diff --git a/so3/arch/arm64/exception.S b/so3/arch/arm64/exception.S
index bde52f61b9..4688b0b6eb 100644
--- a/so3/arch/arm64/exception.S
+++ b/so3/arch/arm64/exception.S
@@ -226,7 +226,7 @@ ENTRY(pre_ret_to_el1_with_spin)
 	// Set the CPU in EL1 mode to proceed with
 	// the bootstrap of the domain
 
-	mov	x2, #PSR_MODE_EL1t
+	mov	x2, #PSR_MODE_EL1h
 
 	// Make sure no interrupt coming from CPU #0 is
 	// interferring with other CPU bootstrap
@@ -271,7 +271,7 @@ ENTRY(pre_ret_to_el1)
 	// Set the CPU in EL1 mode to proceed with
 	// the bootstrap of the domain
 
-	mov	x2, #PSR_MODE_EL1t
+	mov	x2, #PSR_MODE_EL1h
 
 	// Make sure no interrupt coming from CPU #0 is
 	// interferring with other CPU bootstrap
diff --git a/so3/arch/arm64/head.S b/so3/arch/arm64/head.S
index 640803d886..1996af76e4 100644
--- a/so3/arch/arm64/head.S
+++ b/so3/arch/arm64/head.S
@@ -424,7 +424,7 @@ install_el2_stub:
 	msr	vbar_el2, x0
 
 	/* spsr */
-	mov	x0, #(PSR_F_BIT | PSR_I_BIT | PSR_A_BIT | PSR_D_BIT | PSR_MODE_EL1t)
+	mov	x0, #(PSR_F_BIT | PSR_I_BIT | PSR_A_BIT | PSR_D_BIT | PSR_MODE_EL1h)
 	msr	spsr_el2, x0
 	msr	elr_el2, lr
 	mov	w0, #BOOT_CPU_MODE_EL2		// This CPU booted in EL2
diff --git a/so3/arch/arm64/mmu.c b/so3/arch/arm64/mmu.c
index c9cb5161a4..b219a26043 100644
--- a/so3/arch/arm64/mmu.c
+++ b/so3/arch/arm64/mmu.c
@@ -30,6 +30,10 @@
 #include <asm/mmu.h>
 #include <asm/cacheflush.h>
 
+/* We disable these logs here because the UART is difficult to manage during the I/O re-mapping. */
+#undef LOG_DEBUG
+#define LOG_DEBUG(fmt, ...)
+
 void *__current_pgtable = NULL;
 
 void *current_pgtable(void)
@@ -675,8 +679,8 @@ void mmu_configure(addr_t fdt_addr)
 
 		/* Early mapping I/O for UART. Here, the UART is supposed to be in a different L1 entry than the RAM. */
 #ifdef CONFIG_VA_BITS_48
-		__sys_idmap_l1pgtable[l1pte_index(CONFIG_UART_LL_PADDR)] = CONFIG_UART_LL_PADDR & TTB_L1_BLOCK_ADDR_MASK;
-		set_pte_block(&__sys_idmap_l1pgtable[l1pte_index(CONFIG_UART_LL_PADDR)], DCACHE_OFF);
+	__sys_idmap_l1pgtable[l1pte_index(CONFIG_UART_LL_PADDR)] = CONFIG_UART_LL_PADDR & TTB_L1_BLOCK_ADDR_MASK;
+	set_pte_block(&__sys_idmap_l1pgtable[l1pte_index(CONFIG_UART_LL_PADDR)], DCACHE_OFF);
 #elif CONFIG_VA_BITS_39
 	__sys_root_pgtable[l1pte_index(CONFIG_UART_LL_PADDR)] = CONFIG_UART_LL_PADDR & TTB_L1_BLOCK_ADDR_MASK;
 	set_pte_block(&__sys_root_pgtable[l1pte_index(CONFIG_UART_LL_PADDR)], DCACHE_OFF);
diff --git a/so3/arch/arm64/traps.c b/so3/arch/arm64/traps.c
index b94ea34bd6..5501e7de64 100644
--- a/so3/arch/arm64/traps.c
+++ b/so3/arch/arm64/traps.c
@@ -118,6 +118,8 @@ typedef void (*vector_fn_t)(cpu_regs_t *);
 
 void trap_handle(cpu_regs_t *regs)
 {
+	int ret = 0;
+
 #ifndef CONFIG_AVZ
 	syscall_args_t sys_args;
 #endif
@@ -141,7 +143,9 @@ void trap_handle(cpu_regs_t *regs)
 	switch (ESR_ELx_EC(esr)) {
 	case ESR_ELx_EC_DABT_LOW:
 
-		dabt_handle(regs, esr);
+		ret = dabt_handle(regs, esr);
+		if (ret == -1)
+			goto __err;
 		break;
 
 	/* SVC used for syscalls */
@@ -247,6 +251,7 @@ void trap_handle(cpu_regs_t *regs)
 #endif
 
 	default:
+__err:
 		lprintk("### On CPU %d: ESR_Elx_EC(esr): 0x%lx\n", smp_processor_id(), ESR_ELx_EC(esr));
 		trap_handle_error(regs->lr);
 		kernel_panic();
diff --git a/so3/kernel/schedule.c b/so3/kernel/schedule.c
index 6cb12fa2ae..2fb62fc737 100644
--- a/so3/kernel/schedule.c
+++ b/so3/kernel/schedule.c
@@ -444,7 +444,8 @@ void schedule(void)
 		LOG_DEBUG("Now scheduling thread ID: %d name: %s PID: %d prio: %d\n", next->tid, next->name,
 			  ((next->pcb != NULL) ? next->pcb->pid : -1), next->prio);
 		if (prev)
-			LOG_DEBUG("Previous was threadID: %d name: %s PID: %d\n", prev->tid, prev->name);
+			LOG_DEBUG("Previous was threadID: %d name: %s PID: %d\n", prev->tid, prev->name,
+				  (next->pcb != NULL) ? next->pcb->pid : -1);
 
 		/*
 		 * The current threads (here prev) can be in different states, not only running; it may be in *waiting* or *zombie*
diff --git a/so3/mm/memory.c b/so3/mm/memory.c
index 0eae06078f..bd0d103a01 100644
--- a/so3/mm/memory.c
+++ b/so3/mm/memory.c
@@ -54,6 +54,13 @@ static uint32_t kernel_size;
 /* Current available I/O range address */
 struct list_head io_maplist;
 
+/**
+ * @brief This function is called early during the bootstrap by head.S
+ * 	  There is no MMU activated and all adresses are physical.
+ * 	  DO NOT PRINT ANYTHING IN THIS FUNCTION.
+ * 
+ * @param fdt_paddr 
+ */
 void early_memory_init(void *fdt_paddr)
 {
 	int offset;
@@ -65,8 +72,6 @@ void early_memory_init(void *fdt_paddr)
 	__fdt_addr = (void *) __va(fdt_paddr);
 #endif
 
-	if (offset >= 0)
-		LOG_DEBUG("Found %d MB of RAM at 0x%08X", mem_info.size / SZ_1M, mem_info.phys_base);
 }
 
 uint32_t get_kernel_size(void)
diff --git a/usr/lib/libc/exit/exit.c b/usr/lib/libc/exit/exit.c
index 42feb67033..a436c19d3e 100644
--- a/usr/lib/libc/exit/exit.c
+++ b/usr/lib/libc/exit/exit.c
@@ -27,8 +27,16 @@ weak_alias(libc_exit_fini, __libc_exit_fini);
 
 _Noreturn void exit(int code)
 {
+	#warning exit() issue
+	/* 
+	 * Currently, the following code leads to data abort fault randomly. The effect
+	 * is visible on RPi4 (64-bit) more rarely on virt64
+	 */
+#if 0
 	__funcs_on_exit();
-	__libc_exit_fini();
+	__libc_exit_fini();	
 	__stdio_exit();
+#endif /* 0 */
+
 	_Exit(code);
 }