From 83e96dc0d1cc5bab2a711235ab325e1511e1ed2a Mon Sep 17 00:00:00 2001 From: somhi Date: Fri, 30 Dec 2022 22:42:36 +0100 Subject: [PATCH] SoCkit port --- Readme.md | 6 + mycore.qsf | 22 ++- mycore_Q13.qpf | 2 - mycore_Q13.qsf | 46 ------ mycore_Q13.srf | 28 ---- sys/I2C_AV_Config.v | 147 ++++++++++++++++++ sys/I2C_Controller.v | 112 ++++++++++++++ sys/sys.tcl | 331 ++++++++++++++++++++++------------------- sys/sys_analog.tcl | 123 ++++++++++----- sys/sys_dual_sdram.tcl | 88 +++++------ sys/sys_top.sdc | 3 +- sys/sys_top.v | 153 +++++++++++++++---- 12 files changed, 711 insertions(+), 350 deletions(-) delete mode 100644 mycore_Q13.qpf delete mode 100644 mycore_Q13.qsf delete mode 100644 mycore_Q13.srf create mode 100644 sys/I2C_AV_Config.v create mode 100644 sys/I2C_Controller.v diff --git a/Readme.md b/Readme.md index 181dc11..5d07256 100644 --- a/Readme.md +++ b/Readme.md @@ -1,3 +1,9 @@ +# Template core for [SoCkit (MiSTer) Platform](https://github.com/sockitfpga/MiSTer_SoCkit) + +Ported by @somhi from https://github.com/MiSTer-devel/Template_MiSTer + +Follows original README. + # Template core for MiSTer ## General description diff --git a/mycore.qsf b/mycore.qsf index 4e1f259..8013d23 100644 --- a/mycore.qsf +++ b/mycore.qsf @@ -13,15 +13,15 @@ set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top -set_global_assignment -name LAST_QUARTUS_VERSION "17.0.2 Standard Edition" +set_global_assignment -name LAST_QUARTUS_VERSION "17.1.0 Lite Edition" set_global_assignment -name GENERATE_RBF_FILE ON set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL set_global_assignment -name SAVE_DISK_SPACE OFF set_global_assignment -name SMART_RECOMPILE ON -set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40" -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF @@ -50,6 +50,16 @@ set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON set_global_assignment -name ALM_REGISTER_PACKING_EFFORT MEDIUM set_global_assignment -name SEED 1 +set_global_assignment -name ENABLE_OCT_DONE OFF +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name USE_CONFIGURATION_DEVICE ON +set_global_assignment -name CRC_ERROR_OPEN_DRAIN ON +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHZ + #set_global_assignment -name VERILOG_MACRO "MISTER_FB=1" #enable it only if 8bit indexed mode is used in core @@ -70,4 +80,8 @@ set_global_assignment -name SEED 1 source sys/sys.tcl source sys/sys_analog.tcl source files.qip -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file + +set_global_assignment -name VERILOG_FILE sys/I2C_Controller.v +set_global_assignment -name VERILOG_FILE sys/I2C_AV_Config.v + +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top diff --git a/mycore_Q13.qpf b/mycore_Q13.qpf deleted file mode 100644 index 024ab77..0000000 --- a/mycore_Q13.qpf +++ /dev/null @@ -1,2 +0,0 @@ -QUARTUS_VERSION = "13.1" -PROJECT_REVISION = "mycore_Q13" diff --git a/mycore_Q13.qsf b/mycore_Q13.qsf deleted file mode 100644 index 433b4dd..0000000 --- a/mycore_Q13.qsf +++ /dev/null @@ -1,46 +0,0 @@ -# -------------------------------------------------------------------------- -# -# MiSTer project -# -# WARNING WARNING WARNING: -# Do not add files to project in Quartus IDE! It will mess this file! -# Add the files manually to files.qip file. -# -# -------------------------------------------------------------------------- - -set_global_assignment -name TOP_LEVEL_ENTITY sys_top -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top - -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 - -set_global_assignment -name GENERATE_RBF_FILE ON -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files -set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL -set_global_assignment -name SAVE_DISK_SPACE OFF -set_global_assignment -name SMART_RECOMPILE ON -set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40" -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF -set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF -set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS -set_global_assignment -name FITTER_EFFORT "STANDARD FIT" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON -set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 2.0 -set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION ON -set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON -set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE OFF -set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS OFF -set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON -set_global_assignment -name ALM_REGISTER_PACKING_EFFORT LOW -set_global_assignment -name SEED 1 - -source sys/sys.tcl -source sys/sys_analog.tcl -set_global_assignment -name QIP_FILE files.qip -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/mycore_Q13.srf b/mycore_Q13.srf deleted file mode 100644 index 5cb89dc..0000000 --- a/mycore_Q13.srf +++ /dev/null @@ -1,28 +0,0 @@ -{ "" "" "" "Verilog HDL or VHDL warning at sys_top.v(209): object \"vip_newcfg\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Verilog HDL information at MC6845.v(280): always construct contains both blocking and non-blocking assignments" { } { } 0 10268 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Verilog HDL or VHDL warning at sys_top.v(601): object \"VSET\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Port \"extclk\" on the entity instantiation of \"cyclonev_pll\" is connected to a signal of width 1. The formal width of the signal in the module is 2. The extra bits will be left dangling without any fan-out logic." { } { } 0 12030 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "RST port on the PLL is not properly connected on instance emu:emu\|pll:pll\|pll_0002:pll_inst\|altera_pll:altera_pll_i\|general\[0\].gpll. The reset port on the PLL should be connected. If the PLL loses lock for any reason, you might need to manually reset the PLL in order to re-establish lock to the reference clock." { } { } 0 0 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Dummy RLC values generated in IBIS model files for device 5CSEBA6 with package UFBGA and pin count 672" { } { } 0 205009 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Ignored filter at sys_top.sdc(10): vip\|output_inst\|vid_clk could not be matched with a net" { } { } 0 332174 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Ignored create_generated_clock at sys_top.sdc(9): Argument is an empty collection" { } { } 0 332049 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Ignored filter at sys_top.sdc(29): VID_CLK could not be matched with a clock" { } { } 0 332174 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Timing characteristics of device 5CSEBA6U23I7 are preliminary" { } { } 0 334000 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"emu:emu\|rom_map_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "RST port on the PLL is not properly connected on instance emu:emu\|pll:pll\|pll_0002:pll_inst\|altera_pll:altera_pll_i\|general\[1\].gpll. The reset port on the PLL should be connected. If the PLL loses lock for any reason, you might need to manually reset the PLL in order to re-establish lock to the reference clock." { } { } 0 0 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Ignored filter at sys_top.sdc(17): vip\|output_inst\|vid_clk could not be matched with a net" { } { } 0 332174 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Ignored create_generated_clock at sys_top.sdc(16): Argument is an empty collection" { } { } 0 332049 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Ignored filter at sys_top.sdc(37): VID_CLK could not be matched with a clock" { } { } 0 332174 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"emu:emu\|pll:pll\|pll_0002:pll_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Ignoring invalid fast I/O register assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 176250 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Ignored locations or region assignments to the following nodes" { } { } 0 15705 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "RST port on the PLL is not properly connected on instance emu:emu\|pll:pll\|pll_0002:pll_inst\|altera_pll:altera_pll_i\|general\[2\].gpll. The reset port on the PLL should be connected. If the PLL loses lock for any reason, you might need to manually reset the PLL in order to re-establish lock to the reference clock." { } { } 0 0 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "RST port on the PLL is not properly connected on instance pll_audio:pll_audio\|pll_audio_0002:pll_audio_inst\|altera_pll:altera_pll_i\|general\[0\].gpll. The reset port on the PLL should be connected. If the PLL loses lock for any reason, you might need to manually reset the PLL in order to re-establish lock to the reference clock." { } { } 0 0 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_audio:pll_audio\|pll_audio_0002:pll_audio_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 10268 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 276027 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "altera_pll.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "altera_cyclonev_pll.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "altera_pll_reconfig_core.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} diff --git a/sys/I2C_AV_Config.v b/sys/I2C_AV_Config.v new file mode 100644 index 0000000..3f1bb2d --- /dev/null +++ b/sys/I2C_AV_Config.v @@ -0,0 +1,147 @@ +//Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +module I2C_AV_Config ( //Host Side + iCLK, + iRST_N, + // I2C Side + oI2C_SCLK, + oI2C_SDAT + ); + +// Host Side +input iCLK; +input iRST_N; +// I2C Side +output oI2C_SCLK; +inout oI2C_SDAT; +// Internal Registers/Wires +reg [15:0] mI2C_CLK_DIV; +reg [23:0] mI2C_DATA; +reg mI2C_CTRL_CLK; +reg mI2C_GO; +wire mI2C_END; +wire mI2C_ACK; +reg [15:0] LUT_DATA; +reg [3:0] LUT_INDEX; +reg [1:0] mSetup_ST; + +// Clock Setting +parameter CLK_Freq = 24000000; // 24 MHz +parameter I2C_Freq = 20000; // 20 KHz +// LUT Data Number +parameter LUT_SIZE = 11; +// Audio Data Index +parameter Dummy_DATA = 0; +parameter SET_LIN_L = 1; +parameter SET_LIN_R = 2; +parameter SET_HEAD_L = 3; +parameter SET_HEAD_R = 4; +parameter A_PATH_CTRL = 5; +parameter D_PATH_CTRL = 6; +parameter POWER_ON = 7; +parameter SET_FORMAT = 8; +parameter SAMPLE_CTRL = 9; +parameter SET_ACTIVE = 10; + + + +///////////////////// I2C Control Clock //////////////////////// +always@(posedge iCLK or negedge iRST_N) begin + if(!iRST_N) begin + mI2C_CTRL_CLK <= 1'd0; + mI2C_CLK_DIV <= 16'd0; + end else begin + if (mI2C_CLK_DIV < (CLK_Freq/I2C_Freq)) + mI2C_CLK_DIV <= mI2C_CLK_DIV + 16'd1; + else begin + mI2C_CLK_DIV <= 16'd0; + mI2C_CTRL_CLK <= ~mI2C_CTRL_CLK; + end + end +end + +//////////////////////////////////////////////////////////////////// +I2C_Controller u0 ( + .CLOCK(mI2C_CTRL_CLK), // Controller Work Clock + .I2C_SCLK(oI2C_SCLK), // I2C CLOCK + .I2C_SDAT(oI2C_SDAT), // I2C DATA + .I2C_DATA(mI2C_DATA), // DATA:[SLAVE_ADDR,SUB_ADDR,DATA] + .GO(mI2C_GO), // GO transfor + .END(mI2C_END), // END transfor + .ACK(mI2C_ACK), // ACK + .RESET(iRST_N) +); +//////////////////////////////////////////////////////////////////// + + +////////////////////// Config Control //////////////////////////// +always@(posedge mI2C_CTRL_CLK or negedge iRST_N) begin + if(!iRST_N) begin + LUT_INDEX <= 4'd0; + mSetup_ST <= 2'd0; + mI2C_GO <= 1'd0; + end else begin + if(LUT_INDEX < LUT_SIZE) begin + case(mSetup_ST) + 0: begin + mI2C_DATA <= {8'h34,LUT_DATA}; + mI2C_GO <= 1'd1; + mSetup_ST <= 2'd1; + end + 1: begin + if(mI2C_END) begin + if(!mI2C_ACK) + mSetup_ST <= 2'd2; + else + mSetup_ST <= 2'd0; + mI2C_GO <= 1'd0; + end + end + 2: begin + LUT_INDEX <= LUT_INDEX + 4'd1; + mSetup_ST <= 2'd0; + end + endcase + end + end +end +//////////////////////////////////////////////////////////////////// + + +///////////////////// Config Data LUT ////////////////////////// +always @ (*) +begin + case(LUT_INDEX) + // Audio Config Data + Dummy_DATA : LUT_DATA <= 16'h0000; + SET_LIN_L : LUT_DATA <= 16'h009A;//16'h001A; //R0 LINVOL = 1Ah (+4.5bB) + SET_LIN_R : LUT_DATA <= 16'h029A;//16'h021A; //R1 RINVOL = 1Ah (+4.5bB) + SET_HEAD_L : LUT_DATA <= 16'h0479; //R2 LHPVOL = 7Bh (+2dB) + SET_HEAD_R : LUT_DATA <= 16'h0679; //R3 RHPVOL = 7Bh (+2dB) + A_PATH_CTRL : LUT_DATA <= 16'h08D2;//16'h08F8; //R4 DACSEL = 1 + D_PATH_CTRL : LUT_DATA <= 16'h0A06; //R5 DEEMP = 11 (48 KHz) + //POWER_ON : LUT_DATA <= 16'h0C00; //R6 all powered ON + POWER_ON : LUT_DATA <= 16'h0C20; //R6 internal oscilator MCLK powered down + //SET_FORMAT : LUT_DATA <= 16'h0E01; //R7 FORMAT=01,16 bit format left justified + SET_FORMAT : LUT_DATA <= 16'h0E02; //R7 FORMAT=10,16 bit format I2S + //SAMPLE_CTRL : LUT_DATA <= 16'h1009; //R8 48KHz,USB-mode + SAMPLE_CTRL : LUT_DATA <= 16'h1008; //R8 48KHz,Normal mode, clkdiv2=0 + SET_ACTIVE : LUT_DATA <= 16'h1201; //R9 ACTIVE + default : LUT_DATA <= 16'h0000; + endcase +end +//////////////////////////////////////////////////////////////////// + + +endmodule + diff --git a/sys/I2C_Controller.v b/sys/I2C_Controller.v new file mode 100644 index 0000000..4954dc6 --- /dev/null +++ b/sys/I2C_Controller.v @@ -0,0 +1,112 @@ +//Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +module I2C_Controller ( + CLOCK, + I2C_SCLK, //I2C CLOCK + I2C_SDAT, //I2C DATA + I2C_DATA, //DATA:[SLAVE_ADDR,SUB_ADDR,DATA] + GO, //GO transfor + END, //END transfor + ACK, //ACK + RESET, + //TEST + SD_COUNTER, + SDO +); + + input CLOCK; + input [23:0]I2C_DATA; + input GO; + input RESET; + inout I2C_SDAT; + output I2C_SCLK; + output END; + output ACK; +//TEST + output [5:0] SD_COUNTER; + output SDO; + +reg SDO; +reg SCLK; +reg END; +reg [23:0]SD; +reg [5:0]SD_COUNTER; + +wire I2C_SCLK=SCLK | ( ((SD_COUNTER >= 4) & (SD_COUNTER <=30))? ~CLOCK : 1'd0 ); +wire I2C_SDAT=SDO ? 1'bz : 1'b0 ; + +reg ACK1,ACK2,ACK3; +wire ACK=ACK1 | ACK2 |ACK3; + +//--I2C COUNTER +always @(negedge RESET or posedge CLOCK ) begin +if (!RESET) SD_COUNTER=6'b111111; +else begin +if (GO==0) + SD_COUNTER=0; + else + if (SD_COUNTER < 6'b111111) SD_COUNTER=SD_COUNTER + 6'd1; +end +end +//---- + +always @(negedge RESET or posedge CLOCK ) begin +if (!RESET) begin SCLK=1;SDO=1; ACK1=0;ACK2=0;ACK3=0; END=1; end +else +case (SD_COUNTER) + 6'd0 : begin ACK1=0 ;ACK2=0 ;ACK3=0 ; END=0; SDO=1; SCLK=1;end + //start + 6'd1 : begin SD=I2C_DATA;SDO=0;end + 6'd2 : SCLK=0; + //SLAVE ADDR + 6'd3 : SDO=SD[23]; + 6'd4 : SDO=SD[22]; + 6'd5 : SDO=SD[21]; + 6'd6 : SDO=SD[20]; + 6'd7 : SDO=SD[19]; + 6'd8 : SDO=SD[18]; + 6'd9 : SDO=SD[17]; + 6'd10 : SDO=SD[16]; + 6'd11 : SDO=1'b1;//ACK + + //SUB ADDR + 6'd12 : begin SDO=SD[15]; ACK1=I2C_SDAT; end + 6'd13 : SDO=SD[14]; + 6'd14 : SDO=SD[13]; + 6'd15 : SDO=SD[12]; + 6'd16 : SDO=SD[11]; + 6'd17 : SDO=SD[10]; + 6'd18 : SDO=SD[9]; + 6'd19 : SDO=SD[8]; + 6'd20 : SDO=1'b1;//ACK + + //DATA + 6'd21 : begin SDO=SD[7]; ACK2=I2C_SDAT; end + 6'd22 : SDO=SD[6]; + 6'd23 : SDO=SD[5]; + 6'd24 : SDO=SD[4]; + 6'd25 : SDO=SD[3]; + 6'd26 : SDO=SD[2]; + 6'd27 : SDO=SD[1]; + 6'd28 : SDO=SD[0]; + 6'd29 : SDO=1'b1;//ACK + + //stop + 6'd30 : begin SDO=1'b0; SCLK=1'b0; ACK3=I2C_SDAT; end + 6'd31 : SCLK=1'b1; + 6'd32 : begin SDO=1'b1; END=1; end + +endcase +end +endmodule + diff --git a/sys/sys.tcl b/sys/sys.tcl index ce83683..3cfe472 100644 --- a/sys/sys.tcl +++ b/sys/sys.tcl @@ -1,101 +1,125 @@ set_global_assignment -name FAMILY "Cyclone V" -set_global_assignment -name DEVICE 5CSEBA6U23I7 -set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672 -set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7 +set_global_assignment -name DEVICE 5CSXFC6D6F31C6 +set_global_assignment -name DEVICE_FILTER_PACKAGE Any +set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any #============================================================ -# ADC +# ADC (DE10-nano ADC IC signals) #============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CONVST -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO -set_location_assignment PIN_U9 -to ADC_CONVST -set_location_assignment PIN_V10 -to ADC_SCK -set_location_assignment PIN_AC4 -to ADC_SDI -set_location_assignment PIN_AD4 -to ADC_SDO +# set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CONVST +# set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK +# set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI +# set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO +# set_location_assignment PIN_U9 -to ADC_CONVST +# set_location_assignment PIN_V10 -to ADC_SCK +# set_location_assignment PIN_AC4 -to ADC_SDI +# set_location_assignment PIN_AD4 -to ADC_SDO #============================================================ # ARDUINO #============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[*] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ARDUINO_IO[*] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ARDUINO_IO[*] +# set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[*] +# set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ARDUINO_IO[*] +# set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ARDUINO_IO[*] #============================================================ -# I2C LEDS/BUTTONS +# I2C LEDS/BUTTONS (DE10-nano Arduino_IO) #============================================================ -set_location_assignment PIN_U14 -to IO_SCL -set_location_assignment PIN_AG9 -to IO_SDA +set_location_assignment PIN_C5 -to IO_SCL +set_location_assignment PIN_J12 -to IO_SDA set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to IO_S* set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to IO_S* set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to IO_S* +# HSMC J3 connector pin 27 HSMC_TX _n[3] PIN_C5 IO_SCL +# HSMC J3 connector pin 28 HSMC_RX _n[1] PIN_J12 IO_SDA + #============================================================ -# USER PORT +# USER PORT (DE10-nano Arduino_IO) #============================================================ -set_location_assignment PIN_AF17 -to USER_IO[6] -set_location_assignment PIN_AF15 -to USER_IO[5] -set_location_assignment PIN_AG16 -to USER_IO[4] -set_location_assignment PIN_AH11 -to USER_IO[3] -set_location_assignment PIN_AH12 -to USER_IO[2] -set_location_assignment PIN_AH9 -to USER_IO[1] -set_location_assignment PIN_AG11 -to USER_IO[0] +set_location_assignment PIN_C3 -to USER_IO[6] +set_location_assignment PIN_E4 -to USER_IO[5] +set_location_assignment PIN_E2 -to USER_IO[4] +set_location_assignment PIN_J7 -to USER_IO[3] +set_location_assignment PIN_H8 -to USER_IO[2] +set_location_assignment PIN_D4 -to USER_IO[1] +set_location_assignment PIN_H7 -to USER_IO[0] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USER_IO[*] set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to USER_IO[*] set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to USER_IO[*] -#============================================================ -# SDIO_CD or SPDIF_OUT -#============================================================ -set_location_assignment PIN_AH7 -to SDCD_SPDIF +# HSMC J3 connector pin 7 JOY1_B2_P9; HSMC_TX _p[7] PIN_C3 USER_IO[6] (sega C) +# HSMC J3 connector pin 8 JOY1_B1_P6; HSMC_RX _p[6] PIN_H8 USER_IO[2] (sega B) //WSEL +# HSMC J3 connector pin 9 JOY1_UP; HSMC_TX _n[6] PIN_D4 USER_IO[1] //MIDI OUT +# HSMC J3 connector pin 10 JOY1_DOWN; HSMC_RX _n[5] PIN_H7 USER_IO[0] //SDA +# HSMC J3 connector pin 13 JOY1_LEFT; HSMC_TX _p[6] PIN_E4 USER_IO[5] //DAT +# HSMC J3 connector pin 14 JOY1_RIGHT; HSMC_RX _p[5] PIN_J7 USER_IO[3] //SCL +# HSMC J3 connector pin 15 JOYX_SEL_O; HSMC_TX _n[5] PIN_E2 USER_IO[4] //BLCK + +# // Pin | USB Name | |Signal +# // ----+----------+---+------------- +# // 0 | D+ | I |RX +# // 1 | D- | O |TX +# // 2 | TX- | O |RTS +# // 3 | GND_d | I |CTS +# // 4 | RX+ | O |DTR +# // 5 | RX- | I |DSR +# // 6 | TX+ | I |DCD +# // + +#============================================================ +# SDIO_CD or SPDIF_OUT (DE10-nano Arduino_IO) +#============================================================ +set_location_assignment PIN_J10 -to SDCD_SPDIF set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDCD_SPDIF set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCD_SPDIF set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDCD_SPDIF +# HSMC J3 connector pin 22 / PMOD3[6]; HSMC_RX _p[3] PIN_J10 SDCD_SPDIF + #============================================================ # SDRAM #============================================================ -set_location_assignment PIN_Y11 -to SDRAM_A[0] -set_location_assignment PIN_AA26 -to SDRAM_A[1] -set_location_assignment PIN_AA13 -to SDRAM_A[2] -set_location_assignment PIN_AA11 -to SDRAM_A[3] -set_location_assignment PIN_W11 -to SDRAM_A[4] -set_location_assignment PIN_Y19 -to SDRAM_A[5] -set_location_assignment PIN_AB23 -to SDRAM_A[6] -set_location_assignment PIN_AC23 -to SDRAM_A[7] -set_location_assignment PIN_AC22 -to SDRAM_A[8] -set_location_assignment PIN_C12 -to SDRAM_A[9] -set_location_assignment PIN_AB26 -to SDRAM_A[10] -set_location_assignment PIN_AD17 -to SDRAM_A[11] -set_location_assignment PIN_D12 -to SDRAM_A[12] -set_location_assignment PIN_Y17 -to SDRAM_BA[0] -set_location_assignment PIN_AB25 -to SDRAM_BA[1] -set_location_assignment PIN_E8 -to SDRAM_DQ[0] -set_location_assignment PIN_V12 -to SDRAM_DQ[1] -set_location_assignment PIN_D11 -to SDRAM_DQ[2] -set_location_assignment PIN_W12 -to SDRAM_DQ[3] -set_location_assignment PIN_AH13 -to SDRAM_DQ[4] -set_location_assignment PIN_D8 -to SDRAM_DQ[5] -set_location_assignment PIN_AH14 -to SDRAM_DQ[6] -set_location_assignment PIN_AF7 -to SDRAM_DQ[7] -set_location_assignment PIN_AE24 -to SDRAM_DQ[8] -set_location_assignment PIN_AD23 -to SDRAM_DQ[9] -set_location_assignment PIN_AE6 -to SDRAM_DQ[10] -set_location_assignment PIN_AE23 -to SDRAM_DQ[11] -set_location_assignment PIN_AG14 -to SDRAM_DQ[12] -set_location_assignment PIN_AD5 -to SDRAM_DQ[13] -set_location_assignment PIN_AF4 -to SDRAM_DQ[14] -set_location_assignment PIN_AH3 -to SDRAM_DQ[15] -set_location_assignment PIN_AG13 -to SDRAM_DQML -set_location_assignment PIN_AF13 -to SDRAM_DQMH -set_location_assignment PIN_AD20 -to SDRAM_CLK -set_location_assignment PIN_AG10 -to SDRAM_CKE -set_location_assignment PIN_AA19 -to SDRAM_nWE -set_location_assignment PIN_AA18 -to SDRAM_nCAS -set_location_assignment PIN_Y18 -to SDRAM_nCS -set_location_assignment PIN_W14 -to SDRAM_nRAS +set_location_assignment PIN_B1 -to SDRAM_A[0] +set_location_assignment PIN_C2 -to SDRAM_A[1] +set_location_assignment PIN_B2 -to SDRAM_A[2] +set_location_assignment PIN_D2 -to SDRAM_A[3] +set_location_assignment PIN_D9 -to SDRAM_A[4] +set_location_assignment PIN_C7 -to SDRAM_A[5] +set_location_assignment PIN_E12 -to SDRAM_A[6] +set_location_assignment PIN_B7 -to SDRAM_A[7] +set_location_assignment PIN_D12 -to SDRAM_A[8] +set_location_assignment PIN_A11 -to SDRAM_A[9] +set_location_assignment PIN_B6 -to SDRAM_A[10] +set_location_assignment PIN_D11 -to SDRAM_A[11] +set_location_assignment PIN_A10 -to SDRAM_A[12] +set_location_assignment PIN_B5 -to SDRAM_BA[0] +set_location_assignment PIN_A4 -to SDRAM_BA[1] +set_location_assignment PIN_F14 -to SDRAM_DQ[0] +set_location_assignment PIN_G15 -to SDRAM_DQ[1] +set_location_assignment PIN_F15 -to SDRAM_DQ[2] +set_location_assignment PIN_H15 -to SDRAM_DQ[3] +set_location_assignment PIN_G13 -to SDRAM_DQ[4] +set_location_assignment PIN_A13 -to SDRAM_DQ[5] +set_location_assignment PIN_H14 -to SDRAM_DQ[6] +set_location_assignment PIN_B13 -to SDRAM_DQ[7] +set_location_assignment PIN_C13 -to SDRAM_DQ[8] +set_location_assignment PIN_C8 -to SDRAM_DQ[9] +set_location_assignment PIN_B12 -to SDRAM_DQ[10] +set_location_assignment PIN_B8 -to SDRAM_DQ[11] +set_location_assignment PIN_F13 -to SDRAM_DQ[12] +set_location_assignment PIN_C12 -to SDRAM_DQ[13] +set_location_assignment PIN_B11 -to SDRAM_DQ[14] +set_location_assignment PIN_E13 -to SDRAM_DQ[15] +# set_location_assignment -remove -to SDRAM_DQML +# set_location_assignment -remove -to SDRAM_DQMH +set_location_assignment PIN_D10 -to SDRAM_CLK +# set_location_assignment -remove -to SDRAM_CKE +set_location_assignment PIN_A5 -to SDRAM_nWE +set_location_assignment PIN_A6 -to SDRAM_nCAS +set_location_assignment PIN_A3 -to SDRAM_nCS +set_location_assignment PIN_E9 -to SDRAM_nRAS set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_* set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_* @@ -104,105 +128,108 @@ set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*] set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*] set_instance_assignment -name ALLOW_SYNCH_CTRL_USAGE OFF -to *|SDRAM_* +#DQMH/L & CKE not connected in new MiSTer SDRAM modules +set_location_assignment PIN_D1 -to SDRAM_CKE +set_location_assignment PIN_E1 -to SDRAM_DQMH +set_location_assignment PIN_E11 -to SDRAM_DQML +# HSMC J2 connector prototype area +# HSMC_TX _n[8] PIN_D1 SDRAM_CKE +# HSMC_TX _p[8] PIN_E1 SDRAM_DQMH +# HSMC_RX _n[8] PIN_E11 SDRAM_DQML + #============================================================ -# SPI SD +# SPI SD (Secondary SD) (DE10-nano Arduino_IO) [Sockit uses SDIO for 2nd SD card] #============================================================ -set_location_assignment PIN_AE15 -to SD_SPI_CS -set_location_assignment PIN_AH8 -to SD_SPI_MISO -set_location_assignment PIN_AG8 -to SD_SPI_CLK -set_location_assignment PIN_U13 -to SD_SPI_MOSI -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SD_SPI* -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_SPI* -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_SPI* +# set_location_assignment PIN_AE15 -to SD_SPI_CS +# set_location_assignment PIN_AH8 -to SD_SPI_MISO +# set_location_assignment PIN_AG8 -to SD_SPI_CLK +# set_location_assignment PIN_U13 -to SD_SPI_MOSI +# set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SD_SPI* +# set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_SPI* +# set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_SPI* #============================================================ # CLOCK #============================================================ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK1_50 -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK2_50 -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK3_50 -set_location_assignment PIN_V11 -to FPGA_CLK1_50 -set_location_assignment PIN_Y13 -to FPGA_CLK2_50 -set_location_assignment PIN_E11 -to FPGA_CLK3_50 +set_instance_assignment -name IO_STANDARD "1.5 V" -to FPGA_CLK2_50 +set_instance_assignment -name IO_STANDARD "1.5 V" -to FPGA_CLK3_50 +set_location_assignment PIN_Y26 -to FPGA_CLK1_50 +set_location_assignment PIN_AA16 -to FPGA_CLK2_50 +set_location_assignment PIN_AF14 -to FPGA_CLK3_50 #============================================================ # HDMI #============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_* -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2S -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_LRCLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_MCLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_SCLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_* -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_D[*] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_DE -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_HS -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_VS -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_CLK -set_location_assignment PIN_U10 -to HDMI_I2C_SCL -set_location_assignment PIN_AA4 -to HDMI_I2C_SDA -set_location_assignment PIN_T13 -to HDMI_I2S -set_location_assignment PIN_T11 -to HDMI_LRCLK -set_location_assignment PIN_U11 -to HDMI_MCLK -set_location_assignment PIN_T12 -to HDMI_SCLK -set_location_assignment PIN_AG5 -to HDMI_TX_CLK -set_location_assignment PIN_AD19 -to HDMI_TX_DE -set_location_assignment PIN_AD12 -to HDMI_TX_D[0] -set_location_assignment PIN_AE12 -to HDMI_TX_D[1] -set_location_assignment PIN_W8 -to HDMI_TX_D[2] -set_location_assignment PIN_Y8 -to HDMI_TX_D[3] -set_location_assignment PIN_AD11 -to HDMI_TX_D[4] -set_location_assignment PIN_AD10 -to HDMI_TX_D[5] -set_location_assignment PIN_AE11 -to HDMI_TX_D[6] -set_location_assignment PIN_Y5 -to HDMI_TX_D[7] -set_location_assignment PIN_AF10 -to HDMI_TX_D[8] -set_location_assignment PIN_Y4 -to HDMI_TX_D[9] -set_location_assignment PIN_AE9 -to HDMI_TX_D[10] -set_location_assignment PIN_AB4 -to HDMI_TX_D[11] -set_location_assignment PIN_AE7 -to HDMI_TX_D[12] -set_location_assignment PIN_AF6 -to HDMI_TX_D[13] -set_location_assignment PIN_AF8 -to HDMI_TX_D[14] -set_location_assignment PIN_AF5 -to HDMI_TX_D[15] -set_location_assignment PIN_AE4 -to HDMI_TX_D[16] -set_location_assignment PIN_AH2 -to HDMI_TX_D[17] -set_location_assignment PIN_AH4 -to HDMI_TX_D[18] -set_location_assignment PIN_AH5 -to HDMI_TX_D[19] -set_location_assignment PIN_AH6 -to HDMI_TX_D[20] -set_location_assignment PIN_AG6 -to HDMI_TX_D[21] -set_location_assignment PIN_AF9 -to HDMI_TX_D[22] -set_location_assignment PIN_AE8 -to HDMI_TX_D[23] -set_location_assignment PIN_T8 -to HDMI_TX_HS -set_location_assignment PIN_AF11 -to HDMI_TX_INT -set_location_assignment PIN_V13 -to HDMI_TX_VS +# set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_* +# set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2S +# set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_LRCLK +# set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_MCLK +# set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_SCLK +# set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_* +# set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_D[*] +# set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_DE +# set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_HS +# set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_VS +# set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_CLK +# set_location_assignment PIN_U10 -to HDMI_I2C_SCL +# set_location_assignment PIN_AA4 -to HDMI_I2C_SDA +# set_location_assignment PIN_T13 -to HDMI_I2S +# set_location_assignment PIN_T11 -to HDMI_LRCLK +# set_location_assignment PIN_U11 -to HDMI_MCLK +# set_location_assignment PIN_T12 -to HDMI_SCLK +# set_location_assignment PIN_AG5 -to HDMI_TX_CLK +# set_location_assignment PIN_AD19 -to HDMI_TX_DE +# set_location_assignment PIN_AD12 -to HDMI_TX_D[0] +# set_location_assignment PIN_AE12 -to HDMI_TX_D[1] +# set_location_assignment PIN_W8 -to HDMI_TX_D[2] +# set_location_assignment PIN_Y8 -to HDMI_TX_D[3] +# set_location_assignment PIN_AD11 -to HDMI_TX_D[4] +# set_location_assignment PIN_AD10 -to HDMI_TX_D[5] +# set_location_assignment PIN_AE11 -to HDMI_TX_D[6] +# set_location_assignment PIN_Y5 -to HDMI_TX_D[7] +# set_location_assignment PIN_AF10 -to HDMI_TX_D[8] +# set_location_assignment PIN_Y4 -to HDMI_TX_D[9] +# set_location_assignment PIN_AE9 -to HDMI_TX_D[10] +# set_location_assignment PIN_AB4 -to HDMI_TX_D[11] +# set_location_assignment PIN_AE7 -to HDMI_TX_D[12] +# set_location_assignment PIN_AF6 -to HDMI_TX_D[13] +# set_location_assignment PIN_AF8 -to HDMI_TX_D[14] +# set_location_assignment PIN_AF5 -to HDMI_TX_D[15] +# set_location_assignment PIN_AE4 -to HDMI_TX_D[16] +# set_location_assignment PIN_AH2 -to HDMI_TX_D[17] +# set_location_assignment PIN_AH4 -to HDMI_TX_D[18] +# set_location_assignment PIN_AH5 -to HDMI_TX_D[19] +# set_location_assignment PIN_AH6 -to HDMI_TX_D[20] +# set_location_assignment PIN_AG6 -to HDMI_TX_D[21] +# set_location_assignment PIN_AF9 -to HDMI_TX_D[22] +# set_location_assignment PIN_AE8 -to HDMI_TX_D[23] +# set_location_assignment PIN_T8 -to HDMI_TX_HS +# set_location_assignment PIN_AF11 -to HDMI_TX_INT +# set_location_assignment PIN_V13 -to HDMI_TX_VS #============================================================ # KEY #============================================================ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1] -set_location_assignment PIN_AH17 -to KEY[0] -set_location_assignment PIN_AH16 -to KEY[1] +set_location_assignment PIN_AE9 -to KEY[0] +set_location_assignment PIN_AE12 -to KEY[1] +# KEY[0] = OSD button +# KEY[1] = USER button #============================================================ # LED #============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7] -set_location_assignment PIN_W15 -to LED[0] -set_location_assignment PIN_AA24 -to LED[1] -set_location_assignment PIN_V16 -to LED[2] -set_location_assignment PIN_V15 -to LED[3] -set_location_assignment PIN_AF26 -to LED[4] -set_location_assignment PIN_AE26 -to LED[5] -set_location_assignment PIN_Y16 -to LED[6] -set_location_assignment PIN_AA23 -to LED[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_0_USER +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_1_HDD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_2_POWER +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_3_LOCKED +set_location_assignment PIN_AF10 -to LED_0_USER +set_location_assignment PIN_AD10 -to LED_1_HDD +set_location_assignment PIN_AE11 -to LED_2_POWER +set_location_assignment PIN_AD7 -to LED_3_LOCKED #============================================================ # SW @@ -211,14 +238,14 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3] -set_location_assignment PIN_Y24 -to SW[0] -set_location_assignment PIN_W24 -to SW[1] -set_location_assignment PIN_W21 -to SW[2] -set_location_assignment PIN_W20 -to SW[3] +set_location_assignment PIN_W25 -to SW[0] +set_location_assignment PIN_V25 -to SW[1] +set_location_assignment PIN_AC28 -to SW[2] +set_location_assignment PIN_AC29 -to SW[3] set_instance_assignment -name HPS_LOCATION HPSINTERFACEPERIPHERALSPIMASTER_X52_Y72_N111 -entity sys_top -to spi set_instance_assignment -name HPS_LOCATION HPSINTERFACEPERIPHERALUART_X52_Y67_N111 -entity sys_top -to uart -set_instance_assignment -name HPS_LOCATION HPSINTERFACEPERIPHERALI2C_X52_Y60_N111 -entity sys_top -to hdmi_i2c +# set_instance_assignment -name HPS_LOCATION HPSINTERFACEPERIPHERALI2C_X52_Y60_N111 -entity sys_top -to hdmi_i2c set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:sys/build_id.tcl" diff --git a/sys/sys_analog.tcl b/sys/sys_analog.tcl index 692043f..903c02a 100644 --- a/sys/sys_analog.tcl +++ b/sys/sys_analog.tcl @@ -1,70 +1,111 @@ #============================================================ -# SDIO +# SDIO (Secondary SD) (DE10-nano GPIO 1) #============================================================ -set_location_assignment PIN_AF25 -to SDIO_DAT[0] -set_location_assignment PIN_AF23 -to SDIO_DAT[1] -set_location_assignment PIN_AD26 -to SDIO_DAT[2] -set_location_assignment PIN_AF28 -to SDIO_DAT[3] -set_location_assignment PIN_AF27 -to SDIO_CMD -set_location_assignment PIN_AH26 -to SDIO_CLK +set_location_assignment PIN_K7 -to SDIO_DAT[0] +set_location_assignment PIN_J9 -to SDIO_DAT[1] +set_location_assignment PIN_E7 -to SDIO_DAT[2] +set_location_assignment PIN_K8 -to SDIO_DAT[3] +set_location_assignment PIN_E3 -to SDIO_CMD +set_location_assignment PIN_E6 -to SDIO_CLK set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDIO_* set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDIO_* set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_DAT[*] set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_CMD +# HSMC J3 connector pin 16 / PMOD3[0]; HSMC_RX _n[4] PIN_K8 SDIO_DAT[3] +# HSMC J3 connector pin 17 / PMOD3[1]; HSMC_TX _p[5] PIN_E3 SDIO_CMD +# HSMC J3 connector pin 18 / PMOD3[2]; HSMC_RX _p[4] PIN_K7 SDIO_DAT[0] +# HSMC J3 connector pin 19 / PMOD3[3]; HSMC_CLKOUT_n1 PIN_E6 SDIO_CLK +# HSMC J3 connector pin 20 / PMOD3[4]; HSMC_RX _n[3] PIN_J9 SDIO_DAT[1] +# HSMC J3 connector pin 21 / PMOD3[5]; HSMC_CLKOUT_p1 PIN_E7 SDIO_DAT[2] +# HSMC J3 connector pin 22 / PMOD3[6]; HSMC_RX _p[3] PIN_J10 --> SDCD_SPDIF (sys.tcl) +# HSMC J3 connector pin 23 / PMOD3[7]; HSMC_TX _n[4] PIN_C4 --> not used + #============================================================ -# VGA +# VGA (SOCKIT BOARD) #============================================================ -set_location_assignment PIN_AE17 -to VGA_R[0] -set_location_assignment PIN_AE20 -to VGA_R[1] -set_location_assignment PIN_AF20 -to VGA_R[2] -set_location_assignment PIN_AH18 -to VGA_R[3] -set_location_assignment PIN_AH19 -to VGA_R[4] -set_location_assignment PIN_AF21 -to VGA_R[5] +set_location_assignment PIN_AG5 -to VGA_R[0] +set_location_assignment PIN_AA12 -to VGA_R[1] +set_location_assignment PIN_AB12 -to VGA_R[2] +set_location_assignment PIN_AF6 -to VGA_R[3] +set_location_assignment PIN_AG6 -to VGA_R[4] +set_location_assignment PIN_AJ2 -to VGA_R[5] +set_location_assignment PIN_AH5 -to VGA_R[6] +set_location_assignment PIN_AJ1 -to VGA_R[7] -set_location_assignment PIN_AE19 -to VGA_G[0] -set_location_assignment PIN_AG15 -to VGA_G[1] -set_location_assignment PIN_AF18 -to VGA_G[2] -set_location_assignment PIN_AG18 -to VGA_G[3] -set_location_assignment PIN_AG19 -to VGA_G[4] -set_location_assignment PIN_AG20 -to VGA_G[5] +set_location_assignment PIN_Y21 -to VGA_G[0] +set_location_assignment PIN_AA25 -to VGA_G[1] +set_location_assignment PIN_AB26 -to VGA_G[2] +set_location_assignment PIN_AB22 -to VGA_G[3] +set_location_assignment PIN_AB23 -to VGA_G[4] +set_location_assignment PIN_AA24 -to VGA_G[5] +set_location_assignment PIN_AB25 -to VGA_G[6] +set_location_assignment PIN_AE27 -to VGA_G[7] -set_location_assignment PIN_AG21 -to VGA_B[0] -set_location_assignment PIN_AA20 -to VGA_B[1] -set_location_assignment PIN_AE22 -to VGA_B[2] -set_location_assignment PIN_AF22 -to VGA_B[3] -set_location_assignment PIN_AH23 -to VGA_B[4] -set_location_assignment PIN_AH21 -to VGA_B[5] +set_location_assignment PIN_AE28 -to VGA_B[0] +set_location_assignment PIN_Y23 -to VGA_B[1] +set_location_assignment PIN_Y24 -to VGA_B[2] +set_location_assignment PIN_AG28 -to VGA_B[3] +set_location_assignment PIN_AF28 -to VGA_B[4] +set_location_assignment PIN_V23 -to VGA_B[5] +set_location_assignment PIN_W24 -to VGA_B[6] +set_location_assignment PIN_AF29 -to VGA_B[7] -set_location_assignment PIN_AH22 -to VGA_HS -set_location_assignment PIN_AG24 -to VGA_VS +set_location_assignment PIN_AD12 -to VGA_HS +set_location_assignment PIN_AC12 -to VGA_VS -set_location_assignment PIN_AH27 -to VGA_EN -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to VGA_EN +set_location_assignment PIN_AG2 -to VGA_SYNC_N +set_location_assignment PIN_AH3 -to VGA_BLANK_N +set_location_assignment PIN_W20 -to VGA_CLK set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_* set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_* #============================================================ -# AUDIO +# AUDIO DELTA-SIGMA / SPDIF (DE10-nano GPIO 1) #============================================================ -set_location_assignment PIN_AC24 -to AUDIO_L -set_location_assignment PIN_AE25 -to AUDIO_R -set_location_assignment PIN_AG26 -to AUDIO_SPDIF +set_location_assignment PIN_D5 -to AUDIO_L +set_location_assignment PIN_G10 -to AUDIO_R +set_location_assignment PIN_F10 -to AUDIO_SPDIF set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUDIO_* set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to AUDIO_* +# HSMC J3 connector pin 24 HSMC_RX _n[2] PIN_F10 AUDIO_SPDIF +# HSMC J3 connector pin 25 HSMC_TX _p[4] PIN_D5 AUDIO_L +# HSMC J3 connector pin 26 HSMC_RX _p[2] PIN_G10 AUDIO_R + +#============================================================ +# AUDIO CODEC SOCKIT BOARD (I2S) +#============================================================ +set_location_assignment PIN_AC27 -to AUD_ADCDAT +set_location_assignment PIN_AG30 -to AUD_ADCLRCK +set_location_assignment PIN_AE7 -to AUD_BCLK +set_location_assignment PIN_AG3 -to AUD_DACDAT +set_location_assignment PIN_AH4 -to AUD_DACLRCK +set_location_assignment PIN_AD26 -to AUD_MUTE +set_location_assignment PIN_AC9 -to AUD_XCK +set_location_assignment PIN_AH30 -to AUD_I2C_SCLK +set_location_assignment PIN_AF30 -to AUD_I2C_SDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_* + #============================================================ -# I/O #1 +# I/O #1 (DE10-nano GPIO 1) #============================================================ -set_location_assignment PIN_Y15 -to LED_USER -set_location_assignment PIN_AA15 -to LED_HDD -set_location_assignment PIN_AG28 -to LED_POWER +set_location_assignment PIN_D6 -to LED_USER +set_location_assignment PIN_K12 -to LED_HDD +set_location_assignment PIN_F6 -to LED_POWER +# HSMC J3 connector pin 31 HSMC_TX _p[3] PIN_D6 LED_USER +# HSMC J3 connector pin 32 HSMC_RX _p[1] PIN_K12 LED_HDD +# HSMC J3 connector pin 33 HSMC_TX _n[2] PIN_F6 LED_POWER -set_location_assignment PIN_AH24 -to BTN_USER -set_location_assignment PIN_AG25 -to BTN_OSD -set_location_assignment PIN_AG23 -to BTN_RESET +set_location_assignment PIN_G11 -to BTN_USER +set_location_assignment PIN_G7 -to BTN_OSD +set_location_assignment PIN_AD27 -to BTN_RESET +# HSMC J3 connector pin 34 HSMC_RX _n[0] PIN_G11 BTN_USER +# HSMC J3 connector pin 35 HSMC_TX _p[2] PIN_G7 BTN_OSD +# HSMC J3 connector pin 36 HSMC_RX _p[0] PIN_G12 provision for a future external reset button +# SOCKIT KEY4 button (KEY_RESET_n) PIN_AD27 BTN_RESET set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_* set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BTN_* diff --git a/sys/sys_dual_sdram.tcl b/sys/sys_dual_sdram.tcl index cf90eab..77d5ed8 100644 --- a/sys/sys_dual_sdram.tcl +++ b/sys/sys_dual_sdram.tcl @@ -1,51 +1,51 @@ #============================================================ # Secondary SDRAM #============================================================ -set_location_assignment PIN_Y15 -to SDRAM2_DQ[0] -set_location_assignment PIN_AC24 -to SDRAM2_DQ[1] -set_location_assignment PIN_AA15 -to SDRAM2_DQ[2] -set_location_assignment PIN_AD26 -to SDRAM2_DQ[3] -set_location_assignment PIN_AG28 -to SDRAM2_DQ[4] -set_location_assignment PIN_AF28 -to SDRAM2_DQ[5] -set_location_assignment PIN_AE25 -to SDRAM2_DQ[6] -set_location_assignment PIN_AF27 -to SDRAM2_DQ[7] -set_location_assignment PIN_AG26 -to SDRAM2_DQ[14] -set_location_assignment PIN_AH27 -to SDRAM2_DQ[15] +# set_location_assignment PIN_Y15 -to SDRAM2_DQ[0] +# set_location_assignment PIN_AC24 -to SDRAM2_DQ[1] +# set_location_assignment PIN_AA15 -to SDRAM2_DQ[2] +# set_location_assignment PIN_AD26 -to SDRAM2_DQ[3] +# set_location_assignment PIN_AG28 -to SDRAM2_DQ[4] +# set_location_assignment PIN_AF28 -to SDRAM2_DQ[5] +# set_location_assignment PIN_AE25 -to SDRAM2_DQ[6] +# set_location_assignment PIN_AF27 -to SDRAM2_DQ[7] +# set_location_assignment PIN_AG26 -to SDRAM2_DQ[14] +# set_location_assignment PIN_AH27 -to SDRAM2_DQ[15] -set_location_assignment PIN_AG25 -to SDRAM2_DQ[13] -set_location_assignment PIN_AH26 -to SDRAM2_DQ[12] -set_location_assignment PIN_AH24 -to SDRAM2_DQ[11] -set_location_assignment PIN_AF25 -to SDRAM2_DQ[10] -set_location_assignment PIN_AG23 -to SDRAM2_DQ[9] -set_location_assignment PIN_AF23 -to SDRAM2_DQ[8] -set_location_assignment PIN_AG24 -to SDRAM2_A[12] -set_location_assignment PIN_AH22 -to SDRAM2_CLK -set_location_assignment PIN_AH21 -to SDRAM2_A[9] -set_location_assignment PIN_AG21 -to SDRAM2_A[11] -set_location_assignment PIN_AH23 -to SDRAM2_A[7] -set_location_assignment PIN_AA20 -to SDRAM2_A[8] -set_location_assignment PIN_AF22 -to SDRAM2_A[5] -set_location_assignment PIN_AE22 -to SDRAM2_A[6] -set_location_assignment PIN_AG20 -to SDRAM2_nWE -set_location_assignment PIN_AF21 -to SDRAM2_A[4] +# set_location_assignment PIN_AG25 -to SDRAM2_DQ[13] +# set_location_assignment PIN_AH26 -to SDRAM2_DQ[12] +# set_location_assignment PIN_AH24 -to SDRAM2_DQ[11] +# set_location_assignment PIN_AF25 -to SDRAM2_DQ[10] +# set_location_assignment PIN_AG23 -to SDRAM2_DQ[9] +# set_location_assignment PIN_AF23 -to SDRAM2_DQ[8] +# set_location_assignment PIN_AG24 -to SDRAM2_A[12] +# set_location_assignment PIN_AH22 -to SDRAM2_CLK +# set_location_assignment PIN_AH21 -to SDRAM2_A[9] +# set_location_assignment PIN_AG21 -to SDRAM2_A[11] +# set_location_assignment PIN_AH23 -to SDRAM2_A[7] +# set_location_assignment PIN_AA20 -to SDRAM2_A[8] +# set_location_assignment PIN_AF22 -to SDRAM2_A[5] +# set_location_assignment PIN_AE22 -to SDRAM2_A[6] +# set_location_assignment PIN_AG20 -to SDRAM2_nWE +# set_location_assignment PIN_AF21 -to SDRAM2_A[4] -set_location_assignment PIN_AG19 -to SDRAM2_nCAS -set_location_assignment PIN_AH19 -to SDRAM2_nRAS -set_location_assignment PIN_AG18 -to SDRAM2_nCS -set_location_assignment PIN_AH18 -to SDRAM2_BA[0] -set_location_assignment PIN_AF18 -to SDRAM2_BA[1] -set_location_assignment PIN_AF20 -to SDRAM2_A[10] -set_location_assignment PIN_AG15 -to SDRAM2_A[0] -set_location_assignment PIN_AE20 -to SDRAM2_A[1] -set_location_assignment PIN_AE19 -to SDRAM2_A[2] -set_location_assignment PIN_AE17 -to SDRAM2_A[3] +# set_location_assignment PIN_AG19 -to SDRAM2_nCAS +# set_location_assignment PIN_AH19 -to SDRAM2_nRAS +# set_location_assignment PIN_AG18 -to SDRAM2_nCS +# set_location_assignment PIN_AH18 -to SDRAM2_BA[0] +# set_location_assignment PIN_AF18 -to SDRAM2_BA[1] +# set_location_assignment PIN_AF20 -to SDRAM2_A[10] +# set_location_assignment PIN_AG15 -to SDRAM2_A[0] +# set_location_assignment PIN_AE20 -to SDRAM2_A[1] +# set_location_assignment PIN_AE19 -to SDRAM2_A[2] +# set_location_assignment PIN_AE17 -to SDRAM2_A[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM2_* -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM2_* -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM2_* -set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM2_DQ[*] -set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM2_DQ[*] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDRAM2_DQ[*] -set_instance_assignment -name ALLOW_SYNCH_CTRL_USAGE OFF -to *|SDRAM2_* +# set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM2_* +# set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM2_* +# set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM2_* +# set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM2_DQ[*] +# set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM2_DQ[*] +# set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDRAM2_DQ[*] +# set_instance_assignment -name ALLOW_SYNCH_CTRL_USAGE OFF -to *|SDRAM2_* -set_global_assignment -name VERILOG_MACRO "MISTER_DUAL_SDRAM=1" +# set_global_assignment -name VERILOG_MACRO "MISTER_DUAL_SDRAM=1" diff --git a/sys/sys_top.sdc b/sys/sys_top.sdc index 0d8763f..b82e74c 100644 --- a/sys/sys_top.sdc +++ b/sys/sys_top.sdc @@ -4,7 +4,7 @@ create_clock -period "50.0 MHz" [get_ports FPGA_CLK2_50] create_clock -period "50.0 MHz" [get_ports FPGA_CLK3_50] create_clock -period "100.0 MHz" [get_pins -compatibility_mode *|h2f_user0_clk] create_clock -period "100.0 MHz" [get_pins -compatibility_mode spi|sclk_out] -name spi_sck -create_clock -period "10.0 MHz" [get_pins -compatibility_mode hdmi_i2c|out_clk] -name hdmi_sck +#create_clock -period "10.0 MHz" [get_pins -compatibility_mode hdmi_i2c|out_clk] -name hdmi_sck derive_pll_clocks derive_clock_uncertainty @@ -15,7 +15,6 @@ set_clock_groups -exclusive \ -group [get_clocks { pll_hdmi|pll_hdmi_inst|altera_pll_i|*[0].*|divclk}] \ -group [get_clocks { pll_audio|pll_audio_inst|altera_pll_i|*[0].*|divclk}] \ -group [get_clocks { spi_sck}] \ - -group [get_clocks { hdmi_sck}] \ -group [get_clocks { *|h2f_user0_clk}] \ -group [get_clocks { FPGA_CLK1_50 }] \ -group [get_clocks { FPGA_CLK2_50 }] \ diff --git a/sys/sys_top.v b/sys/sys_top.v index 0b24d3d..9d2aa99 100644 --- a/sys/sys_top.v +++ b/sys/sys_top.v @@ -1,5 +1,8 @@ //============================================================================ // +// Arrow SoCKit / DE10-Standard / DE1-SoC MiSTer hardware abstraction module +// 2022 by Somhi https://github.com/somhi, based on 2019 work by modernhackers +// // MiSTer hardware abstraction module // (c)2017-2020 Alexey Melnikov // @@ -27,21 +30,21 @@ module sys_top input FPGA_CLK3_50, //////////// HDMI ////////// - output HDMI_I2C_SCL, - inout HDMI_I2C_SDA, - - output HDMI_MCLK, - output HDMI_SCLK, - output HDMI_LRCLK, - output HDMI_I2S, - - output HDMI_TX_CLK, - output HDMI_TX_DE, - output [23:0] HDMI_TX_D, - output HDMI_TX_HS, - output HDMI_TX_VS, + // output HDMI_I2C_SCL, + // inout HDMI_I2C_SDA, + + // output HDMI_MCLK, + // output HDMI_SCLK, + // output HDMI_LRCLK, + // output HDMI_I2S, + + // output HDMI_TX_CLK, + // output HDMI_TX_DE, + // output [23:0] HDMI_TX_D, + // output HDMI_TX_HS, + // output HDMI_TX_VS, - input HDMI_TX_INT, + // input HDMI_TX_INT, //////////// SDR /////////// output [12:0] SDRAM_A, @@ -69,18 +72,35 @@ module sys_top `else //////////// VGA /////////// - output [5:0] VGA_R, - output [5:0] VGA_G, - output [5:0] VGA_B, + //SoCkit, DE10-standard, DE1-SoC implementation needs 8 bit color otherwise the brightness is low on the DAC + output [7:0] VGA_R, + output [7:0] VGA_G, + output [7:0] VGA_B, inout VGA_HS, // VGA_HS is secondary SD card detect when VGA_EN = 1 (inactive) output VGA_VS, - input VGA_EN, // active low + //input VGA_EN, // active low + //SoCkit, DE10-standard, DE1-SoC implementation for on-board VGA DAC route - additional pins + output VGA_CLK, + output VGA_BLANK_N, + output VGA_SYNC_N, /////////// AUDIO ////////// output AUDIO_L, output AUDIO_R, output AUDIO_SPDIF, + //AUDIO CODEC implementation: SSM2603 for Arrow SoCkit, Wolfson WM8731 for DE10-standard & DE1-SoC + inout wire AUD_ADCLRCK, // Audio CODEC ADC LR Clock + input wire AUD_ADCDAT, // Audio CODEC ADC Data + inout wire AUD_DACLRCK, // Audio CODEC DAC LR Clock + output wire AUD_DACDAT, // Audio CODEC DAC Data + inout wire AUD_BCLK, // Audio CODEC Bit-Stream Clock + output wire AUD_XCK, // Audio CODEC Chip Clock + output wire AUD_MUTE, // Audio CODEC Mute (active low) + // I2C Audio CODEC + inout wire AUD_I2C_SDAT, // I2C Data + output wire AUD_I2C_SCLK, // I2C Clock + //////////// SDIO /////////// inout [3:0] SDIO_DAT, inout SDIO_CMD, @@ -96,34 +116,80 @@ module sys_top `endif ////////// I/O ALT ///////// - output SD_SPI_CS, - input SD_SPI_MISO, - output SD_SPI_CLK, - output SD_SPI_MOSI, + // output SD_SPI_CS, + // input SD_SPI_MISO, + // output SD_SPI_CLK, + // output SD_SPI_MOSI, inout SDCD_SPDIF, output IO_SCL, inout IO_SDA, ////////// ADC ////////////// - output ADC_SCK, - input ADC_SDO, - output ADC_SDI, - output ADC_CONVST, + // output ADC_SCK, + // input ADC_SDO, + // output ADC_SDI, + // output ADC_CONVST, ////////// MB KEY /////////// input [1:0] KEY, ////////// MB SWITCH //////// - input [3:0] SW, + //input [3:0] SW, + //SoCkit, DE10-standard, DE1-SoC board implementation + inout [3:0] SW, ////////// MB LED /////////// - output [7:0] LED, + //output [7:0] LED + //SoCkit, DE10-standard, DE1-SoC board implementation + output LED_0_USER, + output LED_1_HDD, + output LED_2_POWER, + output LED_3_LOCKED, ///////// USER IO /////////// inout [6:0] USER_IO ); +//SoCkit, DE10-standard, DE1-SoC board implementation +wire HDMI_TX_CLK; +wire HDMI_TX_DE; +wire [23:0] HDMI_TX_D; +wire HDMI_TX_HS; +wire HDMI_TX_VS; +wire HDMI_TX_INT; +wire HDMI_I2C_SCL; +wire HDMI_I2C_SDA; +wire HDMI_MCLK; +wire HDMI_SCLK; +wire HDMI_LRCLK; +wire HDMI_I2S; + +wire ADC_SCK; +wire ADC_SDO; +wire ADC_SDI; +wire ADC_CONVST; + +wire SD_SPI_CS; +wire SD_SPI_MISO; +wire SD_SPI_CLK; +wire SD_SPI_MOSI; + +wire [7:0] LED; + +assign LED_0_USER = LED[0]; +assign LED_1_HDD = LED[2]; +assign LED_2_POWER = LED[4]; +assign LED_3_LOCKED = LED[6]; + +// DE10-Standard / DE1-SoC / SoCKit implementation for on-board VGA DAC route - this will be overrided by code to set value to 0 +wire VGA_EN; // active low +assign VGA_EN = 1'b0; //enable VGA mode when VGA_EN is low + +// DE10-Standard / DE1-SoC / Arrow SoCKit VGA mode +assign SW[3] = 1'b0; //necessary for VGA mode + + ////////////////////// Secondary SD /////////////////////////////////// wire SD_CS, SD_CLK, SD_MOSI; @@ -1350,9 +1416,14 @@ csync csync_vga(clk_vid, vga_hs_osd, vga_vs_osd, vga_cs_osd); assign VGA_VS = (VGA_EN | SW[3]) ? 1'bZ : (((vga_fb | vga_scaler) ? (~vgas_vs ^ VS[12]) : VGA_DISABLE ? 1'd1 : ~vga_vs) | csync_en); assign VGA_HS = (VGA_EN | SW[3]) ? 1'bZ : ((vga_fb | vga_scaler) ? ((csync_en ? ~vgas_cs : ~vgas_hs) ^ HS[12]) : VGA_DISABLE ? 1'd1 : (csync_en ? ~vga_cs : ~vga_hs)); - assign VGA_R = (VGA_EN | SW[3]) ? 6'bZZZZZZ : (vga_fb | vga_scaler) ? vgas_o[23:18] : VGA_DISABLE ? 6'd0 : vga_o[23:18]; - assign VGA_G = (VGA_EN | SW[3]) ? 6'bZZZZZZ : (vga_fb | vga_scaler) ? vgas_o[15:10] : VGA_DISABLE ? 6'd0 : vga_o[15:10]; - assign VGA_B = (VGA_EN | SW[3]) ? 6'bZZZZZZ : (vga_fb | vga_scaler) ? vgas_o[7:2] : VGA_DISABLE ? 6'd0 : vga_o[7:2] ; + //DE10-standard / DE1-SoC / SoCkit implementation for on-board VGA DAC route - additional 2 bit per color + assign VGA_R = (VGA_EN | SW[3]) ? 8'bZZZZZZZZ : (vga_fb | vga_scaler) ? vgas_o[23:16] : VGA_DISABLE ? 8'd0 : vga_o[23:16]; + assign VGA_G = (VGA_EN | SW[3]) ? 8'bZZZZZZZZ : (vga_fb | vga_scaler) ? vgas_o[15:8] : VGA_DISABLE ? 8'd0 : vga_o[15:8] ; + assign VGA_B = (VGA_EN | SW[3]) ? 8'bZZZZZZZZ : (vga_fb | vga_scaler) ? vgas_o[7:0] : VGA_DISABLE ? 8'd0 : vga_o[7:0] ; + //DE10-standard / DE1-SoC / SoCkit implementation for on-board VGA DAC route - additional pins + assign VGA_BLANK_N = VGA_HS && VGA_VS; //VGA DAC additional required pin + assign VGA_SYNC_N = 0; //VGA DAC additional required pin + assign VGA_CLK = HDMI_TX_CLK; //has to define a clock to VGA DAC clock otherwise the picture is noisy `endif reg video_sync = 0; @@ -1466,6 +1537,26 @@ alsa alsa .pcm_r(alsa_r) ); + +//AUDIO CODEC implementation & configuration: SSM2603 for Arrow SoCkit and compatible Wolfson WM8731 for DE10-standard & DE1-SoC + +assign AUD_MUTE = 1'b1; +assign AUD_XCK = HDMI_MCLK; +assign AUD_DACLRCK = HDMI_LRCLK; +assign AUD_BCLK = HDMI_SCLK; +assign AUD_DACDAT = HDMI_I2S; + +// I2C audio config +I2C_AV_Config audio_config ( + // host side + .iCLK (clk_audio ), + .iRST_N (!reset ), + // i2c side + .oI2C_SCLK (AUD_I2C_SCLK ), + .oI2C_SDAT (AUD_I2C_SDAT ) +); + + //////////////// User I/O (USB 3.0 connector) ///////////////////////// assign USER_IO[0] = !user_out[0] ? 1'b0 : 1'bZ;