• DEPRECATED PAGE!!!!
  • Build Notes 2.0beta2
  • Schematics
  • BOM
  • Power Supply
  • Option: Low or High Current 9V Supply for Driver
  • Option: LVDS and Ethernet Bank Voltages
  • Option: Switching Power Supply Synchronied by FPGA
  • Issues and Required Modifications
  • Testing
  • FPGA
  • Options
  • Issues and Required Modifications
  • Testing
  • Ethernet
  • Options
  • Issues and Required Modifications
  • Testing
  • Clock
  • Option: No Versa Clock
  • Option: Crystal for X2
  • Option: VCO for X2
  • Option: Bypass Versa5
  • Option: External Clock
  • Option: Recovered Clock
  • Option: External I2C
  • Issues and Required Modifications
  • Testing
  • RF Frontend RX
  • Option: Local Clock
  • Option: External Clock
  • Option: Reverse Polatiry of T2
  • Option: Hand Wound or Commercial T2
  • Option: External RX Filter Board
  • Option: No Reconstruction Filter
  • Option: Secondary RX Input
  • Issues and Required Modifications
  • Testing
  • RF Frontend Low Power TX
  • Option: Instrument TX Only, PA TX Only, or Instrument and PA TX
  • Option: Adjust Low Power TX Level
  • Option: Bypass RF Driver
  • Option: Improve U9 Thermal Dissipation
  • Issues and Required Modifications
  • Testing
  • QRP Power Amplifier
  • Option: TO-220 LDMOS Devices
  • Option: Various Configurations
  • Option: Input Attenuator
  • Option: Transistor Adapter Board
  • Issues and Required Modifications
  • Testing and Usage
  • Input Output