{"payload":{"header_redesign_enabled":false,"results":[{"id":"216615048","archived":false,"color":"#b2b7f8","followers":4,"has_funding_file":false,"hl_name":"solomspd/RISC-V-CPU","hl_trunc_description":"RISC-V 5-stage pipeline RV32I implementation with forwarding in verilog with drivers to work on xilinx nexus a7 FPGA boards","language":"Verilog","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":216615048,"name":"RISC-V-CPU","owner_id":40343437,"owner_login":"solomspd","updated_at":"2022-08-22T20:57:09.057Z","has_issues":true}},"sponsorable":false,"topics":["fpga","verilog","risc-v","xilinx-fpga","rv32i","rv32im"],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":48,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Asolomspd%252FRISC-V-CPU%2B%2Blanguage%253AVerilog","metadata":null,"csrf_tokens":{"/solomspd/RISC-V-CPU/star":{"post":"NUEns61znFbnwxnb_wxmfx7X_8I40Mc4ydJWAqtz0JI8gEBwvM3jfHkdwKKKRu6fvTKDUncvYdZw1XEa0MYikA"},"/solomspd/RISC-V-CPU/unstar":{"post":"oFLW_4Ut4cp3FG3fDsAggL9TIzo1KxqWyw0_Ozw7MAF6rk8siRsFXrk-mCeCcouVGxVKYInLLYETFXxrS1rNGg"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"sMgzQFEh6Sz1DIfRKTIBRF7RR1NpMthqk4X5G3g_rs-K5lMWY4bB_vGiUrlGe13m923FAb4dwSRCgjtYD6RRQQ"}}},"title":"Repository search results"}