{"payload":{"header_redesign_enabled":false,"results":[{"id":"377404971","archived":true,"color":"#b2b7f8","followers":11,"has_funding_file":false,"hl_name":"srg320/S32X_MiSTer","hl_trunc_description":null,"language":"Verilog","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":377404971,"name":"S32X_MiSTer","owner_id":40274294,"owner_login":"srg320","updated_at":"2021-11-12T14:41:34.245Z","has_issues":true}},"sponsorable":false,"topics":[],"type":"Public archive","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":68,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Asrg320%252FS32X_MiSTer%2B%2Blanguage%253AVerilog","metadata":null,"csrf_tokens":{"/srg320/S32X_MiSTer/star":{"post":"s-6VYrb-NuJG4Jhw9cPZowRuLgsedku767aLbIVNglLW46nmT2sFjF53YPss1MAKtqq7ZIvc1FCpesttNcq5Aw"},"/srg320/S32X_MiSTer/unstar":{"post":"BYWR6E7ElsYTauKgM3W3vxAMKMCOWQS5K-0tqkPWoRe8XbnaB7NmlpiyXfQfS9l6KPHsU7tGSfLAkzPHD5zS1Q"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"L62Iljn-mEwgeTCsheio9fWVzAVpd4ccys1kOaRHpNNQ6flpEypGncYzbzjP4WFDG3kNPpYsLqgN2tjqrUP87g"}}},"title":"Repository search results"}