depbase=`echo task.lo | sed 's|[^/]*$|.deps/&|;s|\.lo$||'`;\
/bin/bash ./libtool  --tag=CC   --mode=compile /usr/local/popcorn/x86_64/bin/musl-clang -DHAVE_CONFIG_H -I.  -I./config/linux -I./config/posix -I.  -Wall -Werror -ftls-model=initial-exec -Wc,-pthread -target x86_64-linux-gnu -nostdinc -isystem /usr/local/popcorn/x86_64/include -popcorn-migratable -Wno-error -mllvm -debug-only=regalloc -mllvm -debug-only=stacktransform -pthread -popcorn-alignment -fno-common  -MT task.lo -MD -MP -MF $depbase.Tpo -c -o task.lo task.c &&\
mv -f $depbase.Tpo $depbase.Plo
libtool: compile:  /usr/local/popcorn/x86_64/bin/musl-clang -DHAVE_CONFIG_H -I. -I./config/linux -I./config/posix -I. -Wall -Werror -pthread -ftls-model=initial-exec -target x86_64-linux-gnu -nostdinc -isystem /usr/local/popcorn/x86_64/include -popcorn-migratable -Wno-error -mllvm -debug-only=regalloc -mllvm -debug-only=stacktransform -pthread -popcorn-alignment -fno-common -MT task.lo -MD -MP -MF .deps/task.Tpo -c task.c -o task.o
Computing live-in reg-units in ABI blocks.
0B	BB#0 W0#0 W1#0 W2#0
Created 3 new intervals.
********** INTERVALS **********
W0 [0B,48r:0)[96r,128r:3)[688r,704r:2)[928r,960r:1)  0@0B-phi 1@928r 2@688r 3@96r
W1 [0B,32r:0)[112r,128r:2)[944r,960r:1)  0@0B-phi 1@944r 2@112r
W2 [0B,16r:0)  0@0B-phi
%vreg0 [48r,208r:0)  0@48r
%vreg1 [32r,224r:0)  0@32r
%vreg2 [16r,240r:0)  0@16r
%vreg3 [80r,944r:0)  0@80r
%vreg4 [256r,288r:0)  0@256r
%vreg5 [272r,288r:0)  0@272r
%vreg6 [304r,416r:0)  0@304r
%vreg7 [320r,400r:0)  0@320r
%vreg8 [336r,352r:0)  0@336r
%vreg9 [368r,384r:0)  0@368r
%vreg10 [400r,416r:0)  0@400r
%vreg11 [432r,464r:0)  0@432r
%vreg12 [448r,624r:0)  0@448r
%vreg13 [480r,496r:0)  0@480r
%vreg14 [512r,528r:0)  0@512r
%vreg15 [544r,560r:0)  0@544r
%vreg16 [576r,592r:0)  0@576r
%vreg17 [608r,624r:0)  0@608r
%vreg18 [640r,656r:0)  0@640r
%vreg19 [656r,688r:0)  0@656r
%vreg20 [784r,800r:0)  0@784r
%vreg21 [816r,832r:0)  0@816r
%vreg22 [848r,864r:0)  0@848r
%vreg23 [880r,896r:0)  0@880r
RegMasks: 128r 704r 960r
********** MACHINEINSTRS **********
# Machine code for function gomp_init_task: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=8, align=8, at location [SP]
Function Live Ins: %X0 in %vreg0, %X1 in %vreg1, %X2 in %vreg2

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %X1 %X2
16B		%vreg2<def> = COPY %X2; GPR64:%vreg2
32B		%vreg1<def> = COPY %X1; GPR64:%vreg1
48B		%vreg0<def> = COPY %X0; GPR64:%vreg0
64B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
80B		%vreg3<def> = COPY %XZR; GPR64:%vreg3
96B		%X0<def> = COPY %vreg3; GPR64:%vreg3
112B		%X1<def> = COPY %vreg3; GPR64:%vreg3
128B		BL <ga:@check_migrate>, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %SP<imp-def>, ...
144B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
160B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
176B		STACKMAP 0, 0, %vreg1, %vreg2, %vreg0, ...; GPR64:%vreg1,%vreg2,%vreg0
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		STRXui %vreg0, <fi#0>, 0; mem:ST8[%task.addr] GPR64:%vreg0
224B		STRXui %vreg1, <fi#1>, 0; mem:ST8[%parent_task.addr] GPR64:%vreg1
240B		STRXui %vreg2, <fi#2>, 0; mem:ST8[%prev_icv.addr] GPR64:%vreg2
256B		%vreg4<def> = LDRXui <fi#1>, 0; mem:LD8[%parent_task.addr] GPR64:%vreg4
272B		%vreg5<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg5
288B		STRXui %vreg4, %vreg5, 0; mem:ST8[%parent] GPR64:%vreg4 GPR64common:%vreg5
304B		%vreg6<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg6
320B		%vreg7<def> = LDRXui <fi#2>, 0; mem:LD8[%prev_icv.addr] GPR64common:%vreg7
336B		%vreg8<def> = LDRXui %vreg7, 4; mem:LD8[%5+32] GPR64:%vreg8 GPR64common:%vreg7
352B		STRXui %vreg8, %vreg6, 22; mem:ST8[%4+32] GPR64:%vreg8 GPR64common:%vreg6
368B		%vreg9<def> = LDRQui %vreg7, 1; mem:LD16[%5+16](align=8) FPR128:%vreg9 GPR64common:%vreg7
384B		STRQui %vreg9, %vreg6, 10; mem:ST16[%4+16](align=8) FPR128:%vreg9 GPR64common:%vreg6
400B		%vreg10<def> = LDRQui %vreg7, 0; mem:LD16[%5](align=8) FPR128:%vreg10 GPR64common:%vreg7
416B		STRQui %vreg10, %vreg6, 9; mem:ST16[%4](align=8) FPR128:%vreg10 GPR64common:%vreg6
432B		%vreg11<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg11
448B		%vreg12<def> = COPY %WZR; GPR32:%vreg12
464B		STRWui %vreg12, %vreg11, 50; mem:ST4[%kind] GPR32:%vreg12 GPR64common:%vreg11
480B		%vreg13<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg13
496B		STRXui %vreg3, %vreg13, 8; mem:ST8[%taskwait] GPR64:%vreg3 GPR64common:%vreg13
512B		%vreg14<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg14
528B		STRBBui %vreg12, %vreg14, 204; mem:ST1[%in_tied_task] GPR32:%vreg12 GPR64common:%vreg14
544B		%vreg15<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg15
560B		STRBBui %vreg12, %vreg15, 205; mem:ST1[%final_task] GPR32:%vreg12 GPR64common:%vreg15
576B		%vreg16<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg16
592B		STRBBui %vreg12, %vreg16, 206; mem:ST1[%copy_ctors_done] GPR32:%vreg12 GPR64common:%vreg16
608B		%vreg17<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg17
624B		STRBBui %vreg12, %vreg17, 207; mem:ST1[%parent_depends_on] GPR32:%vreg12 GPR64common:%vreg17
640B		%vreg18<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg18
656B		%vreg19<def> = ADDXri %vreg18, 8, 0; GPR64sp:%vreg19 GPR64common:%vreg18
672B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
688B		%X0<def> = COPY %vreg19; GPR64sp:%vreg19
704B		BL <ga:@priority_queue_init>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...
720B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
736B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
752B		STACKMAP 1, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0]
768B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
784B		%vreg20<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg20
800B		STRXui %vreg3, %vreg20, 5; mem:ST8[%taskgroup] GPR64:%vreg3 GPR64common:%vreg20
816B		%vreg21<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg21
832B		STRXui %vreg3, %vreg21, 6; mem:ST8[%dependers] GPR64:%vreg3 GPR64common:%vreg21
848B		%vreg22<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg22
864B		STRXui %vreg3, %vreg22, 7; mem:ST8[%depend_hash] GPR64:%vreg3 GPR64common:%vreg22
880B		%vreg23<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg23
896B		STRXui %vreg3, %vreg23, 9; mem:ST8[%depend_count] GPR64:%vreg3 GPR64common:%vreg23
912B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
928B		%X0<def> = COPY %vreg3; GPR64:%vreg3
944B		%X1<def> = COPY %vreg3; GPR64:%vreg3
960B		BL <ga:@check_migrate>, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %SP<imp-def>, ...
976B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
992B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1008B		STACKMAP 2, 0, ...
1024B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1040B		RET_ReallyLR

# End machine code for function gomp_init_task.

********** SIMPLE REGISTER COALESCING **********
********** Function: gomp_init_task
********** JOINING INTERVALS ***********
entry:
16B	%vreg2<def> = COPY %X2; GPR64:%vreg2
	Considering merging %vreg2 with %X2
	Can only merge into reserved registers.
32B	%vreg1<def> = COPY %X1; GPR64:%vreg1
	Considering merging %vreg1 with %X1
	Can only merge into reserved registers.
48B	%vreg0<def> = COPY %X0; GPR64:%vreg0
	Considering merging %vreg0 with %X0
	Can only merge into reserved registers.
80B	%vreg3<def> = COPY %XZR; GPR64:%vreg3
	Considering merging %vreg3 with %XZR
		RHS = %vreg3 [80r,944r:0)  0@80r
		updated: 96B	%X0<def> = COPY %XZR
		updated: 112B	%X1<def> = COPY %XZR
		updated: 496B	STRXui %XZR, %vreg13, 8; mem:ST8[%taskwait] GPR64common:%vreg13
		updated: 800B	STRXui %XZR, %vreg20, 5; mem:ST8[%taskgroup] GPR64common:%vreg20
		updated: 832B	STRXui %XZR, %vreg21, 6; mem:ST8[%dependers] GPR64common:%vreg21
		updated: 864B	STRXui %XZR, %vreg22, 7; mem:ST8[%depend_hash] GPR64common:%vreg22
		updated: 896B	STRXui %XZR, %vreg23, 9; mem:ST8[%depend_count] GPR64common:%vreg23
		updated: 928B	%X0<def> = COPY %XZR
		updated: 944B	%X1<def> = COPY %XZR
	Success: %vreg3 -> %XZR
	Result = %XZR
96B	%X0<def> = COPY %XZR
	Not coalescable.
112B	%X1<def> = COPY %XZR
	Not coalescable.
448B	%vreg12<def> = COPY %WZR; GPR32:%vreg12
	Considering merging %vreg12 with %WZR
		RHS = %vreg12 [448r,624r:0)  0@448r
		updated: 464B	STRWui %WZR, %vreg11, 50; mem:ST4[%kind] GPR64common:%vreg11
		updated: 528B	STRBBui %WZR, %vreg14, 204; mem:ST1[%in_tied_task] GPR64common:%vreg14
		updated: 560B	STRBBui %WZR, %vreg15, 205; mem:ST1[%final_task] GPR64common:%vreg15
		updated: 592B	STRBBui %WZR, %vreg16, 206; mem:ST1[%copy_ctors_done] GPR64common:%vreg16
		updated: 624B	STRBBui %WZR, %vreg17, 207; mem:ST1[%parent_depends_on] GPR64common:%vreg17
	Success: %vreg12 -> %WZR
	Result = %WZR
688B	%X0<def> = COPY %vreg19; GPR64sp:%vreg19
	Considering merging %vreg19 with %X0
	Can only merge into reserved registers.
928B	%X0<def> = COPY %XZR
	Not coalescable.
944B	%X1<def> = COPY %XZR
	Not coalescable.
Trying to inflate 0 regs.
********** INTERVALS **********
WZR EMPTY
W0 [0B,48r:0)[96r,128r:3)[688r,704r:2)[928r,960r:1)  0@0B-phi 1@928r 2@688r 3@96r
W1 [0B,32r:0)[112r,128r:2)[944r,960r:1)  0@0B-phi 1@944r 2@112r
W2 [0B,16r:0)  0@0B-phi
%vreg0 [48r,208r:0)  0@48r
%vreg1 [32r,224r:0)  0@32r
%vreg2 [16r,240r:0)  0@16r
%vreg4 [256r,288r:0)  0@256r
%vreg5 [272r,288r:0)  0@272r
%vreg6 [304r,416r:0)  0@304r
%vreg7 [320r,400r:0)  0@320r
%vreg8 [336r,352r:0)  0@336r
%vreg9 [368r,384r:0)  0@368r
%vreg10 [400r,416r:0)  0@400r
%vreg11 [432r,464r:0)  0@432r
%vreg13 [480r,496r:0)  0@480r
%vreg14 [512r,528r:0)  0@512r
%vreg15 [544r,560r:0)  0@544r
%vreg16 [576r,592r:0)  0@576r
%vreg17 [608r,624r:0)  0@608r
%vreg18 [640r,656r:0)  0@640r
%vreg19 [656r,688r:0)  0@656r
%vreg20 [784r,800r:0)  0@784r
%vreg21 [816r,832r:0)  0@816r
%vreg22 [848r,864r:0)  0@848r
%vreg23 [880r,896r:0)  0@880r
RegMasks: 128r 704r 960r
********** MACHINEINSTRS **********
# Machine code for function gomp_init_task: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=8, align=8, at location [SP]
Function Live Ins: %X0 in %vreg0, %X1 in %vreg1, %X2 in %vreg2

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %X1 %X2
16B		%vreg2<def> = COPY %X2; GPR64:%vreg2
32B		%vreg1<def> = COPY %X1; GPR64:%vreg1
48B		%vreg0<def> = COPY %X0; GPR64:%vreg0
64B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
96B		%X0<def> = COPY %XZR
112B		%X1<def> = COPY %XZR
128B		BL <ga:@check_migrate>, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %SP<imp-def>, ...
144B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
160B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
176B		STACKMAP 0, 0, %vreg1, %vreg2, %vreg0, ...; GPR64:%vreg1,%vreg2,%vreg0
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		STRXui %vreg0, <fi#0>, 0; mem:ST8[%task.addr] GPR64:%vreg0
224B		STRXui %vreg1, <fi#1>, 0; mem:ST8[%parent_task.addr] GPR64:%vreg1
240B		STRXui %vreg2, <fi#2>, 0; mem:ST8[%prev_icv.addr] GPR64:%vreg2
256B		%vreg4<def> = LDRXui <fi#1>, 0; mem:LD8[%parent_task.addr] GPR64:%vreg4
272B		%vreg5<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg5
288B		STRXui %vreg4, %vreg5, 0; mem:ST8[%parent] GPR64:%vreg4 GPR64common:%vreg5
304B		%vreg6<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg6
320B		%vreg7<def> = LDRXui <fi#2>, 0; mem:LD8[%prev_icv.addr] GPR64common:%vreg7
336B		%vreg8<def> = LDRXui %vreg7, 4; mem:LD8[%5+32] GPR64:%vreg8 GPR64common:%vreg7
352B		STRXui %vreg8, %vreg6, 22; mem:ST8[%4+32] GPR64:%vreg8 GPR64common:%vreg6
368B		%vreg9<def> = LDRQui %vreg7, 1; mem:LD16[%5+16](align=8) FPR128:%vreg9 GPR64common:%vreg7
384B		STRQui %vreg9, %vreg6, 10; mem:ST16[%4+16](align=8) FPR128:%vreg9 GPR64common:%vreg6
400B		%vreg10<def> = LDRQui %vreg7, 0; mem:LD16[%5](align=8) FPR128:%vreg10 GPR64common:%vreg7
416B		STRQui %vreg10, %vreg6, 9; mem:ST16[%4](align=8) FPR128:%vreg10 GPR64common:%vreg6
432B		%vreg11<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg11
464B		STRWui %WZR, %vreg11, 50; mem:ST4[%kind] GPR64common:%vreg11
480B		%vreg13<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg13
496B		STRXui %XZR, %vreg13, 8; mem:ST8[%taskwait] GPR64common:%vreg13
512B		%vreg14<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg14
528B		STRBBui %WZR, %vreg14, 204; mem:ST1[%in_tied_task] GPR64common:%vreg14
544B		%vreg15<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg15
560B		STRBBui %WZR, %vreg15, 205; mem:ST1[%final_task] GPR64common:%vreg15
576B		%vreg16<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg16
592B		STRBBui %WZR, %vreg16, 206; mem:ST1[%copy_ctors_done] GPR64common:%vreg16
608B		%vreg17<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg17
624B		STRBBui %WZR, %vreg17, 207; mem:ST1[%parent_depends_on] GPR64common:%vreg17
640B		%vreg18<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg18
656B		%vreg19<def> = ADDXri %vreg18, 8, 0; GPR64sp:%vreg19 GPR64common:%vreg18
672B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
688B		%X0<def> = COPY %vreg19; GPR64sp:%vreg19
704B		BL <ga:@priority_queue_init>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...
720B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
736B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
752B		STACKMAP 1, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0]
768B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
784B		%vreg20<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg20
800B		STRXui %XZR, %vreg20, 5; mem:ST8[%taskgroup] GPR64common:%vreg20
816B		%vreg21<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg21
832B		STRXui %XZR, %vreg21, 6; mem:ST8[%dependers] GPR64common:%vreg21
848B		%vreg22<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg22
864B		STRXui %XZR, %vreg22, 7; mem:ST8[%depend_hash] GPR64common:%vreg22
880B		%vreg23<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg23
896B		STRXui %XZR, %vreg23, 9; mem:ST8[%depend_count] GPR64common:%vreg23
912B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
928B		%X0<def> = COPY %XZR
944B		%X1<def> = COPY %XZR
960B		BL <ga:@check_migrate>, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %SP<imp-def>, ...
976B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
992B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1008B		STACKMAP 2, 0, ...
1024B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1040B		RET_ReallyLR

# End machine code for function gomp_init_task.

AllocationOrder(GPR32all) = [ %W0 %W1 %W2 %W3 %W4 %W5 %W6 %W7 %W8 %W9 %W10 %W11 %W12 %W13 %W14 %W15 %W16 %W17 %W18 %W19 %W20 %W21 %W22 %W23 %W24 %W25 %W26 %W27 %W28 %W30 ]
AllocationOrder(GPR32sponly) = [ ]
AllocationOrder(XSeqPairsClass_with_sube64_in_tcGPR64) = [ %X0_X1 %X1_X2 %X2_X3 %X3_X4 %X4_X5 %X5_X6 %X6_X7 %X7_X8 %X8_X9 %X9_X10 %X10_X11 %X11_X12 %X12_X13 %X13_X14 %X14_X15 %X15_X16 %X16_X17 %X17_X18 %X18_X19 ]
AllocationOrder(QQQQ_with_qsub0_in_FPR128_lo) = [ %Q0_Q1_Q2_Q3 %Q1_Q2_Q3_Q4 %Q2_Q3_Q4_Q5 %Q3_Q4_Q5_Q6 %Q4_Q5_Q6_Q7 %Q5_Q6_Q7_Q8 %Q6_Q7_Q8_Q9 %Q7_Q8_Q9_Q10 %Q8_Q9_Q10_Q11 %Q9_Q10_Q11_Q12 %Q10_Q11_Q12_Q13 %Q11_Q12_Q13_Q14 %Q12_Q13_Q14_Q15 %Q13_Q14_Q15_Q16 %Q14_Q15_Q16_Q17 %Q15_Q16_Q17_Q18 ]
AllocationOrder(FPR8) = [ %B0 %B1 %B2 %B3 %B4 %B5 %B6 %B7 %B16 %B17 %B18 %B19 %B20 %B21 %B22 %B23 %B24 %B25 %B26 %B27 %B28 %B29 %B30 %B31 %B8 %B9 %B10 %B11 %B12 %B13 %B14 %B15 ]
AllocationOrder(GPR32all) = [ %W0 %W1 %W2 %W3 %W4 %W5 %W6 %W7 %W8 %W9 %W10 %W11 %W12 %W13 %W14 %W15 %W16 %W17 %W18 %W19 %W20 %W21 %W22 %W23 %W24 %W25 %W26 %W27 %W28 %W30 ]
handleMove 304B -> 328B: %vreg6<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg6
     %vreg6:	[304r,416r:0)  0@304r
        -->	[328r,416r:0)  0@328r
handleMove 240B -> 280B: STRXui %vreg2, <fi#2>, 0; mem:ST8[%prev_icv.addr] GPR64:%vreg2
     %vreg2:	[16r,240r:0)  0@16r
        -->	[16r,280r:0)  0@16r
********** GREEDY REGISTER ALLOCATION **********
********** Function: gomp_init_task
********** INTERVALS **********
WZR EMPTY
W0 [0B,48r:0)[96r,128r:3)[688r,704r:2)[928r,960r:1)  0@0B-phi 1@928r 2@688r 3@96r
W1 [0B,32r:0)[112r,128r:2)[944r,960r:1)  0@0B-phi 1@944r 2@112r
W2 [0B,16r:0)  0@0B-phi
%vreg0 [48r,208r:0)  0@48r
%vreg1 [32r,224r:0)  0@32r
%vreg2 [16r,280r:0)  0@16r
%vreg4 [256r,288r:0)  0@256r
%vreg5 [272r,288r:0)  0@272r
%vreg6 [328r,416r:0)  0@328r
%vreg7 [320r,400r:0)  0@320r
%vreg8 [336r,352r:0)  0@336r
%vreg9 [368r,384r:0)  0@368r
%vreg10 [400r,416r:0)  0@400r
%vreg11 [432r,464r:0)  0@432r
%vreg13 [480r,496r:0)  0@480r
%vreg14 [512r,528r:0)  0@512r
%vreg15 [544r,560r:0)  0@544r
%vreg16 [576r,592r:0)  0@576r
%vreg17 [608r,624r:0)  0@608r
%vreg18 [640r,656r:0)  0@640r
%vreg19 [656r,688r:0)  0@656r
%vreg20 [784r,800r:0)  0@784r
%vreg21 [816r,832r:0)  0@816r
%vreg22 [848r,864r:0)  0@848r
%vreg23 [880r,896r:0)  0@880r
RegMasks: 128r 704r 960r
********** MACHINEINSTRS **********
# Machine code for function gomp_init_task: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=8, align=8, at location [SP]
Function Live Ins: %X0 in %vreg0, %X1 in %vreg1, %X2 in %vreg2

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %X1 %X2
16B		%vreg2<def> = COPY %X2; GPR64:%vreg2
32B		%vreg1<def> = COPY %X1; GPR64:%vreg1
48B		%vreg0<def> = COPY %X0; GPR64:%vreg0
64B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
96B		%X0<def> = COPY %XZR
112B		%X1<def> = COPY %XZR
128B		BL <ga:@check_migrate>, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %SP<imp-def>, ...
144B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
160B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
176B		STACKMAP 0, 0, %vreg1, %vreg2, %vreg0, ...; GPR64:%vreg1,%vreg2,%vreg0
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		STRXui %vreg0, <fi#0>, 0; mem:ST8[%task.addr] GPR64:%vreg0
224B		STRXui %vreg1, <fi#1>, 0; mem:ST8[%parent_task.addr] GPR64:%vreg1
256B		%vreg4<def> = LDRXui <fi#1>, 0; mem:LD8[%parent_task.addr] GPR64:%vreg4
272B		%vreg5<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg5
280B		STRXui %vreg2, <fi#2>, 0; mem:ST8[%prev_icv.addr] GPR64:%vreg2
288B		STRXui %vreg4, %vreg5, 0; mem:ST8[%parent] GPR64:%vreg4 GPR64common:%vreg5
320B		%vreg7<def> = LDRXui <fi#2>, 0; mem:LD8[%prev_icv.addr] GPR64common:%vreg7
328B		%vreg6<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg6
336B		%vreg8<def> = LDRXui %vreg7, 4; mem:LD8[%5+32] GPR64:%vreg8 GPR64common:%vreg7
352B		STRXui %vreg8, %vreg6, 22; mem:ST8[%4+32] GPR64:%vreg8 GPR64common:%vreg6
368B		%vreg9<def> = LDRQui %vreg7, 1; mem:LD16[%5+16](align=8) FPR128:%vreg9 GPR64common:%vreg7
384B		STRQui %vreg9, %vreg6, 10; mem:ST16[%4+16](align=8) FPR128:%vreg9 GPR64common:%vreg6
400B		%vreg10<def> = LDRQui %vreg7, 0; mem:LD16[%5](align=8) FPR128:%vreg10 GPR64common:%vreg7
416B		STRQui %vreg10, %vreg6, 9; mem:ST16[%4](align=8) FPR128:%vreg10 GPR64common:%vreg6
432B		%vreg11<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg11
464B		STRWui %WZR, %vreg11, 50; mem:ST4[%kind] GPR64common:%vreg11
480B		%vreg13<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg13
496B		STRXui %XZR, %vreg13, 8; mem:ST8[%taskwait] GPR64common:%vreg13
512B		%vreg14<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg14
528B		STRBBui %WZR, %vreg14, 204; mem:ST1[%in_tied_task] GPR64common:%vreg14
544B		%vreg15<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg15
560B		STRBBui %WZR, %vreg15, 205; mem:ST1[%final_task] GPR64common:%vreg15
576B		%vreg16<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg16
592B		STRBBui %WZR, %vreg16, 206; mem:ST1[%copy_ctors_done] GPR64common:%vreg16
608B		%vreg17<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg17
624B		STRBBui %WZR, %vreg17, 207; mem:ST1[%parent_depends_on] GPR64common:%vreg17
640B		%vreg18<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg18
656B		%vreg19<def> = ADDXri %vreg18, 8, 0; GPR64sp:%vreg19 GPR64common:%vreg18
672B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
688B		%X0<def> = COPY %vreg19; GPR64sp:%vreg19
704B		BL <ga:@priority_queue_init>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...
720B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
736B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
752B		STACKMAP 1, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0]
768B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
784B		%vreg20<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg20
800B		STRXui %XZR, %vreg20, 5; mem:ST8[%taskgroup] GPR64common:%vreg20
816B		%vreg21<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg21
832B		STRXui %XZR, %vreg21, 6; mem:ST8[%dependers] GPR64common:%vreg21
848B		%vreg22<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg22
864B		STRXui %XZR, %vreg22, 7; mem:ST8[%depend_hash] GPR64common:%vreg22
880B		%vreg23<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg23
896B		STRXui %XZR, %vreg23, 9; mem:ST8[%depend_count] GPR64common:%vreg23
912B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
928B		%X0<def> = COPY %XZR
944B		%X1<def> = COPY %XZR
960B		BL <ga:@check_migrate>, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %SP<imp-def>, ...
976B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
992B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1008B		STACKMAP 2, 0, ...
1024B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1040B		RET_ReallyLR

# End machine code for function gomp_init_task.


selectOrSplit GPR64:%vreg2 [16r,280r:0)  0@16r w=4.563253e-03
AllocationOrder(GPR64) = [ %X8 %X9 %X10 %X11 %X12 %X13 %X14 %X15 %X16 %X17 %X18 %X0 %X1 %X2 %X3 %X4 %X5 %X6 %X7 %X19 %X20 %X21 %X22 %X23 %X24 %X25 %X26 %X27 %X28 %LR ]
hints: %X2
missed hint %X2
assigning %vreg2 to %X19: W19 [16r,280r:0)  0@16r

selectOrSplit GPR64:%vreg1 [32r,224r:0)  0@32r w=5.118243e-03
hints: %X1
missed hint %X1
assigning %vreg1 to %X20: W20 [32r,224r:0)  0@32r

selectOrSplit GPR64:%vreg0 [48r,208r:0)  0@48r w=5.410714e-03
hints: %X0
missed hint %X0
assigning %vreg0 to %X21: W21 [48r,208r:0)  0@48r

selectOrSplit GPR64sp:%vreg19 [656r,688r:0)  0@656r w=4.675926e-03
AllocationOrder(GPR64sp) = [ %X8 %X9 %X10 %X11 %X12 %X13 %X14 %X15 %X16 %X17 %X18 %X0 %X1 %X2 %X3 %X4 %X5 %X6 %X7 %X19 %X20 %X21 %X22 %X23 %X24 %X25 %X26 %X27 %X28 %LR ]
hints: %X0
assigning %vreg19 to %X0: W0 [656r,688r:0)  0@656r

selectOrSplit GPR64:%vreg4 [256r,288r:0)  0@256r w=4.629630e-03
assigning %vreg4 to %X8: W8 [256r,288r:0)  0@256r

selectOrSplit GPR64common:%vreg5 [272r,288r:0)  0@272r w=4.807692e-03
AllocationOrder(GPR64common) = [ %X8 %X9 %X10 %X11 %X12 %X13 %X14 %X15 %X16 %X17 %X18 %X0 %X1 %X2 %X3 %X4 %X5 %X6 %X7 %X19 %X20 %X21 %X22 %X23 %X24 %X25 %X26 %X27 %X28 %LR ]
assigning %vreg5 to %X9: W9 [272r,288r:0)  0@272r

selectOrSplit GPR64common:%vreg7 [320r,400r:0)  0@320r w=8.333334e-03
assigning %vreg7 to %X8: W8 [320r,400r:0)  0@320r

selectOrSplit GPR64common:%vreg6 [328r,416r:0)  0@328r w=8.196721e-03
assigning %vreg6 to %X9: W9 [328r,416r:0)  0@328r

selectOrSplit GPR64:%vreg8 [336r,352r:0)  0@336r w=inf
assigning %vreg8 to %X10: W10 [336r,352r:0)  0@336r

selectOrSplit FPR128:%vreg9 [368r,384r:0)  0@368r w=inf
AllocationOrder(FPR128) = [ %Q0 %Q1 %Q2 %Q3 %Q4 %Q5 %Q6 %Q7 %Q16 %Q17 %Q18 %Q19 %Q20 %Q21 %Q22 %Q23 %Q24 %Q25 %Q26 %Q27 %Q28 %Q29 %Q30 %Q31 %Q8 %Q9 %Q10 %Q11 %Q12 %Q13 %Q14 %Q15 ]
assigning %vreg9 to %Q0: B0 [368r,384r:0)  0@368r

selectOrSplit FPR128:%vreg10 [400r,416r:0)  0@400r w=inf
assigning %vreg10 to %Q0: B0 [400r,416r:0)  0@400r

selectOrSplit GPR64common:%vreg11 [432r,464r:0)  0@432r w=inf
assigning %vreg11 to %X8: W8 [432r,464r:0)  0@432r

selectOrSplit GPR64common:%vreg13 [480r,496r:0)  0@480r w=inf
assigning %vreg13 to %X8: W8 [480r,496r:0)  0@480r

selectOrSplit GPR64common:%vreg14 [512r,528r:0)  0@512r w=inf
assigning %vreg14 to %X8: W8 [512r,528r:0)  0@512r

selectOrSplit GPR64common:%vreg15 [544r,560r:0)  0@544r w=inf
assigning %vreg15 to %X8: W8 [544r,560r:0)  0@544r

selectOrSplit GPR64common:%vreg16 [576r,592r:0)  0@576r w=inf
assigning %vreg16 to %X8: W8 [576r,592r:0)  0@576r

selectOrSplit GPR64common:%vreg17 [608r,624r:0)  0@608r w=inf
assigning %vreg17 to %X8: W8 [608r,624r:0)  0@608r

selectOrSplit GPR64common:%vreg18 [640r,656r:0)  0@640r w=inf
assigning %vreg18 to %X8: W8 [640r,656r:0)  0@640r

selectOrSplit GPR64common:%vreg20 [784r,800r:0)  0@784r w=inf
assigning %vreg20 to %X8: W8 [784r,800r:0)  0@784r

selectOrSplit GPR64common:%vreg21 [816r,832r:0)  0@816r w=inf
assigning %vreg21 to %X8: W8 [816r,832r:0)  0@816r

selectOrSplit GPR64common:%vreg22 [848r,864r:0)  0@848r w=inf
assigning %vreg22 to %X8: W8 [848r,864r:0)  0@848r

selectOrSplit GPR64common:%vreg23 [880r,896r:0)  0@880r w=inf
assigning %vreg23 to %X8: W8 [880r,896r:0)  0@880r

********** STACK TRANSFORMATION METADATA **********
********** Function: gomp_init_task
********** REGISTER MAP **********
[%vreg0 -> %X21] GPR64
[%vreg1 -> %X20] GPR64
[%vreg2 -> %X19] GPR64
[%vreg4 -> %X8] GPR64
[%vreg5 -> %X9] GPR64common
[%vreg6 -> %X9] GPR64common
[%vreg7 -> %X8] GPR64common
[%vreg8 -> %X10] GPR64
[%vreg9 -> %Q0] FPR128
[%vreg10 -> %Q0] FPR128
[%vreg11 -> %X8] GPR64common
[%vreg13 -> %X8] GPR64common
[%vreg14 -> %X8] GPR64common
[%vreg15 -> %X8] GPR64common
[%vreg16 -> %X8] GPR64common
[%vreg17 -> %X8] GPR64common
[%vreg18 -> %X8] GPR64common
[%vreg19 -> %X0] GPR64sp
[%vreg20 -> %X8] GPR64common
[%vreg21 -> %X8] GPR64common
[%vreg22 -> %X8] GPR64common
[%vreg23 -> %X8] GPR64common


*** Stack slot copies ***

Stack slot 0:
  STRXui %vreg0, <fi#0>, 0; mem:ST8[%task.addr] GPR64:%vreg0
  %vreg5<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg5
  %vreg6<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg6
  %vreg11<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg11
  %vreg13<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg13
  %vreg14<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg14
  %vreg15<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg15
  %vreg16<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg16
  %vreg17<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg17
  %vreg18<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg18
  %vreg20<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg20
  %vreg21<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg21
  %vreg22<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg22
  %vreg23<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg23
Stack slot 1:
  STRXui %vreg1, <fi#1>, 0; mem:ST8[%parent_task.addr] GPR64:%vreg1
  %vreg4<def> = LDRXui <fi#1>, 0; mem:LD8[%parent_task.addr] GPR64:%vreg4
Stack slot 2:
  STRXui %vreg2, <fi#2>, 0; mem:ST8[%prev_icv.addr] GPR64:%vreg2
  %vreg7<def> = LDRXui <fi#2>, 0; mem:LD8[%prev_icv.addr] GPR64common:%vreg7

Stackmap 0:
  STACKMAP 0, 0, %vreg1, %vreg2, %vreg0, ...; GPR64:%vreg1,%vreg2,%vreg0

%struct.gomp_task* %parent_task: in register %X20 (vreg 1)
%struct.gomp_task_icv* %prev_icv: in register %X19 (vreg 2)
%struct.gomp_task* %task: in register %X21 (vreg 0)

Unwinding stackmap back to call site:

  - Skipping   ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
  - Skipping   ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0]

%struct.gomp_task** %task.addr: in stack slot 0 (size: 8)

Unwinding stackmap back to call site:

  - Skipping   ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
  - Skipping   ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>

Duplicate operand locations:


Stackmap 2:
  STACKMAP 2, 0, ...


Unwinding stackmap back to call site:

  - Skipping   ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
  - Skipping   ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>

Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, %vreg1, %vreg2, %vreg0, ...; GPR64:%vreg1,%vreg2,%vreg0
  -> Call instruction SlotIndex 128B, searching vregs 0 -> 24 and stack slots 0 -> 3

  STACKMAP 1, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0]
  -> Call instruction SlotIndex 704B, searching vregs 0 -> 24 and stack slots 0 -> 3

  STACKMAP 2, 0, ...
  -> Call instruction SlotIndex 960B, searching vregs 0 -> 24 and stack slots 0 -> 3

********** REWRITE VIRTUAL REGISTERS **********
********** Function: gomp_init_task
********** REGISTER MAP **********
[%vreg0 -> %X21] GPR64
[%vreg1 -> %X20] GPR64
[%vreg2 -> %X19] GPR64
[%vreg4 -> %X8] GPR64
[%vreg5 -> %X9] GPR64common
[%vreg6 -> %X9] GPR64common
[%vreg7 -> %X8] GPR64common
[%vreg8 -> %X10] GPR64
[%vreg9 -> %Q0] FPR128
[%vreg10 -> %Q0] FPR128
[%vreg11 -> %X8] GPR64common
[%vreg13 -> %X8] GPR64common
[%vreg14 -> %X8] GPR64common
[%vreg15 -> %X8] GPR64common
[%vreg16 -> %X8] GPR64common
[%vreg17 -> %X8] GPR64common
[%vreg18 -> %X8] GPR64common
[%vreg19 -> %X0] GPR64sp
[%vreg20 -> %X8] GPR64common
[%vreg21 -> %X8] GPR64common
[%vreg22 -> %X8] GPR64common
[%vreg23 -> %X8] GPR64common

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %X1 %X2
16B		%vreg2<def> = COPY %X2; GPR64:%vreg2
32B		%vreg1<def> = COPY %X1; GPR64:%vreg1
48B		%vreg0<def> = COPY %X0; GPR64:%vreg0
64B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
96B		%X0<def> = COPY %XZR
112B		%X1<def> = COPY %XZR
128B		BL <ga:@check_migrate>, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %SP<imp-def>, ...
144B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
160B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
176B		STACKMAP 0, 0, %vreg1, %vreg2, %vreg0, ...; GPR64:%vreg1,%vreg2,%vreg0
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		STRXui %vreg0<kill>, <fi#0>, 0; mem:ST8[%task.addr] GPR64:%vreg0
224B		STRXui %vreg1<kill>, <fi#1>, 0; mem:ST8[%parent_task.addr] GPR64:%vreg1
256B		%vreg4<def> = LDRXui <fi#1>, 0; mem:LD8[%parent_task.addr] GPR64:%vreg4
272B		%vreg5<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg5
280B		STRXui %vreg2<kill>, <fi#2>, 0; mem:ST8[%prev_icv.addr] GPR64:%vreg2
288B		STRXui %vreg4<kill>, %vreg5<kill>, 0; mem:ST8[%parent] GPR64:%vreg4 GPR64common:%vreg5
320B		%vreg7<def> = LDRXui <fi#2>, 0; mem:LD8[%prev_icv.addr] GPR64common:%vreg7
328B		%vreg6<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg6
336B		%vreg8<def> = LDRXui %vreg7, 4; mem:LD8[%5+32] GPR64:%vreg8 GPR64common:%vreg7
352B		STRXui %vreg8<kill>, %vreg6, 22; mem:ST8[%4+32] GPR64:%vreg8 GPR64common:%vreg6
368B		%vreg9<def> = LDRQui %vreg7, 1; mem:LD16[%5+16](align=8) FPR128:%vreg9 GPR64common:%vreg7
384B		STRQui %vreg9<kill>, %vreg6, 10; mem:ST16[%4+16](align=8) FPR128:%vreg9 GPR64common:%vreg6
400B		%vreg10<def> = LDRQui %vreg7<kill>, 0; mem:LD16[%5](align=8) FPR128:%vreg10 GPR64common:%vreg7
416B		STRQui %vreg10<kill>, %vreg6<kill>, 9; mem:ST16[%4](align=8) FPR128:%vreg10 GPR64common:%vreg6
432B		%vreg11<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg11
464B		STRWui %WZR, %vreg11<kill>, 50; mem:ST4[%kind] GPR64common:%vreg11
480B		%vreg13<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg13
496B		STRXui %XZR, %vreg13<kill>, 8; mem:ST8[%taskwait] GPR64common:%vreg13
512B		%vreg14<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg14
528B		STRBBui %WZR, %vreg14<kill>, 204; mem:ST1[%in_tied_task] GPR64common:%vreg14
544B		%vreg15<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg15
560B		STRBBui %WZR, %vreg15<kill>, 205; mem:ST1[%final_task] GPR64common:%vreg15
576B		%vreg16<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg16
592B		STRBBui %WZR, %vreg16<kill>, 206; mem:ST1[%copy_ctors_done] GPR64common:%vreg16
608B		%vreg17<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg17
624B		STRBBui %WZR, %vreg17<kill>, 207; mem:ST1[%parent_depends_on] GPR64common:%vreg17
640B		%vreg18<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg18
656B		%vreg19<def> = ADDXri %vreg18<kill>, 8, 0; GPR64sp:%vreg19 GPR64common:%vreg18
672B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
688B		%X0<def> = COPY %vreg19<kill>; GPR64sp:%vreg19
704B		BL <ga:@priority_queue_init>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...
720B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
736B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
752B		STACKMAP 1, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0]
768B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
784B		%vreg20<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg20
800B		STRXui %XZR, %vreg20<kill>, 5; mem:ST8[%taskgroup] GPR64common:%vreg20
816B		%vreg21<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg21
832B		STRXui %XZR, %vreg21<kill>, 6; mem:ST8[%dependers] GPR64common:%vreg21
848B		%vreg22<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg22
864B		STRXui %XZR, %vreg22<kill>, 7; mem:ST8[%depend_hash] GPR64common:%vreg22
880B		%vreg23<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg23
896B		STRXui %XZR, %vreg23<kill>, 9; mem:ST8[%depend_count] GPR64common:%vreg23
912B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
928B		%X0<def> = COPY %XZR
944B		%X1<def> = COPY %XZR
960B		BL <ga:@check_migrate>, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %SP<imp-def>, ...
976B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
992B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1008B		STACKMAP 2, 0, ...
1024B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1040B		RET_ReallyLR
> %X19<def> = COPY %X2
> %X20<def> = COPY %X1
> %X21<def> = COPY %X0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %XZR
> %X1<def> = COPY %XZR
> BL <ga:@check_migrate>, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %SP<imp-def>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 0, 0, %X20, %X19, %X21, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRXui %X21<kill>, <fi#0>, 0; mem:ST8[%task.addr]
> STRXui %X20<kill>, <fi#1>, 0; mem:ST8[%parent_task.addr]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[%parent_task.addr]
> %X9<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr]
> STRXui %X19<kill>, <fi#2>, 0; mem:ST8[%prev_icv.addr]
> STRXui %X8<kill>, %X9<kill>, 0; mem:ST8[%parent]
> %X8<def> = LDRXui <fi#2>, 0; mem:LD8[%prev_icv.addr]
> %X9<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr]
> %X10<def> = LDRXui %X8, 4; mem:LD8[%5+32]
> STRXui %X10<kill>, %X9, 22; mem:ST8[%4+32]
> %Q0<def> = LDRQui %X8, 1; mem:LD16[%5+16](align=8)
> STRQui %Q0<kill>, %X9, 10; mem:ST16[%4+16](align=8)
> %Q0<def> = LDRQui %X8<kill>, 0; mem:LD16[%5](align=8)
> STRQui %Q0<kill>, %X9<kill>, 9; mem:ST16[%4](align=8)
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr]
> STRWui %WZR, %X8<kill>, 50; mem:ST4[%kind]
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr]
> STRXui %XZR, %X8<kill>, 8; mem:ST8[%taskwait]
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr]
> STRBBui %WZR, %X8<kill>, 204; mem:ST1[%in_tied_task]
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr]
> STRBBui %WZR, %X8<kill>, 205; mem:ST1[%final_task]
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr]
> STRBBui %WZR, %X8<kill>, 206; mem:ST1[%copy_ctors_done]
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr]
> STRBBui %WZR, %X8<kill>, 207; mem:ST1[%parent_depends_on]
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr]
> %X0<def> = ADDXri %X8<kill>, 8, 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BL <ga:@priority_queue_init>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 1, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr]
> STRXui %XZR, %X8<kill>, 5; mem:ST8[%taskgroup]
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr]
> STRXui %XZR, %X8<kill>, 6; mem:ST8[%dependers]
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr]
> STRXui %XZR, %X8<kill>, 7; mem:ST8[%depend_hash]
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr]
> STRXui %XZR, %X8<kill>, 9; mem:ST8[%depend_count]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %XZR
> %X1<def> = COPY %XZR
> BL <ga:@check_migrate>, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %SP<imp-def>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 2, 0, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> RET_ReallyLR
Computing live-in reg-units in ABI blocks.
0B	BB#0 W0#0
Created 1 new intervals.
********** INTERVALS **********
W0 [0B,16r:0)[64r,96r:2)[288r,320r:1)  0@0B-phi 1@288r 2@64r
%vreg0 [16r,192r:0)  0@16r
%vreg1 [48r,304r:0)  0@48r
%vreg2 [208r,224r:0)  0@208r
%vreg3 [240r,256r:0)  0@240r
RegMasks: 96r 320r
********** MACHINEINSTRS **********
# Machine code for function priority_queue_init: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
Function Live Ins: %X0 in %vreg0

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0
16B		%vreg0<def> = COPY %X0; GPR64common:%vreg0
32B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
48B		%vreg1<def> = COPY %XZR; GPR64:%vreg1
64B		%X0<def> = COPY %vreg1; GPR64:%vreg1
80B		%X1<def> = COPY %vreg1; GPR64:%vreg1
96B		BL <ga:@check_migrate>, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %SP<imp-def>, ...
112B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		STACKMAP 0, 0, %vreg0, ...; GPR64common:%vreg0
160B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
176B		STRXui %vreg0, <fi#0>, 0; mem:ST8[%head.addr] GPR64common:%vreg0
192B		STRXui %vreg1, %vreg0, 0; mem:ST8[%root] GPR64:%vreg1 GPR64common:%vreg0
208B		%vreg2<def> = LDRXui <fi#0>, 0; mem:LD8[%head.addr] GPR64common:%vreg2
224B		STRXui %vreg1, %vreg2, 2; mem:ST8[%tasks] GPR64:%vreg1 GPR64common:%vreg2
240B		%vreg3<def> = LDRXui <fi#0>, 0; mem:LD8[%head.addr] GPR64common:%vreg3
256B		STRXui %vreg1, %vreg3, 3; mem:ST8[%last_parent_depends_on] GPR64:%vreg1 GPR64common:%vreg3
272B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
288B		%X0<def> = COPY %vreg1; GPR64:%vreg1
304B		%X1<def> = COPY %vreg1; GPR64:%vreg1
320B		BL <ga:@check_migrate>, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %SP<imp-def>, ...
336B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
352B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
368B		STACKMAP 1, 0, ...
384B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
400B		RET_ReallyLR

# End machine code for function priority_queue_init.

********** SIMPLE REGISTER COALESCING **********
********** Function: priority_queue_init
********** JOINING INTERVALS ***********
entry:
16B	%vreg0<def> = COPY %X0; GPR64common:%vreg0
	Considering merging %vreg0 with %X0
	Can only merge into reserved registers.
48B	%vreg1<def> = COPY %XZR; GPR64:%vreg1
	Considering merging %vreg1 with %XZR
		RHS = %vreg1 [48r,304r:0)  0@48r
		updated: 64B	%X0<def> = COPY %XZR
		updated: 80B	%X1<def> = COPY %XZR
		updated: 192B	STRXui %XZR, %vreg0, 0; mem:ST8[%root] GPR64common:%vreg0
		updated: 224B	STRXui %XZR, %vreg2, 2; mem:ST8[%tasks] GPR64common:%vreg2
		updated: 256B	STRXui %XZR, %vreg3, 3; mem:ST8[%last_parent_depends_on] GPR64common:%vreg3
		updated: 288B	%X0<def> = COPY %XZR
		updated: 304B	%X1<def> = COPY %XZR
	Success: %vreg1 -> %XZR
	Result = %XZR
64B	%X0<def> = COPY %XZR
	Not coalescable.
80B	%X1<def> = COPY %XZR
	Not coalescable.
288B	%X0<def> = COPY %XZR
	Not coalescable.
304B	%X1<def> = COPY %XZR
	Not coalescable.
Trying to inflate 0 regs.
********** INTERVALS **********
WZR EMPTY
W0 [0B,16r:0)[64r,96r:2)[288r,320r:1)  0@0B-phi 1@288r 2@64r
%vreg0 [16r,192r:0)  0@16r
%vreg2 [208r,224r:0)  0@208r
%vreg3 [240r,256r:0)  0@240r
RegMasks: 96r 320r
********** MACHINEINSTRS **********
# Machine code for function priority_queue_init: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
Function Live Ins: %X0 in %vreg0

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0
16B		%vreg0<def> = COPY %X0; GPR64common:%vreg0
32B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
64B		%X0<def> = COPY %XZR
80B		%X1<def> = COPY %XZR
96B		BL <ga:@check_migrate>, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %SP<imp-def>, ...
112B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		STACKMAP 0, 0, %vreg0, ...; GPR64common:%vreg0
160B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
176B		STRXui %vreg0, <fi#0>, 0; mem:ST8[%head.addr] GPR64common:%vreg0
192B		STRXui %XZR, %vreg0, 0; mem:ST8[%root] GPR64common:%vreg0
208B		%vreg2<def> = LDRXui <fi#0>, 0; mem:LD8[%head.addr] GPR64common:%vreg2
224B		STRXui %XZR, %vreg2, 2; mem:ST8[%tasks] GPR64common:%vreg2
240B		%vreg3<def> = LDRXui <fi#0>, 0; mem:LD8[%head.addr] GPR64common:%vreg3
256B		STRXui %XZR, %vreg3, 3; mem:ST8[%last_parent_depends_on] GPR64common:%vreg3
272B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
288B		%X0<def> = COPY %XZR
304B		%X1<def> = COPY %XZR
320B		BL <ga:@check_migrate>, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %SP<imp-def>, ...
336B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
352B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
368B		STACKMAP 1, 0, ...
384B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
400B		RET_ReallyLR

# End machine code for function priority_queue_init.

********** GREEDY REGISTER ALLOCATION **********
********** Function: priority_queue_init
********** INTERVALS **********
WZR EMPTY
W0 [0B,16r:0)[64r,96r:2)[288r,320r:1)  0@0B-phi 1@288r 2@64r
%vreg0 [16r,192r:0)  0@16r
%vreg2 [208r,224r:0)  0@208r
%vreg3 [240r,256r:0)  0@240r
RegMasks: 96r 320r
********** MACHINEINSTRS **********
# Machine code for function priority_queue_init: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
Function Live Ins: %X0 in %vreg0

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0
16B		%vreg0<def> = COPY %X0; GPR64common:%vreg0
32B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
64B		%X0<def> = COPY %XZR
80B		%X1<def> = COPY %XZR
96B		BL <ga:@check_migrate>, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %SP<imp-def>, ...
112B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		STACKMAP 0, 0, %vreg0, ...; GPR64common:%vreg0
160B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
176B		STRXui %vreg0, <fi#0>, 0; mem:ST8[%head.addr] GPR64common:%vreg0
192B		STRXui %XZR, %vreg0, 0; mem:ST8[%root] GPR64common:%vreg0
208B		%vreg2<def> = LDRXui <fi#0>, 0; mem:LD8[%head.addr] GPR64common:%vreg2
224B		STRXui %XZR, %vreg2, 2; mem:ST8[%tasks] GPR64common:%vreg2
240B		%vreg3<def> = LDRXui <fi#0>, 0; mem:LD8[%head.addr] GPR64common:%vreg3
256B		STRXui %XZR, %vreg3, 3; mem:ST8[%last_parent_depends_on] GPR64common:%vreg3
272B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
288B		%X0<def> = COPY %XZR
304B		%X1<def> = COPY %XZR
320B		BL <ga:@check_migrate>, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %SP<imp-def>, ...
336B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
352B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
368B		STACKMAP 1, 0, ...
384B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
400B		RET_ReallyLR

# End machine code for function priority_queue_init.


selectOrSplit GPR64common:%vreg0 [16r,192r:0)  0@16r w=7.013889e-03
hints: %X0
missed hint %X0
assigning %vreg0 to %X19: W19 [16r,192r:0)  0@16r

selectOrSplit GPR64common:%vreg2 [208r,224r:0)  0@208r w=inf
assigning %vreg2 to %X8: W8 [208r,224r:0)  0@208r

selectOrSplit GPR64common:%vreg3 [240r,256r:0)  0@240r w=inf
assigning %vreg3 to %X8: W8 [240r,256r:0)  0@240r

********** STACK TRANSFORMATION METADATA **********
********** Function: priority_queue_init
********** REGISTER MAP **********
[%vreg0 -> %X19] GPR64common
[%vreg2 -> %X8] GPR64common
[%vreg3 -> %X8] GPR64common


*** Stack slot copies ***

Stack slot 0:
  STRXui %vreg0, <fi#0>, 0; mem:ST8[%head.addr] GPR64common:%vreg0
  %vreg2<def> = LDRXui <fi#0>, 0; mem:LD8[%head.addr] GPR64common:%vreg2
  %vreg3<def> = LDRXui <fi#0>, 0; mem:LD8[%head.addr] GPR64common:%vreg3

Stackmap 0:
  STACKMAP 0, 0, %vreg0, ...; GPR64common:%vreg0

%struct.priority_queue* %head: in register %X19 (vreg 0)

Unwinding stackmap back to call site:

  - Skipping   ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
  - Skipping   ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, ...


Unwinding stackmap back to call site:

  - Skipping   ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
  - Skipping   ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>

Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, %vreg0, ...; GPR64common:%vreg0
  -> Call instruction SlotIndex 96B, searching vregs 0 -> 4 and stack slots 0 -> 1

  STACKMAP 1, 0, ...
  -> Call instruction SlotIndex 320B, searching vregs 0 -> 4 and stack slots 0 -> 1

********** REWRITE VIRTUAL REGISTERS **********
********** Function: priority_queue_init
********** REGISTER MAP **********
[%vreg0 -> %X19] GPR64common
[%vreg2 -> %X8] GPR64common
[%vreg3 -> %X8] GPR64common

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0
16B		%vreg0<def> = COPY %X0; GPR64common:%vreg0
32B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
64B		%X0<def> = COPY %XZR
80B		%X1<def> = COPY %XZR
96B		BL <ga:@check_migrate>, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %SP<imp-def>, ...
112B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		STACKMAP 0, 0, %vreg0, ...; GPR64common:%vreg0
160B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
176B		STRXui %vreg0, <fi#0>, 0; mem:ST8[%head.addr] GPR64common:%vreg0
192B		STRXui %XZR, %vreg0<kill>, 0; mem:ST8[%root] GPR64common:%vreg0
208B		%vreg2<def> = LDRXui <fi#0>, 0; mem:LD8[%head.addr] GPR64common:%vreg2
224B		STRXui %XZR, %vreg2<kill>, 2; mem:ST8[%tasks] GPR64common:%vreg2
240B		%vreg3<def> = LDRXui <fi#0>, 0; mem:LD8[%head.addr] GPR64common:%vreg3
256B		STRXui %XZR, %vreg3<kill>, 3; mem:ST8[%last_parent_depends_on] GPR64common:%vreg3
272B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
288B		%X0<def> = COPY %XZR
304B		%X1<def> = COPY %XZR
320B		BL <ga:@check_migrate>, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %SP<imp-def>, ...
336B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
352B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
368B		STACKMAP 1, 0, ...
384B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
400B		RET_ReallyLR
> %X19<def> = COPY %X0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %XZR
> %X1<def> = COPY %XZR
> BL <ga:@check_migrate>, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %SP<imp-def>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 0, 0, %X19, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRXui %X19, <fi#0>, 0; mem:ST8[%head.addr]
> STRXui %XZR, %X19<kill>, 0; mem:ST8[%root]
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[%head.addr]
> STRXui %XZR, %X8<kill>, 2; mem:ST8[%tasks]
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[%head.addr]
> STRXui %XZR, %X8<kill>, 3; mem:ST8[%last_parent_depends_on]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %XZR
> %X1<def> = COPY %XZR
> BL <ga:@check_migrate>, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %SP<imp-def>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 1, 0, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> RET_ReallyLR
Computing live-in reg-units in ABI blocks.
Created 0 new intervals.
********** INTERVALS **********
%vreg0 [32r,528r:0)  0@32r
%vreg1 [256r,288r:0)  0@256r
%vreg2 [288r,336r:0)  0@288r
%vreg3 [432r,448r:0)  0@432r
%vreg4 [448r,480r:0)  0@448r
%vreg5 [464r,480r:0)  0@464r
RegMasks: 80r 176r 352r 544r
********** MACHINEINSTRS **********
# Machine code for function gomp_end_task: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
  fi#1: size=8, align=8, at location [SP]

0B	BB#0: derived from LLVM BB %entry
16B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
32B		%vreg0<def> = COPY %XZR; GPR64all:%vreg0
48B		%X0<def> = COPY %vreg0; GPR64all:%vreg0
64B		%X1<def> = COPY %vreg0; GPR64all:%vreg0
80B		BL <ga:@check_migrate>, <regmask>, %SP<imp-use>, %X0<imp-use,kill>, %X1<imp-use,kill>, %SP<imp-def>, ...
96B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
112B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
128B		STACKMAP 0, 0, ...
144B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
160B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
176B		BL <ga:@gomp_thread>, <regmask>, %SP<imp-use>, %SP<imp-def>, %X0<imp-def>, ...
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
224B		STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack0]
240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
256B		%vreg1<def> = COPY %X0<kill>; GPR64common:%vreg1
272B		STRXui %vreg1, <fi#0>, 0; mem:ST8[%thr] GPR64common:%vreg1
288B		%vreg2<def> = LDRXui %vreg1, 10; mem:LD8[%task1] GPR64:%vreg2 GPR64common:%vreg1
304B		STRXui %vreg2, <fi#1>, 0; mem:ST8[%task] GPR64:%vreg2
320B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
336B		%X0<def> = COPY %vreg2; GPR64:%vreg2
352B		BL <ga:@gomp_finish_task>, <regmask>, %SP<imp-use>, %X0<imp-use,kill>, %SP<imp-def>, ...
368B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
384B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
400B		STACKMAP 2, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack0]
416B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
432B		%vreg3<def> = LDRXui <fi#1>, 0; mem:LD8[%task] GPR64common:%vreg3
448B		%vreg4<def> = LDRXui %vreg3, 0; mem:LD8[%parent] GPR64:%vreg4 GPR64common:%vreg3
464B		%vreg5<def> = LDRXui <fi#0>, 0; mem:LD8[%thr] GPR64common:%vreg5
480B		STRXui %vreg4, %vreg5, 10; mem:ST8[%task2] GPR64:%vreg4 GPR64common:%vreg5
496B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
512B		%X0<def> = COPY %vreg0; GPR64all:%vreg0
528B		%X1<def> = COPY %vreg0; GPR64all:%vreg0
544B		BL <ga:@check_migrate>, <regmask>, %SP<imp-use>, %X0<imp-use,kill>, %X1<imp-use,kill>, %SP<imp-def>, ...
560B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
576B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
592B		STACKMAP 3, 0, ...
608B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
624B		RET_ReallyLR

# End machine code for function gomp_end_task.

********** SIMPLE REGISTER COALESCING **********
********** Function: gomp_end_task
********** JOINING INTERVALS ***********
entry:
32B	%vreg0<def> = COPY %XZR; GPR64all:%vreg0
	Considering merging %vreg0 with %XZR
		RHS = %vreg0 [32r,528r:0)  0@32r
		updated: 48B	%X0<def> = COPY %XZR
		updated: 64B	%X1<def> = COPY %XZR
		updated: 512B	%X0<def> = COPY %XZR
		updated: 528B	%X1<def> = COPY %XZR
	Success: %vreg0 -> %XZR
	Result = %XZR
48B	%X0<def> = COPY %XZR
	Not coalescable.
64B	%X1<def> = COPY %XZR
	Not coalescable.
256B	%vreg1<def> = COPY %X0<kill>; GPR64common:%vreg1
	Considering merging %vreg1 with %X0
	Can only merge into reserved registers.
336B	%X0<def> = COPY %vreg2; GPR64:%vreg2
	Considering merging %vreg2 with %X0
	Can only merge into reserved registers.
512B	%X0<def> = COPY %XZR
	Not coalescable.
528B	%X1<def> = COPY %XZR
	Not coalescable.
Trying to inflate 0 regs.
********** INTERVALS **********
WZR EMPTY
%vreg1 [256r,288r:0)  0@256r
%vreg2 [288r,336r:0)  0@288r
%vreg3 [432r,448r:0)  0@432r
%vreg4 [448r,480r:0)  0@448r
%vreg5 [464r,480r:0)  0@464r
RegMasks: 80r 176r 352r 544r
********** MACHINEINSTRS **********
# Machine code for function gomp_end_task: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
  fi#1: size=8, align=8, at location [SP]

0B	BB#0: derived from LLVM BB %entry
16B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
48B		%X0<def> = COPY %XZR
64B		%X1<def> = COPY %XZR
80B		BL <ga:@check_migrate>, <regmask>, %SP<imp-use>, %X0<imp-use,kill>, %X1<imp-use,kill>, %SP<imp-def>, ...
96B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
112B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
128B		STACKMAP 0, 0, ...
144B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
160B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
176B		BL <ga:@gomp_thread>, <regmask>, %SP<imp-use>, %SP<imp-def>, %X0<imp-def>, ...
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
224B		STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack0]
240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
256B		%vreg1<def> = COPY %X0<kill>; GPR64common:%vreg1
272B		STRXui %vreg1, <fi#0>, 0; mem:ST8[%thr] GPR64common:%vreg1
288B		%vreg2<def> = LDRXui %vreg1, 10; mem:LD8[%task1] GPR64:%vreg2 GPR64common:%vreg1
304B		STRXui %vreg2, <fi#1>, 0; mem:ST8[%task] GPR64:%vreg2
320B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
336B		%X0<def> = COPY %vreg2; GPR64:%vreg2
352B		BL <ga:@gomp_finish_task>, <regmask>, %SP<imp-use>, %X0<imp-use,kill>, %SP<imp-def>, ...
368B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
384B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
400B		STACKMAP 2, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack0]
416B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
432B		%vreg3<def> = LDRXui <fi#1>, 0; mem:LD8[%task] GPR64common:%vreg3
448B		%vreg4<def> = LDRXui %vreg3, 0; mem:LD8[%parent] GPR64:%vreg4 GPR64common:%vreg3
464B		%vreg5<def> = LDRXui <fi#0>, 0; mem:LD8[%thr] GPR64common:%vreg5
480B		STRXui %vreg4, %vreg5, 10; mem:ST8[%task2] GPR64:%vreg4 GPR64common:%vreg5
496B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
512B		%X0<def> = COPY %XZR
528B		%X1<def> = COPY %XZR
544B		BL <ga:@check_migrate>, <regmask>, %SP<imp-use>, %X0<imp-use,kill>, %X1<imp-use,kill>, %SP<imp-def>, ...
560B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
576B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
592B		STACKMAP 3, 0, ...
608B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
624B		RET_ReallyLR

# End machine code for function gomp_end_task.

********** GREEDY REGISTER ALLOCATION **********
********** Function: gomp_end_task
********** INTERVALS **********
WZR EMPTY
%vreg1 [256r,288r:0)  0@256r
%vreg2 [288r,336r:0)  0@288r
%vreg3 [432r,448r:0)  0@432r
%vreg4 [448r,480r:0)  0@448r
%vreg5 [464r,480r:0)  0@464r
RegMasks: 80r 176r 352r 544r
********** MACHINEINSTRS **********
# Machine code for function gomp_end_task: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
  fi#1: size=8, align=8, at location [SP]

0B	BB#0: derived from LLVM BB %entry
16B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
48B		%X0<def> = COPY %XZR
64B		%X1<def> = COPY %XZR
80B		BL <ga:@check_migrate>, <regmask>, %SP<imp-use>, %X0<imp-use,kill>, %X1<imp-use,kill>, %SP<imp-def>, ...
96B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
112B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
128B		STACKMAP 0, 0, ...
144B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
160B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
176B		BL <ga:@gomp_thread>, <regmask>, %SP<imp-use>, %SP<imp-def>, %X0<imp-def>, ...
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
224B		STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack0]
240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
256B		%vreg1<def> = COPY %X0<kill>; GPR64common:%vreg1
272B		STRXui %vreg1, <fi#0>, 0; mem:ST8[%thr] GPR64common:%vreg1
288B		%vreg2<def> = LDRXui %vreg1, 10; mem:LD8[%task1] GPR64:%vreg2 GPR64common:%vreg1
304B		STRXui %vreg2, <fi#1>, 0; mem:ST8[%task] GPR64:%vreg2
320B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
336B		%X0<def> = COPY %vreg2; GPR64:%vreg2
352B		BL <ga:@gomp_finish_task>, <regmask>, %SP<imp-use>, %X0<imp-use,kill>, %SP<imp-def>, ...
368B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
384B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
400B		STACKMAP 2, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack0]
416B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
432B		%vreg3<def> = LDRXui <fi#1>, 0; mem:LD8[%task] GPR64common:%vreg3
448B		%vreg4<def> = LDRXui %vreg3, 0; mem:LD8[%parent] GPR64:%vreg4 GPR64common:%vreg3
464B		%vreg5<def> = LDRXui <fi#0>, 0; mem:LD8[%thr] GPR64common:%vreg5
480B		STRXui %vreg4, %vreg5, 10; mem:ST8[%task2] GPR64:%vreg4 GPR64common:%vreg5
496B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
512B		%X0<def> = COPY %XZR
528B		%X1<def> = COPY %XZR
544B		BL <ga:@check_migrate>, <regmask>, %SP<imp-use>, %X0<imp-use,kill>, %X1<imp-use,kill>, %SP<imp-def>, ...
560B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
576B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
592B		STACKMAP 3, 0, ...
608B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
624B		RET_ReallyLR

# End machine code for function gomp_end_task.


selectOrSplit GPR64common:%vreg1 [256r,288r:0)  0@256r w=7.013889e-03
hints: %X0
assigning %vreg1 to %X0: W0 [256r,288r:0)  0@256r

selectOrSplit GPR64:%vreg2 [288r,336r:0)  0@288r w=6.763393e-03
hints: %X0
assigning %vreg2 to %X0: W0 [288r,336r:0)  0@288r

selectOrSplit GPR64common:%vreg3 [432r,448r:0)  0@432r w=inf
assigning %vreg3 to %X8: W8 [432r,448r:0)  0@432r

selectOrSplit GPR64:%vreg4 [448r,480r:0)  0@448r w=4.629630e-03
assigning %vreg4 to %X8: W8 [448r,480r:0)  0@448r

selectOrSplit GPR64common:%vreg5 [464r,480r:0)  0@464r w=inf
assigning %vreg5 to %X9: W9 [464r,480r:0)  0@464r

********** STACK TRANSFORMATION METADATA **********
********** Function: gomp_end_task
********** REGISTER MAP **********
[%vreg1 -> %X0] GPR64common
[%vreg2 -> %X0] GPR64
[%vreg3 -> %X8] GPR64common
[%vreg4 -> %X8] GPR64
[%vreg5 -> %X9] GPR64common


*** Stack slot copies ***

Stack slot 0:
  STRXui %vreg1, <fi#0>, 0; mem:ST8[%thr] GPR64common:%vreg1
  %vreg5<def> = LDRXui <fi#0>, 0; mem:LD8[%thr] GPR64common:%vreg5
Stack slot 1:
  STRXui %vreg2, <fi#1>, 0; mem:ST8[%task] GPR64:%vreg2
  %vreg3<def> = LDRXui <fi#1>, 0; mem:LD8[%task] GPR64common:%vreg3

Stackmap 0:
  STACKMAP 0, 0, ...


Unwinding stackmap back to call site:

  - Skipping   ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
  - Skipping   ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack0]

%struct.gomp_task** %task: in stack slot 1 (size: 8)
%struct.gomp_thread** %thr: in stack slot 0 (size: 8)

Unwinding stackmap back to call site:

  - Skipping   ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
  - Skipping   ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>

Duplicate operand locations:


Stackmap 2:
  STACKMAP 2, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack0]

%struct.gomp_task** %task: in stack slot 1 (size: 8)
%struct.gomp_thread** %thr: in stack slot 0 (size: 8)

Unwinding stackmap back to call site:

  - Skipping   ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
  - Skipping   ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>

Duplicate operand locations:


Stackmap 3:
  STACKMAP 3, 0, ...


Unwinding stackmap back to call site:

  - Skipping   ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
  - Skipping   ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>

Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, ...
  -> Call instruction SlotIndex 80B, searching vregs 0 -> 6 and stack slots 0 -> 2

  STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack0]
  -> Call instruction SlotIndex 176B, searching vregs 0 -> 6 and stack slots 0 -> 2

  STACKMAP 2, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack0]
  -> Call instruction SlotIndex 352B, searching vregs 0 -> 6 and stack slots 0 -> 2

  STACKMAP 3, 0, ...
  -> Call instruction SlotIndex 544B, searching vregs 0 -> 6 and stack slots 0 -> 2

********** REWRITE VIRTUAL REGISTERS **********
********** Function: gomp_end_task
********** REGISTER MAP **********
[%vreg1 -> %X0] GPR64common
[%vreg2 -> %X0] GPR64
[%vreg3 -> %X8] GPR64common
[%vreg4 -> %X8] GPR64
[%vreg5 -> %X9] GPR64common

0B	BB#0: derived from LLVM BB %entry
16B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
48B		%X0<def> = COPY %XZR
64B		%X1<def> = COPY %XZR
80B		BL <ga:@check_migrate>, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %SP<imp-def>, ...
96B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
112B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
128B		STACKMAP 0, 0, ...
144B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
160B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
176B		BL <ga:@gomp_thread>, <regmask>, %SP<imp-use>, %SP<imp-def>, %X0<imp-def>, ...
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
224B		STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack0]
240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
256B		%vreg1<def> = COPY %X0; GPR64common:%vreg1
272B		STRXui %vreg1, <fi#0>, 0; mem:ST8[%thr] GPR64common:%vreg1
288B		%vreg2<def> = LDRXui %vreg1<kill>, 10; mem:LD8[%task1] GPR64:%vreg2 GPR64common:%vreg1
304B		STRXui %vreg2, <fi#1>, 0; mem:ST8[%task] GPR64:%vreg2
320B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
336B		%X0<def> = COPY %vreg2<kill>; GPR64:%vreg2
352B		BL <ga:@gomp_finish_task>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...
368B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
384B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
400B		STACKMAP 2, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack0]
416B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
432B		%vreg3<def> = LDRXui <fi#1>, 0; mem:LD8[%task] GPR64common:%vreg3
448B		%vreg4<def> = LDRXui %vreg3<kill>, 0; mem:LD8[%parent] GPR64:%vreg4 GPR64common:%vreg3
464B		%vreg5<def> = LDRXui <fi#0>, 0; mem:LD8[%thr] GPR64common:%vreg5
480B		STRXui %vreg4<kill>, %vreg5<kill>, 10; mem:ST8[%task2] GPR64:%vreg4 GPR64common:%vreg5
496B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
512B		%X0<def> = COPY %XZR
528B		%X1<def> = COPY %XZR
544B		BL <ga:@check_migrate>, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %SP<imp-def>, ...
560B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
576B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
592B		STACKMAP 3, 0, ...
608B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
624B		RET_ReallyLR
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %XZR
> %X1<def> = COPY %XZR
> BL <ga:@check_migrate>, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %SP<imp-def>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 0, 0, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> BL <ga:@gomp_thread>, <regmask>, %SP<imp-use>, %SP<imp-def>, %X0<imp-def>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack0]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0
Deleting identity copy.
> STRXui %X0, <fi#0>, 0; mem:ST8[%thr]
> %X0<def> = LDRXui %X0<kill>, 10; mem:LD8[%task1]
> STRXui %X0, <fi#1>, 0; mem:ST8[%task]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BL <ga:@gomp_finish_task>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 2, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack0]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[%task]
> %X8<def> = LDRXui %X8<kill>, 0; mem:LD8[%parent]
> %X9<def> = LDRXui <fi#0>, 0; mem:LD8[%thr]
> STRXui %X8<kill>, %X9<kill>, 10; mem:ST8[%task2]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %XZR
> %X1<def> = COPY %XZR
> BL <ga:@check_migrate>, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %SP<imp-def>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 3, 0, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> RET_ReallyLR
Computing live-in reg-units in ABI blocks.
Created 0 new intervals.
********** INTERVALS **********
%vreg0 [32r,64r:0)  0@32r
%vreg1 [160r,176r:0)  0@160r
%vreg2 [176r,192r:0)  0@176r
%vreg3 [192r,208r:0)  0@192r
RegMasks: 80r
********** MACHINEINSTRS **********
# Machine code for function gomp_thread: Post SSA

0B	BB#0: derived from LLVM BB %entry
16B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
32B		%vreg0<def> = COPY %XZR; GPR64all:%vreg0
48B		%X0<def> = COPY %vreg0; GPR64all:%vreg0
64B		%X1<def> = COPY %vreg0; GPR64all:%vreg0
80B		BL <ga:@check_migrate>, <regmask>, %SP<imp-use>, %X0<imp-use,kill>, %X1<imp-use,kill>, %SP<imp-def>, ...
96B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
112B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
128B		STACKMAP 0, 0, ...
144B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
160B		%vreg1<def> = MRS 56962; GPR64common:%vreg1
176B		%vreg2<def> = ADDXri %vreg1, <ga:@gomp_tls_data>[TF=71], 0; GPR64sp:%vreg2 GPR64common:%vreg1
192B		%vreg3<def> = ADDXri %vreg2, <ga:@gomp_tls_data>[TF=98], 0; GPR64sp:%vreg3,%vreg2
208B		%X0<def> = COPY %vreg3; GPR64sp:%vreg3
224B		RET_ReallyLR %X0<imp-use,kill>

# End machine code for function gomp_thread.

********** SIMPLE REGISTER COALESCING **********
********** Function: gomp_thread
********** JOINING INTERVALS ***********
entry:
32B	%vreg0<def> = COPY %XZR; GPR64all:%vreg0
	Considering merging %vreg0 with %XZR
		RHS = %vreg0 [32r,64r:0)  0@32r
		updated: 48B	%X0<def> = COPY %XZR
		updated: 64B	%X1<def> = COPY %XZR
	Success: %vreg0 -> %XZR
	Result = %XZR
48B	%X0<def> = COPY %XZR
	Not coalescable.
64B	%X1<def> = COPY %XZR
	Not coalescable.
208B	%X0<def> = COPY %vreg3; GPR64sp:%vreg3
	Considering merging %vreg3 with %X0
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
WZR EMPTY
%vreg1 [160r,176r:0)  0@160r
%vreg2 [176r,192r:0)  0@176r
%vreg3 [192r,208r:0)  0@192r
RegMasks: 80r
********** MACHINEINSTRS **********
# Machine code for function gomp_thread: Post SSA

0B	BB#0: derived from LLVM BB %entry
16B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
48B		%X0<def> = COPY %XZR
64B		%X1<def> = COPY %XZR
80B		BL <ga:@check_migrate>, <regmask>, %SP<imp-use>, %X0<imp-use,kill>, %X1<imp-use,kill>, %SP<imp-def>, ...
96B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
112B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
128B		STACKMAP 0, 0, ...
144B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
160B		%vreg1<def> = MRS 56962; GPR64common:%vreg1
176B		%vreg2<def> = ADDXri %vreg1, <ga:@gomp_tls_data>[TF=71], 0; GPR64sp:%vreg2 GPR64common:%vreg1
192B		%vreg3<def> = ADDXri %vreg2, <ga:@gomp_tls_data>[TF=98], 0; GPR64sp:%vreg3,%vreg2
208B		%X0<def> = COPY %vreg3; GPR64sp:%vreg3
224B		RET_ReallyLR %X0<imp-use,kill>

# End machine code for function gomp_thread.

********** GREEDY REGISTER ALLOCATION **********
********** Function: gomp_thread
********** INTERVALS **********
WZR EMPTY
%vreg1 [160r,176r:0)  0@160r
%vreg2 [176r,192r:0)  0@176r
%vreg3 [192r,208r:0)  0@192r
RegMasks: 80r
********** MACHINEINSTRS **********
# Machine code for function gomp_thread: Post SSA

0B	BB#0: derived from LLVM BB %entry
16B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
48B		%X0<def> = COPY %XZR
64B		%X1<def> = COPY %XZR
80B		BL <ga:@check_migrate>, <regmask>, %SP<imp-use>, %X0<imp-use,kill>, %X1<imp-use,kill>, %SP<imp-def>, ...
96B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
112B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
128B		STACKMAP 0, 0, ...
144B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
160B		%vreg1<def> = MRS 56962; GPR64common:%vreg1
176B		%vreg2<def> = ADDXri %vreg1, <ga:@gomp_tls_data>[TF=71], 0; GPR64sp:%vreg2 GPR64common:%vreg1
192B		%vreg3<def> = ADDXri %vreg2, <ga:@gomp_tls_data>[TF=98], 0; GPR64sp:%vreg3,%vreg2
208B		%X0<def> = COPY %vreg3; GPR64sp:%vreg3
224B		RET_ReallyLR %X0<imp-use,kill>

# End machine code for function gomp_thread.


selectOrSplit GPR64sp:%vreg3 [192r,208r:0)  0@192r w=inf
hints: %X0
assigning %vreg3 to %X0: W0 [192r,208r:0)  0@192r

selectOrSplit GPR64common:%vreg1 [160r,176r:0)  0@160r w=inf
assigning %vreg1 to %X8: W8 [160r,176r:0)  0@160r

selectOrSplit GPR64sp:%vreg2 [176r,192r:0)  0@176r w=inf
assigning %vreg2 to %X8: W8 [176r,192r:0)  0@176r

********** STACK TRANSFORMATION METADATA **********
********** Function: gomp_thread
********** REGISTER MAP **********
[%vreg1 -> %X8] GPR64common
[%vreg2 -> %X8] GPR64sp
[%vreg3 -> %X0] GPR64sp


*** Stack slot copies ***


Stackmap 0:
  STACKMAP 0, 0, ...


Unwinding stackmap back to call site:

  - Skipping   ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
  - Skipping   ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>

Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, ...
  -> Call instruction SlotIndex 80B, searching vregs 0 -> 4 and stack slots 0 -> 0

********** REWRITE VIRTUAL REGISTERS **********
********** Function: gomp_thread
********** REGISTER MAP **********
[%vreg1 -> %X8] GPR64common
[%vreg2 -> %X8] GPR64sp
[%vreg3 -> %X0] GPR64sp

0B	BB#0: derived from LLVM BB %entry
16B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
48B		%X0<def> = COPY %XZR
64B		%X1<def> = COPY %XZR
80B		BL <ga:@check_migrate>, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %SP<imp-def>, ...
96B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
112B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
128B		STACKMAP 0, 0, ...
144B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
160B		%vreg1<def> = MRS 56962; GPR64common:%vreg1
176B		%vreg2<def> = ADDXri %vreg1<kill>, <ga:@gomp_tls_data>[TF=71], 0; GPR64sp:%vreg2 GPR64common:%vreg1
192B		%vreg3<def> = ADDXri %vreg2<kill>, <ga:@gomp_tls_data>[TF=98], 0; GPR64sp:%vreg3,%vreg2
208B		%X0<def> = COPY %vreg3<kill>; GPR64sp:%vreg3
224B		RET_ReallyLR %X0<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %XZR
> %X1<def> = COPY %XZR
> BL <ga:@check_migrate>, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %SP<imp-def>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 0, 0, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X8<def> = MRS 56962
> %X8<def> = ADDXri %X8<kill>, <ga:@gomp_tls_data>[TF=71], 0
> %X0<def> = ADDXri %X8<kill>, <ga:@gomp_tls_data>[TF=98], 0
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> RET_ReallyLR %X0<imp-use>
Computing live-in reg-units in ABI blocks.
0B	BB#0 W0#0
Created 1 new intervals.
********** INTERVALS **********
W0 [0B,16r:0)[64r,96r:3)[304r,320r:2)[464r,496r:1)  0@0B-phi 1@464r 2@304r 3@64r
%vreg0 [16r,192r:0)  0@16r
%vreg1 [48r,80r:0)  0@48r
%vreg2 [192r,208r:0)  0@192r
%vreg3 [256r,272r:0)  0@256r
%vreg4 [272r,304r:0)  0@272r
%vreg5 [448r,480r:0)  0@448r
RegMasks: 96r 320r 496r
********** MACHINEINSTRS **********
# Machine code for function gomp_finish_task: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
Function Live Ins: %X0 in %vreg0

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0
16B		%vreg0<def> = COPY %X0; GPR64common:%vreg0
32B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
48B		%vreg1<def> = COPY %XZR; GPR64all:%vreg1
64B		%X0<def> = COPY %vreg1; GPR64all:%vreg1
80B		%X1<def> = COPY %vreg1; GPR64all:%vreg1
96B		BL <ga:@check_migrate>, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %SP<imp-def>, ...
112B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		STACKMAP 0, 0, %vreg0, ...; GPR64common:%vreg0
160B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
176B		STRXui %vreg0, <fi#0>, 0; mem:ST8[%task.addr] GPR64common:%vreg0
192B		%vreg2<def> = LDRXui %vreg0, 7; mem:LD8[%depend_hash] GPR64:%vreg2 GPR64common:%vreg0
208B		CBZX %vreg2, <BB#2>; GPR64:%vreg2
224B		B <BB#1>
	    Successors according to CFG: BB#1 BB#2

240B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
256B		%vreg3<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg3
272B		%vreg4<def> = LDRXui %vreg3, 7; mem:LD8[%depend_hash2] GPR64:%vreg4 GPR64common:%vreg3
288B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
304B		%X0<def> = COPY %vreg4; GPR64:%vreg4
320B		BL <ga:@free>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...
336B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
352B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
368B		STACKMAP 1, 0, ...
384B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
400B		B <BB#2>
	    Successors according to CFG: BB#2

416B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#1
432B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
448B		%vreg5<def> = COPY %XZR; GPR64all:%vreg5
464B		%X0<def> = COPY %vreg5; GPR64all:%vreg5
480B		%X1<def> = COPY %vreg5; GPR64all:%vreg5
496B		BL <ga:@check_migrate>, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %SP<imp-def>, ...
512B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
528B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
544B		STACKMAP 2, 0, ...
560B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
576B		RET_ReallyLR

# End machine code for function gomp_finish_task.

********** SIMPLE REGISTER COALESCING **********
********** Function: gomp_finish_task
********** JOINING INTERVALS ***********
entry:
16B	%vreg0<def> = COPY %X0; GPR64common:%vreg0
	Considering merging %vreg0 with %X0
	Can only merge into reserved registers.
48B	%vreg1<def> = COPY %XZR; GPR64all:%vreg1
	Considering merging %vreg1 with %XZR
		RHS = %vreg1 [48r,80r:0)  0@48r
		updated: 64B	%X0<def> = COPY %XZR
		updated: 80B	%X1<def> = COPY %XZR
	Success: %vreg1 -> %XZR
	Result = %XZR
64B	%X0<def> = COPY %XZR
	Not coalescable.
80B	%X1<def> = COPY %XZR
	Not coalescable.
if.then:
304B	%X0<def> = COPY %vreg4; GPR64:%vreg4
	Considering merging %vreg4 with %X0
	Can only merge into reserved registers.
if.end:
448B	%vreg5<def> = COPY %XZR; GPR64all:%vreg5
	Considering merging %vreg5 with %XZR
		RHS = %vreg5 [448r,480r:0)  0@448r
		updated: 464B	%X0<def> = COPY %XZR
		updated: 480B	%X1<def> = COPY %XZR
	Success: %vreg5 -> %XZR
	Result = %XZR
464B	%X0<def> = COPY %XZR
	Not coalescable.
480B	%X1<def> = COPY %XZR
	Not coalescable.
Trying to inflate 0 regs.
********** INTERVALS **********
WZR EMPTY
W0 [0B,16r:0)[64r,96r:3)[304r,320r:2)[464r,496r:1)  0@0B-phi 1@464r 2@304r 3@64r
%vreg0 [16r,192r:0)  0@16r
%vreg2 [192r,208r:0)  0@192r
%vreg3 [256r,272r:0)  0@256r
%vreg4 [272r,304r:0)  0@272r
RegMasks: 96r 320r 496r
********** MACHINEINSTRS **********
# Machine code for function gomp_finish_task: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
Function Live Ins: %X0 in %vreg0

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0
16B		%vreg0<def> = COPY %X0; GPR64common:%vreg0
32B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
64B		%X0<def> = COPY %XZR
80B		%X1<def> = COPY %XZR
96B		BL <ga:@check_migrate>, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %SP<imp-def>, ...
112B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		STACKMAP 0, 0, %vreg0, ...; GPR64common:%vreg0
160B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
176B		STRXui %vreg0, <fi#0>, 0; mem:ST8[%task.addr] GPR64common:%vreg0
192B		%vreg2<def> = LDRXui %vreg0, 7; mem:LD8[%depend_hash] GPR64:%vreg2 GPR64common:%vreg0
208B		CBZX %vreg2, <BB#2>; GPR64:%vreg2
224B		B <BB#1>
	    Successors according to CFG: BB#1 BB#2

240B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
256B		%vreg3<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg3
272B		%vreg4<def> = LDRXui %vreg3, 7; mem:LD8[%depend_hash2] GPR64:%vreg4 GPR64common:%vreg3
288B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
304B		%X0<def> = COPY %vreg4; GPR64:%vreg4
320B		BL <ga:@free>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...
336B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
352B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
368B		STACKMAP 1, 0, ...
384B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
400B		B <BB#2>
	    Successors according to CFG: BB#2

416B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#1
432B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
464B		%X0<def> = COPY %XZR
480B		%X1<def> = COPY %XZR
496B		BL <ga:@check_migrate>, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %SP<imp-def>, ...
512B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
528B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
544B		STACKMAP 2, 0, ...
560B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
576B		RET_ReallyLR

# End machine code for function gomp_finish_task.

********** GREEDY REGISTER ALLOCATION **********
********** Function: gomp_finish_task
********** INTERVALS **********
WZR EMPTY
W0 [0B,16r:0)[64r,96r:3)[304r,320r:2)[464r,496r:1)  0@0B-phi 1@464r 2@304r 3@64r
%vreg0 [16r,192r:0)  0@16r
%vreg2 [192r,208r:0)  0@192r
%vreg3 [256r,272r:0)  0@256r
%vreg4 [272r,304r:0)  0@272r
RegMasks: 96r 320r 496r
********** MACHINEINSTRS **********
# Machine code for function gomp_finish_task: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
Function Live Ins: %X0 in %vreg0

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0
16B		%vreg0<def> = COPY %X0; GPR64common:%vreg0
32B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
64B		%X0<def> = COPY %XZR
80B		%X1<def> = COPY %XZR
96B		BL <ga:@check_migrate>, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %SP<imp-def>, ...
112B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		STACKMAP 0, 0, %vreg0, ...; GPR64common:%vreg0
160B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
176B		STRXui %vreg0, <fi#0>, 0; mem:ST8[%task.addr] GPR64common:%vreg0
192B		%vreg2<def> = LDRXui %vreg0, 7; mem:LD8[%depend_hash] GPR64:%vreg2 GPR64common:%vreg0
208B		CBZX %vreg2, <BB#2>; GPR64:%vreg2
224B		B <BB#1>
	    Successors according to CFG: BB#1 BB#2

240B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
256B		%vreg3<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg3
272B		%vreg4<def> = LDRXui %vreg3, 7; mem:LD8[%depend_hash2] GPR64:%vreg4 GPR64common:%vreg3
288B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
304B		%X0<def> = COPY %vreg4; GPR64:%vreg4
320B		BL <ga:@free>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...
336B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
352B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
368B		STACKMAP 1, 0, ...
384B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
400B		B <BB#2>
	    Successors according to CFG: BB#2

416B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#1
432B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
464B		%X0<def> = COPY %XZR
480B		%X1<def> = COPY %XZR
496B		BL <ga:@check_migrate>, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %SP<imp-def>, ...
512B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
528B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
544B		STACKMAP 2, 0, ...
560B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
576B		RET_ReallyLR

# End machine code for function gomp_finish_task.


selectOrSplit GPR64common:%vreg0 [16r,192r:0)  0@16r w=7.013889e-03
hints: %X0
missed hint %X0
assigning %vreg0 to %X19: W19 [16r,192r:0)  0@16r

selectOrSplit GPR64:%vreg4 [272r,304r:0)  0@272r w=2.337963e-03
hints: %X0
assigning %vreg4 to %X0: W0 [272r,304r:0)  0@272r

selectOrSplit GPR64:%vreg2 [192r,208r:0)  0@192r w=inf
assigning %vreg2 to %X8: W8 [192r,208r:0)  0@192r

selectOrSplit GPR64common:%vreg3 [256r,272r:0)  0@256r w=inf
assigning %vreg3 to %X8: W8 [256r,272r:0)  0@256r

********** STACK TRANSFORMATION METADATA **********
********** Function: gomp_finish_task
********** REGISTER MAP **********
[%vreg0 -> %X19] GPR64common
[%vreg2 -> %X8] GPR64
[%vreg3 -> %X8] GPR64common
[%vreg4 -> %X0] GPR64


*** Stack slot copies ***

Stack slot 0:
  STRXui %vreg0, <fi#0>, 0; mem:ST8[%task.addr] GPR64common:%vreg0
  %vreg3<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg3

Stackmap 0:
  STACKMAP 0, 0, %vreg0, ...; GPR64common:%vreg0

%struct.gomp_task* %task: in register %X19 (vreg 0)

Unwinding stackmap back to call site:

  - Skipping   ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
  - Skipping   ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, ...


Unwinding stackmap back to call site:

  - Skipping   ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
  - Skipping   ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>

Duplicate operand locations:


Stackmap 2:
  STACKMAP 2, 0, ...


Unwinding stackmap back to call site:

  - Skipping   ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
  - Skipping   ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>

Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, %vreg0, ...; GPR64common:%vreg0
  -> Call instruction SlotIndex 96B, searching vregs 0 -> 6 and stack slots 0 -> 1

  STACKMAP 1, 0, ...
  -> Call instruction SlotIndex 320B, searching vregs 0 -> 6 and stack slots 0 -> 1

  STACKMAP 2, 0, ...
  -> Call instruction SlotIndex 496B, searching vregs 0 -> 6 and stack slots 0 -> 1

********** REWRITE VIRTUAL REGISTERS **********
********** Function: gomp_finish_task
********** REGISTER MAP **********
[%vreg0 -> %X19] GPR64common
[%vreg2 -> %X8] GPR64
[%vreg3 -> %X8] GPR64common
[%vreg4 -> %X0] GPR64

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0
16B		%vreg0<def> = COPY %X0; GPR64common:%vreg0
32B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
64B		%X0<def> = COPY %XZR
80B		%X1<def> = COPY %XZR
96B		BL <ga:@check_migrate>, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %SP<imp-def>, ...
112B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		STACKMAP 0, 0, %vreg0, ...; GPR64common:%vreg0
160B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
176B		STRXui %vreg0, <fi#0>, 0; mem:ST8[%task.addr] GPR64common:%vreg0
192B		%vreg2<def> = LDRXui %vreg0<kill>, 7; mem:LD8[%depend_hash] GPR64:%vreg2 GPR64common:%vreg0
208B		CBZX %vreg2<kill>, <BB#2>; GPR64:%vreg2
224B		B <BB#1>
	    Successors according to CFG: BB#1 BB#2
> %X19<def> = COPY %X0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %XZR
> %X1<def> = COPY %XZR
> BL <ga:@check_migrate>, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %SP<imp-def>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 0, 0, %X19, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRXui %X19, <fi#0>, 0; mem:ST8[%task.addr]
> %X8<def> = LDRXui %X19<kill>, 7; mem:LD8[%depend_hash]
> CBZX %X8<kill>, <BB#2>
> B <BB#1>
240B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
256B		%vreg3<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr] GPR64common:%vreg3
272B		%vreg4<def> = LDRXui %vreg3<kill>, 7; mem:LD8[%depend_hash2] GPR64:%vreg4 GPR64common:%vreg3
288B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
304B		%X0<def> = COPY %vreg4<kill>; GPR64:%vreg4
320B		BL <ga:@free>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...
336B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
352B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
368B		STACKMAP 1, 0, ...
384B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
400B		B <BB#2>
	    Successors according to CFG: BB#2
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[%task.addr]
> %X0<def> = LDRXui %X8<kill>, 7; mem:LD8[%depend_hash2]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BL <ga:@free>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 1, 0, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> B <BB#2>
416B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#1
432B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
464B		%X0<def> = COPY %XZR
480B		%X1<def> = COPY %XZR
496B		BL <ga:@check_migrate>, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %SP<imp-def>, ...
512B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
528B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
544B		STACKMAP 2, 0, ...
560B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
576B		RET_ReallyLR
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %XZR
> %X1<def> = COPY %XZR
> BL <ga:@check_migrate>, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %SP<imp-def>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 2, 0, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> RET_ReallyLR
Computing live-in reg-units in ABI blocks.
0B	BB#0 W0#0 W1#0 W2#0 W3#0 W4#0 W5#0 W6#0 W7#0
Created 8 new intervals.
********** INTERVALS **********
W0 [0B,128r:0)[208r,240r:38)[480r,560r:37)[720r,736r:36)[736r,816r:8)[2176r,2192r:19)[2368r,2384r:2)[2384r,2464r:18)[2512r,2560r:17)[3792r,3824r:15)[3952r,3968r:14)[4160r,4176r:16)[4352r,4384r:13)[4384r,4464r:1)[4576r,4592r:12)[4720r,4736r:11)[4864r,4880r:10)[5536r,5552r:35)[5552r,5632r:34)[5856r,5872r:7)[5872r,5952r:33)[5984r,6032r:32)[6512r,6544r:30)[6768r,6816r:31)[7184r,7200r:29)[7328r,7344r:28)[7344r,7424r:6)[7952r,7968r:22)[8080r,8096r:21)[8208r,8224r:20)[8624r,8672r:27)[8880r,8896r:23)[9184r,9296r:5)[9584r,9696r:4)[9952r,10064r:3)[10320r,10336r:26)[10640r,10656r:25)[10864r,10896r:24)[11072r,11104r:9)  0@0B-phi 1@4384r 2@2368r 3@9952r 4@9584r 5@9184r 6@7344r 7@5856r 8@736r 9@11072r 10@4864r 11@4720r 12@4576r 13@4352r 14@3952r 15@3792r 16@4160r 17@2512r 18@2384r 19@2176r 20@8208r 21@8080r 22@7952r 23@8880r 24@10864r 25@10640r 26@10320r 27@8624r 28@7328r 29@7184r 30@6512r 31@6768r 32@5984r 33@5872r 34@5552r 35@5536r 36@720r 37@480r 38@208r
W1 [0B,112r:0)[224r,240r:13)[2528r,2560r:5)[3808r,3824r:4)[4368r,4384r:1)[6000r,6032r:12)[6528r,6544r:10)[6784r,6816r:11)[8640r,8672r:9)[9200r,9296r:8)[9600r,9696r:7)[9968r,10064r:6)[10880r,10896r:2)[11088r,11104r:3)  0@0B-phi 1@4368r 2@10880r 3@11088r 4@3808r 5@2528r 6@9968r 7@9600r 8@9200r 9@8640r 10@6528r 11@6784r 12@6000r 13@224r
W2 [0B,96r:0)[2544r,2560r:1)[6016r,6032r:7)[6800r,6816r:6)[8656r,8672r:5)[9216r,9296r:4)[9616r,9696r:3)[9984r,10064r:2)  0@0B-phi 1@2544r 2@9984r 3@9616r 4@9216r 5@8656r 6@6800r 7@6016r
W3 [0B,80r:0)[9232r,9296r:3)[9632r,9696r:2)[10000r,10064r:1)  0@0B-phi 1@10000r 2@9632r 3@9232r
W4 [0B,64r:0)[9248r,9296r:3)[9648r,9696r:2)[10016r,10064r:1)  0@0B-phi 1@10016r 2@9648r 3@9248r
W5 [0B,48r:0)[9264r,9296r:3)[9664r,9696r:2)[10032r,10064r:1)  0@0B-phi 1@10032r 2@9664r 3@9264r
W6 [0B,32r:0)[9280r,9296r:3)[9680r,9696r:2)[10048r,10064r:1)  0@0B-phi 1@10048r 2@9680r 3@9280r
W7 [0B,16r:0)  0@0B-phi
%vreg0 [2944r,2960r:0)  0@2944r
%vreg1 [3008r,3024r:0)  0@3008r
%vreg2 [7776r,7792r:0)  0@7776r
%vreg3 [7840r,7856r:0)  0@7840r
%vreg4 [128r,320r:0)  0@128r
%vreg5 [112r,336r:0)  0@112r
%vreg6 [96r,352r:0)  0@96r
%vreg7 [80r,368r:0)  0@80r
%vreg8 [64r,384r:0)  0@64r
%vreg9 [48r,176r:0)  0@48r
%vreg10 [32r,416r:0)  0@32r
%vreg11 [16r,432r:0)  0@16r
%vreg12 [144r,448r:0)  0@144r
%vreg13 [176r,400r:0)  0@176r
%vreg14 [192r,224r:0)  0@192r
%vreg15 [560r,592r:0)  0@560r
%vreg16 [592r,624r:0)  0@592r
%vreg17 [672r,688r:0)  0@672r
%vreg18 [688r,720r:0)  0@688r
%vreg19 [816r,832r:0)  0@816r
%vreg20 [880r,896r:0)  0@880r
%vreg21 [896r,912r:0)  0@896r
%vreg22 [912r,928r:0)  0@912r
%vreg23 [976r,992r:0)  0@976r
%vreg24 [992r,1008r:0)  0@992r
%vreg25 [1008r,1024r:0)  0@1008r
%vreg26 [1024r,1040r:0)  0@1024r
%vreg27 [1120r,1136r:0)  0@1120r
%vreg28 [1248r,1296r:0)  0@1248r
%vreg29 [1264r,1280r:0)  0@1264r
%vreg30 [1280r,1296r:0)  0@1280r
%vreg31 [1296r,1296d:0)  0@1296r
%vreg32 [1360r,1376r:0)  0@1360r
%vreg33 [1376r,1392r:0)  0@1376r
%vreg34 [1184r,1200r:0)  0@1184r
%vreg35 [1472r,1488r:0)  0@1472r
%vreg36 [1536r,1552r:0)  0@1536r
%vreg37 [1600r,1616r:0)  0@1600r
%vreg38 [1616r,1632r:0)  0@1616r
%vreg39 [1680r,1696r:0)  0@1680r
%vreg40 [1696r,1712r:0)  0@1696r
%vreg41 [1712r,1728r:0)  0@1712r
%vreg42 [1728r,1744r:0)  0@1728r
%vreg43 [1792r,1824r:0)  0@1792r
%vreg44 [1808r,1840r:0)  0@1808r
%vreg45 [1824r,1840r:0)  0@1824r
%vreg46 [1840r,1840d:0)  0@1840r
%vreg47 [5120r,5136r:0)  0@5120r
%vreg48 [5136r,5168r:0)  0@5136r
%vreg49 [5168r,5184r:0)  0@5168r
%vreg50 [5200r,5216r:0)  0@5200r
%vreg51 [5232r,5248r:0)  0@5232r
%vreg52 [5296r,5312r:0)  0@5296r
%vreg53 [5312r,5360r:0)  0@5312r
%vreg54 [5328r,5344r:0)  0@5328r
%vreg55 [5344r,5360r:0)  0@5344r
%vreg56 [5360r,5376r:0)  0@5360r
%vreg57 [5424r,5456r:0)  0@5424r
%vreg58 [5440r,5456r:0)  0@5440r
%vreg59 [5456r,5488r:0)  0@5456r
%vreg60 [5472r,5488r:0)  0@5472r
%vreg61 [5488r,5504r:0)  0@5488r
%vreg62 [5504r,5536r:0)  0@5504r
%vreg63 [5632r,5680r:0)  0@5632r
%vreg64 [5664r,5680r:0)  0@5664r
%vreg65 [5680r,5712r:0)  0@5680r
%vreg66 [5696r,5744r:0)  0@5696r
%vreg67 [5712r,5728r:0)  0@5712r
%vreg68 [5728r,5760r:0)  0@5728r
%vreg69 [5744r,5760r:0)  0@5744r
%vreg70 [5760r,5776r:0)  0@5760r
%vreg71 [5792r,5984r:0)  0@5792r
%vreg72 [5808r,6000r:0)  0@5808r
%vreg73 [5840r,5856r:0)  0@5840r
%vreg74 [5952r,6016r:0)  0@5952r
%vreg75 [6112r,6144r:0)  0@6112r
%vreg76 [6128r,6144r:0)  0@6128r
%vreg77 [6160r,6192r:0)  0@6160r
%vreg78 [6176r,6192r:0)  0@6176r
%vreg79 [6208r,6224r:0)  0@6208r
%vreg80 [6224r,6256r:0)  0@6224r
%vreg81 [6240r,6272r:0)  0@6240r
%vreg82 [6256r,6272r:0)  0@6256r
%vreg83 [6288r,6320r:0)  0@6288r
%vreg84 [6304r,6320r:0)  0@6304r
%vreg85 [6336r,6368r:0)  0@6336r
%vreg86 [6352r,6368r:0)  0@6352r
%vreg87 [6384r,6400r:0)  0@6384r
%vreg88 [6704r,6768r:0)  0@6704r
%vreg89 [6720r,6784r:0)  0@6720r
%vreg90 [6736r,6800r:0)  0@6736r
%vreg91 [6448r,6544r:0)  0@6448r
%vreg92 [6464r,6512r:0)  0@6464r
%vreg93 [6480r,6528r:0)  0@6480r
%vreg94 [6624r,6656r:0)  0@6624r
%vreg95 [6640r,6656r:0)  0@6640r
%vreg96 [6880r,6912r:0)  0@6880r
%vreg97 [6896r,6912r:0)  0@6896r
%vreg98 [6928r,6960r:0)  0@6928r
%vreg99 [6944r,6960r:0)  0@6944r
%vreg100 [6976r,7008r:0)  0@6976r
%vreg101 [6992r,7008r:0)  0@6992r
%vreg102 [7024r,7056r:0)  0@7024r
%vreg103 [7040r,7056r:0)  0@7040r
%vreg104 [7072r,7088r:0)  0@7072r
%vreg105 [7088r,7120r:0)  0@7088r
%vreg106 [7104r,7120r:0)  0@7104r
%vreg107 [7136r,7152r:0)  0@7136r
%vreg108 [7152r,7184r:0)  0@7152r
%vreg109 [7280r,7296r:0)  0@7280r
%vreg110 [7296r,7328r:0)  0@7296r
%vreg111 [7424r,7440r:0)  0@7424r
%vreg112 [7520r,7536r:0)  0@7520r
%vreg113 [7488r,7552r:0)  0@7488r
%vreg114 [7504r,7520r:0)  0@7504r
%vreg115 [7648r,7664r:0)  0@7648r
%vreg116 [7600r,7616r:0)  0@7600r
%vreg117 [7616r,7680r:0)  0@7616r
%vreg118 [7632r,7648r:0)  0@7632r
%vreg119 [7728r,7744r:0)  0@7728r
%vreg120 [7744r,7760r:0)  0@7744r
%vreg121 [7760r,7776r:0)  0@7760r
%vreg122 [8336r,8352r:0)  0@8336r
%vreg123 [8400r,8448r:0)  0@8400r
%vreg124 [8416r,8432r:0)  0@8416r
%vreg125 [8432r,8448r:0)  0@8432r
%vreg126 [8496r,8512r:0)  0@8496r
%vreg127 [8560r,8624r:0)  0@8560r
%vreg128 [8576r,8640r:0)  0@8576r
%vreg129 [8592r,8656r:0)  0@8592r
%vreg130 [8752r,8768r:0)  0@8752r
%vreg131 [8768r,8784r:0)  0@8768r
%vreg132 [9040r,9056r:0)  0@9040r
%vreg133 [9056r,9200r:0)  0@9056r
%vreg134 [9072r,9216r:0)  0@9072r
%vreg135 [9088r,9232r:0)  0@9088r
%vreg136 [9104r,9136r:0)  0@9104r
%vreg137 [9136r,9280r:0)  0@9136r
%vreg138 [9152r,9184r:0)  0@9152r
%vreg139 [9168r,9264r:0)  0@9168r
%vreg140 [9376r,9392r:0)  0@9376r
%vreg141 [9440r,9456r:0)  0@9440r
%vreg142 [9456r,9600r:0)  0@9456r
%vreg143 [9472r,9616r:0)  0@9472r
%vreg144 [9488r,9632r:0)  0@9488r
%vreg145 [9504r,9536r:0)  0@9504r
%vreg146 [9536r,9680r:0)  0@9536r
%vreg147 [9552r,9584r:0)  0@9552r
%vreg148 [9568r,9664r:0)  0@9568r
%vreg149 [9808r,9824r:0)  0@9808r
%vreg150 [9824r,9968r:0)  0@9824r
%vreg151 [9840r,9984r:0)  0@9840r
%vreg152 [9856r,10000r:0)  0@9856r
%vreg153 [9872r,9904r:0)  0@9872r
%vreg154 [9904r,10048r:0)  0@9904r
%vreg155 [9920r,10016r:0)  0@9920r
%vreg156 [9936r,10032r:0)  0@9936r
%vreg157 [10144r,10192r:0)  0@10144r
%vreg158 [10160r,10176r:0)  0@10160r
%vreg159 [10176r,10192r:0)  0@10176r
%vreg160 [10208r,10256r:0)  0@10208r
%vreg161 [10224r,10240r:0)  0@10224r
%vreg162 [10240r,10256r:0)  0@10240r
%vreg163 [10272r,10288r:0)  0@10272r
%vreg164 [10288r,10320r:0)  0@10288r
%vreg165 [10416r,10528r:0)  0@10416r
%vreg166 [10432r,10512r:0)  0@10432r
%vreg167 [10448r,10464r:0)  0@10448r
%vreg168 [10464r,10480r:0)  0@10464r
%vreg169 [10480r,10496r:0)  0@10480r
%vreg170 [10496r,10512r:0)  0@10496r
%vreg171 [10512r,10544r:0)  0@10512r
%vreg172 [10528r,10544r:0)  0@10528r
%vreg173 [10544r,10544d:0)  0@10544r
%vreg174 [10560r,10576r:0)  0@10560r
%vreg175 [10592r,10608r:0)  0@10592r
%vreg176 [10608r,10640r:0)  0@10608r
%vreg177 [10736r,10752r:0)  0@10736r
%vreg178 [10800r,10816r:0)  0@10800r
%vreg179 [10816r,10864r:0)  0@10816r
%vreg180 [10848r,10880r:0)  0@10848r
%vreg181 [8832r,8848r:0)  0@8832r
%vreg182 [8848r,8880r:0)  0@8848r
%vreg183 [7904r,7920r:0)  0@7904r
%vreg184 [7920r,7952r:0)  0@7920r
%vreg185 [8048r,8080r:0)  0@8048r
%vreg186 [8176r,8208r:0)  0@8176r
%vreg187 [1904r,1920r:0)  0@1904r
%vreg188 [1968r,1984r:0)  0@1968r
%vreg189 [1984r,2000r:0)  0@1984r
%vreg190 [2048r,2064r:0)  0@2048r
%vreg191 [2064r,2080r:0)  0@2064r
%vreg192 [2080r,2096r:0)  0@2080r
%vreg193 [2144r,2176r:0)  0@2144r
%vreg194 [2304r,2320r:0)  0@2304r
%vreg195 [2320r,2528r:0)  0@2320r
%vreg196 [2352r,2368r:0)  0@2352r
%vreg197 [2464r,2544r:0)  0@2464r
%vreg198 [2496r,2512r:0)  0@2496r
%vreg199 [2640r,2656r:0)  0@2640r
%vreg200 [2672r,2688r:0)  0@2672r
%vreg201 [2688r,2704r:0)  0@2688r
%vreg202 [2832r,2848r:0)  0@2832r
%vreg203 [2752r,2768r:0)  0@2752r
%vreg204 [2768r,2784r:0)  0@2768r
%vreg205 [2784r,2800r:0)  0@2784r
%vreg206 [2800r,2864r:0)  0@2800r
%vreg207 [2816r,2832r:0)  0@2816r
%vreg208 [2912r,2928r:0)  0@2912r
%vreg209 [2928r,2944r:0)  0@2928r
%vreg210 [3024r,3040r:0)  0@3024r
%vreg211 [3056r,3072r:0)  0@3056r
%vreg212 [3088r,3104r:0)  0@3088r
%vreg213 [3104r,3120r:0)  0@3104r
%vreg214 [3168r,3184r:0)  0@3168r
%vreg215 [3184r,3200r:0)  0@3184r
%vreg216 [3200r,3216r:0)  0@3200r
%vreg217 [3216r,3232r:0)  0@3216r
%vreg218 [3248r,3264r:0)  0@3248r
%vreg219 [3264r,3280r:0)  0@3264r
%vreg220 [3280r,3296r:0)  0@3280r
%vreg221 [3344r,3376r:0)  0@3344r
%vreg222 [3360r,3376r:0)  0@3360r
%vreg223 [3392r,3408r:0)  0@3392r
%vreg224 [4112r,4176r:0)  0@4112r
%vreg225 [4128r,4160r:0)  0@4128r
%vreg226 [3456r,3488r:0)  0@3456r
%vreg227 [3472r,3488r:0)  0@3472r
%vreg228 [3488r,3536r:0)  0@3488r
%vreg229 [3504r,3520r:0)  0@3504r
%vreg230 [3536r,3552r:0)  0@3536r
%vreg231 [3552r,3600r:0)  0@3552r
%vreg232 [3584r,3600r:0)  0@3584r
%vreg233 [3600r,3664r:0)  0@3600r
%vreg234 [3648r,3696r:0)  0@3648r
%vreg235 [3664r,3680r:0)  0@3664r
%vreg236 [3680r,3712r:0)  0@3680r
%vreg237 [3696r,3712r:0)  0@3696r
%vreg238 [3712r,3792r:0)  0@3712r
%vreg239 [3744r,3824r:0)  0@3744r
%vreg240 [3760r,3808r:0)  0@3760r
%vreg241 [3904r,3968r:0)  0@3904r
%vreg242 [3920r,3952r:0)  0@3920r
%vreg243 [4048r,4064r:0)  0@4048r
%vreg244 [4288r,4304r:0)  0@4288r
%vreg245 [4304r,4352r:0)  0@4304r
%vreg246 [4336r,4368r:0)  0@4336r
%vreg247 [4464r,4480r:0)  0@4464r
%vreg248 [4528r,4544r:0)  0@4528r
%vreg249 [4544r,4576r:0)  0@4544r
%vreg250 [4672r,4688r:0)  0@4672r
%vreg251 [4688r,4720r:0)  0@4688r
%vreg252 [4816r,4832r:0)  0@4816r
%vreg253 [4832r,4864r:0)  0@4832r
%vreg254 [11056r,11088r:0)  0@11056r
%vreg255 [2848r,2896B:0)[2960r,2992B:1)[2992B,3008r:2)  0@2848r 1@2960r 2@2992B-phi
%vreg256 [7536r,7584B:0)[7664r,7712B:1)[7792r,7824B:2)[7824B,7840r:3)  0@7536r 1@7664r 2@7792r 3@7824B-phi
RegMasks: 240r 480r 736r 2192r 2384r 2560r 3824r 3968r 4176r 4384r 4592r 4736r 4880r 5008r 5552r 5872r 6032r 6544r 6816r 7200r 7344r 7968r 8096r 8224r 8672r 8896r 9296r 9696r 10064r 10336r 10656r 10896r 11104r
********** MACHINEINSTRS **********
# Machine code for function GOMP_task: Post SSA
Frame Objects:
  fi#-1: size=4, align=16, fixed, at location [SP]
  fi#0: size=8, align=8, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=8, align=8, at location [SP]
  fi#3: size=8, align=8, at location [SP]
  fi#4: size=8, align=8, at location [SP]
  fi#5: size=1, align=1, at location [SP]
  fi#6: size=4, align=4, at location [SP]
  fi#7: size=8, align=8, at location [SP]
  fi#8: size=4, align=4, at location [SP]
  fi#9: size=8, align=8, at location [SP]
  fi#10: size=8, align=8, at location [SP]
  fi#11: size=208, align=8, at location [SP]
  fi#12: size=8, align=8, at location [SP]
  fi#13: size=8, align=8, at location [SP]
  fi#14: size=8, align=8, at location [SP]
  fi#15: size=8, align=8, at location [SP]
  fi#16: size=8, align=8, at location [SP]
  fi#17: size=8, align=8, at location [SP]
  fi#18: size=1, align=1, at location [SP]
  fi#19: size=8, align=8, at location [SP]
  fi#20: variable sized, align=1, at location [SP]
Function Live Ins: %X0 in %vreg4, %X1 in %vreg5, %X2 in %vreg6, %X3 in %vreg7, %X4 in %vreg8, %W5 in %vreg9, %W6 in %vreg10, %X7 in %vreg11

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %X1 %X2 %X3 %X4 %W5 %W6 %X7
16B		%vreg11<def> = COPY %X7; GPR64:%vreg11
32B		%vreg10<def> = COPY %W6; GPR32:%vreg10
48B		%vreg9<def> = COPY %W5; GPR32:%vreg9
64B		%vreg8<def> = COPY %X4; GPR64:%vreg8
80B		%vreg7<def> = COPY %X3; GPR64:%vreg7
96B		%vreg6<def> = COPY %X2; GPR64:%vreg6
112B		%vreg5<def> = COPY %X1; GPR64:%vreg5
128B		%vreg4<def> = COPY %X0; GPR64:%vreg4
144B		%vreg12<def> = LDRWui <fi#-1>, 0; mem:LD4[FixedStack-1] GPR32:%vreg12
160B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
176B		%vreg13<def> = ANDWri %vreg9, 0; GPR32common:%vreg13 GPR32:%vreg9
192B		%vreg14<def> = COPY %XZR; GPR64all:%vreg14
208B		%X0<def> = COPY %vreg14; GPR64all:%vreg14
224B		%X1<def> = COPY %vreg14; GPR64all:%vreg14
240B		BL <ga:@check_migrate>, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %SP<imp-def>, ...
256B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
272B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
288B		STACKMAP 0, 0, %vreg8, %vreg7, %vreg6, %vreg5, %vreg11, %vreg10, %vreg4, %vreg13, %vreg12, ...; GPR64:%vreg8,%vreg7,%vreg6,%vreg5,%vreg11,%vreg4 GPR32:%vreg10,%vreg12 GPR32common:%vreg13
304B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
320B		STRXui %vreg4, <fi#0>, 0; mem:ST8[%fn.addr] GPR64:%vreg4
336B		STRXui %vreg5, <fi#1>, 0; mem:ST8[%data.addr] GPR64:%vreg5
352B		STRXui %vreg6, <fi#2>, 0; mem:ST8[%cpyfn.addr] GPR64:%vreg6
368B		STRXui %vreg7, <fi#3>, 0; mem:ST8[%arg_size.addr] GPR64:%vreg7
384B		STRXui %vreg8, <fi#4>, 0; mem:ST8[%arg_align.addr] GPR64:%vreg8
400B		STRBBui %vreg13, <fi#5>, 0; mem:ST1[%if_clause.addr] GPR32common:%vreg13
416B		STRWui %vreg10, <fi#6>, 0; mem:ST4[%flags.addr] GPR32:%vreg10
432B		STRXui %vreg11, <fi#7>, 0; mem:ST8[%depend.addr] GPR64:%vreg11
448B		STRWui %vreg12, <fi#8>, 0; mem:ST4[%priority.addr] GPR32:%vreg12
464B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
480B		BL <ga:@gomp_thread>, <regmask>, %SP<imp-use>, %SP<imp-def>, %X0<imp-def>, ...
496B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
512B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
528B		STACKMAP 1, 0, 0, <fi#13>, 0, 0, <fi#17>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#19>, 0, 0, <fi#18>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#5>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#12>, 0, 0, <fi#11>, 0, 0, <fi#14>, 0, 0, <fi#16>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack13] LD8[FixedStack17] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack2] LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack19] LD8[FixedStack18](align=1) LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack5](align=1) LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack12] LD8[FixedStack11] LD8[FixedStack14] LD8[FixedStack16] LD8[FixedStack10] LD8[FixedStack9]
544B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
560B		%vreg15<def> = COPY %X0; GPR64common:%vreg15
576B		STRXui %vreg15, <fi#9>, 0; mem:ST8[%thr] GPR64common:%vreg15
592B		%vreg16<def> = LDRXui %vreg15, 2; mem:LD8[%team1] GPR64:%vreg16 GPR64common:%vreg15
608B		STRXui %vreg16, <fi#10>, 0; mem:ST8[%team] GPR64:%vreg16
624B		CBZX %vreg16, <BB#5>; GPR64:%vreg16
640B		B <BB#1>
	    Successors according to CFG: BB#1 BB#5

656B	BB#1: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#0
672B		%vreg17<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg17
688B		%vreg18<def> = ADDXri %vreg17, 128, 0; GPR64sp:%vreg18 GPR64common:%vreg17
704B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
720B		%X0<def> = COPY %vreg18; GPR64sp:%vreg18
736B		BL <ga:@gomp_team_barrier_cancelled>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>, ...
752B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
768B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
784B		STACKMAP 2, 0, 0, <fi#13>, 0, 0, <fi#17>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#19>, 0, 0, <fi#18>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#5>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#12>, 0, 0, <fi#11>, 0, 0, <fi#14>, 0, 0, <fi#16>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack13] LD8[FixedStack17] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack2] LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack19] LD8[FixedStack18](align=1) LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack5](align=1) LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack12] LD8[FixedStack11] LD8[FixedStack14] LD8[FixedStack16] LD8[FixedStack10] LD8[FixedStack9]
800B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
816B		%vreg19<def> = COPY %W0; GPR32:%vreg19
832B		TBNZW %vreg19, 0, <BB#4>; GPR32:%vreg19
848B		B <BB#2>
	    Successors according to CFG: BB#4 BB#2

864B	BB#2: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#1
880B		%vreg20<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg20
896B		%vreg21<def> = LDRXui %vreg20, 10; mem:LD8[%task] GPR64common:%vreg21,%vreg20
912B		%vreg22<def> = LDRXui %vreg21, 5; mem:LD8[%taskgroup] GPR64:%vreg22 GPR64common:%vreg21
928B		CBZX %vreg22, <BB#5>; GPR64:%vreg22
944B		B <BB#3>
	    Successors according to CFG: BB#3 BB#5

960B	BB#3: derived from LLVM BB %land.lhs.true.4
	    Predecessors according to CFG: BB#2
976B		%vreg23<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg23
992B		%vreg24<def> = LDRXui %vreg23, 10; mem:LD8[%task5] GPR64common:%vreg24,%vreg23
1008B		%vreg25<def> = LDRXui %vreg24, 5; mem:LD8[%taskgroup6] GPR64common:%vreg25,%vreg24
1024B		%vreg26<def> = LDRBBui %vreg25, 41; mem:LD1[%cancelled] GPR32:%vreg26 GPR64common:%vreg25
1040B		TBZW %vreg26, 0, <BB#5>; GPR32:%vreg26
1056B		B <BB#4>
	    Successors according to CFG: BB#4 BB#5

1072B	BB#4: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#1 BB#3
1088B		B <BB#52>
	    Successors according to CFG: BB#52

1104B	BB#5: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#2 BB#3
1120B		%vreg27<def> = LDRBBui <fi#6>, 0; mem:LD1[%flags.addr](align=4) GPR32:%vreg27
1136B		TBNZW %vreg27, 4, <BB#7>; GPR32:%vreg27
1152B		B <BB#6>
	    Successors according to CFG: BB#6 BB#7

1168B	BB#6: derived from LLVM BB %if.then.8
	    Predecessors according to CFG: BB#5
1184B		%vreg34<def> = COPY %WZR; GPR32:%vreg34
1200B		STRWui %vreg34, <fi#8>, 0; mem:ST4[%priority.addr] GPR32:%vreg34
1216B		B <BB#10>
	    Successors according to CFG: BB#10

1232B	BB#7: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#5
1248B		%vreg28<def> = LDRWui <fi#8>, 0; mem:LD4[%priority.addr] GPR32:%vreg28
1264B		%vreg29<def> = ADRP <ga:@gomp_max_task_priority_var>[TF=1]; GPR64common:%vreg29
1280B		%vreg30<def> = LDRWui %vreg29, <ga:@gomp_max_task_priority_var>[TF=34]; mem:LD4[@gomp_max_task_priority_var] GPR32:%vreg30 GPR64common:%vreg29
1296B		%vreg31<def,dead> = SUBSWrr %vreg28, %vreg30, %NZCV<imp-def>; GPR32:%vreg31,%vreg28,%vreg30
1312B		Bcc 13, <BB#9>, %NZCV<imp-use,kill>
1328B		B <BB#8>
	    Successors according to CFG: BB#8 BB#9

1344B	BB#8: derived from LLVM BB %if.then.10
	    Predecessors according to CFG: BB#7
1360B		%vreg32<def> = ADRP <ga:@gomp_max_task_priority_var>[TF=1]; GPR64common:%vreg32
1376B		%vreg33<def> = LDRWui %vreg32, <ga:@gomp_max_task_priority_var>[TF=34]; mem:LD4[@gomp_max_task_priority_var] GPR32:%vreg33 GPR64common:%vreg32
1392B		STRWui %vreg33, <fi#8>, 0; mem:ST4[%priority.addr] GPR32:%vreg33
1408B		B <BB#9>
	    Successors according to CFG: BB#9

1424B	BB#9: derived from LLVM BB %if.end.11
	    Predecessors according to CFG: BB#7 BB#8
1440B		B <BB#10>
	    Successors according to CFG: BB#10

1456B	BB#10: derived from LLVM BB %if.end.12
	    Predecessors according to CFG: BB#9 BB#6
1472B		%vreg35<def> = LDRBBui <fi#5>, 0; mem:LD1[%if_clause.addr] GPR32:%vreg35
1488B		TBZW %vreg35, 0, <BB#15>; GPR32:%vreg35
1504B		B <BB#11>
	    Successors according to CFG: BB#11 BB#15

1520B	BB#11: derived from LLVM BB %lor.lhs.false.14
	    Predecessors according to CFG: BB#10
1536B		%vreg36<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64:%vreg36
1552B		CBZX %vreg36, <BB#15>; GPR64:%vreg36
1568B		B <BB#12>
	    Successors according to CFG: BB#15 BB#12

1584B	BB#12: derived from LLVM BB %lor.lhs.false.16
	    Predecessors according to CFG: BB#11
1600B		%vreg37<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg37
1616B		%vreg38<def> = LDRXui %vreg37, 10; mem:LD8[%task17] GPR64:%vreg38 GPR64common:%vreg37
1632B		CBZX %vreg38, <BB#14>; GPR64:%vreg38
1648B		B <BB#13>
	    Successors according to CFG: BB#13 BB#14

1664B	BB#13: derived from LLVM BB %land.lhs.true.19
	    Predecessors according to CFG: BB#12
1680B		%vreg39<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg39
1696B		%vreg40<def> = LDRXui %vreg39, 10; mem:LD8[%task20] GPR64common:%vreg40,%vreg39
1712B		%vreg41<def> = LDRBBui %vreg40, 205; mem:LD1[%final_task] GPR32:%vreg41 GPR64common:%vreg40
1728B		%vreg42<def> = ANDWri %vreg41, 0; GPR32common:%vreg42 GPR32:%vreg41
1744B		TBNZW %vreg42, 0, <BB#15>; GPR32common:%vreg42
1760B		B <BB#14>
	    Successors according to CFG: BB#15 BB#14

1776B	BB#14: derived from LLVM BB %lor.lhs.false.22
	    Predecessors according to CFG: BB#12 BB#13
1792B		%vreg43<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg43
1808B		%vreg44<def> = LDRWui %vreg43, 330; mem:LD4[%task_count] GPR32:%vreg44 GPR64common:%vreg43
1824B		%vreg45<def> = LDRWui %vreg43, 0; mem:LD4[%nthreads] GPR32:%vreg45 GPR64common:%vreg43
1840B		%vreg46<def,dead> = SUBSWrs %vreg44, %vreg45, 6, %NZCV<imp-def>; GPR32:%vreg46,%vreg44,%vreg45
1856B		Bcc 9, <BB#30>, %NZCV<imp-use,kill>
1872B		B <BB#15>
	    Successors according to CFG: BB#15 BB#30

1888B	BB#15: derived from LLVM BB %if.then.24
	    Predecessors according to CFG: BB#10 BB#11 BB#13 BB#14
1904B		%vreg187<def> = LDRBBui <fi#6>, 0; mem:LD1[%flags.addr](align=4) GPR32:%vreg187
1920B		TBZW %vreg187, 3, <BB#19>; GPR32:%vreg187
1936B		B <BB#16>
	    Successors according to CFG: BB#16 BB#19

1952B	BB#16: derived from LLVM BB %land.lhs.true.28
	    Predecessors according to CFG: BB#15
1968B		%vreg188<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg188
1984B		%vreg189<def> = LDRXui %vreg188, 10; mem:LD8[%task29] GPR64:%vreg189 GPR64common:%vreg188
2000B		CBZX %vreg189, <BB#19>; GPR64:%vreg189
2016B		B <BB#17>
	    Successors according to CFG: BB#17 BB#19

2032B	BB#17: derived from LLVM BB %land.lhs.true.31
	    Predecessors according to CFG: BB#16
2048B		%vreg190<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg190
2064B		%vreg191<def> = LDRXui %vreg190, 10; mem:LD8[%task32] GPR64common:%vreg191,%vreg190
2080B		%vreg192<def> = LDRXui %vreg191, 7; mem:LD8[%depend_hash] GPR64:%vreg192 GPR64common:%vreg191
2096B		CBZX %vreg192, <BB#19>; GPR64:%vreg192
2112B		B <BB#18>
	    Successors according to CFG: BB#18 BB#19

2128B	BB#18: derived from LLVM BB %if.then.34
	    Predecessors according to CFG: BB#17
2144B		%vreg193<def> = LDRXui <fi#7>, 0; mem:LD8[%depend.addr] GPR64:%vreg193
2160B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2176B		%X0<def> = COPY %vreg193; GPR64:%vreg193
2192B		BL <ga:@gomp_task_maybe_wait_for_dependencies>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...
2208B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2224B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2240B		STACKMAP 3, 0, 0, <fi#13>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#8>, 0, 0, <fi#12>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack13] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack2] LD8[FixedStack1] LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack8](align=4) LD8[FixedStack12] LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack9]
2256B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2272B		B <BB#19>
	    Successors according to CFG: BB#19

2288B	BB#19: derived from LLVM BB %if.end.35
	    Predecessors according to CFG: BB#15 BB#16 BB#17 BB#18
2304B		%vreg194<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg194
2320B		%vreg195<def> = LDRXui %vreg194, 10; mem:LD8[%task36] GPR64:%vreg195 GPR64common:%vreg194
2336B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2352B		%vreg196<def> = COPY %WZR; GPR32all:%vreg196
2368B		%W0<def> = COPY %vreg196; GPR32all:%vreg196
2384B		BL <ga:@gomp_icv>, <regmask>, %SP<imp-use>, %W0<imp-use>, %SP<imp-def>, %X0<imp-def>, ...
2400B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2416B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2432B		STACKMAP 4, 0, 0, <fi#13>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#8>, 0, 0, <fi#12>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, %vreg195, ...; mem:LD8[FixedStack13] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack2] LD8[FixedStack1] LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack8](align=4) LD8[FixedStack12] LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack9] GPR64:%vreg195
2448B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2464B		%vreg197<def> = COPY %X0; GPR64all:%vreg197
2480B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2496B		%vreg198<def> = ADDXri <fi#11>, 0, 0; GPR64sp:%vreg198
2512B		%X0<def> = COPY %vreg198; GPR64sp:%vreg198
2528B		%X1<def> = COPY %vreg195; GPR64:%vreg195
2544B		%X2<def> = COPY %vreg197; GPR64all:%vreg197
2560B		BL <ga:@gomp_init_task>, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %X2<imp-use>, %SP<imp-def>, ...
2576B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2592B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2608B		STACKMAP 5, 0, 0, <fi#13>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#8>, 0, 0, <fi#12>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack13] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack2] LD8[FixedStack1] LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack8](align=4) LD8[FixedStack12] LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack9]
2624B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2640B		%vreg199<def> = MOVi32imm 1; GPR32:%vreg199
2656B		STRWui %vreg199, <fi#11>, 50; mem:ST4[%kind] GPR32:%vreg199
2672B		%vreg200<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg200
2688B		%vreg201<def> = LDRXui %vreg200, 10; mem:LD8[%task38] GPR64:%vreg201 GPR64common:%vreg200
2704B		CBZX %vreg201, <BB#21>; GPR64:%vreg201
2720B		B <BB#20>
	    Successors according to CFG: BB#20 BB#21

2736B	BB#20: derived from LLVM BB %land.lhs.true.40
	    Predecessors according to CFG: BB#19
2752B		%vreg203<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg203
2768B		%vreg204<def> = LDRXui %vreg203, 10; mem:LD8[%task41] GPR64common:%vreg204,%vreg203
2784B		%vreg205<def> = LDRBBui %vreg204, 205; mem:LD1[%final_task42] GPR32:%vreg205 GPR64common:%vreg204
2800B		%vreg206<def> = ANDWri %vreg205, 0; GPR32common:%vreg206 GPR32:%vreg205
2816B		%vreg207<def> = MOVi32imm 1; GPR32:%vreg207
2832B		%vreg202<def> = COPY %vreg207; GPR32all:%vreg202 GPR32:%vreg207
2848B		%vreg255<def> = COPY %vreg202; GPR32:%vreg255 GPR32all:%vreg202
2864B		TBNZW %vreg206, 0, <BB#22>; GPR32common:%vreg206
2880B		B <BB#21>
	    Successors according to CFG: BB#22 BB#21

2896B	BB#21: derived from LLVM BB %lor.rhs
	    Predecessors according to CFG: BB#19 BB#20
2912B		%vreg208<def> = LDRBBui <fi#6>, 0; mem:LD1[%flags.addr](align=4) GPR32:%vreg208
2928B		%vreg209<def> = UBFMWri %vreg208, 1, 1; GPR32:%vreg209,%vreg208
2944B		%vreg0<def> = COPY %vreg209; GPR32all:%vreg0 GPR32:%vreg209
2960B		%vreg255<def> = COPY %vreg0; GPR32:%vreg255 GPR32all:%vreg0
2976B		B <BB#22>
	    Successors according to CFG: BB#22

2992B	BB#22: derived from LLVM BB %lor.end
	    Predecessors according to CFG: BB#20 BB#21
3008B		%vreg1<def> = COPY %vreg255; GPR32:%vreg1,%vreg255
3024B		%vreg210<def> = ANDWri %vreg1, 0; GPR32common:%vreg210 GPR32:%vreg1
3040B		STRBBui %vreg210, <fi#11>, 205; mem:ST1[%final_task46] GPR32common:%vreg210
3056B		%vreg211<def> = LDRWui <fi#8>, 0; mem:LD4[%priority.addr] GPR32:%vreg211
3072B		STRWui %vreg211, <fi#11>, 22; mem:ST4[%priority48] GPR32:%vreg211
3088B		%vreg212<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg212
3104B		%vreg213<def> = LDRXui %vreg212, 10; mem:LD8[%task49] GPR64:%vreg213 GPR64common:%vreg212
3120B		CBZX %vreg213, <BB#24>; GPR64:%vreg213
3136B		B <BB#23>
	    Successors according to CFG: BB#23 BB#24

3152B	BB#23: derived from LLVM BB %if.then.51
	    Predecessors according to CFG: BB#22
3168B		%vreg214<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg214
3184B		%vreg215<def> = LDRXui %vreg214, 10; mem:LD8[%task52] GPR64common:%vreg215,%vreg214
3200B		%vreg216<def> = LDRBBui %vreg215, 204; mem:LD1[%in_tied_task] GPR32:%vreg216 GPR64common:%vreg215
3216B		%vreg217<def> = ANDWri %vreg216, 0; GPR32common:%vreg217 GPR32:%vreg216
3232B		STRBBui %vreg217, <fi#11>, 204; mem:ST1[%in_tied_task54] GPR32common:%vreg217
3248B		%vreg218<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg218
3264B		%vreg219<def> = LDRXui %vreg218, 10; mem:LD8[%task56] GPR64common:%vreg219,%vreg218
3280B		%vreg220<def> = LDRXui %vreg219, 5; mem:LD8[%taskgroup57] GPR64:%vreg220 GPR64common:%vreg219
3296B		STRXui %vreg220, <fi#11>, 5; mem:ST8[%taskgroup58] GPR64:%vreg220
3312B		B <BB#24>
	    Successors according to CFG: BB#24

3328B	BB#24: derived from LLVM BB %if.end.59
	    Predecessors according to CFG: BB#22 BB#23
3344B		%vreg221<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg221
3360B		%vreg222<def> = ADDXri <fi#11>, 0, 0; GPR64common:%vreg222
3376B		STRXui %vreg222, %vreg221, 10; mem:ST8[%task60] GPR64common:%vreg222,%vreg221
3392B		%vreg223<def> = LDRXui <fi#2>, 0; mem:LD8[%cpyfn.addr] GPR64:%vreg223
3408B		CBZX %vreg223, <BB#26>; GPR64:%vreg223
3424B		B <BB#25>
	    Successors according to CFG: BB#25 BB#26

3440B	BB#25: derived from LLVM BB %if.then.64
	    Predecessors according to CFG: BB#24
3456B		%vreg226<def> = LDRXui <fi#3>, 0; mem:LD8[%arg_size.addr] GPR64:%vreg226
3472B		%vreg227<def> = LDRXui <fi#4>, 0; mem:LD8[%arg_align.addr] GPR64:%vreg227
3488B		%vreg228<def> = ADDXrr %vreg226, %vreg227; GPR64common:%vreg228 GPR64:%vreg226,%vreg227
3504B		%vreg229<def> = COPY %SP; GPR64:%vreg229
3520B		STRXui %vreg229, <fi#12>, 0; mem:ST8[%saved_stack] GPR64:%vreg229
3536B		%vreg230<def> = ADDXri %vreg228, 14, 0; GPR64common:%vreg230,%vreg228
3552B		%vreg231<def> = ANDXri %vreg230, 7995; GPR64common:%vreg231,%vreg230
3568B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3584B		%vreg232<def> = COPY %SP; GPR64:%vreg232
3600B		%vreg233<def> = SUBSXrr %vreg232, %vreg231, %NZCV<imp-def,dead>; GPR64:%vreg233,%vreg232 GPR64common:%vreg231
3616B		%SP<def> = COPY %vreg233; GPR64:%vreg233
3632B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3648B		%vreg234<def> = LDRXui <fi#4>, 0; mem:LD8[%arg_align.addr] GPR64common:%vreg234
3664B		%vreg235<def> = ADDXrr %vreg233, %vreg234; GPR64common:%vreg235,%vreg234 GPR64:%vreg233
3680B		%vreg236<def> = SUBSXri %vreg235, 1, 0, %NZCV<imp-def,dead>; GPR64:%vreg236 GPR64common:%vreg235
3696B		%vreg237<def> = SUBSXri %vreg234, 1, 0, %NZCV<imp-def,dead>; GPR64:%vreg237 GPR64common:%vreg234
3712B		%vreg238<def> = BICXrr %vreg236, %vreg237; GPR64:%vreg238,%vreg236,%vreg237
3728B		STRXui %vreg238, <fi#13>, 0; mem:ST8[%arg] GPR64:%vreg238
3744B		%vreg239<def> = LDRXui <fi#2>, 0; mem:LD8[%cpyfn.addr] GPR64:%vreg239
3760B		%vreg240<def> = LDRXui <fi#1>, 0; mem:LD8[%data.addr] GPR64:%vreg240
3776B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3792B		%X0<def> = COPY %vreg238; GPR64:%vreg238
3808B		%X1<def> = COPY %vreg240; GPR64:%vreg240
3824B		BLR %vreg239, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %SP<imp-def>, ...; GPR64:%vreg239
3840B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3856B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3872B		STACKMAP 6, 0, 0, <fi#13>, 0, 0, <fi#0>, 0, 0, <fi#12>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack13] LD8[FixedStack0] LD8[FixedStack12] LD8[FixedStack11] LD8[FixedStack10]
3888B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3904B		%vreg241<def> = LDRXui <fi#0>, 0; mem:LD8[%fn.addr] GPR64:%vreg241
3920B		%vreg242<def> = LDRXui <fi#13>, 0; mem:LD8[%arg] GPR64:%vreg242
3936B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3952B		%X0<def> = COPY %vreg242; GPR64:%vreg242
3968B		BLR %vreg241, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...; GPR64:%vreg241
3984B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4000B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4016B		STACKMAP 7, 0, 0, <fi#12>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack12] LD8[FixedStack11] LD8[FixedStack10]
4032B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4048B		%vreg243<def> = LDRXui <fi#12>, 0; mem:LD8[%saved_stack] GPR64:%vreg243
4064B		%SP<def> = COPY %vreg243; GPR64:%vreg243
4080B		B <BB#27>
	    Successors according to CFG: BB#27

4096B	BB#26: derived from LLVM BB %if.else.69
	    Predecessors according to CFG: BB#24
4112B		%vreg224<def> = LDRXui <fi#0>, 0; mem:LD8[%fn.addr] GPR64:%vreg224
4128B		%vreg225<def> = LDRXui <fi#1>, 0; mem:LD8[%data.addr] GPR64:%vreg225
4144B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4160B		%X0<def> = COPY %vreg225; GPR64:%vreg225
4176B		BLR %vreg224, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...; GPR64:%vreg224
4192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4224B		STACKMAP 8, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack11] LD8[FixedStack10]
4240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4256B		B <BB#27>
	    Successors according to CFG: BB#27

4272B	BB#27: derived from LLVM BB %if.end.70
	    Predecessors according to CFG: BB#26 BB#25
4288B		%vreg244<def> = ADDXri <fi#11>, 0, 0; GPR64sp:%vreg244
4304B		%vreg245<def> = ADDXri %vreg244, 8, 0; GPR64sp:%vreg245,%vreg244
4320B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4336B		%vreg246<def> = COPY %WZR; GPR32all:%vreg246
4352B		%X0<def> = COPY %vreg245; GPR64sp:%vreg245
4368B		%W1<def> = COPY %vreg246; GPR32all:%vreg246
4384B		BL <ga:@priority_queue_empty_p>, <regmask>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %SP<imp-def>, %W0<imp-def>, ...
4400B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4416B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4432B		STACKMAP 9, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack11] LD8[FixedStack10]
4448B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4464B		%vreg247<def> = COPY %W0; GPR32:%vreg247
4480B		TBNZW %vreg247, 0, <BB#29>; GPR32:%vreg247
4496B		B <BB#28>
	    Successors according to CFG: BB#29 BB#28

4512B	BB#28: derived from LLVM BB %if.then.72
	    Predecessors according to CFG: BB#27
4528B		%vreg248<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg248
4544B		%vreg249<def> = ADDXri %vreg248, 1280, 0; GPR64sp:%vreg249 GPR64common:%vreg248
4560B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4576B		%X0<def> = COPY %vreg249; GPR64sp:%vreg249
4592B		BL <ga:@gomp_mutex_lock>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...
4608B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4624B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4640B		STACKMAP 10, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack11] LD8[FixedStack10]
4656B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4672B		%vreg250<def> = ADDXri <fi#11>, 0, 0; GPR64sp:%vreg250
4688B		%vreg251<def> = ADDXri %vreg250, 8, 0; GPR64sp:%vreg251,%vreg250
4704B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4720B		%X0<def> = COPY %vreg251; GPR64sp:%vreg251
4736B		BL <ga:@gomp_clear_parent>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...
4752B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4768B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4784B		STACKMAP 11, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack10]
4800B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4816B		%vreg252<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg252
4832B		%vreg253<def> = ADDXri %vreg252, 1280, 0; GPR64sp:%vreg253 GPR64common:%vreg252
4848B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4864B		%X0<def> = COPY %vreg253; GPR64sp:%vreg253
4880B		BL <ga:@gomp_mutex_unlock>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...
4896B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4912B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4928B		STACKMAP 12, 0, ...
4944B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4960B		B <BB#29>
	    Successors according to CFG: BB#29

4976B	BB#29: derived from LLVM BB %if.end.75
	    Predecessors according to CFG: BB#27 BB#28
4992B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5008B		BL <ga:@gomp_end_task>, <regmask>, %SP<imp-use>, %SP<imp-def>, ...
5024B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5040B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5056B		STACKMAP 13, 0, ...
5072B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5088B		B <BB#52>
	    Successors according to CFG: BB#52

5104B	BB#30: derived from LLVM BB %if.else.76
	    Predecessors according to CFG: BB#14
5120B		%vreg47<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg47
5136B		%vreg48<def> = LDRXui %vreg47, 10; mem:LD8[%task78] GPR64common:%vreg48,%vreg47
5152B		STRXui %vreg48, <fi#15>, 0; mem:ST8[%parent] GPR64common:%vreg48
5168B		%vreg49<def> = LDRXui %vreg48, 5; mem:LD8[%taskgroup80] GPR64:%vreg49 GPR64common:%vreg48
5184B		STRXui %vreg49, <fi#16>, 0; mem:ST8[%taskgroup79] GPR64:%vreg49
5200B		%vreg50<def> = COPY %XZR; GPR64:%vreg50
5216B		STRXui %vreg50, <fi#19>, 0; mem:ST8[%depend_size] GPR64:%vreg50
5232B		%vreg51<def> = LDRBBui <fi#6>, 0; mem:LD1[%flags.addr](align=4) GPR32:%vreg51
5248B		TBZW %vreg51, 3, <BB#32>; GPR32:%vreg51
5264B		B <BB#31>
	    Successors according to CFG: BB#31 BB#32

5280B	BB#31: derived from LLVM BB %if.then.84
	    Predecessors according to CFG: BB#30
5296B		%vreg52<def> = LDRXui <fi#7>, 0; mem:LD8[%depend.addr] GPR64common:%vreg52
5312B		%vreg53<def> = LDRXui %vreg52, 0; mem:LD8[%arrayidx] GPR64:%vreg53 GPR64common:%vreg52
5328B		%vreg54<def> = MOVi32imm 40; GPR32:%vreg54
5344B		%vreg55<def> = SUBREG_TO_REG 0, %vreg54, 15; GPR64:%vreg55 GPR32:%vreg54
5360B		%vreg56<def> = MADDXrrr %vreg53, %vreg55, %XZR; GPR64:%vreg56,%vreg53,%vreg55
5376B		STRXui %vreg56, <fi#19>, 0; mem:ST8[%depend_size] GPR64:%vreg56
5392B		B <BB#32>
	    Successors according to CFG: BB#32

5408B	BB#32: derived from LLVM BB %if.end.86
	    Predecessors according to CFG: BB#30 BB#31
5424B		%vreg57<def> = LDRXui <fi#19>, 0; mem:LD8[%depend_size] GPR64:%vreg57
5440B		%vreg58<def> = LDRXui <fi#3>, 0; mem:LD8[%arg_size.addr] GPR64:%vreg58
5456B		%vreg59<def> = ADDXrr %vreg57, %vreg58; GPR64:%vreg59,%vreg57,%vreg58
5472B		%vreg60<def> = LDRXui <fi#4>, 0; mem:LD8[%arg_align.addr] GPR64:%vreg60
5488B		%vreg61<def> = ADDXrr %vreg59, %vreg60; GPR64common:%vreg61 GPR64:%vreg59,%vreg60
5504B		%vreg62<def> = ADDXri %vreg61, 207, 0; GPR64sp:%vreg62 GPR64common:%vreg61
5520B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5536B		%X0<def> = COPY %vreg62; GPR64sp:%vreg62
5552B		BL <ga:@gomp_malloc>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %X0<imp-def>, ...
5568B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5584B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5600B		STACKMAP 14, 0, 0, <fi#17>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#19>, 0, 0, <fi#18>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#14>, 0, 0, <fi#16>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack17] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack2] LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack19] LD8[FixedStack18](align=1) LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack14] LD8[FixedStack16] LD8[FixedStack10] LD8[FixedStack9]
5616B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5632B		%vreg63<def> = COPY %X0; GPR64:%vreg63
5648B		STRXui %vreg63, <fi#14>, 0; mem:ST8[%task77] GPR64:%vreg63
5664B		%vreg64<def> = LDRXui <fi#19>, 0; mem:LD8[%depend_size] GPR64:%vreg64
5680B		%vreg65<def> = ADDXrr %vreg63, %vreg64; GPR64:%vreg65,%vreg63,%vreg64
5696B		%vreg66<def> = LDRXui <fi#4>, 0; mem:LD8[%arg_align.addr] GPR64common:%vreg66
5712B		%vreg67<def> = ADDXrr %vreg65, %vreg66; GPR64common:%vreg67,%vreg66 GPR64:%vreg65
5728B		%vreg68<def> = ADDXri %vreg67, 207, 0; GPR64common:%vreg68,%vreg67
5744B		%vreg69<def> = SUBSXri %vreg66, 1, 0, %NZCV<imp-def,dead>; GPR64:%vreg69 GPR64common:%vreg66
5760B		%vreg70<def> = BICXrr %vreg68, %vreg69; GPR64:%vreg70,%vreg69 GPR64common:%vreg68
5776B		STRXui %vreg70, <fi#17>, 0; mem:ST8[%arg81] GPR64:%vreg70
5792B		%vreg71<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64:%vreg71
5808B		%vreg72<def> = LDRXui <fi#15>, 0; mem:LD8[%parent] GPR64:%vreg72
5824B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5840B		%vreg73<def> = COPY %WZR; GPR32all:%vreg73
5856B		%W0<def> = COPY %vreg73; GPR32all:%vreg73
5872B		BL <ga:@gomp_icv>, <regmask>, %SP<imp-use>, %W0<imp-use>, %SP<imp-def>, %X0<imp-def>, ...
5888B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5904B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5920B		STACKMAP 15, 0, 0, <fi#17>, 0, 0, <fi#3>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#19>, 0, 0, <fi#18>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#14>, 0, 0, <fi#16>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, %vreg71, %vreg72, ...; mem:LD8[FixedStack17] LD8[FixedStack3] LD8[FixedStack2] LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack19] LD8[FixedStack18](align=1) LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack14] LD8[FixedStack16] LD8[FixedStack10] LD8[FixedStack9] GPR64:%vreg71,%vreg72
5936B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5952B		%vreg74<def> = COPY %X0; GPR64all:%vreg74
5968B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5984B		%X0<def> = COPY %vreg71; GPR64:%vreg71
6000B		%X1<def> = COPY %vreg72; GPR64:%vreg72
6016B		%X2<def> = COPY %vreg74; GPR64all:%vreg74
6032B		BL <ga:@gomp_init_task>, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %X2<imp-use>, %SP<imp-def>, ...
6048B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
6064B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
6080B		STACKMAP 16, 0, 0, <fi#17>, 0, 0, <fi#3>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#19>, 0, 0, <fi#18>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#14>, 0, 0, <fi#16>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack17] LD8[FixedStack3] LD8[FixedStack2] LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack19] LD8[FixedStack18](align=1) LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack14] LD8[FixedStack16] LD8[FixedStack10] LD8[FixedStack9]
6096B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
6112B		%vreg75<def> = LDRWui <fi#8>, 0; mem:LD4[%priority.addr] GPR32:%vreg75
6128B		%vreg76<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64common:%vreg76
6144B		STRWui %vreg75, %vreg76, 22; mem:ST4[%priority99] GPR32:%vreg75 GPR64common:%vreg76
6160B		%vreg77<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64common:%vreg77
6176B		%vreg78<def> = MOVi32imm 1; GPR32:%vreg78
6192B		STRWui %vreg78, %vreg77, 50; mem:ST4[%kind100] GPR32:%vreg78 GPR64common:%vreg77
6208B		%vreg79<def> = LDRXui <fi#15>, 0; mem:LD8[%parent] GPR64common:%vreg79
6224B		%vreg80<def> = LDRBBui %vreg79, 204; mem:LD1[%in_tied_task101] GPR32:%vreg80 GPR64common:%vreg79
6240B		%vreg81<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64common:%vreg81
6256B		%vreg82<def> = ANDWri %vreg80, 0; GPR32common:%vreg82 GPR32:%vreg80
6272B		STRBBui %vreg82, %vreg81, 204; mem:ST1[%in_tied_task103] GPR32common:%vreg82 GPR64common:%vreg81
6288B		%vreg83<def> = LDRXui <fi#16>, 0; mem:LD8[%taskgroup79] GPR64:%vreg83
6304B		%vreg84<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64common:%vreg84
6320B		STRXui %vreg83, %vreg84, 5; mem:ST8[%taskgroup105] GPR64:%vreg83 GPR64common:%vreg84
6336B		%vreg85<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64:%vreg85
6352B		%vreg86<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg86
6368B		STRXui %vreg85, %vreg86, 10; mem:ST8[%task106] GPR64:%vreg85 GPR64common:%vreg86
6384B		%vreg87<def> = LDRXui <fi#2>, 0; mem:LD8[%cpyfn.addr] GPR64:%vreg87
6400B		CBZX %vreg87, <BB#34>; GPR64:%vreg87
6416B		B <BB#33>
	    Successors according to CFG: BB#33 BB#34

6432B	BB#33: derived from LLVM BB %if.then.108
	    Predecessors according to CFG: BB#32
6448B		%vreg91<def> = LDRXui <fi#2>, 0; mem:LD8[%cpyfn.addr] GPR64:%vreg91
6464B		%vreg92<def> = LDRXui <fi#17>, 0; mem:LD8[%arg81] GPR64:%vreg92
6480B		%vreg93<def> = LDRXui <fi#1>, 0; mem:LD8[%data.addr] GPR64:%vreg93
6496B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
6512B		%X0<def> = COPY %vreg92; GPR64:%vreg92
6528B		%X1<def> = COPY %vreg93; GPR64:%vreg93
6544B		BLR %vreg91, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %SP<imp-def>, ...; GPR64:%vreg91
6560B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
6576B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
6592B		STACKMAP 17, 0, 0, <fi#17>, 0, 0, <fi#7>, 0, 0, <fi#19>, 0, 0, <fi#18>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#14>, 0, 0, <fi#16>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack17] LD8[FixedStack7] LD8[FixedStack19] LD8[FixedStack18](align=1) LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack14] LD8[FixedStack16] LD8[FixedStack10] LD8[FixedStack9]
6608B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
6624B		%vreg94<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64common:%vreg94
6640B		%vreg95<def> = MOVi32imm 1; GPR32:%vreg95
6656B		STRBBui %vreg95, %vreg94, 206; mem:ST1[%copy_ctors_done] GPR32:%vreg95 GPR64common:%vreg94
6672B		B <BB#35>
	    Successors according to CFG: BB#35

6688B	BB#34: derived from LLVM BB %if.else.109
	    Predecessors according to CFG: BB#32
6704B		%vreg88<def> = LDRXui <fi#17>, 0; mem:LD8[%arg81] GPR64:%vreg88
6720B		%vreg89<def> = LDRXui <fi#1>, 0; mem:LD8[%data.addr] GPR64:%vreg89
6736B		%vreg90<def> = LDRXui <fi#3>, 0; mem:LD8[%arg_size.addr] GPR64:%vreg90
6752B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
6768B		%X0<def> = COPY %vreg88; GPR64:%vreg88
6784B		%X1<def> = COPY %vreg89; GPR64:%vreg89
6800B		%X2<def> = COPY %vreg90; GPR64:%vreg90
6816B		BL <es:memcpy>, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %X2<imp-use>, %SP<imp-def>, ...
6832B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
6848B		B <BB#35>
	    Successors according to CFG: BB#35

6864B	BB#35: derived from LLVM BB %if.end.110
	    Predecessors according to CFG: BB#34 BB#33
6880B		%vreg96<def> = LDRXui <fi#15>, 0; mem:LD8[%parent] GPR64:%vreg96
6896B		%vreg97<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg97
6912B		STRXui %vreg96, %vreg97, 10; mem:ST8[%task111] GPR64:%vreg96 GPR64common:%vreg97
6928B		%vreg98<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64common:%vreg98
6944B		%vreg99<def> = MOVi32imm 2; GPR32:%vreg99
6960B		STRWui %vreg99, %vreg98, 50; mem:ST4[%kind112] GPR32:%vreg99 GPR64common:%vreg98
6976B		%vreg100<def> = LDRXui <fi#0>, 0; mem:LD8[%fn.addr] GPR64:%vreg100
6992B		%vreg101<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64common:%vreg101
7008B		STRXui %vreg100, %vreg101, 23; mem:ST8[%fn113] GPR64:%vreg100 GPR64common:%vreg101
7024B		%vreg102<def> = LDRXui <fi#17>, 0; mem:LD8[%arg81] GPR64:%vreg102
7040B		%vreg103<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64common:%vreg103
7056B		STRXui %vreg102, %vreg103, 24; mem:ST8[%fn_data] GPR64:%vreg102 GPR64common:%vreg103
7072B		%vreg104<def> = LDRWui <fi#6>, 0; mem:LD4[%flags.addr] GPR32:%vreg104
7088B		%vreg105<def> = UBFMWri %vreg104, 1, 1; GPR32:%vreg105,%vreg104
7104B		%vreg106<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64common:%vreg106
7120B		STRBBui %vreg105, %vreg106, 205; mem:ST1[%final_task116] GPR32:%vreg105 GPR64common:%vreg106
7136B		%vreg107<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg107
7152B		%vreg108<def> = ADDXri %vreg107, 1280, 0; GPR64sp:%vreg108 GPR64common:%vreg107
7168B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
7184B		%X0<def> = COPY %vreg108; GPR64sp:%vreg108
7200B		BL <ga:@gomp_mutex_lock>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...
7216B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
7232B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
7248B		STACKMAP 18, 0, 0, <fi#7>, 0, 0, <fi#19>, 0, 0, <fi#18>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#14>, 0, 0, <fi#16>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack7] LD8[FixedStack19] LD8[FixedStack18](align=1) LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack14] LD8[FixedStack16] LD8[FixedStack10]
7264B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
7280B		%vreg109<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg109
7296B		%vreg110<def> = ADDXri %vreg109, 128, 0; GPR64sp:%vreg110 GPR64common:%vreg109
7312B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
7328B		%X0<def> = COPY %vreg110; GPR64sp:%vreg110
7344B		BL <ga:@gomp_team_barrier_cancelled>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>, ...
7360B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
7376B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
7392B		STACKMAP 19, 0, 0, <fi#7>, 0, 0, <fi#19>, 0, 0, <fi#18>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#14>, 0, 0, <fi#16>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack7] LD8[FixedStack19] LD8[FixedStack18](align=1) LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack14] LD8[FixedStack16] LD8[FixedStack10]
7408B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
7424B		%vreg111<def> = COPY %W0; GPR32:%vreg111
7440B		TBNZW %vreg111, 0, <BB#38>; GPR32:%vreg111
7456B		B <BB#36>
	    Successors according to CFG: BB#38 BB#36

7472B	BB#36: derived from LLVM BB %lor.lhs.false.122
	    Predecessors according to CFG: BB#35
7488B		%vreg113<def> = LDRXui <fi#16>, 0; mem:LD8[%taskgroup79] GPR64:%vreg113
7504B		%vreg114<def> = COPY %WZR; GPR32all:%vreg114
7520B		%vreg112<def> = COPY %vreg114; GPR32all:%vreg112,%vreg114
7536B		%vreg256<def> = COPY %vreg112; GPR32:%vreg256 GPR32all:%vreg112
7552B		CBZX %vreg113, <BB#39>; GPR64:%vreg113
7568B		B <BB#37>
	    Successors according to CFG: BB#37 BB#39

7584B	BB#37: derived from LLVM BB %land.lhs.true.124
	    Predecessors according to CFG: BB#36
7600B		%vreg116<def> = LDRXui <fi#16>, 0; mem:LD8[%taskgroup79] GPR64common:%vreg116
7616B		%vreg117<def> = LDRBBui %vreg116, 41; mem:LD1[%cancelled125] GPR32:%vreg117 GPR64common:%vreg116
7632B		%vreg118<def> = COPY %WZR; GPR32all:%vreg118
7648B		%vreg115<def> = COPY %vreg118; GPR32all:%vreg115,%vreg118
7664B		%vreg256<def> = COPY %vreg115; GPR32:%vreg256 GPR32all:%vreg115
7680B		TBZW %vreg117, 0, <BB#39>; GPR32:%vreg117
7696B		B <BB#38>
	    Successors according to CFG: BB#38 BB#39

7712B	BB#38: derived from LLVM BB %land.rhs
	    Predecessors according to CFG: BB#35 BB#37
7728B		%vreg119<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64common:%vreg119
7744B		%vreg120<def> = LDRBBui %vreg119, 206; mem:LD1[%copy_ctors_done128] GPR32:%vreg120 GPR64common:%vreg119
7760B		%vreg121<def> = EORWri %vreg120, 0; GPR32sp:%vreg121 GPR32:%vreg120
7776B		%vreg2<def> = COPY %vreg121; GPR32all:%vreg2 GPR32sp:%vreg121
7792B		%vreg256<def> = COPY %vreg2; GPR32:%vreg256 GPR32all:%vreg2
7808B		B <BB#39>
	    Successors according to CFG: BB#39

7824B	BB#39: derived from LLVM BB %land.end
	    Predecessors according to CFG: BB#36 BB#37 BB#38
7840B		%vreg3<def> = COPY %vreg256; GPR32:%vreg3,%vreg256
7856B		TBZW %vreg3, 0, <BB#41>; GPR32:%vreg3
7872B		B <BB#40>
	    Successors according to CFG: BB#40 BB#41

7888B	BB#40: derived from LLVM BB %if.then.132
	    Predecessors according to CFG: BB#39
7904B		%vreg183<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg183
7920B		%vreg184<def> = ADDXri %vreg183, 1280, 0; GPR64sp:%vreg184 GPR64common:%vreg183
7936B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
7952B		%X0<def> = COPY %vreg184; GPR64sp:%vreg184
7968B		BL <ga:@gomp_mutex_unlock>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...
7984B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
8000B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
8016B		STACKMAP 20, 0, 0, <fi#14>, 0, ...; mem:LD8[FixedStack14]
8032B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
8048B		%vreg185<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64:%vreg185
8064B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
8080B		%X0<def> = COPY %vreg185; GPR64:%vreg185
8096B		BL <ga:@gomp_finish_task>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...
8112B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
8128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
8144B		STACKMAP 21, 0, 0, <fi#14>, 0, ...; mem:LD8[FixedStack14]
8160B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
8176B		%vreg186<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64:%vreg186
8192B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
8208B		%X0<def> = COPY %vreg186; GPR64:%vreg186
8224B		BL <ga:@free>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...
8240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
8256B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
8272B		STACKMAP 22, 0, ...
8288B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
8304B		B <BB#52>
	    Successors according to CFG: BB#52

8320B	BB#41: derived from LLVM BB %if.end.134
	    Predecessors according to CFG: BB#39
8336B		%vreg122<def> = LDRXui <fi#16>, 0; mem:LD8[%taskgroup79] GPR64:%vreg122
8352B		CBZX %vreg122, <BB#43>; GPR64:%vreg122
8368B		B <BB#42>
	    Successors according to CFG: BB#42 BB#43

8384B	BB#42: derived from LLVM BB %if.then.136
	    Predecessors according to CFG: BB#41
8400B		%vreg123<def> = LDRXui <fi#16>, 0; mem:LD8[%taskgroup79] GPR64common:%vreg123
8416B		%vreg124<def> = LDRXui %vreg123, 6; mem:LD8[%num_children] GPR64common:%vreg124,%vreg123
8432B		%vreg125<def> = ADDXri %vreg124, 1, 0; GPR64common:%vreg125,%vreg124
8448B		STRXui %vreg125, %vreg123, 6; mem:ST8[%num_children] GPR64common:%vreg125,%vreg123
8464B		B <BB#43>
	    Successors according to CFG: BB#43

8480B	BB#43: derived from LLVM BB %if.end.137
	    Predecessors according to CFG: BB#41 BB#42
8496B		%vreg126<def> = LDRXui <fi#19>, 0; mem:LD8[%depend_size] GPR64:%vreg126
8512B		CBZX %vreg126, <BB#47>; GPR64:%vreg126
8528B		B <BB#44>
	    Successors according to CFG: BB#44 BB#47

8544B	BB#44: derived from LLVM BB %if.then.139
	    Predecessors according to CFG: BB#43
8560B		%vreg127<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64:%vreg127
8576B		%vreg128<def> = LDRXui <fi#15>, 0; mem:LD8[%parent] GPR64:%vreg128
8592B		%vreg129<def> = LDRXui <fi#7>, 0; mem:LD8[%depend.addr] GPR64:%vreg129
8608B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
8624B		%X0<def> = COPY %vreg127; GPR64:%vreg127
8640B		%X1<def> = COPY %vreg128; GPR64:%vreg128
8656B		%X2<def> = COPY %vreg129; GPR64:%vreg129
8672B		BL <ga:@gomp_task_handle_depend>, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %X2<imp-use>, %SP<imp-def>, ...
8688B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
8704B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
8720B		STACKMAP 23, 0, 0, <fi#18>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#14>, 0, 0, <fi#16>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack18](align=1) LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack14] LD8[FixedStack16] LD8[FixedStack10]
8736B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
8752B		%vreg130<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64common:%vreg130
8768B		%vreg131<def> = LDRXui %vreg130, 10; mem:LD8[%num_dependees] GPR64:%vreg131 GPR64common:%vreg130
8784B		CBZX %vreg131, <BB#46>; GPR64:%vreg131
8800B		B <BB#45>
	    Successors according to CFG: BB#45 BB#46

8816B	BB#45: derived from LLVM BB %if.then.141
	    Predecessors according to CFG: BB#44
8832B		%vreg181<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg181
8848B		%vreg182<def> = ADDXri %vreg181, 1280, 0; GPR64sp:%vreg182 GPR64common:%vreg181
8864B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
8880B		%X0<def> = COPY %vreg182; GPR64sp:%vreg182
8896B		BL <ga:@gomp_mutex_unlock>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...
8912B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
8928B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
8944B		STACKMAP 24, 0, ...
8960B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
8976B		B <BB#52>
	    Successors according to CFG: BB#52

8992B	BB#46: derived from LLVM BB %if.end.143
	    Predecessors according to CFG: BB#44
9008B		B <BB#47>
	    Successors according to CFG: BB#47

9024B	BB#47: derived from LLVM BB %if.end.144
	    Predecessors according to CFG: BB#43 BB#46
9040B		%vreg132<def> = LDRXui <fi#15>, 0; mem:LD8[%parent] GPR64common:%vreg132
9056B		%vreg133<def> = ADDXri %vreg132, 8, 0; GPR64sp:%vreg133 GPR64common:%vreg132
9072B		%vreg134<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64common:%vreg134
9088B		%vreg135<def> = LDRWui <fi#8>, 0; mem:LD4[%priority.addr] GPR32:%vreg135
9104B		%vreg136<def> = LDRBBui %vreg134, 207; mem:LD1[%parent_depends_on] GPR32:%vreg136 GPR64common:%vreg134
9120B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
9136B		%vreg137<def> = ANDWri %vreg136, 0; GPR32sp:%vreg137 GPR32:%vreg136
9152B		%vreg138<def> = MOVi32imm 1; GPR32:%vreg138
9168B		%vreg139<def> = COPY %WZR; GPR32all:%vreg139
9184B		%W0<def> = COPY %vreg138; GPR32:%vreg138
9200B		%X1<def> = COPY %vreg133; GPR64sp:%vreg133
9216B		%X2<def> = COPY %vreg134; GPR64common:%vreg134
9232B		%W3<def> = COPY %vreg135; GPR32:%vreg135
9248B		%W4<def> = COPY %vreg139; GPR32all:%vreg139
9264B		%W5<def> = COPY %vreg139; GPR32all:%vreg139
9280B		%W6<def> = COPY %vreg137; GPR32sp:%vreg137
9296B		BL <ga:@priority_queue_insert>, <regmask>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use>, %X2<imp-use>, %W3<imp-use>, %W4<imp-use>, %W5<imp-use>, %W6<imp-use>, %SP<imp-def>, ...
9312B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
9328B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
9344B		STACKMAP 25, 0, 0, <fi#18>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#14>, 0, 0, <fi#16>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack18](align=1) LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack14] LD8[FixedStack16] LD8[FixedStack10]
9360B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
9376B		%vreg140<def> = LDRXui <fi#16>, 0; mem:LD8[%taskgroup79] GPR64:%vreg140
9392B		CBZX %vreg140, <BB#49>; GPR64:%vreg140
9408B		B <BB#48>
	    Successors according to CFG: BB#48 BB#49

9424B	BB#48: derived from LLVM BB %if.then.148
	    Predecessors according to CFG: BB#47
9440B		%vreg141<def> = LDRXui <fi#16>, 0; mem:LD8[%taskgroup79] GPR64common:%vreg141
9456B		%vreg142<def> = ADDXri %vreg141, 8, 0; GPR64sp:%vreg142 GPR64common:%vreg141
9472B		%vreg143<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64common:%vreg143
9488B		%vreg144<def> = LDRWui <fi#8>, 0; mem:LD4[%priority.addr] GPR32:%vreg144
9504B		%vreg145<def> = LDRBBui %vreg143, 207; mem:LD1[%parent_depends_on149] GPR32:%vreg145 GPR64common:%vreg143
9520B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
9536B		%vreg146<def> = ANDWri %vreg145, 0; GPR32sp:%vreg146 GPR32:%vreg145
9552B		%vreg147<def> = MOVi32imm 2; GPR32:%vreg147
9568B		%vreg148<def> = COPY %WZR; GPR32all:%vreg148
9584B		%W0<def> = COPY %vreg147; GPR32:%vreg147
9600B		%X1<def> = COPY %vreg142; GPR64sp:%vreg142
9616B		%X2<def> = COPY %vreg143; GPR64common:%vreg143
9632B		%W3<def> = COPY %vreg144; GPR32:%vreg144
9648B		%W4<def> = COPY %vreg148; GPR32all:%vreg148
9664B		%W5<def> = COPY %vreg148; GPR32all:%vreg148
9680B		%W6<def> = COPY %vreg146; GPR32sp:%vreg146
9696B		BL <ga:@priority_queue_insert>, <regmask>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use>, %X2<imp-use>, %W3<imp-use>, %W4<imp-use>, %W5<imp-use>, %W6<imp-use>, %SP<imp-def>, ...
9712B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
9728B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
9744B		STACKMAP 26, 0, 0, <fi#18>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#14>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack18](align=1) LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack14] LD8[FixedStack10]
9760B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
9776B		B <BB#49>
	    Successors according to CFG: BB#49

9792B	BB#49: derived from LLVM BB %if.end.151
	    Predecessors according to CFG: BB#47 BB#48
9808B		%vreg149<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg149
9824B		%vreg150<def> = ADDXri %vreg149, 1288, 0; GPR64sp:%vreg150 GPR64common:%vreg149
9840B		%vreg151<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64common:%vreg151
9856B		%vreg152<def> = LDRWui <fi#8>, 0; mem:LD4[%priority.addr] GPR32:%vreg152
9872B		%vreg153<def> = LDRBBui %vreg151, 207; mem:LD1[%parent_depends_on152] GPR32:%vreg153 GPR64common:%vreg151
9888B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
9904B		%vreg154<def> = ANDWri %vreg153, 0; GPR32sp:%vreg154 GPR32:%vreg153
9920B		%vreg155<def> = MOVi32imm 1; GPR32:%vreg155
9936B		%vreg156<def> = COPY %WZR; GPR32all:%vreg156
9952B		%W0<def> = COPY %vreg156; GPR32all:%vreg156
9968B		%X1<def> = COPY %vreg150; GPR64sp:%vreg150
9984B		%X2<def> = COPY %vreg151; GPR64common:%vreg151
10000B		%W3<def> = COPY %vreg152; GPR32:%vreg152
10016B		%W4<def> = COPY %vreg155; GPR32:%vreg155
10032B		%W5<def> = COPY %vreg156; GPR32all:%vreg156
10048B		%W6<def> = COPY %vreg154; GPR32sp:%vreg154
10064B		BL <ga:@priority_queue_insert>, <regmask>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use>, %X2<imp-use>, %W3<imp-use>, %W4<imp-use>, %W5<imp-use>, %W6<imp-use>, %SP<imp-def>, ...
10080B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
10096B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
10112B		STACKMAP 27, 0, 0, <fi#18>, 0, 0, <fi#15>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack18](align=1) LD8[FixedStack15] LD8[FixedStack10]
10128B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
10144B		%vreg157<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg157
10160B		%vreg158<def> = LDRWui %vreg157, 330; mem:LD4[%task_count154] GPR32common:%vreg158 GPR64common:%vreg157
10176B		%vreg159<def> = ADDWri %vreg158, 1, 0; GPR32common:%vreg159,%vreg158
10192B		STRWui %vreg159, %vreg157, 330; mem:ST4[%task_count154] GPR32common:%vreg159 GPR64common:%vreg157
10208B		%vreg160<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg160
10224B		%vreg161<def> = LDRWui %vreg160, 331; mem:LD4[%task_queued_count] GPR32common:%vreg161 GPR64common:%vreg160
10240B		%vreg162<def> = ADDWri %vreg161, 1, 0; GPR32common:%vreg162,%vreg161
10256B		STRWui %vreg162, %vreg160, 331; mem:ST4[%task_queued_count] GPR32common:%vreg162 GPR64common:%vreg160
10272B		%vreg163<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg163
10288B		%vreg164<def> = ADDXri %vreg163, 128, 0; GPR64sp:%vreg164 GPR64common:%vreg163
10304B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
10320B		%X0<def> = COPY %vreg164; GPR64sp:%vreg164
10336B		BL <ga:@gomp_team_barrier_set_task_pending>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...
10352B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
10368B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
10384B		STACKMAP 28, 0, 0, <fi#18>, 0, 0, <fi#15>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack18](align=1) LD8[FixedStack15] LD8[FixedStack10]
10400B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
10416B		%vreg165<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg165
10432B		%vreg166<def> = LDRWui %vreg165, 332; mem:LD4[%task_running_count] GPR32:%vreg166 GPR64common:%vreg165
10448B		%vreg167<def> = LDRXui <fi#15>, 0; mem:LD8[%parent] GPR64common:%vreg167
10464B		%vreg168<def> = LDRBBui %vreg167, 204; mem:LD1[%in_tied_task158] GPR32:%vreg168 GPR64common:%vreg167
10480B		%vreg169<def> = ORNWrr %WZR, %vreg168; GPR32:%vreg169,%vreg168
10496B		%vreg170<def> = ANDWri %vreg169, 0; GPR32common:%vreg170 GPR32:%vreg169
10512B		%vreg171<def> = ADDWrr %vreg166, %vreg170; GPR32:%vreg171,%vreg166 GPR32common:%vreg170
10528B		%vreg172<def> = LDRWui %vreg165, 0; mem:LD4[%nthreads162] GPR32:%vreg172 GPR64common:%vreg165
10544B		%vreg173<def,dead> = SUBSWrr %vreg171, %vreg172, %NZCV<imp-def>; GPR32:%vreg173,%vreg171,%vreg172
10560B		%vreg174<def> = CSINCWr %WZR, %WZR, 2, %NZCV<imp-use,kill>; GPR32:%vreg174
10576B		STRBBui %vreg174, <fi#18>, 0; mem:ST1[%do_wake] GPR32:%vreg174
10592B		%vreg175<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg175
10608B		%vreg176<def> = ADDXri %vreg175, 1280, 0; GPR64sp:%vreg176 GPR64common:%vreg175
10624B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
10640B		%X0<def> = COPY %vreg176; GPR64sp:%vreg176
10656B		BL <ga:@gomp_mutex_unlock>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...
10672B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
10688B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
10704B		STACKMAP 29, 0, 0, <fi#18>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack18](align=1) LD8[FixedStack10]
10720B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
10736B		%vreg177<def> = LDRBBui <fi#18>, 0; mem:LD1[%do_wake] GPR32:%vreg177
10752B		TBZW %vreg177, 0, <BB#51>; GPR32:%vreg177
10768B		B <BB#50>
	    Successors according to CFG: BB#50 BB#51

10784B	BB#50: derived from LLVM BB %if.then.168
	    Predecessors according to CFG: BB#49
10800B		%vreg178<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg178
10816B		%vreg179<def> = ADDXri %vreg178, 128, 0; GPR64sp:%vreg179 GPR64common:%vreg178
10832B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
10848B		%vreg180<def> = MOVi32imm 1; GPR32:%vreg180
10864B		%X0<def> = COPY %vreg179; GPR64sp:%vreg179
10880B		%W1<def> = COPY %vreg180; GPR32:%vreg180
10896B		BL <ga:@gomp_team_barrier_wake>, <regmask>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %SP<imp-def>, ...
10912B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
10928B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
10944B		STACKMAP 30, 0, ...
10960B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
10976B		B <BB#51>
	    Successors according to CFG: BB#51

10992B	BB#51: derived from LLVM BB %if.end.170
	    Predecessors according to CFG: BB#49 BB#50
11008B		B <BB#52>
	    Successors according to CFG: BB#52

11024B	BB#52: derived from LLVM BB %if.end.171
	    Predecessors according to CFG: BB#51 BB#45 BB#40 BB#29 BB#4
11040B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
11056B		%vreg254<def> = COPY %XZR; GPR64all:%vreg254
11072B		%X0<def> = COPY %vreg254; GPR64all:%vreg254
11088B		%X1<def> = COPY %vreg254; GPR64all:%vreg254
11104B		BL <ga:@check_migrate>, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %SP<imp-def>, ...
11120B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
11136B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
11152B		STACKMAP 31, 0, ...
11168B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
11184B		RET_ReallyLR

# End machine code for function GOMP_task.

********** SIMPLE REGISTER COALESCING **********
********** Function: GOMP_task
********** JOINING INTERVALS ***********
if.then.24:
if.end.35:
2352B	%vreg196<def> = COPY %WZR; GPR32all:%vreg196
	Considering merging %vreg196 with %WZR
		RHS = %vreg196 [2352r,2368r:0)  0@2352r
		updated: 2368B	%W0<def> = COPY %WZR
	Success: %vreg196 -> %WZR
	Result = %WZR
2368B	%W0<def> = COPY %WZR
	Not coalescable.
2464B	%vreg197<def> = COPY %X0; GPR64all:%vreg197
	Considering merging %vreg197 with %X0
	Can only merge into reserved registers.
2512B	%X0<def> = COPY %vreg198; GPR64sp:%vreg198
	Considering merging %vreg198 with %X0
	Can only merge into reserved registers.
Remat: %X0<def> = ADDXri <fi#11>, 0, 0
Shrink: %vreg198 [2496r,2512r:0)  0@2496r
All defs dead: 2496r	%vreg198<def,dead> = ADDXri <fi#11>, 0, 0; GPR64sp:%vreg198
Shrunk: %vreg198 [2496r,2496d:0)  0@2496r
Deleting dead def 2496r	%vreg198<def,dead> = ADDXri <fi#11>, 0, 0; GPR64sp:%vreg198
2528B	%X1<def> = COPY %vreg195; GPR64:%vreg195
	Considering merging %vreg195 with %X1
	Can only merge into reserved registers.
2544B	%X2<def> = COPY %vreg197; GPR64all:%vreg197
	Considering merging %vreg197 with %X2
	Can only merge into reserved registers.
if.end:
land.end:
if.end.171:
11056B	%vreg254<def> = COPY %XZR; GPR64all:%vreg254
	Considering merging %vreg254 with %XZR
		RHS = %vreg254 [11056r,11088r:0)  0@11056r
		updated: 11072B	%X0<def> = COPY %XZR
		updated: 11088B	%X1<def> = COPY %XZR
	Success: %vreg254 -> %XZR
	Result = %XZR
11072B	%X0<def> = COPY %XZR
	Not coalescable.
11088B	%X1<def> = COPY %XZR
	Not coalescable.
if.end.12:
lor.lhs.false.22:
lor.end:
if.end.59:
if.end.70:
4336B	%vreg246<def> = COPY %WZR; GPR32all:%vreg246
	Considering merging %vreg246 with %WZR
		RHS = %vreg246 [4336r,4368r:0)  0@4336r
		updated: 4368B	%W1<def> = COPY %WZR
	Success: %vreg246 -> %WZR
	Result = %WZR
4352B	%X0<def> = COPY %vreg245; GPR64sp:%vreg245
	Considering merging %vreg245 with %X0
	Can only merge into reserved registers.
4368B	%W1<def> = COPY %WZR
	Not coalescable.
4464B	%vreg247<def> = COPY %W0; GPR32:%vreg247
	Considering merging %vreg247 with %W0
	Can only merge into reserved registers.
if.end.86:
5536B	%X0<def> = COPY %vreg62; GPR64sp:%vreg62
	Considering merging %vreg62 with %X0
	Can only merge into reserved registers.
5632B	%vreg63<def> = COPY %X0; GPR64:%vreg63
	Considering merging %vreg63 with %X0
	Can only merge into reserved registers.
5840B	%vreg73<def> = COPY %WZR; GPR32all:%vreg73
	Considering merging %vreg73 with %WZR
		RHS = %vreg73 [5840r,5856r:0)  0@5840r
		updated: 5856B	%W0<def> = COPY %WZR
	Success: %vreg73 -> %WZR
	Result = %WZR
5856B	%W0<def> = COPY %WZR
	Not coalescable.
5952B	%vreg74<def> = COPY %X0; GPR64all:%vreg74
	Considering merging %vreg74 with %X0
	Can only merge into reserved registers.
5984B	%X0<def> = COPY %vreg71; GPR64:%vreg71
	Considering merging %vreg71 with %X0
	Can only merge into reserved registers.
6000B	%X1<def> = COPY %vreg72; GPR64:%vreg72
	Considering merging %vreg72 with %X1
	Can only merge into reserved registers.
6016B	%X2<def> = COPY %vreg74; GPR64all:%vreg74
	Considering merging %vreg74 with %X2
	Can only merge into reserved registers.
if.end.110:
7184B	%X0<def> = COPY %vreg108; GPR64sp:%vreg108
	Considering merging %vreg108 with %X0
	Can only merge into reserved registers.
7328B	%X0<def> = COPY %vreg110; GPR64sp:%vreg110
	Considering merging %vreg110 with %X0
	Can only merge into reserved registers.
7424B	%vreg111<def> = COPY %W0; GPR32:%vreg111
	Considering merging %vreg111 with %W0
	Can only merge into reserved registers.
if.end.137:
if.end.144:
9168B	%vreg139<def> = COPY %WZR; GPR32all:%vreg139
	Considering merging %vreg139 with %WZR
		RHS = %vreg139 [9168r,9264r:0)  0@9168r
		updated: 9248B	%W4<def> = COPY %WZR
		updated: 9264B	%W5<def> = COPY %WZR
	Success: %vreg139 -> %WZR
	Result = %WZR
9184B	%W0<def> = COPY %vreg138; GPR32:%vreg138
	Considering merging %vreg138 with %W0
	Can only merge into reserved registers.
Remat: %W0<def> = MOVi32imm 1
Shrink: %vreg138 [9152r,9184r:0)  0@9152r
All defs dead: 9152r	%vreg138<def,dead> = MOVi32imm 1; GPR32:%vreg138
Shrunk: %vreg138 [9152r,9152d:0)  0@9152r
Deleting dead def 9152r	%vreg138<def,dead> = MOVi32imm 1; GPR32:%vreg138
9200B	%X1<def> = COPY %vreg133; GPR64sp:%vreg133
	Considering merging %vreg133 with %X1
	Can only merge into reserved registers.
9216B	%X2<def> = COPY %vreg134; GPR64common:%vreg134
	Considering merging %vreg134 with %X2
	Can only merge into reserved registers.
9232B	%W3<def> = COPY %vreg135; GPR32:%vreg135
	Considering merging %vreg135 with %W3
	Can only merge into reserved registers.
9248B	%W4<def> = COPY %WZR
	Not coalescable.
9264B	%W5<def> = COPY %WZR
	Not coalescable.
9280B	%W6<def> = COPY %vreg137; GPR32sp:%vreg137
	Considering merging %vreg137 with %W6
	Can only merge into reserved registers.
if.end.151:
9936B	%vreg156<def> = COPY %WZR; GPR32all:%vreg156
	Considering merging %vreg156 with %WZR
		RHS = %vreg156 [9936r,10032r:0)  0@9936r
		updated: 9952B	%W0<def> = COPY %WZR
		updated: 10032B	%W5<def> = COPY %WZR
	Success: %vreg156 -> %WZR
	Result = %WZR
9952B	%W0<def> = COPY %WZR
	Not coalescable.
9968B	%X1<def> = COPY %vreg150; GPR64sp:%vreg150
	Considering merging %vreg150 with %X1
	Can only merge into reserved registers.
9984B	%X2<def> = COPY %vreg151; GPR64common:%vreg151
	Considering merging %vreg151 with %X2
	Can only merge into reserved registers.
10000B	%W3<def> = COPY %vreg152; GPR32:%vreg152
	Considering merging %vreg152 with %W3
	Can only merge into reserved registers.
10016B	%W4<def> = COPY %vreg155; GPR32:%vreg155
	Considering merging %vreg155 with %W4
	Can only merge into reserved registers.
Remat: %W4<def> = MOVi32imm 1
Shrink: %vreg155 [9920r,10016r:0)  0@9920r
All defs dead: 9920r	%vreg155<def,dead> = MOVi32imm 1; GPR32:%vreg155
Shrunk: %vreg155 [9920r,9920d:0)  0@9920r
Deleting dead def 9920r	%vreg155<def,dead> = MOVi32imm 1; GPR32:%vreg155
10032B	%W5<def> = COPY %WZR
	Not coalescable.
10048B	%W6<def> = COPY %vreg154; GPR32sp:%vreg154
	Considering merging %vreg154 with %W6
	Can only merge into reserved registers.
10320B	%X0<def> = COPY %vreg164; GPR64sp:%vreg164
	Considering merging %vreg164 with %X0
	Can only merge into reserved registers.
10640B	%X0<def> = COPY %vreg176; GPR64sp:%vreg176
	Considering merging %vreg176 with %X0
	Can only merge into reserved registers.
land.lhs.true:
720B	%X0<def> = COPY %vreg18; GPR64sp:%vreg18
	Considering merging %vreg18 with %X0
	Can only merge into reserved registers.
816B	%vreg19<def> = COPY %W0; GPR32:%vreg19
	Considering merging %vreg19 with %W0
	Can only merge into reserved registers.
lor.lhs.false:
land.lhs.true.4:
if.then:
if.else:
if.end.11:
lor.lhs.false.14:
lor.lhs.false.16:
land.lhs.true.19:
land.lhs.true.28:
land.lhs.true.31:
land.lhs.true.40:
lor.rhs:
if.end.75:
if.else.76:
5200B	%vreg50<def> = COPY %XZR; GPR64:%vreg50
	Considering merging %vreg50 with %XZR
		RHS = %vreg50 [5200r,5216r:0)  0@5200r
		updated: 5216B	STRXui %XZR, <fi#19>, 0; mem:ST8[%depend_size]
	Success: %vreg50 -> %XZR
	Result = %XZR
lor.lhs.false.122:
7504B	%vreg114<def> = COPY %WZR; GPR32all:%vreg114
	Considering merging %vreg114 with %WZR
		RHS = %vreg114 [7504r,7520r:0)  0@7504r
		updated: 7520B	%vreg112<def> = COPY %WZR; GPR32all:%vreg112
	Success: %vreg114 -> %WZR
	Result = %WZR
land.lhs.true.124:
7632B	%vreg118<def> = COPY %WZR; GPR32all:%vreg118
	Considering merging %vreg118 with %WZR
		RHS = %vreg118 [7632r,7648r:0)  0@7632r
		updated: 7648B	%vreg115<def> = COPY %WZR; GPR32all:%vreg115
	Success: %vreg118 -> %WZR
	Result = %WZR
land.rhs:
if.end.134:
if.then.139:
8624B	%X0<def> = COPY %vreg127; GPR64:%vreg127
	Considering merging %vreg127 with %X0
	Can only merge into reserved registers.
8640B	%X1<def> = COPY %vreg128; GPR64:%vreg128
	Considering merging %vreg128 with %X1
	Can only merge into reserved registers.
8656B	%X2<def> = COPY %vreg129; GPR64:%vreg129
	Considering merging %vreg129 with %X2
	Can only merge into reserved registers.
if.end.170:
entry:
16B	%vreg11<def> = COPY %X7; GPR64:%vreg11
	Considering merging %vreg11 with %X7
	Can only merge into reserved registers.
32B	%vreg10<def> = COPY %W6; GPR32:%vreg10
	Considering merging %vreg10 with %W6
	Can only merge into reserved registers.
48B	%vreg9<def> = COPY %W5; GPR32:%vreg9
	Considering merging %vreg9 with %W5
	Can only merge into reserved registers.
64B	%vreg8<def> = COPY %X4; GPR64:%vreg8
	Considering merging %vreg8 with %X4
	Can only merge into reserved registers.
80B	%vreg7<def> = COPY %X3; GPR64:%vreg7
	Considering merging %vreg7 with %X3
	Can only merge into reserved registers.
96B	%vreg6<def> = COPY %X2; GPR64:%vreg6
	Considering merging %vreg6 with %X2
	Can only merge into reserved registers.
112B	%vreg5<def> = COPY %X1; GPR64:%vreg5
	Considering merging %vreg5 with %X1
	Can only merge into reserved registers.
128B	%vreg4<def> = COPY %X0; GPR64:%vreg4
	Considering merging %vreg4 with %X0
	Can only merge into reserved registers.
192B	%vreg14<def> = COPY %XZR; GPR64all:%vreg14
	Considering merging %vreg14 with %XZR
		RHS = %vreg14 [192r,224r:0)  0@192r
		updated: 208B	%X0<def> = COPY %XZR
		updated: 224B	%X1<def> = COPY %XZR
	Success: %vreg14 -> %XZR
	Result = %XZR
208B	%X0<def> = COPY %XZR
	Not coalescable.
224B	%X1<def> = COPY %XZR
	Not coalescable.
560B	%vreg15<def> = COPY %X0; GPR64common:%vreg15
	Considering merging %vreg15 with %X0
	Can only merge into reserved registers.
if.then.8:
1184B	%vreg34<def> = COPY %WZR; GPR32:%vreg34
	Considering merging %vreg34 with %WZR
		RHS = %vreg34 [1184r,1200r:0)  0@1184r
		updated: 1200B	STRWui %WZR, <fi#8>, 0; mem:ST4[%priority.addr]
	Success: %vreg34 -> %WZR
	Result = %WZR
if.then.10:
if.then.34:
2176B	%X0<def> = COPY %vreg193; GPR64:%vreg193
	Considering merging %vreg193 with %X0
	Can only merge into reserved registers.
if.then.51:
if.then.64:
3504B	%vreg229<def> = COPY %SP; GPR64:%vreg229
	Not coalescable.
3584B	%vreg232<def> = COPY %SP; GPR64:%vreg232
	Not coalescable.
3616B	%SP<def> = COPY %vreg233; GPR64:%vreg233
	Not coalescable.
3792B	%X0<def> = COPY %vreg238; GPR64:%vreg238
	Considering merging %vreg238 with %X0
	Can only merge into reserved registers.
3808B	%X1<def> = COPY %vreg240; GPR64:%vreg240
	Considering merging %vreg240 with %X1
	Can only merge into reserved registers.
3952B	%X0<def> = COPY %vreg242; GPR64:%vreg242
	Considering merging %vreg242 with %X0
	Can only merge into reserved registers.
4064B	%SP<def> = COPY %vreg243; GPR64:%vreg243
	Not coalescable.
if.else.69:
4160B	%X0<def> = COPY %vreg225; GPR64:%vreg225
	Considering merging %vreg225 with %X0
	Can only merge into reserved registers.
if.then.72:
4576B	%X0<def> = COPY %vreg249; GPR64sp:%vreg249
	Considering merging %vreg249 with %X0
	Can only merge into reserved registers.
4720B	%X0<def> = COPY %vreg251; GPR64sp:%vreg251
	Considering merging %vreg251 with %X0
	Can only merge into reserved registers.
4864B	%X0<def> = COPY %vreg253; GPR64sp:%vreg253
	Considering merging %vreg253 with %X0
	Can only merge into reserved registers.
if.then.84:
5344B	%vreg55<def> = SUBREG_TO_REG 0, %vreg54, 15; GPR64:%vreg55 GPR32:%vreg54
	Considering merging to GPR64 with %vreg54 in %vreg55:sub_32
		RHS = %vreg54 [5328r,5344r:0)  0@5328r
		LHS = %vreg55 [5344r,5360r:0)  0@5344r
		merge %vreg55:0@5344r into %vreg54:0@5328r --> @5328r
		erased:	5344r	%vreg55<def> = SUBREG_TO_REG 0, %vreg54, 15; GPR64:%vreg55 GPR32:%vreg54
AllocationOrder(GPR64) = [ %X8 %X9 %X10 %X11 %X12 %X13 %X14 %X15 %X16 %X17 %X18 %X0 %X1 %X2 %X3 %X4 %X5 %X6 %X7 %X19 %X20 %X21 %X22 %X23 %X24 %X25 %X26 %X27 %X28 %LR ]
		updated: 5328B	%vreg55:sub_32<def,read-undef> = MOVi32imm 40; GPR64:%vreg55
	Success: %vreg54:sub_32 -> %vreg55
	Result = %vreg55 [5328r,5360r:0)  0@5328r
if.then.108:
6512B	%X0<def> = COPY %vreg92; GPR64:%vreg92
	Considering merging %vreg92 with %X0
	Can only merge into reserved registers.
6528B	%X1<def> = COPY %vreg93; GPR64:%vreg93
	Considering merging %vreg93 with %X1
	Can only merge into reserved registers.
if.else.109:
6768B	%X0<def> = COPY %vreg88; GPR64:%vreg88
	Considering merging %vreg88 with %X0
	Can only merge into reserved registers.
6784B	%X1<def> = COPY %vreg89; GPR64:%vreg89
	Considering merging %vreg89 with %X1
	Can only merge into reserved registers.
6800B	%X2<def> = COPY %vreg90; GPR64:%vreg90
	Considering merging %vreg90 with %X2
	Can only merge into reserved registers.
if.then.132:
7952B	%X0<def> = COPY %vreg184; GPR64sp:%vreg184
	Considering merging %vreg184 with %X0
	Can only merge into reserved registers.
8080B	%X0<def> = COPY %vreg185; GPR64:%vreg185
	Considering merging %vreg185 with %X0
	Can only merge into reserved registers.
8208B	%X0<def> = COPY %vreg186; GPR64:%vreg186
	Considering merging %vreg186 with %X0
	Can only merge into reserved registers.
if.then.136:
if.then.141:
8880B	%X0<def> = COPY %vreg182; GPR64sp:%vreg182
	Considering merging %vreg182 with %X0
	Can only merge into reserved registers.
if.end.143:
if.then.148:
9568B	%vreg148<def> = COPY %WZR; GPR32all:%vreg148
	Considering merging %vreg148 with %WZR
		RHS = %vreg148 [9568r,9664r:0)  0@9568r
		updated: 9648B	%W4<def> = COPY %WZR
		updated: 9664B	%W5<def> = COPY %WZR
	Success: %vreg148 -> %WZR
	Result = %WZR
9584B	%W0<def> = COPY %vreg147; GPR32:%vreg147
	Considering merging %vreg147 with %W0
	Can only merge into reserved registers.
Remat: %W0<def> = MOVi32imm 2
Shrink: %vreg147 [9552r,9584r:0)  0@9552r
All defs dead: 9552r	%vreg147<def,dead> = MOVi32imm 2; GPR32:%vreg147
Shrunk: %vreg147 [9552r,9552d:0)  0@9552r
Deleting dead def 9552r	%vreg147<def,dead> = MOVi32imm 2; GPR32:%vreg147
9600B	%X1<def> = COPY %vreg142; GPR64sp:%vreg142
	Considering merging %vreg142 with %X1
	Can only merge into reserved registers.
9616B	%X2<def> = COPY %vreg143; GPR64common:%vreg143
	Considering merging %vreg143 with %X2
	Can only merge into reserved registers.
9632B	%W3<def> = COPY %vreg144; GPR32:%vreg144
	Considering merging %vreg144 with %W3
	Can only merge into reserved registers.
9648B	%W4<def> = COPY %WZR
	Not coalescable.
9664B	%W5<def> = COPY %WZR
	Not coalescable.
9680B	%W6<def> = COPY %vreg146; GPR32sp:%vreg146
	Considering merging %vreg146 with %W6
	Can only merge into reserved registers.
if.then.168:
10864B	%X0<def> = COPY %vreg179; GPR64sp:%vreg179
	Considering merging %vreg179 with %X0
	Can only merge into reserved registers.
10880B	%W1<def> = COPY %vreg180; GPR32:%vreg180
	Considering merging %vreg180 with %W1
	Can only merge into reserved registers.
Remat: %W1<def> = MOVi32imm 1
Shrink: %vreg180 [10848r,10880r:0)  0@10848r
All defs dead: 10848r	%vreg180<def,dead> = MOVi32imm 1; GPR32:%vreg180
Shrunk: %vreg180 [10848r,10848d:0)  0@10848r
Deleting dead def 10848r	%vreg180<def,dead> = MOVi32imm 1; GPR32:%vreg180
7840B	%vreg3<def> = COPY %vreg256; GPR32:%vreg3,%vreg256
	Considering merging to GPR32 with %vreg3 in %vreg256
		RHS = %vreg3 [7840r,7856r:0)  0@7840r
		LHS = %vreg256 [7536r,7584B:0)[7664r,7712B:1)[7792r,7824B:2)[7824B,7840r:3)  0@7536r 1@7664r 2@7792r 3@7824B-phi
		merge %vreg3:0@7840r into %vreg256:3@7824B --> @7824B
		erased:	7840r	%vreg3<def> = COPY %vreg256; GPR32:%vreg3,%vreg256
AllocationOrder(GPR32) = [ %W8 %W9 %W10 %W11 %W12 %W13 %W14 %W15 %W16 %W17 %W18 %W0 %W1 %W2 %W3 %W4 %W5 %W6 %W7 %W19 %W20 %W21 %W22 %W23 %W24 %W25 %W26 %W27 %W28 %W30 ]
		updated: 7856B	TBZW %vreg256, 0, <BB#41>; GPR32:%vreg256
	Success: %vreg3 -> %vreg256
	Result = %vreg256 [7536r,7584B:0)[7664r,7712B:1)[7792r,7824B:2)[7824B,7856r:3)  0@7536r 1@7664r 2@7792r 3@7824B-phi
3008B	%vreg1<def> = COPY %vreg255; GPR32:%vreg1,%vreg255
	Considering merging to GPR32 with %vreg1 in %vreg255
		RHS = %vreg1 [3008r,3024r:0)  0@3008r
		LHS = %vreg255 [2848r,2896B:0)[2960r,2992B:1)[2992B,3008r:2)  0@2848r 1@2960r 2@2992B-phi
		merge %vreg1:0@3008r into %vreg255:2@2992B --> @2992B
		erased:	3008r	%vreg1<def> = COPY %vreg255; GPR32:%vreg1,%vreg255
		updated: 3024B	%vreg210<def> = ANDWri %vreg255, 0; GPR32common:%vreg210 GPR32:%vreg255
	Success: %vreg1 -> %vreg255
	Result = %vreg255 [2848r,2896B:0)[2960r,2992B:1)[2992B,3024r:2)  0@2848r 1@2960r 2@2992B-phi
2832B	%vreg202<def> = COPY %vreg207; GPR32all:%vreg202 GPR32:%vreg207
	Considering merging to GPR32 with %vreg207 in %vreg202
		RHS = %vreg207 [2816r,2832r:0)  0@2816r
		LHS = %vreg202 [2832r,2848r:0)  0@2832r
		merge %vreg202:0@2832r into %vreg207:0@2816r --> @2816r
		erased:	2832r	%vreg202<def> = COPY %vreg207; GPR32all:%vreg202 GPR32:%vreg207
		updated: 2816B	%vreg202<def> = MOVi32imm 1; GPR32:%vreg202
	Success: %vreg207 -> %vreg202
	Result = %vreg202 [2816r,2848r:0)  0@2816r
2848B	%vreg255<def> = COPY %vreg202; GPR32:%vreg255,%vreg202
	Considering merging to GPR32 with %vreg202 in %vreg255
		RHS = %vreg202 [2816r,2848r:0)  0@2816r
		LHS = %vreg255 [2848r,2896B:0)[2960r,2992B:1)[2992B,3024r:2)  0@2848r 1@2960r 2@2992B-phi
		merge %vreg255:0@2848r into %vreg202:0@2816r --> @2816r
		erased:	2848r	%vreg255<def> = COPY %vreg202; GPR32:%vreg255,%vreg202
		updated: 2816B	%vreg255<def> = MOVi32imm 1; GPR32:%vreg255
	Success: %vreg202 -> %vreg255
	Result = %vreg255 [2816r,2896B:0)[2960r,2992B:1)[2992B,3024r:2)  0@2816r 1@2960r 2@2992B-phi
2944B	%vreg0<def> = COPY %vreg209; GPR32all:%vreg0 GPR32:%vreg209
	Considering merging to GPR32 with %vreg209 in %vreg0
		RHS = %vreg209 [2928r,2944r:0)  0@2928r
		LHS = %vreg0 [2944r,2960r:0)  0@2944r
		merge %vreg0:0@2944r into %vreg209:0@2928r --> @2928r
		erased:	2944r	%vreg0<def> = COPY %vreg209; GPR32all:%vreg0 GPR32:%vreg209
		updated: 2928B	%vreg0<def> = UBFMWri %vreg208, 1, 1; GPR32:%vreg0,%vreg208
	Success: %vreg209 -> %vreg0
	Result = %vreg0 [2928r,2960r:0)  0@2928r
2960B	%vreg255<def> = COPY %vreg0; GPR32:%vreg255,%vreg0
	Considering merging to GPR32 with %vreg0 in %vreg255
		RHS = %vreg0 [2928r,2960r:0)  0@2928r
		LHS = %vreg255 [2816r,2896B:0)[2960r,2992B:1)[2992B,3024r:2)  0@2816r 1@2960r 2@2992B-phi
		merge %vreg255:1@2960r into %vreg0:0@2928r --> @2928r
		erased:	2960r	%vreg255<def> = COPY %vreg0; GPR32:%vreg255,%vreg0
		updated: 2928B	%vreg255<def> = UBFMWri %vreg208, 1, 1; GPR32:%vreg255,%vreg208
	Success: %vreg0 -> %vreg255
	Result = %vreg255 [2816r,2896B:0)[2928r,2992B:1)[2992B,3024r:2)  0@2816r 1@2928r 2@2992B-phi
7520B	%vreg112<def> = COPY %WZR; GPR32all:%vreg112
	Considering merging %vreg112 with %WZR
		RHS = %vreg112 [7520r,7536r:0)  0@7520r
		updated: 7536B	%vreg256<def> = COPY %WZR; GPR32:%vreg256
	Success: %vreg112 -> %WZR
	Result = %WZR
7536B	%vreg256<def> = COPY %WZR; GPR32:%vreg256
	Considering merging %vreg256 with %WZR
	Cannot join complex intervals into reserved register.
7648B	%vreg115<def> = COPY %WZR; GPR32all:%vreg115
	Considering merging %vreg115 with %WZR
		RHS = %vreg115 [7648r,7664r:0)  0@7648r
		updated: 7664B	%vreg256<def> = COPY %WZR; GPR32:%vreg256
	Success: %vreg115 -> %WZR
	Result = %WZR
7664B	%vreg256<def> = COPY %WZR; GPR32:%vreg256
	Considering merging %vreg256 with %WZR
	Cannot join complex intervals into reserved register.
7776B	%vreg2<def> = COPY %vreg121; GPR32all:%vreg2 GPR32sp:%vreg121
	Considering merging to GPR32sp with %vreg121 in %vreg2
		RHS = %vreg121 [7760r,7776r:0)  0@7760r
		LHS = %vreg2 [7776r,7792r:0)  0@7776r
		merge %vreg2:0@7776r into %vreg121:0@7760r --> @7760r
		erased:	7776r	%vreg2<def> = COPY %vreg121; GPR32all:%vreg2 GPR32sp:%vreg121
AllocationOrder(GPR32sp) = [ %W8 %W9 %W10 %W11 %W12 %W13 %W14 %W15 %W16 %W17 %W18 %W0 %W1 %W2 %W3 %W4 %W5 %W6 %W7 %W19 %W20 %W21 %W22 %W23 %W24 %W25 %W26 %W27 %W28 %W30 ]
		updated: 7760B	%vreg2<def> = EORWri %vreg120, 0; GPR32sp:%vreg2 GPR32:%vreg120
	Success: %vreg121 -> %vreg2
	Result = %vreg2 [7760r,7792r:0)  0@7760r
7792B	%vreg256<def> = COPY %vreg2; GPR32:%vreg256 GPR32sp:%vreg2
	Considering merging to GPR32common with %vreg2 in %vreg256
		RHS = %vreg2 [7760r,7792r:0)  0@7760r
		LHS = %vreg256 [7536r,7584B:0)[7664r,7712B:1)[7792r,7824B:2)[7824B,7856r:3)  0@7536r 1@7664r 2@7792r 3@7824B-phi
		merge %vreg256:2@7792r into %vreg2:0@7760r --> @7760r
		erased:	7792r	%vreg256<def> = COPY %vreg2; GPR32:%vreg256 GPR32sp:%vreg2
AllocationOrder(GPR32common) = [ %W8 %W9 %W10 %W11 %W12 %W13 %W14 %W15 %W16 %W17 %W18 %W0 %W1 %W2 %W3 %W4 %W5 %W6 %W7 %W19 %W20 %W21 %W22 %W23 %W24 %W25 %W26 %W27 %W28 %W30 ]
		updated: 7760B	%vreg256<def> = EORWri %vreg120, 0; GPR32common:%vreg256 GPR32:%vreg120
	Success: %vreg2 -> %vreg256
	Result = %vreg256 [7536r,7584B:0)[7664r,7712B:1)[7760r,7824B:2)[7824B,7856r:3)  0@7536r 1@7664r 2@7760r 3@7824B-phi
2544B	%X2<def> = COPY %vreg197; GPR64all:%vreg197
	Considering merging %vreg197 with %X2
	Can only merge into reserved registers.
6016B	%X2<def> = COPY %vreg74; GPR64all:%vreg74
	Considering merging %vreg74 with %X2
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
WZR EMPTY
W0 [0B,128r:0)[208r,240r:38)[480r,560r:37)[720r,736r:36)[736r,816r:8)[2176r,2192r:19)[2368r,2384r:2)[2384r,2464r:18)[2512r,2560r:17)[3792r,3824r:15)[3952r,3968r:14)[4160r,4176r:16)[4352r,4384r:13)[4384r,4464r:1)[4576r,4592r:12)[4720r,4736r:11)[4864r,4880r:10)[5536r,5552r:35)[5552r,5632r:34)[5856r,5872r:7)[5872r,5952r:33)[5984r,6032r:32)[6512r,6544r:30)[6768r,6816r:31)[7184r,7200r:29)[7328r,7344r:28)[7344r,7424r:6)[7952r,7968r:22)[8080r,8096r:21)[8208r,8224r:20)[8624r,8672r:27)[8880r,8896r:23)[9184r,9296r:5)[9584r,9696r:4)[9952r,10064r:3)[10320r,10336r:26)[10640r,10656r:25)[10864r,10896r:24)[11072r,11104r:9)  0@0B-phi 1@4384r 2@2368r 3@9952r 4@9584r 5@9184r 6@7344r 7@5856r 8@736r 9@11072r 10@4864r 11@4720r 12@4576r 13@4352r 14@3952r 15@3792r 16@4160r 17@2512r 18@2384r 19@2176r 20@8208r 21@8080r 22@7952r 23@8880r 24@10864r 25@10640r 26@10320r 27@8624r 28@7328r 29@7184r 30@6512r 31@6768r 32@5984r 33@5872r 34@5552r 35@5536r 36@720r 37@480r 38@208r
W1 [0B,112r:0)[224r,240r:13)[2528r,2560r:5)[3808r,3824r:4)[4368r,4384r:1)[6000r,6032r:12)[6528r,6544r:10)[6784r,6816r:11)[8640r,8672r:9)[9200r,9296r:8)[9600r,9696r:7)[9968r,10064r:6)[10880r,10896r:2)[11088r,11104r:3)  0@0B-phi 1@4368r 2@10880r 3@11088r 4@3808r 5@2528r 6@9968r 7@9600r 8@9200r 9@8640r 10@6528r 11@6784r 12@6000r 13@224r
W2 [0B,96r:0)[2544r,2560r:1)[6016r,6032r:7)[6800r,6816r:6)[8656r,8672r:5)[9216r,9296r:4)[9616r,9696r:3)[9984r,10064r:2)  0@0B-phi 1@2544r 2@9984r 3@9616r 4@9216r 5@8656r 6@6800r 7@6016r
W3 [0B,80r:0)[9232r,9296r:3)[9632r,9696r:2)[10000r,10064r:1)  0@0B-phi 1@10000r 2@9632r 3@9232r
W4 [0B,64r:0)[9248r,9296r:3)[9648r,9696r:2)[10016r,10064r:1)  0@0B-phi 1@10016r 2@9648r 3@9248r
W5 [0B,48r:0)[9264r,9296r:3)[9664r,9696r:2)[10032r,10064r:1)  0@0B-phi 1@10032r 2@9664r 3@9264r
W6 [0B,32r:0)[9280r,9296r:3)[9680r,9696r:2)[10048r,10064r:1)  0@0B-phi 1@10048r 2@9680r 3@9280r
W7 [0B,16r:0)  0@0B-phi
%vreg4 [128r,320r:0)  0@128r
%vreg5 [112r,336r:0)  0@112r
%vreg6 [96r,352r:0)  0@96r
%vreg7 [80r,368r:0)  0@80r
%vreg8 [64r,384r:0)  0@64r
%vreg9 [48r,176r:0)  0@48r
%vreg10 [32r,416r:0)  0@32r
%vreg11 [16r,432r:0)  0@16r
%vreg12 [144r,448r:0)  0@144r
%vreg13 [176r,400r:0)  0@176r
%vreg15 [560r,592r:0)  0@560r
%vreg16 [592r,624r:0)  0@592r
%vreg17 [672r,688r:0)  0@672r
%vreg18 [688r,720r:0)  0@688r
%vreg19 [816r,832r:0)  0@816r
%vreg20 [880r,896r:0)  0@880r
%vreg21 [896r,912r:0)  0@896r
%vreg22 [912r,928r:0)  0@912r
%vreg23 [976r,992r:0)  0@976r
%vreg24 [992r,1008r:0)  0@992r
%vreg25 [1008r,1024r:0)  0@1008r
%vreg26 [1024r,1040r:0)  0@1024r
%vreg27 [1120r,1136r:0)  0@1120r
%vreg28 [1248r,1296r:0)  0@1248r
%vreg29 [1264r,1280r:0)  0@1264r
%vreg30 [1280r,1296r:0)  0@1280r
%vreg31 [1296r,1296d:0)  0@1296r
%vreg32 [1360r,1376r:0)  0@1360r
%vreg33 [1376r,1392r:0)  0@1376r
%vreg35 [1472r,1488r:0)  0@1472r
%vreg36 [1536r,1552r:0)  0@1536r
%vreg37 [1600r,1616r:0)  0@1600r
%vreg38 [1616r,1632r:0)  0@1616r
%vreg39 [1680r,1696r:0)  0@1680r
%vreg40 [1696r,1712r:0)  0@1696r
%vreg41 [1712r,1728r:0)  0@1712r
%vreg42 [1728r,1744r:0)  0@1728r
%vreg43 [1792r,1824r:0)  0@1792r
%vreg44 [1808r,1840r:0)  0@1808r
%vreg45 [1824r,1840r:0)  0@1824r
%vreg46 [1840r,1840d:0)  0@1840r
%vreg47 [5120r,5136r:0)  0@5120r
%vreg48 [5136r,5168r:0)  0@5136r
%vreg49 [5168r,5184r:0)  0@5168r
%vreg51 [5232r,5248r:0)  0@5232r
%vreg52 [5296r,5312r:0)  0@5296r
%vreg53 [5312r,5360r:0)  0@5312r
%vreg55 [5328r,5360r:0)  0@5328r
%vreg56 [5360r,5376r:0)  0@5360r
%vreg57 [5424r,5456r:0)  0@5424r
%vreg58 [5440r,5456r:0)  0@5440r
%vreg59 [5456r,5488r:0)  0@5456r
%vreg60 [5472r,5488r:0)  0@5472r
%vreg61 [5488r,5504r:0)  0@5488r
%vreg62 [5504r,5536r:0)  0@5504r
%vreg63 [5632r,5680r:0)  0@5632r
%vreg64 [5664r,5680r:0)  0@5664r
%vreg65 [5680r,5712r:0)  0@5680r
%vreg66 [5696r,5744r:0)  0@5696r
%vreg67 [5712r,5728r:0)  0@5712r
%vreg68 [5728r,5760r:0)  0@5728r
%vreg69 [5744r,5760r:0)  0@5744r
%vreg70 [5760r,5776r:0)  0@5760r
%vreg71 [5792r,5984r:0)  0@5792r
%vreg72 [5808r,6000r:0)  0@5808r
%vreg74 [5952r,6016r:0)  0@5952r
%vreg75 [6112r,6144r:0)  0@6112r
%vreg76 [6128r,6144r:0)  0@6128r
%vreg77 [6160r,6192r:0)  0@6160r
%vreg78 [6176r,6192r:0)  0@6176r
%vreg79 [6208r,6224r:0)  0@6208r
%vreg80 [6224r,6256r:0)  0@6224r
%vreg81 [6240r,6272r:0)  0@6240r
%vreg82 [6256r,6272r:0)  0@6256r
%vreg83 [6288r,6320r:0)  0@6288r
%vreg84 [6304r,6320r:0)  0@6304r
%vreg85 [6336r,6368r:0)  0@6336r
%vreg86 [6352r,6368r:0)  0@6352r
%vreg87 [6384r,6400r:0)  0@6384r
%vreg88 [6704r,6768r:0)  0@6704r
%vreg89 [6720r,6784r:0)  0@6720r
%vreg90 [6736r,6800r:0)  0@6736r
%vreg91 [6448r,6544r:0)  0@6448r
%vreg92 [6464r,6512r:0)  0@6464r
%vreg93 [6480r,6528r:0)  0@6480r
%vreg94 [6624r,6656r:0)  0@6624r
%vreg95 [6640r,6656r:0)  0@6640r
%vreg96 [6880r,6912r:0)  0@6880r
%vreg97 [6896r,6912r:0)  0@6896r
%vreg98 [6928r,6960r:0)  0@6928r
%vreg99 [6944r,6960r:0)  0@6944r
%vreg100 [6976r,7008r:0)  0@6976r
%vreg101 [6992r,7008r:0)  0@6992r
%vreg102 [7024r,7056r:0)  0@7024r
%vreg103 [7040r,7056r:0)  0@7040r
%vreg104 [7072r,7088r:0)  0@7072r
%vreg105 [7088r,7120r:0)  0@7088r
%vreg106 [7104r,7120r:0)  0@7104r
%vreg107 [7136r,7152r:0)  0@7136r
%vreg108 [7152r,7184r:0)  0@7152r
%vreg109 [7280r,7296r:0)  0@7280r
%vreg110 [7296r,7328r:0)  0@7296r
%vreg111 [7424r,7440r:0)  0@7424r
%vreg113 [7488r,7552r:0)  0@7488r
%vreg116 [7600r,7616r:0)  0@7600r
%vreg117 [7616r,7680r:0)  0@7616r
%vreg119 [7728r,7744r:0)  0@7728r
%vreg120 [7744r,7760r:0)  0@7744r
%vreg122 [8336r,8352r:0)  0@8336r
%vreg123 [8400r,8448r:0)  0@8400r
%vreg124 [8416r,8432r:0)  0@8416r
%vreg125 [8432r,8448r:0)  0@8432r
%vreg126 [8496r,8512r:0)  0@8496r
%vreg127 [8560r,8624r:0)  0@8560r
%vreg128 [8576r,8640r:0)  0@8576r
%vreg129 [8592r,8656r:0)  0@8592r
%vreg130 [8752r,8768r:0)  0@8752r
%vreg131 [8768r,8784r:0)  0@8768r
%vreg132 [9040r,9056r:0)  0@9040r
%vreg133 [9056r,9200r:0)  0@9056r
%vreg134 [9072r,9216r:0)  0@9072r
%vreg135 [9088r,9232r:0)  0@9088r
%vreg136 [9104r,9136r:0)  0@9104r
%vreg137 [9136r,9280r:0)  0@9136r
%vreg140 [9376r,9392r:0)  0@9376r
%vreg141 [9440r,9456r:0)  0@9440r
%vreg142 [9456r,9600r:0)  0@9456r
%vreg143 [9472r,9616r:0)  0@9472r
%vreg144 [9488r,9632r:0)  0@9488r
%vreg145 [9504r,9536r:0)  0@9504r
%vreg146 [9536r,9680r:0)  0@9536r
%vreg149 [9808r,9824r:0)  0@9808r
%vreg150 [9824r,9968r:0)  0@9824r
%vreg151 [9840r,9984r:0)  0@9840r
%vreg152 [9856r,10000r:0)  0@9856r
%vreg153 [9872r,9904r:0)  0@9872r
%vreg154 [9904r,10048r:0)  0@9904r
%vreg157 [10144r,10192r:0)  0@10144r
%vreg158 [10160r,10176r:0)  0@10160r
%vreg159 [10176r,10192r:0)  0@10176r
%vreg160 [10208r,10256r:0)  0@10208r
%vreg161 [10224r,10240r:0)  0@10224r
%vreg162 [10240r,10256r:0)  0@10240r
%vreg163 [10272r,10288r:0)  0@10272r
%vreg164 [10288r,10320r:0)  0@10288r
%vreg165 [10416r,10528r:0)  0@10416r
%vreg166 [10432r,10512r:0)  0@10432r
%vreg167 [10448r,10464r:0)  0@10448r
%vreg168 [10464r,10480r:0)  0@10464r
%vreg169 [10480r,10496r:0)  0@10480r
%vreg170 [10496r,10512r:0)  0@10496r
%vreg171 [10512r,10544r:0)  0@10512r
%vreg172 [10528r,10544r:0)  0@10528r
%vreg173 [10544r,10544d:0)  0@10544r
%vreg174 [10560r,10576r:0)  0@10560r
%vreg175 [10592r,10608r:0)  0@10592r
%vreg176 [10608r,10640r:0)  0@10608r
%vreg177 [10736r,10752r:0)  0@10736r
%vreg178 [10800r,10816r:0)  0@10800r
%vreg179 [10816r,10864r:0)  0@10816r
%vreg181 [8832r,8848r:0)  0@8832r
%vreg182 [8848r,8880r:0)  0@8848r
%vreg183 [7904r,7920r:0)  0@7904r
%vreg184 [7920r,7952r:0)  0@7920r
%vreg185 [8048r,8080r:0)  0@8048r
%vreg186 [8176r,8208r:0)  0@8176r
%vreg187 [1904r,1920r:0)  0@1904r
%vreg188 [1968r,1984r:0)  0@1968r
%vreg189 [1984r,2000r:0)  0@1984r
%vreg190 [2048r,2064r:0)  0@2048r
%vreg191 [2064r,2080r:0)  0@2064r
%vreg192 [2080r,2096r:0)  0@2080r
%vreg193 [2144r,2176r:0)  0@2144r
%vreg194 [2304r,2320r:0)  0@2304r
%vreg195 [2320r,2528r:0)  0@2320r
%vreg197 [2464r,2544r:0)  0@2464r
%vreg199 [2640r,2656r:0)  0@2640r
%vreg200 [2672r,2688r:0)  0@2672r
%vreg201 [2688r,2704r:0)  0@2688r
%vreg203 [2752r,2768r:0)  0@2752r
%vreg204 [2768r,2784r:0)  0@2768r
%vreg205 [2784r,2800r:0)  0@2784r
%vreg206 [2800r,2864r:0)  0@2800r
%vreg208 [2912r,2928r:0)  0@2912r
%vreg210 [3024r,3040r:0)  0@3024r
%vreg211 [3056r,3072r:0)  0@3056r
%vreg212 [3088r,3104r:0)  0@3088r
%vreg213 [3104r,3120r:0)  0@3104r
%vreg214 [3168r,3184r:0)  0@3168r
%vreg215 [3184r,3200r:0)  0@3184r
%vreg216 [3200r,3216r:0)  0@3200r
%vreg217 [3216r,3232r:0)  0@3216r
%vreg218 [3248r,3264r:0)  0@3248r
%vreg219 [3264r,3280r:0)  0@3264r
%vreg220 [3280r,3296r:0)  0@3280r
%vreg221 [3344r,3376r:0)  0@3344r
%vreg222 [3360r,3376r:0)  0@3360r
%vreg223 [3392r,3408r:0)  0@3392r
%vreg224 [4112r,4176r:0)  0@4112r
%vreg225 [4128r,4160r:0)  0@4128r
%vreg226 [3456r,3488r:0)  0@3456r
%vreg227 [3472r,3488r:0)  0@3472r
%vreg228 [3488r,3536r:0)  0@3488r
%vreg229 [3504r,3520r:0)  0@3504r
%vreg230 [3536r,3552r:0)  0@3536r
%vreg231 [3552r,3600r:0)  0@3552r
%vreg232 [3584r,3600r:0)  0@3584r
%vreg233 [3600r,3664r:0)  0@3600r
%vreg234 [3648r,3696r:0)  0@3648r
%vreg235 [3664r,3680r:0)  0@3664r
%vreg236 [3680r,3712r:0)  0@3680r
%vreg237 [3696r,3712r:0)  0@3696r
%vreg238 [3712r,3792r:0)  0@3712r
%vreg239 [3744r,3824r:0)  0@3744r
%vreg240 [3760r,3808r:0)  0@3760r
%vreg241 [3904r,3968r:0)  0@3904r
%vreg242 [3920r,3952r:0)  0@3920r
%vreg243 [4048r,4064r:0)  0@4048r
%vreg244 [4288r,4304r:0)  0@4288r
%vreg245 [4304r,4352r:0)  0@4304r
%vreg247 [4464r,4480r:0)  0@4464r
%vreg248 [4528r,4544r:0)  0@4528r
%vreg249 [4544r,4576r:0)  0@4544r
%vreg250 [4672r,4688r:0)  0@4672r
%vreg251 [4688r,4720r:0)  0@4688r
%vreg252 [4816r,4832r:0)  0@4816r
%vreg253 [4832r,4864r:0)  0@4832r
%vreg255 [2816r,2896B:0)[2928r,2992B:1)[2992B,3024r:2)  0@2816r 1@2928r 2@2992B-phi
%vreg256 [7536r,7584B:0)[7664r,7712B:1)[7760r,7824B:2)[7824B,7856r:3)  0@7536r 1@7664r 2@7760r 3@7824B-phi
RegMasks: 240r 480r 736r 2192r 2384r 2560r 3824r 3968r 4176r 4384r 4592r 4736r 4880r 5008r 5552r 5872r 6032r 6544r 6816r 7200r 7344r 7968r 8096r 8224r 8672r 8896r 9296r 9696r 10064r 10336r 10656r 10896r 11104r
********** MACHINEINSTRS **********
# Machine code for function GOMP_task: Post SSA
Frame Objects:
  fi#-1: size=4, align=16, fixed, at location [SP]
  fi#0: size=8, align=8, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=8, align=8, at location [SP]
  fi#3: size=8, align=8, at location [SP]
  fi#4: size=8, align=8, at location [SP]
  fi#5: size=1, align=1, at location [SP]
  fi#6: size=4, align=4, at location [SP]
  fi#7: size=8, align=8, at location [SP]
  fi#8: size=4, align=4, at location [SP]
  fi#9: size=8, align=8, at location [SP]
  fi#10: size=8, align=8, at location [SP]
  fi#11: size=208, align=8, at location [SP]
  fi#12: size=8, align=8, at location [SP]
  fi#13: size=8, align=8, at location [SP]
  fi#14: size=8, align=8, at location [SP]
  fi#15: size=8, align=8, at location [SP]
  fi#16: size=8, align=8, at location [SP]
  fi#17: size=8, align=8, at location [SP]
  fi#18: size=1, align=1, at location [SP]
  fi#19: size=8, align=8, at location [SP]
  fi#20: variable sized, align=1, at location [SP]
Function Live Ins: %X0 in %vreg4, %X1 in %vreg5, %X2 in %vreg6, %X3 in %vreg7, %X4 in %vreg8, %W5 in %vreg9, %W6 in %vreg10, %X7 in %vreg11

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %X1 %X2 %X3 %X4 %W5 %W6 %X7
16B		%vreg11<def> = COPY %X7; GPR64:%vreg11
32B		%vreg10<def> = COPY %W6; GPR32:%vreg10
48B		%vreg9<def> = COPY %W5; GPR32:%vreg9
64B		%vreg8<def> = COPY %X4; GPR64:%vreg8
80B		%vreg7<def> = COPY %X3; GPR64:%vreg7
96B		%vreg6<def> = COPY %X2; GPR64:%vreg6
112B		%vreg5<def> = COPY %X1; GPR64:%vreg5
128B		%vreg4<def> = COPY %X0; GPR64:%vreg4
144B		%vreg12<def> = LDRWui <fi#-1>, 0; mem:LD4[FixedStack-1] GPR32:%vreg12
160B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
176B		%vreg13<def> = ANDWri %vreg9, 0; GPR32common:%vreg13 GPR32:%vreg9
208B		%X0<def> = COPY %XZR
224B		%X1<def> = COPY %XZR
240B		BL <ga:@check_migrate>, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %SP<imp-def>, ...
256B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
272B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
288B		STACKMAP 0, 0, %vreg8, %vreg7, %vreg6, %vreg5, %vreg11, %vreg10, %vreg4, %vreg13, %vreg12, ...; GPR64:%vreg8,%vreg7,%vreg6,%vreg5,%vreg11,%vreg4 GPR32:%vreg10,%vreg12 GPR32common:%vreg13
304B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
320B		STRXui %vreg4, <fi#0>, 0; mem:ST8[%fn.addr] GPR64:%vreg4
336B		STRXui %vreg5, <fi#1>, 0; mem:ST8[%data.addr] GPR64:%vreg5
352B		STRXui %vreg6, <fi#2>, 0; mem:ST8[%cpyfn.addr] GPR64:%vreg6
368B		STRXui %vreg7, <fi#3>, 0; mem:ST8[%arg_size.addr] GPR64:%vreg7
384B		STRXui %vreg8, <fi#4>, 0; mem:ST8[%arg_align.addr] GPR64:%vreg8
400B		STRBBui %vreg13, <fi#5>, 0; mem:ST1[%if_clause.addr] GPR32common:%vreg13
416B		STRWui %vreg10, <fi#6>, 0; mem:ST4[%flags.addr] GPR32:%vreg10
432B		STRXui %vreg11, <fi#7>, 0; mem:ST8[%depend.addr] GPR64:%vreg11
448B		STRWui %vreg12, <fi#8>, 0; mem:ST4[%priority.addr] GPR32:%vreg12
464B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
480B		BL <ga:@gomp_thread>, <regmask>, %SP<imp-use>, %SP<imp-def>, %X0<imp-def>, ...
496B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
512B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
528B		STACKMAP 1, 0, 0, <fi#13>, 0, 0, <fi#17>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#19>, 0, 0, <fi#18>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#5>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#12>, 0, 0, <fi#11>, 0, 0, <fi#14>, 0, 0, <fi#16>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack13] LD8[FixedStack17] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack2] LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack19] LD8[FixedStack18](align=1) LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack5](align=1) LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack12] LD8[FixedStack11] LD8[FixedStack14] LD8[FixedStack16] LD8[FixedStack10] LD8[FixedStack9]
544B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
560B		%vreg15<def> = COPY %X0; GPR64common:%vreg15
576B		STRXui %vreg15, <fi#9>, 0; mem:ST8[%thr] GPR64common:%vreg15
592B		%vreg16<def> = LDRXui %vreg15, 2; mem:LD8[%team1] GPR64:%vreg16 GPR64common:%vreg15
608B		STRXui %vreg16, <fi#10>, 0; mem:ST8[%team] GPR64:%vreg16
624B		CBZX %vreg16, <BB#5>; GPR64:%vreg16
640B		B <BB#1>
	    Successors according to CFG: BB#1 BB#5

656B	BB#1: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#0
672B		%vreg17<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg17
688B		%vreg18<def> = ADDXri %vreg17, 128, 0; GPR64sp:%vreg18 GPR64common:%vreg17
704B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
720B		%X0<def> = COPY %vreg18; GPR64sp:%vreg18
736B		BL <ga:@gomp_team_barrier_cancelled>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>, ...
752B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
768B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
784B		STACKMAP 2, 0, 0, <fi#13>, 0, 0, <fi#17>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#19>, 0, 0, <fi#18>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#5>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#12>, 0, 0, <fi#11>, 0, 0, <fi#14>, 0, 0, <fi#16>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack13] LD8[FixedStack17] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack2] LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack19] LD8[FixedStack18](align=1) LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack5](align=1) LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack12] LD8[FixedStack11] LD8[FixedStack14] LD8[FixedStack16] LD8[FixedStack10] LD8[FixedStack9]
800B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
816B		%vreg19<def> = COPY %W0; GPR32:%vreg19
832B		TBNZW %vreg19, 0, <BB#4>; GPR32:%vreg19
848B		B <BB#2>
	    Successors according to CFG: BB#4 BB#2

864B	BB#2: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#1
880B		%vreg20<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg20
896B		%vreg21<def> = LDRXui %vreg20, 10; mem:LD8[%task] GPR64common:%vreg21,%vreg20
912B		%vreg22<def> = LDRXui %vreg21, 5; mem:LD8[%taskgroup] GPR64:%vreg22 GPR64common:%vreg21
928B		CBZX %vreg22, <BB#5>; GPR64:%vreg22
944B		B <BB#3>
	    Successors according to CFG: BB#3 BB#5

960B	BB#3: derived from LLVM BB %land.lhs.true.4
	    Predecessors according to CFG: BB#2
976B		%vreg23<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg23
992B		%vreg24<def> = LDRXui %vreg23, 10; mem:LD8[%task5] GPR64common:%vreg24,%vreg23
1008B		%vreg25<def> = LDRXui %vreg24, 5; mem:LD8[%taskgroup6] GPR64common:%vreg25,%vreg24
1024B		%vreg26<def> = LDRBBui %vreg25, 41; mem:LD1[%cancelled] GPR32:%vreg26 GPR64common:%vreg25
1040B		TBZW %vreg26, 0, <BB#5>; GPR32:%vreg26
1056B		B <BB#4>
	    Successors according to CFG: BB#4 BB#5

1072B	BB#4: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#1 BB#3
1088B		B <BB#52>
	    Successors according to CFG: BB#52

1104B	BB#5: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#2 BB#3
1120B		%vreg27<def> = LDRBBui <fi#6>, 0; mem:LD1[%flags.addr](align=4) GPR32:%vreg27
1136B		TBNZW %vreg27, 4, <BB#7>; GPR32:%vreg27
1152B		B <BB#6>
	    Successors according to CFG: BB#6 BB#7

1168B	BB#6: derived from LLVM BB %if.then.8
	    Predecessors according to CFG: BB#5
1200B		STRWui %WZR, <fi#8>, 0; mem:ST4[%priority.addr]
1216B		B <BB#10>
	    Successors according to CFG: BB#10

1232B	BB#7: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#5
1248B		%vreg28<def> = LDRWui <fi#8>, 0; mem:LD4[%priority.addr] GPR32:%vreg28
1264B		%vreg29<def> = ADRP <ga:@gomp_max_task_priority_var>[TF=1]; GPR64common:%vreg29
1280B		%vreg30<def> = LDRWui %vreg29, <ga:@gomp_max_task_priority_var>[TF=34]; mem:LD4[@gomp_max_task_priority_var] GPR32:%vreg30 GPR64common:%vreg29
1296B		%vreg31<def,dead> = SUBSWrr %vreg28, %vreg30, %NZCV<imp-def>; GPR32:%vreg31,%vreg28,%vreg30
1312B		Bcc 13, <BB#9>, %NZCV<imp-use,kill>
1328B		B <BB#8>
	    Successors according to CFG: BB#8 BB#9

1344B	BB#8: derived from LLVM BB %if.then.10
	    Predecessors according to CFG: BB#7
1360B		%vreg32<def> = ADRP <ga:@gomp_max_task_priority_var>[TF=1]; GPR64common:%vreg32
1376B		%vreg33<def> = LDRWui %vreg32, <ga:@gomp_max_task_priority_var>[TF=34]; mem:LD4[@gomp_max_task_priority_var] GPR32:%vreg33 GPR64common:%vreg32
1392B		STRWui %vreg33, <fi#8>, 0; mem:ST4[%priority.addr] GPR32:%vreg33
1408B		B <BB#9>
	    Successors according to CFG: BB#9

1424B	BB#9: derived from LLVM BB %if.end.11
	    Predecessors according to CFG: BB#7 BB#8
1440B		B <BB#10>
	    Successors according to CFG: BB#10

1456B	BB#10: derived from LLVM BB %if.end.12
	    Predecessors according to CFG: BB#9 BB#6
1472B		%vreg35<def> = LDRBBui <fi#5>, 0; mem:LD1[%if_clause.addr] GPR32:%vreg35
1488B		TBZW %vreg35, 0, <BB#15>; GPR32:%vreg35
1504B		B <BB#11>
	    Successors according to CFG: BB#11 BB#15

1520B	BB#11: derived from LLVM BB %lor.lhs.false.14
	    Predecessors according to CFG: BB#10
1536B		%vreg36<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64:%vreg36
1552B		CBZX %vreg36, <BB#15>; GPR64:%vreg36
1568B		B <BB#12>
	    Successors according to CFG: BB#15 BB#12

1584B	BB#12: derived from LLVM BB %lor.lhs.false.16
	    Predecessors according to CFG: BB#11
1600B		%vreg37<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg37
1616B		%vreg38<def> = LDRXui %vreg37, 10; mem:LD8[%task17] GPR64:%vreg38 GPR64common:%vreg37
1632B		CBZX %vreg38, <BB#14>; GPR64:%vreg38
1648B		B <BB#13>
	    Successors according to CFG: BB#13 BB#14

1664B	BB#13: derived from LLVM BB %land.lhs.true.19
	    Predecessors according to CFG: BB#12
1680B		%vreg39<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg39
1696B		%vreg40<def> = LDRXui %vreg39, 10; mem:LD8[%task20] GPR64common:%vreg40,%vreg39
1712B		%vreg41<def> = LDRBBui %vreg40, 205; mem:LD1[%final_task] GPR32:%vreg41 GPR64common:%vreg40
1728B		%vreg42<def> = ANDWri %vreg41, 0; GPR32common:%vreg42 GPR32:%vreg41
1744B		TBNZW %vreg42, 0, <BB#15>; GPR32common:%vreg42
1760B		B <BB#14>
	    Successors according to CFG: BB#15 BB#14

1776B	BB#14: derived from LLVM BB %lor.lhs.false.22
	    Predecessors according to CFG: BB#12 BB#13
1792B		%vreg43<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg43
1808B		%vreg44<def> = LDRWui %vreg43, 330; mem:LD4[%task_count] GPR32:%vreg44 GPR64common:%vreg43
1824B		%vreg45<def> = LDRWui %vreg43, 0; mem:LD4[%nthreads] GPR32:%vreg45 GPR64common:%vreg43
1840B		%vreg46<def,dead> = SUBSWrs %vreg44, %vreg45, 6, %NZCV<imp-def>; GPR32:%vreg46,%vreg44,%vreg45
1856B		Bcc 9, <BB#30>, %NZCV<imp-use,kill>
1872B		B <BB#15>
	    Successors according to CFG: BB#15 BB#30

1888B	BB#15: derived from LLVM BB %if.then.24
	    Predecessors according to CFG: BB#10 BB#11 BB#13 BB#14
1904B		%vreg187<def> = LDRBBui <fi#6>, 0; mem:LD1[%flags.addr](align=4) GPR32:%vreg187
1920B		TBZW %vreg187, 3, <BB#19>; GPR32:%vreg187
1936B		B <BB#16>
	    Successors according to CFG: BB#16 BB#19

1952B	BB#16: derived from LLVM BB %land.lhs.true.28
	    Predecessors according to CFG: BB#15
1968B		%vreg188<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg188
1984B		%vreg189<def> = LDRXui %vreg188, 10; mem:LD8[%task29] GPR64:%vreg189 GPR64common:%vreg188
2000B		CBZX %vreg189, <BB#19>; GPR64:%vreg189
2016B		B <BB#17>
	    Successors according to CFG: BB#17 BB#19

2032B	BB#17: derived from LLVM BB %land.lhs.true.31
	    Predecessors according to CFG: BB#16
2048B		%vreg190<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg190
2064B		%vreg191<def> = LDRXui %vreg190, 10; mem:LD8[%task32] GPR64common:%vreg191,%vreg190
2080B		%vreg192<def> = LDRXui %vreg191, 7; mem:LD8[%depend_hash] GPR64:%vreg192 GPR64common:%vreg191
2096B		CBZX %vreg192, <BB#19>; GPR64:%vreg192
2112B		B <BB#18>
	    Successors according to CFG: BB#18 BB#19

2128B	BB#18: derived from LLVM BB %if.then.34
	    Predecessors according to CFG: BB#17
2144B		%vreg193<def> = LDRXui <fi#7>, 0; mem:LD8[%depend.addr] GPR64:%vreg193
2160B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2176B		%X0<def> = COPY %vreg193; GPR64:%vreg193
2192B		BL <ga:@gomp_task_maybe_wait_for_dependencies>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...
2208B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2224B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2240B		STACKMAP 3, 0, 0, <fi#13>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#8>, 0, 0, <fi#12>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack13] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack2] LD8[FixedStack1] LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack8](align=4) LD8[FixedStack12] LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack9]
2256B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2272B		B <BB#19>
	    Successors according to CFG: BB#19

2288B	BB#19: derived from LLVM BB %if.end.35
	    Predecessors according to CFG: BB#15 BB#16 BB#17 BB#18
2304B		%vreg194<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg194
2320B		%vreg195<def> = LDRXui %vreg194, 10; mem:LD8[%task36] GPR64:%vreg195 GPR64common:%vreg194
2336B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2368B		%W0<def> = COPY %WZR
2384B		BL <ga:@gomp_icv>, <regmask>, %SP<imp-use>, %W0<imp-use>, %SP<imp-def>, %X0<imp-def>, ...
2400B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2416B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2432B		STACKMAP 4, 0, 0, <fi#13>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#8>, 0, 0, <fi#12>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, %vreg195, ...; mem:LD8[FixedStack13] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack2] LD8[FixedStack1] LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack8](align=4) LD8[FixedStack12] LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack9] GPR64:%vreg195
2448B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2464B		%vreg197<def> = COPY %X0; GPR64all:%vreg197
2480B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2512B		%X0<def> = ADDXri <fi#11>, 0, 0
2528B		%X1<def> = COPY %vreg195; GPR64:%vreg195
2544B		%X2<def> = COPY %vreg197; GPR64all:%vreg197
2560B		BL <ga:@gomp_init_task>, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %X2<imp-use>, %SP<imp-def>, ...
2576B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2592B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2608B		STACKMAP 5, 0, 0, <fi#13>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#8>, 0, 0, <fi#12>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack13] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack2] LD8[FixedStack1] LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack8](align=4) LD8[FixedStack12] LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack9]
2624B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2640B		%vreg199<def> = MOVi32imm 1; GPR32:%vreg199
2656B		STRWui %vreg199, <fi#11>, 50; mem:ST4[%kind] GPR32:%vreg199
2672B		%vreg200<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg200
2688B		%vreg201<def> = LDRXui %vreg200, 10; mem:LD8[%task38] GPR64:%vreg201 GPR64common:%vreg200
2704B		CBZX %vreg201, <BB#21>; GPR64:%vreg201
2720B		B <BB#20>
	    Successors according to CFG: BB#20 BB#21

2736B	BB#20: derived from LLVM BB %land.lhs.true.40
	    Predecessors according to CFG: BB#19
2752B		%vreg203<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg203
2768B		%vreg204<def> = LDRXui %vreg203, 10; mem:LD8[%task41] GPR64common:%vreg204,%vreg203
2784B		%vreg205<def> = LDRBBui %vreg204, 205; mem:LD1[%final_task42] GPR32:%vreg205 GPR64common:%vreg204
2800B		%vreg206<def> = ANDWri %vreg205, 0; GPR32common:%vreg206 GPR32:%vreg205
2816B		%vreg255<def> = MOVi32imm 1; GPR32:%vreg255
2864B		TBNZW %vreg206, 0, <BB#22>; GPR32common:%vreg206
2880B		B <BB#21>
	    Successors according to CFG: BB#22 BB#21

2896B	BB#21: derived from LLVM BB %lor.rhs
	    Predecessors according to CFG: BB#19 BB#20
2912B		%vreg208<def> = LDRBBui <fi#6>, 0; mem:LD1[%flags.addr](align=4) GPR32:%vreg208
2928B		%vreg255<def> = UBFMWri %vreg208, 1, 1; GPR32:%vreg255,%vreg208
2976B		B <BB#22>
	    Successors according to CFG: BB#22

2992B	BB#22: derived from LLVM BB %lor.end
	    Predecessors according to CFG: BB#20 BB#21
3024B		%vreg210<def> = ANDWri %vreg255, 0; GPR32common:%vreg210 GPR32:%vreg255
3040B		STRBBui %vreg210, <fi#11>, 205; mem:ST1[%final_task46] GPR32common:%vreg210
3056B		%vreg211<def> = LDRWui <fi#8>, 0; mem:LD4[%priority.addr] GPR32:%vreg211
3072B		STRWui %vreg211, <fi#11>, 22; mem:ST4[%priority48] GPR32:%vreg211
3088B		%vreg212<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg212
3104B		%vreg213<def> = LDRXui %vreg212, 10; mem:LD8[%task49] GPR64:%vreg213 GPR64common:%vreg212
3120B		CBZX %vreg213, <BB#24>; GPR64:%vreg213
3136B		B <BB#23>
	    Successors according to CFG: BB#23 BB#24

3152B	BB#23: derived from LLVM BB %if.then.51
	    Predecessors according to CFG: BB#22
3168B		%vreg214<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg214
3184B		%vreg215<def> = LDRXui %vreg214, 10; mem:LD8[%task52] GPR64common:%vreg215,%vreg214
3200B		%vreg216<def> = LDRBBui %vreg215, 204; mem:LD1[%in_tied_task] GPR32:%vreg216 GPR64common:%vreg215
3216B		%vreg217<def> = ANDWri %vreg216, 0; GPR32common:%vreg217 GPR32:%vreg216
3232B		STRBBui %vreg217, <fi#11>, 204; mem:ST1[%in_tied_task54] GPR32common:%vreg217
3248B		%vreg218<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg218
3264B		%vreg219<def> = LDRXui %vreg218, 10; mem:LD8[%task56] GPR64common:%vreg219,%vreg218
3280B		%vreg220<def> = LDRXui %vreg219, 5; mem:LD8[%taskgroup57] GPR64:%vreg220 GPR64common:%vreg219
3296B		STRXui %vreg220, <fi#11>, 5; mem:ST8[%taskgroup58] GPR64:%vreg220
3312B		B <BB#24>
	    Successors according to CFG: BB#24

3328B	BB#24: derived from LLVM BB %if.end.59
	    Predecessors according to CFG: BB#22 BB#23
3344B		%vreg221<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg221
3360B		%vreg222<def> = ADDXri <fi#11>, 0, 0; GPR64common:%vreg222
3376B		STRXui %vreg222, %vreg221, 10; mem:ST8[%task60] GPR64common:%vreg222,%vreg221
3392B		%vreg223<def> = LDRXui <fi#2>, 0; mem:LD8[%cpyfn.addr] GPR64:%vreg223
3408B		CBZX %vreg223, <BB#26>; GPR64:%vreg223
3424B		B <BB#25>
	    Successors according to CFG: BB#25 BB#26

3440B	BB#25: derived from LLVM BB %if.then.64
	    Predecessors according to CFG: BB#24
3456B		%vreg226<def> = LDRXui <fi#3>, 0; mem:LD8[%arg_size.addr] GPR64:%vreg226
3472B		%vreg227<def> = LDRXui <fi#4>, 0; mem:LD8[%arg_align.addr] GPR64:%vreg227
3488B		%vreg228<def> = ADDXrr %vreg226, %vreg227; GPR64common:%vreg228 GPR64:%vreg226,%vreg227
3504B		%vreg229<def> = COPY %SP; GPR64:%vreg229
3520B		STRXui %vreg229, <fi#12>, 0; mem:ST8[%saved_stack] GPR64:%vreg229
3536B		%vreg230<def> = ADDXri %vreg228, 14, 0; GPR64common:%vreg230,%vreg228
3552B		%vreg231<def> = ANDXri %vreg230, 7995; GPR64common:%vreg231,%vreg230
3568B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3584B		%vreg232<def> = COPY %SP; GPR64:%vreg232
3600B		%vreg233<def> = SUBSXrr %vreg232, %vreg231, %NZCV<imp-def,dead>; GPR64:%vreg233,%vreg232 GPR64common:%vreg231
3616B		%SP<def> = COPY %vreg233; GPR64:%vreg233
3632B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3648B		%vreg234<def> = LDRXui <fi#4>, 0; mem:LD8[%arg_align.addr] GPR64common:%vreg234
3664B		%vreg235<def> = ADDXrr %vreg233, %vreg234; GPR64common:%vreg235,%vreg234 GPR64:%vreg233
3680B		%vreg236<def> = SUBSXri %vreg235, 1, 0, %NZCV<imp-def,dead>; GPR64:%vreg236 GPR64common:%vreg235
3696B		%vreg237<def> = SUBSXri %vreg234, 1, 0, %NZCV<imp-def,dead>; GPR64:%vreg237 GPR64common:%vreg234
3712B		%vreg238<def> = BICXrr %vreg236, %vreg237; GPR64:%vreg238,%vreg236,%vreg237
3728B		STRXui %vreg238, <fi#13>, 0; mem:ST8[%arg] GPR64:%vreg238
3744B		%vreg239<def> = LDRXui <fi#2>, 0; mem:LD8[%cpyfn.addr] GPR64:%vreg239
3760B		%vreg240<def> = LDRXui <fi#1>, 0; mem:LD8[%data.addr] GPR64:%vreg240
3776B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3792B		%X0<def> = COPY %vreg238; GPR64:%vreg238
3808B		%X1<def> = COPY %vreg240; GPR64:%vreg240
3824B		BLR %vreg239, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %SP<imp-def>, ...; GPR64:%vreg239
3840B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3856B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3872B		STACKMAP 6, 0, 0, <fi#13>, 0, 0, <fi#0>, 0, 0, <fi#12>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack13] LD8[FixedStack0] LD8[FixedStack12] LD8[FixedStack11] LD8[FixedStack10]
3888B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3904B		%vreg241<def> = LDRXui <fi#0>, 0; mem:LD8[%fn.addr] GPR64:%vreg241
3920B		%vreg242<def> = LDRXui <fi#13>, 0; mem:LD8[%arg] GPR64:%vreg242
3936B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3952B		%X0<def> = COPY %vreg242; GPR64:%vreg242
3968B		BLR %vreg241, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...; GPR64:%vreg241
3984B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4000B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4016B		STACKMAP 7, 0, 0, <fi#12>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack12] LD8[FixedStack11] LD8[FixedStack10]
4032B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4048B		%vreg243<def> = LDRXui <fi#12>, 0; mem:LD8[%saved_stack] GPR64:%vreg243
4064B		%SP<def> = COPY %vreg243; GPR64:%vreg243
4080B		B <BB#27>
	    Successors according to CFG: BB#27

4096B	BB#26: derived from LLVM BB %if.else.69
	    Predecessors according to CFG: BB#24
4112B		%vreg224<def> = LDRXui <fi#0>, 0; mem:LD8[%fn.addr] GPR64:%vreg224
4128B		%vreg225<def> = LDRXui <fi#1>, 0; mem:LD8[%data.addr] GPR64:%vreg225
4144B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4160B		%X0<def> = COPY %vreg225; GPR64:%vreg225
4176B		BLR %vreg224, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...; GPR64:%vreg224
4192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4224B		STACKMAP 8, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack11] LD8[FixedStack10]
4240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4256B		B <BB#27>
	    Successors according to CFG: BB#27

4272B	BB#27: derived from LLVM BB %if.end.70
	    Predecessors according to CFG: BB#26 BB#25
4288B		%vreg244<def> = ADDXri <fi#11>, 0, 0; GPR64sp:%vreg244
4304B		%vreg245<def> = ADDXri %vreg244, 8, 0; GPR64sp:%vreg245,%vreg244
4320B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4352B		%X0<def> = COPY %vreg245; GPR64sp:%vreg245
4368B		%W1<def> = COPY %WZR
4384B		BL <ga:@priority_queue_empty_p>, <regmask>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %SP<imp-def>, %W0<imp-def>, ...
4400B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4416B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4432B		STACKMAP 9, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack11] LD8[FixedStack10]
4448B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4464B		%vreg247<def> = COPY %W0; GPR32:%vreg247
4480B		TBNZW %vreg247, 0, <BB#29>; GPR32:%vreg247
4496B		B <BB#28>
	    Successors according to CFG: BB#29 BB#28

4512B	BB#28: derived from LLVM BB %if.then.72
	    Predecessors according to CFG: BB#27
4528B		%vreg248<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg248
4544B		%vreg249<def> = ADDXri %vreg248, 1280, 0; GPR64sp:%vreg249 GPR64common:%vreg248
4560B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4576B		%X0<def> = COPY %vreg249; GPR64sp:%vreg249
4592B		BL <ga:@gomp_mutex_lock>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...
4608B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4624B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4640B		STACKMAP 10, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack11] LD8[FixedStack10]
4656B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4672B		%vreg250<def> = ADDXri <fi#11>, 0, 0; GPR64sp:%vreg250
4688B		%vreg251<def> = ADDXri %vreg250, 8, 0; GPR64sp:%vreg251,%vreg250
4704B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4720B		%X0<def> = COPY %vreg251; GPR64sp:%vreg251
4736B		BL <ga:@gomp_clear_parent>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...
4752B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4768B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4784B		STACKMAP 11, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack10]
4800B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4816B		%vreg252<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg252
4832B		%vreg253<def> = ADDXri %vreg252, 1280, 0; GPR64sp:%vreg253 GPR64common:%vreg252
4848B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4864B		%X0<def> = COPY %vreg253; GPR64sp:%vreg253
4880B		BL <ga:@gomp_mutex_unlock>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...
4896B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4912B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4928B		STACKMAP 12, 0, ...
4944B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4960B		B <BB#29>
	    Successors according to CFG: BB#29

4976B	BB#29: derived from LLVM BB %if.end.75
	    Predecessors according to CFG: BB#27 BB#28
4992B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5008B		BL <ga:@gomp_end_task>, <regmask>, %SP<imp-use>, %SP<imp-def>, ...
5024B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5040B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5056B		STACKMAP 13, 0, ...
5072B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5088B		B <BB#52>
	    Successors according to CFG: BB#52

5104B	BB#30: derived from LLVM BB %if.else.76
	    Predecessors according to CFG: BB#14
5120B		%vreg47<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg47
5136B		%vreg48<def> = LDRXui %vreg47, 10; mem:LD8[%task78] GPR64common:%vreg48,%vreg47
5152B		STRXui %vreg48, <fi#15>, 0; mem:ST8[%parent] GPR64common:%vreg48
5168B		%vreg49<def> = LDRXui %vreg48, 5; mem:LD8[%taskgroup80] GPR64:%vreg49 GPR64common:%vreg48
5184B		STRXui %vreg49, <fi#16>, 0; mem:ST8[%taskgroup79] GPR64:%vreg49
5216B		STRXui %XZR, <fi#19>, 0; mem:ST8[%depend_size]
5232B		%vreg51<def> = LDRBBui <fi#6>, 0; mem:LD1[%flags.addr](align=4) GPR32:%vreg51
5248B		TBZW %vreg51, 3, <BB#32>; GPR32:%vreg51
5264B		B <BB#31>
	    Successors according to CFG: BB#31 BB#32

5280B	BB#31: derived from LLVM BB %if.then.84
	    Predecessors according to CFG: BB#30
5296B		%vreg52<def> = LDRXui <fi#7>, 0; mem:LD8[%depend.addr] GPR64common:%vreg52
5312B		%vreg53<def> = LDRXui %vreg52, 0; mem:LD8[%arrayidx] GPR64:%vreg53 GPR64common:%vreg52
5328B		%vreg55:sub_32<def,read-undef> = MOVi32imm 40; GPR64:%vreg55
5360B		%vreg56<def> = MADDXrrr %vreg53, %vreg55, %XZR; GPR64:%vreg56,%vreg53,%vreg55
5376B		STRXui %vreg56, <fi#19>, 0; mem:ST8[%depend_size] GPR64:%vreg56
5392B		B <BB#32>
	    Successors according to CFG: BB#32

5408B	BB#32: derived from LLVM BB %if.end.86
	    Predecessors according to CFG: BB#30 BB#31
5424B		%vreg57<def> = LDRXui <fi#19>, 0; mem:LD8[%depend_size] GPR64:%vreg57
5440B		%vreg58<def> = LDRXui <fi#3>, 0; mem:LD8[%arg_size.addr] GPR64:%vreg58
5456B		%vreg59<def> = ADDXrr %vreg57, %vreg58; GPR64:%vreg59,%vreg57,%vreg58
5472B		%vreg60<def> = LDRXui <fi#4>, 0; mem:LD8[%arg_align.addr] GPR64:%vreg60
5488B		%vreg61<def> = ADDXrr %vreg59, %vreg60; GPR64common:%vreg61 GPR64:%vreg59,%vreg60
5504B		%vreg62<def> = ADDXri %vreg61, 207, 0; GPR64sp:%vreg62 GPR64common:%vreg61
5520B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5536B		%X0<def> = COPY %vreg62; GPR64sp:%vreg62
5552B		BL <ga:@gomp_malloc>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %X0<imp-def>, ...
5568B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5584B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5600B		STACKMAP 14, 0, 0, <fi#17>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#19>, 0, 0, <fi#18>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#14>, 0, 0, <fi#16>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack17] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack2] LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack19] LD8[FixedStack18](align=1) LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack14] LD8[FixedStack16] LD8[FixedStack10] LD8[FixedStack9]
5616B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5632B		%vreg63<def> = COPY %X0; GPR64:%vreg63
5648B		STRXui %vreg63, <fi#14>, 0; mem:ST8[%task77] GPR64:%vreg63
5664B		%vreg64<def> = LDRXui <fi#19>, 0; mem:LD8[%depend_size] GPR64:%vreg64
5680B		%vreg65<def> = ADDXrr %vreg63, %vreg64; GPR64:%vreg65,%vreg63,%vreg64
5696B		%vreg66<def> = LDRXui <fi#4>, 0; mem:LD8[%arg_align.addr] GPR64common:%vreg66
5712B		%vreg67<def> = ADDXrr %vreg65, %vreg66; GPR64common:%vreg67,%vreg66 GPR64:%vreg65
5728B		%vreg68<def> = ADDXri %vreg67, 207, 0; GPR64common:%vreg68,%vreg67
5744B		%vreg69<def> = SUBSXri %vreg66, 1, 0, %NZCV<imp-def,dead>; GPR64:%vreg69 GPR64common:%vreg66
5760B		%vreg70<def> = BICXrr %vreg68, %vreg69; GPR64:%vreg70,%vreg69 GPR64common:%vreg68
5776B		STRXui %vreg70, <fi#17>, 0; mem:ST8[%arg81] GPR64:%vreg70
5792B		%vreg71<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64:%vreg71
5808B		%vreg72<def> = LDRXui <fi#15>, 0; mem:LD8[%parent] GPR64:%vreg72
5824B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5856B		%W0<def> = COPY %WZR
5872B		BL <ga:@gomp_icv>, <regmask>, %SP<imp-use>, %W0<imp-use>, %SP<imp-def>, %X0<imp-def>, ...
5888B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5904B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5920B		STACKMAP 15, 0, 0, <fi#17>, 0, 0, <fi#3>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#19>, 0, 0, <fi#18>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#14>, 0, 0, <fi#16>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, %vreg71, %vreg72, ...; mem:LD8[FixedStack17] LD8[FixedStack3] LD8[FixedStack2] LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack19] LD8[FixedStack18](align=1) LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack14] LD8[FixedStack16] LD8[FixedStack10] LD8[FixedStack9] GPR64:%vreg71,%vreg72
5936B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5952B		%vreg74<def> = COPY %X0; GPR64all:%vreg74
5968B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5984B		%X0<def> = COPY %vreg71; GPR64:%vreg71
6000B		%X1<def> = COPY %vreg72; GPR64:%vreg72
6016B		%X2<def> = COPY %vreg74; GPR64all:%vreg74
6032B		BL <ga:@gomp_init_task>, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %X2<imp-use>, %SP<imp-def>, ...
6048B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
6064B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
6080B		STACKMAP 16, 0, 0, <fi#17>, 0, 0, <fi#3>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#19>, 0, 0, <fi#18>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#14>, 0, 0, <fi#16>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack17] LD8[FixedStack3] LD8[FixedStack2] LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack19] LD8[FixedStack18](align=1) LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack14] LD8[FixedStack16] LD8[FixedStack10] LD8[FixedStack9]
6096B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
6112B		%vreg75<def> = LDRWui <fi#8>, 0; mem:LD4[%priority.addr] GPR32:%vreg75
6128B		%vreg76<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64common:%vreg76
6144B		STRWui %vreg75, %vreg76, 22; mem:ST4[%priority99] GPR32:%vreg75 GPR64common:%vreg76
6160B		%vreg77<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64common:%vreg77
6176B		%vreg78<def> = MOVi32imm 1; GPR32:%vreg78
6192B		STRWui %vreg78, %vreg77, 50; mem:ST4[%kind100] GPR32:%vreg78 GPR64common:%vreg77
6208B		%vreg79<def> = LDRXui <fi#15>, 0; mem:LD8[%parent] GPR64common:%vreg79
6224B		%vreg80<def> = LDRBBui %vreg79, 204; mem:LD1[%in_tied_task101] GPR32:%vreg80 GPR64common:%vreg79
6240B		%vreg81<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64common:%vreg81
6256B		%vreg82<def> = ANDWri %vreg80, 0; GPR32common:%vreg82 GPR32:%vreg80
6272B		STRBBui %vreg82, %vreg81, 204; mem:ST1[%in_tied_task103] GPR32common:%vreg82 GPR64common:%vreg81
6288B		%vreg83<def> = LDRXui <fi#16>, 0; mem:LD8[%taskgroup79] GPR64:%vreg83
6304B		%vreg84<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64common:%vreg84
6320B		STRXui %vreg83, %vreg84, 5; mem:ST8[%taskgroup105] GPR64:%vreg83 GPR64common:%vreg84
6336B		%vreg85<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64:%vreg85
6352B		%vreg86<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg86
6368B		STRXui %vreg85, %vreg86, 10; mem:ST8[%task106] GPR64:%vreg85 GPR64common:%vreg86
6384B		%vreg87<def> = LDRXui <fi#2>, 0; mem:LD8[%cpyfn.addr] GPR64:%vreg87
6400B		CBZX %vreg87, <BB#34>; GPR64:%vreg87
6416B		B <BB#33>
	    Successors according to CFG: BB#33 BB#34

6432B	BB#33: derived from LLVM BB %if.then.108
	    Predecessors according to CFG: BB#32
6448B		%vreg91<def> = LDRXui <fi#2>, 0; mem:LD8[%cpyfn.addr] GPR64:%vreg91
6464B		%vreg92<def> = LDRXui <fi#17>, 0; mem:LD8[%arg81] GPR64:%vreg92
6480B		%vreg93<def> = LDRXui <fi#1>, 0; mem:LD8[%data.addr] GPR64:%vreg93
6496B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
6512B		%X0<def> = COPY %vreg92; GPR64:%vreg92
6528B		%X1<def> = COPY %vreg93; GPR64:%vreg93
6544B		BLR %vreg91, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %SP<imp-def>, ...; GPR64:%vreg91
6560B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
6576B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
6592B		STACKMAP 17, 0, 0, <fi#17>, 0, 0, <fi#7>, 0, 0, <fi#19>, 0, 0, <fi#18>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#14>, 0, 0, <fi#16>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack17] LD8[FixedStack7] LD8[FixedStack19] LD8[FixedStack18](align=1) LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack14] LD8[FixedStack16] LD8[FixedStack10] LD8[FixedStack9]
6608B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
6624B		%vreg94<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64common:%vreg94
6640B		%vreg95<def> = MOVi32imm 1; GPR32:%vreg95
6656B		STRBBui %vreg95, %vreg94, 206; mem:ST1[%copy_ctors_done] GPR32:%vreg95 GPR64common:%vreg94
6672B		B <BB#35>
	    Successors according to CFG: BB#35

6688B	BB#34: derived from LLVM BB %if.else.109
	    Predecessors according to CFG: BB#32
6704B		%vreg88<def> = LDRXui <fi#17>, 0; mem:LD8[%arg81] GPR64:%vreg88
6720B		%vreg89<def> = LDRXui <fi#1>, 0; mem:LD8[%data.addr] GPR64:%vreg89
6736B		%vreg90<def> = LDRXui <fi#3>, 0; mem:LD8[%arg_size.addr] GPR64:%vreg90
6752B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
6768B		%X0<def> = COPY %vreg88; GPR64:%vreg88
6784B		%X1<def> = COPY %vreg89; GPR64:%vreg89
6800B		%X2<def> = COPY %vreg90; GPR64:%vreg90
6816B		BL <es:memcpy>, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %X2<imp-use>, %SP<imp-def>, ...
6832B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
6848B		B <BB#35>
	    Successors according to CFG: BB#35

6864B	BB#35: derived from LLVM BB %if.end.110
	    Predecessors according to CFG: BB#34 BB#33
6880B		%vreg96<def> = LDRXui <fi#15>, 0; mem:LD8[%parent] GPR64:%vreg96
6896B		%vreg97<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg97
6912B		STRXui %vreg96, %vreg97, 10; mem:ST8[%task111] GPR64:%vreg96 GPR64common:%vreg97
6928B		%vreg98<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64common:%vreg98
6944B		%vreg99<def> = MOVi32imm 2; GPR32:%vreg99
6960B		STRWui %vreg99, %vreg98, 50; mem:ST4[%kind112] GPR32:%vreg99 GPR64common:%vreg98
6976B		%vreg100<def> = LDRXui <fi#0>, 0; mem:LD8[%fn.addr] GPR64:%vreg100
6992B		%vreg101<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64common:%vreg101
7008B		STRXui %vreg100, %vreg101, 23; mem:ST8[%fn113] GPR64:%vreg100 GPR64common:%vreg101
7024B		%vreg102<def> = LDRXui <fi#17>, 0; mem:LD8[%arg81] GPR64:%vreg102
7040B		%vreg103<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64common:%vreg103
7056B		STRXui %vreg102, %vreg103, 24; mem:ST8[%fn_data] GPR64:%vreg102 GPR64common:%vreg103
7072B		%vreg104<def> = LDRWui <fi#6>, 0; mem:LD4[%flags.addr] GPR32:%vreg104
7088B		%vreg105<def> = UBFMWri %vreg104, 1, 1; GPR32:%vreg105,%vreg104
7104B		%vreg106<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64common:%vreg106
7120B		STRBBui %vreg105, %vreg106, 205; mem:ST1[%final_task116] GPR32:%vreg105 GPR64common:%vreg106
7136B		%vreg107<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg107
7152B		%vreg108<def> = ADDXri %vreg107, 1280, 0; GPR64sp:%vreg108 GPR64common:%vreg107
7168B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
7184B		%X0<def> = COPY %vreg108; GPR64sp:%vreg108
7200B		BL <ga:@gomp_mutex_lock>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...
7216B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
7232B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
7248B		STACKMAP 18, 0, 0, <fi#7>, 0, 0, <fi#19>, 0, 0, <fi#18>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#14>, 0, 0, <fi#16>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack7] LD8[FixedStack19] LD8[FixedStack18](align=1) LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack14] LD8[FixedStack16] LD8[FixedStack10]
7264B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
7280B		%vreg109<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg109
7296B		%vreg110<def> = ADDXri %vreg109, 128, 0; GPR64sp:%vreg110 GPR64common:%vreg109
7312B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
7328B		%X0<def> = COPY %vreg110; GPR64sp:%vreg110
7344B		BL <ga:@gomp_team_barrier_cancelled>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>, ...
7360B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
7376B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
7392B		STACKMAP 19, 0, 0, <fi#7>, 0, 0, <fi#19>, 0, 0, <fi#18>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#14>, 0, 0, <fi#16>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack7] LD8[FixedStack19] LD8[FixedStack18](align=1) LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack14] LD8[FixedStack16] LD8[FixedStack10]
7408B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
7424B		%vreg111<def> = COPY %W0; GPR32:%vreg111
7440B		TBNZW %vreg111, 0, <BB#38>; GPR32:%vreg111
7456B		B <BB#36>
	    Successors according to CFG: BB#38 BB#36

7472B	BB#36: derived from LLVM BB %lor.lhs.false.122
	    Predecessors according to CFG: BB#35
7488B		%vreg113<def> = LDRXui <fi#16>, 0; mem:LD8[%taskgroup79] GPR64:%vreg113
7536B		%vreg256<def> = COPY %WZR; GPR32common:%vreg256
7552B		CBZX %vreg113, <BB#39>; GPR64:%vreg113
7568B		B <BB#37>
	    Successors according to CFG: BB#37 BB#39

7584B	BB#37: derived from LLVM BB %land.lhs.true.124
	    Predecessors according to CFG: BB#36
7600B		%vreg116<def> = LDRXui <fi#16>, 0; mem:LD8[%taskgroup79] GPR64common:%vreg116
7616B		%vreg117<def> = LDRBBui %vreg116, 41; mem:LD1[%cancelled125] GPR32:%vreg117 GPR64common:%vreg116
7664B		%vreg256<def> = COPY %WZR; GPR32common:%vreg256
7680B		TBZW %vreg117, 0, <BB#39>; GPR32:%vreg117
7696B		B <BB#38>
	    Successors according to CFG: BB#38 BB#39

7712B	BB#38: derived from LLVM BB %land.rhs
	    Predecessors according to CFG: BB#35 BB#37
7728B		%vreg119<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64common:%vreg119
7744B		%vreg120<def> = LDRBBui %vreg119, 206; mem:LD1[%copy_ctors_done128] GPR32:%vreg120 GPR64common:%vreg119
7760B		%vreg256<def> = EORWri %vreg120, 0; GPR32common:%vreg256 GPR32:%vreg120
7808B		B <BB#39>
	    Successors according to CFG: BB#39

7824B	BB#39: derived from LLVM BB %land.end
	    Predecessors according to CFG: BB#36 BB#37 BB#38
7856B		TBZW %vreg256, 0, <BB#41>; GPR32common:%vreg256
7872B		B <BB#40>
	    Successors according to CFG: BB#40 BB#41

7888B	BB#40: derived from LLVM BB %if.then.132
	    Predecessors according to CFG: BB#39
7904B		%vreg183<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg183
7920B		%vreg184<def> = ADDXri %vreg183, 1280, 0; GPR64sp:%vreg184 GPR64common:%vreg183
7936B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
7952B		%X0<def> = COPY %vreg184; GPR64sp:%vreg184
7968B		BL <ga:@gomp_mutex_unlock>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...
7984B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
8000B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
8016B		STACKMAP 20, 0, 0, <fi#14>, 0, ...; mem:LD8[FixedStack14]
8032B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
8048B		%vreg185<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64:%vreg185
8064B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
8080B		%X0<def> = COPY %vreg185; GPR64:%vreg185
8096B		BL <ga:@gomp_finish_task>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...
8112B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
8128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
8144B		STACKMAP 21, 0, 0, <fi#14>, 0, ...; mem:LD8[FixedStack14]
8160B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
8176B		%vreg186<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64:%vreg186
8192B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
8208B		%X0<def> = COPY %vreg186; GPR64:%vreg186
8224B		BL <ga:@free>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...
8240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
8256B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
8272B		STACKMAP 22, 0, ...
8288B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
8304B		B <BB#52>
	    Successors according to CFG: BB#52

8320B	BB#41: derived from LLVM BB %if.end.134
	    Predecessors according to CFG: BB#39
8336B		%vreg122<def> = LDRXui <fi#16>, 0; mem:LD8[%taskgroup79] GPR64:%vreg122
8352B		CBZX %vreg122, <BB#43>; GPR64:%vreg122
8368B		B <BB#42>
	    Successors according to CFG: BB#42 BB#43

8384B	BB#42: derived from LLVM BB %if.then.136
	    Predecessors according to CFG: BB#41
8400B		%vreg123<def> = LDRXui <fi#16>, 0; mem:LD8[%taskgroup79] GPR64common:%vreg123
8416B		%vreg124<def> = LDRXui %vreg123, 6; mem:LD8[%num_children] GPR64common:%vreg124,%vreg123
8432B		%vreg125<def> = ADDXri %vreg124, 1, 0; GPR64common:%vreg125,%vreg124
8448B		STRXui %vreg125, %vreg123, 6; mem:ST8[%num_children] GPR64common:%vreg125,%vreg123
8464B		B <BB#43>
	    Successors according to CFG: BB#43

8480B	BB#43: derived from LLVM BB %if.end.137
	    Predecessors according to CFG: BB#41 BB#42
8496B		%vreg126<def> = LDRXui <fi#19>, 0; mem:LD8[%depend_size] GPR64:%vreg126
8512B		CBZX %vreg126, <BB#47>; GPR64:%vreg126
8528B		B <BB#44>
	    Successors according to CFG: BB#44 BB#47

8544B	BB#44: derived from LLVM BB %if.then.139
	    Predecessors according to CFG: BB#43
8560B		%vreg127<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64:%vreg127
8576B		%vreg128<def> = LDRXui <fi#15>, 0; mem:LD8[%parent] GPR64:%vreg128
8592B		%vreg129<def> = LDRXui <fi#7>, 0; mem:LD8[%depend.addr] GPR64:%vreg129
8608B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
8624B		%X0<def> = COPY %vreg127; GPR64:%vreg127
8640B		%X1<def> = COPY %vreg128; GPR64:%vreg128
8656B		%X2<def> = COPY %vreg129; GPR64:%vreg129
8672B		BL <ga:@gomp_task_handle_depend>, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %X2<imp-use>, %SP<imp-def>, ...
8688B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
8704B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
8720B		STACKMAP 23, 0, 0, <fi#18>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#14>, 0, 0, <fi#16>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack18](align=1) LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack14] LD8[FixedStack16] LD8[FixedStack10]
8736B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
8752B		%vreg130<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64common:%vreg130
8768B		%vreg131<def> = LDRXui %vreg130, 10; mem:LD8[%num_dependees] GPR64:%vreg131 GPR64common:%vreg130
8784B		CBZX %vreg131, <BB#46>; GPR64:%vreg131
8800B		B <BB#45>
	    Successors according to CFG: BB#45 BB#46

8816B	BB#45: derived from LLVM BB %if.then.141
	    Predecessors according to CFG: BB#44
8832B		%vreg181<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg181
8848B		%vreg182<def> = ADDXri %vreg181, 1280, 0; GPR64sp:%vreg182 GPR64common:%vreg181
8864B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
8880B		%X0<def> = COPY %vreg182; GPR64sp:%vreg182
8896B		BL <ga:@gomp_mutex_unlock>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...
8912B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
8928B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
8944B		STACKMAP 24, 0, ...
8960B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
8976B		B <BB#52>
	    Successors according to CFG: BB#52

8992B	BB#46: derived from LLVM BB %if.end.143
	    Predecessors according to CFG: BB#44
9008B		B <BB#47>
	    Successors according to CFG: BB#47

9024B	BB#47: derived from LLVM BB %if.end.144
	    Predecessors according to CFG: BB#43 BB#46
9040B		%vreg132<def> = LDRXui <fi#15>, 0; mem:LD8[%parent] GPR64common:%vreg132
9056B		%vreg133<def> = ADDXri %vreg132, 8, 0; GPR64sp:%vreg133 GPR64common:%vreg132
9072B		%vreg134<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64common:%vreg134
9088B		%vreg135<def> = LDRWui <fi#8>, 0; mem:LD4[%priority.addr] GPR32:%vreg135
9104B		%vreg136<def> = LDRBBui %vreg134, 207; mem:LD1[%parent_depends_on] GPR32:%vreg136 GPR64common:%vreg134
9120B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
9136B		%vreg137<def> = ANDWri %vreg136, 0; GPR32sp:%vreg137 GPR32:%vreg136
9184B		%W0<def> = MOVi32imm 1
9200B		%X1<def> = COPY %vreg133; GPR64sp:%vreg133
9216B		%X2<def> = COPY %vreg134; GPR64common:%vreg134
9232B		%W3<def> = COPY %vreg135; GPR32:%vreg135
9248B		%W4<def> = COPY %WZR
9264B		%W5<def> = COPY %WZR
9280B		%W6<def> = COPY %vreg137; GPR32sp:%vreg137
9296B		BL <ga:@priority_queue_insert>, <regmask>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use>, %X2<imp-use>, %W3<imp-use>, %W4<imp-use>, %W5<imp-use>, %W6<imp-use>, %SP<imp-def>, ...
9312B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
9328B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
9344B		STACKMAP 25, 0, 0, <fi#18>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#14>, 0, 0, <fi#16>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack18](align=1) LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack14] LD8[FixedStack16] LD8[FixedStack10]
9360B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
9376B		%vreg140<def> = LDRXui <fi#16>, 0; mem:LD8[%taskgroup79] GPR64:%vreg140
9392B		CBZX %vreg140, <BB#49>; GPR64:%vreg140
9408B		B <BB#48>
	    Successors according to CFG: BB#48 BB#49

9424B	BB#48: derived from LLVM BB %if.then.148
	    Predecessors according to CFG: BB#47
9440B		%vreg141<def> = LDRXui <fi#16>, 0; mem:LD8[%taskgroup79] GPR64common:%vreg141
9456B		%vreg142<def> = ADDXri %vreg141, 8, 0; GPR64sp:%vreg142 GPR64common:%vreg141
9472B		%vreg143<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64common:%vreg143
9488B		%vreg144<def> = LDRWui <fi#8>, 0; mem:LD4[%priority.addr] GPR32:%vreg144
9504B		%vreg145<def> = LDRBBui %vreg143, 207; mem:LD1[%parent_depends_on149] GPR32:%vreg145 GPR64common:%vreg143
9520B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
9536B		%vreg146<def> = ANDWri %vreg145, 0; GPR32sp:%vreg146 GPR32:%vreg145
9584B		%W0<def> = MOVi32imm 2
9600B		%X1<def> = COPY %vreg142; GPR64sp:%vreg142
9616B		%X2<def> = COPY %vreg143; GPR64common:%vreg143
9632B		%W3<def> = COPY %vreg144; GPR32:%vreg144
9648B		%W4<def> = COPY %WZR
9664B		%W5<def> = COPY %WZR
9680B		%W6<def> = COPY %vreg146; GPR32sp:%vreg146
9696B		BL <ga:@priority_queue_insert>, <regmask>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use>, %X2<imp-use>, %W3<imp-use>, %W4<imp-use>, %W5<imp-use>, %W6<imp-use>, %SP<imp-def>, ...
9712B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
9728B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
9744B		STACKMAP 26, 0, 0, <fi#18>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#14>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack18](align=1) LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack14] LD8[FixedStack10]
9760B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
9776B		B <BB#49>
	    Successors according to CFG: BB#49

9792B	BB#49: derived from LLVM BB %if.end.151
	    Predecessors according to CFG: BB#47 BB#48
9808B		%vreg149<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg149
9824B		%vreg150<def> = ADDXri %vreg149, 1288, 0; GPR64sp:%vreg150 GPR64common:%vreg149
9840B		%vreg151<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64common:%vreg151
9856B		%vreg152<def> = LDRWui <fi#8>, 0; mem:LD4[%priority.addr] GPR32:%vreg152
9872B		%vreg153<def> = LDRBBui %vreg151, 207; mem:LD1[%parent_depends_on152] GPR32:%vreg153 GPR64common:%vreg151
9888B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
9904B		%vreg154<def> = ANDWri %vreg153, 0; GPR32sp:%vreg154 GPR32:%vreg153
9952B		%W0<def> = COPY %WZR
9968B		%X1<def> = COPY %vreg150; GPR64sp:%vreg150
9984B		%X2<def> = COPY %vreg151; GPR64common:%vreg151
10000B		%W3<def> = COPY %vreg152; GPR32:%vreg152
10016B		%W4<def> = MOVi32imm 1
10032B		%W5<def> = COPY %WZR
10048B		%W6<def> = COPY %vreg154; GPR32sp:%vreg154
10064B		BL <ga:@priority_queue_insert>, <regmask>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use>, %X2<imp-use>, %W3<imp-use>, %W4<imp-use>, %W5<imp-use>, %W6<imp-use>, %SP<imp-def>, ...
10080B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
10096B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
10112B		STACKMAP 27, 0, 0, <fi#18>, 0, 0, <fi#15>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack18](align=1) LD8[FixedStack15] LD8[FixedStack10]
10128B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
10144B		%vreg157<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg157
10160B		%vreg158<def> = LDRWui %vreg157, 330; mem:LD4[%task_count154] GPR32common:%vreg158 GPR64common:%vreg157
10176B		%vreg159<def> = ADDWri %vreg158, 1, 0; GPR32common:%vreg159,%vreg158
10192B		STRWui %vreg159, %vreg157, 330; mem:ST4[%task_count154] GPR32common:%vreg159 GPR64common:%vreg157
10208B		%vreg160<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg160
10224B		%vreg161<def> = LDRWui %vreg160, 331; mem:LD4[%task_queued_count] GPR32common:%vreg161 GPR64common:%vreg160
10240B		%vreg162<def> = ADDWri %vreg161, 1, 0; GPR32common:%vreg162,%vreg161
10256B		STRWui %vreg162, %vreg160, 331; mem:ST4[%task_queued_count] GPR32common:%vreg162 GPR64common:%vreg160
10272B		%vreg163<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg163
10288B		%vreg164<def> = ADDXri %vreg163, 128, 0; GPR64sp:%vreg164 GPR64common:%vreg163
10304B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
10320B		%X0<def> = COPY %vreg164; GPR64sp:%vreg164
10336B		BL <ga:@gomp_team_barrier_set_task_pending>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...
10352B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
10368B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
10384B		STACKMAP 28, 0, 0, <fi#18>, 0, 0, <fi#15>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack18](align=1) LD8[FixedStack15] LD8[FixedStack10]
10400B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
10416B		%vreg165<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg165
10432B		%vreg166<def> = LDRWui %vreg165, 332; mem:LD4[%task_running_count] GPR32:%vreg166 GPR64common:%vreg165
10448B		%vreg167<def> = LDRXui <fi#15>, 0; mem:LD8[%parent] GPR64common:%vreg167
10464B		%vreg168<def> = LDRBBui %vreg167, 204; mem:LD1[%in_tied_task158] GPR32:%vreg168 GPR64common:%vreg167
10480B		%vreg169<def> = ORNWrr %WZR, %vreg168; GPR32:%vreg169,%vreg168
10496B		%vreg170<def> = ANDWri %vreg169, 0; GPR32common:%vreg170 GPR32:%vreg169
10512B		%vreg171<def> = ADDWrr %vreg166, %vreg170; GPR32:%vreg171,%vreg166 GPR32common:%vreg170
10528B		%vreg172<def> = LDRWui %vreg165, 0; mem:LD4[%nthreads162] GPR32:%vreg172 GPR64common:%vreg165
10544B		%vreg173<def,dead> = SUBSWrr %vreg171, %vreg172, %NZCV<imp-def>; GPR32:%vreg173,%vreg171,%vreg172
10560B		%vreg174<def> = CSINCWr %WZR, %WZR, 2, %NZCV<imp-use,kill>; GPR32:%vreg174
10576B		STRBBui %vreg174, <fi#18>, 0; mem:ST1[%do_wake] GPR32:%vreg174
10592B		%vreg175<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg175
10608B		%vreg176<def> = ADDXri %vreg175, 1280, 0; GPR64sp:%vreg176 GPR64common:%vreg175
10624B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
10640B		%X0<def> = COPY %vreg176; GPR64sp:%vreg176
10656B		BL <ga:@gomp_mutex_unlock>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...
10672B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
10688B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
10704B		STACKMAP 29, 0, 0, <fi#18>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack18](align=1) LD8[FixedStack10]
10720B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
10736B		%vreg177<def> = LDRBBui <fi#18>, 0; mem:LD1[%do_wake] GPR32:%vreg177
10752B		TBZW %vreg177, 0, <BB#51>; GPR32:%vreg177
10768B		B <BB#50>
	    Successors according to CFG: BB#50 BB#51

10784B	BB#50: derived from LLVM BB %if.then.168
	    Predecessors according to CFG: BB#49
10800B		%vreg178<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg178
10816B		%vreg179<def> = ADDXri %vreg178, 128, 0; GPR64sp:%vreg179 GPR64common:%vreg178
10832B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
10864B		%X0<def> = COPY %vreg179; GPR64sp:%vreg179
10880B		%W1<def> = MOVi32imm 1
10896B		BL <ga:@gomp_team_barrier_wake>, <regmask>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %SP<imp-def>, ...
10912B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
10928B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
10944B		STACKMAP 30, 0, ...
10960B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
10976B		B <BB#51>
	    Successors according to CFG: BB#51

10992B	BB#51: derived from LLVM BB %if.end.170
	    Predecessors according to CFG: BB#49 BB#50
11008B		B <BB#52>
	    Successors according to CFG: BB#52

11024B	BB#52: derived from LLVM BB %if.end.171
	    Predecessors according to CFG: BB#51 BB#45 BB#40 BB#29 BB#4
11040B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
11072B		%X0<def> = COPY %XZR
11088B		%X1<def> = COPY %XZR
11104B		BL <ga:@check_migrate>, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %SP<imp-def>, ...
11120B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
11136B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
11152B		STACKMAP 31, 0, ...
11168B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
11184B		RET_ReallyLR

# End machine code for function GOMP_task.

handleMove 128B -> 152B: %vreg4<def> = COPY %X0; GPR64:%vreg4
     %vreg4:	[128r,320r:0)  0@128r
        -->	[152r,320r:0)  0@152r
     W0:	[0B,128r:0)[208r,240r:38)[480r,560r:37)[720r,736r:36)[736r,816r:8)[2176r,2192r:19)[2368r,2384r:2)[2384r,2464r:18)[2512r,2560r:17)[3792r,3824r:15)[3952r,3968r:14)[4160r,4176r:16)[4352r,4384r:13)[4384r,4464r:1)[4576r,4592r:12)[4720r,4736r:11)[4864r,4880r:10)[5536r,5552r:35)[5552r,5632r:34)[5856r,5872r:7)[5872r,5952r:33)[5984r,6032r:32)[6512r,6544r:30)[6768r,6816r:31)[7184r,7200r:29)[7328r,7344r:28)[7344r,7424r:6)[7952r,7968r:22)[8080r,8096r:21)[8208r,8224r:20)[8624r,8672r:27)[8880r,8896r:23)[9184r,9296r:5)[9584r,9696r:4)[9952r,10064r:3)[10320r,10336r:26)[10640r,10656r:25)[10864r,10896r:24)[11072r,11104r:9)  0@0B-phi 1@4384r 2@2368r 3@9952r 4@9584r 5@9184r 6@7344r 7@5856r 8@736r 9@11072r 10@4864r 11@4720r 12@4576r 13@4352r 14@3952r 15@3792r 16@4160r 17@2512r 18@2384r 19@2176r 20@8208r 21@8080r 22@7952r 23@8880r 24@10864r 25@10640r 26@10320r 27@8624r 28@7328r 29@7184r 30@6512r 31@6768r 32@5984r 33@5872r 34@5552r 35@5536r 36@720r 37@480r 38@208r
        -->	[0B,152r:0)[208r,240r:38)[480r,560r:37)[720r,736r:36)[736r,816r:8)[2176r,2192r:19)[2368r,2384r:2)[2384r,2464r:18)[2512r,2560r:17)[3792r,3824r:15)[3952r,3968r:14)[4160r,4176r:16)[4352r,4384r:13)[4384r,4464r:1)[4576r,4592r:12)[4720r,4736r:11)[4864r,4880r:10)[5536r,5552r:35)[5552r,5632r:34)[5856r,5872r:7)[5872r,5952r:33)[5984r,6032r:32)[6512r,6544r:30)[6768r,6816r:31)[7184r,7200r:29)[7328r,7344r:28)[7344r,7424r:6)[7952r,7968r:22)[8080r,8096r:21)[8208r,8224r:20)[8624r,8672r:27)[8880r,8896r:23)[9184r,9296r:5)[9584r,9696r:4)[9952r,10064r:3)[10320r,10336r:26)[10640r,10656r:25)[10864r,10896r:24)[11072r,11104r:9)  0@0B-phi 1@4384r 2@2368r 3@9952r 4@9584r 5@9184r 6@7344r 7@5856r 8@736r 9@11072r 10@4864r 11@4720r 12@4576r 13@4352r 14@3952r 15@3792r 16@4160r 17@2512r 18@2384r 19@2176r 20@8208r 21@8080r 22@7952r 23@8880r 24@10864r 25@10640r 26@10320r 27@8624r 28@7328r 29@7184r 30@6512r 31@6768r 32@5984r 33@5872r 34@5552r 35@5536r 36@720r 37@480r 38@208r
handleMove 112B -> 148B: %vreg5<def> = COPY %X1; GPR64:%vreg5
     %vreg5:	[112r,336r:0)  0@112r
        -->	[148r,336r:0)  0@148r
     W1:	[0B,112r:0)[224r,240r:13)[2528r,2560r:5)[3808r,3824r:4)[4368r,4384r:1)[6000r,6032r:12)[6528r,6544r:10)[6784r,6816r:11)[8640r,8672r:9)[9200r,9296r:8)[9600r,9696r:7)[9968r,10064r:6)[10880r,10896r:2)[11088r,11104r:3)  0@0B-phi 1@4368r 2@10880r 3@11088r 4@3808r 5@2528r 6@9968r 7@9600r 8@9200r 9@8640r 10@6528r 11@6784r 12@6000r 13@224r
        -->	[0B,148r:0)[224r,240r:13)[2528r,2560r:5)[3808r,3824r:4)[4368r,4384r:1)[6000r,6032r:12)[6528r,6544r:10)[6784r,6816r:11)[8640r,8672r:9)[9200r,9296r:8)[9600r,9696r:7)[9968r,10064r:6)[10880r,10896r:2)[11088r,11104r:3)  0@0B-phi 1@4368r 2@10880r 3@11088r 4@3808r 5@2528r 6@9968r 7@9600r 8@9200r 9@8640r 10@6528r 11@6784r 12@6000r 13@224r
handleMove 96B -> 152B: %vreg6<def> = COPY %X2; GPR64:%vreg6
     %vreg6:	[96r,352r:0)  0@96r
        -->	[152r,352r:0)  0@152r
     W2:	[0B,96r:0)[2544r,2560r:1)[6016r,6032r:7)[6800r,6816r:6)[8656r,8672r:5)[9216r,9296r:4)[9616r,9696r:3)[9984r,10064r:2)  0@0B-phi 1@2544r 2@9984r 3@9616r 4@9216r 5@8656r 6@6800r 7@6016r
        -->	[0B,152r:0)[2544r,2560r:1)[6016r,6032r:7)[6800r,6816r:6)[8656r,8672r:5)[9216r,9296r:4)[9616r,9696r:3)[9984r,10064r:2)  0@0B-phi 1@2544r 2@9984r 3@9616r 4@9216r 5@8656r 6@6800r 7@6016r
handleMove 80B -> 148B: %vreg7<def> = COPY %X3; GPR64:%vreg7
     %vreg7:	[80r,368r:0)  0@80r
        -->	[148r,368r:0)  0@148r
     W3:	[0B,80r:0)[9232r,9296r:3)[9632r,9696r:2)[10000r,10064r:1)  0@0B-phi 1@10000r 2@9632r 3@9232r
        -->	[0B,148r:0)[9232r,9296r:3)[9632r,9696r:2)[10000r,10064r:1)  0@0B-phi 1@10000r 2@9632r 3@9232r
handleMove 64B -> 152B: %vreg8<def> = COPY %X4; GPR64:%vreg8
     %vreg8:	[64r,384r:0)  0@64r
        -->	[152r,384r:0)  0@152r
     W4:	[0B,64r:0)[9248r,9296r:3)[9648r,9696r:2)[10016r,10064r:1)  0@0B-phi 1@10016r 2@9648r 3@9248r
        -->	[0B,152r:0)[9248r,9296r:3)[9648r,9696r:2)[10016r,10064r:1)  0@0B-phi 1@10016r 2@9648r 3@9248r
handleMove 48B -> 148B: %vreg9<def> = COPY %W5; GPR32:%vreg9
     %vreg9:	[48r,200r:0)  0@48r
        -->	[148r,200r:0)  0@148r
     W5:	[0B,48r:0)[9264r,9296r:3)[9664r,9696r:2)[10032r,10064r:1)  0@0B-phi 1@10032r 2@9664r 3@9264r
        -->	[0B,148r:0)[9264r,9296r:3)[9664r,9696r:2)[10032r,10064r:1)  0@0B-phi 1@10032r 2@9664r 3@9264r
handleMove 2656B -> 2680B: STRWui %vreg199, <fi#11>, 50; mem:ST4[%kind] GPR32:%vreg199
     %vreg199:	[2640r,2656r:0)  0@2640r
        -->	[2640r,2680r:0)  0@2640r
handleMove 2640B -> 2676B: %vreg199<def> = MOVi32imm 1; GPR32:%vreg199
     %vreg199:	[2640r,2680r:0)  0@2640r
        -->	[2676r,2680r:0)  0@2676r
handleMove 3072B -> 3096B: STRWui %vreg211, <fi#11>, 22; mem:ST4[%priority48] GPR32:%vreg211
     %vreg211:	[3056r,3072r:0)  0@3056r
        -->	[3056r,3096r:0)  0@3056r
handleMove 3040B -> 3092B: STRBBui %vreg210, <fi#11>, 205; mem:ST1[%final_task46] GPR32common:%vreg210
     %vreg210:	[3024r,3040r:0)  0@3024r
        -->	[3024r,3092r:0)  0@3024r
handleMove 3024B -> 3096B: %vreg210<def> = ANDWri %vreg255, 0; GPR32common:%vreg210 GPR32:%vreg255
     %vreg210:	[3024r,3104r:0)  0@3024r
        -->	[3096r,3104r:0)  0@3096r
     %vreg255:	[2816r,2896B:0)[2928r,2992B:1)[2992B,3024r:2)  0@2816r 1@2928r 2@2992B-phi
        -->	[2816r,2896B:0)[2928r,2992B:1)[2992B,3096r:2)  0@2816r 1@2928r 2@2992B-phi
handleMove 3232B -> 3256B: STRBBui %vreg217, <fi#11>, 204; mem:ST1[%in_tied_task54] GPR32common:%vreg217
     %vreg217:	[3216r,3232r:0)  0@3216r
        -->	[3216r,3256r:0)  0@3216r
handleMove 3216B -> 3252B: %vreg217<def> = ANDWri %vreg216, 0; GPR32common:%vreg217 GPR32:%vreg216
     %vreg217:	[3216r,3256r:0)  0@3216r
        -->	[3252r,3256r:0)  0@3252r
     %vreg216:	[3200r,3216r:0)  0@3200r
        -->	[3200r,3252r:0)  0@3200r
handleMove 3728B -> 3768B: STRXui %vreg238, <fi#13>, 0; mem:ST8[%arg] GPR64:%vreg238
     %vreg238:	[3712r,3792r:0)  0@3712r
        -->	[3712r,3792r:0)  0@3712r
handleMove 3712B -> 3764B: %vreg238<def> = BICXrr %vreg236, %vreg237; GPR64:%vreg238,%vreg236,%vreg237
     %vreg238:	[3712r,3792r:0)  0@3712r
        -->	[3764r,3792r:0)  0@3764r
     %vreg236:	[3680r,3712r:0)  0@3680r
        -->	[3680r,3764r:0)  0@3680r
     %vreg237:	[3696r,3712r:0)  0@3696r
        -->	[3696r,3764r:0)  0@3696r
handleMove 3696B -> 3768B: %vreg237<def> = SUBSXri %vreg234, 1, 0, %NZCV<imp-def,dead>; GPR64:%vreg237 GPR64common:%vreg234
     %vreg237:	[3696r,3776r:0)  0@3696r
        -->	[3768r,3776r:0)  0@3768r
     %vreg234:	[3648r,3696r:0)  0@3648r
        -->	[3648r,3768r:0)  0@3648r
     NZCV:	[1296r,1312r:6)[1840r,1856r:5)[3600r,3600d:2)[3680r,3680d:1)[3768r,3768d:0)[5744r,5744d:4)[10544r,10560r:3)  0@3768r 1@3680r 2@3600r 3@10544r 4@5744r 5@1840r 6@1296r
        -->	[1296r,1312r:6)[1840r,1856r:5)[3600r,3600d:2)[3680r,3680d:1)[3768r,3768d:0)[5744r,5744d:4)[10544r,10560r:3)  0@3768r 1@3680r 2@3600r 3@10544r 4@5744r 5@1840r 6@1296r
handleMove 3680B -> 3764B: %vreg236<def> = SUBSXri %vreg235, 1, 0, %NZCV<imp-def,dead>; GPR64:%vreg236 GPR64common:%vreg235
     %vreg236:	[3680r,3776r:0)  0@3680r
        -->	[3764r,3776r:0)  0@3764r
     %vreg235:	[3664r,3680r:0)  0@3664r
        -->	[3664r,3764r:0)  0@3664r
     NZCV:	[1296r,1312r:6)[1840r,1856r:5)[3600r,3600d:2)[3680r,3680d:1)[3768r,3768d:0)[5744r,5744d:4)[10544r,10560r:3)  0@3768r 1@3680r 2@3600r 3@10544r 4@5744r 5@1840r 6@1296r
        -->	[1296r,1312r:6)[1840r,1856r:5)[3600r,3600d:2)[3764r,3764d:1)[3768r,3768d:0)[5744r,5744d:4)[10544r,10560r:3)  0@3768r 1@3764r 2@3600r 3@10544r 4@5744r 5@1840r 6@1296r
handleMove 3664B -> 3768B: %vreg235<def> = ADDXrr %vreg233, %vreg234; GPR64common:%vreg235,%vreg234 GPR64:%vreg233
     %vreg235:	[3664r,3776r:0)  0@3664r
        -->	[3768r,3776r:0)  0@3768r
     %vreg233:	[3600r,3664r:0)  0@3600r
        -->	[3600r,3768r:0)  0@3600r
     %vreg234:	[3648r,3784r:0)  0@3648r
        -->	[3648r,3784r:0)  0@3648r
handleMove 3504B -> 3448B: %vreg229<def> = COPY %SP; GPR64:%vreg229
     %vreg229:	[3504r,3520r:0)  0@3504r
        -->	[3448r,3520r:0)  0@3448r
     WSP:	[192r,192d:166)[240r,240d:165)[256r,256d:164)[272r,272d:163)[304r,304d:162)[464r,464d:161)[480r,480d:160)[496r,496d:159)[512r,512d:158)[544r,544d:157)[704r,704d:156)[736r,736d:155)[752r,752d:154)[768r,768d:153)[800r,800d:152)[2160r,2160d:63)[2192r,2192d:62)[2208r,2208d:61)[2224r,2224d:60)[2256r,2256d:59)[2336r,2336d:58)[2384r,2384d:57)[2400r,2400d:56)[2416r,2416d:55)[2448r,2448d:54)[2480r,2480d:53)[2560r,2560d:52)[2576r,2576d:51)[2592r,2592d:50)[2624r,2624d:49)[3568r,3568d:43)[3616r,3616d:42)[3632r,3632d:41)[3808r,3808d:40)[3832r,3832d:39)[3840r,3840d:38)[3856r,3856d:37)[3888r,3888d:36)[3936r,3936d:35)[3968r,3968d:34)[3984r,3984d:33)[4000r,4000d:32)[4032r,4032d:31)[4064r,4064d:30)[4144r,4144d:48)[4176r,4176d:47)[4192r,4192d:46)[4208r,4208d:45)[4240r,4240d:44)[4320r,4320d:29)[4384r,4384d:28)[4400r,4400d:27)[4416r,4416d:26)[4448r,4448d:25)[4560r,4560d:24)[4592r,4592d:23)[4608r,4608d:22)[4624r,4624d:21)[4656r,4656d:20)[4704r,4704d:19)[4736r,4736d:18)[4752r,4752d:17)[4768r,4768d:16)[4800r,4800d:15)[4848r,4848d:14)[4880r,4880d:13)[4896r,4896d:12)[4912r,4912d:11)[4944r,4944d:10)[4992r,4992d:9)[5008r,5008d:8)[5024r,5024d:7)[5040r,5040d:6)[5072r,5072d:5)[5520r,5520d:151)[5552r,5552d:150)[5568r,5568d:149)[5584r,5584d:148)[5616r,5616d:147)[5824r,5824d:146)[5872r,5872d:145)[5888r,5888d:144)[5904r,5904d:143)[5936r,5936d:142)[5968r,5968d:141)[6032r,6032d:140)[6048r,6048d:139)[6064r,6064d:138)[6096r,6096d:137)[6496r,6496d:133)[6544r,6544d:132)[6560r,6560d:131)[6576r,6576d:130)[6608r,6608d:129)[6752r,6752d:136)[6816r,6816d:135)[6832r,6832d:134)[7168r,7168d:128)[7200r,7200d:127)[7216r,7216d:126)[7232r,7232d:125)[7264r,7264d:124)[7312r,7312d:123)[7344r,7344d:122)[7360r,7360d:121)[7376r,7376d:120)[7408r,7408d:119)[7936r,7936d:78)[7968r,7968d:77)[7984r,7984d:76)[8000r,8000d:75)[8032r,8032d:74)[8064r,8064d:73)[8096r,8096d:72)[8112r,8112d:71)[8128r,8128d:70)[8160r,8160d:69)[8192r,8192d:68)[8224r,8224d:67)[8240r,8240d:66)[8256r,8256d:65)[8288r,8288d:64)[8608r,8608d:118)[8672r,8672d:117)[8688r,8688d:116)[8704r,8704d:115)[8736r,8736d:114)[8864r,8864d:83)[8896r,8896d:82)[8912r,8912d:81)[8928r,8928d:80)[8960r,8960d:79)[9120r,9120d:113)[9296r,9296d:112)[9312r,9312d:111)[9328r,9328d:110)[9360r,9360d:109)[9520r,9520d:108)[9696r,9696d:107)[9712r,9712d:106)[9728r,9728d:105)[9760r,9760d:104)[9888r,9888d:103)[10064r,10064d:102)[10080r,10080d:101)[10096r,10096d:100)[10128r,10128d:99)[10304r,10304d:98)[10336r,10336d:97)[10352r,10352d:96)[10368r,10368d:95)[10400r,10400d:94)[10624r,10624d:93)[10656r,10656d:92)[10672r,10672d:91)[10688r,10688d:90)[10720r,10720d:89)[10832r,10832d:88)[10896r,10896d:87)[10912r,10912d:86)[10928r,10928d:85)[10960r,10960d:84)[11040r,11040d:4)[11104r,11104d:3)[11120r,11120d:2)[11136r,11136d:1)[11168r,11168d:0)  0@11168r 1@11136r 2@11120r 3@11104r 4@11040r 5@5072r 6@5040r 7@5024r 8@5008r 9@4992r 10@4944r 11@4912r 12@4896r 13@4880r 14@4848r 15@4800r 16@4768r 17@4752r 18@4736r 19@4704r 20@4656r 21@4624r 22@4608r 23@4592r 24@4560r 25@4448r 26@4416r 27@4400r 28@4384r 29@4320r 30@4064r 31@4032r 32@4000r 33@3984r 34@3968r 35@3936r 36@3888r 37@3856r 38@3840r 39@3832r 40@3808r 41@3632r 42@3616r 43@3568r 44@4240r 45@4208r 46@4192r 47@4176r 48@4144r 49@2624r 50@2592r 51@2576r 52@2560r 53@2480r 54@2448r 55@2416r 56@2400r 57@2384r 58@2336r 59@2256r 60@2224r 61@2208r 62@2192r 63@2160r 64@8288r 65@8256r 66@8240r 67@8224r 68@8192r 69@8160r 70@8128r 71@8112r 72@8096r 73@8064r 74@8032r 75@8000r 76@7984r 77@7968r 78@7936r 79@8960r 80@8928r 81@8912r 82@8896r 83@8864r 84@10960r 85@10928r 86@10912r 87@10896r 88@10832r 89@10720r 90@10688r 91@10672r 92@10656r 93@10624r 94@10400r 95@10368r 96@10352r 97@10336r 98@10304r 99@10128r 100@10096r 101@10080r 102@10064r 103@9888r 104@9760r 105@9728r 106@9712r 107@9696r 108@9520r 109@9360r 110@9328r 111@9312r 112@9296r 113@9120r 114@8736r 115@8704r 116@8688r 117@8672r 118@8608r 119@7408r 120@7376r 121@7360r 122@7344r 123@7312r 124@7264r 125@7232r 126@7216r 127@7200r 128@7168r 129@6608r 130@6576r 131@6560r 132@6544r 133@6496r 134@6832r 135@6816r 136@6752r 137@6096r 138@6064r 139@6048r 140@6032r 141@5968r 142@5936r 143@5904r 144@5888r 145@5872r 146@5824r 147@5616r 148@5584r 149@5568r 150@5552r 151@5520r 152@800r 153@768r 154@752r 155@736r 156@704r 157@544r 158@512r 159@496r 160@480r 161@464r 162@304r 163@272r 164@256r 165@240r 166@192r
        -->	[192r,192d:166)[240r,240d:165)[256r,256d:164)[272r,272d:163)[304r,304d:162)[464r,464d:161)[480r,480d:160)[496r,496d:159)[512r,512d:158)[544r,544d:157)[704r,704d:156)[736r,736d:155)[752r,752d:154)[768r,768d:153)[800r,800d:152)[2160r,2160d:63)[2192r,2192d:62)[2208r,2208d:61)[2224r,2224d:60)[2256r,2256d:59)[2336r,2336d:58)[2384r,2384d:57)[2400r,2400d:56)[2416r,2416d:55)[2448r,2448d:54)[2480r,2480d:53)[2560r,2560d:52)[2576r,2576d:51)[2592r,2592d:50)[2624r,2624d:49)[3568r,3568d:43)[3616r,3616d:42)[3632r,3632d:41)[3808r,3808d:40)[3832r,3832d:39)[3840r,3840d:38)[3856r,3856d:37)[3888r,3888d:36)[3936r,3936d:35)[3968r,3968d:34)[3984r,3984d:33)[4000r,4000d:32)[4032r,4032d:31)[4064r,4064d:30)[4144r,4144d:48)[4176r,4176d:47)[4192r,4192d:46)[4208r,4208d:45)[4240r,4240d:44)[4320r,4320d:29)[4384r,4384d:28)[4400r,4400d:27)[4416r,4416d:26)[4448r,4448d:25)[4560r,4560d:24)[4592r,4592d:23)[4608r,4608d:22)[4624r,4624d:21)[4656r,4656d:20)[4704r,4704d:19)[4736r,4736d:18)[4752r,4752d:17)[4768r,4768d:16)[4800r,4800d:15)[4848r,4848d:14)[4880r,4880d:13)[4896r,4896d:12)[4912r,4912d:11)[4944r,4944d:10)[4992r,4992d:9)[5008r,5008d:8)[5024r,5024d:7)[5040r,5040d:6)[5072r,5072d:5)[5520r,5520d:151)[5552r,5552d:150)[5568r,5568d:149)[5584r,5584d:148)[5616r,5616d:147)[5824r,5824d:146)[5872r,5872d:145)[5888r,5888d:144)[5904r,5904d:143)[5936r,5936d:142)[5968r,5968d:141)[6032r,6032d:140)[6048r,6048d:139)[6064r,6064d:138)[6096r,6096d:137)[6496r,6496d:133)[6544r,6544d:132)[6560r,6560d:131)[6576r,6576d:130)[6608r,6608d:129)[6752r,6752d:136)[6816r,6816d:135)[6832r,6832d:134)[7168r,7168d:128)[7200r,7200d:127)[7216r,7216d:126)[7232r,7232d:125)[7264r,7264d:124)[7312r,7312d:123)[7344r,7344d:122)[7360r,7360d:121)[7376r,7376d:120)[7408r,7408d:119)[7936r,7936d:78)[7968r,7968d:77)[7984r,7984d:76)[8000r,8000d:75)[8032r,8032d:74)[8064r,8064d:73)[8096r,8096d:72)[8112r,8112d:71)[8128r,8128d:70)[8160r,8160d:69)[8192r,8192d:68)[8224r,8224d:67)[8240r,8240d:66)[8256r,8256d:65)[8288r,8288d:64)[8608r,8608d:118)[8672r,8672d:117)[8688r,8688d:116)[8704r,8704d:115)[8736r,8736d:114)[8864r,8864d:83)[8896r,8896d:82)[8912r,8912d:81)[8928r,8928d:80)[8960r,8960d:79)[9120r,9120d:113)[9296r,9296d:112)[9312r,9312d:111)[9328r,9328d:110)[9360r,9360d:109)[9520r,9520d:108)[9696r,9696d:107)[9712r,9712d:106)[9728r,9728d:105)[9760r,9760d:104)[9888r,9888d:103)[10064r,10064d:102)[10080r,10080d:101)[10096r,10096d:100)[10128r,10128d:99)[10304r,10304d:98)[10336r,10336d:97)[10352r,10352d:96)[10368r,10368d:95)[10400r,10400d:94)[10624r,10624d:93)[10656r,10656d:92)[10672r,10672d:91)[10688r,10688d:90)[10720r,10720d:89)[10832r,10832d:88)[10896r,10896d:87)[10912r,10912d:86)[10928r,10928d:85)[10960r,10960d:84)[11040r,11040d:4)[11104r,11104d:3)[11120r,11120d:2)[11136r,11136d:1)[11168r,11168d:0)  0@11168r 1@11136r 2@11120r 3@11104r 4@11040r 5@5072r 6@5040r 7@5024r 8@5008r 9@4992r 10@4944r 11@4912r 12@4896r 13@4880r 14@4848r 15@4800r 16@4768r 17@4752r 18@4736r 19@4704r 20@4656r 21@4624r 22@4608r 23@4592r 24@4560r 25@4448r 26@4416r 27@4400r 28@4384r 29@4320r 30@4064r 31@4032r 32@4000r 33@3984r 34@3968r 35@3936r 36@3888r 37@3856r 38@3840r 39@3832r 40@3808r 41@3632r 42@3616r 43@3568r 44@4240r 45@4208r 46@4192r 47@4176r 48@4144r 49@2624r 50@2592r 51@2576r 52@2560r 53@2480r 54@2448r 55@2416r 56@2400r 57@2384r 58@2336r 59@2256r 60@2224r 61@2208r 62@2192r 63@2160r 64@8288r 65@8256r 66@8240r 67@8224r 68@8192r 69@8160r 70@8128r 71@8112r 72@8096r 73@8064r 74@8032r 75@8000r 76@7984r 77@7968r 78@7936r 79@8960r 80@8928r 81@8912r 82@8896r 83@8864r 84@10960r 85@10928r 86@10912r 87@10896r 88@10832r 89@10720r 90@10688r 91@10672r 92@10656r 93@10624r 94@10400r 95@10368r 96@10352r 97@10336r 98@10304r 99@10128r 100@10096r 101@10080r 102@10064r 103@9888r 104@9760r 105@9728r 106@9712r 107@9696r 108@9520r 109@9360r 110@9328r 111@9312r 112@9296r 113@9120r 114@8736r 115@8704r 116@8688r 117@8672r 118@8608r 119@7408r 120@7376r 121@7360r 122@7344r 123@7312r 124@7264r 125@7232r 126@7216r 127@7200r 128@7168r 129@6608r 130@6576r 131@6560r 132@6544r 133@6496r 134@6832r 135@6816r 136@6752r 137@6096r 138@6064r 139@6048r 140@6032r 141@5968r 142@5936r 143@5904r 144@5888r 145@5872r 146@5824r 147@5616r 148@5584r 149@5568r 150@5552r 151@5520r 152@800r 153@768r 154@752r 155@736r 156@704r 157@544r 158@512r 159@496r 160@480r 161@464r 162@304r 163@272r 164@256r 165@240r 166@192r
handleMove 4368B -> 4328B: %W1<def> = COPY %WZR
     W1:	[0B,176r:0)[224r,240r:13)[2528r,2560r:5)[3824r,3832r:4)[4368r,4384r:1)[6000r,6032r:12)[6528r,6544r:10)[6784r,6816r:11)[8640r,8672r:9)[9200r,9296r:8)[9600r,9696r:7)[9968r,10064r:6)[10880r,10896r:2)[11088r,11104r:3)  0@0B-phi 1@4368r 2@10880r 3@11088r 4@3824r 5@2528r 6@9968r 7@9600r 8@9200r 9@8640r 10@6528r 11@6784r 12@6000r 13@224r
        -->	[0B,176r:0)[224r,240r:13)[2528r,2560r:5)[3824r,3832r:4)[4328r,4384r:1)[6000r,6032r:12)[6528r,6544r:10)[6784r,6816r:11)[8640r,8672r:9)[9200r,9296r:8)[9600r,9696r:7)[9968r,10064r:6)[10880r,10896r:2)[11088r,11104r:3)  0@0B-phi 1@4328r 2@10880r 3@11088r 4@3824r 5@2528r 6@9968r 7@9600r 8@9200r 9@8640r 10@6528r 11@6784r 12@6000r 13@224r
     WZR:	EMPTY
        -->	EMPTY
handleMove 5216B -> 5240B: STRXui %XZR, <fi#19>, 0; mem:ST8[%depend_size]
     WZR:	EMPTY
        -->	EMPTY
handleMove 5184B -> 5236B: STRXui %vreg49, <fi#16>, 0; mem:ST8[%taskgroup79] GPR64:%vreg49
     %vreg49:	[5168r,5184r:0)  0@5168r
        -->	[5168r,5236r:0)  0@5168r
AllocationOrder(GPR32sponly) = [ ]
handleMove 5776B -> 5816B: STRXui %vreg70, <fi#17>, 0; mem:ST8[%arg81] GPR64:%vreg70
     %vreg70:	[5760r,5776r:0)  0@5760r
        -->	[5760r,5816r:0)  0@5760r
handleMove 5760B -> 5812B: %vreg70<def> = BICXrr %vreg68, %vreg69; GPR64:%vreg70,%vreg69 GPR64common:%vreg68
     %vreg70:	[5760r,5816r:0)  0@5760r
        -->	[5812r,5816r:0)  0@5812r
     %vreg68:	[5728r,5760r:0)  0@5728r
        -->	[5728r,5812r:0)  0@5728r
     %vreg69:	[5744r,5760r:0)  0@5744r
        -->	[5744r,5812r:0)  0@5744r
handleMove 5744B -> 5816B: %vreg69<def> = SUBSXri %vreg66, 1, 0, %NZCV<imp-def,dead>; GPR64:%vreg69 GPR64common:%vreg66
     %vreg69:	[5744r,5824r:0)  0@5744r
        -->	[5816r,5824r:0)  0@5816r
     %vreg66:	[5696r,5744r:0)  0@5696r
        -->	[5696r,5816r:0)  0@5696r
     NZCV:	[1296r,1312r:6)[1840r,1856r:5)[3600r,3600d:2)[3776r,3776d:1)[3784r,3784d:0)[5744r,5744d:4)[10544r,10560r:3)  0@3784r 1@3776r 2@3600r 3@10544r 4@5744r 5@1840r 6@1296r
        -->	[1296r,1312r:6)[1840r,1856r:5)[3600r,3600d:2)[3776r,3776d:1)[3784r,3784d:0)[5816r,5816d:4)[10544r,10560r:3)  0@3784r 1@3776r 2@3600r 3@10544r 4@5816r 5@1840r 6@1296r
handleMove 5728B -> 5812B: %vreg68<def> = ADDXri %vreg67, 207, 0; GPR64common:%vreg68,%vreg67
     %vreg68:	[5728r,5824r:0)  0@5728r
        -->	[5812r,5824r:0)  0@5812r
     %vreg67:	[5712r,5728r:0)  0@5712r
        -->	[5712r,5812r:0)  0@5712r
handleMove 5712B -> 5816B: %vreg67<def> = ADDXrr %vreg65, %vreg66; GPR64common:%vreg67,%vreg66 GPR64:%vreg65
     %vreg67:	[5712r,5824r:0)  0@5712r
        -->	[5816r,5824r:0)  0@5816r
     %vreg65:	[5680r,5712r:0)  0@5680r
        -->	[5680r,5816r:0)  0@5680r
     %vreg66:	[5696r,5832r:0)  0@5696r
        -->	[5696r,5832r:0)  0@5696r
handleMove 5680B -> 5812B: %vreg65<def> = ADDXrr %vreg63, %vreg64; GPR64:%vreg65,%vreg63,%vreg64
     %vreg65:	[5680r,5816r:0)  0@5680r
        -->	[5812r,5816r:0)  0@5812r
     %vreg63:	[5632r,5680r:0)  0@5632r
        -->	[5632r,5812r:0)  0@5632r
     %vreg64:	[5664r,5680r:0)  0@5664r
        -->	[5664r,5812r:0)  0@5664r
handleMove 5792B -> 5816B: %vreg71<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64:%vreg71
     %vreg71:	[5792r,5984r:0)  0@5792r
        -->	[5816r,5984r:0)  0@5816r
handleMove 5456B -> 5480B: %vreg59<def> = ADDXrr %vreg57, %vreg58; GPR64:%vreg59,%vreg57,%vreg58
     %vreg59:	[5456r,5488r:0)  0@5456r
        -->	[5480r,5488r:0)  0@5480r
     %vreg57:	[5424r,5456r:0)  0@5424r
        -->	[5424r,5480r:0)  0@5424r
     %vreg58:	[5440r,5456r:0)  0@5440r
        -->	[5440r,5480r:0)  0@5440r
AllocationOrder(GPR32sponly) = [ ]
handleMove 7088B -> 7112B: %vreg105<def> = UBFMWri %vreg104, 1, 1; GPR32:%vreg105,%vreg104
     %vreg105:	[7088r,7120r:0)  0@7088r
        -->	[7112r,7120r:0)  0@7112r
     %vreg104:	[7072r,7088r:0)  0@7072r
        -->	[7072r,7112r:0)  0@7072r
handleMove 9248B -> 9128B: %W4<def> = COPY %WZR
     W4:	[0B,152r:0)[9248r,9296r:3)[9648r,9696r:2)[10016r,10064r:1)  0@0B-phi 1@10016r 2@9648r 3@9248r
        -->	[0B,152r:0)[9128r,9296r:3)[9648r,9696r:2)[10016r,10064r:1)  0@0B-phi 1@10016r 2@9648r 3@9128r
     WZR:	EMPTY
        -->	EMPTY
handleMove 9264B -> 9132B: %W5<def> = COPY %WZR
     W5:	[0B,148r:0)[9264r,9296r:3)[9664r,9696r:2)[10032r,10064r:1)  0@0B-phi 1@10032r 2@9664r 3@9264r
        -->	[0B,148r:0)[9132r,9296r:3)[9664r,9696r:2)[10032r,10064r:1)  0@0B-phi 1@10032r 2@9664r 3@9132r
     WZR:	EMPTY
        -->	EMPTY
handleMove 9056B -> 9112B: %vreg133<def> = ADDXri %vreg132, 8, 0; GPR64sp:%vreg133 GPR64common:%vreg132
     %vreg133:	[9056r,9200r:0)  0@9056r
        -->	[9112r,9200r:0)  0@9112r
     %vreg132:	[9040r,9056r:0)  0@9040r
        -->	[9040r,9112r:0)  0@9040r
handleMove 9040B -> 9080B: %vreg132<def> = LDRXui <fi#15>, 0; mem:LD8[%parent] GPR64common:%vreg132
     %vreg132:	[9040r,9112r:0)  0@9040r
        -->	[9080r,9112r:0)  0@9080r
handleMove 9648B -> 9528B: %W4<def> = COPY %WZR
     W4:	[0B,152r:0)[9128r,9296r:3)[9648r,9696r:2)[10016r,10064r:1)  0@0B-phi 1@10016r 2@9648r 3@9128r
        -->	[0B,152r:0)[9128r,9296r:3)[9528r,9696r:2)[10016r,10064r:1)  0@0B-phi 1@10016r 2@9528r 3@9128r
     WZR:	EMPTY
        -->	EMPTY
handleMove 9664B -> 9532B: %W5<def> = COPY %WZR
     W5:	[0B,148r:0)[9132r,9296r:3)[9664r,9696r:2)[10032r,10064r:1)  0@0B-phi 1@10032r 2@9664r 3@9132r
        -->	[0B,148r:0)[9132r,9296r:3)[9532r,9696r:2)[10032r,10064r:1)  0@0B-phi 1@10032r 2@9532r 3@9132r
     WZR:	EMPTY
        -->	EMPTY
handleMove 9456B -> 9512B: %vreg142<def> = ADDXri %vreg141, 8, 0; GPR64sp:%vreg142 GPR64common:%vreg141
     %vreg142:	[9456r,9600r:0)  0@9456r
        -->	[9512r,9600r:0)  0@9512r
     %vreg141:	[9440r,9456r:0)  0@9440r
        -->	[9440r,9512r:0)  0@9440r
handleMove 9440B -> 9480B: %vreg141<def> = LDRXui <fi#16>, 0; mem:LD8[%taskgroup79] GPR64common:%vreg141
     %vreg141:	[9440r,9512r:0)  0@9440r
        -->	[9480r,9512r:0)  0@9480r
handleMove 10576B -> 10600B: STRBBui %vreg174, <fi#18>, 0; mem:ST1[%do_wake] GPR32:%vreg174
     %vreg174:	[10560r,10576r:0)  0@10560r
        -->	[10560r,10600r:0)  0@10560r
handleMove 10560B -> 10596B: %vreg174<def> = CSINCWr %WZR, %WZR, 2, %NZCV<imp-use>; GPR32:%vreg174
     %vreg174:	[10560r,10600r:0)  0@10560r
        -->	[10596r,10600r:0)  0@10596r
     WZR:	EMPTY
        -->	EMPTY
     NZCV:	[1296r,1312r:6)[1840r,1856r:5)[3600r,3600d:2)[3776r,3776d:1)[3784r,3784d:0)[5848r,5848d:4)[10544r,10560r:3)  0@3784r 1@3776r 2@3600r 3@10544r 4@5848r 5@1840r 6@1296r
        -->	[1296r,1312r:6)[1840r,1856r:5)[3600r,3600d:2)[3776r,3776d:1)[3784r,3784d:0)[5848r,5848d:4)[10544r,10596r:3)  0@3784r 1@3776r 2@3600r 3@10544r 4@5848r 5@1840r 6@1296r
handleMove 10544B -> 10600B: %vreg173<def,dead> = SUBSWrr %vreg171, %vreg172, %NZCV<imp-def>; GPR32:%vreg173,%vreg171,%vreg172
     %vreg173:	[10544r,10544d:0)  0@10544r
        -->	[10600r,10600d:0)  0@10600r
     %vreg171:	[10512r,10544r:0)  0@10512r
        -->	[10512r,10600r:0)  0@10512r
     %vreg172:	[10528r,10544r:0)  0@10528r
        -->	[10528r,10600r:0)  0@10528r
     NZCV:	[1296r,1312r:6)[1840r,1856r:5)[3600r,3600d:2)[3776r,3776d:1)[3784r,3784d:0)[5848r,5848d:4)[10544r,10608r:3)  0@3784r 1@3776r 2@3600r 3@10544r 4@5848r 5@1840r 6@1296r
        -->	[1296r,1312r:6)[1840r,1856r:5)[3600r,3600d:2)[3776r,3776d:1)[3784r,3784d:0)[5848r,5848d:4)[10600r,10608r:3)  0@3784r 1@3776r 2@3600r 3@10600r 4@5848r 5@1840r 6@1296r
handleMove 10512B -> 10596B: %vreg171<def> = ADDWrr %vreg166, %vreg170; GPR32:%vreg171,%vreg166 GPR32common:%vreg170
     %vreg171:	[10512r,10600r:0)  0@10512r
        -->	[10596r,10600r:0)  0@10596r
     %vreg166:	[10432r,10512r:0)  0@10432r
        -->	[10432r,10596r:0)  0@10432r
     %vreg170:	[10496r,10512r:0)  0@10496r
        -->	[10496r,10596r:0)  0@10496r
handleMove 10496B -> 10600B: %vreg170<def> = ANDWri %vreg169, 0; GPR32common:%vreg170 GPR32:%vreg169
     %vreg170:	[10496r,10608r:0)  0@10496r
        -->	[10600r,10608r:0)  0@10600r
     %vreg169:	[10480r,10496r:0)  0@10480r
        -->	[10480r,10600r:0)  0@10480r
handleMove 10480B -> 10596B: %vreg169<def> = ORNWrr %WZR, %vreg168; GPR32:%vreg169,%vreg168
     %vreg169:	[10480r,10600r:0)  0@10480r
        -->	[10596r,10600r:0)  0@10596r
     WZR:	EMPTY
        -->	EMPTY
     %vreg168:	[10464r,10480r:0)  0@10464r
        -->	[10464r,10596r:0)  0@10464r
handleMove 10528B -> 10600B: %vreg172<def> = LDRWui %vreg165, 0; mem:LD4[%nthreads162] GPR32:%vreg172 GPR64common:%vreg165
     %vreg172:	[10528r,10632r:0)  0@10528r
        -->	[10600r,10632r:0)  0@10600r
     %vreg165:	[10416r,10528r:0)  0@10416r
        -->	[10416r,10600r:0)  0@10416r
handleMove 10432B -> 10596B: %vreg166<def> = LDRWui %vreg165, 332; mem:LD4[%task_running_count] GPR32:%vreg166 GPR64common:%vreg165
     %vreg166:	[10432r,10624r:0)  0@10432r
        -->	[10596r,10624r:0)  0@10596r
     %vreg165:	[10416r,10600r:0)  0@10416r
        -->	[10416r,10600r:0)  0@10416r
handleMove 10416B -> 10456B: %vreg165<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg165
     %vreg165:	[10416r,10600r:0)  0@10416r
        -->	[10456r,10600r:0)  0@10456r
handleMove 9952B -> 9896B: %W0<def> = COPY %WZR
     W0:	[0B,184r:0)[216r,240r:38)[480r,560r:37)[720r,736r:36)[736r,816r:8)[2176r,2192r:19)[2368r,2384r:2)[2384r,2464r:18)[2512r,2560r:17)[3816r,3832r:15)[3952r,3968r:14)[4160r,4176r:16)[4352r,4384r:13)[4384r,4464r:1)[4576r,4592r:12)[4720r,4736r:11)[4864r,4880r:10)[5536r,5552r:35)[5552r,5632r:34)[5888r,5896r:7)[5896r,5952r:33)[5984r,6032r:32)[6512r,6544r:30)[6768r,6816r:31)[7184r,7200r:29)[7328r,7344r:28)[7344r,7424r:6)[7952r,7968r:22)[8080r,8096r:21)[8208r,8224r:20)[8624r,8672r:27)[8880r,8896r:23)[9184r,9296r:5)[9584r,9696r:4)[9952r,10064r:3)[10320r,10336r:26)[10672r,10680r:25)[10864r,10896r:24)[11072r,11104r:9)  0@0B-phi 1@4384r 2@2368r 3@9952r 4@9584r 5@9184r 6@7344r 7@5888r 8@736r 9@11072r 10@4864r 11@4720r 12@4576r 13@4352r 14@3952r 15@3816r 16@4160r 17@2512r 18@2384r 19@2176r 20@8208r 21@8080r 22@7952r 23@8880r 24@10864r 25@10672r 26@10320r 27@8624r 28@7328r 29@7184r 30@6512r 31@6768r 32@5984r 33@5896r 34@5552r 35@5536r 36@720r 37@480r 38@216r
        -->	[0B,184r:0)[216r,240r:38)[480r,560r:37)[720r,736r:36)[736r,816r:8)[2176r,2192r:19)[2368r,2384r:2)[2384r,2464r:18)[2512r,2560r:17)[3816r,3832r:15)[3952r,3968r:14)[4160r,4176r:16)[4352r,4384r:13)[4384r,4464r:1)[4576r,4592r:12)[4720r,4736r:11)[4864r,4880r:10)[5536r,5552r:35)[5552r,5632r:34)[5888r,5896r:7)[5896r,5952r:33)[5984r,6032r:32)[6512r,6544r:30)[6768r,6816r:31)[7184r,7200r:29)[7328r,7344r:28)[7344r,7424r:6)[7952r,7968r:22)[8080r,8096r:21)[8208r,8224r:20)[8624r,8672r:27)[8880r,8896r:23)[9184r,9296r:5)[9584r,9696r:4)[9896r,10064r:3)[10320r,10336r:26)[10672r,10680r:25)[10864r,10896r:24)[11072r,11104r:9)  0@0B-phi 1@4384r 2@2368r 3@9896r 4@9584r 5@9184r 6@7344r 7@5888r 8@736r 9@11072r 10@4864r 11@4720r 12@4576r 13@4352r 14@3952r 15@3816r 16@4160r 17@2512r 18@2384r 19@2176r 20@8208r 21@8080r 22@7952r 23@8880r 24@10864r 25@10672r 26@10320r 27@8624r 28@7328r 29@7184r 30@6512r 31@6768r 32@5984r 33@5896r 34@5552r 35@5536r 36@720r 37@480r 38@216r
     WZR:	EMPTY
        -->	EMPTY
handleMove 10032B -> 9900B: %W5<def> = COPY %WZR
     W5:	[0B,148r:0)[9132r,9296r:3)[9532r,9696r:2)[10032r,10064r:1)  0@0B-phi 1@10032r 2@9532r 3@9132r
        -->	[0B,148r:0)[9132r,9296r:3)[9532r,9696r:2)[9900r,10064r:1)  0@0B-phi 1@9900r 2@9532r 3@9132r
     WZR:	EMPTY
        -->	EMPTY
handleMove 10016B -> 9912B: %W4<def> = MOVi32imm 1
     W4:	[0B,152r:0)[9128r,9296r:3)[9528r,9696r:2)[10016r,10064r:1)  0@0B-phi 1@10016r 2@9528r 3@9128r
        -->	[0B,152r:0)[9128r,9296r:3)[9528r,9696r:2)[9912r,10064r:1)  0@0B-phi 1@9912r 2@9528r 3@9128r
handleMove 9824B -> 9880B: %vreg150<def> = ADDXri %vreg149, 1288, 0; GPR64sp:%vreg150 GPR64common:%vreg149
     %vreg150:	[9824r,9968r:0)  0@9824r
        -->	[9880r,9968r:0)  0@9880r
     %vreg149:	[9808r,9824r:0)  0@9808r
        -->	[9808r,9880r:0)  0@9808r
handleMove 9808B -> 9848B: %vreg149<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg149
     %vreg149:	[9808r,9880r:0)  0@9808r
        -->	[9848r,9880r:0)  0@9848r
handleMove 10864B -> 10888B: %X0<def> = COPY %vreg179; GPR64sp:%vreg179
     W0:	[0B,184r:0)[216r,240r:38)[480r,560r:37)[720r,736r:36)[736r,816r:8)[2176r,2192r:19)[2368r,2384r:2)[2384r,2464r:18)[2512r,2560r:17)[3816r,3832r:15)[3952r,3968r:14)[4160r,4176r:16)[4352r,4384r:13)[4384r,4464r:1)[4576r,4592r:12)[4720r,4736r:11)[4864r,4880r:10)[5536r,5552r:35)[5552r,5632r:34)[5888r,5896r:7)[5896r,5952r:33)[5984r,6032r:32)[6512r,6544r:30)[6768r,6816r:31)[7184r,7200r:29)[7328r,7344r:28)[7344r,7424r:6)[7952r,7968r:22)[8080r,8096r:21)[8208r,8224r:20)[8624r,8672r:27)[8880r,8896r:23)[9184r,9296r:5)[9584r,9696r:4)[9896r,10064r:3)[10320r,10336r:26)[10672r,10680r:25)[10864r,10896r:24)[11072r,11104r:9)  0@0B-phi 1@4384r 2@2368r 3@9896r 4@9584r 5@9184r 6@7344r 7@5888r 8@736r 9@11072r 10@4864r 11@4720r 12@4576r 13@4352r 14@3952r 15@3816r 16@4160r 17@2512r 18@2384r 19@2176r 20@8208r 21@8080r 22@7952r 23@8880r 24@10864r 25@10672r 26@10320r 27@8624r 28@7328r 29@7184r 30@6512r 31@6768r 32@5984r 33@5896r 34@5552r 35@5536r 36@720r 37@480r 38@216r
        -->	[0B,184r:0)[216r,240r:38)[480r,560r:37)[720r,736r:36)[736r,816r:8)[2176r,2192r:19)[2368r,2384r:2)[2384r,2464r:18)[2512r,2560r:17)[3816r,3832r:15)[3952r,3968r:14)[4160r,4176r:16)[4352r,4384r:13)[4384r,4464r:1)[4576r,4592r:12)[4720r,4736r:11)[4864r,4880r:10)[5536r,5552r:35)[5552r,5632r:34)[5888r,5896r:7)[5896r,5952r:33)[5984r,6032r:32)[6512r,6544r:30)[6768r,6816r:31)[7184r,7200r:29)[7328r,7344r:28)[7344r,7424r:6)[7952r,7968r:22)[8080r,8096r:21)[8208r,8224r:20)[8624r,8672r:27)[8880r,8896r:23)[9184r,9296r:5)[9584r,9696r:4)[9896r,10064r:3)[10320r,10336r:26)[10672r,10680r:25)[10888r,10896r:24)[11072r,11104r:9)  0@0B-phi 1@4384r 2@2368r 3@9896r 4@9584r 5@9184r 6@7344r 7@5888r 8@736r 9@11072r 10@4864r 11@4720r 12@4576r 13@4352r 14@3952r 15@3816r 16@4160r 17@2512r 18@2384r 19@2176r 20@8208r 21@8080r 22@7952r 23@8880r 24@10888r 25@10672r 26@10320r 27@8624r 28@7328r 29@7184r 30@6512r 31@6768r 32@5984r 33@5896r 34@5552r 35@5536r 36@720r 37@480r 38@216r
     %vreg179:	[10816r,10864r:0)  0@10816r
        -->	[10816r,10888r:0)  0@10816r
********** GREEDY REGISTER ALLOCATION **********
********** Function: GOMP_task
********** INTERVALS **********
NZCV [1296r,1312r:6)[1840r,1856r:5)[3600r,3600d:2)[3776r,3776d:1)[3784r,3784d:0)[5848r,5848d:4)[10632r,10640r:3)  0@3784r 1@3776r 2@3600r 3@10632r 4@5848r 5@1840r 6@1296r
WSP [192r,192d:166)[240r,240d:165)[256r,256d:164)[272r,272d:163)[304r,304d:162)[464r,464d:161)[480r,480d:160)[496r,496d:159)[512r,512d:158)[544r,544d:157)[704r,704d:156)[736r,736d:155)[752r,752d:154)[768r,768d:153)[800r,800d:152)[2160r,2160d:63)[2192r,2192d:62)[2208r,2208d:61)[2224r,2224d:60)[2256r,2256d:59)[2336r,2336d:58)[2384r,2384d:57)[2400r,2400d:56)[2416r,2416d:55)[2448r,2448d:54)[2480r,2480d:53)[2560r,2560d:52)[2576r,2576d:51)[2592r,2592d:50)[2624r,2624d:49)[3568r,3568d:43)[3616r,3616d:42)[3632r,3632d:41)[3808r,3808d:40)[3832r,3832d:39)[3840r,3840d:38)[3856r,3856d:37)[3888r,3888d:36)[3936r,3936d:35)[3968r,3968d:34)[3984r,3984d:33)[4000r,4000d:32)[4032r,4032d:31)[4064r,4064d:30)[4144r,4144d:48)[4176r,4176d:47)[4192r,4192d:46)[4208r,4208d:45)[4240r,4240d:44)[4320r,4320d:29)[4384r,4384d:28)[4400r,4400d:27)[4416r,4416d:26)[4448r,4448d:25)[4560r,4560d:24)[4592r,4592d:23)[4608r,4608d:22)[4624r,4624d:21)[4656r,4656d:20)[4704r,4704d:19)[4736r,4736d:18)[4752r,4752d:17)[4768r,4768d:16)[4800r,4800d:15)[4848r,4848d:14)[4880r,4880d:13)[4896r,4896d:12)[4912r,4912d:11)[4944r,4944d:10)[4992r,4992d:9)[5008r,5008d:8)[5024r,5024d:7)[5040r,5040d:6)[5072r,5072d:5)[5520r,5520d:151)[5552r,5552d:150)[5568r,5568d:149)[5584r,5584d:148)[5616r,5616d:147)[5872r,5872d:146)[5896r,5896d:145)[5904r,5904d:144)[5912r,5912d:143)[5936r,5936d:142)[5968r,5968d:141)[6032r,6032d:140)[6048r,6048d:139)[6064r,6064d:138)[6096r,6096d:137)[6496r,6496d:133)[6544r,6544d:132)[6560r,6560d:131)[6576r,6576d:130)[6608r,6608d:129)[6752r,6752d:136)[6816r,6816d:135)[6832r,6832d:134)[7168r,7168d:128)[7200r,7200d:127)[7216r,7216d:126)[7232r,7232d:125)[7264r,7264d:124)[7312r,7312d:123)[7344r,7344d:122)[7360r,7360d:121)[7376r,7376d:120)[7408r,7408d:119)[7936r,7936d:78)[7968r,7968d:77)[7984r,7984d:76)[8000r,8000d:75)[8032r,8032d:74)[8064r,8064d:73)[8096r,8096d:72)[8112r,8112d:71)[8128r,8128d:70)[8160r,8160d:69)[8192r,8192d:68)[8224r,8224d:67)[8240r,8240d:66)[8256r,8256d:65)[8288r,8288d:64)[8608r,8608d:118)[8672r,8672d:117)[8688r,8688d:116)[8704r,8704d:115)[8736r,8736d:114)[8864r,8864d:83)[8896r,8896d:82)[8912r,8912d:81)[8928r,8928d:80)[8960r,8960d:79)[9120r,9120d:113)[9296r,9296d:112)[9312r,9312d:111)[9328r,9328d:110)[9360r,9360d:109)[9520r,9520d:108)[9696r,9696d:107)[9712r,9712d:106)[9728r,9728d:105)[9760r,9760d:104)[9888r,9888d:103)[10064r,10064d:102)[10080r,10080d:101)[10096r,10096d:100)[10128r,10128d:99)[10304r,10304d:98)[10336r,10336d:97)[10352r,10352d:96)[10368r,10368d:95)[10400r,10400d:94)[10664r,10664d:93)[10680r,10680d:92)[10688r,10688d:91)[10696r,10696d:90)[10720r,10720d:89)[10832r,10832d:88)[10896r,10896d:87)[10912r,10912d:86)[10928r,10928d:85)[10960r,10960d:84)[11040r,11040d:4)[11104r,11104d:3)[11120r,11120d:2)[11136r,11136d:1)[11168r,11168d:0)  0@11168r 1@11136r 2@11120r 3@11104r 4@11040r 5@5072r 6@5040r 7@5024r 8@5008r 9@4992r 10@4944r 11@4912r 12@4896r 13@4880r 14@4848r 15@4800r 16@4768r 17@4752r 18@4736r 19@4704r 20@4656r 21@4624r 22@4608r 23@4592r 24@4560r 25@4448r 26@4416r 27@4400r 28@4384r 29@4320r 30@4064r 31@4032r 32@4000r 33@3984r 34@3968r 35@3936r 36@3888r 37@3856r 38@3840r 39@3832r 40@3808r 41@3632r 42@3616r 43@3568r 44@4240r 45@4208r 46@4192r 47@4176r 48@4144r 49@2624r 50@2592r 51@2576r 52@2560r 53@2480r 54@2448r 55@2416r 56@2400r 57@2384r 58@2336r 59@2256r 60@2224r 61@2208r 62@2192r 63@2160r 64@8288r 65@8256r 66@8240r 67@8224r 68@8192r 69@8160r 70@8128r 71@8112r 72@8096r 73@8064r 74@8032r 75@8000r 76@7984r 77@7968r 78@7936r 79@8960r 80@8928r 81@8912r 82@8896r 83@8864r 84@10960r 85@10928r 86@10912r 87@10896r 88@10832r 89@10720r 90@10696r 91@10688r 92@10680r 93@10664r 94@10400r 95@10368r 96@10352r 97@10336r 98@10304r 99@10128r 100@10096r 101@10080r 102@10064r 103@9888r 104@9760r 105@9728r 106@9712r 107@9696r 108@9520r 109@9360r 110@9328r 111@9312r 112@9296r 113@9120r 114@8736r 115@8704r 116@8688r 117@8672r 118@8608r 119@7408r 120@7376r 121@7360r 122@7344r 123@7312r 124@7264r 125@7232r 126@7216r 127@7200r 128@7168r 129@6608r 130@6576r 131@6560r 132@6544r 133@6496r 134@6832r 135@6816r 136@6752r 137@6096r 138@6064r 139@6048r 140@6032r 141@5968r 142@5936r 143@5912r 144@5904r 145@5896r 146@5872r 147@5616r 148@5584r 149@5568r 150@5552r 151@5520r 152@800r 153@768r 154@752r 155@736r 156@704r 157@544r 158@512r 159@496r 160@480r 161@464r 162@304r 163@272r 164@256r 165@240r 166@192r
WZR EMPTY
W0 [0B,184r:0)[216r,240r:38)[480r,560r:37)[720r,736r:36)[736r,816r:8)[2176r,2192r:19)[2368r,2384r:2)[2384r,2464r:18)[2512r,2560r:17)[3816r,3832r:15)[3952r,3968r:14)[4160r,4176r:16)[4352r,4384r:13)[4384r,4464r:1)[4576r,4592r:12)[4720r,4736r:11)[4864r,4880r:10)[5536r,5552r:35)[5552r,5632r:34)[5888r,5896r:7)[5896r,5952r:33)[5984r,6032r:32)[6512r,6544r:30)[6768r,6816r:31)[7184r,7200r:29)[7328r,7344r:28)[7344r,7424r:6)[7952r,7968r:22)[8080r,8096r:21)[8208r,8224r:20)[8624r,8672r:27)[8880r,8896r:23)[9184r,9296r:5)[9584r,9696r:4)[9896r,10064r:3)[10320r,10336r:26)[10672r,10680r:25)[10888r,10896r:24)[11072r,11104r:9)  0@0B-phi 1@4384r 2@2368r 3@9896r 4@9584r 5@9184r 6@7344r 7@5888r 8@736r 9@11072r 10@4864r 11@4720r 12@4576r 13@4352r 14@3952r 15@3816r 16@4160r 17@2512r 18@2384r 19@2176r 20@8208r 21@8080r 22@7952r 23@8880r 24@10888r 25@10672r 26@10320r 27@8624r 28@7328r 29@7184r 30@6512r 31@6768r 32@5984r 33@5896r 34@5552r 35@5536r 36@720r 37@480r 38@216r
W1 [0B,176r:0)[224r,240r:13)[2528r,2560r:5)[3824r,3832r:4)[4328r,4384r:1)[6000r,6032r:12)[6528r,6544r:10)[6784r,6816r:11)[8640r,8672r:9)[9200r,9296r:8)[9600r,9696r:7)[9968r,10064r:6)[10880r,10896r:2)[11088r,11104r:3)  0@0B-phi 1@4328r 2@10880r 3@11088r 4@3824r 5@2528r 6@9968r 7@9600r 8@9200r 9@8640r 10@6528r 11@6784r 12@6000r 13@224r
W2 [0B,168r:0)[2544r,2560r:1)[6016r,6032r:7)[6800r,6816r:6)[8656r,8672r:5)[9216r,9296r:4)[9616r,9696r:3)[9984r,10064r:2)  0@0B-phi 1@2544r 2@9984r 3@9616r 4@9216r 5@8656r 6@6800r 7@6016r
W3 [0B,160r:0)[9232r,9296r:3)[9632r,9696r:2)[10000r,10064r:1)  0@0B-phi 1@10000r 2@9632r 3@9232r
W4 [0B,152r:0)[9128r,9296r:3)[9528r,9696r:2)[9912r,10064r:1)  0@0B-phi 1@9912r 2@9528r 3@9128r
W5 [0B,148r:0)[9132r,9296r:3)[9532r,9696r:2)[9900r,10064r:1)  0@0B-phi 1@9900r 2@9532r 3@9132r
W6 [0B,32r:0)[9280r,9296r:3)[9680r,9696r:2)[10048r,10064r:1)  0@0B-phi 1@10048r 2@9680r 3@9280r
W7 [0B,16r:0)  0@0B-phi
%vreg4 [184r,320r:0)  0@184r
%vreg5 [176r,336r:0)  0@176r
%vreg6 [168r,352r:0)  0@168r
%vreg7 [160r,368r:0)  0@160r
%vreg8 [152r,384r:0)  0@152r
%vreg9 [148r,200r:0)  0@148r
%vreg10 [32r,416r:0)  0@32r
%vreg11 [16r,432r:0)  0@16r
%vreg12 [144r,448r:0)  0@144r
%vreg13 [200r,400r:0)  0@200r
%vreg15 [560r,592r:0)  0@560r
%vreg16 [592r,624r:0)  0@592r
%vreg17 [672r,688r:0)  0@672r
%vreg18 [688r,720r:0)  0@688r
%vreg19 [816r,832r:0)  0@816r
%vreg20 [880r,896r:0)  0@880r
%vreg21 [896r,912r:0)  0@896r
%vreg22 [912r,928r:0)  0@912r
%vreg23 [976r,992r:0)  0@976r
%vreg24 [992r,1008r:0)  0@992r
%vreg25 [1008r,1024r:0)  0@1008r
%vreg26 [1024r,1040r:0)  0@1024r
%vreg27 [1120r,1136r:0)  0@1120r
%vreg28 [1248r,1296r:0)  0@1248r
%vreg29 [1264r,1280r:0)  0@1264r
%vreg30 [1280r,1296r:0)  0@1280r
%vreg31 [1296r,1296d:0)  0@1296r
%vreg32 [1360r,1376r:0)  0@1360r
%vreg33 [1376r,1392r:0)  0@1376r
%vreg35 [1472r,1488r:0)  0@1472r
%vreg36 [1536r,1552r:0)  0@1536r
%vreg37 [1600r,1616r:0)  0@1600r
%vreg38 [1616r,1632r:0)  0@1616r
%vreg39 [1680r,1696r:0)  0@1680r
%vreg40 [1696r,1712r:0)  0@1696r
%vreg41 [1712r,1728r:0)  0@1712r
%vreg42 [1728r,1744r:0)  0@1728r
%vreg43 [1792r,1824r:0)  0@1792r
%vreg44 [1808r,1840r:0)  0@1808r
%vreg45 [1824r,1840r:0)  0@1824r
%vreg46 [1840r,1840d:0)  0@1840r
%vreg47 [5120r,5136r:0)  0@5120r
%vreg48 [5136r,5168r:0)  0@5136r
%vreg49 [5168r,5236r:0)  0@5168r
%vreg51 [5232r,5248r:0)  0@5232r
%vreg52 [5296r,5312r:0)  0@5296r
%vreg53 [5312r,5360r:0)  0@5312r
%vreg55 [5328r,5360r:0)  0@5328r
%vreg56 [5360r,5376r:0)  0@5360r
%vreg57 [5424r,5480r:0)  0@5424r
%vreg58 [5440r,5480r:0)  0@5440r
%vreg59 [5480r,5488r:0)  0@5480r
%vreg60 [5472r,5488r:0)  0@5472r
%vreg61 [5488r,5504r:0)  0@5488r
%vreg62 [5504r,5536r:0)  0@5504r
%vreg63 [5632r,5824r:0)  0@5632r
%vreg64 [5664r,5824r:0)  0@5664r
%vreg65 [5824r,5832r:0)  0@5824r
%vreg66 [5696r,5848r:0)  0@5696r
%vreg67 [5832r,5840r:0)  0@5832r
%vreg68 [5840r,5856r:0)  0@5840r
%vreg69 [5848r,5856r:0)  0@5848r
%vreg70 [5856r,5864r:0)  0@5856r
%vreg71 [5816r,5984r:0)  0@5816r
%vreg72 [5808r,6000r:0)  0@5808r
%vreg74 [5952r,6016r:0)  0@5952r
%vreg75 [6112r,6144r:0)  0@6112r
%vreg76 [6128r,6144r:0)  0@6128r
%vreg77 [6160r,6192r:0)  0@6160r
%vreg78 [6176r,6192r:0)  0@6176r
%vreg79 [6208r,6224r:0)  0@6208r
%vreg80 [6224r,6256r:0)  0@6224r
%vreg81 [6240r,6272r:0)  0@6240r
%vreg82 [6256r,6272r:0)  0@6256r
%vreg83 [6288r,6320r:0)  0@6288r
%vreg84 [6304r,6320r:0)  0@6304r
%vreg85 [6336r,6368r:0)  0@6336r
%vreg86 [6352r,6368r:0)  0@6352r
%vreg87 [6384r,6400r:0)  0@6384r
%vreg88 [6704r,6768r:0)  0@6704r
%vreg89 [6720r,6784r:0)  0@6720r
%vreg90 [6736r,6800r:0)  0@6736r
%vreg91 [6448r,6544r:0)  0@6448r
%vreg92 [6464r,6512r:0)  0@6464r
%vreg93 [6480r,6528r:0)  0@6480r
%vreg94 [6624r,6656r:0)  0@6624r
%vreg95 [6640r,6656r:0)  0@6640r
%vreg96 [6880r,6912r:0)  0@6880r
%vreg97 [6896r,6912r:0)  0@6896r
%vreg98 [6928r,6960r:0)  0@6928r
%vreg99 [6944r,6960r:0)  0@6944r
%vreg100 [6976r,7008r:0)  0@6976r
%vreg101 [6992r,7008r:0)  0@6992r
%vreg102 [7024r,7056r:0)  0@7024r
%vreg103 [7040r,7056r:0)  0@7040r
%vreg104 [7072r,7112r:0)  0@7072r
%vreg105 [7112r,7120r:0)  0@7112r
%vreg106 [7104r,7120r:0)  0@7104r
%vreg107 [7136r,7152r:0)  0@7136r
%vreg108 [7152r,7184r:0)  0@7152r
%vreg109 [7280r,7296r:0)  0@7280r
%vreg110 [7296r,7328r:0)  0@7296r
%vreg111 [7424r,7440r:0)  0@7424r
%vreg113 [7488r,7552r:0)  0@7488r
%vreg116 [7600r,7616r:0)  0@7600r
%vreg117 [7616r,7680r:0)  0@7616r
%vreg119 [7728r,7744r:0)  0@7728r
%vreg120 [7744r,7760r:0)  0@7744r
%vreg122 [8336r,8352r:0)  0@8336r
%vreg123 [8400r,8448r:0)  0@8400r
%vreg124 [8416r,8432r:0)  0@8416r
%vreg125 [8432r,8448r:0)  0@8432r
%vreg126 [8496r,8512r:0)  0@8496r
%vreg127 [8560r,8624r:0)  0@8560r
%vreg128 [8576r,8640r:0)  0@8576r
%vreg129 [8592r,8656r:0)  0@8592r
%vreg130 [8752r,8768r:0)  0@8752r
%vreg131 [8768r,8784r:0)  0@8768r
%vreg132 [9080r,9112r:0)  0@9080r
%vreg133 [9112r,9200r:0)  0@9112r
%vreg134 [9072r,9216r:0)  0@9072r
%vreg135 [9088r,9232r:0)  0@9088r
%vreg136 [9104r,9136r:0)  0@9104r
%vreg137 [9136r,9280r:0)  0@9136r
%vreg140 [9376r,9392r:0)  0@9376r
%vreg141 [9480r,9512r:0)  0@9480r
%vreg142 [9512r,9600r:0)  0@9512r
%vreg143 [9472r,9616r:0)  0@9472r
%vreg144 [9488r,9632r:0)  0@9488r
%vreg145 [9504r,9536r:0)  0@9504r
%vreg146 [9536r,9680r:0)  0@9536r
%vreg149 [9848r,9880r:0)  0@9848r
%vreg150 [9880r,9968r:0)  0@9880r
%vreg151 [9840r,9984r:0)  0@9840r
%vreg152 [9856r,10000r:0)  0@9856r
%vreg153 [9872r,9904r:0)  0@9872r
%vreg154 [9904r,10048r:0)  0@9904r
%vreg157 [10144r,10192r:0)  0@10144r
%vreg158 [10160r,10176r:0)  0@10160r
%vreg159 [10176r,10192r:0)  0@10176r
%vreg160 [10208r,10256r:0)  0@10208r
%vreg161 [10224r,10240r:0)  0@10224r
%vreg162 [10240r,10256r:0)  0@10240r
%vreg163 [10272r,10288r:0)  0@10272r
%vreg164 [10288r,10320r:0)  0@10288r
%vreg165 [10456r,10600r:0)  0@10456r
%vreg166 [10596r,10624r:0)  0@10596r
%vreg167 [10448r,10464r:0)  0@10448r
%vreg168 [10464r,10608r:0)  0@10464r
%vreg169 [10608r,10616r:0)  0@10608r
%vreg170 [10616r,10624r:0)  0@10616r
%vreg171 [10624r,10632r:0)  0@10624r
%vreg172 [10600r,10632r:0)  0@10600r
%vreg173 [10632r,10632d:0)  0@10632r
%vreg174 [10640r,10648r:0)  0@10640r
%vreg175 [10592r,10656r:0)  0@10592r
%vreg176 [10656r,10672r:0)  0@10656r
%vreg177 [10736r,10752r:0)  0@10736r
%vreg178 [10800r,10816r:0)  0@10800r
%vreg179 [10816r,10888r:0)  0@10816r
%vreg181 [8832r,8848r:0)  0@8832r
%vreg182 [8848r,8880r:0)  0@8848r
%vreg183 [7904r,7920r:0)  0@7904r
%vreg184 [7920r,7952r:0)  0@7920r
%vreg185 [8048r,8080r:0)  0@8048r
%vreg186 [8176r,8208r:0)  0@8176r
%vreg187 [1904r,1920r:0)  0@1904r
%vreg188 [1968r,1984r:0)  0@1968r
%vreg189 [1984r,2000r:0)  0@1984r
%vreg190 [2048r,2064r:0)  0@2048r
%vreg191 [2064r,2080r:0)  0@2064r
%vreg192 [2080r,2096r:0)  0@2080r
%vreg193 [2144r,2176r:0)  0@2144r
%vreg194 [2304r,2320r:0)  0@2304r
%vreg195 [2320r,2528r:0)  0@2320r
%vreg197 [2464r,2544r:0)  0@2464r
%vreg199 [2676r,2680r:0)  0@2676r
%vreg200 [2672r,2688r:0)  0@2672r
%vreg201 [2688r,2704r:0)  0@2688r
%vreg203 [2752r,2768r:0)  0@2752r
%vreg204 [2768r,2784r:0)  0@2768r
%vreg205 [2784r,2800r:0)  0@2784r
%vreg206 [2800r,2864r:0)  0@2800r
%vreg208 [2912r,2928r:0)  0@2912r
%vreg210 [3096r,3104r:0)  0@3096r
%vreg211 [3056r,3112r:0)  0@3056r
%vreg212 [3088r,3120r:0)  0@3088r
%vreg213 [3120r,3128r:0)  0@3120r
%vreg214 [3168r,3184r:0)  0@3168r
%vreg215 [3184r,3200r:0)  0@3184r
%vreg216 [3200r,3252r:0)  0@3200r
%vreg217 [3252r,3256r:0)  0@3252r
%vreg218 [3248r,3264r:0)  0@3248r
%vreg219 [3264r,3280r:0)  0@3264r
%vreg220 [3280r,3296r:0)  0@3280r
%vreg221 [3344r,3376r:0)  0@3344r
%vreg222 [3360r,3376r:0)  0@3360r
%vreg223 [3392r,3408r:0)  0@3392r
%vreg224 [4112r,4176r:0)  0@4112r
%vreg225 [4128r,4160r:0)  0@4128r
%vreg226 [3456r,3488r:0)  0@3456r
%vreg227 [3472r,3488r:0)  0@3472r
%vreg228 [3488r,3536r:0)  0@3488r
%vreg229 [3448r,3520r:0)  0@3448r
%vreg230 [3536r,3552r:0)  0@3536r
%vreg231 [3552r,3600r:0)  0@3552r
%vreg232 [3584r,3600r:0)  0@3584r
%vreg233 [3600r,3768r:0)  0@3600r
%vreg234 [3648r,3784r:0)  0@3648r
%vreg235 [3768r,3776r:0)  0@3768r
%vreg236 [3776r,3792r:0)  0@3776r
%vreg237 [3784r,3792r:0)  0@3784r
%vreg238 [3792r,3816r:0)  0@3792r
%vreg239 [3744r,3832r:0)  0@3744r
%vreg240 [3760r,3824r:0)  0@3760r
%vreg241 [3904r,3968r:0)  0@3904r
%vreg242 [3920r,3952r:0)  0@3920r
%vreg243 [4048r,4064r:0)  0@4048r
%vreg244 [4288r,4304r:0)  0@4288r
%vreg245 [4304r,4352r:0)  0@4304r
%vreg247 [4464r,4480r:0)  0@4464r
%vreg248 [4528r,4544r:0)  0@4528r
%vreg249 [4544r,4576r:0)  0@4544r
%vreg250 [4672r,4688r:0)  0@4672r
%vreg251 [4688r,4720r:0)  0@4688r
%vreg252 [4816r,4832r:0)  0@4816r
%vreg253 [4832r,4864r:0)  0@4832r
%vreg255 [2816r,2896B:0)[2928r,2992B:1)[2992B,3096r:2)  0@2816r 1@2928r 2@2992B-phi
%vreg256 [7536r,7584B:0)[7664r,7712B:1)[7760r,7824B:2)[7824B,7856r:3)  0@7536r 1@7664r 2@7760r 3@7824B-phi
RegMasks: 240r 480r 736r 2192r 2384r 2560r 3832r 3968r 4176r 4384r 4592r 4736r 4880r 5008r 5552r 5896r 6032r 6544r 6816r 7200r 7344r 7968r 8096r 8224r 8672r 8896r 9296r 9696r 10064r 10336r 10680r 10896r 11104r
********** MACHINEINSTRS **********
# Machine code for function GOMP_task: Post SSA
Frame Objects:
  fi#-1: size=4, align=16, fixed, at location [SP]
  fi#0: size=8, align=8, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=8, align=8, at location [SP]
  fi#3: size=8, align=8, at location [SP]
  fi#4: size=8, align=8, at location [SP]
  fi#5: size=1, align=1, at location [SP]
  fi#6: size=4, align=4, at location [SP]
  fi#7: size=8, align=8, at location [SP]
  fi#8: size=4, align=4, at location [SP]
  fi#9: size=8, align=8, at location [SP]
  fi#10: size=8, align=8, at location [SP]
  fi#11: size=208, align=8, at location [SP]
  fi#12: size=8, align=8, at location [SP]
  fi#13: size=8, align=8, at location [SP]
  fi#14: size=8, align=8, at location [SP]
  fi#15: size=8, align=8, at location [SP]
  fi#16: size=8, align=8, at location [SP]
  fi#17: size=8, align=8, at location [SP]
  fi#18: size=1, align=1, at location [SP]
  fi#19: size=8, align=8, at location [SP]
  fi#20: variable sized, align=1, at location [SP]
Function Live Ins: %X0 in %vreg4, %X1 in %vreg5, %X2 in %vreg6, %X3 in %vreg7, %X4 in %vreg8, %W5 in %vreg9, %W6 in %vreg10, %X7 in %vreg11

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %X1 %X2 %X3 %X4 %W5 %W6 %X7
16B		%vreg11<def> = COPY %X7; GPR64:%vreg11
32B		%vreg10<def> = COPY %W6; GPR32:%vreg10
144B		%vreg12<def> = LDRWui <fi#-1>, 0; mem:LD4[FixedStack-1] GPR32:%vreg12
148B		%vreg9<def> = COPY %W5; GPR32:%vreg9
152B		%vreg8<def> = COPY %X4; GPR64:%vreg8
160B		%vreg7<def> = COPY %X3; GPR64:%vreg7
168B		%vreg6<def> = COPY %X2; GPR64:%vreg6
176B		%vreg5<def> = COPY %X1; GPR64:%vreg5
184B		%vreg4<def> = COPY %X0; GPR64:%vreg4
192B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
200B		%vreg13<def> = ANDWri %vreg9, 0; GPR32common:%vreg13 GPR32:%vreg9
216B		%X0<def> = COPY %XZR
224B		%X1<def> = COPY %XZR
240B		BL <ga:@check_migrate>, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %SP<imp-def>, ...
256B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
272B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
288B		STACKMAP 0, 0, %vreg8, %vreg7, %vreg6, %vreg5, %vreg11, %vreg10, %vreg4, %vreg13, %vreg12, ...; GPR64:%vreg8,%vreg7,%vreg6,%vreg5,%vreg11,%vreg4 GPR32:%vreg10,%vreg12 GPR32common:%vreg13
304B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
320B		STRXui %vreg4, <fi#0>, 0; mem:ST8[%fn.addr] GPR64:%vreg4
336B		STRXui %vreg5, <fi#1>, 0; mem:ST8[%data.addr] GPR64:%vreg5
352B		STRXui %vreg6, <fi#2>, 0; mem:ST8[%cpyfn.addr] GPR64:%vreg6
368B		STRXui %vreg7, <fi#3>, 0; mem:ST8[%arg_size.addr] GPR64:%vreg7
384B		STRXui %vreg8, <fi#4>, 0; mem:ST8[%arg_align.addr] GPR64:%vreg8
400B		STRBBui %vreg13, <fi#5>, 0; mem:ST1[%if_clause.addr] GPR32common:%vreg13
416B		STRWui %vreg10, <fi#6>, 0; mem:ST4[%flags.addr] GPR32:%vreg10
432B		STRXui %vreg11, <fi#7>, 0; mem:ST8[%depend.addr] GPR64:%vreg11
448B		STRWui %vreg12, <fi#8>, 0; mem:ST4[%priority.addr] GPR32:%vreg12
464B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
480B		BL <ga:@gomp_thread>, <regmask>, %SP<imp-use>, %SP<imp-def>, %X0<imp-def>, ...
496B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
512B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
528B		STACKMAP 1, 0, 0, <fi#13>, 0, 0, <fi#17>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#19>, 0, 0, <fi#18>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#5>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#12>, 0, 0, <fi#11>, 0, 0, <fi#14>, 0, 0, <fi#16>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack13] LD8[FixedStack17] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack2] LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack19] LD8[FixedStack18](align=1) LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack5](align=1) LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack12] LD8[FixedStack11] LD8[FixedStack14] LD8[FixedStack16] LD8[FixedStack10] LD8[FixedStack9]
544B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
560B		%vreg15<def> = COPY %X0; GPR64common:%vreg15
576B		STRXui %vreg15, <fi#9>, 0; mem:ST8[%thr] GPR64common:%vreg15
592B		%vreg16<def> = LDRXui %vreg15, 2; mem:LD8[%team1] GPR64:%vreg16 GPR64common:%vreg15
608B		STRXui %vreg16, <fi#10>, 0; mem:ST8[%team] GPR64:%vreg16
624B		CBZX %vreg16, <BB#5>; GPR64:%vreg16
640B		B <BB#1>
	    Successors according to CFG: BB#1 BB#5

656B	BB#1: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#0
672B		%vreg17<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg17
688B		%vreg18<def> = ADDXri %vreg17, 128, 0; GPR64sp:%vreg18 GPR64common:%vreg17
704B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
720B		%X0<def> = COPY %vreg18; GPR64sp:%vreg18
736B		BL <ga:@gomp_team_barrier_cancelled>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>, ...
752B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
768B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
784B		STACKMAP 2, 0, 0, <fi#13>, 0, 0, <fi#17>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#19>, 0, 0, <fi#18>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#5>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#12>, 0, 0, <fi#11>, 0, 0, <fi#14>, 0, 0, <fi#16>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack13] LD8[FixedStack17] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack2] LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack19] LD8[FixedStack18](align=1) LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack5](align=1) LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack12] LD8[FixedStack11] LD8[FixedStack14] LD8[FixedStack16] LD8[FixedStack10] LD8[FixedStack9]
800B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
816B		%vreg19<def> = COPY %W0; GPR32:%vreg19
832B		TBNZW %vreg19, 0, <BB#4>; GPR32:%vreg19
848B		B <BB#2>
	    Successors according to CFG: BB#4 BB#2

864B	BB#2: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#1
880B		%vreg20<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg20
896B		%vreg21<def> = LDRXui %vreg20, 10; mem:LD8[%task] GPR64common:%vreg21,%vreg20
912B		%vreg22<def> = LDRXui %vreg21, 5; mem:LD8[%taskgroup] GPR64:%vreg22 GPR64common:%vreg21
928B		CBZX %vreg22, <BB#5>; GPR64:%vreg22
944B		B <BB#3>
	    Successors according to CFG: BB#3 BB#5

960B	BB#3: derived from LLVM BB %land.lhs.true.4
	    Predecessors according to CFG: BB#2
976B		%vreg23<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg23
992B		%vreg24<def> = LDRXui %vreg23, 10; mem:LD8[%task5] GPR64common:%vreg24,%vreg23
1008B		%vreg25<def> = LDRXui %vreg24, 5; mem:LD8[%taskgroup6] GPR64common:%vreg25,%vreg24
1024B		%vreg26<def> = LDRBBui %vreg25, 41; mem:LD1[%cancelled] GPR32:%vreg26 GPR64common:%vreg25
1040B		TBZW %vreg26, 0, <BB#5>; GPR32:%vreg26
1056B		B <BB#4>
	    Successors according to CFG: BB#4 BB#5

1072B	BB#4: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#1 BB#3
1088B		B <BB#52>
	    Successors according to CFG: BB#52

1104B	BB#5: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#2 BB#3
1120B		%vreg27<def> = LDRBBui <fi#6>, 0; mem:LD1[%flags.addr](align=4) GPR32:%vreg27
1136B		TBNZW %vreg27, 4, <BB#7>; GPR32:%vreg27
1152B		B <BB#6>
	    Successors according to CFG: BB#6 BB#7

1168B	BB#6: derived from LLVM BB %if.then.8
	    Predecessors according to CFG: BB#5
1200B		STRWui %WZR, <fi#8>, 0; mem:ST4[%priority.addr]
1216B		B <BB#10>
	    Successors according to CFG: BB#10

1232B	BB#7: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#5
1248B		%vreg28<def> = LDRWui <fi#8>, 0; mem:LD4[%priority.addr] GPR32:%vreg28
1264B		%vreg29<def> = ADRP <ga:@gomp_max_task_priority_var>[TF=1]; GPR64common:%vreg29
1280B		%vreg30<def> = LDRWui %vreg29, <ga:@gomp_max_task_priority_var>[TF=34]; mem:LD4[@gomp_max_task_priority_var] GPR32:%vreg30 GPR64common:%vreg29
1296B		%vreg31<def,dead> = SUBSWrr %vreg28, %vreg30, %NZCV<imp-def>; GPR32:%vreg31,%vreg28,%vreg30
1312B		Bcc 13, <BB#9>, %NZCV<imp-use>
1328B		B <BB#8>
	    Successors according to CFG: BB#8 BB#9

1344B	BB#8: derived from LLVM BB %if.then.10
	    Predecessors according to CFG: BB#7
1360B		%vreg32<def> = ADRP <ga:@gomp_max_task_priority_var>[TF=1]; GPR64common:%vreg32
1376B		%vreg33<def> = LDRWui %vreg32, <ga:@gomp_max_task_priority_var>[TF=34]; mem:LD4[@gomp_max_task_priority_var] GPR32:%vreg33 GPR64common:%vreg32
1392B		STRWui %vreg33, <fi#8>, 0; mem:ST4[%priority.addr] GPR32:%vreg33
1408B		B <BB#9>
	    Successors according to CFG: BB#9

1424B	BB#9: derived from LLVM BB %if.end.11
	    Predecessors according to CFG: BB#7 BB#8
1440B		B <BB#10>
	    Successors according to CFG: BB#10

1456B	BB#10: derived from LLVM BB %if.end.12
	    Predecessors according to CFG: BB#9 BB#6
1472B		%vreg35<def> = LDRBBui <fi#5>, 0; mem:LD1[%if_clause.addr] GPR32:%vreg35
1488B		TBZW %vreg35, 0, <BB#15>; GPR32:%vreg35
1504B		B <BB#11>
	    Successors according to CFG: BB#11 BB#15

1520B	BB#11: derived from LLVM BB %lor.lhs.false.14
	    Predecessors according to CFG: BB#10
1536B		%vreg36<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64:%vreg36
1552B		CBZX %vreg36, <BB#15>; GPR64:%vreg36
1568B		B <BB#12>
	    Successors according to CFG: BB#15 BB#12

1584B	BB#12: derived from LLVM BB %lor.lhs.false.16
	    Predecessors according to CFG: BB#11
1600B		%vreg37<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg37
1616B		%vreg38<def> = LDRXui %vreg37, 10; mem:LD8[%task17] GPR64:%vreg38 GPR64common:%vreg37
1632B		CBZX %vreg38, <BB#14>; GPR64:%vreg38
1648B		B <BB#13>
	    Successors according to CFG: BB#13 BB#14

1664B	BB#13: derived from LLVM BB %land.lhs.true.19
	    Predecessors according to CFG: BB#12
1680B		%vreg39<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg39
1696B		%vreg40<def> = LDRXui %vreg39, 10; mem:LD8[%task20] GPR64common:%vreg40,%vreg39
1712B		%vreg41<def> = LDRBBui %vreg40, 205; mem:LD1[%final_task] GPR32:%vreg41 GPR64common:%vreg40
1728B		%vreg42<def> = ANDWri %vreg41, 0; GPR32common:%vreg42 GPR32:%vreg41
1744B		TBNZW %vreg42, 0, <BB#15>; GPR32common:%vreg42
1760B		B <BB#14>
	    Successors according to CFG: BB#15 BB#14

1776B	BB#14: derived from LLVM BB %lor.lhs.false.22
	    Predecessors according to CFG: BB#12 BB#13
1792B		%vreg43<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg43
1808B		%vreg44<def> = LDRWui %vreg43, 330; mem:LD4[%task_count] GPR32:%vreg44 GPR64common:%vreg43
1824B		%vreg45<def> = LDRWui %vreg43, 0; mem:LD4[%nthreads] GPR32:%vreg45 GPR64common:%vreg43
1840B		%vreg46<def,dead> = SUBSWrs %vreg44, %vreg45, 6, %NZCV<imp-def>; GPR32:%vreg46,%vreg44,%vreg45
1856B		Bcc 9, <BB#30>, %NZCV<imp-use>
1872B		B <BB#15>
	    Successors according to CFG: BB#15 BB#30

1888B	BB#15: derived from LLVM BB %if.then.24
	    Predecessors according to CFG: BB#10 BB#11 BB#13 BB#14
1904B		%vreg187<def> = LDRBBui <fi#6>, 0; mem:LD1[%flags.addr](align=4) GPR32:%vreg187
1920B		TBZW %vreg187, 3, <BB#19>; GPR32:%vreg187
1936B		B <BB#16>
	    Successors according to CFG: BB#16 BB#19

1952B	BB#16: derived from LLVM BB %land.lhs.true.28
	    Predecessors according to CFG: BB#15
1968B		%vreg188<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg188
1984B		%vreg189<def> = LDRXui %vreg188, 10; mem:LD8[%task29] GPR64:%vreg189 GPR64common:%vreg188
2000B		CBZX %vreg189, <BB#19>; GPR64:%vreg189
2016B		B <BB#17>
	    Successors according to CFG: BB#17 BB#19

2032B	BB#17: derived from LLVM BB %land.lhs.true.31
	    Predecessors according to CFG: BB#16
2048B		%vreg190<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg190
2064B		%vreg191<def> = LDRXui %vreg190, 10; mem:LD8[%task32] GPR64common:%vreg191,%vreg190
2080B		%vreg192<def> = LDRXui %vreg191, 7; mem:LD8[%depend_hash] GPR64:%vreg192 GPR64common:%vreg191
2096B		CBZX %vreg192, <BB#19>; GPR64:%vreg192
2112B		B <BB#18>
	    Successors according to CFG: BB#18 BB#19

2128B	BB#18: derived from LLVM BB %if.then.34
	    Predecessors according to CFG: BB#17
2144B		%vreg193<def> = LDRXui <fi#7>, 0; mem:LD8[%depend.addr] GPR64:%vreg193
2160B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2176B		%X0<def> = COPY %vreg193; GPR64:%vreg193
2192B		BL <ga:@gomp_task_maybe_wait_for_dependencies>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...
2208B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2224B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2240B		STACKMAP 3, 0, 0, <fi#13>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#8>, 0, 0, <fi#12>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack13] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack2] LD8[FixedStack1] LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack8](align=4) LD8[FixedStack12] LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack9]
2256B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2272B		B <BB#19>
	    Successors according to CFG: BB#19

2288B	BB#19: derived from LLVM BB %if.end.35
	    Predecessors according to CFG: BB#15 BB#16 BB#17 BB#18
2304B		%vreg194<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg194
2320B		%vreg195<def> = LDRXui %vreg194, 10; mem:LD8[%task36] GPR64:%vreg195 GPR64common:%vreg194
2336B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2368B		%W0<def> = COPY %WZR
2384B		BL <ga:@gomp_icv>, <regmask>, %SP<imp-use>, %W0<imp-use>, %SP<imp-def>, %X0<imp-def>, ...
2400B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2416B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2432B		STACKMAP 4, 0, 0, <fi#13>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#8>, 0, 0, <fi#12>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, %vreg195, ...; mem:LD8[FixedStack13] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack2] LD8[FixedStack1] LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack8](align=4) LD8[FixedStack12] LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack9] GPR64:%vreg195
2448B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2464B		%vreg197<def> = COPY %X0; GPR64all:%vreg197
2480B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2512B		%X0<def> = ADDXri <fi#11>, 0, 0
2528B		%X1<def> = COPY %vreg195; GPR64:%vreg195
2544B		%X2<def> = COPY %vreg197; GPR64all:%vreg197
2560B		BL <ga:@gomp_init_task>, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %X2<imp-use>, %SP<imp-def>, ...
2576B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2592B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2608B		STACKMAP 5, 0, 0, <fi#13>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#8>, 0, 0, <fi#12>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack13] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack2] LD8[FixedStack1] LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack8](align=4) LD8[FixedStack12] LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack9]
2624B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2672B		%vreg200<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg200
2676B		%vreg199<def> = MOVi32imm 1; GPR32:%vreg199
2680B		STRWui %vreg199, <fi#11>, 50; mem:ST4[%kind] GPR32:%vreg199
2688B		%vreg201<def> = LDRXui %vreg200, 10; mem:LD8[%task38] GPR64:%vreg201 GPR64common:%vreg200
2704B		CBZX %vreg201, <BB#21>; GPR64:%vreg201
2720B		B <BB#20>
	    Successors according to CFG: BB#20 BB#21

2736B	BB#20: derived from LLVM BB %land.lhs.true.40
	    Predecessors according to CFG: BB#19
2752B		%vreg203<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg203
2768B		%vreg204<def> = LDRXui %vreg203, 10; mem:LD8[%task41] GPR64common:%vreg204,%vreg203
2784B		%vreg205<def> = LDRBBui %vreg204, 205; mem:LD1[%final_task42] GPR32:%vreg205 GPR64common:%vreg204
2800B		%vreg206<def> = ANDWri %vreg205, 0; GPR32common:%vreg206 GPR32:%vreg205
2816B		%vreg255<def> = MOVi32imm 1; GPR32:%vreg255
2864B		TBNZW %vreg206, 0, <BB#22>; GPR32common:%vreg206
2880B		B <BB#21>
	    Successors according to CFG: BB#22 BB#21

2896B	BB#21: derived from LLVM BB %lor.rhs
	    Predecessors according to CFG: BB#19 BB#20
2912B		%vreg208<def> = LDRBBui <fi#6>, 0; mem:LD1[%flags.addr](align=4) GPR32:%vreg208
2928B		%vreg255<def> = UBFMWri %vreg208, 1, 1; GPR32:%vreg255,%vreg208
2976B		B <BB#22>
	    Successors according to CFG: BB#22

2992B	BB#22: derived from LLVM BB %lor.end
	    Predecessors according to CFG: BB#20 BB#21
3056B		%vreg211<def> = LDRWui <fi#8>, 0; mem:LD4[%priority.addr] GPR32:%vreg211
3088B		%vreg212<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg212
3096B		%vreg210<def> = ANDWri %vreg255, 0; GPR32common:%vreg210 GPR32:%vreg255
3104B		STRBBui %vreg210, <fi#11>, 205; mem:ST1[%final_task46] GPR32common:%vreg210
3112B		STRWui %vreg211, <fi#11>, 22; mem:ST4[%priority48] GPR32:%vreg211
3120B		%vreg213<def> = LDRXui %vreg212, 10; mem:LD8[%task49] GPR64:%vreg213 GPR64common:%vreg212
3128B		CBZX %vreg213, <BB#24>; GPR64:%vreg213
3136B		B <BB#23>
	    Successors according to CFG: BB#23 BB#24

3152B	BB#23: derived from LLVM BB %if.then.51
	    Predecessors according to CFG: BB#22
3168B		%vreg214<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg214
3184B		%vreg215<def> = LDRXui %vreg214, 10; mem:LD8[%task52] GPR64common:%vreg215,%vreg214
3200B		%vreg216<def> = LDRBBui %vreg215, 204; mem:LD1[%in_tied_task] GPR32:%vreg216 GPR64common:%vreg215
3248B		%vreg218<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg218
3252B		%vreg217<def> = ANDWri %vreg216, 0; GPR32common:%vreg217 GPR32:%vreg216
3256B		STRBBui %vreg217, <fi#11>, 204; mem:ST1[%in_tied_task54] GPR32common:%vreg217
3264B		%vreg219<def> = LDRXui %vreg218, 10; mem:LD8[%task56] GPR64common:%vreg219,%vreg218
3280B		%vreg220<def> = LDRXui %vreg219, 5; mem:LD8[%taskgroup57] GPR64:%vreg220 GPR64common:%vreg219
3296B		STRXui %vreg220, <fi#11>, 5; mem:ST8[%taskgroup58] GPR64:%vreg220
3312B		B <BB#24>
	    Successors according to CFG: BB#24

3328B	BB#24: derived from LLVM BB %if.end.59
	    Predecessors according to CFG: BB#22 BB#23
3344B		%vreg221<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg221
3360B		%vreg222<def> = ADDXri <fi#11>, 0, 0; GPR64common:%vreg222
3376B		STRXui %vreg222, %vreg221, 10; mem:ST8[%task60] GPR64common:%vreg222,%vreg221
3392B		%vreg223<def> = LDRXui <fi#2>, 0; mem:LD8[%cpyfn.addr] GPR64:%vreg223
3408B		CBZX %vreg223, <BB#26>; GPR64:%vreg223
3424B		B <BB#25>
	    Successors according to CFG: BB#25 BB#26

3440B	BB#25: derived from LLVM BB %if.then.64
	    Predecessors according to CFG: BB#24
3448B		%vreg229<def> = COPY %SP; GPR64:%vreg229
3456B		%vreg226<def> = LDRXui <fi#3>, 0; mem:LD8[%arg_size.addr] GPR64:%vreg226
3472B		%vreg227<def> = LDRXui <fi#4>, 0; mem:LD8[%arg_align.addr] GPR64:%vreg227
3488B		%vreg228<def> = ADDXrr %vreg226, %vreg227; GPR64common:%vreg228 GPR64:%vreg226,%vreg227
3520B		STRXui %vreg229, <fi#12>, 0; mem:ST8[%saved_stack] GPR64:%vreg229
3536B		%vreg230<def> = ADDXri %vreg228, 14, 0; GPR64common:%vreg230,%vreg228
3552B		%vreg231<def> = ANDXri %vreg230, 7995; GPR64common:%vreg231,%vreg230
3568B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3584B		%vreg232<def> = COPY %SP; GPR64:%vreg232
3600B		%vreg233<def> = SUBSXrr %vreg232, %vreg231, %NZCV<imp-def,dead>; GPR64:%vreg233,%vreg232 GPR64common:%vreg231
3616B		%SP<def> = COPY %vreg233; GPR64:%vreg233
3632B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3648B		%vreg234<def> = LDRXui <fi#4>, 0; mem:LD8[%arg_align.addr] GPR64common:%vreg234
3744B		%vreg239<def> = LDRXui <fi#2>, 0; mem:LD8[%cpyfn.addr] GPR64:%vreg239
3760B		%vreg240<def> = LDRXui <fi#1>, 0; mem:LD8[%data.addr] GPR64:%vreg240
3768B		%vreg235<def> = ADDXrr %vreg233, %vreg234; GPR64common:%vreg235,%vreg234 GPR64:%vreg233
3776B		%vreg236<def> = SUBSXri %vreg235, 1, 0, %NZCV<imp-def,dead>; GPR64:%vreg236 GPR64common:%vreg235
3784B		%vreg237<def> = SUBSXri %vreg234, 1, 0, %NZCV<imp-def,dead>; GPR64:%vreg237 GPR64common:%vreg234
3792B		%vreg238<def> = BICXrr %vreg236, %vreg237; GPR64:%vreg238,%vreg236,%vreg237
3800B		STRXui %vreg238, <fi#13>, 0; mem:ST8[%arg] GPR64:%vreg238
3808B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3816B		%X0<def> = COPY %vreg238; GPR64:%vreg238
3824B		%X1<def> = COPY %vreg240; GPR64:%vreg240
3832B		BLR %vreg239, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %SP<imp-def>, ...; GPR64:%vreg239
3840B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3856B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3872B		STACKMAP 6, 0, 0, <fi#13>, 0, 0, <fi#0>, 0, 0, <fi#12>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack13] LD8[FixedStack0] LD8[FixedStack12] LD8[FixedStack11] LD8[FixedStack10]
3888B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3904B		%vreg241<def> = LDRXui <fi#0>, 0; mem:LD8[%fn.addr] GPR64:%vreg241
3920B		%vreg242<def> = LDRXui <fi#13>, 0; mem:LD8[%arg] GPR64:%vreg242
3936B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3952B		%X0<def> = COPY %vreg242; GPR64:%vreg242
3968B		BLR %vreg241, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...; GPR64:%vreg241
3984B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4000B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4016B		STACKMAP 7, 0, 0, <fi#12>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack12] LD8[FixedStack11] LD8[FixedStack10]
4032B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4048B		%vreg243<def> = LDRXui <fi#12>, 0; mem:LD8[%saved_stack] GPR64:%vreg243
4064B		%SP<def> = COPY %vreg243; GPR64:%vreg243
4080B		B <BB#27>
	    Successors according to CFG: BB#27

4096B	BB#26: derived from LLVM BB %if.else.69
	    Predecessors according to CFG: BB#24
4112B		%vreg224<def> = LDRXui <fi#0>, 0; mem:LD8[%fn.addr] GPR64:%vreg224
4128B		%vreg225<def> = LDRXui <fi#1>, 0; mem:LD8[%data.addr] GPR64:%vreg225
4144B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4160B		%X0<def> = COPY %vreg225; GPR64:%vreg225
4176B		BLR %vreg224, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...; GPR64:%vreg224
4192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4224B		STACKMAP 8, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack11] LD8[FixedStack10]
4240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4256B		B <BB#27>
	    Successors according to CFG: BB#27

4272B	BB#27: derived from LLVM BB %if.end.70
	    Predecessors according to CFG: BB#26 BB#25
4288B		%vreg244<def> = ADDXri <fi#11>, 0, 0; GPR64sp:%vreg244
4304B		%vreg245<def> = ADDXri %vreg244, 8, 0; GPR64sp:%vreg245,%vreg244
4320B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4328B		%W1<def> = COPY %WZR
4352B		%X0<def> = COPY %vreg245; GPR64sp:%vreg245
4384B		BL <ga:@priority_queue_empty_p>, <regmask>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %SP<imp-def>, %W0<imp-def>, ...
4400B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4416B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4432B		STACKMAP 9, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack11] LD8[FixedStack10]
4448B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4464B		%vreg247<def> = COPY %W0; GPR32:%vreg247
4480B		TBNZW %vreg247, 0, <BB#29>; GPR32:%vreg247
4496B		B <BB#28>
	    Successors according to CFG: BB#29 BB#28

4512B	BB#28: derived from LLVM BB %if.then.72
	    Predecessors according to CFG: BB#27
4528B		%vreg248<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg248
4544B		%vreg249<def> = ADDXri %vreg248, 1280, 0; GPR64sp:%vreg249 GPR64common:%vreg248
4560B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4576B		%X0<def> = COPY %vreg249; GPR64sp:%vreg249
4592B		BL <ga:@gomp_mutex_lock>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...
4608B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4624B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4640B		STACKMAP 10, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack11] LD8[FixedStack10]
4656B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4672B		%vreg250<def> = ADDXri <fi#11>, 0, 0; GPR64sp:%vreg250
4688B		%vreg251<def> = ADDXri %vreg250, 8, 0; GPR64sp:%vreg251,%vreg250
4704B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4720B		%X0<def> = COPY %vreg251; GPR64sp:%vreg251
4736B		BL <ga:@gomp_clear_parent>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...
4752B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4768B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4784B		STACKMAP 11, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack10]
4800B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4816B		%vreg252<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg252
4832B		%vreg253<def> = ADDXri %vreg252, 1280, 0; GPR64sp:%vreg253 GPR64common:%vreg252
4848B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4864B		%X0<def> = COPY %vreg253; GPR64sp:%vreg253
4880B		BL <ga:@gomp_mutex_unlock>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...
4896B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4912B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4928B		STACKMAP 12, 0, ...
4944B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4960B		B <BB#29>
	    Successors according to CFG: BB#29

4976B	BB#29: derived from LLVM BB %if.end.75
	    Predecessors according to CFG: BB#27 BB#28
4992B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5008B		BL <ga:@gomp_end_task>, <regmask>, %SP<imp-use>, %SP<imp-def>, ...
5024B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5040B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5056B		STACKMAP 13, 0, ...
5072B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5088B		B <BB#52>
	    Successors according to CFG: BB#52

5104B	BB#30: derived from LLVM BB %if.else.76
	    Predecessors according to CFG: BB#14
5120B		%vreg47<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg47
5136B		%vreg48<def> = LDRXui %vreg47, 10; mem:LD8[%task78] GPR64common:%vreg48,%vreg47
5152B		STRXui %vreg48, <fi#15>, 0; mem:ST8[%parent] GPR64common:%vreg48
5168B		%vreg49<def> = LDRXui %vreg48, 5; mem:LD8[%taskgroup80] GPR64:%vreg49 GPR64common:%vreg48
5232B		%vreg51<def> = LDRBBui <fi#6>, 0; mem:LD1[%flags.addr](align=4) GPR32:%vreg51
5236B		STRXui %vreg49, <fi#16>, 0; mem:ST8[%taskgroup79] GPR64:%vreg49
5240B		STRXui %XZR, <fi#19>, 0; mem:ST8[%depend_size]
5248B		TBZW %vreg51, 3, <BB#32>; GPR32:%vreg51
5264B		B <BB#31>
	    Successors according to CFG: BB#31 BB#32

5280B	BB#31: derived from LLVM BB %if.then.84
	    Predecessors according to CFG: BB#30
5296B		%vreg52<def> = LDRXui <fi#7>, 0; mem:LD8[%depend.addr] GPR64common:%vreg52
5312B		%vreg53<def> = LDRXui %vreg52, 0; mem:LD8[%arrayidx] GPR64:%vreg53 GPR64common:%vreg52
5328B		%vreg55:sub_32<def,read-undef> = MOVi32imm 40; GPR64:%vreg55
5360B		%vreg56<def> = MADDXrrr %vreg53, %vreg55, %XZR; GPR64:%vreg56,%vreg53,%vreg55
5376B		STRXui %vreg56, <fi#19>, 0; mem:ST8[%depend_size] GPR64:%vreg56
5392B		B <BB#32>
	    Successors according to CFG: BB#32

5408B	BB#32: derived from LLVM BB %if.end.86
	    Predecessors according to CFG: BB#30 BB#31
5424B		%vreg57<def> = LDRXui <fi#19>, 0; mem:LD8[%depend_size] GPR64:%vreg57
5440B		%vreg58<def> = LDRXui <fi#3>, 0; mem:LD8[%arg_size.addr] GPR64:%vreg58
5472B		%vreg60<def> = LDRXui <fi#4>, 0; mem:LD8[%arg_align.addr] GPR64:%vreg60
5480B		%vreg59<def> = ADDXrr %vreg57, %vreg58; GPR64:%vreg59,%vreg57,%vreg58
5488B		%vreg61<def> = ADDXrr %vreg59, %vreg60; GPR64common:%vreg61 GPR64:%vreg59,%vreg60
5504B		%vreg62<def> = ADDXri %vreg61, 207, 0; GPR64sp:%vreg62 GPR64common:%vreg61
5520B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5536B		%X0<def> = COPY %vreg62; GPR64sp:%vreg62
5552B		BL <ga:@gomp_malloc>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %X0<imp-def>, ...
5568B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5584B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5600B		STACKMAP 14, 0, 0, <fi#17>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#19>, 0, 0, <fi#18>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#14>, 0, 0, <fi#16>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack17] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack2] LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack19] LD8[FixedStack18](align=1) LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack14] LD8[FixedStack16] LD8[FixedStack10] LD8[FixedStack9]
5616B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5632B		%vreg63<def> = COPY %X0; GPR64:%vreg63
5648B		STRXui %vreg63, <fi#14>, 0; mem:ST8[%task77] GPR64:%vreg63
5664B		%vreg64<def> = LDRXui <fi#19>, 0; mem:LD8[%depend_size] GPR64:%vreg64
5696B		%vreg66<def> = LDRXui <fi#4>, 0; mem:LD8[%arg_align.addr] GPR64common:%vreg66
5808B		%vreg72<def> = LDRXui <fi#15>, 0; mem:LD8[%parent] GPR64:%vreg72
5816B		%vreg71<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64:%vreg71
5824B		%vreg65<def> = ADDXrr %vreg63, %vreg64; GPR64:%vreg65,%vreg63,%vreg64
5832B		%vreg67<def> = ADDXrr %vreg65, %vreg66; GPR64common:%vreg67,%vreg66 GPR64:%vreg65
5840B		%vreg68<def> = ADDXri %vreg67, 207, 0; GPR64common:%vreg68,%vreg67
5848B		%vreg69<def> = SUBSXri %vreg66, 1, 0, %NZCV<imp-def,dead>; GPR64:%vreg69 GPR64common:%vreg66
5856B		%vreg70<def> = BICXrr %vreg68, %vreg69; GPR64:%vreg70,%vreg69 GPR64common:%vreg68
5864B		STRXui %vreg70, <fi#17>, 0; mem:ST8[%arg81] GPR64:%vreg70
5872B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5888B		%W0<def> = COPY %WZR
5896B		BL <ga:@gomp_icv>, <regmask>, %SP<imp-use>, %W0<imp-use>, %SP<imp-def>, %X0<imp-def>, ...
5904B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5912B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5920B		STACKMAP 15, 0, 0, <fi#17>, 0, 0, <fi#3>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#19>, 0, 0, <fi#18>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#14>, 0, 0, <fi#16>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, %vreg71, %vreg72, ...; mem:LD8[FixedStack17] LD8[FixedStack3] LD8[FixedStack2] LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack19] LD8[FixedStack18](align=1) LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack14] LD8[FixedStack16] LD8[FixedStack10] LD8[FixedStack9] GPR64:%vreg71,%vreg72
5936B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5952B		%vreg74<def> = COPY %X0; GPR64all:%vreg74
5968B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5984B		%X0<def> = COPY %vreg71; GPR64:%vreg71
6000B		%X1<def> = COPY %vreg72; GPR64:%vreg72
6016B		%X2<def> = COPY %vreg74; GPR64all:%vreg74
6032B		BL <ga:@gomp_init_task>, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %X2<imp-use>, %SP<imp-def>, ...
6048B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
6064B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
6080B		STACKMAP 16, 0, 0, <fi#17>, 0, 0, <fi#3>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#19>, 0, 0, <fi#18>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#14>, 0, 0, <fi#16>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack17] LD8[FixedStack3] LD8[FixedStack2] LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack19] LD8[FixedStack18](align=1) LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack14] LD8[FixedStack16] LD8[FixedStack10] LD8[FixedStack9]
6096B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
6112B		%vreg75<def> = LDRWui <fi#8>, 0; mem:LD4[%priority.addr] GPR32:%vreg75
6128B		%vreg76<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64common:%vreg76
6144B		STRWui %vreg75, %vreg76, 22; mem:ST4[%priority99] GPR32:%vreg75 GPR64common:%vreg76
6160B		%vreg77<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64common:%vreg77
6176B		%vreg78<def> = MOVi32imm 1; GPR32:%vreg78
6192B		STRWui %vreg78, %vreg77, 50; mem:ST4[%kind100] GPR32:%vreg78 GPR64common:%vreg77
6208B		%vreg79<def> = LDRXui <fi#15>, 0; mem:LD8[%parent] GPR64common:%vreg79
6224B		%vreg80<def> = LDRBBui %vreg79, 204; mem:LD1[%in_tied_task101] GPR32:%vreg80 GPR64common:%vreg79
6240B		%vreg81<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64common:%vreg81
6256B		%vreg82<def> = ANDWri %vreg80, 0; GPR32common:%vreg82 GPR32:%vreg80
6272B		STRBBui %vreg82, %vreg81, 204; mem:ST1[%in_tied_task103] GPR32common:%vreg82 GPR64common:%vreg81
6288B		%vreg83<def> = LDRXui <fi#16>, 0; mem:LD8[%taskgroup79] GPR64:%vreg83
6304B		%vreg84<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64common:%vreg84
6320B		STRXui %vreg83, %vreg84, 5; mem:ST8[%taskgroup105] GPR64:%vreg83 GPR64common:%vreg84
6336B		%vreg85<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64:%vreg85
6352B		%vreg86<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg86
6368B		STRXui %vreg85, %vreg86, 10; mem:ST8[%task106] GPR64:%vreg85 GPR64common:%vreg86
6384B		%vreg87<def> = LDRXui <fi#2>, 0; mem:LD8[%cpyfn.addr] GPR64:%vreg87
6400B		CBZX %vreg87, <BB#34>; GPR64:%vreg87
6416B		B <BB#33>
	    Successors according to CFG: BB#33 BB#34

6432B	BB#33: derived from LLVM BB %if.then.108
	    Predecessors according to CFG: BB#32
6448B		%vreg91<def> = LDRXui <fi#2>, 0; mem:LD8[%cpyfn.addr] GPR64:%vreg91
6464B		%vreg92<def> = LDRXui <fi#17>, 0; mem:LD8[%arg81] GPR64:%vreg92
6480B		%vreg93<def> = LDRXui <fi#1>, 0; mem:LD8[%data.addr] GPR64:%vreg93
6496B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
6512B		%X0<def> = COPY %vreg92; GPR64:%vreg92
6528B		%X1<def> = COPY %vreg93; GPR64:%vreg93
6544B		BLR %vreg91, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %SP<imp-def>, ...; GPR64:%vreg91
6560B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
6576B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
6592B		STACKMAP 17, 0, 0, <fi#17>, 0, 0, <fi#7>, 0, 0, <fi#19>, 0, 0, <fi#18>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#14>, 0, 0, <fi#16>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack17] LD8[FixedStack7] LD8[FixedStack19] LD8[FixedStack18](align=1) LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack14] LD8[FixedStack16] LD8[FixedStack10] LD8[FixedStack9]
6608B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
6624B		%vreg94<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64common:%vreg94
6640B		%vreg95<def> = MOVi32imm 1; GPR32:%vreg95
6656B		STRBBui %vreg95, %vreg94, 206; mem:ST1[%copy_ctors_done] GPR32:%vreg95 GPR64common:%vreg94
6672B		B <BB#35>
	    Successors according to CFG: BB#35

6688B	BB#34: derived from LLVM BB %if.else.109
	    Predecessors according to CFG: BB#32
6704B		%vreg88<def> = LDRXui <fi#17>, 0; mem:LD8[%arg81] GPR64:%vreg88
6720B		%vreg89<def> = LDRXui <fi#1>, 0; mem:LD8[%data.addr] GPR64:%vreg89
6736B		%vreg90<def> = LDRXui <fi#3>, 0; mem:LD8[%arg_size.addr] GPR64:%vreg90
6752B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
6768B		%X0<def> = COPY %vreg88; GPR64:%vreg88
6784B		%X1<def> = COPY %vreg89; GPR64:%vreg89
6800B		%X2<def> = COPY %vreg90; GPR64:%vreg90
6816B		BL <es:memcpy>, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %X2<imp-use>, %SP<imp-def>, ...
6832B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
6848B		B <BB#35>
	    Successors according to CFG: BB#35

6864B	BB#35: derived from LLVM BB %if.end.110
	    Predecessors according to CFG: BB#34 BB#33
6880B		%vreg96<def> = LDRXui <fi#15>, 0; mem:LD8[%parent] GPR64:%vreg96
6896B		%vreg97<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg97
6912B		STRXui %vreg96, %vreg97, 10; mem:ST8[%task111] GPR64:%vreg96 GPR64common:%vreg97
6928B		%vreg98<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64common:%vreg98
6944B		%vreg99<def> = MOVi32imm 2; GPR32:%vreg99
6960B		STRWui %vreg99, %vreg98, 50; mem:ST4[%kind112] GPR32:%vreg99 GPR64common:%vreg98
6976B		%vreg100<def> = LDRXui <fi#0>, 0; mem:LD8[%fn.addr] GPR64:%vreg100
6992B		%vreg101<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64common:%vreg101
7008B		STRXui %vreg100, %vreg101, 23; mem:ST8[%fn113] GPR64:%vreg100 GPR64common:%vreg101
7024B		%vreg102<def> = LDRXui <fi#17>, 0; mem:LD8[%arg81] GPR64:%vreg102
7040B		%vreg103<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64common:%vreg103
7056B		STRXui %vreg102, %vreg103, 24; mem:ST8[%fn_data] GPR64:%vreg102 GPR64common:%vreg103
7072B		%vreg104<def> = LDRWui <fi#6>, 0; mem:LD4[%flags.addr] GPR32:%vreg104
7104B		%vreg106<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64common:%vreg106
7112B		%vreg105<def> = UBFMWri %vreg104, 1, 1; GPR32:%vreg105,%vreg104
7120B		STRBBui %vreg105, %vreg106, 205; mem:ST1[%final_task116] GPR32:%vreg105 GPR64common:%vreg106
7136B		%vreg107<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg107
7152B		%vreg108<def> = ADDXri %vreg107, 1280, 0; GPR64sp:%vreg108 GPR64common:%vreg107
7168B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
7184B		%X0<def> = COPY %vreg108; GPR64sp:%vreg108
7200B		BL <ga:@gomp_mutex_lock>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...
7216B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
7232B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
7248B		STACKMAP 18, 0, 0, <fi#7>, 0, 0, <fi#19>, 0, 0, <fi#18>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#14>, 0, 0, <fi#16>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack7] LD8[FixedStack19] LD8[FixedStack18](align=1) LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack14] LD8[FixedStack16] LD8[FixedStack10]
7264B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
7280B		%vreg109<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg109
7296B		%vreg110<def> = ADDXri %vreg109, 128, 0; GPR64sp:%vreg110 GPR64common:%vreg109
7312B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
7328B		%X0<def> = COPY %vreg110; GPR64sp:%vreg110
7344B		BL <ga:@gomp_team_barrier_cancelled>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>, ...
7360B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
7376B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
7392B		STACKMAP 19, 0, 0, <fi#7>, 0, 0, <fi#19>, 0, 0, <fi#18>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#14>, 0, 0, <fi#16>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack7] LD8[FixedStack19] LD8[FixedStack18](align=1) LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack14] LD8[FixedStack16] LD8[FixedStack10]
7408B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
7424B		%vreg111<def> = COPY %W0; GPR32:%vreg111
7440B		TBNZW %vreg111, 0, <BB#38>; GPR32:%vreg111
7456B		B <BB#36>
	    Successors according to CFG: BB#38 BB#36

7472B	BB#36: derived from LLVM BB %lor.lhs.false.122
	    Predecessors according to CFG: BB#35
7488B		%vreg113<def> = LDRXui <fi#16>, 0; mem:LD8[%taskgroup79] GPR64:%vreg113
7536B		%vreg256<def> = COPY %WZR; GPR32common:%vreg256
7552B		CBZX %vreg113, <BB#39>; GPR64:%vreg113
7568B		B <BB#37>
	    Successors according to CFG: BB#37 BB#39

7584B	BB#37: derived from LLVM BB %land.lhs.true.124
	    Predecessors according to CFG: BB#36
7600B		%vreg116<def> = LDRXui <fi#16>, 0; mem:LD8[%taskgroup79] GPR64common:%vreg116
7616B		%vreg117<def> = LDRBBui %vreg116, 41; mem:LD1[%cancelled125] GPR32:%vreg117 GPR64common:%vreg116
7664B		%vreg256<def> = COPY %WZR; GPR32common:%vreg256
7680B		TBZW %vreg117, 0, <BB#39>; GPR32:%vreg117
7696B		B <BB#38>
	    Successors according to CFG: BB#38 BB#39

7712B	BB#38: derived from LLVM BB %land.rhs
	    Predecessors according to CFG: BB#35 BB#37
7728B		%vreg119<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64common:%vreg119
7744B		%vreg120<def> = LDRBBui %vreg119, 206; mem:LD1[%copy_ctors_done128] GPR32:%vreg120 GPR64common:%vreg119
7760B		%vreg256<def> = EORWri %vreg120, 0; GPR32common:%vreg256 GPR32:%vreg120
7808B		B <BB#39>
	    Successors according to CFG: BB#39

7824B	BB#39: derived from LLVM BB %land.end
	    Predecessors according to CFG: BB#36 BB#37 BB#38
7856B		TBZW %vreg256, 0, <BB#41>; GPR32common:%vreg256
7872B		B <BB#40>
	    Successors according to CFG: BB#40 BB#41

7888B	BB#40: derived from LLVM BB %if.then.132
	    Predecessors according to CFG: BB#39
7904B		%vreg183<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg183
7920B		%vreg184<def> = ADDXri %vreg183, 1280, 0; GPR64sp:%vreg184 GPR64common:%vreg183
7936B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
7952B		%X0<def> = COPY %vreg184; GPR64sp:%vreg184
7968B		BL <ga:@gomp_mutex_unlock>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...
7984B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
8000B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
8016B		STACKMAP 20, 0, 0, <fi#14>, 0, ...; mem:LD8[FixedStack14]
8032B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
8048B		%vreg185<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64:%vreg185
8064B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
8080B		%X0<def> = COPY %vreg185; GPR64:%vreg185
8096B		BL <ga:@gomp_finish_task>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...
8112B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
8128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
8144B		STACKMAP 21, 0, 0, <fi#14>, 0, ...; mem:LD8[FixedStack14]
8160B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
8176B		%vreg186<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64:%vreg186
8192B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
8208B		%X0<def> = COPY %vreg186; GPR64:%vreg186
8224B		BL <ga:@free>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...
8240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
8256B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
8272B		STACKMAP 22, 0, ...
8288B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
8304B		B <BB#52>
	    Successors according to CFG: BB#52

8320B	BB#41: derived from LLVM BB %if.end.134
	    Predecessors according to CFG: BB#39
8336B		%vreg122<def> = LDRXui <fi#16>, 0; mem:LD8[%taskgroup79] GPR64:%vreg122
8352B		CBZX %vreg122, <BB#43>; GPR64:%vreg122
8368B		B <BB#42>
	    Successors according to CFG: BB#42 BB#43

8384B	BB#42: derived from LLVM BB %if.then.136
	    Predecessors according to CFG: BB#41
8400B		%vreg123<def> = LDRXui <fi#16>, 0; mem:LD8[%taskgroup79] GPR64common:%vreg123
8416B		%vreg124<def> = LDRXui %vreg123, 6; mem:LD8[%num_children] GPR64common:%vreg124,%vreg123
8432B		%vreg125<def> = ADDXri %vreg124, 1, 0; GPR64common:%vreg125,%vreg124
8448B		STRXui %vreg125, %vreg123, 6; mem:ST8[%num_children] GPR64common:%vreg125,%vreg123
8464B		B <BB#43>
	    Successors according to CFG: BB#43

8480B	BB#43: derived from LLVM BB %if.end.137
	    Predecessors according to CFG: BB#41 BB#42
8496B		%vreg126<def> = LDRXui <fi#19>, 0; mem:LD8[%depend_size] GPR64:%vreg126
8512B		CBZX %vreg126, <BB#47>; GPR64:%vreg126
8528B		B <BB#44>
	    Successors according to CFG: BB#44 BB#47

8544B	BB#44: derived from LLVM BB %if.then.139
	    Predecessors according to CFG: BB#43
8560B		%vreg127<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64:%vreg127
8576B		%vreg128<def> = LDRXui <fi#15>, 0; mem:LD8[%parent] GPR64:%vreg128
8592B		%vreg129<def> = LDRXui <fi#7>, 0; mem:LD8[%depend.addr] GPR64:%vreg129
8608B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
8624B		%X0<def> = COPY %vreg127; GPR64:%vreg127
8640B		%X1<def> = COPY %vreg128; GPR64:%vreg128
8656B		%X2<def> = COPY %vreg129; GPR64:%vreg129
8672B		BL <ga:@gomp_task_handle_depend>, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %X2<imp-use>, %SP<imp-def>, ...
8688B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
8704B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
8720B		STACKMAP 23, 0, 0, <fi#18>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#14>, 0, 0, <fi#16>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack18](align=1) LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack14] LD8[FixedStack16] LD8[FixedStack10]
8736B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
8752B		%vreg130<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64common:%vreg130
8768B		%vreg131<def> = LDRXui %vreg130, 10; mem:LD8[%num_dependees] GPR64:%vreg131 GPR64common:%vreg130
8784B		CBZX %vreg131, <BB#46>; GPR64:%vreg131
8800B		B <BB#45>
	    Successors according to CFG: BB#45 BB#46

8816B	BB#45: derived from LLVM BB %if.then.141
	    Predecessors according to CFG: BB#44
8832B		%vreg181<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg181
8848B		%vreg182<def> = ADDXri %vreg181, 1280, 0; GPR64sp:%vreg182 GPR64common:%vreg181
8864B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
8880B		%X0<def> = COPY %vreg182; GPR64sp:%vreg182
8896B		BL <ga:@gomp_mutex_unlock>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...
8912B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
8928B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
8944B		STACKMAP 24, 0, ...
8960B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
8976B		B <BB#52>
	    Successors according to CFG: BB#52

8992B	BB#46: derived from LLVM BB %if.end.143
	    Predecessors according to CFG: BB#44
9008B		B <BB#47>
	    Successors according to CFG: BB#47

9024B	BB#47: derived from LLVM BB %if.end.144
	    Predecessors according to CFG: BB#43 BB#46
9072B		%vreg134<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64common:%vreg134
9080B		%vreg132<def> = LDRXui <fi#15>, 0; mem:LD8[%parent] GPR64common:%vreg132
9088B		%vreg135<def> = LDRWui <fi#8>, 0; mem:LD4[%priority.addr] GPR32:%vreg135
9104B		%vreg136<def> = LDRBBui %vreg134, 207; mem:LD1[%parent_depends_on] GPR32:%vreg136 GPR64common:%vreg134
9112B		%vreg133<def> = ADDXri %vreg132, 8, 0; GPR64sp:%vreg133 GPR64common:%vreg132
9120B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
9128B		%W4<def> = COPY %WZR
9132B		%W5<def> = COPY %WZR
9136B		%vreg137<def> = ANDWri %vreg136, 0; GPR32sp:%vreg137 GPR32:%vreg136
9184B		%W0<def> = MOVi32imm 1
9200B		%X1<def> = COPY %vreg133; GPR64sp:%vreg133
9216B		%X2<def> = COPY %vreg134; GPR64common:%vreg134
9232B		%W3<def> = COPY %vreg135; GPR32:%vreg135
9280B		%W6<def> = COPY %vreg137; GPR32sp:%vreg137
9296B		BL <ga:@priority_queue_insert>, <regmask>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use>, %X2<imp-use>, %W3<imp-use>, %W4<imp-use>, %W5<imp-use>, %W6<imp-use>, %SP<imp-def>, ...
9312B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
9328B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
9344B		STACKMAP 25, 0, 0, <fi#18>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#14>, 0, 0, <fi#16>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack18](align=1) LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack14] LD8[FixedStack16] LD8[FixedStack10]
9360B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
9376B		%vreg140<def> = LDRXui <fi#16>, 0; mem:LD8[%taskgroup79] GPR64:%vreg140
9392B		CBZX %vreg140, <BB#49>; GPR64:%vreg140
9408B		B <BB#48>
	    Successors according to CFG: BB#48 BB#49

9424B	BB#48: derived from LLVM BB %if.then.148
	    Predecessors according to CFG: BB#47
9472B		%vreg143<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64common:%vreg143
9480B		%vreg141<def> = LDRXui <fi#16>, 0; mem:LD8[%taskgroup79] GPR64common:%vreg141
9488B		%vreg144<def> = LDRWui <fi#8>, 0; mem:LD4[%priority.addr] GPR32:%vreg144
9504B		%vreg145<def> = LDRBBui %vreg143, 207; mem:LD1[%parent_depends_on149] GPR32:%vreg145 GPR64common:%vreg143
9512B		%vreg142<def> = ADDXri %vreg141, 8, 0; GPR64sp:%vreg142 GPR64common:%vreg141
9520B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
9528B		%W4<def> = COPY %WZR
9532B		%W5<def> = COPY %WZR
9536B		%vreg146<def> = ANDWri %vreg145, 0; GPR32sp:%vreg146 GPR32:%vreg145
9584B		%W0<def> = MOVi32imm 2
9600B		%X1<def> = COPY %vreg142; GPR64sp:%vreg142
9616B		%X2<def> = COPY %vreg143; GPR64common:%vreg143
9632B		%W3<def> = COPY %vreg144; GPR32:%vreg144
9680B		%W6<def> = COPY %vreg146; GPR32sp:%vreg146
9696B		BL <ga:@priority_queue_insert>, <regmask>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use>, %X2<imp-use>, %W3<imp-use>, %W4<imp-use>, %W5<imp-use>, %W6<imp-use>, %SP<imp-def>, ...
9712B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
9728B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
9744B		STACKMAP 26, 0, 0, <fi#18>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#14>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack18](align=1) LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack14] LD8[FixedStack10]
9760B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
9776B		B <BB#49>
	    Successors according to CFG: BB#49

9792B	BB#49: derived from LLVM BB %if.end.151
	    Predecessors according to CFG: BB#47 BB#48
9840B		%vreg151<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64common:%vreg151
9848B		%vreg149<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg149
9856B		%vreg152<def> = LDRWui <fi#8>, 0; mem:LD4[%priority.addr] GPR32:%vreg152
9872B		%vreg153<def> = LDRBBui %vreg151, 207; mem:LD1[%parent_depends_on152] GPR32:%vreg153 GPR64common:%vreg151
9880B		%vreg150<def> = ADDXri %vreg149, 1288, 0; GPR64sp:%vreg150 GPR64common:%vreg149
9888B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
9896B		%W0<def> = COPY %WZR
9900B		%W5<def> = COPY %WZR
9904B		%vreg154<def> = ANDWri %vreg153, 0; GPR32sp:%vreg154 GPR32:%vreg153
9912B		%W4<def> = MOVi32imm 1
9968B		%X1<def> = COPY %vreg150; GPR64sp:%vreg150
9984B		%X2<def> = COPY %vreg151; GPR64common:%vreg151
10000B		%W3<def> = COPY %vreg152; GPR32:%vreg152
10048B		%W6<def> = COPY %vreg154; GPR32sp:%vreg154
10064B		BL <ga:@priority_queue_insert>, <regmask>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use>, %X2<imp-use>, %W3<imp-use>, %W4<imp-use>, %W5<imp-use>, %W6<imp-use>, %SP<imp-def>, ...
10080B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
10096B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
10112B		STACKMAP 27, 0, 0, <fi#18>, 0, 0, <fi#15>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack18](align=1) LD8[FixedStack15] LD8[FixedStack10]
10128B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
10144B		%vreg157<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg157
10160B		%vreg158<def> = LDRWui %vreg157, 330; mem:LD4[%task_count154] GPR32common:%vreg158 GPR64common:%vreg157
10176B		%vreg159<def> = ADDWri %vreg158, 1, 0; GPR32common:%vreg159,%vreg158
10192B		STRWui %vreg159, %vreg157, 330; mem:ST4[%task_count154] GPR32common:%vreg159 GPR64common:%vreg157
10208B		%vreg160<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg160
10224B		%vreg161<def> = LDRWui %vreg160, 331; mem:LD4[%task_queued_count] GPR32common:%vreg161 GPR64common:%vreg160
10240B		%vreg162<def> = ADDWri %vreg161, 1, 0; GPR32common:%vreg162,%vreg161
10256B		STRWui %vreg162, %vreg160, 331; mem:ST4[%task_queued_count] GPR32common:%vreg162 GPR64common:%vreg160
10272B		%vreg163<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg163
10288B		%vreg164<def> = ADDXri %vreg163, 128, 0; GPR64sp:%vreg164 GPR64common:%vreg163
10304B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
10320B		%X0<def> = COPY %vreg164; GPR64sp:%vreg164
10336B		BL <ga:@gomp_team_barrier_set_task_pending>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...
10352B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
10368B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
10384B		STACKMAP 28, 0, 0, <fi#18>, 0, 0, <fi#15>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack18](align=1) LD8[FixedStack15] LD8[FixedStack10]
10400B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
10448B		%vreg167<def> = LDRXui <fi#15>, 0; mem:LD8[%parent] GPR64common:%vreg167
10456B		%vreg165<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg165
10464B		%vreg168<def> = LDRBBui %vreg167, 204; mem:LD1[%in_tied_task158] GPR32:%vreg168 GPR64common:%vreg167
10592B		%vreg175<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg175
10596B		%vreg166<def> = LDRWui %vreg165, 332; mem:LD4[%task_running_count] GPR32:%vreg166 GPR64common:%vreg165
10600B		%vreg172<def> = LDRWui %vreg165, 0; mem:LD4[%nthreads162] GPR32:%vreg172 GPR64common:%vreg165
10608B		%vreg169<def> = ORNWrr %WZR, %vreg168; GPR32:%vreg169,%vreg168
10616B		%vreg170<def> = ANDWri %vreg169, 0; GPR32common:%vreg170 GPR32:%vreg169
10624B		%vreg171<def> = ADDWrr %vreg166, %vreg170; GPR32:%vreg171,%vreg166 GPR32common:%vreg170
10632B		%vreg173<def,dead> = SUBSWrr %vreg171, %vreg172, %NZCV<imp-def>; GPR32:%vreg173,%vreg171,%vreg172
10640B		%vreg174<def> = CSINCWr %WZR, %WZR, 2, %NZCV<imp-use>; GPR32:%vreg174
10648B		STRBBui %vreg174, <fi#18>, 0; mem:ST1[%do_wake] GPR32:%vreg174
10656B		%vreg176<def> = ADDXri %vreg175, 1280, 0; GPR64sp:%vreg176 GPR64common:%vreg175
10664B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
10672B		%X0<def> = COPY %vreg176; GPR64sp:%vreg176
10680B		BL <ga:@gomp_mutex_unlock>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...
10688B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
10696B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
10704B		STACKMAP 29, 0, 0, <fi#18>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack18](align=1) LD8[FixedStack10]
10720B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
10736B		%vreg177<def> = LDRBBui <fi#18>, 0; mem:LD1[%do_wake] GPR32:%vreg177
10752B		TBZW %vreg177, 0, <BB#51>; GPR32:%vreg177
10768B		B <BB#50>
	    Successors according to CFG: BB#50 BB#51

10784B	BB#50: derived from LLVM BB %if.then.168
	    Predecessors according to CFG: BB#49
10800B		%vreg178<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg178
10816B		%vreg179<def> = ADDXri %vreg178, 128, 0; GPR64sp:%vreg179 GPR64common:%vreg178
10832B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
10880B		%W1<def> = MOVi32imm 1
10888B		%X0<def> = COPY %vreg179; GPR64sp:%vreg179
10896B		BL <ga:@gomp_team_barrier_wake>, <regmask>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %SP<imp-def>, ...
10912B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
10928B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
10944B		STACKMAP 30, 0, ...
10960B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
10976B		B <BB#51>
	    Successors according to CFG: BB#51

10992B	BB#51: derived from LLVM BB %if.end.170
	    Predecessors according to CFG: BB#49 BB#50
11008B		B <BB#52>
	    Successors according to CFG: BB#52

11024B	BB#52: derived from LLVM BB %if.end.171
	    Predecessors according to CFG: BB#51 BB#45 BB#40 BB#29 BB#4
11040B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
11072B		%X0<def> = COPY %XZR
11088B		%X1<def> = COPY %XZR
11104B		BL <ga:@check_migrate>, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %SP<imp-def>, ...
11120B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
11136B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
11152B		STACKMAP 31, 0, ...
11168B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
11184B		RET_ReallyLR

# End machine code for function GOMP_task.


selectOrSplit GPR64:%vreg11 [16r,432r:0)  0@16r w=3.713235e-03
AllocationOrder(GPR64) = [ %X8 %X9 %X10 %X11 %X12 %X13 %X14 %X15 %X16 %X17 %X18 %X0 %X1 %X2 %X3 %X4 %X5 %X6 %X7 %X20 %X21 %X22 %X23 %X24 %X25 %X26 %X27 %X28 %LR ]
hints: %X7
missed hint %X7
assigning %vreg11 to %X20: W20 [16r,432r:0)  0@16r

selectOrSplit GPR32:%vreg10 [32r,416r:0)  0@32r w=3.864796e-03
AllocationOrder(GPR32) = [ %W8 %W9 %W10 %W11 %W12 %W13 %W14 %W15 %W16 %W17 %W18 %W0 %W1 %W2 %W3 %W4 %W5 %W6 %W7 %W20 %W21 %W22 %W23 %W24 %W25 %W26 %W27 %W28 %W30 ]
hints: %W6
missed hint %W6
assigning %vreg10 to %W21: W21 [32r,416r:0)  0@32r

selectOrSplit GPR32:%vreg9 [148r,200r:0)  0@148r w=4.469026e-03
hints: %W5
assigning %vreg9 to %W5: W5 [148r,200r:0)  0@148r

selectOrSplit GPR64:%vreg8 [152r,384r:0)  0@152r w=4.794304e-03
hints: %X4
missed hint %X4
assigning %vreg8 to %X22: W22 [152r,384r:0)  0@152r

selectOrSplit GPR64:%vreg7 [160r,368r:0)  0@160r w=4.983553e-03
hints: %X3
missed hint %X3
assigning %vreg7 to %X23: W23 [160r,368r:0)  0@160r

selectOrSplit GPR64:%vreg6 [168r,352r:0)  0@168r w=5.188356e-03
hints: %X2
missed hint %X2
assigning %vreg6 to %X24: W24 [168r,352r:0)  0@168r

selectOrSplit GPR64:%vreg5 [176r,336r:0)  0@176r w=5.410714e-03
hints: %X1
missed hint %X1
assigning %vreg5 to %X25: W25 [176r,336r:0)  0@176r

selectOrSplit GPR64:%vreg4 [184r,320r:0)  0@184r w=5.652985e-03
hints: %X0
missed hint %X0
assigning %vreg4 to %X26: W26 [184r,320r:0)  0@184r

selectOrSplit GPR64common:%vreg15 [560r,592r:0)  0@560r w=7.013889e-03
AllocationOrder(GPR64common) = [ %X8 %X9 %X10 %X11 %X12 %X13 %X14 %X15 %X16 %X17 %X18 %X0 %X1 %X2 %X3 %X4 %X5 %X6 %X7 %X20 %X21 %X22 %X23 %X24 %X25 %X26 %X27 %X28 %LR ]
hints: %X0
assigning %vreg15 to %X0: W0 [560r,592r:0)  0@560r

selectOrSplit GPR64sp:%vreg18 [688r,720r:0)  0@688r w=2.337963e-03
AllocationOrder(GPR64sp) = [ %X8 %X9 %X10 %X11 %X12 %X13 %X14 %X15 %X16 %X17 %X18 %X0 %X1 %X2 %X3 %X4 %X5 %X6 %X7 %X20 %X21 %X22 %X23 %X24 %X25 %X26 %X27 %X28 %LR ]
hints: %X0
assigning %vreg18 to %X0: W0 [688r,720r:0)  0@688r

selectOrSplit GPR32:%vreg19 [816r,832r:0)  0@816r w=inf
hints: %W0
assigning %vreg19 to %W0: W0 [816r,832r:0)  0@816r

selectOrSplit GPR64:%vreg193 [2144r,2176r:0)  0@2144r w=3.629499e-04
hints: %X0
assigning %vreg193 to %X0: W0 [2144r,2176r:0)  0@2144r

selectOrSplit GPR64:%vreg195 [2320r,2528r:0)  0@2320r w=3.104673e-03
hints: %X1
missed hint %X1
assigning %vreg195 to %X20: W20 [2320r,2528r:0)  0@2320r

selectOrSplit GPR64all:%vreg197 [2464r,2544r:0)  0@2464r w=2.621724e-03
AllocationOrder(GPR64all) = [ %X0 %X1 %X2 %X3 %X4 %X5 %X6 %X7 %X8 %X9 %X10 %X11 %X12 %X13 %X14 %X15 %X16 %X17 %X18 %X20 %X21 %X22 %X23 %X24 %X25 %X26 %X27 %X28 %LR ]
hints: %X0
missed hint %X0
assigning %vreg197 to %X2: W2 [2464r,2544r:0)  0@2464r

selectOrSplit GPR64:%vreg240 [3760r,3824r:0)  0@3760r w=1.356064e-03
hints: %X1
assigning %vreg240 to %X1: W1 [3760r,3824r:0)  0@3760r

selectOrSplit GPR64:%vreg238 [3792r,3816r:0)  0@3792r w=2.225992e-03
hints: %X0
assigning %vreg238 to %X0: W0 [3792r,3816r:0)  0@3792r

selectOrSplit GPR64:%vreg242 [3920r,3952r:0)  0@3920r w=1.456513e-03
hints: %X0
assigning %vreg242 to %X0: W0 [3920r,3952r:0)  0@3920r

selectOrSplit GPR64:%vreg225 [4128r,4160r:0)  0@4128r w=1.456513e-03
hints: %X0
assigning %vreg225 to %X0: W0 [4128r,4160r:0)  0@4128r

selectOrSplit GPR64sp:%vreg245 [4304r,4352r:0)  0@4304r w=2.808990e-03
hints: %X0
assigning %vreg245 to %X0: W0 [4304r,4352r:0)  0@4304r

selectOrSplit GPR32:%vreg247 [4464r,4480r:0)  0@4464r w=inf
hints: %W0
assigning %vreg247 to %W0: W0 [4464r,4480r:0)  0@4464r

selectOrSplit GPR64sp:%vreg249 [4544r,4576r:0)  0@4544r w=1.456513e-03
hints: %X0
assigning %vreg249 to %X0: W0 [4544r,4576r:0)  0@4544r

selectOrSplit GPR64sp:%vreg251 [4688r,4720r:0)  0@4688r w=1.456513e-03
hints: %X0
assigning %vreg251 to %X0: W0 [4688r,4720r:0)  0@4688r

selectOrSplit GPR64sp:%vreg253 [4832r,4864r:0)  0@4832r w=1.456513e-03
hints: %X0
assigning %vreg253 to %X0: W0 [4832r,4864r:0)  0@4832r

selectOrSplit GPR64sp:%vreg62 [5504r,5536r:0)  0@5504r w=3.016726e-04
hints: %X0
assigning %vreg62 to %X0: W0 [5504r,5536r:0)  0@5504r

selectOrSplit GPR64:%vreg63 [5632r,5824r:0)  0@5632r w=3.302092e-04
hints: %X0
assigning %vreg63 to %X0: W0 [5632r,5824r:0)  0@5632r

selectOrSplit GPR64:%vreg72 [5808r,6000r:0)  0@5808r w=3.302092e-04
hints: %X1
missed hint %X1
assigning %vreg72 to %X20: W20 [5808r,6000r:0)  0@5808r

selectOrSplit GPR64:%vreg71 [5816r,5984r:0)  0@5816r w=3.441617e-04
hints: %X0
missed hint %X0
assigning %vreg71 to %X21: W21 [5816r,5984r:0)  0@5816r

selectOrSplit GPR64all:%vreg74 [5952r,6016r:0)  0@5952r w=2.808676e-04
hints: %X0
missed hint %X0
assigning %vreg74 to %X2: W2 [5952r,6016r:0)  0@5952r

selectOrSplit GPR64:%vreg92 [6464r,6512r:0)  0@6464r w=1.454493e-04
hints: %X0
assigning %vreg92 to %X0: W0 [6464r,6512r:0)  0@6464r

selectOrSplit GPR64:%vreg93 [6480r,6528r:0)  0@6480r w=1.454493e-04
hints: %X1
assigning %vreg93 to %X1: W1 [6480r,6528r:0)  0@6480r

selectOrSplit GPR64:%vreg88 [6704r,6768r:0)  0@6704r w=1.404338e-04
hints: %X0
assigning %vreg88 to %X0: W0 [6704r,6768r:0)  0@6704r

selectOrSplit GPR64:%vreg89 [6720r,6784r:0)  0@6720r w=1.404338e-04
hints: %X1
assigning %vreg89 to %X1: W1 [6720r,6784r:0)  0@6720r

selectOrSplit GPR64:%vreg90 [6736r,6800r:0)  0@6736r w=1.404338e-04
hints: %X2
assigning %vreg90 to %X2: W2 [6736r,6800r:0)  0@6736r

selectOrSplit GPR64sp:%vreg108 [7152r,7184r:0)  0@7152r w=3.016726e-04
hints: %X0
assigning %vreg108 to %X0: W0 [7152r,7184r:0)  0@7152r

selectOrSplit GPR64sp:%vreg110 [7296r,7328r:0)  0@7296r w=3.016726e-04
hints: %X0
assigning %vreg110 to %X0: W0 [7296r,7328r:0)  0@7296r

selectOrSplit GPR32:%vreg111 [7424r,7440r:0)  0@7424r w=inf
hints: %W0
assigning %vreg111 to %W0: W0 [7424r,7440r:0)  0@7424r

selectOrSplit GPR64sp:%vreg184 [7920r,7952r:0)  0@7920r w=1.508363e-04
hints: %X0
assigning %vreg184 to %X0: W0 [7920r,7952r:0)  0@7920r

selectOrSplit GPR64:%vreg185 [8048r,8080r:0)  0@8048r w=1.508363e-04
hints: %X0
assigning %vreg185 to %X0: W0 [8048r,8080r:0)  0@8048r

selectOrSplit GPR64:%vreg186 [8176r,8208r:0)  0@8176r w=1.508363e-04
hints: %X0
assigning %vreg186 to %X0: W0 [8176r,8208r:0)  0@8176r

selectOrSplit GPR64:%vreg127 [8560r,8624r:0)  0@8560r w=7.021691e-05
hints: %X0
assigning %vreg127 to %X0: W0 [8560r,8624r:0)  0@8560r

selectOrSplit GPR64:%vreg128 [8576r,8640r:0)  0@8576r w=7.021691e-05
hints: %X1
assigning %vreg128 to %X1: W1 [8576r,8640r:0)  0@8576r

selectOrSplit GPR64:%vreg129 [8592r,8656r:0)  0@8592r w=7.021691e-05
hints: %X2
assigning %vreg129 to %X2: W2 [8592r,8656r:0)  0@8592r

selectOrSplit GPR64sp:%vreg182 [8848r,8880r:0)  0@8848r w=3.770908e-05
hints: %X0
assigning %vreg182 to %X0: W0 [8848r,8880r:0)  0@8848r

selectOrSplit GPR64common:%vreg134 [9072r,9216r:0)  0@9072r w=1.347545e-04
hints: %X2
assigning %vreg134 to %X2: W2 [9072r,9216r:0)  0@9072r

selectOrSplit GPR32:%vreg135 [9088r,9232r:0)  0@9088r w=8.983634e-05
hints: %W3
assigning %vreg135 to %W3: W3 [9088r,9232r:0)  0@9088r

selectOrSplit GPR64sp:%vreg133 [9112r,9200r:0)  0@9112r w=1.001454e-04
hints: %X1
assigning %vreg133 to %X1: W1 [9112r,9200r:0)  0@9112r

selectOrSplit GPR32sp:%vreg137 [9136r,9280r:0)  0@9136r w=8.983634e-05
AllocationOrder(GPR32sp) = [ %W8 %W9 %W10 %W11 %W12 %W13 %W14 %W15 %W16 %W17 %W18 %W0 %W1 %W2 %W3 %W4 %W5 %W6 %W7 %W20 %W21 %W22 %W23 %W24 %W25 %W26 %W27 %W28 %W30 ]
hints: %W6
assigning %vreg137 to %W6: W6 [9136r,9280r:0)  0@9136r

selectOrSplit GPR64common:%vreg143 [9472r,9616r:0)  0@9472r w=6.737725e-05
hints: %X2
assigning %vreg143 to %X2: W2 [9472r,9616r:0)  0@9472r

selectOrSplit GPR32:%vreg144 [9488r,9632r:0)  0@9488r w=4.491817e-05
hints: %W3
assigning %vreg144 to %W3: W3 [9488r,9632r:0)  0@9488r

selectOrSplit GPR64sp:%vreg142 [9512r,9600r:0)  0@9512r w=5.007271e-05
hints: %X1
assigning %vreg142 to %X1: W1 [9512r,9600r:0)  0@9512r

selectOrSplit GPR32sp:%vreg146 [9536r,9680r:0)  0@9536r w=4.491817e-05
hints: %W6
assigning %vreg146 to %W6: W6 [9536r,9680r:0)  0@9536r

selectOrSplit GPR64common:%vreg151 [9840r,9984r:0)  0@9840r w=1.347545e-04
hints: %X2
assigning %vreg151 to %X2: W2 [9840r,9984r:0)  0@9840r

selectOrSplit GPR32:%vreg152 [9856r,10000r:0)  0@9856r w=8.983634e-05
hints: %W3
assigning %vreg152 to %W3: W3 [9856r,10000r:0)  0@9856r

selectOrSplit GPR64sp:%vreg150 [9880r,9968r:0)  0@9880r w=1.001454e-04
hints: %X1
assigning %vreg150 to %X1: W1 [9880r,9968r:0)  0@9880r

selectOrSplit GPR32sp:%vreg154 [9904r,10048r:0)  0@9904r w=8.983634e-05
hints: %W6
assigning %vreg154 to %W6: W6 [9904r,10048r:0)  0@9904r

selectOrSplit GPR64sp:%vreg164 [10288r,10320r:0)  0@10288r w=1.131272e-04
hints: %X0
assigning %vreg164 to %X0: W0 [10288r,10320r:0)  0@10288r

selectOrSplit GPR64sp:%vreg176 [10656r,10672r:0)  0@10656r w=1.174783e-04
hints: %X0
assigning %vreg176 to %X0: W0 [10656r,10672r:0)  0@10656r

selectOrSplit GPR64sp:%vreg179 [10816r,10888r:0)  0@10816r w=5.177009e-05
hints: %X0
assigning %vreg179 to %X0: W0 [10816r,10888r:0)  0@10816r

selectOrSplit GPR32:%vreg255 [2816r,2896B:0)[2928r,2992B:1)[2992B,3096r:2)  0@2816r 1@2928r 2@2992B-phi w=2.170616e-03
assigning %vreg255 to %W8: W8 [2816r,2896B:0)[2928r,2992B:1)[2992B,3096r:2)  0@2816r 1@2928r 2@2992B-phi

selectOrSplit GPR32common:%vreg256 [7536r,7584B:0)[7664r,7712B:1)[7760r,7824B:2)[7824B,7856r:3)  0@7536r 1@7664r 2@7760r 3@7824B-phi w=2.605881e-04
AllocationOrder(GPR32common) = [ %W8 %W9 %W10 %W11 %W12 %W13 %W14 %W15 %W16 %W17 %W18 %W0 %W1 %W2 %W3 %W4 %W5 %W6 %W7 %W20 %W21 %W22 %W23 %W24 %W25 %W26 %W27 %W28 %W30 ]
assigning %vreg256 to %W8: W8 [7536r,7584B:0)[7664r,7712B:1)[7760r,7824B:2)[7824B,7856r:3)  0@7536r 1@7664r 2@7760r 3@7824B-phi

selectOrSplit GPR32:%vreg12 [144r,448r:0)  0@144r w=4.261364e-03
assigning %vreg12 to %W27: W27 [144r,448r:0)  0@144r

selectOrSplit GPR32common:%vreg13 [200r,400r:0)  0@200r w=5.000000e-03
assigning %vreg13 to %W28: W28 [200r,400r:0)  0@200r

selectOrSplit GPR64:%vreg16 [592r,624r:0)  0@592r w=6.944444e-03
assigning %vreg16 to %X8: W8 [592r,624r:0)  0@592r

selectOrSplit GPR64common:%vreg17 [672r,688r:0)  0@672r w=inf
assigning %vreg17 to %X8: W8 [672r,688r:0)  0@672r

selectOrSplit GPR64common:%vreg20 [880r,896r:0)  0@880r w=inf
assigning %vreg20 to %X8: W8 [880r,896r:0)  0@880r

selectOrSplit GPR64common:%vreg21 [896r,912r:0)  0@896r w=inf
assigning %vreg21 to %X8: W8 [896r,912r:0)  0@896r

selectOrSplit GPR64:%vreg22 [912r,928r:0)  0@912r w=inf
assigning %vreg22 to %X8: W8 [912r,928r:0)  0@912r

selectOrSplit GPR64common:%vreg23 [976r,992r:0)  0@976r w=inf
assigning %vreg23 to %X8: W8 [976r,992r:0)  0@976r

selectOrSplit GPR64common:%vreg24 [992r,1008r:0)  0@992r w=inf
assigning %vreg24 to %X8: W8 [992r,1008r:0)  0@992r

selectOrSplit GPR64common:%vreg25 [1008r,1024r:0)  0@1008r w=inf
assigning %vreg25 to %X8: W8 [1008r,1024r:0)  0@1008r

selectOrSplit GPR32:%vreg26 [1024r,1040r:0)  0@1024r w=inf
assigning %vreg26 to %W8: W8 [1024r,1040r:0)  0@1024r

selectOrSplit GPR32:%vreg27 [1120r,1136r:0)  0@1120r w=inf
assigning %vreg27 to %W8: W8 [1120r,1136r:0)  0@1120r

selectOrSplit GPR32:%vreg28 [1248r,1296r:0)  0@1248r w=1.534598e-03
assigning %vreg28 to %W8: W8 [1248r,1296r:0)  0@1248r

selectOrSplit GPR64common:%vreg29 [1264r,1280r:0)  0@1264r w=inf
assigning %vreg29 to %X9: W9 [1264r,1280r:0)  0@1264r

selectOrSplit GPR32:%vreg30 [1280r,1296r:0)  0@1280r w=inf
assigning %vreg30 to %W9: W9 [1280r,1296r:0)  0@1280r

selectOrSplit GPR32:%vreg31 [1296r,1296d:0)  0@1296r w=inf
assigning %vreg31 to %W8: W8 [1296r,1296d:0)  0@1296r

selectOrSplit GPR64common:%vreg32 [1360r,1376r:0)  0@1360r w=inf
assigning %vreg32 to %X8: W8 [1360r,1376r:0)  0@1360r

selectOrSplit GPR32:%vreg33 [1376r,1392r:0)  0@1376r w=inf
assigning %vreg33 to %W8: W8 [1376r,1392r:0)  0@1376r

selectOrSplit GPR32:%vreg35 [1472r,1488r:0)  0@1472r w=inf
assigning %vreg35 to %W8: W8 [1472r,1488r:0)  0@1472r

selectOrSplit GPR64:%vreg36 [1536r,1552r:0)  0@1536r w=inf
assigning %vreg36 to %X8: W8 [1536r,1552r:0)  0@1536r

selectOrSplit GPR64common:%vreg37 [1600r,1616r:0)  0@1600r w=inf
assigning %vreg37 to %X8: W8 [1600r,1616r:0)  0@1600r

selectOrSplit GPR64:%vreg38 [1616r,1632r:0)  0@1616r w=inf
assigning %vreg38 to %X8: W8 [1616r,1632r:0)  0@1616r

selectOrSplit GPR64common:%vreg39 [1680r,1696r:0)  0@1680r w=inf
assigning %vreg39 to %X8: W8 [1680r,1696r:0)  0@1680r

selectOrSplit GPR64common:%vreg40 [1696r,1712r:0)  0@1696r w=inf
assigning %vreg40 to %X8: W8 [1696r,1712r:0)  0@1696r

selectOrSplit GPR32:%vreg41 [1712r,1728r:0)  0@1712r w=inf
assigning %vreg41 to %W8: W8 [1712r,1728r:0)  0@1712r

selectOrSplit GPR32common:%vreg42 [1728r,1744r:0)  0@1728r w=inf
assigning %vreg42 to %W8: W8 [1728r,1744r:0)  0@1728r

selectOrSplit GPR64common:%vreg43 [1792r,1824r:0)  0@1792r w=8.960573e-04
assigning %vreg43 to %X8: W8 [1792r,1824r:0)  0@1792r

selectOrSplit GPR32:%vreg44 [1808r,1840r:0)  0@1808r w=5.973715e-04
assigning %vreg44 to %W9: W9 [1808r,1840r:0)  0@1808r

selectOrSplit GPR32:%vreg45 [1824r,1840r:0)  0@1824r w=inf
assigning %vreg45 to %W8: W8 [1824r,1840r:0)  0@1824r

selectOrSplit GPR32:%vreg46 [1840r,1840d:0)  0@1840r w=inf
assigning %vreg46 to %W8: W8 [1840r,1840d:0)  0@1840r

selectOrSplit GPR32:%vreg187 [1904r,1920r:0)  0@1904r w=inf
assigning %vreg187 to %W8: W8 [1904r,1920r:0)  0@1904r

selectOrSplit GPR64common:%vreg188 [1968r,1984r:0)  0@1968r w=inf
assigning %vreg188 to %X8: W8 [1968r,1984r:0)  0@1968r

selectOrSplit GPR64:%vreg189 [1984r,2000r:0)  0@1984r w=inf
assigning %vreg189 to %X8: W8 [1984r,2000r:0)  0@1984r

selectOrSplit GPR64common:%vreg190 [2048r,2064r:0)  0@2048r w=inf
assigning %vreg190 to %X8: W8 [2048r,2064r:0)  0@2048r

selectOrSplit GPR64common:%vreg191 [2064r,2080r:0)  0@2064r w=inf
assigning %vreg191 to %X8: W8 [2064r,2080r:0)  0@2064r

selectOrSplit GPR64:%vreg192 [2080r,2096r:0)  0@2080r w=inf
assigning %vreg192 to %X8: W8 [2080r,2096r:0)  0@2080r

selectOrSplit GPR64common:%vreg194 [2304r,2320r:0)  0@2304r w=inf
assigning %vreg194 to %X8: W8 [2304r,2320r:0)  0@2304r

selectOrSplit GPR64common:%vreg200 [2672r,2688r:0)  0@2672r w=2.995115e-03
assigning %vreg200 to %X8: W8 [2672r,2688r:0)  0@2672r

selectOrSplit GPR32:%vreg199 [2676r,2680r:0)  0@2676r w=inf
assigning %vreg199 to %W9: W9 [2676r,2680r:0)  0@2676r

selectOrSplit GPR64:%vreg201 [2688r,2704r:0)  0@2688r w=inf
assigning %vreg201 to %X8: W8 [2688r,2704r:0)  0@2688r

selectOrSplit GPR64common:%vreg203 [2752r,2768r:0)  0@2752r w=inf
assigning %vreg203 to %X8: W8 [2752r,2768r:0)  0@2752r

selectOrSplit GPR64common:%vreg204 [2768r,2784r:0)  0@2768r w=inf
assigning %vreg204 to %X8: W8 [2768r,2784r:0)  0@2768r

selectOrSplit GPR32:%vreg205 [2784r,2800r:0)  0@2784r w=inf
assigning %vreg205 to %W8: W8 [2784r,2800r:0)  0@2784r

selectOrSplit GPR32common:%vreg206 [2800r,2864r:0)  0@2800r w=1.342638e-03
assigning %vreg206 to %W9: W9 [2800r,2864r:0)  0@2800r

selectOrSplit GPR32:%vreg208 [2912r,2928r:0)  0@2912r w=inf
assigning %vreg208 to %W8: W8 [2912r,2928r:0)  0@2912r

selectOrSplit GPR32:%vreg211 [3056r,3112r:0)  0@3056r w=2.732385e-03
assigning %vreg211 to %W9: W9 [3056r,3112r:0)  0@3056r

selectOrSplit GPR64common:%vreg212 [3088r,3120r:0)  0@3088r w=2.884185e-03
assigning %vreg212 to %X10: W10 [3088r,3120r:0)  0@3088r

selectOrSplit GPR32common:%vreg210 [3096r,3104r:0)  0@3096r w=inf
assigning %vreg210 to %W8: W8 [3096r,3104r:0)  0@3096r

selectOrSplit GPR64:%vreg213 [3120r,3128r:0)  0@3120r w=inf
assigning %vreg213 to %X8: W8 [3120r,3128r:0)  0@3120r

selectOrSplit GPR64common:%vreg214 [3168r,3184r:0)  0@3168r w=inf
assigning %vreg214 to %X8: W8 [3168r,3184r:0)  0@3168r

selectOrSplit GPR64common:%vreg215 [3184r,3200r:0)  0@3184r w=inf
assigning %vreg215 to %X8: W8 [3184r,3200r:0)  0@3184r

selectOrSplit GPR32:%vreg216 [3200r,3252r:0)  0@3200r w=1.378283e-03
assigning %vreg216 to %W8: W8 [3200r,3252r:0)  0@3200r

selectOrSplit GPR64common:%vreg218 [3248r,3264r:0)  0@3248r w=1.497557e-03
assigning %vreg218 to %X9: W9 [3248r,3264r:0)  0@3248r

selectOrSplit GPR32common:%vreg217 [3252r,3256r:0)  0@3252r w=inf
assigning %vreg217 to %W8: W8 [3252r,3256r:0)  0@3252r

selectOrSplit GPR64common:%vreg219 [3264r,3280r:0)  0@3264r w=inf
assigning %vreg219 to %X8: W8 [3264r,3280r:0)  0@3264r

selectOrSplit GPR64:%vreg220 [3280r,3296r:0)  0@3280r w=inf
assigning %vreg220 to %X8: W8 [3280r,3296r:0)  0@3280r

selectOrSplit GPR64common:%vreg221 [3344r,3376r:0)  0@3344r w=2.884185e-03
assigning %vreg221 to %X8: W8 [3344r,3376r:0)  0@3344r

selectOrSplit GPR64common:%vreg222 [3360r,3376r:0)  0@3360r w=inf
assigning %vreg222 to %X9: W9 [3360r,3376r:0)  0@3360r

selectOrSplit GPR64:%vreg223 [3392r,3408r:0)  0@3392r w=inf
assigning %vreg223 to %X8: W8 [3392r,3408r:0)  0@3392r

selectOrSplit GPR64:%vreg229 [3448r,3520r:0)  0@3448r w=1.319881e-03
assigning %vreg229 to %X8: W8 [3448r,3520r:0)  0@3448r

selectOrSplit GPR64:%vreg226 [3456r,3488r:0)  0@3456r w=1.442092e-03
assigning %vreg226 to %X9: W9 [3456r,3488r:0)  0@3456r

selectOrSplit GPR64:%vreg227 [3472r,3488r:0)  0@3472r w=inf
assigning %vreg227 to %X10: W10 [3472r,3488r:0)  0@3472r

selectOrSplit GPR64common:%vreg228 [3488r,3536r:0)  0@3488r w=1.390589e-03
assigning %vreg228 to %X9: W9 [3488r,3536r:0)  0@3488r

selectOrSplit GPR64common:%vreg230 [3536r,3552r:0)  0@3536r w=inf
assigning %vreg230 to %X8: W8 [3536r,3552r:0)  0@3536r

selectOrSplit GPR64common:%vreg231 [3552r,3600r:0)  0@3552r w=1.390589e-03
assigning %vreg231 to %X8: W8 [3552r,3600r:0)  0@3552r

selectOrSplit GPR64:%vreg232 [3584r,3600r:0)  0@3584r w=inf
assigning %vreg232 to %X9: W9 [3584r,3600r:0)  0@3584r

selectOrSplit GPR64:%vreg233 [3600r,3768r:0)  0@3600r w=1.645204e-03
assigning %vreg233 to %X8: W8 [3600r,3768r:0)  0@3600r

selectOrSplit GPR64common:%vreg234 [3648r,3784r:0)  0@3648r w=1.743425e-03
assigning %vreg234 to %X9: W9 [3648r,3784r:0)  0@3648r

selectOrSplit GPR64:%vreg239 [3744r,3832r:0)  0@3744r w=1.276606e-03
assigning %vreg239 to %X10: W10 [3744r,3832r:0)  0@3744r

selectOrSplit GPR64common:%vreg235 [3768r,3776r:0)  0@3768r w=inf
assigning %vreg235 to %X8: W8 [3768r,3776r:0)  0@3768r

selectOrSplit GPR64:%vreg236 [3776r,3792r:0)  0@3776r w=1.497557e-03
assigning %vreg236 to %X8: W8 [3776r,3792r:0)  0@3776r

selectOrSplit GPR64:%vreg237 [3784r,3792r:0)  0@3784r w=inf
assigning %vreg237 to %X9: W9 [3784r,3792r:0)  0@3784r

selectOrSplit GPR64:%vreg241 [3904r,3968r:0)  0@3904r w=1.342638e-03
assigning %vreg241 to %X8: W8 [3904r,3968r:0)  0@3904r

selectOrSplit GPR64:%vreg243 [4048r,4064r:0)  0@4048r w=inf
assigning %vreg243 to %X8: W8 [4048r,4064r:0)  0@4048r

selectOrSplit GPR64:%vreg224 [4112r,4176r:0)  0@4112r w=1.342638e-03
assigning %vreg224 to %X8: W8 [4112r,4176r:0)  0@4112r

selectOrSplit GPR64sp:%vreg244 [4288r,4304r:0)  0@4288r w=inf
assigning %vreg244 to %X8: W8 [4288r,4304r:0)  0@4288r

selectOrSplit GPR64common:%vreg248 [4528r,4544r:0)  0@4528r w=inf
assigning %vreg248 to %X8: W8 [4528r,4544r:0)  0@4528r

selectOrSplit GPR64sp:%vreg250 [4672r,4688r:0)  0@4672r w=inf
assigning %vreg250 to %X8: W8 [4672r,4688r:0)  0@4672r

selectOrSplit GPR64common:%vreg252 [4816r,4832r:0)  0@4816r w=inf
assigning %vreg252 to %X8: W8 [4816r,4832r:0)  0@4816r

selectOrSplit GPR64common:%vreg47 [5120r,5136r:0)  0@5120r w=inf
assigning %vreg47 to %X8: W8 [5120r,5136r:0)  0@5120r

selectOrSplit GPR64common:%vreg48 [5136r,5168r:0)  0@5136r w=4.480287e-04
assigning %vreg48 to %X8: W8 [5136r,5168r:0)  0@5136r

selectOrSplit GPR64:%vreg49 [5168r,5236r:0)  0@5168r w=2.757100e-04
assigning %vreg49 to %X8: W8 [5168r,5236r:0)  0@5168r

selectOrSplit GPR32:%vreg51 [5232r,5248r:0)  0@5232r w=3.101737e-04
assigning %vreg51 to %W9: W9 [5232r,5248r:0)  0@5232r

selectOrSplit GPR64common:%vreg52 [5296r,5312r:0)  0@5296r w=inf
assigning %vreg52 to %X8: W8 [5296r,5312r:0)  0@5296r

selectOrSplit GPR64:%vreg53 [5312r,5360r:0)  0@5312r w=1.440092e-04
assigning %vreg53 to %X8: W8 [5312r,5360r:0)  0@5312r

selectOrSplit GPR64:%vreg55 [5328r,5360r:0)  0@5328r w=inf
assigning %vreg55 to %X9: W9 [5328r,5360r:0)  0@5328r

selectOrSplit GPR64:%vreg56 [5360r,5376r:0)  0@5360r w=inf
assigning %vreg56 to %X8: W8 [5360r,5376r:0)  0@5360r

selectOrSplit GPR64:%vreg57 [5424r,5480r:0)  0@5424r w=2.829655e-04
assigning %vreg57 to %X8: W8 [5424r,5480r:0)  0@5424r

selectOrSplit GPR64:%vreg58 [5440r,5480r:0)  0@5440r w=2.932551e-04
assigning %vreg58 to %X9: W9 [5440r,5480r:0)  0@5440r

selectOrSplit GPR64:%vreg60 [5472r,5488r:0)  0@5472r w=3.101737e-04
assigning %vreg60 to %X10: W10 [5472r,5488r:0)  0@5472r

selectOrSplit GPR64:%vreg59 [5480r,5488r:0)  0@5480r w=inf
assigning %vreg59 to %X8: W8 [5480r,5488r:0)  0@5480r

selectOrSplit GPR64common:%vreg61 [5488r,5504r:0)  0@5488r w=inf
assigning %vreg61 to %X8: W8 [5488r,5504r:0)  0@5488r

selectOrSplit GPR64:%vreg64 [5664r,5824r:0)  0@5664r w=2.304147e-04
assigning %vreg64 to %X8: W8 [5664r,5824r:0)  0@5664r

selectOrSplit GPR64common:%vreg66 [5696r,5848r:0)  0@5696r w=3.506311e-04
assigning %vreg66 to %X9: W9 [5696r,5848r:0)  0@5696r

selectOrSplit GPR64:%vreg65 [5824r,5832r:0)  0@5824r w=inf
assigning %vreg65 to %X8: W8 [5824r,5832r:0)  0@5824r

selectOrSplit GPR64common:%vreg67 [5832r,5840r:0)  0@5832r w=inf
assigning %vreg67 to %X8: W8 [5832r,5840r:0)  0@5832r

selectOrSplit GPR64common:%vreg68 [5840r,5856r:0)  0@5840r w=3.101737e-04
assigning %vreg68 to %X8: W8 [5840r,5856r:0)  0@5840r

selectOrSplit GPR64:%vreg69 [5848r,5856r:0)  0@5848r w=inf
assigning %vreg69 to %X9: W9 [5848r,5856r:0)  0@5848r

selectOrSplit GPR64:%vreg70 [5856r,5864r:0)  0@5856r w=inf
assigning %vreg70 to %X8: W8 [5856r,5864r:0)  0@5856r

selectOrSplit GPR32:%vreg75 [6112r,6144r:0)  0@6112r w=2.986858e-04
assigning %vreg75 to %W8: W8 [6112r,6144r:0)  0@6112r

selectOrSplit GPR64common:%vreg76 [6128r,6144r:0)  0@6128r w=inf
assigning %vreg76 to %X9: W9 [6128r,6144r:0)  0@6128r

selectOrSplit GPR64common:%vreg77 [6160r,6192r:0)  0@6160r w=2.986858e-04
assigning %vreg77 to %X8: W8 [6160r,6192r:0)  0@6160r

selectOrSplit GPR32:%vreg78 [6176r,6192r:0)  0@6176r w=inf
assigning %vreg78 to %W9: W9 [6176r,6192r:0)  0@6176r

selectOrSplit GPR64common:%vreg79 [6208r,6224r:0)  0@6208r w=inf
assigning %vreg79 to %X8: W8 [6208r,6224r:0)  0@6208r

selectOrSplit GPR32:%vreg80 [6224r,6256r:0)  0@6224r w=2.986858e-04
assigning %vreg80 to %W8: W8 [6224r,6256r:0)  0@6224r

selectOrSplit GPR64common:%vreg81 [6240r,6272r:0)  0@6240r w=2.986858e-04
assigning %vreg81 to %X9: W9 [6240r,6272r:0)  0@6240r

selectOrSplit GPR32common:%vreg82 [6256r,6272r:0)  0@6256r w=inf
assigning %vreg82 to %W8: W8 [6256r,6272r:0)  0@6256r

selectOrSplit GPR64:%vreg83 [6288r,6320r:0)  0@6288r w=2.986858e-04
assigning %vreg83 to %X8: W8 [6288r,6320r:0)  0@6288r

selectOrSplit GPR64common:%vreg84 [6304r,6320r:0)  0@6304r w=inf
assigning %vreg84 to %X9: W9 [6304r,6320r:0)  0@6304r

selectOrSplit GPR64:%vreg85 [6336r,6368r:0)  0@6336r w=2.986858e-04
assigning %vreg85 to %X8: W8 [6336r,6368r:0)  0@6336r

selectOrSplit GPR64common:%vreg86 [6352r,6368r:0)  0@6352r w=inf
assigning %vreg86 to %X9: W9 [6352r,6368r:0)  0@6352r

selectOrSplit GPR64:%vreg87 [6384r,6400r:0)  0@6384r w=inf
assigning %vreg87 to %X8: W8 [6384r,6400r:0)  0@6384r

selectOrSplit GPR64:%vreg91 [6448r,6544r:0)  0@6448r w=1.300728e-04
assigning %vreg91 to %X8: W8 [6448r,6544r:0)  0@6448r

selectOrSplit GPR64common:%vreg94 [6624r,6656r:0)  0@6624r w=1.493429e-04
assigning %vreg94 to %X8: W8 [6624r,6656r:0)  0@6624r

selectOrSplit GPR32:%vreg95 [6640r,6656r:0)  0@6640r w=inf
assigning %vreg95 to %W9: W9 [6640r,6656r:0)  0@6640r

selectOrSplit GPR64:%vreg96 [6880r,6912r:0)  0@6880r w=2.986858e-04
assigning %vreg96 to %X8: W8 [6880r,6912r:0)  0@6880r

selectOrSplit GPR64common:%vreg97 [6896r,6912r:0)  0@6896r w=inf
assigning %vreg97 to %X9: W9 [6896r,6912r:0)  0@6896r

selectOrSplit GPR64common:%vreg98 [6928r,6960r:0)  0@6928r w=2.986858e-04
assigning %vreg98 to %X8: W8 [6928r,6960r:0)  0@6928r

selectOrSplit GPR32:%vreg99 [6944r,6960r:0)  0@6944r w=inf
assigning %vreg99 to %W9: W9 [6944r,6960r:0)  0@6944r

selectOrSplit GPR64:%vreg100 [6976r,7008r:0)  0@6976r w=2.986858e-04
assigning %vreg100 to %X8: W8 [6976r,7008r:0)  0@6976r

selectOrSplit GPR64common:%vreg101 [6992r,7008r:0)  0@6992r w=inf
assigning %vreg101 to %X9: W9 [6992r,7008r:0)  0@6992r

selectOrSplit GPR64:%vreg102 [7024r,7056r:0)  0@7024r w=2.986858e-04
assigning %vreg102 to %X8: W8 [7024r,7056r:0)  0@7024r

selectOrSplit GPR64common:%vreg103 [7040r,7056r:0)  0@7040r w=inf
assigning %vreg103 to %X9: W9 [7040r,7056r:0)  0@7040r

selectOrSplit GPR32:%vreg104 [7072r,7112r:0)  0@7072r w=2.932551e-04
assigning %vreg104 to %W8: W8 [7072r,7112r:0)  0@7072r

selectOrSplit GPR64common:%vreg106 [7104r,7120r:0)  0@7104r w=3.101737e-04
assigning %vreg106 to %X9: W9 [7104r,7120r:0)  0@7104r

selectOrSplit GPR32:%vreg105 [7112r,7120r:0)  0@7112r w=inf
assigning %vreg105 to %W8: W8 [7112r,7120r:0)  0@7112r

selectOrSplit GPR64common:%vreg107 [7136r,7152r:0)  0@7136r w=inf
assigning %vreg107 to %X8: W8 [7136r,7152r:0)  0@7136r

selectOrSplit GPR64common:%vreg109 [7280r,7296r:0)  0@7280r w=inf
assigning %vreg109 to %X8: W8 [7280r,7296r:0)  0@7280r

selectOrSplit GPR64:%vreg113 [7488r,7552r:0)  0@7488r w=1.390434e-04
assigning %vreg113 to %X9: W9 [7488r,7552r:0)  0@7488r

selectOrSplit GPR64common:%vreg116 [7600r,7616r:0)  0@7600r w=inf
assigning %vreg116 to %X8: W8 [7600r,7616r:0)  0@7600r

selectOrSplit GPR32:%vreg117 [7616r,7680r:0)  0@7616r w=6.952169e-05
assigning %vreg117 to %W9: W9 [7616r,7680r:0)  0@7616r

selectOrSplit GPR64common:%vreg119 [7728r,7744r:0)  0@7728r w=inf
assigning %vreg119 to %X8: W8 [7728r,7744r:0)  0@7728r

selectOrSplit GPR32:%vreg120 [7744r,7760r:0)  0@7744r w=inf
assigning %vreg120 to %W8: W8 [7744r,7760r:0)  0@7744r

selectOrSplit GPR64common:%vreg183 [7904r,7920r:0)  0@7904r w=inf
assigning %vreg183 to %X8: W8 [7904r,7920r:0)  0@7904r

selectOrSplit GPR64:%vreg122 [8336r,8352r:0)  0@8336r w=inf
assigning %vreg122 to %X8: W8 [8336r,8352r:0)  0@8336r

selectOrSplit GPR64common:%vreg123 [8400r,8448r:0)  0@8400r w=1.080069e-04
assigning %vreg123 to %X8: W8 [8400r,8448r:0)  0@8400r

selectOrSplit GPR64common:%vreg124 [8416r,8432r:0)  0@8416r w=inf
assigning %vreg124 to %X9: W9 [8416r,8432r:0)  0@8416r

selectOrSplit GPR64common:%vreg125 [8432r,8448r:0)  0@8432r w=inf
assigning %vreg125 to %X9: W9 [8432r,8448r:0)  0@8432r

selectOrSplit GPR64:%vreg126 [8496r,8512r:0)  0@8496r w=inf
assigning %vreg126 to %X8: W8 [8496r,8512r:0)  0@8496r

selectOrSplit GPR64common:%vreg130 [8752r,8768r:0)  0@8752r w=inf
assigning %vreg130 to %X8: W8 [8752r,8768r:0)  0@8752r

selectOrSplit GPR64:%vreg131 [8768r,8784r:0)  0@8768r w=inf
assigning %vreg131 to %X8: W8 [8768r,8784r:0)  0@8768r

selectOrSplit GPR64common:%vreg181 [8832r,8848r:0)  0@8832r w=inf
assigning %vreg181 to %X8: W8 [8832r,8848r:0)  0@8832r

selectOrSplit GPR64common:%vreg132 [9080r,9112r:0)  0@9080r w=1.120072e-04
assigning %vreg132 to %X8: W8 [9080r,9112r:0)  0@9080r

selectOrSplit GPR32:%vreg136 [9104r,9136r:0)  0@9104r w=1.120072e-04
assigning %vreg136 to %W9: W9 [9104r,9136r:0)  0@9104r

selectOrSplit GPR64:%vreg140 [9376r,9392r:0)  0@9376r w=inf
assigning %vreg140 to %X8: W8 [9376r,9392r:0)  0@9376r

selectOrSplit GPR64common:%vreg141 [9480r,9512r:0)  0@9480r w=5.600358e-05
assigning %vreg141 to %X8: W8 [9480r,9512r:0)  0@9480r

selectOrSplit GPR32:%vreg145 [9504r,9536r:0)  0@9504r w=5.600358e-05
assigning %vreg145 to %W9: W9 [9504r,9536r:0)  0@9504r

selectOrSplit GPR64common:%vreg149 [9848r,9880r:0)  0@9848r w=1.120072e-04
assigning %vreg149 to %X8: W8 [9848r,9880r:0)  0@9848r

selectOrSplit GPR32:%vreg153 [9872r,9904r:0)  0@9872r w=1.120072e-04
assigning %vreg153 to %W9: W9 [9872r,9904r:0)  0@9872r

selectOrSplit GPR64common:%vreg157 [10144r,10192r:0)  0@10144r w=1.620104e-04
assigning %vreg157 to %X8: W8 [10144r,10192r:0)  0@10144r

selectOrSplit GPR32common:%vreg158 [10160r,10176r:0)  0@10160r w=inf
assigning %vreg158 to %W9: W9 [10160r,10176r:0)  0@10160r

selectOrSplit GPR32common:%vreg159 [10176r,10192r:0)  0@10176r w=inf
assigning %vreg159 to %W9: W9 [10176r,10192r:0)  0@10176r

selectOrSplit GPR64common:%vreg160 [10208r,10256r:0)  0@10208r w=1.620104e-04
assigning %vreg160 to %X8: W8 [10208r,10256r:0)  0@10208r

selectOrSplit GPR32common:%vreg161 [10224r,10240r:0)  0@10224r w=inf
assigning %vreg161 to %W9: W9 [10224r,10240r:0)  0@10224r

selectOrSplit GPR32common:%vreg162 [10240r,10256r:0)  0@10240r w=inf
assigning %vreg162 to %W9: W9 [10240r,10256r:0)  0@10240r

selectOrSplit GPR64common:%vreg163 [10272r,10288r:0)  0@10272r w=inf
assigning %vreg163 to %X8: W8 [10272r,10288r:0)  0@10272r

selectOrSplit GPR64common:%vreg167 [10448r,10464r:0)  0@10448r w=1.163151e-04
assigning %vreg167 to %X8: W8 [10448r,10464r:0)  0@10448r

selectOrSplit GPR64common:%vreg165 [10456r,10600r:0)  0@10456r w=1.334203e-04
assigning %vreg165 to %X9: W9 [10456r,10600r:0)  0@10456r

selectOrSplit GPR32:%vreg168 [10464r,10608r:0)  0@10464r w=8.894686e-05
assigning %vreg168 to %W8: W8 [10464r,10608r:0)  0@10464r

selectOrSplit GPR64common:%vreg175 [10592r,10656r:0)  0@10592r w=1.042825e-04
assigning %vreg175 to %X10: W10 [10592r,10656r:0)  0@10592r

selectOrSplit GPR32:%vreg166 [10596r,10624r:0)  0@10596r w=1.130540e-04
assigning %vreg166 to %W11: W11 [10596r,10624r:0)  0@10596r

selectOrSplit GPR32:%vreg172 [10600r,10632r:0)  0@10600r w=1.120072e-04
assigning %vreg172 to %W9: W9 [10600r,10632r:0)  0@10600r

selectOrSplit GPR32:%vreg169 [10608r,10616r:0)  0@10608r w=inf
assigning %vreg169 to %W8: W8 [10608r,10616r:0)  0@10608r

selectOrSplit GPR32common:%vreg170 [10616r,10624r:0)  0@10616r w=inf
assigning %vreg170 to %W8: W8 [10616r,10624r:0)  0@10616r

selectOrSplit GPR32:%vreg171 [10624r,10632r:0)  0@10624r w=inf
assigning %vreg171 to %W8: W8 [10624r,10632r:0)  0@10624r

selectOrSplit GPR32:%vreg173 [10632r,10632d:0)  0@10632r w=inf
assigning %vreg173 to %W8: W8 [10632r,10632d:0)  0@10632r

selectOrSplit GPR32:%vreg174 [10640r,10648r:0)  0@10640r w=inf
assigning %vreg174 to %W8: W8 [10640r,10648r:0)  0@10640r

selectOrSplit GPR32:%vreg177 [10736r,10752r:0)  0@10736r w=inf
assigning %vreg177 to %W8: W8 [10736r,10752r:0)  0@10736r

selectOrSplit GPR64common:%vreg178 [10800r,10816r:0)  0@10800r w=inf
assigning %vreg178 to %X8: W8 [10800r,10816r:0)  0@10800r

********** STACK TRANSFORMATION METADATA **********
********** Function: GOMP_task
********** REGISTER MAP **********
[%vreg4 -> %X26] GPR64
[%vreg5 -> %X25] GPR64
[%vreg6 -> %X24] GPR64
[%vreg7 -> %X23] GPR64
[%vreg8 -> %X22] GPR64
[%vreg9 -> %W5] GPR32
[%vreg10 -> %W21] GPR32
[%vreg11 -> %X20] GPR64
[%vreg12 -> %W27] GPR32
[%vreg13 -> %W28] GPR32common
[%vreg15 -> %X0] GPR64common
[%vreg16 -> %X8] GPR64
[%vreg17 -> %X8] GPR64common
[%vreg18 -> %X0] GPR64sp
[%vreg19 -> %W0] GPR32
[%vreg20 -> %X8] GPR64common
[%vreg21 -> %X8] GPR64common
[%vreg22 -> %X8] GPR64
[%vreg23 -> %X8] GPR64common
[%vreg24 -> %X8] GPR64common
[%vreg25 -> %X8] GPR64common
[%vreg26 -> %W8] GPR32
[%vreg27 -> %W8] GPR32
[%vreg28 -> %W8] GPR32
[%vreg29 -> %X9] GPR64common
[%vreg30 -> %W9] GPR32
[%vreg31 -> %W8] GPR32
[%vreg32 -> %X8] GPR64common
[%vreg33 -> %W8] GPR32
[%vreg35 -> %W8] GPR32
[%vreg36 -> %X8] GPR64
[%vreg37 -> %X8] GPR64common
[%vreg38 -> %X8] GPR64
[%vreg39 -> %X8] GPR64common
[%vreg40 -> %X8] GPR64common
[%vreg41 -> %W8] GPR32
[%vreg42 -> %W8] GPR32common
[%vreg43 -> %X8] GPR64common
[%vreg44 -> %W9] GPR32
[%vreg45 -> %W8] GPR32
[%vreg46 -> %W8] GPR32
[%vreg47 -> %X8] GPR64common
[%vreg48 -> %X8] GPR64common
[%vreg49 -> %X8] GPR64
[%vreg51 -> %W9] GPR32
[%vreg52 -> %X8] GPR64common
[%vreg53 -> %X8] GPR64
[%vreg55 -> %X9] GPR64
[%vreg56 -> %X8] GPR64
[%vreg57 -> %X8] GPR64
[%vreg58 -> %X9] GPR64
[%vreg59 -> %X8] GPR64
[%vreg60 -> %X10] GPR64
[%vreg61 -> %X8] GPR64common
[%vreg62 -> %X0] GPR64sp
[%vreg63 -> %X0] GPR64
[%vreg64 -> %X8] GPR64
[%vreg65 -> %X8] GPR64
[%vreg66 -> %X9] GPR64common
[%vreg67 -> %X8] GPR64common
[%vreg68 -> %X8] GPR64common
[%vreg69 -> %X9] GPR64
[%vreg70 -> %X8] GPR64
[%vreg71 -> %X21] GPR64
[%vreg72 -> %X20] GPR64
[%vreg74 -> %X2] GPR64all
[%vreg75 -> %W8] GPR32
[%vreg76 -> %X9] GPR64common
[%vreg77 -> %X8] GPR64common
[%vreg78 -> %W9] GPR32
[%vreg79 -> %X8] GPR64common
[%vreg80 -> %W8] GPR32
[%vreg81 -> %X9] GPR64common
[%vreg82 -> %W8] GPR32common
[%vreg83 -> %X8] GPR64
[%vreg84 -> %X9] GPR64common
[%vreg85 -> %X8] GPR64
[%vreg86 -> %X9] GPR64common
[%vreg87 -> %X8] GPR64
[%vreg88 -> %X0] GPR64
[%vreg89 -> %X1] GPR64
[%vreg90 -> %X2] GPR64
[%vreg91 -> %X8] GPR64
[%vreg92 -> %X0] GPR64
[%vreg93 -> %X1] GPR64
[%vreg94 -> %X8] GPR64common
[%vreg95 -> %W9] GPR32
[%vreg96 -> %X8] GPR64
[%vreg97 -> %X9] GPR64common
[%vreg98 -> %X8] GPR64common
[%vreg99 -> %W9] GPR32
[%vreg100 -> %X8] GPR64
[%vreg101 -> %X9] GPR64common
[%vreg102 -> %X8] GPR64
[%vreg103 -> %X9] GPR64common
[%vreg104 -> %W8] GPR32
[%vreg105 -> %W8] GPR32
[%vreg106 -> %X9] GPR64common
[%vreg107 -> %X8] GPR64common
[%vreg108 -> %X0] GPR64sp
[%vreg109 -> %X8] GPR64common
[%vreg110 -> %X0] GPR64sp
[%vreg111 -> %W0] GPR32
[%vreg113 -> %X9] GPR64
[%vreg116 -> %X8] GPR64common
[%vreg117 -> %W9] GPR32
[%vreg119 -> %X8] GPR64common
[%vreg120 -> %W8] GPR32
[%vreg122 -> %X8] GPR64
[%vreg123 -> %X8] GPR64common
[%vreg124 -> %X9] GPR64common
[%vreg125 -> %X9] GPR64common
[%vreg126 -> %X8] GPR64
[%vreg127 -> %X0] GPR64
[%vreg128 -> %X1] GPR64
[%vreg129 -> %X2] GPR64
[%vreg130 -> %X8] GPR64common
[%vreg131 -> %X8] GPR64
[%vreg132 -> %X8] GPR64common
[%vreg133 -> %X1] GPR64sp
[%vreg134 -> %X2] GPR64common
[%vreg135 -> %W3] GPR32
[%vreg136 -> %W9] GPR32
[%vreg137 -> %W6] GPR32sp
[%vreg140 -> %X8] GPR64
[%vreg141 -> %X8] GPR64common
[%vreg142 -> %X1] GPR64sp
[%vreg143 -> %X2] GPR64common
[%vreg144 -> %W3] GPR32
[%vreg145 -> %W9] GPR32
[%vreg146 -> %W6] GPR32sp
[%vreg149 -> %X8] GPR64common
[%vreg150 -> %X1] GPR64sp
[%vreg151 -> %X2] GPR64common
[%vreg152 -> %W3] GPR32
[%vreg153 -> %W9] GPR32
[%vreg154 -> %W6] GPR32sp
[%vreg157 -> %X8] GPR64common
[%vreg158 -> %W9] GPR32common
[%vreg159 -> %W9] GPR32common
[%vreg160 -> %X8] GPR64common
[%vreg161 -> %W9] GPR32common
[%vreg162 -> %W9] GPR32common
[%vreg163 -> %X8] GPR64common
[%vreg164 -> %X0] GPR64sp
[%vreg165 -> %X9] GPR64common
[%vreg166 -> %W11] GPR32
[%vreg167 -> %X8] GPR64common
[%vreg168 -> %W8] GPR32
[%vreg169 -> %W8] GPR32
[%vreg170 -> %W8] GPR32common
[%vreg171 -> %W8] GPR32
[%vreg172 -> %W9] GPR32
[%vreg173 -> %W8] GPR32
[%vreg174 -> %W8] GPR32
[%vreg175 -> %X10] GPR64common
[%vreg176 -> %X0] GPR64sp
[%vreg177 -> %W8] GPR32
[%vreg178 -> %X8] GPR64common
[%vreg179 -> %X0] GPR64sp
[%vreg181 -> %X8] GPR64common
[%vreg182 -> %X0] GPR64sp
[%vreg183 -> %X8] GPR64common
[%vreg184 -> %X0] GPR64sp
[%vreg185 -> %X0] GPR64
[%vreg186 -> %X0] GPR64
[%vreg187 -> %W8] GPR32
[%vreg188 -> %X8] GPR64common
[%vreg189 -> %X8] GPR64
[%vreg190 -> %X8] GPR64common
[%vreg191 -> %X8] GPR64common
[%vreg192 -> %X8] GPR64
[%vreg193 -> %X0] GPR64
[%vreg194 -> %X8] GPR64common
[%vreg195 -> %X20] GPR64
[%vreg197 -> %X2] GPR64all
[%vreg199 -> %W9] GPR32
[%vreg200 -> %X8] GPR64common
[%vreg201 -> %X8] GPR64
[%vreg203 -> %X8] GPR64common
[%vreg204 -> %X8] GPR64common
[%vreg205 -> %W8] GPR32
[%vreg206 -> %W9] GPR32common
[%vreg208 -> %W8] GPR32
[%vreg210 -> %W8] GPR32common
[%vreg211 -> %W9] GPR32
[%vreg212 -> %X10] GPR64common
[%vreg213 -> %X8] GPR64
[%vreg214 -> %X8] GPR64common
[%vreg215 -> %X8] GPR64common
[%vreg216 -> %W8] GPR32
[%vreg217 -> %W8] GPR32common
[%vreg218 -> %X9] GPR64common
[%vreg219 -> %X8] GPR64common
[%vreg220 -> %X8] GPR64
[%vreg221 -> %X8] GPR64common
[%vreg222 -> %X9] GPR64common
[%vreg223 -> %X8] GPR64
[%vreg224 -> %X8] GPR64
[%vreg225 -> %X0] GPR64
[%vreg226 -> %X9] GPR64
[%vreg227 -> %X10] GPR64
[%vreg228 -> %X9] GPR64common
[%vreg229 -> %X8] GPR64
[%vreg230 -> %X8] GPR64common
[%vreg231 -> %X8] GPR64common
[%vreg232 -> %X9] GPR64
[%vreg233 -> %X8] GPR64
[%vreg234 -> %X9] GPR64common
[%vreg235 -> %X8] GPR64common
[%vreg236 -> %X8] GPR64
[%vreg237 -> %X9] GPR64
[%vreg238 -> %X0] GPR64
[%vreg239 -> %X10] GPR64
[%vreg240 -> %X1] GPR64
[%vreg241 -> %X8] GPR64
[%vreg242 -> %X0] GPR64
[%vreg243 -> %X8] GPR64
[%vreg244 -> %X8] GPR64sp
[%vreg245 -> %X0] GPR64sp
[%vreg247 -> %W0] GPR32
[%vreg248 -> %X8] GPR64common
[%vreg249 -> %X0] GPR64sp
[%vreg250 -> %X8] GPR64sp
[%vreg251 -> %X0] GPR64sp
[%vreg252 -> %X8] GPR64common
[%vreg253 -> %X0] GPR64sp
[%vreg255 -> %W8] GPR32
[%vreg256 -> %W8] GPR32common


*** Stack slot copies ***

Stack slot -1:
  %vreg12<def> = LDRWui <fi#-1>, 0; mem:LD4[FixedStack-1] GPR32:%vreg12
Stack slot 0:
  STRXui %vreg4, <fi#0>, 0; mem:ST8[%fn.addr] GPR64:%vreg4
  %vreg241<def> = LDRXui <fi#0>, 0; mem:LD8[%fn.addr] GPR64:%vreg241
  %vreg224<def> = LDRXui <fi#0>, 0; mem:LD8[%fn.addr] GPR64:%vreg224
  %vreg100<def> = LDRXui <fi#0>, 0; mem:LD8[%fn.addr] GPR64:%vreg100
Stack slot 1:
  STRXui %vreg5, <fi#1>, 0; mem:ST8[%data.addr] GPR64:%vreg5
  %vreg240<def> = LDRXui <fi#1>, 0; mem:LD8[%data.addr] GPR64:%vreg240
  %vreg225<def> = LDRXui <fi#1>, 0; mem:LD8[%data.addr] GPR64:%vreg225
  %vreg93<def> = LDRXui <fi#1>, 0; mem:LD8[%data.addr] GPR64:%vreg93
  %vreg89<def> = LDRXui <fi#1>, 0; mem:LD8[%data.addr] GPR64:%vreg89
Stack slot 2:
  STRXui %vreg6, <fi#2>, 0; mem:ST8[%cpyfn.addr] GPR64:%vreg6
  %vreg223<def> = LDRXui <fi#2>, 0; mem:LD8[%cpyfn.addr] GPR64:%vreg223
  %vreg239<def> = LDRXui <fi#2>, 0; mem:LD8[%cpyfn.addr] GPR64:%vreg239
  %vreg87<def> = LDRXui <fi#2>, 0; mem:LD8[%cpyfn.addr] GPR64:%vreg87
  %vreg91<def> = LDRXui <fi#2>, 0; mem:LD8[%cpyfn.addr] GPR64:%vreg91
Stack slot 3:
  STRXui %vreg7, <fi#3>, 0; mem:ST8[%arg_size.addr] GPR64:%vreg7
  %vreg226<def> = LDRXui <fi#3>, 0; mem:LD8[%arg_size.addr] GPR64:%vreg226
  %vreg58<def> = LDRXui <fi#3>, 0; mem:LD8[%arg_size.addr] GPR64:%vreg58
  %vreg90<def> = LDRXui <fi#3>, 0; mem:LD8[%arg_size.addr] GPR64:%vreg90
Stack slot 4:
  STRXui %vreg8, <fi#4>, 0; mem:ST8[%arg_align.addr] GPR64:%vreg8
  %vreg227<def> = LDRXui <fi#4>, 0; mem:LD8[%arg_align.addr] GPR64:%vreg227
  %vreg234<def> = LDRXui <fi#4>, 0; mem:LD8[%arg_align.addr] GPR64common:%vreg234
  %vreg60<def> = LDRXui <fi#4>, 0; mem:LD8[%arg_align.addr] GPR64:%vreg60
  %vreg66<def> = LDRXui <fi#4>, 0; mem:LD8[%arg_align.addr] GPR64common:%vreg66
Stack slot 6:
  STRWui %vreg10, <fi#6>, 0; mem:ST4[%flags.addr] GPR32:%vreg10
  %vreg104<def> = LDRWui <fi#6>, 0; mem:LD4[%flags.addr] GPR32:%vreg104
Stack slot 7:
  STRXui %vreg11, <fi#7>, 0; mem:ST8[%depend.addr] GPR64:%vreg11
  %vreg193<def> = LDRXui <fi#7>, 0; mem:LD8[%depend.addr] GPR64:%vreg193
  %vreg52<def> = LDRXui <fi#7>, 0; mem:LD8[%depend.addr] GPR64common:%vreg52
  %vreg129<def> = LDRXui <fi#7>, 0; mem:LD8[%depend.addr] GPR64:%vreg129
Stack slot 8:
  STRWui %vreg12, <fi#8>, 0; mem:ST4[%priority.addr] GPR32:%vreg12
  %vreg28<def> = LDRWui <fi#8>, 0; mem:LD4[%priority.addr] GPR32:%vreg28
  STRWui %vreg33, <fi#8>, 0; mem:ST4[%priority.addr] GPR32:%vreg33
  %vreg211<def> = LDRWui <fi#8>, 0; mem:LD4[%priority.addr] GPR32:%vreg211
  %vreg75<def> = LDRWui <fi#8>, 0; mem:LD4[%priority.addr] GPR32:%vreg75
  %vreg135<def> = LDRWui <fi#8>, 0; mem:LD4[%priority.addr] GPR32:%vreg135
  %vreg144<def> = LDRWui <fi#8>, 0; mem:LD4[%priority.addr] GPR32:%vreg144
  %vreg152<def> = LDRWui <fi#8>, 0; mem:LD4[%priority.addr] GPR32:%vreg152
Stack slot 9:
  STRXui %vreg15, <fi#9>, 0; mem:ST8[%thr] GPR64common:%vreg15
  %vreg20<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg20
  %vreg23<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg23
  %vreg37<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg37
  %vreg39<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg39
  %vreg188<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg188
  %vreg190<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg190
  %vreg194<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg194
  %vreg200<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg200
  %vreg203<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg203
  %vreg212<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg212
  %vreg214<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg214
  %vreg218<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg218
  %vreg221<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg221
  %vreg47<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg47
  %vreg86<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg86
  %vreg97<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg97
Stack slot 10:
  STRXui %vreg16, <fi#10>, 0; mem:ST8[%team] GPR64:%vreg16
  %vreg17<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg17
  %vreg36<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64:%vreg36
  %vreg43<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg43
  %vreg248<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg248
  %vreg252<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg252
  %vreg107<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg107
  %vreg109<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg109
  %vreg183<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg183
  %vreg181<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg181
  %vreg149<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg149
  %vreg157<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg157
  %vreg160<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg160
  %vreg163<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg163
  %vreg165<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg165
  %vreg175<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg175
  %vreg178<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg178
Stack slot 12:
  STRXui %vreg229, <fi#12>, 0; mem:ST8[%saved_stack] GPR64:%vreg229
  %vreg243<def> = LDRXui <fi#12>, 0; mem:LD8[%saved_stack] GPR64:%vreg243
Stack slot 13:
  STRXui %vreg238, <fi#13>, 0; mem:ST8[%arg] GPR64:%vreg238
  %vreg242<def> = LDRXui <fi#13>, 0; mem:LD8[%arg] GPR64:%vreg242
Stack slot 14:
  STRXui %vreg63, <fi#14>, 0; mem:ST8[%task77] GPR64:%vreg63
  %vreg71<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64:%vreg71
  %vreg76<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64common:%vreg76
  %vreg77<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64common:%vreg77
  %vreg81<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64common:%vreg81
  %vreg84<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64common:%vreg84
  %vreg85<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64:%vreg85
  %vreg94<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64common:%vreg94
  %vreg98<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64common:%vreg98
  %vreg101<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64common:%vreg101
  %vreg103<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64common:%vreg103
  %vreg106<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64common:%vreg106
  %vreg119<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64common:%vreg119
  %vreg185<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64:%vreg185
  %vreg186<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64:%vreg186
  %vreg127<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64:%vreg127
  %vreg130<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64common:%vreg130
  %vreg134<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64common:%vreg134
  %vreg143<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64common:%vreg143
  %vreg151<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64common:%vreg151
Stack slot 15:
  STRXui %vreg48, <fi#15>, 0; mem:ST8[%parent] GPR64common:%vreg48
  %vreg72<def> = LDRXui <fi#15>, 0; mem:LD8[%parent] GPR64:%vreg72
  %vreg79<def> = LDRXui <fi#15>, 0; mem:LD8[%parent] GPR64common:%vreg79
  %vreg96<def> = LDRXui <fi#15>, 0; mem:LD8[%parent] GPR64:%vreg96
  %vreg128<def> = LDRXui <fi#15>, 0; mem:LD8[%parent] GPR64:%vreg128
  %vreg132<def> = LDRXui <fi#15>, 0; mem:LD8[%parent] GPR64common:%vreg132
  %vreg167<def> = LDRXui <fi#15>, 0; mem:LD8[%parent] GPR64common:%vreg167
Stack slot 16:
  STRXui %vreg49, <fi#16>, 0; mem:ST8[%taskgroup79] GPR64:%vreg49
  %vreg83<def> = LDRXui <fi#16>, 0; mem:LD8[%taskgroup79] GPR64:%vreg83
  %vreg113<def> = LDRXui <fi#16>, 0; mem:LD8[%taskgroup79] GPR64:%vreg113
  %vreg116<def> = LDRXui <fi#16>, 0; mem:LD8[%taskgroup79] GPR64common:%vreg116
  %vreg122<def> = LDRXui <fi#16>, 0; mem:LD8[%taskgroup79] GPR64:%vreg122
  %vreg123<def> = LDRXui <fi#16>, 0; mem:LD8[%taskgroup79] GPR64common:%vreg123
  %vreg140<def> = LDRXui <fi#16>, 0; mem:LD8[%taskgroup79] GPR64:%vreg140
  %vreg141<def> = LDRXui <fi#16>, 0; mem:LD8[%taskgroup79] GPR64common:%vreg141
Stack slot 17:
  STRXui %vreg70, <fi#17>, 0; mem:ST8[%arg81] GPR64:%vreg70
  %vreg92<def> = LDRXui <fi#17>, 0; mem:LD8[%arg81] GPR64:%vreg92
  %vreg88<def> = LDRXui <fi#17>, 0; mem:LD8[%arg81] GPR64:%vreg88
  %vreg102<def> = LDRXui <fi#17>, 0; mem:LD8[%arg81] GPR64:%vreg102
Stack slot 19:
  STRXui %vreg56, <fi#19>, 0; mem:ST8[%depend_size] GPR64:%vreg56
  %vreg57<def> = LDRXui <fi#19>, 0; mem:LD8[%depend_size] GPR64:%vreg57
  %vreg64<def> = LDRXui <fi#19>, 0; mem:LD8[%depend_size] GPR64:%vreg64
  %vreg126<def> = LDRXui <fi#19>, 0; mem:LD8[%depend_size] GPR64:%vreg126

Stackmap 0:
  STACKMAP 0, 0, %vreg8, %vreg7, %vreg6, %vreg5, %vreg11, %vreg10, %vreg4, %vreg13, %vreg12, ...; GPR64:%vreg8,%vreg7,%vreg6,%vreg5,%vreg11,%vreg4 GPR32:%vreg10,%vreg12 GPR32common:%vreg13

i64 %arg_align: in register %X22 (vreg 8)
i64 %arg_size: in register %X23 (vreg 7)
void (i8*, i8*)* %cpyfn: in register %X24 (vreg 6)
i8* %data: in register %X25 (vreg 5)
i8** %depend: in register %X20 (vreg 11)
i32 %flags: in register %W21 (vreg 10)
void (i8*)* %fn: in register %X26 (vreg 4)
i1 %if_clause: in register %W28 (vreg 13)
i32 %priority: in register %W27 (vreg 12)

Unwinding stackmap back to call site:

  - Skipping   ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
  - Skipping   ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, 0, <fi#13>, 0, 0, <fi#17>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#19>, 0, 0, <fi#18>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#5>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#12>, 0, 0, <fi#11>, 0, 0, <fi#14>, 0, 0, <fi#16>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack13] LD8[FixedStack17] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack2] LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack19] LD8[FixedStack18](align=1) LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack5](align=1) LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack12] LD8[FixedStack11] LD8[FixedStack14] LD8[FixedStack16] LD8[FixedStack10] LD8[FixedStack9]

i8** %arg: in stack slot 13 (size: 8)
i8** %arg81: in stack slot 17 (size: 8)
i64* %arg_align.addr: in stack slot 4 (size: 8)
i64* %arg_size.addr: in stack slot 3 (size: 8)
void (i8*, i8*)** %cpyfn.addr: in stack slot 2 (size: 8)
i8** %data.addr: in stack slot 1 (size: 8)
i8*** %depend.addr: in stack slot 7 (size: 8)
i64* %depend_size: in stack slot 19 (size: 8)
i8* %do_wake: in stack slot 18 (size: 1)
i32* %flags.addr: in stack slot 6 (size: 4)
void (i8*)** %fn.addr: in stack slot 0 (size: 8)
i8* %if_clause.addr: in stack slot 5 (size: 1)
%struct.gomp_task** %parent: in stack slot 15 (size: 8)
i32* %priority.addr: in stack slot 8 (size: 4)
i8** %saved_stack: in stack slot 12 (size: 8)
%struct.gomp_task* %task25: in stack slot 11 (size: 208)
%struct.gomp_task** %task77: in stack slot 14 (size: 8)
%struct.gomp_taskgroup** %taskgroup79: in stack slot 16 (size: 8)
%struct.gomp_team** %team: in stack slot 10 (size: 8)
%struct.gomp_thread** %thr: in stack slot 9 (size: 8)

Unwinding stackmap back to call site:

  - Skipping   ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
  - Skipping   ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>

Duplicate operand locations:


Stackmap 2:
  STACKMAP 2, 0, 0, <fi#13>, 0, 0, <fi#17>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#19>, 0, 0, <fi#18>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#5>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#12>, 0, 0, <fi#11>, 0, 0, <fi#14>, 0, 0, <fi#16>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack13] LD8[FixedStack17] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack2] LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack19] LD8[FixedStack18](align=1) LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack5](align=1) LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack12] LD8[FixedStack11] LD8[FixedStack14] LD8[FixedStack16] LD8[FixedStack10] LD8[FixedStack9]

i8** %arg: in stack slot 13 (size: 8)
i8** %arg81: in stack slot 17 (size: 8)
i64* %arg_align.addr: in stack slot 4 (size: 8)
i64* %arg_size.addr: in stack slot 3 (size: 8)
void (i8*, i8*)** %cpyfn.addr: in stack slot 2 (size: 8)
i8** %data.addr: in stack slot 1 (size: 8)
i8*** %depend.addr: in stack slot 7 (size: 8)
i64* %depend_size: in stack slot 19 (size: 8)
i8* %do_wake: in stack slot 18 (size: 1)
i32* %flags.addr: in stack slot 6 (size: 4)
void (i8*)** %fn.addr: in stack slot 0 (size: 8)
i8* %if_clause.addr: in stack slot 5 (size: 1)
%struct.gomp_task** %parent: in stack slot 15 (size: 8)
i32* %priority.addr: in stack slot 8 (size: 4)
i8** %saved_stack: in stack slot 12 (size: 8)
%struct.gomp_task* %task25: in stack slot 11 (size: 208)
%struct.gomp_task** %task77: in stack slot 14 (size: 8)
%struct.gomp_taskgroup** %taskgroup79: in stack slot 16 (size: 8)
%struct.gomp_team** %team: in stack slot 10 (size: 8)
%struct.gomp_thread** %thr: in stack slot 9 (size: 8)

Unwinding stackmap back to call site:

  - Skipping   ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
  - Skipping   ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>

Duplicate operand locations:


Stackmap 3:
  STACKMAP 3, 0, 0, <fi#13>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#8>, 0, 0, <fi#12>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack13] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack2] LD8[FixedStack1] LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack8](align=4) LD8[FixedStack12] LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack9]

i8** %arg: in stack slot 13 (size: 8)
i64* %arg_align.addr: in stack slot 4 (size: 8)
i64* %arg_size.addr: in stack slot 3 (size: 8)
void (i8*, i8*)** %cpyfn.addr: in stack slot 2 (size: 8)
i8** %data.addr: in stack slot 1 (size: 8)
i32* %flags.addr: in stack slot 6 (size: 4)
void (i8*)** %fn.addr: in stack slot 0 (size: 8)
i32* %priority.addr: in stack slot 8 (size: 4)
i8** %saved_stack: in stack slot 12 (size: 8)
%struct.gomp_task* %task25: in stack slot 11 (size: 208)
%struct.gomp_team** %team: in stack slot 10 (size: 8)
%struct.gomp_thread** %thr: in stack slot 9 (size: 8)

Unwinding stackmap back to call site:

  - Skipping   ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
  - Skipping   ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>

Duplicate operand locations:


Stackmap 4:
  STACKMAP 4, 0, 0, <fi#13>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#8>, 0, 0, <fi#12>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, %vreg195, ...; mem:LD8[FixedStack13] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack2] LD8[FixedStack1] LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack8](align=4) LD8[FixedStack12] LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack9] GPR64:%vreg195

i8** %arg: in stack slot 13 (size: 8)
i64* %arg_align.addr: in stack slot 4 (size: 8)
i64* %arg_size.addr: in stack slot 3 (size: 8)
void (i8*, i8*)** %cpyfn.addr: in stack slot 2 (size: 8)
i8** %data.addr: in stack slot 1 (size: 8)
i32* %flags.addr: in stack slot 6 (size: 4)
void (i8*)** %fn.addr: in stack slot 0 (size: 8)
i32* %priority.addr: in stack slot 8 (size: 4)
i8** %saved_stack: in stack slot 12 (size: 8)
%struct.gomp_task* %task25: in stack slot 11 (size: 208)
%struct.gomp_team** %team: in stack slot 10 (size: 8)
%struct.gomp_thread** %thr: in stack slot 9 (size: 8)
%struct.gomp_task* %34: in register %X20 (vreg 195)

Unwinding stackmap back to call site:

  - Skipping   ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
  - Skipping   ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>

Duplicate operand locations:


Stackmap 5:
  STACKMAP 5, 0, 0, <fi#13>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#8>, 0, 0, <fi#12>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack13] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack2] LD8[FixedStack1] LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack8](align=4) LD8[FixedStack12] LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack9]

i8** %arg: in stack slot 13 (size: 8)
i64* %arg_align.addr: in stack slot 4 (size: 8)
i64* %arg_size.addr: in stack slot 3 (size: 8)
void (i8*, i8*)** %cpyfn.addr: in stack slot 2 (size: 8)
i8** %data.addr: in stack slot 1 (size: 8)
i32* %flags.addr: in stack slot 6 (size: 4)
void (i8*)** %fn.addr: in stack slot 0 (size: 8)
i32* %priority.addr: in stack slot 8 (size: 4)
i8** %saved_stack: in stack slot 12 (size: 8)
%struct.gomp_task* %task25: in stack slot 11 (size: 208)
%struct.gomp_team** %team: in stack slot 10 (size: 8)
%struct.gomp_thread** %thr: in stack slot 9 (size: 8)

Unwinding stackmap back to call site:

  - Skipping   ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
  - Skipping   ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>

Duplicate operand locations:


Stackmap 6:
  STACKMAP 6, 0, 0, <fi#13>, 0, 0, <fi#0>, 0, 0, <fi#12>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack13] LD8[FixedStack0] LD8[FixedStack12] LD8[FixedStack11] LD8[FixedStack10]

i8** %arg: in stack slot 13 (size: 8)
void (i8*)** %fn.addr: in stack slot 0 (size: 8)
i8** %saved_stack: in stack slot 12 (size: 8)
%struct.gomp_task* %task25: in stack slot 11 (size: 208)
%struct.gomp_team** %team: in stack slot 10 (size: 8)

Unwinding stackmap back to call site:

  - Skipping   ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
  - Skipping   ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>

Duplicate operand locations:


Stackmap 7:
  STACKMAP 7, 0, 0, <fi#12>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack12] LD8[FixedStack11] LD8[FixedStack10]

i8** %saved_stack: in stack slot 12 (size: 8)
%struct.gomp_task* %task25: in stack slot 11 (size: 208)
%struct.gomp_team** %team: in stack slot 10 (size: 8)

Unwinding stackmap back to call site:

  - Skipping   ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
  - Skipping   ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>

Duplicate operand locations:


Stackmap 8:
  STACKMAP 8, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack11] LD8[FixedStack10]

%struct.gomp_task* %task25: in stack slot 11 (size: 208)
%struct.gomp_team** %team: in stack slot 10 (size: 8)

Unwinding stackmap back to call site:

  - Skipping   ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
  - Skipping   ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>

Duplicate operand locations:


Stackmap 9:
  STACKMAP 9, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack11] LD8[FixedStack10]

%struct.gomp_task* %task25: in stack slot 11 (size: 208)
%struct.gomp_team** %team: in stack slot 10 (size: 8)

Unwinding stackmap back to call site:

  - Skipping   ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
  - Skipping   ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>

Duplicate operand locations:


Stackmap 10:
  STACKMAP 10, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack11] LD8[FixedStack10]

%struct.gomp_task* %task25: in stack slot 11 (size: 208)
%struct.gomp_team** %team: in stack slot 10 (size: 8)

Unwinding stackmap back to call site:

  - Skipping   ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
  - Skipping   ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>

Duplicate operand locations:


Stackmap 11:
  STACKMAP 11, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack10]

%struct.gomp_team** %team: in stack slot 10 (size: 8)

Unwinding stackmap back to call site:

  - Skipping   ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
  - Skipping   ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>

Duplicate operand locations:


Stackmap 12:
  STACKMAP 12, 0, ...


Unwinding stackmap back to call site:

  - Skipping   ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
  - Skipping   ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>

Duplicate operand locations:


Stackmap 13:
  STACKMAP 13, 0, ...


Unwinding stackmap back to call site:

  - Skipping   ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
  - Skipping   ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>

Duplicate operand locations:


Stackmap 14:
  STACKMAP 14, 0, 0, <fi#17>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#19>, 0, 0, <fi#18>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#14>, 0, 0, <fi#16>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack17] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack2] LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack19] LD8[FixedStack18](align=1) LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack14] LD8[FixedStack16] LD8[FixedStack10] LD8[FixedStack9]

i8** %arg81: in stack slot 17 (size: 8)
i64* %arg_align.addr: in stack slot 4 (size: 8)
i64* %arg_size.addr: in stack slot 3 (size: 8)
void (i8*, i8*)** %cpyfn.addr: in stack slot 2 (size: 8)
i8** %data.addr: in stack slot 1 (size: 8)
i8*** %depend.addr: in stack slot 7 (size: 8)
i64* %depend_size: in stack slot 19 (size: 8)
i8* %do_wake: in stack slot 18 (size: 1)
i32* %flags.addr: in stack slot 6 (size: 4)
void (i8*)** %fn.addr: in stack slot 0 (size: 8)
%struct.gomp_task** %parent: in stack slot 15 (size: 8)
i32* %priority.addr: in stack slot 8 (size: 4)
%struct.gomp_task** %task77: in stack slot 14 (size: 8)
%struct.gomp_taskgroup** %taskgroup79: in stack slot 16 (size: 8)
%struct.gomp_team** %team: in stack slot 10 (size: 8)
%struct.gomp_thread** %thr: in stack slot 9 (size: 8)

Unwinding stackmap back to call site:

  - Skipping   ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
  - Skipping   ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>

Duplicate operand locations:


Stackmap 15:
  STACKMAP 15, 0, 0, <fi#17>, 0, 0, <fi#3>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#19>, 0, 0, <fi#18>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#14>, 0, 0, <fi#16>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, %vreg71, %vreg72, ...; mem:LD8[FixedStack17] LD8[FixedStack3] LD8[FixedStack2] LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack19] LD8[FixedStack18](align=1) LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack14] LD8[FixedStack16] LD8[FixedStack10] LD8[FixedStack9] GPR64:%vreg71,%vreg72

i8** %arg81: in stack slot 17 (size: 8)
i64* %arg_size.addr: in stack slot 3 (size: 8)
void (i8*, i8*)** %cpyfn.addr: in stack slot 2 (size: 8)
i8** %data.addr: in stack slot 1 (size: 8)
i8*** %depend.addr: in stack slot 7 (size: 8)
i64* %depend_size: in stack slot 19 (size: 8)
i8* %do_wake: in stack slot 18 (size: 1)
i32* %flags.addr: in stack slot 6 (size: 4)
void (i8*)** %fn.addr: in stack slot 0 (size: 8)
%struct.gomp_task** %parent: in stack slot 15 (size: 8)
i32* %priority.addr: in stack slot 8 (size: 4)
%struct.gomp_task** %task77: in stack slot 14 (size: 8)
%struct.gomp_taskgroup** %taskgroup79: in stack slot 16 (size: 8)
%struct.gomp_team** %team: in stack slot 10 (size: 8)
%struct.gomp_thread** %thr: in stack slot 9 (size: 8)
%struct.gomp_task* %88: in register %X21 (vreg 71)
%struct.gomp_task* %89: in register %X20 (vreg 72)

Unwinding stackmap back to call site:

  - Skipping   ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
  - Skipping   ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>

Duplicate operand locations:


Stackmap 16:
  STACKMAP 16, 0, 0, <fi#17>, 0, 0, <fi#3>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#19>, 0, 0, <fi#18>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#14>, 0, 0, <fi#16>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack17] LD8[FixedStack3] LD8[FixedStack2] LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack19] LD8[FixedStack18](align=1) LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack14] LD8[FixedStack16] LD8[FixedStack10] LD8[FixedStack9]

i8** %arg81: in stack slot 17 (size: 8)
i64* %arg_size.addr: in stack slot 3 (size: 8)
void (i8*, i8*)** %cpyfn.addr: in stack slot 2 (size: 8)
i8** %data.addr: in stack slot 1 (size: 8)
i8*** %depend.addr: in stack slot 7 (size: 8)
i64* %depend_size: in stack slot 19 (size: 8)
i8* %do_wake: in stack slot 18 (size: 1)
i32* %flags.addr: in stack slot 6 (size: 4)
void (i8*)** %fn.addr: in stack slot 0 (size: 8)
%struct.gomp_task** %parent: in stack slot 15 (size: 8)
i32* %priority.addr: in stack slot 8 (size: 4)
%struct.gomp_task** %task77: in stack slot 14 (size: 8)
%struct.gomp_taskgroup** %taskgroup79: in stack slot 16 (size: 8)
%struct.gomp_team** %team: in stack slot 10 (size: 8)
%struct.gomp_thread** %thr: in stack slot 9 (size: 8)

Unwinding stackmap back to call site:

  - Skipping   ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
  - Skipping   ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>

Duplicate operand locations:


Stackmap 17:
  STACKMAP 17, 0, 0, <fi#17>, 0, 0, <fi#7>, 0, 0, <fi#19>, 0, 0, <fi#18>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#14>, 0, 0, <fi#16>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack17] LD8[FixedStack7] LD8[FixedStack19] LD8[FixedStack18](align=1) LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack14] LD8[FixedStack16] LD8[FixedStack10] LD8[FixedStack9]

i8** %arg81: in stack slot 17 (size: 8)
i8*** %depend.addr: in stack slot 7 (size: 8)
i64* %depend_size: in stack slot 19 (size: 8)
i8* %do_wake: in stack slot 18 (size: 1)
i32* %flags.addr: in stack slot 6 (size: 4)
void (i8*)** %fn.addr: in stack slot 0 (size: 8)
%struct.gomp_task** %parent: in stack slot 15 (size: 8)
i32* %priority.addr: in stack slot 8 (size: 4)
%struct.gomp_task** %task77: in stack slot 14 (size: 8)
%struct.gomp_taskgroup** %taskgroup79: in stack slot 16 (size: 8)
%struct.gomp_team** %team: in stack slot 10 (size: 8)
%struct.gomp_thread** %thr: in stack slot 9 (size: 8)

Unwinding stackmap back to call site:

  - Skipping   ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
  - Skipping   ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>

Duplicate operand locations:


Stackmap 18:
  STACKMAP 18, 0, 0, <fi#7>, 0, 0, <fi#19>, 0, 0, <fi#18>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#14>, 0, 0, <fi#16>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack7] LD8[FixedStack19] LD8[FixedStack18](align=1) LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack14] LD8[FixedStack16] LD8[FixedStack10]

i8*** %depend.addr: in stack slot 7 (size: 8)
i64* %depend_size: in stack slot 19 (size: 8)
i8* %do_wake: in stack slot 18 (size: 1)
%struct.gomp_task** %parent: in stack slot 15 (size: 8)
i32* %priority.addr: in stack slot 8 (size: 4)
%struct.gomp_task** %task77: in stack slot 14 (size: 8)
%struct.gomp_taskgroup** %taskgroup79: in stack slot 16 (size: 8)
%struct.gomp_team** %team: in stack slot 10 (size: 8)

Unwinding stackmap back to call site:

  - Skipping   ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
  - Skipping   ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>

Duplicate operand locations:


Stackmap 19:
  STACKMAP 19, 0, 0, <fi#7>, 0, 0, <fi#19>, 0, 0, <fi#18>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#14>, 0, 0, <fi#16>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack7] LD8[FixedStack19] LD8[FixedStack18](align=1) LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack14] LD8[FixedStack16] LD8[FixedStack10]

i8*** %depend.addr: in stack slot 7 (size: 8)
i64* %depend_size: in stack slot 19 (size: 8)
i8* %do_wake: in stack slot 18 (size: 1)
%struct.gomp_task** %parent: in stack slot 15 (size: 8)
i32* %priority.addr: in stack slot 8 (size: 4)
%struct.gomp_task** %task77: in stack slot 14 (size: 8)
%struct.gomp_taskgroup** %taskgroup79: in stack slot 16 (size: 8)
%struct.gomp_team** %team: in stack slot 10 (size: 8)

Unwinding stackmap back to call site:

  - Skipping   ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
  - Skipping   ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>

Duplicate operand locations:


Stackmap 20:
  STACKMAP 20, 0, 0, <fi#14>, 0, ...; mem:LD8[FixedStack14]

%struct.gomp_task** %task77: in stack slot 14 (size: 8)

Unwinding stackmap back to call site:

  - Skipping   ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
  - Skipping   ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>

Duplicate operand locations:


Stackmap 21:
  STACKMAP 21, 0, 0, <fi#14>, 0, ...; mem:LD8[FixedStack14]

%struct.gomp_task** %task77: in stack slot 14 (size: 8)

Unwinding stackmap back to call site:

  - Skipping   ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
  - Skipping   ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>

Duplicate operand locations:


Stackmap 22:
  STACKMAP 22, 0, ...


Unwinding stackmap back to call site:

  - Skipping   ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
  - Skipping   ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>

Duplicate operand locations:


Stackmap 23:
  STACKMAP 23, 0, 0, <fi#18>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#14>, 0, 0, <fi#16>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack18](align=1) LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack14] LD8[FixedStack16] LD8[FixedStack10]

i8* %do_wake: in stack slot 18 (size: 1)
%struct.gomp_task** %parent: in stack slot 15 (size: 8)
i32* %priority.addr: in stack slot 8 (size: 4)
%struct.gomp_task** %task77: in stack slot 14 (size: 8)
%struct.gomp_taskgroup** %taskgroup79: in stack slot 16 (size: 8)
%struct.gomp_team** %team: in stack slot 10 (size: 8)

Unwinding stackmap back to call site:

  - Skipping   ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
  - Skipping   ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>

Duplicate operand locations:


Stackmap 24:
  STACKMAP 24, 0, ...


Unwinding stackmap back to call site:

  - Skipping   ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
  - Skipping   ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>

Duplicate operand locations:


Stackmap 25:
  STACKMAP 25, 0, 0, <fi#18>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#14>, 0, 0, <fi#16>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack18](align=1) LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack14] LD8[FixedStack16] LD8[FixedStack10]

i8* %do_wake: in stack slot 18 (size: 1)
%struct.gomp_task** %parent: in stack slot 15 (size: 8)
i32* %priority.addr: in stack slot 8 (size: 4)
%struct.gomp_task** %task77: in stack slot 14 (size: 8)
%struct.gomp_taskgroup** %taskgroup79: in stack slot 16 (size: 8)
%struct.gomp_team** %team: in stack slot 10 (size: 8)

Unwinding stackmap back to call site:

  - Skipping   ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
  - Skipping   ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>

Duplicate operand locations:


Stackmap 26:
  STACKMAP 26, 0, 0, <fi#18>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#14>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack18](align=1) LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack14] LD8[FixedStack10]

i8* %do_wake: in stack slot 18 (size: 1)
%struct.gomp_task** %parent: in stack slot 15 (size: 8)
i32* %priority.addr: in stack slot 8 (size: 4)
%struct.gomp_task** %task77: in stack slot 14 (size: 8)
%struct.gomp_team** %team: in stack slot 10 (size: 8)

Unwinding stackmap back to call site:

  - Skipping   ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
  - Skipping   ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>

Duplicate operand locations:


Stackmap 27:
  STACKMAP 27, 0, 0, <fi#18>, 0, 0, <fi#15>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack18](align=1) LD8[FixedStack15] LD8[FixedStack10]

i8* %do_wake: in stack slot 18 (size: 1)
%struct.gomp_task** %parent: in stack slot 15 (size: 8)
%struct.gomp_team** %team: in stack slot 10 (size: 8)

Unwinding stackmap back to call site:

  - Skipping   ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
  - Skipping   ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>

Duplicate operand locations:


Stackmap 28:
  STACKMAP 28, 0, 0, <fi#18>, 0, 0, <fi#15>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack18](align=1) LD8[FixedStack15] LD8[FixedStack10]

i8* %do_wake: in stack slot 18 (size: 1)
%struct.gomp_task** %parent: in stack slot 15 (size: 8)
%struct.gomp_team** %team: in stack slot 10 (size: 8)

Unwinding stackmap back to call site:

  - Skipping   ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
  - Skipping   ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>

Duplicate operand locations:


Stackmap 29:
  STACKMAP 29, 0, 0, <fi#18>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack18](align=1) LD8[FixedStack10]

i8* %do_wake: in stack slot 18 (size: 1)
%struct.gomp_team** %team: in stack slot 10 (size: 8)

Unwinding stackmap back to call site:

  - Skipping   ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
  - Skipping   ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>

Duplicate operand locations:


Stackmap 30:
  STACKMAP 30, 0, ...


Unwinding stackmap back to call site:

  - Skipping   ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
  - Skipping   ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>

Duplicate operand locations:


Stackmap 31:
  STACKMAP 31, 0, ...


Unwinding stackmap back to call site:

  - Skipping   ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
  - Skipping   ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>

Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, %vreg8, %vreg7, %vreg6, %vreg5, %vreg11, %vreg10, %vreg4, %vreg13, %vreg12, ...; GPR64:%vreg8,%vreg7,%vreg6,%vreg5,%vreg11,%vreg4 GPR32:%vreg10,%vreg12 GPR32common:%vreg13
  -> Call instruction SlotIndex 240B, searching vregs 0 -> 257 and stack slots -1 -> 21

  STACKMAP 1, 0, 0, <fi#13>, 0, 0, <fi#17>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#19>, 0, 0, <fi#18>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#5>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#12>, 0, 0, <fi#11>, 0, 0, <fi#14>, 0, 0, <fi#16>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack13] LD8[FixedStack17] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack2] LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack19] LD8[FixedStack18](align=1) LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack5](align=1) LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack12] LD8[FixedStack11] LD8[FixedStack14] LD8[FixedStack16] LD8[FixedStack10] LD8[FixedStack9]
  -> Call instruction SlotIndex 480B, searching vregs 0 -> 257 and stack slots -1 -> 21

  STACKMAP 2, 0, 0, <fi#13>, 0, 0, <fi#17>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#19>, 0, 0, <fi#18>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#5>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#12>, 0, 0, <fi#11>, 0, 0, <fi#14>, 0, 0, <fi#16>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack13] LD8[FixedStack17] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack2] LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack19] LD8[FixedStack18](align=1) LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack5](align=1) LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack12] LD8[FixedStack11] LD8[FixedStack14] LD8[FixedStack16] LD8[FixedStack10] LD8[FixedStack9]
  -> Call instruction SlotIndex 736B, searching vregs 0 -> 257 and stack slots -1 -> 21

  STACKMAP 3, 0, 0, <fi#13>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#8>, 0, 0, <fi#12>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack13] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack2] LD8[FixedStack1] LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack8](align=4) LD8[FixedStack12] LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack9]
  -> Call instruction SlotIndex 2192B, searching vregs 0 -> 257 and stack slots -1 -> 21

  STACKMAP 4, 0, 0, <fi#13>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#8>, 0, 0, <fi#12>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, %vreg195, ...; mem:LD8[FixedStack13] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack2] LD8[FixedStack1] LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack8](align=4) LD8[FixedStack12] LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack9] GPR64:%vreg195
  -> Call instruction SlotIndex 2384B, searching vregs 0 -> 257 and stack slots -1 -> 21

  STACKMAP 5, 0, 0, <fi#13>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#8>, 0, 0, <fi#12>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack13] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack2] LD8[FixedStack1] LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack8](align=4) LD8[FixedStack12] LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack9]
  -> Call instruction SlotIndex 2560B, searching vregs 0 -> 257 and stack slots -1 -> 21

  STACKMAP 6, 0, 0, <fi#13>, 0, 0, <fi#0>, 0, 0, <fi#12>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack13] LD8[FixedStack0] LD8[FixedStack12] LD8[FixedStack11] LD8[FixedStack10]
  -> Call instruction SlotIndex 3832B, searching vregs 0 -> 257 and stack slots -1 -> 21

  STACKMAP 7, 0, 0, <fi#12>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack12] LD8[FixedStack11] LD8[FixedStack10]
  -> Call instruction SlotIndex 3968B, searching vregs 0 -> 257 and stack slots -1 -> 21

  STACKMAP 8, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack11] LD8[FixedStack10]
  -> Call instruction SlotIndex 4176B, searching vregs 0 -> 257 and stack slots -1 -> 21

  STACKMAP 9, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack11] LD8[FixedStack10]
  -> Call instruction SlotIndex 4384B, searching vregs 0 -> 257 and stack slots -1 -> 21

  STACKMAP 10, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack11] LD8[FixedStack10]
  -> Call instruction SlotIndex 4592B, searching vregs 0 -> 257 and stack slots -1 -> 21

  STACKMAP 11, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack10]
  -> Call instruction SlotIndex 4736B, searching vregs 0 -> 257 and stack slots -1 -> 21

  STACKMAP 12, 0, ...
  -> Call instruction SlotIndex 4880B, searching vregs 0 -> 257 and stack slots -1 -> 21

  STACKMAP 13, 0, ...
  -> Call instruction SlotIndex 5008B, searching vregs 0 -> 257 and stack slots -1 -> 21

  STACKMAP 14, 0, 0, <fi#17>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#19>, 0, 0, <fi#18>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#14>, 0, 0, <fi#16>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack17] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack2] LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack19] LD8[FixedStack18](align=1) LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack14] LD8[FixedStack16] LD8[FixedStack10] LD8[FixedStack9]
  -> Call instruction SlotIndex 5552B, searching vregs 0 -> 257 and stack slots -1 -> 21

  STACKMAP 15, 0, 0, <fi#17>, 0, 0, <fi#3>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#19>, 0, 0, <fi#18>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#14>, 0, 0, <fi#16>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, %vreg71, %vreg72, ...; mem:LD8[FixedStack17] LD8[FixedStack3] LD8[FixedStack2] LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack19] LD8[FixedStack18](align=1) LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack14] LD8[FixedStack16] LD8[FixedStack10] LD8[FixedStack9] GPR64:%vreg71,%vreg72
  -> Call instruction SlotIndex 5896B, searching vregs 0 -> 257 and stack slots -1 -> 21

  STACKMAP 16, 0, 0, <fi#17>, 0, 0, <fi#3>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#19>, 0, 0, <fi#18>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#14>, 0, 0, <fi#16>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack17] LD8[FixedStack3] LD8[FixedStack2] LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack19] LD8[FixedStack18](align=1) LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack14] LD8[FixedStack16] LD8[FixedStack10] LD8[FixedStack9]
  -> Call instruction SlotIndex 6032B, searching vregs 0 -> 257 and stack slots -1 -> 21

  STACKMAP 17, 0, 0, <fi#17>, 0, 0, <fi#7>, 0, 0, <fi#19>, 0, 0, <fi#18>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#14>, 0, 0, <fi#16>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack17] LD8[FixedStack7] LD8[FixedStack19] LD8[FixedStack18](align=1) LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack14] LD8[FixedStack16] LD8[FixedStack10] LD8[FixedStack9]
  -> Call instruction SlotIndex 6544B, searching vregs 0 -> 257 and stack slots -1 -> 21

  STACKMAP 18, 0, 0, <fi#7>, 0, 0, <fi#19>, 0, 0, <fi#18>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#14>, 0, 0, <fi#16>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack7] LD8[FixedStack19] LD8[FixedStack18](align=1) LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack14] LD8[FixedStack16] LD8[FixedStack10]
  -> Call instruction SlotIndex 7200B, searching vregs 0 -> 257 and stack slots -1 -> 21

  STACKMAP 19, 0, 0, <fi#7>, 0, 0, <fi#19>, 0, 0, <fi#18>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#14>, 0, 0, <fi#16>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack7] LD8[FixedStack19] LD8[FixedStack18](align=1) LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack14] LD8[FixedStack16] LD8[FixedStack10]
  -> Call instruction SlotIndex 7344B, searching vregs 0 -> 257 and stack slots -1 -> 21

  STACKMAP 20, 0, 0, <fi#14>, 0, ...; mem:LD8[FixedStack14]
  -> Call instruction SlotIndex 7968B, searching vregs 0 -> 257 and stack slots -1 -> 21

  STACKMAP 21, 0, 0, <fi#14>, 0, ...; mem:LD8[FixedStack14]
  -> Call instruction SlotIndex 8096B, searching vregs 0 -> 257 and stack slots -1 -> 21

  STACKMAP 22, 0, ...
  -> Call instruction SlotIndex 8224B, searching vregs 0 -> 257 and stack slots -1 -> 21

  STACKMAP 23, 0, 0, <fi#18>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#14>, 0, 0, <fi#16>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack18](align=1) LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack14] LD8[FixedStack16] LD8[FixedStack10]
  -> Call instruction SlotIndex 8672B, searching vregs 0 -> 257 and stack slots -1 -> 21

  STACKMAP 24, 0, ...
  -> Call instruction SlotIndex 8896B, searching vregs 0 -> 257 and stack slots -1 -> 21

  STACKMAP 25, 0, 0, <fi#18>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#14>, 0, 0, <fi#16>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack18](align=1) LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack14] LD8[FixedStack16] LD8[FixedStack10]
  -> Call instruction SlotIndex 9296B, searching vregs 0 -> 257 and stack slots -1 -> 21

  STACKMAP 26, 0, 0, <fi#18>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#14>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack18](align=1) LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack14] LD8[FixedStack10]
  -> Call instruction SlotIndex 9696B, searching vregs 0 -> 257 and stack slots -1 -> 21

  STACKMAP 27, 0, 0, <fi#18>, 0, 0, <fi#15>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack18](align=1) LD8[FixedStack15] LD8[FixedStack10]
  -> Call instruction SlotIndex 10064B, searching vregs 0 -> 257 and stack slots -1 -> 21

  STACKMAP 28, 0, 0, <fi#18>, 0, 0, <fi#15>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack18](align=1) LD8[FixedStack15] LD8[FixedStack10]
  -> Call instruction SlotIndex 10336B, searching vregs 0 -> 257 and stack slots -1 -> 21

  STACKMAP 29, 0, 0, <fi#18>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack18](align=1) LD8[FixedStack10]
  -> Call instruction SlotIndex 10680B, searching vregs 0 -> 257 and stack slots -1 -> 21

  STACKMAP 30, 0, ...
  -> Call instruction SlotIndex 10896B, searching vregs 0 -> 257 and stack slots -1 -> 21

  STACKMAP 31, 0, ...
  -> Call instruction SlotIndex 11104B, searching vregs 0 -> 257 and stack slots -1 -> 21

********** REWRITE VIRTUAL REGISTERS **********
********** Function: GOMP_task
********** REGISTER MAP **********
[%vreg4 -> %X26] GPR64
[%vreg5 -> %X25] GPR64
[%vreg6 -> %X24] GPR64
[%vreg7 -> %X23] GPR64
[%vreg8 -> %X22] GPR64
[%vreg9 -> %W5] GPR32
[%vreg10 -> %W21] GPR32
[%vreg11 -> %X20] GPR64
[%vreg12 -> %W27] GPR32
[%vreg13 -> %W28] GPR32common
[%vreg15 -> %X0] GPR64common
[%vreg16 -> %X8] GPR64
[%vreg17 -> %X8] GPR64common
[%vreg18 -> %X0] GPR64sp
[%vreg19 -> %W0] GPR32
[%vreg20 -> %X8] GPR64common
[%vreg21 -> %X8] GPR64common
[%vreg22 -> %X8] GPR64
[%vreg23 -> %X8] GPR64common
[%vreg24 -> %X8] GPR64common
[%vreg25 -> %X8] GPR64common
[%vreg26 -> %W8] GPR32
[%vreg27 -> %W8] GPR32
[%vreg28 -> %W8] GPR32
[%vreg29 -> %X9] GPR64common
[%vreg30 -> %W9] GPR32
[%vreg31 -> %W8] GPR32
[%vreg32 -> %X8] GPR64common
[%vreg33 -> %W8] GPR32
[%vreg35 -> %W8] GPR32
[%vreg36 -> %X8] GPR64
[%vreg37 -> %X8] GPR64common
[%vreg38 -> %X8] GPR64
[%vreg39 -> %X8] GPR64common
[%vreg40 -> %X8] GPR64common
[%vreg41 -> %W8] GPR32
[%vreg42 -> %W8] GPR32common
[%vreg43 -> %X8] GPR64common
[%vreg44 -> %W9] GPR32
[%vreg45 -> %W8] GPR32
[%vreg46 -> %W8] GPR32
[%vreg47 -> %X8] GPR64common
[%vreg48 -> %X8] GPR64common
[%vreg49 -> %X8] GPR64
[%vreg51 -> %W9] GPR32
[%vreg52 -> %X8] GPR64common
[%vreg53 -> %X8] GPR64
[%vreg55 -> %X9] GPR64
[%vreg56 -> %X8] GPR64
[%vreg57 -> %X8] GPR64
[%vreg58 -> %X9] GPR64
[%vreg59 -> %X8] GPR64
[%vreg60 -> %X10] GPR64
[%vreg61 -> %X8] GPR64common
[%vreg62 -> %X0] GPR64sp
[%vreg63 -> %X0] GPR64
[%vreg64 -> %X8] GPR64
[%vreg65 -> %X8] GPR64
[%vreg66 -> %X9] GPR64common
[%vreg67 -> %X8] GPR64common
[%vreg68 -> %X8] GPR64common
[%vreg69 -> %X9] GPR64
[%vreg70 -> %X8] GPR64
[%vreg71 -> %X21] GPR64
[%vreg72 -> %X20] GPR64
[%vreg74 -> %X2] GPR64all
[%vreg75 -> %W8] GPR32
[%vreg76 -> %X9] GPR64common
[%vreg77 -> %X8] GPR64common
[%vreg78 -> %W9] GPR32
[%vreg79 -> %X8] GPR64common
[%vreg80 -> %W8] GPR32
[%vreg81 -> %X9] GPR64common
[%vreg82 -> %W8] GPR32common
[%vreg83 -> %X8] GPR64
[%vreg84 -> %X9] GPR64common
[%vreg85 -> %X8] GPR64
[%vreg86 -> %X9] GPR64common
[%vreg87 -> %X8] GPR64
[%vreg88 -> %X0] GPR64
[%vreg89 -> %X1] GPR64
[%vreg90 -> %X2] GPR64
[%vreg91 -> %X8] GPR64
[%vreg92 -> %X0] GPR64
[%vreg93 -> %X1] GPR64
[%vreg94 -> %X8] GPR64common
[%vreg95 -> %W9] GPR32
[%vreg96 -> %X8] GPR64
[%vreg97 -> %X9] GPR64common
[%vreg98 -> %X8] GPR64common
[%vreg99 -> %W9] GPR32
[%vreg100 -> %X8] GPR64
[%vreg101 -> %X9] GPR64common
[%vreg102 -> %X8] GPR64
[%vreg103 -> %X9] GPR64common
[%vreg104 -> %W8] GPR32
[%vreg105 -> %W8] GPR32
[%vreg106 -> %X9] GPR64common
[%vreg107 -> %X8] GPR64common
[%vreg108 -> %X0] GPR64sp
[%vreg109 -> %X8] GPR64common
[%vreg110 -> %X0] GPR64sp
[%vreg111 -> %W0] GPR32
[%vreg113 -> %X9] GPR64
[%vreg116 -> %X8] GPR64common
[%vreg117 -> %W9] GPR32
[%vreg119 -> %X8] GPR64common
[%vreg120 -> %W8] GPR32
[%vreg122 -> %X8] GPR64
[%vreg123 -> %X8] GPR64common
[%vreg124 -> %X9] GPR64common
[%vreg125 -> %X9] GPR64common
[%vreg126 -> %X8] GPR64
[%vreg127 -> %X0] GPR64
[%vreg128 -> %X1] GPR64
[%vreg129 -> %X2] GPR64
[%vreg130 -> %X8] GPR64common
[%vreg131 -> %X8] GPR64
[%vreg132 -> %X8] GPR64common
[%vreg133 -> %X1] GPR64sp
[%vreg134 -> %X2] GPR64common
[%vreg135 -> %W3] GPR32
[%vreg136 -> %W9] GPR32
[%vreg137 -> %W6] GPR32sp
[%vreg140 -> %X8] GPR64
[%vreg141 -> %X8] GPR64common
[%vreg142 -> %X1] GPR64sp
[%vreg143 -> %X2] GPR64common
[%vreg144 -> %W3] GPR32
[%vreg145 -> %W9] GPR32
[%vreg146 -> %W6] GPR32sp
[%vreg149 -> %X8] GPR64common
[%vreg150 -> %X1] GPR64sp
[%vreg151 -> %X2] GPR64common
[%vreg152 -> %W3] GPR32
[%vreg153 -> %W9] GPR32
[%vreg154 -> %W6] GPR32sp
[%vreg157 -> %X8] GPR64common
[%vreg158 -> %W9] GPR32common
[%vreg159 -> %W9] GPR32common
[%vreg160 -> %X8] GPR64common
[%vreg161 -> %W9] GPR32common
[%vreg162 -> %W9] GPR32common
[%vreg163 -> %X8] GPR64common
[%vreg164 -> %X0] GPR64sp
[%vreg165 -> %X9] GPR64common
[%vreg166 -> %W11] GPR32
[%vreg167 -> %X8] GPR64common
[%vreg168 -> %W8] GPR32
[%vreg169 -> %W8] GPR32
[%vreg170 -> %W8] GPR32common
[%vreg171 -> %W8] GPR32
[%vreg172 -> %W9] GPR32
[%vreg173 -> %W8] GPR32
[%vreg174 -> %W8] GPR32
[%vreg175 -> %X10] GPR64common
[%vreg176 -> %X0] GPR64sp
[%vreg177 -> %W8] GPR32
[%vreg178 -> %X8] GPR64common
[%vreg179 -> %X0] GPR64sp
[%vreg181 -> %X8] GPR64common
[%vreg182 -> %X0] GPR64sp
[%vreg183 -> %X8] GPR64common
[%vreg184 -> %X0] GPR64sp
[%vreg185 -> %X0] GPR64
[%vreg186 -> %X0] GPR64
[%vreg187 -> %W8] GPR32
[%vreg188 -> %X8] GPR64common
[%vreg189 -> %X8] GPR64
[%vreg190 -> %X8] GPR64common
[%vreg191 -> %X8] GPR64common
[%vreg192 -> %X8] GPR64
[%vreg193 -> %X0] GPR64
[%vreg194 -> %X8] GPR64common
[%vreg195 -> %X20] GPR64
[%vreg197 -> %X2] GPR64all
[%vreg199 -> %W9] GPR32
[%vreg200 -> %X8] GPR64common
[%vreg201 -> %X8] GPR64
[%vreg203 -> %X8] GPR64common
[%vreg204 -> %X8] GPR64common
[%vreg205 -> %W8] GPR32
[%vreg206 -> %W9] GPR32common
[%vreg208 -> %W8] GPR32
[%vreg210 -> %W8] GPR32common
[%vreg211 -> %W9] GPR32
[%vreg212 -> %X10] GPR64common
[%vreg213 -> %X8] GPR64
[%vreg214 -> %X8] GPR64common
[%vreg215 -> %X8] GPR64common
[%vreg216 -> %W8] GPR32
[%vreg217 -> %W8] GPR32common
[%vreg218 -> %X9] GPR64common
[%vreg219 -> %X8] GPR64common
[%vreg220 -> %X8] GPR64
[%vreg221 -> %X8] GPR64common
[%vreg222 -> %X9] GPR64common
[%vreg223 -> %X8] GPR64
[%vreg224 -> %X8] GPR64
[%vreg225 -> %X0] GPR64
[%vreg226 -> %X9] GPR64
[%vreg227 -> %X10] GPR64
[%vreg228 -> %X9] GPR64common
[%vreg229 -> %X8] GPR64
[%vreg230 -> %X8] GPR64common
[%vreg231 -> %X8] GPR64common
[%vreg232 -> %X9] GPR64
[%vreg233 -> %X8] GPR64
[%vreg234 -> %X9] GPR64common
[%vreg235 -> %X8] GPR64common
[%vreg236 -> %X8] GPR64
[%vreg237 -> %X9] GPR64
[%vreg238 -> %X0] GPR64
[%vreg239 -> %X10] GPR64
[%vreg240 -> %X1] GPR64
[%vreg241 -> %X8] GPR64
[%vreg242 -> %X0] GPR64
[%vreg243 -> %X8] GPR64
[%vreg244 -> %X8] GPR64sp
[%vreg245 -> %X0] GPR64sp
[%vreg247 -> %W0] GPR32
[%vreg248 -> %X8] GPR64common
[%vreg249 -> %X0] GPR64sp
[%vreg250 -> %X8] GPR64sp
[%vreg251 -> %X0] GPR64sp
[%vreg252 -> %X8] GPR64common
[%vreg253 -> %X0] GPR64sp
[%vreg255 -> %W8] GPR32
[%vreg256 -> %W8] GPR32common

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %W5 %W6 %X0 %X1 %X2 %X3 %X4 %X7
16B		%vreg11<def> = COPY %X7; GPR64:%vreg11
32B		%vreg10<def> = COPY %W6; GPR32:%vreg10
144B		%vreg12<def> = LDRWui <fi#-1>, 0; mem:LD4[FixedStack-1] GPR32:%vreg12
148B		%vreg9<def> = COPY %W5; GPR32:%vreg9
152B		%vreg8<def> = COPY %X4; GPR64:%vreg8
160B		%vreg7<def> = COPY %X3; GPR64:%vreg7
168B		%vreg6<def> = COPY %X2; GPR64:%vreg6
176B		%vreg5<def> = COPY %X1; GPR64:%vreg5
184B		%vreg4<def> = COPY %X0; GPR64:%vreg4
192B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
200B		%vreg13<def> = ANDWri %vreg9<kill>, 0; GPR32common:%vreg13 GPR32:%vreg9
216B		%X0<def> = COPY %XZR
224B		%X1<def> = COPY %XZR
240B		BL <ga:@check_migrate>, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %SP<imp-def>, ...
256B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
272B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
288B		STACKMAP 0, 0, %vreg8, %vreg7, %vreg6, %vreg5, %vreg11, %vreg10, %vreg4, %vreg13, %vreg12, ...; GPR64:%vreg8,%vreg7,%vreg6,%vreg5,%vreg11,%vreg4 GPR32:%vreg10,%vreg12 GPR32common:%vreg13
304B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
320B		STRXui %vreg4<kill>, <fi#0>, 0; mem:ST8[%fn.addr] GPR64:%vreg4
336B		STRXui %vreg5<kill>, <fi#1>, 0; mem:ST8[%data.addr] GPR64:%vreg5
352B		STRXui %vreg6<kill>, <fi#2>, 0; mem:ST8[%cpyfn.addr] GPR64:%vreg6
368B		STRXui %vreg7<kill>, <fi#3>, 0; mem:ST8[%arg_size.addr] GPR64:%vreg7
384B		STRXui %vreg8<kill>, <fi#4>, 0; mem:ST8[%arg_align.addr] GPR64:%vreg8
400B		STRBBui %vreg13<kill>, <fi#5>, 0; mem:ST1[%if_clause.addr] GPR32common:%vreg13
416B		STRWui %vreg10<kill>, <fi#6>, 0; mem:ST4[%flags.addr] GPR32:%vreg10
432B		STRXui %vreg11<kill>, <fi#7>, 0; mem:ST8[%depend.addr] GPR64:%vreg11
448B		STRWui %vreg12<kill>, <fi#8>, 0; mem:ST4[%priority.addr] GPR32:%vreg12
464B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
480B		BL <ga:@gomp_thread>, <regmask>, %SP<imp-use>, %SP<imp-def>, %X0<imp-def>, ...
496B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
512B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
528B		STACKMAP 1, 0, 0, <fi#13>, 0, 0, <fi#17>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#19>, 0, 0, <fi#18>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#5>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#12>, 0, 0, <fi#11>, 0, 0, <fi#14>, 0, 0, <fi#16>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack13] LD8[FixedStack17] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack2] LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack19] LD8[FixedStack18](align=1) LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack5](align=1) LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack12] LD8[FixedStack11] LD8[FixedStack14] LD8[FixedStack16] LD8[FixedStack10] LD8[FixedStack9]
544B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
560B		%vreg15<def> = COPY %X0; GPR64common:%vreg15
576B		STRXui %vreg15, <fi#9>, 0; mem:ST8[%thr] GPR64common:%vreg15
592B		%vreg16<def> = LDRXui %vreg15<kill>, 2; mem:LD8[%team1] GPR64:%vreg16 GPR64common:%vreg15
608B		STRXui %vreg16, <fi#10>, 0; mem:ST8[%team] GPR64:%vreg16
624B		CBZX %vreg16<kill>, <BB#5>; GPR64:%vreg16
640B		B <BB#1>
	    Successors according to CFG: BB#1 BB#5
> %X20<def> = COPY %X7
> %W21<def> = COPY %W6
> %W27<def> = LDRWui <fi#-1>, 0; mem:LD4[FixedStack-1]
> %W5<def> = COPY %W5
Deleting identity copy.
> %X22<def> = COPY %X4
> %X23<def> = COPY %X3
> %X24<def> = COPY %X2
> %X25<def> = COPY %X1
> %X26<def> = COPY %X0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %W28<def> = ANDWri %W5<kill>, 0
> %X0<def> = COPY %XZR
> %X1<def> = COPY %XZR
> BL <ga:@check_migrate>, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %SP<imp-def>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 0, 0, %X22, %X23, %X24, %X25, %X20, %W21, %X26, %W28, %W27, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRXui %X26<kill>, <fi#0>, 0; mem:ST8[%fn.addr]
> STRXui %X25<kill>, <fi#1>, 0; mem:ST8[%data.addr]
> STRXui %X24<kill>, <fi#2>, 0; mem:ST8[%cpyfn.addr]
> STRXui %X23<kill>, <fi#3>, 0; mem:ST8[%arg_size.addr]
> STRXui %X22<kill>, <fi#4>, 0; mem:ST8[%arg_align.addr]
> STRBBui %W28<kill>, <fi#5>, 0; mem:ST1[%if_clause.addr]
> STRWui %W21<kill>, <fi#6>, 0; mem:ST4[%flags.addr]
> STRXui %X20<kill>, <fi#7>, 0; mem:ST8[%depend.addr]
> STRWui %W27<kill>, <fi#8>, 0; mem:ST4[%priority.addr]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> BL <ga:@gomp_thread>, <regmask>, %SP<imp-use>, %SP<imp-def>, %X0<imp-def>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 1, 0, 0, <fi#13>, 0, 0, <fi#17>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#19>, 0, 0, <fi#18>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#5>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#12>, 0, 0, <fi#11>, 0, 0, <fi#14>, 0, 0, <fi#16>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack13] LD8[FixedStack17] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack2] LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack19] LD8[FixedStack18](align=1) LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack5](align=1) LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack12] LD8[FixedStack11] LD8[FixedStack14] LD8[FixedStack16] LD8[FixedStack10] LD8[FixedStack9]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0
Deleting identity copy.
> STRXui %X0, <fi#9>, 0; mem:ST8[%thr]
> %X8<def> = LDRXui %X0<kill>, 2; mem:LD8[%team1]
> STRXui %X8, <fi#10>, 0; mem:ST8[%team]
> CBZX %X8<kill>, <BB#5>
> B <BB#1>
656B	BB#1: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#0
672B		%vreg17<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg17
688B		%vreg18<def> = ADDXri %vreg17<kill>, 128, 0; GPR64sp:%vreg18 GPR64common:%vreg17
704B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
720B		%X0<def> = COPY %vreg18<kill>; GPR64sp:%vreg18
736B		BL <ga:@gomp_team_barrier_cancelled>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>, ...
752B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
768B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
784B		STACKMAP 2, 0, 0, <fi#13>, 0, 0, <fi#17>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#19>, 0, 0, <fi#18>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#5>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#12>, 0, 0, <fi#11>, 0, 0, <fi#14>, 0, 0, <fi#16>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack13] LD8[FixedStack17] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack2] LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack19] LD8[FixedStack18](align=1) LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack5](align=1) LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack12] LD8[FixedStack11] LD8[FixedStack14] LD8[FixedStack16] LD8[FixedStack10] LD8[FixedStack9]
800B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
816B		%vreg19<def> = COPY %W0; GPR32:%vreg19
832B		TBNZW %vreg19<kill>, 0, <BB#4>; GPR32:%vreg19
848B		B <BB#2>
	    Successors according to CFG: BB#4 BB#2
> %X8<def> = LDRXui <fi#10>, 0; mem:LD8[%team]
> %X0<def> = ADDXri %X8<kill>, 128, 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BL <ga:@gomp_team_barrier_cancelled>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 2, 0, 0, <fi#13>, 0, 0, <fi#17>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#19>, 0, 0, <fi#18>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#5>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#12>, 0, 0, <fi#11>, 0, 0, <fi#14>, 0, 0, <fi#16>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack13] LD8[FixedStack17] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack2] LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack19] LD8[FixedStack18](align=1) LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack5](align=1) LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack12] LD8[FixedStack11] LD8[FixedStack14] LD8[FixedStack16] LD8[FixedStack10] LD8[FixedStack9]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = COPY %W0
Deleting identity copy.
> TBNZW %W0<kill>, 0, <BB#4>
> B <BB#2>
864B	BB#2: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#1
880B		%vreg20<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg20
896B		%vreg21<def> = LDRXui %vreg20<kill>, 10; mem:LD8[%task] GPR64common:%vreg21,%vreg20
912B		%vreg22<def> = LDRXui %vreg21<kill>, 5; mem:LD8[%taskgroup] GPR64:%vreg22 GPR64common:%vreg21
928B		CBZX %vreg22<kill>, <BB#5>; GPR64:%vreg22
944B		B <BB#3>
	    Successors according to CFG: BB#3 BB#5
> %X8<def> = LDRXui <fi#9>, 0; mem:LD8[%thr]
> %X8<def> = LDRXui %X8<kill>, 10; mem:LD8[%task]
> %X8<def> = LDRXui %X8<kill>, 5; mem:LD8[%taskgroup]
> CBZX %X8<kill>, <BB#5>
> B <BB#3>
960B	BB#3: derived from LLVM BB %land.lhs.true.4
	    Predecessors according to CFG: BB#2
976B		%vreg23<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg23
992B		%vreg24<def> = LDRXui %vreg23<kill>, 10; mem:LD8[%task5] GPR64common:%vreg24,%vreg23
1008B		%vreg25<def> = LDRXui %vreg24<kill>, 5; mem:LD8[%taskgroup6] GPR64common:%vreg25,%vreg24
1024B		%vreg26<def> = LDRBBui %vreg25<kill>, 41; mem:LD1[%cancelled] GPR32:%vreg26 GPR64common:%vreg25
1040B		TBZW %vreg26<kill>, 0, <BB#5>; GPR32:%vreg26
1056B		B <BB#4>
	    Successors according to CFG: BB#4 BB#5
> %X8<def> = LDRXui <fi#9>, 0; mem:LD8[%thr]
> %X8<def> = LDRXui %X8<kill>, 10; mem:LD8[%task5]
> %X8<def> = LDRXui %X8<kill>, 5; mem:LD8[%taskgroup6]
> %W8<def> = LDRBBui %X8<kill>, 41; mem:LD1[%cancelled]
> TBZW %W8<kill>, 0, <BB#5>
> B <BB#4>
1072B	BB#4: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#1 BB#3
1088B		B <BB#52>
	    Successors according to CFG: BB#52
> B <BB#52>
1104B	BB#5: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#2 BB#3
1120B		%vreg27<def> = LDRBBui <fi#6>, 0; mem:LD1[%flags.addr](align=4) GPR32:%vreg27
1136B		TBNZW %vreg27<kill>, 4, <BB#7>; GPR32:%vreg27
1152B		B <BB#6>
	    Successors according to CFG: BB#6 BB#7
> %W8<def> = LDRBBui <fi#6>, 0; mem:LD1[%flags.addr](align=4)
> TBNZW %W8<kill>, 4, <BB#7>
> B <BB#6>
1168B	BB#6: derived from LLVM BB %if.then.8
	    Predecessors according to CFG: BB#5
1200B		STRWui %WZR, <fi#8>, 0; mem:ST4[%priority.addr]
1216B		B <BB#10>
	    Successors according to CFG: BB#10
> STRWui %WZR, <fi#8>, 0; mem:ST4[%priority.addr]
> B <BB#10>
1232B	BB#7: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#5
1248B		%vreg28<def> = LDRWui <fi#8>, 0; mem:LD4[%priority.addr] GPR32:%vreg28
1264B		%vreg29<def> = ADRP <ga:@gomp_max_task_priority_var>[TF=1]; GPR64common:%vreg29
1280B		%vreg30<def> = LDRWui %vreg29<kill>, <ga:@gomp_max_task_priority_var>[TF=34]; mem:LD4[@gomp_max_task_priority_var] GPR32:%vreg30 GPR64common:%vreg29
1296B		%vreg31<def,dead> = SUBSWrr %vreg28<kill>, %vreg30<kill>, %NZCV<imp-def>; GPR32:%vreg31,%vreg28,%vreg30
1312B		Bcc 13, <BB#9>, %NZCV<imp-use>
1328B		B <BB#8>
	    Successors according to CFG: BB#8 BB#9
> %W8<def> = LDRWui <fi#8>, 0; mem:LD4[%priority.addr]
> %X9<def> = ADRP <ga:@gomp_max_task_priority_var>[TF=1]
> %W9<def> = LDRWui %X9<kill>, <ga:@gomp_max_task_priority_var>[TF=34]; mem:LD4[@gomp_max_task_priority_var]
> %W8<def,dead> = SUBSWrr %W8<kill>, %W9<kill>, %NZCV<imp-def>
> Bcc 13, <BB#9>, %NZCV<imp-use>
> B <BB#8>
1344B	BB#8: derived from LLVM BB %if.then.10
	    Predecessors according to CFG: BB#7
1360B		%vreg32<def> = ADRP <ga:@gomp_max_task_priority_var>[TF=1]; GPR64common:%vreg32
1376B		%vreg33<def> = LDRWui %vreg32<kill>, <ga:@gomp_max_task_priority_var>[TF=34]; mem:LD4[@gomp_max_task_priority_var] GPR32:%vreg33 GPR64common:%vreg32
1392B		STRWui %vreg33<kill>, <fi#8>, 0; mem:ST4[%priority.addr] GPR32:%vreg33
1408B		B <BB#9>
	    Successors according to CFG: BB#9
> %X8<def> = ADRP <ga:@gomp_max_task_priority_var>[TF=1]
> %W8<def> = LDRWui %X8<kill>, <ga:@gomp_max_task_priority_var>[TF=34]; mem:LD4[@gomp_max_task_priority_var]
> STRWui %W8<kill>, <fi#8>, 0; mem:ST4[%priority.addr]
> B <BB#9>
1424B	BB#9: derived from LLVM BB %if.end.11
	    Predecessors according to CFG: BB#7 BB#8
1440B		B <BB#10>
	    Successors according to CFG: BB#10
> B <BB#10>
1456B	BB#10: derived from LLVM BB %if.end.12
	    Predecessors according to CFG: BB#9 BB#6
1472B		%vreg35<def> = LDRBBui <fi#5>, 0; mem:LD1[%if_clause.addr] GPR32:%vreg35
1488B		TBZW %vreg35<kill>, 0, <BB#15>; GPR32:%vreg35
1504B		B <BB#11>
	    Successors according to CFG: BB#11 BB#15
> %W8<def> = LDRBBui <fi#5>, 0; mem:LD1[%if_clause.addr]
> TBZW %W8<kill>, 0, <BB#15>
> B <BB#11>
1520B	BB#11: derived from LLVM BB %lor.lhs.false.14
	    Predecessors according to CFG: BB#10
1536B		%vreg36<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64:%vreg36
1552B		CBZX %vreg36<kill>, <BB#15>; GPR64:%vreg36
1568B		B <BB#12>
	    Successors according to CFG: BB#15 BB#12
> %X8<def> = LDRXui <fi#10>, 0; mem:LD8[%team]
> CBZX %X8<kill>, <BB#15>
> B <BB#12>
1584B	BB#12: derived from LLVM BB %lor.lhs.false.16
	    Predecessors according to CFG: BB#11
1600B		%vreg37<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg37
1616B		%vreg38<def> = LDRXui %vreg37<kill>, 10; mem:LD8[%task17] GPR64:%vreg38 GPR64common:%vreg37
1632B		CBZX %vreg38<kill>, <BB#14>; GPR64:%vreg38
1648B		B <BB#13>
	    Successors according to CFG: BB#13 BB#14
> %X8<def> = LDRXui <fi#9>, 0; mem:LD8[%thr]
> %X8<def> = LDRXui %X8<kill>, 10; mem:LD8[%task17]
> CBZX %X8<kill>, <BB#14>
> B <BB#13>
1664B	BB#13: derived from LLVM BB %land.lhs.true.19
	    Predecessors according to CFG: BB#12
1680B		%vreg39<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg39
1696B		%vreg40<def> = LDRXui %vreg39<kill>, 10; mem:LD8[%task20] GPR64common:%vreg40,%vreg39
1712B		%vreg41<def> = LDRBBui %vreg40<kill>, 205; mem:LD1[%final_task] GPR32:%vreg41 GPR64common:%vreg40
1728B		%vreg42<def> = ANDWri %vreg41<kill>, 0; GPR32common:%vreg42 GPR32:%vreg41
1744B		TBNZW %vreg42<kill>, 0, <BB#15>; GPR32common:%vreg42
1760B		B <BB#14>
	    Successors according to CFG: BB#15 BB#14
> %X8<def> = LDRXui <fi#9>, 0; mem:LD8[%thr]
> %X8<def> = LDRXui %X8<kill>, 10; mem:LD8[%task20]
> %W8<def> = LDRBBui %X8<kill>, 205; mem:LD1[%final_task]
> %W8<def> = ANDWri %W8<kill>, 0
> TBNZW %W8<kill>, 0, <BB#15>
> B <BB#14>
1776B	BB#14: derived from LLVM BB %lor.lhs.false.22
	    Predecessors according to CFG: BB#12 BB#13
1792B		%vreg43<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg43
1808B		%vreg44<def> = LDRWui %vreg43, 330; mem:LD4[%task_count] GPR32:%vreg44 GPR64common:%vreg43
1824B		%vreg45<def> = LDRWui %vreg43<kill>, 0; mem:LD4[%nthreads] GPR32:%vreg45 GPR64common:%vreg43
1840B		%vreg46<def,dead> = SUBSWrs %vreg44<kill>, %vreg45<kill>, 6, %NZCV<imp-def>; GPR32:%vreg46,%vreg44,%vreg45
1856B		Bcc 9, <BB#30>, %NZCV<imp-use>
1872B		B <BB#15>
	    Successors according to CFG: BB#15 BB#30
> %X8<def> = LDRXui <fi#10>, 0; mem:LD8[%team]
> %W9<def> = LDRWui %X8, 330; mem:LD4[%task_count]
> %W8<def> = LDRWui %X8<kill>, 0; mem:LD4[%nthreads]
> %W8<def,dead> = SUBSWrs %W9<kill>, %W8<kill>, 6, %NZCV<imp-def>
> Bcc 9, <BB#30>, %NZCV<imp-use>
> B <BB#15>
1888B	BB#15: derived from LLVM BB %if.then.24
	    Predecessors according to CFG: BB#10 BB#11 BB#13 BB#14
1904B		%vreg187<def> = LDRBBui <fi#6>, 0; mem:LD1[%flags.addr](align=4) GPR32:%vreg187
1920B		TBZW %vreg187<kill>, 3, <BB#19>; GPR32:%vreg187
1936B		B <BB#16>
	    Successors according to CFG: BB#16 BB#19
> %W8<def> = LDRBBui <fi#6>, 0; mem:LD1[%flags.addr](align=4)
> TBZW %W8<kill>, 3, <BB#19>
> B <BB#16>
1952B	BB#16: derived from LLVM BB %land.lhs.true.28
	    Predecessors according to CFG: BB#15
1968B		%vreg188<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg188
1984B		%vreg189<def> = LDRXui %vreg188<kill>, 10; mem:LD8[%task29] GPR64:%vreg189 GPR64common:%vreg188
2000B		CBZX %vreg189<kill>, <BB#19>; GPR64:%vreg189
2016B		B <BB#17>
	    Successors according to CFG: BB#17 BB#19
> %X8<def> = LDRXui <fi#9>, 0; mem:LD8[%thr]
> %X8<def> = LDRXui %X8<kill>, 10; mem:LD8[%task29]
> CBZX %X8<kill>, <BB#19>
> B <BB#17>
2032B	BB#17: derived from LLVM BB %land.lhs.true.31
	    Predecessors according to CFG: BB#16
2048B		%vreg190<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg190
2064B		%vreg191<def> = LDRXui %vreg190<kill>, 10; mem:LD8[%task32] GPR64common:%vreg191,%vreg190
2080B		%vreg192<def> = LDRXui %vreg191<kill>, 7; mem:LD8[%depend_hash] GPR64:%vreg192 GPR64common:%vreg191
2096B		CBZX %vreg192<kill>, <BB#19>; GPR64:%vreg192
2112B		B <BB#18>
	    Successors according to CFG: BB#18 BB#19
> %X8<def> = LDRXui <fi#9>, 0; mem:LD8[%thr]
> %X8<def> = LDRXui %X8<kill>, 10; mem:LD8[%task32]
> %X8<def> = LDRXui %X8<kill>, 7; mem:LD8[%depend_hash]
> CBZX %X8<kill>, <BB#19>
> B <BB#18>
2128B	BB#18: derived from LLVM BB %if.then.34
	    Predecessors according to CFG: BB#17
2144B		%vreg193<def> = LDRXui <fi#7>, 0; mem:LD8[%depend.addr] GPR64:%vreg193
2160B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2176B		%X0<def> = COPY %vreg193<kill>; GPR64:%vreg193
2192B		BL <ga:@gomp_task_maybe_wait_for_dependencies>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...
2208B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2224B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2240B		STACKMAP 3, 0, 0, <fi#13>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#8>, 0, 0, <fi#12>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack13] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack2] LD8[FixedStack1] LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack8](align=4) LD8[FixedStack12] LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack9]
2256B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2272B		B <BB#19>
	    Successors according to CFG: BB#19
> %X0<def> = LDRXui <fi#7>, 0; mem:LD8[%depend.addr]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BL <ga:@gomp_task_maybe_wait_for_dependencies>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 3, 0, 0, <fi#13>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#8>, 0, 0, <fi#12>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack13] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack2] LD8[FixedStack1] LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack8](align=4) LD8[FixedStack12] LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack9]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> B <BB#19>
2288B	BB#19: derived from LLVM BB %if.end.35
	    Predecessors according to CFG: BB#15 BB#16 BB#17 BB#18
2304B		%vreg194<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg194
2320B		%vreg195<def> = LDRXui %vreg194<kill>, 10; mem:LD8[%task36] GPR64:%vreg195 GPR64common:%vreg194
2336B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2368B		%W0<def> = COPY %WZR
2384B		BL <ga:@gomp_icv>, <regmask>, %SP<imp-use>, %W0<imp-use>, %SP<imp-def>, %X0<imp-def>, ...
2400B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2416B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2432B		STACKMAP 4, 0, 0, <fi#13>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#8>, 0, 0, <fi#12>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, %vreg195, ...; mem:LD8[FixedStack13] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack2] LD8[FixedStack1] LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack8](align=4) LD8[FixedStack12] LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack9] GPR64:%vreg195
2448B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2464B		%vreg197<def> = COPY %X0; GPR64all:%vreg197
2480B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2512B		%X0<def> = ADDXri <fi#11>, 0, 0
2528B		%X1<def> = COPY %vreg195<kill>; GPR64:%vreg195
2544B		%X2<def> = COPY %vreg197<kill>; GPR64all:%vreg197
2560B		BL <ga:@gomp_init_task>, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %X2<imp-use>, %SP<imp-def>, ...
2576B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2592B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2608B		STACKMAP 5, 0, 0, <fi#13>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#8>, 0, 0, <fi#12>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack13] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack2] LD8[FixedStack1] LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack8](align=4) LD8[FixedStack12] LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack9]
2624B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2672B		%vreg200<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg200
2676B		%vreg199<def> = MOVi32imm 1; GPR32:%vreg199
2680B		STRWui %vreg199<kill>, <fi#11>, 50; mem:ST4[%kind] GPR32:%vreg199
2688B		%vreg201<def> = LDRXui %vreg200<kill>, 10; mem:LD8[%task38] GPR64:%vreg201 GPR64common:%vreg200
2704B		CBZX %vreg201<kill>, <BB#21>; GPR64:%vreg201
2720B		B <BB#20>
	    Successors according to CFG: BB#20 BB#21
> %X8<def> = LDRXui <fi#9>, 0; mem:LD8[%thr]
> %X20<def> = LDRXui %X8<kill>, 10; mem:LD8[%task36]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = COPY %WZR
> BL <ga:@gomp_icv>, <regmask>, %SP<imp-use>, %W0<imp-use>, %SP<imp-def>, %X0<imp-def>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 4, 0, 0, <fi#13>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#8>, 0, 0, <fi#12>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, %X20, ...; mem:LD8[FixedStack13] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack2] LD8[FixedStack1] LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack8](align=4) LD8[FixedStack12] LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack9]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X2<def> = COPY %X0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = ADDXri <fi#11>, 0, 0
> %X1<def> = COPY %X20<kill>
> %X2<def> = COPY %X2<kill>
Deleting identity copy.
> BL <ga:@gomp_init_task>, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %X2<imp-use>, %SP<imp-def>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 5, 0, 0, <fi#13>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#8>, 0, 0, <fi#12>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack13] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack2] LD8[FixedStack1] LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack8](align=4) LD8[FixedStack12] LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack9]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X8<def> = LDRXui <fi#9>, 0; mem:LD8[%thr]
> %W9<def> = MOVi32imm 1
> STRWui %W9<kill>, <fi#11>, 50; mem:ST4[%kind]
> %X8<def> = LDRXui %X8<kill>, 10; mem:LD8[%task38]
> CBZX %X8<kill>, <BB#21>
> B <BB#20>
2736B	BB#20: derived from LLVM BB %land.lhs.true.40
	    Predecessors according to CFG: BB#19
2752B		%vreg203<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg203
2768B		%vreg204<def> = LDRXui %vreg203<kill>, 10; mem:LD8[%task41] GPR64common:%vreg204,%vreg203
2784B		%vreg205<def> = LDRBBui %vreg204<kill>, 205; mem:LD1[%final_task42] GPR32:%vreg205 GPR64common:%vreg204
2800B		%vreg206<def> = ANDWri %vreg205<kill>, 0; GPR32common:%vreg206 GPR32:%vreg205
2816B		%vreg255<def> = MOVi32imm 1; GPR32:%vreg255
2864B		TBNZW %vreg206<kill>, 0, <BB#22>; GPR32common:%vreg206
2880B		B <BB#21>
	    Successors according to CFG: BB#22 BB#21
> %X8<def> = LDRXui <fi#9>, 0; mem:LD8[%thr]
> %X8<def> = LDRXui %X8<kill>, 10; mem:LD8[%task41]
> %W8<def> = LDRBBui %X8<kill>, 205; mem:LD1[%final_task42]
> %W9<def> = ANDWri %W8<kill>, 0
> %W8<def> = MOVi32imm 1
> TBNZW %W9<kill>, 0, <BB#22>
> B <BB#21>
2896B	BB#21: derived from LLVM BB %lor.rhs
	    Predecessors according to CFG: BB#19 BB#20
2912B		%vreg208<def> = LDRBBui <fi#6>, 0; mem:LD1[%flags.addr](align=4) GPR32:%vreg208
2928B		%vreg255<def> = UBFMWri %vreg208<kill>, 1, 1; GPR32:%vreg255,%vreg208
2976B		B <BB#22>
	    Successors according to CFG: BB#22
> %W8<def> = LDRBBui <fi#6>, 0; mem:LD1[%flags.addr](align=4)
> %W8<def> = UBFMWri %W8<kill>, 1, 1
> B <BB#22>
2992B	BB#22: derived from LLVM BB %lor.end
	    Live Ins: %W8
	    Predecessors according to CFG: BB#20 BB#21
3056B		%vreg211<def> = LDRWui <fi#8>, 0; mem:LD4[%priority.addr] GPR32:%vreg211
3088B		%vreg212<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg212
3096B		%vreg210<def> = ANDWri %vreg255<kill>, 0; GPR32common:%vreg210 GPR32:%vreg255
3104B		STRBBui %vreg210<kill>, <fi#11>, 205; mem:ST1[%final_task46] GPR32common:%vreg210
3112B		STRWui %vreg211<kill>, <fi#11>, 22; mem:ST4[%priority48] GPR32:%vreg211
3120B		%vreg213<def> = LDRXui %vreg212<kill>, 10; mem:LD8[%task49] GPR64:%vreg213 GPR64common:%vreg212
3128B		CBZX %vreg213<kill>, <BB#24>; GPR64:%vreg213
3136B		B <BB#23>
	    Successors according to CFG: BB#23 BB#24
> %W9<def> = LDRWui <fi#8>, 0; mem:LD4[%priority.addr]
> %X10<def> = LDRXui <fi#9>, 0; mem:LD8[%thr]
> %W8<def> = ANDWri %W8<kill>, 0
> STRBBui %W8<kill>, <fi#11>, 205; mem:ST1[%final_task46]
> STRWui %W9<kill>, <fi#11>, 22; mem:ST4[%priority48]
> %X8<def> = LDRXui %X10<kill>, 10; mem:LD8[%task49]
> CBZX %X8<kill>, <BB#24>
> B <BB#23>
3152B	BB#23: derived from LLVM BB %if.then.51
	    Predecessors according to CFG: BB#22
3168B		%vreg214<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg214
3184B		%vreg215<def> = LDRXui %vreg214<kill>, 10; mem:LD8[%task52] GPR64common:%vreg215,%vreg214
3200B		%vreg216<def> = LDRBBui %vreg215<kill>, 204; mem:LD1[%in_tied_task] GPR32:%vreg216 GPR64common:%vreg215
3248B		%vreg218<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg218
3252B		%vreg217<def> = ANDWri %vreg216<kill>, 0; GPR32common:%vreg217 GPR32:%vreg216
3256B		STRBBui %vreg217<kill>, <fi#11>, 204; mem:ST1[%in_tied_task54] GPR32common:%vreg217
3264B		%vreg219<def> = LDRXui %vreg218<kill>, 10; mem:LD8[%task56] GPR64common:%vreg219,%vreg218
3280B		%vreg220<def> = LDRXui %vreg219<kill>, 5; mem:LD8[%taskgroup57] GPR64:%vreg220 GPR64common:%vreg219
3296B		STRXui %vreg220<kill>, <fi#11>, 5; mem:ST8[%taskgroup58] GPR64:%vreg220
3312B		B <BB#24>
	    Successors according to CFG: BB#24
> %X8<def> = LDRXui <fi#9>, 0; mem:LD8[%thr]
> %X8<def> = LDRXui %X8<kill>, 10; mem:LD8[%task52]
> %W8<def> = LDRBBui %X8<kill>, 204; mem:LD1[%in_tied_task]
> %X9<def> = LDRXui <fi#9>, 0; mem:LD8[%thr]
> %W8<def> = ANDWri %W8<kill>, 0
> STRBBui %W8<kill>, <fi#11>, 204; mem:ST1[%in_tied_task54]
> %X8<def> = LDRXui %X9<kill>, 10; mem:LD8[%task56]
> %X8<def> = LDRXui %X8<kill>, 5; mem:LD8[%taskgroup57]
> STRXui %X8<kill>, <fi#11>, 5; mem:ST8[%taskgroup58]
> B <BB#24>
3328B	BB#24: derived from LLVM BB %if.end.59
	    Predecessors according to CFG: BB#22 BB#23
3344B		%vreg221<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg221
3360B		%vreg222<def> = ADDXri <fi#11>, 0, 0; GPR64common:%vreg222
3376B		STRXui %vreg222<kill>, %vreg221<kill>, 10; mem:ST8[%task60] GPR64common:%vreg222,%vreg221
3392B		%vreg223<def> = LDRXui <fi#2>, 0; mem:LD8[%cpyfn.addr] GPR64:%vreg223
3408B		CBZX %vreg223<kill>, <BB#26>; GPR64:%vreg223
3424B		B <BB#25>
	    Successors according to CFG: BB#25 BB#26
> %X8<def> = LDRXui <fi#9>, 0; mem:LD8[%thr]
> %X9<def> = ADDXri <fi#11>, 0, 0
> STRXui %X9<kill>, %X8<kill>, 10; mem:ST8[%task60]
> %X8<def> = LDRXui <fi#2>, 0; mem:LD8[%cpyfn.addr]
> CBZX %X8<kill>, <BB#26>
> B <BB#25>
3440B	BB#25: derived from LLVM BB %if.then.64
	    Predecessors according to CFG: BB#24
3448B		%vreg229<def> = COPY %SP; GPR64:%vreg229
3456B		%vreg226<def> = LDRXui <fi#3>, 0; mem:LD8[%arg_size.addr] GPR64:%vreg226
3472B		%vreg227<def> = LDRXui <fi#4>, 0; mem:LD8[%arg_align.addr] GPR64:%vreg227
3488B		%vreg228<def> = ADDXrr %vreg226<kill>, %vreg227<kill>; GPR64common:%vreg228 GPR64:%vreg226,%vreg227
3520B		STRXui %vreg229<kill>, <fi#12>, 0; mem:ST8[%saved_stack] GPR64:%vreg229
3536B		%vreg230<def> = ADDXri %vreg228<kill>, 14, 0; GPR64common:%vreg230,%vreg228
3552B		%vreg231<def> = ANDXri %vreg230<kill>, 7995; GPR64common:%vreg231,%vreg230
3568B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3584B		%vreg232<def> = COPY %SP; GPR64:%vreg232
3600B		%vreg233<def> = SUBSXrr %vreg232<kill>, %vreg231<kill>, %NZCV<imp-def,dead>; GPR64:%vreg233,%vreg232 GPR64common:%vreg231
3616B		%SP<def> = COPY %vreg233; GPR64:%vreg233
3632B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3648B		%vreg234<def> = LDRXui <fi#4>, 0; mem:LD8[%arg_align.addr] GPR64common:%vreg234
3744B		%vreg239<def> = LDRXui <fi#2>, 0; mem:LD8[%cpyfn.addr] GPR64:%vreg239
3760B		%vreg240<def> = LDRXui <fi#1>, 0; mem:LD8[%data.addr] GPR64:%vreg240
3768B		%vreg235<def> = ADDXrr %vreg233<kill>, %vreg234; GPR64common:%vreg235,%vreg234 GPR64:%vreg233
3776B		%vreg236<def> = SUBSXri %vreg235<kill>, 1, 0, %NZCV<imp-def,dead>; GPR64:%vreg236 GPR64common:%vreg235
3784B		%vreg237<def> = SUBSXri %vreg234<kill>, 1, 0, %NZCV<imp-def,dead>; GPR64:%vreg237 GPR64common:%vreg234
3792B		%vreg238<def> = BICXrr %vreg236<kill>, %vreg237<kill>; GPR64:%vreg238,%vreg236,%vreg237
3800B		STRXui %vreg238, <fi#13>, 0; mem:ST8[%arg] GPR64:%vreg238
3808B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3816B		%X0<def> = COPY %vreg238<kill>; GPR64:%vreg238
3824B		%X1<def> = COPY %vreg240<kill>; GPR64:%vreg240
3832B		BLR %vreg239<kill>, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %SP<imp-def>, ...; GPR64:%vreg239
3840B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3856B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3872B		STACKMAP 6, 0, 0, <fi#13>, 0, 0, <fi#0>, 0, 0, <fi#12>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack13] LD8[FixedStack0] LD8[FixedStack12] LD8[FixedStack11] LD8[FixedStack10]
3888B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3904B		%vreg241<def> = LDRXui <fi#0>, 0; mem:LD8[%fn.addr] GPR64:%vreg241
3920B		%vreg242<def> = LDRXui <fi#13>, 0; mem:LD8[%arg] GPR64:%vreg242
3936B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3952B		%X0<def> = COPY %vreg242<kill>; GPR64:%vreg242
3968B		BLR %vreg241<kill>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...; GPR64:%vreg241
3984B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4000B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4016B		STACKMAP 7, 0, 0, <fi#12>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack12] LD8[FixedStack11] LD8[FixedStack10]
4032B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4048B		%vreg243<def> = LDRXui <fi#12>, 0; mem:LD8[%saved_stack] GPR64:%vreg243
4064B		%SP<def> = COPY %vreg243<kill>; GPR64:%vreg243
4080B		B <BB#27>
	    Successors according to CFG: BB#27
> %X8<def> = COPY %SP
> %X9<def> = LDRXui <fi#3>, 0; mem:LD8[%arg_size.addr]
> %X10<def> = LDRXui <fi#4>, 0; mem:LD8[%arg_align.addr]
> %X9<def> = ADDXrr %X9<kill>, %X10<kill>
> STRXui %X8<kill>, <fi#12>, 0; mem:ST8[%saved_stack]
> %X8<def> = ADDXri %X9<kill>, 14, 0
> %X8<def> = ANDXri %X8<kill>, 7995
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X9<def> = COPY %SP
> %X8<def> = SUBSXrr %X9<kill>, %X8<kill>, %NZCV<imp-def,dead>
> %SP<def> = COPY %X8
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X9<def> = LDRXui <fi#4>, 0; mem:LD8[%arg_align.addr]
> %X10<def> = LDRXui <fi#2>, 0; mem:LD8[%cpyfn.addr]
> %X1<def> = LDRXui <fi#1>, 0; mem:LD8[%data.addr]
> %X8<def> = ADDXrr %X8<kill>, %X9
> %X8<def> = SUBSXri %X8<kill>, 1, 0, %NZCV<imp-def,dead>
> %X9<def> = SUBSXri %X9<kill>, 1, 0, %NZCV<imp-def,dead>
> %X0<def> = BICXrr %X8<kill>, %X9<kill>
> STRXui %X0, <fi#13>, 0; mem:ST8[%arg]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X1<kill>
Deleting identity copy.
> BLR %X10<kill>, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %SP<imp-def>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 6, 0, 0, <fi#13>, 0, 0, <fi#0>, 0, 0, <fi#12>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack13] LD8[FixedStack0] LD8[FixedStack12] LD8[FixedStack11] LD8[FixedStack10]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[%fn.addr]
> %X0<def> = LDRXui <fi#13>, 0; mem:LD8[%arg]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BLR %X8<kill>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 7, 0, 0, <fi#12>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack12] LD8[FixedStack11] LD8[FixedStack10]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X8<def> = LDRXui <fi#12>, 0; mem:LD8[%saved_stack]
> %SP<def> = COPY %X8<kill>
> B <BB#27>
4096B	BB#26: derived from LLVM BB %if.else.69
	    Predecessors according to CFG: BB#24
4112B		%vreg224<def> = LDRXui <fi#0>, 0; mem:LD8[%fn.addr] GPR64:%vreg224
4128B		%vreg225<def> = LDRXui <fi#1>, 0; mem:LD8[%data.addr] GPR64:%vreg225
4144B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4160B		%X0<def> = COPY %vreg225<kill>; GPR64:%vreg225
4176B		BLR %vreg224<kill>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...; GPR64:%vreg224
4192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4224B		STACKMAP 8, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack11] LD8[FixedStack10]
4240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4256B		B <BB#27>
	    Successors according to CFG: BB#27
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[%fn.addr]
> %X0<def> = LDRXui <fi#1>, 0; mem:LD8[%data.addr]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BLR %X8<kill>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 8, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack11] LD8[FixedStack10]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> B <BB#27>
4272B	BB#27: derived from LLVM BB %if.end.70
	    Predecessors according to CFG: BB#26 BB#25
4288B		%vreg244<def> = ADDXri <fi#11>, 0, 0; GPR64sp:%vreg244
4304B		%vreg245<def> = ADDXri %vreg244<kill>, 8, 0; GPR64sp:%vreg245,%vreg244
4320B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4328B		%W1<def> = COPY %WZR
4352B		%X0<def> = COPY %vreg245<kill>; GPR64sp:%vreg245
4384B		BL <ga:@priority_queue_empty_p>, <regmask>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %SP<imp-def>, %W0<imp-def>, ...
4400B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4416B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4432B		STACKMAP 9, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack11] LD8[FixedStack10]
4448B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4464B		%vreg247<def> = COPY %W0; GPR32:%vreg247
4480B		TBNZW %vreg247<kill>, 0, <BB#29>; GPR32:%vreg247
4496B		B <BB#28>
	    Successors according to CFG: BB#29 BB#28
> %X8<def> = ADDXri <fi#11>, 0, 0
> %X0<def> = ADDXri %X8<kill>, 8, 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %W1<def> = COPY %WZR
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BL <ga:@priority_queue_empty_p>, <regmask>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %SP<imp-def>, %W0<imp-def>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 9, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack11] LD8[FixedStack10]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = COPY %W0
Deleting identity copy.
> TBNZW %W0<kill>, 0, <BB#29>
> B <BB#28>
4512B	BB#28: derived from LLVM BB %if.then.72
	    Predecessors according to CFG: BB#27
4528B		%vreg248<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg248
4544B		%vreg249<def> = ADDXri %vreg248<kill>, 1280, 0; GPR64sp:%vreg249 GPR64common:%vreg248
4560B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4576B		%X0<def> = COPY %vreg249<kill>; GPR64sp:%vreg249
4592B		BL <ga:@gomp_mutex_lock>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...
4608B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4624B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4640B		STACKMAP 10, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack11] LD8[FixedStack10]
4656B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4672B		%vreg250<def> = ADDXri <fi#11>, 0, 0; GPR64sp:%vreg250
4688B		%vreg251<def> = ADDXri %vreg250<kill>, 8, 0; GPR64sp:%vreg251,%vreg250
4704B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4720B		%X0<def> = COPY %vreg251<kill>; GPR64sp:%vreg251
4736B		BL <ga:@gomp_clear_parent>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...
4752B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4768B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4784B		STACKMAP 11, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack10]
4800B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4816B		%vreg252<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg252
4832B		%vreg253<def> = ADDXri %vreg252<kill>, 1280, 0; GPR64sp:%vreg253 GPR64common:%vreg252
4848B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4864B		%X0<def> = COPY %vreg253<kill>; GPR64sp:%vreg253
4880B		BL <ga:@gomp_mutex_unlock>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...
4896B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4912B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4928B		STACKMAP 12, 0, ...
4944B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4960B		B <BB#29>
	    Successors according to CFG: BB#29
> %X8<def> = LDRXui <fi#10>, 0; mem:LD8[%team]
> %X0<def> = ADDXri %X8<kill>, 1280, 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BL <ga:@gomp_mutex_lock>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 10, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack11] LD8[FixedStack10]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X8<def> = ADDXri <fi#11>, 0, 0
> %X0<def> = ADDXri %X8<kill>, 8, 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BL <ga:@gomp_clear_parent>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 11, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack10]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X8<def> = LDRXui <fi#10>, 0; mem:LD8[%team]
> %X0<def> = ADDXri %X8<kill>, 1280, 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BL <ga:@gomp_mutex_unlock>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 12, 0, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> B <BB#29>
4976B	BB#29: derived from LLVM BB %if.end.75
	    Predecessors according to CFG: BB#27 BB#28
4992B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5008B		BL <ga:@gomp_end_task>, <regmask>, %SP<imp-use>, %SP<imp-def>, ...
5024B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5040B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5056B		STACKMAP 13, 0, ...
5072B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5088B		B <BB#52>
	    Successors according to CFG: BB#52
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> BL <ga:@gomp_end_task>, <regmask>, %SP<imp-use>, %SP<imp-def>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 13, 0, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> B <BB#52>
5104B	BB#30: derived from LLVM BB %if.else.76
	    Predecessors according to CFG: BB#14
5120B		%vreg47<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg47
5136B		%vreg48<def> = LDRXui %vreg47<kill>, 10; mem:LD8[%task78] GPR64common:%vreg48,%vreg47
5152B		STRXui %vreg48, <fi#15>, 0; mem:ST8[%parent] GPR64common:%vreg48
5168B		%vreg49<def> = LDRXui %vreg48<kill>, 5; mem:LD8[%taskgroup80] GPR64:%vreg49 GPR64common:%vreg48
5232B		%vreg51<def> = LDRBBui <fi#6>, 0; mem:LD1[%flags.addr](align=4) GPR32:%vreg51
5236B		STRXui %vreg49<kill>, <fi#16>, 0; mem:ST8[%taskgroup79] GPR64:%vreg49
5240B		STRXui %XZR, <fi#19>, 0; mem:ST8[%depend_size]
5248B		TBZW %vreg51<kill>, 3, <BB#32>; GPR32:%vreg51
5264B		B <BB#31>
	    Successors according to CFG: BB#31 BB#32
> %X8<def> = LDRXui <fi#9>, 0; mem:LD8[%thr]
> %X8<def> = LDRXui %X8<kill>, 10; mem:LD8[%task78]
> STRXui %X8, <fi#15>, 0; mem:ST8[%parent]
> %X8<def> = LDRXui %X8<kill>, 5; mem:LD8[%taskgroup80]
> %W9<def> = LDRBBui <fi#6>, 0; mem:LD1[%flags.addr](align=4)
> STRXui %X8<kill>, <fi#16>, 0; mem:ST8[%taskgroup79]
> STRXui %XZR, <fi#19>, 0; mem:ST8[%depend_size]
> TBZW %W9<kill>, 3, <BB#32>
> B <BB#31>
5280B	BB#31: derived from LLVM BB %if.then.84
	    Predecessors according to CFG: BB#30
5296B		%vreg52<def> = LDRXui <fi#7>, 0; mem:LD8[%depend.addr] GPR64common:%vreg52
5312B		%vreg53<def> = LDRXui %vreg52<kill>, 0; mem:LD8[%arrayidx] GPR64:%vreg53 GPR64common:%vreg52
5328B		%vreg55:sub_32<def,read-undef> = MOVi32imm 40; GPR64:%vreg55
5360B		%vreg56<def> = MADDXrrr %vreg53<kill>, %vreg55<kill>, %XZR; GPR64:%vreg56,%vreg53,%vreg55
5376B		STRXui %vreg56<kill>, <fi#19>, 0; mem:ST8[%depend_size] GPR64:%vreg56
5392B		B <BB#32>
	    Successors according to CFG: BB#32
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[%depend.addr]
> %X8<def> = LDRXui %X8<kill>, 0; mem:LD8[%arrayidx]
> %W9<def> = MOVi32imm 40, %X9<imp-def>
> %X8<def> = MADDXrrr %X8<kill>, %X9<kill>, %XZR
> STRXui %X8<kill>, <fi#19>, 0; mem:ST8[%depend_size]
> B <BB#32>
5408B	BB#32: derived from LLVM BB %if.end.86
	    Predecessors according to CFG: BB#30 BB#31
5424B		%vreg57<def> = LDRXui <fi#19>, 0; mem:LD8[%depend_size] GPR64:%vreg57
5440B		%vreg58<def> = LDRXui <fi#3>, 0; mem:LD8[%arg_size.addr] GPR64:%vreg58
5472B		%vreg60<def> = LDRXui <fi#4>, 0; mem:LD8[%arg_align.addr] GPR64:%vreg60
5480B		%vreg59<def> = ADDXrr %vreg57<kill>, %vreg58<kill>; GPR64:%vreg59,%vreg57,%vreg58
5488B		%vreg61<def> = ADDXrr %vreg59<kill>, %vreg60<kill>; GPR64common:%vreg61 GPR64:%vreg59,%vreg60
5504B		%vreg62<def> = ADDXri %vreg61<kill>, 207, 0; GPR64sp:%vreg62 GPR64common:%vreg61
5520B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5536B		%X0<def> = COPY %vreg62<kill>; GPR64sp:%vreg62
5552B		BL <ga:@gomp_malloc>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %X0<imp-def>, ...
5568B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5584B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5600B		STACKMAP 14, 0, 0, <fi#17>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#19>, 0, 0, <fi#18>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#14>, 0, 0, <fi#16>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack17] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack2] LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack19] LD8[FixedStack18](align=1) LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack14] LD8[FixedStack16] LD8[FixedStack10] LD8[FixedStack9]
5616B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5632B		%vreg63<def> = COPY %X0; GPR64:%vreg63
5648B		STRXui %vreg63, <fi#14>, 0; mem:ST8[%task77] GPR64:%vreg63
5664B		%vreg64<def> = LDRXui <fi#19>, 0; mem:LD8[%depend_size] GPR64:%vreg64
5696B		%vreg66<def> = LDRXui <fi#4>, 0; mem:LD8[%arg_align.addr] GPR64common:%vreg66
5808B		%vreg72<def> = LDRXui <fi#15>, 0; mem:LD8[%parent] GPR64:%vreg72
5816B		%vreg71<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64:%vreg71
5824B		%vreg65<def> = ADDXrr %vreg63<kill>, %vreg64<kill>; GPR64:%vreg65,%vreg63,%vreg64
5832B		%vreg67<def> = ADDXrr %vreg65<kill>, %vreg66; GPR64common:%vreg67,%vreg66 GPR64:%vreg65
5840B		%vreg68<def> = ADDXri %vreg67<kill>, 207, 0; GPR64common:%vreg68,%vreg67
5848B		%vreg69<def> = SUBSXri %vreg66<kill>, 1, 0, %NZCV<imp-def,dead>; GPR64:%vreg69 GPR64common:%vreg66
5856B		%vreg70<def> = BICXrr %vreg68<kill>, %vreg69<kill>; GPR64:%vreg70,%vreg69 GPR64common:%vreg68
5864B		STRXui %vreg70<kill>, <fi#17>, 0; mem:ST8[%arg81] GPR64:%vreg70
5872B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5888B		%W0<def> = COPY %WZR
5896B		BL <ga:@gomp_icv>, <regmask>, %SP<imp-use>, %W0<imp-use>, %SP<imp-def>, %X0<imp-def>, ...
5904B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5912B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5920B		STACKMAP 15, 0, 0, <fi#17>, 0, 0, <fi#3>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#19>, 0, 0, <fi#18>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#14>, 0, 0, <fi#16>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, %vreg71, %vreg72, ...; mem:LD8[FixedStack17] LD8[FixedStack3] LD8[FixedStack2] LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack19] LD8[FixedStack18](align=1) LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack14] LD8[FixedStack16] LD8[FixedStack10] LD8[FixedStack9] GPR64:%vreg71,%vreg72
5936B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5952B		%vreg74<def> = COPY %X0; GPR64all:%vreg74
5968B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5984B		%X0<def> = COPY %vreg71<kill>; GPR64:%vreg71
6000B		%X1<def> = COPY %vreg72<kill>; GPR64:%vreg72
6016B		%X2<def> = COPY %vreg74<kill>; GPR64all:%vreg74
6032B		BL <ga:@gomp_init_task>, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %X2<imp-use>, %SP<imp-def>, ...
6048B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
6064B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
6080B		STACKMAP 16, 0, 0, <fi#17>, 0, 0, <fi#3>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#19>, 0, 0, <fi#18>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#14>, 0, 0, <fi#16>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack17] LD8[FixedStack3] LD8[FixedStack2] LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack19] LD8[FixedStack18](align=1) LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack14] LD8[FixedStack16] LD8[FixedStack10] LD8[FixedStack9]
6096B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
6112B		%vreg75<def> = LDRWui <fi#8>, 0; mem:LD4[%priority.addr] GPR32:%vreg75
6128B		%vreg76<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64common:%vreg76
6144B		STRWui %vreg75<kill>, %vreg76<kill>, 22; mem:ST4[%priority99] GPR32:%vreg75 GPR64common:%vreg76
6160B		%vreg77<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64common:%vreg77
6176B		%vreg78<def> = MOVi32imm 1; GPR32:%vreg78
6192B		STRWui %vreg78<kill>, %vreg77<kill>, 50; mem:ST4[%kind100] GPR32:%vreg78 GPR64common:%vreg77
6208B		%vreg79<def> = LDRXui <fi#15>, 0; mem:LD8[%parent] GPR64common:%vreg79
6224B		%vreg80<def> = LDRBBui %vreg79<kill>, 204; mem:LD1[%in_tied_task101] GPR32:%vreg80 GPR64common:%vreg79
6240B		%vreg81<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64common:%vreg81
6256B		%vreg82<def> = ANDWri %vreg80<kill>, 0; GPR32common:%vreg82 GPR32:%vreg80
6272B		STRBBui %vreg82<kill>, %vreg81<kill>, 204; mem:ST1[%in_tied_task103] GPR32common:%vreg82 GPR64common:%vreg81
6288B		%vreg83<def> = LDRXui <fi#16>, 0; mem:LD8[%taskgroup79] GPR64:%vreg83
6304B		%vreg84<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64common:%vreg84
6320B		STRXui %vreg83<kill>, %vreg84<kill>, 5; mem:ST8[%taskgroup105] GPR64:%vreg83 GPR64common:%vreg84
6336B		%vreg85<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64:%vreg85
6352B		%vreg86<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg86
6368B		STRXui %vreg85<kill>, %vreg86<kill>, 10; mem:ST8[%task106] GPR64:%vreg85 GPR64common:%vreg86
6384B		%vreg87<def> = LDRXui <fi#2>, 0; mem:LD8[%cpyfn.addr] GPR64:%vreg87
6400B		CBZX %vreg87<kill>, <BB#34>; GPR64:%vreg87
6416B		B <BB#33>
	    Successors according to CFG: BB#33 BB#34
> %X8<def> = LDRXui <fi#19>, 0; mem:LD8[%depend_size]
> %X9<def> = LDRXui <fi#3>, 0; mem:LD8[%arg_size.addr]
> %X10<def> = LDRXui <fi#4>, 0; mem:LD8[%arg_align.addr]
> %X8<def> = ADDXrr %X8<kill>, %X9<kill>
> %X8<def> = ADDXrr %X8<kill>, %X10<kill>
> %X0<def> = ADDXri %X8<kill>, 207, 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BL <ga:@gomp_malloc>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %X0<imp-def>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 14, 0, 0, <fi#17>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#19>, 0, 0, <fi#18>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#14>, 0, 0, <fi#16>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack17] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack2] LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack19] LD8[FixedStack18](align=1) LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack14] LD8[FixedStack16] LD8[FixedStack10] LD8[FixedStack9]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0
Deleting identity copy.
> STRXui %X0, <fi#14>, 0; mem:ST8[%task77]
> %X8<def> = LDRXui <fi#19>, 0; mem:LD8[%depend_size]
> %X9<def> = LDRXui <fi#4>, 0; mem:LD8[%arg_align.addr]
> %X20<def> = LDRXui <fi#15>, 0; mem:LD8[%parent]
> %X21<def> = LDRXui <fi#14>, 0; mem:LD8[%task77]
> %X8<def> = ADDXrr %X0<kill>, %X8<kill>
> %X8<def> = ADDXrr %X8<kill>, %X9
> %X8<def> = ADDXri %X8<kill>, 207, 0
> %X9<def> = SUBSXri %X9<kill>, 1, 0, %NZCV<imp-def,dead>
> %X8<def> = BICXrr %X8<kill>, %X9<kill>
> STRXui %X8<kill>, <fi#17>, 0; mem:ST8[%arg81]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = COPY %WZR
> BL <ga:@gomp_icv>, <regmask>, %SP<imp-use>, %W0<imp-use>, %SP<imp-def>, %X0<imp-def>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 15, 0, 0, <fi#17>, 0, 0, <fi#3>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#19>, 0, 0, <fi#18>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#14>, 0, 0, <fi#16>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, %X21, %X20, ...; mem:LD8[FixedStack17] LD8[FixedStack3] LD8[FixedStack2] LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack19] LD8[FixedStack18](align=1) LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack14] LD8[FixedStack16] LD8[FixedStack10] LD8[FixedStack9]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X2<def> = COPY %X0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X21<kill>
> %X1<def> = COPY %X20<kill>
> %X2<def> = COPY %X2<kill>
Deleting identity copy.
> BL <ga:@gomp_init_task>, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %X2<imp-use>, %SP<imp-def>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 16, 0, 0, <fi#17>, 0, 0, <fi#3>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#19>, 0, 0, <fi#18>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#14>, 0, 0, <fi#16>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack17] LD8[FixedStack3] LD8[FixedStack2] LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack19] LD8[FixedStack18](align=1) LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack14] LD8[FixedStack16] LD8[FixedStack10] LD8[FixedStack9]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W8<def> = LDRWui <fi#8>, 0; mem:LD4[%priority.addr]
> %X9<def> = LDRXui <fi#14>, 0; mem:LD8[%task77]
> STRWui %W8<kill>, %X9<kill>, 22; mem:ST4[%priority99]
> %X8<def> = LDRXui <fi#14>, 0; mem:LD8[%task77]
> %W9<def> = MOVi32imm 1
> STRWui %W9<kill>, %X8<kill>, 50; mem:ST4[%kind100]
> %X8<def> = LDRXui <fi#15>, 0; mem:LD8[%parent]
> %W8<def> = LDRBBui %X8<kill>, 204; mem:LD1[%in_tied_task101]
> %X9<def> = LDRXui <fi#14>, 0; mem:LD8[%task77]
> %W8<def> = ANDWri %W8<kill>, 0
> STRBBui %W8<kill>, %X9<kill>, 204; mem:ST1[%in_tied_task103]
> %X8<def> = LDRXui <fi#16>, 0; mem:LD8[%taskgroup79]
> %X9<def> = LDRXui <fi#14>, 0; mem:LD8[%task77]
> STRXui %X8<kill>, %X9<kill>, 5; mem:ST8[%taskgroup105]
> %X8<def> = LDRXui <fi#14>, 0; mem:LD8[%task77]
> %X9<def> = LDRXui <fi#9>, 0; mem:LD8[%thr]
> STRXui %X8<kill>, %X9<kill>, 10; mem:ST8[%task106]
> %X8<def> = LDRXui <fi#2>, 0; mem:LD8[%cpyfn.addr]
> CBZX %X8<kill>, <BB#34>
> B <BB#33>
6432B	BB#33: derived from LLVM BB %if.then.108
	    Predecessors according to CFG: BB#32
6448B		%vreg91<def> = LDRXui <fi#2>, 0; mem:LD8[%cpyfn.addr] GPR64:%vreg91
6464B		%vreg92<def> = LDRXui <fi#17>, 0; mem:LD8[%arg81] GPR64:%vreg92
6480B		%vreg93<def> = LDRXui <fi#1>, 0; mem:LD8[%data.addr] GPR64:%vreg93
6496B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
6512B		%X0<def> = COPY %vreg92<kill>; GPR64:%vreg92
6528B		%X1<def> = COPY %vreg93<kill>; GPR64:%vreg93
6544B		BLR %vreg91<kill>, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %SP<imp-def>, ...; GPR64:%vreg91
6560B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
6576B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
6592B		STACKMAP 17, 0, 0, <fi#17>, 0, 0, <fi#7>, 0, 0, <fi#19>, 0, 0, <fi#18>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#14>, 0, 0, <fi#16>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack17] LD8[FixedStack7] LD8[FixedStack19] LD8[FixedStack18](align=1) LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack14] LD8[FixedStack16] LD8[FixedStack10] LD8[FixedStack9]
6608B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
6624B		%vreg94<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64common:%vreg94
6640B		%vreg95<def> = MOVi32imm 1; GPR32:%vreg95
6656B		STRBBui %vreg95<kill>, %vreg94<kill>, 206; mem:ST1[%copy_ctors_done] GPR32:%vreg95 GPR64common:%vreg94
6672B		B <BB#35>
	    Successors according to CFG: BB#35
> %X8<def> = LDRXui <fi#2>, 0; mem:LD8[%cpyfn.addr]
> %X0<def> = LDRXui <fi#17>, 0; mem:LD8[%arg81]
> %X1<def> = LDRXui <fi#1>, 0; mem:LD8[%data.addr]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X1<kill>
Deleting identity copy.
> BLR %X8<kill>, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %SP<imp-def>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 17, 0, 0, <fi#17>, 0, 0, <fi#7>, 0, 0, <fi#19>, 0, 0, <fi#18>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#14>, 0, 0, <fi#16>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack17] LD8[FixedStack7] LD8[FixedStack19] LD8[FixedStack18](align=1) LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack14] LD8[FixedStack16] LD8[FixedStack10] LD8[FixedStack9]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X8<def> = LDRXui <fi#14>, 0; mem:LD8[%task77]
> %W9<def> = MOVi32imm 1
> STRBBui %W9<kill>, %X8<kill>, 206; mem:ST1[%copy_ctors_done]
> B <BB#35>
6688B	BB#34: derived from LLVM BB %if.else.109
	    Predecessors according to CFG: BB#32
6704B		%vreg88<def> = LDRXui <fi#17>, 0; mem:LD8[%arg81] GPR64:%vreg88
6720B		%vreg89<def> = LDRXui <fi#1>, 0; mem:LD8[%data.addr] GPR64:%vreg89
6736B		%vreg90<def> = LDRXui <fi#3>, 0; mem:LD8[%arg_size.addr] GPR64:%vreg90
6752B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
6768B		%X0<def> = COPY %vreg88<kill>; GPR64:%vreg88
6784B		%X1<def> = COPY %vreg89<kill>; GPR64:%vreg89
6800B		%X2<def> = COPY %vreg90<kill>; GPR64:%vreg90
6816B		BL <es:memcpy>, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %X2<imp-use>, %SP<imp-def>, ...
6832B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
6848B		B <BB#35>
	    Successors according to CFG: BB#35
> %X0<def> = LDRXui <fi#17>, 0; mem:LD8[%arg81]
> %X1<def> = LDRXui <fi#1>, 0; mem:LD8[%data.addr]
> %X2<def> = LDRXui <fi#3>, 0; mem:LD8[%arg_size.addr]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X1<kill>
Deleting identity copy.
> %X2<def> = COPY %X2<kill>
Deleting identity copy.
> BL <es:memcpy>, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %X2<imp-use>, %SP<imp-def>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> B <BB#35>
6864B	BB#35: derived from LLVM BB %if.end.110
	    Predecessors according to CFG: BB#34 BB#33
6880B		%vreg96<def> = LDRXui <fi#15>, 0; mem:LD8[%parent] GPR64:%vreg96
6896B		%vreg97<def> = LDRXui <fi#9>, 0; mem:LD8[%thr] GPR64common:%vreg97
6912B		STRXui %vreg96<kill>, %vreg97<kill>, 10; mem:ST8[%task111] GPR64:%vreg96 GPR64common:%vreg97
6928B		%vreg98<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64common:%vreg98
6944B		%vreg99<def> = MOVi32imm 2; GPR32:%vreg99
6960B		STRWui %vreg99<kill>, %vreg98<kill>, 50; mem:ST4[%kind112] GPR32:%vreg99 GPR64common:%vreg98
6976B		%vreg100<def> = LDRXui <fi#0>, 0; mem:LD8[%fn.addr] GPR64:%vreg100
6992B		%vreg101<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64common:%vreg101
7008B		STRXui %vreg100<kill>, %vreg101<kill>, 23; mem:ST8[%fn113] GPR64:%vreg100 GPR64common:%vreg101
7024B		%vreg102<def> = LDRXui <fi#17>, 0; mem:LD8[%arg81] GPR64:%vreg102
7040B		%vreg103<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64common:%vreg103
7056B		STRXui %vreg102<kill>, %vreg103<kill>, 24; mem:ST8[%fn_data] GPR64:%vreg102 GPR64common:%vreg103
7072B		%vreg104<def> = LDRWui <fi#6>, 0; mem:LD4[%flags.addr] GPR32:%vreg104
7104B		%vreg106<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64common:%vreg106
7112B		%vreg105<def> = UBFMWri %vreg104<kill>, 1, 1; GPR32:%vreg105,%vreg104
7120B		STRBBui %vreg105<kill>, %vreg106<kill>, 205; mem:ST1[%final_task116] GPR32:%vreg105 GPR64common:%vreg106
7136B		%vreg107<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg107
7152B		%vreg108<def> = ADDXri %vreg107<kill>, 1280, 0; GPR64sp:%vreg108 GPR64common:%vreg107
7168B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
7184B		%X0<def> = COPY %vreg108<kill>; GPR64sp:%vreg108
7200B		BL <ga:@gomp_mutex_lock>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...
7216B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
7232B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
7248B		STACKMAP 18, 0, 0, <fi#7>, 0, 0, <fi#19>, 0, 0, <fi#18>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#14>, 0, 0, <fi#16>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack7] LD8[FixedStack19] LD8[FixedStack18](align=1) LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack14] LD8[FixedStack16] LD8[FixedStack10]
7264B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
7280B		%vreg109<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg109
7296B		%vreg110<def> = ADDXri %vreg109<kill>, 128, 0; GPR64sp:%vreg110 GPR64common:%vreg109
7312B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
7328B		%X0<def> = COPY %vreg110<kill>; GPR64sp:%vreg110
7344B		BL <ga:@gomp_team_barrier_cancelled>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>, ...
7360B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
7376B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
7392B		STACKMAP 19, 0, 0, <fi#7>, 0, 0, <fi#19>, 0, 0, <fi#18>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#14>, 0, 0, <fi#16>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack7] LD8[FixedStack19] LD8[FixedStack18](align=1) LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack14] LD8[FixedStack16] LD8[FixedStack10]
7408B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
7424B		%vreg111<def> = COPY %W0; GPR32:%vreg111
7440B		TBNZW %vreg111<kill>, 0, <BB#38>; GPR32:%vreg111
7456B		B <BB#36>
	    Successors according to CFG: BB#38 BB#36
> %X8<def> = LDRXui <fi#15>, 0; mem:LD8[%parent]
> %X9<def> = LDRXui <fi#9>, 0; mem:LD8[%thr]
> STRXui %X8<kill>, %X9<kill>, 10; mem:ST8[%task111]
> %X8<def> = LDRXui <fi#14>, 0; mem:LD8[%task77]
> %W9<def> = MOVi32imm 2
> STRWui %W9<kill>, %X8<kill>, 50; mem:ST4[%kind112]
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[%fn.addr]
> %X9<def> = LDRXui <fi#14>, 0; mem:LD8[%task77]
> STRXui %X8<kill>, %X9<kill>, 23; mem:ST8[%fn113]
> %X8<def> = LDRXui <fi#17>, 0; mem:LD8[%arg81]
> %X9<def> = LDRXui <fi#14>, 0; mem:LD8[%task77]
> STRXui %X8<kill>, %X9<kill>, 24; mem:ST8[%fn_data]
> %W8<def> = LDRWui <fi#6>, 0; mem:LD4[%flags.addr]
> %X9<def> = LDRXui <fi#14>, 0; mem:LD8[%task77]
> %W8<def> = UBFMWri %W8<kill>, 1, 1
> STRBBui %W8<kill>, %X9<kill>, 205; mem:ST1[%final_task116]
> %X8<def> = LDRXui <fi#10>, 0; mem:LD8[%team]
> %X0<def> = ADDXri %X8<kill>, 1280, 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BL <ga:@gomp_mutex_lock>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 18, 0, 0, <fi#7>, 0, 0, <fi#19>, 0, 0, <fi#18>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#14>, 0, 0, <fi#16>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack7] LD8[FixedStack19] LD8[FixedStack18](align=1) LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack14] LD8[FixedStack16] LD8[FixedStack10]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X8<def> = LDRXui <fi#10>, 0; mem:LD8[%team]
> %X0<def> = ADDXri %X8<kill>, 128, 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BL <ga:@gomp_team_barrier_cancelled>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 19, 0, 0, <fi#7>, 0, 0, <fi#19>, 0, 0, <fi#18>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#14>, 0, 0, <fi#16>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack7] LD8[FixedStack19] LD8[FixedStack18](align=1) LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack14] LD8[FixedStack16] LD8[FixedStack10]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = COPY %W0
Deleting identity copy.
> TBNZW %W0<kill>, 0, <BB#38>
> B <BB#36>
7472B	BB#36: derived from LLVM BB %lor.lhs.false.122
	    Predecessors according to CFG: BB#35
7488B		%vreg113<def> = LDRXui <fi#16>, 0; mem:LD8[%taskgroup79] GPR64:%vreg113
7536B		%vreg256<def> = COPY %WZR; GPR32common:%vreg256
7552B		CBZX %vreg113<kill>, <BB#39>; GPR64:%vreg113
7568B		B <BB#37>
	    Successors according to CFG: BB#37 BB#39
> %X9<def> = LDRXui <fi#16>, 0; mem:LD8[%taskgroup79]
> %W8<def> = COPY %WZR
> CBZX %X9<kill>, <BB#39>
> B <BB#37>
7584B	BB#37: derived from LLVM BB %land.lhs.true.124
	    Predecessors according to CFG: BB#36
7600B		%vreg116<def> = LDRXui <fi#16>, 0; mem:LD8[%taskgroup79] GPR64common:%vreg116
7616B		%vreg117<def> = LDRBBui %vreg116<kill>, 41; mem:LD1[%cancelled125] GPR32:%vreg117 GPR64common:%vreg116
7664B		%vreg256<def> = COPY %WZR; GPR32common:%vreg256
7680B		TBZW %vreg117<kill>, 0, <BB#39>; GPR32:%vreg117
7696B		B <BB#38>
	    Successors according to CFG: BB#38 BB#39
> %X8<def> = LDRXui <fi#16>, 0; mem:LD8[%taskgroup79]
> %W9<def> = LDRBBui %X8<kill>, 41; mem:LD1[%cancelled125]
> %W8<def> = COPY %WZR
> TBZW %W9<kill>, 0, <BB#39>
> B <BB#38>
7712B	BB#38: derived from LLVM BB %land.rhs
	    Predecessors according to CFG: BB#35 BB#37
7728B		%vreg119<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64common:%vreg119
7744B		%vreg120<def> = LDRBBui %vreg119<kill>, 206; mem:LD1[%copy_ctors_done128] GPR32:%vreg120 GPR64common:%vreg119
7760B		%vreg256<def> = EORWri %vreg120<kill>, 0; GPR32common:%vreg256 GPR32:%vreg120
7808B		B <BB#39>
	    Successors according to CFG: BB#39
> %X8<def> = LDRXui <fi#14>, 0; mem:LD8[%task77]
> %W8<def> = LDRBBui %X8<kill>, 206; mem:LD1[%copy_ctors_done128]
> %W8<def> = EORWri %W8<kill>, 0
> B <BB#39>
7824B	BB#39: derived from LLVM BB %land.end
	    Live Ins: %W8
	    Predecessors according to CFG: BB#36 BB#37 BB#38
7856B		TBZW %vreg256<kill>, 0, <BB#41>; GPR32common:%vreg256
7872B		B <BB#40>
	    Successors according to CFG: BB#40 BB#41
> TBZW %W8<kill>, 0, <BB#41>
> B <BB#40>
7888B	BB#40: derived from LLVM BB %if.then.132
	    Predecessors according to CFG: BB#39
7904B		%vreg183<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg183
7920B		%vreg184<def> = ADDXri %vreg183<kill>, 1280, 0; GPR64sp:%vreg184 GPR64common:%vreg183
7936B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
7952B		%X0<def> = COPY %vreg184<kill>; GPR64sp:%vreg184
7968B		BL <ga:@gomp_mutex_unlock>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...
7984B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
8000B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
8016B		STACKMAP 20, 0, 0, <fi#14>, 0, ...; mem:LD8[FixedStack14]
8032B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
8048B		%vreg185<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64:%vreg185
8064B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
8080B		%X0<def> = COPY %vreg185<kill>; GPR64:%vreg185
8096B		BL <ga:@gomp_finish_task>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...
8112B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
8128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
8144B		STACKMAP 21, 0, 0, <fi#14>, 0, ...; mem:LD8[FixedStack14]
8160B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
8176B		%vreg186<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64:%vreg186
8192B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
8208B		%X0<def> = COPY %vreg186<kill>; GPR64:%vreg186
8224B		BL <ga:@free>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...
8240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
8256B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
8272B		STACKMAP 22, 0, ...
8288B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
8304B		B <BB#52>
	    Successors according to CFG: BB#52
> %X8<def> = LDRXui <fi#10>, 0; mem:LD8[%team]
> %X0<def> = ADDXri %X8<kill>, 1280, 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BL <ga:@gomp_mutex_unlock>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 20, 0, 0, <fi#14>, 0, ...; mem:LD8[FixedStack14]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = LDRXui <fi#14>, 0; mem:LD8[%task77]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BL <ga:@gomp_finish_task>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 21, 0, 0, <fi#14>, 0, ...; mem:LD8[FixedStack14]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = LDRXui <fi#14>, 0; mem:LD8[%task77]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BL <ga:@free>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 22, 0, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> B <BB#52>
8320B	BB#41: derived from LLVM BB %if.end.134
	    Predecessors according to CFG: BB#39
8336B		%vreg122<def> = LDRXui <fi#16>, 0; mem:LD8[%taskgroup79] GPR64:%vreg122
8352B		CBZX %vreg122<kill>, <BB#43>; GPR64:%vreg122
8368B		B <BB#42>
	    Successors according to CFG: BB#42 BB#43
> %X8<def> = LDRXui <fi#16>, 0; mem:LD8[%taskgroup79]
> CBZX %X8<kill>, <BB#43>
> B <BB#42>
8384B	BB#42: derived from LLVM BB %if.then.136
	    Predecessors according to CFG: BB#41
8400B		%vreg123<def> = LDRXui <fi#16>, 0; mem:LD8[%taskgroup79] GPR64common:%vreg123
8416B		%vreg124<def> = LDRXui %vreg123, 6; mem:LD8[%num_children] GPR64common:%vreg124,%vreg123
8432B		%vreg125<def> = ADDXri %vreg124<kill>, 1, 0; GPR64common:%vreg125,%vreg124
8448B		STRXui %vreg125<kill>, %vreg123<kill>, 6; mem:ST8[%num_children] GPR64common:%vreg125,%vreg123
8464B		B <BB#43>
	    Successors according to CFG: BB#43
> %X8<def> = LDRXui <fi#16>, 0; mem:LD8[%taskgroup79]
> %X9<def> = LDRXui %X8, 6; mem:LD8[%num_children]
> %X9<def> = ADDXri %X9<kill>, 1, 0
> STRXui %X9<kill>, %X8<kill>, 6; mem:ST8[%num_children]
> B <BB#43>
8480B	BB#43: derived from LLVM BB %if.end.137
	    Predecessors according to CFG: BB#41 BB#42
8496B		%vreg126<def> = LDRXui <fi#19>, 0; mem:LD8[%depend_size] GPR64:%vreg126
8512B		CBZX %vreg126<kill>, <BB#47>; GPR64:%vreg126
8528B		B <BB#44>
	    Successors according to CFG: BB#44 BB#47
> %X8<def> = LDRXui <fi#19>, 0; mem:LD8[%depend_size]
> CBZX %X8<kill>, <BB#47>
> B <BB#44>
8544B	BB#44: derived from LLVM BB %if.then.139
	    Predecessors according to CFG: BB#43
8560B		%vreg127<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64:%vreg127
8576B		%vreg128<def> = LDRXui <fi#15>, 0; mem:LD8[%parent] GPR64:%vreg128
8592B		%vreg129<def> = LDRXui <fi#7>, 0; mem:LD8[%depend.addr] GPR64:%vreg129
8608B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
8624B		%X0<def> = COPY %vreg127<kill>; GPR64:%vreg127
8640B		%X1<def> = COPY %vreg128<kill>; GPR64:%vreg128
8656B		%X2<def> = COPY %vreg129<kill>; GPR64:%vreg129
8672B		BL <ga:@gomp_task_handle_depend>, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %X2<imp-use>, %SP<imp-def>, ...
8688B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
8704B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
8720B		STACKMAP 23, 0, 0, <fi#18>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#14>, 0, 0, <fi#16>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack18](align=1) LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack14] LD8[FixedStack16] LD8[FixedStack10]
8736B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
8752B		%vreg130<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64common:%vreg130
8768B		%vreg131<def> = LDRXui %vreg130<kill>, 10; mem:LD8[%num_dependees] GPR64:%vreg131 GPR64common:%vreg130
8784B		CBZX %vreg131<kill>, <BB#46>; GPR64:%vreg131
8800B		B <BB#45>
	    Successors according to CFG: BB#45 BB#46
> %X0<def> = LDRXui <fi#14>, 0; mem:LD8[%task77]
> %X1<def> = LDRXui <fi#15>, 0; mem:LD8[%parent]
> %X2<def> = LDRXui <fi#7>, 0; mem:LD8[%depend.addr]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X1<kill>
Deleting identity copy.
> %X2<def> = COPY %X2<kill>
Deleting identity copy.
> BL <ga:@gomp_task_handle_depend>, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %X2<imp-use>, %SP<imp-def>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 23, 0, 0, <fi#18>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#14>, 0, 0, <fi#16>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack18](align=1) LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack14] LD8[FixedStack16] LD8[FixedStack10]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X8<def> = LDRXui <fi#14>, 0; mem:LD8[%task77]
> %X8<def> = LDRXui %X8<kill>, 10; mem:LD8[%num_dependees]
> CBZX %X8<kill>, <BB#46>
> B <BB#45>
8816B	BB#45: derived from LLVM BB %if.then.141
	    Predecessors according to CFG: BB#44
8832B		%vreg181<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg181
8848B		%vreg182<def> = ADDXri %vreg181<kill>, 1280, 0; GPR64sp:%vreg182 GPR64common:%vreg181
8864B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
8880B		%X0<def> = COPY %vreg182<kill>; GPR64sp:%vreg182
8896B		BL <ga:@gomp_mutex_unlock>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...
8912B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
8928B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
8944B		STACKMAP 24, 0, ...
8960B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
8976B		B <BB#52>
	    Successors according to CFG: BB#52
> %X8<def> = LDRXui <fi#10>, 0; mem:LD8[%team]
> %X0<def> = ADDXri %X8<kill>, 1280, 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BL <ga:@gomp_mutex_unlock>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 24, 0, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> B <BB#52>
8992B	BB#46: derived from LLVM BB %if.end.143
	    Predecessors according to CFG: BB#44
9008B		B <BB#47>
	    Successors according to CFG: BB#47
> B <BB#47>
9024B	BB#47: derived from LLVM BB %if.end.144
	    Predecessors according to CFG: BB#43 BB#46
9072B		%vreg134<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64common:%vreg134
9080B		%vreg132<def> = LDRXui <fi#15>, 0; mem:LD8[%parent] GPR64common:%vreg132
9088B		%vreg135<def> = LDRWui <fi#8>, 0; mem:LD4[%priority.addr] GPR32:%vreg135
9104B		%vreg136<def> = LDRBBui %vreg134, 207; mem:LD1[%parent_depends_on] GPR32:%vreg136 GPR64common:%vreg134
9112B		%vreg133<def> = ADDXri %vreg132<kill>, 8, 0; GPR64sp:%vreg133 GPR64common:%vreg132
9120B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
9128B		%W4<def> = COPY %WZR
9132B		%W5<def> = COPY %WZR
9136B		%vreg137<def> = ANDWri %vreg136<kill>, 0; GPR32sp:%vreg137 GPR32:%vreg136
9184B		%W0<def> = MOVi32imm 1
9200B		%X1<def> = COPY %vreg133<kill>; GPR64sp:%vreg133
9216B		%X2<def> = COPY %vreg134<kill>; GPR64common:%vreg134
9232B		%W3<def> = COPY %vreg135<kill>; GPR32:%vreg135
9280B		%W6<def> = COPY %vreg137<kill>; GPR32sp:%vreg137
9296B		BL <ga:@priority_queue_insert>, <regmask>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use>, %X2<imp-use>, %W3<imp-use>, %W4<imp-use>, %W5<imp-use>, %W6<imp-use>, %SP<imp-def>, ...
9312B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
9328B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
9344B		STACKMAP 25, 0, 0, <fi#18>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#14>, 0, 0, <fi#16>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack18](align=1) LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack14] LD8[FixedStack16] LD8[FixedStack10]
9360B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
9376B		%vreg140<def> = LDRXui <fi#16>, 0; mem:LD8[%taskgroup79] GPR64:%vreg140
9392B		CBZX %vreg140<kill>, <BB#49>; GPR64:%vreg140
9408B		B <BB#48>
	    Successors according to CFG: BB#48 BB#49
> %X2<def> = LDRXui <fi#14>, 0; mem:LD8[%task77]
> %X8<def> = LDRXui <fi#15>, 0; mem:LD8[%parent]
> %W3<def> = LDRWui <fi#8>, 0; mem:LD4[%priority.addr]
> %W9<def> = LDRBBui %X2, 207; mem:LD1[%parent_depends_on]
> %X1<def> = ADDXri %X8<kill>, 8, 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %W4<def> = COPY %WZR
> %W5<def> = COPY %WZR
> %W6<def> = ANDWri %W9<kill>, 0
> %W0<def> = MOVi32imm 1
> %X1<def> = COPY %X1<kill>
Deleting identity copy.
> %X2<def> = COPY %X2<kill>
Deleting identity copy.
> %W3<def> = COPY %W3<kill>
Deleting identity copy.
> %W6<def> = COPY %W6<kill>
Deleting identity copy.
> BL <ga:@priority_queue_insert>, <regmask>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use>, %X2<imp-use>, %W3<imp-use>, %W4<imp-use>, %W5<imp-use>, %W6<imp-use>, %SP<imp-def>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 25, 0, 0, <fi#18>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#14>, 0, 0, <fi#16>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack18](align=1) LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack14] LD8[FixedStack16] LD8[FixedStack10]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X8<def> = LDRXui <fi#16>, 0; mem:LD8[%taskgroup79]
> CBZX %X8<kill>, <BB#49>
> B <BB#48>
9424B	BB#48: derived from LLVM BB %if.then.148
	    Predecessors according to CFG: BB#47
9472B		%vreg143<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64common:%vreg143
9480B		%vreg141<def> = LDRXui <fi#16>, 0; mem:LD8[%taskgroup79] GPR64common:%vreg141
9488B		%vreg144<def> = LDRWui <fi#8>, 0; mem:LD4[%priority.addr] GPR32:%vreg144
9504B		%vreg145<def> = LDRBBui %vreg143, 207; mem:LD1[%parent_depends_on149] GPR32:%vreg145 GPR64common:%vreg143
9512B		%vreg142<def> = ADDXri %vreg141<kill>, 8, 0; GPR64sp:%vreg142 GPR64common:%vreg141
9520B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
9528B		%W4<def> = COPY %WZR
9532B		%W5<def> = COPY %WZR
9536B		%vreg146<def> = ANDWri %vreg145<kill>, 0; GPR32sp:%vreg146 GPR32:%vreg145
9584B		%W0<def> = MOVi32imm 2
9600B		%X1<def> = COPY %vreg142<kill>; GPR64sp:%vreg142
9616B		%X2<def> = COPY %vreg143<kill>; GPR64common:%vreg143
9632B		%W3<def> = COPY %vreg144<kill>; GPR32:%vreg144
9680B		%W6<def> = COPY %vreg146<kill>; GPR32sp:%vreg146
9696B		BL <ga:@priority_queue_insert>, <regmask>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use>, %X2<imp-use>, %W3<imp-use>, %W4<imp-use>, %W5<imp-use>, %W6<imp-use>, %SP<imp-def>, ...
9712B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
9728B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
9744B		STACKMAP 26, 0, 0, <fi#18>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#14>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack18](align=1) LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack14] LD8[FixedStack10]
9760B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
9776B		B <BB#49>
	    Successors according to CFG: BB#49
> %X2<def> = LDRXui <fi#14>, 0; mem:LD8[%task77]
> %X8<def> = LDRXui <fi#16>, 0; mem:LD8[%taskgroup79]
> %W3<def> = LDRWui <fi#8>, 0; mem:LD4[%priority.addr]
> %W9<def> = LDRBBui %X2, 207; mem:LD1[%parent_depends_on149]
> %X1<def> = ADDXri %X8<kill>, 8, 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %W4<def> = COPY %WZR
> %W5<def> = COPY %WZR
> %W6<def> = ANDWri %W9<kill>, 0
> %W0<def> = MOVi32imm 2
> %X1<def> = COPY %X1<kill>
Deleting identity copy.
> %X2<def> = COPY %X2<kill>
Deleting identity copy.
> %W3<def> = COPY %W3<kill>
Deleting identity copy.
> %W6<def> = COPY %W6<kill>
Deleting identity copy.
> BL <ga:@priority_queue_insert>, <regmask>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use>, %X2<imp-use>, %W3<imp-use>, %W4<imp-use>, %W5<imp-use>, %W6<imp-use>, %SP<imp-def>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 26, 0, 0, <fi#18>, 0, 0, <fi#15>, 0, 0, <fi#8>, 0, 0, <fi#14>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack18](align=1) LD8[FixedStack15] LD8[FixedStack8](align=4) LD8[FixedStack14] LD8[FixedStack10]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> B <BB#49>
9792B	BB#49: derived from LLVM BB %if.end.151
	    Predecessors according to CFG: BB#47 BB#48
9840B		%vreg151<def> = LDRXui <fi#14>, 0; mem:LD8[%task77] GPR64common:%vreg151
9848B		%vreg149<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg149
9856B		%vreg152<def> = LDRWui <fi#8>, 0; mem:LD4[%priority.addr] GPR32:%vreg152
9872B		%vreg153<def> = LDRBBui %vreg151, 207; mem:LD1[%parent_depends_on152] GPR32:%vreg153 GPR64common:%vreg151
9880B		%vreg150<def> = ADDXri %vreg149<kill>, 1288, 0; GPR64sp:%vreg150 GPR64common:%vreg149
9888B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
9896B		%W0<def> = COPY %WZR
9900B		%W5<def> = COPY %WZR
9904B		%vreg154<def> = ANDWri %vreg153<kill>, 0; GPR32sp:%vreg154 GPR32:%vreg153
9912B		%W4<def> = MOVi32imm 1
9968B		%X1<def> = COPY %vreg150<kill>; GPR64sp:%vreg150
9984B		%X2<def> = COPY %vreg151<kill>; GPR64common:%vreg151
10000B		%W3<def> = COPY %vreg152<kill>; GPR32:%vreg152
10048B		%W6<def> = COPY %vreg154<kill>; GPR32sp:%vreg154
10064B		BL <ga:@priority_queue_insert>, <regmask>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use>, %X2<imp-use>, %W3<imp-use>, %W4<imp-use>, %W5<imp-use>, %W6<imp-use>, %SP<imp-def>, ...
10080B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
10096B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
10112B		STACKMAP 27, 0, 0, <fi#18>, 0, 0, <fi#15>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack18](align=1) LD8[FixedStack15] LD8[FixedStack10]
10128B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
10144B		%vreg157<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg157
10160B		%vreg158<def> = LDRWui %vreg157, 330; mem:LD4[%task_count154] GPR32common:%vreg158 GPR64common:%vreg157
10176B		%vreg159<def> = ADDWri %vreg158<kill>, 1, 0; GPR32common:%vreg159,%vreg158
10192B		STRWui %vreg159<kill>, %vreg157<kill>, 330; mem:ST4[%task_count154] GPR32common:%vreg159 GPR64common:%vreg157
10208B		%vreg160<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg160
10224B		%vreg161<def> = LDRWui %vreg160, 331; mem:LD4[%task_queued_count] GPR32common:%vreg161 GPR64common:%vreg160
10240B		%vreg162<def> = ADDWri %vreg161<kill>, 1, 0; GPR32common:%vreg162,%vreg161
10256B		STRWui %vreg162<kill>, %vreg160<kill>, 331; mem:ST4[%task_queued_count] GPR32common:%vreg162 GPR64common:%vreg160
10272B		%vreg163<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg163
10288B		%vreg164<def> = ADDXri %vreg163<kill>, 128, 0; GPR64sp:%vreg164 GPR64common:%vreg163
10304B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
10320B		%X0<def> = COPY %vreg164<kill>; GPR64sp:%vreg164
10336B		BL <ga:@gomp_team_barrier_set_task_pending>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...
10352B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
10368B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
10384B		STACKMAP 28, 0, 0, <fi#18>, 0, 0, <fi#15>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack18](align=1) LD8[FixedStack15] LD8[FixedStack10]
10400B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
10448B		%vreg167<def> = LDRXui <fi#15>, 0; mem:LD8[%parent] GPR64common:%vreg167
10456B		%vreg165<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg165
10464B		%vreg168<def> = LDRBBui %vreg167<kill>, 204; mem:LD1[%in_tied_task158] GPR32:%vreg168 GPR64common:%vreg167
10592B		%vreg175<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg175
10596B		%vreg166<def> = LDRWui %vreg165, 332; mem:LD4[%task_running_count] GPR32:%vreg166 GPR64common:%vreg165
10600B		%vreg172<def> = LDRWui %vreg165<kill>, 0; mem:LD4[%nthreads162] GPR32:%vreg172 GPR64common:%vreg165
10608B		%vreg169<def> = ORNWrr %WZR, %vreg168<kill>; GPR32:%vreg169,%vreg168
10616B		%vreg170<def> = ANDWri %vreg169<kill>, 0; GPR32common:%vreg170 GPR32:%vreg169
10624B		%vreg171<def> = ADDWrr %vreg166<kill>, %vreg170<kill>; GPR32:%vreg171,%vreg166 GPR32common:%vreg170
10632B		%vreg173<def,dead> = SUBSWrr %vreg171<kill>, %vreg172<kill>, %NZCV<imp-def>; GPR32:%vreg173,%vreg171,%vreg172
10640B		%vreg174<def> = CSINCWr %WZR, %WZR, 2, %NZCV<imp-use>; GPR32:%vreg174
10648B		STRBBui %vreg174<kill>, <fi#18>, 0; mem:ST1[%do_wake] GPR32:%vreg174
10656B		%vreg176<def> = ADDXri %vreg175<kill>, 1280, 0; GPR64sp:%vreg176 GPR64common:%vreg175
10664B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
10672B		%X0<def> = COPY %vreg176<kill>; GPR64sp:%vreg176
10680B		BL <ga:@gomp_mutex_unlock>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...
10688B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
10696B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
10704B		STACKMAP 29, 0, 0, <fi#18>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack18](align=1) LD8[FixedStack10]
10720B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
10736B		%vreg177<def> = LDRBBui <fi#18>, 0; mem:LD1[%do_wake] GPR32:%vreg177
10752B		TBZW %vreg177<kill>, 0, <BB#51>; GPR32:%vreg177
10768B		B <BB#50>
	    Successors according to CFG: BB#50 BB#51
> %X2<def> = LDRXui <fi#14>, 0; mem:LD8[%task77]
> %X8<def> = LDRXui <fi#10>, 0; mem:LD8[%team]
> %W3<def> = LDRWui <fi#8>, 0; mem:LD4[%priority.addr]
> %W9<def> = LDRBBui %X2, 207; mem:LD1[%parent_depends_on152]
> %X1<def> = ADDXri %X8<kill>, 1288, 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = COPY %WZR
> %W5<def> = COPY %WZR
> %W6<def> = ANDWri %W9<kill>, 0
> %W4<def> = MOVi32imm 1
> %X1<def> = COPY %X1<kill>
Deleting identity copy.
> %X2<def> = COPY %X2<kill>
Deleting identity copy.
> %W3<def> = COPY %W3<kill>
Deleting identity copy.
> %W6<def> = COPY %W6<kill>
Deleting identity copy.
> BL <ga:@priority_queue_insert>, <regmask>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use>, %X2<imp-use>, %W3<imp-use>, %W4<imp-use>, %W5<imp-use>, %W6<imp-use>, %SP<imp-def>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 27, 0, 0, <fi#18>, 0, 0, <fi#15>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack18](align=1) LD8[FixedStack15] LD8[FixedStack10]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X8<def> = LDRXui <fi#10>, 0; mem:LD8[%team]
> %W9<def> = LDRWui %X8, 330; mem:LD4[%task_count154]
> %W9<def> = ADDWri %W9<kill>, 1, 0
> STRWui %W9<kill>, %X8<kill>, 330; mem:ST4[%task_count154]
> %X8<def> = LDRXui <fi#10>, 0; mem:LD8[%team]
> %W9<def> = LDRWui %X8, 331; mem:LD4[%task_queued_count]
> %W9<def> = ADDWri %W9<kill>, 1, 0
> STRWui %W9<kill>, %X8<kill>, 331; mem:ST4[%task_queued_count]
> %X8<def> = LDRXui <fi#10>, 0; mem:LD8[%team]
> %X0<def> = ADDXri %X8<kill>, 128, 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BL <ga:@gomp_team_barrier_set_task_pending>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 28, 0, 0, <fi#18>, 0, 0, <fi#15>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack18](align=1) LD8[FixedStack15] LD8[FixedStack10]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X8<def> = LDRXui <fi#15>, 0; mem:LD8[%parent]
> %X9<def> = LDRXui <fi#10>, 0; mem:LD8[%team]
> %W8<def> = LDRBBui %X8<kill>, 204; mem:LD1[%in_tied_task158]
> %X10<def> = LDRXui <fi#10>, 0; mem:LD8[%team]
> %W11<def> = LDRWui %X9, 332; mem:LD4[%task_running_count]
> %W9<def> = LDRWui %X9<kill>, 0; mem:LD4[%nthreads162]
> %W8<def> = ORNWrr %WZR, %W8<kill>
> %W8<def> = ANDWri %W8<kill>, 0
> %W8<def> = ADDWrr %W11<kill>, %W8<kill>
> %W8<def,dead> = SUBSWrr %W8<kill>, %W9<kill>, %NZCV<imp-def>
> %W8<def> = CSINCWr %WZR, %WZR, 2, %NZCV<imp-use>
> STRBBui %W8<kill>, <fi#18>, 0; mem:ST1[%do_wake]
> %X0<def> = ADDXri %X10<kill>, 1280, 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BL <ga:@gomp_mutex_unlock>, <regmask>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 29, 0, 0, <fi#18>, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack18](align=1) LD8[FixedStack10]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W8<def> = LDRBBui <fi#18>, 0; mem:LD1[%do_wake]
> TBZW %W8<kill>, 0, <BB#51>
> B <BB#50>
10784B	BB#50: derived from LLVM BB %if.then.168
	    Predecessors according to CFG: BB#49
10800B		%vreg178<def> = LDRXui <fi#10>, 0; mem:LD8[%team] GPR64common:%vreg178
10816B		%vreg179<def> = ADDXri %vreg178<kill>, 128, 0; GPR64sp:%vreg179 GPR64common:%vreg178
10832B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
10880B		%W1<def> = MOVi32imm 1
10888B		%X0<def> = COPY %vreg179<kill>; GPR64sp:%vreg179
10896B		BL <ga:@gomp_team_barrier_wake>, <regmask>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %SP<imp-def>, ...
10912B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
10928B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
10944B		STACKMAP 30, 0, ...
10960B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
10976B		B <BB#51>
	    Successors according to CFG: BB#51
> %X8<def> = LDRXui <fi#10>, 0; mem:LD8[%team]
> %X0<def> = ADDXri %X8<kill>, 128, 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %W1<def> = MOVi32imm 1
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BL <ga:@gomp_team_barrier_wake>, <regmask>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %SP<imp-def>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 30, 0, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> B <BB#51>
10992B	BB#51: derived from LLVM BB %if.end.170
	    Predecessors according to CFG: BB#49 BB#50
11008B		B <BB#52>
	    Successors according to CFG: BB#52
> B <BB#52>
11024B	BB#52: derived from LLVM BB %if.end.171
	    Predecessors according to CFG: BB#51 BB#45 BB#40 BB#29 BB#4
11040B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
11072B		%X0<def> = COPY %XZR
11088B		%X1<def> = COPY %XZR
11104B		BL <ga:@check_migrate>, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %SP<imp-def>, ...
11120B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
11136B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
11152B		STACKMAP 31, 0, ...
11168B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
11184B		RET_ReallyLR
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %XZR
> %X1<def> = COPY %XZR
> BL <ga:@check_migrate>, <regmask>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %SP<imp-def>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 31, 0, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> RET_ReallyLR
clang-3.7: /usr/local/popcorn/src/llvm/lib/CodeGen/UnwindInfo.cpp:49: void llvm::UnwindInfo::recordUnwindInfo(const llvm::MachineFunction&): Assertion `FrameReg == TRI->getFrameRegister(MF) && "Invalid register used as offset for unwinding information"' failed.
0  libLLVMSupport.so.3.7        0x00007efeb5873950 llvm::sys::PrintStackTrace(llvm::raw_ostream&) + 44
1  libLLVMSupport.so.3.7        0x00007efeb5873cc7
2  libLLVMSupport.so.3.7        0x00007efeb58728c2
3  libc.so.6                    0x00007efeb288a030
4  libc.so.6                    0x00007efeb2889fcf gsignal + 207
5  libc.so.6                    0x00007efeb288b3fa abort + 362
6  libc.so.6                    0x00007efeb2882e37
7  libc.so.6                    0x00007efeb2882ee2
8  libLLVMCodeGen.so.3.7        0x00007efeb88df038 llvm::UnwindInfo::recordUnwindInfo(llvm::MachineFunction const&) + 562
9  libLLVMAArch64CodeGen.so.3.7 0x00007efebb7e0486
10 libLLVMCodeGen.so.3.7        0x00007efeb8721b43 llvm::MachineFunctionPass::runOnFunction(llvm::Function&) + 95
11 libLLVMCore.so.3.7           0x00007efeb7de4f2d llvm::FPPassManager::runOnFunction(llvm::Function&) + 315
12 libLLVMCore.so.3.7           0x00007efeb7de508c llvm::FPPassManager::runOnModule(llvm::Module&) + 118
13 libLLVMCore.so.3.7           0x00007efeb7de53bb
14 libLLVMCore.so.3.7           0x00007efeb7de5a1e llvm::legacy::PassManagerImpl::run(llvm::Module&) + 264
15 libLLVMCore.so.3.7           0x00007efeb7de5c0f llvm::legacy::PassManager::run(llvm::Module&) + 39
16 libclangCodeGen.so.3.7       0x00007efeb4135a0d
17 libclangCodeGen.so.3.7       0x00007efeb4135eff clang::CodegenBackendOutput(clang::DiagnosticsEngine&, clang::CodeGenOptions const&, clang::TargetOptions const&, clang::LangOptions const&, llvm::StringRef, llvm::Module*, clang::BackendAction, llvm::raw_pwrite_stream*) + 492
18 libclangCodeGen.so.3.7       0x00007efeb4353efe
19 libclangParse.so.3.7         0x00007efeae88ccec clang::ParseAST(clang::Sema&, bool, bool) + 789
20 libclangFrontend.so.3.7      0x00007efeb38f63bb clang::ASTFrontendAction::ExecuteAction() + 323
21 libclangCodeGen.so.3.7       0x00007efeb43518ed clang::EmitMultiObjAction::ExecuteAction() + 1065
22 libclangFrontend.so.3.7      0x00007efeb38f5e75 clang::FrontendAction::Execute() + 139
23 libclangFrontend.so.3.7      0x00007efeb38ab609 clang::CompilerInstance::ExecuteAction(clang::FrontendAction&) + 785
24 libclangFrontendTool.so.3.7  0x00007efeb349c27e clang::ExecuteCompilerInvocation(clang::CompilerInstance*) + 1120
25 clang-3.7                    0x000055ef86ae1937 cc1_main(llvm::ArrayRef<char const*>, char const*, void*) + 980
26 clang-3.7                    0x000055ef86ad8d6a
27 clang-3.7                    0x000055ef86ad9253 main + 1041
28 libc.so.6                    0x00007efeb28772b1 __libc_start_main + 241
29 clang-3.7                    0x000055ef86ad75ca _start + 42
Stack dump:
0.	Program arguments: /usr/local/popcorn/bin/clang-3.7 -cc1 -triple x86_64--linux-gnu -emit-obj -mrelax-all -disable-free -main-file-name task.c -mrelocation-model static -mthread-model posix -mdisable-fp-elim -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -target-cpu x86-64 -dwarf-column-info -coverage-file /home/anthony/Research/popcorn-compiler/lib/libopenpop/task.o -nostdsysteminc -nobuiltininc -resource-dir /usr/local/popcorn/bin/../lib/clang/3.7.1 -dependency-file .deps/task.Tpo -sys-header-deps -MP -MT task.lo -isystem /usr/local/popcorn/x86_64/include -isystem /usr/local/popcorn/x86_64/include -D HAVE_CONFIG_H -I . -I ./config/linux -I ./config/posix -I . -isysroot /usr/local/popcorn/x86_64 -Wall -Werror -Wno-error -fdebug-compilation-dir /home/anthony/Research/popcorn-compiler/lib/libopenpop -ferror-limit 19 -fmessage-length 0 -ftls-model=initial-exec -pthread -mstackrealign -fobjc-runtime=gcc -fno-common -fdiagnostics-show-option -mllvm -debug-only=regalloc -mllvm -debug-only=stacktransform -ffunction-sections -fdata-sections -popcorn-alignment -popcorn-migratable -mllvm -popcorn-instrument=migration -mllvm -optimize-regalloc -mllvm -fast-isel=false -o task.o -x c task.c 
1.	<eof> parser at end of file
2.	Code generation
3.	Running pass 'Function Pass Manager' on module 'task.c'.
4.	Running pass 'AArch64 Assembly Printer' on function '@GOMP_task'
clang-3.7: error: unable to execute command: Aborted
clang-3.7: error: clang frontend command failed due to signal (use -v to see invocation)
clang version 3.7.1 (tags/RELEASE_371/final 325143) (llvm/tags/RELEASE_371/final 325142)
Target: x86_64--linux-gnu
Thread model: posix
clang-3.7: note: diagnostic msg: PLEASE submit a bug report to http://llvm.org/bugs/ and include the crash backtrace, preprocessed source, and associated run script.
clang-3.7: note: diagnostic msg: 
********************

PLEASE ATTACH THE FOLLOWING FILES TO THE BUG REPORT:
Preprocessed source(s) and associated run script(s) are located at:
clang-3.7: note: diagnostic msg: /tmp/task-1bc50f.c
clang-3.7: note: diagnostic msg: /tmp/task-1bc50f.sh
clang-3.7: note: diagnostic msg: 

********************
Makefile:716: recipe for target 'task.lo' failed
make[1]: *** [task.lo] Error 1
make[1]: Leaving directory '/home/anthony/Research/popcorn-compiler/lib/libopenpop'
Makefile:530: recipe for target 'all' failed
make: *** [all] Error 2