Computing live-in reg-units in ABI blocks.
0B	BB#0 W0#0 W30#0
Created 2 new intervals.
********** INTERVALS **********
W30 [0B,16r:0)[176r,176d:8)[256e,256d:3)[352r,352d:9)[416e,416d:2)[544r,544d:10)[608e,608d:1)[816r,816d:6)[880e,880d:7)[976r,976d:4)[1024e,1024d:5)  0@0B-phi 1@608e 2@416e 3@256e 4@976r 5@1024e 6@816r 7@880e 8@176r 9@352r 10@544r
W0 [0B,32r:0)[144r,176r:5)[352r,384r:6)[480r,544r:7)[544r,576r:3)[784r,816r:4)[816r,848r:2)[960r,976r:1)  0@0B-phi 1@960r 2@816r 3@544r 4@784r 5@144r 6@352r 7@480r
%vreg0 [32r,48r:0)  0@32r
%vreg1 [48r,288r:0)  0@48r
%vreg3 [640r,656r:0)  0@640r
%vreg7 [464r,496r:0)  0@464r
%vreg8 [576r,576d:0)  0@576r
%vreg9 [384r,528r:0)  0@384r
%vreg10 [320r,512r:0)  0@320r
%vreg11 [208r,224r:0)  0@208r
%vreg12 [224r,304r:0)  0@224r
%vreg13 [304r,480r:0)  0@304r
%vreg14 [64r,80r:0)  0@64r
%vreg15 [80r,96r:0)  0@80r
%vreg16 [96r,144r:0)  0@96r
%vreg17 [112r,160r:0)  0@112r
%vreg18 [16r,112r:0)  0@16r
%vreg20 [768r,800r:0)  0@768r
%vreg21 [848r,848d:0)  0@848r
%vreg22 [704r,720r:0)  0@704r
%vreg23 [720r,736r:0)  0@720r
%vreg24 [736r,784r:0)  0@736r
%vreg25 [928r,960r:0)  0@928r
RegMasks: 176r 352r 544r 816r 976r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bz__AssertH__fail: Post SSA
Frame Objects:
  fi#0: size=4, align=4, at location [SP]
Function Live Ins: %W0 in %vreg0, %LR in %vreg18

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %W0 %LR
16B		%vreg18<def> = COPY %LR; GPR64:%vreg18
32B		%vreg0<def> = COPY %W0; GPR32:%vreg0
48B		%vreg1<def> = COPY %vreg0; GPR32:%vreg1,%vreg0
64B		%vreg14<def> = ADRP <ga:@BZ2_bz__AssertH__fail>[TF=1]; GPR64common:%vreg14
80B		%vreg15<def> = ADDXri %vreg14, <ga:@BZ2_bz__AssertH__fail>[TF=34], 0; GPR64sp:%vreg15 GPR64common:%vreg14
96B		%vreg16<def> = COPY %vreg15; GPR64all:%vreg16 GPR64sp:%vreg15
112B		%vreg17<def> = COPY %vreg18; GPR64all:%vreg17 GPR64:%vreg18
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		%X0<def> = COPY %vreg16; GPR64all:%vreg16
160B		%X1<def> = COPY %vreg17; GPR64all:%vreg17
176B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		%vreg11<def> = ADRP <ga:@stderr>[TF=1]; GPR64common:%vreg11
224B		%vreg12<def> = ADDXri %vreg11, <ga:@stderr>[TF=34], 0; GPR64sp:%vreg12 GPR64common:%vreg11
240B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
256B		STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) GPR32:%vreg1
272B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
288B		STRWui %vreg1, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg1
304B		%vreg13<def> = LDRXui %vreg12, 0; mem:LD8[@stderr] GPR64:%vreg13 GPR64sp:%vreg12
320B		%vreg10<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0] GPR32:%vreg10
336B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
352B		BL <ga:@BZ2_bzlibVersion>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-def>
368B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
384B		%vreg9<def> = COPY %X0; GPR64all:%vreg9
400B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
416B		STACKMAP 1, 0, 0, <fi#0>, 0, %vreg10, %vreg13, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) GPR32:%vreg10 GPR64:%vreg13
432B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
448B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
464B		%vreg7<def> = MOVaddr <ga:@bzlib__str___bzip2_li>[TF=1], <ga:@bzlib__str___bzip2_li>[TF=34]; GPR64:%vreg7
480B		%X0<def> = COPY %vreg13; GPR64:%vreg13
496B		%X1<def> = COPY %vreg7; GPR64:%vreg7
512B		%W2<def> = COPY %vreg10; GPR32:%vreg10
528B		%X3<def> = COPY %vreg9; GPR64all:%vreg9
544B		BL <ga:@fprintf>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %W2<imp-use,kill>, %X3<imp-use,kill>, %SP<imp-def>, %W0<imp-def>
560B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
576B		%vreg8<def,dead> = COPY %W0; GPR32all:%vreg8
592B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
608B		STACKMAP 2, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
624B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
640B		%vreg3<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0] GPR32common:%vreg3
656B		%WZR<def> = SUBSWri %vreg3, 1007, 0, %NZCV<imp-def>; GPR32common:%vreg3
672B		Bcc 1, <BB#2>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

688B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
704B		%vreg22<def> = ADRP <ga:@stderr>[TF=1]; GPR64common:%vreg22
720B		%vreg23<def> = ADDXri %vreg22, <ga:@stderr>[TF=34], 0; GPR64sp:%vreg23 GPR64common:%vreg22
736B		%vreg24<def> = LDRXui %vreg23, 0; mem:LD8[@stderr] GPR64:%vreg24 GPR64sp:%vreg23
752B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
768B		%vreg20<def> = MOVaddr <ga:@bzlib__str_1______A_spe>[TF=1], <ga:@bzlib__str_1______A_spe>[TF=34]; GPR64:%vreg20
784B		%X0<def> = COPY %vreg24; GPR64:%vreg24
800B		%X1<def> = COPY %vreg20; GPR64:%vreg20
816B		BL <ga:@fprintf>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %SP<imp-def>, %W0<imp-def>
832B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
848B		%vreg21<def,dead> = COPY %W0; GPR32all:%vreg21
864B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
880B		STACKMAP 3, 0, %LR<earlyclobber,imp-def,dead>, ...
896B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#2

912B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#1
928B		%vreg25<def> = MOVi32imm 3; GPR32:%vreg25
944B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
960B		%W0<def> = COPY %vreg25; GPR32:%vreg25
976B		BL <ga:@exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-use>
992B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1008B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1024B		STACKMAP 4, 0, %LR<earlyclobber,imp-def,dead>, ...
1040B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>

# End machine code for function BZ2_bz__AssertH__fail.

********** SIMPLE REGISTER COALESCING **********
********** Function: BZ2_bz__AssertH__fail
********** JOINING INTERVALS ***********
entry:
16B	%vreg18<def> = COPY %LR; GPR64:%vreg18
	Considering merging %vreg18 with %LR
	Can only merge into reserved registers.
32B	%vreg0<def> = COPY %W0; GPR32:%vreg0
	Considering merging %vreg0 with %W0
	Can only merge into reserved registers.
144B	%X0<def> = COPY %vreg16; GPR64all:%vreg16
	Considering merging %vreg16 with %X0
	Can only merge into reserved registers.
160B	%X1<def> = COPY %vreg17; GPR64all:%vreg17
	Considering merging %vreg17 with %X1
	Can only merge into reserved registers.
384B	%vreg9<def> = COPY %X0; GPR64all:%vreg9
	Considering merging %vreg9 with %X0
	Can only merge into reserved registers.
480B	%X0<def> = COPY %vreg13; GPR64:%vreg13
	Considering merging %vreg13 with %X0
	Can only merge into reserved registers.
496B	%X1<def> = COPY %vreg7; GPR64:%vreg7
	Considering merging %vreg7 with %X1
	Can only merge into reserved registers.
512B	%W2<def> = COPY %vreg10; GPR32:%vreg10
	Considering merging %vreg10 with %W2
	Can only merge into reserved registers.
528B	%X3<def> = COPY %vreg9; GPR64all:%vreg9
	Considering merging %vreg9 with %X3
	Can only merge into reserved registers.
576B	%vreg8<def,dead> = COPY %W0; GPR32all:%vreg8
	Considering merging %vreg8 with %W0
	Can only merge into reserved registers.
if.then:
784B	%X0<def> = COPY %vreg24; GPR64:%vreg24
	Considering merging %vreg24 with %X0
	Can only merge into reserved registers.
800B	%X1<def> = COPY %vreg20; GPR64:%vreg20
	Considering merging %vreg20 with %X1
	Can only merge into reserved registers.
848B	%vreg21<def,dead> = COPY %W0; GPR32all:%vreg21
	Considering merging %vreg21 with %W0
	Can only merge into reserved registers.
if.end:
960B	%W0<def> = COPY %vreg25; GPR32:%vreg25
	Considering merging %vreg25 with %W0
	Can only merge into reserved registers.
Remat: %W0<def> = MOVi32imm 3
Shrink: %vreg25 [928r,960r:0)  0@928r
All defs dead: 928r	%vreg25<def,dead> = MOVi32imm 3; GPR32:%vreg25
Shrunk: %vreg25 [928r,928d:0)  0@928r
Deleting dead def 928r	%vreg25<def,dead> = MOVi32imm 3; GPR32:%vreg25
48B	%vreg1<def> = COPY %vreg0; GPR32:%vreg1,%vreg0
	Considering merging to GPR32 with %vreg0 in %vreg1
		RHS = %vreg0 [32r,48r:0)  0@32r
		LHS = %vreg1 [48r,288r:0)  0@48r
		merge %vreg1:0@48r into %vreg0:0@32r --> @32r
		erased:	48r	%vreg1<def> = COPY %vreg0; GPR32:%vreg1,%vreg0
AllocationOrder(GPR32) = [ %W8 %W9 %W10 %W11 %W12 %W13 %W14 %W15 %W16 %W17 %W18 %W0 %W1 %W2 %W3 %W4 %W5 %W6 %W7 %W19 %W20 %W21 %W22 %W23 %W24 %W25 %W26 %W27 %W28 %W30 ]
		updated: 32B	%vreg1<def> = COPY %W0; GPR32:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [32r,288r:0)  0@32r
96B	%vreg16<def> = COPY %vreg15; GPR64all:%vreg16 GPR64sp:%vreg15
	Considering merging to GPR64sp with %vreg15 in %vreg16
		RHS = %vreg15 [80r,96r:0)  0@80r
		LHS = %vreg16 [96r,144r:0)  0@96r
		merge %vreg16:0@96r into %vreg15:0@80r --> @80r
		erased:	96r	%vreg16<def> = COPY %vreg15; GPR64all:%vreg16 GPR64sp:%vreg15
AllocationOrder(GPR64sp) = [ %X8 %X9 %X10 %X11 %X12 %X13 %X14 %X15 %X16 %X17 %X18 %X0 %X1 %X2 %X3 %X4 %X5 %X6 %X7 %X19 %X20 %X21 %X22 %X23 %X24 %X25 %X26 %X27 %X28 %LR ]
		updated: 80B	%vreg16<def> = ADDXri %vreg14, <ga:@BZ2_bz__AssertH__fail>[TF=34], 0; GPR64sp:%vreg16 GPR64common:%vreg14
	Success: %vreg15 -> %vreg16
	Result = %vreg16 [80r,144r:0)  0@80r
112B	%vreg17<def> = COPY %vreg18; GPR64all:%vreg17 GPR64:%vreg18
	Considering merging to GPR64 with %vreg18 in %vreg17
		RHS = %vreg18 [16r,112r:0)  0@16r
		LHS = %vreg17 [112r,160r:0)  0@112r
		merge %vreg17:0@112r into %vreg18:0@16r --> @16r
		erased:	112r	%vreg17<def> = COPY %vreg18; GPR64all:%vreg17 GPR64:%vreg18
AllocationOrder(GPR64) = [ %X8 %X9 %X10 %X11 %X12 %X13 %X14 %X15 %X16 %X17 %X18 %X0 %X1 %X2 %X3 %X4 %X5 %X6 %X7 %X19 %X20 %X21 %X22 %X23 %X24 %X25 %X26 %X27 %X28 %LR ]
		updated: 16B	%vreg17<def> = COPY %LR; GPR64:%vreg17
	Success: %vreg18 -> %vreg17
	Result = %vreg17 [16r,160r:0)  0@16r
144B	%X0<def> = COPY %vreg16; GPR64sp:%vreg16
	Considering merging %vreg16 with %X0
	Can only merge into reserved registers.
160B	%X1<def> = COPY %vreg17; GPR64:%vreg17
	Considering merging %vreg17 with %X1
	Can only merge into reserved registers.
528B	%X3<def> = COPY %vreg9; GPR64all:%vreg9
	Considering merging %vreg9 with %X3
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
W30 [0B,16r:0)[176r,176d:8)[256e,256d:3)[352r,352d:9)[416e,416d:2)[544r,544d:10)[608e,608d:1)[816r,816d:6)[880e,880d:7)[976r,976d:4)[1024e,1024d:5)  0@0B-phi 1@608e 2@416e 3@256e 4@976r 5@1024e 6@816r 7@880e 8@176r 9@352r 10@544r
W0 [0B,32r:0)[144r,176r:5)[352r,384r:6)[480r,544r:7)[544r,576r:3)[784r,816r:4)[816r,848r:2)[960r,976r:1)  0@0B-phi 1@960r 2@816r 3@544r 4@784r 5@144r 6@352r 7@480r
%vreg1 [32r,288r:0)  0@32r
%vreg3 [640r,656r:0)  0@640r
%vreg7 [464r,496r:0)  0@464r
%vreg8 [576r,576d:0)  0@576r
%vreg9 [384r,528r:0)  0@384r
%vreg10 [320r,512r:0)  0@320r
%vreg11 [208r,224r:0)  0@208r
%vreg12 [224r,304r:0)  0@224r
%vreg13 [304r,480r:0)  0@304r
%vreg14 [64r,80r:0)  0@64r
%vreg16 [80r,144r:0)  0@80r
%vreg17 [16r,160r:0)  0@16r
%vreg20 [768r,800r:0)  0@768r
%vreg21 [848r,848d:0)  0@848r
%vreg22 [704r,720r:0)  0@704r
%vreg23 [720r,736r:0)  0@720r
%vreg24 [736r,784r:0)  0@736r
RegMasks: 176r 352r 544r 816r 976r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bz__AssertH__fail: Post SSA
Frame Objects:
  fi#0: size=4, align=4, at location [SP]
Function Live Ins: %W0 in %vreg0, %LR in %vreg18

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %W0 %LR
16B		%vreg17<def> = COPY %LR; GPR64:%vreg17
32B		%vreg1<def> = COPY %W0; GPR32:%vreg1
64B		%vreg14<def> = ADRP <ga:@BZ2_bz__AssertH__fail>[TF=1]; GPR64common:%vreg14
80B		%vreg16<def> = ADDXri %vreg14, <ga:@BZ2_bz__AssertH__fail>[TF=34], 0; GPR64sp:%vreg16 GPR64common:%vreg14
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		%X0<def> = COPY %vreg16; GPR64sp:%vreg16
160B		%X1<def> = COPY %vreg17; GPR64:%vreg17
176B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		%vreg11<def> = ADRP <ga:@stderr>[TF=1]; GPR64common:%vreg11
224B		%vreg12<def> = ADDXri %vreg11, <ga:@stderr>[TF=34], 0; GPR64sp:%vreg12 GPR64common:%vreg11
240B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
256B		STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) GPR32:%vreg1
272B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
288B		STRWui %vreg1, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg1
304B		%vreg13<def> = LDRXui %vreg12, 0; mem:LD8[@stderr] GPR64:%vreg13 GPR64sp:%vreg12
320B		%vreg10<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0] GPR32:%vreg10
336B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
352B		BL <ga:@BZ2_bzlibVersion>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-def>
368B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
384B		%vreg9<def> = COPY %X0; GPR64all:%vreg9
400B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
416B		STACKMAP 1, 0, 0, <fi#0>, 0, %vreg10, %vreg13, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) GPR32:%vreg10 GPR64:%vreg13
432B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
448B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
464B		%vreg7<def> = MOVaddr <ga:@bzlib__str___bzip2_li>[TF=1], <ga:@bzlib__str___bzip2_li>[TF=34]; GPR64:%vreg7
480B		%X0<def> = COPY %vreg13; GPR64:%vreg13
496B		%X1<def> = COPY %vreg7; GPR64:%vreg7
512B		%W2<def> = COPY %vreg10; GPR32:%vreg10
528B		%X3<def> = COPY %vreg9; GPR64all:%vreg9
544B		BL <ga:@fprintf>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %W2<imp-use,kill>, %X3<imp-use,kill>, %SP<imp-def>, %W0<imp-def>
560B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
576B		%vreg8<def,dead> = COPY %W0; GPR32all:%vreg8
592B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
608B		STACKMAP 2, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
624B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
640B		%vreg3<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0] GPR32common:%vreg3
656B		%WZR<def> = SUBSWri %vreg3, 1007, 0, %NZCV<imp-def>; GPR32common:%vreg3
672B		Bcc 1, <BB#2>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

688B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
704B		%vreg22<def> = ADRP <ga:@stderr>[TF=1]; GPR64common:%vreg22
720B		%vreg23<def> = ADDXri %vreg22, <ga:@stderr>[TF=34], 0; GPR64sp:%vreg23 GPR64common:%vreg22
736B		%vreg24<def> = LDRXui %vreg23, 0; mem:LD8[@stderr] GPR64:%vreg24 GPR64sp:%vreg23
752B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
768B		%vreg20<def> = MOVaddr <ga:@bzlib__str_1______A_spe>[TF=1], <ga:@bzlib__str_1______A_spe>[TF=34]; GPR64:%vreg20
784B		%X0<def> = COPY %vreg24; GPR64:%vreg24
800B		%X1<def> = COPY %vreg20; GPR64:%vreg20
816B		BL <ga:@fprintf>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %SP<imp-def>, %W0<imp-def>
832B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
848B		%vreg21<def,dead> = COPY %W0; GPR32all:%vreg21
864B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
880B		STACKMAP 3, 0, %LR<earlyclobber,imp-def,dead>, ...
896B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#2

912B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#1
944B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
960B		%W0<def> = MOVi32imm 3
976B		BL <ga:@exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-use>
992B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1008B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1024B		STACKMAP 4, 0, %LR<earlyclobber,imp-def,dead>, ...
1040B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>

# End machine code for function BZ2_bz__AssertH__fail.

AllocationOrder(GPR32all) = [ %W0 %W1 %W2 %W3 %W4 %W5 %W6 %W7 %W8 %W9 %W10 %W11 %W12 %W13 %W14 %W15 %W16 %W17 %W18 %W19 %W20 %W21 %W22 %W23 %W24 %W25 %W26 %W27 %W28 %W30 ]
********** GREEDY REGISTER ALLOCATION **********
********** Function: BZ2_bz__AssertH__fail
********** INTERVALS **********
W30 [0B,16r:0)[176r,176d:8)[256e,256d:3)[352r,352d:9)[416e,416d:2)[544r,544d:10)[608e,608d:1)[816r,816d:6)[880e,880d:7)[976r,976d:4)[1024e,1024d:5)  0@0B-phi 1@608e 2@416e 3@256e 4@976r 5@1024e 6@816r 7@880e 8@176r 9@352r 10@544r
W0 [0B,32r:0)[144r,176r:5)[352r,384r:6)[480r,544r:7)[544r,576r:3)[784r,816r:4)[816r,848r:2)[960r,976r:1)  0@0B-phi 1@960r 2@816r 3@544r 4@784r 5@144r 6@352r 7@480r
%vreg1 [32r,288r:0)  0@32r
%vreg3 [640r,656r:0)  0@640r
%vreg7 [464r,496r:0)  0@464r
%vreg8 [576r,576d:0)  0@576r
%vreg9 [384r,528r:0)  0@384r
%vreg10 [320r,512r:0)  0@320r
%vreg11 [208r,224r:0)  0@208r
%vreg12 [224r,304r:0)  0@224r
%vreg13 [304r,480r:0)  0@304r
%vreg14 [64r,80r:0)  0@64r
%vreg16 [80r,144r:0)  0@80r
%vreg17 [16r,160r:0)  0@16r
%vreg20 [768r,800r:0)  0@768r
%vreg21 [848r,848d:0)  0@848r
%vreg22 [704r,720r:0)  0@704r
%vreg23 [720r,736r:0)  0@720r
%vreg24 [736r,784r:0)  0@736r
RegMasks: 176r 352r 544r 816r 976r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bz__AssertH__fail: Post SSA
Frame Objects:
  fi#0: size=4, align=4, at location [SP]
Function Live Ins: %W0 in %vreg0, %LR in %vreg18

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %W0 %LR
16B		%vreg17<def> = COPY %LR; GPR64:%vreg17
32B		%vreg1<def> = COPY %W0; GPR32:%vreg1
64B		%vreg14<def> = ADRP <ga:@BZ2_bz__AssertH__fail>[TF=1]; GPR64common:%vreg14
80B		%vreg16<def> = ADDXri %vreg14, <ga:@BZ2_bz__AssertH__fail>[TF=34], 0; GPR64sp:%vreg16 GPR64common:%vreg14
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		%X0<def> = COPY %vreg16; GPR64sp:%vreg16
160B		%X1<def> = COPY %vreg17; GPR64:%vreg17
176B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		%vreg11<def> = ADRP <ga:@stderr>[TF=1]; GPR64common:%vreg11
224B		%vreg12<def> = ADDXri %vreg11, <ga:@stderr>[TF=34], 0; GPR64sp:%vreg12 GPR64common:%vreg11
240B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
256B		STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) GPR32:%vreg1
272B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
288B		STRWui %vreg1, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg1
304B		%vreg13<def> = LDRXui %vreg12, 0; mem:LD8[@stderr] GPR64:%vreg13 GPR64sp:%vreg12
320B		%vreg10<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0] GPR32:%vreg10
336B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
352B		BL <ga:@BZ2_bzlibVersion>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-def>
368B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
384B		%vreg9<def> = COPY %X0; GPR64all:%vreg9
400B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
416B		STACKMAP 1, 0, 0, <fi#0>, 0, %vreg10, %vreg13, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) GPR32:%vreg10 GPR64:%vreg13
432B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
448B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
464B		%vreg7<def> = MOVaddr <ga:@bzlib__str___bzip2_li>[TF=1], <ga:@bzlib__str___bzip2_li>[TF=34]; GPR64:%vreg7
480B		%X0<def> = COPY %vreg13; GPR64:%vreg13
496B		%X1<def> = COPY %vreg7; GPR64:%vreg7
512B		%W2<def> = COPY %vreg10; GPR32:%vreg10
528B		%X3<def> = COPY %vreg9; GPR64all:%vreg9
544B		BL <ga:@fprintf>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %W2<imp-use,kill>, %X3<imp-use,kill>, %SP<imp-def>, %W0<imp-def>
560B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
576B		%vreg8<def,dead> = COPY %W0; GPR32all:%vreg8
592B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
608B		STACKMAP 2, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
624B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
640B		%vreg3<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0] GPR32common:%vreg3
656B		%WZR<def> = SUBSWri %vreg3, 1007, 0, %NZCV<imp-def>; GPR32common:%vreg3
672B		Bcc 1, <BB#2>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

688B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
704B		%vreg22<def> = ADRP <ga:@stderr>[TF=1]; GPR64common:%vreg22
720B		%vreg23<def> = ADDXri %vreg22, <ga:@stderr>[TF=34], 0; GPR64sp:%vreg23 GPR64common:%vreg22
736B		%vreg24<def> = LDRXui %vreg23, 0; mem:LD8[@stderr] GPR64:%vreg24 GPR64sp:%vreg23
752B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
768B		%vreg20<def> = MOVaddr <ga:@bzlib__str_1______A_spe>[TF=1], <ga:@bzlib__str_1______A_spe>[TF=34]; GPR64:%vreg20
784B		%X0<def> = COPY %vreg24; GPR64:%vreg24
800B		%X1<def> = COPY %vreg20; GPR64:%vreg20
816B		BL <ga:@fprintf>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %SP<imp-def>, %W0<imp-def>
832B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
848B		%vreg21<def,dead> = COPY %W0; GPR32all:%vreg21
864B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
880B		STACKMAP 3, 0, %LR<earlyclobber,imp-def,dead>, ...
896B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#2

912B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#1
944B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
960B		%W0<def> = MOVi32imm 3
976B		BL <ga:@exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-use>
992B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1008B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1024B		STACKMAP 4, 0, %LR<earlyclobber,imp-def,dead>, ...
1040B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>

# End machine code for function BZ2_bz__AssertH__fail.


selectOrSplit GPR64:%vreg17 [16r,160r:0)  0@16r w=3.713235e-03
AllocationOrder(GPR64) = [ %X8 %X9 %X10 %X11 %X12 %X13 %X14 %X15 %X16 %X17 %X18 %X0 %X1 %X2 %X3 %X4 %X5 %X6 %X7 %X19 %X20 %X21 %X22 %X23 %X24 %X25 %X26 %X27 %X28 %LR ]
hints: %LR
assigning %vreg17 to %LR: W30 [16r,160r:0)  0@16r

selectOrSplit GPR32:%vreg1 [32r,288r:0)  0@32r w=4.618902e-03
AllocationOrder(GPR32) = [ %W8 %W9 %W10 %W11 %W12 %W13 %W14 %W15 %W16 %W17 %W18 %W0 %W1 %W2 %W3 %W4 %W5 %W6 %W7 %W19 %W20 %W21 %W22 %W23 %W24 %W25 %W26 %W27 %W28 %W30 ]
hints: %W0
missed hint %W0
assigning %vreg1 to %W19: W19 [32r,288r:0)  0@32r

selectOrSplit GPR64sp:%vreg16 [80r,144r:0)  0@80r w=4.353448e-03
AllocationOrder(GPR64sp) = [ %X8 %X9 %X10 %X11 %X12 %X13 %X14 %X15 %X16 %X17 %X18 %X0 %X1 %X2 %X3 %X4 %X5 %X6 %X7 %X19 %X20 %X21 %X22 %X23 %X24 %X25 %X26 %X27 %X28 %LR ]
hints: %X0
assigning %vreg16 to %X0: W0 [80r,144r:0)  0@80r

selectOrSplit GPR64:%vreg13 [304r,480r:0)  0@304r w=5.260417e-03
hints: %X0
missed hint %X0
assigning %vreg13 to %X19: W19 [304r,480r:0)  0@304r

selectOrSplit GPR32:%vreg10 [320r,512r:0)  0@320r w=5.118243e-03
hints: %W2
missed hint %W2
assigning %vreg10 to %W20: W20 [320r,512r:0)  0@320r

selectOrSplit GPR64all:%vreg9 [384r,528r:0)  0@384r w=3.713235e-03
AllocationOrder(GPR64all) = [ %X0 %X1 %X2 %X3 %X4 %X5 %X6 %X7 %X8 %X9 %X10 %X11 %X12 %X13 %X14 %X15 %X16 %X17 %X18 %X19 %X20 %X21 %X22 %X23 %X24 %X25 %X26 %X27 %X28 %LR ]
hints: %X0
missed hint %X0
assigning %vreg9 to %X3: W3 [384r,528r:0)  0@384r

selectOrSplit GPR64:%vreg7 [464r,496r:0)  0@464r w=2.337963e-03
hints: %X1
assigning %vreg7 to %X1: W1 [464r,496r:0)  0@464r

selectOrSplit GPR32all:%vreg8 [576r,576d:0)  0@576r w=inf
AllocationOrder(GPR32all) = [ %W0 %W1 %W2 %W3 %W4 %W5 %W6 %W7 %W8 %W9 %W10 %W11 %W12 %W13 %W14 %W15 %W16 %W17 %W18 %W19 %W20 %W21 %W22 %W23 %W24 %W25 %W26 %W27 %W28 %W30 ]
hints: %W0
assigning %vreg8 to %W0: W0 [576r,576d:0)  0@576r

selectOrSplit GPR64:%vreg24 [736r,784r:0)  0@736r w=2.254464e-03
hints: %X0
assigning %vreg24 to %X0: W0 [736r,784r:0)  0@736r

selectOrSplit GPR64:%vreg20 [768r,800r:0)  0@768r w=1.168981e-03
hints: %X1
assigning %vreg20 to %X1: W1 [768r,800r:0)  0@768r

selectOrSplit GPR32all:%vreg21 [848r,848d:0)  0@848r w=inf
hints: %W0
assigning %vreg21 to %W0: W0 [848r,848d:0)  0@848r

selectOrSplit GPR64common:%vreg14 [64r,80r:0)  0@64r w=inf
AllocationOrder(GPR64common) = [ %X8 %X9 %X10 %X11 %X12 %X13 %X14 %X15 %X16 %X17 %X18 %X0 %X1 %X2 %X3 %X4 %X5 %X6 %X7 %X19 %X20 %X21 %X22 %X23 %X24 %X25 %X26 %X27 %X28 %LR ]
assigning %vreg14 to %X8: W8 [64r,80r:0)  0@64r

selectOrSplit GPR64common:%vreg11 [208r,224r:0)  0@208r w=inf
assigning %vreg11 to %X8: W8 [208r,224r:0)  0@208r

selectOrSplit GPR64sp:%vreg12 [224r,304r:0)  0@224r w=4.166667e-03
assigning %vreg12 to %X8: W8 [224r,304r:0)  0@224r

selectOrSplit GPR32common:%vreg3 [640r,656r:0)  0@640r w=inf
AllocationOrder(GPR32common) = [ %W8 %W9 %W10 %W11 %W12 %W13 %W14 %W15 %W16 %W17 %W18 %W0 %W1 %W2 %W3 %W4 %W5 %W6 %W7 %W19 %W20 %W21 %W22 %W23 %W24 %W25 %W26 %W27 %W28 %W30 ]
assigning %vreg3 to %W8: W8 [640r,656r:0)  0@640r

selectOrSplit GPR64common:%vreg22 [704r,720r:0)  0@704r w=inf
assigning %vreg22 to %X8: W8 [704r,720r:0)  0@704r

selectOrSplit GPR64sp:%vreg23 [720r,736r:0)  0@720r w=inf
assigning %vreg23 to %X8: W8 [720r,736r:0)  0@720r

********** STACK TRANSFORMATION METADATA **********
********** Function: BZ2_bz__AssertH__fail
********** REGISTER MAP **********
[%vreg1 -> %W19] GPR32
[%vreg3 -> %W8] GPR32common
[%vreg7 -> %X1] GPR64
[%vreg8 -> %W0] GPR32all
[%vreg9 -> %X3] GPR64all
[%vreg10 -> %W20] GPR32
[%vreg11 -> %X8] GPR64common
[%vreg12 -> %X8] GPR64sp
[%vreg13 -> %X19] GPR64
[%vreg14 -> %X8] GPR64common
[%vreg16 -> %X0] GPR64sp
[%vreg17 -> %LR] GPR64
[%vreg20 -> %X1] GPR64
[%vreg21 -> %W0] GPR32all
[%vreg22 -> %X8] GPR64common
[%vreg23 -> %X8] GPR64sp
[%vreg24 -> %X0] GPR64


Stackmap 0:
  STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) GPR32:%vreg1

i32 %errcode: in register %W19 (vreg 1)
i32* %errcode.addr: in stack slot 0 (size: 4)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, 0, <fi#0>, 0, %vreg10, %vreg13, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) GPR32:%vreg10 GPR64:%vreg13

i32* %errcode.addr: in stack slot 0 (size: 4)
i32 %1: in register %W20 (vreg 10)
%struct._IO_FILE* %0: in register %X19 (vreg 13)

Duplicate operand locations:


Stackmap 2:
  STACKMAP 2, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)

i32* %errcode.addr: in stack slot 0 (size: 4)

Duplicate operand locations:


Stackmap 3:
  STACKMAP 3, 0, %LR<earlyclobber,imp-def,dead>, ...


Duplicate operand locations:


Stackmap 4:
  STACKMAP 4, 0, %LR<earlyclobber,imp-def,dead>, ...


Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) GPR32:%vreg1
  -> Call instruction SlotIndex 176B, searching vregs 0 -> 26 and stack slots 0 -> 1

  STACKMAP 1, 0, 0, <fi#0>, 0, %vreg10, %vreg13, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) GPR32:%vreg10 GPR64:%vreg13
  -> Call instruction SlotIndex 352B, searching vregs 0 -> 26 and stack slots 0 -> 1

  STACKMAP 2, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
  -> Call instruction SlotIndex 544B, searching vregs 0 -> 26 and stack slots 0 -> 1

  STACKMAP 3, 0, %LR<earlyclobber,imp-def,dead>, ...
  -> Call instruction SlotIndex 816B, searching vregs 0 -> 26 and stack slots 0 -> 1

  STACKMAP 4, 0, %LR<earlyclobber,imp-def,dead>, ...
  -> Call instruction SlotIndex 976B, searching vregs 0 -> 26 and stack slots 0 -> 1

********** REWRITE VIRTUAL REGISTERS **********
********** Function: BZ2_bz__AssertH__fail
********** REGISTER MAP **********
[%vreg1 -> %W19] GPR32
[%vreg3 -> %W8] GPR32common
[%vreg7 -> %X1] GPR64
[%vreg8 -> %W0] GPR32all
[%vreg9 -> %X3] GPR64all
[%vreg10 -> %W20] GPR32
[%vreg11 -> %X8] GPR64common
[%vreg12 -> %X8] GPR64sp
[%vreg13 -> %X19] GPR64
[%vreg14 -> %X8] GPR64common
[%vreg16 -> %X0] GPR64sp
[%vreg17 -> %LR] GPR64
[%vreg20 -> %X1] GPR64
[%vreg21 -> %W0] GPR32all
[%vreg22 -> %X8] GPR64common
[%vreg23 -> %X8] GPR64sp
[%vreg24 -> %X0] GPR64

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %LR %W0
16B		%vreg17<def> = COPY %LR; GPR64:%vreg17
32B		%vreg1<def> = COPY %W0; GPR32:%vreg1
64B		%vreg14<def> = ADRP <ga:@BZ2_bz__AssertH__fail>[TF=1]; GPR64common:%vreg14
80B		%vreg16<def> = ADDXri %vreg14<kill>, <ga:@BZ2_bz__AssertH__fail>[TF=34], 0; GPR64sp:%vreg16 GPR64common:%vreg14
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		%X0<def> = COPY %vreg16<kill>; GPR64sp:%vreg16
160B		%X1<def> = COPY %vreg17<kill>; GPR64:%vreg17
176B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		%vreg11<def> = ADRP <ga:@stderr>[TF=1]; GPR64common:%vreg11
224B		%vreg12<def> = ADDXri %vreg11<kill>, <ga:@stderr>[TF=34], 0; GPR64sp:%vreg12 GPR64common:%vreg11
240B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
256B		STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) GPR32:%vreg1
272B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
288B		STRWui %vreg1<kill>, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg1
304B		%vreg13<def> = LDRXui %vreg12<kill>, 0; mem:LD8[@stderr] GPR64:%vreg13 GPR64sp:%vreg12
320B		%vreg10<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0] GPR32:%vreg10
336B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
352B		BL <ga:@BZ2_bzlibVersion>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-def>
368B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
384B		%vreg9<def> = COPY %X0; GPR64all:%vreg9
400B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
416B		STACKMAP 1, 0, 0, <fi#0>, 0, %vreg10, %vreg13, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) GPR32:%vreg10 GPR64:%vreg13
432B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
448B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
464B		%vreg7<def> = MOVaddr <ga:@bzlib__str___bzip2_li>[TF=1], <ga:@bzlib__str___bzip2_li>[TF=34]; GPR64:%vreg7
480B		%X0<def> = COPY %vreg13<kill>; GPR64:%vreg13
496B		%X1<def> = COPY %vreg7<kill>; GPR64:%vreg7
512B		%W2<def> = COPY %vreg10<kill>; GPR32:%vreg10
528B		%X3<def> = COPY %vreg9<kill>; GPR64all:%vreg9
544B		BL <ga:@fprintf>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %W2<imp-use>, %X3<imp-use>, %SP<imp-def>, %W0<imp-def>
560B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
576B		%vreg8<def,dead> = COPY %W0; GPR32all:%vreg8
592B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
608B		STACKMAP 2, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
624B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
640B		%vreg3<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0] GPR32common:%vreg3
656B		%WZR<def> = SUBSWri %vreg3<kill>, 1007, 0, %NZCV<imp-def>; GPR32common:%vreg3
672B		Bcc 1, <BB#2>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1
> %LR<def> = COPY %LR
Deleting identity copy.
> %W19<def> = COPY %W0
> %X8<def> = ADRP <ga:@BZ2_bz__AssertH__fail>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@BZ2_bz__AssertH__fail>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %LR<kill>
> BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X8<def> = ADRP <ga:@stderr>[TF=1]
> %X8<def> = ADDXri %X8<kill>, <ga:@stderr>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 0, 0, %W19, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRWui %W19<kill>, <fi#0>, 0; mem:ST4[FixedStack0]
> %X19<def> = LDRXui %X8<kill>, 0; mem:LD8[@stderr]
> %W20<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> BL <ga:@BZ2_bzlibVersion>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X3<def> = COPY %X0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 1, 0, 0, <fi#0>, 0, %W20, %X19, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X1<def> = MOVaddr <ga:@bzlib__str___bzip2_li>[TF=1], <ga:@bzlib__str___bzip2_li>[TF=34]
> %X0<def> = COPY %X19<kill>
> %X1<def> = COPY %X1<kill>
Deleting identity copy.
> %W2<def> = COPY %W20<kill>
> %X3<def> = COPY %X3<kill>
Deleting identity copy.
> BL <ga:@fprintf>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %W2<imp-use>, %X3<imp-use>, %SP<imp-def>, %W0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def,dead> = COPY %W0
Deleting identity copy.
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 2, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W8<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0]
> %WZR<def> = SUBSWri %W8<kill>, 1007, 0, %NZCV<imp-def>
> Bcc 1, <BB#2>, %NZCV<imp-use,kill>
688B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
704B		%vreg22<def> = ADRP <ga:@stderr>[TF=1]; GPR64common:%vreg22
720B		%vreg23<def> = ADDXri %vreg22<kill>, <ga:@stderr>[TF=34], 0; GPR64sp:%vreg23 GPR64common:%vreg22
736B		%vreg24<def> = LDRXui %vreg23<kill>, 0; mem:LD8[@stderr] GPR64:%vreg24 GPR64sp:%vreg23
752B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
768B		%vreg20<def> = MOVaddr <ga:@bzlib__str_1______A_spe>[TF=1], <ga:@bzlib__str_1______A_spe>[TF=34]; GPR64:%vreg20
784B		%X0<def> = COPY %vreg24<kill>; GPR64:%vreg24
800B		%X1<def> = COPY %vreg20<kill>; GPR64:%vreg20
816B		BL <ga:@fprintf>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %SP<imp-def>, %W0<imp-def>
832B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
848B		%vreg21<def,dead> = COPY %W0; GPR32all:%vreg21
864B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
880B		STACKMAP 3, 0, %LR<earlyclobber,imp-def,dead>, ...
896B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#2
> %X8<def> = ADRP <ga:@stderr>[TF=1]
> %X8<def> = ADDXri %X8<kill>, <ga:@stderr>[TF=34], 0
> %X0<def> = LDRXui %X8<kill>, 0; mem:LD8[@stderr]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X1<def> = MOVaddr <ga:@bzlib__str_1______A_spe>[TF=1], <ga:@bzlib__str_1______A_spe>[TF=34]
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X1<kill>
Deleting identity copy.
> BL <ga:@fprintf>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %SP<imp-def>, %W0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def,dead> = COPY %W0
Deleting identity copy.
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 3, 0, %LR<earlyclobber,imp-def,dead>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
912B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#1
944B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
960B		%W0<def> = MOVi32imm 3
976B		BL <ga:@exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-use>
992B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1008B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1024B		STACKMAP 4, 0, %LR<earlyclobber,imp-def,dead>, ...
1040B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = MOVi32imm 3
> BL <ga:@exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 4, 0, %LR<earlyclobber,imp-def,dead>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
Computing live-in reg-units in ABI blocks.
0B	BB#0 W30#0
Created 1 new intervals.
********** INTERVALS **********
W30 [0B,16r:0)[144r,144d:1)[240e,240d:2)[336r,336d:3)[416e,416d:4)  0@0B-phi 1@144r 2@240e 3@336r 4@416e
%vreg0 [368r,384r:0)  0@368r
%vreg1 [384r,448r:0)  0@384r
%vreg2 [176r,192r:0)  0@176r
%vreg3 [192r,208r:0)  0@192r
%vreg4 [208r,304r:0)  0@208r
%vreg5 [272r,320r:0)  0@272r
%vreg6 [16r,272r:0)  0@16r
%vreg7 [32r,48r:0)  0@32r
%vreg8 [48r,64r:0)  0@48r
%vreg9 [64r,112r:0)  0@64r
%vreg10 [80r,128r:0)  0@80r
RegMasks: 144r 336r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzlibVersion: Post SSA
Function Live Ins: %LR in %vreg6

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %LR
16B		%vreg6<def> = COPY %LR; GPR64:%vreg6
32B		%vreg7<def> = ADRP <ga:@BZ2_bzlibVersion>[TF=1]; GPR64common:%vreg7
48B		%vreg8<def> = ADDXri %vreg7, <ga:@BZ2_bzlibVersion>[TF=34], 0; GPR64sp:%vreg8 GPR64common:%vreg7
64B		%vreg9<def> = COPY %vreg8; GPR64all:%vreg9 GPR64sp:%vreg8
80B		%vreg10<def> = COPY %vreg6; GPR64all:%vreg10 GPR64:%vreg6
96B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
112B		%X0<def> = COPY %vreg9; GPR64all:%vreg9
128B		%X1<def> = COPY %vreg10; GPR64all:%vreg10
144B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use,kill>, %X1<imp-use,kill>
160B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
176B		%vreg2<def> = ADRP <ga:@BZ2_bzlibVersion>[TF=1]; GPR64common:%vreg2
192B		%vreg3<def> = ADDXri %vreg2, <ga:@BZ2_bzlibVersion>[TF=34], 0; GPR64sp:%vreg3 GPR64common:%vreg2
208B		%vreg4<def> = COPY %vreg3; GPR64all:%vreg4 GPR64sp:%vreg3
224B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
240B		STACKMAP 0, 0, %LR<earlyclobber,imp-def,dead>, ...
256B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
272B		%vreg5<def> = COPY %vreg6; GPR64all:%vreg5 GPR64:%vreg6
288B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
304B		%X0<def> = COPY %vreg4; GPR64all:%vreg4
320B		%X1<def> = COPY %vreg5; GPR64all:%vreg5
336B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use,kill>, %X1<imp-use,kill>
352B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
368B		%vreg0<def> = ADRP <ga:@bzlib__str_5_1_0_3__15_>[TF=1]; GPR64common:%vreg0
384B		%vreg1<def> = ADDXri %vreg0, <ga:@bzlib__str_5_1_0_3__15_>[TF=34], 0; GPR64sp:%vreg1 GPR64common:%vreg0
400B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
416B		STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...
432B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
448B		%X0<def> = COPY %vreg1; GPR64sp:%vreg1
464B		RET_ReallyLR %X0<imp-use,kill>

# End machine code for function BZ2_bzlibVersion.

********** SIMPLE REGISTER COALESCING **********
********** Function: BZ2_bzlibVersion
********** JOINING INTERVALS ***********
entry:
16B	%vreg6<def> = COPY %LR; GPR64:%vreg6
	Considering merging %vreg6 with %LR
	Can only merge into reserved registers.
112B	%X0<def> = COPY %vreg9; GPR64all:%vreg9
	Considering merging %vreg9 with %X0
	Can only merge into reserved registers.
128B	%X1<def> = COPY %vreg10; GPR64all:%vreg10
	Considering merging %vreg10 with %X1
	Can only merge into reserved registers.
304B	%X0<def> = COPY %vreg4; GPR64all:%vreg4
	Considering merging %vreg4 with %X0
	Can only merge into reserved registers.
320B	%X1<def> = COPY %vreg5; GPR64all:%vreg5
	Considering merging %vreg5 with %X1
	Can only merge into reserved registers.
448B	%X0<def> = COPY %vreg1; GPR64sp:%vreg1
	Considering merging %vreg1 with %X0
	Can only merge into reserved registers.
64B	%vreg9<def> = COPY %vreg8; GPR64all:%vreg9 GPR64sp:%vreg8
	Considering merging to GPR64sp with %vreg8 in %vreg9
		RHS = %vreg8 [48r,64r:0)  0@48r
		LHS = %vreg9 [64r,112r:0)  0@64r
		merge %vreg9:0@64r into %vreg8:0@48r --> @48r
		erased:	64r	%vreg9<def> = COPY %vreg8; GPR64all:%vreg9 GPR64sp:%vreg8
		updated: 48B	%vreg9<def> = ADDXri %vreg7, <ga:@BZ2_bzlibVersion>[TF=34], 0; GPR64sp:%vreg9 GPR64common:%vreg7
	Success: %vreg8 -> %vreg9
	Result = %vreg9 [48r,112r:0)  0@48r
80B	%vreg10<def> = COPY %vreg6; GPR64all:%vreg10 GPR64:%vreg6
	Considering merging to GPR64 with %vreg6 in %vreg10
		RHS = %vreg6 [16r,272r:0)  0@16r
		LHS = %vreg10 [80r,128r:0)  0@80r
		merge %vreg10:0@80r into %vreg6:0@16r --> @16r
		erased:	80r	%vreg10<def> = COPY %vreg6; GPR64all:%vreg10 GPR64:%vreg6
		updated: 16B	%vreg10<def> = COPY %LR; GPR64:%vreg10
		updated: 272B	%vreg5<def> = COPY %vreg10; GPR64all:%vreg5 GPR64:%vreg10
	Success: %vreg6 -> %vreg10
	Result = %vreg10 [16r,272r:0)  0@16r
208B	%vreg4<def> = COPY %vreg3; GPR64all:%vreg4 GPR64sp:%vreg3
	Considering merging to GPR64sp with %vreg3 in %vreg4
		RHS = %vreg3 [192r,208r:0)  0@192r
		LHS = %vreg4 [208r,304r:0)  0@208r
		merge %vreg4:0@208r into %vreg3:0@192r --> @192r
		erased:	208r	%vreg4<def> = COPY %vreg3; GPR64all:%vreg4 GPR64sp:%vreg3
		updated: 192B	%vreg4<def> = ADDXri %vreg2, <ga:@BZ2_bzlibVersion>[TF=34], 0; GPR64sp:%vreg4 GPR64common:%vreg2
	Success: %vreg3 -> %vreg4
	Result = %vreg4 [192r,304r:0)  0@192r
272B	%vreg5<def> = COPY %vreg10; GPR64all:%vreg5 GPR64:%vreg10
	Considering merging to GPR64 with %vreg10 in %vreg5
		RHS = %vreg10 [16r,272r:0)  0@16r
		LHS = %vreg5 [272r,320r:0)  0@272r
		merge %vreg5:0@272r into %vreg10:0@16r --> @16r
		erased:	272r	%vreg5<def> = COPY %vreg10; GPR64all:%vreg5 GPR64:%vreg10
		updated: 16B	%vreg5<def> = COPY %LR; GPR64:%vreg5
		updated: 128B	%X1<def> = COPY %vreg5; GPR64:%vreg5
	Success: %vreg10 -> %vreg5
	Result = %vreg5 [16r,320r:0)  0@16r
112B	%X0<def> = COPY %vreg9; GPR64sp:%vreg9
	Considering merging %vreg9 with %X0
	Can only merge into reserved registers.
128B	%X1<def> = COPY %vreg5; GPR64:%vreg5
	Considering merging %vreg5 with %X1
	Can only merge into reserved registers.
304B	%X0<def> = COPY %vreg4; GPR64sp:%vreg4
	Considering merging %vreg4 with %X0
	Can only merge into reserved registers.
320B	%X1<def> = COPY %vreg5; GPR64:%vreg5
	Considering merging %vreg5 with %X1
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
W30 [0B,16r:0)[144r,144d:1)[240e,240d:2)[336r,336d:3)[416e,416d:4)  0@0B-phi 1@144r 2@240e 3@336r 4@416e
%vreg0 [368r,384r:0)  0@368r
%vreg1 [384r,448r:0)  0@384r
%vreg2 [176r,192r:0)  0@176r
%vreg4 [192r,304r:0)  0@192r
%vreg5 [16r,320r:0)  0@16r
%vreg7 [32r,48r:0)  0@32r
%vreg9 [48r,112r:0)  0@48r
RegMasks: 144r 336r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzlibVersion: Post SSA
Function Live Ins: %LR in %vreg6

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %LR
16B		%vreg5<def> = COPY %LR; GPR64:%vreg5
32B		%vreg7<def> = ADRP <ga:@BZ2_bzlibVersion>[TF=1]; GPR64common:%vreg7
48B		%vreg9<def> = ADDXri %vreg7, <ga:@BZ2_bzlibVersion>[TF=34], 0; GPR64sp:%vreg9 GPR64common:%vreg7
96B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
112B		%X0<def> = COPY %vreg9; GPR64sp:%vreg9
128B		%X1<def> = COPY %vreg5; GPR64:%vreg5
144B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use,kill>, %X1<imp-use,kill>
160B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
176B		%vreg2<def> = ADRP <ga:@BZ2_bzlibVersion>[TF=1]; GPR64common:%vreg2
192B		%vreg4<def> = ADDXri %vreg2, <ga:@BZ2_bzlibVersion>[TF=34], 0; GPR64sp:%vreg4 GPR64common:%vreg2
224B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
240B		STACKMAP 0, 0, %LR<earlyclobber,imp-def,dead>, ...
256B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
288B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
304B		%X0<def> = COPY %vreg4; GPR64sp:%vreg4
320B		%X1<def> = COPY %vreg5; GPR64:%vreg5
336B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use,kill>, %X1<imp-use,kill>
352B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
368B		%vreg0<def> = ADRP <ga:@bzlib__str_5_1_0_3__15_>[TF=1]; GPR64common:%vreg0
384B		%vreg1<def> = ADDXri %vreg0, <ga:@bzlib__str_5_1_0_3__15_>[TF=34], 0; GPR64sp:%vreg1 GPR64common:%vreg0
400B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
416B		STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...
432B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
448B		%X0<def> = COPY %vreg1; GPR64sp:%vreg1
464B		RET_ReallyLR %X0<imp-use,kill>

# End machine code for function BZ2_bzlibVersion.

********** GREEDY REGISTER ALLOCATION **********
********** Function: BZ2_bzlibVersion
********** INTERVALS **********
W30 [0B,16r:0)[144r,144d:1)[240e,240d:2)[336r,336d:3)[416e,416d:4)  0@0B-phi 1@144r 2@240e 3@336r 4@416e
%vreg0 [368r,384r:0)  0@368r
%vreg1 [384r,448r:0)  0@384r
%vreg2 [176r,192r:0)  0@176r
%vreg4 [192r,304r:0)  0@192r
%vreg5 [16r,320r:0)  0@16r
%vreg7 [32r,48r:0)  0@32r
%vreg9 [48r,112r:0)  0@48r
RegMasks: 144r 336r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzlibVersion: Post SSA
Function Live Ins: %LR in %vreg6

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %LR
16B		%vreg5<def> = COPY %LR; GPR64:%vreg5
32B		%vreg7<def> = ADRP <ga:@BZ2_bzlibVersion>[TF=1]; GPR64common:%vreg7
48B		%vreg9<def> = ADDXri %vreg7, <ga:@BZ2_bzlibVersion>[TF=34], 0; GPR64sp:%vreg9 GPR64common:%vreg7
96B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
112B		%X0<def> = COPY %vreg9; GPR64sp:%vreg9
128B		%X1<def> = COPY %vreg5; GPR64:%vreg5
144B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use,kill>, %X1<imp-use,kill>
160B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
176B		%vreg2<def> = ADRP <ga:@BZ2_bzlibVersion>[TF=1]; GPR64common:%vreg2
192B		%vreg4<def> = ADDXri %vreg2, <ga:@BZ2_bzlibVersion>[TF=34], 0; GPR64sp:%vreg4 GPR64common:%vreg2
224B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
240B		STACKMAP 0, 0, %LR<earlyclobber,imp-def,dead>, ...
256B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
288B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
304B		%X0<def> = COPY %vreg4; GPR64sp:%vreg4
320B		%X1<def> = COPY %vreg5; GPR64:%vreg5
336B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use,kill>, %X1<imp-use,kill>
352B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
368B		%vreg0<def> = ADRP <ga:@bzlib__str_5_1_0_3__15_>[TF=1]; GPR64common:%vreg0
384B		%vreg1<def> = ADDXri %vreg0, <ga:@bzlib__str_5_1_0_3__15_>[TF=34], 0; GPR64sp:%vreg1 GPR64common:%vreg0
400B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
416B		STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...
432B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
448B		%X0<def> = COPY %vreg1; GPR64sp:%vreg1
464B		RET_ReallyLR %X0<imp-use,kill>

# End machine code for function BZ2_bzlibVersion.


selectOrSplit GPR64:%vreg5 [16r,320r:0)  0@16r w=4.303977e-03
hints: %X1
missed hint %X1
assigning %vreg5 to %X19: W19 [16r,320r:0)  0@16r

selectOrSplit GPR64sp:%vreg9 [48r,112r:0)  0@48r w=4.353448e-03
hints: %X0
assigning %vreg9 to %X0: W0 [48r,112r:0)  0@48r

selectOrSplit GPR64sp:%vreg4 [192r,304r:0)  0@192r w=3.945312e-03
hints: %X0
assigning %vreg4 to %X0: W0 [192r,304r:0)  0@192r

selectOrSplit GPR64sp:%vreg1 [384r,448r:0)  0@384r w=4.353448e-03
hints: %X0
assigning %vreg1 to %X0: W0 [384r,448r:0)  0@384r

selectOrSplit GPR64common:%vreg7 [32r,48r:0)  0@32r w=inf
assigning %vreg7 to %X8: W8 [32r,48r:0)  0@32r

selectOrSplit GPR64common:%vreg2 [176r,192r:0)  0@176r w=inf
assigning %vreg2 to %X8: W8 [176r,192r:0)  0@176r

selectOrSplit GPR64common:%vreg0 [368r,384r:0)  0@368r w=inf
assigning %vreg0 to %X8: W8 [368r,384r:0)  0@368r

********** STACK TRANSFORMATION METADATA **********
********** Function: BZ2_bzlibVersion
********** REGISTER MAP **********
[%vreg0 -> %X8] GPR64common
[%vreg1 -> %X0] GPR64sp
[%vreg2 -> %X8] GPR64common
[%vreg4 -> %X0] GPR64sp
[%vreg5 -> %X19] GPR64
[%vreg7 -> %X8] GPR64common
[%vreg9 -> %X0] GPR64sp


Stackmap 0:
  STACKMAP 0, 0, %LR<earlyclobber,imp-def,dead>, ...


Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...


Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, %LR<earlyclobber,imp-def,dead>, ...
  -> Call instruction SlotIndex 144B, searching vregs 0 -> 11 and stack slots 0 -> 0
    + vreg5 is live in register but not in stackmap
      Defining instruction: %vreg5<def> = COPY %LR; GPR64:%vreg5
      Value: generated value, 1 instruction(s)

  STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...
  -> Call instruction SlotIndex 336B, searching vregs 0 -> 11 and stack slots 0 -> 0

********** REWRITE VIRTUAL REGISTERS **********
********** Function: BZ2_bzlibVersion
********** REGISTER MAP **********
[%vreg0 -> %X8] GPR64common
[%vreg1 -> %X0] GPR64sp
[%vreg2 -> %X8] GPR64common
[%vreg4 -> %X0] GPR64sp
[%vreg5 -> %X19] GPR64
[%vreg7 -> %X8] GPR64common
[%vreg9 -> %X0] GPR64sp

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %LR
16B		%vreg5<def> = COPY %LR; GPR64:%vreg5
32B		%vreg7<def> = ADRP <ga:@BZ2_bzlibVersion>[TF=1]; GPR64common:%vreg7
48B		%vreg9<def> = ADDXri %vreg7<kill>, <ga:@BZ2_bzlibVersion>[TF=34], 0; GPR64sp:%vreg9 GPR64common:%vreg7
96B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
112B		%X0<def> = COPY %vreg9<kill>; GPR64sp:%vreg9
128B		%X1<def> = COPY %vreg5; GPR64:%vreg5
144B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
160B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
176B		%vreg2<def> = ADRP <ga:@BZ2_bzlibVersion>[TF=1]; GPR64common:%vreg2
192B		%vreg4<def> = ADDXri %vreg2<kill>, <ga:@BZ2_bzlibVersion>[TF=34], 0; GPR64sp:%vreg4 GPR64common:%vreg2
224B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
240B		STACKMAP 0, 0, %LR<earlyclobber,imp-def,dead>, ...
256B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
288B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
304B		%X0<def> = COPY %vreg4<kill>; GPR64sp:%vreg4
320B		%X1<def> = COPY %vreg5<kill>; GPR64:%vreg5
336B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
352B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
368B		%vreg0<def> = ADRP <ga:@bzlib__str_5_1_0_3__15_>[TF=1]; GPR64common:%vreg0
384B		%vreg1<def> = ADDXri %vreg0<kill>, <ga:@bzlib__str_5_1_0_3__15_>[TF=34], 0; GPR64sp:%vreg1 GPR64common:%vreg0
400B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
416B		STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...
432B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
448B		%X0<def> = COPY %vreg1<kill>; GPR64sp:%vreg1
464B		RET_ReallyLR %X0<imp-use>
> %X19<def> = COPY %LR
> %X8<def> = ADRP <ga:@BZ2_bzlibVersion>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@BZ2_bzlibVersion>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19
> BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X8<def> = ADRP <ga:@BZ2_bzlibVersion>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@BZ2_bzlibVersion>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 0, 0, %LR<earlyclobber,imp-def,dead>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19<kill>
> BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X8<def> = ADRP <ga:@bzlib__str_5_1_0_3__15_>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@bzlib__str_5_1_0_3__15_>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> RET_ReallyLR %X0<imp-use>
Computing live-in reg-units in ABI blocks.
0B	BB#0 W0#0 W1#0 W2#0 W3#0 W30#0
Created 5 new intervals.
********** INTERVALS **********
W30 [0B,16r:0)[272r,272d:25)[320e,320d:13)[432r,432d:26)[496e,496d:12)[1520r,1520d:24)[1584e,1584d:11)[2176r,2176d:21)[2256e,2256d:10)[2544r,2544d:22)[2640e,2640d:9)[2848r,2848d:23)[2912e,2912d:8)[3408r,3408d:18)[3456e,3456d:7)[3728r,3728d:17)[3776e,3776d:6)[4048r,4048d:16)[4096e,4096d:5)[4336r,4336d:15)[4384e,4384d:4)[5392r,5392d:19)[5440e,5440d:3)[5520r,5520d:20)[5568e,5568d:2)[5744r,5744d:14)[5792e,5792d:1)  0@0B-phi 1@5792e 2@5568e 3@5440e 4@4384e 5@4096e 6@3776e 7@3456e 8@2912e 9@2640e 10@2256e 11@1584e 12@496e 13@320e 14@5744r 15@4336r 16@4048r 17@3728r 18@3408r 19@5392r 20@5520r 21@2176r 22@2544r 23@2848r 24@1520r 25@272r 26@432r
W0 [0B,80r:0)[240r,272r:18)[432r,464r:2)[1472r,1520r:17)[1520r,1552r:16)[2128r,2176r:11)[2176r,2208r:10)[2496r,2544r:13)[2544r,2576r:12)[2800r,2848r:15)[2848r,2880r:14)[3376r,3408r:7)[3696r,3728r:6)[4016r,4048r:5)[4304r,4336r:4)[5376r,5392r:8)[5504r,5520r:9)[5712r,5744r:3)[5840r,5856r:1)  0@0B-phi 1@5840r 2@432r 3@5712r 4@4304r 5@4016r 6@3696r 7@3376r 8@5376r 9@5504r 10@2176r 11@2128r 12@2544r 13@2496r 14@2848r 15@2800r 16@1520r 17@1472r 18@240r
W1 [0B,64r:0)[256r,272r:10)[1488r,1520r:4)[2144r,2176r:1)[2512r,2544r:2)[2816r,2848r:3)[3392r,3408r:9)[3712r,3728r:8)[4032r,4048r:7)[4320r,4336r:6)[5728r,5744r:5)  0@0B-phi 1@2144r 2@2512r 3@2816r 4@1488r 5@5728r 6@4320r 7@4032r 8@3712r 9@3392r 10@256r
W2 [0B,48r:0)[1504r,1520r:4)[2160r,2176r:1)[2528r,2544r:2)[2832r,2848r:3)  0@0B-phi 1@2160r 2@2528r 3@2832r 4@1504r
W3 [0B,32r:0)  0@0B-phi
%vreg0 [80r,96r:0)  0@80r
%vreg1 [96r,352r:0)  0@96r
%vreg2 [64r,112r:0)  0@64r
%vreg3 [112r,368r:0)  0@112r
%vreg4 [48r,128r:0)  0@48r
%vreg5 [128r,384r:0)  0@128r
%vreg6 [32r,144r:0)  0@32r
%vreg7 [144r,400r:0)  0@144r
%vreg9 [464r,528r:0)  0@464r
%vreg10 [160r,176r:0)  0@160r
%vreg11 [176r,192r:0)  0@176r
%vreg12 [192r,240r:0)  0@192r
%vreg13 [208r,256r:0)  0@208r
%vreg14 [16r,5680r:0)  0@16r
%vreg15 [560r,576r:0)  0@560r
%vreg17 [624r,640r:0)  0@624r
%vreg19 [672r,688r:0)  0@672r
%vreg21 [736r,752r:0)  0@736r
%vreg23 [800r,816r:0)  0@800r
%vreg25 [848r,864r:0)  0@848r
%vreg27 [976r,992r:0)  0@976r
%vreg28 [1024r,1040r:0)  0@1024r
%vreg31 [1088r,1104r:0)  0@1088r
%vreg32 [1072r,1088r:0)  0@1072r
%vreg33 [1136r,1152r:0)  0@1136r
%vreg34 [1152r,1184r:0)  0@1152r
%vreg36 [1168r,1184r:0)  0@1168r
%vreg39 [1232r,1248r:0)  0@1232r
%vreg40 [1216r,1232r:0)  0@1216r
%vreg41 [1280r,1296r:0)  0@1280r
%vreg42 [1296r,1328r:0)  0@1296r
%vreg44 [1312r,1328r:0)  0@1312r
%vreg46 [1648r,1664r:0)  0@1648r
%vreg49 [1616r,1632r:0)  0@1616r
%vreg52 [1360r,1488r:0)  0@1360r
%vreg53 [1376r,1504r:0)  0@1376r
%vreg54 [1552r,1616r:0)  0@1552r
%vreg56 [1440r,1472r:0)  0@1440r
%vreg57 [1424r,1440r:0)  0@1424r
%vreg59 [1408r,1520r:0)  0@1408r
%vreg60 [1392r,1408r:0)  0@1392r
%vreg63 [3008r,3024r:0)  0@3008r
%vreg64 [2992r,3008r:0)  0@2992r
%vreg67 [2960r,2976r:0)  0@2960r
%vreg69 [2944r,2976r:0)  0@2944r
%vreg72 [2592r,2816r:0)  0@2592r
%vreg73 [2608r,2832r:0)  0@2608r
%vreg74 [2880r,2944r:0)  0@2880r
%vreg76 [2768r,2800r:0)  0@2768r
%vreg77 [2752r,2768r:0)  0@2752r
%vreg79 [2736r,2848r:0)  0@2736r
%vreg80 [2720r,2736r:0)  0@2720r
%vreg83 [2688r,2704r:0)  0@2688r
%vreg85 [2672r,2704r:0)  0@2672r
%vreg89 [2224r,2528r:0)  0@2224r
%vreg90 [2576r,2672r:0)  0@2576r
%vreg92 [2464r,2512r:0)  0@2464r
%vreg94 [2432r,2448r:0)  0@2432r
%vreg95 [2448r,2464r:0)  0@2448r
%vreg97 [2416r,2432r:0)  0@2416r
%vreg98 [2400r,2416r:0)  0@2400r
%vreg100 [2384r,2496r:0)  0@2384r
%vreg101 [2368r,2384r:0)  0@2368r
%vreg103 [2352r,2544r:0)  0@2352r
%vreg104 [2336r,2352r:0)  0@2336r
%vreg107 [2304r,2320r:0)  0@2304r
%vreg109 [2288r,2320r:0)  0@2288r
%vreg113 [1760r,2160r:0)  0@1760r
%vreg114 [2208r,2288r:0)  0@2208r
%vreg116 [2096r,2144r:0)  0@2096r
%vreg118 [2080r,2096r:0)  0@2080r
%vreg122 [2064r,2080r:0)  0@2064r
%vreg124 [2048r,2128r:0)  0@2048r
%vreg125 [2032r,2048r:0)  0@2032r
%vreg127 [2016r,2176r:0)  0@2016r
%vreg128 [2000r,2016r:0)  0@2000r
%vreg130 [1776r,1968r:0)  0@1776r
%vreg132 [1968r,1984r:0)  0@1968r
%vreg133 [1952r,1968r:0)  0@1952r
%vreg134 [1792r,1936r:0)  0@1792r
%vreg136 [1920r,1936r:0)  0@1920r
%vreg138 [1888r,1904r:0)  0@1888r
%vreg140 [1856r,1872r:0)  0@1856r
%vreg143 [1824r,1840r:0)  0@1824r
%vreg144 [1808r,1840r:0)  0@1808r
%vreg147 [3072r,3088r:0)  0@3072r
%vreg148 [3056r,3072r:0)  0@3056r
%vreg151 [3136r,3152r:0)  0@3136r
%vreg152 [3120r,3136r:0)  0@3120r
%vreg154 [5472r,5504r:0)  0@5472r
%vreg156 [5344r,5376r:0)  0@5344r
%vreg158 [5312r,5328r:0)  0@5312r
%vreg160 [5280r,5296r:0)  0@5280r
%vreg162 [5248r,5264r:0)  0@5248r
%vreg164 [5216r,5232r:0)  0@5216r
%vreg167 [5184r,5200r:0)  0@5184r
%vreg169 [5168r,5200r:0)  0@5168r
%vreg170 [5152r,5168r:0)  0@5152r
%vreg173 [5120r,5136r:0)  0@5120r
%vreg175 [5104r,5136r:0)  0@5104r
%vreg176 [5088r,5104r:0)  0@5088r
%vreg177 [4496r,5072r:0)  0@4496r
%vreg179 [5056r,5072r:0)  0@5056r
%vreg182 [5024r,5040r:0)  0@5024r
%vreg184 [5008r,5040r:0)  0@5008r
%vreg186 [4992r,5008r:0)  0@4992r
%vreg187 [4976r,4992r:0)  0@4976r
%vreg190 [4944r,4960r:0)  0@4944r
%vreg192 [4928r,4960r:0)  0@4928r
%vreg194 [4912r,4928r:0)  0@4912r
%vreg195 [4896r,4912r:0)  0@4896r
%vreg198 [4864r,4880r:0)  0@4864r
%vreg199 [4848r,4880r:0)  0@4848r
%vreg202 [4816r,4832r:0)  0@4816r
%vreg203 [4800r,4832r:0)  0@4800r
%vreg206 [4768r,4784r:0)  0@4768r
%vreg208 [4752r,4784r:0)  0@4752r
%vreg209 [4512r,4736r:0)  0@4512r
%vreg211 [4736r,4752r:0)  0@4736r
%vreg212 [4720r,4736r:0)  0@4720r
%vreg215 [4688r,4704r:0)  0@4688r
%vreg216 [4672r,4704r:0)  0@4672r
%vreg218 [4640r,4656r:0)  0@4640r
%vreg219 [4528r,4624r:0)  0@4528r
%vreg221 [4608r,4624r:0)  0@4608r
%vreg223 [4576r,4592r:0)  0@4576r
%vreg225 [4544r,4560r:0)  0@4544r
%vreg228 [3200r,3216r:0)  0@3200r
%vreg229 [3184r,3200r:0)  0@3184r
%vreg234 [3344r,3392r:0)  0@3344r
%vreg236 [3328r,3344r:0)  0@3328r
%vreg237 [3312r,3328r:0)  0@3312r
%vreg239 [3296r,3376r:0)  0@3296r
%vreg240 [3280r,3296r:0)  0@3280r
%vreg242 [3264r,3408r:0)  0@3264r
%vreg243 [3248r,3264r:0)  0@3248r
%vreg246 [3520r,3536r:0)  0@3520r
%vreg247 [3504r,3520r:0)  0@3504r
%vreg252 [3664r,3712r:0)  0@3664r
%vreg254 [3648r,3664r:0)  0@3648r
%vreg255 [3632r,3648r:0)  0@3632r
%vreg257 [3616r,3696r:0)  0@3616r
%vreg258 [3600r,3616r:0)  0@3600r
%vreg260 [3584r,3728r:0)  0@3584r
%vreg261 [3568r,3584r:0)  0@3568r
%vreg264 [3840r,3856r:0)  0@3840r
%vreg265 [3824r,3840r:0)  0@3824r
%vreg270 [3984r,4032r:0)  0@3984r
%vreg272 [3968r,3984r:0)  0@3968r
%vreg273 [3952r,3968r:0)  0@3952r
%vreg275 [3936r,4016r:0)  0@3936r
%vreg276 [3920r,3936r:0)  0@3920r
%vreg278 [3904r,4048r:0)  0@3904r
%vreg279 [3888r,3904r:0)  0@3888r
%vreg281 [4144r,4160r:0)  0@4144r
%vreg286 [4272r,4320r:0)  0@4272r
%vreg287 [4256r,4272r:0)  0@4256r
%vreg289 [4240r,4304r:0)  0@4240r
%vreg290 [4224r,4240r:0)  0@4224r
%vreg292 [4208r,4336r:0)  0@4208r
%vreg293 [4192r,4208r:0)  0@4192r
%vreg294 [4432r,4448r:0)  0@4432r
%vreg295 [1696r,1712r:0)  0@1696r
%vreg296 [912r,928r:0)  0@912r
%vreg298 [5824r,5840r:0)  0@5824r
%vreg299 [5632r,5648r:0)  0@5632r
%vreg300 [5648r,5664r:0)  0@5648r
%vreg301 [5664r,5712r:0)  0@5664r
%vreg302 [5680r,5728r:0)  0@5680r
RegMasks: 272r 432r 1520r 2176r 2544r 2848r 3408r 3728r 4048r 4336r 5392r 5520r 5744r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzCompressInit: Post SSA
Frame Objects:
  fi#0: size=4, align=4, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=4, align=4, at location [SP]
  fi#3: size=4, align=4, at location [SP]
  fi#4: size=4, align=4, at location [SP]
  fi#5: size=4, align=4, at location [SP]
  fi#6: size=8, align=8, at location [SP]
Function Live Ins: %X0 in %vreg0, %W1 in %vreg2, %W2 in %vreg4, %W3 in %vreg6, %LR in %vreg14

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %W1 %W2 %W3 %LR
16B		%vreg14<def> = COPY %LR; GPR64:%vreg14
32B		%vreg6<def> = COPY %W3; GPR32:%vreg6
48B		%vreg4<def> = COPY %W2; GPR32:%vreg4
64B		%vreg2<def> = COPY %W1; GPR32:%vreg2
80B		%vreg0<def> = COPY %X0; GPR64:%vreg0
96B		%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
112B		%vreg3<def> = COPY %vreg2; GPR32:%vreg3,%vreg2
128B		%vreg5<def> = COPY %vreg4; GPR32:%vreg5,%vreg4
144B		%vreg7<def> = COPY %vreg6; GPR32:%vreg7,%vreg6
160B		%vreg10<def> = ADRP <ga:@BZ2_bzCompressInit>[TF=1]; GPR64common:%vreg10
176B		%vreg11<def> = ADDXri %vreg10, <ga:@BZ2_bzCompressInit>[TF=34], 0; GPR64sp:%vreg11 GPR64common:%vreg10
192B		%vreg12<def> = COPY %vreg11; GPR64all:%vreg12 GPR64sp:%vreg11
208B		%vreg13<def> = COPY %vreg14; GPR64all:%vreg13 GPR64:%vreg14
224B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
240B		%X0<def> = COPY %vreg12; GPR64all:%vreg12
256B		%X1<def> = COPY %vreg13; GPR64all:%vreg13
272B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
288B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
304B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
320B		STACKMAP 0, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, %vreg1, 0, <fi#1>, 0, %vreg5, 0, <fi#3>, 0, %vreg7, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4) GPR32:%vreg3,%vreg5,%vreg7 GPR64:%vreg1
336B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
352B		STRXui %vreg1, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg1
368B		STRWui %vreg3, <fi#2>, 0; mem:ST4[FixedStack2] GPR32:%vreg3
384B		STRWui %vreg5, <fi#3>, 0; mem:ST4[FixedStack3] GPR32:%vreg5
400B		STRWui %vreg7, <fi#4>, 0; mem:ST4[FixedStack4] GPR32:%vreg7
416B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
432B		BL <ga:@bz_config_ok>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-def>
448B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
464B		%vreg9<def> = COPY %W0; GPR32:%vreg9
480B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
496B		STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)
512B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
528B		CBNZW %vreg9, <BB#2>; GPR32:%vreg9
	    Successors according to CFG: BB#2 BB#1

544B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
560B		%vreg15<def> = MOVi32imm 4294967287; GPR32:%vreg15
576B		STRWui %vreg15, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg15
592B		B <BB#29>
	    Successors according to CFG: BB#29

608B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0
624B		%vreg17<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg17
640B		CBZX %vreg17, <BB#7>; GPR64:%vreg17
	    Successors according to CFG: BB#7 BB#3

656B	BB#3: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#2
672B		%vreg19<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32common:%vreg19
688B		%WZR<def> = SUBSWri %vreg19, 1, 0, %NZCV<imp-def>; GPR32common:%vreg19
704B		Bcc 11, <BB#7>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#7 BB#4

720B	BB#4: derived from LLVM BB %lor.lhs.false.2
	    Predecessors according to CFG: BB#3
736B		%vreg21<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32common:%vreg21
752B		%WZR<def> = SUBSWri %vreg21, 9, 0, %NZCV<imp-def>; GPR32common:%vreg21
768B		Bcc 12, <BB#7>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#7 BB#5

784B	BB#5: derived from LLVM BB %lor.lhs.false.4
	    Predecessors according to CFG: BB#4
800B		%vreg23<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg23
816B		TBNZW %vreg23, 31, <BB#7>; GPR32:%vreg23
	    Successors according to CFG: BB#7 BB#6

832B	BB#6: derived from LLVM BB %lor.lhs.false.6
	    Predecessors according to CFG: BB#5
848B		%vreg25<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32common:%vreg25
864B		%WZR<def> = SUBSWri %vreg25, 250, 0, %NZCV<imp-def>; GPR32common:%vreg25
880B		Bcc 13, <BB#8>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#8 BB#7

896B	BB#7: derived from LLVM BB %if.then.8
	    Predecessors according to CFG: BB#2 BB#3 BB#4 BB#5 BB#6
912B		%vreg296<def> = MOVi32imm 4294967294; GPR32:%vreg296
928B		STRWui %vreg296, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg296
944B		B <BB#29>
	    Successors according to CFG: BB#29

960B	BB#8: derived from LLVM BB %if.end.9
	    Predecessors according to CFG: BB#6
976B		%vreg27<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg27
992B		CBNZW %vreg27, <BB#10>; GPR32:%vreg27
	    Successors according to CFG: BB#10 BB#9

1008B	BB#9: derived from LLVM BB %if.then.11
	    Predecessors according to CFG: BB#8
1024B		%vreg28<def> = MOVi32imm 30; GPR32:%vreg28
1040B		STRWui %vreg28, <fi#4>, 0; mem:ST4[FixedStack4] GPR32:%vreg28
	    Successors according to CFG: BB#10

1056B	BB#10: derived from LLVM BB %if.end.12
	    Predecessors according to CFG: BB#8 BB#9
1072B		%vreg32<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg32
1088B		%vreg31<def> = LDRXui %vreg32, 7; mem:LD8[%bzalloc] GPR64:%vreg31 GPR64common:%vreg32
1104B		CBNZX %vreg31, <BB#12>; GPR64:%vreg31
	    Successors according to CFG: BB#12 BB#11

1120B	BB#11: derived from LLVM BB %if.then.14
	    Predecessors according to CFG: BB#10
1136B		%vreg33<def> = ADRP <ga:@default_bzalloc>[TF=1]; GPR64common:%vreg33
1152B		%vreg34<def> = ADDXri %vreg33, <ga:@default_bzalloc>[TF=34], 0; GPR64common:%vreg34,%vreg33
1168B		%vreg36<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg36
1184B		STRXui %vreg34, %vreg36, 7; mem:ST8[%bzalloc15] GPR64common:%vreg34,%vreg36
	    Successors according to CFG: BB#12

1200B	BB#12: derived from LLVM BB %if.end.16
	    Predecessors according to CFG: BB#10 BB#11
1216B		%vreg40<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg40
1232B		%vreg39<def> = LDRXui %vreg40, 8; mem:LD8[%bzfree] GPR64:%vreg39 GPR64common:%vreg40
1248B		CBNZX %vreg39, <BB#14>; GPR64:%vreg39
	    Successors according to CFG: BB#14 BB#13

1264B	BB#13: derived from LLVM BB %if.then.18
	    Predecessors according to CFG: BB#12
1280B		%vreg41<def> = ADRP <ga:@default_bzfree>[TF=1]; GPR64common:%vreg41
1296B		%vreg42<def> = ADDXri %vreg41, <ga:@default_bzfree>[TF=34], 0; GPR64common:%vreg42,%vreg41
1312B		%vreg44<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg44
1328B		STRXui %vreg42, %vreg44, 8; mem:ST8[%bzfree19] GPR64common:%vreg42,%vreg44
	    Successors according to CFG: BB#14

1344B	BB#14: derived from LLVM BB %if.end.20
	    Predecessors according to CFG: BB#12 BB#13
1360B		%vreg52<def> = MOVi32imm 55768; GPR32:%vreg52
1376B		%vreg53<def> = MOVi32imm 1; GPR32:%vreg53
1392B		%vreg60<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg60
1408B		%vreg59<def> = LDRXui %vreg60, 7; mem:LD8[%bzalloc21] GPR64:%vreg59 GPR64common:%vreg60
1424B		%vreg57<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg57
1440B		%vreg56<def> = LDRXui %vreg57, 9; mem:LD8[%opaque] GPR64:%vreg56 GPR64common:%vreg57
1456B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1472B		%X0<def> = COPY %vreg56; GPR64:%vreg56
1488B		%W1<def> = COPY %vreg52; GPR32:%vreg52
1504B		%W2<def> = COPY %vreg53; GPR32:%vreg53
1520B		BLR %vreg59, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %W2<imp-use>, %X0<imp-def>; GPR64:%vreg59
1536B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1552B		%vreg54<def> = COPY %X0; GPR64all:%vreg54
1568B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1584B		STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)
1600B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1616B		%vreg49<def> = COPY %vreg54; GPR64:%vreg49 GPR64all:%vreg54
1632B		STRXui %vreg49, <fi#6>, 0; mem:ST8[FixedStack6] GPR64:%vreg49
1648B		%vreg46<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64:%vreg46
1664B		CBNZX %vreg46, <BB#16>; GPR64:%vreg46
	    Successors according to CFG: BB#16 BB#15

1680B	BB#15: derived from LLVM BB %if.then.24
	    Predecessors according to CFG: BB#14
1696B		%vreg295<def> = MOVi32imm 4294967293; GPR32:%vreg295
1712B		STRWui %vreg295, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg295
1728B		B <BB#29>
	    Successors according to CFG: BB#29

1744B	BB#16: derived from LLVM BB %if.end.25
	    Predecessors according to CFG: BB#14
1760B		%vreg113<def> = MOVi32imm 1; GPR32:%vreg113
1776B		%vreg130<def> = MOVi32imm 100000; GPR32:%vreg130
1792B		%vreg134<def> = COPY %XZR; GPR64:%vreg134
1808B		%vreg144<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg144
1824B		%vreg143<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg143
1840B		STRXui %vreg144, %vreg143, 0; mem:ST8[%strm26] GPR64:%vreg144 GPR64common:%vreg143
1856B		%vreg140<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg140
1872B		STRXui %vreg134, %vreg140, 3; mem:ST8[%arr1] GPR64:%vreg134 GPR64common:%vreg140
1888B		%vreg138<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg138
1904B		STRXui %vreg134, %vreg138, 4; mem:ST8[%arr2] GPR64:%vreg134 GPR64common:%vreg138
1920B		%vreg136<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg136
1936B		STRXui %vreg134, %vreg136, 5; mem:ST8[%ftab] GPR64:%vreg134 GPR64common:%vreg136
1952B		%vreg133<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg133
1968B		%vreg132<def> = MADDWrrr %vreg130, %vreg133, %WZR; GPR32:%vreg132,%vreg130,%vreg133
1984B		STRWui %vreg132, <fi#5>, 0; mem:ST4[FixedStack5] GPR32:%vreg132
2000B		%vreg128<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg128
2016B		%vreg127<def> = LDRXui %vreg128, 7; mem:LD8[%bzalloc27] GPR64:%vreg127 GPR64common:%vreg128
2032B		%vreg125<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg125
2048B		%vreg124<def> = LDRXui %vreg125, 9; mem:LD8[%opaque28] GPR64:%vreg124 GPR64common:%vreg125
2064B		%vreg122<def> = LDRSWui <fi#5>, 0; mem:LD4[FixedStack5] GPR64:%vreg122
2080B		%vreg118<def> = UBFMXri %vreg122, 62, 61; GPR64:%vreg118,%vreg122
2096B		%vreg116<def> = COPY %vreg118:sub_32; GPR32all:%vreg116 GPR64:%vreg118
2112B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2128B		%X0<def> = COPY %vreg124; GPR64:%vreg124
2144B		%W1<def> = COPY %vreg116; GPR32all:%vreg116
2160B		%W2<def> = COPY %vreg113; GPR32:%vreg113
2176B		BLR %vreg127, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %W2<imp-use>, %X0<imp-def>; GPR64:%vreg127
2192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2208B		%vreg114<def> = COPY %X0; GPR64all:%vreg114
2224B		%vreg89<def> = MOVi32imm 1; GPR32:%vreg89
2240B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2256B		STACKMAP 3, 0, 0, <fi#2>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)
2272B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2288B		%vreg109<def> = COPY %vreg114; GPR64:%vreg109 GPR64all:%vreg114
2304B		%vreg107<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg107
2320B		STRXui %vreg109, %vreg107, 3; mem:ST8[%arr132] GPR64:%vreg109 GPR64common:%vreg107
2336B		%vreg104<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg104
2352B		%vreg103<def> = LDRXui %vreg104, 7; mem:LD8[%bzalloc33] GPR64:%vreg103 GPR64common:%vreg104
2368B		%vreg101<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg101
2384B		%vreg100<def> = LDRXui %vreg101, 9; mem:LD8[%opaque34] GPR64:%vreg100 GPR64common:%vreg101
2400B		%vreg98<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32common:%vreg98
2416B		%vreg97<def> = ADDWri %vreg98, 34, 0; GPR32sp:%vreg97 GPR32common:%vreg98
2432B		%vreg94<def> = SUBREG_TO_REG 0, %vreg97, 15; GPR64:%vreg94 GPR32sp:%vreg97
2448B		%vreg95<def> = SBFMXri %vreg94, 62, 31; GPR64:%vreg95,%vreg94
2464B		%vreg92<def> = COPY %vreg95:sub_32; GPR32all:%vreg92 GPR64:%vreg95
2480B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2496B		%X0<def> = COPY %vreg100; GPR64:%vreg100
2512B		%W1<def> = COPY %vreg92; GPR32all:%vreg92
2528B		%W2<def> = COPY %vreg89; GPR32:%vreg89
2544B		BLR %vreg103, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %W2<imp-use>, %X0<imp-def>; GPR64:%vreg103
2560B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2576B		%vreg90<def> = COPY %X0; GPR64all:%vreg90
2592B		%vreg72<def> = MOVi32imm 262148; GPR32:%vreg72
2608B		%vreg73<def> = MOVi32imm 1; GPR32:%vreg73
2624B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2640B		STACKMAP 4, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)
2656B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2672B		%vreg85<def> = COPY %vreg90; GPR64:%vreg85 GPR64all:%vreg90
2688B		%vreg83<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg83
2704B		STRXui %vreg85, %vreg83, 4; mem:ST8[%arr239] GPR64:%vreg85 GPR64common:%vreg83
2720B		%vreg80<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg80
2736B		%vreg79<def> = LDRXui %vreg80, 7; mem:LD8[%bzalloc40] GPR64:%vreg79 GPR64common:%vreg80
2752B		%vreg77<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg77
2768B		%vreg76<def> = LDRXui %vreg77, 9; mem:LD8[%opaque41] GPR64:%vreg76 GPR64common:%vreg77
2784B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2800B		%X0<def> = COPY %vreg76; GPR64:%vreg76
2816B		%W1<def> = COPY %vreg72; GPR32:%vreg72
2832B		%W2<def> = COPY %vreg73; GPR32:%vreg73
2848B		BLR %vreg79, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %W2<imp-use>, %X0<imp-def>; GPR64:%vreg79
2864B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2880B		%vreg74<def> = COPY %X0; GPR64all:%vreg74
2896B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2912B		STACKMAP 5, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)
2928B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2944B		%vreg69<def> = COPY %vreg74; GPR64:%vreg69 GPR64all:%vreg74
2960B		%vreg67<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg67
2976B		STRXui %vreg69, %vreg67, 5; mem:ST8[%ftab43] GPR64:%vreg69 GPR64common:%vreg67
2992B		%vreg64<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg64
3008B		%vreg63<def> = LDRXui %vreg64, 3; mem:LD8[%arr144] GPR64:%vreg63 GPR64common:%vreg64
3024B		CBZX %vreg63, <BB#19>; GPR64:%vreg63
	    Successors according to CFG: BB#19 BB#17

3040B	BB#17: derived from LLVM BB %lor.lhs.false.47
	    Predecessors according to CFG: BB#16
3056B		%vreg148<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg148
3072B		%vreg147<def> = LDRXui %vreg148, 4; mem:LD8[%arr248] GPR64:%vreg147 GPR64common:%vreg148
3088B		CBZX %vreg147, <BB#19>; GPR64:%vreg147
	    Successors according to CFG: BB#19 BB#18

3104B	BB#18: derived from LLVM BB %lor.lhs.false.51
	    Predecessors according to CFG: BB#17
3120B		%vreg152<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg152
3136B		%vreg151<def> = LDRXui %vreg152, 5; mem:LD8[%ftab52] GPR64:%vreg151 GPR64common:%vreg152
3152B		CBNZX %vreg151, <BB#28>; GPR64:%vreg151
	    Successors according to CFG: BB#28 BB#19

3168B	BB#19: derived from LLVM BB %if.then.55
	    Predecessors according to CFG: BB#16 BB#17 BB#18
3184B		%vreg229<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg229
3200B		%vreg228<def> = LDRXui %vreg229, 3; mem:LD8[%arr156] GPR64:%vreg228 GPR64common:%vreg229
3216B		CBZX %vreg228, <BB#21>; GPR64:%vreg228
	    Successors according to CFG: BB#21 BB#20

3232B	BB#20: derived from LLVM BB %if.then.59
	    Predecessors according to CFG: BB#19
3248B		%vreg243<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg243
3264B		%vreg242<def> = LDRXui %vreg243, 8; mem:LD8[%bzfree60] GPR64:%vreg242 GPR64common:%vreg243
3280B		%vreg240<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg240
3296B		%vreg239<def> = LDRXui %vreg240, 9; mem:LD8[%opaque61] GPR64:%vreg239 GPR64common:%vreg240
3312B		%vreg237<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg237
3328B		%vreg236<def> = LDRXui %vreg237, 3; mem:LD8[%arr162] GPR64:%vreg236 GPR64common:%vreg237
3344B		%vreg234<def> = COPY %vreg236; GPR64all:%vreg234 GPR64:%vreg236
3360B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3376B		%X0<def> = COPY %vreg239; GPR64:%vreg239
3392B		%X1<def> = COPY %vreg234; GPR64all:%vreg234
3408B		BLR %vreg242, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>; GPR64:%vreg242
3424B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3440B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3456B		STACKMAP 6, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1]
3472B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#21

3488B	BB#21: derived from LLVM BB %if.end.63
	    Predecessors according to CFG: BB#19 BB#20
3504B		%vreg247<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg247
3520B		%vreg246<def> = LDRXui %vreg247, 4; mem:LD8[%arr264] GPR64:%vreg246 GPR64common:%vreg247
3536B		CBZX %vreg246, <BB#23>; GPR64:%vreg246
	    Successors according to CFG: BB#23 BB#22

3552B	BB#22: derived from LLVM BB %if.then.67
	    Predecessors according to CFG: BB#21
3568B		%vreg261<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg261
3584B		%vreg260<def> = LDRXui %vreg261, 8; mem:LD8[%bzfree68] GPR64:%vreg260 GPR64common:%vreg261
3600B		%vreg258<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg258
3616B		%vreg257<def> = LDRXui %vreg258, 9; mem:LD8[%opaque69] GPR64:%vreg257 GPR64common:%vreg258
3632B		%vreg255<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg255
3648B		%vreg254<def> = LDRXui %vreg255, 4; mem:LD8[%arr270] GPR64:%vreg254 GPR64common:%vreg255
3664B		%vreg252<def> = COPY %vreg254; GPR64all:%vreg252 GPR64:%vreg254
3680B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3696B		%X0<def> = COPY %vreg257; GPR64:%vreg257
3712B		%X1<def> = COPY %vreg252; GPR64all:%vreg252
3728B		BLR %vreg260, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>; GPR64:%vreg260
3744B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3760B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3776B		STACKMAP 7, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1]
3792B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#23

3808B	BB#23: derived from LLVM BB %if.end.71
	    Predecessors according to CFG: BB#21 BB#22
3824B		%vreg265<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg265
3840B		%vreg264<def> = LDRXui %vreg265, 5; mem:LD8[%ftab72] GPR64:%vreg264 GPR64common:%vreg265
3856B		CBZX %vreg264, <BB#25>; GPR64:%vreg264
	    Successors according to CFG: BB#25 BB#24

3872B	BB#24: derived from LLVM BB %if.then.75
	    Predecessors according to CFG: BB#23
3888B		%vreg279<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg279
3904B		%vreg278<def> = LDRXui %vreg279, 8; mem:LD8[%bzfree76] GPR64:%vreg278 GPR64common:%vreg279
3920B		%vreg276<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg276
3936B		%vreg275<def> = LDRXui %vreg276, 9; mem:LD8[%opaque77] GPR64:%vreg275 GPR64common:%vreg276
3952B		%vreg273<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg273
3968B		%vreg272<def> = LDRXui %vreg273, 5; mem:LD8[%ftab78] GPR64:%vreg272 GPR64common:%vreg273
3984B		%vreg270<def> = COPY %vreg272; GPR64all:%vreg270 GPR64:%vreg272
4000B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4016B		%X0<def> = COPY %vreg275; GPR64:%vreg275
4032B		%X1<def> = COPY %vreg270; GPR64all:%vreg270
4048B		BLR %vreg278, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>; GPR64:%vreg278
4064B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4080B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4096B		STACKMAP 8, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1]
4112B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#25

4128B	BB#25: derived from LLVM BB %if.end.79
	    Predecessors according to CFG: BB#23 BB#24
4144B		%vreg281<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64:%vreg281
4160B		CBZX %vreg281, <BB#27>; GPR64:%vreg281
	    Successors according to CFG: BB#27 BB#26

4176B	BB#26: derived from LLVM BB %if.then.82
	    Predecessors according to CFG: BB#25
4192B		%vreg293<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg293
4208B		%vreg292<def> = LDRXui %vreg293, 8; mem:LD8[%bzfree83] GPR64:%vreg292 GPR64common:%vreg293
4224B		%vreg290<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg290
4240B		%vreg289<def> = LDRXui %vreg290, 9; mem:LD8[%opaque84] GPR64:%vreg289 GPR64common:%vreg290
4256B		%vreg287<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64:%vreg287
4272B		%vreg286<def> = COPY %vreg287; GPR64all:%vreg286 GPR64:%vreg287
4288B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4304B		%X0<def> = COPY %vreg289; GPR64:%vreg289
4320B		%X1<def> = COPY %vreg286; GPR64all:%vreg286
4336B		BLR %vreg292, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>; GPR64:%vreg292
4352B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4368B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4384B		STACKMAP 9, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
4400B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#27

4416B	BB#27: derived from LLVM BB %if.end.85
	    Predecessors according to CFG: BB#25 BB#26
4432B		%vreg294<def> = MOVi32imm 4294967293; GPR32:%vreg294
4448B		STRWui %vreg294, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg294
4464B		B <BB#29>
	    Successors according to CFG: BB#29

4480B	BB#28: derived from LLVM BB %if.end.86
	    Predecessors according to CFG: BB#18
4496B		%vreg177<def> = COPY %XZR; GPR64:%vreg177
4512B		%vreg209<def> = MOVi32imm 100000; GPR32:%vreg209
4528B		%vreg219<def> = MOVi32imm 2; GPR32:%vreg219
4544B		%vreg225<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg225
4560B		STRWui %WZR, %vreg225, 165; mem:ST4[%blockNo] GPR64common:%vreg225
4576B		%vreg223<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg223
4592B		STRWui %vreg219, %vreg223, 3; mem:ST4[%state] GPR32:%vreg219 GPR64common:%vreg223
4608B		%vreg221<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg221
4624B		STRWui %vreg219, %vreg221, 2; mem:ST4[%mode] GPR32:%vreg219 GPR64common:%vreg221
4640B		%vreg218<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg218
4656B		STRWui %WZR, %vreg218, 163; mem:ST4[%combinedCRC] GPR64common:%vreg218
4672B		%vreg216<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg216
4688B		%vreg215<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg215
4704B		STRWui %vreg216, %vreg215, 166; mem:ST4[%blockSize100k87] GPR32:%vreg216 GPR64common:%vreg215
4720B		%vreg212<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg212
4736B		%vreg211<def> = MADDWrrr %vreg209, %vreg212, %WZR; GPR32common:%vreg211 GPR32:%vreg209,%vreg212
4752B		%vreg208<def> = SUBWri %vreg211, 19, 0; GPR32common:%vreg208,%vreg211
4768B		%vreg206<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg206
4784B		STRWui %vreg208, %vreg206, 28; mem:ST4[%nblockMAX] GPR32common:%vreg208 GPR64common:%vreg206
4800B		%vreg203<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg203
4816B		%vreg202<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg202
4832B		STRWui %vreg203, %vreg202, 164; mem:ST4[%verbosity89] GPR32:%vreg203 GPR64common:%vreg202
4848B		%vreg199<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg199
4864B		%vreg198<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg198
4880B		STRWui %vreg199, %vreg198, 22; mem:ST4[%workFactor90] GPR32:%vreg199 GPR64common:%vreg198
4896B		%vreg195<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg195
4912B		%vreg194<def> = LDRXui %vreg195, 4; mem:LD8[%arr291] GPR64:%vreg194 GPR64common:%vreg195
4928B		%vreg192<def> = COPY %vreg194; GPR64:%vreg192,%vreg194
4944B		%vreg190<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg190
4960B		STRXui %vreg192, %vreg190, 8; mem:ST8[%block] GPR64:%vreg192 GPR64common:%vreg190
4976B		%vreg187<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg187
4992B		%vreg186<def> = LDRXui %vreg187, 3; mem:LD8[%arr192] GPR64:%vreg186 GPR64common:%vreg187
5008B		%vreg184<def> = COPY %vreg186; GPR64:%vreg184,%vreg186
5024B		%vreg182<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg182
5040B		STRXui %vreg184, %vreg182, 9; mem:ST8[%mtfv] GPR64:%vreg184 GPR64common:%vreg182
5056B		%vreg179<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg179
5072B		STRXui %vreg177, %vreg179, 10; mem:ST8[%zbits] GPR64:%vreg177 GPR64common:%vreg179
5088B		%vreg176<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg176
5104B		%vreg175<def> = LDRXui %vreg176, 3; mem:LD8[%arr193] GPR64:%vreg175 GPR64common:%vreg176
5120B		%vreg173<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg173
5136B		STRXui %vreg175, %vreg173, 7; mem:ST8[%ptr] GPR64:%vreg175 GPR64common:%vreg173
5152B		%vreg170<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64:%vreg170
5168B		%vreg169<def> = COPY %vreg170; GPR64:%vreg169,%vreg170
5184B		%vreg167<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg167
5200B		STRXui %vreg169, %vreg167, 6; mem:ST8[%state94] GPR64:%vreg169 GPR64common:%vreg167
5216B		%vreg164<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg164
5232B		STRWui %WZR, %vreg164, 3; mem:ST4[%total_in_lo32] GPR64common:%vreg164
5248B		%vreg162<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg162
5264B		STRWui %WZR, %vreg162, 4; mem:ST4[%total_in_hi32] GPR64common:%vreg162
5280B		%vreg160<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg160
5296B		STRWui %WZR, %vreg160, 9; mem:ST4[%total_out_lo32] GPR64common:%vreg160
5312B		%vreg158<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg158
5328B		STRWui %WZR, %vreg158, 10; mem:ST4[%total_out_hi32] GPR64common:%vreg158
5344B		%vreg156<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64:%vreg156
5360B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5376B		%X0<def> = COPY %vreg156; GPR64:%vreg156
5392B		BL <ga:@init_RL>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>
5408B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5424B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5440B		STACKMAP 10, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack6]
5456B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5472B		%vreg154<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64:%vreg154
5488B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5504B		%X0<def> = COPY %vreg154; GPR64:%vreg154
5520B		BL <ga:@prepare_new_block>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>
5536B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5552B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5568B		STACKMAP 11, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
5584B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5600B		STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
	    Successors according to CFG: BB#29

5616B	BB#29: derived from LLVM BB %return
	    Predecessors according to CFG: BB#1 BB#28 BB#27 BB#15 BB#7
5632B		%vreg299<def> = ADRP <ga:@BZ2_bzCompressInit>[TF=1]; GPR64common:%vreg299
5648B		%vreg300<def> = ADDXri %vreg299, <ga:@BZ2_bzCompressInit>[TF=34], 0; GPR64sp:%vreg300 GPR64common:%vreg299
5664B		%vreg301<def> = COPY %vreg300; GPR64all:%vreg301 GPR64sp:%vreg300
5680B		%vreg302<def> = COPY %vreg14; GPR64all:%vreg302 GPR64:%vreg14
5696B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5712B		%X0<def> = COPY %vreg301; GPR64all:%vreg301
5728B		%X1<def> = COPY %vreg302; GPR64all:%vreg302
5744B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
5760B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5776B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5792B		STACKMAP 12, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
5808B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5824B		%vreg298<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0] GPR32:%vreg298
5840B		%W0<def> = COPY %vreg298; GPR32:%vreg298
5856B		RET_ReallyLR %W0<imp-use>

# End machine code for function BZ2_bzCompressInit.

********** SIMPLE REGISTER COALESCING **********
********** Function: BZ2_bzCompressInit
********** JOINING INTERVALS ***********
if.then.8:
if.then.55:
return:
5712B	%X0<def> = COPY %vreg301; GPR64all:%vreg301
	Considering merging %vreg301 with %X0
	Can only merge into reserved registers.
5728B	%X1<def> = COPY %vreg302; GPR64all:%vreg302
	Considering merging %vreg302 with %X1
	Can only merge into reserved registers.
5840B	%W0<def> = COPY %vreg298; GPR32:%vreg298
	Considering merging %vreg298 with %W0
	Can only merge into reserved registers.
if.end.12:
if.end.16:
if.end.20:
1472B	%X0<def> = COPY %vreg56; GPR64:%vreg56
	Considering merging %vreg56 with %X0
	Can only merge into reserved registers.
1488B	%W1<def> = COPY %vreg52; GPR32:%vreg52
	Considering merging %vreg52 with %W1
	Can only merge into reserved registers.
Remat: %W1<def> = MOVi32imm 55768
Shrink: %vreg52 [1360r,1488r:0)  0@1360r
All defs dead: 1360r	%vreg52<def,dead> = MOVi32imm 55768; GPR32:%vreg52
Shrunk: %vreg52 [1360r,1360d:0)  0@1360r
Deleting dead def 1360r	%vreg52<def,dead> = MOVi32imm 55768; GPR32:%vreg52
1504B	%W2<def> = COPY %vreg53; GPR32:%vreg53
	Considering merging %vreg53 with %W2
	Can only merge into reserved registers.
Remat: %W2<def> = MOVi32imm 1
Shrink: %vreg53 [1376r,1504r:0)  0@1376r
All defs dead: 1376r	%vreg53<def,dead> = MOVi32imm 1; GPR32:%vreg53
Shrunk: %vreg53 [1376r,1376d:0)  0@1376r
Deleting dead def 1376r	%vreg53<def,dead> = MOVi32imm 1; GPR32:%vreg53
1552B	%vreg54<def> = COPY %X0; GPR64all:%vreg54
	Considering merging %vreg54 with %X0
	Can only merge into reserved registers.
if.end.63:
if.end.71:
if.end.79:
if.end:
lor.lhs.false:
lor.lhs.false.2:
lor.lhs.false.4:
lor.lhs.false.6:
if.end.9:
if.end.25:
1792B	%vreg134<def> = COPY %XZR; GPR64:%vreg134
	Considering merging %vreg134 with %XZR
		RHS = %vreg134 [1792r,1936r:0)  0@1792r
		updated: 1936B	STRXui %XZR, %vreg136, 5; mem:ST8[%ftab] GPR64common:%vreg136
		updated: 1904B	STRXui %XZR, %vreg138, 4; mem:ST8[%arr2] GPR64common:%vreg138
		updated: 1872B	STRXui %XZR, %vreg140, 3; mem:ST8[%arr1] GPR64common:%vreg140
	Success: %vreg134 -> %XZR
	Result = %XZR
2128B	%X0<def> = COPY %vreg124; GPR64:%vreg124
	Considering merging %vreg124 with %X0
	Can only merge into reserved registers.
2144B	%W1<def> = COPY %vreg116; GPR32all:%vreg116
	Considering merging %vreg116 with %W1
	Can only merge into reserved registers.
2160B	%W2<def> = COPY %vreg113; GPR32:%vreg113
	Considering merging %vreg113 with %W2
	Can only merge into reserved registers.
Remat: %W2<def> = MOVi32imm 1
Shrink: %vreg113 [1760r,2160r:0)  0@1760r
All defs dead: 1760r	%vreg113<def,dead> = MOVi32imm 1; GPR32:%vreg113
Shrunk: %vreg113 [1760r,1760d:0)  0@1760r
Deleting dead def 1760r	%vreg113<def,dead> = MOVi32imm 1; GPR32:%vreg113
2208B	%vreg114<def> = COPY %X0; GPR64all:%vreg114
	Considering merging %vreg114 with %X0
	Can only merge into reserved registers.
2432B	%vreg94<def> = SUBREG_TO_REG 0, %vreg97, 15; GPR64:%vreg94 GPR32sp:%vreg97
	Considering merging to GPR64common with %vreg97 in %vreg94:sub_32
		RHS = %vreg97 [2416r,2432r:0)  0@2416r
		LHS = %vreg94 [2432r,2448r:0)  0@2432r
		merge %vreg94:0@2432r into %vreg97:0@2416r --> @2416r
		erased:	2432r	%vreg94<def> = SUBREG_TO_REG 0, %vreg97, 15; GPR64:%vreg94 GPR32sp:%vreg97
AllocationOrder(GPR64common) = [ %X8 %X9 %X10 %X11 %X12 %X13 %X14 %X15 %X16 %X17 %X18 %X0 %X1 %X2 %X3 %X4 %X5 %X6 %X7 %X19 %X20 %X21 %X22 %X23 %X24 %X25 %X26 %X27 %X28 %LR ]
		updated: 2416B	%vreg94:sub_32<def,read-undef> = ADDWri %vreg98, 34, 0; GPR64common:%vreg94 GPR32common:%vreg98
	Success: %vreg97:sub_32 -> %vreg94
	Result = %vreg94 [2416r,2448r:0)  0@2416r
2496B	%X0<def> = COPY %vreg100; GPR64:%vreg100
	Considering merging %vreg100 with %X0
	Can only merge into reserved registers.
2512B	%W1<def> = COPY %vreg92; GPR32all:%vreg92
	Considering merging %vreg92 with %W1
	Can only merge into reserved registers.
2528B	%W2<def> = COPY %vreg89; GPR32:%vreg89
	Considering merging %vreg89 with %W2
	Can only merge into reserved registers.
Remat: %W2<def> = MOVi32imm 1
Shrink: %vreg89 [2224r,2528r:0)  0@2224r
All defs dead: 2224r	%vreg89<def,dead> = MOVi32imm 1; GPR32:%vreg89
Shrunk: %vreg89 [2224r,2224d:0)  0@2224r
Deleting dead def 2224r	%vreg89<def,dead> = MOVi32imm 1; GPR32:%vreg89
2576B	%vreg90<def> = COPY %X0; GPR64all:%vreg90
	Considering merging %vreg90 with %X0
	Can only merge into reserved registers.
2800B	%X0<def> = COPY %vreg76; GPR64:%vreg76
	Considering merging %vreg76 with %X0
	Can only merge into reserved registers.
2816B	%W1<def> = COPY %vreg72; GPR32:%vreg72
	Considering merging %vreg72 with %W1
	Can only merge into reserved registers.
Remat: %W1<def> = MOVi32imm 262148
Shrink: %vreg72 [2592r,2816r:0)  0@2592r
All defs dead: 2592r	%vreg72<def,dead> = MOVi32imm 262148; GPR32:%vreg72
Shrunk: %vreg72 [2592r,2592d:0)  0@2592r
Deleting dead def 2592r	%vreg72<def,dead> = MOVi32imm 262148; GPR32:%vreg72
2832B	%W2<def> = COPY %vreg73; GPR32:%vreg73
	Considering merging %vreg73 with %W2
	Can only merge into reserved registers.
Remat: %W2<def> = MOVi32imm 1
Shrink: %vreg73 [2608r,2832r:0)  0@2608r
All defs dead: 2608r	%vreg73<def,dead> = MOVi32imm 1; GPR32:%vreg73
Shrunk: %vreg73 [2608r,2608d:0)  0@2608r
Deleting dead def 2608r	%vreg73<def,dead> = MOVi32imm 1; GPR32:%vreg73
2880B	%vreg74<def> = COPY %X0; GPR64all:%vreg74
	Considering merging %vreg74 with %X0
	Can only merge into reserved registers.
lor.lhs.false.47:
lor.lhs.false.51:
if.end.85:
entry:
16B	%vreg14<def> = COPY %LR; GPR64:%vreg14
	Considering merging %vreg14 with %LR
	Can only merge into reserved registers.
32B	%vreg6<def> = COPY %W3; GPR32:%vreg6
	Considering merging %vreg6 with %W3
	Can only merge into reserved registers.
48B	%vreg4<def> = COPY %W2; GPR32:%vreg4
	Considering merging %vreg4 with %W2
	Can only merge into reserved registers.
64B	%vreg2<def> = COPY %W1; GPR32:%vreg2
	Considering merging %vreg2 with %W1
	Can only merge into reserved registers.
80B	%vreg0<def> = COPY %X0; GPR64:%vreg0
	Considering merging %vreg0 with %X0
	Can only merge into reserved registers.
240B	%X0<def> = COPY %vreg12; GPR64all:%vreg12
	Considering merging %vreg12 with %X0
	Can only merge into reserved registers.
256B	%X1<def> = COPY %vreg13; GPR64all:%vreg13
	Considering merging %vreg13 with %X1
	Can only merge into reserved registers.
464B	%vreg9<def> = COPY %W0; GPR32:%vreg9
	Considering merging %vreg9 with %W0
	Can only merge into reserved registers.
if.then:
if.then.11:
if.then.14:
if.then.18:
if.then.24:
if.then.59:
3376B	%X0<def> = COPY %vreg239; GPR64:%vreg239
	Considering merging %vreg239 with %X0
	Can only merge into reserved registers.
3392B	%X1<def> = COPY %vreg234; GPR64all:%vreg234
	Considering merging %vreg234 with %X1
	Can only merge into reserved registers.
if.then.67:
3696B	%X0<def> = COPY %vreg257; GPR64:%vreg257
	Considering merging %vreg257 with %X0
	Can only merge into reserved registers.
3712B	%X1<def> = COPY %vreg252; GPR64all:%vreg252
	Considering merging %vreg252 with %X1
	Can only merge into reserved registers.
if.then.75:
4016B	%X0<def> = COPY %vreg275; GPR64:%vreg275
	Considering merging %vreg275 with %X0
	Can only merge into reserved registers.
4032B	%X1<def> = COPY %vreg270; GPR64all:%vreg270
	Considering merging %vreg270 with %X1
	Can only merge into reserved registers.
if.then.82:
4304B	%X0<def> = COPY %vreg289; GPR64:%vreg289
	Considering merging %vreg289 with %X0
	Can only merge into reserved registers.
4320B	%X1<def> = COPY %vreg286; GPR64all:%vreg286
	Considering merging %vreg286 with %X1
	Can only merge into reserved registers.
if.end.86:
4496B	%vreg177<def> = COPY %XZR; GPR64:%vreg177
	Considering merging %vreg177 with %XZR
		RHS = %vreg177 [4496r,5072r:0)  0@4496r
		updated: 5072B	STRXui %XZR, %vreg179, 10; mem:ST8[%zbits] GPR64common:%vreg179
	Success: %vreg177 -> %XZR
	Result = %XZR
5376B	%X0<def> = COPY %vreg156; GPR64:%vreg156
	Considering merging %vreg156 with %X0
	Can only merge into reserved registers.
5504B	%X0<def> = COPY %vreg154; GPR64:%vreg154
	Considering merging %vreg154 with %X0
	Can only merge into reserved registers.
5664B	%vreg301<def> = COPY %vreg300; GPR64all:%vreg301 GPR64sp:%vreg300
	Considering merging to GPR64sp with %vreg300 in %vreg301
		RHS = %vreg300 [5648r,5664r:0)  0@5648r
		LHS = %vreg301 [5664r,5712r:0)  0@5664r
		merge %vreg301:0@5664r into %vreg300:0@5648r --> @5648r
		erased:	5664r	%vreg301<def> = COPY %vreg300; GPR64all:%vreg301 GPR64sp:%vreg300
		updated: 5648B	%vreg301<def> = ADDXri %vreg299, <ga:@BZ2_bzCompressInit>[TF=34], 0; GPR64sp:%vreg301 GPR64common:%vreg299
	Success: %vreg300 -> %vreg301
	Result = %vreg301 [5648r,5712r:0)  0@5648r
5680B	%vreg302<def> = COPY %vreg14; GPR64all:%vreg302 GPR64:%vreg14
	Considering merging to GPR64 with %vreg14 in %vreg302
		RHS = %vreg14 [16r,5680r:0)  0@16r
		LHS = %vreg302 [5680r,5728r:0)  0@5680r
		merge %vreg302:0@5680r into %vreg14:0@16r --> @16r
		erased:	5680r	%vreg302<def> = COPY %vreg14; GPR64all:%vreg302 GPR64:%vreg14
		updated: 16B	%vreg302<def> = COPY %LR; GPR64:%vreg302
		updated: 208B	%vreg13<def> = COPY %vreg302; GPR64all:%vreg13 GPR64:%vreg302
	Success: %vreg14 -> %vreg302
	Result = %vreg302 [16r,5728r:0)  0@16r
1616B	%vreg49<def> = COPY %vreg54; GPR64:%vreg49 GPR64all:%vreg54
	Considering merging to GPR64 with %vreg54 in %vreg49
		RHS = %vreg54 [1552r,1616r:0)  0@1552r
		LHS = %vreg49 [1616r,1632r:0)  0@1616r
		merge %vreg49:0@1616r into %vreg54:0@1552r --> @1552r
		erased:	1616r	%vreg49<def> = COPY %vreg54; GPR64:%vreg49 GPR64all:%vreg54
		updated: 1552B	%vreg49<def> = COPY %X0; GPR64:%vreg49
	Success: %vreg54 -> %vreg49
	Result = %vreg49 [1552r,1632r:0)  0@1552r
2096B	%vreg116<def> = COPY %vreg118:sub_32; GPR32all:%vreg116 GPR64:%vreg118
	Considering merging to GPR64 with %vreg116 in %vreg118:sub_32
		RHS = %vreg116 [2096r,2144r:0)  0@2096r
		LHS = %vreg118 [2080r,2096r:0)  0@2080r
		merge %vreg116:0@2096r into %vreg118:0@2080r --> @2080r
		erased:	2096r	%vreg116<def> = COPY %vreg118:sub_32; GPR32all:%vreg116 GPR64:%vreg118
		updated: 2144B	%W1<def> = COPY %vreg118:sub_32; GPR64:%vreg118
	Success: %vreg116:sub_32 -> %vreg118
	Result = %vreg118 [2080r,2144r:0)  0@2080r
2288B	%vreg109<def> = COPY %vreg114; GPR64:%vreg109 GPR64all:%vreg114
	Considering merging to GPR64 with %vreg114 in %vreg109
		RHS = %vreg114 [2208r,2288r:0)  0@2208r
		LHS = %vreg109 [2288r,2320r:0)  0@2288r
		merge %vreg109:0@2288r into %vreg114:0@2208r --> @2208r
		erased:	2288r	%vreg109<def> = COPY %vreg114; GPR64:%vreg109 GPR64all:%vreg114
		updated: 2208B	%vreg109<def> = COPY %X0; GPR64:%vreg109
	Success: %vreg114 -> %vreg109
	Result = %vreg109 [2208r,2320r:0)  0@2208r
2464B	%vreg92<def> = COPY %vreg95:sub_32; GPR32all:%vreg92 GPR64:%vreg95
	Considering merging to GPR64 with %vreg92 in %vreg95:sub_32
		RHS = %vreg92 [2464r,2512r:0)  0@2464r
		LHS = %vreg95 [2448r,2464r:0)  0@2448r
		merge %vreg92:0@2464r into %vreg95:0@2448r --> @2448r
		erased:	2464r	%vreg92<def> = COPY %vreg95:sub_32; GPR32all:%vreg92 GPR64:%vreg95
		updated: 2512B	%W1<def> = COPY %vreg95:sub_32; GPR64:%vreg95
	Success: %vreg92:sub_32 -> %vreg95
	Result = %vreg95 [2448r,2512r:0)  0@2448r
2672B	%vreg85<def> = COPY %vreg90; GPR64:%vreg85 GPR64all:%vreg90
	Considering merging to GPR64 with %vreg90 in %vreg85
		RHS = %vreg90 [2576r,2672r:0)  0@2576r
		LHS = %vreg85 [2672r,2704r:0)  0@2672r
		merge %vreg85:0@2672r into %vreg90:0@2576r --> @2576r
		erased:	2672r	%vreg85<def> = COPY %vreg90; GPR64:%vreg85 GPR64all:%vreg90
		updated: 2576B	%vreg85<def> = COPY %X0; GPR64:%vreg85
	Success: %vreg90 -> %vreg85
	Result = %vreg85 [2576r,2704r:0)  0@2576r
2944B	%vreg69<def> = COPY %vreg74; GPR64:%vreg69 GPR64all:%vreg74
	Considering merging to GPR64 with %vreg74 in %vreg69
		RHS = %vreg74 [2880r,2944r:0)  0@2880r
		LHS = %vreg69 [2944r,2976r:0)  0@2944r
		merge %vreg69:0@2944r into %vreg74:0@2880r --> @2880r
		erased:	2944r	%vreg69<def> = COPY %vreg74; GPR64:%vreg69 GPR64all:%vreg74
		updated: 2880B	%vreg69<def> = COPY %X0; GPR64:%vreg69
	Success: %vreg74 -> %vreg69
	Result = %vreg69 [2880r,2976r:0)  0@2880r
96B	%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
	Considering merging to GPR64 with %vreg0 in %vreg1
		RHS = %vreg0 [80r,96r:0)  0@80r
		LHS = %vreg1 [96r,352r:0)  0@96r
		merge %vreg1:0@96r into %vreg0:0@80r --> @80r
		erased:	96r	%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
		updated: 80B	%vreg1<def> = COPY %X0; GPR64:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [80r,352r:0)  0@80r
112B	%vreg3<def> = COPY %vreg2; GPR32:%vreg3,%vreg2
	Considering merging to GPR32 with %vreg2 in %vreg3
		RHS = %vreg2 [64r,112r:0)  0@64r
		LHS = %vreg3 [112r,368r:0)  0@112r
		merge %vreg3:0@112r into %vreg2:0@64r --> @64r
		erased:	112r	%vreg3<def> = COPY %vreg2; GPR32:%vreg3,%vreg2
		updated: 64B	%vreg3<def> = COPY %W1; GPR32:%vreg3
	Success: %vreg2 -> %vreg3
	Result = %vreg3 [64r,368r:0)  0@64r
128B	%vreg5<def> = COPY %vreg4; GPR32:%vreg5,%vreg4
	Considering merging to GPR32 with %vreg4 in %vreg5
		RHS = %vreg4 [48r,128r:0)  0@48r
		LHS = %vreg5 [128r,384r:0)  0@128r
		merge %vreg5:0@128r into %vreg4:0@48r --> @48r
		erased:	128r	%vreg5<def> = COPY %vreg4; GPR32:%vreg5,%vreg4
		updated: 48B	%vreg5<def> = COPY %W2; GPR32:%vreg5
	Success: %vreg4 -> %vreg5
	Result = %vreg5 [48r,384r:0)  0@48r
144B	%vreg7<def> = COPY %vreg6; GPR32:%vreg7,%vreg6
	Considering merging to GPR32 with %vreg6 in %vreg7
		RHS = %vreg6 [32r,144r:0)  0@32r
		LHS = %vreg7 [144r,400r:0)  0@144r
		merge %vreg7:0@144r into %vreg6:0@32r --> @32r
		erased:	144r	%vreg7<def> = COPY %vreg6; GPR32:%vreg7,%vreg6
		updated: 32B	%vreg7<def> = COPY %W3; GPR32:%vreg7
	Success: %vreg6 -> %vreg7
	Result = %vreg7 [32r,400r:0)  0@32r
192B	%vreg12<def> = COPY %vreg11; GPR64all:%vreg12 GPR64sp:%vreg11
	Considering merging to GPR64sp with %vreg11 in %vreg12
		RHS = %vreg11 [176r,192r:0)  0@176r
		LHS = %vreg12 [192r,240r:0)  0@192r
		merge %vreg12:0@192r into %vreg11:0@176r --> @176r
		erased:	192r	%vreg12<def> = COPY %vreg11; GPR64all:%vreg12 GPR64sp:%vreg11
		updated: 176B	%vreg12<def> = ADDXri %vreg10, <ga:@BZ2_bzCompressInit>[TF=34], 0; GPR64sp:%vreg12 GPR64common:%vreg10
	Success: %vreg11 -> %vreg12
	Result = %vreg12 [176r,240r:0)  0@176r
208B	%vreg13<def> = COPY %vreg302; GPR64all:%vreg13 GPR64:%vreg302
	Considering merging to GPR64 with %vreg302 in %vreg13
		RHS = %vreg302 [16r,5728r:0)  0@16r
		LHS = %vreg13 [208r,256r:0)  0@208r
		merge %vreg13:0@208r into %vreg302:0@16r --> @16r
		erased:	208r	%vreg13<def> = COPY %vreg302; GPR64all:%vreg13 GPR64:%vreg302
		updated: 16B	%vreg13<def> = COPY %LR; GPR64:%vreg13
		updated: 5728B	%X1<def> = COPY %vreg13; GPR64:%vreg13
	Success: %vreg302 -> %vreg13
	Result = %vreg13 [16r,5728r:0)  0@16r
3344B	%vreg234<def> = COPY %vreg236; GPR64all:%vreg234 GPR64:%vreg236
	Considering merging to GPR64 with %vreg236 in %vreg234
		RHS = %vreg236 [3328r,3344r:0)  0@3328r
		LHS = %vreg234 [3344r,3392r:0)  0@3344r
		merge %vreg234:0@3344r into %vreg236:0@3328r --> @3328r
		erased:	3344r	%vreg234<def> = COPY %vreg236; GPR64all:%vreg234 GPR64:%vreg236
		updated: 3328B	%vreg234<def> = LDRXui %vreg237, 3; mem:LD8[%arr162] GPR64:%vreg234 GPR64common:%vreg237
	Success: %vreg236 -> %vreg234
	Result = %vreg234 [3328r,3392r:0)  0@3328r
3664B	%vreg252<def> = COPY %vreg254; GPR64all:%vreg252 GPR64:%vreg254
	Considering merging to GPR64 with %vreg254 in %vreg252
		RHS = %vreg254 [3648r,3664r:0)  0@3648r
		LHS = %vreg252 [3664r,3712r:0)  0@3664r
		merge %vreg252:0@3664r into %vreg254:0@3648r --> @3648r
		erased:	3664r	%vreg252<def> = COPY %vreg254; GPR64all:%vreg252 GPR64:%vreg254
		updated: 3648B	%vreg252<def> = LDRXui %vreg255, 4; mem:LD8[%arr270] GPR64:%vreg252 GPR64common:%vreg255
	Success: %vreg254 -> %vreg252
	Result = %vreg252 [3648r,3712r:0)  0@3648r
3984B	%vreg270<def> = COPY %vreg272; GPR64all:%vreg270 GPR64:%vreg272
	Considering merging to GPR64 with %vreg272 in %vreg270
		RHS = %vreg272 [3968r,3984r:0)  0@3968r
		LHS = %vreg270 [3984r,4032r:0)  0@3984r
		merge %vreg270:0@3984r into %vreg272:0@3968r --> @3968r
		erased:	3984r	%vreg270<def> = COPY %vreg272; GPR64all:%vreg270 GPR64:%vreg272
		updated: 3968B	%vreg270<def> = LDRXui %vreg273, 5; mem:LD8[%ftab78] GPR64:%vreg270 GPR64common:%vreg273
	Success: %vreg272 -> %vreg270
	Result = %vreg270 [3968r,4032r:0)  0@3968r
4272B	%vreg286<def> = COPY %vreg287; GPR64all:%vreg286 GPR64:%vreg287
	Considering merging to GPR64 with %vreg287 in %vreg286
		RHS = %vreg287 [4256r,4272r:0)  0@4256r
		LHS = %vreg286 [4272r,4320r:0)  0@4272r
		merge %vreg286:0@4272r into %vreg287:0@4256r --> @4256r
		erased:	4272r	%vreg286<def> = COPY %vreg287; GPR64all:%vreg286 GPR64:%vreg287
		updated: 4256B	%vreg286<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64:%vreg286
	Success: %vreg287 -> %vreg286
	Result = %vreg286 [4256r,4320r:0)  0@4256r
4928B	%vreg192<def> = COPY %vreg194; GPR64:%vreg192,%vreg194
	Considering merging to GPR64 with %vreg194 in %vreg192
		RHS = %vreg194 [4912r,4928r:0)  0@4912r
		LHS = %vreg192 [4928r,4960r:0)  0@4928r
		merge %vreg192:0@4928r into %vreg194:0@4912r --> @4912r
		erased:	4928r	%vreg192<def> = COPY %vreg194; GPR64:%vreg192,%vreg194
		updated: 4912B	%vreg192<def> = LDRXui %vreg195, 4; mem:LD8[%arr291] GPR64:%vreg192 GPR64common:%vreg195
	Success: %vreg194 -> %vreg192
	Result = %vreg192 [4912r,4960r:0)  0@4912r
5008B	%vreg184<def> = COPY %vreg186; GPR64:%vreg184,%vreg186
	Considering merging to GPR64 with %vreg186 in %vreg184
		RHS = %vreg186 [4992r,5008r:0)  0@4992r
		LHS = %vreg184 [5008r,5040r:0)  0@5008r
		merge %vreg184:0@5008r into %vreg186:0@4992r --> @4992r
		erased:	5008r	%vreg184<def> = COPY %vreg186; GPR64:%vreg184,%vreg186
		updated: 4992B	%vreg184<def> = LDRXui %vreg187, 3; mem:LD8[%arr192] GPR64:%vreg184 GPR64common:%vreg187
	Success: %vreg186 -> %vreg184
	Result = %vreg184 [4992r,5040r:0)  0@4992r
5168B	%vreg169<def> = COPY %vreg170; GPR64:%vreg169,%vreg170
	Considering merging to GPR64 with %vreg170 in %vreg169
		RHS = %vreg170 [5152r,5168r:0)  0@5152r
		LHS = %vreg169 [5168r,5200r:0)  0@5168r
		merge %vreg169:0@5168r into %vreg170:0@5152r --> @5152r
		erased:	5168r	%vreg169<def> = COPY %vreg170; GPR64:%vreg169,%vreg170
		updated: 5152B	%vreg169<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64:%vreg169
	Success: %vreg170 -> %vreg169
	Result = %vreg169 [5152r,5200r:0)  0@5152r
5712B	%X0<def> = COPY %vreg301; GPR64sp:%vreg301
	Considering merging %vreg301 with %X0
	Can only merge into reserved registers.
5728B	%X1<def> = COPY %vreg13; GPR64:%vreg13
	Considering merging %vreg13 with %X1
	Can only merge into reserved registers.
2144B	%W1<def> = COPY %vreg118:sub_32; GPR64:%vreg118
	Considering merging %vreg118 with %X1
	Can only merge into reserved registers.
2512B	%W1<def> = COPY %vreg95:sub_32; GPR64:%vreg95
	Considering merging %vreg95 with %X1
	Can only merge into reserved registers.
240B	%X0<def> = COPY %vreg12; GPR64sp:%vreg12
	Considering merging %vreg12 with %X0
	Can only merge into reserved registers.
256B	%X1<def> = COPY %vreg13; GPR64:%vreg13
	Considering merging %vreg13 with %X1
	Can only merge into reserved registers.
3392B	%X1<def> = COPY %vreg234; GPR64:%vreg234
	Considering merging %vreg234 with %X1
	Can only merge into reserved registers.
3712B	%X1<def> = COPY %vreg252; GPR64:%vreg252
	Considering merging %vreg252 with %X1
	Can only merge into reserved registers.
4032B	%X1<def> = COPY %vreg270; GPR64:%vreg270
	Considering merging %vreg270 with %X1
	Can only merge into reserved registers.
4320B	%X1<def> = COPY %vreg286; GPR64:%vreg286
	Considering merging %vreg286 with %X1
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
W30 [0B,16r:0)[272r,272d:25)[320e,320d:13)[432r,432d:26)[496e,496d:12)[1520r,1520d:24)[1584e,1584d:11)[2176r,2176d:21)[2256e,2256d:10)[2544r,2544d:22)[2640e,2640d:9)[2848r,2848d:23)[2912e,2912d:8)[3408r,3408d:18)[3456e,3456d:7)[3728r,3728d:17)[3776e,3776d:6)[4048r,4048d:16)[4096e,4096d:5)[4336r,4336d:15)[4384e,4384d:4)[5392r,5392d:19)[5440e,5440d:3)[5520r,5520d:20)[5568e,5568d:2)[5744r,5744d:14)[5792e,5792d:1)  0@0B-phi 1@5792e 2@5568e 3@5440e 4@4384e 5@4096e 6@3776e 7@3456e 8@2912e 9@2640e 10@2256e 11@1584e 12@496e 13@320e 14@5744r 15@4336r 16@4048r 17@3728r 18@3408r 19@5392r 20@5520r 21@2176r 22@2544r 23@2848r 24@1520r 25@272r 26@432r
WZR [688r,688d:2)[752r,752d:1)[864r,864d:0)  0@864r 1@752r 2@688r
W0 [0B,80r:0)[240r,272r:18)[432r,464r:2)[1472r,1520r:17)[1520r,1552r:16)[2128r,2176r:11)[2176r,2208r:10)[2496r,2544r:13)[2544r,2576r:12)[2800r,2848r:15)[2848r,2880r:14)[3376r,3408r:7)[3696r,3728r:6)[4016r,4048r:5)[4304r,4336r:4)[5376r,5392r:8)[5504r,5520r:9)[5712r,5744r:3)[5840r,5856r:1)  0@0B-phi 1@5840r 2@432r 3@5712r 4@4304r 5@4016r 6@3696r 7@3376r 8@5376r 9@5504r 10@2176r 11@2128r 12@2544r 13@2496r 14@2848r 15@2800r 16@1520r 17@1472r 18@240r
W1 [0B,64r:0)[256r,272r:10)[1488r,1520r:4)[2144r,2176r:1)[2512r,2544r:2)[2816r,2848r:3)[3392r,3408r:9)[3712r,3728r:8)[4032r,4048r:7)[4320r,4336r:6)[5728r,5744r:5)  0@0B-phi 1@2144r 2@2512r 3@2816r 4@1488r 5@5728r 6@4320r 7@4032r 8@3712r 9@3392r 10@256r
W2 [0B,48r:0)[1504r,1520r:4)[2160r,2176r:1)[2528r,2544r:2)[2832r,2848r:3)  0@0B-phi 1@2160r 2@2528r 3@2832r 4@1504r
W3 [0B,32r:0)  0@0B-phi
%vreg1 [80r,352r:0)  0@80r
%vreg3 [64r,368r:0)  0@64r
%vreg5 [48r,384r:0)  0@48r
%vreg7 [32r,400r:0)  0@32r
%vreg9 [464r,528r:0)  0@464r
%vreg10 [160r,176r:0)  0@160r
%vreg12 [176r,240r:0)  0@176r
%vreg13 [16r,5728r:0)  0@16r
%vreg15 [560r,576r:0)  0@560r
%vreg17 [624r,640r:0)  0@624r
%vreg19 [672r,688r:0)  0@672r
%vreg21 [736r,752r:0)  0@736r
%vreg23 [800r,816r:0)  0@800r
%vreg25 [848r,864r:0)  0@848r
%vreg27 [976r,992r:0)  0@976r
%vreg28 [1024r,1040r:0)  0@1024r
%vreg31 [1088r,1104r:0)  0@1088r
%vreg32 [1072r,1088r:0)  0@1072r
%vreg33 [1136r,1152r:0)  0@1136r
%vreg34 [1152r,1184r:0)  0@1152r
%vreg36 [1168r,1184r:0)  0@1168r
%vreg39 [1232r,1248r:0)  0@1232r
%vreg40 [1216r,1232r:0)  0@1216r
%vreg41 [1280r,1296r:0)  0@1280r
%vreg42 [1296r,1328r:0)  0@1296r
%vreg44 [1312r,1328r:0)  0@1312r
%vreg46 [1648r,1664r:0)  0@1648r
%vreg49 [1552r,1632r:0)  0@1552r
%vreg56 [1440r,1472r:0)  0@1440r
%vreg57 [1424r,1440r:0)  0@1424r
%vreg59 [1408r,1520r:0)  0@1408r
%vreg60 [1392r,1408r:0)  0@1392r
%vreg63 [3008r,3024r:0)  0@3008r
%vreg64 [2992r,3008r:0)  0@2992r
%vreg67 [2960r,2976r:0)  0@2960r
%vreg69 [2880r,2976r:0)  0@2880r
%vreg76 [2768r,2800r:0)  0@2768r
%vreg77 [2752r,2768r:0)  0@2752r
%vreg79 [2736r,2848r:0)  0@2736r
%vreg80 [2720r,2736r:0)  0@2720r
%vreg83 [2688r,2704r:0)  0@2688r
%vreg85 [2576r,2704r:0)  0@2576r
%vreg94 [2416r,2448r:0)  0@2416r
%vreg95 [2448r,2512r:0)  0@2448r
%vreg98 [2400r,2416r:0)  0@2400r
%vreg100 [2384r,2496r:0)  0@2384r
%vreg101 [2368r,2384r:0)  0@2368r
%vreg103 [2352r,2544r:0)  0@2352r
%vreg104 [2336r,2352r:0)  0@2336r
%vreg107 [2304r,2320r:0)  0@2304r
%vreg109 [2208r,2320r:0)  0@2208r
%vreg118 [2080r,2144r:0)  0@2080r
%vreg122 [2064r,2080r:0)  0@2064r
%vreg124 [2048r,2128r:0)  0@2048r
%vreg125 [2032r,2048r:0)  0@2032r
%vreg127 [2016r,2176r:0)  0@2016r
%vreg128 [2000r,2016r:0)  0@2000r
%vreg130 [1776r,1968r:0)  0@1776r
%vreg132 [1968r,1984r:0)  0@1968r
%vreg133 [1952r,1968r:0)  0@1952r
%vreg136 [1920r,1936r:0)  0@1920r
%vreg138 [1888r,1904r:0)  0@1888r
%vreg140 [1856r,1872r:0)  0@1856r
%vreg143 [1824r,1840r:0)  0@1824r
%vreg144 [1808r,1840r:0)  0@1808r
%vreg147 [3072r,3088r:0)  0@3072r
%vreg148 [3056r,3072r:0)  0@3056r
%vreg151 [3136r,3152r:0)  0@3136r
%vreg152 [3120r,3136r:0)  0@3120r
%vreg154 [5472r,5504r:0)  0@5472r
%vreg156 [5344r,5376r:0)  0@5344r
%vreg158 [5312r,5328r:0)  0@5312r
%vreg160 [5280r,5296r:0)  0@5280r
%vreg162 [5248r,5264r:0)  0@5248r
%vreg164 [5216r,5232r:0)  0@5216r
%vreg167 [5184r,5200r:0)  0@5184r
%vreg169 [5152r,5200r:0)  0@5152r
%vreg173 [5120r,5136r:0)  0@5120r
%vreg175 [5104r,5136r:0)  0@5104r
%vreg176 [5088r,5104r:0)  0@5088r
%vreg179 [5056r,5072r:0)  0@5056r
%vreg182 [5024r,5040r:0)  0@5024r
%vreg184 [4992r,5040r:0)  0@4992r
%vreg187 [4976r,4992r:0)  0@4976r
%vreg190 [4944r,4960r:0)  0@4944r
%vreg192 [4912r,4960r:0)  0@4912r
%vreg195 [4896r,4912r:0)  0@4896r
%vreg198 [4864r,4880r:0)  0@4864r
%vreg199 [4848r,4880r:0)  0@4848r
%vreg202 [4816r,4832r:0)  0@4816r
%vreg203 [4800r,4832r:0)  0@4800r
%vreg206 [4768r,4784r:0)  0@4768r
%vreg208 [4752r,4784r:0)  0@4752r
%vreg209 [4512r,4736r:0)  0@4512r
%vreg211 [4736r,4752r:0)  0@4736r
%vreg212 [4720r,4736r:0)  0@4720r
%vreg215 [4688r,4704r:0)  0@4688r
%vreg216 [4672r,4704r:0)  0@4672r
%vreg218 [4640r,4656r:0)  0@4640r
%vreg219 [4528r,4624r:0)  0@4528r
%vreg221 [4608r,4624r:0)  0@4608r
%vreg223 [4576r,4592r:0)  0@4576r
%vreg225 [4544r,4560r:0)  0@4544r
%vreg228 [3200r,3216r:0)  0@3200r
%vreg229 [3184r,3200r:0)  0@3184r
%vreg234 [3328r,3392r:0)  0@3328r
%vreg237 [3312r,3328r:0)  0@3312r
%vreg239 [3296r,3376r:0)  0@3296r
%vreg240 [3280r,3296r:0)  0@3280r
%vreg242 [3264r,3408r:0)  0@3264r
%vreg243 [3248r,3264r:0)  0@3248r
%vreg246 [3520r,3536r:0)  0@3520r
%vreg247 [3504r,3520r:0)  0@3504r
%vreg252 [3648r,3712r:0)  0@3648r
%vreg255 [3632r,3648r:0)  0@3632r
%vreg257 [3616r,3696r:0)  0@3616r
%vreg258 [3600r,3616r:0)  0@3600r
%vreg260 [3584r,3728r:0)  0@3584r
%vreg261 [3568r,3584r:0)  0@3568r
%vreg264 [3840r,3856r:0)  0@3840r
%vreg265 [3824r,3840r:0)  0@3824r
%vreg270 [3968r,4032r:0)  0@3968r
%vreg273 [3952r,3968r:0)  0@3952r
%vreg275 [3936r,4016r:0)  0@3936r
%vreg276 [3920r,3936r:0)  0@3920r
%vreg278 [3904r,4048r:0)  0@3904r
%vreg279 [3888r,3904r:0)  0@3888r
%vreg281 [4144r,4160r:0)  0@4144r
%vreg286 [4256r,4320r:0)  0@4256r
%vreg289 [4240r,4304r:0)  0@4240r
%vreg290 [4224r,4240r:0)  0@4224r
%vreg292 [4208r,4336r:0)  0@4208r
%vreg293 [4192r,4208r:0)  0@4192r
%vreg294 [4432r,4448r:0)  0@4432r
%vreg295 [1696r,1712r:0)  0@1696r
%vreg296 [912r,928r:0)  0@912r
%vreg298 [5824r,5840r:0)  0@5824r
%vreg299 [5632r,5648r:0)  0@5632r
%vreg301 [5648r,5712r:0)  0@5648r
RegMasks: 272r 432r 1520r 2176r 2544r 2848r 3408r 3728r 4048r 4336r 5392r 5520r 5744r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzCompressInit: Post SSA
Frame Objects:
  fi#0: size=4, align=4, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=4, align=4, at location [SP]
  fi#3: size=4, align=4, at location [SP]
  fi#4: size=4, align=4, at location [SP]
  fi#5: size=4, align=4, at location [SP]
  fi#6: size=8, align=8, at location [SP]
Function Live Ins: %X0 in %vreg0, %W1 in %vreg2, %W2 in %vreg4, %W3 in %vreg6, %LR in %vreg14

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %W1 %W2 %W3 %LR
16B		%vreg13<def> = COPY %LR; GPR64:%vreg13
32B		%vreg7<def> = COPY %W3; GPR32:%vreg7
48B		%vreg5<def> = COPY %W2; GPR32:%vreg5
64B		%vreg3<def> = COPY %W1; GPR32:%vreg3
80B		%vreg1<def> = COPY %X0; GPR64:%vreg1
160B		%vreg10<def> = ADRP <ga:@BZ2_bzCompressInit>[TF=1]; GPR64common:%vreg10
176B		%vreg12<def> = ADDXri %vreg10, <ga:@BZ2_bzCompressInit>[TF=34], 0; GPR64sp:%vreg12 GPR64common:%vreg10
224B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
240B		%X0<def> = COPY %vreg12; GPR64sp:%vreg12
256B		%X1<def> = COPY %vreg13; GPR64:%vreg13
272B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
288B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
304B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
320B		STACKMAP 0, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, %vreg1, 0, <fi#1>, 0, %vreg5, 0, <fi#3>, 0, %vreg7, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4) GPR32:%vreg3,%vreg5,%vreg7 GPR64:%vreg1
336B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
352B		STRXui %vreg1, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg1
368B		STRWui %vreg3, <fi#2>, 0; mem:ST4[FixedStack2] GPR32:%vreg3
384B		STRWui %vreg5, <fi#3>, 0; mem:ST4[FixedStack3] GPR32:%vreg5
400B		STRWui %vreg7, <fi#4>, 0; mem:ST4[FixedStack4] GPR32:%vreg7
416B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
432B		BL <ga:@bz_config_ok>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-def>
448B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
464B		%vreg9<def> = COPY %W0; GPR32:%vreg9
480B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
496B		STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)
512B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
528B		CBNZW %vreg9, <BB#2>; GPR32:%vreg9
	    Successors according to CFG: BB#2 BB#1

544B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
560B		%vreg15<def> = MOVi32imm 4294967287; GPR32:%vreg15
576B		STRWui %vreg15, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg15
592B		B <BB#29>
	    Successors according to CFG: BB#29

608B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0
624B		%vreg17<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg17
640B		CBZX %vreg17, <BB#7>; GPR64:%vreg17
	    Successors according to CFG: BB#7 BB#3

656B	BB#3: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#2
672B		%vreg19<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32common:%vreg19
688B		%WZR<def> = SUBSWri %vreg19, 1, 0, %NZCV<imp-def>; GPR32common:%vreg19
704B		Bcc 11, <BB#7>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#7 BB#4

720B	BB#4: derived from LLVM BB %lor.lhs.false.2
	    Predecessors according to CFG: BB#3
736B		%vreg21<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32common:%vreg21
752B		%WZR<def> = SUBSWri %vreg21, 9, 0, %NZCV<imp-def>; GPR32common:%vreg21
768B		Bcc 12, <BB#7>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#7 BB#5

784B	BB#5: derived from LLVM BB %lor.lhs.false.4
	    Predecessors according to CFG: BB#4
800B		%vreg23<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg23
816B		TBNZW %vreg23, 31, <BB#7>; GPR32:%vreg23
	    Successors according to CFG: BB#7 BB#6

832B	BB#6: derived from LLVM BB %lor.lhs.false.6
	    Predecessors according to CFG: BB#5
848B		%vreg25<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32common:%vreg25
864B		%WZR<def> = SUBSWri %vreg25, 250, 0, %NZCV<imp-def>; GPR32common:%vreg25
880B		Bcc 13, <BB#8>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#8 BB#7

896B	BB#7: derived from LLVM BB %if.then.8
	    Predecessors according to CFG: BB#2 BB#3 BB#4 BB#5 BB#6
912B		%vreg296<def> = MOVi32imm 4294967294; GPR32:%vreg296
928B		STRWui %vreg296, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg296
944B		B <BB#29>
	    Successors according to CFG: BB#29

960B	BB#8: derived from LLVM BB %if.end.9
	    Predecessors according to CFG: BB#6
976B		%vreg27<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg27
992B		CBNZW %vreg27, <BB#10>; GPR32:%vreg27
	    Successors according to CFG: BB#10 BB#9

1008B	BB#9: derived from LLVM BB %if.then.11
	    Predecessors according to CFG: BB#8
1024B		%vreg28<def> = MOVi32imm 30; GPR32:%vreg28
1040B		STRWui %vreg28, <fi#4>, 0; mem:ST4[FixedStack4] GPR32:%vreg28
	    Successors according to CFG: BB#10

1056B	BB#10: derived from LLVM BB %if.end.12
	    Predecessors according to CFG: BB#8 BB#9
1072B		%vreg32<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg32
1088B		%vreg31<def> = LDRXui %vreg32, 7; mem:LD8[%bzalloc] GPR64:%vreg31 GPR64common:%vreg32
1104B		CBNZX %vreg31, <BB#12>; GPR64:%vreg31
	    Successors according to CFG: BB#12 BB#11

1120B	BB#11: derived from LLVM BB %if.then.14
	    Predecessors according to CFG: BB#10
1136B		%vreg33<def> = ADRP <ga:@default_bzalloc>[TF=1]; GPR64common:%vreg33
1152B		%vreg34<def> = ADDXri %vreg33, <ga:@default_bzalloc>[TF=34], 0; GPR64common:%vreg34,%vreg33
1168B		%vreg36<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg36
1184B		STRXui %vreg34, %vreg36, 7; mem:ST8[%bzalloc15] GPR64common:%vreg34,%vreg36
	    Successors according to CFG: BB#12

1200B	BB#12: derived from LLVM BB %if.end.16
	    Predecessors according to CFG: BB#10 BB#11
1216B		%vreg40<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg40
1232B		%vreg39<def> = LDRXui %vreg40, 8; mem:LD8[%bzfree] GPR64:%vreg39 GPR64common:%vreg40
1248B		CBNZX %vreg39, <BB#14>; GPR64:%vreg39
	    Successors according to CFG: BB#14 BB#13

1264B	BB#13: derived from LLVM BB %if.then.18
	    Predecessors according to CFG: BB#12
1280B		%vreg41<def> = ADRP <ga:@default_bzfree>[TF=1]; GPR64common:%vreg41
1296B		%vreg42<def> = ADDXri %vreg41, <ga:@default_bzfree>[TF=34], 0; GPR64common:%vreg42,%vreg41
1312B		%vreg44<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg44
1328B		STRXui %vreg42, %vreg44, 8; mem:ST8[%bzfree19] GPR64common:%vreg42,%vreg44
	    Successors according to CFG: BB#14

1344B	BB#14: derived from LLVM BB %if.end.20
	    Predecessors according to CFG: BB#12 BB#13
1392B		%vreg60<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg60
1408B		%vreg59<def> = LDRXui %vreg60, 7; mem:LD8[%bzalloc21] GPR64:%vreg59 GPR64common:%vreg60
1424B		%vreg57<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg57
1440B		%vreg56<def> = LDRXui %vreg57, 9; mem:LD8[%opaque] GPR64:%vreg56 GPR64common:%vreg57
1456B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1472B		%X0<def> = COPY %vreg56; GPR64:%vreg56
1488B		%W1<def> = MOVi32imm 55768
1504B		%W2<def> = MOVi32imm 1
1520B		BLR %vreg59, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %W2<imp-use>, %X0<imp-def>; GPR64:%vreg59
1536B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1552B		%vreg49<def> = COPY %X0; GPR64:%vreg49
1568B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1584B		STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)
1600B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1632B		STRXui %vreg49, <fi#6>, 0; mem:ST8[FixedStack6] GPR64:%vreg49
1648B		%vreg46<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64:%vreg46
1664B		CBNZX %vreg46, <BB#16>; GPR64:%vreg46
	    Successors according to CFG: BB#16 BB#15

1680B	BB#15: derived from LLVM BB %if.then.24
	    Predecessors according to CFG: BB#14
1696B		%vreg295<def> = MOVi32imm 4294967293; GPR32:%vreg295
1712B		STRWui %vreg295, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg295
1728B		B <BB#29>
	    Successors according to CFG: BB#29

1744B	BB#16: derived from LLVM BB %if.end.25
	    Predecessors according to CFG: BB#14
1776B		%vreg130<def> = MOVi32imm 100000; GPR32:%vreg130
1808B		%vreg144<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg144
1824B		%vreg143<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg143
1840B		STRXui %vreg144, %vreg143, 0; mem:ST8[%strm26] GPR64:%vreg144 GPR64common:%vreg143
1856B		%vreg140<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg140
1872B		STRXui %XZR, %vreg140, 3; mem:ST8[%arr1] GPR64common:%vreg140
1888B		%vreg138<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg138
1904B		STRXui %XZR, %vreg138, 4; mem:ST8[%arr2] GPR64common:%vreg138
1920B		%vreg136<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg136
1936B		STRXui %XZR, %vreg136, 5; mem:ST8[%ftab] GPR64common:%vreg136
1952B		%vreg133<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg133
1968B		%vreg132<def> = MADDWrrr %vreg130, %vreg133, %WZR; GPR32:%vreg132,%vreg130,%vreg133
1984B		STRWui %vreg132, <fi#5>, 0; mem:ST4[FixedStack5] GPR32:%vreg132
2000B		%vreg128<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg128
2016B		%vreg127<def> = LDRXui %vreg128, 7; mem:LD8[%bzalloc27] GPR64:%vreg127 GPR64common:%vreg128
2032B		%vreg125<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg125
2048B		%vreg124<def> = LDRXui %vreg125, 9; mem:LD8[%opaque28] GPR64:%vreg124 GPR64common:%vreg125
2064B		%vreg122<def> = LDRSWui <fi#5>, 0; mem:LD4[FixedStack5] GPR64:%vreg122
2080B		%vreg118<def> = UBFMXri %vreg122, 62, 61; GPR64:%vreg118,%vreg122
2112B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2128B		%X0<def> = COPY %vreg124; GPR64:%vreg124
2144B		%W1<def> = COPY %vreg118:sub_32; GPR64:%vreg118
2160B		%W2<def> = MOVi32imm 1
2176B		BLR %vreg127, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %W2<imp-use>, %X0<imp-def>; GPR64:%vreg127
2192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2208B		%vreg109<def> = COPY %X0; GPR64:%vreg109
2240B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2256B		STACKMAP 3, 0, 0, <fi#2>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)
2272B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2304B		%vreg107<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg107
2320B		STRXui %vreg109, %vreg107, 3; mem:ST8[%arr132] GPR64:%vreg109 GPR64common:%vreg107
2336B		%vreg104<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg104
2352B		%vreg103<def> = LDRXui %vreg104, 7; mem:LD8[%bzalloc33] GPR64:%vreg103 GPR64common:%vreg104
2368B		%vreg101<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg101
2384B		%vreg100<def> = LDRXui %vreg101, 9; mem:LD8[%opaque34] GPR64:%vreg100 GPR64common:%vreg101
2400B		%vreg98<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32common:%vreg98
2416B		%vreg94:sub_32<def,read-undef> = ADDWri %vreg98, 34, 0; GPR64common:%vreg94 GPR32common:%vreg98
2448B		%vreg95<def> = SBFMXri %vreg94, 62, 31; GPR64:%vreg95 GPR64common:%vreg94
2480B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2496B		%X0<def> = COPY %vreg100; GPR64:%vreg100
2512B		%W1<def> = COPY %vreg95:sub_32; GPR64:%vreg95
2528B		%W2<def> = MOVi32imm 1
2544B		BLR %vreg103, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %W2<imp-use>, %X0<imp-def>; GPR64:%vreg103
2560B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2576B		%vreg85<def> = COPY %X0; GPR64:%vreg85
2624B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2640B		STACKMAP 4, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)
2656B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2688B		%vreg83<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg83
2704B		STRXui %vreg85, %vreg83, 4; mem:ST8[%arr239] GPR64:%vreg85 GPR64common:%vreg83
2720B		%vreg80<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg80
2736B		%vreg79<def> = LDRXui %vreg80, 7; mem:LD8[%bzalloc40] GPR64:%vreg79 GPR64common:%vreg80
2752B		%vreg77<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg77
2768B		%vreg76<def> = LDRXui %vreg77, 9; mem:LD8[%opaque41] GPR64:%vreg76 GPR64common:%vreg77
2784B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2800B		%X0<def> = COPY %vreg76; GPR64:%vreg76
2816B		%W1<def> = MOVi32imm 262148
2832B		%W2<def> = MOVi32imm 1
2848B		BLR %vreg79, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %W2<imp-use>, %X0<imp-def>; GPR64:%vreg79
2864B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2880B		%vreg69<def> = COPY %X0; GPR64:%vreg69
2896B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2912B		STACKMAP 5, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)
2928B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2960B		%vreg67<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg67
2976B		STRXui %vreg69, %vreg67, 5; mem:ST8[%ftab43] GPR64:%vreg69 GPR64common:%vreg67
2992B		%vreg64<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg64
3008B		%vreg63<def> = LDRXui %vreg64, 3; mem:LD8[%arr144] GPR64:%vreg63 GPR64common:%vreg64
3024B		CBZX %vreg63, <BB#19>; GPR64:%vreg63
	    Successors according to CFG: BB#19 BB#17

3040B	BB#17: derived from LLVM BB %lor.lhs.false.47
	    Predecessors according to CFG: BB#16
3056B		%vreg148<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg148
3072B		%vreg147<def> = LDRXui %vreg148, 4; mem:LD8[%arr248] GPR64:%vreg147 GPR64common:%vreg148
3088B		CBZX %vreg147, <BB#19>; GPR64:%vreg147
	    Successors according to CFG: BB#19 BB#18

3104B	BB#18: derived from LLVM BB %lor.lhs.false.51
	    Predecessors according to CFG: BB#17
3120B		%vreg152<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg152
3136B		%vreg151<def> = LDRXui %vreg152, 5; mem:LD8[%ftab52] GPR64:%vreg151 GPR64common:%vreg152
3152B		CBNZX %vreg151, <BB#28>; GPR64:%vreg151
	    Successors according to CFG: BB#28 BB#19

3168B	BB#19: derived from LLVM BB %if.then.55
	    Predecessors according to CFG: BB#16 BB#17 BB#18
3184B		%vreg229<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg229
3200B		%vreg228<def> = LDRXui %vreg229, 3; mem:LD8[%arr156] GPR64:%vreg228 GPR64common:%vreg229
3216B		CBZX %vreg228, <BB#21>; GPR64:%vreg228
	    Successors according to CFG: BB#21 BB#20

3232B	BB#20: derived from LLVM BB %if.then.59
	    Predecessors according to CFG: BB#19
3248B		%vreg243<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg243
3264B		%vreg242<def> = LDRXui %vreg243, 8; mem:LD8[%bzfree60] GPR64:%vreg242 GPR64common:%vreg243
3280B		%vreg240<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg240
3296B		%vreg239<def> = LDRXui %vreg240, 9; mem:LD8[%opaque61] GPR64:%vreg239 GPR64common:%vreg240
3312B		%vreg237<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg237
3328B		%vreg234<def> = LDRXui %vreg237, 3; mem:LD8[%arr162] GPR64:%vreg234 GPR64common:%vreg237
3360B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3376B		%X0<def> = COPY %vreg239; GPR64:%vreg239
3392B		%X1<def> = COPY %vreg234; GPR64:%vreg234
3408B		BLR %vreg242, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>; GPR64:%vreg242
3424B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3440B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3456B		STACKMAP 6, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1]
3472B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#21

3488B	BB#21: derived from LLVM BB %if.end.63
	    Predecessors according to CFG: BB#19 BB#20
3504B		%vreg247<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg247
3520B		%vreg246<def> = LDRXui %vreg247, 4; mem:LD8[%arr264] GPR64:%vreg246 GPR64common:%vreg247
3536B		CBZX %vreg246, <BB#23>; GPR64:%vreg246
	    Successors according to CFG: BB#23 BB#22

3552B	BB#22: derived from LLVM BB %if.then.67
	    Predecessors according to CFG: BB#21
3568B		%vreg261<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg261
3584B		%vreg260<def> = LDRXui %vreg261, 8; mem:LD8[%bzfree68] GPR64:%vreg260 GPR64common:%vreg261
3600B		%vreg258<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg258
3616B		%vreg257<def> = LDRXui %vreg258, 9; mem:LD8[%opaque69] GPR64:%vreg257 GPR64common:%vreg258
3632B		%vreg255<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg255
3648B		%vreg252<def> = LDRXui %vreg255, 4; mem:LD8[%arr270] GPR64:%vreg252 GPR64common:%vreg255
3680B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3696B		%X0<def> = COPY %vreg257; GPR64:%vreg257
3712B		%X1<def> = COPY %vreg252; GPR64:%vreg252
3728B		BLR %vreg260, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>; GPR64:%vreg260
3744B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3760B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3776B		STACKMAP 7, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1]
3792B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#23

3808B	BB#23: derived from LLVM BB %if.end.71
	    Predecessors according to CFG: BB#21 BB#22
3824B		%vreg265<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg265
3840B		%vreg264<def> = LDRXui %vreg265, 5; mem:LD8[%ftab72] GPR64:%vreg264 GPR64common:%vreg265
3856B		CBZX %vreg264, <BB#25>; GPR64:%vreg264
	    Successors according to CFG: BB#25 BB#24

3872B	BB#24: derived from LLVM BB %if.then.75
	    Predecessors according to CFG: BB#23
3888B		%vreg279<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg279
3904B		%vreg278<def> = LDRXui %vreg279, 8; mem:LD8[%bzfree76] GPR64:%vreg278 GPR64common:%vreg279
3920B		%vreg276<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg276
3936B		%vreg275<def> = LDRXui %vreg276, 9; mem:LD8[%opaque77] GPR64:%vreg275 GPR64common:%vreg276
3952B		%vreg273<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg273
3968B		%vreg270<def> = LDRXui %vreg273, 5; mem:LD8[%ftab78] GPR64:%vreg270 GPR64common:%vreg273
4000B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4016B		%X0<def> = COPY %vreg275; GPR64:%vreg275
4032B		%X1<def> = COPY %vreg270; GPR64:%vreg270
4048B		BLR %vreg278, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>; GPR64:%vreg278
4064B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4080B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4096B		STACKMAP 8, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1]
4112B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#25

4128B	BB#25: derived from LLVM BB %if.end.79
	    Predecessors according to CFG: BB#23 BB#24
4144B		%vreg281<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64:%vreg281
4160B		CBZX %vreg281, <BB#27>; GPR64:%vreg281
	    Successors according to CFG: BB#27 BB#26

4176B	BB#26: derived from LLVM BB %if.then.82
	    Predecessors according to CFG: BB#25
4192B		%vreg293<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg293
4208B		%vreg292<def> = LDRXui %vreg293, 8; mem:LD8[%bzfree83] GPR64:%vreg292 GPR64common:%vreg293
4224B		%vreg290<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg290
4240B		%vreg289<def> = LDRXui %vreg290, 9; mem:LD8[%opaque84] GPR64:%vreg289 GPR64common:%vreg290
4256B		%vreg286<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64:%vreg286
4288B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4304B		%X0<def> = COPY %vreg289; GPR64:%vreg289
4320B		%X1<def> = COPY %vreg286; GPR64:%vreg286
4336B		BLR %vreg292, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>; GPR64:%vreg292
4352B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4368B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4384B		STACKMAP 9, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
4400B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#27

4416B	BB#27: derived from LLVM BB %if.end.85
	    Predecessors according to CFG: BB#25 BB#26
4432B		%vreg294<def> = MOVi32imm 4294967293; GPR32:%vreg294
4448B		STRWui %vreg294, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg294
4464B		B <BB#29>
	    Successors according to CFG: BB#29

4480B	BB#28: derived from LLVM BB %if.end.86
	    Predecessors according to CFG: BB#18
4512B		%vreg209<def> = MOVi32imm 100000; GPR32:%vreg209
4528B		%vreg219<def> = MOVi32imm 2; GPR32:%vreg219
4544B		%vreg225<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg225
4560B		STRWui %WZR, %vreg225, 165; mem:ST4[%blockNo] GPR64common:%vreg225
4576B		%vreg223<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg223
4592B		STRWui %vreg219, %vreg223, 3; mem:ST4[%state] GPR32:%vreg219 GPR64common:%vreg223
4608B		%vreg221<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg221
4624B		STRWui %vreg219, %vreg221, 2; mem:ST4[%mode] GPR32:%vreg219 GPR64common:%vreg221
4640B		%vreg218<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg218
4656B		STRWui %WZR, %vreg218, 163; mem:ST4[%combinedCRC] GPR64common:%vreg218
4672B		%vreg216<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg216
4688B		%vreg215<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg215
4704B		STRWui %vreg216, %vreg215, 166; mem:ST4[%blockSize100k87] GPR32:%vreg216 GPR64common:%vreg215
4720B		%vreg212<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg212
4736B		%vreg211<def> = MADDWrrr %vreg209, %vreg212, %WZR; GPR32common:%vreg211 GPR32:%vreg209,%vreg212
4752B		%vreg208<def> = SUBWri %vreg211, 19, 0; GPR32common:%vreg208,%vreg211
4768B		%vreg206<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg206
4784B		STRWui %vreg208, %vreg206, 28; mem:ST4[%nblockMAX] GPR32common:%vreg208 GPR64common:%vreg206
4800B		%vreg203<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg203
4816B		%vreg202<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg202
4832B		STRWui %vreg203, %vreg202, 164; mem:ST4[%verbosity89] GPR32:%vreg203 GPR64common:%vreg202
4848B		%vreg199<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg199
4864B		%vreg198<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg198
4880B		STRWui %vreg199, %vreg198, 22; mem:ST4[%workFactor90] GPR32:%vreg199 GPR64common:%vreg198
4896B		%vreg195<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg195
4912B		%vreg192<def> = LDRXui %vreg195, 4; mem:LD8[%arr291] GPR64:%vreg192 GPR64common:%vreg195
4944B		%vreg190<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg190
4960B		STRXui %vreg192, %vreg190, 8; mem:ST8[%block] GPR64:%vreg192 GPR64common:%vreg190
4976B		%vreg187<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg187
4992B		%vreg184<def> = LDRXui %vreg187, 3; mem:LD8[%arr192] GPR64:%vreg184 GPR64common:%vreg187
5024B		%vreg182<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg182
5040B		STRXui %vreg184, %vreg182, 9; mem:ST8[%mtfv] GPR64:%vreg184 GPR64common:%vreg182
5056B		%vreg179<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg179
5072B		STRXui %XZR, %vreg179, 10; mem:ST8[%zbits] GPR64common:%vreg179
5088B		%vreg176<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg176
5104B		%vreg175<def> = LDRXui %vreg176, 3; mem:LD8[%arr193] GPR64:%vreg175 GPR64common:%vreg176
5120B		%vreg173<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg173
5136B		STRXui %vreg175, %vreg173, 7; mem:ST8[%ptr] GPR64:%vreg175 GPR64common:%vreg173
5152B		%vreg169<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64:%vreg169
5184B		%vreg167<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg167
5200B		STRXui %vreg169, %vreg167, 6; mem:ST8[%state94] GPR64:%vreg169 GPR64common:%vreg167
5216B		%vreg164<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg164
5232B		STRWui %WZR, %vreg164, 3; mem:ST4[%total_in_lo32] GPR64common:%vreg164
5248B		%vreg162<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg162
5264B		STRWui %WZR, %vreg162, 4; mem:ST4[%total_in_hi32] GPR64common:%vreg162
5280B		%vreg160<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg160
5296B		STRWui %WZR, %vreg160, 9; mem:ST4[%total_out_lo32] GPR64common:%vreg160
5312B		%vreg158<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg158
5328B		STRWui %WZR, %vreg158, 10; mem:ST4[%total_out_hi32] GPR64common:%vreg158
5344B		%vreg156<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64:%vreg156
5360B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5376B		%X0<def> = COPY %vreg156; GPR64:%vreg156
5392B		BL <ga:@init_RL>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>
5408B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5424B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5440B		STACKMAP 10, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack6]
5456B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5472B		%vreg154<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64:%vreg154
5488B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5504B		%X0<def> = COPY %vreg154; GPR64:%vreg154
5520B		BL <ga:@prepare_new_block>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>
5536B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5552B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5568B		STACKMAP 11, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
5584B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5600B		STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
	    Successors according to CFG: BB#29

5616B	BB#29: derived from LLVM BB %return
	    Predecessors according to CFG: BB#1 BB#28 BB#27 BB#15 BB#7
5632B		%vreg299<def> = ADRP <ga:@BZ2_bzCompressInit>[TF=1]; GPR64common:%vreg299
5648B		%vreg301<def> = ADDXri %vreg299, <ga:@BZ2_bzCompressInit>[TF=34], 0; GPR64sp:%vreg301 GPR64common:%vreg299
5696B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5712B		%X0<def> = COPY %vreg301; GPR64sp:%vreg301
5728B		%X1<def> = COPY %vreg13; GPR64:%vreg13
5744B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
5760B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5776B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5792B		STACKMAP 12, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
5808B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5824B		%vreg298<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0] GPR32:%vreg298
5840B		%W0<def> = COPY %vreg298; GPR32:%vreg298
5856B		RET_ReallyLR %W0<imp-use>

# End machine code for function BZ2_bzCompressInit.

handleMove 1152B -> 1176B: %vreg34<def> = ADDXri %vreg33, <ga:@default_bzalloc>[TF=34], 0; GPR64common:%vreg34,%vreg33
     %vreg34:	[1152r,1184r:0)  0@1152r
        -->	[1176r,1184r:0)  0@1176r
     %vreg33:	[1136r,1152r:0)  0@1136r
        -->	[1136r,1176r:0)  0@1136r
handleMove 1136B -> 1172B: %vreg33<def> = ADRP <ga:@default_bzalloc>[TF=1]; GPR64common:%vreg33
     %vreg33:	[1136r,1176r:0)  0@1136r
        -->	[1172r,1176r:0)  0@1172r
handleMove 1296B -> 1320B: %vreg42<def> = ADDXri %vreg41, <ga:@default_bzfree>[TF=34], 0; GPR64common:%vreg42,%vreg41
     %vreg42:	[1296r,1328r:0)  0@1296r
        -->	[1320r,1328r:0)  0@1320r
     %vreg41:	[1280r,1296r:0)  0@1280r
        -->	[1280r,1320r:0)  0@1280r
handleMove 1280B -> 1316B: %vreg41<def> = ADRP <ga:@default_bzfree>[TF=1]; GPR64common:%vreg41
     %vreg41:	[1280r,1320r:0)  0@1280r
        -->	[1316r,1320r:0)  0@1316r
handleMove 1472B -> 1512B: %X0<def> = COPY %vreg56; GPR64:%vreg56
     W0:	[0B,80r:0)[240r,272r:18)[432r,464r:2)[1472r,1520r:17)[1520r,1552r:16)[2128r,2176r:11)[2176r,2208r:10)[2496r,2544r:13)[2544r,2576r:12)[2800r,2848r:15)[2848r,2880r:14)[3376r,3408r:7)[3696r,3728r:6)[4016r,4048r:5)[4304r,4336r:4)[5376r,5392r:8)[5504r,5520r:9)[5712r,5744r:3)[5840r,5856r:1)  0@0B-phi 1@5840r 2@432r 3@5712r 4@4304r 5@4016r 6@3696r 7@3376r 8@5376r 9@5504r 10@2176r 11@2128r 12@2544r 13@2496r 14@2848r 15@2800r 16@1520r 17@1472r 18@240r
        -->	[0B,80r:0)[240r,272r:18)[432r,464r:2)[1512r,1520r:17)[1520r,1552r:16)[2128r,2176r:11)[2176r,2208r:10)[2496r,2544r:13)[2544r,2576r:12)[2800r,2848r:15)[2848r,2880r:14)[3376r,3408r:7)[3696r,3728r:6)[4016r,4048r:5)[4304r,4336r:4)[5376r,5392r:8)[5504r,5520r:9)[5712r,5744r:3)[5840r,5856r:1)  0@0B-phi 1@5840r 2@432r 3@5712r 4@4304r 5@4016r 6@3696r 7@3376r 8@5376r 9@5504r 10@2176r 11@2128r 12@2544r 13@2496r 14@2848r 15@2800r 16@1520r 17@1512r 18@240r
     %vreg56:	[1440r,1472r:0)  0@1440r
        -->	[1440r,1512r:0)  0@1440r
handleMove 1408B -> 1432B: %vreg59<def> = LDRXui %vreg60, 7; mem:LD8[%bzalloc21] GPR64:%vreg59 GPR64common:%vreg60
     %vreg59:	[1408r,1520r:0)  0@1408r
        -->	[1432r,1520r:0)  0@1432r
     %vreg60:	[1392r,1408r:0)  0@1392r
        -->	[1392r,1432r:0)  0@1392r
handleMove 2800B -> 2840B: %X0<def> = COPY %vreg76; GPR64:%vreg76
     W0:	[0B,80r:0)[240r,272r:18)[432r,464r:2)[1512r,1520r:17)[1520r,1552r:16)[2128r,2176r:11)[2176r,2208r:10)[2496r,2544r:13)[2544r,2576r:12)[2800r,2848r:15)[2848r,2880r:14)[3376r,3408r:7)[3696r,3728r:6)[4016r,4048r:5)[4304r,4336r:4)[5376r,5392r:8)[5504r,5520r:9)[5712r,5744r:3)[5840r,5856r:1)  0@0B-phi 1@5840r 2@432r 3@5712r 4@4304r 5@4016r 6@3696r 7@3376r 8@5376r 9@5504r 10@2176r 11@2128r 12@2544r 13@2496r 14@2848r 15@2800r 16@1520r 17@1512r 18@240r
        -->	[0B,80r:0)[240r,272r:18)[432r,464r:2)[1512r,1520r:17)[1520r,1552r:16)[2128r,2176r:11)[2176r,2208r:10)[2496r,2544r:13)[2544r,2576r:12)[2840r,2848r:15)[2848r,2880r:14)[3376r,3408r:7)[3696r,3728r:6)[4016r,4048r:5)[4304r,4336r:4)[5376r,5392r:8)[5504r,5520r:9)[5712r,5744r:3)[5840r,5856r:1)  0@0B-phi 1@5840r 2@432r 3@5712r 4@4304r 5@4016r 6@3696r 7@3376r 8@5376r 9@5504r 10@2176r 11@2128r 12@2544r 13@2496r 14@2848r 15@2840r 16@1520r 17@1512r 18@240r
     %vreg76:	[2768r,2800r:0)  0@2768r
        -->	[2768r,2840r:0)  0@2768r
handleMove 2736B -> 2760B: %vreg79<def> = LDRXui %vreg80, 7; mem:LD8[%bzalloc40] GPR64:%vreg79 GPR64common:%vreg80
     %vreg79:	[2736r,2848r:0)  0@2736r
        -->	[2760r,2848r:0)  0@2760r
     %vreg80:	[2720r,2736r:0)  0@2720r
        -->	[2720r,2760r:0)  0@2720r
handleMove 2528B -> 2488B: %W2<def> = MOVi32imm 1
     W2:	[0B,48r:0)[1504r,1520r:4)[2160r,2176r:1)[2528r,2544r:2)[2832r,2848r:3)  0@0B-phi 1@2160r 2@2528r 3@2832r 4@1504r
        -->	[0B,48r:0)[1504r,1520r:4)[2160r,2176r:1)[2488r,2544r:2)[2832r,2848r:3)  0@0B-phi 1@2160r 2@2488r 3@2832r 4@1504r
handleMove 2384B -> 2408B: %vreg100<def> = LDRXui %vreg101, 9; mem:LD8[%opaque34] GPR64:%vreg100 GPR64common:%vreg101
     %vreg100:	[2384r,2496r:0)  0@2384r
        -->	[2408r,2496r:0)  0@2408r
     %vreg101:	[2368r,2384r:0)  0@2368r
        -->	[2368r,2408r:0)  0@2368r
handleMove 2352B -> 2404B: %vreg103<def> = LDRXui %vreg104, 7; mem:LD8[%bzalloc33] GPR64:%vreg103 GPR64common:%vreg104
     %vreg103:	[2352r,2544r:0)  0@2352r
        -->	[2404r,2544r:0)  0@2404r
     %vreg104:	[2336r,2352r:0)  0@2336r
        -->	[2336r,2404r:0)  0@2336r
handleMove 2160B -> 2120B: %W2<def> = MOVi32imm 1
     W2:	[0B,48r:0)[1504r,1520r:4)[2160r,2176r:1)[2488r,2544r:2)[2832r,2848r:3)  0@0B-phi 1@2160r 2@2488r 3@2832r 4@1504r
        -->	[0B,48r:0)[1504r,1520r:4)[2120r,2176r:1)[2488r,2544r:2)[2832r,2848r:3)  0@0B-phi 1@2120r 2@2488r 3@2832r 4@1504r
AllocationOrder(GPR32sponly) = [ ]
AllocationOrder(XSeqPairsClass_with_sube64_in_tcGPR64) = [ %X0_X1 %X1_X2 %X2_X3 %X3_X4 %X4_X5 %X5_X6 %X6_X7 %X7_X8 %X8_X9 %X9_X10 %X10_X11 %X11_X12 %X12_X13 %X13_X14 %X14_X15 %X15_X16 %X16_X17 %X17_X18 %X18_X19 ]
AllocationOrder(QQQQ_with_qsub0_in_FPR128_lo) = [ %Q0_Q1_Q2_Q3 %Q1_Q2_Q3_Q4 %Q2_Q3_Q4_Q5 %Q3_Q4_Q5_Q6 %Q4_Q5_Q6_Q7 %Q5_Q6_Q7_Q8 %Q6_Q7_Q8_Q9 %Q7_Q8_Q9_Q10 %Q8_Q9_Q10_Q11 %Q9_Q10_Q11_Q12 %Q10_Q11_Q12_Q13 %Q11_Q12_Q13_Q14 %Q12_Q13_Q14_Q15 %Q13_Q14_Q15_Q16 %Q14_Q15_Q16_Q17 %Q15_Q16_Q17_Q18 ]
AllocationOrder(FPR8) = [ %B0 %B1 %B2 %B3 %B4 %B5 %B6 %B7 %B16 %B17 %B18 %B19 %B20 %B21 %B22 %B23 %B24 %B25 %B26 %B27 %B28 %B29 %B30 %B31 %B8 %B9 %B10 %B11 %B12 %B13 %B14 %B15 ]
AllocationOrder(GPR32all) = [ %W0 %W1 %W2 %W3 %W4 %W5 %W6 %W7 %W8 %W9 %W10 %W11 %W12 %W13 %W14 %W15 %W16 %W17 %W18 %W19 %W20 %W21 %W22 %W23 %W24 %W25 %W26 %W27 %W28 %W30 ]
handleMove 2048B -> 2072B: %vreg124<def> = LDRXui %vreg125, 9; mem:LD8[%opaque28] GPR64:%vreg124 GPR64common:%vreg125
     %vreg124:	[2048r,2128r:0)  0@2048r
        -->	[2072r,2128r:0)  0@2072r
     %vreg125:	[2032r,2048r:0)  0@2032r
        -->	[2032r,2072r:0)  0@2032r
handleMove 2016B -> 2068B: %vreg127<def> = LDRXui %vreg128, 7; mem:LD8[%bzalloc27] GPR64:%vreg127 GPR64common:%vreg128
     %vreg127:	[2016r,2176r:0)  0@2016r
        -->	[2068r,2176r:0)  0@2068r
     %vreg128:	[2000r,2016r:0)  0@2000r
        -->	[2000r,2068r:0)  0@2000r
handleMove 1776B -> 1960B: %vreg130<def> = MOVi32imm 100000; GPR32:%vreg130
     %vreg130:	[1776r,1968r:0)  0@1776r
        -->	[1960r,1968r:0)  0@1960r
handleMove 3296B -> 3320B: %vreg239<def> = LDRXui %vreg240, 9; mem:LD8[%opaque61] GPR64:%vreg239 GPR64common:%vreg240
     %vreg239:	[3296r,3376r:0)  0@3296r
        -->	[3320r,3376r:0)  0@3320r
     %vreg240:	[3280r,3296r:0)  0@3280r
        -->	[3280r,3320r:0)  0@3280r
handleMove 3264B -> 3316B: %vreg242<def> = LDRXui %vreg243, 8; mem:LD8[%bzfree60] GPR64:%vreg242 GPR64common:%vreg243
     %vreg242:	[3264r,3408r:0)  0@3264r
        -->	[3316r,3408r:0)  0@3316r
     %vreg243:	[3248r,3264r:0)  0@3248r
        -->	[3248r,3316r:0)  0@3248r
handleMove 3616B -> 3640B: %vreg257<def> = LDRXui %vreg258, 9; mem:LD8[%opaque69] GPR64:%vreg257 GPR64common:%vreg258
     %vreg257:	[3616r,3696r:0)  0@3616r
        -->	[3640r,3696r:0)  0@3640r
     %vreg258:	[3600r,3616r:0)  0@3600r
        -->	[3600r,3640r:0)  0@3600r
handleMove 3584B -> 3636B: %vreg260<def> = LDRXui %vreg261, 8; mem:LD8[%bzfree68] GPR64:%vreg260 GPR64common:%vreg261
     %vreg260:	[3584r,3728r:0)  0@3584r
        -->	[3636r,3728r:0)  0@3636r
     %vreg261:	[3568r,3584r:0)  0@3568r
        -->	[3568r,3636r:0)  0@3568r
handleMove 3936B -> 3960B: %vreg275<def> = LDRXui %vreg276, 9; mem:LD8[%opaque77] GPR64:%vreg275 GPR64common:%vreg276
     %vreg275:	[3936r,4016r:0)  0@3936r
        -->	[3960r,4016r:0)  0@3960r
     %vreg276:	[3920r,3936r:0)  0@3920r
        -->	[3920r,3960r:0)  0@3920r
handleMove 3904B -> 3956B: %vreg278<def> = LDRXui %vreg279, 8; mem:LD8[%bzfree76] GPR64:%vreg278 GPR64common:%vreg279
     %vreg278:	[3904r,4048r:0)  0@3904r
        -->	[3956r,4048r:0)  0@3956r
     %vreg279:	[3888r,3904r:0)  0@3888r
        -->	[3888r,3956r:0)  0@3888r
handleMove 4208B -> 4232B: %vreg292<def> = LDRXui %vreg293, 8; mem:LD8[%bzfree83] GPR64:%vreg292 GPR64common:%vreg293
     %vreg292:	[4208r,4336r:0)  0@4208r
        -->	[4232r,4336r:0)  0@4232r
     %vreg293:	[4192r,4208r:0)  0@4192r
        -->	[4192r,4232r:0)  0@4192r
AllocationOrder(GPR32sponly) = [ ]
handleMove 5104B -> 5128B: %vreg175<def> = LDRXui %vreg176, 3; mem:LD8[%arr193] GPR64:%vreg175 GPR64common:%vreg176
     %vreg175:	[5104r,5136r:0)  0@5104r
        -->	[5128r,5136r:0)  0@5128r
     %vreg176:	[5088r,5104r:0)  0@5088r
        -->	[5088r,5128r:0)  0@5088r
handleMove 4992B -> 5032B: %vreg184<def> = LDRXui %vreg187, 3; mem:LD8[%arr192] GPR64:%vreg184 GPR64common:%vreg187
     %vreg184:	[4992r,5040r:0)  0@4992r
        -->	[5032r,5040r:0)  0@5032r
     %vreg187:	[4976r,4992r:0)  0@4976r
        -->	[4976r,5032r:0)  0@4976r
handleMove 4912B -> 4952B: %vreg192<def> = LDRXui %vreg195, 4; mem:LD8[%arr291] GPR64:%vreg192 GPR64common:%vreg195
     %vreg192:	[4912r,4960r:0)  0@4912r
        -->	[4952r,4960r:0)  0@4952r
     %vreg195:	[4896r,4912r:0)  0@4896r
        -->	[4896r,4952r:0)  0@4896r
handleMove 4752B -> 4776B: %vreg208<def> = SUBWri %vreg211, 19, 0; GPR32common:%vreg208,%vreg211
     %vreg208:	[4752r,4784r:0)  0@4752r
        -->	[4776r,4784r:0)  0@4776r
     %vreg211:	[4736r,4752r:0)  0@4736r
        -->	[4736r,4776r:0)  0@4736r
handleMove 4736B -> 4772B: %vreg211<def> = MADDWrrr %vreg209, %vreg212, %WZR; GPR32common:%vreg211 GPR32:%vreg209,%vreg212
     %vreg211:	[4736r,4776r:0)  0@4736r
        -->	[4772r,4776r:0)  0@4772r
     %vreg209:	[4512r,4736r:0)  0@4512r
        -->	[4512r,4772r:0)  0@4512r
     %vreg212:	[4720r,4736r:0)  0@4720r
        -->	[4720r,4772r:0)  0@4720r
     WZR:	[688r,688d:2)[752r,752d:1)[864r,864d:0)  0@864r 1@752r 2@688r
        -->	[688r,688d:2)[752r,752d:1)[864r,864d:0)  0@864r 1@752r 2@688r
handleMove 4512B -> 4776B: %vreg209<def> = MOVi32imm 100000; GPR32:%vreg209
     %vreg209:	[4512r,4784r:0)  0@4512r
        -->	[4776r,4784r:0)  0@4776r
handleMove 4528B -> 4584B: %vreg219<def> = MOVi32imm 2; GPR32:%vreg219
     %vreg219:	[4528r,4624r:0)  0@4528r
        -->	[4584r,4624r:0)  0@4584r
********** GREEDY REGISTER ALLOCATION **********
********** Function: BZ2_bzCompressInit
********** INTERVALS **********
W30 [0B,16r:0)[272r,272d:25)[320e,320d:13)[432r,432d:26)[496e,496d:12)[1520r,1520d:24)[1584e,1584d:11)[2176r,2176d:21)[2256e,2256d:10)[2544r,2544d:22)[2640e,2640d:9)[2848r,2848d:23)[2912e,2912d:8)[3408r,3408d:18)[3456e,3456d:7)[3728r,3728d:17)[3776e,3776d:6)[4048r,4048d:16)[4096e,4096d:5)[4336r,4336d:15)[4384e,4384d:4)[5392r,5392d:19)[5440e,5440d:3)[5520r,5520d:20)[5568e,5568d:2)[5744r,5744d:14)[5792e,5792d:1)  0@0B-phi 1@5792e 2@5568e 3@5440e 4@4384e 5@4096e 6@3776e 7@3456e 8@2912e 9@2640e 10@2256e 11@1584e 12@496e 13@320e 14@5744r 15@4336r 16@4048r 17@3728r 18@3408r 19@5392r 20@5520r 21@2176r 22@2544r 23@2848r 24@1520r 25@272r 26@432r
WZR [688r,688d:2)[752r,752d:1)[864r,864d:0)  0@864r 1@752r 2@688r
W0 [0B,80r:0)[240r,272r:18)[432r,464r:2)[1512r,1520r:17)[1520r,1552r:16)[2128r,2176r:11)[2176r,2208r:10)[2496r,2544r:13)[2544r,2576r:12)[2840r,2848r:15)[2848r,2880r:14)[3376r,3408r:7)[3696r,3728r:6)[4016r,4048r:5)[4304r,4336r:4)[5376r,5392r:8)[5504r,5520r:9)[5712r,5744r:3)[5840r,5856r:1)  0@0B-phi 1@5840r 2@432r 3@5712r 4@4304r 5@4016r 6@3696r 7@3376r 8@5376r 9@5504r 10@2176r 11@2128r 12@2544r 13@2496r 14@2848r 15@2840r 16@1520r 17@1512r 18@240r
W1 [0B,64r:0)[256r,272r:10)[1488r,1520r:4)[2144r,2176r:1)[2512r,2544r:2)[2816r,2848r:3)[3392r,3408r:9)[3712r,3728r:8)[4032r,4048r:7)[4320r,4336r:6)[5728r,5744r:5)  0@0B-phi 1@2144r 2@2512r 3@2816r 4@1488r 5@5728r 6@4320r 7@4032r 8@3712r 9@3392r 10@256r
W2 [0B,48r:0)[1504r,1520r:4)[2120r,2176r:1)[2488r,2544r:2)[2832r,2848r:3)  0@0B-phi 1@2120r 2@2488r 3@2832r 4@1504r
W3 [0B,32r:0)  0@0B-phi
%vreg1 [80r,352r:0)  0@80r
%vreg3 [64r,368r:0)  0@64r
%vreg5 [48r,384r:0)  0@48r
%vreg7 [32r,400r:0)  0@32r
%vreg9 [464r,528r:0)  0@464r
%vreg10 [160r,176r:0)  0@160r
%vreg12 [176r,240r:0)  0@176r
%vreg13 [16r,5728r:0)  0@16r
%vreg15 [560r,576r:0)  0@560r
%vreg17 [624r,640r:0)  0@624r
%vreg19 [672r,688r:0)  0@672r
%vreg21 [736r,752r:0)  0@736r
%vreg23 [800r,816r:0)  0@800r
%vreg25 [848r,864r:0)  0@848r
%vreg27 [976r,992r:0)  0@976r
%vreg28 [1024r,1040r:0)  0@1024r
%vreg31 [1088r,1104r:0)  0@1088r
%vreg32 [1072r,1088r:0)  0@1072r
%vreg33 [1172r,1176r:0)  0@1172r
%vreg34 [1176r,1184r:0)  0@1176r
%vreg36 [1168r,1184r:0)  0@1168r
%vreg39 [1232r,1248r:0)  0@1232r
%vreg40 [1216r,1232r:0)  0@1216r
%vreg41 [1316r,1320r:0)  0@1316r
%vreg42 [1320r,1328r:0)  0@1320r
%vreg44 [1312r,1328r:0)  0@1312r
%vreg46 [1648r,1664r:0)  0@1648r
%vreg49 [1552r,1632r:0)  0@1552r
%vreg56 [1440r,1512r:0)  0@1440r
%vreg57 [1424r,1440r:0)  0@1424r
%vreg59 [1432r,1520r:0)  0@1432r
%vreg60 [1392r,1432r:0)  0@1392r
%vreg63 [3008r,3024r:0)  0@3008r
%vreg64 [2992r,3008r:0)  0@2992r
%vreg67 [2960r,2976r:0)  0@2960r
%vreg69 [2880r,2976r:0)  0@2880r
%vreg76 [2768r,2840r:0)  0@2768r
%vreg77 [2752r,2768r:0)  0@2752r
%vreg79 [2760r,2848r:0)  0@2760r
%vreg80 [2720r,2760r:0)  0@2720r
%vreg83 [2688r,2704r:0)  0@2688r
%vreg85 [2576r,2704r:0)  0@2576r
%vreg94 [2416r,2448r:0)  0@2416r
%vreg95 [2448r,2512r:0)  0@2448r
%vreg98 [2400r,2416r:0)  0@2400r
%vreg100 [2408r,2496r:0)  0@2408r
%vreg101 [2368r,2408r:0)  0@2368r
%vreg103 [2404r,2544r:0)  0@2404r
%vreg104 [2336r,2404r:0)  0@2336r
%vreg107 [2304r,2320r:0)  0@2304r
%vreg109 [2208r,2320r:0)  0@2208r
%vreg118 [2080r,2144r:0)  0@2080r
%vreg122 [2064r,2080r:0)  0@2064r
%vreg124 [2072r,2128r:0)  0@2072r
%vreg125 [2032r,2072r:0)  0@2032r
%vreg127 [2068r,2176r:0)  0@2068r
%vreg128 [2000r,2068r:0)  0@2000r
%vreg130 [1960r,1968r:0)  0@1960r
%vreg132 [1968r,1984r:0)  0@1968r
%vreg133 [1952r,1968r:0)  0@1952r
%vreg136 [1920r,1936r:0)  0@1920r
%vreg138 [1888r,1904r:0)  0@1888r
%vreg140 [1856r,1872r:0)  0@1856r
%vreg143 [1824r,1840r:0)  0@1824r
%vreg144 [1808r,1840r:0)  0@1808r
%vreg147 [3072r,3088r:0)  0@3072r
%vreg148 [3056r,3072r:0)  0@3056r
%vreg151 [3136r,3152r:0)  0@3136r
%vreg152 [3120r,3136r:0)  0@3120r
%vreg154 [5472r,5504r:0)  0@5472r
%vreg156 [5344r,5376r:0)  0@5344r
%vreg158 [5312r,5328r:0)  0@5312r
%vreg160 [5280r,5296r:0)  0@5280r
%vreg162 [5248r,5264r:0)  0@5248r
%vreg164 [5216r,5232r:0)  0@5216r
%vreg167 [5184r,5200r:0)  0@5184r
%vreg169 [5152r,5200r:0)  0@5152r
%vreg173 [5120r,5136r:0)  0@5120r
%vreg175 [5128r,5136r:0)  0@5128r
%vreg176 [5088r,5128r:0)  0@5088r
%vreg179 [5056r,5072r:0)  0@5056r
%vreg182 [5024r,5040r:0)  0@5024r
%vreg184 [5032r,5040r:0)  0@5032r
%vreg187 [4976r,5032r:0)  0@4976r
%vreg190 [4944r,4960r:0)  0@4944r
%vreg192 [4952r,4960r:0)  0@4952r
%vreg195 [4896r,4952r:0)  0@4896r
%vreg198 [4864r,4880r:0)  0@4864r
%vreg199 [4848r,4880r:0)  0@4848r
%vreg202 [4816r,4832r:0)  0@4816r
%vreg203 [4808r,4832r:0)  0@4808r
%vreg206 [4768r,4800r:0)  0@4768r
%vreg208 [4792r,4800r:0)  0@4792r
%vreg209 [4776r,4784r:0)  0@4776r
%vreg211 [4784r,4792r:0)  0@4784r
%vreg212 [4720r,4784r:0)  0@4720r
%vreg215 [4688r,4704r:0)  0@4688r
%vreg216 [4672r,4704r:0)  0@4672r
%vreg218 [4640r,4656r:0)  0@4640r
%vreg219 [4584r,4624r:0)  0@4584r
%vreg221 [4608r,4624r:0)  0@4608r
%vreg223 [4576r,4592r:0)  0@4576r
%vreg225 [4544r,4560r:0)  0@4544r
%vreg228 [3200r,3216r:0)  0@3200r
%vreg229 [3184r,3200r:0)  0@3184r
%vreg234 [3328r,3392r:0)  0@3328r
%vreg237 [3312r,3328r:0)  0@3312r
%vreg239 [3320r,3376r:0)  0@3320r
%vreg240 [3280r,3320r:0)  0@3280r
%vreg242 [3316r,3408r:0)  0@3316r
%vreg243 [3248r,3316r:0)  0@3248r
%vreg246 [3520r,3536r:0)  0@3520r
%vreg247 [3504r,3520r:0)  0@3504r
%vreg252 [3648r,3712r:0)  0@3648r
%vreg255 [3632r,3648r:0)  0@3632r
%vreg257 [3640r,3696r:0)  0@3640r
%vreg258 [3600r,3640r:0)  0@3600r
%vreg260 [3636r,3728r:0)  0@3636r
%vreg261 [3568r,3636r:0)  0@3568r
%vreg264 [3840r,3856r:0)  0@3840r
%vreg265 [3824r,3840r:0)  0@3824r
%vreg270 [3968r,4032r:0)  0@3968r
%vreg273 [3952r,3968r:0)  0@3952r
%vreg275 [3960r,4016r:0)  0@3960r
%vreg276 [3920r,3960r:0)  0@3920r
%vreg278 [3956r,4048r:0)  0@3956r
%vreg279 [3888r,3956r:0)  0@3888r
%vreg281 [4144r,4160r:0)  0@4144r
%vreg286 [4256r,4320r:0)  0@4256r
%vreg289 [4240r,4304r:0)  0@4240r
%vreg290 [4224r,4240r:0)  0@4224r
%vreg292 [4232r,4336r:0)  0@4232r
%vreg293 [4192r,4232r:0)  0@4192r
%vreg294 [4432r,4448r:0)  0@4432r
%vreg295 [1696r,1712r:0)  0@1696r
%vreg296 [912r,928r:0)  0@912r
%vreg298 [5824r,5840r:0)  0@5824r
%vreg299 [5632r,5648r:0)  0@5632r
%vreg301 [5648r,5712r:0)  0@5648r
RegMasks: 272r 432r 1520r 2176r 2544r 2848r 3408r 3728r 4048r 4336r 5392r 5520r 5744r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzCompressInit: Post SSA
Frame Objects:
  fi#0: size=4, align=4, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=4, align=4, at location [SP]
  fi#3: size=4, align=4, at location [SP]
  fi#4: size=4, align=4, at location [SP]
  fi#5: size=4, align=4, at location [SP]
  fi#6: size=8, align=8, at location [SP]
Function Live Ins: %X0 in %vreg0, %W1 in %vreg2, %W2 in %vreg4, %W3 in %vreg6, %LR in %vreg14

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %W1 %W2 %W3 %LR
16B		%vreg13<def> = COPY %LR; GPR64:%vreg13
32B		%vreg7<def> = COPY %W3; GPR32:%vreg7
48B		%vreg5<def> = COPY %W2; GPR32:%vreg5
64B		%vreg3<def> = COPY %W1; GPR32:%vreg3
80B		%vreg1<def> = COPY %X0; GPR64:%vreg1
160B		%vreg10<def> = ADRP <ga:@BZ2_bzCompressInit>[TF=1]; GPR64common:%vreg10
176B		%vreg12<def> = ADDXri %vreg10, <ga:@BZ2_bzCompressInit>[TF=34], 0; GPR64sp:%vreg12 GPR64common:%vreg10
224B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
240B		%X0<def> = COPY %vreg12; GPR64sp:%vreg12
256B		%X1<def> = COPY %vreg13; GPR64:%vreg13
272B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
288B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
304B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
320B		STACKMAP 0, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, %vreg1, 0, <fi#1>, 0, %vreg5, 0, <fi#3>, 0, %vreg7, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4) GPR32:%vreg3,%vreg5,%vreg7 GPR64:%vreg1
336B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
352B		STRXui %vreg1, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg1
368B		STRWui %vreg3, <fi#2>, 0; mem:ST4[FixedStack2] GPR32:%vreg3
384B		STRWui %vreg5, <fi#3>, 0; mem:ST4[FixedStack3] GPR32:%vreg5
400B		STRWui %vreg7, <fi#4>, 0; mem:ST4[FixedStack4] GPR32:%vreg7
416B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
432B		BL <ga:@bz_config_ok>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-def>
448B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
464B		%vreg9<def> = COPY %W0; GPR32:%vreg9
480B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
496B		STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)
512B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
528B		CBNZW %vreg9, <BB#2>; GPR32:%vreg9
	    Successors according to CFG: BB#2 BB#1

544B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
560B		%vreg15<def> = MOVi32imm 4294967287; GPR32:%vreg15
576B		STRWui %vreg15, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg15
592B		B <BB#29>
	    Successors according to CFG: BB#29

608B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0
624B		%vreg17<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg17
640B		CBZX %vreg17, <BB#7>; GPR64:%vreg17
	    Successors according to CFG: BB#7 BB#3

656B	BB#3: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#2
672B		%vreg19<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32common:%vreg19
688B		%WZR<def> = SUBSWri %vreg19, 1, 0, %NZCV<imp-def>; GPR32common:%vreg19
704B		Bcc 11, <BB#7>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#7 BB#4

720B	BB#4: derived from LLVM BB %lor.lhs.false.2
	    Predecessors according to CFG: BB#3
736B		%vreg21<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32common:%vreg21
752B		%WZR<def> = SUBSWri %vreg21, 9, 0, %NZCV<imp-def>; GPR32common:%vreg21
768B		Bcc 12, <BB#7>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#7 BB#5

784B	BB#5: derived from LLVM BB %lor.lhs.false.4
	    Predecessors according to CFG: BB#4
800B		%vreg23<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg23
816B		TBNZW %vreg23, 31, <BB#7>; GPR32:%vreg23
	    Successors according to CFG: BB#7 BB#6

832B	BB#6: derived from LLVM BB %lor.lhs.false.6
	    Predecessors according to CFG: BB#5
848B		%vreg25<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32common:%vreg25
864B		%WZR<def> = SUBSWri %vreg25, 250, 0, %NZCV<imp-def>; GPR32common:%vreg25
880B		Bcc 13, <BB#8>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#8 BB#7

896B	BB#7: derived from LLVM BB %if.then.8
	    Predecessors according to CFG: BB#2 BB#3 BB#4 BB#5 BB#6
912B		%vreg296<def> = MOVi32imm 4294967294; GPR32:%vreg296
928B		STRWui %vreg296, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg296
944B		B <BB#29>
	    Successors according to CFG: BB#29

960B	BB#8: derived from LLVM BB %if.end.9
	    Predecessors according to CFG: BB#6
976B		%vreg27<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg27
992B		CBNZW %vreg27, <BB#10>; GPR32:%vreg27
	    Successors according to CFG: BB#10 BB#9

1008B	BB#9: derived from LLVM BB %if.then.11
	    Predecessors according to CFG: BB#8
1024B		%vreg28<def> = MOVi32imm 30; GPR32:%vreg28
1040B		STRWui %vreg28, <fi#4>, 0; mem:ST4[FixedStack4] GPR32:%vreg28
	    Successors according to CFG: BB#10

1056B	BB#10: derived from LLVM BB %if.end.12
	    Predecessors according to CFG: BB#8 BB#9
1072B		%vreg32<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg32
1088B		%vreg31<def> = LDRXui %vreg32, 7; mem:LD8[%bzalloc] GPR64:%vreg31 GPR64common:%vreg32
1104B		CBNZX %vreg31, <BB#12>; GPR64:%vreg31
	    Successors according to CFG: BB#12 BB#11

1120B	BB#11: derived from LLVM BB %if.then.14
	    Predecessors according to CFG: BB#10
1168B		%vreg36<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg36
1172B		%vreg33<def> = ADRP <ga:@default_bzalloc>[TF=1]; GPR64common:%vreg33
1176B		%vreg34<def> = ADDXri %vreg33, <ga:@default_bzalloc>[TF=34], 0; GPR64common:%vreg34,%vreg33
1184B		STRXui %vreg34, %vreg36, 7; mem:ST8[%bzalloc15] GPR64common:%vreg34,%vreg36
	    Successors according to CFG: BB#12

1200B	BB#12: derived from LLVM BB %if.end.16
	    Predecessors according to CFG: BB#10 BB#11
1216B		%vreg40<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg40
1232B		%vreg39<def> = LDRXui %vreg40, 8; mem:LD8[%bzfree] GPR64:%vreg39 GPR64common:%vreg40
1248B		CBNZX %vreg39, <BB#14>; GPR64:%vreg39
	    Successors according to CFG: BB#14 BB#13

1264B	BB#13: derived from LLVM BB %if.then.18
	    Predecessors according to CFG: BB#12
1312B		%vreg44<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg44
1316B		%vreg41<def> = ADRP <ga:@default_bzfree>[TF=1]; GPR64common:%vreg41
1320B		%vreg42<def> = ADDXri %vreg41, <ga:@default_bzfree>[TF=34], 0; GPR64common:%vreg42,%vreg41
1328B		STRXui %vreg42, %vreg44, 8; mem:ST8[%bzfree19] GPR64common:%vreg42,%vreg44
	    Successors according to CFG: BB#14

1344B	BB#14: derived from LLVM BB %if.end.20
	    Predecessors according to CFG: BB#12 BB#13
1392B		%vreg60<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg60
1424B		%vreg57<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg57
1432B		%vreg59<def> = LDRXui %vreg60, 7; mem:LD8[%bzalloc21] GPR64:%vreg59 GPR64common:%vreg60
1440B		%vreg56<def> = LDRXui %vreg57, 9; mem:LD8[%opaque] GPR64:%vreg56 GPR64common:%vreg57
1456B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1488B		%W1<def> = MOVi32imm 55768
1504B		%W2<def> = MOVi32imm 1
1512B		%X0<def> = COPY %vreg56; GPR64:%vreg56
1520B		BLR %vreg59, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %W2<imp-use>, %X0<imp-def>; GPR64:%vreg59
1536B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1552B		%vreg49<def> = COPY %X0; GPR64:%vreg49
1568B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1584B		STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)
1600B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1632B		STRXui %vreg49, <fi#6>, 0; mem:ST8[FixedStack6] GPR64:%vreg49
1648B		%vreg46<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64:%vreg46
1664B		CBNZX %vreg46, <BB#16>; GPR64:%vreg46
	    Successors according to CFG: BB#16 BB#15

1680B	BB#15: derived from LLVM BB %if.then.24
	    Predecessors according to CFG: BB#14
1696B		%vreg295<def> = MOVi32imm 4294967293; GPR32:%vreg295
1712B		STRWui %vreg295, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg295
1728B		B <BB#29>
	    Successors according to CFG: BB#29

1744B	BB#16: derived from LLVM BB %if.end.25
	    Predecessors according to CFG: BB#14
1808B		%vreg144<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg144
1824B		%vreg143<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg143
1840B		STRXui %vreg144, %vreg143, 0; mem:ST8[%strm26] GPR64:%vreg144 GPR64common:%vreg143
1856B		%vreg140<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg140
1872B		STRXui %XZR, %vreg140, 3; mem:ST8[%arr1] GPR64common:%vreg140
1888B		%vreg138<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg138
1904B		STRXui %XZR, %vreg138, 4; mem:ST8[%arr2] GPR64common:%vreg138
1920B		%vreg136<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg136
1936B		STRXui %XZR, %vreg136, 5; mem:ST8[%ftab] GPR64common:%vreg136
1952B		%vreg133<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg133
1960B		%vreg130<def> = MOVi32imm 100000; GPR32:%vreg130
1968B		%vreg132<def> = MADDWrrr %vreg130, %vreg133, %WZR; GPR32:%vreg132,%vreg130,%vreg133
1984B		STRWui %vreg132, <fi#5>, 0; mem:ST4[FixedStack5] GPR32:%vreg132
2000B		%vreg128<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg128
2032B		%vreg125<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg125
2064B		%vreg122<def> = LDRSWui <fi#5>, 0; mem:LD4[FixedStack5] GPR64:%vreg122
2068B		%vreg127<def> = LDRXui %vreg128, 7; mem:LD8[%bzalloc27] GPR64:%vreg127 GPR64common:%vreg128
2072B		%vreg124<def> = LDRXui %vreg125, 9; mem:LD8[%opaque28] GPR64:%vreg124 GPR64common:%vreg125
2080B		%vreg118<def> = UBFMXri %vreg122, 62, 61; GPR64:%vreg118,%vreg122
2112B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2120B		%W2<def> = MOVi32imm 1
2128B		%X0<def> = COPY %vreg124; GPR64:%vreg124
2144B		%W1<def> = COPY %vreg118:sub_32; GPR64:%vreg118
2176B		BLR %vreg127, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %W2<imp-use>, %X0<imp-def>; GPR64:%vreg127
2192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2208B		%vreg109<def> = COPY %X0; GPR64:%vreg109
2240B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2256B		STACKMAP 3, 0, 0, <fi#2>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)
2272B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2304B		%vreg107<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg107
2320B		STRXui %vreg109, %vreg107, 3; mem:ST8[%arr132] GPR64:%vreg109 GPR64common:%vreg107
2336B		%vreg104<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg104
2368B		%vreg101<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg101
2400B		%vreg98<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32common:%vreg98
2404B		%vreg103<def> = LDRXui %vreg104, 7; mem:LD8[%bzalloc33] GPR64:%vreg103 GPR64common:%vreg104
2408B		%vreg100<def> = LDRXui %vreg101, 9; mem:LD8[%opaque34] GPR64:%vreg100 GPR64common:%vreg101
2416B		%vreg94:sub_32<def,read-undef> = ADDWri %vreg98, 34, 0; GPR64common:%vreg94 GPR32common:%vreg98
2448B		%vreg95<def> = SBFMXri %vreg94, 62, 31; GPR64:%vreg95 GPR64common:%vreg94
2480B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2488B		%W2<def> = MOVi32imm 1
2496B		%X0<def> = COPY %vreg100; GPR64:%vreg100
2512B		%W1<def> = COPY %vreg95:sub_32; GPR64:%vreg95
2544B		BLR %vreg103, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %W2<imp-use>, %X0<imp-def>; GPR64:%vreg103
2560B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2576B		%vreg85<def> = COPY %X0; GPR64:%vreg85
2624B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2640B		STACKMAP 4, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)
2656B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2688B		%vreg83<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg83
2704B		STRXui %vreg85, %vreg83, 4; mem:ST8[%arr239] GPR64:%vreg85 GPR64common:%vreg83
2720B		%vreg80<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg80
2752B		%vreg77<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg77
2760B		%vreg79<def> = LDRXui %vreg80, 7; mem:LD8[%bzalloc40] GPR64:%vreg79 GPR64common:%vreg80
2768B		%vreg76<def> = LDRXui %vreg77, 9; mem:LD8[%opaque41] GPR64:%vreg76 GPR64common:%vreg77
2784B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2816B		%W1<def> = MOVi32imm 262148
2832B		%W2<def> = MOVi32imm 1
2840B		%X0<def> = COPY %vreg76; GPR64:%vreg76
2848B		BLR %vreg79, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %W2<imp-use>, %X0<imp-def>; GPR64:%vreg79
2864B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2880B		%vreg69<def> = COPY %X0; GPR64:%vreg69
2896B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2912B		STACKMAP 5, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)
2928B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2960B		%vreg67<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg67
2976B		STRXui %vreg69, %vreg67, 5; mem:ST8[%ftab43] GPR64:%vreg69 GPR64common:%vreg67
2992B		%vreg64<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg64
3008B		%vreg63<def> = LDRXui %vreg64, 3; mem:LD8[%arr144] GPR64:%vreg63 GPR64common:%vreg64
3024B		CBZX %vreg63, <BB#19>; GPR64:%vreg63
	    Successors according to CFG: BB#19 BB#17

3040B	BB#17: derived from LLVM BB %lor.lhs.false.47
	    Predecessors according to CFG: BB#16
3056B		%vreg148<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg148
3072B		%vreg147<def> = LDRXui %vreg148, 4; mem:LD8[%arr248] GPR64:%vreg147 GPR64common:%vreg148
3088B		CBZX %vreg147, <BB#19>; GPR64:%vreg147
	    Successors according to CFG: BB#19 BB#18

3104B	BB#18: derived from LLVM BB %lor.lhs.false.51
	    Predecessors according to CFG: BB#17
3120B		%vreg152<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg152
3136B		%vreg151<def> = LDRXui %vreg152, 5; mem:LD8[%ftab52] GPR64:%vreg151 GPR64common:%vreg152
3152B		CBNZX %vreg151, <BB#28>; GPR64:%vreg151
	    Successors according to CFG: BB#28 BB#19

3168B	BB#19: derived from LLVM BB %if.then.55
	    Predecessors according to CFG: BB#16 BB#17 BB#18
3184B		%vreg229<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg229
3200B		%vreg228<def> = LDRXui %vreg229, 3; mem:LD8[%arr156] GPR64:%vreg228 GPR64common:%vreg229
3216B		CBZX %vreg228, <BB#21>; GPR64:%vreg228
	    Successors according to CFG: BB#21 BB#20

3232B	BB#20: derived from LLVM BB %if.then.59
	    Predecessors according to CFG: BB#19
3248B		%vreg243<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg243
3280B		%vreg240<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg240
3312B		%vreg237<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg237
3316B		%vreg242<def> = LDRXui %vreg243, 8; mem:LD8[%bzfree60] GPR64:%vreg242 GPR64common:%vreg243
3320B		%vreg239<def> = LDRXui %vreg240, 9; mem:LD8[%opaque61] GPR64:%vreg239 GPR64common:%vreg240
3328B		%vreg234<def> = LDRXui %vreg237, 3; mem:LD8[%arr162] GPR64:%vreg234 GPR64common:%vreg237
3360B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3376B		%X0<def> = COPY %vreg239; GPR64:%vreg239
3392B		%X1<def> = COPY %vreg234; GPR64:%vreg234
3408B		BLR %vreg242, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>; GPR64:%vreg242
3424B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3440B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3456B		STACKMAP 6, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1]
3472B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#21

3488B	BB#21: derived from LLVM BB %if.end.63
	    Predecessors according to CFG: BB#19 BB#20
3504B		%vreg247<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg247
3520B		%vreg246<def> = LDRXui %vreg247, 4; mem:LD8[%arr264] GPR64:%vreg246 GPR64common:%vreg247
3536B		CBZX %vreg246, <BB#23>; GPR64:%vreg246
	    Successors according to CFG: BB#23 BB#22

3552B	BB#22: derived from LLVM BB %if.then.67
	    Predecessors according to CFG: BB#21
3568B		%vreg261<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg261
3600B		%vreg258<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg258
3632B		%vreg255<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg255
3636B		%vreg260<def> = LDRXui %vreg261, 8; mem:LD8[%bzfree68] GPR64:%vreg260 GPR64common:%vreg261
3640B		%vreg257<def> = LDRXui %vreg258, 9; mem:LD8[%opaque69] GPR64:%vreg257 GPR64common:%vreg258
3648B		%vreg252<def> = LDRXui %vreg255, 4; mem:LD8[%arr270] GPR64:%vreg252 GPR64common:%vreg255
3680B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3696B		%X0<def> = COPY %vreg257; GPR64:%vreg257
3712B		%X1<def> = COPY %vreg252; GPR64:%vreg252
3728B		BLR %vreg260, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>; GPR64:%vreg260
3744B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3760B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3776B		STACKMAP 7, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1]
3792B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#23

3808B	BB#23: derived from LLVM BB %if.end.71
	    Predecessors according to CFG: BB#21 BB#22
3824B		%vreg265<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg265
3840B		%vreg264<def> = LDRXui %vreg265, 5; mem:LD8[%ftab72] GPR64:%vreg264 GPR64common:%vreg265
3856B		CBZX %vreg264, <BB#25>; GPR64:%vreg264
	    Successors according to CFG: BB#25 BB#24

3872B	BB#24: derived from LLVM BB %if.then.75
	    Predecessors according to CFG: BB#23
3888B		%vreg279<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg279
3920B		%vreg276<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg276
3952B		%vreg273<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg273
3956B		%vreg278<def> = LDRXui %vreg279, 8; mem:LD8[%bzfree76] GPR64:%vreg278 GPR64common:%vreg279
3960B		%vreg275<def> = LDRXui %vreg276, 9; mem:LD8[%opaque77] GPR64:%vreg275 GPR64common:%vreg276
3968B		%vreg270<def> = LDRXui %vreg273, 5; mem:LD8[%ftab78] GPR64:%vreg270 GPR64common:%vreg273
4000B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4016B		%X0<def> = COPY %vreg275; GPR64:%vreg275
4032B		%X1<def> = COPY %vreg270; GPR64:%vreg270
4048B		BLR %vreg278, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>; GPR64:%vreg278
4064B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4080B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4096B		STACKMAP 8, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1]
4112B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#25

4128B	BB#25: derived from LLVM BB %if.end.79
	    Predecessors according to CFG: BB#23 BB#24
4144B		%vreg281<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64:%vreg281
4160B		CBZX %vreg281, <BB#27>; GPR64:%vreg281
	    Successors according to CFG: BB#27 BB#26

4176B	BB#26: derived from LLVM BB %if.then.82
	    Predecessors according to CFG: BB#25
4192B		%vreg293<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg293
4224B		%vreg290<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg290
4232B		%vreg292<def> = LDRXui %vreg293, 8; mem:LD8[%bzfree83] GPR64:%vreg292 GPR64common:%vreg293
4240B		%vreg289<def> = LDRXui %vreg290, 9; mem:LD8[%opaque84] GPR64:%vreg289 GPR64common:%vreg290
4256B		%vreg286<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64:%vreg286
4288B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4304B		%X0<def> = COPY %vreg289; GPR64:%vreg289
4320B		%X1<def> = COPY %vreg286; GPR64:%vreg286
4336B		BLR %vreg292, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>; GPR64:%vreg292
4352B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4368B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4384B		STACKMAP 9, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
4400B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#27

4416B	BB#27: derived from LLVM BB %if.end.85
	    Predecessors according to CFG: BB#25 BB#26
4432B		%vreg294<def> = MOVi32imm 4294967293; GPR32:%vreg294
4448B		STRWui %vreg294, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg294
4464B		B <BB#29>
	    Successors according to CFG: BB#29

4480B	BB#28: derived from LLVM BB %if.end.86
	    Predecessors according to CFG: BB#18
4544B		%vreg225<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg225
4560B		STRWui %WZR, %vreg225, 165; mem:ST4[%blockNo] GPR64common:%vreg225
4576B		%vreg223<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg223
4584B		%vreg219<def> = MOVi32imm 2; GPR32:%vreg219
4592B		STRWui %vreg219, %vreg223, 3; mem:ST4[%state] GPR32:%vreg219 GPR64common:%vreg223
4608B		%vreg221<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg221
4624B		STRWui %vreg219, %vreg221, 2; mem:ST4[%mode] GPR32:%vreg219 GPR64common:%vreg221
4640B		%vreg218<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg218
4656B		STRWui %WZR, %vreg218, 163; mem:ST4[%combinedCRC] GPR64common:%vreg218
4672B		%vreg216<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg216
4688B		%vreg215<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg215
4704B		STRWui %vreg216, %vreg215, 166; mem:ST4[%blockSize100k87] GPR32:%vreg216 GPR64common:%vreg215
4720B		%vreg212<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg212
4768B		%vreg206<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg206
4776B		%vreg209<def> = MOVi32imm 100000; GPR32:%vreg209
4784B		%vreg211<def> = MADDWrrr %vreg209, %vreg212, %WZR; GPR32common:%vreg211 GPR32:%vreg209,%vreg212
4792B		%vreg208<def> = SUBWri %vreg211, 19, 0; GPR32common:%vreg208,%vreg211
4800B		STRWui %vreg208, %vreg206, 28; mem:ST4[%nblockMAX] GPR32common:%vreg208 GPR64common:%vreg206
4808B		%vreg203<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg203
4816B		%vreg202<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg202
4832B		STRWui %vreg203, %vreg202, 164; mem:ST4[%verbosity89] GPR32:%vreg203 GPR64common:%vreg202
4848B		%vreg199<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg199
4864B		%vreg198<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg198
4880B		STRWui %vreg199, %vreg198, 22; mem:ST4[%workFactor90] GPR32:%vreg199 GPR64common:%vreg198
4896B		%vreg195<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg195
4944B		%vreg190<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg190
4952B		%vreg192<def> = LDRXui %vreg195, 4; mem:LD8[%arr291] GPR64:%vreg192 GPR64common:%vreg195
4960B		STRXui %vreg192, %vreg190, 8; mem:ST8[%block] GPR64:%vreg192 GPR64common:%vreg190
4976B		%vreg187<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg187
5024B		%vreg182<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg182
5032B		%vreg184<def> = LDRXui %vreg187, 3; mem:LD8[%arr192] GPR64:%vreg184 GPR64common:%vreg187
5040B		STRXui %vreg184, %vreg182, 9; mem:ST8[%mtfv] GPR64:%vreg184 GPR64common:%vreg182
5056B		%vreg179<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg179
5072B		STRXui %XZR, %vreg179, 10; mem:ST8[%zbits] GPR64common:%vreg179
5088B		%vreg176<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg176
5120B		%vreg173<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg173
5128B		%vreg175<def> = LDRXui %vreg176, 3; mem:LD8[%arr193] GPR64:%vreg175 GPR64common:%vreg176
5136B		STRXui %vreg175, %vreg173, 7; mem:ST8[%ptr] GPR64:%vreg175 GPR64common:%vreg173
5152B		%vreg169<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64:%vreg169
5184B		%vreg167<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg167
5200B		STRXui %vreg169, %vreg167, 6; mem:ST8[%state94] GPR64:%vreg169 GPR64common:%vreg167
5216B		%vreg164<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg164
5232B		STRWui %WZR, %vreg164, 3; mem:ST4[%total_in_lo32] GPR64common:%vreg164
5248B		%vreg162<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg162
5264B		STRWui %WZR, %vreg162, 4; mem:ST4[%total_in_hi32] GPR64common:%vreg162
5280B		%vreg160<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg160
5296B		STRWui %WZR, %vreg160, 9; mem:ST4[%total_out_lo32] GPR64common:%vreg160
5312B		%vreg158<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg158
5328B		STRWui %WZR, %vreg158, 10; mem:ST4[%total_out_hi32] GPR64common:%vreg158
5344B		%vreg156<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64:%vreg156
5360B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5376B		%X0<def> = COPY %vreg156; GPR64:%vreg156
5392B		BL <ga:@init_RL>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>
5408B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5424B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5440B		STACKMAP 10, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack6]
5456B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5472B		%vreg154<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64:%vreg154
5488B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5504B		%X0<def> = COPY %vreg154; GPR64:%vreg154
5520B		BL <ga:@prepare_new_block>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>
5536B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5552B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5568B		STACKMAP 11, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
5584B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5600B		STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
	    Successors according to CFG: BB#29

5616B	BB#29: derived from LLVM BB %return
	    Predecessors according to CFG: BB#1 BB#28 BB#27 BB#15 BB#7
5632B		%vreg299<def> = ADRP <ga:@BZ2_bzCompressInit>[TF=1]; GPR64common:%vreg299
5648B		%vreg301<def> = ADDXri %vreg299, <ga:@BZ2_bzCompressInit>[TF=34], 0; GPR64sp:%vreg301 GPR64common:%vreg299
5696B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5712B		%X0<def> = COPY %vreg301; GPR64sp:%vreg301
5728B		%X1<def> = COPY %vreg13; GPR64:%vreg13
5744B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
5760B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5776B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5792B		STACKMAP 12, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
5808B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5824B		%vreg298<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0] GPR32:%vreg298
5840B		%W0<def> = COPY %vreg298; GPR32:%vreg298
5856B		RET_ReallyLR %W0<imp-use>

# End machine code for function BZ2_bzCompressInit.


selectOrSplit GPR64:%vreg13 [16r,5728r:0)  0@16r w=4.957461e-04
hints: %X1
missed hint %X1
Analyze counted 3 instrs in 2 blocks, through 28 blocks.
%X1	static = 1.0 worse than no bundles
%X8	static = 1.0 worse than no bundles
%X9	static = 1.0 worse than no bundles
%X10	static = 1.0 worse than no bundles
%X11	static = 1.0 worse than no bundles
%X12	static = 1.0 worse than no bundles
%X13	static = 1.0 worse than no bundles
%X14	static = 1.0 worse than no bundles
%X15	static = 1.0 worse than no bundles
%X16	static = 1.0 worse than no bundles
%X17	static = 1.0 worse than no bundles
%X18	static = 1.0 worse than no bundles
%X0	no positive bundles
%X2	static = 1.0 worse than no bundles
%X3	static = 1.0 worse than no bundles
%X4	static = 1.0 worse than no bundles
%X5	static = 1.0 worse than no bundles
%X6	static = 1.0 worse than no bundles
%X7	static = 1.0 worse than no bundles
assigning %vreg13 to %X19: W19 [16r,5728r:0)  0@16r

selectOrSplit GPR32:%vreg7 [32r,400r:0)  0@32r w=3.945312e-03
hints: %W3
missed hint %W3
Analyze counted 3 instrs in 1 blocks, through 0 blocks.
%W3	no positive bundles
%W8	no positive bundles
%W9	no positive bundles
%W10	no positive bundles
%W11	no positive bundles
%W12	no positive bundles
%W13	no positive bundles
%W14	no positive bundles
%W15	no positive bundles
%W16	no positive bundles
%W17	no positive bundles
%W18	no positive bundles
%W0	no positive bundles
%W1	no positive bundles
%W2	no positive bundles
%W4	no positive bundles
%W5	no positive bundles
%W6	no positive bundles
%W7	no positive bundles
%W19	no positive bundles
assigning %vreg7 to %W20: W20 [32r,400r:0)  0@32r

selectOrSplit GPR32:%vreg5 [48r,384r:0)  0@48r w=4.116848e-03
hints: %W2
missed hint %W2
Analyze counted 3 instrs in 1 blocks, through 0 blocks.
%W2	no positive bundles
%W8	no positive bundles
%W9	no positive bundles
%W10	no positive bundles
%W11	no positive bundles
%W12	no positive bundles
%W13	no positive bundles
%W14	no positive bundles
%W15	no positive bundles
%W16	no positive bundles
%W17	no positive bundles
%W18	no positive bundles
%W0	no positive bundles
%W1	no positive bundles
%W3	no positive bundles
%W4	no positive bundles
%W5	no positive bundles
%W6	no positive bundles
%W7	no positive bundles
%W19	no positive bundles
%W20	no positive bundles
assigning %vreg5 to %W21: W21 [48r,384r:0)  0@48r

selectOrSplit GPR32:%vreg3 [64r,368r:0)  0@64r w=4.303977e-03
hints: %W1
missed hint %W1
Analyze counted 3 instrs in 1 blocks, through 0 blocks.
%W1	no positive bundles
%W8	no positive bundles
%W9	no positive bundles
%W10	no positive bundles
%W11	no positive bundles
%W12	no positive bundles
%W13	no positive bundles
%W14	no positive bundles
%W15	no positive bundles
%W16	no positive bundles
%W17	no positive bundles
%W18	no positive bundles
%W0	no positive bundles
%W2	no positive bundles
%W3	no positive bundles
%W4	no positive bundles
%W5	no positive bundles
%W6	no positive bundles
%W7	no positive bundles
%W19	no positive bundles
%W20	no positive bundles
%W21	no positive bundles
assigning %vreg3 to %W22: W22 [64r,368r:0)  0@64r

selectOrSplit GPR64:%vreg1 [80r,352r:0)  0@80r w=4.508928e-03
hints: %X0
missed hint %X0
Analyze counted 3 instrs in 1 blocks, through 0 blocks.
%X0	no positive bundles
%X8	no positive bundles
%X9	no positive bundles
%X10	no positive bundles
%X11	no positive bundles
%X12	no positive bundles
%X13	no positive bundles
%X14	no positive bundles
%X15	no positive bundles
%X16	no positive bundles
%X17	no positive bundles
%X18	no positive bundles
%X1	no positive bundles
%X2	no positive bundles
%X3	no positive bundles
%X4	no positive bundles
%X5	no positive bundles
%X6	no positive bundles
%X7	no positive bundles
%X19	no positive bundles
%X20	no positive bundles
%X21	no positive bundles
%X22	no positive bundles
assigning %vreg1 to %X23: W23 [80r,352r:0)  0@80r

selectOrSplit GPR64sp:%vreg12 [176r,240r:0)  0@176r w=4.353448e-03
hints: %X0
assigning %vreg12 to %X0: W0 [176r,240r:0)  0@176r

selectOrSplit GPR32:%vreg9 [464r,528r:0)  0@464r w=4.353448e-03
hints: %W0
assigning %vreg9 to %W0: W0 [464r,528r:0)  0@464r

selectOrSplit GPR64:%vreg56 [1440r,1512r:0)  0@1440r w=6.635539e-05
hints: %X0
assigning %vreg56 to %X0: W0 [1440r,1512r:0)  0@1440r

selectOrSplit GPR64:%vreg49 [1552r,1632r:0)  0@1552r w=6.524946e-05
hints: %X0
assigning %vreg49 to %X0: W0 [1552r,1632r:0)  0@1552r

selectOrSplit GPR64:%vreg124 [2072r,2128r:0)  0@2072r w=3.407141e-05
hints: %X0
assigning %vreg124 to %X0: W0 [2072r,2128r:0)  0@2072r

selectOrSplit GPR64:%vreg118 [2080r,2144r:0)  0@2080r w=3.348398e-05
hints: %X1
assigning %vreg118 to %X1: W1 [2080r,2144r:0)  0@2080r

selectOrSplit GPR64:%vreg109 [2208r,2320r:0)  0@2208r w=3.034485e-05
hints: %X0
assigning %vreg109 to %X0: W0 [2208r,2320r:0)  0@2208r

selectOrSplit GPR64:%vreg100 [2408r,2496r:0)  0@2408r w=3.183722e-05
hints: %X0
assigning %vreg100 to %X0: W0 [2408r,2496r:0)  0@2408r

selectOrSplit GPR64:%vreg95 [2448r,2512r:0)  0@2448r w=3.348398e-05
hints: %X1
assigning %vreg95 to %X1: W1 [2448r,2512r:0)  0@2448r

selectOrSplit GPR64:%vreg85 [2576r,2704r:0)  0@2576r w=2.942531e-05
hints: %X0
assigning %vreg85 to %X0: W0 [2576r,2704r:0)  0@2576r

selectOrSplit GPR64:%vreg76 [2768r,2840r:0)  0@2768r w=3.291645e-05
hints: %X0
assigning %vreg76 to %X0: W0 [2768r,2840r:0)  0@2768r

selectOrSplit GPR64:%vreg69 [2880r,2976r:0)  0@2880r w=3.132372e-05
hints: %X0
assigning %vreg69 to %X0: W0 [2880r,2976r:0)  0@2880r

selectOrSplit GPR64:%vreg239 [3320r,3376r:0)  0@3320r w=1.460203e-05
hints: %X0
assigning %vreg239 to %X0: W0 [3320r,3376r:0)  0@3320r

selectOrSplit GPR64:%vreg234 [3328r,3392r:0)  0@3328r w=1.435027e-05
hints: %X1
assigning %vreg234 to %X1: W1 [3328r,3392r:0)  0@3328r

selectOrSplit GPR64:%vreg257 [3640r,3696r:0)  0@3640r w=1.460203e-05
hints: %X0
assigning %vreg257 to %X0: W0 [3640r,3696r:0)  0@3640r

selectOrSplit GPR64:%vreg252 [3648r,3712r:0)  0@3648r w=1.435027e-05
hints: %X1
assigning %vreg252 to %X1: W1 [3648r,3712r:0)  0@3648r

selectOrSplit GPR64:%vreg275 [3960r,4016r:0)  0@3960r w=1.460203e-05
hints: %X0
assigning %vreg275 to %X0: W0 [3960r,4016r:0)  0@3960r

selectOrSplit GPR64:%vreg270 [3968r,4032r:0)  0@3968r w=1.435027e-05
hints: %X1
assigning %vreg270 to %X1: W1 [3968r,4032r:0)  0@3968r

selectOrSplit GPR64:%vreg289 [4240r,4304r:0)  0@4240r w=1.435027e-05
hints: %X0
assigning %vreg289 to %X0: W0 [4240r,4304r:0)  0@4240r

selectOrSplit GPR64:%vreg286 [4256r,4320r:0)  0@4256r w=1.435027e-05
hints: %X1
assigning %vreg286 to %X1: W1 [4256r,4320r:0)  0@4256r

selectOrSplit GPR64:%vreg156 [5344r,5376r:0)  0@5344r w=4.566891e-06
hints: %X0
assigning %vreg156 to %X0: W0 [5344r,5376r:0)  0@5344r

selectOrSplit GPR64:%vreg154 [5472r,5504r:0)  0@5472r w=4.566891e-06
hints: %X0
assigning %vreg154 to %X0: W0 [5472r,5504r:0)  0@5472r

selectOrSplit GPR64sp:%vreg301 [5648r,5712r:0)  0@5648r w=4.353448e-03
hints: %X0
assigning %vreg301 to %X0: W0 [5648r,5712r:0)  0@5648r

selectOrSplit GPR32:%vreg298 [5824r,5840r:0)  0@5824r w=inf
hints: %W0
assigning %vreg298 to %W0: W0 [5824r,5840r:0)  0@5824r

selectOrSplit GPR64common:%vreg10 [160r,176r:0)  0@160r w=inf
assigning %vreg10 to %X8: W8 [160r,176r:0)  0@160r

selectOrSplit GPR32:%vreg15 [560r,576r:0)  0@560r w=inf
assigning %vreg15 to %W8: W8 [560r,576r:0)  0@560r

selectOrSplit GPR64:%vreg17 [624r,640r:0)  0@624r w=inf
assigning %vreg17 to %X8: W8 [624r,640r:0)  0@624r

selectOrSplit GPR32common:%vreg19 [672r,688r:0)  0@672r w=inf
assigning %vreg19 to %W8: W8 [672r,688r:0)  0@672r

selectOrSplit GPR32common:%vreg21 [736r,752r:0)  0@736r w=inf
assigning %vreg21 to %W8: W8 [736r,752r:0)  0@736r

selectOrSplit GPR32:%vreg23 [800r,816r:0)  0@800r w=inf
assigning %vreg23 to %W8: W8 [800r,816r:0)  0@800r

selectOrSplit GPR32common:%vreg25 [848r,864r:0)  0@848r w=inf
assigning %vreg25 to %W8: W8 [848r,864r:0)  0@848r

selectOrSplit GPR32:%vreg296 [912r,928r:0)  0@912r w=inf
assigning %vreg296 to %W8: W8 [912r,928r:0)  0@912r

selectOrSplit GPR32:%vreg27 [976r,992r:0)  0@976r w=inf
assigning %vreg27 to %W8: W8 [976r,992r:0)  0@976r

selectOrSplit GPR32:%vreg28 [1024r,1040r:0)  0@1024r w=inf
assigning %vreg28 to %W8: W8 [1024r,1040r:0)  0@1024r

selectOrSplit GPR64common:%vreg32 [1072r,1088r:0)  0@1072r w=inf
assigning %vreg32 to %X8: W8 [1072r,1088r:0)  0@1072r

selectOrSplit GPR64:%vreg31 [1088r,1104r:0)  0@1088r w=inf
assigning %vreg31 to %X8: W8 [1088r,1104r:0)  0@1088r

selectOrSplit GPR64common:%vreg36 [1168r,1184r:0)  0@1168r w=3.697773e-05
assigning %vreg36 to %X8: W8 [1168r,1184r:0)  0@1168r

selectOrSplit GPR64common:%vreg33 [1172r,1176r:0)  0@1172r w=inf
assigning %vreg33 to %X9: W9 [1172r,1176r:0)  0@1172r

selectOrSplit GPR64common:%vreg34 [1176r,1184r:0)  0@1176r w=inf
assigning %vreg34 to %X9: W9 [1176r,1184r:0)  0@1176r

selectOrSplit GPR64common:%vreg40 [1216r,1232r:0)  0@1216r w=inf
assigning %vreg40 to %X8: W8 [1216r,1232r:0)  0@1216r

selectOrSplit GPR64:%vreg39 [1232r,1248r:0)  0@1232r w=inf
assigning %vreg39 to %X8: W8 [1232r,1248r:0)  0@1232r

selectOrSplit GPR64common:%vreg44 [1312r,1328r:0)  0@1312r w=3.697773e-05
assigning %vreg44 to %X8: W8 [1312r,1328r:0)  0@1312r

selectOrSplit GPR64common:%vreg41 [1316r,1320r:0)  0@1316r w=inf
assigning %vreg41 to %X9: W9 [1316r,1320r:0)  0@1316r

selectOrSplit GPR64common:%vreg42 [1320r,1328r:0)  0@1320r w=inf
assigning %vreg42 to %X9: W9 [1320r,1328r:0)  0@1320r

selectOrSplit GPR64common:%vreg60 [1392r,1432r:0)  0@1392r w=7.047646e-05
assigning %vreg60 to %X8: W8 [1392r,1432r:0)  0@1392r

selectOrSplit GPR64common:%vreg57 [1424r,1440r:0)  0@1424r w=7.454241e-05
assigning %vreg57 to %X9: W9 [1424r,1440r:0)  0@1424r

selectOrSplit GPR64:%vreg59 [1432r,1520r:0)  0@1432r w=6.354435e-05
assigning %vreg59 to %X8: W8 [1432r,1520r:0)  0@1432r

selectOrSplit GPR64:%vreg46 [1648r,1664r:0)  0@1648r w=inf
assigning %vreg46 to %X8: W8 [1648r,1664r:0)  0@1648r

selectOrSplit GPR32:%vreg295 [1696r,1712r:0)  0@1696r w=inf
assigning %vreg295 to %W8: W8 [1696r,1712r:0)  0@1696r

selectOrSplit GPR64:%vreg144 [1808r,1840r:0)  0@1808r w=3.560819e-05
assigning %vreg144 to %X8: W8 [1808r,1840r:0)  0@1808r

selectOrSplit GPR64common:%vreg143 [1824r,1840r:0)  0@1824r w=inf
assigning %vreg143 to %X9: W9 [1824r,1840r:0)  0@1824r

selectOrSplit GPR64common:%vreg140 [1856r,1872r:0)  0@1856r w=inf
assigning %vreg140 to %X8: W8 [1856r,1872r:0)  0@1856r

selectOrSplit GPR64common:%vreg138 [1888r,1904r:0)  0@1888r w=inf
assigning %vreg138 to %X8: W8 [1888r,1904r:0)  0@1888r

selectOrSplit GPR64common:%vreg136 [1920r,1936r:0)  0@1920r w=inf
assigning %vreg136 to %X8: W8 [1920r,1936r:0)  0@1920r

selectOrSplit GPR32:%vreg133 [1952r,1968r:0)  0@1952r w=3.697773e-05
assigning %vreg133 to %W8: W8 [1952r,1968r:0)  0@1952r

selectOrSplit GPR32:%vreg130 [1960r,1968r:0)  0@1960r w=inf
assigning %vreg130 to %W9: W9 [1960r,1968r:0)  0@1960r

selectOrSplit GPR32:%vreg132 [1968r,1984r:0)  0@1968r w=inf
assigning %vreg132 to %W8: W8 [1968r,1984r:0)  0@1968r

selectOrSplit GPR64common:%vreg128 [2000r,2068r:0)  0@2000r w=3.286909e-05
assigning %vreg128 to %X8: W8 [2000r,2068r:0)  0@2000r

selectOrSplit GPR64common:%vreg125 [2032r,2072r:0)  0@2032r w=3.496077e-05
assigning %vreg125 to %X9: W9 [2032r,2072r:0)  0@2032r

selectOrSplit GPR64:%vreg122 [2064r,2080r:0)  0@2064r w=3.697773e-05
assigning %vreg122 to %X10: W10 [2064r,2080r:0)  0@2064r

selectOrSplit GPR64:%vreg127 [2068r,2176r:0)  0@2068r w=3.028098e-05
assigning %vreg127 to %X8: W8 [2068r,2176r:0)  0@2068r

selectOrSplit GPR64common:%vreg107 [2304r,2320r:0)  0@2304r w=inf
assigning %vreg107 to %X8: W8 [2304r,2320r:0)  0@2304r

selectOrSplit GPR64common:%vreg104 [2336r,2404r:0)  0@2336r w=3.286909e-05
assigning %vreg104 to %X8: W8 [2336r,2404r:0)  0@2336r

selectOrSplit GPR64common:%vreg101 [2368r,2408r:0)  0@2368r w=3.496077e-05
assigning %vreg101 to %X9: W9 [2368r,2408r:0)  0@2368r

selectOrSplit GPR32common:%vreg98 [2400r,2416r:0)  0@2400r w=3.697773e-05
assigning %vreg98 to %W10: W10 [2400r,2416r:0)  0@2400r

selectOrSplit GPR64:%vreg103 [2404r,2544r:0)  0@2404r w=2.848655e-05
assigning %vreg103 to %X8: W8 [2404r,2544r:0)  0@2404r

selectOrSplit GPR64common:%vreg94 [2416r,2448r:0)  0@2416r w=inf
assigning %vreg94 to %X9: W9 [2416r,2448r:0)  0@2416r

selectOrSplit GPR64common:%vreg83 [2688r,2704r:0)  0@2688r w=inf
assigning %vreg83 to %X8: W8 [2688r,2704r:0)  0@2688r

selectOrSplit GPR64common:%vreg80 [2720r,2760r:0)  0@2720r w=3.496077e-05
assigning %vreg80 to %X8: W8 [2720r,2760r:0)  0@2720r

selectOrSplit GPR64common:%vreg77 [2752r,2768r:0)  0@2752r w=3.697773e-05
assigning %vreg77 to %X9: W9 [2752r,2768r:0)  0@2752r

selectOrSplit GPR64:%vreg79 [2760r,2848r:0)  0@2760r w=3.152200e-05
assigning %vreg79 to %X8: W8 [2760r,2848r:0)  0@2760r

selectOrSplit GPR64common:%vreg67 [2960r,2976r:0)  0@2960r w=inf
assigning %vreg67 to %X8: W8 [2960r,2976r:0)  0@2960r

selectOrSplit GPR64common:%vreg64 [2992r,3008r:0)  0@2992r w=inf
assigning %vreg64 to %X8: W8 [2992r,3008r:0)  0@2992r

selectOrSplit GPR64:%vreg63 [3008r,3024r:0)  0@3008r w=inf
assigning %vreg63 to %X8: W8 [3008r,3024r:0)  0@3008r

selectOrSplit GPR64common:%vreg148 [3056r,3072r:0)  0@3056r w=inf
assigning %vreg148 to %X8: W8 [3056r,3072r:0)  0@3056r

selectOrSplit GPR64:%vreg147 [3072r,3088r:0)  0@3072r w=inf
assigning %vreg147 to %X8: W8 [3072r,3088r:0)  0@3072r

selectOrSplit GPR64common:%vreg152 [3120r,3136r:0)  0@3120r w=inf
assigning %vreg152 to %X8: W8 [3120r,3136r:0)  0@3120r

selectOrSplit GPR64:%vreg151 [3136r,3152r:0)  0@3136r w=inf
assigning %vreg151 to %X8: W8 [3136r,3152r:0)  0@3136r

selectOrSplit GPR64common:%vreg229 [3184r,3200r:0)  0@3184r w=inf
assigning %vreg229 to %X8: W8 [3184r,3200r:0)  0@3184r

selectOrSplit GPR64:%vreg228 [3200r,3216r:0)  0@3200r w=inf
assigning %vreg228 to %X8: W8 [3200r,3216r:0)  0@3200r

selectOrSplit GPR64common:%vreg243 [3248r,3316r:0)  0@3248r w=1.408676e-05
assigning %vreg243 to %X8: W8 [3248r,3316r:0)  0@3248r

selectOrSplit GPR64common:%vreg240 [3280r,3320r:0)  0@3280r w=1.498318e-05
assigning %vreg240 to %X9: W9 [3280r,3320r:0)  0@3280r

selectOrSplit GPR64common:%vreg237 [3312r,3328r:0)  0@3312r w=1.584760e-05
assigning %vreg237 to %X10: W10 [3312r,3328r:0)  0@3312r

selectOrSplit GPR64:%vreg242 [3316r,3408r:0)  0@3316r w=1.339960e-05
assigning %vreg242 to %X8: W8 [3316r,3408r:0)  0@3316r

selectOrSplit GPR64common:%vreg247 [3504r,3520r:0)  0@3504r w=inf
assigning %vreg247 to %X8: W8 [3504r,3520r:0)  0@3504r

selectOrSplit GPR64:%vreg246 [3520r,3536r:0)  0@3520r w=inf
assigning %vreg246 to %X8: W8 [3520r,3536r:0)  0@3520r

selectOrSplit GPR64common:%vreg261 [3568r,3636r:0)  0@3568r w=1.408676e-05
assigning %vreg261 to %X8: W8 [3568r,3636r:0)  0@3568r

selectOrSplit GPR64common:%vreg258 [3600r,3640r:0)  0@3600r w=1.498318e-05
assigning %vreg258 to %X9: W9 [3600r,3640r:0)  0@3600r

selectOrSplit GPR64common:%vreg255 [3632r,3648r:0)  0@3632r w=1.584760e-05
assigning %vreg255 to %X10: W10 [3632r,3648r:0)  0@3632r

selectOrSplit GPR64:%vreg260 [3636r,3728r:0)  0@3636r w=1.339960e-05
assigning %vreg260 to %X8: W8 [3636r,3728r:0)  0@3636r

selectOrSplit GPR64common:%vreg265 [3824r,3840r:0)  0@3824r w=inf
assigning %vreg265 to %X8: W8 [3824r,3840r:0)  0@3824r

selectOrSplit GPR64:%vreg264 [3840r,3856r:0)  0@3840r w=inf
assigning %vreg264 to %X8: W8 [3840r,3856r:0)  0@3840r

selectOrSplit GPR64common:%vreg279 [3888r,3956r:0)  0@3888r w=1.408676e-05
assigning %vreg279 to %X8: W8 [3888r,3956r:0)  0@3888r

selectOrSplit GPR64common:%vreg276 [3920r,3960r:0)  0@3920r w=1.498318e-05
assigning %vreg276 to %X9: W9 [3920r,3960r:0)  0@3920r

selectOrSplit GPR64common:%vreg273 [3952r,3968r:0)  0@3952r w=1.584760e-05
assigning %vreg273 to %X10: W10 [3952r,3968r:0)  0@3952r

selectOrSplit GPR64:%vreg278 [3956r,4048r:0)  0@3956r w=1.339960e-05
assigning %vreg278 to %X8: W8 [3956r,4048r:0)  0@3956r

selectOrSplit GPR64:%vreg281 [4144r,4160r:0)  0@4144r w=inf
assigning %vreg281 to %X8: W8 [4144r,4160r:0)  0@4144r

selectOrSplit GPR64common:%vreg293 [4192r,4232r:0)  0@4192r w=1.498318e-05
assigning %vreg293 to %X8: W8 [4192r,4232r:0)  0@4192r

selectOrSplit GPR64common:%vreg290 [4224r,4240r:0)  0@4224r w=1.584760e-05
assigning %vreg290 to %X9: W9 [4224r,4240r:0)  0@4224r

selectOrSplit GPR64:%vreg292 [4232r,4336r:0)  0@4232r w=1.308056e-05
assigning %vreg292 to %X8: W8 [4232r,4336r:0)  0@4232r

selectOrSplit GPR32:%vreg294 [4432r,4448r:0)  0@4432r w=inf
assigning %vreg294 to %W8: W8 [4432r,4448r:0)  0@4432r

selectOrSplit GPR64common:%vreg225 [4544r,4560r:0)  0@4544r w=inf
assigning %vreg225 to %X8: W8 [4544r,4560r:0)  0@4544r

selectOrSplit GPR64common:%vreg223 [4576r,4592r:0)  0@4576r w=4.695585e-06
assigning %vreg223 to %X8: W8 [4576r,4592r:0)  0@4576r

selectOrSplit GPR32:%vreg219 [4584r,4624r:0)  0@4584r w=3.329597e-06
assigning %vreg219 to %W9: W9 [4584r,4624r:0)  0@4584r

selectOrSplit GPR64common:%vreg221 [4608r,4624r:0)  0@4608r w=inf
assigning %vreg221 to %X8: W8 [4608r,4624r:0)  0@4608r

selectOrSplit GPR64common:%vreg218 [4640r,4656r:0)  0@4640r w=inf
assigning %vreg218 to %X8: W8 [4640r,4656r:0)  0@4640r

selectOrSplit GPR32:%vreg216 [4672r,4704r:0)  0@4672r w=4.521675e-06
assigning %vreg216 to %W8: W8 [4672r,4704r:0)  0@4672r

selectOrSplit GPR64common:%vreg215 [4688r,4704r:0)  0@4688r w=inf
assigning %vreg215 to %X9: W9 [4688r,4704r:0)  0@4688r

selectOrSplit GPR32:%vreg212 [4720r,4784r:0)  0@4720r w=4.209835e-06
assigning %vreg212 to %W8: W8 [4720r,4784r:0)  0@4720r

selectOrSplit GPR64common:%vreg206 [4768r,4800r:0)  0@4768r w=4.521675e-06
assigning %vreg206 to %X9: W9 [4768r,4800r:0)  0@4768r

selectOrSplit GPR32:%vreg209 [4776r,4784r:0)  0@4776r w=inf
assigning %vreg209 to %W10: W10 [4776r,4784r:0)  0@4776r

selectOrSplit GPR32common:%vreg211 [4784r,4792r:0)  0@4784r w=inf
assigning %vreg211 to %W8: W8 [4784r,4792r:0)  0@4784r

selectOrSplit GPR32common:%vreg208 [4792r,4800r:0)  0@4792r w=inf
assigning %vreg208 to %W8: W8 [4792r,4800r:0)  0@4792r

selectOrSplit GPR32:%vreg203 [4808r,4832r:0)  0@4808r w=4.606989e-06
assigning %vreg203 to %W8: W8 [4808r,4832r:0)  0@4808r

selectOrSplit GPR64common:%vreg202 [4816r,4832r:0)  0@4816r w=inf
assigning %vreg202 to %X9: W9 [4816r,4832r:0)  0@4816r

selectOrSplit GPR32:%vreg199 [4848r,4880r:0)  0@4848r w=4.521675e-06
assigning %vreg199 to %W8: W8 [4848r,4880r:0)  0@4848r

selectOrSplit GPR64common:%vreg198 [4864r,4880r:0)  0@4864r w=inf
assigning %vreg198 to %X9: W9 [4864r,4880r:0)  0@4864r

selectOrSplit GPR64common:%vreg195 [4896r,4952r:0)  0@4896r w=4.283692e-06
assigning %vreg195 to %X8: W8 [4896r,4952r:0)  0@4896r

selectOrSplit GPR64common:%vreg190 [4944r,4960r:0)  0@4944r w=4.695585e-06
assigning %vreg190 to %X9: W9 [4944r,4960r:0)  0@4944r

selectOrSplit GPR64:%vreg192 [4952r,4960r:0)  0@4952r w=inf
assigning %vreg192 to %X8: W8 [4952r,4960r:0)  0@4952r

selectOrSplit GPR64common:%vreg187 [4976r,5032r:0)  0@4976r w=4.283692e-06
assigning %vreg187 to %X8: W8 [4976r,5032r:0)  0@4976r

selectOrSplit GPR64common:%vreg182 [5024r,5040r:0)  0@5024r w=4.695585e-06
assigning %vreg182 to %X9: W9 [5024r,5040r:0)  0@5024r

selectOrSplit GPR64:%vreg184 [5032r,5040r:0)  0@5032r w=inf
assigning %vreg184 to %X8: W8 [5032r,5040r:0)  0@5032r

selectOrSplit GPR64common:%vreg179 [5056r,5072r:0)  0@5056r w=inf
assigning %vreg179 to %X8: W8 [5056r,5072r:0)  0@5056r

selectOrSplit GPR64common:%vreg176 [5088r,5128r:0)  0@5088r w=4.439462e-06
assigning %vreg176 to %X8: W8 [5088r,5128r:0)  0@5088r

selectOrSplit GPR64common:%vreg173 [5120r,5136r:0)  0@5120r w=4.695585e-06
assigning %vreg173 to %X9: W9 [5120r,5136r:0)  0@5120r

selectOrSplit GPR64:%vreg175 [5128r,5136r:0)  0@5128r w=inf
assigning %vreg175 to %X8: W8 [5128r,5136r:0)  0@5128r

selectOrSplit GPR64:%vreg169 [5152r,5200r:0)  0@5152r w=4.360186e-06
assigning %vreg169 to %X8: W8 [5152r,5200r:0)  0@5152r

selectOrSplit GPR64common:%vreg167 [5184r,5200r:0)  0@5184r w=inf
assigning %vreg167 to %X9: W9 [5184r,5200r:0)  0@5184r

selectOrSplit GPR64common:%vreg164 [5216r,5232r:0)  0@5216r w=inf
assigning %vreg164 to %X8: W8 [5216r,5232r:0)  0@5216r

selectOrSplit GPR64common:%vreg162 [5248r,5264r:0)  0@5248r w=inf
assigning %vreg162 to %X8: W8 [5248r,5264r:0)  0@5248r

selectOrSplit GPR64common:%vreg160 [5280r,5296r:0)  0@5280r w=inf
assigning %vreg160 to %X8: W8 [5280r,5296r:0)  0@5280r

selectOrSplit GPR64common:%vreg158 [5312r,5328r:0)  0@5312r w=inf
assigning %vreg158 to %X8: W8 [5312r,5328r:0)  0@5312r

selectOrSplit GPR64common:%vreg299 [5632r,5648r:0)  0@5632r w=inf
assigning %vreg299 to %X8: W8 [5632r,5648r:0)  0@5632r

********** STACK TRANSFORMATION METADATA **********
********** Function: BZ2_bzCompressInit
********** REGISTER MAP **********
[%vreg1 -> %X23] GPR64
[%vreg3 -> %W22] GPR32
[%vreg5 -> %W21] GPR32
[%vreg7 -> %W20] GPR32
[%vreg9 -> %W0] GPR32
[%vreg10 -> %X8] GPR64common
[%vreg12 -> %X0] GPR64sp
[%vreg13 -> %X19] GPR64
[%vreg15 -> %W8] GPR32
[%vreg17 -> %X8] GPR64
[%vreg19 -> %W8] GPR32common
[%vreg21 -> %W8] GPR32common
[%vreg23 -> %W8] GPR32
[%vreg25 -> %W8] GPR32common
[%vreg27 -> %W8] GPR32
[%vreg28 -> %W8] GPR32
[%vreg31 -> %X8] GPR64
[%vreg32 -> %X8] GPR64common
[%vreg33 -> %X9] GPR64common
[%vreg34 -> %X9] GPR64common
[%vreg36 -> %X8] GPR64common
[%vreg39 -> %X8] GPR64
[%vreg40 -> %X8] GPR64common
[%vreg41 -> %X9] GPR64common
[%vreg42 -> %X9] GPR64common
[%vreg44 -> %X8] GPR64common
[%vreg46 -> %X8] GPR64
[%vreg49 -> %X0] GPR64
[%vreg56 -> %X0] GPR64
[%vreg57 -> %X9] GPR64common
[%vreg59 -> %X8] GPR64
[%vreg60 -> %X8] GPR64common
[%vreg63 -> %X8] GPR64
[%vreg64 -> %X8] GPR64common
[%vreg67 -> %X8] GPR64common
[%vreg69 -> %X0] GPR64
[%vreg76 -> %X0] GPR64
[%vreg77 -> %X9] GPR64common
[%vreg79 -> %X8] GPR64
[%vreg80 -> %X8] GPR64common
[%vreg83 -> %X8] GPR64common
[%vreg85 -> %X0] GPR64
[%vreg94 -> %X9] GPR64common
[%vreg95 -> %X1] GPR64
[%vreg98 -> %W10] GPR32common
[%vreg100 -> %X0] GPR64
[%vreg101 -> %X9] GPR64common
[%vreg103 -> %X8] GPR64
[%vreg104 -> %X8] GPR64common
[%vreg107 -> %X8] GPR64common
[%vreg109 -> %X0] GPR64
[%vreg118 -> %X1] GPR64
[%vreg122 -> %X10] GPR64
[%vreg124 -> %X0] GPR64
[%vreg125 -> %X9] GPR64common
[%vreg127 -> %X8] GPR64
[%vreg128 -> %X8] GPR64common
[%vreg130 -> %W9] GPR32
[%vreg132 -> %W8] GPR32
[%vreg133 -> %W8] GPR32
[%vreg136 -> %X8] GPR64common
[%vreg138 -> %X8] GPR64common
[%vreg140 -> %X8] GPR64common
[%vreg143 -> %X9] GPR64common
[%vreg144 -> %X8] GPR64
[%vreg147 -> %X8] GPR64
[%vreg148 -> %X8] GPR64common
[%vreg151 -> %X8] GPR64
[%vreg152 -> %X8] GPR64common
[%vreg154 -> %X0] GPR64
[%vreg156 -> %X0] GPR64
[%vreg158 -> %X8] GPR64common
[%vreg160 -> %X8] GPR64common
[%vreg162 -> %X8] GPR64common
[%vreg164 -> %X8] GPR64common
[%vreg167 -> %X9] GPR64common
[%vreg169 -> %X8] GPR64
[%vreg173 -> %X9] GPR64common
[%vreg175 -> %X8] GPR64
[%vreg176 -> %X8] GPR64common
[%vreg179 -> %X8] GPR64common
[%vreg182 -> %X9] GPR64common
[%vreg184 -> %X8] GPR64
[%vreg187 -> %X8] GPR64common
[%vreg190 -> %X9] GPR64common
[%vreg192 -> %X8] GPR64
[%vreg195 -> %X8] GPR64common
[%vreg198 -> %X9] GPR64common
[%vreg199 -> %W8] GPR32
[%vreg202 -> %X9] GPR64common
[%vreg203 -> %W8] GPR32
[%vreg206 -> %X9] GPR64common
[%vreg208 -> %W8] GPR32common
[%vreg209 -> %W10] GPR32
[%vreg211 -> %W8] GPR32common
[%vreg212 -> %W8] GPR32
[%vreg215 -> %X9] GPR64common
[%vreg216 -> %W8] GPR32
[%vreg218 -> %X8] GPR64common
[%vreg219 -> %W9] GPR32
[%vreg221 -> %X8] GPR64common
[%vreg223 -> %X8] GPR64common
[%vreg225 -> %X8] GPR64common
[%vreg228 -> %X8] GPR64
[%vreg229 -> %X8] GPR64common
[%vreg234 -> %X1] GPR64
[%vreg237 -> %X10] GPR64common
[%vreg239 -> %X0] GPR64
[%vreg240 -> %X9] GPR64common
[%vreg242 -> %X8] GPR64
[%vreg243 -> %X8] GPR64common
[%vreg246 -> %X8] GPR64
[%vreg247 -> %X8] GPR64common
[%vreg252 -> %X1] GPR64
[%vreg255 -> %X10] GPR64common
[%vreg257 -> %X0] GPR64
[%vreg258 -> %X9] GPR64common
[%vreg260 -> %X8] GPR64
[%vreg261 -> %X8] GPR64common
[%vreg264 -> %X8] GPR64
[%vreg265 -> %X8] GPR64common
[%vreg270 -> %X1] GPR64
[%vreg273 -> %X10] GPR64common
[%vreg275 -> %X0] GPR64
[%vreg276 -> %X9] GPR64common
[%vreg278 -> %X8] GPR64
[%vreg279 -> %X8] GPR64common
[%vreg281 -> %X8] GPR64
[%vreg286 -> %X1] GPR64
[%vreg289 -> %X0] GPR64
[%vreg290 -> %X9] GPR64common
[%vreg292 -> %X8] GPR64
[%vreg293 -> %X8] GPR64common
[%vreg294 -> %W8] GPR32
[%vreg295 -> %W8] GPR32
[%vreg296 -> %W8] GPR32
[%vreg298 -> %W0] GPR32
[%vreg299 -> %X8] GPR64common
[%vreg301 -> %X0] GPR64sp


Stackmap 0:
  STACKMAP 0, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, %vreg1, 0, <fi#1>, 0, %vreg5, 0, <fi#3>, 0, %vreg7, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4) GPR32:%vreg3,%vreg5,%vreg7 GPR64:%vreg1

i32 %blockSize100k: in register %W22 (vreg 3)
i32* %blockSize100k.addr: in stack slot 2 (size: 4)
i32* %n: in stack slot 5 (size: 4)
i32* %retval: in stack slot 0 (size: 4)
%struct.EState** %s: in stack slot 6 (size: 8)
%struct.bz_stream* %strm: in register %X23 (vreg 1)
%struct.bz_stream** %strm.addr: in stack slot 1 (size: 8)
i32 %verbosity: in register %W21 (vreg 5)
i32* %verbosity.addr: in stack slot 3 (size: 4)
i32 %workFactor: in register %W20 (vreg 7)
i32* %workFactor.addr: in stack slot 4 (size: 4)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)

i32* %blockSize100k.addr: in stack slot 2 (size: 4)
i32* %n: in stack slot 5 (size: 4)
i32* %retval: in stack slot 0 (size: 4)
%struct.EState** %s: in stack slot 6 (size: 8)
%struct.bz_stream** %strm.addr: in stack slot 1 (size: 8)
i32* %verbosity.addr: in stack slot 3 (size: 4)
i32* %workFactor.addr: in stack slot 4 (size: 4)

Duplicate operand locations:


Stackmap 2:
  STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)

i32* %blockSize100k.addr: in stack slot 2 (size: 4)
i32* %n: in stack slot 5 (size: 4)
i32* %retval: in stack slot 0 (size: 4)
%struct.EState** %s: in stack slot 6 (size: 8)
%struct.bz_stream** %strm.addr: in stack slot 1 (size: 8)
i32* %verbosity.addr: in stack slot 3 (size: 4)
i32* %workFactor.addr: in stack slot 4 (size: 4)

Duplicate operand locations:


Stackmap 3:
  STACKMAP 3, 0, 0, <fi#2>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)

i32* %blockSize100k.addr: in stack slot 2 (size: 4)
i32* %n: in stack slot 5 (size: 4)
i32* %retval: in stack slot 0 (size: 4)
%struct.EState** %s: in stack slot 6 (size: 8)
%struct.bz_stream** %strm.addr: in stack slot 1 (size: 8)
i32* %verbosity.addr: in stack slot 3 (size: 4)
i32* %workFactor.addr: in stack slot 4 (size: 4)

Duplicate operand locations:


Stackmap 4:
  STACKMAP 4, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)

i32* %blockSize100k.addr: in stack slot 2 (size: 4)
i32* %retval: in stack slot 0 (size: 4)
%struct.EState** %s: in stack slot 6 (size: 8)
%struct.bz_stream** %strm.addr: in stack slot 1 (size: 8)
i32* %verbosity.addr: in stack slot 3 (size: 4)
i32* %workFactor.addr: in stack slot 4 (size: 4)

Duplicate operand locations:


Stackmap 5:
  STACKMAP 5, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)

i32* %blockSize100k.addr: in stack slot 2 (size: 4)
i32* %retval: in stack slot 0 (size: 4)
%struct.EState** %s: in stack slot 6 (size: 8)
%struct.bz_stream** %strm.addr: in stack slot 1 (size: 8)
i32* %verbosity.addr: in stack slot 3 (size: 4)
i32* %workFactor.addr: in stack slot 4 (size: 4)

Duplicate operand locations:


Stackmap 6:
  STACKMAP 6, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1]

i32* %retval: in stack slot 0 (size: 4)
%struct.EState** %s: in stack slot 6 (size: 8)
%struct.bz_stream** %strm.addr: in stack slot 1 (size: 8)

Duplicate operand locations:


Stackmap 7:
  STACKMAP 7, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1]

i32* %retval: in stack slot 0 (size: 4)
%struct.EState** %s: in stack slot 6 (size: 8)
%struct.bz_stream** %strm.addr: in stack slot 1 (size: 8)

Duplicate operand locations:


Stackmap 8:
  STACKMAP 8, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1]

i32* %retval: in stack slot 0 (size: 4)
%struct.EState** %s: in stack slot 6 (size: 8)
%struct.bz_stream** %strm.addr: in stack slot 1 (size: 8)

Duplicate operand locations:


Stackmap 9:
  STACKMAP 9, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)

i32* %retval: in stack slot 0 (size: 4)

Duplicate operand locations:


Stackmap 10:
  STACKMAP 10, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack6]

i32* %retval: in stack slot 0 (size: 4)
%struct.EState** %s: in stack slot 6 (size: 8)

Duplicate operand locations:


Stackmap 11:
  STACKMAP 11, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)

i32* %retval: in stack slot 0 (size: 4)

Duplicate operand locations:


Stackmap 12:
  STACKMAP 12, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)

i32* %retval: in stack slot 0 (size: 4)

Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, %vreg1, 0, <fi#1>, 0, %vreg5, 0, <fi#3>, 0, %vreg7, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4) GPR32:%vreg3,%vreg5,%vreg7 GPR64:%vreg1
  -> Call instruction SlotIndex 272B, searching vregs 0 -> 303 and stack slots 0 -> 7
    + vreg13 is live in register but not in stackmap
      Defining instruction: %vreg13<def> = COPY %LR; GPR64:%vreg13
      Value: generated value, 1 instruction(s)

  STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)
  -> Call instruction SlotIndex 432B, searching vregs 0 -> 303 and stack slots 0 -> 7
    + vreg13 is live in register but not in stackmap
      Defining instruction: %vreg13<def> = COPY %LR; GPR64:%vreg13
      Value: generated value, 1 instruction(s)

  STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)
  -> Call instruction SlotIndex 1520B, searching vregs 0 -> 303 and stack slots 0 -> 7
    + vreg13 is live in register but not in stackmap
      Defining instruction: %vreg13<def> = COPY %LR; GPR64:%vreg13
      Value: generated value, 1 instruction(s)

  STACKMAP 3, 0, 0, <fi#2>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)
  -> Call instruction SlotIndex 2176B, searching vregs 0 -> 303 and stack slots 0 -> 7
    + vreg13 is live in register but not in stackmap
      Defining instruction: %vreg13<def> = COPY %LR; GPR64:%vreg13
      Value: generated value, 1 instruction(s)

  STACKMAP 4, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)
  -> Call instruction SlotIndex 2544B, searching vregs 0 -> 303 and stack slots 0 -> 7
    + vreg13 is live in register but not in stackmap
      Defining instruction: %vreg13<def> = COPY %LR; GPR64:%vreg13
      Value: generated value, 1 instruction(s)

  STACKMAP 5, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)
  -> Call instruction SlotIndex 2848B, searching vregs 0 -> 303 and stack slots 0 -> 7
    + vreg13 is live in register but not in stackmap
      Defining instruction: %vreg13<def> = COPY %LR; GPR64:%vreg13
      Value: generated value, 1 instruction(s)

  STACKMAP 6, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1]
  -> Call instruction SlotIndex 3408B, searching vregs 0 -> 303 and stack slots 0 -> 7
    + vreg13 is live in register but not in stackmap
      Defining instruction: %vreg13<def> = COPY %LR; GPR64:%vreg13
      Value: generated value, 1 instruction(s)

  STACKMAP 7, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1]
  -> Call instruction SlotIndex 3728B, searching vregs 0 -> 303 and stack slots 0 -> 7
    + vreg13 is live in register but not in stackmap
      Defining instruction: %vreg13<def> = COPY %LR; GPR64:%vreg13
      Value: generated value, 1 instruction(s)

  STACKMAP 8, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1]
  -> Call instruction SlotIndex 4048B, searching vregs 0 -> 303 and stack slots 0 -> 7
    + vreg13 is live in register but not in stackmap
      Defining instruction: %vreg13<def> = COPY %LR; GPR64:%vreg13
      Value: generated value, 1 instruction(s)

  STACKMAP 9, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
  -> Call instruction SlotIndex 4336B, searching vregs 0 -> 303 and stack slots 0 -> 7
    + vreg13 is live in register but not in stackmap
      Defining instruction: %vreg13<def> = COPY %LR; GPR64:%vreg13
      Value: generated value, 1 instruction(s)

  STACKMAP 10, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack6]
  -> Call instruction SlotIndex 5392B, searching vregs 0 -> 303 and stack slots 0 -> 7
    + vreg13 is live in register but not in stackmap
      Defining instruction: %vreg13<def> = COPY %LR; GPR64:%vreg13
      Value: generated value, 1 instruction(s)

  STACKMAP 11, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
  -> Call instruction SlotIndex 5520B, searching vregs 0 -> 303 and stack slots 0 -> 7
    + vreg13 is live in register but not in stackmap
      Defining instruction: %vreg13<def> = COPY %LR; GPR64:%vreg13
      Value: generated value, 1 instruction(s)

  STACKMAP 12, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
  -> Call instruction SlotIndex 5744B, searching vregs 0 -> 303 and stack slots 0 -> 7

********** REWRITE VIRTUAL REGISTERS **********
********** Function: BZ2_bzCompressInit
********** REGISTER MAP **********
[%vreg1 -> %X23] GPR64
[%vreg3 -> %W22] GPR32
[%vreg5 -> %W21] GPR32
[%vreg7 -> %W20] GPR32
[%vreg9 -> %W0] GPR32
[%vreg10 -> %X8] GPR64common
[%vreg12 -> %X0] GPR64sp
[%vreg13 -> %X19] GPR64
[%vreg15 -> %W8] GPR32
[%vreg17 -> %X8] GPR64
[%vreg19 -> %W8] GPR32common
[%vreg21 -> %W8] GPR32common
[%vreg23 -> %W8] GPR32
[%vreg25 -> %W8] GPR32common
[%vreg27 -> %W8] GPR32
[%vreg28 -> %W8] GPR32
[%vreg31 -> %X8] GPR64
[%vreg32 -> %X8] GPR64common
[%vreg33 -> %X9] GPR64common
[%vreg34 -> %X9] GPR64common
[%vreg36 -> %X8] GPR64common
[%vreg39 -> %X8] GPR64
[%vreg40 -> %X8] GPR64common
[%vreg41 -> %X9] GPR64common
[%vreg42 -> %X9] GPR64common
[%vreg44 -> %X8] GPR64common
[%vreg46 -> %X8] GPR64
[%vreg49 -> %X0] GPR64
[%vreg56 -> %X0] GPR64
[%vreg57 -> %X9] GPR64common
[%vreg59 -> %X8] GPR64
[%vreg60 -> %X8] GPR64common
[%vreg63 -> %X8] GPR64
[%vreg64 -> %X8] GPR64common
[%vreg67 -> %X8] GPR64common
[%vreg69 -> %X0] GPR64
[%vreg76 -> %X0] GPR64
[%vreg77 -> %X9] GPR64common
[%vreg79 -> %X8] GPR64
[%vreg80 -> %X8] GPR64common
[%vreg83 -> %X8] GPR64common
[%vreg85 -> %X0] GPR64
[%vreg94 -> %X9] GPR64common
[%vreg95 -> %X1] GPR64
[%vreg98 -> %W10] GPR32common
[%vreg100 -> %X0] GPR64
[%vreg101 -> %X9] GPR64common
[%vreg103 -> %X8] GPR64
[%vreg104 -> %X8] GPR64common
[%vreg107 -> %X8] GPR64common
[%vreg109 -> %X0] GPR64
[%vreg118 -> %X1] GPR64
[%vreg122 -> %X10] GPR64
[%vreg124 -> %X0] GPR64
[%vreg125 -> %X9] GPR64common
[%vreg127 -> %X8] GPR64
[%vreg128 -> %X8] GPR64common
[%vreg130 -> %W9] GPR32
[%vreg132 -> %W8] GPR32
[%vreg133 -> %W8] GPR32
[%vreg136 -> %X8] GPR64common
[%vreg138 -> %X8] GPR64common
[%vreg140 -> %X8] GPR64common
[%vreg143 -> %X9] GPR64common
[%vreg144 -> %X8] GPR64
[%vreg147 -> %X8] GPR64
[%vreg148 -> %X8] GPR64common
[%vreg151 -> %X8] GPR64
[%vreg152 -> %X8] GPR64common
[%vreg154 -> %X0] GPR64
[%vreg156 -> %X0] GPR64
[%vreg158 -> %X8] GPR64common
[%vreg160 -> %X8] GPR64common
[%vreg162 -> %X8] GPR64common
[%vreg164 -> %X8] GPR64common
[%vreg167 -> %X9] GPR64common
[%vreg169 -> %X8] GPR64
[%vreg173 -> %X9] GPR64common
[%vreg175 -> %X8] GPR64
[%vreg176 -> %X8] GPR64common
[%vreg179 -> %X8] GPR64common
[%vreg182 -> %X9] GPR64common
[%vreg184 -> %X8] GPR64
[%vreg187 -> %X8] GPR64common
[%vreg190 -> %X9] GPR64common
[%vreg192 -> %X8] GPR64
[%vreg195 -> %X8] GPR64common
[%vreg198 -> %X9] GPR64common
[%vreg199 -> %W8] GPR32
[%vreg202 -> %X9] GPR64common
[%vreg203 -> %W8] GPR32
[%vreg206 -> %X9] GPR64common
[%vreg208 -> %W8] GPR32common
[%vreg209 -> %W10] GPR32
[%vreg211 -> %W8] GPR32common
[%vreg212 -> %W8] GPR32
[%vreg215 -> %X9] GPR64common
[%vreg216 -> %W8] GPR32
[%vreg218 -> %X8] GPR64common
[%vreg219 -> %W9] GPR32
[%vreg221 -> %X8] GPR64common
[%vreg223 -> %X8] GPR64common
[%vreg225 -> %X8] GPR64common
[%vreg228 -> %X8] GPR64
[%vreg229 -> %X8] GPR64common
[%vreg234 -> %X1] GPR64
[%vreg237 -> %X10] GPR64common
[%vreg239 -> %X0] GPR64
[%vreg240 -> %X9] GPR64common
[%vreg242 -> %X8] GPR64
[%vreg243 -> %X8] GPR64common
[%vreg246 -> %X8] GPR64
[%vreg247 -> %X8] GPR64common
[%vreg252 -> %X1] GPR64
[%vreg255 -> %X10] GPR64common
[%vreg257 -> %X0] GPR64
[%vreg258 -> %X9] GPR64common
[%vreg260 -> %X8] GPR64
[%vreg261 -> %X8] GPR64common
[%vreg264 -> %X8] GPR64
[%vreg265 -> %X8] GPR64common
[%vreg270 -> %X1] GPR64
[%vreg273 -> %X10] GPR64common
[%vreg275 -> %X0] GPR64
[%vreg276 -> %X9] GPR64common
[%vreg278 -> %X8] GPR64
[%vreg279 -> %X8] GPR64common
[%vreg281 -> %X8] GPR64
[%vreg286 -> %X1] GPR64
[%vreg289 -> %X0] GPR64
[%vreg290 -> %X9] GPR64common
[%vreg292 -> %X8] GPR64
[%vreg293 -> %X8] GPR64common
[%vreg294 -> %W8] GPR32
[%vreg295 -> %W8] GPR32
[%vreg296 -> %W8] GPR32
[%vreg298 -> %W0] GPR32
[%vreg299 -> %X8] GPR64common
[%vreg301 -> %X0] GPR64sp

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %LR %W1 %W2 %W3 %X0
16B		%vreg13<def> = COPY %LR; GPR64:%vreg13
32B		%vreg7<def> = COPY %W3; GPR32:%vreg7
48B		%vreg5<def> = COPY %W2; GPR32:%vreg5
64B		%vreg3<def> = COPY %W1; GPR32:%vreg3
80B		%vreg1<def> = COPY %X0; GPR64:%vreg1
160B		%vreg10<def> = ADRP <ga:@BZ2_bzCompressInit>[TF=1]; GPR64common:%vreg10
176B		%vreg12<def> = ADDXri %vreg10<kill>, <ga:@BZ2_bzCompressInit>[TF=34], 0; GPR64sp:%vreg12 GPR64common:%vreg10
224B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
240B		%X0<def> = COPY %vreg12<kill>; GPR64sp:%vreg12
256B		%X1<def> = COPY %vreg13; GPR64:%vreg13
272B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
288B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
304B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
320B		STACKMAP 0, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, %vreg1, 0, <fi#1>, 0, %vreg5, 0, <fi#3>, 0, %vreg7, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4) GPR32:%vreg3,%vreg5,%vreg7 GPR64:%vreg1
336B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
352B		STRXui %vreg1<kill>, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg1
368B		STRWui %vreg3<kill>, <fi#2>, 0; mem:ST4[FixedStack2] GPR32:%vreg3
384B		STRWui %vreg5<kill>, <fi#3>, 0; mem:ST4[FixedStack3] GPR32:%vreg5
400B		STRWui %vreg7<kill>, <fi#4>, 0; mem:ST4[FixedStack4] GPR32:%vreg7
416B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
432B		BL <ga:@bz_config_ok>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-def>
448B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
464B		%vreg9<def> = COPY %W0; GPR32:%vreg9
480B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
496B		STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)
512B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
528B		CBNZW %vreg9<kill>, <BB#2>; GPR32:%vreg9
	    Successors according to CFG: BB#2 BB#1
> %X19<def> = COPY %LR
> %W20<def> = COPY %W3
> %W21<def> = COPY %W2
> %W22<def> = COPY %W1
> %X23<def> = COPY %X0
> %X8<def> = ADRP <ga:@BZ2_bzCompressInit>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@BZ2_bzCompressInit>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19
> BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 0, 0, %W22, 0, <fi#2>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, %X23, 0, <fi#1>, 0, %W21, 0, <fi#3>, 0, %W20, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRXui %X23<kill>, <fi#1>, 0; mem:ST8[FixedStack1]
> STRWui %W22<kill>, <fi#2>, 0; mem:ST4[FixedStack2]
> STRWui %W21<kill>, <fi#3>, 0; mem:ST4[FixedStack3]
> STRWui %W20<kill>, <fi#4>, 0; mem:ST4[FixedStack4]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> BL <ga:@bz_config_ok>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = COPY %W0
Deleting identity copy.
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> CBNZW %W0<kill>, <BB#2>
544B	BB#1: derived from LLVM BB %if.then
	    Live Ins: %X19
	    Predecessors according to CFG: BB#0
560B		%vreg15<def> = MOVi32imm 4294967287; GPR32:%vreg15
576B		STRWui %vreg15<kill>, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg15
592B		B <BB#29>
	    Successors according to CFG: BB#29
> %W8<def> = MOVi32imm 4294967287
> STRWui %W8<kill>, <fi#0>, 0; mem:ST4[FixedStack0]
> B <BB#29>
608B	BB#2: derived from LLVM BB %if.end
	    Live Ins: %X19
	    Predecessors according to CFG: BB#0
624B		%vreg17<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg17
640B		CBZX %vreg17<kill>, <BB#7>; GPR64:%vreg17
	    Successors according to CFG: BB#7 BB#3
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> CBZX %X8<kill>, <BB#7>
656B	BB#3: derived from LLVM BB %lor.lhs.false
	    Live Ins: %X19
	    Predecessors according to CFG: BB#2
672B		%vreg19<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32common:%vreg19
688B		%WZR<def> = SUBSWri %vreg19<kill>, 1, 0, %NZCV<imp-def>; GPR32common:%vreg19
704B		Bcc 11, <BB#7>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#7 BB#4
> %W8<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2]
> %WZR<def> = SUBSWri %W8<kill>, 1, 0, %NZCV<imp-def>
> Bcc 11, <BB#7>, %NZCV<imp-use,kill>
720B	BB#4: derived from LLVM BB %lor.lhs.false.2
	    Live Ins: %X19
	    Predecessors according to CFG: BB#3
736B		%vreg21<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32common:%vreg21
752B		%WZR<def> = SUBSWri %vreg21<kill>, 9, 0, %NZCV<imp-def>; GPR32common:%vreg21
768B		Bcc 12, <BB#7>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#7 BB#5
> %W8<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2]
> %WZR<def> = SUBSWri %W8<kill>, 9, 0, %NZCV<imp-def>
> Bcc 12, <BB#7>, %NZCV<imp-use,kill>
784B	BB#5: derived from LLVM BB %lor.lhs.false.4
	    Live Ins: %X19
	    Predecessors according to CFG: BB#4
800B		%vreg23<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg23
816B		TBNZW %vreg23<kill>, 31, <BB#7>; GPR32:%vreg23
	    Successors according to CFG: BB#7 BB#6
> %W8<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4]
> TBNZW %W8<kill>, 31, <BB#7>
832B	BB#6: derived from LLVM BB %lor.lhs.false.6
	    Live Ins: %X19
	    Predecessors according to CFG: BB#5
848B		%vreg25<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32common:%vreg25
864B		%WZR<def> = SUBSWri %vreg25<kill>, 250, 0, %NZCV<imp-def>; GPR32common:%vreg25
880B		Bcc 13, <BB#8>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#8 BB#7
> %W8<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4]
> %WZR<def> = SUBSWri %W8<kill>, 250, 0, %NZCV<imp-def>
> Bcc 13, <BB#8>, %NZCV<imp-use,kill>
896B	BB#7: derived from LLVM BB %if.then.8
	    Live Ins: %X19
	    Predecessors according to CFG: BB#2 BB#3 BB#4 BB#5 BB#6
912B		%vreg296<def> = MOVi32imm 4294967294; GPR32:%vreg296
928B		STRWui %vreg296<kill>, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg296
944B		B <BB#29>
	    Successors according to CFG: BB#29
> %W8<def> = MOVi32imm 4294967294
> STRWui %W8<kill>, <fi#0>, 0; mem:ST4[FixedStack0]
> B <BB#29>
960B	BB#8: derived from LLVM BB %if.end.9
	    Live Ins: %X19
	    Predecessors according to CFG: BB#6
976B		%vreg27<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg27
992B		CBNZW %vreg27<kill>, <BB#10>; GPR32:%vreg27
	    Successors according to CFG: BB#10 BB#9
> %W8<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4]
> CBNZW %W8<kill>, <BB#10>
1008B	BB#9: derived from LLVM BB %if.then.11
	    Live Ins: %X19
	    Predecessors according to CFG: BB#8
1024B		%vreg28<def> = MOVi32imm 30; GPR32:%vreg28
1040B		STRWui %vreg28<kill>, <fi#4>, 0; mem:ST4[FixedStack4] GPR32:%vreg28
	    Successors according to CFG: BB#10
> %W8<def> = MOVi32imm 30
> STRWui %W8<kill>, <fi#4>, 0; mem:ST4[FixedStack4]
1056B	BB#10: derived from LLVM BB %if.end.12
	    Live Ins: %X19
	    Predecessors according to CFG: BB#8 BB#9
1072B		%vreg32<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg32
1088B		%vreg31<def> = LDRXui %vreg32<kill>, 7; mem:LD8[%bzalloc] GPR64:%vreg31 GPR64common:%vreg32
1104B		CBNZX %vreg31<kill>, <BB#12>; GPR64:%vreg31
	    Successors according to CFG: BB#12 BB#11
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X8<def> = LDRXui %X8<kill>, 7; mem:LD8[%bzalloc]
> CBNZX %X8<kill>, <BB#12>
1120B	BB#11: derived from LLVM BB %if.then.14
	    Live Ins: %X19
	    Predecessors according to CFG: BB#10
1168B		%vreg36<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg36
1172B		%vreg33<def> = ADRP <ga:@default_bzalloc>[TF=1]; GPR64common:%vreg33
1176B		%vreg34<def> = ADDXri %vreg33<kill>, <ga:@default_bzalloc>[TF=34], 0; GPR64common:%vreg34,%vreg33
1184B		STRXui %vreg34<kill>, %vreg36<kill>, 7; mem:ST8[%bzalloc15] GPR64common:%vreg34,%vreg36
	    Successors according to CFG: BB#12
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X9<def> = ADRP <ga:@default_bzalloc>[TF=1]
> %X9<def> = ADDXri %X9<kill>, <ga:@default_bzalloc>[TF=34], 0
> STRXui %X9<kill>, %X8<kill>, 7; mem:ST8[%bzalloc15]
1200B	BB#12: derived from LLVM BB %if.end.16
	    Live Ins: %X19
	    Predecessors according to CFG: BB#10 BB#11
1216B		%vreg40<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg40
1232B		%vreg39<def> = LDRXui %vreg40<kill>, 8; mem:LD8[%bzfree] GPR64:%vreg39 GPR64common:%vreg40
1248B		CBNZX %vreg39<kill>, <BB#14>; GPR64:%vreg39
	    Successors according to CFG: BB#14 BB#13
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X8<def> = LDRXui %X8<kill>, 8; mem:LD8[%bzfree]
> CBNZX %X8<kill>, <BB#14>
1264B	BB#13: derived from LLVM BB %if.then.18
	    Live Ins: %X19
	    Predecessors according to CFG: BB#12
1312B		%vreg44<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg44
1316B		%vreg41<def> = ADRP <ga:@default_bzfree>[TF=1]; GPR64common:%vreg41
1320B		%vreg42<def> = ADDXri %vreg41<kill>, <ga:@default_bzfree>[TF=34], 0; GPR64common:%vreg42,%vreg41
1328B		STRXui %vreg42<kill>, %vreg44<kill>, 8; mem:ST8[%bzfree19] GPR64common:%vreg42,%vreg44
	    Successors according to CFG: BB#14
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X9<def> = ADRP <ga:@default_bzfree>[TF=1]
> %X9<def> = ADDXri %X9<kill>, <ga:@default_bzfree>[TF=34], 0
> STRXui %X9<kill>, %X8<kill>, 8; mem:ST8[%bzfree19]
1344B	BB#14: derived from LLVM BB %if.end.20
	    Live Ins: %X19
	    Predecessors according to CFG: BB#12 BB#13
1392B		%vreg60<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg60
1424B		%vreg57<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg57
1432B		%vreg59<def> = LDRXui %vreg60<kill>, 7; mem:LD8[%bzalloc21] GPR64:%vreg59 GPR64common:%vreg60
1440B		%vreg56<def> = LDRXui %vreg57<kill>, 9; mem:LD8[%opaque] GPR64:%vreg56 GPR64common:%vreg57
1456B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1488B		%W1<def> = MOVi32imm 55768
1504B		%W2<def> = MOVi32imm 1
1512B		%X0<def> = COPY %vreg56<kill>; GPR64:%vreg56
1520B		BLR %vreg59<kill>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %W2<imp-use>, %X0<imp-def>; GPR64:%vreg59
1536B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1552B		%vreg49<def> = COPY %X0; GPR64:%vreg49
1568B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1584B		STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)
1600B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1632B		STRXui %vreg49<kill>, <fi#6>, 0; mem:ST8[FixedStack6] GPR64:%vreg49
1648B		%vreg46<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64:%vreg46
1664B		CBNZX %vreg46<kill>, <BB#16>; GPR64:%vreg46
	    Successors according to CFG: BB#16 BB#15
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X8<def> = LDRXui %X8<kill>, 7; mem:LD8[%bzalloc21]
> %X0<def> = LDRXui %X9<kill>, 9; mem:LD8[%opaque]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %W1<def> = MOVi32imm 55768
> %W2<def> = MOVi32imm 1
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BLR %X8<kill>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %W2<imp-use>, %X0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0
Deleting identity copy.
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRXui %X0<kill>, <fi#6>, 0; mem:ST8[FixedStack6]
> %X8<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6]
> CBNZX %X8<kill>, <BB#16>
1680B	BB#15: derived from LLVM BB %if.then.24
	    Live Ins: %X19
	    Predecessors according to CFG: BB#14
1696B		%vreg295<def> = MOVi32imm 4294967293; GPR32:%vreg295
1712B		STRWui %vreg295<kill>, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg295
1728B		B <BB#29>
	    Successors according to CFG: BB#29
> %W8<def> = MOVi32imm 4294967293
> STRWui %W8<kill>, <fi#0>, 0; mem:ST4[FixedStack0]
> B <BB#29>
1744B	BB#16: derived from LLVM BB %if.end.25
	    Live Ins: %X19
	    Predecessors according to CFG: BB#14
1808B		%vreg144<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg144
1824B		%vreg143<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg143
1840B		STRXui %vreg144<kill>, %vreg143<kill>, 0; mem:ST8[%strm26] GPR64:%vreg144 GPR64common:%vreg143
1856B		%vreg140<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg140
1872B		STRXui %XZR, %vreg140<kill>, 3; mem:ST8[%arr1] GPR64common:%vreg140
1888B		%vreg138<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg138
1904B		STRXui %XZR, %vreg138<kill>, 4; mem:ST8[%arr2] GPR64common:%vreg138
1920B		%vreg136<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg136
1936B		STRXui %XZR, %vreg136<kill>, 5; mem:ST8[%ftab] GPR64common:%vreg136
1952B		%vreg133<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg133
1960B		%vreg130<def> = MOVi32imm 100000; GPR32:%vreg130
1968B		%vreg132<def> = MADDWrrr %vreg130<kill>, %vreg133<kill>, %WZR; GPR32:%vreg132,%vreg130,%vreg133
1984B		STRWui %vreg132<kill>, <fi#5>, 0; mem:ST4[FixedStack5] GPR32:%vreg132
2000B		%vreg128<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg128
2032B		%vreg125<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg125
2064B		%vreg122<def> = LDRSWui <fi#5>, 0; mem:LD4[FixedStack5] GPR64:%vreg122
2068B		%vreg127<def> = LDRXui %vreg128<kill>, 7; mem:LD8[%bzalloc27] GPR64:%vreg127 GPR64common:%vreg128
2072B		%vreg124<def> = LDRXui %vreg125<kill>, 9; mem:LD8[%opaque28] GPR64:%vreg124 GPR64common:%vreg125
2080B		%vreg118<def> = UBFMXri %vreg122<kill>, 62, 61; GPR64:%vreg118,%vreg122
2112B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2120B		%W2<def> = MOVi32imm 1
2128B		%X0<def> = COPY %vreg124<kill>; GPR64:%vreg124
2144B		%W1<def> = COPY %vreg118:sub_32<kill>; GPR64:%vreg118
2176B		BLR %vreg127<kill>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %W2<imp-use>, %X0<imp-def>; GPR64:%vreg127
2192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2208B		%vreg109<def> = COPY %X0; GPR64:%vreg109
2240B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2256B		STACKMAP 3, 0, 0, <fi#2>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)
2272B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2304B		%vreg107<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg107
2320B		STRXui %vreg109<kill>, %vreg107<kill>, 3; mem:ST8[%arr132] GPR64:%vreg109 GPR64common:%vreg107
2336B		%vreg104<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg104
2368B		%vreg101<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg101
2400B		%vreg98<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32common:%vreg98
2404B		%vreg103<def> = LDRXui %vreg104<kill>, 7; mem:LD8[%bzalloc33] GPR64:%vreg103 GPR64common:%vreg104
2408B		%vreg100<def> = LDRXui %vreg101<kill>, 9; mem:LD8[%opaque34] GPR64:%vreg100 GPR64common:%vreg101
2416B		%vreg94:sub_32<def,read-undef> = ADDWri %vreg98<kill>, 34, 0; GPR64common:%vreg94 GPR32common:%vreg98
2448B		%vreg95<def> = SBFMXri %vreg94<kill>, 62, 31; GPR64:%vreg95 GPR64common:%vreg94
2480B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2488B		%W2<def> = MOVi32imm 1
2496B		%X0<def> = COPY %vreg100<kill>; GPR64:%vreg100
2512B		%W1<def> = COPY %vreg95:sub_32<kill>; GPR64:%vreg95
2544B		BLR %vreg103<kill>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %W2<imp-use>, %X0<imp-def>; GPR64:%vreg103
2560B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2576B		%vreg85<def> = COPY %X0; GPR64:%vreg85
2624B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2640B		STACKMAP 4, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)
2656B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2688B		%vreg83<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg83
2704B		STRXui %vreg85<kill>, %vreg83<kill>, 4; mem:ST8[%arr239] GPR64:%vreg85 GPR64common:%vreg83
2720B		%vreg80<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg80
2752B		%vreg77<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg77
2760B		%vreg79<def> = LDRXui %vreg80<kill>, 7; mem:LD8[%bzalloc40] GPR64:%vreg79 GPR64common:%vreg80
2768B		%vreg76<def> = LDRXui %vreg77<kill>, 9; mem:LD8[%opaque41] GPR64:%vreg76 GPR64common:%vreg77
2784B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2816B		%W1<def> = MOVi32imm 262148
2832B		%W2<def> = MOVi32imm 1
2840B		%X0<def> = COPY %vreg76<kill>; GPR64:%vreg76
2848B		BLR %vreg79<kill>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %W2<imp-use>, %X0<imp-def>; GPR64:%vreg79
2864B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2880B		%vreg69<def> = COPY %X0; GPR64:%vreg69
2896B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2912B		STACKMAP 5, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)
2928B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2960B		%vreg67<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg67
2976B		STRXui %vreg69<kill>, %vreg67<kill>, 5; mem:ST8[%ftab43] GPR64:%vreg69 GPR64common:%vreg67
2992B		%vreg64<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg64
3008B		%vreg63<def> = LDRXui %vreg64<kill>, 3; mem:LD8[%arr144] GPR64:%vreg63 GPR64common:%vreg64
3024B		CBZX %vreg63<kill>, <BB#19>; GPR64:%vreg63
	    Successors according to CFG: BB#19 BB#17
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X9<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6]
> STRXui %X8<kill>, %X9<kill>, 0; mem:ST8[%strm26]
> %X8<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6]
> STRXui %XZR, %X8<kill>, 3; mem:ST8[%arr1]
> %X8<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6]
> STRXui %XZR, %X8<kill>, 4; mem:ST8[%arr2]
> %X8<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6]
> STRXui %XZR, %X8<kill>, 5; mem:ST8[%ftab]
> %W8<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2]
> %W9<def> = MOVi32imm 100000
> %W8<def> = MADDWrrr %W9<kill>, %W8<kill>, %WZR
> STRWui %W8<kill>, <fi#5>, 0; mem:ST4[FixedStack5]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X10<def> = LDRSWui <fi#5>, 0; mem:LD4[FixedStack5]
> %X8<def> = LDRXui %X8<kill>, 7; mem:LD8[%bzalloc27]
> %X0<def> = LDRXui %X9<kill>, 9; mem:LD8[%opaque28]
> %X1<def> = UBFMXri %X10<kill>, 62, 61
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %W2<def> = MOVi32imm 1
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %W1<def> = COPY %W1, %X1<imp-use,kill>
Deleting identity copy.
> BLR %X8<kill>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %W2<imp-use>, %X0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0
Deleting identity copy.
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 3, 0, 0, <fi#2>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X8<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6]
> STRXui %X0<kill>, %X8<kill>, 3; mem:ST8[%arr132]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W10<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5]
> %X8<def> = LDRXui %X8<kill>, 7; mem:LD8[%bzalloc33]
> %X0<def> = LDRXui %X9<kill>, 9; mem:LD8[%opaque34]
> %W9<def> = ADDWri %W10<kill>, 34, 0, %X9<imp-def>
> %X1<def> = SBFMXri %X9<kill>, 62, 31
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %W2<def> = MOVi32imm 1
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %W1<def> = COPY %W1, %X1<imp-use,kill>
Deleting identity copy.
> BLR %X8<kill>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %W2<imp-use>, %X0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0
Deleting identity copy.
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 4, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X8<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6]
> STRXui %X0<kill>, %X8<kill>, 4; mem:ST8[%arr239]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X8<def> = LDRXui %X8<kill>, 7; mem:LD8[%bzalloc40]
> %X0<def> = LDRXui %X9<kill>, 9; mem:LD8[%opaque41]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %W1<def> = MOVi32imm 262148
> %W2<def> = MOVi32imm 1
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BLR %X8<kill>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %W2<imp-use>, %X0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0
Deleting identity copy.
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 5, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X8<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6]
> STRXui %X0<kill>, %X8<kill>, 5; mem:ST8[%ftab43]
> %X8<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6]
> %X8<def> = LDRXui %X8<kill>, 3; mem:LD8[%arr144]
> CBZX %X8<kill>, <BB#19>
3040B	BB#17: derived from LLVM BB %lor.lhs.false.47
	    Live Ins: %X19
	    Predecessors according to CFG: BB#16
3056B		%vreg148<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg148
3072B		%vreg147<def> = LDRXui %vreg148<kill>, 4; mem:LD8[%arr248] GPR64:%vreg147 GPR64common:%vreg148
3088B		CBZX %vreg147<kill>, <BB#19>; GPR64:%vreg147
	    Successors according to CFG: BB#19 BB#18
> %X8<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6]
> %X8<def> = LDRXui %X8<kill>, 4; mem:LD8[%arr248]
> CBZX %X8<kill>, <BB#19>
3104B	BB#18: derived from LLVM BB %lor.lhs.false.51
	    Live Ins: %X19
	    Predecessors according to CFG: BB#17
3120B		%vreg152<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg152
3136B		%vreg151<def> = LDRXui %vreg152<kill>, 5; mem:LD8[%ftab52] GPR64:%vreg151 GPR64common:%vreg152
3152B		CBNZX %vreg151<kill>, <BB#28>; GPR64:%vreg151
	    Successors according to CFG: BB#28 BB#19
> %X8<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6]
> %X8<def> = LDRXui %X8<kill>, 5; mem:LD8[%ftab52]
> CBNZX %X8<kill>, <BB#28>
3168B	BB#19: derived from LLVM BB %if.then.55
	    Live Ins: %X19
	    Predecessors according to CFG: BB#16 BB#17 BB#18
3184B		%vreg229<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg229
3200B		%vreg228<def> = LDRXui %vreg229<kill>, 3; mem:LD8[%arr156] GPR64:%vreg228 GPR64common:%vreg229
3216B		CBZX %vreg228<kill>, <BB#21>; GPR64:%vreg228
	    Successors according to CFG: BB#21 BB#20
> %X8<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6]
> %X8<def> = LDRXui %X8<kill>, 3; mem:LD8[%arr156]
> CBZX %X8<kill>, <BB#21>
3232B	BB#20: derived from LLVM BB %if.then.59
	    Live Ins: %X19
	    Predecessors according to CFG: BB#19
3248B		%vreg243<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg243
3280B		%vreg240<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg240
3312B		%vreg237<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg237
3316B		%vreg242<def> = LDRXui %vreg243<kill>, 8; mem:LD8[%bzfree60] GPR64:%vreg242 GPR64common:%vreg243
3320B		%vreg239<def> = LDRXui %vreg240<kill>, 9; mem:LD8[%opaque61] GPR64:%vreg239 GPR64common:%vreg240
3328B		%vreg234<def> = LDRXui %vreg237<kill>, 3; mem:LD8[%arr162] GPR64:%vreg234 GPR64common:%vreg237
3360B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3376B		%X0<def> = COPY %vreg239<kill>; GPR64:%vreg239
3392B		%X1<def> = COPY %vreg234<kill>; GPR64:%vreg234
3408B		BLR %vreg242<kill>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>; GPR64:%vreg242
3424B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3440B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3456B		STACKMAP 6, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1]
3472B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#21
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X10<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6]
> %X8<def> = LDRXui %X8<kill>, 8; mem:LD8[%bzfree60]
> %X0<def> = LDRXui %X9<kill>, 9; mem:LD8[%opaque61]
> %X1<def> = LDRXui %X10<kill>, 3; mem:LD8[%arr162]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X1<kill>
Deleting identity copy.
> BLR %X8<kill>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 6, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3488B	BB#21: derived from LLVM BB %if.end.63
	    Live Ins: %X19
	    Predecessors according to CFG: BB#19 BB#20
3504B		%vreg247<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg247
3520B		%vreg246<def> = LDRXui %vreg247<kill>, 4; mem:LD8[%arr264] GPR64:%vreg246 GPR64common:%vreg247
3536B		CBZX %vreg246<kill>, <BB#23>; GPR64:%vreg246
	    Successors according to CFG: BB#23 BB#22
> %X8<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6]
> %X8<def> = LDRXui %X8<kill>, 4; mem:LD8[%arr264]
> CBZX %X8<kill>, <BB#23>
3552B	BB#22: derived from LLVM BB %if.then.67
	    Live Ins: %X19
	    Predecessors according to CFG: BB#21
3568B		%vreg261<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg261
3600B		%vreg258<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg258
3632B		%vreg255<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg255
3636B		%vreg260<def> = LDRXui %vreg261<kill>, 8; mem:LD8[%bzfree68] GPR64:%vreg260 GPR64common:%vreg261
3640B		%vreg257<def> = LDRXui %vreg258<kill>, 9; mem:LD8[%opaque69] GPR64:%vreg257 GPR64common:%vreg258
3648B		%vreg252<def> = LDRXui %vreg255<kill>, 4; mem:LD8[%arr270] GPR64:%vreg252 GPR64common:%vreg255
3680B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3696B		%X0<def> = COPY %vreg257<kill>; GPR64:%vreg257
3712B		%X1<def> = COPY %vreg252<kill>; GPR64:%vreg252
3728B		BLR %vreg260<kill>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>; GPR64:%vreg260
3744B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3760B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3776B		STACKMAP 7, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1]
3792B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#23
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X10<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6]
> %X8<def> = LDRXui %X8<kill>, 8; mem:LD8[%bzfree68]
> %X0<def> = LDRXui %X9<kill>, 9; mem:LD8[%opaque69]
> %X1<def> = LDRXui %X10<kill>, 4; mem:LD8[%arr270]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X1<kill>
Deleting identity copy.
> BLR %X8<kill>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 7, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3808B	BB#23: derived from LLVM BB %if.end.71
	    Live Ins: %X19
	    Predecessors according to CFG: BB#21 BB#22
3824B		%vreg265<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg265
3840B		%vreg264<def> = LDRXui %vreg265<kill>, 5; mem:LD8[%ftab72] GPR64:%vreg264 GPR64common:%vreg265
3856B		CBZX %vreg264<kill>, <BB#25>; GPR64:%vreg264
	    Successors according to CFG: BB#25 BB#24
> %X8<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6]
> %X8<def> = LDRXui %X8<kill>, 5; mem:LD8[%ftab72]
> CBZX %X8<kill>, <BB#25>
3872B	BB#24: derived from LLVM BB %if.then.75
	    Live Ins: %X19
	    Predecessors according to CFG: BB#23
3888B		%vreg279<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg279
3920B		%vreg276<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg276
3952B		%vreg273<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg273
3956B		%vreg278<def> = LDRXui %vreg279<kill>, 8; mem:LD8[%bzfree76] GPR64:%vreg278 GPR64common:%vreg279
3960B		%vreg275<def> = LDRXui %vreg276<kill>, 9; mem:LD8[%opaque77] GPR64:%vreg275 GPR64common:%vreg276
3968B		%vreg270<def> = LDRXui %vreg273<kill>, 5; mem:LD8[%ftab78] GPR64:%vreg270 GPR64common:%vreg273
4000B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4016B		%X0<def> = COPY %vreg275<kill>; GPR64:%vreg275
4032B		%X1<def> = COPY %vreg270<kill>; GPR64:%vreg270
4048B		BLR %vreg278<kill>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>; GPR64:%vreg278
4064B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4080B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4096B		STACKMAP 8, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1]
4112B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#25
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X10<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6]
> %X8<def> = LDRXui %X8<kill>, 8; mem:LD8[%bzfree76]
> %X0<def> = LDRXui %X9<kill>, 9; mem:LD8[%opaque77]
> %X1<def> = LDRXui %X10<kill>, 5; mem:LD8[%ftab78]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X1<kill>
Deleting identity copy.
> BLR %X8<kill>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 8, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4128B	BB#25: derived from LLVM BB %if.end.79
	    Live Ins: %X19
	    Predecessors according to CFG: BB#23 BB#24
4144B		%vreg281<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64:%vreg281
4160B		CBZX %vreg281<kill>, <BB#27>; GPR64:%vreg281
	    Successors according to CFG: BB#27 BB#26
> %X8<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6]
> CBZX %X8<kill>, <BB#27>
4176B	BB#26: derived from LLVM BB %if.then.82
	    Live Ins: %X19
	    Predecessors according to CFG: BB#25
4192B		%vreg293<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg293
4224B		%vreg290<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg290
4232B		%vreg292<def> = LDRXui %vreg293<kill>, 8; mem:LD8[%bzfree83] GPR64:%vreg292 GPR64common:%vreg293
4240B		%vreg289<def> = LDRXui %vreg290<kill>, 9; mem:LD8[%opaque84] GPR64:%vreg289 GPR64common:%vreg290
4256B		%vreg286<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64:%vreg286
4288B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4304B		%X0<def> = COPY %vreg289<kill>; GPR64:%vreg289
4320B		%X1<def> = COPY %vreg286<kill>; GPR64:%vreg286
4336B		BLR %vreg292<kill>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>; GPR64:%vreg292
4352B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4368B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4384B		STACKMAP 9, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
4400B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#27
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X8<def> = LDRXui %X8<kill>, 8; mem:LD8[%bzfree83]
> %X0<def> = LDRXui %X9<kill>, 9; mem:LD8[%opaque84]
> %X1<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X1<kill>
Deleting identity copy.
> BLR %X8<kill>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 9, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4416B	BB#27: derived from LLVM BB %if.end.85
	    Live Ins: %X19
	    Predecessors according to CFG: BB#25 BB#26
4432B		%vreg294<def> = MOVi32imm 4294967293; GPR32:%vreg294
4448B		STRWui %vreg294<kill>, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg294
4464B		B <BB#29>
	    Successors according to CFG: BB#29
> %W8<def> = MOVi32imm 4294967293
> STRWui %W8<kill>, <fi#0>, 0; mem:ST4[FixedStack0]
> B <BB#29>
4480B	BB#28: derived from LLVM BB %if.end.86
	    Live Ins: %X19
	    Predecessors according to CFG: BB#18
4544B		%vreg225<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg225
4560B		STRWui %WZR, %vreg225<kill>, 165; mem:ST4[%blockNo] GPR64common:%vreg225
4576B		%vreg223<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg223
4584B		%vreg219<def> = MOVi32imm 2; GPR32:%vreg219
4592B		STRWui %vreg219, %vreg223<kill>, 3; mem:ST4[%state] GPR32:%vreg219 GPR64common:%vreg223
4608B		%vreg221<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg221
4624B		STRWui %vreg219<kill>, %vreg221<kill>, 2; mem:ST4[%mode] GPR32:%vreg219 GPR64common:%vreg221
4640B		%vreg218<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg218
4656B		STRWui %WZR, %vreg218<kill>, 163; mem:ST4[%combinedCRC] GPR64common:%vreg218
4672B		%vreg216<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg216
4688B		%vreg215<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg215
4704B		STRWui %vreg216<kill>, %vreg215<kill>, 166; mem:ST4[%blockSize100k87] GPR32:%vreg216 GPR64common:%vreg215
4720B		%vreg212<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg212
4768B		%vreg206<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg206
4776B		%vreg209<def> = MOVi32imm 100000; GPR32:%vreg209
4784B		%vreg211<def> = MADDWrrr %vreg209<kill>, %vreg212<kill>, %WZR; GPR32common:%vreg211 GPR32:%vreg209,%vreg212
4792B		%vreg208<def> = SUBWri %vreg211<kill>, 19, 0; GPR32common:%vreg208,%vreg211
4800B		STRWui %vreg208<kill>, %vreg206<kill>, 28; mem:ST4[%nblockMAX] GPR32common:%vreg208 GPR64common:%vreg206
4808B		%vreg203<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg203
4816B		%vreg202<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg202
4832B		STRWui %vreg203<kill>, %vreg202<kill>, 164; mem:ST4[%verbosity89] GPR32:%vreg203 GPR64common:%vreg202
4848B		%vreg199<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg199
4864B		%vreg198<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg198
4880B		STRWui %vreg199<kill>, %vreg198<kill>, 22; mem:ST4[%workFactor90] GPR32:%vreg199 GPR64common:%vreg198
4896B		%vreg195<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg195
4944B		%vreg190<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg190
4952B		%vreg192<def> = LDRXui %vreg195<kill>, 4; mem:LD8[%arr291] GPR64:%vreg192 GPR64common:%vreg195
4960B		STRXui %vreg192<kill>, %vreg190<kill>, 8; mem:ST8[%block] GPR64:%vreg192 GPR64common:%vreg190
4976B		%vreg187<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg187
5024B		%vreg182<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg182
5032B		%vreg184<def> = LDRXui %vreg187<kill>, 3; mem:LD8[%arr192] GPR64:%vreg184 GPR64common:%vreg187
5040B		STRXui %vreg184<kill>, %vreg182<kill>, 9; mem:ST8[%mtfv] GPR64:%vreg184 GPR64common:%vreg182
5056B		%vreg179<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg179
5072B		STRXui %XZR, %vreg179<kill>, 10; mem:ST8[%zbits] GPR64common:%vreg179
5088B		%vreg176<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg176
5120B		%vreg173<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg173
5128B		%vreg175<def> = LDRXui %vreg176<kill>, 3; mem:LD8[%arr193] GPR64:%vreg175 GPR64common:%vreg176
5136B		STRXui %vreg175<kill>, %vreg173<kill>, 7; mem:ST8[%ptr] GPR64:%vreg175 GPR64common:%vreg173
5152B		%vreg169<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64:%vreg169
5184B		%vreg167<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg167
5200B		STRXui %vreg169<kill>, %vreg167<kill>, 6; mem:ST8[%state94] GPR64:%vreg169 GPR64common:%vreg167
5216B		%vreg164<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg164
5232B		STRWui %WZR, %vreg164<kill>, 3; mem:ST4[%total_in_lo32] GPR64common:%vreg164
5248B		%vreg162<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg162
5264B		STRWui %WZR, %vreg162<kill>, 4; mem:ST4[%total_in_hi32] GPR64common:%vreg162
5280B		%vreg160<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg160
5296B		STRWui %WZR, %vreg160<kill>, 9; mem:ST4[%total_out_lo32] GPR64common:%vreg160
5312B		%vreg158<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg158
5328B		STRWui %WZR, %vreg158<kill>, 10; mem:ST4[%total_out_hi32] GPR64common:%vreg158
5344B		%vreg156<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64:%vreg156
5360B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5376B		%X0<def> = COPY %vreg156<kill>; GPR64:%vreg156
5392B		BL <ga:@init_RL>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>
5408B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5424B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5440B		STACKMAP 10, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack6]
5456B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5472B		%vreg154<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64:%vreg154
5488B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5504B		%X0<def> = COPY %vreg154<kill>; GPR64:%vreg154
5520B		BL <ga:@prepare_new_block>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>
5536B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5552B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5568B		STACKMAP 11, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
5584B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5600B		STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
	    Successors according to CFG: BB#29
> %X8<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6]
> STRWui %WZR, %X8<kill>, 165; mem:ST4[%blockNo]
> %X8<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6]
> %W9<def> = MOVi32imm 2
> STRWui %W9, %X8<kill>, 3; mem:ST4[%state]
> %X8<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6]
> STRWui %W9<kill>, %X8<kill>, 2; mem:ST4[%mode]
> %X8<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6]
> STRWui %WZR, %X8<kill>, 163; mem:ST4[%combinedCRC]
> %W8<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2]
> %X9<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6]
> STRWui %W8<kill>, %X9<kill>, 166; mem:ST4[%blockSize100k87]
> %W8<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2]
> %X9<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6]
> %W10<def> = MOVi32imm 100000
> %W8<def> = MADDWrrr %W10<kill>, %W8<kill>, %WZR
> %W8<def> = SUBWri %W8<kill>, 19, 0
> STRWui %W8<kill>, %X9<kill>, 28; mem:ST4[%nblockMAX]
> %W8<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3]
> %X9<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6]
> STRWui %W8<kill>, %X9<kill>, 164; mem:ST4[%verbosity89]
> %W8<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4]
> %X9<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6]
> STRWui %W8<kill>, %X9<kill>, 22; mem:ST4[%workFactor90]
> %X8<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6]
> %X9<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6]
> %X8<def> = LDRXui %X8<kill>, 4; mem:LD8[%arr291]
> STRXui %X8<kill>, %X9<kill>, 8; mem:ST8[%block]
> %X8<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6]
> %X9<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6]
> %X8<def> = LDRXui %X8<kill>, 3; mem:LD8[%arr192]
> STRXui %X8<kill>, %X9<kill>, 9; mem:ST8[%mtfv]
> %X8<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6]
> STRXui %XZR, %X8<kill>, 10; mem:ST8[%zbits]
> %X8<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6]
> %X9<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6]
> %X8<def> = LDRXui %X8<kill>, 3; mem:LD8[%arr193]
> STRXui %X8<kill>, %X9<kill>, 7; mem:ST8[%ptr]
> %X8<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRXui %X8<kill>, %X9<kill>, 6; mem:ST8[%state94]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRWui %WZR, %X8<kill>, 3; mem:ST4[%total_in_lo32]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRWui %WZR, %X8<kill>, 4; mem:ST4[%total_in_hi32]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRWui %WZR, %X8<kill>, 9; mem:ST4[%total_out_lo32]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRWui %WZR, %X8<kill>, 10; mem:ST4[%total_out_hi32]
> %X0<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BL <ga:@init_RL>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 10, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack6]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BL <ga:@prepare_new_block>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 11, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
5616B	BB#29: derived from LLVM BB %return
	    Live Ins: %X19
	    Predecessors according to CFG: BB#1 BB#28 BB#27 BB#15 BB#7
5632B		%vreg299<def> = ADRP <ga:@BZ2_bzCompressInit>[TF=1]; GPR64common:%vreg299
5648B		%vreg301<def> = ADDXri %vreg299<kill>, <ga:@BZ2_bzCompressInit>[TF=34], 0; GPR64sp:%vreg301 GPR64common:%vreg299
5696B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5712B		%X0<def> = COPY %vreg301<kill>; GPR64sp:%vreg301
5728B		%X1<def> = COPY %vreg13<kill>; GPR64:%vreg13
5744B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
5760B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5776B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5792B		STACKMAP 12, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
5808B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5824B		%vreg298<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0] GPR32:%vreg298
5840B		%W0<def> = COPY %vreg298<kill>; GPR32:%vreg298
5856B		RET_ReallyLR %W0<imp-use>
> %X8<def> = ADRP <ga:@BZ2_bzCompressInit>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@BZ2_bzCompressInit>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19<kill>
> BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 12, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0]
> %W0<def> = COPY %W0<kill>
Deleting identity copy.
> RET_ReallyLR %W0<imp-use>
Computing live-in reg-units in ABI blocks.
0B	BB#0 W30#0
Created 1 new intervals.
********** INTERVALS **********
W30 [0B,16r:0)[144r,144d:1)[240e,240d:2)[336r,336d:3)[400e,400d:4)  0@0B-phi 1@144r 2@240e 3@336r 4@400e
%vreg0 [368r,432r:0)  0@368r
%vreg1 [176r,192r:0)  0@176r
%vreg2 [192r,208r:0)  0@192r
%vreg3 [208r,304r:0)  0@208r
%vreg4 [272r,320r:0)  0@272r
%vreg5 [16r,272r:0)  0@16r
%vreg6 [32r,48r:0)  0@32r
%vreg7 [48r,64r:0)  0@48r
%vreg8 [64r,112r:0)  0@64r
%vreg9 [80r,128r:0)  0@80r
RegMasks: 144r 336r
********** MACHINEINSTRS **********
# Machine code for function bz_config_ok: Post SSA
Function Live Ins: %LR in %vreg5

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %LR
16B		%vreg5<def> = COPY %LR; GPR64:%vreg5
32B		%vreg6<def> = ADRP <ga:@bz_config_ok>[TF=1]; GPR64common:%vreg6
48B		%vreg7<def> = ADDXri %vreg6, <ga:@bz_config_ok>[TF=34], 0; GPR64sp:%vreg7 GPR64common:%vreg6
64B		%vreg8<def> = COPY %vreg7; GPR64all:%vreg8 GPR64sp:%vreg7
80B		%vreg9<def> = COPY %vreg5; GPR64all:%vreg9 GPR64:%vreg5
96B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
112B		%X0<def> = COPY %vreg8; GPR64all:%vreg8
128B		%X1<def> = COPY %vreg9; GPR64all:%vreg9
144B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use,kill>, %X1<imp-use,kill>
160B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
176B		%vreg1<def> = ADRP <ga:@bz_config_ok>[TF=1]; GPR64common:%vreg1
192B		%vreg2<def> = ADDXri %vreg1, <ga:@bz_config_ok>[TF=34], 0; GPR64sp:%vreg2 GPR64common:%vreg1
208B		%vreg3<def> = COPY %vreg2; GPR64all:%vreg3 GPR64sp:%vreg2
224B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
240B		STACKMAP 0, 0, %LR<earlyclobber,imp-def,dead>, ...
256B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
272B		%vreg4<def> = COPY %vreg5; GPR64all:%vreg4 GPR64:%vreg5
288B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
304B		%X0<def> = COPY %vreg3; GPR64all:%vreg3
320B		%X1<def> = COPY %vreg4; GPR64all:%vreg4
336B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use,kill>, %X1<imp-use,kill>
352B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
368B		%vreg0<def> = MOVi32imm 1; GPR32:%vreg0
384B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
400B		STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...
416B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
432B		%W0<def> = COPY %vreg0; GPR32:%vreg0
448B		RET_ReallyLR %W0<imp-use,kill>

# End machine code for function bz_config_ok.

********** SIMPLE REGISTER COALESCING **********
********** Function: bz_config_ok
********** JOINING INTERVALS ***********
entry:
16B	%vreg5<def> = COPY %LR; GPR64:%vreg5
	Considering merging %vreg5 with %LR
	Can only merge into reserved registers.
112B	%X0<def> = COPY %vreg8; GPR64all:%vreg8
	Considering merging %vreg8 with %X0
	Can only merge into reserved registers.
128B	%X1<def> = COPY %vreg9; GPR64all:%vreg9
	Considering merging %vreg9 with %X1
	Can only merge into reserved registers.
304B	%X0<def> = COPY %vreg3; GPR64all:%vreg3
	Considering merging %vreg3 with %X0
	Can only merge into reserved registers.
320B	%X1<def> = COPY %vreg4; GPR64all:%vreg4
	Considering merging %vreg4 with %X1
	Can only merge into reserved registers.
432B	%W0<def> = COPY %vreg0; GPR32:%vreg0
	Considering merging %vreg0 with %W0
	Can only merge into reserved registers.
Remat: %W0<def> = MOVi32imm 1
Shrink: %vreg0 [368r,432r:0)  0@368r
All defs dead: 368r	%vreg0<def,dead> = MOVi32imm 1; GPR32:%vreg0
Shrunk: %vreg0 [368r,368d:0)  0@368r
Deleting dead def 368r	%vreg0<def,dead> = MOVi32imm 1; GPR32:%vreg0
64B	%vreg8<def> = COPY %vreg7; GPR64all:%vreg8 GPR64sp:%vreg7
	Considering merging to GPR64sp with %vreg7 in %vreg8
		RHS = %vreg7 [48r,64r:0)  0@48r
		LHS = %vreg8 [64r,112r:0)  0@64r
		merge %vreg8:0@64r into %vreg7:0@48r --> @48r
		erased:	64r	%vreg8<def> = COPY %vreg7; GPR64all:%vreg8 GPR64sp:%vreg7
		updated: 48B	%vreg8<def> = ADDXri %vreg6, <ga:@bz_config_ok>[TF=34], 0; GPR64sp:%vreg8 GPR64common:%vreg6
	Success: %vreg7 -> %vreg8
	Result = %vreg8 [48r,112r:0)  0@48r
80B	%vreg9<def> = COPY %vreg5; GPR64all:%vreg9 GPR64:%vreg5
	Considering merging to GPR64 with %vreg5 in %vreg9
		RHS = %vreg5 [16r,272r:0)  0@16r
		LHS = %vreg9 [80r,128r:0)  0@80r
		merge %vreg9:0@80r into %vreg5:0@16r --> @16r
		erased:	80r	%vreg9<def> = COPY %vreg5; GPR64all:%vreg9 GPR64:%vreg5
		updated: 16B	%vreg9<def> = COPY %LR; GPR64:%vreg9
		updated: 272B	%vreg4<def> = COPY %vreg9; GPR64all:%vreg4 GPR64:%vreg9
	Success: %vreg5 -> %vreg9
	Result = %vreg9 [16r,272r:0)  0@16r
208B	%vreg3<def> = COPY %vreg2; GPR64all:%vreg3 GPR64sp:%vreg2
	Considering merging to GPR64sp with %vreg2 in %vreg3
		RHS = %vreg2 [192r,208r:0)  0@192r
		LHS = %vreg3 [208r,304r:0)  0@208r
		merge %vreg3:0@208r into %vreg2:0@192r --> @192r
		erased:	208r	%vreg3<def> = COPY %vreg2; GPR64all:%vreg3 GPR64sp:%vreg2
		updated: 192B	%vreg3<def> = ADDXri %vreg1, <ga:@bz_config_ok>[TF=34], 0; GPR64sp:%vreg3 GPR64common:%vreg1
	Success: %vreg2 -> %vreg3
	Result = %vreg3 [192r,304r:0)  0@192r
272B	%vreg4<def> = COPY %vreg9; GPR64all:%vreg4 GPR64:%vreg9
	Considering merging to GPR64 with %vreg9 in %vreg4
		RHS = %vreg9 [16r,272r:0)  0@16r
		LHS = %vreg4 [272r,320r:0)  0@272r
		merge %vreg4:0@272r into %vreg9:0@16r --> @16r
		erased:	272r	%vreg4<def> = COPY %vreg9; GPR64all:%vreg4 GPR64:%vreg9
		updated: 16B	%vreg4<def> = COPY %LR; GPR64:%vreg4
		updated: 128B	%X1<def> = COPY %vreg4; GPR64:%vreg4
	Success: %vreg9 -> %vreg4
	Result = %vreg4 [16r,320r:0)  0@16r
112B	%X0<def> = COPY %vreg8; GPR64sp:%vreg8
	Considering merging %vreg8 with %X0
	Can only merge into reserved registers.
128B	%X1<def> = COPY %vreg4; GPR64:%vreg4
	Considering merging %vreg4 with %X1
	Can only merge into reserved registers.
304B	%X0<def> = COPY %vreg3; GPR64sp:%vreg3
	Considering merging %vreg3 with %X0
	Can only merge into reserved registers.
320B	%X1<def> = COPY %vreg4; GPR64:%vreg4
	Considering merging %vreg4 with %X1
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
W30 [0B,16r:0)[144r,144d:1)[240e,240d:2)[336r,336d:3)[400e,400d:4)  0@0B-phi 1@144r 2@240e 3@336r 4@400e
%vreg1 [176r,192r:0)  0@176r
%vreg3 [192r,304r:0)  0@192r
%vreg4 [16r,320r:0)  0@16r
%vreg6 [32r,48r:0)  0@32r
%vreg8 [48r,112r:0)  0@48r
RegMasks: 144r 336r
********** MACHINEINSTRS **********
# Machine code for function bz_config_ok: Post SSA
Function Live Ins: %LR in %vreg5

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %LR
16B		%vreg4<def> = COPY %LR; GPR64:%vreg4
32B		%vreg6<def> = ADRP <ga:@bz_config_ok>[TF=1]; GPR64common:%vreg6
48B		%vreg8<def> = ADDXri %vreg6, <ga:@bz_config_ok>[TF=34], 0; GPR64sp:%vreg8 GPR64common:%vreg6
96B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
112B		%X0<def> = COPY %vreg8; GPR64sp:%vreg8
128B		%X1<def> = COPY %vreg4; GPR64:%vreg4
144B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use,kill>, %X1<imp-use,kill>
160B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
176B		%vreg1<def> = ADRP <ga:@bz_config_ok>[TF=1]; GPR64common:%vreg1
192B		%vreg3<def> = ADDXri %vreg1, <ga:@bz_config_ok>[TF=34], 0; GPR64sp:%vreg3 GPR64common:%vreg1
224B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
240B		STACKMAP 0, 0, %LR<earlyclobber,imp-def,dead>, ...
256B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
288B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
304B		%X0<def> = COPY %vreg3; GPR64sp:%vreg3
320B		%X1<def> = COPY %vreg4; GPR64:%vreg4
336B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use,kill>, %X1<imp-use,kill>
352B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
384B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
400B		STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...
416B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
432B		%W0<def> = MOVi32imm 1
448B		RET_ReallyLR %W0<imp-use,kill>

# End machine code for function bz_config_ok.

********** GREEDY REGISTER ALLOCATION **********
********** Function: bz_config_ok
********** INTERVALS **********
W30 [0B,16r:0)[144r,144d:1)[240e,240d:2)[336r,336d:3)[400e,400d:4)  0@0B-phi 1@144r 2@240e 3@336r 4@400e
%vreg1 [176r,192r:0)  0@176r
%vreg3 [192r,304r:0)  0@192r
%vreg4 [16r,320r:0)  0@16r
%vreg6 [32r,48r:0)  0@32r
%vreg8 [48r,112r:0)  0@48r
RegMasks: 144r 336r
********** MACHINEINSTRS **********
# Machine code for function bz_config_ok: Post SSA
Function Live Ins: %LR in %vreg5

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %LR
16B		%vreg4<def> = COPY %LR; GPR64:%vreg4
32B		%vreg6<def> = ADRP <ga:@bz_config_ok>[TF=1]; GPR64common:%vreg6
48B		%vreg8<def> = ADDXri %vreg6, <ga:@bz_config_ok>[TF=34], 0; GPR64sp:%vreg8 GPR64common:%vreg6
96B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
112B		%X0<def> = COPY %vreg8; GPR64sp:%vreg8
128B		%X1<def> = COPY %vreg4; GPR64:%vreg4
144B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use,kill>, %X1<imp-use,kill>
160B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
176B		%vreg1<def> = ADRP <ga:@bz_config_ok>[TF=1]; GPR64common:%vreg1
192B		%vreg3<def> = ADDXri %vreg1, <ga:@bz_config_ok>[TF=34], 0; GPR64sp:%vreg3 GPR64common:%vreg1
224B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
240B		STACKMAP 0, 0, %LR<earlyclobber,imp-def,dead>, ...
256B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
288B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
304B		%X0<def> = COPY %vreg3; GPR64sp:%vreg3
320B		%X1<def> = COPY %vreg4; GPR64:%vreg4
336B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use,kill>, %X1<imp-use,kill>
352B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
384B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
400B		STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...
416B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
432B		%W0<def> = MOVi32imm 1
448B		RET_ReallyLR %W0<imp-use,kill>

# End machine code for function bz_config_ok.


selectOrSplit GPR64:%vreg4 [16r,320r:0)  0@16r w=4.303977e-03
hints: %X1
missed hint %X1
assigning %vreg4 to %X19: W19 [16r,320r:0)  0@16r

selectOrSplit GPR64sp:%vreg8 [48r,112r:0)  0@48r w=4.353448e-03
hints: %X0
assigning %vreg8 to %X0: W0 [48r,112r:0)  0@48r

selectOrSplit GPR64sp:%vreg3 [192r,304r:0)  0@192r w=3.945312e-03
hints: %X0
assigning %vreg3 to %X0: W0 [192r,304r:0)  0@192r

selectOrSplit GPR64common:%vreg6 [32r,48r:0)  0@32r w=inf
assigning %vreg6 to %X8: W8 [32r,48r:0)  0@32r

selectOrSplit GPR64common:%vreg1 [176r,192r:0)  0@176r w=inf
assigning %vreg1 to %X8: W8 [176r,192r:0)  0@176r

********** STACK TRANSFORMATION METADATA **********
********** Function: bz_config_ok
********** REGISTER MAP **********
[%vreg1 -> %X8] GPR64common
[%vreg3 -> %X0] GPR64sp
[%vreg4 -> %X19] GPR64
[%vreg6 -> %X8] GPR64common
[%vreg8 -> %X0] GPR64sp


Stackmap 0:
  STACKMAP 0, 0, %LR<earlyclobber,imp-def,dead>, ...


Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...


Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, %LR<earlyclobber,imp-def,dead>, ...
  -> Call instruction SlotIndex 144B, searching vregs 0 -> 10 and stack slots 0 -> 0
    + vreg4 is live in register but not in stackmap
      Defining instruction: %vreg4<def> = COPY %LR; GPR64:%vreg4
      Value: generated value, 1 instruction(s)

  STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...
  -> Call instruction SlotIndex 336B, searching vregs 0 -> 10 and stack slots 0 -> 0

********** REWRITE VIRTUAL REGISTERS **********
********** Function: bz_config_ok
********** REGISTER MAP **********
[%vreg1 -> %X8] GPR64common
[%vreg3 -> %X0] GPR64sp
[%vreg4 -> %X19] GPR64
[%vreg6 -> %X8] GPR64common
[%vreg8 -> %X0] GPR64sp

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %LR
16B		%vreg4<def> = COPY %LR; GPR64:%vreg4
32B		%vreg6<def> = ADRP <ga:@bz_config_ok>[TF=1]; GPR64common:%vreg6
48B		%vreg8<def> = ADDXri %vreg6<kill>, <ga:@bz_config_ok>[TF=34], 0; GPR64sp:%vreg8 GPR64common:%vreg6
96B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
112B		%X0<def> = COPY %vreg8<kill>; GPR64sp:%vreg8
128B		%X1<def> = COPY %vreg4; GPR64:%vreg4
144B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
160B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
176B		%vreg1<def> = ADRP <ga:@bz_config_ok>[TF=1]; GPR64common:%vreg1
192B		%vreg3<def> = ADDXri %vreg1<kill>, <ga:@bz_config_ok>[TF=34], 0; GPR64sp:%vreg3 GPR64common:%vreg1
224B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
240B		STACKMAP 0, 0, %LR<earlyclobber,imp-def,dead>, ...
256B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
288B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
304B		%X0<def> = COPY %vreg3<kill>; GPR64sp:%vreg3
320B		%X1<def> = COPY %vreg4<kill>; GPR64:%vreg4
336B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
352B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
384B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
400B		STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...
416B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
432B		%W0<def> = MOVi32imm 1
448B		RET_ReallyLR %W0<imp-use>
> %X19<def> = COPY %LR
> %X8<def> = ADRP <ga:@bz_config_ok>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@bz_config_ok>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19
> BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X8<def> = ADRP <ga:@bz_config_ok>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@bz_config_ok>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 0, 0, %LR<earlyclobber,imp-def,dead>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19<kill>
> BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = MOVi32imm 1
> RET_ReallyLR %W0<imp-use>
Computing live-in reg-units in ABI blocks.
0B	BB#0 W0#0 W1#0 W2#0 W30#0
Created 4 new intervals.
********** INTERVALS **********
W30 [0B,16r:0)[240r,240d:3)[288e,288d:2)[480r,480d:4)[592e,592d:1)[720r,720d:5)[768e,768d:6)  0@0B-phi 1@592e 2@288e 3@240r 4@480r 5@720r 6@768e
W0 [0B,64r:0)[208r,240r:1)[464r,480r:3)[480r,512r:2)[688r,720r:4)[800r,816r:5)  0@0B-phi 1@208r 2@480r 3@464r 4@688r 5@800r
W1 [0B,48r:0)[224r,240r:1)[704r,720r:2)  0@0B-phi 1@224r 2@704r
W2 [0B,32r:0)  0@0B-phi
%vreg0 [64r,80r:0)  0@64r
%vreg1 [80r,320r:0)  0@80r
%vreg2 [48r,96r:0)  0@48r
%vreg3 [96r,336r:0)  0@96r
%vreg4 [32r,112r:0)  0@32r
%vreg5 [112r,352r:0)  0@112r
%vreg7 [528r,544r:0)  0@528r
%vreg8 [544r,560r:0)  0@544r
%vreg9 [560r,688r:0)  0@560r
%vreg10 [656r,704r:0)  0@656r
%vreg11 [16r,656r:0)  0@16r
%vreg12 [640r,800r:0)  0@640r
%vreg15 [512r,624r:0)  0@512r
%vreg17 [416r,432r:0)  0@416r
%vreg18 [432r,464r:0)  0@432r
%vreg21 [400r,416r:0)  0@400r
%vreg22 [384r,400r:0)  0@384r
%vreg23 [368r,400r:0)  0@368r
%vreg24 [128r,144r:0)  0@128r
%vreg25 [144r,160r:0)  0@144r
%vreg26 [160r,208r:0)  0@160r
%vreg27 [176r,224r:0)  0@176r
RegMasks: 240r 480r 720r
********** MACHINEINSTRS **********
# Machine code for function default_bzalloc: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
  fi#1: size=4, align=4, at location [SP]
  fi#2: size=4, align=4, at location [SP]
  fi#3: size=8, align=8, at location [SP]
Function Live Ins: %X0 in %vreg0, %W1 in %vreg2, %W2 in %vreg4, %LR in %vreg11

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %W1 %W2 %LR
16B		%vreg11<def> = COPY %LR; GPR64:%vreg11
32B		%vreg4<def> = COPY %W2; GPR32:%vreg4
48B		%vreg2<def> = COPY %W1; GPR32:%vreg2
64B		%vreg0<def> = COPY %X0; GPR64:%vreg0
80B		%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
96B		%vreg3<def> = COPY %vreg2; GPR32:%vreg3,%vreg2
112B		%vreg5<def> = COPY %vreg4; GPR32:%vreg5,%vreg4
128B		%vreg24<def> = ADRP <ga:@default_bzalloc>[TF=1]; GPR64common:%vreg24
144B		%vreg25<def> = ADDXri %vreg24, <ga:@default_bzalloc>[TF=34], 0; GPR64sp:%vreg25 GPR64common:%vreg24
160B		%vreg26<def> = COPY %vreg25; GPR64all:%vreg26 GPR64sp:%vreg25
176B		%vreg27<def> = COPY %vreg11; GPR64all:%vreg27 GPR64:%vreg11
192B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
208B		%X0<def> = COPY %vreg26; GPR64all:%vreg26
224B		%X1<def> = COPY %vreg27; GPR64all:%vreg27
240B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
256B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
272B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
288B		STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, %vreg5, 0, <fi#2>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=4) LD8[FixedStack0] LD8[FixedStack2](align=4) LD8[FixedStack3] GPR32:%vreg3,%vreg5 GPR64:%vreg1
304B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
320B		STRXui %vreg1, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg1
336B		STRWui %vreg3, <fi#1>, 0; mem:ST4[FixedStack1] GPR32:%vreg3
352B		STRWui %vreg5, <fi#2>, 0; mem:ST4[FixedStack2] GPR32:%vreg5
368B		%vreg23<def> = LDRWui <fi#1>, 0; mem:LD4[FixedStack1] GPR32:%vreg23
384B		%vreg22<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg22
400B		%vreg21<def> = MADDWrrr %vreg23, %vreg22, %WZR; GPR32:%vreg21,%vreg23,%vreg22
416B		%vreg17<def> = SUBREG_TO_REG 0, %vreg21, 15; GPR64:%vreg17 GPR32:%vreg21
432B		%vreg18<def> = SBFMXri %vreg17, 0, 31; GPR64:%vreg18,%vreg17
448B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
464B		%X0<def> = COPY %vreg18; GPR64:%vreg18
480B		BL <ga:@malloc>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X0<imp-def>
496B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
512B		%vreg15<def> = COPY %X0; GPR64:%vreg15
528B		%vreg7<def> = ADRP <ga:@default_bzalloc>[TF=1]; GPR64common:%vreg7
544B		%vreg8<def> = ADDXri %vreg7, <ga:@default_bzalloc>[TF=34], 0; GPR64sp:%vreg8 GPR64common:%vreg7
560B		%vreg9<def> = COPY %vreg8; GPR64all:%vreg9 GPR64sp:%vreg8
576B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
592B		STACKMAP 1, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack3]
608B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
624B		STRXui %vreg15, <fi#3>, 0; mem:ST8[FixedStack3] GPR64:%vreg15
640B		%vreg12<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg12
656B		%vreg10<def> = COPY %vreg11; GPR64all:%vreg10 GPR64:%vreg11
672B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
688B		%X0<def> = COPY %vreg9; GPR64all:%vreg9
704B		%X1<def> = COPY %vreg10; GPR64all:%vreg10
720B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
736B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
752B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
768B		STACKMAP 2, 0, %vreg12, %LR<earlyclobber,imp-def,dead>, ...; GPR64:%vreg12
784B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
800B		%X0<def> = COPY %vreg12; GPR64:%vreg12
816B		RET_ReallyLR %X0<imp-use>

# End machine code for function default_bzalloc.

********** SIMPLE REGISTER COALESCING **********
********** Function: default_bzalloc
********** JOINING INTERVALS ***********
entry:
16B	%vreg11<def> = COPY %LR; GPR64:%vreg11
	Considering merging %vreg11 with %LR
	Can only merge into reserved registers.
32B	%vreg4<def> = COPY %W2; GPR32:%vreg4
	Considering merging %vreg4 with %W2
	Can only merge into reserved registers.
48B	%vreg2<def> = COPY %W1; GPR32:%vreg2
	Considering merging %vreg2 with %W1
	Can only merge into reserved registers.
64B	%vreg0<def> = COPY %X0; GPR64:%vreg0
	Considering merging %vreg0 with %X0
	Can only merge into reserved registers.
208B	%X0<def> = COPY %vreg26; GPR64all:%vreg26
	Considering merging %vreg26 with %X0
	Can only merge into reserved registers.
224B	%X1<def> = COPY %vreg27; GPR64all:%vreg27
	Considering merging %vreg27 with %X1
	Can only merge into reserved registers.
416B	%vreg17<def> = SUBREG_TO_REG 0, %vreg21, 15; GPR64:%vreg17 GPR32:%vreg21
	Considering merging to GPR64 with %vreg21 in %vreg17:sub_32
		RHS = %vreg21 [400r,416r:0)  0@400r
		LHS = %vreg17 [416r,432r:0)  0@416r
		merge %vreg17:0@416r into %vreg21:0@400r --> @400r
		erased:	416r	%vreg17<def> = SUBREG_TO_REG 0, %vreg21, 15; GPR64:%vreg17 GPR32:%vreg21
		updated: 400B	%vreg17:sub_32<def,read-undef> = MADDWrrr %vreg23, %vreg22, %WZR; GPR64:%vreg17 GPR32:%vreg23,%vreg22
	Success: %vreg21:sub_32 -> %vreg17
	Result = %vreg17 [400r,432r:0)  0@400r
464B	%X0<def> = COPY %vreg18; GPR64:%vreg18
	Considering merging %vreg18 with %X0
	Can only merge into reserved registers.
512B	%vreg15<def> = COPY %X0; GPR64:%vreg15
	Considering merging %vreg15 with %X0
	Can only merge into reserved registers.
688B	%X0<def> = COPY %vreg9; GPR64all:%vreg9
	Considering merging %vreg9 with %X0
	Can only merge into reserved registers.
704B	%X1<def> = COPY %vreg10; GPR64all:%vreg10
	Considering merging %vreg10 with %X1
	Can only merge into reserved registers.
800B	%X0<def> = COPY %vreg12; GPR64:%vreg12
	Considering merging %vreg12 with %X0
	Can only merge into reserved registers.
80B	%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
	Considering merging to GPR64 with %vreg0 in %vreg1
		RHS = %vreg0 [64r,80r:0)  0@64r
		LHS = %vreg1 [80r,320r:0)  0@80r
		merge %vreg1:0@80r into %vreg0:0@64r --> @64r
		erased:	80r	%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
		updated: 64B	%vreg1<def> = COPY %X0; GPR64:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [64r,320r:0)  0@64r
96B	%vreg3<def> = COPY %vreg2; GPR32:%vreg3,%vreg2
	Considering merging to GPR32 with %vreg2 in %vreg3
		RHS = %vreg2 [48r,96r:0)  0@48r
		LHS = %vreg3 [96r,336r:0)  0@96r
		merge %vreg3:0@96r into %vreg2:0@48r --> @48r
		erased:	96r	%vreg3<def> = COPY %vreg2; GPR32:%vreg3,%vreg2
		updated: 48B	%vreg3<def> = COPY %W1; GPR32:%vreg3
	Success: %vreg2 -> %vreg3
	Result = %vreg3 [48r,336r:0)  0@48r
112B	%vreg5<def> = COPY %vreg4; GPR32:%vreg5,%vreg4
	Considering merging to GPR32 with %vreg4 in %vreg5
		RHS = %vreg4 [32r,112r:0)  0@32r
		LHS = %vreg5 [112r,352r:0)  0@112r
		merge %vreg5:0@112r into %vreg4:0@32r --> @32r
		erased:	112r	%vreg5<def> = COPY %vreg4; GPR32:%vreg5,%vreg4
		updated: 32B	%vreg5<def> = COPY %W2; GPR32:%vreg5
	Success: %vreg4 -> %vreg5
	Result = %vreg5 [32r,352r:0)  0@32r
160B	%vreg26<def> = COPY %vreg25; GPR64all:%vreg26 GPR64sp:%vreg25
	Considering merging to GPR64sp with %vreg25 in %vreg26
		RHS = %vreg25 [144r,160r:0)  0@144r
		LHS = %vreg26 [160r,208r:0)  0@160r
		merge %vreg26:0@160r into %vreg25:0@144r --> @144r
		erased:	160r	%vreg26<def> = COPY %vreg25; GPR64all:%vreg26 GPR64sp:%vreg25
		updated: 144B	%vreg26<def> = ADDXri %vreg24, <ga:@default_bzalloc>[TF=34], 0; GPR64sp:%vreg26 GPR64common:%vreg24
	Success: %vreg25 -> %vreg26
	Result = %vreg26 [144r,208r:0)  0@144r
176B	%vreg27<def> = COPY %vreg11; GPR64all:%vreg27 GPR64:%vreg11
	Considering merging to GPR64 with %vreg11 in %vreg27
		RHS = %vreg11 [16r,656r:0)  0@16r
		LHS = %vreg27 [176r,224r:0)  0@176r
		merge %vreg27:0@176r into %vreg11:0@16r --> @16r
		erased:	176r	%vreg27<def> = COPY %vreg11; GPR64all:%vreg27 GPR64:%vreg11
		updated: 16B	%vreg27<def> = COPY %LR; GPR64:%vreg27
		updated: 656B	%vreg10<def> = COPY %vreg27; GPR64all:%vreg10 GPR64:%vreg27
	Success: %vreg11 -> %vreg27
	Result = %vreg27 [16r,656r:0)  0@16r
560B	%vreg9<def> = COPY %vreg8; GPR64all:%vreg9 GPR64sp:%vreg8
	Considering merging to GPR64sp with %vreg8 in %vreg9
		RHS = %vreg8 [544r,560r:0)  0@544r
		LHS = %vreg9 [560r,688r:0)  0@560r
		merge %vreg9:0@560r into %vreg8:0@544r --> @544r
		erased:	560r	%vreg9<def> = COPY %vreg8; GPR64all:%vreg9 GPR64sp:%vreg8
		updated: 544B	%vreg9<def> = ADDXri %vreg7, <ga:@default_bzalloc>[TF=34], 0; GPR64sp:%vreg9 GPR64common:%vreg7
	Success: %vreg8 -> %vreg9
	Result = %vreg9 [544r,688r:0)  0@544r
656B	%vreg10<def> = COPY %vreg27; GPR64all:%vreg10 GPR64:%vreg27
	Considering merging to GPR64 with %vreg27 in %vreg10
		RHS = %vreg27 [16r,656r:0)  0@16r
		LHS = %vreg10 [656r,704r:0)  0@656r
		merge %vreg10:0@656r into %vreg27:0@16r --> @16r
		erased:	656r	%vreg10<def> = COPY %vreg27; GPR64all:%vreg10 GPR64:%vreg27
		updated: 16B	%vreg10<def> = COPY %LR; GPR64:%vreg10
		updated: 224B	%X1<def> = COPY %vreg10; GPR64:%vreg10
	Success: %vreg27 -> %vreg10
	Result = %vreg10 [16r,704r:0)  0@16r
208B	%X0<def> = COPY %vreg26; GPR64sp:%vreg26
	Considering merging %vreg26 with %X0
	Can only merge into reserved registers.
224B	%X1<def> = COPY %vreg10; GPR64:%vreg10
	Considering merging %vreg10 with %X1
	Can only merge into reserved registers.
688B	%X0<def> = COPY %vreg9; GPR64sp:%vreg9
	Considering merging %vreg9 with %X0
	Can only merge into reserved registers.
704B	%X1<def> = COPY %vreg10; GPR64:%vreg10
	Considering merging %vreg10 with %X1
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
W30 [0B,16r:0)[240r,240d:3)[288e,288d:2)[480r,480d:4)[592e,592d:1)[720r,720d:5)[768e,768d:6)  0@0B-phi 1@592e 2@288e 3@240r 4@480r 5@720r 6@768e
W0 [0B,64r:0)[208r,240r:1)[464r,480r:3)[480r,512r:2)[688r,720r:4)[800r,816r:5)  0@0B-phi 1@208r 2@480r 3@464r 4@688r 5@800r
W1 [0B,48r:0)[224r,240r:1)[704r,720r:2)  0@0B-phi 1@224r 2@704r
W2 [0B,32r:0)  0@0B-phi
%vreg1 [64r,320r:0)  0@64r
%vreg3 [48r,336r:0)  0@48r
%vreg5 [32r,352r:0)  0@32r
%vreg7 [528r,544r:0)  0@528r
%vreg9 [544r,688r:0)  0@544r
%vreg10 [16r,704r:0)  0@16r
%vreg12 [640r,800r:0)  0@640r
%vreg15 [512r,624r:0)  0@512r
%vreg17 [400r,432r:0)  0@400r
%vreg18 [432r,464r:0)  0@432r
%vreg22 [384r,400r:0)  0@384r
%vreg23 [368r,400r:0)  0@368r
%vreg24 [128r,144r:0)  0@128r
%vreg26 [144r,208r:0)  0@144r
RegMasks: 240r 480r 720r
********** MACHINEINSTRS **********
# Machine code for function default_bzalloc: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
  fi#1: size=4, align=4, at location [SP]
  fi#2: size=4, align=4, at location [SP]
  fi#3: size=8, align=8, at location [SP]
Function Live Ins: %X0 in %vreg0, %W1 in %vreg2, %W2 in %vreg4, %LR in %vreg11

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %W1 %W2 %LR
16B		%vreg10<def> = COPY %LR; GPR64:%vreg10
32B		%vreg5<def> = COPY %W2; GPR32:%vreg5
48B		%vreg3<def> = COPY %W1; GPR32:%vreg3
64B		%vreg1<def> = COPY %X0; GPR64:%vreg1
128B		%vreg24<def> = ADRP <ga:@default_bzalloc>[TF=1]; GPR64common:%vreg24
144B		%vreg26<def> = ADDXri %vreg24, <ga:@default_bzalloc>[TF=34], 0; GPR64sp:%vreg26 GPR64common:%vreg24
192B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
208B		%X0<def> = COPY %vreg26; GPR64sp:%vreg26
224B		%X1<def> = COPY %vreg10; GPR64:%vreg10
240B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
256B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
272B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
288B		STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, %vreg5, 0, <fi#2>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=4) LD8[FixedStack0] LD8[FixedStack2](align=4) LD8[FixedStack3] GPR32:%vreg3,%vreg5 GPR64:%vreg1
304B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
320B		STRXui %vreg1, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg1
336B		STRWui %vreg3, <fi#1>, 0; mem:ST4[FixedStack1] GPR32:%vreg3
352B		STRWui %vreg5, <fi#2>, 0; mem:ST4[FixedStack2] GPR32:%vreg5
368B		%vreg23<def> = LDRWui <fi#1>, 0; mem:LD4[FixedStack1] GPR32:%vreg23
384B		%vreg22<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg22
400B		%vreg17:sub_32<def,read-undef> = MADDWrrr %vreg23, %vreg22, %WZR; GPR64:%vreg17 GPR32:%vreg23,%vreg22
432B		%vreg18<def> = SBFMXri %vreg17, 0, 31; GPR64:%vreg18,%vreg17
448B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
464B		%X0<def> = COPY %vreg18; GPR64:%vreg18
480B		BL <ga:@malloc>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X0<imp-def>
496B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
512B		%vreg15<def> = COPY %X0; GPR64:%vreg15
528B		%vreg7<def> = ADRP <ga:@default_bzalloc>[TF=1]; GPR64common:%vreg7
544B		%vreg9<def> = ADDXri %vreg7, <ga:@default_bzalloc>[TF=34], 0; GPR64sp:%vreg9 GPR64common:%vreg7
576B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
592B		STACKMAP 1, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack3]
608B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
624B		STRXui %vreg15, <fi#3>, 0; mem:ST8[FixedStack3] GPR64:%vreg15
640B		%vreg12<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg12
672B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
688B		%X0<def> = COPY %vreg9; GPR64sp:%vreg9
704B		%X1<def> = COPY %vreg10; GPR64:%vreg10
720B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
736B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
752B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
768B		STACKMAP 2, 0, %vreg12, %LR<earlyclobber,imp-def,dead>, ...; GPR64:%vreg12
784B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
800B		%X0<def> = COPY %vreg12; GPR64:%vreg12
816B		RET_ReallyLR %X0<imp-use>

# End machine code for function default_bzalloc.

********** GREEDY REGISTER ALLOCATION **********
********** Function: default_bzalloc
********** INTERVALS **********
W30 [0B,16r:0)[240r,240d:3)[288e,288d:2)[480r,480d:4)[592e,592d:1)[720r,720d:5)[768e,768d:6)  0@0B-phi 1@592e 2@288e 3@240r 4@480r 5@720r 6@768e
W0 [0B,64r:0)[208r,240r:1)[464r,480r:3)[480r,512r:2)[688r,720r:4)[800r,816r:5)  0@0B-phi 1@208r 2@480r 3@464r 4@688r 5@800r
W1 [0B,48r:0)[224r,240r:1)[704r,720r:2)  0@0B-phi 1@224r 2@704r
W2 [0B,32r:0)  0@0B-phi
%vreg1 [64r,320r:0)  0@64r
%vreg3 [48r,336r:0)  0@48r
%vreg5 [32r,352r:0)  0@32r
%vreg7 [528r,544r:0)  0@528r
%vreg9 [544r,688r:0)  0@544r
%vreg10 [16r,704r:0)  0@16r
%vreg12 [640r,800r:0)  0@640r
%vreg15 [512r,624r:0)  0@512r
%vreg17 [400r,432r:0)  0@400r
%vreg18 [432r,464r:0)  0@432r
%vreg22 [384r,400r:0)  0@384r
%vreg23 [368r,400r:0)  0@368r
%vreg24 [128r,144r:0)  0@128r
%vreg26 [144r,208r:0)  0@144r
RegMasks: 240r 480r 720r
********** MACHINEINSTRS **********
# Machine code for function default_bzalloc: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
  fi#1: size=4, align=4, at location [SP]
  fi#2: size=4, align=4, at location [SP]
  fi#3: size=8, align=8, at location [SP]
Function Live Ins: %X0 in %vreg0, %W1 in %vreg2, %W2 in %vreg4, %LR in %vreg11

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %W1 %W2 %LR
16B		%vreg10<def> = COPY %LR; GPR64:%vreg10
32B		%vreg5<def> = COPY %W2; GPR32:%vreg5
48B		%vreg3<def> = COPY %W1; GPR32:%vreg3
64B		%vreg1<def> = COPY %X0; GPR64:%vreg1
128B		%vreg24<def> = ADRP <ga:@default_bzalloc>[TF=1]; GPR64common:%vreg24
144B		%vreg26<def> = ADDXri %vreg24, <ga:@default_bzalloc>[TF=34], 0; GPR64sp:%vreg26 GPR64common:%vreg24
192B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
208B		%X0<def> = COPY %vreg26; GPR64sp:%vreg26
224B		%X1<def> = COPY %vreg10; GPR64:%vreg10
240B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
256B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
272B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
288B		STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, %vreg5, 0, <fi#2>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=4) LD8[FixedStack0] LD8[FixedStack2](align=4) LD8[FixedStack3] GPR32:%vreg3,%vreg5 GPR64:%vreg1
304B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
320B		STRXui %vreg1, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg1
336B		STRWui %vreg3, <fi#1>, 0; mem:ST4[FixedStack1] GPR32:%vreg3
352B		STRWui %vreg5, <fi#2>, 0; mem:ST4[FixedStack2] GPR32:%vreg5
368B		%vreg23<def> = LDRWui <fi#1>, 0; mem:LD4[FixedStack1] GPR32:%vreg23
384B		%vreg22<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg22
400B		%vreg17:sub_32<def,read-undef> = MADDWrrr %vreg23, %vreg22, %WZR; GPR64:%vreg17 GPR32:%vreg23,%vreg22
432B		%vreg18<def> = SBFMXri %vreg17, 0, 31; GPR64:%vreg18,%vreg17
448B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
464B		%X0<def> = COPY %vreg18; GPR64:%vreg18
480B		BL <ga:@malloc>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X0<imp-def>
496B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
512B		%vreg15<def> = COPY %X0; GPR64:%vreg15
528B		%vreg7<def> = ADRP <ga:@default_bzalloc>[TF=1]; GPR64common:%vreg7
544B		%vreg9<def> = ADDXri %vreg7, <ga:@default_bzalloc>[TF=34], 0; GPR64sp:%vreg9 GPR64common:%vreg7
576B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
592B		STACKMAP 1, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack3]
608B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
624B		STRXui %vreg15, <fi#3>, 0; mem:ST8[FixedStack3] GPR64:%vreg15
640B		%vreg12<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg12
672B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
688B		%X0<def> = COPY %vreg9; GPR64sp:%vreg9
704B		%X1<def> = COPY %vreg10; GPR64:%vreg10
720B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
736B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
752B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
768B		STACKMAP 2, 0, %vreg12, %LR<earlyclobber,imp-def,dead>, ...; GPR64:%vreg12
784B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
800B		%X0<def> = COPY %vreg12; GPR64:%vreg12
816B		RET_ReallyLR %X0<imp-use>

# End machine code for function default_bzalloc.


selectOrSplit GPR64:%vreg10 [16r,704r:0)  0@16r w=2.784926e-03
hints: %X1
missed hint %X1
assigning %vreg10 to %X19: W19 [16r,704r:0)  0@16r

selectOrSplit GPR32:%vreg5 [32r,352r:0)  0@32r w=4.208333e-03
hints: %W2
missed hint %W2
assigning %vreg5 to %W20: W20 [32r,352r:0)  0@32r

selectOrSplit GPR32:%vreg3 [48r,336r:0)  0@48r w=4.404070e-03
hints: %W1
missed hint %W1
assigning %vreg3 to %W21: W21 [48r,336r:0)  0@48r

selectOrSplit GPR64:%vreg1 [64r,320r:0)  0@64r w=4.618902e-03
hints: %X0
missed hint %X0
assigning %vreg1 to %X22: W22 [64r,320r:0)  0@64r

selectOrSplit GPR64sp:%vreg26 [144r,208r:0)  0@144r w=4.353448e-03
hints: %X0
assigning %vreg26 to %X0: W0 [144r,208r:0)  0@144r

selectOrSplit GPR64:%vreg18 [432r,464r:0)  0@432r w=4.675926e-03
hints: %X0
assigning %vreg18 to %X0: W0 [432r,464r:0)  0@432r

selectOrSplit GPR64:%vreg15 [512r,624r:0)  0@512r w=3.945312e-03
hints: %X0
assigning %vreg15 to %X0: W0 [512r,624r:0)  0@512r

selectOrSplit GPR64sp:%vreg9 [544r,688r:0)  0@544r w=3.713235e-03
hints: %X0
missed hint %X0
assigning %vreg9 to %X8: W8 [544r,688r:0)  0@544r

selectOrSplit GPR64:%vreg12 [640r,800r:0)  0@640r w=5.410714e-03
hints: %X0
missed hint %X0
assigning %vreg12 to %X20: W20 [640r,800r:0)  0@640r

selectOrSplit GPR64common:%vreg24 [128r,144r:0)  0@128r w=inf
assigning %vreg24 to %X8: W8 [128r,144r:0)  0@128r

selectOrSplit GPR32:%vreg23 [368r,400r:0)  0@368r w=4.629630e-03
assigning %vreg23 to %W8: W8 [368r,400r:0)  0@368r

selectOrSplit GPR32:%vreg22 [384r,400r:0)  0@384r w=inf
assigning %vreg22 to %W9: W9 [384r,400r:0)  0@384r

selectOrSplit GPR64:%vreg17 [400r,432r:0)  0@400r w=inf
assigning %vreg17 to %X8: W8 [400r,432r:0)  0@400r

selectOrSplit GPR64common:%vreg7 [528r,544r:0)  0@528r w=inf
assigning %vreg7 to %X8: W8 [528r,544r:0)  0@528r

********** STACK TRANSFORMATION METADATA **********
********** Function: default_bzalloc
********** REGISTER MAP **********
[%vreg1 -> %X22] GPR64
[%vreg3 -> %W21] GPR32
[%vreg5 -> %W20] GPR32
[%vreg7 -> %X8] GPR64common
[%vreg9 -> %X8] GPR64sp
[%vreg10 -> %X19] GPR64
[%vreg12 -> %X20] GPR64
[%vreg15 -> %X0] GPR64
[%vreg17 -> %X8] GPR64
[%vreg18 -> %X0] GPR64
[%vreg22 -> %W9] GPR32
[%vreg23 -> %W8] GPR32
[%vreg24 -> %X8] GPR64common
[%vreg26 -> %X0] GPR64sp


Stackmap 0:
  STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, %vreg5, 0, <fi#2>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=4) LD8[FixedStack0] LD8[FixedStack2](align=4) LD8[FixedStack3] GPR32:%vreg3,%vreg5 GPR64:%vreg1

i32 %items: in register %W21 (vreg 3)
i32* %items.addr: in stack slot 1 (size: 4)
i8* %opaque: in register %X22 (vreg 1)
i8** %opaque.addr: in stack slot 0 (size: 8)
i32 %size: in register %W20 (vreg 5)
i32* %size.addr: in stack slot 2 (size: 4)
i8** %v: in stack slot 3 (size: 8)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack3]

i8** %v: in stack slot 3 (size: 8)

Duplicate operand locations:


Stackmap 2:
  STACKMAP 2, 0, %vreg12, %LR<earlyclobber,imp-def,dead>, ...; GPR64:%vreg12

i8* %2: in register %X20 (vreg 12)

Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, %vreg5, 0, <fi#2>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=4) LD8[FixedStack0] LD8[FixedStack2](align=4) LD8[FixedStack3] GPR32:%vreg3,%vreg5 GPR64:%vreg1
  -> Call instruction SlotIndex 240B, searching vregs 0 -> 28 and stack slots 0 -> 4
    + vreg10 is live in register but not in stackmap
      Defining instruction: %vreg10<def> = COPY %LR; GPR64:%vreg10
      Value: generated value, 1 instruction(s)

  STACKMAP 1, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack3]
  -> Call instruction SlotIndex 480B, searching vregs 0 -> 28 and stack slots 0 -> 4
    + vreg10 is live in register but not in stackmap
      Defining instruction: %vreg10<def> = COPY %LR; GPR64:%vreg10
      Value: generated value, 1 instruction(s)

  STACKMAP 2, 0, %vreg12, %LR<earlyclobber,imp-def,dead>, ...; GPR64:%vreg12
  -> Call instruction SlotIndex 720B, searching vregs 0 -> 28 and stack slots 0 -> 4

********** REWRITE VIRTUAL REGISTERS **********
********** Function: default_bzalloc
********** REGISTER MAP **********
[%vreg1 -> %X22] GPR64
[%vreg3 -> %W21] GPR32
[%vreg5 -> %W20] GPR32
[%vreg7 -> %X8] GPR64common
[%vreg9 -> %X8] GPR64sp
[%vreg10 -> %X19] GPR64
[%vreg12 -> %X20] GPR64
[%vreg15 -> %X0] GPR64
[%vreg17 -> %X8] GPR64
[%vreg18 -> %X0] GPR64
[%vreg22 -> %W9] GPR32
[%vreg23 -> %W8] GPR32
[%vreg24 -> %X8] GPR64common
[%vreg26 -> %X0] GPR64sp

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %LR %W1 %W2 %X0
16B		%vreg10<def> = COPY %LR; GPR64:%vreg10
32B		%vreg5<def> = COPY %W2; GPR32:%vreg5
48B		%vreg3<def> = COPY %W1; GPR32:%vreg3
64B		%vreg1<def> = COPY %X0; GPR64:%vreg1
128B		%vreg24<def> = ADRP <ga:@default_bzalloc>[TF=1]; GPR64common:%vreg24
144B		%vreg26<def> = ADDXri %vreg24<kill>, <ga:@default_bzalloc>[TF=34], 0; GPR64sp:%vreg26 GPR64common:%vreg24
192B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
208B		%X0<def> = COPY %vreg26<kill>; GPR64sp:%vreg26
224B		%X1<def> = COPY %vreg10; GPR64:%vreg10
240B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
256B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
272B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
288B		STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, %vreg5, 0, <fi#2>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=4) LD8[FixedStack0] LD8[FixedStack2](align=4) LD8[FixedStack3] GPR32:%vreg3,%vreg5 GPR64:%vreg1
304B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
320B		STRXui %vreg1<kill>, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg1
336B		STRWui %vreg3<kill>, <fi#1>, 0; mem:ST4[FixedStack1] GPR32:%vreg3
352B		STRWui %vreg5<kill>, <fi#2>, 0; mem:ST4[FixedStack2] GPR32:%vreg5
368B		%vreg23<def> = LDRWui <fi#1>, 0; mem:LD4[FixedStack1] GPR32:%vreg23
384B		%vreg22<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg22
400B		%vreg17:sub_32<def,read-undef> = MADDWrrr %vreg23<kill>, %vreg22<kill>, %WZR; GPR64:%vreg17 GPR32:%vreg23,%vreg22
432B		%vreg18<def> = SBFMXri %vreg17<kill>, 0, 31; GPR64:%vreg18,%vreg17
448B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
464B		%X0<def> = COPY %vreg18<kill>; GPR64:%vreg18
480B		BL <ga:@malloc>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X0<imp-def>
496B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
512B		%vreg15<def> = COPY %X0; GPR64:%vreg15
528B		%vreg7<def> = ADRP <ga:@default_bzalloc>[TF=1]; GPR64common:%vreg7
544B		%vreg9<def> = ADDXri %vreg7<kill>, <ga:@default_bzalloc>[TF=34], 0; GPR64sp:%vreg9 GPR64common:%vreg7
576B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
592B		STACKMAP 1, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack3]
608B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
624B		STRXui %vreg15<kill>, <fi#3>, 0; mem:ST8[FixedStack3] GPR64:%vreg15
640B		%vreg12<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg12
672B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
688B		%X0<def> = COPY %vreg9<kill>; GPR64sp:%vreg9
704B		%X1<def> = COPY %vreg10<kill>; GPR64:%vreg10
720B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
736B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
752B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
768B		STACKMAP 2, 0, %vreg12, %LR<earlyclobber,imp-def,dead>, ...; GPR64:%vreg12
784B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
800B		%X0<def> = COPY %vreg12<kill>; GPR64:%vreg12
816B		RET_ReallyLR %X0<imp-use>
> %X19<def> = COPY %LR
> %W20<def> = COPY %W2
> %W21<def> = COPY %W1
> %X22<def> = COPY %X0
> %X8<def> = ADRP <ga:@default_bzalloc>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@default_bzalloc>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19
> BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 0, 0, %W21, 0, <fi#1>, 0, %X22, 0, <fi#0>, 0, %W20, 0, <fi#2>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=4) LD8[FixedStack0] LD8[FixedStack2](align=4) LD8[FixedStack3]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRXui %X22<kill>, <fi#0>, 0; mem:ST8[FixedStack0]
> STRWui %W21<kill>, <fi#1>, 0; mem:ST4[FixedStack1]
> STRWui %W20<kill>, <fi#2>, 0; mem:ST4[FixedStack2]
> %W8<def> = LDRWui <fi#1>, 0; mem:LD4[FixedStack1]
> %W9<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2]
> %W8<def> = MADDWrrr %W8<kill>, %W9<kill>, %WZR, %X8<imp-def>
> %X0<def> = SBFMXri %X8<kill>, 0, 31
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BL <ga:@malloc>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0
Deleting identity copy.
> %X8<def> = ADRP <ga:@default_bzalloc>[TF=1]
> %X8<def> = ADDXri %X8<kill>, <ga:@default_bzalloc>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 1, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack3]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRXui %X0<kill>, <fi#3>, 0; mem:ST8[FixedStack3]
> %X20<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X8<kill>
> %X1<def> = COPY %X19<kill>
> BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 2, 0, %X20, %LR<earlyclobber,imp-def,dead>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X20<kill>
> RET_ReallyLR %X0<imp-use>
Computing live-in reg-units in ABI blocks.
0B	BB#0 W0#0 W1#0 W30#0
Created 3 new intervals.
********** INTERVALS **********
W30 [0B,16r:0)[208r,208d:6)[256e,256d:1)[416r,416d:4)[464e,464d:5)[624r,624d:2)[672e,672d:3)  0@0B-phi 1@256e 2@624r 3@672e 4@416r 5@464e 6@208r
W0 [0B,48r:0)[176r,208r:3)[400r,416r:2)[592r,624r:1)  0@0B-phi 1@592r 2@400r 3@176r
W1 [0B,32r:0)[192r,208r:2)[608r,624r:1)  0@0B-phi 1@608r 2@192r
%vreg0 [48r,64r:0)  0@48r
%vreg1 [64r,288r:0)  0@64r
%vreg2 [32r,80r:0)  0@32r
%vreg3 [80r,304r:0)  0@80r
%vreg5 [320r,336r:0)  0@320r
%vreg6 [96r,112r:0)  0@96r
%vreg7 [112r,128r:0)  0@112r
%vreg8 [128r,176r:0)  0@128r
%vreg9 [144r,192r:0)  0@144r
%vreg10 [16r,560r:0)  0@16r
%vreg12 [368r,400r:0)  0@368r
%vreg13 [512r,528r:0)  0@512r
%vreg14 [528r,544r:0)  0@528r
%vreg15 [544r,592r:0)  0@544r
%vreg16 [560r,608r:0)  0@560r
RegMasks: 208r 416r 624r
********** MACHINEINSTRS **********
# Machine code for function default_bzfree: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
  fi#1: size=8, align=8, at location [SP]
Function Live Ins: %X0 in %vreg0, %X1 in %vreg2, %LR in %vreg10

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %X1 %LR
16B		%vreg10<def> = COPY %LR; GPR64:%vreg10
32B		%vreg2<def> = COPY %X1; GPR64:%vreg2
48B		%vreg0<def> = COPY %X0; GPR64:%vreg0
64B		%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
80B		%vreg3<def> = COPY %vreg2; GPR64:%vreg3,%vreg2
96B		%vreg6<def> = ADRP <ga:@default_bzfree>[TF=1]; GPR64common:%vreg6
112B		%vreg7<def> = ADDXri %vreg6, <ga:@default_bzfree>[TF=34], 0; GPR64sp:%vreg7 GPR64common:%vreg6
128B		%vreg8<def> = COPY %vreg7; GPR64all:%vreg8 GPR64sp:%vreg7
144B		%vreg9<def> = COPY %vreg10; GPR64all:%vreg9 GPR64:%vreg10
160B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
176B		%X0<def> = COPY %vreg8; GPR64all:%vreg8
192B		%X1<def> = COPY %vreg9; GPR64all:%vreg9
208B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
224B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
240B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
256B		STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack0] GPR64:%vreg3,%vreg1
272B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
288B		STRXui %vreg1, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg1
304B		STRXui %vreg3, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg3
320B		%vreg5<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg5
336B		CBZX %vreg5, <BB#2>; GPR64:%vreg5
	    Successors according to CFG: BB#2 BB#1

352B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
368B		%vreg12<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg12
384B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
400B		%X0<def> = COPY %vreg12; GPR64:%vreg12
416B		BL <ga:@free>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>
432B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
448B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
464B		STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...
480B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#2

496B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#1
512B		%vreg13<def> = ADRP <ga:@default_bzfree>[TF=1]; GPR64common:%vreg13
528B		%vreg14<def> = ADDXri %vreg13, <ga:@default_bzfree>[TF=34], 0; GPR64sp:%vreg14 GPR64common:%vreg13
544B		%vreg15<def> = COPY %vreg14; GPR64all:%vreg15 GPR64sp:%vreg14
560B		%vreg16<def> = COPY %vreg10; GPR64all:%vreg16 GPR64:%vreg10
576B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
592B		%X0<def> = COPY %vreg15; GPR64all:%vreg15
608B		%X1<def> = COPY %vreg16; GPR64all:%vreg16
624B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
640B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
656B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
672B		STACKMAP 2, 0, %LR<earlyclobber,imp-def,dead>, ...
688B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
704B		RET_ReallyLR

# End machine code for function default_bzfree.

********** SIMPLE REGISTER COALESCING **********
********** Function: default_bzfree
********** JOINING INTERVALS ***********
entry:
16B	%vreg10<def> = COPY %LR; GPR64:%vreg10
	Considering merging %vreg10 with %LR
	Can only merge into reserved registers.
32B	%vreg2<def> = COPY %X1; GPR64:%vreg2
	Considering merging %vreg2 with %X1
	Can only merge into reserved registers.
48B	%vreg0<def> = COPY %X0; GPR64:%vreg0
	Considering merging %vreg0 with %X0
	Can only merge into reserved registers.
176B	%X0<def> = COPY %vreg8; GPR64all:%vreg8
	Considering merging %vreg8 with %X0
	Can only merge into reserved registers.
192B	%X1<def> = COPY %vreg9; GPR64all:%vreg9
	Considering merging %vreg9 with %X1
	Can only merge into reserved registers.
if.then:
400B	%X0<def> = COPY %vreg12; GPR64:%vreg12
	Considering merging %vreg12 with %X0
	Can only merge into reserved registers.
if.end:
592B	%X0<def> = COPY %vreg15; GPR64all:%vreg15
	Considering merging %vreg15 with %X0
	Can only merge into reserved registers.
608B	%X1<def> = COPY %vreg16; GPR64all:%vreg16
	Considering merging %vreg16 with %X1
	Can only merge into reserved registers.
64B	%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
	Considering merging to GPR64 with %vreg0 in %vreg1
		RHS = %vreg0 [48r,64r:0)  0@48r
		LHS = %vreg1 [64r,288r:0)  0@64r
		merge %vreg1:0@64r into %vreg0:0@48r --> @48r
		erased:	64r	%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
		updated: 48B	%vreg1<def> = COPY %X0; GPR64:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [48r,288r:0)  0@48r
80B	%vreg3<def> = COPY %vreg2; GPR64:%vreg3,%vreg2
	Considering merging to GPR64 with %vreg2 in %vreg3
		RHS = %vreg2 [32r,80r:0)  0@32r
		LHS = %vreg3 [80r,304r:0)  0@80r
		merge %vreg3:0@80r into %vreg2:0@32r --> @32r
		erased:	80r	%vreg3<def> = COPY %vreg2; GPR64:%vreg3,%vreg2
		updated: 32B	%vreg3<def> = COPY %X1; GPR64:%vreg3
	Success: %vreg2 -> %vreg3
	Result = %vreg3 [32r,304r:0)  0@32r
128B	%vreg8<def> = COPY %vreg7; GPR64all:%vreg8 GPR64sp:%vreg7
	Considering merging to GPR64sp with %vreg7 in %vreg8
		RHS = %vreg7 [112r,128r:0)  0@112r
		LHS = %vreg8 [128r,176r:0)  0@128r
		merge %vreg8:0@128r into %vreg7:0@112r --> @112r
		erased:	128r	%vreg8<def> = COPY %vreg7; GPR64all:%vreg8 GPR64sp:%vreg7
		updated: 112B	%vreg8<def> = ADDXri %vreg6, <ga:@default_bzfree>[TF=34], 0; GPR64sp:%vreg8 GPR64common:%vreg6
	Success: %vreg7 -> %vreg8
	Result = %vreg8 [112r,176r:0)  0@112r
144B	%vreg9<def> = COPY %vreg10; GPR64all:%vreg9 GPR64:%vreg10
	Considering merging to GPR64 with %vreg10 in %vreg9
		RHS = %vreg10 [16r,560r:0)  0@16r
		LHS = %vreg9 [144r,192r:0)  0@144r
		merge %vreg9:0@144r into %vreg10:0@16r --> @16r
		erased:	144r	%vreg9<def> = COPY %vreg10; GPR64all:%vreg9 GPR64:%vreg10
		updated: 16B	%vreg9<def> = COPY %LR; GPR64:%vreg9
		updated: 560B	%vreg16<def> = COPY %vreg9; GPR64all:%vreg16 GPR64:%vreg9
	Success: %vreg10 -> %vreg9
	Result = %vreg9 [16r,560r:0)  0@16r
544B	%vreg15<def> = COPY %vreg14; GPR64all:%vreg15 GPR64sp:%vreg14
	Considering merging to GPR64sp with %vreg14 in %vreg15
		RHS = %vreg14 [528r,544r:0)  0@528r
		LHS = %vreg15 [544r,592r:0)  0@544r
		merge %vreg15:0@544r into %vreg14:0@528r --> @528r
		erased:	544r	%vreg15<def> = COPY %vreg14; GPR64all:%vreg15 GPR64sp:%vreg14
		updated: 528B	%vreg15<def> = ADDXri %vreg13, <ga:@default_bzfree>[TF=34], 0; GPR64sp:%vreg15 GPR64common:%vreg13
	Success: %vreg14 -> %vreg15
	Result = %vreg15 [528r,592r:0)  0@528r
560B	%vreg16<def> = COPY %vreg9; GPR64all:%vreg16 GPR64:%vreg9
	Considering merging to GPR64 with %vreg9 in %vreg16
		RHS = %vreg9 [16r,560r:0)  0@16r
		LHS = %vreg16 [560r,608r:0)  0@560r
		merge %vreg16:0@560r into %vreg9:0@16r --> @16r
		erased:	560r	%vreg16<def> = COPY %vreg9; GPR64all:%vreg16 GPR64:%vreg9
		updated: 16B	%vreg16<def> = COPY %LR; GPR64:%vreg16
		updated: 192B	%X1<def> = COPY %vreg16; GPR64:%vreg16
	Success: %vreg9 -> %vreg16
	Result = %vreg16 [16r,608r:0)  0@16r
176B	%X0<def> = COPY %vreg8; GPR64sp:%vreg8
	Considering merging %vreg8 with %X0
	Can only merge into reserved registers.
192B	%X1<def> = COPY %vreg16; GPR64:%vreg16
	Considering merging %vreg16 with %X1
	Can only merge into reserved registers.
592B	%X0<def> = COPY %vreg15; GPR64sp:%vreg15
	Considering merging %vreg15 with %X0
	Can only merge into reserved registers.
608B	%X1<def> = COPY %vreg16; GPR64:%vreg16
	Considering merging %vreg16 with %X1
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
W30 [0B,16r:0)[208r,208d:6)[256e,256d:1)[416r,416d:4)[464e,464d:5)[624r,624d:2)[672e,672d:3)  0@0B-phi 1@256e 2@624r 3@672e 4@416r 5@464e 6@208r
W0 [0B,48r:0)[176r,208r:3)[400r,416r:2)[592r,624r:1)  0@0B-phi 1@592r 2@400r 3@176r
W1 [0B,32r:0)[192r,208r:2)[608r,624r:1)  0@0B-phi 1@608r 2@192r
%vreg1 [48r,288r:0)  0@48r
%vreg3 [32r,304r:0)  0@32r
%vreg5 [320r,336r:0)  0@320r
%vreg6 [96r,112r:0)  0@96r
%vreg8 [112r,176r:0)  0@112r
%vreg12 [368r,400r:0)  0@368r
%vreg13 [512r,528r:0)  0@512r
%vreg15 [528r,592r:0)  0@528r
%vreg16 [16r,608r:0)  0@16r
RegMasks: 208r 416r 624r
********** MACHINEINSTRS **********
# Machine code for function default_bzfree: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
  fi#1: size=8, align=8, at location [SP]
Function Live Ins: %X0 in %vreg0, %X1 in %vreg2, %LR in %vreg10

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %X1 %LR
16B		%vreg16<def> = COPY %LR; GPR64:%vreg16
32B		%vreg3<def> = COPY %X1; GPR64:%vreg3
48B		%vreg1<def> = COPY %X0; GPR64:%vreg1
96B		%vreg6<def> = ADRP <ga:@default_bzfree>[TF=1]; GPR64common:%vreg6
112B		%vreg8<def> = ADDXri %vreg6, <ga:@default_bzfree>[TF=34], 0; GPR64sp:%vreg8 GPR64common:%vreg6
160B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
176B		%X0<def> = COPY %vreg8; GPR64sp:%vreg8
192B		%X1<def> = COPY %vreg16; GPR64:%vreg16
208B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
224B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
240B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
256B		STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack0] GPR64:%vreg3,%vreg1
272B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
288B		STRXui %vreg1, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg1
304B		STRXui %vreg3, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg3
320B		%vreg5<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg5
336B		CBZX %vreg5, <BB#2>; GPR64:%vreg5
	    Successors according to CFG: BB#2 BB#1

352B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
368B		%vreg12<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg12
384B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
400B		%X0<def> = COPY %vreg12; GPR64:%vreg12
416B		BL <ga:@free>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>
432B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
448B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
464B		STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...
480B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#2

496B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#1
512B		%vreg13<def> = ADRP <ga:@default_bzfree>[TF=1]; GPR64common:%vreg13
528B		%vreg15<def> = ADDXri %vreg13, <ga:@default_bzfree>[TF=34], 0; GPR64sp:%vreg15 GPR64common:%vreg13
576B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
592B		%X0<def> = COPY %vreg15; GPR64sp:%vreg15
608B		%X1<def> = COPY %vreg16; GPR64:%vreg16
624B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
640B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
656B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
672B		STACKMAP 2, 0, %LR<earlyclobber,imp-def,dead>, ...
688B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
704B		RET_ReallyLR

# End machine code for function default_bzfree.

********** GREEDY REGISTER ALLOCATION **********
********** Function: default_bzfree
********** INTERVALS **********
W30 [0B,16r:0)[208r,208d:6)[256e,256d:1)[416r,416d:4)[464e,464d:5)[624r,624d:2)[672e,672d:3)  0@0B-phi 1@256e 2@624r 3@672e 4@416r 5@464e 6@208r
W0 [0B,48r:0)[176r,208r:3)[400r,416r:2)[592r,624r:1)  0@0B-phi 1@592r 2@400r 3@176r
W1 [0B,32r:0)[192r,208r:2)[608r,624r:1)  0@0B-phi 1@608r 2@192r
%vreg1 [48r,288r:0)  0@48r
%vreg3 [32r,304r:0)  0@32r
%vreg5 [320r,336r:0)  0@320r
%vreg6 [96r,112r:0)  0@96r
%vreg8 [112r,176r:0)  0@112r
%vreg12 [368r,400r:0)  0@368r
%vreg13 [512r,528r:0)  0@512r
%vreg15 [528r,592r:0)  0@528r
%vreg16 [16r,608r:0)  0@16r
RegMasks: 208r 416r 624r
********** MACHINEINSTRS **********
# Machine code for function default_bzfree: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
  fi#1: size=8, align=8, at location [SP]
Function Live Ins: %X0 in %vreg0, %X1 in %vreg2, %LR in %vreg10

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %X1 %LR
16B		%vreg16<def> = COPY %LR; GPR64:%vreg16
32B		%vreg3<def> = COPY %X1; GPR64:%vreg3
48B		%vreg1<def> = COPY %X0; GPR64:%vreg1
96B		%vreg6<def> = ADRP <ga:@default_bzfree>[TF=1]; GPR64common:%vreg6
112B		%vreg8<def> = ADDXri %vreg6, <ga:@default_bzfree>[TF=34], 0; GPR64sp:%vreg8 GPR64common:%vreg6
160B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
176B		%X0<def> = COPY %vreg8; GPR64sp:%vreg8
192B		%X1<def> = COPY %vreg16; GPR64:%vreg16
208B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
224B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
240B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
256B		STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack0] GPR64:%vreg3,%vreg1
272B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
288B		STRXui %vreg1, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg1
304B		STRXui %vreg3, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg3
320B		%vreg5<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg5
336B		CBZX %vreg5, <BB#2>; GPR64:%vreg5
	    Successors according to CFG: BB#2 BB#1

352B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
368B		%vreg12<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg12
384B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
400B		%X0<def> = COPY %vreg12; GPR64:%vreg12
416B		BL <ga:@free>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>
432B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
448B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
464B		STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...
480B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#2

496B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#1
512B		%vreg13<def> = ADRP <ga:@default_bzfree>[TF=1]; GPR64common:%vreg13
528B		%vreg15<def> = ADDXri %vreg13, <ga:@default_bzfree>[TF=34], 0; GPR64sp:%vreg15 GPR64common:%vreg13
576B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
592B		%X0<def> = COPY %vreg15; GPR64sp:%vreg15
608B		%X1<def> = COPY %vreg16; GPR64:%vreg16
624B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
640B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
656B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
672B		STACKMAP 2, 0, %LR<earlyclobber,imp-def,dead>, ...
688B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
704B		RET_ReallyLR

# End machine code for function default_bzfree.


selectOrSplit GPR64:%vreg16 [16r,608r:0)  0@16r w=3.054435e-03
hints: %X1
missed hint %X1
assigning %vreg16 to %X19: W19 [16r,608r:0)  0@16r

selectOrSplit GPR64:%vreg3 [32r,304r:0)  0@32r w=4.508928e-03
hints: %X1
missed hint %X1
assigning %vreg3 to %X20: W20 [32r,304r:0)  0@32r

selectOrSplit GPR64:%vreg1 [48r,288r:0)  0@48r w=4.734375e-03
hints: %X0
missed hint %X0
assigning %vreg1 to %X21: W21 [48r,288r:0)  0@48r

selectOrSplit GPR64sp:%vreg8 [112r,176r:0)  0@112r w=4.353448e-03
hints: %X0
assigning %vreg8 to %X0: W0 [112r,176r:0)  0@112r

selectOrSplit GPR64:%vreg12 [368r,400r:0)  0@368r w=2.337963e-03
hints: %X0
assigning %vreg12 to %X0: W0 [368r,400r:0)  0@368r

selectOrSplit GPR64sp:%vreg15 [528r,592r:0)  0@528r w=4.353448e-03
hints: %X0
assigning %vreg15 to %X0: W0 [528r,592r:0)  0@528r

selectOrSplit GPR64common:%vreg6 [96r,112r:0)  0@96r w=inf
assigning %vreg6 to %X8: W8 [96r,112r:0)  0@96r

selectOrSplit GPR64:%vreg5 [320r,336r:0)  0@320r w=inf
assigning %vreg5 to %X8: W8 [320r,336r:0)  0@320r

selectOrSplit GPR64common:%vreg13 [512r,528r:0)  0@512r w=inf
assigning %vreg13 to %X8: W8 [512r,528r:0)  0@512r

********** STACK TRANSFORMATION METADATA **********
********** Function: default_bzfree
********** REGISTER MAP **********
[%vreg1 -> %X21] GPR64
[%vreg3 -> %X20] GPR64
[%vreg5 -> %X8] GPR64
[%vreg6 -> %X8] GPR64common
[%vreg8 -> %X0] GPR64sp
[%vreg12 -> %X0] GPR64
[%vreg13 -> %X8] GPR64common
[%vreg15 -> %X0] GPR64sp
[%vreg16 -> %X19] GPR64


Stackmap 0:
  STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack0] GPR64:%vreg3,%vreg1

i8* %addr: in register %X20 (vreg 3)
i8** %addr.addr: in stack slot 1 (size: 8)
i8* %opaque: in register %X21 (vreg 1)
i8** %opaque.addr: in stack slot 0 (size: 8)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...


Duplicate operand locations:


Stackmap 2:
  STACKMAP 2, 0, %LR<earlyclobber,imp-def,dead>, ...


Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack0] GPR64:%vreg3,%vreg1
  -> Call instruction SlotIndex 208B, searching vregs 0 -> 17 and stack slots 0 -> 2
    + vreg16 is live in register but not in stackmap
      Defining instruction: %vreg16<def> = COPY %LR; GPR64:%vreg16
      Value: generated value, 1 instruction(s)

  STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...
  -> Call instruction SlotIndex 416B, searching vregs 0 -> 17 and stack slots 0 -> 2
    + vreg16 is live in register but not in stackmap
      Defining instruction: %vreg16<def> = COPY %LR; GPR64:%vreg16
      Value: generated value, 1 instruction(s)

  STACKMAP 2, 0, %LR<earlyclobber,imp-def,dead>, ...
  -> Call instruction SlotIndex 624B, searching vregs 0 -> 17 and stack slots 0 -> 2

********** REWRITE VIRTUAL REGISTERS **********
********** Function: default_bzfree
********** REGISTER MAP **********
[%vreg1 -> %X21] GPR64
[%vreg3 -> %X20] GPR64
[%vreg5 -> %X8] GPR64
[%vreg6 -> %X8] GPR64common
[%vreg8 -> %X0] GPR64sp
[%vreg12 -> %X0] GPR64
[%vreg13 -> %X8] GPR64common
[%vreg15 -> %X0] GPR64sp
[%vreg16 -> %X19] GPR64

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %LR %X0 %X1
16B		%vreg16<def> = COPY %LR; GPR64:%vreg16
32B		%vreg3<def> = COPY %X1; GPR64:%vreg3
48B		%vreg1<def> = COPY %X0; GPR64:%vreg1
96B		%vreg6<def> = ADRP <ga:@default_bzfree>[TF=1]; GPR64common:%vreg6
112B		%vreg8<def> = ADDXri %vreg6<kill>, <ga:@default_bzfree>[TF=34], 0; GPR64sp:%vreg8 GPR64common:%vreg6
160B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
176B		%X0<def> = COPY %vreg8<kill>; GPR64sp:%vreg8
192B		%X1<def> = COPY %vreg16; GPR64:%vreg16
208B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
224B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
240B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
256B		STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack0] GPR64:%vreg3,%vreg1
272B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
288B		STRXui %vreg1<kill>, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg1
304B		STRXui %vreg3<kill>, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg3
320B		%vreg5<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg5
336B		CBZX %vreg5<kill>, <BB#2>; GPR64:%vreg5
	    Successors according to CFG: BB#2 BB#1
> %X19<def> = COPY %LR
> %X20<def> = COPY %X1
> %X21<def> = COPY %X0
> %X8<def> = ADRP <ga:@default_bzfree>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@default_bzfree>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19
> BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 0, 0, %X20, 0, <fi#1>, 0, %X21, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack0]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRXui %X21<kill>, <fi#0>, 0; mem:ST8[FixedStack0]
> STRXui %X20<kill>, <fi#1>, 0; mem:ST8[FixedStack1]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> CBZX %X8<kill>, <BB#2>
352B	BB#1: derived from LLVM BB %if.then
	    Live Ins: %X19
	    Predecessors according to CFG: BB#0
368B		%vreg12<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg12
384B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
400B		%X0<def> = COPY %vreg12<kill>; GPR64:%vreg12
416B		BL <ga:@free>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>
432B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
448B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
464B		STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...
480B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#2
> %X0<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BL <ga:@free>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
496B	BB#2: derived from LLVM BB %if.end
	    Live Ins: %X19
	    Predecessors according to CFG: BB#0 BB#1
512B		%vreg13<def> = ADRP <ga:@default_bzfree>[TF=1]; GPR64common:%vreg13
528B		%vreg15<def> = ADDXri %vreg13<kill>, <ga:@default_bzfree>[TF=34], 0; GPR64sp:%vreg15 GPR64common:%vreg13
576B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
592B		%X0<def> = COPY %vreg15<kill>; GPR64sp:%vreg15
608B		%X1<def> = COPY %vreg16<kill>; GPR64:%vreg16
624B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
640B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
656B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
672B		STACKMAP 2, 0, %LR<earlyclobber,imp-def,dead>, ...
688B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
704B		RET_ReallyLR
> %X8<def> = ADRP <ga:@default_bzfree>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@default_bzfree>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19<kill>
> BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 2, 0, %LR<earlyclobber,imp-def,dead>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> RET_ReallyLR
Computing live-in reg-units in ABI blocks.
0B	BB#0 W0#0 W30#0
Created 2 new intervals.
********** INTERVALS **********
W30 [0B,16r:0)[176r,176d:2)[288e,288d:1)[464r,464d:3)[512e,512d:4)  0@0B-phi 1@288e 2@176r 3@464r 4@512e
W0 [0B,32r:0)[144r,176r:1)[432r,464r:2)  0@0B-phi 1@144r 2@432r
%vreg0 [32r,48r:0)  0@32r
%vreg1 [48r,320r:0)  0@48r
%vreg2 [208r,224r:0)  0@208r
%vreg3 [224r,240r:0)  0@224r
%vreg4 [240r,432r:0)  0@240r
%vreg5 [400r,448r:0)  0@400r
%vreg6 [16r,400r:0)  0@16r
%vreg8 [368r,384r:0)  0@368r
%vreg9 [256r,352r:0)  0@256r
%vreg11 [336r,352r:0)  0@336r
%vreg12 [64r,80r:0)  0@64r
%vreg13 [80r,96r:0)  0@80r
%vreg14 [96r,144r:0)  0@96r
%vreg15 [112r,160r:0)  0@112r
RegMasks: 176r 464r
********** MACHINEINSTRS **********
# Machine code for function init_RL: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
Function Live Ins: %X0 in %vreg0, %LR in %vreg6

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %LR
16B		%vreg6<def> = COPY %LR; GPR64:%vreg6
32B		%vreg0<def> = COPY %X0; GPR64:%vreg0
48B		%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
64B		%vreg12<def> = ADRP <ga:@init_RL>[TF=1]; GPR64common:%vreg12
80B		%vreg13<def> = ADDXri %vreg12, <ga:@init_RL>[TF=34], 0; GPR64sp:%vreg13 GPR64common:%vreg12
96B		%vreg14<def> = COPY %vreg13; GPR64all:%vreg14 GPR64sp:%vreg13
112B		%vreg15<def> = COPY %vreg6; GPR64all:%vreg15 GPR64:%vreg6
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		%X0<def> = COPY %vreg14; GPR64all:%vreg14
160B		%X1<def> = COPY %vreg15; GPR64all:%vreg15
176B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		%vreg2<def> = ADRP <ga:@init_RL>[TF=1]; GPR64common:%vreg2
224B		%vreg3<def> = ADDXri %vreg2, <ga:@init_RL>[TF=34], 0; GPR64sp:%vreg3 GPR64common:%vreg2
240B		%vreg4<def> = COPY %vreg3; GPR64all:%vreg4 GPR64sp:%vreg3
256B		%vreg9<def> = MOVi32imm 256; GPR32:%vreg9
272B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
288B		STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] GPR64:%vreg1
304B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
320B		STRXui %vreg1, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg1
336B		%vreg11<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg11
352B		STRWui %vreg9, %vreg11, 23; mem:ST4[%state_in_ch] GPR32:%vreg9 GPR64common:%vreg11
368B		%vreg8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg8
384B		STRWui %WZR, %vreg8, 24; mem:ST4[%state_in_len] GPR64common:%vreg8
400B		%vreg5<def> = COPY %vreg6; GPR64all:%vreg5 GPR64:%vreg6
416B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
432B		%X0<def> = COPY %vreg4; GPR64all:%vreg4
448B		%X1<def> = COPY %vreg5; GPR64all:%vreg5
464B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
480B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
496B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
512B		STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...
528B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
544B		RET_ReallyLR

# End machine code for function init_RL.

********** SIMPLE REGISTER COALESCING **********
********** Function: init_RL
********** JOINING INTERVALS ***********
entry:
16B	%vreg6<def> = COPY %LR; GPR64:%vreg6
	Considering merging %vreg6 with %LR
	Can only merge into reserved registers.
32B	%vreg0<def> = COPY %X0; GPR64:%vreg0
	Considering merging %vreg0 with %X0
	Can only merge into reserved registers.
144B	%X0<def> = COPY %vreg14; GPR64all:%vreg14
	Considering merging %vreg14 with %X0
	Can only merge into reserved registers.
160B	%X1<def> = COPY %vreg15; GPR64all:%vreg15
	Considering merging %vreg15 with %X1
	Can only merge into reserved registers.
432B	%X0<def> = COPY %vreg4; GPR64all:%vreg4
	Considering merging %vreg4 with %X0
	Can only merge into reserved registers.
448B	%X1<def> = COPY %vreg5; GPR64all:%vreg5
	Considering merging %vreg5 with %X1
	Can only merge into reserved registers.
48B	%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
	Considering merging to GPR64 with %vreg0 in %vreg1
		RHS = %vreg0 [32r,48r:0)  0@32r
		LHS = %vreg1 [48r,320r:0)  0@48r
		merge %vreg1:0@48r into %vreg0:0@32r --> @32r
		erased:	48r	%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
		updated: 32B	%vreg1<def> = COPY %X0; GPR64:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [32r,320r:0)  0@32r
96B	%vreg14<def> = COPY %vreg13; GPR64all:%vreg14 GPR64sp:%vreg13
	Considering merging to GPR64sp with %vreg13 in %vreg14
		RHS = %vreg13 [80r,96r:0)  0@80r
		LHS = %vreg14 [96r,144r:0)  0@96r
		merge %vreg14:0@96r into %vreg13:0@80r --> @80r
		erased:	96r	%vreg14<def> = COPY %vreg13; GPR64all:%vreg14 GPR64sp:%vreg13
		updated: 80B	%vreg14<def> = ADDXri %vreg12, <ga:@init_RL>[TF=34], 0; GPR64sp:%vreg14 GPR64common:%vreg12
	Success: %vreg13 -> %vreg14
	Result = %vreg14 [80r,144r:0)  0@80r
112B	%vreg15<def> = COPY %vreg6; GPR64all:%vreg15 GPR64:%vreg6
	Considering merging to GPR64 with %vreg6 in %vreg15
		RHS = %vreg6 [16r,400r:0)  0@16r
		LHS = %vreg15 [112r,160r:0)  0@112r
		merge %vreg15:0@112r into %vreg6:0@16r --> @16r
		erased:	112r	%vreg15<def> = COPY %vreg6; GPR64all:%vreg15 GPR64:%vreg6
		updated: 16B	%vreg15<def> = COPY %LR; GPR64:%vreg15
		updated: 400B	%vreg5<def> = COPY %vreg15; GPR64all:%vreg5 GPR64:%vreg15
	Success: %vreg6 -> %vreg15
	Result = %vreg15 [16r,400r:0)  0@16r
240B	%vreg4<def> = COPY %vreg3; GPR64all:%vreg4 GPR64sp:%vreg3
	Considering merging to GPR64sp with %vreg3 in %vreg4
		RHS = %vreg3 [224r,240r:0)  0@224r
		LHS = %vreg4 [240r,432r:0)  0@240r
		merge %vreg4:0@240r into %vreg3:0@224r --> @224r
		erased:	240r	%vreg4<def> = COPY %vreg3; GPR64all:%vreg4 GPR64sp:%vreg3
		updated: 224B	%vreg4<def> = ADDXri %vreg2, <ga:@init_RL>[TF=34], 0; GPR64sp:%vreg4 GPR64common:%vreg2
	Success: %vreg3 -> %vreg4
	Result = %vreg4 [224r,432r:0)  0@224r
400B	%vreg5<def> = COPY %vreg15; GPR64all:%vreg5 GPR64:%vreg15
	Considering merging to GPR64 with %vreg15 in %vreg5
		RHS = %vreg15 [16r,400r:0)  0@16r
		LHS = %vreg5 [400r,448r:0)  0@400r
		merge %vreg5:0@400r into %vreg15:0@16r --> @16r
		erased:	400r	%vreg5<def> = COPY %vreg15; GPR64all:%vreg5 GPR64:%vreg15
		updated: 16B	%vreg5<def> = COPY %LR; GPR64:%vreg5
		updated: 160B	%X1<def> = COPY %vreg5; GPR64:%vreg5
	Success: %vreg15 -> %vreg5
	Result = %vreg5 [16r,448r:0)  0@16r
144B	%X0<def> = COPY %vreg14; GPR64sp:%vreg14
	Considering merging %vreg14 with %X0
	Can only merge into reserved registers.
160B	%X1<def> = COPY %vreg5; GPR64:%vreg5
	Considering merging %vreg5 with %X1
	Can only merge into reserved registers.
432B	%X0<def> = COPY %vreg4; GPR64sp:%vreg4
	Considering merging %vreg4 with %X0
	Can only merge into reserved registers.
448B	%X1<def> = COPY %vreg5; GPR64:%vreg5
	Considering merging %vreg5 with %X1
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
W30 [0B,16r:0)[176r,176d:2)[288e,288d:1)[464r,464d:3)[512e,512d:4)  0@0B-phi 1@288e 2@176r 3@464r 4@512e
W0 [0B,32r:0)[144r,176r:1)[432r,464r:2)  0@0B-phi 1@144r 2@432r
%vreg1 [32r,320r:0)  0@32r
%vreg2 [208r,224r:0)  0@208r
%vreg4 [224r,432r:0)  0@224r
%vreg5 [16r,448r:0)  0@16r
%vreg8 [368r,384r:0)  0@368r
%vreg9 [256r,352r:0)  0@256r
%vreg11 [336r,352r:0)  0@336r
%vreg12 [64r,80r:0)  0@64r
%vreg14 [80r,144r:0)  0@80r
RegMasks: 176r 464r
********** MACHINEINSTRS **********
# Machine code for function init_RL: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
Function Live Ins: %X0 in %vreg0, %LR in %vreg6

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %LR
16B		%vreg5<def> = COPY %LR; GPR64:%vreg5
32B		%vreg1<def> = COPY %X0; GPR64:%vreg1
64B		%vreg12<def> = ADRP <ga:@init_RL>[TF=1]; GPR64common:%vreg12
80B		%vreg14<def> = ADDXri %vreg12, <ga:@init_RL>[TF=34], 0; GPR64sp:%vreg14 GPR64common:%vreg12
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		%X0<def> = COPY %vreg14; GPR64sp:%vreg14
160B		%X1<def> = COPY %vreg5; GPR64:%vreg5
176B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		%vreg2<def> = ADRP <ga:@init_RL>[TF=1]; GPR64common:%vreg2
224B		%vreg4<def> = ADDXri %vreg2, <ga:@init_RL>[TF=34], 0; GPR64sp:%vreg4 GPR64common:%vreg2
256B		%vreg9<def> = MOVi32imm 256; GPR32:%vreg9
272B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
288B		STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] GPR64:%vreg1
304B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
320B		STRXui %vreg1, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg1
336B		%vreg11<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg11
352B		STRWui %vreg9, %vreg11, 23; mem:ST4[%state_in_ch] GPR32:%vreg9 GPR64common:%vreg11
368B		%vreg8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg8
384B		STRWui %WZR, %vreg8, 24; mem:ST4[%state_in_len] GPR64common:%vreg8
416B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
432B		%X0<def> = COPY %vreg4; GPR64sp:%vreg4
448B		%X1<def> = COPY %vreg5; GPR64:%vreg5
464B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
480B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
496B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
512B		STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...
528B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
544B		RET_ReallyLR

# End machine code for function init_RL.

********** GREEDY REGISTER ALLOCATION **********
********** Function: init_RL
********** INTERVALS **********
W30 [0B,16r:0)[176r,176d:2)[288e,288d:1)[464r,464d:3)[512e,512d:4)  0@0B-phi 1@288e 2@176r 3@464r 4@512e
W0 [0B,32r:0)[144r,176r:1)[432r,464r:2)  0@0B-phi 1@144r 2@432r
%vreg1 [32r,320r:0)  0@32r
%vreg2 [208r,224r:0)  0@208r
%vreg4 [224r,432r:0)  0@224r
%vreg5 [16r,448r:0)  0@16r
%vreg8 [368r,384r:0)  0@368r
%vreg9 [256r,352r:0)  0@256r
%vreg11 [336r,352r:0)  0@336r
%vreg12 [64r,80r:0)  0@64r
%vreg14 [80r,144r:0)  0@80r
RegMasks: 176r 464r
********** MACHINEINSTRS **********
# Machine code for function init_RL: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
Function Live Ins: %X0 in %vreg0, %LR in %vreg6

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %LR
16B		%vreg5<def> = COPY %LR; GPR64:%vreg5
32B		%vreg1<def> = COPY %X0; GPR64:%vreg1
64B		%vreg12<def> = ADRP <ga:@init_RL>[TF=1]; GPR64common:%vreg12
80B		%vreg14<def> = ADDXri %vreg12, <ga:@init_RL>[TF=34], 0; GPR64sp:%vreg14 GPR64common:%vreg12
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		%X0<def> = COPY %vreg14; GPR64sp:%vreg14
160B		%X1<def> = COPY %vreg5; GPR64:%vreg5
176B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		%vreg2<def> = ADRP <ga:@init_RL>[TF=1]; GPR64common:%vreg2
224B		%vreg4<def> = ADDXri %vreg2, <ga:@init_RL>[TF=34], 0; GPR64sp:%vreg4 GPR64common:%vreg2
256B		%vreg9<def> = MOVi32imm 256; GPR32:%vreg9
272B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
288B		STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] GPR64:%vreg1
304B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
320B		STRXui %vreg1, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg1
336B		%vreg11<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg11
352B		STRWui %vreg9, %vreg11, 23; mem:ST4[%state_in_ch] GPR32:%vreg9 GPR64common:%vreg11
368B		%vreg8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg8
384B		STRWui %WZR, %vreg8, 24; mem:ST4[%state_in_len] GPR64common:%vreg8
416B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
432B		%X0<def> = COPY %vreg4; GPR64sp:%vreg4
448B		%X1<def> = COPY %vreg5; GPR64:%vreg5
464B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
480B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
496B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
512B		STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...
528B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
544B		RET_ReallyLR

# End machine code for function init_RL.


selectOrSplit GPR64:%vreg5 [16r,448r:0)  0@16r w=3.641827e-03
hints: %X1
missed hint %X1
assigning %vreg5 to %X19: W19 [16r,448r:0)  0@16r

selectOrSplit GPR64:%vreg1 [32r,320r:0)  0@32r w=4.404070e-03
hints: %X0
missed hint %X0
assigning %vreg1 to %X20: W20 [32r,320r:0)  0@32r

selectOrSplit GPR64sp:%vreg14 [80r,144r:0)  0@80r w=4.353448e-03
hints: %X0
assigning %vreg14 to %X0: W0 [80r,144r:0)  0@80r

selectOrSplit GPR64sp:%vreg4 [224r,432r:0)  0@224r w=3.322368e-03
hints: %X0
assigning %vreg4 to %X0: W0 [224r,432r:0)  0@224r

selectOrSplit GPR64common:%vreg12 [64r,80r:0)  0@64r w=inf
assigning %vreg12 to %X8: W8 [64r,80r:0)  0@64r

selectOrSplit GPR64common:%vreg2 [208r,224r:0)  0@208r w=inf
assigning %vreg2 to %X8: W8 [208r,224r:0)  0@208r

selectOrSplit GPR32:%vreg9 [256r,352r:0)  0@256r w=2.016129e-03
assigning %vreg9 to %W8: W8 [256r,352r:0)  0@256r

selectOrSplit GPR64common:%vreg11 [336r,352r:0)  0@336r w=inf
assigning %vreg11 to %X9: W9 [336r,352r:0)  0@336r

selectOrSplit GPR64common:%vreg8 [368r,384r:0)  0@368r w=inf
assigning %vreg8 to %X8: W8 [368r,384r:0)  0@368r

********** STACK TRANSFORMATION METADATA **********
********** Function: init_RL
********** REGISTER MAP **********
[%vreg1 -> %X20] GPR64
[%vreg2 -> %X8] GPR64common
[%vreg4 -> %X0] GPR64sp
[%vreg5 -> %X19] GPR64
[%vreg8 -> %X8] GPR64common
[%vreg9 -> %W8] GPR32
[%vreg11 -> %X9] GPR64common
[%vreg12 -> %X8] GPR64common
[%vreg14 -> %X0] GPR64sp


Stackmap 0:
  STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] GPR64:%vreg1

%struct.EState* %s: in register %X20 (vreg 1)
%struct.EState** %s.addr: in stack slot 0 (size: 8)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...


Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] GPR64:%vreg1
  -> Call instruction SlotIndex 176B, searching vregs 0 -> 16 and stack slots 0 -> 1
    + vreg5 is live in register but not in stackmap
      Defining instruction: %vreg5<def> = COPY %LR; GPR64:%vreg5
      Value: generated value, 1 instruction(s)

  STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...
  -> Call instruction SlotIndex 464B, searching vregs 0 -> 16 and stack slots 0 -> 1

********** REWRITE VIRTUAL REGISTERS **********
********** Function: init_RL
********** REGISTER MAP **********
[%vreg1 -> %X20] GPR64
[%vreg2 -> %X8] GPR64common
[%vreg4 -> %X0] GPR64sp
[%vreg5 -> %X19] GPR64
[%vreg8 -> %X8] GPR64common
[%vreg9 -> %W8] GPR32
[%vreg11 -> %X9] GPR64common
[%vreg12 -> %X8] GPR64common
[%vreg14 -> %X0] GPR64sp

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %LR %X0
16B		%vreg5<def> = COPY %LR; GPR64:%vreg5
32B		%vreg1<def> = COPY %X0; GPR64:%vreg1
64B		%vreg12<def> = ADRP <ga:@init_RL>[TF=1]; GPR64common:%vreg12
80B		%vreg14<def> = ADDXri %vreg12<kill>, <ga:@init_RL>[TF=34], 0; GPR64sp:%vreg14 GPR64common:%vreg12
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		%X0<def> = COPY %vreg14<kill>; GPR64sp:%vreg14
160B		%X1<def> = COPY %vreg5; GPR64:%vreg5
176B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		%vreg2<def> = ADRP <ga:@init_RL>[TF=1]; GPR64common:%vreg2
224B		%vreg4<def> = ADDXri %vreg2<kill>, <ga:@init_RL>[TF=34], 0; GPR64sp:%vreg4 GPR64common:%vreg2
256B		%vreg9<def> = MOVi32imm 256; GPR32:%vreg9
272B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
288B		STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] GPR64:%vreg1
304B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
320B		STRXui %vreg1<kill>, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg1
336B		%vreg11<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg11
352B		STRWui %vreg9<kill>, %vreg11<kill>, 23; mem:ST4[%state_in_ch] GPR32:%vreg9 GPR64common:%vreg11
368B		%vreg8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg8
384B		STRWui %WZR, %vreg8<kill>, 24; mem:ST4[%state_in_len] GPR64common:%vreg8
416B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
432B		%X0<def> = COPY %vreg4<kill>; GPR64sp:%vreg4
448B		%X1<def> = COPY %vreg5<kill>; GPR64:%vreg5
464B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
480B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
496B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
512B		STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...
528B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
544B		RET_ReallyLR
> %X19<def> = COPY %LR
> %X20<def> = COPY %X0
> %X8<def> = ADRP <ga:@init_RL>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@init_RL>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19
> BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X8<def> = ADRP <ga:@init_RL>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@init_RL>[TF=34], 0
> %W8<def> = MOVi32imm 256
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 0, 0, %X20, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRXui %X20<kill>, <fi#0>, 0; mem:ST8[FixedStack0]
> %X9<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> STRWui %W8<kill>, %X9<kill>, 23; mem:ST4[%state_in_ch]
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> STRWui %WZR, %X8<kill>, 24; mem:ST4[%state_in_len]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19<kill>
> BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> RET_ReallyLR
Computing live-in reg-units in ABI blocks.
0B	BB#0 W0#0 W30#0
Created 2 new intervals.
********** INTERVALS **********
W30 [0B,16r:0)[176r,176d:4)[240e,240d:1)[864r,864d:2)[912e,912d:3)  0@0B-phi 1@240e 2@864r 3@912e 4@176r
W0 [0B,32r:0)[144r,176r:2)[832r,864r:1)  0@0B-phi 1@832r 2@144r
%vreg0 [32r,48r:0)  0@32r
%vreg1 [48r,272r:0)  0@48r
%vreg2 [208r,400r:0)  0@208r
%vreg4 [384r,400r:0)  0@384r
%vreg6 [352r,368r:0)  0@352r
%vreg8 [320r,336r:0)  0@320r
%vreg10 [288r,304r:0)  0@288r
%vreg11 [64r,80r:0)  0@64r
%vreg12 [80r,96r:0)  0@80r
%vreg13 [96r,144r:0)  0@96r
%vreg14 [112r,160r:0)  0@112r
%vreg15 [16r,800r:0)  0@16r
%vreg17 [448r,464r:0)  0@448r
%vreg18 [688r,704r:0)  0@688r
%vreg19 [704r,720r:0)  0@704r
%vreg20 [720r,832r:0)  0@720r
%vreg21 [800r,848r:0)  0@800r
%vreg25 [768r,784r:0)  0@768r
%vreg26 [752r,768r:0)  0@752r
%vreg27 [736r,784r:0)  0@736r
%vreg31 [560r,576r:0)  0@560r
%vreg33 [544r,560r:0)  0@544r
%vreg34 [528r,544r:0)  0@528r
%vreg38 [512r,560r:0)  0@512r
%vreg41 [624r,640r:0)  0@624r
%vreg42 [608r,624r:0)  0@608r
RegMasks: 176r 864r
********** MACHINEINSTRS **********
# Machine code for function prepare_new_block: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
  fi#1: size=4, align=4, at location [SP]
Function Live Ins: %X0 in %vreg0, %LR in %vreg15

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %LR
16B		%vreg15<def> = COPY %LR; GPR64:%vreg15
32B		%vreg0<def> = COPY %X0; GPR64:%vreg0
48B		%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
64B		%vreg11<def> = ADRP <ga:@prepare_new_block>[TF=1]; GPR64common:%vreg11
80B		%vreg12<def> = ADDXri %vreg11, <ga:@prepare_new_block>[TF=34], 0; GPR64sp:%vreg12 GPR64common:%vreg11
96B		%vreg13<def> = COPY %vreg12; GPR64all:%vreg13 GPR64sp:%vreg12
112B		%vreg14<def> = COPY %vreg15; GPR64all:%vreg14 GPR64:%vreg15
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		%X0<def> = COPY %vreg13; GPR64all:%vreg13
160B		%X1<def> = COPY %vreg14; GPR64all:%vreg14
176B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		%vreg2<def> = MOVi32imm 4294967295; GPR32:%vreg2
224B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
240B		STACKMAP 0, 0, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=4) LD8[FixedStack0] GPR64:%vreg1
256B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
272B		STRXui %vreg1, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg1
288B		%vreg10<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg10
304B		STRWui %WZR, %vreg10, 27; mem:ST4[%nblock] GPR64common:%vreg10
320B		%vreg8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg8
336B		STRWui %WZR, %vreg8, 29; mem:ST4[%numZ] GPR64common:%vreg8
352B		%vreg6<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg6
368B		STRWui %WZR, %vreg6, 30; mem:ST4[%state_out_pos] GPR64common:%vreg6
384B		%vreg4<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg4
400B		STRWui %vreg2, %vreg4, 162; mem:ST4[%blockCRC] GPR32:%vreg2 GPR64common:%vreg4
416B		STRWui %WZR, <fi#1>, 0; mem:ST4[FixedStack1]
	    Successors according to CFG: BB#1

432B	BB#1: derived from LLVM BB %for.cond
	    Predecessors according to CFG: BB#0 BB#3
448B		%vreg17<def> = LDRWui <fi#1>, 0; mem:LD4[FixedStack1] GPR32common:%vreg17
464B		%WZR<def> = SUBSWri %vreg17, 256, 0, %NZCV<imp-def>; GPR32common:%vreg17
480B		Bcc 10, <BB#4>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#4 BB#2

496B	BB#2: derived from LLVM BB %for.body
	    Predecessors according to CFG: BB#1
512B		%vreg38<def> = LDRSWui <fi#1>, 0; mem:LD4[FixedStack1] GPR64:%vreg38
528B		%vreg34<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg34
544B		%vreg33<def> = ADDXri %vreg34, 128, 0; GPR64common:%vreg33,%vreg34
560B		%vreg31<def> = ADDXrr %vreg33, %vreg38; GPR64common:%vreg31,%vreg33 GPR64:%vreg38
576B		STRBBui %WZR, %vreg31, 0; mem:ST1[%arrayidx] GPR64common:%vreg31
	    Successors according to CFG: BB#3

592B	BB#3: derived from LLVM BB %for.inc
	    Predecessors according to CFG: BB#2
608B		%vreg42<def> = LDRWui <fi#1>, 0; mem:LD4[FixedStack1] GPR32common:%vreg42
624B		%vreg41<def> = ADDWri %vreg42, 1, 0; GPR32common:%vreg41,%vreg42
640B		STRWui %vreg41, <fi#1>, 0; mem:ST4[FixedStack1] GPR32common:%vreg41
656B		B <BB#1>
	    Successors according to CFG: BB#1

672B	BB#4: derived from LLVM BB %for.end
	    Predecessors according to CFG: BB#1
688B		%vreg18<def> = ADRP <ga:@prepare_new_block>[TF=1]; GPR64common:%vreg18
704B		%vreg19<def> = ADDXri %vreg18, <ga:@prepare_new_block>[TF=34], 0; GPR64sp:%vreg19 GPR64common:%vreg18
720B		%vreg20<def> = COPY %vreg19; GPR64all:%vreg20 GPR64sp:%vreg19
736B		%vreg27<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg27
752B		%vreg26<def> = LDRWui %vreg27, 165; mem:LD4[%blockNo] GPR32common:%vreg26 GPR64common:%vreg27
768B		%vreg25<def> = ADDWri %vreg26, 1, 0; GPR32common:%vreg25,%vreg26
784B		STRWui %vreg25, %vreg27, 165; mem:ST4[%blockNo] GPR32common:%vreg25 GPR64common:%vreg27
800B		%vreg21<def> = COPY %vreg15; GPR64all:%vreg21 GPR64:%vreg15
816B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
832B		%X0<def> = COPY %vreg20; GPR64all:%vreg20
848B		%X1<def> = COPY %vreg21; GPR64all:%vreg21
864B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
880B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
896B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
912B		STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...
928B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
944B		RET_ReallyLR

# End machine code for function prepare_new_block.

********** SIMPLE REGISTER COALESCING **********
********** Function: prepare_new_block
********** JOINING INTERVALS ***********
for.cond:
for.body:
for.inc:
entry:
16B	%vreg15<def> = COPY %LR; GPR64:%vreg15
	Considering merging %vreg15 with %LR
	Can only merge into reserved registers.
32B	%vreg0<def> = COPY %X0; GPR64:%vreg0
	Considering merging %vreg0 with %X0
	Can only merge into reserved registers.
144B	%X0<def> = COPY %vreg13; GPR64all:%vreg13
	Considering merging %vreg13 with %X0
	Can only merge into reserved registers.
160B	%X1<def> = COPY %vreg14; GPR64all:%vreg14
	Considering merging %vreg14 with %X1
	Can only merge into reserved registers.
for.end:
832B	%X0<def> = COPY %vreg20; GPR64all:%vreg20
	Considering merging %vreg20 with %X0
	Can only merge into reserved registers.
848B	%X1<def> = COPY %vreg21; GPR64all:%vreg21
	Considering merging %vreg21 with %X1
	Can only merge into reserved registers.
48B	%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
	Considering merging to GPR64 with %vreg0 in %vreg1
		RHS = %vreg0 [32r,48r:0)  0@32r
		LHS = %vreg1 [48r,272r:0)  0@48r
		merge %vreg1:0@48r into %vreg0:0@32r --> @32r
		erased:	48r	%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
		updated: 32B	%vreg1<def> = COPY %X0; GPR64:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [32r,272r:0)  0@32r
96B	%vreg13<def> = COPY %vreg12; GPR64all:%vreg13 GPR64sp:%vreg12
	Considering merging to GPR64sp with %vreg12 in %vreg13
		RHS = %vreg12 [80r,96r:0)  0@80r
		LHS = %vreg13 [96r,144r:0)  0@96r
		merge %vreg13:0@96r into %vreg12:0@80r --> @80r
		erased:	96r	%vreg13<def> = COPY %vreg12; GPR64all:%vreg13 GPR64sp:%vreg12
		updated: 80B	%vreg13<def> = ADDXri %vreg11, <ga:@prepare_new_block>[TF=34], 0; GPR64sp:%vreg13 GPR64common:%vreg11
	Success: %vreg12 -> %vreg13
	Result = %vreg13 [80r,144r:0)  0@80r
112B	%vreg14<def> = COPY %vreg15; GPR64all:%vreg14 GPR64:%vreg15
	Considering merging to GPR64 with %vreg15 in %vreg14
		RHS = %vreg15 [16r,800r:0)  0@16r
		LHS = %vreg14 [112r,160r:0)  0@112r
		merge %vreg14:0@112r into %vreg15:0@16r --> @16r
		erased:	112r	%vreg14<def> = COPY %vreg15; GPR64all:%vreg14 GPR64:%vreg15
		updated: 16B	%vreg14<def> = COPY %LR; GPR64:%vreg14
		updated: 800B	%vreg21<def> = COPY %vreg14; GPR64all:%vreg21 GPR64:%vreg14
	Success: %vreg15 -> %vreg14
	Result = %vreg14 [16r,800r:0)  0@16r
720B	%vreg20<def> = COPY %vreg19; GPR64all:%vreg20 GPR64sp:%vreg19
	Considering merging to GPR64sp with %vreg19 in %vreg20
		RHS = %vreg19 [704r,720r:0)  0@704r
		LHS = %vreg20 [720r,832r:0)  0@720r
		merge %vreg20:0@720r into %vreg19:0@704r --> @704r
		erased:	720r	%vreg20<def> = COPY %vreg19; GPR64all:%vreg20 GPR64sp:%vreg19
		updated: 704B	%vreg20<def> = ADDXri %vreg18, <ga:@prepare_new_block>[TF=34], 0; GPR64sp:%vreg20 GPR64common:%vreg18
	Success: %vreg19 -> %vreg20
	Result = %vreg20 [704r,832r:0)  0@704r
800B	%vreg21<def> = COPY %vreg14; GPR64all:%vreg21 GPR64:%vreg14
	Considering merging to GPR64 with %vreg14 in %vreg21
		RHS = %vreg14 [16r,800r:0)  0@16r
		LHS = %vreg21 [800r,848r:0)  0@800r
		merge %vreg21:0@800r into %vreg14:0@16r --> @16r
		erased:	800r	%vreg21<def> = COPY %vreg14; GPR64all:%vreg21 GPR64:%vreg14
		updated: 16B	%vreg21<def> = COPY %LR; GPR64:%vreg21
		updated: 160B	%X1<def> = COPY %vreg21; GPR64:%vreg21
	Success: %vreg14 -> %vreg21
	Result = %vreg21 [16r,848r:0)  0@16r
144B	%X0<def> = COPY %vreg13; GPR64sp:%vreg13
	Considering merging %vreg13 with %X0
	Can only merge into reserved registers.
160B	%X1<def> = COPY %vreg21; GPR64:%vreg21
	Considering merging %vreg21 with %X1
	Can only merge into reserved registers.
832B	%X0<def> = COPY %vreg20; GPR64sp:%vreg20
	Considering merging %vreg20 with %X0
	Can only merge into reserved registers.
848B	%X1<def> = COPY %vreg21; GPR64:%vreg21
	Considering merging %vreg21 with %X1
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
W30 [0B,16r:0)[176r,176d:4)[240e,240d:1)[864r,864d:2)[912e,912d:3)  0@0B-phi 1@240e 2@864r 3@912e 4@176r
W0 [0B,32r:0)[144r,176r:2)[832r,864r:1)  0@0B-phi 1@832r 2@144r
%vreg1 [32r,272r:0)  0@32r
%vreg2 [208r,400r:0)  0@208r
%vreg4 [384r,400r:0)  0@384r
%vreg6 [352r,368r:0)  0@352r
%vreg8 [320r,336r:0)  0@320r
%vreg10 [288r,304r:0)  0@288r
%vreg11 [64r,80r:0)  0@64r
%vreg13 [80r,144r:0)  0@80r
%vreg17 [448r,464r:0)  0@448r
%vreg18 [688r,704r:0)  0@688r
%vreg20 [704r,832r:0)  0@704r
%vreg21 [16r,848r:0)  0@16r
%vreg25 [768r,784r:0)  0@768r
%vreg26 [752r,768r:0)  0@752r
%vreg27 [736r,784r:0)  0@736r
%vreg31 [560r,576r:0)  0@560r
%vreg33 [544r,560r:0)  0@544r
%vreg34 [528r,544r:0)  0@528r
%vreg38 [512r,560r:0)  0@512r
%vreg41 [624r,640r:0)  0@624r
%vreg42 [608r,624r:0)  0@608r
RegMasks: 176r 864r
********** MACHINEINSTRS **********
# Machine code for function prepare_new_block: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
  fi#1: size=4, align=4, at location [SP]
Function Live Ins: %X0 in %vreg0, %LR in %vreg15

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %LR
16B		%vreg21<def> = COPY %LR; GPR64:%vreg21
32B		%vreg1<def> = COPY %X0; GPR64:%vreg1
64B		%vreg11<def> = ADRP <ga:@prepare_new_block>[TF=1]; GPR64common:%vreg11
80B		%vreg13<def> = ADDXri %vreg11, <ga:@prepare_new_block>[TF=34], 0; GPR64sp:%vreg13 GPR64common:%vreg11
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		%X0<def> = COPY %vreg13; GPR64sp:%vreg13
160B		%X1<def> = COPY %vreg21; GPR64:%vreg21
176B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		%vreg2<def> = MOVi32imm 4294967295; GPR32:%vreg2
224B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
240B		STACKMAP 0, 0, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=4) LD8[FixedStack0] GPR64:%vreg1
256B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
272B		STRXui %vreg1, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg1
288B		%vreg10<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg10
304B		STRWui %WZR, %vreg10, 27; mem:ST4[%nblock] GPR64common:%vreg10
320B		%vreg8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg8
336B		STRWui %WZR, %vreg8, 29; mem:ST4[%numZ] GPR64common:%vreg8
352B		%vreg6<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg6
368B		STRWui %WZR, %vreg6, 30; mem:ST4[%state_out_pos] GPR64common:%vreg6
384B		%vreg4<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg4
400B		STRWui %vreg2, %vreg4, 162; mem:ST4[%blockCRC] GPR32:%vreg2 GPR64common:%vreg4
416B		STRWui %WZR, <fi#1>, 0; mem:ST4[FixedStack1]
	    Successors according to CFG: BB#1

432B	BB#1: derived from LLVM BB %for.cond
	    Predecessors according to CFG: BB#0 BB#3
448B		%vreg17<def> = LDRWui <fi#1>, 0; mem:LD4[FixedStack1] GPR32common:%vreg17
464B		%WZR<def> = SUBSWri %vreg17, 256, 0, %NZCV<imp-def>; GPR32common:%vreg17
480B		Bcc 10, <BB#4>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#4 BB#2

496B	BB#2: derived from LLVM BB %for.body
	    Predecessors according to CFG: BB#1
512B		%vreg38<def> = LDRSWui <fi#1>, 0; mem:LD4[FixedStack1] GPR64:%vreg38
528B		%vreg34<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg34
544B		%vreg33<def> = ADDXri %vreg34, 128, 0; GPR64common:%vreg33,%vreg34
560B		%vreg31<def> = ADDXrr %vreg33, %vreg38; GPR64common:%vreg31,%vreg33 GPR64:%vreg38
576B		STRBBui %WZR, %vreg31, 0; mem:ST1[%arrayidx] GPR64common:%vreg31
	    Successors according to CFG: BB#3

592B	BB#3: derived from LLVM BB %for.inc
	    Predecessors according to CFG: BB#2
608B		%vreg42<def> = LDRWui <fi#1>, 0; mem:LD4[FixedStack1] GPR32common:%vreg42
624B		%vreg41<def> = ADDWri %vreg42, 1, 0; GPR32common:%vreg41,%vreg42
640B		STRWui %vreg41, <fi#1>, 0; mem:ST4[FixedStack1] GPR32common:%vreg41
656B		B <BB#1>
	    Successors according to CFG: BB#1

672B	BB#4: derived from LLVM BB %for.end
	    Predecessors according to CFG: BB#1
688B		%vreg18<def> = ADRP <ga:@prepare_new_block>[TF=1]; GPR64common:%vreg18
704B		%vreg20<def> = ADDXri %vreg18, <ga:@prepare_new_block>[TF=34], 0; GPR64sp:%vreg20 GPR64common:%vreg18
736B		%vreg27<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg27
752B		%vreg26<def> = LDRWui %vreg27, 165; mem:LD4[%blockNo] GPR32common:%vreg26 GPR64common:%vreg27
768B		%vreg25<def> = ADDWri %vreg26, 1, 0; GPR32common:%vreg25,%vreg26
784B		STRWui %vreg25, %vreg27, 165; mem:ST4[%blockNo] GPR32common:%vreg25 GPR64common:%vreg27
816B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
832B		%X0<def> = COPY %vreg20; GPR64sp:%vreg20
848B		%X1<def> = COPY %vreg21; GPR64:%vreg21
864B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
880B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
896B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
912B		STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...
928B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
944B		RET_ReallyLR

# End machine code for function prepare_new_block.

handleMove 512B -> 536B: %vreg38<def> = LDRSWui <fi#1>, 0; mem:LD4[FixedStack1] GPR64:%vreg38
     %vreg38:	[512r,560r:0)  0@512r
        -->	[536r,560r:0)  0@536r
handleMove 704B -> 760B: %vreg20<def> = ADDXri %vreg18, <ga:@prepare_new_block>[TF=34], 0; GPR64sp:%vreg20 GPR64common:%vreg18
     %vreg20:	[704r,832r:0)  0@704r
        -->	[760r,832r:0)  0@760r
     %vreg18:	[688r,704r:0)  0@688r
        -->	[688r,760r:0)  0@688r
handleMove 688B -> 756B: %vreg18<def> = ADRP <ga:@prepare_new_block>[TF=1]; GPR64common:%vreg18
     %vreg18:	[688r,760r:0)  0@688r
        -->	[756r,760r:0)  0@756r
********** GREEDY REGISTER ALLOCATION **********
********** Function: prepare_new_block
********** INTERVALS **********
W30 [0B,16r:0)[176r,176d:4)[240e,240d:1)[864r,864d:2)[912e,912d:3)  0@0B-phi 1@240e 2@864r 3@912e 4@176r
W0 [0B,32r:0)[144r,176r:2)[832r,864r:1)  0@0B-phi 1@832r 2@144r
%vreg1 [32r,272r:0)  0@32r
%vreg2 [208r,400r:0)  0@208r
%vreg4 [384r,400r:0)  0@384r
%vreg6 [352r,368r:0)  0@352r
%vreg8 [320r,336r:0)  0@320r
%vreg10 [288r,304r:0)  0@288r
%vreg11 [64r,80r:0)  0@64r
%vreg13 [80r,144r:0)  0@80r
%vreg17 [448r,464r:0)  0@448r
%vreg18 [756r,760r:0)  0@756r
%vreg20 [760r,832r:0)  0@760r
%vreg21 [16r,848r:0)  0@16r
%vreg25 [768r,784r:0)  0@768r
%vreg26 [752r,768r:0)  0@752r
%vreg27 [736r,784r:0)  0@736r
%vreg31 [560r,576r:0)  0@560r
%vreg33 [544r,560r:0)  0@544r
%vreg34 [528r,544r:0)  0@528r
%vreg38 [536r,560r:0)  0@536r
%vreg41 [624r,640r:0)  0@624r
%vreg42 [608r,624r:0)  0@608r
RegMasks: 176r 864r
********** MACHINEINSTRS **********
# Machine code for function prepare_new_block: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
  fi#1: size=4, align=4, at location [SP]
Function Live Ins: %X0 in %vreg0, %LR in %vreg15

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %LR
16B		%vreg21<def> = COPY %LR; GPR64:%vreg21
32B		%vreg1<def> = COPY %X0; GPR64:%vreg1
64B		%vreg11<def> = ADRP <ga:@prepare_new_block>[TF=1]; GPR64common:%vreg11
80B		%vreg13<def> = ADDXri %vreg11, <ga:@prepare_new_block>[TF=34], 0; GPR64sp:%vreg13 GPR64common:%vreg11
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		%X0<def> = COPY %vreg13; GPR64sp:%vreg13
160B		%X1<def> = COPY %vreg21; GPR64:%vreg21
176B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		%vreg2<def> = MOVi32imm 4294967295; GPR32:%vreg2
224B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
240B		STACKMAP 0, 0, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=4) LD8[FixedStack0] GPR64:%vreg1
256B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
272B		STRXui %vreg1, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg1
288B		%vreg10<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg10
304B		STRWui %WZR, %vreg10, 27; mem:ST4[%nblock] GPR64common:%vreg10
320B		%vreg8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg8
336B		STRWui %WZR, %vreg8, 29; mem:ST4[%numZ] GPR64common:%vreg8
352B		%vreg6<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg6
368B		STRWui %WZR, %vreg6, 30; mem:ST4[%state_out_pos] GPR64common:%vreg6
384B		%vreg4<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg4
400B		STRWui %vreg2, %vreg4, 162; mem:ST4[%blockCRC] GPR32:%vreg2 GPR64common:%vreg4
416B		STRWui %WZR, <fi#1>, 0; mem:ST4[FixedStack1]
	    Successors according to CFG: BB#1

432B	BB#1: derived from LLVM BB %for.cond
	    Predecessors according to CFG: BB#0 BB#3
448B		%vreg17<def> = LDRWui <fi#1>, 0; mem:LD4[FixedStack1] GPR32common:%vreg17
464B		%WZR<def> = SUBSWri %vreg17, 256, 0, %NZCV<imp-def>; GPR32common:%vreg17
480B		Bcc 10, <BB#4>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#4 BB#2

496B	BB#2: derived from LLVM BB %for.body
	    Predecessors according to CFG: BB#1
528B		%vreg34<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg34
536B		%vreg38<def> = LDRSWui <fi#1>, 0; mem:LD4[FixedStack1] GPR64:%vreg38
544B		%vreg33<def> = ADDXri %vreg34, 128, 0; GPR64common:%vreg33,%vreg34
560B		%vreg31<def> = ADDXrr %vreg33, %vreg38; GPR64common:%vreg31,%vreg33 GPR64:%vreg38
576B		STRBBui %WZR, %vreg31, 0; mem:ST1[%arrayidx] GPR64common:%vreg31
	    Successors according to CFG: BB#3

592B	BB#3: derived from LLVM BB %for.inc
	    Predecessors according to CFG: BB#2
608B		%vreg42<def> = LDRWui <fi#1>, 0; mem:LD4[FixedStack1] GPR32common:%vreg42
624B		%vreg41<def> = ADDWri %vreg42, 1, 0; GPR32common:%vreg41,%vreg42
640B		STRWui %vreg41, <fi#1>, 0; mem:ST4[FixedStack1] GPR32common:%vreg41
656B		B <BB#1>
	    Successors according to CFG: BB#1

672B	BB#4: derived from LLVM BB %for.end
	    Predecessors according to CFG: BB#1
736B		%vreg27<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg27
752B		%vreg26<def> = LDRWui %vreg27, 165; mem:LD4[%blockNo] GPR32common:%vreg26 GPR64common:%vreg27
756B		%vreg18<def> = ADRP <ga:@prepare_new_block>[TF=1]; GPR64common:%vreg18
760B		%vreg20<def> = ADDXri %vreg18, <ga:@prepare_new_block>[TF=34], 0; GPR64sp:%vreg20 GPR64common:%vreg18
768B		%vreg25<def> = ADDWri %vreg26, 1, 0; GPR32common:%vreg25,%vreg26
784B		STRWui %vreg25, %vreg27, 165; mem:ST4[%blockNo] GPR32common:%vreg25 GPR64common:%vreg27
816B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
832B		%X0<def> = COPY %vreg20; GPR64sp:%vreg20
848B		%X1<def> = COPY %vreg21; GPR64:%vreg21
864B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
880B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
896B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
912B		STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...
928B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
944B		RET_ReallyLR

# End machine code for function prepare_new_block.


selectOrSplit GPR64:%vreg21 [16r,848r:0)  0@16r w=2.459415e-03
hints: %X1
missed hint %X1
assigning %vreg21 to %X19: W19 [16r,848r:0)  0@16r

selectOrSplit GPR64:%vreg1 [32r,272r:0)  0@32r w=4.734375e-03
hints: %X0
missed hint %X0
assigning %vreg1 to %X20: W20 [32r,272r:0)  0@32r

selectOrSplit GPR64sp:%vreg13 [80r,144r:0)  0@80r w=4.353448e-03
hints: %X0
assigning %vreg13 to %X0: W0 [80r,144r:0)  0@80r

selectOrSplit GPR64sp:%vreg20 [760r,832r:0)  0@760r w=4.279661e-03
hints: %X0
assigning %vreg20 to %X0: W0 [760r,832r:0)  0@760r

selectOrSplit GPR64common:%vreg11 [64r,80r:0)  0@64r w=inf
assigning %vreg11 to %X8: W8 [64r,80r:0)  0@64r

selectOrSplit GPR32:%vreg2 [208r,400r:0)  0@208r w=1.689189e-03
assigning %vreg2 to %W8: W8 [208r,400r:0)  0@208r

selectOrSplit GPR64common:%vreg10 [288r,304r:0)  0@288r w=inf
assigning %vreg10 to %X9: W9 [288r,304r:0)  0@288r

selectOrSplit GPR64common:%vreg8 [320r,336r:0)  0@320r w=inf
assigning %vreg8 to %X9: W9 [320r,336r:0)  0@320r

selectOrSplit GPR64common:%vreg6 [352r,368r:0)  0@352r w=inf
assigning %vreg6 to %X9: W9 [352r,368r:0)  0@352r

selectOrSplit GPR64common:%vreg4 [384r,400r:0)  0@384r w=inf
assigning %vreg4 to %X9: W9 [384r,400r:0)  0@384r

selectOrSplit GPR32common:%vreg17 [448r,464r:0)  0@448r w=inf
assigning %vreg17 to %W8: W8 [448r,464r:0)  0@448r

selectOrSplit GPR64common:%vreg34 [528r,544r:0)  0@528r w=4.807692e-03
assigning %vreg34 to %X8: W8 [528r,544r:0)  0@528r

selectOrSplit GPR64:%vreg38 [536r,560r:0)  0@536r w=4.716981e-03
assigning %vreg38 to %X9: W9 [536r,560r:0)  0@536r

selectOrSplit GPR64common:%vreg33 [544r,560r:0)  0@544r w=inf
assigning %vreg33 to %X8: W8 [544r,560r:0)  0@544r

selectOrSplit GPR64common:%vreg31 [560r,576r:0)  0@560r w=inf
assigning %vreg31 to %X8: W8 [560r,576r:0)  0@560r

selectOrSplit GPR32common:%vreg42 [608r,624r:0)  0@608r w=inf
assigning %vreg42 to %W8: W8 [608r,624r:0)  0@608r

selectOrSplit GPR32common:%vreg41 [624r,640r:0)  0@624r w=inf
assigning %vreg41 to %W8: W8 [624r,640r:0)  0@624r

selectOrSplit GPR64common:%vreg27 [736r,784r:0)  0@736r w=6.696429e-03
assigning %vreg27 to %X8: W8 [736r,784r:0)  0@736r

selectOrSplit GPR32common:%vreg26 [752r,768r:0)  0@752r w=4.807692e-03
assigning %vreg26 to %W9: W9 [752r,768r:0)  0@752r

selectOrSplit GPR64common:%vreg18 [756r,760r:0)  0@756r w=inf
assigning %vreg18 to %X10: W10 [756r,760r:0)  0@756r

selectOrSplit GPR32common:%vreg25 [768r,784r:0)  0@768r w=inf
assigning %vreg25 to %W9: W9 [768r,784r:0)  0@768r

********** STACK TRANSFORMATION METADATA **********
********** Function: prepare_new_block
********** REGISTER MAP **********
[%vreg1 -> %X20] GPR64
[%vreg2 -> %W8] GPR32
[%vreg4 -> %X9] GPR64common
[%vreg6 -> %X9] GPR64common
[%vreg8 -> %X9] GPR64common
[%vreg10 -> %X9] GPR64common
[%vreg11 -> %X8] GPR64common
[%vreg13 -> %X0] GPR64sp
[%vreg17 -> %W8] GPR32common
[%vreg18 -> %X10] GPR64common
[%vreg20 -> %X0] GPR64sp
[%vreg21 -> %X19] GPR64
[%vreg25 -> %W9] GPR32common
[%vreg26 -> %W9] GPR32common
[%vreg27 -> %X8] GPR64common
[%vreg31 -> %X8] GPR64common
[%vreg33 -> %X8] GPR64common
[%vreg34 -> %X8] GPR64common
[%vreg38 -> %X9] GPR64
[%vreg41 -> %W8] GPR32common
[%vreg42 -> %W8] GPR32common


Stackmap 0:
  STACKMAP 0, 0, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=4) LD8[FixedStack0] GPR64:%vreg1

i32* %i: in stack slot 1 (size: 4)
%struct.EState* %s: in register %X20 (vreg 1)
%struct.EState** %s.addr: in stack slot 0 (size: 8)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...


Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=4) LD8[FixedStack0] GPR64:%vreg1
  -> Call instruction SlotIndex 176B, searching vregs 0 -> 43 and stack slots 0 -> 2
    + vreg21 is live in register but not in stackmap
      Defining instruction: %vreg21<def> = COPY %LR; GPR64:%vreg21
      Value: generated value, 1 instruction(s)

  STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...
  -> Call instruction SlotIndex 864B, searching vregs 0 -> 43 and stack slots 0 -> 2

********** REWRITE VIRTUAL REGISTERS **********
********** Function: prepare_new_block
********** REGISTER MAP **********
[%vreg1 -> %X20] GPR64
[%vreg2 -> %W8] GPR32
[%vreg4 -> %X9] GPR64common
[%vreg6 -> %X9] GPR64common
[%vreg8 -> %X9] GPR64common
[%vreg10 -> %X9] GPR64common
[%vreg11 -> %X8] GPR64common
[%vreg13 -> %X0] GPR64sp
[%vreg17 -> %W8] GPR32common
[%vreg18 -> %X10] GPR64common
[%vreg20 -> %X0] GPR64sp
[%vreg21 -> %X19] GPR64
[%vreg25 -> %W9] GPR32common
[%vreg26 -> %W9] GPR32common
[%vreg27 -> %X8] GPR64common
[%vreg31 -> %X8] GPR64common
[%vreg33 -> %X8] GPR64common
[%vreg34 -> %X8] GPR64common
[%vreg38 -> %X9] GPR64
[%vreg41 -> %W8] GPR32common
[%vreg42 -> %W8] GPR32common

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %LR %X0
16B		%vreg21<def> = COPY %LR; GPR64:%vreg21
32B		%vreg1<def> = COPY %X0; GPR64:%vreg1
64B		%vreg11<def> = ADRP <ga:@prepare_new_block>[TF=1]; GPR64common:%vreg11
80B		%vreg13<def> = ADDXri %vreg11<kill>, <ga:@prepare_new_block>[TF=34], 0; GPR64sp:%vreg13 GPR64common:%vreg11
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		%X0<def> = COPY %vreg13<kill>; GPR64sp:%vreg13
160B		%X1<def> = COPY %vreg21; GPR64:%vreg21
176B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		%vreg2<def> = MOVi32imm 4294967295; GPR32:%vreg2
224B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
240B		STACKMAP 0, 0, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=4) LD8[FixedStack0] GPR64:%vreg1
256B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
272B		STRXui %vreg1<kill>, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg1
288B		%vreg10<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg10
304B		STRWui %WZR, %vreg10<kill>, 27; mem:ST4[%nblock] GPR64common:%vreg10
320B		%vreg8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg8
336B		STRWui %WZR, %vreg8<kill>, 29; mem:ST4[%numZ] GPR64common:%vreg8
352B		%vreg6<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg6
368B		STRWui %WZR, %vreg6<kill>, 30; mem:ST4[%state_out_pos] GPR64common:%vreg6
384B		%vreg4<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg4
400B		STRWui %vreg2<kill>, %vreg4<kill>, 162; mem:ST4[%blockCRC] GPR32:%vreg2 GPR64common:%vreg4
416B		STRWui %WZR, <fi#1>, 0; mem:ST4[FixedStack1]
	    Successors according to CFG: BB#1
> %X19<def> = COPY %LR
> %X20<def> = COPY %X0
> %X8<def> = ADRP <ga:@prepare_new_block>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@prepare_new_block>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19
> BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W8<def> = MOVi32imm 4294967295
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 0, 0, 0, <fi#1>, 0, %X20, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=4) LD8[FixedStack0]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRXui %X20<kill>, <fi#0>, 0; mem:ST8[FixedStack0]
> %X9<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> STRWui %WZR, %X9<kill>, 27; mem:ST4[%nblock]
> %X9<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> STRWui %WZR, %X9<kill>, 29; mem:ST4[%numZ]
> %X9<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> STRWui %WZR, %X9<kill>, 30; mem:ST4[%state_out_pos]
> %X9<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> STRWui %W8<kill>, %X9<kill>, 162; mem:ST4[%blockCRC]
> STRWui %WZR, <fi#1>, 0; mem:ST4[FixedStack1]
432B	BB#1: derived from LLVM BB %for.cond
	    Live Ins: %X19
	    Predecessors according to CFG: BB#0 BB#3
448B		%vreg17<def> = LDRWui <fi#1>, 0; mem:LD4[FixedStack1] GPR32common:%vreg17
464B		%WZR<def> = SUBSWri %vreg17<kill>, 256, 0, %NZCV<imp-def>; GPR32common:%vreg17
480B		Bcc 10, <BB#4>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#4 BB#2
> %W8<def> = LDRWui <fi#1>, 0; mem:LD4[FixedStack1]
> %WZR<def> = SUBSWri %W8<kill>, 256, 0, %NZCV<imp-def>
> Bcc 10, <BB#4>, %NZCV<imp-use,kill>
496B	BB#2: derived from LLVM BB %for.body
	    Live Ins: %X19
	    Predecessors according to CFG: BB#1
528B		%vreg34<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg34
536B		%vreg38<def> = LDRSWui <fi#1>, 0; mem:LD4[FixedStack1] GPR64:%vreg38
544B		%vreg33<def> = ADDXri %vreg34<kill>, 128, 0; GPR64common:%vreg33,%vreg34
560B		%vreg31<def> = ADDXrr %vreg33<kill>, %vreg38<kill>; GPR64common:%vreg31,%vreg33 GPR64:%vreg38
576B		STRBBui %WZR, %vreg31<kill>, 0; mem:ST1[%arrayidx] GPR64common:%vreg31
	    Successors according to CFG: BB#3
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %X9<def> = LDRSWui <fi#1>, 0; mem:LD4[FixedStack1]
> %X8<def> = ADDXri %X8<kill>, 128, 0
> %X8<def> = ADDXrr %X8<kill>, %X9<kill>
> STRBBui %WZR, %X8<kill>, 0; mem:ST1[%arrayidx]
592B	BB#3: derived from LLVM BB %for.inc
	    Live Ins: %X19
	    Predecessors according to CFG: BB#2
608B		%vreg42<def> = LDRWui <fi#1>, 0; mem:LD4[FixedStack1] GPR32common:%vreg42
624B		%vreg41<def> = ADDWri %vreg42<kill>, 1, 0; GPR32common:%vreg41,%vreg42
640B		STRWui %vreg41<kill>, <fi#1>, 0; mem:ST4[FixedStack1] GPR32common:%vreg41
656B		B <BB#1>
	    Successors according to CFG: BB#1
> %W8<def> = LDRWui <fi#1>, 0; mem:LD4[FixedStack1]
> %W8<def> = ADDWri %W8<kill>, 1, 0
> STRWui %W8<kill>, <fi#1>, 0; mem:ST4[FixedStack1]
> B <BB#1>
672B	BB#4: derived from LLVM BB %for.end
	    Live Ins: %X19
	    Predecessors according to CFG: BB#1
736B		%vreg27<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg27
752B		%vreg26<def> = LDRWui %vreg27, 165; mem:LD4[%blockNo] GPR32common:%vreg26 GPR64common:%vreg27
756B		%vreg18<def> = ADRP <ga:@prepare_new_block>[TF=1]; GPR64common:%vreg18
760B		%vreg20<def> = ADDXri %vreg18<kill>, <ga:@prepare_new_block>[TF=34], 0; GPR64sp:%vreg20 GPR64common:%vreg18
768B		%vreg25<def> = ADDWri %vreg26<kill>, 1, 0; GPR32common:%vreg25,%vreg26
784B		STRWui %vreg25<kill>, %vreg27<kill>, 165; mem:ST4[%blockNo] GPR32common:%vreg25 GPR64common:%vreg27
816B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
832B		%X0<def> = COPY %vreg20<kill>; GPR64sp:%vreg20
848B		%X1<def> = COPY %vreg21<kill>; GPR64:%vreg21
864B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
880B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
896B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
912B		STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...
928B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
944B		RET_ReallyLR
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %W9<def> = LDRWui %X8, 165; mem:LD4[%blockNo]
> %X10<def> = ADRP <ga:@prepare_new_block>[TF=1]
> %X0<def> = ADDXri %X10<kill>, <ga:@prepare_new_block>[TF=34], 0
> %W9<def> = ADDWri %W9<kill>, 1, 0
> STRWui %W9<kill>, %X8<kill>, 165; mem:ST4[%blockNo]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19<kill>
> BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> RET_ReallyLR
Computing live-in reg-units in ABI blocks.
0B	BB#0 W0#0 W1#0 W30#0
Created 3 new intervals.
********** INTERVALS **********
W30 [0B,16r:0)[208r,208d:14)[256e,256d:7)[1136r,1136d:9)[1248e,1248d:6)[2240r,2240d:11)[2320e,2320d:5)[2496r,2496d:10)[2576e,2576d:4)[3312r,3312d:13)[3392e,3392d:3)[3696r,3696d:12)[3776e,3776d:2)[4288r,4288d:8)[4336e,4336d:1)  0@0B-phi 1@4336e 2@3776e 3@3392e 4@2576e 5@2320e 6@1248e 7@256e 8@4288r 9@1136r 10@2496r 11@2240r 12@3696r 13@3312r 14@208r
W0 [0B,48r:0)[176r,208r:13)[1120r,1136r:8)[1136r,1168r:2)[2224r,2240r:10)[2240r,2272r:4)[2480r,2496r:9)[2496r,2528r:3)[3296r,3312r:12)[3312r,3344r:6)[3680r,3696r:11)[3696r,3728r:5)[4256r,4288r:7)[4384r,4400r:1)  0@0B-phi 1@4384r 2@1136r 3@2496r 4@2240r 5@3696r 6@3312r 7@4256r 8@1120r 9@2480r 10@2224r 11@3680r 12@3296r 13@176r
W1 [0B,32r:0)[192r,208r:2)[4272r,4288r:1)  0@0B-phi 1@4272r 2@192r
%vreg0 [48r,64r:0)  0@48r
%vreg1 [64r,288r:0)  0@64r
%vreg2 [32r,80r:0)  0@32r
%vreg3 [80r,304r:0)  0@80r
%vreg5 [320r,336r:0)  0@320r
%vreg6 [96r,112r:0)  0@96r
%vreg7 [112r,128r:0)  0@112r
%vreg8 [128r,176r:0)  0@128r
%vreg9 [144r,192r:0)  0@144r
%vreg10 [16r,4224r:0)  0@16r
%vreg12 [496r,512r:0)  0@496r
%vreg15 [464r,480r:0)  0@464r
%vreg17 [448r,464r:0)  0@448r
%vreg18 [432r,448r:0)  0@432r
%vreg21 [640r,656r:0)  0@640r
%vreg23 [624r,656r:0)  0@624r
%vreg24 [608r,624r:0)  0@608r
%vreg25 [848r,928r:0)  0@848r
%vreg26 [800r,816r:0)  0@800r
%vreg27 [816r,832r:0)  0@816r
%vreg28 [832r,864r:0)  0@832r
%vreg29 [864r,864d:0)  0@864r
%vreg30 [912r,928r:0)  0@912r
%vreg31 [928r,944r:0)  0@928r
%vreg33 [2944r,2960r:0)  0@2944r
%vreg37 [3136r,3152r:0)  0@3136r
%vreg39 [3120r,3136r:0)  0@3120r
%vreg40 [3104r,3120r:0)  0@3104r
%vreg42 [3088r,3152r:0)  0@3088r
%vreg43 [3072r,3088r:0)  0@3072r
%vreg45 [3456r,3472r:0)  0@3456r
%vreg46 [3440r,3456r:0)  0@3440r
%vreg47 [3360r,3424r:0)  0@3360r
%vreg49 [3344r,3360r:0)  0@3344r
%vreg50 [3264r,3296r:0)  0@3264r
%vreg51 [3504r,3520r:0)  0@3504r
%vreg54 [3584r,3600r:0)  0@3584r
%vreg55 [3568r,3584r:0)  0@3568r
%vreg56 [3744r,3808r:0)  0@3744r
%vreg57 [3808r,3824r:0)  0@3808r
%vreg59 [3728r,3744r:0)  0@3728r
%vreg60 [3648r,3680r:0)  0@3648r
%vreg64 [3904r,3920r:0)  0@3904r
%vreg65 [3888r,3904r:0)  0@3888r
%vreg67 [3872r,3920r:0)  0@3872r
%vreg68 [3856r,3872r:0)  0@3856r
%vreg69 [4032r,4096r:0)  0@4032r
%vreg70 [4048r,4080r:0)  0@4048r
%vreg72 [4064r,4080r:0)  0@4064r
%vreg73 [3968r,3984r:0)  0@3968r
%vreg74 [3200r,3216r:0)  0@3200r
%vreg75 [3008r,3024r:0)  0@3008r
%vreg77 [1872r,1888r:0)  0@1872r
%vreg81 [2064r,2080r:0)  0@2064r
%vreg83 [2048r,2064r:0)  0@2048r
%vreg84 [2032r,2048r:0)  0@2032r
%vreg86 [2016r,2080r:0)  0@2016r
%vreg87 [2000r,2016r:0)  0@2000r
%vreg90 [2384r,2400r:0)  0@2384r
%vreg91 [2368r,2384r:0)  0@2368r
%vreg92 [2288r,2352r:0)  0@2288r
%vreg94 [2272r,2288r:0)  0@2272r
%vreg95 [2192r,2224r:0)  0@2192r
%vreg96 [2544r,2608r:0)  0@2544r
%vreg97 [2608r,2624r:0)  0@2608r
%vreg99 [2528r,2544r:0)  0@2528r
%vreg100 [2448r,2480r:0)  0@2448r
%vreg104 [2704r,2720r:0)  0@2704r
%vreg105 [2688r,2704r:0)  0@2688r
%vreg107 [2672r,2720r:0)  0@2672r
%vreg108 [2656r,2672r:0)  0@2656r
%vreg109 [2832r,2896r:0)  0@2832r
%vreg110 [2848r,2880r:0)  0@2848r
%vreg112 [2864r,2880r:0)  0@2864r
%vreg113 [2768r,2784r:0)  0@2768r
%vreg114 [2128r,2144r:0)  0@2128r
%vreg115 [1936r,1952r:0)  0@1936r
%vreg117 [1040r,1056r:0)  0@1040r
%vreg119 [1392r,1408r:0)  0@1392r
%vreg121 [1600r,1616r:0)  0@1600r
%vreg122 [1808r,1824r:0)  0@1808r
%vreg123 [1664r,1760r:0)  0@1664r
%vreg125 [1744r,1760r:0)  0@1744r
%vreg128 [1712r,1728r:0)  0@1712r
%vreg130 [1696r,1728r:0)  0@1696r
%vreg131 [1680r,1696r:0)  0@1680r
%vreg132 [1456r,1552r:0)  0@1456r
%vreg134 [1536r,1552r:0)  0@1536r
%vreg137 [1504r,1520r:0)  0@1504r
%vreg139 [1488r,1520r:0)  0@1488r
%vreg140 [1472r,1488r:0)  0@1472r
%vreg143 [1200r,1328r:0)  0@1200r
%vreg144 [1216r,1328r:0)  0@1216r
%vreg145 [1328r,1344r:0)  0@1328r
%vreg148 [1296r,1312r:0)  0@1296r
%vreg149 [1184r,1280r:0)  0@1184r
%vreg151 [1168r,1184r:0)  0@1168r
%vreg152 [1088r,1120r:0)  0@1088r
%vreg153 [976r,992r:0)  0@976r
%vreg154 [704r,720r:0)  0@704r
%vreg155 [544r,560r:0)  0@544r
%vreg156 [368r,384r:0)  0@368r
%vreg158 [4368r,4384r:0)  0@4368r
%vreg159 [4176r,4192r:0)  0@4176r
%vreg160 [4192r,4208r:0)  0@4192r
%vreg161 [4208r,4256r:0)  0@4208r
%vreg162 [4224r,4272r:0)  0@4224r
RegMasks: 208r 1136r 2240r 2496r 3312r 3696r 4288r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzCompress: Post SSA
Frame Objects:
  fi#0: size=4, align=4, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=4, align=4, at location [SP]
  fi#3: size=1, align=1, at location [SP]
  fi#4: size=8, align=8, at location [SP]
Jump Tables:
  jt#0:  BB#9 BB#10 BB#17 BB#26
Function Live Ins: %X0 in %vreg0, %W1 in %vreg2, %LR in %vreg10

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %W1 %LR
16B		%vreg10<def> = COPY %LR; GPR64:%vreg10
32B		%vreg2<def> = COPY %W1; GPR32:%vreg2
48B		%vreg0<def> = COPY %X0; GPR64:%vreg0
64B		%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
80B		%vreg3<def> = COPY %vreg2; GPR32:%vreg3,%vreg2
96B		%vreg6<def> = ADRP <ga:@BZ2_bzCompress>[TF=1]; GPR64common:%vreg6
112B		%vreg7<def> = ADDXri %vreg6, <ga:@BZ2_bzCompress>[TF=34], 0; GPR64sp:%vreg7 GPR64common:%vreg6
128B		%vreg8<def> = COPY %vreg7; GPR64all:%vreg8 GPR64sp:%vreg7
144B		%vreg9<def> = COPY %vreg10; GPR64all:%vreg9 GPR64:%vreg10
160B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
176B		%X0<def> = COPY %vreg8; GPR64all:%vreg8
192B		%X1<def> = COPY %vreg9; GPR64all:%vreg9
208B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
224B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
240B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
256B		STACKMAP 0, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#3>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, %vreg1, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack3](align=1) LD8[FixedStack0](align=4) LD8[FixedStack4] LD8[FixedStack1] GPR32:%vreg3 GPR64:%vreg1
272B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
288B		STRXui %vreg1, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg1
304B		STRWui %vreg3, <fi#2>, 0; mem:ST4[FixedStack2] GPR32:%vreg3
320B		%vreg5<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg5
336B		CBNZX %vreg5, <BB#2>; GPR64:%vreg5
	    Successors according to CFG: BB#2 BB#1

352B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
368B		%vreg156<def> = MOVi32imm 4294967294; GPR32:%vreg156
384B		STRWui %vreg156, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg156
400B		B <BB#38>
	    Successors according to CFG: BB#38

416B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0
432B		%vreg18<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg18
448B		%vreg17<def> = LDRXui %vreg18, 6; mem:LD8[%state] GPR64:%vreg17 GPR64common:%vreg18
464B		%vreg15<def> = COPY %vreg17; GPR64:%vreg15,%vreg17
480B		STRXui %vreg15, <fi#4>, 0; mem:ST8[FixedStack4] GPR64:%vreg15
496B		%vreg12<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64:%vreg12
512B		CBNZX %vreg12, <BB#4>; GPR64:%vreg12
	    Successors according to CFG: BB#4 BB#3

528B	BB#3: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#2
544B		%vreg155<def> = MOVi32imm 4294967294; GPR32:%vreg155
560B		STRWui %vreg155, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg155
576B		B <BB#38>
	    Successors according to CFG: BB#38

592B	BB#4: derived from LLVM BB %if.end.3
	    Predecessors according to CFG: BB#2
608B		%vreg24<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg24
624B		%vreg23<def> = LDRXui %vreg24, 0; mem:LD8[%strm4] GPR64:%vreg23 GPR64common:%vreg24
640B		%vreg21<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg21
656B		%XZR<def> = SUBSXrr %vreg23, %vreg21, %NZCV<imp-def>; GPR64:%vreg23,%vreg21
672B		Bcc 0, <BB#6>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#6 BB#5

688B	BB#5: derived from LLVM BB %if.then.6
	    Predecessors according to CFG: BB#4
704B		%vreg154<def> = MOVi32imm 4294967294; GPR32:%vreg154
720B		STRWui %vreg154, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg154
736B		B <BB#38>
	    Successors according to CFG: BB#38

752B	BB#6: derived from LLVM BB %if.end.7
	    Predecessors according to CFG: BB#4
768B		B <BB#7>
	    Successors according to CFG: BB#7

784B	BB#7: derived from LLVM BB %preswitch
	    Predecessors according to CFG: BB#6 BB#15 BB#13
800B		%vreg26<def> = LDRXui <fi#4>, 0; mem:LD8[%s] GPR64common:%vreg26
816B		%vreg27<def> = LDRWui %vreg26, 2; mem:LD4[%mode] GPR32common:%vreg27 GPR64common:%vreg26
832B		%vreg28<def> = SUBSWri %vreg27, 1, 0, %NZCV<imp-def,dead>; GPR32common:%vreg28,%vreg27
848B		%vreg25<def> = SUBREG_TO_REG 0, %vreg28, 15; GPR64:%vreg25 GPR32common:%vreg28
864B		%vreg29<def,dead> = SUBSWri %vreg28, 3, 0, %NZCV<imp-def>; GPR32:%vreg29 GPR32common:%vreg28
880B		Bcc 8, <BB#37>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#37 BB#8

896B	BB#8: derived from LLVM BB %preswitch
	    Predecessors according to CFG: BB#7
912B		%vreg30<def> = MOVaddrJT <jt#0>[TF=1], <jt#0>[TF=34]; GPR64common:%vreg30
928B		%vreg31<def> = LDRXroX %vreg30, %vreg25, 0, 1; mem:LD8[JumpTable] GPR64:%vreg31,%vreg25 GPR64common:%vreg30
944B		BR %vreg31; GPR64:%vreg31
	    Successors according to CFG: BB#9 BB#10 BB#17 BB#26

960B	BB#9: derived from LLVM BB %sw.bb
	    Predecessors according to CFG: BB#8
976B		%vreg153<def> = MOVi32imm 4294967295; GPR32:%vreg153
992B		STRWui %vreg153, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg153
1008B		B <BB#38>
	    Successors according to CFG: BB#38

1024B	BB#10: derived from LLVM BB %sw.bb.8
	    Predecessors according to CFG: BB#8
1040B		%vreg117<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg117
1056B		CBNZW %vreg117, <BB#12>; GPR32:%vreg117
	    Successors according to CFG: BB#12 BB#11

1072B	BB#11: derived from LLVM BB %if.then.10
	    Predecessors according to CFG: BB#10
1088B		%vreg152<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg152
1104B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1120B		%X0<def> = COPY %vreg152; GPR64:%vreg152
1136B		BL <ga:@handle_compress>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>
1152B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1168B		%vreg151<def> = COPY %W0; GPR32:%vreg151
1184B		%vreg149<def> = COPY %vreg151; GPR32:%vreg149,%vreg151
1200B		%vreg143<def> = MOVi32imm 1; GPR32:%vreg143
1216B		%vreg144<def> = MOVi32imm 4294967294; GPR32:%vreg144
1232B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1248B		STACKMAP 1, 0, 0, <fi#3>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack3](align=1) LD8[FixedStack0](align=4)
1264B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1280B		STRBBui %vreg149, <fi#3>, 0; mem:ST1[FixedStack3] GPR32:%vreg149
1296B		%vreg148<def> = LDRBBui <fi#3>, 0; mem:LD1[FixedStack3] GPR32common:%vreg148
1312B		%WZR<def> = SUBSWri %vreg148, 0, 0, %NZCV<imp-def>; GPR32common:%vreg148
1328B		%vreg145<def> = CSELWr %vreg143, %vreg144, 1, %NZCV<imp-use,kill>; GPR32:%vreg145,%vreg143,%vreg144
1344B		STRWui %vreg145, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg145
1360B		B <BB#38>
	    Successors according to CFG: BB#38

1376B	BB#12: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#10
1392B		%vreg119<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32common:%vreg119
1408B		%WZR<def> = SUBSWri %vreg119, 1, 0, %NZCV<imp-def>; GPR32common:%vreg119
1424B		Bcc 1, <BB#14>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#14 BB#13

1440B	BB#13: derived from LLVM BB %if.then.13
	    Predecessors according to CFG: BB#12
1456B		%vreg132<def> = MOVi32imm 3; GPR32:%vreg132
1472B		%vreg140<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg140
1488B		%vreg139<def> = LDRWui %vreg140, 2; mem:LD4[%avail_in] GPR32:%vreg139 GPR64common:%vreg140
1504B		%vreg137<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg137
1520B		STRWui %vreg139, %vreg137, 4; mem:ST4[%avail_in_expect] GPR32:%vreg139 GPR64common:%vreg137
1536B		%vreg134<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg134
1552B		STRWui %vreg132, %vreg134, 2; mem:ST4[%mode14] GPR32:%vreg132 GPR64common:%vreg134
1568B		B <BB#7>
	    Successors according to CFG: BB#7

1584B	BB#14: derived from LLVM BB %if.else.15
	    Predecessors according to CFG: BB#12
1600B		%vreg121<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32common:%vreg121
1616B		%WZR<def> = SUBSWri %vreg121, 2, 0, %NZCV<imp-def>; GPR32common:%vreg121
1632B		Bcc 1, <BB#16>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#16 BB#15

1648B	BB#15: derived from LLVM BB %if.then.18
	    Predecessors according to CFG: BB#14
1664B		%vreg123<def> = MOVi32imm 4; GPR32:%vreg123
1680B		%vreg131<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg131
1696B		%vreg130<def> = LDRWui %vreg131, 2; mem:LD4[%avail_in19] GPR32:%vreg130 GPR64common:%vreg131
1712B		%vreg128<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg128
1728B		STRWui %vreg130, %vreg128, 4; mem:ST4[%avail_in_expect20] GPR32:%vreg130 GPR64common:%vreg128
1744B		%vreg125<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg125
1760B		STRWui %vreg123, %vreg125, 2; mem:ST4[%mode21] GPR32:%vreg123 GPR64common:%vreg125
1776B		B <BB#7>
	    Successors according to CFG: BB#7

1792B	BB#16: derived from LLVM BB %if.else.22
	    Predecessors according to CFG: BB#14
1808B		%vreg122<def> = MOVi32imm 4294967294; GPR32:%vreg122
1824B		STRWui %vreg122, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg122
1840B		B <BB#38>
	    Successors according to CFG: BB#38

1856B	BB#17: derived from LLVM BB %sw.bb.23
	    Predecessors according to CFG: BB#8
1872B		%vreg77<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32common:%vreg77
1888B		%WZR<def> = SUBSWri %vreg77, 1, 0, %NZCV<imp-def>; GPR32common:%vreg77
1904B		Bcc 0, <BB#19>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#19 BB#18

1920B	BB#18: derived from LLVM BB %if.then.26
	    Predecessors according to CFG: BB#17
1936B		%vreg115<def> = MOVi32imm 4294967295; GPR32:%vreg115
1952B		STRWui %vreg115, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg115
1968B		B <BB#38>
	    Successors according to CFG: BB#38

1984B	BB#19: derived from LLVM BB %if.end.27
	    Predecessors according to CFG: BB#17
2000B		%vreg87<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg87
2016B		%vreg86<def> = LDRWui %vreg87, 4; mem:LD4[%avail_in_expect28] GPR32:%vreg86 GPR64common:%vreg87
2032B		%vreg84<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg84
2048B		%vreg83<def> = LDRXui %vreg84, 0; mem:LD8[%strm29] GPR64common:%vreg83,%vreg84
2064B		%vreg81<def> = LDRWui %vreg83, 2; mem:LD4[%avail_in30] GPR32:%vreg81 GPR64common:%vreg83
2080B		%WZR<def> = SUBSWrr %vreg86, %vreg81, %NZCV<imp-def>; GPR32:%vreg86,%vreg81
2096B		Bcc 0, <BB#21>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#21 BB#20

2112B	BB#20: derived from LLVM BB %if.then.33
	    Predecessors according to CFG: BB#19
2128B		%vreg114<def> = MOVi32imm 4294967295; GPR32:%vreg114
2144B		STRWui %vreg114, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg114
2160B		B <BB#38>
	    Successors according to CFG: BB#38

2176B	BB#21: derived from LLVM BB %if.end.34
	    Predecessors according to CFG: BB#19
2192B		%vreg95<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg95
2208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2224B		%X0<def> = COPY %vreg95; GPR64:%vreg95
2240B		BL <ga:@handle_compress>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>
2256B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2272B		%vreg94<def> = COPY %W0; GPR32:%vreg94
2288B		%vreg92<def> = COPY %vreg94; GPR32:%vreg92,%vreg94
2304B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2320B		STACKMAP 2, 0, 0, <fi#3>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack3](align=1) LD8[FixedStack0](align=4) LD8[FixedStack4]
2336B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2352B		STRBBui %vreg92, <fi#3>, 0; mem:ST1[FixedStack3] GPR32:%vreg92
2368B		%vreg91<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg91
2384B		%vreg90<def> = LDRWui %vreg91, 4; mem:LD4[%avail_in_expect36] GPR32common:%vreg90 GPR64common:%vreg91
2400B		%WZR<def> = SUBSWri %vreg90, 0, 0, %NZCV<imp-def>; GPR32common:%vreg90
2416B		Bcc 8, <BB#24>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#24 BB#22

2432B	BB#22: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#21
2448B		%vreg100<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64:%vreg100
2464B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2480B		%X0<def> = COPY %vreg100; GPR64:%vreg100
2496B		BL <ga:@isempty_RL>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>
2512B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2528B		%vreg99<def> = COPY %W0; GPR32:%vreg99
2544B		%vreg96<def> = COPY %vreg99; GPR32:%vreg96,%vreg99
2560B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2576B		STACKMAP 3, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack4]
2592B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2608B		%vreg97<def> = UBFMWri %vreg96, 0, 7; GPR32:%vreg97,%vreg96
2624B		CBZW %vreg97, <BB#24>; GPR32:%vreg97
	    Successors according to CFG: BB#24 BB#23

2640B	BB#23: derived from LLVM BB %lor.lhs.false.41
	    Predecessors according to CFG: BB#22
2656B		%vreg108<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg108
2672B		%vreg107<def> = LDRWui %vreg108, 30; mem:LD4[%state_out_pos] GPR32:%vreg107 GPR64common:%vreg108
2688B		%vreg105<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg105
2704B		%vreg104<def> = LDRWui %vreg105, 29; mem:LD4[%numZ] GPR32:%vreg104 GPR64common:%vreg105
2720B		%WZR<def> = SUBSWrr %vreg107, %vreg104, %NZCV<imp-def>; GPR32:%vreg107,%vreg104
2736B		Bcc 10, <BB#25>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#25 BB#24

2752B	BB#24: derived from LLVM BB %if.then.44
	    Predecessors according to CFG: BB#21 BB#22 BB#23
2768B		%vreg113<def> = MOVi32imm 2; GPR32:%vreg113
2784B		STRWui %vreg113, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg113
2800B		B <BB#38>
	    Successors according to CFG: BB#38

2816B	BB#25: derived from LLVM BB %if.end.45
	    Predecessors according to CFG: BB#23
2832B		%vreg109<def> = MOVi32imm 1; GPR32:%vreg109
2848B		%vreg110<def> = MOVi32imm 2; GPR32:%vreg110
2864B		%vreg112<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg112
2880B		STRWui %vreg110, %vreg112, 2; mem:ST4[%mode46] GPR32:%vreg110 GPR64common:%vreg112
2896B		STRWui %vreg109, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg109
2912B		B <BB#38>
	    Successors according to CFG: BB#38

2928B	BB#26: derived from LLVM BB %sw.bb.47
	    Predecessors according to CFG: BB#8
2944B		%vreg33<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32common:%vreg33
2960B		%WZR<def> = SUBSWri %vreg33, 2, 0, %NZCV<imp-def>; GPR32common:%vreg33
2976B		Bcc 0, <BB#28>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#28 BB#27

2992B	BB#27: derived from LLVM BB %if.then.50
	    Predecessors according to CFG: BB#26
3008B		%vreg75<def> = MOVi32imm 4294967295; GPR32:%vreg75
3024B		STRWui %vreg75, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg75
3040B		B <BB#38>
	    Successors according to CFG: BB#38

3056B	BB#28: derived from LLVM BB %if.end.51
	    Predecessors according to CFG: BB#26
3072B		%vreg43<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg43
3088B		%vreg42<def> = LDRWui %vreg43, 4; mem:LD4[%avail_in_expect52] GPR32:%vreg42 GPR64common:%vreg43
3104B		%vreg40<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg40
3120B		%vreg39<def> = LDRXui %vreg40, 0; mem:LD8[%strm53] GPR64common:%vreg39,%vreg40
3136B		%vreg37<def> = LDRWui %vreg39, 2; mem:LD4[%avail_in54] GPR32:%vreg37 GPR64common:%vreg39
3152B		%WZR<def> = SUBSWrr %vreg42, %vreg37, %NZCV<imp-def>; GPR32:%vreg42,%vreg37
3168B		Bcc 0, <BB#30>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#30 BB#29

3184B	BB#29: derived from LLVM BB %if.then.57
	    Predecessors according to CFG: BB#28
3200B		%vreg74<def> = MOVi32imm 4294967295; GPR32:%vreg74
3216B		STRWui %vreg74, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg74
3232B		B <BB#38>
	    Successors according to CFG: BB#38

3248B	BB#30: derived from LLVM BB %if.end.58
	    Predecessors according to CFG: BB#28
3264B		%vreg50<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg50
3280B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3296B		%X0<def> = COPY %vreg50; GPR64:%vreg50
3312B		BL <ga:@handle_compress>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>
3328B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3344B		%vreg49<def> = COPY %W0; GPR32:%vreg49
3360B		%vreg47<def> = COPY %vreg49; GPR32:%vreg47,%vreg49
3376B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3392B		STACKMAP 4, 0, 0, <fi#3>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack3](align=1) LD8[FixedStack0](align=4) LD8[FixedStack4]
3408B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3424B		STRBBui %vreg47, <fi#3>, 0; mem:ST1[FixedStack3] GPR32:%vreg47
3440B		%vreg46<def> = LDRBBui <fi#3>, 0; mem:LD1[FixedStack3] GPR32:%vreg46
3456B		%vreg45<def> = UBFMWri %vreg46, 0, 7; GPR32:%vreg45,%vreg46
3472B		CBNZW %vreg45, <BB#32>; GPR32:%vreg45
	    Successors according to CFG: BB#32 BB#31

3488B	BB#31: derived from LLVM BB %if.then.61
	    Predecessors according to CFG: BB#30
3504B		%vreg51<def> = MOVi32imm 4294967295; GPR32:%vreg51
3520B		STRWui %vreg51, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg51
3536B		B <BB#38>
	    Successors according to CFG: BB#38

3552B	BB#32: derived from LLVM BB %if.end.62
	    Predecessors according to CFG: BB#30
3568B		%vreg55<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg55
3584B		%vreg54<def> = LDRWui %vreg55, 4; mem:LD4[%avail_in_expect63] GPR32common:%vreg54 GPR64common:%vreg55
3600B		%WZR<def> = SUBSWri %vreg54, 0, 0, %NZCV<imp-def>; GPR32common:%vreg54
3616B		Bcc 8, <BB#35>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#35 BB#33

3632B	BB#33: derived from LLVM BB %lor.lhs.false.66
	    Predecessors according to CFG: BB#32
3648B		%vreg60<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64:%vreg60
3664B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3680B		%X0<def> = COPY %vreg60; GPR64:%vreg60
3696B		BL <ga:@isempty_RL>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>
3712B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3728B		%vreg59<def> = COPY %W0; GPR32:%vreg59
3744B		%vreg56<def> = COPY %vreg59; GPR32:%vreg56,%vreg59
3760B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3776B		STACKMAP 5, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack4]
3792B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3808B		%vreg57<def> = UBFMWri %vreg56, 0, 7; GPR32:%vreg57,%vreg56
3824B		CBZW %vreg57, <BB#35>; GPR32:%vreg57
	    Successors according to CFG: BB#35 BB#34

3840B	BB#34: derived from LLVM BB %lor.lhs.false.69
	    Predecessors according to CFG: BB#33
3856B		%vreg68<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg68
3872B		%vreg67<def> = LDRWui %vreg68, 30; mem:LD4[%state_out_pos70] GPR32:%vreg67 GPR64common:%vreg68
3888B		%vreg65<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg65
3904B		%vreg64<def> = LDRWui %vreg65, 29; mem:LD4[%numZ71] GPR32:%vreg64 GPR64common:%vreg65
3920B		%WZR<def> = SUBSWrr %vreg67, %vreg64, %NZCV<imp-def>; GPR32:%vreg67,%vreg64
3936B		Bcc 10, <BB#36>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#36 BB#35

3952B	BB#35: derived from LLVM BB %if.then.74
	    Predecessors according to CFG: BB#32 BB#33 BB#34
3968B		%vreg73<def> = MOVi32imm 3; GPR32:%vreg73
3984B		STRWui %vreg73, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg73
4000B		B <BB#38>
	    Successors according to CFG: BB#38

4016B	BB#36: derived from LLVM BB %if.end.75
	    Predecessors according to CFG: BB#34
4032B		%vreg69<def> = MOVi32imm 4; GPR32:%vreg69
4048B		%vreg70<def> = MOVi32imm 1; GPR32:%vreg70
4064B		%vreg72<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg72
4080B		STRWui %vreg70, %vreg72, 2; mem:ST4[%mode76] GPR32:%vreg70 GPR64common:%vreg72
4096B		STRWui %vreg69, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg69
4112B		B <BB#38>
	    Successors according to CFG: BB#38

4128B	BB#37: derived from LLVM BB %sw.epilog
	    Predecessors according to CFG: BB#7
4144B		STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
	    Successors according to CFG: BB#38

4160B	BB#38: derived from LLVM BB %return
	    Predecessors according to CFG: BB#31 BB#36 BB#35 BB#29 BB#27 BB#25 BB#24 BB#20 BB#18 BB#16 BB#11 BB#9 BB#37 BB#5 BB#3 BB#1
4176B		%vreg159<def> = ADRP <ga:@BZ2_bzCompress>[TF=1]; GPR64common:%vreg159
4192B		%vreg160<def> = ADDXri %vreg159, <ga:@BZ2_bzCompress>[TF=34], 0; GPR64sp:%vreg160 GPR64common:%vreg159
4208B		%vreg161<def> = COPY %vreg160; GPR64all:%vreg161 GPR64sp:%vreg160
4224B		%vreg162<def> = COPY %vreg10; GPR64all:%vreg162 GPR64:%vreg10
4240B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4256B		%X0<def> = COPY %vreg161; GPR64all:%vreg161
4272B		%X1<def> = COPY %vreg162; GPR64all:%vreg162
4288B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
4304B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4320B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4336B		STACKMAP 6, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
4352B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4368B		%vreg158<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0] GPR32:%vreg158
4384B		%W0<def> = COPY %vreg158; GPR32:%vreg158
4400B		RET_ReallyLR %W0<imp-use>

# End machine code for function BZ2_bzCompress.

********** SIMPLE REGISTER COALESCING **********
********** Function: BZ2_bzCompress
********** JOINING INTERVALS ***********
preswitch:
848B	%vreg25<def> = SUBREG_TO_REG 0, %vreg28, 15; GPR64:%vreg25 GPR32common:%vreg28
	Considering merging to GPR64common with %vreg28 in %vreg25:sub_32
		RHS = %vreg28 [832r,864r:0)  0@832r
		LHS = %vreg25 [848r,928r:0)  0@848r
		merge %vreg25:0@848r into %vreg28:0@832r --> @832r
		erased:	848r	%vreg25<def> = SUBREG_TO_REG 0, %vreg28, 15; GPR64:%vreg25 GPR32common:%vreg28
		updated: 832B	%vreg25:sub_32<def,read-undef> = SUBSWri %vreg27, 1, 0, %NZCV<imp-def,dead>; GPR64common:%vreg25 GPR32common:%vreg27
		updated: 864B	%vreg29<def,dead> = SUBSWri %vreg25:sub_32, 3, 0, %NZCV<imp-def>; GPR32:%vreg29 GPR64common:%vreg25
	Success: %vreg28:sub_32 -> %vreg25
	Result = %vreg25 [832r,928r:0)  0@832r
preswitch:
sw.bb.8:
if.else:
if.else.15:
if.then.13:
if.then.18:
return:
4256B	%X0<def> = COPY %vreg161; GPR64all:%vreg161
	Considering merging %vreg161 with %X0
	Can only merge into reserved registers.
4272B	%X1<def> = COPY %vreg162; GPR64all:%vreg162
	Considering merging %vreg162 with %X1
	Can only merge into reserved registers.
4384B	%W0<def> = COPY %vreg158; GPR32:%vreg158
	Considering merging %vreg158 with %W0
	Can only merge into reserved registers.
if.then.44:
if.then.74:
if.end:
if.end.3:
sw.bb.23:
if.end.27:
if.end.34:
2224B	%X0<def> = COPY %vreg95; GPR64:%vreg95
	Considering merging %vreg95 with %X0
	Can only merge into reserved registers.
2272B	%vreg94<def> = COPY %W0; GPR32:%vreg94
	Considering merging %vreg94 with %W0
	Can only merge into reserved registers.
lor.lhs.false:
2480B	%X0<def> = COPY %vreg100; GPR64:%vreg100
	Considering merging %vreg100 with %X0
	Can only merge into reserved registers.
2528B	%vreg99<def> = COPY %W0; GPR32:%vreg99
	Considering merging %vreg99 with %W0
	Can only merge into reserved registers.
lor.lhs.false.41:
sw.bb.47:
if.end.51:
if.end.58:
3296B	%X0<def> = COPY %vreg50; GPR64:%vreg50
	Considering merging %vreg50 with %X0
	Can only merge into reserved registers.
3344B	%vreg49<def> = COPY %W0; GPR32:%vreg49
	Considering merging %vreg49 with %W0
	Can only merge into reserved registers.
if.end.62:
lor.lhs.false.66:
3680B	%X0<def> = COPY %vreg60; GPR64:%vreg60
	Considering merging %vreg60 with %X0
	Can only merge into reserved registers.
3728B	%vreg59<def> = COPY %W0; GPR32:%vreg59
	Considering merging %vreg59 with %W0
	Can only merge into reserved registers.
lor.lhs.false.69:
entry:
16B	%vreg10<def> = COPY %LR; GPR64:%vreg10
	Considering merging %vreg10 with %LR
	Can only merge into reserved registers.
32B	%vreg2<def> = COPY %W1; GPR32:%vreg2
	Considering merging %vreg2 with %W1
	Can only merge into reserved registers.
48B	%vreg0<def> = COPY %X0; GPR64:%vreg0
	Considering merging %vreg0 with %X0
	Can only merge into reserved registers.
176B	%X0<def> = COPY %vreg8; GPR64all:%vreg8
	Considering merging %vreg8 with %X0
	Can only merge into reserved registers.
192B	%X1<def> = COPY %vreg9; GPR64all:%vreg9
	Considering merging %vreg9 with %X1
	Can only merge into reserved registers.
if.then:
if.then.2:
if.then.6:
if.end.7:
sw.bb:
if.then.10:
1120B	%X0<def> = COPY %vreg152; GPR64:%vreg152
	Considering merging %vreg152 with %X0
	Can only merge into reserved registers.
1168B	%vreg151<def> = COPY %W0; GPR32:%vreg151
	Considering merging %vreg151 with %W0
	Can only merge into reserved registers.
if.else.22:
if.then.26:
if.then.33:
if.end.45:
if.then.50:
if.then.57:
if.then.61:
if.end.75:
sw.epilog:
4208B	%vreg161<def> = COPY %vreg160; GPR64all:%vreg161 GPR64sp:%vreg160
	Considering merging to GPR64sp with %vreg160 in %vreg161
		RHS = %vreg160 [4192r,4208r:0)  0@4192r
		LHS = %vreg161 [4208r,4256r:0)  0@4208r
		merge %vreg161:0@4208r into %vreg160:0@4192r --> @4192r
		erased:	4208r	%vreg161<def> = COPY %vreg160; GPR64all:%vreg161 GPR64sp:%vreg160
		updated: 4192B	%vreg161<def> = ADDXri %vreg159, <ga:@BZ2_bzCompress>[TF=34], 0; GPR64sp:%vreg161 GPR64common:%vreg159
	Success: %vreg160 -> %vreg161
	Result = %vreg161 [4192r,4256r:0)  0@4192r
4224B	%vreg162<def> = COPY %vreg10; GPR64all:%vreg162 GPR64:%vreg10
	Considering merging to GPR64 with %vreg10 in %vreg162
		RHS = %vreg10 [16r,4224r:0)  0@16r
		LHS = %vreg162 [4224r,4272r:0)  0@4224r
		merge %vreg162:0@4224r into %vreg10:0@16r --> @16r
		erased:	4224r	%vreg162<def> = COPY %vreg10; GPR64all:%vreg162 GPR64:%vreg10
		updated: 16B	%vreg162<def> = COPY %LR; GPR64:%vreg162
		updated: 144B	%vreg9<def> = COPY %vreg162; GPR64all:%vreg9 GPR64:%vreg162
	Success: %vreg10 -> %vreg162
	Result = %vreg162 [16r,4272r:0)  0@16r
464B	%vreg15<def> = COPY %vreg17; GPR64:%vreg15,%vreg17
	Considering merging to GPR64 with %vreg17 in %vreg15
		RHS = %vreg17 [448r,464r:0)  0@448r
		LHS = %vreg15 [464r,480r:0)  0@464r
		merge %vreg15:0@464r into %vreg17:0@448r --> @448r
		erased:	464r	%vreg15<def> = COPY %vreg17; GPR64:%vreg15,%vreg17
		updated: 448B	%vreg15<def> = LDRXui %vreg18, 6; mem:LD8[%state] GPR64:%vreg15 GPR64common:%vreg18
	Success: %vreg17 -> %vreg15
	Result = %vreg15 [448r,480r:0)  0@448r
2288B	%vreg92<def> = COPY %vreg94; GPR32:%vreg92,%vreg94
	Considering merging to GPR32 with %vreg94 in %vreg92
		RHS = %vreg94 [2272r,2288r:0)  0@2272r
		LHS = %vreg92 [2288r,2352r:0)  0@2288r
		merge %vreg92:0@2288r into %vreg94:0@2272r --> @2272r
		erased:	2288r	%vreg92<def> = COPY %vreg94; GPR32:%vreg92,%vreg94
		updated: 2272B	%vreg92<def> = COPY %W0; GPR32:%vreg92
	Success: %vreg94 -> %vreg92
	Result = %vreg92 [2272r,2352r:0)  0@2272r
2544B	%vreg96<def> = COPY %vreg99; GPR32:%vreg96,%vreg99
	Considering merging to GPR32 with %vreg99 in %vreg96
		RHS = %vreg99 [2528r,2544r:0)  0@2528r
		LHS = %vreg96 [2544r,2608r:0)  0@2544r
		merge %vreg96:0@2544r into %vreg99:0@2528r --> @2528r
		erased:	2544r	%vreg96<def> = COPY %vreg99; GPR32:%vreg96,%vreg99
		updated: 2528B	%vreg96<def> = COPY %W0; GPR32:%vreg96
	Success: %vreg99 -> %vreg96
	Result = %vreg96 [2528r,2608r:0)  0@2528r
3360B	%vreg47<def> = COPY %vreg49; GPR32:%vreg47,%vreg49
	Considering merging to GPR32 with %vreg49 in %vreg47
		RHS = %vreg49 [3344r,3360r:0)  0@3344r
		LHS = %vreg47 [3360r,3424r:0)  0@3360r
		merge %vreg47:0@3360r into %vreg49:0@3344r --> @3344r
		erased:	3360r	%vreg47<def> = COPY %vreg49; GPR32:%vreg47,%vreg49
		updated: 3344B	%vreg47<def> = COPY %W0; GPR32:%vreg47
	Success: %vreg49 -> %vreg47
	Result = %vreg47 [3344r,3424r:0)  0@3344r
3744B	%vreg56<def> = COPY %vreg59; GPR32:%vreg56,%vreg59
	Considering merging to GPR32 with %vreg59 in %vreg56
		RHS = %vreg59 [3728r,3744r:0)  0@3728r
		LHS = %vreg56 [3744r,3808r:0)  0@3744r
		merge %vreg56:0@3744r into %vreg59:0@3728r --> @3728r
		erased:	3744r	%vreg56<def> = COPY %vreg59; GPR32:%vreg56,%vreg59
		updated: 3728B	%vreg56<def> = COPY %W0; GPR32:%vreg56
	Success: %vreg59 -> %vreg56
	Result = %vreg56 [3728r,3808r:0)  0@3728r
64B	%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
	Considering merging to GPR64 with %vreg0 in %vreg1
		RHS = %vreg0 [48r,64r:0)  0@48r
		LHS = %vreg1 [64r,288r:0)  0@64r
		merge %vreg1:0@64r into %vreg0:0@48r --> @48r
		erased:	64r	%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
		updated: 48B	%vreg1<def> = COPY %X0; GPR64:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [48r,288r:0)  0@48r
80B	%vreg3<def> = COPY %vreg2; GPR32:%vreg3,%vreg2
	Considering merging to GPR32 with %vreg2 in %vreg3
		RHS = %vreg2 [32r,80r:0)  0@32r
		LHS = %vreg3 [80r,304r:0)  0@80r
		merge %vreg3:0@80r into %vreg2:0@32r --> @32r
		erased:	80r	%vreg3<def> = COPY %vreg2; GPR32:%vreg3,%vreg2
		updated: 32B	%vreg3<def> = COPY %W1; GPR32:%vreg3
	Success: %vreg2 -> %vreg3
	Result = %vreg3 [32r,304r:0)  0@32r
128B	%vreg8<def> = COPY %vreg7; GPR64all:%vreg8 GPR64sp:%vreg7
	Considering merging to GPR64sp with %vreg7 in %vreg8
		RHS = %vreg7 [112r,128r:0)  0@112r
		LHS = %vreg8 [128r,176r:0)  0@128r
		merge %vreg8:0@128r into %vreg7:0@112r --> @112r
		erased:	128r	%vreg8<def> = COPY %vreg7; GPR64all:%vreg8 GPR64sp:%vreg7
		updated: 112B	%vreg8<def> = ADDXri %vreg6, <ga:@BZ2_bzCompress>[TF=34], 0; GPR64sp:%vreg8 GPR64common:%vreg6
	Success: %vreg7 -> %vreg8
	Result = %vreg8 [112r,176r:0)  0@112r
144B	%vreg9<def> = COPY %vreg162; GPR64all:%vreg9 GPR64:%vreg162
	Considering merging to GPR64 with %vreg162 in %vreg9
		RHS = %vreg162 [16r,4272r:0)  0@16r
		LHS = %vreg9 [144r,192r:0)  0@144r
		merge %vreg9:0@144r into %vreg162:0@16r --> @16r
		erased:	144r	%vreg9<def> = COPY %vreg162; GPR64all:%vreg9 GPR64:%vreg162
		updated: 16B	%vreg9<def> = COPY %LR; GPR64:%vreg9
		updated: 4272B	%X1<def> = COPY %vreg9; GPR64:%vreg9
	Success: %vreg162 -> %vreg9
	Result = %vreg9 [16r,4272r:0)  0@16r
1184B	%vreg149<def> = COPY %vreg151; GPR32:%vreg149,%vreg151
	Considering merging to GPR32 with %vreg151 in %vreg149
		RHS = %vreg151 [1168r,1184r:0)  0@1168r
		LHS = %vreg149 [1184r,1280r:0)  0@1184r
		merge %vreg149:0@1184r into %vreg151:0@1168r --> @1168r
		erased:	1184r	%vreg149<def> = COPY %vreg151; GPR32:%vreg149,%vreg151
		updated: 1168B	%vreg149<def> = COPY %W0; GPR32:%vreg149
	Success: %vreg151 -> %vreg149
	Result = %vreg149 [1168r,1280r:0)  0@1168r
4256B	%X0<def> = COPY %vreg161; GPR64sp:%vreg161
	Considering merging %vreg161 with %X0
	Can only merge into reserved registers.
4272B	%X1<def> = COPY %vreg9; GPR64:%vreg9
	Considering merging %vreg9 with %X1
	Can only merge into reserved registers.
176B	%X0<def> = COPY %vreg8; GPR64sp:%vreg8
	Considering merging %vreg8 with %X0
	Can only merge into reserved registers.
192B	%X1<def> = COPY %vreg9; GPR64:%vreg9
	Considering merging %vreg9 with %X1
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
W30 [0B,16r:0)[208r,208d:14)[256e,256d:7)[1136r,1136d:9)[1248e,1248d:6)[2240r,2240d:11)[2320e,2320d:5)[2496r,2496d:10)[2576e,2576d:4)[3312r,3312d:13)[3392e,3392d:3)[3696r,3696d:12)[3776e,3776d:2)[4288r,4288d:8)[4336e,4336d:1)  0@0B-phi 1@4336e 2@3776e 3@3392e 4@2576e 5@2320e 6@1248e 7@256e 8@4288r 9@1136r 10@2496r 11@2240r 12@3696r 13@3312r 14@208r
W0 [0B,48r:0)[176r,208r:13)[1120r,1136r:8)[1136r,1168r:2)[2224r,2240r:10)[2240r,2272r:4)[2480r,2496r:9)[2496r,2528r:3)[3296r,3312r:12)[3312r,3344r:6)[3680r,3696r:11)[3696r,3728r:5)[4256r,4288r:7)[4384r,4400r:1)  0@0B-phi 1@4384r 2@1136r 3@2496r 4@2240r 5@3696r 6@3312r 7@4256r 8@1120r 9@2480r 10@2224r 11@3680r 12@3296r 13@176r
W1 [0B,32r:0)[192r,208r:2)[4272r,4288r:1)  0@0B-phi 1@4272r 2@192r
%vreg1 [48r,288r:0)  0@48r
%vreg3 [32r,304r:0)  0@32r
%vreg5 [320r,336r:0)  0@320r
%vreg6 [96r,112r:0)  0@96r
%vreg8 [112r,176r:0)  0@112r
%vreg9 [16r,4272r:0)  0@16r
%vreg12 [496r,512r:0)  0@496r
%vreg15 [448r,480r:0)  0@448r
%vreg18 [432r,448r:0)  0@432r
%vreg21 [640r,656r:0)  0@640r
%vreg23 [624r,656r:0)  0@624r
%vreg24 [608r,624r:0)  0@608r
%vreg25 [832r,928r:0)  0@832r
%vreg26 [800r,816r:0)  0@800r
%vreg27 [816r,832r:0)  0@816r
%vreg29 [864r,864d:0)  0@864r
%vreg30 [912r,928r:0)  0@912r
%vreg31 [928r,944r:0)  0@928r
%vreg33 [2944r,2960r:0)  0@2944r
%vreg37 [3136r,3152r:0)  0@3136r
%vreg39 [3120r,3136r:0)  0@3120r
%vreg40 [3104r,3120r:0)  0@3104r
%vreg42 [3088r,3152r:0)  0@3088r
%vreg43 [3072r,3088r:0)  0@3072r
%vreg45 [3456r,3472r:0)  0@3456r
%vreg46 [3440r,3456r:0)  0@3440r
%vreg47 [3344r,3424r:0)  0@3344r
%vreg50 [3264r,3296r:0)  0@3264r
%vreg51 [3504r,3520r:0)  0@3504r
%vreg54 [3584r,3600r:0)  0@3584r
%vreg55 [3568r,3584r:0)  0@3568r
%vreg56 [3728r,3808r:0)  0@3728r
%vreg57 [3808r,3824r:0)  0@3808r
%vreg60 [3648r,3680r:0)  0@3648r
%vreg64 [3904r,3920r:0)  0@3904r
%vreg65 [3888r,3904r:0)  0@3888r
%vreg67 [3872r,3920r:0)  0@3872r
%vreg68 [3856r,3872r:0)  0@3856r
%vreg69 [4032r,4096r:0)  0@4032r
%vreg70 [4048r,4080r:0)  0@4048r
%vreg72 [4064r,4080r:0)  0@4064r
%vreg73 [3968r,3984r:0)  0@3968r
%vreg74 [3200r,3216r:0)  0@3200r
%vreg75 [3008r,3024r:0)  0@3008r
%vreg77 [1872r,1888r:0)  0@1872r
%vreg81 [2064r,2080r:0)  0@2064r
%vreg83 [2048r,2064r:0)  0@2048r
%vreg84 [2032r,2048r:0)  0@2032r
%vreg86 [2016r,2080r:0)  0@2016r
%vreg87 [2000r,2016r:0)  0@2000r
%vreg90 [2384r,2400r:0)  0@2384r
%vreg91 [2368r,2384r:0)  0@2368r
%vreg92 [2272r,2352r:0)  0@2272r
%vreg95 [2192r,2224r:0)  0@2192r
%vreg96 [2528r,2608r:0)  0@2528r
%vreg97 [2608r,2624r:0)  0@2608r
%vreg100 [2448r,2480r:0)  0@2448r
%vreg104 [2704r,2720r:0)  0@2704r
%vreg105 [2688r,2704r:0)  0@2688r
%vreg107 [2672r,2720r:0)  0@2672r
%vreg108 [2656r,2672r:0)  0@2656r
%vreg109 [2832r,2896r:0)  0@2832r
%vreg110 [2848r,2880r:0)  0@2848r
%vreg112 [2864r,2880r:0)  0@2864r
%vreg113 [2768r,2784r:0)  0@2768r
%vreg114 [2128r,2144r:0)  0@2128r
%vreg115 [1936r,1952r:0)  0@1936r
%vreg117 [1040r,1056r:0)  0@1040r
%vreg119 [1392r,1408r:0)  0@1392r
%vreg121 [1600r,1616r:0)  0@1600r
%vreg122 [1808r,1824r:0)  0@1808r
%vreg123 [1664r,1760r:0)  0@1664r
%vreg125 [1744r,1760r:0)  0@1744r
%vreg128 [1712r,1728r:0)  0@1712r
%vreg130 [1696r,1728r:0)  0@1696r
%vreg131 [1680r,1696r:0)  0@1680r
%vreg132 [1456r,1552r:0)  0@1456r
%vreg134 [1536r,1552r:0)  0@1536r
%vreg137 [1504r,1520r:0)  0@1504r
%vreg139 [1488r,1520r:0)  0@1488r
%vreg140 [1472r,1488r:0)  0@1472r
%vreg143 [1200r,1328r:0)  0@1200r
%vreg144 [1216r,1328r:0)  0@1216r
%vreg145 [1328r,1344r:0)  0@1328r
%vreg148 [1296r,1312r:0)  0@1296r
%vreg149 [1168r,1280r:0)  0@1168r
%vreg152 [1088r,1120r:0)  0@1088r
%vreg153 [976r,992r:0)  0@976r
%vreg154 [704r,720r:0)  0@704r
%vreg155 [544r,560r:0)  0@544r
%vreg156 [368r,384r:0)  0@368r
%vreg158 [4368r,4384r:0)  0@4368r
%vreg159 [4176r,4192r:0)  0@4176r
%vreg161 [4192r,4256r:0)  0@4192r
RegMasks: 208r 1136r 2240r 2496r 3312r 3696r 4288r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzCompress: Post SSA
Frame Objects:
  fi#0: size=4, align=4, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=4, align=4, at location [SP]
  fi#3: size=1, align=1, at location [SP]
  fi#4: size=8, align=8, at location [SP]
Jump Tables:
  jt#0:  BB#9 BB#10 BB#17 BB#26
Function Live Ins: %X0 in %vreg0, %W1 in %vreg2, %LR in %vreg10

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %W1 %LR
16B		%vreg9<def> = COPY %LR; GPR64:%vreg9
32B		%vreg3<def> = COPY %W1; GPR32:%vreg3
48B		%vreg1<def> = COPY %X0; GPR64:%vreg1
96B		%vreg6<def> = ADRP <ga:@BZ2_bzCompress>[TF=1]; GPR64common:%vreg6
112B		%vreg8<def> = ADDXri %vreg6, <ga:@BZ2_bzCompress>[TF=34], 0; GPR64sp:%vreg8 GPR64common:%vreg6
160B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
176B		%X0<def> = COPY %vreg8; GPR64sp:%vreg8
192B		%X1<def> = COPY %vreg9; GPR64:%vreg9
208B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
224B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
240B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
256B		STACKMAP 0, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#3>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, %vreg1, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack3](align=1) LD8[FixedStack0](align=4) LD8[FixedStack4] LD8[FixedStack1] GPR32:%vreg3 GPR64:%vreg1
272B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
288B		STRXui %vreg1, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg1
304B		STRWui %vreg3, <fi#2>, 0; mem:ST4[FixedStack2] GPR32:%vreg3
320B		%vreg5<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg5
336B		CBNZX %vreg5, <BB#2>; GPR64:%vreg5
	    Successors according to CFG: BB#2 BB#1

352B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
368B		%vreg156<def> = MOVi32imm 4294967294; GPR32:%vreg156
384B		STRWui %vreg156, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg156
400B		B <BB#38>
	    Successors according to CFG: BB#38

416B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0
432B		%vreg18<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg18
448B		%vreg15<def> = LDRXui %vreg18, 6; mem:LD8[%state] GPR64:%vreg15 GPR64common:%vreg18
480B		STRXui %vreg15, <fi#4>, 0; mem:ST8[FixedStack4] GPR64:%vreg15
496B		%vreg12<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64:%vreg12
512B		CBNZX %vreg12, <BB#4>; GPR64:%vreg12
	    Successors according to CFG: BB#4 BB#3

528B	BB#3: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#2
544B		%vreg155<def> = MOVi32imm 4294967294; GPR32:%vreg155
560B		STRWui %vreg155, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg155
576B		B <BB#38>
	    Successors according to CFG: BB#38

592B	BB#4: derived from LLVM BB %if.end.3
	    Predecessors according to CFG: BB#2
608B		%vreg24<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg24
624B		%vreg23<def> = LDRXui %vreg24, 0; mem:LD8[%strm4] GPR64:%vreg23 GPR64common:%vreg24
640B		%vreg21<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg21
656B		%XZR<def> = SUBSXrr %vreg23, %vreg21, %NZCV<imp-def>; GPR64:%vreg23,%vreg21
672B		Bcc 0, <BB#6>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#6 BB#5

688B	BB#5: derived from LLVM BB %if.then.6
	    Predecessors according to CFG: BB#4
704B		%vreg154<def> = MOVi32imm 4294967294; GPR32:%vreg154
720B		STRWui %vreg154, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg154
736B		B <BB#38>
	    Successors according to CFG: BB#38

752B	BB#6: derived from LLVM BB %if.end.7
	    Predecessors according to CFG: BB#4
768B		B <BB#7>
	    Successors according to CFG: BB#7

784B	BB#7: derived from LLVM BB %preswitch
	    Predecessors according to CFG: BB#6 BB#15 BB#13
800B		%vreg26<def> = LDRXui <fi#4>, 0; mem:LD8[%s] GPR64common:%vreg26
816B		%vreg27<def> = LDRWui %vreg26, 2; mem:LD4[%mode] GPR32common:%vreg27 GPR64common:%vreg26
832B		%vreg25:sub_32<def,read-undef> = SUBSWri %vreg27, 1, 0, %NZCV<imp-def,dead>; GPR64common:%vreg25 GPR32common:%vreg27
864B		%vreg29<def,dead> = SUBSWri %vreg25:sub_32, 3, 0, %NZCV<imp-def>; GPR32:%vreg29 GPR64common:%vreg25
880B		Bcc 8, <BB#37>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#37 BB#8

896B	BB#8: derived from LLVM BB %preswitch
	    Predecessors according to CFG: BB#7
912B		%vreg30<def> = MOVaddrJT <jt#0>[TF=1], <jt#0>[TF=34]; GPR64common:%vreg30
928B		%vreg31<def> = LDRXroX %vreg30, %vreg25, 0, 1; mem:LD8[JumpTable] GPR64:%vreg31 GPR64common:%vreg30,%vreg25
944B		BR %vreg31; GPR64:%vreg31
	    Successors according to CFG: BB#9 BB#10 BB#17 BB#26

960B	BB#9: derived from LLVM BB %sw.bb
	    Predecessors according to CFG: BB#8
976B		%vreg153<def> = MOVi32imm 4294967295; GPR32:%vreg153
992B		STRWui %vreg153, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg153
1008B		B <BB#38>
	    Successors according to CFG: BB#38

1024B	BB#10: derived from LLVM BB %sw.bb.8
	    Predecessors according to CFG: BB#8
1040B		%vreg117<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg117
1056B		CBNZW %vreg117, <BB#12>; GPR32:%vreg117
	    Successors according to CFG: BB#12 BB#11

1072B	BB#11: derived from LLVM BB %if.then.10
	    Predecessors according to CFG: BB#10
1088B		%vreg152<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg152
1104B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1120B		%X0<def> = COPY %vreg152; GPR64:%vreg152
1136B		BL <ga:@handle_compress>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>
1152B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1168B		%vreg149<def> = COPY %W0; GPR32:%vreg149
1200B		%vreg143<def> = MOVi32imm 1; GPR32:%vreg143
1216B		%vreg144<def> = MOVi32imm 4294967294; GPR32:%vreg144
1232B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1248B		STACKMAP 1, 0, 0, <fi#3>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack3](align=1) LD8[FixedStack0](align=4)
1264B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1280B		STRBBui %vreg149, <fi#3>, 0; mem:ST1[FixedStack3] GPR32:%vreg149
1296B		%vreg148<def> = LDRBBui <fi#3>, 0; mem:LD1[FixedStack3] GPR32common:%vreg148
1312B		%WZR<def> = SUBSWri %vreg148, 0, 0, %NZCV<imp-def>; GPR32common:%vreg148
1328B		%vreg145<def> = CSELWr %vreg143, %vreg144, 1, %NZCV<imp-use,kill>; GPR32:%vreg145,%vreg143,%vreg144
1344B		STRWui %vreg145, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg145
1360B		B <BB#38>
	    Successors according to CFG: BB#38

1376B	BB#12: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#10
1392B		%vreg119<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32common:%vreg119
1408B		%WZR<def> = SUBSWri %vreg119, 1, 0, %NZCV<imp-def>; GPR32common:%vreg119
1424B		Bcc 1, <BB#14>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#14 BB#13

1440B	BB#13: derived from LLVM BB %if.then.13
	    Predecessors according to CFG: BB#12
1456B		%vreg132<def> = MOVi32imm 3; GPR32:%vreg132
1472B		%vreg140<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg140
1488B		%vreg139<def> = LDRWui %vreg140, 2; mem:LD4[%avail_in] GPR32:%vreg139 GPR64common:%vreg140
1504B		%vreg137<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg137
1520B		STRWui %vreg139, %vreg137, 4; mem:ST4[%avail_in_expect] GPR32:%vreg139 GPR64common:%vreg137
1536B		%vreg134<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg134
1552B		STRWui %vreg132, %vreg134, 2; mem:ST4[%mode14] GPR32:%vreg132 GPR64common:%vreg134
1568B		B <BB#7>
	    Successors according to CFG: BB#7

1584B	BB#14: derived from LLVM BB %if.else.15
	    Predecessors according to CFG: BB#12
1600B		%vreg121<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32common:%vreg121
1616B		%WZR<def> = SUBSWri %vreg121, 2, 0, %NZCV<imp-def>; GPR32common:%vreg121
1632B		Bcc 1, <BB#16>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#16 BB#15

1648B	BB#15: derived from LLVM BB %if.then.18
	    Predecessors according to CFG: BB#14
1664B		%vreg123<def> = MOVi32imm 4; GPR32:%vreg123
1680B		%vreg131<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg131
1696B		%vreg130<def> = LDRWui %vreg131, 2; mem:LD4[%avail_in19] GPR32:%vreg130 GPR64common:%vreg131
1712B		%vreg128<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg128
1728B		STRWui %vreg130, %vreg128, 4; mem:ST4[%avail_in_expect20] GPR32:%vreg130 GPR64common:%vreg128
1744B		%vreg125<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg125
1760B		STRWui %vreg123, %vreg125, 2; mem:ST4[%mode21] GPR32:%vreg123 GPR64common:%vreg125
1776B		B <BB#7>
	    Successors according to CFG: BB#7

1792B	BB#16: derived from LLVM BB %if.else.22
	    Predecessors according to CFG: BB#14
1808B		%vreg122<def> = MOVi32imm 4294967294; GPR32:%vreg122
1824B		STRWui %vreg122, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg122
1840B		B <BB#38>
	    Successors according to CFG: BB#38

1856B	BB#17: derived from LLVM BB %sw.bb.23
	    Predecessors according to CFG: BB#8
1872B		%vreg77<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32common:%vreg77
1888B		%WZR<def> = SUBSWri %vreg77, 1, 0, %NZCV<imp-def>; GPR32common:%vreg77
1904B		Bcc 0, <BB#19>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#19 BB#18

1920B	BB#18: derived from LLVM BB %if.then.26
	    Predecessors according to CFG: BB#17
1936B		%vreg115<def> = MOVi32imm 4294967295; GPR32:%vreg115
1952B		STRWui %vreg115, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg115
1968B		B <BB#38>
	    Successors according to CFG: BB#38

1984B	BB#19: derived from LLVM BB %if.end.27
	    Predecessors according to CFG: BB#17
2000B		%vreg87<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg87
2016B		%vreg86<def> = LDRWui %vreg87, 4; mem:LD4[%avail_in_expect28] GPR32:%vreg86 GPR64common:%vreg87
2032B		%vreg84<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg84
2048B		%vreg83<def> = LDRXui %vreg84, 0; mem:LD8[%strm29] GPR64common:%vreg83,%vreg84
2064B		%vreg81<def> = LDRWui %vreg83, 2; mem:LD4[%avail_in30] GPR32:%vreg81 GPR64common:%vreg83
2080B		%WZR<def> = SUBSWrr %vreg86, %vreg81, %NZCV<imp-def>; GPR32:%vreg86,%vreg81
2096B		Bcc 0, <BB#21>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#21 BB#20

2112B	BB#20: derived from LLVM BB %if.then.33
	    Predecessors according to CFG: BB#19
2128B		%vreg114<def> = MOVi32imm 4294967295; GPR32:%vreg114
2144B		STRWui %vreg114, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg114
2160B		B <BB#38>
	    Successors according to CFG: BB#38

2176B	BB#21: derived from LLVM BB %if.end.34
	    Predecessors according to CFG: BB#19
2192B		%vreg95<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg95
2208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2224B		%X0<def> = COPY %vreg95; GPR64:%vreg95
2240B		BL <ga:@handle_compress>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>
2256B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2272B		%vreg92<def> = COPY %W0; GPR32:%vreg92
2304B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2320B		STACKMAP 2, 0, 0, <fi#3>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack3](align=1) LD8[FixedStack0](align=4) LD8[FixedStack4]
2336B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2352B		STRBBui %vreg92, <fi#3>, 0; mem:ST1[FixedStack3] GPR32:%vreg92
2368B		%vreg91<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg91
2384B		%vreg90<def> = LDRWui %vreg91, 4; mem:LD4[%avail_in_expect36] GPR32common:%vreg90 GPR64common:%vreg91
2400B		%WZR<def> = SUBSWri %vreg90, 0, 0, %NZCV<imp-def>; GPR32common:%vreg90
2416B		Bcc 8, <BB#24>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#24 BB#22

2432B	BB#22: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#21
2448B		%vreg100<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64:%vreg100
2464B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2480B		%X0<def> = COPY %vreg100; GPR64:%vreg100
2496B		BL <ga:@isempty_RL>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>
2512B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2528B		%vreg96<def> = COPY %W0; GPR32:%vreg96
2560B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2576B		STACKMAP 3, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack4]
2592B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2608B		%vreg97<def> = UBFMWri %vreg96, 0, 7; GPR32:%vreg97,%vreg96
2624B		CBZW %vreg97, <BB#24>; GPR32:%vreg97
	    Successors according to CFG: BB#24 BB#23

2640B	BB#23: derived from LLVM BB %lor.lhs.false.41
	    Predecessors according to CFG: BB#22
2656B		%vreg108<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg108
2672B		%vreg107<def> = LDRWui %vreg108, 30; mem:LD4[%state_out_pos] GPR32:%vreg107 GPR64common:%vreg108
2688B		%vreg105<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg105
2704B		%vreg104<def> = LDRWui %vreg105, 29; mem:LD4[%numZ] GPR32:%vreg104 GPR64common:%vreg105
2720B		%WZR<def> = SUBSWrr %vreg107, %vreg104, %NZCV<imp-def>; GPR32:%vreg107,%vreg104
2736B		Bcc 10, <BB#25>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#25 BB#24

2752B	BB#24: derived from LLVM BB %if.then.44
	    Predecessors according to CFG: BB#21 BB#22 BB#23
2768B		%vreg113<def> = MOVi32imm 2; GPR32:%vreg113
2784B		STRWui %vreg113, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg113
2800B		B <BB#38>
	    Successors according to CFG: BB#38

2816B	BB#25: derived from LLVM BB %if.end.45
	    Predecessors according to CFG: BB#23
2832B		%vreg109<def> = MOVi32imm 1; GPR32:%vreg109
2848B		%vreg110<def> = MOVi32imm 2; GPR32:%vreg110
2864B		%vreg112<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg112
2880B		STRWui %vreg110, %vreg112, 2; mem:ST4[%mode46] GPR32:%vreg110 GPR64common:%vreg112
2896B		STRWui %vreg109, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg109
2912B		B <BB#38>
	    Successors according to CFG: BB#38

2928B	BB#26: derived from LLVM BB %sw.bb.47
	    Predecessors according to CFG: BB#8
2944B		%vreg33<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32common:%vreg33
2960B		%WZR<def> = SUBSWri %vreg33, 2, 0, %NZCV<imp-def>; GPR32common:%vreg33
2976B		Bcc 0, <BB#28>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#28 BB#27

2992B	BB#27: derived from LLVM BB %if.then.50
	    Predecessors according to CFG: BB#26
3008B		%vreg75<def> = MOVi32imm 4294967295; GPR32:%vreg75
3024B		STRWui %vreg75, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg75
3040B		B <BB#38>
	    Successors according to CFG: BB#38

3056B	BB#28: derived from LLVM BB %if.end.51
	    Predecessors according to CFG: BB#26
3072B		%vreg43<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg43
3088B		%vreg42<def> = LDRWui %vreg43, 4; mem:LD4[%avail_in_expect52] GPR32:%vreg42 GPR64common:%vreg43
3104B		%vreg40<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg40
3120B		%vreg39<def> = LDRXui %vreg40, 0; mem:LD8[%strm53] GPR64common:%vreg39,%vreg40
3136B		%vreg37<def> = LDRWui %vreg39, 2; mem:LD4[%avail_in54] GPR32:%vreg37 GPR64common:%vreg39
3152B		%WZR<def> = SUBSWrr %vreg42, %vreg37, %NZCV<imp-def>; GPR32:%vreg42,%vreg37
3168B		Bcc 0, <BB#30>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#30 BB#29

3184B	BB#29: derived from LLVM BB %if.then.57
	    Predecessors according to CFG: BB#28
3200B		%vreg74<def> = MOVi32imm 4294967295; GPR32:%vreg74
3216B		STRWui %vreg74, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg74
3232B		B <BB#38>
	    Successors according to CFG: BB#38

3248B	BB#30: derived from LLVM BB %if.end.58
	    Predecessors according to CFG: BB#28
3264B		%vreg50<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg50
3280B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3296B		%X0<def> = COPY %vreg50; GPR64:%vreg50
3312B		BL <ga:@handle_compress>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>
3328B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3344B		%vreg47<def> = COPY %W0; GPR32:%vreg47
3376B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3392B		STACKMAP 4, 0, 0, <fi#3>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack3](align=1) LD8[FixedStack0](align=4) LD8[FixedStack4]
3408B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3424B		STRBBui %vreg47, <fi#3>, 0; mem:ST1[FixedStack3] GPR32:%vreg47
3440B		%vreg46<def> = LDRBBui <fi#3>, 0; mem:LD1[FixedStack3] GPR32:%vreg46
3456B		%vreg45<def> = UBFMWri %vreg46, 0, 7; GPR32:%vreg45,%vreg46
3472B		CBNZW %vreg45, <BB#32>; GPR32:%vreg45
	    Successors according to CFG: BB#32 BB#31

3488B	BB#31: derived from LLVM BB %if.then.61
	    Predecessors according to CFG: BB#30
3504B		%vreg51<def> = MOVi32imm 4294967295; GPR32:%vreg51
3520B		STRWui %vreg51, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg51
3536B		B <BB#38>
	    Successors according to CFG: BB#38

3552B	BB#32: derived from LLVM BB %if.end.62
	    Predecessors according to CFG: BB#30
3568B		%vreg55<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg55
3584B		%vreg54<def> = LDRWui %vreg55, 4; mem:LD4[%avail_in_expect63] GPR32common:%vreg54 GPR64common:%vreg55
3600B		%WZR<def> = SUBSWri %vreg54, 0, 0, %NZCV<imp-def>; GPR32common:%vreg54
3616B		Bcc 8, <BB#35>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#35 BB#33

3632B	BB#33: derived from LLVM BB %lor.lhs.false.66
	    Predecessors according to CFG: BB#32
3648B		%vreg60<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64:%vreg60
3664B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3680B		%X0<def> = COPY %vreg60; GPR64:%vreg60
3696B		BL <ga:@isempty_RL>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>
3712B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3728B		%vreg56<def> = COPY %W0; GPR32:%vreg56
3760B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3776B		STACKMAP 5, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack4]
3792B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3808B		%vreg57<def> = UBFMWri %vreg56, 0, 7; GPR32:%vreg57,%vreg56
3824B		CBZW %vreg57, <BB#35>; GPR32:%vreg57
	    Successors according to CFG: BB#35 BB#34

3840B	BB#34: derived from LLVM BB %lor.lhs.false.69
	    Predecessors according to CFG: BB#33
3856B		%vreg68<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg68
3872B		%vreg67<def> = LDRWui %vreg68, 30; mem:LD4[%state_out_pos70] GPR32:%vreg67 GPR64common:%vreg68
3888B		%vreg65<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg65
3904B		%vreg64<def> = LDRWui %vreg65, 29; mem:LD4[%numZ71] GPR32:%vreg64 GPR64common:%vreg65
3920B		%WZR<def> = SUBSWrr %vreg67, %vreg64, %NZCV<imp-def>; GPR32:%vreg67,%vreg64
3936B		Bcc 10, <BB#36>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#36 BB#35

3952B	BB#35: derived from LLVM BB %if.then.74
	    Predecessors according to CFG: BB#32 BB#33 BB#34
3968B		%vreg73<def> = MOVi32imm 3; GPR32:%vreg73
3984B		STRWui %vreg73, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg73
4000B		B <BB#38>
	    Successors according to CFG: BB#38

4016B	BB#36: derived from LLVM BB %if.end.75
	    Predecessors according to CFG: BB#34
4032B		%vreg69<def> = MOVi32imm 4; GPR32:%vreg69
4048B		%vreg70<def> = MOVi32imm 1; GPR32:%vreg70
4064B		%vreg72<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg72
4080B		STRWui %vreg70, %vreg72, 2; mem:ST4[%mode76] GPR32:%vreg70 GPR64common:%vreg72
4096B		STRWui %vreg69, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg69
4112B		B <BB#38>
	    Successors according to CFG: BB#38

4128B	BB#37: derived from LLVM BB %sw.epilog
	    Predecessors according to CFG: BB#7
4144B		STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
	    Successors according to CFG: BB#38

4160B	BB#38: derived from LLVM BB %return
	    Predecessors according to CFG: BB#31 BB#36 BB#35 BB#29 BB#27 BB#25 BB#24 BB#20 BB#18 BB#16 BB#11 BB#9 BB#37 BB#5 BB#3 BB#1
4176B		%vreg159<def> = ADRP <ga:@BZ2_bzCompress>[TF=1]; GPR64common:%vreg159
4192B		%vreg161<def> = ADDXri %vreg159, <ga:@BZ2_bzCompress>[TF=34], 0; GPR64sp:%vreg161 GPR64common:%vreg159
4240B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4256B		%X0<def> = COPY %vreg161; GPR64sp:%vreg161
4272B		%X1<def> = COPY %vreg9; GPR64:%vreg9
4288B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
4304B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4320B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4336B		STACKMAP 6, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
4352B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4368B		%vreg158<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0] GPR32:%vreg158
4384B		%W0<def> = COPY %vreg158; GPR32:%vreg158
4400B		RET_ReallyLR %W0<imp-use>

# End machine code for function BZ2_bzCompress.

handleMove 1456B -> 1544B: %vreg132<def> = MOVi32imm 3; GPR32:%vreg132
     %vreg132:	[1456r,1552r:0)  0@1456r
        -->	[1544r,1552r:0)  0@1544r
handleMove 1664B -> 1752B: %vreg123<def> = MOVi32imm 4; GPR32:%vreg123
     %vreg123:	[1664r,1760r:0)  0@1664r
        -->	[1752r,1760r:0)  0@1752r
handleMove 2016B -> 2056B: %vreg86<def> = LDRWui %vreg87, 4; mem:LD4[%avail_in_expect28] GPR32:%vreg86 GPR64common:%vreg87
     %vreg86:	[2016r,2080r:0)  0@2016r
        -->	[2056r,2080r:0)  0@2056r
     %vreg87:	[2000r,2016r:0)  0@2000r
        -->	[2000r,2056r:0)  0@2000r
handleMove 2000B -> 2040B: %vreg87<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg87
     %vreg87:	[2000r,2056r:0)  0@2000r
        -->	[2040r,2056r:0)  0@2040r
handleMove 2672B -> 2696B: %vreg107<def> = LDRWui %vreg108, 30; mem:LD4[%state_out_pos] GPR32:%vreg107 GPR64common:%vreg108
     %vreg107:	[2672r,2720r:0)  0@2672r
        -->	[2696r,2720r:0)  0@2696r
     %vreg108:	[2656r,2672r:0)  0@2656r
        -->	[2656r,2696r:0)  0@2656r
handleMove 2848B -> 2872B: %vreg110<def> = MOVi32imm 2; GPR32:%vreg110
     %vreg110:	[2848r,2880r:0)  0@2848r
        -->	[2872r,2880r:0)  0@2872r
handleMove 2832B -> 2868B: %vreg109<def> = MOVi32imm 1; GPR32:%vreg109
     %vreg109:	[2832r,2896r:0)  0@2832r
        -->	[2868r,2896r:0)  0@2868r
handleMove 3088B -> 3128B: %vreg42<def> = LDRWui %vreg43, 4; mem:LD4[%avail_in_expect52] GPR32:%vreg42 GPR64common:%vreg43
     %vreg42:	[3088r,3152r:0)  0@3088r
        -->	[3128r,3152r:0)  0@3128r
     %vreg43:	[3072r,3088r:0)  0@3072r
        -->	[3072r,3128r:0)  0@3072r
handleMove 3072B -> 3112B: %vreg43<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg43
     %vreg43:	[3072r,3128r:0)  0@3072r
        -->	[3112r,3128r:0)  0@3112r
handleMove 3872B -> 3896B: %vreg67<def> = LDRWui %vreg68, 30; mem:LD4[%state_out_pos70] GPR32:%vreg67 GPR64common:%vreg68
     %vreg67:	[3872r,3920r:0)  0@3872r
        -->	[3896r,3920r:0)  0@3896r
     %vreg68:	[3856r,3872r:0)  0@3856r
        -->	[3856r,3896r:0)  0@3856r
handleMove 4048B -> 4072B: %vreg70<def> = MOVi32imm 1; GPR32:%vreg70
     %vreg70:	[4048r,4080r:0)  0@4048r
        -->	[4072r,4080r:0)  0@4072r
handleMove 4032B -> 4068B: %vreg69<def> = MOVi32imm 4; GPR32:%vreg69
     %vreg69:	[4032r,4096r:0)  0@4032r
        -->	[4068r,4096r:0)  0@4068r
********** GREEDY REGISTER ALLOCATION **********
********** Function: BZ2_bzCompress
********** INTERVALS **********
W30 [0B,16r:0)[208r,208d:14)[256e,256d:7)[1136r,1136d:9)[1248e,1248d:6)[2240r,2240d:11)[2320e,2320d:5)[2496r,2496d:10)[2576e,2576d:4)[3312r,3312d:13)[3392e,3392d:3)[3696r,3696d:12)[3776e,3776d:2)[4288r,4288d:8)[4336e,4336d:1)  0@0B-phi 1@4336e 2@3776e 3@3392e 4@2576e 5@2320e 6@1248e 7@256e 8@4288r 9@1136r 10@2496r 11@2240r 12@3696r 13@3312r 14@208r
W0 [0B,48r:0)[176r,208r:13)[1120r,1136r:8)[1136r,1168r:2)[2224r,2240r:10)[2240r,2272r:4)[2480r,2496r:9)[2496r,2528r:3)[3296r,3312r:12)[3312r,3344r:6)[3680r,3696r:11)[3696r,3728r:5)[4256r,4288r:7)[4384r,4400r:1)  0@0B-phi 1@4384r 2@1136r 3@2496r 4@2240r 5@3696r 6@3312r 7@4256r 8@1120r 9@2480r 10@2224r 11@3680r 12@3296r 13@176r
W1 [0B,32r:0)[192r,208r:2)[4272r,4288r:1)  0@0B-phi 1@4272r 2@192r
%vreg1 [48r,288r:0)  0@48r
%vreg3 [32r,304r:0)  0@32r
%vreg5 [320r,336r:0)  0@320r
%vreg6 [96r,112r:0)  0@96r
%vreg8 [112r,176r:0)  0@112r
%vreg9 [16r,4272r:0)  0@16r
%vreg12 [496r,512r:0)  0@496r
%vreg15 [448r,480r:0)  0@448r
%vreg18 [432r,448r:0)  0@432r
%vreg21 [640r,656r:0)  0@640r
%vreg23 [624r,656r:0)  0@624r
%vreg24 [608r,624r:0)  0@608r
%vreg25 [832r,928r:0)  0@832r
%vreg26 [800r,816r:0)  0@800r
%vreg27 [816r,832r:0)  0@816r
%vreg29 [864r,864d:0)  0@864r
%vreg30 [912r,928r:0)  0@912r
%vreg31 [928r,944r:0)  0@928r
%vreg33 [2944r,2960r:0)  0@2944r
%vreg37 [3136r,3152r:0)  0@3136r
%vreg39 [3120r,3136r:0)  0@3120r
%vreg40 [3104r,3120r:0)  0@3104r
%vreg42 [3128r,3152r:0)  0@3128r
%vreg43 [3112r,3128r:0)  0@3112r
%vreg45 [3456r,3472r:0)  0@3456r
%vreg46 [3440r,3456r:0)  0@3440r
%vreg47 [3344r,3424r:0)  0@3344r
%vreg50 [3264r,3296r:0)  0@3264r
%vreg51 [3504r,3520r:0)  0@3504r
%vreg54 [3584r,3600r:0)  0@3584r
%vreg55 [3568r,3584r:0)  0@3568r
%vreg56 [3728r,3808r:0)  0@3728r
%vreg57 [3808r,3824r:0)  0@3808r
%vreg60 [3648r,3680r:0)  0@3648r
%vreg64 [3904r,3920r:0)  0@3904r
%vreg65 [3888r,3904r:0)  0@3888r
%vreg67 [3896r,3920r:0)  0@3896r
%vreg68 [3856r,3896r:0)  0@3856r
%vreg69 [4068r,4096r:0)  0@4068r
%vreg70 [4072r,4080r:0)  0@4072r
%vreg72 [4064r,4080r:0)  0@4064r
%vreg73 [3968r,3984r:0)  0@3968r
%vreg74 [3200r,3216r:0)  0@3200r
%vreg75 [3008r,3024r:0)  0@3008r
%vreg77 [1872r,1888r:0)  0@1872r
%vreg81 [2064r,2080r:0)  0@2064r
%vreg83 [2048r,2064r:0)  0@2048r
%vreg84 [2032r,2048r:0)  0@2032r
%vreg86 [2056r,2080r:0)  0@2056r
%vreg87 [2040r,2056r:0)  0@2040r
%vreg90 [2384r,2400r:0)  0@2384r
%vreg91 [2368r,2384r:0)  0@2368r
%vreg92 [2272r,2352r:0)  0@2272r
%vreg95 [2192r,2224r:0)  0@2192r
%vreg96 [2528r,2608r:0)  0@2528r
%vreg97 [2608r,2624r:0)  0@2608r
%vreg100 [2448r,2480r:0)  0@2448r
%vreg104 [2704r,2720r:0)  0@2704r
%vreg105 [2688r,2704r:0)  0@2688r
%vreg107 [2696r,2720r:0)  0@2696r
%vreg108 [2656r,2696r:0)  0@2656r
%vreg109 [2868r,2896r:0)  0@2868r
%vreg110 [2872r,2880r:0)  0@2872r
%vreg112 [2864r,2880r:0)  0@2864r
%vreg113 [2768r,2784r:0)  0@2768r
%vreg114 [2128r,2144r:0)  0@2128r
%vreg115 [1936r,1952r:0)  0@1936r
%vreg117 [1040r,1056r:0)  0@1040r
%vreg119 [1392r,1408r:0)  0@1392r
%vreg121 [1600r,1616r:0)  0@1600r
%vreg122 [1808r,1824r:0)  0@1808r
%vreg123 [1752r,1760r:0)  0@1752r
%vreg125 [1744r,1760r:0)  0@1744r
%vreg128 [1712r,1728r:0)  0@1712r
%vreg130 [1696r,1728r:0)  0@1696r
%vreg131 [1680r,1696r:0)  0@1680r
%vreg132 [1544r,1552r:0)  0@1544r
%vreg134 [1536r,1552r:0)  0@1536r
%vreg137 [1504r,1520r:0)  0@1504r
%vreg139 [1488r,1520r:0)  0@1488r
%vreg140 [1472r,1488r:0)  0@1472r
%vreg143 [1200r,1328r:0)  0@1200r
%vreg144 [1216r,1328r:0)  0@1216r
%vreg145 [1328r,1344r:0)  0@1328r
%vreg148 [1296r,1312r:0)  0@1296r
%vreg149 [1168r,1280r:0)  0@1168r
%vreg152 [1088r,1120r:0)  0@1088r
%vreg153 [976r,992r:0)  0@976r
%vreg154 [704r,720r:0)  0@704r
%vreg155 [544r,560r:0)  0@544r
%vreg156 [368r,384r:0)  0@368r
%vreg158 [4368r,4384r:0)  0@4368r
%vreg159 [4176r,4192r:0)  0@4176r
%vreg161 [4192r,4256r:0)  0@4192r
RegMasks: 208r 1136r 2240r 2496r 3312r 3696r 4288r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzCompress: Post SSA
Frame Objects:
  fi#0: size=4, align=4, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=4, align=4, at location [SP]
  fi#3: size=1, align=1, at location [SP]
  fi#4: size=8, align=8, at location [SP]
Jump Tables:
  jt#0:  BB#9 BB#10 BB#17 BB#26
Function Live Ins: %X0 in %vreg0, %W1 in %vreg2, %LR in %vreg10

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %W1 %LR
16B		%vreg9<def> = COPY %LR; GPR64:%vreg9
32B		%vreg3<def> = COPY %W1; GPR32:%vreg3
48B		%vreg1<def> = COPY %X0; GPR64:%vreg1
96B		%vreg6<def> = ADRP <ga:@BZ2_bzCompress>[TF=1]; GPR64common:%vreg6
112B		%vreg8<def> = ADDXri %vreg6, <ga:@BZ2_bzCompress>[TF=34], 0; GPR64sp:%vreg8 GPR64common:%vreg6
160B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
176B		%X0<def> = COPY %vreg8; GPR64sp:%vreg8
192B		%X1<def> = COPY %vreg9; GPR64:%vreg9
208B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
224B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
240B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
256B		STACKMAP 0, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#3>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, %vreg1, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack3](align=1) LD8[FixedStack0](align=4) LD8[FixedStack4] LD8[FixedStack1] GPR32:%vreg3 GPR64:%vreg1
272B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
288B		STRXui %vreg1, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg1
304B		STRWui %vreg3, <fi#2>, 0; mem:ST4[FixedStack2] GPR32:%vreg3
320B		%vreg5<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg5
336B		CBNZX %vreg5, <BB#2>; GPR64:%vreg5
	    Successors according to CFG: BB#2 BB#1

352B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
368B		%vreg156<def> = MOVi32imm 4294967294; GPR32:%vreg156
384B		STRWui %vreg156, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg156
400B		B <BB#38>
	    Successors according to CFG: BB#38

416B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0
432B		%vreg18<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg18
448B		%vreg15<def> = LDRXui %vreg18, 6; mem:LD8[%state] GPR64:%vreg15 GPR64common:%vreg18
480B		STRXui %vreg15, <fi#4>, 0; mem:ST8[FixedStack4] GPR64:%vreg15
496B		%vreg12<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64:%vreg12
512B		CBNZX %vreg12, <BB#4>; GPR64:%vreg12
	    Successors according to CFG: BB#4 BB#3

528B	BB#3: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#2
544B		%vreg155<def> = MOVi32imm 4294967294; GPR32:%vreg155
560B		STRWui %vreg155, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg155
576B		B <BB#38>
	    Successors according to CFG: BB#38

592B	BB#4: derived from LLVM BB %if.end.3
	    Predecessors according to CFG: BB#2
608B		%vreg24<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg24
624B		%vreg23<def> = LDRXui %vreg24, 0; mem:LD8[%strm4] GPR64:%vreg23 GPR64common:%vreg24
640B		%vreg21<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg21
656B		%XZR<def> = SUBSXrr %vreg23, %vreg21, %NZCV<imp-def>; GPR64:%vreg23,%vreg21
672B		Bcc 0, <BB#6>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#6 BB#5

688B	BB#5: derived from LLVM BB %if.then.6
	    Predecessors according to CFG: BB#4
704B		%vreg154<def> = MOVi32imm 4294967294; GPR32:%vreg154
720B		STRWui %vreg154, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg154
736B		B <BB#38>
	    Successors according to CFG: BB#38

752B	BB#6: derived from LLVM BB %if.end.7
	    Predecessors according to CFG: BB#4
768B		B <BB#7>
	    Successors according to CFG: BB#7

784B	BB#7: derived from LLVM BB %preswitch
	    Predecessors according to CFG: BB#6 BB#15 BB#13
800B		%vreg26<def> = LDRXui <fi#4>, 0; mem:LD8[%s] GPR64common:%vreg26
816B		%vreg27<def> = LDRWui %vreg26, 2; mem:LD4[%mode] GPR32common:%vreg27 GPR64common:%vreg26
832B		%vreg25:sub_32<def,read-undef> = SUBSWri %vreg27, 1, 0, %NZCV<imp-def,dead>; GPR64common:%vreg25 GPR32common:%vreg27
864B		%vreg29<def,dead> = SUBSWri %vreg25:sub_32, 3, 0, %NZCV<imp-def>; GPR32:%vreg29 GPR64common:%vreg25
880B		Bcc 8, <BB#37>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#37 BB#8

896B	BB#8: derived from LLVM BB %preswitch
	    Predecessors according to CFG: BB#7
912B		%vreg30<def> = MOVaddrJT <jt#0>[TF=1], <jt#0>[TF=34]; GPR64common:%vreg30
928B		%vreg31<def> = LDRXroX %vreg30, %vreg25, 0, 1; mem:LD8[JumpTable] GPR64:%vreg31 GPR64common:%vreg30,%vreg25
944B		BR %vreg31; GPR64:%vreg31
	    Successors according to CFG: BB#9 BB#10 BB#17 BB#26

960B	BB#9: derived from LLVM BB %sw.bb
	    Predecessors according to CFG: BB#8
976B		%vreg153<def> = MOVi32imm 4294967295; GPR32:%vreg153
992B		STRWui %vreg153, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg153
1008B		B <BB#38>
	    Successors according to CFG: BB#38

1024B	BB#10: derived from LLVM BB %sw.bb.8
	    Predecessors according to CFG: BB#8
1040B		%vreg117<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg117
1056B		CBNZW %vreg117, <BB#12>; GPR32:%vreg117
	    Successors according to CFG: BB#12 BB#11

1072B	BB#11: derived from LLVM BB %if.then.10
	    Predecessors according to CFG: BB#10
1088B		%vreg152<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg152
1104B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1120B		%X0<def> = COPY %vreg152; GPR64:%vreg152
1136B		BL <ga:@handle_compress>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>
1152B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1168B		%vreg149<def> = COPY %W0; GPR32:%vreg149
1200B		%vreg143<def> = MOVi32imm 1; GPR32:%vreg143
1216B		%vreg144<def> = MOVi32imm 4294967294; GPR32:%vreg144
1232B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1248B		STACKMAP 1, 0, 0, <fi#3>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack3](align=1) LD8[FixedStack0](align=4)
1264B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1280B		STRBBui %vreg149, <fi#3>, 0; mem:ST1[FixedStack3] GPR32:%vreg149
1296B		%vreg148<def> = LDRBBui <fi#3>, 0; mem:LD1[FixedStack3] GPR32common:%vreg148
1312B		%WZR<def> = SUBSWri %vreg148, 0, 0, %NZCV<imp-def>; GPR32common:%vreg148
1328B		%vreg145<def> = CSELWr %vreg143, %vreg144, 1, %NZCV<imp-use,kill>; GPR32:%vreg145,%vreg143,%vreg144
1344B		STRWui %vreg145, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg145
1360B		B <BB#38>
	    Successors according to CFG: BB#38

1376B	BB#12: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#10
1392B		%vreg119<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32common:%vreg119
1408B		%WZR<def> = SUBSWri %vreg119, 1, 0, %NZCV<imp-def>; GPR32common:%vreg119
1424B		Bcc 1, <BB#14>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#14 BB#13

1440B	BB#13: derived from LLVM BB %if.then.13
	    Predecessors according to CFG: BB#12
1472B		%vreg140<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg140
1488B		%vreg139<def> = LDRWui %vreg140, 2; mem:LD4[%avail_in] GPR32:%vreg139 GPR64common:%vreg140
1504B		%vreg137<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg137
1520B		STRWui %vreg139, %vreg137, 4; mem:ST4[%avail_in_expect] GPR32:%vreg139 GPR64common:%vreg137
1536B		%vreg134<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg134
1544B		%vreg132<def> = MOVi32imm 3; GPR32:%vreg132
1552B		STRWui %vreg132, %vreg134, 2; mem:ST4[%mode14] GPR32:%vreg132 GPR64common:%vreg134
1568B		B <BB#7>
	    Successors according to CFG: BB#7

1584B	BB#14: derived from LLVM BB %if.else.15
	    Predecessors according to CFG: BB#12
1600B		%vreg121<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32common:%vreg121
1616B		%WZR<def> = SUBSWri %vreg121, 2, 0, %NZCV<imp-def>; GPR32common:%vreg121
1632B		Bcc 1, <BB#16>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#16 BB#15

1648B	BB#15: derived from LLVM BB %if.then.18
	    Predecessors according to CFG: BB#14
1680B		%vreg131<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg131
1696B		%vreg130<def> = LDRWui %vreg131, 2; mem:LD4[%avail_in19] GPR32:%vreg130 GPR64common:%vreg131
1712B		%vreg128<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg128
1728B		STRWui %vreg130, %vreg128, 4; mem:ST4[%avail_in_expect20] GPR32:%vreg130 GPR64common:%vreg128
1744B		%vreg125<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg125
1752B		%vreg123<def> = MOVi32imm 4; GPR32:%vreg123
1760B		STRWui %vreg123, %vreg125, 2; mem:ST4[%mode21] GPR32:%vreg123 GPR64common:%vreg125
1776B		B <BB#7>
	    Successors according to CFG: BB#7

1792B	BB#16: derived from LLVM BB %if.else.22
	    Predecessors according to CFG: BB#14
1808B		%vreg122<def> = MOVi32imm 4294967294; GPR32:%vreg122
1824B		STRWui %vreg122, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg122
1840B		B <BB#38>
	    Successors according to CFG: BB#38

1856B	BB#17: derived from LLVM BB %sw.bb.23
	    Predecessors according to CFG: BB#8
1872B		%vreg77<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32common:%vreg77
1888B		%WZR<def> = SUBSWri %vreg77, 1, 0, %NZCV<imp-def>; GPR32common:%vreg77
1904B		Bcc 0, <BB#19>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#19 BB#18

1920B	BB#18: derived from LLVM BB %if.then.26
	    Predecessors according to CFG: BB#17
1936B		%vreg115<def> = MOVi32imm 4294967295; GPR32:%vreg115
1952B		STRWui %vreg115, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg115
1968B		B <BB#38>
	    Successors according to CFG: BB#38

1984B	BB#19: derived from LLVM BB %if.end.27
	    Predecessors according to CFG: BB#17
2032B		%vreg84<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg84
2040B		%vreg87<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg87
2048B		%vreg83<def> = LDRXui %vreg84, 0; mem:LD8[%strm29] GPR64common:%vreg83,%vreg84
2056B		%vreg86<def> = LDRWui %vreg87, 4; mem:LD4[%avail_in_expect28] GPR32:%vreg86 GPR64common:%vreg87
2064B		%vreg81<def> = LDRWui %vreg83, 2; mem:LD4[%avail_in30] GPR32:%vreg81 GPR64common:%vreg83
2080B		%WZR<def> = SUBSWrr %vreg86, %vreg81, %NZCV<imp-def>; GPR32:%vreg86,%vreg81
2096B		Bcc 0, <BB#21>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#21 BB#20

2112B	BB#20: derived from LLVM BB %if.then.33
	    Predecessors according to CFG: BB#19
2128B		%vreg114<def> = MOVi32imm 4294967295; GPR32:%vreg114
2144B		STRWui %vreg114, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg114
2160B		B <BB#38>
	    Successors according to CFG: BB#38

2176B	BB#21: derived from LLVM BB %if.end.34
	    Predecessors according to CFG: BB#19
2192B		%vreg95<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg95
2208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2224B		%X0<def> = COPY %vreg95; GPR64:%vreg95
2240B		BL <ga:@handle_compress>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>
2256B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2272B		%vreg92<def> = COPY %W0; GPR32:%vreg92
2304B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2320B		STACKMAP 2, 0, 0, <fi#3>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack3](align=1) LD8[FixedStack0](align=4) LD8[FixedStack4]
2336B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2352B		STRBBui %vreg92, <fi#3>, 0; mem:ST1[FixedStack3] GPR32:%vreg92
2368B		%vreg91<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg91
2384B		%vreg90<def> = LDRWui %vreg91, 4; mem:LD4[%avail_in_expect36] GPR32common:%vreg90 GPR64common:%vreg91
2400B		%WZR<def> = SUBSWri %vreg90, 0, 0, %NZCV<imp-def>; GPR32common:%vreg90
2416B		Bcc 8, <BB#24>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#24 BB#22

2432B	BB#22: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#21
2448B		%vreg100<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64:%vreg100
2464B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2480B		%X0<def> = COPY %vreg100; GPR64:%vreg100
2496B		BL <ga:@isempty_RL>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>
2512B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2528B		%vreg96<def> = COPY %W0; GPR32:%vreg96
2560B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2576B		STACKMAP 3, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack4]
2592B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2608B		%vreg97<def> = UBFMWri %vreg96, 0, 7; GPR32:%vreg97,%vreg96
2624B		CBZW %vreg97, <BB#24>; GPR32:%vreg97
	    Successors according to CFG: BB#24 BB#23

2640B	BB#23: derived from LLVM BB %lor.lhs.false.41
	    Predecessors according to CFG: BB#22
2656B		%vreg108<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg108
2688B		%vreg105<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg105
2696B		%vreg107<def> = LDRWui %vreg108, 30; mem:LD4[%state_out_pos] GPR32:%vreg107 GPR64common:%vreg108
2704B		%vreg104<def> = LDRWui %vreg105, 29; mem:LD4[%numZ] GPR32:%vreg104 GPR64common:%vreg105
2720B		%WZR<def> = SUBSWrr %vreg107, %vreg104, %NZCV<imp-def>; GPR32:%vreg107,%vreg104
2736B		Bcc 10, <BB#25>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#25 BB#24

2752B	BB#24: derived from LLVM BB %if.then.44
	    Predecessors according to CFG: BB#21 BB#22 BB#23
2768B		%vreg113<def> = MOVi32imm 2; GPR32:%vreg113
2784B		STRWui %vreg113, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg113
2800B		B <BB#38>
	    Successors according to CFG: BB#38

2816B	BB#25: derived from LLVM BB %if.end.45
	    Predecessors according to CFG: BB#23
2864B		%vreg112<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg112
2868B		%vreg109<def> = MOVi32imm 1; GPR32:%vreg109
2872B		%vreg110<def> = MOVi32imm 2; GPR32:%vreg110
2880B		STRWui %vreg110, %vreg112, 2; mem:ST4[%mode46] GPR32:%vreg110 GPR64common:%vreg112
2896B		STRWui %vreg109, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg109
2912B		B <BB#38>
	    Successors according to CFG: BB#38

2928B	BB#26: derived from LLVM BB %sw.bb.47
	    Predecessors according to CFG: BB#8
2944B		%vreg33<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32common:%vreg33
2960B		%WZR<def> = SUBSWri %vreg33, 2, 0, %NZCV<imp-def>; GPR32common:%vreg33
2976B		Bcc 0, <BB#28>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#28 BB#27

2992B	BB#27: derived from LLVM BB %if.then.50
	    Predecessors according to CFG: BB#26
3008B		%vreg75<def> = MOVi32imm 4294967295; GPR32:%vreg75
3024B		STRWui %vreg75, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg75
3040B		B <BB#38>
	    Successors according to CFG: BB#38

3056B	BB#28: derived from LLVM BB %if.end.51
	    Predecessors according to CFG: BB#26
3104B		%vreg40<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg40
3112B		%vreg43<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg43
3120B		%vreg39<def> = LDRXui %vreg40, 0; mem:LD8[%strm53] GPR64common:%vreg39,%vreg40
3128B		%vreg42<def> = LDRWui %vreg43, 4; mem:LD4[%avail_in_expect52] GPR32:%vreg42 GPR64common:%vreg43
3136B		%vreg37<def> = LDRWui %vreg39, 2; mem:LD4[%avail_in54] GPR32:%vreg37 GPR64common:%vreg39
3152B		%WZR<def> = SUBSWrr %vreg42, %vreg37, %NZCV<imp-def>; GPR32:%vreg42,%vreg37
3168B		Bcc 0, <BB#30>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#30 BB#29

3184B	BB#29: derived from LLVM BB %if.then.57
	    Predecessors according to CFG: BB#28
3200B		%vreg74<def> = MOVi32imm 4294967295; GPR32:%vreg74
3216B		STRWui %vreg74, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg74
3232B		B <BB#38>
	    Successors according to CFG: BB#38

3248B	BB#30: derived from LLVM BB %if.end.58
	    Predecessors according to CFG: BB#28
3264B		%vreg50<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg50
3280B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3296B		%X0<def> = COPY %vreg50; GPR64:%vreg50
3312B		BL <ga:@handle_compress>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>
3328B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3344B		%vreg47<def> = COPY %W0; GPR32:%vreg47
3376B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3392B		STACKMAP 4, 0, 0, <fi#3>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack3](align=1) LD8[FixedStack0](align=4) LD8[FixedStack4]
3408B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3424B		STRBBui %vreg47, <fi#3>, 0; mem:ST1[FixedStack3] GPR32:%vreg47
3440B		%vreg46<def> = LDRBBui <fi#3>, 0; mem:LD1[FixedStack3] GPR32:%vreg46
3456B		%vreg45<def> = UBFMWri %vreg46, 0, 7; GPR32:%vreg45,%vreg46
3472B		CBNZW %vreg45, <BB#32>; GPR32:%vreg45
	    Successors according to CFG: BB#32 BB#31

3488B	BB#31: derived from LLVM BB %if.then.61
	    Predecessors according to CFG: BB#30
3504B		%vreg51<def> = MOVi32imm 4294967295; GPR32:%vreg51
3520B		STRWui %vreg51, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg51
3536B		B <BB#38>
	    Successors according to CFG: BB#38

3552B	BB#32: derived from LLVM BB %if.end.62
	    Predecessors according to CFG: BB#30
3568B		%vreg55<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg55
3584B		%vreg54<def> = LDRWui %vreg55, 4; mem:LD4[%avail_in_expect63] GPR32common:%vreg54 GPR64common:%vreg55
3600B		%WZR<def> = SUBSWri %vreg54, 0, 0, %NZCV<imp-def>; GPR32common:%vreg54
3616B		Bcc 8, <BB#35>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#35 BB#33

3632B	BB#33: derived from LLVM BB %lor.lhs.false.66
	    Predecessors according to CFG: BB#32
3648B		%vreg60<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64:%vreg60
3664B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3680B		%X0<def> = COPY %vreg60; GPR64:%vreg60
3696B		BL <ga:@isempty_RL>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>
3712B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3728B		%vreg56<def> = COPY %W0; GPR32:%vreg56
3760B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3776B		STACKMAP 5, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack4]
3792B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3808B		%vreg57<def> = UBFMWri %vreg56, 0, 7; GPR32:%vreg57,%vreg56
3824B		CBZW %vreg57, <BB#35>; GPR32:%vreg57
	    Successors according to CFG: BB#35 BB#34

3840B	BB#34: derived from LLVM BB %lor.lhs.false.69
	    Predecessors according to CFG: BB#33
3856B		%vreg68<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg68
3888B		%vreg65<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg65
3896B		%vreg67<def> = LDRWui %vreg68, 30; mem:LD4[%state_out_pos70] GPR32:%vreg67 GPR64common:%vreg68
3904B		%vreg64<def> = LDRWui %vreg65, 29; mem:LD4[%numZ71] GPR32:%vreg64 GPR64common:%vreg65
3920B		%WZR<def> = SUBSWrr %vreg67, %vreg64, %NZCV<imp-def>; GPR32:%vreg67,%vreg64
3936B		Bcc 10, <BB#36>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#36 BB#35

3952B	BB#35: derived from LLVM BB %if.then.74
	    Predecessors according to CFG: BB#32 BB#33 BB#34
3968B		%vreg73<def> = MOVi32imm 3; GPR32:%vreg73
3984B		STRWui %vreg73, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg73
4000B		B <BB#38>
	    Successors according to CFG: BB#38

4016B	BB#36: derived from LLVM BB %if.end.75
	    Predecessors according to CFG: BB#34
4064B		%vreg72<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg72
4068B		%vreg69<def> = MOVi32imm 4; GPR32:%vreg69
4072B		%vreg70<def> = MOVi32imm 1; GPR32:%vreg70
4080B		STRWui %vreg70, %vreg72, 2; mem:ST4[%mode76] GPR32:%vreg70 GPR64common:%vreg72
4096B		STRWui %vreg69, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg69
4112B		B <BB#38>
	    Successors according to CFG: BB#38

4128B	BB#37: derived from LLVM BB %sw.epilog
	    Predecessors according to CFG: BB#7
4144B		STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
	    Successors according to CFG: BB#38

4160B	BB#38: derived from LLVM BB %return
	    Predecessors according to CFG: BB#31 BB#36 BB#35 BB#29 BB#27 BB#25 BB#24 BB#20 BB#18 BB#16 BB#11 BB#9 BB#37 BB#5 BB#3 BB#1
4176B		%vreg159<def> = ADRP <ga:@BZ2_bzCompress>[TF=1]; GPR64common:%vreg159
4192B		%vreg161<def> = ADDXri %vreg159, <ga:@BZ2_bzCompress>[TF=34], 0; GPR64sp:%vreg161 GPR64common:%vreg159
4240B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4256B		%X0<def> = COPY %vreg161; GPR64sp:%vreg161
4272B		%X1<def> = COPY %vreg9; GPR64:%vreg9
4288B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
4304B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4320B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4336B		STACKMAP 6, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
4352B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4368B		%vreg158<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0] GPR32:%vreg158
4384B		%W0<def> = COPY %vreg158; GPR32:%vreg158
4400B		RET_ReallyLR %W0<imp-use>

# End machine code for function BZ2_bzCompress.


selectOrSplit GPR64:%vreg9 [16r,4272r:0)  0@16r w=6.507731e-04
hints: %X1
missed hint %X1
Analyze counted 3 instrs in 2 blocks, through 37 blocks.
%X1	static = 1.0 worse than no bundles
%X8	static = 1.0 worse than no bundles
%X9	static = 1.0 worse than no bundles
%X10	static = 1.0 worse than no bundles
%X11	static = 1.0 worse than no bundles
%X12	static = 1.0 worse than no bundles
%X13	static = 1.0 worse than no bundles
%X14	static = 1.0 worse than no bundles
%X15	static = 1.0 worse than no bundles
%X16	static = 1.0 worse than no bundles
%X17	static = 1.0 worse than no bundles
%X18	static = 1.0 worse than no bundles
%X0	no positive bundles
%X2	static = 1.0 worse than no bundles
%X3	static = 1.0 worse than no bundles
%X4	static = 1.0 worse than no bundles
%X5	static = 1.0 worse than no bundles
%X6	static = 1.0 worse than no bundles
%X7	static = 1.0 worse than no bundles
assigning %vreg9 to %X19: W19 [16r,4272r:0)  0@16r

selectOrSplit GPR32:%vreg3 [32r,304r:0)  0@32r w=4.508928e-03
hints: %W1
missed hint %W1
Analyze counted 3 instrs in 1 blocks, through 0 blocks.
%W1	no positive bundles
%W8	no positive bundles
%W9	no positive bundles
%W10	no positive bundles
%W11	no positive bundles
%W12	no positive bundles
%W13	no positive bundles
%W14	no positive bundles
%W15	no positive bundles
%W16	no positive bundles
%W17	no positive bundles
%W18	no positive bundles
%W0	no positive bundles
%W2	no positive bundles
%W3	no positive bundles
%W4	no positive bundles
%W5	no positive bundles
%W6	no positive bundles
%W7	no positive bundles
%W19	no positive bundles
assigning %vreg3 to %W20: W20 [32r,304r:0)  0@32r

selectOrSplit GPR64:%vreg1 [48r,288r:0)  0@48r w=4.734375e-03
hints: %X0
missed hint %X0
Analyze counted 3 instrs in 1 blocks, through 0 blocks.
%X0	no positive bundles
%X8	no positive bundles
%X9	no positive bundles
%X10	no positive bundles
%X11	no positive bundles
%X12	no positive bundles
%X13	no positive bundles
%X14	no positive bundles
%X15	no positive bundles
%X16	no positive bundles
%X17	no positive bundles
%X18	no positive bundles
%X1	no positive bundles
%X2	no positive bundles
%X3	no positive bundles
%X4	no positive bundles
%X5	no positive bundles
%X6	no positive bundles
%X7	no positive bundles
%X19	no positive bundles
%X20	no positive bundles
assigning %vreg1 to %X21: W21 [48r,288r:0)  0@48r

selectOrSplit GPR64sp:%vreg8 [112r,176r:0)  0@112r w=4.353448e-03
hints: %X0
assigning %vreg8 to %X0: W0 [112r,176r:0)  0@112r

selectOrSplit GPR64:%vreg152 [1088r,1120r:0)  0@1088r w=3.817877e-05
hints: %X0
assigning %vreg152 to %X0: W0 [1088r,1120r:0)  0@1088r

selectOrSplit GPR32:%vreg149 [1168r,1280r:0)  0@1168r w=3.221333e-05
hints: %W0
assigning %vreg149 to %W0: W0 [1168r,1280r:0)  0@1168r

selectOrSplit GPR64:%vreg95 [2192r,2224r:0)  0@2192r w=1.901452e-05
hints: %X0
assigning %vreg95 to %X0: W0 [2192r,2224r:0)  0@2192r

selectOrSplit GPR32:%vreg92 [2272r,2352r:0)  0@2272r w=1.711307e-05
hints: %W0
assigning %vreg92 to %W0: W0 [2272r,2352r:0)  0@2272r

selectOrSplit GPR64:%vreg100 [2448r,2480r:0)  0@2448r w=9.432400e-06
hints: %X0
assigning %vreg100 to %X0: W0 [2448r,2480r:0)  0@2448r

selectOrSplit GPR32:%vreg96 [2528r,2608r:0)  0@2528r w=8.489161e-06
hints: %W0
assigning %vreg96 to %W0: W0 [2528r,2608r:0)  0@2528r

selectOrSplit GPR64:%vreg50 [3264r,3296r:0)  0@3264r w=1.901452e-05
hints: %X0
assigning %vreg50 to %X0: W0 [3264r,3296r:0)  0@3264r

selectOrSplit GPR32:%vreg47 [3344r,3424r:0)  0@3344r w=1.711307e-05
hints: %W0
assigning %vreg47 to %W0: W0 [3344r,3424r:0)  0@3344r

selectOrSplit GPR64:%vreg60 [3648r,3680r:0)  0@3648r w=4.791061e-06
hints: %X0
assigning %vreg60 to %X0: W0 [3648r,3680r:0)  0@3648r

selectOrSplit GPR32:%vreg56 [3728r,3808r:0)  0@3728r w=4.311955e-06
hints: %W0
assigning %vreg56 to %W0: W0 [3728r,3808r:0)  0@3728r

selectOrSplit GPR64sp:%vreg161 [4192r,4256r:0)  0@4192r w=4.353448e-03
hints: %X0
assigning %vreg161 to %X0: W0 [4192r,4256r:0)  0@4192r

selectOrSplit GPR32:%vreg158 [4368r,4384r:0)  0@4368r w=inf
hints: %W0
assigning %vreg158 to %W0: W0 [4368r,4384r:0)  0@4368r

selectOrSplit GPR64common:%vreg25 [832r,928r:0)  0@832r w=1.189562e-03
assigning %vreg25 to %X8: W8 [832r,928r:0)  0@832r

selectOrSplit GPR64common:%vreg6 [96r,112r:0)  0@96r w=inf
assigning %vreg6 to %X8: W8 [96r,112r:0)  0@96r

selectOrSplit GPR64:%vreg5 [320r,336r:0)  0@320r w=inf
assigning %vreg5 to %X8: W8 [320r,336r:0)  0@320r

selectOrSplit GPR32:%vreg156 [368r,384r:0)  0@368r w=inf
assigning %vreg156 to %W8: W8 [368r,384r:0)  0@368r

selectOrSplit GPR64common:%vreg18 [432r,448r:0)  0@432r w=inf
assigning %vreg18 to %X8: W8 [432r,448r:0)  0@432r

selectOrSplit GPR64:%vreg15 [448r,480r:0)  0@448r w=inf
assigning %vreg15 to %X8: W8 [448r,480r:0)  0@448r

selectOrSplit GPR64:%vreg12 [496r,512r:0)  0@496r w=inf
assigning %vreg12 to %X8: W8 [496r,512r:0)  0@496r

selectOrSplit GPR32:%vreg155 [544r,560r:0)  0@544r w=inf
assigning %vreg155 to %W8: W8 [544r,560r:0)  0@544r

selectOrSplit GPR64common:%vreg24 [608r,624r:0)  0@608r w=inf
assigning %vreg24 to %X8: W8 [608r,624r:0)  0@608r

selectOrSplit GPR64:%vreg23 [624r,656r:0)  0@624r w=1.157296e-03
assigning %vreg23 to %X8: W8 [624r,656r:0)  0@624r

selectOrSplit GPR64:%vreg21 [640r,656r:0)  0@640r w=inf
assigning %vreg21 to %X9: W9 [640r,656r:0)  0@640r

selectOrSplit GPR32:%vreg154 [704r,720r:0)  0@704r w=inf
assigning %vreg154 to %W8: W8 [704r,720r:0)  0@704r

selectOrSplit GPR64common:%vreg26 [800r,816r:0)  0@800r w=inf
assigning %vreg26 to %X8: W8 [800r,816r:0)  0@800r

selectOrSplit GPR32common:%vreg27 [816r,832r:0)  0@816r w=inf
assigning %vreg27 to %W8: W8 [816r,832r:0)  0@816r

selectOrSplit GPR32:%vreg29 [864r,864d:0)  0@864r w=inf
assigning %vreg29 to %W9: W9 [864r,864d:0)  0@864r

selectOrSplit GPR64common:%vreg30 [912r,928r:0)  0@912r w=inf
assigning %vreg30 to %X9: W9 [912r,928r:0)  0@912r

selectOrSplit GPR64:%vreg31 [928r,944r:0)  0@928r w=inf
assigning %vreg31 to %X8: W8 [928r,944r:0)  0@928r

selectOrSplit GPR32:%vreg153 [976r,992r:0)  0@976r w=inf
assigning %vreg153 to %W8: W8 [976r,992r:0)  0@976r

selectOrSplit GPR32:%vreg117 [1040r,1056r:0)  0@1040r w=inf
assigning %vreg117 to %W8: W8 [1040r,1056r:0)  0@1040r

selectOrSplit GPR32:%vreg143 [1200r,1328r:0)  0@1200r w=1.546395e-05
assigning %vreg143 to %W8: W8 [1200r,1328r:0)  0@1200r

selectOrSplit GPR32:%vreg144 [1216r,1328r:0)  0@1216r w=1.594719e-05
assigning %vreg144 to %W9: W9 [1216r,1328r:0)  0@1216r

selectOrSplit GPR32common:%vreg148 [1296r,1312r:0)  0@1296r w=inf
assigning %vreg148 to %W10: W10 [1296r,1312r:0)  0@1296r

selectOrSplit GPR32:%vreg145 [1328r,1344r:0)  0@1328r w=inf
assigning %vreg145 to %W8: W8 [1328r,1344r:0)  0@1328r

selectOrSplit GPR32common:%vreg119 [1392r,1408r:0)  0@1392r w=inf
assigning %vreg119 to %W8: W8 [1392r,1408r:0)  0@1392r

selectOrSplit GPR64common:%vreg140 [1472r,1488r:0)  0@1472r w=inf
assigning %vreg140 to %X8: W8 [1472r,1488r:0)  0@1472r

selectOrSplit GPR32:%vreg139 [1488r,1520r:0)  0@1488r w=1.882626e-05
assigning %vreg139 to %W8: W8 [1488r,1520r:0)  0@1488r

selectOrSplit GPR64common:%vreg137 [1504r,1520r:0)  0@1504r w=inf
assigning %vreg137 to %X9: W9 [1504r,1520r:0)  0@1504r

selectOrSplit GPR64common:%vreg134 [1536r,1552r:0)  0@1536r w=1.955035e-05
assigning %vreg134 to %X8: W8 [1536r,1552r:0)  0@1536r

selectOrSplit GPR32:%vreg132 [1544r,1552r:0)  0@1544r w=inf
assigning %vreg132 to %W9: W9 [1544r,1552r:0)  0@1544r

selectOrSplit GPR32common:%vreg121 [1600r,1616r:0)  0@1600r w=inf
assigning %vreg121 to %W8: W8 [1600r,1616r:0)  0@1600r

selectOrSplit GPR64common:%vreg131 [1680r,1696r:0)  0@1680r w=inf
assigning %vreg131 to %X8: W8 [1680r,1696r:0)  0@1680r

selectOrSplit GPR32:%vreg130 [1696r,1728r:0)  0@1696r w=9.339011e-06
assigning %vreg130 to %W8: W8 [1696r,1728r:0)  0@1696r

selectOrSplit GPR64common:%vreg128 [1712r,1728r:0)  0@1712r w=inf
assigning %vreg128 to %X9: W9 [1712r,1728r:0)  0@1712r

selectOrSplit GPR64common:%vreg125 [1744r,1760r:0)  0@1744r w=9.698203e-06
assigning %vreg125 to %X8: W8 [1744r,1760r:0)  0@1744r

selectOrSplit GPR32:%vreg123 [1752r,1760r:0)  0@1752r w=inf
assigning %vreg123 to %W9: W9 [1752r,1760r:0)  0@1752r

selectOrSplit GPR32:%vreg122 [1808r,1824r:0)  0@1808r w=inf
assigning %vreg122 to %W8: W8 [1808r,1824r:0)  0@1808r

selectOrSplit GPR32common:%vreg77 [1872r,1888r:0)  0@1872r w=inf
assigning %vreg77 to %W8: W8 [1872r,1888r:0)  0@1872r

selectOrSplit GPR32:%vreg115 [1936r,1952r:0)  0@1936r w=inf
assigning %vreg115 to %W8: W8 [1936r,1952r:0)  0@1936r

selectOrSplit GPR64common:%vreg84 [2032r,2048r:0)  0@2032r w=3.925463e-05
assigning %vreg84 to %X8: W8 [2032r,2048r:0)  0@2032r

selectOrSplit GPR64common:%vreg87 [2040r,2056r:0)  0@2040r w=3.925463e-05
assigning %vreg87 to %X9: W9 [2040r,2056r:0)  0@2040r

selectOrSplit GPR64common:%vreg83 [2048r,2064r:0)  0@2048r w=3.925463e-05
assigning %vreg83 to %X8: W8 [2048r,2064r:0)  0@2048r

selectOrSplit GPR32:%vreg86 [2056r,2080r:0)  0@2056r w=3.851398e-05
assigning %vreg86 to %W9: W9 [2056r,2080r:0)  0@2056r

selectOrSplit GPR32:%vreg81 [2064r,2080r:0)  0@2064r w=inf
assigning %vreg81 to %W8: W8 [2064r,2080r:0)  0@2064r

selectOrSplit GPR32:%vreg114 [2128r,2144r:0)  0@2128r w=inf
assigning %vreg114 to %W8: W8 [2128r,2144r:0)  0@2128r

selectOrSplit GPR64common:%vreg91 [2368r,2384r:0)  0@2368r w=inf
assigning %vreg91 to %X8: W8 [2368r,2384r:0)  0@2368r

selectOrSplit GPR32common:%vreg90 [2384r,2400r:0)  0@2384r w=inf
assigning %vreg90 to %W8: W8 [2384r,2400r:0)  0@2384r

selectOrSplit GPR32:%vreg97 [2608r,2624r:0)  0@2608r w=inf
assigning %vreg97 to %W8: W8 [2608r,2624r:0)  0@2608r

selectOrSplit GPR64common:%vreg108 [2656r,2696r:0)  0@2656r w=4.657377e-06
assigning %vreg108 to %X8: W8 [2656r,2696r:0)  0@2656r

selectOrSplit GPR64common:%vreg105 [2688r,2704r:0)  0@2688r w=4.926072e-06
assigning %vreg105 to %X9: W9 [2688r,2704r:0)  0@2688r

selectOrSplit GPR32:%vreg107 [2696r,2720r:0)  0@2696r w=4.833127e-06
assigning %vreg107 to %W8: W8 [2696r,2720r:0)  0@2696r

selectOrSplit GPR32:%vreg104 [2704r,2720r:0)  0@2704r w=inf
assigning %vreg104 to %W9: W9 [2704r,2720r:0)  0@2704r

selectOrSplit GPR32:%vreg113 [2768r,2784r:0)  0@2768r w=inf
assigning %vreg113 to %W8: W8 [2768r,2784r:0)  0@2768r

selectOrSplit GPR64common:%vreg112 [2864r,2880r:0)  0@2864r w=2.463036e-06
assigning %vreg112 to %X8: W8 [2864r,2880r:0)  0@2864r

selectOrSplit GPR32:%vreg109 [2868r,2896r:0)  0@2868r w=1.196989e-06
assigning %vreg109 to %W9: W9 [2868r,2896r:0)  0@2868r

selectOrSplit GPR32:%vreg110 [2872r,2880r:0)  0@2872r w=inf
assigning %vreg110 to %W10: W10 [2872r,2880r:0)  0@2872r

selectOrSplit GPR32common:%vreg33 [2944r,2960r:0)  0@2944r w=inf
assigning %vreg33 to %W8: W8 [2944r,2960r:0)  0@2944r

selectOrSplit GPR32:%vreg75 [3008r,3024r:0)  0@3008r w=inf
assigning %vreg75 to %W8: W8 [3008r,3024r:0)  0@3008r

selectOrSplit GPR64common:%vreg40 [3104r,3120r:0)  0@3104r w=3.925463e-05
assigning %vreg40 to %X8: W8 [3104r,3120r:0)  0@3104r

selectOrSplit GPR64common:%vreg43 [3112r,3128r:0)  0@3112r w=3.925463e-05
assigning %vreg43 to %X9: W9 [3112r,3128r:0)  0@3112r

selectOrSplit GPR64common:%vreg39 [3120r,3136r:0)  0@3120r w=3.925463e-05
assigning %vreg39 to %X8: W8 [3120r,3136r:0)  0@3120r

selectOrSplit GPR32:%vreg42 [3128r,3152r:0)  0@3128r w=3.851398e-05
assigning %vreg42 to %W9: W9 [3128r,3152r:0)  0@3128r

selectOrSplit GPR32:%vreg37 [3136r,3152r:0)  0@3136r w=inf
assigning %vreg37 to %W8: W8 [3136r,3152r:0)  0@3136r

selectOrSplit GPR32:%vreg74 [3200r,3216r:0)  0@3200r w=inf
assigning %vreg74 to %W8: W8 [3200r,3216r:0)  0@3200r

selectOrSplit GPR32:%vreg46 [3440r,3456r:0)  0@3440r w=inf
assigning %vreg46 to %W8: W8 [3440r,3456r:0)  0@3440r

selectOrSplit GPR32:%vreg45 [3456r,3472r:0)  0@3456r w=inf
assigning %vreg45 to %W8: W8 [3456r,3472r:0)  0@3456r

selectOrSplit GPR32:%vreg51 [3504r,3520r:0)  0@3504r w=inf
assigning %vreg51 to %W8: W8 [3504r,3520r:0)  0@3504r

selectOrSplit GPR64common:%vreg55 [3568r,3584r:0)  0@3568r w=inf
assigning %vreg55 to %X8: W8 [3568r,3584r:0)  0@3568r

selectOrSplit GPR32common:%vreg54 [3584r,3600r:0)  0@3584r w=inf
assigning %vreg54 to %W8: W8 [3584r,3600r:0)  0@3584r

selectOrSplit GPR32:%vreg57 [3808r,3824r:0)  0@3808r w=inf
assigning %vreg57 to %W8: W8 [3808r,3824r:0)  0@3808r

selectOrSplit GPR64common:%vreg68 [3856r,3896r:0)  0@3856r w=2.328688e-06
assigning %vreg68 to %X8: W8 [3856r,3896r:0)  0@3856r

selectOrSplit GPR64common:%vreg65 [3888r,3904r:0)  0@3888r w=2.463036e-06
assigning %vreg65 to %X9: W9 [3888r,3904r:0)  0@3888r

selectOrSplit GPR32:%vreg67 [3896r,3920r:0)  0@3896r w=2.416564e-06
assigning %vreg67 to %W8: W8 [3896r,3920r:0)  0@3896r

selectOrSplit GPR32:%vreg64 [3904r,3920r:0)  0@3904r w=inf
assigning %vreg64 to %W9: W9 [3904r,3920r:0)  0@3904r

selectOrSplit GPR32:%vreg73 [3968r,3984r:0)  0@3968r w=inf
assigning %vreg73 to %W8: W8 [3968r,3984r:0)  0@3968r

selectOrSplit GPR64common:%vreg72 [4064r,4080r:0)  0@4064r w=1.231518e-06
assigning %vreg72 to %X8: W8 [4064r,4080r:0)  0@4064r

selectOrSplit GPR32:%vreg69 [4068r,4096r:0)  0@4068r w=5.984947e-07
assigning %vreg69 to %W9: W9 [4068r,4096r:0)  0@4068r

selectOrSplit GPR32:%vreg70 [4072r,4080r:0)  0@4072r w=inf
assigning %vreg70 to %W10: W10 [4072r,4080r:0)  0@4072r

selectOrSplit GPR64common:%vreg159 [4176r,4192r:0)  0@4176r w=inf
assigning %vreg159 to %X8: W8 [4176r,4192r:0)  0@4176r

********** STACK TRANSFORMATION METADATA **********
********** Function: BZ2_bzCompress
********** REGISTER MAP **********
[%vreg1 -> %X21] GPR64
[%vreg3 -> %W20] GPR32
[%vreg5 -> %X8] GPR64
[%vreg6 -> %X8] GPR64common
[%vreg8 -> %X0] GPR64sp
[%vreg9 -> %X19] GPR64
[%vreg12 -> %X8] GPR64
[%vreg15 -> %X8] GPR64
[%vreg18 -> %X8] GPR64common
[%vreg21 -> %X9] GPR64
[%vreg23 -> %X8] GPR64
[%vreg24 -> %X8] GPR64common
[%vreg25 -> %X8] GPR64common
[%vreg26 -> %X8] GPR64common
[%vreg27 -> %W8] GPR32common
[%vreg29 -> %W9] GPR32
[%vreg30 -> %X9] GPR64common
[%vreg31 -> %X8] GPR64
[%vreg33 -> %W8] GPR32common
[%vreg37 -> %W8] GPR32
[%vreg39 -> %X8] GPR64common
[%vreg40 -> %X8] GPR64common
[%vreg42 -> %W9] GPR32
[%vreg43 -> %X9] GPR64common
[%vreg45 -> %W8] GPR32
[%vreg46 -> %W8] GPR32
[%vreg47 -> %W0] GPR32
[%vreg50 -> %X0] GPR64
[%vreg51 -> %W8] GPR32
[%vreg54 -> %W8] GPR32common
[%vreg55 -> %X8] GPR64common
[%vreg56 -> %W0] GPR32
[%vreg57 -> %W8] GPR32
[%vreg60 -> %X0] GPR64
[%vreg64 -> %W9] GPR32
[%vreg65 -> %X9] GPR64common
[%vreg67 -> %W8] GPR32
[%vreg68 -> %X8] GPR64common
[%vreg69 -> %W9] GPR32
[%vreg70 -> %W10] GPR32
[%vreg72 -> %X8] GPR64common
[%vreg73 -> %W8] GPR32
[%vreg74 -> %W8] GPR32
[%vreg75 -> %W8] GPR32
[%vreg77 -> %W8] GPR32common
[%vreg81 -> %W8] GPR32
[%vreg83 -> %X8] GPR64common
[%vreg84 -> %X8] GPR64common
[%vreg86 -> %W9] GPR32
[%vreg87 -> %X9] GPR64common
[%vreg90 -> %W8] GPR32common
[%vreg91 -> %X8] GPR64common
[%vreg92 -> %W0] GPR32
[%vreg95 -> %X0] GPR64
[%vreg96 -> %W0] GPR32
[%vreg97 -> %W8] GPR32
[%vreg100 -> %X0] GPR64
[%vreg104 -> %W9] GPR32
[%vreg105 -> %X9] GPR64common
[%vreg107 -> %W8] GPR32
[%vreg108 -> %X8] GPR64common
[%vreg109 -> %W9] GPR32
[%vreg110 -> %W10] GPR32
[%vreg112 -> %X8] GPR64common
[%vreg113 -> %W8] GPR32
[%vreg114 -> %W8] GPR32
[%vreg115 -> %W8] GPR32
[%vreg117 -> %W8] GPR32
[%vreg119 -> %W8] GPR32common
[%vreg121 -> %W8] GPR32common
[%vreg122 -> %W8] GPR32
[%vreg123 -> %W9] GPR32
[%vreg125 -> %X8] GPR64common
[%vreg128 -> %X9] GPR64common
[%vreg130 -> %W8] GPR32
[%vreg131 -> %X8] GPR64common
[%vreg132 -> %W9] GPR32
[%vreg134 -> %X8] GPR64common
[%vreg137 -> %X9] GPR64common
[%vreg139 -> %W8] GPR32
[%vreg140 -> %X8] GPR64common
[%vreg143 -> %W8] GPR32
[%vreg144 -> %W9] GPR32
[%vreg145 -> %W8] GPR32
[%vreg148 -> %W10] GPR32common
[%vreg149 -> %W0] GPR32
[%vreg152 -> %X0] GPR64
[%vreg153 -> %W8] GPR32
[%vreg154 -> %W8] GPR32
[%vreg155 -> %W8] GPR32
[%vreg156 -> %W8] GPR32
[%vreg158 -> %W0] GPR32
[%vreg159 -> %X8] GPR64common
[%vreg161 -> %X0] GPR64sp


Stackmap 0:
  STACKMAP 0, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#3>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, %vreg1, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack3](align=1) LD8[FixedStack0](align=4) LD8[FixedStack4] LD8[FixedStack1] GPR32:%vreg3 GPR64:%vreg1

i32 %action: in register %W20 (vreg 3)
i32* %action.addr: in stack slot 2 (size: 4)
i8* %progress: in stack slot 3 (size: 1)
i32* %retval: in stack slot 0 (size: 4)
%struct.EState** %s: in stack slot 4 (size: 8)
%struct.bz_stream* %strm: in register %X21 (vreg 1)
%struct.bz_stream** %strm.addr: in stack slot 1 (size: 8)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, 0, <fi#3>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack3](align=1) LD8[FixedStack0](align=4)

i8* %progress: in stack slot 3 (size: 1)
i32* %retval: in stack slot 0 (size: 4)

Duplicate operand locations:


Stackmap 2:
  STACKMAP 2, 0, 0, <fi#3>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack3](align=1) LD8[FixedStack0](align=4) LD8[FixedStack4]

i8* %progress: in stack slot 3 (size: 1)
i32* %retval: in stack slot 0 (size: 4)
%struct.EState** %s: in stack slot 4 (size: 8)

Duplicate operand locations:


Stackmap 3:
  STACKMAP 3, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack4]

i32* %retval: in stack slot 0 (size: 4)
%struct.EState** %s: in stack slot 4 (size: 8)

Duplicate operand locations:


Stackmap 4:
  STACKMAP 4, 0, 0, <fi#3>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack3](align=1) LD8[FixedStack0](align=4) LD8[FixedStack4]

i8* %progress: in stack slot 3 (size: 1)
i32* %retval: in stack slot 0 (size: 4)
%struct.EState** %s: in stack slot 4 (size: 8)

Duplicate operand locations:


Stackmap 5:
  STACKMAP 5, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack4]

i32* %retval: in stack slot 0 (size: 4)
%struct.EState** %s: in stack slot 4 (size: 8)

Duplicate operand locations:


Stackmap 6:
  STACKMAP 6, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)

i32* %retval: in stack slot 0 (size: 4)

Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#3>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, %vreg1, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack3](align=1) LD8[FixedStack0](align=4) LD8[FixedStack4] LD8[FixedStack1] GPR32:%vreg3 GPR64:%vreg1
  -> Call instruction SlotIndex 208B, searching vregs 0 -> 163 and stack slots 0 -> 5
    + vreg9 is live in register but not in stackmap
      Defining instruction: %vreg9<def> = COPY %LR; GPR64:%vreg9
      Value: generated value, 1 instruction(s)

  STACKMAP 1, 0, 0, <fi#3>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack3](align=1) LD8[FixedStack0](align=4)
  -> Call instruction SlotIndex 1136B, searching vregs 0 -> 163 and stack slots 0 -> 5
    + vreg9 is live in register but not in stackmap
      Defining instruction: %vreg9<def> = COPY %LR; GPR64:%vreg9
      Value: generated value, 1 instruction(s)

  STACKMAP 2, 0, 0, <fi#3>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack3](align=1) LD8[FixedStack0](align=4) LD8[FixedStack4]
  -> Call instruction SlotIndex 2240B, searching vregs 0 -> 163 and stack slots 0 -> 5
    + vreg9 is live in register but not in stackmap
      Defining instruction: %vreg9<def> = COPY %LR; GPR64:%vreg9
      Value: generated value, 1 instruction(s)

  STACKMAP 3, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack4]
  -> Call instruction SlotIndex 2496B, searching vregs 0 -> 163 and stack slots 0 -> 5
    + vreg9 is live in register but not in stackmap
      Defining instruction: %vreg9<def> = COPY %LR; GPR64:%vreg9
      Value: generated value, 1 instruction(s)

  STACKMAP 4, 0, 0, <fi#3>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack3](align=1) LD8[FixedStack0](align=4) LD8[FixedStack4]
  -> Call instruction SlotIndex 3312B, searching vregs 0 -> 163 and stack slots 0 -> 5
    + vreg9 is live in register but not in stackmap
      Defining instruction: %vreg9<def> = COPY %LR; GPR64:%vreg9
      Value: generated value, 1 instruction(s)

  STACKMAP 5, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack4]
  -> Call instruction SlotIndex 3696B, searching vregs 0 -> 163 and stack slots 0 -> 5
    + vreg9 is live in register but not in stackmap
      Defining instruction: %vreg9<def> = COPY %LR; GPR64:%vreg9
      Value: generated value, 1 instruction(s)

  STACKMAP 6, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
  -> Call instruction SlotIndex 4288B, searching vregs 0 -> 163 and stack slots 0 -> 5

********** REWRITE VIRTUAL REGISTERS **********
********** Function: BZ2_bzCompress
********** REGISTER MAP **********
[%vreg1 -> %X21] GPR64
[%vreg3 -> %W20] GPR32
[%vreg5 -> %X8] GPR64
[%vreg6 -> %X8] GPR64common
[%vreg8 -> %X0] GPR64sp
[%vreg9 -> %X19] GPR64
[%vreg12 -> %X8] GPR64
[%vreg15 -> %X8] GPR64
[%vreg18 -> %X8] GPR64common
[%vreg21 -> %X9] GPR64
[%vreg23 -> %X8] GPR64
[%vreg24 -> %X8] GPR64common
[%vreg25 -> %X8] GPR64common
[%vreg26 -> %X8] GPR64common
[%vreg27 -> %W8] GPR32common
[%vreg29 -> %W9] GPR32
[%vreg30 -> %X9] GPR64common
[%vreg31 -> %X8] GPR64
[%vreg33 -> %W8] GPR32common
[%vreg37 -> %W8] GPR32
[%vreg39 -> %X8] GPR64common
[%vreg40 -> %X8] GPR64common
[%vreg42 -> %W9] GPR32
[%vreg43 -> %X9] GPR64common
[%vreg45 -> %W8] GPR32
[%vreg46 -> %W8] GPR32
[%vreg47 -> %W0] GPR32
[%vreg50 -> %X0] GPR64
[%vreg51 -> %W8] GPR32
[%vreg54 -> %W8] GPR32common
[%vreg55 -> %X8] GPR64common
[%vreg56 -> %W0] GPR32
[%vreg57 -> %W8] GPR32
[%vreg60 -> %X0] GPR64
[%vreg64 -> %W9] GPR32
[%vreg65 -> %X9] GPR64common
[%vreg67 -> %W8] GPR32
[%vreg68 -> %X8] GPR64common
[%vreg69 -> %W9] GPR32
[%vreg70 -> %W10] GPR32
[%vreg72 -> %X8] GPR64common
[%vreg73 -> %W8] GPR32
[%vreg74 -> %W8] GPR32
[%vreg75 -> %W8] GPR32
[%vreg77 -> %W8] GPR32common
[%vreg81 -> %W8] GPR32
[%vreg83 -> %X8] GPR64common
[%vreg84 -> %X8] GPR64common
[%vreg86 -> %W9] GPR32
[%vreg87 -> %X9] GPR64common
[%vreg90 -> %W8] GPR32common
[%vreg91 -> %X8] GPR64common
[%vreg92 -> %W0] GPR32
[%vreg95 -> %X0] GPR64
[%vreg96 -> %W0] GPR32
[%vreg97 -> %W8] GPR32
[%vreg100 -> %X0] GPR64
[%vreg104 -> %W9] GPR32
[%vreg105 -> %X9] GPR64common
[%vreg107 -> %W8] GPR32
[%vreg108 -> %X8] GPR64common
[%vreg109 -> %W9] GPR32
[%vreg110 -> %W10] GPR32
[%vreg112 -> %X8] GPR64common
[%vreg113 -> %W8] GPR32
[%vreg114 -> %W8] GPR32
[%vreg115 -> %W8] GPR32
[%vreg117 -> %W8] GPR32
[%vreg119 -> %W8] GPR32common
[%vreg121 -> %W8] GPR32common
[%vreg122 -> %W8] GPR32
[%vreg123 -> %W9] GPR32
[%vreg125 -> %X8] GPR64common
[%vreg128 -> %X9] GPR64common
[%vreg130 -> %W8] GPR32
[%vreg131 -> %X8] GPR64common
[%vreg132 -> %W9] GPR32
[%vreg134 -> %X8] GPR64common
[%vreg137 -> %X9] GPR64common
[%vreg139 -> %W8] GPR32
[%vreg140 -> %X8] GPR64common
[%vreg143 -> %W8] GPR32
[%vreg144 -> %W9] GPR32
[%vreg145 -> %W8] GPR32
[%vreg148 -> %W10] GPR32common
[%vreg149 -> %W0] GPR32
[%vreg152 -> %X0] GPR64
[%vreg153 -> %W8] GPR32
[%vreg154 -> %W8] GPR32
[%vreg155 -> %W8] GPR32
[%vreg156 -> %W8] GPR32
[%vreg158 -> %W0] GPR32
[%vreg159 -> %X8] GPR64common
[%vreg161 -> %X0] GPR64sp

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %LR %W1 %X0
16B		%vreg9<def> = COPY %LR; GPR64:%vreg9
32B		%vreg3<def> = COPY %W1; GPR32:%vreg3
48B		%vreg1<def> = COPY %X0; GPR64:%vreg1
96B		%vreg6<def> = ADRP <ga:@BZ2_bzCompress>[TF=1]; GPR64common:%vreg6
112B		%vreg8<def> = ADDXri %vreg6<kill>, <ga:@BZ2_bzCompress>[TF=34], 0; GPR64sp:%vreg8 GPR64common:%vreg6
160B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
176B		%X0<def> = COPY %vreg8<kill>; GPR64sp:%vreg8
192B		%X1<def> = COPY %vreg9; GPR64:%vreg9
208B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
224B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
240B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
256B		STACKMAP 0, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#3>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, %vreg1, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack3](align=1) LD8[FixedStack0](align=4) LD8[FixedStack4] LD8[FixedStack1] GPR32:%vreg3 GPR64:%vreg1
272B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
288B		STRXui %vreg1<kill>, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg1
304B		STRWui %vreg3<kill>, <fi#2>, 0; mem:ST4[FixedStack2] GPR32:%vreg3
320B		%vreg5<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg5
336B		CBNZX %vreg5<kill>, <BB#2>; GPR64:%vreg5
	    Successors according to CFG: BB#2 BB#1
> %X19<def> = COPY %LR
> %W20<def> = COPY %W1
> %X21<def> = COPY %X0
> %X8<def> = ADRP <ga:@BZ2_bzCompress>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@BZ2_bzCompress>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19
> BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 0, 0, %W20, 0, <fi#2>, 0, 0, <fi#3>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, %X21, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack3](align=1) LD8[FixedStack0](align=4) LD8[FixedStack4] LD8[FixedStack1]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRXui %X21<kill>, <fi#1>, 0; mem:ST8[FixedStack1]
> STRWui %W20<kill>, <fi#2>, 0; mem:ST4[FixedStack2]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> CBNZX %X8<kill>, <BB#2>
352B	BB#1: derived from LLVM BB %if.then
	    Live Ins: %X19
	    Predecessors according to CFG: BB#0
368B		%vreg156<def> = MOVi32imm 4294967294; GPR32:%vreg156
384B		STRWui %vreg156<kill>, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg156
400B		B <BB#38>
	    Successors according to CFG: BB#38
> %W8<def> = MOVi32imm 4294967294
> STRWui %W8<kill>, <fi#0>, 0; mem:ST4[FixedStack0]
> B <BB#38>
416B	BB#2: derived from LLVM BB %if.end
	    Live Ins: %X19
	    Predecessors according to CFG: BB#0
432B		%vreg18<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg18
448B		%vreg15<def> = LDRXui %vreg18<kill>, 6; mem:LD8[%state] GPR64:%vreg15 GPR64common:%vreg18
480B		STRXui %vreg15<kill>, <fi#4>, 0; mem:ST8[FixedStack4] GPR64:%vreg15
496B		%vreg12<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64:%vreg12
512B		CBNZX %vreg12<kill>, <BB#4>; GPR64:%vreg12
	    Successors according to CFG: BB#4 BB#3
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X8<def> = LDRXui %X8<kill>, 6; mem:LD8[%state]
> STRXui %X8<kill>, <fi#4>, 0; mem:ST8[FixedStack4]
> %X8<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4]
> CBNZX %X8<kill>, <BB#4>
528B	BB#3: derived from LLVM BB %if.then.2
	    Live Ins: %X19
	    Predecessors according to CFG: BB#2
544B		%vreg155<def> = MOVi32imm 4294967294; GPR32:%vreg155
560B		STRWui %vreg155<kill>, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg155
576B		B <BB#38>
	    Successors according to CFG: BB#38
> %W8<def> = MOVi32imm 4294967294
> STRWui %W8<kill>, <fi#0>, 0; mem:ST4[FixedStack0]
> B <BB#38>
592B	BB#4: derived from LLVM BB %if.end.3
	    Live Ins: %X19
	    Predecessors according to CFG: BB#2
608B		%vreg24<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg24
624B		%vreg23<def> = LDRXui %vreg24<kill>, 0; mem:LD8[%strm4] GPR64:%vreg23 GPR64common:%vreg24
640B		%vreg21<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg21
656B		%XZR<def> = SUBSXrr %vreg23<kill>, %vreg21<kill>, %NZCV<imp-def>; GPR64:%vreg23,%vreg21
672B		Bcc 0, <BB#6>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#6 BB#5
> %X8<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4]
> %X8<def> = LDRXui %X8<kill>, 0; mem:LD8[%strm4]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %XZR<def> = SUBSXrr %X8<kill>, %X9<kill>, %NZCV<imp-def>
> Bcc 0, <BB#6>, %NZCV<imp-use,kill>
688B	BB#5: derived from LLVM BB %if.then.6
	    Live Ins: %X19
	    Predecessors according to CFG: BB#4
704B		%vreg154<def> = MOVi32imm 4294967294; GPR32:%vreg154
720B		STRWui %vreg154<kill>, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg154
736B		B <BB#38>
	    Successors according to CFG: BB#38
> %W8<def> = MOVi32imm 4294967294
> STRWui %W8<kill>, <fi#0>, 0; mem:ST4[FixedStack0]
> B <BB#38>
752B	BB#6: derived from LLVM BB %if.end.7
	    Live Ins: %X19
	    Predecessors according to CFG: BB#4
768B		B <BB#7>
	    Successors according to CFG: BB#7
> B <BB#7>
784B	BB#7: derived from LLVM BB %preswitch
	    Live Ins: %X19
	    Predecessors according to CFG: BB#6 BB#15 BB#13
800B		%vreg26<def> = LDRXui <fi#4>, 0; mem:LD8[%s] GPR64common:%vreg26
816B		%vreg27<def> = LDRWui %vreg26<kill>, 2; mem:LD4[%mode] GPR32common:%vreg27 GPR64common:%vreg26
832B		%vreg25:sub_32<def,read-undef> = SUBSWri %vreg27<kill>, 1, 0, %NZCV<imp-def,dead>; GPR64common:%vreg25 GPR32common:%vreg27
864B		%vreg29<def,dead> = SUBSWri %vreg25:sub_32, 3, 0, %NZCV<imp-def>; GPR32:%vreg29 GPR64common:%vreg25
880B		Bcc 8, <BB#37>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#37 BB#8
> %X8<def> = LDRXui <fi#4>, 0; mem:LD8[%s]
> %W8<def> = LDRWui %X8<kill>, 2; mem:LD4[%mode]
> %W8<def> = SUBSWri %W8<kill>, 1, 0, %NZCV<imp-def,dead>, %X8<imp-def>
> %W9<def,dead> = SUBSWri %W8, 3, 0, %NZCV<imp-def>
> Bcc 8, <BB#37>, %NZCV<imp-use,kill>
896B	BB#8: derived from LLVM BB %preswitch
	    Live Ins: %X8 %X19
	    Predecessors according to CFG: BB#7
912B		%vreg30<def> = MOVaddrJT <jt#0>[TF=1], <jt#0>[TF=34]; GPR64common:%vreg30
928B		%vreg31<def> = LDRXroX %vreg30<kill>, %vreg25<kill>, 0, 1; mem:LD8[JumpTable] GPR64:%vreg31 GPR64common:%vreg30,%vreg25
944B		BR %vreg31<kill>; GPR64:%vreg31
	    Successors according to CFG: BB#9 BB#10 BB#17 BB#26
> %X9<def> = MOVaddrJT <jt#0>[TF=1], <jt#0>[TF=34]
> %X8<def> = LDRXroX %X9<kill>, %X8<kill>, 0, 1; mem:LD8[JumpTable]
> BR %X8<kill>
960B	BB#9: derived from LLVM BB %sw.bb
	    Live Ins: %X19
	    Predecessors according to CFG: BB#8
976B		%vreg153<def> = MOVi32imm 4294967295; GPR32:%vreg153
992B		STRWui %vreg153<kill>, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg153
1008B		B <BB#38>
	    Successors according to CFG: BB#38
> %W8<def> = MOVi32imm 4294967295
> STRWui %W8<kill>, <fi#0>, 0; mem:ST4[FixedStack0]
> B <BB#38>
1024B	BB#10: derived from LLVM BB %sw.bb.8
	    Live Ins: %X19
	    Predecessors according to CFG: BB#8
1040B		%vreg117<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg117
1056B		CBNZW %vreg117<kill>, <BB#12>; GPR32:%vreg117
	    Successors according to CFG: BB#12 BB#11
> %W8<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2]
> CBNZW %W8<kill>, <BB#12>
1072B	BB#11: derived from LLVM BB %if.then.10
	    Live Ins: %X19
	    Predecessors according to CFG: BB#10
1088B		%vreg152<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg152
1104B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1120B		%X0<def> = COPY %vreg152<kill>; GPR64:%vreg152
1136B		BL <ga:@handle_compress>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>
1152B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1168B		%vreg149<def> = COPY %W0; GPR32:%vreg149
1200B		%vreg143<def> = MOVi32imm 1; GPR32:%vreg143
1216B		%vreg144<def> = MOVi32imm 4294967294; GPR32:%vreg144
1232B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1248B		STACKMAP 1, 0, 0, <fi#3>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack3](align=1) LD8[FixedStack0](align=4)
1264B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1280B		STRBBui %vreg149<kill>, <fi#3>, 0; mem:ST1[FixedStack3] GPR32:%vreg149
1296B		%vreg148<def> = LDRBBui <fi#3>, 0; mem:LD1[FixedStack3] GPR32common:%vreg148
1312B		%WZR<def> = SUBSWri %vreg148<kill>, 0, 0, %NZCV<imp-def>; GPR32common:%vreg148
1328B		%vreg145<def> = CSELWr %vreg143<kill>, %vreg144<kill>, 1, %NZCV<imp-use,kill>; GPR32:%vreg145,%vreg143,%vreg144
1344B		STRWui %vreg145<kill>, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg145
1360B		B <BB#38>
	    Successors according to CFG: BB#38
> %X0<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BL <ga:@handle_compress>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = COPY %W0
Deleting identity copy.
> %W8<def> = MOVi32imm 1
> %W9<def> = MOVi32imm 4294967294
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 1, 0, 0, <fi#3>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack3](align=1) LD8[FixedStack0](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRBBui %W0<kill>, <fi#3>, 0; mem:ST1[FixedStack3]
> %W10<def> = LDRBBui <fi#3>, 0; mem:LD1[FixedStack3]
> %WZR<def> = SUBSWri %W10<kill>, 0, 0, %NZCV<imp-def>
> %W8<def> = CSELWr %W8<kill>, %W9<kill>, 1, %NZCV<imp-use,kill>
> STRWui %W8<kill>, <fi#0>, 0; mem:ST4[FixedStack0]
> B <BB#38>
1376B	BB#12: derived from LLVM BB %if.else
	    Live Ins: %X19
	    Predecessors according to CFG: BB#10
1392B		%vreg119<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32common:%vreg119
1408B		%WZR<def> = SUBSWri %vreg119<kill>, 1, 0, %NZCV<imp-def>; GPR32common:%vreg119
1424B		Bcc 1, <BB#14>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#14 BB#13
> %W8<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2]
> %WZR<def> = SUBSWri %W8<kill>, 1, 0, %NZCV<imp-def>
> Bcc 1, <BB#14>, %NZCV<imp-use,kill>
1440B	BB#13: derived from LLVM BB %if.then.13
	    Live Ins: %X19
	    Predecessors according to CFG: BB#12
1472B		%vreg140<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg140
1488B		%vreg139<def> = LDRWui %vreg140<kill>, 2; mem:LD4[%avail_in] GPR32:%vreg139 GPR64common:%vreg140
1504B		%vreg137<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg137
1520B		STRWui %vreg139<kill>, %vreg137<kill>, 4; mem:ST4[%avail_in_expect] GPR32:%vreg139 GPR64common:%vreg137
1536B		%vreg134<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg134
1544B		%vreg132<def> = MOVi32imm 3; GPR32:%vreg132
1552B		STRWui %vreg132<kill>, %vreg134<kill>, 2; mem:ST4[%mode14] GPR32:%vreg132 GPR64common:%vreg134
1568B		B <BB#7>
	    Successors according to CFG: BB#7
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W8<def> = LDRWui %X8<kill>, 2; mem:LD4[%avail_in]
> %X9<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4]
> STRWui %W8<kill>, %X9<kill>, 4; mem:ST4[%avail_in_expect]
> %X8<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4]
> %W9<def> = MOVi32imm 3
> STRWui %W9<kill>, %X8<kill>, 2; mem:ST4[%mode14]
> B <BB#7>
1584B	BB#14: derived from LLVM BB %if.else.15
	    Live Ins: %X19
	    Predecessors according to CFG: BB#12
1600B		%vreg121<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32common:%vreg121
1616B		%WZR<def> = SUBSWri %vreg121<kill>, 2, 0, %NZCV<imp-def>; GPR32common:%vreg121
1632B		Bcc 1, <BB#16>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#16 BB#15
> %W8<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2]
> %WZR<def> = SUBSWri %W8<kill>, 2, 0, %NZCV<imp-def>
> Bcc 1, <BB#16>, %NZCV<imp-use,kill>
1648B	BB#15: derived from LLVM BB %if.then.18
	    Live Ins: %X19
	    Predecessors according to CFG: BB#14
1680B		%vreg131<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg131
1696B		%vreg130<def> = LDRWui %vreg131<kill>, 2; mem:LD4[%avail_in19] GPR32:%vreg130 GPR64common:%vreg131
1712B		%vreg128<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg128
1728B		STRWui %vreg130<kill>, %vreg128<kill>, 4; mem:ST4[%avail_in_expect20] GPR32:%vreg130 GPR64common:%vreg128
1744B		%vreg125<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg125
1752B		%vreg123<def> = MOVi32imm 4; GPR32:%vreg123
1760B		STRWui %vreg123<kill>, %vreg125<kill>, 2; mem:ST4[%mode21] GPR32:%vreg123 GPR64common:%vreg125
1776B		B <BB#7>
	    Successors according to CFG: BB#7
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W8<def> = LDRWui %X8<kill>, 2; mem:LD4[%avail_in19]
> %X9<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4]
> STRWui %W8<kill>, %X9<kill>, 4; mem:ST4[%avail_in_expect20]
> %X8<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4]
> %W9<def> = MOVi32imm 4
> STRWui %W9<kill>, %X8<kill>, 2; mem:ST4[%mode21]
> B <BB#7>
1792B	BB#16: derived from LLVM BB %if.else.22
	    Live Ins: %X19
	    Predecessors according to CFG: BB#14
1808B		%vreg122<def> = MOVi32imm 4294967294; GPR32:%vreg122
1824B		STRWui %vreg122<kill>, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg122
1840B		B <BB#38>
	    Successors according to CFG: BB#38
> %W8<def> = MOVi32imm 4294967294
> STRWui %W8<kill>, <fi#0>, 0; mem:ST4[FixedStack0]
> B <BB#38>
1856B	BB#17: derived from LLVM BB %sw.bb.23
	    Live Ins: %X19
	    Predecessors according to CFG: BB#8
1872B		%vreg77<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32common:%vreg77
1888B		%WZR<def> = SUBSWri %vreg77<kill>, 1, 0, %NZCV<imp-def>; GPR32common:%vreg77
1904B		Bcc 0, <BB#19>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#19 BB#18
> %W8<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2]
> %WZR<def> = SUBSWri %W8<kill>, 1, 0, %NZCV<imp-def>
> Bcc 0, <BB#19>, %NZCV<imp-use,kill>
1920B	BB#18: derived from LLVM BB %if.then.26
	    Live Ins: %X19
	    Predecessors according to CFG: BB#17
1936B		%vreg115<def> = MOVi32imm 4294967295; GPR32:%vreg115
1952B		STRWui %vreg115<kill>, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg115
1968B		B <BB#38>
	    Successors according to CFG: BB#38
> %W8<def> = MOVi32imm 4294967295
> STRWui %W8<kill>, <fi#0>, 0; mem:ST4[FixedStack0]
> B <BB#38>
1984B	BB#19: derived from LLVM BB %if.end.27
	    Live Ins: %X19
	    Predecessors according to CFG: BB#17
2032B		%vreg84<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg84
2040B		%vreg87<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg87
2048B		%vreg83<def> = LDRXui %vreg84<kill>, 0; mem:LD8[%strm29] GPR64common:%vreg83,%vreg84
2056B		%vreg86<def> = LDRWui %vreg87<kill>, 4; mem:LD4[%avail_in_expect28] GPR32:%vreg86 GPR64common:%vreg87
2064B		%vreg81<def> = LDRWui %vreg83<kill>, 2; mem:LD4[%avail_in30] GPR32:%vreg81 GPR64common:%vreg83
2080B		%WZR<def> = SUBSWrr %vreg86<kill>, %vreg81<kill>, %NZCV<imp-def>; GPR32:%vreg86,%vreg81
2096B		Bcc 0, <BB#21>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#21 BB#20
> %X8<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4]
> %X9<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4]
> %X8<def> = LDRXui %X8<kill>, 0; mem:LD8[%strm29]
> %W9<def> = LDRWui %X9<kill>, 4; mem:LD4[%avail_in_expect28]
> %W8<def> = LDRWui %X8<kill>, 2; mem:LD4[%avail_in30]
> %WZR<def> = SUBSWrr %W9<kill>, %W8<kill>, %NZCV<imp-def>
> Bcc 0, <BB#21>, %NZCV<imp-use,kill>
2112B	BB#20: derived from LLVM BB %if.then.33
	    Live Ins: %X19
	    Predecessors according to CFG: BB#19
2128B		%vreg114<def> = MOVi32imm 4294967295; GPR32:%vreg114
2144B		STRWui %vreg114<kill>, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg114
2160B		B <BB#38>
	    Successors according to CFG: BB#38
> %W8<def> = MOVi32imm 4294967295
> STRWui %W8<kill>, <fi#0>, 0; mem:ST4[FixedStack0]
> B <BB#38>
2176B	BB#21: derived from LLVM BB %if.end.34
	    Live Ins: %X19
	    Predecessors according to CFG: BB#19
2192B		%vreg95<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg95
2208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2224B		%X0<def> = COPY %vreg95<kill>; GPR64:%vreg95
2240B		BL <ga:@handle_compress>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>
2256B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2272B		%vreg92<def> = COPY %W0; GPR32:%vreg92
2304B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2320B		STACKMAP 2, 0, 0, <fi#3>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack3](align=1) LD8[FixedStack0](align=4) LD8[FixedStack4]
2336B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2352B		STRBBui %vreg92<kill>, <fi#3>, 0; mem:ST1[FixedStack3] GPR32:%vreg92
2368B		%vreg91<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg91
2384B		%vreg90<def> = LDRWui %vreg91<kill>, 4; mem:LD4[%avail_in_expect36] GPR32common:%vreg90 GPR64common:%vreg91
2400B		%WZR<def> = SUBSWri %vreg90<kill>, 0, 0, %NZCV<imp-def>; GPR32common:%vreg90
2416B		Bcc 8, <BB#24>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#24 BB#22
> %X0<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BL <ga:@handle_compress>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = COPY %W0
Deleting identity copy.
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 2, 0, 0, <fi#3>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack3](align=1) LD8[FixedStack0](align=4) LD8[FixedStack4]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRBBui %W0<kill>, <fi#3>, 0; mem:ST1[FixedStack3]
> %X8<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4]
> %W8<def> = LDRWui %X8<kill>, 4; mem:LD4[%avail_in_expect36]
> %WZR<def> = SUBSWri %W8<kill>, 0, 0, %NZCV<imp-def>
> Bcc 8, <BB#24>, %NZCV<imp-use,kill>
2432B	BB#22: derived from LLVM BB %lor.lhs.false
	    Live Ins: %X19
	    Predecessors according to CFG: BB#21
2448B		%vreg100<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64:%vreg100
2464B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2480B		%X0<def> = COPY %vreg100<kill>; GPR64:%vreg100
2496B		BL <ga:@isempty_RL>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>
2512B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2528B		%vreg96<def> = COPY %W0; GPR32:%vreg96
2560B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2576B		STACKMAP 3, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack4]
2592B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2608B		%vreg97<def> = UBFMWri %vreg96<kill>, 0, 7; GPR32:%vreg97,%vreg96
2624B		CBZW %vreg97<kill>, <BB#24>; GPR32:%vreg97
	    Successors according to CFG: BB#24 BB#23
> %X0<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BL <ga:@isempty_RL>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = COPY %W0
Deleting identity copy.
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 3, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack4]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W8<def> = UBFMWri %W0<kill>, 0, 7
> CBZW %W8<kill>, <BB#24>
2640B	BB#23: derived from LLVM BB %lor.lhs.false.41
	    Live Ins: %X19
	    Predecessors according to CFG: BB#22
2656B		%vreg108<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg108
2688B		%vreg105<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg105
2696B		%vreg107<def> = LDRWui %vreg108<kill>, 30; mem:LD4[%state_out_pos] GPR32:%vreg107 GPR64common:%vreg108
2704B		%vreg104<def> = LDRWui %vreg105<kill>, 29; mem:LD4[%numZ] GPR32:%vreg104 GPR64common:%vreg105
2720B		%WZR<def> = SUBSWrr %vreg107<kill>, %vreg104<kill>, %NZCV<imp-def>; GPR32:%vreg107,%vreg104
2736B		Bcc 10, <BB#25>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#25 BB#24
> %X8<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4]
> %X9<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4]
> %W8<def> = LDRWui %X8<kill>, 30; mem:LD4[%state_out_pos]
> %W9<def> = LDRWui %X9<kill>, 29; mem:LD4[%numZ]
> %WZR<def> = SUBSWrr %W8<kill>, %W9<kill>, %NZCV<imp-def>
> Bcc 10, <BB#25>, %NZCV<imp-use,kill>
2752B	BB#24: derived from LLVM BB %if.then.44
	    Live Ins: %X19
	    Predecessors according to CFG: BB#21 BB#22 BB#23
2768B		%vreg113<def> = MOVi32imm 2; GPR32:%vreg113
2784B		STRWui %vreg113<kill>, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg113
2800B		B <BB#38>
	    Successors according to CFG: BB#38
> %W8<def> = MOVi32imm 2
> STRWui %W8<kill>, <fi#0>, 0; mem:ST4[FixedStack0]
> B <BB#38>
2816B	BB#25: derived from LLVM BB %if.end.45
	    Live Ins: %X19
	    Predecessors according to CFG: BB#23
2864B		%vreg112<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg112
2868B		%vreg109<def> = MOVi32imm 1; GPR32:%vreg109
2872B		%vreg110<def> = MOVi32imm 2; GPR32:%vreg110
2880B		STRWui %vreg110<kill>, %vreg112<kill>, 2; mem:ST4[%mode46] GPR32:%vreg110 GPR64common:%vreg112
2896B		STRWui %vreg109<kill>, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg109
2912B		B <BB#38>
	    Successors according to CFG: BB#38
> %X8<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4]
> %W9<def> = MOVi32imm 1
> %W10<def> = MOVi32imm 2
> STRWui %W10<kill>, %X8<kill>, 2; mem:ST4[%mode46]
> STRWui %W9<kill>, <fi#0>, 0; mem:ST4[FixedStack0]
> B <BB#38>
2928B	BB#26: derived from LLVM BB %sw.bb.47
	    Live Ins: %X19
	    Predecessors according to CFG: BB#8
2944B		%vreg33<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32common:%vreg33
2960B		%WZR<def> = SUBSWri %vreg33<kill>, 2, 0, %NZCV<imp-def>; GPR32common:%vreg33
2976B		Bcc 0, <BB#28>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#28 BB#27
> %W8<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2]
> %WZR<def> = SUBSWri %W8<kill>, 2, 0, %NZCV<imp-def>
> Bcc 0, <BB#28>, %NZCV<imp-use,kill>
2992B	BB#27: derived from LLVM BB %if.then.50
	    Live Ins: %X19
	    Predecessors according to CFG: BB#26
3008B		%vreg75<def> = MOVi32imm 4294967295; GPR32:%vreg75
3024B		STRWui %vreg75<kill>, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg75
3040B		B <BB#38>
	    Successors according to CFG: BB#38
> %W8<def> = MOVi32imm 4294967295
> STRWui %W8<kill>, <fi#0>, 0; mem:ST4[FixedStack0]
> B <BB#38>
3056B	BB#28: derived from LLVM BB %if.end.51
	    Live Ins: %X19
	    Predecessors according to CFG: BB#26
3104B		%vreg40<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg40
3112B		%vreg43<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg43
3120B		%vreg39<def> = LDRXui %vreg40<kill>, 0; mem:LD8[%strm53] GPR64common:%vreg39,%vreg40
3128B		%vreg42<def> = LDRWui %vreg43<kill>, 4; mem:LD4[%avail_in_expect52] GPR32:%vreg42 GPR64common:%vreg43
3136B		%vreg37<def> = LDRWui %vreg39<kill>, 2; mem:LD4[%avail_in54] GPR32:%vreg37 GPR64common:%vreg39
3152B		%WZR<def> = SUBSWrr %vreg42<kill>, %vreg37<kill>, %NZCV<imp-def>; GPR32:%vreg42,%vreg37
3168B		Bcc 0, <BB#30>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#30 BB#29
> %X8<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4]
> %X9<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4]
> %X8<def> = LDRXui %X8<kill>, 0; mem:LD8[%strm53]
> %W9<def> = LDRWui %X9<kill>, 4; mem:LD4[%avail_in_expect52]
> %W8<def> = LDRWui %X8<kill>, 2; mem:LD4[%avail_in54]
> %WZR<def> = SUBSWrr %W9<kill>, %W8<kill>, %NZCV<imp-def>
> Bcc 0, <BB#30>, %NZCV<imp-use,kill>
3184B	BB#29: derived from LLVM BB %if.then.57
	    Live Ins: %X19
	    Predecessors according to CFG: BB#28
3200B		%vreg74<def> = MOVi32imm 4294967295; GPR32:%vreg74
3216B		STRWui %vreg74<kill>, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg74
3232B		B <BB#38>
	    Successors according to CFG: BB#38
> %W8<def> = MOVi32imm 4294967295
> STRWui %W8<kill>, <fi#0>, 0; mem:ST4[FixedStack0]
> B <BB#38>
3248B	BB#30: derived from LLVM BB %if.end.58
	    Live Ins: %X19
	    Predecessors according to CFG: BB#28
3264B		%vreg50<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg50
3280B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3296B		%X0<def> = COPY %vreg50<kill>; GPR64:%vreg50
3312B		BL <ga:@handle_compress>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>
3328B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3344B		%vreg47<def> = COPY %W0; GPR32:%vreg47
3376B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3392B		STACKMAP 4, 0, 0, <fi#3>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack3](align=1) LD8[FixedStack0](align=4) LD8[FixedStack4]
3408B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3424B		STRBBui %vreg47<kill>, <fi#3>, 0; mem:ST1[FixedStack3] GPR32:%vreg47
3440B		%vreg46<def> = LDRBBui <fi#3>, 0; mem:LD1[FixedStack3] GPR32:%vreg46
3456B		%vreg45<def> = UBFMWri %vreg46<kill>, 0, 7; GPR32:%vreg45,%vreg46
3472B		CBNZW %vreg45<kill>, <BB#32>; GPR32:%vreg45
	    Successors according to CFG: BB#32 BB#31
> %X0<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BL <ga:@handle_compress>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = COPY %W0
Deleting identity copy.
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 4, 0, 0, <fi#3>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack3](align=1) LD8[FixedStack0](align=4) LD8[FixedStack4]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRBBui %W0<kill>, <fi#3>, 0; mem:ST1[FixedStack3]
> %W8<def> = LDRBBui <fi#3>, 0; mem:LD1[FixedStack3]
> %W8<def> = UBFMWri %W8<kill>, 0, 7
> CBNZW %W8<kill>, <BB#32>
3488B	BB#31: derived from LLVM BB %if.then.61
	    Live Ins: %X19
	    Predecessors according to CFG: BB#30
3504B		%vreg51<def> = MOVi32imm 4294967295; GPR32:%vreg51
3520B		STRWui %vreg51<kill>, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg51
3536B		B <BB#38>
	    Successors according to CFG: BB#38
> %W8<def> = MOVi32imm 4294967295
> STRWui %W8<kill>, <fi#0>, 0; mem:ST4[FixedStack0]
> B <BB#38>
3552B	BB#32: derived from LLVM BB %if.end.62
	    Live Ins: %X19
	    Predecessors according to CFG: BB#30
3568B		%vreg55<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg55
3584B		%vreg54<def> = LDRWui %vreg55<kill>, 4; mem:LD4[%avail_in_expect63] GPR32common:%vreg54 GPR64common:%vreg55
3600B		%WZR<def> = SUBSWri %vreg54<kill>, 0, 0, %NZCV<imp-def>; GPR32common:%vreg54
3616B		Bcc 8, <BB#35>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#35 BB#33
> %X8<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4]
> %W8<def> = LDRWui %X8<kill>, 4; mem:LD4[%avail_in_expect63]
> %WZR<def> = SUBSWri %W8<kill>, 0, 0, %NZCV<imp-def>
> Bcc 8, <BB#35>, %NZCV<imp-use,kill>
3632B	BB#33: derived from LLVM BB %lor.lhs.false.66
	    Live Ins: %X19
	    Predecessors according to CFG: BB#32
3648B		%vreg60<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64:%vreg60
3664B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3680B		%X0<def> = COPY %vreg60<kill>; GPR64:%vreg60
3696B		BL <ga:@isempty_RL>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>
3712B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3728B		%vreg56<def> = COPY %W0; GPR32:%vreg56
3760B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3776B		STACKMAP 5, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack4]
3792B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3808B		%vreg57<def> = UBFMWri %vreg56<kill>, 0, 7; GPR32:%vreg57,%vreg56
3824B		CBZW %vreg57<kill>, <BB#35>; GPR32:%vreg57
	    Successors according to CFG: BB#35 BB#34
> %X0<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BL <ga:@isempty_RL>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = COPY %W0
Deleting identity copy.
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 5, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack4]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W8<def> = UBFMWri %W0<kill>, 0, 7
> CBZW %W8<kill>, <BB#35>
3840B	BB#34: derived from LLVM BB %lor.lhs.false.69
	    Live Ins: %X19
	    Predecessors according to CFG: BB#33
3856B		%vreg68<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg68
3888B		%vreg65<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg65
3896B		%vreg67<def> = LDRWui %vreg68<kill>, 30; mem:LD4[%state_out_pos70] GPR32:%vreg67 GPR64common:%vreg68
3904B		%vreg64<def> = LDRWui %vreg65<kill>, 29; mem:LD4[%numZ71] GPR32:%vreg64 GPR64common:%vreg65
3920B		%WZR<def> = SUBSWrr %vreg67<kill>, %vreg64<kill>, %NZCV<imp-def>; GPR32:%vreg67,%vreg64
3936B		Bcc 10, <BB#36>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#36 BB#35
> %X8<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4]
> %X9<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4]
> %W8<def> = LDRWui %X8<kill>, 30; mem:LD4[%state_out_pos70]
> %W9<def> = LDRWui %X9<kill>, 29; mem:LD4[%numZ71]
> %WZR<def> = SUBSWrr %W8<kill>, %W9<kill>, %NZCV<imp-def>
> Bcc 10, <BB#36>, %NZCV<imp-use,kill>
3952B	BB#35: derived from LLVM BB %if.then.74
	    Live Ins: %X19
	    Predecessors according to CFG: BB#32 BB#33 BB#34
3968B		%vreg73<def> = MOVi32imm 3; GPR32:%vreg73
3984B		STRWui %vreg73<kill>, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg73
4000B		B <BB#38>
	    Successors according to CFG: BB#38
> %W8<def> = MOVi32imm 3
> STRWui %W8<kill>, <fi#0>, 0; mem:ST4[FixedStack0]
> B <BB#38>
4016B	BB#36: derived from LLVM BB %if.end.75
	    Live Ins: %X19
	    Predecessors according to CFG: BB#34
4064B		%vreg72<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg72
4068B		%vreg69<def> = MOVi32imm 4; GPR32:%vreg69
4072B		%vreg70<def> = MOVi32imm 1; GPR32:%vreg70
4080B		STRWui %vreg70<kill>, %vreg72<kill>, 2; mem:ST4[%mode76] GPR32:%vreg70 GPR64common:%vreg72
4096B		STRWui %vreg69<kill>, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg69
4112B		B <BB#38>
	    Successors according to CFG: BB#38
> %X8<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4]
> %W9<def> = MOVi32imm 4
> %W10<def> = MOVi32imm 1
> STRWui %W10<kill>, %X8<kill>, 2; mem:ST4[%mode76]
> STRWui %W9<kill>, <fi#0>, 0; mem:ST4[FixedStack0]
> B <BB#38>
4128B	BB#37: derived from LLVM BB %sw.epilog
	    Live Ins: %X19
	    Predecessors according to CFG: BB#7
4144B		STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
	    Successors according to CFG: BB#38
> STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
4160B	BB#38: derived from LLVM BB %return
	    Live Ins: %X19
	    Predecessors according to CFG: BB#31 BB#36 BB#35 BB#29 BB#27 BB#25 BB#24 BB#20 BB#18 BB#16 BB#11 BB#9 BB#37 BB#5 BB#3 BB#1
4176B		%vreg159<def> = ADRP <ga:@BZ2_bzCompress>[TF=1]; GPR64common:%vreg159
4192B		%vreg161<def> = ADDXri %vreg159<kill>, <ga:@BZ2_bzCompress>[TF=34], 0; GPR64sp:%vreg161 GPR64common:%vreg159
4240B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4256B		%X0<def> = COPY %vreg161<kill>; GPR64sp:%vreg161
4272B		%X1<def> = COPY %vreg9<kill>; GPR64:%vreg9
4288B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
4304B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4320B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4336B		STACKMAP 6, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
4352B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4368B		%vreg158<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0] GPR32:%vreg158
4384B		%W0<def> = COPY %vreg158<kill>; GPR32:%vreg158
4400B		RET_ReallyLR %W0<imp-use>
> %X8<def> = ADRP <ga:@BZ2_bzCompress>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@BZ2_bzCompress>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19<kill>
> BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 6, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0]
> %W0<def> = COPY %W0<kill>
Deleting identity copy.
> RET_ReallyLR %W0<imp-use>
Computing live-in reg-units in ABI blocks.
0B	BB#0 W0#0 W30#0
Created 2 new intervals.
********** INTERVALS **********
W30 [0B,16r:0)[176r,176d:20)[224e,224d:9)[512r,512d:19)[592e,592d:8)[1040r,1040d:18)[1120e,1120d:7)[1280r,1280d:17)[1344e,1344d:6)[1600r,1600d:16)[1680e,1680d:5)[1952r,1952d:15)[2032e,2032d:4)[2336r,2336d:12)[2384e,2384d:3)[2592r,2592d:13)[2656e,2656d:2)[2960r,2960d:14)[3024e,3024d:1)[3632r,3632d:11)[3680e,3680d:10)  0@0B-phi 1@3024e 2@2656e 3@2384e 4@2032e 5@1680e 6@1344e 7@1120e 8@592e 9@224e 10@3680e 11@3632r 12@2336r 13@2592r 14@2960r 15@1952r 16@1600r 17@1280r 18@1040r 19@512r 20@176r
W0 [0B,32r:0)[144r,176r:15)[496r,512r:14)[512r,544r:5)[1024r,1040r:13)[1040r,1072r:4)[1264r,1280r:12)[1584r,1600r:11)[1600r,1632r:3)[1936r,1952r:10)[1952r,1984r:2)[2320r,2336r:7)[2544r,2592r:8)[2912r,2960r:9)[3600r,3632r:6)[3712r,3728r:1)  0@0B-phi 1@3712r 2@1952r 3@1600r 4@1040r 5@512r 6@3600r 7@2320r 8@2544r 9@2912r 10@1936r 11@1584r 12@1264r 13@1024r 14@496r 15@144r
%vreg1 [3520r,3536r:0)  0@3520r
%vreg2 [32r,48r:0)  0@32r
%vreg3 [48r,256r:0)  0@48r
%vreg6 [336r,352r:0)  0@336r
%vreg8 [320r,336r:0)  0@320r
%vreg9 [304r,320r:0)  0@304r
%vreg10 [64r,80r:0)  0@64r
%vreg11 [80r,96r:0)  0@80r
%vreg12 [96r,144r:0)  0@96r
%vreg13 [112r,160r:0)  0@112r
%vreg14 [16r,3616r:0)  0@16r
%vreg17 [400r,416r:0)  0@400r
%vreg18 [384r,400r:0)  0@384r
%vreg22 [752r,768r:0)  0@752r
%vreg23 [736r,752r:0)  0@736r
%vreg25 [720r,768r:0)  0@720r
%vreg26 [704r,720r:0)  0@704r
%vreg29 [672r,688r:0)  0@672r
%vreg32 [656r,672r:0)  0@656r
%vreg35 [640r,656r:0)  0@640r
%vreg36 [560r,624r:0)  0@560r
%vreg37 [624r,656r:0)  0@624r
%vreg39 [544r,560r:0)  0@544r
%vreg40 [464r,496r:0)  0@464r
%vreg43 [864r,880r:0)  0@864r
%vreg44 [848r,864r:0)  0@848r
%vreg47 [944r,960r:0)  0@944r
%vreg48 [928r,944r:0)  0@928r
%vreg50 [1088r,1152r:0)  0@1088r
%vreg51 [1152r,1168r:0)  0@1152r
%vreg53 [1072r,1088r:0)  0@1072r
%vreg54 [992r,1024r:0)  0@992r
%vreg57 [1424r,1440r:0)  0@1424r
%vreg58 [1408r,1424r:0)  0@1408r
%vreg59 [1312r,1392r:0)  0@1312r
%vreg61 [1376r,1392r:0)  0@1376r
%vreg63 [1232r,1264r:0)  0@1232r
%vreg66 [1504r,1520r:0)  0@1504r
%vreg67 [1488r,1504r:0)  0@1488r
%vreg69 [1648r,1712r:0)  0@1648r
%vreg70 [1712r,1728r:0)  0@1712r
%vreg72 [1632r,1648r:0)  0@1632r
%vreg73 [1552r,1584r:0)  0@1552r
%vreg76 [1840r,1856r:0)  0@1840r
%vreg77 [1824r,1840r:0)  0@1824r
%vreg80 [2160r,2176r:0)  0@2160r
%vreg81 [2144r,2160r:0)  0@2144r
%vreg84 [2112r,2128r:0)  0@2112r
%vreg87 [2096r,2112r:0)  0@2096r
%vreg90 [2080r,2096r:0)  0@2080r
%vreg91 [2000r,2064r:0)  0@2000r
%vreg92 [2064r,2096r:0)  0@2064r
%vreg94 [1984r,2000r:0)  0@1984r
%vreg95 [1904r,1936r:0)  0@1904r
%vreg98 [2240r,2256r:0)  0@2240r
%vreg99 [2224r,2240r:0)  0@2224r
%vreg103 [2800r,2816r:0)  0@2800r
%vreg104 [2784r,2800r:0)  0@2784r
%vreg106 [2768r,2816r:0)  0@2768r
%vreg107 [2752r,2768r:0)  0@2752r
%vreg110 [3152r,3168r:0)  0@3152r
%vreg112 [3136r,3152r:0)  0@3136r
%vreg113 [3120r,3136r:0)  0@3120r
%vreg114 [2992r,3072r:0)  0@2992r
%vreg116 [3056r,3072r:0)  0@3056r
%vreg118 [2864r,2928r:0)  0@2864r
%vreg119 [2928r,2944r:0)  0@2928r
%vreg120 [2880r,2912r:0)  0@2880r
%vreg121 [2624r,2704r:0)  0@2624r
%vreg123 [2688r,2704r:0)  0@2688r
%vreg126 [2560r,2576r:0)  0@2560r
%vreg128 [2512r,2560r:0)  0@2512r
%vreg130 [2496r,2512r:0)  0@2496r
%vreg132 [2480r,2496r:0)  0@2480r
%vreg134 [2448r,2464r:0)  0@2448r
%vreg135 [2432r,2448r:0)  0@2432r
%vreg136 [2416r,2544r:0)  0@2416r
%vreg138 [2288r,2320r:0)  0@2288r
%vreg139 [3360r,3392r:0)  0@3360r
%vreg143 [3376r,3408r:0)  0@3376r
%vreg145 [3472r,3488r:0)  0@3472r
%vreg148 [3440r,3456r:0)  0@3440r
%vreg149 [3552r,3552d:0)  0@3552r
%vreg150 [3536r,3712r:0)  0@3536r
%vreg151 [3584r,3600r:0)  0@3584r
%vreg152 [3392r,3424B:0)[3488r,3504B:1)[3504B,3520r:2)  0@3392r 1@3488r 2@3504B-phi
RegMasks: 176r 512r 1040r 1280r 1600r 1952r 2336r 2592r 2960r 3632r
********** MACHINEINSTRS **********
# Machine code for function handle_compress: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
  fi#1: size=1, align=1, at location [SP]
  fi#2: size=1, align=1, at location [SP]
  fi#3: size=8, align=8, at location [SP]
Function Live Ins: %X0 in %vreg2, %LR in %vreg14

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %LR
16B		%vreg14<def> = COPY %LR; GPR64:%vreg14
32B		%vreg2<def> = COPY %X0; GPR64:%vreg2
48B		%vreg3<def> = COPY %vreg2; GPR64:%vreg3,%vreg2
64B		%vreg10<def> = ADRP <ga:@handle_compress>[TF=1]; GPR64common:%vreg10
80B		%vreg11<def> = ADDXri %vreg10, <ga:@handle_compress>[TF=34], 0; GPR64sp:%vreg11 GPR64common:%vreg10
96B		%vreg12<def> = COPY %vreg11; GPR64all:%vreg12 GPR64sp:%vreg11
112B		%vreg13<def> = COPY %vreg14; GPR64all:%vreg13 GPR64:%vreg14
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		%X0<def> = COPY %vreg12; GPR64all:%vreg12
160B		%X1<def> = COPY %vreg13; GPR64all:%vreg13
176B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
224B		STACKMAP 0, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, %vreg3, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3] LD8[FixedStack0] GPR64:%vreg3
240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
256B		STRXui %vreg3, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg3
272B		STRBBui %WZR, <fi#1>, 0; mem:ST1[FixedStack1]
288B		STRBBui %WZR, <fi#2>, 0; mem:ST1[FixedStack2]
304B		%vreg9<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg9
320B		%vreg8<def> = LDRXui %vreg9, 6; mem:LD8[%state] GPR64:%vreg8 GPR64common:%vreg9
336B		%vreg6<def> = COPY %vreg8; GPR64:%vreg6,%vreg8
352B		STRXui %vreg6, <fi#3>, 0; mem:ST8[FixedStack3] GPR64:%vreg6
	    Successors according to CFG: BB#1

368B	BB#1: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#0 BB#24
384B		%vreg18<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg18
400B		%vreg17<def> = LDRWui %vreg18, 3; mem:LD4[%state1] GPR32common:%vreg17 GPR64common:%vreg18
416B		%WZR<def> = SUBSWri %vreg17, 1, 0, %NZCV<imp-def>; GPR32common:%vreg17
432B		Bcc 1, <BB#13>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#13 BB#2

448B	BB#2: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#1
464B		%vreg40<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg40
480B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
496B		%X0<def> = COPY %vreg40; GPR64:%vreg40
512B		BL <ga:@copy_output_until_stop>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>
528B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
544B		%vreg39<def> = COPY %W0; GPR32:%vreg39
560B		%vreg36<def> = COPY %vreg39; GPR32:%vreg36,%vreg39
576B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
592B		STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
608B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
624B		%vreg37<def> = UBFMWri %vreg36, 0, 7; GPR32:%vreg37,%vreg36
640B		%vreg35<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg35
656B		%vreg32<def> = ORRWrr %vreg35, %vreg37; GPR32:%vreg32,%vreg35,%vreg37
672B		%vreg29<def> = COPY %vreg32; GPR32:%vreg29,%vreg32
688B		STRBBui %vreg29, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg29
704B		%vreg26<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg26
720B		%vreg25<def> = LDRWui %vreg26, 30; mem:LD4[%state_out_pos] GPR32:%vreg25 GPR64common:%vreg26
736B		%vreg23<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg23
752B		%vreg22<def> = LDRWui %vreg23, 29; mem:LD4[%numZ] GPR32:%vreg22 GPR64common:%vreg23
768B		%WZR<def> = SUBSWrr %vreg25, %vreg22, %NZCV<imp-def>; GPR32:%vreg25,%vreg22
784B		Bcc 10, <BB#4>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#4 BB#3

800B	BB#3: derived from LLVM BB %if.then.6
	    Predecessors according to CFG: BB#2
816B		B <BB#25>
	    Successors according to CFG: BB#25

832B	BB#4: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#2
848B		%vreg44<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg44
864B		%vreg43<def> = LDRWui %vreg44, 2; mem:LD4[%mode] GPR32common:%vreg43 GPR64common:%vreg44
880B		%WZR<def> = SUBSWri %vreg43, 4, 0, %NZCV<imp-def>; GPR32common:%vreg43
896B		Bcc 1, <BB#8>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#8 BB#5

912B	BB#5: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#4
928B		%vreg48<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg48
944B		%vreg47<def> = LDRWui %vreg48, 4; mem:LD4[%avail_in_expect] GPR32:%vreg47 GPR64common:%vreg48
960B		CBNZW %vreg47, <BB#8>; GPR32:%vreg47
	    Successors according to CFG: BB#8 BB#6

976B	BB#6: derived from LLVM BB %land.lhs.true.11
	    Predecessors according to CFG: BB#5
992B		%vreg54<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg54
1008B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1024B		%X0<def> = COPY %vreg54; GPR64:%vreg54
1040B		BL <ga:@isempty_RL>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>
1056B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1072B		%vreg53<def> = COPY %W0; GPR32:%vreg53
1088B		%vreg50<def> = COPY %vreg53; GPR32:%vreg50,%vreg53
1104B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1120B		STACKMAP 2, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
1136B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1152B		%vreg51<def> = UBFMWri %vreg50, 0, 7; GPR32:%vreg51,%vreg50
1168B		CBZW %vreg51, <BB#8>; GPR32:%vreg51
	    Successors according to CFG: BB#8 BB#7

1184B	BB#7: derived from LLVM BB %if.then.14
	    Predecessors according to CFG: BB#6
1200B		B <BB#25>
	    Successors according to CFG: BB#25

1216B	BB#8: derived from LLVM BB %if.end.15
	    Predecessors according to CFG: BB#4 BB#5 BB#6
1232B		%vreg63<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg63
1248B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1264B		%X0<def> = COPY %vreg63; GPR64:%vreg63
1280B		BL <ga:@prepare_new_block>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>
1296B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1312B		%vreg59<def> = MOVi32imm 2; GPR32:%vreg59
1328B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1344B		STACKMAP 3, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
1360B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1376B		%vreg61<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg61
1392B		STRWui %vreg59, %vreg61, 3; mem:ST4[%state16] GPR32:%vreg59 GPR64common:%vreg61
1408B		%vreg58<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg58
1424B		%vreg57<def> = LDRWui %vreg58, 2; mem:LD4[%mode17] GPR32common:%vreg57 GPR64common:%vreg58
1440B		%WZR<def> = SUBSWri %vreg57, 3, 0, %NZCV<imp-def>; GPR32common:%vreg57
1456B		Bcc 1, <BB#12>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#12 BB#9

1472B	BB#9: derived from LLVM BB %land.lhs.true.20
	    Predecessors according to CFG: BB#8
1488B		%vreg67<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg67
1504B		%vreg66<def> = LDRWui %vreg67, 4; mem:LD4[%avail_in_expect21] GPR32:%vreg66 GPR64common:%vreg67
1520B		CBNZW %vreg66, <BB#12>; GPR32:%vreg66
	    Successors according to CFG: BB#12 BB#10

1536B	BB#10: derived from LLVM BB %land.lhs.true.24
	    Predecessors according to CFG: BB#9
1552B		%vreg73<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg73
1568B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1584B		%X0<def> = COPY %vreg73; GPR64:%vreg73
1600B		BL <ga:@isempty_RL>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>
1616B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1632B		%vreg72<def> = COPY %W0; GPR32:%vreg72
1648B		%vreg69<def> = COPY %vreg72; GPR32:%vreg69,%vreg72
1664B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1680B		STACKMAP 4, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
1696B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1712B		%vreg70<def> = UBFMWri %vreg69, 0, 7; GPR32:%vreg70,%vreg69
1728B		CBZW %vreg70, <BB#12>; GPR32:%vreg70
	    Successors according to CFG: BB#12 BB#11

1744B	BB#11: derived from LLVM BB %if.then.28
	    Predecessors according to CFG: BB#10
1760B		B <BB#25>
	    Successors according to CFG: BB#25

1776B	BB#12: derived from LLVM BB %if.end.29
	    Predecessors according to CFG: BB#8 BB#9 BB#10
1792B		B <BB#13>
	    Successors according to CFG: BB#13

1808B	BB#13: derived from LLVM BB %if.end.30
	    Predecessors according to CFG: BB#1 BB#12
1824B		%vreg77<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg77
1840B		%vreg76<def> = LDRWui %vreg77, 3; mem:LD4[%state31] GPR32common:%vreg76 GPR64common:%vreg77
1856B		%WZR<def> = SUBSWri %vreg76, 2, 0, %NZCV<imp-def>; GPR32common:%vreg76
1872B		Bcc 1, <BB#24>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#24 BB#14

1888B	BB#14: derived from LLVM BB %if.then.34
	    Predecessors according to CFG: BB#13
1904B		%vreg95<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg95
1920B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1936B		%X0<def> = COPY %vreg95; GPR64:%vreg95
1952B		BL <ga:@copy_input_until_stop>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>
1968B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1984B		%vreg94<def> = COPY %W0; GPR32:%vreg94
2000B		%vreg91<def> = COPY %vreg94; GPR32:%vreg91,%vreg94
2016B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2032B		STACKMAP 5, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
2048B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2064B		%vreg92<def> = UBFMWri %vreg91, 0, 7; GPR32:%vreg92,%vreg91
2080B		%vreg90<def> = LDRBBui <fi#1>, 0; mem:LD1[FixedStack1] GPR32:%vreg90
2096B		%vreg87<def> = ORRWrr %vreg90, %vreg92; GPR32:%vreg87,%vreg90,%vreg92
2112B		%vreg84<def> = COPY %vreg87; GPR32:%vreg84,%vreg87
2128B		STRBBui %vreg84, <fi#1>, 0; mem:ST1[FixedStack1] GPR32:%vreg84
2144B		%vreg81<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg81
2160B		%vreg80<def> = LDRWui %vreg81, 2; mem:LD4[%mode40] GPR32common:%vreg80 GPR64common:%vreg81
2176B		%WZR<def> = SUBSWri %vreg80, 2, 0, %NZCV<imp-def>; GPR32common:%vreg80
2192B		Bcc 0, <BB#17>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#17 BB#15

2208B	BB#15: derived from LLVM BB %land.lhs.true.43
	    Predecessors according to CFG: BB#14
2224B		%vreg99<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg99
2240B		%vreg98<def> = LDRWui %vreg99, 4; mem:LD4[%avail_in_expect44] GPR32:%vreg98 GPR64common:%vreg99
2256B		CBNZW %vreg98, <BB#17>; GPR32:%vreg98
	    Successors according to CFG: BB#17 BB#16

2272B	BB#16: derived from LLVM BB %if.then.47
	    Predecessors according to CFG: BB#15
2288B		%vreg138<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg138
2304B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2320B		%X0<def> = COPY %vreg138; GPR64:%vreg138
2336B		BL <ga:@flush_RL>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>
2352B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2368B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2384B		STACKMAP 6, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
2400B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2416B		%vreg136<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg136
2432B		%vreg135<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg135
2448B		%vreg134<def> = LDRWui %vreg135, 2; mem:LD4[%mode48] GPR32common:%vreg134 GPR64common:%vreg135
2464B		%WZR<def> = SUBSWri %vreg134, 4, 0, %NZCV<imp-def>; GPR32common:%vreg134
2480B		%vreg132<def> = CSINCWr %WZR, %WZR, 1, %NZCV<imp-use,kill>; GPR32:%vreg132
2496B		%vreg130<def> = ANDWri %vreg132, 0; GPR32sp:%vreg130 GPR32:%vreg132
2512B		%vreg128<def> = COPY %vreg130; GPR32:%vreg128 GPR32sp:%vreg130
2528B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2544B		%X0<def> = COPY %vreg136; GPR64:%vreg136
2560B		%vreg126<def> = UBFMWri %vreg128, 0, 7; GPR32:%vreg126,%vreg128
2576B		%W1<def> = COPY %vreg126; GPR32:%vreg126
2592B		BL <ga:@BZ2_compressBlock>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use,kill>
2608B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2624B		%vreg121<def> = MOVi32imm 1; GPR32:%vreg121
2640B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2656B		STACKMAP 7, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
2672B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2688B		%vreg123<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg123
2704B		STRWui %vreg121, %vreg123, 3; mem:ST4[%state52] GPR32:%vreg121 GPR64common:%vreg123
2720B		B <BB#23>
	    Successors according to CFG: BB#23

2736B	BB#17: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#14 BB#15
2752B		%vreg107<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg107
2768B		%vreg106<def> = LDRWui %vreg107, 27; mem:LD4[%nblock] GPR32:%vreg106 GPR64common:%vreg107
2784B		%vreg104<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg104
2800B		%vreg103<def> = LDRWui %vreg104, 28; mem:LD4[%nblockMAX] GPR32:%vreg103 GPR64common:%vreg104
2816B		%WZR<def> = SUBSWrr %vreg106, %vreg103, %NZCV<imp-def>; GPR32:%vreg106,%vreg103
2832B		Bcc 11, <BB#19>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#19 BB#18

2848B	BB#18: derived from LLVM BB %if.then.55
	    Predecessors according to CFG: BB#17
2864B		%vreg118<def> = COPY %WZR; GPR32:%vreg118
2880B		%vreg120<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg120
2896B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2912B		%X0<def> = COPY %vreg120; GPR64:%vreg120
2928B		%vreg119<def> = UBFMWri %vreg118, 0, 7; GPR32:%vreg119,%vreg118
2944B		%W1<def> = COPY %vreg119; GPR32:%vreg119
2960B		BL <ga:@BZ2_compressBlock>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use,kill>
2976B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2992B		%vreg114<def> = MOVi32imm 1; GPR32:%vreg114
3008B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3024B		STACKMAP 8, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
3040B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3056B		%vreg116<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg116
3072B		STRWui %vreg114, %vreg116, 3; mem:ST4[%state56] GPR32:%vreg114 GPR64common:%vreg116
3088B		B <BB#22>
	    Successors according to CFG: BB#22

3104B	BB#19: derived from LLVM BB %if.else.57
	    Predecessors according to CFG: BB#17
3120B		%vreg113<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg113
3136B		%vreg112<def> = LDRXui %vreg113, 0; mem:LD8[%strm58] GPR64common:%vreg112,%vreg113
3152B		%vreg110<def> = LDRWui %vreg112, 2; mem:LD4[%avail_in] GPR32:%vreg110 GPR64common:%vreg112
3168B		CBNZW %vreg110, <BB#21>; GPR32:%vreg110
	    Successors according to CFG: BB#21 BB#20

3184B	BB#20: derived from LLVM BB %if.then.61
	    Predecessors according to CFG: BB#19
3200B		B <BB#25>
	    Successors according to CFG: BB#25

3216B	BB#21: derived from LLVM BB %if.end.62
	    Predecessors according to CFG: BB#19
3232B		B <BB#22>
	    Successors according to CFG: BB#22

3248B	BB#22: derived from LLVM BB %if.end.63
	    Predecessors according to CFG: BB#21 BB#18
3264B		B <BB#23>
	    Successors according to CFG: BB#23

3280B	BB#23: derived from LLVM BB %if.end.64
	    Predecessors according to CFG: BB#22 BB#16
3296B		B <BB#24>
	    Successors according to CFG: BB#24

3312B	BB#24: derived from LLVM BB %if.end.65
	    Predecessors according to CFG: BB#13 BB#23
3328B		B <BB#1>
	    Successors according to CFG: BB#1

3344B	BB#25: derived from LLVM BB %while.end
	    Predecessors according to CFG: BB#20 BB#11 BB#7 BB#3
3360B		%vreg139<def> = MOVi32imm 1; GPR32:%vreg139
3376B		%vreg143<def> = LDRBBui <fi#1>, 0; mem:LD1[FixedStack1] GPR32:%vreg143
3392B		%vreg152<def> = COPY %vreg139; GPR32:%vreg152,%vreg139
3408B		CBNZW %vreg143, <BB#27>; GPR32:%vreg143
	    Successors according to CFG: BB#27 BB#26

3424B	BB#26: derived from LLVM BB %lor.rhs
	    Predecessors according to CFG: BB#25
3440B		%vreg148<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32common:%vreg148
3456B		%WZR<def> = SUBSWri %vreg148, 0, 0, %NZCV<imp-def>; GPR32common:%vreg148
3472B		%vreg145<def> = CSINCWr %WZR, %WZR, 0, %NZCV<imp-use,kill>; GPR32:%vreg145
3488B		%vreg152<def> = COPY %vreg145; GPR32:%vreg152,%vreg145
	    Successors according to CFG: BB#27

3504B	BB#27: derived from LLVM BB %lor.end
	    Predecessors according to CFG: BB#25 BB#26
3520B		%vreg1<def> = COPY %vreg152; GPR32:%vreg1,%vreg152
3536B		%vreg150<def> = ANDWri %vreg1, 0; GPR32sp:%vreg150 GPR32:%vreg1
3552B		%vreg149<def,dead> = COPY %vreg150; GPR32all:%vreg149 GPR32sp:%vreg150
3568B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3584B		%vreg151<def> = MOVaddr <ga:@handle_compress>[TF=1], <ga:@handle_compress>[TF=34]; GPR64:%vreg151
3600B		%X0<def> = COPY %vreg151; GPR64:%vreg151
3616B		%X1<def> = COPY %vreg14; GPR64:%vreg14
3632B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %SP<imp-def>
3648B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3664B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3680B		STACKMAP 9, 0, %vreg150, %LR<earlyclobber,imp-def,dead>, ...; GPR32sp:%vreg150
3696B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3712B		%W0<def> = COPY %vreg150; GPR32sp:%vreg150
3728B		RET_ReallyLR %W0<imp-use>

# End machine code for function handle_compress.

********** SIMPLE REGISTER COALESCING **********
********** Function: handle_compress
********** JOINING INTERVALS ***********
if.end.15:
1264B	%X0<def> = COPY %vreg63; GPR64:%vreg63
	Considering merging %vreg63 with %X0
	Can only merge into reserved registers.
while.body:
if.end.29:
if.end.30:
if.else:
if.then:
496B	%X0<def> = COPY %vreg40; GPR64:%vreg40
	Considering merging %vreg40 with %X0
	Can only merge into reserved registers.
544B	%vreg39<def> = COPY %W0; GPR32:%vreg39
	Considering merging %vreg39 with %W0
	Can only merge into reserved registers.
if.end:
land.lhs.true:
land.lhs.true.11:
1024B	%X0<def> = COPY %vreg54; GPR64:%vreg54
	Considering merging %vreg54 with %X0
	Can only merge into reserved registers.
1072B	%vreg53<def> = COPY %W0; GPR32:%vreg53
	Considering merging %vreg53 with %W0
	Can only merge into reserved registers.
land.lhs.true.20:
land.lhs.true.24:
1584B	%X0<def> = COPY %vreg73; GPR64:%vreg73
	Considering merging %vreg73 with %X0
	Can only merge into reserved registers.
1632B	%vreg72<def> = COPY %W0; GPR32:%vreg72
	Considering merging %vreg72 with %W0
	Can only merge into reserved registers.
if.then.34:
1936B	%X0<def> = COPY %vreg95; GPR64:%vreg95
	Considering merging %vreg95 with %X0
	Can only merge into reserved registers.
1984B	%vreg94<def> = COPY %W0; GPR32:%vreg94
	Considering merging %vreg94 with %W0
	Can only merge into reserved registers.
land.lhs.true.43:
if.else.57:
if.end.63:
if.end.64:
if.end.65:
if.then.47:
2320B	%X0<def> = COPY %vreg138; GPR64:%vreg138
	Considering merging %vreg138 with %X0
	Can only merge into reserved registers.
2544B	%X0<def> = COPY %vreg136; GPR64:%vreg136
	Considering merging %vreg136 with %X0
	Can only merge into reserved registers.
2576B	%W1<def> = COPY %vreg126; GPR32:%vreg126
	Considering merging %vreg126 with %W1
	Can only merge into reserved registers.
if.then.55:
2864B	%vreg118<def> = COPY %WZR; GPR32:%vreg118
	Considering merging %vreg118 with %WZR
		RHS = %vreg118 [2864r,2928r:0)  0@2864r
		updated: 2928B	%vreg119<def> = UBFMWri %WZR, 0, 7; GPR32:%vreg119
	Success: %vreg118 -> %WZR
	Result = %WZR
2912B	%X0<def> = COPY %vreg120; GPR64:%vreg120
	Considering merging %vreg120 with %X0
	Can only merge into reserved registers.
2944B	%W1<def> = COPY %vreg119; GPR32:%vreg119
	Considering merging %vreg119 with %W1
	Can only merge into reserved registers.
if.end.62:
560B	%vreg36<def> = COPY %vreg39; GPR32:%vreg36,%vreg39
	Considering merging to GPR32 with %vreg39 in %vreg36
		RHS = %vreg39 [544r,560r:0)  0@544r
		LHS = %vreg36 [560r,624r:0)  0@560r
		merge %vreg36:0@560r into %vreg39:0@544r --> @544r
		erased:	560r	%vreg36<def> = COPY %vreg39; GPR32:%vreg36,%vreg39
		updated: 544B	%vreg36<def> = COPY %W0; GPR32:%vreg36
	Success: %vreg39 -> %vreg36
	Result = %vreg36 [544r,624r:0)  0@544r
672B	%vreg29<def> = COPY %vreg32; GPR32:%vreg29,%vreg32
	Considering merging to GPR32 with %vreg32 in %vreg29
		RHS = %vreg32 [656r,672r:0)  0@656r
		LHS = %vreg29 [672r,688r:0)  0@672r
		merge %vreg29:0@672r into %vreg32:0@656r --> @656r
		erased:	672r	%vreg29<def> = COPY %vreg32; GPR32:%vreg29,%vreg32
		updated: 656B	%vreg29<def> = ORRWrr %vreg35, %vreg37; GPR32:%vreg29,%vreg35,%vreg37
	Success: %vreg32 -> %vreg29
	Result = %vreg29 [656r,688r:0)  0@656r
1088B	%vreg50<def> = COPY %vreg53; GPR32:%vreg50,%vreg53
	Considering merging to GPR32 with %vreg53 in %vreg50
		RHS = %vreg53 [1072r,1088r:0)  0@1072r
		LHS = %vreg50 [1088r,1152r:0)  0@1088r
		merge %vreg50:0@1088r into %vreg53:0@1072r --> @1072r
		erased:	1088r	%vreg50<def> = COPY %vreg53; GPR32:%vreg50,%vreg53
		updated: 1072B	%vreg50<def> = COPY %W0; GPR32:%vreg50
	Success: %vreg53 -> %vreg50
	Result = %vreg50 [1072r,1152r:0)  0@1072r
1648B	%vreg69<def> = COPY %vreg72; GPR32:%vreg69,%vreg72
	Considering merging to GPR32 with %vreg72 in %vreg69
		RHS = %vreg72 [1632r,1648r:0)  0@1632r
		LHS = %vreg69 [1648r,1712r:0)  0@1648r
		merge %vreg69:0@1648r into %vreg72:0@1632r --> @1632r
		erased:	1648r	%vreg69<def> = COPY %vreg72; GPR32:%vreg69,%vreg72
		updated: 1632B	%vreg69<def> = COPY %W0; GPR32:%vreg69
	Success: %vreg72 -> %vreg69
	Result = %vreg69 [1632r,1712r:0)  0@1632r
2000B	%vreg91<def> = COPY %vreg94; GPR32:%vreg91,%vreg94
	Considering merging to GPR32 with %vreg94 in %vreg91
		RHS = %vreg94 [1984r,2000r:0)  0@1984r
		LHS = %vreg91 [2000r,2064r:0)  0@2000r
		merge %vreg91:0@2000r into %vreg94:0@1984r --> @1984r
		erased:	2000r	%vreg91<def> = COPY %vreg94; GPR32:%vreg91,%vreg94
		updated: 1984B	%vreg91<def> = COPY %W0; GPR32:%vreg91
	Success: %vreg94 -> %vreg91
	Result = %vreg91 [1984r,2064r:0)  0@1984r
2112B	%vreg84<def> = COPY %vreg87; GPR32:%vreg84,%vreg87
	Considering merging to GPR32 with %vreg87 in %vreg84
		RHS = %vreg87 [2096r,2112r:0)  0@2096r
		LHS = %vreg84 [2112r,2128r:0)  0@2112r
		merge %vreg84:0@2112r into %vreg87:0@2096r --> @2096r
		erased:	2112r	%vreg84<def> = COPY %vreg87; GPR32:%vreg84,%vreg87
		updated: 2096B	%vreg84<def> = ORRWrr %vreg90, %vreg92; GPR32:%vreg84,%vreg90,%vreg92
	Success: %vreg87 -> %vreg84
	Result = %vreg84 [2096r,2128r:0)  0@2096r
2512B	%vreg128<def> = COPY %vreg130; GPR32:%vreg128 GPR32sp:%vreg130
	Considering merging to GPR32common with %vreg130 in %vreg128
		RHS = %vreg130 [2496r,2512r:0)  0@2496r
		LHS = %vreg128 [2512r,2560r:0)  0@2512r
		merge %vreg128:0@2512r into %vreg130:0@2496r --> @2496r
		erased:	2512r	%vreg128<def> = COPY %vreg130; GPR32:%vreg128 GPR32sp:%vreg130
AllocationOrder(GPR32common) = [ %W8 %W9 %W10 %W11 %W12 %W13 %W14 %W15 %W16 %W17 %W18 %W0 %W1 %W2 %W3 %W4 %W5 %W6 %W7 %W19 %W20 %W21 %W22 %W23 %W24 %W25 %W26 %W27 %W28 %W30 ]
		updated: 2496B	%vreg128<def> = ANDWri %vreg132, 0; GPR32common:%vreg128 GPR32:%vreg132
	Success: %vreg130 -> %vreg128
	Result = %vreg128 [2496r,2560r:0)  0@2496r
while.end:
if.then.6:
if.then.14:
if.then.28:
if.then.61:
lor.rhs:
lor.end:
3600B	%X0<def> = COPY %vreg151; GPR64:%vreg151
	Considering merging %vreg151 with %X0
	Can only merge into reserved registers.
3616B	%X1<def> = COPY %vreg14; GPR64:%vreg14
	Considering merging %vreg14 with %X1
	Can only merge into reserved registers.
3712B	%W0<def> = COPY %vreg150; GPR32sp:%vreg150
	Considering merging %vreg150 with %W0
	Can only merge into reserved registers.
entry:
16B	%vreg14<def> = COPY %LR; GPR64:%vreg14
	Considering merging %vreg14 with %LR
	Can only merge into reserved registers.
32B	%vreg2<def> = COPY %X0; GPR64:%vreg2
	Considering merging %vreg2 with %X0
	Can only merge into reserved registers.
144B	%X0<def> = COPY %vreg12; GPR64all:%vreg12
	Considering merging %vreg12 with %X0
	Can only merge into reserved registers.
160B	%X1<def> = COPY %vreg13; GPR64all:%vreg13
	Considering merging %vreg13 with %X1
	Can only merge into reserved registers.
3392B	%vreg152<def> = COPY %vreg139; GPR32:%vreg152,%vreg139
	Considering merging to GPR32 with %vreg139 in %vreg152
		RHS = %vreg139 [3360r,3392r:0)  0@3360r
		LHS = %vreg152 [3392r,3424B:0)[3488r,3504B:1)[3504B,3520r:2)  0@3392r 1@3488r 2@3504B-phi
		merge %vreg152:0@3392r into %vreg139:0@3360r --> @3360r
		erased:	3392r	%vreg152<def> = COPY %vreg139; GPR32:%vreg152,%vreg139
		updated: 3360B	%vreg152<def> = MOVi32imm 1; GPR32:%vreg152
	Success: %vreg139 -> %vreg152
	Result = %vreg152 [3360r,3424B:0)[3488r,3504B:1)[3504B,3520r:2)  0@3360r 1@3488r 2@3504B-phi
3488B	%vreg152<def> = COPY %vreg145; GPR32:%vreg152,%vreg145
	Considering merging to GPR32 with %vreg145 in %vreg152
		RHS = %vreg145 [3472r,3488r:0)  0@3472r
		LHS = %vreg152 [3360r,3424B:0)[3488r,3504B:1)[3504B,3520r:2)  0@3360r 1@3488r 2@3504B-phi
		merge %vreg152:1@3488r into %vreg145:0@3472r --> @3472r
		erased:	3488r	%vreg152<def> = COPY %vreg145; GPR32:%vreg152,%vreg145
		updated: 3472B	%vreg152<def> = CSINCWr %WZR, %WZR, 0, %NZCV<imp-use,kill>; GPR32:%vreg152
	Success: %vreg145 -> %vreg152
	Result = %vreg152 [3360r,3424B:0)[3472r,3504B:1)[3504B,3520r:2)  0@3360r 1@3472r 2@3504B-phi
3520B	%vreg1<def> = COPY %vreg152; GPR32:%vreg1,%vreg152
	Considering merging to GPR32 with %vreg1 in %vreg152
		RHS = %vreg1 [3520r,3536r:0)  0@3520r
		LHS = %vreg152 [3360r,3424B:0)[3472r,3504B:1)[3504B,3520r:2)  0@3360r 1@3472r 2@3504B-phi
		merge %vreg1:0@3520r into %vreg152:2@3504B --> @3504B
		erased:	3520r	%vreg1<def> = COPY %vreg152; GPR32:%vreg1,%vreg152
		updated: 3536B	%vreg150<def> = ANDWri %vreg152, 0; GPR32sp:%vreg150 GPR32:%vreg152
	Success: %vreg1 -> %vreg152
	Result = %vreg152 [3360r,3424B:0)[3472r,3504B:1)[3504B,3536r:2)  0@3360r 1@3472r 2@3504B-phi
3552B	%vreg149<def,dead> = COPY %vreg150; GPR32all:%vreg149 GPR32sp:%vreg150
	Copy is dead.
Deleting dead def 3552r	%vreg149<def,dead> = COPY %vreg150; GPR32all:%vreg149 GPR32sp:%vreg150
Shrink: %vreg150 [3536r,3712r:0)  0@3536r
Shrunk: %vreg150 [3536r,3712r:0)  0@3536r
48B	%vreg3<def> = COPY %vreg2; GPR64:%vreg3,%vreg2
	Considering merging to GPR64 with %vreg2 in %vreg3
		RHS = %vreg2 [32r,48r:0)  0@32r
		LHS = %vreg3 [48r,256r:0)  0@48r
		merge %vreg3:0@48r into %vreg2:0@32r --> @32r
		erased:	48r	%vreg3<def> = COPY %vreg2; GPR64:%vreg3,%vreg2
		updated: 32B	%vreg3<def> = COPY %X0; GPR64:%vreg3
	Success: %vreg2 -> %vreg3
	Result = %vreg3 [32r,256r:0)  0@32r
96B	%vreg12<def> = COPY %vreg11; GPR64all:%vreg12 GPR64sp:%vreg11
	Considering merging to GPR64sp with %vreg11 in %vreg12
		RHS = %vreg11 [80r,96r:0)  0@80r
		LHS = %vreg12 [96r,144r:0)  0@96r
		merge %vreg12:0@96r into %vreg11:0@80r --> @80r
		erased:	96r	%vreg12<def> = COPY %vreg11; GPR64all:%vreg12 GPR64sp:%vreg11
		updated: 80B	%vreg12<def> = ADDXri %vreg10, <ga:@handle_compress>[TF=34], 0; GPR64sp:%vreg12 GPR64common:%vreg10
	Success: %vreg11 -> %vreg12
	Result = %vreg12 [80r,144r:0)  0@80r
112B	%vreg13<def> = COPY %vreg14; GPR64all:%vreg13 GPR64:%vreg14
	Considering merging to GPR64 with %vreg14 in %vreg13
		RHS = %vreg14 [16r,3616r:0)  0@16r
		LHS = %vreg13 [112r,160r:0)  0@112r
		merge %vreg13:0@112r into %vreg14:0@16r --> @16r
		erased:	112r	%vreg13<def> = COPY %vreg14; GPR64all:%vreg13 GPR64:%vreg14
		updated: 16B	%vreg13<def> = COPY %LR; GPR64:%vreg13
		updated: 3616B	%X1<def> = COPY %vreg13; GPR64:%vreg13
	Success: %vreg14 -> %vreg13
	Result = %vreg13 [16r,3616r:0)  0@16r
336B	%vreg6<def> = COPY %vreg8; GPR64:%vreg6,%vreg8
	Considering merging to GPR64 with %vreg8 in %vreg6
		RHS = %vreg8 [320r,336r:0)  0@320r
		LHS = %vreg6 [336r,352r:0)  0@336r
		merge %vreg6:0@336r into %vreg8:0@320r --> @320r
		erased:	336r	%vreg6<def> = COPY %vreg8; GPR64:%vreg6,%vreg8
		updated: 320B	%vreg6<def> = LDRXui %vreg9, 6; mem:LD8[%state] GPR64:%vreg6 GPR64common:%vreg9
	Success: %vreg8 -> %vreg6
	Result = %vreg6 [320r,352r:0)  0@320r
3616B	%X1<def> = COPY %vreg13; GPR64:%vreg13
	Considering merging %vreg13 with %X1
	Can only merge into reserved registers.
144B	%X0<def> = COPY %vreg12; GPR64sp:%vreg12
	Considering merging %vreg12 with %X0
	Can only merge into reserved registers.
160B	%X1<def> = COPY %vreg13; GPR64:%vreg13
	Considering merging %vreg13 with %X1
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
W30 [0B,16r:0)[176r,176d:20)[224e,224d:9)[512r,512d:19)[592e,592d:8)[1040r,1040d:18)[1120e,1120d:7)[1280r,1280d:17)[1344e,1344d:6)[1600r,1600d:16)[1680e,1680d:5)[1952r,1952d:15)[2032e,2032d:4)[2336r,2336d:12)[2384e,2384d:3)[2592r,2592d:13)[2656e,2656d:2)[2960r,2960d:14)[3024e,3024d:1)[3632r,3632d:11)[3680e,3680d:10)  0@0B-phi 1@3024e 2@2656e 3@2384e 4@2032e 5@1680e 6@1344e 7@1120e 8@592e 9@224e 10@3680e 11@3632r 12@2336r 13@2592r 14@2960r 15@1952r 16@1600r 17@1280r 18@1040r 19@512r 20@176r
WZR [416r,416d:8)[768r,768d:7)[880r,880d:6)[1440r,1440d:5)[1856r,1856d:4)[2176r,2176d:3)[2464r,2464d:1)[2816r,2816d:2)[3456r,3456d:0)  0@3456r 1@2464r 2@2816r 3@2176r 4@1856r 5@1440r 6@880r 7@768r 8@416r
W0 [0B,32r:0)[144r,176r:15)[496r,512r:14)[512r,544r:5)[1024r,1040r:13)[1040r,1072r:4)[1264r,1280r:12)[1584r,1600r:11)[1600r,1632r:3)[1936r,1952r:10)[1952r,1984r:2)[2320r,2336r:7)[2544r,2592r:8)[2912r,2960r:9)[3600r,3632r:6)[3712r,3728r:1)  0@0B-phi 1@3712r 2@1952r 3@1600r 4@1040r 5@512r 6@3600r 7@2320r 8@2544r 9@2912r 10@1936r 11@1584r 12@1264r 13@1024r 14@496r 15@144r
%vreg3 [32r,256r:0)  0@32r
%vreg6 [320r,352r:0)  0@320r
%vreg9 [304r,320r:0)  0@304r
%vreg10 [64r,80r:0)  0@64r
%vreg12 [80r,144r:0)  0@80r
%vreg13 [16r,3616r:0)  0@16r
%vreg17 [400r,416r:0)  0@400r
%vreg18 [384r,400r:0)  0@384r
%vreg22 [752r,768r:0)  0@752r
%vreg23 [736r,752r:0)  0@736r
%vreg25 [720r,768r:0)  0@720r
%vreg26 [704r,720r:0)  0@704r
%vreg29 [656r,688r:0)  0@656r
%vreg35 [640r,656r:0)  0@640r
%vreg36 [544r,624r:0)  0@544r
%vreg37 [624r,656r:0)  0@624r
%vreg40 [464r,496r:0)  0@464r
%vreg43 [864r,880r:0)  0@864r
%vreg44 [848r,864r:0)  0@848r
%vreg47 [944r,960r:0)  0@944r
%vreg48 [928r,944r:0)  0@928r
%vreg50 [1072r,1152r:0)  0@1072r
%vreg51 [1152r,1168r:0)  0@1152r
%vreg54 [992r,1024r:0)  0@992r
%vreg57 [1424r,1440r:0)  0@1424r
%vreg58 [1408r,1424r:0)  0@1408r
%vreg59 [1312r,1392r:0)  0@1312r
%vreg61 [1376r,1392r:0)  0@1376r
%vreg63 [1232r,1264r:0)  0@1232r
%vreg66 [1504r,1520r:0)  0@1504r
%vreg67 [1488r,1504r:0)  0@1488r
%vreg69 [1632r,1712r:0)  0@1632r
%vreg70 [1712r,1728r:0)  0@1712r
%vreg73 [1552r,1584r:0)  0@1552r
%vreg76 [1840r,1856r:0)  0@1840r
%vreg77 [1824r,1840r:0)  0@1824r
%vreg80 [2160r,2176r:0)  0@2160r
%vreg81 [2144r,2160r:0)  0@2144r
%vreg84 [2096r,2128r:0)  0@2096r
%vreg90 [2080r,2096r:0)  0@2080r
%vreg91 [1984r,2064r:0)  0@1984r
%vreg92 [2064r,2096r:0)  0@2064r
%vreg95 [1904r,1936r:0)  0@1904r
%vreg98 [2240r,2256r:0)  0@2240r
%vreg99 [2224r,2240r:0)  0@2224r
%vreg103 [2800r,2816r:0)  0@2800r
%vreg104 [2784r,2800r:0)  0@2784r
%vreg106 [2768r,2816r:0)  0@2768r
%vreg107 [2752r,2768r:0)  0@2752r
%vreg110 [3152r,3168r:0)  0@3152r
%vreg112 [3136r,3152r:0)  0@3136r
%vreg113 [3120r,3136r:0)  0@3120r
%vreg114 [2992r,3072r:0)  0@2992r
%vreg116 [3056r,3072r:0)  0@3056r
%vreg119 [2928r,2944r:0)  0@2928r
%vreg120 [2880r,2912r:0)  0@2880r
%vreg121 [2624r,2704r:0)  0@2624r
%vreg123 [2688r,2704r:0)  0@2688r
%vreg126 [2560r,2576r:0)  0@2560r
%vreg128 [2496r,2560r:0)  0@2496r
%vreg132 [2480r,2496r:0)  0@2480r
%vreg134 [2448r,2464r:0)  0@2448r
%vreg135 [2432r,2448r:0)  0@2432r
%vreg136 [2416r,2544r:0)  0@2416r
%vreg138 [2288r,2320r:0)  0@2288r
%vreg143 [3376r,3408r:0)  0@3376r
%vreg148 [3440r,3456r:0)  0@3440r
%vreg150 [3536r,3712r:0)  0@3536r
%vreg151 [3584r,3600r:0)  0@3584r
%vreg152 [3360r,3424B:0)[3472r,3504B:1)[3504B,3536r:2)  0@3360r 1@3472r 2@3504B-phi
RegMasks: 176r 512r 1040r 1280r 1600r 1952r 2336r 2592r 2960r 3632r
********** MACHINEINSTRS **********
# Machine code for function handle_compress: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
  fi#1: size=1, align=1, at location [SP]
  fi#2: size=1, align=1, at location [SP]
  fi#3: size=8, align=8, at location [SP]
Function Live Ins: %X0 in %vreg2, %LR in %vreg14

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %LR
16B		%vreg13<def> = COPY %LR; GPR64:%vreg13
32B		%vreg3<def> = COPY %X0; GPR64:%vreg3
64B		%vreg10<def> = ADRP <ga:@handle_compress>[TF=1]; GPR64common:%vreg10
80B		%vreg12<def> = ADDXri %vreg10, <ga:@handle_compress>[TF=34], 0; GPR64sp:%vreg12 GPR64common:%vreg10
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		%X0<def> = COPY %vreg12; GPR64sp:%vreg12
160B		%X1<def> = COPY %vreg13; GPR64:%vreg13
176B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
224B		STACKMAP 0, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, %vreg3, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3] LD8[FixedStack0] GPR64:%vreg3
240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
256B		STRXui %vreg3, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg3
272B		STRBBui %WZR, <fi#1>, 0; mem:ST1[FixedStack1]
288B		STRBBui %WZR, <fi#2>, 0; mem:ST1[FixedStack2]
304B		%vreg9<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg9
320B		%vreg6<def> = LDRXui %vreg9, 6; mem:LD8[%state] GPR64:%vreg6 GPR64common:%vreg9
352B		STRXui %vreg6, <fi#3>, 0; mem:ST8[FixedStack3] GPR64:%vreg6
	    Successors according to CFG: BB#1

368B	BB#1: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#0 BB#24
384B		%vreg18<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg18
400B		%vreg17<def> = LDRWui %vreg18, 3; mem:LD4[%state1] GPR32common:%vreg17 GPR64common:%vreg18
416B		%WZR<def> = SUBSWri %vreg17, 1, 0, %NZCV<imp-def>; GPR32common:%vreg17
432B		Bcc 1, <BB#13>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#13 BB#2

448B	BB#2: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#1
464B		%vreg40<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg40
480B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
496B		%X0<def> = COPY %vreg40; GPR64:%vreg40
512B		BL <ga:@copy_output_until_stop>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>
528B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
544B		%vreg36<def> = COPY %W0; GPR32:%vreg36
576B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
592B		STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
608B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
624B		%vreg37<def> = UBFMWri %vreg36, 0, 7; GPR32:%vreg37,%vreg36
640B		%vreg35<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg35
656B		%vreg29<def> = ORRWrr %vreg35, %vreg37; GPR32:%vreg29,%vreg35,%vreg37
688B		STRBBui %vreg29, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg29
704B		%vreg26<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg26
720B		%vreg25<def> = LDRWui %vreg26, 30; mem:LD4[%state_out_pos] GPR32:%vreg25 GPR64common:%vreg26
736B		%vreg23<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg23
752B		%vreg22<def> = LDRWui %vreg23, 29; mem:LD4[%numZ] GPR32:%vreg22 GPR64common:%vreg23
768B		%WZR<def> = SUBSWrr %vreg25, %vreg22, %NZCV<imp-def>; GPR32:%vreg25,%vreg22
784B		Bcc 10, <BB#4>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#4 BB#3

800B	BB#3: derived from LLVM BB %if.then.6
	    Predecessors according to CFG: BB#2
816B		B <BB#25>
	    Successors according to CFG: BB#25

832B	BB#4: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#2
848B		%vreg44<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg44
864B		%vreg43<def> = LDRWui %vreg44, 2; mem:LD4[%mode] GPR32common:%vreg43 GPR64common:%vreg44
880B		%WZR<def> = SUBSWri %vreg43, 4, 0, %NZCV<imp-def>; GPR32common:%vreg43
896B		Bcc 1, <BB#8>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#8 BB#5

912B	BB#5: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#4
928B		%vreg48<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg48
944B		%vreg47<def> = LDRWui %vreg48, 4; mem:LD4[%avail_in_expect] GPR32:%vreg47 GPR64common:%vreg48
960B		CBNZW %vreg47, <BB#8>; GPR32:%vreg47
	    Successors according to CFG: BB#8 BB#6

976B	BB#6: derived from LLVM BB %land.lhs.true.11
	    Predecessors according to CFG: BB#5
992B		%vreg54<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg54
1008B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1024B		%X0<def> = COPY %vreg54; GPR64:%vreg54
1040B		BL <ga:@isempty_RL>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>
1056B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1072B		%vreg50<def> = COPY %W0; GPR32:%vreg50
1104B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1120B		STACKMAP 2, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
1136B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1152B		%vreg51<def> = UBFMWri %vreg50, 0, 7; GPR32:%vreg51,%vreg50
1168B		CBZW %vreg51, <BB#8>; GPR32:%vreg51
	    Successors according to CFG: BB#8 BB#7

1184B	BB#7: derived from LLVM BB %if.then.14
	    Predecessors according to CFG: BB#6
1200B		B <BB#25>
	    Successors according to CFG: BB#25

1216B	BB#8: derived from LLVM BB %if.end.15
	    Predecessors according to CFG: BB#4 BB#5 BB#6
1232B		%vreg63<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg63
1248B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1264B		%X0<def> = COPY %vreg63; GPR64:%vreg63
1280B		BL <ga:@prepare_new_block>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>
1296B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1312B		%vreg59<def> = MOVi32imm 2; GPR32:%vreg59
1328B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1344B		STACKMAP 3, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
1360B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1376B		%vreg61<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg61
1392B		STRWui %vreg59, %vreg61, 3; mem:ST4[%state16] GPR32:%vreg59 GPR64common:%vreg61
1408B		%vreg58<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg58
1424B		%vreg57<def> = LDRWui %vreg58, 2; mem:LD4[%mode17] GPR32common:%vreg57 GPR64common:%vreg58
1440B		%WZR<def> = SUBSWri %vreg57, 3, 0, %NZCV<imp-def>; GPR32common:%vreg57
1456B		Bcc 1, <BB#12>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#12 BB#9

1472B	BB#9: derived from LLVM BB %land.lhs.true.20
	    Predecessors according to CFG: BB#8
1488B		%vreg67<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg67
1504B		%vreg66<def> = LDRWui %vreg67, 4; mem:LD4[%avail_in_expect21] GPR32:%vreg66 GPR64common:%vreg67
1520B		CBNZW %vreg66, <BB#12>; GPR32:%vreg66
	    Successors according to CFG: BB#12 BB#10

1536B	BB#10: derived from LLVM BB %land.lhs.true.24
	    Predecessors according to CFG: BB#9
1552B		%vreg73<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg73
1568B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1584B		%X0<def> = COPY %vreg73; GPR64:%vreg73
1600B		BL <ga:@isempty_RL>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>
1616B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1632B		%vreg69<def> = COPY %W0; GPR32:%vreg69
1664B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1680B		STACKMAP 4, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
1696B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1712B		%vreg70<def> = UBFMWri %vreg69, 0, 7; GPR32:%vreg70,%vreg69
1728B		CBZW %vreg70, <BB#12>; GPR32:%vreg70
	    Successors according to CFG: BB#12 BB#11

1744B	BB#11: derived from LLVM BB %if.then.28
	    Predecessors according to CFG: BB#10
1760B		B <BB#25>
	    Successors according to CFG: BB#25

1776B	BB#12: derived from LLVM BB %if.end.29
	    Predecessors according to CFG: BB#8 BB#9 BB#10
1792B		B <BB#13>
	    Successors according to CFG: BB#13

1808B	BB#13: derived from LLVM BB %if.end.30
	    Predecessors according to CFG: BB#1 BB#12
1824B		%vreg77<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg77
1840B		%vreg76<def> = LDRWui %vreg77, 3; mem:LD4[%state31] GPR32common:%vreg76 GPR64common:%vreg77
1856B		%WZR<def> = SUBSWri %vreg76, 2, 0, %NZCV<imp-def>; GPR32common:%vreg76
1872B		Bcc 1, <BB#24>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#24 BB#14

1888B	BB#14: derived from LLVM BB %if.then.34
	    Predecessors according to CFG: BB#13
1904B		%vreg95<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg95
1920B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1936B		%X0<def> = COPY %vreg95; GPR64:%vreg95
1952B		BL <ga:@copy_input_until_stop>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>
1968B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1984B		%vreg91<def> = COPY %W0; GPR32:%vreg91
2016B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2032B		STACKMAP 5, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
2048B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2064B		%vreg92<def> = UBFMWri %vreg91, 0, 7; GPR32:%vreg92,%vreg91
2080B		%vreg90<def> = LDRBBui <fi#1>, 0; mem:LD1[FixedStack1] GPR32:%vreg90
2096B		%vreg84<def> = ORRWrr %vreg90, %vreg92; GPR32:%vreg84,%vreg90,%vreg92
2128B		STRBBui %vreg84, <fi#1>, 0; mem:ST1[FixedStack1] GPR32:%vreg84
2144B		%vreg81<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg81
2160B		%vreg80<def> = LDRWui %vreg81, 2; mem:LD4[%mode40] GPR32common:%vreg80 GPR64common:%vreg81
2176B		%WZR<def> = SUBSWri %vreg80, 2, 0, %NZCV<imp-def>; GPR32common:%vreg80
2192B		Bcc 0, <BB#17>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#17 BB#15

2208B	BB#15: derived from LLVM BB %land.lhs.true.43
	    Predecessors according to CFG: BB#14
2224B		%vreg99<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg99
2240B		%vreg98<def> = LDRWui %vreg99, 4; mem:LD4[%avail_in_expect44] GPR32:%vreg98 GPR64common:%vreg99
2256B		CBNZW %vreg98, <BB#17>; GPR32:%vreg98
	    Successors according to CFG: BB#17 BB#16

2272B	BB#16: derived from LLVM BB %if.then.47
	    Predecessors according to CFG: BB#15
2288B		%vreg138<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg138
2304B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2320B		%X0<def> = COPY %vreg138; GPR64:%vreg138
2336B		BL <ga:@flush_RL>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>
2352B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2368B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2384B		STACKMAP 6, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
2400B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2416B		%vreg136<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg136
2432B		%vreg135<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg135
2448B		%vreg134<def> = LDRWui %vreg135, 2; mem:LD4[%mode48] GPR32common:%vreg134 GPR64common:%vreg135
2464B		%WZR<def> = SUBSWri %vreg134, 4, 0, %NZCV<imp-def>; GPR32common:%vreg134
2480B		%vreg132<def> = CSINCWr %WZR, %WZR, 1, %NZCV<imp-use,kill>; GPR32:%vreg132
2496B		%vreg128<def> = ANDWri %vreg132, 0; GPR32common:%vreg128 GPR32:%vreg132
2528B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2544B		%X0<def> = COPY %vreg136; GPR64:%vreg136
2560B		%vreg126<def> = UBFMWri %vreg128, 0, 7; GPR32:%vreg126 GPR32common:%vreg128
2576B		%W1<def> = COPY %vreg126; GPR32:%vreg126
2592B		BL <ga:@BZ2_compressBlock>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use,kill>
2608B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2624B		%vreg121<def> = MOVi32imm 1; GPR32:%vreg121
2640B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2656B		STACKMAP 7, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
2672B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2688B		%vreg123<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg123
2704B		STRWui %vreg121, %vreg123, 3; mem:ST4[%state52] GPR32:%vreg121 GPR64common:%vreg123
2720B		B <BB#23>
	    Successors according to CFG: BB#23

2736B	BB#17: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#14 BB#15
2752B		%vreg107<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg107
2768B		%vreg106<def> = LDRWui %vreg107, 27; mem:LD4[%nblock] GPR32:%vreg106 GPR64common:%vreg107
2784B		%vreg104<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg104
2800B		%vreg103<def> = LDRWui %vreg104, 28; mem:LD4[%nblockMAX] GPR32:%vreg103 GPR64common:%vreg104
2816B		%WZR<def> = SUBSWrr %vreg106, %vreg103, %NZCV<imp-def>; GPR32:%vreg106,%vreg103
2832B		Bcc 11, <BB#19>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#19 BB#18

2848B	BB#18: derived from LLVM BB %if.then.55
	    Predecessors according to CFG: BB#17
2880B		%vreg120<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg120
2896B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2912B		%X0<def> = COPY %vreg120; GPR64:%vreg120
2928B		%vreg119<def> = UBFMWri %WZR, 0, 7; GPR32:%vreg119
2944B		%W1<def> = COPY %vreg119; GPR32:%vreg119
2960B		BL <ga:@BZ2_compressBlock>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use,kill>
2976B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2992B		%vreg114<def> = MOVi32imm 1; GPR32:%vreg114
3008B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3024B		STACKMAP 8, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
3040B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3056B		%vreg116<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg116
3072B		STRWui %vreg114, %vreg116, 3; mem:ST4[%state56] GPR32:%vreg114 GPR64common:%vreg116
3088B		B <BB#22>
	    Successors according to CFG: BB#22

3104B	BB#19: derived from LLVM BB %if.else.57
	    Predecessors according to CFG: BB#17
3120B		%vreg113<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg113
3136B		%vreg112<def> = LDRXui %vreg113, 0; mem:LD8[%strm58] GPR64common:%vreg112,%vreg113
3152B		%vreg110<def> = LDRWui %vreg112, 2; mem:LD4[%avail_in] GPR32:%vreg110 GPR64common:%vreg112
3168B		CBNZW %vreg110, <BB#21>; GPR32:%vreg110
	    Successors according to CFG: BB#21 BB#20

3184B	BB#20: derived from LLVM BB %if.then.61
	    Predecessors according to CFG: BB#19
3200B		B <BB#25>
	    Successors according to CFG: BB#25

3216B	BB#21: derived from LLVM BB %if.end.62
	    Predecessors according to CFG: BB#19
3232B		B <BB#22>
	    Successors according to CFG: BB#22

3248B	BB#22: derived from LLVM BB %if.end.63
	    Predecessors according to CFG: BB#21 BB#18
3264B		B <BB#23>
	    Successors according to CFG: BB#23

3280B	BB#23: derived from LLVM BB %if.end.64
	    Predecessors according to CFG: BB#22 BB#16
3296B		B <BB#24>
	    Successors according to CFG: BB#24

3312B	BB#24: derived from LLVM BB %if.end.65
	    Predecessors according to CFG: BB#13 BB#23
3328B		B <BB#1>
	    Successors according to CFG: BB#1

3344B	BB#25: derived from LLVM BB %while.end
	    Predecessors according to CFG: BB#20 BB#11 BB#7 BB#3
3360B		%vreg152<def> = MOVi32imm 1; GPR32:%vreg152
3376B		%vreg143<def> = LDRBBui <fi#1>, 0; mem:LD1[FixedStack1] GPR32:%vreg143
3408B		CBNZW %vreg143, <BB#27>; GPR32:%vreg143
	    Successors according to CFG: BB#27 BB#26

3424B	BB#26: derived from LLVM BB %lor.rhs
	    Predecessors according to CFG: BB#25
3440B		%vreg148<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32common:%vreg148
3456B		%WZR<def> = SUBSWri %vreg148, 0, 0, %NZCV<imp-def>; GPR32common:%vreg148
3472B		%vreg152<def> = CSINCWr %WZR, %WZR, 0, %NZCV<imp-use,kill>; GPR32:%vreg152
	    Successors according to CFG: BB#27

3504B	BB#27: derived from LLVM BB %lor.end
	    Predecessors according to CFG: BB#25 BB#26
3536B		%vreg150<def> = ANDWri %vreg152, 0; GPR32sp:%vreg150 GPR32:%vreg152
3568B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3584B		%vreg151<def> = MOVaddr <ga:@handle_compress>[TF=1], <ga:@handle_compress>[TF=34]; GPR64:%vreg151
3600B		%X0<def> = COPY %vreg151; GPR64:%vreg151
3616B		%X1<def> = COPY %vreg13; GPR64:%vreg13
3632B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %SP<imp-def>
3648B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3664B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3680B		STACKMAP 9, 0, %vreg150, %LR<earlyclobber,imp-def,dead>, ...; GPR32sp:%vreg150
3696B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3712B		%W0<def> = COPY %vreg150; GPR32sp:%vreg150
3728B		RET_ReallyLR %W0<imp-use>

# End machine code for function handle_compress.

handleMove 720B -> 744B: %vreg25<def> = LDRWui %vreg26, 30; mem:LD4[%state_out_pos] GPR32:%vreg25 GPR64common:%vreg26
     %vreg25:	[720r,768r:0)  0@720r
        -->	[744r,768r:0)  0@744r
     %vreg26:	[704r,720r:0)  0@704r
        -->	[704r,744r:0)  0@704r
handleMove 624B -> 648B: %vreg37<def> = UBFMWri %vreg36, 0, 7; GPR32:%vreg37,%vreg36
     %vreg37:	[624r,656r:0)  0@624r
        -->	[648r,656r:0)  0@648r
     %vreg36:	[544r,624r:0)  0@544r
        -->	[544r,648r:0)  0@544r
handleMove 2064B -> 2088B: %vreg92<def> = UBFMWri %vreg91, 0, 7; GPR32:%vreg92,%vreg91
     %vreg92:	[2064r,2096r:0)  0@2064r
        -->	[2088r,2096r:0)  0@2088r
     %vreg91:	[1984r,2064r:0)  0@1984r
        -->	[1984r,2088r:0)  0@1984r
handleMove 2560B -> 2536B: %vreg126<def> = UBFMWri %vreg128, 0, 7; GPR32:%vreg126 GPR32common:%vreg128
     %vreg126:	[2560r,2576r:0)  0@2560r
        -->	[2536r,2576r:0)  0@2536r
     %vreg128:	[2496r,2560r:0)  0@2496r
        -->	[2496r,2536r:0)  0@2496r
handleMove 2416B -> 2456B: %vreg136<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg136
     %vreg136:	[2416r,2544r:0)  0@2416r
        -->	[2456r,2544r:0)  0@2456r
handleMove 2768B -> 2792B: %vreg106<def> = LDRWui %vreg107, 27; mem:LD4[%nblock] GPR32:%vreg106 GPR64common:%vreg107
     %vreg106:	[2768r,2816r:0)  0@2768r
        -->	[2792r,2816r:0)  0@2792r
     %vreg107:	[2752r,2768r:0)  0@2752r
        -->	[2752r,2792r:0)  0@2752r
handleMove 2928B -> 2904B: %vreg119<def> = UBFMWri %WZR, 0, 7; GPR32:%vreg119
     %vreg119:	[2928r,2944r:0)  0@2928r
        -->	[2904r,2944r:0)  0@2904r
     WZR:	[416r,416d:8)[768r,768d:7)[880r,880d:6)[1440r,1440d:5)[1856r,1856d:4)[2176r,2176d:3)[2464r,2464d:1)[2816r,2816d:2)[3456r,3456d:0)  0@3456r 1@2464r 2@2816r 3@2176r 4@1856r 5@1440r 6@880r 7@768r 8@416r
        -->	[416r,416d:8)[768r,768d:7)[880r,880d:6)[1440r,1440d:5)[1856r,1856d:4)[2176r,2176d:3)[2464r,2464d:1)[2816r,2816d:2)[3456r,3456d:0)  0@3456r 1@2464r 2@2816r 3@2176r 4@1856r 5@1440r 6@880r 7@768r 8@416r
handleMove 3360B -> 3384B: %vreg152<def> = MOVi32imm 1; GPR32:%vreg152
     %vreg152:	[3360r,3424B:0)[3472r,3504B:1)[3504B,3536r:2)  0@3360r 1@3472r 2@3504B-phi
        -->	[3384r,3424B:0)[3472r,3504B:1)[3504B,3536r:2)  0@3384r 1@3472r 2@3504B-phi
********** GREEDY REGISTER ALLOCATION **********
********** Function: handle_compress
********** INTERVALS **********
W30 [0B,16r:0)[176r,176d:20)[224e,224d:9)[512r,512d:19)[592e,592d:8)[1040r,1040d:18)[1120e,1120d:7)[1280r,1280d:17)[1344e,1344d:6)[1600r,1600d:16)[1680e,1680d:5)[1952r,1952d:15)[2032e,2032d:4)[2336r,2336d:12)[2384e,2384d:3)[2592r,2592d:13)[2656e,2656d:2)[2960r,2960d:14)[3024e,3024d:1)[3632r,3632d:11)[3680e,3680d:10)  0@0B-phi 1@3024e 2@2656e 3@2384e 4@2032e 5@1680e 6@1344e 7@1120e 8@592e 9@224e 10@3680e 11@3632r 12@2336r 13@2592r 14@2960r 15@1952r 16@1600r 17@1280r 18@1040r 19@512r 20@176r
WZR [416r,416d:8)[768r,768d:7)[880r,880d:6)[1440r,1440d:5)[1856r,1856d:4)[2176r,2176d:3)[2464r,2464d:1)[2816r,2816d:2)[3456r,3456d:0)  0@3456r 1@2464r 2@2816r 3@2176r 4@1856r 5@1440r 6@880r 7@768r 8@416r
W0 [0B,32r:0)[144r,176r:15)[496r,512r:14)[512r,544r:5)[1024r,1040r:13)[1040r,1072r:4)[1264r,1280r:12)[1584r,1600r:11)[1600r,1632r:3)[1936r,1952r:10)[1952r,1984r:2)[2320r,2336r:7)[2544r,2592r:8)[2912r,2960r:9)[3600r,3632r:6)[3712r,3728r:1)  0@0B-phi 1@3712r 2@1952r 3@1600r 4@1040r 5@512r 6@3600r 7@2320r 8@2544r 9@2912r 10@1936r 11@1584r 12@1264r 13@1024r 14@496r 15@144r
%vreg3 [32r,256r:0)  0@32r
%vreg6 [320r,352r:0)  0@320r
%vreg9 [304r,320r:0)  0@304r
%vreg10 [64r,80r:0)  0@64r
%vreg12 [80r,144r:0)  0@80r
%vreg13 [16r,3616r:0)  0@16r
%vreg17 [400r,416r:0)  0@400r
%vreg18 [384r,400r:0)  0@384r
%vreg22 [752r,768r:0)  0@752r
%vreg23 [736r,752r:0)  0@736r
%vreg25 [744r,768r:0)  0@744r
%vreg26 [704r,744r:0)  0@704r
%vreg29 [656r,688r:0)  0@656r
%vreg35 [640r,656r:0)  0@640r
%vreg36 [544r,648r:0)  0@544r
%vreg37 [648r,656r:0)  0@648r
%vreg40 [464r,496r:0)  0@464r
%vreg43 [864r,880r:0)  0@864r
%vreg44 [848r,864r:0)  0@848r
%vreg47 [944r,960r:0)  0@944r
%vreg48 [928r,944r:0)  0@928r
%vreg50 [1072r,1152r:0)  0@1072r
%vreg51 [1152r,1168r:0)  0@1152r
%vreg54 [992r,1024r:0)  0@992r
%vreg57 [1424r,1440r:0)  0@1424r
%vreg58 [1408r,1424r:0)  0@1408r
%vreg59 [1312r,1392r:0)  0@1312r
%vreg61 [1376r,1392r:0)  0@1376r
%vreg63 [1232r,1264r:0)  0@1232r
%vreg66 [1504r,1520r:0)  0@1504r
%vreg67 [1488r,1504r:0)  0@1488r
%vreg69 [1632r,1712r:0)  0@1632r
%vreg70 [1712r,1728r:0)  0@1712r
%vreg73 [1552r,1584r:0)  0@1552r
%vreg76 [1840r,1856r:0)  0@1840r
%vreg77 [1824r,1840r:0)  0@1824r
%vreg80 [2160r,2176r:0)  0@2160r
%vreg81 [2144r,2160r:0)  0@2144r
%vreg84 [2096r,2128r:0)  0@2096r
%vreg90 [2080r,2096r:0)  0@2080r
%vreg91 [1984r,2088r:0)  0@1984r
%vreg92 [2088r,2096r:0)  0@2088r
%vreg95 [1904r,1936r:0)  0@1904r
%vreg98 [2240r,2256r:0)  0@2240r
%vreg99 [2224r,2240r:0)  0@2224r
%vreg103 [2800r,2816r:0)  0@2800r
%vreg104 [2784r,2800r:0)  0@2784r
%vreg106 [2792r,2816r:0)  0@2792r
%vreg107 [2752r,2792r:0)  0@2752r
%vreg110 [3152r,3168r:0)  0@3152r
%vreg112 [3136r,3152r:0)  0@3136r
%vreg113 [3120r,3136r:0)  0@3120r
%vreg114 [2992r,3072r:0)  0@2992r
%vreg116 [3056r,3072r:0)  0@3056r
%vreg119 [2904r,2944r:0)  0@2904r
%vreg120 [2880r,2912r:0)  0@2880r
%vreg121 [2624r,2704r:0)  0@2624r
%vreg123 [2688r,2704r:0)  0@2688r
%vreg126 [2536r,2576r:0)  0@2536r
%vreg128 [2496r,2536r:0)  0@2496r
%vreg132 [2480r,2496r:0)  0@2480r
%vreg134 [2448r,2464r:0)  0@2448r
%vreg135 [2432r,2448r:0)  0@2432r
%vreg136 [2456r,2544r:0)  0@2456r
%vreg138 [2288r,2320r:0)  0@2288r
%vreg143 [3376r,3408r:0)  0@3376r
%vreg148 [3440r,3456r:0)  0@3440r
%vreg150 [3536r,3712r:0)  0@3536r
%vreg151 [3584r,3600r:0)  0@3584r
%vreg152 [3384r,3424B:0)[3472r,3504B:1)[3504B,3536r:2)  0@3384r 1@3472r 2@3504B-phi
RegMasks: 176r 512r 1040r 1280r 1600r 1952r 2336r 2592r 2960r 3632r
********** MACHINEINSTRS **********
# Machine code for function handle_compress: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
  fi#1: size=1, align=1, at location [SP]
  fi#2: size=1, align=1, at location [SP]
  fi#3: size=8, align=8, at location [SP]
Function Live Ins: %X0 in %vreg2, %LR in %vreg14

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %LR
16B		%vreg13<def> = COPY %LR; GPR64:%vreg13
32B		%vreg3<def> = COPY %X0; GPR64:%vreg3
64B		%vreg10<def> = ADRP <ga:@handle_compress>[TF=1]; GPR64common:%vreg10
80B		%vreg12<def> = ADDXri %vreg10, <ga:@handle_compress>[TF=34], 0; GPR64sp:%vreg12 GPR64common:%vreg10
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		%X0<def> = COPY %vreg12; GPR64sp:%vreg12
160B		%X1<def> = COPY %vreg13; GPR64:%vreg13
176B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
224B		STACKMAP 0, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, %vreg3, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3] LD8[FixedStack0] GPR64:%vreg3
240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
256B		STRXui %vreg3, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg3
272B		STRBBui %WZR, <fi#1>, 0; mem:ST1[FixedStack1]
288B		STRBBui %WZR, <fi#2>, 0; mem:ST1[FixedStack2]
304B		%vreg9<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg9
320B		%vreg6<def> = LDRXui %vreg9, 6; mem:LD8[%state] GPR64:%vreg6 GPR64common:%vreg9
352B		STRXui %vreg6, <fi#3>, 0; mem:ST8[FixedStack3] GPR64:%vreg6
	    Successors according to CFG: BB#1

368B	BB#1: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#0 BB#24
384B		%vreg18<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg18
400B		%vreg17<def> = LDRWui %vreg18, 3; mem:LD4[%state1] GPR32common:%vreg17 GPR64common:%vreg18
416B		%WZR<def> = SUBSWri %vreg17, 1, 0, %NZCV<imp-def>; GPR32common:%vreg17
432B		Bcc 1, <BB#13>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#13 BB#2

448B	BB#2: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#1
464B		%vreg40<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg40
480B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
496B		%X0<def> = COPY %vreg40; GPR64:%vreg40
512B		BL <ga:@copy_output_until_stop>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>
528B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
544B		%vreg36<def> = COPY %W0; GPR32:%vreg36
576B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
592B		STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
608B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
640B		%vreg35<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg35
648B		%vreg37<def> = UBFMWri %vreg36, 0, 7; GPR32:%vreg37,%vreg36
656B		%vreg29<def> = ORRWrr %vreg35, %vreg37; GPR32:%vreg29,%vreg35,%vreg37
688B		STRBBui %vreg29, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg29
704B		%vreg26<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg26
736B		%vreg23<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg23
744B		%vreg25<def> = LDRWui %vreg26, 30; mem:LD4[%state_out_pos] GPR32:%vreg25 GPR64common:%vreg26
752B		%vreg22<def> = LDRWui %vreg23, 29; mem:LD4[%numZ] GPR32:%vreg22 GPR64common:%vreg23
768B		%WZR<def> = SUBSWrr %vreg25, %vreg22, %NZCV<imp-def>; GPR32:%vreg25,%vreg22
784B		Bcc 10, <BB#4>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#4 BB#3

800B	BB#3: derived from LLVM BB %if.then.6
	    Predecessors according to CFG: BB#2
816B		B <BB#25>
	    Successors according to CFG: BB#25

832B	BB#4: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#2
848B		%vreg44<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg44
864B		%vreg43<def> = LDRWui %vreg44, 2; mem:LD4[%mode] GPR32common:%vreg43 GPR64common:%vreg44
880B		%WZR<def> = SUBSWri %vreg43, 4, 0, %NZCV<imp-def>; GPR32common:%vreg43
896B		Bcc 1, <BB#8>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#8 BB#5

912B	BB#5: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#4
928B		%vreg48<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg48
944B		%vreg47<def> = LDRWui %vreg48, 4; mem:LD4[%avail_in_expect] GPR32:%vreg47 GPR64common:%vreg48
960B		CBNZW %vreg47, <BB#8>; GPR32:%vreg47
	    Successors according to CFG: BB#8 BB#6

976B	BB#6: derived from LLVM BB %land.lhs.true.11
	    Predecessors according to CFG: BB#5
992B		%vreg54<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg54
1008B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1024B		%X0<def> = COPY %vreg54; GPR64:%vreg54
1040B		BL <ga:@isempty_RL>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>
1056B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1072B		%vreg50<def> = COPY %W0; GPR32:%vreg50
1104B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1120B		STACKMAP 2, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
1136B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1152B		%vreg51<def> = UBFMWri %vreg50, 0, 7; GPR32:%vreg51,%vreg50
1168B		CBZW %vreg51, <BB#8>; GPR32:%vreg51
	    Successors according to CFG: BB#8 BB#7

1184B	BB#7: derived from LLVM BB %if.then.14
	    Predecessors according to CFG: BB#6
1200B		B <BB#25>
	    Successors according to CFG: BB#25

1216B	BB#8: derived from LLVM BB %if.end.15
	    Predecessors according to CFG: BB#4 BB#5 BB#6
1232B		%vreg63<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg63
1248B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1264B		%X0<def> = COPY %vreg63; GPR64:%vreg63
1280B		BL <ga:@prepare_new_block>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>
1296B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1312B		%vreg59<def> = MOVi32imm 2; GPR32:%vreg59
1328B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1344B		STACKMAP 3, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
1360B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1376B		%vreg61<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg61
1392B		STRWui %vreg59, %vreg61, 3; mem:ST4[%state16] GPR32:%vreg59 GPR64common:%vreg61
1408B		%vreg58<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg58
1424B		%vreg57<def> = LDRWui %vreg58, 2; mem:LD4[%mode17] GPR32common:%vreg57 GPR64common:%vreg58
1440B		%WZR<def> = SUBSWri %vreg57, 3, 0, %NZCV<imp-def>; GPR32common:%vreg57
1456B		Bcc 1, <BB#12>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#12 BB#9

1472B	BB#9: derived from LLVM BB %land.lhs.true.20
	    Predecessors according to CFG: BB#8
1488B		%vreg67<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg67
1504B		%vreg66<def> = LDRWui %vreg67, 4; mem:LD4[%avail_in_expect21] GPR32:%vreg66 GPR64common:%vreg67
1520B		CBNZW %vreg66, <BB#12>; GPR32:%vreg66
	    Successors according to CFG: BB#12 BB#10

1536B	BB#10: derived from LLVM BB %land.lhs.true.24
	    Predecessors according to CFG: BB#9
1552B		%vreg73<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg73
1568B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1584B		%X0<def> = COPY %vreg73; GPR64:%vreg73
1600B		BL <ga:@isempty_RL>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>
1616B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1632B		%vreg69<def> = COPY %W0; GPR32:%vreg69
1664B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1680B		STACKMAP 4, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
1696B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1712B		%vreg70<def> = UBFMWri %vreg69, 0, 7; GPR32:%vreg70,%vreg69
1728B		CBZW %vreg70, <BB#12>; GPR32:%vreg70
	    Successors according to CFG: BB#12 BB#11

1744B	BB#11: derived from LLVM BB %if.then.28
	    Predecessors according to CFG: BB#10
1760B		B <BB#25>
	    Successors according to CFG: BB#25

1776B	BB#12: derived from LLVM BB %if.end.29
	    Predecessors according to CFG: BB#8 BB#9 BB#10
1792B		B <BB#13>
	    Successors according to CFG: BB#13

1808B	BB#13: derived from LLVM BB %if.end.30
	    Predecessors according to CFG: BB#1 BB#12
1824B		%vreg77<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg77
1840B		%vreg76<def> = LDRWui %vreg77, 3; mem:LD4[%state31] GPR32common:%vreg76 GPR64common:%vreg77
1856B		%WZR<def> = SUBSWri %vreg76, 2, 0, %NZCV<imp-def>; GPR32common:%vreg76
1872B		Bcc 1, <BB#24>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#24 BB#14

1888B	BB#14: derived from LLVM BB %if.then.34
	    Predecessors according to CFG: BB#13
1904B		%vreg95<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg95
1920B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1936B		%X0<def> = COPY %vreg95; GPR64:%vreg95
1952B		BL <ga:@copy_input_until_stop>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>
1968B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1984B		%vreg91<def> = COPY %W0; GPR32:%vreg91
2016B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2032B		STACKMAP 5, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
2048B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2080B		%vreg90<def> = LDRBBui <fi#1>, 0; mem:LD1[FixedStack1] GPR32:%vreg90
2088B		%vreg92<def> = UBFMWri %vreg91, 0, 7; GPR32:%vreg92,%vreg91
2096B		%vreg84<def> = ORRWrr %vreg90, %vreg92; GPR32:%vreg84,%vreg90,%vreg92
2128B		STRBBui %vreg84, <fi#1>, 0; mem:ST1[FixedStack1] GPR32:%vreg84
2144B		%vreg81<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg81
2160B		%vreg80<def> = LDRWui %vreg81, 2; mem:LD4[%mode40] GPR32common:%vreg80 GPR64common:%vreg81
2176B		%WZR<def> = SUBSWri %vreg80, 2, 0, %NZCV<imp-def>; GPR32common:%vreg80
2192B		Bcc 0, <BB#17>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#17 BB#15

2208B	BB#15: derived from LLVM BB %land.lhs.true.43
	    Predecessors according to CFG: BB#14
2224B		%vreg99<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg99
2240B		%vreg98<def> = LDRWui %vreg99, 4; mem:LD4[%avail_in_expect44] GPR32:%vreg98 GPR64common:%vreg99
2256B		CBNZW %vreg98, <BB#17>; GPR32:%vreg98
	    Successors according to CFG: BB#17 BB#16

2272B	BB#16: derived from LLVM BB %if.then.47
	    Predecessors according to CFG: BB#15
2288B		%vreg138<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg138
2304B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2320B		%X0<def> = COPY %vreg138; GPR64:%vreg138
2336B		BL <ga:@flush_RL>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>
2352B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2368B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2384B		STACKMAP 6, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
2400B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2432B		%vreg135<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg135
2448B		%vreg134<def> = LDRWui %vreg135, 2; mem:LD4[%mode48] GPR32common:%vreg134 GPR64common:%vreg135
2456B		%vreg136<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg136
2464B		%WZR<def> = SUBSWri %vreg134, 4, 0, %NZCV<imp-def>; GPR32common:%vreg134
2480B		%vreg132<def> = CSINCWr %WZR, %WZR, 1, %NZCV<imp-use,kill>; GPR32:%vreg132
2496B		%vreg128<def> = ANDWri %vreg132, 0; GPR32common:%vreg128 GPR32:%vreg132
2528B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2536B		%vreg126<def> = UBFMWri %vreg128, 0, 7; GPR32:%vreg126 GPR32common:%vreg128
2544B		%X0<def> = COPY %vreg136; GPR64:%vreg136
2576B		%W1<def> = COPY %vreg126; GPR32:%vreg126
2592B		BL <ga:@BZ2_compressBlock>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use,kill>
2608B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2624B		%vreg121<def> = MOVi32imm 1; GPR32:%vreg121
2640B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2656B		STACKMAP 7, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
2672B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2688B		%vreg123<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg123
2704B		STRWui %vreg121, %vreg123, 3; mem:ST4[%state52] GPR32:%vreg121 GPR64common:%vreg123
2720B		B <BB#23>
	    Successors according to CFG: BB#23

2736B	BB#17: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#14 BB#15
2752B		%vreg107<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg107
2784B		%vreg104<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg104
2792B		%vreg106<def> = LDRWui %vreg107, 27; mem:LD4[%nblock] GPR32:%vreg106 GPR64common:%vreg107
2800B		%vreg103<def> = LDRWui %vreg104, 28; mem:LD4[%nblockMAX] GPR32:%vreg103 GPR64common:%vreg104
2816B		%WZR<def> = SUBSWrr %vreg106, %vreg103, %NZCV<imp-def>; GPR32:%vreg106,%vreg103
2832B		Bcc 11, <BB#19>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#19 BB#18

2848B	BB#18: derived from LLVM BB %if.then.55
	    Predecessors according to CFG: BB#17
2880B		%vreg120<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg120
2896B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2904B		%vreg119<def> = UBFMWri %WZR, 0, 7; GPR32:%vreg119
2912B		%X0<def> = COPY %vreg120; GPR64:%vreg120
2944B		%W1<def> = COPY %vreg119; GPR32:%vreg119
2960B		BL <ga:@BZ2_compressBlock>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use,kill>
2976B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2992B		%vreg114<def> = MOVi32imm 1; GPR32:%vreg114
3008B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3024B		STACKMAP 8, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
3040B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3056B		%vreg116<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg116
3072B		STRWui %vreg114, %vreg116, 3; mem:ST4[%state56] GPR32:%vreg114 GPR64common:%vreg116
3088B		B <BB#22>
	    Successors according to CFG: BB#22

3104B	BB#19: derived from LLVM BB %if.else.57
	    Predecessors according to CFG: BB#17
3120B		%vreg113<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg113
3136B		%vreg112<def> = LDRXui %vreg113, 0; mem:LD8[%strm58] GPR64common:%vreg112,%vreg113
3152B		%vreg110<def> = LDRWui %vreg112, 2; mem:LD4[%avail_in] GPR32:%vreg110 GPR64common:%vreg112
3168B		CBNZW %vreg110, <BB#21>; GPR32:%vreg110
	    Successors according to CFG: BB#21 BB#20

3184B	BB#20: derived from LLVM BB %if.then.61
	    Predecessors according to CFG: BB#19
3200B		B <BB#25>
	    Successors according to CFG: BB#25

3216B	BB#21: derived from LLVM BB %if.end.62
	    Predecessors according to CFG: BB#19
3232B		B <BB#22>
	    Successors according to CFG: BB#22

3248B	BB#22: derived from LLVM BB %if.end.63
	    Predecessors according to CFG: BB#21 BB#18
3264B		B <BB#23>
	    Successors according to CFG: BB#23

3280B	BB#23: derived from LLVM BB %if.end.64
	    Predecessors according to CFG: BB#22 BB#16
3296B		B <BB#24>
	    Successors according to CFG: BB#24

3312B	BB#24: derived from LLVM BB %if.end.65
	    Predecessors according to CFG: BB#13 BB#23
3328B		B <BB#1>
	    Successors according to CFG: BB#1

3344B	BB#25: derived from LLVM BB %while.end
	    Predecessors according to CFG: BB#20 BB#11 BB#7 BB#3
3376B		%vreg143<def> = LDRBBui <fi#1>, 0; mem:LD1[FixedStack1] GPR32:%vreg143
3384B		%vreg152<def> = MOVi32imm 1; GPR32:%vreg152
3408B		CBNZW %vreg143, <BB#27>; GPR32:%vreg143
	    Successors according to CFG: BB#27 BB#26

3424B	BB#26: derived from LLVM BB %lor.rhs
	    Predecessors according to CFG: BB#25
3440B		%vreg148<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32common:%vreg148
3456B		%WZR<def> = SUBSWri %vreg148, 0, 0, %NZCV<imp-def>; GPR32common:%vreg148
3472B		%vreg152<def> = CSINCWr %WZR, %WZR, 0, %NZCV<imp-use,kill>; GPR32:%vreg152
	    Successors according to CFG: BB#27

3504B	BB#27: derived from LLVM BB %lor.end
	    Predecessors according to CFG: BB#25 BB#26
3536B		%vreg150<def> = ANDWri %vreg152, 0; GPR32sp:%vreg150 GPR32:%vreg152
3568B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3584B		%vreg151<def> = MOVaddr <ga:@handle_compress>[TF=1], <ga:@handle_compress>[TF=34]; GPR64:%vreg151
3600B		%X0<def> = COPY %vreg151; GPR64:%vreg151
3616B		%X1<def> = COPY %vreg13; GPR64:%vreg13
3632B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %SP<imp-def>
3648B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3664B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3680B		STACKMAP 9, 0, %vreg150, %LR<earlyclobber,imp-def,dead>, ...; GPR32sp:%vreg150
3696B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3712B		%W0<def> = COPY %vreg150; GPR32sp:%vreg150
3728B		RET_ReallyLR %W0<imp-use>

# End machine code for function handle_compress.


selectOrSplit GPR64:%vreg13 [16r,3616r:0)  0@16r w=7.574999e-04
hints: %X1
missed hint %X1
assigning %vreg13 to %X19: W19 [16r,3616r:0)  0@16r

selectOrSplit GPR64:%vreg3 [32r,256r:0)  0@32r w=4.855769e-03
hints: %X0
missed hint %X0
assigning %vreg3 to %X20: W20 [32r,256r:0)  0@32r

selectOrSplit GPR64sp:%vreg12 [80r,144r:0)  0@80r w=4.353448e-03
hints: %X0
assigning %vreg12 to %X0: W0 [80r,144r:0)  0@80r

selectOrSplit GPR64:%vreg40 [464r,496r:0)  0@464r w=6.263167e-03
hints: %X0
assigning %vreg40 to %X0: W0 [464r,496r:0)  0@464r

selectOrSplit GPR32:%vreg36 [544r,648r:0)  0@544r w=5.368429e-03
hints: %W0
assigning %vreg36 to %W0: W0 [544r,648r:0)  0@544r

selectOrSplit GPR64:%vreg54 [992r,1024r:0)  0@992r w=7.721712e-04
hints: %X0
assigning %vreg54 to %X0: W0 [992r,1024r:0)  0@992r

selectOrSplit GPR32:%vreg50 [1072r,1152r:0)  0@1072r w=6.949541e-04
hints: %W0
assigning %vreg50 to %W0: W0 [1072r,1152r:0)  0@1072r

selectOrSplit GPR64:%vreg63 [1232r,1264r:0)  0@1232r w=2.702599e-03
hints: %X0
assigning %vreg63 to %X0: W0 [1232r,1264r:0)  0@1232r

selectOrSplit GPR64:%vreg73 [1552r,1584r:0)  0@1552r w=6.863744e-04
hints: %X0
assigning %vreg73 to %X0: W0 [1552r,1584r:0)  0@1552r

selectOrSplit GPR32:%vreg69 [1632r,1712r:0)  0@1632r w=6.177370e-04
hints: %W0
assigning %vreg69 to %W0: W0 [1632r,1712r:0)  0@1632r

selectOrSplit GPR64:%vreg95 [1904r,1936r:0)  0@1904r w=4.332738e-03
hints: %X0
assigning %vreg95 to %X0: W0 [1904r,1936r:0)  0@1904r

selectOrSplit GPR32:%vreg91 [1984r,2088r:0)  0@1984r w=3.713776e-03
hints: %W0
assigning %vreg91 to %W0: W0 [1984r,2088r:0)  0@1984r

selectOrSplit GPR64:%vreg138 [2288r,2320r:0)  0@2288r w=1.072460e-03
hints: %X0
assigning %vreg138 to %X0: W0 [2288r,2320r:0)  0@2288r

selectOrSplit GPR64:%vreg136 [2456r,2544r:0)  0@2456r w=9.493908e-04
hints: %X0
assigning %vreg136 to %X0: W0 [2456r,2544r:0)  0@2456r

selectOrSplit GPR32:%vreg126 [2536r,2576r:0)  0@2536r w=1.052961e-03
hints: %W1
assigning %vreg126 to %W1: W1 [2536r,2576r:0)  0@2536r

selectOrSplit GPR64:%vreg120 [2880r,2912r:0)  0@2880r w=1.587241e-03
hints: %X0
assigning %vreg120 to %X0: W0 [2880r,2912r:0)  0@2880r

selectOrSplit GPR32:%vreg119 [2904r,2944r:0)  0@2904r w=1.558382e-03
hints: %W1
assigning %vreg119 to %W1: W1 [2904r,2944r:0)  0@2904r

selectOrSplit GPR32sp:%vreg150 [3536r,3712r:0)  0@3536r w=5.260416e-03
AllocationOrder(GPR32sp) = [ %W8 %W9 %W10 %W11 %W12 %W13 %W14 %W15 %W16 %W17 %W18 %W0 %W1 %W2 %W3 %W4 %W5 %W6 %W7 %W19 %W20 %W21 %W22 %W23 %W24 %W25 %W26 %W27 %W28 %W30 ]
hints: %W0
missed hint %W0
assigning %vreg150 to %W20: W20 [3536r,3712r:0)  0@3536r

selectOrSplit GPR64:%vreg151 [3584r,3600r:0)  0@3584r w=inf
hints: %X0
assigning %vreg151 to %X0: W0 [3584r,3600r:0)  0@3584r

selectOrSplit GPR32:%vreg152 [3384r,3424B:0)[3472r,3504B:1)[3504B,3536r:2)  0@3384r 1@3472r 2@3504B-phi w=4.970942e-03
assigning %vreg152 to %W8: W8 [3384r,3424B:0)[3472r,3504B:1)[3504B,3536r:2)  0@3384r 1@3472r 2@3504B-phi

selectOrSplit GPR64common:%vreg10 [64r,80r:0)  0@64r w=inf
assigning %vreg10 to %X8: W8 [64r,80r:0)  0@64r

selectOrSplit GPR64common:%vreg9 [304r,320r:0)  0@304r w=inf
assigning %vreg9 to %X8: W8 [304r,320r:0)  0@304r

selectOrSplit GPR64:%vreg6 [320r,352r:0)  0@320r w=inf
assigning %vreg6 to %X8: W8 [320r,352r:0)  0@320r

selectOrSplit GPR64common:%vreg18 [384r,400r:0)  0@384r w=inf
assigning %vreg18 to %X8: W8 [384r,400r:0)  0@384r

selectOrSplit GPR32common:%vreg17 [400r,416r:0)  0@400r w=inf
assigning %vreg17 to %W8: W8 [400r,416r:0)  0@400r

selectOrSplit GPR32:%vreg35 [640r,656r:0)  0@640r w=6.439661e-03
assigning %vreg35 to %W8: W8 [640r,656r:0)  0@640r

selectOrSplit GPR32:%vreg37 [648r,656r:0)  0@648r w=inf
assigning %vreg37 to %W9: W9 [648r,656r:0)  0@648r

selectOrSplit GPR32:%vreg29 [656r,688r:0)  0@656r w=inf
assigning %vreg29 to %W8: W8 [656r,688r:0)  0@656r

selectOrSplit GPR64common:%vreg26 [704r,744r:0)  0@704r w=6.088407e-03
assigning %vreg26 to %X8: W8 [704r,744r:0)  0@704r

selectOrSplit GPR64common:%vreg23 [736r,752r:0)  0@736r w=6.439661e-03
assigning %vreg23 to %X9: W9 [736r,752r:0)  0@736r

selectOrSplit GPR32:%vreg25 [744r,768r:0)  0@744r w=6.318158e-03
assigning %vreg25 to %W8: W8 [744r,768r:0)  0@744r

selectOrSplit GPR32:%vreg22 [752r,768r:0)  0@752r w=inf
assigning %vreg22 to %W9: W9 [752r,768r:0)  0@752r

selectOrSplit GPR64common:%vreg44 [848r,864r:0)  0@848r w=inf
assigning %vreg44 to %X8: W8 [848r,864r:0)  0@848r

selectOrSplit GPR32common:%vreg43 [864r,880r:0)  0@864r w=inf
assigning %vreg43 to %W8: W8 [864r,880r:0)  0@864r

selectOrSplit GPR64common:%vreg48 [928r,944r:0)  0@928r w=inf
assigning %vreg48 to %X8: W8 [928r,944r:0)  0@928r

selectOrSplit GPR32:%vreg47 [944r,960r:0)  0@944r w=inf
assigning %vreg47 to %W8: W8 [944r,960r:0)  0@944r

selectOrSplit GPR32:%vreg51 [1152r,1168r:0)  0@1152r w=inf
assigning %vreg51 to %W8: W8 [1152r,1168r:0)  0@1152r

selectOrSplit GPR32:%vreg59 [1312r,1392r:0)  0@1312r w=1.204128e-03
assigning %vreg59 to %W8: W8 [1312r,1392r:0)  0@1312r

selectOrSplit GPR64common:%vreg61 [1376r,1392r:0)  0@1376r w=inf
assigning %vreg61 to %X9: W9 [1376r,1392r:0)  0@1376r

selectOrSplit GPR64common:%vreg58 [1408r,1424r:0)  0@1408r w=inf
assigning %vreg58 to %X8: W8 [1408r,1424r:0)  0@1408r

selectOrSplit GPR32common:%vreg57 [1424r,1440r:0)  0@1424r w=inf
assigning %vreg57 to %W8: W8 [1424r,1440r:0)  0@1424r

selectOrSplit GPR64common:%vreg67 [1488r,1504r:0)  0@1488r w=inf
assigning %vreg67 to %X8: W8 [1488r,1504r:0)  0@1488r

selectOrSplit GPR32:%vreg66 [1504r,1520r:0)  0@1504r w=inf
assigning %vreg66 to %W8: W8 [1504r,1520r:0)  0@1504r

selectOrSplit GPR32:%vreg70 [1712r,1728r:0)  0@1712r w=inf
assigning %vreg70 to %W8: W8 [1712r,1728r:0)  0@1712r

selectOrSplit GPR64common:%vreg77 [1824r,1840r:0)  0@1824r w=inf
assigning %vreg77 to %X8: W8 [1824r,1840r:0)  0@1824r

selectOrSplit GPR32common:%vreg76 [1840r,1856r:0)  0@1840r w=inf
assigning %vreg76 to %W8: W8 [1840r,1856r:0)  0@1840r

selectOrSplit GPR32:%vreg90 [2080r,2096r:0)  0@2080r w=4.454834e-03
assigning %vreg90 to %W8: W8 [2080r,2096r:0)  0@2080r

selectOrSplit GPR32:%vreg92 [2088r,2096r:0)  0@2088r w=inf
assigning %vreg92 to %W9: W9 [2088r,2096r:0)  0@2088r

selectOrSplit GPR32:%vreg84 [2096r,2128r:0)  0@2096r w=inf
assigning %vreg84 to %W8: W8 [2096r,2128r:0)  0@2096r

selectOrSplit GPR64common:%vreg81 [2144r,2160r:0)  0@2144r w=inf
assigning %vreg81 to %X8: W8 [2144r,2160r:0)  0@2144r

selectOrSplit GPR32common:%vreg80 [2160r,2176r:0)  0@2160r w=inf
assigning %vreg80 to %W8: W8 [2160r,2176r:0)  0@2160r

selectOrSplit GPR64common:%vreg99 [2224r,2240r:0)  0@2224r w=inf
assigning %vreg99 to %X8: W8 [2224r,2240r:0)  0@2224r

selectOrSplit GPR32:%vreg98 [2240r,2256r:0)  0@2240r w=inf
assigning %vreg98 to %W8: W8 [2240r,2256r:0)  0@2240r

selectOrSplit GPR64common:%vreg135 [2432r,2448r:0)  0@2432r w=inf
assigning %vreg135 to %X8: W8 [2432r,2448r:0)  0@2432r

selectOrSplit GPR32common:%vreg134 [2448r,2464r:0)  0@2448r w=1.102682e-03
assigning %vreg134 to %W8: W8 [2448r,2464r:0)  0@2448r

selectOrSplit GPR32:%vreg132 [2480r,2496r:0)  0@2480r w=inf
assigning %vreg132 to %W8: W8 [2480r,2496r:0)  0@2480r

selectOrSplit GPR32common:%vreg128 [2496r,2536r:0)  0@2496r w=1.042535e-03
assigning %vreg128 to %W8: W8 [2496r,2536r:0)  0@2496r

selectOrSplit GPR32:%vreg121 [2624r,2704r:0)  0@2624r w=4.778287e-04
assigning %vreg121 to %W8: W8 [2624r,2704r:0)  0@2624r

selectOrSplit GPR64common:%vreg123 [2688r,2704r:0)  0@2688r w=inf
assigning %vreg123 to %X9: W9 [2688r,2704r:0)  0@2688r

selectOrSplit GPR64common:%vreg107 [2752r,2792r:0)  0@2752r w=3.127606e-03
assigning %vreg107 to %X8: W8 [2752r,2792r:0)  0@2752r

selectOrSplit GPR64common:%vreg104 [2784r,2800r:0)  0@2784r w=3.308045e-03
assigning %vreg104 to %X9: W9 [2784r,2800r:0)  0@2784r

selectOrSplit GPR32:%vreg106 [2792r,2816r:0)  0@2792r w=3.245629e-03
assigning %vreg106 to %W8: W8 [2792r,2816r:0)  0@2792r

selectOrSplit GPR32:%vreg103 [2800r,2816r:0)  0@2800r w=inf
assigning %vreg103 to %W9: W9 [2800r,2816r:0)  0@2800r

selectOrSplit GPR32:%vreg114 [2992r,3072r:0)  0@2992r w=7.071865e-04
assigning %vreg114 to %W8: W8 [2992r,3072r:0)  0@2992r

selectOrSplit GPR64common:%vreg116 [3056r,3072r:0)  0@3056r w=inf
assigning %vreg116 to %X9: W9 [3056r,3072r:0)  0@3056r

selectOrSplit GPR64common:%vreg113 [3120r,3136r:0)  0@3120r w=inf
assigning %vreg113 to %X8: W8 [3120r,3136r:0)  0@3120r

selectOrSplit GPR64common:%vreg112 [3136r,3152r:0)  0@3136r w=inf
assigning %vreg112 to %X8: W8 [3136r,3152r:0)  0@3136r

selectOrSplit GPR32:%vreg110 [3152r,3168r:0)  0@3152r w=inf
assigning %vreg110 to %W8: W8 [3152r,3168r:0)  0@3152r

selectOrSplit GPR32:%vreg143 [3376r,3408r:0)  0@3376r w=4.629629e-03
assigning %vreg143 to %W9: W9 [3376r,3408r:0)  0@3376r

selectOrSplit GPR32common:%vreg148 [3440r,3456r:0)  0@3440r w=inf
assigning %vreg148 to %W8: W8 [3440r,3456r:0)  0@3440r

********** STACK TRANSFORMATION METADATA **********
********** Function: handle_compress
********** REGISTER MAP **********
[%vreg3 -> %X20] GPR64
[%vreg6 -> %X8] GPR64
[%vreg9 -> %X8] GPR64common
[%vreg10 -> %X8] GPR64common
[%vreg12 -> %X0] GPR64sp
[%vreg13 -> %X19] GPR64
[%vreg17 -> %W8] GPR32common
[%vreg18 -> %X8] GPR64common
[%vreg22 -> %W9] GPR32
[%vreg23 -> %X9] GPR64common
[%vreg25 -> %W8] GPR32
[%vreg26 -> %X8] GPR64common
[%vreg29 -> %W8] GPR32
[%vreg35 -> %W8] GPR32
[%vreg36 -> %W0] GPR32
[%vreg37 -> %W9] GPR32
[%vreg40 -> %X0] GPR64
[%vreg43 -> %W8] GPR32common
[%vreg44 -> %X8] GPR64common
[%vreg47 -> %W8] GPR32
[%vreg48 -> %X8] GPR64common
[%vreg50 -> %W0] GPR32
[%vreg51 -> %W8] GPR32
[%vreg54 -> %X0] GPR64
[%vreg57 -> %W8] GPR32common
[%vreg58 -> %X8] GPR64common
[%vreg59 -> %W8] GPR32
[%vreg61 -> %X9] GPR64common
[%vreg63 -> %X0] GPR64
[%vreg66 -> %W8] GPR32
[%vreg67 -> %X8] GPR64common
[%vreg69 -> %W0] GPR32
[%vreg70 -> %W8] GPR32
[%vreg73 -> %X0] GPR64
[%vreg76 -> %W8] GPR32common
[%vreg77 -> %X8] GPR64common
[%vreg80 -> %W8] GPR32common
[%vreg81 -> %X8] GPR64common
[%vreg84 -> %W8] GPR32
[%vreg90 -> %W8] GPR32
[%vreg91 -> %W0] GPR32
[%vreg92 -> %W9] GPR32
[%vreg95 -> %X0] GPR64
[%vreg98 -> %W8] GPR32
[%vreg99 -> %X8] GPR64common
[%vreg103 -> %W9] GPR32
[%vreg104 -> %X9] GPR64common
[%vreg106 -> %W8] GPR32
[%vreg107 -> %X8] GPR64common
[%vreg110 -> %W8] GPR32
[%vreg112 -> %X8] GPR64common
[%vreg113 -> %X8] GPR64common
[%vreg114 -> %W8] GPR32
[%vreg116 -> %X9] GPR64common
[%vreg119 -> %W1] GPR32
[%vreg120 -> %X0] GPR64
[%vreg121 -> %W8] GPR32
[%vreg123 -> %X9] GPR64common
[%vreg126 -> %W1] GPR32
[%vreg128 -> %W8] GPR32common
[%vreg132 -> %W8] GPR32
[%vreg134 -> %W8] GPR32common
[%vreg135 -> %X8] GPR64common
[%vreg136 -> %X0] GPR64
[%vreg138 -> %X0] GPR64
[%vreg143 -> %W9] GPR32
[%vreg148 -> %W8] GPR32common
[%vreg150 -> %W20] GPR32sp
[%vreg151 -> %X0] GPR64
[%vreg152 -> %W8] GPR32


Stackmap 0:
  STACKMAP 0, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, %vreg3, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3] LD8[FixedStack0] GPR64:%vreg3

i8* %progress_in: in stack slot 1 (size: 1)
i8* %progress_out: in stack slot 2 (size: 1)
%struct.EState** %s: in stack slot 3 (size: 8)
%struct.bz_stream* %strm: in register %X20 (vreg 3)
%struct.bz_stream** %strm.addr: in stack slot 0 (size: 8)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]

i8* %progress_in: in stack slot 1 (size: 1)
i8* %progress_out: in stack slot 2 (size: 1)
%struct.EState** %s: in stack slot 3 (size: 8)

Duplicate operand locations:


Stackmap 2:
  STACKMAP 2, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]

i8* %progress_in: in stack slot 1 (size: 1)
i8* %progress_out: in stack slot 2 (size: 1)
%struct.EState** %s: in stack slot 3 (size: 8)

Duplicate operand locations:


Stackmap 3:
  STACKMAP 3, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]

i8* %progress_in: in stack slot 1 (size: 1)
i8* %progress_out: in stack slot 2 (size: 1)
%struct.EState** %s: in stack slot 3 (size: 8)

Duplicate operand locations:


Stackmap 4:
  STACKMAP 4, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]

i8* %progress_in: in stack slot 1 (size: 1)
i8* %progress_out: in stack slot 2 (size: 1)
%struct.EState** %s: in stack slot 3 (size: 8)

Duplicate operand locations:


Stackmap 5:
  STACKMAP 5, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]

i8* %progress_in: in stack slot 1 (size: 1)
i8* %progress_out: in stack slot 2 (size: 1)
%struct.EState** %s: in stack slot 3 (size: 8)

Duplicate operand locations:


Stackmap 6:
  STACKMAP 6, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]

i8* %progress_in: in stack slot 1 (size: 1)
i8* %progress_out: in stack slot 2 (size: 1)
%struct.EState** %s: in stack slot 3 (size: 8)

Duplicate operand locations:


Stackmap 7:
  STACKMAP 7, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]

i8* %progress_in: in stack slot 1 (size: 1)
i8* %progress_out: in stack slot 2 (size: 1)
%struct.EState** %s: in stack slot 3 (size: 8)

Duplicate operand locations:


Stackmap 8:
  STACKMAP 8, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]

i8* %progress_in: in stack slot 1 (size: 1)
i8* %progress_out: in stack slot 2 (size: 1)
%struct.EState** %s: in stack slot 3 (size: 8)

Duplicate operand locations:


Stackmap 9:
  STACKMAP 9, 0, %vreg150, %LR<earlyclobber,imp-def,dead>, ...; GPR32sp:%vreg150

i8 %conv70: in register %W20 (vreg 150)

Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, %vreg3, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3] LD8[FixedStack0] GPR64:%vreg3
  -> Call instruction SlotIndex 176B, searching vregs 0 -> 153 and stack slots 0 -> 4
    + vreg13 is live in register but not in stackmap
      Defining instruction: %vreg13<def> = COPY %LR; GPR64:%vreg13
      Value: generated value, 1 instruction(s)

  STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
  -> Call instruction SlotIndex 512B, searching vregs 0 -> 153 and stack slots 0 -> 4
    + vreg13 is live in register but not in stackmap
      Defining instruction: %vreg13<def> = COPY %LR; GPR64:%vreg13
      Value: generated value, 1 instruction(s)

  STACKMAP 2, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
  -> Call instruction SlotIndex 1040B, searching vregs 0 -> 153 and stack slots 0 -> 4
    + vreg13 is live in register but not in stackmap
      Defining instruction: %vreg13<def> = COPY %LR; GPR64:%vreg13
      Value: generated value, 1 instruction(s)

  STACKMAP 3, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
  -> Call instruction SlotIndex 1280B, searching vregs 0 -> 153 and stack slots 0 -> 4
    + vreg13 is live in register but not in stackmap
      Defining instruction: %vreg13<def> = COPY %LR; GPR64:%vreg13
      Value: generated value, 1 instruction(s)

  STACKMAP 4, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
  -> Call instruction SlotIndex 1600B, searching vregs 0 -> 153 and stack slots 0 -> 4
    + vreg13 is live in register but not in stackmap
      Defining instruction: %vreg13<def> = COPY %LR; GPR64:%vreg13
      Value: generated value, 1 instruction(s)

  STACKMAP 5, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
  -> Call instruction SlotIndex 1952B, searching vregs 0 -> 153 and stack slots 0 -> 4
    + vreg13 is live in register but not in stackmap
      Defining instruction: %vreg13<def> = COPY %LR; GPR64:%vreg13
      Value: generated value, 1 instruction(s)

  STACKMAP 6, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
  -> Call instruction SlotIndex 2336B, searching vregs 0 -> 153 and stack slots 0 -> 4
    + vreg13 is live in register but not in stackmap
      Defining instruction: %vreg13<def> = COPY %LR; GPR64:%vreg13
      Value: generated value, 1 instruction(s)

  STACKMAP 7, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
  -> Call instruction SlotIndex 2592B, searching vregs 0 -> 153 and stack slots 0 -> 4
    + vreg13 is live in register but not in stackmap
      Defining instruction: %vreg13<def> = COPY %LR; GPR64:%vreg13
      Value: generated value, 1 instruction(s)

  STACKMAP 8, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
  -> Call instruction SlotIndex 2960B, searching vregs 0 -> 153 and stack slots 0 -> 4
    + vreg13 is live in register but not in stackmap
      Defining instruction: %vreg13<def> = COPY %LR; GPR64:%vreg13
      Value: generated value, 1 instruction(s)

  STACKMAP 9, 0, %vreg150, %LR<earlyclobber,imp-def,dead>, ...; GPR32sp:%vreg150
  -> Call instruction SlotIndex 3632B, searching vregs 0 -> 153 and stack slots 0 -> 4

********** REWRITE VIRTUAL REGISTERS **********
********** Function: handle_compress
********** REGISTER MAP **********
[%vreg3 -> %X20] GPR64
[%vreg6 -> %X8] GPR64
[%vreg9 -> %X8] GPR64common
[%vreg10 -> %X8] GPR64common
[%vreg12 -> %X0] GPR64sp
[%vreg13 -> %X19] GPR64
[%vreg17 -> %W8] GPR32common
[%vreg18 -> %X8] GPR64common
[%vreg22 -> %W9] GPR32
[%vreg23 -> %X9] GPR64common
[%vreg25 -> %W8] GPR32
[%vreg26 -> %X8] GPR64common
[%vreg29 -> %W8] GPR32
[%vreg35 -> %W8] GPR32
[%vreg36 -> %W0] GPR32
[%vreg37 -> %W9] GPR32
[%vreg40 -> %X0] GPR64
[%vreg43 -> %W8] GPR32common
[%vreg44 -> %X8] GPR64common
[%vreg47 -> %W8] GPR32
[%vreg48 -> %X8] GPR64common
[%vreg50 -> %W0] GPR32
[%vreg51 -> %W8] GPR32
[%vreg54 -> %X0] GPR64
[%vreg57 -> %W8] GPR32common
[%vreg58 -> %X8] GPR64common
[%vreg59 -> %W8] GPR32
[%vreg61 -> %X9] GPR64common
[%vreg63 -> %X0] GPR64
[%vreg66 -> %W8] GPR32
[%vreg67 -> %X8] GPR64common
[%vreg69 -> %W0] GPR32
[%vreg70 -> %W8] GPR32
[%vreg73 -> %X0] GPR64
[%vreg76 -> %W8] GPR32common
[%vreg77 -> %X8] GPR64common
[%vreg80 -> %W8] GPR32common
[%vreg81 -> %X8] GPR64common
[%vreg84 -> %W8] GPR32
[%vreg90 -> %W8] GPR32
[%vreg91 -> %W0] GPR32
[%vreg92 -> %W9] GPR32
[%vreg95 -> %X0] GPR64
[%vreg98 -> %W8] GPR32
[%vreg99 -> %X8] GPR64common
[%vreg103 -> %W9] GPR32
[%vreg104 -> %X9] GPR64common
[%vreg106 -> %W8] GPR32
[%vreg107 -> %X8] GPR64common
[%vreg110 -> %W8] GPR32
[%vreg112 -> %X8] GPR64common
[%vreg113 -> %X8] GPR64common
[%vreg114 -> %W8] GPR32
[%vreg116 -> %X9] GPR64common
[%vreg119 -> %W1] GPR32
[%vreg120 -> %X0] GPR64
[%vreg121 -> %W8] GPR32
[%vreg123 -> %X9] GPR64common
[%vreg126 -> %W1] GPR32
[%vreg128 -> %W8] GPR32common
[%vreg132 -> %W8] GPR32
[%vreg134 -> %W8] GPR32common
[%vreg135 -> %X8] GPR64common
[%vreg136 -> %X0] GPR64
[%vreg138 -> %X0] GPR64
[%vreg143 -> %W9] GPR32
[%vreg148 -> %W8] GPR32common
[%vreg150 -> %W20] GPR32sp
[%vreg151 -> %X0] GPR64
[%vreg152 -> %W8] GPR32

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %LR %X0
16B		%vreg13<def> = COPY %LR; GPR64:%vreg13
32B		%vreg3<def> = COPY %X0; GPR64:%vreg3
64B		%vreg10<def> = ADRP <ga:@handle_compress>[TF=1]; GPR64common:%vreg10
80B		%vreg12<def> = ADDXri %vreg10<kill>, <ga:@handle_compress>[TF=34], 0; GPR64sp:%vreg12 GPR64common:%vreg10
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		%X0<def> = COPY %vreg12<kill>; GPR64sp:%vreg12
160B		%X1<def> = COPY %vreg13; GPR64:%vreg13
176B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
224B		STACKMAP 0, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, %vreg3, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3] LD8[FixedStack0] GPR64:%vreg3
240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
256B		STRXui %vreg3<kill>, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg3
272B		STRBBui %WZR, <fi#1>, 0; mem:ST1[FixedStack1]
288B		STRBBui %WZR, <fi#2>, 0; mem:ST1[FixedStack2]
304B		%vreg9<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg9
320B		%vreg6<def> = LDRXui %vreg9<kill>, 6; mem:LD8[%state] GPR64:%vreg6 GPR64common:%vreg9
352B		STRXui %vreg6<kill>, <fi#3>, 0; mem:ST8[FixedStack3] GPR64:%vreg6
	    Successors according to CFG: BB#1
> %X19<def> = COPY %LR
> %X20<def> = COPY %X0
> %X8<def> = ADRP <ga:@handle_compress>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@handle_compress>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19
> BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 0, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, %X20, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3] LD8[FixedStack0]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRXui %X20<kill>, <fi#0>, 0; mem:ST8[FixedStack0]
> STRBBui %WZR, <fi#1>, 0; mem:ST1[FixedStack1]
> STRBBui %WZR, <fi#2>, 0; mem:ST1[FixedStack2]
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %X8<def> = LDRXui %X8<kill>, 6; mem:LD8[%state]
> STRXui %X8<kill>, <fi#3>, 0; mem:ST8[FixedStack3]
368B	BB#1: derived from LLVM BB %while.body
	    Live Ins: %X19
	    Predecessors according to CFG: BB#0 BB#24
384B		%vreg18<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg18
400B		%vreg17<def> = LDRWui %vreg18<kill>, 3; mem:LD4[%state1] GPR32common:%vreg17 GPR64common:%vreg18
416B		%WZR<def> = SUBSWri %vreg17<kill>, 1, 0, %NZCV<imp-def>; GPR32common:%vreg17
432B		Bcc 1, <BB#13>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#13 BB#2
> %X8<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> %W8<def> = LDRWui %X8<kill>, 3; mem:LD4[%state1]
> %WZR<def> = SUBSWri %W8<kill>, 1, 0, %NZCV<imp-def>
> Bcc 1, <BB#13>, %NZCV<imp-use,kill>
448B	BB#2: derived from LLVM BB %if.then
	    Live Ins: %X19
	    Predecessors according to CFG: BB#1
464B		%vreg40<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg40
480B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
496B		%X0<def> = COPY %vreg40<kill>; GPR64:%vreg40
512B		BL <ga:@copy_output_until_stop>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>
528B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
544B		%vreg36<def> = COPY %W0; GPR32:%vreg36
576B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
592B		STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
608B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
640B		%vreg35<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg35
648B		%vreg37<def> = UBFMWri %vreg36<kill>, 0, 7; GPR32:%vreg37,%vreg36
656B		%vreg29<def> = ORRWrr %vreg35<kill>, %vreg37<kill>; GPR32:%vreg29,%vreg35,%vreg37
688B		STRBBui %vreg29<kill>, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg29
704B		%vreg26<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg26
736B		%vreg23<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg23
744B		%vreg25<def> = LDRWui %vreg26<kill>, 30; mem:LD4[%state_out_pos] GPR32:%vreg25 GPR64common:%vreg26
752B		%vreg22<def> = LDRWui %vreg23<kill>, 29; mem:LD4[%numZ] GPR32:%vreg22 GPR64common:%vreg23
768B		%WZR<def> = SUBSWrr %vreg25<kill>, %vreg22<kill>, %NZCV<imp-def>; GPR32:%vreg25,%vreg22
784B		Bcc 10, <BB#4>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#4 BB#3
> %X0<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BL <ga:@copy_output_until_stop>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = COPY %W0
Deleting identity copy.
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W8<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2]
> %W9<def> = UBFMWri %W0<kill>, 0, 7
> %W8<def> = ORRWrr %W8<kill>, %W9<kill>
> STRBBui %W8<kill>, <fi#2>, 0; mem:ST1[FixedStack2]
> %X8<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> %X9<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> %W8<def> = LDRWui %X8<kill>, 30; mem:LD4[%state_out_pos]
> %W9<def> = LDRWui %X9<kill>, 29; mem:LD4[%numZ]
> %WZR<def> = SUBSWrr %W8<kill>, %W9<kill>, %NZCV<imp-def>
> Bcc 10, <BB#4>, %NZCV<imp-use,kill>
800B	BB#3: derived from LLVM BB %if.then.6
	    Live Ins: %X19
	    Predecessors according to CFG: BB#2
816B		B <BB#25>
	    Successors according to CFG: BB#25
> B <BB#25>
832B	BB#4: derived from LLVM BB %if.end
	    Live Ins: %X19
	    Predecessors according to CFG: BB#2
848B		%vreg44<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg44
864B		%vreg43<def> = LDRWui %vreg44<kill>, 2; mem:LD4[%mode] GPR32common:%vreg43 GPR64common:%vreg44
880B		%WZR<def> = SUBSWri %vreg43<kill>, 4, 0, %NZCV<imp-def>; GPR32common:%vreg43
896B		Bcc 1, <BB#8>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#8 BB#5
> %X8<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> %W8<def> = LDRWui %X8<kill>, 2; mem:LD4[%mode]
> %WZR<def> = SUBSWri %W8<kill>, 4, 0, %NZCV<imp-def>
> Bcc 1, <BB#8>, %NZCV<imp-use,kill>
912B	BB#5: derived from LLVM BB %land.lhs.true
	    Live Ins: %X19
	    Predecessors according to CFG: BB#4
928B		%vreg48<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg48
944B		%vreg47<def> = LDRWui %vreg48<kill>, 4; mem:LD4[%avail_in_expect] GPR32:%vreg47 GPR64common:%vreg48
960B		CBNZW %vreg47<kill>, <BB#8>; GPR32:%vreg47
	    Successors according to CFG: BB#8 BB#6
> %X8<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> %W8<def> = LDRWui %X8<kill>, 4; mem:LD4[%avail_in_expect]
> CBNZW %W8<kill>, <BB#8>
976B	BB#6: derived from LLVM BB %land.lhs.true.11
	    Live Ins: %X19
	    Predecessors according to CFG: BB#5
992B		%vreg54<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg54
1008B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1024B		%X0<def> = COPY %vreg54<kill>; GPR64:%vreg54
1040B		BL <ga:@isempty_RL>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>
1056B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1072B		%vreg50<def> = COPY %W0; GPR32:%vreg50
1104B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1120B		STACKMAP 2, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
1136B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1152B		%vreg51<def> = UBFMWri %vreg50<kill>, 0, 7; GPR32:%vreg51,%vreg50
1168B		CBZW %vreg51<kill>, <BB#8>; GPR32:%vreg51
	    Successors according to CFG: BB#8 BB#7
> %X0<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BL <ga:@isempty_RL>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = COPY %W0
Deleting identity copy.
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 2, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W8<def> = UBFMWri %W0<kill>, 0, 7
> CBZW %W8<kill>, <BB#8>
1184B	BB#7: derived from LLVM BB %if.then.14
	    Live Ins: %X19
	    Predecessors according to CFG: BB#6
1200B		B <BB#25>
	    Successors according to CFG: BB#25
> B <BB#25>
1216B	BB#8: derived from LLVM BB %if.end.15
	    Live Ins: %X19
	    Predecessors according to CFG: BB#4 BB#5 BB#6
1232B		%vreg63<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg63
1248B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1264B		%X0<def> = COPY %vreg63<kill>; GPR64:%vreg63
1280B		BL <ga:@prepare_new_block>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>
1296B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1312B		%vreg59<def> = MOVi32imm 2; GPR32:%vreg59
1328B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1344B		STACKMAP 3, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
1360B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1376B		%vreg61<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg61
1392B		STRWui %vreg59<kill>, %vreg61<kill>, 3; mem:ST4[%state16] GPR32:%vreg59 GPR64common:%vreg61
1408B		%vreg58<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg58
1424B		%vreg57<def> = LDRWui %vreg58<kill>, 2; mem:LD4[%mode17] GPR32common:%vreg57 GPR64common:%vreg58
1440B		%WZR<def> = SUBSWri %vreg57<kill>, 3, 0, %NZCV<imp-def>; GPR32common:%vreg57
1456B		Bcc 1, <BB#12>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#12 BB#9
> %X0<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BL <ga:@prepare_new_block>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W8<def> = MOVi32imm 2
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 3, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X9<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> STRWui %W8<kill>, %X9<kill>, 3; mem:ST4[%state16]
> %X8<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> %W8<def> = LDRWui %X8<kill>, 2; mem:LD4[%mode17]
> %WZR<def> = SUBSWri %W8<kill>, 3, 0, %NZCV<imp-def>
> Bcc 1, <BB#12>, %NZCV<imp-use,kill>
1472B	BB#9: derived from LLVM BB %land.lhs.true.20
	    Live Ins: %X19
	    Predecessors according to CFG: BB#8
1488B		%vreg67<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg67
1504B		%vreg66<def> = LDRWui %vreg67<kill>, 4; mem:LD4[%avail_in_expect21] GPR32:%vreg66 GPR64common:%vreg67
1520B		CBNZW %vreg66<kill>, <BB#12>; GPR32:%vreg66
	    Successors according to CFG: BB#12 BB#10
> %X8<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> %W8<def> = LDRWui %X8<kill>, 4; mem:LD4[%avail_in_expect21]
> CBNZW %W8<kill>, <BB#12>
1536B	BB#10: derived from LLVM BB %land.lhs.true.24
	    Live Ins: %X19
	    Predecessors according to CFG: BB#9
1552B		%vreg73<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg73
1568B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1584B		%X0<def> = COPY %vreg73<kill>; GPR64:%vreg73
1600B		BL <ga:@isempty_RL>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>
1616B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1632B		%vreg69<def> = COPY %W0; GPR32:%vreg69
1664B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1680B		STACKMAP 4, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
1696B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1712B		%vreg70<def> = UBFMWri %vreg69<kill>, 0, 7; GPR32:%vreg70,%vreg69
1728B		CBZW %vreg70<kill>, <BB#12>; GPR32:%vreg70
	    Successors according to CFG: BB#12 BB#11
> %X0<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BL <ga:@isempty_RL>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = COPY %W0
Deleting identity copy.
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 4, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W8<def> = UBFMWri %W0<kill>, 0, 7
> CBZW %W8<kill>, <BB#12>
1744B	BB#11: derived from LLVM BB %if.then.28
	    Live Ins: %X19
	    Predecessors according to CFG: BB#10
1760B		B <BB#25>
	    Successors according to CFG: BB#25
> B <BB#25>
1776B	BB#12: derived from LLVM BB %if.end.29
	    Live Ins: %X19
	    Predecessors according to CFG: BB#8 BB#9 BB#10
1792B		B <BB#13>
	    Successors according to CFG: BB#13
> B <BB#13>
1808B	BB#13: derived from LLVM BB %if.end.30
	    Live Ins: %X19
	    Predecessors according to CFG: BB#1 BB#12
1824B		%vreg77<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg77
1840B		%vreg76<def> = LDRWui %vreg77<kill>, 3; mem:LD4[%state31] GPR32common:%vreg76 GPR64common:%vreg77
1856B		%WZR<def> = SUBSWri %vreg76<kill>, 2, 0, %NZCV<imp-def>; GPR32common:%vreg76
1872B		Bcc 1, <BB#24>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#24 BB#14
> %X8<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> %W8<def> = LDRWui %X8<kill>, 3; mem:LD4[%state31]
> %WZR<def> = SUBSWri %W8<kill>, 2, 0, %NZCV<imp-def>
> Bcc 1, <BB#24>, %NZCV<imp-use,kill>
1888B	BB#14: derived from LLVM BB %if.then.34
	    Live Ins: %X19
	    Predecessors according to CFG: BB#13
1904B		%vreg95<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg95
1920B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1936B		%X0<def> = COPY %vreg95<kill>; GPR64:%vreg95
1952B		BL <ga:@copy_input_until_stop>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>
1968B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1984B		%vreg91<def> = COPY %W0; GPR32:%vreg91
2016B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2032B		STACKMAP 5, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
2048B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2080B		%vreg90<def> = LDRBBui <fi#1>, 0; mem:LD1[FixedStack1] GPR32:%vreg90
2088B		%vreg92<def> = UBFMWri %vreg91<kill>, 0, 7; GPR32:%vreg92,%vreg91
2096B		%vreg84<def> = ORRWrr %vreg90<kill>, %vreg92<kill>; GPR32:%vreg84,%vreg90,%vreg92
2128B		STRBBui %vreg84<kill>, <fi#1>, 0; mem:ST1[FixedStack1] GPR32:%vreg84
2144B		%vreg81<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg81
2160B		%vreg80<def> = LDRWui %vreg81<kill>, 2; mem:LD4[%mode40] GPR32common:%vreg80 GPR64common:%vreg81
2176B		%WZR<def> = SUBSWri %vreg80<kill>, 2, 0, %NZCV<imp-def>; GPR32common:%vreg80
2192B		Bcc 0, <BB#17>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#17 BB#15
> %X0<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BL <ga:@copy_input_until_stop>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = COPY %W0
Deleting identity copy.
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 5, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W8<def> = LDRBBui <fi#1>, 0; mem:LD1[FixedStack1]
> %W9<def> = UBFMWri %W0<kill>, 0, 7
> %W8<def> = ORRWrr %W8<kill>, %W9<kill>
> STRBBui %W8<kill>, <fi#1>, 0; mem:ST1[FixedStack1]
> %X8<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> %W8<def> = LDRWui %X8<kill>, 2; mem:LD4[%mode40]
> %WZR<def> = SUBSWri %W8<kill>, 2, 0, %NZCV<imp-def>
> Bcc 0, <BB#17>, %NZCV<imp-use,kill>
2208B	BB#15: derived from LLVM BB %land.lhs.true.43
	    Live Ins: %X19
	    Predecessors according to CFG: BB#14
2224B		%vreg99<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg99
2240B		%vreg98<def> = LDRWui %vreg99<kill>, 4; mem:LD4[%avail_in_expect44] GPR32:%vreg98 GPR64common:%vreg99
2256B		CBNZW %vreg98<kill>, <BB#17>; GPR32:%vreg98
	    Successors according to CFG: BB#17 BB#16
> %X8<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> %W8<def> = LDRWui %X8<kill>, 4; mem:LD4[%avail_in_expect44]
> CBNZW %W8<kill>, <BB#17>
2272B	BB#16: derived from LLVM BB %if.then.47
	    Live Ins: %X19
	    Predecessors according to CFG: BB#15
2288B		%vreg138<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg138
2304B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2320B		%X0<def> = COPY %vreg138<kill>; GPR64:%vreg138
2336B		BL <ga:@flush_RL>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>
2352B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2368B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2384B		STACKMAP 6, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
2400B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2432B		%vreg135<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg135
2448B		%vreg134<def> = LDRWui %vreg135<kill>, 2; mem:LD4[%mode48] GPR32common:%vreg134 GPR64common:%vreg135
2456B		%vreg136<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg136
2464B		%WZR<def> = SUBSWri %vreg134<kill>, 4, 0, %NZCV<imp-def>; GPR32common:%vreg134
2480B		%vreg132<def> = CSINCWr %WZR, %WZR, 1, %NZCV<imp-use,kill>; GPR32:%vreg132
2496B		%vreg128<def> = ANDWri %vreg132<kill>, 0; GPR32common:%vreg128 GPR32:%vreg132
2528B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2536B		%vreg126<def> = UBFMWri %vreg128<kill>, 0, 7; GPR32:%vreg126 GPR32common:%vreg128
2544B		%X0<def> = COPY %vreg136<kill>; GPR64:%vreg136
2576B		%W1<def> = COPY %vreg126<kill>; GPR32:%vreg126
2592B		BL <ga:@BZ2_compressBlock>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>
2608B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2624B		%vreg121<def> = MOVi32imm 1; GPR32:%vreg121
2640B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2656B		STACKMAP 7, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
2672B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2688B		%vreg123<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg123
2704B		STRWui %vreg121<kill>, %vreg123<kill>, 3; mem:ST4[%state52] GPR32:%vreg121 GPR64common:%vreg123
2720B		B <BB#23>
	    Successors according to CFG: BB#23
> %X0<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BL <ga:@flush_RL>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 6, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X8<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> %W8<def> = LDRWui %X8<kill>, 2; mem:LD4[%mode48]
> %X0<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> %WZR<def> = SUBSWri %W8<kill>, 4, 0, %NZCV<imp-def>
> %W8<def> = CSINCWr %WZR, %WZR, 1, %NZCV<imp-use,kill>
> %W8<def> = ANDWri %W8<kill>, 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %W1<def> = UBFMWri %W8<kill>, 0, 7
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %W1<def> = COPY %W1<kill>
Deleting identity copy.
> BL <ga:@BZ2_compressBlock>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W8<def> = MOVi32imm 1
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 7, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X9<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> STRWui %W8<kill>, %X9<kill>, 3; mem:ST4[%state52]
> B <BB#23>
2736B	BB#17: derived from LLVM BB %if.else
	    Live Ins: %X19
	    Predecessors according to CFG: BB#14 BB#15
2752B		%vreg107<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg107
2784B		%vreg104<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg104
2792B		%vreg106<def> = LDRWui %vreg107<kill>, 27; mem:LD4[%nblock] GPR32:%vreg106 GPR64common:%vreg107
2800B		%vreg103<def> = LDRWui %vreg104<kill>, 28; mem:LD4[%nblockMAX] GPR32:%vreg103 GPR64common:%vreg104
2816B		%WZR<def> = SUBSWrr %vreg106<kill>, %vreg103<kill>, %NZCV<imp-def>; GPR32:%vreg106,%vreg103
2832B		Bcc 11, <BB#19>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#19 BB#18
> %X8<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> %X9<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> %W8<def> = LDRWui %X8<kill>, 27; mem:LD4[%nblock]
> %W9<def> = LDRWui %X9<kill>, 28; mem:LD4[%nblockMAX]
> %WZR<def> = SUBSWrr %W8<kill>, %W9<kill>, %NZCV<imp-def>
> Bcc 11, <BB#19>, %NZCV<imp-use,kill>
2848B	BB#18: derived from LLVM BB %if.then.55
	    Live Ins: %X19
	    Predecessors according to CFG: BB#17
2880B		%vreg120<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg120
2896B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2904B		%vreg119<def> = UBFMWri %WZR, 0, 7; GPR32:%vreg119
2912B		%X0<def> = COPY %vreg120<kill>; GPR64:%vreg120
2944B		%W1<def> = COPY %vreg119<kill>; GPR32:%vreg119
2960B		BL <ga:@BZ2_compressBlock>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>
2976B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2992B		%vreg114<def> = MOVi32imm 1; GPR32:%vreg114
3008B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3024B		STACKMAP 8, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
3040B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3056B		%vreg116<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg116
3072B		STRWui %vreg114<kill>, %vreg116<kill>, 3; mem:ST4[%state56] GPR32:%vreg114 GPR64common:%vreg116
3088B		B <BB#22>
	    Successors according to CFG: BB#22
> %X0<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %W1<def> = UBFMWri %WZR, 0, 7
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %W1<def> = COPY %W1<kill>
Deleting identity copy.
> BL <ga:@BZ2_compressBlock>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W8<def> = MOVi32imm 1
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 8, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X9<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> STRWui %W8<kill>, %X9<kill>, 3; mem:ST4[%state56]
> B <BB#22>
3104B	BB#19: derived from LLVM BB %if.else.57
	    Live Ins: %X19
	    Predecessors according to CFG: BB#17
3120B		%vreg113<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg113
3136B		%vreg112<def> = LDRXui %vreg113<kill>, 0; mem:LD8[%strm58] GPR64common:%vreg112,%vreg113
3152B		%vreg110<def> = LDRWui %vreg112<kill>, 2; mem:LD4[%avail_in] GPR32:%vreg110 GPR64common:%vreg112
3168B		CBNZW %vreg110<kill>, <BB#21>; GPR32:%vreg110
	    Successors according to CFG: BB#21 BB#20
> %X8<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> %X8<def> = LDRXui %X8<kill>, 0; mem:LD8[%strm58]
> %W8<def> = LDRWui %X8<kill>, 2; mem:LD4[%avail_in]
> CBNZW %W8<kill>, <BB#21>
3184B	BB#20: derived from LLVM BB %if.then.61
	    Live Ins: %X19
	    Predecessors according to CFG: BB#19
3200B		B <BB#25>
	    Successors according to CFG: BB#25
> B <BB#25>
3216B	BB#21: derived from LLVM BB %if.end.62
	    Live Ins: %X19
	    Predecessors according to CFG: BB#19
3232B		B <BB#22>
	    Successors according to CFG: BB#22
> B <BB#22>
3248B	BB#22: derived from LLVM BB %if.end.63
	    Live Ins: %X19
	    Predecessors according to CFG: BB#21 BB#18
3264B		B <BB#23>
	    Successors according to CFG: BB#23
> B <BB#23>
3280B	BB#23: derived from LLVM BB %if.end.64
	    Live Ins: %X19
	    Predecessors according to CFG: BB#22 BB#16
3296B		B <BB#24>
	    Successors according to CFG: BB#24
> B <BB#24>
3312B	BB#24: derived from LLVM BB %if.end.65
	    Live Ins: %X19
	    Predecessors according to CFG: BB#13 BB#23
3328B		B <BB#1>
	    Successors according to CFG: BB#1
> B <BB#1>
3344B	BB#25: derived from LLVM BB %while.end
	    Live Ins: %X19
	    Predecessors according to CFG: BB#20 BB#11 BB#7 BB#3
3376B		%vreg143<def> = LDRBBui <fi#1>, 0; mem:LD1[FixedStack1] GPR32:%vreg143
3384B		%vreg152<def> = MOVi32imm 1; GPR32:%vreg152
3408B		CBNZW %vreg143<kill>, <BB#27>; GPR32:%vreg143
	    Successors according to CFG: BB#27 BB#26
> %W9<def> = LDRBBui <fi#1>, 0; mem:LD1[FixedStack1]
> %W8<def> = MOVi32imm 1
> CBNZW %W9<kill>, <BB#27>
3424B	BB#26: derived from LLVM BB %lor.rhs
	    Live Ins: %X19
	    Predecessors according to CFG: BB#25
3440B		%vreg148<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32common:%vreg148
3456B		%WZR<def> = SUBSWri %vreg148<kill>, 0, 0, %NZCV<imp-def>; GPR32common:%vreg148
3472B		%vreg152<def> = CSINCWr %WZR, %WZR, 0, %NZCV<imp-use,kill>; GPR32:%vreg152
	    Successors according to CFG: BB#27
> %W8<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2]
> %WZR<def> = SUBSWri %W8<kill>, 0, 0, %NZCV<imp-def>
> %W8<def> = CSINCWr %WZR, %WZR, 0, %NZCV<imp-use,kill>
3504B	BB#27: derived from LLVM BB %lor.end
	    Live Ins: %W8 %X19
	    Predecessors according to CFG: BB#25 BB#26
3536B		%vreg150<def> = ANDWri %vreg152<kill>, 0; GPR32sp:%vreg150 GPR32:%vreg152
3568B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3584B		%vreg151<def> = MOVaddr <ga:@handle_compress>[TF=1], <ga:@handle_compress>[TF=34]; GPR64:%vreg151
3600B		%X0<def> = COPY %vreg151<kill>; GPR64:%vreg151
3616B		%X1<def> = COPY %vreg13<kill>; GPR64:%vreg13
3632B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %SP<imp-def>
3648B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3664B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3680B		STACKMAP 9, 0, %vreg150, %LR<earlyclobber,imp-def,dead>, ...; GPR32sp:%vreg150
3696B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3712B		%W0<def> = COPY %vreg150<kill>; GPR32sp:%vreg150
3728B		RET_ReallyLR %W0<imp-use>
> %W20<def> = ANDWri %W8<kill>, 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = MOVaddr <ga:@handle_compress>[TF=1], <ga:@handle_compress>[TF=34]
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19<kill>
> BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %SP<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 9, 0, %W20, %LR<earlyclobber,imp-def,dead>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = COPY %W20<kill>
> RET_ReallyLR %W0<imp-use>
Computing live-in reg-units in ABI blocks.
0B	BB#0 W0#0 W30#0
Created 2 new intervals.
********** INTERVALS **********
W30 [0B,16r:0)[176r,176d:4)[224e,224d:2)[592r,592d:3)[640e,640d:1)  0@0B-phi 1@640e 2@224e 3@592r 4@176r
W0 [0B,32r:0)[144r,176r:3)[560r,592r:2)[704r,720r:1)  0@0B-phi 1@704r 2@560r 3@144r
%vreg0 [32r,48r:0)  0@32r
%vreg1 [48r,256r:0)  0@48r
%vreg4 [288r,304r:0)  0@288r
%vreg5 [272r,288r:0)  0@272r
%vreg6 [64r,80r:0)  0@64r
%vreg7 [80r,96r:0)  0@80r
%vreg8 [96r,144r:0)  0@96r
%vreg9 [112r,160r:0)  0@112r
%vreg10 [16r,576r:0)  0@16r
%vreg13 [368r,384r:0)  0@368r
%vreg14 [352r,368r:0)  0@352r
%vreg15 [480r,496r:0)  0@480r
%vreg16 [688r,688d:0)  0@688r
%vreg17 [544r,560r:0)  0@544r
%vreg18 [672r,704r:0)  0@672r
RegMasks: 176r 592r
********** MACHINEINSTRS **********
# Machine code for function isempty_RL: Post SSA
Frame Objects:
  fi#0: size=1, align=1, at location [SP]
  fi#1: size=8, align=8, at location [SP]
Function Live Ins: %X0 in %vreg0, %LR in %vreg10

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %LR
16B		%vreg10<def> = COPY %LR; GPR64:%vreg10
32B		%vreg0<def> = COPY %X0; GPR64:%vreg0
48B		%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
64B		%vreg6<def> = ADRP <ga:@isempty_RL>[TF=1]; GPR64common:%vreg6
80B		%vreg7<def> = ADDXri %vreg6, <ga:@isempty_RL>[TF=34], 0; GPR64sp:%vreg7 GPR64common:%vreg6
96B		%vreg8<def> = COPY %vreg7; GPR64all:%vreg8 GPR64sp:%vreg7
112B		%vreg9<def> = COPY %vreg10; GPR64all:%vreg9 GPR64:%vreg10
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		%X0<def> = COPY %vreg8; GPR64all:%vreg8
160B		%X1<def> = COPY %vreg9; GPR64all:%vreg9
176B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
224B		STACKMAP 0, 0, 0, <fi#0>, 0, %vreg1, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=1) LD8[FixedStack1] GPR64:%vreg1
240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
256B		STRXui %vreg1, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg1
272B		%vreg5<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg5
288B		%vreg4<def> = LDRWui %vreg5, 23; mem:LD4[%state_in_ch] GPR32common:%vreg4 GPR64common:%vreg5
304B		%WZR<def> = SUBSWri %vreg4, 256, 0, %NZCV<imp-def>; GPR32common:%vreg4
320B		Bcc 2, <BB#3>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#3 BB#1

336B	BB#1: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#0
352B		%vreg14<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg14
368B		%vreg13<def> = LDRWui %vreg14, 24; mem:LD4[%state_in_len] GPR32common:%vreg13 GPR64common:%vreg14
384B		%WZR<def> = SUBSWri %vreg13, 0, 0, %NZCV<imp-def>; GPR32common:%vreg13
400B		Bcc 13, <BB#3>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#3 BB#2

416B	BB#2: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#1
432B		STRBBui %WZR, <fi#0>, 0; mem:ST1[FixedStack0]
448B		B <BB#4>
	    Successors according to CFG: BB#4

464B	BB#3: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#0 BB#1
480B		%vreg15<def> = MOVi32imm 1; GPR32:%vreg15
496B		STRBBui %vreg15, <fi#0>, 0; mem:ST1[FixedStack0] GPR32:%vreg15
	    Successors according to CFG: BB#4

512B	BB#4: derived from LLVM BB %return
	    Predecessors according to CFG: BB#3 BB#2
528B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
544B		%vreg17<def> = MOVaddr <ga:@isempty_RL>[TF=1], <ga:@isempty_RL>[TF=34]; GPR64:%vreg17
560B		%X0<def> = COPY %vreg17; GPR64:%vreg17
576B		%X1<def> = COPY %vreg10; GPR64:%vreg10
592B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %SP<imp-def>
608B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
624B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
640B		STACKMAP 1, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=1)
656B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
672B		%vreg18<def> = LDRBBui <fi#0>, 0; mem:LD1[%retval] GPR32:%vreg18
688B		%vreg16<def,dead> = COPY %vreg18; GPR32all:%vreg16 GPR32:%vreg18
704B		%W0<def> = COPY %vreg18; GPR32:%vreg18
720B		RET_ReallyLR %W0<imp-use>

# End machine code for function isempty_RL.

********** SIMPLE REGISTER COALESCING **********
********** Function: isempty_RL
********** JOINING INTERVALS ***********
land.lhs.true:
if.else:
entry:
16B	%vreg10<def> = COPY %LR; GPR64:%vreg10
	Considering merging %vreg10 with %LR
	Can only merge into reserved registers.
32B	%vreg0<def> = COPY %X0; GPR64:%vreg0
	Considering merging %vreg0 with %X0
	Can only merge into reserved registers.
144B	%X0<def> = COPY %vreg8; GPR64all:%vreg8
	Considering merging %vreg8 with %X0
	Can only merge into reserved registers.
160B	%X1<def> = COPY %vreg9; GPR64all:%vreg9
	Considering merging %vreg9 with %X1
	Can only merge into reserved registers.
if.then:
return:
560B	%X0<def> = COPY %vreg17; GPR64:%vreg17
	Considering merging %vreg17 with %X0
	Can only merge into reserved registers.
576B	%X1<def> = COPY %vreg10; GPR64:%vreg10
	Considering merging %vreg10 with %X1
	Can only merge into reserved registers.
704B	%W0<def> = COPY %vreg18; GPR32:%vreg18
	Considering merging %vreg18 with %W0
	Can only merge into reserved registers.
48B	%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
	Considering merging to GPR64 with %vreg0 in %vreg1
		RHS = %vreg0 [32r,48r:0)  0@32r
		LHS = %vreg1 [48r,256r:0)  0@48r
		merge %vreg1:0@48r into %vreg0:0@32r --> @32r
		erased:	48r	%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
		updated: 32B	%vreg1<def> = COPY %X0; GPR64:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [32r,256r:0)  0@32r
96B	%vreg8<def> = COPY %vreg7; GPR64all:%vreg8 GPR64sp:%vreg7
	Considering merging to GPR64sp with %vreg7 in %vreg8
		RHS = %vreg7 [80r,96r:0)  0@80r
		LHS = %vreg8 [96r,144r:0)  0@96r
		merge %vreg8:0@96r into %vreg7:0@80r --> @80r
		erased:	96r	%vreg8<def> = COPY %vreg7; GPR64all:%vreg8 GPR64sp:%vreg7
		updated: 80B	%vreg8<def> = ADDXri %vreg6, <ga:@isempty_RL>[TF=34], 0; GPR64sp:%vreg8 GPR64common:%vreg6
	Success: %vreg7 -> %vreg8
	Result = %vreg8 [80r,144r:0)  0@80r
112B	%vreg9<def> = COPY %vreg10; GPR64all:%vreg9 GPR64:%vreg10
	Considering merging to GPR64 with %vreg10 in %vreg9
		RHS = %vreg10 [16r,576r:0)  0@16r
		LHS = %vreg9 [112r,160r:0)  0@112r
		merge %vreg9:0@112r into %vreg10:0@16r --> @16r
		erased:	112r	%vreg9<def> = COPY %vreg10; GPR64all:%vreg9 GPR64:%vreg10
		updated: 16B	%vreg9<def> = COPY %LR; GPR64:%vreg9
		updated: 576B	%X1<def> = COPY %vreg9; GPR64:%vreg9
	Success: %vreg10 -> %vreg9
	Result = %vreg9 [16r,576r:0)  0@16r
688B	%vreg16<def,dead> = COPY %vreg18; GPR32all:%vreg16 GPR32:%vreg18
	Copy is dead.
Deleting dead def 688r	%vreg16<def,dead> = COPY %vreg18; GPR32all:%vreg16 GPR32:%vreg18
Shrink: %vreg18 [672r,704r:0)  0@672r
Shrunk: %vreg18 [672r,704r:0)  0@672r
144B	%X0<def> = COPY %vreg8; GPR64sp:%vreg8
	Considering merging %vreg8 with %X0
	Can only merge into reserved registers.
160B	%X1<def> = COPY %vreg9; GPR64:%vreg9
	Considering merging %vreg9 with %X1
	Can only merge into reserved registers.
576B	%X1<def> = COPY %vreg9; GPR64:%vreg9
	Considering merging %vreg9 with %X1
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
W30 [0B,16r:0)[176r,176d:4)[224e,224d:2)[592r,592d:3)[640e,640d:1)  0@0B-phi 1@640e 2@224e 3@592r 4@176r
W0 [0B,32r:0)[144r,176r:3)[560r,592r:2)[704r,720r:1)  0@0B-phi 1@704r 2@560r 3@144r
%vreg1 [32r,256r:0)  0@32r
%vreg4 [288r,304r:0)  0@288r
%vreg5 [272r,288r:0)  0@272r
%vreg6 [64r,80r:0)  0@64r
%vreg8 [80r,144r:0)  0@80r
%vreg9 [16r,576r:0)  0@16r
%vreg13 [368r,384r:0)  0@368r
%vreg14 [352r,368r:0)  0@352r
%vreg15 [480r,496r:0)  0@480r
%vreg17 [544r,560r:0)  0@544r
%vreg18 [672r,704r:0)  0@672r
RegMasks: 176r 592r
********** MACHINEINSTRS **********
# Machine code for function isempty_RL: Post SSA
Frame Objects:
  fi#0: size=1, align=1, at location [SP]
  fi#1: size=8, align=8, at location [SP]
Function Live Ins: %X0 in %vreg0, %LR in %vreg10

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %LR
16B		%vreg9<def> = COPY %LR; GPR64:%vreg9
32B		%vreg1<def> = COPY %X0; GPR64:%vreg1
64B		%vreg6<def> = ADRP <ga:@isempty_RL>[TF=1]; GPR64common:%vreg6
80B		%vreg8<def> = ADDXri %vreg6, <ga:@isempty_RL>[TF=34], 0; GPR64sp:%vreg8 GPR64common:%vreg6
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		%X0<def> = COPY %vreg8; GPR64sp:%vreg8
160B		%X1<def> = COPY %vreg9; GPR64:%vreg9
176B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
224B		STACKMAP 0, 0, 0, <fi#0>, 0, %vreg1, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=1) LD8[FixedStack1] GPR64:%vreg1
240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
256B		STRXui %vreg1, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg1
272B		%vreg5<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg5
288B		%vreg4<def> = LDRWui %vreg5, 23; mem:LD4[%state_in_ch] GPR32common:%vreg4 GPR64common:%vreg5
304B		%WZR<def> = SUBSWri %vreg4, 256, 0, %NZCV<imp-def>; GPR32common:%vreg4
320B		Bcc 2, <BB#3>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#3 BB#1

336B	BB#1: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#0
352B		%vreg14<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg14
368B		%vreg13<def> = LDRWui %vreg14, 24; mem:LD4[%state_in_len] GPR32common:%vreg13 GPR64common:%vreg14
384B		%WZR<def> = SUBSWri %vreg13, 0, 0, %NZCV<imp-def>; GPR32common:%vreg13
400B		Bcc 13, <BB#3>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#3 BB#2

416B	BB#2: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#1
432B		STRBBui %WZR, <fi#0>, 0; mem:ST1[FixedStack0]
448B		B <BB#4>
	    Successors according to CFG: BB#4

464B	BB#3: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#0 BB#1
480B		%vreg15<def> = MOVi32imm 1; GPR32:%vreg15
496B		STRBBui %vreg15, <fi#0>, 0; mem:ST1[FixedStack0] GPR32:%vreg15
	    Successors according to CFG: BB#4

512B	BB#4: derived from LLVM BB %return
	    Predecessors according to CFG: BB#3 BB#2
528B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
544B		%vreg17<def> = MOVaddr <ga:@isempty_RL>[TF=1], <ga:@isempty_RL>[TF=34]; GPR64:%vreg17
560B		%X0<def> = COPY %vreg17; GPR64:%vreg17
576B		%X1<def> = COPY %vreg9; GPR64:%vreg9
592B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %SP<imp-def>
608B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
624B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
640B		STACKMAP 1, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=1)
656B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
672B		%vreg18<def> = LDRBBui <fi#0>, 0; mem:LD1[%retval] GPR32:%vreg18
704B		%W0<def> = COPY %vreg18; GPR32:%vreg18
720B		RET_ReallyLR %W0<imp-use>

# End machine code for function isempty_RL.

********** GREEDY REGISTER ALLOCATION **********
********** Function: isempty_RL
********** INTERVALS **********
W30 [0B,16r:0)[176r,176d:4)[224e,224d:2)[592r,592d:3)[640e,640d:1)  0@0B-phi 1@640e 2@224e 3@592r 4@176r
W0 [0B,32r:0)[144r,176r:3)[560r,592r:2)[704r,720r:1)  0@0B-phi 1@704r 2@560r 3@144r
%vreg1 [32r,256r:0)  0@32r
%vreg4 [288r,304r:0)  0@288r
%vreg5 [272r,288r:0)  0@272r
%vreg6 [64r,80r:0)  0@64r
%vreg8 [80r,144r:0)  0@80r
%vreg9 [16r,576r:0)  0@16r
%vreg13 [368r,384r:0)  0@368r
%vreg14 [352r,368r:0)  0@352r
%vreg15 [480r,496r:0)  0@480r
%vreg17 [544r,560r:0)  0@544r
%vreg18 [672r,704r:0)  0@672r
RegMasks: 176r 592r
********** MACHINEINSTRS **********
# Machine code for function isempty_RL: Post SSA
Frame Objects:
  fi#0: size=1, align=1, at location [SP]
  fi#1: size=8, align=8, at location [SP]
Function Live Ins: %X0 in %vreg0, %LR in %vreg10

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %LR
16B		%vreg9<def> = COPY %LR; GPR64:%vreg9
32B		%vreg1<def> = COPY %X0; GPR64:%vreg1
64B		%vreg6<def> = ADRP <ga:@isempty_RL>[TF=1]; GPR64common:%vreg6
80B		%vreg8<def> = ADDXri %vreg6, <ga:@isempty_RL>[TF=34], 0; GPR64sp:%vreg8 GPR64common:%vreg6
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		%X0<def> = COPY %vreg8; GPR64sp:%vreg8
160B		%X1<def> = COPY %vreg9; GPR64:%vreg9
176B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
224B		STACKMAP 0, 0, 0, <fi#0>, 0, %vreg1, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=1) LD8[FixedStack1] GPR64:%vreg1
240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
256B		STRXui %vreg1, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg1
272B		%vreg5<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg5
288B		%vreg4<def> = LDRWui %vreg5, 23; mem:LD4[%state_in_ch] GPR32common:%vreg4 GPR64common:%vreg5
304B		%WZR<def> = SUBSWri %vreg4, 256, 0, %NZCV<imp-def>; GPR32common:%vreg4
320B		Bcc 2, <BB#3>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#3 BB#1

336B	BB#1: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#0
352B		%vreg14<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg14
368B		%vreg13<def> = LDRWui %vreg14, 24; mem:LD4[%state_in_len] GPR32common:%vreg13 GPR64common:%vreg14
384B		%WZR<def> = SUBSWri %vreg13, 0, 0, %NZCV<imp-def>; GPR32common:%vreg13
400B		Bcc 13, <BB#3>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#3 BB#2

416B	BB#2: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#1
432B		STRBBui %WZR, <fi#0>, 0; mem:ST1[FixedStack0]
448B		B <BB#4>
	    Successors according to CFG: BB#4

464B	BB#3: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#0 BB#1
480B		%vreg15<def> = MOVi32imm 1; GPR32:%vreg15
496B		STRBBui %vreg15, <fi#0>, 0; mem:ST1[FixedStack0] GPR32:%vreg15
	    Successors according to CFG: BB#4

512B	BB#4: derived from LLVM BB %return
	    Predecessors according to CFG: BB#3 BB#2
528B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
544B		%vreg17<def> = MOVaddr <ga:@isempty_RL>[TF=1], <ga:@isempty_RL>[TF=34]; GPR64:%vreg17
560B		%X0<def> = COPY %vreg17; GPR64:%vreg17
576B		%X1<def> = COPY %vreg9; GPR64:%vreg9
592B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %SP<imp-def>
608B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
624B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
640B		STACKMAP 1, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=1)
656B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
672B		%vreg18<def> = LDRBBui <fi#0>, 0; mem:LD1[%retval] GPR32:%vreg18
704B		%W0<def> = COPY %vreg18; GPR32:%vreg18
720B		RET_ReallyLR %W0<imp-use>

# End machine code for function isempty_RL.


selectOrSplit GPR64:%vreg9 [16r,576r:0)  0@16r w=3.156250e-03
hints: %X1
missed hint %X1
assigning %vreg9 to %X19: W19 [16r,576r:0)  0@16r

selectOrSplit GPR64:%vreg1 [32r,256r:0)  0@32r w=4.855769e-03
hints: %X0
missed hint %X0
assigning %vreg1 to %X20: W20 [32r,256r:0)  0@32r

selectOrSplit GPR64sp:%vreg8 [80r,144r:0)  0@80r w=4.353448e-03
hints: %X0
assigning %vreg8 to %X0: W0 [80r,144r:0)  0@80r

selectOrSplit GPR64:%vreg17 [544r,560r:0)  0@544r w=inf
hints: %X0
assigning %vreg17 to %X0: W0 [544r,560r:0)  0@544r

selectOrSplit GPR32:%vreg18 [672r,704r:0)  0@672r w=inf
hints: %W0
assigning %vreg18 to %W0: W0 [672r,704r:0)  0@672r

selectOrSplit GPR64common:%vreg6 [64r,80r:0)  0@64r w=inf
assigning %vreg6 to %X8: W8 [64r,80r:0)  0@64r

selectOrSplit GPR64common:%vreg5 [272r,288r:0)  0@272r w=inf
assigning %vreg5 to %X8: W8 [272r,288r:0)  0@272r

selectOrSplit GPR32common:%vreg4 [288r,304r:0)  0@288r w=inf
assigning %vreg4 to %W8: W8 [288r,304r:0)  0@288r

selectOrSplit GPR64common:%vreg14 [352r,368r:0)  0@352r w=inf
assigning %vreg14 to %X8: W8 [352r,368r:0)  0@352r

selectOrSplit GPR32common:%vreg13 [368r,384r:0)  0@368r w=inf
assigning %vreg13 to %W8: W8 [368r,384r:0)  0@368r

selectOrSplit GPR32:%vreg15 [480r,496r:0)  0@480r w=inf
assigning %vreg15 to %W8: W8 [480r,496r:0)  0@480r

********** STACK TRANSFORMATION METADATA **********
********** Function: isempty_RL
********** REGISTER MAP **********
[%vreg1 -> %X20] GPR64
[%vreg4 -> %W8] GPR32common
[%vreg5 -> %X8] GPR64common
[%vreg6 -> %X8] GPR64common
[%vreg8 -> %X0] GPR64sp
[%vreg9 -> %X19] GPR64
[%vreg13 -> %W8] GPR32common
[%vreg14 -> %X8] GPR64common
[%vreg15 -> %W8] GPR32
[%vreg17 -> %X0] GPR64
[%vreg18 -> %W0] GPR32


Stackmap 0:
  STACKMAP 0, 0, 0, <fi#0>, 0, %vreg1, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=1) LD8[FixedStack1] GPR64:%vreg1

i8* %retval: in stack slot 0 (size: 1)
%struct.EState* %s: in register %X20 (vreg 1)
%struct.EState** %s.addr: in stack slot 1 (size: 8)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=1)

i8* %retval: in stack slot 0 (size: 1)

Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, 0, <fi#0>, 0, %vreg1, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=1) LD8[FixedStack1] GPR64:%vreg1
  -> Call instruction SlotIndex 176B, searching vregs 0 -> 19 and stack slots 0 -> 2
    + vreg9 is live in register but not in stackmap
      Defining instruction: %vreg9<def> = COPY %LR; GPR64:%vreg9
      Value: generated value, 1 instruction(s)

  STACKMAP 1, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=1)
  -> Call instruction SlotIndex 592B, searching vregs 0 -> 19 and stack slots 0 -> 2

********** REWRITE VIRTUAL REGISTERS **********
********** Function: isempty_RL
********** REGISTER MAP **********
[%vreg1 -> %X20] GPR64
[%vreg4 -> %W8] GPR32common
[%vreg5 -> %X8] GPR64common
[%vreg6 -> %X8] GPR64common
[%vreg8 -> %X0] GPR64sp
[%vreg9 -> %X19] GPR64
[%vreg13 -> %W8] GPR32common
[%vreg14 -> %X8] GPR64common
[%vreg15 -> %W8] GPR32
[%vreg17 -> %X0] GPR64
[%vreg18 -> %W0] GPR32

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %LR %X0
16B		%vreg9<def> = COPY %LR; GPR64:%vreg9
32B		%vreg1<def> = COPY %X0; GPR64:%vreg1
64B		%vreg6<def> = ADRP <ga:@isempty_RL>[TF=1]; GPR64common:%vreg6
80B		%vreg8<def> = ADDXri %vreg6<kill>, <ga:@isempty_RL>[TF=34], 0; GPR64sp:%vreg8 GPR64common:%vreg6
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		%X0<def> = COPY %vreg8<kill>; GPR64sp:%vreg8
160B		%X1<def> = COPY %vreg9; GPR64:%vreg9
176B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
224B		STACKMAP 0, 0, 0, <fi#0>, 0, %vreg1, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=1) LD8[FixedStack1] GPR64:%vreg1
240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
256B		STRXui %vreg1<kill>, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg1
272B		%vreg5<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg5
288B		%vreg4<def> = LDRWui %vreg5<kill>, 23; mem:LD4[%state_in_ch] GPR32common:%vreg4 GPR64common:%vreg5
304B		%WZR<def> = SUBSWri %vreg4<kill>, 256, 0, %NZCV<imp-def>; GPR32common:%vreg4
320B		Bcc 2, <BB#3>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#3 BB#1
> %X19<def> = COPY %LR
> %X20<def> = COPY %X0
> %X8<def> = ADRP <ga:@isempty_RL>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@isempty_RL>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19
> BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 0, 0, 0, <fi#0>, 0, %X20, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=1) LD8[FixedStack1]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRXui %X20<kill>, <fi#1>, 0; mem:ST8[FixedStack1]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W8<def> = LDRWui %X8<kill>, 23; mem:LD4[%state_in_ch]
> %WZR<def> = SUBSWri %W8<kill>, 256, 0, %NZCV<imp-def>
> Bcc 2, <BB#3>, %NZCV<imp-use,kill>
336B	BB#1: derived from LLVM BB %land.lhs.true
	    Live Ins: %X19
	    Predecessors according to CFG: BB#0
352B		%vreg14<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg14
368B		%vreg13<def> = LDRWui %vreg14<kill>, 24; mem:LD4[%state_in_len] GPR32common:%vreg13 GPR64common:%vreg14
384B		%WZR<def> = SUBSWri %vreg13<kill>, 0, 0, %NZCV<imp-def>; GPR32common:%vreg13
400B		Bcc 13, <BB#3>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#3 BB#2
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W8<def> = LDRWui %X8<kill>, 24; mem:LD4[%state_in_len]
> %WZR<def> = SUBSWri %W8<kill>, 0, 0, %NZCV<imp-def>
> Bcc 13, <BB#3>, %NZCV<imp-use,kill>
416B	BB#2: derived from LLVM BB %if.then
	    Live Ins: %X19
	    Predecessors according to CFG: BB#1
432B		STRBBui %WZR, <fi#0>, 0; mem:ST1[FixedStack0]
448B		B <BB#4>
	    Successors according to CFG: BB#4
> STRBBui %WZR, <fi#0>, 0; mem:ST1[FixedStack0]
> B <BB#4>
464B	BB#3: derived from LLVM BB %if.else
	    Live Ins: %X19
	    Predecessors according to CFG: BB#0 BB#1
480B		%vreg15<def> = MOVi32imm 1; GPR32:%vreg15
496B		STRBBui %vreg15<kill>, <fi#0>, 0; mem:ST1[FixedStack0] GPR32:%vreg15
	    Successors according to CFG: BB#4
> %W8<def> = MOVi32imm 1
> STRBBui %W8<kill>, <fi#0>, 0; mem:ST1[FixedStack0]
512B	BB#4: derived from LLVM BB %return
	    Live Ins: %X19
	    Predecessors according to CFG: BB#3 BB#2
528B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
544B		%vreg17<def> = MOVaddr <ga:@isempty_RL>[TF=1], <ga:@isempty_RL>[TF=34]; GPR64:%vreg17
560B		%X0<def> = COPY %vreg17<kill>; GPR64:%vreg17
576B		%X1<def> = COPY %vreg9<kill>; GPR64:%vreg9
592B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %SP<imp-def>
608B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
624B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
640B		STACKMAP 1, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=1)
656B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
672B		%vreg18<def> = LDRBBui <fi#0>, 0; mem:LD1[%retval] GPR32:%vreg18
704B		%W0<def> = COPY %vreg18<kill>; GPR32:%vreg18
720B		RET_ReallyLR %W0<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = MOVaddr <ga:@isempty_RL>[TF=1], <ga:@isempty_RL>[TF=34]
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19<kill>
> BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %SP<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 1, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=1)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = LDRBBui <fi#0>, 0; mem:LD1[%retval]
> %W0<def> = COPY %W0<kill>
Deleting identity copy.
> RET_ReallyLR %W0<imp-use>
Computing live-in reg-units in ABI blocks.
0B	BB#0 W0#0 W30#0
Created 2 new intervals.
********** INTERVALS **********
W30 [0B,16r:0)[176r,176d:12)[224e,224d:6)[944r,944d:11)[992e,992d:5)[1264r,1264d:10)[1312e,1312d:4)[1584r,1584d:9)[1632e,1632d:3)[1824r,1824d:8)[1888e,1888d:2)[2096r,2096d:7)[2144e,2144d:1)  0@0B-phi 1@2144e 2@1888e 3@1632e 4@1312e 5@992e 6@224e 7@2096r 8@1824r 9@1584r 10@1264r 11@944r 12@176r
W0 [0B,32r:0)[144r,176r:7)[912r,944r:6)[1232r,1264r:5)[1552r,1584r:4)[1792r,1824r:3)[2064r,2096r:2)[2192r,2208r:1)  0@0B-phi 1@2192r 2@2064r 3@1792r 4@1552r 5@1232r 6@912r 7@144r
%vreg0 [32r,48r:0)  0@32r
%vreg1 [48r,256r:0)  0@48r
%vreg3 [272r,288r:0)  0@272r
%vreg4 [64r,80r:0)  0@64r
%vreg5 [80r,96r:0)  0@80r
%vreg6 [96r,144r:0)  0@96r
%vreg7 [112r,160r:0)  0@112r
%vreg8 [16r,2032r:0)  0@16r
%vreg10 [448r,464r:0)  0@448r
%vreg13 [416r,432r:0)  0@416r
%vreg15 [400r,416r:0)  0@400r
%vreg16 [384r,400r:0)  0@384r
%vreg19 [592r,608r:0)  0@592r
%vreg21 [576r,608r:0)  0@576r
%vreg22 [560r,576r:0)  0@560r
%vreg25 [736r,752r:0)  0@736r
%vreg26 [720r,736r:0)  0@720r
%vreg31 [880r,928r:0)  0@880r
%vreg33 [864r,880r:0)  0@864r
%vreg34 [848r,864r:0)  0@848r
%vreg36 [832r,912r:0)  0@832r
%vreg37 [816r,832r:0)  0@816r
%vreg39 [800r,944r:0)  0@800r
%vreg40 [784r,800r:0)  0@784r
%vreg43 [1056r,1072r:0)  0@1056r
%vreg44 [1040r,1056r:0)  0@1040r
%vreg49 [1200r,1248r:0)  0@1200r
%vreg51 [1184r,1200r:0)  0@1184r
%vreg52 [1168r,1184r:0)  0@1168r
%vreg54 [1152r,1232r:0)  0@1152r
%vreg55 [1136r,1152r:0)  0@1136r
%vreg57 [1120r,1264r:0)  0@1120r
%vreg58 [1104r,1120r:0)  0@1104r
%vreg61 [1376r,1392r:0)  0@1376r
%vreg62 [1360r,1376r:0)  0@1360r
%vreg67 [1520r,1568r:0)  0@1520r
%vreg69 [1504r,1520r:0)  0@1504r
%vreg70 [1488r,1504r:0)  0@1488r
%vreg72 [1472r,1552r:0)  0@1472r
%vreg73 [1456r,1472r:0)  0@1456r
%vreg75 [1440r,1584r:0)  0@1440r
%vreg76 [1424r,1440r:0)  0@1424r
%vreg77 [1856r,1936r:0)  0@1856r
%vreg79 [1920r,1936r:0)  0@1920r
%vreg84 [1760r,1808r:0)  0@1760r
%vreg85 [1744r,1760r:0)  0@1744r
%vreg87 [1728r,1792r:0)  0@1728r
%vreg88 [1712r,1728r:0)  0@1712r
%vreg90 [1696r,1824r:0)  0@1696r
%vreg91 [1680r,1696r:0)  0@1680r
%vreg92 [656r,672r:0)  0@656r
%vreg93 [496r,512r:0)  0@496r
%vreg94 [320r,336r:0)  0@320r
%vreg96 [2176r,2192r:0)  0@2176r
%vreg97 [1984r,2000r:0)  0@1984r
%vreg98 [2000r,2016r:0)  0@2000r
%vreg99 [2016r,2064r:0)  0@2016r
%vreg100 [2032r,2080r:0)  0@2032r
RegMasks: 176r 944r 1264r 1584r 1824r 2096r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzCompressEnd: Post SSA
Frame Objects:
  fi#0: size=4, align=4, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=8, align=8, at location [SP]
Function Live Ins: %X0 in %vreg0, %LR in %vreg8

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %LR
16B		%vreg8<def> = COPY %LR; GPR64:%vreg8
32B		%vreg0<def> = COPY %X0; GPR64:%vreg0
48B		%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
64B		%vreg4<def> = ADRP <ga:@BZ2_bzCompressEnd>[TF=1]; GPR64common:%vreg4
80B		%vreg5<def> = ADDXri %vreg4, <ga:@BZ2_bzCompressEnd>[TF=34], 0; GPR64sp:%vreg5 GPR64common:%vreg4
96B		%vreg6<def> = COPY %vreg5; GPR64all:%vreg6 GPR64sp:%vreg5
112B		%vreg7<def> = COPY %vreg8; GPR64all:%vreg7 GPR64:%vreg8
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		%X0<def> = COPY %vreg6; GPR64all:%vreg6
160B		%X1<def> = COPY %vreg7; GPR64all:%vreg7
176B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
224B		STACKMAP 0, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, %vreg1, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1] GPR64:%vreg1
240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
256B		STRXui %vreg1, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg1
272B		%vreg3<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg3
288B		CBNZX %vreg3, <BB#2>; GPR64:%vreg3
	    Successors according to CFG: BB#2 BB#1

304B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
320B		%vreg94<def> = MOVi32imm 4294967294; GPR32:%vreg94
336B		STRWui %vreg94, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg94
352B		B <BB#13>
	    Successors according to CFG: BB#13

368B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0
384B		%vreg16<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg16
400B		%vreg15<def> = LDRXui %vreg16, 6; mem:LD8[%state] GPR64:%vreg15 GPR64common:%vreg16
416B		%vreg13<def> = COPY %vreg15; GPR64:%vreg13,%vreg15
432B		STRXui %vreg13, <fi#2>, 0; mem:ST8[FixedStack2] GPR64:%vreg13
448B		%vreg10<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg10
464B		CBNZX %vreg10, <BB#4>; GPR64:%vreg10
	    Successors according to CFG: BB#4 BB#3

480B	BB#3: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#2
496B		%vreg93<def> = MOVi32imm 4294967294; GPR32:%vreg93
512B		STRWui %vreg93, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg93
528B		B <BB#13>
	    Successors according to CFG: BB#13

544B	BB#4: derived from LLVM BB %if.end.3
	    Predecessors according to CFG: BB#2
560B		%vreg22<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg22
576B		%vreg21<def> = LDRXui %vreg22, 0; mem:LD8[%strm4] GPR64:%vreg21 GPR64common:%vreg22
592B		%vreg19<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg19
608B		%XZR<def> = SUBSXrr %vreg21, %vreg19, %NZCV<imp-def>; GPR64:%vreg21,%vreg19
624B		Bcc 0, <BB#6>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#6 BB#5

640B	BB#5: derived from LLVM BB %if.then.6
	    Predecessors according to CFG: BB#4
656B		%vreg92<def> = MOVi32imm 4294967294; GPR32:%vreg92
672B		STRWui %vreg92, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg92
688B		B <BB#13>
	    Successors according to CFG: BB#13

704B	BB#6: derived from LLVM BB %if.end.7
	    Predecessors according to CFG: BB#4
720B		%vreg26<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg26
736B		%vreg25<def> = LDRXui %vreg26, 3; mem:LD8[%arr1] GPR64:%vreg25 GPR64common:%vreg26
752B		CBZX %vreg25, <BB#8>; GPR64:%vreg25
	    Successors according to CFG: BB#8 BB#7

768B	BB#7: derived from LLVM BB %if.then.9
	    Predecessors according to CFG: BB#6
784B		%vreg40<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg40
800B		%vreg39<def> = LDRXui %vreg40, 8; mem:LD8[%bzfree] GPR64:%vreg39 GPR64common:%vreg40
816B		%vreg37<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg37
832B		%vreg36<def> = LDRXui %vreg37, 9; mem:LD8[%opaque] GPR64:%vreg36 GPR64common:%vreg37
848B		%vreg34<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg34
864B		%vreg33<def> = LDRXui %vreg34, 3; mem:LD8[%arr110] GPR64:%vreg33 GPR64common:%vreg34
880B		%vreg31<def> = COPY %vreg33; GPR64all:%vreg31 GPR64:%vreg33
896B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
912B		%X0<def> = COPY %vreg36; GPR64:%vreg36
928B		%X1<def> = COPY %vreg31; GPR64all:%vreg31
944B		BLR %vreg39, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>; GPR64:%vreg39
960B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
976B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
992B		STACKMAP 1, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1]
1008B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#8

1024B	BB#8: derived from LLVM BB %if.end.11
	    Predecessors according to CFG: BB#6 BB#7
1040B		%vreg44<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg44
1056B		%vreg43<def> = LDRXui %vreg44, 4; mem:LD8[%arr2] GPR64:%vreg43 GPR64common:%vreg44
1072B		CBZX %vreg43, <BB#10>; GPR64:%vreg43
	    Successors according to CFG: BB#10 BB#9

1088B	BB#9: derived from LLVM BB %if.then.13
	    Predecessors according to CFG: BB#8
1104B		%vreg58<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg58
1120B		%vreg57<def> = LDRXui %vreg58, 8; mem:LD8[%bzfree14] GPR64:%vreg57 GPR64common:%vreg58
1136B		%vreg55<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg55
1152B		%vreg54<def> = LDRXui %vreg55, 9; mem:LD8[%opaque15] GPR64:%vreg54 GPR64common:%vreg55
1168B		%vreg52<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg52
1184B		%vreg51<def> = LDRXui %vreg52, 4; mem:LD8[%arr216] GPR64:%vreg51 GPR64common:%vreg52
1200B		%vreg49<def> = COPY %vreg51; GPR64all:%vreg49 GPR64:%vreg51
1216B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1232B		%X0<def> = COPY %vreg54; GPR64:%vreg54
1248B		%X1<def> = COPY %vreg49; GPR64all:%vreg49
1264B		BLR %vreg57, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>; GPR64:%vreg57
1280B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1296B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1312B		STACKMAP 2, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1]
1328B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#10

1344B	BB#10: derived from LLVM BB %if.end.17
	    Predecessors according to CFG: BB#8 BB#9
1360B		%vreg62<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg62
1376B		%vreg61<def> = LDRXui %vreg62, 5; mem:LD8[%ftab] GPR64:%vreg61 GPR64common:%vreg62
1392B		CBZX %vreg61, <BB#12>; GPR64:%vreg61
	    Successors according to CFG: BB#12 BB#11

1408B	BB#11: derived from LLVM BB %if.then.19
	    Predecessors according to CFG: BB#10
1424B		%vreg76<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg76
1440B		%vreg75<def> = LDRXui %vreg76, 8; mem:LD8[%bzfree20] GPR64:%vreg75 GPR64common:%vreg76
1456B		%vreg73<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg73
1472B		%vreg72<def> = LDRXui %vreg73, 9; mem:LD8[%opaque21] GPR64:%vreg72 GPR64common:%vreg73
1488B		%vreg70<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg70
1504B		%vreg69<def> = LDRXui %vreg70, 5; mem:LD8[%ftab22] GPR64:%vreg69 GPR64common:%vreg70
1520B		%vreg67<def> = COPY %vreg69; GPR64all:%vreg67 GPR64:%vreg69
1536B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1552B		%X0<def> = COPY %vreg72; GPR64:%vreg72
1568B		%X1<def> = COPY %vreg67; GPR64all:%vreg67
1584B		BLR %vreg75, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>; GPR64:%vreg75
1600B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1616B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1632B		STACKMAP 3, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack1]
1648B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#12

1664B	BB#12: derived from LLVM BB %if.end.23
	    Predecessors according to CFG: BB#10 BB#11
1680B		%vreg91<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg91
1696B		%vreg90<def> = LDRXui %vreg91, 8; mem:LD8[%bzfree24] GPR64:%vreg90 GPR64common:%vreg91
1712B		%vreg88<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg88
1728B		%vreg87<def> = LDRXui %vreg88, 9; mem:LD8[%opaque25] GPR64:%vreg87 GPR64common:%vreg88
1744B		%vreg85<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg85
1760B		%vreg84<def> = LDRXui %vreg85, 6; mem:LD8[%state26] GPR64:%vreg84 GPR64common:%vreg85
1776B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1792B		%X0<def> = COPY %vreg87; GPR64:%vreg87
1808B		%X1<def> = COPY %vreg84; GPR64:%vreg84
1824B		BLR %vreg90, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>; GPR64:%vreg90
1840B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1856B		%vreg77<def> = COPY %XZR; GPR64:%vreg77
1872B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1888B		STACKMAP 4, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack1]
1904B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1920B		%vreg79<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg79
1936B		STRXui %vreg77, %vreg79, 6; mem:ST8[%state27] GPR64:%vreg77 GPR64common:%vreg79
1952B		STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
	    Successors according to CFG: BB#13

1968B	BB#13: derived from LLVM BB %return
	    Predecessors according to CFG: BB#12 BB#5 BB#3 BB#1
1984B		%vreg97<def> = ADRP <ga:@BZ2_bzCompressEnd>[TF=1]; GPR64common:%vreg97
2000B		%vreg98<def> = ADDXri %vreg97, <ga:@BZ2_bzCompressEnd>[TF=34], 0; GPR64sp:%vreg98 GPR64common:%vreg97
2016B		%vreg99<def> = COPY %vreg98; GPR64all:%vreg99 GPR64sp:%vreg98
2032B		%vreg100<def> = COPY %vreg8; GPR64all:%vreg100 GPR64:%vreg8
2048B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2064B		%X0<def> = COPY %vreg99; GPR64all:%vreg99
2080B		%X1<def> = COPY %vreg100; GPR64all:%vreg100
2096B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
2112B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2144B		STACKMAP 5, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
2160B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2176B		%vreg96<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0] GPR32:%vreg96
2192B		%W0<def> = COPY %vreg96; GPR32:%vreg96
2208B		RET_ReallyLR %W0<imp-use>

# End machine code for function BZ2_bzCompressEnd.

********** SIMPLE REGISTER COALESCING **********
********** Function: BZ2_bzCompressEnd
********** JOINING INTERVALS ***********
if.end.11:
if.end.17:
return:
2064B	%X0<def> = COPY %vreg99; GPR64all:%vreg99
	Considering merging %vreg99 with %X0
	Can only merge into reserved registers.
2080B	%X1<def> = COPY %vreg100; GPR64all:%vreg100
	Considering merging %vreg100 with %X1
	Can only merge into reserved registers.
2192B	%W0<def> = COPY %vreg96; GPR32:%vreg96
	Considering merging %vreg96 with %W0
	Can only merge into reserved registers.
if.end:
if.end.3:
if.end.7:
if.end.23:
1792B	%X0<def> = COPY %vreg87; GPR64:%vreg87
	Considering merging %vreg87 with %X0
	Can only merge into reserved registers.
1808B	%X1<def> = COPY %vreg84; GPR64:%vreg84
	Considering merging %vreg84 with %X1
	Can only merge into reserved registers.
1856B	%vreg77<def> = COPY %XZR; GPR64:%vreg77
	Considering merging %vreg77 with %XZR
		RHS = %vreg77 [1856r,1936r:0)  0@1856r
		updated: 1936B	STRXui %XZR, %vreg79, 6; mem:ST8[%state27] GPR64common:%vreg79
	Success: %vreg77 -> %XZR
	Result = %XZR
entry:
16B	%vreg8<def> = COPY %LR; GPR64:%vreg8
	Considering merging %vreg8 with %LR
	Can only merge into reserved registers.
32B	%vreg0<def> = COPY %X0; GPR64:%vreg0
	Considering merging %vreg0 with %X0
	Can only merge into reserved registers.
144B	%X0<def> = COPY %vreg6; GPR64all:%vreg6
	Considering merging %vreg6 with %X0
	Can only merge into reserved registers.
160B	%X1<def> = COPY %vreg7; GPR64all:%vreg7
	Considering merging %vreg7 with %X1
	Can only merge into reserved registers.
if.then:
if.then.2:
if.then.6:
if.then.9:
912B	%X0<def> = COPY %vreg36; GPR64:%vreg36
	Considering merging %vreg36 with %X0
	Can only merge into reserved registers.
928B	%X1<def> = COPY %vreg31; GPR64all:%vreg31
	Considering merging %vreg31 with %X1
	Can only merge into reserved registers.
if.then.13:
1232B	%X0<def> = COPY %vreg54; GPR64:%vreg54
	Considering merging %vreg54 with %X0
	Can only merge into reserved registers.
1248B	%X1<def> = COPY %vreg49; GPR64all:%vreg49
	Considering merging %vreg49 with %X1
	Can only merge into reserved registers.
if.then.19:
1552B	%X0<def> = COPY %vreg72; GPR64:%vreg72
	Considering merging %vreg72 with %X0
	Can only merge into reserved registers.
1568B	%X1<def> = COPY %vreg67; GPR64all:%vreg67
	Considering merging %vreg67 with %X1
	Can only merge into reserved registers.
2016B	%vreg99<def> = COPY %vreg98; GPR64all:%vreg99 GPR64sp:%vreg98
	Considering merging to GPR64sp with %vreg98 in %vreg99
		RHS = %vreg98 [2000r,2016r:0)  0@2000r
		LHS = %vreg99 [2016r,2064r:0)  0@2016r
		merge %vreg99:0@2016r into %vreg98:0@2000r --> @2000r
		erased:	2016r	%vreg99<def> = COPY %vreg98; GPR64all:%vreg99 GPR64sp:%vreg98
		updated: 2000B	%vreg99<def> = ADDXri %vreg97, <ga:@BZ2_bzCompressEnd>[TF=34], 0; GPR64sp:%vreg99 GPR64common:%vreg97
	Success: %vreg98 -> %vreg99
	Result = %vreg99 [2000r,2064r:0)  0@2000r
2032B	%vreg100<def> = COPY %vreg8; GPR64all:%vreg100 GPR64:%vreg8
	Considering merging to GPR64 with %vreg8 in %vreg100
		RHS = %vreg8 [16r,2032r:0)  0@16r
		LHS = %vreg100 [2032r,2080r:0)  0@2032r
		merge %vreg100:0@2032r into %vreg8:0@16r --> @16r
		erased:	2032r	%vreg100<def> = COPY %vreg8; GPR64all:%vreg100 GPR64:%vreg8
		updated: 16B	%vreg100<def> = COPY %LR; GPR64:%vreg100
		updated: 112B	%vreg7<def> = COPY %vreg100; GPR64all:%vreg7 GPR64:%vreg100
	Success: %vreg8 -> %vreg100
	Result = %vreg100 [16r,2080r:0)  0@16r
416B	%vreg13<def> = COPY %vreg15; GPR64:%vreg13,%vreg15
	Considering merging to GPR64 with %vreg15 in %vreg13
		RHS = %vreg15 [400r,416r:0)  0@400r
		LHS = %vreg13 [416r,432r:0)  0@416r
		merge %vreg13:0@416r into %vreg15:0@400r --> @400r
		erased:	416r	%vreg13<def> = COPY %vreg15; GPR64:%vreg13,%vreg15
		updated: 400B	%vreg13<def> = LDRXui %vreg16, 6; mem:LD8[%state] GPR64:%vreg13 GPR64common:%vreg16
	Success: %vreg15 -> %vreg13
	Result = %vreg13 [400r,432r:0)  0@400r
48B	%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
	Considering merging to GPR64 with %vreg0 in %vreg1
		RHS = %vreg0 [32r,48r:0)  0@32r
		LHS = %vreg1 [48r,256r:0)  0@48r
		merge %vreg1:0@48r into %vreg0:0@32r --> @32r
		erased:	48r	%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
		updated: 32B	%vreg1<def> = COPY %X0; GPR64:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [32r,256r:0)  0@32r
96B	%vreg6<def> = COPY %vreg5; GPR64all:%vreg6 GPR64sp:%vreg5
	Considering merging to GPR64sp with %vreg5 in %vreg6
		RHS = %vreg5 [80r,96r:0)  0@80r
		LHS = %vreg6 [96r,144r:0)  0@96r
		merge %vreg6:0@96r into %vreg5:0@80r --> @80r
		erased:	96r	%vreg6<def> = COPY %vreg5; GPR64all:%vreg6 GPR64sp:%vreg5
		updated: 80B	%vreg6<def> = ADDXri %vreg4, <ga:@BZ2_bzCompressEnd>[TF=34], 0; GPR64sp:%vreg6 GPR64common:%vreg4
	Success: %vreg5 -> %vreg6
	Result = %vreg6 [80r,144r:0)  0@80r
112B	%vreg7<def> = COPY %vreg100; GPR64all:%vreg7 GPR64:%vreg100
	Considering merging to GPR64 with %vreg100 in %vreg7
		RHS = %vreg100 [16r,2080r:0)  0@16r
		LHS = %vreg7 [112r,160r:0)  0@112r
		merge %vreg7:0@112r into %vreg100:0@16r --> @16r
		erased:	112r	%vreg7<def> = COPY %vreg100; GPR64all:%vreg7 GPR64:%vreg100
		updated: 16B	%vreg7<def> = COPY %LR; GPR64:%vreg7
		updated: 2080B	%X1<def> = COPY %vreg7; GPR64:%vreg7
	Success: %vreg100 -> %vreg7
	Result = %vreg7 [16r,2080r:0)  0@16r
880B	%vreg31<def> = COPY %vreg33; GPR64all:%vreg31 GPR64:%vreg33
	Considering merging to GPR64 with %vreg33 in %vreg31
		RHS = %vreg33 [864r,880r:0)  0@864r
		LHS = %vreg31 [880r,928r:0)  0@880r
		merge %vreg31:0@880r into %vreg33:0@864r --> @864r
		erased:	880r	%vreg31<def> = COPY %vreg33; GPR64all:%vreg31 GPR64:%vreg33
		updated: 864B	%vreg31<def> = LDRXui %vreg34, 3; mem:LD8[%arr110] GPR64:%vreg31 GPR64common:%vreg34
	Success: %vreg33 -> %vreg31
	Result = %vreg31 [864r,928r:0)  0@864r
1200B	%vreg49<def> = COPY %vreg51; GPR64all:%vreg49 GPR64:%vreg51
	Considering merging to GPR64 with %vreg51 in %vreg49
		RHS = %vreg51 [1184r,1200r:0)  0@1184r
		LHS = %vreg49 [1200r,1248r:0)  0@1200r
		merge %vreg49:0@1200r into %vreg51:0@1184r --> @1184r
		erased:	1200r	%vreg49<def> = COPY %vreg51; GPR64all:%vreg49 GPR64:%vreg51
		updated: 1184B	%vreg49<def> = LDRXui %vreg52, 4; mem:LD8[%arr216] GPR64:%vreg49 GPR64common:%vreg52
	Success: %vreg51 -> %vreg49
	Result = %vreg49 [1184r,1248r:0)  0@1184r
1520B	%vreg67<def> = COPY %vreg69; GPR64all:%vreg67 GPR64:%vreg69
	Considering merging to GPR64 with %vreg69 in %vreg67
		RHS = %vreg69 [1504r,1520r:0)  0@1504r
		LHS = %vreg67 [1520r,1568r:0)  0@1520r
		merge %vreg67:0@1520r into %vreg69:0@1504r --> @1504r
		erased:	1520r	%vreg67<def> = COPY %vreg69; GPR64all:%vreg67 GPR64:%vreg69
		updated: 1504B	%vreg67<def> = LDRXui %vreg70, 5; mem:LD8[%ftab22] GPR64:%vreg67 GPR64common:%vreg70
	Success: %vreg69 -> %vreg67
	Result = %vreg67 [1504r,1568r:0)  0@1504r
2064B	%X0<def> = COPY %vreg99; GPR64sp:%vreg99
	Considering merging %vreg99 with %X0
	Can only merge into reserved registers.
2080B	%X1<def> = COPY %vreg7; GPR64:%vreg7
	Considering merging %vreg7 with %X1
	Can only merge into reserved registers.
144B	%X0<def> = COPY %vreg6; GPR64sp:%vreg6
	Considering merging %vreg6 with %X0
	Can only merge into reserved registers.
160B	%X1<def> = COPY %vreg7; GPR64:%vreg7
	Considering merging %vreg7 with %X1
	Can only merge into reserved registers.
928B	%X1<def> = COPY %vreg31; GPR64:%vreg31
	Considering merging %vreg31 with %X1
	Can only merge into reserved registers.
1248B	%X1<def> = COPY %vreg49; GPR64:%vreg49
	Considering merging %vreg49 with %X1
	Can only merge into reserved registers.
1568B	%X1<def> = COPY %vreg67; GPR64:%vreg67
	Considering merging %vreg67 with %X1
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
W30 [0B,16r:0)[176r,176d:12)[224e,224d:6)[944r,944d:11)[992e,992d:5)[1264r,1264d:10)[1312e,1312d:4)[1584r,1584d:9)[1632e,1632d:3)[1824r,1824d:8)[1888e,1888d:2)[2096r,2096d:7)[2144e,2144d:1)  0@0B-phi 1@2144e 2@1888e 3@1632e 4@1312e 5@992e 6@224e 7@2096r 8@1824r 9@1584r 10@1264r 11@944r 12@176r
WZR [608r,608d:0)  0@608r
W0 [0B,32r:0)[144r,176r:7)[912r,944r:6)[1232r,1264r:5)[1552r,1584r:4)[1792r,1824r:3)[2064r,2096r:2)[2192r,2208r:1)  0@0B-phi 1@2192r 2@2064r 3@1792r 4@1552r 5@1232r 6@912r 7@144r
%vreg1 [32r,256r:0)  0@32r
%vreg3 [272r,288r:0)  0@272r
%vreg4 [64r,80r:0)  0@64r
%vreg6 [80r,144r:0)  0@80r
%vreg7 [16r,2080r:0)  0@16r
%vreg10 [448r,464r:0)  0@448r
%vreg13 [400r,432r:0)  0@400r
%vreg16 [384r,400r:0)  0@384r
%vreg19 [592r,608r:0)  0@592r
%vreg21 [576r,608r:0)  0@576r
%vreg22 [560r,576r:0)  0@560r
%vreg25 [736r,752r:0)  0@736r
%vreg26 [720r,736r:0)  0@720r
%vreg31 [864r,928r:0)  0@864r
%vreg34 [848r,864r:0)  0@848r
%vreg36 [832r,912r:0)  0@832r
%vreg37 [816r,832r:0)  0@816r
%vreg39 [800r,944r:0)  0@800r
%vreg40 [784r,800r:0)  0@784r
%vreg43 [1056r,1072r:0)  0@1056r
%vreg44 [1040r,1056r:0)  0@1040r
%vreg49 [1184r,1248r:0)  0@1184r
%vreg52 [1168r,1184r:0)  0@1168r
%vreg54 [1152r,1232r:0)  0@1152r
%vreg55 [1136r,1152r:0)  0@1136r
%vreg57 [1120r,1264r:0)  0@1120r
%vreg58 [1104r,1120r:0)  0@1104r
%vreg61 [1376r,1392r:0)  0@1376r
%vreg62 [1360r,1376r:0)  0@1360r
%vreg67 [1504r,1568r:0)  0@1504r
%vreg70 [1488r,1504r:0)  0@1488r
%vreg72 [1472r,1552r:0)  0@1472r
%vreg73 [1456r,1472r:0)  0@1456r
%vreg75 [1440r,1584r:0)  0@1440r
%vreg76 [1424r,1440r:0)  0@1424r
%vreg79 [1920r,1936r:0)  0@1920r
%vreg84 [1760r,1808r:0)  0@1760r
%vreg85 [1744r,1760r:0)  0@1744r
%vreg87 [1728r,1792r:0)  0@1728r
%vreg88 [1712r,1728r:0)  0@1712r
%vreg90 [1696r,1824r:0)  0@1696r
%vreg91 [1680r,1696r:0)  0@1680r
%vreg92 [656r,672r:0)  0@656r
%vreg93 [496r,512r:0)  0@496r
%vreg94 [320r,336r:0)  0@320r
%vreg96 [2176r,2192r:0)  0@2176r
%vreg97 [1984r,2000r:0)  0@1984r
%vreg99 [2000r,2064r:0)  0@2000r
RegMasks: 176r 944r 1264r 1584r 1824r 2096r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzCompressEnd: Post SSA
Frame Objects:
  fi#0: size=4, align=4, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=8, align=8, at location [SP]
Function Live Ins: %X0 in %vreg0, %LR in %vreg8

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %LR
16B		%vreg7<def> = COPY %LR; GPR64:%vreg7
32B		%vreg1<def> = COPY %X0; GPR64:%vreg1
64B		%vreg4<def> = ADRP <ga:@BZ2_bzCompressEnd>[TF=1]; GPR64common:%vreg4
80B		%vreg6<def> = ADDXri %vreg4, <ga:@BZ2_bzCompressEnd>[TF=34], 0; GPR64sp:%vreg6 GPR64common:%vreg4
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		%X0<def> = COPY %vreg6; GPR64sp:%vreg6
160B		%X1<def> = COPY %vreg7; GPR64:%vreg7
176B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
224B		STACKMAP 0, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, %vreg1, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1] GPR64:%vreg1
240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
256B		STRXui %vreg1, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg1
272B		%vreg3<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg3
288B		CBNZX %vreg3, <BB#2>; GPR64:%vreg3
	    Successors according to CFG: BB#2 BB#1

304B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
320B		%vreg94<def> = MOVi32imm 4294967294; GPR32:%vreg94
336B		STRWui %vreg94, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg94
352B		B <BB#13>
	    Successors according to CFG: BB#13

368B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0
384B		%vreg16<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg16
400B		%vreg13<def> = LDRXui %vreg16, 6; mem:LD8[%state] GPR64:%vreg13 GPR64common:%vreg16
432B		STRXui %vreg13, <fi#2>, 0; mem:ST8[FixedStack2] GPR64:%vreg13
448B		%vreg10<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg10
464B		CBNZX %vreg10, <BB#4>; GPR64:%vreg10
	    Successors according to CFG: BB#4 BB#3

480B	BB#3: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#2
496B		%vreg93<def> = MOVi32imm 4294967294; GPR32:%vreg93
512B		STRWui %vreg93, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg93
528B		B <BB#13>
	    Successors according to CFG: BB#13

544B	BB#4: derived from LLVM BB %if.end.3
	    Predecessors according to CFG: BB#2
560B		%vreg22<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg22
576B		%vreg21<def> = LDRXui %vreg22, 0; mem:LD8[%strm4] GPR64:%vreg21 GPR64common:%vreg22
592B		%vreg19<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg19
608B		%XZR<def> = SUBSXrr %vreg21, %vreg19, %NZCV<imp-def>; GPR64:%vreg21,%vreg19
624B		Bcc 0, <BB#6>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#6 BB#5

640B	BB#5: derived from LLVM BB %if.then.6
	    Predecessors according to CFG: BB#4
656B		%vreg92<def> = MOVi32imm 4294967294; GPR32:%vreg92
672B		STRWui %vreg92, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg92
688B		B <BB#13>
	    Successors according to CFG: BB#13

704B	BB#6: derived from LLVM BB %if.end.7
	    Predecessors according to CFG: BB#4
720B		%vreg26<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg26
736B		%vreg25<def> = LDRXui %vreg26, 3; mem:LD8[%arr1] GPR64:%vreg25 GPR64common:%vreg26
752B		CBZX %vreg25, <BB#8>; GPR64:%vreg25
	    Successors according to CFG: BB#8 BB#7

768B	BB#7: derived from LLVM BB %if.then.9
	    Predecessors according to CFG: BB#6
784B		%vreg40<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg40
800B		%vreg39<def> = LDRXui %vreg40, 8; mem:LD8[%bzfree] GPR64:%vreg39 GPR64common:%vreg40
816B		%vreg37<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg37
832B		%vreg36<def> = LDRXui %vreg37, 9; mem:LD8[%opaque] GPR64:%vreg36 GPR64common:%vreg37
848B		%vreg34<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg34
864B		%vreg31<def> = LDRXui %vreg34, 3; mem:LD8[%arr110] GPR64:%vreg31 GPR64common:%vreg34
896B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
912B		%X0<def> = COPY %vreg36; GPR64:%vreg36
928B		%X1<def> = COPY %vreg31; GPR64:%vreg31
944B		BLR %vreg39, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>; GPR64:%vreg39
960B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
976B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
992B		STACKMAP 1, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1]
1008B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#8

1024B	BB#8: derived from LLVM BB %if.end.11
	    Predecessors according to CFG: BB#6 BB#7
1040B		%vreg44<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg44
1056B		%vreg43<def> = LDRXui %vreg44, 4; mem:LD8[%arr2] GPR64:%vreg43 GPR64common:%vreg44
1072B		CBZX %vreg43, <BB#10>; GPR64:%vreg43
	    Successors according to CFG: BB#10 BB#9

1088B	BB#9: derived from LLVM BB %if.then.13
	    Predecessors according to CFG: BB#8
1104B		%vreg58<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg58
1120B		%vreg57<def> = LDRXui %vreg58, 8; mem:LD8[%bzfree14] GPR64:%vreg57 GPR64common:%vreg58
1136B		%vreg55<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg55
1152B		%vreg54<def> = LDRXui %vreg55, 9; mem:LD8[%opaque15] GPR64:%vreg54 GPR64common:%vreg55
1168B		%vreg52<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg52
1184B		%vreg49<def> = LDRXui %vreg52, 4; mem:LD8[%arr216] GPR64:%vreg49 GPR64common:%vreg52
1216B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1232B		%X0<def> = COPY %vreg54; GPR64:%vreg54
1248B		%X1<def> = COPY %vreg49; GPR64:%vreg49
1264B		BLR %vreg57, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>; GPR64:%vreg57
1280B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1296B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1312B		STACKMAP 2, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1]
1328B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#10

1344B	BB#10: derived from LLVM BB %if.end.17
	    Predecessors according to CFG: BB#8 BB#9
1360B		%vreg62<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg62
1376B		%vreg61<def> = LDRXui %vreg62, 5; mem:LD8[%ftab] GPR64:%vreg61 GPR64common:%vreg62
1392B		CBZX %vreg61, <BB#12>; GPR64:%vreg61
	    Successors according to CFG: BB#12 BB#11

1408B	BB#11: derived from LLVM BB %if.then.19
	    Predecessors according to CFG: BB#10
1424B		%vreg76<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg76
1440B		%vreg75<def> = LDRXui %vreg76, 8; mem:LD8[%bzfree20] GPR64:%vreg75 GPR64common:%vreg76
1456B		%vreg73<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg73
1472B		%vreg72<def> = LDRXui %vreg73, 9; mem:LD8[%opaque21] GPR64:%vreg72 GPR64common:%vreg73
1488B		%vreg70<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg70
1504B		%vreg67<def> = LDRXui %vreg70, 5; mem:LD8[%ftab22] GPR64:%vreg67 GPR64common:%vreg70
1536B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1552B		%X0<def> = COPY %vreg72; GPR64:%vreg72
1568B		%X1<def> = COPY %vreg67; GPR64:%vreg67
1584B		BLR %vreg75, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>; GPR64:%vreg75
1600B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1616B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1632B		STACKMAP 3, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack1]
1648B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#12

1664B	BB#12: derived from LLVM BB %if.end.23
	    Predecessors according to CFG: BB#10 BB#11
1680B		%vreg91<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg91
1696B		%vreg90<def> = LDRXui %vreg91, 8; mem:LD8[%bzfree24] GPR64:%vreg90 GPR64common:%vreg91
1712B		%vreg88<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg88
1728B		%vreg87<def> = LDRXui %vreg88, 9; mem:LD8[%opaque25] GPR64:%vreg87 GPR64common:%vreg88
1744B		%vreg85<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg85
1760B		%vreg84<def> = LDRXui %vreg85, 6; mem:LD8[%state26] GPR64:%vreg84 GPR64common:%vreg85
1776B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1792B		%X0<def> = COPY %vreg87; GPR64:%vreg87
1808B		%X1<def> = COPY %vreg84; GPR64:%vreg84
1824B		BLR %vreg90, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>; GPR64:%vreg90
1840B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1872B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1888B		STACKMAP 4, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack1]
1904B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1920B		%vreg79<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg79
1936B		STRXui %XZR, %vreg79, 6; mem:ST8[%state27] GPR64common:%vreg79
1952B		STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
	    Successors according to CFG: BB#13

1968B	BB#13: derived from LLVM BB %return
	    Predecessors according to CFG: BB#12 BB#5 BB#3 BB#1
1984B		%vreg97<def> = ADRP <ga:@BZ2_bzCompressEnd>[TF=1]; GPR64common:%vreg97
2000B		%vreg99<def> = ADDXri %vreg97, <ga:@BZ2_bzCompressEnd>[TF=34], 0; GPR64sp:%vreg99 GPR64common:%vreg97
2048B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2064B		%X0<def> = COPY %vreg99; GPR64sp:%vreg99
2080B		%X1<def> = COPY %vreg7; GPR64:%vreg7
2096B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
2112B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2144B		STACKMAP 5, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
2160B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2176B		%vreg96<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0] GPR32:%vreg96
2192B		%W0<def> = COPY %vreg96; GPR32:%vreg96
2208B		RET_ReallyLR %W0<imp-use>

# End machine code for function BZ2_bzCompressEnd.

handleMove 832B -> 856B: %vreg36<def> = LDRXui %vreg37, 9; mem:LD8[%opaque] GPR64:%vreg36 GPR64common:%vreg37
     %vreg36:	[832r,912r:0)  0@832r
        -->	[856r,912r:0)  0@856r
     %vreg37:	[816r,832r:0)  0@816r
        -->	[816r,856r:0)  0@816r
handleMove 800B -> 852B: %vreg39<def> = LDRXui %vreg40, 8; mem:LD8[%bzfree] GPR64:%vreg39 GPR64common:%vreg40
     %vreg39:	[800r,944r:0)  0@800r
        -->	[852r,944r:0)  0@852r
     %vreg40:	[784r,800r:0)  0@784r
        -->	[784r,852r:0)  0@784r
handleMove 1152B -> 1176B: %vreg54<def> = LDRXui %vreg55, 9; mem:LD8[%opaque15] GPR64:%vreg54 GPR64common:%vreg55
     %vreg54:	[1152r,1232r:0)  0@1152r
        -->	[1176r,1232r:0)  0@1176r
     %vreg55:	[1136r,1152r:0)  0@1136r
        -->	[1136r,1176r:0)  0@1136r
handleMove 1120B -> 1172B: %vreg57<def> = LDRXui %vreg58, 8; mem:LD8[%bzfree14] GPR64:%vreg57 GPR64common:%vreg58
     %vreg57:	[1120r,1264r:0)  0@1120r
        -->	[1172r,1264r:0)  0@1172r
     %vreg58:	[1104r,1120r:0)  0@1104r
        -->	[1104r,1172r:0)  0@1104r
handleMove 1472B -> 1496B: %vreg72<def> = LDRXui %vreg73, 9; mem:LD8[%opaque21] GPR64:%vreg72 GPR64common:%vreg73
     %vreg72:	[1472r,1552r:0)  0@1472r
        -->	[1496r,1552r:0)  0@1496r
     %vreg73:	[1456r,1472r:0)  0@1456r
        -->	[1456r,1496r:0)  0@1456r
handleMove 1440B -> 1492B: %vreg75<def> = LDRXui %vreg76, 8; mem:LD8[%bzfree20] GPR64:%vreg75 GPR64common:%vreg76
     %vreg75:	[1440r,1584r:0)  0@1440r
        -->	[1492r,1584r:0)  0@1492r
     %vreg76:	[1424r,1440r:0)  0@1424r
        -->	[1424r,1492r:0)  0@1424r
handleMove 1728B -> 1752B: %vreg87<def> = LDRXui %vreg88, 9; mem:LD8[%opaque25] GPR64:%vreg87 GPR64common:%vreg88
     %vreg87:	[1728r,1792r:0)  0@1728r
        -->	[1752r,1792r:0)  0@1752r
     %vreg88:	[1712r,1728r:0)  0@1712r
        -->	[1712r,1752r:0)  0@1712r
handleMove 1696B -> 1748B: %vreg90<def> = LDRXui %vreg91, 8; mem:LD8[%bzfree24] GPR64:%vreg90 GPR64common:%vreg91
     %vreg90:	[1696r,1824r:0)  0@1696r
        -->	[1748r,1824r:0)  0@1748r
     %vreg91:	[1680r,1696r:0)  0@1680r
        -->	[1680r,1748r:0)  0@1680r
********** GREEDY REGISTER ALLOCATION **********
********** Function: BZ2_bzCompressEnd
********** INTERVALS **********
W30 [0B,16r:0)[176r,176d:12)[224e,224d:6)[944r,944d:11)[992e,992d:5)[1264r,1264d:10)[1312e,1312d:4)[1584r,1584d:9)[1632e,1632d:3)[1824r,1824d:8)[1888e,1888d:2)[2096r,2096d:7)[2144e,2144d:1)  0@0B-phi 1@2144e 2@1888e 3@1632e 4@1312e 5@992e 6@224e 7@2096r 8@1824r 9@1584r 10@1264r 11@944r 12@176r
WZR [608r,608d:0)  0@608r
W0 [0B,32r:0)[144r,176r:7)[912r,944r:6)[1232r,1264r:5)[1552r,1584r:4)[1792r,1824r:3)[2064r,2096r:2)[2192r,2208r:1)  0@0B-phi 1@2192r 2@2064r 3@1792r 4@1552r 5@1232r 6@912r 7@144r
%vreg1 [32r,256r:0)  0@32r
%vreg3 [272r,288r:0)  0@272r
%vreg4 [64r,80r:0)  0@64r
%vreg6 [80r,144r:0)  0@80r
%vreg7 [16r,2080r:0)  0@16r
%vreg10 [448r,464r:0)  0@448r
%vreg13 [400r,432r:0)  0@400r
%vreg16 [384r,400r:0)  0@384r
%vreg19 [592r,608r:0)  0@592r
%vreg21 [576r,608r:0)  0@576r
%vreg22 [560r,576r:0)  0@560r
%vreg25 [736r,752r:0)  0@736r
%vreg26 [720r,736r:0)  0@720r
%vreg31 [864r,928r:0)  0@864r
%vreg34 [848r,864r:0)  0@848r
%vreg36 [856r,912r:0)  0@856r
%vreg37 [816r,856r:0)  0@816r
%vreg39 [852r,944r:0)  0@852r
%vreg40 [784r,852r:0)  0@784r
%vreg43 [1056r,1072r:0)  0@1056r
%vreg44 [1040r,1056r:0)  0@1040r
%vreg49 [1184r,1248r:0)  0@1184r
%vreg52 [1168r,1184r:0)  0@1168r
%vreg54 [1176r,1232r:0)  0@1176r
%vreg55 [1136r,1176r:0)  0@1136r
%vreg57 [1172r,1264r:0)  0@1172r
%vreg58 [1104r,1172r:0)  0@1104r
%vreg61 [1376r,1392r:0)  0@1376r
%vreg62 [1360r,1376r:0)  0@1360r
%vreg67 [1504r,1568r:0)  0@1504r
%vreg70 [1488r,1504r:0)  0@1488r
%vreg72 [1496r,1552r:0)  0@1496r
%vreg73 [1456r,1496r:0)  0@1456r
%vreg75 [1492r,1584r:0)  0@1492r
%vreg76 [1424r,1492r:0)  0@1424r
%vreg79 [1920r,1936r:0)  0@1920r
%vreg84 [1760r,1808r:0)  0@1760r
%vreg85 [1744r,1760r:0)  0@1744r
%vreg87 [1752r,1792r:0)  0@1752r
%vreg88 [1712r,1752r:0)  0@1712r
%vreg90 [1748r,1824r:0)  0@1748r
%vreg91 [1680r,1748r:0)  0@1680r
%vreg92 [656r,672r:0)  0@656r
%vreg93 [496r,512r:0)  0@496r
%vreg94 [320r,336r:0)  0@320r
%vreg96 [2176r,2192r:0)  0@2176r
%vreg97 [1984r,2000r:0)  0@1984r
%vreg99 [2000r,2064r:0)  0@2000r
RegMasks: 176r 944r 1264r 1584r 1824r 2096r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzCompressEnd: Post SSA
Frame Objects:
  fi#0: size=4, align=4, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=8, align=8, at location [SP]
Function Live Ins: %X0 in %vreg0, %LR in %vreg8

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %LR
16B		%vreg7<def> = COPY %LR; GPR64:%vreg7
32B		%vreg1<def> = COPY %X0; GPR64:%vreg1
64B		%vreg4<def> = ADRP <ga:@BZ2_bzCompressEnd>[TF=1]; GPR64common:%vreg4
80B		%vreg6<def> = ADDXri %vreg4, <ga:@BZ2_bzCompressEnd>[TF=34], 0; GPR64sp:%vreg6 GPR64common:%vreg4
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		%X0<def> = COPY %vreg6; GPR64sp:%vreg6
160B		%X1<def> = COPY %vreg7; GPR64:%vreg7
176B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
224B		STACKMAP 0, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, %vreg1, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1] GPR64:%vreg1
240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
256B		STRXui %vreg1, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg1
272B		%vreg3<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg3
288B		CBNZX %vreg3, <BB#2>; GPR64:%vreg3
	    Successors according to CFG: BB#2 BB#1

304B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
320B		%vreg94<def> = MOVi32imm 4294967294; GPR32:%vreg94
336B		STRWui %vreg94, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg94
352B		B <BB#13>
	    Successors according to CFG: BB#13

368B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0
384B		%vreg16<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg16
400B		%vreg13<def> = LDRXui %vreg16, 6; mem:LD8[%state] GPR64:%vreg13 GPR64common:%vreg16
432B		STRXui %vreg13, <fi#2>, 0; mem:ST8[FixedStack2] GPR64:%vreg13
448B		%vreg10<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg10
464B		CBNZX %vreg10, <BB#4>; GPR64:%vreg10
	    Successors according to CFG: BB#4 BB#3

480B	BB#3: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#2
496B		%vreg93<def> = MOVi32imm 4294967294; GPR32:%vreg93
512B		STRWui %vreg93, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg93
528B		B <BB#13>
	    Successors according to CFG: BB#13

544B	BB#4: derived from LLVM BB %if.end.3
	    Predecessors according to CFG: BB#2
560B		%vreg22<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg22
576B		%vreg21<def> = LDRXui %vreg22, 0; mem:LD8[%strm4] GPR64:%vreg21 GPR64common:%vreg22
592B		%vreg19<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg19
608B		%XZR<def> = SUBSXrr %vreg21, %vreg19, %NZCV<imp-def>; GPR64:%vreg21,%vreg19
624B		Bcc 0, <BB#6>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#6 BB#5

640B	BB#5: derived from LLVM BB %if.then.6
	    Predecessors according to CFG: BB#4
656B		%vreg92<def> = MOVi32imm 4294967294; GPR32:%vreg92
672B		STRWui %vreg92, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg92
688B		B <BB#13>
	    Successors according to CFG: BB#13

704B	BB#6: derived from LLVM BB %if.end.7
	    Predecessors according to CFG: BB#4
720B		%vreg26<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg26
736B		%vreg25<def> = LDRXui %vreg26, 3; mem:LD8[%arr1] GPR64:%vreg25 GPR64common:%vreg26
752B		CBZX %vreg25, <BB#8>; GPR64:%vreg25
	    Successors according to CFG: BB#8 BB#7

768B	BB#7: derived from LLVM BB %if.then.9
	    Predecessors according to CFG: BB#6
784B		%vreg40<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg40
816B		%vreg37<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg37
848B		%vreg34<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg34
852B		%vreg39<def> = LDRXui %vreg40, 8; mem:LD8[%bzfree] GPR64:%vreg39 GPR64common:%vreg40
856B		%vreg36<def> = LDRXui %vreg37, 9; mem:LD8[%opaque] GPR64:%vreg36 GPR64common:%vreg37
864B		%vreg31<def> = LDRXui %vreg34, 3; mem:LD8[%arr110] GPR64:%vreg31 GPR64common:%vreg34
896B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
912B		%X0<def> = COPY %vreg36; GPR64:%vreg36
928B		%X1<def> = COPY %vreg31; GPR64:%vreg31
944B		BLR %vreg39, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>; GPR64:%vreg39
960B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
976B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
992B		STACKMAP 1, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1]
1008B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#8

1024B	BB#8: derived from LLVM BB %if.end.11
	    Predecessors according to CFG: BB#6 BB#7
1040B		%vreg44<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg44
1056B		%vreg43<def> = LDRXui %vreg44, 4; mem:LD8[%arr2] GPR64:%vreg43 GPR64common:%vreg44
1072B		CBZX %vreg43, <BB#10>; GPR64:%vreg43
	    Successors according to CFG: BB#10 BB#9

1088B	BB#9: derived from LLVM BB %if.then.13
	    Predecessors according to CFG: BB#8
1104B		%vreg58<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg58
1136B		%vreg55<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg55
1168B		%vreg52<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg52
1172B		%vreg57<def> = LDRXui %vreg58, 8; mem:LD8[%bzfree14] GPR64:%vreg57 GPR64common:%vreg58
1176B		%vreg54<def> = LDRXui %vreg55, 9; mem:LD8[%opaque15] GPR64:%vreg54 GPR64common:%vreg55
1184B		%vreg49<def> = LDRXui %vreg52, 4; mem:LD8[%arr216] GPR64:%vreg49 GPR64common:%vreg52
1216B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1232B		%X0<def> = COPY %vreg54; GPR64:%vreg54
1248B		%X1<def> = COPY %vreg49; GPR64:%vreg49
1264B		BLR %vreg57, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>; GPR64:%vreg57
1280B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1296B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1312B		STACKMAP 2, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1]
1328B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#10

1344B	BB#10: derived from LLVM BB %if.end.17
	    Predecessors according to CFG: BB#8 BB#9
1360B		%vreg62<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg62
1376B		%vreg61<def> = LDRXui %vreg62, 5; mem:LD8[%ftab] GPR64:%vreg61 GPR64common:%vreg62
1392B		CBZX %vreg61, <BB#12>; GPR64:%vreg61
	    Successors according to CFG: BB#12 BB#11

1408B	BB#11: derived from LLVM BB %if.then.19
	    Predecessors according to CFG: BB#10
1424B		%vreg76<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg76
1456B		%vreg73<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg73
1488B		%vreg70<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg70
1492B		%vreg75<def> = LDRXui %vreg76, 8; mem:LD8[%bzfree20] GPR64:%vreg75 GPR64common:%vreg76
1496B		%vreg72<def> = LDRXui %vreg73, 9; mem:LD8[%opaque21] GPR64:%vreg72 GPR64common:%vreg73
1504B		%vreg67<def> = LDRXui %vreg70, 5; mem:LD8[%ftab22] GPR64:%vreg67 GPR64common:%vreg70
1536B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1552B		%X0<def> = COPY %vreg72; GPR64:%vreg72
1568B		%X1<def> = COPY %vreg67; GPR64:%vreg67
1584B		BLR %vreg75, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>; GPR64:%vreg75
1600B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1616B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1632B		STACKMAP 3, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack1]
1648B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#12

1664B	BB#12: derived from LLVM BB %if.end.23
	    Predecessors according to CFG: BB#10 BB#11
1680B		%vreg91<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg91
1712B		%vreg88<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg88
1744B		%vreg85<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg85
1748B		%vreg90<def> = LDRXui %vreg91, 8; mem:LD8[%bzfree24] GPR64:%vreg90 GPR64common:%vreg91
1752B		%vreg87<def> = LDRXui %vreg88, 9; mem:LD8[%opaque25] GPR64:%vreg87 GPR64common:%vreg88
1760B		%vreg84<def> = LDRXui %vreg85, 6; mem:LD8[%state26] GPR64:%vreg84 GPR64common:%vreg85
1776B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1792B		%X0<def> = COPY %vreg87; GPR64:%vreg87
1808B		%X1<def> = COPY %vreg84; GPR64:%vreg84
1824B		BLR %vreg90, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>; GPR64:%vreg90
1840B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1872B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1888B		STACKMAP 4, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack1]
1904B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1920B		%vreg79<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg79
1936B		STRXui %XZR, %vreg79, 6; mem:ST8[%state27] GPR64common:%vreg79
1952B		STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
	    Successors according to CFG: BB#13

1968B	BB#13: derived from LLVM BB %return
	    Predecessors according to CFG: BB#12 BB#5 BB#3 BB#1
1984B		%vreg97<def> = ADRP <ga:@BZ2_bzCompressEnd>[TF=1]; GPR64common:%vreg97
2000B		%vreg99<def> = ADDXri %vreg97, <ga:@BZ2_bzCompressEnd>[TF=34], 0; GPR64sp:%vreg99 GPR64common:%vreg97
2048B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2064B		%X0<def> = COPY %vreg99; GPR64sp:%vreg99
2080B		%X1<def> = COPY %vreg7; GPR64:%vreg7
2096B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
2112B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2144B		STACKMAP 5, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
2160B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2176B		%vreg96<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0] GPR32:%vreg96
2192B		%W0<def> = COPY %vreg96; GPR32:%vreg96
2208B		RET_ReallyLR %W0<imp-use>

# End machine code for function BZ2_bzCompressEnd.


selectOrSplit GPR64:%vreg7 [16r,2080r:0)  0@16r w=1.229708e-03
hints: %X1
missed hint %X1
assigning %vreg7 to %X19: W19 [16r,2080r:0)  0@16r

selectOrSplit GPR64:%vreg1 [32r,256r:0)  0@32r w=4.855769e-03
hints: %X0
missed hint %X0
assigning %vreg1 to %X20: W20 [32r,256r:0)  0@32r

selectOrSplit GPR64sp:%vreg6 [80r,144r:0)  0@80r w=4.353448e-03
hints: %X0
assigning %vreg6 to %X0: W0 [80r,144r:0)  0@80r

selectOrSplit GPR64:%vreg36 [856r,912r:0)  0@856r w=2.790441e-04
hints: %X0
assigning %vreg36 to %X0: W0 [856r,912r:0)  0@856r

selectOrSplit GPR64:%vreg31 [864r,928r:0)  0@864r w=2.742330e-04
hints: %X1
assigning %vreg31 to %X1: W1 [864r,928r:0)  0@864r

selectOrSplit GPR64:%vreg54 [1176r,1232r:0)  0@1176r w=2.790441e-04
hints: %X0
assigning %vreg54 to %X0: W0 [1176r,1232r:0)  0@1176r

selectOrSplit GPR64:%vreg49 [1184r,1248r:0)  0@1184r w=2.742330e-04
hints: %X1
assigning %vreg49 to %X1: W1 [1184r,1248r:0)  0@1184r

selectOrSplit GPR64:%vreg72 [1496r,1552r:0)  0@1496r w=2.790441e-04
hints: %X0
assigning %vreg72 to %X0: W0 [1496r,1552r:0)  0@1496r

selectOrSplit GPR64:%vreg67 [1504r,1568r:0)  0@1504r w=2.742330e-04
hints: %X1
assigning %vreg67 to %X1: W1 [1504r,1568r:0)  0@1504r

selectOrSplit GPR64:%vreg87 [1752r,1792r:0)  0@1752r w=5.422333e-04
hints: %X0
assigning %vreg87 to %X0: W0 [1752r,1792r:0)  0@1752r

selectOrSplit GPR64:%vreg84 [1760r,1808r:0)  0@1760r w=5.325506e-04
hints: %X1
assigning %vreg84 to %X1: W1 [1760r,1808r:0)  0@1760r

selectOrSplit GPR64sp:%vreg99 [2000r,2064r:0)  0@2000r w=4.353448e-03
hints: %X0
assigning %vreg99 to %X0: W0 [2000r,2064r:0)  0@2000r

selectOrSplit GPR32:%vreg96 [2176r,2192r:0)  0@2176r w=inf
hints: %W0
assigning %vreg96 to %W0: W0 [2176r,2192r:0)  0@2176r

selectOrSplit GPR64common:%vreg4 [64r,80r:0)  0@64r w=inf
assigning %vreg4 to %X8: W8 [64r,80r:0)  0@64r

selectOrSplit GPR64:%vreg3 [272r,288r:0)  0@272r w=inf
assigning %vreg3 to %X8: W8 [272r,288r:0)  0@272r

selectOrSplit GPR32:%vreg94 [320r,336r:0)  0@320r w=inf
assigning %vreg94 to %W8: W8 [320r,336r:0)  0@320r

selectOrSplit GPR64common:%vreg16 [384r,400r:0)  0@384r w=inf
assigning %vreg16 to %X8: W8 [384r,400r:0)  0@384r

selectOrSplit GPR64:%vreg13 [400r,432r:0)  0@400r w=inf
assigning %vreg13 to %X8: W8 [400r,432r:0)  0@400r

selectOrSplit GPR64:%vreg10 [448r,464r:0)  0@448r w=inf
assigning %vreg10 to %X8: W8 [448r,464r:0)  0@448r

selectOrSplit GPR32:%vreg93 [496r,512r:0)  0@496r w=inf
assigning %vreg93 to %W8: W8 [496r,512r:0)  0@496r

selectOrSplit GPR64common:%vreg22 [560r,576r:0)  0@560r w=inf
assigning %vreg22 to %X8: W8 [560r,576r:0)  0@560r

selectOrSplit GPR64:%vreg21 [576r,608r:0)  0@576r w=1.130067e-03
assigning %vreg21 to %X8: W8 [576r,608r:0)  0@576r

selectOrSplit GPR64:%vreg19 [592r,608r:0)  0@592r w=inf
assigning %vreg19 to %X9: W9 [592r,608r:0)  0@592r

selectOrSplit GPR32:%vreg92 [656r,672r:0)  0@656r w=inf
assigning %vreg92 to %W8: W8 [656r,672r:0)  0@656r

selectOrSplit GPR64common:%vreg26 [720r,736r:0)  0@720r w=inf
assigning %vreg26 to %X8: W8 [720r,736r:0)  0@720r

selectOrSplit GPR64:%vreg25 [736r,752r:0)  0@736r w=inf
assigning %vreg25 to %X8: W8 [736r,752r:0)  0@736r

selectOrSplit GPR64common:%vreg40 [784r,852r:0)  0@784r w=2.691971e-04
assigning %vreg40 to %X8: W8 [784r,852r:0)  0@784r

selectOrSplit GPR64common:%vreg37 [816r,856r:0)  0@816r w=2.863278e-04
assigning %vreg37 to %X9: W9 [816r,856r:0)  0@816r

selectOrSplit GPR64common:%vreg34 [848r,864r:0)  0@848r w=3.028467e-04
assigning %vreg34 to %X10: W10 [848r,864r:0)  0@848r

selectOrSplit GPR64:%vreg39 [852r,944r:0)  0@852r w=2.560655e-04
assigning %vreg39 to %X8: W8 [852r,944r:0)  0@852r

selectOrSplit GPR64common:%vreg44 [1040r,1056r:0)  0@1040r w=inf
assigning %vreg44 to %X8: W8 [1040r,1056r:0)  0@1040r

selectOrSplit GPR64:%vreg43 [1056r,1072r:0)  0@1056r w=inf
assigning %vreg43 to %X8: W8 [1056r,1072r:0)  0@1056r

selectOrSplit GPR64common:%vreg58 [1104r,1172r:0)  0@1104r w=2.691971e-04
assigning %vreg58 to %X8: W8 [1104r,1172r:0)  0@1104r

selectOrSplit GPR64common:%vreg55 [1136r,1176r:0)  0@1136r w=2.863278e-04
assigning %vreg55 to %X9: W9 [1136r,1176r:0)  0@1136r

selectOrSplit GPR64common:%vreg52 [1168r,1184r:0)  0@1168r w=3.028467e-04
assigning %vreg52 to %X10: W10 [1168r,1184r:0)  0@1168r

selectOrSplit GPR64:%vreg57 [1172r,1264r:0)  0@1172r w=2.560655e-04
assigning %vreg57 to %X8: W8 [1172r,1264r:0)  0@1172r

selectOrSplit GPR64common:%vreg62 [1360r,1376r:0)  0@1360r w=inf
assigning %vreg62 to %X8: W8 [1360r,1376r:0)  0@1360r

selectOrSplit GPR64:%vreg61 [1376r,1392r:0)  0@1376r w=inf
assigning %vreg61 to %X8: W8 [1376r,1392r:0)  0@1376r

selectOrSplit GPR64common:%vreg76 [1424r,1492r:0)  0@1424r w=2.691971e-04
assigning %vreg76 to %X8: W8 [1424r,1492r:0)  0@1424r

selectOrSplit GPR64common:%vreg73 [1456r,1496r:0)  0@1456r w=2.863278e-04
assigning %vreg73 to %X9: W9 [1456r,1496r:0)  0@1456r

selectOrSplit GPR64common:%vreg70 [1488r,1504r:0)  0@1488r w=3.028467e-04
assigning %vreg70 to %X10: W10 [1488r,1504r:0)  0@1488r

selectOrSplit GPR64:%vreg75 [1492r,1584r:0)  0@1492r w=2.560655e-04
assigning %vreg75 to %X8: W8 [1492r,1584r:0)  0@1492r

selectOrSplit GPR64common:%vreg91 [1680r,1748r:0)  0@1680r w=5.047446e-04
assigning %vreg91 to %X8: W8 [1680r,1748r:0)  0@1680r

selectOrSplit GPR64common:%vreg88 [1712r,1752r:0)  0@1712r w=5.368647e-04
assigning %vreg88 to %X9: W9 [1712r,1752r:0)  0@1712r

selectOrSplit GPR64common:%vreg85 [1744r,1760r:0)  0@1744r w=5.678377e-04
assigning %vreg85 to %X10: W10 [1744r,1760r:0)  0@1744r

selectOrSplit GPR64:%vreg90 [1748r,1824r:0)  0@1748r w=4.962615e-04
assigning %vreg90 to %X8: W8 [1748r,1824r:0)  0@1748r

selectOrSplit GPR64common:%vreg79 [1920r,1936r:0)  0@1920r w=inf
assigning %vreg79 to %X8: W8 [1920r,1936r:0)  0@1920r

selectOrSplit GPR64common:%vreg97 [1984r,2000r:0)  0@1984r w=inf
assigning %vreg97 to %X8: W8 [1984r,2000r:0)  0@1984r

********** STACK TRANSFORMATION METADATA **********
********** Function: BZ2_bzCompressEnd
********** REGISTER MAP **********
[%vreg1 -> %X20] GPR64
[%vreg3 -> %X8] GPR64
[%vreg4 -> %X8] GPR64common
[%vreg6 -> %X0] GPR64sp
[%vreg7 -> %X19] GPR64
[%vreg10 -> %X8] GPR64
[%vreg13 -> %X8] GPR64
[%vreg16 -> %X8] GPR64common
[%vreg19 -> %X9] GPR64
[%vreg21 -> %X8] GPR64
[%vreg22 -> %X8] GPR64common
[%vreg25 -> %X8] GPR64
[%vreg26 -> %X8] GPR64common
[%vreg31 -> %X1] GPR64
[%vreg34 -> %X10] GPR64common
[%vreg36 -> %X0] GPR64
[%vreg37 -> %X9] GPR64common
[%vreg39 -> %X8] GPR64
[%vreg40 -> %X8] GPR64common
[%vreg43 -> %X8] GPR64
[%vreg44 -> %X8] GPR64common
[%vreg49 -> %X1] GPR64
[%vreg52 -> %X10] GPR64common
[%vreg54 -> %X0] GPR64
[%vreg55 -> %X9] GPR64common
[%vreg57 -> %X8] GPR64
[%vreg58 -> %X8] GPR64common
[%vreg61 -> %X8] GPR64
[%vreg62 -> %X8] GPR64common
[%vreg67 -> %X1] GPR64
[%vreg70 -> %X10] GPR64common
[%vreg72 -> %X0] GPR64
[%vreg73 -> %X9] GPR64common
[%vreg75 -> %X8] GPR64
[%vreg76 -> %X8] GPR64common
[%vreg79 -> %X8] GPR64common
[%vreg84 -> %X1] GPR64
[%vreg85 -> %X10] GPR64common
[%vreg87 -> %X0] GPR64
[%vreg88 -> %X9] GPR64common
[%vreg90 -> %X8] GPR64
[%vreg91 -> %X8] GPR64common
[%vreg92 -> %W8] GPR32
[%vreg93 -> %W8] GPR32
[%vreg94 -> %W8] GPR32
[%vreg96 -> %W0] GPR32
[%vreg97 -> %X8] GPR64common
[%vreg99 -> %X0] GPR64sp


Stackmap 0:
  STACKMAP 0, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, %vreg1, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1] GPR64:%vreg1

i32* %retval: in stack slot 0 (size: 4)
%struct.EState** %s: in stack slot 2 (size: 8)
%struct.bz_stream* %strm: in register %X20 (vreg 1)
%struct.bz_stream** %strm.addr: in stack slot 1 (size: 8)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1]

i32* %retval: in stack slot 0 (size: 4)
%struct.EState** %s: in stack slot 2 (size: 8)
%struct.bz_stream** %strm.addr: in stack slot 1 (size: 8)

Duplicate operand locations:


Stackmap 2:
  STACKMAP 2, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1]

i32* %retval: in stack slot 0 (size: 4)
%struct.EState** %s: in stack slot 2 (size: 8)
%struct.bz_stream** %strm.addr: in stack slot 1 (size: 8)

Duplicate operand locations:


Stackmap 3:
  STACKMAP 3, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack1]

i32* %retval: in stack slot 0 (size: 4)
%struct.bz_stream** %strm.addr: in stack slot 1 (size: 8)

Duplicate operand locations:


Stackmap 4:
  STACKMAP 4, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack1]

i32* %retval: in stack slot 0 (size: 4)
%struct.bz_stream** %strm.addr: in stack slot 1 (size: 8)

Duplicate operand locations:


Stackmap 5:
  STACKMAP 5, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)

i32* %retval: in stack slot 0 (size: 4)

Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, %vreg1, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1] GPR64:%vreg1
  -> Call instruction SlotIndex 176B, searching vregs 0 -> 101 and stack slots 0 -> 3
    + vreg7 is live in register but not in stackmap
      Defining instruction: %vreg7<def> = COPY %LR; GPR64:%vreg7
      Value: generated value, 1 instruction(s)

  STACKMAP 1, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1]
  -> Call instruction SlotIndex 944B, searching vregs 0 -> 101 and stack slots 0 -> 3
    + vreg7 is live in register but not in stackmap
      Defining instruction: %vreg7<def> = COPY %LR; GPR64:%vreg7
      Value: generated value, 1 instruction(s)

  STACKMAP 2, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1]
  -> Call instruction SlotIndex 1264B, searching vregs 0 -> 101 and stack slots 0 -> 3
    + vreg7 is live in register but not in stackmap
      Defining instruction: %vreg7<def> = COPY %LR; GPR64:%vreg7
      Value: generated value, 1 instruction(s)

  STACKMAP 3, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack1]
  -> Call instruction SlotIndex 1584B, searching vregs 0 -> 101 and stack slots 0 -> 3
    + vreg7 is live in register but not in stackmap
      Defining instruction: %vreg7<def> = COPY %LR; GPR64:%vreg7
      Value: generated value, 1 instruction(s)

  STACKMAP 4, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack1]
  -> Call instruction SlotIndex 1824B, searching vregs 0 -> 101 and stack slots 0 -> 3
    + vreg7 is live in register but not in stackmap
      Defining instruction: %vreg7<def> = COPY %LR; GPR64:%vreg7
      Value: generated value, 1 instruction(s)

  STACKMAP 5, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
  -> Call instruction SlotIndex 2096B, searching vregs 0 -> 101 and stack slots 0 -> 3

********** REWRITE VIRTUAL REGISTERS **********
********** Function: BZ2_bzCompressEnd
********** REGISTER MAP **********
[%vreg1 -> %X20] GPR64
[%vreg3 -> %X8] GPR64
[%vreg4 -> %X8] GPR64common
[%vreg6 -> %X0] GPR64sp
[%vreg7 -> %X19] GPR64
[%vreg10 -> %X8] GPR64
[%vreg13 -> %X8] GPR64
[%vreg16 -> %X8] GPR64common
[%vreg19 -> %X9] GPR64
[%vreg21 -> %X8] GPR64
[%vreg22 -> %X8] GPR64common
[%vreg25 -> %X8] GPR64
[%vreg26 -> %X8] GPR64common
[%vreg31 -> %X1] GPR64
[%vreg34 -> %X10] GPR64common
[%vreg36 -> %X0] GPR64
[%vreg37 -> %X9] GPR64common
[%vreg39 -> %X8] GPR64
[%vreg40 -> %X8] GPR64common
[%vreg43 -> %X8] GPR64
[%vreg44 -> %X8] GPR64common
[%vreg49 -> %X1] GPR64
[%vreg52 -> %X10] GPR64common
[%vreg54 -> %X0] GPR64
[%vreg55 -> %X9] GPR64common
[%vreg57 -> %X8] GPR64
[%vreg58 -> %X8] GPR64common
[%vreg61 -> %X8] GPR64
[%vreg62 -> %X8] GPR64common
[%vreg67 -> %X1] GPR64
[%vreg70 -> %X10] GPR64common
[%vreg72 -> %X0] GPR64
[%vreg73 -> %X9] GPR64common
[%vreg75 -> %X8] GPR64
[%vreg76 -> %X8] GPR64common
[%vreg79 -> %X8] GPR64common
[%vreg84 -> %X1] GPR64
[%vreg85 -> %X10] GPR64common
[%vreg87 -> %X0] GPR64
[%vreg88 -> %X9] GPR64common
[%vreg90 -> %X8] GPR64
[%vreg91 -> %X8] GPR64common
[%vreg92 -> %W8] GPR32
[%vreg93 -> %W8] GPR32
[%vreg94 -> %W8] GPR32
[%vreg96 -> %W0] GPR32
[%vreg97 -> %X8] GPR64common
[%vreg99 -> %X0] GPR64sp

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %LR %X0
16B		%vreg7<def> = COPY %LR; GPR64:%vreg7
32B		%vreg1<def> = COPY %X0; GPR64:%vreg1
64B		%vreg4<def> = ADRP <ga:@BZ2_bzCompressEnd>[TF=1]; GPR64common:%vreg4
80B		%vreg6<def> = ADDXri %vreg4<kill>, <ga:@BZ2_bzCompressEnd>[TF=34], 0; GPR64sp:%vreg6 GPR64common:%vreg4
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		%X0<def> = COPY %vreg6<kill>; GPR64sp:%vreg6
160B		%X1<def> = COPY %vreg7; GPR64:%vreg7
176B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
224B		STACKMAP 0, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, %vreg1, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1] GPR64:%vreg1
240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
256B		STRXui %vreg1<kill>, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg1
272B		%vreg3<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg3
288B		CBNZX %vreg3<kill>, <BB#2>; GPR64:%vreg3
	    Successors according to CFG: BB#2 BB#1
> %X19<def> = COPY %LR
> %X20<def> = COPY %X0
> %X8<def> = ADRP <ga:@BZ2_bzCompressEnd>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@BZ2_bzCompressEnd>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19
> BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 0, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, %X20, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRXui %X20<kill>, <fi#1>, 0; mem:ST8[FixedStack1]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> CBNZX %X8<kill>, <BB#2>
304B	BB#1: derived from LLVM BB %if.then
	    Live Ins: %X19
	    Predecessors according to CFG: BB#0
320B		%vreg94<def> = MOVi32imm 4294967294; GPR32:%vreg94
336B		STRWui %vreg94<kill>, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg94
352B		B <BB#13>
	    Successors according to CFG: BB#13
> %W8<def> = MOVi32imm 4294967294
> STRWui %W8<kill>, <fi#0>, 0; mem:ST4[FixedStack0]
> B <BB#13>
368B	BB#2: derived from LLVM BB %if.end
	    Live Ins: %X19
	    Predecessors according to CFG: BB#0
384B		%vreg16<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg16
400B		%vreg13<def> = LDRXui %vreg16<kill>, 6; mem:LD8[%state] GPR64:%vreg13 GPR64common:%vreg16
432B		STRXui %vreg13<kill>, <fi#2>, 0; mem:ST8[FixedStack2] GPR64:%vreg13
448B		%vreg10<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg10
464B		CBNZX %vreg10<kill>, <BB#4>; GPR64:%vreg10
	    Successors according to CFG: BB#4 BB#3
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X8<def> = LDRXui %X8<kill>, 6; mem:LD8[%state]
> STRXui %X8<kill>, <fi#2>, 0; mem:ST8[FixedStack2]
> %X8<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2]
> CBNZX %X8<kill>, <BB#4>
480B	BB#3: derived from LLVM BB %if.then.2
	    Live Ins: %X19
	    Predecessors according to CFG: BB#2
496B		%vreg93<def> = MOVi32imm 4294967294; GPR32:%vreg93
512B		STRWui %vreg93<kill>, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg93
528B		B <BB#13>
	    Successors according to CFG: BB#13
> %W8<def> = MOVi32imm 4294967294
> STRWui %W8<kill>, <fi#0>, 0; mem:ST4[FixedStack0]
> B <BB#13>
544B	BB#4: derived from LLVM BB %if.end.3
	    Live Ins: %X19
	    Predecessors according to CFG: BB#2
560B		%vreg22<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg22
576B		%vreg21<def> = LDRXui %vreg22<kill>, 0; mem:LD8[%strm4] GPR64:%vreg21 GPR64common:%vreg22
592B		%vreg19<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg19
608B		%XZR<def> = SUBSXrr %vreg21<kill>, %vreg19<kill>, %NZCV<imp-def>; GPR64:%vreg21,%vreg19
624B		Bcc 0, <BB#6>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#6 BB#5
> %X8<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2]
> %X8<def> = LDRXui %X8<kill>, 0; mem:LD8[%strm4]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %XZR<def> = SUBSXrr %X8<kill>, %X9<kill>, %NZCV<imp-def>
> Bcc 0, <BB#6>, %NZCV<imp-use,kill>
640B	BB#5: derived from LLVM BB %if.then.6
	    Live Ins: %X19
	    Predecessors according to CFG: BB#4
656B		%vreg92<def> = MOVi32imm 4294967294; GPR32:%vreg92
672B		STRWui %vreg92<kill>, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg92
688B		B <BB#13>
	    Successors according to CFG: BB#13
> %W8<def> = MOVi32imm 4294967294
> STRWui %W8<kill>, <fi#0>, 0; mem:ST4[FixedStack0]
> B <BB#13>
704B	BB#6: derived from LLVM BB %if.end.7
	    Live Ins: %X19
	    Predecessors according to CFG: BB#4
720B		%vreg26<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg26
736B		%vreg25<def> = LDRXui %vreg26<kill>, 3; mem:LD8[%arr1] GPR64:%vreg25 GPR64common:%vreg26
752B		CBZX %vreg25<kill>, <BB#8>; GPR64:%vreg25
	    Successors according to CFG: BB#8 BB#7
> %X8<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2]
> %X8<def> = LDRXui %X8<kill>, 3; mem:LD8[%arr1]
> CBZX %X8<kill>, <BB#8>
768B	BB#7: derived from LLVM BB %if.then.9
	    Live Ins: %X19
	    Predecessors according to CFG: BB#6
784B		%vreg40<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg40
816B		%vreg37<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg37
848B		%vreg34<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg34
852B		%vreg39<def> = LDRXui %vreg40<kill>, 8; mem:LD8[%bzfree] GPR64:%vreg39 GPR64common:%vreg40
856B		%vreg36<def> = LDRXui %vreg37<kill>, 9; mem:LD8[%opaque] GPR64:%vreg36 GPR64common:%vreg37
864B		%vreg31<def> = LDRXui %vreg34<kill>, 3; mem:LD8[%arr110] GPR64:%vreg31 GPR64common:%vreg34
896B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
912B		%X0<def> = COPY %vreg36<kill>; GPR64:%vreg36
928B		%X1<def> = COPY %vreg31<kill>; GPR64:%vreg31
944B		BLR %vreg39<kill>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>; GPR64:%vreg39
960B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
976B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
992B		STACKMAP 1, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1]
1008B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#8
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X10<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2]
> %X8<def> = LDRXui %X8<kill>, 8; mem:LD8[%bzfree]
> %X0<def> = LDRXui %X9<kill>, 9; mem:LD8[%opaque]
> %X1<def> = LDRXui %X10<kill>, 3; mem:LD8[%arr110]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X1<kill>
Deleting identity copy.
> BLR %X8<kill>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 1, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1024B	BB#8: derived from LLVM BB %if.end.11
	    Live Ins: %X19
	    Predecessors according to CFG: BB#6 BB#7
1040B		%vreg44<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg44
1056B		%vreg43<def> = LDRXui %vreg44<kill>, 4; mem:LD8[%arr2] GPR64:%vreg43 GPR64common:%vreg44
1072B		CBZX %vreg43<kill>, <BB#10>; GPR64:%vreg43
	    Successors according to CFG: BB#10 BB#9
> %X8<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2]
> %X8<def> = LDRXui %X8<kill>, 4; mem:LD8[%arr2]
> CBZX %X8<kill>, <BB#10>
1088B	BB#9: derived from LLVM BB %if.then.13
	    Live Ins: %X19
	    Predecessors according to CFG: BB#8
1104B		%vreg58<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg58
1136B		%vreg55<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg55
1168B		%vreg52<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg52
1172B		%vreg57<def> = LDRXui %vreg58<kill>, 8; mem:LD8[%bzfree14] GPR64:%vreg57 GPR64common:%vreg58
1176B		%vreg54<def> = LDRXui %vreg55<kill>, 9; mem:LD8[%opaque15] GPR64:%vreg54 GPR64common:%vreg55
1184B		%vreg49<def> = LDRXui %vreg52<kill>, 4; mem:LD8[%arr216] GPR64:%vreg49 GPR64common:%vreg52
1216B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1232B		%X0<def> = COPY %vreg54<kill>; GPR64:%vreg54
1248B		%X1<def> = COPY %vreg49<kill>; GPR64:%vreg49
1264B		BLR %vreg57<kill>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>; GPR64:%vreg57
1280B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1296B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1312B		STACKMAP 2, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1]
1328B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#10
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X10<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2]
> %X8<def> = LDRXui %X8<kill>, 8; mem:LD8[%bzfree14]
> %X0<def> = LDRXui %X9<kill>, 9; mem:LD8[%opaque15]
> %X1<def> = LDRXui %X10<kill>, 4; mem:LD8[%arr216]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X1<kill>
Deleting identity copy.
> BLR %X8<kill>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 2, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1344B	BB#10: derived from LLVM BB %if.end.17
	    Live Ins: %X19
	    Predecessors according to CFG: BB#8 BB#9
1360B		%vreg62<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg62
1376B		%vreg61<def> = LDRXui %vreg62<kill>, 5; mem:LD8[%ftab] GPR64:%vreg61 GPR64common:%vreg62
1392B		CBZX %vreg61<kill>, <BB#12>; GPR64:%vreg61
	    Successors according to CFG: BB#12 BB#11
> %X8<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2]
> %X8<def> = LDRXui %X8<kill>, 5; mem:LD8[%ftab]
> CBZX %X8<kill>, <BB#12>
1408B	BB#11: derived from LLVM BB %if.then.19
	    Live Ins: %X19
	    Predecessors according to CFG: BB#10
1424B		%vreg76<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg76
1456B		%vreg73<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg73
1488B		%vreg70<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg70
1492B		%vreg75<def> = LDRXui %vreg76<kill>, 8; mem:LD8[%bzfree20] GPR64:%vreg75 GPR64common:%vreg76
1496B		%vreg72<def> = LDRXui %vreg73<kill>, 9; mem:LD8[%opaque21] GPR64:%vreg72 GPR64common:%vreg73
1504B		%vreg67<def> = LDRXui %vreg70<kill>, 5; mem:LD8[%ftab22] GPR64:%vreg67 GPR64common:%vreg70
1536B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1552B		%X0<def> = COPY %vreg72<kill>; GPR64:%vreg72
1568B		%X1<def> = COPY %vreg67<kill>; GPR64:%vreg67
1584B		BLR %vreg75<kill>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>; GPR64:%vreg75
1600B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1616B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1632B		STACKMAP 3, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack1]
1648B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#12
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X10<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2]
> %X8<def> = LDRXui %X8<kill>, 8; mem:LD8[%bzfree20]
> %X0<def> = LDRXui %X9<kill>, 9; mem:LD8[%opaque21]
> %X1<def> = LDRXui %X10<kill>, 5; mem:LD8[%ftab22]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X1<kill>
Deleting identity copy.
> BLR %X8<kill>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 3, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack1]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1664B	BB#12: derived from LLVM BB %if.end.23
	    Live Ins: %X19
	    Predecessors according to CFG: BB#10 BB#11
1680B		%vreg91<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg91
1712B		%vreg88<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg88
1744B		%vreg85<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg85
1748B		%vreg90<def> = LDRXui %vreg91<kill>, 8; mem:LD8[%bzfree24] GPR64:%vreg90 GPR64common:%vreg91
1752B		%vreg87<def> = LDRXui %vreg88<kill>, 9; mem:LD8[%opaque25] GPR64:%vreg87 GPR64common:%vreg88
1760B		%vreg84<def> = LDRXui %vreg85<kill>, 6; mem:LD8[%state26] GPR64:%vreg84 GPR64common:%vreg85
1776B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1792B		%X0<def> = COPY %vreg87<kill>; GPR64:%vreg87
1808B		%X1<def> = COPY %vreg84<kill>; GPR64:%vreg84
1824B		BLR %vreg90<kill>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>; GPR64:%vreg90
1840B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1872B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1888B		STACKMAP 4, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack1]
1904B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1920B		%vreg79<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg79
1936B		STRXui %XZR, %vreg79<kill>, 6; mem:ST8[%state27] GPR64common:%vreg79
1952B		STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
	    Successors according to CFG: BB#13
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X10<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X8<def> = LDRXui %X8<kill>, 8; mem:LD8[%bzfree24]
> %X0<def> = LDRXui %X9<kill>, 9; mem:LD8[%opaque25]
> %X1<def> = LDRXui %X10<kill>, 6; mem:LD8[%state26]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X1<kill>
Deleting identity copy.
> BLR %X8<kill>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 4, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack1]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRXui %XZR, %X8<kill>, 6; mem:ST8[%state27]
> STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
1968B	BB#13: derived from LLVM BB %return
	    Live Ins: %X19
	    Predecessors according to CFG: BB#12 BB#5 BB#3 BB#1
1984B		%vreg97<def> = ADRP <ga:@BZ2_bzCompressEnd>[TF=1]; GPR64common:%vreg97
2000B		%vreg99<def> = ADDXri %vreg97<kill>, <ga:@BZ2_bzCompressEnd>[TF=34], 0; GPR64sp:%vreg99 GPR64common:%vreg97
2048B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2064B		%X0<def> = COPY %vreg99<kill>; GPR64sp:%vreg99
2080B		%X1<def> = COPY %vreg7<kill>; GPR64:%vreg7
2096B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
2112B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2144B		STACKMAP 5, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
2160B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2176B		%vreg96<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0] GPR32:%vreg96
2192B		%W0<def> = COPY %vreg96<kill>; GPR32:%vreg96
2208B		RET_ReallyLR %W0<imp-use>
> %X8<def> = ADRP <ga:@BZ2_bzCompressEnd>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@BZ2_bzCompressEnd>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19<kill>
> BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 5, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0]
> %W0<def> = COPY %W0<kill>
Deleting identity copy.
> RET_ReallyLR %W0<imp-use>
Computing live-in reg-units in ABI blocks.
0B	BB#0 W0#0 W1#0 W2#0 W30#0
Created 4 new intervals.
********** INTERVALS **********
W30 [0B,16r:0)[240r,240d:7)[288e,288d:4)[384r,384d:8)[448e,448d:3)[1488r,1488d:6)[1552e,1552d:2)[2512r,2512d:5)[2560e,2560d:1)  0@0B-phi 1@2560e 2@1552e 3@448e 4@288e 5@2512r 6@1488r 7@240r 8@384r
W0 [0B,64r:0)[208r,240r:6)[384r,416r:2)[1440r,1488r:5)[1488r,1520r:4)[2480r,2512r:3)[2608r,2624r:1)  0@0B-phi 1@2608r 2@384r 3@2480r 4@1488r 5@1440r 6@208r
W1 [0B,48r:0)[224r,240r:3)[1456r,1488r:1)[2496r,2512r:2)  0@0B-phi 1@1456r 2@2496r 3@224r
W2 [0B,32r:0)[1472r,1488r:1)  0@0B-phi 1@1472r
%vreg0 [64r,80r:0)  0@64r
%vreg1 [80r,320r:0)  0@80r
%vreg2 [48r,96r:0)  0@48r
%vreg3 [96r,336r:0)  0@96r
%vreg4 [32r,112r:0)  0@32r
%vreg5 [112r,352r:0)  0@112r
%vreg7 [416r,480r:0)  0@416r
%vreg8 [128r,144r:0)  0@128r
%vreg9 [144r,160r:0)  0@144r
%vreg10 [160r,208r:0)  0@160r
%vreg11 [176r,224r:0)  0@176r
%vreg12 [16r,2448r:0)  0@16r
%vreg13 [512r,528r:0)  0@512r
%vreg15 [576r,592r:0)  0@576r
%vreg17 [688r,704r:0)  0@688r
%vreg19 [736r,752r:0)  0@736r
%vreg21 [864r,880r:0)  0@864r
%vreg23 [912r,928r:0)  0@912r
%vreg26 [1056r,1072r:0)  0@1056r
%vreg27 [1040r,1056r:0)  0@1040r
%vreg28 [1104r,1120r:0)  0@1104r
%vreg29 [1120r,1152r:0)  0@1120r
%vreg31 [1136r,1152r:0)  0@1136r
%vreg34 [1200r,1216r:0)  0@1200r
%vreg35 [1184r,1200r:0)  0@1184r
%vreg36 [1248r,1264r:0)  0@1248r
%vreg37 [1264r,1296r:0)  0@1264r
%vreg39 [1280r,1296r:0)  0@1280r
%vreg41 [1616r,1632r:0)  0@1616r
%vreg44 [1584r,1600r:0)  0@1584r
%vreg47 [1328r,1456r:0)  0@1328r
%vreg48 [1344r,1472r:0)  0@1344r
%vreg49 [1520r,1584r:0)  0@1520r
%vreg51 [1408r,1440r:0)  0@1408r
%vreg52 [1392r,1408r:0)  0@1392r
%vreg54 [1376r,1488r:0)  0@1376r
%vreg55 [1360r,1376r:0)  0@1360r
%vreg58 [2336r,2352r:0)  0@2336r
%vreg59 [2320r,2352r:0)  0@2320r
%vreg61 [2288r,2304r:0)  0@2288r
%vreg62 [1728r,2272r:0)  0@1728r
%vreg64 [2256r,2272r:0)  0@2256r
%vreg66 [2224r,2240r:0)  0@2224r
%vreg68 [2192r,2208r:0)  0@2192r
%vreg71 [2160r,2176r:0)  0@2160r
%vreg73 [2144r,2176r:0)  0@2144r
%vreg74 [2128r,2144r:0)  0@2128r
%vreg76 [2096r,2112r:0)  0@2096r
%vreg78 [2064r,2080r:0)  0@2064r
%vreg80 [2032r,2048r:0)  0@2032r
%vreg82 [2000r,2016r:0)  0@2000r
%vreg84 [1968r,1984r:0)  0@1968r
%vreg86 [1936r,1952r:0)  0@1936r
%vreg88 [1904r,1920r:0)  0@1904r
%vreg89 [1744r,1888r:0)  0@1744r
%vreg91 [1872r,1888r:0)  0@1872r
%vreg94 [1840r,1856r:0)  0@1840r
%vreg96 [1824r,1856r:0)  0@1824r
%vreg97 [1808r,1824r:0)  0@1808r
%vreg100 [1776r,1792r:0)  0@1776r
%vreg101 [1760r,1792r:0)  0@1760r
%vreg102 [1664r,1680r:0)  0@1664r
%vreg103 [976r,992r:0)  0@976r
%vreg104 [800r,816r:0)  0@800r
%vreg105 [624r,640r:0)  0@624r
%vreg107 [2592r,2608r:0)  0@2592r
%vreg108 [2400r,2416r:0)  0@2400r
%vreg109 [2416r,2432r:0)  0@2416r
%vreg110 [2432r,2480r:0)  0@2432r
%vreg111 [2448r,2496r:0)  0@2448r
RegMasks: 240r 384r 1488r 2512r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzDecompressInit: Post SSA
Frame Objects:
  fi#0: size=4, align=4, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=4, align=4, at location [SP]
  fi#3: size=4, align=4, at location [SP]
  fi#4: size=8, align=8, at location [SP]
Function Live Ins: %X0 in %vreg0, %W1 in %vreg2, %W2 in %vreg4, %LR in %vreg12

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %W1 %W2 %LR
16B		%vreg12<def> = COPY %LR; GPR64:%vreg12
32B		%vreg4<def> = COPY %W2; GPR32:%vreg4
48B		%vreg2<def> = COPY %W1; GPR32:%vreg2
64B		%vreg0<def> = COPY %X0; GPR64:%vreg0
80B		%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
96B		%vreg3<def> = COPY %vreg2; GPR32:%vreg3,%vreg2
112B		%vreg5<def> = COPY %vreg4; GPR32:%vreg5,%vreg4
128B		%vreg8<def> = ADRP <ga:@BZ2_bzDecompressInit>[TF=1]; GPR64common:%vreg8
144B		%vreg9<def> = ADDXri %vreg8, <ga:@BZ2_bzDecompressInit>[TF=34], 0; GPR64sp:%vreg9 GPR64common:%vreg8
160B		%vreg10<def> = COPY %vreg9; GPR64all:%vreg10 GPR64sp:%vreg9
176B		%vreg11<def> = COPY %vreg12; GPR64all:%vreg11 GPR64:%vreg12
192B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
208B		%X0<def> = COPY %vreg10; GPR64all:%vreg10
224B		%X1<def> = COPY %vreg11; GPR64all:%vreg11
240B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
256B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
272B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
288B		STACKMAP 0, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, %vreg5, 0, <fi#3>, 0, %vreg1, 0, <fi#1>, 0, %vreg3, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack4] LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack2](align=4) GPR32:%vreg5,%vreg3 GPR64:%vreg1
304B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
320B		STRXui %vreg1, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg1
336B		STRWui %vreg3, <fi#2>, 0; mem:ST4[FixedStack2] GPR32:%vreg3
352B		STRWui %vreg5, <fi#3>, 0; mem:ST4[FixedStack3] GPR32:%vreg5
368B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
384B		BL <ga:@bz_config_ok>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-def>
400B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
416B		%vreg7<def> = COPY %W0; GPR32:%vreg7
432B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
448B		STACKMAP 1, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack4] LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack2](align=4)
464B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
480B		CBNZW %vreg7, <BB#2>; GPR32:%vreg7
	    Successors according to CFG: BB#2 BB#1

496B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
512B		%vreg13<def> = MOVi32imm 4294967287; GPR32:%vreg13
528B		STRWui %vreg13, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg13
544B		B <BB#17>
	    Successors according to CFG: BB#17

560B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0
576B		%vreg15<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg15
592B		CBNZX %vreg15, <BB#4>; GPR64:%vreg15
	    Successors according to CFG: BB#4 BB#3

608B	BB#3: derived from LLVM BB %if.then.1
	    Predecessors according to CFG: BB#2
624B		%vreg105<def> = MOVi32imm 4294967294; GPR32:%vreg105
640B		STRWui %vreg105, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg105
656B		B <BB#17>
	    Successors according to CFG: BB#17

672B	BB#4: derived from LLVM BB %if.end.2
	    Predecessors according to CFG: BB#2
688B		%vreg17<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg17
704B		CBZW %vreg17, <BB#7>; GPR32:%vreg17
	    Successors according to CFG: BB#7 BB#5

720B	BB#5: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#4
736B		%vreg19<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32common:%vreg19
752B		%WZR<def> = SUBSWri %vreg19, 1, 0, %NZCV<imp-def>; GPR32common:%vreg19
768B		Bcc 0, <BB#7>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#7 BB#6

784B	BB#6: derived from LLVM BB %if.then.5
	    Predecessors according to CFG: BB#5
800B		%vreg104<def> = MOVi32imm 4294967294; GPR32:%vreg104
816B		STRWui %vreg104, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg104
832B		B <BB#17>
	    Successors according to CFG: BB#17

848B	BB#7: derived from LLVM BB %if.end.6
	    Predecessors according to CFG: BB#4 BB#5
864B		%vreg21<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg21
880B		TBNZW %vreg21, 31, <BB#9>; GPR32:%vreg21
	    Successors according to CFG: BB#9 BB#8

896B	BB#8: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#7
912B		%vreg23<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32common:%vreg23
928B		%WZR<def> = SUBSWri %vreg23, 4, 0, %NZCV<imp-def>; GPR32common:%vreg23
944B		Bcc 13, <BB#10>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#10 BB#9

960B	BB#9: derived from LLVM BB %if.then.9
	    Predecessors according to CFG: BB#7 BB#8
976B		%vreg103<def> = MOVi32imm 4294967294; GPR32:%vreg103
992B		STRWui %vreg103, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg103
1008B		B <BB#17>
	    Successors according to CFG: BB#17

1024B	BB#10: derived from LLVM BB %if.end.10
	    Predecessors according to CFG: BB#8
1040B		%vreg27<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg27
1056B		%vreg26<def> = LDRXui %vreg27, 7; mem:LD8[%bzalloc] GPR64:%vreg26 GPR64common:%vreg27
1072B		CBNZX %vreg26, <BB#12>; GPR64:%vreg26
	    Successors according to CFG: BB#12 BB#11

1088B	BB#11: derived from LLVM BB %if.then.12
	    Predecessors according to CFG: BB#10
1104B		%vreg28<def> = ADRP <ga:@default_bzalloc>[TF=1]; GPR64common:%vreg28
1120B		%vreg29<def> = ADDXri %vreg28, <ga:@default_bzalloc>[TF=34], 0; GPR64common:%vreg29,%vreg28
1136B		%vreg31<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg31
1152B		STRXui %vreg29, %vreg31, 7; mem:ST8[%bzalloc13] GPR64common:%vreg29,%vreg31
	    Successors according to CFG: BB#12

1168B	BB#12: derived from LLVM BB %if.end.14
	    Predecessors according to CFG: BB#10 BB#11
1184B		%vreg35<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg35
1200B		%vreg34<def> = LDRXui %vreg35, 8; mem:LD8[%bzfree] GPR64:%vreg34 GPR64common:%vreg35
1216B		CBNZX %vreg34, <BB#14>; GPR64:%vreg34
	    Successors according to CFG: BB#14 BB#13

1232B	BB#13: derived from LLVM BB %if.then.16
	    Predecessors according to CFG: BB#12
1248B		%vreg36<def> = ADRP <ga:@default_bzfree>[TF=1]; GPR64common:%vreg36
1264B		%vreg37<def> = ADDXri %vreg36, <ga:@default_bzfree>[TF=34], 0; GPR64common:%vreg37,%vreg36
1280B		%vreg39<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg39
1296B		STRXui %vreg37, %vreg39, 8; mem:ST8[%bzfree17] GPR64common:%vreg37,%vreg39
	    Successors according to CFG: BB#14

1312B	BB#14: derived from LLVM BB %if.end.18
	    Predecessors according to CFG: BB#12 BB#13
1328B		%vreg47<def> = MOVi32imm 64144; GPR32:%vreg47
1344B		%vreg48<def> = MOVi32imm 1; GPR32:%vreg48
1360B		%vreg55<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg55
1376B		%vreg54<def> = LDRXui %vreg55, 7; mem:LD8[%bzalloc19] GPR64:%vreg54 GPR64common:%vreg55
1392B		%vreg52<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg52
1408B		%vreg51<def> = LDRXui %vreg52, 9; mem:LD8[%opaque] GPR64:%vreg51 GPR64common:%vreg52
1424B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1440B		%X0<def> = COPY %vreg51; GPR64:%vreg51
1456B		%W1<def> = COPY %vreg47; GPR32:%vreg47
1472B		%W2<def> = COPY %vreg48; GPR32:%vreg48
1488B		BLR %vreg54, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %W2<imp-use>, %X0<imp-def>; GPR64:%vreg54
1504B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1520B		%vreg49<def> = COPY %X0; GPR64all:%vreg49
1536B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1552B		STACKMAP 2, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack4] LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack2](align=4)
1568B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1584B		%vreg44<def> = COPY %vreg49; GPR64:%vreg44 GPR64all:%vreg49
1600B		STRXui %vreg44, <fi#4>, 0; mem:ST8[FixedStack4] GPR64:%vreg44
1616B		%vreg41<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64:%vreg41
1632B		CBNZX %vreg41, <BB#16>; GPR64:%vreg41
	    Successors according to CFG: BB#16 BB#15

1648B	BB#15: derived from LLVM BB %if.then.22
	    Predecessors according to CFG: BB#14
1664B		%vreg102<def> = MOVi32imm 4294967293; GPR32:%vreg102
1680B		STRWui %vreg102, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg102
1696B		B <BB#17>
	    Successors according to CFG: BB#17

1712B	BB#16: derived from LLVM BB %if.end.23
	    Predecessors according to CFG: BB#14
1728B		%vreg62<def> = COPY %XZR; GPR64:%vreg62
1744B		%vreg89<def> = MOVi32imm 10; GPR32:%vreg89
1760B		%vreg101<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg101
1776B		%vreg100<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg100
1792B		STRXui %vreg101, %vreg100, 0; mem:ST8[%strm24] GPR64:%vreg101 GPR64common:%vreg100
1808B		%vreg97<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64:%vreg97
1824B		%vreg96<def> = COPY %vreg97; GPR64:%vreg96,%vreg97
1840B		%vreg94<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg94
1856B		STRXui %vreg96, %vreg94, 6; mem:ST8[%state] GPR64:%vreg96 GPR64common:%vreg94
1872B		%vreg91<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg91
1888B		STRWui %vreg89, %vreg91, 2; mem:ST4[%state25] GPR32:%vreg89 GPR64common:%vreg91
1904B		%vreg88<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg88
1920B		STRWui %WZR, %vreg88, 9; mem:ST4[%bsLive] GPR64common:%vreg88
1936B		%vreg86<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg86
1952B		STRWui %WZR, %vreg86, 8; mem:ST4[%bsBuff] GPR64common:%vreg86
1968B		%vreg84<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg84
1984B		STRWui %WZR, %vreg84, 797; mem:ST4[%calculatedCombinedCRC] GPR64common:%vreg84
2000B		%vreg82<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg82
2016B		STRWui %WZR, %vreg82, 3; mem:ST4[%total_in_lo32] GPR64common:%vreg82
2032B		%vreg80<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg80
2048B		STRWui %WZR, %vreg80, 4; mem:ST4[%total_in_hi32] GPR64common:%vreg80
2064B		%vreg78<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg78
2080B		STRWui %WZR, %vreg78, 9; mem:ST4[%total_out_lo32] GPR64common:%vreg78
2096B		%vreg76<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg76
2112B		STRWui %WZR, %vreg76, 10; mem:ST4[%total_out_hi32] GPR64common:%vreg76
2128B		%vreg74<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg74
2144B		%vreg73<def> = COPY %vreg74; GPR32:%vreg73,%vreg74
2160B		%vreg71<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg71
2176B		STRBBui %vreg73, %vreg71, 44; mem:ST1[%smallDecompress] GPR32:%vreg73 GPR64common:%vreg71
2192B		%vreg68<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg68
2208B		STRXui %vreg62, %vreg68, 396; mem:ST8[%ll4] GPR64:%vreg62 GPR64common:%vreg68
2224B		%vreg66<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg66
2240B		STRXui %vreg62, %vreg66, 395; mem:ST8[%ll16] GPR64:%vreg62 GPR64common:%vreg66
2256B		%vreg64<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg64
2272B		STRXui %vreg62, %vreg64, 394; mem:ST8[%tt] GPR64:%vreg62 GPR64common:%vreg64
2288B		%vreg61<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg61
2304B		STRWui %WZR, %vreg61, 12; mem:ST4[%currBlockNo] GPR64common:%vreg61
2320B		%vreg59<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg59
2336B		%vreg58<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg58
2352B		STRWui %vreg59, %vreg58, 13; mem:ST4[%verbosity26] GPR32:%vreg59 GPR64common:%vreg58
2368B		STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
	    Successors according to CFG: BB#17

2384B	BB#17: derived from LLVM BB %return
	    Predecessors according to CFG: BB#1 BB#16 BB#15 BB#9 BB#6 BB#3
2400B		%vreg108<def> = ADRP <ga:@BZ2_bzDecompressInit>[TF=1]; GPR64common:%vreg108
2416B		%vreg109<def> = ADDXri %vreg108, <ga:@BZ2_bzDecompressInit>[TF=34], 0; GPR64sp:%vreg109 GPR64common:%vreg108
2432B		%vreg110<def> = COPY %vreg109; GPR64all:%vreg110 GPR64sp:%vreg109
2448B		%vreg111<def> = COPY %vreg12; GPR64all:%vreg111 GPR64:%vreg12
2464B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2480B		%X0<def> = COPY %vreg110; GPR64all:%vreg110
2496B		%X1<def> = COPY %vreg111; GPR64all:%vreg111
2512B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
2528B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2544B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2560B		STACKMAP 3, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
2576B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2592B		%vreg107<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0] GPR32:%vreg107
2608B		%W0<def> = COPY %vreg107; GPR32:%vreg107
2624B		RET_ReallyLR %W0<imp-use>

# End machine code for function BZ2_bzDecompressInit.

********** SIMPLE REGISTER COALESCING **********
********** Function: BZ2_bzDecompressInit
********** JOINING INTERVALS ***********
return:
2480B	%X0<def> = COPY %vreg110; GPR64all:%vreg110
	Considering merging %vreg110 with %X0
	Can only merge into reserved registers.
2496B	%X1<def> = COPY %vreg111; GPR64all:%vreg111
	Considering merging %vreg111 with %X1
	Can only merge into reserved registers.
2608B	%W0<def> = COPY %vreg107; GPR32:%vreg107
	Considering merging %vreg107 with %W0
	Can only merge into reserved registers.
if.end.6:
if.end.14:
if.end.18:
1440B	%X0<def> = COPY %vreg51; GPR64:%vreg51
	Considering merging %vreg51 with %X0
	Can only merge into reserved registers.
1456B	%W1<def> = COPY %vreg47; GPR32:%vreg47
	Considering merging %vreg47 with %W1
	Can only merge into reserved registers.
Remat: %W1<def> = MOVi32imm 64144
Shrink: %vreg47 [1328r,1456r:0)  0@1328r
All defs dead: 1328r	%vreg47<def,dead> = MOVi32imm 64144; GPR32:%vreg47
Shrunk: %vreg47 [1328r,1328d:0)  0@1328r
Deleting dead def 1328r	%vreg47<def,dead> = MOVi32imm 64144; GPR32:%vreg47
1472B	%W2<def> = COPY %vreg48; GPR32:%vreg48
	Considering merging %vreg48 with %W2
	Can only merge into reserved registers.
Remat: %W2<def> = MOVi32imm 1
Shrink: %vreg48 [1344r,1472r:0)  0@1344r
All defs dead: 1344r	%vreg48<def,dead> = MOVi32imm 1; GPR32:%vreg48
Shrunk: %vreg48 [1344r,1344d:0)  0@1344r
Deleting dead def 1344r	%vreg48<def,dead> = MOVi32imm 1; GPR32:%vreg48
1520B	%vreg49<def> = COPY %X0; GPR64all:%vreg49
	Considering merging %vreg49 with %X0
	Can only merge into reserved registers.
if.end:
if.end.2:
land.lhs.true:
lor.lhs.false:
if.then.9:
if.end.10:
entry:
16B	%vreg12<def> = COPY %LR; GPR64:%vreg12
	Considering merging %vreg12 with %LR
	Can only merge into reserved registers.
32B	%vreg4<def> = COPY %W2; GPR32:%vreg4
	Considering merging %vreg4 with %W2
	Can only merge into reserved registers.
48B	%vreg2<def> = COPY %W1; GPR32:%vreg2
	Considering merging %vreg2 with %W1
	Can only merge into reserved registers.
64B	%vreg0<def> = COPY %X0; GPR64:%vreg0
	Considering merging %vreg0 with %X0
	Can only merge into reserved registers.
208B	%X0<def> = COPY %vreg10; GPR64all:%vreg10
	Considering merging %vreg10 with %X0
	Can only merge into reserved registers.
224B	%X1<def> = COPY %vreg11; GPR64all:%vreg11
	Considering merging %vreg11 with %X1
	Can only merge into reserved registers.
416B	%vreg7<def> = COPY %W0; GPR32:%vreg7
	Considering merging %vreg7 with %W0
	Can only merge into reserved registers.
if.then:
if.then.1:
if.then.5:
if.then.12:
if.then.16:
if.then.22:
if.end.23:
1728B	%vreg62<def> = COPY %XZR; GPR64:%vreg62
	Considering merging %vreg62 with %XZR
		RHS = %vreg62 [1728r,2272r:0)  0@1728r
		updated: 2272B	STRXui %XZR, %vreg64, 394; mem:ST8[%tt] GPR64common:%vreg64
		updated: 2240B	STRXui %XZR, %vreg66, 395; mem:ST8[%ll16] GPR64common:%vreg66
		updated: 2208B	STRXui %XZR, %vreg68, 396; mem:ST8[%ll4] GPR64common:%vreg68
	Success: %vreg62 -> %XZR
	Result = %XZR
2432B	%vreg110<def> = COPY %vreg109; GPR64all:%vreg110 GPR64sp:%vreg109
	Considering merging to GPR64sp with %vreg109 in %vreg110
		RHS = %vreg109 [2416r,2432r:0)  0@2416r
		LHS = %vreg110 [2432r,2480r:0)  0@2432r
		merge %vreg110:0@2432r into %vreg109:0@2416r --> @2416r
		erased:	2432r	%vreg110<def> = COPY %vreg109; GPR64all:%vreg110 GPR64sp:%vreg109
		updated: 2416B	%vreg110<def> = ADDXri %vreg108, <ga:@BZ2_bzDecompressInit>[TF=34], 0; GPR64sp:%vreg110 GPR64common:%vreg108
	Success: %vreg109 -> %vreg110
	Result = %vreg110 [2416r,2480r:0)  0@2416r
2448B	%vreg111<def> = COPY %vreg12; GPR64all:%vreg111 GPR64:%vreg12
	Considering merging to GPR64 with %vreg12 in %vreg111
		RHS = %vreg12 [16r,2448r:0)  0@16r
		LHS = %vreg111 [2448r,2496r:0)  0@2448r
		merge %vreg111:0@2448r into %vreg12:0@16r --> @16r
		erased:	2448r	%vreg111<def> = COPY %vreg12; GPR64all:%vreg111 GPR64:%vreg12
		updated: 16B	%vreg111<def> = COPY %LR; GPR64:%vreg111
		updated: 176B	%vreg11<def> = COPY %vreg111; GPR64all:%vreg11 GPR64:%vreg111
	Success: %vreg12 -> %vreg111
	Result = %vreg111 [16r,2496r:0)  0@16r
1584B	%vreg44<def> = COPY %vreg49; GPR64:%vreg44 GPR64all:%vreg49
	Considering merging to GPR64 with %vreg49 in %vreg44
		RHS = %vreg49 [1520r,1584r:0)  0@1520r
		LHS = %vreg44 [1584r,1600r:0)  0@1584r
		merge %vreg44:0@1584r into %vreg49:0@1520r --> @1520r
		erased:	1584r	%vreg44<def> = COPY %vreg49; GPR64:%vreg44 GPR64all:%vreg49
		updated: 1520B	%vreg44<def> = COPY %X0; GPR64:%vreg44
	Success: %vreg49 -> %vreg44
	Result = %vreg44 [1520r,1600r:0)  0@1520r
80B	%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
	Considering merging to GPR64 with %vreg0 in %vreg1
		RHS = %vreg0 [64r,80r:0)  0@64r
		LHS = %vreg1 [80r,320r:0)  0@80r
		merge %vreg1:0@80r into %vreg0:0@64r --> @64r
		erased:	80r	%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
		updated: 64B	%vreg1<def> = COPY %X0; GPR64:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [64r,320r:0)  0@64r
96B	%vreg3<def> = COPY %vreg2; GPR32:%vreg3,%vreg2
	Considering merging to GPR32 with %vreg2 in %vreg3
		RHS = %vreg2 [48r,96r:0)  0@48r
		LHS = %vreg3 [96r,336r:0)  0@96r
		merge %vreg3:0@96r into %vreg2:0@48r --> @48r
		erased:	96r	%vreg3<def> = COPY %vreg2; GPR32:%vreg3,%vreg2
		updated: 48B	%vreg3<def> = COPY %W1; GPR32:%vreg3
	Success: %vreg2 -> %vreg3
	Result = %vreg3 [48r,336r:0)  0@48r
112B	%vreg5<def> = COPY %vreg4; GPR32:%vreg5,%vreg4
	Considering merging to GPR32 with %vreg4 in %vreg5
		RHS = %vreg4 [32r,112r:0)  0@32r
		LHS = %vreg5 [112r,352r:0)  0@112r
		merge %vreg5:0@112r into %vreg4:0@32r --> @32r
		erased:	112r	%vreg5<def> = COPY %vreg4; GPR32:%vreg5,%vreg4
		updated: 32B	%vreg5<def> = COPY %W2; GPR32:%vreg5
	Success: %vreg4 -> %vreg5
	Result = %vreg5 [32r,352r:0)  0@32r
160B	%vreg10<def> = COPY %vreg9; GPR64all:%vreg10 GPR64sp:%vreg9
	Considering merging to GPR64sp with %vreg9 in %vreg10
		RHS = %vreg9 [144r,160r:0)  0@144r
		LHS = %vreg10 [160r,208r:0)  0@160r
		merge %vreg10:0@160r into %vreg9:0@144r --> @144r
		erased:	160r	%vreg10<def> = COPY %vreg9; GPR64all:%vreg10 GPR64sp:%vreg9
		updated: 144B	%vreg10<def> = ADDXri %vreg8, <ga:@BZ2_bzDecompressInit>[TF=34], 0; GPR64sp:%vreg10 GPR64common:%vreg8
	Success: %vreg9 -> %vreg10
	Result = %vreg10 [144r,208r:0)  0@144r
176B	%vreg11<def> = COPY %vreg111; GPR64all:%vreg11 GPR64:%vreg111
	Considering merging to GPR64 with %vreg111 in %vreg11
		RHS = %vreg111 [16r,2496r:0)  0@16r
		LHS = %vreg11 [176r,224r:0)  0@176r
		merge %vreg11:0@176r into %vreg111:0@16r --> @16r
		erased:	176r	%vreg11<def> = COPY %vreg111; GPR64all:%vreg11 GPR64:%vreg111
		updated: 16B	%vreg11<def> = COPY %LR; GPR64:%vreg11
		updated: 2496B	%X1<def> = COPY %vreg11; GPR64:%vreg11
	Success: %vreg111 -> %vreg11
	Result = %vreg11 [16r,2496r:0)  0@16r
1824B	%vreg96<def> = COPY %vreg97; GPR64:%vreg96,%vreg97
	Considering merging to GPR64 with %vreg97 in %vreg96
		RHS = %vreg97 [1808r,1824r:0)  0@1808r
		LHS = %vreg96 [1824r,1856r:0)  0@1824r
		merge %vreg96:0@1824r into %vreg97:0@1808r --> @1808r
		erased:	1824r	%vreg96<def> = COPY %vreg97; GPR64:%vreg96,%vreg97
		updated: 1808B	%vreg96<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64:%vreg96
	Success: %vreg97 -> %vreg96
	Result = %vreg96 [1808r,1856r:0)  0@1808r
2144B	%vreg73<def> = COPY %vreg74; GPR32:%vreg73,%vreg74
	Considering merging to GPR32 with %vreg74 in %vreg73
		RHS = %vreg74 [2128r,2144r:0)  0@2128r
		LHS = %vreg73 [2144r,2176r:0)  0@2144r
		merge %vreg73:0@2144r into %vreg74:0@2128r --> @2128r
		erased:	2144r	%vreg73<def> = COPY %vreg74; GPR32:%vreg73,%vreg74
		updated: 2128B	%vreg73<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg73
	Success: %vreg74 -> %vreg73
	Result = %vreg73 [2128r,2176r:0)  0@2128r
2480B	%X0<def> = COPY %vreg110; GPR64sp:%vreg110
	Considering merging %vreg110 with %X0
	Can only merge into reserved registers.
2496B	%X1<def> = COPY %vreg11; GPR64:%vreg11
	Considering merging %vreg11 with %X1
	Can only merge into reserved registers.
208B	%X0<def> = COPY %vreg10; GPR64sp:%vreg10
	Considering merging %vreg10 with %X0
	Can only merge into reserved registers.
224B	%X1<def> = COPY %vreg11; GPR64:%vreg11
	Considering merging %vreg11 with %X1
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
W30 [0B,16r:0)[240r,240d:7)[288e,288d:4)[384r,384d:8)[448e,448d:3)[1488r,1488d:6)[1552e,1552d:2)[2512r,2512d:5)[2560e,2560d:1)  0@0B-phi 1@2560e 2@1552e 3@448e 4@288e 5@2512r 6@1488r 7@240r 8@384r
WZR [752r,752d:1)[928r,928d:0)  0@928r 1@752r
W0 [0B,64r:0)[208r,240r:6)[384r,416r:2)[1440r,1488r:5)[1488r,1520r:4)[2480r,2512r:3)[2608r,2624r:1)  0@0B-phi 1@2608r 2@384r 3@2480r 4@1488r 5@1440r 6@208r
W1 [0B,48r:0)[224r,240r:3)[1456r,1488r:1)[2496r,2512r:2)  0@0B-phi 1@1456r 2@2496r 3@224r
W2 [0B,32r:0)[1472r,1488r:1)  0@0B-phi 1@1472r
%vreg1 [64r,320r:0)  0@64r
%vreg3 [48r,336r:0)  0@48r
%vreg5 [32r,352r:0)  0@32r
%vreg7 [416r,480r:0)  0@416r
%vreg8 [128r,144r:0)  0@128r
%vreg10 [144r,208r:0)  0@144r
%vreg11 [16r,2496r:0)  0@16r
%vreg13 [512r,528r:0)  0@512r
%vreg15 [576r,592r:0)  0@576r
%vreg17 [688r,704r:0)  0@688r
%vreg19 [736r,752r:0)  0@736r
%vreg21 [864r,880r:0)  0@864r
%vreg23 [912r,928r:0)  0@912r
%vreg26 [1056r,1072r:0)  0@1056r
%vreg27 [1040r,1056r:0)  0@1040r
%vreg28 [1104r,1120r:0)  0@1104r
%vreg29 [1120r,1152r:0)  0@1120r
%vreg31 [1136r,1152r:0)  0@1136r
%vreg34 [1200r,1216r:0)  0@1200r
%vreg35 [1184r,1200r:0)  0@1184r
%vreg36 [1248r,1264r:0)  0@1248r
%vreg37 [1264r,1296r:0)  0@1264r
%vreg39 [1280r,1296r:0)  0@1280r
%vreg41 [1616r,1632r:0)  0@1616r
%vreg44 [1520r,1600r:0)  0@1520r
%vreg51 [1408r,1440r:0)  0@1408r
%vreg52 [1392r,1408r:0)  0@1392r
%vreg54 [1376r,1488r:0)  0@1376r
%vreg55 [1360r,1376r:0)  0@1360r
%vreg58 [2336r,2352r:0)  0@2336r
%vreg59 [2320r,2352r:0)  0@2320r
%vreg61 [2288r,2304r:0)  0@2288r
%vreg64 [2256r,2272r:0)  0@2256r
%vreg66 [2224r,2240r:0)  0@2224r
%vreg68 [2192r,2208r:0)  0@2192r
%vreg71 [2160r,2176r:0)  0@2160r
%vreg73 [2128r,2176r:0)  0@2128r
%vreg76 [2096r,2112r:0)  0@2096r
%vreg78 [2064r,2080r:0)  0@2064r
%vreg80 [2032r,2048r:0)  0@2032r
%vreg82 [2000r,2016r:0)  0@2000r
%vreg84 [1968r,1984r:0)  0@1968r
%vreg86 [1936r,1952r:0)  0@1936r
%vreg88 [1904r,1920r:0)  0@1904r
%vreg89 [1744r,1888r:0)  0@1744r
%vreg91 [1872r,1888r:0)  0@1872r
%vreg94 [1840r,1856r:0)  0@1840r
%vreg96 [1808r,1856r:0)  0@1808r
%vreg100 [1776r,1792r:0)  0@1776r
%vreg101 [1760r,1792r:0)  0@1760r
%vreg102 [1664r,1680r:0)  0@1664r
%vreg103 [976r,992r:0)  0@976r
%vreg104 [800r,816r:0)  0@800r
%vreg105 [624r,640r:0)  0@624r
%vreg107 [2592r,2608r:0)  0@2592r
%vreg108 [2400r,2416r:0)  0@2400r
%vreg110 [2416r,2480r:0)  0@2416r
RegMasks: 240r 384r 1488r 2512r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzDecompressInit: Post SSA
Frame Objects:
  fi#0: size=4, align=4, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=4, align=4, at location [SP]
  fi#3: size=4, align=4, at location [SP]
  fi#4: size=8, align=8, at location [SP]
Function Live Ins: %X0 in %vreg0, %W1 in %vreg2, %W2 in %vreg4, %LR in %vreg12

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %W1 %W2 %LR
16B		%vreg11<def> = COPY %LR; GPR64:%vreg11
32B		%vreg5<def> = COPY %W2; GPR32:%vreg5
48B		%vreg3<def> = COPY %W1; GPR32:%vreg3
64B		%vreg1<def> = COPY %X0; GPR64:%vreg1
128B		%vreg8<def> = ADRP <ga:@BZ2_bzDecompressInit>[TF=1]; GPR64common:%vreg8
144B		%vreg10<def> = ADDXri %vreg8, <ga:@BZ2_bzDecompressInit>[TF=34], 0; GPR64sp:%vreg10 GPR64common:%vreg8
192B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
208B		%X0<def> = COPY %vreg10; GPR64sp:%vreg10
224B		%X1<def> = COPY %vreg11; GPR64:%vreg11
240B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
256B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
272B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
288B		STACKMAP 0, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, %vreg5, 0, <fi#3>, 0, %vreg1, 0, <fi#1>, 0, %vreg3, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack4] LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack2](align=4) GPR32:%vreg5,%vreg3 GPR64:%vreg1
304B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
320B		STRXui %vreg1, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg1
336B		STRWui %vreg3, <fi#2>, 0; mem:ST4[FixedStack2] GPR32:%vreg3
352B		STRWui %vreg5, <fi#3>, 0; mem:ST4[FixedStack3] GPR32:%vreg5
368B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
384B		BL <ga:@bz_config_ok>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-def>
400B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
416B		%vreg7<def> = COPY %W0; GPR32:%vreg7
432B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
448B		STACKMAP 1, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack4] LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack2](align=4)
464B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
480B		CBNZW %vreg7, <BB#2>; GPR32:%vreg7
	    Successors according to CFG: BB#2 BB#1

496B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
512B		%vreg13<def> = MOVi32imm 4294967287; GPR32:%vreg13
528B		STRWui %vreg13, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg13
544B		B <BB#17>
	    Successors according to CFG: BB#17

560B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0
576B		%vreg15<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg15
592B		CBNZX %vreg15, <BB#4>; GPR64:%vreg15
	    Successors according to CFG: BB#4 BB#3

608B	BB#3: derived from LLVM BB %if.then.1
	    Predecessors according to CFG: BB#2
624B		%vreg105<def> = MOVi32imm 4294967294; GPR32:%vreg105
640B		STRWui %vreg105, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg105
656B		B <BB#17>
	    Successors according to CFG: BB#17

672B	BB#4: derived from LLVM BB %if.end.2
	    Predecessors according to CFG: BB#2
688B		%vreg17<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg17
704B		CBZW %vreg17, <BB#7>; GPR32:%vreg17
	    Successors according to CFG: BB#7 BB#5

720B	BB#5: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#4
736B		%vreg19<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32common:%vreg19
752B		%WZR<def> = SUBSWri %vreg19, 1, 0, %NZCV<imp-def>; GPR32common:%vreg19
768B		Bcc 0, <BB#7>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#7 BB#6

784B	BB#6: derived from LLVM BB %if.then.5
	    Predecessors according to CFG: BB#5
800B		%vreg104<def> = MOVi32imm 4294967294; GPR32:%vreg104
816B		STRWui %vreg104, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg104
832B		B <BB#17>
	    Successors according to CFG: BB#17

848B	BB#7: derived from LLVM BB %if.end.6
	    Predecessors according to CFG: BB#4 BB#5
864B		%vreg21<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg21
880B		TBNZW %vreg21, 31, <BB#9>; GPR32:%vreg21
	    Successors according to CFG: BB#9 BB#8

896B	BB#8: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#7
912B		%vreg23<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32common:%vreg23
928B		%WZR<def> = SUBSWri %vreg23, 4, 0, %NZCV<imp-def>; GPR32common:%vreg23
944B		Bcc 13, <BB#10>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#10 BB#9

960B	BB#9: derived from LLVM BB %if.then.9
	    Predecessors according to CFG: BB#7 BB#8
976B		%vreg103<def> = MOVi32imm 4294967294; GPR32:%vreg103
992B		STRWui %vreg103, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg103
1008B		B <BB#17>
	    Successors according to CFG: BB#17

1024B	BB#10: derived from LLVM BB %if.end.10
	    Predecessors according to CFG: BB#8
1040B		%vreg27<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg27
1056B		%vreg26<def> = LDRXui %vreg27, 7; mem:LD8[%bzalloc] GPR64:%vreg26 GPR64common:%vreg27
1072B		CBNZX %vreg26, <BB#12>; GPR64:%vreg26
	    Successors according to CFG: BB#12 BB#11

1088B	BB#11: derived from LLVM BB %if.then.12
	    Predecessors according to CFG: BB#10
1104B		%vreg28<def> = ADRP <ga:@default_bzalloc>[TF=1]; GPR64common:%vreg28
1120B		%vreg29<def> = ADDXri %vreg28, <ga:@default_bzalloc>[TF=34], 0; GPR64common:%vreg29,%vreg28
1136B		%vreg31<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg31
1152B		STRXui %vreg29, %vreg31, 7; mem:ST8[%bzalloc13] GPR64common:%vreg29,%vreg31
	    Successors according to CFG: BB#12

1168B	BB#12: derived from LLVM BB %if.end.14
	    Predecessors according to CFG: BB#10 BB#11
1184B		%vreg35<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg35
1200B		%vreg34<def> = LDRXui %vreg35, 8; mem:LD8[%bzfree] GPR64:%vreg34 GPR64common:%vreg35
1216B		CBNZX %vreg34, <BB#14>; GPR64:%vreg34
	    Successors according to CFG: BB#14 BB#13

1232B	BB#13: derived from LLVM BB %if.then.16
	    Predecessors according to CFG: BB#12
1248B		%vreg36<def> = ADRP <ga:@default_bzfree>[TF=1]; GPR64common:%vreg36
1264B		%vreg37<def> = ADDXri %vreg36, <ga:@default_bzfree>[TF=34], 0; GPR64common:%vreg37,%vreg36
1280B		%vreg39<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg39
1296B		STRXui %vreg37, %vreg39, 8; mem:ST8[%bzfree17] GPR64common:%vreg37,%vreg39
	    Successors according to CFG: BB#14

1312B	BB#14: derived from LLVM BB %if.end.18
	    Predecessors according to CFG: BB#12 BB#13
1360B		%vreg55<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg55
1376B		%vreg54<def> = LDRXui %vreg55, 7; mem:LD8[%bzalloc19] GPR64:%vreg54 GPR64common:%vreg55
1392B		%vreg52<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg52
1408B		%vreg51<def> = LDRXui %vreg52, 9; mem:LD8[%opaque] GPR64:%vreg51 GPR64common:%vreg52
1424B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1440B		%X0<def> = COPY %vreg51; GPR64:%vreg51
1456B		%W1<def> = MOVi32imm 64144
1472B		%W2<def> = MOVi32imm 1
1488B		BLR %vreg54, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %W2<imp-use>, %X0<imp-def>; GPR64:%vreg54
1504B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1520B		%vreg44<def> = COPY %X0; GPR64:%vreg44
1536B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1552B		STACKMAP 2, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack4] LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack2](align=4)
1568B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1600B		STRXui %vreg44, <fi#4>, 0; mem:ST8[FixedStack4] GPR64:%vreg44
1616B		%vreg41<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64:%vreg41
1632B		CBNZX %vreg41, <BB#16>; GPR64:%vreg41
	    Successors according to CFG: BB#16 BB#15

1648B	BB#15: derived from LLVM BB %if.then.22
	    Predecessors according to CFG: BB#14
1664B		%vreg102<def> = MOVi32imm 4294967293; GPR32:%vreg102
1680B		STRWui %vreg102, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg102
1696B		B <BB#17>
	    Successors according to CFG: BB#17

1712B	BB#16: derived from LLVM BB %if.end.23
	    Predecessors according to CFG: BB#14
1744B		%vreg89<def> = MOVi32imm 10; GPR32:%vreg89
1760B		%vreg101<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg101
1776B		%vreg100<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg100
1792B		STRXui %vreg101, %vreg100, 0; mem:ST8[%strm24] GPR64:%vreg101 GPR64common:%vreg100
1808B		%vreg96<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64:%vreg96
1840B		%vreg94<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg94
1856B		STRXui %vreg96, %vreg94, 6; mem:ST8[%state] GPR64:%vreg96 GPR64common:%vreg94
1872B		%vreg91<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg91
1888B		STRWui %vreg89, %vreg91, 2; mem:ST4[%state25] GPR32:%vreg89 GPR64common:%vreg91
1904B		%vreg88<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg88
1920B		STRWui %WZR, %vreg88, 9; mem:ST4[%bsLive] GPR64common:%vreg88
1936B		%vreg86<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg86
1952B		STRWui %WZR, %vreg86, 8; mem:ST4[%bsBuff] GPR64common:%vreg86
1968B		%vreg84<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg84
1984B		STRWui %WZR, %vreg84, 797; mem:ST4[%calculatedCombinedCRC] GPR64common:%vreg84
2000B		%vreg82<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg82
2016B		STRWui %WZR, %vreg82, 3; mem:ST4[%total_in_lo32] GPR64common:%vreg82
2032B		%vreg80<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg80
2048B		STRWui %WZR, %vreg80, 4; mem:ST4[%total_in_hi32] GPR64common:%vreg80
2064B		%vreg78<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg78
2080B		STRWui %WZR, %vreg78, 9; mem:ST4[%total_out_lo32] GPR64common:%vreg78
2096B		%vreg76<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg76
2112B		STRWui %WZR, %vreg76, 10; mem:ST4[%total_out_hi32] GPR64common:%vreg76
2128B		%vreg73<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg73
2160B		%vreg71<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg71
2176B		STRBBui %vreg73, %vreg71, 44; mem:ST1[%smallDecompress] GPR32:%vreg73 GPR64common:%vreg71
2192B		%vreg68<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg68
2208B		STRXui %XZR, %vreg68, 396; mem:ST8[%ll4] GPR64common:%vreg68
2224B		%vreg66<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg66
2240B		STRXui %XZR, %vreg66, 395; mem:ST8[%ll16] GPR64common:%vreg66
2256B		%vreg64<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg64
2272B		STRXui %XZR, %vreg64, 394; mem:ST8[%tt] GPR64common:%vreg64
2288B		%vreg61<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg61
2304B		STRWui %WZR, %vreg61, 12; mem:ST4[%currBlockNo] GPR64common:%vreg61
2320B		%vreg59<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg59
2336B		%vreg58<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg58
2352B		STRWui %vreg59, %vreg58, 13; mem:ST4[%verbosity26] GPR32:%vreg59 GPR64common:%vreg58
2368B		STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
	    Successors according to CFG: BB#17

2384B	BB#17: derived from LLVM BB %return
	    Predecessors according to CFG: BB#1 BB#16 BB#15 BB#9 BB#6 BB#3
2400B		%vreg108<def> = ADRP <ga:@BZ2_bzDecompressInit>[TF=1]; GPR64common:%vreg108
2416B		%vreg110<def> = ADDXri %vreg108, <ga:@BZ2_bzDecompressInit>[TF=34], 0; GPR64sp:%vreg110 GPR64common:%vreg108
2464B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2480B		%X0<def> = COPY %vreg110; GPR64sp:%vreg110
2496B		%X1<def> = COPY %vreg11; GPR64:%vreg11
2512B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
2528B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2544B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2560B		STACKMAP 3, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
2576B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2592B		%vreg107<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0] GPR32:%vreg107
2608B		%W0<def> = COPY %vreg107; GPR32:%vreg107
2624B		RET_ReallyLR %W0<imp-use>

# End machine code for function BZ2_bzDecompressInit.

handleMove 1120B -> 1144B: %vreg29<def> = ADDXri %vreg28, <ga:@default_bzalloc>[TF=34], 0; GPR64common:%vreg29,%vreg28
     %vreg29:	[1120r,1152r:0)  0@1120r
        -->	[1144r,1152r:0)  0@1144r
     %vreg28:	[1104r,1120r:0)  0@1104r
        -->	[1104r,1144r:0)  0@1104r
handleMove 1104B -> 1140B: %vreg28<def> = ADRP <ga:@default_bzalloc>[TF=1]; GPR64common:%vreg28
     %vreg28:	[1104r,1144r:0)  0@1104r
        -->	[1140r,1144r:0)  0@1140r
handleMove 1264B -> 1288B: %vreg37<def> = ADDXri %vreg36, <ga:@default_bzfree>[TF=34], 0; GPR64common:%vreg37,%vreg36
     %vreg37:	[1264r,1296r:0)  0@1264r
        -->	[1288r,1296r:0)  0@1288r
     %vreg36:	[1248r,1264r:0)  0@1248r
        -->	[1248r,1288r:0)  0@1248r
handleMove 1248B -> 1284B: %vreg36<def> = ADRP <ga:@default_bzfree>[TF=1]; GPR64common:%vreg36
     %vreg36:	[1248r,1288r:0)  0@1248r
        -->	[1284r,1288r:0)  0@1284r
handleMove 1440B -> 1480B: %X0<def> = COPY %vreg51; GPR64:%vreg51
     W0:	[0B,64r:0)[208r,240r:6)[384r,416r:2)[1440r,1488r:5)[1488r,1520r:4)[2480r,2512r:3)[2608r,2624r:1)  0@0B-phi 1@2608r 2@384r 3@2480r 4@1488r 5@1440r 6@208r
        -->	[0B,64r:0)[208r,240r:6)[384r,416r:2)[1480r,1488r:5)[1488r,1520r:4)[2480r,2512r:3)[2608r,2624r:1)  0@0B-phi 1@2608r 2@384r 3@2480r 4@1488r 5@1480r 6@208r
     %vreg51:	[1408r,1440r:0)  0@1408r
        -->	[1408r,1480r:0)  0@1408r
handleMove 1376B -> 1400B: %vreg54<def> = LDRXui %vreg55, 7; mem:LD8[%bzalloc19] GPR64:%vreg54 GPR64common:%vreg55
     %vreg54:	[1376r,1488r:0)  0@1376r
        -->	[1400r,1488r:0)  0@1400r
     %vreg55:	[1360r,1376r:0)  0@1360r
        -->	[1360r,1400r:0)  0@1360r
AllocationOrder(GPR32sponly) = [ ]
handleMove 1744B -> 1880B: %vreg89<def> = MOVi32imm 10; GPR32:%vreg89
     %vreg89:	[1744r,1888r:0)  0@1744r
        -->	[1880r,1888r:0)  0@1880r
********** GREEDY REGISTER ALLOCATION **********
********** Function: BZ2_bzDecompressInit
********** INTERVALS **********
W30 [0B,16r:0)[240r,240d:7)[288e,288d:4)[384r,384d:8)[448e,448d:3)[1488r,1488d:6)[1552e,1552d:2)[2512r,2512d:5)[2560e,2560d:1)  0@0B-phi 1@2560e 2@1552e 3@448e 4@288e 5@2512r 6@1488r 7@240r 8@384r
WZR [752r,752d:1)[928r,928d:0)  0@928r 1@752r
W0 [0B,64r:0)[208r,240r:6)[384r,416r:2)[1480r,1488r:5)[1488r,1520r:4)[2480r,2512r:3)[2608r,2624r:1)  0@0B-phi 1@2608r 2@384r 3@2480r 4@1488r 5@1480r 6@208r
W1 [0B,48r:0)[224r,240r:3)[1456r,1488r:1)[2496r,2512r:2)  0@0B-phi 1@1456r 2@2496r 3@224r
W2 [0B,32r:0)[1472r,1488r:1)  0@0B-phi 1@1472r
%vreg1 [64r,320r:0)  0@64r
%vreg3 [48r,336r:0)  0@48r
%vreg5 [32r,352r:0)  0@32r
%vreg7 [416r,480r:0)  0@416r
%vreg8 [128r,144r:0)  0@128r
%vreg10 [144r,208r:0)  0@144r
%vreg11 [16r,2496r:0)  0@16r
%vreg13 [512r,528r:0)  0@512r
%vreg15 [576r,592r:0)  0@576r
%vreg17 [688r,704r:0)  0@688r
%vreg19 [736r,752r:0)  0@736r
%vreg21 [864r,880r:0)  0@864r
%vreg23 [912r,928r:0)  0@912r
%vreg26 [1056r,1072r:0)  0@1056r
%vreg27 [1040r,1056r:0)  0@1040r
%vreg28 [1140r,1144r:0)  0@1140r
%vreg29 [1144r,1152r:0)  0@1144r
%vreg31 [1136r,1152r:0)  0@1136r
%vreg34 [1200r,1216r:0)  0@1200r
%vreg35 [1184r,1200r:0)  0@1184r
%vreg36 [1284r,1288r:0)  0@1284r
%vreg37 [1288r,1296r:0)  0@1288r
%vreg39 [1280r,1296r:0)  0@1280r
%vreg41 [1616r,1632r:0)  0@1616r
%vreg44 [1520r,1600r:0)  0@1520r
%vreg51 [1408r,1480r:0)  0@1408r
%vreg52 [1392r,1408r:0)  0@1392r
%vreg54 [1400r,1488r:0)  0@1400r
%vreg55 [1360r,1400r:0)  0@1360r
%vreg58 [2336r,2352r:0)  0@2336r
%vreg59 [2320r,2352r:0)  0@2320r
%vreg61 [2288r,2304r:0)  0@2288r
%vreg64 [2256r,2272r:0)  0@2256r
%vreg66 [2224r,2240r:0)  0@2224r
%vreg68 [2192r,2208r:0)  0@2192r
%vreg71 [2160r,2176r:0)  0@2160r
%vreg73 [2128r,2176r:0)  0@2128r
%vreg76 [2096r,2112r:0)  0@2096r
%vreg78 [2064r,2080r:0)  0@2064r
%vreg80 [2032r,2048r:0)  0@2032r
%vreg82 [2000r,2016r:0)  0@2000r
%vreg84 [1968r,1984r:0)  0@1968r
%vreg86 [1936r,1952r:0)  0@1936r
%vreg88 [1904r,1920r:0)  0@1904r
%vreg89 [1880r,1888r:0)  0@1880r
%vreg91 [1872r,1888r:0)  0@1872r
%vreg94 [1840r,1856r:0)  0@1840r
%vreg96 [1808r,1856r:0)  0@1808r
%vreg100 [1776r,1792r:0)  0@1776r
%vreg101 [1760r,1792r:0)  0@1760r
%vreg102 [1664r,1680r:0)  0@1664r
%vreg103 [976r,992r:0)  0@976r
%vreg104 [800r,816r:0)  0@800r
%vreg105 [624r,640r:0)  0@624r
%vreg107 [2592r,2608r:0)  0@2592r
%vreg108 [2400r,2416r:0)  0@2400r
%vreg110 [2416r,2480r:0)  0@2416r
RegMasks: 240r 384r 1488r 2512r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzDecompressInit: Post SSA
Frame Objects:
  fi#0: size=4, align=4, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=4, align=4, at location [SP]
  fi#3: size=4, align=4, at location [SP]
  fi#4: size=8, align=8, at location [SP]
Function Live Ins: %X0 in %vreg0, %W1 in %vreg2, %W2 in %vreg4, %LR in %vreg12

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %W1 %W2 %LR
16B		%vreg11<def> = COPY %LR; GPR64:%vreg11
32B		%vreg5<def> = COPY %W2; GPR32:%vreg5
48B		%vreg3<def> = COPY %W1; GPR32:%vreg3
64B		%vreg1<def> = COPY %X0; GPR64:%vreg1
128B		%vreg8<def> = ADRP <ga:@BZ2_bzDecompressInit>[TF=1]; GPR64common:%vreg8
144B		%vreg10<def> = ADDXri %vreg8, <ga:@BZ2_bzDecompressInit>[TF=34], 0; GPR64sp:%vreg10 GPR64common:%vreg8
192B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
208B		%X0<def> = COPY %vreg10; GPR64sp:%vreg10
224B		%X1<def> = COPY %vreg11; GPR64:%vreg11
240B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
256B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
272B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
288B		STACKMAP 0, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, %vreg5, 0, <fi#3>, 0, %vreg1, 0, <fi#1>, 0, %vreg3, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack4] LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack2](align=4) GPR32:%vreg5,%vreg3 GPR64:%vreg1
304B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
320B		STRXui %vreg1, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg1
336B		STRWui %vreg3, <fi#2>, 0; mem:ST4[FixedStack2] GPR32:%vreg3
352B		STRWui %vreg5, <fi#3>, 0; mem:ST4[FixedStack3] GPR32:%vreg5
368B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
384B		BL <ga:@bz_config_ok>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-def>
400B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
416B		%vreg7<def> = COPY %W0; GPR32:%vreg7
432B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
448B		STACKMAP 1, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack4] LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack2](align=4)
464B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
480B		CBNZW %vreg7, <BB#2>; GPR32:%vreg7
	    Successors according to CFG: BB#2 BB#1

496B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
512B		%vreg13<def> = MOVi32imm 4294967287; GPR32:%vreg13
528B		STRWui %vreg13, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg13
544B		B <BB#17>
	    Successors according to CFG: BB#17

560B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0
576B		%vreg15<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg15
592B		CBNZX %vreg15, <BB#4>; GPR64:%vreg15
	    Successors according to CFG: BB#4 BB#3

608B	BB#3: derived from LLVM BB %if.then.1
	    Predecessors according to CFG: BB#2
624B		%vreg105<def> = MOVi32imm 4294967294; GPR32:%vreg105
640B		STRWui %vreg105, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg105
656B		B <BB#17>
	    Successors according to CFG: BB#17

672B	BB#4: derived from LLVM BB %if.end.2
	    Predecessors according to CFG: BB#2
688B		%vreg17<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg17
704B		CBZW %vreg17, <BB#7>; GPR32:%vreg17
	    Successors according to CFG: BB#7 BB#5

720B	BB#5: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#4
736B		%vreg19<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32common:%vreg19
752B		%WZR<def> = SUBSWri %vreg19, 1, 0, %NZCV<imp-def>; GPR32common:%vreg19
768B		Bcc 0, <BB#7>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#7 BB#6

784B	BB#6: derived from LLVM BB %if.then.5
	    Predecessors according to CFG: BB#5
800B		%vreg104<def> = MOVi32imm 4294967294; GPR32:%vreg104
816B		STRWui %vreg104, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg104
832B		B <BB#17>
	    Successors according to CFG: BB#17

848B	BB#7: derived from LLVM BB %if.end.6
	    Predecessors according to CFG: BB#4 BB#5
864B		%vreg21<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg21
880B		TBNZW %vreg21, 31, <BB#9>; GPR32:%vreg21
	    Successors according to CFG: BB#9 BB#8

896B	BB#8: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#7
912B		%vreg23<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32common:%vreg23
928B		%WZR<def> = SUBSWri %vreg23, 4, 0, %NZCV<imp-def>; GPR32common:%vreg23
944B		Bcc 13, <BB#10>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#10 BB#9

960B	BB#9: derived from LLVM BB %if.then.9
	    Predecessors according to CFG: BB#7 BB#8
976B		%vreg103<def> = MOVi32imm 4294967294; GPR32:%vreg103
992B		STRWui %vreg103, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg103
1008B		B <BB#17>
	    Successors according to CFG: BB#17

1024B	BB#10: derived from LLVM BB %if.end.10
	    Predecessors according to CFG: BB#8
1040B		%vreg27<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg27
1056B		%vreg26<def> = LDRXui %vreg27, 7; mem:LD8[%bzalloc] GPR64:%vreg26 GPR64common:%vreg27
1072B		CBNZX %vreg26, <BB#12>; GPR64:%vreg26
	    Successors according to CFG: BB#12 BB#11

1088B	BB#11: derived from LLVM BB %if.then.12
	    Predecessors according to CFG: BB#10
1136B		%vreg31<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg31
1140B		%vreg28<def> = ADRP <ga:@default_bzalloc>[TF=1]; GPR64common:%vreg28
1144B		%vreg29<def> = ADDXri %vreg28, <ga:@default_bzalloc>[TF=34], 0; GPR64common:%vreg29,%vreg28
1152B		STRXui %vreg29, %vreg31, 7; mem:ST8[%bzalloc13] GPR64common:%vreg29,%vreg31
	    Successors according to CFG: BB#12

1168B	BB#12: derived from LLVM BB %if.end.14
	    Predecessors according to CFG: BB#10 BB#11
1184B		%vreg35<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg35
1200B		%vreg34<def> = LDRXui %vreg35, 8; mem:LD8[%bzfree] GPR64:%vreg34 GPR64common:%vreg35
1216B		CBNZX %vreg34, <BB#14>; GPR64:%vreg34
	    Successors according to CFG: BB#14 BB#13

1232B	BB#13: derived from LLVM BB %if.then.16
	    Predecessors according to CFG: BB#12
1280B		%vreg39<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg39
1284B		%vreg36<def> = ADRP <ga:@default_bzfree>[TF=1]; GPR64common:%vreg36
1288B		%vreg37<def> = ADDXri %vreg36, <ga:@default_bzfree>[TF=34], 0; GPR64common:%vreg37,%vreg36
1296B		STRXui %vreg37, %vreg39, 8; mem:ST8[%bzfree17] GPR64common:%vreg37,%vreg39
	    Successors according to CFG: BB#14

1312B	BB#14: derived from LLVM BB %if.end.18
	    Predecessors according to CFG: BB#12 BB#13
1360B		%vreg55<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg55
1392B		%vreg52<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg52
1400B		%vreg54<def> = LDRXui %vreg55, 7; mem:LD8[%bzalloc19] GPR64:%vreg54 GPR64common:%vreg55
1408B		%vreg51<def> = LDRXui %vreg52, 9; mem:LD8[%opaque] GPR64:%vreg51 GPR64common:%vreg52
1424B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1456B		%W1<def> = MOVi32imm 64144
1472B		%W2<def> = MOVi32imm 1
1480B		%X0<def> = COPY %vreg51; GPR64:%vreg51
1488B		BLR %vreg54, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %W2<imp-use>, %X0<imp-def>; GPR64:%vreg54
1504B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1520B		%vreg44<def> = COPY %X0; GPR64:%vreg44
1536B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1552B		STACKMAP 2, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack4] LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack2](align=4)
1568B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1600B		STRXui %vreg44, <fi#4>, 0; mem:ST8[FixedStack4] GPR64:%vreg44
1616B		%vreg41<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64:%vreg41
1632B		CBNZX %vreg41, <BB#16>; GPR64:%vreg41
	    Successors according to CFG: BB#16 BB#15

1648B	BB#15: derived from LLVM BB %if.then.22
	    Predecessors according to CFG: BB#14
1664B		%vreg102<def> = MOVi32imm 4294967293; GPR32:%vreg102
1680B		STRWui %vreg102, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg102
1696B		B <BB#17>
	    Successors according to CFG: BB#17

1712B	BB#16: derived from LLVM BB %if.end.23
	    Predecessors according to CFG: BB#14
1760B		%vreg101<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg101
1776B		%vreg100<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg100
1792B		STRXui %vreg101, %vreg100, 0; mem:ST8[%strm24] GPR64:%vreg101 GPR64common:%vreg100
1808B		%vreg96<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64:%vreg96
1840B		%vreg94<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg94
1856B		STRXui %vreg96, %vreg94, 6; mem:ST8[%state] GPR64:%vreg96 GPR64common:%vreg94
1872B		%vreg91<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg91
1880B		%vreg89<def> = MOVi32imm 10; GPR32:%vreg89
1888B		STRWui %vreg89, %vreg91, 2; mem:ST4[%state25] GPR32:%vreg89 GPR64common:%vreg91
1904B		%vreg88<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg88
1920B		STRWui %WZR, %vreg88, 9; mem:ST4[%bsLive] GPR64common:%vreg88
1936B		%vreg86<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg86
1952B		STRWui %WZR, %vreg86, 8; mem:ST4[%bsBuff] GPR64common:%vreg86
1968B		%vreg84<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg84
1984B		STRWui %WZR, %vreg84, 797; mem:ST4[%calculatedCombinedCRC] GPR64common:%vreg84
2000B		%vreg82<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg82
2016B		STRWui %WZR, %vreg82, 3; mem:ST4[%total_in_lo32] GPR64common:%vreg82
2032B		%vreg80<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg80
2048B		STRWui %WZR, %vreg80, 4; mem:ST4[%total_in_hi32] GPR64common:%vreg80
2064B		%vreg78<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg78
2080B		STRWui %WZR, %vreg78, 9; mem:ST4[%total_out_lo32] GPR64common:%vreg78
2096B		%vreg76<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg76
2112B		STRWui %WZR, %vreg76, 10; mem:ST4[%total_out_hi32] GPR64common:%vreg76
2128B		%vreg73<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg73
2160B		%vreg71<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg71
2176B		STRBBui %vreg73, %vreg71, 44; mem:ST1[%smallDecompress] GPR32:%vreg73 GPR64common:%vreg71
2192B		%vreg68<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg68
2208B		STRXui %XZR, %vreg68, 396; mem:ST8[%ll4] GPR64common:%vreg68
2224B		%vreg66<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg66
2240B		STRXui %XZR, %vreg66, 395; mem:ST8[%ll16] GPR64common:%vreg66
2256B		%vreg64<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg64
2272B		STRXui %XZR, %vreg64, 394; mem:ST8[%tt] GPR64common:%vreg64
2288B		%vreg61<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg61
2304B		STRWui %WZR, %vreg61, 12; mem:ST4[%currBlockNo] GPR64common:%vreg61
2320B		%vreg59<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg59
2336B		%vreg58<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg58
2352B		STRWui %vreg59, %vreg58, 13; mem:ST4[%verbosity26] GPR32:%vreg59 GPR64common:%vreg58
2368B		STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
	    Successors according to CFG: BB#17

2384B	BB#17: derived from LLVM BB %return
	    Predecessors according to CFG: BB#1 BB#16 BB#15 BB#9 BB#6 BB#3
2400B		%vreg108<def> = ADRP <ga:@BZ2_bzDecompressInit>[TF=1]; GPR64common:%vreg108
2416B		%vreg110<def> = ADDXri %vreg108, <ga:@BZ2_bzDecompressInit>[TF=34], 0; GPR64sp:%vreg110 GPR64common:%vreg108
2464B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2480B		%X0<def> = COPY %vreg110; GPR64sp:%vreg110
2496B		%X1<def> = COPY %vreg11; GPR64:%vreg11
2512B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
2528B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2544B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2560B		STACKMAP 3, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
2576B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2592B		%vreg107<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0] GPR32:%vreg107
2608B		%W0<def> = COPY %vreg107; GPR32:%vreg107
2624B		RET_ReallyLR %W0<imp-use>

# End machine code for function BZ2_bzDecompressInit.


selectOrSplit GPR64:%vreg11 [16r,2496r:0)  0@16r w=1.052083e-03
hints: %X1
missed hint %X1
assigning %vreg11 to %X19: W19 [16r,2496r:0)  0@16r

selectOrSplit GPR32:%vreg5 [32r,352r:0)  0@32r w=4.208333e-03
hints: %W2
missed hint %W2
assigning %vreg5 to %W20: W20 [32r,352r:0)  0@32r

selectOrSplit GPR32:%vreg3 [48r,336r:0)  0@48r w=4.404070e-03
hints: %W1
missed hint %W1
assigning %vreg3 to %W21: W21 [48r,336r:0)  0@48r

selectOrSplit GPR64:%vreg1 [64r,320r:0)  0@64r w=4.618902e-03
hints: %X0
missed hint %X0
assigning %vreg1 to %X22: W22 [64r,320r:0)  0@64r

selectOrSplit GPR64sp:%vreg10 [144r,208r:0)  0@144r w=4.353448e-03
hints: %X0
assigning %vreg10 to %X0: W0 [144r,208r:0)  0@144r

selectOrSplit GPR32:%vreg7 [416r,480r:0)  0@416r w=4.353448e-03
hints: %W0
assigning %vreg7 to %W0: W0 [416r,480r:0)  0@416r

selectOrSplit GPR64:%vreg51 [1408r,1480r:0)  0@1408r w=1.882549e-04
hints: %X0
assigning %vreg51 to %X0: W0 [1408r,1480r:0)  0@1408r

selectOrSplit GPR64:%vreg44 [1520r,1600r:0)  0@1520r w=1.851173e-04
hints: %X0
assigning %vreg44 to %X0: W0 [1520r,1600r:0)  0@1520r

selectOrSplit GPR64sp:%vreg110 [2416r,2480r:0)  0@2416r w=4.353448e-03
hints: %X0
assigning %vreg110 to %X0: W0 [2416r,2480r:0)  0@2416r

selectOrSplit GPR32:%vreg107 [2592r,2608r:0)  0@2592r w=inf
hints: %W0
assigning %vreg107 to %W0: W0 [2592r,2608r:0)  0@2592r

selectOrSplit GPR64common:%vreg8 [128r,144r:0)  0@128r w=inf
assigning %vreg8 to %X8: W8 [128r,144r:0)  0@128r

selectOrSplit GPR32:%vreg13 [512r,528r:0)  0@512r w=inf
assigning %vreg13 to %W8: W8 [512r,528r:0)  0@512r

selectOrSplit GPR64:%vreg15 [576r,592r:0)  0@576r w=inf
assigning %vreg15 to %X8: W8 [576r,592r:0)  0@576r

selectOrSplit GPR32:%vreg105 [624r,640r:0)  0@624r w=inf
assigning %vreg105 to %W8: W8 [624r,640r:0)  0@624r

selectOrSplit GPR32:%vreg17 [688r,704r:0)  0@688r w=inf
assigning %vreg17 to %W8: W8 [688r,704r:0)  0@688r

selectOrSplit GPR32common:%vreg19 [736r,752r:0)  0@736r w=inf
assigning %vreg19 to %W8: W8 [736r,752r:0)  0@736r

selectOrSplit GPR32:%vreg104 [800r,816r:0)  0@800r w=inf
assigning %vreg104 to %W8: W8 [800r,816r:0)  0@800r

selectOrSplit GPR32:%vreg21 [864r,880r:0)  0@864r w=inf
assigning %vreg21 to %W8: W8 [864r,880r:0)  0@864r

selectOrSplit GPR32common:%vreg23 [912r,928r:0)  0@912r w=inf
assigning %vreg23 to %W8: W8 [912r,928r:0)  0@912r

selectOrSplit GPR32:%vreg103 [976r,992r:0)  0@976r w=inf
assigning %vreg103 to %W8: W8 [976r,992r:0)  0@976r

selectOrSplit GPR64common:%vreg27 [1040r,1056r:0)  0@1040r w=inf
assigning %vreg27 to %X8: W8 [1040r,1056r:0)  0@1040r

selectOrSplit GPR64:%vreg26 [1056r,1072r:0)  0@1056r w=inf
assigning %vreg26 to %X8: W8 [1056r,1072r:0)  0@1056r

selectOrSplit GPR64common:%vreg31 [1136r,1152r:0)  0@1136r w=1.127904e-04
assigning %vreg31 to %X8: W8 [1136r,1152r:0)  0@1136r

selectOrSplit GPR64common:%vreg28 [1140r,1144r:0)  0@1140r w=inf
assigning %vreg28 to %X9: W9 [1140r,1144r:0)  0@1140r

selectOrSplit GPR64common:%vreg29 [1144r,1152r:0)  0@1144r w=inf
assigning %vreg29 to %X9: W9 [1144r,1152r:0)  0@1144r

selectOrSplit GPR64common:%vreg35 [1184r,1200r:0)  0@1184r w=inf
assigning %vreg35 to %X8: W8 [1184r,1200r:0)  0@1184r

selectOrSplit GPR64:%vreg34 [1200r,1216r:0)  0@1200r w=inf
assigning %vreg34 to %X8: W8 [1200r,1216r:0)  0@1200r

selectOrSplit GPR64common:%vreg39 [1280r,1296r:0)  0@1280r w=1.127904e-04
assigning %vreg39 to %X8: W8 [1280r,1296r:0)  0@1280r

selectOrSplit GPR64common:%vreg36 [1284r,1288r:0)  0@1284r w=inf
assigning %vreg36 to %X9: W9 [1284r,1288r:0)  0@1284r

selectOrSplit GPR64common:%vreg37 [1288r,1296r:0)  0@1288r w=inf
assigning %vreg37 to %X9: W9 [1288r,1296r:0)  0@1288r

selectOrSplit GPR64common:%vreg55 [1360r,1400r:0)  0@1360r w=1.999467e-04
assigning %vreg55 to %X8: W8 [1360r,1400r:0)  0@1360r

selectOrSplit GPR64common:%vreg52 [1392r,1408r:0)  0@1392r w=2.114821e-04
assigning %vreg52 to %X9: W9 [1392r,1408r:0)  0@1392r

selectOrSplit GPR64:%vreg54 [1400r,1488r:0)  0@1400r w=1.802798e-04
assigning %vreg54 to %X8: W8 [1400r,1488r:0)  0@1400r

selectOrSplit GPR64:%vreg41 [1616r,1632r:0)  0@1616r w=inf
assigning %vreg41 to %X8: W8 [1616r,1632r:0)  0@1616r

selectOrSplit GPR32:%vreg102 [1664r,1680r:0)  0@1664r w=inf
assigning %vreg102 to %W8: W8 [1664r,1680r:0)  0@1664r

selectOrSplit GPR64:%vreg101 [1760r,1792r:0)  0@1760r w=1.086130e-04
assigning %vreg101 to %X8: W8 [1760r,1792r:0)  0@1760r

selectOrSplit GPR64common:%vreg100 [1776r,1792r:0)  0@1776r w=inf
assigning %vreg100 to %X9: W9 [1776r,1792r:0)  0@1776r

selectOrSplit GPR64:%vreg96 [1808r,1856r:0)  0@1808r w=1.047340e-04
assigning %vreg96 to %X8: W8 [1808r,1856r:0)  0@1808r

selectOrSplit GPR64common:%vreg94 [1840r,1856r:0)  0@1840r w=inf
assigning %vreg94 to %X9: W9 [1840r,1856r:0)  0@1840r

selectOrSplit GPR64common:%vreg91 [1872r,1888r:0)  0@1872r w=1.127904e-04
assigning %vreg91 to %X8: W8 [1872r,1888r:0)  0@1872r

selectOrSplit GPR32:%vreg89 [1880r,1888r:0)  0@1880r w=inf
assigning %vreg89 to %W9: W9 [1880r,1888r:0)  0@1880r

selectOrSplit GPR64common:%vreg88 [1904r,1920r:0)  0@1904r w=inf
assigning %vreg88 to %X8: W8 [1904r,1920r:0)  0@1904r

selectOrSplit GPR64common:%vreg86 [1936r,1952r:0)  0@1936r w=inf
assigning %vreg86 to %X8: W8 [1936r,1952r:0)  0@1936r

selectOrSplit GPR64common:%vreg84 [1968r,1984r:0)  0@1968r w=inf
assigning %vreg84 to %X8: W8 [1968r,1984r:0)  0@1968r

selectOrSplit GPR64common:%vreg82 [2000r,2016r:0)  0@2000r w=inf
assigning %vreg82 to %X8: W8 [2000r,2016r:0)  0@2000r

selectOrSplit GPR64common:%vreg80 [2032r,2048r:0)  0@2032r w=inf
assigning %vreg80 to %X8: W8 [2032r,2048r:0)  0@2032r

selectOrSplit GPR64common:%vreg78 [2064r,2080r:0)  0@2064r w=inf
assigning %vreg78 to %X8: W8 [2064r,2080r:0)  0@2064r

selectOrSplit GPR64common:%vreg76 [2096r,2112r:0)  0@2096r w=inf
assigning %vreg76 to %X8: W8 [2096r,2112r:0)  0@2096r

selectOrSplit GPR32:%vreg73 [2128r,2176r:0)  0@2128r w=1.047340e-04
assigning %vreg73 to %W8: W8 [2128r,2176r:0)  0@2128r

selectOrSplit GPR64common:%vreg71 [2160r,2176r:0)  0@2160r w=inf
assigning %vreg71 to %X9: W9 [2160r,2176r:0)  0@2160r

selectOrSplit GPR64common:%vreg68 [2192r,2208r:0)  0@2192r w=inf
assigning %vreg68 to %X8: W8 [2192r,2208r:0)  0@2192r

selectOrSplit GPR64common:%vreg66 [2224r,2240r:0)  0@2224r w=inf
assigning %vreg66 to %X8: W8 [2224r,2240r:0)  0@2224r

selectOrSplit GPR64common:%vreg64 [2256r,2272r:0)  0@2256r w=inf
assigning %vreg64 to %X8: W8 [2256r,2272r:0)  0@2256r

selectOrSplit GPR64common:%vreg61 [2288r,2304r:0)  0@2288r w=inf
assigning %vreg61 to %X8: W8 [2288r,2304r:0)  0@2288r

selectOrSplit GPR32:%vreg59 [2320r,2352r:0)  0@2320r w=1.086130e-04
assigning %vreg59 to %W8: W8 [2320r,2352r:0)  0@2320r

selectOrSplit GPR64common:%vreg58 [2336r,2352r:0)  0@2336r w=inf
assigning %vreg58 to %X9: W9 [2336r,2352r:0)  0@2336r

selectOrSplit GPR64common:%vreg108 [2400r,2416r:0)  0@2400r w=inf
assigning %vreg108 to %X8: W8 [2400r,2416r:0)  0@2400r

********** STACK TRANSFORMATION METADATA **********
********** Function: BZ2_bzDecompressInit
********** REGISTER MAP **********
[%vreg1 -> %X22] GPR64
[%vreg3 -> %W21] GPR32
[%vreg5 -> %W20] GPR32
[%vreg7 -> %W0] GPR32
[%vreg8 -> %X8] GPR64common
[%vreg10 -> %X0] GPR64sp
[%vreg11 -> %X19] GPR64
[%vreg13 -> %W8] GPR32
[%vreg15 -> %X8] GPR64
[%vreg17 -> %W8] GPR32
[%vreg19 -> %W8] GPR32common
[%vreg21 -> %W8] GPR32
[%vreg23 -> %W8] GPR32common
[%vreg26 -> %X8] GPR64
[%vreg27 -> %X8] GPR64common
[%vreg28 -> %X9] GPR64common
[%vreg29 -> %X9] GPR64common
[%vreg31 -> %X8] GPR64common
[%vreg34 -> %X8] GPR64
[%vreg35 -> %X8] GPR64common
[%vreg36 -> %X9] GPR64common
[%vreg37 -> %X9] GPR64common
[%vreg39 -> %X8] GPR64common
[%vreg41 -> %X8] GPR64
[%vreg44 -> %X0] GPR64
[%vreg51 -> %X0] GPR64
[%vreg52 -> %X9] GPR64common
[%vreg54 -> %X8] GPR64
[%vreg55 -> %X8] GPR64common
[%vreg58 -> %X9] GPR64common
[%vreg59 -> %W8] GPR32
[%vreg61 -> %X8] GPR64common
[%vreg64 -> %X8] GPR64common
[%vreg66 -> %X8] GPR64common
[%vreg68 -> %X8] GPR64common
[%vreg71 -> %X9] GPR64common
[%vreg73 -> %W8] GPR32
[%vreg76 -> %X8] GPR64common
[%vreg78 -> %X8] GPR64common
[%vreg80 -> %X8] GPR64common
[%vreg82 -> %X8] GPR64common
[%vreg84 -> %X8] GPR64common
[%vreg86 -> %X8] GPR64common
[%vreg88 -> %X8] GPR64common
[%vreg89 -> %W9] GPR32
[%vreg91 -> %X8] GPR64common
[%vreg94 -> %X9] GPR64common
[%vreg96 -> %X8] GPR64
[%vreg100 -> %X9] GPR64common
[%vreg101 -> %X8] GPR64
[%vreg102 -> %W8] GPR32
[%vreg103 -> %W8] GPR32
[%vreg104 -> %W8] GPR32
[%vreg105 -> %W8] GPR32
[%vreg107 -> %W0] GPR32
[%vreg108 -> %X8] GPR64common
[%vreg110 -> %X0] GPR64sp


Stackmap 0:
  STACKMAP 0, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, %vreg5, 0, <fi#3>, 0, %vreg1, 0, <fi#1>, 0, %vreg3, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack4] LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack2](align=4) GPR32:%vreg5,%vreg3 GPR64:%vreg1

i32* %retval: in stack slot 0 (size: 4)
%struct.DState** %s: in stack slot 4 (size: 8)
i32 %small: in register %W20 (vreg 5)
i32* %small.addr: in stack slot 3 (size: 4)
%struct.bz_stream* %strm: in register %X22 (vreg 1)
%struct.bz_stream** %strm.addr: in stack slot 1 (size: 8)
i32 %verbosity: in register %W21 (vreg 3)
i32* %verbosity.addr: in stack slot 2 (size: 4)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack4] LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack2](align=4)

i32* %retval: in stack slot 0 (size: 4)
%struct.DState** %s: in stack slot 4 (size: 8)
i32* %small.addr: in stack slot 3 (size: 4)
%struct.bz_stream** %strm.addr: in stack slot 1 (size: 8)
i32* %verbosity.addr: in stack slot 2 (size: 4)

Duplicate operand locations:


Stackmap 2:
  STACKMAP 2, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack4] LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack2](align=4)

i32* %retval: in stack slot 0 (size: 4)
%struct.DState** %s: in stack slot 4 (size: 8)
i32* %small.addr: in stack slot 3 (size: 4)
%struct.bz_stream** %strm.addr: in stack slot 1 (size: 8)
i32* %verbosity.addr: in stack slot 2 (size: 4)

Duplicate operand locations:


Stackmap 3:
  STACKMAP 3, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)

i32* %retval: in stack slot 0 (size: 4)

Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, %vreg5, 0, <fi#3>, 0, %vreg1, 0, <fi#1>, 0, %vreg3, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack4] LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack2](align=4) GPR32:%vreg5,%vreg3 GPR64:%vreg1
  -> Call instruction SlotIndex 240B, searching vregs 0 -> 112 and stack slots 0 -> 5
    + vreg11 is live in register but not in stackmap
      Defining instruction: %vreg11<def> = COPY %LR; GPR64:%vreg11
      Value: generated value, 1 instruction(s)

  STACKMAP 1, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack4] LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack2](align=4)
  -> Call instruction SlotIndex 384B, searching vregs 0 -> 112 and stack slots 0 -> 5
    + vreg11 is live in register but not in stackmap
      Defining instruction: %vreg11<def> = COPY %LR; GPR64:%vreg11
      Value: generated value, 1 instruction(s)

  STACKMAP 2, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack4] LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack2](align=4)
  -> Call instruction SlotIndex 1488B, searching vregs 0 -> 112 and stack slots 0 -> 5
    + vreg11 is live in register but not in stackmap
      Defining instruction: %vreg11<def> = COPY %LR; GPR64:%vreg11
      Value: generated value, 1 instruction(s)

  STACKMAP 3, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
  -> Call instruction SlotIndex 2512B, searching vregs 0 -> 112 and stack slots 0 -> 5

********** REWRITE VIRTUAL REGISTERS **********
********** Function: BZ2_bzDecompressInit
********** REGISTER MAP **********
[%vreg1 -> %X22] GPR64
[%vreg3 -> %W21] GPR32
[%vreg5 -> %W20] GPR32
[%vreg7 -> %W0] GPR32
[%vreg8 -> %X8] GPR64common
[%vreg10 -> %X0] GPR64sp
[%vreg11 -> %X19] GPR64
[%vreg13 -> %W8] GPR32
[%vreg15 -> %X8] GPR64
[%vreg17 -> %W8] GPR32
[%vreg19 -> %W8] GPR32common
[%vreg21 -> %W8] GPR32
[%vreg23 -> %W8] GPR32common
[%vreg26 -> %X8] GPR64
[%vreg27 -> %X8] GPR64common
[%vreg28 -> %X9] GPR64common
[%vreg29 -> %X9] GPR64common
[%vreg31 -> %X8] GPR64common
[%vreg34 -> %X8] GPR64
[%vreg35 -> %X8] GPR64common
[%vreg36 -> %X9] GPR64common
[%vreg37 -> %X9] GPR64common
[%vreg39 -> %X8] GPR64common
[%vreg41 -> %X8] GPR64
[%vreg44 -> %X0] GPR64
[%vreg51 -> %X0] GPR64
[%vreg52 -> %X9] GPR64common
[%vreg54 -> %X8] GPR64
[%vreg55 -> %X8] GPR64common
[%vreg58 -> %X9] GPR64common
[%vreg59 -> %W8] GPR32
[%vreg61 -> %X8] GPR64common
[%vreg64 -> %X8] GPR64common
[%vreg66 -> %X8] GPR64common
[%vreg68 -> %X8] GPR64common
[%vreg71 -> %X9] GPR64common
[%vreg73 -> %W8] GPR32
[%vreg76 -> %X8] GPR64common
[%vreg78 -> %X8] GPR64common
[%vreg80 -> %X8] GPR64common
[%vreg82 -> %X8] GPR64common
[%vreg84 -> %X8] GPR64common
[%vreg86 -> %X8] GPR64common
[%vreg88 -> %X8] GPR64common
[%vreg89 -> %W9] GPR32
[%vreg91 -> %X8] GPR64common
[%vreg94 -> %X9] GPR64common
[%vreg96 -> %X8] GPR64
[%vreg100 -> %X9] GPR64common
[%vreg101 -> %X8] GPR64
[%vreg102 -> %W8] GPR32
[%vreg103 -> %W8] GPR32
[%vreg104 -> %W8] GPR32
[%vreg105 -> %W8] GPR32
[%vreg107 -> %W0] GPR32
[%vreg108 -> %X8] GPR64common
[%vreg110 -> %X0] GPR64sp

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %LR %W1 %W2 %X0
16B		%vreg11<def> = COPY %LR; GPR64:%vreg11
32B		%vreg5<def> = COPY %W2; GPR32:%vreg5
48B		%vreg3<def> = COPY %W1; GPR32:%vreg3
64B		%vreg1<def> = COPY %X0; GPR64:%vreg1
128B		%vreg8<def> = ADRP <ga:@BZ2_bzDecompressInit>[TF=1]; GPR64common:%vreg8
144B		%vreg10<def> = ADDXri %vreg8<kill>, <ga:@BZ2_bzDecompressInit>[TF=34], 0; GPR64sp:%vreg10 GPR64common:%vreg8
192B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
208B		%X0<def> = COPY %vreg10<kill>; GPR64sp:%vreg10
224B		%X1<def> = COPY %vreg11; GPR64:%vreg11
240B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
256B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
272B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
288B		STACKMAP 0, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, %vreg5, 0, <fi#3>, 0, %vreg1, 0, <fi#1>, 0, %vreg3, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack4] LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack2](align=4) GPR32:%vreg5,%vreg3 GPR64:%vreg1
304B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
320B		STRXui %vreg1<kill>, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg1
336B		STRWui %vreg3<kill>, <fi#2>, 0; mem:ST4[FixedStack2] GPR32:%vreg3
352B		STRWui %vreg5<kill>, <fi#3>, 0; mem:ST4[FixedStack3] GPR32:%vreg5
368B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
384B		BL <ga:@bz_config_ok>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-def>
400B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
416B		%vreg7<def> = COPY %W0; GPR32:%vreg7
432B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
448B		STACKMAP 1, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack4] LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack2](align=4)
464B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
480B		CBNZW %vreg7<kill>, <BB#2>; GPR32:%vreg7
	    Successors according to CFG: BB#2 BB#1
> %X19<def> = COPY %LR
> %W20<def> = COPY %W2
> %W21<def> = COPY %W1
> %X22<def> = COPY %X0
> %X8<def> = ADRP <ga:@BZ2_bzDecompressInit>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@BZ2_bzDecompressInit>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19
> BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 0, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, %W20, 0, <fi#3>, 0, %X22, 0, <fi#1>, 0, %W21, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack4] LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack2](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRXui %X22<kill>, <fi#1>, 0; mem:ST8[FixedStack1]
> STRWui %W21<kill>, <fi#2>, 0; mem:ST4[FixedStack2]
> STRWui %W20<kill>, <fi#3>, 0; mem:ST4[FixedStack3]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> BL <ga:@bz_config_ok>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = COPY %W0
Deleting identity copy.
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 1, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack4] LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack2](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> CBNZW %W0<kill>, <BB#2>
496B	BB#1: derived from LLVM BB %if.then
	    Live Ins: %X19
	    Predecessors according to CFG: BB#0
512B		%vreg13<def> = MOVi32imm 4294967287; GPR32:%vreg13
528B		STRWui %vreg13<kill>, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg13
544B		B <BB#17>
	    Successors according to CFG: BB#17
> %W8<def> = MOVi32imm 4294967287
> STRWui %W8<kill>, <fi#0>, 0; mem:ST4[FixedStack0]
> B <BB#17>
560B	BB#2: derived from LLVM BB %if.end
	    Live Ins: %X19
	    Predecessors according to CFG: BB#0
576B		%vreg15<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg15
592B		CBNZX %vreg15<kill>, <BB#4>; GPR64:%vreg15
	    Successors according to CFG: BB#4 BB#3
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> CBNZX %X8<kill>, <BB#4>
608B	BB#3: derived from LLVM BB %if.then.1
	    Live Ins: %X19
	    Predecessors according to CFG: BB#2
624B		%vreg105<def> = MOVi32imm 4294967294; GPR32:%vreg105
640B		STRWui %vreg105<kill>, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg105
656B		B <BB#17>
	    Successors according to CFG: BB#17
> %W8<def> = MOVi32imm 4294967294
> STRWui %W8<kill>, <fi#0>, 0; mem:ST4[FixedStack0]
> B <BB#17>
672B	BB#4: derived from LLVM BB %if.end.2
	    Live Ins: %X19
	    Predecessors according to CFG: BB#2
688B		%vreg17<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg17
704B		CBZW %vreg17<kill>, <BB#7>; GPR32:%vreg17
	    Successors according to CFG: BB#7 BB#5
> %W8<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3]
> CBZW %W8<kill>, <BB#7>
720B	BB#5: derived from LLVM BB %land.lhs.true
	    Live Ins: %X19
	    Predecessors according to CFG: BB#4
736B		%vreg19<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32common:%vreg19
752B		%WZR<def> = SUBSWri %vreg19<kill>, 1, 0, %NZCV<imp-def>; GPR32common:%vreg19
768B		Bcc 0, <BB#7>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#7 BB#6
> %W8<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3]
> %WZR<def> = SUBSWri %W8<kill>, 1, 0, %NZCV<imp-def>
> Bcc 0, <BB#7>, %NZCV<imp-use,kill>
784B	BB#6: derived from LLVM BB %if.then.5
	    Live Ins: %X19
	    Predecessors according to CFG: BB#5
800B		%vreg104<def> = MOVi32imm 4294967294; GPR32:%vreg104
816B		STRWui %vreg104<kill>, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg104
832B		B <BB#17>
	    Successors according to CFG: BB#17
> %W8<def> = MOVi32imm 4294967294
> STRWui %W8<kill>, <fi#0>, 0; mem:ST4[FixedStack0]
> B <BB#17>
848B	BB#7: derived from LLVM BB %if.end.6
	    Live Ins: %X19
	    Predecessors according to CFG: BB#4 BB#5
864B		%vreg21<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg21
880B		TBNZW %vreg21<kill>, 31, <BB#9>; GPR32:%vreg21
	    Successors according to CFG: BB#9 BB#8
> %W8<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2]
> TBNZW %W8<kill>, 31, <BB#9>
896B	BB#8: derived from LLVM BB %lor.lhs.false
	    Live Ins: %X19
	    Predecessors according to CFG: BB#7
912B		%vreg23<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32common:%vreg23
928B		%WZR<def> = SUBSWri %vreg23<kill>, 4, 0, %NZCV<imp-def>; GPR32common:%vreg23
944B		Bcc 13, <BB#10>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#10 BB#9
> %W8<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2]
> %WZR<def> = SUBSWri %W8<kill>, 4, 0, %NZCV<imp-def>
> Bcc 13, <BB#10>, %NZCV<imp-use,kill>
960B	BB#9: derived from LLVM BB %if.then.9
	    Live Ins: %X19
	    Predecessors according to CFG: BB#7 BB#8
976B		%vreg103<def> = MOVi32imm 4294967294; GPR32:%vreg103
992B		STRWui %vreg103<kill>, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg103
1008B		B <BB#17>
	    Successors according to CFG: BB#17
> %W8<def> = MOVi32imm 4294967294
> STRWui %W8<kill>, <fi#0>, 0; mem:ST4[FixedStack0]
> B <BB#17>
1024B	BB#10: derived from LLVM BB %if.end.10
	    Live Ins: %X19
	    Predecessors according to CFG: BB#8
1040B		%vreg27<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg27
1056B		%vreg26<def> = LDRXui %vreg27<kill>, 7; mem:LD8[%bzalloc] GPR64:%vreg26 GPR64common:%vreg27
1072B		CBNZX %vreg26<kill>, <BB#12>; GPR64:%vreg26
	    Successors according to CFG: BB#12 BB#11
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X8<def> = LDRXui %X8<kill>, 7; mem:LD8[%bzalloc]
> CBNZX %X8<kill>, <BB#12>
1088B	BB#11: derived from LLVM BB %if.then.12
	    Live Ins: %X19
	    Predecessors according to CFG: BB#10
1136B		%vreg31<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg31
1140B		%vreg28<def> = ADRP <ga:@default_bzalloc>[TF=1]; GPR64common:%vreg28
1144B		%vreg29<def> = ADDXri %vreg28<kill>, <ga:@default_bzalloc>[TF=34], 0; GPR64common:%vreg29,%vreg28
1152B		STRXui %vreg29<kill>, %vreg31<kill>, 7; mem:ST8[%bzalloc13] GPR64common:%vreg29,%vreg31
	    Successors according to CFG: BB#12
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X9<def> = ADRP <ga:@default_bzalloc>[TF=1]
> %X9<def> = ADDXri %X9<kill>, <ga:@default_bzalloc>[TF=34], 0
> STRXui %X9<kill>, %X8<kill>, 7; mem:ST8[%bzalloc13]
1168B	BB#12: derived from LLVM BB %if.end.14
	    Live Ins: %X19
	    Predecessors according to CFG: BB#10 BB#11
1184B		%vreg35<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg35
1200B		%vreg34<def> = LDRXui %vreg35<kill>, 8; mem:LD8[%bzfree] GPR64:%vreg34 GPR64common:%vreg35
1216B		CBNZX %vreg34<kill>, <BB#14>; GPR64:%vreg34
	    Successors according to CFG: BB#14 BB#13
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X8<def> = LDRXui %X8<kill>, 8; mem:LD8[%bzfree]
> CBNZX %X8<kill>, <BB#14>
1232B	BB#13: derived from LLVM BB %if.then.16
	    Live Ins: %X19
	    Predecessors according to CFG: BB#12
1280B		%vreg39<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg39
1284B		%vreg36<def> = ADRP <ga:@default_bzfree>[TF=1]; GPR64common:%vreg36
1288B		%vreg37<def> = ADDXri %vreg36<kill>, <ga:@default_bzfree>[TF=34], 0; GPR64common:%vreg37,%vreg36
1296B		STRXui %vreg37<kill>, %vreg39<kill>, 8; mem:ST8[%bzfree17] GPR64common:%vreg37,%vreg39
	    Successors according to CFG: BB#14
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X9<def> = ADRP <ga:@default_bzfree>[TF=1]
> %X9<def> = ADDXri %X9<kill>, <ga:@default_bzfree>[TF=34], 0
> STRXui %X9<kill>, %X8<kill>, 8; mem:ST8[%bzfree17]
1312B	BB#14: derived from LLVM BB %if.end.18
	    Live Ins: %X19
	    Predecessors according to CFG: BB#12 BB#13
1360B		%vreg55<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg55
1392B		%vreg52<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg52
1400B		%vreg54<def> = LDRXui %vreg55<kill>, 7; mem:LD8[%bzalloc19] GPR64:%vreg54 GPR64common:%vreg55
1408B		%vreg51<def> = LDRXui %vreg52<kill>, 9; mem:LD8[%opaque] GPR64:%vreg51 GPR64common:%vreg52
1424B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1456B		%W1<def> = MOVi32imm 64144
1472B		%W2<def> = MOVi32imm 1
1480B		%X0<def> = COPY %vreg51<kill>; GPR64:%vreg51
1488B		BLR %vreg54<kill>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %W2<imp-use>, %X0<imp-def>; GPR64:%vreg54
1504B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1520B		%vreg44<def> = COPY %X0; GPR64:%vreg44
1536B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1552B		STACKMAP 2, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack4] LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack2](align=4)
1568B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1600B		STRXui %vreg44<kill>, <fi#4>, 0; mem:ST8[FixedStack4] GPR64:%vreg44
1616B		%vreg41<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64:%vreg41
1632B		CBNZX %vreg41<kill>, <BB#16>; GPR64:%vreg41
	    Successors according to CFG: BB#16 BB#15
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X8<def> = LDRXui %X8<kill>, 7; mem:LD8[%bzalloc19]
> %X0<def> = LDRXui %X9<kill>, 9; mem:LD8[%opaque]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %W1<def> = MOVi32imm 64144
> %W2<def> = MOVi32imm 1
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BLR %X8<kill>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %W2<imp-use>, %X0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0
Deleting identity copy.
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 2, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack4] LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack2](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRXui %X0<kill>, <fi#4>, 0; mem:ST8[FixedStack4]
> %X8<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4]
> CBNZX %X8<kill>, <BB#16>
1648B	BB#15: derived from LLVM BB %if.then.22
	    Live Ins: %X19
	    Predecessors according to CFG: BB#14
1664B		%vreg102<def> = MOVi32imm 4294967293; GPR32:%vreg102
1680B		STRWui %vreg102<kill>, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg102
1696B		B <BB#17>
	    Successors according to CFG: BB#17
> %W8<def> = MOVi32imm 4294967293
> STRWui %W8<kill>, <fi#0>, 0; mem:ST4[FixedStack0]
> B <BB#17>
1712B	BB#16: derived from LLVM BB %if.end.23
	    Live Ins: %X19
	    Predecessors according to CFG: BB#14
1760B		%vreg101<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg101
1776B		%vreg100<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg100
1792B		STRXui %vreg101<kill>, %vreg100<kill>, 0; mem:ST8[%strm24] GPR64:%vreg101 GPR64common:%vreg100
1808B		%vreg96<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64:%vreg96
1840B		%vreg94<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg94
1856B		STRXui %vreg96<kill>, %vreg94<kill>, 6; mem:ST8[%state] GPR64:%vreg96 GPR64common:%vreg94
1872B		%vreg91<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg91
1880B		%vreg89<def> = MOVi32imm 10; GPR32:%vreg89
1888B		STRWui %vreg89<kill>, %vreg91<kill>, 2; mem:ST4[%state25] GPR32:%vreg89 GPR64common:%vreg91
1904B		%vreg88<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg88
1920B		STRWui %WZR, %vreg88<kill>, 9; mem:ST4[%bsLive] GPR64common:%vreg88
1936B		%vreg86<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg86
1952B		STRWui %WZR, %vreg86<kill>, 8; mem:ST4[%bsBuff] GPR64common:%vreg86
1968B		%vreg84<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg84
1984B		STRWui %WZR, %vreg84<kill>, 797; mem:ST4[%calculatedCombinedCRC] GPR64common:%vreg84
2000B		%vreg82<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg82
2016B		STRWui %WZR, %vreg82<kill>, 3; mem:ST4[%total_in_lo32] GPR64common:%vreg82
2032B		%vreg80<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg80
2048B		STRWui %WZR, %vreg80<kill>, 4; mem:ST4[%total_in_hi32] GPR64common:%vreg80
2064B		%vreg78<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg78
2080B		STRWui %WZR, %vreg78<kill>, 9; mem:ST4[%total_out_lo32] GPR64common:%vreg78
2096B		%vreg76<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg76
2112B		STRWui %WZR, %vreg76<kill>, 10; mem:ST4[%total_out_hi32] GPR64common:%vreg76
2128B		%vreg73<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg73
2160B		%vreg71<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg71
2176B		STRBBui %vreg73<kill>, %vreg71<kill>, 44; mem:ST1[%smallDecompress] GPR32:%vreg73 GPR64common:%vreg71
2192B		%vreg68<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg68
2208B		STRXui %XZR, %vreg68<kill>, 396; mem:ST8[%ll4] GPR64common:%vreg68
2224B		%vreg66<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg66
2240B		STRXui %XZR, %vreg66<kill>, 395; mem:ST8[%ll16] GPR64common:%vreg66
2256B		%vreg64<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg64
2272B		STRXui %XZR, %vreg64<kill>, 394; mem:ST8[%tt] GPR64common:%vreg64
2288B		%vreg61<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg61
2304B		STRWui %WZR, %vreg61<kill>, 12; mem:ST4[%currBlockNo] GPR64common:%vreg61
2320B		%vreg59<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg59
2336B		%vreg58<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg58
2352B		STRWui %vreg59<kill>, %vreg58<kill>, 13; mem:ST4[%verbosity26] GPR32:%vreg59 GPR64common:%vreg58
2368B		STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
	    Successors according to CFG: BB#17
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X9<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4]
> STRXui %X8<kill>, %X9<kill>, 0; mem:ST8[%strm24]
> %X8<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRXui %X8<kill>, %X9<kill>, 6; mem:ST8[%state]
> %X8<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4]
> %W9<def> = MOVi32imm 10
> STRWui %W9<kill>, %X8<kill>, 2; mem:ST4[%state25]
> %X8<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4]
> STRWui %WZR, %X8<kill>, 9; mem:ST4[%bsLive]
> %X8<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4]
> STRWui %WZR, %X8<kill>, 8; mem:ST4[%bsBuff]
> %X8<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4]
> STRWui %WZR, %X8<kill>, 797; mem:ST4[%calculatedCombinedCRC]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRWui %WZR, %X8<kill>, 3; mem:ST4[%total_in_lo32]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRWui %WZR, %X8<kill>, 4; mem:ST4[%total_in_hi32]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRWui %WZR, %X8<kill>, 9; mem:ST4[%total_out_lo32]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRWui %WZR, %X8<kill>, 10; mem:ST4[%total_out_hi32]
> %W8<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3]
> %X9<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4]
> STRBBui %W8<kill>, %X9<kill>, 44; mem:ST1[%smallDecompress]
> %X8<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4]
> STRXui %XZR, %X8<kill>, 396; mem:ST8[%ll4]
> %X8<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4]
> STRXui %XZR, %X8<kill>, 395; mem:ST8[%ll16]
> %X8<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4]
> STRXui %XZR, %X8<kill>, 394; mem:ST8[%tt]
> %X8<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4]
> STRWui %WZR, %X8<kill>, 12; mem:ST4[%currBlockNo]
> %W8<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2]
> %X9<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4]
> STRWui %W8<kill>, %X9<kill>, 13; mem:ST4[%verbosity26]
> STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
2384B	BB#17: derived from LLVM BB %return
	    Live Ins: %X19
	    Predecessors according to CFG: BB#1 BB#16 BB#15 BB#9 BB#6 BB#3
2400B		%vreg108<def> = ADRP <ga:@BZ2_bzDecompressInit>[TF=1]; GPR64common:%vreg108
2416B		%vreg110<def> = ADDXri %vreg108<kill>, <ga:@BZ2_bzDecompressInit>[TF=34], 0; GPR64sp:%vreg110 GPR64common:%vreg108
2464B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2480B		%X0<def> = COPY %vreg110<kill>; GPR64sp:%vreg110
2496B		%X1<def> = COPY %vreg11<kill>; GPR64:%vreg11
2512B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
2528B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2544B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2560B		STACKMAP 3, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
2576B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2592B		%vreg107<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0] GPR32:%vreg107
2608B		%W0<def> = COPY %vreg107<kill>; GPR32:%vreg107
2624B		RET_ReallyLR %W0<imp-use>
> %X8<def> = ADRP <ga:@BZ2_bzDecompressInit>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@BZ2_bzDecompressInit>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19<kill>
> BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 3, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0]
> %W0<def> = COPY %W0<kill>
Deleting identity copy.
> RET_ReallyLR %W0<imp-use>
Computing live-in reg-units in ABI blocks.
0B	BB#0 W0#0 W1#0 W30#0
Created 3 new intervals.
********** INTERVALS **********
W30 [0B,16r:0)[208r,208d:4)[272e,272d:1)[992r,992d:2)[1040e,1040d:3)  0@0B-phi 1@272e 2@992r 3@1040e 4@208r
W0 [0B,48r:0)[176r,208r:3)[960r,992r:2)[1072r,1088r:1)  0@0B-phi 1@1072r 2@960r 3@176r
W1 [0B,32r:0)[192r,208r:2)[976r,992r:1)  0@0B-phi 1@976r 2@192r
%vreg0 [48r,64r:0)  0@48r
%vreg1 [64r,304r:0)  0@64r
%vreg2 [32r,80r:0)  0@32r
%vreg3 [80r,320r:0)  0@80r
%vreg4 [240r,352r:0)  0@240r
%vreg5 [96r,112r:0)  0@96r
%vreg6 [112r,128r:0)  0@112r
%vreg7 [128r,176r:0)  0@128r
%vreg8 [144r,192r:0)  0@144r
%vreg9 [16r,928r:0)  0@16r
%vreg13 [560r,576r:0)  0@560r
%vreg16 [512r,528r:0)  0@512r
%vreg17 [528r,544r:0)  0@528r
%vreg18 [544r,560r:0)  0@544r
%vreg19 [496r,544r:0)  0@496r
%vreg23 [480r,528r:0)  0@480r
%vreg24 [464r,576r:0)  0@464r
%vreg27 [432r,448r:0)  0@432r
%vreg30 [416r,432r:0)  0@416r
%vreg31 [400r,416r:0)  0@400r
%vreg32 [384r,416r:0)  0@384r
%vreg34 [688r,704r:0)  0@688r
%vreg36 [624r,640r:0)  0@624r
%vreg40 [800r,816r:0)  0@800r
%vreg41 [784r,800r:0)  0@784r
%vreg42 [768r,800r:0)  0@768r
%vreg44 [864r,880r:0)  0@864r
%vreg45 [880r,896r:0)  0@880r
%vreg46 [896r,960r:0)  0@896r
%vreg47 [928r,976r:0)  0@928r
%vreg48 [912r,1072r:0)  0@912r
RegMasks: 208r 992r
********** MACHINEINSTRS **********
# Machine code for function BZ2_indexIntoF: Post SSA
Frame Objects:
  fi#0: size=4, align=4, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=4, align=4, at location [SP]
  fi#3: size=4, align=4, at location [SP]
  fi#4: size=4, align=4, at location [SP]
Function Live Ins: %W0 in %vreg0, %X1 in %vreg2, %LR in %vreg9

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %W0 %X1 %LR
16B		%vreg9<def> = COPY %LR; GPR64:%vreg9
32B		%vreg2<def> = COPY %X1; GPR64:%vreg2
48B		%vreg0<def> = COPY %W0; GPR32:%vreg0
64B		%vreg1<def> = COPY %vreg0; GPR32:%vreg1,%vreg0
80B		%vreg3<def> = COPY %vreg2; GPR64:%vreg3,%vreg2
96B		%vreg5<def> = ADRP <ga:@BZ2_indexIntoF>[TF=1]; GPR64common:%vreg5
112B		%vreg6<def> = ADDXri %vreg5, <ga:@BZ2_indexIntoF>[TF=34], 0; GPR64sp:%vreg6 GPR64common:%vreg5
128B		%vreg7<def> = COPY %vreg6; GPR64all:%vreg7 GPR64sp:%vreg6
144B		%vreg8<def> = COPY %vreg9; GPR64all:%vreg8 GPR64:%vreg9
160B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
176B		%X0<def> = COPY %vreg7; GPR64all:%vreg7
192B		%X1<def> = COPY %vreg8; GPR64all:%vreg8
208B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
224B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
240B		%vreg4<def> = MOVi32imm 256; GPR32:%vreg4
256B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
272B		STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack0](align=4) LD8[FixedStack4](align=4) LD8[FixedStack3](align=4) LD8[FixedStack2](align=4) GPR64:%vreg3 GPR32:%vreg1
288B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
304B		STRWui %vreg1, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg1
320B		STRXui %vreg3, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg3
336B		STRWui %WZR, <fi#2>, 0; mem:ST4[FixedStack2]
352B		STRWui %vreg4, <fi#3>, 0; mem:ST4[FixedStack3] GPR32:%vreg4
	    Successors according to CFG: BB#1

368B	BB#1: derived from LLVM BB %do.body
	    Predecessors according to CFG: BB#0 BB#5
384B		%vreg32<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg32
400B		%vreg31<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg31
416B		%vreg30<def> = ADDWrr %vreg32, %vreg31; GPR32:%vreg30,%vreg32,%vreg31
432B		%vreg27<def> = SBFMWri %vreg30, 1, 31; GPR32:%vreg27,%vreg30
448B		STRWui %vreg27, <fi#4>, 0; mem:ST4[FixedStack4] GPR32:%vreg27
464B		%vreg24<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0] GPR32:%vreg24
480B		%vreg23<def> = LDRSWui <fi#4>, 0; mem:LD4[FixedStack4] GPR64:%vreg23
496B		%vreg19<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg19
512B		%vreg16<def> = MOVi64imm 4; GPR64:%vreg16
528B		%vreg17<def> = MADDXrrr %vreg23, %vreg16, %XZR; GPR64:%vreg17,%vreg23,%vreg16
544B		%vreg18<def> = ADDXrr %vreg19, %vreg17; GPR64common:%vreg18 GPR64:%vreg19,%vreg17
560B		%vreg13<def> = LDRWui %vreg18, 0; mem:LD4[%arrayidx] GPR32:%vreg13 GPR64common:%vreg18
576B		%WZR<def> = SUBSWrr %vreg24, %vreg13, %NZCV<imp-def>; GPR32:%vreg24,%vreg13
592B		Bcc 11, <BB#3>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#3 BB#2

608B	BB#2: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#1
624B		%vreg36<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg36
640B		STRWui %vreg36, <fi#2>, 0; mem:ST4[FixedStack2] GPR32:%vreg36
656B		B <BB#4>
	    Successors according to CFG: BB#4

672B	BB#3: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#1
688B		%vreg34<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg34
704B		STRWui %vreg34, <fi#3>, 0; mem:ST4[FixedStack3] GPR32:%vreg34
	    Successors according to CFG: BB#4

720B	BB#4: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#3 BB#2
736B		B <BB#5>
	    Successors according to CFG: BB#5

752B	BB#5: derived from LLVM BB %do.cond
	    Predecessors according to CFG: BB#4
768B		%vreg42<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg42
784B		%vreg41<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg41
800B		%vreg40<def> = SUBWrr %vreg42, %vreg41; GPR32common:%vreg40 GPR32:%vreg42,%vreg41
816B		%WZR<def> = SUBSWri %vreg40, 1, 0, %NZCV<imp-def>; GPR32common:%vreg40
832B		Bcc 1, <BB#1>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#1 BB#6

848B	BB#6: derived from LLVM BB %do.end
	    Predecessors according to CFG: BB#5
864B		%vreg44<def> = ADRP <ga:@BZ2_indexIntoF>[TF=1]; GPR64common:%vreg44
880B		%vreg45<def> = ADDXri %vreg44, <ga:@BZ2_indexIntoF>[TF=34], 0; GPR64sp:%vreg45 GPR64common:%vreg44
896B		%vreg46<def> = COPY %vreg45; GPR64all:%vreg46 GPR64sp:%vreg45
912B		%vreg48<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg48
928B		%vreg47<def> = COPY %vreg9; GPR64all:%vreg47 GPR64:%vreg9
944B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
960B		%X0<def> = COPY %vreg46; GPR64all:%vreg46
976B		%X1<def> = COPY %vreg47; GPR64all:%vreg47
992B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
1008B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1024B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1040B		STACKMAP 1, 0, %vreg48, %LR<earlyclobber,imp-def,dead>, ...; GPR32:%vreg48
1056B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1072B		%W0<def> = COPY %vreg48; GPR32:%vreg48
1088B		RET_ReallyLR %W0<imp-use>

# End machine code for function BZ2_indexIntoF.

********** SIMPLE REGISTER COALESCING **********
********** Function: BZ2_indexIntoF
********** JOINING INTERVALS ***********
do.body:
if.end:
do.cond:
if.then:
if.else:
entry:
16B	%vreg9<def> = COPY %LR; GPR64:%vreg9
	Considering merging %vreg9 with %LR
	Can only merge into reserved registers.
32B	%vreg2<def> = COPY %X1; GPR64:%vreg2
	Considering merging %vreg2 with %X1
	Can only merge into reserved registers.
48B	%vreg0<def> = COPY %W0; GPR32:%vreg0
	Considering merging %vreg0 with %W0
	Can only merge into reserved registers.
176B	%X0<def> = COPY %vreg7; GPR64all:%vreg7
	Considering merging %vreg7 with %X0
	Can only merge into reserved registers.
192B	%X1<def> = COPY %vreg8; GPR64all:%vreg8
	Considering merging %vreg8 with %X1
	Can only merge into reserved registers.
do.end:
960B	%X0<def> = COPY %vreg46; GPR64all:%vreg46
	Considering merging %vreg46 with %X0
	Can only merge into reserved registers.
976B	%X1<def> = COPY %vreg47; GPR64all:%vreg47
	Considering merging %vreg47 with %X1
	Can only merge into reserved registers.
1072B	%W0<def> = COPY %vreg48; GPR32:%vreg48
	Considering merging %vreg48 with %W0
	Can only merge into reserved registers.
64B	%vreg1<def> = COPY %vreg0; GPR32:%vreg1,%vreg0
	Considering merging to GPR32 with %vreg0 in %vreg1
		RHS = %vreg0 [48r,64r:0)  0@48r
		LHS = %vreg1 [64r,304r:0)  0@64r
		merge %vreg1:0@64r into %vreg0:0@48r --> @48r
		erased:	64r	%vreg1<def> = COPY %vreg0; GPR32:%vreg1,%vreg0
		updated: 48B	%vreg1<def> = COPY %W0; GPR32:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [48r,304r:0)  0@48r
80B	%vreg3<def> = COPY %vreg2; GPR64:%vreg3,%vreg2
	Considering merging to GPR64 with %vreg2 in %vreg3
		RHS = %vreg2 [32r,80r:0)  0@32r
		LHS = %vreg3 [80r,320r:0)  0@80r
		merge %vreg3:0@80r into %vreg2:0@32r --> @32r
		erased:	80r	%vreg3<def> = COPY %vreg2; GPR64:%vreg3,%vreg2
		updated: 32B	%vreg3<def> = COPY %X1; GPR64:%vreg3
	Success: %vreg2 -> %vreg3
	Result = %vreg3 [32r,320r:0)  0@32r
128B	%vreg7<def> = COPY %vreg6; GPR64all:%vreg7 GPR64sp:%vreg6
	Considering merging to GPR64sp with %vreg6 in %vreg7
		RHS = %vreg6 [112r,128r:0)  0@112r
		LHS = %vreg7 [128r,176r:0)  0@128r
		merge %vreg7:0@128r into %vreg6:0@112r --> @112r
		erased:	128r	%vreg7<def> = COPY %vreg6; GPR64all:%vreg7 GPR64sp:%vreg6
		updated: 112B	%vreg7<def> = ADDXri %vreg5, <ga:@BZ2_indexIntoF>[TF=34], 0; GPR64sp:%vreg7 GPR64common:%vreg5
	Success: %vreg6 -> %vreg7
	Result = %vreg7 [112r,176r:0)  0@112r
144B	%vreg8<def> = COPY %vreg9; GPR64all:%vreg8 GPR64:%vreg9
	Considering merging to GPR64 with %vreg9 in %vreg8
		RHS = %vreg9 [16r,928r:0)  0@16r
		LHS = %vreg8 [144r,192r:0)  0@144r
		merge %vreg8:0@144r into %vreg9:0@16r --> @16r
		erased:	144r	%vreg8<def> = COPY %vreg9; GPR64all:%vreg8 GPR64:%vreg9
		updated: 16B	%vreg8<def> = COPY %LR; GPR64:%vreg8
		updated: 928B	%vreg47<def> = COPY %vreg8; GPR64all:%vreg47 GPR64:%vreg8
	Success: %vreg9 -> %vreg8
	Result = %vreg8 [16r,928r:0)  0@16r
896B	%vreg46<def> = COPY %vreg45; GPR64all:%vreg46 GPR64sp:%vreg45
	Considering merging to GPR64sp with %vreg45 in %vreg46
		RHS = %vreg45 [880r,896r:0)  0@880r
		LHS = %vreg46 [896r,960r:0)  0@896r
		merge %vreg46:0@896r into %vreg45:0@880r --> @880r
		erased:	896r	%vreg46<def> = COPY %vreg45; GPR64all:%vreg46 GPR64sp:%vreg45
		updated: 880B	%vreg46<def> = ADDXri %vreg44, <ga:@BZ2_indexIntoF>[TF=34], 0; GPR64sp:%vreg46 GPR64common:%vreg44
	Success: %vreg45 -> %vreg46
	Result = %vreg46 [880r,960r:0)  0@880r
928B	%vreg47<def> = COPY %vreg8; GPR64all:%vreg47 GPR64:%vreg8
	Considering merging to GPR64 with %vreg8 in %vreg47
		RHS = %vreg8 [16r,928r:0)  0@16r
		LHS = %vreg47 [928r,976r:0)  0@928r
		merge %vreg47:0@928r into %vreg8:0@16r --> @16r
		erased:	928r	%vreg47<def> = COPY %vreg8; GPR64all:%vreg47 GPR64:%vreg8
		updated: 16B	%vreg47<def> = COPY %LR; GPR64:%vreg47
		updated: 192B	%X1<def> = COPY %vreg47; GPR64:%vreg47
	Success: %vreg8 -> %vreg47
	Result = %vreg47 [16r,976r:0)  0@16r
176B	%X0<def> = COPY %vreg7; GPR64sp:%vreg7
	Considering merging %vreg7 with %X0
	Can only merge into reserved registers.
192B	%X1<def> = COPY %vreg47; GPR64:%vreg47
	Considering merging %vreg47 with %X1
	Can only merge into reserved registers.
960B	%X0<def> = COPY %vreg46; GPR64sp:%vreg46
	Considering merging %vreg46 with %X0
	Can only merge into reserved registers.
976B	%X1<def> = COPY %vreg47; GPR64:%vreg47
	Considering merging %vreg47 with %X1
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
W30 [0B,16r:0)[208r,208d:4)[272e,272d:1)[992r,992d:2)[1040e,1040d:3)  0@0B-phi 1@272e 2@992r 3@1040e 4@208r
W0 [0B,48r:0)[176r,208r:3)[960r,992r:2)[1072r,1088r:1)  0@0B-phi 1@1072r 2@960r 3@176r
W1 [0B,32r:0)[192r,208r:2)[976r,992r:1)  0@0B-phi 1@976r 2@192r
%vreg1 [48r,304r:0)  0@48r
%vreg3 [32r,320r:0)  0@32r
%vreg4 [240r,352r:0)  0@240r
%vreg5 [96r,112r:0)  0@96r
%vreg7 [112r,176r:0)  0@112r
%vreg13 [560r,576r:0)  0@560r
%vreg16 [512r,528r:0)  0@512r
%vreg17 [528r,544r:0)  0@528r
%vreg18 [544r,560r:0)  0@544r
%vreg19 [496r,544r:0)  0@496r
%vreg23 [480r,528r:0)  0@480r
%vreg24 [464r,576r:0)  0@464r
%vreg27 [432r,448r:0)  0@432r
%vreg30 [416r,432r:0)  0@416r
%vreg31 [400r,416r:0)  0@400r
%vreg32 [384r,416r:0)  0@384r
%vreg34 [688r,704r:0)  0@688r
%vreg36 [624r,640r:0)  0@624r
%vreg40 [800r,816r:0)  0@800r
%vreg41 [784r,800r:0)  0@784r
%vreg42 [768r,800r:0)  0@768r
%vreg44 [864r,880r:0)  0@864r
%vreg46 [880r,960r:0)  0@880r
%vreg47 [16r,976r:0)  0@16r
%vreg48 [912r,1072r:0)  0@912r
RegMasks: 208r 992r
********** MACHINEINSTRS **********
# Machine code for function BZ2_indexIntoF: Post SSA
Frame Objects:
  fi#0: size=4, align=4, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=4, align=4, at location [SP]
  fi#3: size=4, align=4, at location [SP]
  fi#4: size=4, align=4, at location [SP]
Function Live Ins: %W0 in %vreg0, %X1 in %vreg2, %LR in %vreg9

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %W0 %X1 %LR
16B		%vreg47<def> = COPY %LR; GPR64:%vreg47
32B		%vreg3<def> = COPY %X1; GPR64:%vreg3
48B		%vreg1<def> = COPY %W0; GPR32:%vreg1
96B		%vreg5<def> = ADRP <ga:@BZ2_indexIntoF>[TF=1]; GPR64common:%vreg5
112B		%vreg7<def> = ADDXri %vreg5, <ga:@BZ2_indexIntoF>[TF=34], 0; GPR64sp:%vreg7 GPR64common:%vreg5
160B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
176B		%X0<def> = COPY %vreg7; GPR64sp:%vreg7
192B		%X1<def> = COPY %vreg47; GPR64:%vreg47
208B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
224B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
240B		%vreg4<def> = MOVi32imm 256; GPR32:%vreg4
256B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
272B		STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack0](align=4) LD8[FixedStack4](align=4) LD8[FixedStack3](align=4) LD8[FixedStack2](align=4) GPR64:%vreg3 GPR32:%vreg1
288B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
304B		STRWui %vreg1, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg1
320B		STRXui %vreg3, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg3
336B		STRWui %WZR, <fi#2>, 0; mem:ST4[FixedStack2]
352B		STRWui %vreg4, <fi#3>, 0; mem:ST4[FixedStack3] GPR32:%vreg4
	    Successors according to CFG: BB#1

368B	BB#1: derived from LLVM BB %do.body
	    Predecessors according to CFG: BB#0 BB#5
384B		%vreg32<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg32
400B		%vreg31<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg31
416B		%vreg30<def> = ADDWrr %vreg32, %vreg31; GPR32:%vreg30,%vreg32,%vreg31
432B		%vreg27<def> = SBFMWri %vreg30, 1, 31; GPR32:%vreg27,%vreg30
448B		STRWui %vreg27, <fi#4>, 0; mem:ST4[FixedStack4] GPR32:%vreg27
464B		%vreg24<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0] GPR32:%vreg24
480B		%vreg23<def> = LDRSWui <fi#4>, 0; mem:LD4[FixedStack4] GPR64:%vreg23
496B		%vreg19<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg19
512B		%vreg16<def> = MOVi64imm 4; GPR64:%vreg16
528B		%vreg17<def> = MADDXrrr %vreg23, %vreg16, %XZR; GPR64:%vreg17,%vreg23,%vreg16
544B		%vreg18<def> = ADDXrr %vreg19, %vreg17; GPR64common:%vreg18 GPR64:%vreg19,%vreg17
560B		%vreg13<def> = LDRWui %vreg18, 0; mem:LD4[%arrayidx] GPR32:%vreg13 GPR64common:%vreg18
576B		%WZR<def> = SUBSWrr %vreg24, %vreg13, %NZCV<imp-def>; GPR32:%vreg24,%vreg13
592B		Bcc 11, <BB#3>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#3 BB#2

608B	BB#2: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#1
624B		%vreg36<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg36
640B		STRWui %vreg36, <fi#2>, 0; mem:ST4[FixedStack2] GPR32:%vreg36
656B		B <BB#4>
	    Successors according to CFG: BB#4

672B	BB#3: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#1
688B		%vreg34<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg34
704B		STRWui %vreg34, <fi#3>, 0; mem:ST4[FixedStack3] GPR32:%vreg34
	    Successors according to CFG: BB#4

720B	BB#4: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#3 BB#2
736B		B <BB#5>
	    Successors according to CFG: BB#5

752B	BB#5: derived from LLVM BB %do.cond
	    Predecessors according to CFG: BB#4
768B		%vreg42<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg42
784B		%vreg41<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg41
800B		%vreg40<def> = SUBWrr %vreg42, %vreg41; GPR32common:%vreg40 GPR32:%vreg42,%vreg41
816B		%WZR<def> = SUBSWri %vreg40, 1, 0, %NZCV<imp-def>; GPR32common:%vreg40
832B		Bcc 1, <BB#1>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#1 BB#6

848B	BB#6: derived from LLVM BB %do.end
	    Predecessors according to CFG: BB#5
864B		%vreg44<def> = ADRP <ga:@BZ2_indexIntoF>[TF=1]; GPR64common:%vreg44
880B		%vreg46<def> = ADDXri %vreg44, <ga:@BZ2_indexIntoF>[TF=34], 0; GPR64sp:%vreg46 GPR64common:%vreg44
912B		%vreg48<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg48
944B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
960B		%X0<def> = COPY %vreg46; GPR64sp:%vreg46
976B		%X1<def> = COPY %vreg47; GPR64:%vreg47
992B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
1008B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1024B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1040B		STACKMAP 1, 0, %vreg48, %LR<earlyclobber,imp-def,dead>, ...; GPR32:%vreg48
1056B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1072B		%W0<def> = COPY %vreg48; GPR32:%vreg48
1088B		RET_ReallyLR %W0<imp-use>

# End machine code for function BZ2_indexIntoF.

handleMove 464B -> 504B: %vreg24<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0] GPR32:%vreg24
     %vreg24:	[464r,576r:0)  0@464r
        -->	[504r,576r:0)  0@504r
handleMove 880B -> 920B: %vreg46<def> = ADDXri %vreg44, <ga:@BZ2_indexIntoF>[TF=34], 0; GPR64sp:%vreg46 GPR64common:%vreg44
     %vreg46:	[880r,960r:0)  0@880r
        -->	[920r,960r:0)  0@920r
     %vreg44:	[864r,880r:0)  0@864r
        -->	[864r,920r:0)  0@864r
handleMove 864B -> 916B: %vreg44<def> = ADRP <ga:@BZ2_indexIntoF>[TF=1]; GPR64common:%vreg44
     %vreg44:	[864r,920r:0)  0@864r
        -->	[916r,920r:0)  0@916r
********** GREEDY REGISTER ALLOCATION **********
********** Function: BZ2_indexIntoF
********** INTERVALS **********
W30 [0B,16r:0)[208r,208d:4)[272e,272d:1)[992r,992d:2)[1040e,1040d:3)  0@0B-phi 1@272e 2@992r 3@1040e 4@208r
W0 [0B,48r:0)[176r,208r:3)[960r,992r:2)[1072r,1088r:1)  0@0B-phi 1@1072r 2@960r 3@176r
W1 [0B,32r:0)[192r,208r:2)[976r,992r:1)  0@0B-phi 1@976r 2@192r
%vreg1 [48r,304r:0)  0@48r
%vreg3 [32r,320r:0)  0@32r
%vreg4 [240r,352r:0)  0@240r
%vreg5 [96r,112r:0)  0@96r
%vreg7 [112r,176r:0)  0@112r
%vreg13 [560r,576r:0)  0@560r
%vreg16 [512r,528r:0)  0@512r
%vreg17 [528r,544r:0)  0@528r
%vreg18 [544r,560r:0)  0@544r
%vreg19 [496r,544r:0)  0@496r
%vreg23 [480r,528r:0)  0@480r
%vreg24 [504r,576r:0)  0@504r
%vreg27 [432r,448r:0)  0@432r
%vreg30 [416r,432r:0)  0@416r
%vreg31 [400r,416r:0)  0@400r
%vreg32 [384r,416r:0)  0@384r
%vreg34 [688r,704r:0)  0@688r
%vreg36 [624r,640r:0)  0@624r
%vreg40 [800r,816r:0)  0@800r
%vreg41 [784r,800r:0)  0@784r
%vreg42 [768r,800r:0)  0@768r
%vreg44 [916r,920r:0)  0@916r
%vreg46 [920r,960r:0)  0@920r
%vreg47 [16r,976r:0)  0@16r
%vreg48 [912r,1072r:0)  0@912r
RegMasks: 208r 992r
********** MACHINEINSTRS **********
# Machine code for function BZ2_indexIntoF: Post SSA
Frame Objects:
  fi#0: size=4, align=4, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=4, align=4, at location [SP]
  fi#3: size=4, align=4, at location [SP]
  fi#4: size=4, align=4, at location [SP]
Function Live Ins: %W0 in %vreg0, %X1 in %vreg2, %LR in %vreg9

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %W0 %X1 %LR
16B		%vreg47<def> = COPY %LR; GPR64:%vreg47
32B		%vreg3<def> = COPY %X1; GPR64:%vreg3
48B		%vreg1<def> = COPY %W0; GPR32:%vreg1
96B		%vreg5<def> = ADRP <ga:@BZ2_indexIntoF>[TF=1]; GPR64common:%vreg5
112B		%vreg7<def> = ADDXri %vreg5, <ga:@BZ2_indexIntoF>[TF=34], 0; GPR64sp:%vreg7 GPR64common:%vreg5
160B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
176B		%X0<def> = COPY %vreg7; GPR64sp:%vreg7
192B		%X1<def> = COPY %vreg47; GPR64:%vreg47
208B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
224B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
240B		%vreg4<def> = MOVi32imm 256; GPR32:%vreg4
256B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
272B		STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack0](align=4) LD8[FixedStack4](align=4) LD8[FixedStack3](align=4) LD8[FixedStack2](align=4) GPR64:%vreg3 GPR32:%vreg1
288B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
304B		STRWui %vreg1, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg1
320B		STRXui %vreg3, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg3
336B		STRWui %WZR, <fi#2>, 0; mem:ST4[FixedStack2]
352B		STRWui %vreg4, <fi#3>, 0; mem:ST4[FixedStack3] GPR32:%vreg4
	    Successors according to CFG: BB#1

368B	BB#1: derived from LLVM BB %do.body
	    Predecessors according to CFG: BB#0 BB#5
384B		%vreg32<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg32
400B		%vreg31<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg31
416B		%vreg30<def> = ADDWrr %vreg32, %vreg31; GPR32:%vreg30,%vreg32,%vreg31
432B		%vreg27<def> = SBFMWri %vreg30, 1, 31; GPR32:%vreg27,%vreg30
448B		STRWui %vreg27, <fi#4>, 0; mem:ST4[FixedStack4] GPR32:%vreg27
480B		%vreg23<def> = LDRSWui <fi#4>, 0; mem:LD4[FixedStack4] GPR64:%vreg23
496B		%vreg19<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg19
504B		%vreg24<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0] GPR32:%vreg24
512B		%vreg16<def> = MOVi64imm 4; GPR64:%vreg16
528B		%vreg17<def> = MADDXrrr %vreg23, %vreg16, %XZR; GPR64:%vreg17,%vreg23,%vreg16
544B		%vreg18<def> = ADDXrr %vreg19, %vreg17; GPR64common:%vreg18 GPR64:%vreg19,%vreg17
560B		%vreg13<def> = LDRWui %vreg18, 0; mem:LD4[%arrayidx] GPR32:%vreg13 GPR64common:%vreg18
576B		%WZR<def> = SUBSWrr %vreg24, %vreg13, %NZCV<imp-def>; GPR32:%vreg24,%vreg13
592B		Bcc 11, <BB#3>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#3 BB#2

608B	BB#2: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#1
624B		%vreg36<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg36
640B		STRWui %vreg36, <fi#2>, 0; mem:ST4[FixedStack2] GPR32:%vreg36
656B		B <BB#4>
	    Successors according to CFG: BB#4

672B	BB#3: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#1
688B		%vreg34<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg34
704B		STRWui %vreg34, <fi#3>, 0; mem:ST4[FixedStack3] GPR32:%vreg34
	    Successors according to CFG: BB#4

720B	BB#4: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#3 BB#2
736B		B <BB#5>
	    Successors according to CFG: BB#5

752B	BB#5: derived from LLVM BB %do.cond
	    Predecessors according to CFG: BB#4
768B		%vreg42<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg42
784B		%vreg41<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg41
800B		%vreg40<def> = SUBWrr %vreg42, %vreg41; GPR32common:%vreg40 GPR32:%vreg42,%vreg41
816B		%WZR<def> = SUBSWri %vreg40, 1, 0, %NZCV<imp-def>; GPR32common:%vreg40
832B		Bcc 1, <BB#1>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#1 BB#6

848B	BB#6: derived from LLVM BB %do.end
	    Predecessors according to CFG: BB#5
912B		%vreg48<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg48
916B		%vreg44<def> = ADRP <ga:@BZ2_indexIntoF>[TF=1]; GPR64common:%vreg44
920B		%vreg46<def> = ADDXri %vreg44, <ga:@BZ2_indexIntoF>[TF=34], 0; GPR64sp:%vreg46 GPR64common:%vreg44
944B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
960B		%X0<def> = COPY %vreg46; GPR64sp:%vreg46
976B		%X1<def> = COPY %vreg47; GPR64:%vreg47
992B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
1008B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1024B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1040B		STACKMAP 1, 0, %vreg48, %LR<earlyclobber,imp-def,dead>, ...; GPR32:%vreg48
1056B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1072B		%W0<def> = COPY %vreg48; GPR32:%vreg48
1088B		RET_ReallyLR %W0<imp-use>

# End machine code for function BZ2_indexIntoF.


selectOrSplit GPR64:%vreg47 [16r,976r:0)  0@16r w=2.227941e-03
hints: %X1
missed hint %X1
assigning %vreg47 to %X19: W19 [16r,976r:0)  0@16r

selectOrSplit GPR64:%vreg3 [32r,320r:0)  0@32r w=4.404070e-03
hints: %X1
missed hint %X1
assigning %vreg3 to %X20: W20 [32r,320r:0)  0@32r

selectOrSplit GPR32:%vreg1 [48r,304r:0)  0@48r w=4.618902e-03
hints: %W0
missed hint %W0
assigning %vreg1 to %W21: W21 [48r,304r:0)  0@48r

selectOrSplit GPR64sp:%vreg7 [112r,176r:0)  0@112r w=4.353448e-03
hints: %X0
assigning %vreg7 to %X0: W0 [112r,176r:0)  0@112r

selectOrSplit GPR32:%vreg48 [912r,1072r:0)  0@912r w=5.410714e-03
hints: %W0
missed hint %W0
assigning %vreg48 to %W20: W20 [912r,1072r:0)  0@912r

selectOrSplit GPR64sp:%vreg46 [920r,960r:0)  0@920r w=4.590909e-03
hints: %X0
assigning %vreg46 to %X0: W0 [920r,960r:0)  0@920r

selectOrSplit GPR64common:%vreg5 [96r,112r:0)  0@96r w=inf
assigning %vreg5 to %X8: W8 [96r,112r:0)  0@96r

selectOrSplit GPR32:%vreg4 [240r,352r:0)  0@240r w=1.953125e-03
assigning %vreg4 to %W8: W8 [240r,352r:0)  0@240r

selectOrSplit GPR32:%vreg32 [384r,416r:0)  0@384r w=9.259259e-03
assigning %vreg32 to %W8: W8 [384r,416r:0)  0@384r

selectOrSplit GPR32:%vreg31 [400r,416r:0)  0@400r w=inf
assigning %vreg31 to %W9: W9 [400r,416r:0)  0@400r

selectOrSplit GPR32:%vreg30 [416r,432r:0)  0@416r w=inf
assigning %vreg30 to %W8: W8 [416r,432r:0)  0@416r

selectOrSplit GPR32:%vreg27 [432r,448r:0)  0@432r w=inf
assigning %vreg27 to %W8: W8 [432r,448r:0)  0@432r

selectOrSplit GPR64:%vreg23 [480r,528r:0)  0@480r w=8.928572e-03
assigning %vreg23 to %X8: W8 [480r,528r:0)  0@480r

selectOrSplit GPR64:%vreg19 [496r,544r:0)  0@496r w=8.928572e-03
assigning %vreg19 to %X9: W9 [496r,544r:0)  0@496r

selectOrSplit GPR32:%vreg24 [504r,576r:0)  0@504r w=8.474576e-03
assigning %vreg24 to %W10: W10 [504r,576r:0)  0@504r

selectOrSplit GPR64:%vreg16 [512r,528r:0)  0@512r w=inf
assigning %vreg16 to %X11: W11 [512r,528r:0)  0@512r

selectOrSplit GPR64:%vreg17 [528r,544r:0)  0@528r w=inf
assigning %vreg17 to %X8: W8 [528r,544r:0)  0@528r

selectOrSplit GPR64common:%vreg18 [544r,560r:0)  0@544r w=inf
assigning %vreg18 to %X8: W8 [544r,560r:0)  0@544r

selectOrSplit GPR32:%vreg13 [560r,576r:0)  0@560r w=inf
assigning %vreg13 to %W8: W8 [560r,576r:0)  0@560r

selectOrSplit GPR32:%vreg36 [624r,640r:0)  0@624r w=inf
assigning %vreg36 to %W8: W8 [624r,640r:0)  0@624r

selectOrSplit GPR32:%vreg34 [688r,704r:0)  0@688r w=inf
assigning %vreg34 to %W8: W8 [688r,704r:0)  0@688r

selectOrSplit GPR32:%vreg42 [768r,800r:0)  0@768r w=9.259259e-03
assigning %vreg42 to %W8: W8 [768r,800r:0)  0@768r

selectOrSplit GPR32:%vreg41 [784r,800r:0)  0@784r w=inf
assigning %vreg41 to %W9: W9 [784r,800r:0)  0@784r

selectOrSplit GPR32common:%vreg40 [800r,816r:0)  0@800r w=inf
assigning %vreg40 to %W8: W8 [800r,816r:0)  0@800r

selectOrSplit GPR64common:%vreg44 [916r,920r:0)  0@916r w=inf
assigning %vreg44 to %X8: W8 [916r,920r:0)  0@916r

********** STACK TRANSFORMATION METADATA **********
********** Function: BZ2_indexIntoF
********** REGISTER MAP **********
[%vreg1 -> %W21] GPR32
[%vreg3 -> %X20] GPR64
[%vreg4 -> %W8] GPR32
[%vreg5 -> %X8] GPR64common
[%vreg7 -> %X0] GPR64sp
[%vreg13 -> %W8] GPR32
[%vreg16 -> %X11] GPR64
[%vreg17 -> %X8] GPR64
[%vreg18 -> %X8] GPR64common
[%vreg19 -> %X9] GPR64
[%vreg23 -> %X8] GPR64
[%vreg24 -> %W10] GPR32
[%vreg27 -> %W8] GPR32
[%vreg30 -> %W8] GPR32
[%vreg31 -> %W9] GPR32
[%vreg32 -> %W8] GPR32
[%vreg34 -> %W8] GPR32
[%vreg36 -> %W8] GPR32
[%vreg40 -> %W8] GPR32common
[%vreg41 -> %W9] GPR32
[%vreg42 -> %W8] GPR32
[%vreg44 -> %X8] GPR64common
[%vreg46 -> %X0] GPR64sp
[%vreg47 -> %X19] GPR64
[%vreg48 -> %W20] GPR32


Stackmap 0:
  STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack0](align=4) LD8[FixedStack4](align=4) LD8[FixedStack3](align=4) LD8[FixedStack2](align=4) GPR64:%vreg3 GPR32:%vreg1

i32* %cftab: in register %X20 (vreg 3)
i32** %cftab.addr: in stack slot 1 (size: 8)
i32 %indx: in register %W21 (vreg 1)
i32* %indx.addr: in stack slot 0 (size: 4)
i32* %mid: in stack slot 4 (size: 4)
i32* %na: in stack slot 3 (size: 4)
i32* %nb: in stack slot 2 (size: 4)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, %vreg48, %LR<earlyclobber,imp-def,dead>, ...; GPR32:%vreg48

i32 %10: in register %W20 (vreg 48)

Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack0](align=4) LD8[FixedStack4](align=4) LD8[FixedStack3](align=4) LD8[FixedStack2](align=4) GPR64:%vreg3 GPR32:%vreg1
  -> Call instruction SlotIndex 208B, searching vregs 0 -> 49 and stack slots 0 -> 5
    + vreg47 is live in register but not in stackmap
      Defining instruction: %vreg47<def> = COPY %LR; GPR64:%vreg47
      Value: generated value, 1 instruction(s)

  STACKMAP 1, 0, %vreg48, %LR<earlyclobber,imp-def,dead>, ...; GPR32:%vreg48
  -> Call instruction SlotIndex 992B, searching vregs 0 -> 49 and stack slots 0 -> 5

********** REWRITE VIRTUAL REGISTERS **********
********** Function: BZ2_indexIntoF
********** REGISTER MAP **********
[%vreg1 -> %W21] GPR32
[%vreg3 -> %X20] GPR64
[%vreg4 -> %W8] GPR32
[%vreg5 -> %X8] GPR64common
[%vreg7 -> %X0] GPR64sp
[%vreg13 -> %W8] GPR32
[%vreg16 -> %X11] GPR64
[%vreg17 -> %X8] GPR64
[%vreg18 -> %X8] GPR64common
[%vreg19 -> %X9] GPR64
[%vreg23 -> %X8] GPR64
[%vreg24 -> %W10] GPR32
[%vreg27 -> %W8] GPR32
[%vreg30 -> %W8] GPR32
[%vreg31 -> %W9] GPR32
[%vreg32 -> %W8] GPR32
[%vreg34 -> %W8] GPR32
[%vreg36 -> %W8] GPR32
[%vreg40 -> %W8] GPR32common
[%vreg41 -> %W9] GPR32
[%vreg42 -> %W8] GPR32
[%vreg44 -> %X8] GPR64common
[%vreg46 -> %X0] GPR64sp
[%vreg47 -> %X19] GPR64
[%vreg48 -> %W20] GPR32

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %LR %W0 %X1
16B		%vreg47<def> = COPY %LR; GPR64:%vreg47
32B		%vreg3<def> = COPY %X1; GPR64:%vreg3
48B		%vreg1<def> = COPY %W0; GPR32:%vreg1
96B		%vreg5<def> = ADRP <ga:@BZ2_indexIntoF>[TF=1]; GPR64common:%vreg5
112B		%vreg7<def> = ADDXri %vreg5<kill>, <ga:@BZ2_indexIntoF>[TF=34], 0; GPR64sp:%vreg7 GPR64common:%vreg5
160B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
176B		%X0<def> = COPY %vreg7<kill>; GPR64sp:%vreg7
192B		%X1<def> = COPY %vreg47; GPR64:%vreg47
208B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
224B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
240B		%vreg4<def> = MOVi32imm 256; GPR32:%vreg4
256B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
272B		STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack0](align=4) LD8[FixedStack4](align=4) LD8[FixedStack3](align=4) LD8[FixedStack2](align=4) GPR64:%vreg3 GPR32:%vreg1
288B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
304B		STRWui %vreg1<kill>, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg1
320B		STRXui %vreg3<kill>, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg3
336B		STRWui %WZR, <fi#2>, 0; mem:ST4[FixedStack2]
352B		STRWui %vreg4<kill>, <fi#3>, 0; mem:ST4[FixedStack3] GPR32:%vreg4
	    Successors according to CFG: BB#1
> %X19<def> = COPY %LR
> %X20<def> = COPY %X1
> %W21<def> = COPY %W0
> %X8<def> = ADRP <ga:@BZ2_indexIntoF>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@BZ2_indexIntoF>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19
> BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W8<def> = MOVi32imm 256
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 0, 0, %X20, 0, <fi#1>, 0, %W21, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack0](align=4) LD8[FixedStack4](align=4) LD8[FixedStack3](align=4) LD8[FixedStack2](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRWui %W21<kill>, <fi#0>, 0; mem:ST4[FixedStack0]
> STRXui %X20<kill>, <fi#1>, 0; mem:ST8[FixedStack1]
> STRWui %WZR, <fi#2>, 0; mem:ST4[FixedStack2]
> STRWui %W8<kill>, <fi#3>, 0; mem:ST4[FixedStack3]
368B	BB#1: derived from LLVM BB %do.body
	    Live Ins: %X19
	    Predecessors according to CFG: BB#0 BB#5
384B		%vreg32<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg32
400B		%vreg31<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg31
416B		%vreg30<def> = ADDWrr %vreg32<kill>, %vreg31<kill>; GPR32:%vreg30,%vreg32,%vreg31
432B		%vreg27<def> = SBFMWri %vreg30<kill>, 1, 31; GPR32:%vreg27,%vreg30
448B		STRWui %vreg27<kill>, <fi#4>, 0; mem:ST4[FixedStack4] GPR32:%vreg27
480B		%vreg23<def> = LDRSWui <fi#4>, 0; mem:LD4[FixedStack4] GPR64:%vreg23
496B		%vreg19<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg19
504B		%vreg24<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0] GPR32:%vreg24
512B		%vreg16<def> = MOVi64imm 4; GPR64:%vreg16
528B		%vreg17<def> = MADDXrrr %vreg23<kill>, %vreg16<kill>, %XZR; GPR64:%vreg17,%vreg23,%vreg16
544B		%vreg18<def> = ADDXrr %vreg19<kill>, %vreg17<kill>; GPR64common:%vreg18 GPR64:%vreg19,%vreg17
560B		%vreg13<def> = LDRWui %vreg18<kill>, 0; mem:LD4[%arrayidx] GPR32:%vreg13 GPR64common:%vreg18
576B		%WZR<def> = SUBSWrr %vreg24<kill>, %vreg13<kill>, %NZCV<imp-def>; GPR32:%vreg24,%vreg13
592B		Bcc 11, <BB#3>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#3 BB#2
> %W8<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2]
> %W9<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3]
> %W8<def> = ADDWrr %W8<kill>, %W9<kill>
> %W8<def> = SBFMWri %W8<kill>, 1, 31
> STRWui %W8<kill>, <fi#4>, 0; mem:ST4[FixedStack4]
> %X8<def> = LDRSWui <fi#4>, 0; mem:LD4[FixedStack4]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W10<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0]
> %X11<def> = MOVi64imm 4
> %X8<def> = MADDXrrr %X8<kill>, %X11<kill>, %XZR
> %X8<def> = ADDXrr %X9<kill>, %X8<kill>
> %W8<def> = LDRWui %X8<kill>, 0; mem:LD4[%arrayidx]
> %WZR<def> = SUBSWrr %W10<kill>, %W8<kill>, %NZCV<imp-def>
> Bcc 11, <BB#3>, %NZCV<imp-use,kill>
608B	BB#2: derived from LLVM BB %if.then
	    Live Ins: %X19
	    Predecessors according to CFG: BB#1
624B		%vreg36<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg36
640B		STRWui %vreg36<kill>, <fi#2>, 0; mem:ST4[FixedStack2] GPR32:%vreg36
656B		B <BB#4>
	    Successors according to CFG: BB#4
> %W8<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4]
> STRWui %W8<kill>, <fi#2>, 0; mem:ST4[FixedStack2]
> B <BB#4>
672B	BB#3: derived from LLVM BB %if.else
	    Live Ins: %X19
	    Predecessors according to CFG: BB#1
688B		%vreg34<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg34
704B		STRWui %vreg34<kill>, <fi#3>, 0; mem:ST4[FixedStack3] GPR32:%vreg34
	    Successors according to CFG: BB#4
> %W8<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4]
> STRWui %W8<kill>, <fi#3>, 0; mem:ST4[FixedStack3]
720B	BB#4: derived from LLVM BB %if.end
	    Live Ins: %X19
	    Predecessors according to CFG: BB#3 BB#2
736B		B <BB#5>
	    Successors according to CFG: BB#5
> B <BB#5>
752B	BB#5: derived from LLVM BB %do.cond
	    Live Ins: %X19
	    Predecessors according to CFG: BB#4
768B		%vreg42<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg42
784B		%vreg41<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg41
800B		%vreg40<def> = SUBWrr %vreg42<kill>, %vreg41<kill>; GPR32common:%vreg40 GPR32:%vreg42,%vreg41
816B		%WZR<def> = SUBSWri %vreg40<kill>, 1, 0, %NZCV<imp-def>; GPR32common:%vreg40
832B		Bcc 1, <BB#1>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#1 BB#6
> %W8<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3]
> %W9<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2]
> %W8<def> = SUBWrr %W8<kill>, %W9<kill>
> %WZR<def> = SUBSWri %W8<kill>, 1, 0, %NZCV<imp-def>
> Bcc 1, <BB#1>, %NZCV<imp-use,kill>
848B	BB#6: derived from LLVM BB %do.end
	    Live Ins: %X19
	    Predecessors according to CFG: BB#5
912B		%vreg48<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg48
916B		%vreg44<def> = ADRP <ga:@BZ2_indexIntoF>[TF=1]; GPR64common:%vreg44
920B		%vreg46<def> = ADDXri %vreg44<kill>, <ga:@BZ2_indexIntoF>[TF=34], 0; GPR64sp:%vreg46 GPR64common:%vreg44
944B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
960B		%X0<def> = COPY %vreg46<kill>; GPR64sp:%vreg46
976B		%X1<def> = COPY %vreg47<kill>; GPR64:%vreg47
992B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
1008B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1024B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1040B		STACKMAP 1, 0, %vreg48, %LR<earlyclobber,imp-def,dead>, ...; GPR32:%vreg48
1056B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1072B		%W0<def> = COPY %vreg48<kill>; GPR32:%vreg48
1088B		RET_ReallyLR %W0<imp-use>
> %W20<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2]
> %X8<def> = ADRP <ga:@BZ2_indexIntoF>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@BZ2_indexIntoF>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19<kill>
> BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 1, 0, %W20, %LR<earlyclobber,imp-def,dead>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = COPY %W20<kill>
> RET_ReallyLR %W0<imp-use>
Computing live-in reg-units in ABI blocks.
0B	BB#0 W0#0 W30#0
Created 2 new intervals.
********** INTERVALS **********
W30 [0B,16r:0)[176r,176d:16)[224e,224d:8)[1104r,1104d:14)[1184e,1184d:7)[1312r,1312d:15)[1392e,1392d:6)[2192r,2192d:13)[2256e,2256d:5)[2496r,2496d:12)[2560e,2560d:4)[3296r,3296d:11)[3360e,3360d:3)[3760r,3760d:10)[3824e,3824d:2)[4432r,4432d:9)[4480e,4480d:1)  0@0B-phi 1@4480e 2@3824e 3@3360e 4@2560e 5@2256e 6@1392e 7@1184e 8@224e 9@4432r 10@3760r 11@3296r 12@2496r 13@2192r 14@1104r 15@1312r 16@176r
W0 [0B,32r:0)[144r,176r:15)[1088r,1104r:13)[1104r,1136r:6)[1296r,1312r:14)[1312r,1344r:7)[2128r,2192r:12)[2192r,2224r:5)[2464r,2496r:11)[2496r,2528r:4)[3280r,3296r:10)[3296r,3328r:3)[3696r,3760r:9)[3760r,3792r:2)[4400r,4432r:8)[4528r,4544r:1)  0@0B-phi 1@4528r 2@3760r 3@3296r 4@2496r 5@2192r 6@1104r 7@1312r 8@4400r 9@3696r 10@3280r 11@2464r 12@2128r 13@1088r 14@1296r 15@144r
%vreg0 [32r,48r:0)  0@32r
%vreg1 [48r,256r:0)  0@48r
%vreg3 [272r,288r:0)  0@272r
%vreg4 [64r,80r:0)  0@64r
%vreg5 [80r,96r:0)  0@80r
%vreg6 [96r,144r:0)  0@96r
%vreg7 [112r,160r:0)  0@112r
%vreg8 [16r,4368r:0)  0@16r
%vreg10 [448r,464r:0)  0@448r
%vreg13 [416r,432r:0)  0@416r
%vreg15 [400r,416r:0)  0@400r
%vreg16 [384r,400r:0)  0@384r
%vreg19 [592r,608r:0)  0@592r
%vreg21 [576r,608r:0)  0@576r
%vreg22 [560r,576r:0)  0@560r
%vreg25 [768r,784r:0)  0@768r
%vreg26 [752r,768r:0)  0@752r
%vreg29 [912r,928r:0)  0@912r
%vreg30 [896r,912r:0)  0@896r
%vreg32 [1008r,1024r:0)  0@1008r
%vreg34 [992r,1008r:0)  0@992r
%vreg35 [976r,992r:0)  0@976r
%vreg36 [1360r,1424r:0)  0@1360r
%vreg38 [1344r,1360r:0)  0@1344r
%vreg39 [1264r,1296r:0)  0@1264r
%vreg40 [1152r,1216r:0)  0@1152r
%vreg42 [1136r,1152r:0)  0@1136r
%vreg43 [1056r,1088r:0)  0@1056r
%vreg45 [1472r,1488r:0)  0@1472r
%vreg46 [1456r,1472r:0)  0@1456r
%vreg50 [1680r,1696r:0)  0@1680r
%vreg52 [1632r,1648r:0)  0@1632r
%vreg53 [1648r,1664r:0)  0@1648r
%vreg54 [1664r,1680r:0)  0@1664r
%vreg55 [1616r,1648r:0)  0@1616r
%vreg57 [1600r,1696r:0)  0@1600r
%vreg58 [1584r,1600r:0)  0@1584r
%vreg61 [1760r,1776r:0)  0@1760r
%vreg62 [1744r,1760r:0)  0@1744r
%vreg65 [1920r,1936r:0)  0@1920r
%vreg66 [1904r,1920r:0)  0@1904r
%vreg69 [1872r,1888r:0)  0@1872r
%vreg71 [1808r,1856r:0)  0@1808r
%vreg72 [1856r,1888r:0)  0@1856r
%vreg74 [1840r,1856r:0)  0@1840r
%vreg75 [1824r,1840r:0)  0@1824r
%vreg79 [2112r,2144r:0)  0@2112r
%vreg80 [2224r,2224d:0)  0@2224r
%vreg82 [2080r,2176r:0)  0@2080r
%vreg83 [2064r,2080r:0)  0@2064r
%vreg85 [2048r,2160r:0)  0@2048r
%vreg86 [2032r,2048r:0)  0@2032r
%vreg87 [1984r,2000r:0)  0@1984r
%vreg88 [2000r,2016r:0)  0@2000r
%vreg89 [2016r,2128r:0)  0@2016r
%vreg92 [2320r,2336r:0)  0@2320r
%vreg93 [2304r,2320r:0)  0@2304r
%vreg95 [2448r,2480r:0)  0@2448r
%vreg96 [2528r,2528d:0)  0@2528r
%vreg97 [2384r,2400r:0)  0@2384r
%vreg98 [2400r,2416r:0)  0@2400r
%vreg99 [2416r,2464r:0)  0@2416r
%vreg103 [2656r,2672r:0)  0@2656r
%vreg104 [2640r,2656r:0)  0@2640r
%vreg106 [2624r,2672r:0)  0@2624r
%vreg107 [2608r,2624r:0)  0@2608r
%vreg108 [2784r,3040r:0)  0@2784r
%vreg110 [3024r,3040r:0)  0@3024r
%vreg115 [2992r,3008r:0)  0@2992r
%vreg116 [2976r,2992r:0)  0@2976r
%vreg117 [2960r,3008r:0)  0@2960r
%vreg119 [2944r,2992r:0)  0@2944r
%vreg120 [2928r,2944r:0)  0@2928r
%vreg123 [2896r,2912r:0)  0@2896r
%vreg126 [2880r,2912r:0)  0@2880r
%vreg128 [2864r,2880r:0)  0@2864r
%vreg130 [2848r,2864r:0)  0@2848r
%vreg131 [2832r,2848r:0)  0@2832r
%vreg133 [2816r,2880r:0)  0@2816r
%vreg134 [2800r,2816r:0)  0@2800r
%vreg137 [3184r,3200r:0)  0@3184r
%vreg138 [3168r,3184r:0)  0@3168r
%vreg140 [3408r,3424r:0)  0@3408r
%vreg143 [3328r,3392r:0)  0@3328r
%vreg144 [3248r,3280r:0)  0@3248r
%vreg147 [4128r,4144r:0)  0@4128r
%vreg148 [4112r,4128r:0)  0@4112r
%vreg150 [4192r,4208r:0)  0@4192r
%vreg153 [3488r,3504r:0)  0@3488r
%vreg154 [3472r,3488r:0)  0@3472r
%vreg158 [3680r,3712r:0)  0@3680r
%vreg159 [3792r,3792d:0)  0@3792r
%vreg161 [3648r,3744r:0)  0@3648r
%vreg162 [3632r,3648r:0)  0@3632r
%vreg164 [3616r,3728r:0)  0@3616r
%vreg165 [3600r,3616r:0)  0@3600r
%vreg166 [3552r,3568r:0)  0@3552r
%vreg167 [3568r,3584r:0)  0@3568r
%vreg168 [3584r,3696r:0)  0@3584r
%vreg172 [3920r,3936r:0)  0@3920r
%vreg173 [3904r,3920r:0)  0@3904r
%vreg175 [3888r,3936r:0)  0@3888r
%vreg176 [3872r,3888r:0)  0@3872r
%vreg178 [4048r,4064r:0)  0@4048r
%vreg179 [3984r,4000r:0)  0@3984r
%vreg180 [2720r,2736r:0)  0@2720r
%vreg181 [1520r,1536r:0)  0@1520r
%vreg182 [832r,848r:0)  0@832r
%vreg183 [656r,672r:0)  0@656r
%vreg184 [496r,512r:0)  0@496r
%vreg185 [320r,336r:0)  0@320r
%vreg187 [4512r,4528r:0)  0@4512r
%vreg188 [4320r,4336r:0)  0@4320r
%vreg189 [4336r,4352r:0)  0@4336r
%vreg190 [4352r,4400r:0)  0@4352r
%vreg191 [4368r,4416r:0)  0@4368r
RegMasks: 176r 1104r 1312r 2192r 2496r 3296r 3760r 4432r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzDecompress: Post SSA
Frame Objects:
  fi#0: size=4, align=4, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=1, align=1, at location [SP]
  fi#3: size=8, align=8, at location [SP]
  fi#4: size=4, align=4, at location [SP]
Function Live Ins: %X0 in %vreg0, %LR in %vreg8

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %LR
16B		%vreg8<def> = COPY %LR; GPR64:%vreg8
32B		%vreg0<def> = COPY %X0; GPR64:%vreg0
48B		%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
64B		%vreg4<def> = ADRP <ga:@BZ2_bzDecompress>[TF=1]; GPR64common:%vreg4
80B		%vreg5<def> = ADDXri %vreg4, <ga:@BZ2_bzDecompress>[TF=34], 0; GPR64sp:%vreg5 GPR64common:%vreg4
96B		%vreg6<def> = COPY %vreg5; GPR64all:%vreg6 GPR64sp:%vreg5
112B		%vreg7<def> = COPY %vreg8; GPR64all:%vreg7 GPR64:%vreg8
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		%X0<def> = COPY %vreg6; GPR64all:%vreg6
160B		%X1<def> = COPY %vreg7; GPR64all:%vreg7
176B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
224B		STACKMAP 0, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, %vreg1, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3] LD8[FixedStack1] GPR64:%vreg1
240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
256B		STRXui %vreg1, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg1
272B		%vreg3<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg3
288B		CBNZX %vreg3, <BB#2>; GPR64:%vreg3
	    Successors according to CFG: BB#2 BB#1

304B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
320B		%vreg185<def> = MOVi32imm 4294967294; GPR32:%vreg185
336B		STRWui %vreg185, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg185
352B		B <BB#37>
	    Successors according to CFG: BB#37

368B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0
384B		%vreg16<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg16
400B		%vreg15<def> = LDRXui %vreg16, 6; mem:LD8[%state] GPR64:%vreg15 GPR64common:%vreg16
416B		%vreg13<def> = COPY %vreg15; GPR64:%vreg13,%vreg15
432B		STRXui %vreg13, <fi#3>, 0; mem:ST8[FixedStack3] GPR64:%vreg13
448B		%vreg10<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg10
464B		CBNZX %vreg10, <BB#4>; GPR64:%vreg10
	    Successors according to CFG: BB#4 BB#3

480B	BB#3: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#2
496B		%vreg184<def> = MOVi32imm 4294967294; GPR32:%vreg184
512B		STRWui %vreg184, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg184
528B		B <BB#37>
	    Successors according to CFG: BB#37

544B	BB#4: derived from LLVM BB %if.end.3
	    Predecessors according to CFG: BB#2
560B		%vreg22<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg22
576B		%vreg21<def> = LDRXui %vreg22, 0; mem:LD8[%strm4] GPR64:%vreg21 GPR64common:%vreg22
592B		%vreg19<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg19
608B		%XZR<def> = SUBSXrr %vreg21, %vreg19, %NZCV<imp-def>; GPR64:%vreg21,%vreg19
624B		Bcc 0, <BB#6>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#6 BB#5

640B	BB#5: derived from LLVM BB %if.then.6
	    Predecessors according to CFG: BB#4
656B		%vreg183<def> = MOVi32imm 4294967294; GPR32:%vreg183
672B		STRWui %vreg183, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg183
688B		B <BB#37>
	    Successors according to CFG: BB#37

704B	BB#6: derived from LLVM BB %if.end.7
	    Predecessors according to CFG: BB#4
720B		B <BB#7>
	    Successors according to CFG: BB#7

736B	BB#7: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#6 BB#36
752B		%vreg26<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg26
768B		%vreg25<def> = LDRWui %vreg26, 2; mem:LD4[%state8] GPR32common:%vreg25 GPR64common:%vreg26
784B		%WZR<def> = SUBSWri %vreg25, 1, 0, %NZCV<imp-def>; GPR32common:%vreg25
800B		Bcc 1, <BB#9>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#9 BB#8

816B	BB#8: derived from LLVM BB %if.then.10
	    Predecessors according to CFG: BB#7
832B		%vreg182<def> = MOVi32imm 4294967295; GPR32:%vreg182
848B		STRWui %vreg182, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg182
864B		B <BB#37>
	    Successors according to CFG: BB#37

880B	BB#9: derived from LLVM BB %if.end.11
	    Predecessors according to CFG: BB#7
896B		%vreg30<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg30
912B		%vreg29<def> = LDRWui %vreg30, 2; mem:LD4[%state12] GPR32common:%vreg29 GPR64common:%vreg30
928B		%WZR<def> = SUBSWri %vreg29, 2, 0, %NZCV<imp-def>; GPR32common:%vreg29
944B		Bcc 1, <BB#26>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#26 BB#10

960B	BB#10: derived from LLVM BB %if.then.14
	    Predecessors according to CFG: BB#9
976B		%vreg35<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg35
992B		%vreg34<def> = LDRBBui %vreg35, 44; mem:LD1[%smallDecompress] GPR32:%vreg34 GPR64common:%vreg35
1008B		%vreg32<def> = UBFMWri %vreg34, 0, 7; GPR32:%vreg32,%vreg34
1024B		CBZW %vreg32, <BB#12>; GPR32:%vreg32
	    Successors according to CFG: BB#12 BB#11

1040B	BB#11: derived from LLVM BB %if.then.15
	    Predecessors according to CFG: BB#10
1056B		%vreg43<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg43
1072B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1088B		%X0<def> = COPY %vreg43; GPR64:%vreg43
1104B		BL <ga:@unRLE_obuf_to_output_SMALL>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>
1120B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1136B		%vreg42<def> = COPY %W0; GPR32:%vreg42
1152B		%vreg40<def> = COPY %vreg42; GPR32:%vreg40,%vreg42
1168B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1184B		STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
1200B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1216B		STRBBui %vreg40, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg40
1232B		B <BB#13>
	    Successors according to CFG: BB#13

1248B	BB#12: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#10
1264B		%vreg39<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg39
1280B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1296B		%X0<def> = COPY %vreg39; GPR64:%vreg39
1312B		BL <ga:@unRLE_obuf_to_output_FAST>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>
1328B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1344B		%vreg38<def> = COPY %W0; GPR32:%vreg38
1360B		%vreg36<def> = COPY %vreg38; GPR32:%vreg36,%vreg38
1376B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1392B		STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
1408B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1424B		STRBBui %vreg36, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg36
	    Successors according to CFG: BB#13

1440B	BB#13: derived from LLVM BB %if.end.17
	    Predecessors according to CFG: BB#12 BB#11
1456B		%vreg46<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg46
1472B		%vreg45<def> = UBFMWri %vreg46, 0, 7; GPR32:%vreg45,%vreg46
1488B		CBZW %vreg45, <BB#15>; GPR32:%vreg45
	    Successors according to CFG: BB#15 BB#14

1504B	BB#14: derived from LLVM BB %if.then.19
	    Predecessors according to CFG: BB#13
1520B		%vreg181<def> = MOVi32imm 4294967292; GPR32:%vreg181
1536B		STRWui %vreg181, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg181
1552B		B <BB#37>
	    Successors according to CFG: BB#37

1568B	BB#15: derived from LLVM BB %if.end.20
	    Predecessors according to CFG: BB#13
1584B		%vreg58<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg58
1600B		%vreg57<def> = LDRWui %vreg58, 273; mem:LD4[%nblock_used] GPR32:%vreg57 GPR64common:%vreg58
1616B		%vreg55<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg55
1632B		%vreg52<def> = MOVi64imm 64080; GPR64:%vreg52
1648B		%vreg53<def> = ADDXrr %vreg55, %vreg52; GPR64common:%vreg53 GPR64:%vreg55,%vreg52
1664B		%vreg54<def> = LDRWui %vreg53, 0; mem:LD4[%save_nblock] GPR32common:%vreg54 GPR64common:%vreg53
1680B		%vreg50<def> = ADDWri %vreg54, 1, 0; GPR32common:%vreg50,%vreg54
1696B		%WZR<def> = SUBSWrr %vreg57, %vreg50, %NZCV<imp-def>; GPR32:%vreg57 GPR32common:%vreg50
1712B		Bcc 1, <BB#24>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#24 BB#16

1728B	BB#16: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#15
1744B		%vreg62<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg62
1760B		%vreg61<def> = LDRWui %vreg62, 4; mem:LD4[%state_out_len] GPR32:%vreg61 GPR64common:%vreg62
1776B		CBNZW %vreg61, <BB#24>; GPR32:%vreg61
	    Successors according to CFG: BB#24 BB#17

1792B	BB#17: derived from LLVM BB %if.then.23
	    Predecessors according to CFG: BB#16
1808B		%vreg71<def> = MOVi32imm 4294967295; GPR32:%vreg71
1824B		%vreg75<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg75
1840B		%vreg74<def> = LDRWui %vreg75, 796; mem:LD4[%calculatedBlockCRC] GPR32:%vreg74 GPR64common:%vreg75
1856B		%vreg72<def> = EORWrr %vreg74, %vreg71; GPR32:%vreg72,%vreg74,%vreg71
1872B		%vreg69<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg69
1888B		STRWui %vreg72, %vreg69, 796; mem:ST4[%calculatedBlockCRC24] GPR32:%vreg72 GPR64common:%vreg69
1904B		%vreg66<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg66
1920B		%vreg65<def> = LDRWui %vreg66, 13; mem:LD4[%verbosity] GPR32common:%vreg65 GPR64common:%vreg66
1936B		%WZR<def> = SUBSWri %vreg65, 3, 0, %NZCV<imp-def>; GPR32common:%vreg65
1952B		Bcc 11, <BB#19>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#19 BB#18

1968B	BB#18: derived from LLVM BB %if.then.26
	    Predecessors according to CFG: BB#17
1984B		%vreg87<def> = ADRP <ga:@stderr>[TF=1]; GPR64common:%vreg87
2000B		%vreg88<def> = ADDXri %vreg87, <ga:@stderr>[TF=34], 0; GPR64sp:%vreg88 GPR64common:%vreg87
2016B		%vreg89<def> = LDRXui %vreg88, 0; mem:LD8[@stderr] GPR64:%vreg89 GPR64sp:%vreg88
2032B		%vreg86<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg86
2048B		%vreg85<def> = LDRWui %vreg86, 794; mem:LD4[%storedBlockCRC] GPR32:%vreg85 GPR64common:%vreg86
2064B		%vreg83<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg83
2080B		%vreg82<def> = LDRWui %vreg83, 796; mem:LD4[%calculatedBlockCRC27] GPR32:%vreg82 GPR64common:%vreg83
2096B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2112B		%vreg79<def> = MOVaddr <ga:@bzlib__str_2___0x_08x__>[TF=1], <ga:@bzlib__str_2___0x_08x__>[TF=34]; GPR64:%vreg79
2128B		%X0<def> = COPY %vreg89; GPR64:%vreg89
2144B		%X1<def> = COPY %vreg79; GPR64:%vreg79
2160B		%W2<def> = COPY %vreg85; GPR32:%vreg85
2176B		%W3<def> = COPY %vreg82; GPR32:%vreg82
2192B		BL <ga:@fprintf>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %W2<imp-use,kill>, %W3<imp-use,kill>, %SP<imp-def>, %W0<imp-def>
2208B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2224B		%vreg80<def,dead> = COPY %W0; GPR32all:%vreg80
2240B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2256B		STACKMAP 3, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
2272B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#19

2288B	BB#19: derived from LLVM BB %if.end.29
	    Predecessors according to CFG: BB#17 BB#18
2304B		%vreg93<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg93
2320B		%vreg92<def> = LDRWui %vreg93, 13; mem:LD4[%verbosity30] GPR32common:%vreg92 GPR64common:%vreg93
2336B		%WZR<def> = SUBSWri %vreg92, 2, 0, %NZCV<imp-def>; GPR32common:%vreg92
2352B		Bcc 11, <BB#21>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#21 BB#20

2368B	BB#20: derived from LLVM BB %if.then.32
	    Predecessors according to CFG: BB#19
2384B		%vreg97<def> = ADRP <ga:@stderr>[TF=1]; GPR64common:%vreg97
2400B		%vreg98<def> = ADDXri %vreg97, <ga:@stderr>[TF=34], 0; GPR64sp:%vreg98 GPR64common:%vreg97
2416B		%vreg99<def> = LDRXui %vreg98, 0; mem:LD8[@stderr] GPR64:%vreg99 GPR64sp:%vreg98
2432B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2448B		%vreg95<def> = MOVaddr <ga:@bzlib__str_3___>[TF=1], <ga:@bzlib__str_3___>[TF=34]; GPR64:%vreg95
2464B		%X0<def> = COPY %vreg99; GPR64:%vreg99
2480B		%X1<def> = COPY %vreg95; GPR64:%vreg95
2496B		BL <ga:@fprintf>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %SP<imp-def>, %W0<imp-def>
2512B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2528B		%vreg96<def,dead> = COPY %W0; GPR32all:%vreg96
2544B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2560B		STACKMAP 4, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
2576B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#21

2592B	BB#21: derived from LLVM BB %if.end.34
	    Predecessors according to CFG: BB#19 BB#20
2608B		%vreg107<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg107
2624B		%vreg106<def> = LDRWui %vreg107, 796; mem:LD4[%calculatedBlockCRC35] GPR32:%vreg106 GPR64common:%vreg107
2640B		%vreg104<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg104
2656B		%vreg103<def> = LDRWui %vreg104, 794; mem:LD4[%storedBlockCRC36] GPR32:%vreg103 GPR64common:%vreg104
2672B		%WZR<def> = SUBSWrr %vreg106, %vreg103, %NZCV<imp-def>; GPR32:%vreg106,%vreg103
2688B		Bcc 0, <BB#23>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#23 BB#22

2704B	BB#22: derived from LLVM BB %if.then.38
	    Predecessors according to CFG: BB#21
2720B		%vreg180<def> = MOVi32imm 4294967292; GPR32:%vreg180
2736B		STRWui %vreg180, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg180
2752B		B <BB#37>
	    Successors according to CFG: BB#37

2768B	BB#23: derived from LLVM BB %if.end.39
	    Predecessors according to CFG: BB#21
2784B		%vreg108<def> = MOVi32imm 14; GPR32:%vreg108
2800B		%vreg134<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg134
2816B		%vreg133<def> = LDRWui %vreg134, 797; mem:LD4[%calculatedCombinedCRC] GPR32:%vreg133 GPR64common:%vreg134
2832B		%vreg131<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg131
2848B		%vreg130<def> = LDRWui %vreg131, 797; mem:LD4[%calculatedCombinedCRC40] GPR32:%vreg130 GPR64common:%vreg131
2864B		%vreg128<def> = UBFMWri %vreg130, 31, 31; GPR32:%vreg128,%vreg130
2880B		%vreg126<def> = ORRWrs %vreg128, %vreg133, 1; GPR32:%vreg126,%vreg128,%vreg133
2896B		%vreg123<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg123
2912B		STRWui %vreg126, %vreg123, 797; mem:ST4[%calculatedCombinedCRC41] GPR32:%vreg126 GPR64common:%vreg123
2928B		%vreg120<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg120
2944B		%vreg119<def> = LDRWui %vreg120, 796; mem:LD4[%calculatedBlockCRC42] GPR32:%vreg119 GPR64common:%vreg120
2960B		%vreg117<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg117
2976B		%vreg116<def> = LDRWui %vreg117, 797; mem:LD4[%calculatedCombinedCRC43] GPR32:%vreg116 GPR64common:%vreg117
2992B		%vreg115<def> = EORWrr %vreg116, %vreg119; GPR32:%vreg115,%vreg116,%vreg119
3008B		STRWui %vreg115, %vreg117, 797; mem:ST4[%calculatedCombinedCRC43] GPR32:%vreg115 GPR64common:%vreg117
3024B		%vreg110<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg110
3040B		STRWui %vreg108, %vreg110, 2; mem:ST4[%state44] GPR32:%vreg108 GPR64common:%vreg110
3056B		B <BB#25>
	    Successors according to CFG: BB#25

3072B	BB#24: derived from LLVM BB %if.else.45
	    Predecessors according to CFG: BB#15 BB#16
3088B		STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
3104B		B <BB#37>
	    Successors according to CFG: BB#37

3120B	BB#25: derived from LLVM BB %if.end.46
	    Predecessors according to CFG: BB#23
3136B		B <BB#26>
	    Successors according to CFG: BB#26

3152B	BB#26: derived from LLVM BB %if.end.47
	    Predecessors according to CFG: BB#9 BB#25
3168B		%vreg138<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg138
3184B		%vreg137<def> = LDRWui %vreg138, 2; mem:LD4[%state48] GPR32common:%vreg137 GPR64common:%vreg138
3200B		%WZR<def> = SUBSWri %vreg137, 10, 0, %NZCV<imp-def>; GPR32common:%vreg137
3216B		Bcc 11, <BB#36>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#36 BB#27

3232B	BB#27: derived from LLVM BB %if.then.50
	    Predecessors according to CFG: BB#26
3248B		%vreg144<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg144
3264B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3280B		%X0<def> = COPY %vreg144; GPR64:%vreg144
3296B		BL <ga:@BZ2_decompress>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
3312B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3328B		%vreg143<def> = COPY %W0; GPR32:%vreg143
3344B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3360B		STACKMAP 5, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
3376B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3392B		STRWui %vreg143, <fi#4>, 0; mem:ST4[FixedStack4] GPR32:%vreg143
3408B		%vreg140<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32common:%vreg140
3424B		%WZR<def> = SUBSWri %vreg140, 4, 0, %NZCV<imp-def>; GPR32common:%vreg140
3440B		Bcc 1, <BB#33>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#33 BB#28

3456B	BB#28: derived from LLVM BB %if.then.53
	    Predecessors according to CFG: BB#27
3472B		%vreg154<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg154
3488B		%vreg153<def> = LDRWui %vreg154, 13; mem:LD4[%verbosity54] GPR32common:%vreg153 GPR64common:%vreg154
3504B		%WZR<def> = SUBSWri %vreg153, 3, 0, %NZCV<imp-def>; GPR32common:%vreg153
3520B		Bcc 11, <BB#30>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#30 BB#29

3536B	BB#29: derived from LLVM BB %if.then.56
	    Predecessors according to CFG: BB#28
3552B		%vreg166<def> = ADRP <ga:@stderr>[TF=1]; GPR64common:%vreg166
3568B		%vreg167<def> = ADDXri %vreg166, <ga:@stderr>[TF=34], 0; GPR64sp:%vreg167 GPR64common:%vreg166
3584B		%vreg168<def> = LDRXui %vreg167, 0; mem:LD8[@stderr] GPR64:%vreg168 GPR64sp:%vreg167
3600B		%vreg165<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg165
3616B		%vreg164<def> = LDRWui %vreg165, 795; mem:LD4[%storedCombinedCRC] GPR32:%vreg164 GPR64common:%vreg165
3632B		%vreg162<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg162
3648B		%vreg161<def> = LDRWui %vreg162, 797; mem:LD4[%calculatedCombinedCRC57] GPR32:%vreg161 GPR64common:%vreg162
3664B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3680B		%vreg158<def> = MOVaddr <ga:@bzlib__str_4______combi>[TF=1], <ga:@bzlib__str_4______combi>[TF=34]; GPR64:%vreg158
3696B		%X0<def> = COPY %vreg168; GPR64:%vreg168
3712B		%X1<def> = COPY %vreg158; GPR64:%vreg158
3728B		%W2<def> = COPY %vreg164; GPR32:%vreg164
3744B		%W3<def> = COPY %vreg161; GPR32:%vreg161
3760B		BL <ga:@fprintf>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %W2<imp-use,kill>, %W3<imp-use,kill>, %SP<imp-def>, %W0<imp-def>
3776B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3792B		%vreg159<def,dead> = COPY %W0; GPR32all:%vreg159
3808B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3824B		STACKMAP 6, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
3840B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#30

3856B	BB#30: derived from LLVM BB %if.end.59
	    Predecessors according to CFG: BB#28 BB#29
3872B		%vreg176<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg176
3888B		%vreg175<def> = LDRWui %vreg176, 797; mem:LD4[%calculatedCombinedCRC60] GPR32:%vreg175 GPR64common:%vreg176
3904B		%vreg173<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg173
3920B		%vreg172<def> = LDRWui %vreg173, 795; mem:LD4[%storedCombinedCRC61] GPR32:%vreg172 GPR64common:%vreg173
3936B		%WZR<def> = SUBSWrr %vreg175, %vreg172, %NZCV<imp-def>; GPR32:%vreg175,%vreg172
3952B		Bcc 0, <BB#32>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#32 BB#31

3968B	BB#31: derived from LLVM BB %if.then.63
	    Predecessors according to CFG: BB#30
3984B		%vreg179<def> = MOVi32imm 4294967292; GPR32:%vreg179
4000B		STRWui %vreg179, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg179
4016B		B <BB#37>
	    Successors according to CFG: BB#37

4032B	BB#32: derived from LLVM BB %if.end.64
	    Predecessors according to CFG: BB#30
4048B		%vreg178<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg178
4064B		STRWui %vreg178, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg178
4080B		B <BB#37>
	    Successors according to CFG: BB#37

4096B	BB#33: derived from LLVM BB %if.end.65
	    Predecessors according to CFG: BB#27
4112B		%vreg148<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg148
4128B		%vreg147<def> = LDRWui %vreg148, 2; mem:LD4[%state66] GPR32common:%vreg147 GPR64common:%vreg148
4144B		%WZR<def> = SUBSWri %vreg147, 2, 0, %NZCV<imp-def>; GPR32common:%vreg147
4160B		Bcc 0, <BB#35>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#35 BB#34

4176B	BB#34: derived from LLVM BB %if.then.68
	    Predecessors according to CFG: BB#33
4192B		%vreg150<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg150
4208B		STRWui %vreg150, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg150
4224B		B <BB#37>
	    Successors according to CFG: BB#37

4240B	BB#35: derived from LLVM BB %if.end.69
	    Predecessors according to CFG: BB#33
4256B		B <BB#36>
	    Successors according to CFG: BB#36

4272B	BB#36: derived from LLVM BB %if.end.70
	    Predecessors according to CFG: BB#26 BB#35
4288B		B <BB#7>
	    Successors according to CFG: BB#7

4304B	BB#37: derived from LLVM BB %return
	    Predecessors according to CFG: BB#24 BB#34 BB#32 BB#31 BB#22 BB#14 BB#8 BB#5 BB#3 BB#1
4320B		%vreg188<def> = ADRP <ga:@BZ2_bzDecompress>[TF=1]; GPR64common:%vreg188
4336B		%vreg189<def> = ADDXri %vreg188, <ga:@BZ2_bzDecompress>[TF=34], 0; GPR64sp:%vreg189 GPR64common:%vreg188
4352B		%vreg190<def> = COPY %vreg189; GPR64all:%vreg190 GPR64sp:%vreg189
4368B		%vreg191<def> = COPY %vreg8; GPR64all:%vreg191 GPR64:%vreg8
4384B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4400B		%X0<def> = COPY %vreg190; GPR64all:%vreg190
4416B		%X1<def> = COPY %vreg191; GPR64all:%vreg191
4432B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
4448B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4464B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4480B		STACKMAP 7, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
4496B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4512B		%vreg187<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0] GPR32:%vreg187
4528B		%W0<def> = COPY %vreg187; GPR32:%vreg187
4544B		RET_ReallyLR %W0<imp-use>

# End machine code for function BZ2_bzDecompress.

********** SIMPLE REGISTER COALESCING **********
********** Function: BZ2_bzDecompress
********** JOINING INTERVALS ***********
while.body:
if.end.17:
if.end.29:
if.end.34:
if.end.47:
if.end.11:
if.then.14:
if.end.20:
land.lhs.true:
if.then.23:
if.then.50:
3280B	%X0<def> = COPY %vreg144; GPR64:%vreg144
	Considering merging %vreg144 with %X0
	Can only merge into reserved registers.
3328B	%vreg143<def> = COPY %W0; GPR32:%vreg143
	Considering merging %vreg143 with %W0
	Can only merge into reserved registers.
if.end.65:
if.end.70:
if.then.15:
1088B	%X0<def> = COPY %vreg43; GPR64:%vreg43
	Considering merging %vreg43 with %X0
	Can only merge into reserved registers.
1136B	%vreg42<def> = COPY %W0; GPR32:%vreg42
	Considering merging %vreg42 with %W0
	Can only merge into reserved registers.
if.else:
1296B	%X0<def> = COPY %vreg39; GPR64:%vreg39
	Considering merging %vreg39 with %X0
	Can only merge into reserved registers.
1344B	%vreg38<def> = COPY %W0; GPR32:%vreg38
	Considering merging %vreg38 with %W0
	Can only merge into reserved registers.
if.then.26:
2128B	%X0<def> = COPY %vreg89; GPR64:%vreg89
	Considering merging %vreg89 with %X0
	Can only merge into reserved registers.
2144B	%X1<def> = COPY %vreg79; GPR64:%vreg79
	Considering merging %vreg79 with %X1
	Can only merge into reserved registers.
2160B	%W2<def> = COPY %vreg85; GPR32:%vreg85
	Considering merging %vreg85 with %W2
	Can only merge into reserved registers.
2176B	%W3<def> = COPY %vreg82; GPR32:%vreg82
	Considering merging %vreg82 with %W3
	Can only merge into reserved registers.
2224B	%vreg80<def,dead> = COPY %W0; GPR32all:%vreg80
	Considering merging %vreg80 with %W0
	Can only merge into reserved registers.
if.then.32:
2464B	%X0<def> = COPY %vreg99; GPR64:%vreg99
	Considering merging %vreg99 with %X0
	Can only merge into reserved registers.
2480B	%X1<def> = COPY %vreg95; GPR64:%vreg95
	Considering merging %vreg95 with %X1
	Can only merge into reserved registers.
2528B	%vreg96<def,dead> = COPY %W0; GPR32all:%vreg96
	Considering merging %vreg96 with %W0
	Can only merge into reserved registers.
if.end.39:
if.end.46:
if.end.69:
1152B	%vreg40<def> = COPY %vreg42; GPR32:%vreg40,%vreg42
	Considering merging to GPR32 with %vreg42 in %vreg40
		RHS = %vreg42 [1136r,1152r:0)  0@1136r
		LHS = %vreg40 [1152r,1216r:0)  0@1152r
		merge %vreg40:0@1152r into %vreg42:0@1136r --> @1136r
		erased:	1152r	%vreg40<def> = COPY %vreg42; GPR32:%vreg40,%vreg42
		updated: 1136B	%vreg40<def> = COPY %W0; GPR32:%vreg40
	Success: %vreg42 -> %vreg40
	Result = %vreg40 [1136r,1216r:0)  0@1136r
1360B	%vreg36<def> = COPY %vreg38; GPR32:%vreg36,%vreg38
	Considering merging to GPR32 with %vreg38 in %vreg36
		RHS = %vreg38 [1344r,1360r:0)  0@1344r
		LHS = %vreg36 [1360r,1424r:0)  0@1360r
		merge %vreg36:0@1360r into %vreg38:0@1344r --> @1344r
		erased:	1360r	%vreg36<def> = COPY %vreg38; GPR32:%vreg36,%vreg38
		updated: 1344B	%vreg36<def> = COPY %W0; GPR32:%vreg36
	Success: %vreg38 -> %vreg36
	Result = %vreg36 [1344r,1424r:0)  0@1344r
return:
4400B	%X0<def> = COPY %vreg190; GPR64all:%vreg190
	Considering merging %vreg190 with %X0
	Can only merge into reserved registers.
4416B	%X1<def> = COPY %vreg191; GPR64all:%vreg191
	Considering merging %vreg191 with %X1
	Can only merge into reserved registers.
4528B	%W0<def> = COPY %vreg187; GPR32:%vreg187
	Considering merging %vreg187 with %W0
	Can only merge into reserved registers.
if.end.59:
if.end:
if.end.3:
if.else.45:
if.then.53:
entry:
16B	%vreg8<def> = COPY %LR; GPR64:%vreg8
	Considering merging %vreg8 with %LR
	Can only merge into reserved registers.
32B	%vreg0<def> = COPY %X0; GPR64:%vreg0
	Considering merging %vreg0 with %X0
	Can only merge into reserved registers.
144B	%X0<def> = COPY %vreg6; GPR64all:%vreg6
	Considering merging %vreg6 with %X0
	Can only merge into reserved registers.
160B	%X1<def> = COPY %vreg7; GPR64all:%vreg7
	Considering merging %vreg7 with %X1
	Can only merge into reserved registers.
if.then:
if.then.2:
if.then.6:
if.end.7:
if.then.10:
if.then.19:
if.then.38:
if.then.56:
3696B	%X0<def> = COPY %vreg168; GPR64:%vreg168
	Considering merging %vreg168 with %X0
	Can only merge into reserved registers.
3712B	%X1<def> = COPY %vreg158; GPR64:%vreg158
	Considering merging %vreg158 with %X1
	Can only merge into reserved registers.
3728B	%W2<def> = COPY %vreg164; GPR32:%vreg164
	Considering merging %vreg164 with %W2
	Can only merge into reserved registers.
3744B	%W3<def> = COPY %vreg161; GPR32:%vreg161
	Considering merging %vreg161 with %W3
	Can only merge into reserved registers.
3792B	%vreg159<def,dead> = COPY %W0; GPR32all:%vreg159
	Considering merging %vreg159 with %W0
	Can only merge into reserved registers.
if.then.63:
if.end.64:
if.then.68:
4352B	%vreg190<def> = COPY %vreg189; GPR64all:%vreg190 GPR64sp:%vreg189
	Considering merging to GPR64sp with %vreg189 in %vreg190
		RHS = %vreg189 [4336r,4352r:0)  0@4336r
		LHS = %vreg190 [4352r,4400r:0)  0@4352r
		merge %vreg190:0@4352r into %vreg189:0@4336r --> @4336r
		erased:	4352r	%vreg190<def> = COPY %vreg189; GPR64all:%vreg190 GPR64sp:%vreg189
		updated: 4336B	%vreg190<def> = ADDXri %vreg188, <ga:@BZ2_bzDecompress>[TF=34], 0; GPR64sp:%vreg190 GPR64common:%vreg188
	Success: %vreg189 -> %vreg190
	Result = %vreg190 [4336r,4400r:0)  0@4336r
4368B	%vreg191<def> = COPY %vreg8; GPR64all:%vreg191 GPR64:%vreg8
	Considering merging to GPR64 with %vreg8 in %vreg191
		RHS = %vreg8 [16r,4368r:0)  0@16r
		LHS = %vreg191 [4368r,4416r:0)  0@4368r
		merge %vreg191:0@4368r into %vreg8:0@16r --> @16r
		erased:	4368r	%vreg191<def> = COPY %vreg8; GPR64all:%vreg191 GPR64:%vreg8
		updated: 16B	%vreg191<def> = COPY %LR; GPR64:%vreg191
		updated: 112B	%vreg7<def> = COPY %vreg191; GPR64all:%vreg7 GPR64:%vreg191
	Success: %vreg8 -> %vreg191
	Result = %vreg191 [16r,4416r:0)  0@16r
416B	%vreg13<def> = COPY %vreg15; GPR64:%vreg13,%vreg15
	Considering merging to GPR64 with %vreg15 in %vreg13
		RHS = %vreg15 [400r,416r:0)  0@400r
		LHS = %vreg13 [416r,432r:0)  0@416r
		merge %vreg13:0@416r into %vreg15:0@400r --> @400r
		erased:	416r	%vreg13<def> = COPY %vreg15; GPR64:%vreg13,%vreg15
		updated: 400B	%vreg13<def> = LDRXui %vreg16, 6; mem:LD8[%state] GPR64:%vreg13 GPR64common:%vreg16
	Success: %vreg15 -> %vreg13
	Result = %vreg13 [400r,432r:0)  0@400r
48B	%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
	Considering merging to GPR64 with %vreg0 in %vreg1
		RHS = %vreg0 [32r,48r:0)  0@32r
		LHS = %vreg1 [48r,256r:0)  0@48r
		merge %vreg1:0@48r into %vreg0:0@32r --> @32r
		erased:	48r	%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
		updated: 32B	%vreg1<def> = COPY %X0; GPR64:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [32r,256r:0)  0@32r
96B	%vreg6<def> = COPY %vreg5; GPR64all:%vreg6 GPR64sp:%vreg5
	Considering merging to GPR64sp with %vreg5 in %vreg6
		RHS = %vreg5 [80r,96r:0)  0@80r
		LHS = %vreg6 [96r,144r:0)  0@96r
		merge %vreg6:0@96r into %vreg5:0@80r --> @80r
		erased:	96r	%vreg6<def> = COPY %vreg5; GPR64all:%vreg6 GPR64sp:%vreg5
		updated: 80B	%vreg6<def> = ADDXri %vreg4, <ga:@BZ2_bzDecompress>[TF=34], 0; GPR64sp:%vreg6 GPR64common:%vreg4
	Success: %vreg5 -> %vreg6
	Result = %vreg6 [80r,144r:0)  0@80r
112B	%vreg7<def> = COPY %vreg191; GPR64all:%vreg7 GPR64:%vreg191
	Considering merging to GPR64 with %vreg191 in %vreg7
		RHS = %vreg191 [16r,4416r:0)  0@16r
		LHS = %vreg7 [112r,160r:0)  0@112r
		merge %vreg7:0@112r into %vreg191:0@16r --> @16r
		erased:	112r	%vreg7<def> = COPY %vreg191; GPR64all:%vreg7 GPR64:%vreg191
		updated: 16B	%vreg7<def> = COPY %LR; GPR64:%vreg7
		updated: 4416B	%X1<def> = COPY %vreg7; GPR64:%vreg7
	Success: %vreg191 -> %vreg7
	Result = %vreg7 [16r,4416r:0)  0@16r
4400B	%X0<def> = COPY %vreg190; GPR64sp:%vreg190
	Considering merging %vreg190 with %X0
	Can only merge into reserved registers.
4416B	%X1<def> = COPY %vreg7; GPR64:%vreg7
	Considering merging %vreg7 with %X1
	Can only merge into reserved registers.
144B	%X0<def> = COPY %vreg6; GPR64sp:%vreg6
	Considering merging %vreg6 with %X0
	Can only merge into reserved registers.
160B	%X1<def> = COPY %vreg7; GPR64:%vreg7
	Considering merging %vreg7 with %X1
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
W30 [0B,16r:0)[176r,176d:16)[224e,224d:8)[1104r,1104d:14)[1184e,1184d:7)[1312r,1312d:15)[1392e,1392d:6)[2192r,2192d:13)[2256e,2256d:5)[2496r,2496d:12)[2560e,2560d:4)[3296r,3296d:11)[3360e,3360d:3)[3760r,3760d:10)[3824e,3824d:2)[4432r,4432d:9)[4480e,4480d:1)  0@0B-phi 1@4480e 2@3824e 3@3360e 4@2560e 5@2256e 6@1392e 7@1184e 8@224e 9@4432r 10@3760r 11@3296r 12@2496r 13@2192r 14@1104r 15@1312r 16@176r
W0 [0B,32r:0)[144r,176r:15)[1088r,1104r:13)[1104r,1136r:6)[1296r,1312r:14)[1312r,1344r:7)[2128r,2192r:12)[2192r,2224r:5)[2464r,2496r:11)[2496r,2528r:4)[3280r,3296r:10)[3296r,3328r:3)[3696r,3760r:9)[3760r,3792r:2)[4400r,4432r:8)[4528r,4544r:1)  0@0B-phi 1@4528r 2@3760r 3@3296r 4@2496r 5@2192r 6@1104r 7@1312r 8@4400r 9@3696r 10@3280r 11@2464r 12@2128r 13@1088r 14@1296r 15@144r
%vreg1 [32r,256r:0)  0@32r
%vreg3 [272r,288r:0)  0@272r
%vreg4 [64r,80r:0)  0@64r
%vreg6 [80r,144r:0)  0@80r
%vreg7 [16r,4416r:0)  0@16r
%vreg10 [448r,464r:0)  0@448r
%vreg13 [400r,432r:0)  0@400r
%vreg16 [384r,400r:0)  0@384r
%vreg19 [592r,608r:0)  0@592r
%vreg21 [576r,608r:0)  0@576r
%vreg22 [560r,576r:0)  0@560r
%vreg25 [768r,784r:0)  0@768r
%vreg26 [752r,768r:0)  0@752r
%vreg29 [912r,928r:0)  0@912r
%vreg30 [896r,912r:0)  0@896r
%vreg32 [1008r,1024r:0)  0@1008r
%vreg34 [992r,1008r:0)  0@992r
%vreg35 [976r,992r:0)  0@976r
%vreg36 [1344r,1424r:0)  0@1344r
%vreg39 [1264r,1296r:0)  0@1264r
%vreg40 [1136r,1216r:0)  0@1136r
%vreg43 [1056r,1088r:0)  0@1056r
%vreg45 [1472r,1488r:0)  0@1472r
%vreg46 [1456r,1472r:0)  0@1456r
%vreg50 [1680r,1696r:0)  0@1680r
%vreg52 [1632r,1648r:0)  0@1632r
%vreg53 [1648r,1664r:0)  0@1648r
%vreg54 [1664r,1680r:0)  0@1664r
%vreg55 [1616r,1648r:0)  0@1616r
%vreg57 [1600r,1696r:0)  0@1600r
%vreg58 [1584r,1600r:0)  0@1584r
%vreg61 [1760r,1776r:0)  0@1760r
%vreg62 [1744r,1760r:0)  0@1744r
%vreg65 [1920r,1936r:0)  0@1920r
%vreg66 [1904r,1920r:0)  0@1904r
%vreg69 [1872r,1888r:0)  0@1872r
%vreg71 [1808r,1856r:0)  0@1808r
%vreg72 [1856r,1888r:0)  0@1856r
%vreg74 [1840r,1856r:0)  0@1840r
%vreg75 [1824r,1840r:0)  0@1824r
%vreg79 [2112r,2144r:0)  0@2112r
%vreg80 [2224r,2224d:0)  0@2224r
%vreg82 [2080r,2176r:0)  0@2080r
%vreg83 [2064r,2080r:0)  0@2064r
%vreg85 [2048r,2160r:0)  0@2048r
%vreg86 [2032r,2048r:0)  0@2032r
%vreg87 [1984r,2000r:0)  0@1984r
%vreg88 [2000r,2016r:0)  0@2000r
%vreg89 [2016r,2128r:0)  0@2016r
%vreg92 [2320r,2336r:0)  0@2320r
%vreg93 [2304r,2320r:0)  0@2304r
%vreg95 [2448r,2480r:0)  0@2448r
%vreg96 [2528r,2528d:0)  0@2528r
%vreg97 [2384r,2400r:0)  0@2384r
%vreg98 [2400r,2416r:0)  0@2400r
%vreg99 [2416r,2464r:0)  0@2416r
%vreg103 [2656r,2672r:0)  0@2656r
%vreg104 [2640r,2656r:0)  0@2640r
%vreg106 [2624r,2672r:0)  0@2624r
%vreg107 [2608r,2624r:0)  0@2608r
%vreg108 [2784r,3040r:0)  0@2784r
%vreg110 [3024r,3040r:0)  0@3024r
%vreg115 [2992r,3008r:0)  0@2992r
%vreg116 [2976r,2992r:0)  0@2976r
%vreg117 [2960r,3008r:0)  0@2960r
%vreg119 [2944r,2992r:0)  0@2944r
%vreg120 [2928r,2944r:0)  0@2928r
%vreg123 [2896r,2912r:0)  0@2896r
%vreg126 [2880r,2912r:0)  0@2880r
%vreg128 [2864r,2880r:0)  0@2864r
%vreg130 [2848r,2864r:0)  0@2848r
%vreg131 [2832r,2848r:0)  0@2832r
%vreg133 [2816r,2880r:0)  0@2816r
%vreg134 [2800r,2816r:0)  0@2800r
%vreg137 [3184r,3200r:0)  0@3184r
%vreg138 [3168r,3184r:0)  0@3168r
%vreg140 [3408r,3424r:0)  0@3408r
%vreg143 [3328r,3392r:0)  0@3328r
%vreg144 [3248r,3280r:0)  0@3248r
%vreg147 [4128r,4144r:0)  0@4128r
%vreg148 [4112r,4128r:0)  0@4112r
%vreg150 [4192r,4208r:0)  0@4192r
%vreg153 [3488r,3504r:0)  0@3488r
%vreg154 [3472r,3488r:0)  0@3472r
%vreg158 [3680r,3712r:0)  0@3680r
%vreg159 [3792r,3792d:0)  0@3792r
%vreg161 [3648r,3744r:0)  0@3648r
%vreg162 [3632r,3648r:0)  0@3632r
%vreg164 [3616r,3728r:0)  0@3616r
%vreg165 [3600r,3616r:0)  0@3600r
%vreg166 [3552r,3568r:0)  0@3552r
%vreg167 [3568r,3584r:0)  0@3568r
%vreg168 [3584r,3696r:0)  0@3584r
%vreg172 [3920r,3936r:0)  0@3920r
%vreg173 [3904r,3920r:0)  0@3904r
%vreg175 [3888r,3936r:0)  0@3888r
%vreg176 [3872r,3888r:0)  0@3872r
%vreg178 [4048r,4064r:0)  0@4048r
%vreg179 [3984r,4000r:0)  0@3984r
%vreg180 [2720r,2736r:0)  0@2720r
%vreg181 [1520r,1536r:0)  0@1520r
%vreg182 [832r,848r:0)  0@832r
%vreg183 [656r,672r:0)  0@656r
%vreg184 [496r,512r:0)  0@496r
%vreg185 [320r,336r:0)  0@320r
%vreg187 [4512r,4528r:0)  0@4512r
%vreg188 [4320r,4336r:0)  0@4320r
%vreg190 [4336r,4400r:0)  0@4336r
RegMasks: 176r 1104r 1312r 2192r 2496r 3296r 3760r 4432r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzDecompress: Post SSA
Frame Objects:
  fi#0: size=4, align=4, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=1, align=1, at location [SP]
  fi#3: size=8, align=8, at location [SP]
  fi#4: size=4, align=4, at location [SP]
Function Live Ins: %X0 in %vreg0, %LR in %vreg8

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %LR
16B		%vreg7<def> = COPY %LR; GPR64:%vreg7
32B		%vreg1<def> = COPY %X0; GPR64:%vreg1
64B		%vreg4<def> = ADRP <ga:@BZ2_bzDecompress>[TF=1]; GPR64common:%vreg4
80B		%vreg6<def> = ADDXri %vreg4, <ga:@BZ2_bzDecompress>[TF=34], 0; GPR64sp:%vreg6 GPR64common:%vreg4
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		%X0<def> = COPY %vreg6; GPR64sp:%vreg6
160B		%X1<def> = COPY %vreg7; GPR64:%vreg7
176B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
224B		STACKMAP 0, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, %vreg1, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3] LD8[FixedStack1] GPR64:%vreg1
240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
256B		STRXui %vreg1, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg1
272B		%vreg3<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg3
288B		CBNZX %vreg3, <BB#2>; GPR64:%vreg3
	    Successors according to CFG: BB#2 BB#1

304B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
320B		%vreg185<def> = MOVi32imm 4294967294; GPR32:%vreg185
336B		STRWui %vreg185, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg185
352B		B <BB#37>
	    Successors according to CFG: BB#37

368B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0
384B		%vreg16<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg16
400B		%vreg13<def> = LDRXui %vreg16, 6; mem:LD8[%state] GPR64:%vreg13 GPR64common:%vreg16
432B		STRXui %vreg13, <fi#3>, 0; mem:ST8[FixedStack3] GPR64:%vreg13
448B		%vreg10<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg10
464B		CBNZX %vreg10, <BB#4>; GPR64:%vreg10
	    Successors according to CFG: BB#4 BB#3

480B	BB#3: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#2
496B		%vreg184<def> = MOVi32imm 4294967294; GPR32:%vreg184
512B		STRWui %vreg184, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg184
528B		B <BB#37>
	    Successors according to CFG: BB#37

544B	BB#4: derived from LLVM BB %if.end.3
	    Predecessors according to CFG: BB#2
560B		%vreg22<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg22
576B		%vreg21<def> = LDRXui %vreg22, 0; mem:LD8[%strm4] GPR64:%vreg21 GPR64common:%vreg22
592B		%vreg19<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg19
608B		%XZR<def> = SUBSXrr %vreg21, %vreg19, %NZCV<imp-def>; GPR64:%vreg21,%vreg19
624B		Bcc 0, <BB#6>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#6 BB#5

640B	BB#5: derived from LLVM BB %if.then.6
	    Predecessors according to CFG: BB#4
656B		%vreg183<def> = MOVi32imm 4294967294; GPR32:%vreg183
672B		STRWui %vreg183, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg183
688B		B <BB#37>
	    Successors according to CFG: BB#37

704B	BB#6: derived from LLVM BB %if.end.7
	    Predecessors according to CFG: BB#4
720B		B <BB#7>
	    Successors according to CFG: BB#7

736B	BB#7: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#6 BB#36
752B		%vreg26<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg26
768B		%vreg25<def> = LDRWui %vreg26, 2; mem:LD4[%state8] GPR32common:%vreg25 GPR64common:%vreg26
784B		%WZR<def> = SUBSWri %vreg25, 1, 0, %NZCV<imp-def>; GPR32common:%vreg25
800B		Bcc 1, <BB#9>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#9 BB#8

816B	BB#8: derived from LLVM BB %if.then.10
	    Predecessors according to CFG: BB#7
832B		%vreg182<def> = MOVi32imm 4294967295; GPR32:%vreg182
848B		STRWui %vreg182, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg182
864B		B <BB#37>
	    Successors according to CFG: BB#37

880B	BB#9: derived from LLVM BB %if.end.11
	    Predecessors according to CFG: BB#7
896B		%vreg30<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg30
912B		%vreg29<def> = LDRWui %vreg30, 2; mem:LD4[%state12] GPR32common:%vreg29 GPR64common:%vreg30
928B		%WZR<def> = SUBSWri %vreg29, 2, 0, %NZCV<imp-def>; GPR32common:%vreg29
944B		Bcc 1, <BB#26>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#26 BB#10

960B	BB#10: derived from LLVM BB %if.then.14
	    Predecessors according to CFG: BB#9
976B		%vreg35<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg35
992B		%vreg34<def> = LDRBBui %vreg35, 44; mem:LD1[%smallDecompress] GPR32:%vreg34 GPR64common:%vreg35
1008B		%vreg32<def> = UBFMWri %vreg34, 0, 7; GPR32:%vreg32,%vreg34
1024B		CBZW %vreg32, <BB#12>; GPR32:%vreg32
	    Successors according to CFG: BB#12 BB#11

1040B	BB#11: derived from LLVM BB %if.then.15
	    Predecessors according to CFG: BB#10
1056B		%vreg43<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg43
1072B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1088B		%X0<def> = COPY %vreg43; GPR64:%vreg43
1104B		BL <ga:@unRLE_obuf_to_output_SMALL>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>
1120B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1136B		%vreg40<def> = COPY %W0; GPR32:%vreg40
1168B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1184B		STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
1200B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1216B		STRBBui %vreg40, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg40
1232B		B <BB#13>
	    Successors according to CFG: BB#13

1248B	BB#12: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#10
1264B		%vreg39<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg39
1280B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1296B		%X0<def> = COPY %vreg39; GPR64:%vreg39
1312B		BL <ga:@unRLE_obuf_to_output_FAST>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>
1328B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1344B		%vreg36<def> = COPY %W0; GPR32:%vreg36
1376B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1392B		STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
1408B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1424B		STRBBui %vreg36, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg36
	    Successors according to CFG: BB#13

1440B	BB#13: derived from LLVM BB %if.end.17
	    Predecessors according to CFG: BB#12 BB#11
1456B		%vreg46<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg46
1472B		%vreg45<def> = UBFMWri %vreg46, 0, 7; GPR32:%vreg45,%vreg46
1488B		CBZW %vreg45, <BB#15>; GPR32:%vreg45
	    Successors according to CFG: BB#15 BB#14

1504B	BB#14: derived from LLVM BB %if.then.19
	    Predecessors according to CFG: BB#13
1520B		%vreg181<def> = MOVi32imm 4294967292; GPR32:%vreg181
1536B		STRWui %vreg181, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg181
1552B		B <BB#37>
	    Successors according to CFG: BB#37

1568B	BB#15: derived from LLVM BB %if.end.20
	    Predecessors according to CFG: BB#13
1584B		%vreg58<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg58
1600B		%vreg57<def> = LDRWui %vreg58, 273; mem:LD4[%nblock_used] GPR32:%vreg57 GPR64common:%vreg58
1616B		%vreg55<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg55
1632B		%vreg52<def> = MOVi64imm 64080; GPR64:%vreg52
1648B		%vreg53<def> = ADDXrr %vreg55, %vreg52; GPR64common:%vreg53 GPR64:%vreg55,%vreg52
1664B		%vreg54<def> = LDRWui %vreg53, 0; mem:LD4[%save_nblock] GPR32common:%vreg54 GPR64common:%vreg53
1680B		%vreg50<def> = ADDWri %vreg54, 1, 0; GPR32common:%vreg50,%vreg54
1696B		%WZR<def> = SUBSWrr %vreg57, %vreg50, %NZCV<imp-def>; GPR32:%vreg57 GPR32common:%vreg50
1712B		Bcc 1, <BB#24>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#24 BB#16

1728B	BB#16: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#15
1744B		%vreg62<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg62
1760B		%vreg61<def> = LDRWui %vreg62, 4; mem:LD4[%state_out_len] GPR32:%vreg61 GPR64common:%vreg62
1776B		CBNZW %vreg61, <BB#24>; GPR32:%vreg61
	    Successors according to CFG: BB#24 BB#17

1792B	BB#17: derived from LLVM BB %if.then.23
	    Predecessors according to CFG: BB#16
1808B		%vreg71<def> = MOVi32imm 4294967295; GPR32:%vreg71
1824B		%vreg75<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg75
1840B		%vreg74<def> = LDRWui %vreg75, 796; mem:LD4[%calculatedBlockCRC] GPR32:%vreg74 GPR64common:%vreg75
1856B		%vreg72<def> = EORWrr %vreg74, %vreg71; GPR32:%vreg72,%vreg74,%vreg71
1872B		%vreg69<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg69
1888B		STRWui %vreg72, %vreg69, 796; mem:ST4[%calculatedBlockCRC24] GPR32:%vreg72 GPR64common:%vreg69
1904B		%vreg66<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg66
1920B		%vreg65<def> = LDRWui %vreg66, 13; mem:LD4[%verbosity] GPR32common:%vreg65 GPR64common:%vreg66
1936B		%WZR<def> = SUBSWri %vreg65, 3, 0, %NZCV<imp-def>; GPR32common:%vreg65
1952B		Bcc 11, <BB#19>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#19 BB#18

1968B	BB#18: derived from LLVM BB %if.then.26
	    Predecessors according to CFG: BB#17
1984B		%vreg87<def> = ADRP <ga:@stderr>[TF=1]; GPR64common:%vreg87
2000B		%vreg88<def> = ADDXri %vreg87, <ga:@stderr>[TF=34], 0; GPR64sp:%vreg88 GPR64common:%vreg87
2016B		%vreg89<def> = LDRXui %vreg88, 0; mem:LD8[@stderr] GPR64:%vreg89 GPR64sp:%vreg88
2032B		%vreg86<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg86
2048B		%vreg85<def> = LDRWui %vreg86, 794; mem:LD4[%storedBlockCRC] GPR32:%vreg85 GPR64common:%vreg86
2064B		%vreg83<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg83
2080B		%vreg82<def> = LDRWui %vreg83, 796; mem:LD4[%calculatedBlockCRC27] GPR32:%vreg82 GPR64common:%vreg83
2096B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2112B		%vreg79<def> = MOVaddr <ga:@bzlib__str_2___0x_08x__>[TF=1], <ga:@bzlib__str_2___0x_08x__>[TF=34]; GPR64:%vreg79
2128B		%X0<def> = COPY %vreg89; GPR64:%vreg89
2144B		%X1<def> = COPY %vreg79; GPR64:%vreg79
2160B		%W2<def> = COPY %vreg85; GPR32:%vreg85
2176B		%W3<def> = COPY %vreg82; GPR32:%vreg82
2192B		BL <ga:@fprintf>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %W2<imp-use,kill>, %W3<imp-use,kill>, %SP<imp-def>, %W0<imp-def>
2208B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2224B		%vreg80<def,dead> = COPY %W0; GPR32all:%vreg80
2240B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2256B		STACKMAP 3, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
2272B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#19

2288B	BB#19: derived from LLVM BB %if.end.29
	    Predecessors according to CFG: BB#17 BB#18
2304B		%vreg93<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg93
2320B		%vreg92<def> = LDRWui %vreg93, 13; mem:LD4[%verbosity30] GPR32common:%vreg92 GPR64common:%vreg93
2336B		%WZR<def> = SUBSWri %vreg92, 2, 0, %NZCV<imp-def>; GPR32common:%vreg92
2352B		Bcc 11, <BB#21>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#21 BB#20

2368B	BB#20: derived from LLVM BB %if.then.32
	    Predecessors according to CFG: BB#19
2384B		%vreg97<def> = ADRP <ga:@stderr>[TF=1]; GPR64common:%vreg97
2400B		%vreg98<def> = ADDXri %vreg97, <ga:@stderr>[TF=34], 0; GPR64sp:%vreg98 GPR64common:%vreg97
2416B		%vreg99<def> = LDRXui %vreg98, 0; mem:LD8[@stderr] GPR64:%vreg99 GPR64sp:%vreg98
2432B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2448B		%vreg95<def> = MOVaddr <ga:@bzlib__str_3___>[TF=1], <ga:@bzlib__str_3___>[TF=34]; GPR64:%vreg95
2464B		%X0<def> = COPY %vreg99; GPR64:%vreg99
2480B		%X1<def> = COPY %vreg95; GPR64:%vreg95
2496B		BL <ga:@fprintf>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %SP<imp-def>, %W0<imp-def>
2512B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2528B		%vreg96<def,dead> = COPY %W0; GPR32all:%vreg96
2544B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2560B		STACKMAP 4, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
2576B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#21

2592B	BB#21: derived from LLVM BB %if.end.34
	    Predecessors according to CFG: BB#19 BB#20
2608B		%vreg107<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg107
2624B		%vreg106<def> = LDRWui %vreg107, 796; mem:LD4[%calculatedBlockCRC35] GPR32:%vreg106 GPR64common:%vreg107
2640B		%vreg104<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg104
2656B		%vreg103<def> = LDRWui %vreg104, 794; mem:LD4[%storedBlockCRC36] GPR32:%vreg103 GPR64common:%vreg104
2672B		%WZR<def> = SUBSWrr %vreg106, %vreg103, %NZCV<imp-def>; GPR32:%vreg106,%vreg103
2688B		Bcc 0, <BB#23>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#23 BB#22

2704B	BB#22: derived from LLVM BB %if.then.38
	    Predecessors according to CFG: BB#21
2720B		%vreg180<def> = MOVi32imm 4294967292; GPR32:%vreg180
2736B		STRWui %vreg180, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg180
2752B		B <BB#37>
	    Successors according to CFG: BB#37

2768B	BB#23: derived from LLVM BB %if.end.39
	    Predecessors according to CFG: BB#21
2784B		%vreg108<def> = MOVi32imm 14; GPR32:%vreg108
2800B		%vreg134<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg134
2816B		%vreg133<def> = LDRWui %vreg134, 797; mem:LD4[%calculatedCombinedCRC] GPR32:%vreg133 GPR64common:%vreg134
2832B		%vreg131<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg131
2848B		%vreg130<def> = LDRWui %vreg131, 797; mem:LD4[%calculatedCombinedCRC40] GPR32:%vreg130 GPR64common:%vreg131
2864B		%vreg128<def> = UBFMWri %vreg130, 31, 31; GPR32:%vreg128,%vreg130
2880B		%vreg126<def> = ORRWrs %vreg128, %vreg133, 1; GPR32:%vreg126,%vreg128,%vreg133
2896B		%vreg123<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg123
2912B		STRWui %vreg126, %vreg123, 797; mem:ST4[%calculatedCombinedCRC41] GPR32:%vreg126 GPR64common:%vreg123
2928B		%vreg120<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg120
2944B		%vreg119<def> = LDRWui %vreg120, 796; mem:LD4[%calculatedBlockCRC42] GPR32:%vreg119 GPR64common:%vreg120
2960B		%vreg117<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg117
2976B		%vreg116<def> = LDRWui %vreg117, 797; mem:LD4[%calculatedCombinedCRC43] GPR32:%vreg116 GPR64common:%vreg117
2992B		%vreg115<def> = EORWrr %vreg116, %vreg119; GPR32:%vreg115,%vreg116,%vreg119
3008B		STRWui %vreg115, %vreg117, 797; mem:ST4[%calculatedCombinedCRC43] GPR32:%vreg115 GPR64common:%vreg117
3024B		%vreg110<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg110
3040B		STRWui %vreg108, %vreg110, 2; mem:ST4[%state44] GPR32:%vreg108 GPR64common:%vreg110
3056B		B <BB#25>
	    Successors according to CFG: BB#25

3072B	BB#24: derived from LLVM BB %if.else.45
	    Predecessors according to CFG: BB#15 BB#16
3088B		STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
3104B		B <BB#37>
	    Successors according to CFG: BB#37

3120B	BB#25: derived from LLVM BB %if.end.46
	    Predecessors according to CFG: BB#23
3136B		B <BB#26>
	    Successors according to CFG: BB#26

3152B	BB#26: derived from LLVM BB %if.end.47
	    Predecessors according to CFG: BB#9 BB#25
3168B		%vreg138<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg138
3184B		%vreg137<def> = LDRWui %vreg138, 2; mem:LD4[%state48] GPR32common:%vreg137 GPR64common:%vreg138
3200B		%WZR<def> = SUBSWri %vreg137, 10, 0, %NZCV<imp-def>; GPR32common:%vreg137
3216B		Bcc 11, <BB#36>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#36 BB#27

3232B	BB#27: derived from LLVM BB %if.then.50
	    Predecessors according to CFG: BB#26
3248B		%vreg144<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg144
3264B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3280B		%X0<def> = COPY %vreg144; GPR64:%vreg144
3296B		BL <ga:@BZ2_decompress>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
3312B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3328B		%vreg143<def> = COPY %W0; GPR32:%vreg143
3344B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3360B		STACKMAP 5, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
3376B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3392B		STRWui %vreg143, <fi#4>, 0; mem:ST4[FixedStack4] GPR32:%vreg143
3408B		%vreg140<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32common:%vreg140
3424B		%WZR<def> = SUBSWri %vreg140, 4, 0, %NZCV<imp-def>; GPR32common:%vreg140
3440B		Bcc 1, <BB#33>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#33 BB#28

3456B	BB#28: derived from LLVM BB %if.then.53
	    Predecessors according to CFG: BB#27
3472B		%vreg154<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg154
3488B		%vreg153<def> = LDRWui %vreg154, 13; mem:LD4[%verbosity54] GPR32common:%vreg153 GPR64common:%vreg154
3504B		%WZR<def> = SUBSWri %vreg153, 3, 0, %NZCV<imp-def>; GPR32common:%vreg153
3520B		Bcc 11, <BB#30>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#30 BB#29

3536B	BB#29: derived from LLVM BB %if.then.56
	    Predecessors according to CFG: BB#28
3552B		%vreg166<def> = ADRP <ga:@stderr>[TF=1]; GPR64common:%vreg166
3568B		%vreg167<def> = ADDXri %vreg166, <ga:@stderr>[TF=34], 0; GPR64sp:%vreg167 GPR64common:%vreg166
3584B		%vreg168<def> = LDRXui %vreg167, 0; mem:LD8[@stderr] GPR64:%vreg168 GPR64sp:%vreg167
3600B		%vreg165<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg165
3616B		%vreg164<def> = LDRWui %vreg165, 795; mem:LD4[%storedCombinedCRC] GPR32:%vreg164 GPR64common:%vreg165
3632B		%vreg162<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg162
3648B		%vreg161<def> = LDRWui %vreg162, 797; mem:LD4[%calculatedCombinedCRC57] GPR32:%vreg161 GPR64common:%vreg162
3664B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3680B		%vreg158<def> = MOVaddr <ga:@bzlib__str_4______combi>[TF=1], <ga:@bzlib__str_4______combi>[TF=34]; GPR64:%vreg158
3696B		%X0<def> = COPY %vreg168; GPR64:%vreg168
3712B		%X1<def> = COPY %vreg158; GPR64:%vreg158
3728B		%W2<def> = COPY %vreg164; GPR32:%vreg164
3744B		%W3<def> = COPY %vreg161; GPR32:%vreg161
3760B		BL <ga:@fprintf>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %W2<imp-use,kill>, %W3<imp-use,kill>, %SP<imp-def>, %W0<imp-def>
3776B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3792B		%vreg159<def,dead> = COPY %W0; GPR32all:%vreg159
3808B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3824B		STACKMAP 6, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
3840B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#30

3856B	BB#30: derived from LLVM BB %if.end.59
	    Predecessors according to CFG: BB#28 BB#29
3872B		%vreg176<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg176
3888B		%vreg175<def> = LDRWui %vreg176, 797; mem:LD4[%calculatedCombinedCRC60] GPR32:%vreg175 GPR64common:%vreg176
3904B		%vreg173<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg173
3920B		%vreg172<def> = LDRWui %vreg173, 795; mem:LD4[%storedCombinedCRC61] GPR32:%vreg172 GPR64common:%vreg173
3936B		%WZR<def> = SUBSWrr %vreg175, %vreg172, %NZCV<imp-def>; GPR32:%vreg175,%vreg172
3952B		Bcc 0, <BB#32>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#32 BB#31

3968B	BB#31: derived from LLVM BB %if.then.63
	    Predecessors according to CFG: BB#30
3984B		%vreg179<def> = MOVi32imm 4294967292; GPR32:%vreg179
4000B		STRWui %vreg179, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg179
4016B		B <BB#37>
	    Successors according to CFG: BB#37

4032B	BB#32: derived from LLVM BB %if.end.64
	    Predecessors according to CFG: BB#30
4048B		%vreg178<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg178
4064B		STRWui %vreg178, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg178
4080B		B <BB#37>
	    Successors according to CFG: BB#37

4096B	BB#33: derived from LLVM BB %if.end.65
	    Predecessors according to CFG: BB#27
4112B		%vreg148<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg148
4128B		%vreg147<def> = LDRWui %vreg148, 2; mem:LD4[%state66] GPR32common:%vreg147 GPR64common:%vreg148
4144B		%WZR<def> = SUBSWri %vreg147, 2, 0, %NZCV<imp-def>; GPR32common:%vreg147
4160B		Bcc 0, <BB#35>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#35 BB#34

4176B	BB#34: derived from LLVM BB %if.then.68
	    Predecessors according to CFG: BB#33
4192B		%vreg150<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg150
4208B		STRWui %vreg150, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg150
4224B		B <BB#37>
	    Successors according to CFG: BB#37

4240B	BB#35: derived from LLVM BB %if.end.69
	    Predecessors according to CFG: BB#33
4256B		B <BB#36>
	    Successors according to CFG: BB#36

4272B	BB#36: derived from LLVM BB %if.end.70
	    Predecessors according to CFG: BB#26 BB#35
4288B		B <BB#7>
	    Successors according to CFG: BB#7

4304B	BB#37: derived from LLVM BB %return
	    Predecessors according to CFG: BB#24 BB#34 BB#32 BB#31 BB#22 BB#14 BB#8 BB#5 BB#3 BB#1
4320B		%vreg188<def> = ADRP <ga:@BZ2_bzDecompress>[TF=1]; GPR64common:%vreg188
4336B		%vreg190<def> = ADDXri %vreg188, <ga:@BZ2_bzDecompress>[TF=34], 0; GPR64sp:%vreg190 GPR64common:%vreg188
4384B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4400B		%X0<def> = COPY %vreg190; GPR64sp:%vreg190
4416B		%X1<def> = COPY %vreg7; GPR64:%vreg7
4432B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
4448B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4464B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4480B		STACKMAP 7, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
4496B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4512B		%vreg187<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0] GPR32:%vreg187
4528B		%W0<def> = COPY %vreg187; GPR32:%vreg187
4544B		RET_ReallyLR %W0<imp-use>

# End machine code for function BZ2_bzDecompress.

handleMove 1600B -> 1672B: %vreg57<def> = LDRWui %vreg58, 273; mem:LD4[%nblock_used] GPR32:%vreg57 GPR64common:%vreg58
     %vreg57:	[1600r,1696r:0)  0@1600r
        -->	[1672r,1696r:0)  0@1672r
     %vreg58:	[1584r,1600r:0)  0@1584r
        -->	[1584r,1672r:0)  0@1584r
handleMove 1584B -> 1624B: %vreg58<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg58
     %vreg58:	[1584r,1672r:0)  0@1584r
        -->	[1624r,1672r:0)  0@1624r
handleMove 1856B -> 1880B: %vreg72<def> = EORWrr %vreg74, %vreg71; GPR32:%vreg72,%vreg74,%vreg71
     %vreg72:	[1856r,1888r:0)  0@1856r
        -->	[1880r,1888r:0)  0@1880r
     %vreg74:	[1840r,1856r:0)  0@1840r
        -->	[1840r,1880r:0)  0@1840r
     %vreg71:	[1808r,1856r:0)  0@1808r
        -->	[1808r,1880r:0)  0@1808r
handleMove 1808B -> 1876B: %vreg71<def> = MOVi32imm 4294967295; GPR32:%vreg71
     %vreg71:	[1808r,1880r:0)  0@1808r
        -->	[1876r,1880r:0)  0@1876r
handleMove 2048B -> 2072B: %vreg85<def> = LDRWui %vreg86, 794; mem:LD4[%storedBlockCRC] GPR32:%vreg85 GPR64common:%vreg86
     %vreg85:	[2048r,2160r:0)  0@2048r
        -->	[2072r,2160r:0)  0@2072r
     %vreg86:	[2032r,2048r:0)  0@2032r
        -->	[2032r,2072r:0)  0@2032r
handleMove 2016B -> 2068B: %vreg89<def> = LDRXui %vreg88, 0; mem:LD8[@stderr] GPR64:%vreg89 GPR64sp:%vreg88
     %vreg89:	[2016r,2128r:0)  0@2016r
        -->	[2068r,2128r:0)  0@2068r
     %vreg88:	[2000r,2016r:0)  0@2000r
        -->	[2000r,2068r:0)  0@2000r
handleMove 2000B -> 2072B: %vreg88<def> = ADDXri %vreg87, <ga:@stderr>[TF=34], 0; GPR64sp:%vreg88 GPR64common:%vreg87
     %vreg88:	[2000r,2080r:0)  0@2000r
        -->	[2072r,2080r:0)  0@2072r
     %vreg87:	[1984r,2000r:0)  0@1984r
        -->	[1984r,2072r:0)  0@1984r
handleMove 2624B -> 2648B: %vreg106<def> = LDRWui %vreg107, 796; mem:LD4[%calculatedBlockCRC35] GPR32:%vreg106 GPR64common:%vreg107
     %vreg106:	[2624r,2672r:0)  0@2624r
        -->	[2648r,2672r:0)  0@2648r
     %vreg107:	[2608r,2624r:0)  0@2608r
        -->	[2608r,2648r:0)  0@2608r
AllocationOrder(GPR32sponly) = [ ]
handleMove 2784B -> 3032B: %vreg108<def> = MOVi32imm 14; GPR32:%vreg108
     %vreg108:	[2784r,3040r:0)  0@2784r
        -->	[3032r,3040r:0)  0@3032r
handleMove 2944B -> 2968B: %vreg119<def> = LDRWui %vreg120, 796; mem:LD4[%calculatedBlockCRC42] GPR32:%vreg119 GPR64common:%vreg120
     %vreg119:	[2944r,2992r:0)  0@2944r
        -->	[2968r,2992r:0)  0@2968r
     %vreg120:	[2928r,2944r:0)  0@2928r
        -->	[2928r,2968r:0)  0@2928r
handleMove 2880B -> 2904B: %vreg126<def> = ORRWrs %vreg128, %vreg133, 1; GPR32:%vreg126,%vreg128,%vreg133
     %vreg126:	[2880r,2912r:0)  0@2880r
        -->	[2904r,2912r:0)  0@2904r
     %vreg128:	[2864r,2880r:0)  0@2864r
        -->	[2864r,2904r:0)  0@2864r
     %vreg133:	[2816r,2880r:0)  0@2816r
        -->	[2816r,2904r:0)  0@2816r
handleMove 2864B -> 2900B: %vreg128<def> = UBFMWri %vreg130, 31, 31; GPR32:%vreg128,%vreg130
     %vreg128:	[2864r,2904r:0)  0@2864r
        -->	[2900r,2904r:0)  0@2900r
     %vreg130:	[2848r,2864r:0)  0@2848r
        -->	[2848r,2900r:0)  0@2848r
handleMove 2816B -> 2856B: %vreg133<def> = LDRWui %vreg134, 797; mem:LD4[%calculatedCombinedCRC] GPR32:%vreg133 GPR64common:%vreg134
     %vreg133:	[2816r,2904r:0)  0@2816r
        -->	[2856r,2904r:0)  0@2856r
     %vreg134:	[2800r,2816r:0)  0@2800r
        -->	[2800r,2856r:0)  0@2800r
handleMove 2800B -> 2840B: %vreg134<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg134
     %vreg134:	[2800r,2856r:0)  0@2800r
        -->	[2840r,2856r:0)  0@2840r
handleMove 3616B -> 3640B: %vreg164<def> = LDRWui %vreg165, 795; mem:LD4[%storedCombinedCRC] GPR32:%vreg164 GPR64common:%vreg165
     %vreg164:	[3616r,3728r:0)  0@3616r
        -->	[3640r,3728r:0)  0@3640r
     %vreg165:	[3600r,3616r:0)  0@3600r
        -->	[3600r,3640r:0)  0@3600r
handleMove 3584B -> 3636B: %vreg168<def> = LDRXui %vreg167, 0; mem:LD8[@stderr] GPR64:%vreg168 GPR64sp:%vreg167
     %vreg168:	[3584r,3696r:0)  0@3584r
        -->	[3636r,3696r:0)  0@3636r
     %vreg167:	[3568r,3584r:0)  0@3568r
        -->	[3568r,3636r:0)  0@3568r
handleMove 3568B -> 3640B: %vreg167<def> = ADDXri %vreg166, <ga:@stderr>[TF=34], 0; GPR64sp:%vreg167 GPR64common:%vreg166
     %vreg167:	[3568r,3648r:0)  0@3568r
        -->	[3640r,3648r:0)  0@3640r
     %vreg166:	[3552r,3568r:0)  0@3552r
        -->	[3552r,3640r:0)  0@3552r
handleMove 3888B -> 3912B: %vreg175<def> = LDRWui %vreg176, 797; mem:LD4[%calculatedCombinedCRC60] GPR32:%vreg175 GPR64common:%vreg176
     %vreg175:	[3888r,3936r:0)  0@3888r
        -->	[3912r,3936r:0)  0@3912r
     %vreg176:	[3872r,3888r:0)  0@3872r
        -->	[3872r,3912r:0)  0@3872r
********** GREEDY REGISTER ALLOCATION **********
********** Function: BZ2_bzDecompress
********** INTERVALS **********
W30 [0B,16r:0)[176r,176d:16)[224e,224d:8)[1104r,1104d:14)[1184e,1184d:7)[1312r,1312d:15)[1392e,1392d:6)[2192r,2192d:13)[2256e,2256d:5)[2496r,2496d:12)[2560e,2560d:4)[3296r,3296d:11)[3360e,3360d:3)[3760r,3760d:10)[3824e,3824d:2)[4432r,4432d:9)[4480e,4480d:1)  0@0B-phi 1@4480e 2@3824e 3@3360e 4@2560e 5@2256e 6@1392e 7@1184e 8@224e 9@4432r 10@3760r 11@3296r 12@2496r 13@2192r 14@1104r 15@1312r 16@176r
W0 [0B,32r:0)[144r,176r:15)[1088r,1104r:13)[1104r,1136r:6)[1296r,1312r:14)[1312r,1344r:7)[2128r,2192r:12)[2192r,2224r:5)[2464r,2496r:11)[2496r,2528r:4)[3280r,3296r:10)[3296r,3328r:3)[3696r,3760r:9)[3760r,3792r:2)[4400r,4432r:8)[4528r,4544r:1)  0@0B-phi 1@4528r 2@3760r 3@3296r 4@2496r 5@2192r 6@1104r 7@1312r 8@4400r 9@3696r 10@3280r 11@2464r 12@2128r 13@1088r 14@1296r 15@144r
%vreg1 [32r,256r:0)  0@32r
%vreg3 [272r,288r:0)  0@272r
%vreg4 [64r,80r:0)  0@64r
%vreg6 [80r,144r:0)  0@80r
%vreg7 [16r,4416r:0)  0@16r
%vreg10 [448r,464r:0)  0@448r
%vreg13 [400r,432r:0)  0@400r
%vreg16 [384r,400r:0)  0@384r
%vreg19 [592r,608r:0)  0@592r
%vreg21 [576r,608r:0)  0@576r
%vreg22 [560r,576r:0)  0@560r
%vreg25 [768r,784r:0)  0@768r
%vreg26 [752r,768r:0)  0@752r
%vreg29 [912r,928r:0)  0@912r
%vreg30 [896r,912r:0)  0@896r
%vreg32 [1008r,1024r:0)  0@1008r
%vreg34 [992r,1008r:0)  0@992r
%vreg35 [976r,992r:0)  0@976r
%vreg36 [1344r,1424r:0)  0@1344r
%vreg39 [1264r,1296r:0)  0@1264r
%vreg40 [1136r,1216r:0)  0@1136r
%vreg43 [1056r,1088r:0)  0@1056r
%vreg45 [1472r,1488r:0)  0@1472r
%vreg46 [1456r,1472r:0)  0@1456r
%vreg50 [1680r,1696r:0)  0@1680r
%vreg52 [1632r,1648r:0)  0@1632r
%vreg53 [1648r,1664r:0)  0@1648r
%vreg54 [1664r,1680r:0)  0@1664r
%vreg55 [1616r,1648r:0)  0@1616r
%vreg57 [1672r,1696r:0)  0@1672r
%vreg58 [1624r,1672r:0)  0@1624r
%vreg61 [1760r,1776r:0)  0@1760r
%vreg62 [1744r,1760r:0)  0@1744r
%vreg65 [1920r,1936r:0)  0@1920r
%vreg66 [1904r,1920r:0)  0@1904r
%vreg69 [1872r,1888r:0)  0@1872r
%vreg71 [1876r,1880r:0)  0@1876r
%vreg72 [1880r,1888r:0)  0@1880r
%vreg74 [1840r,1880r:0)  0@1840r
%vreg75 [1824r,1840r:0)  0@1824r
%vreg79 [2112r,2144r:0)  0@2112r
%vreg80 [2224r,2224d:0)  0@2224r
%vreg82 [2096r,2176r:0)  0@2096r
%vreg83 [2064r,2096r:0)  0@2064r
%vreg85 [2088r,2160r:0)  0@2088r
%vreg86 [2032r,2088r:0)  0@2032r
%vreg87 [1984r,2072r:0)  0@1984r
%vreg88 [2072r,2080r:0)  0@2072r
%vreg89 [2080r,2128r:0)  0@2080r
%vreg92 [2320r,2336r:0)  0@2320r
%vreg93 [2304r,2320r:0)  0@2304r
%vreg95 [2448r,2480r:0)  0@2448r
%vreg96 [2528r,2528d:0)  0@2528r
%vreg97 [2384r,2400r:0)  0@2384r
%vreg98 [2400r,2416r:0)  0@2400r
%vreg99 [2416r,2464r:0)  0@2416r
%vreg103 [2656r,2672r:0)  0@2656r
%vreg104 [2640r,2656r:0)  0@2640r
%vreg106 [2648r,2672r:0)  0@2648r
%vreg107 [2608r,2648r:0)  0@2608r
%vreg108 [3032r,3040r:0)  0@3032r
%vreg110 [3024r,3040r:0)  0@3024r
%vreg115 [2992r,3008r:0)  0@2992r
%vreg116 [2976r,2992r:0)  0@2976r
%vreg117 [2960r,3008r:0)  0@2960r
%vreg119 [2968r,2992r:0)  0@2968r
%vreg120 [2928r,2968r:0)  0@2928r
%vreg123 [2896r,2912r:0)  0@2896r
%vreg126 [2904r,2912r:0)  0@2904r
%vreg128 [2900r,2904r:0)  0@2900r
%vreg130 [2848r,2900r:0)  0@2848r
%vreg131 [2832r,2848r:0)  0@2832r
%vreg133 [2856r,2904r:0)  0@2856r
%vreg134 [2840r,2856r:0)  0@2840r
%vreg137 [3184r,3200r:0)  0@3184r
%vreg138 [3168r,3184r:0)  0@3168r
%vreg140 [3408r,3424r:0)  0@3408r
%vreg143 [3328r,3392r:0)  0@3328r
%vreg144 [3248r,3280r:0)  0@3248r
%vreg147 [4128r,4144r:0)  0@4128r
%vreg148 [4112r,4128r:0)  0@4112r
%vreg150 [4192r,4208r:0)  0@4192r
%vreg153 [3488r,3504r:0)  0@3488r
%vreg154 [3472r,3488r:0)  0@3472r
%vreg158 [3680r,3712r:0)  0@3680r
%vreg159 [3792r,3792d:0)  0@3792r
%vreg161 [3664r,3744r:0)  0@3664r
%vreg162 [3632r,3664r:0)  0@3632r
%vreg164 [3656r,3728r:0)  0@3656r
%vreg165 [3600r,3656r:0)  0@3600r
%vreg166 [3552r,3640r:0)  0@3552r
%vreg167 [3640r,3648r:0)  0@3640r
%vreg168 [3648r,3696r:0)  0@3648r
%vreg172 [3920r,3936r:0)  0@3920r
%vreg173 [3904r,3920r:0)  0@3904r
%vreg175 [3912r,3936r:0)  0@3912r
%vreg176 [3872r,3912r:0)  0@3872r
%vreg178 [4048r,4064r:0)  0@4048r
%vreg179 [3984r,4000r:0)  0@3984r
%vreg180 [2720r,2736r:0)  0@2720r
%vreg181 [1520r,1536r:0)  0@1520r
%vreg182 [832r,848r:0)  0@832r
%vreg183 [656r,672r:0)  0@656r
%vreg184 [496r,512r:0)  0@496r
%vreg185 [320r,336r:0)  0@320r
%vreg187 [4512r,4528r:0)  0@4512r
%vreg188 [4320r,4336r:0)  0@4320r
%vreg190 [4336r,4400r:0)  0@4336r
RegMasks: 176r 1104r 1312r 2192r 2496r 3296r 3760r 4432r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzDecompress: Post SSA
Frame Objects:
  fi#0: size=4, align=4, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=1, align=1, at location [SP]
  fi#3: size=8, align=8, at location [SP]
  fi#4: size=4, align=4, at location [SP]
Function Live Ins: %X0 in %vreg0, %LR in %vreg8

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %LR
16B		%vreg7<def> = COPY %LR; GPR64:%vreg7
32B		%vreg1<def> = COPY %X0; GPR64:%vreg1
64B		%vreg4<def> = ADRP <ga:@BZ2_bzDecompress>[TF=1]; GPR64common:%vreg4
80B		%vreg6<def> = ADDXri %vreg4, <ga:@BZ2_bzDecompress>[TF=34], 0; GPR64sp:%vreg6 GPR64common:%vreg4
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		%X0<def> = COPY %vreg6; GPR64sp:%vreg6
160B		%X1<def> = COPY %vreg7; GPR64:%vreg7
176B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
224B		STACKMAP 0, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, %vreg1, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3] LD8[FixedStack1] GPR64:%vreg1
240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
256B		STRXui %vreg1, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg1
272B		%vreg3<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg3
288B		CBNZX %vreg3, <BB#2>; GPR64:%vreg3
	    Successors according to CFG: BB#2 BB#1

304B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
320B		%vreg185<def> = MOVi32imm 4294967294; GPR32:%vreg185
336B		STRWui %vreg185, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg185
352B		B <BB#37>
	    Successors according to CFG: BB#37

368B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0
384B		%vreg16<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg16
400B		%vreg13<def> = LDRXui %vreg16, 6; mem:LD8[%state] GPR64:%vreg13 GPR64common:%vreg16
432B		STRXui %vreg13, <fi#3>, 0; mem:ST8[FixedStack3] GPR64:%vreg13
448B		%vreg10<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg10
464B		CBNZX %vreg10, <BB#4>; GPR64:%vreg10
	    Successors according to CFG: BB#4 BB#3

480B	BB#3: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#2
496B		%vreg184<def> = MOVi32imm 4294967294; GPR32:%vreg184
512B		STRWui %vreg184, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg184
528B		B <BB#37>
	    Successors according to CFG: BB#37

544B	BB#4: derived from LLVM BB %if.end.3
	    Predecessors according to CFG: BB#2
560B		%vreg22<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg22
576B		%vreg21<def> = LDRXui %vreg22, 0; mem:LD8[%strm4] GPR64:%vreg21 GPR64common:%vreg22
592B		%vreg19<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg19
608B		%XZR<def> = SUBSXrr %vreg21, %vreg19, %NZCV<imp-def>; GPR64:%vreg21,%vreg19
624B		Bcc 0, <BB#6>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#6 BB#5

640B	BB#5: derived from LLVM BB %if.then.6
	    Predecessors according to CFG: BB#4
656B		%vreg183<def> = MOVi32imm 4294967294; GPR32:%vreg183
672B		STRWui %vreg183, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg183
688B		B <BB#37>
	    Successors according to CFG: BB#37

704B	BB#6: derived from LLVM BB %if.end.7
	    Predecessors according to CFG: BB#4
720B		B <BB#7>
	    Successors according to CFG: BB#7

736B	BB#7: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#6 BB#36
752B		%vreg26<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg26
768B		%vreg25<def> = LDRWui %vreg26, 2; mem:LD4[%state8] GPR32common:%vreg25 GPR64common:%vreg26
784B		%WZR<def> = SUBSWri %vreg25, 1, 0, %NZCV<imp-def>; GPR32common:%vreg25
800B		Bcc 1, <BB#9>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#9 BB#8

816B	BB#8: derived from LLVM BB %if.then.10
	    Predecessors according to CFG: BB#7
832B		%vreg182<def> = MOVi32imm 4294967295; GPR32:%vreg182
848B		STRWui %vreg182, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg182
864B		B <BB#37>
	    Successors according to CFG: BB#37

880B	BB#9: derived from LLVM BB %if.end.11
	    Predecessors according to CFG: BB#7
896B		%vreg30<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg30
912B		%vreg29<def> = LDRWui %vreg30, 2; mem:LD4[%state12] GPR32common:%vreg29 GPR64common:%vreg30
928B		%WZR<def> = SUBSWri %vreg29, 2, 0, %NZCV<imp-def>; GPR32common:%vreg29
944B		Bcc 1, <BB#26>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#26 BB#10

960B	BB#10: derived from LLVM BB %if.then.14
	    Predecessors according to CFG: BB#9
976B		%vreg35<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg35
992B		%vreg34<def> = LDRBBui %vreg35, 44; mem:LD1[%smallDecompress] GPR32:%vreg34 GPR64common:%vreg35
1008B		%vreg32<def> = UBFMWri %vreg34, 0, 7; GPR32:%vreg32,%vreg34
1024B		CBZW %vreg32, <BB#12>; GPR32:%vreg32
	    Successors according to CFG: BB#12 BB#11

1040B	BB#11: derived from LLVM BB %if.then.15
	    Predecessors according to CFG: BB#10
1056B		%vreg43<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg43
1072B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1088B		%X0<def> = COPY %vreg43; GPR64:%vreg43
1104B		BL <ga:@unRLE_obuf_to_output_SMALL>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>
1120B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1136B		%vreg40<def> = COPY %W0; GPR32:%vreg40
1168B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1184B		STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
1200B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1216B		STRBBui %vreg40, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg40
1232B		B <BB#13>
	    Successors according to CFG: BB#13

1248B	BB#12: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#10
1264B		%vreg39<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg39
1280B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1296B		%X0<def> = COPY %vreg39; GPR64:%vreg39
1312B		BL <ga:@unRLE_obuf_to_output_FAST>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>
1328B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1344B		%vreg36<def> = COPY %W0; GPR32:%vreg36
1376B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1392B		STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
1408B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1424B		STRBBui %vreg36, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg36
	    Successors according to CFG: BB#13

1440B	BB#13: derived from LLVM BB %if.end.17
	    Predecessors according to CFG: BB#12 BB#11
1456B		%vreg46<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg46
1472B		%vreg45<def> = UBFMWri %vreg46, 0, 7; GPR32:%vreg45,%vreg46
1488B		CBZW %vreg45, <BB#15>; GPR32:%vreg45
	    Successors according to CFG: BB#15 BB#14

1504B	BB#14: derived from LLVM BB %if.then.19
	    Predecessors according to CFG: BB#13
1520B		%vreg181<def> = MOVi32imm 4294967292; GPR32:%vreg181
1536B		STRWui %vreg181, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg181
1552B		B <BB#37>
	    Successors according to CFG: BB#37

1568B	BB#15: derived from LLVM BB %if.end.20
	    Predecessors according to CFG: BB#13
1616B		%vreg55<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg55
1624B		%vreg58<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg58
1632B		%vreg52<def> = MOVi64imm 64080; GPR64:%vreg52
1648B		%vreg53<def> = ADDXrr %vreg55, %vreg52; GPR64common:%vreg53 GPR64:%vreg55,%vreg52
1664B		%vreg54<def> = LDRWui %vreg53, 0; mem:LD4[%save_nblock] GPR32common:%vreg54 GPR64common:%vreg53
1672B		%vreg57<def> = LDRWui %vreg58, 273; mem:LD4[%nblock_used] GPR32:%vreg57 GPR64common:%vreg58
1680B		%vreg50<def> = ADDWri %vreg54, 1, 0; GPR32common:%vreg50,%vreg54
1696B		%WZR<def> = SUBSWrr %vreg57, %vreg50, %NZCV<imp-def>; GPR32:%vreg57 GPR32common:%vreg50
1712B		Bcc 1, <BB#24>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#24 BB#16

1728B	BB#16: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#15
1744B		%vreg62<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg62
1760B		%vreg61<def> = LDRWui %vreg62, 4; mem:LD4[%state_out_len] GPR32:%vreg61 GPR64common:%vreg62
1776B		CBNZW %vreg61, <BB#24>; GPR32:%vreg61
	    Successors according to CFG: BB#24 BB#17

1792B	BB#17: derived from LLVM BB %if.then.23
	    Predecessors according to CFG: BB#16
1824B		%vreg75<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg75
1840B		%vreg74<def> = LDRWui %vreg75, 796; mem:LD4[%calculatedBlockCRC] GPR32:%vreg74 GPR64common:%vreg75
1872B		%vreg69<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg69
1876B		%vreg71<def> = MOVi32imm 4294967295; GPR32:%vreg71
1880B		%vreg72<def> = EORWrr %vreg74, %vreg71; GPR32:%vreg72,%vreg74,%vreg71
1888B		STRWui %vreg72, %vreg69, 796; mem:ST4[%calculatedBlockCRC24] GPR32:%vreg72 GPR64common:%vreg69
1904B		%vreg66<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg66
1920B		%vreg65<def> = LDRWui %vreg66, 13; mem:LD4[%verbosity] GPR32common:%vreg65 GPR64common:%vreg66
1936B		%WZR<def> = SUBSWri %vreg65, 3, 0, %NZCV<imp-def>; GPR32common:%vreg65
1952B		Bcc 11, <BB#19>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#19 BB#18

1968B	BB#18: derived from LLVM BB %if.then.26
	    Predecessors according to CFG: BB#17
1984B		%vreg87<def> = ADRP <ga:@stderr>[TF=1]; GPR64common:%vreg87
2032B		%vreg86<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg86
2064B		%vreg83<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg83
2072B		%vreg88<def> = ADDXri %vreg87, <ga:@stderr>[TF=34], 0; GPR64sp:%vreg88 GPR64common:%vreg87
2080B		%vreg89<def> = LDRXui %vreg88, 0; mem:LD8[@stderr] GPR64:%vreg89 GPR64sp:%vreg88
2088B		%vreg85<def> = LDRWui %vreg86, 794; mem:LD4[%storedBlockCRC] GPR32:%vreg85 GPR64common:%vreg86
2096B		%vreg82<def> = LDRWui %vreg83, 796; mem:LD4[%calculatedBlockCRC27] GPR32:%vreg82 GPR64common:%vreg83
2104B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2112B		%vreg79<def> = MOVaddr <ga:@bzlib__str_2___0x_08x__>[TF=1], <ga:@bzlib__str_2___0x_08x__>[TF=34]; GPR64:%vreg79
2128B		%X0<def> = COPY %vreg89; GPR64:%vreg89
2144B		%X1<def> = COPY %vreg79; GPR64:%vreg79
2160B		%W2<def> = COPY %vreg85; GPR32:%vreg85
2176B		%W3<def> = COPY %vreg82; GPR32:%vreg82
2192B		BL <ga:@fprintf>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %W2<imp-use,kill>, %W3<imp-use,kill>, %SP<imp-def>, %W0<imp-def>
2208B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2224B		%vreg80<def,dead> = COPY %W0; GPR32all:%vreg80
2240B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2256B		STACKMAP 3, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
2272B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#19

2288B	BB#19: derived from LLVM BB %if.end.29
	    Predecessors according to CFG: BB#17 BB#18
2304B		%vreg93<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg93
2320B		%vreg92<def> = LDRWui %vreg93, 13; mem:LD4[%verbosity30] GPR32common:%vreg92 GPR64common:%vreg93
2336B		%WZR<def> = SUBSWri %vreg92, 2, 0, %NZCV<imp-def>; GPR32common:%vreg92
2352B		Bcc 11, <BB#21>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#21 BB#20

2368B	BB#20: derived from LLVM BB %if.then.32
	    Predecessors according to CFG: BB#19
2384B		%vreg97<def> = ADRP <ga:@stderr>[TF=1]; GPR64common:%vreg97
2400B		%vreg98<def> = ADDXri %vreg97, <ga:@stderr>[TF=34], 0; GPR64sp:%vreg98 GPR64common:%vreg97
2416B		%vreg99<def> = LDRXui %vreg98, 0; mem:LD8[@stderr] GPR64:%vreg99 GPR64sp:%vreg98
2432B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2448B		%vreg95<def> = MOVaddr <ga:@bzlib__str_3___>[TF=1], <ga:@bzlib__str_3___>[TF=34]; GPR64:%vreg95
2464B		%X0<def> = COPY %vreg99; GPR64:%vreg99
2480B		%X1<def> = COPY %vreg95; GPR64:%vreg95
2496B		BL <ga:@fprintf>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %SP<imp-def>, %W0<imp-def>
2512B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2528B		%vreg96<def,dead> = COPY %W0; GPR32all:%vreg96
2544B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2560B		STACKMAP 4, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
2576B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#21

2592B	BB#21: derived from LLVM BB %if.end.34
	    Predecessors according to CFG: BB#19 BB#20
2608B		%vreg107<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg107
2640B		%vreg104<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg104
2648B		%vreg106<def> = LDRWui %vreg107, 796; mem:LD4[%calculatedBlockCRC35] GPR32:%vreg106 GPR64common:%vreg107
2656B		%vreg103<def> = LDRWui %vreg104, 794; mem:LD4[%storedBlockCRC36] GPR32:%vreg103 GPR64common:%vreg104
2672B		%WZR<def> = SUBSWrr %vreg106, %vreg103, %NZCV<imp-def>; GPR32:%vreg106,%vreg103
2688B		Bcc 0, <BB#23>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#23 BB#22

2704B	BB#22: derived from LLVM BB %if.then.38
	    Predecessors according to CFG: BB#21
2720B		%vreg180<def> = MOVi32imm 4294967292; GPR32:%vreg180
2736B		STRWui %vreg180, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg180
2752B		B <BB#37>
	    Successors according to CFG: BB#37

2768B	BB#23: derived from LLVM BB %if.end.39
	    Predecessors according to CFG: BB#21
2832B		%vreg131<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg131
2840B		%vreg134<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg134
2848B		%vreg130<def> = LDRWui %vreg131, 797; mem:LD4[%calculatedCombinedCRC40] GPR32:%vreg130 GPR64common:%vreg131
2856B		%vreg133<def> = LDRWui %vreg134, 797; mem:LD4[%calculatedCombinedCRC] GPR32:%vreg133 GPR64common:%vreg134
2896B		%vreg123<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg123
2900B		%vreg128<def> = UBFMWri %vreg130, 31, 31; GPR32:%vreg128,%vreg130
2904B		%vreg126<def> = ORRWrs %vreg128, %vreg133, 1; GPR32:%vreg126,%vreg128,%vreg133
2912B		STRWui %vreg126, %vreg123, 797; mem:ST4[%calculatedCombinedCRC41] GPR32:%vreg126 GPR64common:%vreg123
2928B		%vreg120<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg120
2960B		%vreg117<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg117
2968B		%vreg119<def> = LDRWui %vreg120, 796; mem:LD4[%calculatedBlockCRC42] GPR32:%vreg119 GPR64common:%vreg120
2976B		%vreg116<def> = LDRWui %vreg117, 797; mem:LD4[%calculatedCombinedCRC43] GPR32:%vreg116 GPR64common:%vreg117
2992B		%vreg115<def> = EORWrr %vreg116, %vreg119; GPR32:%vreg115,%vreg116,%vreg119
3008B		STRWui %vreg115, %vreg117, 797; mem:ST4[%calculatedCombinedCRC43] GPR32:%vreg115 GPR64common:%vreg117
3024B		%vreg110<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg110
3032B		%vreg108<def> = MOVi32imm 14; GPR32:%vreg108
3040B		STRWui %vreg108, %vreg110, 2; mem:ST4[%state44] GPR32:%vreg108 GPR64common:%vreg110
3056B		B <BB#25>
	    Successors according to CFG: BB#25

3072B	BB#24: derived from LLVM BB %if.else.45
	    Predecessors according to CFG: BB#15 BB#16
3088B		STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
3104B		B <BB#37>
	    Successors according to CFG: BB#37

3120B	BB#25: derived from LLVM BB %if.end.46
	    Predecessors according to CFG: BB#23
3136B		B <BB#26>
	    Successors according to CFG: BB#26

3152B	BB#26: derived from LLVM BB %if.end.47
	    Predecessors according to CFG: BB#9 BB#25
3168B		%vreg138<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg138
3184B		%vreg137<def> = LDRWui %vreg138, 2; mem:LD4[%state48] GPR32common:%vreg137 GPR64common:%vreg138
3200B		%WZR<def> = SUBSWri %vreg137, 10, 0, %NZCV<imp-def>; GPR32common:%vreg137
3216B		Bcc 11, <BB#36>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#36 BB#27

3232B	BB#27: derived from LLVM BB %if.then.50
	    Predecessors according to CFG: BB#26
3248B		%vreg144<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg144
3264B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3280B		%X0<def> = COPY %vreg144; GPR64:%vreg144
3296B		BL <ga:@BZ2_decompress>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
3312B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3328B		%vreg143<def> = COPY %W0; GPR32:%vreg143
3344B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3360B		STACKMAP 5, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
3376B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3392B		STRWui %vreg143, <fi#4>, 0; mem:ST4[FixedStack4] GPR32:%vreg143
3408B		%vreg140<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32common:%vreg140
3424B		%WZR<def> = SUBSWri %vreg140, 4, 0, %NZCV<imp-def>; GPR32common:%vreg140
3440B		Bcc 1, <BB#33>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#33 BB#28

3456B	BB#28: derived from LLVM BB %if.then.53
	    Predecessors according to CFG: BB#27
3472B		%vreg154<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg154
3488B		%vreg153<def> = LDRWui %vreg154, 13; mem:LD4[%verbosity54] GPR32common:%vreg153 GPR64common:%vreg154
3504B		%WZR<def> = SUBSWri %vreg153, 3, 0, %NZCV<imp-def>; GPR32common:%vreg153
3520B		Bcc 11, <BB#30>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#30 BB#29

3536B	BB#29: derived from LLVM BB %if.then.56
	    Predecessors according to CFG: BB#28
3552B		%vreg166<def> = ADRP <ga:@stderr>[TF=1]; GPR64common:%vreg166
3600B		%vreg165<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg165
3632B		%vreg162<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg162
3640B		%vreg167<def> = ADDXri %vreg166, <ga:@stderr>[TF=34], 0; GPR64sp:%vreg167 GPR64common:%vreg166
3648B		%vreg168<def> = LDRXui %vreg167, 0; mem:LD8[@stderr] GPR64:%vreg168 GPR64sp:%vreg167
3656B		%vreg164<def> = LDRWui %vreg165, 795; mem:LD4[%storedCombinedCRC] GPR32:%vreg164 GPR64common:%vreg165
3664B		%vreg161<def> = LDRWui %vreg162, 797; mem:LD4[%calculatedCombinedCRC57] GPR32:%vreg161 GPR64common:%vreg162
3672B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3680B		%vreg158<def> = MOVaddr <ga:@bzlib__str_4______combi>[TF=1], <ga:@bzlib__str_4______combi>[TF=34]; GPR64:%vreg158
3696B		%X0<def> = COPY %vreg168; GPR64:%vreg168
3712B		%X1<def> = COPY %vreg158; GPR64:%vreg158
3728B		%W2<def> = COPY %vreg164; GPR32:%vreg164
3744B		%W3<def> = COPY %vreg161; GPR32:%vreg161
3760B		BL <ga:@fprintf>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %W2<imp-use,kill>, %W3<imp-use,kill>, %SP<imp-def>, %W0<imp-def>
3776B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3792B		%vreg159<def,dead> = COPY %W0; GPR32all:%vreg159
3808B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3824B		STACKMAP 6, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
3840B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#30

3856B	BB#30: derived from LLVM BB %if.end.59
	    Predecessors according to CFG: BB#28 BB#29
3872B		%vreg176<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg176
3904B		%vreg173<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg173
3912B		%vreg175<def> = LDRWui %vreg176, 797; mem:LD4[%calculatedCombinedCRC60] GPR32:%vreg175 GPR64common:%vreg176
3920B		%vreg172<def> = LDRWui %vreg173, 795; mem:LD4[%storedCombinedCRC61] GPR32:%vreg172 GPR64common:%vreg173
3936B		%WZR<def> = SUBSWrr %vreg175, %vreg172, %NZCV<imp-def>; GPR32:%vreg175,%vreg172
3952B		Bcc 0, <BB#32>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#32 BB#31

3968B	BB#31: derived from LLVM BB %if.then.63
	    Predecessors according to CFG: BB#30
3984B		%vreg179<def> = MOVi32imm 4294967292; GPR32:%vreg179
4000B		STRWui %vreg179, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg179
4016B		B <BB#37>
	    Successors according to CFG: BB#37

4032B	BB#32: derived from LLVM BB %if.end.64
	    Predecessors according to CFG: BB#30
4048B		%vreg178<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg178
4064B		STRWui %vreg178, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg178
4080B		B <BB#37>
	    Successors according to CFG: BB#37

4096B	BB#33: derived from LLVM BB %if.end.65
	    Predecessors according to CFG: BB#27
4112B		%vreg148<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg148
4128B		%vreg147<def> = LDRWui %vreg148, 2; mem:LD4[%state66] GPR32common:%vreg147 GPR64common:%vreg148
4144B		%WZR<def> = SUBSWri %vreg147, 2, 0, %NZCV<imp-def>; GPR32common:%vreg147
4160B		Bcc 0, <BB#35>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#35 BB#34

4176B	BB#34: derived from LLVM BB %if.then.68
	    Predecessors according to CFG: BB#33
4192B		%vreg150<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg150
4208B		STRWui %vreg150, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg150
4224B		B <BB#37>
	    Successors according to CFG: BB#37

4240B	BB#35: derived from LLVM BB %if.end.69
	    Predecessors according to CFG: BB#33
4256B		B <BB#36>
	    Successors according to CFG: BB#36

4272B	BB#36: derived from LLVM BB %if.end.70
	    Predecessors according to CFG: BB#26 BB#35
4288B		B <BB#7>
	    Successors according to CFG: BB#7

4304B	BB#37: derived from LLVM BB %return
	    Predecessors according to CFG: BB#24 BB#34 BB#32 BB#31 BB#22 BB#14 BB#8 BB#5 BB#3 BB#1
4320B		%vreg188<def> = ADRP <ga:@BZ2_bzDecompress>[TF=1]; GPR64common:%vreg188
4336B		%vreg190<def> = ADDXri %vreg188, <ga:@BZ2_bzDecompress>[TF=34], 0; GPR64sp:%vreg190 GPR64common:%vreg188
4384B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4400B		%X0<def> = COPY %vreg190; GPR64sp:%vreg190
4416B		%X1<def> = COPY %vreg7; GPR64:%vreg7
4432B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
4448B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4464B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4480B		STACKMAP 7, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
4496B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4512B		%vreg187<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0] GPR32:%vreg187
4528B		%W0<def> = COPY %vreg187; GPR32:%vreg187
4544B		RET_ReallyLR %W0<imp-use>

# End machine code for function BZ2_bzDecompress.


selectOrSplit GPR64:%vreg7 [16r,4416r:0)  0@16r w=6.312500e-04
hints: %X1
missed hint %X1
Analyze counted 3 instrs in 2 blocks, through 36 blocks.
%X1	static = 1.0 worse than no bundles
%X8	static = 1.0 worse than no bundles
%X9	static = 1.0 worse than no bundles
%X10	static = 1.0 worse than no bundles
%X11	static = 1.0 worse than no bundles
%X12	static = 1.0 worse than no bundles
%X13	static = 1.0 worse than no bundles
%X14	static = 1.0 worse than no bundles
%X15	static = 1.0 worse than no bundles
%X16	static = 1.0 worse than no bundles
%X17	static = 1.0 worse than no bundles
%X18	static = 1.0 worse than no bundles
%X0	no positive bundles
%X2	static = 1.0 worse than no bundles
%X3	static = 1.0 worse than no bundles
%X4	static = 1.0 worse than no bundles
%X5	static = 1.0 worse than no bundles
%X6	static = 1.0 worse than no bundles
%X7	static = 1.0 worse than no bundles
assigning %vreg7 to %X19: W19 [16r,4416r:0)  0@16r

selectOrSplit GPR64:%vreg1 [32r,256r:0)  0@32r w=4.855769e-03
hints: %X0
missed hint %X0
Analyze counted 3 instrs in 1 blocks, through 0 blocks.
%X0	no positive bundles
%X8	no positive bundles
%X9	no positive bundles
%X10	no positive bundles
%X11	no positive bundles
%X12	no positive bundles
%X13	no positive bundles
%X14	no positive bundles
%X15	no positive bundles
%X16	no positive bundles
%X17	no positive bundles
%X18	no positive bundles
%X1	no positive bundles
%X2	no positive bundles
%X3	no positive bundles
%X4	no positive bundles
%X5	no positive bundles
%X6	no positive bundles
%X7	no positive bundles
%X19	no positive bundles
assigning %vreg1 to %X20: W20 [32r,256r:0)  0@32r

selectOrSplit GPR64sp:%vreg6 [80r,144r:0)  0@80r w=4.353448e-03
hints: %X0
assigning %vreg6 to %X0: W0 [80r,144r:0)  0@80r

selectOrSplit GPR64:%vreg43 [1056r,1088r:0)  0@1056r w=8.626159e-05
hints: %X0
assigning %vreg43 to %X0: W0 [1056r,1088r:0)  0@1056r

selectOrSplit GPR32:%vreg40 [1136r,1216r:0)  0@1136r w=7.763543e-05
hints: %W0
assigning %vreg40 to %W0: W0 [1136r,1216r:0)  0@1136r

selectOrSplit GPR64:%vreg39 [1264r,1296r:0)  0@1264r w=8.626159e-05
hints: %X0
assigning %vreg39 to %X0: W0 [1264r,1296r:0)  0@1264r

selectOrSplit GPR32:%vreg36 [1344r,1424r:0)  0@1344r w=7.763543e-05
hints: %W0
assigning %vreg36 to %W0: W0 [1344r,1424r:0)  0@1344r

selectOrSplit GPR64:%vreg89 [2080r,2128r:0)  0@2080r w=1.056264e-05
hints: %X0
assigning %vreg89 to %X0: W0 [2080r,2128r:0)  0@2080r

selectOrSplit GPR32:%vreg85 [2088r,2160r:0)  0@2088r w=1.002556e-05
hints: %W2
assigning %vreg85 to %W2: W2 [2088r,2160r:0)  0@2088r

selectOrSplit GPR32:%vreg82 [2096r,2176r:0)  0@2096r w=9.858468e-06
hints: %W3
assigning %vreg82 to %W3: W3 [2096r,2176r:0)  0@2096r

selectOrSplit GPR64:%vreg79 [2112r,2144r:0)  0@2112r w=5.476927e-06
hints: %X1
assigning %vreg79 to %X1: W1 [2112r,2144r:0)  0@2112r

selectOrSplit GPR32all:%vreg80 [2224r,2224d:0)  0@2224r w=inf
hints: %W0
assigning %vreg80 to %W0: W0 [2224r,2224d:0)  0@2224r

selectOrSplit GPR64:%vreg99 [2416r,2464r:0)  0@2416r w=1.056264e-05
hints: %X0
assigning %vreg99 to %X0: W0 [2416r,2464r:0)  0@2416r

selectOrSplit GPR64:%vreg95 [2448r,2480r:0)  0@2448r w=5.476927e-06
hints: %X1
assigning %vreg95 to %X1: W1 [2448r,2480r:0)  0@2448r

selectOrSplit GPR32all:%vreg96 [2528r,2528d:0)  0@2528r w=inf
hints: %W0
assigning %vreg96 to %W0: W0 [2528r,2528d:0)  0@2528r

selectOrSplit GPR64:%vreg144 [3248r,3280r:0)  0@3248r w=9.173852e-05
hints: %X0
assigning %vreg144 to %X0: W0 [3248r,3280r:0)  0@3248r

selectOrSplit GPR32:%vreg143 [3328r,3392r:0)  0@3328r w=8.541172e-05
hints: %W0
assigning %vreg143 to %W0: W0 [3328r,3392r:0)  0@3328r

selectOrSplit GPR64:%vreg168 [3648r,3696r:0)  0@3648r w=2.244562e-05
hints: %X0
assigning %vreg168 to %X0: W0 [3648r,3696r:0)  0@3648r

selectOrSplit GPR32:%vreg164 [3656r,3728r:0)  0@3656r w=2.130431e-05
hints: %W2
assigning %vreg164 to %W2: W2 [3656r,3728r:0)  0@3656r

selectOrSplit GPR32:%vreg161 [3664r,3744r:0)  0@3664r w=2.094924e-05
hints: %W3
assigning %vreg161 to %W3: W3 [3664r,3744r:0)  0@3664r

selectOrSplit GPR64:%vreg158 [3680r,3712r:0)  0@3680r w=1.163847e-05
hints: %X1
assigning %vreg158 to %X1: W1 [3680r,3712r:0)  0@3680r

selectOrSplit GPR32all:%vreg159 [3792r,3792d:0)  0@3792r w=inf
hints: %W0
assigning %vreg159 to %W0: W0 [3792r,3792d:0)  0@3792r

selectOrSplit GPR64sp:%vreg190 [4336r,4400r:0)  0@4336r w=4.353448e-03
hints: %X0
assigning %vreg190 to %X0: W0 [4336r,4400r:0)  0@4336r

selectOrSplit GPR32:%vreg187 [4512r,4528r:0)  0@4512r w=inf
hints: %W0
assigning %vreg187 to %W0: W0 [4512r,4528r:0)  0@4512r

selectOrSplit GPR64common:%vreg4 [64r,80r:0)  0@64r w=inf
assigning %vreg4 to %X8: W8 [64r,80r:0)  0@64r

selectOrSplit GPR64:%vreg3 [272r,288r:0)  0@272r w=inf
assigning %vreg3 to %X8: W8 [272r,288r:0)  0@272r

selectOrSplit GPR32:%vreg185 [320r,336r:0)  0@320r w=inf
assigning %vreg185 to %W8: W8 [320r,336r:0)  0@320r

selectOrSplit GPR64common:%vreg16 [384r,400r:0)  0@384r w=inf
assigning %vreg16 to %X8: W8 [384r,400r:0)  0@384r

selectOrSplit GPR64:%vreg13 [400r,432r:0)  0@400r w=inf
assigning %vreg13 to %X8: W8 [400r,432r:0)  0@400r

selectOrSplit GPR64:%vreg10 [448r,464r:0)  0@448r w=inf
assigning %vreg10 to %X8: W8 [448r,464r:0)  0@448r

selectOrSplit GPR32:%vreg184 [496r,512r:0)  0@496r w=inf
assigning %vreg184 to %W8: W8 [496r,512r:0)  0@496r

selectOrSplit GPR64common:%vreg22 [560r,576r:0)  0@560r w=inf
assigning %vreg22 to %X8: W8 [560r,576r:0)  0@560r

selectOrSplit GPR64:%vreg21 [576r,608r:0)  0@576r w=1.156391e-03
assigning %vreg21 to %X8: W8 [576r,608r:0)  0@576r

selectOrSplit GPR64:%vreg19 [592r,608r:0)  0@592r w=inf
assigning %vreg19 to %X9: W9 [592r,608r:0)  0@592r

selectOrSplit GPR32:%vreg183 [656r,672r:0)  0@656r w=inf
assigning %vreg183 to %W8: W8 [656r,672r:0)  0@656r

selectOrSplit GPR64common:%vreg26 [752r,768r:0)  0@752r w=inf
assigning %vreg26 to %X8: W8 [752r,768r:0)  0@752r

selectOrSplit GPR32common:%vreg25 [768r,784r:0)  0@768r w=inf
assigning %vreg25 to %W8: W8 [768r,784r:0)  0@768r

selectOrSplit GPR32:%vreg182 [832r,848r:0)  0@832r w=inf
assigning %vreg182 to %W8: W8 [832r,848r:0)  0@832r

selectOrSplit GPR64common:%vreg30 [896r,912r:0)  0@896r w=inf
assigning %vreg30 to %X8: W8 [896r,912r:0)  0@896r

selectOrSplit GPR32common:%vreg29 [912r,928r:0)  0@912r w=inf
assigning %vreg29 to %W8: W8 [912r,928r:0)  0@912r

selectOrSplit GPR64common:%vreg35 [976r,992r:0)  0@976r w=inf
assigning %vreg35 to %X8: W8 [976r,992r:0)  0@976r

selectOrSplit GPR32:%vreg34 [992r,1008r:0)  0@992r w=inf
assigning %vreg34 to %W8: W8 [992r,1008r:0)  0@992r

selectOrSplit GPR32:%vreg32 [1008r,1024r:0)  0@1008r w=inf
assigning %vreg32 to %W8: W8 [1008r,1024r:0)  0@1008r

selectOrSplit GPR32:%vreg46 [1456r,1472r:0)  0@1456r w=inf
assigning %vreg46 to %W8: W8 [1456r,1472r:0)  0@1456r

selectOrSplit GPR32:%vreg45 [1472r,1488r:0)  0@1472r w=inf
assigning %vreg45 to %W8: W8 [1472r,1488r:0)  0@1472r

selectOrSplit GPR32:%vreg181 [1520r,1536r:0)  0@1520r w=inf
assigning %vreg181 to %W8: W8 [1520r,1536r:0)  0@1520r

selectOrSplit GPR64:%vreg55 [1616r,1648r:0)  0@1616r w=8.540751e-05
assigning %vreg55 to %X8: W8 [1616r,1648r:0)  0@1616r

selectOrSplit GPR64common:%vreg58 [1624r,1672r:0)  0@1624r w=8.235725e-05
assigning %vreg58 to %X9: W9 [1624r,1672r:0)  0@1624r

selectOrSplit GPR64:%vreg52 [1632r,1648r:0)  0@1632r w=inf
assigning %vreg52 to %X10: W10 [1632r,1648r:0)  0@1632r

selectOrSplit GPR64common:%vreg53 [1648r,1664r:0)  0@1648r w=inf
assigning %vreg53 to %X8: W8 [1648r,1664r:0)  0@1648r

selectOrSplit GPR32common:%vreg54 [1664r,1680r:0)  0@1664r w=8.869242e-05
assigning %vreg54 to %W8: W8 [1664r,1680r:0)  0@1664r

selectOrSplit GPR32:%vreg57 [1672r,1696r:0)  0@1672r w=8.701898e-05
assigning %vreg57 to %W9: W9 [1672r,1696r:0)  0@1672r

selectOrSplit GPR32common:%vreg50 [1680r,1696r:0)  0@1680r w=inf
assigning %vreg50 to %W8: W8 [1680r,1696r:0)  0@1680r

selectOrSplit GPR64common:%vreg62 [1744r,1760r:0)  0@1744r w=inf
assigning %vreg62 to %X8: W8 [1744r,1760r:0)  0@1744r

selectOrSplit GPR32:%vreg61 [1760r,1776r:0)  0@1760r w=inf
assigning %vreg61 to %W8: W8 [1760r,1776r:0)  0@1760r

selectOrSplit GPR64common:%vreg75 [1824r,1840r:0)  0@1824r w=inf
assigning %vreg75 to %X8: W8 [1824r,1840r:0)  0@1824r

selectOrSplit GPR32:%vreg74 [1840r,1880r:0)  0@1840r w=1.996539e-05
assigning %vreg74 to %W8: W8 [1840r,1880r:0)  0@1840r

selectOrSplit GPR64common:%vreg69 [1872r,1888r:0)  0@1872r w=2.111724e-05
assigning %vreg69 to %X9: W9 [1872r,1888r:0)  0@1872r

selectOrSplit GPR32:%vreg71 [1876r,1880r:0)  0@1876r w=inf
assigning %vreg71 to %W10: W10 [1876r,1880r:0)  0@1876r

selectOrSplit GPR32:%vreg72 [1880r,1888r:0)  0@1880r w=inf
assigning %vreg72 to %W8: W8 [1880r,1888r:0)  0@1880r

selectOrSplit GPR64common:%vreg66 [1904r,1920r:0)  0@1904r w=inf
assigning %vreg66 to %X8: W8 [1904r,1920r:0)  0@1904r

selectOrSplit GPR32common:%vreg65 [1920r,1936r:0)  0@1920r w=inf
assigning %vreg65 to %W8: W8 [1920r,1936r:0)  0@1920r

selectOrSplit GPR64common:%vreg87 [1984r,2072r:0)  0@1984r w=4.800423e-06
assigning %vreg87 to %X8: W8 [1984r,2072r:0)  0@1984r

selectOrSplit GPR64common:%vreg86 [2032r,2088r:0)  0@2032r w=1.027459e-05
assigning %vreg86 to %X9: W9 [2032r,2088r:0)  0@2032r

selectOrSplit GPR64common:%vreg83 [2064r,2096r:0)  0@2064r w=1.084540e-05
assigning %vreg83 to %X10: W10 [2064r,2096r:0)  0@2064r

selectOrSplit GPR64sp:%vreg88 [2072r,2080r:0)  0@2072r w=inf
assigning %vreg88 to %X8: W8 [2072r,2080r:0)  0@2072r

selectOrSplit GPR64common:%vreg93 [2304r,2320r:0)  0@2304r w=inf
assigning %vreg93 to %X8: W8 [2304r,2320r:0)  0@2304r

selectOrSplit GPR32common:%vreg92 [2320r,2336r:0)  0@2320r w=inf
assigning %vreg92 to %W8: W8 [2320r,2336r:0)  0@2320r

selectOrSplit GPR64common:%vreg97 [2384r,2400r:0)  0@2384r w=inf
assigning %vreg97 to %X8: W8 [2384r,2400r:0)  0@2384r

selectOrSplit GPR64sp:%vreg98 [2400r,2416r:0)  0@2400r w=inf
assigning %vreg98 to %X8: W8 [2400r,2416r:0)  0@2400r

selectOrSplit GPR64common:%vreg107 [2608r,2648r:0)  0@2608r w=1.996539e-05
assigning %vreg107 to %X8: W8 [2608r,2648r:0)  0@2608r

selectOrSplit GPR64common:%vreg104 [2640r,2656r:0)  0@2640r w=2.111724e-05
assigning %vreg104 to %X9: W9 [2640r,2656r:0)  0@2640r

selectOrSplit GPR32:%vreg106 [2648r,2672r:0)  0@2648r w=2.071880e-05
assigning %vreg106 to %W8: W8 [2648r,2672r:0)  0@2648r

selectOrSplit GPR32:%vreg103 [2656r,2672r:0)  0@2656r w=inf
assigning %vreg103 to %W9: W9 [2656r,2672r:0)  0@2656r

selectOrSplit GPR32:%vreg180 [2720r,2736r:0)  0@2720r w=inf
assigning %vreg180 to %W8: W8 [2720r,2736r:0)  0@2720r

selectOrSplit GPR64common:%vreg131 [2832r,2848r:0)  0@2832r w=1.126253e-05
assigning %vreg131 to %X8: W8 [2832r,2848r:0)  0@2832r

selectOrSplit GPR64common:%vreg134 [2840r,2856r:0)  0@2840r w=1.126253e-05
assigning %vreg134 to %X9: W9 [2840r,2856r:0)  0@2840r

selectOrSplit GPR32:%vreg130 [2848r,2900r:0)  0@2848r w=1.036551e-05
assigning %vreg130 to %W8: W8 [2848r,2900r:0)  0@2848r

selectOrSplit GPR32:%vreg133 [2856r,2904r:0)  0@2856r w=1.045806e-05
assigning %vreg133 to %W9: W9 [2856r,2904r:0)  0@2856r

selectOrSplit GPR64common:%vreg123 [2896r,2912r:0)  0@2896r w=1.126253e-05
assigning %vreg123 to %X10: W10 [2896r,2912r:0)  0@2896r

selectOrSplit GPR32:%vreg128 [2900r,2904r:0)  0@2900r w=inf
assigning %vreg128 to %W8: W8 [2900r,2904r:0)  0@2900r

selectOrSplit GPR32:%vreg126 [2904r,2912r:0)  0@2904r w=inf
assigning %vreg126 to %W8: W8 [2904r,2912r:0)  0@2904r

selectOrSplit GPR64common:%vreg120 [2928r,2968r:0)  0@2928r w=1.064821e-05
assigning %vreg120 to %X8: W8 [2928r,2968r:0)  0@2928r

selectOrSplit GPR64common:%vreg117 [2960r,3008r:0)  0@2960r w=1.568710e-05
assigning %vreg117 to %X9: W9 [2960r,3008r:0)  0@2960r

selectOrSplit GPR32:%vreg119 [2968r,2992r:0)  0@2968r w=1.105003e-05
assigning %vreg119 to %W8: W8 [2968r,2992r:0)  0@2968r

selectOrSplit GPR32:%vreg116 [2976r,2992r:0)  0@2976r w=inf
assigning %vreg116 to %W10: W10 [2976r,2992r:0)  0@2976r

selectOrSplit GPR32:%vreg115 [2992r,3008r:0)  0@2992r w=inf
assigning %vreg115 to %W8: W8 [2992r,3008r:0)  0@2992r

selectOrSplit GPR64common:%vreg110 [3024r,3040r:0)  0@3024r w=1.126253e-05
assigning %vreg110 to %X8: W8 [3024r,3040r:0)  0@3024r

selectOrSplit GPR32:%vreg108 [3032r,3040r:0)  0@3032r w=inf
assigning %vreg108 to %W9: W9 [3032r,3040r:0)  0@3032r

selectOrSplit GPR64common:%vreg138 [3168r,3184r:0)  0@3168r w=inf
assigning %vreg138 to %X8: W8 [3168r,3184r:0)  0@3168r

selectOrSplit GPR32common:%vreg137 [3184r,3200r:0)  0@3184r w=inf
assigning %vreg137 to %W8: W8 [3184r,3200r:0)  0@3184r

selectOrSplit GPR32common:%vreg140 [3408r,3424r:0)  0@3408r w=inf
assigning %vreg140 to %W8: W8 [3408r,3424r:0)  0@3408r

selectOrSplit GPR64common:%vreg154 [3472r,3488r:0)  0@3472r w=inf
assigning %vreg154 to %X8: W8 [3472r,3488r:0)  0@3472r

selectOrSplit GPR32common:%vreg153 [3488r,3504r:0)  0@3488r w=inf
assigning %vreg153 to %W8: W8 [3488r,3504r:0)  0@3488r

selectOrSplit GPR64common:%vreg166 [3552r,3640r:0)  0@3552r w=1.020090e-05
assigning %vreg166 to %X8: W8 [3552r,3640r:0)  0@3552r

selectOrSplit GPR64common:%vreg165 [3600r,3656r:0)  0@3600r w=2.183350e-05
assigning %vreg165 to %X9: W9 [3600r,3656r:0)  0@3600r

selectOrSplit GPR64common:%vreg162 [3632r,3664r:0)  0@3632r w=2.304647e-05
assigning %vreg162 to %X10: W10 [3632r,3664r:0)  0@3632r

selectOrSplit GPR64sp:%vreg167 [3640r,3648r:0)  0@3640r w=inf
assigning %vreg167 to %X8: W8 [3640r,3648r:0)  0@3640r

selectOrSplit GPR64common:%vreg176 [3872r,3912r:0)  0@3872r w=4.525490e-05
assigning %vreg176 to %X8: W8 [3872r,3912r:0)  0@3872r

selectOrSplit GPR64common:%vreg173 [3904r,3920r:0)  0@3904r w=4.786575e-05
assigning %vreg173 to %X9: W9 [3904r,3920r:0)  0@3904r

selectOrSplit GPR32:%vreg175 [3912r,3936r:0)  0@3912r w=4.696262e-05
assigning %vreg175 to %W8: W8 [3912r,3936r:0)  0@3912r

selectOrSplit GPR32:%vreg172 [3920r,3936r:0)  0@3920r w=inf
assigning %vreg172 to %W9: W9 [3920r,3936r:0)  0@3920r

selectOrSplit GPR32:%vreg179 [3984r,4000r:0)  0@3984r w=inf
assigning %vreg179 to %W8: W8 [3984r,4000r:0)  0@3984r

selectOrSplit GPR32:%vreg178 [4048r,4064r:0)  0@4048r w=inf
assigning %vreg178 to %W8: W8 [4048r,4064r:0)  0@4048r

selectOrSplit GPR64common:%vreg148 [4112r,4128r:0)  0@4112r w=inf
assigning %vreg148 to %X8: W8 [4112r,4128r:0)  0@4112r

selectOrSplit GPR32common:%vreg147 [4128r,4144r:0)  0@4128r w=inf
assigning %vreg147 to %W8: W8 [4128r,4144r:0)  0@4128r

selectOrSplit GPR32:%vreg150 [4192r,4208r:0)  0@4192r w=inf
assigning %vreg150 to %W8: W8 [4192r,4208r:0)  0@4192r

selectOrSplit GPR64common:%vreg188 [4320r,4336r:0)  0@4320r w=inf
assigning %vreg188 to %X8: W8 [4320r,4336r:0)  0@4320r

********** STACK TRANSFORMATION METADATA **********
********** Function: BZ2_bzDecompress
********** REGISTER MAP **********
[%vreg1 -> %X20] GPR64
[%vreg3 -> %X8] GPR64
[%vreg4 -> %X8] GPR64common
[%vreg6 -> %X0] GPR64sp
[%vreg7 -> %X19] GPR64
[%vreg10 -> %X8] GPR64
[%vreg13 -> %X8] GPR64
[%vreg16 -> %X8] GPR64common
[%vreg19 -> %X9] GPR64
[%vreg21 -> %X8] GPR64
[%vreg22 -> %X8] GPR64common
[%vreg25 -> %W8] GPR32common
[%vreg26 -> %X8] GPR64common
[%vreg29 -> %W8] GPR32common
[%vreg30 -> %X8] GPR64common
[%vreg32 -> %W8] GPR32
[%vreg34 -> %W8] GPR32
[%vreg35 -> %X8] GPR64common
[%vreg36 -> %W0] GPR32
[%vreg39 -> %X0] GPR64
[%vreg40 -> %W0] GPR32
[%vreg43 -> %X0] GPR64
[%vreg45 -> %W8] GPR32
[%vreg46 -> %W8] GPR32
[%vreg50 -> %W8] GPR32common
[%vreg52 -> %X10] GPR64
[%vreg53 -> %X8] GPR64common
[%vreg54 -> %W8] GPR32common
[%vreg55 -> %X8] GPR64
[%vreg57 -> %W9] GPR32
[%vreg58 -> %X9] GPR64common
[%vreg61 -> %W8] GPR32
[%vreg62 -> %X8] GPR64common
[%vreg65 -> %W8] GPR32common
[%vreg66 -> %X8] GPR64common
[%vreg69 -> %X9] GPR64common
[%vreg71 -> %W10] GPR32
[%vreg72 -> %W8] GPR32
[%vreg74 -> %W8] GPR32
[%vreg75 -> %X8] GPR64common
[%vreg79 -> %X1] GPR64
[%vreg80 -> %W0] GPR32all
[%vreg82 -> %W3] GPR32
[%vreg83 -> %X10] GPR64common
[%vreg85 -> %W2] GPR32
[%vreg86 -> %X9] GPR64common
[%vreg87 -> %X8] GPR64common
[%vreg88 -> %X8] GPR64sp
[%vreg89 -> %X0] GPR64
[%vreg92 -> %W8] GPR32common
[%vreg93 -> %X8] GPR64common
[%vreg95 -> %X1] GPR64
[%vreg96 -> %W0] GPR32all
[%vreg97 -> %X8] GPR64common
[%vreg98 -> %X8] GPR64sp
[%vreg99 -> %X0] GPR64
[%vreg103 -> %W9] GPR32
[%vreg104 -> %X9] GPR64common
[%vreg106 -> %W8] GPR32
[%vreg107 -> %X8] GPR64common
[%vreg108 -> %W9] GPR32
[%vreg110 -> %X8] GPR64common
[%vreg115 -> %W8] GPR32
[%vreg116 -> %W10] GPR32
[%vreg117 -> %X9] GPR64common
[%vreg119 -> %W8] GPR32
[%vreg120 -> %X8] GPR64common
[%vreg123 -> %X10] GPR64common
[%vreg126 -> %W8] GPR32
[%vreg128 -> %W8] GPR32
[%vreg130 -> %W8] GPR32
[%vreg131 -> %X8] GPR64common
[%vreg133 -> %W9] GPR32
[%vreg134 -> %X9] GPR64common
[%vreg137 -> %W8] GPR32common
[%vreg138 -> %X8] GPR64common
[%vreg140 -> %W8] GPR32common
[%vreg143 -> %W0] GPR32
[%vreg144 -> %X0] GPR64
[%vreg147 -> %W8] GPR32common
[%vreg148 -> %X8] GPR64common
[%vreg150 -> %W8] GPR32
[%vreg153 -> %W8] GPR32common
[%vreg154 -> %X8] GPR64common
[%vreg158 -> %X1] GPR64
[%vreg159 -> %W0] GPR32all
[%vreg161 -> %W3] GPR32
[%vreg162 -> %X10] GPR64common
[%vreg164 -> %W2] GPR32
[%vreg165 -> %X9] GPR64common
[%vreg166 -> %X8] GPR64common
[%vreg167 -> %X8] GPR64sp
[%vreg168 -> %X0] GPR64
[%vreg172 -> %W9] GPR32
[%vreg173 -> %X9] GPR64common
[%vreg175 -> %W8] GPR32
[%vreg176 -> %X8] GPR64common
[%vreg178 -> %W8] GPR32
[%vreg179 -> %W8] GPR32
[%vreg180 -> %W8] GPR32
[%vreg181 -> %W8] GPR32
[%vreg182 -> %W8] GPR32
[%vreg183 -> %W8] GPR32
[%vreg184 -> %W8] GPR32
[%vreg185 -> %W8] GPR32
[%vreg187 -> %W0] GPR32
[%vreg188 -> %X8] GPR64common
[%vreg190 -> %X0] GPR64sp


Stackmap 0:
  STACKMAP 0, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, %vreg1, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3] LD8[FixedStack1] GPR64:%vreg1

i8* %corrupt: in stack slot 2 (size: 1)
i32* %r: in stack slot 4 (size: 4)
i32* %retval: in stack slot 0 (size: 4)
%struct.DState** %s: in stack slot 3 (size: 8)
%struct.bz_stream* %strm: in register %X20 (vreg 1)
%struct.bz_stream** %strm.addr: in stack slot 1 (size: 8)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]

i8* %corrupt: in stack slot 2 (size: 1)
i32* %r: in stack slot 4 (size: 4)
i32* %retval: in stack slot 0 (size: 4)
%struct.DState** %s: in stack slot 3 (size: 8)

Duplicate operand locations:


Stackmap 2:
  STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]

i8* %corrupt: in stack slot 2 (size: 1)
i32* %r: in stack slot 4 (size: 4)
i32* %retval: in stack slot 0 (size: 4)
%struct.DState** %s: in stack slot 3 (size: 8)

Duplicate operand locations:


Stackmap 3:
  STACKMAP 3, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]

i8* %corrupt: in stack slot 2 (size: 1)
i32* %r: in stack slot 4 (size: 4)
i32* %retval: in stack slot 0 (size: 4)
%struct.DState** %s: in stack slot 3 (size: 8)

Duplicate operand locations:


Stackmap 4:
  STACKMAP 4, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]

i8* %corrupt: in stack slot 2 (size: 1)
i32* %r: in stack slot 4 (size: 4)
i32* %retval: in stack slot 0 (size: 4)
%struct.DState** %s: in stack slot 3 (size: 8)

Duplicate operand locations:


Stackmap 5:
  STACKMAP 5, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]

i8* %corrupt: in stack slot 2 (size: 1)
i32* %r: in stack slot 4 (size: 4)
i32* %retval: in stack slot 0 (size: 4)
%struct.DState** %s: in stack slot 3 (size: 8)

Duplicate operand locations:


Stackmap 6:
  STACKMAP 6, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]

i32* %r: in stack slot 4 (size: 4)
i32* %retval: in stack slot 0 (size: 4)
%struct.DState** %s: in stack slot 3 (size: 8)

Duplicate operand locations:


Stackmap 7:
  STACKMAP 7, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)

i32* %retval: in stack slot 0 (size: 4)

Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, %vreg1, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3] LD8[FixedStack1] GPR64:%vreg1
  -> Call instruction SlotIndex 176B, searching vregs 0 -> 192 and stack slots 0 -> 5
    + vreg7 is live in register but not in stackmap
      Defining instruction: %vreg7<def> = COPY %LR; GPR64:%vreg7
      Value: generated value, 1 instruction(s)

  STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
  -> Call instruction SlotIndex 1104B, searching vregs 0 -> 192 and stack slots 0 -> 5
    + vreg7 is live in register but not in stackmap
      Defining instruction: %vreg7<def> = COPY %LR; GPR64:%vreg7
      Value: generated value, 1 instruction(s)

  STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
  -> Call instruction SlotIndex 1312B, searching vregs 0 -> 192 and stack slots 0 -> 5
    + vreg7 is live in register but not in stackmap
      Defining instruction: %vreg7<def> = COPY %LR; GPR64:%vreg7
      Value: generated value, 1 instruction(s)

  STACKMAP 3, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
  -> Call instruction SlotIndex 2192B, searching vregs 0 -> 192 and stack slots 0 -> 5
    + vreg7 is live in register but not in stackmap
      Defining instruction: %vreg7<def> = COPY %LR; GPR64:%vreg7
      Value: generated value, 1 instruction(s)

  STACKMAP 4, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
  -> Call instruction SlotIndex 2496B, searching vregs 0 -> 192 and stack slots 0 -> 5
    + vreg7 is live in register but not in stackmap
      Defining instruction: %vreg7<def> = COPY %LR; GPR64:%vreg7
      Value: generated value, 1 instruction(s)

  STACKMAP 5, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
  -> Call instruction SlotIndex 3296B, searching vregs 0 -> 192 and stack slots 0 -> 5
    + vreg7 is live in register but not in stackmap
      Defining instruction: %vreg7<def> = COPY %LR; GPR64:%vreg7
      Value: generated value, 1 instruction(s)

  STACKMAP 6, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
  -> Call instruction SlotIndex 3760B, searching vregs 0 -> 192 and stack slots 0 -> 5
    + vreg7 is live in register but not in stackmap
      Defining instruction: %vreg7<def> = COPY %LR; GPR64:%vreg7
      Value: generated value, 1 instruction(s)

  STACKMAP 7, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
  -> Call instruction SlotIndex 4432B, searching vregs 0 -> 192 and stack slots 0 -> 5

********** REWRITE VIRTUAL REGISTERS **********
********** Function: BZ2_bzDecompress
********** REGISTER MAP **********
[%vreg1 -> %X20] GPR64
[%vreg3 -> %X8] GPR64
[%vreg4 -> %X8] GPR64common
[%vreg6 -> %X0] GPR64sp
[%vreg7 -> %X19] GPR64
[%vreg10 -> %X8] GPR64
[%vreg13 -> %X8] GPR64
[%vreg16 -> %X8] GPR64common
[%vreg19 -> %X9] GPR64
[%vreg21 -> %X8] GPR64
[%vreg22 -> %X8] GPR64common
[%vreg25 -> %W8] GPR32common
[%vreg26 -> %X8] GPR64common
[%vreg29 -> %W8] GPR32common
[%vreg30 -> %X8] GPR64common
[%vreg32 -> %W8] GPR32
[%vreg34 -> %W8] GPR32
[%vreg35 -> %X8] GPR64common
[%vreg36 -> %W0] GPR32
[%vreg39 -> %X0] GPR64
[%vreg40 -> %W0] GPR32
[%vreg43 -> %X0] GPR64
[%vreg45 -> %W8] GPR32
[%vreg46 -> %W8] GPR32
[%vreg50 -> %W8] GPR32common
[%vreg52 -> %X10] GPR64
[%vreg53 -> %X8] GPR64common
[%vreg54 -> %W8] GPR32common
[%vreg55 -> %X8] GPR64
[%vreg57 -> %W9] GPR32
[%vreg58 -> %X9] GPR64common
[%vreg61 -> %W8] GPR32
[%vreg62 -> %X8] GPR64common
[%vreg65 -> %W8] GPR32common
[%vreg66 -> %X8] GPR64common
[%vreg69 -> %X9] GPR64common
[%vreg71 -> %W10] GPR32
[%vreg72 -> %W8] GPR32
[%vreg74 -> %W8] GPR32
[%vreg75 -> %X8] GPR64common
[%vreg79 -> %X1] GPR64
[%vreg80 -> %W0] GPR32all
[%vreg82 -> %W3] GPR32
[%vreg83 -> %X10] GPR64common
[%vreg85 -> %W2] GPR32
[%vreg86 -> %X9] GPR64common
[%vreg87 -> %X8] GPR64common
[%vreg88 -> %X8] GPR64sp
[%vreg89 -> %X0] GPR64
[%vreg92 -> %W8] GPR32common
[%vreg93 -> %X8] GPR64common
[%vreg95 -> %X1] GPR64
[%vreg96 -> %W0] GPR32all
[%vreg97 -> %X8] GPR64common
[%vreg98 -> %X8] GPR64sp
[%vreg99 -> %X0] GPR64
[%vreg103 -> %W9] GPR32
[%vreg104 -> %X9] GPR64common
[%vreg106 -> %W8] GPR32
[%vreg107 -> %X8] GPR64common
[%vreg108 -> %W9] GPR32
[%vreg110 -> %X8] GPR64common
[%vreg115 -> %W8] GPR32
[%vreg116 -> %W10] GPR32
[%vreg117 -> %X9] GPR64common
[%vreg119 -> %W8] GPR32
[%vreg120 -> %X8] GPR64common
[%vreg123 -> %X10] GPR64common
[%vreg126 -> %W8] GPR32
[%vreg128 -> %W8] GPR32
[%vreg130 -> %W8] GPR32
[%vreg131 -> %X8] GPR64common
[%vreg133 -> %W9] GPR32
[%vreg134 -> %X9] GPR64common
[%vreg137 -> %W8] GPR32common
[%vreg138 -> %X8] GPR64common
[%vreg140 -> %W8] GPR32common
[%vreg143 -> %W0] GPR32
[%vreg144 -> %X0] GPR64
[%vreg147 -> %W8] GPR32common
[%vreg148 -> %X8] GPR64common
[%vreg150 -> %W8] GPR32
[%vreg153 -> %W8] GPR32common
[%vreg154 -> %X8] GPR64common
[%vreg158 -> %X1] GPR64
[%vreg159 -> %W0] GPR32all
[%vreg161 -> %W3] GPR32
[%vreg162 -> %X10] GPR64common
[%vreg164 -> %W2] GPR32
[%vreg165 -> %X9] GPR64common
[%vreg166 -> %X8] GPR64common
[%vreg167 -> %X8] GPR64sp
[%vreg168 -> %X0] GPR64
[%vreg172 -> %W9] GPR32
[%vreg173 -> %X9] GPR64common
[%vreg175 -> %W8] GPR32
[%vreg176 -> %X8] GPR64common
[%vreg178 -> %W8] GPR32
[%vreg179 -> %W8] GPR32
[%vreg180 -> %W8] GPR32
[%vreg181 -> %W8] GPR32
[%vreg182 -> %W8] GPR32
[%vreg183 -> %W8] GPR32
[%vreg184 -> %W8] GPR32
[%vreg185 -> %W8] GPR32
[%vreg187 -> %W0] GPR32
[%vreg188 -> %X8] GPR64common
[%vreg190 -> %X0] GPR64sp

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %LR %X0
16B		%vreg7<def> = COPY %LR; GPR64:%vreg7
32B		%vreg1<def> = COPY %X0; GPR64:%vreg1
64B		%vreg4<def> = ADRP <ga:@BZ2_bzDecompress>[TF=1]; GPR64common:%vreg4
80B		%vreg6<def> = ADDXri %vreg4<kill>, <ga:@BZ2_bzDecompress>[TF=34], 0; GPR64sp:%vreg6 GPR64common:%vreg4
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		%X0<def> = COPY %vreg6<kill>; GPR64sp:%vreg6
160B		%X1<def> = COPY %vreg7; GPR64:%vreg7
176B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
224B		STACKMAP 0, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, %vreg1, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3] LD8[FixedStack1] GPR64:%vreg1
240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
256B		STRXui %vreg1<kill>, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg1
272B		%vreg3<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg3
288B		CBNZX %vreg3<kill>, <BB#2>; GPR64:%vreg3
	    Successors according to CFG: BB#2 BB#1
> %X19<def> = COPY %LR
> %X20<def> = COPY %X0
> %X8<def> = ADRP <ga:@BZ2_bzDecompress>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@BZ2_bzDecompress>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19
> BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 0, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, %X20, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3] LD8[FixedStack1]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRXui %X20<kill>, <fi#1>, 0; mem:ST8[FixedStack1]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> CBNZX %X8<kill>, <BB#2>
304B	BB#1: derived from LLVM BB %if.then
	    Live Ins: %X19
	    Predecessors according to CFG: BB#0
320B		%vreg185<def> = MOVi32imm 4294967294; GPR32:%vreg185
336B		STRWui %vreg185<kill>, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg185
352B		B <BB#37>
	    Successors according to CFG: BB#37
> %W8<def> = MOVi32imm 4294967294
> STRWui %W8<kill>, <fi#0>, 0; mem:ST4[FixedStack0]
> B <BB#37>
368B	BB#2: derived from LLVM BB %if.end
	    Live Ins: %X19
	    Predecessors according to CFG: BB#0
384B		%vreg16<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg16
400B		%vreg13<def> = LDRXui %vreg16<kill>, 6; mem:LD8[%state] GPR64:%vreg13 GPR64common:%vreg16
432B		STRXui %vreg13<kill>, <fi#3>, 0; mem:ST8[FixedStack3] GPR64:%vreg13
448B		%vreg10<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg10
464B		CBNZX %vreg10<kill>, <BB#4>; GPR64:%vreg10
	    Successors according to CFG: BB#4 BB#3
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X8<def> = LDRXui %X8<kill>, 6; mem:LD8[%state]
> STRXui %X8<kill>, <fi#3>, 0; mem:ST8[FixedStack3]
> %X8<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> CBNZX %X8<kill>, <BB#4>
480B	BB#3: derived from LLVM BB %if.then.2
	    Live Ins: %X19
	    Predecessors according to CFG: BB#2
496B		%vreg184<def> = MOVi32imm 4294967294; GPR32:%vreg184
512B		STRWui %vreg184<kill>, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg184
528B		B <BB#37>
	    Successors according to CFG: BB#37
> %W8<def> = MOVi32imm 4294967294
> STRWui %W8<kill>, <fi#0>, 0; mem:ST4[FixedStack0]
> B <BB#37>
544B	BB#4: derived from LLVM BB %if.end.3
	    Live Ins: %X19
	    Predecessors according to CFG: BB#2
560B		%vreg22<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg22
576B		%vreg21<def> = LDRXui %vreg22<kill>, 0; mem:LD8[%strm4] GPR64:%vreg21 GPR64common:%vreg22
592B		%vreg19<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg19
608B		%XZR<def> = SUBSXrr %vreg21<kill>, %vreg19<kill>, %NZCV<imp-def>; GPR64:%vreg21,%vreg19
624B		Bcc 0, <BB#6>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#6 BB#5
> %X8<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> %X8<def> = LDRXui %X8<kill>, 0; mem:LD8[%strm4]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %XZR<def> = SUBSXrr %X8<kill>, %X9<kill>, %NZCV<imp-def>
> Bcc 0, <BB#6>, %NZCV<imp-use,kill>
640B	BB#5: derived from LLVM BB %if.then.6
	    Live Ins: %X19
	    Predecessors according to CFG: BB#4
656B		%vreg183<def> = MOVi32imm 4294967294; GPR32:%vreg183
672B		STRWui %vreg183<kill>, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg183
688B		B <BB#37>
	    Successors according to CFG: BB#37
> %W8<def> = MOVi32imm 4294967294
> STRWui %W8<kill>, <fi#0>, 0; mem:ST4[FixedStack0]
> B <BB#37>
704B	BB#6: derived from LLVM BB %if.end.7
	    Live Ins: %X19
	    Predecessors according to CFG: BB#4
720B		B <BB#7>
	    Successors according to CFG: BB#7
> B <BB#7>
736B	BB#7: derived from LLVM BB %while.body
	    Live Ins: %X19
	    Predecessors according to CFG: BB#6 BB#36
752B		%vreg26<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg26
768B		%vreg25<def> = LDRWui %vreg26<kill>, 2; mem:LD4[%state8] GPR32common:%vreg25 GPR64common:%vreg26
784B		%WZR<def> = SUBSWri %vreg25<kill>, 1, 0, %NZCV<imp-def>; GPR32common:%vreg25
800B		Bcc 1, <BB#9>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#9 BB#8
> %X8<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> %W8<def> = LDRWui %X8<kill>, 2; mem:LD4[%state8]
> %WZR<def> = SUBSWri %W8<kill>, 1, 0, %NZCV<imp-def>
> Bcc 1, <BB#9>, %NZCV<imp-use,kill>
816B	BB#8: derived from LLVM BB %if.then.10
	    Live Ins: %X19
	    Predecessors according to CFG: BB#7
832B		%vreg182<def> = MOVi32imm 4294967295; GPR32:%vreg182
848B		STRWui %vreg182<kill>, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg182
864B		B <BB#37>
	    Successors according to CFG: BB#37
> %W8<def> = MOVi32imm 4294967295
> STRWui %W8<kill>, <fi#0>, 0; mem:ST4[FixedStack0]
> B <BB#37>
880B	BB#9: derived from LLVM BB %if.end.11
	    Live Ins: %X19
	    Predecessors according to CFG: BB#7
896B		%vreg30<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg30
912B		%vreg29<def> = LDRWui %vreg30<kill>, 2; mem:LD4[%state12] GPR32common:%vreg29 GPR64common:%vreg30
928B		%WZR<def> = SUBSWri %vreg29<kill>, 2, 0, %NZCV<imp-def>; GPR32common:%vreg29
944B		Bcc 1, <BB#26>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#26 BB#10
> %X8<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> %W8<def> = LDRWui %X8<kill>, 2; mem:LD4[%state12]
> %WZR<def> = SUBSWri %W8<kill>, 2, 0, %NZCV<imp-def>
> Bcc 1, <BB#26>, %NZCV<imp-use,kill>
960B	BB#10: derived from LLVM BB %if.then.14
	    Live Ins: %X19
	    Predecessors according to CFG: BB#9
976B		%vreg35<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg35
992B		%vreg34<def> = LDRBBui %vreg35<kill>, 44; mem:LD1[%smallDecompress] GPR32:%vreg34 GPR64common:%vreg35
1008B		%vreg32<def> = UBFMWri %vreg34<kill>, 0, 7; GPR32:%vreg32,%vreg34
1024B		CBZW %vreg32<kill>, <BB#12>; GPR32:%vreg32
	    Successors according to CFG: BB#12 BB#11
> %X8<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> %W8<def> = LDRBBui %X8<kill>, 44; mem:LD1[%smallDecompress]
> %W8<def> = UBFMWri %W8<kill>, 0, 7
> CBZW %W8<kill>, <BB#12>
1040B	BB#11: derived from LLVM BB %if.then.15
	    Live Ins: %X19
	    Predecessors according to CFG: BB#10
1056B		%vreg43<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg43
1072B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1088B		%X0<def> = COPY %vreg43<kill>; GPR64:%vreg43
1104B		BL <ga:@unRLE_obuf_to_output_SMALL>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>
1120B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1136B		%vreg40<def> = COPY %W0; GPR32:%vreg40
1168B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1184B		STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
1200B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1216B		STRBBui %vreg40<kill>, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg40
1232B		B <BB#13>
	    Successors according to CFG: BB#13
> %X0<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BL <ga:@unRLE_obuf_to_output_SMALL>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = COPY %W0
Deleting identity copy.
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRBBui %W0<kill>, <fi#2>, 0; mem:ST1[FixedStack2]
> B <BB#13>
1248B	BB#12: derived from LLVM BB %if.else
	    Live Ins: %X19
	    Predecessors according to CFG: BB#10
1264B		%vreg39<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg39
1280B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1296B		%X0<def> = COPY %vreg39<kill>; GPR64:%vreg39
1312B		BL <ga:@unRLE_obuf_to_output_FAST>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>
1328B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1344B		%vreg36<def> = COPY %W0; GPR32:%vreg36
1376B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1392B		STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
1408B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1424B		STRBBui %vreg36<kill>, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg36
	    Successors according to CFG: BB#13
> %X0<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BL <ga:@unRLE_obuf_to_output_FAST>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = COPY %W0
Deleting identity copy.
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRBBui %W0<kill>, <fi#2>, 0; mem:ST1[FixedStack2]
1440B	BB#13: derived from LLVM BB %if.end.17
	    Live Ins: %X19
	    Predecessors according to CFG: BB#12 BB#11
1456B		%vreg46<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg46
1472B		%vreg45<def> = UBFMWri %vreg46<kill>, 0, 7; GPR32:%vreg45,%vreg46
1488B		CBZW %vreg45<kill>, <BB#15>; GPR32:%vreg45
	    Successors according to CFG: BB#15 BB#14
> %W8<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2]
> %W8<def> = UBFMWri %W8<kill>, 0, 7
> CBZW %W8<kill>, <BB#15>
1504B	BB#14: derived from LLVM BB %if.then.19
	    Live Ins: %X19
	    Predecessors according to CFG: BB#13
1520B		%vreg181<def> = MOVi32imm 4294967292; GPR32:%vreg181
1536B		STRWui %vreg181<kill>, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg181
1552B		B <BB#37>
	    Successors according to CFG: BB#37
> %W8<def> = MOVi32imm 4294967292
> STRWui %W8<kill>, <fi#0>, 0; mem:ST4[FixedStack0]
> B <BB#37>
1568B	BB#15: derived from LLVM BB %if.end.20
	    Live Ins: %X19
	    Predecessors according to CFG: BB#13
1616B		%vreg55<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg55
1624B		%vreg58<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg58
1632B		%vreg52<def> = MOVi64imm 64080; GPR64:%vreg52
1648B		%vreg53<def> = ADDXrr %vreg55<kill>, %vreg52<kill>; GPR64common:%vreg53 GPR64:%vreg55,%vreg52
1664B		%vreg54<def> = LDRWui %vreg53<kill>, 0; mem:LD4[%save_nblock] GPR32common:%vreg54 GPR64common:%vreg53
1672B		%vreg57<def> = LDRWui %vreg58<kill>, 273; mem:LD4[%nblock_used] GPR32:%vreg57 GPR64common:%vreg58
1680B		%vreg50<def> = ADDWri %vreg54<kill>, 1, 0; GPR32common:%vreg50,%vreg54
1696B		%WZR<def> = SUBSWrr %vreg57<kill>, %vreg50<kill>, %NZCV<imp-def>; GPR32:%vreg57 GPR32common:%vreg50
1712B		Bcc 1, <BB#24>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#24 BB#16
> %X8<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> %X9<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> %X10<def> = MOVi64imm 64080
> %X8<def> = ADDXrr %X8<kill>, %X10<kill>
> %W8<def> = LDRWui %X8<kill>, 0; mem:LD4[%save_nblock]
> %W9<def> = LDRWui %X9<kill>, 273; mem:LD4[%nblock_used]
> %W8<def> = ADDWri %W8<kill>, 1, 0
> %WZR<def> = SUBSWrr %W9<kill>, %W8<kill>, %NZCV<imp-def>
> Bcc 1, <BB#24>, %NZCV<imp-use,kill>
1728B	BB#16: derived from LLVM BB %land.lhs.true
	    Live Ins: %X19
	    Predecessors according to CFG: BB#15
1744B		%vreg62<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg62
1760B		%vreg61<def> = LDRWui %vreg62<kill>, 4; mem:LD4[%state_out_len] GPR32:%vreg61 GPR64common:%vreg62
1776B		CBNZW %vreg61<kill>, <BB#24>; GPR32:%vreg61
	    Successors according to CFG: BB#24 BB#17
> %X8<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> %W8<def> = LDRWui %X8<kill>, 4; mem:LD4[%state_out_len]
> CBNZW %W8<kill>, <BB#24>
1792B	BB#17: derived from LLVM BB %if.then.23
	    Live Ins: %X19
	    Predecessors according to CFG: BB#16
1824B		%vreg75<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg75
1840B		%vreg74<def> = LDRWui %vreg75<kill>, 796; mem:LD4[%calculatedBlockCRC] GPR32:%vreg74 GPR64common:%vreg75
1872B		%vreg69<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg69
1876B		%vreg71<def> = MOVi32imm 4294967295; GPR32:%vreg71
1880B		%vreg72<def> = EORWrr %vreg74<kill>, %vreg71<kill>; GPR32:%vreg72,%vreg74,%vreg71
1888B		STRWui %vreg72<kill>, %vreg69<kill>, 796; mem:ST4[%calculatedBlockCRC24] GPR32:%vreg72 GPR64common:%vreg69
1904B		%vreg66<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg66
1920B		%vreg65<def> = LDRWui %vreg66<kill>, 13; mem:LD4[%verbosity] GPR32common:%vreg65 GPR64common:%vreg66
1936B		%WZR<def> = SUBSWri %vreg65<kill>, 3, 0, %NZCV<imp-def>; GPR32common:%vreg65
1952B		Bcc 11, <BB#19>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#19 BB#18
> %X8<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> %W8<def> = LDRWui %X8<kill>, 796; mem:LD4[%calculatedBlockCRC]
> %X9<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> %W10<def> = MOVi32imm 4294967295
> %W8<def> = EORWrr %W8<kill>, %W10<kill>
> STRWui %W8<kill>, %X9<kill>, 796; mem:ST4[%calculatedBlockCRC24]
> %X8<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> %W8<def> = LDRWui %X8<kill>, 13; mem:LD4[%verbosity]
> %WZR<def> = SUBSWri %W8<kill>, 3, 0, %NZCV<imp-def>
> Bcc 11, <BB#19>, %NZCV<imp-use,kill>
1968B	BB#18: derived from LLVM BB %if.then.26
	    Live Ins: %X19
	    Predecessors according to CFG: BB#17
1984B		%vreg87<def> = ADRP <ga:@stderr>[TF=1]; GPR64common:%vreg87
2032B		%vreg86<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg86
2064B		%vreg83<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg83
2072B		%vreg88<def> = ADDXri %vreg87<kill>, <ga:@stderr>[TF=34], 0; GPR64sp:%vreg88 GPR64common:%vreg87
2080B		%vreg89<def> = LDRXui %vreg88<kill>, 0; mem:LD8[@stderr] GPR64:%vreg89 GPR64sp:%vreg88
2088B		%vreg85<def> = LDRWui %vreg86<kill>, 794; mem:LD4[%storedBlockCRC] GPR32:%vreg85 GPR64common:%vreg86
2096B		%vreg82<def> = LDRWui %vreg83<kill>, 796; mem:LD4[%calculatedBlockCRC27] GPR32:%vreg82 GPR64common:%vreg83
2104B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2112B		%vreg79<def> = MOVaddr <ga:@bzlib__str_2___0x_08x__>[TF=1], <ga:@bzlib__str_2___0x_08x__>[TF=34]; GPR64:%vreg79
2128B		%X0<def> = COPY %vreg89<kill>; GPR64:%vreg89
2144B		%X1<def> = COPY %vreg79<kill>; GPR64:%vreg79
2160B		%W2<def> = COPY %vreg85<kill>; GPR32:%vreg85
2176B		%W3<def> = COPY %vreg82<kill>; GPR32:%vreg82
2192B		BL <ga:@fprintf>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %W2<imp-use>, %W3<imp-use>, %SP<imp-def>, %W0<imp-def>
2208B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2224B		%vreg80<def,dead> = COPY %W0; GPR32all:%vreg80
2240B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2256B		STACKMAP 3, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
2272B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#19
> %X8<def> = ADRP <ga:@stderr>[TF=1]
> %X9<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> %X10<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> %X8<def> = ADDXri %X8<kill>, <ga:@stderr>[TF=34], 0
> %X0<def> = LDRXui %X8<kill>, 0; mem:LD8[@stderr]
> %W2<def> = LDRWui %X9<kill>, 794; mem:LD4[%storedBlockCRC]
> %W3<def> = LDRWui %X10<kill>, 796; mem:LD4[%calculatedBlockCRC27]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X1<def> = MOVaddr <ga:@bzlib__str_2___0x_08x__>[TF=1], <ga:@bzlib__str_2___0x_08x__>[TF=34]
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X1<kill>
Deleting identity copy.
> %W2<def> = COPY %W2<kill>
Deleting identity copy.
> %W3<def> = COPY %W3<kill>
Deleting identity copy.
> BL <ga:@fprintf>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %W2<imp-use>, %W3<imp-use>, %SP<imp-def>, %W0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def,dead> = COPY %W0
Deleting identity copy.
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 3, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2288B	BB#19: derived from LLVM BB %if.end.29
	    Live Ins: %X19
	    Predecessors according to CFG: BB#17 BB#18
2304B		%vreg93<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg93
2320B		%vreg92<def> = LDRWui %vreg93<kill>, 13; mem:LD4[%verbosity30] GPR32common:%vreg92 GPR64common:%vreg93
2336B		%WZR<def> = SUBSWri %vreg92<kill>, 2, 0, %NZCV<imp-def>; GPR32common:%vreg92
2352B		Bcc 11, <BB#21>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#21 BB#20
> %X8<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> %W8<def> = LDRWui %X8<kill>, 13; mem:LD4[%verbosity30]
> %WZR<def> = SUBSWri %W8<kill>, 2, 0, %NZCV<imp-def>
> Bcc 11, <BB#21>, %NZCV<imp-use,kill>
2368B	BB#20: derived from LLVM BB %if.then.32
	    Live Ins: %X19
	    Predecessors according to CFG: BB#19
2384B		%vreg97<def> = ADRP <ga:@stderr>[TF=1]; GPR64common:%vreg97
2400B		%vreg98<def> = ADDXri %vreg97<kill>, <ga:@stderr>[TF=34], 0; GPR64sp:%vreg98 GPR64common:%vreg97
2416B		%vreg99<def> = LDRXui %vreg98<kill>, 0; mem:LD8[@stderr] GPR64:%vreg99 GPR64sp:%vreg98
2432B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2448B		%vreg95<def> = MOVaddr <ga:@bzlib__str_3___>[TF=1], <ga:@bzlib__str_3___>[TF=34]; GPR64:%vreg95
2464B		%X0<def> = COPY %vreg99<kill>; GPR64:%vreg99
2480B		%X1<def> = COPY %vreg95<kill>; GPR64:%vreg95
2496B		BL <ga:@fprintf>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %SP<imp-def>, %W0<imp-def>
2512B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2528B		%vreg96<def,dead> = COPY %W0; GPR32all:%vreg96
2544B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2560B		STACKMAP 4, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
2576B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#21
> %X8<def> = ADRP <ga:@stderr>[TF=1]
> %X8<def> = ADDXri %X8<kill>, <ga:@stderr>[TF=34], 0
> %X0<def> = LDRXui %X8<kill>, 0; mem:LD8[@stderr]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X1<def> = MOVaddr <ga:@bzlib__str_3___>[TF=1], <ga:@bzlib__str_3___>[TF=34]
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X1<kill>
Deleting identity copy.
> BL <ga:@fprintf>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %SP<imp-def>, %W0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def,dead> = COPY %W0
Deleting identity copy.
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 4, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2592B	BB#21: derived from LLVM BB %if.end.34
	    Live Ins: %X19
	    Predecessors according to CFG: BB#19 BB#20
2608B		%vreg107<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg107
2640B		%vreg104<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg104
2648B		%vreg106<def> = LDRWui %vreg107<kill>, 796; mem:LD4[%calculatedBlockCRC35] GPR32:%vreg106 GPR64common:%vreg107
2656B		%vreg103<def> = LDRWui %vreg104<kill>, 794; mem:LD4[%storedBlockCRC36] GPR32:%vreg103 GPR64common:%vreg104
2672B		%WZR<def> = SUBSWrr %vreg106<kill>, %vreg103<kill>, %NZCV<imp-def>; GPR32:%vreg106,%vreg103
2688B		Bcc 0, <BB#23>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#23 BB#22
> %X8<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> %X9<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> %W8<def> = LDRWui %X8<kill>, 796; mem:LD4[%calculatedBlockCRC35]
> %W9<def> = LDRWui %X9<kill>, 794; mem:LD4[%storedBlockCRC36]
> %WZR<def> = SUBSWrr %W8<kill>, %W9<kill>, %NZCV<imp-def>
> Bcc 0, <BB#23>, %NZCV<imp-use,kill>
2704B	BB#22: derived from LLVM BB %if.then.38
	    Live Ins: %X19
	    Predecessors according to CFG: BB#21
2720B		%vreg180<def> = MOVi32imm 4294967292; GPR32:%vreg180
2736B		STRWui %vreg180<kill>, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg180
2752B		B <BB#37>
	    Successors according to CFG: BB#37
> %W8<def> = MOVi32imm 4294967292
> STRWui %W8<kill>, <fi#0>, 0; mem:ST4[FixedStack0]
> B <BB#37>
2768B	BB#23: derived from LLVM BB %if.end.39
	    Live Ins: %X19
	    Predecessors according to CFG: BB#21
2832B		%vreg131<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg131
2840B		%vreg134<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg134
2848B		%vreg130<def> = LDRWui %vreg131<kill>, 797; mem:LD4[%calculatedCombinedCRC40] GPR32:%vreg130 GPR64common:%vreg131
2856B		%vreg133<def> = LDRWui %vreg134<kill>, 797; mem:LD4[%calculatedCombinedCRC] GPR32:%vreg133 GPR64common:%vreg134
2896B		%vreg123<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg123
2900B		%vreg128<def> = UBFMWri %vreg130<kill>, 31, 31; GPR32:%vreg128,%vreg130
2904B		%vreg126<def> = ORRWrs %vreg128<kill>, %vreg133<kill>, 1; GPR32:%vreg126,%vreg128,%vreg133
2912B		STRWui %vreg126<kill>, %vreg123<kill>, 797; mem:ST4[%calculatedCombinedCRC41] GPR32:%vreg126 GPR64common:%vreg123
2928B		%vreg120<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg120
2960B		%vreg117<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg117
2968B		%vreg119<def> = LDRWui %vreg120<kill>, 796; mem:LD4[%calculatedBlockCRC42] GPR32:%vreg119 GPR64common:%vreg120
2976B		%vreg116<def> = LDRWui %vreg117, 797; mem:LD4[%calculatedCombinedCRC43] GPR32:%vreg116 GPR64common:%vreg117
2992B		%vreg115<def> = EORWrr %vreg116<kill>, %vreg119<kill>; GPR32:%vreg115,%vreg116,%vreg119
3008B		STRWui %vreg115<kill>, %vreg117<kill>, 797; mem:ST4[%calculatedCombinedCRC43] GPR32:%vreg115 GPR64common:%vreg117
3024B		%vreg110<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg110
3032B		%vreg108<def> = MOVi32imm 14; GPR32:%vreg108
3040B		STRWui %vreg108<kill>, %vreg110<kill>, 2; mem:ST4[%state44] GPR32:%vreg108 GPR64common:%vreg110
3056B		B <BB#25>
	    Successors according to CFG: BB#25
> %X8<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> %X9<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> %W8<def> = LDRWui %X8<kill>, 797; mem:LD4[%calculatedCombinedCRC40]
> %W9<def> = LDRWui %X9<kill>, 797; mem:LD4[%calculatedCombinedCRC]
> %X10<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> %W8<def> = UBFMWri %W8<kill>, 31, 31
> %W8<def> = ORRWrs %W8<kill>, %W9<kill>, 1
> STRWui %W8<kill>, %X10<kill>, 797; mem:ST4[%calculatedCombinedCRC41]
> %X8<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> %X9<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> %W8<def> = LDRWui %X8<kill>, 796; mem:LD4[%calculatedBlockCRC42]
> %W10<def> = LDRWui %X9, 797; mem:LD4[%calculatedCombinedCRC43]
> %W8<def> = EORWrr %W10<kill>, %W8<kill>
> STRWui %W8<kill>, %X9<kill>, 797; mem:ST4[%calculatedCombinedCRC43]
> %X8<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> %W9<def> = MOVi32imm 14
> STRWui %W9<kill>, %X8<kill>, 2; mem:ST4[%state44]
> B <BB#25>
3072B	BB#24: derived from LLVM BB %if.else.45
	    Live Ins: %X19
	    Predecessors according to CFG: BB#15 BB#16
3088B		STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
3104B		B <BB#37>
	    Successors according to CFG: BB#37
> STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
> B <BB#37>
3120B	BB#25: derived from LLVM BB %if.end.46
	    Live Ins: %X19
	    Predecessors according to CFG: BB#23
3136B		B <BB#26>
	    Successors according to CFG: BB#26
> B <BB#26>
3152B	BB#26: derived from LLVM BB %if.end.47
	    Live Ins: %X19
	    Predecessors according to CFG: BB#9 BB#25
3168B		%vreg138<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg138
3184B		%vreg137<def> = LDRWui %vreg138<kill>, 2; mem:LD4[%state48] GPR32common:%vreg137 GPR64common:%vreg138
3200B		%WZR<def> = SUBSWri %vreg137<kill>, 10, 0, %NZCV<imp-def>; GPR32common:%vreg137
3216B		Bcc 11, <BB#36>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#36 BB#27
> %X8<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> %W8<def> = LDRWui %X8<kill>, 2; mem:LD4[%state48]
> %WZR<def> = SUBSWri %W8<kill>, 10, 0, %NZCV<imp-def>
> Bcc 11, <BB#36>, %NZCV<imp-use,kill>
3232B	BB#27: derived from LLVM BB %if.then.50
	    Live Ins: %X19
	    Predecessors according to CFG: BB#26
3248B		%vreg144<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg144
3264B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3280B		%X0<def> = COPY %vreg144<kill>; GPR64:%vreg144
3296B		BL <ga:@BZ2_decompress>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
3312B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3328B		%vreg143<def> = COPY %W0; GPR32:%vreg143
3344B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3360B		STACKMAP 5, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
3376B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3392B		STRWui %vreg143<kill>, <fi#4>, 0; mem:ST4[FixedStack4] GPR32:%vreg143
3408B		%vreg140<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32common:%vreg140
3424B		%WZR<def> = SUBSWri %vreg140<kill>, 4, 0, %NZCV<imp-def>; GPR32common:%vreg140
3440B		Bcc 1, <BB#33>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#33 BB#28
> %X0<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BL <ga:@BZ2_decompress>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = COPY %W0
Deleting identity copy.
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 5, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRWui %W0<kill>, <fi#4>, 0; mem:ST4[FixedStack4]
> %W8<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4]
> %WZR<def> = SUBSWri %W8<kill>, 4, 0, %NZCV<imp-def>
> Bcc 1, <BB#33>, %NZCV<imp-use,kill>
3456B	BB#28: derived from LLVM BB %if.then.53
	    Live Ins: %X19
	    Predecessors according to CFG: BB#27
3472B		%vreg154<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg154
3488B		%vreg153<def> = LDRWui %vreg154<kill>, 13; mem:LD4[%verbosity54] GPR32common:%vreg153 GPR64common:%vreg154
3504B		%WZR<def> = SUBSWri %vreg153<kill>, 3, 0, %NZCV<imp-def>; GPR32common:%vreg153
3520B		Bcc 11, <BB#30>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#30 BB#29
> %X8<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> %W8<def> = LDRWui %X8<kill>, 13; mem:LD4[%verbosity54]
> %WZR<def> = SUBSWri %W8<kill>, 3, 0, %NZCV<imp-def>
> Bcc 11, <BB#30>, %NZCV<imp-use,kill>
3536B	BB#29: derived from LLVM BB %if.then.56
	    Live Ins: %X19
	    Predecessors according to CFG: BB#28
3552B		%vreg166<def> = ADRP <ga:@stderr>[TF=1]; GPR64common:%vreg166
3600B		%vreg165<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg165
3632B		%vreg162<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg162
3640B		%vreg167<def> = ADDXri %vreg166<kill>, <ga:@stderr>[TF=34], 0; GPR64sp:%vreg167 GPR64common:%vreg166
3648B		%vreg168<def> = LDRXui %vreg167<kill>, 0; mem:LD8[@stderr] GPR64:%vreg168 GPR64sp:%vreg167
3656B		%vreg164<def> = LDRWui %vreg165<kill>, 795; mem:LD4[%storedCombinedCRC] GPR32:%vreg164 GPR64common:%vreg165
3664B		%vreg161<def> = LDRWui %vreg162<kill>, 797; mem:LD4[%calculatedCombinedCRC57] GPR32:%vreg161 GPR64common:%vreg162
3672B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3680B		%vreg158<def> = MOVaddr <ga:@bzlib__str_4______combi>[TF=1], <ga:@bzlib__str_4______combi>[TF=34]; GPR64:%vreg158
3696B		%X0<def> = COPY %vreg168<kill>; GPR64:%vreg168
3712B		%X1<def> = COPY %vreg158<kill>; GPR64:%vreg158
3728B		%W2<def> = COPY %vreg164<kill>; GPR32:%vreg164
3744B		%W3<def> = COPY %vreg161<kill>; GPR32:%vreg161
3760B		BL <ga:@fprintf>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %W2<imp-use>, %W3<imp-use>, %SP<imp-def>, %W0<imp-def>
3776B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3792B		%vreg159<def,dead> = COPY %W0; GPR32all:%vreg159
3808B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3824B		STACKMAP 6, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
3840B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#30
> %X8<def> = ADRP <ga:@stderr>[TF=1]
> %X9<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> %X10<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> %X8<def> = ADDXri %X8<kill>, <ga:@stderr>[TF=34], 0
> %X0<def> = LDRXui %X8<kill>, 0; mem:LD8[@stderr]
> %W2<def> = LDRWui %X9<kill>, 795; mem:LD4[%storedCombinedCRC]
> %W3<def> = LDRWui %X10<kill>, 797; mem:LD4[%calculatedCombinedCRC57]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X1<def> = MOVaddr <ga:@bzlib__str_4______combi>[TF=1], <ga:@bzlib__str_4______combi>[TF=34]
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X1<kill>
Deleting identity copy.
> %W2<def> = COPY %W2<kill>
Deleting identity copy.
> %W3<def> = COPY %W3<kill>
Deleting identity copy.
> BL <ga:@fprintf>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %W2<imp-use>, %W3<imp-use>, %SP<imp-def>, %W0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def,dead> = COPY %W0
Deleting identity copy.
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 6, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3856B	BB#30: derived from LLVM BB %if.end.59
	    Live Ins: %X19
	    Predecessors according to CFG: BB#28 BB#29
3872B		%vreg176<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg176
3904B		%vreg173<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg173
3912B		%vreg175<def> = LDRWui %vreg176<kill>, 797; mem:LD4[%calculatedCombinedCRC60] GPR32:%vreg175 GPR64common:%vreg176
3920B		%vreg172<def> = LDRWui %vreg173<kill>, 795; mem:LD4[%storedCombinedCRC61] GPR32:%vreg172 GPR64common:%vreg173
3936B		%WZR<def> = SUBSWrr %vreg175<kill>, %vreg172<kill>, %NZCV<imp-def>; GPR32:%vreg175,%vreg172
3952B		Bcc 0, <BB#32>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#32 BB#31
> %X8<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> %X9<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> %W8<def> = LDRWui %X8<kill>, 797; mem:LD4[%calculatedCombinedCRC60]
> %W9<def> = LDRWui %X9<kill>, 795; mem:LD4[%storedCombinedCRC61]
> %WZR<def> = SUBSWrr %W8<kill>, %W9<kill>, %NZCV<imp-def>
> Bcc 0, <BB#32>, %NZCV<imp-use,kill>
3968B	BB#31: derived from LLVM BB %if.then.63
	    Live Ins: %X19
	    Predecessors according to CFG: BB#30
3984B		%vreg179<def> = MOVi32imm 4294967292; GPR32:%vreg179
4000B		STRWui %vreg179<kill>, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg179
4016B		B <BB#37>
	    Successors according to CFG: BB#37
> %W8<def> = MOVi32imm 4294967292
> STRWui %W8<kill>, <fi#0>, 0; mem:ST4[FixedStack0]
> B <BB#37>
4032B	BB#32: derived from LLVM BB %if.end.64
	    Live Ins: %X19
	    Predecessors according to CFG: BB#30
4048B		%vreg178<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg178
4064B		STRWui %vreg178<kill>, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg178
4080B		B <BB#37>
	    Successors according to CFG: BB#37
> %W8<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4]
> STRWui %W8<kill>, <fi#0>, 0; mem:ST4[FixedStack0]
> B <BB#37>
4096B	BB#33: derived from LLVM BB %if.end.65
	    Live Ins: %X19
	    Predecessors according to CFG: BB#27
4112B		%vreg148<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg148
4128B		%vreg147<def> = LDRWui %vreg148<kill>, 2; mem:LD4[%state66] GPR32common:%vreg147 GPR64common:%vreg148
4144B		%WZR<def> = SUBSWri %vreg147<kill>, 2, 0, %NZCV<imp-def>; GPR32common:%vreg147
4160B		Bcc 0, <BB#35>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#35 BB#34
> %X8<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> %W8<def> = LDRWui %X8<kill>, 2; mem:LD4[%state66]
> %WZR<def> = SUBSWri %W8<kill>, 2, 0, %NZCV<imp-def>
> Bcc 0, <BB#35>, %NZCV<imp-use,kill>
4176B	BB#34: derived from LLVM BB %if.then.68
	    Live Ins: %X19
	    Predecessors according to CFG: BB#33
4192B		%vreg150<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg150
4208B		STRWui %vreg150<kill>, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg150
4224B		B <BB#37>
	    Successors according to CFG: BB#37
> %W8<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4]
> STRWui %W8<kill>, <fi#0>, 0; mem:ST4[FixedStack0]
> B <BB#37>
4240B	BB#35: derived from LLVM BB %if.end.69
	    Live Ins: %X19
	    Predecessors according to CFG: BB#33
4256B		B <BB#36>
	    Successors according to CFG: BB#36
> B <BB#36>
4272B	BB#36: derived from LLVM BB %if.end.70
	    Live Ins: %X19
	    Predecessors according to CFG: BB#26 BB#35
4288B		B <BB#7>
	    Successors according to CFG: BB#7
> B <BB#7>
4304B	BB#37: derived from LLVM BB %return
	    Live Ins: %X19
	    Predecessors according to CFG: BB#24 BB#34 BB#32 BB#31 BB#22 BB#14 BB#8 BB#5 BB#3 BB#1
4320B		%vreg188<def> = ADRP <ga:@BZ2_bzDecompress>[TF=1]; GPR64common:%vreg188
4336B		%vreg190<def> = ADDXri %vreg188<kill>, <ga:@BZ2_bzDecompress>[TF=34], 0; GPR64sp:%vreg190 GPR64common:%vreg188
4384B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4400B		%X0<def> = COPY %vreg190<kill>; GPR64sp:%vreg190
4416B		%X1<def> = COPY %vreg7<kill>; GPR64:%vreg7
4432B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
4448B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4464B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4480B		STACKMAP 7, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
4496B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4512B		%vreg187<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0] GPR32:%vreg187
4528B		%W0<def> = COPY %vreg187<kill>; GPR32:%vreg187
4544B		RET_ReallyLR %W0<imp-use>
> %X8<def> = ADRP <ga:@BZ2_bzDecompress>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@BZ2_bzDecompress>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19<kill>
> BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 7, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0]
> %W0<def> = COPY %W0<kill>
Deleting identity copy.
> RET_ReallyLR %W0<imp-use>
Computing live-in reg-units in ABI blocks.
0B	BB#0 W0#0 W30#0
Created 2 new intervals.
********** INTERVALS **********
W30 [0B,16r:0)[176r,176d:24)[224e,224d:12)[2224r,2224d:18)[2304e,2304d:11)[4048r,4048d:17)[4128e,4128d:10)[5872r,5872d:16)[5952e,5952d:9)[7648r,7648d:15)[7728e,7728d:8)[9120r,9120d:14)[9200e,9200d:7)[12320r,12320d:23)[12400e,12400d:6)[13472r,13472d:22)[13552e,13552d:5)[14624r,14624d:21)[14704e,14704d:4)[15728r,15728d:19)[15808e,15808d:3)[16528r,16528d:20)[16608e,16608d:2)[17248r,17248d:13)[17296e,17296d:1)  0@0B-phi 1@17296e 2@16608e 3@15808e 4@14704e 5@13552e 6@12400e 7@9200e 8@7728e 9@5952e 10@4128e 11@2304e 12@224e 13@17248r 14@9120r 15@7648r 16@5872r 17@4048r 18@2224r 19@15728r 20@16528r 21@14624r 22@13472r 23@12320r 24@176r
W0 [0B,32r:0)[144r,176r:23)[2192r,2224r:11)[2224r,2256r:10)[4016r,4048r:9)[4048r,4080r:8)[5840r,5872r:7)[5872r,5904r:6)[7616r,7648r:5)[7648r,7680r:4)[9088r,9120r:3)[9120r,9152r:2)[12288r,12320r:21)[12320r,12352r:20)[13440r,13472r:19)[13472r,13504r:18)[14592r,14624r:17)[14624r,14656r:16)[15696r,15728r:13)[15728r,15760r:12)[16496r,16528r:15)[16528r,16560r:14)[17216r,17248r:22)[17360r,17376r:1)  0@0B-phi 1@17360r 2@9120r 3@9088r 4@7648r 5@7616r 6@5872r 7@5840r 8@4048r 9@4016r 10@2224r 11@2192r 12@15728r 13@15696r 14@16528r 15@16496r 16@14624r 17@14592r 18@13472r 19@13440r 20@12320r 21@12288r 22@17216r 23@144r
%vreg0 [32r,48r:0)  0@32r
%vreg1 [48r,256r:0)  0@48r
%vreg3 [304r,320r:0)  0@304r
%vreg5 [288r,304r:0)  0@288r
%vreg6 [272r,288r:0)  0@272r
%vreg7 [64r,80r:0)  0@64r
%vreg8 [80r,96r:0)  0@80r
%vreg9 [96r,144r:0)  0@96r
%vreg10 [112r,160r:0)  0@112r
%vreg11 [16r,17232r:0)  0@16r
%vreg14 [10544r,10560r:0)  0@10544r
%vreg16 [10528r,10544r:0)  0@10528r
%vreg17 [10512r,10528r:0)  0@10512r
%vreg20 [10656r,10672r:0)  0@10656r
%vreg21 [10640r,10656r:0)  0@10640r
%vreg24 [11472r,11488r:0)  0@11472r
%vreg26 [11456r,11472r:0)  0@11456r
%vreg27 [11440r,11456r:0)  0@11440r
%vreg31 [11408r,11424r:0)  0@11408r
%vreg32 [11392r,11408r:0)  0@11392r
%vreg34 [11376r,11424r:0)  0@11376r
%vreg35 [11360r,11376r:0)  0@11360r
%vreg39 [11328r,11344r:0)  0@11328r
%vreg40 [11312r,11328r:0)  0@11312r
%vreg42 [11296r,11344r:0)  0@11296r
%vreg43 [11280r,11296r:0)  0@11280r
%vreg47 [11248r,11264r:0)  0@11248r
%vreg48 [11232r,11248r:0)  0@11232r
%vreg50 [11216r,11264r:0)  0@11216r
%vreg51 [11200r,11216r:0)  0@11200r
%vreg55 [11168r,11184r:0)  0@11168r
%vreg56 [11152r,11168r:0)  0@11152r
%vreg57 [11136r,11184r:0)  0@11136r
%vreg60 [11104r,11120r:0)  0@11104r
%vreg63 [11088r,11120r:0)  0@11088r
%vreg65 [11072r,11088r:0)  0@11072r
%vreg66 [10736r,10752r:0)  0@10736r
%vreg67 [10752r,11056r:0)  0@10752r
%vreg69 [11024r,11040r:0)  0@11024r
%vreg70 [11040r,11056r:0)  0@11040r
%vreg71 [11056r,11072r:0)  0@11056r
%vreg73 [10992r,11008r:0)  0@10992r
%vreg74 [11008r,11040r:0)  0@11008r
%vreg77 [10976r,10992r:0)  0@10976r
%vreg81 [10960r,10976r:0)  0@10960r
%vreg82 [10944r,10960r:0)  0@10944r
%vreg84 [10928r,10976r:0)  0@10928r
%vreg86 [10912r,10928r:0)  0@10912r
%vreg87 [10896r,10912r:0)  0@10896r
%vreg89 [10880r,11088r:0)  0@10880r
%vreg90 [10864r,10880r:0)  0@10864r
%vreg94 [10832r,10848r:0)  0@10832r
%vreg96 [10816r,10832r:0)  0@10816r
%vreg97 [10800r,10816r:0)  0@10800r
%vreg99 [10784r,10848r:0)  0@10784r
%vreg100 [10768r,10784r:0)  0@10768r
%vreg104 [11568r,11584r:0)  0@11568r
%vreg105 [11552r,11568r:0)  0@11552r
%vreg107 [11536r,11584r:0)  0@11536r
%vreg108 [11520r,11536r:0)  0@11520r
%vreg112 [11744r,11760r:0)  0@11744r
%vreg114 [11696r,11712r:0)  0@11696r
%vreg115 [11712r,11728r:0)  0@11712r
%vreg116 [11728r,11744r:0)  0@11728r
%vreg117 [11680r,11712r:0)  0@11680r
%vreg119 [11664r,11760r:0)  0@11664r
%vreg120 [11648r,11664r:0)  0@11648r
%vreg124 [11952r,11968r:0)  0@11952r
%vreg126 [11904r,11920r:0)  0@11904r
%vreg127 [11920r,11936r:0)  0@11920r
%vreg128 [11936r,11952r:0)  0@11936r
%vreg129 [11888r,11920r:0)  0@11888r
%vreg131 [11872r,11968r:0)  0@11872r
%vreg132 [11856r,11872r:0)  0@11856r
%vreg136 [13040r,13056r:0)  0@13040r
%vreg138 [12992r,13008r:0)  0@12992r
%vreg139 [13008r,13024r:0)  0@13008r
%vreg140 [13024r,13040r:0)  0@13024r
%vreg141 [12976r,13008r:0)  0@12976r
%vreg143 [12960r,13056r:0)  0@12960r
%vreg144 [12944r,12960r:0)  0@12944r
%vreg148 [12912r,12928r:0)  0@12912r
%vreg149 [12896r,12912r:0)  0@12896r
%vreg150 [12880r,12928r:0)  0@12880r
%vreg153 [12848r,12864r:0)  0@12848r
%vreg156 [12832r,12864r:0)  0@12832r
%vreg158 [12816r,12832r:0)  0@12816r
%vreg161 [12800r,12816r:0)  0@12800r
%vreg162 [12368r,12784r:0)  0@12368r
%vreg164 [12784r,12800r:0)  0@12784r
%vreg166 [12768r,12784r:0)  0@12768r
%vreg167 [12752r,12768r:0)  0@12752r
%vreg171 [12736r,12800r:0)  0@12736r
%vreg174 [12720r,12736r:0)  0@12720r
%vreg176 [12704r,12720r:0)  0@12704r
%vreg177 [12688r,12704r:0)  0@12688r
%vreg179 [12656r,12672r:0)  0@12656r
%vreg180 [12672r,12720r:0)  0@12672r
%vreg182 [12640r,12656r:0)  0@12640r
%vreg184 [12624r,12640r:0)  0@12624r
%vreg185 [12608r,12624r:0)  0@12608r
%vreg189 [12592r,12832r:0)  0@12592r
%vreg192 [12544r,12560r:0)  0@12544r
%vreg193 [12560r,12576r:0)  0@12560r
%vreg194 [12576r,12592r:0)  0@12576r
%vreg196 [12528r,12576r:0)  0@12528r
%vreg197 [12512r,12528r:0)  0@12512r
%vreg202 [12480r,12496r:0)  0@12480r
%vreg203 [12496r,12560r:0)  0@12496r
%vreg204 [12464r,12480r:0)  0@12464r
%vreg207 [12432r,12448r:0)  0@12432r
%vreg210 [12352r,12432r:0)  0@12352r
%vreg213 [12256r,12304r:0)  0@12256r
%vreg214 [12240r,12256r:0)  0@12240r
%vreg216 [12224r,12288r:0)  0@12224r
%vreg217 [12208r,12224r:0)  0@12208r
%vreg220 [12176r,12192r:0)  0@12176r
%vreg222 [12160r,12192r:0)  0@12160r
%vreg224 [12144r,12160r:0)  0@12144r
%vreg225 [12128r,12144r:0)  0@12128r
%vreg226 [12080r,12112r:0)  0@12080r
%vreg228 [12096r,12112r:0)  0@12096r
%vreg232 [13168r,13184r:0)  0@13168r
%vreg233 [13152r,13168r:0)  0@13152r
%vreg236 [13136r,13184r:0)  0@13136r
%vreg240 [14192r,14208r:0)  0@14192r
%vreg242 [14144r,14160r:0)  0@14144r
%vreg243 [14160r,14176r:0)  0@14160r
%vreg244 [14176r,14192r:0)  0@14176r
%vreg245 [14128r,14160r:0)  0@14128r
%vreg247 [14112r,14208r:0)  0@14112r
%vreg248 [14096r,14112r:0)  0@14096r
%vreg252 [14064r,14080r:0)  0@14064r
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%vreg972 [4688r,4768r:0)  0@4688r
%vreg974 [4736r,4752r:0)  0@4736r
%vreg975 [4752r,4768r:0)  0@4752r
%vreg976 [4768r,4784r:0)  0@4768r
%vreg981 [4720r,4752r:0)  0@4720r
%vreg982 [4704r,4720r:0)  0@4704r
%vreg984 [4976r,4992r:0)  0@4976r
%vreg988 [5440r,5456r:0)  0@5440r
%vreg990 [5392r,5408r:0)  0@5392r
%vreg991 [5408r,5424r:0)  0@5408r
%vreg992 [5424r,5440r:0)  0@5424r
%vreg993 [5376r,5408r:0)  0@5376r
%vreg995 [5360r,5456r:0)  0@5360r
%vreg996 [5344r,5360r:0)  0@5344r
%vreg1000 [5312r,5328r:0)  0@5312r
%vreg1001 [5296r,5312r:0)  0@5296r
%vreg1002 [5280r,5328r:0)  0@5280r
%vreg1005 [5248r,5264r:0)  0@5248r
%vreg1008 [5232r,5248r:0)  0@5232r
%vreg1011 [5216r,5232r:0)  0@5216r
%vreg1013 [5056r,5200r:0)  0@5056r
%vreg1014 [5072r,5200r:0)  0@5072r
%vreg1015 [5200r,5232r:0)  0@5200r
%vreg1017 [5168r,5184r:0)  0@5168r
%vreg1018 [5152r,5168r:0)  0@5152r
%vreg1022 [5120r,5136r:0)  0@5120r
%vreg1023 [5104r,5120r:0)  0@5104r
%vreg1024 [5088r,5136r:0)  0@5088r
%vreg1028 [5568r,5584r:0)  0@5568r
%vreg1029 [5552r,5568r:0)  0@5552r
%vreg1032 [5536r,5584r:0)  0@5536r
%vreg1035 [6448r,6464r:0)  0@6448r
%vreg1036 [6432r,6448r:0)  0@6432r
%vreg1039 [6400r,6416r:0)  0@6400r
%vreg1042 [6384r,6416r:0)  0@6384r
%vreg1044 [6368r,6384r:0)  0@6368r
%vreg1047 [6352r,6368r:0)  0@6352r
%vreg1048 [5920r,6336r:0)  0@5920r
%vreg1050 [6336r,6352r:0)  0@6336r
%vreg1052 [6320r,6336r:0)  0@6320r
%vreg1053 [6304r,6320r:0)  0@6304r
%vreg1057 [6288r,6352r:0)  0@6288r
%vreg1060 [6272r,6288r:0)  0@6272r
%vreg1062 [6256r,6272r:0)  0@6256r
%vreg1063 [6240r,6256r:0)  0@6240r
%vreg1065 [6208r,6224r:0)  0@6208r
%vreg1066 [6224r,6272r:0)  0@6224r
%vreg1068 [6192r,6208r:0)  0@6192r
%vreg1070 [6176r,6192r:0)  0@6176r
%vreg1071 [6160r,6176r:0)  0@6160r
%vreg1075 [6144r,6384r:0)  0@6144r
%vreg1078 [6096r,6112r:0)  0@6096r
%vreg1079 [6112r,6128r:0)  0@6112r
%vreg1080 [6128r,6144r:0)  0@6128r
%vreg1082 [6080r,6128r:0)  0@6080r
%vreg1083 [6064r,6080r:0)  0@6064r
%vreg1088 [6032r,6048r:0)  0@6032r
%vreg1089 [6048r,6112r:0)  0@6048r
%vreg1090 [6016r,6032r:0)  0@6016r
%vreg1093 [5984r,6000r:0)  0@5984r
%vreg1096 [5904r,5984r:0)  0@5904r
%vreg1099 [5808r,5856r:0)  0@5808r
%vreg1100 [5792r,5808r:0)  0@5792r
%vreg1102 [5776r,5840r:0)  0@5776r
%vreg1103 [5760r,5776r:0)  0@5760r
%vreg1104 [5712r,5744r:0)  0@5712r
%vreg1106 [5728r,5744r:0)  0@5728r
%vreg1109 [6736r,6752r:0)  0@6736r
%vreg1110 [6720r,6736r:0)  0@6720r
%vreg1114 [6688r,6704r:0)  0@6688r
%vreg1115 [6672r,6688r:0)  0@6672r
%vreg1116 [6656r,6704r:0)  0@6656r
%vreg1119 [6624r,6640r:0)  0@6624r
%vreg1121 [6608r,6640r:0)  0@6608r
%vreg1122 [6496r,6512r:0)  0@6496r
%vreg1123 [6512r,6592r:0)  0@6512r
%vreg1125 [6560r,6576r:0)  0@6560r
%vreg1126 [6576r,6592r:0)  0@6576r
%vreg1127 [6592r,6608r:0)  0@6592r
%vreg1132 [6544r,6576r:0)  0@6544r
%vreg1133 [6528r,6544r:0)  0@6528r
%vreg1135 [6800r,6816r:0)  0@6800r
%vreg1139 [7264r,7280r:0)  0@7264r
%vreg1141 [7216r,7232r:0)  0@7216r
%vreg1142 [7232r,7248r:0)  0@7232r
%vreg1143 [7248r,7264r:0)  0@7248r
%vreg1144 [7200r,7232r:0)  0@7200r
%vreg1146 [7184r,7280r:0)  0@7184r
%vreg1147 [7168r,7184r:0)  0@7168r
%vreg1151 [7136r,7152r:0)  0@7136r
%vreg1152 [7120r,7136r:0)  0@7120r
%vreg1153 [7104r,7152r:0)  0@7104r
%vreg1156 [7072r,7088r:0)  0@7072r
%vreg1159 [7056r,7072r:0)  0@7056r
%vreg1162 [7040r,7056r:0)  0@7040r
%vreg1164 [6880r,7024r:0)  0@6880r
%vreg1165 [6896r,7024r:0)  0@6896r
%vreg1166 [7024r,7056r:0)  0@7024r
%vreg1168 [6992r,7008r:0)  0@6992r
%vreg1169 [6976r,6992r:0)  0@6976r
%vreg1173 [6944r,6960r:0)  0@6944r
%vreg1174 [6928r,6944r:0)  0@6928r
%vreg1175 [6912r,6960r:0)  0@6912r
%vreg1179 [7392r,7408r:0)  0@7392r
%vreg1180 [7376r,7392r:0)  0@7376r
%vreg1183 [7360r,7408r:0)  0@7360r
%vreg1186 [8224r,8240r:0)  0@8224r
%vreg1187 [8208r,8224r:0)  0@8208r
%vreg1190 [8176r,8192r:0)  0@8176r
%vreg1193 [8160r,8192r:0)  0@8160r
%vreg1195 [8144r,8160r:0)  0@8144r
%vreg1198 [8128r,8144r:0)  0@8128r
%vreg1199 [7696r,8112r:0)  0@7696r
%vreg1201 [8112r,8128r:0)  0@8112r
%vreg1203 [8096r,8112r:0)  0@8096r
%vreg1204 [8080r,8096r:0)  0@8080r
%vreg1208 [8064r,8128r:0)  0@8064r
%vreg1211 [8048r,8064r:0)  0@8048r
%vreg1213 [8032r,8048r:0)  0@8032r
%vreg1214 [8016r,8032r:0)  0@8016r
%vreg1216 [7984r,8000r:0)  0@7984r
%vreg1217 [8000r,8048r:0)  0@8000r
%vreg1219 [7968r,7984r:0)  0@7968r
%vreg1221 [7952r,7968r:0)  0@7952r
%vreg1222 [7936r,7952r:0)  0@7936r
%vreg1226 [7920r,8160r:0)  0@7920r
%vreg1229 [7872r,7888r:0)  0@7872r
%vreg1230 [7888r,7904r:0)  0@7888r
%vreg1231 [7904r,7920r:0)  0@7904r
%vreg1233 [7856r,7904r:0)  0@7856r
%vreg1234 [7840r,7856r:0)  0@7840r
%vreg1239 [7808r,7824r:0)  0@7808r
%vreg1240 [7824r,7888r:0)  0@7824r
%vreg1241 [7792r,7808r:0)  0@7792r
%vreg1244 [7760r,7776r:0)  0@7760r
%vreg1247 [7680r,7760r:0)  0@7680r
%vreg1250 [7584r,7632r:0)  0@7584r
%vreg1251 [7568r,7584r:0)  0@7568r
%vreg1253 [7552r,7616r:0)  0@7552r
%vreg1254 [7536r,7552r:0)  0@7536r
%vreg1257 [8512r,8528r:0)  0@8512r
%vreg1258 [8496r,8512r:0)  0@8496r
%vreg1262 [8464r,8480r:0)  0@8464r
%vreg1263 [8448r,8464r:0)  0@8448r
%vreg1264 [8432r,8480r:0)  0@8432r
%vreg1267 [8400r,8416r:0)  0@8400r
%vreg1269 [8384r,8416r:0)  0@8384r
%vreg1270 [8272r,8288r:0)  0@8272r
%vreg1271 [8288r,8368r:0)  0@8288r
%vreg1273 [8336r,8352r:0)  0@8336r
%vreg1274 [8352r,8368r:0)  0@8352r
%vreg1275 [8368r,8384r:0)  0@8368r
%vreg1280 [8320r,8352r:0)  0@8320r
%vreg1281 [8304r,8320r:0)  0@8304r
%vreg1283 [8576r,8592r:0)  0@8576r
%vreg1286 [9696r,9712r:0)  0@9696r
%vreg1287 [9680r,9696r:0)  0@9680r
%vreg1290 [9648r,9664r:0)  0@9648r
%vreg1293 [9632r,9664r:0)  0@9632r
%vreg1295 [9616r,9632r:0)  0@9616r
%vreg1298 [9600r,9616r:0)  0@9600r
%vreg1299 [9168r,9584r:0)  0@9168r
%vreg1301 [9584r,9600r:0)  0@9584r
%vreg1303 [9568r,9584r:0)  0@9568r
%vreg1304 [9552r,9568r:0)  0@9552r
%vreg1308 [9536r,9600r:0)  0@9536r
%vreg1311 [9520r,9536r:0)  0@9520r
%vreg1313 [9504r,9520r:0)  0@9504r
%vreg1314 [9488r,9504r:0)  0@9488r
%vreg1316 [9456r,9472r:0)  0@9456r
%vreg1317 [9472r,9520r:0)  0@9472r
%vreg1319 [9440r,9456r:0)  0@9440r
%vreg1321 [9424r,9440r:0)  0@9424r
%vreg1322 [9408r,9424r:0)  0@9408r
%vreg1326 [9392r,9632r:0)  0@9392r
%vreg1329 [9344r,9360r:0)  0@9344r
%vreg1330 [9360r,9376r:0)  0@9360r
%vreg1331 [9376r,9392r:0)  0@9376r
%vreg1333 [9328r,9376r:0)  0@9328r
%vreg1334 [9312r,9328r:0)  0@9312r
%vreg1339 [9280r,9296r:0)  0@9280r
%vreg1340 [9296r,9360r:0)  0@9296r
%vreg1341 [9264r,9280r:0)  0@9264r
%vreg1344 [9232r,9248r:0)  0@9232r
%vreg1347 [9152r,9248r:0)  0@9152r
%vreg1350 [9056r,9104r:0)  0@9056r
%vreg1351 [9040r,9056r:0)  0@9040r
%vreg1353 [9024r,9088r:0)  0@9024r
%vreg1354 [9008r,9024r:0)  0@9008r
%vreg1357 [8976r,8992r:0)  0@8976r
%vreg1359 [8960r,8992r:0)  0@8960r
%vreg1362 [8944r,8960r:0)  0@8944r
%vreg1366 [8912r,8928r:0)  0@8912r
%vreg1367 [8896r,8912r:0)  0@8896r
%vreg1368 [8880r,8928r:0)  0@8880r
%vreg1371 [8848r,8864r:0)  0@8848r
%vreg1374 [8832r,8848r:0)  0@8832r
%vreg1377 [8816r,8832r:0)  0@8816r
%vreg1379 [8656r,8800r:0)  0@8656r
%vreg1380 [8672r,8800r:0)  0@8672r
%vreg1381 [8800r,8832r:0)  0@8800r
%vreg1383 [8768r,8784r:0)  0@8768r
%vreg1384 [8752r,8768r:0)  0@8752r
%vreg1388 [8720r,8736r:0)  0@8720r
%vreg1389 [8704r,8720r:0)  0@8704r
%vreg1390 [8688r,8736r:0)  0@8688r
%vreg1393 [9984r,10000r:0)  0@9984r
%vreg1394 [9968r,9984r:0)  0@9968r
%vreg1398 [9936r,9952r:0)  0@9936r
%vreg1399 [9920r,9936r:0)  0@9920r
%vreg1400 [9904r,9952r:0)  0@9904r
%vreg1403 [9872r,9888r:0)  0@9872r
%vreg1405 [9856r,9888r:0)  0@9856r
%vreg1406 [9744r,9760r:0)  0@9744r
%vreg1407 [9760r,9840r:0)  0@9760r
%vreg1409 [9808r,9824r:0)  0@9808r
%vreg1410 [9824r,9840r:0)  0@9824r
%vreg1411 [9840r,9856r:0)  0@9840r
%vreg1416 [9792r,9824r:0)  0@9792r
%vreg1417 [9776r,9792r:0)  0@9776r
%vreg1419 [10048r,10064r:0)  0@10048r
%vreg1423 [10384r,10400r:0)  0@10384r
%vreg1424 [10368r,10384r:0)  0@10368r
%vreg1425 [10352r,10400r:0)  0@10352r
%vreg1430 [10320r,10336r:0)  0@10320r
%vreg1431 [10304r,10320r:0)  0@10304r
%vreg1432 [10288r,10336r:0)  0@10288r
%vreg1434 [10128r,10272r:0)  0@10128r
%vreg1435 [10144r,10272r:0)  0@10144r
%vreg1436 [10272r,10320r:0)  0@10272r
%vreg1438 [10240r,10256r:0)  0@10240r
%vreg1439 [10224r,10240r:0)  0@10224r
%vreg1443 [10192r,10208r:0)  0@10192r
%vreg1444 [10176r,10192r:0)  0@10176r
%vreg1445 [10160r,10208r:0)  0@10160r
%vreg1448 [7472r,7488r:0)  0@7472r
%vreg1451 [7456r,7488r:0)  0@7456r
%vreg1454 [5648r,5664r:0)  0@5648r
%vreg1457 [5632r,5664r:0)  0@5632r
%vreg1460 [3824r,3840r:0)  0@3824r
%vreg1463 [3808r,3840r:0)  0@3808r
%vreg1464 [1920r,1936r:0)  0@1920r
%vreg1465 [17344r,17344d:0)  0@17344r
%vreg1466 [17200r,17216r:0)  0@17200r
%vreg1467 [17328r,17360r:0)  0@17328r
RegMasks: 176r 2224r 4048r 5872r 7648r 9120r 12320r 13472r 14624r 15728r 16528r 17248r
********** MACHINEINSTRS **********
# Machine code for function unRLE_obuf_to_output_SMALL: Post SSA
Frame Objects:
  fi#0: size=1, align=1, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=1, align=1, at location [SP]
Function Live Ins: %X0 in %vreg0, %LR in %vreg11

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %LR
16B		%vreg11<def> = COPY %LR; GPR64:%vreg11
32B		%vreg0<def> = COPY %X0; GPR64:%vreg0
48B		%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
64B		%vreg7<def> = ADRP <ga:@unRLE_obuf_to_output_SMALL>[TF=1]; GPR64common:%vreg7
80B		%vreg8<def> = ADDXri %vreg7, <ga:@unRLE_obuf_to_output_SMALL>[TF=34], 0; GPR64sp:%vreg8 GPR64common:%vreg7
96B		%vreg9<def> = COPY %vreg8; GPR64all:%vreg9 GPR64sp:%vreg8
112B		%vreg10<def> = COPY %vreg11; GPR64all:%vreg10 GPR64:%vreg11
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		%X0<def> = COPY %vreg9; GPR64all:%vreg9
160B		%X1<def> = COPY %vreg10; GPR64all:%vreg10
176B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
224B		STACKMAP 0, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, %vreg1, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1] GPR64:%vreg1
240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
256B		STRXui %vreg1, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg1
272B		%vreg6<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg6
288B		%vreg5<def> = LDRBBui %vreg6, 20; mem:LD1[%blockRandomised] GPR32:%vreg5 GPR64common:%vreg6
304B		%vreg3<def> = UBFMWri %vreg5, 0, 7; GPR32:%vreg3,%vreg5
320B		CBZW %vreg3, <BB#47>; GPR32:%vreg3
	    Successors according to CFG: BB#47 BB#1

336B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
352B		B <BB#2>
	    Successors according to CFG: BB#2

368B	BB#2: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#1 BB#46 BB#37 BB#35 BB#29 BB#27 BB#21 BB#19
384B		B <BB#3>
	    Successors according to CFG: BB#3

400B	BB#3: derived from LLVM BB %while.body.2
	    Predecessors according to CFG: BB#2 BB#9
416B		%vreg607<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg607
432B		%vreg606<def> = LDRXui %vreg607, 0; mem:LD8[%strm] GPR64common:%vreg606,%vreg607
448B		%vreg604<def> = LDRWui %vreg606, 8; mem:LD4[%avail_out] GPR32:%vreg604 GPR64common:%vreg606
464B		CBNZW %vreg604, <BB#5>; GPR32:%vreg604
	    Successors according to CFG: BB#5 BB#4

480B	BB#4: derived from LLVM BB %if.then.3
	    Predecessors according to CFG: BB#3
496B		STRBBui %WZR, <fi#0>, 0; mem:ST1[FixedStack0]
512B		B <BB#73>
	    Successors according to CFG: BB#73

528B	BB#5: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#3
544B		%vreg611<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg611
560B		%vreg610<def> = LDRWui %vreg611, 4; mem:LD4[%state_out_len] GPR32:%vreg610 GPR64common:%vreg611
576B		CBNZW %vreg610, <BB#7>; GPR32:%vreg610
	    Successors according to CFG: BB#7 BB#6

592B	BB#6: derived from LLVM BB %if.then.5
	    Predecessors according to CFG: BB#5
608B		B <BB#10>
	    Successors according to CFG: BB#10

624B	BB#7: derived from LLVM BB %if.end.6
	    Predecessors according to CFG: BB#5
640B		%vreg656<def> = ADRP <ga:@BZ2_crc32Table>[TF=1]; GPR64common:%vreg656
656B		%vreg657<def> = ADDXri %vreg656, <ga:@BZ2_crc32Table>[TF=34], 0; GPR64common:%vreg657,%vreg656
672B		%vreg690<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg690
688B		%vreg689<def> = LDRBBui %vreg690, 12; mem:LD1[%state_out_ch] GPR32:%vreg689 GPR64common:%vreg690
704B		%vreg687<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg687
720B		%vreg686<def> = LDRXui %vreg687, 0; mem:LD8[%strm7] GPR64common:%vreg686,%vreg687
736B		%vreg684<def> = LDRXui %vreg686, 3; mem:LD8[%next_out] GPR64common:%vreg684,%vreg686
752B		STRBBui %vreg689, %vreg684, 0; mem:ST1[%11] GPR32:%vreg689 GPR64common:%vreg684
768B		%vreg680<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg680
784B		%vreg679<def> = LDRWui %vreg680, 796; mem:LD4[%calculatedBlockCRC] GPR32:%vreg679 GPR64common:%vreg680
800B		%vreg677<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg677
816B		%vreg676<def> = LDRWui %vreg677, 796; mem:LD4[%calculatedBlockCRC8] GPR32:%vreg676 GPR64common:%vreg677
832B		%vreg674<def> = UBFMWri %vreg676, 24, 31; GPR32:%vreg674,%vreg676
848B		%vreg672<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg672
864B		%vreg671<def> = LDRBBui %vreg672, 12; mem:LD1[%state_out_ch9] GPR32:%vreg671 GPR64common:%vreg672
880B		%vreg667<def> = EORWrr %vreg674, %vreg671; GPR32:%vreg667,%vreg674,%vreg671
896B		%vreg663<def> = SUBREG_TO_REG 0, %vreg667, 15; GPR64:%vreg663 GPR32:%vreg667
912B		%vreg664<def> = UBFMXri %vreg663, 0, 31; GPR64:%vreg664,%vreg663
928B		%vreg659<def> = MOVi64imm 4; GPR64:%vreg659
944B		%vreg660<def> = MADDXrrr %vreg664, %vreg659, %XZR; GPR64:%vreg660,%vreg664,%vreg659
960B		%vreg661<def> = ADDXrr %vreg657, %vreg660; GPR64common:%vreg661,%vreg657 GPR64:%vreg660
976B		%vreg655<def> = LDRWui %vreg661, 0; mem:LD4[%arrayidx] GPR32:%vreg655 GPR64common:%vreg661
992B		%vreg653<def> = EORWrs %vreg655, %vreg679, 8; GPR32:%vreg653,%vreg655,%vreg679
1008B		%vreg650<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg650
1024B		STRWui %vreg653, %vreg650, 796; mem:ST4[%calculatedBlockCRC11] GPR32:%vreg653 GPR64common:%vreg650
1040B		%vreg647<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg647
1056B		%vreg646<def> = LDRWui %vreg647, 4; mem:LD4[%state_out_len12] GPR32common:%vreg646 GPR64common:%vreg647
1072B		%vreg645<def> = SUBWri %vreg646, 1, 0; GPR32common:%vreg645,%vreg646
1088B		STRWui %vreg645, %vreg647, 4; mem:ST4[%state_out_len12] GPR32common:%vreg645 GPR64common:%vreg647
1104B		%vreg641<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg641
1120B		%vreg640<def> = LDRXui %vreg641, 0; mem:LD8[%strm13] GPR64common:%vreg640,%vreg641
1136B		%vreg638<def> = LDRXui %vreg640, 3; mem:LD8[%next_out14] GPR64common:%vreg638,%vreg640
1152B		%vreg637<def> = ADDXri %vreg638, 1, 0; GPR64common:%vreg637,%vreg638
1168B		STRXui %vreg637, %vreg640, 3; mem:ST8[%next_out14] GPR64common:%vreg637,%vreg640
1184B		%vreg633<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg633
1200B		%vreg632<def> = LDRXui %vreg633, 0; mem:LD8[%strm15] GPR64common:%vreg632,%vreg633
1216B		%vreg630<def> = LDRWui %vreg632, 8; mem:LD4[%avail_out16] GPR32common:%vreg630 GPR64common:%vreg632
1232B		%vreg629<def> = SUBWri %vreg630, 1, 0; GPR32common:%vreg629,%vreg630
1248B		STRWui %vreg629, %vreg632, 8; mem:ST4[%avail_out16] GPR32common:%vreg629 GPR64common:%vreg632
1264B		%vreg625<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg625
1280B		%vreg624<def> = LDRXui %vreg625, 0; mem:LD8[%strm18] GPR64common:%vreg624,%vreg625
1296B		%vreg622<def> = LDRWui %vreg624, 9; mem:LD4[%total_out_lo32] GPR32common:%vreg622 GPR64common:%vreg624
1312B		%vreg621<def> = ADDWri %vreg622, 1, 0; GPR32common:%vreg621,%vreg622
1328B		STRWui %vreg621, %vreg624, 9; mem:ST4[%total_out_lo32] GPR32common:%vreg621 GPR64common:%vreg624
1344B		%vreg617<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg617
1360B		%vreg616<def> = LDRXui %vreg617, 0; mem:LD8[%strm19] GPR64common:%vreg616,%vreg617
1376B		%vreg614<def> = LDRWui %vreg616, 9; mem:LD4[%total_out_lo3220] GPR32:%vreg614 GPR64common:%vreg616
1392B		CBNZW %vreg614, <BB#9>; GPR32:%vreg614
	    Successors according to CFG: BB#9 BB#8

1408B	BB#8: derived from LLVM BB %if.then.23
	    Predecessors according to CFG: BB#7
1424B		%vreg698<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg698
1440B		%vreg697<def> = LDRXui %vreg698, 0; mem:LD8[%strm24] GPR64common:%vreg697,%vreg698
1456B		%vreg695<def> = LDRWui %vreg697, 10; mem:LD4[%total_out_hi32] GPR32common:%vreg695 GPR64common:%vreg697
1472B		%vreg694<def> = ADDWri %vreg695, 1, 0; GPR32common:%vreg694,%vreg695
1488B		STRWui %vreg694, %vreg697, 10; mem:ST4[%total_out_hi32] GPR32common:%vreg694 GPR64common:%vreg697
	    Successors according to CFG: BB#9

1504B	BB#9: derived from LLVM BB %if.end.26
	    Predecessors according to CFG: BB#7 BB#8
1520B		B <BB#3>
	    Successors according to CFG: BB#3

1536B	BB#10: derived from LLVM BB %while.end
	    Predecessors according to CFG: BB#6
1552B		%vreg710<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg710
1568B		%vreg709<def> = LDRWui %vreg710, 273; mem:LD4[%nblock_used] GPR32:%vreg709 GPR64common:%vreg710
1584B		%vreg707<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg707
1600B		%vreg704<def> = MOVi64imm 64080; GPR64:%vreg704
1616B		%vreg705<def> = ADDXrr %vreg707, %vreg704; GPR64common:%vreg705 GPR64:%vreg707,%vreg704
1632B		%vreg706<def> = LDRWui %vreg705, 0; mem:LD4[%save_nblock] GPR32common:%vreg706 GPR64common:%vreg705
1648B		%vreg702<def> = ADDWri %vreg706, 1, 0; GPR32common:%vreg702,%vreg706
1664B		%WZR<def> = SUBSWrr %vreg709, %vreg702, %NZCV<imp-def>; GPR32:%vreg709 GPR32common:%vreg702
1680B		Bcc 1, <BB#12>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#12 BB#11

1696B	BB#11: derived from LLVM BB %if.then.29
	    Predecessors according to CFG: BB#10
1712B		STRBBui %WZR, <fi#0>, 0; mem:ST1[FixedStack0]
1728B		B <BB#73>
	    Successors according to CFG: BB#73

1744B	BB#12: derived from LLVM BB %if.end.30
	    Predecessors according to CFG: BB#10
1760B		%vreg722<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg722
1776B		%vreg721<def> = LDRWui %vreg722, 273; mem:LD4[%nblock_used31] GPR32:%vreg721 GPR64common:%vreg722
1792B		%vreg719<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg719
1808B		%vreg716<def> = MOVi64imm 64080; GPR64:%vreg716
1824B		%vreg717<def> = ADDXrr %vreg719, %vreg716; GPR64common:%vreg717 GPR64:%vreg719,%vreg716
1840B		%vreg718<def> = LDRWui %vreg717, 0; mem:LD4[%save_nblock32] GPR32common:%vreg718 GPR64common:%vreg717
1856B		%vreg714<def> = ADDWri %vreg718, 1, 0; GPR32common:%vreg714,%vreg718
1872B		%WZR<def> = SUBSWrr %vreg721, %vreg714, %NZCV<imp-def>; GPR32:%vreg721 GPR32common:%vreg714
1888B		Bcc 13, <BB#14>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#14 BB#13

1904B	BB#13: derived from LLVM BB %if.then.36
	    Predecessors according to CFG: BB#12
1920B		%vreg1464<def> = MOVi32imm 1; GPR32:%vreg1464
1936B		STRBBui %vreg1464, <fi#0>, 0; mem:ST1[FixedStack0] GPR32:%vreg1464
1952B		B <BB#73>
	    Successors according to CFG: BB#73

1968B	BB#14: derived from LLVM BB %if.end.37
	    Predecessors according to CFG: BB#12
1984B		%vreg802<def> = MOVi32imm 1; GPR32:%vreg802
2000B		%vreg804<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg804
2016B		STRWui %vreg802, %vreg804, 4; mem:ST4[%state_out_len38] GPR32:%vreg802 GPR64common:%vreg804
2032B		%vreg801<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg801
2048B		%vreg800<def> = LDRWui %vreg801, 16; mem:LD4[%k0] GPR32:%vreg800 GPR64common:%vreg801
2064B		%vreg798<def> = COPY %vreg800; GPR32:%vreg798,%vreg800
2080B		%vreg796<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg796
2096B		STRBBui %vreg798, %vreg796, 12; mem:ST1[%state_out_ch40] GPR32:%vreg798 GPR64common:%vreg796
2112B		%vreg793<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg793
2128B		%vreg792<def> = LDRWui %vreg793, 15; mem:LD4[%tPos] GPR32:%vreg792 GPR64common:%vreg793
2144B		%vreg790<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg790
2160B		%vreg789<def> = ADDXri %vreg790, 1096, 0; GPR64sp:%vreg789 GPR64common:%vreg790
2176B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2192B		%W0<def> = COPY %vreg792; GPR32:%vreg792
2208B		%X1<def> = COPY %vreg789; GPR64sp:%vreg789
2224B		BL <ga:@BZ2_indexIntoF>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use,kill>, %W0<imp-def>
2240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2256B		%vreg786<def> = COPY %W0; GPR32all:%vreg786
2272B		%vreg738<def> = MOVi32imm 4; GPR32:%vreg738
2288B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2304B		STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
2320B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2336B		%vreg783<def> = COPY %vreg786; GPR32:%vreg783 GPR32all:%vreg786
2352B		STRBBui %vreg783, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg783
2368B		%vreg780<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg780
2384B		%vreg778<def> = LDRWui %vreg780, 15; mem:LD4[%tPos42] GPR32:%vreg778 GPR64common:%vreg780
2400B		%vreg779<def> = SUBREG_TO_REG 0, %vreg778, 15; GPR64:%vreg779 GPR32:%vreg778
2416B		%vreg773<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg773
2432B		%vreg772<def> = LDRXui %vreg773, 395; mem:LD8[%ll16] GPR64:%vreg772 GPR64common:%vreg773
2448B		%vreg768<def> = MOVi64imm 2; GPR64:%vreg768
2464B		%vreg769<def> = MADDXrrr %vreg779, %vreg768, %XZR; GPR64:%vreg769,%vreg779,%vreg768
2480B		%vreg770<def> = ADDXrr %vreg772, %vreg769; GPR64common:%vreg770 GPR64:%vreg772,%vreg769
2496B		%vreg765<def> = LDRHHui %vreg770, 0; mem:LD2[%arrayidx44] GPR32:%vreg765 GPR64common:%vreg770
2512B		%vreg761<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg761
2528B		%vreg760<def> = LDRWui %vreg761, 15; mem:LD4[%tPos46] GPR32:%vreg760 GPR64common:%vreg761
2544B		%vreg758<def> = UBFMWri %vreg760, 1, 31; GPR32:%vreg758,%vreg760
2560B		%vreg755<def> = SUBREG_TO_REG 0, %vreg758, 15; GPR64:%vreg755 GPR32:%vreg758
2576B		%vreg756<def> = UBFMXri %vreg755, 0, 31; GPR64:%vreg756,%vreg755
2592B		%vreg753<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg753
2608B		%vreg752<def> = LDRXui %vreg753, 396; mem:LD8[%ll4] GPR64:%vreg752 GPR64common:%vreg753
2624B		%vreg750<def> = ADDXrr %vreg752, %vreg756; GPR64common:%vreg750 GPR64:%vreg752,%vreg756
2640B		%vreg747<def> = LDRBBui %vreg750, 0; mem:LD1[%arrayidx49] GPR32:%vreg747 GPR64common:%vreg750
2656B		%vreg743<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg743
2672B		%vreg742<def> = LDRWui %vreg743, 15; mem:LD4[%tPos51] GPR32:%vreg742 GPR64common:%vreg743
2688B		%vreg740<def> = ANDWrs %vreg738, %vreg742, 2; GPR32:%vreg740,%vreg738,%vreg742
2704B		%vreg737<def> = LSRVWr %vreg747, %vreg740; GPR32:%vreg737,%vreg747,%vreg740
2720B		%vreg734<def> = ANDWri %vreg737, 3; GPR32common:%vreg734 GPR32:%vreg737
2736B		%vreg732<def> = ORRWrs %vreg765, %vreg734, 16; GPR32:%vreg732,%vreg765 GPR32common:%vreg734
2752B		%vreg729<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg729
2768B		STRWui %vreg732, %vreg729, 15; mem:ST4[%tPos56] GPR32:%vreg732 GPR64common:%vreg729
2784B		%vreg726<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg726
2800B		%vreg725<def> = LDRWui %vreg726, 6; mem:LD4[%rNToGo] GPR32:%vreg725 GPR64common:%vreg726
2816B		CBNZW %vreg725, <BB#18>; GPR32:%vreg725
	    Successors according to CFG: BB#18 BB#15

2832B	BB#15: derived from LLVM BB %if.then.59
	    Predecessors according to CFG: BB#14
2848B		%vreg820<def> = ADRP <ga:@BZ2_rNums>[TF=1]; GPR64common:%vreg820
2864B		%vreg821<def> = ADDXri %vreg820, <ga:@BZ2_rNums>[TF=34], 0; GPR64common:%vreg821,%vreg820
2880B		%vreg831<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg831
2896B		%vreg830<def> = LDRSWui %vreg831, 7; mem:LD4[%rTPos] GPR64:%vreg830 GPR64common:%vreg831
2912B		%vreg823<def> = MOVi64imm 4; GPR64:%vreg823
2928B		%vreg824<def> = MADDXrrr %vreg830, %vreg823, %XZR; GPR64:%vreg824,%vreg830,%vreg823
2944B		%vreg825<def> = ADDXrr %vreg821, %vreg824; GPR64common:%vreg825,%vreg821 GPR64:%vreg824
2960B		%vreg819<def> = LDRWui %vreg825, 0; mem:LD4[%arrayidx61] GPR32:%vreg819 GPR64common:%vreg825
2976B		%vreg817<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg817
2992B		STRWui %vreg819, %vreg817, 6; mem:ST4[%rNToGo62] GPR32:%vreg819 GPR64common:%vreg817
3008B		%vreg814<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg814
3024B		%vreg813<def> = LDRWui %vreg814, 7; mem:LD4[%rTPos63] GPR32common:%vreg813 GPR64common:%vreg814
3040B		%vreg812<def> = ADDWri %vreg813, 1, 0; GPR32common:%vreg812,%vreg813
3056B		STRWui %vreg812, %vreg814, 7; mem:ST4[%rTPos63] GPR32common:%vreg812 GPR64common:%vreg814
3072B		%vreg808<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg808
3088B		%vreg807<def> = LDRWui %vreg808, 7; mem:LD4[%rTPos65] GPR32common:%vreg807 GPR64common:%vreg808
3104B		%WZR<def> = SUBSWri %vreg807, 512, 0, %NZCV<imp-def>; GPR32common:%vreg807
3120B		Bcc 1, <BB#17>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#17 BB#16

3136B	BB#16: derived from LLVM BB %if.then.68
	    Predecessors according to CFG: BB#15
3152B		%vreg833<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg833
3168B		STRWui %WZR, %vreg833, 7; mem:ST4[%rTPos69] GPR64common:%vreg833
	    Successors according to CFG: BB#17

3184B	BB#17: derived from LLVM BB %if.end.70
	    Predecessors according to CFG: BB#15 BB#16
3200B		B <BB#18>
	    Successors according to CFG: BB#18

3216B	BB#18: derived from LLVM BB %if.end.71
	    Predecessors according to CFG: BB#14 BB#17
3232B		%vreg862<def> = MOVi32imm 1; GPR32:%vreg862
3248B		%vreg863<def> = COPY %WZR; GPR32:%vreg863
3264B		%vreg873<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg873
3280B		%vreg872<def> = LDRWui %vreg873, 6; mem:LD4[%rNToGo72] GPR32common:%vreg872 GPR64common:%vreg873
3296B		%vreg871<def> = SUBWri %vreg872, 1, 0; GPR32common:%vreg871,%vreg872
3312B		STRWui %vreg871, %vreg873, 6; mem:ST4[%rNToGo72] GPR32common:%vreg871 GPR64common:%vreg873
3328B		%vreg867<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg867
3344B		%vreg866<def> = LDRWui %vreg867, 6; mem:LD4[%rNToGo74] GPR32common:%vreg866 GPR64common:%vreg867
3360B		%WZR<def> = SUBSWri %vreg866, 1, 0, %NZCV<imp-def>; GPR32common:%vreg866
3376B		%vreg864<def> = CSELWr %vreg862, %vreg863, 0, %NZCV<imp-use,kill>; GPR32:%vreg864,%vreg862,%vreg863
3392B		%vreg860<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg860
3408B		%vreg857<def> = EORWrr %vreg860, %vreg864; GPR32:%vreg857,%vreg860,%vreg864
3424B		%vreg854<def> = COPY %vreg857; GPR32:%vreg854,%vreg857
3440B		STRBBui %vreg854, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg854
3456B		%vreg851<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg851
3472B		%vreg850<def> = LDRWui %vreg851, 273; mem:LD4[%nblock_used80] GPR32common:%vreg850 GPR64common:%vreg851
3488B		%vreg849<def> = ADDWri %vreg850, 1, 0; GPR32common:%vreg849,%vreg850
3504B		STRWui %vreg849, %vreg851, 273; mem:ST4[%nblock_used80] GPR32common:%vreg849 GPR64common:%vreg851
3520B		%vreg845<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg845
3536B		%vreg844<def> = LDRWui %vreg845, 273; mem:LD4[%nblock_used82] GPR32:%vreg844 GPR64common:%vreg845
3552B		%vreg842<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg842
3568B		%vreg839<def> = MOVi64imm 64080; GPR64:%vreg839
3584B		%vreg840<def> = ADDXrr %vreg842, %vreg839; GPR64common:%vreg840 GPR64:%vreg842,%vreg839
3600B		%vreg841<def> = LDRWui %vreg840, 0; mem:LD4[%save_nblock83] GPR32common:%vreg841 GPR64common:%vreg840
3616B		%vreg837<def> = ADDWri %vreg841, 1, 0; GPR32common:%vreg837,%vreg841
3632B		%WZR<def> = SUBSWrr %vreg844, %vreg837, %NZCV<imp-def>; GPR32:%vreg844 GPR32common:%vreg837
3648B		Bcc 1, <BB#20>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#20 BB#19

3664B	BB#19: derived from LLVM BB %if.then.87
	    Predecessors according to CFG: BB#18
3680B		B <BB#2>
	    Successors according to CFG: BB#2

3696B	BB#20: derived from LLVM BB %if.end.88
	    Predecessors according to CFG: BB#18
3712B		%vreg881<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg881
3728B		%vreg878<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg878
3744B		%vreg877<def> = LDRWui %vreg878, 16; mem:LD4[%k090] GPR32:%vreg877 GPR64common:%vreg878
3760B		%WZR<def> = SUBSWrr %vreg881, %vreg877, %NZCV<imp-def>; GPR32:%vreg881,%vreg877
3776B		Bcc 0, <BB#22>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#22 BB#21

3792B	BB#21: derived from LLVM BB %if.then.93
	    Predecessors according to CFG: BB#20
3808B		%vreg1463<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg1463
3824B		%vreg1460<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1460
3840B		STRWui %vreg1463, %vreg1460, 16; mem:ST4[%k095] GPR32:%vreg1463 GPR64common:%vreg1460
3856B		B <BB#2>
	    Successors according to CFG: BB#2

3872B	BB#22: derived from LLVM BB %if.end.96
	    Predecessors according to CFG: BB#20
3888B		%vreg953<def> = MOVi32imm 2; GPR32:%vreg953
3904B		%vreg955<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg955
3920B		STRWui %vreg953, %vreg955, 4; mem:ST4[%state_out_len97] GPR32:%vreg953 GPR64common:%vreg955
3936B		%vreg952<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg952
3952B		%vreg951<def> = LDRWui %vreg952, 15; mem:LD4[%tPos98] GPR32:%vreg951 GPR64common:%vreg952
3968B		%vreg949<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg949
3984B		%vreg948<def> = ADDXri %vreg949, 1096, 0; GPR64sp:%vreg948 GPR64common:%vreg949
4000B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4016B		%W0<def> = COPY %vreg951; GPR32:%vreg951
4032B		%X1<def> = COPY %vreg948; GPR64sp:%vreg948
4048B		BL <ga:@BZ2_indexIntoF>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use,kill>, %W0<imp-def>
4064B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4080B		%vreg945<def> = COPY %W0; GPR32all:%vreg945
4096B		%vreg897<def> = MOVi32imm 4; GPR32:%vreg897
4112B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4128B		STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
4144B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4160B		%vreg942<def> = COPY %vreg945; GPR32:%vreg942 GPR32all:%vreg945
4176B		STRBBui %vreg942, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg942
4192B		%vreg939<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg939
4208B		%vreg937<def> = LDRWui %vreg939, 15; mem:LD4[%tPos103] GPR32:%vreg937 GPR64common:%vreg939
4224B		%vreg938<def> = SUBREG_TO_REG 0, %vreg937, 15; GPR64:%vreg938 GPR32:%vreg937
4240B		%vreg932<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg932
4256B		%vreg931<def> = LDRXui %vreg932, 395; mem:LD8[%ll16105] GPR64:%vreg931 GPR64common:%vreg932
4272B		%vreg927<def> = MOVi64imm 2; GPR64:%vreg927
4288B		%vreg928<def> = MADDXrrr %vreg938, %vreg927, %XZR; GPR64:%vreg928,%vreg938,%vreg927
4304B		%vreg929<def> = ADDXrr %vreg931, %vreg928; GPR64common:%vreg929 GPR64:%vreg931,%vreg928
4320B		%vreg924<def> = LDRHHui %vreg929, 0; mem:LD2[%arrayidx106] GPR32:%vreg924 GPR64common:%vreg929
4336B		%vreg920<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg920
4352B		%vreg919<def> = LDRWui %vreg920, 15; mem:LD4[%tPos108] GPR32:%vreg919 GPR64common:%vreg920
4368B		%vreg917<def> = UBFMWri %vreg919, 1, 31; GPR32:%vreg917,%vreg919
4384B		%vreg914<def> = SUBREG_TO_REG 0, %vreg917, 15; GPR64:%vreg914 GPR32:%vreg917
4400B		%vreg915<def> = UBFMXri %vreg914, 0, 31; GPR64:%vreg915,%vreg914
4416B		%vreg912<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg912
4432B		%vreg911<def> = LDRXui %vreg912, 396; mem:LD8[%ll4111] GPR64:%vreg911 GPR64common:%vreg912
4448B		%vreg909<def> = ADDXrr %vreg911, %vreg915; GPR64common:%vreg909 GPR64:%vreg911,%vreg915
4464B		%vreg906<def> = LDRBBui %vreg909, 0; mem:LD1[%arrayidx112] GPR32:%vreg906 GPR64common:%vreg909
4480B		%vreg902<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg902
4496B		%vreg901<def> = LDRWui %vreg902, 15; mem:LD4[%tPos114] GPR32:%vreg901 GPR64common:%vreg902
4512B		%vreg899<def> = ANDWrs %vreg897, %vreg901, 2; GPR32:%vreg899,%vreg897,%vreg901
4528B		%vreg896<def> = LSRVWr %vreg906, %vreg899; GPR32:%vreg896,%vreg906,%vreg899
4544B		%vreg893<def> = ANDWri %vreg896, 3; GPR32common:%vreg893 GPR32:%vreg896
4560B		%vreg891<def> = ORRWrs %vreg924, %vreg893, 16; GPR32:%vreg891,%vreg924 GPR32common:%vreg893
4576B		%vreg888<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg888
4592B		STRWui %vreg891, %vreg888, 15; mem:ST4[%tPos121] GPR32:%vreg891 GPR64common:%vreg888
4608B		%vreg885<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg885
4624B		%vreg884<def> = LDRWui %vreg885, 6; mem:LD4[%rNToGo122] GPR32:%vreg884 GPR64common:%vreg885
4640B		CBNZW %vreg884, <BB#26>; GPR32:%vreg884
	    Successors according to CFG: BB#26 BB#23

4656B	BB#23: derived from LLVM BB %if.then.125
	    Predecessors according to CFG: BB#22
4672B		%vreg971<def> = ADRP <ga:@BZ2_rNums>[TF=1]; GPR64common:%vreg971
4688B		%vreg972<def> = ADDXri %vreg971, <ga:@BZ2_rNums>[TF=34], 0; GPR64common:%vreg972,%vreg971
4704B		%vreg982<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg982
4720B		%vreg981<def> = LDRSWui %vreg982, 7; mem:LD4[%rTPos126] GPR64:%vreg981 GPR64common:%vreg982
4736B		%vreg974<def> = MOVi64imm 4; GPR64:%vreg974
4752B		%vreg975<def> = MADDXrrr %vreg981, %vreg974, %XZR; GPR64:%vreg975,%vreg981,%vreg974
4768B		%vreg976<def> = ADDXrr %vreg972, %vreg975; GPR64common:%vreg976,%vreg972 GPR64:%vreg975
4784B		%vreg970<def> = LDRWui %vreg976, 0; mem:LD4[%arrayidx128] GPR32:%vreg970 GPR64common:%vreg976
4800B		%vreg968<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg968
4816B		STRWui %vreg970, %vreg968, 6; mem:ST4[%rNToGo129] GPR32:%vreg970 GPR64common:%vreg968
4832B		%vreg965<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg965
4848B		%vreg964<def> = LDRWui %vreg965, 7; mem:LD4[%rTPos130] GPR32common:%vreg964 GPR64common:%vreg965
4864B		%vreg963<def> = ADDWri %vreg964, 1, 0; GPR32common:%vreg963,%vreg964
4880B		STRWui %vreg963, %vreg965, 7; mem:ST4[%rTPos130] GPR32common:%vreg963 GPR64common:%vreg965
4896B		%vreg959<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg959
4912B		%vreg958<def> = LDRWui %vreg959, 7; mem:LD4[%rTPos132] GPR32common:%vreg958 GPR64common:%vreg959
4928B		%WZR<def> = SUBSWri %vreg958, 512, 0, %NZCV<imp-def>; GPR32common:%vreg958
4944B		Bcc 1, <BB#25>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#25 BB#24

4960B	BB#24: derived from LLVM BB %if.then.135
	    Predecessors according to CFG: BB#23
4976B		%vreg984<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg984
4992B		STRWui %WZR, %vreg984, 7; mem:ST4[%rTPos136] GPR64common:%vreg984
	    Successors according to CFG: BB#25

5008B	BB#25: derived from LLVM BB %if.end.137
	    Predecessors according to CFG: BB#23 BB#24
5024B		B <BB#26>
	    Successors according to CFG: BB#26

5040B	BB#26: derived from LLVM BB %if.end.138
	    Predecessors according to CFG: BB#22 BB#25
5056B		%vreg1013<def> = MOVi32imm 1; GPR32:%vreg1013
5072B		%vreg1014<def> = COPY %WZR; GPR32:%vreg1014
5088B		%vreg1024<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1024
5104B		%vreg1023<def> = LDRWui %vreg1024, 6; mem:LD4[%rNToGo139] GPR32common:%vreg1023 GPR64common:%vreg1024
5120B		%vreg1022<def> = SUBWri %vreg1023, 1, 0; GPR32common:%vreg1022,%vreg1023
5136B		STRWui %vreg1022, %vreg1024, 6; mem:ST4[%rNToGo139] GPR32common:%vreg1022 GPR64common:%vreg1024
5152B		%vreg1018<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1018
5168B		%vreg1017<def> = LDRWui %vreg1018, 6; mem:LD4[%rNToGo141] GPR32common:%vreg1017 GPR64common:%vreg1018
5184B		%WZR<def> = SUBSWri %vreg1017, 1, 0, %NZCV<imp-def>; GPR32common:%vreg1017
5200B		%vreg1015<def> = CSELWr %vreg1013, %vreg1014, 0, %NZCV<imp-use,kill>; GPR32:%vreg1015,%vreg1013,%vreg1014
5216B		%vreg1011<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg1011
5232B		%vreg1008<def> = EORWrr %vreg1011, %vreg1015; GPR32:%vreg1008,%vreg1011,%vreg1015
5248B		%vreg1005<def> = COPY %vreg1008; GPR32:%vreg1005,%vreg1008
5264B		STRBBui %vreg1005, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg1005
5280B		%vreg1002<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1002
5296B		%vreg1001<def> = LDRWui %vreg1002, 273; mem:LD4[%nblock_used148] GPR32common:%vreg1001 GPR64common:%vreg1002
5312B		%vreg1000<def> = ADDWri %vreg1001, 1, 0; GPR32common:%vreg1000,%vreg1001
5328B		STRWui %vreg1000, %vreg1002, 273; mem:ST4[%nblock_used148] GPR32common:%vreg1000 GPR64common:%vreg1002
5344B		%vreg996<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg996
5360B		%vreg995<def> = LDRWui %vreg996, 273; mem:LD4[%nblock_used150] GPR32:%vreg995 GPR64common:%vreg996
5376B		%vreg993<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg993
5392B		%vreg990<def> = MOVi64imm 64080; GPR64:%vreg990
5408B		%vreg991<def> = ADDXrr %vreg993, %vreg990; GPR64common:%vreg991 GPR64:%vreg993,%vreg990
5424B		%vreg992<def> = LDRWui %vreg991, 0; mem:LD4[%save_nblock151] GPR32common:%vreg992 GPR64common:%vreg991
5440B		%vreg988<def> = ADDWri %vreg992, 1, 0; GPR32common:%vreg988,%vreg992
5456B		%WZR<def> = SUBSWrr %vreg995, %vreg988, %NZCV<imp-def>; GPR32:%vreg995 GPR32common:%vreg988
5472B		Bcc 1, <BB#28>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#28 BB#27

5488B	BB#27: derived from LLVM BB %if.then.155
	    Predecessors according to CFG: BB#26
5504B		B <BB#2>
	    Successors according to CFG: BB#2

5520B	BB#28: derived from LLVM BB %if.end.156
	    Predecessors according to CFG: BB#26
5536B		%vreg1032<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg1032
5552B		%vreg1029<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1029
5568B		%vreg1028<def> = LDRWui %vreg1029, 16; mem:LD4[%k0158] GPR32:%vreg1028 GPR64common:%vreg1029
5584B		%WZR<def> = SUBSWrr %vreg1032, %vreg1028, %NZCV<imp-def>; GPR32:%vreg1032,%vreg1028
5600B		Bcc 0, <BB#30>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#30 BB#29

5616B	BB#29: derived from LLVM BB %if.then.161
	    Predecessors according to CFG: BB#28
5632B		%vreg1457<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg1457
5648B		%vreg1454<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1454
5664B		STRWui %vreg1457, %vreg1454, 16; mem:ST4[%k0163] GPR32:%vreg1457 GPR64common:%vreg1454
5680B		B <BB#2>
	    Successors according to CFG: BB#2

5696B	BB#30: derived from LLVM BB %if.end.164
	    Predecessors according to CFG: BB#28
5712B		%vreg1104<def> = MOVi32imm 3; GPR32:%vreg1104
5728B		%vreg1106<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1106
5744B		STRWui %vreg1104, %vreg1106, 4; mem:ST4[%state_out_len165] GPR32:%vreg1104 GPR64common:%vreg1106
5760B		%vreg1103<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1103
5776B		%vreg1102<def> = LDRWui %vreg1103, 15; mem:LD4[%tPos166] GPR32:%vreg1102 GPR64common:%vreg1103
5792B		%vreg1100<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1100
5808B		%vreg1099<def> = ADDXri %vreg1100, 1096, 0; GPR64sp:%vreg1099 GPR64common:%vreg1100
5824B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5840B		%W0<def> = COPY %vreg1102; GPR32:%vreg1102
5856B		%X1<def> = COPY %vreg1099; GPR64sp:%vreg1099
5872B		BL <ga:@BZ2_indexIntoF>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use,kill>, %W0<imp-def>
5888B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5904B		%vreg1096<def> = COPY %W0; GPR32all:%vreg1096
5920B		%vreg1048<def> = MOVi32imm 4; GPR32:%vreg1048
5936B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5952B		STACKMAP 3, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
5968B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5984B		%vreg1093<def> = COPY %vreg1096; GPR32:%vreg1093 GPR32all:%vreg1096
6000B		STRBBui %vreg1093, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg1093
6016B		%vreg1090<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1090
6032B		%vreg1088<def> = LDRWui %vreg1090, 15; mem:LD4[%tPos171] GPR32:%vreg1088 GPR64common:%vreg1090
6048B		%vreg1089<def> = SUBREG_TO_REG 0, %vreg1088, 15; GPR64:%vreg1089 GPR32:%vreg1088
6064B		%vreg1083<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1083
6080B		%vreg1082<def> = LDRXui %vreg1083, 395; mem:LD8[%ll16173] GPR64:%vreg1082 GPR64common:%vreg1083
6096B		%vreg1078<def> = MOVi64imm 2; GPR64:%vreg1078
6112B		%vreg1079<def> = MADDXrrr %vreg1089, %vreg1078, %XZR; GPR64:%vreg1079,%vreg1089,%vreg1078
6128B		%vreg1080<def> = ADDXrr %vreg1082, %vreg1079; GPR64common:%vreg1080 GPR64:%vreg1082,%vreg1079
6144B		%vreg1075<def> = LDRHHui %vreg1080, 0; mem:LD2[%arrayidx174] GPR32:%vreg1075 GPR64common:%vreg1080
6160B		%vreg1071<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1071
6176B		%vreg1070<def> = LDRWui %vreg1071, 15; mem:LD4[%tPos176] GPR32:%vreg1070 GPR64common:%vreg1071
6192B		%vreg1068<def> = UBFMWri %vreg1070, 1, 31; GPR32:%vreg1068,%vreg1070
6208B		%vreg1065<def> = SUBREG_TO_REG 0, %vreg1068, 15; GPR64:%vreg1065 GPR32:%vreg1068
6224B		%vreg1066<def> = UBFMXri %vreg1065, 0, 31; GPR64:%vreg1066,%vreg1065
6240B		%vreg1063<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1063
6256B		%vreg1062<def> = LDRXui %vreg1063, 396; mem:LD8[%ll4179] GPR64:%vreg1062 GPR64common:%vreg1063
6272B		%vreg1060<def> = ADDXrr %vreg1062, %vreg1066; GPR64common:%vreg1060 GPR64:%vreg1062,%vreg1066
6288B		%vreg1057<def> = LDRBBui %vreg1060, 0; mem:LD1[%arrayidx180] GPR32:%vreg1057 GPR64common:%vreg1060
6304B		%vreg1053<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1053
6320B		%vreg1052<def> = LDRWui %vreg1053, 15; mem:LD4[%tPos182] GPR32:%vreg1052 GPR64common:%vreg1053
6336B		%vreg1050<def> = ANDWrs %vreg1048, %vreg1052, 2; GPR32:%vreg1050,%vreg1048,%vreg1052
6352B		%vreg1047<def> = LSRVWr %vreg1057, %vreg1050; GPR32:%vreg1047,%vreg1057,%vreg1050
6368B		%vreg1044<def> = ANDWri %vreg1047, 3; GPR32common:%vreg1044 GPR32:%vreg1047
6384B		%vreg1042<def> = ORRWrs %vreg1075, %vreg1044, 16; GPR32:%vreg1042,%vreg1075 GPR32common:%vreg1044
6400B		%vreg1039<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1039
6416B		STRWui %vreg1042, %vreg1039, 15; mem:ST4[%tPos189] GPR32:%vreg1042 GPR64common:%vreg1039
6432B		%vreg1036<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1036
6448B		%vreg1035<def> = LDRWui %vreg1036, 6; mem:LD4[%rNToGo190] GPR32:%vreg1035 GPR64common:%vreg1036
6464B		CBNZW %vreg1035, <BB#34>; GPR32:%vreg1035
	    Successors according to CFG: BB#34 BB#31

6480B	BB#31: derived from LLVM BB %if.then.193
	    Predecessors according to CFG: BB#30
6496B		%vreg1122<def> = ADRP <ga:@BZ2_rNums>[TF=1]; GPR64common:%vreg1122
6512B		%vreg1123<def> = ADDXri %vreg1122, <ga:@BZ2_rNums>[TF=34], 0; GPR64common:%vreg1123,%vreg1122
6528B		%vreg1133<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1133
6544B		%vreg1132<def> = LDRSWui %vreg1133, 7; mem:LD4[%rTPos194] GPR64:%vreg1132 GPR64common:%vreg1133
6560B		%vreg1125<def> = MOVi64imm 4; GPR64:%vreg1125
6576B		%vreg1126<def> = MADDXrrr %vreg1132, %vreg1125, %XZR; GPR64:%vreg1126,%vreg1132,%vreg1125
6592B		%vreg1127<def> = ADDXrr %vreg1123, %vreg1126; GPR64common:%vreg1127,%vreg1123 GPR64:%vreg1126
6608B		%vreg1121<def> = LDRWui %vreg1127, 0; mem:LD4[%arrayidx196] GPR32:%vreg1121 GPR64common:%vreg1127
6624B		%vreg1119<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1119
6640B		STRWui %vreg1121, %vreg1119, 6; mem:ST4[%rNToGo197] GPR32:%vreg1121 GPR64common:%vreg1119
6656B		%vreg1116<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1116
6672B		%vreg1115<def> = LDRWui %vreg1116, 7; mem:LD4[%rTPos198] GPR32common:%vreg1115 GPR64common:%vreg1116
6688B		%vreg1114<def> = ADDWri %vreg1115, 1, 0; GPR32common:%vreg1114,%vreg1115
6704B		STRWui %vreg1114, %vreg1116, 7; mem:ST4[%rTPos198] GPR32common:%vreg1114 GPR64common:%vreg1116
6720B		%vreg1110<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1110
6736B		%vreg1109<def> = LDRWui %vreg1110, 7; mem:LD4[%rTPos200] GPR32common:%vreg1109 GPR64common:%vreg1110
6752B		%WZR<def> = SUBSWri %vreg1109, 512, 0, %NZCV<imp-def>; GPR32common:%vreg1109
6768B		Bcc 1, <BB#33>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#33 BB#32

6784B	BB#32: derived from LLVM BB %if.then.203
	    Predecessors according to CFG: BB#31
6800B		%vreg1135<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1135
6816B		STRWui %WZR, %vreg1135, 7; mem:ST4[%rTPos204] GPR64common:%vreg1135
	    Successors according to CFG: BB#33

6832B	BB#33: derived from LLVM BB %if.end.205
	    Predecessors according to CFG: BB#31 BB#32
6848B		B <BB#34>
	    Successors according to CFG: BB#34

6864B	BB#34: derived from LLVM BB %if.end.206
	    Predecessors according to CFG: BB#30 BB#33
6880B		%vreg1164<def> = MOVi32imm 1; GPR32:%vreg1164
6896B		%vreg1165<def> = COPY %WZR; GPR32:%vreg1165
6912B		%vreg1175<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1175
6928B		%vreg1174<def> = LDRWui %vreg1175, 6; mem:LD4[%rNToGo207] GPR32common:%vreg1174 GPR64common:%vreg1175
6944B		%vreg1173<def> = SUBWri %vreg1174, 1, 0; GPR32common:%vreg1173,%vreg1174
6960B		STRWui %vreg1173, %vreg1175, 6; mem:ST4[%rNToGo207] GPR32common:%vreg1173 GPR64common:%vreg1175
6976B		%vreg1169<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1169
6992B		%vreg1168<def> = LDRWui %vreg1169, 6; mem:LD4[%rNToGo209] GPR32common:%vreg1168 GPR64common:%vreg1169
7008B		%WZR<def> = SUBSWri %vreg1168, 1, 0, %NZCV<imp-def>; GPR32common:%vreg1168
7024B		%vreg1166<def> = CSELWr %vreg1164, %vreg1165, 0, %NZCV<imp-use,kill>; GPR32:%vreg1166,%vreg1164,%vreg1165
7040B		%vreg1162<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg1162
7056B		%vreg1159<def> = EORWrr %vreg1162, %vreg1166; GPR32:%vreg1159,%vreg1162,%vreg1166
7072B		%vreg1156<def> = COPY %vreg1159; GPR32:%vreg1156,%vreg1159
7088B		STRBBui %vreg1156, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg1156
7104B		%vreg1153<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1153
7120B		%vreg1152<def> = LDRWui %vreg1153, 273; mem:LD4[%nblock_used216] GPR32common:%vreg1152 GPR64common:%vreg1153
7136B		%vreg1151<def> = ADDWri %vreg1152, 1, 0; GPR32common:%vreg1151,%vreg1152
7152B		STRWui %vreg1151, %vreg1153, 273; mem:ST4[%nblock_used216] GPR32common:%vreg1151 GPR64common:%vreg1153
7168B		%vreg1147<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1147
7184B		%vreg1146<def> = LDRWui %vreg1147, 273; mem:LD4[%nblock_used218] GPR32:%vreg1146 GPR64common:%vreg1147
7200B		%vreg1144<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg1144
7216B		%vreg1141<def> = MOVi64imm 64080; GPR64:%vreg1141
7232B		%vreg1142<def> = ADDXrr %vreg1144, %vreg1141; GPR64common:%vreg1142 GPR64:%vreg1144,%vreg1141
7248B		%vreg1143<def> = LDRWui %vreg1142, 0; mem:LD4[%save_nblock219] GPR32common:%vreg1143 GPR64common:%vreg1142
7264B		%vreg1139<def> = ADDWri %vreg1143, 1, 0; GPR32common:%vreg1139,%vreg1143
7280B		%WZR<def> = SUBSWrr %vreg1146, %vreg1139, %NZCV<imp-def>; GPR32:%vreg1146 GPR32common:%vreg1139
7296B		Bcc 1, <BB#36>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#36 BB#35

7312B	BB#35: derived from LLVM BB %if.then.223
	    Predecessors according to CFG: BB#34
7328B		B <BB#2>
	    Successors according to CFG: BB#2

7344B	BB#36: derived from LLVM BB %if.end.224
	    Predecessors according to CFG: BB#34
7360B		%vreg1183<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg1183
7376B		%vreg1180<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1180
7392B		%vreg1179<def> = LDRWui %vreg1180, 16; mem:LD4[%k0226] GPR32:%vreg1179 GPR64common:%vreg1180
7408B		%WZR<def> = SUBSWrr %vreg1183, %vreg1179, %NZCV<imp-def>; GPR32:%vreg1183,%vreg1179
7424B		Bcc 0, <BB#38>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#38 BB#37

7440B	BB#37: derived from LLVM BB %if.then.229
	    Predecessors according to CFG: BB#36
7456B		%vreg1451<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg1451
7472B		%vreg1448<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1448
7488B		STRWui %vreg1451, %vreg1448, 16; mem:ST4[%k0231] GPR32:%vreg1451 GPR64common:%vreg1448
7504B		B <BB#2>
	    Successors according to CFG: BB#2

7520B	BB#38: derived from LLVM BB %if.end.232
	    Predecessors according to CFG: BB#36
7536B		%vreg1254<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1254
7552B		%vreg1253<def> = LDRWui %vreg1254, 15; mem:LD4[%tPos233] GPR32:%vreg1253 GPR64common:%vreg1254
7568B		%vreg1251<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1251
7584B		%vreg1250<def> = ADDXri %vreg1251, 1096, 0; GPR64sp:%vreg1250 GPR64common:%vreg1251
7600B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
7616B		%W0<def> = COPY %vreg1253; GPR32:%vreg1253
7632B		%X1<def> = COPY %vreg1250; GPR64sp:%vreg1250
7648B		BL <ga:@BZ2_indexIntoF>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use,kill>, %W0<imp-def>
7664B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
7680B		%vreg1247<def> = COPY %W0; GPR32all:%vreg1247
7696B		%vreg1199<def> = MOVi32imm 4; GPR32:%vreg1199
7712B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
7728B		STACKMAP 4, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
7744B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
7760B		%vreg1244<def> = COPY %vreg1247; GPR32:%vreg1244 GPR32all:%vreg1247
7776B		STRBBui %vreg1244, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg1244
7792B		%vreg1241<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1241
7808B		%vreg1239<def> = LDRWui %vreg1241, 15; mem:LD4[%tPos238] GPR32:%vreg1239 GPR64common:%vreg1241
7824B		%vreg1240<def> = SUBREG_TO_REG 0, %vreg1239, 15; GPR64:%vreg1240 GPR32:%vreg1239
7840B		%vreg1234<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1234
7856B		%vreg1233<def> = LDRXui %vreg1234, 395; mem:LD8[%ll16240] GPR64:%vreg1233 GPR64common:%vreg1234
7872B		%vreg1229<def> = MOVi64imm 2; GPR64:%vreg1229
7888B		%vreg1230<def> = MADDXrrr %vreg1240, %vreg1229, %XZR; GPR64:%vreg1230,%vreg1240,%vreg1229
7904B		%vreg1231<def> = ADDXrr %vreg1233, %vreg1230; GPR64common:%vreg1231 GPR64:%vreg1233,%vreg1230
7920B		%vreg1226<def> = LDRHHui %vreg1231, 0; mem:LD2[%arrayidx241] GPR32:%vreg1226 GPR64common:%vreg1231
7936B		%vreg1222<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1222
7952B		%vreg1221<def> = LDRWui %vreg1222, 15; mem:LD4[%tPos243] GPR32:%vreg1221 GPR64common:%vreg1222
7968B		%vreg1219<def> = UBFMWri %vreg1221, 1, 31; GPR32:%vreg1219,%vreg1221
7984B		%vreg1216<def> = SUBREG_TO_REG 0, %vreg1219, 15; GPR64:%vreg1216 GPR32:%vreg1219
8000B		%vreg1217<def> = UBFMXri %vreg1216, 0, 31; GPR64:%vreg1217,%vreg1216
8016B		%vreg1214<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1214
8032B		%vreg1213<def> = LDRXui %vreg1214, 396; mem:LD8[%ll4246] GPR64:%vreg1213 GPR64common:%vreg1214
8048B		%vreg1211<def> = ADDXrr %vreg1213, %vreg1217; GPR64common:%vreg1211 GPR64:%vreg1213,%vreg1217
8064B		%vreg1208<def> = LDRBBui %vreg1211, 0; mem:LD1[%arrayidx247] GPR32:%vreg1208 GPR64common:%vreg1211
8080B		%vreg1204<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1204
8096B		%vreg1203<def> = LDRWui %vreg1204, 15; mem:LD4[%tPos249] GPR32:%vreg1203 GPR64common:%vreg1204
8112B		%vreg1201<def> = ANDWrs %vreg1199, %vreg1203, 2; GPR32:%vreg1201,%vreg1199,%vreg1203
8128B		%vreg1198<def> = LSRVWr %vreg1208, %vreg1201; GPR32:%vreg1198,%vreg1208,%vreg1201
8144B		%vreg1195<def> = ANDWri %vreg1198, 3; GPR32common:%vreg1195 GPR32:%vreg1198
8160B		%vreg1193<def> = ORRWrs %vreg1226, %vreg1195, 16; GPR32:%vreg1193,%vreg1226 GPR32common:%vreg1195
8176B		%vreg1190<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1190
8192B		STRWui %vreg1193, %vreg1190, 15; mem:ST4[%tPos256] GPR32:%vreg1193 GPR64common:%vreg1190
8208B		%vreg1187<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1187
8224B		%vreg1186<def> = LDRWui %vreg1187, 6; mem:LD4[%rNToGo257] GPR32:%vreg1186 GPR64common:%vreg1187
8240B		CBNZW %vreg1186, <BB#42>; GPR32:%vreg1186
	    Successors according to CFG: BB#42 BB#39

8256B	BB#39: derived from LLVM BB %if.then.260
	    Predecessors according to CFG: BB#38
8272B		%vreg1270<def> = ADRP <ga:@BZ2_rNums>[TF=1]; GPR64common:%vreg1270
8288B		%vreg1271<def> = ADDXri %vreg1270, <ga:@BZ2_rNums>[TF=34], 0; GPR64common:%vreg1271,%vreg1270
8304B		%vreg1281<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1281
8320B		%vreg1280<def> = LDRSWui %vreg1281, 7; mem:LD4[%rTPos261] GPR64:%vreg1280 GPR64common:%vreg1281
8336B		%vreg1273<def> = MOVi64imm 4; GPR64:%vreg1273
8352B		%vreg1274<def> = MADDXrrr %vreg1280, %vreg1273, %XZR; GPR64:%vreg1274,%vreg1280,%vreg1273
8368B		%vreg1275<def> = ADDXrr %vreg1271, %vreg1274; GPR64common:%vreg1275,%vreg1271 GPR64:%vreg1274
8384B		%vreg1269<def> = LDRWui %vreg1275, 0; mem:LD4[%arrayidx263] GPR32:%vreg1269 GPR64common:%vreg1275
8400B		%vreg1267<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1267
8416B		STRWui %vreg1269, %vreg1267, 6; mem:ST4[%rNToGo264] GPR32:%vreg1269 GPR64common:%vreg1267
8432B		%vreg1264<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1264
8448B		%vreg1263<def> = LDRWui %vreg1264, 7; mem:LD4[%rTPos265] GPR32common:%vreg1263 GPR64common:%vreg1264
8464B		%vreg1262<def> = ADDWri %vreg1263, 1, 0; GPR32common:%vreg1262,%vreg1263
8480B		STRWui %vreg1262, %vreg1264, 7; mem:ST4[%rTPos265] GPR32common:%vreg1262 GPR64common:%vreg1264
8496B		%vreg1258<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1258
8512B		%vreg1257<def> = LDRWui %vreg1258, 7; mem:LD4[%rTPos267] GPR32common:%vreg1257 GPR64common:%vreg1258
8528B		%WZR<def> = SUBSWri %vreg1257, 512, 0, %NZCV<imp-def>; GPR32common:%vreg1257
8544B		Bcc 1, <BB#41>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#41 BB#40

8560B	BB#40: derived from LLVM BB %if.then.270
	    Predecessors according to CFG: BB#39
8576B		%vreg1283<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1283
8592B		STRWui %WZR, %vreg1283, 7; mem:ST4[%rTPos271] GPR64common:%vreg1283
	    Successors according to CFG: BB#41

8608B	BB#41: derived from LLVM BB %if.end.272
	    Predecessors according to CFG: BB#39 BB#40
8624B		B <BB#42>
	    Successors according to CFG: BB#42

8640B	BB#42: derived from LLVM BB %if.end.273
	    Predecessors according to CFG: BB#38 BB#41
8656B		%vreg1379<def> = MOVi32imm 1; GPR32:%vreg1379
8672B		%vreg1380<def> = COPY %WZR; GPR32:%vreg1380
8688B		%vreg1390<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1390
8704B		%vreg1389<def> = LDRWui %vreg1390, 6; mem:LD4[%rNToGo274] GPR32common:%vreg1389 GPR64common:%vreg1390
8720B		%vreg1388<def> = SUBWri %vreg1389, 1, 0; GPR32common:%vreg1388,%vreg1389
8736B		STRWui %vreg1388, %vreg1390, 6; mem:ST4[%rNToGo274] GPR32common:%vreg1388 GPR64common:%vreg1390
8752B		%vreg1384<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1384
8768B		%vreg1383<def> = LDRWui %vreg1384, 6; mem:LD4[%rNToGo276] GPR32common:%vreg1383 GPR64common:%vreg1384
8784B		%WZR<def> = SUBSWri %vreg1383, 1, 0, %NZCV<imp-def>; GPR32common:%vreg1383
8800B		%vreg1381<def> = CSELWr %vreg1379, %vreg1380, 0, %NZCV<imp-use,kill>; GPR32:%vreg1381,%vreg1379,%vreg1380
8816B		%vreg1377<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg1377
8832B		%vreg1374<def> = EORWrr %vreg1377, %vreg1381; GPR32:%vreg1374,%vreg1377,%vreg1381
8848B		%vreg1371<def> = COPY %vreg1374; GPR32:%vreg1371,%vreg1374
8864B		STRBBui %vreg1371, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg1371
8880B		%vreg1368<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1368
8896B		%vreg1367<def> = LDRWui %vreg1368, 273; mem:LD4[%nblock_used283] GPR32common:%vreg1367 GPR64common:%vreg1368
8912B		%vreg1366<def> = ADDWri %vreg1367, 1, 0; GPR32common:%vreg1366,%vreg1367
8928B		STRWui %vreg1366, %vreg1368, 273; mem:ST4[%nblock_used283] GPR32common:%vreg1366 GPR64common:%vreg1368
8944B		%vreg1362<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32common:%vreg1362
8960B		%vreg1359<def> = ADDWri %vreg1362, 4, 0; GPR32common:%vreg1359,%vreg1362
8976B		%vreg1357<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1357
8992B		STRWui %vreg1359, %vreg1357, 4; mem:ST4[%state_out_len287] GPR32common:%vreg1359 GPR64common:%vreg1357
9008B		%vreg1354<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1354
9024B		%vreg1353<def> = LDRWui %vreg1354, 15; mem:LD4[%tPos288] GPR32:%vreg1353 GPR64common:%vreg1354
9040B		%vreg1351<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1351
9056B		%vreg1350<def> = ADDXri %vreg1351, 1096, 0; GPR64sp:%vreg1350 GPR64common:%vreg1351
9072B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
9088B		%W0<def> = COPY %vreg1353; GPR32:%vreg1353
9104B		%X1<def> = COPY %vreg1350; GPR64sp:%vreg1350
9120B		BL <ga:@BZ2_indexIntoF>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use,kill>, %W0<imp-def>
9136B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
9152B		%vreg1347<def> = COPY %W0; GPR32:%vreg1347
9168B		%vreg1299<def> = MOVi32imm 4; GPR32:%vreg1299
9184B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
9200B		STACKMAP 5, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
9216B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
9232B		%vreg1344<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1344
9248B		STRWui %vreg1347, %vreg1344, 16; mem:ST4[%k0292] GPR32:%vreg1347 GPR64common:%vreg1344
9264B		%vreg1341<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1341
9280B		%vreg1339<def> = LDRWui %vreg1341, 15; mem:LD4[%tPos293] GPR32:%vreg1339 GPR64common:%vreg1341
9296B		%vreg1340<def> = SUBREG_TO_REG 0, %vreg1339, 15; GPR64:%vreg1340 GPR32:%vreg1339
9312B		%vreg1334<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1334
9328B		%vreg1333<def> = LDRXui %vreg1334, 395; mem:LD8[%ll16295] GPR64:%vreg1333 GPR64common:%vreg1334
9344B		%vreg1329<def> = MOVi64imm 2; GPR64:%vreg1329
9360B		%vreg1330<def> = MADDXrrr %vreg1340, %vreg1329, %XZR; GPR64:%vreg1330,%vreg1340,%vreg1329
9376B		%vreg1331<def> = ADDXrr %vreg1333, %vreg1330; GPR64common:%vreg1331 GPR64:%vreg1333,%vreg1330
9392B		%vreg1326<def> = LDRHHui %vreg1331, 0; mem:LD2[%arrayidx296] GPR32:%vreg1326 GPR64common:%vreg1331
9408B		%vreg1322<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1322
9424B		%vreg1321<def> = LDRWui %vreg1322, 15; mem:LD4[%tPos298] GPR32:%vreg1321 GPR64common:%vreg1322
9440B		%vreg1319<def> = UBFMWri %vreg1321, 1, 31; GPR32:%vreg1319,%vreg1321
9456B		%vreg1316<def> = SUBREG_TO_REG 0, %vreg1319, 15; GPR64:%vreg1316 GPR32:%vreg1319
9472B		%vreg1317<def> = UBFMXri %vreg1316, 0, 31; GPR64:%vreg1317,%vreg1316
9488B		%vreg1314<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1314
9504B		%vreg1313<def> = LDRXui %vreg1314, 396; mem:LD8[%ll4301] GPR64:%vreg1313 GPR64common:%vreg1314
9520B		%vreg1311<def> = ADDXrr %vreg1313, %vreg1317; GPR64common:%vreg1311 GPR64:%vreg1313,%vreg1317
9536B		%vreg1308<def> = LDRBBui %vreg1311, 0; mem:LD1[%arrayidx302] GPR32:%vreg1308 GPR64common:%vreg1311
9552B		%vreg1304<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1304
9568B		%vreg1303<def> = LDRWui %vreg1304, 15; mem:LD4[%tPos304] GPR32:%vreg1303 GPR64common:%vreg1304
9584B		%vreg1301<def> = ANDWrs %vreg1299, %vreg1303, 2; GPR32:%vreg1301,%vreg1299,%vreg1303
9600B		%vreg1298<def> = LSRVWr %vreg1308, %vreg1301; GPR32:%vreg1298,%vreg1308,%vreg1301
9616B		%vreg1295<def> = ANDWri %vreg1298, 3; GPR32common:%vreg1295 GPR32:%vreg1298
9632B		%vreg1293<def> = ORRWrs %vreg1326, %vreg1295, 16; GPR32:%vreg1293,%vreg1326 GPR32common:%vreg1295
9648B		%vreg1290<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1290
9664B		STRWui %vreg1293, %vreg1290, 15; mem:ST4[%tPos311] GPR32:%vreg1293 GPR64common:%vreg1290
9680B		%vreg1287<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1287
9696B		%vreg1286<def> = LDRWui %vreg1287, 6; mem:LD4[%rNToGo312] GPR32:%vreg1286 GPR64common:%vreg1287
9712B		CBNZW %vreg1286, <BB#46>; GPR32:%vreg1286
	    Successors according to CFG: BB#46 BB#43

9728B	BB#43: derived from LLVM BB %if.then.315
	    Predecessors according to CFG: BB#42
9744B		%vreg1406<def> = ADRP <ga:@BZ2_rNums>[TF=1]; GPR64common:%vreg1406
9760B		%vreg1407<def> = ADDXri %vreg1406, <ga:@BZ2_rNums>[TF=34], 0; GPR64common:%vreg1407,%vreg1406
9776B		%vreg1417<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1417
9792B		%vreg1416<def> = LDRSWui %vreg1417, 7; mem:LD4[%rTPos316] GPR64:%vreg1416 GPR64common:%vreg1417
9808B		%vreg1409<def> = MOVi64imm 4; GPR64:%vreg1409
9824B		%vreg1410<def> = MADDXrrr %vreg1416, %vreg1409, %XZR; GPR64:%vreg1410,%vreg1416,%vreg1409
9840B		%vreg1411<def> = ADDXrr %vreg1407, %vreg1410; GPR64common:%vreg1411,%vreg1407 GPR64:%vreg1410
9856B		%vreg1405<def> = LDRWui %vreg1411, 0; mem:LD4[%arrayidx318] GPR32:%vreg1405 GPR64common:%vreg1411
9872B		%vreg1403<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1403
9888B		STRWui %vreg1405, %vreg1403, 6; mem:ST4[%rNToGo319] GPR32:%vreg1405 GPR64common:%vreg1403
9904B		%vreg1400<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1400
9920B		%vreg1399<def> = LDRWui %vreg1400, 7; mem:LD4[%rTPos320] GPR32common:%vreg1399 GPR64common:%vreg1400
9936B		%vreg1398<def> = ADDWri %vreg1399, 1, 0; GPR32common:%vreg1398,%vreg1399
9952B		STRWui %vreg1398, %vreg1400, 7; mem:ST4[%rTPos320] GPR32common:%vreg1398 GPR64common:%vreg1400
9968B		%vreg1394<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1394
9984B		%vreg1393<def> = LDRWui %vreg1394, 7; mem:LD4[%rTPos322] GPR32common:%vreg1393 GPR64common:%vreg1394
10000B		%WZR<def> = SUBSWri %vreg1393, 512, 0, %NZCV<imp-def>; GPR32common:%vreg1393
10016B		Bcc 1, <BB#45>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#45 BB#44

10032B	BB#44: derived from LLVM BB %if.then.325
	    Predecessors according to CFG: BB#43
10048B		%vreg1419<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1419
10064B		STRWui %WZR, %vreg1419, 7; mem:ST4[%rTPos326] GPR64common:%vreg1419
	    Successors according to CFG: BB#45

10080B	BB#45: derived from LLVM BB %if.end.327
	    Predecessors according to CFG: BB#43 BB#44
10096B		B <BB#46>
	    Successors according to CFG: BB#46

10112B	BB#46: derived from LLVM BB %if.end.328
	    Predecessors according to CFG: BB#42 BB#45
10128B		%vreg1434<def> = MOVi32imm 1; GPR32:%vreg1434
10144B		%vreg1435<def> = COPY %WZR; GPR32:%vreg1435
10160B		%vreg1445<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1445
10176B		%vreg1444<def> = LDRWui %vreg1445, 6; mem:LD4[%rNToGo329] GPR32common:%vreg1444 GPR64common:%vreg1445
10192B		%vreg1443<def> = SUBWri %vreg1444, 1, 0; GPR32common:%vreg1443,%vreg1444
10208B		STRWui %vreg1443, %vreg1445, 6; mem:ST4[%rNToGo329] GPR32common:%vreg1443 GPR64common:%vreg1445
10224B		%vreg1439<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1439
10240B		%vreg1438<def> = LDRWui %vreg1439, 6; mem:LD4[%rNToGo331] GPR32common:%vreg1438 GPR64common:%vreg1439
10256B		%WZR<def> = SUBSWri %vreg1438, 1, 0, %NZCV<imp-def>; GPR32common:%vreg1438
10272B		%vreg1436<def> = CSELWr %vreg1434, %vreg1435, 0, %NZCV<imp-use,kill>; GPR32:%vreg1436,%vreg1434,%vreg1435
10288B		%vreg1432<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1432
10304B		%vreg1431<def> = LDRWui %vreg1432, 16; mem:LD4[%k0335] GPR32:%vreg1431 GPR64common:%vreg1432
10320B		%vreg1430<def> = EORWrr %vreg1431, %vreg1436; GPR32:%vreg1430,%vreg1431,%vreg1436
10336B		STRWui %vreg1430, %vreg1432, 16; mem:ST4[%k0335] GPR32:%vreg1430 GPR64common:%vreg1432
10352B		%vreg1425<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1425
10368B		%vreg1424<def> = LDRWui %vreg1425, 273; mem:LD4[%nblock_used337] GPR32common:%vreg1424 GPR64common:%vreg1425
10384B		%vreg1423<def> = ADDWri %vreg1424, 1, 0; GPR32common:%vreg1423,%vreg1424
10400B		STRWui %vreg1423, %vreg1425, 273; mem:ST4[%nblock_used337] GPR32common:%vreg1423 GPR64common:%vreg1425
10416B		B <BB#2>
	    Successors according to CFG: BB#2

10432B	BB#47: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#0
10448B		B <BB#48>
	    Successors according to CFG: BB#48

10464B	BB#48: derived from LLVM BB %while.body.339
	    Predecessors according to CFG: BB#47 BB#72 BB#71 BB#69 BB#67 BB#65 BB#63 BB#61
10480B		B <BB#49>
	    Successors according to CFG: BB#49

10496B	BB#49: derived from LLVM BB %while.body.341
	    Predecessors according to CFG: BB#48 BB#55
10512B		%vreg17<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg17
10528B		%vreg16<def> = LDRXui %vreg17, 0; mem:LD8[%strm342] GPR64common:%vreg16,%vreg17
10544B		%vreg14<def> = LDRWui %vreg16, 8; mem:LD4[%avail_out343] GPR32:%vreg14 GPR64common:%vreg16
10560B		CBNZW %vreg14, <BB#51>; GPR32:%vreg14
	    Successors according to CFG: BB#51 BB#50

10576B	BB#50: derived from LLVM BB %if.then.346
	    Predecessors according to CFG: BB#49
10592B		STRBBui %WZR, <fi#0>, 0; mem:ST1[FixedStack0]
10608B		B <BB#73>
	    Successors according to CFG: BB#73

10624B	BB#51: derived from LLVM BB %if.end.347
	    Predecessors according to CFG: BB#49
10640B		%vreg21<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg21
10656B		%vreg20<def> = LDRWui %vreg21, 4; mem:LD4[%state_out_len348] GPR32:%vreg20 GPR64common:%vreg21
10672B		CBNZW %vreg20, <BB#53>; GPR32:%vreg20
	    Successors according to CFG: BB#53 BB#52

10688B	BB#52: derived from LLVM BB %if.then.351
	    Predecessors according to CFG: BB#51
10704B		B <BB#56>
	    Successors according to CFG: BB#56

10720B	BB#53: derived from LLVM BB %if.end.352
	    Predecessors according to CFG: BB#51
10736B		%vreg66<def> = ADRP <ga:@BZ2_crc32Table>[TF=1]; GPR64common:%vreg66
10752B		%vreg67<def> = ADDXri %vreg66, <ga:@BZ2_crc32Table>[TF=34], 0; GPR64common:%vreg67,%vreg66
10768B		%vreg100<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg100
10784B		%vreg99<def> = LDRBBui %vreg100, 12; mem:LD1[%state_out_ch353] GPR32:%vreg99 GPR64common:%vreg100
10800B		%vreg97<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg97
10816B		%vreg96<def> = LDRXui %vreg97, 0; mem:LD8[%strm354] GPR64common:%vreg96,%vreg97
10832B		%vreg94<def> = LDRXui %vreg96, 3; mem:LD8[%next_out355] GPR64common:%vreg94,%vreg96
10848B		STRBBui %vreg99, %vreg94, 0; mem:ST1[%261] GPR32:%vreg99 GPR64common:%vreg94
10864B		%vreg90<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg90
10880B		%vreg89<def> = LDRWui %vreg90, 796; mem:LD4[%calculatedBlockCRC356] GPR32:%vreg89 GPR64common:%vreg90
10896B		%vreg87<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg87
10912B		%vreg86<def> = LDRWui %vreg87, 796; mem:LD4[%calculatedBlockCRC358] GPR32:%vreg86 GPR64common:%vreg87
10928B		%vreg84<def> = UBFMWri %vreg86, 24, 31; GPR32:%vreg84,%vreg86
10944B		%vreg82<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg82
10960B		%vreg81<def> = LDRBBui %vreg82, 12; mem:LD1[%state_out_ch360] GPR32:%vreg81 GPR64common:%vreg82
10976B		%vreg77<def> = EORWrr %vreg84, %vreg81; GPR32:%vreg77,%vreg84,%vreg81
10992B		%vreg73<def> = SUBREG_TO_REG 0, %vreg77, 15; GPR64:%vreg73 GPR32:%vreg77
11008B		%vreg74<def> = UBFMXri %vreg73, 0, 31; GPR64:%vreg74,%vreg73
11024B		%vreg69<def> = MOVi64imm 4; GPR64:%vreg69
11040B		%vreg70<def> = MADDXrrr %vreg74, %vreg69, %XZR; GPR64:%vreg70,%vreg74,%vreg69
11056B		%vreg71<def> = ADDXrr %vreg67, %vreg70; GPR64common:%vreg71,%vreg67 GPR64:%vreg70
11072B		%vreg65<def> = LDRWui %vreg71, 0; mem:LD4[%arrayidx364] GPR32:%vreg65 GPR64common:%vreg71
11088B		%vreg63<def> = EORWrs %vreg65, %vreg89, 8; GPR32:%vreg63,%vreg65,%vreg89
11104B		%vreg60<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg60
11120B		STRWui %vreg63, %vreg60, 796; mem:ST4[%calculatedBlockCRC366] GPR32:%vreg63 GPR64common:%vreg60
11136B		%vreg57<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg57
11152B		%vreg56<def> = LDRWui %vreg57, 4; mem:LD4[%state_out_len367] GPR32common:%vreg56 GPR64common:%vreg57
11168B		%vreg55<def> = SUBWri %vreg56, 1, 0; GPR32common:%vreg55,%vreg56
11184B		STRWui %vreg55, %vreg57, 4; mem:ST4[%state_out_len367] GPR32common:%vreg55 GPR64common:%vreg57
11200B		%vreg51<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg51
11216B		%vreg50<def> = LDRXui %vreg51, 0; mem:LD8[%strm369] GPR64common:%vreg50,%vreg51
11232B		%vreg48<def> = LDRXui %vreg50, 3; mem:LD8[%next_out370] GPR64common:%vreg48,%vreg50
11248B		%vreg47<def> = ADDXri %vreg48, 1, 0; GPR64common:%vreg47,%vreg48
11264B		STRXui %vreg47, %vreg50, 3; mem:ST8[%next_out370] GPR64common:%vreg47,%vreg50
11280B		%vreg43<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg43
11296B		%vreg42<def> = LDRXui %vreg43, 0; mem:LD8[%strm372] GPR64common:%vreg42,%vreg43
11312B		%vreg40<def> = LDRWui %vreg42, 8; mem:LD4[%avail_out373] GPR32common:%vreg40 GPR64common:%vreg42
11328B		%vreg39<def> = SUBWri %vreg40, 1, 0; GPR32common:%vreg39,%vreg40
11344B		STRWui %vreg39, %vreg42, 8; mem:ST4[%avail_out373] GPR32common:%vreg39 GPR64common:%vreg42
11360B		%vreg35<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg35
11376B		%vreg34<def> = LDRXui %vreg35, 0; mem:LD8[%strm375] GPR64common:%vreg34,%vreg35
11392B		%vreg32<def> = LDRWui %vreg34, 9; mem:LD4[%total_out_lo32376] GPR32common:%vreg32 GPR64common:%vreg34
11408B		%vreg31<def> = ADDWri %vreg32, 1, 0; GPR32common:%vreg31,%vreg32
11424B		STRWui %vreg31, %vreg34, 9; mem:ST4[%total_out_lo32376] GPR32common:%vreg31 GPR64common:%vreg34
11440B		%vreg27<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg27
11456B		%vreg26<def> = LDRXui %vreg27, 0; mem:LD8[%strm378] GPR64common:%vreg26,%vreg27
11472B		%vreg24<def> = LDRWui %vreg26, 9; mem:LD4[%total_out_lo32379] GPR32:%vreg24 GPR64common:%vreg26
11488B		CBNZW %vreg24, <BB#55>; GPR32:%vreg24
	    Successors according to CFG: BB#55 BB#54

11504B	BB#54: derived from LLVM BB %if.then.382
	    Predecessors according to CFG: BB#53
11520B		%vreg108<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg108
11536B		%vreg107<def> = LDRXui %vreg108, 0; mem:LD8[%strm383] GPR64common:%vreg107,%vreg108
11552B		%vreg105<def> = LDRWui %vreg107, 10; mem:LD4[%total_out_hi32384] GPR32common:%vreg105 GPR64common:%vreg107
11568B		%vreg104<def> = ADDWri %vreg105, 1, 0; GPR32common:%vreg104,%vreg105
11584B		STRWui %vreg104, %vreg107, 10; mem:ST4[%total_out_hi32384] GPR32common:%vreg104 GPR64common:%vreg107
	    Successors according to CFG: BB#55

11600B	BB#55: derived from LLVM BB %if.end.386
	    Predecessors according to CFG: BB#53 BB#54
11616B		B <BB#49>
	    Successors according to CFG: BB#49

11632B	BB#56: derived from LLVM BB %while.end.387
	    Predecessors according to CFG: BB#52
11648B		%vreg120<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg120
11664B		%vreg119<def> = LDRWui %vreg120, 273; mem:LD4[%nblock_used388] GPR32:%vreg119 GPR64common:%vreg120
11680B		%vreg117<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg117
11696B		%vreg114<def> = MOVi64imm 64080; GPR64:%vreg114
11712B		%vreg115<def> = ADDXrr %vreg117, %vreg114; GPR64common:%vreg115 GPR64:%vreg117,%vreg114
11728B		%vreg116<def> = LDRWui %vreg115, 0; mem:LD4[%save_nblock389] GPR32common:%vreg116 GPR64common:%vreg115
11744B		%vreg112<def> = ADDWri %vreg116, 1, 0; GPR32common:%vreg112,%vreg116
11760B		%WZR<def> = SUBSWrr %vreg119, %vreg112, %NZCV<imp-def>; GPR32:%vreg119 GPR32common:%vreg112
11776B		Bcc 1, <BB#58>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#58 BB#57

11792B	BB#57: derived from LLVM BB %if.then.393
	    Predecessors according to CFG: BB#56
11808B		STRBBui %WZR, <fi#0>, 0; mem:ST1[FixedStack0]
11824B		B <BB#73>
	    Successors according to CFG: BB#73

11840B	BB#58: derived from LLVM BB %if.end.394
	    Predecessors according to CFG: BB#56
11856B		%vreg132<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg132
11872B		%vreg131<def> = LDRWui %vreg132, 273; mem:LD4[%nblock_used395] GPR32:%vreg131 GPR64common:%vreg132
11888B		%vreg129<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg129
11904B		%vreg126<def> = MOVi64imm 64080; GPR64:%vreg126
11920B		%vreg127<def> = ADDXrr %vreg129, %vreg126; GPR64common:%vreg127 GPR64:%vreg129,%vreg126
11936B		%vreg128<def> = LDRWui %vreg127, 0; mem:LD4[%save_nblock396] GPR32common:%vreg128 GPR64common:%vreg127
11952B		%vreg124<def> = ADDWri %vreg128, 1, 0; GPR32common:%vreg124,%vreg128
11968B		%WZR<def> = SUBSWrr %vreg131, %vreg124, %NZCV<imp-def>; GPR32:%vreg131 GPR32common:%vreg124
11984B		Bcc 13, <BB#60>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#60 BB#59

12000B	BB#59: derived from LLVM BB %if.then.400
	    Predecessors according to CFG: BB#58
12016B		%vreg601<def> = MOVi32imm 1; GPR32:%vreg601
12032B		STRBBui %vreg601, <fi#0>, 0; mem:ST1[FixedStack0] GPR32:%vreg601
12048B		B <BB#73>
	    Successors according to CFG: BB#73

12064B	BB#60: derived from LLVM BB %if.end.401
	    Predecessors according to CFG: BB#58
12080B		%vreg226<def> = MOVi32imm 1; GPR32:%vreg226
12096B		%vreg228<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg228
12112B		STRWui %vreg226, %vreg228, 4; mem:ST4[%state_out_len402] GPR32:%vreg226 GPR64common:%vreg228
12128B		%vreg225<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg225
12144B		%vreg224<def> = LDRWui %vreg225, 16; mem:LD4[%k0403] GPR32:%vreg224 GPR64common:%vreg225
12160B		%vreg222<def> = COPY %vreg224; GPR32:%vreg222,%vreg224
12176B		%vreg220<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg220
12192B		STRBBui %vreg222, %vreg220, 12; mem:ST1[%state_out_ch405] GPR32:%vreg222 GPR64common:%vreg220
12208B		%vreg217<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg217
12224B		%vreg216<def> = LDRWui %vreg217, 15; mem:LD4[%tPos406] GPR32:%vreg216 GPR64common:%vreg217
12240B		%vreg214<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg214
12256B		%vreg213<def> = ADDXri %vreg214, 1096, 0; GPR64sp:%vreg213 GPR64common:%vreg214
12272B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
12288B		%W0<def> = COPY %vreg216; GPR32:%vreg216
12304B		%X1<def> = COPY %vreg213; GPR64sp:%vreg213
12320B		BL <ga:@BZ2_indexIntoF>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use,kill>, %W0<imp-def>
12336B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
12352B		%vreg210<def> = COPY %W0; GPR32all:%vreg210
12368B		%vreg162<def> = MOVi32imm 4; GPR32:%vreg162
12384B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
12400B		STACKMAP 6, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
12416B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
12432B		%vreg207<def> = COPY %vreg210; GPR32:%vreg207 GPR32all:%vreg210
12448B		STRBBui %vreg207, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg207
12464B		%vreg204<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg204
12480B		%vreg202<def> = LDRWui %vreg204, 15; mem:LD4[%tPos411] GPR32:%vreg202 GPR64common:%vreg204
12496B		%vreg203<def> = SUBREG_TO_REG 0, %vreg202, 15; GPR64:%vreg203 GPR32:%vreg202
12512B		%vreg197<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg197
12528B		%vreg196<def> = LDRXui %vreg197, 395; mem:LD8[%ll16413] GPR64:%vreg196 GPR64common:%vreg197
12544B		%vreg192<def> = MOVi64imm 2; GPR64:%vreg192
12560B		%vreg193<def> = MADDXrrr %vreg203, %vreg192, %XZR; GPR64:%vreg193,%vreg203,%vreg192
12576B		%vreg194<def> = ADDXrr %vreg196, %vreg193; GPR64common:%vreg194 GPR64:%vreg196,%vreg193
12592B		%vreg189<def> = LDRHHui %vreg194, 0; mem:LD2[%arrayidx414] GPR32:%vreg189 GPR64common:%vreg194
12608B		%vreg185<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg185
12624B		%vreg184<def> = LDRWui %vreg185, 15; mem:LD4[%tPos416] GPR32:%vreg184 GPR64common:%vreg185
12640B		%vreg182<def> = UBFMWri %vreg184, 1, 31; GPR32:%vreg182,%vreg184
12656B		%vreg179<def> = SUBREG_TO_REG 0, %vreg182, 15; GPR64:%vreg179 GPR32:%vreg182
12672B		%vreg180<def> = UBFMXri %vreg179, 0, 31; GPR64:%vreg180,%vreg179
12688B		%vreg177<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg177
12704B		%vreg176<def> = LDRXui %vreg177, 396; mem:LD8[%ll4419] GPR64:%vreg176 GPR64common:%vreg177
12720B		%vreg174<def> = ADDXrr %vreg176, %vreg180; GPR64common:%vreg174 GPR64:%vreg176,%vreg180
12736B		%vreg171<def> = LDRBBui %vreg174, 0; mem:LD1[%arrayidx420] GPR32:%vreg171 GPR64common:%vreg174
12752B		%vreg167<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg167
12768B		%vreg166<def> = LDRWui %vreg167, 15; mem:LD4[%tPos422] GPR32:%vreg166 GPR64common:%vreg167
12784B		%vreg164<def> = ANDWrs %vreg162, %vreg166, 2; GPR32:%vreg164,%vreg162,%vreg166
12800B		%vreg161<def> = LSRVWr %vreg171, %vreg164; GPR32:%vreg161,%vreg171,%vreg164
12816B		%vreg158<def> = ANDWri %vreg161, 3; GPR32common:%vreg158 GPR32:%vreg161
12832B		%vreg156<def> = ORRWrs %vreg189, %vreg158, 16; GPR32:%vreg156,%vreg189 GPR32common:%vreg158
12848B		%vreg153<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg153
12864B		STRWui %vreg156, %vreg153, 15; mem:ST4[%tPos429] GPR32:%vreg156 GPR64common:%vreg153
12880B		%vreg150<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg150
12896B		%vreg149<def> = LDRWui %vreg150, 273; mem:LD4[%nblock_used430] GPR32common:%vreg149 GPR64common:%vreg150
12912B		%vreg148<def> = ADDWri %vreg149, 1, 0; GPR32common:%vreg148,%vreg149
12928B		STRWui %vreg148, %vreg150, 273; mem:ST4[%nblock_used430] GPR32common:%vreg148 GPR64common:%vreg150
12944B		%vreg144<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg144
12960B		%vreg143<def> = LDRWui %vreg144, 273; mem:LD4[%nblock_used432] GPR32:%vreg143 GPR64common:%vreg144
12976B		%vreg141<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg141
12992B		%vreg138<def> = MOVi64imm 64080; GPR64:%vreg138
13008B		%vreg139<def> = ADDXrr %vreg141, %vreg138; GPR64common:%vreg139 GPR64:%vreg141,%vreg138
13024B		%vreg140<def> = LDRWui %vreg139, 0; mem:LD4[%save_nblock433] GPR32common:%vreg140 GPR64common:%vreg139
13040B		%vreg136<def> = ADDWri %vreg140, 1, 0; GPR32common:%vreg136,%vreg140
13056B		%WZR<def> = SUBSWrr %vreg143, %vreg136, %NZCV<imp-def>; GPR32:%vreg143 GPR32common:%vreg136
13072B		Bcc 1, <BB#62>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#62 BB#61

13088B	BB#61: derived from LLVM BB %if.then.437
	    Predecessors according to CFG: BB#60
13104B		B <BB#48>
	    Successors according to CFG: BB#48

13120B	BB#62: derived from LLVM BB %if.end.438
	    Predecessors according to CFG: BB#60
13136B		%vreg236<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg236
13152B		%vreg233<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg233
13168B		%vreg232<def> = LDRWui %vreg233, 16; mem:LD4[%k0440] GPR32:%vreg232 GPR64common:%vreg233
13184B		%WZR<def> = SUBSWrr %vreg236, %vreg232, %NZCV<imp-def>; GPR32:%vreg236,%vreg232
13200B		Bcc 0, <BB#64>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#64 BB#63

13216B	BB#63: derived from LLVM BB %if.then.443
	    Predecessors according to CFG: BB#62
13232B		%vreg600<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg600
13248B		%vreg597<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg597
13264B		STRWui %vreg600, %vreg597, 16; mem:ST4[%k0445] GPR32:%vreg600 GPR64common:%vreg597
13280B		B <BB#48>
	    Successors according to CFG: BB#48

13296B	BB#64: derived from LLVM BB %if.end.446
	    Predecessors according to CFG: BB#62
13312B		%vreg322<def> = MOVi32imm 2; GPR32:%vreg322
13328B		%vreg324<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg324
13344B		STRWui %vreg322, %vreg324, 4; mem:ST4[%state_out_len447] GPR32:%vreg322 GPR64common:%vreg324
13360B		%vreg321<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg321
13376B		%vreg320<def> = LDRWui %vreg321, 15; mem:LD4[%tPos448] GPR32:%vreg320 GPR64common:%vreg321
13392B		%vreg318<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg318
13408B		%vreg317<def> = ADDXri %vreg318, 1096, 0; GPR64sp:%vreg317 GPR64common:%vreg318
13424B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
13440B		%W0<def> = COPY %vreg320; GPR32:%vreg320
13456B		%X1<def> = COPY %vreg317; GPR64sp:%vreg317
13472B		BL <ga:@BZ2_indexIntoF>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use,kill>, %W0<imp-def>
13488B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
13504B		%vreg314<def> = COPY %W0; GPR32all:%vreg314
13520B		%vreg266<def> = MOVi32imm 4; GPR32:%vreg266
13536B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
13552B		STACKMAP 7, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
13568B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
13584B		%vreg311<def> = COPY %vreg314; GPR32:%vreg311 GPR32all:%vreg314
13600B		STRBBui %vreg311, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg311
13616B		%vreg308<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg308
13632B		%vreg306<def> = LDRWui %vreg308, 15; mem:LD4[%tPos453] GPR32:%vreg306 GPR64common:%vreg308
13648B		%vreg307<def> = SUBREG_TO_REG 0, %vreg306, 15; GPR64:%vreg307 GPR32:%vreg306
13664B		%vreg301<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg301
13680B		%vreg300<def> = LDRXui %vreg301, 395; mem:LD8[%ll16455] GPR64:%vreg300 GPR64common:%vreg301
13696B		%vreg296<def> = MOVi64imm 2; GPR64:%vreg296
13712B		%vreg297<def> = MADDXrrr %vreg307, %vreg296, %XZR; GPR64:%vreg297,%vreg307,%vreg296
13728B		%vreg298<def> = ADDXrr %vreg300, %vreg297; GPR64common:%vreg298 GPR64:%vreg300,%vreg297
13744B		%vreg293<def> = LDRHHui %vreg298, 0; mem:LD2[%arrayidx456] GPR32:%vreg293 GPR64common:%vreg298
13760B		%vreg289<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg289
13776B		%vreg288<def> = LDRWui %vreg289, 15; mem:LD4[%tPos458] GPR32:%vreg288 GPR64common:%vreg289
13792B		%vreg286<def> = UBFMWri %vreg288, 1, 31; GPR32:%vreg286,%vreg288
13808B		%vreg283<def> = SUBREG_TO_REG 0, %vreg286, 15; GPR64:%vreg283 GPR32:%vreg286
13824B		%vreg284<def> = UBFMXri %vreg283, 0, 31; GPR64:%vreg284,%vreg283
13840B		%vreg281<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg281
13856B		%vreg280<def> = LDRXui %vreg281, 396; mem:LD8[%ll4461] GPR64:%vreg280 GPR64common:%vreg281
13872B		%vreg278<def> = ADDXrr %vreg280, %vreg284; GPR64common:%vreg278 GPR64:%vreg280,%vreg284
13888B		%vreg275<def> = LDRBBui %vreg278, 0; mem:LD1[%arrayidx462] GPR32:%vreg275 GPR64common:%vreg278
13904B		%vreg271<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg271
13920B		%vreg270<def> = LDRWui %vreg271, 15; mem:LD4[%tPos464] GPR32:%vreg270 GPR64common:%vreg271
13936B		%vreg268<def> = ANDWrs %vreg266, %vreg270, 2; GPR32:%vreg268,%vreg266,%vreg270
13952B		%vreg265<def> = LSRVWr %vreg275, %vreg268; GPR32:%vreg265,%vreg275,%vreg268
13968B		%vreg262<def> = ANDWri %vreg265, 3; GPR32common:%vreg262 GPR32:%vreg265
13984B		%vreg260<def> = ORRWrs %vreg293, %vreg262, 16; GPR32:%vreg260,%vreg293 GPR32common:%vreg262
14000B		%vreg257<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg257
14016B		STRWui %vreg260, %vreg257, 15; mem:ST4[%tPos471] GPR32:%vreg260 GPR64common:%vreg257
14032B		%vreg254<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg254
14048B		%vreg253<def> = LDRWui %vreg254, 273; mem:LD4[%nblock_used472] GPR32common:%vreg253 GPR64common:%vreg254
14064B		%vreg252<def> = ADDWri %vreg253, 1, 0; GPR32common:%vreg252,%vreg253
14080B		STRWui %vreg252, %vreg254, 273; mem:ST4[%nblock_used472] GPR32common:%vreg252 GPR64common:%vreg254
14096B		%vreg248<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg248
14112B		%vreg247<def> = LDRWui %vreg248, 273; mem:LD4[%nblock_used474] GPR32:%vreg247 GPR64common:%vreg248
14128B		%vreg245<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg245
14144B		%vreg242<def> = MOVi64imm 64080; GPR64:%vreg242
14160B		%vreg243<def> = ADDXrr %vreg245, %vreg242; GPR64common:%vreg243 GPR64:%vreg245,%vreg242
14176B		%vreg244<def> = LDRWui %vreg243, 0; mem:LD4[%save_nblock475] GPR32common:%vreg244 GPR64common:%vreg243
14192B		%vreg240<def> = ADDWri %vreg244, 1, 0; GPR32common:%vreg240,%vreg244
14208B		%WZR<def> = SUBSWrr %vreg247, %vreg240, %NZCV<imp-def>; GPR32:%vreg247 GPR32common:%vreg240
14224B		Bcc 1, <BB#66>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#66 BB#65

14240B	BB#65: derived from LLVM BB %if.then.479
	    Predecessors according to CFG: BB#64
14256B		B <BB#48>
	    Successors according to CFG: BB#48

14272B	BB#66: derived from LLVM BB %if.end.480
	    Predecessors according to CFG: BB#64
14288B		%vreg332<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg332
14304B		%vreg329<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg329
14320B		%vreg328<def> = LDRWui %vreg329, 16; mem:LD4[%k0482] GPR32:%vreg328 GPR64common:%vreg329
14336B		%WZR<def> = SUBSWrr %vreg332, %vreg328, %NZCV<imp-def>; GPR32:%vreg332,%vreg328
14352B		Bcc 0, <BB#68>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#68 BB#67

14368B	BB#67: derived from LLVM BB %if.then.485
	    Predecessors according to CFG: BB#66
14384B		%vreg594<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg594
14400B		%vreg591<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg591
14416B		STRWui %vreg594, %vreg591, 16; mem:ST4[%k0487] GPR32:%vreg594 GPR64common:%vreg591
14432B		B <BB#48>
	    Successors according to CFG: BB#48

14448B	BB#68: derived from LLVM BB %if.end.488
	    Predecessors according to CFG: BB#66
14464B		%vreg418<def> = MOVi32imm 3; GPR32:%vreg418
14480B		%vreg420<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg420
14496B		STRWui %vreg418, %vreg420, 4; mem:ST4[%state_out_len489] GPR32:%vreg418 GPR64common:%vreg420
14512B		%vreg417<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg417
14528B		%vreg416<def> = LDRWui %vreg417, 15; mem:LD4[%tPos490] GPR32:%vreg416 GPR64common:%vreg417
14544B		%vreg414<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg414
14560B		%vreg413<def> = ADDXri %vreg414, 1096, 0; GPR64sp:%vreg413 GPR64common:%vreg414
14576B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
14592B		%W0<def> = COPY %vreg416; GPR32:%vreg416
14608B		%X1<def> = COPY %vreg413; GPR64sp:%vreg413
14624B		BL <ga:@BZ2_indexIntoF>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use,kill>, %W0<imp-def>
14640B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
14656B		%vreg410<def> = COPY %W0; GPR32all:%vreg410
14672B		%vreg362<def> = MOVi32imm 4; GPR32:%vreg362
14688B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
14704B		STACKMAP 8, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
14720B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
14736B		%vreg407<def> = COPY %vreg410; GPR32:%vreg407 GPR32all:%vreg410
14752B		STRBBui %vreg407, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg407
14768B		%vreg404<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg404
14784B		%vreg402<def> = LDRWui %vreg404, 15; mem:LD4[%tPos495] GPR32:%vreg402 GPR64common:%vreg404
14800B		%vreg403<def> = SUBREG_TO_REG 0, %vreg402, 15; GPR64:%vreg403 GPR32:%vreg402
14816B		%vreg397<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg397
14832B		%vreg396<def> = LDRXui %vreg397, 395; mem:LD8[%ll16497] GPR64:%vreg396 GPR64common:%vreg397
14848B		%vreg392<def> = MOVi64imm 2; GPR64:%vreg392
14864B		%vreg393<def> = MADDXrrr %vreg403, %vreg392, %XZR; GPR64:%vreg393,%vreg403,%vreg392
14880B		%vreg394<def> = ADDXrr %vreg396, %vreg393; GPR64common:%vreg394 GPR64:%vreg396,%vreg393
14896B		%vreg389<def> = LDRHHui %vreg394, 0; mem:LD2[%arrayidx498] GPR32:%vreg389 GPR64common:%vreg394
14912B		%vreg385<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg385
14928B		%vreg384<def> = LDRWui %vreg385, 15; mem:LD4[%tPos500] GPR32:%vreg384 GPR64common:%vreg385
14944B		%vreg382<def> = UBFMWri %vreg384, 1, 31; GPR32:%vreg382,%vreg384
14960B		%vreg379<def> = SUBREG_TO_REG 0, %vreg382, 15; GPR64:%vreg379 GPR32:%vreg382
14976B		%vreg380<def> = UBFMXri %vreg379, 0, 31; GPR64:%vreg380,%vreg379
14992B		%vreg377<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg377
15008B		%vreg376<def> = LDRXui %vreg377, 396; mem:LD8[%ll4503] GPR64:%vreg376 GPR64common:%vreg377
15024B		%vreg374<def> = ADDXrr %vreg376, %vreg380; GPR64common:%vreg374 GPR64:%vreg376,%vreg380
15040B		%vreg371<def> = LDRBBui %vreg374, 0; mem:LD1[%arrayidx504] GPR32:%vreg371 GPR64common:%vreg374
15056B		%vreg367<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg367
15072B		%vreg366<def> = LDRWui %vreg367, 15; mem:LD4[%tPos506] GPR32:%vreg366 GPR64common:%vreg367
15088B		%vreg364<def> = ANDWrs %vreg362, %vreg366, 2; GPR32:%vreg364,%vreg362,%vreg366
15104B		%vreg361<def> = LSRVWr %vreg371, %vreg364; GPR32:%vreg361,%vreg371,%vreg364
15120B		%vreg358<def> = ANDWri %vreg361, 3; GPR32common:%vreg358 GPR32:%vreg361
15136B		%vreg356<def> = ORRWrs %vreg389, %vreg358, 16; GPR32:%vreg356,%vreg389 GPR32common:%vreg358
15152B		%vreg353<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg353
15168B		STRWui %vreg356, %vreg353, 15; mem:ST4[%tPos513] GPR32:%vreg356 GPR64common:%vreg353
15184B		%vreg350<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg350
15200B		%vreg349<def> = LDRWui %vreg350, 273; mem:LD4[%nblock_used514] GPR32common:%vreg349 GPR64common:%vreg350
15216B		%vreg348<def> = ADDWri %vreg349, 1, 0; GPR32common:%vreg348,%vreg349
15232B		STRWui %vreg348, %vreg350, 273; mem:ST4[%nblock_used514] GPR32common:%vreg348 GPR64common:%vreg350
15248B		%vreg344<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg344
15264B		%vreg343<def> = LDRWui %vreg344, 273; mem:LD4[%nblock_used516] GPR32:%vreg343 GPR64common:%vreg344
15280B		%vreg341<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg341
15296B		%vreg338<def> = MOVi64imm 64080; GPR64:%vreg338
15312B		%vreg339<def> = ADDXrr %vreg341, %vreg338; GPR64common:%vreg339 GPR64:%vreg341,%vreg338
15328B		%vreg340<def> = LDRWui %vreg339, 0; mem:LD4[%save_nblock517] GPR32common:%vreg340 GPR64common:%vreg339
15344B		%vreg336<def> = ADDWri %vreg340, 1, 0; GPR32common:%vreg336,%vreg340
15360B		%WZR<def> = SUBSWrr %vreg343, %vreg336, %NZCV<imp-def>; GPR32:%vreg343 GPR32common:%vreg336
15376B		Bcc 1, <BB#70>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#70 BB#69

15392B	BB#69: derived from LLVM BB %if.then.521
	    Predecessors according to CFG: BB#68
15408B		B <BB#48>
	    Successors according to CFG: BB#48

15424B	BB#70: derived from LLVM BB %if.end.522
	    Predecessors according to CFG: BB#68
15440B		%vreg428<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg428
15456B		%vreg425<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg425
15472B		%vreg424<def> = LDRWui %vreg425, 16; mem:LD4[%k0524] GPR32:%vreg424 GPR64common:%vreg425
15488B		%WZR<def> = SUBSWrr %vreg428, %vreg424, %NZCV<imp-def>; GPR32:%vreg428,%vreg424
15504B		Bcc 0, <BB#72>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#72 BB#71

15520B	BB#71: derived from LLVM BB %if.then.527
	    Predecessors according to CFG: BB#70
15536B		%vreg588<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg588
15552B		%vreg585<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg585
15568B		STRWui %vreg588, %vreg585, 16; mem:ST4[%k0529] GPR32:%vreg588 GPR64common:%vreg585
15584B		B <BB#48>
	    Successors according to CFG: BB#48

15600B	BB#72: derived from LLVM BB %if.end.530
	    Predecessors according to CFG: BB#70
15616B		%vreg582<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg582
15632B		%vreg581<def> = LDRWui %vreg582, 15; mem:LD4[%tPos531] GPR32:%vreg581 GPR64common:%vreg582
15648B		%vreg579<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg579
15664B		%vreg578<def> = ADDXri %vreg579, 1096, 0; GPR64sp:%vreg578 GPR64common:%vreg579
15680B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
15696B		%W0<def> = COPY %vreg581; GPR32:%vreg581
15712B		%X1<def> = COPY %vreg578; GPR64sp:%vreg578
15728B		BL <ga:@BZ2_indexIntoF>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use,kill>, %W0<imp-def>
15744B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
15760B		%vreg575<def> = COPY %W0; GPR32all:%vreg575
15776B		%vreg527<def> = MOVi32imm 4; GPR32:%vreg527
15792B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
15808B		STACKMAP 9, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
15824B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
15840B		%vreg572<def> = COPY %vreg575; GPR32:%vreg572 GPR32all:%vreg575
15856B		STRBBui %vreg572, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg572
15872B		%vreg569<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg569
15888B		%vreg567<def> = LDRWui %vreg569, 15; mem:LD4[%tPos536] GPR32:%vreg567 GPR64common:%vreg569
15904B		%vreg568<def> = SUBREG_TO_REG 0, %vreg567, 15; GPR64:%vreg568 GPR32:%vreg567
15920B		%vreg562<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg562
15936B		%vreg561<def> = LDRXui %vreg562, 395; mem:LD8[%ll16538] GPR64:%vreg561 GPR64common:%vreg562
15952B		%vreg557<def> = MOVi64imm 2; GPR64:%vreg557
15968B		%vreg558<def> = MADDXrrr %vreg568, %vreg557, %XZR; GPR64:%vreg558,%vreg568,%vreg557
15984B		%vreg559<def> = ADDXrr %vreg561, %vreg558; GPR64common:%vreg559 GPR64:%vreg561,%vreg558
16000B		%vreg554<def> = LDRHHui %vreg559, 0; mem:LD2[%arrayidx539] GPR32:%vreg554 GPR64common:%vreg559
16016B		%vreg550<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg550
16032B		%vreg549<def> = LDRWui %vreg550, 15; mem:LD4[%tPos541] GPR32:%vreg549 GPR64common:%vreg550
16048B		%vreg547<def> = UBFMWri %vreg549, 1, 31; GPR32:%vreg547,%vreg549
16064B		%vreg544<def> = SUBREG_TO_REG 0, %vreg547, 15; GPR64:%vreg544 GPR32:%vreg547
16080B		%vreg545<def> = UBFMXri %vreg544, 0, 31; GPR64:%vreg545,%vreg544
16096B		%vreg542<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg542
16112B		%vreg541<def> = LDRXui %vreg542, 396; mem:LD8[%ll4544] GPR64:%vreg541 GPR64common:%vreg542
16128B		%vreg539<def> = ADDXrr %vreg541, %vreg545; GPR64common:%vreg539 GPR64:%vreg541,%vreg545
16144B		%vreg536<def> = LDRBBui %vreg539, 0; mem:LD1[%arrayidx545] GPR32:%vreg536 GPR64common:%vreg539
16160B		%vreg532<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg532
16176B		%vreg531<def> = LDRWui %vreg532, 15; mem:LD4[%tPos547] GPR32:%vreg531 GPR64common:%vreg532
16192B		%vreg529<def> = ANDWrs %vreg527, %vreg531, 2; GPR32:%vreg529,%vreg527,%vreg531
16208B		%vreg526<def> = LSRVWr %vreg536, %vreg529; GPR32:%vreg526,%vreg536,%vreg529
16224B		%vreg523<def> = ANDWri %vreg526, 3; GPR32common:%vreg523 GPR32:%vreg526
16240B		%vreg521<def> = ORRWrs %vreg554, %vreg523, 16; GPR32:%vreg521,%vreg554 GPR32common:%vreg523
16256B		%vreg518<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg518
16272B		STRWui %vreg521, %vreg518, 15; mem:ST4[%tPos554] GPR32:%vreg521 GPR64common:%vreg518
16288B		%vreg515<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg515
16304B		%vreg514<def> = LDRWui %vreg515, 273; mem:LD4[%nblock_used555] GPR32common:%vreg514 GPR64common:%vreg515
16320B		%vreg513<def> = ADDWri %vreg514, 1, 0; GPR32common:%vreg513,%vreg514
16336B		STRWui %vreg513, %vreg515, 273; mem:ST4[%nblock_used555] GPR32common:%vreg513 GPR64common:%vreg515
16352B		%vreg509<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32common:%vreg509
16368B		%vreg506<def> = ADDWri %vreg509, 4, 0; GPR32common:%vreg506,%vreg509
16384B		%vreg504<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg504
16400B		STRWui %vreg506, %vreg504, 4; mem:ST4[%state_out_len559] GPR32common:%vreg506 GPR64common:%vreg504
16416B		%vreg501<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg501
16432B		%vreg500<def> = LDRWui %vreg501, 15; mem:LD4[%tPos560] GPR32:%vreg500 GPR64common:%vreg501
16448B		%vreg498<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg498
16464B		%vreg497<def> = ADDXri %vreg498, 1096, 0; GPR64sp:%vreg497 GPR64common:%vreg498
16480B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
16496B		%W0<def> = COPY %vreg500; GPR32:%vreg500
16512B		%X1<def> = COPY %vreg497; GPR64sp:%vreg497
16528B		BL <ga:@BZ2_indexIntoF>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use,kill>, %W0<imp-def>
16544B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
16560B		%vreg494<def> = COPY %W0; GPR32:%vreg494
16576B		%vreg446<def> = MOVi32imm 4; GPR32:%vreg446
16592B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
16608B		STACKMAP 10, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
16624B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
16640B		%vreg491<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg491
16656B		STRWui %vreg494, %vreg491, 16; mem:ST4[%k0564] GPR32:%vreg494 GPR64common:%vreg491
16672B		%vreg488<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg488
16688B		%vreg486<def> = LDRWui %vreg488, 15; mem:LD4[%tPos565] GPR32:%vreg486 GPR64common:%vreg488
16704B		%vreg487<def> = SUBREG_TO_REG 0, %vreg486, 15; GPR64:%vreg487 GPR32:%vreg486
16720B		%vreg481<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg481
16736B		%vreg480<def> = LDRXui %vreg481, 395; mem:LD8[%ll16567] GPR64:%vreg480 GPR64common:%vreg481
16752B		%vreg476<def> = MOVi64imm 2; GPR64:%vreg476
16768B		%vreg477<def> = MADDXrrr %vreg487, %vreg476, %XZR; GPR64:%vreg477,%vreg487,%vreg476
16784B		%vreg478<def> = ADDXrr %vreg480, %vreg477; GPR64common:%vreg478 GPR64:%vreg480,%vreg477
16800B		%vreg473<def> = LDRHHui %vreg478, 0; mem:LD2[%arrayidx568] GPR32:%vreg473 GPR64common:%vreg478
16816B		%vreg469<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg469
16832B		%vreg468<def> = LDRWui %vreg469, 15; mem:LD4[%tPos570] GPR32:%vreg468 GPR64common:%vreg469
16848B		%vreg466<def> = UBFMWri %vreg468, 1, 31; GPR32:%vreg466,%vreg468
16864B		%vreg463<def> = SUBREG_TO_REG 0, %vreg466, 15; GPR64:%vreg463 GPR32:%vreg466
16880B		%vreg464<def> = UBFMXri %vreg463, 0, 31; GPR64:%vreg464,%vreg463
16896B		%vreg461<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg461
16912B		%vreg460<def> = LDRXui %vreg461, 396; mem:LD8[%ll4573] GPR64:%vreg460 GPR64common:%vreg461
16928B		%vreg458<def> = ADDXrr %vreg460, %vreg464; GPR64common:%vreg458 GPR64:%vreg460,%vreg464
16944B		%vreg455<def> = LDRBBui %vreg458, 0; mem:LD1[%arrayidx574] GPR32:%vreg455 GPR64common:%vreg458
16960B		%vreg451<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg451
16976B		%vreg450<def> = LDRWui %vreg451, 15; mem:LD4[%tPos576] GPR32:%vreg450 GPR64common:%vreg451
16992B		%vreg448<def> = ANDWrs %vreg446, %vreg450, 2; GPR32:%vreg448,%vreg446,%vreg450
17008B		%vreg445<def> = LSRVWr %vreg455, %vreg448; GPR32:%vreg445,%vreg455,%vreg448
17024B		%vreg442<def> = ANDWri %vreg445, 3; GPR32common:%vreg442 GPR32:%vreg445
17040B		%vreg440<def> = ORRWrs %vreg473, %vreg442, 16; GPR32:%vreg440,%vreg473 GPR32common:%vreg442
17056B		%vreg437<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg437
17072B		STRWui %vreg440, %vreg437, 15; mem:ST4[%tPos583] GPR32:%vreg440 GPR64common:%vreg437
17088B		%vreg434<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg434
17104B		%vreg433<def> = LDRWui %vreg434, 273; mem:LD4[%nblock_used584] GPR32common:%vreg433 GPR64common:%vreg434
17120B		%vreg432<def> = ADDWri %vreg433, 1, 0; GPR32common:%vreg432,%vreg433
17136B		STRWui %vreg432, %vreg434, 273; mem:ST4[%nblock_used584] GPR32common:%vreg432 GPR64common:%vreg434
17152B		B <BB#48>
	    Successors according to CFG: BB#48

17168B	BB#73: derived from LLVM BB %return
	    Predecessors according to CFG: BB#59 BB#57 BB#50 BB#13 BB#11 BB#4
17184B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
17200B		%vreg1466<def> = MOVaddr <ga:@unRLE_obuf_to_output_SMALL>[TF=1], <ga:@unRLE_obuf_to_output_SMALL>[TF=34]; GPR64:%vreg1466
17216B		%X0<def> = COPY %vreg1466; GPR64:%vreg1466
17232B		%X1<def> = COPY %vreg11; GPR64:%vreg11
17248B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %SP<imp-def>
17264B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
17280B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
17296B		STACKMAP 11, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=1)
17312B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
17328B		%vreg1467<def> = LDRBBui <fi#0>, 0; mem:LD1[%retval] GPR32:%vreg1467
17344B		%vreg1465<def,dead> = COPY %vreg1467; GPR32all:%vreg1465 GPR32:%vreg1467
17360B		%W0<def> = COPY %vreg1467; GPR32:%vreg1467
17376B		RET_ReallyLR %W0<imp-use>

# End machine code for function unRLE_obuf_to_output_SMALL.

********** SIMPLE REGISTER COALESCING **********
********** Function: unRLE_obuf_to_output_SMALL
********** JOINING INTERVALS ***********
while.body.2:
while.body.341:
if.end:
if.end.6:
896B	%vreg663<def> = SUBREG_TO_REG 0, %vreg667, 15; GPR64:%vreg663 GPR32:%vreg667
	Considering merging to GPR64 with %vreg667 in %vreg663:sub_32
		RHS = %vreg667 [880r,896r:0)  0@880r
		LHS = %vreg663 [896r,912r:0)  0@896r
		merge %vreg663:0@896r into %vreg667:0@880r --> @880r
		erased:	896r	%vreg663<def> = SUBREG_TO_REG 0, %vreg667, 15; GPR64:%vreg663 GPR32:%vreg667
		updated: 880B	%vreg663:sub_32<def,read-undef> = EORWrr %vreg674, %vreg671; GPR64:%vreg663 GPR32:%vreg674,%vreg671
	Success: %vreg667:sub_32 -> %vreg663
	Result = %vreg663 [880r,912r:0)  0@880r
if.end.26:
if.end.347:
if.end.352:
10992B	%vreg73<def> = SUBREG_TO_REG 0, %vreg77, 15; GPR64:%vreg73 GPR32:%vreg77
	Considering merging to GPR64 with %vreg77 in %vreg73:sub_32
		RHS = %vreg77 [10976r,10992r:0)  0@10976r
		LHS = %vreg73 [10992r,11008r:0)  0@10992r
		merge %vreg73:0@10992r into %vreg77:0@10976r --> @10976r
		erased:	10992r	%vreg73<def> = SUBREG_TO_REG 0, %vreg77, 15; GPR64:%vreg73 GPR32:%vreg77
		updated: 10976B	%vreg73:sub_32<def,read-undef> = EORWrr %vreg84, %vreg81; GPR64:%vreg73 GPR32:%vreg84,%vreg81
	Success: %vreg77:sub_32 -> %vreg73
	Result = %vreg73 [10976r,11008r:0)  0@10976r
if.end.386:
if.then.23:
if.then.382:
while.body:
while.body.339:
if.end.71:
3248B	%vreg863<def> = COPY %WZR; GPR32:%vreg863
	Considering merging %vreg863 with %WZR
		RHS = %vreg863 [3248r,3376r:0)  0@3248r
		Interference: WZR
	Interference!
if.end.138:
5072B	%vreg1014<def> = COPY %WZR; GPR32:%vreg1014
	Considering merging %vreg1014 with %WZR
		RHS = %vreg1014 [5072r,5200r:0)  0@5072r
		Interference: WZR
	Interference!
if.end.206:
6896B	%vreg1165<def> = COPY %WZR; GPR32:%vreg1165
	Considering merging %vreg1165 with %WZR
		RHS = %vreg1165 [6896r,7024r:0)  0@6896r
		Interference: WZR
	Interference!
if.end.273:
8672B	%vreg1380<def> = COPY %WZR; GPR32:%vreg1380
	Considering merging %vreg1380 with %WZR
		RHS = %vreg1380 [8672r,8800r:0)  0@8672r
		Interference: WZR
	Interference!
9088B	%W0<def> = COPY %vreg1353; GPR32:%vreg1353
	Considering merging %vreg1353 with %W0
	Can only merge into reserved registers.
9104B	%X1<def> = COPY %vreg1350; GPR64sp:%vreg1350
	Considering merging %vreg1350 with %X1
	Can only merge into reserved registers.
9152B	%vreg1347<def> = COPY %W0; GPR32:%vreg1347
	Considering merging %vreg1347 with %W0
	Can only merge into reserved registers.
9296B	%vreg1340<def> = SUBREG_TO_REG 0, %vreg1339, 15; GPR64:%vreg1340 GPR32:%vreg1339
	Considering merging to GPR64 with %vreg1339 in %vreg1340:sub_32
		RHS = %vreg1339 [9280r,9296r:0)  0@9280r
		LHS = %vreg1340 [9296r,9360r:0)  0@9296r
		merge %vreg1340:0@9296r into %vreg1339:0@9280r --> @9280r
		erased:	9296r	%vreg1340<def> = SUBREG_TO_REG 0, %vreg1339, 15; GPR64:%vreg1340 GPR32:%vreg1339
		updated: 9280B	%vreg1340:sub_32<def,read-undef> = LDRWui %vreg1341, 15; mem:LD4[%tPos293] GPR64:%vreg1340 GPR64common:%vreg1341
	Success: %vreg1339:sub_32 -> %vreg1340
	Result = %vreg1340 [9280r,9360r:0)  0@9280r
9456B	%vreg1316<def> = SUBREG_TO_REG 0, %vreg1319, 15; GPR64:%vreg1316 GPR32:%vreg1319
	Considering merging to GPR64 with %vreg1319 in %vreg1316:sub_32
		RHS = %vreg1319 [9440r,9456r:0)  0@9440r
		LHS = %vreg1316 [9456r,9472r:0)  0@9456r
		merge %vreg1316:0@9456r into %vreg1319:0@9440r --> @9440r
		erased:	9456r	%vreg1316<def> = SUBREG_TO_REG 0, %vreg1319, 15; GPR64:%vreg1316 GPR32:%vreg1319
		updated: 9440B	%vreg1316:sub_32<def,read-undef> = UBFMWri %vreg1321, 1, 31; GPR64:%vreg1316 GPR32:%vreg1321
	Success: %vreg1319:sub_32 -> %vreg1316
	Result = %vreg1316 [9440r,9472r:0)  0@9440r
while.end:
if.end.30:
if.end.37:
2192B	%W0<def> = COPY %vreg792; GPR32:%vreg792
	Considering merging %vreg792 with %W0
	Can only merge into reserved registers.
2208B	%X1<def> = COPY %vreg789; GPR64sp:%vreg789
	Considering merging %vreg789 with %X1
	Can only merge into reserved registers.
2256B	%vreg786<def> = COPY %W0; GPR32all:%vreg786
	Considering merging %vreg786 with %W0
	Can only merge into reserved registers.
2400B	%vreg779<def> = SUBREG_TO_REG 0, %vreg778, 15; GPR64:%vreg779 GPR32:%vreg778
	Considering merging to GPR64 with %vreg778 in %vreg779:sub_32
		RHS = %vreg778 [2384r,2400r:0)  0@2384r
		LHS = %vreg779 [2400r,2464r:0)  0@2400r
		merge %vreg779:0@2400r into %vreg778:0@2384r --> @2384r
		erased:	2400r	%vreg779<def> = SUBREG_TO_REG 0, %vreg778, 15; GPR64:%vreg779 GPR32:%vreg778
		updated: 2384B	%vreg779:sub_32<def,read-undef> = LDRWui %vreg780, 15; mem:LD4[%tPos42] GPR64:%vreg779 GPR64common:%vreg780
	Success: %vreg778:sub_32 -> %vreg779
	Result = %vreg779 [2384r,2464r:0)  0@2384r
2560B	%vreg755<def> = SUBREG_TO_REG 0, %vreg758, 15; GPR64:%vreg755 GPR32:%vreg758
	Considering merging to GPR64 with %vreg758 in %vreg755:sub_32
		RHS = %vreg758 [2544r,2560r:0)  0@2544r
		LHS = %vreg755 [2560r,2576r:0)  0@2560r
		merge %vreg755:0@2560r into %vreg758:0@2544r --> @2544r
		erased:	2560r	%vreg755<def> = SUBREG_TO_REG 0, %vreg758, 15; GPR64:%vreg755 GPR32:%vreg758
		updated: 2544B	%vreg755:sub_32<def,read-undef> = UBFMWri %vreg760, 1, 31; GPR64:%vreg755 GPR32:%vreg760
	Success: %vreg758:sub_32 -> %vreg755
	Result = %vreg755 [2544r,2576r:0)  0@2544r
if.then.59:
if.end.70:
if.end.88:
if.end.96:
4016B	%W0<def> = COPY %vreg951; GPR32:%vreg951
	Considering merging %vreg951 with %W0
	Can only merge into reserved registers.
4032B	%X1<def> = COPY %vreg948; GPR64sp:%vreg948
	Considering merging %vreg948 with %X1
	Can only merge into reserved registers.
4080B	%vreg945<def> = COPY %W0; GPR32all:%vreg945
	Considering merging %vreg945 with %W0
	Can only merge into reserved registers.
4224B	%vreg938<def> = SUBREG_TO_REG 0, %vreg937, 15; GPR64:%vreg938 GPR32:%vreg937
	Considering merging to GPR64 with %vreg937 in %vreg938:sub_32
		RHS = %vreg937 [4208r,4224r:0)  0@4208r
		LHS = %vreg938 [4224r,4288r:0)  0@4224r
		merge %vreg938:0@4224r into %vreg937:0@4208r --> @4208r
		erased:	4224r	%vreg938<def> = SUBREG_TO_REG 0, %vreg937, 15; GPR64:%vreg938 GPR32:%vreg937
		updated: 4208B	%vreg938:sub_32<def,read-undef> = LDRWui %vreg939, 15; mem:LD4[%tPos103] GPR64:%vreg938 GPR64common:%vreg939
	Success: %vreg937:sub_32 -> %vreg938
	Result = %vreg938 [4208r,4288r:0)  0@4208r
4384B	%vreg914<def> = SUBREG_TO_REG 0, %vreg917, 15; GPR64:%vreg914 GPR32:%vreg917
	Considering merging to GPR64 with %vreg917 in %vreg914:sub_32
		RHS = %vreg917 [4368r,4384r:0)  0@4368r
		LHS = %vreg914 [4384r,4400r:0)  0@4384r
		merge %vreg914:0@4384r into %vreg917:0@4368r --> @4368r
		erased:	4384r	%vreg914<def> = SUBREG_TO_REG 0, %vreg917, 15; GPR64:%vreg914 GPR32:%vreg917
		updated: 4368B	%vreg914:sub_32<def,read-undef> = UBFMWri %vreg919, 1, 31; GPR64:%vreg914 GPR32:%vreg919
	Success: %vreg917:sub_32 -> %vreg914
	Result = %vreg914 [4368r,4400r:0)  0@4368r
if.then.125:
if.end.137:
if.end.156:
if.end.164:
5840B	%W0<def> = COPY %vreg1102; GPR32:%vreg1102
	Considering merging %vreg1102 with %W0
	Can only merge into reserved registers.
5856B	%X1<def> = COPY %vreg1099; GPR64sp:%vreg1099
	Considering merging %vreg1099 with %X1
	Can only merge into reserved registers.
5904B	%vreg1096<def> = COPY %W0; GPR32all:%vreg1096
	Considering merging %vreg1096 with %W0
	Can only merge into reserved registers.
6048B	%vreg1089<def> = SUBREG_TO_REG 0, %vreg1088, 15; GPR64:%vreg1089 GPR32:%vreg1088
	Considering merging to GPR64 with %vreg1088 in %vreg1089:sub_32
		RHS = %vreg1088 [6032r,6048r:0)  0@6032r
		LHS = %vreg1089 [6048r,6112r:0)  0@6048r
		merge %vreg1089:0@6048r into %vreg1088:0@6032r --> @6032r
		erased:	6048r	%vreg1089<def> = SUBREG_TO_REG 0, %vreg1088, 15; GPR64:%vreg1089 GPR32:%vreg1088
		updated: 6032B	%vreg1089:sub_32<def,read-undef> = LDRWui %vreg1090, 15; mem:LD4[%tPos171] GPR64:%vreg1089 GPR64common:%vreg1090
	Success: %vreg1088:sub_32 -> %vreg1089
	Result = %vreg1089 [6032r,6112r:0)  0@6032r
6208B	%vreg1065<def> = SUBREG_TO_REG 0, %vreg1068, 15; GPR64:%vreg1065 GPR32:%vreg1068
	Considering merging to GPR64 with %vreg1068 in %vreg1065:sub_32
		RHS = %vreg1068 [6192r,6208r:0)  0@6192r
		LHS = %vreg1065 [6208r,6224r:0)  0@6208r
		merge %vreg1065:0@6208r into %vreg1068:0@6192r --> @6192r
		erased:	6208r	%vreg1065<def> = SUBREG_TO_REG 0, %vreg1068, 15; GPR64:%vreg1065 GPR32:%vreg1068
		updated: 6192B	%vreg1065:sub_32<def,read-undef> = UBFMWri %vreg1070, 1, 31; GPR64:%vreg1065 GPR32:%vreg1070
	Success: %vreg1068:sub_32 -> %vreg1065
	Result = %vreg1065 [6192r,6224r:0)  0@6192r
if.then.193:
if.end.205:
if.end.224:
if.end.232:
7616B	%W0<def> = COPY %vreg1253; GPR32:%vreg1253
	Considering merging %vreg1253 with %W0
	Can only merge into reserved registers.
7632B	%X1<def> = COPY %vreg1250; GPR64sp:%vreg1250
	Considering merging %vreg1250 with %X1
	Can only merge into reserved registers.
7680B	%vreg1247<def> = COPY %W0; GPR32all:%vreg1247
	Considering merging %vreg1247 with %W0
	Can only merge into reserved registers.
7824B	%vreg1240<def> = SUBREG_TO_REG 0, %vreg1239, 15; GPR64:%vreg1240 GPR32:%vreg1239
	Considering merging to GPR64 with %vreg1239 in %vreg1240:sub_32
		RHS = %vreg1239 [7808r,7824r:0)  0@7808r
		LHS = %vreg1240 [7824r,7888r:0)  0@7824r
		merge %vreg1240:0@7824r into %vreg1239:0@7808r --> @7808r
		erased:	7824r	%vreg1240<def> = SUBREG_TO_REG 0, %vreg1239, 15; GPR64:%vreg1240 GPR32:%vreg1239
		updated: 7808B	%vreg1240:sub_32<def,read-undef> = LDRWui %vreg1241, 15; mem:LD4[%tPos238] GPR64:%vreg1240 GPR64common:%vreg1241
	Success: %vreg1239:sub_32 -> %vreg1240
	Result = %vreg1240 [7808r,7888r:0)  0@7808r
7984B	%vreg1216<def> = SUBREG_TO_REG 0, %vreg1219, 15; GPR64:%vreg1216 GPR32:%vreg1219
	Considering merging to GPR64 with %vreg1219 in %vreg1216:sub_32
		RHS = %vreg1219 [7968r,7984r:0)  0@7968r
		LHS = %vreg1216 [7984r,8000r:0)  0@7984r
		merge %vreg1216:0@7984r into %vreg1219:0@7968r --> @7968r
		erased:	7984r	%vreg1216<def> = SUBREG_TO_REG 0, %vreg1219, 15; GPR64:%vreg1216 GPR32:%vreg1219
		updated: 7968B	%vreg1216:sub_32<def,read-undef> = UBFMWri %vreg1221, 1, 31; GPR64:%vreg1216 GPR32:%vreg1221
	Success: %vreg1219:sub_32 -> %vreg1216
	Result = %vreg1216 [7968r,8000r:0)  0@7968r
if.then.260:
if.end.272:
if.then.315:
if.end.327:
if.end.328:
10144B	%vreg1435<def> = COPY %WZR; GPR32:%vreg1435
	Considering merging %vreg1435 with %WZR
		RHS = %vreg1435 [10144r,10272r:0)  0@10144r
		Interference: WZR
	Interference!
while.end.387:
if.end.394:
if.end.401:
12288B	%W0<def> = COPY %vreg216; GPR32:%vreg216
	Considering merging %vreg216 with %W0
	Can only merge into reserved registers.
12304B	%X1<def> = COPY %vreg213; GPR64sp:%vreg213
	Considering merging %vreg213 with %X1
	Can only merge into reserved registers.
12352B	%vreg210<def> = COPY %W0; GPR32all:%vreg210
	Considering merging %vreg210 with %W0
	Can only merge into reserved registers.
12496B	%vreg203<def> = SUBREG_TO_REG 0, %vreg202, 15; GPR64:%vreg203 GPR32:%vreg202
	Considering merging to GPR64 with %vreg202 in %vreg203:sub_32
		RHS = %vreg202 [12480r,12496r:0)  0@12480r
		LHS = %vreg203 [12496r,12560r:0)  0@12496r
		merge %vreg203:0@12496r into %vreg202:0@12480r --> @12480r
		erased:	12496r	%vreg203<def> = SUBREG_TO_REG 0, %vreg202, 15; GPR64:%vreg203 GPR32:%vreg202
		updated: 12480B	%vreg203:sub_32<def,read-undef> = LDRWui %vreg204, 15; mem:LD4[%tPos411] GPR64:%vreg203 GPR64common:%vreg204
	Success: %vreg202:sub_32 -> %vreg203
	Result = %vreg203 [12480r,12560r:0)  0@12480r
12656B	%vreg179<def> = SUBREG_TO_REG 0, %vreg182, 15; GPR64:%vreg179 GPR32:%vreg182
	Considering merging to GPR64 with %vreg182 in %vreg179:sub_32
		RHS = %vreg182 [12640r,12656r:0)  0@12640r
		LHS = %vreg179 [12656r,12672r:0)  0@12656r
		merge %vreg179:0@12656r into %vreg182:0@12640r --> @12640r
		erased:	12656r	%vreg179<def> = SUBREG_TO_REG 0, %vreg182, 15; GPR64:%vreg179 GPR32:%vreg182
		updated: 12640B	%vreg179:sub_32<def,read-undef> = UBFMWri %vreg184, 1, 31; GPR64:%vreg179 GPR32:%vreg184
	Success: %vreg182:sub_32 -> %vreg179
	Result = %vreg179 [12640r,12672r:0)  0@12640r
if.end.438:
if.end.446:
13440B	%W0<def> = COPY %vreg320; GPR32:%vreg320
	Considering merging %vreg320 with %W0
	Can only merge into reserved registers.
13456B	%X1<def> = COPY %vreg317; GPR64sp:%vreg317
	Considering merging %vreg317 with %X1
	Can only merge into reserved registers.
13504B	%vreg314<def> = COPY %W0; GPR32all:%vreg314
	Considering merging %vreg314 with %W0
	Can only merge into reserved registers.
13648B	%vreg307<def> = SUBREG_TO_REG 0, %vreg306, 15; GPR64:%vreg307 GPR32:%vreg306
	Considering merging to GPR64 with %vreg306 in %vreg307:sub_32
		RHS = %vreg306 [13632r,13648r:0)  0@13632r
		LHS = %vreg307 [13648r,13712r:0)  0@13648r
		merge %vreg307:0@13648r into %vreg306:0@13632r --> @13632r
		erased:	13648r	%vreg307<def> = SUBREG_TO_REG 0, %vreg306, 15; GPR64:%vreg307 GPR32:%vreg306
		updated: 13632B	%vreg307:sub_32<def,read-undef> = LDRWui %vreg308, 15; mem:LD4[%tPos453] GPR64:%vreg307 GPR64common:%vreg308
	Success: %vreg306:sub_32 -> %vreg307
	Result = %vreg307 [13632r,13712r:0)  0@13632r
13808B	%vreg283<def> = SUBREG_TO_REG 0, %vreg286, 15; GPR64:%vreg283 GPR32:%vreg286
	Considering merging to GPR64 with %vreg286 in %vreg283:sub_32
		RHS = %vreg286 [13792r,13808r:0)  0@13792r
		LHS = %vreg283 [13808r,13824r:0)  0@13808r
		merge %vreg283:0@13808r into %vreg286:0@13792r --> @13792r
		erased:	13808r	%vreg283<def> = SUBREG_TO_REG 0, %vreg286, 15; GPR64:%vreg283 GPR32:%vreg286
		updated: 13792B	%vreg283:sub_32<def,read-undef> = UBFMWri %vreg288, 1, 31; GPR64:%vreg283 GPR32:%vreg288
	Success: %vreg286:sub_32 -> %vreg283
	Result = %vreg283 [13792r,13824r:0)  0@13792r
if.end.480:
if.end.488:
14592B	%W0<def> = COPY %vreg416; GPR32:%vreg416
	Considering merging %vreg416 with %W0
	Can only merge into reserved registers.
14608B	%X1<def> = COPY %vreg413; GPR64sp:%vreg413
	Considering merging %vreg413 with %X1
	Can only merge into reserved registers.
14656B	%vreg410<def> = COPY %W0; GPR32all:%vreg410
	Considering merging %vreg410 with %W0
	Can only merge into reserved registers.
14800B	%vreg403<def> = SUBREG_TO_REG 0, %vreg402, 15; GPR64:%vreg403 GPR32:%vreg402
	Considering merging to GPR64 with %vreg402 in %vreg403:sub_32
		RHS = %vreg402 [14784r,14800r:0)  0@14784r
		LHS = %vreg403 [14800r,14864r:0)  0@14800r
		merge %vreg403:0@14800r into %vreg402:0@14784r --> @14784r
		erased:	14800r	%vreg403<def> = SUBREG_TO_REG 0, %vreg402, 15; GPR64:%vreg403 GPR32:%vreg402
		updated: 14784B	%vreg403:sub_32<def,read-undef> = LDRWui %vreg404, 15; mem:LD4[%tPos495] GPR64:%vreg403 GPR64common:%vreg404
	Success: %vreg402:sub_32 -> %vreg403
	Result = %vreg403 [14784r,14864r:0)  0@14784r
14960B	%vreg379<def> = SUBREG_TO_REG 0, %vreg382, 15; GPR64:%vreg379 GPR32:%vreg382
	Considering merging to GPR64 with %vreg382 in %vreg379:sub_32
		RHS = %vreg382 [14944r,14960r:0)  0@14944r
		LHS = %vreg379 [14960r,14976r:0)  0@14960r
		merge %vreg379:0@14960r into %vreg382:0@14944r --> @14944r
		erased:	14960r	%vreg379<def> = SUBREG_TO_REG 0, %vreg382, 15; GPR64:%vreg379 GPR32:%vreg382
		updated: 14944B	%vreg379:sub_32<def,read-undef> = UBFMWri %vreg384, 1, 31; GPR64:%vreg379 GPR32:%vreg384
	Success: %vreg382:sub_32 -> %vreg379
	Result = %vreg379 [14944r,14976r:0)  0@14944r
if.end.522:
if.then.5:
if.then.68:
if.then.87:
if.then.93:
if.then.135:
if.then.155:
if.then.161:
if.then.203:
if.then.223:
if.then.229:
if.then.270:
if.then.325:
if.then.351:
if.then.437:
if.then.443:
if.then.479:
if.then.485:
if.then.521:
if.then.527:
if.end.530:
15696B	%W0<def> = COPY %vreg581; GPR32:%vreg581
	Considering merging %vreg581 with %W0
	Can only merge into reserved registers.
15712B	%X1<def> = COPY %vreg578; GPR64sp:%vreg578
	Considering merging %vreg578 with %X1
	Can only merge into reserved registers.
15760B	%vreg575<def> = COPY %W0; GPR32all:%vreg575
	Considering merging %vreg575 with %W0
	Can only merge into reserved registers.
15904B	%vreg568<def> = SUBREG_TO_REG 0, %vreg567, 15; GPR64:%vreg568 GPR32:%vreg567
	Considering merging to GPR64 with %vreg567 in %vreg568:sub_32
		RHS = %vreg567 [15888r,15904r:0)  0@15888r
		LHS = %vreg568 [15904r,15968r:0)  0@15904r
		merge %vreg568:0@15904r into %vreg567:0@15888r --> @15888r
		erased:	15904r	%vreg568<def> = SUBREG_TO_REG 0, %vreg567, 15; GPR64:%vreg568 GPR32:%vreg567
		updated: 15888B	%vreg568:sub_32<def,read-undef> = LDRWui %vreg569, 15; mem:LD4[%tPos536] GPR64:%vreg568 GPR64common:%vreg569
	Success: %vreg567:sub_32 -> %vreg568
	Result = %vreg568 [15888r,15968r:0)  0@15888r
16064B	%vreg544<def> = SUBREG_TO_REG 0, %vreg547, 15; GPR64:%vreg544 GPR32:%vreg547
	Considering merging to GPR64 with %vreg547 in %vreg544:sub_32
		RHS = %vreg547 [16048r,16064r:0)  0@16048r
		LHS = %vreg544 [16064r,16080r:0)  0@16064r
		merge %vreg544:0@16064r into %vreg547:0@16048r --> @16048r
		erased:	16064r	%vreg544<def> = SUBREG_TO_REG 0, %vreg547, 15; GPR64:%vreg544 GPR32:%vreg547
		updated: 16048B	%vreg544:sub_32<def,read-undef> = UBFMWri %vreg549, 1, 31; GPR64:%vreg544 GPR32:%vreg549
	Success: %vreg547:sub_32 -> %vreg544
	Result = %vreg544 [16048r,16080r:0)  0@16048r
16496B	%W0<def> = COPY %vreg500; GPR32:%vreg500
	Considering merging %vreg500 with %W0
	Can only merge into reserved registers.
16512B	%X1<def> = COPY %vreg497; GPR64sp:%vreg497
	Considering merging %vreg497 with %X1
	Can only merge into reserved registers.
16560B	%vreg494<def> = COPY %W0; GPR32:%vreg494
	Considering merging %vreg494 with %W0
	Can only merge into reserved registers.
16704B	%vreg487<def> = SUBREG_TO_REG 0, %vreg486, 15; GPR64:%vreg487 GPR32:%vreg486
	Considering merging to GPR64 with %vreg486 in %vreg487:sub_32
		RHS = %vreg486 [16688r,16704r:0)  0@16688r
		LHS = %vreg487 [16704r,16768r:0)  0@16704r
		merge %vreg487:0@16704r into %vreg486:0@16688r --> @16688r
		erased:	16704r	%vreg487<def> = SUBREG_TO_REG 0, %vreg486, 15; GPR64:%vreg487 GPR32:%vreg486
		updated: 16688B	%vreg487:sub_32<def,read-undef> = LDRWui %vreg488, 15; mem:LD4[%tPos565] GPR64:%vreg487 GPR64common:%vreg488
	Success: %vreg486:sub_32 -> %vreg487
	Result = %vreg487 [16688r,16768r:0)  0@16688r
16864B	%vreg463<def> = SUBREG_TO_REG 0, %vreg466, 15; GPR64:%vreg463 GPR32:%vreg466
	Considering merging to GPR64 with %vreg466 in %vreg463:sub_32
		RHS = %vreg466 [16848r,16864r:0)  0@16848r
		LHS = %vreg463 [16864r,16880r:0)  0@16864r
		merge %vreg463:0@16864r into %vreg466:0@16848r --> @16848r
		erased:	16864r	%vreg463<def> = SUBREG_TO_REG 0, %vreg466, 15; GPR64:%vreg463 GPR32:%vreg466
		updated: 16848B	%vreg463:sub_32<def,read-undef> = UBFMWri %vreg468, 1, 31; GPR64:%vreg463 GPR32:%vreg468
	Success: %vreg466:sub_32 -> %vreg463
	Result = %vreg463 [16848r,16880r:0)  0@16848r
3424B	%vreg854<def> = COPY %vreg857; GPR32:%vreg854,%vreg857
	Considering merging to GPR32 with %vreg857 in %vreg854
		RHS = %vreg857 [3408r,3424r:0)  0@3408r
		LHS = %vreg854 [3424r,3440r:0)  0@3424r
		merge %vreg854:0@3424r into %vreg857:0@3408r --> @3408r
		erased:	3424r	%vreg854<def> = COPY %vreg857; GPR32:%vreg854,%vreg857
		updated: 3408B	%vreg854<def> = EORWrr %vreg860, %vreg864; GPR32:%vreg854,%vreg860,%vreg864
	Success: %vreg857 -> %vreg854
	Result = %vreg854 [3408r,3440r:0)  0@3408r
5248B	%vreg1005<def> = COPY %vreg1008; GPR32:%vreg1005,%vreg1008
	Considering merging to GPR32 with %vreg1008 in %vreg1005
		RHS = %vreg1008 [5232r,5248r:0)  0@5232r
		LHS = %vreg1005 [5248r,5264r:0)  0@5248r
		merge %vreg1005:0@5248r into %vreg1008:0@5232r --> @5232r
		erased:	5248r	%vreg1005<def> = COPY %vreg1008; GPR32:%vreg1005,%vreg1008
		updated: 5232B	%vreg1005<def> = EORWrr %vreg1011, %vreg1015; GPR32:%vreg1005,%vreg1011,%vreg1015
	Success: %vreg1008 -> %vreg1005
	Result = %vreg1005 [5232r,5264r:0)  0@5232r
7072B	%vreg1156<def> = COPY %vreg1159; GPR32:%vreg1156,%vreg1159
	Considering merging to GPR32 with %vreg1159 in %vreg1156
		RHS = %vreg1159 [7056r,7072r:0)  0@7056r
		LHS = %vreg1156 [7072r,7088r:0)  0@7072r
		merge %vreg1156:0@7072r into %vreg1159:0@7056r --> @7056r
		erased:	7072r	%vreg1156<def> = COPY %vreg1159; GPR32:%vreg1156,%vreg1159
		updated: 7056B	%vreg1156<def> = EORWrr %vreg1162, %vreg1166; GPR32:%vreg1156,%vreg1162,%vreg1166
	Success: %vreg1159 -> %vreg1156
	Result = %vreg1156 [7056r,7088r:0)  0@7056r
8848B	%vreg1371<def> = COPY %vreg1374; GPR32:%vreg1371,%vreg1374
	Considering merging to GPR32 with %vreg1374 in %vreg1371
		RHS = %vreg1374 [8832r,8848r:0)  0@8832r
		LHS = %vreg1371 [8848r,8864r:0)  0@8848r
		merge %vreg1371:0@8848r into %vreg1374:0@8832r --> @8832r
		erased:	8848r	%vreg1371<def> = COPY %vreg1374; GPR32:%vreg1371,%vreg1374
		updated: 8832B	%vreg1371<def> = EORWrr %vreg1377, %vreg1381; GPR32:%vreg1371,%vreg1377,%vreg1381
	Success: %vreg1374 -> %vreg1371
	Result = %vreg1371 [8832r,8864r:0)  0@8832r
2064B	%vreg798<def> = COPY %vreg800; GPR32:%vreg798,%vreg800
	Considering merging to GPR32 with %vreg800 in %vreg798
		RHS = %vreg800 [2048r,2064r:0)  0@2048r
		LHS = %vreg798 [2064r,2096r:0)  0@2064r
		merge %vreg798:0@2064r into %vreg800:0@2048r --> @2048r
		erased:	2064r	%vreg798<def> = COPY %vreg800; GPR32:%vreg798,%vreg800
		updated: 2048B	%vreg798<def> = LDRWui %vreg801, 16; mem:LD4[%k0] GPR32:%vreg798 GPR64common:%vreg801
	Success: %vreg800 -> %vreg798
	Result = %vreg798 [2048r,2096r:0)  0@2048r
2336B	%vreg783<def> = COPY %vreg786; GPR32:%vreg783 GPR32all:%vreg786
	Considering merging to GPR32 with %vreg786 in %vreg783
		RHS = %vreg786 [2256r,2336r:0)  0@2256r
		LHS = %vreg783 [2336r,2352r:0)  0@2336r
		merge %vreg783:0@2336r into %vreg786:0@2256r --> @2256r
		erased:	2336r	%vreg783<def> = COPY %vreg786; GPR32:%vreg783 GPR32all:%vreg786
		updated: 2256B	%vreg783<def> = COPY %W0; GPR32:%vreg783
	Success: %vreg786 -> %vreg783
	Result = %vreg783 [2256r,2352r:0)  0@2256r
4160B	%vreg942<def> = COPY %vreg945; GPR32:%vreg942 GPR32all:%vreg945
	Considering merging to GPR32 with %vreg945 in %vreg942
		RHS = %vreg945 [4080r,4160r:0)  0@4080r
		LHS = %vreg942 [4160r,4176r:0)  0@4160r
		merge %vreg942:0@4160r into %vreg945:0@4080r --> @4080r
		erased:	4160r	%vreg942<def> = COPY %vreg945; GPR32:%vreg942 GPR32all:%vreg945
		updated: 4080B	%vreg942<def> = COPY %W0; GPR32:%vreg942
	Success: %vreg945 -> %vreg942
	Result = %vreg942 [4080r,4176r:0)  0@4080r
5984B	%vreg1093<def> = COPY %vreg1096; GPR32:%vreg1093 GPR32all:%vreg1096
	Considering merging to GPR32 with %vreg1096 in %vreg1093
		RHS = %vreg1096 [5904r,5984r:0)  0@5904r
		LHS = %vreg1093 [5984r,6000r:0)  0@5984r
		merge %vreg1093:0@5984r into %vreg1096:0@5904r --> @5904r
		erased:	5984r	%vreg1093<def> = COPY %vreg1096; GPR32:%vreg1093 GPR32all:%vreg1096
		updated: 5904B	%vreg1093<def> = COPY %W0; GPR32:%vreg1093
	Success: %vreg1096 -> %vreg1093
	Result = %vreg1093 [5904r,6000r:0)  0@5904r
7760B	%vreg1244<def> = COPY %vreg1247; GPR32:%vreg1244 GPR32all:%vreg1247
	Considering merging to GPR32 with %vreg1247 in %vreg1244
		RHS = %vreg1247 [7680r,7760r:0)  0@7680r
		LHS = %vreg1244 [7760r,7776r:0)  0@7760r
		merge %vreg1244:0@7760r into %vreg1247:0@7680r --> @7680r
		erased:	7760r	%vreg1244<def> = COPY %vreg1247; GPR32:%vreg1244 GPR32all:%vreg1247
		updated: 7680B	%vreg1244<def> = COPY %W0; GPR32:%vreg1244
	Success: %vreg1247 -> %vreg1244
	Result = %vreg1244 [7680r,7776r:0)  0@7680r
12160B	%vreg222<def> = COPY %vreg224; GPR32:%vreg222,%vreg224
	Considering merging to GPR32 with %vreg224 in %vreg222
		RHS = %vreg224 [12144r,12160r:0)  0@12144r
		LHS = %vreg222 [12160r,12192r:0)  0@12160r
		merge %vreg222:0@12160r into %vreg224:0@12144r --> @12144r
		erased:	12160r	%vreg222<def> = COPY %vreg224; GPR32:%vreg222,%vreg224
		updated: 12144B	%vreg222<def> = LDRWui %vreg225, 16; mem:LD4[%k0403] GPR32:%vreg222 GPR64common:%vreg225
	Success: %vreg224 -> %vreg222
	Result = %vreg222 [12144r,12192r:0)  0@12144r
12432B	%vreg207<def> = COPY %vreg210; GPR32:%vreg207 GPR32all:%vreg210
	Considering merging to GPR32 with %vreg210 in %vreg207
		RHS = %vreg210 [12352r,12432r:0)  0@12352r
		LHS = %vreg207 [12432r,12448r:0)  0@12432r
		merge %vreg207:0@12432r into %vreg210:0@12352r --> @12352r
		erased:	12432r	%vreg207<def> = COPY %vreg210; GPR32:%vreg207 GPR32all:%vreg210
		updated: 12352B	%vreg207<def> = COPY %W0; GPR32:%vreg207
	Success: %vreg210 -> %vreg207
	Result = %vreg207 [12352r,12448r:0)  0@12352r
13584B	%vreg311<def> = COPY %vreg314; GPR32:%vreg311 GPR32all:%vreg314
	Considering merging to GPR32 with %vreg314 in %vreg311
		RHS = %vreg314 [13504r,13584r:0)  0@13504r
		LHS = %vreg311 [13584r,13600r:0)  0@13584r
		merge %vreg311:0@13584r into %vreg314:0@13504r --> @13504r
		erased:	13584r	%vreg311<def> = COPY %vreg314; GPR32:%vreg311 GPR32all:%vreg314
		updated: 13504B	%vreg311<def> = COPY %W0; GPR32:%vreg311
	Success: %vreg314 -> %vreg311
	Result = %vreg311 [13504r,13600r:0)  0@13504r
14736B	%vreg407<def> = COPY %vreg410; GPR32:%vreg407 GPR32all:%vreg410
	Considering merging to GPR32 with %vreg410 in %vreg407
		RHS = %vreg410 [14656r,14736r:0)  0@14656r
		LHS = %vreg407 [14736r,14752r:0)  0@14736r
		merge %vreg407:0@14736r into %vreg410:0@14656r --> @14656r
		erased:	14736r	%vreg407<def> = COPY %vreg410; GPR32:%vreg407 GPR32all:%vreg410
		updated: 14656B	%vreg407<def> = COPY %W0; GPR32:%vreg407
	Success: %vreg410 -> %vreg407
	Result = %vreg407 [14656r,14752r:0)  0@14656r
15840B	%vreg572<def> = COPY %vreg575; GPR32:%vreg572 GPR32all:%vreg575
	Considering merging to GPR32 with %vreg575 in %vreg572
		RHS = %vreg575 [15760r,15840r:0)  0@15760r
		LHS = %vreg572 [15840r,15856r:0)  0@15840r
		merge %vreg572:0@15840r into %vreg575:0@15760r --> @15760r
		erased:	15840r	%vreg572<def> = COPY %vreg575; GPR32:%vreg572 GPR32all:%vreg575
		updated: 15760B	%vreg572<def> = COPY %W0; GPR32:%vreg572
	Success: %vreg575 -> %vreg572
	Result = %vreg572 [15760r,15856r:0)  0@15760r
return:
17216B	%X0<def> = COPY %vreg1466; GPR64:%vreg1466
	Considering merging %vreg1466 with %X0
	Can only merge into reserved registers.
17232B	%X1<def> = COPY %vreg11; GPR64:%vreg11
	Considering merging %vreg11 with %X1
	Can only merge into reserved registers.
17360B	%W0<def> = COPY %vreg1467; GPR32:%vreg1467
	Considering merging %vreg1467 with %W0
	Can only merge into reserved registers.
entry:
16B	%vreg11<def> = COPY %LR; GPR64:%vreg11
	Considering merging %vreg11 with %LR
	Can only merge into reserved registers.
32B	%vreg0<def> = COPY %X0; GPR64:%vreg0
	Considering merging %vreg0 with %X0
	Can only merge into reserved registers.
144B	%X0<def> = COPY %vreg9; GPR64all:%vreg9
	Considering merging %vreg9 with %X0
	Can only merge into reserved registers.
160B	%X1<def> = COPY %vreg10; GPR64all:%vreg10
	Considering merging %vreg10 with %X1
	Can only merge into reserved registers.
if.then:
if.then.3:
if.then.29:
if.then.36:
if.else:
if.then.346:
if.then.393:
if.then.400:
17344B	%vreg1465<def,dead> = COPY %vreg1467; GPR32all:%vreg1465 GPR32:%vreg1467
	Copy is dead.
Deleting dead def 17344r	%vreg1465<def,dead> = COPY %vreg1467; GPR32all:%vreg1465 GPR32:%vreg1467
Shrink: %vreg1467 [17328r,17360r:0)  0@17328r
Shrunk: %vreg1467 [17328r,17360r:0)  0@17328r
48B	%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
	Considering merging to GPR64 with %vreg0 in %vreg1
		RHS = %vreg0 [32r,48r:0)  0@32r
		LHS = %vreg1 [48r,256r:0)  0@48r
		merge %vreg1:0@48r into %vreg0:0@32r --> @32r
		erased:	48r	%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
		updated: 32B	%vreg1<def> = COPY %X0; GPR64:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [32r,256r:0)  0@32r
96B	%vreg9<def> = COPY %vreg8; GPR64all:%vreg9 GPR64sp:%vreg8
	Considering merging to GPR64sp with %vreg8 in %vreg9
		RHS = %vreg8 [80r,96r:0)  0@80r
		LHS = %vreg9 [96r,144r:0)  0@96r
		merge %vreg9:0@96r into %vreg8:0@80r --> @80r
		erased:	96r	%vreg9<def> = COPY %vreg8; GPR64all:%vreg9 GPR64sp:%vreg8
		updated: 80B	%vreg9<def> = ADDXri %vreg7, <ga:@unRLE_obuf_to_output_SMALL>[TF=34], 0; GPR64sp:%vreg9 GPR64common:%vreg7
	Success: %vreg8 -> %vreg9
	Result = %vreg9 [80r,144r:0)  0@80r
112B	%vreg10<def> = COPY %vreg11; GPR64all:%vreg10 GPR64:%vreg11
	Considering merging to GPR64 with %vreg11 in %vreg10
		RHS = %vreg11 [16r,17232r:0)  0@16r
		LHS = %vreg10 [112r,160r:0)  0@112r
		merge %vreg10:0@112r into %vreg11:0@16r --> @16r
		erased:	112r	%vreg10<def> = COPY %vreg11; GPR64all:%vreg10 GPR64:%vreg11
		updated: 16B	%vreg10<def> = COPY %LR; GPR64:%vreg10
		updated: 17232B	%X1<def> = COPY %vreg10; GPR64:%vreg10
	Success: %vreg11 -> %vreg10
	Result = %vreg10 [16r,17232r:0)  0@16r
3248B	%vreg863<def> = COPY %WZR; GPR32:%vreg863
	Considering merging %vreg863 with %WZR
		RHS = %vreg863 [3248r,3376r:0)  0@3248r
		Interference: WZR
	Interference!
5072B	%vreg1014<def> = COPY %WZR; GPR32:%vreg1014
	Considering merging %vreg1014 with %WZR
		RHS = %vreg1014 [5072r,5200r:0)  0@5072r
		Interference: WZR
	Interference!
6896B	%vreg1165<def> = COPY %WZR; GPR32:%vreg1165
	Considering merging %vreg1165 with %WZR
		RHS = %vreg1165 [6896r,7024r:0)  0@6896r
		Interference: WZR
	Interference!
8672B	%vreg1380<def> = COPY %WZR; GPR32:%vreg1380
	Considering merging %vreg1380 with %WZR
		RHS = %vreg1380 [8672r,8800r:0)  0@8672r
		Interference: WZR
	Interference!
10144B	%vreg1435<def> = COPY %WZR; GPR32:%vreg1435
	Considering merging %vreg1435 with %WZR
		RHS = %vreg1435 [10144r,10272r:0)  0@10144r
		Interference: WZR
	Interference!
17232B	%X1<def> = COPY %vreg10; GPR64:%vreg10
	Considering merging %vreg10 with %X1
	Can only merge into reserved registers.
144B	%X0<def> = COPY %vreg9; GPR64sp:%vreg9
	Considering merging %vreg9 with %X0
	Can only merge into reserved registers.
160B	%X1<def> = COPY %vreg10; GPR64:%vreg10
	Considering merging %vreg10 with %X1
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
W30 [0B,16r:0)[176r,176d:24)[224e,224d:12)[2224r,2224d:18)[2304e,2304d:11)[4048r,4048d:17)[4128e,4128d:10)[5872r,5872d:16)[5952e,5952d:9)[7648r,7648d:15)[7728e,7728d:8)[9120r,9120d:14)[9200e,9200d:7)[12320r,12320d:23)[12400e,12400d:6)[13472r,13472d:22)[13552e,13552d:5)[14624r,14624d:21)[14704e,14704d:4)[15728r,15728d:19)[15808e,15808d:3)[16528r,16528d:20)[16608e,16608d:2)[17248r,17248d:13)[17296e,17296d:1)  0@0B-phi 1@17296e 2@16608e 3@15808e 4@14704e 5@13552e 6@12400e 7@9200e 8@7728e 9@5952e 10@4128e 11@2304e 12@224e 13@17248r 14@9120r 15@7648r 16@5872r 17@4048r 18@2224r 19@15728r 20@16528r 21@14624r 22@13472r 23@12320r 24@176r
WZR [1664r,1664d:17)[1872r,1872d:16)[3104r,3104d:15)[3360r,3360d:13)[3632r,3632d:14)[3760r,3760d:12)[4928r,4928d:11)[5184r,5184d:9)[5456r,5456d:10)[5584r,5584d:8)[6752r,6752d:7)[7008r,7008d:5)[7280r,7280d:6)[7408r,7408d:4)[8528r,8528d:3)[8784r,8784d:2)[10000r,10000d:1)[10256r,10256d:0)[11760r,11760d:25)[11968r,11968d:24)[13056r,13056d:23)[13184r,13184d:22)[14208r,14208d:21)[14336r,14336d:20)[15360r,15360d:19)[15488r,15488d:18)  0@10256r 1@10000r 2@8784r 3@8528r 4@7408r 5@7008r 6@7280r 7@6752r 8@5584r 9@5184r 10@5456r 11@4928r 12@3760r 13@3360r 14@3632r 15@3104r 16@1872r 17@1664r 18@15488r 19@15360r 20@14336r 21@14208r 22@13184r 23@13056r 24@11968r 25@11760r
W0 [0B,32r:0)[144r,176r:23)[2192r,2224r:11)[2224r,2256r:10)[4016r,4048r:9)[4048r,4080r:8)[5840r,5872r:7)[5872r,5904r:6)[7616r,7648r:5)[7648r,7680r:4)[9088r,9120r:3)[9120r,9152r:2)[12288r,12320r:21)[12320r,12352r:20)[13440r,13472r:19)[13472r,13504r:18)[14592r,14624r:17)[14624r,14656r:16)[15696r,15728r:13)[15728r,15760r:12)[16496r,16528r:15)[16528r,16560r:14)[17216r,17248r:22)[17360r,17376r:1)  0@0B-phi 1@17360r 2@9120r 3@9088r 4@7648r 5@7616r 6@5872r 7@5840r 8@4048r 9@4016r 10@2224r 11@2192r 12@15728r 13@15696r 14@16528r 15@16496r 16@14624r 17@14592r 18@13472r 19@13440r 20@12320r 21@12288r 22@17216r 23@144r
%vreg1 [32r,256r:0)  0@32r
%vreg3 [304r,320r:0)  0@304r
%vreg5 [288r,304r:0)  0@288r
%vreg6 [272r,288r:0)  0@272r
%vreg7 [64r,80r:0)  0@64r
%vreg9 [80r,144r:0)  0@80r
%vreg10 [16r,17232r:0)  0@16r
%vreg14 [10544r,10560r:0)  0@10544r
%vreg16 [10528r,10544r:0)  0@10528r
%vreg17 [10512r,10528r:0)  0@10512r
%vreg20 [10656r,10672r:0)  0@10656r
%vreg21 [10640r,10656r:0)  0@10640r
%vreg24 [11472r,11488r:0)  0@11472r
%vreg26 [11456r,11472r:0)  0@11456r
%vreg27 [11440r,11456r:0)  0@11440r
%vreg31 [11408r,11424r:0)  0@11408r
%vreg32 [11392r,11408r:0)  0@11392r
%vreg34 [11376r,11424r:0)  0@11376r
%vreg35 [11360r,11376r:0)  0@11360r
%vreg39 [11328r,11344r:0)  0@11328r
%vreg40 [11312r,11328r:0)  0@11312r
%vreg42 [11296r,11344r:0)  0@11296r
%vreg43 [11280r,11296r:0)  0@11280r
%vreg47 [11248r,11264r:0)  0@11248r
%vreg48 [11232r,11248r:0)  0@11232r
%vreg50 [11216r,11264r:0)  0@11216r
%vreg51 [11200r,11216r:0)  0@11200r
%vreg55 [11168r,11184r:0)  0@11168r
%vreg56 [11152r,11168r:0)  0@11152r
%vreg57 [11136r,11184r:0)  0@11136r
%vreg60 [11104r,11120r:0)  0@11104r
%vreg63 [11088r,11120r:0)  0@11088r
%vreg65 [11072r,11088r:0)  0@11072r
%vreg66 [10736r,10752r:0)  0@10736r
%vreg67 [10752r,11056r:0)  0@10752r
%vreg69 [11024r,11040r:0)  0@11024r
%vreg70 [11040r,11056r:0)  0@11040r
%vreg71 [11056r,11072r:0)  0@11056r
%vreg73 [10976r,11008r:0)  0@10976r
%vreg74 [11008r,11040r:0)  0@11008r
%vreg81 [10960r,10976r:0)  0@10960r
%vreg82 [10944r,10960r:0)  0@10944r
%vreg84 [10928r,10976r:0)  0@10928r
%vreg86 [10912r,10928r:0)  0@10912r
%vreg87 [10896r,10912r:0)  0@10896r
%vreg89 [10880r,11088r:0)  0@10880r
%vreg90 [10864r,10880r:0)  0@10864r
%vreg94 [10832r,10848r:0)  0@10832r
%vreg96 [10816r,10832r:0)  0@10816r
%vreg97 [10800r,10816r:0)  0@10800r
%vreg99 [10784r,10848r:0)  0@10784r
%vreg100 [10768r,10784r:0)  0@10768r
%vreg104 [11568r,11584r:0)  0@11568r
%vreg105 [11552r,11568r:0)  0@11552r
%vreg107 [11536r,11584r:0)  0@11536r
%vreg108 [11520r,11536r:0)  0@11520r
%vreg112 [11744r,11760r:0)  0@11744r
%vreg114 [11696r,11712r:0)  0@11696r
%vreg115 [11712r,11728r:0)  0@11712r
%vreg116 [11728r,11744r:0)  0@11728r
%vreg117 [11680r,11712r:0)  0@11680r
%vreg119 [11664r,11760r:0)  0@11664r
%vreg120 [11648r,11664r:0)  0@11648r
%vreg124 [11952r,11968r:0)  0@11952r
%vreg126 [11904r,11920r:0)  0@11904r
%vreg127 [11920r,11936r:0)  0@11920r
%vreg128 [11936r,11952r:0)  0@11936r
%vreg129 [11888r,11920r:0)  0@11888r
%vreg131 [11872r,11968r:0)  0@11872r
%vreg132 [11856r,11872r:0)  0@11856r
%vreg136 [13040r,13056r:0)  0@13040r
%vreg138 [12992r,13008r:0)  0@12992r
%vreg139 [13008r,13024r:0)  0@13008r
%vreg140 [13024r,13040r:0)  0@13024r
%vreg141 [12976r,13008r:0)  0@12976r
%vreg143 [12960r,13056r:0)  0@12960r
%vreg144 [12944r,12960r:0)  0@12944r
%vreg148 [12912r,12928r:0)  0@12912r
%vreg149 [12896r,12912r:0)  0@12896r
%vreg150 [12880r,12928r:0)  0@12880r
%vreg153 [12848r,12864r:0)  0@12848r
%vreg156 [12832r,12864r:0)  0@12832r
%vreg158 [12816r,12832r:0)  0@12816r
%vreg161 [12800r,12816r:0)  0@12800r
%vreg162 [12368r,12784r:0)  0@12368r
%vreg164 [12784r,12800r:0)  0@12784r
%vreg166 [12768r,12784r:0)  0@12768r
%vreg167 [12752r,12768r:0)  0@12752r
%vreg171 [12736r,12800r:0)  0@12736r
%vreg174 [12720r,12736r:0)  0@12720r
%vreg176 [12704r,12720r:0)  0@12704r
%vreg177 [12688r,12704r:0)  0@12688r
%vreg179 [12640r,12672r:0)  0@12640r
%vreg180 [12672r,12720r:0)  0@12672r
%vreg184 [12624r,12640r:0)  0@12624r
%vreg185 [12608r,12624r:0)  0@12608r
%vreg189 [12592r,12832r:0)  0@12592r
%vreg192 [12544r,12560r:0)  0@12544r
%vreg193 [12560r,12576r:0)  0@12560r
%vreg194 [12576r,12592r:0)  0@12576r
%vreg196 [12528r,12576r:0)  0@12528r
%vreg197 [12512r,12528r:0)  0@12512r
%vreg203 [12480r,12560r:0)  0@12480r
%vreg204 [12464r,12480r:0)  0@12464r
%vreg207 [12352r,12448r:0)  0@12352r
%vreg213 [12256r,12304r:0)  0@12256r
%vreg214 [12240r,12256r:0)  0@12240r
%vreg216 [12224r,12288r:0)  0@12224r
%vreg217 [12208r,12224r:0)  0@12208r
%vreg220 [12176r,12192r:0)  0@12176r
%vreg222 [12144r,12192r:0)  0@12144r
%vreg225 [12128r,12144r:0)  0@12128r
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%vreg988 [5440r,5456r:0)  0@5440r
%vreg990 [5392r,5408r:0)  0@5392r
%vreg991 [5408r,5424r:0)  0@5408r
%vreg992 [5424r,5440r:0)  0@5424r
%vreg993 [5376r,5408r:0)  0@5376r
%vreg995 [5360r,5456r:0)  0@5360r
%vreg996 [5344r,5360r:0)  0@5344r
%vreg1000 [5312r,5328r:0)  0@5312r
%vreg1001 [5296r,5312r:0)  0@5296r
%vreg1002 [5280r,5328r:0)  0@5280r
%vreg1005 [5232r,5264r:0)  0@5232r
%vreg1011 [5216r,5232r:0)  0@5216r
%vreg1013 [5056r,5200r:0)  0@5056r
%vreg1014 [5072r,5200r:0)  0@5072r
%vreg1015 [5200r,5232r:0)  0@5200r
%vreg1017 [5168r,5184r:0)  0@5168r
%vreg1018 [5152r,5168r:0)  0@5152r
%vreg1022 [5120r,5136r:0)  0@5120r
%vreg1023 [5104r,5120r:0)  0@5104r
%vreg1024 [5088r,5136r:0)  0@5088r
%vreg1028 [5568r,5584r:0)  0@5568r
%vreg1029 [5552r,5568r:0)  0@5552r
%vreg1032 [5536r,5584r:0)  0@5536r
%vreg1035 [6448r,6464r:0)  0@6448r
%vreg1036 [6432r,6448r:0)  0@6432r
%vreg1039 [6400r,6416r:0)  0@6400r
%vreg1042 [6384r,6416r:0)  0@6384r
%vreg1044 [6368r,6384r:0)  0@6368r
%vreg1047 [6352r,6368r:0)  0@6352r
%vreg1048 [5920r,6336r:0)  0@5920r
%vreg1050 [6336r,6352r:0)  0@6336r
%vreg1052 [6320r,6336r:0)  0@6320r
%vreg1053 [6304r,6320r:0)  0@6304r
%vreg1057 [6288r,6352r:0)  0@6288r
%vreg1060 [6272r,6288r:0)  0@6272r
%vreg1062 [6256r,6272r:0)  0@6256r
%vreg1063 [6240r,6256r:0)  0@6240r
%vreg1065 [6192r,6224r:0)  0@6192r
%vreg1066 [6224r,6272r:0)  0@6224r
%vreg1070 [6176r,6192r:0)  0@6176r
%vreg1071 [6160r,6176r:0)  0@6160r
%vreg1075 [6144r,6384r:0)  0@6144r
%vreg1078 [6096r,6112r:0)  0@6096r
%vreg1079 [6112r,6128r:0)  0@6112r
%vreg1080 [6128r,6144r:0)  0@6128r
%vreg1082 [6080r,6128r:0)  0@6080r
%vreg1083 [6064r,6080r:0)  0@6064r
%vreg1089 [6032r,6112r:0)  0@6032r
%vreg1090 [6016r,6032r:0)  0@6016r
%vreg1093 [5904r,6000r:0)  0@5904r
%vreg1099 [5808r,5856r:0)  0@5808r
%vreg1100 [5792r,5808r:0)  0@5792r
%vreg1102 [5776r,5840r:0)  0@5776r
%vreg1103 [5760r,5776r:0)  0@5760r
%vreg1104 [5712r,5744r:0)  0@5712r
%vreg1106 [5728r,5744r:0)  0@5728r
%vreg1109 [6736r,6752r:0)  0@6736r
%vreg1110 [6720r,6736r:0)  0@6720r
%vreg1114 [6688r,6704r:0)  0@6688r
%vreg1115 [6672r,6688r:0)  0@6672r
%vreg1116 [6656r,6704r:0)  0@6656r
%vreg1119 [6624r,6640r:0)  0@6624r
%vreg1121 [6608r,6640r:0)  0@6608r
%vreg1122 [6496r,6512r:0)  0@6496r
%vreg1123 [6512r,6592r:0)  0@6512r
%vreg1125 [6560r,6576r:0)  0@6560r
%vreg1126 [6576r,6592r:0)  0@6576r
%vreg1127 [6592r,6608r:0)  0@6592r
%vreg1132 [6544r,6576r:0)  0@6544r
%vreg1133 [6528r,6544r:0)  0@6528r
%vreg1135 [6800r,6816r:0)  0@6800r
%vreg1139 [7264r,7280r:0)  0@7264r
%vreg1141 [7216r,7232r:0)  0@7216r
%vreg1142 [7232r,7248r:0)  0@7232r
%vreg1143 [7248r,7264r:0)  0@7248r
%vreg1144 [7200r,7232r:0)  0@7200r
%vreg1146 [7184r,7280r:0)  0@7184r
%vreg1147 [7168r,7184r:0)  0@7168r
%vreg1151 [7136r,7152r:0)  0@7136r
%vreg1152 [7120r,7136r:0)  0@7120r
%vreg1153 [7104r,7152r:0)  0@7104r
%vreg1156 [7056r,7088r:0)  0@7056r
%vreg1162 [7040r,7056r:0)  0@7040r
%vreg1164 [6880r,7024r:0)  0@6880r
%vreg1165 [6896r,7024r:0)  0@6896r
%vreg1166 [7024r,7056r:0)  0@7024r
%vreg1168 [6992r,7008r:0)  0@6992r
%vreg1169 [6976r,6992r:0)  0@6976r
%vreg1173 [6944r,6960r:0)  0@6944r
%vreg1174 [6928r,6944r:0)  0@6928r
%vreg1175 [6912r,6960r:0)  0@6912r
%vreg1179 [7392r,7408r:0)  0@7392r
%vreg1180 [7376r,7392r:0)  0@7376r
%vreg1183 [7360r,7408r:0)  0@7360r
%vreg1186 [8224r,8240r:0)  0@8224r
%vreg1187 [8208r,8224r:0)  0@8208r
%vreg1190 [8176r,8192r:0)  0@8176r
%vreg1193 [8160r,8192r:0)  0@8160r
%vreg1195 [8144r,8160r:0)  0@8144r
%vreg1198 [8128r,8144r:0)  0@8128r
%vreg1199 [7696r,8112r:0)  0@7696r
%vreg1201 [8112r,8128r:0)  0@8112r
%vreg1203 [8096r,8112r:0)  0@8096r
%vreg1204 [8080r,8096r:0)  0@8080r
%vreg1208 [8064r,8128r:0)  0@8064r
%vreg1211 [8048r,8064r:0)  0@8048r
%vreg1213 [8032r,8048r:0)  0@8032r
%vreg1214 [8016r,8032r:0)  0@8016r
%vreg1216 [7968r,8000r:0)  0@7968r
%vreg1217 [8000r,8048r:0)  0@8000r
%vreg1221 [7952r,7968r:0)  0@7952r
%vreg1222 [7936r,7952r:0)  0@7936r
%vreg1226 [7920r,8160r:0)  0@7920r
%vreg1229 [7872r,7888r:0)  0@7872r
%vreg1230 [7888r,7904r:0)  0@7888r
%vreg1231 [7904r,7920r:0)  0@7904r
%vreg1233 [7856r,7904r:0)  0@7856r
%vreg1234 [7840r,7856r:0)  0@7840r
%vreg1240 [7808r,7888r:0)  0@7808r
%vreg1241 [7792r,7808r:0)  0@7792r
%vreg1244 [7680r,7776r:0)  0@7680r
%vreg1250 [7584r,7632r:0)  0@7584r
%vreg1251 [7568r,7584r:0)  0@7568r
%vreg1253 [7552r,7616r:0)  0@7552r
%vreg1254 [7536r,7552r:0)  0@7536r
%vreg1257 [8512r,8528r:0)  0@8512r
%vreg1258 [8496r,8512r:0)  0@8496r
%vreg1262 [8464r,8480r:0)  0@8464r
%vreg1263 [8448r,8464r:0)  0@8448r
%vreg1264 [8432r,8480r:0)  0@8432r
%vreg1267 [8400r,8416r:0)  0@8400r
%vreg1269 [8384r,8416r:0)  0@8384r
%vreg1270 [8272r,8288r:0)  0@8272r
%vreg1271 [8288r,8368r:0)  0@8288r
%vreg1273 [8336r,8352r:0)  0@8336r
%vreg1274 [8352r,8368r:0)  0@8352r
%vreg1275 [8368r,8384r:0)  0@8368r
%vreg1280 [8320r,8352r:0)  0@8320r
%vreg1281 [8304r,8320r:0)  0@8304r
%vreg1283 [8576r,8592r:0)  0@8576r
%vreg1286 [9696r,9712r:0)  0@9696r
%vreg1287 [9680r,9696r:0)  0@9680r
%vreg1290 [9648r,9664r:0)  0@9648r
%vreg1293 [9632r,9664r:0)  0@9632r
%vreg1295 [9616r,9632r:0)  0@9616r
%vreg1298 [9600r,9616r:0)  0@9600r
%vreg1299 [9168r,9584r:0)  0@9168r
%vreg1301 [9584r,9600r:0)  0@9584r
%vreg1303 [9568r,9584r:0)  0@9568r
%vreg1304 [9552r,9568r:0)  0@9552r
%vreg1308 [9536r,9600r:0)  0@9536r
%vreg1311 [9520r,9536r:0)  0@9520r
%vreg1313 [9504r,9520r:0)  0@9504r
%vreg1314 [9488r,9504r:0)  0@9488r
%vreg1316 [9440r,9472r:0)  0@9440r
%vreg1317 [9472r,9520r:0)  0@9472r
%vreg1321 [9424r,9440r:0)  0@9424r
%vreg1322 [9408r,9424r:0)  0@9408r
%vreg1326 [9392r,9632r:0)  0@9392r
%vreg1329 [9344r,9360r:0)  0@9344r
%vreg1330 [9360r,9376r:0)  0@9360r
%vreg1331 [9376r,9392r:0)  0@9376r
%vreg1333 [9328r,9376r:0)  0@9328r
%vreg1334 [9312r,9328r:0)  0@9312r
%vreg1340 [9280r,9360r:0)  0@9280r
%vreg1341 [9264r,9280r:0)  0@9264r
%vreg1344 [9232r,9248r:0)  0@9232r
%vreg1347 [9152r,9248r:0)  0@9152r
%vreg1350 [9056r,9104r:0)  0@9056r
%vreg1351 [9040r,9056r:0)  0@9040r
%vreg1353 [9024r,9088r:0)  0@9024r
%vreg1354 [9008r,9024r:0)  0@9008r
%vreg1357 [8976r,8992r:0)  0@8976r
%vreg1359 [8960r,8992r:0)  0@8960r
%vreg1362 [8944r,8960r:0)  0@8944r
%vreg1366 [8912r,8928r:0)  0@8912r
%vreg1367 [8896r,8912r:0)  0@8896r
%vreg1368 [8880r,8928r:0)  0@8880r
%vreg1371 [8832r,8864r:0)  0@8832r
%vreg1377 [8816r,8832r:0)  0@8816r
%vreg1379 [8656r,8800r:0)  0@8656r
%vreg1380 [8672r,8800r:0)  0@8672r
%vreg1381 [8800r,8832r:0)  0@8800r
%vreg1383 [8768r,8784r:0)  0@8768r
%vreg1384 [8752r,8768r:0)  0@8752r
%vreg1388 [8720r,8736r:0)  0@8720r
%vreg1389 [8704r,8720r:0)  0@8704r
%vreg1390 [8688r,8736r:0)  0@8688r
%vreg1393 [9984r,10000r:0)  0@9984r
%vreg1394 [9968r,9984r:0)  0@9968r
%vreg1398 [9936r,9952r:0)  0@9936r
%vreg1399 [9920r,9936r:0)  0@9920r
%vreg1400 [9904r,9952r:0)  0@9904r
%vreg1403 [9872r,9888r:0)  0@9872r
%vreg1405 [9856r,9888r:0)  0@9856r
%vreg1406 [9744r,9760r:0)  0@9744r
%vreg1407 [9760r,9840r:0)  0@9760r
%vreg1409 [9808r,9824r:0)  0@9808r
%vreg1410 [9824r,9840r:0)  0@9824r
%vreg1411 [9840r,9856r:0)  0@9840r
%vreg1416 [9792r,9824r:0)  0@9792r
%vreg1417 [9776r,9792r:0)  0@9776r
%vreg1419 [10048r,10064r:0)  0@10048r
%vreg1423 [10384r,10400r:0)  0@10384r
%vreg1424 [10368r,10384r:0)  0@10368r
%vreg1425 [10352r,10400r:0)  0@10352r
%vreg1430 [10320r,10336r:0)  0@10320r
%vreg1431 [10304r,10320r:0)  0@10304r
%vreg1432 [10288r,10336r:0)  0@10288r
%vreg1434 [10128r,10272r:0)  0@10128r
%vreg1435 [10144r,10272r:0)  0@10144r
%vreg1436 [10272r,10320r:0)  0@10272r
%vreg1438 [10240r,10256r:0)  0@10240r
%vreg1439 [10224r,10240r:0)  0@10224r
%vreg1443 [10192r,10208r:0)  0@10192r
%vreg1444 [10176r,10192r:0)  0@10176r
%vreg1445 [10160r,10208r:0)  0@10160r
%vreg1448 [7472r,7488r:0)  0@7472r
%vreg1451 [7456r,7488r:0)  0@7456r
%vreg1454 [5648r,5664r:0)  0@5648r
%vreg1457 [5632r,5664r:0)  0@5632r
%vreg1460 [3824r,3840r:0)  0@3824r
%vreg1463 [3808r,3840r:0)  0@3808r
%vreg1464 [1920r,1936r:0)  0@1920r
%vreg1466 [17200r,17216r:0)  0@17200r
%vreg1467 [17328r,17360r:0)  0@17328r
RegMasks: 176r 2224r 4048r 5872r 7648r 9120r 12320r 13472r 14624r 15728r 16528r 17248r
********** MACHINEINSTRS **********
# Machine code for function unRLE_obuf_to_output_SMALL: Post SSA
Frame Objects:
  fi#0: size=1, align=1, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=1, align=1, at location [SP]
Function Live Ins: %X0 in %vreg0, %LR in %vreg11

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %LR
16B		%vreg10<def> = COPY %LR; GPR64:%vreg10
32B		%vreg1<def> = COPY %X0; GPR64:%vreg1
64B		%vreg7<def> = ADRP <ga:@unRLE_obuf_to_output_SMALL>[TF=1]; GPR64common:%vreg7
80B		%vreg9<def> = ADDXri %vreg7, <ga:@unRLE_obuf_to_output_SMALL>[TF=34], 0; GPR64sp:%vreg9 GPR64common:%vreg7
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		%X0<def> = COPY %vreg9; GPR64sp:%vreg9
160B		%X1<def> = COPY %vreg10; GPR64:%vreg10
176B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
224B		STACKMAP 0, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, %vreg1, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1] GPR64:%vreg1
240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
256B		STRXui %vreg1, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg1
272B		%vreg6<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg6
288B		%vreg5<def> = LDRBBui %vreg6, 20; mem:LD1[%blockRandomised] GPR32:%vreg5 GPR64common:%vreg6
304B		%vreg3<def> = UBFMWri %vreg5, 0, 7; GPR32:%vreg3,%vreg5
320B		CBZW %vreg3, <BB#47>; GPR32:%vreg3
	    Successors according to CFG: BB#47 BB#1

336B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
352B		B <BB#2>
	    Successors according to CFG: BB#2

368B	BB#2: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#1 BB#46 BB#37 BB#35 BB#29 BB#27 BB#21 BB#19
384B		B <BB#3>
	    Successors according to CFG: BB#3

400B	BB#3: derived from LLVM BB %while.body.2
	    Predecessors according to CFG: BB#2 BB#9
416B		%vreg607<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg607
432B		%vreg606<def> = LDRXui %vreg607, 0; mem:LD8[%strm] GPR64common:%vreg606,%vreg607
448B		%vreg604<def> = LDRWui %vreg606, 8; mem:LD4[%avail_out] GPR32:%vreg604 GPR64common:%vreg606
464B		CBNZW %vreg604, <BB#5>; GPR32:%vreg604
	    Successors according to CFG: BB#5 BB#4

480B	BB#4: derived from LLVM BB %if.then.3
	    Predecessors according to CFG: BB#3
496B		STRBBui %WZR, <fi#0>, 0; mem:ST1[FixedStack0]
512B		B <BB#73>
	    Successors according to CFG: BB#73

528B	BB#5: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#3
544B		%vreg611<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg611
560B		%vreg610<def> = LDRWui %vreg611, 4; mem:LD4[%state_out_len] GPR32:%vreg610 GPR64common:%vreg611
576B		CBNZW %vreg610, <BB#7>; GPR32:%vreg610
	    Successors according to CFG: BB#7 BB#6

592B	BB#6: derived from LLVM BB %if.then.5
	    Predecessors according to CFG: BB#5
608B		B <BB#10>
	    Successors according to CFG: BB#10

624B	BB#7: derived from LLVM BB %if.end.6
	    Predecessors according to CFG: BB#5
640B		%vreg656<def> = ADRP <ga:@BZ2_crc32Table>[TF=1]; GPR64common:%vreg656
656B		%vreg657<def> = ADDXri %vreg656, <ga:@BZ2_crc32Table>[TF=34], 0; GPR64common:%vreg657,%vreg656
672B		%vreg690<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg690
688B		%vreg689<def> = LDRBBui %vreg690, 12; mem:LD1[%state_out_ch] GPR32:%vreg689 GPR64common:%vreg690
704B		%vreg687<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg687
720B		%vreg686<def> = LDRXui %vreg687, 0; mem:LD8[%strm7] GPR64common:%vreg686,%vreg687
736B		%vreg684<def> = LDRXui %vreg686, 3; mem:LD8[%next_out] GPR64common:%vreg684,%vreg686
752B		STRBBui %vreg689, %vreg684, 0; mem:ST1[%11] GPR32:%vreg689 GPR64common:%vreg684
768B		%vreg680<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg680
784B		%vreg679<def> = LDRWui %vreg680, 796; mem:LD4[%calculatedBlockCRC] GPR32:%vreg679 GPR64common:%vreg680
800B		%vreg677<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg677
816B		%vreg676<def> = LDRWui %vreg677, 796; mem:LD4[%calculatedBlockCRC8] GPR32:%vreg676 GPR64common:%vreg677
832B		%vreg674<def> = UBFMWri %vreg676, 24, 31; GPR32:%vreg674,%vreg676
848B		%vreg672<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg672
864B		%vreg671<def> = LDRBBui %vreg672, 12; mem:LD1[%state_out_ch9] GPR32:%vreg671 GPR64common:%vreg672
880B		%vreg663:sub_32<def,read-undef> = EORWrr %vreg674, %vreg671; GPR64:%vreg663 GPR32:%vreg674,%vreg671
912B		%vreg664<def> = UBFMXri %vreg663, 0, 31; GPR64:%vreg664,%vreg663
928B		%vreg659<def> = MOVi64imm 4; GPR64:%vreg659
944B		%vreg660<def> = MADDXrrr %vreg664, %vreg659, %XZR; GPR64:%vreg660,%vreg664,%vreg659
960B		%vreg661<def> = ADDXrr %vreg657, %vreg660; GPR64common:%vreg661,%vreg657 GPR64:%vreg660
976B		%vreg655<def> = LDRWui %vreg661, 0; mem:LD4[%arrayidx] GPR32:%vreg655 GPR64common:%vreg661
992B		%vreg653<def> = EORWrs %vreg655, %vreg679, 8; GPR32:%vreg653,%vreg655,%vreg679
1008B		%vreg650<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg650
1024B		STRWui %vreg653, %vreg650, 796; mem:ST4[%calculatedBlockCRC11] GPR32:%vreg653 GPR64common:%vreg650
1040B		%vreg647<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg647
1056B		%vreg646<def> = LDRWui %vreg647, 4; mem:LD4[%state_out_len12] GPR32common:%vreg646 GPR64common:%vreg647
1072B		%vreg645<def> = SUBWri %vreg646, 1, 0; GPR32common:%vreg645,%vreg646
1088B		STRWui %vreg645, %vreg647, 4; mem:ST4[%state_out_len12] GPR32common:%vreg645 GPR64common:%vreg647
1104B		%vreg641<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg641
1120B		%vreg640<def> = LDRXui %vreg641, 0; mem:LD8[%strm13] GPR64common:%vreg640,%vreg641
1136B		%vreg638<def> = LDRXui %vreg640, 3; mem:LD8[%next_out14] GPR64common:%vreg638,%vreg640
1152B		%vreg637<def> = ADDXri %vreg638, 1, 0; GPR64common:%vreg637,%vreg638
1168B		STRXui %vreg637, %vreg640, 3; mem:ST8[%next_out14] GPR64common:%vreg637,%vreg640
1184B		%vreg633<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg633
1200B		%vreg632<def> = LDRXui %vreg633, 0; mem:LD8[%strm15] GPR64common:%vreg632,%vreg633
1216B		%vreg630<def> = LDRWui %vreg632, 8; mem:LD4[%avail_out16] GPR32common:%vreg630 GPR64common:%vreg632
1232B		%vreg629<def> = SUBWri %vreg630, 1, 0; GPR32common:%vreg629,%vreg630
1248B		STRWui %vreg629, %vreg632, 8; mem:ST4[%avail_out16] GPR32common:%vreg629 GPR64common:%vreg632
1264B		%vreg625<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg625
1280B		%vreg624<def> = LDRXui %vreg625, 0; mem:LD8[%strm18] GPR64common:%vreg624,%vreg625
1296B		%vreg622<def> = LDRWui %vreg624, 9; mem:LD4[%total_out_lo32] GPR32common:%vreg622 GPR64common:%vreg624
1312B		%vreg621<def> = ADDWri %vreg622, 1, 0; GPR32common:%vreg621,%vreg622
1328B		STRWui %vreg621, %vreg624, 9; mem:ST4[%total_out_lo32] GPR32common:%vreg621 GPR64common:%vreg624
1344B		%vreg617<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg617
1360B		%vreg616<def> = LDRXui %vreg617, 0; mem:LD8[%strm19] GPR64common:%vreg616,%vreg617
1376B		%vreg614<def> = LDRWui %vreg616, 9; mem:LD4[%total_out_lo3220] GPR32:%vreg614 GPR64common:%vreg616
1392B		CBNZW %vreg614, <BB#9>; GPR32:%vreg614
	    Successors according to CFG: BB#9 BB#8

1408B	BB#8: derived from LLVM BB %if.then.23
	    Predecessors according to CFG: BB#7
1424B		%vreg698<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg698
1440B		%vreg697<def> = LDRXui %vreg698, 0; mem:LD8[%strm24] GPR64common:%vreg697,%vreg698
1456B		%vreg695<def> = LDRWui %vreg697, 10; mem:LD4[%total_out_hi32] GPR32common:%vreg695 GPR64common:%vreg697
1472B		%vreg694<def> = ADDWri %vreg695, 1, 0; GPR32common:%vreg694,%vreg695
1488B		STRWui %vreg694, %vreg697, 10; mem:ST4[%total_out_hi32] GPR32common:%vreg694 GPR64common:%vreg697
	    Successors according to CFG: BB#9

1504B	BB#9: derived from LLVM BB %if.end.26
	    Predecessors according to CFG: BB#7 BB#8
1520B		B <BB#3>
	    Successors according to CFG: BB#3

1536B	BB#10: derived from LLVM BB %while.end
	    Predecessors according to CFG: BB#6
1552B		%vreg710<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg710
1568B		%vreg709<def> = LDRWui %vreg710, 273; mem:LD4[%nblock_used] GPR32:%vreg709 GPR64common:%vreg710
1584B		%vreg707<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg707
1600B		%vreg704<def> = MOVi64imm 64080; GPR64:%vreg704
1616B		%vreg705<def> = ADDXrr %vreg707, %vreg704; GPR64common:%vreg705 GPR64:%vreg707,%vreg704
1632B		%vreg706<def> = LDRWui %vreg705, 0; mem:LD4[%save_nblock] GPR32common:%vreg706 GPR64common:%vreg705
1648B		%vreg702<def> = ADDWri %vreg706, 1, 0; GPR32common:%vreg702,%vreg706
1664B		%WZR<def> = SUBSWrr %vreg709, %vreg702, %NZCV<imp-def>; GPR32:%vreg709 GPR32common:%vreg702
1680B		Bcc 1, <BB#12>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#12 BB#11

1696B	BB#11: derived from LLVM BB %if.then.29
	    Predecessors according to CFG: BB#10
1712B		STRBBui %WZR, <fi#0>, 0; mem:ST1[FixedStack0]
1728B		B <BB#73>
	    Successors according to CFG: BB#73

1744B	BB#12: derived from LLVM BB %if.end.30
	    Predecessors according to CFG: BB#10
1760B		%vreg722<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg722
1776B		%vreg721<def> = LDRWui %vreg722, 273; mem:LD4[%nblock_used31] GPR32:%vreg721 GPR64common:%vreg722
1792B		%vreg719<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg719
1808B		%vreg716<def> = MOVi64imm 64080; GPR64:%vreg716
1824B		%vreg717<def> = ADDXrr %vreg719, %vreg716; GPR64common:%vreg717 GPR64:%vreg719,%vreg716
1840B		%vreg718<def> = LDRWui %vreg717, 0; mem:LD4[%save_nblock32] GPR32common:%vreg718 GPR64common:%vreg717
1856B		%vreg714<def> = ADDWri %vreg718, 1, 0; GPR32common:%vreg714,%vreg718
1872B		%WZR<def> = SUBSWrr %vreg721, %vreg714, %NZCV<imp-def>; GPR32:%vreg721 GPR32common:%vreg714
1888B		Bcc 13, <BB#14>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#14 BB#13

1904B	BB#13: derived from LLVM BB %if.then.36
	    Predecessors according to CFG: BB#12
1920B		%vreg1464<def> = MOVi32imm 1; GPR32:%vreg1464
1936B		STRBBui %vreg1464, <fi#0>, 0; mem:ST1[FixedStack0] GPR32:%vreg1464
1952B		B <BB#73>
	    Successors according to CFG: BB#73

1968B	BB#14: derived from LLVM BB %if.end.37
	    Predecessors according to CFG: BB#12
1984B		%vreg802<def> = MOVi32imm 1; GPR32:%vreg802
2000B		%vreg804<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg804
2016B		STRWui %vreg802, %vreg804, 4; mem:ST4[%state_out_len38] GPR32:%vreg802 GPR64common:%vreg804
2032B		%vreg801<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg801
2048B		%vreg798<def> = LDRWui %vreg801, 16; mem:LD4[%k0] GPR32:%vreg798 GPR64common:%vreg801
2080B		%vreg796<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg796
2096B		STRBBui %vreg798, %vreg796, 12; mem:ST1[%state_out_ch40] GPR32:%vreg798 GPR64common:%vreg796
2112B		%vreg793<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg793
2128B		%vreg792<def> = LDRWui %vreg793, 15; mem:LD4[%tPos] GPR32:%vreg792 GPR64common:%vreg793
2144B		%vreg790<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg790
2160B		%vreg789<def> = ADDXri %vreg790, 1096, 0; GPR64sp:%vreg789 GPR64common:%vreg790
2176B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2192B		%W0<def> = COPY %vreg792; GPR32:%vreg792
2208B		%X1<def> = COPY %vreg789; GPR64sp:%vreg789
2224B		BL <ga:@BZ2_indexIntoF>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use,kill>, %W0<imp-def>
2240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2256B		%vreg783<def> = COPY %W0; GPR32:%vreg783
2272B		%vreg738<def> = MOVi32imm 4; GPR32:%vreg738
2288B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2304B		STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
2320B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2352B		STRBBui %vreg783, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg783
2368B		%vreg780<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg780
2384B		%vreg779:sub_32<def,read-undef> = LDRWui %vreg780, 15; mem:LD4[%tPos42] GPR64:%vreg779 GPR64common:%vreg780
2416B		%vreg773<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg773
2432B		%vreg772<def> = LDRXui %vreg773, 395; mem:LD8[%ll16] GPR64:%vreg772 GPR64common:%vreg773
2448B		%vreg768<def> = MOVi64imm 2; GPR64:%vreg768
2464B		%vreg769<def> = MADDXrrr %vreg779, %vreg768, %XZR; GPR64:%vreg769,%vreg779,%vreg768
2480B		%vreg770<def> = ADDXrr %vreg772, %vreg769; GPR64common:%vreg770 GPR64:%vreg772,%vreg769
2496B		%vreg765<def> = LDRHHui %vreg770, 0; mem:LD2[%arrayidx44] GPR32:%vreg765 GPR64common:%vreg770
2512B		%vreg761<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg761
2528B		%vreg760<def> = LDRWui %vreg761, 15; mem:LD4[%tPos46] GPR32:%vreg760 GPR64common:%vreg761
2544B		%vreg755:sub_32<def,read-undef> = UBFMWri %vreg760, 1, 31; GPR64:%vreg755 GPR32:%vreg760
2576B		%vreg756<def> = UBFMXri %vreg755, 0, 31; GPR64:%vreg756,%vreg755
2592B		%vreg753<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg753
2608B		%vreg752<def> = LDRXui %vreg753, 396; mem:LD8[%ll4] GPR64:%vreg752 GPR64common:%vreg753
2624B		%vreg750<def> = ADDXrr %vreg752, %vreg756; GPR64common:%vreg750 GPR64:%vreg752,%vreg756
2640B		%vreg747<def> = LDRBBui %vreg750, 0; mem:LD1[%arrayidx49] GPR32:%vreg747 GPR64common:%vreg750
2656B		%vreg743<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg743
2672B		%vreg742<def> = LDRWui %vreg743, 15; mem:LD4[%tPos51] GPR32:%vreg742 GPR64common:%vreg743
2688B		%vreg740<def> = ANDWrs %vreg738, %vreg742, 2; GPR32:%vreg740,%vreg738,%vreg742
2704B		%vreg737<def> = LSRVWr %vreg747, %vreg740; GPR32:%vreg737,%vreg747,%vreg740
2720B		%vreg734<def> = ANDWri %vreg737, 3; GPR32common:%vreg734 GPR32:%vreg737
2736B		%vreg732<def> = ORRWrs %vreg765, %vreg734, 16; GPR32:%vreg732,%vreg765 GPR32common:%vreg734
2752B		%vreg729<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg729
2768B		STRWui %vreg732, %vreg729, 15; mem:ST4[%tPos56] GPR32:%vreg732 GPR64common:%vreg729
2784B		%vreg726<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg726
2800B		%vreg725<def> = LDRWui %vreg726, 6; mem:LD4[%rNToGo] GPR32:%vreg725 GPR64common:%vreg726
2816B		CBNZW %vreg725, <BB#18>; GPR32:%vreg725
	    Successors according to CFG: BB#18 BB#15

2832B	BB#15: derived from LLVM BB %if.then.59
	    Predecessors according to CFG: BB#14
2848B		%vreg820<def> = ADRP <ga:@BZ2_rNums>[TF=1]; GPR64common:%vreg820
2864B		%vreg821<def> = ADDXri %vreg820, <ga:@BZ2_rNums>[TF=34], 0; GPR64common:%vreg821,%vreg820
2880B		%vreg831<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg831
2896B		%vreg830<def> = LDRSWui %vreg831, 7; mem:LD4[%rTPos] GPR64:%vreg830 GPR64common:%vreg831
2912B		%vreg823<def> = MOVi64imm 4; GPR64:%vreg823
2928B		%vreg824<def> = MADDXrrr %vreg830, %vreg823, %XZR; GPR64:%vreg824,%vreg830,%vreg823
2944B		%vreg825<def> = ADDXrr %vreg821, %vreg824; GPR64common:%vreg825,%vreg821 GPR64:%vreg824
2960B		%vreg819<def> = LDRWui %vreg825, 0; mem:LD4[%arrayidx61] GPR32:%vreg819 GPR64common:%vreg825
2976B		%vreg817<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg817
2992B		STRWui %vreg819, %vreg817, 6; mem:ST4[%rNToGo62] GPR32:%vreg819 GPR64common:%vreg817
3008B		%vreg814<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg814
3024B		%vreg813<def> = LDRWui %vreg814, 7; mem:LD4[%rTPos63] GPR32common:%vreg813 GPR64common:%vreg814
3040B		%vreg812<def> = ADDWri %vreg813, 1, 0; GPR32common:%vreg812,%vreg813
3056B		STRWui %vreg812, %vreg814, 7; mem:ST4[%rTPos63] GPR32common:%vreg812 GPR64common:%vreg814
3072B		%vreg808<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg808
3088B		%vreg807<def> = LDRWui %vreg808, 7; mem:LD4[%rTPos65] GPR32common:%vreg807 GPR64common:%vreg808
3104B		%WZR<def> = SUBSWri %vreg807, 512, 0, %NZCV<imp-def>; GPR32common:%vreg807
3120B		Bcc 1, <BB#17>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#17 BB#16

3136B	BB#16: derived from LLVM BB %if.then.68
	    Predecessors according to CFG: BB#15
3152B		%vreg833<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg833
3168B		STRWui %WZR, %vreg833, 7; mem:ST4[%rTPos69] GPR64common:%vreg833
	    Successors according to CFG: BB#17

3184B	BB#17: derived from LLVM BB %if.end.70
	    Predecessors according to CFG: BB#15 BB#16
3200B		B <BB#18>
	    Successors according to CFG: BB#18

3216B	BB#18: derived from LLVM BB %if.end.71
	    Predecessors according to CFG: BB#14 BB#17
3232B		%vreg862<def> = MOVi32imm 1; GPR32:%vreg862
3248B		%vreg863<def> = COPY %WZR; GPR32:%vreg863
3264B		%vreg873<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg873
3280B		%vreg872<def> = LDRWui %vreg873, 6; mem:LD4[%rNToGo72] GPR32common:%vreg872 GPR64common:%vreg873
3296B		%vreg871<def> = SUBWri %vreg872, 1, 0; GPR32common:%vreg871,%vreg872
3312B		STRWui %vreg871, %vreg873, 6; mem:ST4[%rNToGo72] GPR32common:%vreg871 GPR64common:%vreg873
3328B		%vreg867<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg867
3344B		%vreg866<def> = LDRWui %vreg867, 6; mem:LD4[%rNToGo74] GPR32common:%vreg866 GPR64common:%vreg867
3360B		%WZR<def> = SUBSWri %vreg866, 1, 0, %NZCV<imp-def>; GPR32common:%vreg866
3376B		%vreg864<def> = CSELWr %vreg862, %vreg863, 0, %NZCV<imp-use,kill>; GPR32:%vreg864,%vreg862,%vreg863
3392B		%vreg860<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg860
3408B		%vreg854<def> = EORWrr %vreg860, %vreg864; GPR32:%vreg854,%vreg860,%vreg864
3440B		STRBBui %vreg854, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg854
3456B		%vreg851<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg851
3472B		%vreg850<def> = LDRWui %vreg851, 273; mem:LD4[%nblock_used80] GPR32common:%vreg850 GPR64common:%vreg851
3488B		%vreg849<def> = ADDWri %vreg850, 1, 0; GPR32common:%vreg849,%vreg850
3504B		STRWui %vreg849, %vreg851, 273; mem:ST4[%nblock_used80] GPR32common:%vreg849 GPR64common:%vreg851
3520B		%vreg845<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg845
3536B		%vreg844<def> = LDRWui %vreg845, 273; mem:LD4[%nblock_used82] GPR32:%vreg844 GPR64common:%vreg845
3552B		%vreg842<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg842
3568B		%vreg839<def> = MOVi64imm 64080; GPR64:%vreg839
3584B		%vreg840<def> = ADDXrr %vreg842, %vreg839; GPR64common:%vreg840 GPR64:%vreg842,%vreg839
3600B		%vreg841<def> = LDRWui %vreg840, 0; mem:LD4[%save_nblock83] GPR32common:%vreg841 GPR64common:%vreg840
3616B		%vreg837<def> = ADDWri %vreg841, 1, 0; GPR32common:%vreg837,%vreg841
3632B		%WZR<def> = SUBSWrr %vreg844, %vreg837, %NZCV<imp-def>; GPR32:%vreg844 GPR32common:%vreg837
3648B		Bcc 1, <BB#20>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#20 BB#19

3664B	BB#19: derived from LLVM BB %if.then.87
	    Predecessors according to CFG: BB#18
3680B		B <BB#2>
	    Successors according to CFG: BB#2

3696B	BB#20: derived from LLVM BB %if.end.88
	    Predecessors according to CFG: BB#18
3712B		%vreg881<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg881
3728B		%vreg878<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg878
3744B		%vreg877<def> = LDRWui %vreg878, 16; mem:LD4[%k090] GPR32:%vreg877 GPR64common:%vreg878
3760B		%WZR<def> = SUBSWrr %vreg881, %vreg877, %NZCV<imp-def>; GPR32:%vreg881,%vreg877
3776B		Bcc 0, <BB#22>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#22 BB#21

3792B	BB#21: derived from LLVM BB %if.then.93
	    Predecessors according to CFG: BB#20
3808B		%vreg1463<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg1463
3824B		%vreg1460<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1460
3840B		STRWui %vreg1463, %vreg1460, 16; mem:ST4[%k095] GPR32:%vreg1463 GPR64common:%vreg1460
3856B		B <BB#2>
	    Successors according to CFG: BB#2

3872B	BB#22: derived from LLVM BB %if.end.96
	    Predecessors according to CFG: BB#20
3888B		%vreg953<def> = MOVi32imm 2; GPR32:%vreg953
3904B		%vreg955<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg955
3920B		STRWui %vreg953, %vreg955, 4; mem:ST4[%state_out_len97] GPR32:%vreg953 GPR64common:%vreg955
3936B		%vreg952<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg952
3952B		%vreg951<def> = LDRWui %vreg952, 15; mem:LD4[%tPos98] GPR32:%vreg951 GPR64common:%vreg952
3968B		%vreg949<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg949
3984B		%vreg948<def> = ADDXri %vreg949, 1096, 0; GPR64sp:%vreg948 GPR64common:%vreg949
4000B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4016B		%W0<def> = COPY %vreg951; GPR32:%vreg951
4032B		%X1<def> = COPY %vreg948; GPR64sp:%vreg948
4048B		BL <ga:@BZ2_indexIntoF>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use,kill>, %W0<imp-def>
4064B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4080B		%vreg942<def> = COPY %W0; GPR32:%vreg942
4096B		%vreg897<def> = MOVi32imm 4; GPR32:%vreg897
4112B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4128B		STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
4144B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4176B		STRBBui %vreg942, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg942
4192B		%vreg939<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg939
4208B		%vreg938:sub_32<def,read-undef> = LDRWui %vreg939, 15; mem:LD4[%tPos103] GPR64:%vreg938 GPR64common:%vreg939
4240B		%vreg932<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg932
4256B		%vreg931<def> = LDRXui %vreg932, 395; mem:LD8[%ll16105] GPR64:%vreg931 GPR64common:%vreg932
4272B		%vreg927<def> = MOVi64imm 2; GPR64:%vreg927
4288B		%vreg928<def> = MADDXrrr %vreg938, %vreg927, %XZR; GPR64:%vreg928,%vreg938,%vreg927
4304B		%vreg929<def> = ADDXrr %vreg931, %vreg928; GPR64common:%vreg929 GPR64:%vreg931,%vreg928
4320B		%vreg924<def> = LDRHHui %vreg929, 0; mem:LD2[%arrayidx106] GPR32:%vreg924 GPR64common:%vreg929
4336B		%vreg920<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg920
4352B		%vreg919<def> = LDRWui %vreg920, 15; mem:LD4[%tPos108] GPR32:%vreg919 GPR64common:%vreg920
4368B		%vreg914:sub_32<def,read-undef> = UBFMWri %vreg919, 1, 31; GPR64:%vreg914 GPR32:%vreg919
4400B		%vreg915<def> = UBFMXri %vreg914, 0, 31; GPR64:%vreg915,%vreg914
4416B		%vreg912<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg912
4432B		%vreg911<def> = LDRXui %vreg912, 396; mem:LD8[%ll4111] GPR64:%vreg911 GPR64common:%vreg912
4448B		%vreg909<def> = ADDXrr %vreg911, %vreg915; GPR64common:%vreg909 GPR64:%vreg911,%vreg915
4464B		%vreg906<def> = LDRBBui %vreg909, 0; mem:LD1[%arrayidx112] GPR32:%vreg906 GPR64common:%vreg909
4480B		%vreg902<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg902
4496B		%vreg901<def> = LDRWui %vreg902, 15; mem:LD4[%tPos114] GPR32:%vreg901 GPR64common:%vreg902
4512B		%vreg899<def> = ANDWrs %vreg897, %vreg901, 2; GPR32:%vreg899,%vreg897,%vreg901
4528B		%vreg896<def> = LSRVWr %vreg906, %vreg899; GPR32:%vreg896,%vreg906,%vreg899
4544B		%vreg893<def> = ANDWri %vreg896, 3; GPR32common:%vreg893 GPR32:%vreg896
4560B		%vreg891<def> = ORRWrs %vreg924, %vreg893, 16; GPR32:%vreg891,%vreg924 GPR32common:%vreg893
4576B		%vreg888<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg888
4592B		STRWui %vreg891, %vreg888, 15; mem:ST4[%tPos121] GPR32:%vreg891 GPR64common:%vreg888
4608B		%vreg885<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg885
4624B		%vreg884<def> = LDRWui %vreg885, 6; mem:LD4[%rNToGo122] GPR32:%vreg884 GPR64common:%vreg885
4640B		CBNZW %vreg884, <BB#26>; GPR32:%vreg884
	    Successors according to CFG: BB#26 BB#23

4656B	BB#23: derived from LLVM BB %if.then.125
	    Predecessors according to CFG: BB#22
4672B		%vreg971<def> = ADRP <ga:@BZ2_rNums>[TF=1]; GPR64common:%vreg971
4688B		%vreg972<def> = ADDXri %vreg971, <ga:@BZ2_rNums>[TF=34], 0; GPR64common:%vreg972,%vreg971
4704B		%vreg982<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg982
4720B		%vreg981<def> = LDRSWui %vreg982, 7; mem:LD4[%rTPos126] GPR64:%vreg981 GPR64common:%vreg982
4736B		%vreg974<def> = MOVi64imm 4; GPR64:%vreg974
4752B		%vreg975<def> = MADDXrrr %vreg981, %vreg974, %XZR; GPR64:%vreg975,%vreg981,%vreg974
4768B		%vreg976<def> = ADDXrr %vreg972, %vreg975; GPR64common:%vreg976,%vreg972 GPR64:%vreg975
4784B		%vreg970<def> = LDRWui %vreg976, 0; mem:LD4[%arrayidx128] GPR32:%vreg970 GPR64common:%vreg976
4800B		%vreg968<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg968
4816B		STRWui %vreg970, %vreg968, 6; mem:ST4[%rNToGo129] GPR32:%vreg970 GPR64common:%vreg968
4832B		%vreg965<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg965
4848B		%vreg964<def> = LDRWui %vreg965, 7; mem:LD4[%rTPos130] GPR32common:%vreg964 GPR64common:%vreg965
4864B		%vreg963<def> = ADDWri %vreg964, 1, 0; GPR32common:%vreg963,%vreg964
4880B		STRWui %vreg963, %vreg965, 7; mem:ST4[%rTPos130] GPR32common:%vreg963 GPR64common:%vreg965
4896B		%vreg959<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg959
4912B		%vreg958<def> = LDRWui %vreg959, 7; mem:LD4[%rTPos132] GPR32common:%vreg958 GPR64common:%vreg959
4928B		%WZR<def> = SUBSWri %vreg958, 512, 0, %NZCV<imp-def>; GPR32common:%vreg958
4944B		Bcc 1, <BB#25>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#25 BB#24

4960B	BB#24: derived from LLVM BB %if.then.135
	    Predecessors according to CFG: BB#23
4976B		%vreg984<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg984
4992B		STRWui %WZR, %vreg984, 7; mem:ST4[%rTPos136] GPR64common:%vreg984
	    Successors according to CFG: BB#25

5008B	BB#25: derived from LLVM BB %if.end.137
	    Predecessors according to CFG: BB#23 BB#24
5024B		B <BB#26>
	    Successors according to CFG: BB#26

5040B	BB#26: derived from LLVM BB %if.end.138
	    Predecessors according to CFG: BB#22 BB#25
5056B		%vreg1013<def> = MOVi32imm 1; GPR32:%vreg1013
5072B		%vreg1014<def> = COPY %WZR; GPR32:%vreg1014
5088B		%vreg1024<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1024
5104B		%vreg1023<def> = LDRWui %vreg1024, 6; mem:LD4[%rNToGo139] GPR32common:%vreg1023 GPR64common:%vreg1024
5120B		%vreg1022<def> = SUBWri %vreg1023, 1, 0; GPR32common:%vreg1022,%vreg1023
5136B		STRWui %vreg1022, %vreg1024, 6; mem:ST4[%rNToGo139] GPR32common:%vreg1022 GPR64common:%vreg1024
5152B		%vreg1018<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1018
5168B		%vreg1017<def> = LDRWui %vreg1018, 6; mem:LD4[%rNToGo141] GPR32common:%vreg1017 GPR64common:%vreg1018
5184B		%WZR<def> = SUBSWri %vreg1017, 1, 0, %NZCV<imp-def>; GPR32common:%vreg1017
5200B		%vreg1015<def> = CSELWr %vreg1013, %vreg1014, 0, %NZCV<imp-use,kill>; GPR32:%vreg1015,%vreg1013,%vreg1014
5216B		%vreg1011<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg1011
5232B		%vreg1005<def> = EORWrr %vreg1011, %vreg1015; GPR32:%vreg1005,%vreg1011,%vreg1015
5264B		STRBBui %vreg1005, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg1005
5280B		%vreg1002<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1002
5296B		%vreg1001<def> = LDRWui %vreg1002, 273; mem:LD4[%nblock_used148] GPR32common:%vreg1001 GPR64common:%vreg1002
5312B		%vreg1000<def> = ADDWri %vreg1001, 1, 0; GPR32common:%vreg1000,%vreg1001
5328B		STRWui %vreg1000, %vreg1002, 273; mem:ST4[%nblock_used148] GPR32common:%vreg1000 GPR64common:%vreg1002
5344B		%vreg996<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg996
5360B		%vreg995<def> = LDRWui %vreg996, 273; mem:LD4[%nblock_used150] GPR32:%vreg995 GPR64common:%vreg996
5376B		%vreg993<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg993
5392B		%vreg990<def> = MOVi64imm 64080; GPR64:%vreg990
5408B		%vreg991<def> = ADDXrr %vreg993, %vreg990; GPR64common:%vreg991 GPR64:%vreg993,%vreg990
5424B		%vreg992<def> = LDRWui %vreg991, 0; mem:LD4[%save_nblock151] GPR32common:%vreg992 GPR64common:%vreg991
5440B		%vreg988<def> = ADDWri %vreg992, 1, 0; GPR32common:%vreg988,%vreg992
5456B		%WZR<def> = SUBSWrr %vreg995, %vreg988, %NZCV<imp-def>; GPR32:%vreg995 GPR32common:%vreg988
5472B		Bcc 1, <BB#28>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#28 BB#27

5488B	BB#27: derived from LLVM BB %if.then.155
	    Predecessors according to CFG: BB#26
5504B		B <BB#2>
	    Successors according to CFG: BB#2

5520B	BB#28: derived from LLVM BB %if.end.156
	    Predecessors according to CFG: BB#26
5536B		%vreg1032<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg1032
5552B		%vreg1029<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1029
5568B		%vreg1028<def> = LDRWui %vreg1029, 16; mem:LD4[%k0158] GPR32:%vreg1028 GPR64common:%vreg1029
5584B		%WZR<def> = SUBSWrr %vreg1032, %vreg1028, %NZCV<imp-def>; GPR32:%vreg1032,%vreg1028
5600B		Bcc 0, <BB#30>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#30 BB#29

5616B	BB#29: derived from LLVM BB %if.then.161
	    Predecessors according to CFG: BB#28
5632B		%vreg1457<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg1457
5648B		%vreg1454<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1454
5664B		STRWui %vreg1457, %vreg1454, 16; mem:ST4[%k0163] GPR32:%vreg1457 GPR64common:%vreg1454
5680B		B <BB#2>
	    Successors according to CFG: BB#2

5696B	BB#30: derived from LLVM BB %if.end.164
	    Predecessors according to CFG: BB#28
5712B		%vreg1104<def> = MOVi32imm 3; GPR32:%vreg1104
5728B		%vreg1106<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1106
5744B		STRWui %vreg1104, %vreg1106, 4; mem:ST4[%state_out_len165] GPR32:%vreg1104 GPR64common:%vreg1106
5760B		%vreg1103<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1103
5776B		%vreg1102<def> = LDRWui %vreg1103, 15; mem:LD4[%tPos166] GPR32:%vreg1102 GPR64common:%vreg1103
5792B		%vreg1100<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1100
5808B		%vreg1099<def> = ADDXri %vreg1100, 1096, 0; GPR64sp:%vreg1099 GPR64common:%vreg1100
5824B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5840B		%W0<def> = COPY %vreg1102; GPR32:%vreg1102
5856B		%X1<def> = COPY %vreg1099; GPR64sp:%vreg1099
5872B		BL <ga:@BZ2_indexIntoF>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use,kill>, %W0<imp-def>
5888B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5904B		%vreg1093<def> = COPY %W0; GPR32:%vreg1093
5920B		%vreg1048<def> = MOVi32imm 4; GPR32:%vreg1048
5936B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5952B		STACKMAP 3, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
5968B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
6000B		STRBBui %vreg1093, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg1093
6016B		%vreg1090<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1090
6032B		%vreg1089:sub_32<def,read-undef> = LDRWui %vreg1090, 15; mem:LD4[%tPos171] GPR64:%vreg1089 GPR64common:%vreg1090
6064B		%vreg1083<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1083
6080B		%vreg1082<def> = LDRXui %vreg1083, 395; mem:LD8[%ll16173] GPR64:%vreg1082 GPR64common:%vreg1083
6096B		%vreg1078<def> = MOVi64imm 2; GPR64:%vreg1078
6112B		%vreg1079<def> = MADDXrrr %vreg1089, %vreg1078, %XZR; GPR64:%vreg1079,%vreg1089,%vreg1078
6128B		%vreg1080<def> = ADDXrr %vreg1082, %vreg1079; GPR64common:%vreg1080 GPR64:%vreg1082,%vreg1079
6144B		%vreg1075<def> = LDRHHui %vreg1080, 0; mem:LD2[%arrayidx174] GPR32:%vreg1075 GPR64common:%vreg1080
6160B		%vreg1071<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1071
6176B		%vreg1070<def> = LDRWui %vreg1071, 15; mem:LD4[%tPos176] GPR32:%vreg1070 GPR64common:%vreg1071
6192B		%vreg1065:sub_32<def,read-undef> = UBFMWri %vreg1070, 1, 31; GPR64:%vreg1065 GPR32:%vreg1070
6224B		%vreg1066<def> = UBFMXri %vreg1065, 0, 31; GPR64:%vreg1066,%vreg1065
6240B		%vreg1063<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1063
6256B		%vreg1062<def> = LDRXui %vreg1063, 396; mem:LD8[%ll4179] GPR64:%vreg1062 GPR64common:%vreg1063
6272B		%vreg1060<def> = ADDXrr %vreg1062, %vreg1066; GPR64common:%vreg1060 GPR64:%vreg1062,%vreg1066
6288B		%vreg1057<def> = LDRBBui %vreg1060, 0; mem:LD1[%arrayidx180] GPR32:%vreg1057 GPR64common:%vreg1060
6304B		%vreg1053<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1053
6320B		%vreg1052<def> = LDRWui %vreg1053, 15; mem:LD4[%tPos182] GPR32:%vreg1052 GPR64common:%vreg1053
6336B		%vreg1050<def> = ANDWrs %vreg1048, %vreg1052, 2; GPR32:%vreg1050,%vreg1048,%vreg1052
6352B		%vreg1047<def> = LSRVWr %vreg1057, %vreg1050; GPR32:%vreg1047,%vreg1057,%vreg1050
6368B		%vreg1044<def> = ANDWri %vreg1047, 3; GPR32common:%vreg1044 GPR32:%vreg1047
6384B		%vreg1042<def> = ORRWrs %vreg1075, %vreg1044, 16; GPR32:%vreg1042,%vreg1075 GPR32common:%vreg1044
6400B		%vreg1039<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1039
6416B		STRWui %vreg1042, %vreg1039, 15; mem:ST4[%tPos189] GPR32:%vreg1042 GPR64common:%vreg1039
6432B		%vreg1036<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1036
6448B		%vreg1035<def> = LDRWui %vreg1036, 6; mem:LD4[%rNToGo190] GPR32:%vreg1035 GPR64common:%vreg1036
6464B		CBNZW %vreg1035, <BB#34>; GPR32:%vreg1035
	    Successors according to CFG: BB#34 BB#31

6480B	BB#31: derived from LLVM BB %if.then.193
	    Predecessors according to CFG: BB#30
6496B		%vreg1122<def> = ADRP <ga:@BZ2_rNums>[TF=1]; GPR64common:%vreg1122
6512B		%vreg1123<def> = ADDXri %vreg1122, <ga:@BZ2_rNums>[TF=34], 0; GPR64common:%vreg1123,%vreg1122
6528B		%vreg1133<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1133
6544B		%vreg1132<def> = LDRSWui %vreg1133, 7; mem:LD4[%rTPos194] GPR64:%vreg1132 GPR64common:%vreg1133
6560B		%vreg1125<def> = MOVi64imm 4; GPR64:%vreg1125
6576B		%vreg1126<def> = MADDXrrr %vreg1132, %vreg1125, %XZR; GPR64:%vreg1126,%vreg1132,%vreg1125
6592B		%vreg1127<def> = ADDXrr %vreg1123, %vreg1126; GPR64common:%vreg1127,%vreg1123 GPR64:%vreg1126
6608B		%vreg1121<def> = LDRWui %vreg1127, 0; mem:LD4[%arrayidx196] GPR32:%vreg1121 GPR64common:%vreg1127
6624B		%vreg1119<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1119
6640B		STRWui %vreg1121, %vreg1119, 6; mem:ST4[%rNToGo197] GPR32:%vreg1121 GPR64common:%vreg1119
6656B		%vreg1116<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1116
6672B		%vreg1115<def> = LDRWui %vreg1116, 7; mem:LD4[%rTPos198] GPR32common:%vreg1115 GPR64common:%vreg1116
6688B		%vreg1114<def> = ADDWri %vreg1115, 1, 0; GPR32common:%vreg1114,%vreg1115
6704B		STRWui %vreg1114, %vreg1116, 7; mem:ST4[%rTPos198] GPR32common:%vreg1114 GPR64common:%vreg1116
6720B		%vreg1110<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1110
6736B		%vreg1109<def> = LDRWui %vreg1110, 7; mem:LD4[%rTPos200] GPR32common:%vreg1109 GPR64common:%vreg1110
6752B		%WZR<def> = SUBSWri %vreg1109, 512, 0, %NZCV<imp-def>; GPR32common:%vreg1109
6768B		Bcc 1, <BB#33>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#33 BB#32

6784B	BB#32: derived from LLVM BB %if.then.203
	    Predecessors according to CFG: BB#31
6800B		%vreg1135<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1135
6816B		STRWui %WZR, %vreg1135, 7; mem:ST4[%rTPos204] GPR64common:%vreg1135
	    Successors according to CFG: BB#33

6832B	BB#33: derived from LLVM BB %if.end.205
	    Predecessors according to CFG: BB#31 BB#32
6848B		B <BB#34>
	    Successors according to CFG: BB#34

6864B	BB#34: derived from LLVM BB %if.end.206
	    Predecessors according to CFG: BB#30 BB#33
6880B		%vreg1164<def> = MOVi32imm 1; GPR32:%vreg1164
6896B		%vreg1165<def> = COPY %WZR; GPR32:%vreg1165
6912B		%vreg1175<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1175
6928B		%vreg1174<def> = LDRWui %vreg1175, 6; mem:LD4[%rNToGo207] GPR32common:%vreg1174 GPR64common:%vreg1175
6944B		%vreg1173<def> = SUBWri %vreg1174, 1, 0; GPR32common:%vreg1173,%vreg1174
6960B		STRWui %vreg1173, %vreg1175, 6; mem:ST4[%rNToGo207] GPR32common:%vreg1173 GPR64common:%vreg1175
6976B		%vreg1169<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1169
6992B		%vreg1168<def> = LDRWui %vreg1169, 6; mem:LD4[%rNToGo209] GPR32common:%vreg1168 GPR64common:%vreg1169
7008B		%WZR<def> = SUBSWri %vreg1168, 1, 0, %NZCV<imp-def>; GPR32common:%vreg1168
7024B		%vreg1166<def> = CSELWr %vreg1164, %vreg1165, 0, %NZCV<imp-use,kill>; GPR32:%vreg1166,%vreg1164,%vreg1165
7040B		%vreg1162<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg1162
7056B		%vreg1156<def> = EORWrr %vreg1162, %vreg1166; GPR32:%vreg1156,%vreg1162,%vreg1166
7088B		STRBBui %vreg1156, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg1156
7104B		%vreg1153<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1153
7120B		%vreg1152<def> = LDRWui %vreg1153, 273; mem:LD4[%nblock_used216] GPR32common:%vreg1152 GPR64common:%vreg1153
7136B		%vreg1151<def> = ADDWri %vreg1152, 1, 0; GPR32common:%vreg1151,%vreg1152
7152B		STRWui %vreg1151, %vreg1153, 273; mem:ST4[%nblock_used216] GPR32common:%vreg1151 GPR64common:%vreg1153
7168B		%vreg1147<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1147
7184B		%vreg1146<def> = LDRWui %vreg1147, 273; mem:LD4[%nblock_used218] GPR32:%vreg1146 GPR64common:%vreg1147
7200B		%vreg1144<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg1144
7216B		%vreg1141<def> = MOVi64imm 64080; GPR64:%vreg1141
7232B		%vreg1142<def> = ADDXrr %vreg1144, %vreg1141; GPR64common:%vreg1142 GPR64:%vreg1144,%vreg1141
7248B		%vreg1143<def> = LDRWui %vreg1142, 0; mem:LD4[%save_nblock219] GPR32common:%vreg1143 GPR64common:%vreg1142
7264B		%vreg1139<def> = ADDWri %vreg1143, 1, 0; GPR32common:%vreg1139,%vreg1143
7280B		%WZR<def> = SUBSWrr %vreg1146, %vreg1139, %NZCV<imp-def>; GPR32:%vreg1146 GPR32common:%vreg1139
7296B		Bcc 1, <BB#36>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#36 BB#35

7312B	BB#35: derived from LLVM BB %if.then.223
	    Predecessors according to CFG: BB#34
7328B		B <BB#2>
	    Successors according to CFG: BB#2

7344B	BB#36: derived from LLVM BB %if.end.224
	    Predecessors according to CFG: BB#34
7360B		%vreg1183<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg1183
7376B		%vreg1180<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1180
7392B		%vreg1179<def> = LDRWui %vreg1180, 16; mem:LD4[%k0226] GPR32:%vreg1179 GPR64common:%vreg1180
7408B		%WZR<def> = SUBSWrr %vreg1183, %vreg1179, %NZCV<imp-def>; GPR32:%vreg1183,%vreg1179
7424B		Bcc 0, <BB#38>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#38 BB#37

7440B	BB#37: derived from LLVM BB %if.then.229
	    Predecessors according to CFG: BB#36
7456B		%vreg1451<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg1451
7472B		%vreg1448<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1448
7488B		STRWui %vreg1451, %vreg1448, 16; mem:ST4[%k0231] GPR32:%vreg1451 GPR64common:%vreg1448
7504B		B <BB#2>
	    Successors according to CFG: BB#2

7520B	BB#38: derived from LLVM BB %if.end.232
	    Predecessors according to CFG: BB#36
7536B		%vreg1254<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1254
7552B		%vreg1253<def> = LDRWui %vreg1254, 15; mem:LD4[%tPos233] GPR32:%vreg1253 GPR64common:%vreg1254
7568B		%vreg1251<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1251
7584B		%vreg1250<def> = ADDXri %vreg1251, 1096, 0; GPR64sp:%vreg1250 GPR64common:%vreg1251
7600B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
7616B		%W0<def> = COPY %vreg1253; GPR32:%vreg1253
7632B		%X1<def> = COPY %vreg1250; GPR64sp:%vreg1250
7648B		BL <ga:@BZ2_indexIntoF>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use,kill>, %W0<imp-def>
7664B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
7680B		%vreg1244<def> = COPY %W0; GPR32:%vreg1244
7696B		%vreg1199<def> = MOVi32imm 4; GPR32:%vreg1199
7712B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
7728B		STACKMAP 4, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
7744B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
7776B		STRBBui %vreg1244, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg1244
7792B		%vreg1241<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1241
7808B		%vreg1240:sub_32<def,read-undef> = LDRWui %vreg1241, 15; mem:LD4[%tPos238] GPR64:%vreg1240 GPR64common:%vreg1241
7840B		%vreg1234<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1234
7856B		%vreg1233<def> = LDRXui %vreg1234, 395; mem:LD8[%ll16240] GPR64:%vreg1233 GPR64common:%vreg1234
7872B		%vreg1229<def> = MOVi64imm 2; GPR64:%vreg1229
7888B		%vreg1230<def> = MADDXrrr %vreg1240, %vreg1229, %XZR; GPR64:%vreg1230,%vreg1240,%vreg1229
7904B		%vreg1231<def> = ADDXrr %vreg1233, %vreg1230; GPR64common:%vreg1231 GPR64:%vreg1233,%vreg1230
7920B		%vreg1226<def> = LDRHHui %vreg1231, 0; mem:LD2[%arrayidx241] GPR32:%vreg1226 GPR64common:%vreg1231
7936B		%vreg1222<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1222
7952B		%vreg1221<def> = LDRWui %vreg1222, 15; mem:LD4[%tPos243] GPR32:%vreg1221 GPR64common:%vreg1222
7968B		%vreg1216:sub_32<def,read-undef> = UBFMWri %vreg1221, 1, 31; GPR64:%vreg1216 GPR32:%vreg1221
8000B		%vreg1217<def> = UBFMXri %vreg1216, 0, 31; GPR64:%vreg1217,%vreg1216
8016B		%vreg1214<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1214
8032B		%vreg1213<def> = LDRXui %vreg1214, 396; mem:LD8[%ll4246] GPR64:%vreg1213 GPR64common:%vreg1214
8048B		%vreg1211<def> = ADDXrr %vreg1213, %vreg1217; GPR64common:%vreg1211 GPR64:%vreg1213,%vreg1217
8064B		%vreg1208<def> = LDRBBui %vreg1211, 0; mem:LD1[%arrayidx247] GPR32:%vreg1208 GPR64common:%vreg1211
8080B		%vreg1204<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1204
8096B		%vreg1203<def> = LDRWui %vreg1204, 15; mem:LD4[%tPos249] GPR32:%vreg1203 GPR64common:%vreg1204
8112B		%vreg1201<def> = ANDWrs %vreg1199, %vreg1203, 2; GPR32:%vreg1201,%vreg1199,%vreg1203
8128B		%vreg1198<def> = LSRVWr %vreg1208, %vreg1201; GPR32:%vreg1198,%vreg1208,%vreg1201
8144B		%vreg1195<def> = ANDWri %vreg1198, 3; GPR32common:%vreg1195 GPR32:%vreg1198
8160B		%vreg1193<def> = ORRWrs %vreg1226, %vreg1195, 16; GPR32:%vreg1193,%vreg1226 GPR32common:%vreg1195
8176B		%vreg1190<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1190
8192B		STRWui %vreg1193, %vreg1190, 15; mem:ST4[%tPos256] GPR32:%vreg1193 GPR64common:%vreg1190
8208B		%vreg1187<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1187
8224B		%vreg1186<def> = LDRWui %vreg1187, 6; mem:LD4[%rNToGo257] GPR32:%vreg1186 GPR64common:%vreg1187
8240B		CBNZW %vreg1186, <BB#42>; GPR32:%vreg1186
	    Successors according to CFG: BB#42 BB#39

8256B	BB#39: derived from LLVM BB %if.then.260
	    Predecessors according to CFG: BB#38
8272B		%vreg1270<def> = ADRP <ga:@BZ2_rNums>[TF=1]; GPR64common:%vreg1270
8288B		%vreg1271<def> = ADDXri %vreg1270, <ga:@BZ2_rNums>[TF=34], 0; GPR64common:%vreg1271,%vreg1270
8304B		%vreg1281<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1281
8320B		%vreg1280<def> = LDRSWui %vreg1281, 7; mem:LD4[%rTPos261] GPR64:%vreg1280 GPR64common:%vreg1281
8336B		%vreg1273<def> = MOVi64imm 4; GPR64:%vreg1273
8352B		%vreg1274<def> = MADDXrrr %vreg1280, %vreg1273, %XZR; GPR64:%vreg1274,%vreg1280,%vreg1273
8368B		%vreg1275<def> = ADDXrr %vreg1271, %vreg1274; GPR64common:%vreg1275,%vreg1271 GPR64:%vreg1274
8384B		%vreg1269<def> = LDRWui %vreg1275, 0; mem:LD4[%arrayidx263] GPR32:%vreg1269 GPR64common:%vreg1275
8400B		%vreg1267<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1267
8416B		STRWui %vreg1269, %vreg1267, 6; mem:ST4[%rNToGo264] GPR32:%vreg1269 GPR64common:%vreg1267
8432B		%vreg1264<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1264
8448B		%vreg1263<def> = LDRWui %vreg1264, 7; mem:LD4[%rTPos265] GPR32common:%vreg1263 GPR64common:%vreg1264
8464B		%vreg1262<def> = ADDWri %vreg1263, 1, 0; GPR32common:%vreg1262,%vreg1263
8480B		STRWui %vreg1262, %vreg1264, 7; mem:ST4[%rTPos265] GPR32common:%vreg1262 GPR64common:%vreg1264
8496B		%vreg1258<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1258
8512B		%vreg1257<def> = LDRWui %vreg1258, 7; mem:LD4[%rTPos267] GPR32common:%vreg1257 GPR64common:%vreg1258
8528B		%WZR<def> = SUBSWri %vreg1257, 512, 0, %NZCV<imp-def>; GPR32common:%vreg1257
8544B		Bcc 1, <BB#41>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#41 BB#40

8560B	BB#40: derived from LLVM BB %if.then.270
	    Predecessors according to CFG: BB#39
8576B		%vreg1283<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1283
8592B		STRWui %WZR, %vreg1283, 7; mem:ST4[%rTPos271] GPR64common:%vreg1283
	    Successors according to CFG: BB#41

8608B	BB#41: derived from LLVM BB %if.end.272
	    Predecessors according to CFG: BB#39 BB#40
8624B		B <BB#42>
	    Successors according to CFG: BB#42

8640B	BB#42: derived from LLVM BB %if.end.273
	    Predecessors according to CFG: BB#38 BB#41
8656B		%vreg1379<def> = MOVi32imm 1; GPR32:%vreg1379
8672B		%vreg1380<def> = COPY %WZR; GPR32:%vreg1380
8688B		%vreg1390<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1390
8704B		%vreg1389<def> = LDRWui %vreg1390, 6; mem:LD4[%rNToGo274] GPR32common:%vreg1389 GPR64common:%vreg1390
8720B		%vreg1388<def> = SUBWri %vreg1389, 1, 0; GPR32common:%vreg1388,%vreg1389
8736B		STRWui %vreg1388, %vreg1390, 6; mem:ST4[%rNToGo274] GPR32common:%vreg1388 GPR64common:%vreg1390
8752B		%vreg1384<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1384
8768B		%vreg1383<def> = LDRWui %vreg1384, 6; mem:LD4[%rNToGo276] GPR32common:%vreg1383 GPR64common:%vreg1384
8784B		%WZR<def> = SUBSWri %vreg1383, 1, 0, %NZCV<imp-def>; GPR32common:%vreg1383
8800B		%vreg1381<def> = CSELWr %vreg1379, %vreg1380, 0, %NZCV<imp-use,kill>; GPR32:%vreg1381,%vreg1379,%vreg1380
8816B		%vreg1377<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg1377
8832B		%vreg1371<def> = EORWrr %vreg1377, %vreg1381; GPR32:%vreg1371,%vreg1377,%vreg1381
8864B		STRBBui %vreg1371, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg1371
8880B		%vreg1368<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1368
8896B		%vreg1367<def> = LDRWui %vreg1368, 273; mem:LD4[%nblock_used283] GPR32common:%vreg1367 GPR64common:%vreg1368
8912B		%vreg1366<def> = ADDWri %vreg1367, 1, 0; GPR32common:%vreg1366,%vreg1367
8928B		STRWui %vreg1366, %vreg1368, 273; mem:ST4[%nblock_used283] GPR32common:%vreg1366 GPR64common:%vreg1368
8944B		%vreg1362<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32common:%vreg1362
8960B		%vreg1359<def> = ADDWri %vreg1362, 4, 0; GPR32common:%vreg1359,%vreg1362
8976B		%vreg1357<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1357
8992B		STRWui %vreg1359, %vreg1357, 4; mem:ST4[%state_out_len287] GPR32common:%vreg1359 GPR64common:%vreg1357
9008B		%vreg1354<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1354
9024B		%vreg1353<def> = LDRWui %vreg1354, 15; mem:LD4[%tPos288] GPR32:%vreg1353 GPR64common:%vreg1354
9040B		%vreg1351<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1351
9056B		%vreg1350<def> = ADDXri %vreg1351, 1096, 0; GPR64sp:%vreg1350 GPR64common:%vreg1351
9072B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
9088B		%W0<def> = COPY %vreg1353; GPR32:%vreg1353
9104B		%X1<def> = COPY %vreg1350; GPR64sp:%vreg1350
9120B		BL <ga:@BZ2_indexIntoF>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use,kill>, %W0<imp-def>
9136B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
9152B		%vreg1347<def> = COPY %W0; GPR32:%vreg1347
9168B		%vreg1299<def> = MOVi32imm 4; GPR32:%vreg1299
9184B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
9200B		STACKMAP 5, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
9216B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
9232B		%vreg1344<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1344
9248B		STRWui %vreg1347, %vreg1344, 16; mem:ST4[%k0292] GPR32:%vreg1347 GPR64common:%vreg1344
9264B		%vreg1341<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1341
9280B		%vreg1340:sub_32<def,read-undef> = LDRWui %vreg1341, 15; mem:LD4[%tPos293] GPR64:%vreg1340 GPR64common:%vreg1341
9312B		%vreg1334<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1334
9328B		%vreg1333<def> = LDRXui %vreg1334, 395; mem:LD8[%ll16295] GPR64:%vreg1333 GPR64common:%vreg1334
9344B		%vreg1329<def> = MOVi64imm 2; GPR64:%vreg1329
9360B		%vreg1330<def> = MADDXrrr %vreg1340, %vreg1329, %XZR; GPR64:%vreg1330,%vreg1340,%vreg1329
9376B		%vreg1331<def> = ADDXrr %vreg1333, %vreg1330; GPR64common:%vreg1331 GPR64:%vreg1333,%vreg1330
9392B		%vreg1326<def> = LDRHHui %vreg1331, 0; mem:LD2[%arrayidx296] GPR32:%vreg1326 GPR64common:%vreg1331
9408B		%vreg1322<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1322
9424B		%vreg1321<def> = LDRWui %vreg1322, 15; mem:LD4[%tPos298] GPR32:%vreg1321 GPR64common:%vreg1322
9440B		%vreg1316:sub_32<def,read-undef> = UBFMWri %vreg1321, 1, 31; GPR64:%vreg1316 GPR32:%vreg1321
9472B		%vreg1317<def> = UBFMXri %vreg1316, 0, 31; GPR64:%vreg1317,%vreg1316
9488B		%vreg1314<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1314
9504B		%vreg1313<def> = LDRXui %vreg1314, 396; mem:LD8[%ll4301] GPR64:%vreg1313 GPR64common:%vreg1314
9520B		%vreg1311<def> = ADDXrr %vreg1313, %vreg1317; GPR64common:%vreg1311 GPR64:%vreg1313,%vreg1317
9536B		%vreg1308<def> = LDRBBui %vreg1311, 0; mem:LD1[%arrayidx302] GPR32:%vreg1308 GPR64common:%vreg1311
9552B		%vreg1304<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1304
9568B		%vreg1303<def> = LDRWui %vreg1304, 15; mem:LD4[%tPos304] GPR32:%vreg1303 GPR64common:%vreg1304
9584B		%vreg1301<def> = ANDWrs %vreg1299, %vreg1303, 2; GPR32:%vreg1301,%vreg1299,%vreg1303
9600B		%vreg1298<def> = LSRVWr %vreg1308, %vreg1301; GPR32:%vreg1298,%vreg1308,%vreg1301
9616B		%vreg1295<def> = ANDWri %vreg1298, 3; GPR32common:%vreg1295 GPR32:%vreg1298
9632B		%vreg1293<def> = ORRWrs %vreg1326, %vreg1295, 16; GPR32:%vreg1293,%vreg1326 GPR32common:%vreg1295
9648B		%vreg1290<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1290
9664B		STRWui %vreg1293, %vreg1290, 15; mem:ST4[%tPos311] GPR32:%vreg1293 GPR64common:%vreg1290
9680B		%vreg1287<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1287
9696B		%vreg1286<def> = LDRWui %vreg1287, 6; mem:LD4[%rNToGo312] GPR32:%vreg1286 GPR64common:%vreg1287
9712B		CBNZW %vreg1286, <BB#46>; GPR32:%vreg1286
	    Successors according to CFG: BB#46 BB#43

9728B	BB#43: derived from LLVM BB %if.then.315
	    Predecessors according to CFG: BB#42
9744B		%vreg1406<def> = ADRP <ga:@BZ2_rNums>[TF=1]; GPR64common:%vreg1406
9760B		%vreg1407<def> = ADDXri %vreg1406, <ga:@BZ2_rNums>[TF=34], 0; GPR64common:%vreg1407,%vreg1406
9776B		%vreg1417<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1417
9792B		%vreg1416<def> = LDRSWui %vreg1417, 7; mem:LD4[%rTPos316] GPR64:%vreg1416 GPR64common:%vreg1417
9808B		%vreg1409<def> = MOVi64imm 4; GPR64:%vreg1409
9824B		%vreg1410<def> = MADDXrrr %vreg1416, %vreg1409, %XZR; GPR64:%vreg1410,%vreg1416,%vreg1409
9840B		%vreg1411<def> = ADDXrr %vreg1407, %vreg1410; GPR64common:%vreg1411,%vreg1407 GPR64:%vreg1410
9856B		%vreg1405<def> = LDRWui %vreg1411, 0; mem:LD4[%arrayidx318] GPR32:%vreg1405 GPR64common:%vreg1411
9872B		%vreg1403<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1403
9888B		STRWui %vreg1405, %vreg1403, 6; mem:ST4[%rNToGo319] GPR32:%vreg1405 GPR64common:%vreg1403
9904B		%vreg1400<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1400
9920B		%vreg1399<def> = LDRWui %vreg1400, 7; mem:LD4[%rTPos320] GPR32common:%vreg1399 GPR64common:%vreg1400
9936B		%vreg1398<def> = ADDWri %vreg1399, 1, 0; GPR32common:%vreg1398,%vreg1399
9952B		STRWui %vreg1398, %vreg1400, 7; mem:ST4[%rTPos320] GPR32common:%vreg1398 GPR64common:%vreg1400
9968B		%vreg1394<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1394
9984B		%vreg1393<def> = LDRWui %vreg1394, 7; mem:LD4[%rTPos322] GPR32common:%vreg1393 GPR64common:%vreg1394
10000B		%WZR<def> = SUBSWri %vreg1393, 512, 0, %NZCV<imp-def>; GPR32common:%vreg1393
10016B		Bcc 1, <BB#45>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#45 BB#44

10032B	BB#44: derived from LLVM BB %if.then.325
	    Predecessors according to CFG: BB#43
10048B		%vreg1419<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1419
10064B		STRWui %WZR, %vreg1419, 7; mem:ST4[%rTPos326] GPR64common:%vreg1419
	    Successors according to CFG: BB#45

10080B	BB#45: derived from LLVM BB %if.end.327
	    Predecessors according to CFG: BB#43 BB#44
10096B		B <BB#46>
	    Successors according to CFG: BB#46

10112B	BB#46: derived from LLVM BB %if.end.328
	    Predecessors according to CFG: BB#42 BB#45
10128B		%vreg1434<def> = MOVi32imm 1; GPR32:%vreg1434
10144B		%vreg1435<def> = COPY %WZR; GPR32:%vreg1435
10160B		%vreg1445<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1445
10176B		%vreg1444<def> = LDRWui %vreg1445, 6; mem:LD4[%rNToGo329] GPR32common:%vreg1444 GPR64common:%vreg1445
10192B		%vreg1443<def> = SUBWri %vreg1444, 1, 0; GPR32common:%vreg1443,%vreg1444
10208B		STRWui %vreg1443, %vreg1445, 6; mem:ST4[%rNToGo329] GPR32common:%vreg1443 GPR64common:%vreg1445
10224B		%vreg1439<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1439
10240B		%vreg1438<def> = LDRWui %vreg1439, 6; mem:LD4[%rNToGo331] GPR32common:%vreg1438 GPR64common:%vreg1439
10256B		%WZR<def> = SUBSWri %vreg1438, 1, 0, %NZCV<imp-def>; GPR32common:%vreg1438
10272B		%vreg1436<def> = CSELWr %vreg1434, %vreg1435, 0, %NZCV<imp-use,kill>; GPR32:%vreg1436,%vreg1434,%vreg1435
10288B		%vreg1432<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1432
10304B		%vreg1431<def> = LDRWui %vreg1432, 16; mem:LD4[%k0335] GPR32:%vreg1431 GPR64common:%vreg1432
10320B		%vreg1430<def> = EORWrr %vreg1431, %vreg1436; GPR32:%vreg1430,%vreg1431,%vreg1436
10336B		STRWui %vreg1430, %vreg1432, 16; mem:ST4[%k0335] GPR32:%vreg1430 GPR64common:%vreg1432
10352B		%vreg1425<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1425
10368B		%vreg1424<def> = LDRWui %vreg1425, 273; mem:LD4[%nblock_used337] GPR32common:%vreg1424 GPR64common:%vreg1425
10384B		%vreg1423<def> = ADDWri %vreg1424, 1, 0; GPR32common:%vreg1423,%vreg1424
10400B		STRWui %vreg1423, %vreg1425, 273; mem:ST4[%nblock_used337] GPR32common:%vreg1423 GPR64common:%vreg1425
10416B		B <BB#2>
	    Successors according to CFG: BB#2

10432B	BB#47: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#0
10448B		B <BB#48>
	    Successors according to CFG: BB#48

10464B	BB#48: derived from LLVM BB %while.body.339
	    Predecessors according to CFG: BB#47 BB#72 BB#71 BB#69 BB#67 BB#65 BB#63 BB#61
10480B		B <BB#49>
	    Successors according to CFG: BB#49

10496B	BB#49: derived from LLVM BB %while.body.341
	    Predecessors according to CFG: BB#48 BB#55
10512B		%vreg17<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg17
10528B		%vreg16<def> = LDRXui %vreg17, 0; mem:LD8[%strm342] GPR64common:%vreg16,%vreg17
10544B		%vreg14<def> = LDRWui %vreg16, 8; mem:LD4[%avail_out343] GPR32:%vreg14 GPR64common:%vreg16
10560B		CBNZW %vreg14, <BB#51>; GPR32:%vreg14
	    Successors according to CFG: BB#51 BB#50

10576B	BB#50: derived from LLVM BB %if.then.346
	    Predecessors according to CFG: BB#49
10592B		STRBBui %WZR, <fi#0>, 0; mem:ST1[FixedStack0]
10608B		B <BB#73>
	    Successors according to CFG: BB#73

10624B	BB#51: derived from LLVM BB %if.end.347
	    Predecessors according to CFG: BB#49
10640B		%vreg21<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg21
10656B		%vreg20<def> = LDRWui %vreg21, 4; mem:LD4[%state_out_len348] GPR32:%vreg20 GPR64common:%vreg21
10672B		CBNZW %vreg20, <BB#53>; GPR32:%vreg20
	    Successors according to CFG: BB#53 BB#52

10688B	BB#52: derived from LLVM BB %if.then.351
	    Predecessors according to CFG: BB#51
10704B		B <BB#56>
	    Successors according to CFG: BB#56

10720B	BB#53: derived from LLVM BB %if.end.352
	    Predecessors according to CFG: BB#51
10736B		%vreg66<def> = ADRP <ga:@BZ2_crc32Table>[TF=1]; GPR64common:%vreg66
10752B		%vreg67<def> = ADDXri %vreg66, <ga:@BZ2_crc32Table>[TF=34], 0; GPR64common:%vreg67,%vreg66
10768B		%vreg100<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg100
10784B		%vreg99<def> = LDRBBui %vreg100, 12; mem:LD1[%state_out_ch353] GPR32:%vreg99 GPR64common:%vreg100
10800B		%vreg97<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg97
10816B		%vreg96<def> = LDRXui %vreg97, 0; mem:LD8[%strm354] GPR64common:%vreg96,%vreg97
10832B		%vreg94<def> = LDRXui %vreg96, 3; mem:LD8[%next_out355] GPR64common:%vreg94,%vreg96
10848B		STRBBui %vreg99, %vreg94, 0; mem:ST1[%261] GPR32:%vreg99 GPR64common:%vreg94
10864B		%vreg90<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg90
10880B		%vreg89<def> = LDRWui %vreg90, 796; mem:LD4[%calculatedBlockCRC356] GPR32:%vreg89 GPR64common:%vreg90
10896B		%vreg87<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg87
10912B		%vreg86<def> = LDRWui %vreg87, 796; mem:LD4[%calculatedBlockCRC358] GPR32:%vreg86 GPR64common:%vreg87
10928B		%vreg84<def> = UBFMWri %vreg86, 24, 31; GPR32:%vreg84,%vreg86
10944B		%vreg82<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg82
10960B		%vreg81<def> = LDRBBui %vreg82, 12; mem:LD1[%state_out_ch360] GPR32:%vreg81 GPR64common:%vreg82
10976B		%vreg73:sub_32<def,read-undef> = EORWrr %vreg84, %vreg81; GPR64:%vreg73 GPR32:%vreg84,%vreg81
11008B		%vreg74<def> = UBFMXri %vreg73, 0, 31; GPR64:%vreg74,%vreg73
11024B		%vreg69<def> = MOVi64imm 4; GPR64:%vreg69
11040B		%vreg70<def> = MADDXrrr %vreg74, %vreg69, %XZR; GPR64:%vreg70,%vreg74,%vreg69
11056B		%vreg71<def> = ADDXrr %vreg67, %vreg70; GPR64common:%vreg71,%vreg67 GPR64:%vreg70
11072B		%vreg65<def> = LDRWui %vreg71, 0; mem:LD4[%arrayidx364] GPR32:%vreg65 GPR64common:%vreg71
11088B		%vreg63<def> = EORWrs %vreg65, %vreg89, 8; GPR32:%vreg63,%vreg65,%vreg89
11104B		%vreg60<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg60
11120B		STRWui %vreg63, %vreg60, 796; mem:ST4[%calculatedBlockCRC366] GPR32:%vreg63 GPR64common:%vreg60
11136B		%vreg57<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg57
11152B		%vreg56<def> = LDRWui %vreg57, 4; mem:LD4[%state_out_len367] GPR32common:%vreg56 GPR64common:%vreg57
11168B		%vreg55<def> = SUBWri %vreg56, 1, 0; GPR32common:%vreg55,%vreg56
11184B		STRWui %vreg55, %vreg57, 4; mem:ST4[%state_out_len367] GPR32common:%vreg55 GPR64common:%vreg57
11200B		%vreg51<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg51
11216B		%vreg50<def> = LDRXui %vreg51, 0; mem:LD8[%strm369] GPR64common:%vreg50,%vreg51
11232B		%vreg48<def> = LDRXui %vreg50, 3; mem:LD8[%next_out370] GPR64common:%vreg48,%vreg50
11248B		%vreg47<def> = ADDXri %vreg48, 1, 0; GPR64common:%vreg47,%vreg48
11264B		STRXui %vreg47, %vreg50, 3; mem:ST8[%next_out370] GPR64common:%vreg47,%vreg50
11280B		%vreg43<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg43
11296B		%vreg42<def> = LDRXui %vreg43, 0; mem:LD8[%strm372] GPR64common:%vreg42,%vreg43
11312B		%vreg40<def> = LDRWui %vreg42, 8; mem:LD4[%avail_out373] GPR32common:%vreg40 GPR64common:%vreg42
11328B		%vreg39<def> = SUBWri %vreg40, 1, 0; GPR32common:%vreg39,%vreg40
11344B		STRWui %vreg39, %vreg42, 8; mem:ST4[%avail_out373] GPR32common:%vreg39 GPR64common:%vreg42
11360B		%vreg35<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg35
11376B		%vreg34<def> = LDRXui %vreg35, 0; mem:LD8[%strm375] GPR64common:%vreg34,%vreg35
11392B		%vreg32<def> = LDRWui %vreg34, 9; mem:LD4[%total_out_lo32376] GPR32common:%vreg32 GPR64common:%vreg34
11408B		%vreg31<def> = ADDWri %vreg32, 1, 0; GPR32common:%vreg31,%vreg32
11424B		STRWui %vreg31, %vreg34, 9; mem:ST4[%total_out_lo32376] GPR32common:%vreg31 GPR64common:%vreg34
11440B		%vreg27<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg27
11456B		%vreg26<def> = LDRXui %vreg27, 0; mem:LD8[%strm378] GPR64common:%vreg26,%vreg27
11472B		%vreg24<def> = LDRWui %vreg26, 9; mem:LD4[%total_out_lo32379] GPR32:%vreg24 GPR64common:%vreg26
11488B		CBNZW %vreg24, <BB#55>; GPR32:%vreg24
	    Successors according to CFG: BB#55 BB#54

11504B	BB#54: derived from LLVM BB %if.then.382
	    Predecessors according to CFG: BB#53
11520B		%vreg108<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg108
11536B		%vreg107<def> = LDRXui %vreg108, 0; mem:LD8[%strm383] GPR64common:%vreg107,%vreg108
11552B		%vreg105<def> = LDRWui %vreg107, 10; mem:LD4[%total_out_hi32384] GPR32common:%vreg105 GPR64common:%vreg107
11568B		%vreg104<def> = ADDWri %vreg105, 1, 0; GPR32common:%vreg104,%vreg105
11584B		STRWui %vreg104, %vreg107, 10; mem:ST4[%total_out_hi32384] GPR32common:%vreg104 GPR64common:%vreg107
	    Successors according to CFG: BB#55

11600B	BB#55: derived from LLVM BB %if.end.386
	    Predecessors according to CFG: BB#53 BB#54
11616B		B <BB#49>
	    Successors according to CFG: BB#49

11632B	BB#56: derived from LLVM BB %while.end.387
	    Predecessors according to CFG: BB#52
11648B		%vreg120<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg120
11664B		%vreg119<def> = LDRWui %vreg120, 273; mem:LD4[%nblock_used388] GPR32:%vreg119 GPR64common:%vreg120
11680B		%vreg117<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg117
11696B		%vreg114<def> = MOVi64imm 64080; GPR64:%vreg114
11712B		%vreg115<def> = ADDXrr %vreg117, %vreg114; GPR64common:%vreg115 GPR64:%vreg117,%vreg114
11728B		%vreg116<def> = LDRWui %vreg115, 0; mem:LD4[%save_nblock389] GPR32common:%vreg116 GPR64common:%vreg115
11744B		%vreg112<def> = ADDWri %vreg116, 1, 0; GPR32common:%vreg112,%vreg116
11760B		%WZR<def> = SUBSWrr %vreg119, %vreg112, %NZCV<imp-def>; GPR32:%vreg119 GPR32common:%vreg112
11776B		Bcc 1, <BB#58>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#58 BB#57

11792B	BB#57: derived from LLVM BB %if.then.393
	    Predecessors according to CFG: BB#56
11808B		STRBBui %WZR, <fi#0>, 0; mem:ST1[FixedStack0]
11824B		B <BB#73>
	    Successors according to CFG: BB#73

11840B	BB#58: derived from LLVM BB %if.end.394
	    Predecessors according to CFG: BB#56
11856B		%vreg132<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg132
11872B		%vreg131<def> = LDRWui %vreg132, 273; mem:LD4[%nblock_used395] GPR32:%vreg131 GPR64common:%vreg132
11888B		%vreg129<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg129
11904B		%vreg126<def> = MOVi64imm 64080; GPR64:%vreg126
11920B		%vreg127<def> = ADDXrr %vreg129, %vreg126; GPR64common:%vreg127 GPR64:%vreg129,%vreg126
11936B		%vreg128<def> = LDRWui %vreg127, 0; mem:LD4[%save_nblock396] GPR32common:%vreg128 GPR64common:%vreg127
11952B		%vreg124<def> = ADDWri %vreg128, 1, 0; GPR32common:%vreg124,%vreg128
11968B		%WZR<def> = SUBSWrr %vreg131, %vreg124, %NZCV<imp-def>; GPR32:%vreg131 GPR32common:%vreg124
11984B		Bcc 13, <BB#60>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#60 BB#59

12000B	BB#59: derived from LLVM BB %if.then.400
	    Predecessors according to CFG: BB#58
12016B		%vreg601<def> = MOVi32imm 1; GPR32:%vreg601
12032B		STRBBui %vreg601, <fi#0>, 0; mem:ST1[FixedStack0] GPR32:%vreg601
12048B		B <BB#73>
	    Successors according to CFG: BB#73

12064B	BB#60: derived from LLVM BB %if.end.401
	    Predecessors according to CFG: BB#58
12080B		%vreg226<def> = MOVi32imm 1; GPR32:%vreg226
12096B		%vreg228<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg228
12112B		STRWui %vreg226, %vreg228, 4; mem:ST4[%state_out_len402] GPR32:%vreg226 GPR64common:%vreg228
12128B		%vreg225<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg225
12144B		%vreg222<def> = LDRWui %vreg225, 16; mem:LD4[%k0403] GPR32:%vreg222 GPR64common:%vreg225
12176B		%vreg220<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg220
12192B		STRBBui %vreg222, %vreg220, 12; mem:ST1[%state_out_ch405] GPR32:%vreg222 GPR64common:%vreg220
12208B		%vreg217<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg217
12224B		%vreg216<def> = LDRWui %vreg217, 15; mem:LD4[%tPos406] GPR32:%vreg216 GPR64common:%vreg217
12240B		%vreg214<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg214
12256B		%vreg213<def> = ADDXri %vreg214, 1096, 0; GPR64sp:%vreg213 GPR64common:%vreg214
12272B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
12288B		%W0<def> = COPY %vreg216; GPR32:%vreg216
12304B		%X1<def> = COPY %vreg213; GPR64sp:%vreg213
12320B		BL <ga:@BZ2_indexIntoF>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use,kill>, %W0<imp-def>
12336B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
12352B		%vreg207<def> = COPY %W0; GPR32:%vreg207
12368B		%vreg162<def> = MOVi32imm 4; GPR32:%vreg162
12384B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
12400B		STACKMAP 6, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
12416B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
12448B		STRBBui %vreg207, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg207
12464B		%vreg204<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg204
12480B		%vreg203:sub_32<def,read-undef> = LDRWui %vreg204, 15; mem:LD4[%tPos411] GPR64:%vreg203 GPR64common:%vreg204
12512B		%vreg197<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg197
12528B		%vreg196<def> = LDRXui %vreg197, 395; mem:LD8[%ll16413] GPR64:%vreg196 GPR64common:%vreg197
12544B		%vreg192<def> = MOVi64imm 2; GPR64:%vreg192
12560B		%vreg193<def> = MADDXrrr %vreg203, %vreg192, %XZR; GPR64:%vreg193,%vreg203,%vreg192
12576B		%vreg194<def> = ADDXrr %vreg196, %vreg193; GPR64common:%vreg194 GPR64:%vreg196,%vreg193
12592B		%vreg189<def> = LDRHHui %vreg194, 0; mem:LD2[%arrayidx414] GPR32:%vreg189 GPR64common:%vreg194
12608B		%vreg185<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg185
12624B		%vreg184<def> = LDRWui %vreg185, 15; mem:LD4[%tPos416] GPR32:%vreg184 GPR64common:%vreg185
12640B		%vreg179:sub_32<def,read-undef> = UBFMWri %vreg184, 1, 31; GPR64:%vreg179 GPR32:%vreg184
12672B		%vreg180<def> = UBFMXri %vreg179, 0, 31; GPR64:%vreg180,%vreg179
12688B		%vreg177<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg177
12704B		%vreg176<def> = LDRXui %vreg177, 396; mem:LD8[%ll4419] GPR64:%vreg176 GPR64common:%vreg177
12720B		%vreg174<def> = ADDXrr %vreg176, %vreg180; GPR64common:%vreg174 GPR64:%vreg176,%vreg180
12736B		%vreg171<def> = LDRBBui %vreg174, 0; mem:LD1[%arrayidx420] GPR32:%vreg171 GPR64common:%vreg174
12752B		%vreg167<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg167
12768B		%vreg166<def> = LDRWui %vreg167, 15; mem:LD4[%tPos422] GPR32:%vreg166 GPR64common:%vreg167
12784B		%vreg164<def> = ANDWrs %vreg162, %vreg166, 2; GPR32:%vreg164,%vreg162,%vreg166
12800B		%vreg161<def> = LSRVWr %vreg171, %vreg164; GPR32:%vreg161,%vreg171,%vreg164
12816B		%vreg158<def> = ANDWri %vreg161, 3; GPR32common:%vreg158 GPR32:%vreg161
12832B		%vreg156<def> = ORRWrs %vreg189, %vreg158, 16; GPR32:%vreg156,%vreg189 GPR32common:%vreg158
12848B		%vreg153<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg153
12864B		STRWui %vreg156, %vreg153, 15; mem:ST4[%tPos429] GPR32:%vreg156 GPR64common:%vreg153
12880B		%vreg150<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg150
12896B		%vreg149<def> = LDRWui %vreg150, 273; mem:LD4[%nblock_used430] GPR32common:%vreg149 GPR64common:%vreg150
12912B		%vreg148<def> = ADDWri %vreg149, 1, 0; GPR32common:%vreg148,%vreg149
12928B		STRWui %vreg148, %vreg150, 273; mem:ST4[%nblock_used430] GPR32common:%vreg148 GPR64common:%vreg150
12944B		%vreg144<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg144
12960B		%vreg143<def> = LDRWui %vreg144, 273; mem:LD4[%nblock_used432] GPR32:%vreg143 GPR64common:%vreg144
12976B		%vreg141<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg141
12992B		%vreg138<def> = MOVi64imm 64080; GPR64:%vreg138
13008B		%vreg139<def> = ADDXrr %vreg141, %vreg138; GPR64common:%vreg139 GPR64:%vreg141,%vreg138
13024B		%vreg140<def> = LDRWui %vreg139, 0; mem:LD4[%save_nblock433] GPR32common:%vreg140 GPR64common:%vreg139
13040B		%vreg136<def> = ADDWri %vreg140, 1, 0; GPR32common:%vreg136,%vreg140
13056B		%WZR<def> = SUBSWrr %vreg143, %vreg136, %NZCV<imp-def>; GPR32:%vreg143 GPR32common:%vreg136
13072B		Bcc 1, <BB#62>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#62 BB#61

13088B	BB#61: derived from LLVM BB %if.then.437
	    Predecessors according to CFG: BB#60
13104B		B <BB#48>
	    Successors according to CFG: BB#48

13120B	BB#62: derived from LLVM BB %if.end.438
	    Predecessors according to CFG: BB#60
13136B		%vreg236<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg236
13152B		%vreg233<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg233
13168B		%vreg232<def> = LDRWui %vreg233, 16; mem:LD4[%k0440] GPR32:%vreg232 GPR64common:%vreg233
13184B		%WZR<def> = SUBSWrr %vreg236, %vreg232, %NZCV<imp-def>; GPR32:%vreg236,%vreg232
13200B		Bcc 0, <BB#64>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#64 BB#63

13216B	BB#63: derived from LLVM BB %if.then.443
	    Predecessors according to CFG: BB#62
13232B		%vreg600<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg600
13248B		%vreg597<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg597
13264B		STRWui %vreg600, %vreg597, 16; mem:ST4[%k0445] GPR32:%vreg600 GPR64common:%vreg597
13280B		B <BB#48>
	    Successors according to CFG: BB#48

13296B	BB#64: derived from LLVM BB %if.end.446
	    Predecessors according to CFG: BB#62
13312B		%vreg322<def> = MOVi32imm 2; GPR32:%vreg322
13328B		%vreg324<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg324
13344B		STRWui %vreg322, %vreg324, 4; mem:ST4[%state_out_len447] GPR32:%vreg322 GPR64common:%vreg324
13360B		%vreg321<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg321
13376B		%vreg320<def> = LDRWui %vreg321, 15; mem:LD4[%tPos448] GPR32:%vreg320 GPR64common:%vreg321
13392B		%vreg318<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg318
13408B		%vreg317<def> = ADDXri %vreg318, 1096, 0; GPR64sp:%vreg317 GPR64common:%vreg318
13424B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
13440B		%W0<def> = COPY %vreg320; GPR32:%vreg320
13456B		%X1<def> = COPY %vreg317; GPR64sp:%vreg317
13472B		BL <ga:@BZ2_indexIntoF>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use,kill>, %W0<imp-def>
13488B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
13504B		%vreg311<def> = COPY %W0; GPR32:%vreg311
13520B		%vreg266<def> = MOVi32imm 4; GPR32:%vreg266
13536B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
13552B		STACKMAP 7, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
13568B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
13600B		STRBBui %vreg311, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg311
13616B		%vreg308<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg308
13632B		%vreg307:sub_32<def,read-undef> = LDRWui %vreg308, 15; mem:LD4[%tPos453] GPR64:%vreg307 GPR64common:%vreg308
13664B		%vreg301<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg301
13680B		%vreg300<def> = LDRXui %vreg301, 395; mem:LD8[%ll16455] GPR64:%vreg300 GPR64common:%vreg301
13696B		%vreg296<def> = MOVi64imm 2; GPR64:%vreg296
13712B		%vreg297<def> = MADDXrrr %vreg307, %vreg296, %XZR; GPR64:%vreg297,%vreg307,%vreg296
13728B		%vreg298<def> = ADDXrr %vreg300, %vreg297; GPR64common:%vreg298 GPR64:%vreg300,%vreg297
13744B		%vreg293<def> = LDRHHui %vreg298, 0; mem:LD2[%arrayidx456] GPR32:%vreg293 GPR64common:%vreg298
13760B		%vreg289<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg289
13776B		%vreg288<def> = LDRWui %vreg289, 15; mem:LD4[%tPos458] GPR32:%vreg288 GPR64common:%vreg289
13792B		%vreg283:sub_32<def,read-undef> = UBFMWri %vreg288, 1, 31; GPR64:%vreg283 GPR32:%vreg288
13824B		%vreg284<def> = UBFMXri %vreg283, 0, 31; GPR64:%vreg284,%vreg283
13840B		%vreg281<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg281
13856B		%vreg280<def> = LDRXui %vreg281, 396; mem:LD8[%ll4461] GPR64:%vreg280 GPR64common:%vreg281
13872B		%vreg278<def> = ADDXrr %vreg280, %vreg284; GPR64common:%vreg278 GPR64:%vreg280,%vreg284
13888B		%vreg275<def> = LDRBBui %vreg278, 0; mem:LD1[%arrayidx462] GPR32:%vreg275 GPR64common:%vreg278
13904B		%vreg271<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg271
13920B		%vreg270<def> = LDRWui %vreg271, 15; mem:LD4[%tPos464] GPR32:%vreg270 GPR64common:%vreg271
13936B		%vreg268<def> = ANDWrs %vreg266, %vreg270, 2; GPR32:%vreg268,%vreg266,%vreg270
13952B		%vreg265<def> = LSRVWr %vreg275, %vreg268; GPR32:%vreg265,%vreg275,%vreg268
13968B		%vreg262<def> = ANDWri %vreg265, 3; GPR32common:%vreg262 GPR32:%vreg265
13984B		%vreg260<def> = ORRWrs %vreg293, %vreg262, 16; GPR32:%vreg260,%vreg293 GPR32common:%vreg262
14000B		%vreg257<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg257
14016B		STRWui %vreg260, %vreg257, 15; mem:ST4[%tPos471] GPR32:%vreg260 GPR64common:%vreg257
14032B		%vreg254<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg254
14048B		%vreg253<def> = LDRWui %vreg254, 273; mem:LD4[%nblock_used472] GPR32common:%vreg253 GPR64common:%vreg254
14064B		%vreg252<def> = ADDWri %vreg253, 1, 0; GPR32common:%vreg252,%vreg253
14080B		STRWui %vreg252, %vreg254, 273; mem:ST4[%nblock_used472] GPR32common:%vreg252 GPR64common:%vreg254
14096B		%vreg248<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg248
14112B		%vreg247<def> = LDRWui %vreg248, 273; mem:LD4[%nblock_used474] GPR32:%vreg247 GPR64common:%vreg248
14128B		%vreg245<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg245
14144B		%vreg242<def> = MOVi64imm 64080; GPR64:%vreg242
14160B		%vreg243<def> = ADDXrr %vreg245, %vreg242; GPR64common:%vreg243 GPR64:%vreg245,%vreg242
14176B		%vreg244<def> = LDRWui %vreg243, 0; mem:LD4[%save_nblock475] GPR32common:%vreg244 GPR64common:%vreg243
14192B		%vreg240<def> = ADDWri %vreg244, 1, 0; GPR32common:%vreg240,%vreg244
14208B		%WZR<def> = SUBSWrr %vreg247, %vreg240, %NZCV<imp-def>; GPR32:%vreg247 GPR32common:%vreg240
14224B		Bcc 1, <BB#66>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#66 BB#65

14240B	BB#65: derived from LLVM BB %if.then.479
	    Predecessors according to CFG: BB#64
14256B		B <BB#48>
	    Successors according to CFG: BB#48

14272B	BB#66: derived from LLVM BB %if.end.480
	    Predecessors according to CFG: BB#64
14288B		%vreg332<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg332
14304B		%vreg329<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg329
14320B		%vreg328<def> = LDRWui %vreg329, 16; mem:LD4[%k0482] GPR32:%vreg328 GPR64common:%vreg329
14336B		%WZR<def> = SUBSWrr %vreg332, %vreg328, %NZCV<imp-def>; GPR32:%vreg332,%vreg328
14352B		Bcc 0, <BB#68>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#68 BB#67

14368B	BB#67: derived from LLVM BB %if.then.485
	    Predecessors according to CFG: BB#66
14384B		%vreg594<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg594
14400B		%vreg591<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg591
14416B		STRWui %vreg594, %vreg591, 16; mem:ST4[%k0487] GPR32:%vreg594 GPR64common:%vreg591
14432B		B <BB#48>
	    Successors according to CFG: BB#48

14448B	BB#68: derived from LLVM BB %if.end.488
	    Predecessors according to CFG: BB#66
14464B		%vreg418<def> = MOVi32imm 3; GPR32:%vreg418
14480B		%vreg420<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg420
14496B		STRWui %vreg418, %vreg420, 4; mem:ST4[%state_out_len489] GPR32:%vreg418 GPR64common:%vreg420
14512B		%vreg417<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg417
14528B		%vreg416<def> = LDRWui %vreg417, 15; mem:LD4[%tPos490] GPR32:%vreg416 GPR64common:%vreg417
14544B		%vreg414<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg414
14560B		%vreg413<def> = ADDXri %vreg414, 1096, 0; GPR64sp:%vreg413 GPR64common:%vreg414
14576B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
14592B		%W0<def> = COPY %vreg416; GPR32:%vreg416
14608B		%X1<def> = COPY %vreg413; GPR64sp:%vreg413
14624B		BL <ga:@BZ2_indexIntoF>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use,kill>, %W0<imp-def>
14640B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
14656B		%vreg407<def> = COPY %W0; GPR32:%vreg407
14672B		%vreg362<def> = MOVi32imm 4; GPR32:%vreg362
14688B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
14704B		STACKMAP 8, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
14720B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
14752B		STRBBui %vreg407, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg407
14768B		%vreg404<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg404
14784B		%vreg403:sub_32<def,read-undef> = LDRWui %vreg404, 15; mem:LD4[%tPos495] GPR64:%vreg403 GPR64common:%vreg404
14816B		%vreg397<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg397
14832B		%vreg396<def> = LDRXui %vreg397, 395; mem:LD8[%ll16497] GPR64:%vreg396 GPR64common:%vreg397
14848B		%vreg392<def> = MOVi64imm 2; GPR64:%vreg392
14864B		%vreg393<def> = MADDXrrr %vreg403, %vreg392, %XZR; GPR64:%vreg393,%vreg403,%vreg392
14880B		%vreg394<def> = ADDXrr %vreg396, %vreg393; GPR64common:%vreg394 GPR64:%vreg396,%vreg393
14896B		%vreg389<def> = LDRHHui %vreg394, 0; mem:LD2[%arrayidx498] GPR32:%vreg389 GPR64common:%vreg394
14912B		%vreg385<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg385
14928B		%vreg384<def> = LDRWui %vreg385, 15; mem:LD4[%tPos500] GPR32:%vreg384 GPR64common:%vreg385
14944B		%vreg379:sub_32<def,read-undef> = UBFMWri %vreg384, 1, 31; GPR64:%vreg379 GPR32:%vreg384
14976B		%vreg380<def> = UBFMXri %vreg379, 0, 31; GPR64:%vreg380,%vreg379
14992B		%vreg377<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg377
15008B		%vreg376<def> = LDRXui %vreg377, 396; mem:LD8[%ll4503] GPR64:%vreg376 GPR64common:%vreg377
15024B		%vreg374<def> = ADDXrr %vreg376, %vreg380; GPR64common:%vreg374 GPR64:%vreg376,%vreg380
15040B		%vreg371<def> = LDRBBui %vreg374, 0; mem:LD1[%arrayidx504] GPR32:%vreg371 GPR64common:%vreg374
15056B		%vreg367<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg367
15072B		%vreg366<def> = LDRWui %vreg367, 15; mem:LD4[%tPos506] GPR32:%vreg366 GPR64common:%vreg367
15088B		%vreg364<def> = ANDWrs %vreg362, %vreg366, 2; GPR32:%vreg364,%vreg362,%vreg366
15104B		%vreg361<def> = LSRVWr %vreg371, %vreg364; GPR32:%vreg361,%vreg371,%vreg364
15120B		%vreg358<def> = ANDWri %vreg361, 3; GPR32common:%vreg358 GPR32:%vreg361
15136B		%vreg356<def> = ORRWrs %vreg389, %vreg358, 16; GPR32:%vreg356,%vreg389 GPR32common:%vreg358
15152B		%vreg353<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg353
15168B		STRWui %vreg356, %vreg353, 15; mem:ST4[%tPos513] GPR32:%vreg356 GPR64common:%vreg353
15184B		%vreg350<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg350
15200B		%vreg349<def> = LDRWui %vreg350, 273; mem:LD4[%nblock_used514] GPR32common:%vreg349 GPR64common:%vreg350
15216B		%vreg348<def> = ADDWri %vreg349, 1, 0; GPR32common:%vreg348,%vreg349
15232B		STRWui %vreg348, %vreg350, 273; mem:ST4[%nblock_used514] GPR32common:%vreg348 GPR64common:%vreg350
15248B		%vreg344<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg344
15264B		%vreg343<def> = LDRWui %vreg344, 273; mem:LD4[%nblock_used516] GPR32:%vreg343 GPR64common:%vreg344
15280B		%vreg341<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg341
15296B		%vreg338<def> = MOVi64imm 64080; GPR64:%vreg338
15312B		%vreg339<def> = ADDXrr %vreg341, %vreg338; GPR64common:%vreg339 GPR64:%vreg341,%vreg338
15328B		%vreg340<def> = LDRWui %vreg339, 0; mem:LD4[%save_nblock517] GPR32common:%vreg340 GPR64common:%vreg339
15344B		%vreg336<def> = ADDWri %vreg340, 1, 0; GPR32common:%vreg336,%vreg340
15360B		%WZR<def> = SUBSWrr %vreg343, %vreg336, %NZCV<imp-def>; GPR32:%vreg343 GPR32common:%vreg336
15376B		Bcc 1, <BB#70>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#70 BB#69

15392B	BB#69: derived from LLVM BB %if.then.521
	    Predecessors according to CFG: BB#68
15408B		B <BB#48>
	    Successors according to CFG: BB#48

15424B	BB#70: derived from LLVM BB %if.end.522
	    Predecessors according to CFG: BB#68
15440B		%vreg428<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg428
15456B		%vreg425<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg425
15472B		%vreg424<def> = LDRWui %vreg425, 16; mem:LD4[%k0524] GPR32:%vreg424 GPR64common:%vreg425
15488B		%WZR<def> = SUBSWrr %vreg428, %vreg424, %NZCV<imp-def>; GPR32:%vreg428,%vreg424
15504B		Bcc 0, <BB#72>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#72 BB#71

15520B	BB#71: derived from LLVM BB %if.then.527
	    Predecessors according to CFG: BB#70
15536B		%vreg588<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg588
15552B		%vreg585<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg585
15568B		STRWui %vreg588, %vreg585, 16; mem:ST4[%k0529] GPR32:%vreg588 GPR64common:%vreg585
15584B		B <BB#48>
	    Successors according to CFG: BB#48

15600B	BB#72: derived from LLVM BB %if.end.530
	    Predecessors according to CFG: BB#70
15616B		%vreg582<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg582
15632B		%vreg581<def> = LDRWui %vreg582, 15; mem:LD4[%tPos531] GPR32:%vreg581 GPR64common:%vreg582
15648B		%vreg579<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg579
15664B		%vreg578<def> = ADDXri %vreg579, 1096, 0; GPR64sp:%vreg578 GPR64common:%vreg579
15680B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
15696B		%W0<def> = COPY %vreg581; GPR32:%vreg581
15712B		%X1<def> = COPY %vreg578; GPR64sp:%vreg578
15728B		BL <ga:@BZ2_indexIntoF>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use,kill>, %W0<imp-def>
15744B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
15760B		%vreg572<def> = COPY %W0; GPR32:%vreg572
15776B		%vreg527<def> = MOVi32imm 4; GPR32:%vreg527
15792B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
15808B		STACKMAP 9, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
15824B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
15856B		STRBBui %vreg572, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg572
15872B		%vreg569<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg569
15888B		%vreg568:sub_32<def,read-undef> = LDRWui %vreg569, 15; mem:LD4[%tPos536] GPR64:%vreg568 GPR64common:%vreg569
15920B		%vreg562<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg562
15936B		%vreg561<def> = LDRXui %vreg562, 395; mem:LD8[%ll16538] GPR64:%vreg561 GPR64common:%vreg562
15952B		%vreg557<def> = MOVi64imm 2; GPR64:%vreg557
15968B		%vreg558<def> = MADDXrrr %vreg568, %vreg557, %XZR; GPR64:%vreg558,%vreg568,%vreg557
15984B		%vreg559<def> = ADDXrr %vreg561, %vreg558; GPR64common:%vreg559 GPR64:%vreg561,%vreg558
16000B		%vreg554<def> = LDRHHui %vreg559, 0; mem:LD2[%arrayidx539] GPR32:%vreg554 GPR64common:%vreg559
16016B		%vreg550<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg550
16032B		%vreg549<def> = LDRWui %vreg550, 15; mem:LD4[%tPos541] GPR32:%vreg549 GPR64common:%vreg550
16048B		%vreg544:sub_32<def,read-undef> = UBFMWri %vreg549, 1, 31; GPR64:%vreg544 GPR32:%vreg549
16080B		%vreg545<def> = UBFMXri %vreg544, 0, 31; GPR64:%vreg545,%vreg544
16096B		%vreg542<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg542
16112B		%vreg541<def> = LDRXui %vreg542, 396; mem:LD8[%ll4544] GPR64:%vreg541 GPR64common:%vreg542
16128B		%vreg539<def> = ADDXrr %vreg541, %vreg545; GPR64common:%vreg539 GPR64:%vreg541,%vreg545
16144B		%vreg536<def> = LDRBBui %vreg539, 0; mem:LD1[%arrayidx545] GPR32:%vreg536 GPR64common:%vreg539
16160B		%vreg532<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg532
16176B		%vreg531<def> = LDRWui %vreg532, 15; mem:LD4[%tPos547] GPR32:%vreg531 GPR64common:%vreg532
16192B		%vreg529<def> = ANDWrs %vreg527, %vreg531, 2; GPR32:%vreg529,%vreg527,%vreg531
16208B		%vreg526<def> = LSRVWr %vreg536, %vreg529; GPR32:%vreg526,%vreg536,%vreg529
16224B		%vreg523<def> = ANDWri %vreg526, 3; GPR32common:%vreg523 GPR32:%vreg526
16240B		%vreg521<def> = ORRWrs %vreg554, %vreg523, 16; GPR32:%vreg521,%vreg554 GPR32common:%vreg523
16256B		%vreg518<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg518
16272B		STRWui %vreg521, %vreg518, 15; mem:ST4[%tPos554] GPR32:%vreg521 GPR64common:%vreg518
16288B		%vreg515<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg515
16304B		%vreg514<def> = LDRWui %vreg515, 273; mem:LD4[%nblock_used555] GPR32common:%vreg514 GPR64common:%vreg515
16320B		%vreg513<def> = ADDWri %vreg514, 1, 0; GPR32common:%vreg513,%vreg514
16336B		STRWui %vreg513, %vreg515, 273; mem:ST4[%nblock_used555] GPR32common:%vreg513 GPR64common:%vreg515
16352B		%vreg509<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32common:%vreg509
16368B		%vreg506<def> = ADDWri %vreg509, 4, 0; GPR32common:%vreg506,%vreg509
16384B		%vreg504<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg504
16400B		STRWui %vreg506, %vreg504, 4; mem:ST4[%state_out_len559] GPR32common:%vreg506 GPR64common:%vreg504
16416B		%vreg501<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg501
16432B		%vreg500<def> = LDRWui %vreg501, 15; mem:LD4[%tPos560] GPR32:%vreg500 GPR64common:%vreg501
16448B		%vreg498<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg498
16464B		%vreg497<def> = ADDXri %vreg498, 1096, 0; GPR64sp:%vreg497 GPR64common:%vreg498
16480B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
16496B		%W0<def> = COPY %vreg500; GPR32:%vreg500
16512B		%X1<def> = COPY %vreg497; GPR64sp:%vreg497
16528B		BL <ga:@BZ2_indexIntoF>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use,kill>, %W0<imp-def>
16544B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
16560B		%vreg494<def> = COPY %W0; GPR32:%vreg494
16576B		%vreg446<def> = MOVi32imm 4; GPR32:%vreg446
16592B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
16608B		STACKMAP 10, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
16624B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
16640B		%vreg491<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg491
16656B		STRWui %vreg494, %vreg491, 16; mem:ST4[%k0564] GPR32:%vreg494 GPR64common:%vreg491
16672B		%vreg488<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg488
16688B		%vreg487:sub_32<def,read-undef> = LDRWui %vreg488, 15; mem:LD4[%tPos565] GPR64:%vreg487 GPR64common:%vreg488
16720B		%vreg481<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg481
16736B		%vreg480<def> = LDRXui %vreg481, 395; mem:LD8[%ll16567] GPR64:%vreg480 GPR64common:%vreg481
16752B		%vreg476<def> = MOVi64imm 2; GPR64:%vreg476
16768B		%vreg477<def> = MADDXrrr %vreg487, %vreg476, %XZR; GPR64:%vreg477,%vreg487,%vreg476
16784B		%vreg478<def> = ADDXrr %vreg480, %vreg477; GPR64common:%vreg478 GPR64:%vreg480,%vreg477
16800B		%vreg473<def> = LDRHHui %vreg478, 0; mem:LD2[%arrayidx568] GPR32:%vreg473 GPR64common:%vreg478
16816B		%vreg469<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg469
16832B		%vreg468<def> = LDRWui %vreg469, 15; mem:LD4[%tPos570] GPR32:%vreg468 GPR64common:%vreg469
16848B		%vreg463:sub_32<def,read-undef> = UBFMWri %vreg468, 1, 31; GPR64:%vreg463 GPR32:%vreg468
16880B		%vreg464<def> = UBFMXri %vreg463, 0, 31; GPR64:%vreg464,%vreg463
16896B		%vreg461<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg461
16912B		%vreg460<def> = LDRXui %vreg461, 396; mem:LD8[%ll4573] GPR64:%vreg460 GPR64common:%vreg461
16928B		%vreg458<def> = ADDXrr %vreg460, %vreg464; GPR64common:%vreg458 GPR64:%vreg460,%vreg464
16944B		%vreg455<def> = LDRBBui %vreg458, 0; mem:LD1[%arrayidx574] GPR32:%vreg455 GPR64common:%vreg458
16960B		%vreg451<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg451
16976B		%vreg450<def> = LDRWui %vreg451, 15; mem:LD4[%tPos576] GPR32:%vreg450 GPR64common:%vreg451
16992B		%vreg448<def> = ANDWrs %vreg446, %vreg450, 2; GPR32:%vreg448,%vreg446,%vreg450
17008B		%vreg445<def> = LSRVWr %vreg455, %vreg448; GPR32:%vreg445,%vreg455,%vreg448
17024B		%vreg442<def> = ANDWri %vreg445, 3; GPR32common:%vreg442 GPR32:%vreg445
17040B		%vreg440<def> = ORRWrs %vreg473, %vreg442, 16; GPR32:%vreg440,%vreg473 GPR32common:%vreg442
17056B		%vreg437<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg437
17072B		STRWui %vreg440, %vreg437, 15; mem:ST4[%tPos583] GPR32:%vreg440 GPR64common:%vreg437
17088B		%vreg434<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg434
17104B		%vreg433<def> = LDRWui %vreg434, 273; mem:LD4[%nblock_used584] GPR32common:%vreg433 GPR64common:%vreg434
17120B		%vreg432<def> = ADDWri %vreg433, 1, 0; GPR32common:%vreg432,%vreg433
17136B		STRWui %vreg432, %vreg434, 273; mem:ST4[%nblock_used584] GPR32common:%vreg432 GPR64common:%vreg434
17152B		B <BB#48>
	    Successors according to CFG: BB#48

17168B	BB#73: derived from LLVM BB %return
	    Predecessors according to CFG: BB#59 BB#57 BB#50 BB#13 BB#11 BB#4
17184B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
17200B		%vreg1466<def> = MOVaddr <ga:@unRLE_obuf_to_output_SMALL>[TF=1], <ga:@unRLE_obuf_to_output_SMALL>[TF=34]; GPR64:%vreg1466
17216B		%X0<def> = COPY %vreg1466; GPR64:%vreg1466
17232B		%X1<def> = COPY %vreg10; GPR64:%vreg10
17248B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %SP<imp-def>
17264B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
17280B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
17296B		STACKMAP 11, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=1)
17312B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
17328B		%vreg1467<def> = LDRBBui <fi#0>, 0; mem:LD1[%retval] GPR32:%vreg1467
17360B		%W0<def> = COPY %vreg1467; GPR32:%vreg1467
17376B		RET_ReallyLR %W0<imp-use>

# End machine code for function unRLE_obuf_to_output_SMALL.

AllocationOrder(GPR32sponly) = [ ]
handleMove 992B -> 1016B: %vreg653<def> = EORWrs %vreg655, %vreg679, 8; GPR32:%vreg653,%vreg655,%vreg679
     %vreg653:	[992r,1024r:0)  0@992r
        -->	[1016r,1024r:0)  0@1016r
     %vreg655:	[976r,992r:0)  0@976r
        -->	[976r,1016r:0)  0@976r
     %vreg679:	[784r,992r:0)  0@784r
        -->	[784r,1016r:0)  0@784r
handleMove 832B -> 872B: %vreg674<def> = UBFMWri %vreg676, 24, 31; GPR32:%vreg674,%vreg676
     %vreg674:	[832r,880r:0)  0@832r
        -->	[872r,880r:0)  0@872r
     %vreg676:	[816r,832r:0)  0@816r
        -->	[816r,872r:0)  0@816r
handleMove 784B -> 868B: %vreg679<def> = LDRWui %vreg680, 796; mem:LD4[%calculatedBlockCRC] GPR32:%vreg679 GPR64common:%vreg680
     %vreg679:	[784r,1016r:0)  0@784r
        -->	[868r,1016r:0)  0@868r
     %vreg680:	[768r,784r:0)  0@768r
        -->	[768r,868r:0)  0@768r
handleMove 656B -> 872B: %vreg657<def> = ADDXri %vreg656, <ga:@BZ2_crc32Table>[TF=34], 0; GPR64common:%vreg657,%vreg656
     %vreg657:	[656r,960r:0)  0@656r
        -->	[872r,960r:0)  0@872r
     %vreg656:	[640r,656r:0)  0@640r
        -->	[640r,872r:0)  0@640r
handleMove 816B -> 856B: %vreg676<def> = LDRWui %vreg677, 796; mem:LD4[%calculatedBlockCRC8] GPR32:%vreg676 GPR64common:%vreg677
     %vreg676:	[816r,888r:0)  0@816r
        -->	[856r,888r:0)  0@856r
     %vreg677:	[800r,816r:0)  0@800r
        -->	[800r,856r:0)  0@800r
handleMove 768B -> 852B: %vreg680<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg680
     %vreg680:	[768r,880r:0)  0@768r
        -->	[852r,880r:0)  0@852r
handleMove 640B -> 856B: %vreg656<def> = ADRP <ga:@BZ2_crc32Table>[TF=1]; GPR64common:%vreg656
     %vreg656:	[640r,888r:0)  0@640r
        -->	[856r,888r:0)  0@856r
handleMove 688B -> 728B: %vreg689<def> = LDRBBui %vreg690, 12; mem:LD1[%state_out_ch] GPR32:%vreg689 GPR64common:%vreg690
     %vreg689:	[688r,752r:0)  0@688r
        -->	[728r,752r:0)  0@728r
     %vreg690:	[672r,688r:0)  0@672r
        -->	[672r,728r:0)  0@672r
handleMove 672B -> 712B: %vreg690<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg690
     %vreg690:	[672r,728r:0)  0@672r
        -->	[712r,728r:0)  0@712r
handleMove 1568B -> 1640B: %vreg709<def> = LDRWui %vreg710, 273; mem:LD4[%nblock_used] GPR32:%vreg709 GPR64common:%vreg710
     %vreg709:	[1568r,1664r:0)  0@1568r
        -->	[1640r,1664r:0)  0@1640r
     %vreg710:	[1552r,1568r:0)  0@1552r
        -->	[1552r,1640r:0)  0@1552r
handleMove 1552B -> 1592B: %vreg710<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg710
     %vreg710:	[1552r,1640r:0)  0@1552r
        -->	[1592r,1640r:0)  0@1592r
handleMove 1776B -> 1848B: %vreg721<def> = LDRWui %vreg722, 273; mem:LD4[%nblock_used31] GPR32:%vreg721 GPR64common:%vreg722
     %vreg721:	[1776r,1872r:0)  0@1776r
        -->	[1848r,1872r:0)  0@1848r
     %vreg722:	[1760r,1776r:0)  0@1760r
        -->	[1760r,1848r:0)  0@1760r
handleMove 1760B -> 1800B: %vreg722<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg722
     %vreg722:	[1760r,1848r:0)  0@1760r
        -->	[1800r,1848r:0)  0@1800r
AllocationOrder(GPR32sponly) = [ ]
handleMove 2736B -> 2760B: %vreg732<def> = ORRWrs %vreg765, %vreg734, 16; GPR32:%vreg732,%vreg765 GPR32common:%vreg734
     %vreg732:	[2736r,2768r:0)  0@2736r
        -->	[2760r,2768r:0)  0@2760r
     %vreg765:	[2496r,2736r:0)  0@2496r
        -->	[2496r,2760r:0)  0@2496r
     %vreg734:	[2720r,2736r:0)  0@2720r
        -->	[2720r,2760r:0)  0@2720r
handleMove 2720B -> 2756B: %vreg734<def> = ANDWri %vreg737, 3; GPR32common:%vreg734 GPR32:%vreg737
     %vreg734:	[2720r,2760r:0)  0@2720r
        -->	[2756r,2760r:0)  0@2756r
     %vreg737:	[2704r,2720r:0)  0@2704r
        -->	[2704r,2756r:0)  0@2704r
handleMove 2704B -> 2760B: %vreg737<def> = LSRVWr %vreg747, %vreg740; GPR32:%vreg737,%vreg747,%vreg740
     %vreg737:	[2704r,2768r:0)  0@2704r
        -->	[2760r,2768r:0)  0@2760r
     %vreg747:	[2640r,2704r:0)  0@2640r
        -->	[2640r,2760r:0)  0@2640r
     %vreg740:	[2688r,2704r:0)  0@2688r
        -->	[2688r,2760r:0)  0@2688r
handleMove 2496B -> 2680B: %vreg765<def> = LDRHHui %vreg770, 0; mem:LD2[%arrayidx44] GPR32:%vreg765 GPR64common:%vreg770
     %vreg765:	[2496r,2776r:0)  0@2496r
        -->	[2680r,2776r:0)  0@2680r
     %vreg770:	[2480r,2496r:0)  0@2480r
        -->	[2480r,2680r:0)  0@2480r
handleMove 2640B -> 2676B: %vreg747<def> = LDRBBui %vreg750, 0; mem:LD1[%arrayidx49] GPR32:%vreg747 GPR64common:%vreg750
     %vreg747:	[2640r,2760r:0)  0@2640r
        -->	[2676r,2760r:0)  0@2676r
     %vreg750:	[2624r,2640r:0)  0@2624r
        -->	[2624r,2676r:0)  0@2624r
handleMove 2624B -> 2680B: %vreg750<def> = ADDXrr %vreg752, %vreg756; GPR64common:%vreg750 GPR64:%vreg752,%vreg756
     %vreg750:	[2624r,2688r:0)  0@2624r
        -->	[2680r,2688r:0)  0@2680r
     %vreg752:	[2608r,2624r:0)  0@2608r
        -->	[2608r,2680r:0)  0@2608r
     %vreg756:	[2576r,2624r:0)  0@2576r
        -->	[2576r,2680r:0)  0@2576r
handleMove 2576B -> 2664B: %vreg756<def> = UBFMXri %vreg755, 0, 31; GPR64:%vreg756,%vreg755
     %vreg756:	[2576r,2680r:0)  0@2576r
        -->	[2664r,2680r:0)  0@2664r
     %vreg755:	[2544r,2576r:0)  0@2544r
        -->	[2544r,2664r:0)  0@2544r
handleMove 2544B -> 2660B: %vreg755:sub_32<def,read-undef> = UBFMWri %vreg760, 1, 31; GPR64:%vreg755 GPR32:%vreg760
     %vreg755:	[2544r,2664r:0)  0@2544r
        -->	[2660r,2664r:0)  0@2660r
     %vreg760:	[2528r,2544r:0)  0@2528r
        -->	[2528r,2660r:0)  0@2528r
handleMove 2608B -> 2664B: %vreg752<def> = LDRXui %vreg753, 396; mem:LD8[%ll4] GPR64:%vreg752 GPR64common:%vreg753
     %vreg752:	[2608r,2696r:0)  0@2608r
        -->	[2664r,2696r:0)  0@2664r
     %vreg753:	[2592r,2608r:0)  0@2592r
        -->	[2592r,2664r:0)  0@2592r
handleMove 2480B -> 2600B: %vreg770<def> = ADDXrr %vreg772, %vreg769; GPR64common:%vreg770 GPR64:%vreg772,%vreg769
     %vreg770:	[2480r,2712r:0)  0@2480r
        -->	[2600r,2712r:0)  0@2600r
     %vreg772:	[2432r,2480r:0)  0@2432r
        -->	[2432r,2600r:0)  0@2432r
     %vreg769:	[2464r,2480r:0)  0@2464r
        -->	[2464r,2600r:0)  0@2464r
handleMove 2528B -> 2596B: %vreg760<def> = LDRWui %vreg761, 15; mem:LD4[%tPos46] GPR32:%vreg760 GPR64common:%vreg761
     %vreg760:	[2528r,2672r:0)  0@2528r
        -->	[2596r,2672r:0)  0@2596r
     %vreg761:	[2512r,2528r:0)  0@2512r
        -->	[2512r,2596r:0)  0@2512r
handleMove 2464B -> 2520B: %vreg769<def> = MADDXrrr %vreg779, %vreg768, %XZR; GPR64:%vreg769,%vreg779,%vreg768
     %vreg769:	[2464r,2600r:0)  0@2464r
        -->	[2520r,2600r:0)  0@2520r
     %vreg779:	[2384r,2464r:0)  0@2384r
        -->	[2384r,2520r:0)  0@2384r
     %vreg768:	[2448r,2464r:0)  0@2448r
        -->	[2448r,2520r:0)  0@2448r
     WZR:	[1664r,1664d:17)[1872r,1872d:16)[3104r,3104d:15)[3360r,3360d:13)[3632r,3632d:14)[3760r,3760d:12)[4928r,4928d:11)[5184r,5184d:9)[5456r,5456d:10)[5584r,5584d:8)[6752r,6752d:7)[7008r,7008d:5)[7280r,7280d:6)[7408r,7408d:4)[8528r,8528d:3)[8784r,8784d:2)[10000r,10000d:1)[10256r,10256d:0)[11760r,11760d:25)[11968r,11968d:24)[13056r,13056d:23)[13184r,13184d:22)[14208r,14208d:21)[14336r,14336d:20)[15360r,15360d:19)[15488r,15488d:18)  0@10256r 1@10000r 2@8784r 3@8528r 4@7408r 5@7008r 6@7280r 7@6752r 8@5584r 9@5184r 10@5456r 11@4928r 12@3760r 13@3360r 14@3632r 15@3104r 16@1872r 17@1664r 18@15488r 19@15360r 20@14336r 21@14208r 22@13184r 23@13056r 24@11968r 25@11760r
        -->	[1664r,1664d:17)[1872r,1872d:16)[3104r,3104d:15)[3360r,3360d:13)[3632r,3632d:14)[3760r,3760d:12)[4928r,4928d:11)[5184r,5184d:9)[5456r,5456d:10)[5584r,5584d:8)[6752r,6752d:7)[7008r,7008d:5)[7280r,7280d:6)[7408r,7408d:4)[8528r,8528d:3)[8784r,8784d:2)[10000r,10000d:1)[10256r,10256d:0)[11760r,11760d:25)[11968r,11968d:24)[13056r,13056d:23)[13184r,13184d:22)[14208r,14208d:21)[14336r,14336d:20)[15360r,15360d:19)[15488r,15488d:18)  0@10256r 1@10000r 2@8784r 3@8528r 4@7408r 5@7008r 6@7280r 7@6752r 8@5584r 9@5184r 10@5456r 11@4928r 12@3760r 13@3360r 14@3632r 15@3104r 16@1872r 17@1664r 18@15488r 19@15360r 20@14336r 21@14208r 22@13184r 23@13056r 24@11968r 25@11760r
handleMove 2432B -> 2516B: %vreg772<def> = LDRXui %vreg773, 395; mem:LD8[%ll16] GPR64:%vreg772 GPR64common:%vreg773
     %vreg772:	[2432r,2600r:0)  0@2432r
        -->	[2516r,2600r:0)  0@2516r
     %vreg773:	[2416r,2432r:0)  0@2416r
        -->	[2416r,2516r:0)  0@2416r
handleMove 2384B -> 2424B: %vreg779:sub_32<def,read-undef> = LDRWui %vreg780, 15; mem:LD4[%tPos42] GPR64:%vreg779 GPR64common:%vreg780
     %vreg779:	[2384r,2520r:0)  0@2384r
        -->	[2424r,2520r:0)  0@2424r
     %vreg780:	[2368r,2384r:0)  0@2368r
        -->	[2368r,2424r:0)  0@2368r
handleMove 2128B -> 2152B: %vreg792<def> = LDRWui %vreg793, 15; mem:LD4[%tPos] GPR32:%vreg792 GPR64common:%vreg793
     %vreg792:	[2128r,2192r:0)  0@2128r
        -->	[2152r,2192r:0)  0@2152r
     %vreg793:	[2112r,2128r:0)  0@2112r
        -->	[2112r,2152r:0)  0@2112r
handleMove 1984B -> 2008B: %vreg802<def> = MOVi32imm 1; GPR32:%vreg802
     %vreg802:	[1984r,2016r:0)  0@1984r
        -->	[2008r,2016r:0)  0@2008r
AllocationOrder(GPR32sponly) = [ ]
handleMove 2864B -> 2920B: %vreg821<def> = ADDXri %vreg820, <ga:@BZ2_rNums>[TF=34], 0; GPR64common:%vreg821,%vreg820
     %vreg821:	[2864r,2944r:0)  0@2864r
        -->	[2920r,2944r:0)  0@2920r
     %vreg820:	[2848r,2864r:0)  0@2848r
        -->	[2848r,2920r:0)  0@2848r
handleMove 2848B -> 2904B: %vreg820<def> = ADRP <ga:@BZ2_rNums>[TF=1]; GPR64common:%vreg820
     %vreg820:	[2848r,2920r:0)  0@2848r
        -->	[2904r,2920r:0)  0@2904r
AllocationOrder(GPR32sponly) = [ ]
handleMove 3536B -> 3608B: %vreg844<def> = LDRWui %vreg845, 273; mem:LD4[%nblock_used82] GPR32:%vreg844 GPR64common:%vreg845
     %vreg844:	[3536r,3632r:0)  0@3536r
        -->	[3608r,3632r:0)  0@3608r
     %vreg845:	[3520r,3536r:0)  0@3520r
        -->	[3520r,3608r:0)  0@3520r
handleMove 3520B -> 3560B: %vreg845<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg845
     %vreg845:	[3520r,3608r:0)  0@3520r
        -->	[3560r,3608r:0)  0@3560r
handleMove 3376B -> 3400B: %vreg864<def> = CSELWr %vreg862, %vreg863, 0, %NZCV<imp-use,kill>; GPR32:%vreg864,%vreg862,%vreg863
     %vreg864:	[3376r,3408r:0)  0@3376r
        -->	[3400r,3408r:0)  0@3400r
     %vreg862:	[3232r,3376r:0)  0@3232r
        -->	[3232r,3400r:0)  0@3232r
     %vreg863:	[3248r,3376r:0)  0@3248r
        -->	[3248r,3400r:0)  0@3248r
     NZCV:	[1664r,1680r:17)[1872r,1888r:16)[3104r,3120r:15)[3360r,3400r:13)[3632r,3648r:14)[3760r,3776r:12)[4928r,4944r:11)[5184r,5200r:9)[5456r,5472r:10)[5584r,5600r:8)[6752r,6768r:7)[7008r,7024r:5)[7280r,7296r:6)[7408r,7424r:4)[8528r,8544r:3)[8784r,8800r:2)[10000r,10016r:1)[10256r,10272r:0)[11760r,11776r:25)[11968r,11984r:24)[13056r,13072r:23)[13184r,13200r:22)[14208r,14224r:21)[14336r,14352r:20)[15360r,15376r:19)[15488r,15504r:18)  0@10256r 1@10000r 2@8784r 3@8528r 4@7408r 5@7008r 6@7280r 7@6752r 8@5584r 9@5184r 10@5456r 11@4928r 12@3760r 13@3360r 14@3632r 15@3104r 16@1872r 17@1664r 18@15488r 19@15360r 20@14336r 21@14208r 22@13184r 23@13056r 24@11968r 25@11760r
        -->	[1664r,1680r:17)[1872r,1888r:16)[3104r,3120r:15)[3360r,3400r:13)[3632r,3648r:14)[3760r,3776r:12)[4928r,4944r:11)[5184r,5200r:9)[5456r,5472r:10)[5584r,5600r:8)[6752r,6768r:7)[7008r,7024r:5)[7280r,7296r:6)[7408r,7424r:4)[8528r,8544r:3)[8784r,8800r:2)[10000r,10016r:1)[10256r,10272r:0)[11760r,11776r:25)[11968r,11984r:24)[13056r,13072r:23)[13184r,13200r:22)[14208r,14224r:21)[14336r,14352r:20)[15360r,15376r:19)[15488r,15504r:18)  0@10256r 1@10000r 2@8784r 3@8528r 4@7408r 5@7008r 6@7280r 7@6752r 8@5584r 9@5184r 10@5456r 11@4928r 12@3760r 13@3360r 14@3632r 15@3104r 16@1872r 17@1664r 18@15488r 19@15360r 20@14336r 21@14208r 22@13184r 23@13056r 24@11968r 25@11760r
handleMove 3248B -> 3224B: %vreg863<def> = COPY %WZR; GPR32:%vreg863
     %vreg863:	[3248r,3400r:0)  0@3248r
        -->	[3224r,3400r:0)  0@3224r
     WZR:	[1664r,1664d:17)[1872r,1872d:16)[3104r,3104d:15)[3360r,3360d:13)[3632r,3632d:14)[3760r,3760d:12)[4928r,4928d:11)[5184r,5184d:9)[5456r,5456d:10)[5584r,5584d:8)[6752r,6752d:7)[7008r,7008d:5)[7280r,7280d:6)[7408r,7408d:4)[8528r,8528d:3)[8784r,8784d:2)[10000r,10000d:1)[10256r,10256d:0)[11760r,11760d:25)[11968r,11968d:24)[13056r,13056d:23)[13184r,13184d:22)[14208r,14208d:21)[14336r,14336d:20)[15360r,15360d:19)[15488r,15488d:18)  0@10256r 1@10000r 2@8784r 3@8528r 4@7408r 5@7008r 6@7280r 7@6752r 8@5584r 9@5184r 10@5456r 11@4928r 12@3760r 13@3360r 14@3632r 15@3104r 16@1872r 17@1664r 18@15488r 19@15360r 20@14336r 21@14208r 22@13184r 23@13056r 24@11968r 25@11760r
        -->	[1664r,1664d:17)[1872r,1872d:16)[3104r,3104d:15)[3360r,3360d:13)[3632r,3632d:14)[3760r,3760d:12)[4928r,4928d:11)[5184r,5184d:9)[5456r,5456d:10)[5584r,5584d:8)[6752r,6752d:7)[7008r,7008d:5)[7280r,7280d:6)[7408r,7408d:4)[8528r,8528d:3)[8784r,8784d:2)[10000r,10000d:1)[10256r,10256d:0)[11760r,11760d:25)[11968r,11968d:24)[13056r,13056d:23)[13184r,13184d:22)[14208r,14208d:21)[14336r,14336d:20)[15360r,15360d:19)[15488r,15488d:18)  0@10256r 1@10000r 2@8784r 3@8528r 4@7408r 5@7008r 6@7280r 7@6752r 8@5584r 9@5184r 10@5456r 11@4928r 12@3760r 13@3360r 14@3632r 15@3104r 16@1872r 17@1664r 18@15488r 19@15360r 20@14336r 21@14208r 22@13184r 23@13056r 24@11968r 25@11760r
handleMove 3360B -> 3396B: %WZR<def> = SUBSWri %vreg866, 1, 0, %NZCV<imp-def>; GPR32common:%vreg866
     WZR:	[1664r,1664d:17)[1872r,1872d:16)[3104r,3104d:15)[3360r,3360d:13)[3632r,3632d:14)[3760r,3760d:12)[4928r,4928d:11)[5184r,5184d:9)[5456r,5456d:10)[5584r,5584d:8)[6752r,6752d:7)[7008r,7008d:5)[7280r,7280d:6)[7408r,7408d:4)[8528r,8528d:3)[8784r,8784d:2)[10000r,10000d:1)[10256r,10256d:0)[11760r,11760d:25)[11968r,11968d:24)[13056r,13056d:23)[13184r,13184d:22)[14208r,14208d:21)[14336r,14336d:20)[15360r,15360d:19)[15488r,15488d:18)  0@10256r 1@10000r 2@8784r 3@8528r 4@7408r 5@7008r 6@7280r 7@6752r 8@5584r 9@5184r 10@5456r 11@4928r 12@3760r 13@3360r 14@3632r 15@3104r 16@1872r 17@1664r 18@15488r 19@15360r 20@14336r 21@14208r 22@13184r 23@13056r 24@11968r 25@11760r
        -->	[1664r,1664d:17)[1872r,1872d:16)[3104r,3104d:15)[3396r,3396d:13)[3632r,3632d:14)[3760r,3760d:12)[4928r,4928d:11)[5184r,5184d:9)[5456r,5456d:10)[5584r,5584d:8)[6752r,6752d:7)[7008r,7008d:5)[7280r,7280d:6)[7408r,7408d:4)[8528r,8528d:3)[8784r,8784d:2)[10000r,10000d:1)[10256r,10256d:0)[11760r,11760d:25)[11968r,11968d:24)[13056r,13056d:23)[13184r,13184d:22)[14208r,14208d:21)[14336r,14336d:20)[15360r,15360d:19)[15488r,15488d:18)  0@10256r 1@10000r 2@8784r 3@8528r 4@7408r 5@7008r 6@7280r 7@6752r 8@5584r 9@5184r 10@5456r 11@4928r 12@3760r 13@3396r 14@3632r 15@3104r 16@1872r 17@1664r 18@15488r 19@15360r 20@14336r 21@14208r 22@13184r 23@13056r 24@11968r 25@11760r
     %vreg866:	[3344r,3360r:0)  0@3344r
        -->	[3344r,3396r:0)  0@3344r
     NZCV:	[1664r,1680r:17)[1872r,1888r:16)[3104r,3120r:15)[3360r,3400r:13)[3632r,3648r:14)[3760r,3776r:12)[4928r,4944r:11)[5184r,5200r:9)[5456r,5472r:10)[5584r,5600r:8)[6752r,6768r:7)[7008r,7024r:5)[7280r,7296r:6)[7408r,7424r:4)[8528r,8544r:3)[8784r,8800r:2)[10000r,10016r:1)[10256r,10272r:0)[11760r,11776r:25)[11968r,11984r:24)[13056r,13072r:23)[13184r,13200r:22)[14208r,14224r:21)[14336r,14352r:20)[15360r,15376r:19)[15488r,15504r:18)  0@10256r 1@10000r 2@8784r 3@8528r 4@7408r 5@7008r 6@7280r 7@6752r 8@5584r 9@5184r 10@5456r 11@4928r 12@3760r 13@3360r 14@3632r 15@3104r 16@1872r 17@1664r 18@15488r 19@15360r 20@14336r 21@14208r 22@13184r 23@13056r 24@11968r 25@11760r
        -->	[1664r,1680r:17)[1872r,1888r:16)[3104r,3120r:15)[3396r,3400r:13)[3632r,3648r:14)[3760r,3776r:12)[4928r,4944r:11)[5184r,5200r:9)[5456r,5472r:10)[5584r,5600r:8)[6752r,6768r:7)[7008r,7024r:5)[7280r,7296r:6)[7408r,7424r:4)[8528r,8544r:3)[8784r,8800r:2)[10000r,10016r:1)[10256r,10272r:0)[11760r,11776r:25)[11968r,11984r:24)[13056r,13072r:23)[13184r,13200r:22)[14208r,14224r:21)[14336r,14352r:20)[15360r,15376r:19)[15488r,15504r:18)  0@10256r 1@10000r 2@8784r 3@8528r 4@7408r 5@7008r 6@7280r 7@6752r 8@5584r 9@5184r 10@5456r 11@4928r 12@3760r 13@3396r 14@3632r 15@3104r 16@1872r 17@1664r 18@15488r 19@15360r 20@14336r 21@14208r 22@13184r 23@13056r 24@11968r 25@11760r
handleMove 3232B -> 3400B: %vreg862<def> = MOVi32imm 1; GPR32:%vreg862
     %vreg862:	[3232r,3416r:0)  0@3232r
        -->	[3400r,3416r:0)  0@3400r
handleMove 3712B -> 3736B: %vreg881<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg881
     %vreg881:	[3712r,3760r:0)  0@3712r
        -->	[3736r,3760r:0)  0@3736r
AllocationOrder(GPR32sponly) = [ ]
handleMove 4560B -> 4584B: %vreg891<def> = ORRWrs %vreg924, %vreg893, 16; GPR32:%vreg891,%vreg924 GPR32common:%vreg893
     %vreg891:	[4560r,4592r:0)  0@4560r
        -->	[4584r,4592r:0)  0@4584r
     %vreg924:	[4320r,4560r:0)  0@4320r
        -->	[4320r,4584r:0)  0@4320r
     %vreg893:	[4544r,4560r:0)  0@4544r
        -->	[4544r,4584r:0)  0@4544r
handleMove 4544B -> 4580B: %vreg893<def> = ANDWri %vreg896, 3; GPR32common:%vreg893 GPR32:%vreg896
     %vreg893:	[4544r,4584r:0)  0@4544r
        -->	[4580r,4584r:0)  0@4580r
     %vreg896:	[4528r,4544r:0)  0@4528r
        -->	[4528r,4580r:0)  0@4528r
handleMove 4528B -> 4584B: %vreg896<def> = LSRVWr %vreg906, %vreg899; GPR32:%vreg896,%vreg906,%vreg899
     %vreg896:	[4528r,4592r:0)  0@4528r
        -->	[4584r,4592r:0)  0@4584r
     %vreg906:	[4464r,4528r:0)  0@4464r
        -->	[4464r,4584r:0)  0@4464r
     %vreg899:	[4512r,4528r:0)  0@4512r
        -->	[4512r,4584r:0)  0@4512r
handleMove 4320B -> 4504B: %vreg924<def> = LDRHHui %vreg929, 0; mem:LD2[%arrayidx106] GPR32:%vreg924 GPR64common:%vreg929
     %vreg924:	[4320r,4600r:0)  0@4320r
        -->	[4504r,4600r:0)  0@4504r
     %vreg929:	[4304r,4320r:0)  0@4304r
        -->	[4304r,4504r:0)  0@4304r
handleMove 4464B -> 4500B: %vreg906<def> = LDRBBui %vreg909, 0; mem:LD1[%arrayidx112] GPR32:%vreg906 GPR64common:%vreg909
     %vreg906:	[4464r,4584r:0)  0@4464r
        -->	[4500r,4584r:0)  0@4500r
     %vreg909:	[4448r,4464r:0)  0@4448r
        -->	[4448r,4500r:0)  0@4448r
handleMove 4448B -> 4504B: %vreg909<def> = ADDXrr %vreg911, %vreg915; GPR64common:%vreg909 GPR64:%vreg911,%vreg915
     %vreg909:	[4448r,4512r:0)  0@4448r
        -->	[4504r,4512r:0)  0@4504r
     %vreg911:	[4432r,4448r:0)  0@4432r
        -->	[4432r,4504r:0)  0@4432r
     %vreg915:	[4400r,4448r:0)  0@4400r
        -->	[4400r,4504r:0)  0@4400r
handleMove 4400B -> 4488B: %vreg915<def> = UBFMXri %vreg914, 0, 31; GPR64:%vreg915,%vreg914
     %vreg915:	[4400r,4504r:0)  0@4400r
        -->	[4488r,4504r:0)  0@4488r
     %vreg914:	[4368r,4400r:0)  0@4368r
        -->	[4368r,4488r:0)  0@4368r
handleMove 4368B -> 4484B: %vreg914:sub_32<def,read-undef> = UBFMWri %vreg919, 1, 31; GPR64:%vreg914 GPR32:%vreg919
     %vreg914:	[4368r,4488r:0)  0@4368r
        -->	[4484r,4488r:0)  0@4484r
     %vreg919:	[4352r,4368r:0)  0@4352r
        -->	[4352r,4484r:0)  0@4352r
handleMove 4432B -> 4488B: %vreg911<def> = LDRXui %vreg912, 396; mem:LD8[%ll4111] GPR64:%vreg911 GPR64common:%vreg912
     %vreg911:	[4432r,4520r:0)  0@4432r
        -->	[4488r,4520r:0)  0@4488r
     %vreg912:	[4416r,4432r:0)  0@4416r
        -->	[4416r,4488r:0)  0@4416r
handleMove 4304B -> 4424B: %vreg929<def> = ADDXrr %vreg931, %vreg928; GPR64common:%vreg929 GPR64:%vreg931,%vreg928
     %vreg929:	[4304r,4536r:0)  0@4304r
        -->	[4424r,4536r:0)  0@4424r
     %vreg931:	[4256r,4304r:0)  0@4256r
        -->	[4256r,4424r:0)  0@4256r
     %vreg928:	[4288r,4304r:0)  0@4288r
        -->	[4288r,4424r:0)  0@4288r
handleMove 4352B -> 4420B: %vreg919<def> = LDRWui %vreg920, 15; mem:LD4[%tPos108] GPR32:%vreg919 GPR64common:%vreg920
     %vreg919:	[4352r,4496r:0)  0@4352r
        -->	[4420r,4496r:0)  0@4420r
     %vreg920:	[4336r,4352r:0)  0@4336r
        -->	[4336r,4420r:0)  0@4336r
handleMove 4288B -> 4344B: %vreg928<def> = MADDXrrr %vreg938, %vreg927, %XZR; GPR64:%vreg928,%vreg938,%vreg927
     %vreg928:	[4288r,4424r:0)  0@4288r
        -->	[4344r,4424r:0)  0@4344r
     %vreg938:	[4208r,4288r:0)  0@4208r
        -->	[4208r,4344r:0)  0@4208r
     %vreg927:	[4272r,4288r:0)  0@4272r
        -->	[4272r,4344r:0)  0@4272r
     WZR:	[1664r,1664d:17)[1872r,1872d:16)[3104r,3104d:15)[3408r,3408d:13)[3632r,3632d:14)[3760r,3760d:12)[4928r,4928d:11)[5184r,5184d:9)[5456r,5456d:10)[5584r,5584d:8)[6752r,6752d:7)[7008r,7008d:5)[7280r,7280d:6)[7408r,7408d:4)[8528r,8528d:3)[8784r,8784d:2)[10000r,10000d:1)[10256r,10256d:0)[11760r,11760d:25)[11968r,11968d:24)[13056r,13056d:23)[13184r,13184d:22)[14208r,14208d:21)[14336r,14336d:20)[15360r,15360d:19)[15488r,15488d:18)  0@10256r 1@10000r 2@8784r 3@8528r 4@7408r 5@7008r 6@7280r 7@6752r 8@5584r 9@5184r 10@5456r 11@4928r 12@3760r 13@3408r 14@3632r 15@3104r 16@1872r 17@1664r 18@15488r 19@15360r 20@14336r 21@14208r 22@13184r 23@13056r 24@11968r 25@11760r
        -->	[1664r,1664d:17)[1872r,1872d:16)[3104r,3104d:15)[3408r,3408d:13)[3632r,3632d:14)[3760r,3760d:12)[4928r,4928d:11)[5184r,5184d:9)[5456r,5456d:10)[5584r,5584d:8)[6752r,6752d:7)[7008r,7008d:5)[7280r,7280d:6)[7408r,7408d:4)[8528r,8528d:3)[8784r,8784d:2)[10000r,10000d:1)[10256r,10256d:0)[11760r,11760d:25)[11968r,11968d:24)[13056r,13056d:23)[13184r,13184d:22)[14208r,14208d:21)[14336r,14336d:20)[15360r,15360d:19)[15488r,15488d:18)  0@10256r 1@10000r 2@8784r 3@8528r 4@7408r 5@7008r 6@7280r 7@6752r 8@5584r 9@5184r 10@5456r 11@4928r 12@3760r 13@3408r 14@3632r 15@3104r 16@1872r 17@1664r 18@15488r 19@15360r 20@14336r 21@14208r 22@13184r 23@13056r 24@11968r 25@11760r
handleMove 4256B -> 4340B: %vreg931<def> = LDRXui %vreg932, 395; mem:LD8[%ll16105] GPR64:%vreg931 GPR64common:%vreg932
     %vreg931:	[4256r,4424r:0)  0@4256r
        -->	[4340r,4424r:0)  0@4340r
     %vreg932:	[4240r,4256r:0)  0@4240r
        -->	[4240r,4340r:0)  0@4240r
handleMove 4208B -> 4248B: %vreg938:sub_32<def,read-undef> = LDRWui %vreg939, 15; mem:LD4[%tPos103] GPR64:%vreg938 GPR64common:%vreg939
     %vreg938:	[4208r,4344r:0)  0@4208r
        -->	[4248r,4344r:0)  0@4248r
     %vreg939:	[4192r,4208r:0)  0@4192r
        -->	[4192r,4248r:0)  0@4192r
handleMove 3952B -> 3976B: %vreg951<def> = LDRWui %vreg952, 15; mem:LD4[%tPos98] GPR32:%vreg951 GPR64common:%vreg952
     %vreg951:	[3952r,4016r:0)  0@3952r
        -->	[3976r,4016r:0)  0@3976r
     %vreg952:	[3936r,3952r:0)  0@3936r
        -->	[3936r,3976r:0)  0@3936r
handleMove 3888B -> 3912B: %vreg953<def> = MOVi32imm 2; GPR32:%vreg953
     %vreg953:	[3888r,3920r:0)  0@3888r
        -->	[3912r,3920r:0)  0@3912r
AllocationOrder(GPR32sponly) = [ ]
handleMove 4688B -> 4744B: %vreg972<def> = ADDXri %vreg971, <ga:@BZ2_rNums>[TF=34], 0; GPR64common:%vreg972,%vreg971
     %vreg972:	[4688r,4768r:0)  0@4688r
        -->	[4744r,4768r:0)  0@4744r
     %vreg971:	[4672r,4688r:0)  0@4672r
        -->	[4672r,4744r:0)  0@4672r
handleMove 4672B -> 4728B: %vreg971<def> = ADRP <ga:@BZ2_rNums>[TF=1]; GPR64common:%vreg971
     %vreg971:	[4672r,4744r:0)  0@4672r
        -->	[4728r,4744r:0)  0@4728r
AllocationOrder(GPR32sponly) = [ ]
handleMove 5360B -> 5432B: %vreg995<def> = LDRWui %vreg996, 273; mem:LD4[%nblock_used150] GPR32:%vreg995 GPR64common:%vreg996
     %vreg995:	[5360r,5456r:0)  0@5360r
        -->	[5432r,5456r:0)  0@5432r
     %vreg996:	[5344r,5360r:0)  0@5344r
        -->	[5344r,5432r:0)  0@5344r
handleMove 5344B -> 5384B: %vreg996<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg996
     %vreg996:	[5344r,5432r:0)  0@5344r
        -->	[5384r,5432r:0)  0@5384r
handleMove 5200B -> 5224B: %vreg1015<def> = CSELWr %vreg1013, %vreg1014, 0, %NZCV<imp-use>; GPR32:%vreg1015,%vreg1013,%vreg1014
     %vreg1015:	[5200r,5232r:0)  0@5200r
        -->	[5224r,5232r:0)  0@5224r
     %vreg1013:	[5056r,5200r:0)  0@5056r
        -->	[5056r,5224r:0)  0@5056r
     %vreg1014:	[5072r,5200r:0)  0@5072r
        -->	[5072r,5224r:0)  0@5072r
     NZCV:	[1664r,1680r:17)[1872r,1888r:16)[3104r,3120r:15)[3408r,3416r:13)[3632r,3648r:14)[3760r,3776r:12)[4928r,4944r:11)[5184r,5200r:9)[5456r,5472r:10)[5584r,5600r:8)[6752r,6768r:7)[7008r,7024r:5)[7280r,7296r:6)[7408r,7424r:4)[8528r,8544r:3)[8784r,8800r:2)[10000r,10016r:1)[10256r,10272r:0)[11760r,11776r:25)[11968r,11984r:24)[13056r,13072r:23)[13184r,13200r:22)[14208r,14224r:21)[14336r,14352r:20)[15360r,15376r:19)[15488r,15504r:18)  0@10256r 1@10000r 2@8784r 3@8528r 4@7408r 5@7008r 6@7280r 7@6752r 8@5584r 9@5184r 10@5456r 11@4928r 12@3760r 13@3408r 14@3632r 15@3104r 16@1872r 17@1664r 18@15488r 19@15360r 20@14336r 21@14208r 22@13184r 23@13056r 24@11968r 25@11760r
        -->	[1664r,1680r:17)[1872r,1888r:16)[3104r,3120r:15)[3408r,3416r:13)[3632r,3648r:14)[3760r,3776r:12)[4928r,4944r:11)[5184r,5224r:9)[5456r,5472r:10)[5584r,5600r:8)[6752r,6768r:7)[7008r,7024r:5)[7280r,7296r:6)[7408r,7424r:4)[8528r,8544r:3)[8784r,8800r:2)[10000r,10016r:1)[10256r,10272r:0)[11760r,11776r:25)[11968r,11984r:24)[13056r,13072r:23)[13184r,13200r:22)[14208r,14224r:21)[14336r,14352r:20)[15360r,15376r:19)[15488r,15504r:18)  0@10256r 1@10000r 2@8784r 3@8528r 4@7408r 5@7008r 6@7280r 7@6752r 8@5584r 9@5184r 10@5456r 11@4928r 12@3760r 13@3408r 14@3632r 15@3104r 16@1872r 17@1664r 18@15488r 19@15360r 20@14336r 21@14208r 22@13184r 23@13056r 24@11968r 25@11760r
handleMove 5072B -> 5048B: %vreg1014<def> = COPY %WZR; GPR32:%vreg1014
     %vreg1014:	[5072r,5224r:0)  0@5072r
        -->	[5048r,5224r:0)  0@5048r
     WZR:	[1664r,1664d:17)[1872r,1872d:16)[3104r,3104d:15)[3408r,3408d:13)[3632r,3632d:14)[3760r,3760d:12)[4928r,4928d:11)[5184r,5184d:9)[5456r,5456d:10)[5584r,5584d:8)[6752r,6752d:7)[7008r,7008d:5)[7280r,7280d:6)[7408r,7408d:4)[8528r,8528d:3)[8784r,8784d:2)[10000r,10000d:1)[10256r,10256d:0)[11760r,11760d:25)[11968r,11968d:24)[13056r,13056d:23)[13184r,13184d:22)[14208r,14208d:21)[14336r,14336d:20)[15360r,15360d:19)[15488r,15488d:18)  0@10256r 1@10000r 2@8784r 3@8528r 4@7408r 5@7008r 6@7280r 7@6752r 8@5584r 9@5184r 10@5456r 11@4928r 12@3760r 13@3408r 14@3632r 15@3104r 16@1872r 17@1664r 18@15488r 19@15360r 20@14336r 21@14208r 22@13184r 23@13056r 24@11968r 25@11760r
        -->	[1664r,1664d:17)[1872r,1872d:16)[3104r,3104d:15)[3408r,3408d:13)[3632r,3632d:14)[3760r,3760d:12)[4928r,4928d:11)[5184r,5184d:9)[5456r,5456d:10)[5584r,5584d:8)[6752r,6752d:7)[7008r,7008d:5)[7280r,7280d:6)[7408r,7408d:4)[8528r,8528d:3)[8784r,8784d:2)[10000r,10000d:1)[10256r,10256d:0)[11760r,11760d:25)[11968r,11968d:24)[13056r,13056d:23)[13184r,13184d:22)[14208r,14208d:21)[14336r,14336d:20)[15360r,15360d:19)[15488r,15488d:18)  0@10256r 1@10000r 2@8784r 3@8528r 4@7408r 5@7008r 6@7280r 7@6752r 8@5584r 9@5184r 10@5456r 11@4928r 12@3760r 13@3408r 14@3632r 15@3104r 16@1872r 17@1664r 18@15488r 19@15360r 20@14336r 21@14208r 22@13184r 23@13056r 24@11968r 25@11760r
handleMove 5184B -> 5220B: %WZR<def> = SUBSWri %vreg1017, 1, 0, %NZCV<imp-def>; GPR32common:%vreg1017
     WZR:	[1664r,1664d:17)[1872r,1872d:16)[3104r,3104d:15)[3408r,3408d:13)[3632r,3632d:14)[3760r,3760d:12)[4928r,4928d:11)[5184r,5184d:9)[5456r,5456d:10)[5584r,5584d:8)[6752r,6752d:7)[7008r,7008d:5)[7280r,7280d:6)[7408r,7408d:4)[8528r,8528d:3)[8784r,8784d:2)[10000r,10000d:1)[10256r,10256d:0)[11760r,11760d:25)[11968r,11968d:24)[13056r,13056d:23)[13184r,13184d:22)[14208r,14208d:21)[14336r,14336d:20)[15360r,15360d:19)[15488r,15488d:18)  0@10256r 1@10000r 2@8784r 3@8528r 4@7408r 5@7008r 6@7280r 7@6752r 8@5584r 9@5184r 10@5456r 11@4928r 12@3760r 13@3408r 14@3632r 15@3104r 16@1872r 17@1664r 18@15488r 19@15360r 20@14336r 21@14208r 22@13184r 23@13056r 24@11968r 25@11760r
        -->	[1664r,1664d:17)[1872r,1872d:16)[3104r,3104d:15)[3408r,3408d:13)[3632r,3632d:14)[3760r,3760d:12)[4928r,4928d:11)[5220r,5220d:9)[5456r,5456d:10)[5584r,5584d:8)[6752r,6752d:7)[7008r,7008d:5)[7280r,7280d:6)[7408r,7408d:4)[8528r,8528d:3)[8784r,8784d:2)[10000r,10000d:1)[10256r,10256d:0)[11760r,11760d:25)[11968r,11968d:24)[13056r,13056d:23)[13184r,13184d:22)[14208r,14208d:21)[14336r,14336d:20)[15360r,15360d:19)[15488r,15488d:18)  0@10256r 1@10000r 2@8784r 3@8528r 4@7408r 5@7008r 6@7280r 7@6752r 8@5584r 9@5220r 10@5456r 11@4928r 12@3760r 13@3408r 14@3632r 15@3104r 16@1872r 17@1664r 18@15488r 19@15360r 20@14336r 21@14208r 22@13184r 23@13056r 24@11968r 25@11760r
     %vreg1017:	[5168r,5184r:0)  0@5168r
        -->	[5168r,5220r:0)  0@5168r
     NZCV:	[1664r,1680r:17)[1872r,1888r:16)[3104r,3120r:15)[3408r,3416r:13)[3632r,3648r:14)[3760r,3776r:12)[4928r,4944r:11)[5184r,5224r:9)[5456r,5472r:10)[5584r,5600r:8)[6752r,6768r:7)[7008r,7024r:5)[7280r,7296r:6)[7408r,7424r:4)[8528r,8544r:3)[8784r,8800r:2)[10000r,10016r:1)[10256r,10272r:0)[11760r,11776r:25)[11968r,11984r:24)[13056r,13072r:23)[13184r,13200r:22)[14208r,14224r:21)[14336r,14352r:20)[15360r,15376r:19)[15488r,15504r:18)  0@10256r 1@10000r 2@8784r 3@8528r 4@7408r 5@7008r 6@7280r 7@6752r 8@5584r 9@5184r 10@5456r 11@4928r 12@3760r 13@3408r 14@3632r 15@3104r 16@1872r 17@1664r 18@15488r 19@15360r 20@14336r 21@14208r 22@13184r 23@13056r 24@11968r 25@11760r
        -->	[1664r,1680r:17)[1872r,1888r:16)[3104r,3120r:15)[3408r,3416r:13)[3632r,3648r:14)[3760r,3776r:12)[4928r,4944r:11)[5220r,5224r:9)[5456r,5472r:10)[5584r,5600r:8)[6752r,6768r:7)[7008r,7024r:5)[7280r,7296r:6)[7408r,7424r:4)[8528r,8544r:3)[8784r,8800r:2)[10000r,10016r:1)[10256r,10272r:0)[11760r,11776r:25)[11968r,11984r:24)[13056r,13072r:23)[13184r,13200r:22)[14208r,14224r:21)[14336r,14352r:20)[15360r,15376r:19)[15488r,15504r:18)  0@10256r 1@10000r 2@8784r 3@8528r 4@7408r 5@7008r 6@7280r 7@6752r 8@5584r 9@5220r 10@5456r 11@4928r 12@3760r 13@3408r 14@3632r 15@3104r 16@1872r 17@1664r 18@15488r 19@15360r 20@14336r 21@14208r 22@13184r 23@13056r 24@11968r 25@11760r
handleMove 5056B -> 5224B: %vreg1013<def> = MOVi32imm 1; GPR32:%vreg1013
     %vreg1013:	[5056r,5240r:0)  0@5056r
        -->	[5224r,5240r:0)  0@5224r
handleMove 5536B -> 5560B: %vreg1032<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg1032
     %vreg1032:	[5536r,5584r:0)  0@5536r
        -->	[5560r,5584r:0)  0@5560r
AllocationOrder(GPR32sponly) = [ ]
handleMove 6384B -> 6408B: %vreg1042<def> = ORRWrs %vreg1075, %vreg1044, 16; GPR32:%vreg1042,%vreg1075 GPR32common:%vreg1044
     %vreg1042:	[6384r,6416r:0)  0@6384r
        -->	[6408r,6416r:0)  0@6408r
     %vreg1075:	[6144r,6384r:0)  0@6144r
        -->	[6144r,6408r:0)  0@6144r
     %vreg1044:	[6368r,6384r:0)  0@6368r
        -->	[6368r,6408r:0)  0@6368r
handleMove 6368B -> 6404B: %vreg1044<def> = ANDWri %vreg1047, 3; GPR32common:%vreg1044 GPR32:%vreg1047
     %vreg1044:	[6368r,6408r:0)  0@6368r
        -->	[6404r,6408r:0)  0@6404r
     %vreg1047:	[6352r,6368r:0)  0@6352r
        -->	[6352r,6404r:0)  0@6352r
handleMove 6352B -> 6408B: %vreg1047<def> = LSRVWr %vreg1057, %vreg1050; GPR32:%vreg1047,%vreg1057,%vreg1050
     %vreg1047:	[6352r,6416r:0)  0@6352r
        -->	[6408r,6416r:0)  0@6408r
     %vreg1057:	[6288r,6352r:0)  0@6288r
        -->	[6288r,6408r:0)  0@6288r
     %vreg1050:	[6336r,6352r:0)  0@6336r
        -->	[6336r,6408r:0)  0@6336r
handleMove 6144B -> 6328B: %vreg1075<def> = LDRHHui %vreg1080, 0; mem:LD2[%arrayidx174] GPR32:%vreg1075 GPR64common:%vreg1080
     %vreg1075:	[6144r,6424r:0)  0@6144r
        -->	[6328r,6424r:0)  0@6328r
     %vreg1080:	[6128r,6144r:0)  0@6128r
        -->	[6128r,6328r:0)  0@6128r
handleMove 6288B -> 6324B: %vreg1057<def> = LDRBBui %vreg1060, 0; mem:LD1[%arrayidx180] GPR32:%vreg1057 GPR64common:%vreg1060
     %vreg1057:	[6288r,6408r:0)  0@6288r
        -->	[6324r,6408r:0)  0@6324r
     %vreg1060:	[6272r,6288r:0)  0@6272r
        -->	[6272r,6324r:0)  0@6272r
handleMove 6272B -> 6328B: %vreg1060<def> = ADDXrr %vreg1062, %vreg1066; GPR64common:%vreg1060 GPR64:%vreg1062,%vreg1066
     %vreg1060:	[6272r,6336r:0)  0@6272r
        -->	[6328r,6336r:0)  0@6328r
     %vreg1062:	[6256r,6272r:0)  0@6256r
        -->	[6256r,6328r:0)  0@6256r
     %vreg1066:	[6224r,6272r:0)  0@6224r
        -->	[6224r,6328r:0)  0@6224r
handleMove 6224B -> 6312B: %vreg1066<def> = UBFMXri %vreg1065, 0, 31; GPR64:%vreg1066,%vreg1065
     %vreg1066:	[6224r,6328r:0)  0@6224r
        -->	[6312r,6328r:0)  0@6312r
     %vreg1065:	[6192r,6224r:0)  0@6192r
        -->	[6192r,6312r:0)  0@6192r
handleMove 6192B -> 6308B: %vreg1065:sub_32<def,read-undef> = UBFMWri %vreg1070, 1, 31; GPR64:%vreg1065 GPR32:%vreg1070
     %vreg1065:	[6192r,6312r:0)  0@6192r
        -->	[6308r,6312r:0)  0@6308r
     %vreg1070:	[6176r,6192r:0)  0@6176r
        -->	[6176r,6308r:0)  0@6176r
handleMove 6256B -> 6312B: %vreg1062<def> = LDRXui %vreg1063, 396; mem:LD8[%ll4179] GPR64:%vreg1062 GPR64common:%vreg1063
     %vreg1062:	[6256r,6344r:0)  0@6256r
        -->	[6312r,6344r:0)  0@6312r
     %vreg1063:	[6240r,6256r:0)  0@6240r
        -->	[6240r,6312r:0)  0@6240r
handleMove 6128B -> 6248B: %vreg1080<def> = ADDXrr %vreg1082, %vreg1079; GPR64common:%vreg1080 GPR64:%vreg1082,%vreg1079
     %vreg1080:	[6128r,6360r:0)  0@6128r
        -->	[6248r,6360r:0)  0@6248r
     %vreg1082:	[6080r,6128r:0)  0@6080r
        -->	[6080r,6248r:0)  0@6080r
     %vreg1079:	[6112r,6128r:0)  0@6112r
        -->	[6112r,6248r:0)  0@6112r
handleMove 6176B -> 6244B: %vreg1070<def> = LDRWui %vreg1071, 15; mem:LD4[%tPos176] GPR32:%vreg1070 GPR64common:%vreg1071
     %vreg1070:	[6176r,6320r:0)  0@6176r
        -->	[6244r,6320r:0)  0@6244r
     %vreg1071:	[6160r,6176r:0)  0@6160r
        -->	[6160r,6244r:0)  0@6160r
handleMove 6112B -> 6168B: %vreg1079<def> = MADDXrrr %vreg1089, %vreg1078, %XZR; GPR64:%vreg1079,%vreg1089,%vreg1078
     %vreg1079:	[6112r,6248r:0)  0@6112r
        -->	[6168r,6248r:0)  0@6168r
     %vreg1089:	[6032r,6112r:0)  0@6032r
        -->	[6032r,6168r:0)  0@6032r
     %vreg1078:	[6096r,6112r:0)  0@6096r
        -->	[6096r,6168r:0)  0@6096r
     WZR:	[1664r,1664d:17)[1872r,1872d:16)[3104r,3104d:15)[3408r,3408d:13)[3632r,3632d:14)[3760r,3760d:12)[4928r,4928d:11)[5232r,5232d:9)[5456r,5456d:10)[5584r,5584d:8)[6752r,6752d:7)[7008r,7008d:5)[7280r,7280d:6)[7408r,7408d:4)[8528r,8528d:3)[8784r,8784d:2)[10000r,10000d:1)[10256r,10256d:0)[11760r,11760d:25)[11968r,11968d:24)[13056r,13056d:23)[13184r,13184d:22)[14208r,14208d:21)[14336r,14336d:20)[15360r,15360d:19)[15488r,15488d:18)  0@10256r 1@10000r 2@8784r 3@8528r 4@7408r 5@7008r 6@7280r 7@6752r 8@5584r 9@5232r 10@5456r 11@4928r 12@3760r 13@3408r 14@3632r 15@3104r 16@1872r 17@1664r 18@15488r 19@15360r 20@14336r 21@14208r 22@13184r 23@13056r 24@11968r 25@11760r
        -->	[1664r,1664d:17)[1872r,1872d:16)[3104r,3104d:15)[3408r,3408d:13)[3632r,3632d:14)[3760r,3760d:12)[4928r,4928d:11)[5232r,5232d:9)[5456r,5456d:10)[5584r,5584d:8)[6752r,6752d:7)[7008r,7008d:5)[7280r,7280d:6)[7408r,7408d:4)[8528r,8528d:3)[8784r,8784d:2)[10000r,10000d:1)[10256r,10256d:0)[11760r,11760d:25)[11968r,11968d:24)[13056r,13056d:23)[13184r,13184d:22)[14208r,14208d:21)[14336r,14336d:20)[15360r,15360d:19)[15488r,15488d:18)  0@10256r 1@10000r 2@8784r 3@8528r 4@7408r 5@7008r 6@7280r 7@6752r 8@5584r 9@5232r 10@5456r 11@4928r 12@3760r 13@3408r 14@3632r 15@3104r 16@1872r 17@1664r 18@15488r 19@15360r 20@14336r 21@14208r 22@13184r 23@13056r 24@11968r 25@11760r
handleMove 6080B -> 6164B: %vreg1082<def> = LDRXui %vreg1083, 395; mem:LD8[%ll16173] GPR64:%vreg1082 GPR64common:%vreg1083
     %vreg1082:	[6080r,6248r:0)  0@6080r
        -->	[6164r,6248r:0)  0@6164r
     %vreg1083:	[6064r,6080r:0)  0@6064r
        -->	[6064r,6164r:0)  0@6064r
handleMove 6032B -> 6072B: %vreg1089:sub_32<def,read-undef> = LDRWui %vreg1090, 15; mem:LD4[%tPos171] GPR64:%vreg1089 GPR64common:%vreg1090
     %vreg1089:	[6032r,6168r:0)  0@6032r
        -->	[6072r,6168r:0)  0@6072r
     %vreg1090:	[6016r,6032r:0)  0@6016r
        -->	[6016r,6072r:0)  0@6016r
handleMove 5776B -> 5800B: %vreg1102<def> = LDRWui %vreg1103, 15; mem:LD4[%tPos166] GPR32:%vreg1102 GPR64common:%vreg1103
     %vreg1102:	[5776r,5840r:0)  0@5776r
        -->	[5800r,5840r:0)  0@5800r
     %vreg1103:	[5760r,5776r:0)  0@5760r
        -->	[5760r,5800r:0)  0@5760r
handleMove 5712B -> 5736B: %vreg1104<def> = MOVi32imm 3; GPR32:%vreg1104
     %vreg1104:	[5712r,5744r:0)  0@5712r
        -->	[5736r,5744r:0)  0@5736r
AllocationOrder(GPR32sponly) = [ ]
handleMove 6512B -> 6568B: %vreg1123<def> = ADDXri %vreg1122, <ga:@BZ2_rNums>[TF=34], 0; GPR64common:%vreg1123,%vreg1122
     %vreg1123:	[6512r,6592r:0)  0@6512r
        -->	[6568r,6592r:0)  0@6568r
     %vreg1122:	[6496r,6512r:0)  0@6496r
        -->	[6496r,6568r:0)  0@6496r
handleMove 6496B -> 6552B: %vreg1122<def> = ADRP <ga:@BZ2_rNums>[TF=1]; GPR64common:%vreg1122
     %vreg1122:	[6496r,6568r:0)  0@6496r
        -->	[6552r,6568r:0)  0@6552r
AllocationOrder(GPR32sponly) = [ ]
handleMove 7184B -> 7256B: %vreg1146<def> = LDRWui %vreg1147, 273; mem:LD4[%nblock_used218] GPR32:%vreg1146 GPR64common:%vreg1147
     %vreg1146:	[7184r,7280r:0)  0@7184r
        -->	[7256r,7280r:0)  0@7256r
     %vreg1147:	[7168r,7184r:0)  0@7168r
        -->	[7168r,7256r:0)  0@7168r
handleMove 7168B -> 7208B: %vreg1147<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1147
     %vreg1147:	[7168r,7256r:0)  0@7168r
        -->	[7208r,7256r:0)  0@7208r
handleMove 7024B -> 7048B: %vreg1166<def> = CSELWr %vreg1164, %vreg1165, 0, %NZCV<imp-use>; GPR32:%vreg1166,%vreg1164,%vreg1165
     %vreg1166:	[7024r,7056r:0)  0@7024r
        -->	[7048r,7056r:0)  0@7048r
     %vreg1164:	[6880r,7024r:0)  0@6880r
        -->	[6880r,7048r:0)  0@6880r
     %vreg1165:	[6896r,7024r:0)  0@6896r
        -->	[6896r,7048r:0)  0@6896r
     NZCV:	[1664r,1680r:17)[1872r,1888r:16)[3104r,3120r:15)[3408r,3416r:13)[3632r,3648r:14)[3760r,3776r:12)[4928r,4944r:11)[5232r,5240r:9)[5456r,5472r:10)[5584r,5600r:8)[6752r,6768r:7)[7008r,7024r:5)[7280r,7296r:6)[7408r,7424r:4)[8528r,8544r:3)[8784r,8800r:2)[10000r,10016r:1)[10256r,10272r:0)[11760r,11776r:25)[11968r,11984r:24)[13056r,13072r:23)[13184r,13200r:22)[14208r,14224r:21)[14336r,14352r:20)[15360r,15376r:19)[15488r,15504r:18)  0@10256r 1@10000r 2@8784r 3@8528r 4@7408r 5@7008r 6@7280r 7@6752r 8@5584r 9@5232r 10@5456r 11@4928r 12@3760r 13@3408r 14@3632r 15@3104r 16@1872r 17@1664r 18@15488r 19@15360r 20@14336r 21@14208r 22@13184r 23@13056r 24@11968r 25@11760r
        -->	[1664r,1680r:17)[1872r,1888r:16)[3104r,3120r:15)[3408r,3416r:13)[3632r,3648r:14)[3760r,3776r:12)[4928r,4944r:11)[5232r,5240r:9)[5456r,5472r:10)[5584r,5600r:8)[6752r,6768r:7)[7008r,7048r:5)[7280r,7296r:6)[7408r,7424r:4)[8528r,8544r:3)[8784r,8800r:2)[10000r,10016r:1)[10256r,10272r:0)[11760r,11776r:25)[11968r,11984r:24)[13056r,13072r:23)[13184r,13200r:22)[14208r,14224r:21)[14336r,14352r:20)[15360r,15376r:19)[15488r,15504r:18)  0@10256r 1@10000r 2@8784r 3@8528r 4@7408r 5@7008r 6@7280r 7@6752r 8@5584r 9@5232r 10@5456r 11@4928r 12@3760r 13@3408r 14@3632r 15@3104r 16@1872r 17@1664r 18@15488r 19@15360r 20@14336r 21@14208r 22@13184r 23@13056r 24@11968r 25@11760r
handleMove 6896B -> 6872B: %vreg1165<def> = COPY %WZR; GPR32:%vreg1165
     %vreg1165:	[6896r,7048r:0)  0@6896r
        -->	[6872r,7048r:0)  0@6872r
     WZR:	[1664r,1664d:17)[1872r,1872d:16)[3104r,3104d:15)[3408r,3408d:13)[3632r,3632d:14)[3760r,3760d:12)[4928r,4928d:11)[5232r,5232d:9)[5456r,5456d:10)[5584r,5584d:8)[6752r,6752d:7)[7008r,7008d:5)[7280r,7280d:6)[7408r,7408d:4)[8528r,8528d:3)[8784r,8784d:2)[10000r,10000d:1)[10256r,10256d:0)[11760r,11760d:25)[11968r,11968d:24)[13056r,13056d:23)[13184r,13184d:22)[14208r,14208d:21)[14336r,14336d:20)[15360r,15360d:19)[15488r,15488d:18)  0@10256r 1@10000r 2@8784r 3@8528r 4@7408r 5@7008r 6@7280r 7@6752r 8@5584r 9@5232r 10@5456r 11@4928r 12@3760r 13@3408r 14@3632r 15@3104r 16@1872r 17@1664r 18@15488r 19@15360r 20@14336r 21@14208r 22@13184r 23@13056r 24@11968r 25@11760r
        -->	[1664r,1664d:17)[1872r,1872d:16)[3104r,3104d:15)[3408r,3408d:13)[3632r,3632d:14)[3760r,3760d:12)[4928r,4928d:11)[5232r,5232d:9)[5456r,5456d:10)[5584r,5584d:8)[6752r,6752d:7)[7008r,7008d:5)[7280r,7280d:6)[7408r,7408d:4)[8528r,8528d:3)[8784r,8784d:2)[10000r,10000d:1)[10256r,10256d:0)[11760r,11760d:25)[11968r,11968d:24)[13056r,13056d:23)[13184r,13184d:22)[14208r,14208d:21)[14336r,14336d:20)[15360r,15360d:19)[15488r,15488d:18)  0@10256r 1@10000r 2@8784r 3@8528r 4@7408r 5@7008r 6@7280r 7@6752r 8@5584r 9@5232r 10@5456r 11@4928r 12@3760r 13@3408r 14@3632r 15@3104r 16@1872r 17@1664r 18@15488r 19@15360r 20@14336r 21@14208r 22@13184r 23@13056r 24@11968r 25@11760r
handleMove 7008B -> 7044B: %WZR<def> = SUBSWri %vreg1168, 1, 0, %NZCV<imp-def>; GPR32common:%vreg1168
     WZR:	[1664r,1664d:17)[1872r,1872d:16)[3104r,3104d:15)[3408r,3408d:13)[3632r,3632d:14)[3760r,3760d:12)[4928r,4928d:11)[5232r,5232d:9)[5456r,5456d:10)[5584r,5584d:8)[6752r,6752d:7)[7008r,7008d:5)[7280r,7280d:6)[7408r,7408d:4)[8528r,8528d:3)[8784r,8784d:2)[10000r,10000d:1)[10256r,10256d:0)[11760r,11760d:25)[11968r,11968d:24)[13056r,13056d:23)[13184r,13184d:22)[14208r,14208d:21)[14336r,14336d:20)[15360r,15360d:19)[15488r,15488d:18)  0@10256r 1@10000r 2@8784r 3@8528r 4@7408r 5@7008r 6@7280r 7@6752r 8@5584r 9@5232r 10@5456r 11@4928r 12@3760r 13@3408r 14@3632r 15@3104r 16@1872r 17@1664r 18@15488r 19@15360r 20@14336r 21@14208r 22@13184r 23@13056r 24@11968r 25@11760r
        -->	[1664r,1664d:17)[1872r,1872d:16)[3104r,3104d:15)[3408r,3408d:13)[3632r,3632d:14)[3760r,3760d:12)[4928r,4928d:11)[5232r,5232d:9)[5456r,5456d:10)[5584r,5584d:8)[6752r,6752d:7)[7044r,7044d:5)[7280r,7280d:6)[7408r,7408d:4)[8528r,8528d:3)[8784r,8784d:2)[10000r,10000d:1)[10256r,10256d:0)[11760r,11760d:25)[11968r,11968d:24)[13056r,13056d:23)[13184r,13184d:22)[14208r,14208d:21)[14336r,14336d:20)[15360r,15360d:19)[15488r,15488d:18)  0@10256r 1@10000r 2@8784r 3@8528r 4@7408r 5@7044r 6@7280r 7@6752r 8@5584r 9@5232r 10@5456r 11@4928r 12@3760r 13@3408r 14@3632r 15@3104r 16@1872r 17@1664r 18@15488r 19@15360r 20@14336r 21@14208r 22@13184r 23@13056r 24@11968r 25@11760r
     %vreg1168:	[6992r,7008r:0)  0@6992r
        -->	[6992r,7044r:0)  0@6992r
     NZCV:	[1664r,1680r:17)[1872r,1888r:16)[3104r,3120r:15)[3408r,3416r:13)[3632r,3648r:14)[3760r,3776r:12)[4928r,4944r:11)[5232r,5240r:9)[5456r,5472r:10)[5584r,5600r:8)[6752r,6768r:7)[7008r,7048r:5)[7280r,7296r:6)[7408r,7424r:4)[8528r,8544r:3)[8784r,8800r:2)[10000r,10016r:1)[10256r,10272r:0)[11760r,11776r:25)[11968r,11984r:24)[13056r,13072r:23)[13184r,13200r:22)[14208r,14224r:21)[14336r,14352r:20)[15360r,15376r:19)[15488r,15504r:18)  0@10256r 1@10000r 2@8784r 3@8528r 4@7408r 5@7008r 6@7280r 7@6752r 8@5584r 9@5232r 10@5456r 11@4928r 12@3760r 13@3408r 14@3632r 15@3104r 16@1872r 17@1664r 18@15488r 19@15360r 20@14336r 21@14208r 22@13184r 23@13056r 24@11968r 25@11760r
        -->	[1664r,1680r:17)[1872r,1888r:16)[3104r,3120r:15)[3408r,3416r:13)[3632r,3648r:14)[3760r,3776r:12)[4928r,4944r:11)[5232r,5240r:9)[5456r,5472r:10)[5584r,5600r:8)[6752r,6768r:7)[7044r,7048r:5)[7280r,7296r:6)[7408r,7424r:4)[8528r,8544r:3)[8784r,8800r:2)[10000r,10016r:1)[10256r,10272r:0)[11760r,11776r:25)[11968r,11984r:24)[13056r,13072r:23)[13184r,13200r:22)[14208r,14224r:21)[14336r,14352r:20)[15360r,15376r:19)[15488r,15504r:18)  0@10256r 1@10000r 2@8784r 3@8528r 4@7408r 5@7044r 6@7280r 7@6752r 8@5584r 9@5232r 10@5456r 11@4928r 12@3760r 13@3408r 14@3632r 15@3104r 16@1872r 17@1664r 18@15488r 19@15360r 20@14336r 21@14208r 22@13184r 23@13056r 24@11968r 25@11760r
handleMove 6880B -> 7048B: %vreg1164<def> = MOVi32imm 1; GPR32:%vreg1164
     %vreg1164:	[6880r,7064r:0)  0@6880r
        -->	[7048r,7064r:0)  0@7048r
handleMove 7360B -> 7384B: %vreg1183<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg1183
     %vreg1183:	[7360r,7408r:0)  0@7360r
        -->	[7384r,7408r:0)  0@7384r
AllocationOrder(GPR32sponly) = [ ]
handleMove 8160B -> 8184B: %vreg1193<def> = ORRWrs %vreg1226, %vreg1195, 16; GPR32:%vreg1193,%vreg1226 GPR32common:%vreg1195
     %vreg1193:	[8160r,8192r:0)  0@8160r
        -->	[8184r,8192r:0)  0@8184r
     %vreg1226:	[7920r,8160r:0)  0@7920r
        -->	[7920r,8184r:0)  0@7920r
     %vreg1195:	[8144r,8160r:0)  0@8144r
        -->	[8144r,8184r:0)  0@8144r
handleMove 8144B -> 8180B: %vreg1195<def> = ANDWri %vreg1198, 3; GPR32common:%vreg1195 GPR32:%vreg1198
     %vreg1195:	[8144r,8184r:0)  0@8144r
        -->	[8180r,8184r:0)  0@8180r
     %vreg1198:	[8128r,8144r:0)  0@8128r
        -->	[8128r,8180r:0)  0@8128r
handleMove 8128B -> 8184B: %vreg1198<def> = LSRVWr %vreg1208, %vreg1201; GPR32:%vreg1198,%vreg1208,%vreg1201
     %vreg1198:	[8128r,8192r:0)  0@8128r
        -->	[8184r,8192r:0)  0@8184r
     %vreg1208:	[8064r,8128r:0)  0@8064r
        -->	[8064r,8184r:0)  0@8064r
     %vreg1201:	[8112r,8128r:0)  0@8112r
        -->	[8112r,8184r:0)  0@8112r
handleMove 7920B -> 8104B: %vreg1226<def> = LDRHHui %vreg1231, 0; mem:LD2[%arrayidx241] GPR32:%vreg1226 GPR64common:%vreg1231
     %vreg1226:	[7920r,8200r:0)  0@7920r
        -->	[8104r,8200r:0)  0@8104r
     %vreg1231:	[7904r,7920r:0)  0@7904r
        -->	[7904r,8104r:0)  0@7904r
handleMove 8064B -> 8100B: %vreg1208<def> = LDRBBui %vreg1211, 0; mem:LD1[%arrayidx247] GPR32:%vreg1208 GPR64common:%vreg1211
     %vreg1208:	[8064r,8184r:0)  0@8064r
        -->	[8100r,8184r:0)  0@8100r
     %vreg1211:	[8048r,8064r:0)  0@8048r
        -->	[8048r,8100r:0)  0@8048r
handleMove 8048B -> 8104B: %vreg1211<def> = ADDXrr %vreg1213, %vreg1217; GPR64common:%vreg1211 GPR64:%vreg1213,%vreg1217
     %vreg1211:	[8048r,8112r:0)  0@8048r
        -->	[8104r,8112r:0)  0@8104r
     %vreg1213:	[8032r,8048r:0)  0@8032r
        -->	[8032r,8104r:0)  0@8032r
     %vreg1217:	[8000r,8048r:0)  0@8000r
        -->	[8000r,8104r:0)  0@8000r
handleMove 8000B -> 8088B: %vreg1217<def> = UBFMXri %vreg1216, 0, 31; GPR64:%vreg1217,%vreg1216
     %vreg1217:	[8000r,8104r:0)  0@8000r
        -->	[8088r,8104r:0)  0@8088r
     %vreg1216:	[7968r,8000r:0)  0@7968r
        -->	[7968r,8088r:0)  0@7968r
handleMove 7968B -> 8084B: %vreg1216:sub_32<def,read-undef> = UBFMWri %vreg1221, 1, 31; GPR64:%vreg1216 GPR32:%vreg1221
     %vreg1216:	[7968r,8088r:0)  0@7968r
        -->	[8084r,8088r:0)  0@8084r
     %vreg1221:	[7952r,7968r:0)  0@7952r
        -->	[7952r,8084r:0)  0@7952r
handleMove 8032B -> 8088B: %vreg1213<def> = LDRXui %vreg1214, 396; mem:LD8[%ll4246] GPR64:%vreg1213 GPR64common:%vreg1214
     %vreg1213:	[8032r,8120r:0)  0@8032r
        -->	[8088r,8120r:0)  0@8088r
     %vreg1214:	[8016r,8032r:0)  0@8016r
        -->	[8016r,8088r:0)  0@8016r
handleMove 7904B -> 8024B: %vreg1231<def> = ADDXrr %vreg1233, %vreg1230; GPR64common:%vreg1231 GPR64:%vreg1233,%vreg1230
     %vreg1231:	[7904r,8136r:0)  0@7904r
        -->	[8024r,8136r:0)  0@8024r
     %vreg1233:	[7856r,7904r:0)  0@7856r
        -->	[7856r,8024r:0)  0@7856r
     %vreg1230:	[7888r,7904r:0)  0@7888r
        -->	[7888r,8024r:0)  0@7888r
handleMove 7952B -> 8020B: %vreg1221<def> = LDRWui %vreg1222, 15; mem:LD4[%tPos243] GPR32:%vreg1221 GPR64common:%vreg1222
     %vreg1221:	[7952r,8096r:0)  0@7952r
        -->	[8020r,8096r:0)  0@8020r
     %vreg1222:	[7936r,7952r:0)  0@7936r
        -->	[7936r,8020r:0)  0@7936r
handleMove 7888B -> 7944B: %vreg1230<def> = MADDXrrr %vreg1240, %vreg1229, %XZR; GPR64:%vreg1230,%vreg1240,%vreg1229
     %vreg1230:	[7888r,8024r:0)  0@7888r
        -->	[7944r,8024r:0)  0@7944r
     %vreg1240:	[7808r,7888r:0)  0@7808r
        -->	[7808r,7944r:0)  0@7808r
     %vreg1229:	[7872r,7888r:0)  0@7872r
        -->	[7872r,7944r:0)  0@7872r
     WZR:	[1664r,1664d:17)[1872r,1872d:16)[3104r,3104d:15)[3408r,3408d:13)[3632r,3632d:14)[3760r,3760d:12)[4928r,4928d:11)[5232r,5232d:9)[5456r,5456d:10)[5584r,5584d:8)[6752r,6752d:7)[7056r,7056d:5)[7280r,7280d:6)[7408r,7408d:4)[8528r,8528d:3)[8784r,8784d:2)[10000r,10000d:1)[10256r,10256d:0)[11760r,11760d:25)[11968r,11968d:24)[13056r,13056d:23)[13184r,13184d:22)[14208r,14208d:21)[14336r,14336d:20)[15360r,15360d:19)[15488r,15488d:18)  0@10256r 1@10000r 2@8784r 3@8528r 4@7408r 5@7056r 6@7280r 7@6752r 8@5584r 9@5232r 10@5456r 11@4928r 12@3760r 13@3408r 14@3632r 15@3104r 16@1872r 17@1664r 18@15488r 19@15360r 20@14336r 21@14208r 22@13184r 23@13056r 24@11968r 25@11760r
        -->	[1664r,1664d:17)[1872r,1872d:16)[3104r,3104d:15)[3408r,3408d:13)[3632r,3632d:14)[3760r,3760d:12)[4928r,4928d:11)[5232r,5232d:9)[5456r,5456d:10)[5584r,5584d:8)[6752r,6752d:7)[7056r,7056d:5)[7280r,7280d:6)[7408r,7408d:4)[8528r,8528d:3)[8784r,8784d:2)[10000r,10000d:1)[10256r,10256d:0)[11760r,11760d:25)[11968r,11968d:24)[13056r,13056d:23)[13184r,13184d:22)[14208r,14208d:21)[14336r,14336d:20)[15360r,15360d:19)[15488r,15488d:18)  0@10256r 1@10000r 2@8784r 3@8528r 4@7408r 5@7056r 6@7280r 7@6752r 8@5584r 9@5232r 10@5456r 11@4928r 12@3760r 13@3408r 14@3632r 15@3104r 16@1872r 17@1664r 18@15488r 19@15360r 20@14336r 21@14208r 22@13184r 23@13056r 24@11968r 25@11760r
handleMove 7856B -> 7940B: %vreg1233<def> = LDRXui %vreg1234, 395; mem:LD8[%ll16240] GPR64:%vreg1233 GPR64common:%vreg1234
     %vreg1233:	[7856r,8024r:0)  0@7856r
        -->	[7940r,8024r:0)  0@7940r
     %vreg1234:	[7840r,7856r:0)  0@7840r
        -->	[7840r,7940r:0)  0@7840r
handleMove 7808B -> 7848B: %vreg1240:sub_32<def,read-undef> = LDRWui %vreg1241, 15; mem:LD4[%tPos238] GPR64:%vreg1240 GPR64common:%vreg1241
     %vreg1240:	[7808r,7944r:0)  0@7808r
        -->	[7848r,7944r:0)  0@7848r
     %vreg1241:	[7792r,7808r:0)  0@7792r
        -->	[7792r,7848r:0)  0@7792r
handleMove 7552B -> 7576B: %vreg1253<def> = LDRWui %vreg1254, 15; mem:LD4[%tPos233] GPR32:%vreg1253 GPR64common:%vreg1254
     %vreg1253:	[7552r,7616r:0)  0@7552r
        -->	[7576r,7616r:0)  0@7576r
     %vreg1254:	[7536r,7552r:0)  0@7536r
        -->	[7536r,7576r:0)  0@7536r
AllocationOrder(GPR32sponly) = [ ]
handleMove 8288B -> 8344B: %vreg1271<def> = ADDXri %vreg1270, <ga:@BZ2_rNums>[TF=34], 0; GPR64common:%vreg1271,%vreg1270
     %vreg1271:	[8288r,8368r:0)  0@8288r
        -->	[8344r,8368r:0)  0@8344r
     %vreg1270:	[8272r,8288r:0)  0@8272r
        -->	[8272r,8344r:0)  0@8272r
handleMove 8272B -> 8328B: %vreg1270<def> = ADRP <ga:@BZ2_rNums>[TF=1]; GPR64common:%vreg1270
     %vreg1270:	[8272r,8344r:0)  0@8272r
        -->	[8328r,8344r:0)  0@8328r
AllocationOrder(GPR32sponly) = [ ]
handleMove 9632B -> 9656B: %vreg1293<def> = ORRWrs %vreg1326, %vreg1295, 16; GPR32:%vreg1293,%vreg1326 GPR32common:%vreg1295
     %vreg1293:	[9632r,9664r:0)  0@9632r
        -->	[9656r,9664r:0)  0@9656r
     %vreg1326:	[9392r,9632r:0)  0@9392r
        -->	[9392r,9656r:0)  0@9392r
     %vreg1295:	[9616r,9632r:0)  0@9616r
        -->	[9616r,9656r:0)  0@9616r
handleMove 9616B -> 9652B: %vreg1295<def> = ANDWri %vreg1298, 3; GPR32common:%vreg1295 GPR32:%vreg1298
     %vreg1295:	[9616r,9656r:0)  0@9616r
        -->	[9652r,9656r:0)  0@9652r
     %vreg1298:	[9600r,9616r:0)  0@9600r
        -->	[9600r,9652r:0)  0@9600r
handleMove 9600B -> 9656B: %vreg1298<def> = LSRVWr %vreg1308, %vreg1301; GPR32:%vreg1298,%vreg1308,%vreg1301
     %vreg1298:	[9600r,9664r:0)  0@9600r
        -->	[9656r,9664r:0)  0@9656r
     %vreg1308:	[9536r,9600r:0)  0@9536r
        -->	[9536r,9656r:0)  0@9536r
     %vreg1301:	[9584r,9600r:0)  0@9584r
        -->	[9584r,9656r:0)  0@9584r
handleMove 9392B -> 9576B: %vreg1326<def> = LDRHHui %vreg1331, 0; mem:LD2[%arrayidx296] GPR32:%vreg1326 GPR64common:%vreg1331
     %vreg1326:	[9392r,9672r:0)  0@9392r
        -->	[9576r,9672r:0)  0@9576r
     %vreg1331:	[9376r,9392r:0)  0@9376r
        -->	[9376r,9576r:0)  0@9376r
handleMove 9536B -> 9572B: %vreg1308<def> = LDRBBui %vreg1311, 0; mem:LD1[%arrayidx302] GPR32:%vreg1308 GPR64common:%vreg1311
     %vreg1308:	[9536r,9656r:0)  0@9536r
        -->	[9572r,9656r:0)  0@9572r
     %vreg1311:	[9520r,9536r:0)  0@9520r
        -->	[9520r,9572r:0)  0@9520r
handleMove 9520B -> 9576B: %vreg1311<def> = ADDXrr %vreg1313, %vreg1317; GPR64common:%vreg1311 GPR64:%vreg1313,%vreg1317
     %vreg1311:	[9520r,9584r:0)  0@9520r
        -->	[9576r,9584r:0)  0@9576r
     %vreg1313:	[9504r,9520r:0)  0@9504r
        -->	[9504r,9576r:0)  0@9504r
     %vreg1317:	[9472r,9520r:0)  0@9472r
        -->	[9472r,9576r:0)  0@9472r
handleMove 9472B -> 9560B: %vreg1317<def> = UBFMXri %vreg1316, 0, 31; GPR64:%vreg1317,%vreg1316
     %vreg1317:	[9472r,9576r:0)  0@9472r
        -->	[9560r,9576r:0)  0@9560r
     %vreg1316:	[9440r,9472r:0)  0@9440r
        -->	[9440r,9560r:0)  0@9440r
handleMove 9440B -> 9556B: %vreg1316:sub_32<def,read-undef> = UBFMWri %vreg1321, 1, 31; GPR64:%vreg1316 GPR32:%vreg1321
     %vreg1316:	[9440r,9560r:0)  0@9440r
        -->	[9556r,9560r:0)  0@9556r
     %vreg1321:	[9424r,9440r:0)  0@9424r
        -->	[9424r,9556r:0)  0@9424r
handleMove 9504B -> 9560B: %vreg1313<def> = LDRXui %vreg1314, 396; mem:LD8[%ll4301] GPR64:%vreg1313 GPR64common:%vreg1314
     %vreg1313:	[9504r,9592r:0)  0@9504r
        -->	[9560r,9592r:0)  0@9560r
     %vreg1314:	[9488r,9504r:0)  0@9488r
        -->	[9488r,9560r:0)  0@9488r
handleMove 9376B -> 9496B: %vreg1331<def> = ADDXrr %vreg1333, %vreg1330; GPR64common:%vreg1331 GPR64:%vreg1333,%vreg1330
     %vreg1331:	[9376r,9608r:0)  0@9376r
        -->	[9496r,9608r:0)  0@9496r
     %vreg1333:	[9328r,9376r:0)  0@9328r
        -->	[9328r,9496r:0)  0@9328r
     %vreg1330:	[9360r,9376r:0)  0@9360r
        -->	[9360r,9496r:0)  0@9360r
handleMove 9424B -> 9492B: %vreg1321<def> = LDRWui %vreg1322, 15; mem:LD4[%tPos298] GPR32:%vreg1321 GPR64common:%vreg1322
     %vreg1321:	[9424r,9568r:0)  0@9424r
        -->	[9492r,9568r:0)  0@9492r
     %vreg1322:	[9408r,9424r:0)  0@9408r
        -->	[9408r,9492r:0)  0@9408r
handleMove 9360B -> 9416B: %vreg1330<def> = MADDXrrr %vreg1340, %vreg1329, %XZR; GPR64:%vreg1330,%vreg1340,%vreg1329
     %vreg1330:	[9360r,9496r:0)  0@9360r
        -->	[9416r,9496r:0)  0@9416r
     %vreg1340:	[9280r,9360r:0)  0@9280r
        -->	[9280r,9416r:0)  0@9280r
     %vreg1329:	[9344r,9360r:0)  0@9344r
        -->	[9344r,9416r:0)  0@9344r
     WZR:	[1664r,1664d:17)[1872r,1872d:16)[3104r,3104d:15)[3408r,3408d:13)[3632r,3632d:14)[3760r,3760d:12)[4928r,4928d:11)[5232r,5232d:9)[5456r,5456d:10)[5584r,5584d:8)[6752r,6752d:7)[7056r,7056d:5)[7280r,7280d:6)[7408r,7408d:4)[8528r,8528d:3)[8784r,8784d:2)[10000r,10000d:1)[10256r,10256d:0)[11760r,11760d:25)[11968r,11968d:24)[13056r,13056d:23)[13184r,13184d:22)[14208r,14208d:21)[14336r,14336d:20)[15360r,15360d:19)[15488r,15488d:18)  0@10256r 1@10000r 2@8784r 3@8528r 4@7408r 5@7056r 6@7280r 7@6752r 8@5584r 9@5232r 10@5456r 11@4928r 12@3760r 13@3408r 14@3632r 15@3104r 16@1872r 17@1664r 18@15488r 19@15360r 20@14336r 21@14208r 22@13184r 23@13056r 24@11968r 25@11760r
        -->	[1664r,1664d:17)[1872r,1872d:16)[3104r,3104d:15)[3408r,3408d:13)[3632r,3632d:14)[3760r,3760d:12)[4928r,4928d:11)[5232r,5232d:9)[5456r,5456d:10)[5584r,5584d:8)[6752r,6752d:7)[7056r,7056d:5)[7280r,7280d:6)[7408r,7408d:4)[8528r,8528d:3)[8784r,8784d:2)[10000r,10000d:1)[10256r,10256d:0)[11760r,11760d:25)[11968r,11968d:24)[13056r,13056d:23)[13184r,13184d:22)[14208r,14208d:21)[14336r,14336d:20)[15360r,15360d:19)[15488r,15488d:18)  0@10256r 1@10000r 2@8784r 3@8528r 4@7408r 5@7056r 6@7280r 7@6752r 8@5584r 9@5232r 10@5456r 11@4928r 12@3760r 13@3408r 14@3632r 15@3104r 16@1872r 17@1664r 18@15488r 19@15360r 20@14336r 21@14208r 22@13184r 23@13056r 24@11968r 25@11760r
handleMove 9328B -> 9412B: %vreg1333<def> = LDRXui %vreg1334, 395; mem:LD8[%ll16295] GPR64:%vreg1333 GPR64common:%vreg1334
     %vreg1333:	[9328r,9496r:0)  0@9328r
        -->	[9412r,9496r:0)  0@9412r
     %vreg1334:	[9312r,9328r:0)  0@9312r
        -->	[9312r,9412r:0)  0@9312r
handleMove 9280B -> 9320B: %vreg1340:sub_32<def,read-undef> = LDRWui %vreg1341, 15; mem:LD4[%tPos293] GPR64:%vreg1340 GPR64common:%vreg1341
     %vreg1340:	[9280r,9416r:0)  0@9280r
        -->	[9320r,9416r:0)  0@9320r
     %vreg1341:	[9264r,9280r:0)  0@9264r
        -->	[9264r,9320r:0)  0@9264r
AllocationOrder(GPR32sponly) = [ ]
handleMove 9024B -> 9048B: %vreg1353<def> = LDRWui %vreg1354, 15; mem:LD4[%tPos288] GPR32:%vreg1353 GPR64common:%vreg1354
     %vreg1353:	[9024r,9088r:0)  0@9024r
        -->	[9048r,9088r:0)  0@9048r
     %vreg1354:	[9008r,9024r:0)  0@9008r
        -->	[9008r,9048r:0)  0@9008r
handleMove 8960B -> 8984B: %vreg1359<def> = ADDWri %vreg1362, 4, 0; GPR32common:%vreg1359,%vreg1362
     %vreg1359:	[8960r,8992r:0)  0@8960r
        -->	[8984r,8992r:0)  0@8984r
     %vreg1362:	[8944r,8960r:0)  0@8944r
        -->	[8944r,8984r:0)  0@8944r
handleMove 8800B -> 8824B: %vreg1381<def> = CSELWr %vreg1379, %vreg1380, 0, %NZCV<imp-use>; GPR32:%vreg1381,%vreg1379,%vreg1380
     %vreg1381:	[8800r,8832r:0)  0@8800r
        -->	[8824r,8832r:0)  0@8824r
     %vreg1379:	[8656r,8800r:0)  0@8656r
        -->	[8656r,8824r:0)  0@8656r
     %vreg1380:	[8672r,8800r:0)  0@8672r
        -->	[8672r,8824r:0)  0@8672r
     NZCV:	[1664r,1680r:17)[1872r,1888r:16)[3104r,3120r:15)[3408r,3416r:13)[3632r,3648r:14)[3760r,3776r:12)[4928r,4944r:11)[5232r,5240r:9)[5456r,5472r:10)[5584r,5600r:8)[6752r,6768r:7)[7056r,7064r:5)[7280r,7296r:6)[7408r,7424r:4)[8528r,8544r:3)[8784r,8800r:2)[10000r,10016r:1)[10256r,10272r:0)[11760r,11776r:25)[11968r,11984r:24)[13056r,13072r:23)[13184r,13200r:22)[14208r,14224r:21)[14336r,14352r:20)[15360r,15376r:19)[15488r,15504r:18)  0@10256r 1@10000r 2@8784r 3@8528r 4@7408r 5@7056r 6@7280r 7@6752r 8@5584r 9@5232r 10@5456r 11@4928r 12@3760r 13@3408r 14@3632r 15@3104r 16@1872r 17@1664r 18@15488r 19@15360r 20@14336r 21@14208r 22@13184r 23@13056r 24@11968r 25@11760r
        -->	[1664r,1680r:17)[1872r,1888r:16)[3104r,3120r:15)[3408r,3416r:13)[3632r,3648r:14)[3760r,3776r:12)[4928r,4944r:11)[5232r,5240r:9)[5456r,5472r:10)[5584r,5600r:8)[6752r,6768r:7)[7056r,7064r:5)[7280r,7296r:6)[7408r,7424r:4)[8528r,8544r:3)[8784r,8824r:2)[10000r,10016r:1)[10256r,10272r:0)[11760r,11776r:25)[11968r,11984r:24)[13056r,13072r:23)[13184r,13200r:22)[14208r,14224r:21)[14336r,14352r:20)[15360r,15376r:19)[15488r,15504r:18)  0@10256r 1@10000r 2@8784r 3@8528r 4@7408r 5@7056r 6@7280r 7@6752r 8@5584r 9@5232r 10@5456r 11@4928r 12@3760r 13@3408r 14@3632r 15@3104r 16@1872r 17@1664r 18@15488r 19@15360r 20@14336r 21@14208r 22@13184r 23@13056r 24@11968r 25@11760r
handleMove 8672B -> 8648B: %vreg1380<def> = COPY %WZR; GPR32:%vreg1380
     %vreg1380:	[8672r,8824r:0)  0@8672r
        -->	[8648r,8824r:0)  0@8648r
     WZR:	[1664r,1664d:17)[1872r,1872d:16)[3104r,3104d:15)[3408r,3408d:13)[3632r,3632d:14)[3760r,3760d:12)[4928r,4928d:11)[5232r,5232d:9)[5456r,5456d:10)[5584r,5584d:8)[6752r,6752d:7)[7056r,7056d:5)[7280r,7280d:6)[7408r,7408d:4)[8528r,8528d:3)[8784r,8784d:2)[10000r,10000d:1)[10256r,10256d:0)[11760r,11760d:25)[11968r,11968d:24)[13056r,13056d:23)[13184r,13184d:22)[14208r,14208d:21)[14336r,14336d:20)[15360r,15360d:19)[15488r,15488d:18)  0@10256r 1@10000r 2@8784r 3@8528r 4@7408r 5@7056r 6@7280r 7@6752r 8@5584r 9@5232r 10@5456r 11@4928r 12@3760r 13@3408r 14@3632r 15@3104r 16@1872r 17@1664r 18@15488r 19@15360r 20@14336r 21@14208r 22@13184r 23@13056r 24@11968r 25@11760r
        -->	[1664r,1664d:17)[1872r,1872d:16)[3104r,3104d:15)[3408r,3408d:13)[3632r,3632d:14)[3760r,3760d:12)[4928r,4928d:11)[5232r,5232d:9)[5456r,5456d:10)[5584r,5584d:8)[6752r,6752d:7)[7056r,7056d:5)[7280r,7280d:6)[7408r,7408d:4)[8528r,8528d:3)[8784r,8784d:2)[10000r,10000d:1)[10256r,10256d:0)[11760r,11760d:25)[11968r,11968d:24)[13056r,13056d:23)[13184r,13184d:22)[14208r,14208d:21)[14336r,14336d:20)[15360r,15360d:19)[15488r,15488d:18)  0@10256r 1@10000r 2@8784r 3@8528r 4@7408r 5@7056r 6@7280r 7@6752r 8@5584r 9@5232r 10@5456r 11@4928r 12@3760r 13@3408r 14@3632r 15@3104r 16@1872r 17@1664r 18@15488r 19@15360r 20@14336r 21@14208r 22@13184r 23@13056r 24@11968r 25@11760r
handleMove 8784B -> 8820B: %WZR<def> = SUBSWri %vreg1383, 1, 0, %NZCV<imp-def>; GPR32common:%vreg1383
     WZR:	[1664r,1664d:17)[1872r,1872d:16)[3104r,3104d:15)[3408r,3408d:13)[3632r,3632d:14)[3760r,3760d:12)[4928r,4928d:11)[5232r,5232d:9)[5456r,5456d:10)[5584r,5584d:8)[6752r,6752d:7)[7056r,7056d:5)[7280r,7280d:6)[7408r,7408d:4)[8528r,8528d:3)[8784r,8784d:2)[10000r,10000d:1)[10256r,10256d:0)[11760r,11760d:25)[11968r,11968d:24)[13056r,13056d:23)[13184r,13184d:22)[14208r,14208d:21)[14336r,14336d:20)[15360r,15360d:19)[15488r,15488d:18)  0@10256r 1@10000r 2@8784r 3@8528r 4@7408r 5@7056r 6@7280r 7@6752r 8@5584r 9@5232r 10@5456r 11@4928r 12@3760r 13@3408r 14@3632r 15@3104r 16@1872r 17@1664r 18@15488r 19@15360r 20@14336r 21@14208r 22@13184r 23@13056r 24@11968r 25@11760r
        -->	[1664r,1664d:17)[1872r,1872d:16)[3104r,3104d:15)[3408r,3408d:13)[3632r,3632d:14)[3760r,3760d:12)[4928r,4928d:11)[5232r,5232d:9)[5456r,5456d:10)[5584r,5584d:8)[6752r,6752d:7)[7056r,7056d:5)[7280r,7280d:6)[7408r,7408d:4)[8528r,8528d:3)[8820r,8820d:2)[10000r,10000d:1)[10256r,10256d:0)[11760r,11760d:25)[11968r,11968d:24)[13056r,13056d:23)[13184r,13184d:22)[14208r,14208d:21)[14336r,14336d:20)[15360r,15360d:19)[15488r,15488d:18)  0@10256r 1@10000r 2@8820r 3@8528r 4@7408r 5@7056r 6@7280r 7@6752r 8@5584r 9@5232r 10@5456r 11@4928r 12@3760r 13@3408r 14@3632r 15@3104r 16@1872r 17@1664r 18@15488r 19@15360r 20@14336r 21@14208r 22@13184r 23@13056r 24@11968r 25@11760r
     %vreg1383:	[8768r,8784r:0)  0@8768r
        -->	[8768r,8820r:0)  0@8768r
     NZCV:	[1664r,1680r:17)[1872r,1888r:16)[3104r,3120r:15)[3408r,3416r:13)[3632r,3648r:14)[3760r,3776r:12)[4928r,4944r:11)[5232r,5240r:9)[5456r,5472r:10)[5584r,5600r:8)[6752r,6768r:7)[7056r,7064r:5)[7280r,7296r:6)[7408r,7424r:4)[8528r,8544r:3)[8784r,8824r:2)[10000r,10016r:1)[10256r,10272r:0)[11760r,11776r:25)[11968r,11984r:24)[13056r,13072r:23)[13184r,13200r:22)[14208r,14224r:21)[14336r,14352r:20)[15360r,15376r:19)[15488r,15504r:18)  0@10256r 1@10000r 2@8784r 3@8528r 4@7408r 5@7056r 6@7280r 7@6752r 8@5584r 9@5232r 10@5456r 11@4928r 12@3760r 13@3408r 14@3632r 15@3104r 16@1872r 17@1664r 18@15488r 19@15360r 20@14336r 21@14208r 22@13184r 23@13056r 24@11968r 25@11760r
        -->	[1664r,1680r:17)[1872r,1888r:16)[3104r,3120r:15)[3408r,3416r:13)[3632r,3648r:14)[3760r,3776r:12)[4928r,4944r:11)[5232r,5240r:9)[5456r,5472r:10)[5584r,5600r:8)[6752r,6768r:7)[7056r,7064r:5)[7280r,7296r:6)[7408r,7424r:4)[8528r,8544r:3)[8820r,8824r:2)[10000r,10016r:1)[10256r,10272r:0)[11760r,11776r:25)[11968r,11984r:24)[13056r,13072r:23)[13184r,13200r:22)[14208r,14224r:21)[14336r,14352r:20)[15360r,15376r:19)[15488r,15504r:18)  0@10256r 1@10000r 2@8820r 3@8528r 4@7408r 5@7056r 6@7280r 7@6752r 8@5584r 9@5232r 10@5456r 11@4928r 12@3760r 13@3408r 14@3632r 15@3104r 16@1872r 17@1664r 18@15488r 19@15360r 20@14336r 21@14208r 22@13184r 23@13056r 24@11968r 25@11760r
handleMove 8656B -> 8824B: %vreg1379<def> = MOVi32imm 1; GPR32:%vreg1379
     %vreg1379:	[8656r,8840r:0)  0@8656r
        -->	[8824r,8840r:0)  0@8824r
AllocationOrder(GPR32sponly) = [ ]
handleMove 9760B -> 9816B: %vreg1407<def> = ADDXri %vreg1406, <ga:@BZ2_rNums>[TF=34], 0; GPR64common:%vreg1407,%vreg1406
     %vreg1407:	[9760r,9840r:0)  0@9760r
        -->	[9816r,9840r:0)  0@9816r
     %vreg1406:	[9744r,9760r:0)  0@9744r
        -->	[9744r,9816r:0)  0@9744r
handleMove 9744B -> 9800B: %vreg1406<def> = ADRP <ga:@BZ2_rNums>[TF=1]; GPR64common:%vreg1406
     %vreg1406:	[9744r,9816r:0)  0@9744r
        -->	[9800r,9816r:0)  0@9800r
AllocationOrder(GPR32sponly) = [ ]
handleMove 10272B -> 10312B: %vreg1436<def> = CSELWr %vreg1434, %vreg1435, 0, %NZCV<imp-use>; GPR32:%vreg1436,%vreg1434,%vreg1435
     %vreg1436:	[10272r,10320r:0)  0@10272r
        -->	[10312r,10320r:0)  0@10312r
     %vreg1434:	[10128r,10272r:0)  0@10128r
        -->	[10128r,10312r:0)  0@10128r
     %vreg1435:	[10144r,10272r:0)  0@10144r
        -->	[10144r,10312r:0)  0@10144r
     NZCV:	[1664r,1680r:17)[1872r,1888r:16)[3104r,3120r:15)[3408r,3416r:13)[3632r,3648r:14)[3760r,3776r:12)[4928r,4944r:11)[5232r,5240r:9)[5456r,5472r:10)[5584r,5600r:8)[6752r,6768r:7)[7056r,7064r:5)[7280r,7296r:6)[7408r,7424r:4)[8528r,8544r:3)[8832r,8840r:2)[10000r,10016r:1)[10256r,10272r:0)[11760r,11776r:25)[11968r,11984r:24)[13056r,13072r:23)[13184r,13200r:22)[14208r,14224r:21)[14336r,14352r:20)[15360r,15376r:19)[15488r,15504r:18)  0@10256r 1@10000r 2@8832r 3@8528r 4@7408r 5@7056r 6@7280r 7@6752r 8@5584r 9@5232r 10@5456r 11@4928r 12@3760r 13@3408r 14@3632r 15@3104r 16@1872r 17@1664r 18@15488r 19@15360r 20@14336r 21@14208r 22@13184r 23@13056r 24@11968r 25@11760r
        -->	[1664r,1680r:17)[1872r,1888r:16)[3104r,3120r:15)[3408r,3416r:13)[3632r,3648r:14)[3760r,3776r:12)[4928r,4944r:11)[5232r,5240r:9)[5456r,5472r:10)[5584r,5600r:8)[6752r,6768r:7)[7056r,7064r:5)[7280r,7296r:6)[7408r,7424r:4)[8528r,8544r:3)[8832r,8840r:2)[10000r,10016r:1)[10256r,10312r:0)[11760r,11776r:25)[11968r,11984r:24)[13056r,13072r:23)[13184r,13200r:22)[14208r,14224r:21)[14336r,14352r:20)[15360r,15376r:19)[15488r,15504r:18)  0@10256r 1@10000r 2@8832r 3@8528r 4@7408r 5@7056r 6@7280r 7@6752r 8@5584r 9@5232r 10@5456r 11@4928r 12@3760r 13@3408r 14@3632r 15@3104r 16@1872r 17@1664r 18@15488r 19@15360r 20@14336r 21@14208r 22@13184r 23@13056r 24@11968r 25@11760r
handleMove 10144B -> 10120B: %vreg1435<def> = COPY %WZR; GPR32:%vreg1435
     %vreg1435:	[10144r,10312r:0)  0@10144r
        -->	[10120r,10312r:0)  0@10120r
     WZR:	[1664r,1664d:17)[1872r,1872d:16)[3104r,3104d:15)[3408r,3408d:13)[3632r,3632d:14)[3760r,3760d:12)[4928r,4928d:11)[5232r,5232d:9)[5456r,5456d:10)[5584r,5584d:8)[6752r,6752d:7)[7056r,7056d:5)[7280r,7280d:6)[7408r,7408d:4)[8528r,8528d:3)[8832r,8832d:2)[10000r,10000d:1)[10256r,10256d:0)[11760r,11760d:25)[11968r,11968d:24)[13056r,13056d:23)[13184r,13184d:22)[14208r,14208d:21)[14336r,14336d:20)[15360r,15360d:19)[15488r,15488d:18)  0@10256r 1@10000r 2@8832r 3@8528r 4@7408r 5@7056r 6@7280r 7@6752r 8@5584r 9@5232r 10@5456r 11@4928r 12@3760r 13@3408r 14@3632r 15@3104r 16@1872r 17@1664r 18@15488r 19@15360r 20@14336r 21@14208r 22@13184r 23@13056r 24@11968r 25@11760r
        -->	[1664r,1664d:17)[1872r,1872d:16)[3104r,3104d:15)[3408r,3408d:13)[3632r,3632d:14)[3760r,3760d:12)[4928r,4928d:11)[5232r,5232d:9)[5456r,5456d:10)[5584r,5584d:8)[6752r,6752d:7)[7056r,7056d:5)[7280r,7280d:6)[7408r,7408d:4)[8528r,8528d:3)[8832r,8832d:2)[10000r,10000d:1)[10256r,10256d:0)[11760r,11760d:25)[11968r,11968d:24)[13056r,13056d:23)[13184r,13184d:22)[14208r,14208d:21)[14336r,14336d:20)[15360r,15360d:19)[15488r,15488d:18)  0@10256r 1@10000r 2@8832r 3@8528r 4@7408r 5@7056r 6@7280r 7@6752r 8@5584r 9@5232r 10@5456r 11@4928r 12@3760r 13@3408r 14@3632r 15@3104r 16@1872r 17@1664r 18@15488r 19@15360r 20@14336r 21@14208r 22@13184r 23@13056r 24@11968r 25@11760r
handleMove 10128B -> 10308B: %vreg1434<def> = MOVi32imm 1; GPR32:%vreg1434
     %vreg1434:	[10128r,10312r:0)  0@10128r
        -->	[10308r,10312r:0)  0@10308r
handleMove 10256B -> 10312B: %WZR<def> = SUBSWri %vreg1438, 1, 0, %NZCV<imp-def>; GPR32common:%vreg1438
     WZR:	[1664r,1664d:17)[1872r,1872d:16)[3104r,3104d:15)[3408r,3408d:13)[3632r,3632d:14)[3760r,3760d:12)[4928r,4928d:11)[5232r,5232d:9)[5456r,5456d:10)[5584r,5584d:8)[6752r,6752d:7)[7056r,7056d:5)[7280r,7280d:6)[7408r,7408d:4)[8528r,8528d:3)[8832r,8832d:2)[10000r,10000d:1)[10256r,10256d:0)[11760r,11760d:25)[11968r,11968d:24)[13056r,13056d:23)[13184r,13184d:22)[14208r,14208d:21)[14336r,14336d:20)[15360r,15360d:19)[15488r,15488d:18)  0@10256r 1@10000r 2@8832r 3@8528r 4@7408r 5@7056r 6@7280r 7@6752r 8@5584r 9@5232r 10@5456r 11@4928r 12@3760r 13@3408r 14@3632r 15@3104r 16@1872r 17@1664r 18@15488r 19@15360r 20@14336r 21@14208r 22@13184r 23@13056r 24@11968r 25@11760r
        -->	[1664r,1664d:17)[1872r,1872d:16)[3104r,3104d:15)[3408r,3408d:13)[3632r,3632d:14)[3760r,3760d:12)[4928r,4928d:11)[5232r,5232d:9)[5456r,5456d:10)[5584r,5584d:8)[6752r,6752d:7)[7056r,7056d:5)[7280r,7280d:6)[7408r,7408d:4)[8528r,8528d:3)[8832r,8832d:2)[10000r,10000d:1)[10312r,10312d:0)[11760r,11760d:25)[11968r,11968d:24)[13056r,13056d:23)[13184r,13184d:22)[14208r,14208d:21)[14336r,14336d:20)[15360r,15360d:19)[15488r,15488d:18)  0@10312r 1@10000r 2@8832r 3@8528r 4@7408r 5@7056r 6@7280r 7@6752r 8@5584r 9@5232r 10@5456r 11@4928r 12@3760r 13@3408r 14@3632r 15@3104r 16@1872r 17@1664r 18@15488r 19@15360r 20@14336r 21@14208r 22@13184r 23@13056r 24@11968r 25@11760r
     %vreg1438:	[10240r,10256r:0)  0@10240r
        -->	[10240r,10312r:0)  0@10240r
     NZCV:	[1664r,1680r:17)[1872r,1888r:16)[3104r,3120r:15)[3408r,3416r:13)[3632r,3648r:14)[3760r,3776r:12)[4928r,4944r:11)[5232r,5240r:9)[5456r,5472r:10)[5584r,5600r:8)[6752r,6768r:7)[7056r,7064r:5)[7280r,7296r:6)[7408r,7424r:4)[8528r,8544r:3)[8832r,8840r:2)[10000r,10016r:1)[10256r,10328r:0)[11760r,11776r:25)[11968r,11984r:24)[13056r,13072r:23)[13184r,13200r:22)[14208r,14224r:21)[14336r,14352r:20)[15360r,15376r:19)[15488r,15504r:18)  0@10256r 1@10000r 2@8832r 3@8528r 4@7408r 5@7056r 6@7280r 7@6752r 8@5584r 9@5232r 10@5456r 11@4928r 12@3760r 13@3408r 14@3632r 15@3104r 16@1872r 17@1664r 18@15488r 19@15360r 20@14336r 21@14208r 22@13184r 23@13056r 24@11968r 25@11760r
        -->	[1664r,1680r:17)[1872r,1888r:16)[3104r,3120r:15)[3408r,3416r:13)[3632r,3648r:14)[3760r,3776r:12)[4928r,4944r:11)[5232r,5240r:9)[5456r,5472r:10)[5584r,5600r:8)[6752r,6768r:7)[7056r,7064r:5)[7280r,7296r:6)[7408r,7424r:4)[8528r,8544r:3)[8832r,8840r:2)[10000r,10016r:1)[10312r,10328r:0)[11760r,11776r:25)[11968r,11984r:24)[13056r,13072r:23)[13184r,13200r:22)[14208r,14224r:21)[14336r,14352r:20)[15360r,15376r:19)[15488r,15504r:18)  0@10312r 1@10000r 2@8832r 3@8528r 4@7408r 5@7056r 6@7280r 7@6752r 8@5584r 9@5232r 10@5456r 11@4928r 12@3760r 13@3408r 14@3632r 15@3104r 16@1872r 17@1664r 18@15488r 19@15360r 20@14336r 21@14208r 22@13184r 23@13056r 24@11968r 25@11760r
handleMove 10240B -> 10296B: %vreg1438<def> = LDRWui %vreg1439, 6; mem:LD4[%rNToGo331] GPR32common:%vreg1438 GPR64common:%vreg1439
     %vreg1438:	[10240r,10312r:0)  0@10240r
        -->	[10296r,10312r:0)  0@10296r
     %vreg1439:	[10224r,10240r:0)  0@10224r
        -->	[10224r,10296r:0)  0@10224r
AllocationOrder(GPR32sponly) = [ ]
handleMove 11088B -> 11112B: %vreg63<def> = EORWrs %vreg65, %vreg89, 8; GPR32:%vreg63,%vreg65,%vreg89
     %vreg63:	[11088r,11120r:0)  0@11088r
        -->	[11112r,11120r:0)  0@11112r
     %vreg65:	[11072r,11088r:0)  0@11072r
        -->	[11072r,11112r:0)  0@11072r
     %vreg89:	[10880r,11088r:0)  0@10880r
        -->	[10880r,11112r:0)  0@10880r
handleMove 10928B -> 10968B: %vreg84<def> = UBFMWri %vreg86, 24, 31; GPR32:%vreg84,%vreg86
     %vreg84:	[10928r,10976r:0)  0@10928r
        -->	[10968r,10976r:0)  0@10968r
     %vreg86:	[10912r,10928r:0)  0@10912r
        -->	[10912r,10968r:0)  0@10912r
handleMove 10880B -> 10964B: %vreg89<def> = LDRWui %vreg90, 796; mem:LD4[%calculatedBlockCRC356] GPR32:%vreg89 GPR64common:%vreg90
     %vreg89:	[10880r,11112r:0)  0@10880r
        -->	[10964r,11112r:0)  0@10964r
     %vreg90:	[10864r,10880r:0)  0@10864r
        -->	[10864r,10964r:0)  0@10864r
handleMove 10752B -> 10968B: %vreg67<def> = ADDXri %vreg66, <ga:@BZ2_crc32Table>[TF=34], 0; GPR64common:%vreg67,%vreg66
     %vreg67:	[10752r,11056r:0)  0@10752r
        -->	[10968r,11056r:0)  0@10968r
     %vreg66:	[10736r,10752r:0)  0@10736r
        -->	[10736r,10968r:0)  0@10736r
handleMove 10912B -> 10952B: %vreg86<def> = LDRWui %vreg87, 796; mem:LD4[%calculatedBlockCRC358] GPR32:%vreg86 GPR64common:%vreg87
     %vreg86:	[10912r,10984r:0)  0@10912r
        -->	[10952r,10984r:0)  0@10952r
     %vreg87:	[10896r,10912r:0)  0@10896r
        -->	[10896r,10952r:0)  0@10896r
handleMove 10864B -> 10948B: %vreg90<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg90
     %vreg90:	[10864r,10976r:0)  0@10864r
        -->	[10948r,10976r:0)  0@10948r
handleMove 10736B -> 10952B: %vreg66<def> = ADRP <ga:@BZ2_crc32Table>[TF=1]; GPR64common:%vreg66
     %vreg66:	[10736r,10984r:0)  0@10736r
        -->	[10952r,10984r:0)  0@10952r
handleMove 10784B -> 10824B: %vreg99<def> = LDRBBui %vreg100, 12; mem:LD1[%state_out_ch353] GPR32:%vreg99 GPR64common:%vreg100
     %vreg99:	[10784r,10848r:0)  0@10784r
        -->	[10824r,10848r:0)  0@10824r
     %vreg100:	[10768r,10784r:0)  0@10768r
        -->	[10768r,10824r:0)  0@10768r
handleMove 10768B -> 10808B: %vreg100<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg100
     %vreg100:	[10768r,10824r:0)  0@10768r
        -->	[10808r,10824r:0)  0@10808r
handleMove 11664B -> 11736B: %vreg119<def> = LDRWui %vreg120, 273; mem:LD4[%nblock_used388] GPR32:%vreg119 GPR64common:%vreg120
     %vreg119:	[11664r,11760r:0)  0@11664r
        -->	[11736r,11760r:0)  0@11736r
     %vreg120:	[11648r,11664r:0)  0@11648r
        -->	[11648r,11736r:0)  0@11648r
handleMove 11648B -> 11688B: %vreg120<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg120
     %vreg120:	[11648r,11736r:0)  0@11648r
        -->	[11688r,11736r:0)  0@11688r
handleMove 11872B -> 11944B: %vreg131<def> = LDRWui %vreg132, 273; mem:LD4[%nblock_used395] GPR32:%vreg131 GPR64common:%vreg132
     %vreg131:	[11872r,11968r:0)  0@11872r
        -->	[11944r,11968r:0)  0@11944r
     %vreg132:	[11856r,11872r:0)  0@11856r
        -->	[11856r,11944r:0)  0@11856r
handleMove 11856B -> 11896B: %vreg132<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg132
     %vreg132:	[11856r,11944r:0)  0@11856r
        -->	[11896r,11944r:0)  0@11896r
AllocationOrder(GPR32sponly) = [ ]
handleMove 12960B -> 13032B: %vreg143<def> = LDRWui %vreg144, 273; mem:LD4[%nblock_used432] GPR32:%vreg143 GPR64common:%vreg144
     %vreg143:	[12960r,13056r:0)  0@12960r
        -->	[13032r,13056r:0)  0@13032r
     %vreg144:	[12944r,12960r:0)  0@12944r
        -->	[12944r,13032r:0)  0@12944r
handleMove 12944B -> 12984B: %vreg144<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg144
     %vreg144:	[12944r,13032r:0)  0@12944r
        -->	[12984r,13032r:0)  0@12984r
handleMove 12832B -> 12856B: %vreg156<def> = ORRWrs %vreg189, %vreg158, 16; GPR32:%vreg156,%vreg189 GPR32common:%vreg158
     %vreg156:	[12832r,12864r:0)  0@12832r
        -->	[12856r,12864r:0)  0@12856r
     %vreg189:	[12592r,12832r:0)  0@12592r
        -->	[12592r,12856r:0)  0@12592r
     %vreg158:	[12816r,12832r:0)  0@12816r
        -->	[12816r,12856r:0)  0@12816r
handleMove 12816B -> 12852B: %vreg158<def> = ANDWri %vreg161, 3; GPR32common:%vreg158 GPR32:%vreg161
     %vreg158:	[12816r,12856r:0)  0@12816r
        -->	[12852r,12856r:0)  0@12852r
     %vreg161:	[12800r,12816r:0)  0@12800r
        -->	[12800r,12852r:0)  0@12800r
handleMove 12800B -> 12856B: %vreg161<def> = LSRVWr %vreg171, %vreg164; GPR32:%vreg161,%vreg171,%vreg164
     %vreg161:	[12800r,12864r:0)  0@12800r
        -->	[12856r,12864r:0)  0@12856r
     %vreg171:	[12736r,12800r:0)  0@12736r
        -->	[12736r,12856r:0)  0@12736r
     %vreg164:	[12784r,12800r:0)  0@12784r
        -->	[12784r,12856r:0)  0@12784r
handleMove 12592B -> 12776B: %vreg189<def> = LDRHHui %vreg194, 0; mem:LD2[%arrayidx414] GPR32:%vreg189 GPR64common:%vreg194
     %vreg189:	[12592r,12872r:0)  0@12592r
        -->	[12776r,12872r:0)  0@12776r
     %vreg194:	[12576r,12592r:0)  0@12576r
        -->	[12576r,12776r:0)  0@12576r
handleMove 12736B -> 12772B: %vreg171<def> = LDRBBui %vreg174, 0; mem:LD1[%arrayidx420] GPR32:%vreg171 GPR64common:%vreg174
     %vreg171:	[12736r,12856r:0)  0@12736r
        -->	[12772r,12856r:0)  0@12772r
     %vreg174:	[12720r,12736r:0)  0@12720r
        -->	[12720r,12772r:0)  0@12720r
handleMove 12720B -> 12776B: %vreg174<def> = ADDXrr %vreg176, %vreg180; GPR64common:%vreg174 GPR64:%vreg176,%vreg180
     %vreg174:	[12720r,12784r:0)  0@12720r
        -->	[12776r,12784r:0)  0@12776r
     %vreg176:	[12704r,12720r:0)  0@12704r
        -->	[12704r,12776r:0)  0@12704r
     %vreg180:	[12672r,12720r:0)  0@12672r
        -->	[12672r,12776r:0)  0@12672r
handleMove 12672B -> 12760B: %vreg180<def> = UBFMXri %vreg179, 0, 31; GPR64:%vreg180,%vreg179
     %vreg180:	[12672r,12776r:0)  0@12672r
        -->	[12760r,12776r:0)  0@12760r
     %vreg179:	[12640r,12672r:0)  0@12640r
        -->	[12640r,12760r:0)  0@12640r
handleMove 12640B -> 12756B: %vreg179:sub_32<def,read-undef> = UBFMWri %vreg184, 1, 31; GPR64:%vreg179 GPR32:%vreg184
     %vreg179:	[12640r,12760r:0)  0@12640r
        -->	[12756r,12760r:0)  0@12756r
     %vreg184:	[12624r,12640r:0)  0@12624r
        -->	[12624r,12756r:0)  0@12624r
handleMove 12704B -> 12760B: %vreg176<def> = LDRXui %vreg177, 396; mem:LD8[%ll4419] GPR64:%vreg176 GPR64common:%vreg177
     %vreg176:	[12704r,12792r:0)  0@12704r
        -->	[12760r,12792r:0)  0@12760r
     %vreg177:	[12688r,12704r:0)  0@12688r
        -->	[12688r,12760r:0)  0@12688r
handleMove 12576B -> 12696B: %vreg194<def> = ADDXrr %vreg196, %vreg193; GPR64common:%vreg194 GPR64:%vreg196,%vreg193
     %vreg194:	[12576r,12808r:0)  0@12576r
        -->	[12696r,12808r:0)  0@12696r
     %vreg196:	[12528r,12576r:0)  0@12528r
        -->	[12528r,12696r:0)  0@12528r
     %vreg193:	[12560r,12576r:0)  0@12560r
        -->	[12560r,12696r:0)  0@12560r
handleMove 12624B -> 12692B: %vreg184<def> = LDRWui %vreg185, 15; mem:LD4[%tPos416] GPR32:%vreg184 GPR64common:%vreg185
     %vreg184:	[12624r,12768r:0)  0@12624r
        -->	[12692r,12768r:0)  0@12692r
     %vreg185:	[12608r,12624r:0)  0@12608r
        -->	[12608r,12692r:0)  0@12608r
handleMove 12560B -> 12616B: %vreg193<def> = MADDXrrr %vreg203, %vreg192, %XZR; GPR64:%vreg193,%vreg203,%vreg192
     %vreg193:	[12560r,12696r:0)  0@12560r
        -->	[12616r,12696r:0)  0@12616r
     %vreg203:	[12480r,12560r:0)  0@12480r
        -->	[12480r,12616r:0)  0@12480r
     %vreg192:	[12544r,12560r:0)  0@12544r
        -->	[12544r,12616r:0)  0@12544r
     WZR:	[1664r,1664d:17)[1872r,1872d:16)[3104r,3104d:15)[3408r,3408d:13)[3632r,3632d:14)[3760r,3760d:12)[4928r,4928d:11)[5232r,5232d:9)[5456r,5456d:10)[5584r,5584d:8)[6752r,6752d:7)[7056r,7056d:5)[7280r,7280d:6)[7408r,7408d:4)[8528r,8528d:3)[8832r,8832d:2)[10000r,10000d:1)[10312r,10312d:0)[11760r,11760d:25)[11968r,11968d:24)[13056r,13056d:23)[13184r,13184d:22)[14208r,14208d:21)[14336r,14336d:20)[15360r,15360d:19)[15488r,15488d:18)  0@10312r 1@10000r 2@8832r 3@8528r 4@7408r 5@7056r 6@7280r 7@6752r 8@5584r 9@5232r 10@5456r 11@4928r 12@3760r 13@3408r 14@3632r 15@3104r 16@1872r 17@1664r 18@15488r 19@15360r 20@14336r 21@14208r 22@13184r 23@13056r 24@11968r 25@11760r
        -->	[1664r,1664d:17)[1872r,1872d:16)[3104r,3104d:15)[3408r,3408d:13)[3632r,3632d:14)[3760r,3760d:12)[4928r,4928d:11)[5232r,5232d:9)[5456r,5456d:10)[5584r,5584d:8)[6752r,6752d:7)[7056r,7056d:5)[7280r,7280d:6)[7408r,7408d:4)[8528r,8528d:3)[8832r,8832d:2)[10000r,10000d:1)[10312r,10312d:0)[11760r,11760d:25)[11968r,11968d:24)[13056r,13056d:23)[13184r,13184d:22)[14208r,14208d:21)[14336r,14336d:20)[15360r,15360d:19)[15488r,15488d:18)  0@10312r 1@10000r 2@8832r 3@8528r 4@7408r 5@7056r 6@7280r 7@6752r 8@5584r 9@5232r 10@5456r 11@4928r 12@3760r 13@3408r 14@3632r 15@3104r 16@1872r 17@1664r 18@15488r 19@15360r 20@14336r 21@14208r 22@13184r 23@13056r 24@11968r 25@11760r
handleMove 12528B -> 12612B: %vreg196<def> = LDRXui %vreg197, 395; mem:LD8[%ll16413] GPR64:%vreg196 GPR64common:%vreg197
     %vreg196:	[12528r,12696r:0)  0@12528r
        -->	[12612r,12696r:0)  0@12612r
     %vreg197:	[12512r,12528r:0)  0@12512r
        -->	[12512r,12612r:0)  0@12512r
handleMove 12480B -> 12520B: %vreg203:sub_32<def,read-undef> = LDRWui %vreg204, 15; mem:LD4[%tPos411] GPR64:%vreg203 GPR64common:%vreg204
     %vreg203:	[12480r,12616r:0)  0@12480r
        -->	[12520r,12616r:0)  0@12520r
     %vreg204:	[12464r,12480r:0)  0@12464r
        -->	[12464r,12520r:0)  0@12464r
handleMove 12224B -> 12248B: %vreg216<def> = LDRWui %vreg217, 15; mem:LD4[%tPos406] GPR32:%vreg216 GPR64common:%vreg217
     %vreg216:	[12224r,12288r:0)  0@12224r
        -->	[12248r,12288r:0)  0@12248r
     %vreg217:	[12208r,12224r:0)  0@12208r
        -->	[12208r,12248r:0)  0@12208r
handleMove 12080B -> 12104B: %vreg226<def> = MOVi32imm 1; GPR32:%vreg226
     %vreg226:	[12080r,12112r:0)  0@12080r
        -->	[12104r,12112r:0)  0@12104r
handleMove 13136B -> 13160B: %vreg236<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg236
     %vreg236:	[13136r,13184r:0)  0@13136r
        -->	[13160r,13184r:0)  0@13160r
AllocationOrder(GPR32sponly) = [ ]
handleMove 14112B -> 14184B: %vreg247<def> = LDRWui %vreg248, 273; mem:LD4[%nblock_used474] GPR32:%vreg247 GPR64common:%vreg248
     %vreg247:	[14112r,14208r:0)  0@14112r
        -->	[14184r,14208r:0)  0@14184r
     %vreg248:	[14096r,14112r:0)  0@14096r
        -->	[14096r,14184r:0)  0@14096r
handleMove 14096B -> 14136B: %vreg248<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg248
     %vreg248:	[14096r,14184r:0)  0@14096r
        -->	[14136r,14184r:0)  0@14136r
handleMove 13984B -> 14008B: %vreg260<def> = ORRWrs %vreg293, %vreg262, 16; GPR32:%vreg260,%vreg293 GPR32common:%vreg262
     %vreg260:	[13984r,14016r:0)  0@13984r
        -->	[14008r,14016r:0)  0@14008r
     %vreg293:	[13744r,13984r:0)  0@13744r
        -->	[13744r,14008r:0)  0@13744r
     %vreg262:	[13968r,13984r:0)  0@13968r
        -->	[13968r,14008r:0)  0@13968r
handleMove 13968B -> 14004B: %vreg262<def> = ANDWri %vreg265, 3; GPR32common:%vreg262 GPR32:%vreg265
     %vreg262:	[13968r,14008r:0)  0@13968r
        -->	[14004r,14008r:0)  0@14004r
     %vreg265:	[13952r,13968r:0)  0@13952r
        -->	[13952r,14004r:0)  0@13952r
handleMove 13952B -> 14008B: %vreg265<def> = LSRVWr %vreg275, %vreg268; GPR32:%vreg265,%vreg275,%vreg268
     %vreg265:	[13952r,14016r:0)  0@13952r
        -->	[14008r,14016r:0)  0@14008r
     %vreg275:	[13888r,13952r:0)  0@13888r
        -->	[13888r,14008r:0)  0@13888r
     %vreg268:	[13936r,13952r:0)  0@13936r
        -->	[13936r,14008r:0)  0@13936r
handleMove 13744B -> 13928B: %vreg293<def> = LDRHHui %vreg298, 0; mem:LD2[%arrayidx456] GPR32:%vreg293 GPR64common:%vreg298
     %vreg293:	[13744r,14024r:0)  0@13744r
        -->	[13928r,14024r:0)  0@13928r
     %vreg298:	[13728r,13744r:0)  0@13728r
        -->	[13728r,13928r:0)  0@13728r
handleMove 13888B -> 13924B: %vreg275<def> = LDRBBui %vreg278, 0; mem:LD1[%arrayidx462] GPR32:%vreg275 GPR64common:%vreg278
     %vreg275:	[13888r,14008r:0)  0@13888r
        -->	[13924r,14008r:0)  0@13924r
     %vreg278:	[13872r,13888r:0)  0@13872r
        -->	[13872r,13924r:0)  0@13872r
handleMove 13872B -> 13928B: %vreg278<def> = ADDXrr %vreg280, %vreg284; GPR64common:%vreg278 GPR64:%vreg280,%vreg284
     %vreg278:	[13872r,13936r:0)  0@13872r
        -->	[13928r,13936r:0)  0@13928r
     %vreg280:	[13856r,13872r:0)  0@13856r
        -->	[13856r,13928r:0)  0@13856r
     %vreg284:	[13824r,13872r:0)  0@13824r
        -->	[13824r,13928r:0)  0@13824r
handleMove 13824B -> 13912B: %vreg284<def> = UBFMXri %vreg283, 0, 31; GPR64:%vreg284,%vreg283
     %vreg284:	[13824r,13928r:0)  0@13824r
        -->	[13912r,13928r:0)  0@13912r
     %vreg283:	[13792r,13824r:0)  0@13792r
        -->	[13792r,13912r:0)  0@13792r
handleMove 13792B -> 13908B: %vreg283:sub_32<def,read-undef> = UBFMWri %vreg288, 1, 31; GPR64:%vreg283 GPR32:%vreg288
     %vreg283:	[13792r,13912r:0)  0@13792r
        -->	[13908r,13912r:0)  0@13908r
     %vreg288:	[13776r,13792r:0)  0@13776r
        -->	[13776r,13908r:0)  0@13776r
handleMove 13856B -> 13912B: %vreg280<def> = LDRXui %vreg281, 396; mem:LD8[%ll4461] GPR64:%vreg280 GPR64common:%vreg281
     %vreg280:	[13856r,13944r:0)  0@13856r
        -->	[13912r,13944r:0)  0@13912r
     %vreg281:	[13840r,13856r:0)  0@13840r
        -->	[13840r,13912r:0)  0@13840r
handleMove 13728B -> 13848B: %vreg298<def> = ADDXrr %vreg300, %vreg297; GPR64common:%vreg298 GPR64:%vreg300,%vreg297
     %vreg298:	[13728r,13960r:0)  0@13728r
        -->	[13848r,13960r:0)  0@13848r
     %vreg300:	[13680r,13728r:0)  0@13680r
        -->	[13680r,13848r:0)  0@13680r
     %vreg297:	[13712r,13728r:0)  0@13712r
        -->	[13712r,13848r:0)  0@13712r
handleMove 13776B -> 13844B: %vreg288<def> = LDRWui %vreg289, 15; mem:LD4[%tPos458] GPR32:%vreg288 GPR64common:%vreg289
     %vreg288:	[13776r,13920r:0)  0@13776r
        -->	[13844r,13920r:0)  0@13844r
     %vreg289:	[13760r,13776r:0)  0@13760r
        -->	[13760r,13844r:0)  0@13760r
handleMove 13712B -> 13768B: %vreg297<def> = MADDXrrr %vreg307, %vreg296, %XZR; GPR64:%vreg297,%vreg307,%vreg296
     %vreg297:	[13712r,13848r:0)  0@13712r
        -->	[13768r,13848r:0)  0@13768r
     %vreg307:	[13632r,13712r:0)  0@13632r
        -->	[13632r,13768r:0)  0@13632r
     %vreg296:	[13696r,13712r:0)  0@13696r
        -->	[13696r,13768r:0)  0@13696r
     WZR:	[1664r,1664d:17)[1872r,1872d:16)[3104r,3104d:15)[3408r,3408d:13)[3632r,3632d:14)[3760r,3760d:12)[4928r,4928d:11)[5232r,5232d:9)[5456r,5456d:10)[5584r,5584d:8)[6752r,6752d:7)[7056r,7056d:5)[7280r,7280d:6)[7408r,7408d:4)[8528r,8528d:3)[8832r,8832d:2)[10000r,10000d:1)[10312r,10312d:0)[11760r,11760d:25)[11968r,11968d:24)[13056r,13056d:23)[13184r,13184d:22)[14208r,14208d:21)[14336r,14336d:20)[15360r,15360d:19)[15488r,15488d:18)  0@10312r 1@10000r 2@8832r 3@8528r 4@7408r 5@7056r 6@7280r 7@6752r 8@5584r 9@5232r 10@5456r 11@4928r 12@3760r 13@3408r 14@3632r 15@3104r 16@1872r 17@1664r 18@15488r 19@15360r 20@14336r 21@14208r 22@13184r 23@13056r 24@11968r 25@11760r
        -->	[1664r,1664d:17)[1872r,1872d:16)[3104r,3104d:15)[3408r,3408d:13)[3632r,3632d:14)[3760r,3760d:12)[4928r,4928d:11)[5232r,5232d:9)[5456r,5456d:10)[5584r,5584d:8)[6752r,6752d:7)[7056r,7056d:5)[7280r,7280d:6)[7408r,7408d:4)[8528r,8528d:3)[8832r,8832d:2)[10000r,10000d:1)[10312r,10312d:0)[11760r,11760d:25)[11968r,11968d:24)[13056r,13056d:23)[13184r,13184d:22)[14208r,14208d:21)[14336r,14336d:20)[15360r,15360d:19)[15488r,15488d:18)  0@10312r 1@10000r 2@8832r 3@8528r 4@7408r 5@7056r 6@7280r 7@6752r 8@5584r 9@5232r 10@5456r 11@4928r 12@3760r 13@3408r 14@3632r 15@3104r 16@1872r 17@1664r 18@15488r 19@15360r 20@14336r 21@14208r 22@13184r 23@13056r 24@11968r 25@11760r
handleMove 13680B -> 13764B: %vreg300<def> = LDRXui %vreg301, 395; mem:LD8[%ll16455] GPR64:%vreg300 GPR64common:%vreg301
     %vreg300:	[13680r,13848r:0)  0@13680r
        -->	[13764r,13848r:0)  0@13764r
     %vreg301:	[13664r,13680r:0)  0@13664r
        -->	[13664r,13764r:0)  0@13664r
handleMove 13632B -> 13672B: %vreg307:sub_32<def,read-undef> = LDRWui %vreg308, 15; mem:LD4[%tPos453] GPR64:%vreg307 GPR64common:%vreg308
     %vreg307:	[13632r,13768r:0)  0@13632r
        -->	[13672r,13768r:0)  0@13672r
     %vreg308:	[13616r,13632r:0)  0@13616r
        -->	[13616r,13672r:0)  0@13616r
handleMove 13376B -> 13400B: %vreg320<def> = LDRWui %vreg321, 15; mem:LD4[%tPos448] GPR32:%vreg320 GPR64common:%vreg321
     %vreg320:	[13376r,13440r:0)  0@13376r
        -->	[13400r,13440r:0)  0@13400r
     %vreg321:	[13360r,13376r:0)  0@13360r
        -->	[13360r,13400r:0)  0@13360r
handleMove 13312B -> 13336B: %vreg322<def> = MOVi32imm 2; GPR32:%vreg322
     %vreg322:	[13312r,13344r:0)  0@13312r
        -->	[13336r,13344r:0)  0@13336r
handleMove 14288B -> 14312B: %vreg332<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg332
     %vreg332:	[14288r,14336r:0)  0@14288r
        -->	[14312r,14336r:0)  0@14312r
AllocationOrder(GPR32sponly) = [ ]
handleMove 15264B -> 15336B: %vreg343<def> = LDRWui %vreg344, 273; mem:LD4[%nblock_used516] GPR32:%vreg343 GPR64common:%vreg344
     %vreg343:	[15264r,15360r:0)  0@15264r
        -->	[15336r,15360r:0)  0@15336r
     %vreg344:	[15248r,15264r:0)  0@15248r
        -->	[15248r,15336r:0)  0@15248r
handleMove 15248B -> 15288B: %vreg344<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg344
     %vreg344:	[15248r,15336r:0)  0@15248r
        -->	[15288r,15336r:0)  0@15288r
handleMove 15136B -> 15160B: %vreg356<def> = ORRWrs %vreg389, %vreg358, 16; GPR32:%vreg356,%vreg389 GPR32common:%vreg358
     %vreg356:	[15136r,15168r:0)  0@15136r
        -->	[15160r,15168r:0)  0@15160r
     %vreg389:	[14896r,15136r:0)  0@14896r
        -->	[14896r,15160r:0)  0@14896r
     %vreg358:	[15120r,15136r:0)  0@15120r
        -->	[15120r,15160r:0)  0@15120r
handleMove 15120B -> 15156B: %vreg358<def> = ANDWri %vreg361, 3; GPR32common:%vreg358 GPR32:%vreg361
     %vreg358:	[15120r,15160r:0)  0@15120r
        -->	[15156r,15160r:0)  0@15156r
     %vreg361:	[15104r,15120r:0)  0@15104r
        -->	[15104r,15156r:0)  0@15104r
handleMove 15104B -> 15160B: %vreg361<def> = LSRVWr %vreg371, %vreg364; GPR32:%vreg361,%vreg371,%vreg364
     %vreg361:	[15104r,15168r:0)  0@15104r
        -->	[15160r,15168r:0)  0@15160r
     %vreg371:	[15040r,15104r:0)  0@15040r
        -->	[15040r,15160r:0)  0@15040r
     %vreg364:	[15088r,15104r:0)  0@15088r
        -->	[15088r,15160r:0)  0@15088r
handleMove 14896B -> 15080B: %vreg389<def> = LDRHHui %vreg394, 0; mem:LD2[%arrayidx498] GPR32:%vreg389 GPR64common:%vreg394
     %vreg389:	[14896r,15176r:0)  0@14896r
        -->	[15080r,15176r:0)  0@15080r
     %vreg394:	[14880r,14896r:0)  0@14880r
        -->	[14880r,15080r:0)  0@14880r
handleMove 15040B -> 15076B: %vreg371<def> = LDRBBui %vreg374, 0; mem:LD1[%arrayidx504] GPR32:%vreg371 GPR64common:%vreg374
     %vreg371:	[15040r,15160r:0)  0@15040r
        -->	[15076r,15160r:0)  0@15076r
     %vreg374:	[15024r,15040r:0)  0@15024r
        -->	[15024r,15076r:0)  0@15024r
handleMove 15024B -> 15080B: %vreg374<def> = ADDXrr %vreg376, %vreg380; GPR64common:%vreg374 GPR64:%vreg376,%vreg380
     %vreg374:	[15024r,15088r:0)  0@15024r
        -->	[15080r,15088r:0)  0@15080r
     %vreg376:	[15008r,15024r:0)  0@15008r
        -->	[15008r,15080r:0)  0@15008r
     %vreg380:	[14976r,15024r:0)  0@14976r
        -->	[14976r,15080r:0)  0@14976r
handleMove 14976B -> 15064B: %vreg380<def> = UBFMXri %vreg379, 0, 31; GPR64:%vreg380,%vreg379
     %vreg380:	[14976r,15080r:0)  0@14976r
        -->	[15064r,15080r:0)  0@15064r
     %vreg379:	[14944r,14976r:0)  0@14944r
        -->	[14944r,15064r:0)  0@14944r
handleMove 14944B -> 15060B: %vreg379:sub_32<def,read-undef> = UBFMWri %vreg384, 1, 31; GPR64:%vreg379 GPR32:%vreg384
     %vreg379:	[14944r,15064r:0)  0@14944r
        -->	[15060r,15064r:0)  0@15060r
     %vreg384:	[14928r,14944r:0)  0@14928r
        -->	[14928r,15060r:0)  0@14928r
handleMove 15008B -> 15064B: %vreg376<def> = LDRXui %vreg377, 396; mem:LD8[%ll4503] GPR64:%vreg376 GPR64common:%vreg377
     %vreg376:	[15008r,15096r:0)  0@15008r
        -->	[15064r,15096r:0)  0@15064r
     %vreg377:	[14992r,15008r:0)  0@14992r
        -->	[14992r,15064r:0)  0@14992r
handleMove 14880B -> 15000B: %vreg394<def> = ADDXrr %vreg396, %vreg393; GPR64common:%vreg394 GPR64:%vreg396,%vreg393
     %vreg394:	[14880r,15112r:0)  0@14880r
        -->	[15000r,15112r:0)  0@15000r
     %vreg396:	[14832r,14880r:0)  0@14832r
        -->	[14832r,15000r:0)  0@14832r
     %vreg393:	[14864r,14880r:0)  0@14864r
        -->	[14864r,15000r:0)  0@14864r
handleMove 14928B -> 14996B: %vreg384<def> = LDRWui %vreg385, 15; mem:LD4[%tPos500] GPR32:%vreg384 GPR64common:%vreg385
     %vreg384:	[14928r,15072r:0)  0@14928r
        -->	[14996r,15072r:0)  0@14996r
     %vreg385:	[14912r,14928r:0)  0@14912r
        -->	[14912r,14996r:0)  0@14912r
handleMove 14864B -> 14920B: %vreg393<def> = MADDXrrr %vreg403, %vreg392, %XZR; GPR64:%vreg393,%vreg403,%vreg392
     %vreg393:	[14864r,15000r:0)  0@14864r
        -->	[14920r,15000r:0)  0@14920r
     %vreg403:	[14784r,14864r:0)  0@14784r
        -->	[14784r,14920r:0)  0@14784r
     %vreg392:	[14848r,14864r:0)  0@14848r
        -->	[14848r,14920r:0)  0@14848r
     WZR:	[1664r,1664d:17)[1872r,1872d:16)[3104r,3104d:15)[3408r,3408d:13)[3632r,3632d:14)[3760r,3760d:12)[4928r,4928d:11)[5232r,5232d:9)[5456r,5456d:10)[5584r,5584d:8)[6752r,6752d:7)[7056r,7056d:5)[7280r,7280d:6)[7408r,7408d:4)[8528r,8528d:3)[8832r,8832d:2)[10000r,10000d:1)[10312r,10312d:0)[11760r,11760d:25)[11968r,11968d:24)[13056r,13056d:23)[13184r,13184d:22)[14208r,14208d:21)[14336r,14336d:20)[15360r,15360d:19)[15488r,15488d:18)  0@10312r 1@10000r 2@8832r 3@8528r 4@7408r 5@7056r 6@7280r 7@6752r 8@5584r 9@5232r 10@5456r 11@4928r 12@3760r 13@3408r 14@3632r 15@3104r 16@1872r 17@1664r 18@15488r 19@15360r 20@14336r 21@14208r 22@13184r 23@13056r 24@11968r 25@11760r
        -->	[1664r,1664d:17)[1872r,1872d:16)[3104r,3104d:15)[3408r,3408d:13)[3632r,3632d:14)[3760r,3760d:12)[4928r,4928d:11)[5232r,5232d:9)[5456r,5456d:10)[5584r,5584d:8)[6752r,6752d:7)[7056r,7056d:5)[7280r,7280d:6)[7408r,7408d:4)[8528r,8528d:3)[8832r,8832d:2)[10000r,10000d:1)[10312r,10312d:0)[11760r,11760d:25)[11968r,11968d:24)[13056r,13056d:23)[13184r,13184d:22)[14208r,14208d:21)[14336r,14336d:20)[15360r,15360d:19)[15488r,15488d:18)  0@10312r 1@10000r 2@8832r 3@8528r 4@7408r 5@7056r 6@7280r 7@6752r 8@5584r 9@5232r 10@5456r 11@4928r 12@3760r 13@3408r 14@3632r 15@3104r 16@1872r 17@1664r 18@15488r 19@15360r 20@14336r 21@14208r 22@13184r 23@13056r 24@11968r 25@11760r
handleMove 14832B -> 14916B: %vreg396<def> = LDRXui %vreg397, 395; mem:LD8[%ll16497] GPR64:%vreg396 GPR64common:%vreg397
     %vreg396:	[14832r,15000r:0)  0@14832r
        -->	[14916r,15000r:0)  0@14916r
     %vreg397:	[14816r,14832r:0)  0@14816r
        -->	[14816r,14916r:0)  0@14816r
handleMove 14784B -> 14824B: %vreg403:sub_32<def,read-undef> = LDRWui %vreg404, 15; mem:LD4[%tPos495] GPR64:%vreg403 GPR64common:%vreg404
     %vreg403:	[14784r,14920r:0)  0@14784r
        -->	[14824r,14920r:0)  0@14824r
     %vreg404:	[14768r,14784r:0)  0@14768r
        -->	[14768r,14824r:0)  0@14768r
handleMove 14528B -> 14552B: %vreg416<def> = LDRWui %vreg417, 15; mem:LD4[%tPos490] GPR32:%vreg416 GPR64common:%vreg417
     %vreg416:	[14528r,14592r:0)  0@14528r
        -->	[14552r,14592r:0)  0@14552r
     %vreg417:	[14512r,14528r:0)  0@14512r
        -->	[14512r,14552r:0)  0@14512r
handleMove 14464B -> 14488B: %vreg418<def> = MOVi32imm 3; GPR32:%vreg418
     %vreg418:	[14464r,14496r:0)  0@14464r
        -->	[14488r,14496r:0)  0@14488r
handleMove 15440B -> 15464B: %vreg428<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg428
     %vreg428:	[15440r,15488r:0)  0@15440r
        -->	[15464r,15488r:0)  0@15464r
AllocationOrder(GPR32sponly) = [ ]
handleMove 17040B -> 17064B: %vreg440<def> = ORRWrs %vreg473, %vreg442, 16; GPR32:%vreg440,%vreg473 GPR32common:%vreg442
     %vreg440:	[17040r,17072r:0)  0@17040r
        -->	[17064r,17072r:0)  0@17064r
     %vreg473:	[16800r,17040r:0)  0@16800r
        -->	[16800r,17064r:0)  0@16800r
     %vreg442:	[17024r,17040r:0)  0@17024r
        -->	[17024r,17064r:0)  0@17024r
handleMove 17024B -> 17060B: %vreg442<def> = ANDWri %vreg445, 3; GPR32common:%vreg442 GPR32:%vreg445
     %vreg442:	[17024r,17064r:0)  0@17024r
        -->	[17060r,17064r:0)  0@17060r
     %vreg445:	[17008r,17024r:0)  0@17008r
        -->	[17008r,17060r:0)  0@17008r
handleMove 17008B -> 17064B: %vreg445<def> = LSRVWr %vreg455, %vreg448; GPR32:%vreg445,%vreg455,%vreg448
     %vreg445:	[17008r,17072r:0)  0@17008r
        -->	[17064r,17072r:0)  0@17064r
     %vreg455:	[16944r,17008r:0)  0@16944r
        -->	[16944r,17064r:0)  0@16944r
     %vreg448:	[16992r,17008r:0)  0@16992r
        -->	[16992r,17064r:0)  0@16992r
handleMove 16800B -> 16984B: %vreg473<def> = LDRHHui %vreg478, 0; mem:LD2[%arrayidx568] GPR32:%vreg473 GPR64common:%vreg478
     %vreg473:	[16800r,17080r:0)  0@16800r
        -->	[16984r,17080r:0)  0@16984r
     %vreg478:	[16784r,16800r:0)  0@16784r
        -->	[16784r,16984r:0)  0@16784r
handleMove 16944B -> 16980B: %vreg455<def> = LDRBBui %vreg458, 0; mem:LD1[%arrayidx574] GPR32:%vreg455 GPR64common:%vreg458
     %vreg455:	[16944r,17064r:0)  0@16944r
        -->	[16980r,17064r:0)  0@16980r
     %vreg458:	[16928r,16944r:0)  0@16928r
        -->	[16928r,16980r:0)  0@16928r
handleMove 16928B -> 16984B: %vreg458<def> = ADDXrr %vreg460, %vreg464; GPR64common:%vreg458 GPR64:%vreg460,%vreg464
     %vreg458:	[16928r,16992r:0)  0@16928r
        -->	[16984r,16992r:0)  0@16984r
     %vreg460:	[16912r,16928r:0)  0@16912r
        -->	[16912r,16984r:0)  0@16912r
     %vreg464:	[16880r,16928r:0)  0@16880r
        -->	[16880r,16984r:0)  0@16880r
handleMove 16880B -> 16968B: %vreg464<def> = UBFMXri %vreg463, 0, 31; GPR64:%vreg464,%vreg463
     %vreg464:	[16880r,16984r:0)  0@16880r
        -->	[16968r,16984r:0)  0@16968r
     %vreg463:	[16848r,16880r:0)  0@16848r
        -->	[16848r,16968r:0)  0@16848r
handleMove 16848B -> 16964B: %vreg463:sub_32<def,read-undef> = UBFMWri %vreg468, 1, 31; GPR64:%vreg463 GPR32:%vreg468
     %vreg463:	[16848r,16968r:0)  0@16848r
        -->	[16964r,16968r:0)  0@16964r
     %vreg468:	[16832r,16848r:0)  0@16832r
        -->	[16832r,16964r:0)  0@16832r
handleMove 16912B -> 16968B: %vreg460<def> = LDRXui %vreg461, 396; mem:LD8[%ll4573] GPR64:%vreg460 GPR64common:%vreg461
     %vreg460:	[16912r,17000r:0)  0@16912r
        -->	[16968r,17000r:0)  0@16968r
     %vreg461:	[16896r,16912r:0)  0@16896r
        -->	[16896r,16968r:0)  0@16896r
handleMove 16784B -> 16904B: %vreg478<def> = ADDXrr %vreg480, %vreg477; GPR64common:%vreg478 GPR64:%vreg480,%vreg477
     %vreg478:	[16784r,17016r:0)  0@16784r
        -->	[16904r,17016r:0)  0@16904r
     %vreg480:	[16736r,16784r:0)  0@16736r
        -->	[16736r,16904r:0)  0@16736r
     %vreg477:	[16768r,16784r:0)  0@16768r
        -->	[16768r,16904r:0)  0@16768r
handleMove 16832B -> 16900B: %vreg468<def> = LDRWui %vreg469, 15; mem:LD4[%tPos570] GPR32:%vreg468 GPR64common:%vreg469
     %vreg468:	[16832r,16976r:0)  0@16832r
        -->	[16900r,16976r:0)  0@16900r
     %vreg469:	[16816r,16832r:0)  0@16816r
        -->	[16816r,16900r:0)  0@16816r
handleMove 16768B -> 16824B: %vreg477<def> = MADDXrrr %vreg487, %vreg476, %XZR; GPR64:%vreg477,%vreg487,%vreg476
     %vreg477:	[16768r,16904r:0)  0@16768r
        -->	[16824r,16904r:0)  0@16824r
     %vreg487:	[16688r,16768r:0)  0@16688r
        -->	[16688r,16824r:0)  0@16688r
     %vreg476:	[16752r,16768r:0)  0@16752r
        -->	[16752r,16824r:0)  0@16752r
     WZR:	[1664r,1664d:17)[1872r,1872d:16)[3104r,3104d:15)[3408r,3408d:13)[3632r,3632d:14)[3760r,3760d:12)[4928r,4928d:11)[5232r,5232d:9)[5456r,5456d:10)[5584r,5584d:8)[6752r,6752d:7)[7056r,7056d:5)[7280r,7280d:6)[7408r,7408d:4)[8528r,8528d:3)[8832r,8832d:2)[10000r,10000d:1)[10312r,10312d:0)[11760r,11760d:25)[11968r,11968d:24)[13056r,13056d:23)[13184r,13184d:22)[14208r,14208d:21)[14336r,14336d:20)[15360r,15360d:19)[15488r,15488d:18)  0@10312r 1@10000r 2@8832r 3@8528r 4@7408r 5@7056r 6@7280r 7@6752r 8@5584r 9@5232r 10@5456r 11@4928r 12@3760r 13@3408r 14@3632r 15@3104r 16@1872r 17@1664r 18@15488r 19@15360r 20@14336r 21@14208r 22@13184r 23@13056r 24@11968r 25@11760r
        -->	[1664r,1664d:17)[1872r,1872d:16)[3104r,3104d:15)[3408r,3408d:13)[3632r,3632d:14)[3760r,3760d:12)[4928r,4928d:11)[5232r,5232d:9)[5456r,5456d:10)[5584r,5584d:8)[6752r,6752d:7)[7056r,7056d:5)[7280r,7280d:6)[7408r,7408d:4)[8528r,8528d:3)[8832r,8832d:2)[10000r,10000d:1)[10312r,10312d:0)[11760r,11760d:25)[11968r,11968d:24)[13056r,13056d:23)[13184r,13184d:22)[14208r,14208d:21)[14336r,14336d:20)[15360r,15360d:19)[15488r,15488d:18)  0@10312r 1@10000r 2@8832r 3@8528r 4@7408r 5@7056r 6@7280r 7@6752r 8@5584r 9@5232r 10@5456r 11@4928r 12@3760r 13@3408r 14@3632r 15@3104r 16@1872r 17@1664r 18@15488r 19@15360r 20@14336r 21@14208r 22@13184r 23@13056r 24@11968r 25@11760r
handleMove 16736B -> 16820B: %vreg480<def> = LDRXui %vreg481, 395; mem:LD8[%ll16567] GPR64:%vreg480 GPR64common:%vreg481
     %vreg480:	[16736r,16904r:0)  0@16736r
        -->	[16820r,16904r:0)  0@16820r
     %vreg481:	[16720r,16736r:0)  0@16720r
        -->	[16720r,16820r:0)  0@16720r
handleMove 16688B -> 16728B: %vreg487:sub_32<def,read-undef> = LDRWui %vreg488, 15; mem:LD4[%tPos565] GPR64:%vreg487 GPR64common:%vreg488
     %vreg487:	[16688r,16824r:0)  0@16688r
        -->	[16728r,16824r:0)  0@16728r
     %vreg488:	[16672r,16688r:0)  0@16672r
        -->	[16672r,16728r:0)  0@16672r
AllocationOrder(GPR32sponly) = [ ]
handleMove 16432B -> 16456B: %vreg500<def> = LDRWui %vreg501, 15; mem:LD4[%tPos560] GPR32:%vreg500 GPR64common:%vreg501
     %vreg500:	[16432r,16496r:0)  0@16432r
        -->	[16456r,16496r:0)  0@16456r
     %vreg501:	[16416r,16432r:0)  0@16416r
        -->	[16416r,16456r:0)  0@16416r
handleMove 16368B -> 16392B: %vreg506<def> = ADDWri %vreg509, 4, 0; GPR32common:%vreg506,%vreg509
     %vreg506:	[16368r,16400r:0)  0@16368r
        -->	[16392r,16400r:0)  0@16392r
     %vreg509:	[16352r,16368r:0)  0@16352r
        -->	[16352r,16392r:0)  0@16352r
handleMove 16240B -> 16264B: %vreg521<def> = ORRWrs %vreg554, %vreg523, 16; GPR32:%vreg521,%vreg554 GPR32common:%vreg523
     %vreg521:	[16240r,16272r:0)  0@16240r
        -->	[16264r,16272r:0)  0@16264r
     %vreg554:	[16000r,16240r:0)  0@16000r
        -->	[16000r,16264r:0)  0@16000r
     %vreg523:	[16224r,16240r:0)  0@16224r
        -->	[16224r,16264r:0)  0@16224r
handleMove 16224B -> 16260B: %vreg523<def> = ANDWri %vreg526, 3; GPR32common:%vreg523 GPR32:%vreg526
     %vreg523:	[16224r,16264r:0)  0@16224r
        -->	[16260r,16264r:0)  0@16260r
     %vreg526:	[16208r,16224r:0)  0@16208r
        -->	[16208r,16260r:0)  0@16208r
handleMove 16208B -> 16264B: %vreg526<def> = LSRVWr %vreg536, %vreg529; GPR32:%vreg526,%vreg536,%vreg529
     %vreg526:	[16208r,16272r:0)  0@16208r
        -->	[16264r,16272r:0)  0@16264r
     %vreg536:	[16144r,16208r:0)  0@16144r
        -->	[16144r,16264r:0)  0@16144r
     %vreg529:	[16192r,16208r:0)  0@16192r
        -->	[16192r,16264r:0)  0@16192r
handleMove 16000B -> 16184B: %vreg554<def> = LDRHHui %vreg559, 0; mem:LD2[%arrayidx539] GPR32:%vreg554 GPR64common:%vreg559
     %vreg554:	[16000r,16280r:0)  0@16000r
        -->	[16184r,16280r:0)  0@16184r
     %vreg559:	[15984r,16000r:0)  0@15984r
        -->	[15984r,16184r:0)  0@15984r
handleMove 16144B -> 16180B: %vreg536<def> = LDRBBui %vreg539, 0; mem:LD1[%arrayidx545] GPR32:%vreg536 GPR64common:%vreg539
     %vreg536:	[16144r,16264r:0)  0@16144r
        -->	[16180r,16264r:0)  0@16180r
     %vreg539:	[16128r,16144r:0)  0@16128r
        -->	[16128r,16180r:0)  0@16128r
handleMove 16128B -> 16184B: %vreg539<def> = ADDXrr %vreg541, %vreg545; GPR64common:%vreg539 GPR64:%vreg541,%vreg545
     %vreg539:	[16128r,16192r:0)  0@16128r
        -->	[16184r,16192r:0)  0@16184r
     %vreg541:	[16112r,16128r:0)  0@16112r
        -->	[16112r,16184r:0)  0@16112r
     %vreg545:	[16080r,16128r:0)  0@16080r
        -->	[16080r,16184r:0)  0@16080r
handleMove 16080B -> 16168B: %vreg545<def> = UBFMXri %vreg544, 0, 31; GPR64:%vreg545,%vreg544
     %vreg545:	[16080r,16184r:0)  0@16080r
        -->	[16168r,16184r:0)  0@16168r
     %vreg544:	[16048r,16080r:0)  0@16048r
        -->	[16048r,16168r:0)  0@16048r
handleMove 16048B -> 16164B: %vreg544:sub_32<def,read-undef> = UBFMWri %vreg549, 1, 31; GPR64:%vreg544 GPR32:%vreg549
     %vreg544:	[16048r,16168r:0)  0@16048r
        -->	[16164r,16168r:0)  0@16164r
     %vreg549:	[16032r,16048r:0)  0@16032r
        -->	[16032r,16164r:0)  0@16032r
handleMove 16112B -> 16168B: %vreg541<def> = LDRXui %vreg542, 396; mem:LD8[%ll4544] GPR64:%vreg541 GPR64common:%vreg542
     %vreg541:	[16112r,16200r:0)  0@16112r
        -->	[16168r,16200r:0)  0@16168r
     %vreg542:	[16096r,16112r:0)  0@16096r
        -->	[16096r,16168r:0)  0@16096r
handleMove 15984B -> 16104B: %vreg559<def> = ADDXrr %vreg561, %vreg558; GPR64common:%vreg559 GPR64:%vreg561,%vreg558
     %vreg559:	[15984r,16216r:0)  0@15984r
        -->	[16104r,16216r:0)  0@16104r
     %vreg561:	[15936r,15984r:0)  0@15936r
        -->	[15936r,16104r:0)  0@15936r
     %vreg558:	[15968r,15984r:0)  0@15968r
        -->	[15968r,16104r:0)  0@15968r
handleMove 16032B -> 16100B: %vreg549<def> = LDRWui %vreg550, 15; mem:LD4[%tPos541] GPR32:%vreg549 GPR64common:%vreg550
     %vreg549:	[16032r,16176r:0)  0@16032r
        -->	[16100r,16176r:0)  0@16100r
     %vreg550:	[16016r,16032r:0)  0@16016r
        -->	[16016r,16100r:0)  0@16016r
handleMove 15968B -> 16024B: %vreg558<def> = MADDXrrr %vreg568, %vreg557, %XZR; GPR64:%vreg558,%vreg568,%vreg557
     %vreg558:	[15968r,16104r:0)  0@15968r
        -->	[16024r,16104r:0)  0@16024r
     %vreg568:	[15888r,15968r:0)  0@15888r
        -->	[15888r,16024r:0)  0@15888r
     %vreg557:	[15952r,15968r:0)  0@15952r
        -->	[15952r,16024r:0)  0@15952r
     WZR:	[1664r,1664d:17)[1872r,1872d:16)[3104r,3104d:15)[3408r,3408d:13)[3632r,3632d:14)[3760r,3760d:12)[4928r,4928d:11)[5232r,5232d:9)[5456r,5456d:10)[5584r,5584d:8)[6752r,6752d:7)[7056r,7056d:5)[7280r,7280d:6)[7408r,7408d:4)[8528r,8528d:3)[8832r,8832d:2)[10000r,10000d:1)[10312r,10312d:0)[11760r,11760d:25)[11968r,11968d:24)[13056r,13056d:23)[13184r,13184d:22)[14208r,14208d:21)[14336r,14336d:20)[15360r,15360d:19)[15488r,15488d:18)  0@10312r 1@10000r 2@8832r 3@8528r 4@7408r 5@7056r 6@7280r 7@6752r 8@5584r 9@5232r 10@5456r 11@4928r 12@3760r 13@3408r 14@3632r 15@3104r 16@1872r 17@1664r 18@15488r 19@15360r 20@14336r 21@14208r 22@13184r 23@13056r 24@11968r 25@11760r
        -->	[1664r,1664d:17)[1872r,1872d:16)[3104r,3104d:15)[3408r,3408d:13)[3632r,3632d:14)[3760r,3760d:12)[4928r,4928d:11)[5232r,5232d:9)[5456r,5456d:10)[5584r,5584d:8)[6752r,6752d:7)[7056r,7056d:5)[7280r,7280d:6)[7408r,7408d:4)[8528r,8528d:3)[8832r,8832d:2)[10000r,10000d:1)[10312r,10312d:0)[11760r,11760d:25)[11968r,11968d:24)[13056r,13056d:23)[13184r,13184d:22)[14208r,14208d:21)[14336r,14336d:20)[15360r,15360d:19)[15488r,15488d:18)  0@10312r 1@10000r 2@8832r 3@8528r 4@7408r 5@7056r 6@7280r 7@6752r 8@5584r 9@5232r 10@5456r 11@4928r 12@3760r 13@3408r 14@3632r 15@3104r 16@1872r 17@1664r 18@15488r 19@15360r 20@14336r 21@14208r 22@13184r 23@13056r 24@11968r 25@11760r
handleMove 15936B -> 16020B: %vreg561<def> = LDRXui %vreg562, 395; mem:LD8[%ll16538] GPR64:%vreg561 GPR64common:%vreg562
     %vreg561:	[15936r,16104r:0)  0@15936r
        -->	[16020r,16104r:0)  0@16020r
     %vreg562:	[15920r,15936r:0)  0@15920r
        -->	[15920r,16020r:0)  0@15920r
handleMove 15888B -> 15928B: %vreg568:sub_32<def,read-undef> = LDRWui %vreg569, 15; mem:LD4[%tPos536] GPR64:%vreg568 GPR64common:%vreg569
     %vreg568:	[15888r,16024r:0)  0@15888r
        -->	[15928r,16024r:0)  0@15928r
     %vreg569:	[15872r,15888r:0)  0@15872r
        -->	[15872r,15928r:0)  0@15872r
handleMove 15632B -> 15656B: %vreg581<def> = LDRWui %vreg582, 15; mem:LD4[%tPos531] GPR32:%vreg581 GPR64common:%vreg582
     %vreg581:	[15632r,15696r:0)  0@15632r
        -->	[15656r,15696r:0)  0@15656r
     %vreg582:	[15616r,15632r:0)  0@15616r
        -->	[15616r,15656r:0)  0@15616r
********** GREEDY REGISTER ALLOCATION **********
********** Function: unRLE_obuf_to_output_SMALL
********** INTERVALS **********
W30 [0B,16r:0)[176r,176d:24)[224e,224d:12)[2224r,2224d:18)[2304e,2304d:11)[4048r,4048d:17)[4128e,4128d:10)[5872r,5872d:16)[5952e,5952d:9)[7648r,7648d:15)[7728e,7728d:8)[9120r,9120d:14)[9200e,9200d:7)[12320r,12320d:23)[12400e,12400d:6)[13472r,13472d:22)[13552e,13552d:5)[14624r,14624d:21)[14704e,14704d:4)[15728r,15728d:19)[15808e,15808d:3)[16528r,16528d:20)[16608e,16608d:2)[17248r,17248d:13)[17296e,17296d:1)  0@0B-phi 1@17296e 2@16608e 3@15808e 4@14704e 5@13552e 6@12400e 7@9200e 8@7728e 9@5952e 10@4128e 11@2304e 12@224e 13@17248r 14@9120r 15@7648r 16@5872r 17@4048r 18@2224r 19@15728r 20@16528r 21@14624r 22@13472r 23@12320r 24@176r
NZCV [1664r,1680r:17)[1872r,1888r:16)[3104r,3120r:15)[3408r,3416r:13)[3632r,3648r:14)[3760r,3776r:12)[4928r,4944r:11)[5232r,5240r:9)[5456r,5472r:10)[5584r,5600r:8)[6752r,6768r:7)[7056r,7064r:5)[7280r,7296r:6)[7408r,7424r:4)[8528r,8544r:3)[8832r,8840r:2)[10000r,10016r:1)[10312r,10328r:0)[11760r,11776r:25)[11968r,11984r:24)[13056r,13072r:23)[13184r,13200r:22)[14208r,14224r:21)[14336r,14352r:20)[15360r,15376r:19)[15488r,15504r:18)  0@10312r 1@10000r 2@8832r 3@8528r 4@7408r 5@7056r 6@7280r 7@6752r 8@5584r 9@5232r 10@5456r 11@4928r 12@3760r 13@3408r 14@3632r 15@3104r 16@1872r 17@1664r 18@15488r 19@15360r 20@14336r 21@14208r 22@13184r 23@13056r 24@11968r 25@11760r
WZR [1664r,1664d:17)[1872r,1872d:16)[3104r,3104d:15)[3408r,3408d:13)[3632r,3632d:14)[3760r,3760d:12)[4928r,4928d:11)[5232r,5232d:9)[5456r,5456d:10)[5584r,5584d:8)[6752r,6752d:7)[7056r,7056d:5)[7280r,7280d:6)[7408r,7408d:4)[8528r,8528d:3)[8832r,8832d:2)[10000r,10000d:1)[10312r,10312d:0)[11760r,11760d:25)[11968r,11968d:24)[13056r,13056d:23)[13184r,13184d:22)[14208r,14208d:21)[14336r,14336d:20)[15360r,15360d:19)[15488r,15488d:18)  0@10312r 1@10000r 2@8832r 3@8528r 4@7408r 5@7056r 6@7280r 7@6752r 8@5584r 9@5232r 10@5456r 11@4928r 12@3760r 13@3408r 14@3632r 15@3104r 16@1872r 17@1664r 18@15488r 19@15360r 20@14336r 21@14208r 22@13184r 23@13056r 24@11968r 25@11760r
W0 [0B,32r:0)[144r,176r:23)[2192r,2224r:11)[2224r,2256r:10)[4016r,4048r:9)[4048r,4080r:8)[5840r,5872r:7)[5872r,5904r:6)[7616r,7648r:5)[7648r,7680r:4)[9088r,9120r:3)[9120r,9152r:2)[12288r,12320r:21)[12320r,12352r:20)[13440r,13472r:19)[13472r,13504r:18)[14592r,14624r:17)[14624r,14656r:16)[15696r,15728r:13)[15728r,15760r:12)[16496r,16528r:15)[16528r,16560r:14)[17216r,17248r:22)[17360r,17376r:1)  0@0B-phi 1@17360r 2@9120r 3@9088r 4@7648r 5@7616r 6@5872r 7@5840r 8@4048r 9@4016r 10@2224r 11@2192r 12@15728r 13@15696r 14@16528r 15@16496r 16@14624r 17@14592r 18@13472r 19@13440r 20@12320r 21@12288r 22@17216r 23@144r
%vreg1 [32r,256r:0)  0@32r
%vreg3 [304r,320r:0)  0@304r
%vreg5 [288r,304r:0)  0@288r
%vreg6 [272r,288r:0)  0@272r
%vreg7 [64r,80r:0)  0@64r
%vreg9 [80r,144r:0)  0@80r
%vreg10 [16r,17232r:0)  0@16r
%vreg14 [10544r,10560r:0)  0@10544r
%vreg16 [10528r,10544r:0)  0@10528r
%vreg17 [10512r,10528r:0)  0@10512r
%vreg20 [10656r,10672r:0)  0@10656r
%vreg21 [10640r,10656r:0)  0@10640r
%vreg24 [11472r,11488r:0)  0@11472r
%vreg26 [11456r,11472r:0)  0@11456r
%vreg27 [11440r,11456r:0)  0@11440r
%vreg31 [11408r,11424r:0)  0@11408r
%vreg32 [11392r,11408r:0)  0@11392r
%vreg34 [11376r,11424r:0)  0@11376r
%vreg35 [11360r,11376r:0)  0@11360r
%vreg39 [11328r,11344r:0)  0@11328r
%vreg40 [11312r,11328r:0)  0@11312r
%vreg42 [11296r,11344r:0)  0@11296r
%vreg43 [11280r,11296r:0)  0@11280r
%vreg47 [11248r,11264r:0)  0@11248r
%vreg48 [11232r,11248r:0)  0@11232r
%vreg50 [11216r,11264r:0)  0@11216r
%vreg51 [11200r,11216r:0)  0@11200r
%vreg55 [11168r,11184r:0)  0@11168r
%vreg56 [11152r,11168r:0)  0@11152r
%vreg57 [11136r,11184r:0)  0@11136r
%vreg60 [11104r,11120r:0)  0@11104r
%vreg63 [11112r,11120r:0)  0@11112r
%vreg65 [11072r,11112r:0)  0@11072r
%vreg66 [10952r,10984r:0)  0@10952r
%vreg67 [10984r,11056r:0)  0@10984r
%vreg69 [11032r,11040r:0)  0@11032r
%vreg70 [11040r,11056r:0)  0@11040r
%vreg71 [11056r,11072r:0)  0@11056r
%vreg73 [11008r,11024r:0)  0@11008r
%vreg74 [11024r,11040r:0)  0@11024r
%vreg81 [10976r,11008r:0)  0@10976r
%vreg82 [10944r,10976r:0)  0@10944r
%vreg84 [11000r,11008r:0)  0@11000r
%vreg86 [10968r,11000r:0)  0@10968r
%vreg87 [10896r,10968r:0)  0@10896r
%vreg89 [10992r,11112r:0)  0@10992r
%vreg90 [10960r,10992r:0)  0@10960r
%vreg94 [10832r,10848r:0)  0@10832r
%vreg96 [10816r,10832r:0)  0@10816r
%vreg97 [10800r,10816r:0)  0@10800r
%vreg99 [10824r,10848r:0)  0@10824r
%vreg100 [10808r,10824r:0)  0@10808r
%vreg104 [11568r,11584r:0)  0@11568r
%vreg105 [11552r,11568r:0)  0@11552r
%vreg107 [11536r,11584r:0)  0@11536r
%vreg108 [11520r,11536r:0)  0@11520r
%vreg112 [11744r,11760r:0)  0@11744r
%vreg114 [11696r,11712r:0)  0@11696r
%vreg115 [11712r,11728r:0)  0@11712r
%vreg116 [11728r,11744r:0)  0@11728r
%vreg117 [11680r,11712r:0)  0@11680r
%vreg119 [11736r,11760r:0)  0@11736r
%vreg120 [11688r,11736r:0)  0@11688r
%vreg124 [11952r,11968r:0)  0@11952r
%vreg126 [11904r,11920r:0)  0@11904r
%vreg127 [11920r,11936r:0)  0@11920r
%vreg128 [11936r,11952r:0)  0@11936r
%vreg129 [11888r,11920r:0)  0@11888r
%vreg131 [11944r,11968r:0)  0@11944r
%vreg132 [11896r,11944r:0)  0@11896r
%vreg136 [13040r,13056r:0)  0@13040r
%vreg138 [12992r,13008r:0)  0@12992r
%vreg139 [13008r,13024r:0)  0@13008r
%vreg140 [13024r,13040r:0)  0@13024r
%vreg141 [12976r,13008r:0)  0@12976r
%vreg143 [13032r,13056r:0)  0@13032r
%vreg144 [12984r,13032r:0)  0@12984r
%vreg148 [12912r,12928r:0)  0@12912r
%vreg149 [12896r,12912r:0)  0@12896r
%vreg150 [12888r,12928r:0)  0@12888r
%vreg153 [12848r,12880r:0)  0@12848r
%vreg156 [12872r,12880r:0)  0@12872r
%vreg158 [12864r,12872r:0)  0@12864r
%vreg161 [12856r,12864r:0)  0@12856r
%vreg162 [12368r,12816r:0)  0@12368r
%vreg164 [12816r,12856r:0)  0@12816r
%vreg166 [12784r,12816r:0)  0@12784r
%vreg167 [12752r,12784r:0)  0@12752r
%vreg171 [12800r,12856r:0)  0@12800r
%vreg174 [12792r,12800r:0)  0@12792r
%vreg176 [12760r,12792r:0)  0@12760r
%vreg177 [12688r,12760r:0)  0@12688r
%vreg179 [12768r,12776r:0)  0@12768r
%vreg180 [12776r,12792r:0)  0@12776r
%vreg184 [12692r,12768r:0)  0@12692r
%vreg185 [12608r,12692r:0)  0@12608r
%vreg189 [12808r,12872r:0)  0@12808r
%vreg192 [12544r,12616r:0)  0@12544r
%vreg193 [12616r,12696r:0)  0@12616r
%vreg194 [12696r,12808r:0)  0@12696r
%vreg196 [12612r,12696r:0)  0@12612r
%vreg197 [12512r,12612r:0)  0@12512r
%vreg203 [12520r,12616r:0)  0@12520r
%vreg204 [12464r,12520r:0)  0@12464r
%vreg207 [12352r,12448r:0)  0@12352r
%vreg213 [12256r,12304r:0)  0@12256r
%vreg214 [12240r,12256r:0)  0@12240r
%vreg216 [12248r,12288r:0)  0@12248r
%vreg217 [12208r,12248r:0)  0@12208r
%vreg220 [12176r,12192r:0)  0@12176r
%vreg222 [12144r,12192r:0)  0@12144r
%vreg225 [12128r,12144r:0)  0@12128r
%vreg226 [12104r,12112r:0)  0@12104r
%vreg228 [12096r,12112r:0)  0@12096r
%vreg232 [13168r,13184r:0)  0@13168r
%vreg233 [13152r,13168r:0)  0@13152r
%vreg236 [13160r,13184r:0)  0@13160r
%vreg240 [14192r,14208r:0)  0@14192r
%vreg242 [14144r,14160r:0)  0@14144r
%vreg243 [14160r,14176r:0)  0@14160r
%vreg244 [14176r,14192r:0)  0@14176r
%vreg245 [14128r,14160r:0)  0@14128r
%vreg247 [14184r,14208r:0)  0@14184r
%vreg248 [14136r,14184r:0)  0@14136r
%vreg252 [14064r,14080r:0)  0@14064r
%vreg253 [14048r,14064r:0)  0@14048r
%vreg254 [14040r,14080r:0)  0@14040r
%vreg257 [14000r,14032r:0)  0@14000r
%vreg260 [14024r,14032r:0)  0@14024r
%vreg262 [14016r,14024r:0)  0@14016r
%vreg265 [14008r,14016r:0)  0@14008r
%vreg266 [13520r,13968r:0)  0@13520r
%vreg268 [13968r,14008r:0)  0@13968r
%vreg270 [13936r,13968r:0)  0@13936r
%vreg271 [13904r,13936r:0)  0@13904r
%vreg275 [13952r,14008r:0)  0@13952r
%vreg278 [13944r,13952r:0)  0@13944r
%vreg280 [13912r,13944r:0)  0@13912r
%vreg281 [13840r,13912r:0)  0@13840r
%vreg283 [13920r,13928r:0)  0@13920r
%vreg284 [13928r,13944r:0)  0@13928r
%vreg288 [13844r,13920r:0)  0@13844r
%vreg289 [13760r,13844r:0)  0@13760r
%vreg293 [13960r,14024r:0)  0@13960r
%vreg296 [13696r,13768r:0)  0@13696r
%vreg297 [13768r,13848r:0)  0@13768r
%vreg298 [13848r,13960r:0)  0@13848r
%vreg300 [13764r,13848r:0)  0@13764r
%vreg301 [13664r,13764r:0)  0@13664r
%vreg307 [13672r,13768r:0)  0@13672r
%vreg308 [13616r,13672r:0)  0@13616r
%vreg311 [13504r,13600r:0)  0@13504r
%vreg317 [13408r,13456r:0)  0@13408r
%vreg318 [13392r,13408r:0)  0@13392r
%vreg320 [13400r,13440r:0)  0@13400r
%vreg321 [13360r,13400r:0)  0@13360r
%vreg322 [13336r,13344r:0)  0@13336r
%vreg324 [13328r,13344r:0)  0@13328r
%vreg328 [14320r,14336r:0)  0@14320r
%vreg329 [14304r,14320r:0)  0@14304r
%vreg332 [14312r,14336r:0)  0@14312r
%vreg336 [15344r,15360r:0)  0@15344r
%vreg338 [15296r,15312r:0)  0@15296r
%vreg339 [15312r,15328r:0)  0@15312r
%vreg340 [15328r,15344r:0)  0@15328r
%vreg341 [15280r,15312r:0)  0@15280r
%vreg343 [15336r,15360r:0)  0@15336r
%vreg344 [15288r,15336r:0)  0@15288r
%vreg348 [15216r,15232r:0)  0@15216r
%vreg349 [15200r,15216r:0)  0@15200r
%vreg350 [15192r,15232r:0)  0@15192r
%vreg353 [15152r,15184r:0)  0@15152r
%vreg356 [15176r,15184r:0)  0@15176r
%vreg358 [15168r,15176r:0)  0@15168r
%vreg361 [15160r,15168r:0)  0@15160r
%vreg362 [14672r,15120r:0)  0@14672r
%vreg364 [15120r,15160r:0)  0@15120r
%vreg366 [15088r,15120r:0)  0@15088r
%vreg367 [15056r,15088r:0)  0@15056r
%vreg371 [15104r,15160r:0)  0@15104r
%vreg374 [15096r,15104r:0)  0@15096r
%vreg376 [15064r,15096r:0)  0@15064r
%vreg377 [14992r,15064r:0)  0@14992r
%vreg379 [15072r,15080r:0)  0@15072r
%vreg380 [15080r,15096r:0)  0@15080r
%vreg384 [14996r,15072r:0)  0@14996r
%vreg385 [14912r,14996r:0)  0@14912r
%vreg389 [15112r,15176r:0)  0@15112r
%vreg392 [14848r,14920r:0)  0@14848r
%vreg393 [14920r,15000r:0)  0@14920r
%vreg394 [15000r,15112r:0)  0@15000r
%vreg396 [14916r,15000r:0)  0@14916r
%vreg397 [14816r,14916r:0)  0@14816r
%vreg403 [14824r,14920r:0)  0@14824r
%vreg404 [14768r,14824r:0)  0@14768r
%vreg407 [14656r,14752r:0)  0@14656r
%vreg413 [14560r,14608r:0)  0@14560r
%vreg414 [14544r,14560r:0)  0@14544r
%vreg416 [14552r,14592r:0)  0@14552r
%vreg417 [14512r,14552r:0)  0@14512r
%vreg418 [14488r,14496r:0)  0@14488r
%vreg420 [14480r,14496r:0)  0@14480r
%vreg424 [15472r,15488r:0)  0@15472r
%vreg425 [15456r,15472r:0)  0@15456r
%vreg428 [15464r,15488r:0)  0@15464r
%vreg432 [17120r,17136r:0)  0@17120r
%vreg433 [17104r,17120r:0)  0@17104r
%vreg434 [17096r,17136r:0)  0@17096r
%vreg437 [17056r,17088r:0)  0@17056r
%vreg440 [17080r,17088r:0)  0@17080r
%vreg442 [17072r,17080r:0)  0@17072r
%vreg445 [17064r,17072r:0)  0@17064r
%vreg446 [16576r,17024r:0)  0@16576r
%vreg448 [17024r,17064r:0)  0@17024r
%vreg450 [16992r,17024r:0)  0@16992r
%vreg451 [16960r,16992r:0)  0@16960r
%vreg455 [17008r,17064r:0)  0@17008r
%vreg458 [17000r,17008r:0)  0@17000r
%vreg460 [16968r,17000r:0)  0@16968r
%vreg461 [16896r,16968r:0)  0@16896r
%vreg463 [16976r,16984r:0)  0@16976r
%vreg464 [16984r,17000r:0)  0@16984r
%vreg468 [16900r,16976r:0)  0@16900r
%vreg469 [16816r,16900r:0)  0@16816r
%vreg473 [17016r,17080r:0)  0@17016r
%vreg476 [16752r,16824r:0)  0@16752r
%vreg477 [16824r,16904r:0)  0@16824r
%vreg478 [16904r,17016r:0)  0@16904r
%vreg480 [16820r,16904r:0)  0@16820r
%vreg481 [16720r,16820r:0)  0@16720r
%vreg487 [16728r,16824r:0)  0@16728r
%vreg488 [16672r,16728r:0)  0@16672r
%vreg491 [16640r,16656r:0)  0@16640r
%vreg494 [16560r,16656r:0)  0@16560r
%vreg497 [16464r,16512r:0)  0@16464r
%vreg498 [16448r,16464r:0)  0@16448r
%vreg500 [16456r,16496r:0)  0@16456r
%vreg501 [16416r,16456r:0)  0@16416r
%vreg504 [16384r,16400r:0)  0@16384r
%vreg506 [16392r,16400r:0)  0@16392r
%vreg509 [16352r,16392r:0)  0@16352r
%vreg513 [16320r,16336r:0)  0@16320r
%vreg514 [16304r,16320r:0)  0@16304r
%vreg515 [16296r,16336r:0)  0@16296r
%vreg518 [16256r,16288r:0)  0@16256r
%vreg521 [16280r,16288r:0)  0@16280r
%vreg523 [16272r,16280r:0)  0@16272r
%vreg526 [16264r,16272r:0)  0@16264r
%vreg527 [15776r,16224r:0)  0@15776r
%vreg529 [16224r,16264r:0)  0@16224r
%vreg531 [16192r,16224r:0)  0@16192r
%vreg532 [16160r,16192r:0)  0@16160r
%vreg536 [16208r,16264r:0)  0@16208r
%vreg539 [16200r,16208r:0)  0@16200r
%vreg541 [16168r,16200r:0)  0@16168r
%vreg542 [16096r,16168r:0)  0@16096r
%vreg544 [16176r,16184r:0)  0@16176r
%vreg545 [16184r,16200r:0)  0@16184r
%vreg549 [16100r,16176r:0)  0@16100r
%vreg550 [16016r,16100r:0)  0@16016r
%vreg554 [16216r,16280r:0)  0@16216r
%vreg557 [15952r,16024r:0)  0@15952r
%vreg558 [16024r,16104r:0)  0@16024r
%vreg559 [16104r,16216r:0)  0@16104r
%vreg561 [16020r,16104r:0)  0@16020r
%vreg562 [15920r,16020r:0)  0@15920r
%vreg568 [15928r,16024r:0)  0@15928r
%vreg569 [15872r,15928r:0)  0@15872r
%vreg572 [15760r,15856r:0)  0@15760r
%vreg578 [15664r,15712r:0)  0@15664r
%vreg579 [15648r,15664r:0)  0@15648r
%vreg581 [15656r,15696r:0)  0@15656r
%vreg582 [15616r,15656r:0)  0@15616r
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%vreg1317 [9576r,9592r:0)  0@9576r
%vreg1321 [9492r,9568r:0)  0@9492r
%vreg1322 [9408r,9492r:0)  0@9408r
%vreg1326 [9608r,9672r:0)  0@9608r
%vreg1329 [9344r,9416r:0)  0@9344r
%vreg1330 [9416r,9496r:0)  0@9416r
%vreg1331 [9496r,9608r:0)  0@9496r
%vreg1333 [9412r,9496r:0)  0@9412r
%vreg1334 [9312r,9412r:0)  0@9312r
%vreg1340 [9320r,9416r:0)  0@9320r
%vreg1341 [9264r,9320r:0)  0@9264r
%vreg1344 [9232r,9248r:0)  0@9232r
%vreg1347 [9152r,9248r:0)  0@9152r
%vreg1350 [9056r,9104r:0)  0@9056r
%vreg1351 [9040r,9056r:0)  0@9040r
%vreg1353 [9048r,9088r:0)  0@9048r
%vreg1354 [9008r,9048r:0)  0@9008r
%vreg1357 [8976r,8992r:0)  0@8976r
%vreg1359 [8984r,8992r:0)  0@8984r
%vreg1362 [8944r,8984r:0)  0@8944r
%vreg1366 [8912r,8928r:0)  0@8912r
%vreg1367 [8896r,8912r:0)  0@8896r
%vreg1368 [8880r,8928r:0)  0@8880r
%vreg1371 [8848r,8864r:0)  0@8848r
%vreg1377 [8816r,8848r:0)  0@8816r
%vreg1379 [8824r,8840r:0)  0@8824r
%vreg1380 [8648r,8840r:0)  0@8648r
%vreg1381 [8840r,8848r:0)  0@8840r
%vreg1383 [8768r,8832r:0)  0@8768r
%vreg1384 [8752r,8768r:0)  0@8752r
%vreg1388 [8720r,8736r:0)  0@8720r
%vreg1389 [8704r,8720r:0)  0@8704r
%vreg1390 [8688r,8736r:0)  0@8688r
%vreg1393 [9984r,10000r:0)  0@9984r
%vreg1394 [9968r,9984r:0)  0@9968r
%vreg1398 [9936r,9952r:0)  0@9936r
%vreg1399 [9920r,9936r:0)  0@9920r
%vreg1400 [9904r,9952r:0)  0@9904r
%vreg1403 [9872r,9888r:0)  0@9872r
%vreg1405 [9856r,9888r:0)  0@9856r
%vreg1406 [9800r,9816r:0)  0@9800r
%vreg1407 [9816r,9840r:0)  0@9816r
%vreg1409 [9808r,9824r:0)  0@9808r
%vreg1410 [9824r,9840r:0)  0@9824r
%vreg1411 [9840r,9856r:0)  0@9840r
%vreg1416 [9792r,9824r:0)  0@9792r
%vreg1417 [9776r,9792r:0)  0@9776r
%vreg1419 [10048r,10064r:0)  0@10048r
%vreg1423 [10384r,10400r:0)  0@10384r
%vreg1424 [10368r,10384r:0)  0@10368r
%vreg1425 [10352r,10400r:0)  0@10352r
%vreg1430 [10336r,10344r:0)  0@10336r
%vreg1431 [10304r,10336r:0)  0@10304r
%vreg1432 [10288r,10344r:0)  0@10288r
%vreg1434 [10320r,10328r:0)  0@10320r
%vreg1435 [10120r,10328r:0)  0@10120r
%vreg1436 [10328r,10336r:0)  0@10328r
%vreg1438 [10296r,10312r:0)  0@10296r
%vreg1439 [10224r,10296r:0)  0@10224r
%vreg1443 [10192r,10208r:0)  0@10192r
%vreg1444 [10176r,10192r:0)  0@10176r
%vreg1445 [10160r,10208r:0)  0@10160r
%vreg1448 [7472r,7488r:0)  0@7472r
%vreg1451 [7456r,7488r:0)  0@7456r
%vreg1454 [5648r,5664r:0)  0@5648r
%vreg1457 [5632r,5664r:0)  0@5632r
%vreg1460 [3824r,3840r:0)  0@3824r
%vreg1463 [3808r,3840r:0)  0@3808r
%vreg1464 [1920r,1936r:0)  0@1920r
%vreg1466 [17200r,17216r:0)  0@17200r
%vreg1467 [17328r,17360r:0)  0@17328r
RegMasks: 176r 2224r 4048r 5872r 7648r 9120r 12320r 13472r 14624r 15728r 16528r 17248r
********** MACHINEINSTRS **********
# Machine code for function unRLE_obuf_to_output_SMALL: Post SSA
Frame Objects:
  fi#0: size=1, align=1, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=1, align=1, at location [SP]
Function Live Ins: %X0 in %vreg0, %LR in %vreg11

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %LR
16B		%vreg10<def> = COPY %LR; GPR64:%vreg10
32B		%vreg1<def> = COPY %X0; GPR64:%vreg1
64B		%vreg7<def> = ADRP <ga:@unRLE_obuf_to_output_SMALL>[TF=1]; GPR64common:%vreg7
80B		%vreg9<def> = ADDXri %vreg7, <ga:@unRLE_obuf_to_output_SMALL>[TF=34], 0; GPR64sp:%vreg9 GPR64common:%vreg7
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		%X0<def> = COPY %vreg9; GPR64sp:%vreg9
160B		%X1<def> = COPY %vreg10; GPR64:%vreg10
176B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
224B		STACKMAP 0, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, %vreg1, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1] GPR64:%vreg1
240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
256B		STRXui %vreg1, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg1
272B		%vreg6<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg6
288B		%vreg5<def> = LDRBBui %vreg6, 20; mem:LD1[%blockRandomised] GPR32:%vreg5 GPR64common:%vreg6
304B		%vreg3<def> = UBFMWri %vreg5, 0, 7; GPR32:%vreg3,%vreg5
320B		CBZW %vreg3, <BB#47>; GPR32:%vreg3
	    Successors according to CFG: BB#47 BB#1

336B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
352B		B <BB#2>
	    Successors according to CFG: BB#2

368B	BB#2: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#1 BB#46 BB#37 BB#35 BB#29 BB#27 BB#21 BB#19
384B		B <BB#3>
	    Successors according to CFG: BB#3

400B	BB#3: derived from LLVM BB %while.body.2
	    Predecessors according to CFG: BB#2 BB#9
416B		%vreg607<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg607
432B		%vreg606<def> = LDRXui %vreg607, 0; mem:LD8[%strm] GPR64common:%vreg606,%vreg607
448B		%vreg604<def> = LDRWui %vreg606, 8; mem:LD4[%avail_out] GPR32:%vreg604 GPR64common:%vreg606
464B		CBNZW %vreg604, <BB#5>; GPR32:%vreg604
	    Successors according to CFG: BB#5 BB#4

480B	BB#4: derived from LLVM BB %if.then.3
	    Predecessors according to CFG: BB#3
496B		STRBBui %WZR, <fi#0>, 0; mem:ST1[FixedStack0]
512B		B <BB#73>
	    Successors according to CFG: BB#73

528B	BB#5: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#3
544B		%vreg611<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg611
560B		%vreg610<def> = LDRWui %vreg611, 4; mem:LD4[%state_out_len] GPR32:%vreg610 GPR64common:%vreg611
576B		CBNZW %vreg610, <BB#7>; GPR32:%vreg610
	    Successors according to CFG: BB#7 BB#6

592B	BB#6: derived from LLVM BB %if.then.5
	    Predecessors according to CFG: BB#5
608B		B <BB#10>
	    Successors according to CFG: BB#10

624B	BB#7: derived from LLVM BB %if.end.6
	    Predecessors according to CFG: BB#5
704B		%vreg687<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg687
712B		%vreg690<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg690
720B		%vreg686<def> = LDRXui %vreg687, 0; mem:LD8[%strm7] GPR64common:%vreg686,%vreg687
728B		%vreg689<def> = LDRBBui %vreg690, 12; mem:LD1[%state_out_ch] GPR32:%vreg689 GPR64common:%vreg690
736B		%vreg684<def> = LDRXui %vreg686, 3; mem:LD8[%next_out] GPR64common:%vreg684,%vreg686
752B		STRBBui %vreg689, %vreg684, 0; mem:ST1[%11] GPR32:%vreg689 GPR64common:%vreg684
800B		%vreg677<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg677
848B		%vreg672<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg672
856B		%vreg656<def> = ADRP <ga:@BZ2_crc32Table>[TF=1]; GPR64common:%vreg656
864B		%vreg680<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg680
872B		%vreg676<def> = LDRWui %vreg677, 796; mem:LD4[%calculatedBlockCRC8] GPR32:%vreg676 GPR64common:%vreg677
880B		%vreg671<def> = LDRBBui %vreg672, 12; mem:LD1[%state_out_ch9] GPR32:%vreg671 GPR64common:%vreg672
888B		%vreg657<def> = ADDXri %vreg656, <ga:@BZ2_crc32Table>[TF=34], 0; GPR64common:%vreg657,%vreg656
896B		%vreg679<def> = LDRWui %vreg680, 796; mem:LD4[%calculatedBlockCRC] GPR32:%vreg679 GPR64common:%vreg680
904B		%vreg674<def> = UBFMWri %vreg676, 24, 31; GPR32:%vreg674,%vreg676
912B		%vreg663:sub_32<def,read-undef> = EORWrr %vreg674, %vreg671; GPR64:%vreg663 GPR32:%vreg674,%vreg671
928B		%vreg664<def> = UBFMXri %vreg663, 0, 31; GPR64:%vreg664,%vreg663
936B		%vreg659<def> = MOVi64imm 4; GPR64:%vreg659
944B		%vreg660<def> = MADDXrrr %vreg664, %vreg659, %XZR; GPR64:%vreg660,%vreg664,%vreg659
960B		%vreg661<def> = ADDXrr %vreg657, %vreg660; GPR64common:%vreg661,%vreg657 GPR64:%vreg660
976B		%vreg655<def> = LDRWui %vreg661, 0; mem:LD4[%arrayidx] GPR32:%vreg655 GPR64common:%vreg661
1008B		%vreg650<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg650
1016B		%vreg653<def> = EORWrs %vreg655, %vreg679, 8; GPR32:%vreg653,%vreg655,%vreg679
1024B		STRWui %vreg653, %vreg650, 796; mem:ST4[%calculatedBlockCRC11] GPR32:%vreg653 GPR64common:%vreg650
1040B		%vreg647<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg647
1056B		%vreg646<def> = LDRWui %vreg647, 4; mem:LD4[%state_out_len12] GPR32common:%vreg646 GPR64common:%vreg647
1072B		%vreg645<def> = SUBWri %vreg646, 1, 0; GPR32common:%vreg645,%vreg646
1088B		STRWui %vreg645, %vreg647, 4; mem:ST4[%state_out_len12] GPR32common:%vreg645 GPR64common:%vreg647
1104B		%vreg641<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg641
1120B		%vreg640<def> = LDRXui %vreg641, 0; mem:LD8[%strm13] GPR64common:%vreg640,%vreg641
1136B		%vreg638<def> = LDRXui %vreg640, 3; mem:LD8[%next_out14] GPR64common:%vreg638,%vreg640
1152B		%vreg637<def> = ADDXri %vreg638, 1, 0; GPR64common:%vreg637,%vreg638
1168B		STRXui %vreg637, %vreg640, 3; mem:ST8[%next_out14] GPR64common:%vreg637,%vreg640
1184B		%vreg633<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg633
1200B		%vreg632<def> = LDRXui %vreg633, 0; mem:LD8[%strm15] GPR64common:%vreg632,%vreg633
1216B		%vreg630<def> = LDRWui %vreg632, 8; mem:LD4[%avail_out16] GPR32common:%vreg630 GPR64common:%vreg632
1232B		%vreg629<def> = SUBWri %vreg630, 1, 0; GPR32common:%vreg629,%vreg630
1248B		STRWui %vreg629, %vreg632, 8; mem:ST4[%avail_out16] GPR32common:%vreg629 GPR64common:%vreg632
1264B		%vreg625<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg625
1280B		%vreg624<def> = LDRXui %vreg625, 0; mem:LD8[%strm18] GPR64common:%vreg624,%vreg625
1296B		%vreg622<def> = LDRWui %vreg624, 9; mem:LD4[%total_out_lo32] GPR32common:%vreg622 GPR64common:%vreg624
1312B		%vreg621<def> = ADDWri %vreg622, 1, 0; GPR32common:%vreg621,%vreg622
1328B		STRWui %vreg621, %vreg624, 9; mem:ST4[%total_out_lo32] GPR32common:%vreg621 GPR64common:%vreg624
1344B		%vreg617<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg617
1360B		%vreg616<def> = LDRXui %vreg617, 0; mem:LD8[%strm19] GPR64common:%vreg616,%vreg617
1376B		%vreg614<def> = LDRWui %vreg616, 9; mem:LD4[%total_out_lo3220] GPR32:%vreg614 GPR64common:%vreg616
1392B		CBNZW %vreg614, <BB#9>; GPR32:%vreg614
	    Successors according to CFG: BB#9 BB#8

1408B	BB#8: derived from LLVM BB %if.then.23
	    Predecessors according to CFG: BB#7
1424B		%vreg698<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg698
1440B		%vreg697<def> = LDRXui %vreg698, 0; mem:LD8[%strm24] GPR64common:%vreg697,%vreg698
1456B		%vreg695<def> = LDRWui %vreg697, 10; mem:LD4[%total_out_hi32] GPR32common:%vreg695 GPR64common:%vreg697
1472B		%vreg694<def> = ADDWri %vreg695, 1, 0; GPR32common:%vreg694,%vreg695
1488B		STRWui %vreg694, %vreg697, 10; mem:ST4[%total_out_hi32] GPR32common:%vreg694 GPR64common:%vreg697
	    Successors according to CFG: BB#9

1504B	BB#9: derived from LLVM BB %if.end.26
	    Predecessors according to CFG: BB#7 BB#8
1520B		B <BB#3>
	    Successors according to CFG: BB#3

1536B	BB#10: derived from LLVM BB %while.end
	    Predecessors according to CFG: BB#6
1584B		%vreg707<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg707
1592B		%vreg710<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg710
1600B		%vreg704<def> = MOVi64imm 64080; GPR64:%vreg704
1616B		%vreg705<def> = ADDXrr %vreg707, %vreg704; GPR64common:%vreg705 GPR64:%vreg707,%vreg704
1632B		%vreg706<def> = LDRWui %vreg705, 0; mem:LD4[%save_nblock] GPR32common:%vreg706 GPR64common:%vreg705
1640B		%vreg709<def> = LDRWui %vreg710, 273; mem:LD4[%nblock_used] GPR32:%vreg709 GPR64common:%vreg710
1648B		%vreg702<def> = ADDWri %vreg706, 1, 0; GPR32common:%vreg702,%vreg706
1664B		%WZR<def> = SUBSWrr %vreg709, %vreg702, %NZCV<imp-def>; GPR32:%vreg709 GPR32common:%vreg702
1680B		Bcc 1, <BB#12>, %NZCV<imp-use>
	    Successors according to CFG: BB#12 BB#11

1696B	BB#11: derived from LLVM BB %if.then.29
	    Predecessors according to CFG: BB#10
1712B		STRBBui %WZR, <fi#0>, 0; mem:ST1[FixedStack0]
1728B		B <BB#73>
	    Successors according to CFG: BB#73

1744B	BB#12: derived from LLVM BB %if.end.30
	    Predecessors according to CFG: BB#10
1792B		%vreg719<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg719
1800B		%vreg722<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg722
1808B		%vreg716<def> = MOVi64imm 64080; GPR64:%vreg716
1824B		%vreg717<def> = ADDXrr %vreg719, %vreg716; GPR64common:%vreg717 GPR64:%vreg719,%vreg716
1840B		%vreg718<def> = LDRWui %vreg717, 0; mem:LD4[%save_nblock32] GPR32common:%vreg718 GPR64common:%vreg717
1848B		%vreg721<def> = LDRWui %vreg722, 273; mem:LD4[%nblock_used31] GPR32:%vreg721 GPR64common:%vreg722
1856B		%vreg714<def> = ADDWri %vreg718, 1, 0; GPR32common:%vreg714,%vreg718
1872B		%WZR<def> = SUBSWrr %vreg721, %vreg714, %NZCV<imp-def>; GPR32:%vreg721 GPR32common:%vreg714
1888B		Bcc 13, <BB#14>, %NZCV<imp-use>
	    Successors according to CFG: BB#14 BB#13

1904B	BB#13: derived from LLVM BB %if.then.36
	    Predecessors according to CFG: BB#12
1920B		%vreg1464<def> = MOVi32imm 1; GPR32:%vreg1464
1936B		STRBBui %vreg1464, <fi#0>, 0; mem:ST1[FixedStack0] GPR32:%vreg1464
1952B		B <BB#73>
	    Successors according to CFG: BB#73

1968B	BB#14: derived from LLVM BB %if.end.37
	    Predecessors according to CFG: BB#12
2000B		%vreg804<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg804
2008B		%vreg802<def> = MOVi32imm 1; GPR32:%vreg802
2016B		STRWui %vreg802, %vreg804, 4; mem:ST4[%state_out_len38] GPR32:%vreg802 GPR64common:%vreg804
2032B		%vreg801<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg801
2048B		%vreg798<def> = LDRWui %vreg801, 16; mem:LD4[%k0] GPR32:%vreg798 GPR64common:%vreg801
2080B		%vreg796<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg796
2096B		STRBBui %vreg798, %vreg796, 12; mem:ST1[%state_out_ch40] GPR32:%vreg798 GPR64common:%vreg796
2112B		%vreg793<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg793
2144B		%vreg790<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg790
2152B		%vreg792<def> = LDRWui %vreg793, 15; mem:LD4[%tPos] GPR32:%vreg792 GPR64common:%vreg793
2160B		%vreg789<def> = ADDXri %vreg790, 1096, 0; GPR64sp:%vreg789 GPR64common:%vreg790
2176B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2192B		%W0<def> = COPY %vreg792; GPR32:%vreg792
2208B		%X1<def> = COPY %vreg789; GPR64sp:%vreg789
2224B		BL <ga:@BZ2_indexIntoF>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use,kill>, %W0<imp-def>
2240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2256B		%vreg783<def> = COPY %W0; GPR32:%vreg783
2272B		%vreg738<def> = MOVi32imm 4; GPR32:%vreg738
2288B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2304B		STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
2320B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2352B		STRBBui %vreg783, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg783
2368B		%vreg780<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg780
2416B		%vreg773<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg773
2424B		%vreg779:sub_32<def,read-undef> = LDRWui %vreg780, 15; mem:LD4[%tPos42] GPR64:%vreg779 GPR64common:%vreg780
2448B		%vreg768<def> = MOVi64imm 2; GPR64:%vreg768
2512B		%vreg761<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg761
2516B		%vreg772<def> = LDRXui %vreg773, 395; mem:LD8[%ll16] GPR64:%vreg772 GPR64common:%vreg773
2520B		%vreg769<def> = MADDXrrr %vreg779, %vreg768, %XZR; GPR64:%vreg769,%vreg779,%vreg768
2592B		%vreg753<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg753
2596B		%vreg760<def> = LDRWui %vreg761, 15; mem:LD4[%tPos46] GPR32:%vreg760 GPR64common:%vreg761
2600B		%vreg770<def> = ADDXrr %vreg772, %vreg769; GPR64common:%vreg770 GPR64:%vreg772,%vreg769
2656B		%vreg743<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg743
2664B		%vreg752<def> = LDRXui %vreg753, 396; mem:LD8[%ll4] GPR64:%vreg752 GPR64common:%vreg753
2672B		%vreg755:sub_32<def,read-undef> = UBFMWri %vreg760, 1, 31; GPR64:%vreg755 GPR32:%vreg760
2680B		%vreg756<def> = UBFMXri %vreg755, 0, 31; GPR64:%vreg756,%vreg755
2688B		%vreg742<def> = LDRWui %vreg743, 15; mem:LD4[%tPos51] GPR32:%vreg742 GPR64common:%vreg743
2696B		%vreg750<def> = ADDXrr %vreg752, %vreg756; GPR64common:%vreg750 GPR64:%vreg752,%vreg756
2704B		%vreg747<def> = LDRBBui %vreg750, 0; mem:LD1[%arrayidx49] GPR32:%vreg747 GPR64common:%vreg750
2712B		%vreg765<def> = LDRHHui %vreg770, 0; mem:LD2[%arrayidx44] GPR32:%vreg765 GPR64common:%vreg770
2720B		%vreg740<def> = ANDWrs %vreg738, %vreg742, 2; GPR32:%vreg740,%vreg738,%vreg742
2752B		%vreg729<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg729
2760B		%vreg737<def> = LSRVWr %vreg747, %vreg740; GPR32:%vreg737,%vreg747,%vreg740
2768B		%vreg734<def> = ANDWri %vreg737, 3; GPR32common:%vreg734 GPR32:%vreg737
2776B		%vreg732<def> = ORRWrs %vreg765, %vreg734, 16; GPR32:%vreg732,%vreg765 GPR32common:%vreg734
2784B		STRWui %vreg732, %vreg729, 15; mem:ST4[%tPos56] GPR32:%vreg732 GPR64common:%vreg729
2792B		%vreg726<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg726
2800B		%vreg725<def> = LDRWui %vreg726, 6; mem:LD4[%rNToGo] GPR32:%vreg725 GPR64common:%vreg726
2816B		CBNZW %vreg725, <BB#18>; GPR32:%vreg725
	    Successors according to CFG: BB#18 BB#15

2832B	BB#15: derived from LLVM BB %if.then.59
	    Predecessors according to CFG: BB#14
2880B		%vreg831<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg831
2896B		%vreg830<def> = LDRSWui %vreg831, 7; mem:LD4[%rTPos] GPR64:%vreg830 GPR64common:%vreg831
2904B		%vreg820<def> = ADRP <ga:@BZ2_rNums>[TF=1]; GPR64common:%vreg820
2912B		%vreg823<def> = MOVi64imm 4; GPR64:%vreg823
2920B		%vreg821<def> = ADDXri %vreg820, <ga:@BZ2_rNums>[TF=34], 0; GPR64common:%vreg821,%vreg820
2928B		%vreg824<def> = MADDXrrr %vreg830, %vreg823, %XZR; GPR64:%vreg824,%vreg830,%vreg823
2944B		%vreg825<def> = ADDXrr %vreg821, %vreg824; GPR64common:%vreg825,%vreg821 GPR64:%vreg824
2960B		%vreg819<def> = LDRWui %vreg825, 0; mem:LD4[%arrayidx61] GPR32:%vreg819 GPR64common:%vreg825
2976B		%vreg817<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg817
2992B		STRWui %vreg819, %vreg817, 6; mem:ST4[%rNToGo62] GPR32:%vreg819 GPR64common:%vreg817
3008B		%vreg814<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg814
3024B		%vreg813<def> = LDRWui %vreg814, 7; mem:LD4[%rTPos63] GPR32common:%vreg813 GPR64common:%vreg814
3040B		%vreg812<def> = ADDWri %vreg813, 1, 0; GPR32common:%vreg812,%vreg813
3056B		STRWui %vreg812, %vreg814, 7; mem:ST4[%rTPos63] GPR32common:%vreg812 GPR64common:%vreg814
3072B		%vreg808<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg808
3088B		%vreg807<def> = LDRWui %vreg808, 7; mem:LD4[%rTPos65] GPR32common:%vreg807 GPR64common:%vreg808
3104B		%WZR<def> = SUBSWri %vreg807, 512, 0, %NZCV<imp-def>; GPR32common:%vreg807
3120B		Bcc 1, <BB#17>, %NZCV<imp-use>
	    Successors according to CFG: BB#17 BB#16

3136B	BB#16: derived from LLVM BB %if.then.68
	    Predecessors according to CFG: BB#15
3152B		%vreg833<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg833
3168B		STRWui %WZR, %vreg833, 7; mem:ST4[%rTPos69] GPR64common:%vreg833
	    Successors according to CFG: BB#17

3184B	BB#17: derived from LLVM BB %if.end.70
	    Predecessors according to CFG: BB#15 BB#16
3200B		B <BB#18>
	    Successors according to CFG: BB#18

3216B	BB#18: derived from LLVM BB %if.end.71
	    Predecessors according to CFG: BB#14 BB#17
3224B		%vreg863<def> = COPY %WZR; GPR32:%vreg863
3264B		%vreg873<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg873
3280B		%vreg872<def> = LDRWui %vreg873, 6; mem:LD4[%rNToGo72] GPR32common:%vreg872 GPR64common:%vreg873
3296B		%vreg871<def> = SUBWri %vreg872, 1, 0; GPR32common:%vreg871,%vreg872
3312B		STRWui %vreg871, %vreg873, 6; mem:ST4[%rNToGo72] GPR32common:%vreg871 GPR64common:%vreg873
3328B		%vreg867<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg867
3344B		%vreg866<def> = LDRWui %vreg867, 6; mem:LD4[%rNToGo74] GPR32common:%vreg866 GPR64common:%vreg867
3392B		%vreg860<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg860
3400B		%vreg862<def> = MOVi32imm 1; GPR32:%vreg862
3408B		%WZR<def> = SUBSWri %vreg866, 1, 0, %NZCV<imp-def>; GPR32common:%vreg866
3416B		%vreg864<def> = CSELWr %vreg862, %vreg863, 0, %NZCV<imp-use>; GPR32:%vreg864,%vreg862,%vreg863
3424B		%vreg854<def> = EORWrr %vreg860, %vreg864; GPR32:%vreg854,%vreg860,%vreg864
3440B		STRBBui %vreg854, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg854
3456B		%vreg851<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg851
3472B		%vreg850<def> = LDRWui %vreg851, 273; mem:LD4[%nblock_used80] GPR32common:%vreg850 GPR64common:%vreg851
3488B		%vreg849<def> = ADDWri %vreg850, 1, 0; GPR32common:%vreg849,%vreg850
3504B		STRWui %vreg849, %vreg851, 273; mem:ST4[%nblock_used80] GPR32common:%vreg849 GPR64common:%vreg851
3552B		%vreg842<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg842
3560B		%vreg845<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg845
3568B		%vreg839<def> = MOVi64imm 64080; GPR64:%vreg839
3584B		%vreg840<def> = ADDXrr %vreg842, %vreg839; GPR64common:%vreg840 GPR64:%vreg842,%vreg839
3600B		%vreg841<def> = LDRWui %vreg840, 0; mem:LD4[%save_nblock83] GPR32common:%vreg841 GPR64common:%vreg840
3608B		%vreg844<def> = LDRWui %vreg845, 273; mem:LD4[%nblock_used82] GPR32:%vreg844 GPR64common:%vreg845
3616B		%vreg837<def> = ADDWri %vreg841, 1, 0; GPR32common:%vreg837,%vreg841
3632B		%WZR<def> = SUBSWrr %vreg844, %vreg837, %NZCV<imp-def>; GPR32:%vreg844 GPR32common:%vreg837
3648B		Bcc 1, <BB#20>, %NZCV<imp-use>
	    Successors according to CFG: BB#20 BB#19

3664B	BB#19: derived from LLVM BB %if.then.87
	    Predecessors according to CFG: BB#18
3680B		B <BB#2>
	    Successors according to CFG: BB#2

3696B	BB#20: derived from LLVM BB %if.end.88
	    Predecessors according to CFG: BB#18
3728B		%vreg878<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg878
3736B		%vreg881<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg881
3744B		%vreg877<def> = LDRWui %vreg878, 16; mem:LD4[%k090] GPR32:%vreg877 GPR64common:%vreg878
3760B		%WZR<def> = SUBSWrr %vreg881, %vreg877, %NZCV<imp-def>; GPR32:%vreg881,%vreg877
3776B		Bcc 0, <BB#22>, %NZCV<imp-use>
	    Successors according to CFG: BB#22 BB#21

3792B	BB#21: derived from LLVM BB %if.then.93
	    Predecessors according to CFG: BB#20
3808B		%vreg1463<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg1463
3824B		%vreg1460<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1460
3840B		STRWui %vreg1463, %vreg1460, 16; mem:ST4[%k095] GPR32:%vreg1463 GPR64common:%vreg1460
3856B		B <BB#2>
	    Successors according to CFG: BB#2

3872B	BB#22: derived from LLVM BB %if.end.96
	    Predecessors according to CFG: BB#20
3904B		%vreg955<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg955
3912B		%vreg953<def> = MOVi32imm 2; GPR32:%vreg953
3920B		STRWui %vreg953, %vreg955, 4; mem:ST4[%state_out_len97] GPR32:%vreg953 GPR64common:%vreg955
3936B		%vreg952<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg952
3968B		%vreg949<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg949
3976B		%vreg951<def> = LDRWui %vreg952, 15; mem:LD4[%tPos98] GPR32:%vreg951 GPR64common:%vreg952
3984B		%vreg948<def> = ADDXri %vreg949, 1096, 0; GPR64sp:%vreg948 GPR64common:%vreg949
4000B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4016B		%W0<def> = COPY %vreg951; GPR32:%vreg951
4032B		%X1<def> = COPY %vreg948; GPR64sp:%vreg948
4048B		BL <ga:@BZ2_indexIntoF>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use,kill>, %W0<imp-def>
4064B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4080B		%vreg942<def> = COPY %W0; GPR32:%vreg942
4096B		%vreg897<def> = MOVi32imm 4; GPR32:%vreg897
4112B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4128B		STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
4144B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4176B		STRBBui %vreg942, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg942
4192B		%vreg939<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg939
4240B		%vreg932<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg932
4248B		%vreg938:sub_32<def,read-undef> = LDRWui %vreg939, 15; mem:LD4[%tPos103] GPR64:%vreg938 GPR64common:%vreg939
4272B		%vreg927<def> = MOVi64imm 2; GPR64:%vreg927
4336B		%vreg920<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg920
4340B		%vreg931<def> = LDRXui %vreg932, 395; mem:LD8[%ll16105] GPR64:%vreg931 GPR64common:%vreg932
4344B		%vreg928<def> = MADDXrrr %vreg938, %vreg927, %XZR; GPR64:%vreg928,%vreg938,%vreg927
4416B		%vreg912<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg912
4420B		%vreg919<def> = LDRWui %vreg920, 15; mem:LD4[%tPos108] GPR32:%vreg919 GPR64common:%vreg920
4424B		%vreg929<def> = ADDXrr %vreg931, %vreg928; GPR64common:%vreg929 GPR64:%vreg931,%vreg928
4480B		%vreg902<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg902
4488B		%vreg911<def> = LDRXui %vreg912, 396; mem:LD8[%ll4111] GPR64:%vreg911 GPR64common:%vreg912
4496B		%vreg914:sub_32<def,read-undef> = UBFMWri %vreg919, 1, 31; GPR64:%vreg914 GPR32:%vreg919
4504B		%vreg915<def> = UBFMXri %vreg914, 0, 31; GPR64:%vreg915,%vreg914
4512B		%vreg901<def> = LDRWui %vreg902, 15; mem:LD4[%tPos114] GPR32:%vreg901 GPR64common:%vreg902
4520B		%vreg909<def> = ADDXrr %vreg911, %vreg915; GPR64common:%vreg909 GPR64:%vreg911,%vreg915
4528B		%vreg906<def> = LDRBBui %vreg909, 0; mem:LD1[%arrayidx112] GPR32:%vreg906 GPR64common:%vreg909
4536B		%vreg924<def> = LDRHHui %vreg929, 0; mem:LD2[%arrayidx106] GPR32:%vreg924 GPR64common:%vreg929
4544B		%vreg899<def> = ANDWrs %vreg897, %vreg901, 2; GPR32:%vreg899,%vreg897,%vreg901
4576B		%vreg888<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg888
4584B		%vreg896<def> = LSRVWr %vreg906, %vreg899; GPR32:%vreg896,%vreg906,%vreg899
4592B		%vreg893<def> = ANDWri %vreg896, 3; GPR32common:%vreg893 GPR32:%vreg896
4600B		%vreg891<def> = ORRWrs %vreg924, %vreg893, 16; GPR32:%vreg891,%vreg924 GPR32common:%vreg893
4608B		STRWui %vreg891, %vreg888, 15; mem:ST4[%tPos121] GPR32:%vreg891 GPR64common:%vreg888
4616B		%vreg885<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg885
4624B		%vreg884<def> = LDRWui %vreg885, 6; mem:LD4[%rNToGo122] GPR32:%vreg884 GPR64common:%vreg885
4640B		CBNZW %vreg884, <BB#26>; GPR32:%vreg884
	    Successors according to CFG: BB#26 BB#23

4656B	BB#23: derived from LLVM BB %if.then.125
	    Predecessors according to CFG: BB#22
4704B		%vreg982<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg982
4720B		%vreg981<def> = LDRSWui %vreg982, 7; mem:LD4[%rTPos126] GPR64:%vreg981 GPR64common:%vreg982
4728B		%vreg971<def> = ADRP <ga:@BZ2_rNums>[TF=1]; GPR64common:%vreg971
4736B		%vreg974<def> = MOVi64imm 4; GPR64:%vreg974
4744B		%vreg972<def> = ADDXri %vreg971, <ga:@BZ2_rNums>[TF=34], 0; GPR64common:%vreg972,%vreg971
4752B		%vreg975<def> = MADDXrrr %vreg981, %vreg974, %XZR; GPR64:%vreg975,%vreg981,%vreg974
4768B		%vreg976<def> = ADDXrr %vreg972, %vreg975; GPR64common:%vreg976,%vreg972 GPR64:%vreg975
4784B		%vreg970<def> = LDRWui %vreg976, 0; mem:LD4[%arrayidx128] GPR32:%vreg970 GPR64common:%vreg976
4800B		%vreg968<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg968
4816B		STRWui %vreg970, %vreg968, 6; mem:ST4[%rNToGo129] GPR32:%vreg970 GPR64common:%vreg968
4832B		%vreg965<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg965
4848B		%vreg964<def> = LDRWui %vreg965, 7; mem:LD4[%rTPos130] GPR32common:%vreg964 GPR64common:%vreg965
4864B		%vreg963<def> = ADDWri %vreg964, 1, 0; GPR32common:%vreg963,%vreg964
4880B		STRWui %vreg963, %vreg965, 7; mem:ST4[%rTPos130] GPR32common:%vreg963 GPR64common:%vreg965
4896B		%vreg959<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg959
4912B		%vreg958<def> = LDRWui %vreg959, 7; mem:LD4[%rTPos132] GPR32common:%vreg958 GPR64common:%vreg959
4928B		%WZR<def> = SUBSWri %vreg958, 512, 0, %NZCV<imp-def>; GPR32common:%vreg958
4944B		Bcc 1, <BB#25>, %NZCV<imp-use>
	    Successors according to CFG: BB#25 BB#24

4960B	BB#24: derived from LLVM BB %if.then.135
	    Predecessors according to CFG: BB#23
4976B		%vreg984<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg984
4992B		STRWui %WZR, %vreg984, 7; mem:ST4[%rTPos136] GPR64common:%vreg984
	    Successors according to CFG: BB#25

5008B	BB#25: derived from LLVM BB %if.end.137
	    Predecessors according to CFG: BB#23 BB#24
5024B		B <BB#26>
	    Successors according to CFG: BB#26

5040B	BB#26: derived from LLVM BB %if.end.138
	    Predecessors according to CFG: BB#22 BB#25
5048B		%vreg1014<def> = COPY %WZR; GPR32:%vreg1014
5088B		%vreg1024<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1024
5104B		%vreg1023<def> = LDRWui %vreg1024, 6; mem:LD4[%rNToGo139] GPR32common:%vreg1023 GPR64common:%vreg1024
5120B		%vreg1022<def> = SUBWri %vreg1023, 1, 0; GPR32common:%vreg1022,%vreg1023
5136B		STRWui %vreg1022, %vreg1024, 6; mem:ST4[%rNToGo139] GPR32common:%vreg1022 GPR64common:%vreg1024
5152B		%vreg1018<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1018
5168B		%vreg1017<def> = LDRWui %vreg1018, 6; mem:LD4[%rNToGo141] GPR32common:%vreg1017 GPR64common:%vreg1018
5216B		%vreg1011<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg1011
5224B		%vreg1013<def> = MOVi32imm 1; GPR32:%vreg1013
5232B		%WZR<def> = SUBSWri %vreg1017, 1, 0, %NZCV<imp-def>; GPR32common:%vreg1017
5240B		%vreg1015<def> = CSELWr %vreg1013, %vreg1014, 0, %NZCV<imp-use>; GPR32:%vreg1015,%vreg1013,%vreg1014
5248B		%vreg1005<def> = EORWrr %vreg1011, %vreg1015; GPR32:%vreg1005,%vreg1011,%vreg1015
5264B		STRBBui %vreg1005, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg1005
5280B		%vreg1002<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1002
5296B		%vreg1001<def> = LDRWui %vreg1002, 273; mem:LD4[%nblock_used148] GPR32common:%vreg1001 GPR64common:%vreg1002
5312B		%vreg1000<def> = ADDWri %vreg1001, 1, 0; GPR32common:%vreg1000,%vreg1001
5328B		STRWui %vreg1000, %vreg1002, 273; mem:ST4[%nblock_used148] GPR32common:%vreg1000 GPR64common:%vreg1002
5376B		%vreg993<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg993
5384B		%vreg996<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg996
5392B		%vreg990<def> = MOVi64imm 64080; GPR64:%vreg990
5408B		%vreg991<def> = ADDXrr %vreg993, %vreg990; GPR64common:%vreg991 GPR64:%vreg993,%vreg990
5424B		%vreg992<def> = LDRWui %vreg991, 0; mem:LD4[%save_nblock151] GPR32common:%vreg992 GPR64common:%vreg991
5432B		%vreg995<def> = LDRWui %vreg996, 273; mem:LD4[%nblock_used150] GPR32:%vreg995 GPR64common:%vreg996
5440B		%vreg988<def> = ADDWri %vreg992, 1, 0; GPR32common:%vreg988,%vreg992
5456B		%WZR<def> = SUBSWrr %vreg995, %vreg988, %NZCV<imp-def>; GPR32:%vreg995 GPR32common:%vreg988
5472B		Bcc 1, <BB#28>, %NZCV<imp-use>
	    Successors according to CFG: BB#28 BB#27

5488B	BB#27: derived from LLVM BB %if.then.155
	    Predecessors according to CFG: BB#26
5504B		B <BB#2>
	    Successors according to CFG: BB#2

5520B	BB#28: derived from LLVM BB %if.end.156
	    Predecessors according to CFG: BB#26
5552B		%vreg1029<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1029
5560B		%vreg1032<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg1032
5568B		%vreg1028<def> = LDRWui %vreg1029, 16; mem:LD4[%k0158] GPR32:%vreg1028 GPR64common:%vreg1029
5584B		%WZR<def> = SUBSWrr %vreg1032, %vreg1028, %NZCV<imp-def>; GPR32:%vreg1032,%vreg1028
5600B		Bcc 0, <BB#30>, %NZCV<imp-use>
	    Successors according to CFG: BB#30 BB#29

5616B	BB#29: derived from LLVM BB %if.then.161
	    Predecessors according to CFG: BB#28
5632B		%vreg1457<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg1457
5648B		%vreg1454<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1454
5664B		STRWui %vreg1457, %vreg1454, 16; mem:ST4[%k0163] GPR32:%vreg1457 GPR64common:%vreg1454
5680B		B <BB#2>
	    Successors according to CFG: BB#2

5696B	BB#30: derived from LLVM BB %if.end.164
	    Predecessors according to CFG: BB#28
5728B		%vreg1106<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1106
5736B		%vreg1104<def> = MOVi32imm 3; GPR32:%vreg1104
5744B		STRWui %vreg1104, %vreg1106, 4; mem:ST4[%state_out_len165] GPR32:%vreg1104 GPR64common:%vreg1106
5760B		%vreg1103<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1103
5792B		%vreg1100<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1100
5800B		%vreg1102<def> = LDRWui %vreg1103, 15; mem:LD4[%tPos166] GPR32:%vreg1102 GPR64common:%vreg1103
5808B		%vreg1099<def> = ADDXri %vreg1100, 1096, 0; GPR64sp:%vreg1099 GPR64common:%vreg1100
5824B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5840B		%W0<def> = COPY %vreg1102; GPR32:%vreg1102
5856B		%X1<def> = COPY %vreg1099; GPR64sp:%vreg1099
5872B		BL <ga:@BZ2_indexIntoF>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use,kill>, %W0<imp-def>
5888B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5904B		%vreg1093<def> = COPY %W0; GPR32:%vreg1093
5920B		%vreg1048<def> = MOVi32imm 4; GPR32:%vreg1048
5936B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5952B		STACKMAP 3, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
5968B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
6000B		STRBBui %vreg1093, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg1093
6016B		%vreg1090<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1090
6064B		%vreg1083<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1083
6072B		%vreg1089:sub_32<def,read-undef> = LDRWui %vreg1090, 15; mem:LD4[%tPos171] GPR64:%vreg1089 GPR64common:%vreg1090
6096B		%vreg1078<def> = MOVi64imm 2; GPR64:%vreg1078
6160B		%vreg1071<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1071
6164B		%vreg1082<def> = LDRXui %vreg1083, 395; mem:LD8[%ll16173] GPR64:%vreg1082 GPR64common:%vreg1083
6168B		%vreg1079<def> = MADDXrrr %vreg1089, %vreg1078, %XZR; GPR64:%vreg1079,%vreg1089,%vreg1078
6240B		%vreg1063<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1063
6244B		%vreg1070<def> = LDRWui %vreg1071, 15; mem:LD4[%tPos176] GPR32:%vreg1070 GPR64common:%vreg1071
6248B		%vreg1080<def> = ADDXrr %vreg1082, %vreg1079; GPR64common:%vreg1080 GPR64:%vreg1082,%vreg1079
6304B		%vreg1053<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1053
6312B		%vreg1062<def> = LDRXui %vreg1063, 396; mem:LD8[%ll4179] GPR64:%vreg1062 GPR64common:%vreg1063
6320B		%vreg1065:sub_32<def,read-undef> = UBFMWri %vreg1070, 1, 31; GPR64:%vreg1065 GPR32:%vreg1070
6328B		%vreg1066<def> = UBFMXri %vreg1065, 0, 31; GPR64:%vreg1066,%vreg1065
6336B		%vreg1052<def> = LDRWui %vreg1053, 15; mem:LD4[%tPos182] GPR32:%vreg1052 GPR64common:%vreg1053
6344B		%vreg1060<def> = ADDXrr %vreg1062, %vreg1066; GPR64common:%vreg1060 GPR64:%vreg1062,%vreg1066
6352B		%vreg1057<def> = LDRBBui %vreg1060, 0; mem:LD1[%arrayidx180] GPR32:%vreg1057 GPR64common:%vreg1060
6360B		%vreg1075<def> = LDRHHui %vreg1080, 0; mem:LD2[%arrayidx174] GPR32:%vreg1075 GPR64common:%vreg1080
6368B		%vreg1050<def> = ANDWrs %vreg1048, %vreg1052, 2; GPR32:%vreg1050,%vreg1048,%vreg1052
6400B		%vreg1039<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1039
6408B		%vreg1047<def> = LSRVWr %vreg1057, %vreg1050; GPR32:%vreg1047,%vreg1057,%vreg1050
6416B		%vreg1044<def> = ANDWri %vreg1047, 3; GPR32common:%vreg1044 GPR32:%vreg1047
6424B		%vreg1042<def> = ORRWrs %vreg1075, %vreg1044, 16; GPR32:%vreg1042,%vreg1075 GPR32common:%vreg1044
6432B		STRWui %vreg1042, %vreg1039, 15; mem:ST4[%tPos189] GPR32:%vreg1042 GPR64common:%vreg1039
6440B		%vreg1036<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1036
6448B		%vreg1035<def> = LDRWui %vreg1036, 6; mem:LD4[%rNToGo190] GPR32:%vreg1035 GPR64common:%vreg1036
6464B		CBNZW %vreg1035, <BB#34>; GPR32:%vreg1035
	    Successors according to CFG: BB#34 BB#31

6480B	BB#31: derived from LLVM BB %if.then.193
	    Predecessors according to CFG: BB#30
6528B		%vreg1133<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1133
6544B		%vreg1132<def> = LDRSWui %vreg1133, 7; mem:LD4[%rTPos194] GPR64:%vreg1132 GPR64common:%vreg1133
6552B		%vreg1122<def> = ADRP <ga:@BZ2_rNums>[TF=1]; GPR64common:%vreg1122
6560B		%vreg1125<def> = MOVi64imm 4; GPR64:%vreg1125
6568B		%vreg1123<def> = ADDXri %vreg1122, <ga:@BZ2_rNums>[TF=34], 0; GPR64common:%vreg1123,%vreg1122
6576B		%vreg1126<def> = MADDXrrr %vreg1132, %vreg1125, %XZR; GPR64:%vreg1126,%vreg1132,%vreg1125
6592B		%vreg1127<def> = ADDXrr %vreg1123, %vreg1126; GPR64common:%vreg1127,%vreg1123 GPR64:%vreg1126
6608B		%vreg1121<def> = LDRWui %vreg1127, 0; mem:LD4[%arrayidx196] GPR32:%vreg1121 GPR64common:%vreg1127
6624B		%vreg1119<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1119
6640B		STRWui %vreg1121, %vreg1119, 6; mem:ST4[%rNToGo197] GPR32:%vreg1121 GPR64common:%vreg1119
6656B		%vreg1116<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1116
6672B		%vreg1115<def> = LDRWui %vreg1116, 7; mem:LD4[%rTPos198] GPR32common:%vreg1115 GPR64common:%vreg1116
6688B		%vreg1114<def> = ADDWri %vreg1115, 1, 0; GPR32common:%vreg1114,%vreg1115
6704B		STRWui %vreg1114, %vreg1116, 7; mem:ST4[%rTPos198] GPR32common:%vreg1114 GPR64common:%vreg1116
6720B		%vreg1110<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1110
6736B		%vreg1109<def> = LDRWui %vreg1110, 7; mem:LD4[%rTPos200] GPR32common:%vreg1109 GPR64common:%vreg1110
6752B		%WZR<def> = SUBSWri %vreg1109, 512, 0, %NZCV<imp-def>; GPR32common:%vreg1109
6768B		Bcc 1, <BB#33>, %NZCV<imp-use>
	    Successors according to CFG: BB#33 BB#32

6784B	BB#32: derived from LLVM BB %if.then.203
	    Predecessors according to CFG: BB#31
6800B		%vreg1135<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1135
6816B		STRWui %WZR, %vreg1135, 7; mem:ST4[%rTPos204] GPR64common:%vreg1135
	    Successors according to CFG: BB#33

6832B	BB#33: derived from LLVM BB %if.end.205
	    Predecessors according to CFG: BB#31 BB#32
6848B		B <BB#34>
	    Successors according to CFG: BB#34

6864B	BB#34: derived from LLVM BB %if.end.206
	    Predecessors according to CFG: BB#30 BB#33
6872B		%vreg1165<def> = COPY %WZR; GPR32:%vreg1165
6912B		%vreg1175<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1175
6928B		%vreg1174<def> = LDRWui %vreg1175, 6; mem:LD4[%rNToGo207] GPR32common:%vreg1174 GPR64common:%vreg1175
6944B		%vreg1173<def> = SUBWri %vreg1174, 1, 0; GPR32common:%vreg1173,%vreg1174
6960B		STRWui %vreg1173, %vreg1175, 6; mem:ST4[%rNToGo207] GPR32common:%vreg1173 GPR64common:%vreg1175
6976B		%vreg1169<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1169
6992B		%vreg1168<def> = LDRWui %vreg1169, 6; mem:LD4[%rNToGo209] GPR32common:%vreg1168 GPR64common:%vreg1169
7040B		%vreg1162<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg1162
7048B		%vreg1164<def> = MOVi32imm 1; GPR32:%vreg1164
7056B		%WZR<def> = SUBSWri %vreg1168, 1, 0, %NZCV<imp-def>; GPR32common:%vreg1168
7064B		%vreg1166<def> = CSELWr %vreg1164, %vreg1165, 0, %NZCV<imp-use>; GPR32:%vreg1166,%vreg1164,%vreg1165
7072B		%vreg1156<def> = EORWrr %vreg1162, %vreg1166; GPR32:%vreg1156,%vreg1162,%vreg1166
7088B		STRBBui %vreg1156, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg1156
7104B		%vreg1153<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1153
7120B		%vreg1152<def> = LDRWui %vreg1153, 273; mem:LD4[%nblock_used216] GPR32common:%vreg1152 GPR64common:%vreg1153
7136B		%vreg1151<def> = ADDWri %vreg1152, 1, 0; GPR32common:%vreg1151,%vreg1152
7152B		STRWui %vreg1151, %vreg1153, 273; mem:ST4[%nblock_used216] GPR32common:%vreg1151 GPR64common:%vreg1153
7200B		%vreg1144<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg1144
7208B		%vreg1147<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1147
7216B		%vreg1141<def> = MOVi64imm 64080; GPR64:%vreg1141
7232B		%vreg1142<def> = ADDXrr %vreg1144, %vreg1141; GPR64common:%vreg1142 GPR64:%vreg1144,%vreg1141
7248B		%vreg1143<def> = LDRWui %vreg1142, 0; mem:LD4[%save_nblock219] GPR32common:%vreg1143 GPR64common:%vreg1142
7256B		%vreg1146<def> = LDRWui %vreg1147, 273; mem:LD4[%nblock_used218] GPR32:%vreg1146 GPR64common:%vreg1147
7264B		%vreg1139<def> = ADDWri %vreg1143, 1, 0; GPR32common:%vreg1139,%vreg1143
7280B		%WZR<def> = SUBSWrr %vreg1146, %vreg1139, %NZCV<imp-def>; GPR32:%vreg1146 GPR32common:%vreg1139
7296B		Bcc 1, <BB#36>, %NZCV<imp-use>
	    Successors according to CFG: BB#36 BB#35

7312B	BB#35: derived from LLVM BB %if.then.223
	    Predecessors according to CFG: BB#34
7328B		B <BB#2>
	    Successors according to CFG: BB#2

7344B	BB#36: derived from LLVM BB %if.end.224
	    Predecessors according to CFG: BB#34
7376B		%vreg1180<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1180
7384B		%vreg1183<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg1183
7392B		%vreg1179<def> = LDRWui %vreg1180, 16; mem:LD4[%k0226] GPR32:%vreg1179 GPR64common:%vreg1180
7408B		%WZR<def> = SUBSWrr %vreg1183, %vreg1179, %NZCV<imp-def>; GPR32:%vreg1183,%vreg1179
7424B		Bcc 0, <BB#38>, %NZCV<imp-use>
	    Successors according to CFG: BB#38 BB#37

7440B	BB#37: derived from LLVM BB %if.then.229
	    Predecessors according to CFG: BB#36
7456B		%vreg1451<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg1451
7472B		%vreg1448<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1448
7488B		STRWui %vreg1451, %vreg1448, 16; mem:ST4[%k0231] GPR32:%vreg1451 GPR64common:%vreg1448
7504B		B <BB#2>
	    Successors according to CFG: BB#2

7520B	BB#38: derived from LLVM BB %if.end.232
	    Predecessors according to CFG: BB#36
7536B		%vreg1254<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1254
7568B		%vreg1251<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1251
7576B		%vreg1253<def> = LDRWui %vreg1254, 15; mem:LD4[%tPos233] GPR32:%vreg1253 GPR64common:%vreg1254
7584B		%vreg1250<def> = ADDXri %vreg1251, 1096, 0; GPR64sp:%vreg1250 GPR64common:%vreg1251
7600B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
7616B		%W0<def> = COPY %vreg1253; GPR32:%vreg1253
7632B		%X1<def> = COPY %vreg1250; GPR64sp:%vreg1250
7648B		BL <ga:@BZ2_indexIntoF>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use,kill>, %W0<imp-def>
7664B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
7680B		%vreg1244<def> = COPY %W0; GPR32:%vreg1244
7696B		%vreg1199<def> = MOVi32imm 4; GPR32:%vreg1199
7712B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
7728B		STACKMAP 4, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
7744B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
7776B		STRBBui %vreg1244, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg1244
7792B		%vreg1241<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1241
7840B		%vreg1234<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1234
7848B		%vreg1240:sub_32<def,read-undef> = LDRWui %vreg1241, 15; mem:LD4[%tPos238] GPR64:%vreg1240 GPR64common:%vreg1241
7872B		%vreg1229<def> = MOVi64imm 2; GPR64:%vreg1229
7936B		%vreg1222<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1222
7940B		%vreg1233<def> = LDRXui %vreg1234, 395; mem:LD8[%ll16240] GPR64:%vreg1233 GPR64common:%vreg1234
7944B		%vreg1230<def> = MADDXrrr %vreg1240, %vreg1229, %XZR; GPR64:%vreg1230,%vreg1240,%vreg1229
8016B		%vreg1214<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1214
8020B		%vreg1221<def> = LDRWui %vreg1222, 15; mem:LD4[%tPos243] GPR32:%vreg1221 GPR64common:%vreg1222
8024B		%vreg1231<def> = ADDXrr %vreg1233, %vreg1230; GPR64common:%vreg1231 GPR64:%vreg1233,%vreg1230
8080B		%vreg1204<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1204
8088B		%vreg1213<def> = LDRXui %vreg1214, 396; mem:LD8[%ll4246] GPR64:%vreg1213 GPR64common:%vreg1214
8096B		%vreg1216:sub_32<def,read-undef> = UBFMWri %vreg1221, 1, 31; GPR64:%vreg1216 GPR32:%vreg1221
8104B		%vreg1217<def> = UBFMXri %vreg1216, 0, 31; GPR64:%vreg1217,%vreg1216
8112B		%vreg1203<def> = LDRWui %vreg1204, 15; mem:LD4[%tPos249] GPR32:%vreg1203 GPR64common:%vreg1204
8120B		%vreg1211<def> = ADDXrr %vreg1213, %vreg1217; GPR64common:%vreg1211 GPR64:%vreg1213,%vreg1217
8128B		%vreg1208<def> = LDRBBui %vreg1211, 0; mem:LD1[%arrayidx247] GPR32:%vreg1208 GPR64common:%vreg1211
8136B		%vreg1226<def> = LDRHHui %vreg1231, 0; mem:LD2[%arrayidx241] GPR32:%vreg1226 GPR64common:%vreg1231
8144B		%vreg1201<def> = ANDWrs %vreg1199, %vreg1203, 2; GPR32:%vreg1201,%vreg1199,%vreg1203
8176B		%vreg1190<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1190
8184B		%vreg1198<def> = LSRVWr %vreg1208, %vreg1201; GPR32:%vreg1198,%vreg1208,%vreg1201
8192B		%vreg1195<def> = ANDWri %vreg1198, 3; GPR32common:%vreg1195 GPR32:%vreg1198
8200B		%vreg1193<def> = ORRWrs %vreg1226, %vreg1195, 16; GPR32:%vreg1193,%vreg1226 GPR32common:%vreg1195
8208B		STRWui %vreg1193, %vreg1190, 15; mem:ST4[%tPos256] GPR32:%vreg1193 GPR64common:%vreg1190
8216B		%vreg1187<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1187
8224B		%vreg1186<def> = LDRWui %vreg1187, 6; mem:LD4[%rNToGo257] GPR32:%vreg1186 GPR64common:%vreg1187
8240B		CBNZW %vreg1186, <BB#42>; GPR32:%vreg1186
	    Successors according to CFG: BB#42 BB#39

8256B	BB#39: derived from LLVM BB %if.then.260
	    Predecessors according to CFG: BB#38
8304B		%vreg1281<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1281
8320B		%vreg1280<def> = LDRSWui %vreg1281, 7; mem:LD4[%rTPos261] GPR64:%vreg1280 GPR64common:%vreg1281
8328B		%vreg1270<def> = ADRP <ga:@BZ2_rNums>[TF=1]; GPR64common:%vreg1270
8336B		%vreg1273<def> = MOVi64imm 4; GPR64:%vreg1273
8344B		%vreg1271<def> = ADDXri %vreg1270, <ga:@BZ2_rNums>[TF=34], 0; GPR64common:%vreg1271,%vreg1270
8352B		%vreg1274<def> = MADDXrrr %vreg1280, %vreg1273, %XZR; GPR64:%vreg1274,%vreg1280,%vreg1273
8368B		%vreg1275<def> = ADDXrr %vreg1271, %vreg1274; GPR64common:%vreg1275,%vreg1271 GPR64:%vreg1274
8384B		%vreg1269<def> = LDRWui %vreg1275, 0; mem:LD4[%arrayidx263] GPR32:%vreg1269 GPR64common:%vreg1275
8400B		%vreg1267<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1267
8416B		STRWui %vreg1269, %vreg1267, 6; mem:ST4[%rNToGo264] GPR32:%vreg1269 GPR64common:%vreg1267
8432B		%vreg1264<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1264
8448B		%vreg1263<def> = LDRWui %vreg1264, 7; mem:LD4[%rTPos265] GPR32common:%vreg1263 GPR64common:%vreg1264
8464B		%vreg1262<def> = ADDWri %vreg1263, 1, 0; GPR32common:%vreg1262,%vreg1263
8480B		STRWui %vreg1262, %vreg1264, 7; mem:ST4[%rTPos265] GPR32common:%vreg1262 GPR64common:%vreg1264
8496B		%vreg1258<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1258
8512B		%vreg1257<def> = LDRWui %vreg1258, 7; mem:LD4[%rTPos267] GPR32common:%vreg1257 GPR64common:%vreg1258
8528B		%WZR<def> = SUBSWri %vreg1257, 512, 0, %NZCV<imp-def>; GPR32common:%vreg1257
8544B		Bcc 1, <BB#41>, %NZCV<imp-use>
	    Successors according to CFG: BB#41 BB#40

8560B	BB#40: derived from LLVM BB %if.then.270
	    Predecessors according to CFG: BB#39
8576B		%vreg1283<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1283
8592B		STRWui %WZR, %vreg1283, 7; mem:ST4[%rTPos271] GPR64common:%vreg1283
	    Successors according to CFG: BB#41

8608B	BB#41: derived from LLVM BB %if.end.272
	    Predecessors according to CFG: BB#39 BB#40
8624B		B <BB#42>
	    Successors according to CFG: BB#42

8640B	BB#42: derived from LLVM BB %if.end.273
	    Predecessors according to CFG: BB#38 BB#41
8648B		%vreg1380<def> = COPY %WZR; GPR32:%vreg1380
8688B		%vreg1390<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1390
8704B		%vreg1389<def> = LDRWui %vreg1390, 6; mem:LD4[%rNToGo274] GPR32common:%vreg1389 GPR64common:%vreg1390
8720B		%vreg1388<def> = SUBWri %vreg1389, 1, 0; GPR32common:%vreg1388,%vreg1389
8736B		STRWui %vreg1388, %vreg1390, 6; mem:ST4[%rNToGo274] GPR32common:%vreg1388 GPR64common:%vreg1390
8752B		%vreg1384<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1384
8768B		%vreg1383<def> = LDRWui %vreg1384, 6; mem:LD4[%rNToGo276] GPR32common:%vreg1383 GPR64common:%vreg1384
8816B		%vreg1377<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg1377
8824B		%vreg1379<def> = MOVi32imm 1; GPR32:%vreg1379
8832B		%WZR<def> = SUBSWri %vreg1383, 1, 0, %NZCV<imp-def>; GPR32common:%vreg1383
8840B		%vreg1381<def> = CSELWr %vreg1379, %vreg1380, 0, %NZCV<imp-use>; GPR32:%vreg1381,%vreg1379,%vreg1380
8848B		%vreg1371<def> = EORWrr %vreg1377, %vreg1381; GPR32:%vreg1371,%vreg1377,%vreg1381
8864B		STRBBui %vreg1371, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg1371
8880B		%vreg1368<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1368
8896B		%vreg1367<def> = LDRWui %vreg1368, 273; mem:LD4[%nblock_used283] GPR32common:%vreg1367 GPR64common:%vreg1368
8912B		%vreg1366<def> = ADDWri %vreg1367, 1, 0; GPR32common:%vreg1366,%vreg1367
8928B		STRWui %vreg1366, %vreg1368, 273; mem:ST4[%nblock_used283] GPR32common:%vreg1366 GPR64common:%vreg1368
8944B		%vreg1362<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32common:%vreg1362
8976B		%vreg1357<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1357
8984B		%vreg1359<def> = ADDWri %vreg1362, 4, 0; GPR32common:%vreg1359,%vreg1362
8992B		STRWui %vreg1359, %vreg1357, 4; mem:ST4[%state_out_len287] GPR32common:%vreg1359 GPR64common:%vreg1357
9008B		%vreg1354<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1354
9040B		%vreg1351<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1351
9048B		%vreg1353<def> = LDRWui %vreg1354, 15; mem:LD4[%tPos288] GPR32:%vreg1353 GPR64common:%vreg1354
9056B		%vreg1350<def> = ADDXri %vreg1351, 1096, 0; GPR64sp:%vreg1350 GPR64common:%vreg1351
9072B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
9088B		%W0<def> = COPY %vreg1353; GPR32:%vreg1353
9104B		%X1<def> = COPY %vreg1350; GPR64sp:%vreg1350
9120B		BL <ga:@BZ2_indexIntoF>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use,kill>, %W0<imp-def>
9136B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
9152B		%vreg1347<def> = COPY %W0; GPR32:%vreg1347
9168B		%vreg1299<def> = MOVi32imm 4; GPR32:%vreg1299
9184B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
9200B		STACKMAP 5, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
9216B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
9232B		%vreg1344<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1344
9248B		STRWui %vreg1347, %vreg1344, 16; mem:ST4[%k0292] GPR32:%vreg1347 GPR64common:%vreg1344
9264B		%vreg1341<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1341
9312B		%vreg1334<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1334
9320B		%vreg1340:sub_32<def,read-undef> = LDRWui %vreg1341, 15; mem:LD4[%tPos293] GPR64:%vreg1340 GPR64common:%vreg1341
9344B		%vreg1329<def> = MOVi64imm 2; GPR64:%vreg1329
9408B		%vreg1322<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1322
9412B		%vreg1333<def> = LDRXui %vreg1334, 395; mem:LD8[%ll16295] GPR64:%vreg1333 GPR64common:%vreg1334
9416B		%vreg1330<def> = MADDXrrr %vreg1340, %vreg1329, %XZR; GPR64:%vreg1330,%vreg1340,%vreg1329
9488B		%vreg1314<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1314
9492B		%vreg1321<def> = LDRWui %vreg1322, 15; mem:LD4[%tPos298] GPR32:%vreg1321 GPR64common:%vreg1322
9496B		%vreg1331<def> = ADDXrr %vreg1333, %vreg1330; GPR64common:%vreg1331 GPR64:%vreg1333,%vreg1330
9552B		%vreg1304<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1304
9560B		%vreg1313<def> = LDRXui %vreg1314, 396; mem:LD8[%ll4301] GPR64:%vreg1313 GPR64common:%vreg1314
9568B		%vreg1316:sub_32<def,read-undef> = UBFMWri %vreg1321, 1, 31; GPR64:%vreg1316 GPR32:%vreg1321
9576B		%vreg1317<def> = UBFMXri %vreg1316, 0, 31; GPR64:%vreg1317,%vreg1316
9584B		%vreg1303<def> = LDRWui %vreg1304, 15; mem:LD4[%tPos304] GPR32:%vreg1303 GPR64common:%vreg1304
9592B		%vreg1311<def> = ADDXrr %vreg1313, %vreg1317; GPR64common:%vreg1311 GPR64:%vreg1313,%vreg1317
9600B		%vreg1308<def> = LDRBBui %vreg1311, 0; mem:LD1[%arrayidx302] GPR32:%vreg1308 GPR64common:%vreg1311
9608B		%vreg1326<def> = LDRHHui %vreg1331, 0; mem:LD2[%arrayidx296] GPR32:%vreg1326 GPR64common:%vreg1331
9616B		%vreg1301<def> = ANDWrs %vreg1299, %vreg1303, 2; GPR32:%vreg1301,%vreg1299,%vreg1303
9648B		%vreg1290<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1290
9656B		%vreg1298<def> = LSRVWr %vreg1308, %vreg1301; GPR32:%vreg1298,%vreg1308,%vreg1301
9664B		%vreg1295<def> = ANDWri %vreg1298, 3; GPR32common:%vreg1295 GPR32:%vreg1298
9672B		%vreg1293<def> = ORRWrs %vreg1326, %vreg1295, 16; GPR32:%vreg1293,%vreg1326 GPR32common:%vreg1295
9680B		STRWui %vreg1293, %vreg1290, 15; mem:ST4[%tPos311] GPR32:%vreg1293 GPR64common:%vreg1290
9688B		%vreg1287<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1287
9696B		%vreg1286<def> = LDRWui %vreg1287, 6; mem:LD4[%rNToGo312] GPR32:%vreg1286 GPR64common:%vreg1287
9712B		CBNZW %vreg1286, <BB#46>; GPR32:%vreg1286
	    Successors according to CFG: BB#46 BB#43

9728B	BB#43: derived from LLVM BB %if.then.315
	    Predecessors according to CFG: BB#42
9776B		%vreg1417<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1417
9792B		%vreg1416<def> = LDRSWui %vreg1417, 7; mem:LD4[%rTPos316] GPR64:%vreg1416 GPR64common:%vreg1417
9800B		%vreg1406<def> = ADRP <ga:@BZ2_rNums>[TF=1]; GPR64common:%vreg1406
9808B		%vreg1409<def> = MOVi64imm 4; GPR64:%vreg1409
9816B		%vreg1407<def> = ADDXri %vreg1406, <ga:@BZ2_rNums>[TF=34], 0; GPR64common:%vreg1407,%vreg1406
9824B		%vreg1410<def> = MADDXrrr %vreg1416, %vreg1409, %XZR; GPR64:%vreg1410,%vreg1416,%vreg1409
9840B		%vreg1411<def> = ADDXrr %vreg1407, %vreg1410; GPR64common:%vreg1411,%vreg1407 GPR64:%vreg1410
9856B		%vreg1405<def> = LDRWui %vreg1411, 0; mem:LD4[%arrayidx318] GPR32:%vreg1405 GPR64common:%vreg1411
9872B		%vreg1403<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1403
9888B		STRWui %vreg1405, %vreg1403, 6; mem:ST4[%rNToGo319] GPR32:%vreg1405 GPR64common:%vreg1403
9904B		%vreg1400<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1400
9920B		%vreg1399<def> = LDRWui %vreg1400, 7; mem:LD4[%rTPos320] GPR32common:%vreg1399 GPR64common:%vreg1400
9936B		%vreg1398<def> = ADDWri %vreg1399, 1, 0; GPR32common:%vreg1398,%vreg1399
9952B		STRWui %vreg1398, %vreg1400, 7; mem:ST4[%rTPos320] GPR32common:%vreg1398 GPR64common:%vreg1400
9968B		%vreg1394<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1394
9984B		%vreg1393<def> = LDRWui %vreg1394, 7; mem:LD4[%rTPos322] GPR32common:%vreg1393 GPR64common:%vreg1394
10000B		%WZR<def> = SUBSWri %vreg1393, 512, 0, %NZCV<imp-def>; GPR32common:%vreg1393
10016B		Bcc 1, <BB#45>, %NZCV<imp-use>
	    Successors according to CFG: BB#45 BB#44

10032B	BB#44: derived from LLVM BB %if.then.325
	    Predecessors according to CFG: BB#43
10048B		%vreg1419<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1419
10064B		STRWui %WZR, %vreg1419, 7; mem:ST4[%rTPos326] GPR64common:%vreg1419
	    Successors according to CFG: BB#45

10080B	BB#45: derived from LLVM BB %if.end.327
	    Predecessors according to CFG: BB#43 BB#44
10096B		B <BB#46>
	    Successors according to CFG: BB#46

10112B	BB#46: derived from LLVM BB %if.end.328
	    Predecessors according to CFG: BB#42 BB#45
10120B		%vreg1435<def> = COPY %WZR; GPR32:%vreg1435
10160B		%vreg1445<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1445
10176B		%vreg1444<def> = LDRWui %vreg1445, 6; mem:LD4[%rNToGo329] GPR32common:%vreg1444 GPR64common:%vreg1445
10192B		%vreg1443<def> = SUBWri %vreg1444, 1, 0; GPR32common:%vreg1443,%vreg1444
10208B		STRWui %vreg1443, %vreg1445, 6; mem:ST4[%rNToGo329] GPR32common:%vreg1443 GPR64common:%vreg1445
10224B		%vreg1439<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1439
10288B		%vreg1432<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1432
10296B		%vreg1438<def> = LDRWui %vreg1439, 6; mem:LD4[%rNToGo331] GPR32common:%vreg1438 GPR64common:%vreg1439
10304B		%vreg1431<def> = LDRWui %vreg1432, 16; mem:LD4[%k0335] GPR32:%vreg1431 GPR64common:%vreg1432
10312B		%WZR<def> = SUBSWri %vreg1438, 1, 0, %NZCV<imp-def>; GPR32common:%vreg1438
10320B		%vreg1434<def> = MOVi32imm 1; GPR32:%vreg1434
10328B		%vreg1436<def> = CSELWr %vreg1434, %vreg1435, 0, %NZCV<imp-use>; GPR32:%vreg1436,%vreg1434,%vreg1435
10336B		%vreg1430<def> = EORWrr %vreg1431, %vreg1436; GPR32:%vreg1430,%vreg1431,%vreg1436
10344B		STRWui %vreg1430, %vreg1432, 16; mem:ST4[%k0335] GPR32:%vreg1430 GPR64common:%vreg1432
10352B		%vreg1425<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1425
10368B		%vreg1424<def> = LDRWui %vreg1425, 273; mem:LD4[%nblock_used337] GPR32common:%vreg1424 GPR64common:%vreg1425
10384B		%vreg1423<def> = ADDWri %vreg1424, 1, 0; GPR32common:%vreg1423,%vreg1424
10400B		STRWui %vreg1423, %vreg1425, 273; mem:ST4[%nblock_used337] GPR32common:%vreg1423 GPR64common:%vreg1425
10416B		B <BB#2>
	    Successors according to CFG: BB#2

10432B	BB#47: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#0
10448B		B <BB#48>
	    Successors according to CFG: BB#48

10464B	BB#48: derived from LLVM BB %while.body.339
	    Predecessors according to CFG: BB#47 BB#72 BB#71 BB#69 BB#67 BB#65 BB#63 BB#61
10480B		B <BB#49>
	    Successors according to CFG: BB#49

10496B	BB#49: derived from LLVM BB %while.body.341
	    Predecessors according to CFG: BB#48 BB#55
10512B		%vreg17<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg17
10528B		%vreg16<def> = LDRXui %vreg17, 0; mem:LD8[%strm342] GPR64common:%vreg16,%vreg17
10544B		%vreg14<def> = LDRWui %vreg16, 8; mem:LD4[%avail_out343] GPR32:%vreg14 GPR64common:%vreg16
10560B		CBNZW %vreg14, <BB#51>; GPR32:%vreg14
	    Successors according to CFG: BB#51 BB#50

10576B	BB#50: derived from LLVM BB %if.then.346
	    Predecessors according to CFG: BB#49
10592B		STRBBui %WZR, <fi#0>, 0; mem:ST1[FixedStack0]
10608B		B <BB#73>
	    Successors according to CFG: BB#73

10624B	BB#51: derived from LLVM BB %if.end.347
	    Predecessors according to CFG: BB#49
10640B		%vreg21<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg21
10656B		%vreg20<def> = LDRWui %vreg21, 4; mem:LD4[%state_out_len348] GPR32:%vreg20 GPR64common:%vreg21
10672B		CBNZW %vreg20, <BB#53>; GPR32:%vreg20
	    Successors according to CFG: BB#53 BB#52

10688B	BB#52: derived from LLVM BB %if.then.351
	    Predecessors according to CFG: BB#51
10704B		B <BB#56>
	    Successors according to CFG: BB#56

10720B	BB#53: derived from LLVM BB %if.end.352
	    Predecessors according to CFG: BB#51
10800B		%vreg97<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg97
10808B		%vreg100<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg100
10816B		%vreg96<def> = LDRXui %vreg97, 0; mem:LD8[%strm354] GPR64common:%vreg96,%vreg97
10824B		%vreg99<def> = LDRBBui %vreg100, 12; mem:LD1[%state_out_ch353] GPR32:%vreg99 GPR64common:%vreg100
10832B		%vreg94<def> = LDRXui %vreg96, 3; mem:LD8[%next_out355] GPR64common:%vreg94,%vreg96
10848B		STRBBui %vreg99, %vreg94, 0; mem:ST1[%261] GPR32:%vreg99 GPR64common:%vreg94
10896B		%vreg87<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg87
10944B		%vreg82<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg82
10952B		%vreg66<def> = ADRP <ga:@BZ2_crc32Table>[TF=1]; GPR64common:%vreg66
10960B		%vreg90<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg90
10968B		%vreg86<def> = LDRWui %vreg87, 796; mem:LD4[%calculatedBlockCRC358] GPR32:%vreg86 GPR64common:%vreg87
10976B		%vreg81<def> = LDRBBui %vreg82, 12; mem:LD1[%state_out_ch360] GPR32:%vreg81 GPR64common:%vreg82
10984B		%vreg67<def> = ADDXri %vreg66, <ga:@BZ2_crc32Table>[TF=34], 0; GPR64common:%vreg67,%vreg66
10992B		%vreg89<def> = LDRWui %vreg90, 796; mem:LD4[%calculatedBlockCRC356] GPR32:%vreg89 GPR64common:%vreg90
11000B		%vreg84<def> = UBFMWri %vreg86, 24, 31; GPR32:%vreg84,%vreg86
11008B		%vreg73:sub_32<def,read-undef> = EORWrr %vreg84, %vreg81; GPR64:%vreg73 GPR32:%vreg84,%vreg81
11024B		%vreg74<def> = UBFMXri %vreg73, 0, 31; GPR64:%vreg74,%vreg73
11032B		%vreg69<def> = MOVi64imm 4; GPR64:%vreg69
11040B		%vreg70<def> = MADDXrrr %vreg74, %vreg69, %XZR; GPR64:%vreg70,%vreg74,%vreg69
11056B		%vreg71<def> = ADDXrr %vreg67, %vreg70; GPR64common:%vreg71,%vreg67 GPR64:%vreg70
11072B		%vreg65<def> = LDRWui %vreg71, 0; mem:LD4[%arrayidx364] GPR32:%vreg65 GPR64common:%vreg71
11104B		%vreg60<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg60
11112B		%vreg63<def> = EORWrs %vreg65, %vreg89, 8; GPR32:%vreg63,%vreg65,%vreg89
11120B		STRWui %vreg63, %vreg60, 796; mem:ST4[%calculatedBlockCRC366] GPR32:%vreg63 GPR64common:%vreg60
11136B		%vreg57<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg57
11152B		%vreg56<def> = LDRWui %vreg57, 4; mem:LD4[%state_out_len367] GPR32common:%vreg56 GPR64common:%vreg57
11168B		%vreg55<def> = SUBWri %vreg56, 1, 0; GPR32common:%vreg55,%vreg56
11184B		STRWui %vreg55, %vreg57, 4; mem:ST4[%state_out_len367] GPR32common:%vreg55 GPR64common:%vreg57
11200B		%vreg51<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg51
11216B		%vreg50<def> = LDRXui %vreg51, 0; mem:LD8[%strm369] GPR64common:%vreg50,%vreg51
11232B		%vreg48<def> = LDRXui %vreg50, 3; mem:LD8[%next_out370] GPR64common:%vreg48,%vreg50
11248B		%vreg47<def> = ADDXri %vreg48, 1, 0; GPR64common:%vreg47,%vreg48
11264B		STRXui %vreg47, %vreg50, 3; mem:ST8[%next_out370] GPR64common:%vreg47,%vreg50
11280B		%vreg43<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg43
11296B		%vreg42<def> = LDRXui %vreg43, 0; mem:LD8[%strm372] GPR64common:%vreg42,%vreg43
11312B		%vreg40<def> = LDRWui %vreg42, 8; mem:LD4[%avail_out373] GPR32common:%vreg40 GPR64common:%vreg42
11328B		%vreg39<def> = SUBWri %vreg40, 1, 0; GPR32common:%vreg39,%vreg40
11344B		STRWui %vreg39, %vreg42, 8; mem:ST4[%avail_out373] GPR32common:%vreg39 GPR64common:%vreg42
11360B		%vreg35<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg35
11376B		%vreg34<def> = LDRXui %vreg35, 0; mem:LD8[%strm375] GPR64common:%vreg34,%vreg35
11392B		%vreg32<def> = LDRWui %vreg34, 9; mem:LD4[%total_out_lo32376] GPR32common:%vreg32 GPR64common:%vreg34
11408B		%vreg31<def> = ADDWri %vreg32, 1, 0; GPR32common:%vreg31,%vreg32
11424B		STRWui %vreg31, %vreg34, 9; mem:ST4[%total_out_lo32376] GPR32common:%vreg31 GPR64common:%vreg34
11440B		%vreg27<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg27
11456B		%vreg26<def> = LDRXui %vreg27, 0; mem:LD8[%strm378] GPR64common:%vreg26,%vreg27
11472B		%vreg24<def> = LDRWui %vreg26, 9; mem:LD4[%total_out_lo32379] GPR32:%vreg24 GPR64common:%vreg26
11488B		CBNZW %vreg24, <BB#55>; GPR32:%vreg24
	    Successors according to CFG: BB#55 BB#54

11504B	BB#54: derived from LLVM BB %if.then.382
	    Predecessors according to CFG: BB#53
11520B		%vreg108<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg108
11536B		%vreg107<def> = LDRXui %vreg108, 0; mem:LD8[%strm383] GPR64common:%vreg107,%vreg108
11552B		%vreg105<def> = LDRWui %vreg107, 10; mem:LD4[%total_out_hi32384] GPR32common:%vreg105 GPR64common:%vreg107
11568B		%vreg104<def> = ADDWri %vreg105, 1, 0; GPR32common:%vreg104,%vreg105
11584B		STRWui %vreg104, %vreg107, 10; mem:ST4[%total_out_hi32384] GPR32common:%vreg104 GPR64common:%vreg107
	    Successors according to CFG: BB#55

11600B	BB#55: derived from LLVM BB %if.end.386
	    Predecessors according to CFG: BB#53 BB#54
11616B		B <BB#49>
	    Successors according to CFG: BB#49

11632B	BB#56: derived from LLVM BB %while.end.387
	    Predecessors according to CFG: BB#52
11680B		%vreg117<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg117
11688B		%vreg120<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg120
11696B		%vreg114<def> = MOVi64imm 64080; GPR64:%vreg114
11712B		%vreg115<def> = ADDXrr %vreg117, %vreg114; GPR64common:%vreg115 GPR64:%vreg117,%vreg114
11728B		%vreg116<def> = LDRWui %vreg115, 0; mem:LD4[%save_nblock389] GPR32common:%vreg116 GPR64common:%vreg115
11736B		%vreg119<def> = LDRWui %vreg120, 273; mem:LD4[%nblock_used388] GPR32:%vreg119 GPR64common:%vreg120
11744B		%vreg112<def> = ADDWri %vreg116, 1, 0; GPR32common:%vreg112,%vreg116
11760B		%WZR<def> = SUBSWrr %vreg119, %vreg112, %NZCV<imp-def>; GPR32:%vreg119 GPR32common:%vreg112
11776B		Bcc 1, <BB#58>, %NZCV<imp-use>
	    Successors according to CFG: BB#58 BB#57

11792B	BB#57: derived from LLVM BB %if.then.393
	    Predecessors according to CFG: BB#56
11808B		STRBBui %WZR, <fi#0>, 0; mem:ST1[FixedStack0]
11824B		B <BB#73>
	    Successors according to CFG: BB#73

11840B	BB#58: derived from LLVM BB %if.end.394
	    Predecessors according to CFG: BB#56
11888B		%vreg129<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg129
11896B		%vreg132<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg132
11904B		%vreg126<def> = MOVi64imm 64080; GPR64:%vreg126
11920B		%vreg127<def> = ADDXrr %vreg129, %vreg126; GPR64common:%vreg127 GPR64:%vreg129,%vreg126
11936B		%vreg128<def> = LDRWui %vreg127, 0; mem:LD4[%save_nblock396] GPR32common:%vreg128 GPR64common:%vreg127
11944B		%vreg131<def> = LDRWui %vreg132, 273; mem:LD4[%nblock_used395] GPR32:%vreg131 GPR64common:%vreg132
11952B		%vreg124<def> = ADDWri %vreg128, 1, 0; GPR32common:%vreg124,%vreg128
11968B		%WZR<def> = SUBSWrr %vreg131, %vreg124, %NZCV<imp-def>; GPR32:%vreg131 GPR32common:%vreg124
11984B		Bcc 13, <BB#60>, %NZCV<imp-use>
	    Successors according to CFG: BB#60 BB#59

12000B	BB#59: derived from LLVM BB %if.then.400
	    Predecessors according to CFG: BB#58
12016B		%vreg601<def> = MOVi32imm 1; GPR32:%vreg601
12032B		STRBBui %vreg601, <fi#0>, 0; mem:ST1[FixedStack0] GPR32:%vreg601
12048B		B <BB#73>
	    Successors according to CFG: BB#73

12064B	BB#60: derived from LLVM BB %if.end.401
	    Predecessors according to CFG: BB#58
12096B		%vreg228<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg228
12104B		%vreg226<def> = MOVi32imm 1; GPR32:%vreg226
12112B		STRWui %vreg226, %vreg228, 4; mem:ST4[%state_out_len402] GPR32:%vreg226 GPR64common:%vreg228
12128B		%vreg225<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg225
12144B		%vreg222<def> = LDRWui %vreg225, 16; mem:LD4[%k0403] GPR32:%vreg222 GPR64common:%vreg225
12176B		%vreg220<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg220
12192B		STRBBui %vreg222, %vreg220, 12; mem:ST1[%state_out_ch405] GPR32:%vreg222 GPR64common:%vreg220
12208B		%vreg217<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg217
12240B		%vreg214<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg214
12248B		%vreg216<def> = LDRWui %vreg217, 15; mem:LD4[%tPos406] GPR32:%vreg216 GPR64common:%vreg217
12256B		%vreg213<def> = ADDXri %vreg214, 1096, 0; GPR64sp:%vreg213 GPR64common:%vreg214
12272B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
12288B		%W0<def> = COPY %vreg216; GPR32:%vreg216
12304B		%X1<def> = COPY %vreg213; GPR64sp:%vreg213
12320B		BL <ga:@BZ2_indexIntoF>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use,kill>, %W0<imp-def>
12336B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
12352B		%vreg207<def> = COPY %W0; GPR32:%vreg207
12368B		%vreg162<def> = MOVi32imm 4; GPR32:%vreg162
12384B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
12400B		STACKMAP 6, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
12416B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
12448B		STRBBui %vreg207, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg207
12464B		%vreg204<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg204
12512B		%vreg197<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg197
12520B		%vreg203:sub_32<def,read-undef> = LDRWui %vreg204, 15; mem:LD4[%tPos411] GPR64:%vreg203 GPR64common:%vreg204
12544B		%vreg192<def> = MOVi64imm 2; GPR64:%vreg192
12608B		%vreg185<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg185
12612B		%vreg196<def> = LDRXui %vreg197, 395; mem:LD8[%ll16413] GPR64:%vreg196 GPR64common:%vreg197
12616B		%vreg193<def> = MADDXrrr %vreg203, %vreg192, %XZR; GPR64:%vreg193,%vreg203,%vreg192
12688B		%vreg177<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg177
12692B		%vreg184<def> = LDRWui %vreg185, 15; mem:LD4[%tPos416] GPR32:%vreg184 GPR64common:%vreg185
12696B		%vreg194<def> = ADDXrr %vreg196, %vreg193; GPR64common:%vreg194 GPR64:%vreg196,%vreg193
12752B		%vreg167<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg167
12760B		%vreg176<def> = LDRXui %vreg177, 396; mem:LD8[%ll4419] GPR64:%vreg176 GPR64common:%vreg177
12768B		%vreg179:sub_32<def,read-undef> = UBFMWri %vreg184, 1, 31; GPR64:%vreg179 GPR32:%vreg184
12776B		%vreg180<def> = UBFMXri %vreg179, 0, 31; GPR64:%vreg180,%vreg179
12784B		%vreg166<def> = LDRWui %vreg167, 15; mem:LD4[%tPos422] GPR32:%vreg166 GPR64common:%vreg167
12792B		%vreg174<def> = ADDXrr %vreg176, %vreg180; GPR64common:%vreg174 GPR64:%vreg176,%vreg180
12800B		%vreg171<def> = LDRBBui %vreg174, 0; mem:LD1[%arrayidx420] GPR32:%vreg171 GPR64common:%vreg174
12808B		%vreg189<def> = LDRHHui %vreg194, 0; mem:LD2[%arrayidx414] GPR32:%vreg189 GPR64common:%vreg194
12816B		%vreg164<def> = ANDWrs %vreg162, %vreg166, 2; GPR32:%vreg164,%vreg162,%vreg166
12848B		%vreg153<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg153
12856B		%vreg161<def> = LSRVWr %vreg171, %vreg164; GPR32:%vreg161,%vreg171,%vreg164
12864B		%vreg158<def> = ANDWri %vreg161, 3; GPR32common:%vreg158 GPR32:%vreg161
12872B		%vreg156<def> = ORRWrs %vreg189, %vreg158, 16; GPR32:%vreg156,%vreg189 GPR32common:%vreg158
12880B		STRWui %vreg156, %vreg153, 15; mem:ST4[%tPos429] GPR32:%vreg156 GPR64common:%vreg153
12888B		%vreg150<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg150
12896B		%vreg149<def> = LDRWui %vreg150, 273; mem:LD4[%nblock_used430] GPR32common:%vreg149 GPR64common:%vreg150
12912B		%vreg148<def> = ADDWri %vreg149, 1, 0; GPR32common:%vreg148,%vreg149
12928B		STRWui %vreg148, %vreg150, 273; mem:ST4[%nblock_used430] GPR32common:%vreg148 GPR64common:%vreg150
12976B		%vreg141<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg141
12984B		%vreg144<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg144
12992B		%vreg138<def> = MOVi64imm 64080; GPR64:%vreg138
13008B		%vreg139<def> = ADDXrr %vreg141, %vreg138; GPR64common:%vreg139 GPR64:%vreg141,%vreg138
13024B		%vreg140<def> = LDRWui %vreg139, 0; mem:LD4[%save_nblock433] GPR32common:%vreg140 GPR64common:%vreg139
13032B		%vreg143<def> = LDRWui %vreg144, 273; mem:LD4[%nblock_used432] GPR32:%vreg143 GPR64common:%vreg144
13040B		%vreg136<def> = ADDWri %vreg140, 1, 0; GPR32common:%vreg136,%vreg140
13056B		%WZR<def> = SUBSWrr %vreg143, %vreg136, %NZCV<imp-def>; GPR32:%vreg143 GPR32common:%vreg136
13072B		Bcc 1, <BB#62>, %NZCV<imp-use>
	    Successors according to CFG: BB#62 BB#61

13088B	BB#61: derived from LLVM BB %if.then.437
	    Predecessors according to CFG: BB#60
13104B		B <BB#48>
	    Successors according to CFG: BB#48

13120B	BB#62: derived from LLVM BB %if.end.438
	    Predecessors according to CFG: BB#60
13152B		%vreg233<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg233
13160B		%vreg236<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg236
13168B		%vreg232<def> = LDRWui %vreg233, 16; mem:LD4[%k0440] GPR32:%vreg232 GPR64common:%vreg233
13184B		%WZR<def> = SUBSWrr %vreg236, %vreg232, %NZCV<imp-def>; GPR32:%vreg236,%vreg232
13200B		Bcc 0, <BB#64>, %NZCV<imp-use>
	    Successors according to CFG: BB#64 BB#63

13216B	BB#63: derived from LLVM BB %if.then.443
	    Predecessors according to CFG: BB#62
13232B		%vreg600<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg600
13248B		%vreg597<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg597
13264B		STRWui %vreg600, %vreg597, 16; mem:ST4[%k0445] GPR32:%vreg600 GPR64common:%vreg597
13280B		B <BB#48>
	    Successors according to CFG: BB#48

13296B	BB#64: derived from LLVM BB %if.end.446
	    Predecessors according to CFG: BB#62
13328B		%vreg324<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg324
13336B		%vreg322<def> = MOVi32imm 2; GPR32:%vreg322
13344B		STRWui %vreg322, %vreg324, 4; mem:ST4[%state_out_len447] GPR32:%vreg322 GPR64common:%vreg324
13360B		%vreg321<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg321
13392B		%vreg318<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg318
13400B		%vreg320<def> = LDRWui %vreg321, 15; mem:LD4[%tPos448] GPR32:%vreg320 GPR64common:%vreg321
13408B		%vreg317<def> = ADDXri %vreg318, 1096, 0; GPR64sp:%vreg317 GPR64common:%vreg318
13424B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
13440B		%W0<def> = COPY %vreg320; GPR32:%vreg320
13456B		%X1<def> = COPY %vreg317; GPR64sp:%vreg317
13472B		BL <ga:@BZ2_indexIntoF>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use,kill>, %W0<imp-def>
13488B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
13504B		%vreg311<def> = COPY %W0; GPR32:%vreg311
13520B		%vreg266<def> = MOVi32imm 4; GPR32:%vreg266
13536B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
13552B		STACKMAP 7, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
13568B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
13600B		STRBBui %vreg311, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg311
13616B		%vreg308<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg308
13664B		%vreg301<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg301
13672B		%vreg307:sub_32<def,read-undef> = LDRWui %vreg308, 15; mem:LD4[%tPos453] GPR64:%vreg307 GPR64common:%vreg308
13696B		%vreg296<def> = MOVi64imm 2; GPR64:%vreg296
13760B		%vreg289<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg289
13764B		%vreg300<def> = LDRXui %vreg301, 395; mem:LD8[%ll16455] GPR64:%vreg300 GPR64common:%vreg301
13768B		%vreg297<def> = MADDXrrr %vreg307, %vreg296, %XZR; GPR64:%vreg297,%vreg307,%vreg296
13840B		%vreg281<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg281
13844B		%vreg288<def> = LDRWui %vreg289, 15; mem:LD4[%tPos458] GPR32:%vreg288 GPR64common:%vreg289
13848B		%vreg298<def> = ADDXrr %vreg300, %vreg297; GPR64common:%vreg298 GPR64:%vreg300,%vreg297
13904B		%vreg271<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg271
13912B		%vreg280<def> = LDRXui %vreg281, 396; mem:LD8[%ll4461] GPR64:%vreg280 GPR64common:%vreg281
13920B		%vreg283:sub_32<def,read-undef> = UBFMWri %vreg288, 1, 31; GPR64:%vreg283 GPR32:%vreg288
13928B		%vreg284<def> = UBFMXri %vreg283, 0, 31; GPR64:%vreg284,%vreg283
13936B		%vreg270<def> = LDRWui %vreg271, 15; mem:LD4[%tPos464] GPR32:%vreg270 GPR64common:%vreg271
13944B		%vreg278<def> = ADDXrr %vreg280, %vreg284; GPR64common:%vreg278 GPR64:%vreg280,%vreg284
13952B		%vreg275<def> = LDRBBui %vreg278, 0; mem:LD1[%arrayidx462] GPR32:%vreg275 GPR64common:%vreg278
13960B		%vreg293<def> = LDRHHui %vreg298, 0; mem:LD2[%arrayidx456] GPR32:%vreg293 GPR64common:%vreg298
13968B		%vreg268<def> = ANDWrs %vreg266, %vreg270, 2; GPR32:%vreg268,%vreg266,%vreg270
14000B		%vreg257<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg257
14008B		%vreg265<def> = LSRVWr %vreg275, %vreg268; GPR32:%vreg265,%vreg275,%vreg268
14016B		%vreg262<def> = ANDWri %vreg265, 3; GPR32common:%vreg262 GPR32:%vreg265
14024B		%vreg260<def> = ORRWrs %vreg293, %vreg262, 16; GPR32:%vreg260,%vreg293 GPR32common:%vreg262
14032B		STRWui %vreg260, %vreg257, 15; mem:ST4[%tPos471] GPR32:%vreg260 GPR64common:%vreg257
14040B		%vreg254<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg254
14048B		%vreg253<def> = LDRWui %vreg254, 273; mem:LD4[%nblock_used472] GPR32common:%vreg253 GPR64common:%vreg254
14064B		%vreg252<def> = ADDWri %vreg253, 1, 0; GPR32common:%vreg252,%vreg253
14080B		STRWui %vreg252, %vreg254, 273; mem:ST4[%nblock_used472] GPR32common:%vreg252 GPR64common:%vreg254
14128B		%vreg245<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg245
14136B		%vreg248<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg248
14144B		%vreg242<def> = MOVi64imm 64080; GPR64:%vreg242
14160B		%vreg243<def> = ADDXrr %vreg245, %vreg242; GPR64common:%vreg243 GPR64:%vreg245,%vreg242
14176B		%vreg244<def> = LDRWui %vreg243, 0; mem:LD4[%save_nblock475] GPR32common:%vreg244 GPR64common:%vreg243
14184B		%vreg247<def> = LDRWui %vreg248, 273; mem:LD4[%nblock_used474] GPR32:%vreg247 GPR64common:%vreg248
14192B		%vreg240<def> = ADDWri %vreg244, 1, 0; GPR32common:%vreg240,%vreg244
14208B		%WZR<def> = SUBSWrr %vreg247, %vreg240, %NZCV<imp-def>; GPR32:%vreg247 GPR32common:%vreg240
14224B		Bcc 1, <BB#66>, %NZCV<imp-use>
	    Successors according to CFG: BB#66 BB#65

14240B	BB#65: derived from LLVM BB %if.then.479
	    Predecessors according to CFG: BB#64
14256B		B <BB#48>
	    Successors according to CFG: BB#48

14272B	BB#66: derived from LLVM BB %if.end.480
	    Predecessors according to CFG: BB#64
14304B		%vreg329<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg329
14312B		%vreg332<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg332
14320B		%vreg328<def> = LDRWui %vreg329, 16; mem:LD4[%k0482] GPR32:%vreg328 GPR64common:%vreg329
14336B		%WZR<def> = SUBSWrr %vreg332, %vreg328, %NZCV<imp-def>; GPR32:%vreg332,%vreg328
14352B		Bcc 0, <BB#68>, %NZCV<imp-use>
	    Successors according to CFG: BB#68 BB#67

14368B	BB#67: derived from LLVM BB %if.then.485
	    Predecessors according to CFG: BB#66
14384B		%vreg594<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg594
14400B		%vreg591<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg591
14416B		STRWui %vreg594, %vreg591, 16; mem:ST4[%k0487] GPR32:%vreg594 GPR64common:%vreg591
14432B		B <BB#48>
	    Successors according to CFG: BB#48

14448B	BB#68: derived from LLVM BB %if.end.488
	    Predecessors according to CFG: BB#66
14480B		%vreg420<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg420
14488B		%vreg418<def> = MOVi32imm 3; GPR32:%vreg418
14496B		STRWui %vreg418, %vreg420, 4; mem:ST4[%state_out_len489] GPR32:%vreg418 GPR64common:%vreg420
14512B		%vreg417<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg417
14544B		%vreg414<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg414
14552B		%vreg416<def> = LDRWui %vreg417, 15; mem:LD4[%tPos490] GPR32:%vreg416 GPR64common:%vreg417
14560B		%vreg413<def> = ADDXri %vreg414, 1096, 0; GPR64sp:%vreg413 GPR64common:%vreg414
14576B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
14592B		%W0<def> = COPY %vreg416; GPR32:%vreg416
14608B		%X1<def> = COPY %vreg413; GPR64sp:%vreg413
14624B		BL <ga:@BZ2_indexIntoF>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use,kill>, %W0<imp-def>
14640B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
14656B		%vreg407<def> = COPY %W0; GPR32:%vreg407
14672B		%vreg362<def> = MOVi32imm 4; GPR32:%vreg362
14688B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
14704B		STACKMAP 8, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
14720B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
14752B		STRBBui %vreg407, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg407
14768B		%vreg404<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg404
14816B		%vreg397<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg397
14824B		%vreg403:sub_32<def,read-undef> = LDRWui %vreg404, 15; mem:LD4[%tPos495] GPR64:%vreg403 GPR64common:%vreg404
14848B		%vreg392<def> = MOVi64imm 2; GPR64:%vreg392
14912B		%vreg385<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg385
14916B		%vreg396<def> = LDRXui %vreg397, 395; mem:LD8[%ll16497] GPR64:%vreg396 GPR64common:%vreg397
14920B		%vreg393<def> = MADDXrrr %vreg403, %vreg392, %XZR; GPR64:%vreg393,%vreg403,%vreg392
14992B		%vreg377<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg377
14996B		%vreg384<def> = LDRWui %vreg385, 15; mem:LD4[%tPos500] GPR32:%vreg384 GPR64common:%vreg385
15000B		%vreg394<def> = ADDXrr %vreg396, %vreg393; GPR64common:%vreg394 GPR64:%vreg396,%vreg393
15056B		%vreg367<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg367
15064B		%vreg376<def> = LDRXui %vreg377, 396; mem:LD8[%ll4503] GPR64:%vreg376 GPR64common:%vreg377
15072B		%vreg379:sub_32<def,read-undef> = UBFMWri %vreg384, 1, 31; GPR64:%vreg379 GPR32:%vreg384
15080B		%vreg380<def> = UBFMXri %vreg379, 0, 31; GPR64:%vreg380,%vreg379
15088B		%vreg366<def> = LDRWui %vreg367, 15; mem:LD4[%tPos506] GPR32:%vreg366 GPR64common:%vreg367
15096B		%vreg374<def> = ADDXrr %vreg376, %vreg380; GPR64common:%vreg374 GPR64:%vreg376,%vreg380
15104B		%vreg371<def> = LDRBBui %vreg374, 0; mem:LD1[%arrayidx504] GPR32:%vreg371 GPR64common:%vreg374
15112B		%vreg389<def> = LDRHHui %vreg394, 0; mem:LD2[%arrayidx498] GPR32:%vreg389 GPR64common:%vreg394
15120B		%vreg364<def> = ANDWrs %vreg362, %vreg366, 2; GPR32:%vreg364,%vreg362,%vreg366
15152B		%vreg353<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg353
15160B		%vreg361<def> = LSRVWr %vreg371, %vreg364; GPR32:%vreg361,%vreg371,%vreg364
15168B		%vreg358<def> = ANDWri %vreg361, 3; GPR32common:%vreg358 GPR32:%vreg361
15176B		%vreg356<def> = ORRWrs %vreg389, %vreg358, 16; GPR32:%vreg356,%vreg389 GPR32common:%vreg358
15184B		STRWui %vreg356, %vreg353, 15; mem:ST4[%tPos513] GPR32:%vreg356 GPR64common:%vreg353
15192B		%vreg350<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg350
15200B		%vreg349<def> = LDRWui %vreg350, 273; mem:LD4[%nblock_used514] GPR32common:%vreg349 GPR64common:%vreg350
15216B		%vreg348<def> = ADDWri %vreg349, 1, 0; GPR32common:%vreg348,%vreg349
15232B		STRWui %vreg348, %vreg350, 273; mem:ST4[%nblock_used514] GPR32common:%vreg348 GPR64common:%vreg350
15280B		%vreg341<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg341
15288B		%vreg344<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg344
15296B		%vreg338<def> = MOVi64imm 64080; GPR64:%vreg338
15312B		%vreg339<def> = ADDXrr %vreg341, %vreg338; GPR64common:%vreg339 GPR64:%vreg341,%vreg338
15328B		%vreg340<def> = LDRWui %vreg339, 0; mem:LD4[%save_nblock517] GPR32common:%vreg340 GPR64common:%vreg339
15336B		%vreg343<def> = LDRWui %vreg344, 273; mem:LD4[%nblock_used516] GPR32:%vreg343 GPR64common:%vreg344
15344B		%vreg336<def> = ADDWri %vreg340, 1, 0; GPR32common:%vreg336,%vreg340
15360B		%WZR<def> = SUBSWrr %vreg343, %vreg336, %NZCV<imp-def>; GPR32:%vreg343 GPR32common:%vreg336
15376B		Bcc 1, <BB#70>, %NZCV<imp-use>
	    Successors according to CFG: BB#70 BB#69

15392B	BB#69: derived from LLVM BB %if.then.521
	    Predecessors according to CFG: BB#68
15408B		B <BB#48>
	    Successors according to CFG: BB#48

15424B	BB#70: derived from LLVM BB %if.end.522
	    Predecessors according to CFG: BB#68
15456B		%vreg425<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg425
15464B		%vreg428<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg428
15472B		%vreg424<def> = LDRWui %vreg425, 16; mem:LD4[%k0524] GPR32:%vreg424 GPR64common:%vreg425
15488B		%WZR<def> = SUBSWrr %vreg428, %vreg424, %NZCV<imp-def>; GPR32:%vreg428,%vreg424
15504B		Bcc 0, <BB#72>, %NZCV<imp-use>
	    Successors according to CFG: BB#72 BB#71

15520B	BB#71: derived from LLVM BB %if.then.527
	    Predecessors according to CFG: BB#70
15536B		%vreg588<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg588
15552B		%vreg585<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg585
15568B		STRWui %vreg588, %vreg585, 16; mem:ST4[%k0529] GPR32:%vreg588 GPR64common:%vreg585
15584B		B <BB#48>
	    Successors according to CFG: BB#48

15600B	BB#72: derived from LLVM BB %if.end.530
	    Predecessors according to CFG: BB#70
15616B		%vreg582<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg582
15648B		%vreg579<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg579
15656B		%vreg581<def> = LDRWui %vreg582, 15; mem:LD4[%tPos531] GPR32:%vreg581 GPR64common:%vreg582
15664B		%vreg578<def> = ADDXri %vreg579, 1096, 0; GPR64sp:%vreg578 GPR64common:%vreg579
15680B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
15696B		%W0<def> = COPY %vreg581; GPR32:%vreg581
15712B		%X1<def> = COPY %vreg578; GPR64sp:%vreg578
15728B		BL <ga:@BZ2_indexIntoF>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use,kill>, %W0<imp-def>
15744B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
15760B		%vreg572<def> = COPY %W0; GPR32:%vreg572
15776B		%vreg527<def> = MOVi32imm 4; GPR32:%vreg527
15792B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
15808B		STACKMAP 9, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
15824B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
15856B		STRBBui %vreg572, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg572
15872B		%vreg569<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg569
15920B		%vreg562<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg562
15928B		%vreg568:sub_32<def,read-undef> = LDRWui %vreg569, 15; mem:LD4[%tPos536] GPR64:%vreg568 GPR64common:%vreg569
15952B		%vreg557<def> = MOVi64imm 2; GPR64:%vreg557
16016B		%vreg550<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg550
16020B		%vreg561<def> = LDRXui %vreg562, 395; mem:LD8[%ll16538] GPR64:%vreg561 GPR64common:%vreg562
16024B		%vreg558<def> = MADDXrrr %vreg568, %vreg557, %XZR; GPR64:%vreg558,%vreg568,%vreg557
16096B		%vreg542<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg542
16100B		%vreg549<def> = LDRWui %vreg550, 15; mem:LD4[%tPos541] GPR32:%vreg549 GPR64common:%vreg550
16104B		%vreg559<def> = ADDXrr %vreg561, %vreg558; GPR64common:%vreg559 GPR64:%vreg561,%vreg558
16160B		%vreg532<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg532
16168B		%vreg541<def> = LDRXui %vreg542, 396; mem:LD8[%ll4544] GPR64:%vreg541 GPR64common:%vreg542
16176B		%vreg544:sub_32<def,read-undef> = UBFMWri %vreg549, 1, 31; GPR64:%vreg544 GPR32:%vreg549
16184B		%vreg545<def> = UBFMXri %vreg544, 0, 31; GPR64:%vreg545,%vreg544
16192B		%vreg531<def> = LDRWui %vreg532, 15; mem:LD4[%tPos547] GPR32:%vreg531 GPR64common:%vreg532
16200B		%vreg539<def> = ADDXrr %vreg541, %vreg545; GPR64common:%vreg539 GPR64:%vreg541,%vreg545
16208B		%vreg536<def> = LDRBBui %vreg539, 0; mem:LD1[%arrayidx545] GPR32:%vreg536 GPR64common:%vreg539
16216B		%vreg554<def> = LDRHHui %vreg559, 0; mem:LD2[%arrayidx539] GPR32:%vreg554 GPR64common:%vreg559
16224B		%vreg529<def> = ANDWrs %vreg527, %vreg531, 2; GPR32:%vreg529,%vreg527,%vreg531
16256B		%vreg518<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg518
16264B		%vreg526<def> = LSRVWr %vreg536, %vreg529; GPR32:%vreg526,%vreg536,%vreg529
16272B		%vreg523<def> = ANDWri %vreg526, 3; GPR32common:%vreg523 GPR32:%vreg526
16280B		%vreg521<def> = ORRWrs %vreg554, %vreg523, 16; GPR32:%vreg521,%vreg554 GPR32common:%vreg523
16288B		STRWui %vreg521, %vreg518, 15; mem:ST4[%tPos554] GPR32:%vreg521 GPR64common:%vreg518
16296B		%vreg515<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg515
16304B		%vreg514<def> = LDRWui %vreg515, 273; mem:LD4[%nblock_used555] GPR32common:%vreg514 GPR64common:%vreg515
16320B		%vreg513<def> = ADDWri %vreg514, 1, 0; GPR32common:%vreg513,%vreg514
16336B		STRWui %vreg513, %vreg515, 273; mem:ST4[%nblock_used555] GPR32common:%vreg513 GPR64common:%vreg515
16352B		%vreg509<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32common:%vreg509
16384B		%vreg504<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg504
16392B		%vreg506<def> = ADDWri %vreg509, 4, 0; GPR32common:%vreg506,%vreg509
16400B		STRWui %vreg506, %vreg504, 4; mem:ST4[%state_out_len559] GPR32common:%vreg506 GPR64common:%vreg504
16416B		%vreg501<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg501
16448B		%vreg498<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg498
16456B		%vreg500<def> = LDRWui %vreg501, 15; mem:LD4[%tPos560] GPR32:%vreg500 GPR64common:%vreg501
16464B		%vreg497<def> = ADDXri %vreg498, 1096, 0; GPR64sp:%vreg497 GPR64common:%vreg498
16480B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
16496B		%W0<def> = COPY %vreg500; GPR32:%vreg500
16512B		%X1<def> = COPY %vreg497; GPR64sp:%vreg497
16528B		BL <ga:@BZ2_indexIntoF>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use,kill>, %W0<imp-def>
16544B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
16560B		%vreg494<def> = COPY %W0; GPR32:%vreg494
16576B		%vreg446<def> = MOVi32imm 4; GPR32:%vreg446
16592B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
16608B		STACKMAP 10, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
16624B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
16640B		%vreg491<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg491
16656B		STRWui %vreg494, %vreg491, 16; mem:ST4[%k0564] GPR32:%vreg494 GPR64common:%vreg491
16672B		%vreg488<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg488
16720B		%vreg481<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg481
16728B		%vreg487:sub_32<def,read-undef> = LDRWui %vreg488, 15; mem:LD4[%tPos565] GPR64:%vreg487 GPR64common:%vreg488
16752B		%vreg476<def> = MOVi64imm 2; GPR64:%vreg476
16816B		%vreg469<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg469
16820B		%vreg480<def> = LDRXui %vreg481, 395; mem:LD8[%ll16567] GPR64:%vreg480 GPR64common:%vreg481
16824B		%vreg477<def> = MADDXrrr %vreg487, %vreg476, %XZR; GPR64:%vreg477,%vreg487,%vreg476
16896B		%vreg461<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg461
16900B		%vreg468<def> = LDRWui %vreg469, 15; mem:LD4[%tPos570] GPR32:%vreg468 GPR64common:%vreg469
16904B		%vreg478<def> = ADDXrr %vreg480, %vreg477; GPR64common:%vreg478 GPR64:%vreg480,%vreg477
16960B		%vreg451<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg451
16968B		%vreg460<def> = LDRXui %vreg461, 396; mem:LD8[%ll4573] GPR64:%vreg460 GPR64common:%vreg461
16976B		%vreg463:sub_32<def,read-undef> = UBFMWri %vreg468, 1, 31; GPR64:%vreg463 GPR32:%vreg468
16984B		%vreg464<def> = UBFMXri %vreg463, 0, 31; GPR64:%vreg464,%vreg463
16992B		%vreg450<def> = LDRWui %vreg451, 15; mem:LD4[%tPos576] GPR32:%vreg450 GPR64common:%vreg451
17000B		%vreg458<def> = ADDXrr %vreg460, %vreg464; GPR64common:%vreg458 GPR64:%vreg460,%vreg464
17008B		%vreg455<def> = LDRBBui %vreg458, 0; mem:LD1[%arrayidx574] GPR32:%vreg455 GPR64common:%vreg458
17016B		%vreg473<def> = LDRHHui %vreg478, 0; mem:LD2[%arrayidx568] GPR32:%vreg473 GPR64common:%vreg478
17024B		%vreg448<def> = ANDWrs %vreg446, %vreg450, 2; GPR32:%vreg448,%vreg446,%vreg450
17056B		%vreg437<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg437
17064B		%vreg445<def> = LSRVWr %vreg455, %vreg448; GPR32:%vreg445,%vreg455,%vreg448
17072B		%vreg442<def> = ANDWri %vreg445, 3; GPR32common:%vreg442 GPR32:%vreg445
17080B		%vreg440<def> = ORRWrs %vreg473, %vreg442, 16; GPR32:%vreg440,%vreg473 GPR32common:%vreg442
17088B		STRWui %vreg440, %vreg437, 15; mem:ST4[%tPos583] GPR32:%vreg440 GPR64common:%vreg437
17096B		%vreg434<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg434
17104B		%vreg433<def> = LDRWui %vreg434, 273; mem:LD4[%nblock_used584] GPR32common:%vreg433 GPR64common:%vreg434
17120B		%vreg432<def> = ADDWri %vreg433, 1, 0; GPR32common:%vreg432,%vreg433
17136B		STRWui %vreg432, %vreg434, 273; mem:ST4[%nblock_used584] GPR32common:%vreg432 GPR64common:%vreg434
17152B		B <BB#48>
	    Successors according to CFG: BB#48

17168B	BB#73: derived from LLVM BB %return
	    Predecessors according to CFG: BB#59 BB#57 BB#50 BB#13 BB#11 BB#4
17184B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
17200B		%vreg1466<def> = MOVaddr <ga:@unRLE_obuf_to_output_SMALL>[TF=1], <ga:@unRLE_obuf_to_output_SMALL>[TF=34]; GPR64:%vreg1466
17216B		%X0<def> = COPY %vreg1466; GPR64:%vreg1466
17232B		%X1<def> = COPY %vreg10; GPR64:%vreg10
17248B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %SP<imp-def>
17264B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
17280B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
17296B		STACKMAP 11, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=1)
17312B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
17328B		%vreg1467<def> = LDRBBui <fi#0>, 0; mem:LD1[%retval] GPR32:%vreg1467
17360B		%W0<def> = COPY %vreg1467; GPR32:%vreg1467
17376B		RET_ReallyLR %W0<imp-use>

# End machine code for function unRLE_obuf_to_output_SMALL.


selectOrSplit GPR64:%vreg10 [16r,17232r:0)  0@16r w=1.720027e-04
hints: %X1
missed hint %X1
Analyze counted 3 instrs in 2 blocks, through 72 blocks.
%X1	static = 1.0 worse than no bundles
%X8	static = 1.0 worse than no bundles
%X9	static = 1.0 worse than no bundles
%X10	static = 1.0 worse than no bundles
%X11	static = 1.0 worse than no bundles
%X12	static = 1.0 worse than no bundles
%X13	static = 1.0 worse than no bundles
%X14	static = 1.0 worse than no bundles
%X15	static = 1.0 worse than no bundles
%X16	static = 1.0 worse than no bundles
%X17	static = 1.0 worse than no bundles
%X18	static = 1.0 worse than no bundles
%X0	no positive bundles
%X2	static = 1.0 worse than no bundles
%X3	static = 1.0 worse than no bundles
%X4	static = 1.0 worse than no bundles
%X5	static = 1.0 worse than no bundles
%X6	static = 1.0 worse than no bundles
%X7	static = 1.0 worse than no bundles
assigning %vreg10 to %X19: W19 [16r,17232r:0)  0@16r

selectOrSplit GPR64:%vreg1 [32r,256r:0)  0@32r w=4.855769e-03
hints: %X0
missed hint %X0
Analyze counted 3 instrs in 1 blocks, through 0 blocks.
%X0	no positive bundles
%X8	no positive bundles
%X9	no positive bundles
%X10	no positive bundles
%X11	no positive bundles
%X12	no positive bundles
%X13	no positive bundles
%X14	no positive bundles
%X15	no positive bundles
%X16	no positive bundles
%X17	no positive bundles
%X18	no positive bundles
%X1	no positive bundles
%X2	no positive bundles
%X3	no positive bundles
%X4	no positive bundles
%X5	no positive bundles
%X6	no positive bundles
%X7	no positive bundles
%X19	no positive bundles
assigning %vreg1 to %X20: W20 [32r,256r:0)  0@32r

selectOrSplit GPR64sp:%vreg9 [80r,144r:0)  0@80r w=4.353448e-03
hints: %X0
assigning %vreg9 to %X0: W0 [80r,144r:0)  0@80r

selectOrSplit GPR32:%vreg792 [2152r,2192r:0)  0@2152r w=2.085804e-04
hints: %W0
assigning %vreg792 to %W0: W0 [2152r,2192r:0)  0@2152r

selectOrSplit GPR64sp:%vreg789 [2160r,2208r:0)  0@2160r w=2.048558e-04
hints: %X1
assigning %vreg789 to %X1: W1 [2160r,2208r:0)  0@2160r

selectOrSplit GPR32:%vreg783 [2256r,2352r:0)  0@2256r w=1.850310e-04
hints: %W0
assigning %vreg783 to %W0: W0 [2256r,2352r:0)  0@2256r

selectOrSplit GPR32:%vreg951 [3976r,4016r:0)  0@3976r w=5.206868e-05
hints: %W0
assigning %vreg951 to %W0: W0 [3976r,4016r:0)  0@3976r

selectOrSplit GPR64sp:%vreg948 [3984r,4032r:0)  0@3984r w=5.113888e-05
hints: %X1
assigning %vreg948 to %X1: W1 [3984r,4032r:0)  0@3984r

selectOrSplit GPR32:%vreg942 [4080r,4176r:0)  0@4080r w=4.618996e-05
hints: %W0
assigning %vreg942 to %W0: W0 [4080r,4176r:0)  0@4080r

selectOrSplit GPR32:%vreg1102 [5800r,5840r:0)  0@5800r w=1.294075e-05
hints: %W0
assigning %vreg1102 to %W0: W0 [5800r,5840r:0)  0@5800r

selectOrSplit GPR64sp:%vreg1099 [5808r,5856r:0)  0@5808r w=1.270966e-05
hints: %X1
assigning %vreg1099 to %X1: W1 [5808r,5856r:0)  0@5808r

selectOrSplit GPR32:%vreg1093 [5904r,6000r:0)  0@5904r w=1.147970e-05
hints: %W0
assigning %vreg1093 to %W0: W0 [5904r,6000r:0)  0@5904r

selectOrSplit GPR32:%vreg1253 [7576r,7616r:0)  0@7576r w=3.158765e-06
hints: %W0
assigning %vreg1253 to %W0: W0 [7576r,7616r:0)  0@7576r

selectOrSplit GPR64sp:%vreg1250 [7584r,7632r:0)  0@7584r w=3.102359e-06
hints: %X1
assigning %vreg1250 to %X1: W1 [7584r,7632r:0)  0@7584r

selectOrSplit GPR32:%vreg1244 [7680r,7776r:0)  0@7680r w=2.802131e-06
hints: %W0
assigning %vreg1244 to %W0: W0 [7680r,7776r:0)  0@7680r

selectOrSplit GPR32:%vreg1353 [9048r,9088r:0)  0@9048r w=3.158765e-06
hints: %W0
assigning %vreg1353 to %W0: W0 [9048r,9088r:0)  0@9048r

selectOrSplit GPR64sp:%vreg1350 [9056r,9104r:0)  0@9056r w=3.102359e-06
hints: %X1
assigning %vreg1350 to %X1: W1 [9056r,9104r:0)  0@9056r

selectOrSplit GPR32:%vreg1347 [9152r,9248r:0)  0@9152r w=2.802131e-06
hints: %W0
assigning %vreg1347 to %W0: W0 [9152r,9248r:0)  0@9152r

selectOrSplit GPR32:%vreg216 [12248r,12288r:0)  0@12248r w=2.085804e-04
hints: %W0
assigning %vreg216 to %W0: W0 [12248r,12288r:0)  0@12248r

selectOrSplit GPR64sp:%vreg213 [12256r,12304r:0)  0@12256r w=2.048558e-04
hints: %X1
assigning %vreg213 to %X1: W1 [12256r,12304r:0)  0@12256r

selectOrSplit GPR32:%vreg207 [12352r,12448r:0)  0@12352r w=1.850310e-04
hints: %W0
assigning %vreg207 to %W0: W0 [12352r,12448r:0)  0@12352r

selectOrSplit GPR32:%vreg320 [13400r,13440r:0)  0@13400r w=5.206868e-05
hints: %W0
assigning %vreg320 to %W0: W0 [13400r,13440r:0)  0@13400r

selectOrSplit GPR64sp:%vreg317 [13408r,13456r:0)  0@13408r w=5.113888e-05
hints: %X1
assigning %vreg317 to %X1: W1 [13408r,13456r:0)  0@13408r

selectOrSplit GPR32:%vreg311 [13504r,13600r:0)  0@13504r w=4.618996e-05
hints: %W0
assigning %vreg311 to %W0: W0 [13504r,13600r:0)  0@13504r

selectOrSplit GPR32:%vreg416 [14552r,14592r:0)  0@14552r w=1.294075e-05
hints: %W0
assigning %vreg416 to %W0: W0 [14552r,14592r:0)  0@14552r

selectOrSplit GPR64sp:%vreg413 [14560r,14608r:0)  0@14560r w=1.270966e-05
hints: %X1
assigning %vreg413 to %X1: W1 [14560r,14608r:0)  0@14560r

selectOrSplit GPR32:%vreg407 [14656r,14752r:0)  0@14656r w=1.147970e-05
hints: %W0
assigning %vreg407 to %W0: W0 [14656r,14752r:0)  0@14656r

selectOrSplit GPR32:%vreg581 [15656r,15696r:0)  0@15656r w=3.158765e-06
hints: %W0
assigning %vreg581 to %W0: W0 [15656r,15696r:0)  0@15656r

selectOrSplit GPR64sp:%vreg578 [15664r,15712r:0)  0@15664r w=3.102359e-06
hints: %X1
assigning %vreg578 to %X1: W1 [15664r,15712r:0)  0@15664r

selectOrSplit GPR32:%vreg572 [15760r,15856r:0)  0@15760r w=2.802131e-06
hints: %W0
assigning %vreg572 to %W0: W0 [15760r,15856r:0)  0@15760r

selectOrSplit GPR32:%vreg500 [16456r,16496r:0)  0@16456r w=3.158765e-06
hints: %W0
assigning %vreg500 to %W0: W0 [16456r,16496r:0)  0@16456r

selectOrSplit GPR64sp:%vreg497 [16464r,16512r:0)  0@16464r w=3.102359e-06
hints: %X1
assigning %vreg497 to %X1: W1 [16464r,16512r:0)  0@16464r

selectOrSplit GPR32:%vreg494 [16560r,16656r:0)  0@16560r w=2.802131e-06
hints: %W0
assigning %vreg494 to %W0: W0 [16560r,16656r:0)  0@16560r

selectOrSplit GPR64:%vreg1466 [17200r,17216r:0)  0@17200r w=inf
hints: %X0
assigning %vreg1466 to %X0: W0 [17200r,17216r:0)  0@17200r

selectOrSplit GPR32:%vreg1467 [17328r,17360r:0)  0@17328r w=inf
hints: %W0
assigning %vreg1467 to %W0: W0 [17328r,17360r:0)  0@17328r

selectOrSplit GPR64common:%vreg7 [64r,80r:0)  0@64r w=inf
assigning %vreg7 to %X8: W8 [64r,80r:0)  0@64r

selectOrSplit GPR64common:%vreg6 [272r,288r:0)  0@272r w=inf
assigning %vreg6 to %X8: W8 [272r,288r:0)  0@272r

selectOrSplit GPR32:%vreg5 [288r,304r:0)  0@288r w=inf
assigning %vreg5 to %W8: W8 [288r,304r:0)  0@288r

selectOrSplit GPR32:%vreg3 [304r,320r:0)  0@304r w=inf
assigning %vreg3 to %W8: W8 [304r,320r:0)  0@304r

selectOrSplit GPR64common:%vreg607 [416r,432r:0)  0@416r w=inf
assigning %vreg607 to %X8: W8 [416r,432r:0)  0@416r

selectOrSplit GPR64common:%vreg606 [432r,448r:0)  0@432r w=inf
assigning %vreg606 to %X8: W8 [432r,448r:0)  0@432r

selectOrSplit GPR32:%vreg604 [448r,464r:0)  0@448r w=inf
assigning %vreg604 to %W8: W8 [448r,464r:0)  0@448r

selectOrSplit GPR64common:%vreg611 [544r,560r:0)  0@544r w=inf
assigning %vreg611 to %X8: W8 [544r,560r:0)  0@544r

selectOrSplit GPR32:%vreg610 [560r,576r:0)  0@560r w=inf
assigning %vreg610 to %W8: W8 [560r,576r:0)  0@560r

selectOrSplit GPR64common:%vreg687 [704r,720r:0)  0@704r w=8.740386e-04
assigning %vreg687 to %X8: W8 [704r,720r:0)  0@704r

selectOrSplit GPR64common:%vreg690 [712r,728r:0)  0@712r w=8.740386e-04
assigning %vreg690 to %X9: W9 [712r,728r:0)  0@712r

selectOrSplit GPR64common:%vreg686 [720r,736r:0)  0@720r w=8.740386e-04
assigning %vreg686 to %X8: W8 [720r,736r:0)  0@720r

selectOrSplit GPR32:%vreg689 [728r,752r:0)  0@728r w=8.575473e-04
assigning %vreg689 to %W9: W9 [728r,752r:0)  0@728r

selectOrSplit GPR64common:%vreg684 [736r,752r:0)  0@736r w=inf
assigning %vreg684 to %X8: W8 [736r,752r:0)  0@736r

selectOrSplit GPR64common:%vreg677 [800r,872r:0)  0@800r w=7.703391e-04
assigning %vreg677 to %X8: W8 [800r,872r:0)  0@800r

selectOrSplit GPR64common:%vreg672 [848r,880r:0)  0@848r w=8.416668e-04
assigning %vreg672 to %X9: W9 [848r,880r:0)  0@848r

selectOrSplit GPR64common:%vreg656 [856r,888r:0)  0@856r w=4.208334e-04
assigning %vreg656 to %X10: W10 [856r,888r:0)  0@856r

selectOrSplit GPR64common:%vreg680 [864r,896r:0)  0@864r w=8.416668e-04
assigning %vreg680 to %X11: W11 [864r,896r:0)  0@864r

selectOrSplit GPR32:%vreg676 [872r,904r:0)  0@872r w=8.416668e-04
assigning %vreg676 to %W8: W8 [872r,904r:0)  0@872r

selectOrSplit GPR32:%vreg671 [880r,912r:0)  0@880r w=8.416668e-04
assigning %vreg671 to %W9: W9 [880r,912r:0)  0@880r

selectOrSplit GPR64common:%vreg657 [888r,960r:0)  0@888r w=7.703391e-04
assigning %vreg657 to %X10: W10 [888r,960r:0)  0@888r

selectOrSplit GPR32:%vreg679 [896r,1016r:0)  0@896r w=6.992309e-04
assigning %vreg679 to %W11: W11 [896r,1016r:0)  0@896r

selectOrSplit GPR32:%vreg674 [904r,912r:0)  0@904r w=inf
assigning %vreg674 to %W8: W8 [904r,912r:0)  0@904r

selectOrSplit GPR64:%vreg663 [912r,928r:0)  0@912r w=inf
assigning %vreg663 to %X8: W8 [912r,928r:0)  0@912r

selectOrSplit GPR64:%vreg664 [928r,944r:0)  0@928r w=8.740386e-04
assigning %vreg664 to %X8: W8 [928r,944r:0)  0@928r

selectOrSplit GPR64:%vreg659 [936r,944r:0)  0@936r w=inf
assigning %vreg659 to %X9: W9 [936r,944r:0)  0@936r

selectOrSplit GPR64:%vreg660 [944r,960r:0)  0@944r w=inf
assigning %vreg660 to %X8: W8 [944r,960r:0)  0@944r

selectOrSplit GPR64common:%vreg661 [960r,976r:0)  0@960r w=inf
assigning %vreg661 to %X8: W8 [960r,976r:0)  0@960r

selectOrSplit GPR32:%vreg655 [976r,1016r:0)  0@976r w=8.263637e-04
assigning %vreg655 to %W8: W8 [976r,1016r:0)  0@976r

selectOrSplit GPR64common:%vreg650 [1008r,1024r:0)  0@1008r w=8.740386e-04
assigning %vreg650 to %X9: W9 [1008r,1024r:0)  0@1008r

selectOrSplit GPR32:%vreg653 [1016r,1024r:0)  0@1016r w=inf
assigning %vreg653 to %W8: W8 [1016r,1024r:0)  0@1016r

selectOrSplit GPR64common:%vreg647 [1040r,1088r:0)  0@1040r w=1.217411e-03
assigning %vreg647 to %X8: W8 [1040r,1088r:0)  0@1040r

selectOrSplit GPR32common:%vreg646 [1056r,1072r:0)  0@1056r w=inf
assigning %vreg646 to %W9: W9 [1056r,1072r:0)  0@1056r

selectOrSplit GPR32common:%vreg645 [1072r,1088r:0)  0@1072r w=inf
assigning %vreg645 to %W9: W9 [1072r,1088r:0)  0@1072r

selectOrSplit GPR64common:%vreg641 [1104r,1120r:0)  0@1104r w=inf
assigning %vreg641 to %X8: W8 [1104r,1120r:0)  0@1104r

selectOrSplit GPR64common:%vreg640 [1120r,1168r:0)  0@1120r w=1.217411e-03
assigning %vreg640 to %X8: W8 [1120r,1168r:0)  0@1120r

selectOrSplit GPR64common:%vreg638 [1136r,1152r:0)  0@1136r w=inf
assigning %vreg638 to %X9: W9 [1136r,1152r:0)  0@1136r

selectOrSplit GPR64common:%vreg637 [1152r,1168r:0)  0@1152r w=inf
assigning %vreg637 to %X9: W9 [1152r,1168r:0)  0@1152r

selectOrSplit GPR64common:%vreg633 [1184r,1200r:0)  0@1184r w=inf
assigning %vreg633 to %X8: W8 [1184r,1200r:0)  0@1184r

selectOrSplit GPR64common:%vreg632 [1200r,1248r:0)  0@1200r w=1.217411e-03
assigning %vreg632 to %X8: W8 [1200r,1248r:0)  0@1200r

selectOrSplit GPR32common:%vreg630 [1216r,1232r:0)  0@1216r w=inf
assigning %vreg630 to %W9: W9 [1216r,1232r:0)  0@1216r

selectOrSplit GPR32common:%vreg629 [1232r,1248r:0)  0@1232r w=inf
assigning %vreg629 to %W9: W9 [1232r,1248r:0)  0@1232r

selectOrSplit GPR64common:%vreg625 [1264r,1280r:0)  0@1264r w=inf
assigning %vreg625 to %X8: W8 [1264r,1280r:0)  0@1264r

selectOrSplit GPR64common:%vreg624 [1280r,1328r:0)  0@1280r w=1.217411e-03
assigning %vreg624 to %X8: W8 [1280r,1328r:0)  0@1280r

selectOrSplit GPR32common:%vreg622 [1296r,1312r:0)  0@1296r w=inf
assigning %vreg622 to %W9: W9 [1296r,1312r:0)  0@1296r

selectOrSplit GPR32common:%vreg621 [1312r,1328r:0)  0@1312r w=inf
assigning %vreg621 to %W9: W9 [1312r,1328r:0)  0@1312r

selectOrSplit GPR64common:%vreg617 [1344r,1360r:0)  0@1344r w=inf
assigning %vreg617 to %X8: W8 [1344r,1360r:0)  0@1344r

selectOrSplit GPR64common:%vreg616 [1360r,1376r:0)  0@1360r w=inf
assigning %vreg616 to %X8: W8 [1360r,1376r:0)  0@1360r

selectOrSplit GPR32:%vreg614 [1376r,1392r:0)  0@1376r w=inf
assigning %vreg614 to %W8: W8 [1376r,1392r:0)  0@1376r

selectOrSplit GPR64common:%vreg698 [1424r,1440r:0)  0@1424r w=inf
assigning %vreg698 to %X8: W8 [1424r,1440r:0)  0@1424r

selectOrSplit GPR64common:%vreg697 [1440r,1488r:0)  0@1440r w=6.086311e-04
assigning %vreg697 to %X8: W8 [1440r,1488r:0)  0@1440r

selectOrSplit GPR32common:%vreg695 [1456r,1472r:0)  0@1456r w=inf
assigning %vreg695 to %W9: W9 [1456r,1472r:0)  0@1456r

selectOrSplit GPR32common:%vreg694 [1472r,1488r:0)  0@1472r w=inf
assigning %vreg694 to %W9: W9 [1472r,1488r:0)  0@1472r

selectOrSplit GPR64:%vreg707 [1584r,1616r:0)  0@1584r w=8.416668e-04
assigning %vreg707 to %X8: W8 [1584r,1616r:0)  0@1584r

selectOrSplit GPR64common:%vreg710 [1592r,1640r:0)  0@1592r w=8.116072e-04
assigning %vreg710 to %X9: W9 [1592r,1640r:0)  0@1592r

selectOrSplit GPR64:%vreg704 [1600r,1616r:0)  0@1600r w=inf
assigning %vreg704 to %X10: W10 [1600r,1616r:0)  0@1600r

selectOrSplit GPR64common:%vreg705 [1616r,1632r:0)  0@1616r w=inf
assigning %vreg705 to %X8: W8 [1616r,1632r:0)  0@1616r

selectOrSplit GPR32common:%vreg706 [1632r,1648r:0)  0@1632r w=8.740386e-04
assigning %vreg706 to %W8: W8 [1632r,1648r:0)  0@1632r

selectOrSplit GPR32:%vreg709 [1640r,1664r:0)  0@1640r w=8.575473e-04
assigning %vreg709 to %W9: W9 [1640r,1664r:0)  0@1640r

selectOrSplit GPR32common:%vreg702 [1648r,1664r:0)  0@1648r w=inf
assigning %vreg702 to %W8: W8 [1648r,1664r:0)  0@1648r

selectOrSplit GPR64:%vreg719 [1792r,1824r:0)  0@1792r w=4.207820e-04
assigning %vreg719 to %X8: W8 [1792r,1824r:0)  0@1792r

selectOrSplit GPR64common:%vreg722 [1800r,1848r:0)  0@1800r w=4.057541e-04
assigning %vreg722 to %X9: W9 [1800r,1848r:0)  0@1800r

selectOrSplit GPR64:%vreg716 [1808r,1824r:0)  0@1808r w=inf
assigning %vreg716 to %X10: W10 [1808r,1824r:0)  0@1808r

selectOrSplit GPR64common:%vreg717 [1824r,1840r:0)  0@1824r w=inf
assigning %vreg717 to %X8: W8 [1824r,1840r:0)  0@1824r

selectOrSplit GPR32common:%vreg718 [1840r,1856r:0)  0@1840r w=4.369659e-04
assigning %vreg718 to %W8: W8 [1840r,1856r:0)  0@1840r

selectOrSplit GPR32:%vreg721 [1848r,1872r:0)  0@1848r w=4.287213e-04
assigning %vreg721 to %W9: W9 [1848r,1872r:0)  0@1848r

selectOrSplit GPR32common:%vreg714 [1856r,1872r:0)  0@1856r w=inf
assigning %vreg714 to %W8: W8 [1856r,1872r:0)  0@1856r

selectOrSplit GPR32:%vreg1464 [1920r,1936r:0)  0@1920r w=inf
assigning %vreg1464 to %W8: W8 [1920r,1936r:0)  0@1920r

selectOrSplit GPR64common:%vreg804 [2000r,2016r:0)  0@2000r w=2.184296e-04
assigning %vreg804 to %X8: W8 [2000r,2016r:0)  0@2000r

selectOrSplit GPR32:%vreg802 [2008r,2016r:0)  0@2008r w=inf
assigning %vreg802 to %W9: W9 [2008r,2016r:0)  0@2008r

selectOrSplit GPR64common:%vreg801 [2032r,2048r:0)  0@2032r w=inf
assigning %vreg801 to %X8: W8 [2032r,2048r:0)  0@2032r

selectOrSplit GPR32:%vreg798 [2048r,2096r:0)  0@2048r w=2.028275e-04
assigning %vreg798 to %W8: W8 [2048r,2096r:0)  0@2048r

selectOrSplit GPR64common:%vreg796 [2080r,2096r:0)  0@2080r w=inf
assigning %vreg796 to %X9: W9 [2080r,2096r:0)  0@2080r

selectOrSplit GPR64common:%vreg793 [2112r,2152r:0)  0@2112r w=2.065153e-04
assigning %vreg793 to %X8: W8 [2112r,2152r:0)  0@2112r

selectOrSplit GPR64common:%vreg790 [2144r,2160r:0)  0@2144r w=2.184296e-04
assigning %vreg790 to %X9: W9 [2144r,2160r:0)  0@2144r

selectOrSplit GPR32:%vreg738 [2272r,2720r:0)  0@2272r w=5.357707e-05
assigning %vreg738 to %W8: W8 [2272r,2720r:0)  0@2272r

selectOrSplit GPR64common:%vreg780 [2368r,2424r:0)  0@2368r w=1.992691e-04
assigning %vreg780 to %X9: W9 [2368r,2424r:0)  0@2368r

selectOrSplit GPR64common:%vreg773 [2416r,2516r:0)  0@2416r w=1.817334e-04
assigning %vreg773 to %X10: W10 [2416r,2516r:0)  0@2416r

selectOrSplit GPR64:%vreg779 [2424r,2520r:0)  0@2424r w=1.831990e-04
assigning %vreg779 to %X9: W9 [2424r,2520r:0)  0@2424r

selectOrSplit GPR64:%vreg768 [2448r,2520r:0)  0@2448r w=9.625711e-05
assigning %vreg768 to %X11: W11 [2448r,2520r:0)  0@2448r

selectOrSplit GPR64common:%vreg761 [2512r,2596r:0)  0@2512r w=1.877411e-04
assigning %vreg761 to %X12: W12 [2512r,2596r:0)  0@2512r

selectOrSplit GPR64:%vreg772 [2516r,2600r:0)  0@2516r w=1.877411e-04
assigning %vreg772 to %X10: W10 [2516r,2600r:0)  0@2516r

selectOrSplit GPR64:%vreg769 [2520r,2600r:0)  0@2520r w=1.893057e-04
assigning %vreg769 to %X9: W9 [2520r,2600r:0)  0@2520r

selectOrSplit GPR64common:%vreg753 [2592r,2664r:0)  0@2592r w=1.925142e-04
assigning %vreg753 to %X11: W11 [2592r,2664r:0)  0@2592r

selectOrSplit GPR32:%vreg760 [2596r,2672r:0)  0@2596r w=1.908965e-04
assigning %vreg760 to %W12: W12 [2596r,2672r:0)  0@2596r

selectOrSplit GPR64common:%vreg770 [2600r,2712r:0)  0@2600r w=1.774741e-04
assigning %vreg770 to %X9: W9 [2600r,2712r:0)  0@2600r

selectOrSplit GPR64common:%vreg743 [2656r,2688r:0)  0@2656r w=2.103396e-04
assigning %vreg743 to %X10: W10 [2656r,2688r:0)  0@2656r

selectOrSplit GPR64:%vreg752 [2664r,2696r:0)  0@2664r w=2.103396e-04
assigning %vreg752 to %X11: W11 [2664r,2696r:0)  0@2664r

selectOrSplit GPR64:%vreg755 [2672r,2680r:0)  0@2672r w=inf
assigning %vreg755 to %X12: W12 [2672r,2680r:0)  0@2672r

selectOrSplit GPR64:%vreg756 [2680r,2696r:0)  0@2680r w=2.184296e-04
assigning %vreg756 to %X12: W12 [2680r,2696r:0)  0@2680r

selectOrSplit GPR32:%vreg742 [2688r,2720r:0)  0@2688r w=2.103396e-04
assigning %vreg742 to %W10: W10 [2688r,2720r:0)  0@2688r

selectOrSplit GPR64common:%vreg750 [2696r,2704r:0)  0@2696r w=inf
assigning %vreg750 to %X11: W11 [2696r,2704r:0)  0@2696r

selectOrSplit GPR32:%vreg747 [2704r,2760r:0)  0@2704r w=1.992691e-04
assigning %vreg747 to %W11: W11 [2704r,2760r:0)  0@2704r

selectOrSplit GPR32:%vreg765 [2712r,2776r:0)  0@2712r w=1.958334e-04
assigning %vreg765 to %W9: W9 [2712r,2776r:0)  0@2712r

selectOrSplit GPR32:%vreg740 [2720r,2760r:0)  0@2720r w=2.065153e-04
assigning %vreg740 to %W8: W8 [2720r,2760r:0)  0@2720r

selectOrSplit GPR64common:%vreg729 [2752r,2784r:0)  0@2752r w=2.103396e-04
assigning %vreg729 to %X10: W10 [2752r,2784r:0)  0@2752r

selectOrSplit GPR32:%vreg737 [2760r,2768r:0)  0@2760r w=inf
assigning %vreg737 to %W8: W8 [2760r,2768r:0)  0@2760r

selectOrSplit GPR32common:%vreg734 [2768r,2776r:0)  0@2768r w=inf
assigning %vreg734 to %W8: W8 [2768r,2776r:0)  0@2768r

selectOrSplit GPR32:%vreg732 [2776r,2784r:0)  0@2776r w=inf
assigning %vreg732 to %W8: W8 [2776r,2784r:0)  0@2776r

selectOrSplit GPR64common:%vreg726 [2792r,2800r:0)  0@2792r w=inf
assigning %vreg726 to %X8: W8 [2792r,2800r:0)  0@2792r

selectOrSplit GPR32:%vreg725 [2800r,2816r:0)  0@2800r w=inf
assigning %vreg725 to %W8: W8 [2800r,2816r:0)  0@2800r

selectOrSplit GPR64common:%vreg831 [2880r,2896r:0)  0@2880r w=inf
assigning %vreg831 to %X8: W8 [2880r,2896r:0)  0@2880r

selectOrSplit GPR64:%vreg830 [2896r,2928r:0)  0@2896r w=1.051184e-04
assigning %vreg830 to %X8: W8 [2896r,2928r:0)  0@2896r

selectOrSplit GPR64common:%vreg820 [2904r,2920r:0)  0@2904r w=5.458072e-05
assigning %vreg820 to %X9: W9 [2904r,2920r:0)  0@2904r

selectOrSplit GPR64:%vreg823 [2912r,2928r:0)  0@2912r w=5.458072e-05
assigning %vreg823 to %X10: W10 [2912r,2928r:0)  0@2912r

selectOrSplit GPR64common:%vreg821 [2920r,2944r:0)  0@2920r w=1.071018e-04
assigning %vreg821 to %X9: W9 [2920r,2944r:0)  0@2920r

selectOrSplit GPR64:%vreg824 [2928r,2944r:0)  0@2928r w=inf
assigning %vreg824 to %X8: W8 [2928r,2944r:0)  0@2928r

selectOrSplit GPR64common:%vreg825 [2944r,2960r:0)  0@2944r w=inf
assigning %vreg825 to %X8: W8 [2944r,2960r:0)  0@2944r

selectOrSplit GPR32:%vreg819 [2960r,2992r:0)  0@2960r w=1.051184e-04
assigning %vreg819 to %W8: W8 [2960r,2992r:0)  0@2960r

selectOrSplit GPR64common:%vreg817 [2976r,2992r:0)  0@2976r w=inf
assigning %vreg817 to %X9: W9 [2976r,2992r:0)  0@2976r

selectOrSplit GPR64common:%vreg814 [3008r,3056r:0)  0@3008r w=1.520463e-04
assigning %vreg814 to %X8: W8 [3008r,3056r:0)  0@3008r

selectOrSplit GPR32common:%vreg813 [3024r,3040r:0)  0@3024r w=inf
assigning %vreg813 to %W9: W9 [3024r,3040r:0)  0@3024r

selectOrSplit GPR32common:%vreg812 [3040r,3056r:0)  0@3040r w=inf
assigning %vreg812 to %W9: W9 [3040r,3056r:0)  0@3040r

selectOrSplit GPR64common:%vreg808 [3072r,3088r:0)  0@3072r w=inf
assigning %vreg808 to %X8: W8 [3072r,3088r:0)  0@3072r

selectOrSplit GPR32common:%vreg807 [3088r,3104r:0)  0@3088r w=inf
assigning %vreg807 to %W8: W8 [3088r,3104r:0)  0@3088r

selectOrSplit GPR64common:%vreg833 [3152r,3168r:0)  0@3152r w=inf
assigning %vreg833 to %X8: W8 [3152r,3168r:0)  0@3152r

selectOrSplit GPR32:%vreg863 [3224r,3416r:0)  0@3224r w=1.534911e-04
assigning %vreg863 to %W8: W8 [3224r,3416r:0)  0@3224r

selectOrSplit GPR64common:%vreg873 [3264r,3312r:0)  0@3264r w=3.042412e-04
assigning %vreg873 to %X9: W9 [3264r,3312r:0)  0@3264r

selectOrSplit GPR32common:%vreg872 [3280r,3296r:0)  0@3280r w=inf
assigning %vreg872 to %W10: W10 [3280r,3296r:0)  0@3280r

selectOrSplit GPR32common:%vreg871 [3296r,3312r:0)  0@3296r w=inf
assigning %vreg871 to %W10: W10 [3296r,3312r:0)  0@3296r

selectOrSplit GPR64common:%vreg867 [3328r,3344r:0)  0@3328r w=inf
assigning %vreg867 to %X9: W9 [3328r,3344r:0)  0@3328r

selectOrSplit GPR32common:%vreg866 [3344r,3408r:0)  0@3344r w=1.958334e-04
assigning %vreg866 to %W9: W9 [3344r,3408r:0)  0@3344r

selectOrSplit GPR32:%vreg860 [3392r,3424r:0)  0@3392r w=2.103396e-04
assigning %vreg860 to %W10: W10 [3392r,3424r:0)  0@3392r

selectOrSplit GPR32:%vreg862 [3400r,3416r:0)  0@3400r w=1.092148e-04
assigning %vreg862 to %W11: W11 [3400r,3416r:0)  0@3400r

selectOrSplit GPR32:%vreg864 [3416r,3424r:0)  0@3416r w=inf
assigning %vreg864 to %W8: W8 [3416r,3424r:0)  0@3416r

selectOrSplit GPR32:%vreg854 [3424r,3440r:0)  0@3424r w=inf
assigning %vreg854 to %W8: W8 [3424r,3440r:0)  0@3424r

selectOrSplit GPR64common:%vreg851 [3456r,3504r:0)  0@3456r w=3.042412e-04
assigning %vreg851 to %X8: W8 [3456r,3504r:0)  0@3456r

selectOrSplit GPR32common:%vreg850 [3472r,3488r:0)  0@3472r w=inf
assigning %vreg850 to %W9: W9 [3472r,3488r:0)  0@3472r

selectOrSplit GPR32common:%vreg849 [3488r,3504r:0)  0@3488r w=inf
assigning %vreg849 to %W9: W9 [3488r,3504r:0)  0@3488r

selectOrSplit GPR64:%vreg842 [3552r,3584r:0)  0@3552r w=2.103396e-04
assigning %vreg842 to %X8: W8 [3552r,3584r:0)  0@3552r

selectOrSplit GPR64common:%vreg845 [3560r,3608r:0)  0@3560r w=2.028275e-04
assigning %vreg845 to %X9: W9 [3560r,3608r:0)  0@3560r

selectOrSplit GPR64:%vreg839 [3568r,3584r:0)  0@3568r w=inf
assigning %vreg839 to %X10: W10 [3568r,3584r:0)  0@3568r

selectOrSplit GPR64common:%vreg840 [3584r,3600r:0)  0@3584r w=inf
assigning %vreg840 to %X8: W8 [3584r,3600r:0)  0@3584r

selectOrSplit GPR32common:%vreg841 [3600r,3616r:0)  0@3600r w=2.184296e-04
assigning %vreg841 to %W8: W8 [3600r,3616r:0)  0@3600r

selectOrSplit GPR32:%vreg844 [3608r,3632r:0)  0@3608r w=2.143083e-04
assigning %vreg844 to %W9: W9 [3608r,3632r:0)  0@3608r

selectOrSplit GPR32common:%vreg837 [3616r,3632r:0)  0@3616r w=inf
assigning %vreg837 to %W8: W8 [3616r,3632r:0)  0@3616r

selectOrSplit GPR64common:%vreg878 [3728r,3744r:0)  0@3728r w=1.091614e-04
assigning %vreg878 to %X8: W8 [3728r,3744r:0)  0@3728r

selectOrSplit GPR32:%vreg881 [3736r,3760r:0)  0@3736r w=1.071018e-04
assigning %vreg881 to %W9: W9 [3736r,3760r:0)  0@3736r

selectOrSplit GPR32:%vreg877 [3744r,3760r:0)  0@3744r w=inf
assigning %vreg877 to %W8: W8 [3744r,3760r:0)  0@3744r

selectOrSplit GPR32:%vreg1463 [3808r,3840r:0)  0@3808r w=5.250784e-05
assigning %vreg1463 to %W8: W8 [3808r,3840r:0)  0@3808r

selectOrSplit GPR64common:%vreg1460 [3824r,3840r:0)  0@3824r w=inf
assigning %vreg1460 to %X9: W9 [3824r,3840r:0)  0@3824r

selectOrSplit GPR64common:%vreg955 [3904r,3920r:0)  0@3904r w=5.452737e-05
assigning %vreg955 to %X8: W8 [3904r,3920r:0)  0@3904r

selectOrSplit GPR32:%vreg953 [3912r,3920r:0)  0@3912r w=inf
assigning %vreg953 to %W9: W9 [3912r,3920r:0)  0@3912r

selectOrSplit GPR64common:%vreg952 [3936r,3976r:0)  0@3936r w=5.155315e-05
assigning %vreg952 to %X8: W8 [3936r,3976r:0)  0@3936r

selectOrSplit GPR64common:%vreg949 [3968r,3984r:0)  0@3968r w=5.452737e-05
assigning %vreg949 to %X9: W9 [3968r,3984r:0)  0@3968r

selectOrSplit GPR32:%vreg897 [4096r,4544r:0)  0@4096r w=1.337464e-05
assigning %vreg897 to %W8: W8 [4096r,4544r:0)  0@4096r

selectOrSplit GPR64common:%vreg939 [4192r,4248r:0)  0@4192r w=4.974427e-05
assigning %vreg939 to %X9: W9 [4192r,4248r:0)  0@4192r

selectOrSplit GPR64common:%vreg932 [4240r,4340r:0)  0@4240r w=4.536677e-05
assigning %vreg932 to %X10: W10 [4240r,4340r:0)  0@4240r

selectOrSplit GPR64:%vreg938 [4248r,4344r:0)  0@4248r w=4.573263e-05
assigning %vreg938 to %X9: W9 [4248r,4344r:0)  0@4248r

selectOrSplit GPR64:%vreg927 [4272r,4344r:0)  0@4272r w=2.402901e-05
assigning %vreg927 to %X11: W11 [4272r,4344r:0)  0@4272r

selectOrSplit GPR64common:%vreg920 [4336r,4420r:0)  0@4336r w=4.686650e-05
assigning %vreg920 to %X12: W12 [4336r,4420r:0)  0@4336r

selectOrSplit GPR64:%vreg931 [4340r,4424r:0)  0@4340r w=4.686650e-05
assigning %vreg931 to %X10: W10 [4340r,4424r:0)  0@4340r

selectOrSplit GPR64:%vreg928 [4344r,4424r:0)  0@4344r w=4.725705e-05
assigning %vreg928 to %X9: W9 [4344r,4424r:0)  0@4344r

selectOrSplit GPR64common:%vreg912 [4416r,4488r:0)  0@4416r w=4.805802e-05
assigning %vreg912 to %X11: W11 [4416r,4488r:0)  0@4416r

selectOrSplit GPR32:%vreg919 [4420r,4496r:0)  0@4420r w=4.765417e-05
assigning %vreg919 to %W12: W12 [4420r,4496r:0)  0@4420r

selectOrSplit GPR64common:%vreg929 [4424r,4536r:0)  0@4424r w=4.430349e-05
assigning %vreg929 to %X9: W9 [4424r,4536r:0)  0@4424r

selectOrSplit GPR64common:%vreg902 [4480r,4512r:0)  0@4480r w=5.250784e-05
assigning %vreg902 to %X10: W10 [4480r,4512r:0)  0@4480r

selectOrSplit GPR64:%vreg911 [4488r,4520r:0)  0@4488r w=5.250784e-05
assigning %vreg911 to %X11: W11 [4488r,4520r:0)  0@4488r

selectOrSplit GPR64:%vreg914 [4496r,4504r:0)  0@4496r w=inf
assigning %vreg914 to %X12: W12 [4496r,4504r:0)  0@4496r

selectOrSplit GPR64:%vreg915 [4504r,4520r:0)  0@4504r w=5.452737e-05
assigning %vreg915 to %X12: W12 [4504r,4520r:0)  0@4504r

selectOrSplit GPR32:%vreg901 [4512r,4544r:0)  0@4512r w=5.250784e-05
assigning %vreg901 to %W10: W10 [4512r,4544r:0)  0@4512r

selectOrSplit GPR64common:%vreg909 [4520r,4528r:0)  0@4520r w=inf
assigning %vreg909 to %X11: W11 [4520r,4528r:0)  0@4520r

selectOrSplit GPR32:%vreg906 [4528r,4584r:0)  0@4528r w=4.974427e-05
assigning %vreg906 to %W11: W11 [4528r,4584r:0)  0@4528r

selectOrSplit GPR32:%vreg924 [4536r,4600r:0)  0@4536r w=4.888661e-05
assigning %vreg924 to %W9: W9 [4536r,4600r:0)  0@4536r

selectOrSplit GPR32:%vreg899 [4544r,4584r:0)  0@4544r w=5.155315e-05
assigning %vreg899 to %W8: W8 [4544r,4584r:0)  0@4544r

selectOrSplit GPR64common:%vreg888 [4576r,4608r:0)  0@4576r w=5.250784e-05
assigning %vreg888 to %X10: W10 [4576r,4608r:0)  0@4576r

selectOrSplit GPR32:%vreg896 [4584r,4592r:0)  0@4584r w=inf
assigning %vreg896 to %W8: W8 [4584r,4592r:0)  0@4584r

selectOrSplit GPR32common:%vreg893 [4592r,4600r:0)  0@4592r w=inf
assigning %vreg893 to %W8: W8 [4592r,4600r:0)  0@4592r

selectOrSplit GPR32:%vreg891 [4600r,4608r:0)  0@4600r w=inf
assigning %vreg891 to %W8: W8 [4600r,4608r:0)  0@4600r

selectOrSplit GPR64common:%vreg885 [4616r,4624r:0)  0@4616r w=inf
assigning %vreg885 to %X8: W8 [4616r,4624r:0)  0@4616r

selectOrSplit GPR32:%vreg884 [4624r,4640r:0)  0@4624r w=inf
assigning %vreg884 to %W8: W8 [4624r,4640r:0)  0@4624r

selectOrSplit GPR64common:%vreg982 [4704r,4720r:0)  0@4704r w=inf
assigning %vreg982 to %X8: W8 [4704r,4720r:0)  0@4704r

selectOrSplit GPR64:%vreg981 [4720r,4752r:0)  0@4720r w=2.620254e-05
assigning %vreg981 to %X8: W8 [4720r,4752r:0)  0@4720r

selectOrSplit GPR64common:%vreg971 [4728r,4744r:0)  0@4728r w=1.360517e-05
assigning %vreg971 to %X9: W9 [4728r,4744r:0)  0@4728r

selectOrSplit GPR64:%vreg974 [4736r,4752r:0)  0@4736r w=1.360517e-05
assigning %vreg974 to %X10: W10 [4736r,4752r:0)  0@4736r

selectOrSplit GPR64common:%vreg972 [4744r,4768r:0)  0@4744r w=2.669693e-05
assigning %vreg972 to %X9: W9 [4744r,4768r:0)  0@4744r

selectOrSplit GPR64:%vreg975 [4752r,4768r:0)  0@4752r w=inf
assigning %vreg975 to %X8: W8 [4752r,4768r:0)  0@4752r

selectOrSplit GPR64common:%vreg976 [4768r,4784r:0)  0@4768r w=inf
assigning %vreg976 to %X8: W8 [4768r,4784r:0)  0@4768r

selectOrSplit GPR32:%vreg970 [4784r,4816r:0)  0@4784r w=2.620254e-05
assigning %vreg970 to %W8: W8 [4784r,4816r:0)  0@4784r

selectOrSplit GPR64common:%vreg968 [4800r,4816r:0)  0@4800r w=inf
assigning %vreg968 to %X9: W9 [4800r,4816r:0)  0@4800r

selectOrSplit GPR64common:%vreg965 [4832r,4880r:0)  0@4832r w=3.790011e-05
assigning %vreg965 to %X8: W8 [4832r,4880r:0)  0@4832r

selectOrSplit GPR32common:%vreg964 [4848r,4864r:0)  0@4848r w=inf
assigning %vreg964 to %W9: W9 [4848r,4864r:0)  0@4848r

selectOrSplit GPR32common:%vreg963 [4864r,4880r:0)  0@4864r w=inf
assigning %vreg963 to %W9: W9 [4864r,4880r:0)  0@4864r

selectOrSplit GPR64common:%vreg959 [4896r,4912r:0)  0@4896r w=inf
assigning %vreg959 to %X8: W8 [4896r,4912r:0)  0@4896r

selectOrSplit GPR32common:%vreg958 [4912r,4928r:0)  0@4912r w=inf
assigning %vreg958 to %W8: W8 [4912r,4928r:0)  0@4912r

selectOrSplit GPR64common:%vreg984 [4976r,4992r:0)  0@4976r w=inf
assigning %vreg984 to %X8: W8 [4976r,4992r:0)  0@4976r

selectOrSplit GPR32:%vreg1014 [5048r,5240r:0)  0@5048r w=3.831653e-05
assigning %vreg1014 to %W8: W8 [5048r,5240r:0)  0@5048r

selectOrSplit GPR64common:%vreg1024 [5088r,5136r:0)  0@5088r w=7.594884e-05
assigning %vreg1024 to %X9: W9 [5088r,5136r:0)  0@5088r

selectOrSplit GPR32common:%vreg1023 [5104r,5120r:0)  0@5104r w=inf
assigning %vreg1023 to %W10: W10 [5104r,5120r:0)  0@5104r

selectOrSplit GPR32common:%vreg1022 [5120r,5136r:0)  0@5120r w=inf
assigning %vreg1022 to %W10: W10 [5120r,5136r:0)  0@5120r

selectOrSplit GPR64common:%vreg1018 [5152r,5168r:0)  0@5152r w=inf
assigning %vreg1018 to %X9: W9 [5152r,5168r:0)  0@5152r

selectOrSplit GPR32common:%vreg1017 [5168r,5232r:0)  0@5168r w=4.888661e-05
assigning %vreg1017 to %W9: W9 [5168r,5232r:0)  0@5168r

selectOrSplit GPR32:%vreg1011 [5216r,5248r:0)  0@5216r w=5.250784e-05
assigning %vreg1011 to %W10: W10 [5216r,5248r:0)  0@5216r

selectOrSplit GPR32:%vreg1013 [5224r,5240r:0)  0@5224r w=2.726368e-05
assigning %vreg1013 to %W11: W11 [5224r,5240r:0)  0@5224r

selectOrSplit GPR32:%vreg1015 [5240r,5248r:0)  0@5240r w=inf
assigning %vreg1015 to %W8: W8 [5240r,5248r:0)  0@5240r

selectOrSplit GPR32:%vreg1005 [5248r,5264r:0)  0@5248r w=inf
assigning %vreg1005 to %W8: W8 [5248r,5264r:0)  0@5248r

selectOrSplit GPR64common:%vreg1002 [5280r,5328r:0)  0@5280r w=7.594884e-05
assigning %vreg1002 to %X8: W8 [5280r,5328r:0)  0@5280r

selectOrSplit GPR32common:%vreg1001 [5296r,5312r:0)  0@5296r w=inf
assigning %vreg1001 to %W9: W9 [5296r,5312r:0)  0@5296r

selectOrSplit GPR32common:%vreg1000 [5312r,5328r:0)  0@5312r w=inf
assigning %vreg1000 to %W9: W9 [5312r,5328r:0)  0@5312r

selectOrSplit GPR64:%vreg993 [5376r,5408r:0)  0@5376r w=5.250784e-05
assigning %vreg993 to %X8: W8 [5376r,5408r:0)  0@5376r

selectOrSplit GPR64common:%vreg996 [5384r,5432r:0)  0@5384r w=5.063256e-05
assigning %vreg996 to %X9: W9 [5384r,5432r:0)  0@5384r

selectOrSplit GPR64:%vreg990 [5392r,5408r:0)  0@5392r w=inf
assigning %vreg990 to %X10: W10 [5392r,5408r:0)  0@5392r

selectOrSplit GPR64common:%vreg991 [5408r,5424r:0)  0@5408r w=inf
assigning %vreg991 to %X8: W8 [5408r,5424r:0)  0@5408r

selectOrSplit GPR32common:%vreg992 [5424r,5440r:0)  0@5424r w=5.452737e-05
assigning %vreg992 to %W8: W8 [5424r,5440r:0)  0@5424r

selectOrSplit GPR32:%vreg995 [5432r,5456r:0)  0@5432r w=5.349855e-05
assigning %vreg995 to %W9: W9 [5432r,5456r:0)  0@5432r

selectOrSplit GPR32common:%vreg988 [5440r,5456r:0)  0@5440r w=inf
assigning %vreg988 to %W8: W8 [5440r,5456r:0)  0@5440r

selectOrSplit GPR64common:%vreg1029 [5552r,5568r:0)  0@5552r w=2.721033e-05
assigning %vreg1029 to %X8: W8 [5552r,5568r:0)  0@5552r

selectOrSplit GPR32:%vreg1032 [5560r,5584r:0)  0@5560r w=2.669693e-05
assigning %vreg1032 to %W9: W9 [5560r,5584r:0)  0@5560r

selectOrSplit GPR32:%vreg1028 [5568r,5584r:0)  0@5568r w=inf
assigning %vreg1028 to %W8: W8 [5568r,5584r:0)  0@5568r

selectOrSplit GPR32:%vreg1457 [5632r,5664r:0)  0@5632r w=1.304989e-05
assigning %vreg1457 to %W8: W8 [5632r,5664r:0)  0@5632r

selectOrSplit GPR64common:%vreg1454 [5648r,5664r:0)  0@5648r w=inf
assigning %vreg1454 to %X9: W9 [5648r,5664r:0)  0@5648r

selectOrSplit GPR64common:%vreg1106 [5728r,5744r:0)  0@5728r w=1.355181e-05
assigning %vreg1106 to %X8: W8 [5728r,5744r:0)  0@5728r

selectOrSplit GPR32:%vreg1104 [5736r,5744r:0)  0@5736r w=inf
assigning %vreg1104 to %W9: W9 [5736r,5744r:0)  0@5736r

selectOrSplit GPR64common:%vreg1103 [5760r,5800r:0)  0@5760r w=1.281262e-05
assigning %vreg1103 to %X8: W8 [5760r,5800r:0)  0@5760r

selectOrSplit GPR64common:%vreg1100 [5792r,5808r:0)  0@5792r w=1.355181e-05
assigning %vreg1100 to %X9: W9 [5792r,5808r:0)  0@5792r

selectOrSplit GPR32:%vreg1048 [5920r,6368r:0)  0@5920r w=3.324029e-06
assigning %vreg1048 to %W8: W8 [5920r,6368r:0)  0@5920r

selectOrSplit GPR64common:%vreg1090 [6016r,6072r:0)  0@6016r w=1.236306e-05
assigning %vreg1090 to %X9: W9 [6016r,6072r:0)  0@6016r

selectOrSplit GPR64common:%vreg1083 [6064r,6164r:0)  0@6064r w=1.127511e-05
assigning %vreg1083 to %X10: W10 [6064r,6164r:0)  0@6064r

selectOrSplit GPR64:%vreg1089 [6072r,6168r:0)  0@6072r w=1.136604e-05
assigning %vreg1089 to %X9: W9 [6072r,6168r:0)  0@6072r

selectOrSplit GPR64:%vreg1078 [6096r,6168r:0)  0@6096r w=5.971985e-06
assigning %vreg1078 to %X11: W11 [6096r,6168r:0)  0@6096r

selectOrSplit GPR64common:%vreg1071 [6160r,6244r:0)  0@6160r w=1.164784e-05
assigning %vreg1071 to %X12: W12 [6160r,6244r:0)  0@6160r

selectOrSplit GPR64:%vreg1082 [6164r,6248r:0)  0@6164r w=1.164784e-05
assigning %vreg1082 to %X10: W10 [6164r,6248r:0)  0@6164r

selectOrSplit GPR64:%vreg1079 [6168r,6248r:0)  0@6168r w=1.174490e-05
assigning %vreg1079 to %X9: W9 [6168r,6248r:0)  0@6168r

selectOrSplit GPR64common:%vreg1063 [6240r,6312r:0)  0@6240r w=1.194397e-05
assigning %vreg1063 to %X11: W11 [6240r,6312r:0)  0@6240r

selectOrSplit GPR32:%vreg1070 [6244r,6320r:0)  0@6244r w=1.184360e-05
assigning %vreg1070 to %W12: W12 [6244r,6320r:0)  0@6244r

selectOrSplit GPR64common:%vreg1080 [6248r,6360r:0)  0@6248r w=1.101085e-05
assigning %vreg1080 to %X9: W9 [6248r,6360r:0)  0@6248r

selectOrSplit GPR64common:%vreg1053 [6304r,6336r:0)  0@6304r w=1.304989e-05
assigning %vreg1053 to %X10: W10 [6304r,6336r:0)  0@6304r

selectOrSplit GPR64:%vreg1062 [6312r,6344r:0)  0@6312r w=1.304989e-05
assigning %vreg1062 to %X11: W11 [6312r,6344r:0)  0@6312r

selectOrSplit GPR64:%vreg1065 [6320r,6328r:0)  0@6320r w=inf
assigning %vreg1065 to %X12: W12 [6320r,6328r:0)  0@6320r

selectOrSplit GPR64:%vreg1066 [6328r,6344r:0)  0@6328r w=1.355181e-05
assigning %vreg1066 to %X12: W12 [6328r,6344r:0)  0@6328r

selectOrSplit GPR32:%vreg1052 [6336r,6368r:0)  0@6336r w=1.304989e-05
assigning %vreg1052 to %W10: W10 [6336r,6368r:0)  0@6336r

selectOrSplit GPR64common:%vreg1060 [6344r,6352r:0)  0@6344r w=inf
assigning %vreg1060 to %X11: W11 [6344r,6352r:0)  0@6344r

selectOrSplit GPR32:%vreg1057 [6352r,6408r:0)  0@6352r w=1.236306e-05
assigning %vreg1057 to %W11: W11 [6352r,6408r:0)  0@6352r

selectOrSplit GPR32:%vreg1075 [6360r,6424r:0)  0@6360r w=1.214990e-05
assigning %vreg1075 to %W9: W9 [6360r,6424r:0)  0@6360r

selectOrSplit GPR32:%vreg1050 [6368r,6408r:0)  0@6368r w=1.281262e-05
assigning %vreg1050 to %W8: W8 [6368r,6408r:0)  0@6368r

selectOrSplit GPR64common:%vreg1039 [6400r,6432r:0)  0@6400r w=1.304989e-05
assigning %vreg1039 to %X10: W10 [6400r,6432r:0)  0@6400r

selectOrSplit GPR32:%vreg1047 [6408r,6416r:0)  0@6408r w=inf
assigning %vreg1047 to %W8: W8 [6408r,6416r:0)  0@6408r

selectOrSplit GPR32common:%vreg1044 [6416r,6424r:0)  0@6416r w=inf
assigning %vreg1044 to %W8: W8 [6416r,6424r:0)  0@6416r

selectOrSplit GPR32:%vreg1042 [6424r,6432r:0)  0@6424r w=inf
assigning %vreg1042 to %W8: W8 [6424r,6432r:0)  0@6424r

selectOrSplit GPR64common:%vreg1036 [6440r,6448r:0)  0@6440r w=inf
assigning %vreg1036 to %X8: W8 [6440r,6448r:0)  0@6440r

selectOrSplit GPR32:%vreg1035 [6448r,6464r:0)  0@6448r w=inf
assigning %vreg1035 to %W8: W8 [6448r,6464r:0)  0@6448r

selectOrSplit GPR64common:%vreg1133 [6528r,6544r:0)  0@6528r w=inf
assigning %vreg1133 to %X8: W8 [6528r,6544r:0)  0@6528r

selectOrSplit GPR64:%vreg1132 [6544r,6576r:0)  0@6544r w=6.473569e-06
assigning %vreg1132 to %X8: W8 [6544r,6576r:0)  0@6544r

selectOrSplit GPR64common:%vreg1122 [6552r,6568r:0)  0@6552r w=3.361276e-06
assigning %vreg1122 to %X9: W9 [6552r,6568r:0)  0@6552r

selectOrSplit GPR64:%vreg1125 [6560r,6576r:0)  0@6560r w=3.361276e-06
assigning %vreg1125 to %X10: W10 [6560r,6576r:0)  0@6560r

selectOrSplit GPR64common:%vreg1123 [6568r,6592r:0)  0@6568r w=6.595712e-06
assigning %vreg1123 to %X9: W9 [6568r,6592r:0)  0@6568r

selectOrSplit GPR64:%vreg1126 [6576r,6592r:0)  0@6576r w=inf
assigning %vreg1126 to %X8: W8 [6576r,6592r:0)  0@6576r

selectOrSplit GPR64common:%vreg1127 [6592r,6608r:0)  0@6592r w=inf
assigning %vreg1127 to %X8: W8 [6592r,6608r:0)  0@6592r

selectOrSplit GPR32:%vreg1121 [6608r,6640r:0)  0@6608r w=6.473569e-06
assigning %vreg1121 to %W8: W8 [6608r,6640r:0)  0@6608r

selectOrSplit GPR64common:%vreg1119 [6624r,6640r:0)  0@6624r w=inf
assigning %vreg1119 to %X9: W9 [6624r,6640r:0)  0@6624r

selectOrSplit GPR64common:%vreg1116 [6656r,6704r:0)  0@6656r w=9.363555e-06
assigning %vreg1116 to %X8: W8 [6656r,6704r:0)  0@6656r

selectOrSplit GPR32common:%vreg1115 [6672r,6688r:0)  0@6672r w=inf
assigning %vreg1115 to %W9: W9 [6672r,6688r:0)  0@6672r

selectOrSplit GPR32common:%vreg1114 [6688r,6704r:0)  0@6688r w=inf
assigning %vreg1114 to %W9: W9 [6688r,6704r:0)  0@6688r

selectOrSplit GPR64common:%vreg1110 [6720r,6736r:0)  0@6720r w=inf
assigning %vreg1110 to %X8: W8 [6720r,6736r:0)  0@6720r

selectOrSplit GPR32common:%vreg1109 [6736r,6752r:0)  0@6736r w=inf
assigning %vreg1109 to %W8: W8 [6736r,6752r:0)  0@6736r

selectOrSplit GPR64common:%vreg1135 [6800r,6816r:0)  0@6800r w=inf
assigning %vreg1135 to %X8: W8 [6800r,6816r:0)  0@6800r

selectOrSplit GPR32:%vreg1165 [6872r,7064r:0)  0@6872r w=9.522895e-06
assigning %vreg1165 to %W8: W8 [6872r,7064r:0)  0@6872r

selectOrSplit GPR64common:%vreg1175 [6912r,6960r:0)  0@6912r w=1.887574e-05
assigning %vreg1175 to %X9: W9 [6912r,6960r:0)  0@6912r

selectOrSplit GPR32common:%vreg1174 [6928r,6944r:0)  0@6928r w=inf
assigning %vreg1174 to %W10: W10 [6928r,6944r:0)  0@6928r

selectOrSplit GPR32common:%vreg1173 [6944r,6960r:0)  0@6944r w=inf
assigning %vreg1173 to %W10: W10 [6944r,6960r:0)  0@6944r

selectOrSplit GPR64common:%vreg1169 [6976r,6992r:0)  0@6976r w=inf
assigning %vreg1169 to %X9: W9 [6976r,6992r:0)  0@6976r

selectOrSplit GPR32common:%vreg1168 [6992r,7056r:0)  0@6992r w=1.214990e-05
assigning %vreg1168 to %W9: W9 [6992r,7056r:0)  0@6992r

selectOrSplit GPR32:%vreg1162 [7040r,7072r:0)  0@7040r w=1.304989e-05
assigning %vreg1162 to %W10: W10 [7040r,7072r:0)  0@7040r

selectOrSplit GPR32:%vreg1164 [7048r,7064r:0)  0@7048r w=6.775906e-06
assigning %vreg1164 to %W11: W11 [7048r,7064r:0)  0@7048r

selectOrSplit GPR32:%vreg1166 [7064r,7072r:0)  0@7064r w=inf
assigning %vreg1166 to %W8: W8 [7064r,7072r:0)  0@7064r

selectOrSplit GPR32:%vreg1156 [7072r,7088r:0)  0@7072r w=inf
assigning %vreg1156 to %W8: W8 [7072r,7088r:0)  0@7072r

selectOrSplit GPR64common:%vreg1153 [7104r,7152r:0)  0@7104r w=1.887574e-05
assigning %vreg1153 to %X8: W8 [7104r,7152r:0)  0@7104r

selectOrSplit GPR32common:%vreg1152 [7120r,7136r:0)  0@7120r w=inf
assigning %vreg1152 to %W9: W9 [7120r,7136r:0)  0@7120r

selectOrSplit GPR32common:%vreg1151 [7136r,7152r:0)  0@7136r w=inf
assigning %vreg1151 to %W9: W9 [7136r,7152r:0)  0@7136r

selectOrSplit GPR64:%vreg1144 [7200r,7232r:0)  0@7200r w=1.304989e-05
assigning %vreg1144 to %X8: W8 [7200r,7232r:0)  0@7200r

selectOrSplit GPR64common:%vreg1147 [7208r,7256r:0)  0@7208r w=1.258383e-05
assigning %vreg1147 to %X9: W9 [7208r,7256r:0)  0@7208r

selectOrSplit GPR64:%vreg1141 [7216r,7232r:0)  0@7216r w=inf
assigning %vreg1141 to %X10: W10 [7216r,7232r:0)  0@7216r

selectOrSplit GPR64common:%vreg1142 [7232r,7248r:0)  0@7232r w=inf
assigning %vreg1142 to %X8: W8 [7232r,7248r:0)  0@7232r

selectOrSplit GPR32common:%vreg1143 [7248r,7264r:0)  0@7248r w=1.355181e-05
assigning %vreg1143 to %W8: W8 [7248r,7264r:0)  0@7248r

selectOrSplit GPR32:%vreg1146 [7256r,7280r:0)  0@7256r w=1.329612e-05
assigning %vreg1146 to %W9: W9 [7256r,7280r:0)  0@7256r

selectOrSplit GPR32common:%vreg1139 [7264r,7280r:0)  0@7264r w=inf
assigning %vreg1139 to %W8: W8 [7264r,7280r:0)  0@7264r

selectOrSplit GPR64common:%vreg1180 [7376r,7392r:0)  0@7376r w=6.722553e-06
assigning %vreg1180 to %X8: W8 [7376r,7392r:0)  0@7376r

selectOrSplit GPR32:%vreg1183 [7384r,7408r:0)  0@7384r w=6.595712e-06
assigning %vreg1183 to %W9: W9 [7384r,7408r:0)  0@7384r

selectOrSplit GPR32:%vreg1179 [7392r,7408r:0)  0@7392r w=inf
assigning %vreg1179 to %W8: W8 [7392r,7408r:0)  0@7392r

selectOrSplit GPR32:%vreg1451 [7456r,7488r:0)  0@7456r w=3.185407e-06
assigning %vreg1451 to %W8: W8 [7456r,7488r:0)  0@7456r

selectOrSplit GPR64common:%vreg1448 [7472r,7488r:0)  0@7472r w=inf
assigning %vreg1448 to %X9: W9 [7472r,7488r:0)  0@7472r

selectOrSplit GPR64common:%vreg1254 [7536r,7576r:0)  0@7536r w=3.127491e-06
assigning %vreg1254 to %X8: W8 [7536r,7576r:0)  0@7536r

selectOrSplit GPR64common:%vreg1251 [7568r,7584r:0)  0@7568r w=3.307923e-06
assigning %vreg1251 to %X9: W9 [7568r,7584r:0)  0@7568r

selectOrSplit GPR32:%vreg1199 [7696r,8144r:0)  0@7696r w=8.113772e-07
assigning %vreg1199 to %W8: W8 [7696r,8144r:0)  0@7696r

selectOrSplit GPR64common:%vreg1241 [7792r,7848r:0)  0@7792r w=3.017754e-06
assigning %vreg1241 to %X9: W9 [7792r,7848r:0)  0@7792r

selectOrSplit GPR64common:%vreg1234 [7840r,7940r:0)  0@7840r w=2.752192e-06
assigning %vreg1234 to %X10: W10 [7840r,7940r:0)  0@7840r

selectOrSplit GPR64:%vreg1240 [7848r,7944r:0)  0@7848r w=2.774387e-06
assigning %vreg1240 to %X9: W9 [7848r,7944r:0)  0@7848r

selectOrSplit GPR64:%vreg1229 [7872r,7944r:0)  0@7872r w=1.457729e-06
assigning %vreg1229 to %X11: W11 [7872r,7944r:0)  0@7872r

selectOrSplit GPR64common:%vreg1222 [7936r,8020r:0)  0@7936r w=2.843173e-06
assigning %vreg1222 to %X12: W12 [7936r,8020r:0)  0@7936r

selectOrSplit GPR64:%vreg1233 [7940r,8024r:0)  0@7940r w=2.843173e-06
assigning %vreg1233 to %X10: W10 [7940r,8024r:0)  0@7940r

selectOrSplit GPR64:%vreg1230 [7944r,8024r:0)  0@7944r w=2.866866e-06
assigning %vreg1230 to %X9: W9 [7944r,8024r:0)  0@7944r

selectOrSplit GPR64common:%vreg1214 [8016r,8088r:0)  0@8016r w=2.915457e-06
assigning %vreg1214 to %X11: W11 [8016r,8088r:0)  0@8016r

selectOrSplit GPR32:%vreg1221 [8020r,8096r:0)  0@8020r w=2.890958e-06
assigning %vreg1221 to %W12: W12 [8020r,8096r:0)  0@8020r

selectOrSplit GPR64common:%vreg1231 [8024r,8136r:0)  0@8024r w=2.687687e-06
assigning %vreg1231 to %X9: W9 [8024r,8136r:0)  0@8024r

selectOrSplit GPR64common:%vreg1204 [8080r,8112r:0)  0@8080r w=3.185407e-06
assigning %vreg1204 to %X10: W10 [8080r,8112r:0)  0@8080r

selectOrSplit GPR64:%vreg1213 [8088r,8120r:0)  0@8088r w=3.185407e-06
assigning %vreg1213 to %X11: W11 [8088r,8120r:0)  0@8088r

selectOrSplit GPR64:%vreg1216 [8096r,8104r:0)  0@8096r w=inf
assigning %vreg1216 to %X12: W12 [8096r,8104r:0)  0@8096r

selectOrSplit GPR64:%vreg1217 [8104r,8120r:0)  0@8104r w=3.307923e-06
assigning %vreg1217 to %X12: W12 [8104r,8120r:0)  0@8104r

selectOrSplit GPR32:%vreg1203 [8112r,8144r:0)  0@8112r w=3.185407e-06
assigning %vreg1203 to %W10: W10 [8112r,8144r:0)  0@8112r

selectOrSplit GPR64common:%vreg1211 [8120r,8128r:0)  0@8120r w=inf
assigning %vreg1211 to %X11: W11 [8120r,8128r:0)  0@8120r

selectOrSplit GPR32:%vreg1208 [8128r,8184r:0)  0@8128r w=3.017754e-06
assigning %vreg1208 to %W11: W11 [8128r,8184r:0)  0@8128r

selectOrSplit GPR32:%vreg1226 [8136r,8200r:0)  0@8136r w=2.965724e-06
assigning %vreg1226 to %W9: W9 [8136r,8200r:0)  0@8136r

selectOrSplit GPR32:%vreg1201 [8144r,8184r:0)  0@8144r w=3.127491e-06
assigning %vreg1201 to %W8: W8 [8144r,8184r:0)  0@8144r

selectOrSplit GPR64common:%vreg1190 [8176r,8208r:0)  0@8176r w=3.185407e-06
assigning %vreg1190 to %X10: W10 [8176r,8208r:0)  0@8176r

selectOrSplit GPR32:%vreg1198 [8184r,8192r:0)  0@8184r w=inf
assigning %vreg1198 to %W8: W8 [8184r,8192r:0)  0@8184r

selectOrSplit GPR32common:%vreg1195 [8192r,8200r:0)  0@8192r w=inf
assigning %vreg1195 to %W8: W8 [8192r,8200r:0)  0@8192r

selectOrSplit GPR32:%vreg1193 [8200r,8208r:0)  0@8200r w=inf
assigning %vreg1193 to %W8: W8 [8200r,8208r:0)  0@8200r

selectOrSplit GPR64common:%vreg1187 [8216r,8224r:0)  0@8216r w=inf
assigning %vreg1187 to %X8: W8 [8216r,8224r:0)  0@8216r

selectOrSplit GPR32:%vreg1186 [8224r,8240r:0)  0@8224r w=inf
assigning %vreg1186 to %W8: W8 [8224r,8240r:0)  0@8224r

selectOrSplit GPR64common:%vreg1281 [8304r,8320r:0)  0@8304r w=inf
assigning %vreg1281 to %X8: W8 [8304r,8320r:0)  0@8304r

selectOrSplit GPR64:%vreg1280 [8320r,8352r:0)  0@8320r w=1.644081e-06
assigning %vreg1280 to %X8: W8 [8320r,8352r:0)  0@8320r

selectOrSplit GPR64common:%vreg1270 [8328r,8344r:0)  0@8328r w=8.536575e-07
assigning %vreg1270 to %X9: W9 [8328r,8344r:0)  0@8328r

selectOrSplit GPR64:%vreg1273 [8336r,8352r:0)  0@8336r w=8.536575e-07
assigning %vreg1273 to %X10: W10 [8336r,8352r:0)  0@8336r

selectOrSplit GPR64common:%vreg1271 [8344r,8368r:0)  0@8344r w=1.675101e-06
assigning %vreg1271 to %X9: W9 [8344r,8368r:0)  0@8344r

selectOrSplit GPR64:%vreg1274 [8352r,8368r:0)  0@8352r w=inf
assigning %vreg1274 to %X8: W8 [8352r,8368r:0)  0@8352r

selectOrSplit GPR64common:%vreg1275 [8368r,8384r:0)  0@8368r w=inf
assigning %vreg1275 to %X8: W8 [8368r,8384r:0)  0@8368r

selectOrSplit GPR32:%vreg1269 [8384r,8416r:0)  0@8384r w=1.644081e-06
assigning %vreg1269 to %W8: W8 [8384r,8416r:0)  0@8384r

selectOrSplit GPR64common:%vreg1267 [8400r,8416r:0)  0@8400r w=inf
assigning %vreg1267 to %X9: W9 [8400r,8416r:0)  0@8400r

selectOrSplit GPR64common:%vreg1264 [8432r,8480r:0)  0@8432r w=2.378046e-06
assigning %vreg1264 to %X8: W8 [8432r,8480r:0)  0@8432r

selectOrSplit GPR32common:%vreg1263 [8448r,8464r:0)  0@8448r w=inf
assigning %vreg1263 to %W9: W9 [8448r,8464r:0)  0@8448r

selectOrSplit GPR32common:%vreg1262 [8464r,8480r:0)  0@8464r w=inf
assigning %vreg1262 to %W9: W9 [8464r,8480r:0)  0@8464r

selectOrSplit GPR64common:%vreg1258 [8496r,8512r:0)  0@8496r w=inf
assigning %vreg1258 to %X8: W8 [8496r,8512r:0)  0@8496r

selectOrSplit GPR32common:%vreg1257 [8512r,8528r:0)  0@8512r w=inf
assigning %vreg1257 to %W8: W8 [8512r,8528r:0)  0@8512r

selectOrSplit GPR64common:%vreg1283 [8576r,8592r:0)  0@8576r w=inf
assigning %vreg1283 to %X8: W8 [8576r,8592r:0)  0@8576r

selectOrSplit GPR32:%vreg1380 [8648r,8840r:0)  0@8648r w=2.324486e-06
assigning %vreg1380 to %W8: W8 [8648r,8840r:0)  0@8648r

selectOrSplit GPR64common:%vreg1390 [8688r,8736r:0)  0@8688r w=4.607464e-06
assigning %vreg1390 to %X9: W9 [8688r,8736r:0)  0@8688r

selectOrSplit GPR32common:%vreg1389 [8704r,8720r:0)  0@8704r w=inf
assigning %vreg1389 to %W10: W10 [8704r,8720r:0)  0@8704r

selectOrSplit GPR32common:%vreg1388 [8720r,8736r:0)  0@8720r w=inf
assigning %vreg1388 to %W10: W10 [8720r,8736r:0)  0@8720r

selectOrSplit GPR64common:%vreg1384 [8752r,8768r:0)  0@8752r w=inf
assigning %vreg1384 to %X9: W9 [8752r,8768r:0)  0@8752r

selectOrSplit GPR32common:%vreg1383 [8768r,8832r:0)  0@8768r w=2.965724e-06
assigning %vreg1383 to %W9: W9 [8768r,8832r:0)  0@8768r

selectOrSplit GPR32:%vreg1377 [8816r,8848r:0)  0@8816r w=3.185407e-06
assigning %vreg1377 to %W10: W10 [8816r,8848r:0)  0@8816r

selectOrSplit GPR32:%vreg1379 [8824r,8840r:0)  0@8824r w=1.653961e-06
assigning %vreg1379 to %W11: W11 [8824r,8840r:0)  0@8824r

selectOrSplit GPR32:%vreg1381 [8840r,8848r:0)  0@8840r w=inf
assigning %vreg1381 to %W8: W8 [8840r,8848r:0)  0@8840r

selectOrSplit GPR32:%vreg1371 [8848r,8864r:0)  0@8848r w=inf
assigning %vreg1371 to %W8: W8 [8848r,8864r:0)  0@8848r

selectOrSplit GPR64common:%vreg1368 [8880r,8928r:0)  0@8880r w=4.607464e-06
assigning %vreg1368 to %X8: W8 [8880r,8928r:0)  0@8880r

selectOrSplit GPR32common:%vreg1367 [8896r,8912r:0)  0@8896r w=inf
assigning %vreg1367 to %W9: W9 [8896r,8912r:0)  0@8896r

selectOrSplit GPR32common:%vreg1366 [8912r,8928r:0)  0@8912r w=inf
assigning %vreg1366 to %W9: W9 [8912r,8928r:0)  0@8912r

selectOrSplit GPR32common:%vreg1362 [8944r,8984r:0)  0@8944r w=3.127491e-06
assigning %vreg1362 to %W8: W8 [8944r,8984r:0)  0@8944r

selectOrSplit GPR64common:%vreg1357 [8976r,8992r:0)  0@8976r w=3.307923e-06
assigning %vreg1357 to %X9: W9 [8976r,8992r:0)  0@8976r

selectOrSplit GPR32common:%vreg1359 [8984r,8992r:0)  0@8984r w=inf
assigning %vreg1359 to %W8: W8 [8984r,8992r:0)  0@8984r

selectOrSplit GPR64common:%vreg1354 [9008r,9048r:0)  0@9008r w=3.127491e-06
assigning %vreg1354 to %X8: W8 [9008r,9048r:0)  0@9008r

selectOrSplit GPR64common:%vreg1351 [9040r,9056r:0)  0@9040r w=3.307923e-06
assigning %vreg1351 to %X9: W9 [9040r,9056r:0)  0@9040r

selectOrSplit GPR32:%vreg1299 [9168r,9616r:0)  0@9168r w=8.113772e-07
assigning %vreg1299 to %W8: W8 [9168r,9616r:0)  0@9168r

selectOrSplit GPR64common:%vreg1344 [9232r,9248r:0)  0@9232r w=inf
assigning %vreg1344 to %X9: W9 [9232r,9248r:0)  0@9232r

selectOrSplit GPR64common:%vreg1341 [9264r,9320r:0)  0@9264r w=3.017754e-06
assigning %vreg1341 to %X9: W9 [9264r,9320r:0)  0@9264r

selectOrSplit GPR64common:%vreg1334 [9312r,9412r:0)  0@9312r w=2.752192e-06
assigning %vreg1334 to %X10: W10 [9312r,9412r:0)  0@9312r

selectOrSplit GPR64:%vreg1340 [9320r,9416r:0)  0@9320r w=2.774387e-06
assigning %vreg1340 to %X9: W9 [9320r,9416r:0)  0@9320r

selectOrSplit GPR64:%vreg1329 [9344r,9416r:0)  0@9344r w=1.457729e-06
assigning %vreg1329 to %X11: W11 [9344r,9416r:0)  0@9344r

selectOrSplit GPR64common:%vreg1322 [9408r,9492r:0)  0@9408r w=2.843173e-06
assigning %vreg1322 to %X12: W12 [9408r,9492r:0)  0@9408r

selectOrSplit GPR64:%vreg1333 [9412r,9496r:0)  0@9412r w=2.843173e-06
assigning %vreg1333 to %X10: W10 [9412r,9496r:0)  0@9412r

selectOrSplit GPR64:%vreg1330 [9416r,9496r:0)  0@9416r w=2.866866e-06
assigning %vreg1330 to %X9: W9 [9416r,9496r:0)  0@9416r

selectOrSplit GPR64common:%vreg1314 [9488r,9560r:0)  0@9488r w=2.915457e-06
assigning %vreg1314 to %X11: W11 [9488r,9560r:0)  0@9488r

selectOrSplit GPR32:%vreg1321 [9492r,9568r:0)  0@9492r w=2.890958e-06
assigning %vreg1321 to %W12: W12 [9492r,9568r:0)  0@9492r

selectOrSplit GPR64common:%vreg1331 [9496r,9608r:0)  0@9496r w=2.687687e-06
assigning %vreg1331 to %X9: W9 [9496r,9608r:0)  0@9496r

selectOrSplit GPR64common:%vreg1304 [9552r,9584r:0)  0@9552r w=3.185407e-06
assigning %vreg1304 to %X10: W10 [9552r,9584r:0)  0@9552r

selectOrSplit GPR64:%vreg1313 [9560r,9592r:0)  0@9560r w=3.185407e-06
assigning %vreg1313 to %X11: W11 [9560r,9592r:0)  0@9560r

selectOrSplit GPR64:%vreg1316 [9568r,9576r:0)  0@9568r w=inf
assigning %vreg1316 to %X12: W12 [9568r,9576r:0)  0@9568r

selectOrSplit GPR64:%vreg1317 [9576r,9592r:0)  0@9576r w=3.307923e-06
assigning %vreg1317 to %X12: W12 [9576r,9592r:0)  0@9576r

selectOrSplit GPR32:%vreg1303 [9584r,9616r:0)  0@9584r w=3.185407e-06
assigning %vreg1303 to %W10: W10 [9584r,9616r:0)  0@9584r

selectOrSplit GPR64common:%vreg1311 [9592r,9600r:0)  0@9592r w=inf
assigning %vreg1311 to %X11: W11 [9592r,9600r:0)  0@9592r

selectOrSplit GPR32:%vreg1308 [9600r,9656r:0)  0@9600r w=3.017754e-06
assigning %vreg1308 to %W11: W11 [9600r,9656r:0)  0@9600r

selectOrSplit GPR32:%vreg1326 [9608r,9672r:0)  0@9608r w=2.965724e-06
assigning %vreg1326 to %W9: W9 [9608r,9672r:0)  0@9608r

selectOrSplit GPR32:%vreg1301 [9616r,9656r:0)  0@9616r w=3.127491e-06
assigning %vreg1301 to %W8: W8 [9616r,9656r:0)  0@9616r

selectOrSplit GPR64common:%vreg1290 [9648r,9680r:0)  0@9648r w=3.185407e-06
assigning %vreg1290 to %X10: W10 [9648r,9680r:0)  0@9648r

selectOrSplit GPR32:%vreg1298 [9656r,9664r:0)  0@9656r w=inf
assigning %vreg1298 to %W8: W8 [9656r,9664r:0)  0@9656r

selectOrSplit GPR32common:%vreg1295 [9664r,9672r:0)  0@9664r w=inf
assigning %vreg1295 to %W8: W8 [9664r,9672r:0)  0@9664r

selectOrSplit GPR32:%vreg1293 [9672r,9680r:0)  0@9672r w=inf
assigning %vreg1293 to %W8: W8 [9672r,9680r:0)  0@9672r

selectOrSplit GPR64common:%vreg1287 [9688r,9696r:0)  0@9688r w=inf
assigning %vreg1287 to %X8: W8 [9688r,9696r:0)  0@9688r

selectOrSplit GPR32:%vreg1286 [9696r,9712r:0)  0@9696r w=inf
assigning %vreg1286 to %W8: W8 [9696r,9712r:0)  0@9696r

selectOrSplit GPR64common:%vreg1417 [9776r,9792r:0)  0@9776r w=inf
assigning %vreg1417 to %X8: W8 [9776r,9792r:0)  0@9776r

selectOrSplit GPR64:%vreg1416 [9792r,9824r:0)  0@9792r w=1.644081e-06
assigning %vreg1416 to %X8: W8 [9792r,9824r:0)  0@9792r

selectOrSplit GPR64common:%vreg1406 [9800r,9816r:0)  0@9800r w=8.536575e-07
assigning %vreg1406 to %X9: W9 [9800r,9816r:0)  0@9800r

selectOrSplit GPR64:%vreg1409 [9808r,9824r:0)  0@9808r w=8.536575e-07
assigning %vreg1409 to %X10: W10 [9808r,9824r:0)  0@9808r

selectOrSplit GPR64common:%vreg1407 [9816r,9840r:0)  0@9816r w=1.675101e-06
assigning %vreg1407 to %X9: W9 [9816r,9840r:0)  0@9816r

selectOrSplit GPR64:%vreg1410 [9824r,9840r:0)  0@9824r w=inf
assigning %vreg1410 to %X8: W8 [9824r,9840r:0)  0@9824r

selectOrSplit GPR64common:%vreg1411 [9840r,9856r:0)  0@9840r w=inf
assigning %vreg1411 to %X8: W8 [9840r,9856r:0)  0@9840r

selectOrSplit GPR32:%vreg1405 [9856r,9888r:0)  0@9856r w=1.644081e-06
assigning %vreg1405 to %W8: W8 [9856r,9888r:0)  0@9856r

selectOrSplit GPR64common:%vreg1403 [9872r,9888r:0)  0@9872r w=inf
assigning %vreg1403 to %X9: W9 [9872r,9888r:0)  0@9872r

selectOrSplit GPR64common:%vreg1400 [9904r,9952r:0)  0@9904r w=2.378046e-06
assigning %vreg1400 to %X8: W8 [9904r,9952r:0)  0@9904r

selectOrSplit GPR32common:%vreg1399 [9920r,9936r:0)  0@9920r w=inf
assigning %vreg1399 to %W9: W9 [9920r,9936r:0)  0@9920r

selectOrSplit GPR32common:%vreg1398 [9936r,9952r:0)  0@9936r w=inf
assigning %vreg1398 to %W9: W9 [9936r,9952r:0)  0@9936r

selectOrSplit GPR64common:%vreg1394 [9968r,9984r:0)  0@9968r w=inf
assigning %vreg1394 to %X8: W8 [9968r,9984r:0)  0@9968r

selectOrSplit GPR32common:%vreg1393 [9984r,10000r:0)  0@9984r w=inf
assigning %vreg1393 to %W8: W8 [9984r,10000r:0)  0@9984r

selectOrSplit GPR64common:%vreg1419 [10048r,10064r:0)  0@10048r w=inf
assigning %vreg1419 to %X8: W8 [10048r,10064r:0)  0@10048r

selectOrSplit GPR32:%vreg1435 [10120r,10328r:0)  0@10120r w=2.263316e-06
assigning %vreg1435 to %W8: W8 [10120r,10328r:0)  0@10120r

selectOrSplit GPR64common:%vreg1445 [10160r,10208r:0)  0@10160r w=4.607464e-06
assigning %vreg1445 to %X9: W9 [10160r,10208r:0)  0@10160r

selectOrSplit GPR32common:%vreg1444 [10176r,10192r:0)  0@10176r w=inf
assigning %vreg1444 to %W10: W10 [10176r,10192r:0)  0@10176r

selectOrSplit GPR32common:%vreg1443 [10192r,10208r:0)  0@10192r w=inf
assigning %vreg1443 to %W10: W10 [10192r,10208r:0)  0@10192r

selectOrSplit GPR64common:%vreg1439 [10224r,10296r:0)  0@10224r w=2.915457e-06
assigning %vreg1439 to %X9: W9 [10224r,10296r:0)  0@10224r

selectOrSplit GPR64common:%vreg1432 [10288r,10344r:0)  0@10288r w=4.526631e-06
assigning %vreg1432 to %X10: W10 [10288r,10344r:0)  0@10288r

selectOrSplit GPR32common:%vreg1438 [10296r,10312r:0)  0@10296r w=3.307923e-06
assigning %vreg1438 to %W9: W9 [10296r,10312r:0)  0@10296r

selectOrSplit GPR32:%vreg1431 [10304r,10336r:0)  0@10304r w=3.185407e-06
assigning %vreg1431 to %W11: W11 [10304r,10336r:0)  0@10304r

selectOrSplit GPR32:%vreg1434 [10320r,10328r:0)  0@10320r w=inf
assigning %vreg1434 to %W9: W9 [10320r,10328r:0)  0@10320r

selectOrSplit GPR32:%vreg1436 [10328r,10336r:0)  0@10328r w=inf
assigning %vreg1436 to %W8: W8 [10328r,10336r:0)  0@10328r

selectOrSplit GPR32:%vreg1430 [10336r,10344r:0)  0@10336r w=inf
assigning %vreg1430 to %W8: W8 [10336r,10344r:0)  0@10336r

selectOrSplit GPR64common:%vreg1425 [10352r,10400r:0)  0@10352r w=4.607464e-06
assigning %vreg1425 to %X8: W8 [10352r,10400r:0)  0@10352r

selectOrSplit GPR32common:%vreg1424 [10368r,10384r:0)  0@10368r w=inf
assigning %vreg1424 to %W9: W9 [10368r,10384r:0)  0@10368r

selectOrSplit GPR32common:%vreg1423 [10384r,10400r:0)  0@10384r w=inf
assigning %vreg1423 to %W9: W9 [10384r,10400r:0)  0@10384r

selectOrSplit GPR64common:%vreg17 [10512r,10528r:0)  0@10512r w=inf
assigning %vreg17 to %X8: W8 [10512r,10528r:0)  0@10512r

selectOrSplit GPR64common:%vreg16 [10528r,10544r:0)  0@10528r w=inf
assigning %vreg16 to %X8: W8 [10528r,10544r:0)  0@10528r

selectOrSplit GPR32:%vreg14 [10544r,10560r:0)  0@10544r w=inf
assigning %vreg14 to %W8: W8 [10544r,10560r:0)  0@10544r

selectOrSplit GPR64common:%vreg21 [10640r,10656r:0)  0@10640r w=inf
assigning %vreg21 to %X8: W8 [10640r,10656r:0)  0@10640r

selectOrSplit GPR32:%vreg20 [10656r,10672r:0)  0@10656r w=inf
assigning %vreg20 to %W8: W8 [10656r,10672r:0)  0@10656r

selectOrSplit GPR64common:%vreg97 [10800r,10816r:0)  0@10800r w=8.740386e-04
assigning %vreg97 to %X8: W8 [10800r,10816r:0)  0@10800r

selectOrSplit GPR64common:%vreg100 [10808r,10824r:0)  0@10808r w=8.740386e-04
assigning %vreg100 to %X9: W9 [10808r,10824r:0)  0@10808r

selectOrSplit GPR64common:%vreg96 [10816r,10832r:0)  0@10816r w=8.740386e-04
assigning %vreg96 to %X8: W8 [10816r,10832r:0)  0@10816r

selectOrSplit GPR32:%vreg99 [10824r,10848r:0)  0@10824r w=8.575473e-04
assigning %vreg99 to %W9: W9 [10824r,10848r:0)  0@10824r

selectOrSplit GPR64common:%vreg94 [10832r,10848r:0)  0@10832r w=inf
assigning %vreg94 to %X8: W8 [10832r,10848r:0)  0@10832r

selectOrSplit GPR64common:%vreg87 [10896r,10968r:0)  0@10896r w=7.703391e-04
assigning %vreg87 to %X8: W8 [10896r,10968r:0)  0@10896r

selectOrSplit GPR64common:%vreg82 [10944r,10976r:0)  0@10944r w=8.416668e-04
assigning %vreg82 to %X9: W9 [10944r,10976r:0)  0@10944r

selectOrSplit GPR64common:%vreg66 [10952r,10984r:0)  0@10952r w=4.208334e-04
assigning %vreg66 to %X10: W10 [10952r,10984r:0)  0@10952r

selectOrSplit GPR64common:%vreg90 [10960r,10992r:0)  0@10960r w=8.416668e-04
assigning %vreg90 to %X11: W11 [10960r,10992r:0)  0@10960r

selectOrSplit GPR32:%vreg86 [10968r,11000r:0)  0@10968r w=8.416668e-04
assigning %vreg86 to %W8: W8 [10968r,11000r:0)  0@10968r

selectOrSplit GPR32:%vreg81 [10976r,11008r:0)  0@10976r w=8.416668e-04
assigning %vreg81 to %W9: W9 [10976r,11008r:0)  0@10976r

selectOrSplit GPR64common:%vreg67 [10984r,11056r:0)  0@10984r w=7.703391e-04
assigning %vreg67 to %X10: W10 [10984r,11056r:0)  0@10984r

selectOrSplit GPR32:%vreg89 [10992r,11112r:0)  0@10992r w=6.992309e-04
assigning %vreg89 to %W11: W11 [10992r,11112r:0)  0@10992r

selectOrSplit GPR32:%vreg84 [11000r,11008r:0)  0@11000r w=inf
assigning %vreg84 to %W8: W8 [11000r,11008r:0)  0@11000r

selectOrSplit GPR64:%vreg73 [11008r,11024r:0)  0@11008r w=inf
assigning %vreg73 to %X8: W8 [11008r,11024r:0)  0@11008r

selectOrSplit GPR64:%vreg74 [11024r,11040r:0)  0@11024r w=8.740386e-04
assigning %vreg74 to %X8: W8 [11024r,11040r:0)  0@11024r

selectOrSplit GPR64:%vreg69 [11032r,11040r:0)  0@11032r w=inf
assigning %vreg69 to %X9: W9 [11032r,11040r:0)  0@11032r

selectOrSplit GPR64:%vreg70 [11040r,11056r:0)  0@11040r w=inf
assigning %vreg70 to %X8: W8 [11040r,11056r:0)  0@11040r

selectOrSplit GPR64common:%vreg71 [11056r,11072r:0)  0@11056r w=inf
assigning %vreg71 to %X8: W8 [11056r,11072r:0)  0@11056r

selectOrSplit GPR32:%vreg65 [11072r,11112r:0)  0@11072r w=8.263637e-04
assigning %vreg65 to %W8: W8 [11072r,11112r:0)  0@11072r

selectOrSplit GPR64common:%vreg60 [11104r,11120r:0)  0@11104r w=8.740386e-04
assigning %vreg60 to %X9: W9 [11104r,11120r:0)  0@11104r

selectOrSplit GPR32:%vreg63 [11112r,11120r:0)  0@11112r w=inf
assigning %vreg63 to %W8: W8 [11112r,11120r:0)  0@11112r

selectOrSplit GPR64common:%vreg57 [11136r,11184r:0)  0@11136r w=1.217411e-03
assigning %vreg57 to %X8: W8 [11136r,11184r:0)  0@11136r

selectOrSplit GPR32common:%vreg56 [11152r,11168r:0)  0@11152r w=inf
assigning %vreg56 to %W9: W9 [11152r,11168r:0)  0@11152r

selectOrSplit GPR32common:%vreg55 [11168r,11184r:0)  0@11168r w=inf
assigning %vreg55 to %W9: W9 [11168r,11184r:0)  0@11168r

selectOrSplit GPR64common:%vreg51 [11200r,11216r:0)  0@11200r w=inf
assigning %vreg51 to %X8: W8 [11200r,11216r:0)  0@11200r

selectOrSplit GPR64common:%vreg50 [11216r,11264r:0)  0@11216r w=1.217411e-03
assigning %vreg50 to %X8: W8 [11216r,11264r:0)  0@11216r

selectOrSplit GPR64common:%vreg48 [11232r,11248r:0)  0@11232r w=inf
assigning %vreg48 to %X9: W9 [11232r,11248r:0)  0@11232r

selectOrSplit GPR64common:%vreg47 [11248r,11264r:0)  0@11248r w=inf
assigning %vreg47 to %X9: W9 [11248r,11264r:0)  0@11248r

selectOrSplit GPR64common:%vreg43 [11280r,11296r:0)  0@11280r w=inf
assigning %vreg43 to %X8: W8 [11280r,11296r:0)  0@11280r

selectOrSplit GPR64common:%vreg42 [11296r,11344r:0)  0@11296r w=1.217411e-03
assigning %vreg42 to %X8: W8 [11296r,11344r:0)  0@11296r

selectOrSplit GPR32common:%vreg40 [11312r,11328r:0)  0@11312r w=inf
assigning %vreg40 to %W9: W9 [11312r,11328r:0)  0@11312r

selectOrSplit GPR32common:%vreg39 [11328r,11344r:0)  0@11328r w=inf
assigning %vreg39 to %W9: W9 [11328r,11344r:0)  0@11328r

selectOrSplit GPR64common:%vreg35 [11360r,11376r:0)  0@11360r w=inf
assigning %vreg35 to %X8: W8 [11360r,11376r:0)  0@11360r

selectOrSplit GPR64common:%vreg34 [11376r,11424r:0)  0@11376r w=1.217411e-03
assigning %vreg34 to %X8: W8 [11376r,11424r:0)  0@11376r

selectOrSplit GPR32common:%vreg32 [11392r,11408r:0)  0@11392r w=inf
assigning %vreg32 to %W9: W9 [11392r,11408r:0)  0@11392r

selectOrSplit GPR32common:%vreg31 [11408r,11424r:0)  0@11408r w=inf
assigning %vreg31 to %W9: W9 [11408r,11424r:0)  0@11408r

selectOrSplit GPR64common:%vreg27 [11440r,11456r:0)  0@11440r w=inf
assigning %vreg27 to %X8: W8 [11440r,11456r:0)  0@11440r

selectOrSplit GPR64common:%vreg26 [11456r,11472r:0)  0@11456r w=inf
assigning %vreg26 to %X8: W8 [11456r,11472r:0)  0@11456r

selectOrSplit GPR32:%vreg24 [11472r,11488r:0)  0@11472r w=inf
assigning %vreg24 to %W8: W8 [11472r,11488r:0)  0@11472r

selectOrSplit GPR64common:%vreg108 [11520r,11536r:0)  0@11520r w=inf
assigning %vreg108 to %X8: W8 [11520r,11536r:0)  0@11520r

selectOrSplit GPR64common:%vreg107 [11536r,11584r:0)  0@11536r w=6.086311e-04
assigning %vreg107 to %X8: W8 [11536r,11584r:0)  0@11536r

selectOrSplit GPR32common:%vreg105 [11552r,11568r:0)  0@11552r w=inf
assigning %vreg105 to %W9: W9 [11552r,11568r:0)  0@11552r

selectOrSplit GPR32common:%vreg104 [11568r,11584r:0)  0@11568r w=inf
assigning %vreg104 to %W9: W9 [11568r,11584r:0)  0@11568r

selectOrSplit GPR64:%vreg117 [11680r,11712r:0)  0@11680r w=8.416668e-04
assigning %vreg117 to %X8: W8 [11680r,11712r:0)  0@11680r

selectOrSplit GPR64common:%vreg120 [11688r,11736r:0)  0@11688r w=8.116072e-04
assigning %vreg120 to %X9: W9 [11688r,11736r:0)  0@11688r

selectOrSplit GPR64:%vreg114 [11696r,11712r:0)  0@11696r w=inf
assigning %vreg114 to %X10: W10 [11696r,11712r:0)  0@11696r

selectOrSplit GPR64common:%vreg115 [11712r,11728r:0)  0@11712r w=inf
assigning %vreg115 to %X8: W8 [11712r,11728r:0)  0@11712r

selectOrSplit GPR32common:%vreg116 [11728r,11744r:0)  0@11728r w=8.740386e-04
assigning %vreg116 to %W8: W8 [11728r,11744r:0)  0@11728r

selectOrSplit GPR32:%vreg119 [11736r,11760r:0)  0@11736r w=8.575473e-04
assigning %vreg119 to %W9: W9 [11736r,11760r:0)  0@11736r

selectOrSplit GPR32common:%vreg112 [11744r,11760r:0)  0@11744r w=inf
assigning %vreg112 to %W8: W8 [11744r,11760r:0)  0@11744r

selectOrSplit GPR64:%vreg129 [11888r,11920r:0)  0@11888r w=4.207820e-04
assigning %vreg129 to %X8: W8 [11888r,11920r:0)  0@11888r

selectOrSplit GPR64common:%vreg132 [11896r,11944r:0)  0@11896r w=4.057541e-04
assigning %vreg132 to %X9: W9 [11896r,11944r:0)  0@11896r

selectOrSplit GPR64:%vreg126 [11904r,11920r:0)  0@11904r w=inf
assigning %vreg126 to %X10: W10 [11904r,11920r:0)  0@11904r

selectOrSplit GPR64common:%vreg127 [11920r,11936r:0)  0@11920r w=inf
assigning %vreg127 to %X8: W8 [11920r,11936r:0)  0@11920r

selectOrSplit GPR32common:%vreg128 [11936r,11952r:0)  0@11936r w=4.369659e-04
assigning %vreg128 to %W8: W8 [11936r,11952r:0)  0@11936r

selectOrSplit GPR32:%vreg131 [11944r,11968r:0)  0@11944r w=4.287213e-04
assigning %vreg131 to %W9: W9 [11944r,11968r:0)  0@11944r

selectOrSplit GPR32common:%vreg124 [11952r,11968r:0)  0@11952r w=inf
assigning %vreg124 to %W8: W8 [11952r,11968r:0)  0@11952r

selectOrSplit GPR32:%vreg601 [12016r,12032r:0)  0@12016r w=inf
assigning %vreg601 to %W8: W8 [12016r,12032r:0)  0@12016r

selectOrSplit GPR64common:%vreg228 [12096r,12112r:0)  0@12096r w=2.184296e-04
assigning %vreg228 to %X8: W8 [12096r,12112r:0)  0@12096r

selectOrSplit GPR32:%vreg226 [12104r,12112r:0)  0@12104r w=inf
assigning %vreg226 to %W9: W9 [12104r,12112r:0)  0@12104r

selectOrSplit GPR64common:%vreg225 [12128r,12144r:0)  0@12128r w=inf
assigning %vreg225 to %X8: W8 [12128r,12144r:0)  0@12128r

selectOrSplit GPR32:%vreg222 [12144r,12192r:0)  0@12144r w=2.028275e-04
assigning %vreg222 to %W8: W8 [12144r,12192r:0)  0@12144r

selectOrSplit GPR64common:%vreg220 [12176r,12192r:0)  0@12176r w=inf
assigning %vreg220 to %X9: W9 [12176r,12192r:0)  0@12176r

selectOrSplit GPR64common:%vreg217 [12208r,12248r:0)  0@12208r w=2.065153e-04
assigning %vreg217 to %X8: W8 [12208r,12248r:0)  0@12208r

selectOrSplit GPR64common:%vreg214 [12240r,12256r:0)  0@12240r w=2.184296e-04
assigning %vreg214 to %X9: W9 [12240r,12256r:0)  0@12240r

selectOrSplit GPR32:%vreg162 [12368r,12816r:0)  0@12368r w=5.357707e-05
assigning %vreg162 to %W8: W8 [12368r,12816r:0)  0@12368r

selectOrSplit GPR64common:%vreg204 [12464r,12520r:0)  0@12464r w=1.992691e-04
assigning %vreg204 to %X9: W9 [12464r,12520r:0)  0@12464r

selectOrSplit GPR64common:%vreg197 [12512r,12612r:0)  0@12512r w=1.817334e-04
assigning %vreg197 to %X10: W10 [12512r,12612r:0)  0@12512r

selectOrSplit GPR64:%vreg203 [12520r,12616r:0)  0@12520r w=1.831990e-04
assigning %vreg203 to %X9: W9 [12520r,12616r:0)  0@12520r

selectOrSplit GPR64:%vreg192 [12544r,12616r:0)  0@12544r w=9.625711e-05
assigning %vreg192 to %X11: W11 [12544r,12616r:0)  0@12544r

selectOrSplit GPR64common:%vreg185 [12608r,12692r:0)  0@12608r w=1.877411e-04
assigning %vreg185 to %X12: W12 [12608r,12692r:0)  0@12608r

selectOrSplit GPR64:%vreg196 [12612r,12696r:0)  0@12612r w=1.877411e-04
assigning %vreg196 to %X10: W10 [12612r,12696r:0)  0@12612r

selectOrSplit GPR64:%vreg193 [12616r,12696r:0)  0@12616r w=1.893057e-04
assigning %vreg193 to %X9: W9 [12616r,12696r:0)  0@12616r

selectOrSplit GPR64common:%vreg177 [12688r,12760r:0)  0@12688r w=1.925142e-04
assigning %vreg177 to %X11: W11 [12688r,12760r:0)  0@12688r

selectOrSplit GPR32:%vreg184 [12692r,12768r:0)  0@12692r w=1.908965e-04
assigning %vreg184 to %W12: W12 [12692r,12768r:0)  0@12692r

selectOrSplit GPR64common:%vreg194 [12696r,12808r:0)  0@12696r w=1.774741e-04
assigning %vreg194 to %X9: W9 [12696r,12808r:0)  0@12696r

selectOrSplit GPR64common:%vreg167 [12752r,12784r:0)  0@12752r w=2.103396e-04
assigning %vreg167 to %X10: W10 [12752r,12784r:0)  0@12752r

selectOrSplit GPR64:%vreg176 [12760r,12792r:0)  0@12760r w=2.103396e-04
assigning %vreg176 to %X11: W11 [12760r,12792r:0)  0@12760r

selectOrSplit GPR64:%vreg179 [12768r,12776r:0)  0@12768r w=inf
assigning %vreg179 to %X12: W12 [12768r,12776r:0)  0@12768r

selectOrSplit GPR64:%vreg180 [12776r,12792r:0)  0@12776r w=2.184296e-04
assigning %vreg180 to %X12: W12 [12776r,12792r:0)  0@12776r

selectOrSplit GPR32:%vreg166 [12784r,12816r:0)  0@12784r w=2.103396e-04
assigning %vreg166 to %W10: W10 [12784r,12816r:0)  0@12784r

selectOrSplit GPR64common:%vreg174 [12792r,12800r:0)  0@12792r w=inf
assigning %vreg174 to %X11: W11 [12792r,12800r:0)  0@12792r

selectOrSplit GPR32:%vreg171 [12800r,12856r:0)  0@12800r w=1.992691e-04
assigning %vreg171 to %W11: W11 [12800r,12856r:0)  0@12800r

selectOrSplit GPR32:%vreg189 [12808r,12872r:0)  0@12808r w=1.958334e-04
assigning %vreg189 to %W9: W9 [12808r,12872r:0)  0@12808r

selectOrSplit GPR32:%vreg164 [12816r,12856r:0)  0@12816r w=2.065153e-04
assigning %vreg164 to %W8: W8 [12816r,12856r:0)  0@12816r

selectOrSplit GPR64common:%vreg153 [12848r,12880r:0)  0@12848r w=2.103396e-04
assigning %vreg153 to %X10: W10 [12848r,12880r:0)  0@12848r

selectOrSplit GPR32:%vreg161 [12856r,12864r:0)  0@12856r w=inf
assigning %vreg161 to %W8: W8 [12856r,12864r:0)  0@12856r

selectOrSplit GPR32common:%vreg158 [12864r,12872r:0)  0@12864r w=inf
assigning %vreg158 to %W8: W8 [12864r,12872r:0)  0@12864r

selectOrSplit GPR32:%vreg156 [12872r,12880r:0)  0@12872r w=inf
assigning %vreg156 to %W8: W8 [12872r,12880r:0)  0@12872r

selectOrSplit GPR64common:%vreg150 [12888r,12928r:0)  0@12888r w=3.097729e-04
assigning %vreg150 to %X8: W8 [12888r,12928r:0)  0@12888r

selectOrSplit GPR32common:%vreg149 [12896r,12912r:0)  0@12896r w=inf
assigning %vreg149 to %W9: W9 [12896r,12912r:0)  0@12896r

selectOrSplit GPR32common:%vreg148 [12912r,12928r:0)  0@12912r w=inf
assigning %vreg148 to %W9: W9 [12912r,12928r:0)  0@12912r

selectOrSplit GPR64:%vreg141 [12976r,13008r:0)  0@12976r w=2.103396e-04
assigning %vreg141 to %X8: W8 [12976r,13008r:0)  0@12976r

selectOrSplit GPR64common:%vreg144 [12984r,13032r:0)  0@12984r w=2.028275e-04
assigning %vreg144 to %X9: W9 [12984r,13032r:0)  0@12984r

selectOrSplit GPR64:%vreg138 [12992r,13008r:0)  0@12992r w=inf
assigning %vreg138 to %X10: W10 [12992r,13008r:0)  0@12992r

selectOrSplit GPR64common:%vreg139 [13008r,13024r:0)  0@13008r w=inf
assigning %vreg139 to %X8: W8 [13008r,13024r:0)  0@13008r

selectOrSplit GPR32common:%vreg140 [13024r,13040r:0)  0@13024r w=2.184296e-04
assigning %vreg140 to %W8: W8 [13024r,13040r:0)  0@13024r

selectOrSplit GPR32:%vreg143 [13032r,13056r:0)  0@13032r w=2.143083e-04
assigning %vreg143 to %W9: W9 [13032r,13056r:0)  0@13032r

selectOrSplit GPR32common:%vreg136 [13040r,13056r:0)  0@13040r w=inf
assigning %vreg136 to %W8: W8 [13040r,13056r:0)  0@13040r

selectOrSplit GPR64common:%vreg233 [13152r,13168r:0)  0@13152r w=1.091614e-04
assigning %vreg233 to %X8: W8 [13152r,13168r:0)  0@13152r

selectOrSplit GPR32:%vreg236 [13160r,13184r:0)  0@13160r w=1.071018e-04
assigning %vreg236 to %W9: W9 [13160r,13184r:0)  0@13160r

selectOrSplit GPR32:%vreg232 [13168r,13184r:0)  0@13168r w=inf
assigning %vreg232 to %W8: W8 [13168r,13184r:0)  0@13168r

selectOrSplit GPR32:%vreg600 [13232r,13264r:0)  0@13232r w=5.250784e-05
assigning %vreg600 to %W8: W8 [13232r,13264r:0)  0@13232r

selectOrSplit GPR64common:%vreg597 [13248r,13264r:0)  0@13248r w=inf
assigning %vreg597 to %X9: W9 [13248r,13264r:0)  0@13248r

selectOrSplit GPR64common:%vreg324 [13328r,13344r:0)  0@13328r w=5.452737e-05
assigning %vreg324 to %X8: W8 [13328r,13344r:0)  0@13328r

selectOrSplit GPR32:%vreg322 [13336r,13344r:0)  0@13336r w=inf
assigning %vreg322 to %W9: W9 [13336r,13344r:0)  0@13336r

selectOrSplit GPR64common:%vreg321 [13360r,13400r:0)  0@13360r w=5.155315e-05
assigning %vreg321 to %X8: W8 [13360r,13400r:0)  0@13360r

selectOrSplit GPR64common:%vreg318 [13392r,13408r:0)  0@13392r w=5.452737e-05
assigning %vreg318 to %X9: W9 [13392r,13408r:0)  0@13392r

selectOrSplit GPR32:%vreg266 [13520r,13968r:0)  0@13520r w=1.337464e-05
assigning %vreg266 to %W8: W8 [13520r,13968r:0)  0@13520r

selectOrSplit GPR64common:%vreg308 [13616r,13672r:0)  0@13616r w=4.974427e-05
assigning %vreg308 to %X9: W9 [13616r,13672r:0)  0@13616r

selectOrSplit GPR64common:%vreg301 [13664r,13764r:0)  0@13664r w=4.536677e-05
assigning %vreg301 to %X10: W10 [13664r,13764r:0)  0@13664r

selectOrSplit GPR64:%vreg307 [13672r,13768r:0)  0@13672r w=4.573263e-05
assigning %vreg307 to %X9: W9 [13672r,13768r:0)  0@13672r

selectOrSplit GPR64:%vreg296 [13696r,13768r:0)  0@13696r w=2.402901e-05
assigning %vreg296 to %X11: W11 [13696r,13768r:0)  0@13696r

selectOrSplit GPR64common:%vreg289 [13760r,13844r:0)  0@13760r w=4.686650e-05
assigning %vreg289 to %X12: W12 [13760r,13844r:0)  0@13760r

selectOrSplit GPR64:%vreg300 [13764r,13848r:0)  0@13764r w=4.686650e-05
assigning %vreg300 to %X10: W10 [13764r,13848r:0)  0@13764r

selectOrSplit GPR64:%vreg297 [13768r,13848r:0)  0@13768r w=4.725705e-05
assigning %vreg297 to %X9: W9 [13768r,13848r:0)  0@13768r

selectOrSplit GPR64common:%vreg281 [13840r,13912r:0)  0@13840r w=4.805802e-05
assigning %vreg281 to %X11: W11 [13840r,13912r:0)  0@13840r

selectOrSplit GPR32:%vreg288 [13844r,13920r:0)  0@13844r w=4.765417e-05
assigning %vreg288 to %W12: W12 [13844r,13920r:0)  0@13844r

selectOrSplit GPR64common:%vreg298 [13848r,13960r:0)  0@13848r w=4.430349e-05
assigning %vreg298 to %X9: W9 [13848r,13960r:0)  0@13848r

selectOrSplit GPR64common:%vreg271 [13904r,13936r:0)  0@13904r w=5.250784e-05
assigning %vreg271 to %X10: W10 [13904r,13936r:0)  0@13904r

selectOrSplit GPR64:%vreg280 [13912r,13944r:0)  0@13912r w=5.250784e-05
assigning %vreg280 to %X11: W11 [13912r,13944r:0)  0@13912r

selectOrSplit GPR64:%vreg283 [13920r,13928r:0)  0@13920r w=inf
assigning %vreg283 to %X12: W12 [13920r,13928r:0)  0@13920r

selectOrSplit GPR64:%vreg284 [13928r,13944r:0)  0@13928r w=5.452737e-05
assigning %vreg284 to %X12: W12 [13928r,13944r:0)  0@13928r

selectOrSplit GPR32:%vreg270 [13936r,13968r:0)  0@13936r w=5.250784e-05
assigning %vreg270 to %W10: W10 [13936r,13968r:0)  0@13936r

selectOrSplit GPR64common:%vreg278 [13944r,13952r:0)  0@13944r w=inf
assigning %vreg278 to %X11: W11 [13944r,13952r:0)  0@13944r

selectOrSplit GPR32:%vreg275 [13952r,14008r:0)  0@13952r w=4.974427e-05
assigning %vreg275 to %W11: W11 [13952r,14008r:0)  0@13952r

selectOrSplit GPR32:%vreg293 [13960r,14024r:0)  0@13960r w=4.888661e-05
assigning %vreg293 to %W9: W9 [13960r,14024r:0)  0@13960r

selectOrSplit GPR32:%vreg268 [13968r,14008r:0)  0@13968r w=5.155315e-05
assigning %vreg268 to %W8: W8 [13968r,14008r:0)  0@13968r

selectOrSplit GPR64common:%vreg257 [14000r,14032r:0)  0@14000r w=5.250784e-05
assigning %vreg257 to %X10: W10 [14000r,14032r:0)  0@14000r

selectOrSplit GPR32:%vreg265 [14008r,14016r:0)  0@14008r w=inf
assigning %vreg265 to %W8: W8 [14008r,14016r:0)  0@14008r

selectOrSplit GPR32common:%vreg262 [14016r,14024r:0)  0@14016r w=inf
assigning %vreg262 to %W8: W8 [14016r,14024r:0)  0@14016r

selectOrSplit GPR32:%vreg260 [14024r,14032r:0)  0@14024r w=inf
assigning %vreg260 to %W8: W8 [14024r,14032r:0)  0@14024r

selectOrSplit GPR64common:%vreg254 [14040r,14080r:0)  0@14040r w=7.732973e-05
assigning %vreg254 to %X8: W8 [14040r,14080r:0)  0@14040r

selectOrSplit GPR32common:%vreg253 [14048r,14064r:0)  0@14048r w=inf
assigning %vreg253 to %W9: W9 [14048r,14064r:0)  0@14048r

selectOrSplit GPR32common:%vreg252 [14064r,14080r:0)  0@14064r w=inf
assigning %vreg252 to %W9: W9 [14064r,14080r:0)  0@14064r

selectOrSplit GPR64:%vreg245 [14128r,14160r:0)  0@14128r w=5.250784e-05
assigning %vreg245 to %X8: W8 [14128r,14160r:0)  0@14128r

selectOrSplit GPR64common:%vreg248 [14136r,14184r:0)  0@14136r w=5.063256e-05
assigning %vreg248 to %X9: W9 [14136r,14184r:0)  0@14136r

selectOrSplit GPR64:%vreg242 [14144r,14160r:0)  0@14144r w=inf
assigning %vreg242 to %X10: W10 [14144r,14160r:0)  0@14144r

selectOrSplit GPR64common:%vreg243 [14160r,14176r:0)  0@14160r w=inf
assigning %vreg243 to %X8: W8 [14160r,14176r:0)  0@14160r

selectOrSplit GPR32common:%vreg244 [14176r,14192r:0)  0@14176r w=5.452737e-05
assigning %vreg244 to %W8: W8 [14176r,14192r:0)  0@14176r

selectOrSplit GPR32:%vreg247 [14184r,14208r:0)  0@14184r w=5.349855e-05
assigning %vreg247 to %W9: W9 [14184r,14208r:0)  0@14184r

selectOrSplit GPR32common:%vreg240 [14192r,14208r:0)  0@14192r w=inf
assigning %vreg240 to %W8: W8 [14192r,14208r:0)  0@14192r

selectOrSplit GPR64common:%vreg329 [14304r,14320r:0)  0@14304r w=2.721033e-05
assigning %vreg329 to %X8: W8 [14304r,14320r:0)  0@14304r

selectOrSplit GPR32:%vreg332 [14312r,14336r:0)  0@14312r w=2.669693e-05
assigning %vreg332 to %W9: W9 [14312r,14336r:0)  0@14312r

selectOrSplit GPR32:%vreg328 [14320r,14336r:0)  0@14320r w=inf
assigning %vreg328 to %W8: W8 [14320r,14336r:0)  0@14320r

selectOrSplit GPR32:%vreg594 [14384r,14416r:0)  0@14384r w=1.304989e-05
assigning %vreg594 to %W8: W8 [14384r,14416r:0)  0@14384r

selectOrSplit GPR64common:%vreg591 [14400r,14416r:0)  0@14400r w=inf
assigning %vreg591 to %X9: W9 [14400r,14416r:0)  0@14400r

selectOrSplit GPR64common:%vreg420 [14480r,14496r:0)  0@14480r w=1.355181e-05
assigning %vreg420 to %X8: W8 [14480r,14496r:0)  0@14480r

selectOrSplit GPR32:%vreg418 [14488r,14496r:0)  0@14488r w=inf
assigning %vreg418 to %W9: W9 [14488r,14496r:0)  0@14488r

selectOrSplit GPR64common:%vreg417 [14512r,14552r:0)  0@14512r w=1.281262e-05
assigning %vreg417 to %X8: W8 [14512r,14552r:0)  0@14512r

selectOrSplit GPR64common:%vreg414 [14544r,14560r:0)  0@14544r w=1.355181e-05
assigning %vreg414 to %X9: W9 [14544r,14560r:0)  0@14544r

selectOrSplit GPR32:%vreg362 [14672r,15120r:0)  0@14672r w=3.324029e-06
assigning %vreg362 to %W8: W8 [14672r,15120r:0)  0@14672r

selectOrSplit GPR64common:%vreg404 [14768r,14824r:0)  0@14768r w=1.236306e-05
assigning %vreg404 to %X9: W9 [14768r,14824r:0)  0@14768r

selectOrSplit GPR64common:%vreg397 [14816r,14916r:0)  0@14816r w=1.127511e-05
assigning %vreg397 to %X10: W10 [14816r,14916r:0)  0@14816r

selectOrSplit GPR64:%vreg403 [14824r,14920r:0)  0@14824r w=1.136604e-05
assigning %vreg403 to %X9: W9 [14824r,14920r:0)  0@14824r

selectOrSplit GPR64:%vreg392 [14848r,14920r:0)  0@14848r w=5.971985e-06
assigning %vreg392 to %X11: W11 [14848r,14920r:0)  0@14848r

selectOrSplit GPR64common:%vreg385 [14912r,14996r:0)  0@14912r w=1.164784e-05
assigning %vreg385 to %X12: W12 [14912r,14996r:0)  0@14912r

selectOrSplit GPR64:%vreg396 [14916r,15000r:0)  0@14916r w=1.164784e-05
assigning %vreg396 to %X10: W10 [14916r,15000r:0)  0@14916r

selectOrSplit GPR64:%vreg393 [14920r,15000r:0)  0@14920r w=1.174490e-05
assigning %vreg393 to %X9: W9 [14920r,15000r:0)  0@14920r

selectOrSplit GPR64common:%vreg377 [14992r,15064r:0)  0@14992r w=1.194397e-05
assigning %vreg377 to %X11: W11 [14992r,15064r:0)  0@14992r

selectOrSplit GPR32:%vreg384 [14996r,15072r:0)  0@14996r w=1.184360e-05
assigning %vreg384 to %W12: W12 [14996r,15072r:0)  0@14996r

selectOrSplit GPR64common:%vreg394 [15000r,15112r:0)  0@15000r w=1.101085e-05
assigning %vreg394 to %X9: W9 [15000r,15112r:0)  0@15000r

selectOrSplit GPR64common:%vreg367 [15056r,15088r:0)  0@15056r w=1.304989e-05
assigning %vreg367 to %X10: W10 [15056r,15088r:0)  0@15056r

selectOrSplit GPR64:%vreg376 [15064r,15096r:0)  0@15064r w=1.304989e-05
assigning %vreg376 to %X11: W11 [15064r,15096r:0)  0@15064r

selectOrSplit GPR64:%vreg379 [15072r,15080r:0)  0@15072r w=inf
assigning %vreg379 to %X12: W12 [15072r,15080r:0)  0@15072r

selectOrSplit GPR64:%vreg380 [15080r,15096r:0)  0@15080r w=1.355181e-05
assigning %vreg380 to %X12: W12 [15080r,15096r:0)  0@15080r

selectOrSplit GPR32:%vreg366 [15088r,15120r:0)  0@15088r w=1.304989e-05
assigning %vreg366 to %W10: W10 [15088r,15120r:0)  0@15088r

selectOrSplit GPR64common:%vreg374 [15096r,15104r:0)  0@15096r w=inf
assigning %vreg374 to %X11: W11 [15096r,15104r:0)  0@15096r

selectOrSplit GPR32:%vreg371 [15104r,15160r:0)  0@15104r w=1.236306e-05
assigning %vreg371 to %W11: W11 [15104r,15160r:0)  0@15104r

selectOrSplit GPR32:%vreg389 [15112r,15176r:0)  0@15112r w=1.214990e-05
assigning %vreg389 to %W9: W9 [15112r,15176r:0)  0@15112r

selectOrSplit GPR32:%vreg364 [15120r,15160r:0)  0@15120r w=1.281262e-05
assigning %vreg364 to %W8: W8 [15120r,15160r:0)  0@15120r

selectOrSplit GPR64common:%vreg353 [15152r,15184r:0)  0@15152r w=1.304989e-05
assigning %vreg353 to %X10: W10 [15152r,15184r:0)  0@15152r

selectOrSplit GPR32:%vreg361 [15160r,15168r:0)  0@15160r w=inf
assigning %vreg361 to %W8: W8 [15160r,15168r:0)  0@15160r

selectOrSplit GPR32common:%vreg358 [15168r,15176r:0)  0@15168r w=inf
assigning %vreg358 to %W8: W8 [15168r,15176r:0)  0@15168r

selectOrSplit GPR32:%vreg356 [15176r,15184r:0)  0@15176r w=inf
assigning %vreg356 to %W8: W8 [15176r,15184r:0)  0@15176r

selectOrSplit GPR64common:%vreg350 [15192r,15232r:0)  0@15192r w=1.921893e-05
assigning %vreg350 to %X8: W8 [15192r,15232r:0)  0@15192r

selectOrSplit GPR32common:%vreg349 [15200r,15216r:0)  0@15200r w=inf
assigning %vreg349 to %W9: W9 [15200r,15216r:0)  0@15200r

selectOrSplit GPR32common:%vreg348 [15216r,15232r:0)  0@15216r w=inf
assigning %vreg348 to %W9: W9 [15216r,15232r:0)  0@15216r

selectOrSplit GPR64:%vreg341 [15280r,15312r:0)  0@15280r w=1.304989e-05
assigning %vreg341 to %X8: W8 [15280r,15312r:0)  0@15280r

selectOrSplit GPR64common:%vreg344 [15288r,15336r:0)  0@15288r w=1.258383e-05
assigning %vreg344 to %X9: W9 [15288r,15336r:0)  0@15288r

selectOrSplit GPR64:%vreg338 [15296r,15312r:0)  0@15296r w=inf
assigning %vreg338 to %X10: W10 [15296r,15312r:0)  0@15296r

selectOrSplit GPR64common:%vreg339 [15312r,15328r:0)  0@15312r w=inf
assigning %vreg339 to %X8: W8 [15312r,15328r:0)  0@15312r

selectOrSplit GPR32common:%vreg340 [15328r,15344r:0)  0@15328r w=1.355181e-05
assigning %vreg340 to %W8: W8 [15328r,15344r:0)  0@15328r

selectOrSplit GPR32:%vreg343 [15336r,15360r:0)  0@15336r w=1.329612e-05
assigning %vreg343 to %W9: W9 [15336r,15360r:0)  0@15336r

selectOrSplit GPR32common:%vreg336 [15344r,15360r:0)  0@15344r w=inf
assigning %vreg336 to %W8: W8 [15344r,15360r:0)  0@15344r

selectOrSplit GPR64common:%vreg425 [15456r,15472r:0)  0@15456r w=6.722553e-06
assigning %vreg425 to %X8: W8 [15456r,15472r:0)  0@15456r

selectOrSplit GPR32:%vreg428 [15464r,15488r:0)  0@15464r w=6.595712e-06
assigning %vreg428 to %W9: W9 [15464r,15488r:0)  0@15464r

selectOrSplit GPR32:%vreg424 [15472r,15488r:0)  0@15472r w=inf
assigning %vreg424 to %W8: W8 [15472r,15488r:0)  0@15472r

selectOrSplit GPR32:%vreg588 [15536r,15568r:0)  0@15536r w=3.185407e-06
assigning %vreg588 to %W8: W8 [15536r,15568r:0)  0@15536r

selectOrSplit GPR64common:%vreg585 [15552r,15568r:0)  0@15552r w=inf
assigning %vreg585 to %X9: W9 [15552r,15568r:0)  0@15552r

selectOrSplit GPR64common:%vreg582 [15616r,15656r:0)  0@15616r w=3.127491e-06
assigning %vreg582 to %X8: W8 [15616r,15656r:0)  0@15616r

selectOrSplit GPR64common:%vreg579 [15648r,15664r:0)  0@15648r w=3.307923e-06
assigning %vreg579 to %X9: W9 [15648r,15664r:0)  0@15648r

selectOrSplit GPR32:%vreg527 [15776r,16224r:0)  0@15776r w=8.113772e-07
assigning %vreg527 to %W8: W8 [15776r,16224r:0)  0@15776r

selectOrSplit GPR64common:%vreg569 [15872r,15928r:0)  0@15872r w=3.017754e-06
assigning %vreg569 to %X9: W9 [15872r,15928r:0)  0@15872r

selectOrSplit GPR64common:%vreg562 [15920r,16020r:0)  0@15920r w=2.752192e-06
assigning %vreg562 to %X10: W10 [15920r,16020r:0)  0@15920r

selectOrSplit GPR64:%vreg568 [15928r,16024r:0)  0@15928r w=2.774387e-06
assigning %vreg568 to %X9: W9 [15928r,16024r:0)  0@15928r

selectOrSplit GPR64:%vreg557 [15952r,16024r:0)  0@15952r w=1.457729e-06
assigning %vreg557 to %X11: W11 [15952r,16024r:0)  0@15952r

selectOrSplit GPR64common:%vreg550 [16016r,16100r:0)  0@16016r w=2.843173e-06
assigning %vreg550 to %X12: W12 [16016r,16100r:0)  0@16016r

selectOrSplit GPR64:%vreg561 [16020r,16104r:0)  0@16020r w=2.843173e-06
assigning %vreg561 to %X10: W10 [16020r,16104r:0)  0@16020r

selectOrSplit GPR64:%vreg558 [16024r,16104r:0)  0@16024r w=2.866866e-06
assigning %vreg558 to %X9: W9 [16024r,16104r:0)  0@16024r

selectOrSplit GPR64common:%vreg542 [16096r,16168r:0)  0@16096r w=2.915457e-06
assigning %vreg542 to %X11: W11 [16096r,16168r:0)  0@16096r

selectOrSplit GPR32:%vreg549 [16100r,16176r:0)  0@16100r w=2.890958e-06
assigning %vreg549 to %W12: W12 [16100r,16176r:0)  0@16100r

selectOrSplit GPR64common:%vreg559 [16104r,16216r:0)  0@16104r w=2.687687e-06
assigning %vreg559 to %X9: W9 [16104r,16216r:0)  0@16104r

selectOrSplit GPR64common:%vreg532 [16160r,16192r:0)  0@16160r w=3.185407e-06
assigning %vreg532 to %X10: W10 [16160r,16192r:0)  0@16160r

selectOrSplit GPR64:%vreg541 [16168r,16200r:0)  0@16168r w=3.185407e-06
assigning %vreg541 to %X11: W11 [16168r,16200r:0)  0@16168r

selectOrSplit GPR64:%vreg544 [16176r,16184r:0)  0@16176r w=inf
assigning %vreg544 to %X12: W12 [16176r,16184r:0)  0@16176r

selectOrSplit GPR64:%vreg545 [16184r,16200r:0)  0@16184r w=3.307923e-06
assigning %vreg545 to %X12: W12 [16184r,16200r:0)  0@16184r

selectOrSplit GPR32:%vreg531 [16192r,16224r:0)  0@16192r w=3.185407e-06
assigning %vreg531 to %W10: W10 [16192r,16224r:0)  0@16192r

selectOrSplit GPR64common:%vreg539 [16200r,16208r:0)  0@16200r w=inf
assigning %vreg539 to %X11: W11 [16200r,16208r:0)  0@16200r

selectOrSplit GPR32:%vreg536 [16208r,16264r:0)  0@16208r w=3.017754e-06
assigning %vreg536 to %W11: W11 [16208r,16264r:0)  0@16208r

selectOrSplit GPR32:%vreg554 [16216r,16280r:0)  0@16216r w=2.965724e-06
assigning %vreg554 to %W9: W9 [16216r,16280r:0)  0@16216r

selectOrSplit GPR32:%vreg529 [16224r,16264r:0)  0@16224r w=3.127491e-06
assigning %vreg529 to %W8: W8 [16224r,16264r:0)  0@16224r

selectOrSplit GPR64common:%vreg518 [16256r,16288r:0)  0@16256r w=3.185407e-06
assigning %vreg518 to %X10: W10 [16256r,16288r:0)  0@16256r

selectOrSplit GPR32:%vreg526 [16264r,16272r:0)  0@16264r w=inf
assigning %vreg526 to %W8: W8 [16264r,16272r:0)  0@16264r

selectOrSplit GPR32common:%vreg523 [16272r,16280r:0)  0@16272r w=inf
assigning %vreg523 to %W8: W8 [16272r,16280r:0)  0@16272r

selectOrSplit GPR32:%vreg521 [16280r,16288r:0)  0@16280r w=inf
assigning %vreg521 to %W8: W8 [16280r,16288r:0)  0@16280r

selectOrSplit GPR64common:%vreg515 [16296r,16336r:0)  0@16296r w=4.691236e-06
assigning %vreg515 to %X8: W8 [16296r,16336r:0)  0@16296r

selectOrSplit GPR32common:%vreg514 [16304r,16320r:0)  0@16304r w=inf
assigning %vreg514 to %W9: W9 [16304r,16320r:0)  0@16304r

selectOrSplit GPR32common:%vreg513 [16320r,16336r:0)  0@16320r w=inf
assigning %vreg513 to %W9: W9 [16320r,16336r:0)  0@16320r

selectOrSplit GPR32common:%vreg509 [16352r,16392r:0)  0@16352r w=3.127491e-06
assigning %vreg509 to %W8: W8 [16352r,16392r:0)  0@16352r

selectOrSplit GPR64common:%vreg504 [16384r,16400r:0)  0@16384r w=3.307923e-06
assigning %vreg504 to %X9: W9 [16384r,16400r:0)  0@16384r

selectOrSplit GPR32common:%vreg506 [16392r,16400r:0)  0@16392r w=inf
assigning %vreg506 to %W8: W8 [16392r,16400r:0)  0@16392r

selectOrSplit GPR64common:%vreg501 [16416r,16456r:0)  0@16416r w=3.127491e-06
assigning %vreg501 to %X8: W8 [16416r,16456r:0)  0@16416r

selectOrSplit GPR64common:%vreg498 [16448r,16464r:0)  0@16448r w=3.307923e-06
assigning %vreg498 to %X9: W9 [16448r,16464r:0)  0@16448r

selectOrSplit GPR32:%vreg446 [16576r,17024r:0)  0@16576r w=8.113772e-07
assigning %vreg446 to %W8: W8 [16576r,17024r:0)  0@16576r

selectOrSplit GPR64common:%vreg491 [16640r,16656r:0)  0@16640r w=inf
assigning %vreg491 to %X9: W9 [16640r,16656r:0)  0@16640r

selectOrSplit GPR64common:%vreg488 [16672r,16728r:0)  0@16672r w=3.017754e-06
assigning %vreg488 to %X9: W9 [16672r,16728r:0)  0@16672r

selectOrSplit GPR64common:%vreg481 [16720r,16820r:0)  0@16720r w=2.752192e-06
assigning %vreg481 to %X10: W10 [16720r,16820r:0)  0@16720r

selectOrSplit GPR64:%vreg487 [16728r,16824r:0)  0@16728r w=2.774387e-06
assigning %vreg487 to %X9: W9 [16728r,16824r:0)  0@16728r

selectOrSplit GPR64:%vreg476 [16752r,16824r:0)  0@16752r w=1.457729e-06
assigning %vreg476 to %X11: W11 [16752r,16824r:0)  0@16752r

selectOrSplit GPR64common:%vreg469 [16816r,16900r:0)  0@16816r w=2.843173e-06
assigning %vreg469 to %X12: W12 [16816r,16900r:0)  0@16816r

selectOrSplit GPR64:%vreg480 [16820r,16904r:0)  0@16820r w=2.843173e-06
assigning %vreg480 to %X10: W10 [16820r,16904r:0)  0@16820r

selectOrSplit GPR64:%vreg477 [16824r,16904r:0)  0@16824r w=2.866866e-06
assigning %vreg477 to %X9: W9 [16824r,16904r:0)  0@16824r

selectOrSplit GPR64common:%vreg461 [16896r,16968r:0)  0@16896r w=2.915457e-06
assigning %vreg461 to %X11: W11 [16896r,16968r:0)  0@16896r

selectOrSplit GPR32:%vreg468 [16900r,16976r:0)  0@16900r w=2.890958e-06
assigning %vreg468 to %W12: W12 [16900r,16976r:0)  0@16900r

selectOrSplit GPR64common:%vreg478 [16904r,17016r:0)  0@16904r w=2.687687e-06
assigning %vreg478 to %X9: W9 [16904r,17016r:0)  0@16904r

selectOrSplit GPR64common:%vreg451 [16960r,16992r:0)  0@16960r w=3.185407e-06
assigning %vreg451 to %X10: W10 [16960r,16992r:0)  0@16960r

selectOrSplit GPR64:%vreg460 [16968r,17000r:0)  0@16968r w=3.185407e-06
assigning %vreg460 to %X11: W11 [16968r,17000r:0)  0@16968r

selectOrSplit GPR64:%vreg463 [16976r,16984r:0)  0@16976r w=inf
assigning %vreg463 to %X12: W12 [16976r,16984r:0)  0@16976r

selectOrSplit GPR64:%vreg464 [16984r,17000r:0)  0@16984r w=3.307923e-06
assigning %vreg464 to %X12: W12 [16984r,17000r:0)  0@16984r

selectOrSplit GPR32:%vreg450 [16992r,17024r:0)  0@16992r w=3.185407e-06
assigning %vreg450 to %W10: W10 [16992r,17024r:0)  0@16992r

selectOrSplit GPR64common:%vreg458 [17000r,17008r:0)  0@17000r w=inf
assigning %vreg458 to %X11: W11 [17000r,17008r:0)  0@17000r

selectOrSplit GPR32:%vreg455 [17008r,17064r:0)  0@17008r w=3.017754e-06
assigning %vreg455 to %W11: W11 [17008r,17064r:0)  0@17008r

selectOrSplit GPR32:%vreg473 [17016r,17080r:0)  0@17016r w=2.965724e-06
assigning %vreg473 to %W9: W9 [17016r,17080r:0)  0@17016r

selectOrSplit GPR32:%vreg448 [17024r,17064r:0)  0@17024r w=3.127491e-06
assigning %vreg448 to %W8: W8 [17024r,17064r:0)  0@17024r

selectOrSplit GPR64common:%vreg437 [17056r,17088r:0)  0@17056r w=3.185407e-06
assigning %vreg437 to %X10: W10 [17056r,17088r:0)  0@17056r

selectOrSplit GPR32:%vreg445 [17064r,17072r:0)  0@17064r w=inf
assigning %vreg445 to %W8: W8 [17064r,17072r:0)  0@17064r

selectOrSplit GPR32common:%vreg442 [17072r,17080r:0)  0@17072r w=inf
assigning %vreg442 to %W8: W8 [17072r,17080r:0)  0@17072r

selectOrSplit GPR32:%vreg440 [17080r,17088r:0)  0@17080r w=inf
assigning %vreg440 to %W8: W8 [17080r,17088r:0)  0@17080r

selectOrSplit GPR64common:%vreg434 [17096r,17136r:0)  0@17096r w=4.691236e-06
assigning %vreg434 to %X8: W8 [17096r,17136r:0)  0@17096r

selectOrSplit GPR32common:%vreg433 [17104r,17120r:0)  0@17104r w=inf
assigning %vreg433 to %W9: W9 [17104r,17120r:0)  0@17104r

selectOrSplit GPR32common:%vreg432 [17120r,17136r:0)  0@17120r w=inf
assigning %vreg432 to %W9: W9 [17120r,17136r:0)  0@17120r

********** STACK TRANSFORMATION METADATA **********
********** Function: unRLE_obuf_to_output_SMALL
********** REGISTER MAP **********
[%vreg1 -> %X20] GPR64
[%vreg3 -> %W8] GPR32
[%vreg5 -> %W8] GPR32
[%vreg6 -> %X8] GPR64common
[%vreg7 -> %X8] GPR64common
[%vreg9 -> %X0] GPR64sp
[%vreg10 -> %X19] GPR64
[%vreg14 -> %W8] GPR32
[%vreg16 -> %X8] GPR64common
[%vreg17 -> %X8] GPR64common
[%vreg20 -> %W8] GPR32
[%vreg21 -> %X8] GPR64common
[%vreg24 -> %W8] GPR32
[%vreg26 -> %X8] GPR64common
[%vreg27 -> %X8] GPR64common
[%vreg31 -> %W9] GPR32common
[%vreg32 -> %W9] GPR32common
[%vreg34 -> %X8] GPR64common
[%vreg35 -> %X8] GPR64common
[%vreg39 -> %W9] GPR32common
[%vreg40 -> %W9] GPR32common
[%vreg42 -> %X8] GPR64common
[%vreg43 -> %X8] GPR64common
[%vreg47 -> %X9] GPR64common
[%vreg48 -> %X9] GPR64common
[%vreg50 -> %X8] GPR64common
[%vreg51 -> %X8] GPR64common
[%vreg55 -> %W9] GPR32common
[%vreg56 -> %W9] GPR32common
[%vreg57 -> %X8] GPR64common
[%vreg60 -> %X9] GPR64common
[%vreg63 -> %W8] GPR32
[%vreg65 -> %W8] GPR32
[%vreg66 -> %X10] GPR64common
[%vreg67 -> %X10] GPR64common
[%vreg69 -> %X9] GPR64
[%vreg70 -> %X8] GPR64
[%vreg71 -> %X8] GPR64common
[%vreg73 -> %X8] GPR64
[%vreg74 -> %X8] GPR64
[%vreg81 -> %W9] GPR32
[%vreg82 -> %X9] GPR64common
[%vreg84 -> %W8] GPR32
[%vreg86 -> %W8] GPR32
[%vreg87 -> %X8] GPR64common
[%vreg89 -> %W11] GPR32
[%vreg90 -> %X11] GPR64common
[%vreg94 -> %X8] GPR64common
[%vreg96 -> %X8] GPR64common
[%vreg97 -> %X8] GPR64common
[%vreg99 -> %W9] GPR32
[%vreg100 -> %X9] GPR64common
[%vreg104 -> %W9] GPR32common
[%vreg105 -> %W9] GPR32common
[%vreg107 -> %X8] GPR64common
[%vreg108 -> %X8] GPR64common
[%vreg112 -> %W8] GPR32common
[%vreg114 -> %X10] GPR64
[%vreg115 -> %X8] GPR64common
[%vreg116 -> %W8] GPR32common
[%vreg117 -> %X8] GPR64
[%vreg119 -> %W9] GPR32
[%vreg120 -> %X9] GPR64common
[%vreg124 -> %W8] GPR32common
[%vreg126 -> %X10] GPR64
[%vreg127 -> %X8] GPR64common
[%vreg128 -> %W8] GPR32common
[%vreg129 -> %X8] GPR64
[%vreg131 -> %W9] GPR32
[%vreg132 -> %X9] GPR64common
[%vreg136 -> %W8] GPR32common
[%vreg138 -> %X10] GPR64
[%vreg139 -> %X8] GPR64common
[%vreg140 -> %W8] GPR32common
[%vreg141 -> %X8] GPR64
[%vreg143 -> %W9] GPR32
[%vreg144 -> %X9] GPR64common
[%vreg148 -> %W9] GPR32common
[%vreg149 -> %W9] GPR32common
[%vreg150 -> %X8] GPR64common
[%vreg153 -> %X10] GPR64common
[%vreg156 -> %W8] GPR32
[%vreg158 -> %W8] GPR32common
[%vreg161 -> %W8] GPR32
[%vreg162 -> %W8] GPR32
[%vreg164 -> %W8] GPR32
[%vreg166 -> %W10] GPR32
[%vreg167 -> %X10] GPR64common
[%vreg171 -> %W11] GPR32
[%vreg174 -> %X11] GPR64common
[%vreg176 -> %X11] GPR64
[%vreg177 -> %X11] GPR64common
[%vreg179 -> %X12] GPR64
[%vreg180 -> %X12] GPR64
[%vreg184 -> %W12] GPR32
[%vreg185 -> %X12] GPR64common
[%vreg189 -> %W9] GPR32
[%vreg192 -> %X11] GPR64
[%vreg193 -> %X9] GPR64
[%vreg194 -> %X9] GPR64common
[%vreg196 -> %X10] GPR64
[%vreg197 -> %X10] GPR64common
[%vreg203 -> %X9] GPR64
[%vreg204 -> %X9] GPR64common
[%vreg207 -> %W0] GPR32
[%vreg213 -> %X1] GPR64sp
[%vreg214 -> %X9] GPR64common
[%vreg216 -> %W0] GPR32
[%vreg217 -> %X8] GPR64common
[%vreg220 -> %X9] GPR64common
[%vreg222 -> %W8] GPR32
[%vreg225 -> %X8] GPR64common
[%vreg226 -> %W9] GPR32
[%vreg228 -> %X8] GPR64common
[%vreg232 -> %W8] GPR32
[%vreg233 -> %X8] GPR64common
[%vreg236 -> %W9] GPR32
[%vreg240 -> %W8] GPR32common
[%vreg242 -> %X10] GPR64
[%vreg243 -> %X8] GPR64common
[%vreg244 -> %W8] GPR32common
[%vreg245 -> %X8] GPR64
[%vreg247 -> %W9] GPR32
[%vreg248 -> %X9] GPR64common
[%vreg252 -> %W9] GPR32common
[%vreg253 -> %W9] GPR32common
[%vreg254 -> %X8] GPR64common
[%vreg257 -> %X10] GPR64common
[%vreg260 -> %W8] GPR32
[%vreg262 -> %W8] GPR32common
[%vreg265 -> %W8] GPR32
[%vreg266 -> %W8] GPR32
[%vreg268 -> %W8] GPR32
[%vreg270 -> %W10] GPR32
[%vreg271 -> %X10] GPR64common
[%vreg275 -> %W11] GPR32
[%vreg278 -> %X11] GPR64common
[%vreg280 -> %X11] GPR64
[%vreg281 -> %X11] GPR64common
[%vreg283 -> %X12] GPR64
[%vreg284 -> %X12] GPR64
[%vreg288 -> %W12] GPR32
[%vreg289 -> %X12] GPR64common
[%vreg293 -> %W9] GPR32
[%vreg296 -> %X11] GPR64
[%vreg297 -> %X9] GPR64
[%vreg298 -> %X9] GPR64common
[%vreg300 -> %X10] GPR64
[%vreg301 -> %X10] GPR64common
[%vreg307 -> %X9] GPR64
[%vreg308 -> %X9] GPR64common
[%vreg311 -> %W0] GPR32
[%vreg317 -> %X1] GPR64sp
[%vreg318 -> %X9] GPR64common
[%vreg320 -> %W0] GPR32
[%vreg321 -> %X8] GPR64common
[%vreg322 -> %W9] GPR32
[%vreg324 -> %X8] GPR64common
[%vreg328 -> %W8] GPR32
[%vreg329 -> %X8] GPR64common
[%vreg332 -> %W9] GPR32
[%vreg336 -> %W8] GPR32common
[%vreg338 -> %X10] GPR64
[%vreg339 -> %X8] GPR64common
[%vreg340 -> %W8] GPR32common
[%vreg341 -> %X8] GPR64
[%vreg343 -> %W9] GPR32
[%vreg344 -> %X9] GPR64common
[%vreg348 -> %W9] GPR32common
[%vreg349 -> %W9] GPR32common
[%vreg350 -> %X8] GPR64common
[%vreg353 -> %X10] GPR64common
[%vreg356 -> %W8] GPR32
[%vreg358 -> %W8] GPR32common
[%vreg361 -> %W8] GPR32
[%vreg362 -> %W8] GPR32
[%vreg364 -> %W8] GPR32
[%vreg366 -> %W10] GPR32
[%vreg367 -> %X10] GPR64common
[%vreg371 -> %W11] GPR32
[%vreg374 -> %X11] GPR64common
[%vreg376 -> %X11] GPR64
[%vreg377 -> %X11] GPR64common
[%vreg379 -> %X12] GPR64
[%vreg380 -> %X12] GPR64
[%vreg384 -> %W12] GPR32
[%vreg385 -> %X12] GPR64common
[%vreg389 -> %W9] GPR32
[%vreg392 -> %X11] GPR64
[%vreg393 -> %X9] GPR64
[%vreg394 -> %X9] GPR64common
[%vreg396 -> %X10] GPR64
[%vreg397 -> %X10] GPR64common
[%vreg403 -> %X9] GPR64
[%vreg404 -> %X9] GPR64common
[%vreg407 -> %W0] GPR32
[%vreg413 -> %X1] GPR64sp
[%vreg414 -> %X9] GPR64common
[%vreg416 -> %W0] GPR32
[%vreg417 -> %X8] GPR64common
[%vreg418 -> %W9] GPR32
[%vreg420 -> %X8] GPR64common
[%vreg424 -> %W8] GPR32
[%vreg425 -> %X8] GPR64common
[%vreg428 -> %W9] GPR32
[%vreg432 -> %W9] GPR32common
[%vreg433 -> %W9] GPR32common
[%vreg434 -> %X8] GPR64common
[%vreg437 -> %X10] GPR64common
[%vreg440 -> %W8] GPR32
[%vreg442 -> %W8] GPR32common
[%vreg445 -> %W8] GPR32
[%vreg446 -> %W8] GPR32
[%vreg448 -> %W8] GPR32
[%vreg450 -> %W10] GPR32
[%vreg451 -> %X10] GPR64common
[%vreg455 -> %W11] GPR32
[%vreg458 -> %X11] GPR64common
[%vreg460 -> %X11] GPR64
[%vreg461 -> %X11] GPR64common
[%vreg463 -> %X12] GPR64
[%vreg464 -> %X12] GPR64
[%vreg468 -> %W12] GPR32
[%vreg469 -> %X12] GPR64common
[%vreg473 -> %W9] GPR32
[%vreg476 -> %X11] GPR64
[%vreg477 -> %X9] GPR64
[%vreg478 -> %X9] GPR64common
[%vreg480 -> %X10] GPR64
[%vreg481 -> %X10] GPR64common
[%vreg487 -> %X9] GPR64
[%vreg488 -> %X9] GPR64common
[%vreg491 -> %X9] GPR64common
[%vreg494 -> %W0] GPR32
[%vreg497 -> %X1] GPR64sp
[%vreg498 -> %X9] GPR64common
[%vreg500 -> %W0] GPR32
[%vreg501 -> %X8] GPR64common
[%vreg504 -> %X9] GPR64common
[%vreg506 -> %W8] GPR32common
[%vreg509 -> %W8] GPR32common
[%vreg513 -> %W9] GPR32common
[%vreg514 -> %W9] GPR32common
[%vreg515 -> %X8] GPR64common
[%vreg518 -> %X10] GPR64common
[%vreg521 -> %W8] GPR32
[%vreg523 -> %W8] GPR32common
[%vreg526 -> %W8] GPR32
[%vreg527 -> %W8] GPR32
[%vreg529 -> %W8] GPR32
[%vreg531 -> %W10] GPR32
[%vreg532 -> %X10] GPR64common
[%vreg536 -> %W11] GPR32
[%vreg539 -> %X11] GPR64common
[%vreg541 -> %X11] GPR64
[%vreg542 -> %X11] GPR64common
[%vreg544 -> %X12] GPR64
[%vreg545 -> %X12] GPR64
[%vreg549 -> %W12] GPR32
[%vreg550 -> %X12] GPR64common
[%vreg554 -> %W9] GPR32
[%vreg557 -> %X11] GPR64
[%vreg558 -> %X9] GPR64
[%vreg559 -> %X9] GPR64common
[%vreg561 -> %X10] GPR64
[%vreg562 -> %X10] GPR64common
[%vreg568 -> %X9] GPR64
[%vreg569 -> %X9] GPR64common
[%vreg572 -> %W0] GPR32
[%vreg578 -> %X1] GPR64sp
[%vreg579 -> %X9] GPR64common
[%vreg581 -> %W0] GPR32
[%vreg582 -> %X8] GPR64common
[%vreg585 -> %X9] GPR64common
[%vreg588 -> %W8] GPR32
[%vreg591 -> %X9] GPR64common
[%vreg594 -> %W8] GPR32
[%vreg597 -> %X9] GPR64common
[%vreg600 -> %W8] GPR32
[%vreg601 -> %W8] GPR32
[%vreg604 -> %W8] GPR32
[%vreg606 -> %X8] GPR64common
[%vreg607 -> %X8] GPR64common
[%vreg610 -> %W8] GPR32
[%vreg611 -> %X8] GPR64common
[%vreg614 -> %W8] GPR32
[%vreg616 -> %X8] GPR64common
[%vreg617 -> %X8] GPR64common
[%vreg621 -> %W9] GPR32common
[%vreg622 -> %W9] GPR32common
[%vreg624 -> %X8] GPR64common
[%vreg625 -> %X8] GPR64common
[%vreg629 -> %W9] GPR32common
[%vreg630 -> %W9] GPR32common
[%vreg632 -> %X8] GPR64common
[%vreg633 -> %X8] GPR64common
[%vreg637 -> %X9] GPR64common
[%vreg638 -> %X9] GPR64common
[%vreg640 -> %X8] GPR64common
[%vreg641 -> %X8] GPR64common
[%vreg645 -> %W9] GPR32common
[%vreg646 -> %W9] GPR32common
[%vreg647 -> %X8] GPR64common
[%vreg650 -> %X9] GPR64common
[%vreg653 -> %W8] GPR32
[%vreg655 -> %W8] GPR32
[%vreg656 -> %X10] GPR64common
[%vreg657 -> %X10] GPR64common
[%vreg659 -> %X9] GPR64
[%vreg660 -> %X8] GPR64
[%vreg661 -> %X8] GPR64common
[%vreg663 -> %X8] GPR64
[%vreg664 -> %X8] GPR64
[%vreg671 -> %W9] GPR32
[%vreg672 -> %X9] GPR64common
[%vreg674 -> %W8] GPR32
[%vreg676 -> %W8] GPR32
[%vreg677 -> %X8] GPR64common
[%vreg679 -> %W11] GPR32
[%vreg680 -> %X11] GPR64common
[%vreg684 -> %X8] GPR64common
[%vreg686 -> %X8] GPR64common
[%vreg687 -> %X8] GPR64common
[%vreg689 -> %W9] GPR32
[%vreg690 -> %X9] GPR64common
[%vreg694 -> %W9] GPR32common
[%vreg695 -> %W9] GPR32common
[%vreg697 -> %X8] GPR64common
[%vreg698 -> %X8] GPR64common
[%vreg702 -> %W8] GPR32common
[%vreg704 -> %X10] GPR64
[%vreg705 -> %X8] GPR64common
[%vreg706 -> %W8] GPR32common
[%vreg707 -> %X8] GPR64
[%vreg709 -> %W9] GPR32
[%vreg710 -> %X9] GPR64common
[%vreg714 -> %W8] GPR32common
[%vreg716 -> %X10] GPR64
[%vreg717 -> %X8] GPR64common
[%vreg718 -> %W8] GPR32common
[%vreg719 -> %X8] GPR64
[%vreg721 -> %W9] GPR32
[%vreg722 -> %X9] GPR64common
[%vreg725 -> %W8] GPR32
[%vreg726 -> %X8] GPR64common
[%vreg729 -> %X10] GPR64common
[%vreg732 -> %W8] GPR32
[%vreg734 -> %W8] GPR32common
[%vreg737 -> %W8] GPR32
[%vreg738 -> %W8] GPR32
[%vreg740 -> %W8] GPR32
[%vreg742 -> %W10] GPR32
[%vreg743 -> %X10] GPR64common
[%vreg747 -> %W11] GPR32
[%vreg750 -> %X11] GPR64common
[%vreg752 -> %X11] GPR64
[%vreg753 -> %X11] GPR64common
[%vreg755 -> %X12] GPR64
[%vreg756 -> %X12] GPR64
[%vreg760 -> %W12] GPR32
[%vreg761 -> %X12] GPR64common
[%vreg765 -> %W9] GPR32
[%vreg768 -> %X11] GPR64
[%vreg769 -> %X9] GPR64
[%vreg770 -> %X9] GPR64common
[%vreg772 -> %X10] GPR64
[%vreg773 -> %X10] GPR64common
[%vreg779 -> %X9] GPR64
[%vreg780 -> %X9] GPR64common
[%vreg783 -> %W0] GPR32
[%vreg789 -> %X1] GPR64sp
[%vreg790 -> %X9] GPR64common
[%vreg792 -> %W0] GPR32
[%vreg793 -> %X8] GPR64common
[%vreg796 -> %X9] GPR64common
[%vreg798 -> %W8] GPR32
[%vreg801 -> %X8] GPR64common
[%vreg802 -> %W9] GPR32
[%vreg804 -> %X8] GPR64common
[%vreg807 -> %W8] GPR32common
[%vreg808 -> %X8] GPR64common
[%vreg812 -> %W9] GPR32common
[%vreg813 -> %W9] GPR32common
[%vreg814 -> %X8] GPR64common
[%vreg817 -> %X9] GPR64common
[%vreg819 -> %W8] GPR32
[%vreg820 -> %X9] GPR64common
[%vreg821 -> %X9] GPR64common
[%vreg823 -> %X10] GPR64
[%vreg824 -> %X8] GPR64
[%vreg825 -> %X8] GPR64common
[%vreg830 -> %X8] GPR64
[%vreg831 -> %X8] GPR64common
[%vreg833 -> %X8] GPR64common
[%vreg837 -> %W8] GPR32common
[%vreg839 -> %X10] GPR64
[%vreg840 -> %X8] GPR64common
[%vreg841 -> %W8] GPR32common
[%vreg842 -> %X8] GPR64
[%vreg844 -> %W9] GPR32
[%vreg845 -> %X9] GPR64common
[%vreg849 -> %W9] GPR32common
[%vreg850 -> %W9] GPR32common
[%vreg851 -> %X8] GPR64common
[%vreg854 -> %W8] GPR32
[%vreg860 -> %W10] GPR32
[%vreg862 -> %W11] GPR32
[%vreg863 -> %W8] GPR32
[%vreg864 -> %W8] GPR32
[%vreg866 -> %W9] GPR32common
[%vreg867 -> %X9] GPR64common
[%vreg871 -> %W10] GPR32common
[%vreg872 -> %W10] GPR32common
[%vreg873 -> %X9] GPR64common
[%vreg877 -> %W8] GPR32
[%vreg878 -> %X8] GPR64common
[%vreg881 -> %W9] GPR32
[%vreg884 -> %W8] GPR32
[%vreg885 -> %X8] GPR64common
[%vreg888 -> %X10] GPR64common
[%vreg891 -> %W8] GPR32
[%vreg893 -> %W8] GPR32common
[%vreg896 -> %W8] GPR32
[%vreg897 -> %W8] GPR32
[%vreg899 -> %W8] GPR32
[%vreg901 -> %W10] GPR32
[%vreg902 -> %X10] GPR64common
[%vreg906 -> %W11] GPR32
[%vreg909 -> %X11] GPR64common
[%vreg911 -> %X11] GPR64
[%vreg912 -> %X11] GPR64common
[%vreg914 -> %X12] GPR64
[%vreg915 -> %X12] GPR64
[%vreg919 -> %W12] GPR32
[%vreg920 -> %X12] GPR64common
[%vreg924 -> %W9] GPR32
[%vreg927 -> %X11] GPR64
[%vreg928 -> %X9] GPR64
[%vreg929 -> %X9] GPR64common
[%vreg931 -> %X10] GPR64
[%vreg932 -> %X10] GPR64common
[%vreg938 -> %X9] GPR64
[%vreg939 -> %X9] GPR64common
[%vreg942 -> %W0] GPR32
[%vreg948 -> %X1] GPR64sp
[%vreg949 -> %X9] GPR64common
[%vreg951 -> %W0] GPR32
[%vreg952 -> %X8] GPR64common
[%vreg953 -> %W9] GPR32
[%vreg955 -> %X8] GPR64common
[%vreg958 -> %W8] GPR32common
[%vreg959 -> %X8] GPR64common
[%vreg963 -> %W9] GPR32common
[%vreg964 -> %W9] GPR32common
[%vreg965 -> %X8] GPR64common
[%vreg968 -> %X9] GPR64common
[%vreg970 -> %W8] GPR32
[%vreg971 -> %X9] GPR64common
[%vreg972 -> %X9] GPR64common
[%vreg974 -> %X10] GPR64
[%vreg975 -> %X8] GPR64
[%vreg976 -> %X8] GPR64common
[%vreg981 -> %X8] GPR64
[%vreg982 -> %X8] GPR64common
[%vreg984 -> %X8] GPR64common
[%vreg988 -> %W8] GPR32common
[%vreg990 -> %X10] GPR64
[%vreg991 -> %X8] GPR64common
[%vreg992 -> %W8] GPR32common
[%vreg993 -> %X8] GPR64
[%vreg995 -> %W9] GPR32
[%vreg996 -> %X9] GPR64common
[%vreg1000 -> %W9] GPR32common
[%vreg1001 -> %W9] GPR32common
[%vreg1002 -> %X8] GPR64common
[%vreg1005 -> %W8] GPR32
[%vreg1011 -> %W10] GPR32
[%vreg1013 -> %W11] GPR32
[%vreg1014 -> %W8] GPR32
[%vreg1015 -> %W8] GPR32
[%vreg1017 -> %W9] GPR32common
[%vreg1018 -> %X9] GPR64common
[%vreg1022 -> %W10] GPR32common
[%vreg1023 -> %W10] GPR32common
[%vreg1024 -> %X9] GPR64common
[%vreg1028 -> %W8] GPR32
[%vreg1029 -> %X8] GPR64common
[%vreg1032 -> %W9] GPR32
[%vreg1035 -> %W8] GPR32
[%vreg1036 -> %X8] GPR64common
[%vreg1039 -> %X10] GPR64common
[%vreg1042 -> %W8] GPR32
[%vreg1044 -> %W8] GPR32common
[%vreg1047 -> %W8] GPR32
[%vreg1048 -> %W8] GPR32
[%vreg1050 -> %W8] GPR32
[%vreg1052 -> %W10] GPR32
[%vreg1053 -> %X10] GPR64common
[%vreg1057 -> %W11] GPR32
[%vreg1060 -> %X11] GPR64common
[%vreg1062 -> %X11] GPR64
[%vreg1063 -> %X11] GPR64common
[%vreg1065 -> %X12] GPR64
[%vreg1066 -> %X12] GPR64
[%vreg1070 -> %W12] GPR32
[%vreg1071 -> %X12] GPR64common
[%vreg1075 -> %W9] GPR32
[%vreg1078 -> %X11] GPR64
[%vreg1079 -> %X9] GPR64
[%vreg1080 -> %X9] GPR64common
[%vreg1082 -> %X10] GPR64
[%vreg1083 -> %X10] GPR64common
[%vreg1089 -> %X9] GPR64
[%vreg1090 -> %X9] GPR64common
[%vreg1093 -> %W0] GPR32
[%vreg1099 -> %X1] GPR64sp
[%vreg1100 -> %X9] GPR64common
[%vreg1102 -> %W0] GPR32
[%vreg1103 -> %X8] GPR64common
[%vreg1104 -> %W9] GPR32
[%vreg1106 -> %X8] GPR64common
[%vreg1109 -> %W8] GPR32common
[%vreg1110 -> %X8] GPR64common
[%vreg1114 -> %W9] GPR32common
[%vreg1115 -> %W9] GPR32common
[%vreg1116 -> %X8] GPR64common
[%vreg1119 -> %X9] GPR64common
[%vreg1121 -> %W8] GPR32
[%vreg1122 -> %X9] GPR64common
[%vreg1123 -> %X9] GPR64common
[%vreg1125 -> %X10] GPR64
[%vreg1126 -> %X8] GPR64
[%vreg1127 -> %X8] GPR64common
[%vreg1132 -> %X8] GPR64
[%vreg1133 -> %X8] GPR64common
[%vreg1135 -> %X8] GPR64common
[%vreg1139 -> %W8] GPR32common
[%vreg1141 -> %X10] GPR64
[%vreg1142 -> %X8] GPR64common
[%vreg1143 -> %W8] GPR32common
[%vreg1144 -> %X8] GPR64
[%vreg1146 -> %W9] GPR32
[%vreg1147 -> %X9] GPR64common
[%vreg1151 -> %W9] GPR32common
[%vreg1152 -> %W9] GPR32common
[%vreg1153 -> %X8] GPR64common
[%vreg1156 -> %W8] GPR32
[%vreg1162 -> %W10] GPR32
[%vreg1164 -> %W11] GPR32
[%vreg1165 -> %W8] GPR32
[%vreg1166 -> %W8] GPR32
[%vreg1168 -> %W9] GPR32common
[%vreg1169 -> %X9] GPR64common
[%vreg1173 -> %W10] GPR32common
[%vreg1174 -> %W10] GPR32common
[%vreg1175 -> %X9] GPR64common
[%vreg1179 -> %W8] GPR32
[%vreg1180 -> %X8] GPR64common
[%vreg1183 -> %W9] GPR32
[%vreg1186 -> %W8] GPR32
[%vreg1187 -> %X8] GPR64common
[%vreg1190 -> %X10] GPR64common
[%vreg1193 -> %W8] GPR32
[%vreg1195 -> %W8] GPR32common
[%vreg1198 -> %W8] GPR32
[%vreg1199 -> %W8] GPR32
[%vreg1201 -> %W8] GPR32
[%vreg1203 -> %W10] GPR32
[%vreg1204 -> %X10] GPR64common
[%vreg1208 -> %W11] GPR32
[%vreg1211 -> %X11] GPR64common
[%vreg1213 -> %X11] GPR64
[%vreg1214 -> %X11] GPR64common
[%vreg1216 -> %X12] GPR64
[%vreg1217 -> %X12] GPR64
[%vreg1221 -> %W12] GPR32
[%vreg1222 -> %X12] GPR64common
[%vreg1226 -> %W9] GPR32
[%vreg1229 -> %X11] GPR64
[%vreg1230 -> %X9] GPR64
[%vreg1231 -> %X9] GPR64common
[%vreg1233 -> %X10] GPR64
[%vreg1234 -> %X10] GPR64common
[%vreg1240 -> %X9] GPR64
[%vreg1241 -> %X9] GPR64common
[%vreg1244 -> %W0] GPR32
[%vreg1250 -> %X1] GPR64sp
[%vreg1251 -> %X9] GPR64common
[%vreg1253 -> %W0] GPR32
[%vreg1254 -> %X8] GPR64common
[%vreg1257 -> %W8] GPR32common
[%vreg1258 -> %X8] GPR64common
[%vreg1262 -> %W9] GPR32common
[%vreg1263 -> %W9] GPR32common
[%vreg1264 -> %X8] GPR64common
[%vreg1267 -> %X9] GPR64common
[%vreg1269 -> %W8] GPR32
[%vreg1270 -> %X9] GPR64common
[%vreg1271 -> %X9] GPR64common
[%vreg1273 -> %X10] GPR64
[%vreg1274 -> %X8] GPR64
[%vreg1275 -> %X8] GPR64common
[%vreg1280 -> %X8] GPR64
[%vreg1281 -> %X8] GPR64common
[%vreg1283 -> %X8] GPR64common
[%vreg1286 -> %W8] GPR32
[%vreg1287 -> %X8] GPR64common
[%vreg1290 -> %X10] GPR64common
[%vreg1293 -> %W8] GPR32
[%vreg1295 -> %W8] GPR32common
[%vreg1298 -> %W8] GPR32
[%vreg1299 -> %W8] GPR32
[%vreg1301 -> %W8] GPR32
[%vreg1303 -> %W10] GPR32
[%vreg1304 -> %X10] GPR64common
[%vreg1308 -> %W11] GPR32
[%vreg1311 -> %X11] GPR64common
[%vreg1313 -> %X11] GPR64
[%vreg1314 -> %X11] GPR64common
[%vreg1316 -> %X12] GPR64
[%vreg1317 -> %X12] GPR64
[%vreg1321 -> %W12] GPR32
[%vreg1322 -> %X12] GPR64common
[%vreg1326 -> %W9] GPR32
[%vreg1329 -> %X11] GPR64
[%vreg1330 -> %X9] GPR64
[%vreg1331 -> %X9] GPR64common
[%vreg1333 -> %X10] GPR64
[%vreg1334 -> %X10] GPR64common
[%vreg1340 -> %X9] GPR64
[%vreg1341 -> %X9] GPR64common
[%vreg1344 -> %X9] GPR64common
[%vreg1347 -> %W0] GPR32
[%vreg1350 -> %X1] GPR64sp
[%vreg1351 -> %X9] GPR64common
[%vreg1353 -> %W0] GPR32
[%vreg1354 -> %X8] GPR64common
[%vreg1357 -> %X9] GPR64common
[%vreg1359 -> %W8] GPR32common
[%vreg1362 -> %W8] GPR32common
[%vreg1366 -> %W9] GPR32common
[%vreg1367 -> %W9] GPR32common
[%vreg1368 -> %X8] GPR64common
[%vreg1371 -> %W8] GPR32
[%vreg1377 -> %W10] GPR32
[%vreg1379 -> %W11] GPR32
[%vreg1380 -> %W8] GPR32
[%vreg1381 -> %W8] GPR32
[%vreg1383 -> %W9] GPR32common
[%vreg1384 -> %X9] GPR64common
[%vreg1388 -> %W10] GPR32common
[%vreg1389 -> %W10] GPR32common
[%vreg1390 -> %X9] GPR64common
[%vreg1393 -> %W8] GPR32common
[%vreg1394 -> %X8] GPR64common
[%vreg1398 -> %W9] GPR32common
[%vreg1399 -> %W9] GPR32common
[%vreg1400 -> %X8] GPR64common
[%vreg1403 -> %X9] GPR64common
[%vreg1405 -> %W8] GPR32
[%vreg1406 -> %X9] GPR64common
[%vreg1407 -> %X9] GPR64common
[%vreg1409 -> %X10] GPR64
[%vreg1410 -> %X8] GPR64
[%vreg1411 -> %X8] GPR64common
[%vreg1416 -> %X8] GPR64
[%vreg1417 -> %X8] GPR64common
[%vreg1419 -> %X8] GPR64common
[%vreg1423 -> %W9] GPR32common
[%vreg1424 -> %W9] GPR32common
[%vreg1425 -> %X8] GPR64common
[%vreg1430 -> %W8] GPR32
[%vreg1431 -> %W11] GPR32
[%vreg1432 -> %X10] GPR64common
[%vreg1434 -> %W9] GPR32
[%vreg1435 -> %W8] GPR32
[%vreg1436 -> %W8] GPR32
[%vreg1438 -> %W9] GPR32common
[%vreg1439 -> %X9] GPR64common
[%vreg1443 -> %W10] GPR32common
[%vreg1444 -> %W10] GPR32common
[%vreg1445 -> %X9] GPR64common
[%vreg1448 -> %X9] GPR64common
[%vreg1451 -> %W8] GPR32
[%vreg1454 -> %X9] GPR64common
[%vreg1457 -> %W8] GPR32
[%vreg1460 -> %X9] GPR64common
[%vreg1463 -> %W8] GPR32
[%vreg1464 -> %W8] GPR32
[%vreg1466 -> %X0] GPR64
[%vreg1467 -> %W0] GPR32


Stackmap 0:
  STACKMAP 0, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, %vreg1, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1] GPR64:%vreg1

i8* %k1: in stack slot 2 (size: 1)
i8* %retval: in stack slot 0 (size: 1)
%struct.DState* %s: in register %X20 (vreg 1)
%struct.DState** %s.addr: in stack slot 1 (size: 8)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]

i8* %k1: in stack slot 2 (size: 1)
i8* %retval: in stack slot 0 (size: 1)
%struct.DState** %s.addr: in stack slot 1 (size: 8)

Duplicate operand locations:


Stackmap 2:
  STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]

i8* %k1: in stack slot 2 (size: 1)
i8* %retval: in stack slot 0 (size: 1)
%struct.DState** %s.addr: in stack slot 1 (size: 8)

Duplicate operand locations:


Stackmap 3:
  STACKMAP 3, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]

i8* %k1: in stack slot 2 (size: 1)
i8* %retval: in stack slot 0 (size: 1)
%struct.DState** %s.addr: in stack slot 1 (size: 8)

Duplicate operand locations:


Stackmap 4:
  STACKMAP 4, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]

i8* %k1: in stack slot 2 (size: 1)
i8* %retval: in stack slot 0 (size: 1)
%struct.DState** %s.addr: in stack slot 1 (size: 8)

Duplicate operand locations:


Stackmap 5:
  STACKMAP 5, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]

i8* %k1: in stack slot 2 (size: 1)
i8* %retval: in stack slot 0 (size: 1)
%struct.DState** %s.addr: in stack slot 1 (size: 8)

Duplicate operand locations:


Stackmap 6:
  STACKMAP 6, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]

i8* %k1: in stack slot 2 (size: 1)
i8* %retval: in stack slot 0 (size: 1)
%struct.DState** %s.addr: in stack slot 1 (size: 8)

Duplicate operand locations:


Stackmap 7:
  STACKMAP 7, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]

i8* %k1: in stack slot 2 (size: 1)
i8* %retval: in stack slot 0 (size: 1)
%struct.DState** %s.addr: in stack slot 1 (size: 8)

Duplicate operand locations:


Stackmap 8:
  STACKMAP 8, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]

i8* %k1: in stack slot 2 (size: 1)
i8* %retval: in stack slot 0 (size: 1)
%struct.DState** %s.addr: in stack slot 1 (size: 8)

Duplicate operand locations:


Stackmap 9:
  STACKMAP 9, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]

i8* %k1: in stack slot 2 (size: 1)
i8* %retval: in stack slot 0 (size: 1)
%struct.DState** %s.addr: in stack slot 1 (size: 8)

Duplicate operand locations:


Stackmap 10:
  STACKMAP 10, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]

i8* %k1: in stack slot 2 (size: 1)
i8* %retval: in stack slot 0 (size: 1)
%struct.DState** %s.addr: in stack slot 1 (size: 8)

Duplicate operand locations:


Stackmap 11:
  STACKMAP 11, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=1)

i8* %retval: in stack slot 0 (size: 1)

Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, %vreg1, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1] GPR64:%vreg1
  -> Call instruction SlotIndex 176B, searching vregs 0 -> 1468 and stack slots 0 -> 3
    + vreg10 is live in register but not in stackmap
      Defining instruction: %vreg10<def> = COPY %LR; GPR64:%vreg10
      Value: generated value, 1 instruction(s)

  STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
  -> Call instruction SlotIndex 2224B, searching vregs 0 -> 1468 and stack slots 0 -> 3
    + vreg10 is live in register but not in stackmap
      Defining instruction: %vreg10<def> = COPY %LR; GPR64:%vreg10
      Value: generated value, 1 instruction(s)

  STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
  -> Call instruction SlotIndex 4048B, searching vregs 0 -> 1468 and stack slots 0 -> 3
    + vreg10 is live in register but not in stackmap
      Defining instruction: %vreg10<def> = COPY %LR; GPR64:%vreg10
      Value: generated value, 1 instruction(s)

  STACKMAP 3, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
  -> Call instruction SlotIndex 5872B, searching vregs 0 -> 1468 and stack slots 0 -> 3
    + vreg10 is live in register but not in stackmap
      Defining instruction: %vreg10<def> = COPY %LR; GPR64:%vreg10
      Value: generated value, 1 instruction(s)

  STACKMAP 4, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
  -> Call instruction SlotIndex 7648B, searching vregs 0 -> 1468 and stack slots 0 -> 3
    + vreg10 is live in register but not in stackmap
      Defining instruction: %vreg10<def> = COPY %LR; GPR64:%vreg10
      Value: generated value, 1 instruction(s)

  STACKMAP 5, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
  -> Call instruction SlotIndex 9120B, searching vregs 0 -> 1468 and stack slots 0 -> 3
    + vreg10 is live in register but not in stackmap
      Defining instruction: %vreg10<def> = COPY %LR; GPR64:%vreg10
      Value: generated value, 1 instruction(s)

  STACKMAP 6, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
  -> Call instruction SlotIndex 12320B, searching vregs 0 -> 1468 and stack slots 0 -> 3
    + vreg10 is live in register but not in stackmap
      Defining instruction: %vreg10<def> = COPY %LR; GPR64:%vreg10
      Value: generated value, 1 instruction(s)

  STACKMAP 7, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
  -> Call instruction SlotIndex 13472B, searching vregs 0 -> 1468 and stack slots 0 -> 3
    + vreg10 is live in register but not in stackmap
      Defining instruction: %vreg10<def> = COPY %LR; GPR64:%vreg10
      Value: generated value, 1 instruction(s)

  STACKMAP 8, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
  -> Call instruction SlotIndex 14624B, searching vregs 0 -> 1468 and stack slots 0 -> 3
    + vreg10 is live in register but not in stackmap
      Defining instruction: %vreg10<def> = COPY %LR; GPR64:%vreg10
      Value: generated value, 1 instruction(s)

  STACKMAP 9, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
  -> Call instruction SlotIndex 15728B, searching vregs 0 -> 1468 and stack slots 0 -> 3
    + vreg10 is live in register but not in stackmap
      Defining instruction: %vreg10<def> = COPY %LR; GPR64:%vreg10
      Value: generated value, 1 instruction(s)

  STACKMAP 10, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
  -> Call instruction SlotIndex 16528B, searching vregs 0 -> 1468 and stack slots 0 -> 3
    + vreg10 is live in register but not in stackmap
      Defining instruction: %vreg10<def> = COPY %LR; GPR64:%vreg10
      Value: generated value, 1 instruction(s)

  STACKMAP 11, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=1)
  -> Call instruction SlotIndex 17248B, searching vregs 0 -> 1468 and stack slots 0 -> 3

********** REWRITE VIRTUAL REGISTERS **********
********** Function: unRLE_obuf_to_output_SMALL
********** REGISTER MAP **********
[%vreg1 -> %X20] GPR64
[%vreg3 -> %W8] GPR32
[%vreg5 -> %W8] GPR32
[%vreg6 -> %X8] GPR64common
[%vreg7 -> %X8] GPR64common
[%vreg9 -> %X0] GPR64sp
[%vreg10 -> %X19] GPR64
[%vreg14 -> %W8] GPR32
[%vreg16 -> %X8] GPR64common
[%vreg17 -> %X8] GPR64common
[%vreg20 -> %W8] GPR32
[%vreg21 -> %X8] GPR64common
[%vreg24 -> %W8] GPR32
[%vreg26 -> %X8] GPR64common
[%vreg27 -> %X8] GPR64common
[%vreg31 -> %W9] GPR32common
[%vreg32 -> %W9] GPR32common
[%vreg34 -> %X8] GPR64common
[%vreg35 -> %X8] GPR64common
[%vreg39 -> %W9] GPR32common
[%vreg40 -> %W9] GPR32common
[%vreg42 -> %X8] GPR64common
[%vreg43 -> %X8] GPR64common
[%vreg47 -> %X9] GPR64common
[%vreg48 -> %X9] GPR64common
[%vreg50 -> %X8] GPR64common
[%vreg51 -> %X8] GPR64common
[%vreg55 -> %W9] GPR32common
[%vreg56 -> %W9] GPR32common
[%vreg57 -> %X8] GPR64common
[%vreg60 -> %X9] GPR64common
[%vreg63 -> %W8] GPR32
[%vreg65 -> %W8] GPR32
[%vreg66 -> %X10] GPR64common
[%vreg67 -> %X10] GPR64common
[%vreg69 -> %X9] GPR64
[%vreg70 -> %X8] GPR64
[%vreg71 -> %X8] GPR64common
[%vreg73 -> %X8] GPR64
[%vreg74 -> %X8] GPR64
[%vreg81 -> %W9] GPR32
[%vreg82 -> %X9] GPR64common
[%vreg84 -> %W8] GPR32
[%vreg86 -> %W8] GPR32
[%vreg87 -> %X8] GPR64common
[%vreg89 -> %W11] GPR32
[%vreg90 -> %X11] GPR64common
[%vreg94 -> %X8] GPR64common
[%vreg96 -> %X8] GPR64common
[%vreg97 -> %X8] GPR64common
[%vreg99 -> %W9] GPR32
[%vreg100 -> %X9] GPR64common
[%vreg104 -> %W9] GPR32common
[%vreg105 -> %W9] GPR32common
[%vreg107 -> %X8] GPR64common
[%vreg108 -> %X8] GPR64common
[%vreg112 -> %W8] GPR32common
[%vreg114 -> %X10] GPR64
[%vreg115 -> %X8] GPR64common
[%vreg116 -> %W8] GPR32common
[%vreg117 -> %X8] GPR64
[%vreg119 -> %W9] GPR32
[%vreg120 -> %X9] GPR64common
[%vreg124 -> %W8] GPR32common
[%vreg126 -> %X10] GPR64
[%vreg127 -> %X8] GPR64common
[%vreg128 -> %W8] GPR32common
[%vreg129 -> %X8] GPR64
[%vreg131 -> %W9] GPR32
[%vreg132 -> %X9] GPR64common
[%vreg136 -> %W8] GPR32common
[%vreg138 -> %X10] GPR64
[%vreg139 -> %X8] GPR64common
[%vreg140 -> %W8] GPR32common
[%vreg141 -> %X8] GPR64
[%vreg143 -> %W9] GPR32
[%vreg144 -> %X9] GPR64common
[%vreg148 -> %W9] GPR32common
[%vreg149 -> %W9] GPR32common
[%vreg150 -> %X8] GPR64common
[%vreg153 -> %X10] GPR64common
[%vreg156 -> %W8] GPR32
[%vreg158 -> %W8] GPR32common
[%vreg161 -> %W8] GPR32
[%vreg162 -> %W8] GPR32
[%vreg164 -> %W8] GPR32
[%vreg166 -> %W10] GPR32
[%vreg167 -> %X10] GPR64common
[%vreg171 -> %W11] GPR32
[%vreg174 -> %X11] GPR64common
[%vreg176 -> %X11] GPR64
[%vreg177 -> %X11] GPR64common
[%vreg179 -> %X12] GPR64
[%vreg180 -> %X12] GPR64
[%vreg184 -> %W12] GPR32
[%vreg185 -> %X12] GPR64common
[%vreg189 -> %W9] GPR32
[%vreg192 -> %X11] GPR64
[%vreg193 -> %X9] GPR64
[%vreg194 -> %X9] GPR64common
[%vreg196 -> %X10] GPR64
[%vreg197 -> %X10] GPR64common
[%vreg203 -> %X9] GPR64
[%vreg204 -> %X9] GPR64common
[%vreg207 -> %W0] GPR32
[%vreg213 -> %X1] GPR64sp
[%vreg214 -> %X9] GPR64common
[%vreg216 -> %W0] GPR32
[%vreg217 -> %X8] GPR64common
[%vreg220 -> %X9] GPR64common
[%vreg222 -> %W8] GPR32
[%vreg225 -> %X8] GPR64common
[%vreg226 -> %W9] GPR32
[%vreg228 -> %X8] GPR64common
[%vreg232 -> %W8] GPR32
[%vreg233 -> %X8] GPR64common
[%vreg236 -> %W9] GPR32
[%vreg240 -> %W8] GPR32common
[%vreg242 -> %X10] GPR64
[%vreg243 -> %X8] GPR64common
[%vreg244 -> %W8] GPR32common
[%vreg245 -> %X8] GPR64
[%vreg247 -> %W9] GPR32
[%vreg248 -> %X9] GPR64common
[%vreg252 -> %W9] GPR32common
[%vreg253 -> %W9] GPR32common
[%vreg254 -> %X8] GPR64common
[%vreg257 -> %X10] GPR64common
[%vreg260 -> %W8] GPR32
[%vreg262 -> %W8] GPR32common
[%vreg265 -> %W8] GPR32
[%vreg266 -> %W8] GPR32
[%vreg268 -> %W8] GPR32
[%vreg270 -> %W10] GPR32
[%vreg271 -> %X10] GPR64common
[%vreg275 -> %W11] GPR32
[%vreg278 -> %X11] GPR64common
[%vreg280 -> %X11] GPR64
[%vreg281 -> %X11] GPR64common
[%vreg283 -> %X12] GPR64
[%vreg284 -> %X12] GPR64
[%vreg288 -> %W12] GPR32
[%vreg289 -> %X12] GPR64common
[%vreg293 -> %W9] GPR32
[%vreg296 -> %X11] GPR64
[%vreg297 -> %X9] GPR64
[%vreg298 -> %X9] GPR64common
[%vreg300 -> %X10] GPR64
[%vreg301 -> %X10] GPR64common
[%vreg307 -> %X9] GPR64
[%vreg308 -> %X9] GPR64common
[%vreg311 -> %W0] GPR32
[%vreg317 -> %X1] GPR64sp
[%vreg318 -> %X9] GPR64common
[%vreg320 -> %W0] GPR32
[%vreg321 -> %X8] GPR64common
[%vreg322 -> %W9] GPR32
[%vreg324 -> %X8] GPR64common
[%vreg328 -> %W8] GPR32
[%vreg329 -> %X8] GPR64common
[%vreg332 -> %W9] GPR32
[%vreg336 -> %W8] GPR32common
[%vreg338 -> %X10] GPR64
[%vreg339 -> %X8] GPR64common
[%vreg340 -> %W8] GPR32common
[%vreg341 -> %X8] GPR64
[%vreg343 -> %W9] GPR32
[%vreg344 -> %X9] GPR64common
[%vreg348 -> %W9] GPR32common
[%vreg349 -> %W9] GPR32common
[%vreg350 -> %X8] GPR64common
[%vreg353 -> %X10] GPR64common
[%vreg356 -> %W8] GPR32
[%vreg358 -> %W8] GPR32common
[%vreg361 -> %W8] GPR32
[%vreg362 -> %W8] GPR32
[%vreg364 -> %W8] GPR32
[%vreg366 -> %W10] GPR32
[%vreg367 -> %X10] GPR64common
[%vreg371 -> %W11] GPR32
[%vreg374 -> %X11] GPR64common
[%vreg376 -> %X11] GPR64
[%vreg377 -> %X11] GPR64common
[%vreg379 -> %X12] GPR64
[%vreg380 -> %X12] GPR64
[%vreg384 -> %W12] GPR32
[%vreg385 -> %X12] GPR64common
[%vreg389 -> %W9] GPR32
[%vreg392 -> %X11] GPR64
[%vreg393 -> %X9] GPR64
[%vreg394 -> %X9] GPR64common
[%vreg396 -> %X10] GPR64
[%vreg397 -> %X10] GPR64common
[%vreg403 -> %X9] GPR64
[%vreg404 -> %X9] GPR64common
[%vreg407 -> %W0] GPR32
[%vreg413 -> %X1] GPR64sp
[%vreg414 -> %X9] GPR64common
[%vreg416 -> %W0] GPR32
[%vreg417 -> %X8] GPR64common
[%vreg418 -> %W9] GPR32
[%vreg420 -> %X8] GPR64common
[%vreg424 -> %W8] GPR32
[%vreg425 -> %X8] GPR64common
[%vreg428 -> %W9] GPR32
[%vreg432 -> %W9] GPR32common
[%vreg433 -> %W9] GPR32common
[%vreg434 -> %X8] GPR64common
[%vreg437 -> %X10] GPR64common
[%vreg440 -> %W8] GPR32
[%vreg442 -> %W8] GPR32common
[%vreg445 -> %W8] GPR32
[%vreg446 -> %W8] GPR32
[%vreg448 -> %W8] GPR32
[%vreg450 -> %W10] GPR32
[%vreg451 -> %X10] GPR64common
[%vreg455 -> %W11] GPR32
[%vreg458 -> %X11] GPR64common
[%vreg460 -> %X11] GPR64
[%vreg461 -> %X11] GPR64common
[%vreg463 -> %X12] GPR64
[%vreg464 -> %X12] GPR64
[%vreg468 -> %W12] GPR32
[%vreg469 -> %X12] GPR64common
[%vreg473 -> %W9] GPR32
[%vreg476 -> %X11] GPR64
[%vreg477 -> %X9] GPR64
[%vreg478 -> %X9] GPR64common
[%vreg480 -> %X10] GPR64
[%vreg481 -> %X10] GPR64common
[%vreg487 -> %X9] GPR64
[%vreg488 -> %X9] GPR64common
[%vreg491 -> %X9] GPR64common
[%vreg494 -> %W0] GPR32
[%vreg497 -> %X1] GPR64sp
[%vreg498 -> %X9] GPR64common
[%vreg500 -> %W0] GPR32
[%vreg501 -> %X8] GPR64common
[%vreg504 -> %X9] GPR64common
[%vreg506 -> %W8] GPR32common
[%vreg509 -> %W8] GPR32common
[%vreg513 -> %W9] GPR32common
[%vreg514 -> %W9] GPR32common
[%vreg515 -> %X8] GPR64common
[%vreg518 -> %X10] GPR64common
[%vreg521 -> %W8] GPR32
[%vreg523 -> %W8] GPR32common
[%vreg526 -> %W8] GPR32
[%vreg527 -> %W8] GPR32
[%vreg529 -> %W8] GPR32
[%vreg531 -> %W10] GPR32
[%vreg532 -> %X10] GPR64common
[%vreg536 -> %W11] GPR32
[%vreg539 -> %X11] GPR64common
[%vreg541 -> %X11] GPR64
[%vreg542 -> %X11] GPR64common
[%vreg544 -> %X12] GPR64
[%vreg545 -> %X12] GPR64
[%vreg549 -> %W12] GPR32
[%vreg550 -> %X12] GPR64common
[%vreg554 -> %W9] GPR32
[%vreg557 -> %X11] GPR64
[%vreg558 -> %X9] GPR64
[%vreg559 -> %X9] GPR64common
[%vreg561 -> %X10] GPR64
[%vreg562 -> %X10] GPR64common
[%vreg568 -> %X9] GPR64
[%vreg569 -> %X9] GPR64common
[%vreg572 -> %W0] GPR32
[%vreg578 -> %X1] GPR64sp
[%vreg579 -> %X9] GPR64common
[%vreg581 -> %W0] GPR32
[%vreg582 -> %X8] GPR64common
[%vreg585 -> %X9] GPR64common
[%vreg588 -> %W8] GPR32
[%vreg591 -> %X9] GPR64common
[%vreg594 -> %W8] GPR32
[%vreg597 -> %X9] GPR64common
[%vreg600 -> %W8] GPR32
[%vreg601 -> %W8] GPR32
[%vreg604 -> %W8] GPR32
[%vreg606 -> %X8] GPR64common
[%vreg607 -> %X8] GPR64common
[%vreg610 -> %W8] GPR32
[%vreg611 -> %X8] GPR64common
[%vreg614 -> %W8] GPR32
[%vreg616 -> %X8] GPR64common
[%vreg617 -> %X8] GPR64common
[%vreg621 -> %W9] GPR32common
[%vreg622 -> %W9] GPR32common
[%vreg624 -> %X8] GPR64common
[%vreg625 -> %X8] GPR64common
[%vreg629 -> %W9] GPR32common
[%vreg630 -> %W9] GPR32common
[%vreg632 -> %X8] GPR64common
[%vreg633 -> %X8] GPR64common
[%vreg637 -> %X9] GPR64common
[%vreg638 -> %X9] GPR64common
[%vreg640 -> %X8] GPR64common
[%vreg641 -> %X8] GPR64common
[%vreg645 -> %W9] GPR32common
[%vreg646 -> %W9] GPR32common
[%vreg647 -> %X8] GPR64common
[%vreg650 -> %X9] GPR64common
[%vreg653 -> %W8] GPR32
[%vreg655 -> %W8] GPR32
[%vreg656 -> %X10] GPR64common
[%vreg657 -> %X10] GPR64common
[%vreg659 -> %X9] GPR64
[%vreg660 -> %X8] GPR64
[%vreg661 -> %X8] GPR64common
[%vreg663 -> %X8] GPR64
[%vreg664 -> %X8] GPR64
[%vreg671 -> %W9] GPR32
[%vreg672 -> %X9] GPR64common
[%vreg674 -> %W8] GPR32
[%vreg676 -> %W8] GPR32
[%vreg677 -> %X8] GPR64common
[%vreg679 -> %W11] GPR32
[%vreg680 -> %X11] GPR64common
[%vreg684 -> %X8] GPR64common
[%vreg686 -> %X8] GPR64common
[%vreg687 -> %X8] GPR64common
[%vreg689 -> %W9] GPR32
[%vreg690 -> %X9] GPR64common
[%vreg694 -> %W9] GPR32common
[%vreg695 -> %W9] GPR32common
[%vreg697 -> %X8] GPR64common
[%vreg698 -> %X8] GPR64common
[%vreg702 -> %W8] GPR32common
[%vreg704 -> %X10] GPR64
[%vreg705 -> %X8] GPR64common
[%vreg706 -> %W8] GPR32common
[%vreg707 -> %X8] GPR64
[%vreg709 -> %W9] GPR32
[%vreg710 -> %X9] GPR64common
[%vreg714 -> %W8] GPR32common
[%vreg716 -> %X10] GPR64
[%vreg717 -> %X8] GPR64common
[%vreg718 -> %W8] GPR32common
[%vreg719 -> %X8] GPR64
[%vreg721 -> %W9] GPR32
[%vreg722 -> %X9] GPR64common
[%vreg725 -> %W8] GPR32
[%vreg726 -> %X8] GPR64common
[%vreg729 -> %X10] GPR64common
[%vreg732 -> %W8] GPR32
[%vreg734 -> %W8] GPR32common
[%vreg737 -> %W8] GPR32
[%vreg738 -> %W8] GPR32
[%vreg740 -> %W8] GPR32
[%vreg742 -> %W10] GPR32
[%vreg743 -> %X10] GPR64common
[%vreg747 -> %W11] GPR32
[%vreg750 -> %X11] GPR64common
[%vreg752 -> %X11] GPR64
[%vreg753 -> %X11] GPR64common
[%vreg755 -> %X12] GPR64
[%vreg756 -> %X12] GPR64
[%vreg760 -> %W12] GPR32
[%vreg761 -> %X12] GPR64common
[%vreg765 -> %W9] GPR32
[%vreg768 -> %X11] GPR64
[%vreg769 -> %X9] GPR64
[%vreg770 -> %X9] GPR64common
[%vreg772 -> %X10] GPR64
[%vreg773 -> %X10] GPR64common
[%vreg779 -> %X9] GPR64
[%vreg780 -> %X9] GPR64common
[%vreg783 -> %W0] GPR32
[%vreg789 -> %X1] GPR64sp
[%vreg790 -> %X9] GPR64common
[%vreg792 -> %W0] GPR32
[%vreg793 -> %X8] GPR64common
[%vreg796 -> %X9] GPR64common
[%vreg798 -> %W8] GPR32
[%vreg801 -> %X8] GPR64common
[%vreg802 -> %W9] GPR32
[%vreg804 -> %X8] GPR64common
[%vreg807 -> %W8] GPR32common
[%vreg808 -> %X8] GPR64common
[%vreg812 -> %W9] GPR32common
[%vreg813 -> %W9] GPR32common
[%vreg814 -> %X8] GPR64common
[%vreg817 -> %X9] GPR64common
[%vreg819 -> %W8] GPR32
[%vreg820 -> %X9] GPR64common
[%vreg821 -> %X9] GPR64common
[%vreg823 -> %X10] GPR64
[%vreg824 -> %X8] GPR64
[%vreg825 -> %X8] GPR64common
[%vreg830 -> %X8] GPR64
[%vreg831 -> %X8] GPR64common
[%vreg833 -> %X8] GPR64common
[%vreg837 -> %W8] GPR32common
[%vreg839 -> %X10] GPR64
[%vreg840 -> %X8] GPR64common
[%vreg841 -> %W8] GPR32common
[%vreg842 -> %X8] GPR64
[%vreg844 -> %W9] GPR32
[%vreg845 -> %X9] GPR64common
[%vreg849 -> %W9] GPR32common
[%vreg850 -> %W9] GPR32common
[%vreg851 -> %X8] GPR64common
[%vreg854 -> %W8] GPR32
[%vreg860 -> %W10] GPR32
[%vreg862 -> %W11] GPR32
[%vreg863 -> %W8] GPR32
[%vreg864 -> %W8] GPR32
[%vreg866 -> %W9] GPR32common
[%vreg867 -> %X9] GPR64common
[%vreg871 -> %W10] GPR32common
[%vreg872 -> %W10] GPR32common
[%vreg873 -> %X9] GPR64common
[%vreg877 -> %W8] GPR32
[%vreg878 -> %X8] GPR64common
[%vreg881 -> %W9] GPR32
[%vreg884 -> %W8] GPR32
[%vreg885 -> %X8] GPR64common
[%vreg888 -> %X10] GPR64common
[%vreg891 -> %W8] GPR32
[%vreg893 -> %W8] GPR32common
[%vreg896 -> %W8] GPR32
[%vreg897 -> %W8] GPR32
[%vreg899 -> %W8] GPR32
[%vreg901 -> %W10] GPR32
[%vreg902 -> %X10] GPR64common
[%vreg906 -> %W11] GPR32
[%vreg909 -> %X11] GPR64common
[%vreg911 -> %X11] GPR64
[%vreg912 -> %X11] GPR64common
[%vreg914 -> %X12] GPR64
[%vreg915 -> %X12] GPR64
[%vreg919 -> %W12] GPR32
[%vreg920 -> %X12] GPR64common
[%vreg924 -> %W9] GPR32
[%vreg927 -> %X11] GPR64
[%vreg928 -> %X9] GPR64
[%vreg929 -> %X9] GPR64common
[%vreg931 -> %X10] GPR64
[%vreg932 -> %X10] GPR64common
[%vreg938 -> %X9] GPR64
[%vreg939 -> %X9] GPR64common
[%vreg942 -> %W0] GPR32
[%vreg948 -> %X1] GPR64sp
[%vreg949 -> %X9] GPR64common
[%vreg951 -> %W0] GPR32
[%vreg952 -> %X8] GPR64common
[%vreg953 -> %W9] GPR32
[%vreg955 -> %X8] GPR64common
[%vreg958 -> %W8] GPR32common
[%vreg959 -> %X8] GPR64common
[%vreg963 -> %W9] GPR32common
[%vreg964 -> %W9] GPR32common
[%vreg965 -> %X8] GPR64common
[%vreg968 -> %X9] GPR64common
[%vreg970 -> %W8] GPR32
[%vreg971 -> %X9] GPR64common
[%vreg972 -> %X9] GPR64common
[%vreg974 -> %X10] GPR64
[%vreg975 -> %X8] GPR64
[%vreg976 -> %X8] GPR64common
[%vreg981 -> %X8] GPR64
[%vreg982 -> %X8] GPR64common
[%vreg984 -> %X8] GPR64common
[%vreg988 -> %W8] GPR32common
[%vreg990 -> %X10] GPR64
[%vreg991 -> %X8] GPR64common
[%vreg992 -> %W8] GPR32common
[%vreg993 -> %X8] GPR64
[%vreg995 -> %W9] GPR32
[%vreg996 -> %X9] GPR64common
[%vreg1000 -> %W9] GPR32common
[%vreg1001 -> %W9] GPR32common
[%vreg1002 -> %X8] GPR64common
[%vreg1005 -> %W8] GPR32
[%vreg1011 -> %W10] GPR32
[%vreg1013 -> %W11] GPR32
[%vreg1014 -> %W8] GPR32
[%vreg1015 -> %W8] GPR32
[%vreg1017 -> %W9] GPR32common
[%vreg1018 -> %X9] GPR64common
[%vreg1022 -> %W10] GPR32common
[%vreg1023 -> %W10] GPR32common
[%vreg1024 -> %X9] GPR64common
[%vreg1028 -> %W8] GPR32
[%vreg1029 -> %X8] GPR64common
[%vreg1032 -> %W9] GPR32
[%vreg1035 -> %W8] GPR32
[%vreg1036 -> %X8] GPR64common
[%vreg1039 -> %X10] GPR64common
[%vreg1042 -> %W8] GPR32
[%vreg1044 -> %W8] GPR32common
[%vreg1047 -> %W8] GPR32
[%vreg1048 -> %W8] GPR32
[%vreg1050 -> %W8] GPR32
[%vreg1052 -> %W10] GPR32
[%vreg1053 -> %X10] GPR64common
[%vreg1057 -> %W11] GPR32
[%vreg1060 -> %X11] GPR64common
[%vreg1062 -> %X11] GPR64
[%vreg1063 -> %X11] GPR64common
[%vreg1065 -> %X12] GPR64
[%vreg1066 -> %X12] GPR64
[%vreg1070 -> %W12] GPR32
[%vreg1071 -> %X12] GPR64common
[%vreg1075 -> %W9] GPR32
[%vreg1078 -> %X11] GPR64
[%vreg1079 -> %X9] GPR64
[%vreg1080 -> %X9] GPR64common
[%vreg1082 -> %X10] GPR64
[%vreg1083 -> %X10] GPR64common
[%vreg1089 -> %X9] GPR64
[%vreg1090 -> %X9] GPR64common
[%vreg1093 -> %W0] GPR32
[%vreg1099 -> %X1] GPR64sp
[%vreg1100 -> %X9] GPR64common
[%vreg1102 -> %W0] GPR32
[%vreg1103 -> %X8] GPR64common
[%vreg1104 -> %W9] GPR32
[%vreg1106 -> %X8] GPR64common
[%vreg1109 -> %W8] GPR32common
[%vreg1110 -> %X8] GPR64common
[%vreg1114 -> %W9] GPR32common
[%vreg1115 -> %W9] GPR32common
[%vreg1116 -> %X8] GPR64common
[%vreg1119 -> %X9] GPR64common
[%vreg1121 -> %W8] GPR32
[%vreg1122 -> %X9] GPR64common
[%vreg1123 -> %X9] GPR64common
[%vreg1125 -> %X10] GPR64
[%vreg1126 -> %X8] GPR64
[%vreg1127 -> %X8] GPR64common
[%vreg1132 -> %X8] GPR64
[%vreg1133 -> %X8] GPR64common
[%vreg1135 -> %X8] GPR64common
[%vreg1139 -> %W8] GPR32common
[%vreg1141 -> %X10] GPR64
[%vreg1142 -> %X8] GPR64common
[%vreg1143 -> %W8] GPR32common
[%vreg1144 -> %X8] GPR64
[%vreg1146 -> %W9] GPR32
[%vreg1147 -> %X9] GPR64common
[%vreg1151 -> %W9] GPR32common
[%vreg1152 -> %W9] GPR32common
[%vreg1153 -> %X8] GPR64common
[%vreg1156 -> %W8] GPR32
[%vreg1162 -> %W10] GPR32
[%vreg1164 -> %W11] GPR32
[%vreg1165 -> %W8] GPR32
[%vreg1166 -> %W8] GPR32
[%vreg1168 -> %W9] GPR32common
[%vreg1169 -> %X9] GPR64common
[%vreg1173 -> %W10] GPR32common
[%vreg1174 -> %W10] GPR32common
[%vreg1175 -> %X9] GPR64common
[%vreg1179 -> %W8] GPR32
[%vreg1180 -> %X8] GPR64common
[%vreg1183 -> %W9] GPR32
[%vreg1186 -> %W8] GPR32
[%vreg1187 -> %X8] GPR64common
[%vreg1190 -> %X10] GPR64common
[%vreg1193 -> %W8] GPR32
[%vreg1195 -> %W8] GPR32common
[%vreg1198 -> %W8] GPR32
[%vreg1199 -> %W8] GPR32
[%vreg1201 -> %W8] GPR32
[%vreg1203 -> %W10] GPR32
[%vreg1204 -> %X10] GPR64common
[%vreg1208 -> %W11] GPR32
[%vreg1211 -> %X11] GPR64common
[%vreg1213 -> %X11] GPR64
[%vreg1214 -> %X11] GPR64common
[%vreg1216 -> %X12] GPR64
[%vreg1217 -> %X12] GPR64
[%vreg1221 -> %W12] GPR32
[%vreg1222 -> %X12] GPR64common
[%vreg1226 -> %W9] GPR32
[%vreg1229 -> %X11] GPR64
[%vreg1230 -> %X9] GPR64
[%vreg1231 -> %X9] GPR64common
[%vreg1233 -> %X10] GPR64
[%vreg1234 -> %X10] GPR64common
[%vreg1240 -> %X9] GPR64
[%vreg1241 -> %X9] GPR64common
[%vreg1244 -> %W0] GPR32
[%vreg1250 -> %X1] GPR64sp
[%vreg1251 -> %X9] GPR64common
[%vreg1253 -> %W0] GPR32
[%vreg1254 -> %X8] GPR64common
[%vreg1257 -> %W8] GPR32common
[%vreg1258 -> %X8] GPR64common
[%vreg1262 -> %W9] GPR32common
[%vreg1263 -> %W9] GPR32common
[%vreg1264 -> %X8] GPR64common
[%vreg1267 -> %X9] GPR64common
[%vreg1269 -> %W8] GPR32
[%vreg1270 -> %X9] GPR64common
[%vreg1271 -> %X9] GPR64common
[%vreg1273 -> %X10] GPR64
[%vreg1274 -> %X8] GPR64
[%vreg1275 -> %X8] GPR64common
[%vreg1280 -> %X8] GPR64
[%vreg1281 -> %X8] GPR64common
[%vreg1283 -> %X8] GPR64common
[%vreg1286 -> %W8] GPR32
[%vreg1287 -> %X8] GPR64common
[%vreg1290 -> %X10] GPR64common
[%vreg1293 -> %W8] GPR32
[%vreg1295 -> %W8] GPR32common
[%vreg1298 -> %W8] GPR32
[%vreg1299 -> %W8] GPR32
[%vreg1301 -> %W8] GPR32
[%vreg1303 -> %W10] GPR32
[%vreg1304 -> %X10] GPR64common
[%vreg1308 -> %W11] GPR32
[%vreg1311 -> %X11] GPR64common
[%vreg1313 -> %X11] GPR64
[%vreg1314 -> %X11] GPR64common
[%vreg1316 -> %X12] GPR64
[%vreg1317 -> %X12] GPR64
[%vreg1321 -> %W12] GPR32
[%vreg1322 -> %X12] GPR64common
[%vreg1326 -> %W9] GPR32
[%vreg1329 -> %X11] GPR64
[%vreg1330 -> %X9] GPR64
[%vreg1331 -> %X9] GPR64common
[%vreg1333 -> %X10] GPR64
[%vreg1334 -> %X10] GPR64common
[%vreg1340 -> %X9] GPR64
[%vreg1341 -> %X9] GPR64common
[%vreg1344 -> %X9] GPR64common
[%vreg1347 -> %W0] GPR32
[%vreg1350 -> %X1] GPR64sp
[%vreg1351 -> %X9] GPR64common
[%vreg1353 -> %W0] GPR32
[%vreg1354 -> %X8] GPR64common
[%vreg1357 -> %X9] GPR64common
[%vreg1359 -> %W8] GPR32common
[%vreg1362 -> %W8] GPR32common
[%vreg1366 -> %W9] GPR32common
[%vreg1367 -> %W9] GPR32common
[%vreg1368 -> %X8] GPR64common
[%vreg1371 -> %W8] GPR32
[%vreg1377 -> %W10] GPR32
[%vreg1379 -> %W11] GPR32
[%vreg1380 -> %W8] GPR32
[%vreg1381 -> %W8] GPR32
[%vreg1383 -> %W9] GPR32common
[%vreg1384 -> %X9] GPR64common
[%vreg1388 -> %W10] GPR32common
[%vreg1389 -> %W10] GPR32common
[%vreg1390 -> %X9] GPR64common
[%vreg1393 -> %W8] GPR32common
[%vreg1394 -> %X8] GPR64common
[%vreg1398 -> %W9] GPR32common
[%vreg1399 -> %W9] GPR32common
[%vreg1400 -> %X8] GPR64common
[%vreg1403 -> %X9] GPR64common
[%vreg1405 -> %W8] GPR32
[%vreg1406 -> %X9] GPR64common
[%vreg1407 -> %X9] GPR64common
[%vreg1409 -> %X10] GPR64
[%vreg1410 -> %X8] GPR64
[%vreg1411 -> %X8] GPR64common
[%vreg1416 -> %X8] GPR64
[%vreg1417 -> %X8] GPR64common
[%vreg1419 -> %X8] GPR64common
[%vreg1423 -> %W9] GPR32common
[%vreg1424 -> %W9] GPR32common
[%vreg1425 -> %X8] GPR64common
[%vreg1430 -> %W8] GPR32
[%vreg1431 -> %W11] GPR32
[%vreg1432 -> %X10] GPR64common
[%vreg1434 -> %W9] GPR32
[%vreg1435 -> %W8] GPR32
[%vreg1436 -> %W8] GPR32
[%vreg1438 -> %W9] GPR32common
[%vreg1439 -> %X9] GPR64common
[%vreg1443 -> %W10] GPR32common
[%vreg1444 -> %W10] GPR32common
[%vreg1445 -> %X9] GPR64common
[%vreg1448 -> %X9] GPR64common
[%vreg1451 -> %W8] GPR32
[%vreg1454 -> %X9] GPR64common
[%vreg1457 -> %W8] GPR32
[%vreg1460 -> %X9] GPR64common
[%vreg1463 -> %W8] GPR32
[%vreg1464 -> %W8] GPR32
[%vreg1466 -> %X0] GPR64
[%vreg1467 -> %W0] GPR32

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %LR %X0
16B		%vreg10<def> = COPY %LR; GPR64:%vreg10
32B		%vreg1<def> = COPY %X0; GPR64:%vreg1
64B		%vreg7<def> = ADRP <ga:@unRLE_obuf_to_output_SMALL>[TF=1]; GPR64common:%vreg7
80B		%vreg9<def> = ADDXri %vreg7<kill>, <ga:@unRLE_obuf_to_output_SMALL>[TF=34], 0; GPR64sp:%vreg9 GPR64common:%vreg7
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		%X0<def> = COPY %vreg9<kill>; GPR64sp:%vreg9
160B		%X1<def> = COPY %vreg10; GPR64:%vreg10
176B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
224B		STACKMAP 0, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, %vreg1, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1] GPR64:%vreg1
240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
256B		STRXui %vreg1<kill>, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg1
272B		%vreg6<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg6
288B		%vreg5<def> = LDRBBui %vreg6<kill>, 20; mem:LD1[%blockRandomised] GPR32:%vreg5 GPR64common:%vreg6
304B		%vreg3<def> = UBFMWri %vreg5<kill>, 0, 7; GPR32:%vreg3,%vreg5
320B		CBZW %vreg3<kill>, <BB#47>; GPR32:%vreg3
	    Successors according to CFG: BB#47 BB#1
> %X19<def> = COPY %LR
> %X20<def> = COPY %X0
> %X8<def> = ADRP <ga:@unRLE_obuf_to_output_SMALL>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@unRLE_obuf_to_output_SMALL>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19
> BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 0, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, %X20, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRXui %X20<kill>, <fi#1>, 0; mem:ST8[FixedStack1]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W8<def> = LDRBBui %X8<kill>, 20; mem:LD1[%blockRandomised]
> %W8<def> = UBFMWri %W8<kill>, 0, 7
> CBZW %W8<kill>, <BB#47>
336B	BB#1: derived from LLVM BB %if.then
	    Live Ins: %X19
	    Predecessors according to CFG: BB#0
352B		B <BB#2>
	    Successors according to CFG: BB#2
> B <BB#2>
368B	BB#2: derived from LLVM BB %while.body
	    Live Ins: %X19
	    Predecessors according to CFG: BB#1 BB#46 BB#37 BB#35 BB#29 BB#27 BB#21 BB#19
384B		B <BB#3>
	    Successors according to CFG: BB#3
> B <BB#3>
400B	BB#3: derived from LLVM BB %while.body.2
	    Live Ins: %X19
	    Predecessors according to CFG: BB#2 BB#9
416B		%vreg607<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg607
432B		%vreg606<def> = LDRXui %vreg607<kill>, 0; mem:LD8[%strm] GPR64common:%vreg606,%vreg607
448B		%vreg604<def> = LDRWui %vreg606<kill>, 8; mem:LD4[%avail_out] GPR32:%vreg604 GPR64common:%vreg606
464B		CBNZW %vreg604<kill>, <BB#5>; GPR32:%vreg604
	    Successors according to CFG: BB#5 BB#4
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X8<def> = LDRXui %X8<kill>, 0; mem:LD8[%strm]
> %W8<def> = LDRWui %X8<kill>, 8; mem:LD4[%avail_out]
> CBNZW %W8<kill>, <BB#5>
480B	BB#4: derived from LLVM BB %if.then.3
	    Live Ins: %X19
	    Predecessors according to CFG: BB#3
496B		STRBBui %WZR, <fi#0>, 0; mem:ST1[FixedStack0]
512B		B <BB#73>
	    Successors according to CFG: BB#73
> STRBBui %WZR, <fi#0>, 0; mem:ST1[FixedStack0]
> B <BB#73>
528B	BB#5: derived from LLVM BB %if.end
	    Live Ins: %X19
	    Predecessors according to CFG: BB#3
544B		%vreg611<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg611
560B		%vreg610<def> = LDRWui %vreg611<kill>, 4; mem:LD4[%state_out_len] GPR32:%vreg610 GPR64common:%vreg611
576B		CBNZW %vreg610<kill>, <BB#7>; GPR32:%vreg610
	    Successors according to CFG: BB#7 BB#6
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W8<def> = LDRWui %X8<kill>, 4; mem:LD4[%state_out_len]
> CBNZW %W8<kill>, <BB#7>
592B	BB#6: derived from LLVM BB %if.then.5
	    Live Ins: %X19
	    Predecessors according to CFG: BB#5
608B		B <BB#10>
	    Successors according to CFG: BB#10
> B <BB#10>
624B	BB#7: derived from LLVM BB %if.end.6
	    Live Ins: %X19
	    Predecessors according to CFG: BB#5
704B		%vreg687<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg687
712B		%vreg690<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg690
720B		%vreg686<def> = LDRXui %vreg687<kill>, 0; mem:LD8[%strm7] GPR64common:%vreg686,%vreg687
728B		%vreg689<def> = LDRBBui %vreg690<kill>, 12; mem:LD1[%state_out_ch] GPR32:%vreg689 GPR64common:%vreg690
736B		%vreg684<def> = LDRXui %vreg686<kill>, 3; mem:LD8[%next_out] GPR64common:%vreg684,%vreg686
752B		STRBBui %vreg689<kill>, %vreg684<kill>, 0; mem:ST1[%11] GPR32:%vreg689 GPR64common:%vreg684
800B		%vreg677<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg677
848B		%vreg672<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg672
856B		%vreg656<def> = ADRP <ga:@BZ2_crc32Table>[TF=1]; GPR64common:%vreg656
864B		%vreg680<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg680
872B		%vreg676<def> = LDRWui %vreg677<kill>, 796; mem:LD4[%calculatedBlockCRC8] GPR32:%vreg676 GPR64common:%vreg677
880B		%vreg671<def> = LDRBBui %vreg672<kill>, 12; mem:LD1[%state_out_ch9] GPR32:%vreg671 GPR64common:%vreg672
888B		%vreg657<def> = ADDXri %vreg656<kill>, <ga:@BZ2_crc32Table>[TF=34], 0; GPR64common:%vreg657,%vreg656
896B		%vreg679<def> = LDRWui %vreg680<kill>, 796; mem:LD4[%calculatedBlockCRC] GPR32:%vreg679 GPR64common:%vreg680
904B		%vreg674<def> = UBFMWri %vreg676<kill>, 24, 31; GPR32:%vreg674,%vreg676
912B		%vreg663:sub_32<def,read-undef> = EORWrr %vreg674<kill>, %vreg671<kill>; GPR64:%vreg663 GPR32:%vreg674,%vreg671
928B		%vreg664<def> = UBFMXri %vreg663<kill>, 0, 31; GPR64:%vreg664,%vreg663
936B		%vreg659<def> = MOVi64imm 4; GPR64:%vreg659
944B		%vreg660<def> = MADDXrrr %vreg664<kill>, %vreg659<kill>, %XZR; GPR64:%vreg660,%vreg664,%vreg659
960B		%vreg661<def> = ADDXrr %vreg657<kill>, %vreg660<kill>; GPR64common:%vreg661,%vreg657 GPR64:%vreg660
976B		%vreg655<def> = LDRWui %vreg661<kill>, 0; mem:LD4[%arrayidx] GPR32:%vreg655 GPR64common:%vreg661
1008B		%vreg650<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg650
1016B		%vreg653<def> = EORWrs %vreg655<kill>, %vreg679<kill>, 8; GPR32:%vreg653,%vreg655,%vreg679
1024B		STRWui %vreg653<kill>, %vreg650<kill>, 796; mem:ST4[%calculatedBlockCRC11] GPR32:%vreg653 GPR64common:%vreg650
1040B		%vreg647<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg647
1056B		%vreg646<def> = LDRWui %vreg647, 4; mem:LD4[%state_out_len12] GPR32common:%vreg646 GPR64common:%vreg647
1072B		%vreg645<def> = SUBWri %vreg646<kill>, 1, 0; GPR32common:%vreg645,%vreg646
1088B		STRWui %vreg645<kill>, %vreg647<kill>, 4; mem:ST4[%state_out_len12] GPR32common:%vreg645 GPR64common:%vreg647
1104B		%vreg641<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg641
1120B		%vreg640<def> = LDRXui %vreg641<kill>, 0; mem:LD8[%strm13] GPR64common:%vreg640,%vreg641
1136B		%vreg638<def> = LDRXui %vreg640, 3; mem:LD8[%next_out14] GPR64common:%vreg638,%vreg640
1152B		%vreg637<def> = ADDXri %vreg638<kill>, 1, 0; GPR64common:%vreg637,%vreg638
1168B		STRXui %vreg637<kill>, %vreg640<kill>, 3; mem:ST8[%next_out14] GPR64common:%vreg637,%vreg640
1184B		%vreg633<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg633
1200B		%vreg632<def> = LDRXui %vreg633<kill>, 0; mem:LD8[%strm15] GPR64common:%vreg632,%vreg633
1216B		%vreg630<def> = LDRWui %vreg632, 8; mem:LD4[%avail_out16] GPR32common:%vreg630 GPR64common:%vreg632
1232B		%vreg629<def> = SUBWri %vreg630<kill>, 1, 0; GPR32common:%vreg629,%vreg630
1248B		STRWui %vreg629<kill>, %vreg632<kill>, 8; mem:ST4[%avail_out16] GPR32common:%vreg629 GPR64common:%vreg632
1264B		%vreg625<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg625
1280B		%vreg624<def> = LDRXui %vreg625<kill>, 0; mem:LD8[%strm18] GPR64common:%vreg624,%vreg625
1296B		%vreg622<def> = LDRWui %vreg624, 9; mem:LD4[%total_out_lo32] GPR32common:%vreg622 GPR64common:%vreg624
1312B		%vreg621<def> = ADDWri %vreg622<kill>, 1, 0; GPR32common:%vreg621,%vreg622
1328B		STRWui %vreg621<kill>, %vreg624<kill>, 9; mem:ST4[%total_out_lo32] GPR32common:%vreg621 GPR64common:%vreg624
1344B		%vreg617<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg617
1360B		%vreg616<def> = LDRXui %vreg617<kill>, 0; mem:LD8[%strm19] GPR64common:%vreg616,%vreg617
1376B		%vreg614<def> = LDRWui %vreg616<kill>, 9; mem:LD4[%total_out_lo3220] GPR32:%vreg614 GPR64common:%vreg616
1392B		CBNZW %vreg614<kill>, <BB#9>; GPR32:%vreg614
	    Successors according to CFG: BB#9 BB#8
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X8<def> = LDRXui %X8<kill>, 0; mem:LD8[%strm7]
> %W9<def> = LDRBBui %X9<kill>, 12; mem:LD1[%state_out_ch]
> %X8<def> = LDRXui %X8<kill>, 3; mem:LD8[%next_out]
> STRBBui %W9<kill>, %X8<kill>, 0; mem:ST1[%11]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X10<def> = ADRP <ga:@BZ2_crc32Table>[TF=1]
> %X11<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W8<def> = LDRWui %X8<kill>, 796; mem:LD4[%calculatedBlockCRC8]
> %W9<def> = LDRBBui %X9<kill>, 12; mem:LD1[%state_out_ch9]
> %X10<def> = ADDXri %X10<kill>, <ga:@BZ2_crc32Table>[TF=34], 0
> %W11<def> = LDRWui %X11<kill>, 796; mem:LD4[%calculatedBlockCRC]
> %W8<def> = UBFMWri %W8<kill>, 24, 31
> %W8<def> = EORWrr %W8<kill>, %W9<kill>, %X8<imp-def>
> %X8<def> = UBFMXri %X8<kill>, 0, 31
> %X9<def> = MOVi64imm 4
> %X8<def> = MADDXrrr %X8<kill>, %X9<kill>, %XZR
> %X8<def> = ADDXrr %X10<kill>, %X8<kill>
> %W8<def> = LDRWui %X8<kill>, 0; mem:LD4[%arrayidx]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W8<def> = EORWrs %W8<kill>, %W11<kill>, 8
> STRWui %W8<kill>, %X9<kill>, 796; mem:ST4[%calculatedBlockCRC11]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = LDRWui %X8, 4; mem:LD4[%state_out_len12]
> %W9<def> = SUBWri %W9<kill>, 1, 0
> STRWui %W9<kill>, %X8<kill>, 4; mem:ST4[%state_out_len12]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X8<def> = LDRXui %X8<kill>, 0; mem:LD8[%strm13]
> %X9<def> = LDRXui %X8, 3; mem:LD8[%next_out14]
> %X9<def> = ADDXri %X9<kill>, 1, 0
> STRXui %X9<kill>, %X8<kill>, 3; mem:ST8[%next_out14]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X8<def> = LDRXui %X8<kill>, 0; mem:LD8[%strm15]
> %W9<def> = LDRWui %X8, 8; mem:LD4[%avail_out16]
> %W9<def> = SUBWri %W9<kill>, 1, 0
> STRWui %W9<kill>, %X8<kill>, 8; mem:ST4[%avail_out16]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X8<def> = LDRXui %X8<kill>, 0; mem:LD8[%strm18]
> %W9<def> = LDRWui %X8, 9; mem:LD4[%total_out_lo32]
> %W9<def> = ADDWri %W9<kill>, 1, 0
> STRWui %W9<kill>, %X8<kill>, 9; mem:ST4[%total_out_lo32]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X8<def> = LDRXui %X8<kill>, 0; mem:LD8[%strm19]
> %W8<def> = LDRWui %X8<kill>, 9; mem:LD4[%total_out_lo3220]
> CBNZW %W8<kill>, <BB#9>
1408B	BB#8: derived from LLVM BB %if.then.23
	    Live Ins: %X19
	    Predecessors according to CFG: BB#7
1424B		%vreg698<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg698
1440B		%vreg697<def> = LDRXui %vreg698<kill>, 0; mem:LD8[%strm24] GPR64common:%vreg697,%vreg698
1456B		%vreg695<def> = LDRWui %vreg697, 10; mem:LD4[%total_out_hi32] GPR32common:%vreg695 GPR64common:%vreg697
1472B		%vreg694<def> = ADDWri %vreg695<kill>, 1, 0; GPR32common:%vreg694,%vreg695
1488B		STRWui %vreg694<kill>, %vreg697<kill>, 10; mem:ST4[%total_out_hi32] GPR32common:%vreg694 GPR64common:%vreg697
	    Successors according to CFG: BB#9
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X8<def> = LDRXui %X8<kill>, 0; mem:LD8[%strm24]
> %W9<def> = LDRWui %X8, 10; mem:LD4[%total_out_hi32]
> %W9<def> = ADDWri %W9<kill>, 1, 0
> STRWui %W9<kill>, %X8<kill>, 10; mem:ST4[%total_out_hi32]
1504B	BB#9: derived from LLVM BB %if.end.26
	    Live Ins: %X19
	    Predecessors according to CFG: BB#7 BB#8
1520B		B <BB#3>
	    Successors according to CFG: BB#3
> B <BB#3>
1536B	BB#10: derived from LLVM BB %while.end
	    Live Ins: %X19
	    Predecessors according to CFG: BB#6
1584B		%vreg707<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg707
1592B		%vreg710<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg710
1600B		%vreg704<def> = MOVi64imm 64080; GPR64:%vreg704
1616B		%vreg705<def> = ADDXrr %vreg707<kill>, %vreg704<kill>; GPR64common:%vreg705 GPR64:%vreg707,%vreg704
1632B		%vreg706<def> = LDRWui %vreg705<kill>, 0; mem:LD4[%save_nblock] GPR32common:%vreg706 GPR64common:%vreg705
1640B		%vreg709<def> = LDRWui %vreg710<kill>, 273; mem:LD4[%nblock_used] GPR32:%vreg709 GPR64common:%vreg710
1648B		%vreg702<def> = ADDWri %vreg706<kill>, 1, 0; GPR32common:%vreg702,%vreg706
1664B		%WZR<def> = SUBSWrr %vreg709<kill>, %vreg702<kill>, %NZCV<imp-def>; GPR32:%vreg709 GPR32common:%vreg702
1680B		Bcc 1, <BB#12>, %NZCV<imp-use>
	    Successors according to CFG: BB#12 BB#11
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X10<def> = MOVi64imm 64080
> %X8<def> = ADDXrr %X8<kill>, %X10<kill>
> %W8<def> = LDRWui %X8<kill>, 0; mem:LD4[%save_nblock]
> %W9<def> = LDRWui %X9<kill>, 273; mem:LD4[%nblock_used]
> %W8<def> = ADDWri %W8<kill>, 1, 0
> %WZR<def> = SUBSWrr %W9<kill>, %W8<kill>, %NZCV<imp-def>
> Bcc 1, <BB#12>, %NZCV<imp-use>
1696B	BB#11: derived from LLVM BB %if.then.29
	    Live Ins: %X19
	    Predecessors according to CFG: BB#10
1712B		STRBBui %WZR, <fi#0>, 0; mem:ST1[FixedStack0]
1728B		B <BB#73>
	    Successors according to CFG: BB#73
> STRBBui %WZR, <fi#0>, 0; mem:ST1[FixedStack0]
> B <BB#73>
1744B	BB#12: derived from LLVM BB %if.end.30
	    Live Ins: %X19
	    Predecessors according to CFG: BB#10
1792B		%vreg719<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg719
1800B		%vreg722<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg722
1808B		%vreg716<def> = MOVi64imm 64080; GPR64:%vreg716
1824B		%vreg717<def> = ADDXrr %vreg719<kill>, %vreg716<kill>; GPR64common:%vreg717 GPR64:%vreg719,%vreg716
1840B		%vreg718<def> = LDRWui %vreg717<kill>, 0; mem:LD4[%save_nblock32] GPR32common:%vreg718 GPR64common:%vreg717
1848B		%vreg721<def> = LDRWui %vreg722<kill>, 273; mem:LD4[%nblock_used31] GPR32:%vreg721 GPR64common:%vreg722
1856B		%vreg714<def> = ADDWri %vreg718<kill>, 1, 0; GPR32common:%vreg714,%vreg718
1872B		%WZR<def> = SUBSWrr %vreg721<kill>, %vreg714<kill>, %NZCV<imp-def>; GPR32:%vreg721 GPR32common:%vreg714
1888B		Bcc 13, <BB#14>, %NZCV<imp-use>
	    Successors according to CFG: BB#14 BB#13
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X10<def> = MOVi64imm 64080
> %X8<def> = ADDXrr %X8<kill>, %X10<kill>
> %W8<def> = LDRWui %X8<kill>, 0; mem:LD4[%save_nblock32]
> %W9<def> = LDRWui %X9<kill>, 273; mem:LD4[%nblock_used31]
> %W8<def> = ADDWri %W8<kill>, 1, 0
> %WZR<def> = SUBSWrr %W9<kill>, %W8<kill>, %NZCV<imp-def>
> Bcc 13, <BB#14>, %NZCV<imp-use>
1904B	BB#13: derived from LLVM BB %if.then.36
	    Live Ins: %X19
	    Predecessors according to CFG: BB#12
1920B		%vreg1464<def> = MOVi32imm 1; GPR32:%vreg1464
1936B		STRBBui %vreg1464<kill>, <fi#0>, 0; mem:ST1[FixedStack0] GPR32:%vreg1464
1952B		B <BB#73>
	    Successors according to CFG: BB#73
> %W8<def> = MOVi32imm 1
> STRBBui %W8<kill>, <fi#0>, 0; mem:ST1[FixedStack0]
> B <BB#73>
1968B	BB#14: derived from LLVM BB %if.end.37
	    Live Ins: %X19
	    Predecessors according to CFG: BB#12
2000B		%vreg804<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg804
2008B		%vreg802<def> = MOVi32imm 1; GPR32:%vreg802
2016B		STRWui %vreg802<kill>, %vreg804<kill>, 4; mem:ST4[%state_out_len38] GPR32:%vreg802 GPR64common:%vreg804
2032B		%vreg801<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg801
2048B		%vreg798<def> = LDRWui %vreg801<kill>, 16; mem:LD4[%k0] GPR32:%vreg798 GPR64common:%vreg801
2080B		%vreg796<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg796
2096B		STRBBui %vreg798<kill>, %vreg796<kill>, 12; mem:ST1[%state_out_ch40] GPR32:%vreg798 GPR64common:%vreg796
2112B		%vreg793<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg793
2144B		%vreg790<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg790
2152B		%vreg792<def> = LDRWui %vreg793<kill>, 15; mem:LD4[%tPos] GPR32:%vreg792 GPR64common:%vreg793
2160B		%vreg789<def> = ADDXri %vreg790<kill>, 1096, 0; GPR64sp:%vreg789 GPR64common:%vreg790
2176B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2192B		%W0<def> = COPY %vreg792<kill>; GPR32:%vreg792
2208B		%X1<def> = COPY %vreg789<kill>; GPR64sp:%vreg789
2224B		BL <ga:@BZ2_indexIntoF>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use>, %W0<imp-def>
2240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2256B		%vreg783<def> = COPY %W0; GPR32:%vreg783
2272B		%vreg738<def> = MOVi32imm 4; GPR32:%vreg738
2288B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2304B		STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
2320B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2352B		STRBBui %vreg783<kill>, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg783
2368B		%vreg780<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg780
2416B		%vreg773<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg773
2424B		%vreg779:sub_32<def,read-undef> = LDRWui %vreg780<kill>, 15; mem:LD4[%tPos42] GPR64:%vreg779 GPR64common:%vreg780
2448B		%vreg768<def> = MOVi64imm 2; GPR64:%vreg768
2512B		%vreg761<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg761
2516B		%vreg772<def> = LDRXui %vreg773<kill>, 395; mem:LD8[%ll16] GPR64:%vreg772 GPR64common:%vreg773
2520B		%vreg769<def> = MADDXrrr %vreg779<kill>, %vreg768<kill>, %XZR; GPR64:%vreg769,%vreg779,%vreg768
2592B		%vreg753<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg753
2596B		%vreg760<def> = LDRWui %vreg761<kill>, 15; mem:LD4[%tPos46] GPR32:%vreg760 GPR64common:%vreg761
2600B		%vreg770<def> = ADDXrr %vreg772<kill>, %vreg769<kill>; GPR64common:%vreg770 GPR64:%vreg772,%vreg769
2656B		%vreg743<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg743
2664B		%vreg752<def> = LDRXui %vreg753<kill>, 396; mem:LD8[%ll4] GPR64:%vreg752 GPR64common:%vreg753
2672B		%vreg755:sub_32<def,read-undef> = UBFMWri %vreg760<kill>, 1, 31; GPR64:%vreg755 GPR32:%vreg760
2680B		%vreg756<def> = UBFMXri %vreg755<kill>, 0, 31; GPR64:%vreg756,%vreg755
2688B		%vreg742<def> = LDRWui %vreg743<kill>, 15; mem:LD4[%tPos51] GPR32:%vreg742 GPR64common:%vreg743
2696B		%vreg750<def> = ADDXrr %vreg752<kill>, %vreg756<kill>; GPR64common:%vreg750 GPR64:%vreg752,%vreg756
2704B		%vreg747<def> = LDRBBui %vreg750<kill>, 0; mem:LD1[%arrayidx49] GPR32:%vreg747 GPR64common:%vreg750
2712B		%vreg765<def> = LDRHHui %vreg770<kill>, 0; mem:LD2[%arrayidx44] GPR32:%vreg765 GPR64common:%vreg770
2720B		%vreg740<def> = ANDWrs %vreg738<kill>, %vreg742<kill>, 2; GPR32:%vreg740,%vreg738,%vreg742
2752B		%vreg729<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg729
2760B		%vreg737<def> = LSRVWr %vreg747<kill>, %vreg740<kill>; GPR32:%vreg737,%vreg747,%vreg740
2768B		%vreg734<def> = ANDWri %vreg737<kill>, 3; GPR32common:%vreg734 GPR32:%vreg737
2776B		%vreg732<def> = ORRWrs %vreg765<kill>, %vreg734<kill>, 16; GPR32:%vreg732,%vreg765 GPR32common:%vreg734
2784B		STRWui %vreg732<kill>, %vreg729<kill>, 15; mem:ST4[%tPos56] GPR32:%vreg732 GPR64common:%vreg729
2792B		%vreg726<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg726
2800B		%vreg725<def> = LDRWui %vreg726<kill>, 6; mem:LD4[%rNToGo] GPR32:%vreg725 GPR64common:%vreg726
2816B		CBNZW %vreg725<kill>, <BB#18>; GPR32:%vreg725
	    Successors according to CFG: BB#18 BB#15
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = MOVi32imm 1
> STRWui %W9<kill>, %X8<kill>, 4; mem:ST4[%state_out_len38]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W8<def> = LDRWui %X8<kill>, 16; mem:LD4[%k0]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRBBui %W8<kill>, %X9<kill>, 12; mem:ST1[%state_out_ch40]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W0<def> = LDRWui %X8<kill>, 15; mem:LD4[%tPos]
> %X1<def> = ADDXri %X9<kill>, 1096, 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = COPY %W0<kill>
Deleting identity copy.
> %X1<def> = COPY %X1<kill>
Deleting identity copy.
> BL <ga:@BZ2_indexIntoF>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use>, %W0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = COPY %W0
Deleting identity copy.
> %W8<def> = MOVi32imm 4
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRBBui %W0<kill>, <fi#2>, 0; mem:ST1[FixedStack2]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X10<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = LDRWui %X9<kill>, 15, %X9<imp-def>; mem:LD4[%tPos42]
> %X11<def> = MOVi64imm 2
> %X12<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X10<def> = LDRXui %X10<kill>, 395; mem:LD8[%ll16]
> %X9<def> = MADDXrrr %X9<kill>, %X11<kill>, %XZR
> %X11<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W12<def> = LDRWui %X12<kill>, 15; mem:LD4[%tPos46]
> %X9<def> = ADDXrr %X10<kill>, %X9<kill>
> %X10<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X11<def> = LDRXui %X11<kill>, 396; mem:LD8[%ll4]
> %W12<def> = UBFMWri %W12<kill>, 1, 31, %X12<imp-def>
> %X12<def> = UBFMXri %X12<kill>, 0, 31
> %W10<def> = LDRWui %X10<kill>, 15; mem:LD4[%tPos51]
> %X11<def> = ADDXrr %X11<kill>, %X12<kill>
> %W11<def> = LDRBBui %X11<kill>, 0; mem:LD1[%arrayidx49]
> %W9<def> = LDRHHui %X9<kill>, 0; mem:LD2[%arrayidx44]
> %W8<def> = ANDWrs %W8<kill>, %W10<kill>, 2
> %X10<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W8<def> = LSRVWr %W11<kill>, %W8<kill>
> %W8<def> = ANDWri %W8<kill>, 3
> %W8<def> = ORRWrs %W9<kill>, %W8<kill>, 16
> STRWui %W8<kill>, %X10<kill>, 15; mem:ST4[%tPos56]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W8<def> = LDRWui %X8<kill>, 6; mem:LD4[%rNToGo]
> CBNZW %W8<kill>, <BB#18>
2832B	BB#15: derived from LLVM BB %if.then.59
	    Live Ins: %X19
	    Predecessors according to CFG: BB#14
2880B		%vreg831<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg831
2896B		%vreg830<def> = LDRSWui %vreg831<kill>, 7; mem:LD4[%rTPos] GPR64:%vreg830 GPR64common:%vreg831
2904B		%vreg820<def> = ADRP <ga:@BZ2_rNums>[TF=1]; GPR64common:%vreg820
2912B		%vreg823<def> = MOVi64imm 4; GPR64:%vreg823
2920B		%vreg821<def> = ADDXri %vreg820<kill>, <ga:@BZ2_rNums>[TF=34], 0; GPR64common:%vreg821,%vreg820
2928B		%vreg824<def> = MADDXrrr %vreg830<kill>, %vreg823<kill>, %XZR; GPR64:%vreg824,%vreg830,%vreg823
2944B		%vreg825<def> = ADDXrr %vreg821<kill>, %vreg824<kill>; GPR64common:%vreg825,%vreg821 GPR64:%vreg824
2960B		%vreg819<def> = LDRWui %vreg825<kill>, 0; mem:LD4[%arrayidx61] GPR32:%vreg819 GPR64common:%vreg825
2976B		%vreg817<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg817
2992B		STRWui %vreg819<kill>, %vreg817<kill>, 6; mem:ST4[%rNToGo62] GPR32:%vreg819 GPR64common:%vreg817
3008B		%vreg814<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg814
3024B		%vreg813<def> = LDRWui %vreg814, 7; mem:LD4[%rTPos63] GPR32common:%vreg813 GPR64common:%vreg814
3040B		%vreg812<def> = ADDWri %vreg813<kill>, 1, 0; GPR32common:%vreg812,%vreg813
3056B		STRWui %vreg812<kill>, %vreg814<kill>, 7; mem:ST4[%rTPos63] GPR32common:%vreg812 GPR64common:%vreg814
3072B		%vreg808<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg808
3088B		%vreg807<def> = LDRWui %vreg808<kill>, 7; mem:LD4[%rTPos65] GPR32common:%vreg807 GPR64common:%vreg808
3104B		%WZR<def> = SUBSWri %vreg807<kill>, 512, 0, %NZCV<imp-def>; GPR32common:%vreg807
3120B		Bcc 1, <BB#17>, %NZCV<imp-use>
	    Successors according to CFG: BB#17 BB#16
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X8<def> = LDRSWui %X8<kill>, 7; mem:LD4[%rTPos]
> %X9<def> = ADRP <ga:@BZ2_rNums>[TF=1]
> %X10<def> = MOVi64imm 4
> %X9<def> = ADDXri %X9<kill>, <ga:@BZ2_rNums>[TF=34], 0
> %X8<def> = MADDXrrr %X8<kill>, %X10<kill>, %XZR
> %X8<def> = ADDXrr %X9<kill>, %X8<kill>
> %W8<def> = LDRWui %X8<kill>, 0; mem:LD4[%arrayidx61]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRWui %W8<kill>, %X9<kill>, 6; mem:ST4[%rNToGo62]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = LDRWui %X8, 7; mem:LD4[%rTPos63]
> %W9<def> = ADDWri %W9<kill>, 1, 0
> STRWui %W9<kill>, %X8<kill>, 7; mem:ST4[%rTPos63]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W8<def> = LDRWui %X8<kill>, 7; mem:LD4[%rTPos65]
> %WZR<def> = SUBSWri %W8<kill>, 512, 0, %NZCV<imp-def>
> Bcc 1, <BB#17>, %NZCV<imp-use>
3136B	BB#16: derived from LLVM BB %if.then.68
	    Live Ins: %X19
	    Predecessors according to CFG: BB#15
3152B		%vreg833<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg833
3168B		STRWui %WZR, %vreg833<kill>, 7; mem:ST4[%rTPos69] GPR64common:%vreg833
	    Successors according to CFG: BB#17
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRWui %WZR, %X8<kill>, 7; mem:ST4[%rTPos69]
3184B	BB#17: derived from LLVM BB %if.end.70
	    Live Ins: %X19
	    Predecessors according to CFG: BB#15 BB#16
3200B		B <BB#18>
	    Successors according to CFG: BB#18
> B <BB#18>
3216B	BB#18: derived from LLVM BB %if.end.71
	    Live Ins: %X19
	    Predecessors according to CFG: BB#14 BB#17
3224B		%vreg863<def> = COPY %WZR; GPR32:%vreg863
3264B		%vreg873<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg873
3280B		%vreg872<def> = LDRWui %vreg873, 6; mem:LD4[%rNToGo72] GPR32common:%vreg872 GPR64common:%vreg873
3296B		%vreg871<def> = SUBWri %vreg872<kill>, 1, 0; GPR32common:%vreg871,%vreg872
3312B		STRWui %vreg871<kill>, %vreg873<kill>, 6; mem:ST4[%rNToGo72] GPR32common:%vreg871 GPR64common:%vreg873
3328B		%vreg867<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg867
3344B		%vreg866<def> = LDRWui %vreg867<kill>, 6; mem:LD4[%rNToGo74] GPR32common:%vreg866 GPR64common:%vreg867
3392B		%vreg860<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg860
3400B		%vreg862<def> = MOVi32imm 1; GPR32:%vreg862
3408B		%WZR<def> = SUBSWri %vreg866<kill>, 1, 0, %NZCV<imp-def>; GPR32common:%vreg866
3416B		%vreg864<def> = CSELWr %vreg862<kill>, %vreg863<kill>, 0, %NZCV<imp-use>; GPR32:%vreg864,%vreg862,%vreg863
3424B		%vreg854<def> = EORWrr %vreg860<kill>, %vreg864<kill>; GPR32:%vreg854,%vreg860,%vreg864
3440B		STRBBui %vreg854<kill>, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg854
3456B		%vreg851<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg851
3472B		%vreg850<def> = LDRWui %vreg851, 273; mem:LD4[%nblock_used80] GPR32common:%vreg850 GPR64common:%vreg851
3488B		%vreg849<def> = ADDWri %vreg850<kill>, 1, 0; GPR32common:%vreg849,%vreg850
3504B		STRWui %vreg849<kill>, %vreg851<kill>, 273; mem:ST4[%nblock_used80] GPR32common:%vreg849 GPR64common:%vreg851
3552B		%vreg842<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg842
3560B		%vreg845<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg845
3568B		%vreg839<def> = MOVi64imm 64080; GPR64:%vreg839
3584B		%vreg840<def> = ADDXrr %vreg842<kill>, %vreg839<kill>; GPR64common:%vreg840 GPR64:%vreg842,%vreg839
3600B		%vreg841<def> = LDRWui %vreg840<kill>, 0; mem:LD4[%save_nblock83] GPR32common:%vreg841 GPR64common:%vreg840
3608B		%vreg844<def> = LDRWui %vreg845<kill>, 273; mem:LD4[%nblock_used82] GPR32:%vreg844 GPR64common:%vreg845
3616B		%vreg837<def> = ADDWri %vreg841<kill>, 1, 0; GPR32common:%vreg837,%vreg841
3632B		%WZR<def> = SUBSWrr %vreg844<kill>, %vreg837<kill>, %NZCV<imp-def>; GPR32:%vreg844 GPR32common:%vreg837
3648B		Bcc 1, <BB#20>, %NZCV<imp-use>
	    Successors according to CFG: BB#20 BB#19
> %W8<def> = COPY %WZR
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W10<def> = LDRWui %X9, 6; mem:LD4[%rNToGo72]
> %W10<def> = SUBWri %W10<kill>, 1, 0
> STRWui %W10<kill>, %X9<kill>, 6; mem:ST4[%rNToGo72]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = LDRWui %X9<kill>, 6; mem:LD4[%rNToGo74]
> %W10<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2]
> %W11<def> = MOVi32imm 1
> %WZR<def> = SUBSWri %W9<kill>, 1, 0, %NZCV<imp-def>
> %W8<def> = CSELWr %W11<kill>, %W8<kill>, 0, %NZCV<imp-use>
> %W8<def> = EORWrr %W10<kill>, %W8<kill>
> STRBBui %W8<kill>, <fi#2>, 0; mem:ST1[FixedStack2]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = LDRWui %X8, 273; mem:LD4[%nblock_used80]
> %W9<def> = ADDWri %W9<kill>, 1, 0
> STRWui %W9<kill>, %X8<kill>, 273; mem:ST4[%nblock_used80]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X10<def> = MOVi64imm 64080
> %X8<def> = ADDXrr %X8<kill>, %X10<kill>
> %W8<def> = LDRWui %X8<kill>, 0; mem:LD4[%save_nblock83]
> %W9<def> = LDRWui %X9<kill>, 273; mem:LD4[%nblock_used82]
> %W8<def> = ADDWri %W8<kill>, 1, 0
> %WZR<def> = SUBSWrr %W9<kill>, %W8<kill>, %NZCV<imp-def>
> Bcc 1, <BB#20>, %NZCV<imp-use>
3664B	BB#19: derived from LLVM BB %if.then.87
	    Live Ins: %X19
	    Predecessors according to CFG: BB#18
3680B		B <BB#2>
	    Successors according to CFG: BB#2
> B <BB#2>
3696B	BB#20: derived from LLVM BB %if.end.88
	    Live Ins: %X19
	    Predecessors according to CFG: BB#18
3728B		%vreg878<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg878
3736B		%vreg881<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg881
3744B		%vreg877<def> = LDRWui %vreg878<kill>, 16; mem:LD4[%k090] GPR32:%vreg877 GPR64common:%vreg878
3760B		%WZR<def> = SUBSWrr %vreg881<kill>, %vreg877<kill>, %NZCV<imp-def>; GPR32:%vreg881,%vreg877
3776B		Bcc 0, <BB#22>, %NZCV<imp-use>
	    Successors according to CFG: BB#22 BB#21
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2]
> %W8<def> = LDRWui %X8<kill>, 16; mem:LD4[%k090]
> %WZR<def> = SUBSWrr %W9<kill>, %W8<kill>, %NZCV<imp-def>
> Bcc 0, <BB#22>, %NZCV<imp-use>
3792B	BB#21: derived from LLVM BB %if.then.93
	    Live Ins: %X19
	    Predecessors according to CFG: BB#20
3808B		%vreg1463<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg1463
3824B		%vreg1460<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1460
3840B		STRWui %vreg1463<kill>, %vreg1460<kill>, 16; mem:ST4[%k095] GPR32:%vreg1463 GPR64common:%vreg1460
3856B		B <BB#2>
	    Successors according to CFG: BB#2
> %W8<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRWui %W8<kill>, %X9<kill>, 16; mem:ST4[%k095]
> B <BB#2>
3872B	BB#22: derived from LLVM BB %if.end.96
	    Live Ins: %X19
	    Predecessors according to CFG: BB#20
3904B		%vreg955<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg955
3912B		%vreg953<def> = MOVi32imm 2; GPR32:%vreg953
3920B		STRWui %vreg953<kill>, %vreg955<kill>, 4; mem:ST4[%state_out_len97] GPR32:%vreg953 GPR64common:%vreg955
3936B		%vreg952<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg952
3968B		%vreg949<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg949
3976B		%vreg951<def> = LDRWui %vreg952<kill>, 15; mem:LD4[%tPos98] GPR32:%vreg951 GPR64common:%vreg952
3984B		%vreg948<def> = ADDXri %vreg949<kill>, 1096, 0; GPR64sp:%vreg948 GPR64common:%vreg949
4000B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4016B		%W0<def> = COPY %vreg951<kill>; GPR32:%vreg951
4032B		%X1<def> = COPY %vreg948<kill>; GPR64sp:%vreg948
4048B		BL <ga:@BZ2_indexIntoF>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use>, %W0<imp-def>
4064B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4080B		%vreg942<def> = COPY %W0; GPR32:%vreg942
4096B		%vreg897<def> = MOVi32imm 4; GPR32:%vreg897
4112B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4128B		STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
4144B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4176B		STRBBui %vreg942<kill>, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg942
4192B		%vreg939<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg939
4240B		%vreg932<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg932
4248B		%vreg938:sub_32<def,read-undef> = LDRWui %vreg939<kill>, 15; mem:LD4[%tPos103] GPR64:%vreg938 GPR64common:%vreg939
4272B		%vreg927<def> = MOVi64imm 2; GPR64:%vreg927
4336B		%vreg920<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg920
4340B		%vreg931<def> = LDRXui %vreg932<kill>, 395; mem:LD8[%ll16105] GPR64:%vreg931 GPR64common:%vreg932
4344B		%vreg928<def> = MADDXrrr %vreg938<kill>, %vreg927<kill>, %XZR; GPR64:%vreg928,%vreg938,%vreg927
4416B		%vreg912<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg912
4420B		%vreg919<def> = LDRWui %vreg920<kill>, 15; mem:LD4[%tPos108] GPR32:%vreg919 GPR64common:%vreg920
4424B		%vreg929<def> = ADDXrr %vreg931<kill>, %vreg928<kill>; GPR64common:%vreg929 GPR64:%vreg931,%vreg928
4480B		%vreg902<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg902
4488B		%vreg911<def> = LDRXui %vreg912<kill>, 396; mem:LD8[%ll4111] GPR64:%vreg911 GPR64common:%vreg912
4496B		%vreg914:sub_32<def,read-undef> = UBFMWri %vreg919<kill>, 1, 31; GPR64:%vreg914 GPR32:%vreg919
4504B		%vreg915<def> = UBFMXri %vreg914<kill>, 0, 31; GPR64:%vreg915,%vreg914
4512B		%vreg901<def> = LDRWui %vreg902<kill>, 15; mem:LD4[%tPos114] GPR32:%vreg901 GPR64common:%vreg902
4520B		%vreg909<def> = ADDXrr %vreg911<kill>, %vreg915<kill>; GPR64common:%vreg909 GPR64:%vreg911,%vreg915
4528B		%vreg906<def> = LDRBBui %vreg909<kill>, 0; mem:LD1[%arrayidx112] GPR32:%vreg906 GPR64common:%vreg909
4536B		%vreg924<def> = LDRHHui %vreg929<kill>, 0; mem:LD2[%arrayidx106] GPR32:%vreg924 GPR64common:%vreg929
4544B		%vreg899<def> = ANDWrs %vreg897<kill>, %vreg901<kill>, 2; GPR32:%vreg899,%vreg897,%vreg901
4576B		%vreg888<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg888
4584B		%vreg896<def> = LSRVWr %vreg906<kill>, %vreg899<kill>; GPR32:%vreg896,%vreg906,%vreg899
4592B		%vreg893<def> = ANDWri %vreg896<kill>, 3; GPR32common:%vreg893 GPR32:%vreg896
4600B		%vreg891<def> = ORRWrs %vreg924<kill>, %vreg893<kill>, 16; GPR32:%vreg891,%vreg924 GPR32common:%vreg893
4608B		STRWui %vreg891<kill>, %vreg888<kill>, 15; mem:ST4[%tPos121] GPR32:%vreg891 GPR64common:%vreg888
4616B		%vreg885<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg885
4624B		%vreg884<def> = LDRWui %vreg885<kill>, 6; mem:LD4[%rNToGo122] GPR32:%vreg884 GPR64common:%vreg885
4640B		CBNZW %vreg884<kill>, <BB#26>; GPR32:%vreg884
	    Successors according to CFG: BB#26 BB#23
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = MOVi32imm 2
> STRWui %W9<kill>, %X8<kill>, 4; mem:ST4[%state_out_len97]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W0<def> = LDRWui %X8<kill>, 15; mem:LD4[%tPos98]
> %X1<def> = ADDXri %X9<kill>, 1096, 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = COPY %W0<kill>
Deleting identity copy.
> %X1<def> = COPY %X1<kill>
Deleting identity copy.
> BL <ga:@BZ2_indexIntoF>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use>, %W0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = COPY %W0
Deleting identity copy.
> %W8<def> = MOVi32imm 4
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRBBui %W0<kill>, <fi#2>, 0; mem:ST1[FixedStack2]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X10<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = LDRWui %X9<kill>, 15, %X9<imp-def>; mem:LD4[%tPos103]
> %X11<def> = MOVi64imm 2
> %X12<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X10<def> = LDRXui %X10<kill>, 395; mem:LD8[%ll16105]
> %X9<def> = MADDXrrr %X9<kill>, %X11<kill>, %XZR
> %X11<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W12<def> = LDRWui %X12<kill>, 15; mem:LD4[%tPos108]
> %X9<def> = ADDXrr %X10<kill>, %X9<kill>
> %X10<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X11<def> = LDRXui %X11<kill>, 396; mem:LD8[%ll4111]
> %W12<def> = UBFMWri %W12<kill>, 1, 31, %X12<imp-def>
> %X12<def> = UBFMXri %X12<kill>, 0, 31
> %W10<def> = LDRWui %X10<kill>, 15; mem:LD4[%tPos114]
> %X11<def> = ADDXrr %X11<kill>, %X12<kill>
> %W11<def> = LDRBBui %X11<kill>, 0; mem:LD1[%arrayidx112]
> %W9<def> = LDRHHui %X9<kill>, 0; mem:LD2[%arrayidx106]
> %W8<def> = ANDWrs %W8<kill>, %W10<kill>, 2
> %X10<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W8<def> = LSRVWr %W11<kill>, %W8<kill>
> %W8<def> = ANDWri %W8<kill>, 3
> %W8<def> = ORRWrs %W9<kill>, %W8<kill>, 16
> STRWui %W8<kill>, %X10<kill>, 15; mem:ST4[%tPos121]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W8<def> = LDRWui %X8<kill>, 6; mem:LD4[%rNToGo122]
> CBNZW %W8<kill>, <BB#26>
4656B	BB#23: derived from LLVM BB %if.then.125
	    Live Ins: %X19
	    Predecessors according to CFG: BB#22
4704B		%vreg982<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg982
4720B		%vreg981<def> = LDRSWui %vreg982<kill>, 7; mem:LD4[%rTPos126] GPR64:%vreg981 GPR64common:%vreg982
4728B		%vreg971<def> = ADRP <ga:@BZ2_rNums>[TF=1]; GPR64common:%vreg971
4736B		%vreg974<def> = MOVi64imm 4; GPR64:%vreg974
4744B		%vreg972<def> = ADDXri %vreg971<kill>, <ga:@BZ2_rNums>[TF=34], 0; GPR64common:%vreg972,%vreg971
4752B		%vreg975<def> = MADDXrrr %vreg981<kill>, %vreg974<kill>, %XZR; GPR64:%vreg975,%vreg981,%vreg974
4768B		%vreg976<def> = ADDXrr %vreg972<kill>, %vreg975<kill>; GPR64common:%vreg976,%vreg972 GPR64:%vreg975
4784B		%vreg970<def> = LDRWui %vreg976<kill>, 0; mem:LD4[%arrayidx128] GPR32:%vreg970 GPR64common:%vreg976
4800B		%vreg968<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg968
4816B		STRWui %vreg970<kill>, %vreg968<kill>, 6; mem:ST4[%rNToGo129] GPR32:%vreg970 GPR64common:%vreg968
4832B		%vreg965<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg965
4848B		%vreg964<def> = LDRWui %vreg965, 7; mem:LD4[%rTPos130] GPR32common:%vreg964 GPR64common:%vreg965
4864B		%vreg963<def> = ADDWri %vreg964<kill>, 1, 0; GPR32common:%vreg963,%vreg964
4880B		STRWui %vreg963<kill>, %vreg965<kill>, 7; mem:ST4[%rTPos130] GPR32common:%vreg963 GPR64common:%vreg965
4896B		%vreg959<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg959
4912B		%vreg958<def> = LDRWui %vreg959<kill>, 7; mem:LD4[%rTPos132] GPR32common:%vreg958 GPR64common:%vreg959
4928B		%WZR<def> = SUBSWri %vreg958<kill>, 512, 0, %NZCV<imp-def>; GPR32common:%vreg958
4944B		Bcc 1, <BB#25>, %NZCV<imp-use>
	    Successors according to CFG: BB#25 BB#24
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X8<def> = LDRSWui %X8<kill>, 7; mem:LD4[%rTPos126]
> %X9<def> = ADRP <ga:@BZ2_rNums>[TF=1]
> %X10<def> = MOVi64imm 4
> %X9<def> = ADDXri %X9<kill>, <ga:@BZ2_rNums>[TF=34], 0
> %X8<def> = MADDXrrr %X8<kill>, %X10<kill>, %XZR
> %X8<def> = ADDXrr %X9<kill>, %X8<kill>
> %W8<def> = LDRWui %X8<kill>, 0; mem:LD4[%arrayidx128]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRWui %W8<kill>, %X9<kill>, 6; mem:ST4[%rNToGo129]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = LDRWui %X8, 7; mem:LD4[%rTPos130]
> %W9<def> = ADDWri %W9<kill>, 1, 0
> STRWui %W9<kill>, %X8<kill>, 7; mem:ST4[%rTPos130]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W8<def> = LDRWui %X8<kill>, 7; mem:LD4[%rTPos132]
> %WZR<def> = SUBSWri %W8<kill>, 512, 0, %NZCV<imp-def>
> Bcc 1, <BB#25>, %NZCV<imp-use>
4960B	BB#24: derived from LLVM BB %if.then.135
	    Live Ins: %X19
	    Predecessors according to CFG: BB#23
4976B		%vreg984<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg984
4992B		STRWui %WZR, %vreg984<kill>, 7; mem:ST4[%rTPos136] GPR64common:%vreg984
	    Successors according to CFG: BB#25
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRWui %WZR, %X8<kill>, 7; mem:ST4[%rTPos136]
5008B	BB#25: derived from LLVM BB %if.end.137
	    Live Ins: %X19
	    Predecessors according to CFG: BB#23 BB#24
5024B		B <BB#26>
	    Successors according to CFG: BB#26
> B <BB#26>
5040B	BB#26: derived from LLVM BB %if.end.138
	    Live Ins: %X19
	    Predecessors according to CFG: BB#22 BB#25
5048B		%vreg1014<def> = COPY %WZR; GPR32:%vreg1014
5088B		%vreg1024<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1024
5104B		%vreg1023<def> = LDRWui %vreg1024, 6; mem:LD4[%rNToGo139] GPR32common:%vreg1023 GPR64common:%vreg1024
5120B		%vreg1022<def> = SUBWri %vreg1023<kill>, 1, 0; GPR32common:%vreg1022,%vreg1023
5136B		STRWui %vreg1022<kill>, %vreg1024<kill>, 6; mem:ST4[%rNToGo139] GPR32common:%vreg1022 GPR64common:%vreg1024
5152B		%vreg1018<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1018
5168B		%vreg1017<def> = LDRWui %vreg1018<kill>, 6; mem:LD4[%rNToGo141] GPR32common:%vreg1017 GPR64common:%vreg1018
5216B		%vreg1011<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg1011
5224B		%vreg1013<def> = MOVi32imm 1; GPR32:%vreg1013
5232B		%WZR<def> = SUBSWri %vreg1017<kill>, 1, 0, %NZCV<imp-def>; GPR32common:%vreg1017
5240B		%vreg1015<def> = CSELWr %vreg1013<kill>, %vreg1014<kill>, 0, %NZCV<imp-use>; GPR32:%vreg1015,%vreg1013,%vreg1014
5248B		%vreg1005<def> = EORWrr %vreg1011<kill>, %vreg1015<kill>; GPR32:%vreg1005,%vreg1011,%vreg1015
5264B		STRBBui %vreg1005<kill>, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg1005
5280B		%vreg1002<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1002
5296B		%vreg1001<def> = LDRWui %vreg1002, 273; mem:LD4[%nblock_used148] GPR32common:%vreg1001 GPR64common:%vreg1002
5312B		%vreg1000<def> = ADDWri %vreg1001<kill>, 1, 0; GPR32common:%vreg1000,%vreg1001
5328B		STRWui %vreg1000<kill>, %vreg1002<kill>, 273; mem:ST4[%nblock_used148] GPR32common:%vreg1000 GPR64common:%vreg1002
5376B		%vreg993<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg993
5384B		%vreg996<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg996
5392B		%vreg990<def> = MOVi64imm 64080; GPR64:%vreg990
5408B		%vreg991<def> = ADDXrr %vreg993<kill>, %vreg990<kill>; GPR64common:%vreg991 GPR64:%vreg993,%vreg990
5424B		%vreg992<def> = LDRWui %vreg991<kill>, 0; mem:LD4[%save_nblock151] GPR32common:%vreg992 GPR64common:%vreg991
5432B		%vreg995<def> = LDRWui %vreg996<kill>, 273; mem:LD4[%nblock_used150] GPR32:%vreg995 GPR64common:%vreg996
5440B		%vreg988<def> = ADDWri %vreg992<kill>, 1, 0; GPR32common:%vreg988,%vreg992
5456B		%WZR<def> = SUBSWrr %vreg995<kill>, %vreg988<kill>, %NZCV<imp-def>; GPR32:%vreg995 GPR32common:%vreg988
5472B		Bcc 1, <BB#28>, %NZCV<imp-use>
	    Successors according to CFG: BB#28 BB#27
> %W8<def> = COPY %WZR
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W10<def> = LDRWui %X9, 6; mem:LD4[%rNToGo139]
> %W10<def> = SUBWri %W10<kill>, 1, 0
> STRWui %W10<kill>, %X9<kill>, 6; mem:ST4[%rNToGo139]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = LDRWui %X9<kill>, 6; mem:LD4[%rNToGo141]
> %W10<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2]
> %W11<def> = MOVi32imm 1
> %WZR<def> = SUBSWri %W9<kill>, 1, 0, %NZCV<imp-def>
> %W8<def> = CSELWr %W11<kill>, %W8<kill>, 0, %NZCV<imp-use>
> %W8<def> = EORWrr %W10<kill>, %W8<kill>
> STRBBui %W8<kill>, <fi#2>, 0; mem:ST1[FixedStack2]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = LDRWui %X8, 273; mem:LD4[%nblock_used148]
> %W9<def> = ADDWri %W9<kill>, 1, 0
> STRWui %W9<kill>, %X8<kill>, 273; mem:ST4[%nblock_used148]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X10<def> = MOVi64imm 64080
> %X8<def> = ADDXrr %X8<kill>, %X10<kill>
> %W8<def> = LDRWui %X8<kill>, 0; mem:LD4[%save_nblock151]
> %W9<def> = LDRWui %X9<kill>, 273; mem:LD4[%nblock_used150]
> %W8<def> = ADDWri %W8<kill>, 1, 0
> %WZR<def> = SUBSWrr %W9<kill>, %W8<kill>, %NZCV<imp-def>
> Bcc 1, <BB#28>, %NZCV<imp-use>
5488B	BB#27: derived from LLVM BB %if.then.155
	    Live Ins: %X19
	    Predecessors according to CFG: BB#26
5504B		B <BB#2>
	    Successors according to CFG: BB#2
> B <BB#2>
5520B	BB#28: derived from LLVM BB %if.end.156
	    Live Ins: %X19
	    Predecessors according to CFG: BB#26
5552B		%vreg1029<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1029
5560B		%vreg1032<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg1032
5568B		%vreg1028<def> = LDRWui %vreg1029<kill>, 16; mem:LD4[%k0158] GPR32:%vreg1028 GPR64common:%vreg1029
5584B		%WZR<def> = SUBSWrr %vreg1032<kill>, %vreg1028<kill>, %NZCV<imp-def>; GPR32:%vreg1032,%vreg1028
5600B		Bcc 0, <BB#30>, %NZCV<imp-use>
	    Successors according to CFG: BB#30 BB#29
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2]
> %W8<def> = LDRWui %X8<kill>, 16; mem:LD4[%k0158]
> %WZR<def> = SUBSWrr %W9<kill>, %W8<kill>, %NZCV<imp-def>
> Bcc 0, <BB#30>, %NZCV<imp-use>
5616B	BB#29: derived from LLVM BB %if.then.161
	    Live Ins: %X19
	    Predecessors according to CFG: BB#28
5632B		%vreg1457<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg1457
5648B		%vreg1454<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1454
5664B		STRWui %vreg1457<kill>, %vreg1454<kill>, 16; mem:ST4[%k0163] GPR32:%vreg1457 GPR64common:%vreg1454
5680B		B <BB#2>
	    Successors according to CFG: BB#2
> %W8<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRWui %W8<kill>, %X9<kill>, 16; mem:ST4[%k0163]
> B <BB#2>
5696B	BB#30: derived from LLVM BB %if.end.164
	    Live Ins: %X19
	    Predecessors according to CFG: BB#28
5728B		%vreg1106<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1106
5736B		%vreg1104<def> = MOVi32imm 3; GPR32:%vreg1104
5744B		STRWui %vreg1104<kill>, %vreg1106<kill>, 4; mem:ST4[%state_out_len165] GPR32:%vreg1104 GPR64common:%vreg1106
5760B		%vreg1103<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1103
5792B		%vreg1100<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1100
5800B		%vreg1102<def> = LDRWui %vreg1103<kill>, 15; mem:LD4[%tPos166] GPR32:%vreg1102 GPR64common:%vreg1103
5808B		%vreg1099<def> = ADDXri %vreg1100<kill>, 1096, 0; GPR64sp:%vreg1099 GPR64common:%vreg1100
5824B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5840B		%W0<def> = COPY %vreg1102<kill>; GPR32:%vreg1102
5856B		%X1<def> = COPY %vreg1099<kill>; GPR64sp:%vreg1099
5872B		BL <ga:@BZ2_indexIntoF>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use>, %W0<imp-def>
5888B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5904B		%vreg1093<def> = COPY %W0; GPR32:%vreg1093
5920B		%vreg1048<def> = MOVi32imm 4; GPR32:%vreg1048
5936B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5952B		STACKMAP 3, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
5968B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
6000B		STRBBui %vreg1093<kill>, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg1093
6016B		%vreg1090<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1090
6064B		%vreg1083<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1083
6072B		%vreg1089:sub_32<def,read-undef> = LDRWui %vreg1090<kill>, 15; mem:LD4[%tPos171] GPR64:%vreg1089 GPR64common:%vreg1090
6096B		%vreg1078<def> = MOVi64imm 2; GPR64:%vreg1078
6160B		%vreg1071<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1071
6164B		%vreg1082<def> = LDRXui %vreg1083<kill>, 395; mem:LD8[%ll16173] GPR64:%vreg1082 GPR64common:%vreg1083
6168B		%vreg1079<def> = MADDXrrr %vreg1089<kill>, %vreg1078<kill>, %XZR; GPR64:%vreg1079,%vreg1089,%vreg1078
6240B		%vreg1063<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1063
6244B		%vreg1070<def> = LDRWui %vreg1071<kill>, 15; mem:LD4[%tPos176] GPR32:%vreg1070 GPR64common:%vreg1071
6248B		%vreg1080<def> = ADDXrr %vreg1082<kill>, %vreg1079<kill>; GPR64common:%vreg1080 GPR64:%vreg1082,%vreg1079
6304B		%vreg1053<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1053
6312B		%vreg1062<def> = LDRXui %vreg1063<kill>, 396; mem:LD8[%ll4179] GPR64:%vreg1062 GPR64common:%vreg1063
6320B		%vreg1065:sub_32<def,read-undef> = UBFMWri %vreg1070<kill>, 1, 31; GPR64:%vreg1065 GPR32:%vreg1070
6328B		%vreg1066<def> = UBFMXri %vreg1065<kill>, 0, 31; GPR64:%vreg1066,%vreg1065
6336B		%vreg1052<def> = LDRWui %vreg1053<kill>, 15; mem:LD4[%tPos182] GPR32:%vreg1052 GPR64common:%vreg1053
6344B		%vreg1060<def> = ADDXrr %vreg1062<kill>, %vreg1066<kill>; GPR64common:%vreg1060 GPR64:%vreg1062,%vreg1066
6352B		%vreg1057<def> = LDRBBui %vreg1060<kill>, 0; mem:LD1[%arrayidx180] GPR32:%vreg1057 GPR64common:%vreg1060
6360B		%vreg1075<def> = LDRHHui %vreg1080<kill>, 0; mem:LD2[%arrayidx174] GPR32:%vreg1075 GPR64common:%vreg1080
6368B		%vreg1050<def> = ANDWrs %vreg1048<kill>, %vreg1052<kill>, 2; GPR32:%vreg1050,%vreg1048,%vreg1052
6400B		%vreg1039<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1039
6408B		%vreg1047<def> = LSRVWr %vreg1057<kill>, %vreg1050<kill>; GPR32:%vreg1047,%vreg1057,%vreg1050
6416B		%vreg1044<def> = ANDWri %vreg1047<kill>, 3; GPR32common:%vreg1044 GPR32:%vreg1047
6424B		%vreg1042<def> = ORRWrs %vreg1075<kill>, %vreg1044<kill>, 16; GPR32:%vreg1042,%vreg1075 GPR32common:%vreg1044
6432B		STRWui %vreg1042<kill>, %vreg1039<kill>, 15; mem:ST4[%tPos189] GPR32:%vreg1042 GPR64common:%vreg1039
6440B		%vreg1036<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1036
6448B		%vreg1035<def> = LDRWui %vreg1036<kill>, 6; mem:LD4[%rNToGo190] GPR32:%vreg1035 GPR64common:%vreg1036
6464B		CBNZW %vreg1035<kill>, <BB#34>; GPR32:%vreg1035
	    Successors according to CFG: BB#34 BB#31
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = MOVi32imm 3
> STRWui %W9<kill>, %X8<kill>, 4; mem:ST4[%state_out_len165]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W0<def> = LDRWui %X8<kill>, 15; mem:LD4[%tPos166]
> %X1<def> = ADDXri %X9<kill>, 1096, 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = COPY %W0<kill>
Deleting identity copy.
> %X1<def> = COPY %X1<kill>
Deleting identity copy.
> BL <ga:@BZ2_indexIntoF>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use>, %W0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = COPY %W0
Deleting identity copy.
> %W8<def> = MOVi32imm 4
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 3, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRBBui %W0<kill>, <fi#2>, 0; mem:ST1[FixedStack2]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X10<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = LDRWui %X9<kill>, 15, %X9<imp-def>; mem:LD4[%tPos171]
> %X11<def> = MOVi64imm 2
> %X12<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X10<def> = LDRXui %X10<kill>, 395; mem:LD8[%ll16173]
> %X9<def> = MADDXrrr %X9<kill>, %X11<kill>, %XZR
> %X11<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W12<def> = LDRWui %X12<kill>, 15; mem:LD4[%tPos176]
> %X9<def> = ADDXrr %X10<kill>, %X9<kill>
> %X10<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X11<def> = LDRXui %X11<kill>, 396; mem:LD8[%ll4179]
> %W12<def> = UBFMWri %W12<kill>, 1, 31, %X12<imp-def>
> %X12<def> = UBFMXri %X12<kill>, 0, 31
> %W10<def> = LDRWui %X10<kill>, 15; mem:LD4[%tPos182]
> %X11<def> = ADDXrr %X11<kill>, %X12<kill>
> %W11<def> = LDRBBui %X11<kill>, 0; mem:LD1[%arrayidx180]
> %W9<def> = LDRHHui %X9<kill>, 0; mem:LD2[%arrayidx174]
> %W8<def> = ANDWrs %W8<kill>, %W10<kill>, 2
> %X10<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W8<def> = LSRVWr %W11<kill>, %W8<kill>
> %W8<def> = ANDWri %W8<kill>, 3
> %W8<def> = ORRWrs %W9<kill>, %W8<kill>, 16
> STRWui %W8<kill>, %X10<kill>, 15; mem:ST4[%tPos189]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W8<def> = LDRWui %X8<kill>, 6; mem:LD4[%rNToGo190]
> CBNZW %W8<kill>, <BB#34>
6480B	BB#31: derived from LLVM BB %if.then.193
	    Live Ins: %X19
	    Predecessors according to CFG: BB#30
6528B		%vreg1133<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1133
6544B		%vreg1132<def> = LDRSWui %vreg1133<kill>, 7; mem:LD4[%rTPos194] GPR64:%vreg1132 GPR64common:%vreg1133
6552B		%vreg1122<def> = ADRP <ga:@BZ2_rNums>[TF=1]; GPR64common:%vreg1122
6560B		%vreg1125<def> = MOVi64imm 4; GPR64:%vreg1125
6568B		%vreg1123<def> = ADDXri %vreg1122<kill>, <ga:@BZ2_rNums>[TF=34], 0; GPR64common:%vreg1123,%vreg1122
6576B		%vreg1126<def> = MADDXrrr %vreg1132<kill>, %vreg1125<kill>, %XZR; GPR64:%vreg1126,%vreg1132,%vreg1125
6592B		%vreg1127<def> = ADDXrr %vreg1123<kill>, %vreg1126<kill>; GPR64common:%vreg1127,%vreg1123 GPR64:%vreg1126
6608B		%vreg1121<def> = LDRWui %vreg1127<kill>, 0; mem:LD4[%arrayidx196] GPR32:%vreg1121 GPR64common:%vreg1127
6624B		%vreg1119<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1119
6640B		STRWui %vreg1121<kill>, %vreg1119<kill>, 6; mem:ST4[%rNToGo197] GPR32:%vreg1121 GPR64common:%vreg1119
6656B		%vreg1116<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1116
6672B		%vreg1115<def> = LDRWui %vreg1116, 7; mem:LD4[%rTPos198] GPR32common:%vreg1115 GPR64common:%vreg1116
6688B		%vreg1114<def> = ADDWri %vreg1115<kill>, 1, 0; GPR32common:%vreg1114,%vreg1115
6704B		STRWui %vreg1114<kill>, %vreg1116<kill>, 7; mem:ST4[%rTPos198] GPR32common:%vreg1114 GPR64common:%vreg1116
6720B		%vreg1110<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1110
6736B		%vreg1109<def> = LDRWui %vreg1110<kill>, 7; mem:LD4[%rTPos200] GPR32common:%vreg1109 GPR64common:%vreg1110
6752B		%WZR<def> = SUBSWri %vreg1109<kill>, 512, 0, %NZCV<imp-def>; GPR32common:%vreg1109
6768B		Bcc 1, <BB#33>, %NZCV<imp-use>
	    Successors according to CFG: BB#33 BB#32
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X8<def> = LDRSWui %X8<kill>, 7; mem:LD4[%rTPos194]
> %X9<def> = ADRP <ga:@BZ2_rNums>[TF=1]
> %X10<def> = MOVi64imm 4
> %X9<def> = ADDXri %X9<kill>, <ga:@BZ2_rNums>[TF=34], 0
> %X8<def> = MADDXrrr %X8<kill>, %X10<kill>, %XZR
> %X8<def> = ADDXrr %X9<kill>, %X8<kill>
> %W8<def> = LDRWui %X8<kill>, 0; mem:LD4[%arrayidx196]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRWui %W8<kill>, %X9<kill>, 6; mem:ST4[%rNToGo197]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = LDRWui %X8, 7; mem:LD4[%rTPos198]
> %W9<def> = ADDWri %W9<kill>, 1, 0
> STRWui %W9<kill>, %X8<kill>, 7; mem:ST4[%rTPos198]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W8<def> = LDRWui %X8<kill>, 7; mem:LD4[%rTPos200]
> %WZR<def> = SUBSWri %W8<kill>, 512, 0, %NZCV<imp-def>
> Bcc 1, <BB#33>, %NZCV<imp-use>
6784B	BB#32: derived from LLVM BB %if.then.203
	    Live Ins: %X19
	    Predecessors according to CFG: BB#31
6800B		%vreg1135<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1135
6816B		STRWui %WZR, %vreg1135<kill>, 7; mem:ST4[%rTPos204] GPR64common:%vreg1135
	    Successors according to CFG: BB#33
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRWui %WZR, %X8<kill>, 7; mem:ST4[%rTPos204]
6832B	BB#33: derived from LLVM BB %if.end.205
	    Live Ins: %X19
	    Predecessors according to CFG: BB#31 BB#32
6848B		B <BB#34>
	    Successors according to CFG: BB#34
> B <BB#34>
6864B	BB#34: derived from LLVM BB %if.end.206
	    Live Ins: %X19
	    Predecessors according to CFG: BB#30 BB#33
6872B		%vreg1165<def> = COPY %WZR; GPR32:%vreg1165
6912B		%vreg1175<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1175
6928B		%vreg1174<def> = LDRWui %vreg1175, 6; mem:LD4[%rNToGo207] GPR32common:%vreg1174 GPR64common:%vreg1175
6944B		%vreg1173<def> = SUBWri %vreg1174<kill>, 1, 0; GPR32common:%vreg1173,%vreg1174
6960B		STRWui %vreg1173<kill>, %vreg1175<kill>, 6; mem:ST4[%rNToGo207] GPR32common:%vreg1173 GPR64common:%vreg1175
6976B		%vreg1169<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1169
6992B		%vreg1168<def> = LDRWui %vreg1169<kill>, 6; mem:LD4[%rNToGo209] GPR32common:%vreg1168 GPR64common:%vreg1169
7040B		%vreg1162<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg1162
7048B		%vreg1164<def> = MOVi32imm 1; GPR32:%vreg1164
7056B		%WZR<def> = SUBSWri %vreg1168<kill>, 1, 0, %NZCV<imp-def>; GPR32common:%vreg1168
7064B		%vreg1166<def> = CSELWr %vreg1164<kill>, %vreg1165<kill>, 0, %NZCV<imp-use>; GPR32:%vreg1166,%vreg1164,%vreg1165
7072B		%vreg1156<def> = EORWrr %vreg1162<kill>, %vreg1166<kill>; GPR32:%vreg1156,%vreg1162,%vreg1166
7088B		STRBBui %vreg1156<kill>, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg1156
7104B		%vreg1153<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1153
7120B		%vreg1152<def> = LDRWui %vreg1153, 273; mem:LD4[%nblock_used216] GPR32common:%vreg1152 GPR64common:%vreg1153
7136B		%vreg1151<def> = ADDWri %vreg1152<kill>, 1, 0; GPR32common:%vreg1151,%vreg1152
7152B		STRWui %vreg1151<kill>, %vreg1153<kill>, 273; mem:ST4[%nblock_used216] GPR32common:%vreg1151 GPR64common:%vreg1153
7200B		%vreg1144<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg1144
7208B		%vreg1147<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1147
7216B		%vreg1141<def> = MOVi64imm 64080; GPR64:%vreg1141
7232B		%vreg1142<def> = ADDXrr %vreg1144<kill>, %vreg1141<kill>; GPR64common:%vreg1142 GPR64:%vreg1144,%vreg1141
7248B		%vreg1143<def> = LDRWui %vreg1142<kill>, 0; mem:LD4[%save_nblock219] GPR32common:%vreg1143 GPR64common:%vreg1142
7256B		%vreg1146<def> = LDRWui %vreg1147<kill>, 273; mem:LD4[%nblock_used218] GPR32:%vreg1146 GPR64common:%vreg1147
7264B		%vreg1139<def> = ADDWri %vreg1143<kill>, 1, 0; GPR32common:%vreg1139,%vreg1143
7280B		%WZR<def> = SUBSWrr %vreg1146<kill>, %vreg1139<kill>, %NZCV<imp-def>; GPR32:%vreg1146 GPR32common:%vreg1139
7296B		Bcc 1, <BB#36>, %NZCV<imp-use>
	    Successors according to CFG: BB#36 BB#35
> %W8<def> = COPY %WZR
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W10<def> = LDRWui %X9, 6; mem:LD4[%rNToGo207]
> %W10<def> = SUBWri %W10<kill>, 1, 0
> STRWui %W10<kill>, %X9<kill>, 6; mem:ST4[%rNToGo207]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = LDRWui %X9<kill>, 6; mem:LD4[%rNToGo209]
> %W10<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2]
> %W11<def> = MOVi32imm 1
> %WZR<def> = SUBSWri %W9<kill>, 1, 0, %NZCV<imp-def>
> %W8<def> = CSELWr %W11<kill>, %W8<kill>, 0, %NZCV<imp-use>
> %W8<def> = EORWrr %W10<kill>, %W8<kill>
> STRBBui %W8<kill>, <fi#2>, 0; mem:ST1[FixedStack2]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = LDRWui %X8, 273; mem:LD4[%nblock_used216]
> %W9<def> = ADDWri %W9<kill>, 1, 0
> STRWui %W9<kill>, %X8<kill>, 273; mem:ST4[%nblock_used216]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X10<def> = MOVi64imm 64080
> %X8<def> = ADDXrr %X8<kill>, %X10<kill>
> %W8<def> = LDRWui %X8<kill>, 0; mem:LD4[%save_nblock219]
> %W9<def> = LDRWui %X9<kill>, 273; mem:LD4[%nblock_used218]
> %W8<def> = ADDWri %W8<kill>, 1, 0
> %WZR<def> = SUBSWrr %W9<kill>, %W8<kill>, %NZCV<imp-def>
> Bcc 1, <BB#36>, %NZCV<imp-use>
7312B	BB#35: derived from LLVM BB %if.then.223
	    Live Ins: %X19
	    Predecessors according to CFG: BB#34
7328B		B <BB#2>
	    Successors according to CFG: BB#2
> B <BB#2>
7344B	BB#36: derived from LLVM BB %if.end.224
	    Live Ins: %X19
	    Predecessors according to CFG: BB#34
7376B		%vreg1180<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1180
7384B		%vreg1183<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg1183
7392B		%vreg1179<def> = LDRWui %vreg1180<kill>, 16; mem:LD4[%k0226] GPR32:%vreg1179 GPR64common:%vreg1180
7408B		%WZR<def> = SUBSWrr %vreg1183<kill>, %vreg1179<kill>, %NZCV<imp-def>; GPR32:%vreg1183,%vreg1179
7424B		Bcc 0, <BB#38>, %NZCV<imp-use>
	    Successors according to CFG: BB#38 BB#37
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2]
> %W8<def> = LDRWui %X8<kill>, 16; mem:LD4[%k0226]
> %WZR<def> = SUBSWrr %W9<kill>, %W8<kill>, %NZCV<imp-def>
> Bcc 0, <BB#38>, %NZCV<imp-use>
7440B	BB#37: derived from LLVM BB %if.then.229
	    Live Ins: %X19
	    Predecessors according to CFG: BB#36
7456B		%vreg1451<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg1451
7472B		%vreg1448<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1448
7488B		STRWui %vreg1451<kill>, %vreg1448<kill>, 16; mem:ST4[%k0231] GPR32:%vreg1451 GPR64common:%vreg1448
7504B		B <BB#2>
	    Successors according to CFG: BB#2
> %W8<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRWui %W8<kill>, %X9<kill>, 16; mem:ST4[%k0231]
> B <BB#2>
7520B	BB#38: derived from LLVM BB %if.end.232
	    Live Ins: %X19
	    Predecessors according to CFG: BB#36
7536B		%vreg1254<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1254
7568B		%vreg1251<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1251
7576B		%vreg1253<def> = LDRWui %vreg1254<kill>, 15; mem:LD4[%tPos233] GPR32:%vreg1253 GPR64common:%vreg1254
7584B		%vreg1250<def> = ADDXri %vreg1251<kill>, 1096, 0; GPR64sp:%vreg1250 GPR64common:%vreg1251
7600B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
7616B		%W0<def> = COPY %vreg1253<kill>; GPR32:%vreg1253
7632B		%X1<def> = COPY %vreg1250<kill>; GPR64sp:%vreg1250
7648B		BL <ga:@BZ2_indexIntoF>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use>, %W0<imp-def>
7664B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
7680B		%vreg1244<def> = COPY %W0; GPR32:%vreg1244
7696B		%vreg1199<def> = MOVi32imm 4; GPR32:%vreg1199
7712B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
7728B		STACKMAP 4, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
7744B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
7776B		STRBBui %vreg1244<kill>, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg1244
7792B		%vreg1241<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1241
7840B		%vreg1234<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1234
7848B		%vreg1240:sub_32<def,read-undef> = LDRWui %vreg1241<kill>, 15; mem:LD4[%tPos238] GPR64:%vreg1240 GPR64common:%vreg1241
7872B		%vreg1229<def> = MOVi64imm 2; GPR64:%vreg1229
7936B		%vreg1222<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1222
7940B		%vreg1233<def> = LDRXui %vreg1234<kill>, 395; mem:LD8[%ll16240] GPR64:%vreg1233 GPR64common:%vreg1234
7944B		%vreg1230<def> = MADDXrrr %vreg1240<kill>, %vreg1229<kill>, %XZR; GPR64:%vreg1230,%vreg1240,%vreg1229
8016B		%vreg1214<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1214
8020B		%vreg1221<def> = LDRWui %vreg1222<kill>, 15; mem:LD4[%tPos243] GPR32:%vreg1221 GPR64common:%vreg1222
8024B		%vreg1231<def> = ADDXrr %vreg1233<kill>, %vreg1230<kill>; GPR64common:%vreg1231 GPR64:%vreg1233,%vreg1230
8080B		%vreg1204<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1204
8088B		%vreg1213<def> = LDRXui %vreg1214<kill>, 396; mem:LD8[%ll4246] GPR64:%vreg1213 GPR64common:%vreg1214
8096B		%vreg1216:sub_32<def,read-undef> = UBFMWri %vreg1221<kill>, 1, 31; GPR64:%vreg1216 GPR32:%vreg1221
8104B		%vreg1217<def> = UBFMXri %vreg1216<kill>, 0, 31; GPR64:%vreg1217,%vreg1216
8112B		%vreg1203<def> = LDRWui %vreg1204<kill>, 15; mem:LD4[%tPos249] GPR32:%vreg1203 GPR64common:%vreg1204
8120B		%vreg1211<def> = ADDXrr %vreg1213<kill>, %vreg1217<kill>; GPR64common:%vreg1211 GPR64:%vreg1213,%vreg1217
8128B		%vreg1208<def> = LDRBBui %vreg1211<kill>, 0; mem:LD1[%arrayidx247] GPR32:%vreg1208 GPR64common:%vreg1211
8136B		%vreg1226<def> = LDRHHui %vreg1231<kill>, 0; mem:LD2[%arrayidx241] GPR32:%vreg1226 GPR64common:%vreg1231
8144B		%vreg1201<def> = ANDWrs %vreg1199<kill>, %vreg1203<kill>, 2; GPR32:%vreg1201,%vreg1199,%vreg1203
8176B		%vreg1190<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1190
8184B		%vreg1198<def> = LSRVWr %vreg1208<kill>, %vreg1201<kill>; GPR32:%vreg1198,%vreg1208,%vreg1201
8192B		%vreg1195<def> = ANDWri %vreg1198<kill>, 3; GPR32common:%vreg1195 GPR32:%vreg1198
8200B		%vreg1193<def> = ORRWrs %vreg1226<kill>, %vreg1195<kill>, 16; GPR32:%vreg1193,%vreg1226 GPR32common:%vreg1195
8208B		STRWui %vreg1193<kill>, %vreg1190<kill>, 15; mem:ST4[%tPos256] GPR32:%vreg1193 GPR64common:%vreg1190
8216B		%vreg1187<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1187
8224B		%vreg1186<def> = LDRWui %vreg1187<kill>, 6; mem:LD4[%rNToGo257] GPR32:%vreg1186 GPR64common:%vreg1187
8240B		CBNZW %vreg1186<kill>, <BB#42>; GPR32:%vreg1186
	    Successors according to CFG: BB#42 BB#39
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W0<def> = LDRWui %X8<kill>, 15; mem:LD4[%tPos233]
> %X1<def> = ADDXri %X9<kill>, 1096, 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = COPY %W0<kill>
Deleting identity copy.
> %X1<def> = COPY %X1<kill>
Deleting identity copy.
> BL <ga:@BZ2_indexIntoF>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use>, %W0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = COPY %W0
Deleting identity copy.
> %W8<def> = MOVi32imm 4
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 4, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRBBui %W0<kill>, <fi#2>, 0; mem:ST1[FixedStack2]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X10<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = LDRWui %X9<kill>, 15, %X9<imp-def>; mem:LD4[%tPos238]
> %X11<def> = MOVi64imm 2
> %X12<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X10<def> = LDRXui %X10<kill>, 395; mem:LD8[%ll16240]
> %X9<def> = MADDXrrr %X9<kill>, %X11<kill>, %XZR
> %X11<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W12<def> = LDRWui %X12<kill>, 15; mem:LD4[%tPos243]
> %X9<def> = ADDXrr %X10<kill>, %X9<kill>
> %X10<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X11<def> = LDRXui %X11<kill>, 396; mem:LD8[%ll4246]
> %W12<def> = UBFMWri %W12<kill>, 1, 31, %X12<imp-def>
> %X12<def> = UBFMXri %X12<kill>, 0, 31
> %W10<def> = LDRWui %X10<kill>, 15; mem:LD4[%tPos249]
> %X11<def> = ADDXrr %X11<kill>, %X12<kill>
> %W11<def> = LDRBBui %X11<kill>, 0; mem:LD1[%arrayidx247]
> %W9<def> = LDRHHui %X9<kill>, 0; mem:LD2[%arrayidx241]
> %W8<def> = ANDWrs %W8<kill>, %W10<kill>, 2
> %X10<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W8<def> = LSRVWr %W11<kill>, %W8<kill>
> %W8<def> = ANDWri %W8<kill>, 3
> %W8<def> = ORRWrs %W9<kill>, %W8<kill>, 16
> STRWui %W8<kill>, %X10<kill>, 15; mem:ST4[%tPos256]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W8<def> = LDRWui %X8<kill>, 6; mem:LD4[%rNToGo257]
> CBNZW %W8<kill>, <BB#42>
8256B	BB#39: derived from LLVM BB %if.then.260
	    Live Ins: %X19
	    Predecessors according to CFG: BB#38
8304B		%vreg1281<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1281
8320B		%vreg1280<def> = LDRSWui %vreg1281<kill>, 7; mem:LD4[%rTPos261] GPR64:%vreg1280 GPR64common:%vreg1281
8328B		%vreg1270<def> = ADRP <ga:@BZ2_rNums>[TF=1]; GPR64common:%vreg1270
8336B		%vreg1273<def> = MOVi64imm 4; GPR64:%vreg1273
8344B		%vreg1271<def> = ADDXri %vreg1270<kill>, <ga:@BZ2_rNums>[TF=34], 0; GPR64common:%vreg1271,%vreg1270
8352B		%vreg1274<def> = MADDXrrr %vreg1280<kill>, %vreg1273<kill>, %XZR; GPR64:%vreg1274,%vreg1280,%vreg1273
8368B		%vreg1275<def> = ADDXrr %vreg1271<kill>, %vreg1274<kill>; GPR64common:%vreg1275,%vreg1271 GPR64:%vreg1274
8384B		%vreg1269<def> = LDRWui %vreg1275<kill>, 0; mem:LD4[%arrayidx263] GPR32:%vreg1269 GPR64common:%vreg1275
8400B		%vreg1267<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1267
8416B		STRWui %vreg1269<kill>, %vreg1267<kill>, 6; mem:ST4[%rNToGo264] GPR32:%vreg1269 GPR64common:%vreg1267
8432B		%vreg1264<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1264
8448B		%vreg1263<def> = LDRWui %vreg1264, 7; mem:LD4[%rTPos265] GPR32common:%vreg1263 GPR64common:%vreg1264
8464B		%vreg1262<def> = ADDWri %vreg1263<kill>, 1, 0; GPR32common:%vreg1262,%vreg1263
8480B		STRWui %vreg1262<kill>, %vreg1264<kill>, 7; mem:ST4[%rTPos265] GPR32common:%vreg1262 GPR64common:%vreg1264
8496B		%vreg1258<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1258
8512B		%vreg1257<def> = LDRWui %vreg1258<kill>, 7; mem:LD4[%rTPos267] GPR32common:%vreg1257 GPR64common:%vreg1258
8528B		%WZR<def> = SUBSWri %vreg1257<kill>, 512, 0, %NZCV<imp-def>; GPR32common:%vreg1257
8544B		Bcc 1, <BB#41>, %NZCV<imp-use>
	    Successors according to CFG: BB#41 BB#40
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X8<def> = LDRSWui %X8<kill>, 7; mem:LD4[%rTPos261]
> %X9<def> = ADRP <ga:@BZ2_rNums>[TF=1]
> %X10<def> = MOVi64imm 4
> %X9<def> = ADDXri %X9<kill>, <ga:@BZ2_rNums>[TF=34], 0
> %X8<def> = MADDXrrr %X8<kill>, %X10<kill>, %XZR
> %X8<def> = ADDXrr %X9<kill>, %X8<kill>
> %W8<def> = LDRWui %X8<kill>, 0; mem:LD4[%arrayidx263]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRWui %W8<kill>, %X9<kill>, 6; mem:ST4[%rNToGo264]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = LDRWui %X8, 7; mem:LD4[%rTPos265]
> %W9<def> = ADDWri %W9<kill>, 1, 0
> STRWui %W9<kill>, %X8<kill>, 7; mem:ST4[%rTPos265]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W8<def> = LDRWui %X8<kill>, 7; mem:LD4[%rTPos267]
> %WZR<def> = SUBSWri %W8<kill>, 512, 0, %NZCV<imp-def>
> Bcc 1, <BB#41>, %NZCV<imp-use>
8560B	BB#40: derived from LLVM BB %if.then.270
	    Live Ins: %X19
	    Predecessors according to CFG: BB#39
8576B		%vreg1283<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1283
8592B		STRWui %WZR, %vreg1283<kill>, 7; mem:ST4[%rTPos271] GPR64common:%vreg1283
	    Successors according to CFG: BB#41
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRWui %WZR, %X8<kill>, 7; mem:ST4[%rTPos271]
8608B	BB#41: derived from LLVM BB %if.end.272
	    Live Ins: %X19
	    Predecessors according to CFG: BB#39 BB#40
8624B		B <BB#42>
	    Successors according to CFG: BB#42
> B <BB#42>
8640B	BB#42: derived from LLVM BB %if.end.273
	    Live Ins: %X19
	    Predecessors according to CFG: BB#38 BB#41
8648B		%vreg1380<def> = COPY %WZR; GPR32:%vreg1380
8688B		%vreg1390<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1390
8704B		%vreg1389<def> = LDRWui %vreg1390, 6; mem:LD4[%rNToGo274] GPR32common:%vreg1389 GPR64common:%vreg1390
8720B		%vreg1388<def> = SUBWri %vreg1389<kill>, 1, 0; GPR32common:%vreg1388,%vreg1389
8736B		STRWui %vreg1388<kill>, %vreg1390<kill>, 6; mem:ST4[%rNToGo274] GPR32common:%vreg1388 GPR64common:%vreg1390
8752B		%vreg1384<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1384
8768B		%vreg1383<def> = LDRWui %vreg1384<kill>, 6; mem:LD4[%rNToGo276] GPR32common:%vreg1383 GPR64common:%vreg1384
8816B		%vreg1377<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg1377
8824B		%vreg1379<def> = MOVi32imm 1; GPR32:%vreg1379
8832B		%WZR<def> = SUBSWri %vreg1383<kill>, 1, 0, %NZCV<imp-def>; GPR32common:%vreg1383
8840B		%vreg1381<def> = CSELWr %vreg1379<kill>, %vreg1380<kill>, 0, %NZCV<imp-use>; GPR32:%vreg1381,%vreg1379,%vreg1380
8848B		%vreg1371<def> = EORWrr %vreg1377<kill>, %vreg1381<kill>; GPR32:%vreg1371,%vreg1377,%vreg1381
8864B		STRBBui %vreg1371<kill>, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg1371
8880B		%vreg1368<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1368
8896B		%vreg1367<def> = LDRWui %vreg1368, 273; mem:LD4[%nblock_used283] GPR32common:%vreg1367 GPR64common:%vreg1368
8912B		%vreg1366<def> = ADDWri %vreg1367<kill>, 1, 0; GPR32common:%vreg1366,%vreg1367
8928B		STRWui %vreg1366<kill>, %vreg1368<kill>, 273; mem:ST4[%nblock_used283] GPR32common:%vreg1366 GPR64common:%vreg1368
8944B		%vreg1362<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32common:%vreg1362
8976B		%vreg1357<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1357
8984B		%vreg1359<def> = ADDWri %vreg1362<kill>, 4, 0; GPR32common:%vreg1359,%vreg1362
8992B		STRWui %vreg1359<kill>, %vreg1357<kill>, 4; mem:ST4[%state_out_len287] GPR32common:%vreg1359 GPR64common:%vreg1357
9008B		%vreg1354<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1354
9040B		%vreg1351<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1351
9048B		%vreg1353<def> = LDRWui %vreg1354<kill>, 15; mem:LD4[%tPos288] GPR32:%vreg1353 GPR64common:%vreg1354
9056B		%vreg1350<def> = ADDXri %vreg1351<kill>, 1096, 0; GPR64sp:%vreg1350 GPR64common:%vreg1351
9072B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
9088B		%W0<def> = COPY %vreg1353<kill>; GPR32:%vreg1353
9104B		%X1<def> = COPY %vreg1350<kill>; GPR64sp:%vreg1350
9120B		BL <ga:@BZ2_indexIntoF>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use>, %W0<imp-def>
9136B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
9152B		%vreg1347<def> = COPY %W0; GPR32:%vreg1347
9168B		%vreg1299<def> = MOVi32imm 4; GPR32:%vreg1299
9184B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
9200B		STACKMAP 5, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
9216B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
9232B		%vreg1344<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1344
9248B		STRWui %vreg1347<kill>, %vreg1344<kill>, 16; mem:ST4[%k0292] GPR32:%vreg1347 GPR64common:%vreg1344
9264B		%vreg1341<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1341
9312B		%vreg1334<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1334
9320B		%vreg1340:sub_32<def,read-undef> = LDRWui %vreg1341<kill>, 15; mem:LD4[%tPos293] GPR64:%vreg1340 GPR64common:%vreg1341
9344B		%vreg1329<def> = MOVi64imm 2; GPR64:%vreg1329
9408B		%vreg1322<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1322
9412B		%vreg1333<def> = LDRXui %vreg1334<kill>, 395; mem:LD8[%ll16295] GPR64:%vreg1333 GPR64common:%vreg1334
9416B		%vreg1330<def> = MADDXrrr %vreg1340<kill>, %vreg1329<kill>, %XZR; GPR64:%vreg1330,%vreg1340,%vreg1329
9488B		%vreg1314<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1314
9492B		%vreg1321<def> = LDRWui %vreg1322<kill>, 15; mem:LD4[%tPos298] GPR32:%vreg1321 GPR64common:%vreg1322
9496B		%vreg1331<def> = ADDXrr %vreg1333<kill>, %vreg1330<kill>; GPR64common:%vreg1331 GPR64:%vreg1333,%vreg1330
9552B		%vreg1304<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1304
9560B		%vreg1313<def> = LDRXui %vreg1314<kill>, 396; mem:LD8[%ll4301] GPR64:%vreg1313 GPR64common:%vreg1314
9568B		%vreg1316:sub_32<def,read-undef> = UBFMWri %vreg1321<kill>, 1, 31; GPR64:%vreg1316 GPR32:%vreg1321
9576B		%vreg1317<def> = UBFMXri %vreg1316<kill>, 0, 31; GPR64:%vreg1317,%vreg1316
9584B		%vreg1303<def> = LDRWui %vreg1304<kill>, 15; mem:LD4[%tPos304] GPR32:%vreg1303 GPR64common:%vreg1304
9592B		%vreg1311<def> = ADDXrr %vreg1313<kill>, %vreg1317<kill>; GPR64common:%vreg1311 GPR64:%vreg1313,%vreg1317
9600B		%vreg1308<def> = LDRBBui %vreg1311<kill>, 0; mem:LD1[%arrayidx302] GPR32:%vreg1308 GPR64common:%vreg1311
9608B		%vreg1326<def> = LDRHHui %vreg1331<kill>, 0; mem:LD2[%arrayidx296] GPR32:%vreg1326 GPR64common:%vreg1331
9616B		%vreg1301<def> = ANDWrs %vreg1299<kill>, %vreg1303<kill>, 2; GPR32:%vreg1301,%vreg1299,%vreg1303
9648B		%vreg1290<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1290
9656B		%vreg1298<def> = LSRVWr %vreg1308<kill>, %vreg1301<kill>; GPR32:%vreg1298,%vreg1308,%vreg1301
9664B		%vreg1295<def> = ANDWri %vreg1298<kill>, 3; GPR32common:%vreg1295 GPR32:%vreg1298
9672B		%vreg1293<def> = ORRWrs %vreg1326<kill>, %vreg1295<kill>, 16; GPR32:%vreg1293,%vreg1326 GPR32common:%vreg1295
9680B		STRWui %vreg1293<kill>, %vreg1290<kill>, 15; mem:ST4[%tPos311] GPR32:%vreg1293 GPR64common:%vreg1290
9688B		%vreg1287<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1287
9696B		%vreg1286<def> = LDRWui %vreg1287<kill>, 6; mem:LD4[%rNToGo312] GPR32:%vreg1286 GPR64common:%vreg1287
9712B		CBNZW %vreg1286<kill>, <BB#46>; GPR32:%vreg1286
	    Successors according to CFG: BB#46 BB#43
> %W8<def> = COPY %WZR
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W10<def> = LDRWui %X9, 6; mem:LD4[%rNToGo274]
> %W10<def> = SUBWri %W10<kill>, 1, 0
> STRWui %W10<kill>, %X9<kill>, 6; mem:ST4[%rNToGo274]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = LDRWui %X9<kill>, 6; mem:LD4[%rNToGo276]
> %W10<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2]
> %W11<def> = MOVi32imm 1
> %WZR<def> = SUBSWri %W9<kill>, 1, 0, %NZCV<imp-def>
> %W8<def> = CSELWr %W11<kill>, %W8<kill>, 0, %NZCV<imp-use>
> %W8<def> = EORWrr %W10<kill>, %W8<kill>
> STRBBui %W8<kill>, <fi#2>, 0; mem:ST1[FixedStack2]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = LDRWui %X8, 273; mem:LD4[%nblock_used283]
> %W9<def> = ADDWri %W9<kill>, 1, 0
> STRWui %W9<kill>, %X8<kill>, 273; mem:ST4[%nblock_used283]
> %W8<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W8<def> = ADDWri %W8<kill>, 4, 0
> STRWui %W8<kill>, %X9<kill>, 4; mem:ST4[%state_out_len287]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W0<def> = LDRWui %X8<kill>, 15; mem:LD4[%tPos288]
> %X1<def> = ADDXri %X9<kill>, 1096, 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = COPY %W0<kill>
Deleting identity copy.
> %X1<def> = COPY %X1<kill>
Deleting identity copy.
> BL <ga:@BZ2_indexIntoF>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use>, %W0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = COPY %W0
Deleting identity copy.
> %W8<def> = MOVi32imm 4
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 5, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRWui %W0<kill>, %X9<kill>, 16; mem:ST4[%k0292]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X10<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = LDRWui %X9<kill>, 15, %X9<imp-def>; mem:LD4[%tPos293]
> %X11<def> = MOVi64imm 2
> %X12<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X10<def> = LDRXui %X10<kill>, 395; mem:LD8[%ll16295]
> %X9<def> = MADDXrrr %X9<kill>, %X11<kill>, %XZR
> %X11<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W12<def> = LDRWui %X12<kill>, 15; mem:LD4[%tPos298]
> %X9<def> = ADDXrr %X10<kill>, %X9<kill>
> %X10<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X11<def> = LDRXui %X11<kill>, 396; mem:LD8[%ll4301]
> %W12<def> = UBFMWri %W12<kill>, 1, 31, %X12<imp-def>
> %X12<def> = UBFMXri %X12<kill>, 0, 31
> %W10<def> = LDRWui %X10<kill>, 15; mem:LD4[%tPos304]
> %X11<def> = ADDXrr %X11<kill>, %X12<kill>
> %W11<def> = LDRBBui %X11<kill>, 0; mem:LD1[%arrayidx302]
> %W9<def> = LDRHHui %X9<kill>, 0; mem:LD2[%arrayidx296]
> %W8<def> = ANDWrs %W8<kill>, %W10<kill>, 2
> %X10<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W8<def> = LSRVWr %W11<kill>, %W8<kill>
> %W8<def> = ANDWri %W8<kill>, 3
> %W8<def> = ORRWrs %W9<kill>, %W8<kill>, 16
> STRWui %W8<kill>, %X10<kill>, 15; mem:ST4[%tPos311]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W8<def> = LDRWui %X8<kill>, 6; mem:LD4[%rNToGo312]
> CBNZW %W8<kill>, <BB#46>
9728B	BB#43: derived from LLVM BB %if.then.315
	    Live Ins: %X19
	    Predecessors according to CFG: BB#42
9776B		%vreg1417<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1417
9792B		%vreg1416<def> = LDRSWui %vreg1417<kill>, 7; mem:LD4[%rTPos316] GPR64:%vreg1416 GPR64common:%vreg1417
9800B		%vreg1406<def> = ADRP <ga:@BZ2_rNums>[TF=1]; GPR64common:%vreg1406
9808B		%vreg1409<def> = MOVi64imm 4; GPR64:%vreg1409
9816B		%vreg1407<def> = ADDXri %vreg1406<kill>, <ga:@BZ2_rNums>[TF=34], 0; GPR64common:%vreg1407,%vreg1406
9824B		%vreg1410<def> = MADDXrrr %vreg1416<kill>, %vreg1409<kill>, %XZR; GPR64:%vreg1410,%vreg1416,%vreg1409
9840B		%vreg1411<def> = ADDXrr %vreg1407<kill>, %vreg1410<kill>; GPR64common:%vreg1411,%vreg1407 GPR64:%vreg1410
9856B		%vreg1405<def> = LDRWui %vreg1411<kill>, 0; mem:LD4[%arrayidx318] GPR32:%vreg1405 GPR64common:%vreg1411
9872B		%vreg1403<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1403
9888B		STRWui %vreg1405<kill>, %vreg1403<kill>, 6; mem:ST4[%rNToGo319] GPR32:%vreg1405 GPR64common:%vreg1403
9904B		%vreg1400<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1400
9920B		%vreg1399<def> = LDRWui %vreg1400, 7; mem:LD4[%rTPos320] GPR32common:%vreg1399 GPR64common:%vreg1400
9936B		%vreg1398<def> = ADDWri %vreg1399<kill>, 1, 0; GPR32common:%vreg1398,%vreg1399
9952B		STRWui %vreg1398<kill>, %vreg1400<kill>, 7; mem:ST4[%rTPos320] GPR32common:%vreg1398 GPR64common:%vreg1400
9968B		%vreg1394<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1394
9984B		%vreg1393<def> = LDRWui %vreg1394<kill>, 7; mem:LD4[%rTPos322] GPR32common:%vreg1393 GPR64common:%vreg1394
10000B		%WZR<def> = SUBSWri %vreg1393<kill>, 512, 0, %NZCV<imp-def>; GPR32common:%vreg1393
10016B		Bcc 1, <BB#45>, %NZCV<imp-use>
	    Successors according to CFG: BB#45 BB#44
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X8<def> = LDRSWui %X8<kill>, 7; mem:LD4[%rTPos316]
> %X9<def> = ADRP <ga:@BZ2_rNums>[TF=1]
> %X10<def> = MOVi64imm 4
> %X9<def> = ADDXri %X9<kill>, <ga:@BZ2_rNums>[TF=34], 0
> %X8<def> = MADDXrrr %X8<kill>, %X10<kill>, %XZR
> %X8<def> = ADDXrr %X9<kill>, %X8<kill>
> %W8<def> = LDRWui %X8<kill>, 0; mem:LD4[%arrayidx318]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRWui %W8<kill>, %X9<kill>, 6; mem:ST4[%rNToGo319]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = LDRWui %X8, 7; mem:LD4[%rTPos320]
> %W9<def> = ADDWri %W9<kill>, 1, 0
> STRWui %W9<kill>, %X8<kill>, 7; mem:ST4[%rTPos320]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W8<def> = LDRWui %X8<kill>, 7; mem:LD4[%rTPos322]
> %WZR<def> = SUBSWri %W8<kill>, 512, 0, %NZCV<imp-def>
> Bcc 1, <BB#45>, %NZCV<imp-use>
10032B	BB#44: derived from LLVM BB %if.then.325
	    Live Ins: %X19
	    Predecessors according to CFG: BB#43
10048B		%vreg1419<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1419
10064B		STRWui %WZR, %vreg1419<kill>, 7; mem:ST4[%rTPos326] GPR64common:%vreg1419
	    Successors according to CFG: BB#45
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRWui %WZR, %X8<kill>, 7; mem:ST4[%rTPos326]
10080B	BB#45: derived from LLVM BB %if.end.327
	    Live Ins: %X19
	    Predecessors according to CFG: BB#43 BB#44
10096B		B <BB#46>
	    Successors according to CFG: BB#46
> B <BB#46>
10112B	BB#46: derived from LLVM BB %if.end.328
	    Live Ins: %X19
	    Predecessors according to CFG: BB#42 BB#45
10120B		%vreg1435<def> = COPY %WZR; GPR32:%vreg1435
10160B		%vreg1445<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1445
10176B		%vreg1444<def> = LDRWui %vreg1445, 6; mem:LD4[%rNToGo329] GPR32common:%vreg1444 GPR64common:%vreg1445
10192B		%vreg1443<def> = SUBWri %vreg1444<kill>, 1, 0; GPR32common:%vreg1443,%vreg1444
10208B		STRWui %vreg1443<kill>, %vreg1445<kill>, 6; mem:ST4[%rNToGo329] GPR32common:%vreg1443 GPR64common:%vreg1445
10224B		%vreg1439<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1439
10288B		%vreg1432<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1432
10296B		%vreg1438<def> = LDRWui %vreg1439<kill>, 6; mem:LD4[%rNToGo331] GPR32common:%vreg1438 GPR64common:%vreg1439
10304B		%vreg1431<def> = LDRWui %vreg1432, 16; mem:LD4[%k0335] GPR32:%vreg1431 GPR64common:%vreg1432
10312B		%WZR<def> = SUBSWri %vreg1438<kill>, 1, 0, %NZCV<imp-def>; GPR32common:%vreg1438
10320B		%vreg1434<def> = MOVi32imm 1; GPR32:%vreg1434
10328B		%vreg1436<def> = CSELWr %vreg1434<kill>, %vreg1435<kill>, 0, %NZCV<imp-use>; GPR32:%vreg1436,%vreg1434,%vreg1435
10336B		%vreg1430<def> = EORWrr %vreg1431<kill>, %vreg1436<kill>; GPR32:%vreg1430,%vreg1431,%vreg1436
10344B		STRWui %vreg1430<kill>, %vreg1432<kill>, 16; mem:ST4[%k0335] GPR32:%vreg1430 GPR64common:%vreg1432
10352B		%vreg1425<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1425
10368B		%vreg1424<def> = LDRWui %vreg1425, 273; mem:LD4[%nblock_used337] GPR32common:%vreg1424 GPR64common:%vreg1425
10384B		%vreg1423<def> = ADDWri %vreg1424<kill>, 1, 0; GPR32common:%vreg1423,%vreg1424
10400B		STRWui %vreg1423<kill>, %vreg1425<kill>, 273; mem:ST4[%nblock_used337] GPR32common:%vreg1423 GPR64common:%vreg1425
10416B		B <BB#2>
	    Successors according to CFG: BB#2
> %W8<def> = COPY %WZR
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W10<def> = LDRWui %X9, 6; mem:LD4[%rNToGo329]
> %W10<def> = SUBWri %W10<kill>, 1, 0
> STRWui %W10<kill>, %X9<kill>, 6; mem:ST4[%rNToGo329]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X10<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = LDRWui %X9<kill>, 6; mem:LD4[%rNToGo331]
> %W11<def> = LDRWui %X10, 16; mem:LD4[%k0335]
> %WZR<def> = SUBSWri %W9<kill>, 1, 0, %NZCV<imp-def>
> %W9<def> = MOVi32imm 1
> %W8<def> = CSELWr %W9<kill>, %W8<kill>, 0, %NZCV<imp-use>
> %W8<def> = EORWrr %W11<kill>, %W8<kill>
> STRWui %W8<kill>, %X10<kill>, 16; mem:ST4[%k0335]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = LDRWui %X8, 273; mem:LD4[%nblock_used337]
> %W9<def> = ADDWri %W9<kill>, 1, 0
> STRWui %W9<kill>, %X8<kill>, 273; mem:ST4[%nblock_used337]
> B <BB#2>
10432B	BB#47: derived from LLVM BB %if.else
	    Live Ins: %X19
	    Predecessors according to CFG: BB#0
10448B		B <BB#48>
	    Successors according to CFG: BB#48
> B <BB#48>
10464B	BB#48: derived from LLVM BB %while.body.339
	    Live Ins: %X19
	    Predecessors according to CFG: BB#47 BB#72 BB#71 BB#69 BB#67 BB#65 BB#63 BB#61
10480B		B <BB#49>
	    Successors according to CFG: BB#49
> B <BB#49>
10496B	BB#49: derived from LLVM BB %while.body.341
	    Live Ins: %X19
	    Predecessors according to CFG: BB#48 BB#55
10512B		%vreg17<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg17
10528B		%vreg16<def> = LDRXui %vreg17<kill>, 0; mem:LD8[%strm342] GPR64common:%vreg16,%vreg17
10544B		%vreg14<def> = LDRWui %vreg16<kill>, 8; mem:LD4[%avail_out343] GPR32:%vreg14 GPR64common:%vreg16
10560B		CBNZW %vreg14<kill>, <BB#51>; GPR32:%vreg14
	    Successors according to CFG: BB#51 BB#50
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X8<def> = LDRXui %X8<kill>, 0; mem:LD8[%strm342]
> %W8<def> = LDRWui %X8<kill>, 8; mem:LD4[%avail_out343]
> CBNZW %W8<kill>, <BB#51>
10576B	BB#50: derived from LLVM BB %if.then.346
	    Live Ins: %X19
	    Predecessors according to CFG: BB#49
10592B		STRBBui %WZR, <fi#0>, 0; mem:ST1[FixedStack0]
10608B		B <BB#73>
	    Successors according to CFG: BB#73
> STRBBui %WZR, <fi#0>, 0; mem:ST1[FixedStack0]
> B <BB#73>
10624B	BB#51: derived from LLVM BB %if.end.347
	    Live Ins: %X19
	    Predecessors according to CFG: BB#49
10640B		%vreg21<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg21
10656B		%vreg20<def> = LDRWui %vreg21<kill>, 4; mem:LD4[%state_out_len348] GPR32:%vreg20 GPR64common:%vreg21
10672B		CBNZW %vreg20<kill>, <BB#53>; GPR32:%vreg20
	    Successors according to CFG: BB#53 BB#52
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W8<def> = LDRWui %X8<kill>, 4; mem:LD4[%state_out_len348]
> CBNZW %W8<kill>, <BB#53>
10688B	BB#52: derived from LLVM BB %if.then.351
	    Live Ins: %X19
	    Predecessors according to CFG: BB#51
10704B		B <BB#56>
	    Successors according to CFG: BB#56
> B <BB#56>
10720B	BB#53: derived from LLVM BB %if.end.352
	    Live Ins: %X19
	    Predecessors according to CFG: BB#51
10800B		%vreg97<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg97
10808B		%vreg100<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg100
10816B		%vreg96<def> = LDRXui %vreg97<kill>, 0; mem:LD8[%strm354] GPR64common:%vreg96,%vreg97
10824B		%vreg99<def> = LDRBBui %vreg100<kill>, 12; mem:LD1[%state_out_ch353] GPR32:%vreg99 GPR64common:%vreg100
10832B		%vreg94<def> = LDRXui %vreg96<kill>, 3; mem:LD8[%next_out355] GPR64common:%vreg94,%vreg96
10848B		STRBBui %vreg99<kill>, %vreg94<kill>, 0; mem:ST1[%261] GPR32:%vreg99 GPR64common:%vreg94
10896B		%vreg87<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg87
10944B		%vreg82<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg82
10952B		%vreg66<def> = ADRP <ga:@BZ2_crc32Table>[TF=1]; GPR64common:%vreg66
10960B		%vreg90<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg90
10968B		%vreg86<def> = LDRWui %vreg87<kill>, 796; mem:LD4[%calculatedBlockCRC358] GPR32:%vreg86 GPR64common:%vreg87
10976B		%vreg81<def> = LDRBBui %vreg82<kill>, 12; mem:LD1[%state_out_ch360] GPR32:%vreg81 GPR64common:%vreg82
10984B		%vreg67<def> = ADDXri %vreg66<kill>, <ga:@BZ2_crc32Table>[TF=34], 0; GPR64common:%vreg67,%vreg66
10992B		%vreg89<def> = LDRWui %vreg90<kill>, 796; mem:LD4[%calculatedBlockCRC356] GPR32:%vreg89 GPR64common:%vreg90
11000B		%vreg84<def> = UBFMWri %vreg86<kill>, 24, 31; GPR32:%vreg84,%vreg86
11008B		%vreg73:sub_32<def,read-undef> = EORWrr %vreg84<kill>, %vreg81<kill>; GPR64:%vreg73 GPR32:%vreg84,%vreg81
11024B		%vreg74<def> = UBFMXri %vreg73<kill>, 0, 31; GPR64:%vreg74,%vreg73
11032B		%vreg69<def> = MOVi64imm 4; GPR64:%vreg69
11040B		%vreg70<def> = MADDXrrr %vreg74<kill>, %vreg69<kill>, %XZR; GPR64:%vreg70,%vreg74,%vreg69
11056B		%vreg71<def> = ADDXrr %vreg67<kill>, %vreg70<kill>; GPR64common:%vreg71,%vreg67 GPR64:%vreg70
11072B		%vreg65<def> = LDRWui %vreg71<kill>, 0; mem:LD4[%arrayidx364] GPR32:%vreg65 GPR64common:%vreg71
11104B		%vreg60<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg60
11112B		%vreg63<def> = EORWrs %vreg65<kill>, %vreg89<kill>, 8; GPR32:%vreg63,%vreg65,%vreg89
11120B		STRWui %vreg63<kill>, %vreg60<kill>, 796; mem:ST4[%calculatedBlockCRC366] GPR32:%vreg63 GPR64common:%vreg60
11136B		%vreg57<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg57
11152B		%vreg56<def> = LDRWui %vreg57, 4; mem:LD4[%state_out_len367] GPR32common:%vreg56 GPR64common:%vreg57
11168B		%vreg55<def> = SUBWri %vreg56<kill>, 1, 0; GPR32common:%vreg55,%vreg56
11184B		STRWui %vreg55<kill>, %vreg57<kill>, 4; mem:ST4[%state_out_len367] GPR32common:%vreg55 GPR64common:%vreg57
11200B		%vreg51<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg51
11216B		%vreg50<def> = LDRXui %vreg51<kill>, 0; mem:LD8[%strm369] GPR64common:%vreg50,%vreg51
11232B		%vreg48<def> = LDRXui %vreg50, 3; mem:LD8[%next_out370] GPR64common:%vreg48,%vreg50
11248B		%vreg47<def> = ADDXri %vreg48<kill>, 1, 0; GPR64common:%vreg47,%vreg48
11264B		STRXui %vreg47<kill>, %vreg50<kill>, 3; mem:ST8[%next_out370] GPR64common:%vreg47,%vreg50
11280B		%vreg43<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg43
11296B		%vreg42<def> = LDRXui %vreg43<kill>, 0; mem:LD8[%strm372] GPR64common:%vreg42,%vreg43
11312B		%vreg40<def> = LDRWui %vreg42, 8; mem:LD4[%avail_out373] GPR32common:%vreg40 GPR64common:%vreg42
11328B		%vreg39<def> = SUBWri %vreg40<kill>, 1, 0; GPR32common:%vreg39,%vreg40
11344B		STRWui %vreg39<kill>, %vreg42<kill>, 8; mem:ST4[%avail_out373] GPR32common:%vreg39 GPR64common:%vreg42
11360B		%vreg35<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg35
11376B		%vreg34<def> = LDRXui %vreg35<kill>, 0; mem:LD8[%strm375] GPR64common:%vreg34,%vreg35
11392B		%vreg32<def> = LDRWui %vreg34, 9; mem:LD4[%total_out_lo32376] GPR32common:%vreg32 GPR64common:%vreg34
11408B		%vreg31<def> = ADDWri %vreg32<kill>, 1, 0; GPR32common:%vreg31,%vreg32
11424B		STRWui %vreg31<kill>, %vreg34<kill>, 9; mem:ST4[%total_out_lo32376] GPR32common:%vreg31 GPR64common:%vreg34
11440B		%vreg27<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg27
11456B		%vreg26<def> = LDRXui %vreg27<kill>, 0; mem:LD8[%strm378] GPR64common:%vreg26,%vreg27
11472B		%vreg24<def> = LDRWui %vreg26<kill>, 9; mem:LD4[%total_out_lo32379] GPR32:%vreg24 GPR64common:%vreg26
11488B		CBNZW %vreg24<kill>, <BB#55>; GPR32:%vreg24
	    Successors according to CFG: BB#55 BB#54
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X8<def> = LDRXui %X8<kill>, 0; mem:LD8[%strm354]
> %W9<def> = LDRBBui %X9<kill>, 12; mem:LD1[%state_out_ch353]
> %X8<def> = LDRXui %X8<kill>, 3; mem:LD8[%next_out355]
> STRBBui %W9<kill>, %X8<kill>, 0; mem:ST1[%261]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X10<def> = ADRP <ga:@BZ2_crc32Table>[TF=1]
> %X11<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W8<def> = LDRWui %X8<kill>, 796; mem:LD4[%calculatedBlockCRC358]
> %W9<def> = LDRBBui %X9<kill>, 12; mem:LD1[%state_out_ch360]
> %X10<def> = ADDXri %X10<kill>, <ga:@BZ2_crc32Table>[TF=34], 0
> %W11<def> = LDRWui %X11<kill>, 796; mem:LD4[%calculatedBlockCRC356]
> %W8<def> = UBFMWri %W8<kill>, 24, 31
> %W8<def> = EORWrr %W8<kill>, %W9<kill>, %X8<imp-def>
> %X8<def> = UBFMXri %X8<kill>, 0, 31
> %X9<def> = MOVi64imm 4
> %X8<def> = MADDXrrr %X8<kill>, %X9<kill>, %XZR
> %X8<def> = ADDXrr %X10<kill>, %X8<kill>
> %W8<def> = LDRWui %X8<kill>, 0; mem:LD4[%arrayidx364]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W8<def> = EORWrs %W8<kill>, %W11<kill>, 8
> STRWui %W8<kill>, %X9<kill>, 796; mem:ST4[%calculatedBlockCRC366]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = LDRWui %X8, 4; mem:LD4[%state_out_len367]
> %W9<def> = SUBWri %W9<kill>, 1, 0
> STRWui %W9<kill>, %X8<kill>, 4; mem:ST4[%state_out_len367]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X8<def> = LDRXui %X8<kill>, 0; mem:LD8[%strm369]
> %X9<def> = LDRXui %X8, 3; mem:LD8[%next_out370]
> %X9<def> = ADDXri %X9<kill>, 1, 0
> STRXui %X9<kill>, %X8<kill>, 3; mem:ST8[%next_out370]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X8<def> = LDRXui %X8<kill>, 0; mem:LD8[%strm372]
> %W9<def> = LDRWui %X8, 8; mem:LD4[%avail_out373]
> %W9<def> = SUBWri %W9<kill>, 1, 0
> STRWui %W9<kill>, %X8<kill>, 8; mem:ST4[%avail_out373]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X8<def> = LDRXui %X8<kill>, 0; mem:LD8[%strm375]
> %W9<def> = LDRWui %X8, 9; mem:LD4[%total_out_lo32376]
> %W9<def> = ADDWri %W9<kill>, 1, 0
> STRWui %W9<kill>, %X8<kill>, 9; mem:ST4[%total_out_lo32376]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X8<def> = LDRXui %X8<kill>, 0; mem:LD8[%strm378]
> %W8<def> = LDRWui %X8<kill>, 9; mem:LD4[%total_out_lo32379]
> CBNZW %W8<kill>, <BB#55>
11504B	BB#54: derived from LLVM BB %if.then.382
	    Live Ins: %X19
	    Predecessors according to CFG: BB#53
11520B		%vreg108<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg108
11536B		%vreg107<def> = LDRXui %vreg108<kill>, 0; mem:LD8[%strm383] GPR64common:%vreg107,%vreg108
11552B		%vreg105<def> = LDRWui %vreg107, 10; mem:LD4[%total_out_hi32384] GPR32common:%vreg105 GPR64common:%vreg107
11568B		%vreg104<def> = ADDWri %vreg105<kill>, 1, 0; GPR32common:%vreg104,%vreg105
11584B		STRWui %vreg104<kill>, %vreg107<kill>, 10; mem:ST4[%total_out_hi32384] GPR32common:%vreg104 GPR64common:%vreg107
	    Successors according to CFG: BB#55
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X8<def> = LDRXui %X8<kill>, 0; mem:LD8[%strm383]
> %W9<def> = LDRWui %X8, 10; mem:LD4[%total_out_hi32384]
> %W9<def> = ADDWri %W9<kill>, 1, 0
> STRWui %W9<kill>, %X8<kill>, 10; mem:ST4[%total_out_hi32384]
11600B	BB#55: derived from LLVM BB %if.end.386
	    Live Ins: %X19
	    Predecessors according to CFG: BB#53 BB#54
11616B		B <BB#49>
	    Successors according to CFG: BB#49
> B <BB#49>
11632B	BB#56: derived from LLVM BB %while.end.387
	    Live Ins: %X19
	    Predecessors according to CFG: BB#52
11680B		%vreg117<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg117
11688B		%vreg120<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg120
11696B		%vreg114<def> = MOVi64imm 64080; GPR64:%vreg114
11712B		%vreg115<def> = ADDXrr %vreg117<kill>, %vreg114<kill>; GPR64common:%vreg115 GPR64:%vreg117,%vreg114
11728B		%vreg116<def> = LDRWui %vreg115<kill>, 0; mem:LD4[%save_nblock389] GPR32common:%vreg116 GPR64common:%vreg115
11736B		%vreg119<def> = LDRWui %vreg120<kill>, 273; mem:LD4[%nblock_used388] GPR32:%vreg119 GPR64common:%vreg120
11744B		%vreg112<def> = ADDWri %vreg116<kill>, 1, 0; GPR32common:%vreg112,%vreg116
11760B		%WZR<def> = SUBSWrr %vreg119<kill>, %vreg112<kill>, %NZCV<imp-def>; GPR32:%vreg119 GPR32common:%vreg112
11776B		Bcc 1, <BB#58>, %NZCV<imp-use>
	    Successors according to CFG: BB#58 BB#57
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X10<def> = MOVi64imm 64080
> %X8<def> = ADDXrr %X8<kill>, %X10<kill>
> %W8<def> = LDRWui %X8<kill>, 0; mem:LD4[%save_nblock389]
> %W9<def> = LDRWui %X9<kill>, 273; mem:LD4[%nblock_used388]
> %W8<def> = ADDWri %W8<kill>, 1, 0
> %WZR<def> = SUBSWrr %W9<kill>, %W8<kill>, %NZCV<imp-def>
> Bcc 1, <BB#58>, %NZCV<imp-use>
11792B	BB#57: derived from LLVM BB %if.then.393
	    Live Ins: %X19
	    Predecessors according to CFG: BB#56
11808B		STRBBui %WZR, <fi#0>, 0; mem:ST1[FixedStack0]
11824B		B <BB#73>
	    Successors according to CFG: BB#73
> STRBBui %WZR, <fi#0>, 0; mem:ST1[FixedStack0]
> B <BB#73>
11840B	BB#58: derived from LLVM BB %if.end.394
	    Live Ins: %X19
	    Predecessors according to CFG: BB#56
11888B		%vreg129<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg129
11896B		%vreg132<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg132
11904B		%vreg126<def> = MOVi64imm 64080; GPR64:%vreg126
11920B		%vreg127<def> = ADDXrr %vreg129<kill>, %vreg126<kill>; GPR64common:%vreg127 GPR64:%vreg129,%vreg126
11936B		%vreg128<def> = LDRWui %vreg127<kill>, 0; mem:LD4[%save_nblock396] GPR32common:%vreg128 GPR64common:%vreg127
11944B		%vreg131<def> = LDRWui %vreg132<kill>, 273; mem:LD4[%nblock_used395] GPR32:%vreg131 GPR64common:%vreg132
11952B		%vreg124<def> = ADDWri %vreg128<kill>, 1, 0; GPR32common:%vreg124,%vreg128
11968B		%WZR<def> = SUBSWrr %vreg131<kill>, %vreg124<kill>, %NZCV<imp-def>; GPR32:%vreg131 GPR32common:%vreg124
11984B		Bcc 13, <BB#60>, %NZCV<imp-use>
	    Successors according to CFG: BB#60 BB#59
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X10<def> = MOVi64imm 64080
> %X8<def> = ADDXrr %X8<kill>, %X10<kill>
> %W8<def> = LDRWui %X8<kill>, 0; mem:LD4[%save_nblock396]
> %W9<def> = LDRWui %X9<kill>, 273; mem:LD4[%nblock_used395]
> %W8<def> = ADDWri %W8<kill>, 1, 0
> %WZR<def> = SUBSWrr %W9<kill>, %W8<kill>, %NZCV<imp-def>
> Bcc 13, <BB#60>, %NZCV<imp-use>
12000B	BB#59: derived from LLVM BB %if.then.400
	    Live Ins: %X19
	    Predecessors according to CFG: BB#58
12016B		%vreg601<def> = MOVi32imm 1; GPR32:%vreg601
12032B		STRBBui %vreg601<kill>, <fi#0>, 0; mem:ST1[FixedStack0] GPR32:%vreg601
12048B		B <BB#73>
	    Successors according to CFG: BB#73
> %W8<def> = MOVi32imm 1
> STRBBui %W8<kill>, <fi#0>, 0; mem:ST1[FixedStack0]
> B <BB#73>
12064B	BB#60: derived from LLVM BB %if.end.401
	    Live Ins: %X19
	    Predecessors according to CFG: BB#58
12096B		%vreg228<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg228
12104B		%vreg226<def> = MOVi32imm 1; GPR32:%vreg226
12112B		STRWui %vreg226<kill>, %vreg228<kill>, 4; mem:ST4[%state_out_len402] GPR32:%vreg226 GPR64common:%vreg228
12128B		%vreg225<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg225
12144B		%vreg222<def> = LDRWui %vreg225<kill>, 16; mem:LD4[%k0403] GPR32:%vreg222 GPR64common:%vreg225
12176B		%vreg220<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg220
12192B		STRBBui %vreg222<kill>, %vreg220<kill>, 12; mem:ST1[%state_out_ch405] GPR32:%vreg222 GPR64common:%vreg220
12208B		%vreg217<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg217
12240B		%vreg214<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg214
12248B		%vreg216<def> = LDRWui %vreg217<kill>, 15; mem:LD4[%tPos406] GPR32:%vreg216 GPR64common:%vreg217
12256B		%vreg213<def> = ADDXri %vreg214<kill>, 1096, 0; GPR64sp:%vreg213 GPR64common:%vreg214
12272B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
12288B		%W0<def> = COPY %vreg216<kill>; GPR32:%vreg216
12304B		%X1<def> = COPY %vreg213<kill>; GPR64sp:%vreg213
12320B		BL <ga:@BZ2_indexIntoF>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use>, %W0<imp-def>
12336B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
12352B		%vreg207<def> = COPY %W0; GPR32:%vreg207
12368B		%vreg162<def> = MOVi32imm 4; GPR32:%vreg162
12384B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
12400B		STACKMAP 6, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
12416B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
12448B		STRBBui %vreg207<kill>, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg207
12464B		%vreg204<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg204
12512B		%vreg197<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg197
12520B		%vreg203:sub_32<def,read-undef> = LDRWui %vreg204<kill>, 15; mem:LD4[%tPos411] GPR64:%vreg203 GPR64common:%vreg204
12544B		%vreg192<def> = MOVi64imm 2; GPR64:%vreg192
12608B		%vreg185<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg185
12612B		%vreg196<def> = LDRXui %vreg197<kill>, 395; mem:LD8[%ll16413] GPR64:%vreg196 GPR64common:%vreg197
12616B		%vreg193<def> = MADDXrrr %vreg203<kill>, %vreg192<kill>, %XZR; GPR64:%vreg193,%vreg203,%vreg192
12688B		%vreg177<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg177
12692B		%vreg184<def> = LDRWui %vreg185<kill>, 15; mem:LD4[%tPos416] GPR32:%vreg184 GPR64common:%vreg185
12696B		%vreg194<def> = ADDXrr %vreg196<kill>, %vreg193<kill>; GPR64common:%vreg194 GPR64:%vreg196,%vreg193
12752B		%vreg167<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg167
12760B		%vreg176<def> = LDRXui %vreg177<kill>, 396; mem:LD8[%ll4419] GPR64:%vreg176 GPR64common:%vreg177
12768B		%vreg179:sub_32<def,read-undef> = UBFMWri %vreg184<kill>, 1, 31; GPR64:%vreg179 GPR32:%vreg184
12776B		%vreg180<def> = UBFMXri %vreg179<kill>, 0, 31; GPR64:%vreg180,%vreg179
12784B		%vreg166<def> = LDRWui %vreg167<kill>, 15; mem:LD4[%tPos422] GPR32:%vreg166 GPR64common:%vreg167
12792B		%vreg174<def> = ADDXrr %vreg176<kill>, %vreg180<kill>; GPR64common:%vreg174 GPR64:%vreg176,%vreg180
12800B		%vreg171<def> = LDRBBui %vreg174<kill>, 0; mem:LD1[%arrayidx420] GPR32:%vreg171 GPR64common:%vreg174
12808B		%vreg189<def> = LDRHHui %vreg194<kill>, 0; mem:LD2[%arrayidx414] GPR32:%vreg189 GPR64common:%vreg194
12816B		%vreg164<def> = ANDWrs %vreg162<kill>, %vreg166<kill>, 2; GPR32:%vreg164,%vreg162,%vreg166
12848B		%vreg153<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg153
12856B		%vreg161<def> = LSRVWr %vreg171<kill>, %vreg164<kill>; GPR32:%vreg161,%vreg171,%vreg164
12864B		%vreg158<def> = ANDWri %vreg161<kill>, 3; GPR32common:%vreg158 GPR32:%vreg161
12872B		%vreg156<def> = ORRWrs %vreg189<kill>, %vreg158<kill>, 16; GPR32:%vreg156,%vreg189 GPR32common:%vreg158
12880B		STRWui %vreg156<kill>, %vreg153<kill>, 15; mem:ST4[%tPos429] GPR32:%vreg156 GPR64common:%vreg153
12888B		%vreg150<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg150
12896B		%vreg149<def> = LDRWui %vreg150, 273; mem:LD4[%nblock_used430] GPR32common:%vreg149 GPR64common:%vreg150
12912B		%vreg148<def> = ADDWri %vreg149<kill>, 1, 0; GPR32common:%vreg148,%vreg149
12928B		STRWui %vreg148<kill>, %vreg150<kill>, 273; mem:ST4[%nblock_used430] GPR32common:%vreg148 GPR64common:%vreg150
12976B		%vreg141<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg141
12984B		%vreg144<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg144
12992B		%vreg138<def> = MOVi64imm 64080; GPR64:%vreg138
13008B		%vreg139<def> = ADDXrr %vreg141<kill>, %vreg138<kill>; GPR64common:%vreg139 GPR64:%vreg141,%vreg138
13024B		%vreg140<def> = LDRWui %vreg139<kill>, 0; mem:LD4[%save_nblock433] GPR32common:%vreg140 GPR64common:%vreg139
13032B		%vreg143<def> = LDRWui %vreg144<kill>, 273; mem:LD4[%nblock_used432] GPR32:%vreg143 GPR64common:%vreg144
13040B		%vreg136<def> = ADDWri %vreg140<kill>, 1, 0; GPR32common:%vreg136,%vreg140
13056B		%WZR<def> = SUBSWrr %vreg143<kill>, %vreg136<kill>, %NZCV<imp-def>; GPR32:%vreg143 GPR32common:%vreg136
13072B		Bcc 1, <BB#62>, %NZCV<imp-use>
	    Successors according to CFG: BB#62 BB#61
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = MOVi32imm 1
> STRWui %W9<kill>, %X8<kill>, 4; mem:ST4[%state_out_len402]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W8<def> = LDRWui %X8<kill>, 16; mem:LD4[%k0403]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRBBui %W8<kill>, %X9<kill>, 12; mem:ST1[%state_out_ch405]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W0<def> = LDRWui %X8<kill>, 15; mem:LD4[%tPos406]
> %X1<def> = ADDXri %X9<kill>, 1096, 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = COPY %W0<kill>
Deleting identity copy.
> %X1<def> = COPY %X1<kill>
Deleting identity copy.
> BL <ga:@BZ2_indexIntoF>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use>, %W0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = COPY %W0
Deleting identity copy.
> %W8<def> = MOVi32imm 4
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 6, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRBBui %W0<kill>, <fi#2>, 0; mem:ST1[FixedStack2]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X10<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = LDRWui %X9<kill>, 15, %X9<imp-def>; mem:LD4[%tPos411]
> %X11<def> = MOVi64imm 2
> %X12<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X10<def> = LDRXui %X10<kill>, 395; mem:LD8[%ll16413]
> %X9<def> = MADDXrrr %X9<kill>, %X11<kill>, %XZR
> %X11<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W12<def> = LDRWui %X12<kill>, 15; mem:LD4[%tPos416]
> %X9<def> = ADDXrr %X10<kill>, %X9<kill>
> %X10<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X11<def> = LDRXui %X11<kill>, 396; mem:LD8[%ll4419]
> %W12<def> = UBFMWri %W12<kill>, 1, 31, %X12<imp-def>
> %X12<def> = UBFMXri %X12<kill>, 0, 31
> %W10<def> = LDRWui %X10<kill>, 15; mem:LD4[%tPos422]
> %X11<def> = ADDXrr %X11<kill>, %X12<kill>
> %W11<def> = LDRBBui %X11<kill>, 0; mem:LD1[%arrayidx420]
> %W9<def> = LDRHHui %X9<kill>, 0; mem:LD2[%arrayidx414]
> %W8<def> = ANDWrs %W8<kill>, %W10<kill>, 2
> %X10<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W8<def> = LSRVWr %W11<kill>, %W8<kill>
> %W8<def> = ANDWri %W8<kill>, 3
> %W8<def> = ORRWrs %W9<kill>, %W8<kill>, 16
> STRWui %W8<kill>, %X10<kill>, 15; mem:ST4[%tPos429]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = LDRWui %X8, 273; mem:LD4[%nblock_used430]
> %W9<def> = ADDWri %W9<kill>, 1, 0
> STRWui %W9<kill>, %X8<kill>, 273; mem:ST4[%nblock_used430]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X10<def> = MOVi64imm 64080
> %X8<def> = ADDXrr %X8<kill>, %X10<kill>
> %W8<def> = LDRWui %X8<kill>, 0; mem:LD4[%save_nblock433]
> %W9<def> = LDRWui %X9<kill>, 273; mem:LD4[%nblock_used432]
> %W8<def> = ADDWri %W8<kill>, 1, 0
> %WZR<def> = SUBSWrr %W9<kill>, %W8<kill>, %NZCV<imp-def>
> Bcc 1, <BB#62>, %NZCV<imp-use>
13088B	BB#61: derived from LLVM BB %if.then.437
	    Live Ins: %X19
	    Predecessors according to CFG: BB#60
13104B		B <BB#48>
	    Successors according to CFG: BB#48
> B <BB#48>
13120B	BB#62: derived from LLVM BB %if.end.438
	    Live Ins: %X19
	    Predecessors according to CFG: BB#60
13152B		%vreg233<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg233
13160B		%vreg236<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg236
13168B		%vreg232<def> = LDRWui %vreg233<kill>, 16; mem:LD4[%k0440] GPR32:%vreg232 GPR64common:%vreg233
13184B		%WZR<def> = SUBSWrr %vreg236<kill>, %vreg232<kill>, %NZCV<imp-def>; GPR32:%vreg236,%vreg232
13200B		Bcc 0, <BB#64>, %NZCV<imp-use>
	    Successors according to CFG: BB#64 BB#63
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2]
> %W8<def> = LDRWui %X8<kill>, 16; mem:LD4[%k0440]
> %WZR<def> = SUBSWrr %W9<kill>, %W8<kill>, %NZCV<imp-def>
> Bcc 0, <BB#64>, %NZCV<imp-use>
13216B	BB#63: derived from LLVM BB %if.then.443
	    Live Ins: %X19
	    Predecessors according to CFG: BB#62
13232B		%vreg600<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg600
13248B		%vreg597<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg597
13264B		STRWui %vreg600<kill>, %vreg597<kill>, 16; mem:ST4[%k0445] GPR32:%vreg600 GPR64common:%vreg597
13280B		B <BB#48>
	    Successors according to CFG: BB#48
> %W8<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRWui %W8<kill>, %X9<kill>, 16; mem:ST4[%k0445]
> B <BB#48>
13296B	BB#64: derived from LLVM BB %if.end.446
	    Live Ins: %X19
	    Predecessors according to CFG: BB#62
13328B		%vreg324<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg324
13336B		%vreg322<def> = MOVi32imm 2; GPR32:%vreg322
13344B		STRWui %vreg322<kill>, %vreg324<kill>, 4; mem:ST4[%state_out_len447] GPR32:%vreg322 GPR64common:%vreg324
13360B		%vreg321<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg321
13392B		%vreg318<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg318
13400B		%vreg320<def> = LDRWui %vreg321<kill>, 15; mem:LD4[%tPos448] GPR32:%vreg320 GPR64common:%vreg321
13408B		%vreg317<def> = ADDXri %vreg318<kill>, 1096, 0; GPR64sp:%vreg317 GPR64common:%vreg318
13424B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
13440B		%W0<def> = COPY %vreg320<kill>; GPR32:%vreg320
13456B		%X1<def> = COPY %vreg317<kill>; GPR64sp:%vreg317
13472B		BL <ga:@BZ2_indexIntoF>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use>, %W0<imp-def>
13488B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
13504B		%vreg311<def> = COPY %W0; GPR32:%vreg311
13520B		%vreg266<def> = MOVi32imm 4; GPR32:%vreg266
13536B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
13552B		STACKMAP 7, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
13568B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
13600B		STRBBui %vreg311<kill>, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg311
13616B		%vreg308<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg308
13664B		%vreg301<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg301
13672B		%vreg307:sub_32<def,read-undef> = LDRWui %vreg308<kill>, 15; mem:LD4[%tPos453] GPR64:%vreg307 GPR64common:%vreg308
13696B		%vreg296<def> = MOVi64imm 2; GPR64:%vreg296
13760B		%vreg289<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg289
13764B		%vreg300<def> = LDRXui %vreg301<kill>, 395; mem:LD8[%ll16455] GPR64:%vreg300 GPR64common:%vreg301
13768B		%vreg297<def> = MADDXrrr %vreg307<kill>, %vreg296<kill>, %XZR; GPR64:%vreg297,%vreg307,%vreg296
13840B		%vreg281<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg281
13844B		%vreg288<def> = LDRWui %vreg289<kill>, 15; mem:LD4[%tPos458] GPR32:%vreg288 GPR64common:%vreg289
13848B		%vreg298<def> = ADDXrr %vreg300<kill>, %vreg297<kill>; GPR64common:%vreg298 GPR64:%vreg300,%vreg297
13904B		%vreg271<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg271
13912B		%vreg280<def> = LDRXui %vreg281<kill>, 396; mem:LD8[%ll4461] GPR64:%vreg280 GPR64common:%vreg281
13920B		%vreg283:sub_32<def,read-undef> = UBFMWri %vreg288<kill>, 1, 31; GPR64:%vreg283 GPR32:%vreg288
13928B		%vreg284<def> = UBFMXri %vreg283<kill>, 0, 31; GPR64:%vreg284,%vreg283
13936B		%vreg270<def> = LDRWui %vreg271<kill>, 15; mem:LD4[%tPos464] GPR32:%vreg270 GPR64common:%vreg271
13944B		%vreg278<def> = ADDXrr %vreg280<kill>, %vreg284<kill>; GPR64common:%vreg278 GPR64:%vreg280,%vreg284
13952B		%vreg275<def> = LDRBBui %vreg278<kill>, 0; mem:LD1[%arrayidx462] GPR32:%vreg275 GPR64common:%vreg278
13960B		%vreg293<def> = LDRHHui %vreg298<kill>, 0; mem:LD2[%arrayidx456] GPR32:%vreg293 GPR64common:%vreg298
13968B		%vreg268<def> = ANDWrs %vreg266<kill>, %vreg270<kill>, 2; GPR32:%vreg268,%vreg266,%vreg270
14000B		%vreg257<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg257
14008B		%vreg265<def> = LSRVWr %vreg275<kill>, %vreg268<kill>; GPR32:%vreg265,%vreg275,%vreg268
14016B		%vreg262<def> = ANDWri %vreg265<kill>, 3; GPR32common:%vreg262 GPR32:%vreg265
14024B		%vreg260<def> = ORRWrs %vreg293<kill>, %vreg262<kill>, 16; GPR32:%vreg260,%vreg293 GPR32common:%vreg262
14032B		STRWui %vreg260<kill>, %vreg257<kill>, 15; mem:ST4[%tPos471] GPR32:%vreg260 GPR64common:%vreg257
14040B		%vreg254<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg254
14048B		%vreg253<def> = LDRWui %vreg254, 273; mem:LD4[%nblock_used472] GPR32common:%vreg253 GPR64common:%vreg254
14064B		%vreg252<def> = ADDWri %vreg253<kill>, 1, 0; GPR32common:%vreg252,%vreg253
14080B		STRWui %vreg252<kill>, %vreg254<kill>, 273; mem:ST4[%nblock_used472] GPR32common:%vreg252 GPR64common:%vreg254
14128B		%vreg245<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg245
14136B		%vreg248<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg248
14144B		%vreg242<def> = MOVi64imm 64080; GPR64:%vreg242
14160B		%vreg243<def> = ADDXrr %vreg245<kill>, %vreg242<kill>; GPR64common:%vreg243 GPR64:%vreg245,%vreg242
14176B		%vreg244<def> = LDRWui %vreg243<kill>, 0; mem:LD4[%save_nblock475] GPR32common:%vreg244 GPR64common:%vreg243
14184B		%vreg247<def> = LDRWui %vreg248<kill>, 273; mem:LD4[%nblock_used474] GPR32:%vreg247 GPR64common:%vreg248
14192B		%vreg240<def> = ADDWri %vreg244<kill>, 1, 0; GPR32common:%vreg240,%vreg244
14208B		%WZR<def> = SUBSWrr %vreg247<kill>, %vreg240<kill>, %NZCV<imp-def>; GPR32:%vreg247 GPR32common:%vreg240
14224B		Bcc 1, <BB#66>, %NZCV<imp-use>
	    Successors according to CFG: BB#66 BB#65
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = MOVi32imm 2
> STRWui %W9<kill>, %X8<kill>, 4; mem:ST4[%state_out_len447]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W0<def> = LDRWui %X8<kill>, 15; mem:LD4[%tPos448]
> %X1<def> = ADDXri %X9<kill>, 1096, 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = COPY %W0<kill>
Deleting identity copy.
> %X1<def> = COPY %X1<kill>
Deleting identity copy.
> BL <ga:@BZ2_indexIntoF>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use>, %W0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = COPY %W0
Deleting identity copy.
> %W8<def> = MOVi32imm 4
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 7, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRBBui %W0<kill>, <fi#2>, 0; mem:ST1[FixedStack2]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X10<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = LDRWui %X9<kill>, 15, %X9<imp-def>; mem:LD4[%tPos453]
> %X11<def> = MOVi64imm 2
> %X12<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X10<def> = LDRXui %X10<kill>, 395; mem:LD8[%ll16455]
> %X9<def> = MADDXrrr %X9<kill>, %X11<kill>, %XZR
> %X11<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W12<def> = LDRWui %X12<kill>, 15; mem:LD4[%tPos458]
> %X9<def> = ADDXrr %X10<kill>, %X9<kill>
> %X10<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X11<def> = LDRXui %X11<kill>, 396; mem:LD8[%ll4461]
> %W12<def> = UBFMWri %W12<kill>, 1, 31, %X12<imp-def>
> %X12<def> = UBFMXri %X12<kill>, 0, 31
> %W10<def> = LDRWui %X10<kill>, 15; mem:LD4[%tPos464]
> %X11<def> = ADDXrr %X11<kill>, %X12<kill>
> %W11<def> = LDRBBui %X11<kill>, 0; mem:LD1[%arrayidx462]
> %W9<def> = LDRHHui %X9<kill>, 0; mem:LD2[%arrayidx456]
> %W8<def> = ANDWrs %W8<kill>, %W10<kill>, 2
> %X10<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W8<def> = LSRVWr %W11<kill>, %W8<kill>
> %W8<def> = ANDWri %W8<kill>, 3
> %W8<def> = ORRWrs %W9<kill>, %W8<kill>, 16
> STRWui %W8<kill>, %X10<kill>, 15; mem:ST4[%tPos471]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = LDRWui %X8, 273; mem:LD4[%nblock_used472]
> %W9<def> = ADDWri %W9<kill>, 1, 0
> STRWui %W9<kill>, %X8<kill>, 273; mem:ST4[%nblock_used472]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X10<def> = MOVi64imm 64080
> %X8<def> = ADDXrr %X8<kill>, %X10<kill>
> %W8<def> = LDRWui %X8<kill>, 0; mem:LD4[%save_nblock475]
> %W9<def> = LDRWui %X9<kill>, 273; mem:LD4[%nblock_used474]
> %W8<def> = ADDWri %W8<kill>, 1, 0
> %WZR<def> = SUBSWrr %W9<kill>, %W8<kill>, %NZCV<imp-def>
> Bcc 1, <BB#66>, %NZCV<imp-use>
14240B	BB#65: derived from LLVM BB %if.then.479
	    Live Ins: %X19
	    Predecessors according to CFG: BB#64
14256B		B <BB#48>
	    Successors according to CFG: BB#48
> B <BB#48>
14272B	BB#66: derived from LLVM BB %if.end.480
	    Live Ins: %X19
	    Predecessors according to CFG: BB#64
14304B		%vreg329<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg329
14312B		%vreg332<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg332
14320B		%vreg328<def> = LDRWui %vreg329<kill>, 16; mem:LD4[%k0482] GPR32:%vreg328 GPR64common:%vreg329
14336B		%WZR<def> = SUBSWrr %vreg332<kill>, %vreg328<kill>, %NZCV<imp-def>; GPR32:%vreg332,%vreg328
14352B		Bcc 0, <BB#68>, %NZCV<imp-use>
	    Successors according to CFG: BB#68 BB#67
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2]
> %W8<def> = LDRWui %X8<kill>, 16; mem:LD4[%k0482]
> %WZR<def> = SUBSWrr %W9<kill>, %W8<kill>, %NZCV<imp-def>
> Bcc 0, <BB#68>, %NZCV<imp-use>
14368B	BB#67: derived from LLVM BB %if.then.485
	    Live Ins: %X19
	    Predecessors according to CFG: BB#66
14384B		%vreg594<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg594
14400B		%vreg591<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg591
14416B		STRWui %vreg594<kill>, %vreg591<kill>, 16; mem:ST4[%k0487] GPR32:%vreg594 GPR64common:%vreg591
14432B		B <BB#48>
	    Successors according to CFG: BB#48
> %W8<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRWui %W8<kill>, %X9<kill>, 16; mem:ST4[%k0487]
> B <BB#48>
14448B	BB#68: derived from LLVM BB %if.end.488
	    Live Ins: %X19
	    Predecessors according to CFG: BB#66
14480B		%vreg420<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg420
14488B		%vreg418<def> = MOVi32imm 3; GPR32:%vreg418
14496B		STRWui %vreg418<kill>, %vreg420<kill>, 4; mem:ST4[%state_out_len489] GPR32:%vreg418 GPR64common:%vreg420
14512B		%vreg417<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg417
14544B		%vreg414<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg414
14552B		%vreg416<def> = LDRWui %vreg417<kill>, 15; mem:LD4[%tPos490] GPR32:%vreg416 GPR64common:%vreg417
14560B		%vreg413<def> = ADDXri %vreg414<kill>, 1096, 0; GPR64sp:%vreg413 GPR64common:%vreg414
14576B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
14592B		%W0<def> = COPY %vreg416<kill>; GPR32:%vreg416
14608B		%X1<def> = COPY %vreg413<kill>; GPR64sp:%vreg413
14624B		BL <ga:@BZ2_indexIntoF>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use>, %W0<imp-def>
14640B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
14656B		%vreg407<def> = COPY %W0; GPR32:%vreg407
14672B		%vreg362<def> = MOVi32imm 4; GPR32:%vreg362
14688B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
14704B		STACKMAP 8, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
14720B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
14752B		STRBBui %vreg407<kill>, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg407
14768B		%vreg404<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg404
14816B		%vreg397<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg397
14824B		%vreg403:sub_32<def,read-undef> = LDRWui %vreg404<kill>, 15; mem:LD4[%tPos495] GPR64:%vreg403 GPR64common:%vreg404
14848B		%vreg392<def> = MOVi64imm 2; GPR64:%vreg392
14912B		%vreg385<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg385
14916B		%vreg396<def> = LDRXui %vreg397<kill>, 395; mem:LD8[%ll16497] GPR64:%vreg396 GPR64common:%vreg397
14920B		%vreg393<def> = MADDXrrr %vreg403<kill>, %vreg392<kill>, %XZR; GPR64:%vreg393,%vreg403,%vreg392
14992B		%vreg377<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg377
14996B		%vreg384<def> = LDRWui %vreg385<kill>, 15; mem:LD4[%tPos500] GPR32:%vreg384 GPR64common:%vreg385
15000B		%vreg394<def> = ADDXrr %vreg396<kill>, %vreg393<kill>; GPR64common:%vreg394 GPR64:%vreg396,%vreg393
15056B		%vreg367<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg367
15064B		%vreg376<def> = LDRXui %vreg377<kill>, 396; mem:LD8[%ll4503] GPR64:%vreg376 GPR64common:%vreg377
15072B		%vreg379:sub_32<def,read-undef> = UBFMWri %vreg384<kill>, 1, 31; GPR64:%vreg379 GPR32:%vreg384
15080B		%vreg380<def> = UBFMXri %vreg379<kill>, 0, 31; GPR64:%vreg380,%vreg379
15088B		%vreg366<def> = LDRWui %vreg367<kill>, 15; mem:LD4[%tPos506] GPR32:%vreg366 GPR64common:%vreg367
15096B		%vreg374<def> = ADDXrr %vreg376<kill>, %vreg380<kill>; GPR64common:%vreg374 GPR64:%vreg376,%vreg380
15104B		%vreg371<def> = LDRBBui %vreg374<kill>, 0; mem:LD1[%arrayidx504] GPR32:%vreg371 GPR64common:%vreg374
15112B		%vreg389<def> = LDRHHui %vreg394<kill>, 0; mem:LD2[%arrayidx498] GPR32:%vreg389 GPR64common:%vreg394
15120B		%vreg364<def> = ANDWrs %vreg362<kill>, %vreg366<kill>, 2; GPR32:%vreg364,%vreg362,%vreg366
15152B		%vreg353<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg353
15160B		%vreg361<def> = LSRVWr %vreg371<kill>, %vreg364<kill>; GPR32:%vreg361,%vreg371,%vreg364
15168B		%vreg358<def> = ANDWri %vreg361<kill>, 3; GPR32common:%vreg358 GPR32:%vreg361
15176B		%vreg356<def> = ORRWrs %vreg389<kill>, %vreg358<kill>, 16; GPR32:%vreg356,%vreg389 GPR32common:%vreg358
15184B		STRWui %vreg356<kill>, %vreg353<kill>, 15; mem:ST4[%tPos513] GPR32:%vreg356 GPR64common:%vreg353
15192B		%vreg350<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg350
15200B		%vreg349<def> = LDRWui %vreg350, 273; mem:LD4[%nblock_used514] GPR32common:%vreg349 GPR64common:%vreg350
15216B		%vreg348<def> = ADDWri %vreg349<kill>, 1, 0; GPR32common:%vreg348,%vreg349
15232B		STRWui %vreg348<kill>, %vreg350<kill>, 273; mem:ST4[%nblock_used514] GPR32common:%vreg348 GPR64common:%vreg350
15280B		%vreg341<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg341
15288B		%vreg344<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg344
15296B		%vreg338<def> = MOVi64imm 64080; GPR64:%vreg338
15312B		%vreg339<def> = ADDXrr %vreg341<kill>, %vreg338<kill>; GPR64common:%vreg339 GPR64:%vreg341,%vreg338
15328B		%vreg340<def> = LDRWui %vreg339<kill>, 0; mem:LD4[%save_nblock517] GPR32common:%vreg340 GPR64common:%vreg339
15336B		%vreg343<def> = LDRWui %vreg344<kill>, 273; mem:LD4[%nblock_used516] GPR32:%vreg343 GPR64common:%vreg344
15344B		%vreg336<def> = ADDWri %vreg340<kill>, 1, 0; GPR32common:%vreg336,%vreg340
15360B		%WZR<def> = SUBSWrr %vreg343<kill>, %vreg336<kill>, %NZCV<imp-def>; GPR32:%vreg343 GPR32common:%vreg336
15376B		Bcc 1, <BB#70>, %NZCV<imp-use>
	    Successors according to CFG: BB#70 BB#69
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = MOVi32imm 3
> STRWui %W9<kill>, %X8<kill>, 4; mem:ST4[%state_out_len489]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W0<def> = LDRWui %X8<kill>, 15; mem:LD4[%tPos490]
> %X1<def> = ADDXri %X9<kill>, 1096, 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = COPY %W0<kill>
Deleting identity copy.
> %X1<def> = COPY %X1<kill>
Deleting identity copy.
> BL <ga:@BZ2_indexIntoF>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use>, %W0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = COPY %W0
Deleting identity copy.
> %W8<def> = MOVi32imm 4
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 8, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRBBui %W0<kill>, <fi#2>, 0; mem:ST1[FixedStack2]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X10<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = LDRWui %X9<kill>, 15, %X9<imp-def>; mem:LD4[%tPos495]
> %X11<def> = MOVi64imm 2
> %X12<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X10<def> = LDRXui %X10<kill>, 395; mem:LD8[%ll16497]
> %X9<def> = MADDXrrr %X9<kill>, %X11<kill>, %XZR
> %X11<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W12<def> = LDRWui %X12<kill>, 15; mem:LD4[%tPos500]
> %X9<def> = ADDXrr %X10<kill>, %X9<kill>
> %X10<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X11<def> = LDRXui %X11<kill>, 396; mem:LD8[%ll4503]
> %W12<def> = UBFMWri %W12<kill>, 1, 31, %X12<imp-def>
> %X12<def> = UBFMXri %X12<kill>, 0, 31
> %W10<def> = LDRWui %X10<kill>, 15; mem:LD4[%tPos506]
> %X11<def> = ADDXrr %X11<kill>, %X12<kill>
> %W11<def> = LDRBBui %X11<kill>, 0; mem:LD1[%arrayidx504]
> %W9<def> = LDRHHui %X9<kill>, 0; mem:LD2[%arrayidx498]
> %W8<def> = ANDWrs %W8<kill>, %W10<kill>, 2
> %X10<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W8<def> = LSRVWr %W11<kill>, %W8<kill>
> %W8<def> = ANDWri %W8<kill>, 3
> %W8<def> = ORRWrs %W9<kill>, %W8<kill>, 16
> STRWui %W8<kill>, %X10<kill>, 15; mem:ST4[%tPos513]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = LDRWui %X8, 273; mem:LD4[%nblock_used514]
> %W9<def> = ADDWri %W9<kill>, 1, 0
> STRWui %W9<kill>, %X8<kill>, 273; mem:ST4[%nblock_used514]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X10<def> = MOVi64imm 64080
> %X8<def> = ADDXrr %X8<kill>, %X10<kill>
> %W8<def> = LDRWui %X8<kill>, 0; mem:LD4[%save_nblock517]
> %W9<def> = LDRWui %X9<kill>, 273; mem:LD4[%nblock_used516]
> %W8<def> = ADDWri %W8<kill>, 1, 0
> %WZR<def> = SUBSWrr %W9<kill>, %W8<kill>, %NZCV<imp-def>
> Bcc 1, <BB#70>, %NZCV<imp-use>
15392B	BB#69: derived from LLVM BB %if.then.521
	    Live Ins: %X19
	    Predecessors according to CFG: BB#68
15408B		B <BB#48>
	    Successors according to CFG: BB#48
> B <BB#48>
15424B	BB#70: derived from LLVM BB %if.end.522
	    Live Ins: %X19
	    Predecessors according to CFG: BB#68
15456B		%vreg425<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg425
15464B		%vreg428<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg428
15472B		%vreg424<def> = LDRWui %vreg425<kill>, 16; mem:LD4[%k0524] GPR32:%vreg424 GPR64common:%vreg425
15488B		%WZR<def> = SUBSWrr %vreg428<kill>, %vreg424<kill>, %NZCV<imp-def>; GPR32:%vreg428,%vreg424
15504B		Bcc 0, <BB#72>, %NZCV<imp-use>
	    Successors according to CFG: BB#72 BB#71
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2]
> %W8<def> = LDRWui %X8<kill>, 16; mem:LD4[%k0524]
> %WZR<def> = SUBSWrr %W9<kill>, %W8<kill>, %NZCV<imp-def>
> Bcc 0, <BB#72>, %NZCV<imp-use>
15520B	BB#71: derived from LLVM BB %if.then.527
	    Live Ins: %X19
	    Predecessors according to CFG: BB#70
15536B		%vreg588<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg588
15552B		%vreg585<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg585
15568B		STRWui %vreg588<kill>, %vreg585<kill>, 16; mem:ST4[%k0529] GPR32:%vreg588 GPR64common:%vreg585
15584B		B <BB#48>
	    Successors according to CFG: BB#48
> %W8<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRWui %W8<kill>, %X9<kill>, 16; mem:ST4[%k0529]
> B <BB#48>
15600B	BB#72: derived from LLVM BB %if.end.530
	    Live Ins: %X19
	    Predecessors according to CFG: BB#70
15616B		%vreg582<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg582
15648B		%vreg579<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg579
15656B		%vreg581<def> = LDRWui %vreg582<kill>, 15; mem:LD4[%tPos531] GPR32:%vreg581 GPR64common:%vreg582
15664B		%vreg578<def> = ADDXri %vreg579<kill>, 1096, 0; GPR64sp:%vreg578 GPR64common:%vreg579
15680B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
15696B		%W0<def> = COPY %vreg581<kill>; GPR32:%vreg581
15712B		%X1<def> = COPY %vreg578<kill>; GPR64sp:%vreg578
15728B		BL <ga:@BZ2_indexIntoF>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use>, %W0<imp-def>
15744B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
15760B		%vreg572<def> = COPY %W0; GPR32:%vreg572
15776B		%vreg527<def> = MOVi32imm 4; GPR32:%vreg527
15792B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
15808B		STACKMAP 9, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
15824B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
15856B		STRBBui %vreg572<kill>, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg572
15872B		%vreg569<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg569
15920B		%vreg562<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg562
15928B		%vreg568:sub_32<def,read-undef> = LDRWui %vreg569<kill>, 15; mem:LD4[%tPos536] GPR64:%vreg568 GPR64common:%vreg569
15952B		%vreg557<def> = MOVi64imm 2; GPR64:%vreg557
16016B		%vreg550<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg550
16020B		%vreg561<def> = LDRXui %vreg562<kill>, 395; mem:LD8[%ll16538] GPR64:%vreg561 GPR64common:%vreg562
16024B		%vreg558<def> = MADDXrrr %vreg568<kill>, %vreg557<kill>, %XZR; GPR64:%vreg558,%vreg568,%vreg557
16096B		%vreg542<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg542
16100B		%vreg549<def> = LDRWui %vreg550<kill>, 15; mem:LD4[%tPos541] GPR32:%vreg549 GPR64common:%vreg550
16104B		%vreg559<def> = ADDXrr %vreg561<kill>, %vreg558<kill>; GPR64common:%vreg559 GPR64:%vreg561,%vreg558
16160B		%vreg532<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg532
16168B		%vreg541<def> = LDRXui %vreg542<kill>, 396; mem:LD8[%ll4544] GPR64:%vreg541 GPR64common:%vreg542
16176B		%vreg544:sub_32<def,read-undef> = UBFMWri %vreg549<kill>, 1, 31; GPR64:%vreg544 GPR32:%vreg549
16184B		%vreg545<def> = UBFMXri %vreg544<kill>, 0, 31; GPR64:%vreg545,%vreg544
16192B		%vreg531<def> = LDRWui %vreg532<kill>, 15; mem:LD4[%tPos547] GPR32:%vreg531 GPR64common:%vreg532
16200B		%vreg539<def> = ADDXrr %vreg541<kill>, %vreg545<kill>; GPR64common:%vreg539 GPR64:%vreg541,%vreg545
16208B		%vreg536<def> = LDRBBui %vreg539<kill>, 0; mem:LD1[%arrayidx545] GPR32:%vreg536 GPR64common:%vreg539
16216B		%vreg554<def> = LDRHHui %vreg559<kill>, 0; mem:LD2[%arrayidx539] GPR32:%vreg554 GPR64common:%vreg559
16224B		%vreg529<def> = ANDWrs %vreg527<kill>, %vreg531<kill>, 2; GPR32:%vreg529,%vreg527,%vreg531
16256B		%vreg518<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg518
16264B		%vreg526<def> = LSRVWr %vreg536<kill>, %vreg529<kill>; GPR32:%vreg526,%vreg536,%vreg529
16272B		%vreg523<def> = ANDWri %vreg526<kill>, 3; GPR32common:%vreg523 GPR32:%vreg526
16280B		%vreg521<def> = ORRWrs %vreg554<kill>, %vreg523<kill>, 16; GPR32:%vreg521,%vreg554 GPR32common:%vreg523
16288B		STRWui %vreg521<kill>, %vreg518<kill>, 15; mem:ST4[%tPos554] GPR32:%vreg521 GPR64common:%vreg518
16296B		%vreg515<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg515
16304B		%vreg514<def> = LDRWui %vreg515, 273; mem:LD4[%nblock_used555] GPR32common:%vreg514 GPR64common:%vreg515
16320B		%vreg513<def> = ADDWri %vreg514<kill>, 1, 0; GPR32common:%vreg513,%vreg514
16336B		STRWui %vreg513<kill>, %vreg515<kill>, 273; mem:ST4[%nblock_used555] GPR32common:%vreg513 GPR64common:%vreg515
16352B		%vreg509<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32common:%vreg509
16384B		%vreg504<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg504
16392B		%vreg506<def> = ADDWri %vreg509<kill>, 4, 0; GPR32common:%vreg506,%vreg509
16400B		STRWui %vreg506<kill>, %vreg504<kill>, 4; mem:ST4[%state_out_len559] GPR32common:%vreg506 GPR64common:%vreg504
16416B		%vreg501<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg501
16448B		%vreg498<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg498
16456B		%vreg500<def> = LDRWui %vreg501<kill>, 15; mem:LD4[%tPos560] GPR32:%vreg500 GPR64common:%vreg501
16464B		%vreg497<def> = ADDXri %vreg498<kill>, 1096, 0; GPR64sp:%vreg497 GPR64common:%vreg498
16480B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
16496B		%W0<def> = COPY %vreg500<kill>; GPR32:%vreg500
16512B		%X1<def> = COPY %vreg497<kill>; GPR64sp:%vreg497
16528B		BL <ga:@BZ2_indexIntoF>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use>, %W0<imp-def>
16544B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
16560B		%vreg494<def> = COPY %W0; GPR32:%vreg494
16576B		%vreg446<def> = MOVi32imm 4; GPR32:%vreg446
16592B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
16608B		STACKMAP 10, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
16624B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
16640B		%vreg491<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg491
16656B		STRWui %vreg494<kill>, %vreg491<kill>, 16; mem:ST4[%k0564] GPR32:%vreg494 GPR64common:%vreg491
16672B		%vreg488<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg488
16720B		%vreg481<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg481
16728B		%vreg487:sub_32<def,read-undef> = LDRWui %vreg488<kill>, 15; mem:LD4[%tPos565] GPR64:%vreg487 GPR64common:%vreg488
16752B		%vreg476<def> = MOVi64imm 2; GPR64:%vreg476
16816B		%vreg469<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg469
16820B		%vreg480<def> = LDRXui %vreg481<kill>, 395; mem:LD8[%ll16567] GPR64:%vreg480 GPR64common:%vreg481
16824B		%vreg477<def> = MADDXrrr %vreg487<kill>, %vreg476<kill>, %XZR; GPR64:%vreg477,%vreg487,%vreg476
16896B		%vreg461<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg461
16900B		%vreg468<def> = LDRWui %vreg469<kill>, 15; mem:LD4[%tPos570] GPR32:%vreg468 GPR64common:%vreg469
16904B		%vreg478<def> = ADDXrr %vreg480<kill>, %vreg477<kill>; GPR64common:%vreg478 GPR64:%vreg480,%vreg477
16960B		%vreg451<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg451
16968B		%vreg460<def> = LDRXui %vreg461<kill>, 396; mem:LD8[%ll4573] GPR64:%vreg460 GPR64common:%vreg461
16976B		%vreg463:sub_32<def,read-undef> = UBFMWri %vreg468<kill>, 1, 31; GPR64:%vreg463 GPR32:%vreg468
16984B		%vreg464<def> = UBFMXri %vreg463<kill>, 0, 31; GPR64:%vreg464,%vreg463
16992B		%vreg450<def> = LDRWui %vreg451<kill>, 15; mem:LD4[%tPos576] GPR32:%vreg450 GPR64common:%vreg451
17000B		%vreg458<def> = ADDXrr %vreg460<kill>, %vreg464<kill>; GPR64common:%vreg458 GPR64:%vreg460,%vreg464
17008B		%vreg455<def> = LDRBBui %vreg458<kill>, 0; mem:LD1[%arrayidx574] GPR32:%vreg455 GPR64common:%vreg458
17016B		%vreg473<def> = LDRHHui %vreg478<kill>, 0; mem:LD2[%arrayidx568] GPR32:%vreg473 GPR64common:%vreg478
17024B		%vreg448<def> = ANDWrs %vreg446<kill>, %vreg450<kill>, 2; GPR32:%vreg448,%vreg446,%vreg450
17056B		%vreg437<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg437
17064B		%vreg445<def> = LSRVWr %vreg455<kill>, %vreg448<kill>; GPR32:%vreg445,%vreg455,%vreg448
17072B		%vreg442<def> = ANDWri %vreg445<kill>, 3; GPR32common:%vreg442 GPR32:%vreg445
17080B		%vreg440<def> = ORRWrs %vreg473<kill>, %vreg442<kill>, 16; GPR32:%vreg440,%vreg473 GPR32common:%vreg442
17088B		STRWui %vreg440<kill>, %vreg437<kill>, 15; mem:ST4[%tPos583] GPR32:%vreg440 GPR64common:%vreg437
17096B		%vreg434<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg434
17104B		%vreg433<def> = LDRWui %vreg434, 273; mem:LD4[%nblock_used584] GPR32common:%vreg433 GPR64common:%vreg434
17120B		%vreg432<def> = ADDWri %vreg433<kill>, 1, 0; GPR32common:%vreg432,%vreg433
17136B		STRWui %vreg432<kill>, %vreg434<kill>, 273; mem:ST4[%nblock_used584] GPR32common:%vreg432 GPR64common:%vreg434
17152B		B <BB#48>
	    Successors according to CFG: BB#48
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W0<def> = LDRWui %X8<kill>, 15; mem:LD4[%tPos531]
> %X1<def> = ADDXri %X9<kill>, 1096, 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = COPY %W0<kill>
Deleting identity copy.
> %X1<def> = COPY %X1<kill>
Deleting identity copy.
> BL <ga:@BZ2_indexIntoF>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use>, %W0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = COPY %W0
Deleting identity copy.
> %W8<def> = MOVi32imm 4
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 9, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRBBui %W0<kill>, <fi#2>, 0; mem:ST1[FixedStack2]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X10<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = LDRWui %X9<kill>, 15, %X9<imp-def>; mem:LD4[%tPos536]
> %X11<def> = MOVi64imm 2
> %X12<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X10<def> = LDRXui %X10<kill>, 395; mem:LD8[%ll16538]
> %X9<def> = MADDXrrr %X9<kill>, %X11<kill>, %XZR
> %X11<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W12<def> = LDRWui %X12<kill>, 15; mem:LD4[%tPos541]
> %X9<def> = ADDXrr %X10<kill>, %X9<kill>
> %X10<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X11<def> = LDRXui %X11<kill>, 396; mem:LD8[%ll4544]
> %W12<def> = UBFMWri %W12<kill>, 1, 31, %X12<imp-def>
> %X12<def> = UBFMXri %X12<kill>, 0, 31
> %W10<def> = LDRWui %X10<kill>, 15; mem:LD4[%tPos547]
> %X11<def> = ADDXrr %X11<kill>, %X12<kill>
> %W11<def> = LDRBBui %X11<kill>, 0; mem:LD1[%arrayidx545]
> %W9<def> = LDRHHui %X9<kill>, 0; mem:LD2[%arrayidx539]
> %W8<def> = ANDWrs %W8<kill>, %W10<kill>, 2
> %X10<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W8<def> = LSRVWr %W11<kill>, %W8<kill>
> %W8<def> = ANDWri %W8<kill>, 3
> %W8<def> = ORRWrs %W9<kill>, %W8<kill>, 16
> STRWui %W8<kill>, %X10<kill>, 15; mem:ST4[%tPos554]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = LDRWui %X8, 273; mem:LD4[%nblock_used555]
> %W9<def> = ADDWri %W9<kill>, 1, 0
> STRWui %W9<kill>, %X8<kill>, 273; mem:ST4[%nblock_used555]
> %W8<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W8<def> = ADDWri %W8<kill>, 4, 0
> STRWui %W8<kill>, %X9<kill>, 4; mem:ST4[%state_out_len559]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W0<def> = LDRWui %X8<kill>, 15; mem:LD4[%tPos560]
> %X1<def> = ADDXri %X9<kill>, 1096, 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = COPY %W0<kill>
Deleting identity copy.
> %X1<def> = COPY %X1<kill>
Deleting identity copy.
> BL <ga:@BZ2_indexIntoF>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use>, %W0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = COPY %W0
Deleting identity copy.
> %W8<def> = MOVi32imm 4
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 10, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRWui %W0<kill>, %X9<kill>, 16; mem:ST4[%k0564]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X10<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = LDRWui %X9<kill>, 15, %X9<imp-def>; mem:LD4[%tPos565]
> %X11<def> = MOVi64imm 2
> %X12<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X10<def> = LDRXui %X10<kill>, 395; mem:LD8[%ll16567]
> %X9<def> = MADDXrrr %X9<kill>, %X11<kill>, %XZR
> %X11<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W12<def> = LDRWui %X12<kill>, 15; mem:LD4[%tPos570]
> %X9<def> = ADDXrr %X10<kill>, %X9<kill>
> %X10<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X11<def> = LDRXui %X11<kill>, 396; mem:LD8[%ll4573]
> %W12<def> = UBFMWri %W12<kill>, 1, 31, %X12<imp-def>
> %X12<def> = UBFMXri %X12<kill>, 0, 31
> %W10<def> = LDRWui %X10<kill>, 15; mem:LD4[%tPos576]
> %X11<def> = ADDXrr %X11<kill>, %X12<kill>
> %W11<def> = LDRBBui %X11<kill>, 0; mem:LD1[%arrayidx574]
> %W9<def> = LDRHHui %X9<kill>, 0; mem:LD2[%arrayidx568]
> %W8<def> = ANDWrs %W8<kill>, %W10<kill>, 2
> %X10<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W8<def> = LSRVWr %W11<kill>, %W8<kill>
> %W8<def> = ANDWri %W8<kill>, 3
> %W8<def> = ORRWrs %W9<kill>, %W8<kill>, 16
> STRWui %W8<kill>, %X10<kill>, 15; mem:ST4[%tPos583]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = LDRWui %X8, 273; mem:LD4[%nblock_used584]
> %W9<def> = ADDWri %W9<kill>, 1, 0
> STRWui %W9<kill>, %X8<kill>, 273; mem:ST4[%nblock_used584]
> B <BB#48>
17168B	BB#73: derived from LLVM BB %return
	    Live Ins: %X19
	    Predecessors according to CFG: BB#59 BB#57 BB#50 BB#13 BB#11 BB#4
17184B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
17200B		%vreg1466<def> = MOVaddr <ga:@unRLE_obuf_to_output_SMALL>[TF=1], <ga:@unRLE_obuf_to_output_SMALL>[TF=34]; GPR64:%vreg1466
17216B		%X0<def> = COPY %vreg1466<kill>; GPR64:%vreg1466
17232B		%X1<def> = COPY %vreg10<kill>; GPR64:%vreg10
17248B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %SP<imp-def>
17264B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
17280B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
17296B		STACKMAP 11, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=1)
17312B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
17328B		%vreg1467<def> = LDRBBui <fi#0>, 0; mem:LD1[%retval] GPR32:%vreg1467
17360B		%W0<def> = COPY %vreg1467<kill>; GPR32:%vreg1467
17376B		RET_ReallyLR %W0<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = MOVaddr <ga:@unRLE_obuf_to_output_SMALL>[TF=1], <ga:@unRLE_obuf_to_output_SMALL>[TF=34]
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19<kill>
> BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %SP<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 11, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=1)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = LDRBBui <fi#0>, 0; mem:LD1[%retval]
> %W0<def> = COPY %W0<kill>
Deleting identity copy.
> RET_ReallyLR %W0<imp-use>
Computing live-in reg-units in ABI blocks.
0B	BB#0 W0#0 W30#0
Created 2 new intervals.
********** INTERVALS **********
W30 [0B,16r:0)[176r,176d:4)[224e,224d:2)[14272r,14272d:3)[14320e,14320d:1)  0@0B-phi 1@14320e 2@224e 3@14272r 4@176r
W0 [0B,32r:0)[144r,176r:3)[14240r,14272r:2)[14384r,14400r:1)  0@0B-phi 1@14384r 2@14240r 3@144r
%vreg0 [32r,48r:0)  0@32r
%vreg1 [48r,256r:0)  0@48r
%vreg3 [304r,320r:0)  0@304r
%vreg5 [288r,304r:0)  0@288r
%vreg6 [272r,288r:0)  0@272r
%vreg7 [64r,80r:0)  0@64r
%vreg8 [80r,96r:0)  0@80r
%vreg9 [96r,144r:0)  0@96r
%vreg10 [112r,160r:0)  0@112r
%vreg11 [16r,14256r:0)  0@16r
%vreg14 [9280r,9296r:0)  0@9280r
%vreg16 [9232r,9248r:0)  0@9232r
%vreg17 [9248r,9264r:0)  0@9248r
%vreg18 [9264r,9280r:0)  0@9264r
%vreg19 [9216r,9248r:0)  0@9216r
%vreg21 [9184r,9200r:0)  0@9184r
%vreg24 [9152r,9168r:0)  0@9152r
%vreg26 [9136r,9152r:0)  0@9136r
%vreg27 [9120r,9136r:0)  0@9120r
%vreg30 [9088r,9104r:0)  0@9088r
%vreg32 [9072r,9088r:0)  0@9072r
%vreg33 [9056r,9072r:0)  0@9056r
%vreg36 [9024r,9040r:0)  0@9024r
%vreg37 [9008r,9024r:0)  0@9008r
%vreg40 [8976r,8992r:0)  0@8976r
%vreg41 [8960r,8976r:0)  0@8960r
%vreg44 [8928r,8944r:0)  0@8928r
%vreg45 [8912r,8928r:0)  0@8912r
%vreg48 [8880r,8896r:0)  0@8880r
%vreg49 [8864r,8880r:0)  0@8864r
%vreg52 [8832r,8848r:0)  0@8832r
%vreg53 [8816r,8832r:0)  0@8816r
%vreg56 [8784r,8800r:0)  0@8784r
%vreg57 [8768r,8784r:0)  0@8768r
%vreg60 [8736r,8752r:0)  0@8736r
%vreg61 [8720r,8736r:0)  0@8720r
%vreg63 [9328r,9344r:0)  0@9328r
%vreg65 [9424r,9440r:0)  0@9424r
%vreg67 [9504r,9520r:0)  0@9504r
%vreg70 [10000r,10016r:0)  0@10000r
%vreg71 [9984r,10000r:0)  0@9984r
%vreg74 [9952r,9968r:0)  0@9952r
%vreg75 [9936r,9952r:0)  0@9936r
%vreg78 [9904r,9920r:0)  0@9904r
%vreg79 [9888r,9904r:0)  0@9888r
%vreg83 [9856r,9872r:0)  0@9856r
%vreg85 [9840r,9856r:0)  0@9840r
%vreg86 [9600r,9616r:0)  0@9600r
%vreg87 [9616r,9824r:0)  0@9616r
%vreg89 [9792r,9808r:0)  0@9792r
%vreg90 [9808r,9824r:0)  0@9808r
%vreg91 [9824r,9840r:0)  0@9824r
%vreg93 [9760r,9776r:0)  0@9760r
%vreg94 [9776r,9808r:0)  0@9776r
%vreg97 [9744r,9760r:0)  0@9744r
%vreg100 [9728r,9744r:0)  0@9728r
%vreg102 [9712r,9744r:0)  0@9712r
%vreg103 [9696r,9712r:0)  0@9696r
%vreg104 [9680r,9856r:0)  0@9680r
%vreg107 [9648r,9664r:0)  0@9648r
%vreg108 [9632r,9664r:0)  0@9632r
%vreg110 [10096r,10112r:0)  0@10096r
%vreg113 [10560r,10576r:0)  0@10560r
%vreg114 [10544r,10560r:0)  0@10544r
%vreg117 [10512r,10528r:0)  0@10512r
%vreg118 [10496r,10512r:0)  0@10496r
%vreg122 [10464r,10480r:0)  0@10464r
%vreg124 [10448r,10464r:0)  0@10448r
%vreg125 [10208r,10224r:0)  0@10208r
%vreg126 [10224r,10432r:0)  0@10224r
%vreg128 [10400r,10416r:0)  0@10400r
%vreg129 [10416r,10432r:0)  0@10416r
%vreg130 [10432r,10448r:0)  0@10432r
%vreg132 [10368r,10384r:0)  0@10368r
%vreg133 [10384r,10416r:0)  0@10384r
%vreg136 [10352r,10368r:0)  0@10352r
%vreg139 [10336r,10352r:0)  0@10336r
%vreg141 [10320r,10352r:0)  0@10320r
%vreg142 [10304r,10320r:0)  0@10304r
%vreg143 [10288r,10464r:0)  0@10288r
%vreg146 [10256r,10272r:0)  0@10256r
%vreg147 [10240r,10272r:0)  0@10240r
%vreg150 [10624r,10640r:0)  0@10624r
%vreg151 [10608r,10640r:0)  0@10608r
%vreg154 [10768r,10784r:0)  0@10768r
%vreg155 [10752r,10784r:0)  0@10752r
%vreg158 [11232r,11248r:0)  0@11232r
%vreg161 [11216r,11248r:0)  0@11216r
%vreg164 [11184r,11200r:0)  0@11184r
%vreg165 [11168r,11184r:0)  0@11168r
%vreg168 [11136r,11152r:0)  0@11136r
%vreg169 [11120r,11136r:0)  0@11120r
%vreg172 [11088r,11104r:0)  0@11088r
%vreg174 [11072r,11088r:0)  0@11072r
%vreg175 [11056r,11072r:0)  0@11056r
%vreg178 [11024r,11040r:0)  0@11024r
%vreg181 [10976r,10992r:0)  0@10976r
%vreg182 [10992r,11008r:0)  0@10992r
%vreg183 [11008r,11024r:0)  0@11008r
%vreg184 [10960r,11008r:0)  0@10960r
%vreg188 [10928r,10944r:0)  0@10928r
%vreg189 [10944r,10992r:0)  0@10944r
%vreg192 [10896r,10912r:0)  0@10896r
%vreg193 [10880r,10896r:0)  0@10880r
%vreg196 [11376r,11392r:0)  0@11376r
%vreg197 [11360r,11392r:0)  0@11360r
%vreg200 [11808r,11824r:0)  0@11808r
%vreg201 [11792r,11824r:0)  0@11792r
%vreg204 [11760r,11776r:0)  0@11760r
%vreg205 [11744r,11760r:0)  0@11744r
%vreg208 [11712r,11728r:0)  0@11712r
%vreg209 [11696r,11712r:0)  0@11696r
%vreg212 [11664r,11680r:0)  0@11664r
%vreg214 [11648r,11664r:0)  0@11648r
%vreg215 [11632r,11648r:0)  0@11632r
%vreg218 [11600r,11616r:0)  0@11600r
%vreg221 [11552r,11568r:0)  0@11552r
%vreg222 [11568r,11584r:0)  0@11568r
%vreg223 [11584r,11600r:0)  0@11584r
%vreg224 [11536r,11584r:0)  0@11536r
%vreg228 [11504r,11520r:0)  0@11504r
%vreg229 [11520r,11568r:0)  0@11520r
%vreg230 [11472r,11488r:0)  0@11472r
%vreg233 [11920r,11936r:0)  0@11920r
%vreg236 [11904r,11936r:0)  0@11904r
%vreg239 [12384r,12400r:0)  0@12384r
%vreg240 [12368r,12400r:0)  0@12368r
%vreg243 [12336r,12352r:0)  0@12336r
%vreg244 [12320r,12336r:0)  0@12320r
%vreg247 [12288r,12304r:0)  0@12288r
%vreg248 [12272r,12288r:0)  0@12272r
%vreg251 [12240r,12256r:0)  0@12240r
%vreg253 [12224r,12240r:0)  0@12224r
%vreg254 [12208r,12224r:0)  0@12208r
%vreg257 [12176r,12192r:0)  0@12176r
%vreg260 [12128r,12144r:0)  0@12128r
%vreg261 [12144r,12160r:0)  0@12144r
%vreg262 [12160r,12176r:0)  0@12160r
%vreg263 [12112r,12160r:0)  0@12112r
%vreg267 [12080r,12096r:0)  0@12080r
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%vreg969 [6928r,6944r:0)  0@6928r
%vreg970 [6944r,6960r:0)  0@6944r
%vreg971 [6960r,6976r:0)  0@6960r
%vreg976 [6912r,6944r:0)  0@6912r
%vreg977 [6896r,6912r:0)  0@6896r
%vreg979 [7168r,7184r:0)  0@7168r
%vreg982 [7968r,7984r:0)  0@7968r
%vreg983 [7952r,7968r:0)  0@7952r
%vreg987 [7920r,7936r:0)  0@7920r
%vreg988 [7904r,7920r:0)  0@7904r
%vreg989 [7888r,7936r:0)  0@7888r
%vreg992 [7856r,7872r:0)  0@7856r
%vreg994 [7840r,7872r:0)  0@7840r
%vreg996 [7824r,7840r:0)  0@7824r
%vreg998 [7808r,7824r:0)  0@7808r
%vreg1000 [7792r,7808r:0)  0@7792r
%vreg1001 [7776r,7792r:0)  0@7776r
%vreg1004 [7744r,7760r:0)  0@7744r
%vreg1006 [7728r,7760r:0)  0@7728r
%vreg1009 [7680r,7696r:0)  0@7680r
%vreg1010 [7696r,7712r:0)  0@7696r
%vreg1011 [7712r,7728r:0)  0@7712r
%vreg1013 [7664r,7712r:0)  0@7664r
%vreg1014 [7648r,7664r:0)  0@7648r
%vreg1019 [7616r,7632r:0)  0@7616r
%vreg1020 [7632r,7696r:0)  0@7632r
%vreg1021 [7600r,7616r:0)  0@7600r
%vreg1024 [7568r,7584r:0)  0@7568r
%vreg1026 [7552r,7584r:0)  0@7552r
%vreg1029 [7536r,7552r:0)  0@7536r
%vreg1033 [7504r,7520r:0)  0@7504r
%vreg1034 [7488r,7504r:0)  0@7488r
%vreg1035 [7472r,7520r:0)  0@7472r
%vreg1038 [7440r,7456r:0)  0@7440r
%vreg1041 [7424r,7440r:0)  0@7424r
%vreg1044 [7408r,7424r:0)  0@7408r
%vreg1046 [7248r,7392r:0)  0@7248r
%vreg1047 [7264r,7392r:0)  0@7264r
%vreg1048 [7392r,7424r:0)  0@7392r
%vreg1050 [7360r,7376r:0)  0@7360r
%vreg1051 [7344r,7360r:0)  0@7344r
%vreg1055 [7312r,7328r:0)  0@7312r
%vreg1056 [7296r,7312r:0)  0@7296r
%vreg1057 [7280r,7328r:0)  0@7280r
%vreg1060 [8256r,8272r:0)  0@8256r
%vreg1061 [8240r,8256r:0)  0@8240r
%vreg1065 [8208r,8224r:0)  0@8208r
%vreg1066 [8192r,8208r:0)  0@8192r
%vreg1067 [8176r,8224r:0)  0@8176r
%vreg1070 [8144r,8160r:0)  0@8144r
%vreg1072 [8128r,8160r:0)  0@8128r
%vreg1073 [8016r,8032r:0)  0@8016r
%vreg1074 [8032r,8112r:0)  0@8032r
%vreg1076 [8080r,8096r:0)  0@8080r
%vreg1077 [8096r,8112r:0)  0@8096r
%vreg1078 [8112r,8128r:0)  0@8112r
%vreg1083 [8064r,8096r:0)  0@8064r
%vreg1084 [8048r,8064r:0)  0@8048r
%vreg1086 [8320r,8336r:0)  0@8320r
%vreg1090 [8656r,8672r:0)  0@8656r
%vreg1091 [8640r,8656r:0)  0@8640r
%vreg1092 [8624r,8672r:0)  0@8624r
%vreg1097 [8592r,8608r:0)  0@8592r
%vreg1098 [8576r,8592r:0)  0@8576r
%vreg1099 [8560r,8608r:0)  0@8560r
%vreg1101 [8400r,8544r:0)  0@8400r
%vreg1102 [8416r,8544r:0)  0@8416r
%vreg1103 [8544r,8592r:0)  0@8544r
%vreg1105 [8512r,8528r:0)  0@8512r
%vreg1106 [8496r,8512r:0)  0@8496r
%vreg1110 [8464r,8480r:0)  0@8464r
%vreg1111 [8448r,8464r:0)  0@8448r
%vreg1112 [8432r,8480r:0)  0@8432r
%vreg1115 [6416r,6432r:0)  0@6416r
%vreg1118 [6400r,6432r:0)  0@6400r
%vreg1121 [4944r,4960r:0)  0@4944r
%vreg1124 [4928r,4960r:0)  0@4928r
%vreg1127 [3472r,3488r:0)  0@3472r
%vreg1130 [3456r,3488r:0)  0@3456r
%vreg1131 [1920r,1936r:0)  0@1920r
%vreg1132 [14368r,14368d:0)  0@14368r
%vreg1133 [14224r,14240r:0)  0@14224r
%vreg1134 [14352r,14384r:0)  0@14352r
RegMasks: 176r 14272r
********** MACHINEINSTRS **********
# Machine code for function unRLE_obuf_to_output_FAST: Post SSA
Frame Objects:
  fi#0: size=1, align=1, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=1, align=1, at location [SP]
  fi#3: size=4, align=4, at location [SP]
  fi#4: size=1, align=1, at location [SP]
  fi#5: size=4, align=4, at location [SP]
  fi#6: size=4, align=4, at location [SP]
  fi#7: size=4, align=4, at location [SP]
  fi#8: size=8, align=8, at location [SP]
  fi#9: size=4, align=4, at location [SP]
  fi#10: size=8, align=8, at location [SP]
  fi#11: size=4, align=4, at location [SP]
  fi#12: size=4, align=4, at location [SP]
  fi#13: size=4, align=4, at location [SP]
  fi#14: size=4, align=4, at location [SP]
Function Live Ins: %X0 in %vreg0, %LR in %vreg11

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %LR
16B		%vreg11<def> = COPY %LR; GPR64:%vreg11
32B		%vreg0<def> = COPY %X0; GPR64:%vreg0
48B		%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
64B		%vreg7<def> = ADRP <ga:@unRLE_obuf_to_output_FAST>[TF=1]; GPR64common:%vreg7
80B		%vreg8<def> = ADDXri %vreg7, <ga:@unRLE_obuf_to_output_FAST>[TF=34], 0; GPR64sp:%vreg8 GPR64common:%vreg7
96B		%vreg9<def> = COPY %vreg8; GPR64all:%vreg9 GPR64sp:%vreg8
112B		%vreg10<def> = COPY %vreg11; GPR64all:%vreg10 GPR64:%vreg11
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		%X0<def> = COPY %vreg9; GPR64all:%vreg9
160B		%X1<def> = COPY %vreg10; GPR64all:%vreg10
176B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
224B		STACKMAP 0, 0, 0, <fi#12>, 0, 0, <fi#3>, 0, 0, <fi#7>, 0, 0, <fi#6>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#9>, 0, 0, <fi#8>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, %vreg1, 0, <fi#1>, 0, 0, <fi#13>, 0, 0, <fi#14>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack12](align=4) LD8[FixedStack3](align=4) LD8[FixedStack7](align=4) LD8[FixedStack6](align=4) LD8[FixedStack4](align=1) LD8[FixedStack5](align=4) LD8[FixedStack9](align=4) LD8[FixedStack8] LD8[FixedStack11](align=4) LD8[FixedStack10] LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1] LD8[FixedStack13](align=4) LD8[FixedStack14](align=4) GPR64:%vreg1
240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
256B		STRXui %vreg1, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg1
272B		%vreg6<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg6
288B		%vreg5<def> = LDRBBui %vreg6, 20; mem:LD1[%blockRandomised] GPR32:%vreg5 GPR64common:%vreg6
304B		%vreg3<def> = UBFMWri %vreg5, 0, 7; GPR32:%vreg3,%vreg5
320B		CBZW %vreg3, <BB#47>; GPR32:%vreg3
	    Successors according to CFG: BB#47 BB#1

336B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
352B		B <BB#2>
	    Successors according to CFG: BB#2

368B	BB#2: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#1 BB#46 BB#37 BB#35 BB#29 BB#27 BB#21 BB#19
384B		B <BB#3>
	    Successors according to CFG: BB#3

400B	BB#3: derived from LLVM BB %while.body.2
	    Predecessors according to CFG: BB#2 BB#9
416B		%vreg435<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg435
432B		%vreg434<def> = LDRXui %vreg435, 0; mem:LD8[%strm] GPR64common:%vreg434,%vreg435
448B		%vreg432<def> = LDRWui %vreg434, 8; mem:LD4[%avail_out] GPR32:%vreg432 GPR64common:%vreg434
464B		CBNZW %vreg432, <BB#5>; GPR32:%vreg432
	    Successors according to CFG: BB#5 BB#4

480B	BB#4: derived from LLVM BB %if.then.3
	    Predecessors according to CFG: BB#3
496B		STRBBui %WZR, <fi#0>, 0; mem:ST1[FixedStack0]
512B		B <BB#80>
	    Successors according to CFG: BB#80

528B	BB#5: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#3
544B		%vreg439<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg439
560B		%vreg438<def> = LDRWui %vreg439, 4; mem:LD4[%state_out_len] GPR32:%vreg438 GPR64common:%vreg439
576B		CBNZW %vreg438, <BB#7>; GPR32:%vreg438
	    Successors according to CFG: BB#7 BB#6

592B	BB#6: derived from LLVM BB %if.then.5
	    Predecessors according to CFG: BB#5
608B		B <BB#10>
	    Successors according to CFG: BB#10

624B	BB#7: derived from LLVM BB %if.end.6
	    Predecessors according to CFG: BB#5
640B		%vreg484<def> = ADRP <ga:@BZ2_crc32Table>[TF=1]; GPR64common:%vreg484
656B		%vreg485<def> = ADDXri %vreg484, <ga:@BZ2_crc32Table>[TF=34], 0; GPR64common:%vreg485,%vreg484
672B		%vreg518<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg518
688B		%vreg517<def> = LDRBBui %vreg518, 12; mem:LD1[%state_out_ch] GPR32:%vreg517 GPR64common:%vreg518
704B		%vreg515<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg515
720B		%vreg514<def> = LDRXui %vreg515, 0; mem:LD8[%strm7] GPR64common:%vreg514,%vreg515
736B		%vreg512<def> = LDRXui %vreg514, 3; mem:LD8[%next_out] GPR64common:%vreg512,%vreg514
752B		STRBBui %vreg517, %vreg512, 0; mem:ST1[%11] GPR32:%vreg517 GPR64common:%vreg512
768B		%vreg508<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg508
784B		%vreg507<def> = LDRWui %vreg508, 796; mem:LD4[%calculatedBlockCRC] GPR32:%vreg507 GPR64common:%vreg508
800B		%vreg505<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg505
816B		%vreg504<def> = LDRWui %vreg505, 796; mem:LD4[%calculatedBlockCRC8] GPR32:%vreg504 GPR64common:%vreg505
832B		%vreg502<def> = UBFMWri %vreg504, 24, 31; GPR32:%vreg502,%vreg504
848B		%vreg500<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg500
864B		%vreg499<def> = LDRBBui %vreg500, 12; mem:LD1[%state_out_ch9] GPR32:%vreg499 GPR64common:%vreg500
880B		%vreg495<def> = EORWrr %vreg502, %vreg499; GPR32:%vreg495,%vreg502,%vreg499
896B		%vreg491<def> = SUBREG_TO_REG 0, %vreg495, 15; GPR64:%vreg491 GPR32:%vreg495
912B		%vreg492<def> = UBFMXri %vreg491, 0, 31; GPR64:%vreg492,%vreg491
928B		%vreg487<def> = MOVi64imm 4; GPR64:%vreg487
944B		%vreg488<def> = MADDXrrr %vreg492, %vreg487, %XZR; GPR64:%vreg488,%vreg492,%vreg487
960B		%vreg489<def> = ADDXrr %vreg485, %vreg488; GPR64common:%vreg489,%vreg485 GPR64:%vreg488
976B		%vreg483<def> = LDRWui %vreg489, 0; mem:LD4[%arrayidx] GPR32:%vreg483 GPR64common:%vreg489
992B		%vreg481<def> = EORWrs %vreg483, %vreg507, 8; GPR32:%vreg481,%vreg483,%vreg507
1008B		%vreg478<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg478
1024B		STRWui %vreg481, %vreg478, 796; mem:ST4[%calculatedBlockCRC11] GPR32:%vreg481 GPR64common:%vreg478
1040B		%vreg475<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg475
1056B		%vreg474<def> = LDRWui %vreg475, 4; mem:LD4[%state_out_len12] GPR32common:%vreg474 GPR64common:%vreg475
1072B		%vreg473<def> = SUBWri %vreg474, 1, 0; GPR32common:%vreg473,%vreg474
1088B		STRWui %vreg473, %vreg475, 4; mem:ST4[%state_out_len12] GPR32common:%vreg473 GPR64common:%vreg475
1104B		%vreg469<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg469
1120B		%vreg468<def> = LDRXui %vreg469, 0; mem:LD8[%strm13] GPR64common:%vreg468,%vreg469
1136B		%vreg466<def> = LDRXui %vreg468, 3; mem:LD8[%next_out14] GPR64common:%vreg466,%vreg468
1152B		%vreg465<def> = ADDXri %vreg466, 1, 0; GPR64common:%vreg465,%vreg466
1168B		STRXui %vreg465, %vreg468, 3; mem:ST8[%next_out14] GPR64common:%vreg465,%vreg468
1184B		%vreg461<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg461
1200B		%vreg460<def> = LDRXui %vreg461, 0; mem:LD8[%strm15] GPR64common:%vreg460,%vreg461
1216B		%vreg458<def> = LDRWui %vreg460, 8; mem:LD4[%avail_out16] GPR32common:%vreg458 GPR64common:%vreg460
1232B		%vreg457<def> = SUBWri %vreg458, 1, 0; GPR32common:%vreg457,%vreg458
1248B		STRWui %vreg457, %vreg460, 8; mem:ST4[%avail_out16] GPR32common:%vreg457 GPR64common:%vreg460
1264B		%vreg453<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg453
1280B		%vreg452<def> = LDRXui %vreg453, 0; mem:LD8[%strm18] GPR64common:%vreg452,%vreg453
1296B		%vreg450<def> = LDRWui %vreg452, 9; mem:LD4[%total_out_lo32] GPR32common:%vreg450 GPR64common:%vreg452
1312B		%vreg449<def> = ADDWri %vreg450, 1, 0; GPR32common:%vreg449,%vreg450
1328B		STRWui %vreg449, %vreg452, 9; mem:ST4[%total_out_lo32] GPR32common:%vreg449 GPR64common:%vreg452
1344B		%vreg445<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg445
1360B		%vreg444<def> = LDRXui %vreg445, 0; mem:LD8[%strm19] GPR64common:%vreg444,%vreg445
1376B		%vreg442<def> = LDRWui %vreg444, 9; mem:LD4[%total_out_lo3220] GPR32:%vreg442 GPR64common:%vreg444
1392B		CBNZW %vreg442, <BB#9>; GPR32:%vreg442
	    Successors according to CFG: BB#9 BB#8

1408B	BB#8: derived from LLVM BB %if.then.23
	    Predecessors according to CFG: BB#7
1424B		%vreg526<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg526
1440B		%vreg525<def> = LDRXui %vreg526, 0; mem:LD8[%strm24] GPR64common:%vreg525,%vreg526
1456B		%vreg523<def> = LDRWui %vreg525, 10; mem:LD4[%total_out_hi32] GPR32common:%vreg523 GPR64common:%vreg525
1472B		%vreg522<def> = ADDWri %vreg523, 1, 0; GPR32common:%vreg522,%vreg523
1488B		STRWui %vreg522, %vreg525, 10; mem:ST4[%total_out_hi32] GPR32common:%vreg522 GPR64common:%vreg525
	    Successors according to CFG: BB#9

1504B	BB#9: derived from LLVM BB %if.end.26
	    Predecessors according to CFG: BB#7 BB#8
1520B		B <BB#3>
	    Successors according to CFG: BB#3

1536B	BB#10: derived from LLVM BB %while.end
	    Predecessors according to CFG: BB#6
1552B		%vreg538<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg538
1568B		%vreg537<def> = LDRWui %vreg538, 273; mem:LD4[%nblock_used] GPR32:%vreg537 GPR64common:%vreg538
1584B		%vreg535<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg535
1600B		%vreg532<def> = MOVi64imm 64080; GPR64:%vreg532
1616B		%vreg533<def> = ADDXrr %vreg535, %vreg532; GPR64common:%vreg533 GPR64:%vreg535,%vreg532
1632B		%vreg534<def> = LDRWui %vreg533, 0; mem:LD4[%save_nblock] GPR32common:%vreg534 GPR64common:%vreg533
1648B		%vreg530<def> = ADDWri %vreg534, 1, 0; GPR32common:%vreg530,%vreg534
1664B		%WZR<def> = SUBSWrr %vreg537, %vreg530, %NZCV<imp-def>; GPR32:%vreg537 GPR32common:%vreg530
1680B		Bcc 1, <BB#12>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#12 BB#11

1696B	BB#11: derived from LLVM BB %if.then.29
	    Predecessors according to CFG: BB#10
1712B		STRBBui %WZR, <fi#0>, 0; mem:ST1[FixedStack0]
1728B		B <BB#80>
	    Successors according to CFG: BB#80

1744B	BB#12: derived from LLVM BB %if.end.30
	    Predecessors according to CFG: BB#10
1760B		%vreg550<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg550
1776B		%vreg549<def> = LDRWui %vreg550, 273; mem:LD4[%nblock_used31] GPR32:%vreg549 GPR64common:%vreg550
1792B		%vreg547<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg547
1808B		%vreg544<def> = MOVi64imm 64080; GPR64:%vreg544
1824B		%vreg545<def> = ADDXrr %vreg547, %vreg544; GPR64common:%vreg545 GPR64:%vreg547,%vreg544
1840B		%vreg546<def> = LDRWui %vreg545, 0; mem:LD4[%save_nblock32] GPR32common:%vreg546 GPR64common:%vreg545
1856B		%vreg542<def> = ADDWri %vreg546, 1, 0; GPR32common:%vreg542,%vreg546
1872B		%WZR<def> = SUBSWrr %vreg549, %vreg542, %NZCV<imp-def>; GPR32:%vreg549 GPR32common:%vreg542
1888B		Bcc 13, <BB#14>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#14 BB#13

1904B	BB#13: derived from LLVM BB %if.then.36
	    Predecessors according to CFG: BB#12
1920B		%vreg1131<def> = MOVi32imm 1; GPR32:%vreg1131
1936B		STRBBui %vreg1131, <fi#0>, 0; mem:ST1[FixedStack0] GPR32:%vreg1131
1952B		B <BB#80>
	    Successors according to CFG: BB#80

1968B	BB#14: derived from LLVM BB %if.end.37
	    Predecessors according to CFG: BB#12
1984B		%vreg597<def> = MOVi32imm 1; GPR32:%vreg597
2000B		%vreg599<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg599
2016B		STRWui %vreg597, %vreg599, 4; mem:ST4[%state_out_len38] GPR32:%vreg597 GPR64common:%vreg599
2032B		%vreg596<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg596
2048B		%vreg595<def> = LDRWui %vreg596, 16; mem:LD4[%k0] GPR32:%vreg595 GPR64common:%vreg596
2064B		%vreg593<def> = COPY %vreg595; GPR32:%vreg593,%vreg595
2080B		%vreg591<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg591
2096B		STRBBui %vreg593, %vreg591, 12; mem:ST1[%state_out_ch40] GPR32:%vreg593 GPR64common:%vreg591
2112B		%vreg588<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg588
2128B		%vreg586<def> = LDRWui %vreg588, 15; mem:LD4[%tPos] GPR32:%vreg586 GPR64common:%vreg588
2144B		%vreg587<def> = SUBREG_TO_REG 0, %vreg586, 15; GPR64:%vreg587 GPR32:%vreg586
2160B		%vreg581<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg581
2176B		%vreg580<def> = LDRXui %vreg581, 394; mem:LD8[%tt] GPR64:%vreg580 GPR64common:%vreg581
2192B		%vreg576<def> = MOVi64imm 4; GPR64:%vreg576
2208B		%vreg577<def> = MADDXrrr %vreg587, %vreg576, %XZR; GPR64:%vreg577,%vreg587,%vreg576
2224B		%vreg578<def> = ADDXrr %vreg580, %vreg577; GPR64common:%vreg578 GPR64:%vreg580,%vreg577
2240B		%vreg573<def> = LDRWui %vreg578, 0; mem:LD4[%arrayidx42] GPR32:%vreg573 GPR64common:%vreg578
2256B		%vreg571<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg571
2272B		STRWui %vreg573, %vreg571, 15; mem:ST4[%tPos43] GPR32:%vreg573 GPR64common:%vreg571
2288B		%vreg568<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg568
2304B		%vreg567<def> = LDRWui %vreg568, 15; mem:LD4[%tPos44] GPR32:%vreg567 GPR64common:%vreg568
2320B		%vreg565<def> = ANDWri %vreg567, 7; GPR32sp:%vreg565 GPR32:%vreg567
2336B		%vreg563<def> = COPY %vreg565; GPR32:%vreg563 GPR32sp:%vreg565
2352B		STRBBui %vreg563, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg563
2368B		%vreg560<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg560
2384B		%vreg559<def> = LDRWui %vreg560, 15; mem:LD4[%tPos46] GPR32:%vreg559 GPR64common:%vreg560
2400B		%vreg558<def> = UBFMWri %vreg559, 8, 31; GPR32:%vreg558,%vreg559
2416B		STRWui %vreg558, %vreg560, 15; mem:ST4[%tPos46] GPR32:%vreg558 GPR64common:%vreg560
2432B		%vreg554<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg554
2448B		%vreg553<def> = LDRWui %vreg554, 6; mem:LD4[%rNToGo] GPR32:%vreg553 GPR64common:%vreg554
2464B		CBNZW %vreg553, <BB#18>; GPR32:%vreg553
	    Successors according to CFG: BB#18 BB#15

2480B	BB#15: derived from LLVM BB %if.then.50
	    Predecessors according to CFG: BB#14
2496B		%vreg615<def> = ADRP <ga:@BZ2_rNums>[TF=1]; GPR64common:%vreg615
2512B		%vreg616<def> = ADDXri %vreg615, <ga:@BZ2_rNums>[TF=34], 0; GPR64common:%vreg616,%vreg615
2528B		%vreg626<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg626
2544B		%vreg625<def> = LDRSWui %vreg626, 7; mem:LD4[%rTPos] GPR64:%vreg625 GPR64common:%vreg626
2560B		%vreg618<def> = MOVi64imm 4; GPR64:%vreg618
2576B		%vreg619<def> = MADDXrrr %vreg625, %vreg618, %XZR; GPR64:%vreg619,%vreg625,%vreg618
2592B		%vreg620<def> = ADDXrr %vreg616, %vreg619; GPR64common:%vreg620,%vreg616 GPR64:%vreg619
2608B		%vreg614<def> = LDRWui %vreg620, 0; mem:LD4[%arrayidx52] GPR32:%vreg614 GPR64common:%vreg620
2624B		%vreg612<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg612
2640B		STRWui %vreg614, %vreg612, 6; mem:ST4[%rNToGo53] GPR32:%vreg614 GPR64common:%vreg612
2656B		%vreg609<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg609
2672B		%vreg608<def> = LDRWui %vreg609, 7; mem:LD4[%rTPos54] GPR32common:%vreg608 GPR64common:%vreg609
2688B		%vreg607<def> = ADDWri %vreg608, 1, 0; GPR32common:%vreg607,%vreg608
2704B		STRWui %vreg607, %vreg609, 7; mem:ST4[%rTPos54] GPR32common:%vreg607 GPR64common:%vreg609
2720B		%vreg603<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg603
2736B		%vreg602<def> = LDRWui %vreg603, 7; mem:LD4[%rTPos56] GPR32common:%vreg602 GPR64common:%vreg603
2752B		%WZR<def> = SUBSWri %vreg602, 512, 0, %NZCV<imp-def>; GPR32common:%vreg602
2768B		Bcc 1, <BB#17>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#17 BB#16

2784B	BB#16: derived from LLVM BB %if.then.59
	    Predecessors according to CFG: BB#15
2800B		%vreg628<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg628
2816B		STRWui %WZR, %vreg628, 7; mem:ST4[%rTPos60] GPR64common:%vreg628
	    Successors according to CFG: BB#17

2832B	BB#17: derived from LLVM BB %if.end.61
	    Predecessors according to CFG: BB#15 BB#16
2848B		B <BB#18>
	    Successors according to CFG: BB#18

2864B	BB#18: derived from LLVM BB %if.end.62
	    Predecessors according to CFG: BB#14 BB#17
2880B		%vreg657<def> = MOVi32imm 1; GPR32:%vreg657
2896B		%vreg658<def> = COPY %WZR; GPR32:%vreg658
2912B		%vreg668<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg668
2928B		%vreg667<def> = LDRWui %vreg668, 6; mem:LD4[%rNToGo63] GPR32common:%vreg667 GPR64common:%vreg668
2944B		%vreg666<def> = SUBWri %vreg667, 1, 0; GPR32common:%vreg666,%vreg667
2960B		STRWui %vreg666, %vreg668, 6; mem:ST4[%rNToGo63] GPR32common:%vreg666 GPR64common:%vreg668
2976B		%vreg662<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg662
2992B		%vreg661<def> = LDRWui %vreg662, 6; mem:LD4[%rNToGo65] GPR32common:%vreg661 GPR64common:%vreg662
3008B		%WZR<def> = SUBSWri %vreg661, 1, 0, %NZCV<imp-def>; GPR32common:%vreg661
3024B		%vreg659<def> = CSELWr %vreg657, %vreg658, 0, %NZCV<imp-use,kill>; GPR32:%vreg659,%vreg657,%vreg658
3040B		%vreg655<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg655
3056B		%vreg652<def> = EORWrr %vreg655, %vreg659; GPR32:%vreg652,%vreg655,%vreg659
3072B		%vreg649<def> = COPY %vreg652; GPR32:%vreg649,%vreg652
3088B		STRBBui %vreg649, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg649
3104B		%vreg646<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg646
3120B		%vreg645<def> = LDRWui %vreg646, 273; mem:LD4[%nblock_used71] GPR32common:%vreg645 GPR64common:%vreg646
3136B		%vreg644<def> = ADDWri %vreg645, 1, 0; GPR32common:%vreg644,%vreg645
3152B		STRWui %vreg644, %vreg646, 273; mem:ST4[%nblock_used71] GPR32common:%vreg644 GPR64common:%vreg646
3168B		%vreg640<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg640
3184B		%vreg639<def> = LDRWui %vreg640, 273; mem:LD4[%nblock_used73] GPR32:%vreg639 GPR64common:%vreg640
3200B		%vreg637<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg637
3216B		%vreg634<def> = MOVi64imm 64080; GPR64:%vreg634
3232B		%vreg635<def> = ADDXrr %vreg637, %vreg634; GPR64common:%vreg635 GPR64:%vreg637,%vreg634
3248B		%vreg636<def> = LDRWui %vreg635, 0; mem:LD4[%save_nblock74] GPR32common:%vreg636 GPR64common:%vreg635
3264B		%vreg632<def> = ADDWri %vreg636, 1, 0; GPR32common:%vreg632,%vreg636
3280B		%WZR<def> = SUBSWrr %vreg639, %vreg632, %NZCV<imp-def>; GPR32:%vreg639 GPR32common:%vreg632
3296B		Bcc 1, <BB#20>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#20 BB#19

3312B	BB#19: derived from LLVM BB %if.then.78
	    Predecessors according to CFG: BB#18
3328B		B <BB#2>
	    Successors according to CFG: BB#2

3344B	BB#20: derived from LLVM BB %if.end.79
	    Predecessors according to CFG: BB#18
3360B		%vreg676<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg676
3376B		%vreg673<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg673
3392B		%vreg672<def> = LDRWui %vreg673, 16; mem:LD4[%k081] GPR32:%vreg672 GPR64common:%vreg673
3408B		%WZR<def> = SUBSWrr %vreg676, %vreg672, %NZCV<imp-def>; GPR32:%vreg676,%vreg672
3424B		Bcc 0, <BB#22>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#22 BB#21

3440B	BB#21: derived from LLVM BB %if.then.84
	    Predecessors according to CFG: BB#20
3456B		%vreg1130<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg1130
3472B		%vreg1127<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1127
3488B		STRWui %vreg1130, %vreg1127, 16; mem:ST4[%k086] GPR32:%vreg1130 GPR64common:%vreg1127
3504B		B <BB#2>
	    Successors according to CFG: BB#2

3520B	BB#22: derived from LLVM BB %if.end.87
	    Predecessors according to CFG: BB#20
3536B		%vreg715<def> = MOVi32imm 2; GPR32:%vreg715
3552B		%vreg717<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg717
3568B		STRWui %vreg715, %vreg717, 4; mem:ST4[%state_out_len88] GPR32:%vreg715 GPR64common:%vreg717
3584B		%vreg714<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg714
3600B		%vreg712<def> = LDRWui %vreg714, 15; mem:LD4[%tPos89] GPR32:%vreg712 GPR64common:%vreg714
3616B		%vreg713<def> = SUBREG_TO_REG 0, %vreg712, 15; GPR64:%vreg713 GPR32:%vreg712
3632B		%vreg707<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg707
3648B		%vreg706<def> = LDRXui %vreg707, 394; mem:LD8[%tt91] GPR64:%vreg706 GPR64common:%vreg707
3664B		%vreg702<def> = MOVi64imm 4; GPR64:%vreg702
3680B		%vreg703<def> = MADDXrrr %vreg713, %vreg702, %XZR; GPR64:%vreg703,%vreg713,%vreg702
3696B		%vreg704<def> = ADDXrr %vreg706, %vreg703; GPR64common:%vreg704 GPR64:%vreg706,%vreg703
3712B		%vreg699<def> = LDRWui %vreg704, 0; mem:LD4[%arrayidx92] GPR32:%vreg699 GPR64common:%vreg704
3728B		%vreg697<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg697
3744B		STRWui %vreg699, %vreg697, 15; mem:ST4[%tPos93] GPR32:%vreg699 GPR64common:%vreg697
3760B		%vreg694<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg694
3776B		%vreg693<def> = LDRWui %vreg694, 15; mem:LD4[%tPos94] GPR32:%vreg693 GPR64common:%vreg694
3792B		%vreg691<def> = ANDWri %vreg693, 7; GPR32sp:%vreg691 GPR32:%vreg693
3808B		%vreg689<def> = COPY %vreg691; GPR32:%vreg689 GPR32sp:%vreg691
3824B		STRBBui %vreg689, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg689
3840B		%vreg686<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg686
3856B		%vreg685<def> = LDRWui %vreg686, 15; mem:LD4[%tPos97] GPR32:%vreg685 GPR64common:%vreg686
3872B		%vreg684<def> = UBFMWri %vreg685, 8, 31; GPR32:%vreg684,%vreg685
3888B		STRWui %vreg684, %vreg686, 15; mem:ST4[%tPos97] GPR32:%vreg684 GPR64common:%vreg686
3904B		%vreg680<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg680
3920B		%vreg679<def> = LDRWui %vreg680, 6; mem:LD4[%rNToGo99] GPR32:%vreg679 GPR64common:%vreg680
3936B		CBNZW %vreg679, <BB#26>; GPR32:%vreg679
	    Successors according to CFG: BB#26 BB#23

3952B	BB#23: derived from LLVM BB %if.then.102
	    Predecessors according to CFG: BB#22
3968B		%vreg733<def> = ADRP <ga:@BZ2_rNums>[TF=1]; GPR64common:%vreg733
3984B		%vreg734<def> = ADDXri %vreg733, <ga:@BZ2_rNums>[TF=34], 0; GPR64common:%vreg734,%vreg733
4000B		%vreg744<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg744
4016B		%vreg743<def> = LDRSWui %vreg744, 7; mem:LD4[%rTPos103] GPR64:%vreg743 GPR64common:%vreg744
4032B		%vreg736<def> = MOVi64imm 4; GPR64:%vreg736
4048B		%vreg737<def> = MADDXrrr %vreg743, %vreg736, %XZR; GPR64:%vreg737,%vreg743,%vreg736
4064B		%vreg738<def> = ADDXrr %vreg734, %vreg737; GPR64common:%vreg738,%vreg734 GPR64:%vreg737
4080B		%vreg732<def> = LDRWui %vreg738, 0; mem:LD4[%arrayidx105] GPR32:%vreg732 GPR64common:%vreg738
4096B		%vreg730<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg730
4112B		STRWui %vreg732, %vreg730, 6; mem:ST4[%rNToGo106] GPR32:%vreg732 GPR64common:%vreg730
4128B		%vreg727<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg727
4144B		%vreg726<def> = LDRWui %vreg727, 7; mem:LD4[%rTPos107] GPR32common:%vreg726 GPR64common:%vreg727
4160B		%vreg725<def> = ADDWri %vreg726, 1, 0; GPR32common:%vreg725,%vreg726
4176B		STRWui %vreg725, %vreg727, 7; mem:ST4[%rTPos107] GPR32common:%vreg725 GPR64common:%vreg727
4192B		%vreg721<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg721
4208B		%vreg720<def> = LDRWui %vreg721, 7; mem:LD4[%rTPos109] GPR32common:%vreg720 GPR64common:%vreg721
4224B		%WZR<def> = SUBSWri %vreg720, 512, 0, %NZCV<imp-def>; GPR32common:%vreg720
4240B		Bcc 1, <BB#25>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#25 BB#24

4256B	BB#24: derived from LLVM BB %if.then.112
	    Predecessors according to CFG: BB#23
4272B		%vreg746<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg746
4288B		STRWui %WZR, %vreg746, 7; mem:ST4[%rTPos113] GPR64common:%vreg746
	    Successors according to CFG: BB#25

4304B	BB#25: derived from LLVM BB %if.end.114
	    Predecessors according to CFG: BB#23 BB#24
4320B		B <BB#26>
	    Successors according to CFG: BB#26

4336B	BB#26: derived from LLVM BB %if.end.115
	    Predecessors according to CFG: BB#22 BB#25
4352B		%vreg775<def> = MOVi32imm 1; GPR32:%vreg775
4368B		%vreg776<def> = COPY %WZR; GPR32:%vreg776
4384B		%vreg786<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg786
4400B		%vreg785<def> = LDRWui %vreg786, 6; mem:LD4[%rNToGo116] GPR32common:%vreg785 GPR64common:%vreg786
4416B		%vreg784<def> = SUBWri %vreg785, 1, 0; GPR32common:%vreg784,%vreg785
4432B		STRWui %vreg784, %vreg786, 6; mem:ST4[%rNToGo116] GPR32common:%vreg784 GPR64common:%vreg786
4448B		%vreg780<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg780
4464B		%vreg779<def> = LDRWui %vreg780, 6; mem:LD4[%rNToGo118] GPR32common:%vreg779 GPR64common:%vreg780
4480B		%WZR<def> = SUBSWri %vreg779, 1, 0, %NZCV<imp-def>; GPR32common:%vreg779
4496B		%vreg777<def> = CSELWr %vreg775, %vreg776, 0, %NZCV<imp-use,kill>; GPR32:%vreg777,%vreg775,%vreg776
4512B		%vreg773<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg773
4528B		%vreg770<def> = EORWrr %vreg773, %vreg777; GPR32:%vreg770,%vreg773,%vreg777
4544B		%vreg767<def> = COPY %vreg770; GPR32:%vreg767,%vreg770
4560B		STRBBui %vreg767, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg767
4576B		%vreg764<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg764
4592B		%vreg763<def> = LDRWui %vreg764, 273; mem:LD4[%nblock_used125] GPR32common:%vreg763 GPR64common:%vreg764
4608B		%vreg762<def> = ADDWri %vreg763, 1, 0; GPR32common:%vreg762,%vreg763
4624B		STRWui %vreg762, %vreg764, 273; mem:ST4[%nblock_used125] GPR32common:%vreg762 GPR64common:%vreg764
4640B		%vreg758<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg758
4656B		%vreg757<def> = LDRWui %vreg758, 273; mem:LD4[%nblock_used127] GPR32:%vreg757 GPR64common:%vreg758
4672B		%vreg755<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg755
4688B		%vreg752<def> = MOVi64imm 64080; GPR64:%vreg752
4704B		%vreg753<def> = ADDXrr %vreg755, %vreg752; GPR64common:%vreg753 GPR64:%vreg755,%vreg752
4720B		%vreg754<def> = LDRWui %vreg753, 0; mem:LD4[%save_nblock128] GPR32common:%vreg754 GPR64common:%vreg753
4736B		%vreg750<def> = ADDWri %vreg754, 1, 0; GPR32common:%vreg750,%vreg754
4752B		%WZR<def> = SUBSWrr %vreg757, %vreg750, %NZCV<imp-def>; GPR32:%vreg757 GPR32common:%vreg750
4768B		Bcc 1, <BB#28>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#28 BB#27

4784B	BB#27: derived from LLVM BB %if.then.132
	    Predecessors according to CFG: BB#26
4800B		B <BB#2>
	    Successors according to CFG: BB#2

4816B	BB#28: derived from LLVM BB %if.end.133
	    Predecessors according to CFG: BB#26
4832B		%vreg794<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg794
4848B		%vreg791<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg791
4864B		%vreg790<def> = LDRWui %vreg791, 16; mem:LD4[%k0135] GPR32:%vreg790 GPR64common:%vreg791
4880B		%WZR<def> = SUBSWrr %vreg794, %vreg790, %NZCV<imp-def>; GPR32:%vreg794,%vreg790
4896B		Bcc 0, <BB#30>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#30 BB#29

4912B	BB#29: derived from LLVM BB %if.then.138
	    Predecessors according to CFG: BB#28
4928B		%vreg1124<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg1124
4944B		%vreg1121<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1121
4960B		STRWui %vreg1124, %vreg1121, 16; mem:ST4[%k0140] GPR32:%vreg1124 GPR64common:%vreg1121
4976B		B <BB#2>
	    Successors according to CFG: BB#2

4992B	BB#30: derived from LLVM BB %if.end.141
	    Predecessors according to CFG: BB#28
5008B		%vreg833<def> = MOVi32imm 3; GPR32:%vreg833
5024B		%vreg835<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg835
5040B		STRWui %vreg833, %vreg835, 4; mem:ST4[%state_out_len142] GPR32:%vreg833 GPR64common:%vreg835
5056B		%vreg832<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg832
5072B		%vreg830<def> = LDRWui %vreg832, 15; mem:LD4[%tPos143] GPR32:%vreg830 GPR64common:%vreg832
5088B		%vreg831<def> = SUBREG_TO_REG 0, %vreg830, 15; GPR64:%vreg831 GPR32:%vreg830
5104B		%vreg825<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg825
5120B		%vreg824<def> = LDRXui %vreg825, 394; mem:LD8[%tt145] GPR64:%vreg824 GPR64common:%vreg825
5136B		%vreg820<def> = MOVi64imm 4; GPR64:%vreg820
5152B		%vreg821<def> = MADDXrrr %vreg831, %vreg820, %XZR; GPR64:%vreg821,%vreg831,%vreg820
5168B		%vreg822<def> = ADDXrr %vreg824, %vreg821; GPR64common:%vreg822 GPR64:%vreg824,%vreg821
5184B		%vreg817<def> = LDRWui %vreg822, 0; mem:LD4[%arrayidx146] GPR32:%vreg817 GPR64common:%vreg822
5200B		%vreg815<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg815
5216B		STRWui %vreg817, %vreg815, 15; mem:ST4[%tPos147] GPR32:%vreg817 GPR64common:%vreg815
5232B		%vreg812<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg812
5248B		%vreg811<def> = LDRWui %vreg812, 15; mem:LD4[%tPos148] GPR32:%vreg811 GPR64common:%vreg812
5264B		%vreg809<def> = ANDWri %vreg811, 7; GPR32sp:%vreg809 GPR32:%vreg811
5280B		%vreg807<def> = COPY %vreg809; GPR32:%vreg807 GPR32sp:%vreg809
5296B		STRBBui %vreg807, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg807
5312B		%vreg804<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg804
5328B		%vreg803<def> = LDRWui %vreg804, 15; mem:LD4[%tPos151] GPR32:%vreg803 GPR64common:%vreg804
5344B		%vreg802<def> = UBFMWri %vreg803, 8, 31; GPR32:%vreg802,%vreg803
5360B		STRWui %vreg802, %vreg804, 15; mem:ST4[%tPos151] GPR32:%vreg802 GPR64common:%vreg804
5376B		%vreg798<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg798
5392B		%vreg797<def> = LDRWui %vreg798, 6; mem:LD4[%rNToGo153] GPR32:%vreg797 GPR64common:%vreg798
5408B		CBNZW %vreg797, <BB#34>; GPR32:%vreg797
	    Successors according to CFG: BB#34 BB#31

5424B	BB#31: derived from LLVM BB %if.then.156
	    Predecessors according to CFG: BB#30
5440B		%vreg851<def> = ADRP <ga:@BZ2_rNums>[TF=1]; GPR64common:%vreg851
5456B		%vreg852<def> = ADDXri %vreg851, <ga:@BZ2_rNums>[TF=34], 0; GPR64common:%vreg852,%vreg851
5472B		%vreg862<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg862
5488B		%vreg861<def> = LDRSWui %vreg862, 7; mem:LD4[%rTPos157] GPR64:%vreg861 GPR64common:%vreg862
5504B		%vreg854<def> = MOVi64imm 4; GPR64:%vreg854
5520B		%vreg855<def> = MADDXrrr %vreg861, %vreg854, %XZR; GPR64:%vreg855,%vreg861,%vreg854
5536B		%vreg856<def> = ADDXrr %vreg852, %vreg855; GPR64common:%vreg856,%vreg852 GPR64:%vreg855
5552B		%vreg850<def> = LDRWui %vreg856, 0; mem:LD4[%arrayidx159] GPR32:%vreg850 GPR64common:%vreg856
5568B		%vreg848<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg848
5584B		STRWui %vreg850, %vreg848, 6; mem:ST4[%rNToGo160] GPR32:%vreg850 GPR64common:%vreg848
5600B		%vreg845<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg845
5616B		%vreg844<def> = LDRWui %vreg845, 7; mem:LD4[%rTPos161] GPR32common:%vreg844 GPR64common:%vreg845
5632B		%vreg843<def> = ADDWri %vreg844, 1, 0; GPR32common:%vreg843,%vreg844
5648B		STRWui %vreg843, %vreg845, 7; mem:ST4[%rTPos161] GPR32common:%vreg843 GPR64common:%vreg845
5664B		%vreg839<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg839
5680B		%vreg838<def> = LDRWui %vreg839, 7; mem:LD4[%rTPos163] GPR32common:%vreg838 GPR64common:%vreg839
5696B		%WZR<def> = SUBSWri %vreg838, 512, 0, %NZCV<imp-def>; GPR32common:%vreg838
5712B		Bcc 1, <BB#33>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#33 BB#32

5728B	BB#32: derived from LLVM BB %if.then.166
	    Predecessors according to CFG: BB#31
5744B		%vreg864<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg864
5760B		STRWui %WZR, %vreg864, 7; mem:ST4[%rTPos167] GPR64common:%vreg864
	    Successors according to CFG: BB#33

5776B	BB#33: derived from LLVM BB %if.end.168
	    Predecessors according to CFG: BB#31 BB#32
5792B		B <BB#34>
	    Successors according to CFG: BB#34

5808B	BB#34: derived from LLVM BB %if.end.169
	    Predecessors according to CFG: BB#30 BB#33
5824B		%vreg893<def> = MOVi32imm 1; GPR32:%vreg893
5840B		%vreg894<def> = COPY %WZR; GPR32:%vreg894
5856B		%vreg904<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg904
5872B		%vreg903<def> = LDRWui %vreg904, 6; mem:LD4[%rNToGo170] GPR32common:%vreg903 GPR64common:%vreg904
5888B		%vreg902<def> = SUBWri %vreg903, 1, 0; GPR32common:%vreg902,%vreg903
5904B		STRWui %vreg902, %vreg904, 6; mem:ST4[%rNToGo170] GPR32common:%vreg902 GPR64common:%vreg904
5920B		%vreg898<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg898
5936B		%vreg897<def> = LDRWui %vreg898, 6; mem:LD4[%rNToGo172] GPR32common:%vreg897 GPR64common:%vreg898
5952B		%WZR<def> = SUBSWri %vreg897, 1, 0, %NZCV<imp-def>; GPR32common:%vreg897
5968B		%vreg895<def> = CSELWr %vreg893, %vreg894, 0, %NZCV<imp-use,kill>; GPR32:%vreg895,%vreg893,%vreg894
5984B		%vreg891<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg891
6000B		%vreg888<def> = EORWrr %vreg891, %vreg895; GPR32:%vreg888,%vreg891,%vreg895
6016B		%vreg885<def> = COPY %vreg888; GPR32:%vreg885,%vreg888
6032B		STRBBui %vreg885, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg885
6048B		%vreg882<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg882
6064B		%vreg881<def> = LDRWui %vreg882, 273; mem:LD4[%nblock_used179] GPR32common:%vreg881 GPR64common:%vreg882
6080B		%vreg880<def> = ADDWri %vreg881, 1, 0; GPR32common:%vreg880,%vreg881
6096B		STRWui %vreg880, %vreg882, 273; mem:ST4[%nblock_used179] GPR32common:%vreg880 GPR64common:%vreg882
6112B		%vreg876<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg876
6128B		%vreg875<def> = LDRWui %vreg876, 273; mem:LD4[%nblock_used181] GPR32:%vreg875 GPR64common:%vreg876
6144B		%vreg873<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg873
6160B		%vreg870<def> = MOVi64imm 64080; GPR64:%vreg870
6176B		%vreg871<def> = ADDXrr %vreg873, %vreg870; GPR64common:%vreg871 GPR64:%vreg873,%vreg870
6192B		%vreg872<def> = LDRWui %vreg871, 0; mem:LD4[%save_nblock182] GPR32common:%vreg872 GPR64common:%vreg871
6208B		%vreg868<def> = ADDWri %vreg872, 1, 0; GPR32common:%vreg868,%vreg872
6224B		%WZR<def> = SUBSWrr %vreg875, %vreg868, %NZCV<imp-def>; GPR32:%vreg875 GPR32common:%vreg868
6240B		Bcc 1, <BB#36>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#36 BB#35

6256B	BB#35: derived from LLVM BB %if.then.186
	    Predecessors according to CFG: BB#34
6272B		B <BB#2>
	    Successors according to CFG: BB#2

6288B	BB#36: derived from LLVM BB %if.end.187
	    Predecessors according to CFG: BB#34
6304B		%vreg912<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg912
6320B		%vreg909<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg909
6336B		%vreg908<def> = LDRWui %vreg909, 16; mem:LD4[%k0189] GPR32:%vreg908 GPR64common:%vreg909
6352B		%WZR<def> = SUBSWrr %vreg912, %vreg908, %NZCV<imp-def>; GPR32:%vreg912,%vreg908
6368B		Bcc 0, <BB#38>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#38 BB#37

6384B	BB#37: derived from LLVM BB %if.then.192
	    Predecessors according to CFG: BB#36
6400B		%vreg1118<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg1118
6416B		%vreg1115<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1115
6432B		STRWui %vreg1118, %vreg1115, 16; mem:ST4[%k0194] GPR32:%vreg1118 GPR64common:%vreg1115
6448B		B <BB#2>
	    Successors according to CFG: BB#2

6464B	BB#38: derived from LLVM BB %if.end.195
	    Predecessors according to CFG: BB#36
6480B		%vreg950<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg950
6496B		%vreg948<def> = LDRWui %vreg950, 15; mem:LD4[%tPos196] GPR32:%vreg948 GPR64common:%vreg950
6512B		%vreg949<def> = SUBREG_TO_REG 0, %vreg948, 15; GPR64:%vreg949 GPR32:%vreg948
6528B		%vreg943<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg943
6544B		%vreg942<def> = LDRXui %vreg943, 394; mem:LD8[%tt198] GPR64:%vreg942 GPR64common:%vreg943
6560B		%vreg938<def> = MOVi64imm 4; GPR64:%vreg938
6576B		%vreg939<def> = MADDXrrr %vreg949, %vreg938, %XZR; GPR64:%vreg939,%vreg949,%vreg938
6592B		%vreg940<def> = ADDXrr %vreg942, %vreg939; GPR64common:%vreg940 GPR64:%vreg942,%vreg939
6608B		%vreg935<def> = LDRWui %vreg940, 0; mem:LD4[%arrayidx199] GPR32:%vreg935 GPR64common:%vreg940
6624B		%vreg933<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg933
6640B		STRWui %vreg935, %vreg933, 15; mem:ST4[%tPos200] GPR32:%vreg935 GPR64common:%vreg933
6656B		%vreg930<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg930
6672B		%vreg929<def> = LDRWui %vreg930, 15; mem:LD4[%tPos201] GPR32:%vreg929 GPR64common:%vreg930
6688B		%vreg927<def> = ANDWri %vreg929, 7; GPR32sp:%vreg927 GPR32:%vreg929
6704B		%vreg925<def> = COPY %vreg927; GPR32:%vreg925 GPR32sp:%vreg927
6720B		STRBBui %vreg925, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg925
6736B		%vreg922<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg922
6752B		%vreg921<def> = LDRWui %vreg922, 15; mem:LD4[%tPos204] GPR32:%vreg921 GPR64common:%vreg922
6768B		%vreg920<def> = UBFMWri %vreg921, 8, 31; GPR32:%vreg920,%vreg921
6784B		STRWui %vreg920, %vreg922, 15; mem:ST4[%tPos204] GPR32:%vreg920 GPR64common:%vreg922
6800B		%vreg916<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg916
6816B		%vreg915<def> = LDRWui %vreg916, 6; mem:LD4[%rNToGo206] GPR32:%vreg915 GPR64common:%vreg916
6832B		CBNZW %vreg915, <BB#42>; GPR32:%vreg915
	    Successors according to CFG: BB#42 BB#39

6848B	BB#39: derived from LLVM BB %if.then.209
	    Predecessors according to CFG: BB#38
6864B		%vreg966<def> = ADRP <ga:@BZ2_rNums>[TF=1]; GPR64common:%vreg966
6880B		%vreg967<def> = ADDXri %vreg966, <ga:@BZ2_rNums>[TF=34], 0; GPR64common:%vreg967,%vreg966
6896B		%vreg977<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg977
6912B		%vreg976<def> = LDRSWui %vreg977, 7; mem:LD4[%rTPos210] GPR64:%vreg976 GPR64common:%vreg977
6928B		%vreg969<def> = MOVi64imm 4; GPR64:%vreg969
6944B		%vreg970<def> = MADDXrrr %vreg976, %vreg969, %XZR; GPR64:%vreg970,%vreg976,%vreg969
6960B		%vreg971<def> = ADDXrr %vreg967, %vreg970; GPR64common:%vreg971,%vreg967 GPR64:%vreg970
6976B		%vreg965<def> = LDRWui %vreg971, 0; mem:LD4[%arrayidx212] GPR32:%vreg965 GPR64common:%vreg971
6992B		%vreg963<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg963
7008B		STRWui %vreg965, %vreg963, 6; mem:ST4[%rNToGo213] GPR32:%vreg965 GPR64common:%vreg963
7024B		%vreg960<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg960
7040B		%vreg959<def> = LDRWui %vreg960, 7; mem:LD4[%rTPos214] GPR32common:%vreg959 GPR64common:%vreg960
7056B		%vreg958<def> = ADDWri %vreg959, 1, 0; GPR32common:%vreg958,%vreg959
7072B		STRWui %vreg958, %vreg960, 7; mem:ST4[%rTPos214] GPR32common:%vreg958 GPR64common:%vreg960
7088B		%vreg954<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg954
7104B		%vreg953<def> = LDRWui %vreg954, 7; mem:LD4[%rTPos216] GPR32common:%vreg953 GPR64common:%vreg954
7120B		%WZR<def> = SUBSWri %vreg953, 512, 0, %NZCV<imp-def>; GPR32common:%vreg953
7136B		Bcc 1, <BB#41>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#41 BB#40

7152B	BB#40: derived from LLVM BB %if.then.219
	    Predecessors according to CFG: BB#39
7168B		%vreg979<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg979
7184B		STRWui %WZR, %vreg979, 7; mem:ST4[%rTPos220] GPR64common:%vreg979
	    Successors according to CFG: BB#41

7200B	BB#41: derived from LLVM BB %if.end.221
	    Predecessors according to CFG: BB#39 BB#40
7216B		B <BB#42>
	    Successors according to CFG: BB#42

7232B	BB#42: derived from LLVM BB %if.end.222
	    Predecessors according to CFG: BB#38 BB#41
7248B		%vreg1046<def> = MOVi32imm 1; GPR32:%vreg1046
7264B		%vreg1047<def> = COPY %WZR; GPR32:%vreg1047
7280B		%vreg1057<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1057
7296B		%vreg1056<def> = LDRWui %vreg1057, 6; mem:LD4[%rNToGo223] GPR32common:%vreg1056 GPR64common:%vreg1057
7312B		%vreg1055<def> = SUBWri %vreg1056, 1, 0; GPR32common:%vreg1055,%vreg1056
7328B		STRWui %vreg1055, %vreg1057, 6; mem:ST4[%rNToGo223] GPR32common:%vreg1055 GPR64common:%vreg1057
7344B		%vreg1051<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1051
7360B		%vreg1050<def> = LDRWui %vreg1051, 6; mem:LD4[%rNToGo225] GPR32common:%vreg1050 GPR64common:%vreg1051
7376B		%WZR<def> = SUBSWri %vreg1050, 1, 0, %NZCV<imp-def>; GPR32common:%vreg1050
7392B		%vreg1048<def> = CSELWr %vreg1046, %vreg1047, 0, %NZCV<imp-use,kill>; GPR32:%vreg1048,%vreg1046,%vreg1047
7408B		%vreg1044<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg1044
7424B		%vreg1041<def> = EORWrr %vreg1044, %vreg1048; GPR32:%vreg1041,%vreg1044,%vreg1048
7440B		%vreg1038<def> = COPY %vreg1041; GPR32:%vreg1038,%vreg1041
7456B		STRBBui %vreg1038, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg1038
7472B		%vreg1035<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1035
7488B		%vreg1034<def> = LDRWui %vreg1035, 273; mem:LD4[%nblock_used232] GPR32common:%vreg1034 GPR64common:%vreg1035
7504B		%vreg1033<def> = ADDWri %vreg1034, 1, 0; GPR32common:%vreg1033,%vreg1034
7520B		STRWui %vreg1033, %vreg1035, 273; mem:ST4[%nblock_used232] GPR32common:%vreg1033 GPR64common:%vreg1035
7536B		%vreg1029<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32common:%vreg1029
7552B		%vreg1026<def> = ADDWri %vreg1029, 4, 0; GPR32common:%vreg1026,%vreg1029
7568B		%vreg1024<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1024
7584B		STRWui %vreg1026, %vreg1024, 4; mem:ST4[%state_out_len236] GPR32common:%vreg1026 GPR64common:%vreg1024
7600B		%vreg1021<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1021
7616B		%vreg1019<def> = LDRWui %vreg1021, 15; mem:LD4[%tPos237] GPR32:%vreg1019 GPR64common:%vreg1021
7632B		%vreg1020<def> = SUBREG_TO_REG 0, %vreg1019, 15; GPR64:%vreg1020 GPR32:%vreg1019
7648B		%vreg1014<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1014
7664B		%vreg1013<def> = LDRXui %vreg1014, 394; mem:LD8[%tt239] GPR64:%vreg1013 GPR64common:%vreg1014
7680B		%vreg1009<def> = MOVi64imm 4; GPR64:%vreg1009
7696B		%vreg1010<def> = MADDXrrr %vreg1020, %vreg1009, %XZR; GPR64:%vreg1010,%vreg1020,%vreg1009
7712B		%vreg1011<def> = ADDXrr %vreg1013, %vreg1010; GPR64common:%vreg1011 GPR64:%vreg1013,%vreg1010
7728B		%vreg1006<def> = LDRWui %vreg1011, 0; mem:LD4[%arrayidx240] GPR32:%vreg1006 GPR64common:%vreg1011
7744B		%vreg1004<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1004
7760B		STRWui %vreg1006, %vreg1004, 15; mem:ST4[%tPos241] GPR32:%vreg1006 GPR64common:%vreg1004
7776B		%vreg1001<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1001
7792B		%vreg1000<def> = LDRWui %vreg1001, 15; mem:LD4[%tPos242] GPR32:%vreg1000 GPR64common:%vreg1001
7808B		%vreg998<def> = ANDWri %vreg1000, 7; GPR32sp:%vreg998 GPR32:%vreg1000
7824B		%vreg996<def> = COPY %vreg998; GPR32:%vreg996 GPR32sp:%vreg998
7840B		%vreg994<def> = UBFMWri %vreg996, 0, 7; GPR32:%vreg994,%vreg996
7856B		%vreg992<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg992
7872B		STRWui %vreg994, %vreg992, 16; mem:ST4[%k0246] GPR32:%vreg994 GPR64common:%vreg992
7888B		%vreg989<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg989
7904B		%vreg988<def> = LDRWui %vreg989, 15; mem:LD4[%tPos247] GPR32:%vreg988 GPR64common:%vreg989
7920B		%vreg987<def> = UBFMWri %vreg988, 8, 31; GPR32:%vreg987,%vreg988
7936B		STRWui %vreg987, %vreg989, 15; mem:ST4[%tPos247] GPR32:%vreg987 GPR64common:%vreg989
7952B		%vreg983<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg983
7968B		%vreg982<def> = LDRWui %vreg983, 6; mem:LD4[%rNToGo249] GPR32:%vreg982 GPR64common:%vreg983
7984B		CBNZW %vreg982, <BB#46>; GPR32:%vreg982
	    Successors according to CFG: BB#46 BB#43

8000B	BB#43: derived from LLVM BB %if.then.252
	    Predecessors according to CFG: BB#42
8016B		%vreg1073<def> = ADRP <ga:@BZ2_rNums>[TF=1]; GPR64common:%vreg1073
8032B		%vreg1074<def> = ADDXri %vreg1073, <ga:@BZ2_rNums>[TF=34], 0; GPR64common:%vreg1074,%vreg1073
8048B		%vreg1084<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1084
8064B		%vreg1083<def> = LDRSWui %vreg1084, 7; mem:LD4[%rTPos253] GPR64:%vreg1083 GPR64common:%vreg1084
8080B		%vreg1076<def> = MOVi64imm 4; GPR64:%vreg1076
8096B		%vreg1077<def> = MADDXrrr %vreg1083, %vreg1076, %XZR; GPR64:%vreg1077,%vreg1083,%vreg1076
8112B		%vreg1078<def> = ADDXrr %vreg1074, %vreg1077; GPR64common:%vreg1078,%vreg1074 GPR64:%vreg1077
8128B		%vreg1072<def> = LDRWui %vreg1078, 0; mem:LD4[%arrayidx255] GPR32:%vreg1072 GPR64common:%vreg1078
8144B		%vreg1070<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1070
8160B		STRWui %vreg1072, %vreg1070, 6; mem:ST4[%rNToGo256] GPR32:%vreg1072 GPR64common:%vreg1070
8176B		%vreg1067<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1067
8192B		%vreg1066<def> = LDRWui %vreg1067, 7; mem:LD4[%rTPos257] GPR32common:%vreg1066 GPR64common:%vreg1067
8208B		%vreg1065<def> = ADDWri %vreg1066, 1, 0; GPR32common:%vreg1065,%vreg1066
8224B		STRWui %vreg1065, %vreg1067, 7; mem:ST4[%rTPos257] GPR32common:%vreg1065 GPR64common:%vreg1067
8240B		%vreg1061<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1061
8256B		%vreg1060<def> = LDRWui %vreg1061, 7; mem:LD4[%rTPos259] GPR32common:%vreg1060 GPR64common:%vreg1061
8272B		%WZR<def> = SUBSWri %vreg1060, 512, 0, %NZCV<imp-def>; GPR32common:%vreg1060
8288B		Bcc 1, <BB#45>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#45 BB#44

8304B	BB#44: derived from LLVM BB %if.then.262
	    Predecessors according to CFG: BB#43
8320B		%vreg1086<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1086
8336B		STRWui %WZR, %vreg1086, 7; mem:ST4[%rTPos263] GPR64common:%vreg1086
	    Successors according to CFG: BB#45

8352B	BB#45: derived from LLVM BB %if.end.264
	    Predecessors according to CFG: BB#43 BB#44
8368B		B <BB#46>
	    Successors according to CFG: BB#46

8384B	BB#46: derived from LLVM BB %if.end.265
	    Predecessors according to CFG: BB#42 BB#45
8400B		%vreg1101<def> = MOVi32imm 1; GPR32:%vreg1101
8416B		%vreg1102<def> = COPY %WZR; GPR32:%vreg1102
8432B		%vreg1112<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1112
8448B		%vreg1111<def> = LDRWui %vreg1112, 6; mem:LD4[%rNToGo266] GPR32common:%vreg1111 GPR64common:%vreg1112
8464B		%vreg1110<def> = SUBWri %vreg1111, 1, 0; GPR32common:%vreg1110,%vreg1111
8480B		STRWui %vreg1110, %vreg1112, 6; mem:ST4[%rNToGo266] GPR32common:%vreg1110 GPR64common:%vreg1112
8496B		%vreg1106<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1106
8512B		%vreg1105<def> = LDRWui %vreg1106, 6; mem:LD4[%rNToGo268] GPR32common:%vreg1105 GPR64common:%vreg1106
8528B		%WZR<def> = SUBSWri %vreg1105, 1, 0, %NZCV<imp-def>; GPR32common:%vreg1105
8544B		%vreg1103<def> = CSELWr %vreg1101, %vreg1102, 0, %NZCV<imp-use,kill>; GPR32:%vreg1103,%vreg1101,%vreg1102
8560B		%vreg1099<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1099
8576B		%vreg1098<def> = LDRWui %vreg1099, 16; mem:LD4[%k0272] GPR32:%vreg1098 GPR64common:%vreg1099
8592B		%vreg1097<def> = EORWrr %vreg1098, %vreg1103; GPR32:%vreg1097,%vreg1098,%vreg1103
8608B		STRWui %vreg1097, %vreg1099, 16; mem:ST4[%k0272] GPR32:%vreg1097 GPR64common:%vreg1099
8624B		%vreg1092<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1092
8640B		%vreg1091<def> = LDRWui %vreg1092, 273; mem:LD4[%nblock_used274] GPR32common:%vreg1091 GPR64common:%vreg1092
8656B		%vreg1090<def> = ADDWri %vreg1091, 1, 0; GPR32common:%vreg1090,%vreg1091
8672B		STRWui %vreg1090, %vreg1092, 273; mem:ST4[%nblock_used274] GPR32common:%vreg1090 GPR64common:%vreg1092
8688B		B <BB#2>
	    Successors according to CFG: BB#2

8704B	BB#47: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#0
8720B		%vreg61<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg61
8736B		%vreg60<def> = LDRWui %vreg61, 796; mem:LD4[%calculatedBlockCRC276] GPR32:%vreg60 GPR64common:%vreg61
8752B		STRWui %vreg60, <fi#3>, 0; mem:ST4[FixedStack3] GPR32:%vreg60
8768B		%vreg57<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg57
8784B		%vreg56<def> = LDRBBui %vreg57, 12; mem:LD1[%state_out_ch277] GPR32:%vreg56 GPR64common:%vreg57
8800B		STRBBui %vreg56, <fi#4>, 0; mem:ST1[FixedStack4] GPR32:%vreg56
8816B		%vreg53<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg53
8832B		%vreg52<def> = LDRWui %vreg53, 4; mem:LD4[%state_out_len278] GPR32:%vreg52 GPR64common:%vreg53
8848B		STRWui %vreg52, <fi#5>, 0; mem:ST4[FixedStack5] GPR32:%vreg52
8864B		%vreg49<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg49
8880B		%vreg48<def> = LDRWui %vreg49, 273; mem:LD4[%nblock_used279] GPR32:%vreg48 GPR64common:%vreg49
8896B		STRWui %vreg48, <fi#6>, 0; mem:ST4[FixedStack6] GPR32:%vreg48
8912B		%vreg45<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg45
8928B		%vreg44<def> = LDRWui %vreg45, 16; mem:LD4[%k0280] GPR32:%vreg44 GPR64common:%vreg45
8944B		STRWui %vreg44, <fi#7>, 0; mem:ST4[FixedStack7] GPR32:%vreg44
8960B		%vreg41<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg41
8976B		%vreg40<def> = LDRXui %vreg41, 394; mem:LD8[%tt281] GPR64:%vreg40 GPR64common:%vreg41
8992B		STRXui %vreg40, <fi#8>, 0; mem:ST8[FixedStack8] GPR64:%vreg40
9008B		%vreg37<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg37
9024B		%vreg36<def> = LDRWui %vreg37, 15; mem:LD4[%tPos282] GPR32:%vreg36 GPR64common:%vreg37
9040B		STRWui %vreg36, <fi#9>, 0; mem:ST4[FixedStack9] GPR32:%vreg36
9056B		%vreg33<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg33
9072B		%vreg32<def> = LDRXui %vreg33, 0; mem:LD8[%strm283] GPR64common:%vreg32,%vreg33
9088B		%vreg30<def> = LDRXui %vreg32, 3; mem:LD8[%next_out284] GPR64:%vreg30 GPR64common:%vreg32
9104B		STRXui %vreg30, <fi#10>, 0; mem:ST8[FixedStack10] GPR64:%vreg30
9120B		%vreg27<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg27
9136B		%vreg26<def> = LDRXui %vreg27, 0; mem:LD8[%strm285] GPR64common:%vreg26,%vreg27
9152B		%vreg24<def> = LDRWui %vreg26, 8; mem:LD4[%avail_out286] GPR32:%vreg24 GPR64common:%vreg26
9168B		STRWui %vreg24, <fi#11>, 0; mem:ST4[FixedStack11] GPR32:%vreg24
9184B		%vreg21<def> = LDRWui <fi#11>, 0; mem:LD4[FixedStack11] GPR32:%vreg21
9200B		STRWui %vreg21, <fi#12>, 0; mem:ST4[FixedStack12] GPR32:%vreg21
9216B		%vreg19<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg19
9232B		%vreg16<def> = MOVi64imm 64080; GPR64:%vreg16
9248B		%vreg17<def> = ADDXrr %vreg19, %vreg16; GPR64common:%vreg17 GPR64:%vreg19,%vreg16
9264B		%vreg18<def> = LDRWui %vreg17, 0; mem:LD4[%save_nblock287] GPR32common:%vreg18 GPR64common:%vreg17
9280B		%vreg14<def> = ADDWri %vreg18, 1, 0; GPR32common:%vreg14,%vreg18
9296B		STRWui %vreg14, <fi#13>, 0; mem:ST4[FixedStack13] GPR32common:%vreg14
	    Successors according to CFG: BB#48

9312B	BB#48: derived from LLVM BB %while.body.289
	    Predecessors according to CFG: BB#47 BB#75 BB#74 BB#72 BB#70 BB#68
9328B		%vreg63<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32common:%vreg63
9344B		%WZR<def> = SUBSWri %vreg63, 0, 0, %NZCV<imp-def>; GPR32common:%vreg63
9360B		Bcc 13, <BB#59>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#59 BB#49

9376B	BB#49: derived from LLVM BB %if.then.292
	    Predecessors according to CFG: BB#48
9392B		B <BB#50>
	    Successors according to CFG: BB#50

9408B	BB#50: derived from LLVM BB %while.body.294
	    Predecessors according to CFG: BB#49 BB#54
9424B		%vreg65<def> = LDRWui <fi#11>, 0; mem:LD4[FixedStack11] GPR32:%vreg65
9440B		CBNZW %vreg65, <BB#52>; GPR32:%vreg65
	    Successors according to CFG: BB#52 BB#51

9456B	BB#51: derived from LLVM BB %if.then.297
	    Predecessors according to CFG: BB#50
9472B		B <BB#76>
	    Successors according to CFG: BB#76

9488B	BB#52: derived from LLVM BB %if.end.298
	    Predecessors according to CFG: BB#50
9504B		%vreg67<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32common:%vreg67
9520B		%WZR<def> = SUBSWri %vreg67, 1, 0, %NZCV<imp-def>; GPR32common:%vreg67
9536B		Bcc 1, <BB#54>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#54 BB#53

9552B	BB#53: derived from LLVM BB %if.then.301
	    Predecessors according to CFG: BB#52
9568B		B <BB#55>
	    Successors according to CFG: BB#55

9584B	BB#54: derived from LLVM BB %if.end.302
	    Predecessors according to CFG: BB#52
9600B		%vreg86<def> = ADRP <ga:@BZ2_crc32Table>[TF=1]; GPR64common:%vreg86
9616B		%vreg87<def> = ADDXri %vreg86, <ga:@BZ2_crc32Table>[TF=34], 0; GPR64common:%vreg87,%vreg86
9632B		%vreg108<def> = LDRBBui <fi#4>, 0; mem:LD1[FixedStack4] GPR32:%vreg108
9648B		%vreg107<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg107
9664B		STRBBui %vreg108, %vreg107, 0; mem:ST1[%249] GPR32:%vreg108 GPR64common:%vreg107
9680B		%vreg104<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg104
9696B		%vreg103<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg103
9712B		%vreg102<def> = UBFMWri %vreg103, 24, 31; GPR32:%vreg102,%vreg103
9728B		%vreg100<def> = LDRBBui <fi#4>, 0; mem:LD1[FixedStack4] GPR32:%vreg100
9744B		%vreg97<def> = EORWrr %vreg102, %vreg100; GPR32:%vreg97,%vreg102,%vreg100
9760B		%vreg93<def> = SUBREG_TO_REG 0, %vreg97, 15; GPR64:%vreg93 GPR32:%vreg97
9776B		%vreg94<def> = UBFMXri %vreg93, 0, 31; GPR64:%vreg94,%vreg93
9792B		%vreg89<def> = MOVi64imm 4; GPR64:%vreg89
9808B		%vreg90<def> = MADDXrrr %vreg94, %vreg89, %XZR; GPR64:%vreg90,%vreg94,%vreg89
9824B		%vreg91<def> = ADDXrr %vreg87, %vreg90; GPR64common:%vreg91,%vreg87 GPR64:%vreg90
9840B		%vreg85<def> = LDRWui %vreg91, 0; mem:LD4[%arrayidx308] GPR32:%vreg85 GPR64common:%vreg91
9856B		%vreg83<def> = EORWrs %vreg85, %vreg104, 8; GPR32:%vreg83,%vreg85,%vreg104
9872B		STRWui %vreg83, <fi#3>, 0; mem:ST4[FixedStack3] GPR32:%vreg83
9888B		%vreg79<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32common:%vreg79
9904B		%vreg78<def> = SUBWri %vreg79, 1, 0; GPR32common:%vreg78,%vreg79
9920B		STRWui %vreg78, <fi#5>, 0; mem:ST4[FixedStack5] GPR32common:%vreg78
9936B		%vreg75<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg75
9952B		%vreg74<def> = ADDXri %vreg75, 1, 0; GPR64common:%vreg74,%vreg75
9968B		STRXui %vreg74, <fi#10>, 0; mem:ST8[FixedStack10] GPR64common:%vreg74
9984B		%vreg71<def> = LDRWui <fi#11>, 0; mem:LD4[FixedStack11] GPR32common:%vreg71
10000B		%vreg70<def> = SUBWri %vreg71, 1, 0; GPR32common:%vreg70,%vreg71
10016B		STRWui %vreg70, <fi#11>, 0; mem:ST4[FixedStack11] GPR32common:%vreg70
10032B		B <BB#50>
	    Successors according to CFG: BB#50

10048B	BB#55: derived from LLVM BB %while.end.313
	    Predecessors according to CFG: BB#53
10064B		B <BB#56>
	    Successors according to CFG: BB#56

10080B	BB#56: derived from LLVM BB %s_state_out_len_eq_one
	    Predecessors according to CFG: BB#55 BB#66 BB#64
10096B		%vreg110<def> = LDRWui <fi#11>, 0; mem:LD4[FixedStack11] GPR32:%vreg110
10112B		CBNZW %vreg110, <BB#58>; GPR32:%vreg110
	    Successors according to CFG: BB#58 BB#57

10128B	BB#57: derived from LLVM BB %if.then.316
	    Predecessors according to CFG: BB#56
10144B		%vreg353<def> = MOVi32imm 1; GPR32:%vreg353
10160B		STRWui %vreg353, <fi#5>, 0; mem:ST4[FixedStack5] GPR32:%vreg353
10176B		B <BB#76>
	    Successors according to CFG: BB#76

10192B	BB#58: derived from LLVM BB %if.end.317
	    Predecessors according to CFG: BB#56
10208B		%vreg125<def> = ADRP <ga:@BZ2_crc32Table>[TF=1]; GPR64common:%vreg125
10224B		%vreg126<def> = ADDXri %vreg125, <ga:@BZ2_crc32Table>[TF=34], 0; GPR64common:%vreg126,%vreg125
10240B		%vreg147<def> = LDRBBui <fi#4>, 0; mem:LD1[FixedStack4] GPR32:%vreg147
10256B		%vreg146<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg146
10272B		STRBBui %vreg147, %vreg146, 0; mem:ST1[%259] GPR32:%vreg147 GPR64common:%vreg146
10288B		%vreg143<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg143
10304B		%vreg142<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg142
10320B		%vreg141<def> = UBFMWri %vreg142, 24, 31; GPR32:%vreg141,%vreg142
10336B		%vreg139<def> = LDRBBui <fi#4>, 0; mem:LD1[FixedStack4] GPR32:%vreg139
10352B		%vreg136<def> = EORWrr %vreg141, %vreg139; GPR32:%vreg136,%vreg141,%vreg139
10368B		%vreg132<def> = SUBREG_TO_REG 0, %vreg136, 15; GPR64:%vreg132 GPR32:%vreg136
10384B		%vreg133<def> = UBFMXri %vreg132, 0, 31; GPR64:%vreg133,%vreg132
10400B		%vreg128<def> = MOVi64imm 4; GPR64:%vreg128
10416B		%vreg129<def> = MADDXrrr %vreg133, %vreg128, %XZR; GPR64:%vreg129,%vreg133,%vreg128
10432B		%vreg130<def> = ADDXrr %vreg126, %vreg129; GPR64common:%vreg130,%vreg126 GPR64:%vreg129
10448B		%vreg124<def> = LDRWui %vreg130, 0; mem:LD4[%arrayidx323] GPR32:%vreg124 GPR64common:%vreg130
10464B		%vreg122<def> = EORWrs %vreg124, %vreg143, 8; GPR32:%vreg122,%vreg124,%vreg143
10480B		STRWui %vreg122, <fi#3>, 0; mem:ST4[FixedStack3] GPR32:%vreg122
10496B		%vreg118<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg118
10512B		%vreg117<def> = ADDXri %vreg118, 1, 0; GPR64common:%vreg117,%vreg118
10528B		STRXui %vreg117, <fi#10>, 0; mem:ST8[FixedStack10] GPR64common:%vreg117
10544B		%vreg114<def> = LDRWui <fi#11>, 0; mem:LD4[FixedStack11] GPR32common:%vreg114
10560B		%vreg113<def> = SUBWri %vreg114, 1, 0; GPR32common:%vreg113,%vreg114
10576B		STRWui %vreg113, <fi#11>, 0; mem:ST4[FixedStack11] GPR32common:%vreg113
	    Successors according to CFG: BB#59

10592B	BB#59: derived from LLVM BB %if.end.327
	    Predecessors according to CFG: BB#48 BB#58
10608B		%vreg151<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg151
10624B		%vreg150<def> = LDRWui <fi#13>, 0; mem:LD4[FixedStack13] GPR32:%vreg150
10640B		%WZR<def> = SUBSWrr %vreg151, %vreg150, %NZCV<imp-def>; GPR32:%vreg151,%vreg150
10656B		Bcc 13, <BB#61>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#61 BB#60

10672B	BB#60: derived from LLVM BB %if.then.330
	    Predecessors according to CFG: BB#59
10688B		%vreg352<def> = MOVi32imm 1; GPR32:%vreg352
10704B		STRBBui %vreg352, <fi#0>, 0; mem:ST1[FixedStack0] GPR32:%vreg352
10720B		B <BB#80>
	    Successors according to CFG: BB#80

10736B	BB#61: derived from LLVM BB %if.end.331
	    Predecessors according to CFG: BB#59
10752B		%vreg155<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg155
10768B		%vreg154<def> = LDRWui <fi#13>, 0; mem:LD4[FixedStack13] GPR32:%vreg154
10784B		%WZR<def> = SUBSWrr %vreg155, %vreg154, %NZCV<imp-def>; GPR32:%vreg155,%vreg154
10800B		Bcc 1, <BB#63>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#63 BB#62

10816B	BB#62: derived from LLVM BB %if.then.334
	    Predecessors according to CFG: BB#61
10832B		STRWui %WZR, <fi#5>, 0; mem:ST4[FixedStack5]
10848B		B <BB#76>
	    Successors according to CFG: BB#76

10864B	BB#63: derived from LLVM BB %if.end.335
	    Predecessors according to CFG: BB#61
10880B		%vreg193<def> = LDRWui <fi#7>, 0; mem:LD4[FixedStack7] GPR32:%vreg193
10896B		%vreg192<def> = COPY %vreg193; GPR32:%vreg192,%vreg193
10912B		STRBBui %vreg192, <fi#4>, 0; mem:ST1[FixedStack4] GPR32:%vreg192
10928B		%vreg188<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32:%vreg188
10944B		%vreg189<def> = SUBREG_TO_REG 0, %vreg188, 15; GPR64:%vreg189 GPR32:%vreg188
10960B		%vreg184<def> = LDRXui <fi#8>, 0; mem:LD8[FixedStack8] GPR64:%vreg184
10976B		%vreg181<def> = MOVi64imm 4; GPR64:%vreg181
10992B		%vreg182<def> = MADDXrrr %vreg189, %vreg181, %XZR; GPR64:%vreg182,%vreg189,%vreg181
11008B		%vreg183<def> = ADDXrr %vreg184, %vreg182; GPR64common:%vreg183 GPR64:%vreg184,%vreg182
11024B		%vreg178<def> = LDRWui %vreg183, 0; mem:LD4[%arrayidx338] GPR32:%vreg178 GPR64common:%vreg183
11040B		STRWui %vreg178, <fi#9>, 0; mem:ST4[FixedStack9] GPR32:%vreg178
11056B		%vreg175<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32:%vreg175
11072B		%vreg174<def> = ANDWri %vreg175, 7; GPR32sp:%vreg174 GPR32:%vreg175
11088B		%vreg172<def> = COPY %vreg174; GPR32:%vreg172 GPR32sp:%vreg174
11104B		STRBBui %vreg172, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg172
11120B		%vreg169<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32:%vreg169
11136B		%vreg168<def> = UBFMWri %vreg169, 8, 31; GPR32:%vreg168,%vreg169
11152B		STRWui %vreg168, <fi#9>, 0; mem:ST4[FixedStack9] GPR32:%vreg168
11168B		%vreg165<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32common:%vreg165
11184B		%vreg164<def> = ADDWri %vreg165, 1, 0; GPR32common:%vreg164,%vreg165
11200B		STRWui %vreg164, <fi#6>, 0; mem:ST4[FixedStack6] GPR32common:%vreg164
11216B		%vreg161<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg161
11232B		%vreg158<def> = LDRWui <fi#7>, 0; mem:LD4[FixedStack7] GPR32:%vreg158
11248B		%WZR<def> = SUBSWrr %vreg161, %vreg158, %NZCV<imp-def>; GPR32:%vreg161,%vreg158
11264B		Bcc 0, <BB#65>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#65 BB#64

11280B	BB#64: derived from LLVM BB %if.then.346
	    Predecessors according to CFG: BB#63
11296B		%vreg351<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg351
11312B		STRWui %vreg351, <fi#7>, 0; mem:ST4[FixedStack7] GPR32:%vreg351
11328B		B <BB#56>
	    Successors according to CFG: BB#56

11344B	BB#65: derived from LLVM BB %if.end.348
	    Predecessors according to CFG: BB#63
11360B		%vreg197<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg197
11376B		%vreg196<def> = LDRWui <fi#13>, 0; mem:LD4[FixedStack13] GPR32:%vreg196
11392B		%WZR<def> = SUBSWrr %vreg197, %vreg196, %NZCV<imp-def>; GPR32:%vreg197,%vreg196
11408B		Bcc 1, <BB#67>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#67 BB#66

11424B	BB#66: derived from LLVM BB %if.then.351
	    Predecessors according to CFG: BB#65
11440B		B <BB#56>
	    Successors according to CFG: BB#56

11456B	BB#67: derived from LLVM BB %if.end.352
	    Predecessors according to CFG: BB#65
11472B		%vreg230<def> = MOVi32imm 2; GPR32:%vreg230
11488B		STRWui %vreg230, <fi#5>, 0; mem:ST4[FixedStack5] GPR32:%vreg230
11504B		%vreg228<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32:%vreg228
11520B		%vreg229<def> = SUBREG_TO_REG 0, %vreg228, 15; GPR64:%vreg229 GPR32:%vreg228
11536B		%vreg224<def> = LDRXui <fi#8>, 0; mem:LD8[FixedStack8] GPR64:%vreg224
11552B		%vreg221<def> = MOVi64imm 4; GPR64:%vreg221
11568B		%vreg222<def> = MADDXrrr %vreg229, %vreg221, %XZR; GPR64:%vreg222,%vreg229,%vreg221
11584B		%vreg223<def> = ADDXrr %vreg224, %vreg222; GPR64common:%vreg223 GPR64:%vreg224,%vreg222
11600B		%vreg218<def> = LDRWui %vreg223, 0; mem:LD4[%arrayidx354] GPR32:%vreg218 GPR64common:%vreg223
11616B		STRWui %vreg218, <fi#9>, 0; mem:ST4[FixedStack9] GPR32:%vreg218
11632B		%vreg215<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32:%vreg215
11648B		%vreg214<def> = ANDWri %vreg215, 7; GPR32sp:%vreg214 GPR32:%vreg215
11664B		%vreg212<def> = COPY %vreg214; GPR32:%vreg212 GPR32sp:%vreg214
11680B		STRBBui %vreg212, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg212
11696B		%vreg209<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32:%vreg209
11712B		%vreg208<def> = UBFMWri %vreg209, 8, 31; GPR32:%vreg208,%vreg209
11728B		STRWui %vreg208, <fi#9>, 0; mem:ST4[FixedStack9] GPR32:%vreg208
11744B		%vreg205<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32common:%vreg205
11760B		%vreg204<def> = ADDWri %vreg205, 1, 0; GPR32common:%vreg204,%vreg205
11776B		STRWui %vreg204, <fi#6>, 0; mem:ST4[FixedStack6] GPR32common:%vreg204
11792B		%vreg201<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg201
11808B		%vreg200<def> = LDRWui <fi#13>, 0; mem:LD4[FixedStack13] GPR32:%vreg200
11824B		%WZR<def> = SUBSWrr %vreg201, %vreg200, %NZCV<imp-def>; GPR32:%vreg201,%vreg200
11840B		Bcc 1, <BB#69>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#69 BB#68

11856B	BB#68: derived from LLVM BB %if.then.361
	    Predecessors according to CFG: BB#67
11872B		B <BB#48>
	    Successors according to CFG: BB#48

11888B	BB#69: derived from LLVM BB %if.end.362
	    Predecessors according to CFG: BB#67
11904B		%vreg236<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg236
11920B		%vreg233<def> = LDRWui <fi#7>, 0; mem:LD4[FixedStack7] GPR32:%vreg233
11936B		%WZR<def> = SUBSWrr %vreg236, %vreg233, %NZCV<imp-def>; GPR32:%vreg236,%vreg233
11952B		Bcc 0, <BB#71>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#71 BB#70

11968B	BB#70: derived from LLVM BB %if.then.366
	    Predecessors according to CFG: BB#69
11984B		%vreg347<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg347
12000B		STRWui %vreg347, <fi#7>, 0; mem:ST4[FixedStack7] GPR32:%vreg347
12016B		B <BB#48>
	    Successors according to CFG: BB#48

12032B	BB#71: derived from LLVM BB %if.end.368
	    Predecessors according to CFG: BB#69
12048B		%vreg269<def> = MOVi32imm 3; GPR32:%vreg269
12064B		STRWui %vreg269, <fi#5>, 0; mem:ST4[FixedStack5] GPR32:%vreg269
12080B		%vreg267<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32:%vreg267
12096B		%vreg268<def> = SUBREG_TO_REG 0, %vreg267, 15; GPR64:%vreg268 GPR32:%vreg267
12112B		%vreg263<def> = LDRXui <fi#8>, 0; mem:LD8[FixedStack8] GPR64:%vreg263
12128B		%vreg260<def> = MOVi64imm 4; GPR64:%vreg260
12144B		%vreg261<def> = MADDXrrr %vreg268, %vreg260, %XZR; GPR64:%vreg261,%vreg268,%vreg260
12160B		%vreg262<def> = ADDXrr %vreg263, %vreg261; GPR64common:%vreg262 GPR64:%vreg263,%vreg261
12176B		%vreg257<def> = LDRWui %vreg262, 0; mem:LD4[%arrayidx370] GPR32:%vreg257 GPR64common:%vreg262
12192B		STRWui %vreg257, <fi#9>, 0; mem:ST4[FixedStack9] GPR32:%vreg257
12208B		%vreg254<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32:%vreg254
12224B		%vreg253<def> = ANDWri %vreg254, 7; GPR32sp:%vreg253 GPR32:%vreg254
12240B		%vreg251<def> = COPY %vreg253; GPR32:%vreg251 GPR32sp:%vreg253
12256B		STRBBui %vreg251, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg251
12272B		%vreg248<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32:%vreg248
12288B		%vreg247<def> = UBFMWri %vreg248, 8, 31; GPR32:%vreg247,%vreg248
12304B		STRWui %vreg247, <fi#9>, 0; mem:ST4[FixedStack9] GPR32:%vreg247
12320B		%vreg244<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32common:%vreg244
12336B		%vreg243<def> = ADDWri %vreg244, 1, 0; GPR32common:%vreg243,%vreg244
12352B		STRWui %vreg243, <fi#6>, 0; mem:ST4[FixedStack6] GPR32common:%vreg243
12368B		%vreg240<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg240
12384B		%vreg239<def> = LDRWui <fi#13>, 0; mem:LD4[FixedStack13] GPR32:%vreg239
12400B		%WZR<def> = SUBSWrr %vreg240, %vreg239, %NZCV<imp-def>; GPR32:%vreg240,%vreg239
12416B		Bcc 1, <BB#73>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#73 BB#72

12432B	BB#72: derived from LLVM BB %if.then.377
	    Predecessors according to CFG: BB#71
12448B		B <BB#48>
	    Successors according to CFG: BB#48

12464B	BB#73: derived from LLVM BB %if.end.378
	    Predecessors according to CFG: BB#71
12480B		%vreg275<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg275
12496B		%vreg272<def> = LDRWui <fi#7>, 0; mem:LD4[FixedStack7] GPR32:%vreg272
12512B		%WZR<def> = SUBSWrr %vreg275, %vreg272, %NZCV<imp-def>; GPR32:%vreg275,%vreg272
12528B		Bcc 0, <BB#75>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#75 BB#74

12544B	BB#74: derived from LLVM BB %if.then.382
	    Predecessors according to CFG: BB#73
12560B		%vreg343<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg343
12576B		STRWui %vreg343, <fi#7>, 0; mem:ST4[FixedStack7] GPR32:%vreg343
12592B		B <BB#48>
	    Successors according to CFG: BB#48

12608B	BB#75: derived from LLVM BB %if.end.384
	    Predecessors according to CFG: BB#73
12624B		%vreg338<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32:%vreg338
12640B		%vreg339<def> = SUBREG_TO_REG 0, %vreg338, 15; GPR64:%vreg339 GPR32:%vreg338
12656B		%vreg334<def> = LDRXui <fi#8>, 0; mem:LD8[FixedStack8] GPR64:%vreg334
12672B		%vreg331<def> = MOVi64imm 4; GPR64:%vreg331
12688B		%vreg332<def> = MADDXrrr %vreg339, %vreg331, %XZR; GPR64:%vreg332,%vreg339,%vreg331
12704B		%vreg333<def> = ADDXrr %vreg334, %vreg332; GPR64common:%vreg333 GPR64:%vreg334,%vreg332
12720B		%vreg328<def> = LDRWui %vreg333, 0; mem:LD4[%arrayidx386] GPR32:%vreg328 GPR64common:%vreg333
12736B		STRWui %vreg328, <fi#9>, 0; mem:ST4[FixedStack9] GPR32:%vreg328
12752B		%vreg325<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32:%vreg325
12768B		%vreg324<def> = ANDWri %vreg325, 7; GPR32sp:%vreg324 GPR32:%vreg325
12784B		%vreg322<def> = COPY %vreg324; GPR32:%vreg322 GPR32sp:%vreg324
12800B		STRBBui %vreg322, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg322
12816B		%vreg319<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32:%vreg319
12832B		%vreg318<def> = UBFMWri %vreg319, 8, 31; GPR32:%vreg318,%vreg319
12848B		STRWui %vreg318, <fi#9>, 0; mem:ST4[FixedStack9] GPR32:%vreg318
12864B		%vreg315<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32common:%vreg315
12880B		%vreg314<def> = ADDWri %vreg315, 1, 0; GPR32common:%vreg314,%vreg315
12896B		STRWui %vreg314, <fi#6>, 0; mem:ST4[FixedStack6] GPR32common:%vreg314
12912B		%vreg311<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32common:%vreg311
12928B		%vreg308<def> = ADDWri %vreg311, 4, 0; GPR32common:%vreg308,%vreg311
12944B		STRWui %vreg308, <fi#5>, 0; mem:ST4[FixedStack5] GPR32common:%vreg308
12960B		%vreg304<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32:%vreg304
12976B		%vreg305<def> = SUBREG_TO_REG 0, %vreg304, 15; GPR64:%vreg305 GPR32:%vreg304
12992B		%vreg300<def> = LDRXui <fi#8>, 0; mem:LD8[FixedStack8] GPR64:%vreg300
13008B		%vreg297<def> = MOVi64imm 4; GPR64:%vreg297
13024B		%vreg298<def> = MADDXrrr %vreg305, %vreg297, %XZR; GPR64:%vreg298,%vreg305,%vreg297
13040B		%vreg299<def> = ADDXrr %vreg300, %vreg298; GPR64common:%vreg299 GPR64:%vreg300,%vreg298
13056B		%vreg294<def> = LDRWui %vreg299, 0; mem:LD4[%arrayidx394] GPR32:%vreg294 GPR64common:%vreg299
13072B		STRWui %vreg294, <fi#9>, 0; mem:ST4[FixedStack9] GPR32:%vreg294
13088B		%vreg291<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32:%vreg291
13104B		%vreg290<def> = ANDWri %vreg291, 7; GPR32sp:%vreg290 GPR32:%vreg291
13120B		%vreg288<def> = COPY %vreg290; GPR32:%vreg288 GPR32sp:%vreg290
13136B		%vreg286<def> = UBFMWri %vreg288, 0, 7; GPR32:%vreg286,%vreg288
13152B		STRWui %vreg286, <fi#7>, 0; mem:ST4[FixedStack7] GPR32:%vreg286
13168B		%vreg283<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32:%vreg283
13184B		%vreg282<def> = UBFMWri %vreg283, 8, 31; GPR32:%vreg282,%vreg283
13200B		STRWui %vreg282, <fi#9>, 0; mem:ST4[FixedStack9] GPR32:%vreg282
13216B		%vreg279<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32common:%vreg279
13232B		%vreg278<def> = ADDWri %vreg279, 1, 0; GPR32common:%vreg278,%vreg279
13248B		STRWui %vreg278, <fi#6>, 0; mem:ST4[FixedStack6] GPR32common:%vreg278
13264B		B <BB#48>
	    Successors according to CFG: BB#48

13280B	BB#76: derived from LLVM BB %return_notr
	    Predecessors according to CFG: BB#62 BB#57 BB#51
13296B		%vreg381<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg381
13312B		%vreg380<def> = LDRXui %vreg381, 0; mem:LD8[%strm400] GPR64common:%vreg380,%vreg381
13328B		%vreg378<def> = LDRWui %vreg380, 9; mem:LD4[%total_out_lo32401] GPR32:%vreg378 GPR64common:%vreg380
13344B		STRWui %vreg378, <fi#14>, 0; mem:ST4[FixedStack14] GPR32:%vreg378
13360B		%vreg375<def> = LDRWui <fi#12>, 0; mem:LD4[FixedStack12] GPR32:%vreg375
13376B		%vreg374<def> = LDRWui <fi#11>, 0; mem:LD4[FixedStack11] GPR32:%vreg374
13392B		%vreg373<def> = SUBWrr %vreg375, %vreg374; GPR32:%vreg373,%vreg375,%vreg374
13408B		%vreg370<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg370
13424B		%vreg369<def> = LDRXui %vreg370, 0; mem:LD8[%strm402] GPR64common:%vreg369,%vreg370
13440B		%vreg367<def> = LDRWui %vreg369, 9; mem:LD4[%total_out_lo32403] GPR32:%vreg367 GPR64common:%vreg369
13456B		%vreg366<def> = ADDWrr %vreg367, %vreg373; GPR32:%vreg366,%vreg367,%vreg373
13472B		STRWui %vreg366, %vreg369, 9; mem:ST4[%total_out_lo32403] GPR32:%vreg366 GPR64common:%vreg369
13488B		%vreg361<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg361
13504B		%vreg360<def> = LDRXui %vreg361, 0; mem:LD8[%strm405] GPR64common:%vreg360,%vreg361
13520B		%vreg358<def> = LDRWui %vreg360, 9; mem:LD4[%total_out_lo32406] GPR32:%vreg358 GPR64common:%vreg360
13536B		%vreg356<def> = LDRWui <fi#14>, 0; mem:LD4[FixedStack14] GPR32:%vreg356
13552B		%WZR<def> = SUBSWrr %vreg358, %vreg356, %NZCV<imp-def>; GPR32:%vreg358,%vreg356
13568B		Bcc 2, <BB#78>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#78 BB#77

13584B	BB#77: derived from LLVM BB %if.then.409
	    Predecessors according to CFG: BB#76
13600B		%vreg389<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg389
13616B		%vreg388<def> = LDRXui %vreg389, 0; mem:LD8[%strm410] GPR64common:%vreg388,%vreg389
13632B		%vreg386<def> = LDRWui %vreg388, 10; mem:LD4[%total_out_hi32411] GPR32common:%vreg386 GPR64common:%vreg388
13648B		%vreg385<def> = ADDWri %vreg386, 1, 0; GPR32common:%vreg385,%vreg386
13664B		STRWui %vreg385, %vreg388, 10; mem:ST4[%total_out_hi32411] GPR32common:%vreg385 GPR64common:%vreg388
	    Successors according to CFG: BB#78

13680B	BB#78: derived from LLVM BB %if.end.413
	    Predecessors according to CFG: BB#76 BB#77
13696B		%vreg429<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg429
13712B		%vreg428<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg428
13728B		STRWui %vreg429, %vreg428, 796; mem:ST4[%calculatedBlockCRC414] GPR32:%vreg429 GPR64common:%vreg428
13744B		%vreg425<def> = LDRBBui <fi#4>, 0; mem:LD1[FixedStack4] GPR32:%vreg425
13760B		%vreg424<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg424
13776B		STRBBui %vreg425, %vreg424, 12; mem:ST1[%state_out_ch415] GPR32:%vreg425 GPR64common:%vreg424
13792B		%vreg421<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32:%vreg421
13808B		%vreg420<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg420
13824B		STRWui %vreg421, %vreg420, 4; mem:ST4[%state_out_len416] GPR32:%vreg421 GPR64common:%vreg420
13840B		%vreg417<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg417
13856B		%vreg416<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg416
13872B		STRWui %vreg417, %vreg416, 273; mem:ST4[%nblock_used417] GPR32:%vreg417 GPR64common:%vreg416
13888B		%vreg413<def> = LDRWui <fi#7>, 0; mem:LD4[FixedStack7] GPR32:%vreg413
13904B		%vreg412<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg412
13920B		STRWui %vreg413, %vreg412, 16; mem:ST4[%k0418] GPR32:%vreg413 GPR64common:%vreg412
13936B		%vreg409<def> = LDRXui <fi#8>, 0; mem:LD8[FixedStack8] GPR64:%vreg409
13952B		%vreg408<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg408
13968B		STRXui %vreg409, %vreg408, 394; mem:ST8[%tt419] GPR64:%vreg409 GPR64common:%vreg408
13984B		%vreg405<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32:%vreg405
14000B		%vreg404<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg404
14016B		STRWui %vreg405, %vreg404, 15; mem:ST4[%tPos420] GPR32:%vreg405 GPR64common:%vreg404
14032B		%vreg401<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg401
14048B		%vreg400<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg400
14064B		%vreg399<def> = LDRXui %vreg400, 0; mem:LD8[%strm421] GPR64common:%vreg399,%vreg400
14080B		STRXui %vreg401, %vreg399, 3; mem:ST8[%next_out422] GPR64:%vreg401 GPR64common:%vreg399
14096B		%vreg395<def> = LDRWui <fi#11>, 0; mem:LD4[FixedStack11] GPR32:%vreg395
14112B		%vreg394<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg394
14128B		%vreg393<def> = LDRXui %vreg394, 0; mem:LD8[%strm423] GPR64common:%vreg393,%vreg394
14144B		STRWui %vreg395, %vreg393, 8; mem:ST4[%avail_out424] GPR32:%vreg395 GPR64common:%vreg393
	    Successors according to CFG: BB#79

14160B	BB#79: derived from LLVM BB %if.end.425
	    Predecessors according to CFG: BB#78
14176B		STRBBui %WZR, <fi#0>, 0; mem:ST1[FixedStack0]
	    Successors according to CFG: BB#80

14192B	BB#80: derived from LLVM BB %return
	    Predecessors according to CFG: BB#60 BB#79 BB#13 BB#11 BB#4
14208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
14224B		%vreg1133<def> = MOVaddr <ga:@unRLE_obuf_to_output_FAST>[TF=1], <ga:@unRLE_obuf_to_output_FAST>[TF=34]; GPR64:%vreg1133
14240B		%X0<def> = COPY %vreg1133; GPR64:%vreg1133
14256B		%X1<def> = COPY %vreg11; GPR64:%vreg11
14272B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %SP<imp-def>
14288B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
14304B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
14320B		STACKMAP 1, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=1)
14336B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
14352B		%vreg1134<def> = LDRBBui <fi#0>, 0; mem:LD1[%retval] GPR32:%vreg1134
14368B		%vreg1132<def,dead> = COPY %vreg1134; GPR32all:%vreg1132 GPR32:%vreg1134
14384B		%W0<def> = COPY %vreg1134; GPR32:%vreg1134
14400B		RET_ReallyLR %W0<imp-use>

# End machine code for function unRLE_obuf_to_output_FAST.

********** SIMPLE REGISTER COALESCING **********
********** Function: unRLE_obuf_to_output_FAST
********** JOINING INTERVALS ***********
while.body.2:
while.body.294:
if.end:
if.end.6:
896B	%vreg491<def> = SUBREG_TO_REG 0, %vreg495, 15; GPR64:%vreg491 GPR32:%vreg495
	Considering merging to GPR64 with %vreg495 in %vreg491:sub_32
		RHS = %vreg495 [880r,896r:0)  0@880r
		LHS = %vreg491 [896r,912r:0)  0@896r
		merge %vreg491:0@896r into %vreg495:0@880r --> @880r
		erased:	896r	%vreg491<def> = SUBREG_TO_REG 0, %vreg495, 15; GPR64:%vreg491 GPR32:%vreg495
		updated: 880B	%vreg491:sub_32<def,read-undef> = EORWrr %vreg502, %vreg499; GPR64:%vreg491 GPR32:%vreg502,%vreg499
	Success: %vreg495:sub_32 -> %vreg491
	Result = %vreg491 [880r,912r:0)  0@880r
if.end.26:
if.end.298:
if.then.23:
if.end.302:
9760B	%vreg93<def> = SUBREG_TO_REG 0, %vreg97, 15; GPR64:%vreg93 GPR32:%vreg97
	Considering merging to GPR64 with %vreg97 in %vreg93:sub_32
		RHS = %vreg97 [9744r,9760r:0)  0@9744r
		LHS = %vreg93 [9760r,9776r:0)  0@9760r
		merge %vreg93:0@9760r into %vreg97:0@9744r --> @9744r
		erased:	9760r	%vreg93<def> = SUBREG_TO_REG 0, %vreg97, 15; GPR64:%vreg93 GPR32:%vreg97
		updated: 9744B	%vreg93:sub_32<def,read-undef> = EORWrr %vreg102, %vreg100; GPR64:%vreg93 GPR32:%vreg102,%vreg100
	Success: %vreg97:sub_32 -> %vreg93
	Result = %vreg93 [9744r,9776r:0)  0@9744r
while.body:
while.body.289:
s_state_out_len_eq_one:
if.end.62:
2896B	%vreg658<def> = COPY %WZR; GPR32:%vreg658
	Considering merging %vreg658 with %WZR
		RHS = %vreg658 [2896r,3024r:0)  0@2896r
		Interference: WZR
	Interference!
if.end.115:
4368B	%vreg776<def> = COPY %WZR; GPR32:%vreg776
	Considering merging %vreg776 with %WZR
		RHS = %vreg776 [4368r,4496r:0)  0@4368r
		Interference: WZR
	Interference!
if.end.169:
5840B	%vreg894<def> = COPY %WZR; GPR32:%vreg894
	Considering merging %vreg894 with %WZR
		RHS = %vreg894 [5840r,5968r:0)  0@5840r
		Interference: WZR
	Interference!
if.end.222:
7264B	%vreg1047<def> = COPY %WZR; GPR32:%vreg1047
	Considering merging %vreg1047 with %WZR
		RHS = %vreg1047 [7264r,7392r:0)  0@7264r
		Interference: WZR
	Interference!
7632B	%vreg1020<def> = SUBREG_TO_REG 0, %vreg1019, 15; GPR64:%vreg1020 GPR32:%vreg1019
	Considering merging to GPR64 with %vreg1019 in %vreg1020:sub_32
		RHS = %vreg1019 [7616r,7632r:0)  0@7616r
		LHS = %vreg1020 [7632r,7696r:0)  0@7632r
		merge %vreg1020:0@7632r into %vreg1019:0@7616r --> @7616r
		erased:	7632r	%vreg1020<def> = SUBREG_TO_REG 0, %vreg1019, 15; GPR64:%vreg1020 GPR32:%vreg1019
		updated: 7616B	%vreg1020:sub_32<def,read-undef> = LDRWui %vreg1021, 15; mem:LD4[%tPos237] GPR64:%vreg1020 GPR64common:%vreg1021
	Success: %vreg1019:sub_32 -> %vreg1020
	Result = %vreg1020 [7616r,7696r:0)  0@7616r
if.end.327:
while.end:
if.end.30:
if.end.37:
2144B	%vreg587<def> = SUBREG_TO_REG 0, %vreg586, 15; GPR64:%vreg587 GPR32:%vreg586
	Considering merging to GPR64 with %vreg586 in %vreg587:sub_32
		RHS = %vreg586 [2128r,2144r:0)  0@2128r
		LHS = %vreg587 [2144r,2208r:0)  0@2144r
		merge %vreg587:0@2144r into %vreg586:0@2128r --> @2128r
		erased:	2144r	%vreg587<def> = SUBREG_TO_REG 0, %vreg586, 15; GPR64:%vreg587 GPR32:%vreg586
		updated: 2128B	%vreg587:sub_32<def,read-undef> = LDRWui %vreg588, 15; mem:LD4[%tPos] GPR64:%vreg587 GPR64common:%vreg588
	Success: %vreg586:sub_32 -> %vreg587
	Result = %vreg587 [2128r,2208r:0)  0@2128r
if.then.50:
if.end.61:
if.end.79:
if.end.87:
3616B	%vreg713<def> = SUBREG_TO_REG 0, %vreg712, 15; GPR64:%vreg713 GPR32:%vreg712
	Considering merging to GPR64 with %vreg712 in %vreg713:sub_32
		RHS = %vreg712 [3600r,3616r:0)  0@3600r
		LHS = %vreg713 [3616r,3680r:0)  0@3616r
		merge %vreg713:0@3616r into %vreg712:0@3600r --> @3600r
		erased:	3616r	%vreg713<def> = SUBREG_TO_REG 0, %vreg712, 15; GPR64:%vreg713 GPR32:%vreg712
		updated: 3600B	%vreg713:sub_32<def,read-undef> = LDRWui %vreg714, 15; mem:LD4[%tPos89] GPR64:%vreg713 GPR64common:%vreg714
	Success: %vreg712:sub_32 -> %vreg713
	Result = %vreg713 [3600r,3680r:0)  0@3600r
if.then.102:
if.end.114:
if.end.133:
if.end.141:
5088B	%vreg831<def> = SUBREG_TO_REG 0, %vreg830, 15; GPR64:%vreg831 GPR32:%vreg830
	Considering merging to GPR64 with %vreg830 in %vreg831:sub_32
		RHS = %vreg830 [5072r,5088r:0)  0@5072r
		LHS = %vreg831 [5088r,5152r:0)  0@5088r
		merge %vreg831:0@5088r into %vreg830:0@5072r --> @5072r
		erased:	5088r	%vreg831<def> = SUBREG_TO_REG 0, %vreg830, 15; GPR64:%vreg831 GPR32:%vreg830
		updated: 5072B	%vreg831:sub_32<def,read-undef> = LDRWui %vreg832, 15; mem:LD4[%tPos143] GPR64:%vreg831 GPR64common:%vreg832
	Success: %vreg830:sub_32 -> %vreg831
	Result = %vreg831 [5072r,5152r:0)  0@5072r
if.then.156:
if.end.168:
if.end.187:
if.end.195:
6512B	%vreg949<def> = SUBREG_TO_REG 0, %vreg948, 15; GPR64:%vreg949 GPR32:%vreg948
	Considering merging to GPR64 with %vreg948 in %vreg949:sub_32
		RHS = %vreg948 [6496r,6512r:0)  0@6496r
		LHS = %vreg949 [6512r,6576r:0)  0@6512r
		merge %vreg949:0@6512r into %vreg948:0@6496r --> @6496r
		erased:	6512r	%vreg949<def> = SUBREG_TO_REG 0, %vreg948, 15; GPR64:%vreg949 GPR32:%vreg948
		updated: 6496B	%vreg949:sub_32<def,read-undef> = LDRWui %vreg950, 15; mem:LD4[%tPos196] GPR64:%vreg949 GPR64common:%vreg950
	Success: %vreg948:sub_32 -> %vreg949
	Result = %vreg949 [6496r,6576r:0)  0@6496r
if.then.209:
if.end.221:
if.then.252:
if.end.264:
if.end.265:
8416B	%vreg1102<def> = COPY %WZR; GPR32:%vreg1102
	Considering merging %vreg1102 with %WZR
		RHS = %vreg1102 [8416r,8544r:0)  0@8416r
		Interference: WZR
	Interference!
if.end.331:
if.end.335:
10944B	%vreg189<def> = SUBREG_TO_REG 0, %vreg188, 15; GPR64:%vreg189 GPR32:%vreg188
	Considering merging to GPR64 with %vreg188 in %vreg189:sub_32
		RHS = %vreg188 [10928r,10944r:0)  0@10928r
		LHS = %vreg189 [10944r,10992r:0)  0@10944r
		merge %vreg189:0@10944r into %vreg188:0@10928r --> @10928r
		erased:	10944r	%vreg189<def> = SUBREG_TO_REG 0, %vreg188, 15; GPR64:%vreg189 GPR32:%vreg188
		updated: 10928B	%vreg189:sub_32<def,read-undef> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR64:%vreg189
	Success: %vreg188:sub_32 -> %vreg189
	Result = %vreg189 [10928r,10992r:0)  0@10928r
if.end.348:
if.end.352:
11520B	%vreg229<def> = SUBREG_TO_REG 0, %vreg228, 15; GPR64:%vreg229 GPR32:%vreg228
	Considering merging to GPR64 with %vreg228 in %vreg229:sub_32
		RHS = %vreg228 [11504r,11520r:0)  0@11504r
		LHS = %vreg229 [11520r,11568r:0)  0@11520r
		merge %vreg229:0@11520r into %vreg228:0@11504r --> @11504r
		erased:	11520r	%vreg229<def> = SUBREG_TO_REG 0, %vreg228, 15; GPR64:%vreg229 GPR32:%vreg228
		updated: 11504B	%vreg229:sub_32<def,read-undef> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR64:%vreg229
	Success: %vreg228:sub_32 -> %vreg229
	Result = %vreg229 [11504r,11568r:0)  0@11504r
if.end.362:
if.end.368:
12096B	%vreg268<def> = SUBREG_TO_REG 0, %vreg267, 15; GPR64:%vreg268 GPR32:%vreg267
	Considering merging to GPR64 with %vreg267 in %vreg268:sub_32
		RHS = %vreg267 [12080r,12096r:0)  0@12080r
		LHS = %vreg268 [12096r,12144r:0)  0@12096r
		merge %vreg268:0@12096r into %vreg267:0@12080r --> @12080r
		erased:	12096r	%vreg268<def> = SUBREG_TO_REG 0, %vreg267, 15; GPR64:%vreg268 GPR32:%vreg267
		updated: 12080B	%vreg268:sub_32<def,read-undef> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR64:%vreg268
	Success: %vreg267:sub_32 -> %vreg268
	Result = %vreg268 [12080r,12144r:0)  0@12080r
if.end.378:
if.then.5:
if.then.59:
if.then.78:
if.then.84:
if.then.112:
if.then.132:
if.then.138:
if.then.166:
if.then.186:
if.then.192:
if.then.219:
if.then.262:
if.then.292:
if.then.301:
while.end.313:
if.end.317:
10368B	%vreg132<def> = SUBREG_TO_REG 0, %vreg136, 15; GPR64:%vreg132 GPR32:%vreg136
	Considering merging to GPR64 with %vreg136 in %vreg132:sub_32
		RHS = %vreg136 [10352r,10368r:0)  0@10352r
		LHS = %vreg132 [10368r,10384r:0)  0@10368r
		merge %vreg132:0@10368r into %vreg136:0@10352r --> @10352r
		erased:	10368r	%vreg132<def> = SUBREG_TO_REG 0, %vreg136, 15; GPR64:%vreg132 GPR32:%vreg136
		updated: 10352B	%vreg132:sub_32<def,read-undef> = EORWrr %vreg141, %vreg139; GPR64:%vreg132 GPR32:%vreg141,%vreg139
	Success: %vreg136:sub_32 -> %vreg132
	Result = %vreg132 [10352r,10384r:0)  0@10352r
if.then.346:
if.then.351:
if.then.361:
if.then.366:
if.then.377:
if.then.382:
if.end.384:
12640B	%vreg339<def> = SUBREG_TO_REG 0, %vreg338, 15; GPR64:%vreg339 GPR32:%vreg338
	Considering merging to GPR64 with %vreg338 in %vreg339:sub_32
		RHS = %vreg338 [12624r,12640r:0)  0@12624r
		LHS = %vreg339 [12640r,12688r:0)  0@12640r
		merge %vreg339:0@12640r into %vreg338:0@12624r --> @12624r
		erased:	12640r	%vreg339<def> = SUBREG_TO_REG 0, %vreg338, 15; GPR64:%vreg339 GPR32:%vreg338
		updated: 12624B	%vreg339:sub_32<def,read-undef> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR64:%vreg339
	Success: %vreg338:sub_32 -> %vreg339
	Result = %vreg339 [12624r,12688r:0)  0@12624r
12976B	%vreg305<def> = SUBREG_TO_REG 0, %vreg304, 15; GPR64:%vreg305 GPR32:%vreg304
	Considering merging to GPR64 with %vreg304 in %vreg305:sub_32
		RHS = %vreg304 [12960r,12976r:0)  0@12960r
		LHS = %vreg305 [12976r,13024r:0)  0@12976r
		merge %vreg305:0@12976r into %vreg304:0@12960r --> @12960r
		erased:	12976r	%vreg305<def> = SUBREG_TO_REG 0, %vreg304, 15; GPR64:%vreg305 GPR32:%vreg304
		updated: 12960B	%vreg305:sub_32<def,read-undef> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR64:%vreg305
	Success: %vreg304:sub_32 -> %vreg305
	Result = %vreg305 [12960r,13024r:0)  0@12960r
3072B	%vreg649<def> = COPY %vreg652; GPR32:%vreg649,%vreg652
	Considering merging to GPR32 with %vreg652 in %vreg649
		RHS = %vreg652 [3056r,3072r:0)  0@3056r
		LHS = %vreg649 [3072r,3088r:0)  0@3072r
		merge %vreg649:0@3072r into %vreg652:0@3056r --> @3056r
		erased:	3072r	%vreg649<def> = COPY %vreg652; GPR32:%vreg649,%vreg652
		updated: 3056B	%vreg649<def> = EORWrr %vreg655, %vreg659; GPR32:%vreg649,%vreg655,%vreg659
	Success: %vreg652 -> %vreg649
	Result = %vreg649 [3056r,3088r:0)  0@3056r
4544B	%vreg767<def> = COPY %vreg770; GPR32:%vreg767,%vreg770
	Considering merging to GPR32 with %vreg770 in %vreg767
		RHS = %vreg770 [4528r,4544r:0)  0@4528r
		LHS = %vreg767 [4544r,4560r:0)  0@4544r
		merge %vreg767:0@4544r into %vreg770:0@4528r --> @4528r
		erased:	4544r	%vreg767<def> = COPY %vreg770; GPR32:%vreg767,%vreg770
		updated: 4528B	%vreg767<def> = EORWrr %vreg773, %vreg777; GPR32:%vreg767,%vreg773,%vreg777
	Success: %vreg770 -> %vreg767
	Result = %vreg767 [4528r,4560r:0)  0@4528r
6016B	%vreg885<def> = COPY %vreg888; GPR32:%vreg885,%vreg888
	Considering merging to GPR32 with %vreg888 in %vreg885
		RHS = %vreg888 [6000r,6016r:0)  0@6000r
		LHS = %vreg885 [6016r,6032r:0)  0@6016r
		merge %vreg885:0@6016r into %vreg888:0@6000r --> @6000r
		erased:	6016r	%vreg885<def> = COPY %vreg888; GPR32:%vreg885,%vreg888
		updated: 6000B	%vreg885<def> = EORWrr %vreg891, %vreg895; GPR32:%vreg885,%vreg891,%vreg895
	Success: %vreg888 -> %vreg885
	Result = %vreg885 [6000r,6032r:0)  0@6000r
7440B	%vreg1038<def> = COPY %vreg1041; GPR32:%vreg1038,%vreg1041
	Considering merging to GPR32 with %vreg1041 in %vreg1038
		RHS = %vreg1041 [7424r,7440r:0)  0@7424r
		LHS = %vreg1038 [7440r,7456r:0)  0@7440r
		merge %vreg1038:0@7440r into %vreg1041:0@7424r --> @7424r
		erased:	7440r	%vreg1038<def> = COPY %vreg1041; GPR32:%vreg1038,%vreg1041
		updated: 7424B	%vreg1038<def> = EORWrr %vreg1044, %vreg1048; GPR32:%vreg1038,%vreg1044,%vreg1048
	Success: %vreg1041 -> %vreg1038
	Result = %vreg1038 [7424r,7456r:0)  0@7424r
7824B	%vreg996<def> = COPY %vreg998; GPR32:%vreg996 GPR32sp:%vreg998
	Considering merging to GPR32common with %vreg998 in %vreg996
		RHS = %vreg998 [7808r,7824r:0)  0@7808r
		LHS = %vreg996 [7824r,7840r:0)  0@7824r
		merge %vreg996:0@7824r into %vreg998:0@7808r --> @7808r
		erased:	7824r	%vreg996<def> = COPY %vreg998; GPR32:%vreg996 GPR32sp:%vreg998
		updated: 7808B	%vreg996<def> = ANDWri %vreg1000, 7; GPR32common:%vreg996 GPR32:%vreg1000
	Success: %vreg998 -> %vreg996
	Result = %vreg996 [7808r,7840r:0)  0@7808r
2064B	%vreg593<def> = COPY %vreg595; GPR32:%vreg593,%vreg595
	Considering merging to GPR32 with %vreg595 in %vreg593
		RHS = %vreg595 [2048r,2064r:0)  0@2048r
		LHS = %vreg593 [2064r,2096r:0)  0@2064r
		merge %vreg593:0@2064r into %vreg595:0@2048r --> @2048r
		erased:	2064r	%vreg593<def> = COPY %vreg595; GPR32:%vreg593,%vreg595
		updated: 2048B	%vreg593<def> = LDRWui %vreg596, 16; mem:LD4[%k0] GPR32:%vreg593 GPR64common:%vreg596
	Success: %vreg595 -> %vreg593
	Result = %vreg593 [2048r,2096r:0)  0@2048r
2336B	%vreg563<def> = COPY %vreg565; GPR32:%vreg563 GPR32sp:%vreg565
	Considering merging to GPR32common with %vreg565 in %vreg563
		RHS = %vreg565 [2320r,2336r:0)  0@2320r
		LHS = %vreg563 [2336r,2352r:0)  0@2336r
		merge %vreg563:0@2336r into %vreg565:0@2320r --> @2320r
		erased:	2336r	%vreg563<def> = COPY %vreg565; GPR32:%vreg563 GPR32sp:%vreg565
		updated: 2320B	%vreg563<def> = ANDWri %vreg567, 7; GPR32common:%vreg563 GPR32:%vreg567
	Success: %vreg565 -> %vreg563
	Result = %vreg563 [2320r,2352r:0)  0@2320r
3808B	%vreg689<def> = COPY %vreg691; GPR32:%vreg689 GPR32sp:%vreg691
	Considering merging to GPR32common with %vreg691 in %vreg689
		RHS = %vreg691 [3792r,3808r:0)  0@3792r
		LHS = %vreg689 [3808r,3824r:0)  0@3808r
		merge %vreg689:0@3808r into %vreg691:0@3792r --> @3792r
		erased:	3808r	%vreg689<def> = COPY %vreg691; GPR32:%vreg689 GPR32sp:%vreg691
		updated: 3792B	%vreg689<def> = ANDWri %vreg693, 7; GPR32common:%vreg689 GPR32:%vreg693
	Success: %vreg691 -> %vreg689
	Result = %vreg689 [3792r,3824r:0)  0@3792r
5280B	%vreg807<def> = COPY %vreg809; GPR32:%vreg807 GPR32sp:%vreg809
	Considering merging to GPR32common with %vreg809 in %vreg807
		RHS = %vreg809 [5264r,5280r:0)  0@5264r
		LHS = %vreg807 [5280r,5296r:0)  0@5280r
		merge %vreg807:0@5280r into %vreg809:0@5264r --> @5264r
		erased:	5280r	%vreg807<def> = COPY %vreg809; GPR32:%vreg807 GPR32sp:%vreg809
		updated: 5264B	%vreg807<def> = ANDWri %vreg811, 7; GPR32common:%vreg807 GPR32:%vreg811
	Success: %vreg809 -> %vreg807
	Result = %vreg807 [5264r,5296r:0)  0@5264r
6704B	%vreg925<def> = COPY %vreg927; GPR32:%vreg925 GPR32sp:%vreg927
	Considering merging to GPR32common with %vreg927 in %vreg925
		RHS = %vreg927 [6688r,6704r:0)  0@6688r
		LHS = %vreg925 [6704r,6720r:0)  0@6704r
		merge %vreg925:0@6704r into %vreg927:0@6688r --> @6688r
		erased:	6704r	%vreg925<def> = COPY %vreg927; GPR32:%vreg925 GPR32sp:%vreg927
		updated: 6688B	%vreg925<def> = ANDWri %vreg929, 7; GPR32common:%vreg925 GPR32:%vreg929
	Success: %vreg927 -> %vreg925
	Result = %vreg925 [6688r,6720r:0)  0@6688r
10896B	%vreg192<def> = COPY %vreg193; GPR32:%vreg192,%vreg193
	Considering merging to GPR32 with %vreg193 in %vreg192
		RHS = %vreg193 [10880r,10896r:0)  0@10880r
		LHS = %vreg192 [10896r,10912r:0)  0@10896r
		merge %vreg192:0@10896r into %vreg193:0@10880r --> @10880r
		erased:	10896r	%vreg192<def> = COPY %vreg193; GPR32:%vreg192,%vreg193
		updated: 10880B	%vreg192<def> = LDRWui <fi#7>, 0; mem:LD4[FixedStack7] GPR32:%vreg192
	Success: %vreg193 -> %vreg192
	Result = %vreg192 [10880r,10912r:0)  0@10880r
11088B	%vreg172<def> = COPY %vreg174; GPR32:%vreg172 GPR32sp:%vreg174
	Considering merging to GPR32common with %vreg174 in %vreg172
		RHS = %vreg174 [11072r,11088r:0)  0@11072r
		LHS = %vreg172 [11088r,11104r:0)  0@11088r
		merge %vreg172:0@11088r into %vreg174:0@11072r --> @11072r
		erased:	11088r	%vreg172<def> = COPY %vreg174; GPR32:%vreg172 GPR32sp:%vreg174
		updated: 11072B	%vreg172<def> = ANDWri %vreg175, 7; GPR32common:%vreg172 GPR32:%vreg175
	Success: %vreg174 -> %vreg172
	Result = %vreg172 [11072r,11104r:0)  0@11072r
11664B	%vreg212<def> = COPY %vreg214; GPR32:%vreg212 GPR32sp:%vreg214
	Considering merging to GPR32common with %vreg214 in %vreg212
		RHS = %vreg214 [11648r,11664r:0)  0@11648r
		LHS = %vreg212 [11664r,11680r:0)  0@11664r
		merge %vreg212:0@11664r into %vreg214:0@11648r --> @11648r
		erased:	11664r	%vreg212<def> = COPY %vreg214; GPR32:%vreg212 GPR32sp:%vreg214
		updated: 11648B	%vreg212<def> = ANDWri %vreg215, 7; GPR32common:%vreg212 GPR32:%vreg215
	Success: %vreg214 -> %vreg212
	Result = %vreg212 [11648r,11680r:0)  0@11648r
12240B	%vreg251<def> = COPY %vreg253; GPR32:%vreg251 GPR32sp:%vreg253
	Considering merging to GPR32common with %vreg253 in %vreg251
		RHS = %vreg253 [12224r,12240r:0)  0@12224r
		LHS = %vreg251 [12240r,12256r:0)  0@12240r
		merge %vreg251:0@12240r into %vreg253:0@12224r --> @12224r
		erased:	12240r	%vreg251<def> = COPY %vreg253; GPR32:%vreg251 GPR32sp:%vreg253
		updated: 12224B	%vreg251<def> = ANDWri %vreg254, 7; GPR32common:%vreg251 GPR32:%vreg254
	Success: %vreg253 -> %vreg251
	Result = %vreg251 [12224r,12256r:0)  0@12224r
12784B	%vreg322<def> = COPY %vreg324; GPR32:%vreg322 GPR32sp:%vreg324
	Considering merging to GPR32common with %vreg324 in %vreg322
		RHS = %vreg324 [12768r,12784r:0)  0@12768r
		LHS = %vreg322 [12784r,12800r:0)  0@12784r
		merge %vreg322:0@12784r into %vreg324:0@12768r --> @12768r
		erased:	12784r	%vreg322<def> = COPY %vreg324; GPR32:%vreg322 GPR32sp:%vreg324
		updated: 12768B	%vreg322<def> = ANDWri %vreg325, 7; GPR32common:%vreg322 GPR32:%vreg325
	Success: %vreg324 -> %vreg322
	Result = %vreg322 [12768r,12800r:0)  0@12768r
13120B	%vreg288<def> = COPY %vreg290; GPR32:%vreg288 GPR32sp:%vreg290
	Considering merging to GPR32common with %vreg290 in %vreg288
		RHS = %vreg290 [13104r,13120r:0)  0@13104r
		LHS = %vreg288 [13120r,13136r:0)  0@13120r
		merge %vreg288:0@13120r into %vreg290:0@13104r --> @13104r
		erased:	13120r	%vreg288<def> = COPY %vreg290; GPR32:%vreg288 GPR32sp:%vreg290
		updated: 13104B	%vreg288<def> = ANDWri %vreg291, 7; GPR32common:%vreg288 GPR32:%vreg291
	Success: %vreg290 -> %vreg288
	Result = %vreg288 [13104r,13136r:0)  0@13104r
return_notr:
return:
14240B	%X0<def> = COPY %vreg1133; GPR64:%vreg1133
	Considering merging %vreg1133 with %X0
	Can only merge into reserved registers.
14256B	%X1<def> = COPY %vreg11; GPR64:%vreg11
	Considering merging %vreg11 with %X1
	Can only merge into reserved registers.
14384B	%W0<def> = COPY %vreg1134; GPR32:%vreg1134
	Considering merging %vreg1134 with %W0
	Can only merge into reserved registers.
if.end.413:
entry:
16B	%vreg11<def> = COPY %LR; GPR64:%vreg11
	Considering merging %vreg11 with %LR
	Can only merge into reserved registers.
32B	%vreg0<def> = COPY %X0; GPR64:%vreg0
	Considering merging %vreg0 with %X0
	Can only merge into reserved registers.
144B	%X0<def> = COPY %vreg9; GPR64all:%vreg9
	Considering merging %vreg9 with %X0
	Can only merge into reserved registers.
160B	%X1<def> = COPY %vreg10; GPR64all:%vreg10
	Considering merging %vreg10 with %X1
	Can only merge into reserved registers.
if.then:
if.then.3:
if.then.29:
if.then.36:
if.else:
if.then.297:
if.then.316:
if.then.330:
if.then.334:
if.then.409:
if.end.425:
14368B	%vreg1132<def,dead> = COPY %vreg1134; GPR32all:%vreg1132 GPR32:%vreg1134
	Copy is dead.
Deleting dead def 14368r	%vreg1132<def,dead> = COPY %vreg1134; GPR32all:%vreg1132 GPR32:%vreg1134
Shrink: %vreg1134 [14352r,14384r:0)  0@14352r
Shrunk: %vreg1134 [14352r,14384r:0)  0@14352r
48B	%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
	Considering merging to GPR64 with %vreg0 in %vreg1
		RHS = %vreg0 [32r,48r:0)  0@32r
		LHS = %vreg1 [48r,256r:0)  0@48r
		merge %vreg1:0@48r into %vreg0:0@32r --> @32r
		erased:	48r	%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
		updated: 32B	%vreg1<def> = COPY %X0; GPR64:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [32r,256r:0)  0@32r
96B	%vreg9<def> = COPY %vreg8; GPR64all:%vreg9 GPR64sp:%vreg8
	Considering merging to GPR64sp with %vreg8 in %vreg9
		RHS = %vreg8 [80r,96r:0)  0@80r
		LHS = %vreg9 [96r,144r:0)  0@96r
		merge %vreg9:0@96r into %vreg8:0@80r --> @80r
		erased:	96r	%vreg9<def> = COPY %vreg8; GPR64all:%vreg9 GPR64sp:%vreg8
		updated: 80B	%vreg9<def> = ADDXri %vreg7, <ga:@unRLE_obuf_to_output_FAST>[TF=34], 0; GPR64sp:%vreg9 GPR64common:%vreg7
	Success: %vreg8 -> %vreg9
	Result = %vreg9 [80r,144r:0)  0@80r
112B	%vreg10<def> = COPY %vreg11; GPR64all:%vreg10 GPR64:%vreg11
	Considering merging to GPR64 with %vreg11 in %vreg10
		RHS = %vreg11 [16r,14256r:0)  0@16r
		LHS = %vreg10 [112r,160r:0)  0@112r
		merge %vreg10:0@112r into %vreg11:0@16r --> @16r
		erased:	112r	%vreg10<def> = COPY %vreg11; GPR64all:%vreg10 GPR64:%vreg11
		updated: 16B	%vreg10<def> = COPY %LR; GPR64:%vreg10
		updated: 14256B	%X1<def> = COPY %vreg10; GPR64:%vreg10
	Success: %vreg11 -> %vreg10
	Result = %vreg10 [16r,14256r:0)  0@16r
2896B	%vreg658<def> = COPY %WZR; GPR32:%vreg658
	Considering merging %vreg658 with %WZR
		RHS = %vreg658 [2896r,3024r:0)  0@2896r
		Interference: WZR
	Interference!
4368B	%vreg776<def> = COPY %WZR; GPR32:%vreg776
	Considering merging %vreg776 with %WZR
		RHS = %vreg776 [4368r,4496r:0)  0@4368r
		Interference: WZR
	Interference!
5840B	%vreg894<def> = COPY %WZR; GPR32:%vreg894
	Considering merging %vreg894 with %WZR
		RHS = %vreg894 [5840r,5968r:0)  0@5840r
		Interference: WZR
	Interference!
7264B	%vreg1047<def> = COPY %WZR; GPR32:%vreg1047
	Considering merging %vreg1047 with %WZR
		RHS = %vreg1047 [7264r,7392r:0)  0@7264r
		Interference: WZR
	Interference!
8416B	%vreg1102<def> = COPY %WZR; GPR32:%vreg1102
	Considering merging %vreg1102 with %WZR
		RHS = %vreg1102 [8416r,8544r:0)  0@8416r
		Interference: WZR
	Interference!
14256B	%X1<def> = COPY %vreg10; GPR64:%vreg10
	Considering merging %vreg10 with %X1
	Can only merge into reserved registers.
144B	%X0<def> = COPY %vreg9; GPR64sp:%vreg9
	Considering merging %vreg9 with %X0
	Can only merge into reserved registers.
160B	%X1<def> = COPY %vreg10; GPR64:%vreg10
	Considering merging %vreg10 with %X1
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
W30 [0B,16r:0)[176r,176d:4)[224e,224d:2)[14272r,14272d:3)[14320e,14320d:1)  0@0B-phi 1@14320e 2@224e 3@14272r 4@176r
WZR [1664r,1664d:17)[1872r,1872d:16)[2752r,2752d:15)[3008r,3008d:13)[3280r,3280d:14)[3408r,3408d:12)[4224r,4224d:11)[4480r,4480d:9)[4752r,4752d:10)[4880r,4880d:8)[5696r,5696d:7)[5952r,5952d:5)[6224r,6224d:6)[6352r,6352d:4)[7120r,7120d:3)[7376r,7376d:2)[8272r,8272d:1)[8528r,8528d:0)[9344r,9344d:28)[9520r,9520d:27)[10640r,10640d:26)[10784r,10784d:25)[11248r,11248d:24)[11392r,11392d:23)[11824r,11824d:22)[11936r,11936d:21)[12400r,12400d:20)[12512r,12512d:19)[13552r,13552d:18)  0@8528r 1@8272r 2@7376r 3@7120r 4@6352r 5@5952r 6@6224r 7@5696r 8@4880r 9@4480r 10@4752r 11@4224r 12@3408r 13@3008r 14@3280r 15@2752r 16@1872r 17@1664r 18@13552r 19@12512r 20@12400r 21@11936r 22@11824r 23@11392r 24@11248r 25@10784r 26@10640r 27@9520r 28@9344r
W0 [0B,32r:0)[144r,176r:3)[14240r,14272r:2)[14384r,14400r:1)  0@0B-phi 1@14384r 2@14240r 3@144r
%vreg1 [32r,256r:0)  0@32r
%vreg3 [304r,320r:0)  0@304r
%vreg5 [288r,304r:0)  0@288r
%vreg6 [272r,288r:0)  0@272r
%vreg7 [64r,80r:0)  0@64r
%vreg9 [80r,144r:0)  0@80r
%vreg10 [16r,14256r:0)  0@16r
%vreg14 [9280r,9296r:0)  0@9280r
%vreg16 [9232r,9248r:0)  0@9232r
%vreg17 [9248r,9264r:0)  0@9248r
%vreg18 [9264r,9280r:0)  0@9264r
%vreg19 [9216r,9248r:0)  0@9216r
%vreg21 [9184r,9200r:0)  0@9184r
%vreg24 [9152r,9168r:0)  0@9152r
%vreg26 [9136r,9152r:0)  0@9136r
%vreg27 [9120r,9136r:0)  0@9120r
%vreg30 [9088r,9104r:0)  0@9088r
%vreg32 [9072r,9088r:0)  0@9072r
%vreg33 [9056r,9072r:0)  0@9056r
%vreg36 [9024r,9040r:0)  0@9024r
%vreg37 [9008r,9024r:0)  0@9008r
%vreg40 [8976r,8992r:0)  0@8976r
%vreg41 [8960r,8976r:0)  0@8960r
%vreg44 [8928r,8944r:0)  0@8928r
%vreg45 [8912r,8928r:0)  0@8912r
%vreg48 [8880r,8896r:0)  0@8880r
%vreg49 [8864r,8880r:0)  0@8864r
%vreg52 [8832r,8848r:0)  0@8832r
%vreg53 [8816r,8832r:0)  0@8816r
%vreg56 [8784r,8800r:0)  0@8784r
%vreg57 [8768r,8784r:0)  0@8768r
%vreg60 [8736r,8752r:0)  0@8736r
%vreg61 [8720r,8736r:0)  0@8720r
%vreg63 [9328r,9344r:0)  0@9328r
%vreg65 [9424r,9440r:0)  0@9424r
%vreg67 [9504r,9520r:0)  0@9504r
%vreg70 [10000r,10016r:0)  0@10000r
%vreg71 [9984r,10000r:0)  0@9984r
%vreg74 [9952r,9968r:0)  0@9952r
%vreg75 [9936r,9952r:0)  0@9936r
%vreg78 [9904r,9920r:0)  0@9904r
%vreg79 [9888r,9904r:0)  0@9888r
%vreg83 [9856r,9872r:0)  0@9856r
%vreg85 [9840r,9856r:0)  0@9840r
%vreg86 [9600r,9616r:0)  0@9600r
%vreg87 [9616r,9824r:0)  0@9616r
%vreg89 [9792r,9808r:0)  0@9792r
%vreg90 [9808r,9824r:0)  0@9808r
%vreg91 [9824r,9840r:0)  0@9824r
%vreg93 [9744r,9776r:0)  0@9744r
%vreg94 [9776r,9808r:0)  0@9776r
%vreg100 [9728r,9744r:0)  0@9728r
%vreg102 [9712r,9744r:0)  0@9712r
%vreg103 [9696r,9712r:0)  0@9696r
%vreg104 [9680r,9856r:0)  0@9680r
%vreg107 [9648r,9664r:0)  0@9648r
%vreg108 [9632r,9664r:0)  0@9632r
%vreg110 [10096r,10112r:0)  0@10096r
%vreg113 [10560r,10576r:0)  0@10560r
%vreg114 [10544r,10560r:0)  0@10544r
%vreg117 [10512r,10528r:0)  0@10512r
%vreg118 [10496r,10512r:0)  0@10496r
%vreg122 [10464r,10480r:0)  0@10464r
%vreg124 [10448r,10464r:0)  0@10448r
%vreg125 [10208r,10224r:0)  0@10208r
%vreg126 [10224r,10432r:0)  0@10224r
%vreg128 [10400r,10416r:0)  0@10400r
%vreg129 [10416r,10432r:0)  0@10416r
%vreg130 [10432r,10448r:0)  0@10432r
%vreg132 [10352r,10384r:0)  0@10352r
%vreg133 [10384r,10416r:0)  0@10384r
%vreg139 [10336r,10352r:0)  0@10336r
%vreg141 [10320r,10352r:0)  0@10320r
%vreg142 [10304r,10320r:0)  0@10304r
%vreg143 [10288r,10464r:0)  0@10288r
%vreg146 [10256r,10272r:0)  0@10256r
%vreg147 [10240r,10272r:0)  0@10240r
%vreg150 [10624r,10640r:0)  0@10624r
%vreg151 [10608r,10640r:0)  0@10608r
%vreg154 [10768r,10784r:0)  0@10768r
%vreg155 [10752r,10784r:0)  0@10752r
%vreg158 [11232r,11248r:0)  0@11232r
%vreg161 [11216r,11248r:0)  0@11216r
%vreg164 [11184r,11200r:0)  0@11184r
%vreg165 [11168r,11184r:0)  0@11168r
%vreg168 [11136r,11152r:0)  0@11136r
%vreg169 [11120r,11136r:0)  0@11120r
%vreg172 [11072r,11104r:0)  0@11072r
%vreg175 [11056r,11072r:0)  0@11056r
%vreg178 [11024r,11040r:0)  0@11024r
%vreg181 [10976r,10992r:0)  0@10976r
%vreg182 [10992r,11008r:0)  0@10992r
%vreg183 [11008r,11024r:0)  0@11008r
%vreg184 [10960r,11008r:0)  0@10960r
%vreg189 [10928r,10992r:0)  0@10928r
%vreg192 [10880r,10912r:0)  0@10880r
%vreg196 [11376r,11392r:0)  0@11376r
%vreg197 [11360r,11392r:0)  0@11360r
%vreg200 [11808r,11824r:0)  0@11808r
%vreg201 [11792r,11824r:0)  0@11792r
%vreg204 [11760r,11776r:0)  0@11760r
%vreg205 [11744r,11760r:0)  0@11744r
%vreg208 [11712r,11728r:0)  0@11712r
%vreg209 [11696r,11712r:0)  0@11696r
%vreg212 [11648r,11680r:0)  0@11648r
%vreg215 [11632r,11648r:0)  0@11632r
%vreg218 [11600r,11616r:0)  0@11600r
%vreg221 [11552r,11568r:0)  0@11552r
%vreg222 [11568r,11584r:0)  0@11568r
%vreg223 [11584r,11600r:0)  0@11584r
%vreg224 [11536r,11584r:0)  0@11536r
%vreg229 [11504r,11568r:0)  0@11504r
%vreg230 [11472r,11488r:0)  0@11472r
%vreg233 [11920r,11936r:0)  0@11920r
%vreg236 [11904r,11936r:0)  0@11904r
%vreg239 [12384r,12400r:0)  0@12384r
%vreg240 [12368r,12400r:0)  0@12368r
%vreg243 [12336r,12352r:0)  0@12336r
%vreg244 [12320r,12336r:0)  0@12320r
%vreg247 [12288r,12304r:0)  0@12288r
%vreg248 [12272r,12288r:0)  0@12272r
%vreg251 [12224r,12256r:0)  0@12224r
%vreg254 [12208r,12224r:0)  0@12208r
%vreg257 [12176r,12192r:0)  0@12176r
%vreg260 [12128r,12144r:0)  0@12128r
%vreg261 [12144r,12160r:0)  0@12144r
%vreg262 [12160r,12176r:0)  0@12160r
%vreg263 [12112r,12160r:0)  0@12112r
%vreg268 [12080r,12144r:0)  0@12080r
%vreg269 [12048r,12064r:0)  0@12048r
%vreg272 [12496r,12512r:0)  0@12496r
%vreg275 [12480r,12512r:0)  0@12480r
%vreg278 [13232r,13248r:0)  0@13232r
%vreg279 [13216r,13232r:0)  0@13216r
%vreg282 [13184r,13200r:0)  0@13184r
%vreg283 [13168r,13184r:0)  0@13168r
%vreg286 [13136r,13152r:0)  0@13136r
%vreg288 [13104r,13136r:0)  0@13104r
%vreg291 [13088r,13104r:0)  0@13088r
%vreg294 [13056r,13072r:0)  0@13056r
%vreg297 [13008r,13024r:0)  0@13008r
%vreg298 [13024r,13040r:0)  0@13024r
%vreg299 [13040r,13056r:0)  0@13040r
%vreg300 [12992r,13040r:0)  0@12992r
%vreg305 [12960r,13024r:0)  0@12960r
%vreg308 [12928r,12944r:0)  0@12928r
%vreg311 [12912r,12928r:0)  0@12912r
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%vreg1048 [7392r,7424r:0)  0@7392r
%vreg1050 [7360r,7376r:0)  0@7360r
%vreg1051 [7344r,7360r:0)  0@7344r
%vreg1055 [7312r,7328r:0)  0@7312r
%vreg1056 [7296r,7312r:0)  0@7296r
%vreg1057 [7280r,7328r:0)  0@7280r
%vreg1060 [8256r,8272r:0)  0@8256r
%vreg1061 [8240r,8256r:0)  0@8240r
%vreg1065 [8208r,8224r:0)  0@8208r
%vreg1066 [8192r,8208r:0)  0@8192r
%vreg1067 [8176r,8224r:0)  0@8176r
%vreg1070 [8144r,8160r:0)  0@8144r
%vreg1072 [8128r,8160r:0)  0@8128r
%vreg1073 [8016r,8032r:0)  0@8016r
%vreg1074 [8032r,8112r:0)  0@8032r
%vreg1076 [8080r,8096r:0)  0@8080r
%vreg1077 [8096r,8112r:0)  0@8096r
%vreg1078 [8112r,8128r:0)  0@8112r
%vreg1083 [8064r,8096r:0)  0@8064r
%vreg1084 [8048r,8064r:0)  0@8048r
%vreg1086 [8320r,8336r:0)  0@8320r
%vreg1090 [8656r,8672r:0)  0@8656r
%vreg1091 [8640r,8656r:0)  0@8640r
%vreg1092 [8624r,8672r:0)  0@8624r
%vreg1097 [8592r,8608r:0)  0@8592r
%vreg1098 [8576r,8592r:0)  0@8576r
%vreg1099 [8560r,8608r:0)  0@8560r
%vreg1101 [8400r,8544r:0)  0@8400r
%vreg1102 [8416r,8544r:0)  0@8416r
%vreg1103 [8544r,8592r:0)  0@8544r
%vreg1105 [8512r,8528r:0)  0@8512r
%vreg1106 [8496r,8512r:0)  0@8496r
%vreg1110 [8464r,8480r:0)  0@8464r
%vreg1111 [8448r,8464r:0)  0@8448r
%vreg1112 [8432r,8480r:0)  0@8432r
%vreg1115 [6416r,6432r:0)  0@6416r
%vreg1118 [6400r,6432r:0)  0@6400r
%vreg1121 [4944r,4960r:0)  0@4944r
%vreg1124 [4928r,4960r:0)  0@4928r
%vreg1127 [3472r,3488r:0)  0@3472r
%vreg1130 [3456r,3488r:0)  0@3456r
%vreg1131 [1920r,1936r:0)  0@1920r
%vreg1133 [14224r,14240r:0)  0@14224r
%vreg1134 [14352r,14384r:0)  0@14352r
RegMasks: 176r 14272r
********** MACHINEINSTRS **********
# Machine code for function unRLE_obuf_to_output_FAST: Post SSA
Frame Objects:
  fi#0: size=1, align=1, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=1, align=1, at location [SP]
  fi#3: size=4, align=4, at location [SP]
  fi#4: size=1, align=1, at location [SP]
  fi#5: size=4, align=4, at location [SP]
  fi#6: size=4, align=4, at location [SP]
  fi#7: size=4, align=4, at location [SP]
  fi#8: size=8, align=8, at location [SP]
  fi#9: size=4, align=4, at location [SP]
  fi#10: size=8, align=8, at location [SP]
  fi#11: size=4, align=4, at location [SP]
  fi#12: size=4, align=4, at location [SP]
  fi#13: size=4, align=4, at location [SP]
  fi#14: size=4, align=4, at location [SP]
Function Live Ins: %X0 in %vreg0, %LR in %vreg11

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %LR
16B		%vreg10<def> = COPY %LR; GPR64:%vreg10
32B		%vreg1<def> = COPY %X0; GPR64:%vreg1
64B		%vreg7<def> = ADRP <ga:@unRLE_obuf_to_output_FAST>[TF=1]; GPR64common:%vreg7
80B		%vreg9<def> = ADDXri %vreg7, <ga:@unRLE_obuf_to_output_FAST>[TF=34], 0; GPR64sp:%vreg9 GPR64common:%vreg7
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		%X0<def> = COPY %vreg9; GPR64sp:%vreg9
160B		%X1<def> = COPY %vreg10; GPR64:%vreg10
176B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
224B		STACKMAP 0, 0, 0, <fi#12>, 0, 0, <fi#3>, 0, 0, <fi#7>, 0, 0, <fi#6>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#9>, 0, 0, <fi#8>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, %vreg1, 0, <fi#1>, 0, 0, <fi#13>, 0, 0, <fi#14>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack12](align=4) LD8[FixedStack3](align=4) LD8[FixedStack7](align=4) LD8[FixedStack6](align=4) LD8[FixedStack4](align=1) LD8[FixedStack5](align=4) LD8[FixedStack9](align=4) LD8[FixedStack8] LD8[FixedStack11](align=4) LD8[FixedStack10] LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1] LD8[FixedStack13](align=4) LD8[FixedStack14](align=4) GPR64:%vreg1
240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
256B		STRXui %vreg1, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg1
272B		%vreg6<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg6
288B		%vreg5<def> = LDRBBui %vreg6, 20; mem:LD1[%blockRandomised] GPR32:%vreg5 GPR64common:%vreg6
304B		%vreg3<def> = UBFMWri %vreg5, 0, 7; GPR32:%vreg3,%vreg5
320B		CBZW %vreg3, <BB#47>; GPR32:%vreg3
	    Successors according to CFG: BB#47 BB#1

336B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
352B		B <BB#2>
	    Successors according to CFG: BB#2

368B	BB#2: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#1 BB#46 BB#37 BB#35 BB#29 BB#27 BB#21 BB#19
384B		B <BB#3>
	    Successors according to CFG: BB#3

400B	BB#3: derived from LLVM BB %while.body.2
	    Predecessors according to CFG: BB#2 BB#9
416B		%vreg435<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg435
432B		%vreg434<def> = LDRXui %vreg435, 0; mem:LD8[%strm] GPR64common:%vreg434,%vreg435
448B		%vreg432<def> = LDRWui %vreg434, 8; mem:LD4[%avail_out] GPR32:%vreg432 GPR64common:%vreg434
464B		CBNZW %vreg432, <BB#5>; GPR32:%vreg432
	    Successors according to CFG: BB#5 BB#4

480B	BB#4: derived from LLVM BB %if.then.3
	    Predecessors according to CFG: BB#3
496B		STRBBui %WZR, <fi#0>, 0; mem:ST1[FixedStack0]
512B		B <BB#80>
	    Successors according to CFG: BB#80

528B	BB#5: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#3
544B		%vreg439<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg439
560B		%vreg438<def> = LDRWui %vreg439, 4; mem:LD4[%state_out_len] GPR32:%vreg438 GPR64common:%vreg439
576B		CBNZW %vreg438, <BB#7>; GPR32:%vreg438
	    Successors according to CFG: BB#7 BB#6

592B	BB#6: derived from LLVM BB %if.then.5
	    Predecessors according to CFG: BB#5
608B		B <BB#10>
	    Successors according to CFG: BB#10

624B	BB#7: derived from LLVM BB %if.end.6
	    Predecessors according to CFG: BB#5
640B		%vreg484<def> = ADRP <ga:@BZ2_crc32Table>[TF=1]; GPR64common:%vreg484
656B		%vreg485<def> = ADDXri %vreg484, <ga:@BZ2_crc32Table>[TF=34], 0; GPR64common:%vreg485,%vreg484
672B		%vreg518<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg518
688B		%vreg517<def> = LDRBBui %vreg518, 12; mem:LD1[%state_out_ch] GPR32:%vreg517 GPR64common:%vreg518
704B		%vreg515<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg515
720B		%vreg514<def> = LDRXui %vreg515, 0; mem:LD8[%strm7] GPR64common:%vreg514,%vreg515
736B		%vreg512<def> = LDRXui %vreg514, 3; mem:LD8[%next_out] GPR64common:%vreg512,%vreg514
752B		STRBBui %vreg517, %vreg512, 0; mem:ST1[%11] GPR32:%vreg517 GPR64common:%vreg512
768B		%vreg508<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg508
784B		%vreg507<def> = LDRWui %vreg508, 796; mem:LD4[%calculatedBlockCRC] GPR32:%vreg507 GPR64common:%vreg508
800B		%vreg505<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg505
816B		%vreg504<def> = LDRWui %vreg505, 796; mem:LD4[%calculatedBlockCRC8] GPR32:%vreg504 GPR64common:%vreg505
832B		%vreg502<def> = UBFMWri %vreg504, 24, 31; GPR32:%vreg502,%vreg504
848B		%vreg500<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg500
864B		%vreg499<def> = LDRBBui %vreg500, 12; mem:LD1[%state_out_ch9] GPR32:%vreg499 GPR64common:%vreg500
880B		%vreg491:sub_32<def,read-undef> = EORWrr %vreg502, %vreg499; GPR64:%vreg491 GPR32:%vreg502,%vreg499
912B		%vreg492<def> = UBFMXri %vreg491, 0, 31; GPR64:%vreg492,%vreg491
928B		%vreg487<def> = MOVi64imm 4; GPR64:%vreg487
944B		%vreg488<def> = MADDXrrr %vreg492, %vreg487, %XZR; GPR64:%vreg488,%vreg492,%vreg487
960B		%vreg489<def> = ADDXrr %vreg485, %vreg488; GPR64common:%vreg489,%vreg485 GPR64:%vreg488
976B		%vreg483<def> = LDRWui %vreg489, 0; mem:LD4[%arrayidx] GPR32:%vreg483 GPR64common:%vreg489
992B		%vreg481<def> = EORWrs %vreg483, %vreg507, 8; GPR32:%vreg481,%vreg483,%vreg507
1008B		%vreg478<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg478
1024B		STRWui %vreg481, %vreg478, 796; mem:ST4[%calculatedBlockCRC11] GPR32:%vreg481 GPR64common:%vreg478
1040B		%vreg475<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg475
1056B		%vreg474<def> = LDRWui %vreg475, 4; mem:LD4[%state_out_len12] GPR32common:%vreg474 GPR64common:%vreg475
1072B		%vreg473<def> = SUBWri %vreg474, 1, 0; GPR32common:%vreg473,%vreg474
1088B		STRWui %vreg473, %vreg475, 4; mem:ST4[%state_out_len12] GPR32common:%vreg473 GPR64common:%vreg475
1104B		%vreg469<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg469
1120B		%vreg468<def> = LDRXui %vreg469, 0; mem:LD8[%strm13] GPR64common:%vreg468,%vreg469
1136B		%vreg466<def> = LDRXui %vreg468, 3; mem:LD8[%next_out14] GPR64common:%vreg466,%vreg468
1152B		%vreg465<def> = ADDXri %vreg466, 1, 0; GPR64common:%vreg465,%vreg466
1168B		STRXui %vreg465, %vreg468, 3; mem:ST8[%next_out14] GPR64common:%vreg465,%vreg468
1184B		%vreg461<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg461
1200B		%vreg460<def> = LDRXui %vreg461, 0; mem:LD8[%strm15] GPR64common:%vreg460,%vreg461
1216B		%vreg458<def> = LDRWui %vreg460, 8; mem:LD4[%avail_out16] GPR32common:%vreg458 GPR64common:%vreg460
1232B		%vreg457<def> = SUBWri %vreg458, 1, 0; GPR32common:%vreg457,%vreg458
1248B		STRWui %vreg457, %vreg460, 8; mem:ST4[%avail_out16] GPR32common:%vreg457 GPR64common:%vreg460
1264B		%vreg453<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg453
1280B		%vreg452<def> = LDRXui %vreg453, 0; mem:LD8[%strm18] GPR64common:%vreg452,%vreg453
1296B		%vreg450<def> = LDRWui %vreg452, 9; mem:LD4[%total_out_lo32] GPR32common:%vreg450 GPR64common:%vreg452
1312B		%vreg449<def> = ADDWri %vreg450, 1, 0; GPR32common:%vreg449,%vreg450
1328B		STRWui %vreg449, %vreg452, 9; mem:ST4[%total_out_lo32] GPR32common:%vreg449 GPR64common:%vreg452
1344B		%vreg445<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg445
1360B		%vreg444<def> = LDRXui %vreg445, 0; mem:LD8[%strm19] GPR64common:%vreg444,%vreg445
1376B		%vreg442<def> = LDRWui %vreg444, 9; mem:LD4[%total_out_lo3220] GPR32:%vreg442 GPR64common:%vreg444
1392B		CBNZW %vreg442, <BB#9>; GPR32:%vreg442
	    Successors according to CFG: BB#9 BB#8

1408B	BB#8: derived from LLVM BB %if.then.23
	    Predecessors according to CFG: BB#7
1424B		%vreg526<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg526
1440B		%vreg525<def> = LDRXui %vreg526, 0; mem:LD8[%strm24] GPR64common:%vreg525,%vreg526
1456B		%vreg523<def> = LDRWui %vreg525, 10; mem:LD4[%total_out_hi32] GPR32common:%vreg523 GPR64common:%vreg525
1472B		%vreg522<def> = ADDWri %vreg523, 1, 0; GPR32common:%vreg522,%vreg523
1488B		STRWui %vreg522, %vreg525, 10; mem:ST4[%total_out_hi32] GPR32common:%vreg522 GPR64common:%vreg525
	    Successors according to CFG: BB#9

1504B	BB#9: derived from LLVM BB %if.end.26
	    Predecessors according to CFG: BB#7 BB#8
1520B		B <BB#3>
	    Successors according to CFG: BB#3

1536B	BB#10: derived from LLVM BB %while.end
	    Predecessors according to CFG: BB#6
1552B		%vreg538<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg538
1568B		%vreg537<def> = LDRWui %vreg538, 273; mem:LD4[%nblock_used] GPR32:%vreg537 GPR64common:%vreg538
1584B		%vreg535<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg535
1600B		%vreg532<def> = MOVi64imm 64080; GPR64:%vreg532
1616B		%vreg533<def> = ADDXrr %vreg535, %vreg532; GPR64common:%vreg533 GPR64:%vreg535,%vreg532
1632B		%vreg534<def> = LDRWui %vreg533, 0; mem:LD4[%save_nblock] GPR32common:%vreg534 GPR64common:%vreg533
1648B		%vreg530<def> = ADDWri %vreg534, 1, 0; GPR32common:%vreg530,%vreg534
1664B		%WZR<def> = SUBSWrr %vreg537, %vreg530, %NZCV<imp-def>; GPR32:%vreg537 GPR32common:%vreg530
1680B		Bcc 1, <BB#12>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#12 BB#11

1696B	BB#11: derived from LLVM BB %if.then.29
	    Predecessors according to CFG: BB#10
1712B		STRBBui %WZR, <fi#0>, 0; mem:ST1[FixedStack0]
1728B		B <BB#80>
	    Successors according to CFG: BB#80

1744B	BB#12: derived from LLVM BB %if.end.30
	    Predecessors according to CFG: BB#10
1760B		%vreg550<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg550
1776B		%vreg549<def> = LDRWui %vreg550, 273; mem:LD4[%nblock_used31] GPR32:%vreg549 GPR64common:%vreg550
1792B		%vreg547<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg547
1808B		%vreg544<def> = MOVi64imm 64080; GPR64:%vreg544
1824B		%vreg545<def> = ADDXrr %vreg547, %vreg544; GPR64common:%vreg545 GPR64:%vreg547,%vreg544
1840B		%vreg546<def> = LDRWui %vreg545, 0; mem:LD4[%save_nblock32] GPR32common:%vreg546 GPR64common:%vreg545
1856B		%vreg542<def> = ADDWri %vreg546, 1, 0; GPR32common:%vreg542,%vreg546
1872B		%WZR<def> = SUBSWrr %vreg549, %vreg542, %NZCV<imp-def>; GPR32:%vreg549 GPR32common:%vreg542
1888B		Bcc 13, <BB#14>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#14 BB#13

1904B	BB#13: derived from LLVM BB %if.then.36
	    Predecessors according to CFG: BB#12
1920B		%vreg1131<def> = MOVi32imm 1; GPR32:%vreg1131
1936B		STRBBui %vreg1131, <fi#0>, 0; mem:ST1[FixedStack0] GPR32:%vreg1131
1952B		B <BB#80>
	    Successors according to CFG: BB#80

1968B	BB#14: derived from LLVM BB %if.end.37
	    Predecessors according to CFG: BB#12
1984B		%vreg597<def> = MOVi32imm 1; GPR32:%vreg597
2000B		%vreg599<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg599
2016B		STRWui %vreg597, %vreg599, 4; mem:ST4[%state_out_len38] GPR32:%vreg597 GPR64common:%vreg599
2032B		%vreg596<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg596
2048B		%vreg593<def> = LDRWui %vreg596, 16; mem:LD4[%k0] GPR32:%vreg593 GPR64common:%vreg596
2080B		%vreg591<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg591
2096B		STRBBui %vreg593, %vreg591, 12; mem:ST1[%state_out_ch40] GPR32:%vreg593 GPR64common:%vreg591
2112B		%vreg588<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg588
2128B		%vreg587:sub_32<def,read-undef> = LDRWui %vreg588, 15; mem:LD4[%tPos] GPR64:%vreg587 GPR64common:%vreg588
2160B		%vreg581<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg581
2176B		%vreg580<def> = LDRXui %vreg581, 394; mem:LD8[%tt] GPR64:%vreg580 GPR64common:%vreg581
2192B		%vreg576<def> = MOVi64imm 4; GPR64:%vreg576
2208B		%vreg577<def> = MADDXrrr %vreg587, %vreg576, %XZR; GPR64:%vreg577,%vreg587,%vreg576
2224B		%vreg578<def> = ADDXrr %vreg580, %vreg577; GPR64common:%vreg578 GPR64:%vreg580,%vreg577
2240B		%vreg573<def> = LDRWui %vreg578, 0; mem:LD4[%arrayidx42] GPR32:%vreg573 GPR64common:%vreg578
2256B		%vreg571<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg571
2272B		STRWui %vreg573, %vreg571, 15; mem:ST4[%tPos43] GPR32:%vreg573 GPR64common:%vreg571
2288B		%vreg568<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg568
2304B		%vreg567<def> = LDRWui %vreg568, 15; mem:LD4[%tPos44] GPR32:%vreg567 GPR64common:%vreg568
2320B		%vreg563<def> = ANDWri %vreg567, 7; GPR32common:%vreg563 GPR32:%vreg567
2352B		STRBBui %vreg563, <fi#2>, 0; mem:ST1[FixedStack2] GPR32common:%vreg563
2368B		%vreg560<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg560
2384B		%vreg559<def> = LDRWui %vreg560, 15; mem:LD4[%tPos46] GPR32:%vreg559 GPR64common:%vreg560
2400B		%vreg558<def> = UBFMWri %vreg559, 8, 31; GPR32:%vreg558,%vreg559
2416B		STRWui %vreg558, %vreg560, 15; mem:ST4[%tPos46] GPR32:%vreg558 GPR64common:%vreg560
2432B		%vreg554<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg554
2448B		%vreg553<def> = LDRWui %vreg554, 6; mem:LD4[%rNToGo] GPR32:%vreg553 GPR64common:%vreg554
2464B		CBNZW %vreg553, <BB#18>; GPR32:%vreg553
	    Successors according to CFG: BB#18 BB#15

2480B	BB#15: derived from LLVM BB %if.then.50
	    Predecessors according to CFG: BB#14
2496B		%vreg615<def> = ADRP <ga:@BZ2_rNums>[TF=1]; GPR64common:%vreg615
2512B		%vreg616<def> = ADDXri %vreg615, <ga:@BZ2_rNums>[TF=34], 0; GPR64common:%vreg616,%vreg615
2528B		%vreg626<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg626
2544B		%vreg625<def> = LDRSWui %vreg626, 7; mem:LD4[%rTPos] GPR64:%vreg625 GPR64common:%vreg626
2560B		%vreg618<def> = MOVi64imm 4; GPR64:%vreg618
2576B		%vreg619<def> = MADDXrrr %vreg625, %vreg618, %XZR; GPR64:%vreg619,%vreg625,%vreg618
2592B		%vreg620<def> = ADDXrr %vreg616, %vreg619; GPR64common:%vreg620,%vreg616 GPR64:%vreg619
2608B		%vreg614<def> = LDRWui %vreg620, 0; mem:LD4[%arrayidx52] GPR32:%vreg614 GPR64common:%vreg620
2624B		%vreg612<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg612
2640B		STRWui %vreg614, %vreg612, 6; mem:ST4[%rNToGo53] GPR32:%vreg614 GPR64common:%vreg612
2656B		%vreg609<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg609
2672B		%vreg608<def> = LDRWui %vreg609, 7; mem:LD4[%rTPos54] GPR32common:%vreg608 GPR64common:%vreg609
2688B		%vreg607<def> = ADDWri %vreg608, 1, 0; GPR32common:%vreg607,%vreg608
2704B		STRWui %vreg607, %vreg609, 7; mem:ST4[%rTPos54] GPR32common:%vreg607 GPR64common:%vreg609
2720B		%vreg603<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg603
2736B		%vreg602<def> = LDRWui %vreg603, 7; mem:LD4[%rTPos56] GPR32common:%vreg602 GPR64common:%vreg603
2752B		%WZR<def> = SUBSWri %vreg602, 512, 0, %NZCV<imp-def>; GPR32common:%vreg602
2768B		Bcc 1, <BB#17>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#17 BB#16

2784B	BB#16: derived from LLVM BB %if.then.59
	    Predecessors according to CFG: BB#15
2800B		%vreg628<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg628
2816B		STRWui %WZR, %vreg628, 7; mem:ST4[%rTPos60] GPR64common:%vreg628
	    Successors according to CFG: BB#17

2832B	BB#17: derived from LLVM BB %if.end.61
	    Predecessors according to CFG: BB#15 BB#16
2848B		B <BB#18>
	    Successors according to CFG: BB#18

2864B	BB#18: derived from LLVM BB %if.end.62
	    Predecessors according to CFG: BB#14 BB#17
2880B		%vreg657<def> = MOVi32imm 1; GPR32:%vreg657
2896B		%vreg658<def> = COPY %WZR; GPR32:%vreg658
2912B		%vreg668<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg668
2928B		%vreg667<def> = LDRWui %vreg668, 6; mem:LD4[%rNToGo63] GPR32common:%vreg667 GPR64common:%vreg668
2944B		%vreg666<def> = SUBWri %vreg667, 1, 0; GPR32common:%vreg666,%vreg667
2960B		STRWui %vreg666, %vreg668, 6; mem:ST4[%rNToGo63] GPR32common:%vreg666 GPR64common:%vreg668
2976B		%vreg662<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg662
2992B		%vreg661<def> = LDRWui %vreg662, 6; mem:LD4[%rNToGo65] GPR32common:%vreg661 GPR64common:%vreg662
3008B		%WZR<def> = SUBSWri %vreg661, 1, 0, %NZCV<imp-def>; GPR32common:%vreg661
3024B		%vreg659<def> = CSELWr %vreg657, %vreg658, 0, %NZCV<imp-use,kill>; GPR32:%vreg659,%vreg657,%vreg658
3040B		%vreg655<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg655
3056B		%vreg649<def> = EORWrr %vreg655, %vreg659; GPR32:%vreg649,%vreg655,%vreg659
3088B		STRBBui %vreg649, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg649
3104B		%vreg646<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg646
3120B		%vreg645<def> = LDRWui %vreg646, 273; mem:LD4[%nblock_used71] GPR32common:%vreg645 GPR64common:%vreg646
3136B		%vreg644<def> = ADDWri %vreg645, 1, 0; GPR32common:%vreg644,%vreg645
3152B		STRWui %vreg644, %vreg646, 273; mem:ST4[%nblock_used71] GPR32common:%vreg644 GPR64common:%vreg646
3168B		%vreg640<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg640
3184B		%vreg639<def> = LDRWui %vreg640, 273; mem:LD4[%nblock_used73] GPR32:%vreg639 GPR64common:%vreg640
3200B		%vreg637<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg637
3216B		%vreg634<def> = MOVi64imm 64080; GPR64:%vreg634
3232B		%vreg635<def> = ADDXrr %vreg637, %vreg634; GPR64common:%vreg635 GPR64:%vreg637,%vreg634
3248B		%vreg636<def> = LDRWui %vreg635, 0; mem:LD4[%save_nblock74] GPR32common:%vreg636 GPR64common:%vreg635
3264B		%vreg632<def> = ADDWri %vreg636, 1, 0; GPR32common:%vreg632,%vreg636
3280B		%WZR<def> = SUBSWrr %vreg639, %vreg632, %NZCV<imp-def>; GPR32:%vreg639 GPR32common:%vreg632
3296B		Bcc 1, <BB#20>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#20 BB#19

3312B	BB#19: derived from LLVM BB %if.then.78
	    Predecessors according to CFG: BB#18
3328B		B <BB#2>
	    Successors according to CFG: BB#2

3344B	BB#20: derived from LLVM BB %if.end.79
	    Predecessors according to CFG: BB#18
3360B		%vreg676<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg676
3376B		%vreg673<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg673
3392B		%vreg672<def> = LDRWui %vreg673, 16; mem:LD4[%k081] GPR32:%vreg672 GPR64common:%vreg673
3408B		%WZR<def> = SUBSWrr %vreg676, %vreg672, %NZCV<imp-def>; GPR32:%vreg676,%vreg672
3424B		Bcc 0, <BB#22>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#22 BB#21

3440B	BB#21: derived from LLVM BB %if.then.84
	    Predecessors according to CFG: BB#20
3456B		%vreg1130<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg1130
3472B		%vreg1127<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1127
3488B		STRWui %vreg1130, %vreg1127, 16; mem:ST4[%k086] GPR32:%vreg1130 GPR64common:%vreg1127
3504B		B <BB#2>
	    Successors according to CFG: BB#2

3520B	BB#22: derived from LLVM BB %if.end.87
	    Predecessors according to CFG: BB#20
3536B		%vreg715<def> = MOVi32imm 2; GPR32:%vreg715
3552B		%vreg717<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg717
3568B		STRWui %vreg715, %vreg717, 4; mem:ST4[%state_out_len88] GPR32:%vreg715 GPR64common:%vreg717
3584B		%vreg714<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg714
3600B		%vreg713:sub_32<def,read-undef> = LDRWui %vreg714, 15; mem:LD4[%tPos89] GPR64:%vreg713 GPR64common:%vreg714
3632B		%vreg707<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg707
3648B		%vreg706<def> = LDRXui %vreg707, 394; mem:LD8[%tt91] GPR64:%vreg706 GPR64common:%vreg707
3664B		%vreg702<def> = MOVi64imm 4; GPR64:%vreg702
3680B		%vreg703<def> = MADDXrrr %vreg713, %vreg702, %XZR; GPR64:%vreg703,%vreg713,%vreg702
3696B		%vreg704<def> = ADDXrr %vreg706, %vreg703; GPR64common:%vreg704 GPR64:%vreg706,%vreg703
3712B		%vreg699<def> = LDRWui %vreg704, 0; mem:LD4[%arrayidx92] GPR32:%vreg699 GPR64common:%vreg704
3728B		%vreg697<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg697
3744B		STRWui %vreg699, %vreg697, 15; mem:ST4[%tPos93] GPR32:%vreg699 GPR64common:%vreg697
3760B		%vreg694<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg694
3776B		%vreg693<def> = LDRWui %vreg694, 15; mem:LD4[%tPos94] GPR32:%vreg693 GPR64common:%vreg694
3792B		%vreg689<def> = ANDWri %vreg693, 7; GPR32common:%vreg689 GPR32:%vreg693
3824B		STRBBui %vreg689, <fi#2>, 0; mem:ST1[FixedStack2] GPR32common:%vreg689
3840B		%vreg686<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg686
3856B		%vreg685<def> = LDRWui %vreg686, 15; mem:LD4[%tPos97] GPR32:%vreg685 GPR64common:%vreg686
3872B		%vreg684<def> = UBFMWri %vreg685, 8, 31; GPR32:%vreg684,%vreg685
3888B		STRWui %vreg684, %vreg686, 15; mem:ST4[%tPos97] GPR32:%vreg684 GPR64common:%vreg686
3904B		%vreg680<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg680
3920B		%vreg679<def> = LDRWui %vreg680, 6; mem:LD4[%rNToGo99] GPR32:%vreg679 GPR64common:%vreg680
3936B		CBNZW %vreg679, <BB#26>; GPR32:%vreg679
	    Successors according to CFG: BB#26 BB#23

3952B	BB#23: derived from LLVM BB %if.then.102
	    Predecessors according to CFG: BB#22
3968B		%vreg733<def> = ADRP <ga:@BZ2_rNums>[TF=1]; GPR64common:%vreg733
3984B		%vreg734<def> = ADDXri %vreg733, <ga:@BZ2_rNums>[TF=34], 0; GPR64common:%vreg734,%vreg733
4000B		%vreg744<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg744
4016B		%vreg743<def> = LDRSWui %vreg744, 7; mem:LD4[%rTPos103] GPR64:%vreg743 GPR64common:%vreg744
4032B		%vreg736<def> = MOVi64imm 4; GPR64:%vreg736
4048B		%vreg737<def> = MADDXrrr %vreg743, %vreg736, %XZR; GPR64:%vreg737,%vreg743,%vreg736
4064B		%vreg738<def> = ADDXrr %vreg734, %vreg737; GPR64common:%vreg738,%vreg734 GPR64:%vreg737
4080B		%vreg732<def> = LDRWui %vreg738, 0; mem:LD4[%arrayidx105] GPR32:%vreg732 GPR64common:%vreg738
4096B		%vreg730<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg730
4112B		STRWui %vreg732, %vreg730, 6; mem:ST4[%rNToGo106] GPR32:%vreg732 GPR64common:%vreg730
4128B		%vreg727<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg727
4144B		%vreg726<def> = LDRWui %vreg727, 7; mem:LD4[%rTPos107] GPR32common:%vreg726 GPR64common:%vreg727
4160B		%vreg725<def> = ADDWri %vreg726, 1, 0; GPR32common:%vreg725,%vreg726
4176B		STRWui %vreg725, %vreg727, 7; mem:ST4[%rTPos107] GPR32common:%vreg725 GPR64common:%vreg727
4192B		%vreg721<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg721
4208B		%vreg720<def> = LDRWui %vreg721, 7; mem:LD4[%rTPos109] GPR32common:%vreg720 GPR64common:%vreg721
4224B		%WZR<def> = SUBSWri %vreg720, 512, 0, %NZCV<imp-def>; GPR32common:%vreg720
4240B		Bcc 1, <BB#25>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#25 BB#24

4256B	BB#24: derived from LLVM BB %if.then.112
	    Predecessors according to CFG: BB#23
4272B		%vreg746<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg746
4288B		STRWui %WZR, %vreg746, 7; mem:ST4[%rTPos113] GPR64common:%vreg746
	    Successors according to CFG: BB#25

4304B	BB#25: derived from LLVM BB %if.end.114
	    Predecessors according to CFG: BB#23 BB#24
4320B		B <BB#26>
	    Successors according to CFG: BB#26

4336B	BB#26: derived from LLVM BB %if.end.115
	    Predecessors according to CFG: BB#22 BB#25
4352B		%vreg775<def> = MOVi32imm 1; GPR32:%vreg775
4368B		%vreg776<def> = COPY %WZR; GPR32:%vreg776
4384B		%vreg786<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg786
4400B		%vreg785<def> = LDRWui %vreg786, 6; mem:LD4[%rNToGo116] GPR32common:%vreg785 GPR64common:%vreg786
4416B		%vreg784<def> = SUBWri %vreg785, 1, 0; GPR32common:%vreg784,%vreg785
4432B		STRWui %vreg784, %vreg786, 6; mem:ST4[%rNToGo116] GPR32common:%vreg784 GPR64common:%vreg786
4448B		%vreg780<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg780
4464B		%vreg779<def> = LDRWui %vreg780, 6; mem:LD4[%rNToGo118] GPR32common:%vreg779 GPR64common:%vreg780
4480B		%WZR<def> = SUBSWri %vreg779, 1, 0, %NZCV<imp-def>; GPR32common:%vreg779
4496B		%vreg777<def> = CSELWr %vreg775, %vreg776, 0, %NZCV<imp-use,kill>; GPR32:%vreg777,%vreg775,%vreg776
4512B		%vreg773<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg773
4528B		%vreg767<def> = EORWrr %vreg773, %vreg777; GPR32:%vreg767,%vreg773,%vreg777
4560B		STRBBui %vreg767, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg767
4576B		%vreg764<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg764
4592B		%vreg763<def> = LDRWui %vreg764, 273; mem:LD4[%nblock_used125] GPR32common:%vreg763 GPR64common:%vreg764
4608B		%vreg762<def> = ADDWri %vreg763, 1, 0; GPR32common:%vreg762,%vreg763
4624B		STRWui %vreg762, %vreg764, 273; mem:ST4[%nblock_used125] GPR32common:%vreg762 GPR64common:%vreg764
4640B		%vreg758<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg758
4656B		%vreg757<def> = LDRWui %vreg758, 273; mem:LD4[%nblock_used127] GPR32:%vreg757 GPR64common:%vreg758
4672B		%vreg755<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg755
4688B		%vreg752<def> = MOVi64imm 64080; GPR64:%vreg752
4704B		%vreg753<def> = ADDXrr %vreg755, %vreg752; GPR64common:%vreg753 GPR64:%vreg755,%vreg752
4720B		%vreg754<def> = LDRWui %vreg753, 0; mem:LD4[%save_nblock128] GPR32common:%vreg754 GPR64common:%vreg753
4736B		%vreg750<def> = ADDWri %vreg754, 1, 0; GPR32common:%vreg750,%vreg754
4752B		%WZR<def> = SUBSWrr %vreg757, %vreg750, %NZCV<imp-def>; GPR32:%vreg757 GPR32common:%vreg750
4768B		Bcc 1, <BB#28>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#28 BB#27

4784B	BB#27: derived from LLVM BB %if.then.132
	    Predecessors according to CFG: BB#26
4800B		B <BB#2>
	    Successors according to CFG: BB#2

4816B	BB#28: derived from LLVM BB %if.end.133
	    Predecessors according to CFG: BB#26
4832B		%vreg794<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg794
4848B		%vreg791<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg791
4864B		%vreg790<def> = LDRWui %vreg791, 16; mem:LD4[%k0135] GPR32:%vreg790 GPR64common:%vreg791
4880B		%WZR<def> = SUBSWrr %vreg794, %vreg790, %NZCV<imp-def>; GPR32:%vreg794,%vreg790
4896B		Bcc 0, <BB#30>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#30 BB#29

4912B	BB#29: derived from LLVM BB %if.then.138
	    Predecessors according to CFG: BB#28
4928B		%vreg1124<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg1124
4944B		%vreg1121<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1121
4960B		STRWui %vreg1124, %vreg1121, 16; mem:ST4[%k0140] GPR32:%vreg1124 GPR64common:%vreg1121
4976B		B <BB#2>
	    Successors according to CFG: BB#2

4992B	BB#30: derived from LLVM BB %if.end.141
	    Predecessors according to CFG: BB#28
5008B		%vreg833<def> = MOVi32imm 3; GPR32:%vreg833
5024B		%vreg835<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg835
5040B		STRWui %vreg833, %vreg835, 4; mem:ST4[%state_out_len142] GPR32:%vreg833 GPR64common:%vreg835
5056B		%vreg832<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg832
5072B		%vreg831:sub_32<def,read-undef> = LDRWui %vreg832, 15; mem:LD4[%tPos143] GPR64:%vreg831 GPR64common:%vreg832
5104B		%vreg825<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg825
5120B		%vreg824<def> = LDRXui %vreg825, 394; mem:LD8[%tt145] GPR64:%vreg824 GPR64common:%vreg825
5136B		%vreg820<def> = MOVi64imm 4; GPR64:%vreg820
5152B		%vreg821<def> = MADDXrrr %vreg831, %vreg820, %XZR; GPR64:%vreg821,%vreg831,%vreg820
5168B		%vreg822<def> = ADDXrr %vreg824, %vreg821; GPR64common:%vreg822 GPR64:%vreg824,%vreg821
5184B		%vreg817<def> = LDRWui %vreg822, 0; mem:LD4[%arrayidx146] GPR32:%vreg817 GPR64common:%vreg822
5200B		%vreg815<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg815
5216B		STRWui %vreg817, %vreg815, 15; mem:ST4[%tPos147] GPR32:%vreg817 GPR64common:%vreg815
5232B		%vreg812<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg812
5248B		%vreg811<def> = LDRWui %vreg812, 15; mem:LD4[%tPos148] GPR32:%vreg811 GPR64common:%vreg812
5264B		%vreg807<def> = ANDWri %vreg811, 7; GPR32common:%vreg807 GPR32:%vreg811
5296B		STRBBui %vreg807, <fi#2>, 0; mem:ST1[FixedStack2] GPR32common:%vreg807
5312B		%vreg804<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg804
5328B		%vreg803<def> = LDRWui %vreg804, 15; mem:LD4[%tPos151] GPR32:%vreg803 GPR64common:%vreg804
5344B		%vreg802<def> = UBFMWri %vreg803, 8, 31; GPR32:%vreg802,%vreg803
5360B		STRWui %vreg802, %vreg804, 15; mem:ST4[%tPos151] GPR32:%vreg802 GPR64common:%vreg804
5376B		%vreg798<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg798
5392B		%vreg797<def> = LDRWui %vreg798, 6; mem:LD4[%rNToGo153] GPR32:%vreg797 GPR64common:%vreg798
5408B		CBNZW %vreg797, <BB#34>; GPR32:%vreg797
	    Successors according to CFG: BB#34 BB#31

5424B	BB#31: derived from LLVM BB %if.then.156
	    Predecessors according to CFG: BB#30
5440B		%vreg851<def> = ADRP <ga:@BZ2_rNums>[TF=1]; GPR64common:%vreg851
5456B		%vreg852<def> = ADDXri %vreg851, <ga:@BZ2_rNums>[TF=34], 0; GPR64common:%vreg852,%vreg851
5472B		%vreg862<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg862
5488B		%vreg861<def> = LDRSWui %vreg862, 7; mem:LD4[%rTPos157] GPR64:%vreg861 GPR64common:%vreg862
5504B		%vreg854<def> = MOVi64imm 4; GPR64:%vreg854
5520B		%vreg855<def> = MADDXrrr %vreg861, %vreg854, %XZR; GPR64:%vreg855,%vreg861,%vreg854
5536B		%vreg856<def> = ADDXrr %vreg852, %vreg855; GPR64common:%vreg856,%vreg852 GPR64:%vreg855
5552B		%vreg850<def> = LDRWui %vreg856, 0; mem:LD4[%arrayidx159] GPR32:%vreg850 GPR64common:%vreg856
5568B		%vreg848<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg848
5584B		STRWui %vreg850, %vreg848, 6; mem:ST4[%rNToGo160] GPR32:%vreg850 GPR64common:%vreg848
5600B		%vreg845<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg845
5616B		%vreg844<def> = LDRWui %vreg845, 7; mem:LD4[%rTPos161] GPR32common:%vreg844 GPR64common:%vreg845
5632B		%vreg843<def> = ADDWri %vreg844, 1, 0; GPR32common:%vreg843,%vreg844
5648B		STRWui %vreg843, %vreg845, 7; mem:ST4[%rTPos161] GPR32common:%vreg843 GPR64common:%vreg845
5664B		%vreg839<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg839
5680B		%vreg838<def> = LDRWui %vreg839, 7; mem:LD4[%rTPos163] GPR32common:%vreg838 GPR64common:%vreg839
5696B		%WZR<def> = SUBSWri %vreg838, 512, 0, %NZCV<imp-def>; GPR32common:%vreg838
5712B		Bcc 1, <BB#33>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#33 BB#32

5728B	BB#32: derived from LLVM BB %if.then.166
	    Predecessors according to CFG: BB#31
5744B		%vreg864<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg864
5760B		STRWui %WZR, %vreg864, 7; mem:ST4[%rTPos167] GPR64common:%vreg864
	    Successors according to CFG: BB#33

5776B	BB#33: derived from LLVM BB %if.end.168
	    Predecessors according to CFG: BB#31 BB#32
5792B		B <BB#34>
	    Successors according to CFG: BB#34

5808B	BB#34: derived from LLVM BB %if.end.169
	    Predecessors according to CFG: BB#30 BB#33
5824B		%vreg893<def> = MOVi32imm 1; GPR32:%vreg893
5840B		%vreg894<def> = COPY %WZR; GPR32:%vreg894
5856B		%vreg904<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg904
5872B		%vreg903<def> = LDRWui %vreg904, 6; mem:LD4[%rNToGo170] GPR32common:%vreg903 GPR64common:%vreg904
5888B		%vreg902<def> = SUBWri %vreg903, 1, 0; GPR32common:%vreg902,%vreg903
5904B		STRWui %vreg902, %vreg904, 6; mem:ST4[%rNToGo170] GPR32common:%vreg902 GPR64common:%vreg904
5920B		%vreg898<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg898
5936B		%vreg897<def> = LDRWui %vreg898, 6; mem:LD4[%rNToGo172] GPR32common:%vreg897 GPR64common:%vreg898
5952B		%WZR<def> = SUBSWri %vreg897, 1, 0, %NZCV<imp-def>; GPR32common:%vreg897
5968B		%vreg895<def> = CSELWr %vreg893, %vreg894, 0, %NZCV<imp-use,kill>; GPR32:%vreg895,%vreg893,%vreg894
5984B		%vreg891<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg891
6000B		%vreg885<def> = EORWrr %vreg891, %vreg895; GPR32:%vreg885,%vreg891,%vreg895
6032B		STRBBui %vreg885, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg885
6048B		%vreg882<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg882
6064B		%vreg881<def> = LDRWui %vreg882, 273; mem:LD4[%nblock_used179] GPR32common:%vreg881 GPR64common:%vreg882
6080B		%vreg880<def> = ADDWri %vreg881, 1, 0; GPR32common:%vreg880,%vreg881
6096B		STRWui %vreg880, %vreg882, 273; mem:ST4[%nblock_used179] GPR32common:%vreg880 GPR64common:%vreg882
6112B		%vreg876<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg876
6128B		%vreg875<def> = LDRWui %vreg876, 273; mem:LD4[%nblock_used181] GPR32:%vreg875 GPR64common:%vreg876
6144B		%vreg873<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg873
6160B		%vreg870<def> = MOVi64imm 64080; GPR64:%vreg870
6176B		%vreg871<def> = ADDXrr %vreg873, %vreg870; GPR64common:%vreg871 GPR64:%vreg873,%vreg870
6192B		%vreg872<def> = LDRWui %vreg871, 0; mem:LD4[%save_nblock182] GPR32common:%vreg872 GPR64common:%vreg871
6208B		%vreg868<def> = ADDWri %vreg872, 1, 0; GPR32common:%vreg868,%vreg872
6224B		%WZR<def> = SUBSWrr %vreg875, %vreg868, %NZCV<imp-def>; GPR32:%vreg875 GPR32common:%vreg868
6240B		Bcc 1, <BB#36>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#36 BB#35

6256B	BB#35: derived from LLVM BB %if.then.186
	    Predecessors according to CFG: BB#34
6272B		B <BB#2>
	    Successors according to CFG: BB#2

6288B	BB#36: derived from LLVM BB %if.end.187
	    Predecessors according to CFG: BB#34
6304B		%vreg912<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg912
6320B		%vreg909<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg909
6336B		%vreg908<def> = LDRWui %vreg909, 16; mem:LD4[%k0189] GPR32:%vreg908 GPR64common:%vreg909
6352B		%WZR<def> = SUBSWrr %vreg912, %vreg908, %NZCV<imp-def>; GPR32:%vreg912,%vreg908
6368B		Bcc 0, <BB#38>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#38 BB#37

6384B	BB#37: derived from LLVM BB %if.then.192
	    Predecessors according to CFG: BB#36
6400B		%vreg1118<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg1118
6416B		%vreg1115<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1115
6432B		STRWui %vreg1118, %vreg1115, 16; mem:ST4[%k0194] GPR32:%vreg1118 GPR64common:%vreg1115
6448B		B <BB#2>
	    Successors according to CFG: BB#2

6464B	BB#38: derived from LLVM BB %if.end.195
	    Predecessors according to CFG: BB#36
6480B		%vreg950<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg950
6496B		%vreg949:sub_32<def,read-undef> = LDRWui %vreg950, 15; mem:LD4[%tPos196] GPR64:%vreg949 GPR64common:%vreg950
6528B		%vreg943<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg943
6544B		%vreg942<def> = LDRXui %vreg943, 394; mem:LD8[%tt198] GPR64:%vreg942 GPR64common:%vreg943
6560B		%vreg938<def> = MOVi64imm 4; GPR64:%vreg938
6576B		%vreg939<def> = MADDXrrr %vreg949, %vreg938, %XZR; GPR64:%vreg939,%vreg949,%vreg938
6592B		%vreg940<def> = ADDXrr %vreg942, %vreg939; GPR64common:%vreg940 GPR64:%vreg942,%vreg939
6608B		%vreg935<def> = LDRWui %vreg940, 0; mem:LD4[%arrayidx199] GPR32:%vreg935 GPR64common:%vreg940
6624B		%vreg933<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg933
6640B		STRWui %vreg935, %vreg933, 15; mem:ST4[%tPos200] GPR32:%vreg935 GPR64common:%vreg933
6656B		%vreg930<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg930
6672B		%vreg929<def> = LDRWui %vreg930, 15; mem:LD4[%tPos201] GPR32:%vreg929 GPR64common:%vreg930
6688B		%vreg925<def> = ANDWri %vreg929, 7; GPR32common:%vreg925 GPR32:%vreg929
6720B		STRBBui %vreg925, <fi#2>, 0; mem:ST1[FixedStack2] GPR32common:%vreg925
6736B		%vreg922<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg922
6752B		%vreg921<def> = LDRWui %vreg922, 15; mem:LD4[%tPos204] GPR32:%vreg921 GPR64common:%vreg922
6768B		%vreg920<def> = UBFMWri %vreg921, 8, 31; GPR32:%vreg920,%vreg921
6784B		STRWui %vreg920, %vreg922, 15; mem:ST4[%tPos204] GPR32:%vreg920 GPR64common:%vreg922
6800B		%vreg916<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg916
6816B		%vreg915<def> = LDRWui %vreg916, 6; mem:LD4[%rNToGo206] GPR32:%vreg915 GPR64common:%vreg916
6832B		CBNZW %vreg915, <BB#42>; GPR32:%vreg915
	    Successors according to CFG: BB#42 BB#39

6848B	BB#39: derived from LLVM BB %if.then.209
	    Predecessors according to CFG: BB#38
6864B		%vreg966<def> = ADRP <ga:@BZ2_rNums>[TF=1]; GPR64common:%vreg966
6880B		%vreg967<def> = ADDXri %vreg966, <ga:@BZ2_rNums>[TF=34], 0; GPR64common:%vreg967,%vreg966
6896B		%vreg977<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg977
6912B		%vreg976<def> = LDRSWui %vreg977, 7; mem:LD4[%rTPos210] GPR64:%vreg976 GPR64common:%vreg977
6928B		%vreg969<def> = MOVi64imm 4; GPR64:%vreg969
6944B		%vreg970<def> = MADDXrrr %vreg976, %vreg969, %XZR; GPR64:%vreg970,%vreg976,%vreg969
6960B		%vreg971<def> = ADDXrr %vreg967, %vreg970; GPR64common:%vreg971,%vreg967 GPR64:%vreg970
6976B		%vreg965<def> = LDRWui %vreg971, 0; mem:LD4[%arrayidx212] GPR32:%vreg965 GPR64common:%vreg971
6992B		%vreg963<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg963
7008B		STRWui %vreg965, %vreg963, 6; mem:ST4[%rNToGo213] GPR32:%vreg965 GPR64common:%vreg963
7024B		%vreg960<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg960
7040B		%vreg959<def> = LDRWui %vreg960, 7; mem:LD4[%rTPos214] GPR32common:%vreg959 GPR64common:%vreg960
7056B		%vreg958<def> = ADDWri %vreg959, 1, 0; GPR32common:%vreg958,%vreg959
7072B		STRWui %vreg958, %vreg960, 7; mem:ST4[%rTPos214] GPR32common:%vreg958 GPR64common:%vreg960
7088B		%vreg954<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg954
7104B		%vreg953<def> = LDRWui %vreg954, 7; mem:LD4[%rTPos216] GPR32common:%vreg953 GPR64common:%vreg954
7120B		%WZR<def> = SUBSWri %vreg953, 512, 0, %NZCV<imp-def>; GPR32common:%vreg953
7136B		Bcc 1, <BB#41>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#41 BB#40

7152B	BB#40: derived from LLVM BB %if.then.219
	    Predecessors according to CFG: BB#39
7168B		%vreg979<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg979
7184B		STRWui %WZR, %vreg979, 7; mem:ST4[%rTPos220] GPR64common:%vreg979
	    Successors according to CFG: BB#41

7200B	BB#41: derived from LLVM BB %if.end.221
	    Predecessors according to CFG: BB#39 BB#40
7216B		B <BB#42>
	    Successors according to CFG: BB#42

7232B	BB#42: derived from LLVM BB %if.end.222
	    Predecessors according to CFG: BB#38 BB#41
7248B		%vreg1046<def> = MOVi32imm 1; GPR32:%vreg1046
7264B		%vreg1047<def> = COPY %WZR; GPR32:%vreg1047
7280B		%vreg1057<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1057
7296B		%vreg1056<def> = LDRWui %vreg1057, 6; mem:LD4[%rNToGo223] GPR32common:%vreg1056 GPR64common:%vreg1057
7312B		%vreg1055<def> = SUBWri %vreg1056, 1, 0; GPR32common:%vreg1055,%vreg1056
7328B		STRWui %vreg1055, %vreg1057, 6; mem:ST4[%rNToGo223] GPR32common:%vreg1055 GPR64common:%vreg1057
7344B		%vreg1051<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1051
7360B		%vreg1050<def> = LDRWui %vreg1051, 6; mem:LD4[%rNToGo225] GPR32common:%vreg1050 GPR64common:%vreg1051
7376B		%WZR<def> = SUBSWri %vreg1050, 1, 0, %NZCV<imp-def>; GPR32common:%vreg1050
7392B		%vreg1048<def> = CSELWr %vreg1046, %vreg1047, 0, %NZCV<imp-use,kill>; GPR32:%vreg1048,%vreg1046,%vreg1047
7408B		%vreg1044<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg1044
7424B		%vreg1038<def> = EORWrr %vreg1044, %vreg1048; GPR32:%vreg1038,%vreg1044,%vreg1048
7456B		STRBBui %vreg1038, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg1038
7472B		%vreg1035<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1035
7488B		%vreg1034<def> = LDRWui %vreg1035, 273; mem:LD4[%nblock_used232] GPR32common:%vreg1034 GPR64common:%vreg1035
7504B		%vreg1033<def> = ADDWri %vreg1034, 1, 0; GPR32common:%vreg1033,%vreg1034
7520B		STRWui %vreg1033, %vreg1035, 273; mem:ST4[%nblock_used232] GPR32common:%vreg1033 GPR64common:%vreg1035
7536B		%vreg1029<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32common:%vreg1029
7552B		%vreg1026<def> = ADDWri %vreg1029, 4, 0; GPR32common:%vreg1026,%vreg1029
7568B		%vreg1024<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1024
7584B		STRWui %vreg1026, %vreg1024, 4; mem:ST4[%state_out_len236] GPR32common:%vreg1026 GPR64common:%vreg1024
7600B		%vreg1021<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1021
7616B		%vreg1020:sub_32<def,read-undef> = LDRWui %vreg1021, 15; mem:LD4[%tPos237] GPR64:%vreg1020 GPR64common:%vreg1021
7648B		%vreg1014<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1014
7664B		%vreg1013<def> = LDRXui %vreg1014, 394; mem:LD8[%tt239] GPR64:%vreg1013 GPR64common:%vreg1014
7680B		%vreg1009<def> = MOVi64imm 4; GPR64:%vreg1009
7696B		%vreg1010<def> = MADDXrrr %vreg1020, %vreg1009, %XZR; GPR64:%vreg1010,%vreg1020,%vreg1009
7712B		%vreg1011<def> = ADDXrr %vreg1013, %vreg1010; GPR64common:%vreg1011 GPR64:%vreg1013,%vreg1010
7728B		%vreg1006<def> = LDRWui %vreg1011, 0; mem:LD4[%arrayidx240] GPR32:%vreg1006 GPR64common:%vreg1011
7744B		%vreg1004<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1004
7760B		STRWui %vreg1006, %vreg1004, 15; mem:ST4[%tPos241] GPR32:%vreg1006 GPR64common:%vreg1004
7776B		%vreg1001<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1001
7792B		%vreg1000<def> = LDRWui %vreg1001, 15; mem:LD4[%tPos242] GPR32:%vreg1000 GPR64common:%vreg1001
7808B		%vreg996<def> = ANDWri %vreg1000, 7; GPR32common:%vreg996 GPR32:%vreg1000
7840B		%vreg994<def> = UBFMWri %vreg996, 0, 7; GPR32:%vreg994 GPR32common:%vreg996
7856B		%vreg992<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg992
7872B		STRWui %vreg994, %vreg992, 16; mem:ST4[%k0246] GPR32:%vreg994 GPR64common:%vreg992
7888B		%vreg989<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg989
7904B		%vreg988<def> = LDRWui %vreg989, 15; mem:LD4[%tPos247] GPR32:%vreg988 GPR64common:%vreg989
7920B		%vreg987<def> = UBFMWri %vreg988, 8, 31; GPR32:%vreg987,%vreg988
7936B		STRWui %vreg987, %vreg989, 15; mem:ST4[%tPos247] GPR32:%vreg987 GPR64common:%vreg989
7952B		%vreg983<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg983
7968B		%vreg982<def> = LDRWui %vreg983, 6; mem:LD4[%rNToGo249] GPR32:%vreg982 GPR64common:%vreg983
7984B		CBNZW %vreg982, <BB#46>; GPR32:%vreg982
	    Successors according to CFG: BB#46 BB#43

8000B	BB#43: derived from LLVM BB %if.then.252
	    Predecessors according to CFG: BB#42
8016B		%vreg1073<def> = ADRP <ga:@BZ2_rNums>[TF=1]; GPR64common:%vreg1073
8032B		%vreg1074<def> = ADDXri %vreg1073, <ga:@BZ2_rNums>[TF=34], 0; GPR64common:%vreg1074,%vreg1073
8048B		%vreg1084<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1084
8064B		%vreg1083<def> = LDRSWui %vreg1084, 7; mem:LD4[%rTPos253] GPR64:%vreg1083 GPR64common:%vreg1084
8080B		%vreg1076<def> = MOVi64imm 4; GPR64:%vreg1076
8096B		%vreg1077<def> = MADDXrrr %vreg1083, %vreg1076, %XZR; GPR64:%vreg1077,%vreg1083,%vreg1076
8112B		%vreg1078<def> = ADDXrr %vreg1074, %vreg1077; GPR64common:%vreg1078,%vreg1074 GPR64:%vreg1077
8128B		%vreg1072<def> = LDRWui %vreg1078, 0; mem:LD4[%arrayidx255] GPR32:%vreg1072 GPR64common:%vreg1078
8144B		%vreg1070<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1070
8160B		STRWui %vreg1072, %vreg1070, 6; mem:ST4[%rNToGo256] GPR32:%vreg1072 GPR64common:%vreg1070
8176B		%vreg1067<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1067
8192B		%vreg1066<def> = LDRWui %vreg1067, 7; mem:LD4[%rTPos257] GPR32common:%vreg1066 GPR64common:%vreg1067
8208B		%vreg1065<def> = ADDWri %vreg1066, 1, 0; GPR32common:%vreg1065,%vreg1066
8224B		STRWui %vreg1065, %vreg1067, 7; mem:ST4[%rTPos257] GPR32common:%vreg1065 GPR64common:%vreg1067
8240B		%vreg1061<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1061
8256B		%vreg1060<def> = LDRWui %vreg1061, 7; mem:LD4[%rTPos259] GPR32common:%vreg1060 GPR64common:%vreg1061
8272B		%WZR<def> = SUBSWri %vreg1060, 512, 0, %NZCV<imp-def>; GPR32common:%vreg1060
8288B		Bcc 1, <BB#45>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#45 BB#44

8304B	BB#44: derived from LLVM BB %if.then.262
	    Predecessors according to CFG: BB#43
8320B		%vreg1086<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1086
8336B		STRWui %WZR, %vreg1086, 7; mem:ST4[%rTPos263] GPR64common:%vreg1086
	    Successors according to CFG: BB#45

8352B	BB#45: derived from LLVM BB %if.end.264
	    Predecessors according to CFG: BB#43 BB#44
8368B		B <BB#46>
	    Successors according to CFG: BB#46

8384B	BB#46: derived from LLVM BB %if.end.265
	    Predecessors according to CFG: BB#42 BB#45
8400B		%vreg1101<def> = MOVi32imm 1; GPR32:%vreg1101
8416B		%vreg1102<def> = COPY %WZR; GPR32:%vreg1102
8432B		%vreg1112<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1112
8448B		%vreg1111<def> = LDRWui %vreg1112, 6; mem:LD4[%rNToGo266] GPR32common:%vreg1111 GPR64common:%vreg1112
8464B		%vreg1110<def> = SUBWri %vreg1111, 1, 0; GPR32common:%vreg1110,%vreg1111
8480B		STRWui %vreg1110, %vreg1112, 6; mem:ST4[%rNToGo266] GPR32common:%vreg1110 GPR64common:%vreg1112
8496B		%vreg1106<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1106
8512B		%vreg1105<def> = LDRWui %vreg1106, 6; mem:LD4[%rNToGo268] GPR32common:%vreg1105 GPR64common:%vreg1106
8528B		%WZR<def> = SUBSWri %vreg1105, 1, 0, %NZCV<imp-def>; GPR32common:%vreg1105
8544B		%vreg1103<def> = CSELWr %vreg1101, %vreg1102, 0, %NZCV<imp-use,kill>; GPR32:%vreg1103,%vreg1101,%vreg1102
8560B		%vreg1099<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1099
8576B		%vreg1098<def> = LDRWui %vreg1099, 16; mem:LD4[%k0272] GPR32:%vreg1098 GPR64common:%vreg1099
8592B		%vreg1097<def> = EORWrr %vreg1098, %vreg1103; GPR32:%vreg1097,%vreg1098,%vreg1103
8608B		STRWui %vreg1097, %vreg1099, 16; mem:ST4[%k0272] GPR32:%vreg1097 GPR64common:%vreg1099
8624B		%vreg1092<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1092
8640B		%vreg1091<def> = LDRWui %vreg1092, 273; mem:LD4[%nblock_used274] GPR32common:%vreg1091 GPR64common:%vreg1092
8656B		%vreg1090<def> = ADDWri %vreg1091, 1, 0; GPR32common:%vreg1090,%vreg1091
8672B		STRWui %vreg1090, %vreg1092, 273; mem:ST4[%nblock_used274] GPR32common:%vreg1090 GPR64common:%vreg1092
8688B		B <BB#2>
	    Successors according to CFG: BB#2

8704B	BB#47: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#0
8720B		%vreg61<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg61
8736B		%vreg60<def> = LDRWui %vreg61, 796; mem:LD4[%calculatedBlockCRC276] GPR32:%vreg60 GPR64common:%vreg61
8752B		STRWui %vreg60, <fi#3>, 0; mem:ST4[FixedStack3] GPR32:%vreg60
8768B		%vreg57<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg57
8784B		%vreg56<def> = LDRBBui %vreg57, 12; mem:LD1[%state_out_ch277] GPR32:%vreg56 GPR64common:%vreg57
8800B		STRBBui %vreg56, <fi#4>, 0; mem:ST1[FixedStack4] GPR32:%vreg56
8816B		%vreg53<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg53
8832B		%vreg52<def> = LDRWui %vreg53, 4; mem:LD4[%state_out_len278] GPR32:%vreg52 GPR64common:%vreg53
8848B		STRWui %vreg52, <fi#5>, 0; mem:ST4[FixedStack5] GPR32:%vreg52
8864B		%vreg49<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg49
8880B		%vreg48<def> = LDRWui %vreg49, 273; mem:LD4[%nblock_used279] GPR32:%vreg48 GPR64common:%vreg49
8896B		STRWui %vreg48, <fi#6>, 0; mem:ST4[FixedStack6] GPR32:%vreg48
8912B		%vreg45<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg45
8928B		%vreg44<def> = LDRWui %vreg45, 16; mem:LD4[%k0280] GPR32:%vreg44 GPR64common:%vreg45
8944B		STRWui %vreg44, <fi#7>, 0; mem:ST4[FixedStack7] GPR32:%vreg44
8960B		%vreg41<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg41
8976B		%vreg40<def> = LDRXui %vreg41, 394; mem:LD8[%tt281] GPR64:%vreg40 GPR64common:%vreg41
8992B		STRXui %vreg40, <fi#8>, 0; mem:ST8[FixedStack8] GPR64:%vreg40
9008B		%vreg37<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg37
9024B		%vreg36<def> = LDRWui %vreg37, 15; mem:LD4[%tPos282] GPR32:%vreg36 GPR64common:%vreg37
9040B		STRWui %vreg36, <fi#9>, 0; mem:ST4[FixedStack9] GPR32:%vreg36
9056B		%vreg33<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg33
9072B		%vreg32<def> = LDRXui %vreg33, 0; mem:LD8[%strm283] GPR64common:%vreg32,%vreg33
9088B		%vreg30<def> = LDRXui %vreg32, 3; mem:LD8[%next_out284] GPR64:%vreg30 GPR64common:%vreg32
9104B		STRXui %vreg30, <fi#10>, 0; mem:ST8[FixedStack10] GPR64:%vreg30
9120B		%vreg27<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg27
9136B		%vreg26<def> = LDRXui %vreg27, 0; mem:LD8[%strm285] GPR64common:%vreg26,%vreg27
9152B		%vreg24<def> = LDRWui %vreg26, 8; mem:LD4[%avail_out286] GPR32:%vreg24 GPR64common:%vreg26
9168B		STRWui %vreg24, <fi#11>, 0; mem:ST4[FixedStack11] GPR32:%vreg24
9184B		%vreg21<def> = LDRWui <fi#11>, 0; mem:LD4[FixedStack11] GPR32:%vreg21
9200B		STRWui %vreg21, <fi#12>, 0; mem:ST4[FixedStack12] GPR32:%vreg21
9216B		%vreg19<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg19
9232B		%vreg16<def> = MOVi64imm 64080; GPR64:%vreg16
9248B		%vreg17<def> = ADDXrr %vreg19, %vreg16; GPR64common:%vreg17 GPR64:%vreg19,%vreg16
9264B		%vreg18<def> = LDRWui %vreg17, 0; mem:LD4[%save_nblock287] GPR32common:%vreg18 GPR64common:%vreg17
9280B		%vreg14<def> = ADDWri %vreg18, 1, 0; GPR32common:%vreg14,%vreg18
9296B		STRWui %vreg14, <fi#13>, 0; mem:ST4[FixedStack13] GPR32common:%vreg14
	    Successors according to CFG: BB#48

9312B	BB#48: derived from LLVM BB %while.body.289
	    Predecessors according to CFG: BB#47 BB#75 BB#74 BB#72 BB#70 BB#68
9328B		%vreg63<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32common:%vreg63
9344B		%WZR<def> = SUBSWri %vreg63, 0, 0, %NZCV<imp-def>; GPR32common:%vreg63
9360B		Bcc 13, <BB#59>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#59 BB#49

9376B	BB#49: derived from LLVM BB %if.then.292
	    Predecessors according to CFG: BB#48
9392B		B <BB#50>
	    Successors according to CFG: BB#50

9408B	BB#50: derived from LLVM BB %while.body.294
	    Predecessors according to CFG: BB#49 BB#54
9424B		%vreg65<def> = LDRWui <fi#11>, 0; mem:LD4[FixedStack11] GPR32:%vreg65
9440B		CBNZW %vreg65, <BB#52>; GPR32:%vreg65
	    Successors according to CFG: BB#52 BB#51

9456B	BB#51: derived from LLVM BB %if.then.297
	    Predecessors according to CFG: BB#50
9472B		B <BB#76>
	    Successors according to CFG: BB#76

9488B	BB#52: derived from LLVM BB %if.end.298
	    Predecessors according to CFG: BB#50
9504B		%vreg67<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32common:%vreg67
9520B		%WZR<def> = SUBSWri %vreg67, 1, 0, %NZCV<imp-def>; GPR32common:%vreg67
9536B		Bcc 1, <BB#54>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#54 BB#53

9552B	BB#53: derived from LLVM BB %if.then.301
	    Predecessors according to CFG: BB#52
9568B		B <BB#55>
	    Successors according to CFG: BB#55

9584B	BB#54: derived from LLVM BB %if.end.302
	    Predecessors according to CFG: BB#52
9600B		%vreg86<def> = ADRP <ga:@BZ2_crc32Table>[TF=1]; GPR64common:%vreg86
9616B		%vreg87<def> = ADDXri %vreg86, <ga:@BZ2_crc32Table>[TF=34], 0; GPR64common:%vreg87,%vreg86
9632B		%vreg108<def> = LDRBBui <fi#4>, 0; mem:LD1[FixedStack4] GPR32:%vreg108
9648B		%vreg107<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg107
9664B		STRBBui %vreg108, %vreg107, 0; mem:ST1[%249] GPR32:%vreg108 GPR64common:%vreg107
9680B		%vreg104<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg104
9696B		%vreg103<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg103
9712B		%vreg102<def> = UBFMWri %vreg103, 24, 31; GPR32:%vreg102,%vreg103
9728B		%vreg100<def> = LDRBBui <fi#4>, 0; mem:LD1[FixedStack4] GPR32:%vreg100
9744B		%vreg93:sub_32<def,read-undef> = EORWrr %vreg102, %vreg100; GPR64:%vreg93 GPR32:%vreg102,%vreg100
9776B		%vreg94<def> = UBFMXri %vreg93, 0, 31; GPR64:%vreg94,%vreg93
9792B		%vreg89<def> = MOVi64imm 4; GPR64:%vreg89
9808B		%vreg90<def> = MADDXrrr %vreg94, %vreg89, %XZR; GPR64:%vreg90,%vreg94,%vreg89
9824B		%vreg91<def> = ADDXrr %vreg87, %vreg90; GPR64common:%vreg91,%vreg87 GPR64:%vreg90
9840B		%vreg85<def> = LDRWui %vreg91, 0; mem:LD4[%arrayidx308] GPR32:%vreg85 GPR64common:%vreg91
9856B		%vreg83<def> = EORWrs %vreg85, %vreg104, 8; GPR32:%vreg83,%vreg85,%vreg104
9872B		STRWui %vreg83, <fi#3>, 0; mem:ST4[FixedStack3] GPR32:%vreg83
9888B		%vreg79<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32common:%vreg79
9904B		%vreg78<def> = SUBWri %vreg79, 1, 0; GPR32common:%vreg78,%vreg79
9920B		STRWui %vreg78, <fi#5>, 0; mem:ST4[FixedStack5] GPR32common:%vreg78
9936B		%vreg75<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg75
9952B		%vreg74<def> = ADDXri %vreg75, 1, 0; GPR64common:%vreg74,%vreg75
9968B		STRXui %vreg74, <fi#10>, 0; mem:ST8[FixedStack10] GPR64common:%vreg74
9984B		%vreg71<def> = LDRWui <fi#11>, 0; mem:LD4[FixedStack11] GPR32common:%vreg71
10000B		%vreg70<def> = SUBWri %vreg71, 1, 0; GPR32common:%vreg70,%vreg71
10016B		STRWui %vreg70, <fi#11>, 0; mem:ST4[FixedStack11] GPR32common:%vreg70
10032B		B <BB#50>
	    Successors according to CFG: BB#50

10048B	BB#55: derived from LLVM BB %while.end.313
	    Predecessors according to CFG: BB#53
10064B		B <BB#56>
	    Successors according to CFG: BB#56

10080B	BB#56: derived from LLVM BB %s_state_out_len_eq_one
	    Predecessors according to CFG: BB#55 BB#66 BB#64
10096B		%vreg110<def> = LDRWui <fi#11>, 0; mem:LD4[FixedStack11] GPR32:%vreg110
10112B		CBNZW %vreg110, <BB#58>; GPR32:%vreg110
	    Successors according to CFG: BB#58 BB#57

10128B	BB#57: derived from LLVM BB %if.then.316
	    Predecessors according to CFG: BB#56
10144B		%vreg353<def> = MOVi32imm 1; GPR32:%vreg353
10160B		STRWui %vreg353, <fi#5>, 0; mem:ST4[FixedStack5] GPR32:%vreg353
10176B		B <BB#76>
	    Successors according to CFG: BB#76

10192B	BB#58: derived from LLVM BB %if.end.317
	    Predecessors according to CFG: BB#56
10208B		%vreg125<def> = ADRP <ga:@BZ2_crc32Table>[TF=1]; GPR64common:%vreg125
10224B		%vreg126<def> = ADDXri %vreg125, <ga:@BZ2_crc32Table>[TF=34], 0; GPR64common:%vreg126,%vreg125
10240B		%vreg147<def> = LDRBBui <fi#4>, 0; mem:LD1[FixedStack4] GPR32:%vreg147
10256B		%vreg146<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg146
10272B		STRBBui %vreg147, %vreg146, 0; mem:ST1[%259] GPR32:%vreg147 GPR64common:%vreg146
10288B		%vreg143<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg143
10304B		%vreg142<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg142
10320B		%vreg141<def> = UBFMWri %vreg142, 24, 31; GPR32:%vreg141,%vreg142
10336B		%vreg139<def> = LDRBBui <fi#4>, 0; mem:LD1[FixedStack4] GPR32:%vreg139
10352B		%vreg132:sub_32<def,read-undef> = EORWrr %vreg141, %vreg139; GPR64:%vreg132 GPR32:%vreg141,%vreg139
10384B		%vreg133<def> = UBFMXri %vreg132, 0, 31; GPR64:%vreg133,%vreg132
10400B		%vreg128<def> = MOVi64imm 4; GPR64:%vreg128
10416B		%vreg129<def> = MADDXrrr %vreg133, %vreg128, %XZR; GPR64:%vreg129,%vreg133,%vreg128
10432B		%vreg130<def> = ADDXrr %vreg126, %vreg129; GPR64common:%vreg130,%vreg126 GPR64:%vreg129
10448B		%vreg124<def> = LDRWui %vreg130, 0; mem:LD4[%arrayidx323] GPR32:%vreg124 GPR64common:%vreg130
10464B		%vreg122<def> = EORWrs %vreg124, %vreg143, 8; GPR32:%vreg122,%vreg124,%vreg143
10480B		STRWui %vreg122, <fi#3>, 0; mem:ST4[FixedStack3] GPR32:%vreg122
10496B		%vreg118<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg118
10512B		%vreg117<def> = ADDXri %vreg118, 1, 0; GPR64common:%vreg117,%vreg118
10528B		STRXui %vreg117, <fi#10>, 0; mem:ST8[FixedStack10] GPR64common:%vreg117
10544B		%vreg114<def> = LDRWui <fi#11>, 0; mem:LD4[FixedStack11] GPR32common:%vreg114
10560B		%vreg113<def> = SUBWri %vreg114, 1, 0; GPR32common:%vreg113,%vreg114
10576B		STRWui %vreg113, <fi#11>, 0; mem:ST4[FixedStack11] GPR32common:%vreg113
	    Successors according to CFG: BB#59

10592B	BB#59: derived from LLVM BB %if.end.327
	    Predecessors according to CFG: BB#48 BB#58
10608B		%vreg151<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg151
10624B		%vreg150<def> = LDRWui <fi#13>, 0; mem:LD4[FixedStack13] GPR32:%vreg150
10640B		%WZR<def> = SUBSWrr %vreg151, %vreg150, %NZCV<imp-def>; GPR32:%vreg151,%vreg150
10656B		Bcc 13, <BB#61>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#61 BB#60

10672B	BB#60: derived from LLVM BB %if.then.330
	    Predecessors according to CFG: BB#59
10688B		%vreg352<def> = MOVi32imm 1; GPR32:%vreg352
10704B		STRBBui %vreg352, <fi#0>, 0; mem:ST1[FixedStack0] GPR32:%vreg352
10720B		B <BB#80>
	    Successors according to CFG: BB#80

10736B	BB#61: derived from LLVM BB %if.end.331
	    Predecessors according to CFG: BB#59
10752B		%vreg155<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg155
10768B		%vreg154<def> = LDRWui <fi#13>, 0; mem:LD4[FixedStack13] GPR32:%vreg154
10784B		%WZR<def> = SUBSWrr %vreg155, %vreg154, %NZCV<imp-def>; GPR32:%vreg155,%vreg154
10800B		Bcc 1, <BB#63>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#63 BB#62

10816B	BB#62: derived from LLVM BB %if.then.334
	    Predecessors according to CFG: BB#61
10832B		STRWui %WZR, <fi#5>, 0; mem:ST4[FixedStack5]
10848B		B <BB#76>
	    Successors according to CFG: BB#76

10864B	BB#63: derived from LLVM BB %if.end.335
	    Predecessors according to CFG: BB#61
10880B		%vreg192<def> = LDRWui <fi#7>, 0; mem:LD4[FixedStack7] GPR32:%vreg192
10912B		STRBBui %vreg192, <fi#4>, 0; mem:ST1[FixedStack4] GPR32:%vreg192
10928B		%vreg189:sub_32<def,read-undef> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR64:%vreg189
10960B		%vreg184<def> = LDRXui <fi#8>, 0; mem:LD8[FixedStack8] GPR64:%vreg184
10976B		%vreg181<def> = MOVi64imm 4; GPR64:%vreg181
10992B		%vreg182<def> = MADDXrrr %vreg189, %vreg181, %XZR; GPR64:%vreg182,%vreg189,%vreg181
11008B		%vreg183<def> = ADDXrr %vreg184, %vreg182; GPR64common:%vreg183 GPR64:%vreg184,%vreg182
11024B		%vreg178<def> = LDRWui %vreg183, 0; mem:LD4[%arrayidx338] GPR32:%vreg178 GPR64common:%vreg183
11040B		STRWui %vreg178, <fi#9>, 0; mem:ST4[FixedStack9] GPR32:%vreg178
11056B		%vreg175<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32:%vreg175
11072B		%vreg172<def> = ANDWri %vreg175, 7; GPR32common:%vreg172 GPR32:%vreg175
11104B		STRBBui %vreg172, <fi#2>, 0; mem:ST1[FixedStack2] GPR32common:%vreg172
11120B		%vreg169<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32:%vreg169
11136B		%vreg168<def> = UBFMWri %vreg169, 8, 31; GPR32:%vreg168,%vreg169
11152B		STRWui %vreg168, <fi#9>, 0; mem:ST4[FixedStack9] GPR32:%vreg168
11168B		%vreg165<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32common:%vreg165
11184B		%vreg164<def> = ADDWri %vreg165, 1, 0; GPR32common:%vreg164,%vreg165
11200B		STRWui %vreg164, <fi#6>, 0; mem:ST4[FixedStack6] GPR32common:%vreg164
11216B		%vreg161<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg161
11232B		%vreg158<def> = LDRWui <fi#7>, 0; mem:LD4[FixedStack7] GPR32:%vreg158
11248B		%WZR<def> = SUBSWrr %vreg161, %vreg158, %NZCV<imp-def>; GPR32:%vreg161,%vreg158
11264B		Bcc 0, <BB#65>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#65 BB#64

11280B	BB#64: derived from LLVM BB %if.then.346
	    Predecessors according to CFG: BB#63
11296B		%vreg351<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg351
11312B		STRWui %vreg351, <fi#7>, 0; mem:ST4[FixedStack7] GPR32:%vreg351
11328B		B <BB#56>
	    Successors according to CFG: BB#56

11344B	BB#65: derived from LLVM BB %if.end.348
	    Predecessors according to CFG: BB#63
11360B		%vreg197<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg197
11376B		%vreg196<def> = LDRWui <fi#13>, 0; mem:LD4[FixedStack13] GPR32:%vreg196
11392B		%WZR<def> = SUBSWrr %vreg197, %vreg196, %NZCV<imp-def>; GPR32:%vreg197,%vreg196
11408B		Bcc 1, <BB#67>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#67 BB#66

11424B	BB#66: derived from LLVM BB %if.then.351
	    Predecessors according to CFG: BB#65
11440B		B <BB#56>
	    Successors according to CFG: BB#56

11456B	BB#67: derived from LLVM BB %if.end.352
	    Predecessors according to CFG: BB#65
11472B		%vreg230<def> = MOVi32imm 2; GPR32:%vreg230
11488B		STRWui %vreg230, <fi#5>, 0; mem:ST4[FixedStack5] GPR32:%vreg230
11504B		%vreg229:sub_32<def,read-undef> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR64:%vreg229
11536B		%vreg224<def> = LDRXui <fi#8>, 0; mem:LD8[FixedStack8] GPR64:%vreg224
11552B		%vreg221<def> = MOVi64imm 4; GPR64:%vreg221
11568B		%vreg222<def> = MADDXrrr %vreg229, %vreg221, %XZR; GPR64:%vreg222,%vreg229,%vreg221
11584B		%vreg223<def> = ADDXrr %vreg224, %vreg222; GPR64common:%vreg223 GPR64:%vreg224,%vreg222
11600B		%vreg218<def> = LDRWui %vreg223, 0; mem:LD4[%arrayidx354] GPR32:%vreg218 GPR64common:%vreg223
11616B		STRWui %vreg218, <fi#9>, 0; mem:ST4[FixedStack9] GPR32:%vreg218
11632B		%vreg215<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32:%vreg215
11648B		%vreg212<def> = ANDWri %vreg215, 7; GPR32common:%vreg212 GPR32:%vreg215
11680B		STRBBui %vreg212, <fi#2>, 0; mem:ST1[FixedStack2] GPR32common:%vreg212
11696B		%vreg209<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32:%vreg209
11712B		%vreg208<def> = UBFMWri %vreg209, 8, 31; GPR32:%vreg208,%vreg209
11728B		STRWui %vreg208, <fi#9>, 0; mem:ST4[FixedStack9] GPR32:%vreg208
11744B		%vreg205<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32common:%vreg205
11760B		%vreg204<def> = ADDWri %vreg205, 1, 0; GPR32common:%vreg204,%vreg205
11776B		STRWui %vreg204, <fi#6>, 0; mem:ST4[FixedStack6] GPR32common:%vreg204
11792B		%vreg201<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg201
11808B		%vreg200<def> = LDRWui <fi#13>, 0; mem:LD4[FixedStack13] GPR32:%vreg200
11824B		%WZR<def> = SUBSWrr %vreg201, %vreg200, %NZCV<imp-def>; GPR32:%vreg201,%vreg200
11840B		Bcc 1, <BB#69>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#69 BB#68

11856B	BB#68: derived from LLVM BB %if.then.361
	    Predecessors according to CFG: BB#67
11872B		B <BB#48>
	    Successors according to CFG: BB#48

11888B	BB#69: derived from LLVM BB %if.end.362
	    Predecessors according to CFG: BB#67
11904B		%vreg236<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg236
11920B		%vreg233<def> = LDRWui <fi#7>, 0; mem:LD4[FixedStack7] GPR32:%vreg233
11936B		%WZR<def> = SUBSWrr %vreg236, %vreg233, %NZCV<imp-def>; GPR32:%vreg236,%vreg233
11952B		Bcc 0, <BB#71>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#71 BB#70

11968B	BB#70: derived from LLVM BB %if.then.366
	    Predecessors according to CFG: BB#69
11984B		%vreg347<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg347
12000B		STRWui %vreg347, <fi#7>, 0; mem:ST4[FixedStack7] GPR32:%vreg347
12016B		B <BB#48>
	    Successors according to CFG: BB#48

12032B	BB#71: derived from LLVM BB %if.end.368
	    Predecessors according to CFG: BB#69
12048B		%vreg269<def> = MOVi32imm 3; GPR32:%vreg269
12064B		STRWui %vreg269, <fi#5>, 0; mem:ST4[FixedStack5] GPR32:%vreg269
12080B		%vreg268:sub_32<def,read-undef> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR64:%vreg268
12112B		%vreg263<def> = LDRXui <fi#8>, 0; mem:LD8[FixedStack8] GPR64:%vreg263
12128B		%vreg260<def> = MOVi64imm 4; GPR64:%vreg260
12144B		%vreg261<def> = MADDXrrr %vreg268, %vreg260, %XZR; GPR64:%vreg261,%vreg268,%vreg260
12160B		%vreg262<def> = ADDXrr %vreg263, %vreg261; GPR64common:%vreg262 GPR64:%vreg263,%vreg261
12176B		%vreg257<def> = LDRWui %vreg262, 0; mem:LD4[%arrayidx370] GPR32:%vreg257 GPR64common:%vreg262
12192B		STRWui %vreg257, <fi#9>, 0; mem:ST4[FixedStack9] GPR32:%vreg257
12208B		%vreg254<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32:%vreg254
12224B		%vreg251<def> = ANDWri %vreg254, 7; GPR32common:%vreg251 GPR32:%vreg254
12256B		STRBBui %vreg251, <fi#2>, 0; mem:ST1[FixedStack2] GPR32common:%vreg251
12272B		%vreg248<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32:%vreg248
12288B		%vreg247<def> = UBFMWri %vreg248, 8, 31; GPR32:%vreg247,%vreg248
12304B		STRWui %vreg247, <fi#9>, 0; mem:ST4[FixedStack9] GPR32:%vreg247
12320B		%vreg244<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32common:%vreg244
12336B		%vreg243<def> = ADDWri %vreg244, 1, 0; GPR32common:%vreg243,%vreg244
12352B		STRWui %vreg243, <fi#6>, 0; mem:ST4[FixedStack6] GPR32common:%vreg243
12368B		%vreg240<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg240
12384B		%vreg239<def> = LDRWui <fi#13>, 0; mem:LD4[FixedStack13] GPR32:%vreg239
12400B		%WZR<def> = SUBSWrr %vreg240, %vreg239, %NZCV<imp-def>; GPR32:%vreg240,%vreg239
12416B		Bcc 1, <BB#73>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#73 BB#72

12432B	BB#72: derived from LLVM BB %if.then.377
	    Predecessors according to CFG: BB#71
12448B		B <BB#48>
	    Successors according to CFG: BB#48

12464B	BB#73: derived from LLVM BB %if.end.378
	    Predecessors according to CFG: BB#71
12480B		%vreg275<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg275
12496B		%vreg272<def> = LDRWui <fi#7>, 0; mem:LD4[FixedStack7] GPR32:%vreg272
12512B		%WZR<def> = SUBSWrr %vreg275, %vreg272, %NZCV<imp-def>; GPR32:%vreg275,%vreg272
12528B		Bcc 0, <BB#75>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#75 BB#74

12544B	BB#74: derived from LLVM BB %if.then.382
	    Predecessors according to CFG: BB#73
12560B		%vreg343<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg343
12576B		STRWui %vreg343, <fi#7>, 0; mem:ST4[FixedStack7] GPR32:%vreg343
12592B		B <BB#48>
	    Successors according to CFG: BB#48

12608B	BB#75: derived from LLVM BB %if.end.384
	    Predecessors according to CFG: BB#73
12624B		%vreg339:sub_32<def,read-undef> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR64:%vreg339
12656B		%vreg334<def> = LDRXui <fi#8>, 0; mem:LD8[FixedStack8] GPR64:%vreg334
12672B		%vreg331<def> = MOVi64imm 4; GPR64:%vreg331
12688B		%vreg332<def> = MADDXrrr %vreg339, %vreg331, %XZR; GPR64:%vreg332,%vreg339,%vreg331
12704B		%vreg333<def> = ADDXrr %vreg334, %vreg332; GPR64common:%vreg333 GPR64:%vreg334,%vreg332
12720B		%vreg328<def> = LDRWui %vreg333, 0; mem:LD4[%arrayidx386] GPR32:%vreg328 GPR64common:%vreg333
12736B		STRWui %vreg328, <fi#9>, 0; mem:ST4[FixedStack9] GPR32:%vreg328
12752B		%vreg325<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32:%vreg325
12768B		%vreg322<def> = ANDWri %vreg325, 7; GPR32common:%vreg322 GPR32:%vreg325
12800B		STRBBui %vreg322, <fi#2>, 0; mem:ST1[FixedStack2] GPR32common:%vreg322
12816B		%vreg319<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32:%vreg319
12832B		%vreg318<def> = UBFMWri %vreg319, 8, 31; GPR32:%vreg318,%vreg319
12848B		STRWui %vreg318, <fi#9>, 0; mem:ST4[FixedStack9] GPR32:%vreg318
12864B		%vreg315<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32common:%vreg315
12880B		%vreg314<def> = ADDWri %vreg315, 1, 0; GPR32common:%vreg314,%vreg315
12896B		STRWui %vreg314, <fi#6>, 0; mem:ST4[FixedStack6] GPR32common:%vreg314
12912B		%vreg311<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32common:%vreg311
12928B		%vreg308<def> = ADDWri %vreg311, 4, 0; GPR32common:%vreg308,%vreg311
12944B		STRWui %vreg308, <fi#5>, 0; mem:ST4[FixedStack5] GPR32common:%vreg308
12960B		%vreg305:sub_32<def,read-undef> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR64:%vreg305
12992B		%vreg300<def> = LDRXui <fi#8>, 0; mem:LD8[FixedStack8] GPR64:%vreg300
13008B		%vreg297<def> = MOVi64imm 4; GPR64:%vreg297
13024B		%vreg298<def> = MADDXrrr %vreg305, %vreg297, %XZR; GPR64:%vreg298,%vreg305,%vreg297
13040B		%vreg299<def> = ADDXrr %vreg300, %vreg298; GPR64common:%vreg299 GPR64:%vreg300,%vreg298
13056B		%vreg294<def> = LDRWui %vreg299, 0; mem:LD4[%arrayidx394] GPR32:%vreg294 GPR64common:%vreg299
13072B		STRWui %vreg294, <fi#9>, 0; mem:ST4[FixedStack9] GPR32:%vreg294
13088B		%vreg291<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32:%vreg291
13104B		%vreg288<def> = ANDWri %vreg291, 7; GPR32common:%vreg288 GPR32:%vreg291
13136B		%vreg286<def> = UBFMWri %vreg288, 0, 7; GPR32:%vreg286 GPR32common:%vreg288
13152B		STRWui %vreg286, <fi#7>, 0; mem:ST4[FixedStack7] GPR32:%vreg286
13168B		%vreg283<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32:%vreg283
13184B		%vreg282<def> = UBFMWri %vreg283, 8, 31; GPR32:%vreg282,%vreg283
13200B		STRWui %vreg282, <fi#9>, 0; mem:ST4[FixedStack9] GPR32:%vreg282
13216B		%vreg279<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32common:%vreg279
13232B		%vreg278<def> = ADDWri %vreg279, 1, 0; GPR32common:%vreg278,%vreg279
13248B		STRWui %vreg278, <fi#6>, 0; mem:ST4[FixedStack6] GPR32common:%vreg278
13264B		B <BB#48>
	    Successors according to CFG: BB#48

13280B	BB#76: derived from LLVM BB %return_notr
	    Predecessors according to CFG: BB#62 BB#57 BB#51
13296B		%vreg381<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg381
13312B		%vreg380<def> = LDRXui %vreg381, 0; mem:LD8[%strm400] GPR64common:%vreg380,%vreg381
13328B		%vreg378<def> = LDRWui %vreg380, 9; mem:LD4[%total_out_lo32401] GPR32:%vreg378 GPR64common:%vreg380
13344B		STRWui %vreg378, <fi#14>, 0; mem:ST4[FixedStack14] GPR32:%vreg378
13360B		%vreg375<def> = LDRWui <fi#12>, 0; mem:LD4[FixedStack12] GPR32:%vreg375
13376B		%vreg374<def> = LDRWui <fi#11>, 0; mem:LD4[FixedStack11] GPR32:%vreg374
13392B		%vreg373<def> = SUBWrr %vreg375, %vreg374; GPR32:%vreg373,%vreg375,%vreg374
13408B		%vreg370<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg370
13424B		%vreg369<def> = LDRXui %vreg370, 0; mem:LD8[%strm402] GPR64common:%vreg369,%vreg370
13440B		%vreg367<def> = LDRWui %vreg369, 9; mem:LD4[%total_out_lo32403] GPR32:%vreg367 GPR64common:%vreg369
13456B		%vreg366<def> = ADDWrr %vreg367, %vreg373; GPR32:%vreg366,%vreg367,%vreg373
13472B		STRWui %vreg366, %vreg369, 9; mem:ST4[%total_out_lo32403] GPR32:%vreg366 GPR64common:%vreg369
13488B		%vreg361<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg361
13504B		%vreg360<def> = LDRXui %vreg361, 0; mem:LD8[%strm405] GPR64common:%vreg360,%vreg361
13520B		%vreg358<def> = LDRWui %vreg360, 9; mem:LD4[%total_out_lo32406] GPR32:%vreg358 GPR64common:%vreg360
13536B		%vreg356<def> = LDRWui <fi#14>, 0; mem:LD4[FixedStack14] GPR32:%vreg356
13552B		%WZR<def> = SUBSWrr %vreg358, %vreg356, %NZCV<imp-def>; GPR32:%vreg358,%vreg356
13568B		Bcc 2, <BB#78>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#78 BB#77

13584B	BB#77: derived from LLVM BB %if.then.409
	    Predecessors according to CFG: BB#76
13600B		%vreg389<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg389
13616B		%vreg388<def> = LDRXui %vreg389, 0; mem:LD8[%strm410] GPR64common:%vreg388,%vreg389
13632B		%vreg386<def> = LDRWui %vreg388, 10; mem:LD4[%total_out_hi32411] GPR32common:%vreg386 GPR64common:%vreg388
13648B		%vreg385<def> = ADDWri %vreg386, 1, 0; GPR32common:%vreg385,%vreg386
13664B		STRWui %vreg385, %vreg388, 10; mem:ST4[%total_out_hi32411] GPR32common:%vreg385 GPR64common:%vreg388
	    Successors according to CFG: BB#78

13680B	BB#78: derived from LLVM BB %if.end.413
	    Predecessors according to CFG: BB#76 BB#77
13696B		%vreg429<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg429
13712B		%vreg428<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg428
13728B		STRWui %vreg429, %vreg428, 796; mem:ST4[%calculatedBlockCRC414] GPR32:%vreg429 GPR64common:%vreg428
13744B		%vreg425<def> = LDRBBui <fi#4>, 0; mem:LD1[FixedStack4] GPR32:%vreg425
13760B		%vreg424<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg424
13776B		STRBBui %vreg425, %vreg424, 12; mem:ST1[%state_out_ch415] GPR32:%vreg425 GPR64common:%vreg424
13792B		%vreg421<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32:%vreg421
13808B		%vreg420<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg420
13824B		STRWui %vreg421, %vreg420, 4; mem:ST4[%state_out_len416] GPR32:%vreg421 GPR64common:%vreg420
13840B		%vreg417<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg417
13856B		%vreg416<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg416
13872B		STRWui %vreg417, %vreg416, 273; mem:ST4[%nblock_used417] GPR32:%vreg417 GPR64common:%vreg416
13888B		%vreg413<def> = LDRWui <fi#7>, 0; mem:LD4[FixedStack7] GPR32:%vreg413
13904B		%vreg412<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg412
13920B		STRWui %vreg413, %vreg412, 16; mem:ST4[%k0418] GPR32:%vreg413 GPR64common:%vreg412
13936B		%vreg409<def> = LDRXui <fi#8>, 0; mem:LD8[FixedStack8] GPR64:%vreg409
13952B		%vreg408<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg408
13968B		STRXui %vreg409, %vreg408, 394; mem:ST8[%tt419] GPR64:%vreg409 GPR64common:%vreg408
13984B		%vreg405<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32:%vreg405
14000B		%vreg404<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg404
14016B		STRWui %vreg405, %vreg404, 15; mem:ST4[%tPos420] GPR32:%vreg405 GPR64common:%vreg404
14032B		%vreg401<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg401
14048B		%vreg400<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg400
14064B		%vreg399<def> = LDRXui %vreg400, 0; mem:LD8[%strm421] GPR64common:%vreg399,%vreg400
14080B		STRXui %vreg401, %vreg399, 3; mem:ST8[%next_out422] GPR64:%vreg401 GPR64common:%vreg399
14096B		%vreg395<def> = LDRWui <fi#11>, 0; mem:LD4[FixedStack11] GPR32:%vreg395
14112B		%vreg394<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg394
14128B		%vreg393<def> = LDRXui %vreg394, 0; mem:LD8[%strm423] GPR64common:%vreg393,%vreg394
14144B		STRWui %vreg395, %vreg393, 8; mem:ST4[%avail_out424] GPR32:%vreg395 GPR64common:%vreg393
	    Successors according to CFG: BB#79

14160B	BB#79: derived from LLVM BB %if.end.425
	    Predecessors according to CFG: BB#78
14176B		STRBBui %WZR, <fi#0>, 0; mem:ST1[FixedStack0]
	    Successors according to CFG: BB#80

14192B	BB#80: derived from LLVM BB %return
	    Predecessors according to CFG: BB#60 BB#79 BB#13 BB#11 BB#4
14208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
14224B		%vreg1133<def> = MOVaddr <ga:@unRLE_obuf_to_output_FAST>[TF=1], <ga:@unRLE_obuf_to_output_FAST>[TF=34]; GPR64:%vreg1133
14240B		%X0<def> = COPY %vreg1133; GPR64:%vreg1133
14256B		%X1<def> = COPY %vreg10; GPR64:%vreg10
14272B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %SP<imp-def>
14288B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
14304B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
14320B		STACKMAP 1, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=1)
14336B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
14352B		%vreg1134<def> = LDRBBui <fi#0>, 0; mem:LD1[%retval] GPR32:%vreg1134
14384B		%W0<def> = COPY %vreg1134; GPR32:%vreg1134
14400B		RET_ReallyLR %W0<imp-use>

# End machine code for function unRLE_obuf_to_output_FAST.

AllocationOrder(GPR32sponly) = [ ]
handleMove 992B -> 1016B: %vreg481<def> = EORWrs %vreg483, %vreg507, 8; GPR32:%vreg481,%vreg483,%vreg507
     %vreg481:	[992r,1024r:0)  0@992r
        -->	[1016r,1024r:0)  0@1016r
     %vreg483:	[976r,992r:0)  0@976r
        -->	[976r,1016r:0)  0@976r
     %vreg507:	[784r,992r:0)  0@784r
        -->	[784r,1016r:0)  0@784r
handleMove 832B -> 872B: %vreg502<def> = UBFMWri %vreg504, 24, 31; GPR32:%vreg502,%vreg504
     %vreg502:	[832r,880r:0)  0@832r
        -->	[872r,880r:0)  0@872r
     %vreg504:	[816r,832r:0)  0@816r
        -->	[816r,872r:0)  0@816r
handleMove 784B -> 868B: %vreg507<def> = LDRWui %vreg508, 796; mem:LD4[%calculatedBlockCRC] GPR32:%vreg507 GPR64common:%vreg508
     %vreg507:	[784r,1016r:0)  0@784r
        -->	[868r,1016r:0)  0@868r
     %vreg508:	[768r,784r:0)  0@768r
        -->	[768r,868r:0)  0@768r
handleMove 656B -> 872B: %vreg485<def> = ADDXri %vreg484, <ga:@BZ2_crc32Table>[TF=34], 0; GPR64common:%vreg485,%vreg484
     %vreg485:	[656r,960r:0)  0@656r
        -->	[872r,960r:0)  0@872r
     %vreg484:	[640r,656r:0)  0@640r
        -->	[640r,872r:0)  0@640r
handleMove 816B -> 856B: %vreg504<def> = LDRWui %vreg505, 796; mem:LD4[%calculatedBlockCRC8] GPR32:%vreg504 GPR64common:%vreg505
     %vreg504:	[816r,888r:0)  0@816r
        -->	[856r,888r:0)  0@856r
     %vreg505:	[800r,816r:0)  0@800r
        -->	[800r,856r:0)  0@800r
handleMove 768B -> 852B: %vreg508<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg508
     %vreg508:	[768r,880r:0)  0@768r
        -->	[852r,880r:0)  0@852r
handleMove 640B -> 856B: %vreg484<def> = ADRP <ga:@BZ2_crc32Table>[TF=1]; GPR64common:%vreg484
     %vreg484:	[640r,888r:0)  0@640r
        -->	[856r,888r:0)  0@856r
handleMove 688B -> 728B: %vreg517<def> = LDRBBui %vreg518, 12; mem:LD1[%state_out_ch] GPR32:%vreg517 GPR64common:%vreg518
     %vreg517:	[688r,752r:0)  0@688r
        -->	[728r,752r:0)  0@728r
     %vreg518:	[672r,688r:0)  0@672r
        -->	[672r,728r:0)  0@672r
handleMove 672B -> 712B: %vreg518<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg518
     %vreg518:	[672r,728r:0)  0@672r
        -->	[712r,728r:0)  0@712r
handleMove 1568B -> 1640B: %vreg537<def> = LDRWui %vreg538, 273; mem:LD4[%nblock_used] GPR32:%vreg537 GPR64common:%vreg538
     %vreg537:	[1568r,1664r:0)  0@1568r
        -->	[1640r,1664r:0)  0@1640r
     %vreg538:	[1552r,1568r:0)  0@1552r
        -->	[1552r,1640r:0)  0@1552r
handleMove 1552B -> 1592B: %vreg538<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg538
     %vreg538:	[1552r,1640r:0)  0@1552r
        -->	[1592r,1640r:0)  0@1592r
handleMove 1776B -> 1848B: %vreg549<def> = LDRWui %vreg550, 273; mem:LD4[%nblock_used31] GPR32:%vreg549 GPR64common:%vreg550
     %vreg549:	[1776r,1872r:0)  0@1776r
        -->	[1848r,1872r:0)  0@1848r
     %vreg550:	[1760r,1776r:0)  0@1760r
        -->	[1760r,1848r:0)  0@1760r
handleMove 1760B -> 1800B: %vreg550<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg550
     %vreg550:	[1760r,1848r:0)  0@1760r
        -->	[1800r,1848r:0)  0@1800r
AllocationOrder(GPR32sponly) = [ ]
handleMove 2128B -> 2168B: %vreg587:sub_32<def,read-undef> = LDRWui %vreg588, 15; mem:LD4[%tPos] GPR64:%vreg587 GPR64common:%vreg588
     %vreg587:	[2128r,2208r:0)  0@2128r
        -->	[2168r,2208r:0)  0@2168r
     %vreg588:	[2112r,2128r:0)  0@2112r
        -->	[2112r,2168r:0)  0@2112r
handleMove 2048B -> 2088B: %vreg593<def> = LDRWui %vreg596, 16; mem:LD4[%k0] GPR32:%vreg593 GPR64common:%vreg596
     %vreg593:	[2048r,2096r:0)  0@2048r
        -->	[2088r,2096r:0)  0@2088r
     %vreg596:	[2032r,2048r:0)  0@2032r
        -->	[2032r,2088r:0)  0@2032r
handleMove 1984B -> 2008B: %vreg597<def> = MOVi32imm 1; GPR32:%vreg597
     %vreg597:	[1984r,2016r:0)  0@1984r
        -->	[2008r,2016r:0)  0@2008r
AllocationOrder(GPR32sponly) = [ ]
handleMove 2512B -> 2568B: %vreg616<def> = ADDXri %vreg615, <ga:@BZ2_rNums>[TF=34], 0; GPR64common:%vreg616,%vreg615
     %vreg616:	[2512r,2592r:0)  0@2512r
        -->	[2568r,2592r:0)  0@2568r
     %vreg615:	[2496r,2512r:0)  0@2496r
        -->	[2496r,2568r:0)  0@2496r
handleMove 2496B -> 2552B: %vreg615<def> = ADRP <ga:@BZ2_rNums>[TF=1]; GPR64common:%vreg615
     %vreg615:	[2496r,2568r:0)  0@2496r
        -->	[2552r,2568r:0)  0@2552r
AllocationOrder(GPR32sponly) = [ ]
handleMove 3184B -> 3256B: %vreg639<def> = LDRWui %vreg640, 273; mem:LD4[%nblock_used73] GPR32:%vreg639 GPR64common:%vreg640
     %vreg639:	[3184r,3280r:0)  0@3184r
        -->	[3256r,3280r:0)  0@3256r
     %vreg640:	[3168r,3184r:0)  0@3168r
        -->	[3168r,3256r:0)  0@3168r
handleMove 3168B -> 3208B: %vreg640<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg640
     %vreg640:	[3168r,3256r:0)  0@3168r
        -->	[3208r,3256r:0)  0@3208r
handleMove 3024B -> 3048B: %vreg659<def> = CSELWr %vreg657, %vreg658, 0, %NZCV<imp-use,kill>; GPR32:%vreg659,%vreg657,%vreg658
     %vreg659:	[3024r,3056r:0)  0@3024r
        -->	[3048r,3056r:0)  0@3048r
     %vreg657:	[2880r,3024r:0)  0@2880r
        -->	[2880r,3048r:0)  0@2880r
     %vreg658:	[2896r,3024r:0)  0@2896r
        -->	[2896r,3048r:0)  0@2896r
     NZCV:	[1664r,1680r:17)[1872r,1888r:16)[2752r,2768r:15)[3008r,3048r:13)[3280r,3296r:14)[3408r,3424r:12)[4224r,4240r:11)[4480r,4496r:9)[4752r,4768r:10)[4880r,4896r:8)[5696r,5712r:7)[5952r,5968r:5)[6224r,6240r:6)[6352r,6368r:4)[7120r,7136r:3)[7376r,7392r:2)[8272r,8288r:1)[8528r,8544r:0)[9344r,9360r:28)[9520r,9536r:27)[10640r,10656r:26)[10784r,10800r:25)[11248r,11264r:24)[11392r,11408r:23)[11824r,11840r:22)[11936r,11952r:21)[12400r,12416r:20)[12512r,12528r:19)[13552r,13568r:18)  0@8528r 1@8272r 2@7376r 3@7120r 4@6352r 5@5952r 6@6224r 7@5696r 8@4880r 9@4480r 10@4752r 11@4224r 12@3408r 13@3008r 14@3280r 15@2752r 16@1872r 17@1664r 18@13552r 19@12512r 20@12400r 21@11936r 22@11824r 23@11392r 24@11248r 25@10784r 26@10640r 27@9520r 28@9344r
        -->	[1664r,1680r:17)[1872r,1888r:16)[2752r,2768r:15)[3008r,3048r:13)[3280r,3296r:14)[3408r,3424r:12)[4224r,4240r:11)[4480r,4496r:9)[4752r,4768r:10)[4880r,4896r:8)[5696r,5712r:7)[5952r,5968r:5)[6224r,6240r:6)[6352r,6368r:4)[7120r,7136r:3)[7376r,7392r:2)[8272r,8288r:1)[8528r,8544r:0)[9344r,9360r:28)[9520r,9536r:27)[10640r,10656r:26)[10784r,10800r:25)[11248r,11264r:24)[11392r,11408r:23)[11824r,11840r:22)[11936r,11952r:21)[12400r,12416r:20)[12512r,12528r:19)[13552r,13568r:18)  0@8528r 1@8272r 2@7376r 3@7120r 4@6352r 5@5952r 6@6224r 7@5696r 8@4880r 9@4480r 10@4752r 11@4224r 12@3408r 13@3008r 14@3280r 15@2752r 16@1872r 17@1664r 18@13552r 19@12512r 20@12400r 21@11936r 22@11824r 23@11392r 24@11248r 25@10784r 26@10640r 27@9520r 28@9344r
handleMove 2896B -> 2872B: %vreg658<def> = COPY %WZR; GPR32:%vreg658
     %vreg658:	[2896r,3048r:0)  0@2896r
        -->	[2872r,3048r:0)  0@2872r
     WZR:	[1664r,1664d:17)[1872r,1872d:16)[2752r,2752d:15)[3008r,3008d:13)[3280r,3280d:14)[3408r,3408d:12)[4224r,4224d:11)[4480r,4480d:9)[4752r,4752d:10)[4880r,4880d:8)[5696r,5696d:7)[5952r,5952d:5)[6224r,6224d:6)[6352r,6352d:4)[7120r,7120d:3)[7376r,7376d:2)[8272r,8272d:1)[8528r,8528d:0)[9344r,9344d:28)[9520r,9520d:27)[10640r,10640d:26)[10784r,10784d:25)[11248r,11248d:24)[11392r,11392d:23)[11824r,11824d:22)[11936r,11936d:21)[12400r,12400d:20)[12512r,12512d:19)[13552r,13552d:18)  0@8528r 1@8272r 2@7376r 3@7120r 4@6352r 5@5952r 6@6224r 7@5696r 8@4880r 9@4480r 10@4752r 11@4224r 12@3408r 13@3008r 14@3280r 15@2752r 16@1872r 17@1664r 18@13552r 19@12512r 20@12400r 21@11936r 22@11824r 23@11392r 24@11248r 25@10784r 26@10640r 27@9520r 28@9344r
        -->	[1664r,1664d:17)[1872r,1872d:16)[2752r,2752d:15)[3008r,3008d:13)[3280r,3280d:14)[3408r,3408d:12)[4224r,4224d:11)[4480r,4480d:9)[4752r,4752d:10)[4880r,4880d:8)[5696r,5696d:7)[5952r,5952d:5)[6224r,6224d:6)[6352r,6352d:4)[7120r,7120d:3)[7376r,7376d:2)[8272r,8272d:1)[8528r,8528d:0)[9344r,9344d:28)[9520r,9520d:27)[10640r,10640d:26)[10784r,10784d:25)[11248r,11248d:24)[11392r,11392d:23)[11824r,11824d:22)[11936r,11936d:21)[12400r,12400d:20)[12512r,12512d:19)[13552r,13552d:18)  0@8528r 1@8272r 2@7376r 3@7120r 4@6352r 5@5952r 6@6224r 7@5696r 8@4880r 9@4480r 10@4752r 11@4224r 12@3408r 13@3008r 14@3280r 15@2752r 16@1872r 17@1664r 18@13552r 19@12512r 20@12400r 21@11936r 22@11824r 23@11392r 24@11248r 25@10784r 26@10640r 27@9520r 28@9344r
handleMove 3008B -> 3044B: %WZR<def> = SUBSWri %vreg661, 1, 0, %NZCV<imp-def>; GPR32common:%vreg661
     WZR:	[1664r,1664d:17)[1872r,1872d:16)[2752r,2752d:15)[3008r,3008d:13)[3280r,3280d:14)[3408r,3408d:12)[4224r,4224d:11)[4480r,4480d:9)[4752r,4752d:10)[4880r,4880d:8)[5696r,5696d:7)[5952r,5952d:5)[6224r,6224d:6)[6352r,6352d:4)[7120r,7120d:3)[7376r,7376d:2)[8272r,8272d:1)[8528r,8528d:0)[9344r,9344d:28)[9520r,9520d:27)[10640r,10640d:26)[10784r,10784d:25)[11248r,11248d:24)[11392r,11392d:23)[11824r,11824d:22)[11936r,11936d:21)[12400r,12400d:20)[12512r,12512d:19)[13552r,13552d:18)  0@8528r 1@8272r 2@7376r 3@7120r 4@6352r 5@5952r 6@6224r 7@5696r 8@4880r 9@4480r 10@4752r 11@4224r 12@3408r 13@3008r 14@3280r 15@2752r 16@1872r 17@1664r 18@13552r 19@12512r 20@12400r 21@11936r 22@11824r 23@11392r 24@11248r 25@10784r 26@10640r 27@9520r 28@9344r
        -->	[1664r,1664d:17)[1872r,1872d:16)[2752r,2752d:15)[3044r,3044d:13)[3280r,3280d:14)[3408r,3408d:12)[4224r,4224d:11)[4480r,4480d:9)[4752r,4752d:10)[4880r,4880d:8)[5696r,5696d:7)[5952r,5952d:5)[6224r,6224d:6)[6352r,6352d:4)[7120r,7120d:3)[7376r,7376d:2)[8272r,8272d:1)[8528r,8528d:0)[9344r,9344d:28)[9520r,9520d:27)[10640r,10640d:26)[10784r,10784d:25)[11248r,11248d:24)[11392r,11392d:23)[11824r,11824d:22)[11936r,11936d:21)[12400r,12400d:20)[12512r,12512d:19)[13552r,13552d:18)  0@8528r 1@8272r 2@7376r 3@7120r 4@6352r 5@5952r 6@6224r 7@5696r 8@4880r 9@4480r 10@4752r 11@4224r 12@3408r 13@3044r 14@3280r 15@2752r 16@1872r 17@1664r 18@13552r 19@12512r 20@12400r 21@11936r 22@11824r 23@11392r 24@11248r 25@10784r 26@10640r 27@9520r 28@9344r
     %vreg661:	[2992r,3008r:0)  0@2992r
        -->	[2992r,3044r:0)  0@2992r
     NZCV:	[1664r,1680r:17)[1872r,1888r:16)[2752r,2768r:15)[3008r,3048r:13)[3280r,3296r:14)[3408r,3424r:12)[4224r,4240r:11)[4480r,4496r:9)[4752r,4768r:10)[4880r,4896r:8)[5696r,5712r:7)[5952r,5968r:5)[6224r,6240r:6)[6352r,6368r:4)[7120r,7136r:3)[7376r,7392r:2)[8272r,8288r:1)[8528r,8544r:0)[9344r,9360r:28)[9520r,9536r:27)[10640r,10656r:26)[10784r,10800r:25)[11248r,11264r:24)[11392r,11408r:23)[11824r,11840r:22)[11936r,11952r:21)[12400r,12416r:20)[12512r,12528r:19)[13552r,13568r:18)  0@8528r 1@8272r 2@7376r 3@7120r 4@6352r 5@5952r 6@6224r 7@5696r 8@4880r 9@4480r 10@4752r 11@4224r 12@3408r 13@3008r 14@3280r 15@2752r 16@1872r 17@1664r 18@13552r 19@12512r 20@12400r 21@11936r 22@11824r 23@11392r 24@11248r 25@10784r 26@10640r 27@9520r 28@9344r
        -->	[1664r,1680r:17)[1872r,1888r:16)[2752r,2768r:15)[3044r,3048r:13)[3280r,3296r:14)[3408r,3424r:12)[4224r,4240r:11)[4480r,4496r:9)[4752r,4768r:10)[4880r,4896r:8)[5696r,5712r:7)[5952r,5968r:5)[6224r,6240r:6)[6352r,6368r:4)[7120r,7136r:3)[7376r,7392r:2)[8272r,8288r:1)[8528r,8544r:0)[9344r,9360r:28)[9520r,9536r:27)[10640r,10656r:26)[10784r,10800r:25)[11248r,11264r:24)[11392r,11408r:23)[11824r,11840r:22)[11936r,11952r:21)[12400r,12416r:20)[12512r,12528r:19)[13552r,13568r:18)  0@8528r 1@8272r 2@7376r 3@7120r 4@6352r 5@5952r 6@6224r 7@5696r 8@4880r 9@4480r 10@4752r 11@4224r 12@3408r 13@3044r 14@3280r 15@2752r 16@1872r 17@1664r 18@13552r 19@12512r 20@12400r 21@11936r 22@11824r 23@11392r 24@11248r 25@10784r 26@10640r 27@9520r 28@9344r
handleMove 2880B -> 3048B: %vreg657<def> = MOVi32imm 1; GPR32:%vreg657
     %vreg657:	[2880r,3064r:0)  0@2880r
        -->	[3048r,3064r:0)  0@3048r
handleMove 3360B -> 3384B: %vreg676<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg676
     %vreg676:	[3360r,3408r:0)  0@3360r
        -->	[3384r,3408r:0)  0@3384r
AllocationOrder(GPR32sponly) = [ ]
handleMove 3600B -> 3640B: %vreg713:sub_32<def,read-undef> = LDRWui %vreg714, 15; mem:LD4[%tPos89] GPR64:%vreg713 GPR64common:%vreg714
     %vreg713:	[3600r,3680r:0)  0@3600r
        -->	[3640r,3680r:0)  0@3640r
     %vreg714:	[3584r,3600r:0)  0@3584r
        -->	[3584r,3640r:0)  0@3584r
handleMove 3536B -> 3560B: %vreg715<def> = MOVi32imm 2; GPR32:%vreg715
     %vreg715:	[3536r,3568r:0)  0@3536r
        -->	[3560r,3568r:0)  0@3560r
AllocationOrder(GPR32sponly) = [ ]
handleMove 3984B -> 4040B: %vreg734<def> = ADDXri %vreg733, <ga:@BZ2_rNums>[TF=34], 0; GPR64common:%vreg734,%vreg733
     %vreg734:	[3984r,4064r:0)  0@3984r
        -->	[4040r,4064r:0)  0@4040r
     %vreg733:	[3968r,3984r:0)  0@3968r
        -->	[3968r,4040r:0)  0@3968r
handleMove 3968B -> 4024B: %vreg733<def> = ADRP <ga:@BZ2_rNums>[TF=1]; GPR64common:%vreg733
     %vreg733:	[3968r,4040r:0)  0@3968r
        -->	[4024r,4040r:0)  0@4024r
AllocationOrder(GPR32sponly) = [ ]
handleMove 4656B -> 4728B: %vreg757<def> = LDRWui %vreg758, 273; mem:LD4[%nblock_used127] GPR32:%vreg757 GPR64common:%vreg758
     %vreg757:	[4656r,4752r:0)  0@4656r
        -->	[4728r,4752r:0)  0@4728r
     %vreg758:	[4640r,4656r:0)  0@4640r
        -->	[4640r,4728r:0)  0@4640r
handleMove 4640B -> 4680B: %vreg758<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg758
     %vreg758:	[4640r,4728r:0)  0@4640r
        -->	[4680r,4728r:0)  0@4680r
handleMove 4496B -> 4520B: %vreg777<def> = CSELWr %vreg775, %vreg776, 0, %NZCV<imp-use>; GPR32:%vreg777,%vreg775,%vreg776
     %vreg777:	[4496r,4528r:0)  0@4496r
        -->	[4520r,4528r:0)  0@4520r
     %vreg775:	[4352r,4496r:0)  0@4352r
        -->	[4352r,4520r:0)  0@4352r
     %vreg776:	[4368r,4496r:0)  0@4368r
        -->	[4368r,4520r:0)  0@4368r
     NZCV:	[1664r,1680r:17)[1872r,1888r:16)[2752r,2768r:15)[3056r,3064r:13)[3280r,3296r:14)[3408r,3424r:12)[4224r,4240r:11)[4480r,4496r:9)[4752r,4768r:10)[4880r,4896r:8)[5696r,5712r:7)[5952r,5968r:5)[6224r,6240r:6)[6352r,6368r:4)[7120r,7136r:3)[7376r,7392r:2)[8272r,8288r:1)[8528r,8544r:0)[9344r,9360r:28)[9520r,9536r:27)[10640r,10656r:26)[10784r,10800r:25)[11248r,11264r:24)[11392r,11408r:23)[11824r,11840r:22)[11936r,11952r:21)[12400r,12416r:20)[12512r,12528r:19)[13552r,13568r:18)  0@8528r 1@8272r 2@7376r 3@7120r 4@6352r 5@5952r 6@6224r 7@5696r 8@4880r 9@4480r 10@4752r 11@4224r 12@3408r 13@3056r 14@3280r 15@2752r 16@1872r 17@1664r 18@13552r 19@12512r 20@12400r 21@11936r 22@11824r 23@11392r 24@11248r 25@10784r 26@10640r 27@9520r 28@9344r
        -->	[1664r,1680r:17)[1872r,1888r:16)[2752r,2768r:15)[3056r,3064r:13)[3280r,3296r:14)[3408r,3424r:12)[4224r,4240r:11)[4480r,4520r:9)[4752r,4768r:10)[4880r,4896r:8)[5696r,5712r:7)[5952r,5968r:5)[6224r,6240r:6)[6352r,6368r:4)[7120r,7136r:3)[7376r,7392r:2)[8272r,8288r:1)[8528r,8544r:0)[9344r,9360r:28)[9520r,9536r:27)[10640r,10656r:26)[10784r,10800r:25)[11248r,11264r:24)[11392r,11408r:23)[11824r,11840r:22)[11936r,11952r:21)[12400r,12416r:20)[12512r,12528r:19)[13552r,13568r:18)  0@8528r 1@8272r 2@7376r 3@7120r 4@6352r 5@5952r 6@6224r 7@5696r 8@4880r 9@4480r 10@4752r 11@4224r 12@3408r 13@3056r 14@3280r 15@2752r 16@1872r 17@1664r 18@13552r 19@12512r 20@12400r 21@11936r 22@11824r 23@11392r 24@11248r 25@10784r 26@10640r 27@9520r 28@9344r
handleMove 4368B -> 4344B: %vreg776<def> = COPY %WZR; GPR32:%vreg776
     %vreg776:	[4368r,4520r:0)  0@4368r
        -->	[4344r,4520r:0)  0@4344r
     WZR:	[1664r,1664d:17)[1872r,1872d:16)[2752r,2752d:15)[3056r,3056d:13)[3280r,3280d:14)[3408r,3408d:12)[4224r,4224d:11)[4480r,4480d:9)[4752r,4752d:10)[4880r,4880d:8)[5696r,5696d:7)[5952r,5952d:5)[6224r,6224d:6)[6352r,6352d:4)[7120r,7120d:3)[7376r,7376d:2)[8272r,8272d:1)[8528r,8528d:0)[9344r,9344d:28)[9520r,9520d:27)[10640r,10640d:26)[10784r,10784d:25)[11248r,11248d:24)[11392r,11392d:23)[11824r,11824d:22)[11936r,11936d:21)[12400r,12400d:20)[12512r,12512d:19)[13552r,13552d:18)  0@8528r 1@8272r 2@7376r 3@7120r 4@6352r 5@5952r 6@6224r 7@5696r 8@4880r 9@4480r 10@4752r 11@4224r 12@3408r 13@3056r 14@3280r 15@2752r 16@1872r 17@1664r 18@13552r 19@12512r 20@12400r 21@11936r 22@11824r 23@11392r 24@11248r 25@10784r 26@10640r 27@9520r 28@9344r
        -->	[1664r,1664d:17)[1872r,1872d:16)[2752r,2752d:15)[3056r,3056d:13)[3280r,3280d:14)[3408r,3408d:12)[4224r,4224d:11)[4480r,4480d:9)[4752r,4752d:10)[4880r,4880d:8)[5696r,5696d:7)[5952r,5952d:5)[6224r,6224d:6)[6352r,6352d:4)[7120r,7120d:3)[7376r,7376d:2)[8272r,8272d:1)[8528r,8528d:0)[9344r,9344d:28)[9520r,9520d:27)[10640r,10640d:26)[10784r,10784d:25)[11248r,11248d:24)[11392r,11392d:23)[11824r,11824d:22)[11936r,11936d:21)[12400r,12400d:20)[12512r,12512d:19)[13552r,13552d:18)  0@8528r 1@8272r 2@7376r 3@7120r 4@6352r 5@5952r 6@6224r 7@5696r 8@4880r 9@4480r 10@4752r 11@4224r 12@3408r 13@3056r 14@3280r 15@2752r 16@1872r 17@1664r 18@13552r 19@12512r 20@12400r 21@11936r 22@11824r 23@11392r 24@11248r 25@10784r 26@10640r 27@9520r 28@9344r
handleMove 4480B -> 4516B: %WZR<def> = SUBSWri %vreg779, 1, 0, %NZCV<imp-def>; GPR32common:%vreg779
     WZR:	[1664r,1664d:17)[1872r,1872d:16)[2752r,2752d:15)[3056r,3056d:13)[3280r,3280d:14)[3408r,3408d:12)[4224r,4224d:11)[4480r,4480d:9)[4752r,4752d:10)[4880r,4880d:8)[5696r,5696d:7)[5952r,5952d:5)[6224r,6224d:6)[6352r,6352d:4)[7120r,7120d:3)[7376r,7376d:2)[8272r,8272d:1)[8528r,8528d:0)[9344r,9344d:28)[9520r,9520d:27)[10640r,10640d:26)[10784r,10784d:25)[11248r,11248d:24)[11392r,11392d:23)[11824r,11824d:22)[11936r,11936d:21)[12400r,12400d:20)[12512r,12512d:19)[13552r,13552d:18)  0@8528r 1@8272r 2@7376r 3@7120r 4@6352r 5@5952r 6@6224r 7@5696r 8@4880r 9@4480r 10@4752r 11@4224r 12@3408r 13@3056r 14@3280r 15@2752r 16@1872r 17@1664r 18@13552r 19@12512r 20@12400r 21@11936r 22@11824r 23@11392r 24@11248r 25@10784r 26@10640r 27@9520r 28@9344r
        -->	[1664r,1664d:17)[1872r,1872d:16)[2752r,2752d:15)[3056r,3056d:13)[3280r,3280d:14)[3408r,3408d:12)[4224r,4224d:11)[4516r,4516d:9)[4752r,4752d:10)[4880r,4880d:8)[5696r,5696d:7)[5952r,5952d:5)[6224r,6224d:6)[6352r,6352d:4)[7120r,7120d:3)[7376r,7376d:2)[8272r,8272d:1)[8528r,8528d:0)[9344r,9344d:28)[9520r,9520d:27)[10640r,10640d:26)[10784r,10784d:25)[11248r,11248d:24)[11392r,11392d:23)[11824r,11824d:22)[11936r,11936d:21)[12400r,12400d:20)[12512r,12512d:19)[13552r,13552d:18)  0@8528r 1@8272r 2@7376r 3@7120r 4@6352r 5@5952r 6@6224r 7@5696r 8@4880r 9@4516r 10@4752r 11@4224r 12@3408r 13@3056r 14@3280r 15@2752r 16@1872r 17@1664r 18@13552r 19@12512r 20@12400r 21@11936r 22@11824r 23@11392r 24@11248r 25@10784r 26@10640r 27@9520r 28@9344r
     %vreg779:	[4464r,4480r:0)  0@4464r
        -->	[4464r,4516r:0)  0@4464r
     NZCV:	[1664r,1680r:17)[1872r,1888r:16)[2752r,2768r:15)[3056r,3064r:13)[3280r,3296r:14)[3408r,3424r:12)[4224r,4240r:11)[4480r,4520r:9)[4752r,4768r:10)[4880r,4896r:8)[5696r,5712r:7)[5952r,5968r:5)[6224r,6240r:6)[6352r,6368r:4)[7120r,7136r:3)[7376r,7392r:2)[8272r,8288r:1)[8528r,8544r:0)[9344r,9360r:28)[9520r,9536r:27)[10640r,10656r:26)[10784r,10800r:25)[11248r,11264r:24)[11392r,11408r:23)[11824r,11840r:22)[11936r,11952r:21)[12400r,12416r:20)[12512r,12528r:19)[13552r,13568r:18)  0@8528r 1@8272r 2@7376r 3@7120r 4@6352r 5@5952r 6@6224r 7@5696r 8@4880r 9@4480r 10@4752r 11@4224r 12@3408r 13@3056r 14@3280r 15@2752r 16@1872r 17@1664r 18@13552r 19@12512r 20@12400r 21@11936r 22@11824r 23@11392r 24@11248r 25@10784r 26@10640r 27@9520r 28@9344r
        -->	[1664r,1680r:17)[1872r,1888r:16)[2752r,2768r:15)[3056r,3064r:13)[3280r,3296r:14)[3408r,3424r:12)[4224r,4240r:11)[4516r,4520r:9)[4752r,4768r:10)[4880r,4896r:8)[5696r,5712r:7)[5952r,5968r:5)[6224r,6240r:6)[6352r,6368r:4)[7120r,7136r:3)[7376r,7392r:2)[8272r,8288r:1)[8528r,8544r:0)[9344r,9360r:28)[9520r,9536r:27)[10640r,10656r:26)[10784r,10800r:25)[11248r,11264r:24)[11392r,11408r:23)[11824r,11840r:22)[11936r,11952r:21)[12400r,12416r:20)[12512r,12528r:19)[13552r,13568r:18)  0@8528r 1@8272r 2@7376r 3@7120r 4@6352r 5@5952r 6@6224r 7@5696r 8@4880r 9@4516r 10@4752r 11@4224r 12@3408r 13@3056r 14@3280r 15@2752r 16@1872r 17@1664r 18@13552r 19@12512r 20@12400r 21@11936r 22@11824r 23@11392r 24@11248r 25@10784r 26@10640r 27@9520r 28@9344r
handleMove 4352B -> 4520B: %vreg775<def> = MOVi32imm 1; GPR32:%vreg775
     %vreg775:	[4352r,4536r:0)  0@4352r
        -->	[4520r,4536r:0)  0@4520r
handleMove 4832B -> 4856B: %vreg794<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg794
     %vreg794:	[4832r,4880r:0)  0@4832r
        -->	[4856r,4880r:0)  0@4856r
AllocationOrder(GPR32sponly) = [ ]
handleMove 5072B -> 5112B: %vreg831:sub_32<def,read-undef> = LDRWui %vreg832, 15; mem:LD4[%tPos143] GPR64:%vreg831 GPR64common:%vreg832
     %vreg831:	[5072r,5152r:0)  0@5072r
        -->	[5112r,5152r:0)  0@5112r
     %vreg832:	[5056r,5072r:0)  0@5056r
        -->	[5056r,5112r:0)  0@5056r
handleMove 5008B -> 5032B: %vreg833<def> = MOVi32imm 3; GPR32:%vreg833
     %vreg833:	[5008r,5040r:0)  0@5008r
        -->	[5032r,5040r:0)  0@5032r
AllocationOrder(GPR32sponly) = [ ]
handleMove 5456B -> 5512B: %vreg852<def> = ADDXri %vreg851, <ga:@BZ2_rNums>[TF=34], 0; GPR64common:%vreg852,%vreg851
     %vreg852:	[5456r,5536r:0)  0@5456r
        -->	[5512r,5536r:0)  0@5512r
     %vreg851:	[5440r,5456r:0)  0@5440r
        -->	[5440r,5512r:0)  0@5440r
handleMove 5440B -> 5496B: %vreg851<def> = ADRP <ga:@BZ2_rNums>[TF=1]; GPR64common:%vreg851
     %vreg851:	[5440r,5512r:0)  0@5440r
        -->	[5496r,5512r:0)  0@5496r
AllocationOrder(GPR32sponly) = [ ]
handleMove 6128B -> 6200B: %vreg875<def> = LDRWui %vreg876, 273; mem:LD4[%nblock_used181] GPR32:%vreg875 GPR64common:%vreg876
     %vreg875:	[6128r,6224r:0)  0@6128r
        -->	[6200r,6224r:0)  0@6200r
     %vreg876:	[6112r,6128r:0)  0@6112r
        -->	[6112r,6200r:0)  0@6112r
handleMove 6112B -> 6152B: %vreg876<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg876
     %vreg876:	[6112r,6200r:0)  0@6112r
        -->	[6152r,6200r:0)  0@6152r
handleMove 5968B -> 5992B: %vreg895<def> = CSELWr %vreg893, %vreg894, 0, %NZCV<imp-use>; GPR32:%vreg895,%vreg893,%vreg894
     %vreg895:	[5968r,6000r:0)  0@5968r
        -->	[5992r,6000r:0)  0@5992r
     %vreg893:	[5824r,5968r:0)  0@5824r
        -->	[5824r,5992r:0)  0@5824r
     %vreg894:	[5840r,5968r:0)  0@5840r
        -->	[5840r,5992r:0)  0@5840r
     NZCV:	[1664r,1680r:17)[1872r,1888r:16)[2752r,2768r:15)[3056r,3064r:13)[3280r,3296r:14)[3408r,3424r:12)[4224r,4240r:11)[4528r,4536r:9)[4752r,4768r:10)[4880r,4896r:8)[5696r,5712r:7)[5952r,5968r:5)[6224r,6240r:6)[6352r,6368r:4)[7120r,7136r:3)[7376r,7392r:2)[8272r,8288r:1)[8528r,8544r:0)[9344r,9360r:28)[9520r,9536r:27)[10640r,10656r:26)[10784r,10800r:25)[11248r,11264r:24)[11392r,11408r:23)[11824r,11840r:22)[11936r,11952r:21)[12400r,12416r:20)[12512r,12528r:19)[13552r,13568r:18)  0@8528r 1@8272r 2@7376r 3@7120r 4@6352r 5@5952r 6@6224r 7@5696r 8@4880r 9@4528r 10@4752r 11@4224r 12@3408r 13@3056r 14@3280r 15@2752r 16@1872r 17@1664r 18@13552r 19@12512r 20@12400r 21@11936r 22@11824r 23@11392r 24@11248r 25@10784r 26@10640r 27@9520r 28@9344r
        -->	[1664r,1680r:17)[1872r,1888r:16)[2752r,2768r:15)[3056r,3064r:13)[3280r,3296r:14)[3408r,3424r:12)[4224r,4240r:11)[4528r,4536r:9)[4752r,4768r:10)[4880r,4896r:8)[5696r,5712r:7)[5952r,5992r:5)[6224r,6240r:6)[6352r,6368r:4)[7120r,7136r:3)[7376r,7392r:2)[8272r,8288r:1)[8528r,8544r:0)[9344r,9360r:28)[9520r,9536r:27)[10640r,10656r:26)[10784r,10800r:25)[11248r,11264r:24)[11392r,11408r:23)[11824r,11840r:22)[11936r,11952r:21)[12400r,12416r:20)[12512r,12528r:19)[13552r,13568r:18)  0@8528r 1@8272r 2@7376r 3@7120r 4@6352r 5@5952r 6@6224r 7@5696r 8@4880r 9@4528r 10@4752r 11@4224r 12@3408r 13@3056r 14@3280r 15@2752r 16@1872r 17@1664r 18@13552r 19@12512r 20@12400r 21@11936r 22@11824r 23@11392r 24@11248r 25@10784r 26@10640r 27@9520r 28@9344r
handleMove 5840B -> 5816B: %vreg894<def> = COPY %WZR; GPR32:%vreg894
     %vreg894:	[5840r,5992r:0)  0@5840r
        -->	[5816r,5992r:0)  0@5816r
     WZR:	[1664r,1664d:17)[1872r,1872d:16)[2752r,2752d:15)[3056r,3056d:13)[3280r,3280d:14)[3408r,3408d:12)[4224r,4224d:11)[4528r,4528d:9)[4752r,4752d:10)[4880r,4880d:8)[5696r,5696d:7)[5952r,5952d:5)[6224r,6224d:6)[6352r,6352d:4)[7120r,7120d:3)[7376r,7376d:2)[8272r,8272d:1)[8528r,8528d:0)[9344r,9344d:28)[9520r,9520d:27)[10640r,10640d:26)[10784r,10784d:25)[11248r,11248d:24)[11392r,11392d:23)[11824r,11824d:22)[11936r,11936d:21)[12400r,12400d:20)[12512r,12512d:19)[13552r,13552d:18)  0@8528r 1@8272r 2@7376r 3@7120r 4@6352r 5@5952r 6@6224r 7@5696r 8@4880r 9@4528r 10@4752r 11@4224r 12@3408r 13@3056r 14@3280r 15@2752r 16@1872r 17@1664r 18@13552r 19@12512r 20@12400r 21@11936r 22@11824r 23@11392r 24@11248r 25@10784r 26@10640r 27@9520r 28@9344r
        -->	[1664r,1664d:17)[1872r,1872d:16)[2752r,2752d:15)[3056r,3056d:13)[3280r,3280d:14)[3408r,3408d:12)[4224r,4224d:11)[4528r,4528d:9)[4752r,4752d:10)[4880r,4880d:8)[5696r,5696d:7)[5952r,5952d:5)[6224r,6224d:6)[6352r,6352d:4)[7120r,7120d:3)[7376r,7376d:2)[8272r,8272d:1)[8528r,8528d:0)[9344r,9344d:28)[9520r,9520d:27)[10640r,10640d:26)[10784r,10784d:25)[11248r,11248d:24)[11392r,11392d:23)[11824r,11824d:22)[11936r,11936d:21)[12400r,12400d:20)[12512r,12512d:19)[13552r,13552d:18)  0@8528r 1@8272r 2@7376r 3@7120r 4@6352r 5@5952r 6@6224r 7@5696r 8@4880r 9@4528r 10@4752r 11@4224r 12@3408r 13@3056r 14@3280r 15@2752r 16@1872r 17@1664r 18@13552r 19@12512r 20@12400r 21@11936r 22@11824r 23@11392r 24@11248r 25@10784r 26@10640r 27@9520r 28@9344r
handleMove 5952B -> 5988B: %WZR<def> = SUBSWri %vreg897, 1, 0, %NZCV<imp-def>; GPR32common:%vreg897
     WZR:	[1664r,1664d:17)[1872r,1872d:16)[2752r,2752d:15)[3056r,3056d:13)[3280r,3280d:14)[3408r,3408d:12)[4224r,4224d:11)[4528r,4528d:9)[4752r,4752d:10)[4880r,4880d:8)[5696r,5696d:7)[5952r,5952d:5)[6224r,6224d:6)[6352r,6352d:4)[7120r,7120d:3)[7376r,7376d:2)[8272r,8272d:1)[8528r,8528d:0)[9344r,9344d:28)[9520r,9520d:27)[10640r,10640d:26)[10784r,10784d:25)[11248r,11248d:24)[11392r,11392d:23)[11824r,11824d:22)[11936r,11936d:21)[12400r,12400d:20)[12512r,12512d:19)[13552r,13552d:18)  0@8528r 1@8272r 2@7376r 3@7120r 4@6352r 5@5952r 6@6224r 7@5696r 8@4880r 9@4528r 10@4752r 11@4224r 12@3408r 13@3056r 14@3280r 15@2752r 16@1872r 17@1664r 18@13552r 19@12512r 20@12400r 21@11936r 22@11824r 23@11392r 24@11248r 25@10784r 26@10640r 27@9520r 28@9344r
        -->	[1664r,1664d:17)[1872r,1872d:16)[2752r,2752d:15)[3056r,3056d:13)[3280r,3280d:14)[3408r,3408d:12)[4224r,4224d:11)[4528r,4528d:9)[4752r,4752d:10)[4880r,4880d:8)[5696r,5696d:7)[5988r,5988d:5)[6224r,6224d:6)[6352r,6352d:4)[7120r,7120d:3)[7376r,7376d:2)[8272r,8272d:1)[8528r,8528d:0)[9344r,9344d:28)[9520r,9520d:27)[10640r,10640d:26)[10784r,10784d:25)[11248r,11248d:24)[11392r,11392d:23)[11824r,11824d:22)[11936r,11936d:21)[12400r,12400d:20)[12512r,12512d:19)[13552r,13552d:18)  0@8528r 1@8272r 2@7376r 3@7120r 4@6352r 5@5988r 6@6224r 7@5696r 8@4880r 9@4528r 10@4752r 11@4224r 12@3408r 13@3056r 14@3280r 15@2752r 16@1872r 17@1664r 18@13552r 19@12512r 20@12400r 21@11936r 22@11824r 23@11392r 24@11248r 25@10784r 26@10640r 27@9520r 28@9344r
     %vreg897:	[5936r,5952r:0)  0@5936r
        -->	[5936r,5988r:0)  0@5936r
     NZCV:	[1664r,1680r:17)[1872r,1888r:16)[2752r,2768r:15)[3056r,3064r:13)[3280r,3296r:14)[3408r,3424r:12)[4224r,4240r:11)[4528r,4536r:9)[4752r,4768r:10)[4880r,4896r:8)[5696r,5712r:7)[5952r,5992r:5)[6224r,6240r:6)[6352r,6368r:4)[7120r,7136r:3)[7376r,7392r:2)[8272r,8288r:1)[8528r,8544r:0)[9344r,9360r:28)[9520r,9536r:27)[10640r,10656r:26)[10784r,10800r:25)[11248r,11264r:24)[11392r,11408r:23)[11824r,11840r:22)[11936r,11952r:21)[12400r,12416r:20)[12512r,12528r:19)[13552r,13568r:18)  0@8528r 1@8272r 2@7376r 3@7120r 4@6352r 5@5952r 6@6224r 7@5696r 8@4880r 9@4528r 10@4752r 11@4224r 12@3408r 13@3056r 14@3280r 15@2752r 16@1872r 17@1664r 18@13552r 19@12512r 20@12400r 21@11936r 22@11824r 23@11392r 24@11248r 25@10784r 26@10640r 27@9520r 28@9344r
        -->	[1664r,1680r:17)[1872r,1888r:16)[2752r,2768r:15)[3056r,3064r:13)[3280r,3296r:14)[3408r,3424r:12)[4224r,4240r:11)[4528r,4536r:9)[4752r,4768r:10)[4880r,4896r:8)[5696r,5712r:7)[5988r,5992r:5)[6224r,6240r:6)[6352r,6368r:4)[7120r,7136r:3)[7376r,7392r:2)[8272r,8288r:1)[8528r,8544r:0)[9344r,9360r:28)[9520r,9536r:27)[10640r,10656r:26)[10784r,10800r:25)[11248r,11264r:24)[11392r,11408r:23)[11824r,11840r:22)[11936r,11952r:21)[12400r,12416r:20)[12512r,12528r:19)[13552r,13568r:18)  0@8528r 1@8272r 2@7376r 3@7120r 4@6352r 5@5988r 6@6224r 7@5696r 8@4880r 9@4528r 10@4752r 11@4224r 12@3408r 13@3056r 14@3280r 15@2752r 16@1872r 17@1664r 18@13552r 19@12512r 20@12400r 21@11936r 22@11824r 23@11392r 24@11248r 25@10784r 26@10640r 27@9520r 28@9344r
handleMove 5824B -> 5992B: %vreg893<def> = MOVi32imm 1; GPR32:%vreg893
     %vreg893:	[5824r,6008r:0)  0@5824r
        -->	[5992r,6008r:0)  0@5992r
handleMove 6304B -> 6328B: %vreg912<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg912
     %vreg912:	[6304r,6352r:0)  0@6304r
        -->	[6328r,6352r:0)  0@6328r
AllocationOrder(GPR32sponly) = [ ]
handleMove 6496B -> 6536B: %vreg949:sub_32<def,read-undef> = LDRWui %vreg950, 15; mem:LD4[%tPos196] GPR64:%vreg949 GPR64common:%vreg950
     %vreg949:	[6496r,6576r:0)  0@6496r
        -->	[6536r,6576r:0)  0@6536r
     %vreg950:	[6480r,6496r:0)  0@6480r
        -->	[6480r,6536r:0)  0@6480r
AllocationOrder(GPR32sponly) = [ ]
handleMove 6880B -> 6936B: %vreg967<def> = ADDXri %vreg966, <ga:@BZ2_rNums>[TF=34], 0; GPR64common:%vreg967,%vreg966
     %vreg967:	[6880r,6960r:0)  0@6880r
        -->	[6936r,6960r:0)  0@6936r
     %vreg966:	[6864r,6880r:0)  0@6864r
        -->	[6864r,6936r:0)  0@6864r
handleMove 6864B -> 6920B: %vreg966<def> = ADRP <ga:@BZ2_rNums>[TF=1]; GPR64common:%vreg966
     %vreg966:	[6864r,6936r:0)  0@6864r
        -->	[6920r,6936r:0)  0@6920r
AllocationOrder(GPR32sponly) = [ ]
handleMove 7840B -> 7864B: %vreg994<def> = UBFMWri %vreg996, 0, 7; GPR32:%vreg994 GPR32common:%vreg996
     %vreg994:	[7840r,7872r:0)  0@7840r
        -->	[7864r,7872r:0)  0@7864r
     %vreg996:	[7808r,7840r:0)  0@7808r
        -->	[7808r,7864r:0)  0@7808r
handleMove 7808B -> 7860B: %vreg996<def> = ANDWri %vreg1000, 7; GPR32common:%vreg996 GPR32:%vreg1000
     %vreg996:	[7808r,7864r:0)  0@7808r
        -->	[7860r,7864r:0)  0@7860r
     %vreg1000:	[7792r,7808r:0)  0@7792r
        -->	[7792r,7860r:0)  0@7792r
handleMove 7264B -> 7240B: %vreg1047<def> = COPY %WZR; GPR32:%vreg1047
     %vreg1047:	[7264r,7392r:0)  0@7264r
        -->	[7240r,7392r:0)  0@7240r
     WZR:	[1664r,1664d:17)[1872r,1872d:16)[2752r,2752d:15)[3056r,3056d:13)[3280r,3280d:14)[3408r,3408d:12)[4224r,4224d:11)[4528r,4528d:9)[4752r,4752d:10)[4880r,4880d:8)[5696r,5696d:7)[6000r,6000d:5)[6224r,6224d:6)[6352r,6352d:4)[7120r,7120d:3)[7376r,7376d:2)[8272r,8272d:1)[8528r,8528d:0)[9344r,9344d:28)[9520r,9520d:27)[10640r,10640d:26)[10784r,10784d:25)[11248r,11248d:24)[11392r,11392d:23)[11824r,11824d:22)[11936r,11936d:21)[12400r,12400d:20)[12512r,12512d:19)[13552r,13552d:18)  0@8528r 1@8272r 2@7376r 3@7120r 4@6352r 5@6000r 6@6224r 7@5696r 8@4880r 9@4528r 10@4752r 11@4224r 12@3408r 13@3056r 14@3280r 15@2752r 16@1872r 17@1664r 18@13552r 19@12512r 20@12400r 21@11936r 22@11824r 23@11392r 24@11248r 25@10784r 26@10640r 27@9520r 28@9344r
        -->	[1664r,1664d:17)[1872r,1872d:16)[2752r,2752d:15)[3056r,3056d:13)[3280r,3280d:14)[3408r,3408d:12)[4224r,4224d:11)[4528r,4528d:9)[4752r,4752d:10)[4880r,4880d:8)[5696r,5696d:7)[6000r,6000d:5)[6224r,6224d:6)[6352r,6352d:4)[7120r,7120d:3)[7376r,7376d:2)[8272r,8272d:1)[8528r,8528d:0)[9344r,9344d:28)[9520r,9520d:27)[10640r,10640d:26)[10784r,10784d:25)[11248r,11248d:24)[11392r,11392d:23)[11824r,11824d:22)[11936r,11936d:21)[12400r,12400d:20)[12512r,12512d:19)[13552r,13552d:18)  0@8528r 1@8272r 2@7376r 3@7120r 4@6352r 5@6000r 6@6224r 7@5696r 8@4880r 9@4528r 10@4752r 11@4224r 12@3408r 13@3056r 14@3280r 15@2752r 16@1872r 17@1664r 18@13552r 19@12512r 20@12400r 21@11936r 22@11824r 23@11392r 24@11248r 25@10784r 26@10640r 27@9520r 28@9344r
handleMove 7616B -> 7656B: %vreg1020:sub_32<def,read-undef> = LDRWui %vreg1021, 15; mem:LD4[%tPos237] GPR64:%vreg1020 GPR64common:%vreg1021
     %vreg1020:	[7616r,7696r:0)  0@7616r
        -->	[7656r,7696r:0)  0@7656r
     %vreg1021:	[7600r,7616r:0)  0@7600r
        -->	[7600r,7656r:0)  0@7600r
handleMove 7552B -> 7576B: %vreg1026<def> = ADDWri %vreg1029, 4, 0; GPR32common:%vreg1026,%vreg1029
     %vreg1026:	[7552r,7584r:0)  0@7552r
        -->	[7576r,7584r:0)  0@7576r
     %vreg1029:	[7536r,7552r:0)  0@7536r
        -->	[7536r,7576r:0)  0@7536r
handleMove 7392B -> 7416B: %vreg1048<def> = CSELWr %vreg1046, %vreg1047, 0, %NZCV<imp-use>; GPR32:%vreg1048,%vreg1046,%vreg1047
     %vreg1048:	[7392r,7424r:0)  0@7392r
        -->	[7416r,7424r:0)  0@7416r
     %vreg1046:	[7248r,7392r:0)  0@7248r
        -->	[7248r,7416r:0)  0@7248r
     %vreg1047:	[7240r,7392r:0)  0@7240r
        -->	[7240r,7416r:0)  0@7240r
     NZCV:	[1664r,1680r:17)[1872r,1888r:16)[2752r,2768r:15)[3056r,3064r:13)[3280r,3296r:14)[3408r,3424r:12)[4224r,4240r:11)[4528r,4536r:9)[4752r,4768r:10)[4880r,4896r:8)[5696r,5712r:7)[6000r,6008r:5)[6224r,6240r:6)[6352r,6368r:4)[7120r,7136r:3)[7376r,7392r:2)[8272r,8288r:1)[8528r,8544r:0)[9344r,9360r:28)[9520r,9536r:27)[10640r,10656r:26)[10784r,10800r:25)[11248r,11264r:24)[11392r,11408r:23)[11824r,11840r:22)[11936r,11952r:21)[12400r,12416r:20)[12512r,12528r:19)[13552r,13568r:18)  0@8528r 1@8272r 2@7376r 3@7120r 4@6352r 5@6000r 6@6224r 7@5696r 8@4880r 9@4528r 10@4752r 11@4224r 12@3408r 13@3056r 14@3280r 15@2752r 16@1872r 17@1664r 18@13552r 19@12512r 20@12400r 21@11936r 22@11824r 23@11392r 24@11248r 25@10784r 26@10640r 27@9520r 28@9344r
        -->	[1664r,1680r:17)[1872r,1888r:16)[2752r,2768r:15)[3056r,3064r:13)[3280r,3296r:14)[3408r,3424r:12)[4224r,4240r:11)[4528r,4536r:9)[4752r,4768r:10)[4880r,4896r:8)[5696r,5712r:7)[6000r,6008r:5)[6224r,6240r:6)[6352r,6368r:4)[7120r,7136r:3)[7376r,7416r:2)[8272r,8288r:1)[8528r,8544r:0)[9344r,9360r:28)[9520r,9536r:27)[10640r,10656r:26)[10784r,10800r:25)[11248r,11264r:24)[11392r,11408r:23)[11824r,11840r:22)[11936r,11952r:21)[12400r,12416r:20)[12512r,12528r:19)[13552r,13568r:18)  0@8528r 1@8272r 2@7376r 3@7120r 4@6352r 5@6000r 6@6224r 7@5696r 8@4880r 9@4528r 10@4752r 11@4224r 12@3408r 13@3056r 14@3280r 15@2752r 16@1872r 17@1664r 18@13552r 19@12512r 20@12400r 21@11936r 22@11824r 23@11392r 24@11248r 25@10784r 26@10640r 27@9520r 28@9344r
handleMove 7376B -> 7412B: %WZR<def> = SUBSWri %vreg1050, 1, 0, %NZCV<imp-def>; GPR32common:%vreg1050
     WZR:	[1664r,1664d:17)[1872r,1872d:16)[2752r,2752d:15)[3056r,3056d:13)[3280r,3280d:14)[3408r,3408d:12)[4224r,4224d:11)[4528r,4528d:9)[4752r,4752d:10)[4880r,4880d:8)[5696r,5696d:7)[6000r,6000d:5)[6224r,6224d:6)[6352r,6352d:4)[7120r,7120d:3)[7376r,7376d:2)[8272r,8272d:1)[8528r,8528d:0)[9344r,9344d:28)[9520r,9520d:27)[10640r,10640d:26)[10784r,10784d:25)[11248r,11248d:24)[11392r,11392d:23)[11824r,11824d:22)[11936r,11936d:21)[12400r,12400d:20)[12512r,12512d:19)[13552r,13552d:18)  0@8528r 1@8272r 2@7376r 3@7120r 4@6352r 5@6000r 6@6224r 7@5696r 8@4880r 9@4528r 10@4752r 11@4224r 12@3408r 13@3056r 14@3280r 15@2752r 16@1872r 17@1664r 18@13552r 19@12512r 20@12400r 21@11936r 22@11824r 23@11392r 24@11248r 25@10784r 26@10640r 27@9520r 28@9344r
        -->	[1664r,1664d:17)[1872r,1872d:16)[2752r,2752d:15)[3056r,3056d:13)[3280r,3280d:14)[3408r,3408d:12)[4224r,4224d:11)[4528r,4528d:9)[4752r,4752d:10)[4880r,4880d:8)[5696r,5696d:7)[6000r,6000d:5)[6224r,6224d:6)[6352r,6352d:4)[7120r,7120d:3)[7412r,7412d:2)[8272r,8272d:1)[8528r,8528d:0)[9344r,9344d:28)[9520r,9520d:27)[10640r,10640d:26)[10784r,10784d:25)[11248r,11248d:24)[11392r,11392d:23)[11824r,11824d:22)[11936r,11936d:21)[12400r,12400d:20)[12512r,12512d:19)[13552r,13552d:18)  0@8528r 1@8272r 2@7412r 3@7120r 4@6352r 5@6000r 6@6224r 7@5696r 8@4880r 9@4528r 10@4752r 11@4224r 12@3408r 13@3056r 14@3280r 15@2752r 16@1872r 17@1664r 18@13552r 19@12512r 20@12400r 21@11936r 22@11824r 23@11392r 24@11248r 25@10784r 26@10640r 27@9520r 28@9344r
     %vreg1050:	[7360r,7376r:0)  0@7360r
        -->	[7360r,7412r:0)  0@7360r
     NZCV:	[1664r,1680r:17)[1872r,1888r:16)[2752r,2768r:15)[3056r,3064r:13)[3280r,3296r:14)[3408r,3424r:12)[4224r,4240r:11)[4528r,4536r:9)[4752r,4768r:10)[4880r,4896r:8)[5696r,5712r:7)[6000r,6008r:5)[6224r,6240r:6)[6352r,6368r:4)[7120r,7136r:3)[7376r,7416r:2)[8272r,8288r:1)[8528r,8544r:0)[9344r,9360r:28)[9520r,9536r:27)[10640r,10656r:26)[10784r,10800r:25)[11248r,11264r:24)[11392r,11408r:23)[11824r,11840r:22)[11936r,11952r:21)[12400r,12416r:20)[12512r,12528r:19)[13552r,13568r:18)  0@8528r 1@8272r 2@7376r 3@7120r 4@6352r 5@6000r 6@6224r 7@5696r 8@4880r 9@4528r 10@4752r 11@4224r 12@3408r 13@3056r 14@3280r 15@2752r 16@1872r 17@1664r 18@13552r 19@12512r 20@12400r 21@11936r 22@11824r 23@11392r 24@11248r 25@10784r 26@10640r 27@9520r 28@9344r
        -->	[1664r,1680r:17)[1872r,1888r:16)[2752r,2768r:15)[3056r,3064r:13)[3280r,3296r:14)[3408r,3424r:12)[4224r,4240r:11)[4528r,4536r:9)[4752r,4768r:10)[4880r,4896r:8)[5696r,5712r:7)[6000r,6008r:5)[6224r,6240r:6)[6352r,6368r:4)[7120r,7136r:3)[7412r,7416r:2)[8272r,8288r:1)[8528r,8544r:0)[9344r,9360r:28)[9520r,9536r:27)[10640r,10656r:26)[10784r,10800r:25)[11248r,11264r:24)[11392r,11408r:23)[11824r,11840r:22)[11936r,11952r:21)[12400r,12416r:20)[12512r,12528r:19)[13552r,13568r:18)  0@8528r 1@8272r 2@7412r 3@7120r 4@6352r 5@6000r 6@6224r 7@5696r 8@4880r 9@4528r 10@4752r 11@4224r 12@3408r 13@3056r 14@3280r 15@2752r 16@1872r 17@1664r 18@13552r 19@12512r 20@12400r 21@11936r 22@11824r 23@11392r 24@11248r 25@10784r 26@10640r 27@9520r 28@9344r
handleMove 7248B -> 7416B: %vreg1046<def> = MOVi32imm 1; GPR32:%vreg1046
     %vreg1046:	[7248r,7432r:0)  0@7248r
        -->	[7416r,7432r:0)  0@7416r
AllocationOrder(GPR32sponly) = [ ]
handleMove 8032B -> 8088B: %vreg1074<def> = ADDXri %vreg1073, <ga:@BZ2_rNums>[TF=34], 0; GPR64common:%vreg1074,%vreg1073
     %vreg1074:	[8032r,8112r:0)  0@8032r
        -->	[8088r,8112r:0)  0@8088r
     %vreg1073:	[8016r,8032r:0)  0@8016r
        -->	[8016r,8088r:0)  0@8016r
handleMove 8016B -> 8072B: %vreg1073<def> = ADRP <ga:@BZ2_rNums>[TF=1]; GPR64common:%vreg1073
     %vreg1073:	[8016r,8088r:0)  0@8016r
        -->	[8072r,8088r:0)  0@8072r
AllocationOrder(GPR32sponly) = [ ]
handleMove 8544B -> 8584B: %vreg1103<def> = CSELWr %vreg1101, %vreg1102, 0, %NZCV<imp-use>; GPR32:%vreg1103,%vreg1101,%vreg1102
     %vreg1103:	[8544r,8592r:0)  0@8544r
        -->	[8584r,8592r:0)  0@8584r
     %vreg1101:	[8400r,8544r:0)  0@8400r
        -->	[8400r,8584r:0)  0@8400r
     %vreg1102:	[8416r,8544r:0)  0@8416r
        -->	[8416r,8584r:0)  0@8416r
     NZCV:	[1664r,1680r:17)[1872r,1888r:16)[2752r,2768r:15)[3056r,3064r:13)[3280r,3296r:14)[3408r,3424r:12)[4224r,4240r:11)[4528r,4536r:9)[4752r,4768r:10)[4880r,4896r:8)[5696r,5712r:7)[6000r,6008r:5)[6224r,6240r:6)[6352r,6368r:4)[7120r,7136r:3)[7424r,7432r:2)[8272r,8288r:1)[8528r,8544r:0)[9344r,9360r:28)[9520r,9536r:27)[10640r,10656r:26)[10784r,10800r:25)[11248r,11264r:24)[11392r,11408r:23)[11824r,11840r:22)[11936r,11952r:21)[12400r,12416r:20)[12512r,12528r:19)[13552r,13568r:18)  0@8528r 1@8272r 2@7424r 3@7120r 4@6352r 5@6000r 6@6224r 7@5696r 8@4880r 9@4528r 10@4752r 11@4224r 12@3408r 13@3056r 14@3280r 15@2752r 16@1872r 17@1664r 18@13552r 19@12512r 20@12400r 21@11936r 22@11824r 23@11392r 24@11248r 25@10784r 26@10640r 27@9520r 28@9344r
        -->	[1664r,1680r:17)[1872r,1888r:16)[2752r,2768r:15)[3056r,3064r:13)[3280r,3296r:14)[3408r,3424r:12)[4224r,4240r:11)[4528r,4536r:9)[4752r,4768r:10)[4880r,4896r:8)[5696r,5712r:7)[6000r,6008r:5)[6224r,6240r:6)[6352r,6368r:4)[7120r,7136r:3)[7424r,7432r:2)[8272r,8288r:1)[8528r,8584r:0)[9344r,9360r:28)[9520r,9536r:27)[10640r,10656r:26)[10784r,10800r:25)[11248r,11264r:24)[11392r,11408r:23)[11824r,11840r:22)[11936r,11952r:21)[12400r,12416r:20)[12512r,12528r:19)[13552r,13568r:18)  0@8528r 1@8272r 2@7424r 3@7120r 4@6352r 5@6000r 6@6224r 7@5696r 8@4880r 9@4528r 10@4752r 11@4224r 12@3408r 13@3056r 14@3280r 15@2752r 16@1872r 17@1664r 18@13552r 19@12512r 20@12400r 21@11936r 22@11824r 23@11392r 24@11248r 25@10784r 26@10640r 27@9520r 28@9344r
handleMove 8416B -> 8392B: %vreg1102<def> = COPY %WZR; GPR32:%vreg1102
     %vreg1102:	[8416r,8584r:0)  0@8416r
        -->	[8392r,8584r:0)  0@8392r
     WZR:	[1664r,1664d:17)[1872r,1872d:16)[2752r,2752d:15)[3056r,3056d:13)[3280r,3280d:14)[3408r,3408d:12)[4224r,4224d:11)[4528r,4528d:9)[4752r,4752d:10)[4880r,4880d:8)[5696r,5696d:7)[6000r,6000d:5)[6224r,6224d:6)[6352r,6352d:4)[7120r,7120d:3)[7424r,7424d:2)[8272r,8272d:1)[8528r,8528d:0)[9344r,9344d:28)[9520r,9520d:27)[10640r,10640d:26)[10784r,10784d:25)[11248r,11248d:24)[11392r,11392d:23)[11824r,11824d:22)[11936r,11936d:21)[12400r,12400d:20)[12512r,12512d:19)[13552r,13552d:18)  0@8528r 1@8272r 2@7424r 3@7120r 4@6352r 5@6000r 6@6224r 7@5696r 8@4880r 9@4528r 10@4752r 11@4224r 12@3408r 13@3056r 14@3280r 15@2752r 16@1872r 17@1664r 18@13552r 19@12512r 20@12400r 21@11936r 22@11824r 23@11392r 24@11248r 25@10784r 26@10640r 27@9520r 28@9344r
        -->	[1664r,1664d:17)[1872r,1872d:16)[2752r,2752d:15)[3056r,3056d:13)[3280r,3280d:14)[3408r,3408d:12)[4224r,4224d:11)[4528r,4528d:9)[4752r,4752d:10)[4880r,4880d:8)[5696r,5696d:7)[6000r,6000d:5)[6224r,6224d:6)[6352r,6352d:4)[7120r,7120d:3)[7424r,7424d:2)[8272r,8272d:1)[8528r,8528d:0)[9344r,9344d:28)[9520r,9520d:27)[10640r,10640d:26)[10784r,10784d:25)[11248r,11248d:24)[11392r,11392d:23)[11824r,11824d:22)[11936r,11936d:21)[12400r,12400d:20)[12512r,12512d:19)[13552r,13552d:18)  0@8528r 1@8272r 2@7424r 3@7120r 4@6352r 5@6000r 6@6224r 7@5696r 8@4880r 9@4528r 10@4752r 11@4224r 12@3408r 13@3056r 14@3280r 15@2752r 16@1872r 17@1664r 18@13552r 19@12512r 20@12400r 21@11936r 22@11824r 23@11392r 24@11248r 25@10784r 26@10640r 27@9520r 28@9344r
handleMove 8400B -> 8580B: %vreg1101<def> = MOVi32imm 1; GPR32:%vreg1101
     %vreg1101:	[8400r,8584r:0)  0@8400r
        -->	[8580r,8584r:0)  0@8580r
handleMove 8528B -> 8584B: %WZR<def> = SUBSWri %vreg1105, 1, 0, %NZCV<imp-def>; GPR32common:%vreg1105
     WZR:	[1664r,1664d:17)[1872r,1872d:16)[2752r,2752d:15)[3056r,3056d:13)[3280r,3280d:14)[3408r,3408d:12)[4224r,4224d:11)[4528r,4528d:9)[4752r,4752d:10)[4880r,4880d:8)[5696r,5696d:7)[6000r,6000d:5)[6224r,6224d:6)[6352r,6352d:4)[7120r,7120d:3)[7424r,7424d:2)[8272r,8272d:1)[8528r,8528d:0)[9344r,9344d:28)[9520r,9520d:27)[10640r,10640d:26)[10784r,10784d:25)[11248r,11248d:24)[11392r,11392d:23)[11824r,11824d:22)[11936r,11936d:21)[12400r,12400d:20)[12512r,12512d:19)[13552r,13552d:18)  0@8528r 1@8272r 2@7424r 3@7120r 4@6352r 5@6000r 6@6224r 7@5696r 8@4880r 9@4528r 10@4752r 11@4224r 12@3408r 13@3056r 14@3280r 15@2752r 16@1872r 17@1664r 18@13552r 19@12512r 20@12400r 21@11936r 22@11824r 23@11392r 24@11248r 25@10784r 26@10640r 27@9520r 28@9344r
        -->	[1664r,1664d:17)[1872r,1872d:16)[2752r,2752d:15)[3056r,3056d:13)[3280r,3280d:14)[3408r,3408d:12)[4224r,4224d:11)[4528r,4528d:9)[4752r,4752d:10)[4880r,4880d:8)[5696r,5696d:7)[6000r,6000d:5)[6224r,6224d:6)[6352r,6352d:4)[7120r,7120d:3)[7424r,7424d:2)[8272r,8272d:1)[8584r,8584d:0)[9344r,9344d:28)[9520r,9520d:27)[10640r,10640d:26)[10784r,10784d:25)[11248r,11248d:24)[11392r,11392d:23)[11824r,11824d:22)[11936r,11936d:21)[12400r,12400d:20)[12512r,12512d:19)[13552r,13552d:18)  0@8584r 1@8272r 2@7424r 3@7120r 4@6352r 5@6000r 6@6224r 7@5696r 8@4880r 9@4528r 10@4752r 11@4224r 12@3408r 13@3056r 14@3280r 15@2752r 16@1872r 17@1664r 18@13552r 19@12512r 20@12400r 21@11936r 22@11824r 23@11392r 24@11248r 25@10784r 26@10640r 27@9520r 28@9344r
     %vreg1105:	[8512r,8528r:0)  0@8512r
        -->	[8512r,8584r:0)  0@8512r
     NZCV:	[1664r,1680r:17)[1872r,1888r:16)[2752r,2768r:15)[3056r,3064r:13)[3280r,3296r:14)[3408r,3424r:12)[4224r,4240r:11)[4528r,4536r:9)[4752r,4768r:10)[4880r,4896r:8)[5696r,5712r:7)[6000r,6008r:5)[6224r,6240r:6)[6352r,6368r:4)[7120r,7136r:3)[7424r,7432r:2)[8272r,8288r:1)[8528r,8600r:0)[9344r,9360r:28)[9520r,9536r:27)[10640r,10656r:26)[10784r,10800r:25)[11248r,11264r:24)[11392r,11408r:23)[11824r,11840r:22)[11936r,11952r:21)[12400r,12416r:20)[12512r,12528r:19)[13552r,13568r:18)  0@8528r 1@8272r 2@7424r 3@7120r 4@6352r 5@6000r 6@6224r 7@5696r 8@4880r 9@4528r 10@4752r 11@4224r 12@3408r 13@3056r 14@3280r 15@2752r 16@1872r 17@1664r 18@13552r 19@12512r 20@12400r 21@11936r 22@11824r 23@11392r 24@11248r 25@10784r 26@10640r 27@9520r 28@9344r
        -->	[1664r,1680r:17)[1872r,1888r:16)[2752r,2768r:15)[3056r,3064r:13)[3280r,3296r:14)[3408r,3424r:12)[4224r,4240r:11)[4528r,4536r:9)[4752r,4768r:10)[4880r,4896r:8)[5696r,5712r:7)[6000r,6008r:5)[6224r,6240r:6)[6352r,6368r:4)[7120r,7136r:3)[7424r,7432r:2)[8272r,8288r:1)[8584r,8600r:0)[9344r,9360r:28)[9520r,9536r:27)[10640r,10656r:26)[10784r,10800r:25)[11248r,11264r:24)[11392r,11408r:23)[11824r,11840r:22)[11936r,11952r:21)[12400r,12416r:20)[12512r,12528r:19)[13552r,13568r:18)  0@8584r 1@8272r 2@7424r 3@7120r 4@6352r 5@6000r 6@6224r 7@5696r 8@4880r 9@4528r 10@4752r 11@4224r 12@3408r 13@3056r 14@3280r 15@2752r 16@1872r 17@1664r 18@13552r 19@12512r 20@12400r 21@11936r 22@11824r 23@11392r 24@11248r 25@10784r 26@10640r 27@9520r 28@9344r
handleMove 8512B -> 8568B: %vreg1105<def> = LDRWui %vreg1106, 6; mem:LD4[%rNToGo268] GPR32common:%vreg1105 GPR64common:%vreg1106
     %vreg1105:	[8512r,8584r:0)  0@8512r
        -->	[8568r,8584r:0)  0@8568r
     %vreg1106:	[8496r,8512r:0)  0@8496r
        -->	[8496r,8568r:0)  0@8496r
AllocationOrder(GPR32sponly) = [ ]
AllocationOrder(GPR32sponly) = [ ]
handleMove 9712B -> 9736B: %vreg102<def> = UBFMWri %vreg103, 24, 31; GPR32:%vreg102,%vreg103
     %vreg102:	[9712r,9744r:0)  0@9712r
        -->	[9736r,9744r:0)  0@9736r
     %vreg103:	[9696r,9712r:0)  0@9696r
        -->	[9696r,9736r:0)  0@9696r
handleMove 9680B -> 9732B: %vreg104<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg104
     %vreg104:	[9680r,9856r:0)  0@9680r
        -->	[9732r,9856r:0)  0@9732r
handleMove 9616B -> 9736B: %vreg87<def> = ADDXri %vreg86, <ga:@BZ2_crc32Table>[TF=34], 0; GPR64common:%vreg87,%vreg86
     %vreg87:	[9616r,9824r:0)  0@9616r
        -->	[9736r,9824r:0)  0@9736r
     %vreg86:	[9600r,9616r:0)  0@9600r
        -->	[9600r,9736r:0)  0@9600r
handleMove 9600B -> 9656B: %vreg86<def> = ADRP <ga:@BZ2_crc32Table>[TF=1]; GPR64common:%vreg86
     %vreg86:	[9600r,9736r:0)  0@9600r
        -->	[9656r,9736r:0)  0@9656r
AllocationOrder(GPR32sponly) = [ ]
handleMove 10320B -> 10344B: %vreg141<def> = UBFMWri %vreg142, 24, 31; GPR32:%vreg141,%vreg142
     %vreg141:	[10320r,10352r:0)  0@10320r
        -->	[10344r,10352r:0)  0@10344r
     %vreg142:	[10304r,10320r:0)  0@10304r
        -->	[10304r,10344r:0)  0@10304r
handleMove 10288B -> 10340B: %vreg143<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg143
     %vreg143:	[10288r,10464r:0)  0@10288r
        -->	[10340r,10464r:0)  0@10340r
handleMove 10224B -> 10344B: %vreg126<def> = ADDXri %vreg125, <ga:@BZ2_crc32Table>[TF=34], 0; GPR64common:%vreg126,%vreg125
     %vreg126:	[10224r,10432r:0)  0@10224r
        -->	[10344r,10432r:0)  0@10344r
     %vreg125:	[10208r,10224r:0)  0@10208r
        -->	[10208r,10344r:0)  0@10208r
handleMove 10208B -> 10264B: %vreg125<def> = ADRP <ga:@BZ2_crc32Table>[TF=1]; GPR64common:%vreg125
     %vreg125:	[10208r,10344r:0)  0@10208r
        -->	[10264r,10344r:0)  0@10264r
AllocationOrder(GPR32sponly) = [ ]
AllocationOrder(GPR32sponly) = [ ]
AllocationOrder(GPR32sponly) = [ ]
AllocationOrder(GPR32sponly) = [ ]
AllocationOrder(GPR32sponly) = [ ]
handleMove 13392B -> 13448B: %vreg373<def> = SUBWrr %vreg375, %vreg374; GPR32:%vreg373,%vreg375,%vreg374
     %vreg373:	[13392r,13456r:0)  0@13392r
        -->	[13448r,13456r:0)  0@13448r
     %vreg375:	[13360r,13392r:0)  0@13360r
        -->	[13360r,13448r:0)  0@13360r
     %vreg374:	[13376r,13392r:0)  0@13376r
        -->	[13376r,13448r:0)  0@13376r
handleMove 13376B -> 13432B: %vreg374<def> = LDRWui <fi#11>, 0; mem:LD4[FixedStack11] GPR32:%vreg374
     %vreg374:	[13376r,13448r:0)  0@13376r
        -->	[13432r,13448r:0)  0@13432r
handleMove 13360B -> 13428B: %vreg375<def> = LDRWui <fi#12>, 0; mem:LD4[FixedStack12] GPR32:%vreg375
     %vreg375:	[13360r,13448r:0)  0@13360r
        -->	[13428r,13448r:0)  0@13428r
AllocationOrder(GPR32sponly) = [ ]
handleMove 14096B -> 14120B: %vreg395<def> = LDRWui <fi#11>, 0; mem:LD4[FixedStack11] GPR32:%vreg395
     %vreg395:	[14096r,14144r:0)  0@14096r
        -->	[14120r,14144r:0)  0@14120r
handleMove 14032B -> 14056B: %vreg401<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg401
     %vreg401:	[14032r,14080r:0)  0@14032r
        -->	[14056r,14080r:0)  0@14056r
********** GREEDY REGISTER ALLOCATION **********
********** Function: unRLE_obuf_to_output_FAST
********** INTERVALS **********
W30 [0B,16r:0)[176r,176d:4)[224e,224d:2)[14272r,14272d:3)[14320e,14320d:1)  0@0B-phi 1@14320e 2@224e 3@14272r 4@176r
NZCV [1664r,1680r:17)[1872r,1888r:16)[2752r,2768r:15)[3056r,3064r:13)[3280r,3296r:14)[3408r,3424r:12)[4224r,4240r:11)[4528r,4536r:9)[4752r,4768r:10)[4880r,4896r:8)[5696r,5712r:7)[6000r,6008r:5)[6224r,6240r:6)[6352r,6368r:4)[7120r,7136r:3)[7424r,7432r:2)[8272r,8288r:1)[8584r,8600r:0)[9344r,9360r:28)[9520r,9536r:27)[10640r,10656r:26)[10784r,10800r:25)[11248r,11264r:24)[11392r,11408r:23)[11824r,11840r:22)[11936r,11952r:21)[12400r,12416r:20)[12512r,12528r:19)[13552r,13568r:18)  0@8584r 1@8272r 2@7424r 3@7120r 4@6352r 5@6000r 6@6224r 7@5696r 8@4880r 9@4528r 10@4752r 11@4224r 12@3408r 13@3056r 14@3280r 15@2752r 16@1872r 17@1664r 18@13552r 19@12512r 20@12400r 21@11936r 22@11824r 23@11392r 24@11248r 25@10784r 26@10640r 27@9520r 28@9344r
WZR [1664r,1664d:17)[1872r,1872d:16)[2752r,2752d:15)[3056r,3056d:13)[3280r,3280d:14)[3408r,3408d:12)[4224r,4224d:11)[4528r,4528d:9)[4752r,4752d:10)[4880r,4880d:8)[5696r,5696d:7)[6000r,6000d:5)[6224r,6224d:6)[6352r,6352d:4)[7120r,7120d:3)[7424r,7424d:2)[8272r,8272d:1)[8584r,8584d:0)[9344r,9344d:28)[9520r,9520d:27)[10640r,10640d:26)[10784r,10784d:25)[11248r,11248d:24)[11392r,11392d:23)[11824r,11824d:22)[11936r,11936d:21)[12400r,12400d:20)[12512r,12512d:19)[13552r,13552d:18)  0@8584r 1@8272r 2@7424r 3@7120r 4@6352r 5@6000r 6@6224r 7@5696r 8@4880r 9@4528r 10@4752r 11@4224r 12@3408r 13@3056r 14@3280r 15@2752r 16@1872r 17@1664r 18@13552r 19@12512r 20@12400r 21@11936r 22@11824r 23@11392r 24@11248r 25@10784r 26@10640r 27@9520r 28@9344r
W0 [0B,32r:0)[144r,176r:3)[14240r,14272r:2)[14384r,14400r:1)  0@0B-phi 1@14384r 2@14240r 3@144r
%vreg1 [32r,256r:0)  0@32r
%vreg3 [304r,320r:0)  0@304r
%vreg5 [288r,304r:0)  0@288r
%vreg6 [272r,288r:0)  0@272r
%vreg7 [64r,80r:0)  0@64r
%vreg9 [80r,144r:0)  0@80r
%vreg10 [16r,14256r:0)  0@16r
%vreg14 [9280r,9296r:0)  0@9280r
%vreg16 [9232r,9248r:0)  0@9232r
%vreg17 [9248r,9264r:0)  0@9248r
%vreg18 [9264r,9280r:0)  0@9264r
%vreg19 [9216r,9248r:0)  0@9216r
%vreg21 [9184r,9200r:0)  0@9184r
%vreg24 [9152r,9168r:0)  0@9152r
%vreg26 [9136r,9152r:0)  0@9136r
%vreg27 [9120r,9136r:0)  0@9120r
%vreg30 [9088r,9104r:0)  0@9088r
%vreg32 [9072r,9088r:0)  0@9072r
%vreg33 [9056r,9072r:0)  0@9056r
%vreg36 [9024r,9040r:0)  0@9024r
%vreg37 [9008r,9024r:0)  0@9008r
%vreg40 [8976r,8992r:0)  0@8976r
%vreg41 [8960r,8976r:0)  0@8960r
%vreg44 [8928r,8944r:0)  0@8928r
%vreg45 [8912r,8928r:0)  0@8912r
%vreg48 [8880r,8896r:0)  0@8880r
%vreg49 [8864r,8880r:0)  0@8864r
%vreg52 [8832r,8848r:0)  0@8832r
%vreg53 [8816r,8832r:0)  0@8816r
%vreg56 [8784r,8800r:0)  0@8784r
%vreg57 [8768r,8784r:0)  0@8768r
%vreg60 [8736r,8752r:0)  0@8736r
%vreg61 [8720r,8736r:0)  0@8720r
%vreg63 [9328r,9344r:0)  0@9328r
%vreg65 [9424r,9440r:0)  0@9424r
%vreg67 [9504r,9520r:0)  0@9504r
%vreg70 [10000r,10016r:0)  0@10000r
%vreg71 [9984r,10000r:0)  0@9984r
%vreg74 [9952r,9968r:0)  0@9952r
%vreg75 [9936r,9952r:0)  0@9936r
%vreg78 [9904r,9920r:0)  0@9904r
%vreg79 [9888r,9904r:0)  0@9888r
%vreg83 [9856r,9872r:0)  0@9856r
%vreg85 [9840r,9856r:0)  0@9840r
%vreg86 [9656r,9736r:0)  0@9656r
%vreg87 [9736r,9824r:0)  0@9736r
%vreg89 [9792r,9808r:0)  0@9792r
%vreg90 [9808r,9824r:0)  0@9808r
%vreg91 [9824r,9840r:0)  0@9824r
%vreg93 [9760r,9776r:0)  0@9760r
%vreg94 [9776r,9808r:0)  0@9776r
%vreg100 [9728r,9760r:0)  0@9728r
%vreg102 [9752r,9760r:0)  0@9752r
%vreg103 [9696r,9752r:0)  0@9696r
%vreg104 [9744r,9856r:0)  0@9744r
%vreg107 [9648r,9664r:0)  0@9648r
%vreg108 [9632r,9664r:0)  0@9632r
%vreg110 [10096r,10112r:0)  0@10096r
%vreg113 [10560r,10576r:0)  0@10560r
%vreg114 [10544r,10560r:0)  0@10544r
%vreg117 [10512r,10528r:0)  0@10512r
%vreg118 [10496r,10512r:0)  0@10496r
%vreg122 [10464r,10480r:0)  0@10464r
%vreg124 [10448r,10464r:0)  0@10448r
%vreg125 [10264r,10344r:0)  0@10264r
%vreg126 [10344r,10432r:0)  0@10344r
%vreg128 [10400r,10416r:0)  0@10400r
%vreg129 [10416r,10432r:0)  0@10416r
%vreg130 [10432r,10448r:0)  0@10432r
%vreg132 [10368r,10384r:0)  0@10368r
%vreg133 [10384r,10416r:0)  0@10384r
%vreg139 [10336r,10368r:0)  0@10336r
%vreg141 [10360r,10368r:0)  0@10360r
%vreg142 [10304r,10360r:0)  0@10304r
%vreg143 [10352r,10464r:0)  0@10352r
%vreg146 [10256r,10272r:0)  0@10256r
%vreg147 [10240r,10272r:0)  0@10240r
%vreg150 [10624r,10640r:0)  0@10624r
%vreg151 [10608r,10640r:0)  0@10608r
%vreg154 [10768r,10784r:0)  0@10768r
%vreg155 [10752r,10784r:0)  0@10752r
%vreg158 [11232r,11248r:0)  0@11232r
%vreg161 [11216r,11248r:0)  0@11216r
%vreg164 [11184r,11200r:0)  0@11184r
%vreg165 [11168r,11184r:0)  0@11168r
%vreg168 [11136r,11152r:0)  0@11136r
%vreg169 [11120r,11136r:0)  0@11120r
%vreg172 [11072r,11104r:0)  0@11072r
%vreg175 [11056r,11072r:0)  0@11056r
%vreg178 [11024r,11040r:0)  0@11024r
%vreg181 [10976r,10992r:0)  0@10976r
%vreg182 [10992r,11008r:0)  0@10992r
%vreg183 [11008r,11024r:0)  0@11008r
%vreg184 [10960r,11008r:0)  0@10960r
%vreg189 [10928r,10992r:0)  0@10928r
%vreg192 [10880r,10912r:0)  0@10880r
%vreg196 [11376r,11392r:0)  0@11376r
%vreg197 [11360r,11392r:0)  0@11360r
%vreg200 [11808r,11824r:0)  0@11808r
%vreg201 [11792r,11824r:0)  0@11792r
%vreg204 [11760r,11776r:0)  0@11760r
%vreg205 [11744r,11760r:0)  0@11744r
%vreg208 [11712r,11728r:0)  0@11712r
%vreg209 [11696r,11712r:0)  0@11696r
%vreg212 [11648r,11680r:0)  0@11648r
%vreg215 [11632r,11648r:0)  0@11632r
%vreg218 [11600r,11616r:0)  0@11600r
%vreg221 [11552r,11568r:0)  0@11552r
%vreg222 [11568r,11584r:0)  0@11568r
%vreg223 [11584r,11600r:0)  0@11584r
%vreg224 [11536r,11584r:0)  0@11536r
%vreg229 [11504r,11568r:0)  0@11504r
%vreg230 [11472r,11488r:0)  0@11472r
%vreg233 [11920r,11936r:0)  0@11920r
%vreg236 [11904r,11936r:0)  0@11904r
%vreg239 [12384r,12400r:0)  0@12384r
%vreg240 [12368r,12400r:0)  0@12368r
%vreg243 [12336r,12352r:0)  0@12336r
%vreg244 [12320r,12336r:0)  0@12320r
%vreg247 [12288r,12304r:0)  0@12288r
%vreg248 [12272r,12288r:0)  0@12272r
%vreg251 [12224r,12256r:0)  0@12224r
%vreg254 [12208r,12224r:0)  0@12208r
%vreg257 [12176r,12192r:0)  0@12176r
%vreg260 [12128r,12144r:0)  0@12128r
%vreg261 [12144r,12160r:0)  0@12144r
%vreg262 [12160r,12176r:0)  0@12160r
%vreg263 [12112r,12160r:0)  0@12112r
%vreg268 [12080r,12144r:0)  0@12080r
%vreg269 [12048r,12064r:0)  0@12048r
%vreg272 [12496r,12512r:0)  0@12496r
%vreg275 [12480r,12512r:0)  0@12480r
%vreg278 [13232r,13248r:0)  0@13232r
%vreg279 [13216r,13232r:0)  0@13216r
%vreg282 [13184r,13200r:0)  0@13184r
%vreg283 [13168r,13184r:0)  0@13168r
%vreg286 [13136r,13152r:0)  0@13136r
%vreg288 [13104r,13136r:0)  0@13104r
%vreg291 [13088r,13104r:0)  0@13088r
%vreg294 [13056r,13072r:0)  0@13056r
%vreg297 [13008r,13024r:0)  0@13008r
%vreg298 [13024r,13040r:0)  0@13024r
%vreg299 [13040r,13056r:0)  0@13040r
%vreg300 [12992r,13040r:0)  0@12992r
%vreg305 [12960r,13024r:0)  0@12960r
%vreg308 [12928r,12944r:0)  0@12928r
%vreg311 [12912r,12928r:0)  0@12912r
%vreg314 [12880r,12896r:0)  0@12880r
%vreg315 [12864r,12880r:0)  0@12864r
%vreg318 [12832r,12848r:0)  0@12832r
%vreg319 [12816r,12832r:0)  0@12816r
%vreg322 [12768r,12800r:0)  0@12768r
%vreg325 [12752r,12768r:0)  0@12752r
%vreg328 [12720r,12736r:0)  0@12720r
%vreg331 [12672r,12688r:0)  0@12672r
%vreg332 [12688r,12704r:0)  0@12688r
%vreg333 [12704r,12720r:0)  0@12704r
%vreg334 [12656r,12704r:0)  0@12656r
%vreg339 [12624r,12688r:0)  0@12624r
%vreg343 [12560r,12576r:0)  0@12560r
%vreg347 [11984r,12000r:0)  0@11984r
%vreg351 [11296r,11312r:0)  0@11296r
%vreg352 [10688r,10704r:0)  0@10688r
%vreg353 [10144r,10160r:0)  0@10144r
%vreg356 [13536r,13552r:0)  0@13536r
%vreg358 [13520r,13552r:0)  0@13520r
%vreg360 [13504r,13520r:0)  0@13504r
%vreg361 [13488r,13504r:0)  0@13488r
%vreg366 [13456r,13472r:0)  0@13456r
%vreg367 [13440r,13456r:0)  0@13440r
%vreg369 [13424r,13472r:0)  0@13424r
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%vreg1091 [8640r,8656r:0)  0@8640r
%vreg1092 [8624r,8672r:0)  0@8624r
%vreg1097 [8608r,8616r:0)  0@8608r
%vreg1098 [8576r,8608r:0)  0@8576r
%vreg1099 [8560r,8616r:0)  0@8560r
%vreg1101 [8592r,8600r:0)  0@8592r
%vreg1102 [8392r,8600r:0)  0@8392r
%vreg1103 [8600r,8608r:0)  0@8600r
%vreg1105 [8568r,8584r:0)  0@8568r
%vreg1106 [8496r,8568r:0)  0@8496r
%vreg1110 [8464r,8480r:0)  0@8464r
%vreg1111 [8448r,8464r:0)  0@8448r
%vreg1112 [8432r,8480r:0)  0@8432r
%vreg1115 [6416r,6432r:0)  0@6416r
%vreg1118 [6400r,6432r:0)  0@6400r
%vreg1121 [4944r,4960r:0)  0@4944r
%vreg1124 [4928r,4960r:0)  0@4928r
%vreg1127 [3472r,3488r:0)  0@3472r
%vreg1130 [3456r,3488r:0)  0@3456r
%vreg1131 [1920r,1936r:0)  0@1920r
%vreg1133 [14224r,14240r:0)  0@14224r
%vreg1134 [14352r,14384r:0)  0@14352r
RegMasks: 176r 14272r
********** MACHINEINSTRS **********
# Machine code for function unRLE_obuf_to_output_FAST: Post SSA
Frame Objects:
  fi#0: size=1, align=1, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=1, align=1, at location [SP]
  fi#3: size=4, align=4, at location [SP]
  fi#4: size=1, align=1, at location [SP]
  fi#5: size=4, align=4, at location [SP]
  fi#6: size=4, align=4, at location [SP]
  fi#7: size=4, align=4, at location [SP]
  fi#8: size=8, align=8, at location [SP]
  fi#9: size=4, align=4, at location [SP]
  fi#10: size=8, align=8, at location [SP]
  fi#11: size=4, align=4, at location [SP]
  fi#12: size=4, align=4, at location [SP]
  fi#13: size=4, align=4, at location [SP]
  fi#14: size=4, align=4, at location [SP]
Function Live Ins: %X0 in %vreg0, %LR in %vreg11

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %LR
16B		%vreg10<def> = COPY %LR; GPR64:%vreg10
32B		%vreg1<def> = COPY %X0; GPR64:%vreg1
64B		%vreg7<def> = ADRP <ga:@unRLE_obuf_to_output_FAST>[TF=1]; GPR64common:%vreg7
80B		%vreg9<def> = ADDXri %vreg7, <ga:@unRLE_obuf_to_output_FAST>[TF=34], 0; GPR64sp:%vreg9 GPR64common:%vreg7
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		%X0<def> = COPY %vreg9; GPR64sp:%vreg9
160B		%X1<def> = COPY %vreg10; GPR64:%vreg10
176B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
224B		STACKMAP 0, 0, 0, <fi#12>, 0, 0, <fi#3>, 0, 0, <fi#7>, 0, 0, <fi#6>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#9>, 0, 0, <fi#8>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, %vreg1, 0, <fi#1>, 0, 0, <fi#13>, 0, 0, <fi#14>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack12](align=4) LD8[FixedStack3](align=4) LD8[FixedStack7](align=4) LD8[FixedStack6](align=4) LD8[FixedStack4](align=1) LD8[FixedStack5](align=4) LD8[FixedStack9](align=4) LD8[FixedStack8] LD8[FixedStack11](align=4) LD8[FixedStack10] LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1] LD8[FixedStack13](align=4) LD8[FixedStack14](align=4) GPR64:%vreg1
240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
256B		STRXui %vreg1, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg1
272B		%vreg6<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg6
288B		%vreg5<def> = LDRBBui %vreg6, 20; mem:LD1[%blockRandomised] GPR32:%vreg5 GPR64common:%vreg6
304B		%vreg3<def> = UBFMWri %vreg5, 0, 7; GPR32:%vreg3,%vreg5
320B		CBZW %vreg3, <BB#47>; GPR32:%vreg3
	    Successors according to CFG: BB#47 BB#1

336B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
352B		B <BB#2>
	    Successors according to CFG: BB#2

368B	BB#2: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#1 BB#46 BB#37 BB#35 BB#29 BB#27 BB#21 BB#19
384B		B <BB#3>
	    Successors according to CFG: BB#3

400B	BB#3: derived from LLVM BB %while.body.2
	    Predecessors according to CFG: BB#2 BB#9
416B		%vreg435<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg435
432B		%vreg434<def> = LDRXui %vreg435, 0; mem:LD8[%strm] GPR64common:%vreg434,%vreg435
448B		%vreg432<def> = LDRWui %vreg434, 8; mem:LD4[%avail_out] GPR32:%vreg432 GPR64common:%vreg434
464B		CBNZW %vreg432, <BB#5>; GPR32:%vreg432
	    Successors according to CFG: BB#5 BB#4

480B	BB#4: derived from LLVM BB %if.then.3
	    Predecessors according to CFG: BB#3
496B		STRBBui %WZR, <fi#0>, 0; mem:ST1[FixedStack0]
512B		B <BB#80>
	    Successors according to CFG: BB#80

528B	BB#5: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#3
544B		%vreg439<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg439
560B		%vreg438<def> = LDRWui %vreg439, 4; mem:LD4[%state_out_len] GPR32:%vreg438 GPR64common:%vreg439
576B		CBNZW %vreg438, <BB#7>; GPR32:%vreg438
	    Successors according to CFG: BB#7 BB#6

592B	BB#6: derived from LLVM BB %if.then.5
	    Predecessors according to CFG: BB#5
608B		B <BB#10>
	    Successors according to CFG: BB#10

624B	BB#7: derived from LLVM BB %if.end.6
	    Predecessors according to CFG: BB#5
704B		%vreg515<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg515
712B		%vreg518<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg518
720B		%vreg514<def> = LDRXui %vreg515, 0; mem:LD8[%strm7] GPR64common:%vreg514,%vreg515
728B		%vreg517<def> = LDRBBui %vreg518, 12; mem:LD1[%state_out_ch] GPR32:%vreg517 GPR64common:%vreg518
736B		%vreg512<def> = LDRXui %vreg514, 3; mem:LD8[%next_out] GPR64common:%vreg512,%vreg514
752B		STRBBui %vreg517, %vreg512, 0; mem:ST1[%11] GPR32:%vreg517 GPR64common:%vreg512
800B		%vreg505<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg505
848B		%vreg500<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg500
856B		%vreg484<def> = ADRP <ga:@BZ2_crc32Table>[TF=1]; GPR64common:%vreg484
864B		%vreg508<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg508
872B		%vreg504<def> = LDRWui %vreg505, 796; mem:LD4[%calculatedBlockCRC8] GPR32:%vreg504 GPR64common:%vreg505
880B		%vreg499<def> = LDRBBui %vreg500, 12; mem:LD1[%state_out_ch9] GPR32:%vreg499 GPR64common:%vreg500
888B		%vreg485<def> = ADDXri %vreg484, <ga:@BZ2_crc32Table>[TF=34], 0; GPR64common:%vreg485,%vreg484
896B		%vreg507<def> = LDRWui %vreg508, 796; mem:LD4[%calculatedBlockCRC] GPR32:%vreg507 GPR64common:%vreg508
904B		%vreg502<def> = UBFMWri %vreg504, 24, 31; GPR32:%vreg502,%vreg504
912B		%vreg491:sub_32<def,read-undef> = EORWrr %vreg502, %vreg499; GPR64:%vreg491 GPR32:%vreg502,%vreg499
928B		%vreg492<def> = UBFMXri %vreg491, 0, 31; GPR64:%vreg492,%vreg491
936B		%vreg487<def> = MOVi64imm 4; GPR64:%vreg487
944B		%vreg488<def> = MADDXrrr %vreg492, %vreg487, %XZR; GPR64:%vreg488,%vreg492,%vreg487
960B		%vreg489<def> = ADDXrr %vreg485, %vreg488; GPR64common:%vreg489,%vreg485 GPR64:%vreg488
976B		%vreg483<def> = LDRWui %vreg489, 0; mem:LD4[%arrayidx] GPR32:%vreg483 GPR64common:%vreg489
1008B		%vreg478<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg478
1016B		%vreg481<def> = EORWrs %vreg483, %vreg507, 8; GPR32:%vreg481,%vreg483,%vreg507
1024B		STRWui %vreg481, %vreg478, 796; mem:ST4[%calculatedBlockCRC11] GPR32:%vreg481 GPR64common:%vreg478
1040B		%vreg475<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg475
1056B		%vreg474<def> = LDRWui %vreg475, 4; mem:LD4[%state_out_len12] GPR32common:%vreg474 GPR64common:%vreg475
1072B		%vreg473<def> = SUBWri %vreg474, 1, 0; GPR32common:%vreg473,%vreg474
1088B		STRWui %vreg473, %vreg475, 4; mem:ST4[%state_out_len12] GPR32common:%vreg473 GPR64common:%vreg475
1104B		%vreg469<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg469
1120B		%vreg468<def> = LDRXui %vreg469, 0; mem:LD8[%strm13] GPR64common:%vreg468,%vreg469
1136B		%vreg466<def> = LDRXui %vreg468, 3; mem:LD8[%next_out14] GPR64common:%vreg466,%vreg468
1152B		%vreg465<def> = ADDXri %vreg466, 1, 0; GPR64common:%vreg465,%vreg466
1168B		STRXui %vreg465, %vreg468, 3; mem:ST8[%next_out14] GPR64common:%vreg465,%vreg468
1184B		%vreg461<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg461
1200B		%vreg460<def> = LDRXui %vreg461, 0; mem:LD8[%strm15] GPR64common:%vreg460,%vreg461
1216B		%vreg458<def> = LDRWui %vreg460, 8; mem:LD4[%avail_out16] GPR32common:%vreg458 GPR64common:%vreg460
1232B		%vreg457<def> = SUBWri %vreg458, 1, 0; GPR32common:%vreg457,%vreg458
1248B		STRWui %vreg457, %vreg460, 8; mem:ST4[%avail_out16] GPR32common:%vreg457 GPR64common:%vreg460
1264B		%vreg453<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg453
1280B		%vreg452<def> = LDRXui %vreg453, 0; mem:LD8[%strm18] GPR64common:%vreg452,%vreg453
1296B		%vreg450<def> = LDRWui %vreg452, 9; mem:LD4[%total_out_lo32] GPR32common:%vreg450 GPR64common:%vreg452
1312B		%vreg449<def> = ADDWri %vreg450, 1, 0; GPR32common:%vreg449,%vreg450
1328B		STRWui %vreg449, %vreg452, 9; mem:ST4[%total_out_lo32] GPR32common:%vreg449 GPR64common:%vreg452
1344B		%vreg445<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg445
1360B		%vreg444<def> = LDRXui %vreg445, 0; mem:LD8[%strm19] GPR64common:%vreg444,%vreg445
1376B		%vreg442<def> = LDRWui %vreg444, 9; mem:LD4[%total_out_lo3220] GPR32:%vreg442 GPR64common:%vreg444
1392B		CBNZW %vreg442, <BB#9>; GPR32:%vreg442
	    Successors according to CFG: BB#9 BB#8

1408B	BB#8: derived from LLVM BB %if.then.23
	    Predecessors according to CFG: BB#7
1424B		%vreg526<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg526
1440B		%vreg525<def> = LDRXui %vreg526, 0; mem:LD8[%strm24] GPR64common:%vreg525,%vreg526
1456B		%vreg523<def> = LDRWui %vreg525, 10; mem:LD4[%total_out_hi32] GPR32common:%vreg523 GPR64common:%vreg525
1472B		%vreg522<def> = ADDWri %vreg523, 1, 0; GPR32common:%vreg522,%vreg523
1488B		STRWui %vreg522, %vreg525, 10; mem:ST4[%total_out_hi32] GPR32common:%vreg522 GPR64common:%vreg525
	    Successors according to CFG: BB#9

1504B	BB#9: derived from LLVM BB %if.end.26
	    Predecessors according to CFG: BB#7 BB#8
1520B		B <BB#3>
	    Successors according to CFG: BB#3

1536B	BB#10: derived from LLVM BB %while.end
	    Predecessors according to CFG: BB#6
1584B		%vreg535<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg535
1592B		%vreg538<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg538
1600B		%vreg532<def> = MOVi64imm 64080; GPR64:%vreg532
1616B		%vreg533<def> = ADDXrr %vreg535, %vreg532; GPR64common:%vreg533 GPR64:%vreg535,%vreg532
1632B		%vreg534<def> = LDRWui %vreg533, 0; mem:LD4[%save_nblock] GPR32common:%vreg534 GPR64common:%vreg533
1640B		%vreg537<def> = LDRWui %vreg538, 273; mem:LD4[%nblock_used] GPR32:%vreg537 GPR64common:%vreg538
1648B		%vreg530<def> = ADDWri %vreg534, 1, 0; GPR32common:%vreg530,%vreg534
1664B		%WZR<def> = SUBSWrr %vreg537, %vreg530, %NZCV<imp-def>; GPR32:%vreg537 GPR32common:%vreg530
1680B		Bcc 1, <BB#12>, %NZCV<imp-use>
	    Successors according to CFG: BB#12 BB#11

1696B	BB#11: derived from LLVM BB %if.then.29
	    Predecessors according to CFG: BB#10
1712B		STRBBui %WZR, <fi#0>, 0; mem:ST1[FixedStack0]
1728B		B <BB#80>
	    Successors according to CFG: BB#80

1744B	BB#12: derived from LLVM BB %if.end.30
	    Predecessors according to CFG: BB#10
1792B		%vreg547<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg547
1800B		%vreg550<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg550
1808B		%vreg544<def> = MOVi64imm 64080; GPR64:%vreg544
1824B		%vreg545<def> = ADDXrr %vreg547, %vreg544; GPR64common:%vreg545 GPR64:%vreg547,%vreg544
1840B		%vreg546<def> = LDRWui %vreg545, 0; mem:LD4[%save_nblock32] GPR32common:%vreg546 GPR64common:%vreg545
1848B		%vreg549<def> = LDRWui %vreg550, 273; mem:LD4[%nblock_used31] GPR32:%vreg549 GPR64common:%vreg550
1856B		%vreg542<def> = ADDWri %vreg546, 1, 0; GPR32common:%vreg542,%vreg546
1872B		%WZR<def> = SUBSWrr %vreg549, %vreg542, %NZCV<imp-def>; GPR32:%vreg549 GPR32common:%vreg542
1888B		Bcc 13, <BB#14>, %NZCV<imp-use>
	    Successors according to CFG: BB#14 BB#13

1904B	BB#13: derived from LLVM BB %if.then.36
	    Predecessors according to CFG: BB#12
1920B		%vreg1131<def> = MOVi32imm 1; GPR32:%vreg1131
1936B		STRBBui %vreg1131, <fi#0>, 0; mem:ST1[FixedStack0] GPR32:%vreg1131
1952B		B <BB#80>
	    Successors according to CFG: BB#80

1968B	BB#14: derived from LLVM BB %if.end.37
	    Predecessors according to CFG: BB#12
2000B		%vreg599<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg599
2008B		%vreg597<def> = MOVi32imm 1; GPR32:%vreg597
2016B		STRWui %vreg597, %vreg599, 4; mem:ST4[%state_out_len38] GPR32:%vreg597 GPR64common:%vreg599
2032B		%vreg596<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg596
2080B		%vreg591<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg591
2088B		%vreg593<def> = LDRWui %vreg596, 16; mem:LD4[%k0] GPR32:%vreg593 GPR64common:%vreg596
2096B		STRBBui %vreg593, %vreg591, 12; mem:ST1[%state_out_ch40] GPR32:%vreg593 GPR64common:%vreg591
2112B		%vreg588<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg588
2160B		%vreg581<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg581
2168B		%vreg587:sub_32<def,read-undef> = LDRWui %vreg588, 15; mem:LD4[%tPos] GPR64:%vreg587 GPR64common:%vreg588
2176B		%vreg580<def> = LDRXui %vreg581, 394; mem:LD8[%tt] GPR64:%vreg580 GPR64common:%vreg581
2192B		%vreg576<def> = MOVi64imm 4; GPR64:%vreg576
2208B		%vreg577<def> = MADDXrrr %vreg587, %vreg576, %XZR; GPR64:%vreg577,%vreg587,%vreg576
2224B		%vreg578<def> = ADDXrr %vreg580, %vreg577; GPR64common:%vreg578 GPR64:%vreg580,%vreg577
2240B		%vreg573<def> = LDRWui %vreg578, 0; mem:LD4[%arrayidx42] GPR32:%vreg573 GPR64common:%vreg578
2256B		%vreg571<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg571
2272B		STRWui %vreg573, %vreg571, 15; mem:ST4[%tPos43] GPR32:%vreg573 GPR64common:%vreg571
2288B		%vreg568<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg568
2304B		%vreg567<def> = LDRWui %vreg568, 15; mem:LD4[%tPos44] GPR32:%vreg567 GPR64common:%vreg568
2320B		%vreg563<def> = ANDWri %vreg567, 7; GPR32common:%vreg563 GPR32:%vreg567
2352B		STRBBui %vreg563, <fi#2>, 0; mem:ST1[FixedStack2] GPR32common:%vreg563
2368B		%vreg560<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg560
2384B		%vreg559<def> = LDRWui %vreg560, 15; mem:LD4[%tPos46] GPR32:%vreg559 GPR64common:%vreg560
2400B		%vreg558<def> = UBFMWri %vreg559, 8, 31; GPR32:%vreg558,%vreg559
2416B		STRWui %vreg558, %vreg560, 15; mem:ST4[%tPos46] GPR32:%vreg558 GPR64common:%vreg560
2432B		%vreg554<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg554
2448B		%vreg553<def> = LDRWui %vreg554, 6; mem:LD4[%rNToGo] GPR32:%vreg553 GPR64common:%vreg554
2464B		CBNZW %vreg553, <BB#18>; GPR32:%vreg553
	    Successors according to CFG: BB#18 BB#15

2480B	BB#15: derived from LLVM BB %if.then.50
	    Predecessors according to CFG: BB#14
2528B		%vreg626<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg626
2544B		%vreg625<def> = LDRSWui %vreg626, 7; mem:LD4[%rTPos] GPR64:%vreg625 GPR64common:%vreg626
2552B		%vreg615<def> = ADRP <ga:@BZ2_rNums>[TF=1]; GPR64common:%vreg615
2560B		%vreg618<def> = MOVi64imm 4; GPR64:%vreg618
2568B		%vreg616<def> = ADDXri %vreg615, <ga:@BZ2_rNums>[TF=34], 0; GPR64common:%vreg616,%vreg615
2576B		%vreg619<def> = MADDXrrr %vreg625, %vreg618, %XZR; GPR64:%vreg619,%vreg625,%vreg618
2592B		%vreg620<def> = ADDXrr %vreg616, %vreg619; GPR64common:%vreg620,%vreg616 GPR64:%vreg619
2608B		%vreg614<def> = LDRWui %vreg620, 0; mem:LD4[%arrayidx52] GPR32:%vreg614 GPR64common:%vreg620
2624B		%vreg612<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg612
2640B		STRWui %vreg614, %vreg612, 6; mem:ST4[%rNToGo53] GPR32:%vreg614 GPR64common:%vreg612
2656B		%vreg609<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg609
2672B		%vreg608<def> = LDRWui %vreg609, 7; mem:LD4[%rTPos54] GPR32common:%vreg608 GPR64common:%vreg609
2688B		%vreg607<def> = ADDWri %vreg608, 1, 0; GPR32common:%vreg607,%vreg608
2704B		STRWui %vreg607, %vreg609, 7; mem:ST4[%rTPos54] GPR32common:%vreg607 GPR64common:%vreg609
2720B		%vreg603<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg603
2736B		%vreg602<def> = LDRWui %vreg603, 7; mem:LD4[%rTPos56] GPR32common:%vreg602 GPR64common:%vreg603
2752B		%WZR<def> = SUBSWri %vreg602, 512, 0, %NZCV<imp-def>; GPR32common:%vreg602
2768B		Bcc 1, <BB#17>, %NZCV<imp-use>
	    Successors according to CFG: BB#17 BB#16

2784B	BB#16: derived from LLVM BB %if.then.59
	    Predecessors according to CFG: BB#15
2800B		%vreg628<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg628
2816B		STRWui %WZR, %vreg628, 7; mem:ST4[%rTPos60] GPR64common:%vreg628
	    Successors according to CFG: BB#17

2832B	BB#17: derived from LLVM BB %if.end.61
	    Predecessors according to CFG: BB#15 BB#16
2848B		B <BB#18>
	    Successors according to CFG: BB#18

2864B	BB#18: derived from LLVM BB %if.end.62
	    Predecessors according to CFG: BB#14 BB#17
2872B		%vreg658<def> = COPY %WZR; GPR32:%vreg658
2912B		%vreg668<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg668
2928B		%vreg667<def> = LDRWui %vreg668, 6; mem:LD4[%rNToGo63] GPR32common:%vreg667 GPR64common:%vreg668
2944B		%vreg666<def> = SUBWri %vreg667, 1, 0; GPR32common:%vreg666,%vreg667
2960B		STRWui %vreg666, %vreg668, 6; mem:ST4[%rNToGo63] GPR32common:%vreg666 GPR64common:%vreg668
2976B		%vreg662<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg662
2992B		%vreg661<def> = LDRWui %vreg662, 6; mem:LD4[%rNToGo65] GPR32common:%vreg661 GPR64common:%vreg662
3040B		%vreg655<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg655
3048B		%vreg657<def> = MOVi32imm 1; GPR32:%vreg657
3056B		%WZR<def> = SUBSWri %vreg661, 1, 0, %NZCV<imp-def>; GPR32common:%vreg661
3064B		%vreg659<def> = CSELWr %vreg657, %vreg658, 0, %NZCV<imp-use>; GPR32:%vreg659,%vreg657,%vreg658
3072B		%vreg649<def> = EORWrr %vreg655, %vreg659; GPR32:%vreg649,%vreg655,%vreg659
3088B		STRBBui %vreg649, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg649
3104B		%vreg646<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg646
3120B		%vreg645<def> = LDRWui %vreg646, 273; mem:LD4[%nblock_used71] GPR32common:%vreg645 GPR64common:%vreg646
3136B		%vreg644<def> = ADDWri %vreg645, 1, 0; GPR32common:%vreg644,%vreg645
3152B		STRWui %vreg644, %vreg646, 273; mem:ST4[%nblock_used71] GPR32common:%vreg644 GPR64common:%vreg646
3200B		%vreg637<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg637
3208B		%vreg640<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg640
3216B		%vreg634<def> = MOVi64imm 64080; GPR64:%vreg634
3232B		%vreg635<def> = ADDXrr %vreg637, %vreg634; GPR64common:%vreg635 GPR64:%vreg637,%vreg634
3248B		%vreg636<def> = LDRWui %vreg635, 0; mem:LD4[%save_nblock74] GPR32common:%vreg636 GPR64common:%vreg635
3256B		%vreg639<def> = LDRWui %vreg640, 273; mem:LD4[%nblock_used73] GPR32:%vreg639 GPR64common:%vreg640
3264B		%vreg632<def> = ADDWri %vreg636, 1, 0; GPR32common:%vreg632,%vreg636
3280B		%WZR<def> = SUBSWrr %vreg639, %vreg632, %NZCV<imp-def>; GPR32:%vreg639 GPR32common:%vreg632
3296B		Bcc 1, <BB#20>, %NZCV<imp-use>
	    Successors according to CFG: BB#20 BB#19

3312B	BB#19: derived from LLVM BB %if.then.78
	    Predecessors according to CFG: BB#18
3328B		B <BB#2>
	    Successors according to CFG: BB#2

3344B	BB#20: derived from LLVM BB %if.end.79
	    Predecessors according to CFG: BB#18
3376B		%vreg673<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg673
3384B		%vreg676<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg676
3392B		%vreg672<def> = LDRWui %vreg673, 16; mem:LD4[%k081] GPR32:%vreg672 GPR64common:%vreg673
3408B		%WZR<def> = SUBSWrr %vreg676, %vreg672, %NZCV<imp-def>; GPR32:%vreg676,%vreg672
3424B		Bcc 0, <BB#22>, %NZCV<imp-use>
	    Successors according to CFG: BB#22 BB#21

3440B	BB#21: derived from LLVM BB %if.then.84
	    Predecessors according to CFG: BB#20
3456B		%vreg1130<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg1130
3472B		%vreg1127<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1127
3488B		STRWui %vreg1130, %vreg1127, 16; mem:ST4[%k086] GPR32:%vreg1130 GPR64common:%vreg1127
3504B		B <BB#2>
	    Successors according to CFG: BB#2

3520B	BB#22: derived from LLVM BB %if.end.87
	    Predecessors according to CFG: BB#20
3552B		%vreg717<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg717
3560B		%vreg715<def> = MOVi32imm 2; GPR32:%vreg715
3568B		STRWui %vreg715, %vreg717, 4; mem:ST4[%state_out_len88] GPR32:%vreg715 GPR64common:%vreg717
3584B		%vreg714<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg714
3632B		%vreg707<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg707
3640B		%vreg713:sub_32<def,read-undef> = LDRWui %vreg714, 15; mem:LD4[%tPos89] GPR64:%vreg713 GPR64common:%vreg714
3648B		%vreg706<def> = LDRXui %vreg707, 394; mem:LD8[%tt91] GPR64:%vreg706 GPR64common:%vreg707
3664B		%vreg702<def> = MOVi64imm 4; GPR64:%vreg702
3680B		%vreg703<def> = MADDXrrr %vreg713, %vreg702, %XZR; GPR64:%vreg703,%vreg713,%vreg702
3696B		%vreg704<def> = ADDXrr %vreg706, %vreg703; GPR64common:%vreg704 GPR64:%vreg706,%vreg703
3712B		%vreg699<def> = LDRWui %vreg704, 0; mem:LD4[%arrayidx92] GPR32:%vreg699 GPR64common:%vreg704
3728B		%vreg697<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg697
3744B		STRWui %vreg699, %vreg697, 15; mem:ST4[%tPos93] GPR32:%vreg699 GPR64common:%vreg697
3760B		%vreg694<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg694
3776B		%vreg693<def> = LDRWui %vreg694, 15; mem:LD4[%tPos94] GPR32:%vreg693 GPR64common:%vreg694
3792B		%vreg689<def> = ANDWri %vreg693, 7; GPR32common:%vreg689 GPR32:%vreg693
3824B		STRBBui %vreg689, <fi#2>, 0; mem:ST1[FixedStack2] GPR32common:%vreg689
3840B		%vreg686<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg686
3856B		%vreg685<def> = LDRWui %vreg686, 15; mem:LD4[%tPos97] GPR32:%vreg685 GPR64common:%vreg686
3872B		%vreg684<def> = UBFMWri %vreg685, 8, 31; GPR32:%vreg684,%vreg685
3888B		STRWui %vreg684, %vreg686, 15; mem:ST4[%tPos97] GPR32:%vreg684 GPR64common:%vreg686
3904B		%vreg680<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg680
3920B		%vreg679<def> = LDRWui %vreg680, 6; mem:LD4[%rNToGo99] GPR32:%vreg679 GPR64common:%vreg680
3936B		CBNZW %vreg679, <BB#26>; GPR32:%vreg679
	    Successors according to CFG: BB#26 BB#23

3952B	BB#23: derived from LLVM BB %if.then.102
	    Predecessors according to CFG: BB#22
4000B		%vreg744<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg744
4016B		%vreg743<def> = LDRSWui %vreg744, 7; mem:LD4[%rTPos103] GPR64:%vreg743 GPR64common:%vreg744
4024B		%vreg733<def> = ADRP <ga:@BZ2_rNums>[TF=1]; GPR64common:%vreg733
4032B		%vreg736<def> = MOVi64imm 4; GPR64:%vreg736
4040B		%vreg734<def> = ADDXri %vreg733, <ga:@BZ2_rNums>[TF=34], 0; GPR64common:%vreg734,%vreg733
4048B		%vreg737<def> = MADDXrrr %vreg743, %vreg736, %XZR; GPR64:%vreg737,%vreg743,%vreg736
4064B		%vreg738<def> = ADDXrr %vreg734, %vreg737; GPR64common:%vreg738,%vreg734 GPR64:%vreg737
4080B		%vreg732<def> = LDRWui %vreg738, 0; mem:LD4[%arrayidx105] GPR32:%vreg732 GPR64common:%vreg738
4096B		%vreg730<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg730
4112B		STRWui %vreg732, %vreg730, 6; mem:ST4[%rNToGo106] GPR32:%vreg732 GPR64common:%vreg730
4128B		%vreg727<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg727
4144B		%vreg726<def> = LDRWui %vreg727, 7; mem:LD4[%rTPos107] GPR32common:%vreg726 GPR64common:%vreg727
4160B		%vreg725<def> = ADDWri %vreg726, 1, 0; GPR32common:%vreg725,%vreg726
4176B		STRWui %vreg725, %vreg727, 7; mem:ST4[%rTPos107] GPR32common:%vreg725 GPR64common:%vreg727
4192B		%vreg721<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg721
4208B		%vreg720<def> = LDRWui %vreg721, 7; mem:LD4[%rTPos109] GPR32common:%vreg720 GPR64common:%vreg721
4224B		%WZR<def> = SUBSWri %vreg720, 512, 0, %NZCV<imp-def>; GPR32common:%vreg720
4240B		Bcc 1, <BB#25>, %NZCV<imp-use>
	    Successors according to CFG: BB#25 BB#24

4256B	BB#24: derived from LLVM BB %if.then.112
	    Predecessors according to CFG: BB#23
4272B		%vreg746<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg746
4288B		STRWui %WZR, %vreg746, 7; mem:ST4[%rTPos113] GPR64common:%vreg746
	    Successors according to CFG: BB#25

4304B	BB#25: derived from LLVM BB %if.end.114
	    Predecessors according to CFG: BB#23 BB#24
4320B		B <BB#26>
	    Successors according to CFG: BB#26

4336B	BB#26: derived from LLVM BB %if.end.115
	    Predecessors according to CFG: BB#22 BB#25
4344B		%vreg776<def> = COPY %WZR; GPR32:%vreg776
4384B		%vreg786<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg786
4400B		%vreg785<def> = LDRWui %vreg786, 6; mem:LD4[%rNToGo116] GPR32common:%vreg785 GPR64common:%vreg786
4416B		%vreg784<def> = SUBWri %vreg785, 1, 0; GPR32common:%vreg784,%vreg785
4432B		STRWui %vreg784, %vreg786, 6; mem:ST4[%rNToGo116] GPR32common:%vreg784 GPR64common:%vreg786
4448B		%vreg780<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg780
4464B		%vreg779<def> = LDRWui %vreg780, 6; mem:LD4[%rNToGo118] GPR32common:%vreg779 GPR64common:%vreg780
4512B		%vreg773<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg773
4520B		%vreg775<def> = MOVi32imm 1; GPR32:%vreg775
4528B		%WZR<def> = SUBSWri %vreg779, 1, 0, %NZCV<imp-def>; GPR32common:%vreg779
4536B		%vreg777<def> = CSELWr %vreg775, %vreg776, 0, %NZCV<imp-use>; GPR32:%vreg777,%vreg775,%vreg776
4544B		%vreg767<def> = EORWrr %vreg773, %vreg777; GPR32:%vreg767,%vreg773,%vreg777
4560B		STRBBui %vreg767, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg767
4576B		%vreg764<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg764
4592B		%vreg763<def> = LDRWui %vreg764, 273; mem:LD4[%nblock_used125] GPR32common:%vreg763 GPR64common:%vreg764
4608B		%vreg762<def> = ADDWri %vreg763, 1, 0; GPR32common:%vreg762,%vreg763
4624B		STRWui %vreg762, %vreg764, 273; mem:ST4[%nblock_used125] GPR32common:%vreg762 GPR64common:%vreg764
4672B		%vreg755<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg755
4680B		%vreg758<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg758
4688B		%vreg752<def> = MOVi64imm 64080; GPR64:%vreg752
4704B		%vreg753<def> = ADDXrr %vreg755, %vreg752; GPR64common:%vreg753 GPR64:%vreg755,%vreg752
4720B		%vreg754<def> = LDRWui %vreg753, 0; mem:LD4[%save_nblock128] GPR32common:%vreg754 GPR64common:%vreg753
4728B		%vreg757<def> = LDRWui %vreg758, 273; mem:LD4[%nblock_used127] GPR32:%vreg757 GPR64common:%vreg758
4736B		%vreg750<def> = ADDWri %vreg754, 1, 0; GPR32common:%vreg750,%vreg754
4752B		%WZR<def> = SUBSWrr %vreg757, %vreg750, %NZCV<imp-def>; GPR32:%vreg757 GPR32common:%vreg750
4768B		Bcc 1, <BB#28>, %NZCV<imp-use>
	    Successors according to CFG: BB#28 BB#27

4784B	BB#27: derived from LLVM BB %if.then.132
	    Predecessors according to CFG: BB#26
4800B		B <BB#2>
	    Successors according to CFG: BB#2

4816B	BB#28: derived from LLVM BB %if.end.133
	    Predecessors according to CFG: BB#26
4848B		%vreg791<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg791
4856B		%vreg794<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg794
4864B		%vreg790<def> = LDRWui %vreg791, 16; mem:LD4[%k0135] GPR32:%vreg790 GPR64common:%vreg791
4880B		%WZR<def> = SUBSWrr %vreg794, %vreg790, %NZCV<imp-def>; GPR32:%vreg794,%vreg790
4896B		Bcc 0, <BB#30>, %NZCV<imp-use>
	    Successors according to CFG: BB#30 BB#29

4912B	BB#29: derived from LLVM BB %if.then.138
	    Predecessors according to CFG: BB#28
4928B		%vreg1124<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg1124
4944B		%vreg1121<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1121
4960B		STRWui %vreg1124, %vreg1121, 16; mem:ST4[%k0140] GPR32:%vreg1124 GPR64common:%vreg1121
4976B		B <BB#2>
	    Successors according to CFG: BB#2

4992B	BB#30: derived from LLVM BB %if.end.141
	    Predecessors according to CFG: BB#28
5024B		%vreg835<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg835
5032B		%vreg833<def> = MOVi32imm 3; GPR32:%vreg833
5040B		STRWui %vreg833, %vreg835, 4; mem:ST4[%state_out_len142] GPR32:%vreg833 GPR64common:%vreg835
5056B		%vreg832<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg832
5104B		%vreg825<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg825
5112B		%vreg831:sub_32<def,read-undef> = LDRWui %vreg832, 15; mem:LD4[%tPos143] GPR64:%vreg831 GPR64common:%vreg832
5120B		%vreg824<def> = LDRXui %vreg825, 394; mem:LD8[%tt145] GPR64:%vreg824 GPR64common:%vreg825
5136B		%vreg820<def> = MOVi64imm 4; GPR64:%vreg820
5152B		%vreg821<def> = MADDXrrr %vreg831, %vreg820, %XZR; GPR64:%vreg821,%vreg831,%vreg820
5168B		%vreg822<def> = ADDXrr %vreg824, %vreg821; GPR64common:%vreg822 GPR64:%vreg824,%vreg821
5184B		%vreg817<def> = LDRWui %vreg822, 0; mem:LD4[%arrayidx146] GPR32:%vreg817 GPR64common:%vreg822
5200B		%vreg815<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg815
5216B		STRWui %vreg817, %vreg815, 15; mem:ST4[%tPos147] GPR32:%vreg817 GPR64common:%vreg815
5232B		%vreg812<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg812
5248B		%vreg811<def> = LDRWui %vreg812, 15; mem:LD4[%tPos148] GPR32:%vreg811 GPR64common:%vreg812
5264B		%vreg807<def> = ANDWri %vreg811, 7; GPR32common:%vreg807 GPR32:%vreg811
5296B		STRBBui %vreg807, <fi#2>, 0; mem:ST1[FixedStack2] GPR32common:%vreg807
5312B		%vreg804<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg804
5328B		%vreg803<def> = LDRWui %vreg804, 15; mem:LD4[%tPos151] GPR32:%vreg803 GPR64common:%vreg804
5344B		%vreg802<def> = UBFMWri %vreg803, 8, 31; GPR32:%vreg802,%vreg803
5360B		STRWui %vreg802, %vreg804, 15; mem:ST4[%tPos151] GPR32:%vreg802 GPR64common:%vreg804
5376B		%vreg798<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg798
5392B		%vreg797<def> = LDRWui %vreg798, 6; mem:LD4[%rNToGo153] GPR32:%vreg797 GPR64common:%vreg798
5408B		CBNZW %vreg797, <BB#34>; GPR32:%vreg797
	    Successors according to CFG: BB#34 BB#31

5424B	BB#31: derived from LLVM BB %if.then.156
	    Predecessors according to CFG: BB#30
5472B		%vreg862<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg862
5488B		%vreg861<def> = LDRSWui %vreg862, 7; mem:LD4[%rTPos157] GPR64:%vreg861 GPR64common:%vreg862
5496B		%vreg851<def> = ADRP <ga:@BZ2_rNums>[TF=1]; GPR64common:%vreg851
5504B		%vreg854<def> = MOVi64imm 4; GPR64:%vreg854
5512B		%vreg852<def> = ADDXri %vreg851, <ga:@BZ2_rNums>[TF=34], 0; GPR64common:%vreg852,%vreg851
5520B		%vreg855<def> = MADDXrrr %vreg861, %vreg854, %XZR; GPR64:%vreg855,%vreg861,%vreg854
5536B		%vreg856<def> = ADDXrr %vreg852, %vreg855; GPR64common:%vreg856,%vreg852 GPR64:%vreg855
5552B		%vreg850<def> = LDRWui %vreg856, 0; mem:LD4[%arrayidx159] GPR32:%vreg850 GPR64common:%vreg856
5568B		%vreg848<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg848
5584B		STRWui %vreg850, %vreg848, 6; mem:ST4[%rNToGo160] GPR32:%vreg850 GPR64common:%vreg848
5600B		%vreg845<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg845
5616B		%vreg844<def> = LDRWui %vreg845, 7; mem:LD4[%rTPos161] GPR32common:%vreg844 GPR64common:%vreg845
5632B		%vreg843<def> = ADDWri %vreg844, 1, 0; GPR32common:%vreg843,%vreg844
5648B		STRWui %vreg843, %vreg845, 7; mem:ST4[%rTPos161] GPR32common:%vreg843 GPR64common:%vreg845
5664B		%vreg839<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg839
5680B		%vreg838<def> = LDRWui %vreg839, 7; mem:LD4[%rTPos163] GPR32common:%vreg838 GPR64common:%vreg839
5696B		%WZR<def> = SUBSWri %vreg838, 512, 0, %NZCV<imp-def>; GPR32common:%vreg838
5712B		Bcc 1, <BB#33>, %NZCV<imp-use>
	    Successors according to CFG: BB#33 BB#32

5728B	BB#32: derived from LLVM BB %if.then.166
	    Predecessors according to CFG: BB#31
5744B		%vreg864<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg864
5760B		STRWui %WZR, %vreg864, 7; mem:ST4[%rTPos167] GPR64common:%vreg864
	    Successors according to CFG: BB#33

5776B	BB#33: derived from LLVM BB %if.end.168
	    Predecessors according to CFG: BB#31 BB#32
5792B		B <BB#34>
	    Successors according to CFG: BB#34

5808B	BB#34: derived from LLVM BB %if.end.169
	    Predecessors according to CFG: BB#30 BB#33
5816B		%vreg894<def> = COPY %WZR; GPR32:%vreg894
5856B		%vreg904<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg904
5872B		%vreg903<def> = LDRWui %vreg904, 6; mem:LD4[%rNToGo170] GPR32common:%vreg903 GPR64common:%vreg904
5888B		%vreg902<def> = SUBWri %vreg903, 1, 0; GPR32common:%vreg902,%vreg903
5904B		STRWui %vreg902, %vreg904, 6; mem:ST4[%rNToGo170] GPR32common:%vreg902 GPR64common:%vreg904
5920B		%vreg898<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg898
5936B		%vreg897<def> = LDRWui %vreg898, 6; mem:LD4[%rNToGo172] GPR32common:%vreg897 GPR64common:%vreg898
5984B		%vreg891<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg891
5992B		%vreg893<def> = MOVi32imm 1; GPR32:%vreg893
6000B		%WZR<def> = SUBSWri %vreg897, 1, 0, %NZCV<imp-def>; GPR32common:%vreg897
6008B		%vreg895<def> = CSELWr %vreg893, %vreg894, 0, %NZCV<imp-use>; GPR32:%vreg895,%vreg893,%vreg894
6016B		%vreg885<def> = EORWrr %vreg891, %vreg895; GPR32:%vreg885,%vreg891,%vreg895
6032B		STRBBui %vreg885, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg885
6048B		%vreg882<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg882
6064B		%vreg881<def> = LDRWui %vreg882, 273; mem:LD4[%nblock_used179] GPR32common:%vreg881 GPR64common:%vreg882
6080B		%vreg880<def> = ADDWri %vreg881, 1, 0; GPR32common:%vreg880,%vreg881
6096B		STRWui %vreg880, %vreg882, 273; mem:ST4[%nblock_used179] GPR32common:%vreg880 GPR64common:%vreg882
6144B		%vreg873<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg873
6152B		%vreg876<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg876
6160B		%vreg870<def> = MOVi64imm 64080; GPR64:%vreg870
6176B		%vreg871<def> = ADDXrr %vreg873, %vreg870; GPR64common:%vreg871 GPR64:%vreg873,%vreg870
6192B		%vreg872<def> = LDRWui %vreg871, 0; mem:LD4[%save_nblock182] GPR32common:%vreg872 GPR64common:%vreg871
6200B		%vreg875<def> = LDRWui %vreg876, 273; mem:LD4[%nblock_used181] GPR32:%vreg875 GPR64common:%vreg876
6208B		%vreg868<def> = ADDWri %vreg872, 1, 0; GPR32common:%vreg868,%vreg872
6224B		%WZR<def> = SUBSWrr %vreg875, %vreg868, %NZCV<imp-def>; GPR32:%vreg875 GPR32common:%vreg868
6240B		Bcc 1, <BB#36>, %NZCV<imp-use>
	    Successors according to CFG: BB#36 BB#35

6256B	BB#35: derived from LLVM BB %if.then.186
	    Predecessors according to CFG: BB#34
6272B		B <BB#2>
	    Successors according to CFG: BB#2

6288B	BB#36: derived from LLVM BB %if.end.187
	    Predecessors according to CFG: BB#34
6320B		%vreg909<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg909
6328B		%vreg912<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg912
6336B		%vreg908<def> = LDRWui %vreg909, 16; mem:LD4[%k0189] GPR32:%vreg908 GPR64common:%vreg909
6352B		%WZR<def> = SUBSWrr %vreg912, %vreg908, %NZCV<imp-def>; GPR32:%vreg912,%vreg908
6368B		Bcc 0, <BB#38>, %NZCV<imp-use>
	    Successors according to CFG: BB#38 BB#37

6384B	BB#37: derived from LLVM BB %if.then.192
	    Predecessors according to CFG: BB#36
6400B		%vreg1118<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg1118
6416B		%vreg1115<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1115
6432B		STRWui %vreg1118, %vreg1115, 16; mem:ST4[%k0194] GPR32:%vreg1118 GPR64common:%vreg1115
6448B		B <BB#2>
	    Successors according to CFG: BB#2

6464B	BB#38: derived from LLVM BB %if.end.195
	    Predecessors according to CFG: BB#36
6480B		%vreg950<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg950
6528B		%vreg943<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg943
6536B		%vreg949:sub_32<def,read-undef> = LDRWui %vreg950, 15; mem:LD4[%tPos196] GPR64:%vreg949 GPR64common:%vreg950
6544B		%vreg942<def> = LDRXui %vreg943, 394; mem:LD8[%tt198] GPR64:%vreg942 GPR64common:%vreg943
6560B		%vreg938<def> = MOVi64imm 4; GPR64:%vreg938
6576B		%vreg939<def> = MADDXrrr %vreg949, %vreg938, %XZR; GPR64:%vreg939,%vreg949,%vreg938
6592B		%vreg940<def> = ADDXrr %vreg942, %vreg939; GPR64common:%vreg940 GPR64:%vreg942,%vreg939
6608B		%vreg935<def> = LDRWui %vreg940, 0; mem:LD4[%arrayidx199] GPR32:%vreg935 GPR64common:%vreg940
6624B		%vreg933<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg933
6640B		STRWui %vreg935, %vreg933, 15; mem:ST4[%tPos200] GPR32:%vreg935 GPR64common:%vreg933
6656B		%vreg930<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg930
6672B		%vreg929<def> = LDRWui %vreg930, 15; mem:LD4[%tPos201] GPR32:%vreg929 GPR64common:%vreg930
6688B		%vreg925<def> = ANDWri %vreg929, 7; GPR32common:%vreg925 GPR32:%vreg929
6720B		STRBBui %vreg925, <fi#2>, 0; mem:ST1[FixedStack2] GPR32common:%vreg925
6736B		%vreg922<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg922
6752B		%vreg921<def> = LDRWui %vreg922, 15; mem:LD4[%tPos204] GPR32:%vreg921 GPR64common:%vreg922
6768B		%vreg920<def> = UBFMWri %vreg921, 8, 31; GPR32:%vreg920,%vreg921
6784B		STRWui %vreg920, %vreg922, 15; mem:ST4[%tPos204] GPR32:%vreg920 GPR64common:%vreg922
6800B		%vreg916<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg916
6816B		%vreg915<def> = LDRWui %vreg916, 6; mem:LD4[%rNToGo206] GPR32:%vreg915 GPR64common:%vreg916
6832B		CBNZW %vreg915, <BB#42>; GPR32:%vreg915
	    Successors according to CFG: BB#42 BB#39

6848B	BB#39: derived from LLVM BB %if.then.209
	    Predecessors according to CFG: BB#38
6896B		%vreg977<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg977
6912B		%vreg976<def> = LDRSWui %vreg977, 7; mem:LD4[%rTPos210] GPR64:%vreg976 GPR64common:%vreg977
6920B		%vreg966<def> = ADRP <ga:@BZ2_rNums>[TF=1]; GPR64common:%vreg966
6928B		%vreg969<def> = MOVi64imm 4; GPR64:%vreg969
6936B		%vreg967<def> = ADDXri %vreg966, <ga:@BZ2_rNums>[TF=34], 0; GPR64common:%vreg967,%vreg966
6944B		%vreg970<def> = MADDXrrr %vreg976, %vreg969, %XZR; GPR64:%vreg970,%vreg976,%vreg969
6960B		%vreg971<def> = ADDXrr %vreg967, %vreg970; GPR64common:%vreg971,%vreg967 GPR64:%vreg970
6976B		%vreg965<def> = LDRWui %vreg971, 0; mem:LD4[%arrayidx212] GPR32:%vreg965 GPR64common:%vreg971
6992B		%vreg963<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg963
7008B		STRWui %vreg965, %vreg963, 6; mem:ST4[%rNToGo213] GPR32:%vreg965 GPR64common:%vreg963
7024B		%vreg960<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg960
7040B		%vreg959<def> = LDRWui %vreg960, 7; mem:LD4[%rTPos214] GPR32common:%vreg959 GPR64common:%vreg960
7056B		%vreg958<def> = ADDWri %vreg959, 1, 0; GPR32common:%vreg958,%vreg959
7072B		STRWui %vreg958, %vreg960, 7; mem:ST4[%rTPos214] GPR32common:%vreg958 GPR64common:%vreg960
7088B		%vreg954<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg954
7104B		%vreg953<def> = LDRWui %vreg954, 7; mem:LD4[%rTPos216] GPR32common:%vreg953 GPR64common:%vreg954
7120B		%WZR<def> = SUBSWri %vreg953, 512, 0, %NZCV<imp-def>; GPR32common:%vreg953
7136B		Bcc 1, <BB#41>, %NZCV<imp-use>
	    Successors according to CFG: BB#41 BB#40

7152B	BB#40: derived from LLVM BB %if.then.219
	    Predecessors according to CFG: BB#39
7168B		%vreg979<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg979
7184B		STRWui %WZR, %vreg979, 7; mem:ST4[%rTPos220] GPR64common:%vreg979
	    Successors according to CFG: BB#41

7200B	BB#41: derived from LLVM BB %if.end.221
	    Predecessors according to CFG: BB#39 BB#40
7216B		B <BB#42>
	    Successors according to CFG: BB#42

7232B	BB#42: derived from LLVM BB %if.end.222
	    Predecessors according to CFG: BB#38 BB#41
7240B		%vreg1047<def> = COPY %WZR; GPR32:%vreg1047
7280B		%vreg1057<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1057
7296B		%vreg1056<def> = LDRWui %vreg1057, 6; mem:LD4[%rNToGo223] GPR32common:%vreg1056 GPR64common:%vreg1057
7312B		%vreg1055<def> = SUBWri %vreg1056, 1, 0; GPR32common:%vreg1055,%vreg1056
7328B		STRWui %vreg1055, %vreg1057, 6; mem:ST4[%rNToGo223] GPR32common:%vreg1055 GPR64common:%vreg1057
7344B		%vreg1051<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1051
7360B		%vreg1050<def> = LDRWui %vreg1051, 6; mem:LD4[%rNToGo225] GPR32common:%vreg1050 GPR64common:%vreg1051
7408B		%vreg1044<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg1044
7416B		%vreg1046<def> = MOVi32imm 1; GPR32:%vreg1046
7424B		%WZR<def> = SUBSWri %vreg1050, 1, 0, %NZCV<imp-def>; GPR32common:%vreg1050
7432B		%vreg1048<def> = CSELWr %vreg1046, %vreg1047, 0, %NZCV<imp-use>; GPR32:%vreg1048,%vreg1046,%vreg1047
7440B		%vreg1038<def> = EORWrr %vreg1044, %vreg1048; GPR32:%vreg1038,%vreg1044,%vreg1048
7456B		STRBBui %vreg1038, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg1038
7472B		%vreg1035<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1035
7488B		%vreg1034<def> = LDRWui %vreg1035, 273; mem:LD4[%nblock_used232] GPR32common:%vreg1034 GPR64common:%vreg1035
7504B		%vreg1033<def> = ADDWri %vreg1034, 1, 0; GPR32common:%vreg1033,%vreg1034
7520B		STRWui %vreg1033, %vreg1035, 273; mem:ST4[%nblock_used232] GPR32common:%vreg1033 GPR64common:%vreg1035
7536B		%vreg1029<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32common:%vreg1029
7568B		%vreg1024<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1024
7576B		%vreg1026<def> = ADDWri %vreg1029, 4, 0; GPR32common:%vreg1026,%vreg1029
7584B		STRWui %vreg1026, %vreg1024, 4; mem:ST4[%state_out_len236] GPR32common:%vreg1026 GPR64common:%vreg1024
7600B		%vreg1021<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1021
7648B		%vreg1014<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1014
7656B		%vreg1020:sub_32<def,read-undef> = LDRWui %vreg1021, 15; mem:LD4[%tPos237] GPR64:%vreg1020 GPR64common:%vreg1021
7664B		%vreg1013<def> = LDRXui %vreg1014, 394; mem:LD8[%tt239] GPR64:%vreg1013 GPR64common:%vreg1014
7680B		%vreg1009<def> = MOVi64imm 4; GPR64:%vreg1009
7696B		%vreg1010<def> = MADDXrrr %vreg1020, %vreg1009, %XZR; GPR64:%vreg1010,%vreg1020,%vreg1009
7712B		%vreg1011<def> = ADDXrr %vreg1013, %vreg1010; GPR64common:%vreg1011 GPR64:%vreg1013,%vreg1010
7728B		%vreg1006<def> = LDRWui %vreg1011, 0; mem:LD4[%arrayidx240] GPR32:%vreg1006 GPR64common:%vreg1011
7744B		%vreg1004<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1004
7760B		STRWui %vreg1006, %vreg1004, 15; mem:ST4[%tPos241] GPR32:%vreg1006 GPR64common:%vreg1004
7776B		%vreg1001<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1001
7792B		%vreg1000<def> = LDRWui %vreg1001, 15; mem:LD4[%tPos242] GPR32:%vreg1000 GPR64common:%vreg1001
7856B		%vreg992<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg992
7860B		%vreg996<def> = ANDWri %vreg1000, 7; GPR32common:%vreg996 GPR32:%vreg1000
7864B		%vreg994<def> = UBFMWri %vreg996, 0, 7; GPR32:%vreg994 GPR32common:%vreg996
7872B		STRWui %vreg994, %vreg992, 16; mem:ST4[%k0246] GPR32:%vreg994 GPR64common:%vreg992
7888B		%vreg989<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg989
7904B		%vreg988<def> = LDRWui %vreg989, 15; mem:LD4[%tPos247] GPR32:%vreg988 GPR64common:%vreg989
7920B		%vreg987<def> = UBFMWri %vreg988, 8, 31; GPR32:%vreg987,%vreg988
7936B		STRWui %vreg987, %vreg989, 15; mem:ST4[%tPos247] GPR32:%vreg987 GPR64common:%vreg989
7952B		%vreg983<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg983
7968B		%vreg982<def> = LDRWui %vreg983, 6; mem:LD4[%rNToGo249] GPR32:%vreg982 GPR64common:%vreg983
7984B		CBNZW %vreg982, <BB#46>; GPR32:%vreg982
	    Successors according to CFG: BB#46 BB#43

8000B	BB#43: derived from LLVM BB %if.then.252
	    Predecessors according to CFG: BB#42
8048B		%vreg1084<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1084
8064B		%vreg1083<def> = LDRSWui %vreg1084, 7; mem:LD4[%rTPos253] GPR64:%vreg1083 GPR64common:%vreg1084
8072B		%vreg1073<def> = ADRP <ga:@BZ2_rNums>[TF=1]; GPR64common:%vreg1073
8080B		%vreg1076<def> = MOVi64imm 4; GPR64:%vreg1076
8088B		%vreg1074<def> = ADDXri %vreg1073, <ga:@BZ2_rNums>[TF=34], 0; GPR64common:%vreg1074,%vreg1073
8096B		%vreg1077<def> = MADDXrrr %vreg1083, %vreg1076, %XZR; GPR64:%vreg1077,%vreg1083,%vreg1076
8112B		%vreg1078<def> = ADDXrr %vreg1074, %vreg1077; GPR64common:%vreg1078,%vreg1074 GPR64:%vreg1077
8128B		%vreg1072<def> = LDRWui %vreg1078, 0; mem:LD4[%arrayidx255] GPR32:%vreg1072 GPR64common:%vreg1078
8144B		%vreg1070<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1070
8160B		STRWui %vreg1072, %vreg1070, 6; mem:ST4[%rNToGo256] GPR32:%vreg1072 GPR64common:%vreg1070
8176B		%vreg1067<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1067
8192B		%vreg1066<def> = LDRWui %vreg1067, 7; mem:LD4[%rTPos257] GPR32common:%vreg1066 GPR64common:%vreg1067
8208B		%vreg1065<def> = ADDWri %vreg1066, 1, 0; GPR32common:%vreg1065,%vreg1066
8224B		STRWui %vreg1065, %vreg1067, 7; mem:ST4[%rTPos257] GPR32common:%vreg1065 GPR64common:%vreg1067
8240B		%vreg1061<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1061
8256B		%vreg1060<def> = LDRWui %vreg1061, 7; mem:LD4[%rTPos259] GPR32common:%vreg1060 GPR64common:%vreg1061
8272B		%WZR<def> = SUBSWri %vreg1060, 512, 0, %NZCV<imp-def>; GPR32common:%vreg1060
8288B		Bcc 1, <BB#45>, %NZCV<imp-use>
	    Successors according to CFG: BB#45 BB#44

8304B	BB#44: derived from LLVM BB %if.then.262
	    Predecessors according to CFG: BB#43
8320B		%vreg1086<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1086
8336B		STRWui %WZR, %vreg1086, 7; mem:ST4[%rTPos263] GPR64common:%vreg1086
	    Successors according to CFG: BB#45

8352B	BB#45: derived from LLVM BB %if.end.264
	    Predecessors according to CFG: BB#43 BB#44
8368B		B <BB#46>
	    Successors according to CFG: BB#46

8384B	BB#46: derived from LLVM BB %if.end.265
	    Predecessors according to CFG: BB#42 BB#45
8392B		%vreg1102<def> = COPY %WZR; GPR32:%vreg1102
8432B		%vreg1112<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1112
8448B		%vreg1111<def> = LDRWui %vreg1112, 6; mem:LD4[%rNToGo266] GPR32common:%vreg1111 GPR64common:%vreg1112
8464B		%vreg1110<def> = SUBWri %vreg1111, 1, 0; GPR32common:%vreg1110,%vreg1111
8480B		STRWui %vreg1110, %vreg1112, 6; mem:ST4[%rNToGo266] GPR32common:%vreg1110 GPR64common:%vreg1112
8496B		%vreg1106<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1106
8560B		%vreg1099<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1099
8568B		%vreg1105<def> = LDRWui %vreg1106, 6; mem:LD4[%rNToGo268] GPR32common:%vreg1105 GPR64common:%vreg1106
8576B		%vreg1098<def> = LDRWui %vreg1099, 16; mem:LD4[%k0272] GPR32:%vreg1098 GPR64common:%vreg1099
8584B		%WZR<def> = SUBSWri %vreg1105, 1, 0, %NZCV<imp-def>; GPR32common:%vreg1105
8592B		%vreg1101<def> = MOVi32imm 1; GPR32:%vreg1101
8600B		%vreg1103<def> = CSELWr %vreg1101, %vreg1102, 0, %NZCV<imp-use>; GPR32:%vreg1103,%vreg1101,%vreg1102
8608B		%vreg1097<def> = EORWrr %vreg1098, %vreg1103; GPR32:%vreg1097,%vreg1098,%vreg1103
8616B		STRWui %vreg1097, %vreg1099, 16; mem:ST4[%k0272] GPR32:%vreg1097 GPR64common:%vreg1099
8624B		%vreg1092<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1092
8640B		%vreg1091<def> = LDRWui %vreg1092, 273; mem:LD4[%nblock_used274] GPR32common:%vreg1091 GPR64common:%vreg1092
8656B		%vreg1090<def> = ADDWri %vreg1091, 1, 0; GPR32common:%vreg1090,%vreg1091
8672B		STRWui %vreg1090, %vreg1092, 273; mem:ST4[%nblock_used274] GPR32common:%vreg1090 GPR64common:%vreg1092
8688B		B <BB#2>
	    Successors according to CFG: BB#2

8704B	BB#47: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#0
8720B		%vreg61<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg61
8736B		%vreg60<def> = LDRWui %vreg61, 796; mem:LD4[%calculatedBlockCRC276] GPR32:%vreg60 GPR64common:%vreg61
8752B		STRWui %vreg60, <fi#3>, 0; mem:ST4[FixedStack3] GPR32:%vreg60
8768B		%vreg57<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg57
8784B		%vreg56<def> = LDRBBui %vreg57, 12; mem:LD1[%state_out_ch277] GPR32:%vreg56 GPR64common:%vreg57
8800B		STRBBui %vreg56, <fi#4>, 0; mem:ST1[FixedStack4] GPR32:%vreg56
8816B		%vreg53<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg53
8832B		%vreg52<def> = LDRWui %vreg53, 4; mem:LD4[%state_out_len278] GPR32:%vreg52 GPR64common:%vreg53
8848B		STRWui %vreg52, <fi#5>, 0; mem:ST4[FixedStack5] GPR32:%vreg52
8864B		%vreg49<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg49
8880B		%vreg48<def> = LDRWui %vreg49, 273; mem:LD4[%nblock_used279] GPR32:%vreg48 GPR64common:%vreg49
8896B		STRWui %vreg48, <fi#6>, 0; mem:ST4[FixedStack6] GPR32:%vreg48
8912B		%vreg45<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg45
8928B		%vreg44<def> = LDRWui %vreg45, 16; mem:LD4[%k0280] GPR32:%vreg44 GPR64common:%vreg45
8944B		STRWui %vreg44, <fi#7>, 0; mem:ST4[FixedStack7] GPR32:%vreg44
8960B		%vreg41<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg41
8976B		%vreg40<def> = LDRXui %vreg41, 394; mem:LD8[%tt281] GPR64:%vreg40 GPR64common:%vreg41
8992B		STRXui %vreg40, <fi#8>, 0; mem:ST8[FixedStack8] GPR64:%vreg40
9008B		%vreg37<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg37
9024B		%vreg36<def> = LDRWui %vreg37, 15; mem:LD4[%tPos282] GPR32:%vreg36 GPR64common:%vreg37
9040B		STRWui %vreg36, <fi#9>, 0; mem:ST4[FixedStack9] GPR32:%vreg36
9056B		%vreg33<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg33
9072B		%vreg32<def> = LDRXui %vreg33, 0; mem:LD8[%strm283] GPR64common:%vreg32,%vreg33
9088B		%vreg30<def> = LDRXui %vreg32, 3; mem:LD8[%next_out284] GPR64:%vreg30 GPR64common:%vreg32
9104B		STRXui %vreg30, <fi#10>, 0; mem:ST8[FixedStack10] GPR64:%vreg30
9120B		%vreg27<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg27
9136B		%vreg26<def> = LDRXui %vreg27, 0; mem:LD8[%strm285] GPR64common:%vreg26,%vreg27
9152B		%vreg24<def> = LDRWui %vreg26, 8; mem:LD4[%avail_out286] GPR32:%vreg24 GPR64common:%vreg26
9168B		STRWui %vreg24, <fi#11>, 0; mem:ST4[FixedStack11] GPR32:%vreg24
9184B		%vreg21<def> = LDRWui <fi#11>, 0; mem:LD4[FixedStack11] GPR32:%vreg21
9200B		STRWui %vreg21, <fi#12>, 0; mem:ST4[FixedStack12] GPR32:%vreg21
9216B		%vreg19<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg19
9232B		%vreg16<def> = MOVi64imm 64080; GPR64:%vreg16
9248B		%vreg17<def> = ADDXrr %vreg19, %vreg16; GPR64common:%vreg17 GPR64:%vreg19,%vreg16
9264B		%vreg18<def> = LDRWui %vreg17, 0; mem:LD4[%save_nblock287] GPR32common:%vreg18 GPR64common:%vreg17
9280B		%vreg14<def> = ADDWri %vreg18, 1, 0; GPR32common:%vreg14,%vreg18
9296B		STRWui %vreg14, <fi#13>, 0; mem:ST4[FixedStack13] GPR32common:%vreg14
	    Successors according to CFG: BB#48

9312B	BB#48: derived from LLVM BB %while.body.289
	    Predecessors according to CFG: BB#47 BB#75 BB#74 BB#72 BB#70 BB#68
9328B		%vreg63<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32common:%vreg63
9344B		%WZR<def> = SUBSWri %vreg63, 0, 0, %NZCV<imp-def>; GPR32common:%vreg63
9360B		Bcc 13, <BB#59>, %NZCV<imp-use>
	    Successors according to CFG: BB#59 BB#49

9376B	BB#49: derived from LLVM BB %if.then.292
	    Predecessors according to CFG: BB#48
9392B		B <BB#50>
	    Successors according to CFG: BB#50

9408B	BB#50: derived from LLVM BB %while.body.294
	    Predecessors according to CFG: BB#49 BB#54
9424B		%vreg65<def> = LDRWui <fi#11>, 0; mem:LD4[FixedStack11] GPR32:%vreg65
9440B		CBNZW %vreg65, <BB#52>; GPR32:%vreg65
	    Successors according to CFG: BB#52 BB#51

9456B	BB#51: derived from LLVM BB %if.then.297
	    Predecessors according to CFG: BB#50
9472B		B <BB#76>
	    Successors according to CFG: BB#76

9488B	BB#52: derived from LLVM BB %if.end.298
	    Predecessors according to CFG: BB#50
9504B		%vreg67<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32common:%vreg67
9520B		%WZR<def> = SUBSWri %vreg67, 1, 0, %NZCV<imp-def>; GPR32common:%vreg67
9536B		Bcc 1, <BB#54>, %NZCV<imp-use>
	    Successors according to CFG: BB#54 BB#53

9552B	BB#53: derived from LLVM BB %if.then.301
	    Predecessors according to CFG: BB#52
9568B		B <BB#55>
	    Successors according to CFG: BB#55

9584B	BB#54: derived from LLVM BB %if.end.302
	    Predecessors according to CFG: BB#52
9632B		%vreg108<def> = LDRBBui <fi#4>, 0; mem:LD1[FixedStack4] GPR32:%vreg108
9648B		%vreg107<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg107
9656B		%vreg86<def> = ADRP <ga:@BZ2_crc32Table>[TF=1]; GPR64common:%vreg86
9664B		STRBBui %vreg108, %vreg107, 0; mem:ST1[%249] GPR32:%vreg108 GPR64common:%vreg107
9696B		%vreg103<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg103
9728B		%vreg100<def> = LDRBBui <fi#4>, 0; mem:LD1[FixedStack4] GPR32:%vreg100
9736B		%vreg87<def> = ADDXri %vreg86, <ga:@BZ2_crc32Table>[TF=34], 0; GPR64common:%vreg87,%vreg86
9744B		%vreg104<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg104
9752B		%vreg102<def> = UBFMWri %vreg103, 24, 31; GPR32:%vreg102,%vreg103
9760B		%vreg93:sub_32<def,read-undef> = EORWrr %vreg102, %vreg100; GPR64:%vreg93 GPR32:%vreg102,%vreg100
9776B		%vreg94<def> = UBFMXri %vreg93, 0, 31; GPR64:%vreg94,%vreg93
9792B		%vreg89<def> = MOVi64imm 4; GPR64:%vreg89
9808B		%vreg90<def> = MADDXrrr %vreg94, %vreg89, %XZR; GPR64:%vreg90,%vreg94,%vreg89
9824B		%vreg91<def> = ADDXrr %vreg87, %vreg90; GPR64common:%vreg91,%vreg87 GPR64:%vreg90
9840B		%vreg85<def> = LDRWui %vreg91, 0; mem:LD4[%arrayidx308] GPR32:%vreg85 GPR64common:%vreg91
9856B		%vreg83<def> = EORWrs %vreg85, %vreg104, 8; GPR32:%vreg83,%vreg85,%vreg104
9872B		STRWui %vreg83, <fi#3>, 0; mem:ST4[FixedStack3] GPR32:%vreg83
9888B		%vreg79<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32common:%vreg79
9904B		%vreg78<def> = SUBWri %vreg79, 1, 0; GPR32common:%vreg78,%vreg79
9920B		STRWui %vreg78, <fi#5>, 0; mem:ST4[FixedStack5] GPR32common:%vreg78
9936B		%vreg75<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg75
9952B		%vreg74<def> = ADDXri %vreg75, 1, 0; GPR64common:%vreg74,%vreg75
9968B		STRXui %vreg74, <fi#10>, 0; mem:ST8[FixedStack10] GPR64common:%vreg74
9984B		%vreg71<def> = LDRWui <fi#11>, 0; mem:LD4[FixedStack11] GPR32common:%vreg71
10000B		%vreg70<def> = SUBWri %vreg71, 1, 0; GPR32common:%vreg70,%vreg71
10016B		STRWui %vreg70, <fi#11>, 0; mem:ST4[FixedStack11] GPR32common:%vreg70
10032B		B <BB#50>
	    Successors according to CFG: BB#50

10048B	BB#55: derived from LLVM BB %while.end.313
	    Predecessors according to CFG: BB#53
10064B		B <BB#56>
	    Successors according to CFG: BB#56

10080B	BB#56: derived from LLVM BB %s_state_out_len_eq_one
	    Predecessors according to CFG: BB#55 BB#66 BB#64
10096B		%vreg110<def> = LDRWui <fi#11>, 0; mem:LD4[FixedStack11] GPR32:%vreg110
10112B		CBNZW %vreg110, <BB#58>; GPR32:%vreg110
	    Successors according to CFG: BB#58 BB#57

10128B	BB#57: derived from LLVM BB %if.then.316
	    Predecessors according to CFG: BB#56
10144B		%vreg353<def> = MOVi32imm 1; GPR32:%vreg353
10160B		STRWui %vreg353, <fi#5>, 0; mem:ST4[FixedStack5] GPR32:%vreg353
10176B		B <BB#76>
	    Successors according to CFG: BB#76

10192B	BB#58: derived from LLVM BB %if.end.317
	    Predecessors according to CFG: BB#56
10240B		%vreg147<def> = LDRBBui <fi#4>, 0; mem:LD1[FixedStack4] GPR32:%vreg147
10256B		%vreg146<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg146
10264B		%vreg125<def> = ADRP <ga:@BZ2_crc32Table>[TF=1]; GPR64common:%vreg125
10272B		STRBBui %vreg147, %vreg146, 0; mem:ST1[%259] GPR32:%vreg147 GPR64common:%vreg146
10304B		%vreg142<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg142
10336B		%vreg139<def> = LDRBBui <fi#4>, 0; mem:LD1[FixedStack4] GPR32:%vreg139
10344B		%vreg126<def> = ADDXri %vreg125, <ga:@BZ2_crc32Table>[TF=34], 0; GPR64common:%vreg126,%vreg125
10352B		%vreg143<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg143
10360B		%vreg141<def> = UBFMWri %vreg142, 24, 31; GPR32:%vreg141,%vreg142
10368B		%vreg132:sub_32<def,read-undef> = EORWrr %vreg141, %vreg139; GPR64:%vreg132 GPR32:%vreg141,%vreg139
10384B		%vreg133<def> = UBFMXri %vreg132, 0, 31; GPR64:%vreg133,%vreg132
10400B		%vreg128<def> = MOVi64imm 4; GPR64:%vreg128
10416B		%vreg129<def> = MADDXrrr %vreg133, %vreg128, %XZR; GPR64:%vreg129,%vreg133,%vreg128
10432B		%vreg130<def> = ADDXrr %vreg126, %vreg129; GPR64common:%vreg130,%vreg126 GPR64:%vreg129
10448B		%vreg124<def> = LDRWui %vreg130, 0; mem:LD4[%arrayidx323] GPR32:%vreg124 GPR64common:%vreg130
10464B		%vreg122<def> = EORWrs %vreg124, %vreg143, 8; GPR32:%vreg122,%vreg124,%vreg143
10480B		STRWui %vreg122, <fi#3>, 0; mem:ST4[FixedStack3] GPR32:%vreg122
10496B		%vreg118<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg118
10512B		%vreg117<def> = ADDXri %vreg118, 1, 0; GPR64common:%vreg117,%vreg118
10528B		STRXui %vreg117, <fi#10>, 0; mem:ST8[FixedStack10] GPR64common:%vreg117
10544B		%vreg114<def> = LDRWui <fi#11>, 0; mem:LD4[FixedStack11] GPR32common:%vreg114
10560B		%vreg113<def> = SUBWri %vreg114, 1, 0; GPR32common:%vreg113,%vreg114
10576B		STRWui %vreg113, <fi#11>, 0; mem:ST4[FixedStack11] GPR32common:%vreg113
	    Successors according to CFG: BB#59

10592B	BB#59: derived from LLVM BB %if.end.327
	    Predecessors according to CFG: BB#48 BB#58
10608B		%vreg151<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg151
10624B		%vreg150<def> = LDRWui <fi#13>, 0; mem:LD4[FixedStack13] GPR32:%vreg150
10640B		%WZR<def> = SUBSWrr %vreg151, %vreg150, %NZCV<imp-def>; GPR32:%vreg151,%vreg150
10656B		Bcc 13, <BB#61>, %NZCV<imp-use>
	    Successors according to CFG: BB#61 BB#60

10672B	BB#60: derived from LLVM BB %if.then.330
	    Predecessors according to CFG: BB#59
10688B		%vreg352<def> = MOVi32imm 1; GPR32:%vreg352
10704B		STRBBui %vreg352, <fi#0>, 0; mem:ST1[FixedStack0] GPR32:%vreg352
10720B		B <BB#80>
	    Successors according to CFG: BB#80

10736B	BB#61: derived from LLVM BB %if.end.331
	    Predecessors according to CFG: BB#59
10752B		%vreg155<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg155
10768B		%vreg154<def> = LDRWui <fi#13>, 0; mem:LD4[FixedStack13] GPR32:%vreg154
10784B		%WZR<def> = SUBSWrr %vreg155, %vreg154, %NZCV<imp-def>; GPR32:%vreg155,%vreg154
10800B		Bcc 1, <BB#63>, %NZCV<imp-use>
	    Successors according to CFG: BB#63 BB#62

10816B	BB#62: derived from LLVM BB %if.then.334
	    Predecessors according to CFG: BB#61
10832B		STRWui %WZR, <fi#5>, 0; mem:ST4[FixedStack5]
10848B		B <BB#76>
	    Successors according to CFG: BB#76

10864B	BB#63: derived from LLVM BB %if.end.335
	    Predecessors according to CFG: BB#61
10880B		%vreg192<def> = LDRWui <fi#7>, 0; mem:LD4[FixedStack7] GPR32:%vreg192
10912B		STRBBui %vreg192, <fi#4>, 0; mem:ST1[FixedStack4] GPR32:%vreg192
10928B		%vreg189:sub_32<def,read-undef> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR64:%vreg189
10960B		%vreg184<def> = LDRXui <fi#8>, 0; mem:LD8[FixedStack8] GPR64:%vreg184
10976B		%vreg181<def> = MOVi64imm 4; GPR64:%vreg181
10992B		%vreg182<def> = MADDXrrr %vreg189, %vreg181, %XZR; GPR64:%vreg182,%vreg189,%vreg181
11008B		%vreg183<def> = ADDXrr %vreg184, %vreg182; GPR64common:%vreg183 GPR64:%vreg184,%vreg182
11024B		%vreg178<def> = LDRWui %vreg183, 0; mem:LD4[%arrayidx338] GPR32:%vreg178 GPR64common:%vreg183
11040B		STRWui %vreg178, <fi#9>, 0; mem:ST4[FixedStack9] GPR32:%vreg178
11056B		%vreg175<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32:%vreg175
11072B		%vreg172<def> = ANDWri %vreg175, 7; GPR32common:%vreg172 GPR32:%vreg175
11104B		STRBBui %vreg172, <fi#2>, 0; mem:ST1[FixedStack2] GPR32common:%vreg172
11120B		%vreg169<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32:%vreg169
11136B		%vreg168<def> = UBFMWri %vreg169, 8, 31; GPR32:%vreg168,%vreg169
11152B		STRWui %vreg168, <fi#9>, 0; mem:ST4[FixedStack9] GPR32:%vreg168
11168B		%vreg165<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32common:%vreg165
11184B		%vreg164<def> = ADDWri %vreg165, 1, 0; GPR32common:%vreg164,%vreg165
11200B		STRWui %vreg164, <fi#6>, 0; mem:ST4[FixedStack6] GPR32common:%vreg164
11216B		%vreg161<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg161
11232B		%vreg158<def> = LDRWui <fi#7>, 0; mem:LD4[FixedStack7] GPR32:%vreg158
11248B		%WZR<def> = SUBSWrr %vreg161, %vreg158, %NZCV<imp-def>; GPR32:%vreg161,%vreg158
11264B		Bcc 0, <BB#65>, %NZCV<imp-use>
	    Successors according to CFG: BB#65 BB#64

11280B	BB#64: derived from LLVM BB %if.then.346
	    Predecessors according to CFG: BB#63
11296B		%vreg351<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg351
11312B		STRWui %vreg351, <fi#7>, 0; mem:ST4[FixedStack7] GPR32:%vreg351
11328B		B <BB#56>
	    Successors according to CFG: BB#56

11344B	BB#65: derived from LLVM BB %if.end.348
	    Predecessors according to CFG: BB#63
11360B		%vreg197<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg197
11376B		%vreg196<def> = LDRWui <fi#13>, 0; mem:LD4[FixedStack13] GPR32:%vreg196
11392B		%WZR<def> = SUBSWrr %vreg197, %vreg196, %NZCV<imp-def>; GPR32:%vreg197,%vreg196
11408B		Bcc 1, <BB#67>, %NZCV<imp-use>
	    Successors according to CFG: BB#67 BB#66

11424B	BB#66: derived from LLVM BB %if.then.351
	    Predecessors according to CFG: BB#65
11440B		B <BB#56>
	    Successors according to CFG: BB#56

11456B	BB#67: derived from LLVM BB %if.end.352
	    Predecessors according to CFG: BB#65
11472B		%vreg230<def> = MOVi32imm 2; GPR32:%vreg230
11488B		STRWui %vreg230, <fi#5>, 0; mem:ST4[FixedStack5] GPR32:%vreg230
11504B		%vreg229:sub_32<def,read-undef> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR64:%vreg229
11536B		%vreg224<def> = LDRXui <fi#8>, 0; mem:LD8[FixedStack8] GPR64:%vreg224
11552B		%vreg221<def> = MOVi64imm 4; GPR64:%vreg221
11568B		%vreg222<def> = MADDXrrr %vreg229, %vreg221, %XZR; GPR64:%vreg222,%vreg229,%vreg221
11584B		%vreg223<def> = ADDXrr %vreg224, %vreg222; GPR64common:%vreg223 GPR64:%vreg224,%vreg222
11600B		%vreg218<def> = LDRWui %vreg223, 0; mem:LD4[%arrayidx354] GPR32:%vreg218 GPR64common:%vreg223
11616B		STRWui %vreg218, <fi#9>, 0; mem:ST4[FixedStack9] GPR32:%vreg218
11632B		%vreg215<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32:%vreg215
11648B		%vreg212<def> = ANDWri %vreg215, 7; GPR32common:%vreg212 GPR32:%vreg215
11680B		STRBBui %vreg212, <fi#2>, 0; mem:ST1[FixedStack2] GPR32common:%vreg212
11696B		%vreg209<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32:%vreg209
11712B		%vreg208<def> = UBFMWri %vreg209, 8, 31; GPR32:%vreg208,%vreg209
11728B		STRWui %vreg208, <fi#9>, 0; mem:ST4[FixedStack9] GPR32:%vreg208
11744B		%vreg205<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32common:%vreg205
11760B		%vreg204<def> = ADDWri %vreg205, 1, 0; GPR32common:%vreg204,%vreg205
11776B		STRWui %vreg204, <fi#6>, 0; mem:ST4[FixedStack6] GPR32common:%vreg204
11792B		%vreg201<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg201
11808B		%vreg200<def> = LDRWui <fi#13>, 0; mem:LD4[FixedStack13] GPR32:%vreg200
11824B		%WZR<def> = SUBSWrr %vreg201, %vreg200, %NZCV<imp-def>; GPR32:%vreg201,%vreg200
11840B		Bcc 1, <BB#69>, %NZCV<imp-use>
	    Successors according to CFG: BB#69 BB#68

11856B	BB#68: derived from LLVM BB %if.then.361
	    Predecessors according to CFG: BB#67
11872B		B <BB#48>
	    Successors according to CFG: BB#48

11888B	BB#69: derived from LLVM BB %if.end.362
	    Predecessors according to CFG: BB#67
11904B		%vreg236<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg236
11920B		%vreg233<def> = LDRWui <fi#7>, 0; mem:LD4[FixedStack7] GPR32:%vreg233
11936B		%WZR<def> = SUBSWrr %vreg236, %vreg233, %NZCV<imp-def>; GPR32:%vreg236,%vreg233
11952B		Bcc 0, <BB#71>, %NZCV<imp-use>
	    Successors according to CFG: BB#71 BB#70

11968B	BB#70: derived from LLVM BB %if.then.366
	    Predecessors according to CFG: BB#69
11984B		%vreg347<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg347
12000B		STRWui %vreg347, <fi#7>, 0; mem:ST4[FixedStack7] GPR32:%vreg347
12016B		B <BB#48>
	    Successors according to CFG: BB#48

12032B	BB#71: derived from LLVM BB %if.end.368
	    Predecessors according to CFG: BB#69
12048B		%vreg269<def> = MOVi32imm 3; GPR32:%vreg269
12064B		STRWui %vreg269, <fi#5>, 0; mem:ST4[FixedStack5] GPR32:%vreg269
12080B		%vreg268:sub_32<def,read-undef> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR64:%vreg268
12112B		%vreg263<def> = LDRXui <fi#8>, 0; mem:LD8[FixedStack8] GPR64:%vreg263
12128B		%vreg260<def> = MOVi64imm 4; GPR64:%vreg260
12144B		%vreg261<def> = MADDXrrr %vreg268, %vreg260, %XZR; GPR64:%vreg261,%vreg268,%vreg260
12160B		%vreg262<def> = ADDXrr %vreg263, %vreg261; GPR64common:%vreg262 GPR64:%vreg263,%vreg261
12176B		%vreg257<def> = LDRWui %vreg262, 0; mem:LD4[%arrayidx370] GPR32:%vreg257 GPR64common:%vreg262
12192B		STRWui %vreg257, <fi#9>, 0; mem:ST4[FixedStack9] GPR32:%vreg257
12208B		%vreg254<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32:%vreg254
12224B		%vreg251<def> = ANDWri %vreg254, 7; GPR32common:%vreg251 GPR32:%vreg254
12256B		STRBBui %vreg251, <fi#2>, 0; mem:ST1[FixedStack2] GPR32common:%vreg251
12272B		%vreg248<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32:%vreg248
12288B		%vreg247<def> = UBFMWri %vreg248, 8, 31; GPR32:%vreg247,%vreg248
12304B		STRWui %vreg247, <fi#9>, 0; mem:ST4[FixedStack9] GPR32:%vreg247
12320B		%vreg244<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32common:%vreg244
12336B		%vreg243<def> = ADDWri %vreg244, 1, 0; GPR32common:%vreg243,%vreg244
12352B		STRWui %vreg243, <fi#6>, 0; mem:ST4[FixedStack6] GPR32common:%vreg243
12368B		%vreg240<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg240
12384B		%vreg239<def> = LDRWui <fi#13>, 0; mem:LD4[FixedStack13] GPR32:%vreg239
12400B		%WZR<def> = SUBSWrr %vreg240, %vreg239, %NZCV<imp-def>; GPR32:%vreg240,%vreg239
12416B		Bcc 1, <BB#73>, %NZCV<imp-use>
	    Successors according to CFG: BB#73 BB#72

12432B	BB#72: derived from LLVM BB %if.then.377
	    Predecessors according to CFG: BB#71
12448B		B <BB#48>
	    Successors according to CFG: BB#48

12464B	BB#73: derived from LLVM BB %if.end.378
	    Predecessors according to CFG: BB#71
12480B		%vreg275<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg275
12496B		%vreg272<def> = LDRWui <fi#7>, 0; mem:LD4[FixedStack7] GPR32:%vreg272
12512B		%WZR<def> = SUBSWrr %vreg275, %vreg272, %NZCV<imp-def>; GPR32:%vreg275,%vreg272
12528B		Bcc 0, <BB#75>, %NZCV<imp-use>
	    Successors according to CFG: BB#75 BB#74

12544B	BB#74: derived from LLVM BB %if.then.382
	    Predecessors according to CFG: BB#73
12560B		%vreg343<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg343
12576B		STRWui %vreg343, <fi#7>, 0; mem:ST4[FixedStack7] GPR32:%vreg343
12592B		B <BB#48>
	    Successors according to CFG: BB#48

12608B	BB#75: derived from LLVM BB %if.end.384
	    Predecessors according to CFG: BB#73
12624B		%vreg339:sub_32<def,read-undef> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR64:%vreg339
12656B		%vreg334<def> = LDRXui <fi#8>, 0; mem:LD8[FixedStack8] GPR64:%vreg334
12672B		%vreg331<def> = MOVi64imm 4; GPR64:%vreg331
12688B		%vreg332<def> = MADDXrrr %vreg339, %vreg331, %XZR; GPR64:%vreg332,%vreg339,%vreg331
12704B		%vreg333<def> = ADDXrr %vreg334, %vreg332; GPR64common:%vreg333 GPR64:%vreg334,%vreg332
12720B		%vreg328<def> = LDRWui %vreg333, 0; mem:LD4[%arrayidx386] GPR32:%vreg328 GPR64common:%vreg333
12736B		STRWui %vreg328, <fi#9>, 0; mem:ST4[FixedStack9] GPR32:%vreg328
12752B		%vreg325<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32:%vreg325
12768B		%vreg322<def> = ANDWri %vreg325, 7; GPR32common:%vreg322 GPR32:%vreg325
12800B		STRBBui %vreg322, <fi#2>, 0; mem:ST1[FixedStack2] GPR32common:%vreg322
12816B		%vreg319<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32:%vreg319
12832B		%vreg318<def> = UBFMWri %vreg319, 8, 31; GPR32:%vreg318,%vreg319
12848B		STRWui %vreg318, <fi#9>, 0; mem:ST4[FixedStack9] GPR32:%vreg318
12864B		%vreg315<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32common:%vreg315
12880B		%vreg314<def> = ADDWri %vreg315, 1, 0; GPR32common:%vreg314,%vreg315
12896B		STRWui %vreg314, <fi#6>, 0; mem:ST4[FixedStack6] GPR32common:%vreg314
12912B		%vreg311<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32common:%vreg311
12928B		%vreg308<def> = ADDWri %vreg311, 4, 0; GPR32common:%vreg308,%vreg311
12944B		STRWui %vreg308, <fi#5>, 0; mem:ST4[FixedStack5] GPR32common:%vreg308
12960B		%vreg305:sub_32<def,read-undef> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR64:%vreg305
12992B		%vreg300<def> = LDRXui <fi#8>, 0; mem:LD8[FixedStack8] GPR64:%vreg300
13008B		%vreg297<def> = MOVi64imm 4; GPR64:%vreg297
13024B		%vreg298<def> = MADDXrrr %vreg305, %vreg297, %XZR; GPR64:%vreg298,%vreg305,%vreg297
13040B		%vreg299<def> = ADDXrr %vreg300, %vreg298; GPR64common:%vreg299 GPR64:%vreg300,%vreg298
13056B		%vreg294<def> = LDRWui %vreg299, 0; mem:LD4[%arrayidx394] GPR32:%vreg294 GPR64common:%vreg299
13072B		STRWui %vreg294, <fi#9>, 0; mem:ST4[FixedStack9] GPR32:%vreg294
13088B		%vreg291<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32:%vreg291
13104B		%vreg288<def> = ANDWri %vreg291, 7; GPR32common:%vreg288 GPR32:%vreg291
13136B		%vreg286<def> = UBFMWri %vreg288, 0, 7; GPR32:%vreg286 GPR32common:%vreg288
13152B		STRWui %vreg286, <fi#7>, 0; mem:ST4[FixedStack7] GPR32:%vreg286
13168B		%vreg283<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32:%vreg283
13184B		%vreg282<def> = UBFMWri %vreg283, 8, 31; GPR32:%vreg282,%vreg283
13200B		STRWui %vreg282, <fi#9>, 0; mem:ST4[FixedStack9] GPR32:%vreg282
13216B		%vreg279<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32common:%vreg279
13232B		%vreg278<def> = ADDWri %vreg279, 1, 0; GPR32common:%vreg278,%vreg279
13248B		STRWui %vreg278, <fi#6>, 0; mem:ST4[FixedStack6] GPR32common:%vreg278
13264B		B <BB#48>
	    Successors according to CFG: BB#48

13280B	BB#76: derived from LLVM BB %return_notr
	    Predecessors according to CFG: BB#62 BB#57 BB#51
13296B		%vreg381<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg381
13312B		%vreg380<def> = LDRXui %vreg381, 0; mem:LD8[%strm400] GPR64common:%vreg380,%vreg381
13328B		%vreg378<def> = LDRWui %vreg380, 9; mem:LD4[%total_out_lo32401] GPR32:%vreg378 GPR64common:%vreg380
13344B		STRWui %vreg378, <fi#14>, 0; mem:ST4[FixedStack14] GPR32:%vreg378
13408B		%vreg370<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg370
13424B		%vreg369<def> = LDRXui %vreg370, 0; mem:LD8[%strm402] GPR64common:%vreg369,%vreg370
13428B		%vreg375<def> = LDRWui <fi#12>, 0; mem:LD4[FixedStack12] GPR32:%vreg375
13432B		%vreg374<def> = LDRWui <fi#11>, 0; mem:LD4[FixedStack11] GPR32:%vreg374
13440B		%vreg367<def> = LDRWui %vreg369, 9; mem:LD4[%total_out_lo32403] GPR32:%vreg367 GPR64common:%vreg369
13448B		%vreg373<def> = SUBWrr %vreg375, %vreg374; GPR32:%vreg373,%vreg375,%vreg374
13456B		%vreg366<def> = ADDWrr %vreg367, %vreg373; GPR32:%vreg366,%vreg367,%vreg373
13472B		STRWui %vreg366, %vreg369, 9; mem:ST4[%total_out_lo32403] GPR32:%vreg366 GPR64common:%vreg369
13488B		%vreg361<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg361
13504B		%vreg360<def> = LDRXui %vreg361, 0; mem:LD8[%strm405] GPR64common:%vreg360,%vreg361
13520B		%vreg358<def> = LDRWui %vreg360, 9; mem:LD4[%total_out_lo32406] GPR32:%vreg358 GPR64common:%vreg360
13536B		%vreg356<def> = LDRWui <fi#14>, 0; mem:LD4[FixedStack14] GPR32:%vreg356
13552B		%WZR<def> = SUBSWrr %vreg358, %vreg356, %NZCV<imp-def>; GPR32:%vreg358,%vreg356
13568B		Bcc 2, <BB#78>, %NZCV<imp-use>
	    Successors according to CFG: BB#78 BB#77

13584B	BB#77: derived from LLVM BB %if.then.409
	    Predecessors according to CFG: BB#76
13600B		%vreg389<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg389
13616B		%vreg388<def> = LDRXui %vreg389, 0; mem:LD8[%strm410] GPR64common:%vreg388,%vreg389
13632B		%vreg386<def> = LDRWui %vreg388, 10; mem:LD4[%total_out_hi32411] GPR32common:%vreg386 GPR64common:%vreg388
13648B		%vreg385<def> = ADDWri %vreg386, 1, 0; GPR32common:%vreg385,%vreg386
13664B		STRWui %vreg385, %vreg388, 10; mem:ST4[%total_out_hi32411] GPR32common:%vreg385 GPR64common:%vreg388
	    Successors according to CFG: BB#78

13680B	BB#78: derived from LLVM BB %if.end.413
	    Predecessors according to CFG: BB#76 BB#77
13696B		%vreg429<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg429
13712B		%vreg428<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg428
13728B		STRWui %vreg429, %vreg428, 796; mem:ST4[%calculatedBlockCRC414] GPR32:%vreg429 GPR64common:%vreg428
13744B		%vreg425<def> = LDRBBui <fi#4>, 0; mem:LD1[FixedStack4] GPR32:%vreg425
13760B		%vreg424<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg424
13776B		STRBBui %vreg425, %vreg424, 12; mem:ST1[%state_out_ch415] GPR32:%vreg425 GPR64common:%vreg424
13792B		%vreg421<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32:%vreg421
13808B		%vreg420<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg420
13824B		STRWui %vreg421, %vreg420, 4; mem:ST4[%state_out_len416] GPR32:%vreg421 GPR64common:%vreg420
13840B		%vreg417<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg417
13856B		%vreg416<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg416
13872B		STRWui %vreg417, %vreg416, 273; mem:ST4[%nblock_used417] GPR32:%vreg417 GPR64common:%vreg416
13888B		%vreg413<def> = LDRWui <fi#7>, 0; mem:LD4[FixedStack7] GPR32:%vreg413
13904B		%vreg412<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg412
13920B		STRWui %vreg413, %vreg412, 16; mem:ST4[%k0418] GPR32:%vreg413 GPR64common:%vreg412
13936B		%vreg409<def> = LDRXui <fi#8>, 0; mem:LD8[FixedStack8] GPR64:%vreg409
13952B		%vreg408<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg408
13968B		STRXui %vreg409, %vreg408, 394; mem:ST8[%tt419] GPR64:%vreg409 GPR64common:%vreg408
13984B		%vreg405<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32:%vreg405
14000B		%vreg404<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg404
14016B		STRWui %vreg405, %vreg404, 15; mem:ST4[%tPos420] GPR32:%vreg405 GPR64common:%vreg404
14048B		%vreg400<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg400
14056B		%vreg401<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg401
14064B		%vreg399<def> = LDRXui %vreg400, 0; mem:LD8[%strm421] GPR64common:%vreg399,%vreg400
14080B		STRXui %vreg401, %vreg399, 3; mem:ST8[%next_out422] GPR64:%vreg401 GPR64common:%vreg399
14112B		%vreg394<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg394
14120B		%vreg395<def> = LDRWui <fi#11>, 0; mem:LD4[FixedStack11] GPR32:%vreg395
14128B		%vreg393<def> = LDRXui %vreg394, 0; mem:LD8[%strm423] GPR64common:%vreg393,%vreg394
14144B		STRWui %vreg395, %vreg393, 8; mem:ST4[%avail_out424] GPR32:%vreg395 GPR64common:%vreg393
	    Successors according to CFG: BB#79

14160B	BB#79: derived from LLVM BB %if.end.425
	    Predecessors according to CFG: BB#78
14176B		STRBBui %WZR, <fi#0>, 0; mem:ST1[FixedStack0]
	    Successors according to CFG: BB#80

14192B	BB#80: derived from LLVM BB %return
	    Predecessors according to CFG: BB#60 BB#79 BB#13 BB#11 BB#4
14208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
14224B		%vreg1133<def> = MOVaddr <ga:@unRLE_obuf_to_output_FAST>[TF=1], <ga:@unRLE_obuf_to_output_FAST>[TF=34]; GPR64:%vreg1133
14240B		%X0<def> = COPY %vreg1133; GPR64:%vreg1133
14256B		%X1<def> = COPY %vreg10; GPR64:%vreg10
14272B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %SP<imp-def>
14288B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
14304B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
14320B		STACKMAP 1, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=1)
14336B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
14352B		%vreg1134<def> = LDRBBui <fi#0>, 0; mem:LD1[%retval] GPR32:%vreg1134
14384B		%W0<def> = COPY %vreg1134; GPR32:%vreg1134
14400B		RET_ReallyLR %W0<imp-use>

# End machine code for function unRLE_obuf_to_output_FAST.


selectOrSplit GPR64:%vreg10 [16r,14256r:0)  0@16r w=2.069672e-04
hints: %X1
missed hint %X1
Analyze counted 3 instrs in 2 blocks, through 79 blocks.
%X1	static = 1.0 worse than no bundles
%X8	static = 1.0 worse than no bundles
%X9	static = 1.0 worse than no bundles
%X10	static = 1.0 worse than no bundles
%X11	static = 1.0 worse than no bundles
%X12	static = 1.0 worse than no bundles
%X13	static = 1.0 worse than no bundles
%X14	static = 1.0 worse than no bundles
%X15	static = 1.0 worse than no bundles
%X16	static = 1.0 worse than no bundles
%X17	static = 1.0 worse than no bundles
%X18	static = 1.0 worse than no bundles
%X0	no positive bundles
%X2	static = 1.0 worse than no bundles
%X3	static = 1.0 worse than no bundles
%X4	static = 1.0 worse than no bundles
%X5	static = 1.0 worse than no bundles
%X6	static = 1.0 worse than no bundles
%X7	static = 1.0 worse than no bundles
assigning %vreg10 to %X19: W19 [16r,14256r:0)  0@16r

selectOrSplit GPR64:%vreg1 [32r,256r:0)  0@32r w=4.855769e-03
hints: %X0
missed hint %X0
Analyze counted 3 instrs in 1 blocks, through 0 blocks.
%X0	no positive bundles
%X8	no positive bundles
%X9	no positive bundles
%X10	no positive bundles
%X11	no positive bundles
%X12	no positive bundles
%X13	no positive bundles
%X14	no positive bundles
%X15	no positive bundles
%X16	no positive bundles
%X17	no positive bundles
%X18	no positive bundles
%X1	no positive bundles
%X2	no positive bundles
%X3	no positive bundles
%X4	no positive bundles
%X5	no positive bundles
%X6	no positive bundles
%X7	no positive bundles
%X19	no positive bundles
assigning %vreg1 to %X20: W20 [32r,256r:0)  0@32r

selectOrSplit GPR64sp:%vreg9 [80r,144r:0)  0@80r w=4.353448e-03
hints: %X0
assigning %vreg9 to %X0: W0 [80r,144r:0)  0@80r

selectOrSplit GPR64:%vreg1133 [14224r,14240r:0)  0@14224r w=inf
hints: %X0
assigning %vreg1133 to %X0: W0 [14224r,14240r:0)  0@14224r

selectOrSplit GPR32:%vreg1134 [14352r,14384r:0)  0@14352r w=inf
hints: %W0
assigning %vreg1134 to %W0: W0 [14352r,14384r:0)  0@14352r

selectOrSplit GPR64common:%vreg7 [64r,80r:0)  0@64r w=inf
assigning %vreg7 to %X8: W8 [64r,80r:0)  0@64r

selectOrSplit GPR64common:%vreg6 [272r,288r:0)  0@272r w=inf
assigning %vreg6 to %X8: W8 [272r,288r:0)  0@272r

selectOrSplit GPR32:%vreg5 [288r,304r:0)  0@288r w=inf
assigning %vreg5 to %W8: W8 [288r,304r:0)  0@288r

selectOrSplit GPR32:%vreg3 [304r,320r:0)  0@304r w=inf
assigning %vreg3 to %W8: W8 [304r,320r:0)  0@304r

selectOrSplit GPR64common:%vreg435 [416r,432r:0)  0@416r w=inf
assigning %vreg435 to %X8: W8 [416r,432r:0)  0@416r

selectOrSplit GPR64common:%vreg434 [432r,448r:0)  0@432r w=inf
assigning %vreg434 to %X8: W8 [432r,448r:0)  0@432r

selectOrSplit GPR32:%vreg432 [448r,464r:0)  0@448r w=inf
assigning %vreg432 to %W8: W8 [448r,464r:0)  0@448r

selectOrSplit GPR64common:%vreg439 [544r,560r:0)  0@544r w=inf
assigning %vreg439 to %X8: W8 [544r,560r:0)  0@544r

selectOrSplit GPR32:%vreg438 [560r,576r:0)  0@560r w=inf
assigning %vreg438 to %W8: W8 [560r,576r:0)  0@560r

selectOrSplit GPR64common:%vreg515 [704r,720r:0)  0@704r w=8.740386e-04
assigning %vreg515 to %X8: W8 [704r,720r:0)  0@704r

selectOrSplit GPR64common:%vreg518 [712r,728r:0)  0@712r w=8.740386e-04
assigning %vreg518 to %X9: W9 [712r,728r:0)  0@712r

selectOrSplit GPR64common:%vreg514 [720r,736r:0)  0@720r w=8.740386e-04
assigning %vreg514 to %X8: W8 [720r,736r:0)  0@720r

selectOrSplit GPR32:%vreg517 [728r,752r:0)  0@728r w=8.575473e-04
assigning %vreg517 to %W9: W9 [728r,752r:0)  0@728r

selectOrSplit GPR64common:%vreg512 [736r,752r:0)  0@736r w=inf
assigning %vreg512 to %X8: W8 [736r,752r:0)  0@736r

selectOrSplit GPR64common:%vreg505 [800r,872r:0)  0@800r w=7.703391e-04
assigning %vreg505 to %X8: W8 [800r,872r:0)  0@800r

selectOrSplit GPR64common:%vreg500 [848r,880r:0)  0@848r w=8.416668e-04
assigning %vreg500 to %X9: W9 [848r,880r:0)  0@848r

selectOrSplit GPR64common:%vreg484 [856r,888r:0)  0@856r w=4.208334e-04
assigning %vreg484 to %X10: W10 [856r,888r:0)  0@856r

selectOrSplit GPR64common:%vreg508 [864r,896r:0)  0@864r w=8.416668e-04
assigning %vreg508 to %X11: W11 [864r,896r:0)  0@864r

selectOrSplit GPR32:%vreg504 [872r,904r:0)  0@872r w=8.416668e-04
assigning %vreg504 to %W8: W8 [872r,904r:0)  0@872r

selectOrSplit GPR32:%vreg499 [880r,912r:0)  0@880r w=8.416668e-04
assigning %vreg499 to %W9: W9 [880r,912r:0)  0@880r

selectOrSplit GPR64common:%vreg485 [888r,960r:0)  0@888r w=7.703391e-04
assigning %vreg485 to %X10: W10 [888r,960r:0)  0@888r

selectOrSplit GPR32:%vreg507 [896r,1016r:0)  0@896r w=6.992309e-04
assigning %vreg507 to %W11: W11 [896r,1016r:0)  0@896r

selectOrSplit GPR32:%vreg502 [904r,912r:0)  0@904r w=inf
assigning %vreg502 to %W8: W8 [904r,912r:0)  0@904r

selectOrSplit GPR64:%vreg491 [912r,928r:0)  0@912r w=inf
assigning %vreg491 to %X8: W8 [912r,928r:0)  0@912r

selectOrSplit GPR64:%vreg492 [928r,944r:0)  0@928r w=8.740386e-04
assigning %vreg492 to %X8: W8 [928r,944r:0)  0@928r

selectOrSplit GPR64:%vreg487 [936r,944r:0)  0@936r w=inf
assigning %vreg487 to %X9: W9 [936r,944r:0)  0@936r

selectOrSplit GPR64:%vreg488 [944r,960r:0)  0@944r w=inf
assigning %vreg488 to %X8: W8 [944r,960r:0)  0@944r

selectOrSplit GPR64common:%vreg489 [960r,976r:0)  0@960r w=inf
assigning %vreg489 to %X8: W8 [960r,976r:0)  0@960r

selectOrSplit GPR32:%vreg483 [976r,1016r:0)  0@976r w=8.263637e-04
assigning %vreg483 to %W8: W8 [976r,1016r:0)  0@976r

selectOrSplit GPR64common:%vreg478 [1008r,1024r:0)  0@1008r w=8.740386e-04
assigning %vreg478 to %X9: W9 [1008r,1024r:0)  0@1008r

selectOrSplit GPR32:%vreg481 [1016r,1024r:0)  0@1016r w=inf
assigning %vreg481 to %W8: W8 [1016r,1024r:0)  0@1016r

selectOrSplit GPR64common:%vreg475 [1040r,1088r:0)  0@1040r w=1.217411e-03
assigning %vreg475 to %X8: W8 [1040r,1088r:0)  0@1040r

selectOrSplit GPR32common:%vreg474 [1056r,1072r:0)  0@1056r w=inf
assigning %vreg474 to %W9: W9 [1056r,1072r:0)  0@1056r

selectOrSplit GPR32common:%vreg473 [1072r,1088r:0)  0@1072r w=inf
assigning %vreg473 to %W9: W9 [1072r,1088r:0)  0@1072r

selectOrSplit GPR64common:%vreg469 [1104r,1120r:0)  0@1104r w=inf
assigning %vreg469 to %X8: W8 [1104r,1120r:0)  0@1104r

selectOrSplit GPR64common:%vreg468 [1120r,1168r:0)  0@1120r w=1.217411e-03
assigning %vreg468 to %X8: W8 [1120r,1168r:0)  0@1120r

selectOrSplit GPR64common:%vreg466 [1136r,1152r:0)  0@1136r w=inf
assigning %vreg466 to %X9: W9 [1136r,1152r:0)  0@1136r

selectOrSplit GPR64common:%vreg465 [1152r,1168r:0)  0@1152r w=inf
assigning %vreg465 to %X9: W9 [1152r,1168r:0)  0@1152r

selectOrSplit GPR64common:%vreg461 [1184r,1200r:0)  0@1184r w=inf
assigning %vreg461 to %X8: W8 [1184r,1200r:0)  0@1184r

selectOrSplit GPR64common:%vreg460 [1200r,1248r:0)  0@1200r w=1.217411e-03
assigning %vreg460 to %X8: W8 [1200r,1248r:0)  0@1200r

selectOrSplit GPR32common:%vreg458 [1216r,1232r:0)  0@1216r w=inf
assigning %vreg458 to %W9: W9 [1216r,1232r:0)  0@1216r

selectOrSplit GPR32common:%vreg457 [1232r,1248r:0)  0@1232r w=inf
assigning %vreg457 to %W9: W9 [1232r,1248r:0)  0@1232r

selectOrSplit GPR64common:%vreg453 [1264r,1280r:0)  0@1264r w=inf
assigning %vreg453 to %X8: W8 [1264r,1280r:0)  0@1264r

selectOrSplit GPR64common:%vreg452 [1280r,1328r:0)  0@1280r w=1.217411e-03
assigning %vreg452 to %X8: W8 [1280r,1328r:0)  0@1280r

selectOrSplit GPR32common:%vreg450 [1296r,1312r:0)  0@1296r w=inf
assigning %vreg450 to %W9: W9 [1296r,1312r:0)  0@1296r

selectOrSplit GPR32common:%vreg449 [1312r,1328r:0)  0@1312r w=inf
assigning %vreg449 to %W9: W9 [1312r,1328r:0)  0@1312r

selectOrSplit GPR64common:%vreg445 [1344r,1360r:0)  0@1344r w=inf
assigning %vreg445 to %X8: W8 [1344r,1360r:0)  0@1344r

selectOrSplit GPR64common:%vreg444 [1360r,1376r:0)  0@1360r w=inf
assigning %vreg444 to %X8: W8 [1360r,1376r:0)  0@1360r

selectOrSplit GPR32:%vreg442 [1376r,1392r:0)  0@1376r w=inf
assigning %vreg442 to %W8: W8 [1376r,1392r:0)  0@1376r

selectOrSplit GPR64common:%vreg526 [1424r,1440r:0)  0@1424r w=inf
assigning %vreg526 to %X8: W8 [1424r,1440r:0)  0@1424r

selectOrSplit GPR64common:%vreg525 [1440r,1488r:0)  0@1440r w=6.086311e-04
assigning %vreg525 to %X8: W8 [1440r,1488r:0)  0@1440r

selectOrSplit GPR32common:%vreg523 [1456r,1472r:0)  0@1456r w=inf
assigning %vreg523 to %W9: W9 [1456r,1472r:0)  0@1456r

selectOrSplit GPR32common:%vreg522 [1472r,1488r:0)  0@1472r w=inf
assigning %vreg522 to %W9: W9 [1472r,1488r:0)  0@1472r

selectOrSplit GPR64:%vreg535 [1584r,1616r:0)  0@1584r w=8.416668e-04
assigning %vreg535 to %X8: W8 [1584r,1616r:0)  0@1584r

selectOrSplit GPR64common:%vreg538 [1592r,1640r:0)  0@1592r w=8.116072e-04
assigning %vreg538 to %X9: W9 [1592r,1640r:0)  0@1592r

selectOrSplit GPR64:%vreg532 [1600r,1616r:0)  0@1600r w=inf
assigning %vreg532 to %X10: W10 [1600r,1616r:0)  0@1600r

selectOrSplit GPR64common:%vreg533 [1616r,1632r:0)  0@1616r w=inf
assigning %vreg533 to %X8: W8 [1616r,1632r:0)  0@1616r

selectOrSplit GPR32common:%vreg534 [1632r,1648r:0)  0@1632r w=8.740386e-04
assigning %vreg534 to %W8: W8 [1632r,1648r:0)  0@1632r

selectOrSplit GPR32:%vreg537 [1640r,1664r:0)  0@1640r w=8.575473e-04
assigning %vreg537 to %W9: W9 [1640r,1664r:0)  0@1640r

selectOrSplit GPR32common:%vreg530 [1648r,1664r:0)  0@1648r w=inf
assigning %vreg530 to %W8: W8 [1648r,1664r:0)  0@1648r

selectOrSplit GPR64:%vreg547 [1792r,1824r:0)  0@1792r w=4.207820e-04
assigning %vreg547 to %X8: W8 [1792r,1824r:0)  0@1792r

selectOrSplit GPR64common:%vreg550 [1800r,1848r:0)  0@1800r w=4.057541e-04
assigning %vreg550 to %X9: W9 [1800r,1848r:0)  0@1800r

selectOrSplit GPR64:%vreg544 [1808r,1824r:0)  0@1808r w=inf
assigning %vreg544 to %X10: W10 [1808r,1824r:0)  0@1808r

selectOrSplit GPR64common:%vreg545 [1824r,1840r:0)  0@1824r w=inf
assigning %vreg545 to %X8: W8 [1824r,1840r:0)  0@1824r

selectOrSplit GPR32common:%vreg546 [1840r,1856r:0)  0@1840r w=4.369659e-04
assigning %vreg546 to %W8: W8 [1840r,1856r:0)  0@1840r

selectOrSplit GPR32:%vreg549 [1848r,1872r:0)  0@1848r w=4.287213e-04
assigning %vreg549 to %W9: W9 [1848r,1872r:0)  0@1848r

selectOrSplit GPR32common:%vreg542 [1856r,1872r:0)  0@1856r w=inf
assigning %vreg542 to %W8: W8 [1856r,1872r:0)  0@1856r

selectOrSplit GPR32:%vreg1131 [1920r,1936r:0)  0@1920r w=inf
assigning %vreg1131 to %W8: W8 [1920r,1936r:0)  0@1920r

selectOrSplit GPR64common:%vreg599 [2000r,2016r:0)  0@2000r w=2.184296e-04
assigning %vreg599 to %X8: W8 [2000r,2016r:0)  0@2000r

selectOrSplit GPR32:%vreg597 [2008r,2016r:0)  0@2008r w=inf
assigning %vreg597 to %W9: W9 [2008r,2016r:0)  0@2008r

selectOrSplit GPR64common:%vreg596 [2032r,2088r:0)  0@2032r w=1.992691e-04
assigning %vreg596 to %X8: W8 [2032r,2088r:0)  0@2032r

selectOrSplit GPR64common:%vreg591 [2080r,2096r:0)  0@2080r w=2.184296e-04
assigning %vreg591 to %X9: W9 [2080r,2096r:0)  0@2080r

selectOrSplit GPR32:%vreg593 [2088r,2096r:0)  0@2088r w=inf
assigning %vreg593 to %W8: W8 [2088r,2096r:0)  0@2088r

selectOrSplit GPR64common:%vreg588 [2112r,2168r:0)  0@2112r w=1.992691e-04
assigning %vreg588 to %X8: W8 [2112r,2168r:0)  0@2112r

selectOrSplit GPR64common:%vreg581 [2160r,2176r:0)  0@2160r w=2.184296e-04
assigning %vreg581 to %X9: W9 [2160r,2176r:0)  0@2160r

selectOrSplit GPR64:%vreg587 [2168r,2208r:0)  0@2168r w=2.065153e-04
assigning %vreg587 to %X8: W8 [2168r,2208r:0)  0@2168r

selectOrSplit GPR64:%vreg580 [2176r,2224r:0)  0@2176r w=2.028275e-04
assigning %vreg580 to %X9: W9 [2176r,2224r:0)  0@2176r

selectOrSplit GPR64:%vreg576 [2192r,2208r:0)  0@2192r w=inf
assigning %vreg576 to %X10: W10 [2192r,2208r:0)  0@2192r

selectOrSplit GPR64:%vreg577 [2208r,2224r:0)  0@2208r w=inf
assigning %vreg577 to %X8: W8 [2208r,2224r:0)  0@2208r

selectOrSplit GPR64common:%vreg578 [2224r,2240r:0)  0@2224r w=inf
assigning %vreg578 to %X8: W8 [2224r,2240r:0)  0@2224r

selectOrSplit GPR32:%vreg573 [2240r,2272r:0)  0@2240r w=2.103396e-04
assigning %vreg573 to %W8: W8 [2240r,2272r:0)  0@2240r

selectOrSplit GPR64common:%vreg571 [2256r,2272r:0)  0@2256r w=inf
assigning %vreg571 to %X9: W9 [2256r,2272r:0)  0@2256r

selectOrSplit GPR64common:%vreg568 [2288r,2304r:0)  0@2288r w=inf
assigning %vreg568 to %X8: W8 [2288r,2304r:0)  0@2288r

selectOrSplit GPR32:%vreg567 [2304r,2320r:0)  0@2304r w=inf
assigning %vreg567 to %W8: W8 [2304r,2320r:0)  0@2304r

selectOrSplit GPR32common:%vreg563 [2320r,2352r:0)  0@2320r w=inf
assigning %vreg563 to %W8: W8 [2320r,2352r:0)  0@2320r

selectOrSplit GPR64common:%vreg560 [2368r,2416r:0)  0@2368r w=3.042412e-04
assigning %vreg560 to %X8: W8 [2368r,2416r:0)  0@2368r

selectOrSplit GPR32:%vreg559 [2384r,2400r:0)  0@2384r w=inf
assigning %vreg559 to %W9: W9 [2384r,2400r:0)  0@2384r

selectOrSplit GPR32:%vreg558 [2400r,2416r:0)  0@2400r w=inf
assigning %vreg558 to %W9: W9 [2400r,2416r:0)  0@2400r

selectOrSplit GPR64common:%vreg554 [2432r,2448r:0)  0@2432r w=inf
assigning %vreg554 to %X8: W8 [2432r,2448r:0)  0@2432r

selectOrSplit GPR32:%vreg553 [2448r,2464r:0)  0@2448r w=inf
assigning %vreg553 to %W8: W8 [2448r,2464r:0)  0@2448r

selectOrSplit GPR64common:%vreg626 [2528r,2544r:0)  0@2528r w=inf
assigning %vreg626 to %X8: W8 [2528r,2544r:0)  0@2528r

selectOrSplit GPR64:%vreg625 [2544r,2576r:0)  0@2544r w=1.051184e-04
assigning %vreg625 to %X8: W8 [2544r,2576r:0)  0@2544r

selectOrSplit GPR64common:%vreg615 [2552r,2568r:0)  0@2552r w=5.458072e-05
assigning %vreg615 to %X9: W9 [2552r,2568r:0)  0@2552r

selectOrSplit GPR64:%vreg618 [2560r,2576r:0)  0@2560r w=5.458072e-05
assigning %vreg618 to %X10: W10 [2560r,2576r:0)  0@2560r

selectOrSplit GPR64common:%vreg616 [2568r,2592r:0)  0@2568r w=1.071018e-04
assigning %vreg616 to %X9: W9 [2568r,2592r:0)  0@2568r

selectOrSplit GPR64:%vreg619 [2576r,2592r:0)  0@2576r w=inf
assigning %vreg619 to %X8: W8 [2576r,2592r:0)  0@2576r

selectOrSplit GPR64common:%vreg620 [2592r,2608r:0)  0@2592r w=inf
assigning %vreg620 to %X8: W8 [2592r,2608r:0)  0@2592r

selectOrSplit GPR32:%vreg614 [2608r,2640r:0)  0@2608r w=1.051184e-04
assigning %vreg614 to %W8: W8 [2608r,2640r:0)  0@2608r

selectOrSplit GPR64common:%vreg612 [2624r,2640r:0)  0@2624r w=inf
assigning %vreg612 to %X9: W9 [2624r,2640r:0)  0@2624r

selectOrSplit GPR64common:%vreg609 [2656r,2704r:0)  0@2656r w=1.520463e-04
assigning %vreg609 to %X8: W8 [2656r,2704r:0)  0@2656r

selectOrSplit GPR32common:%vreg608 [2672r,2688r:0)  0@2672r w=inf
assigning %vreg608 to %W9: W9 [2672r,2688r:0)  0@2672r

selectOrSplit GPR32common:%vreg607 [2688r,2704r:0)  0@2688r w=inf
assigning %vreg607 to %W9: W9 [2688r,2704r:0)  0@2688r

selectOrSplit GPR64common:%vreg603 [2720r,2736r:0)  0@2720r w=inf
assigning %vreg603 to %X8: W8 [2720r,2736r:0)  0@2720r

selectOrSplit GPR32common:%vreg602 [2736r,2752r:0)  0@2736r w=inf
assigning %vreg602 to %W8: W8 [2736r,2752r:0)  0@2736r

selectOrSplit GPR64common:%vreg628 [2800r,2816r:0)  0@2800r w=inf
assigning %vreg628 to %X8: W8 [2800r,2816r:0)  0@2800r

selectOrSplit GPR32:%vreg658 [2872r,3064r:0)  0@2872r w=1.534911e-04
assigning %vreg658 to %W8: W8 [2872r,3064r:0)  0@2872r

selectOrSplit GPR64common:%vreg668 [2912r,2960r:0)  0@2912r w=3.042412e-04
assigning %vreg668 to %X9: W9 [2912r,2960r:0)  0@2912r

selectOrSplit GPR32common:%vreg667 [2928r,2944r:0)  0@2928r w=inf
assigning %vreg667 to %W10: W10 [2928r,2944r:0)  0@2928r

selectOrSplit GPR32common:%vreg666 [2944r,2960r:0)  0@2944r w=inf
assigning %vreg666 to %W10: W10 [2944r,2960r:0)  0@2944r

selectOrSplit GPR64common:%vreg662 [2976r,2992r:0)  0@2976r w=inf
assigning %vreg662 to %X9: W9 [2976r,2992r:0)  0@2976r

selectOrSplit GPR32common:%vreg661 [2992r,3056r:0)  0@2992r w=1.958334e-04
assigning %vreg661 to %W9: W9 [2992r,3056r:0)  0@2992r

selectOrSplit GPR32:%vreg655 [3040r,3072r:0)  0@3040r w=2.103396e-04
assigning %vreg655 to %W10: W10 [3040r,3072r:0)  0@3040r

selectOrSplit GPR32:%vreg657 [3048r,3064r:0)  0@3048r w=1.092148e-04
assigning %vreg657 to %W11: W11 [3048r,3064r:0)  0@3048r

selectOrSplit GPR32:%vreg659 [3064r,3072r:0)  0@3064r w=inf
assigning %vreg659 to %W8: W8 [3064r,3072r:0)  0@3064r

selectOrSplit GPR32:%vreg649 [3072r,3088r:0)  0@3072r w=inf
assigning %vreg649 to %W8: W8 [3072r,3088r:0)  0@3072r

selectOrSplit GPR64common:%vreg646 [3104r,3152r:0)  0@3104r w=3.042412e-04
assigning %vreg646 to %X8: W8 [3104r,3152r:0)  0@3104r

selectOrSplit GPR32common:%vreg645 [3120r,3136r:0)  0@3120r w=inf
assigning %vreg645 to %W9: W9 [3120r,3136r:0)  0@3120r

selectOrSplit GPR32common:%vreg644 [3136r,3152r:0)  0@3136r w=inf
assigning %vreg644 to %W9: W9 [3136r,3152r:0)  0@3136r

selectOrSplit GPR64:%vreg637 [3200r,3232r:0)  0@3200r w=2.103396e-04
assigning %vreg637 to %X8: W8 [3200r,3232r:0)  0@3200r

selectOrSplit GPR64common:%vreg640 [3208r,3256r:0)  0@3208r w=2.028275e-04
assigning %vreg640 to %X9: W9 [3208r,3256r:0)  0@3208r

selectOrSplit GPR64:%vreg634 [3216r,3232r:0)  0@3216r w=inf
assigning %vreg634 to %X10: W10 [3216r,3232r:0)  0@3216r

selectOrSplit GPR64common:%vreg635 [3232r,3248r:0)  0@3232r w=inf
assigning %vreg635 to %X8: W8 [3232r,3248r:0)  0@3232r

selectOrSplit GPR32common:%vreg636 [3248r,3264r:0)  0@3248r w=2.184296e-04
assigning %vreg636 to %W8: W8 [3248r,3264r:0)  0@3248r

selectOrSplit GPR32:%vreg639 [3256r,3280r:0)  0@3256r w=2.143083e-04
assigning %vreg639 to %W9: W9 [3256r,3280r:0)  0@3256r

selectOrSplit GPR32common:%vreg632 [3264r,3280r:0)  0@3264r w=inf
assigning %vreg632 to %W8: W8 [3264r,3280r:0)  0@3264r

selectOrSplit GPR64common:%vreg673 [3376r,3392r:0)  0@3376r w=1.091614e-04
assigning %vreg673 to %X8: W8 [3376r,3392r:0)  0@3376r

selectOrSplit GPR32:%vreg676 [3384r,3408r:0)  0@3384r w=1.071018e-04
assigning %vreg676 to %W9: W9 [3384r,3408r:0)  0@3384r

selectOrSplit GPR32:%vreg672 [3392r,3408r:0)  0@3392r w=inf
assigning %vreg672 to %W8: W8 [3392r,3408r:0)  0@3392r

selectOrSplit GPR32:%vreg1130 [3456r,3488r:0)  0@3456r w=5.250784e-05
assigning %vreg1130 to %W8: W8 [3456r,3488r:0)  0@3456r

selectOrSplit GPR64common:%vreg1127 [3472r,3488r:0)  0@3472r w=inf
assigning %vreg1127 to %X9: W9 [3472r,3488r:0)  0@3472r

selectOrSplit GPR64common:%vreg717 [3552r,3568r:0)  0@3552r w=5.452737e-05
assigning %vreg717 to %X8: W8 [3552r,3568r:0)  0@3552r

selectOrSplit GPR32:%vreg715 [3560r,3568r:0)  0@3560r w=inf
assigning %vreg715 to %W9: W9 [3560r,3568r:0)  0@3560r

selectOrSplit GPR64common:%vreg714 [3584r,3640r:0)  0@3584r w=4.974427e-05
assigning %vreg714 to %X8: W8 [3584r,3640r:0)  0@3584r

selectOrSplit GPR64common:%vreg707 [3632r,3648r:0)  0@3632r w=5.452737e-05
assigning %vreg707 to %X9: W9 [3632r,3648r:0)  0@3632r

selectOrSplit GPR64:%vreg713 [3640r,3680r:0)  0@3640r w=5.155315e-05
assigning %vreg713 to %X8: W8 [3640r,3680r:0)  0@3640r

selectOrSplit GPR64:%vreg706 [3648r,3696r:0)  0@3648r w=5.063256e-05
assigning %vreg706 to %X9: W9 [3648r,3696r:0)  0@3648r

selectOrSplit GPR64:%vreg702 [3664r,3680r:0)  0@3664r w=inf
assigning %vreg702 to %X10: W10 [3664r,3680r:0)  0@3664r

selectOrSplit GPR64:%vreg703 [3680r,3696r:0)  0@3680r w=inf
assigning %vreg703 to %X8: W8 [3680r,3696r:0)  0@3680r

selectOrSplit GPR64common:%vreg704 [3696r,3712r:0)  0@3696r w=inf
assigning %vreg704 to %X8: W8 [3696r,3712r:0)  0@3696r

selectOrSplit GPR32:%vreg699 [3712r,3744r:0)  0@3712r w=5.250784e-05
assigning %vreg699 to %W8: W8 [3712r,3744r:0)  0@3712r

selectOrSplit GPR64common:%vreg697 [3728r,3744r:0)  0@3728r w=inf
assigning %vreg697 to %X9: W9 [3728r,3744r:0)  0@3728r

selectOrSplit GPR64common:%vreg694 [3760r,3776r:0)  0@3760r w=inf
assigning %vreg694 to %X8: W8 [3760r,3776r:0)  0@3760r

selectOrSplit GPR32:%vreg693 [3776r,3792r:0)  0@3776r w=inf
assigning %vreg693 to %W8: W8 [3776r,3792r:0)  0@3776r

selectOrSplit GPR32common:%vreg689 [3792r,3824r:0)  0@3792r w=inf
assigning %vreg689 to %W8: W8 [3792r,3824r:0)  0@3792r

selectOrSplit GPR64common:%vreg686 [3840r,3888r:0)  0@3840r w=7.594884e-05
assigning %vreg686 to %X8: W8 [3840r,3888r:0)  0@3840r

selectOrSplit GPR32:%vreg685 [3856r,3872r:0)  0@3856r w=inf
assigning %vreg685 to %W9: W9 [3856r,3872r:0)  0@3856r

selectOrSplit GPR32:%vreg684 [3872r,3888r:0)  0@3872r w=inf
assigning %vreg684 to %W9: W9 [3872r,3888r:0)  0@3872r

selectOrSplit GPR64common:%vreg680 [3904r,3920r:0)  0@3904r w=inf
assigning %vreg680 to %X8: W8 [3904r,3920r:0)  0@3904r

selectOrSplit GPR32:%vreg679 [3920r,3936r:0)  0@3920r w=inf
assigning %vreg679 to %W8: W8 [3920r,3936r:0)  0@3920r

selectOrSplit GPR64common:%vreg744 [4000r,4016r:0)  0@4000r w=inf
assigning %vreg744 to %X8: W8 [4000r,4016r:0)  0@4000r

selectOrSplit GPR64:%vreg743 [4016r,4048r:0)  0@4016r w=2.620254e-05
assigning %vreg743 to %X8: W8 [4016r,4048r:0)  0@4016r

selectOrSplit GPR64common:%vreg733 [4024r,4040r:0)  0@4024r w=1.360517e-05
assigning %vreg733 to %X9: W9 [4024r,4040r:0)  0@4024r

selectOrSplit GPR64:%vreg736 [4032r,4048r:0)  0@4032r w=1.360517e-05
assigning %vreg736 to %X10: W10 [4032r,4048r:0)  0@4032r

selectOrSplit GPR64common:%vreg734 [4040r,4064r:0)  0@4040r w=2.669693e-05
assigning %vreg734 to %X9: W9 [4040r,4064r:0)  0@4040r

selectOrSplit GPR64:%vreg737 [4048r,4064r:0)  0@4048r w=inf
assigning %vreg737 to %X8: W8 [4048r,4064r:0)  0@4048r

selectOrSplit GPR64common:%vreg738 [4064r,4080r:0)  0@4064r w=inf
assigning %vreg738 to %X8: W8 [4064r,4080r:0)  0@4064r

selectOrSplit GPR32:%vreg732 [4080r,4112r:0)  0@4080r w=2.620254e-05
assigning %vreg732 to %W8: W8 [4080r,4112r:0)  0@4080r

selectOrSplit GPR64common:%vreg730 [4096r,4112r:0)  0@4096r w=inf
assigning %vreg730 to %X9: W9 [4096r,4112r:0)  0@4096r

selectOrSplit GPR64common:%vreg727 [4128r,4176r:0)  0@4128r w=3.790011e-05
assigning %vreg727 to %X8: W8 [4128r,4176r:0)  0@4128r

selectOrSplit GPR32common:%vreg726 [4144r,4160r:0)  0@4144r w=inf
assigning %vreg726 to %W9: W9 [4144r,4160r:0)  0@4144r

selectOrSplit GPR32common:%vreg725 [4160r,4176r:0)  0@4160r w=inf
assigning %vreg725 to %W9: W9 [4160r,4176r:0)  0@4160r

selectOrSplit GPR64common:%vreg721 [4192r,4208r:0)  0@4192r w=inf
assigning %vreg721 to %X8: W8 [4192r,4208r:0)  0@4192r

selectOrSplit GPR32common:%vreg720 [4208r,4224r:0)  0@4208r w=inf
assigning %vreg720 to %W8: W8 [4208r,4224r:0)  0@4208r

selectOrSplit GPR64common:%vreg746 [4272r,4288r:0)  0@4272r w=inf
assigning %vreg746 to %X8: W8 [4272r,4288r:0)  0@4272r

selectOrSplit GPR32:%vreg776 [4344r,4536r:0)  0@4344r w=3.831653e-05
assigning %vreg776 to %W8: W8 [4344r,4536r:0)  0@4344r

selectOrSplit GPR64common:%vreg786 [4384r,4432r:0)  0@4384r w=7.594884e-05
assigning %vreg786 to %X9: W9 [4384r,4432r:0)  0@4384r

selectOrSplit GPR32common:%vreg785 [4400r,4416r:0)  0@4400r w=inf
assigning %vreg785 to %W10: W10 [4400r,4416r:0)  0@4400r

selectOrSplit GPR32common:%vreg784 [4416r,4432r:0)  0@4416r w=inf
assigning %vreg784 to %W10: W10 [4416r,4432r:0)  0@4416r

selectOrSplit GPR64common:%vreg780 [4448r,4464r:0)  0@4448r w=inf
assigning %vreg780 to %X9: W9 [4448r,4464r:0)  0@4448r

selectOrSplit GPR32common:%vreg779 [4464r,4528r:0)  0@4464r w=4.888661e-05
assigning %vreg779 to %W9: W9 [4464r,4528r:0)  0@4464r

selectOrSplit GPR32:%vreg773 [4512r,4544r:0)  0@4512r w=5.250784e-05
assigning %vreg773 to %W10: W10 [4512r,4544r:0)  0@4512r

selectOrSplit GPR32:%vreg775 [4520r,4536r:0)  0@4520r w=2.726368e-05
assigning %vreg775 to %W11: W11 [4520r,4536r:0)  0@4520r

selectOrSplit GPR32:%vreg777 [4536r,4544r:0)  0@4536r w=inf
assigning %vreg777 to %W8: W8 [4536r,4544r:0)  0@4536r

selectOrSplit GPR32:%vreg767 [4544r,4560r:0)  0@4544r w=inf
assigning %vreg767 to %W8: W8 [4544r,4560r:0)  0@4544r

selectOrSplit GPR64common:%vreg764 [4576r,4624r:0)  0@4576r w=7.594884e-05
assigning %vreg764 to %X8: W8 [4576r,4624r:0)  0@4576r

selectOrSplit GPR32common:%vreg763 [4592r,4608r:0)  0@4592r w=inf
assigning %vreg763 to %W9: W9 [4592r,4608r:0)  0@4592r

selectOrSplit GPR32common:%vreg762 [4608r,4624r:0)  0@4608r w=inf
assigning %vreg762 to %W9: W9 [4608r,4624r:0)  0@4608r

selectOrSplit GPR64:%vreg755 [4672r,4704r:0)  0@4672r w=5.250784e-05
assigning %vreg755 to %X8: W8 [4672r,4704r:0)  0@4672r

selectOrSplit GPR64common:%vreg758 [4680r,4728r:0)  0@4680r w=5.063256e-05
assigning %vreg758 to %X9: W9 [4680r,4728r:0)  0@4680r

selectOrSplit GPR64:%vreg752 [4688r,4704r:0)  0@4688r w=inf
assigning %vreg752 to %X10: W10 [4688r,4704r:0)  0@4688r

selectOrSplit GPR64common:%vreg753 [4704r,4720r:0)  0@4704r w=inf
assigning %vreg753 to %X8: W8 [4704r,4720r:0)  0@4704r

selectOrSplit GPR32common:%vreg754 [4720r,4736r:0)  0@4720r w=5.452737e-05
assigning %vreg754 to %W8: W8 [4720r,4736r:0)  0@4720r

selectOrSplit GPR32:%vreg757 [4728r,4752r:0)  0@4728r w=5.349855e-05
assigning %vreg757 to %W9: W9 [4728r,4752r:0)  0@4728r

selectOrSplit GPR32common:%vreg750 [4736r,4752r:0)  0@4736r w=inf
assigning %vreg750 to %W8: W8 [4736r,4752r:0)  0@4736r

selectOrSplit GPR64common:%vreg791 [4848r,4864r:0)  0@4848r w=2.721033e-05
assigning %vreg791 to %X8: W8 [4848r,4864r:0)  0@4848r

selectOrSplit GPR32:%vreg794 [4856r,4880r:0)  0@4856r w=2.669693e-05
assigning %vreg794 to %W9: W9 [4856r,4880r:0)  0@4856r

selectOrSplit GPR32:%vreg790 [4864r,4880r:0)  0@4864r w=inf
assigning %vreg790 to %W8: W8 [4864r,4880r:0)  0@4864r

selectOrSplit GPR32:%vreg1124 [4928r,4960r:0)  0@4928r w=1.304989e-05
assigning %vreg1124 to %W8: W8 [4928r,4960r:0)  0@4928r

selectOrSplit GPR64common:%vreg1121 [4944r,4960r:0)  0@4944r w=inf
assigning %vreg1121 to %X9: W9 [4944r,4960r:0)  0@4944r

selectOrSplit GPR64common:%vreg835 [5024r,5040r:0)  0@5024r w=1.355181e-05
assigning %vreg835 to %X8: W8 [5024r,5040r:0)  0@5024r

selectOrSplit GPR32:%vreg833 [5032r,5040r:0)  0@5032r w=inf
assigning %vreg833 to %W9: W9 [5032r,5040r:0)  0@5032r

selectOrSplit GPR64common:%vreg832 [5056r,5112r:0)  0@5056r w=1.236306e-05
assigning %vreg832 to %X8: W8 [5056r,5112r:0)  0@5056r

selectOrSplit GPR64common:%vreg825 [5104r,5120r:0)  0@5104r w=1.355181e-05
assigning %vreg825 to %X9: W9 [5104r,5120r:0)  0@5104r

selectOrSplit GPR64:%vreg831 [5112r,5152r:0)  0@5112r w=1.281262e-05
assigning %vreg831 to %X8: W8 [5112r,5152r:0)  0@5112r

selectOrSplit GPR64:%vreg824 [5120r,5168r:0)  0@5120r w=1.258383e-05
assigning %vreg824 to %X9: W9 [5120r,5168r:0)  0@5120r

selectOrSplit GPR64:%vreg820 [5136r,5152r:0)  0@5136r w=inf
assigning %vreg820 to %X10: W10 [5136r,5152r:0)  0@5136r

selectOrSplit GPR64:%vreg821 [5152r,5168r:0)  0@5152r w=inf
assigning %vreg821 to %X8: W8 [5152r,5168r:0)  0@5152r

selectOrSplit GPR64common:%vreg822 [5168r,5184r:0)  0@5168r w=inf
assigning %vreg822 to %X8: W8 [5168r,5184r:0)  0@5168r

selectOrSplit GPR32:%vreg817 [5184r,5216r:0)  0@5184r w=1.304989e-05
assigning %vreg817 to %W8: W8 [5184r,5216r:0)  0@5184r

selectOrSplit GPR64common:%vreg815 [5200r,5216r:0)  0@5200r w=inf
assigning %vreg815 to %X9: W9 [5200r,5216r:0)  0@5200r

selectOrSplit GPR64common:%vreg812 [5232r,5248r:0)  0@5232r w=inf
assigning %vreg812 to %X8: W8 [5232r,5248r:0)  0@5232r

selectOrSplit GPR32:%vreg811 [5248r,5264r:0)  0@5248r w=inf
assigning %vreg811 to %W8: W8 [5248r,5264r:0)  0@5248r

selectOrSplit GPR32common:%vreg807 [5264r,5296r:0)  0@5264r w=inf
assigning %vreg807 to %W8: W8 [5264r,5296r:0)  0@5264r

selectOrSplit GPR64common:%vreg804 [5312r,5360r:0)  0@5312r w=1.887574e-05
assigning %vreg804 to %X8: W8 [5312r,5360r:0)  0@5312r

selectOrSplit GPR32:%vreg803 [5328r,5344r:0)  0@5328r w=inf
assigning %vreg803 to %W9: W9 [5328r,5344r:0)  0@5328r

selectOrSplit GPR32:%vreg802 [5344r,5360r:0)  0@5344r w=inf
assigning %vreg802 to %W9: W9 [5344r,5360r:0)  0@5344r

selectOrSplit GPR64common:%vreg798 [5376r,5392r:0)  0@5376r w=inf
assigning %vreg798 to %X8: W8 [5376r,5392r:0)  0@5376r

selectOrSplit GPR32:%vreg797 [5392r,5408r:0)  0@5392r w=inf
assigning %vreg797 to %W8: W8 [5392r,5408r:0)  0@5392r

selectOrSplit GPR64common:%vreg862 [5472r,5488r:0)  0@5472r w=inf
assigning %vreg862 to %X8: W8 [5472r,5488r:0)  0@5472r

selectOrSplit GPR64:%vreg861 [5488r,5520r:0)  0@5488r w=6.473569e-06
assigning %vreg861 to %X8: W8 [5488r,5520r:0)  0@5488r

selectOrSplit GPR64common:%vreg851 [5496r,5512r:0)  0@5496r w=3.361276e-06
assigning %vreg851 to %X9: W9 [5496r,5512r:0)  0@5496r

selectOrSplit GPR64:%vreg854 [5504r,5520r:0)  0@5504r w=3.361276e-06
assigning %vreg854 to %X10: W10 [5504r,5520r:0)  0@5504r

selectOrSplit GPR64common:%vreg852 [5512r,5536r:0)  0@5512r w=6.595712e-06
assigning %vreg852 to %X9: W9 [5512r,5536r:0)  0@5512r

selectOrSplit GPR64:%vreg855 [5520r,5536r:0)  0@5520r w=inf
assigning %vreg855 to %X8: W8 [5520r,5536r:0)  0@5520r

selectOrSplit GPR64common:%vreg856 [5536r,5552r:0)  0@5536r w=inf
assigning %vreg856 to %X8: W8 [5536r,5552r:0)  0@5536r

selectOrSplit GPR32:%vreg850 [5552r,5584r:0)  0@5552r w=6.473569e-06
assigning %vreg850 to %W8: W8 [5552r,5584r:0)  0@5552r

selectOrSplit GPR64common:%vreg848 [5568r,5584r:0)  0@5568r w=inf
assigning %vreg848 to %X9: W9 [5568r,5584r:0)  0@5568r

selectOrSplit GPR64common:%vreg845 [5600r,5648r:0)  0@5600r w=9.363555e-06
assigning %vreg845 to %X8: W8 [5600r,5648r:0)  0@5600r

selectOrSplit GPR32common:%vreg844 [5616r,5632r:0)  0@5616r w=inf
assigning %vreg844 to %W9: W9 [5616r,5632r:0)  0@5616r

selectOrSplit GPR32common:%vreg843 [5632r,5648r:0)  0@5632r w=inf
assigning %vreg843 to %W9: W9 [5632r,5648r:0)  0@5632r

selectOrSplit GPR64common:%vreg839 [5664r,5680r:0)  0@5664r w=inf
assigning %vreg839 to %X8: W8 [5664r,5680r:0)  0@5664r

selectOrSplit GPR32common:%vreg838 [5680r,5696r:0)  0@5680r w=inf
assigning %vreg838 to %W8: W8 [5680r,5696r:0)  0@5680r

selectOrSplit GPR64common:%vreg864 [5744r,5760r:0)  0@5744r w=inf
assigning %vreg864 to %X8: W8 [5744r,5760r:0)  0@5744r

selectOrSplit GPR32:%vreg894 [5816r,6008r:0)  0@5816r w=9.522895e-06
assigning %vreg894 to %W8: W8 [5816r,6008r:0)  0@5816r

selectOrSplit GPR64common:%vreg904 [5856r,5904r:0)  0@5856r w=1.887574e-05
assigning %vreg904 to %X9: W9 [5856r,5904r:0)  0@5856r

selectOrSplit GPR32common:%vreg903 [5872r,5888r:0)  0@5872r w=inf
assigning %vreg903 to %W10: W10 [5872r,5888r:0)  0@5872r

selectOrSplit GPR32common:%vreg902 [5888r,5904r:0)  0@5888r w=inf
assigning %vreg902 to %W10: W10 [5888r,5904r:0)  0@5888r

selectOrSplit GPR64common:%vreg898 [5920r,5936r:0)  0@5920r w=inf
assigning %vreg898 to %X9: W9 [5920r,5936r:0)  0@5920r

selectOrSplit GPR32common:%vreg897 [5936r,6000r:0)  0@5936r w=1.214990e-05
assigning %vreg897 to %W9: W9 [5936r,6000r:0)  0@5936r

selectOrSplit GPR32:%vreg891 [5984r,6016r:0)  0@5984r w=1.304989e-05
assigning %vreg891 to %W10: W10 [5984r,6016r:0)  0@5984r

selectOrSplit GPR32:%vreg893 [5992r,6008r:0)  0@5992r w=6.775906e-06
assigning %vreg893 to %W11: W11 [5992r,6008r:0)  0@5992r

selectOrSplit GPR32:%vreg895 [6008r,6016r:0)  0@6008r w=inf
assigning %vreg895 to %W8: W8 [6008r,6016r:0)  0@6008r

selectOrSplit GPR32:%vreg885 [6016r,6032r:0)  0@6016r w=inf
assigning %vreg885 to %W8: W8 [6016r,6032r:0)  0@6016r

selectOrSplit GPR64common:%vreg882 [6048r,6096r:0)  0@6048r w=1.887574e-05
assigning %vreg882 to %X8: W8 [6048r,6096r:0)  0@6048r

selectOrSplit GPR32common:%vreg881 [6064r,6080r:0)  0@6064r w=inf
assigning %vreg881 to %W9: W9 [6064r,6080r:0)  0@6064r

selectOrSplit GPR32common:%vreg880 [6080r,6096r:0)  0@6080r w=inf
assigning %vreg880 to %W9: W9 [6080r,6096r:0)  0@6080r

selectOrSplit GPR64:%vreg873 [6144r,6176r:0)  0@6144r w=1.304989e-05
assigning %vreg873 to %X8: W8 [6144r,6176r:0)  0@6144r

selectOrSplit GPR64common:%vreg876 [6152r,6200r:0)  0@6152r w=1.258383e-05
assigning %vreg876 to %X9: W9 [6152r,6200r:0)  0@6152r

selectOrSplit GPR64:%vreg870 [6160r,6176r:0)  0@6160r w=inf
assigning %vreg870 to %X10: W10 [6160r,6176r:0)  0@6160r

selectOrSplit GPR64common:%vreg871 [6176r,6192r:0)  0@6176r w=inf
assigning %vreg871 to %X8: W8 [6176r,6192r:0)  0@6176r

selectOrSplit GPR32common:%vreg872 [6192r,6208r:0)  0@6192r w=1.355181e-05
assigning %vreg872 to %W8: W8 [6192r,6208r:0)  0@6192r

selectOrSplit GPR32:%vreg875 [6200r,6224r:0)  0@6200r w=1.329612e-05
assigning %vreg875 to %W9: W9 [6200r,6224r:0)  0@6200r

selectOrSplit GPR32common:%vreg868 [6208r,6224r:0)  0@6208r w=inf
assigning %vreg868 to %W8: W8 [6208r,6224r:0)  0@6208r

selectOrSplit GPR64common:%vreg909 [6320r,6336r:0)  0@6320r w=6.722553e-06
assigning %vreg909 to %X8: W8 [6320r,6336r:0)  0@6320r

selectOrSplit GPR32:%vreg912 [6328r,6352r:0)  0@6328r w=6.595712e-06
assigning %vreg912 to %W9: W9 [6328r,6352r:0)  0@6328r

selectOrSplit GPR32:%vreg908 [6336r,6352r:0)  0@6336r w=inf
assigning %vreg908 to %W8: W8 [6336r,6352r:0)  0@6336r

selectOrSplit GPR32:%vreg1118 [6400r,6432r:0)  0@6400r w=3.185407e-06
assigning %vreg1118 to %W8: W8 [6400r,6432r:0)  0@6400r

selectOrSplit GPR64common:%vreg1115 [6416r,6432r:0)  0@6416r w=inf
assigning %vreg1115 to %X9: W9 [6416r,6432r:0)  0@6416r

selectOrSplit GPR64common:%vreg950 [6480r,6536r:0)  0@6480r w=3.017754e-06
assigning %vreg950 to %X8: W8 [6480r,6536r:0)  0@6480r

selectOrSplit GPR64common:%vreg943 [6528r,6544r:0)  0@6528r w=3.307923e-06
assigning %vreg943 to %X9: W9 [6528r,6544r:0)  0@6528r

selectOrSplit GPR64:%vreg949 [6536r,6576r:0)  0@6536r w=3.127491e-06
assigning %vreg949 to %X8: W8 [6536r,6576r:0)  0@6536r

selectOrSplit GPR64:%vreg942 [6544r,6592r:0)  0@6544r w=3.071642e-06
assigning %vreg942 to %X9: W9 [6544r,6592r:0)  0@6544r

selectOrSplit GPR64:%vreg938 [6560r,6576r:0)  0@6560r w=inf
assigning %vreg938 to %X10: W10 [6560r,6576r:0)  0@6560r

selectOrSplit GPR64:%vreg939 [6576r,6592r:0)  0@6576r w=inf
assigning %vreg939 to %X8: W8 [6576r,6592r:0)  0@6576r

selectOrSplit GPR64common:%vreg940 [6592r,6608r:0)  0@6592r w=inf
assigning %vreg940 to %X8: W8 [6592r,6608r:0)  0@6592r

selectOrSplit GPR32:%vreg935 [6608r,6640r:0)  0@6608r w=3.185407e-06
assigning %vreg935 to %W8: W8 [6608r,6640r:0)  0@6608r

selectOrSplit GPR64common:%vreg933 [6624r,6640r:0)  0@6624r w=inf
assigning %vreg933 to %X9: W9 [6624r,6640r:0)  0@6624r

selectOrSplit GPR64common:%vreg930 [6656r,6672r:0)  0@6656r w=inf
assigning %vreg930 to %X8: W8 [6656r,6672r:0)  0@6656r

selectOrSplit GPR32:%vreg929 [6672r,6688r:0)  0@6672r w=inf
assigning %vreg929 to %W8: W8 [6672r,6688r:0)  0@6672r

selectOrSplit GPR32common:%vreg925 [6688r,6720r:0)  0@6688r w=inf
assigning %vreg925 to %W8: W8 [6688r,6720r:0)  0@6688r

selectOrSplit GPR64common:%vreg922 [6736r,6784r:0)  0@6736r w=4.607464e-06
assigning %vreg922 to %X8: W8 [6736r,6784r:0)  0@6736r

selectOrSplit GPR32:%vreg921 [6752r,6768r:0)  0@6752r w=inf
assigning %vreg921 to %W9: W9 [6752r,6768r:0)  0@6752r

selectOrSplit GPR32:%vreg920 [6768r,6784r:0)  0@6768r w=inf
assigning %vreg920 to %W9: W9 [6768r,6784r:0)  0@6768r

selectOrSplit GPR64common:%vreg916 [6800r,6816r:0)  0@6800r w=inf
assigning %vreg916 to %X8: W8 [6800r,6816r:0)  0@6800r

selectOrSplit GPR32:%vreg915 [6816r,6832r:0)  0@6816r w=inf
assigning %vreg915 to %W8: W8 [6816r,6832r:0)  0@6816r

selectOrSplit GPR64common:%vreg977 [6896r,6912r:0)  0@6896r w=inf
assigning %vreg977 to %X8: W8 [6896r,6912r:0)  0@6896r

selectOrSplit GPR64:%vreg976 [6912r,6944r:0)  0@6912r w=1.644081e-06
assigning %vreg976 to %X8: W8 [6912r,6944r:0)  0@6912r

selectOrSplit GPR64common:%vreg966 [6920r,6936r:0)  0@6920r w=8.536575e-07
assigning %vreg966 to %X9: W9 [6920r,6936r:0)  0@6920r

selectOrSplit GPR64:%vreg969 [6928r,6944r:0)  0@6928r w=8.536575e-07
assigning %vreg969 to %X10: W10 [6928r,6944r:0)  0@6928r

selectOrSplit GPR64common:%vreg967 [6936r,6960r:0)  0@6936r w=1.675101e-06
assigning %vreg967 to %X9: W9 [6936r,6960r:0)  0@6936r

selectOrSplit GPR64:%vreg970 [6944r,6960r:0)  0@6944r w=inf
assigning %vreg970 to %X8: W8 [6944r,6960r:0)  0@6944r

selectOrSplit GPR64common:%vreg971 [6960r,6976r:0)  0@6960r w=inf
assigning %vreg971 to %X8: W8 [6960r,6976r:0)  0@6960r

selectOrSplit GPR32:%vreg965 [6976r,7008r:0)  0@6976r w=1.644081e-06
assigning %vreg965 to %W8: W8 [6976r,7008r:0)  0@6976r

selectOrSplit GPR64common:%vreg963 [6992r,7008r:0)  0@6992r w=inf
assigning %vreg963 to %X9: W9 [6992r,7008r:0)  0@6992r

selectOrSplit GPR64common:%vreg960 [7024r,7072r:0)  0@7024r w=2.378046e-06
assigning %vreg960 to %X8: W8 [7024r,7072r:0)  0@7024r

selectOrSplit GPR32common:%vreg959 [7040r,7056r:0)  0@7040r w=inf
assigning %vreg959 to %W9: W9 [7040r,7056r:0)  0@7040r

selectOrSplit GPR32common:%vreg958 [7056r,7072r:0)  0@7056r w=inf
assigning %vreg958 to %W9: W9 [7056r,7072r:0)  0@7056r

selectOrSplit GPR64common:%vreg954 [7088r,7104r:0)  0@7088r w=inf
assigning %vreg954 to %X8: W8 [7088r,7104r:0)  0@7088r

selectOrSplit GPR32common:%vreg953 [7104r,7120r:0)  0@7104r w=inf
assigning %vreg953 to %W8: W8 [7104r,7120r:0)  0@7104r

selectOrSplit GPR64common:%vreg979 [7168r,7184r:0)  0@7168r w=inf
assigning %vreg979 to %X8: W8 [7168r,7184r:0)  0@7168r

selectOrSplit GPR32:%vreg1047 [7240r,7432r:0)  0@7240r w=2.324486e-06
assigning %vreg1047 to %W8: W8 [7240r,7432r:0)  0@7240r

selectOrSplit GPR64common:%vreg1057 [7280r,7328r:0)  0@7280r w=4.607464e-06
assigning %vreg1057 to %X9: W9 [7280r,7328r:0)  0@7280r

selectOrSplit GPR32common:%vreg1056 [7296r,7312r:0)  0@7296r w=inf
assigning %vreg1056 to %W10: W10 [7296r,7312r:0)  0@7296r

selectOrSplit GPR32common:%vreg1055 [7312r,7328r:0)  0@7312r w=inf
assigning %vreg1055 to %W10: W10 [7312r,7328r:0)  0@7312r

selectOrSplit GPR64common:%vreg1051 [7344r,7360r:0)  0@7344r w=inf
assigning %vreg1051 to %X9: W9 [7344r,7360r:0)  0@7344r

selectOrSplit GPR32common:%vreg1050 [7360r,7424r:0)  0@7360r w=2.965724e-06
assigning %vreg1050 to %W9: W9 [7360r,7424r:0)  0@7360r

selectOrSplit GPR32:%vreg1044 [7408r,7440r:0)  0@7408r w=3.185407e-06
assigning %vreg1044 to %W10: W10 [7408r,7440r:0)  0@7408r

selectOrSplit GPR32:%vreg1046 [7416r,7432r:0)  0@7416r w=1.653961e-06
assigning %vreg1046 to %W11: W11 [7416r,7432r:0)  0@7416r

selectOrSplit GPR32:%vreg1048 [7432r,7440r:0)  0@7432r w=inf
assigning %vreg1048 to %W8: W8 [7432r,7440r:0)  0@7432r

selectOrSplit GPR32:%vreg1038 [7440r,7456r:0)  0@7440r w=inf
assigning %vreg1038 to %W8: W8 [7440r,7456r:0)  0@7440r

selectOrSplit GPR64common:%vreg1035 [7472r,7520r:0)  0@7472r w=4.607464e-06
assigning %vreg1035 to %X8: W8 [7472r,7520r:0)  0@7472r

selectOrSplit GPR32common:%vreg1034 [7488r,7504r:0)  0@7488r w=inf
assigning %vreg1034 to %W9: W9 [7488r,7504r:0)  0@7488r

selectOrSplit GPR32common:%vreg1033 [7504r,7520r:0)  0@7504r w=inf
assigning %vreg1033 to %W9: W9 [7504r,7520r:0)  0@7504r

selectOrSplit GPR32common:%vreg1029 [7536r,7576r:0)  0@7536r w=3.127491e-06
assigning %vreg1029 to %W8: W8 [7536r,7576r:0)  0@7536r

selectOrSplit GPR64common:%vreg1024 [7568r,7584r:0)  0@7568r w=3.307923e-06
assigning %vreg1024 to %X9: W9 [7568r,7584r:0)  0@7568r

selectOrSplit GPR32common:%vreg1026 [7576r,7584r:0)  0@7576r w=inf
assigning %vreg1026 to %W8: W8 [7576r,7584r:0)  0@7576r

selectOrSplit GPR64common:%vreg1021 [7600r,7656r:0)  0@7600r w=3.017754e-06
assigning %vreg1021 to %X8: W8 [7600r,7656r:0)  0@7600r

selectOrSplit GPR64common:%vreg1014 [7648r,7664r:0)  0@7648r w=3.307923e-06
assigning %vreg1014 to %X9: W9 [7648r,7664r:0)  0@7648r

selectOrSplit GPR64:%vreg1020 [7656r,7696r:0)  0@7656r w=3.127491e-06
assigning %vreg1020 to %X8: W8 [7656r,7696r:0)  0@7656r

selectOrSplit GPR64:%vreg1013 [7664r,7712r:0)  0@7664r w=3.071642e-06
assigning %vreg1013 to %X9: W9 [7664r,7712r:0)  0@7664r

selectOrSplit GPR64:%vreg1009 [7680r,7696r:0)  0@7680r w=inf
assigning %vreg1009 to %X10: W10 [7680r,7696r:0)  0@7680r

selectOrSplit GPR64:%vreg1010 [7696r,7712r:0)  0@7696r w=inf
assigning %vreg1010 to %X8: W8 [7696r,7712r:0)  0@7696r

selectOrSplit GPR64common:%vreg1011 [7712r,7728r:0)  0@7712r w=inf
assigning %vreg1011 to %X8: W8 [7712r,7728r:0)  0@7712r

selectOrSplit GPR32:%vreg1006 [7728r,7760r:0)  0@7728r w=3.185407e-06
assigning %vreg1006 to %W8: W8 [7728r,7760r:0)  0@7728r

selectOrSplit GPR64common:%vreg1004 [7744r,7760r:0)  0@7744r w=inf
assigning %vreg1004 to %X9: W9 [7744r,7760r:0)  0@7744r

selectOrSplit GPR64common:%vreg1001 [7776r,7792r:0)  0@7776r w=inf
assigning %vreg1001 to %X8: W8 [7776r,7792r:0)  0@7776r

selectOrSplit GPR32:%vreg1000 [7792r,7860r:0)  0@7792r w=2.940376e-06
assigning %vreg1000 to %W8: W8 [7792r,7860r:0)  0@7792r

selectOrSplit GPR64common:%vreg992 [7856r,7872r:0)  0@7856r w=3.307923e-06
assigning %vreg992 to %X9: W9 [7856r,7872r:0)  0@7856r

selectOrSplit GPR32common:%vreg996 [7860r,7864r:0)  0@7860r w=inf
assigning %vreg996 to %W8: W8 [7860r,7864r:0)  0@7860r

selectOrSplit GPR32:%vreg994 [7864r,7872r:0)  0@7864r w=inf
assigning %vreg994 to %W8: W8 [7864r,7872r:0)  0@7864r

selectOrSplit GPR64common:%vreg989 [7888r,7936r:0)  0@7888r w=4.607464e-06
assigning %vreg989 to %X8: W8 [7888r,7936r:0)  0@7888r

selectOrSplit GPR32:%vreg988 [7904r,7920r:0)  0@7904r w=inf
assigning %vreg988 to %W9: W9 [7904r,7920r:0)  0@7904r

selectOrSplit GPR32:%vreg987 [7920r,7936r:0)  0@7920r w=inf
assigning %vreg987 to %W9: W9 [7920r,7936r:0)  0@7920r

selectOrSplit GPR64common:%vreg983 [7952r,7968r:0)  0@7952r w=inf
assigning %vreg983 to %X8: W8 [7952r,7968r:0)  0@7952r

selectOrSplit GPR32:%vreg982 [7968r,7984r:0)  0@7968r w=inf
assigning %vreg982 to %W8: W8 [7968r,7984r:0)  0@7968r

selectOrSplit GPR64common:%vreg1084 [8048r,8064r:0)  0@8048r w=inf
assigning %vreg1084 to %X8: W8 [8048r,8064r:0)  0@8048r

selectOrSplit GPR64:%vreg1083 [8064r,8096r:0)  0@8064r w=1.644081e-06
assigning %vreg1083 to %X8: W8 [8064r,8096r:0)  0@8064r

selectOrSplit GPR64common:%vreg1073 [8072r,8088r:0)  0@8072r w=8.536575e-07
assigning %vreg1073 to %X9: W9 [8072r,8088r:0)  0@8072r

selectOrSplit GPR64:%vreg1076 [8080r,8096r:0)  0@8080r w=8.536575e-07
assigning %vreg1076 to %X10: W10 [8080r,8096r:0)  0@8080r

selectOrSplit GPR64common:%vreg1074 [8088r,8112r:0)  0@8088r w=1.675101e-06
assigning %vreg1074 to %X9: W9 [8088r,8112r:0)  0@8088r

selectOrSplit GPR64:%vreg1077 [8096r,8112r:0)  0@8096r w=inf
assigning %vreg1077 to %X8: W8 [8096r,8112r:0)  0@8096r

selectOrSplit GPR64common:%vreg1078 [8112r,8128r:0)  0@8112r w=inf
assigning %vreg1078 to %X8: W8 [8112r,8128r:0)  0@8112r

selectOrSplit GPR32:%vreg1072 [8128r,8160r:0)  0@8128r w=1.644081e-06
assigning %vreg1072 to %W8: W8 [8128r,8160r:0)  0@8128r

selectOrSplit GPR64common:%vreg1070 [8144r,8160r:0)  0@8144r w=inf
assigning %vreg1070 to %X9: W9 [8144r,8160r:0)  0@8144r

selectOrSplit GPR64common:%vreg1067 [8176r,8224r:0)  0@8176r w=2.378046e-06
assigning %vreg1067 to %X8: W8 [8176r,8224r:0)  0@8176r

selectOrSplit GPR32common:%vreg1066 [8192r,8208r:0)  0@8192r w=inf
assigning %vreg1066 to %W9: W9 [8192r,8208r:0)  0@8192r

selectOrSplit GPR32common:%vreg1065 [8208r,8224r:0)  0@8208r w=inf
assigning %vreg1065 to %W9: W9 [8208r,8224r:0)  0@8208r

selectOrSplit GPR64common:%vreg1061 [8240r,8256r:0)  0@8240r w=inf
assigning %vreg1061 to %X8: W8 [8240r,8256r:0)  0@8240r

selectOrSplit GPR32common:%vreg1060 [8256r,8272r:0)  0@8256r w=inf
assigning %vreg1060 to %W8: W8 [8256r,8272r:0)  0@8256r

selectOrSplit GPR64common:%vreg1086 [8320r,8336r:0)  0@8320r w=inf
assigning %vreg1086 to %X8: W8 [8320r,8336r:0)  0@8320r

selectOrSplit GPR32:%vreg1102 [8392r,8600r:0)  0@8392r w=2.263316e-06
assigning %vreg1102 to %W8: W8 [8392r,8600r:0)  0@8392r

selectOrSplit GPR64common:%vreg1112 [8432r,8480r:0)  0@8432r w=4.607464e-06
assigning %vreg1112 to %X9: W9 [8432r,8480r:0)  0@8432r

selectOrSplit GPR32common:%vreg1111 [8448r,8464r:0)  0@8448r w=inf
assigning %vreg1111 to %W10: W10 [8448r,8464r:0)  0@8448r

selectOrSplit GPR32common:%vreg1110 [8464r,8480r:0)  0@8464r w=inf
assigning %vreg1110 to %W10: W10 [8464r,8480r:0)  0@8464r

selectOrSplit GPR64common:%vreg1106 [8496r,8568r:0)  0@8496r w=2.915457e-06
assigning %vreg1106 to %X9: W9 [8496r,8568r:0)  0@8496r

selectOrSplit GPR64common:%vreg1099 [8560r,8616r:0)  0@8560r w=4.526631e-06
assigning %vreg1099 to %X10: W10 [8560r,8616r:0)  0@8560r

selectOrSplit GPR32common:%vreg1105 [8568r,8584r:0)  0@8568r w=3.307923e-06
assigning %vreg1105 to %W9: W9 [8568r,8584r:0)  0@8568r

selectOrSplit GPR32:%vreg1098 [8576r,8608r:0)  0@8576r w=3.185407e-06
assigning %vreg1098 to %W11: W11 [8576r,8608r:0)  0@8576r

selectOrSplit GPR32:%vreg1101 [8592r,8600r:0)  0@8592r w=inf
assigning %vreg1101 to %W9: W9 [8592r,8600r:0)  0@8592r

selectOrSplit GPR32:%vreg1103 [8600r,8608r:0)  0@8600r w=inf
assigning %vreg1103 to %W8: W8 [8600r,8608r:0)  0@8600r

selectOrSplit GPR32:%vreg1097 [8608r,8616r:0)  0@8608r w=inf
assigning %vreg1097 to %W8: W8 [8608r,8616r:0)  0@8608r

selectOrSplit GPR64common:%vreg1092 [8624r,8672r:0)  0@8624r w=4.607464e-06
assigning %vreg1092 to %X8: W8 [8624r,8672r:0)  0@8624r

selectOrSplit GPR32common:%vreg1091 [8640r,8656r:0)  0@8640r w=inf
assigning %vreg1091 to %W9: W9 [8640r,8656r:0)  0@8640r

selectOrSplit GPR32common:%vreg1090 [8656r,8672r:0)  0@8656r w=inf
assigning %vreg1090 to %W9: W9 [8656r,8672r:0)  0@8656r

selectOrSplit GPR64common:%vreg61 [8720r,8736r:0)  0@8720r w=inf
assigning %vreg61 to %X8: W8 [8720r,8736r:0)  0@8720r

selectOrSplit GPR32:%vreg60 [8736r,8752r:0)  0@8736r w=inf
assigning %vreg60 to %W8: W8 [8736r,8752r:0)  0@8736r

selectOrSplit GPR64common:%vreg57 [8768r,8784r:0)  0@8768r w=inf
assigning %vreg57 to %X8: W8 [8768r,8784r:0)  0@8768r

selectOrSplit GPR32:%vreg56 [8784r,8800r:0)  0@8784r w=inf
assigning %vreg56 to %W8: W8 [8784r,8800r:0)  0@8784r

selectOrSplit GPR64common:%vreg53 [8816r,8832r:0)  0@8816r w=inf
assigning %vreg53 to %X8: W8 [8816r,8832r:0)  0@8816r

selectOrSplit GPR32:%vreg52 [8832r,8848r:0)  0@8832r w=inf
assigning %vreg52 to %W8: W8 [8832r,8848r:0)  0@8832r

selectOrSplit GPR64common:%vreg49 [8864r,8880r:0)  0@8864r w=inf
assigning %vreg49 to %X8: W8 [8864r,8880r:0)  0@8864r

selectOrSplit GPR32:%vreg48 [8880r,8896r:0)  0@8880r w=inf
assigning %vreg48 to %W8: W8 [8880r,8896r:0)  0@8880r

selectOrSplit GPR64common:%vreg45 [8912r,8928r:0)  0@8912r w=inf
assigning %vreg45 to %X8: W8 [8912r,8928r:0)  0@8912r

selectOrSplit GPR32:%vreg44 [8928r,8944r:0)  0@8928r w=inf
assigning %vreg44 to %W8: W8 [8928r,8944r:0)  0@8928r

selectOrSplit GPR64common:%vreg41 [8960r,8976r:0)  0@8960r w=inf
assigning %vreg41 to %X8: W8 [8960r,8976r:0)  0@8960r

selectOrSplit GPR64:%vreg40 [8976r,8992r:0)  0@8976r w=inf
assigning %vreg40 to %X8: W8 [8976r,8992r:0)  0@8976r

selectOrSplit GPR64common:%vreg37 [9008r,9024r:0)  0@9008r w=inf
assigning %vreg37 to %X8: W8 [9008r,9024r:0)  0@9008r

selectOrSplit GPR32:%vreg36 [9024r,9040r:0)  0@9024r w=inf
assigning %vreg36 to %W8: W8 [9024r,9040r:0)  0@9024r

selectOrSplit GPR64common:%vreg33 [9056r,9072r:0)  0@9056r w=inf
assigning %vreg33 to %X8: W8 [9056r,9072r:0)  0@9056r

selectOrSplit GPR64common:%vreg32 [9072r,9088r:0)  0@9072r w=inf
assigning %vreg32 to %X8: W8 [9072r,9088r:0)  0@9072r

selectOrSplit GPR64:%vreg30 [9088r,9104r:0)  0@9088r w=inf
assigning %vreg30 to %X8: W8 [9088r,9104r:0)  0@9088r

selectOrSplit GPR64common:%vreg27 [9120r,9136r:0)  0@9120r w=inf
assigning %vreg27 to %X8: W8 [9120r,9136r:0)  0@9120r

selectOrSplit GPR64common:%vreg26 [9136r,9152r:0)  0@9136r w=inf
assigning %vreg26 to %X8: W8 [9136r,9152r:0)  0@9136r

selectOrSplit GPR32:%vreg24 [9152r,9168r:0)  0@9152r w=inf
assigning %vreg24 to %W8: W8 [9152r,9168r:0)  0@9152r

selectOrSplit GPR32:%vreg21 [9184r,9200r:0)  0@9184r w=inf
assigning %vreg21 to %W8: W8 [9184r,9200r:0)  0@9184r

selectOrSplit GPR64:%vreg19 [9216r,9248r:0)  0@9216r w=2.314763e-03
assigning %vreg19 to %X8: W8 [9216r,9248r:0)  0@9216r

selectOrSplit GPR64:%vreg16 [9232r,9248r:0)  0@9232r w=inf
assigning %vreg16 to %X9: W9 [9232r,9248r:0)  0@9232r

selectOrSplit GPR64common:%vreg17 [9248r,9264r:0)  0@9248r w=inf
assigning %vreg17 to %X8: W8 [9248r,9264r:0)  0@9248r

selectOrSplit GPR32common:%vreg18 [9264r,9280r:0)  0@9264r w=inf
assigning %vreg18 to %W8: W8 [9264r,9280r:0)  0@9264r

selectOrSplit GPR32common:%vreg14 [9280r,9296r:0)  0@9280r w=inf
assigning %vreg14 to %W8: W8 [9280r,9296r:0)  0@9280r

selectOrSplit GPR32common:%vreg63 [9328r,9344r:0)  0@9328r w=inf
assigning %vreg63 to %W8: W8 [9328r,9344r:0)  0@9328r

selectOrSplit GPR32:%vreg65 [9424r,9440r:0)  0@9424r w=inf
assigning %vreg65 to %W8: W8 [9424r,9440r:0)  0@9424r

selectOrSplit GPR32common:%vreg67 [9504r,9520r:0)  0@9504r w=inf
assigning %vreg67 to %W8: W8 [9504r,9520r:0)  0@9504r

selectOrSplit GPR32:%vreg108 [9632r,9664r:0)  0@9632r w=3.983814e-04
assigning %vreg108 to %W8: W8 [9632r,9664r:0)  0@9632r

selectOrSplit GPR64common:%vreg107 [9648r,9664r:0)  0@9648r w=4.137037e-04
assigning %vreg107 to %X9: W9 [9648r,9664r:0)  0@9648r

selectOrSplit GPR64common:%vreg86 [9656r,9736r:0)  0@9656r w=1.792716e-04
assigning %vreg86 to %X10: W10 [9656r,9736r:0)  0@9656r

selectOrSplit GPR32:%vreg103 [9696r,9752r:0)  0@9696r w=3.774139e-04
assigning %vreg103 to %W8: W8 [9696r,9752r:0)  0@9696r

selectOrSplit GPR32:%vreg100 [9728r,9760r:0)  0@9728r w=3.983814e-04
assigning %vreg100 to %W9: W9 [9728r,9760r:0)  0@9728r

selectOrSplit GPR64common:%vreg87 [9736r,9824r:0)  0@9736r w=3.526655e-04
assigning %vreg87 to %X10: W10 [9736r,9824r:0)  0@9736r

selectOrSplit GPR32:%vreg104 [9744r,9856r:0)  0@9744r w=3.361343e-04
assigning %vreg104 to %W11: W11 [9744r,9856r:0)  0@9744r

selectOrSplit GPR32:%vreg102 [9752r,9760r:0)  0@9752r w=inf
assigning %vreg102 to %W8: W8 [9752r,9760r:0)  0@9752r

selectOrSplit GPR64:%vreg93 [9760r,9776r:0)  0@9760r w=inf
assigning %vreg93 to %X8: W8 [9760r,9776r:0)  0@9760r

selectOrSplit GPR64:%vreg94 [9776r,9808r:0)  0@9776r w=3.983814e-04
assigning %vreg94 to %X8: W8 [9776r,9808r:0)  0@9776r

selectOrSplit GPR64:%vreg89 [9792r,9808r:0)  0@9792r w=inf
assigning %vreg89 to %X9: W9 [9792r,9808r:0)  0@9792r

selectOrSplit GPR64:%vreg90 [9808r,9824r:0)  0@9808r w=inf
assigning %vreg90 to %X8: W8 [9808r,9824r:0)  0@9808r

selectOrSplit GPR64common:%vreg91 [9824r,9840r:0)  0@9824r w=inf
assigning %vreg91 to %X8: W8 [9824r,9840r:0)  0@9824r

selectOrSplit GPR32:%vreg85 [9840r,9856r:0)  0@9840r w=inf
assigning %vreg85 to %W8: W8 [9840r,9856r:0)  0@9840r

selectOrSplit GPR32:%vreg83 [9856r,9872r:0)  0@9856r w=inf
assigning %vreg83 to %W8: W8 [9856r,9872r:0)  0@9856r

selectOrSplit GPR32common:%vreg79 [9888r,9904r:0)  0@9888r w=inf
assigning %vreg79 to %W8: W8 [9888r,9904r:0)  0@9888r

selectOrSplit GPR32common:%vreg78 [9904r,9920r:0)  0@9904r w=inf
assigning %vreg78 to %W8: W8 [9904r,9920r:0)  0@9904r

selectOrSplit GPR64common:%vreg75 [9936r,9952r:0)  0@9936r w=inf
assigning %vreg75 to %X8: W8 [9936r,9952r:0)  0@9936r

selectOrSplit GPR64common:%vreg74 [9952r,9968r:0)  0@9952r w=inf
assigning %vreg74 to %X8: W8 [9952r,9968r:0)  0@9952r

selectOrSplit GPR32common:%vreg71 [9984r,10000r:0)  0@9984r w=inf
assigning %vreg71 to %W8: W8 [9984r,10000r:0)  0@9984r

selectOrSplit GPR32common:%vreg70 [10000r,10016r:0)  0@10000r w=inf
assigning %vreg70 to %W8: W8 [10000r,10016r:0)  0@10000r

selectOrSplit GPR32:%vreg110 [10096r,10112r:0)  0@10096r w=inf
assigning %vreg110 to %W8: W8 [10096r,10112r:0)  0@10096r

selectOrSplit GPR32:%vreg353 [10144r,10160r:0)  0@10144r w=inf
assigning %vreg353 to %W8: W8 [10144r,10160r:0)  0@10144r

selectOrSplit GPR32:%vreg147 [10240r,10272r:0)  0@10240r w=6.070769e-04
assigning %vreg147 to %W8: W8 [10240r,10272r:0)  0@10240r

selectOrSplit GPR64common:%vreg146 [10256r,10272r:0)  0@10256r w=6.304260e-04
assigning %vreg146 to %X9: W9 [10256r,10272r:0)  0@10256r

selectOrSplit GPR64common:%vreg125 [10264r,10344r:0)  0@10264r w=2.731846e-04
assigning %vreg125 to %X10: W10 [10264r,10344r:0)  0@10264r

selectOrSplit GPR32:%vreg142 [10304r,10360r:0)  0@10304r w=5.751255e-04
assigning %vreg142 to %W8: W8 [10304r,10360r:0)  0@10304r

selectOrSplit GPR32:%vreg139 [10336r,10368r:0)  0@10336r w=6.070769e-04
assigning %vreg139 to %W9: W9 [10336r,10368r:0)  0@10336r

selectOrSplit GPR64common:%vreg126 [10344r,10432r:0)  0@10344r w=5.374124e-04
assigning %vreg126 to %X10: W10 [10344r,10432r:0)  0@10344r

selectOrSplit GPR32:%vreg143 [10352r,10464r:0)  0@10352r w=5.122211e-04
assigning %vreg143 to %W11: W11 [10352r,10464r:0)  0@10352r

selectOrSplit GPR32:%vreg141 [10360r,10368r:0)  0@10360r w=inf
assigning %vreg141 to %W8: W8 [10360r,10368r:0)  0@10360r

selectOrSplit GPR64:%vreg132 [10368r,10384r:0)  0@10368r w=inf
assigning %vreg132 to %X8: W8 [10368r,10384r:0)  0@10368r

selectOrSplit GPR64:%vreg133 [10384r,10416r:0)  0@10384r w=6.070769e-04
assigning %vreg133 to %X8: W8 [10384r,10416r:0)  0@10384r

selectOrSplit GPR64:%vreg128 [10400r,10416r:0)  0@10400r w=inf
assigning %vreg128 to %X9: W9 [10400r,10416r:0)  0@10400r

selectOrSplit GPR64:%vreg129 [10416r,10432r:0)  0@10416r w=inf
assigning %vreg129 to %X8: W8 [10416r,10432r:0)  0@10416r

selectOrSplit GPR64common:%vreg130 [10432r,10448r:0)  0@10432r w=inf
assigning %vreg130 to %X8: W8 [10432r,10448r:0)  0@10432r

selectOrSplit GPR32:%vreg124 [10448r,10464r:0)  0@10448r w=inf
assigning %vreg124 to %W8: W8 [10448r,10464r:0)  0@10448r

selectOrSplit GPR32:%vreg122 [10464r,10480r:0)  0@10464r w=inf
assigning %vreg122 to %W8: W8 [10464r,10480r:0)  0@10464r

selectOrSplit GPR64common:%vreg118 [10496r,10512r:0)  0@10496r w=inf
assigning %vreg118 to %X8: W8 [10496r,10512r:0)  0@10496r

selectOrSplit GPR64common:%vreg117 [10512r,10528r:0)  0@10512r w=inf
assigning %vreg117 to %X8: W8 [10512r,10528r:0)  0@10512r

selectOrSplit GPR32common:%vreg114 [10544r,10560r:0)  0@10544r w=inf
assigning %vreg114 to %W8: W8 [10544r,10560r:0)  0@10544r

selectOrSplit GPR32common:%vreg113 [10560r,10576r:0)  0@10560r w=inf
assigning %vreg113 to %W8: W8 [10560r,10576r:0)  0@10560r

selectOrSplit GPR32:%vreg151 [10608r,10640r:0)  0@10608r w=1.766257e-03
assigning %vreg151 to %W8: W8 [10608r,10640r:0)  0@10608r

selectOrSplit GPR32:%vreg150 [10624r,10640r:0)  0@10624r w=inf
assigning %vreg150 to %W9: W9 [10624r,10640r:0)  0@10624r

selectOrSplit GPR32:%vreg352 [10688r,10704r:0)  0@10688r w=inf
assigning %vreg352 to %W8: W8 [10688r,10704r:0)  0@10688r

selectOrSplit GPR32:%vreg155 [10752r,10784r:0)  0@10752r w=6.070769e-04
assigning %vreg155 to %W8: W8 [10752r,10784r:0)  0@10752r

selectOrSplit GPR32:%vreg154 [10768r,10784r:0)  0@10768r w=inf
assigning %vreg154 to %W9: W9 [10768r,10784r:0)  0@10768r

selectOrSplit GPR32:%vreg192 [10880r,10912r:0)  0@10880r w=inf
assigning %vreg192 to %W8: W8 [10880r,10912r:0)  0@10880r

selectOrSplit GPR64:%vreg189 [10928r,10992r:0)  0@10928r w=2.826048e-04
assigning %vreg189 to %X8: W8 [10928r,10992r:0)  0@10928r

selectOrSplit GPR64:%vreg184 [10960r,11008r:0)  0@10960r w=2.926978e-04
assigning %vreg184 to %X9: W9 [10960r,11008r:0)  0@10960r

selectOrSplit GPR64:%vreg181 [10976r,10992r:0)  0@10976r w=inf
assigning %vreg181 to %X10: W10 [10976r,10992r:0)  0@10976r

selectOrSplit GPR64:%vreg182 [10992r,11008r:0)  0@10992r w=inf
assigning %vreg182 to %X8: W8 [10992r,11008r:0)  0@10992r

selectOrSplit GPR64common:%vreg183 [11008r,11024r:0)  0@11008r w=inf
assigning %vreg183 to %X8: W8 [11008r,11024r:0)  0@11008r

selectOrSplit GPR32:%vreg178 [11024r,11040r:0)  0@11024r w=inf
assigning %vreg178 to %W8: W8 [11024r,11040r:0)  0@11024r

selectOrSplit GPR32:%vreg175 [11056r,11072r:0)  0@11056r w=inf
assigning %vreg175 to %W8: W8 [11056r,11072r:0)  0@11056r

selectOrSplit GPR32common:%vreg172 [11072r,11104r:0)  0@11072r w=inf
assigning %vreg172 to %W8: W8 [11072r,11104r:0)  0@11072r

selectOrSplit GPR32:%vreg169 [11120r,11136r:0)  0@11120r w=inf
assigning %vreg169 to %W8: W8 [11120r,11136r:0)  0@11120r

selectOrSplit GPR32:%vreg168 [11136r,11152r:0)  0@11136r w=inf
assigning %vreg168 to %W8: W8 [11136r,11152r:0)  0@11136r

selectOrSplit GPR32common:%vreg165 [11168r,11184r:0)  0@11168r w=inf
assigning %vreg165 to %W8: W8 [11168r,11184r:0)  0@11168r

selectOrSplit GPR32common:%vreg164 [11184r,11200r:0)  0@11184r w=inf
assigning %vreg164 to %W8: W8 [11184r,11200r:0)  0@11184r

selectOrSplit GPR32:%vreg161 [11216r,11248r:0)  0@11216r w=3.035385e-04
assigning %vreg161 to %W8: W8 [11216r,11248r:0)  0@11216r

selectOrSplit GPR32:%vreg158 [11232r,11248r:0)  0@11232r w=inf
assigning %vreg158 to %W9: W9 [11232r,11248r:0)  0@11232r

selectOrSplit GPR32:%vreg351 [11296r,11312r:0)  0@11296r w=inf
assigning %vreg351 to %W8: W8 [11296r,11312r:0)  0@11296r

selectOrSplit GPR32:%vreg197 [11360r,11392r:0)  0@11360r w=1.517692e-04
assigning %vreg197 to %W8: W8 [11360r,11392r:0)  0@11360r

selectOrSplit GPR32:%vreg196 [11376r,11392r:0)  0@11376r w=inf
assigning %vreg196 to %W9: W9 [11376r,11392r:0)  0@11376r

selectOrSplit GPR32:%vreg230 [11472r,11488r:0)  0@11472r w=inf
assigning %vreg230 to %W8: W8 [11472r,11488r:0)  0@11472r

selectOrSplit GPR64:%vreg229 [11504r,11568r:0)  0@11504r w=7.060335e-05
assigning %vreg229 to %X8: W8 [11504r,11568r:0)  0@11504r

selectOrSplit GPR64:%vreg224 [11536r,11584r:0)  0@11536r w=7.312490e-05
assigning %vreg224 to %X9: W9 [11536r,11584r:0)  0@11536r

selectOrSplit GPR64:%vreg221 [11552r,11568r:0)  0@11552r w=inf
assigning %vreg221 to %X10: W10 [11552r,11568r:0)  0@11552r

selectOrSplit GPR64:%vreg222 [11568r,11584r:0)  0@11568r w=inf
assigning %vreg222 to %X8: W8 [11568r,11584r:0)  0@11568r

selectOrSplit GPR64common:%vreg223 [11584r,11600r:0)  0@11584r w=inf
assigning %vreg223 to %X8: W8 [11584r,11600r:0)  0@11584r

selectOrSplit GPR32:%vreg218 [11600r,11616r:0)  0@11600r w=inf
assigning %vreg218 to %W8: W8 [11600r,11616r:0)  0@11600r

selectOrSplit GPR32:%vreg215 [11632r,11648r:0)  0@11632r w=inf
assigning %vreg215 to %W8: W8 [11632r,11648r:0)  0@11632r

selectOrSplit GPR32common:%vreg212 [11648r,11680r:0)  0@11648r w=inf
assigning %vreg212 to %W8: W8 [11648r,11680r:0)  0@11648r

selectOrSplit GPR32:%vreg209 [11696r,11712r:0)  0@11696r w=inf
assigning %vreg209 to %W8: W8 [11696r,11712r:0)  0@11696r

selectOrSplit GPR32:%vreg208 [11712r,11728r:0)  0@11712r w=inf
assigning %vreg208 to %W8: W8 [11712r,11728r:0)  0@11712r

selectOrSplit GPR32common:%vreg205 [11744r,11760r:0)  0@11744r w=inf
assigning %vreg205 to %W8: W8 [11744r,11760r:0)  0@11744r

selectOrSplit GPR32common:%vreg204 [11760r,11776r:0)  0@11760r w=inf
assigning %vreg204 to %W8: W8 [11760r,11776r:0)  0@11760r

selectOrSplit GPR32:%vreg201 [11792r,11824r:0)  0@11792r w=7.583323e-05
assigning %vreg201 to %W8: W8 [11792r,11824r:0)  0@11792r

selectOrSplit GPR32:%vreg200 [11808r,11824r:0)  0@11808r w=inf
assigning %vreg200 to %W9: W9 [11808r,11824r:0)  0@11808r

selectOrSplit GPR32:%vreg236 [11904r,11936r:0)  0@11904r w=3.791662e-05
assigning %vreg236 to %W8: W8 [11904r,11936r:0)  0@11904r

selectOrSplit GPR32:%vreg233 [11920r,11936r:0)  0@11920r w=inf
assigning %vreg233 to %W9: W9 [11920r,11936r:0)  0@11920r

selectOrSplit GPR32:%vreg347 [11984r,12000r:0)  0@11984r w=inf
assigning %vreg347 to %W8: W8 [11984r,12000r:0)  0@11984r

selectOrSplit GPR32:%vreg269 [12048r,12064r:0)  0@12048r w=inf
assigning %vreg269 to %W8: W8 [12048r,12064r:0)  0@12048r

selectOrSplit GPR64:%vreg268 [12080r,12144r:0)  0@12080r w=1.760301e-05
assigning %vreg268 to %X8: W8 [12080r,12144r:0)  0@12080r

selectOrSplit GPR64:%vreg263 [12112r,12160r:0)  0@12112r w=1.823169e-05
assigning %vreg263 to %X9: W9 [12112r,12160r:0)  0@12112r

selectOrSplit GPR64:%vreg260 [12128r,12144r:0)  0@12128r w=inf
assigning %vreg260 to %X10: W10 [12128r,12144r:0)  0@12128r

selectOrSplit GPR64:%vreg261 [12144r,12160r:0)  0@12144r w=inf
assigning %vreg261 to %X8: W8 [12144r,12160r:0)  0@12144r

selectOrSplit GPR64common:%vreg262 [12160r,12176r:0)  0@12160r w=inf
assigning %vreg262 to %X8: W8 [12160r,12176r:0)  0@12160r

selectOrSplit GPR32:%vreg257 [12176r,12192r:0)  0@12176r w=inf
assigning %vreg257 to %W8: W8 [12176r,12192r:0)  0@12176r

selectOrSplit GPR32:%vreg254 [12208r,12224r:0)  0@12208r w=inf
assigning %vreg254 to %W8: W8 [12208r,12224r:0)  0@12208r

selectOrSplit GPR32common:%vreg251 [12224r,12256r:0)  0@12224r w=inf
assigning %vreg251 to %W8: W8 [12224r,12256r:0)  0@12224r

selectOrSplit GPR32:%vreg248 [12272r,12288r:0)  0@12272r w=inf
assigning %vreg248 to %W8: W8 [12272r,12288r:0)  0@12272r

selectOrSplit GPR32:%vreg247 [12288r,12304r:0)  0@12288r w=inf
assigning %vreg247 to %W8: W8 [12288r,12304r:0)  0@12288r

selectOrSplit GPR32common:%vreg244 [12320r,12336r:0)  0@12320r w=inf
assigning %vreg244 to %W8: W8 [12320r,12336r:0)  0@12320r

selectOrSplit GPR32common:%vreg243 [12336r,12352r:0)  0@12336r w=inf
assigning %vreg243 to %W8: W8 [12336r,12352r:0)  0@12336r

selectOrSplit GPR32:%vreg240 [12368r,12400r:0)  0@12368r w=1.890693e-05
assigning %vreg240 to %W8: W8 [12368r,12400r:0)  0@12368r

selectOrSplit GPR32:%vreg239 [12384r,12400r:0)  0@12384r w=inf
assigning %vreg239 to %W9: W9 [12384r,12400r:0)  0@12384r

selectOrSplit GPR32:%vreg275 [12480r,12512r:0)  0@12480r w=9.453466e-06
assigning %vreg275 to %W8: W8 [12480r,12512r:0)  0@12480r

selectOrSplit GPR32:%vreg272 [12496r,12512r:0)  0@12496r w=inf
assigning %vreg272 to %W9: W9 [12496r,12512r:0)  0@12496r

selectOrSplit GPR32:%vreg343 [12560r,12576r:0)  0@12560r w=inf
assigning %vreg343 to %W8: W8 [12560r,12576r:0)  0@12560r

selectOrSplit GPR64:%vreg339 [12624r,12688r:0)  0@12624r w=4.400752e-06
assigning %vreg339 to %X8: W8 [12624r,12688r:0)  0@12624r

selectOrSplit GPR64:%vreg334 [12656r,12704r:0)  0@12656r w=4.557921e-06
assigning %vreg334 to %X9: W9 [12656r,12704r:0)  0@12656r

selectOrSplit GPR64:%vreg331 [12672r,12688r:0)  0@12672r w=inf
assigning %vreg331 to %X10: W10 [12672r,12688r:0)  0@12672r

selectOrSplit GPR64:%vreg332 [12688r,12704r:0)  0@12688r w=inf
assigning %vreg332 to %X8: W8 [12688r,12704r:0)  0@12688r

selectOrSplit GPR64common:%vreg333 [12704r,12720r:0)  0@12704r w=inf
assigning %vreg333 to %X8: W8 [12704r,12720r:0)  0@12704r

selectOrSplit GPR32:%vreg328 [12720r,12736r:0)  0@12720r w=inf
assigning %vreg328 to %W8: W8 [12720r,12736r:0)  0@12720r

selectOrSplit GPR32:%vreg325 [12752r,12768r:0)  0@12752r w=inf
assigning %vreg325 to %W8: W8 [12752r,12768r:0)  0@12752r

selectOrSplit GPR32common:%vreg322 [12768r,12800r:0)  0@12768r w=inf
assigning %vreg322 to %W8: W8 [12768r,12800r:0)  0@12768r

selectOrSplit GPR32:%vreg319 [12816r,12832r:0)  0@12816r w=inf
assigning %vreg319 to %W8: W8 [12816r,12832r:0)  0@12816r

selectOrSplit GPR32:%vreg318 [12832r,12848r:0)  0@12832r w=inf
assigning %vreg318 to %W8: W8 [12832r,12848r:0)  0@12832r

selectOrSplit GPR32common:%vreg315 [12864r,12880r:0)  0@12864r w=inf
assigning %vreg315 to %W8: W8 [12864r,12880r:0)  0@12864r

selectOrSplit GPR32common:%vreg314 [12880r,12896r:0)  0@12880r w=inf
assigning %vreg314 to %W8: W8 [12880r,12896r:0)  0@12880r

selectOrSplit GPR32common:%vreg311 [12912r,12928r:0)  0@12912r w=inf
assigning %vreg311 to %W8: W8 [12912r,12928r:0)  0@12912r

selectOrSplit GPR32common:%vreg308 [12928r,12944r:0)  0@12928r w=inf
assigning %vreg308 to %W8: W8 [12928r,12944r:0)  0@12928r

selectOrSplit GPR64:%vreg305 [12960r,13024r:0)  0@12960r w=4.400752e-06
assigning %vreg305 to %X8: W8 [12960r,13024r:0)  0@12960r

selectOrSplit GPR64:%vreg300 [12992r,13040r:0)  0@12992r w=4.557921e-06
assigning %vreg300 to %X9: W9 [12992r,13040r:0)  0@12992r

selectOrSplit GPR64:%vreg297 [13008r,13024r:0)  0@13008r w=inf
assigning %vreg297 to %X10: W10 [13008r,13024r:0)  0@13008r

selectOrSplit GPR64:%vreg298 [13024r,13040r:0)  0@13024r w=inf
assigning %vreg298 to %X8: W8 [13024r,13040r:0)  0@13024r

selectOrSplit GPR64common:%vreg299 [13040r,13056r:0)  0@13040r w=inf
assigning %vreg299 to %X8: W8 [13040r,13056r:0)  0@13040r

selectOrSplit GPR32:%vreg294 [13056r,13072r:0)  0@13056r w=inf
assigning %vreg294 to %W8: W8 [13056r,13072r:0)  0@13056r

selectOrSplit GPR32:%vreg291 [13088r,13104r:0)  0@13088r w=inf
assigning %vreg291 to %W8: W8 [13088r,13104r:0)  0@13088r

selectOrSplit GPR32common:%vreg288 [13104r,13136r:0)  0@13104r w=inf
assigning %vreg288 to %W8: W8 [13104r,13136r:0)  0@13104r

selectOrSplit GPR32:%vreg286 [13136r,13152r:0)  0@13136r w=inf
assigning %vreg286 to %W8: W8 [13136r,13152r:0)  0@13136r

selectOrSplit GPR32:%vreg283 [13168r,13184r:0)  0@13168r w=inf
assigning %vreg283 to %W8: W8 [13168r,13184r:0)  0@13168r

selectOrSplit GPR32:%vreg282 [13184r,13200r:0)  0@13184r w=inf
assigning %vreg282 to %W8: W8 [13184r,13200r:0)  0@13184r

selectOrSplit GPR32common:%vreg279 [13216r,13232r:0)  0@13216r w=inf
assigning %vreg279 to %W8: W8 [13216r,13232r:0)  0@13216r

selectOrSplit GPR32common:%vreg278 [13232r,13248r:0)  0@13232r w=inf
assigning %vreg278 to %W8: W8 [13232r,13248r:0)  0@13232r

selectOrSplit GPR64common:%vreg381 [13296r,13312r:0)  0@13296r w=inf
assigning %vreg381 to %X8: W8 [13296r,13312r:0)  0@13296r

selectOrSplit GPR64common:%vreg380 [13312r,13328r:0)  0@13312r w=inf
assigning %vreg380 to %X8: W8 [13312r,13328r:0)  0@13312r

selectOrSplit GPR32:%vreg378 [13328r,13344r:0)  0@13328r w=inf
assigning %vreg378 to %W8: W8 [13328r,13344r:0)  0@13328r

selectOrSplit GPR64common:%vreg370 [13408r,13424r:0)  0@13408r w=inf
assigning %vreg370 to %X8: W8 [13408r,13424r:0)  0@13408r

selectOrSplit GPR64common:%vreg369 [13424r,13472r:0)  0@13424r w=2.470047e-03
assigning %vreg369 to %X8: W8 [13424r,13472r:0)  0@13424r

selectOrSplit GPR32:%vreg375 [13428r,13448r:0)  0@13428r w=1.756478e-03
assigning %vreg375 to %W9: W9 [13428r,13448r:0)  0@13428r

selectOrSplit GPR32:%vreg374 [13432r,13448r:0)  0@13432r w=1.773367e-03
assigning %vreg374 to %W10: W10 [13432r,13448r:0)  0@13432r

selectOrSplit GPR32:%vreg367 [13440r,13456r:0)  0@13440r w=1.773367e-03
assigning %vreg367 to %W11: W11 [13440r,13456r:0)  0@13440r

selectOrSplit GPR32:%vreg373 [13448r,13456r:0)  0@13448r w=inf
assigning %vreg373 to %W9: W9 [13448r,13456r:0)  0@13448r

selectOrSplit GPR32:%vreg366 [13456r,13472r:0)  0@13456r w=inf
assigning %vreg366 to %W9: W9 [13456r,13472r:0)  0@13456r

selectOrSplit GPR64common:%vreg361 [13488r,13504r:0)  0@13488r w=inf
assigning %vreg361 to %X8: W8 [13488r,13504r:0)  0@13488r

selectOrSplit GPR64common:%vreg360 [13504r,13520r:0)  0@13504r w=inf
assigning %vreg360 to %X8: W8 [13504r,13520r:0)  0@13504r

selectOrSplit GPR32:%vreg358 [13520r,13552r:0)  0@13520r w=1.707686e-03
assigning %vreg358 to %W8: W8 [13520r,13552r:0)  0@13520r

selectOrSplit GPR32:%vreg356 [13536r,13552r:0)  0@13536r w=inf
assigning %vreg356 to %W9: W9 [13536r,13552r:0)  0@13536r

selectOrSplit GPR64common:%vreg389 [13600r,13616r:0)  0@13600r w=inf
assigning %vreg389 to %X8: W8 [13600r,13616r:0)  0@13600r

selectOrSplit GPR64common:%vreg388 [13616r,13664r:0)  0@13616r w=1.234949e-03
assigning %vreg388 to %X8: W8 [13616r,13664r:0)  0@13616r

selectOrSplit GPR32common:%vreg386 [13632r,13648r:0)  0@13632r w=inf
assigning %vreg386 to %W9: W9 [13632r,13648r:0)  0@13632r

selectOrSplit GPR32common:%vreg385 [13648r,13664r:0)  0@13648r w=inf
assigning %vreg385 to %W9: W9 [13648r,13664r:0)  0@13648r

selectOrSplit GPR32:%vreg429 [13696r,13728r:0)  0@13696r w=1.707686e-03
assigning %vreg429 to %W8: W8 [13696r,13728r:0)  0@13696r

selectOrSplit GPR64common:%vreg428 [13712r,13728r:0)  0@13712r w=inf
assigning %vreg428 to %X9: W9 [13712r,13728r:0)  0@13712r

selectOrSplit GPR32:%vreg425 [13744r,13776r:0)  0@13744r w=1.707686e-03
assigning %vreg425 to %W8: W8 [13744r,13776r:0)  0@13744r

selectOrSplit GPR64common:%vreg424 [13760r,13776r:0)  0@13760r w=inf
assigning %vreg424 to %X9: W9 [13760r,13776r:0)  0@13760r

selectOrSplit GPR32:%vreg421 [13792r,13824r:0)  0@13792r w=1.707686e-03
assigning %vreg421 to %W8: W8 [13792r,13824r:0)  0@13792r

selectOrSplit GPR64common:%vreg420 [13808r,13824r:0)  0@13808r w=inf
assigning %vreg420 to %X9: W9 [13808r,13824r:0)  0@13808r

selectOrSplit GPR32:%vreg417 [13840r,13872r:0)  0@13840r w=1.707686e-03
assigning %vreg417 to %W8: W8 [13840r,13872r:0)  0@13840r

selectOrSplit GPR64common:%vreg416 [13856r,13872r:0)  0@13856r w=inf
assigning %vreg416 to %X9: W9 [13856r,13872r:0)  0@13856r

selectOrSplit GPR32:%vreg413 [13888r,13920r:0)  0@13888r w=1.707686e-03
assigning %vreg413 to %W8: W8 [13888r,13920r:0)  0@13888r

selectOrSplit GPR64common:%vreg412 [13904r,13920r:0)  0@13904r w=inf
assigning %vreg412 to %X9: W9 [13904r,13920r:0)  0@13904r

selectOrSplit GPR64:%vreg409 [13936r,13968r:0)  0@13936r w=1.707686e-03
assigning %vreg409 to %X8: W8 [13936r,13968r:0)  0@13936r

selectOrSplit GPR64common:%vreg408 [13952r,13968r:0)  0@13952r w=inf
assigning %vreg408 to %X9: W9 [13952r,13968r:0)  0@13952r

selectOrSplit GPR32:%vreg405 [13984r,14016r:0)  0@13984r w=1.707686e-03
assigning %vreg405 to %W8: W8 [13984r,14016r:0)  0@13984r

selectOrSplit GPR64common:%vreg404 [14000r,14016r:0)  0@14000r w=inf
assigning %vreg404 to %X9: W9 [14000r,14016r:0)  0@14000r

selectOrSplit GPR64common:%vreg400 [14048r,14064r:0)  0@14048r w=1.773367e-03
assigning %vreg400 to %X8: W8 [14048r,14064r:0)  0@14048r

selectOrSplit GPR64:%vreg401 [14056r,14080r:0)  0@14056r w=1.739907e-03
assigning %vreg401 to %X9: W9 [14056r,14080r:0)  0@14056r

selectOrSplit GPR64common:%vreg399 [14064r,14080r:0)  0@14064r w=inf
assigning %vreg399 to %X8: W8 [14064r,14080r:0)  0@14064r

selectOrSplit GPR64common:%vreg394 [14112r,14128r:0)  0@14112r w=1.773367e-03
assigning %vreg394 to %X8: W8 [14112r,14128r:0)  0@14112r

selectOrSplit GPR32:%vreg395 [14120r,14144r:0)  0@14120r w=1.739907e-03
assigning %vreg395 to %W9: W9 [14120r,14144r:0)  0@14120r

selectOrSplit GPR64common:%vreg393 [14128r,14144r:0)  0@14128r w=inf
assigning %vreg393 to %X8: W8 [14128r,14144r:0)  0@14128r

********** STACK TRANSFORMATION METADATA **********
********** Function: unRLE_obuf_to_output_FAST
********** REGISTER MAP **********
[%vreg1 -> %X20] GPR64
[%vreg3 -> %W8] GPR32
[%vreg5 -> %W8] GPR32
[%vreg6 -> %X8] GPR64common
[%vreg7 -> %X8] GPR64common
[%vreg9 -> %X0] GPR64sp
[%vreg10 -> %X19] GPR64
[%vreg14 -> %W8] GPR32common
[%vreg16 -> %X9] GPR64
[%vreg17 -> %X8] GPR64common
[%vreg18 -> %W8] GPR32common
[%vreg19 -> %X8] GPR64
[%vreg21 -> %W8] GPR32
[%vreg24 -> %W8] GPR32
[%vreg26 -> %X8] GPR64common
[%vreg27 -> %X8] GPR64common
[%vreg30 -> %X8] GPR64
[%vreg32 -> %X8] GPR64common
[%vreg33 -> %X8] GPR64common
[%vreg36 -> %W8] GPR32
[%vreg37 -> %X8] GPR64common
[%vreg40 -> %X8] GPR64
[%vreg41 -> %X8] GPR64common
[%vreg44 -> %W8] GPR32
[%vreg45 -> %X8] GPR64common
[%vreg48 -> %W8] GPR32
[%vreg49 -> %X8] GPR64common
[%vreg52 -> %W8] GPR32
[%vreg53 -> %X8] GPR64common
[%vreg56 -> %W8] GPR32
[%vreg57 -> %X8] GPR64common
[%vreg60 -> %W8] GPR32
[%vreg61 -> %X8] GPR64common
[%vreg63 -> %W8] GPR32common
[%vreg65 -> %W8] GPR32
[%vreg67 -> %W8] GPR32common
[%vreg70 -> %W8] GPR32common
[%vreg71 -> %W8] GPR32common
[%vreg74 -> %X8] GPR64common
[%vreg75 -> %X8] GPR64common
[%vreg78 -> %W8] GPR32common
[%vreg79 -> %W8] GPR32common
[%vreg83 -> %W8] GPR32
[%vreg85 -> %W8] GPR32
[%vreg86 -> %X10] GPR64common
[%vreg87 -> %X10] GPR64common
[%vreg89 -> %X9] GPR64
[%vreg90 -> %X8] GPR64
[%vreg91 -> %X8] GPR64common
[%vreg93 -> %X8] GPR64
[%vreg94 -> %X8] GPR64
[%vreg100 -> %W9] GPR32
[%vreg102 -> %W8] GPR32
[%vreg103 -> %W8] GPR32
[%vreg104 -> %W11] GPR32
[%vreg107 -> %X9] GPR64common
[%vreg108 -> %W8] GPR32
[%vreg110 -> %W8] GPR32
[%vreg113 -> %W8] GPR32common
[%vreg114 -> %W8] GPR32common
[%vreg117 -> %X8] GPR64common
[%vreg118 -> %X8] GPR64common
[%vreg122 -> %W8] GPR32
[%vreg124 -> %W8] GPR32
[%vreg125 -> %X10] GPR64common
[%vreg126 -> %X10] GPR64common
[%vreg128 -> %X9] GPR64
[%vreg129 -> %X8] GPR64
[%vreg130 -> %X8] GPR64common
[%vreg132 -> %X8] GPR64
[%vreg133 -> %X8] GPR64
[%vreg139 -> %W9] GPR32
[%vreg141 -> %W8] GPR32
[%vreg142 -> %W8] GPR32
[%vreg143 -> %W11] GPR32
[%vreg146 -> %X9] GPR64common
[%vreg147 -> %W8] GPR32
[%vreg150 -> %W9] GPR32
[%vreg151 -> %W8] GPR32
[%vreg154 -> %W9] GPR32
[%vreg155 -> %W8] GPR32
[%vreg158 -> %W9] GPR32
[%vreg161 -> %W8] GPR32
[%vreg164 -> %W8] GPR32common
[%vreg165 -> %W8] GPR32common
[%vreg168 -> %W8] GPR32
[%vreg169 -> %W8] GPR32
[%vreg172 -> %W8] GPR32common
[%vreg175 -> %W8] GPR32
[%vreg178 -> %W8] GPR32
[%vreg181 -> %X10] GPR64
[%vreg182 -> %X8] GPR64
[%vreg183 -> %X8] GPR64common
[%vreg184 -> %X9] GPR64
[%vreg189 -> %X8] GPR64
[%vreg192 -> %W8] GPR32
[%vreg196 -> %W9] GPR32
[%vreg197 -> %W8] GPR32
[%vreg200 -> %W9] GPR32
[%vreg201 -> %W8] GPR32
[%vreg204 -> %W8] GPR32common
[%vreg205 -> %W8] GPR32common
[%vreg208 -> %W8] GPR32
[%vreg209 -> %W8] GPR32
[%vreg212 -> %W8] GPR32common
[%vreg215 -> %W8] GPR32
[%vreg218 -> %W8] GPR32
[%vreg221 -> %X10] GPR64
[%vreg222 -> %X8] GPR64
[%vreg223 -> %X8] GPR64common
[%vreg224 -> %X9] GPR64
[%vreg229 -> %X8] GPR64
[%vreg230 -> %W8] GPR32
[%vreg233 -> %W9] GPR32
[%vreg236 -> %W8] GPR32
[%vreg239 -> %W9] GPR32
[%vreg240 -> %W8] GPR32
[%vreg243 -> %W8] GPR32common
[%vreg244 -> %W8] GPR32common
[%vreg247 -> %W8] GPR32
[%vreg248 -> %W8] GPR32
[%vreg251 -> %W8] GPR32common
[%vreg254 -> %W8] GPR32
[%vreg257 -> %W8] GPR32
[%vreg260 -> %X10] GPR64
[%vreg261 -> %X8] GPR64
[%vreg262 -> %X8] GPR64common
[%vreg263 -> %X9] GPR64
[%vreg268 -> %X8] GPR64
[%vreg269 -> %W8] GPR32
[%vreg272 -> %W9] GPR32
[%vreg275 -> %W8] GPR32
[%vreg278 -> %W8] GPR32common
[%vreg279 -> %W8] GPR32common
[%vreg282 -> %W8] GPR32
[%vreg283 -> %W8] GPR32
[%vreg286 -> %W8] GPR32
[%vreg288 -> %W8] GPR32common
[%vreg291 -> %W8] GPR32
[%vreg294 -> %W8] GPR32
[%vreg297 -> %X10] GPR64
[%vreg298 -> %X8] GPR64
[%vreg299 -> %X8] GPR64common
[%vreg300 -> %X9] GPR64
[%vreg305 -> %X8] GPR64
[%vreg308 -> %W8] GPR32common
[%vreg311 -> %W8] GPR32common
[%vreg314 -> %W8] GPR32common
[%vreg315 -> %W8] GPR32common
[%vreg318 -> %W8] GPR32
[%vreg319 -> %W8] GPR32
[%vreg322 -> %W8] GPR32common
[%vreg325 -> %W8] GPR32
[%vreg328 -> %W8] GPR32
[%vreg331 -> %X10] GPR64
[%vreg332 -> %X8] GPR64
[%vreg333 -> %X8] GPR64common
[%vreg334 -> %X9] GPR64
[%vreg339 -> %X8] GPR64
[%vreg343 -> %W8] GPR32
[%vreg347 -> %W8] GPR32
[%vreg351 -> %W8] GPR32
[%vreg352 -> %W8] GPR32
[%vreg353 -> %W8] GPR32
[%vreg356 -> %W9] GPR32
[%vreg358 -> %W8] GPR32
[%vreg360 -> %X8] GPR64common
[%vreg361 -> %X8] GPR64common
[%vreg366 -> %W9] GPR32
[%vreg367 -> %W11] GPR32
[%vreg369 -> %X8] GPR64common
[%vreg370 -> %X8] GPR64common
[%vreg373 -> %W9] GPR32
[%vreg374 -> %W10] GPR32
[%vreg375 -> %W9] GPR32
[%vreg378 -> %W8] GPR32
[%vreg380 -> %X8] GPR64common
[%vreg381 -> %X8] GPR64common
[%vreg385 -> %W9] GPR32common
[%vreg386 -> %W9] GPR32common
[%vreg388 -> %X8] GPR64common
[%vreg389 -> %X8] GPR64common
[%vreg393 -> %X8] GPR64common
[%vreg394 -> %X8] GPR64common
[%vreg395 -> %W9] GPR32
[%vreg399 -> %X8] GPR64common
[%vreg400 -> %X8] GPR64common
[%vreg401 -> %X9] GPR64
[%vreg404 -> %X9] GPR64common
[%vreg405 -> %W8] GPR32
[%vreg408 -> %X9] GPR64common
[%vreg409 -> %X8] GPR64
[%vreg412 -> %X9] GPR64common
[%vreg413 -> %W8] GPR32
[%vreg416 -> %X9] GPR64common
[%vreg417 -> %W8] GPR32
[%vreg420 -> %X9] GPR64common
[%vreg421 -> %W8] GPR32
[%vreg424 -> %X9] GPR64common
[%vreg425 -> %W8] GPR32
[%vreg428 -> %X9] GPR64common
[%vreg429 -> %W8] GPR32
[%vreg432 -> %W8] GPR32
[%vreg434 -> %X8] GPR64common
[%vreg435 -> %X8] GPR64common
[%vreg438 -> %W8] GPR32
[%vreg439 -> %X8] GPR64common
[%vreg442 -> %W8] GPR32
[%vreg444 -> %X8] GPR64common
[%vreg445 -> %X8] GPR64common
[%vreg449 -> %W9] GPR32common
[%vreg450 -> %W9] GPR32common
[%vreg452 -> %X8] GPR64common
[%vreg453 -> %X8] GPR64common
[%vreg457 -> %W9] GPR32common
[%vreg458 -> %W9] GPR32common
[%vreg460 -> %X8] GPR64common
[%vreg461 -> %X8] GPR64common
[%vreg465 -> %X9] GPR64common
[%vreg466 -> %X9] GPR64common
[%vreg468 -> %X8] GPR64common
[%vreg469 -> %X8] GPR64common
[%vreg473 -> %W9] GPR32common
[%vreg474 -> %W9] GPR32common
[%vreg475 -> %X8] GPR64common
[%vreg478 -> %X9] GPR64common
[%vreg481 -> %W8] GPR32
[%vreg483 -> %W8] GPR32
[%vreg484 -> %X10] GPR64common
[%vreg485 -> %X10] GPR64common
[%vreg487 -> %X9] GPR64
[%vreg488 -> %X8] GPR64
[%vreg489 -> %X8] GPR64common
[%vreg491 -> %X8] GPR64
[%vreg492 -> %X8] GPR64
[%vreg499 -> %W9] GPR32
[%vreg500 -> %X9] GPR64common
[%vreg502 -> %W8] GPR32
[%vreg504 -> %W8] GPR32
[%vreg505 -> %X8] GPR64common
[%vreg507 -> %W11] GPR32
[%vreg508 -> %X11] GPR64common
[%vreg512 -> %X8] GPR64common
[%vreg514 -> %X8] GPR64common
[%vreg515 -> %X8] GPR64common
[%vreg517 -> %W9] GPR32
[%vreg518 -> %X9] GPR64common
[%vreg522 -> %W9] GPR32common
[%vreg523 -> %W9] GPR32common
[%vreg525 -> %X8] GPR64common
[%vreg526 -> %X8] GPR64common
[%vreg530 -> %W8] GPR32common
[%vreg532 -> %X10] GPR64
[%vreg533 -> %X8] GPR64common
[%vreg534 -> %W8] GPR32common
[%vreg535 -> %X8] GPR64
[%vreg537 -> %W9] GPR32
[%vreg538 -> %X9] GPR64common
[%vreg542 -> %W8] GPR32common
[%vreg544 -> %X10] GPR64
[%vreg545 -> %X8] GPR64common
[%vreg546 -> %W8] GPR32common
[%vreg547 -> %X8] GPR64
[%vreg549 -> %W9] GPR32
[%vreg550 -> %X9] GPR64common
[%vreg553 -> %W8] GPR32
[%vreg554 -> %X8] GPR64common
[%vreg558 -> %W9] GPR32
[%vreg559 -> %W9] GPR32
[%vreg560 -> %X8] GPR64common
[%vreg563 -> %W8] GPR32common
[%vreg567 -> %W8] GPR32
[%vreg568 -> %X8] GPR64common
[%vreg571 -> %X9] GPR64common
[%vreg573 -> %W8] GPR32
[%vreg576 -> %X10] GPR64
[%vreg577 -> %X8] GPR64
[%vreg578 -> %X8] GPR64common
[%vreg580 -> %X9] GPR64
[%vreg581 -> %X9] GPR64common
[%vreg587 -> %X8] GPR64
[%vreg588 -> %X8] GPR64common
[%vreg591 -> %X9] GPR64common
[%vreg593 -> %W8] GPR32
[%vreg596 -> %X8] GPR64common
[%vreg597 -> %W9] GPR32
[%vreg599 -> %X8] GPR64common
[%vreg602 -> %W8] GPR32common
[%vreg603 -> %X8] GPR64common
[%vreg607 -> %W9] GPR32common
[%vreg608 -> %W9] GPR32common
[%vreg609 -> %X8] GPR64common
[%vreg612 -> %X9] GPR64common
[%vreg614 -> %W8] GPR32
[%vreg615 -> %X9] GPR64common
[%vreg616 -> %X9] GPR64common
[%vreg618 -> %X10] GPR64
[%vreg619 -> %X8] GPR64
[%vreg620 -> %X8] GPR64common
[%vreg625 -> %X8] GPR64
[%vreg626 -> %X8] GPR64common
[%vreg628 -> %X8] GPR64common
[%vreg632 -> %W8] GPR32common
[%vreg634 -> %X10] GPR64
[%vreg635 -> %X8] GPR64common
[%vreg636 -> %W8] GPR32common
[%vreg637 -> %X8] GPR64
[%vreg639 -> %W9] GPR32
[%vreg640 -> %X9] GPR64common
[%vreg644 -> %W9] GPR32common
[%vreg645 -> %W9] GPR32common
[%vreg646 -> %X8] GPR64common
[%vreg649 -> %W8] GPR32
[%vreg655 -> %W10] GPR32
[%vreg657 -> %W11] GPR32
[%vreg658 -> %W8] GPR32
[%vreg659 -> %W8] GPR32
[%vreg661 -> %W9] GPR32common
[%vreg662 -> %X9] GPR64common
[%vreg666 -> %W10] GPR32common
[%vreg667 -> %W10] GPR32common
[%vreg668 -> %X9] GPR64common
[%vreg672 -> %W8] GPR32
[%vreg673 -> %X8] GPR64common
[%vreg676 -> %W9] GPR32
[%vreg679 -> %W8] GPR32
[%vreg680 -> %X8] GPR64common
[%vreg684 -> %W9] GPR32
[%vreg685 -> %W9] GPR32
[%vreg686 -> %X8] GPR64common
[%vreg689 -> %W8] GPR32common
[%vreg693 -> %W8] GPR32
[%vreg694 -> %X8] GPR64common
[%vreg697 -> %X9] GPR64common
[%vreg699 -> %W8] GPR32
[%vreg702 -> %X10] GPR64
[%vreg703 -> %X8] GPR64
[%vreg704 -> %X8] GPR64common
[%vreg706 -> %X9] GPR64
[%vreg707 -> %X9] GPR64common
[%vreg713 -> %X8] GPR64
[%vreg714 -> %X8] GPR64common
[%vreg715 -> %W9] GPR32
[%vreg717 -> %X8] GPR64common
[%vreg720 -> %W8] GPR32common
[%vreg721 -> %X8] GPR64common
[%vreg725 -> %W9] GPR32common
[%vreg726 -> %W9] GPR32common
[%vreg727 -> %X8] GPR64common
[%vreg730 -> %X9] GPR64common
[%vreg732 -> %W8] GPR32
[%vreg733 -> %X9] GPR64common
[%vreg734 -> %X9] GPR64common
[%vreg736 -> %X10] GPR64
[%vreg737 -> %X8] GPR64
[%vreg738 -> %X8] GPR64common
[%vreg743 -> %X8] GPR64
[%vreg744 -> %X8] GPR64common
[%vreg746 -> %X8] GPR64common
[%vreg750 -> %W8] GPR32common
[%vreg752 -> %X10] GPR64
[%vreg753 -> %X8] GPR64common
[%vreg754 -> %W8] GPR32common
[%vreg755 -> %X8] GPR64
[%vreg757 -> %W9] GPR32
[%vreg758 -> %X9] GPR64common
[%vreg762 -> %W9] GPR32common
[%vreg763 -> %W9] GPR32common
[%vreg764 -> %X8] GPR64common
[%vreg767 -> %W8] GPR32
[%vreg773 -> %W10] GPR32
[%vreg775 -> %W11] GPR32
[%vreg776 -> %W8] GPR32
[%vreg777 -> %W8] GPR32
[%vreg779 -> %W9] GPR32common
[%vreg780 -> %X9] GPR64common
[%vreg784 -> %W10] GPR32common
[%vreg785 -> %W10] GPR32common
[%vreg786 -> %X9] GPR64common
[%vreg790 -> %W8] GPR32
[%vreg791 -> %X8] GPR64common
[%vreg794 -> %W9] GPR32
[%vreg797 -> %W8] GPR32
[%vreg798 -> %X8] GPR64common
[%vreg802 -> %W9] GPR32
[%vreg803 -> %W9] GPR32
[%vreg804 -> %X8] GPR64common
[%vreg807 -> %W8] GPR32common
[%vreg811 -> %W8] GPR32
[%vreg812 -> %X8] GPR64common
[%vreg815 -> %X9] GPR64common
[%vreg817 -> %W8] GPR32
[%vreg820 -> %X10] GPR64
[%vreg821 -> %X8] GPR64
[%vreg822 -> %X8] GPR64common
[%vreg824 -> %X9] GPR64
[%vreg825 -> %X9] GPR64common
[%vreg831 -> %X8] GPR64
[%vreg832 -> %X8] GPR64common
[%vreg833 -> %W9] GPR32
[%vreg835 -> %X8] GPR64common
[%vreg838 -> %W8] GPR32common
[%vreg839 -> %X8] GPR64common
[%vreg843 -> %W9] GPR32common
[%vreg844 -> %W9] GPR32common
[%vreg845 -> %X8] GPR64common
[%vreg848 -> %X9] GPR64common
[%vreg850 -> %W8] GPR32
[%vreg851 -> %X9] GPR64common
[%vreg852 -> %X9] GPR64common
[%vreg854 -> %X10] GPR64
[%vreg855 -> %X8] GPR64
[%vreg856 -> %X8] GPR64common
[%vreg861 -> %X8] GPR64
[%vreg862 -> %X8] GPR64common
[%vreg864 -> %X8] GPR64common
[%vreg868 -> %W8] GPR32common
[%vreg870 -> %X10] GPR64
[%vreg871 -> %X8] GPR64common
[%vreg872 -> %W8] GPR32common
[%vreg873 -> %X8] GPR64
[%vreg875 -> %W9] GPR32
[%vreg876 -> %X9] GPR64common
[%vreg880 -> %W9] GPR32common
[%vreg881 -> %W9] GPR32common
[%vreg882 -> %X8] GPR64common
[%vreg885 -> %W8] GPR32
[%vreg891 -> %W10] GPR32
[%vreg893 -> %W11] GPR32
[%vreg894 -> %W8] GPR32
[%vreg895 -> %W8] GPR32
[%vreg897 -> %W9] GPR32common
[%vreg898 -> %X9] GPR64common
[%vreg902 -> %W10] GPR32common
[%vreg903 -> %W10] GPR32common
[%vreg904 -> %X9] GPR64common
[%vreg908 -> %W8] GPR32
[%vreg909 -> %X8] GPR64common
[%vreg912 -> %W9] GPR32
[%vreg915 -> %W8] GPR32
[%vreg916 -> %X8] GPR64common
[%vreg920 -> %W9] GPR32
[%vreg921 -> %W9] GPR32
[%vreg922 -> %X8] GPR64common
[%vreg925 -> %W8] GPR32common
[%vreg929 -> %W8] GPR32
[%vreg930 -> %X8] GPR64common
[%vreg933 -> %X9] GPR64common
[%vreg935 -> %W8] GPR32
[%vreg938 -> %X10] GPR64
[%vreg939 -> %X8] GPR64
[%vreg940 -> %X8] GPR64common
[%vreg942 -> %X9] GPR64
[%vreg943 -> %X9] GPR64common
[%vreg949 -> %X8] GPR64
[%vreg950 -> %X8] GPR64common
[%vreg953 -> %W8] GPR32common
[%vreg954 -> %X8] GPR64common
[%vreg958 -> %W9] GPR32common
[%vreg959 -> %W9] GPR32common
[%vreg960 -> %X8] GPR64common
[%vreg963 -> %X9] GPR64common
[%vreg965 -> %W8] GPR32
[%vreg966 -> %X9] GPR64common
[%vreg967 -> %X9] GPR64common
[%vreg969 -> %X10] GPR64
[%vreg970 -> %X8] GPR64
[%vreg971 -> %X8] GPR64common
[%vreg976 -> %X8] GPR64
[%vreg977 -> %X8] GPR64common
[%vreg979 -> %X8] GPR64common
[%vreg982 -> %W8] GPR32
[%vreg983 -> %X8] GPR64common
[%vreg987 -> %W9] GPR32
[%vreg988 -> %W9] GPR32
[%vreg989 -> %X8] GPR64common
[%vreg992 -> %X9] GPR64common
[%vreg994 -> %W8] GPR32
[%vreg996 -> %W8] GPR32common
[%vreg1000 -> %W8] GPR32
[%vreg1001 -> %X8] GPR64common
[%vreg1004 -> %X9] GPR64common
[%vreg1006 -> %W8] GPR32
[%vreg1009 -> %X10] GPR64
[%vreg1010 -> %X8] GPR64
[%vreg1011 -> %X8] GPR64common
[%vreg1013 -> %X9] GPR64
[%vreg1014 -> %X9] GPR64common
[%vreg1020 -> %X8] GPR64
[%vreg1021 -> %X8] GPR64common
[%vreg1024 -> %X9] GPR64common
[%vreg1026 -> %W8] GPR32common
[%vreg1029 -> %W8] GPR32common
[%vreg1033 -> %W9] GPR32common
[%vreg1034 -> %W9] GPR32common
[%vreg1035 -> %X8] GPR64common
[%vreg1038 -> %W8] GPR32
[%vreg1044 -> %W10] GPR32
[%vreg1046 -> %W11] GPR32
[%vreg1047 -> %W8] GPR32
[%vreg1048 -> %W8] GPR32
[%vreg1050 -> %W9] GPR32common
[%vreg1051 -> %X9] GPR64common
[%vreg1055 -> %W10] GPR32common
[%vreg1056 -> %W10] GPR32common
[%vreg1057 -> %X9] GPR64common
[%vreg1060 -> %W8] GPR32common
[%vreg1061 -> %X8] GPR64common
[%vreg1065 -> %W9] GPR32common
[%vreg1066 -> %W9] GPR32common
[%vreg1067 -> %X8] GPR64common
[%vreg1070 -> %X9] GPR64common
[%vreg1072 -> %W8] GPR32
[%vreg1073 -> %X9] GPR64common
[%vreg1074 -> %X9] GPR64common
[%vreg1076 -> %X10] GPR64
[%vreg1077 -> %X8] GPR64
[%vreg1078 -> %X8] GPR64common
[%vreg1083 -> %X8] GPR64
[%vreg1084 -> %X8] GPR64common
[%vreg1086 -> %X8] GPR64common
[%vreg1090 -> %W9] GPR32common
[%vreg1091 -> %W9] GPR32common
[%vreg1092 -> %X8] GPR64common
[%vreg1097 -> %W8] GPR32
[%vreg1098 -> %W11] GPR32
[%vreg1099 -> %X10] GPR64common
[%vreg1101 -> %W9] GPR32
[%vreg1102 -> %W8] GPR32
[%vreg1103 -> %W8] GPR32
[%vreg1105 -> %W9] GPR32common
[%vreg1106 -> %X9] GPR64common
[%vreg1110 -> %W10] GPR32common
[%vreg1111 -> %W10] GPR32common
[%vreg1112 -> %X9] GPR64common
[%vreg1115 -> %X9] GPR64common
[%vreg1118 -> %W8] GPR32
[%vreg1121 -> %X9] GPR64common
[%vreg1124 -> %W8] GPR32
[%vreg1127 -> %X9] GPR64common
[%vreg1130 -> %W8] GPR32
[%vreg1131 -> %W8] GPR32
[%vreg1133 -> %X0] GPR64
[%vreg1134 -> %W0] GPR32


Stackmap 0:
  STACKMAP 0, 0, 0, <fi#12>, 0, 0, <fi#3>, 0, 0, <fi#7>, 0, 0, <fi#6>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#9>, 0, 0, <fi#8>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, %vreg1, 0, <fi#1>, 0, 0, <fi#13>, 0, 0, <fi#14>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack12](align=4) LD8[FixedStack3](align=4) LD8[FixedStack7](align=4) LD8[FixedStack6](align=4) LD8[FixedStack4](align=1) LD8[FixedStack5](align=4) LD8[FixedStack9](align=4) LD8[FixedStack8] LD8[FixedStack11](align=4) LD8[FixedStack10] LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1] LD8[FixedStack13](align=4) LD8[FixedStack14](align=4) GPR64:%vreg1

i32* %avail_out_INIT: in stack slot 12 (size: 4)
i32* %c_calculatedBlockCRC: in stack slot 3 (size: 4)
i32* %c_k0: in stack slot 7 (size: 4)
i32* %c_nblock_used: in stack slot 6 (size: 4)
i8* %c_state_out_ch: in stack slot 4 (size: 1)
i32* %c_state_out_len: in stack slot 5 (size: 4)
i32* %c_tPos: in stack slot 9 (size: 4)
i32** %c_tt: in stack slot 8 (size: 8)
i32* %cs_avail_out: in stack slot 11 (size: 4)
i8** %cs_next_out: in stack slot 10 (size: 8)
i8* %k1: in stack slot 2 (size: 1)
i8* %retval: in stack slot 0 (size: 1)
%struct.DState* %s: in register %X20 (vreg 1)
%struct.DState** %s.addr: in stack slot 1 (size: 8)
i32* %s_save_nblockPP: in stack slot 13 (size: 4)
i32* %total_out_lo32_old: in stack slot 14 (size: 4)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=1)

i8* %retval: in stack slot 0 (size: 1)

Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, 0, <fi#12>, 0, 0, <fi#3>, 0, 0, <fi#7>, 0, 0, <fi#6>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#9>, 0, 0, <fi#8>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, %vreg1, 0, <fi#1>, 0, 0, <fi#13>, 0, 0, <fi#14>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack12](align=4) LD8[FixedStack3](align=4) LD8[FixedStack7](align=4) LD8[FixedStack6](align=4) LD8[FixedStack4](align=1) LD8[FixedStack5](align=4) LD8[FixedStack9](align=4) LD8[FixedStack8] LD8[FixedStack11](align=4) LD8[FixedStack10] LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1] LD8[FixedStack13](align=4) LD8[FixedStack14](align=4) GPR64:%vreg1
  -> Call instruction SlotIndex 176B, searching vregs 0 -> 1135 and stack slots 0 -> 15
    + vreg10 is live in register but not in stackmap
      Defining instruction: %vreg10<def> = COPY %LR; GPR64:%vreg10
      Value: generated value, 1 instruction(s)

  STACKMAP 1, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=1)
  -> Call instruction SlotIndex 14272B, searching vregs 0 -> 1135 and stack slots 0 -> 15

********** REWRITE VIRTUAL REGISTERS **********
********** Function: unRLE_obuf_to_output_FAST
********** REGISTER MAP **********
[%vreg1 -> %X20] GPR64
[%vreg3 -> %W8] GPR32
[%vreg5 -> %W8] GPR32
[%vreg6 -> %X8] GPR64common
[%vreg7 -> %X8] GPR64common
[%vreg9 -> %X0] GPR64sp
[%vreg10 -> %X19] GPR64
[%vreg14 -> %W8] GPR32common
[%vreg16 -> %X9] GPR64
[%vreg17 -> %X8] GPR64common
[%vreg18 -> %W8] GPR32common
[%vreg19 -> %X8] GPR64
[%vreg21 -> %W8] GPR32
[%vreg24 -> %W8] GPR32
[%vreg26 -> %X8] GPR64common
[%vreg27 -> %X8] GPR64common
[%vreg30 -> %X8] GPR64
[%vreg32 -> %X8] GPR64common
[%vreg33 -> %X8] GPR64common
[%vreg36 -> %W8] GPR32
[%vreg37 -> %X8] GPR64common
[%vreg40 -> %X8] GPR64
[%vreg41 -> %X8] GPR64common
[%vreg44 -> %W8] GPR32
[%vreg45 -> %X8] GPR64common
[%vreg48 -> %W8] GPR32
[%vreg49 -> %X8] GPR64common
[%vreg52 -> %W8] GPR32
[%vreg53 -> %X8] GPR64common
[%vreg56 -> %W8] GPR32
[%vreg57 -> %X8] GPR64common
[%vreg60 -> %W8] GPR32
[%vreg61 -> %X8] GPR64common
[%vreg63 -> %W8] GPR32common
[%vreg65 -> %W8] GPR32
[%vreg67 -> %W8] GPR32common
[%vreg70 -> %W8] GPR32common
[%vreg71 -> %W8] GPR32common
[%vreg74 -> %X8] GPR64common
[%vreg75 -> %X8] GPR64common
[%vreg78 -> %W8] GPR32common
[%vreg79 -> %W8] GPR32common
[%vreg83 -> %W8] GPR32
[%vreg85 -> %W8] GPR32
[%vreg86 -> %X10] GPR64common
[%vreg87 -> %X10] GPR64common
[%vreg89 -> %X9] GPR64
[%vreg90 -> %X8] GPR64
[%vreg91 -> %X8] GPR64common
[%vreg93 -> %X8] GPR64
[%vreg94 -> %X8] GPR64
[%vreg100 -> %W9] GPR32
[%vreg102 -> %W8] GPR32
[%vreg103 -> %W8] GPR32
[%vreg104 -> %W11] GPR32
[%vreg107 -> %X9] GPR64common
[%vreg108 -> %W8] GPR32
[%vreg110 -> %W8] GPR32
[%vreg113 -> %W8] GPR32common
[%vreg114 -> %W8] GPR32common
[%vreg117 -> %X8] GPR64common
[%vreg118 -> %X8] GPR64common
[%vreg122 -> %W8] GPR32
[%vreg124 -> %W8] GPR32
[%vreg125 -> %X10] GPR64common
[%vreg126 -> %X10] GPR64common
[%vreg128 -> %X9] GPR64
[%vreg129 -> %X8] GPR64
[%vreg130 -> %X8] GPR64common
[%vreg132 -> %X8] GPR64
[%vreg133 -> %X8] GPR64
[%vreg139 -> %W9] GPR32
[%vreg141 -> %W8] GPR32
[%vreg142 -> %W8] GPR32
[%vreg143 -> %W11] GPR32
[%vreg146 -> %X9] GPR64common
[%vreg147 -> %W8] GPR32
[%vreg150 -> %W9] GPR32
[%vreg151 -> %W8] GPR32
[%vreg154 -> %W9] GPR32
[%vreg155 -> %W8] GPR32
[%vreg158 -> %W9] GPR32
[%vreg161 -> %W8] GPR32
[%vreg164 -> %W8] GPR32common
[%vreg165 -> %W8] GPR32common
[%vreg168 -> %W8] GPR32
[%vreg169 -> %W8] GPR32
[%vreg172 -> %W8] GPR32common
[%vreg175 -> %W8] GPR32
[%vreg178 -> %W8] GPR32
[%vreg181 -> %X10] GPR64
[%vreg182 -> %X8] GPR64
[%vreg183 -> %X8] GPR64common
[%vreg184 -> %X9] GPR64
[%vreg189 -> %X8] GPR64
[%vreg192 -> %W8] GPR32
[%vreg196 -> %W9] GPR32
[%vreg197 -> %W8] GPR32
[%vreg200 -> %W9] GPR32
[%vreg201 -> %W8] GPR32
[%vreg204 -> %W8] GPR32common
[%vreg205 -> %W8] GPR32common
[%vreg208 -> %W8] GPR32
[%vreg209 -> %W8] GPR32
[%vreg212 -> %W8] GPR32common
[%vreg215 -> %W8] GPR32
[%vreg218 -> %W8] GPR32
[%vreg221 -> %X10] GPR64
[%vreg222 -> %X8] GPR64
[%vreg223 -> %X8] GPR64common
[%vreg224 -> %X9] GPR64
[%vreg229 -> %X8] GPR64
[%vreg230 -> %W8] GPR32
[%vreg233 -> %W9] GPR32
[%vreg236 -> %W8] GPR32
[%vreg239 -> %W9] GPR32
[%vreg240 -> %W8] GPR32
[%vreg243 -> %W8] GPR32common
[%vreg244 -> %W8] GPR32common
[%vreg247 -> %W8] GPR32
[%vreg248 -> %W8] GPR32
[%vreg251 -> %W8] GPR32common
[%vreg254 -> %W8] GPR32
[%vreg257 -> %W8] GPR32
[%vreg260 -> %X10] GPR64
[%vreg261 -> %X8] GPR64
[%vreg262 -> %X8] GPR64common
[%vreg263 -> %X9] GPR64
[%vreg268 -> %X8] GPR64
[%vreg269 -> %W8] GPR32
[%vreg272 -> %W9] GPR32
[%vreg275 -> %W8] GPR32
[%vreg278 -> %W8] GPR32common
[%vreg279 -> %W8] GPR32common
[%vreg282 -> %W8] GPR32
[%vreg283 -> %W8] GPR32
[%vreg286 -> %W8] GPR32
[%vreg288 -> %W8] GPR32common
[%vreg291 -> %W8] GPR32
[%vreg294 -> %W8] GPR32
[%vreg297 -> %X10] GPR64
[%vreg298 -> %X8] GPR64
[%vreg299 -> %X8] GPR64common
[%vreg300 -> %X9] GPR64
[%vreg305 -> %X8] GPR64
[%vreg308 -> %W8] GPR32common
[%vreg311 -> %W8] GPR32common
[%vreg314 -> %W8] GPR32common
[%vreg315 -> %W8] GPR32common
[%vreg318 -> %W8] GPR32
[%vreg319 -> %W8] GPR32
[%vreg322 -> %W8] GPR32common
[%vreg325 -> %W8] GPR32
[%vreg328 -> %W8] GPR32
[%vreg331 -> %X10] GPR64
[%vreg332 -> %X8] GPR64
[%vreg333 -> %X8] GPR64common
[%vreg334 -> %X9] GPR64
[%vreg339 -> %X8] GPR64
[%vreg343 -> %W8] GPR32
[%vreg347 -> %W8] GPR32
[%vreg351 -> %W8] GPR32
[%vreg352 -> %W8] GPR32
[%vreg353 -> %W8] GPR32
[%vreg356 -> %W9] GPR32
[%vreg358 -> %W8] GPR32
[%vreg360 -> %X8] GPR64common
[%vreg361 -> %X8] GPR64common
[%vreg366 -> %W9] GPR32
[%vreg367 -> %W11] GPR32
[%vreg369 -> %X8] GPR64common
[%vreg370 -> %X8] GPR64common
[%vreg373 -> %W9] GPR32
[%vreg374 -> %W10] GPR32
[%vreg375 -> %W9] GPR32
[%vreg378 -> %W8] GPR32
[%vreg380 -> %X8] GPR64common
[%vreg381 -> %X8] GPR64common
[%vreg385 -> %W9] GPR32common
[%vreg386 -> %W9] GPR32common
[%vreg388 -> %X8] GPR64common
[%vreg389 -> %X8] GPR64common
[%vreg393 -> %X8] GPR64common
[%vreg394 -> %X8] GPR64common
[%vreg395 -> %W9] GPR32
[%vreg399 -> %X8] GPR64common
[%vreg400 -> %X8] GPR64common
[%vreg401 -> %X9] GPR64
[%vreg404 -> %X9] GPR64common
[%vreg405 -> %W8] GPR32
[%vreg408 -> %X9] GPR64common
[%vreg409 -> %X8] GPR64
[%vreg412 -> %X9] GPR64common
[%vreg413 -> %W8] GPR32
[%vreg416 -> %X9] GPR64common
[%vreg417 -> %W8] GPR32
[%vreg420 -> %X9] GPR64common
[%vreg421 -> %W8] GPR32
[%vreg424 -> %X9] GPR64common
[%vreg425 -> %W8] GPR32
[%vreg428 -> %X9] GPR64common
[%vreg429 -> %W8] GPR32
[%vreg432 -> %W8] GPR32
[%vreg434 -> %X8] GPR64common
[%vreg435 -> %X8] GPR64common
[%vreg438 -> %W8] GPR32
[%vreg439 -> %X8] GPR64common
[%vreg442 -> %W8] GPR32
[%vreg444 -> %X8] GPR64common
[%vreg445 -> %X8] GPR64common
[%vreg449 -> %W9] GPR32common
[%vreg450 -> %W9] GPR32common
[%vreg452 -> %X8] GPR64common
[%vreg453 -> %X8] GPR64common
[%vreg457 -> %W9] GPR32common
[%vreg458 -> %W9] GPR32common
[%vreg460 -> %X8] GPR64common
[%vreg461 -> %X8] GPR64common
[%vreg465 -> %X9] GPR64common
[%vreg466 -> %X9] GPR64common
[%vreg468 -> %X8] GPR64common
[%vreg469 -> %X8] GPR64common
[%vreg473 -> %W9] GPR32common
[%vreg474 -> %W9] GPR32common
[%vreg475 -> %X8] GPR64common
[%vreg478 -> %X9] GPR64common
[%vreg481 -> %W8] GPR32
[%vreg483 -> %W8] GPR32
[%vreg484 -> %X10] GPR64common
[%vreg485 -> %X10] GPR64common
[%vreg487 -> %X9] GPR64
[%vreg488 -> %X8] GPR64
[%vreg489 -> %X8] GPR64common
[%vreg491 -> %X8] GPR64
[%vreg492 -> %X8] GPR64
[%vreg499 -> %W9] GPR32
[%vreg500 -> %X9] GPR64common
[%vreg502 -> %W8] GPR32
[%vreg504 -> %W8] GPR32
[%vreg505 -> %X8] GPR64common
[%vreg507 -> %W11] GPR32
[%vreg508 -> %X11] GPR64common
[%vreg512 -> %X8] GPR64common
[%vreg514 -> %X8] GPR64common
[%vreg515 -> %X8] GPR64common
[%vreg517 -> %W9] GPR32
[%vreg518 -> %X9] GPR64common
[%vreg522 -> %W9] GPR32common
[%vreg523 -> %W9] GPR32common
[%vreg525 -> %X8] GPR64common
[%vreg526 -> %X8] GPR64common
[%vreg530 -> %W8] GPR32common
[%vreg532 -> %X10] GPR64
[%vreg533 -> %X8] GPR64common
[%vreg534 -> %W8] GPR32common
[%vreg535 -> %X8] GPR64
[%vreg537 -> %W9] GPR32
[%vreg538 -> %X9] GPR64common
[%vreg542 -> %W8] GPR32common
[%vreg544 -> %X10] GPR64
[%vreg545 -> %X8] GPR64common
[%vreg546 -> %W8] GPR32common
[%vreg547 -> %X8] GPR64
[%vreg549 -> %W9] GPR32
[%vreg550 -> %X9] GPR64common
[%vreg553 -> %W8] GPR32
[%vreg554 -> %X8] GPR64common
[%vreg558 -> %W9] GPR32
[%vreg559 -> %W9] GPR32
[%vreg560 -> %X8] GPR64common
[%vreg563 -> %W8] GPR32common
[%vreg567 -> %W8] GPR32
[%vreg568 -> %X8] GPR64common
[%vreg571 -> %X9] GPR64common
[%vreg573 -> %W8] GPR32
[%vreg576 -> %X10] GPR64
[%vreg577 -> %X8] GPR64
[%vreg578 -> %X8] GPR64common
[%vreg580 -> %X9] GPR64
[%vreg581 -> %X9] GPR64common
[%vreg587 -> %X8] GPR64
[%vreg588 -> %X8] GPR64common
[%vreg591 -> %X9] GPR64common
[%vreg593 -> %W8] GPR32
[%vreg596 -> %X8] GPR64common
[%vreg597 -> %W9] GPR32
[%vreg599 -> %X8] GPR64common
[%vreg602 -> %W8] GPR32common
[%vreg603 -> %X8] GPR64common
[%vreg607 -> %W9] GPR32common
[%vreg608 -> %W9] GPR32common
[%vreg609 -> %X8] GPR64common
[%vreg612 -> %X9] GPR64common
[%vreg614 -> %W8] GPR32
[%vreg615 -> %X9] GPR64common
[%vreg616 -> %X9] GPR64common
[%vreg618 -> %X10] GPR64
[%vreg619 -> %X8] GPR64
[%vreg620 -> %X8] GPR64common
[%vreg625 -> %X8] GPR64
[%vreg626 -> %X8] GPR64common
[%vreg628 -> %X8] GPR64common
[%vreg632 -> %W8] GPR32common
[%vreg634 -> %X10] GPR64
[%vreg635 -> %X8] GPR64common
[%vreg636 -> %W8] GPR32common
[%vreg637 -> %X8] GPR64
[%vreg639 -> %W9] GPR32
[%vreg640 -> %X9] GPR64common
[%vreg644 -> %W9] GPR32common
[%vreg645 -> %W9] GPR32common
[%vreg646 -> %X8] GPR64common
[%vreg649 -> %W8] GPR32
[%vreg655 -> %W10] GPR32
[%vreg657 -> %W11] GPR32
[%vreg658 -> %W8] GPR32
[%vreg659 -> %W8] GPR32
[%vreg661 -> %W9] GPR32common
[%vreg662 -> %X9] GPR64common
[%vreg666 -> %W10] GPR32common
[%vreg667 -> %W10] GPR32common
[%vreg668 -> %X9] GPR64common
[%vreg672 -> %W8] GPR32
[%vreg673 -> %X8] GPR64common
[%vreg676 -> %W9] GPR32
[%vreg679 -> %W8] GPR32
[%vreg680 -> %X8] GPR64common
[%vreg684 -> %W9] GPR32
[%vreg685 -> %W9] GPR32
[%vreg686 -> %X8] GPR64common
[%vreg689 -> %W8] GPR32common
[%vreg693 -> %W8] GPR32
[%vreg694 -> %X8] GPR64common
[%vreg697 -> %X9] GPR64common
[%vreg699 -> %W8] GPR32
[%vreg702 -> %X10] GPR64
[%vreg703 -> %X8] GPR64
[%vreg704 -> %X8] GPR64common
[%vreg706 -> %X9] GPR64
[%vreg707 -> %X9] GPR64common
[%vreg713 -> %X8] GPR64
[%vreg714 -> %X8] GPR64common
[%vreg715 -> %W9] GPR32
[%vreg717 -> %X8] GPR64common
[%vreg720 -> %W8] GPR32common
[%vreg721 -> %X8] GPR64common
[%vreg725 -> %W9] GPR32common
[%vreg726 -> %W9] GPR32common
[%vreg727 -> %X8] GPR64common
[%vreg730 -> %X9] GPR64common
[%vreg732 -> %W8] GPR32
[%vreg733 -> %X9] GPR64common
[%vreg734 -> %X9] GPR64common
[%vreg736 -> %X10] GPR64
[%vreg737 -> %X8] GPR64
[%vreg738 -> %X8] GPR64common
[%vreg743 -> %X8] GPR64
[%vreg744 -> %X8] GPR64common
[%vreg746 -> %X8] GPR64common
[%vreg750 -> %W8] GPR32common
[%vreg752 -> %X10] GPR64
[%vreg753 -> %X8] GPR64common
[%vreg754 -> %W8] GPR32common
[%vreg755 -> %X8] GPR64
[%vreg757 -> %W9] GPR32
[%vreg758 -> %X9] GPR64common
[%vreg762 -> %W9] GPR32common
[%vreg763 -> %W9] GPR32common
[%vreg764 -> %X8] GPR64common
[%vreg767 -> %W8] GPR32
[%vreg773 -> %W10] GPR32
[%vreg775 -> %W11] GPR32
[%vreg776 -> %W8] GPR32
[%vreg777 -> %W8] GPR32
[%vreg779 -> %W9] GPR32common
[%vreg780 -> %X9] GPR64common
[%vreg784 -> %W10] GPR32common
[%vreg785 -> %W10] GPR32common
[%vreg786 -> %X9] GPR64common
[%vreg790 -> %W8] GPR32
[%vreg791 -> %X8] GPR64common
[%vreg794 -> %W9] GPR32
[%vreg797 -> %W8] GPR32
[%vreg798 -> %X8] GPR64common
[%vreg802 -> %W9] GPR32
[%vreg803 -> %W9] GPR32
[%vreg804 -> %X8] GPR64common
[%vreg807 -> %W8] GPR32common
[%vreg811 -> %W8] GPR32
[%vreg812 -> %X8] GPR64common
[%vreg815 -> %X9] GPR64common
[%vreg817 -> %W8] GPR32
[%vreg820 -> %X10] GPR64
[%vreg821 -> %X8] GPR64
[%vreg822 -> %X8] GPR64common
[%vreg824 -> %X9] GPR64
[%vreg825 -> %X9] GPR64common
[%vreg831 -> %X8] GPR64
[%vreg832 -> %X8] GPR64common
[%vreg833 -> %W9] GPR32
[%vreg835 -> %X8] GPR64common
[%vreg838 -> %W8] GPR32common
[%vreg839 -> %X8] GPR64common
[%vreg843 -> %W9] GPR32common
[%vreg844 -> %W9] GPR32common
[%vreg845 -> %X8] GPR64common
[%vreg848 -> %X9] GPR64common
[%vreg850 -> %W8] GPR32
[%vreg851 -> %X9] GPR64common
[%vreg852 -> %X9] GPR64common
[%vreg854 -> %X10] GPR64
[%vreg855 -> %X8] GPR64
[%vreg856 -> %X8] GPR64common
[%vreg861 -> %X8] GPR64
[%vreg862 -> %X8] GPR64common
[%vreg864 -> %X8] GPR64common
[%vreg868 -> %W8] GPR32common
[%vreg870 -> %X10] GPR64
[%vreg871 -> %X8] GPR64common
[%vreg872 -> %W8] GPR32common
[%vreg873 -> %X8] GPR64
[%vreg875 -> %W9] GPR32
[%vreg876 -> %X9] GPR64common
[%vreg880 -> %W9] GPR32common
[%vreg881 -> %W9] GPR32common
[%vreg882 -> %X8] GPR64common
[%vreg885 -> %W8] GPR32
[%vreg891 -> %W10] GPR32
[%vreg893 -> %W11] GPR32
[%vreg894 -> %W8] GPR32
[%vreg895 -> %W8] GPR32
[%vreg897 -> %W9] GPR32common
[%vreg898 -> %X9] GPR64common
[%vreg902 -> %W10] GPR32common
[%vreg903 -> %W10] GPR32common
[%vreg904 -> %X9] GPR64common
[%vreg908 -> %W8] GPR32
[%vreg909 -> %X8] GPR64common
[%vreg912 -> %W9] GPR32
[%vreg915 -> %W8] GPR32
[%vreg916 -> %X8] GPR64common
[%vreg920 -> %W9] GPR32
[%vreg921 -> %W9] GPR32
[%vreg922 -> %X8] GPR64common
[%vreg925 -> %W8] GPR32common
[%vreg929 -> %W8] GPR32
[%vreg930 -> %X8] GPR64common
[%vreg933 -> %X9] GPR64common
[%vreg935 -> %W8] GPR32
[%vreg938 -> %X10] GPR64
[%vreg939 -> %X8] GPR64
[%vreg940 -> %X8] GPR64common
[%vreg942 -> %X9] GPR64
[%vreg943 -> %X9] GPR64common
[%vreg949 -> %X8] GPR64
[%vreg950 -> %X8] GPR64common
[%vreg953 -> %W8] GPR32common
[%vreg954 -> %X8] GPR64common
[%vreg958 -> %W9] GPR32common
[%vreg959 -> %W9] GPR32common
[%vreg960 -> %X8] GPR64common
[%vreg963 -> %X9] GPR64common
[%vreg965 -> %W8] GPR32
[%vreg966 -> %X9] GPR64common
[%vreg967 -> %X9] GPR64common
[%vreg969 -> %X10] GPR64
[%vreg970 -> %X8] GPR64
[%vreg971 -> %X8] GPR64common
[%vreg976 -> %X8] GPR64
[%vreg977 -> %X8] GPR64common
[%vreg979 -> %X8] GPR64common
[%vreg982 -> %W8] GPR32
[%vreg983 -> %X8] GPR64common
[%vreg987 -> %W9] GPR32
[%vreg988 -> %W9] GPR32
[%vreg989 -> %X8] GPR64common
[%vreg992 -> %X9] GPR64common
[%vreg994 -> %W8] GPR32
[%vreg996 -> %W8] GPR32common
[%vreg1000 -> %W8] GPR32
[%vreg1001 -> %X8] GPR64common
[%vreg1004 -> %X9] GPR64common
[%vreg1006 -> %W8] GPR32
[%vreg1009 -> %X10] GPR64
[%vreg1010 -> %X8] GPR64
[%vreg1011 -> %X8] GPR64common
[%vreg1013 -> %X9] GPR64
[%vreg1014 -> %X9] GPR64common
[%vreg1020 -> %X8] GPR64
[%vreg1021 -> %X8] GPR64common
[%vreg1024 -> %X9] GPR64common
[%vreg1026 -> %W8] GPR32common
[%vreg1029 -> %W8] GPR32common
[%vreg1033 -> %W9] GPR32common
[%vreg1034 -> %W9] GPR32common
[%vreg1035 -> %X8] GPR64common
[%vreg1038 -> %W8] GPR32
[%vreg1044 -> %W10] GPR32
[%vreg1046 -> %W11] GPR32
[%vreg1047 -> %W8] GPR32
[%vreg1048 -> %W8] GPR32
[%vreg1050 -> %W9] GPR32common
[%vreg1051 -> %X9] GPR64common
[%vreg1055 -> %W10] GPR32common
[%vreg1056 -> %W10] GPR32common
[%vreg1057 -> %X9] GPR64common
[%vreg1060 -> %W8] GPR32common
[%vreg1061 -> %X8] GPR64common
[%vreg1065 -> %W9] GPR32common
[%vreg1066 -> %W9] GPR32common
[%vreg1067 -> %X8] GPR64common
[%vreg1070 -> %X9] GPR64common
[%vreg1072 -> %W8] GPR32
[%vreg1073 -> %X9] GPR64common
[%vreg1074 -> %X9] GPR64common
[%vreg1076 -> %X10] GPR64
[%vreg1077 -> %X8] GPR64
[%vreg1078 -> %X8] GPR64common
[%vreg1083 -> %X8] GPR64
[%vreg1084 -> %X8] GPR64common
[%vreg1086 -> %X8] GPR64common
[%vreg1090 -> %W9] GPR32common
[%vreg1091 -> %W9] GPR32common
[%vreg1092 -> %X8] GPR64common
[%vreg1097 -> %W8] GPR32
[%vreg1098 -> %W11] GPR32
[%vreg1099 -> %X10] GPR64common
[%vreg1101 -> %W9] GPR32
[%vreg1102 -> %W8] GPR32
[%vreg1103 -> %W8] GPR32
[%vreg1105 -> %W9] GPR32common
[%vreg1106 -> %X9] GPR64common
[%vreg1110 -> %W10] GPR32common
[%vreg1111 -> %W10] GPR32common
[%vreg1112 -> %X9] GPR64common
[%vreg1115 -> %X9] GPR64common
[%vreg1118 -> %W8] GPR32
[%vreg1121 -> %X9] GPR64common
[%vreg1124 -> %W8] GPR32
[%vreg1127 -> %X9] GPR64common
[%vreg1130 -> %W8] GPR32
[%vreg1131 -> %W8] GPR32
[%vreg1133 -> %X0] GPR64
[%vreg1134 -> %W0] GPR32

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %LR %X0
16B		%vreg10<def> = COPY %LR; GPR64:%vreg10
32B		%vreg1<def> = COPY %X0; GPR64:%vreg1
64B		%vreg7<def> = ADRP <ga:@unRLE_obuf_to_output_FAST>[TF=1]; GPR64common:%vreg7
80B		%vreg9<def> = ADDXri %vreg7<kill>, <ga:@unRLE_obuf_to_output_FAST>[TF=34], 0; GPR64sp:%vreg9 GPR64common:%vreg7
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		%X0<def> = COPY %vreg9<kill>; GPR64sp:%vreg9
160B		%X1<def> = COPY %vreg10; GPR64:%vreg10
176B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
224B		STACKMAP 0, 0, 0, <fi#12>, 0, 0, <fi#3>, 0, 0, <fi#7>, 0, 0, <fi#6>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#9>, 0, 0, <fi#8>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, %vreg1, 0, <fi#1>, 0, 0, <fi#13>, 0, 0, <fi#14>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack12](align=4) LD8[FixedStack3](align=4) LD8[FixedStack7](align=4) LD8[FixedStack6](align=4) LD8[FixedStack4](align=1) LD8[FixedStack5](align=4) LD8[FixedStack9](align=4) LD8[FixedStack8] LD8[FixedStack11](align=4) LD8[FixedStack10] LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1] LD8[FixedStack13](align=4) LD8[FixedStack14](align=4) GPR64:%vreg1
240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
256B		STRXui %vreg1<kill>, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg1
272B		%vreg6<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg6
288B		%vreg5<def> = LDRBBui %vreg6<kill>, 20; mem:LD1[%blockRandomised] GPR32:%vreg5 GPR64common:%vreg6
304B		%vreg3<def> = UBFMWri %vreg5<kill>, 0, 7; GPR32:%vreg3,%vreg5
320B		CBZW %vreg3<kill>, <BB#47>; GPR32:%vreg3
	    Successors according to CFG: BB#47 BB#1
> %X19<def> = COPY %LR
> %X20<def> = COPY %X0
> %X8<def> = ADRP <ga:@unRLE_obuf_to_output_FAST>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@unRLE_obuf_to_output_FAST>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19
> BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 0, 0, 0, <fi#12>, 0, 0, <fi#3>, 0, 0, <fi#7>, 0, 0, <fi#6>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#9>, 0, 0, <fi#8>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, %X20, 0, <fi#1>, 0, 0, <fi#13>, 0, 0, <fi#14>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack12](align=4) LD8[FixedStack3](align=4) LD8[FixedStack7](align=4) LD8[FixedStack6](align=4) LD8[FixedStack4](align=1) LD8[FixedStack5](align=4) LD8[FixedStack9](align=4) LD8[FixedStack8] LD8[FixedStack11](align=4) LD8[FixedStack10] LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1] LD8[FixedStack13](align=4) LD8[FixedStack14](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRXui %X20<kill>, <fi#1>, 0; mem:ST8[FixedStack1]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W8<def> = LDRBBui %X8<kill>, 20; mem:LD1[%blockRandomised]
> %W8<def> = UBFMWri %W8<kill>, 0, 7
> CBZW %W8<kill>, <BB#47>
336B	BB#1: derived from LLVM BB %if.then
	    Live Ins: %X19
	    Predecessors according to CFG: BB#0
352B		B <BB#2>
	    Successors according to CFG: BB#2
> B <BB#2>
368B	BB#2: derived from LLVM BB %while.body
	    Live Ins: %X19
	    Predecessors according to CFG: BB#1 BB#46 BB#37 BB#35 BB#29 BB#27 BB#21 BB#19
384B		B <BB#3>
	    Successors according to CFG: BB#3
> B <BB#3>
400B	BB#3: derived from LLVM BB %while.body.2
	    Live Ins: %X19
	    Predecessors according to CFG: BB#2 BB#9
416B		%vreg435<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg435
432B		%vreg434<def> = LDRXui %vreg435<kill>, 0; mem:LD8[%strm] GPR64common:%vreg434,%vreg435
448B		%vreg432<def> = LDRWui %vreg434<kill>, 8; mem:LD4[%avail_out] GPR32:%vreg432 GPR64common:%vreg434
464B		CBNZW %vreg432<kill>, <BB#5>; GPR32:%vreg432
	    Successors according to CFG: BB#5 BB#4
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X8<def> = LDRXui %X8<kill>, 0; mem:LD8[%strm]
> %W8<def> = LDRWui %X8<kill>, 8; mem:LD4[%avail_out]
> CBNZW %W8<kill>, <BB#5>
480B	BB#4: derived from LLVM BB %if.then.3
	    Live Ins: %X19
	    Predecessors according to CFG: BB#3
496B		STRBBui %WZR, <fi#0>, 0; mem:ST1[FixedStack0]
512B		B <BB#80>
	    Successors according to CFG: BB#80
> STRBBui %WZR, <fi#0>, 0; mem:ST1[FixedStack0]
> B <BB#80>
528B	BB#5: derived from LLVM BB %if.end
	    Live Ins: %X19
	    Predecessors according to CFG: BB#3
544B		%vreg439<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg439
560B		%vreg438<def> = LDRWui %vreg439<kill>, 4; mem:LD4[%state_out_len] GPR32:%vreg438 GPR64common:%vreg439
576B		CBNZW %vreg438<kill>, <BB#7>; GPR32:%vreg438
	    Successors according to CFG: BB#7 BB#6
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W8<def> = LDRWui %X8<kill>, 4; mem:LD4[%state_out_len]
> CBNZW %W8<kill>, <BB#7>
592B	BB#6: derived from LLVM BB %if.then.5
	    Live Ins: %X19
	    Predecessors according to CFG: BB#5
608B		B <BB#10>
	    Successors according to CFG: BB#10
> B <BB#10>
624B	BB#7: derived from LLVM BB %if.end.6
	    Live Ins: %X19
	    Predecessors according to CFG: BB#5
704B		%vreg515<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg515
712B		%vreg518<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg518
720B		%vreg514<def> = LDRXui %vreg515<kill>, 0; mem:LD8[%strm7] GPR64common:%vreg514,%vreg515
728B		%vreg517<def> = LDRBBui %vreg518<kill>, 12; mem:LD1[%state_out_ch] GPR32:%vreg517 GPR64common:%vreg518
736B		%vreg512<def> = LDRXui %vreg514<kill>, 3; mem:LD8[%next_out] GPR64common:%vreg512,%vreg514
752B		STRBBui %vreg517<kill>, %vreg512<kill>, 0; mem:ST1[%11] GPR32:%vreg517 GPR64common:%vreg512
800B		%vreg505<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg505
848B		%vreg500<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg500
856B		%vreg484<def> = ADRP <ga:@BZ2_crc32Table>[TF=1]; GPR64common:%vreg484
864B		%vreg508<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg508
872B		%vreg504<def> = LDRWui %vreg505<kill>, 796; mem:LD4[%calculatedBlockCRC8] GPR32:%vreg504 GPR64common:%vreg505
880B		%vreg499<def> = LDRBBui %vreg500<kill>, 12; mem:LD1[%state_out_ch9] GPR32:%vreg499 GPR64common:%vreg500
888B		%vreg485<def> = ADDXri %vreg484<kill>, <ga:@BZ2_crc32Table>[TF=34], 0; GPR64common:%vreg485,%vreg484
896B		%vreg507<def> = LDRWui %vreg508<kill>, 796; mem:LD4[%calculatedBlockCRC] GPR32:%vreg507 GPR64common:%vreg508
904B		%vreg502<def> = UBFMWri %vreg504<kill>, 24, 31; GPR32:%vreg502,%vreg504
912B		%vreg491:sub_32<def,read-undef> = EORWrr %vreg502<kill>, %vreg499<kill>; GPR64:%vreg491 GPR32:%vreg502,%vreg499
928B		%vreg492<def> = UBFMXri %vreg491<kill>, 0, 31; GPR64:%vreg492,%vreg491
936B		%vreg487<def> = MOVi64imm 4; GPR64:%vreg487
944B		%vreg488<def> = MADDXrrr %vreg492<kill>, %vreg487<kill>, %XZR; GPR64:%vreg488,%vreg492,%vreg487
960B		%vreg489<def> = ADDXrr %vreg485<kill>, %vreg488<kill>; GPR64common:%vreg489,%vreg485 GPR64:%vreg488
976B		%vreg483<def> = LDRWui %vreg489<kill>, 0; mem:LD4[%arrayidx] GPR32:%vreg483 GPR64common:%vreg489
1008B		%vreg478<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg478
1016B		%vreg481<def> = EORWrs %vreg483<kill>, %vreg507<kill>, 8; GPR32:%vreg481,%vreg483,%vreg507
1024B		STRWui %vreg481<kill>, %vreg478<kill>, 796; mem:ST4[%calculatedBlockCRC11] GPR32:%vreg481 GPR64common:%vreg478
1040B		%vreg475<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg475
1056B		%vreg474<def> = LDRWui %vreg475, 4; mem:LD4[%state_out_len12] GPR32common:%vreg474 GPR64common:%vreg475
1072B		%vreg473<def> = SUBWri %vreg474<kill>, 1, 0; GPR32common:%vreg473,%vreg474
1088B		STRWui %vreg473<kill>, %vreg475<kill>, 4; mem:ST4[%state_out_len12] GPR32common:%vreg473 GPR64common:%vreg475
1104B		%vreg469<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg469
1120B		%vreg468<def> = LDRXui %vreg469<kill>, 0; mem:LD8[%strm13] GPR64common:%vreg468,%vreg469
1136B		%vreg466<def> = LDRXui %vreg468, 3; mem:LD8[%next_out14] GPR64common:%vreg466,%vreg468
1152B		%vreg465<def> = ADDXri %vreg466<kill>, 1, 0; GPR64common:%vreg465,%vreg466
1168B		STRXui %vreg465<kill>, %vreg468<kill>, 3; mem:ST8[%next_out14] GPR64common:%vreg465,%vreg468
1184B		%vreg461<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg461
1200B		%vreg460<def> = LDRXui %vreg461<kill>, 0; mem:LD8[%strm15] GPR64common:%vreg460,%vreg461
1216B		%vreg458<def> = LDRWui %vreg460, 8; mem:LD4[%avail_out16] GPR32common:%vreg458 GPR64common:%vreg460
1232B		%vreg457<def> = SUBWri %vreg458<kill>, 1, 0; GPR32common:%vreg457,%vreg458
1248B		STRWui %vreg457<kill>, %vreg460<kill>, 8; mem:ST4[%avail_out16] GPR32common:%vreg457 GPR64common:%vreg460
1264B		%vreg453<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg453
1280B		%vreg452<def> = LDRXui %vreg453<kill>, 0; mem:LD8[%strm18] GPR64common:%vreg452,%vreg453
1296B		%vreg450<def> = LDRWui %vreg452, 9; mem:LD4[%total_out_lo32] GPR32common:%vreg450 GPR64common:%vreg452
1312B		%vreg449<def> = ADDWri %vreg450<kill>, 1, 0; GPR32common:%vreg449,%vreg450
1328B		STRWui %vreg449<kill>, %vreg452<kill>, 9; mem:ST4[%total_out_lo32] GPR32common:%vreg449 GPR64common:%vreg452
1344B		%vreg445<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg445
1360B		%vreg444<def> = LDRXui %vreg445<kill>, 0; mem:LD8[%strm19] GPR64common:%vreg444,%vreg445
1376B		%vreg442<def> = LDRWui %vreg444<kill>, 9; mem:LD4[%total_out_lo3220] GPR32:%vreg442 GPR64common:%vreg444
1392B		CBNZW %vreg442<kill>, <BB#9>; GPR32:%vreg442
	    Successors according to CFG: BB#9 BB#8
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X8<def> = LDRXui %X8<kill>, 0; mem:LD8[%strm7]
> %W9<def> = LDRBBui %X9<kill>, 12; mem:LD1[%state_out_ch]
> %X8<def> = LDRXui %X8<kill>, 3; mem:LD8[%next_out]
> STRBBui %W9<kill>, %X8<kill>, 0; mem:ST1[%11]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X10<def> = ADRP <ga:@BZ2_crc32Table>[TF=1]
> %X11<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W8<def> = LDRWui %X8<kill>, 796; mem:LD4[%calculatedBlockCRC8]
> %W9<def> = LDRBBui %X9<kill>, 12; mem:LD1[%state_out_ch9]
> %X10<def> = ADDXri %X10<kill>, <ga:@BZ2_crc32Table>[TF=34], 0
> %W11<def> = LDRWui %X11<kill>, 796; mem:LD4[%calculatedBlockCRC]
> %W8<def> = UBFMWri %W8<kill>, 24, 31
> %W8<def> = EORWrr %W8<kill>, %W9<kill>, %X8<imp-def>
> %X8<def> = UBFMXri %X8<kill>, 0, 31
> %X9<def> = MOVi64imm 4
> %X8<def> = MADDXrrr %X8<kill>, %X9<kill>, %XZR
> %X8<def> = ADDXrr %X10<kill>, %X8<kill>
> %W8<def> = LDRWui %X8<kill>, 0; mem:LD4[%arrayidx]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W8<def> = EORWrs %W8<kill>, %W11<kill>, 8
> STRWui %W8<kill>, %X9<kill>, 796; mem:ST4[%calculatedBlockCRC11]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = LDRWui %X8, 4; mem:LD4[%state_out_len12]
> %W9<def> = SUBWri %W9<kill>, 1, 0
> STRWui %W9<kill>, %X8<kill>, 4; mem:ST4[%state_out_len12]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X8<def> = LDRXui %X8<kill>, 0; mem:LD8[%strm13]
> %X9<def> = LDRXui %X8, 3; mem:LD8[%next_out14]
> %X9<def> = ADDXri %X9<kill>, 1, 0
> STRXui %X9<kill>, %X8<kill>, 3; mem:ST8[%next_out14]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X8<def> = LDRXui %X8<kill>, 0; mem:LD8[%strm15]
> %W9<def> = LDRWui %X8, 8; mem:LD4[%avail_out16]
> %W9<def> = SUBWri %W9<kill>, 1, 0
> STRWui %W9<kill>, %X8<kill>, 8; mem:ST4[%avail_out16]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X8<def> = LDRXui %X8<kill>, 0; mem:LD8[%strm18]
> %W9<def> = LDRWui %X8, 9; mem:LD4[%total_out_lo32]
> %W9<def> = ADDWri %W9<kill>, 1, 0
> STRWui %W9<kill>, %X8<kill>, 9; mem:ST4[%total_out_lo32]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X8<def> = LDRXui %X8<kill>, 0; mem:LD8[%strm19]
> %W8<def> = LDRWui %X8<kill>, 9; mem:LD4[%total_out_lo3220]
> CBNZW %W8<kill>, <BB#9>
1408B	BB#8: derived from LLVM BB %if.then.23
	    Live Ins: %X19
	    Predecessors according to CFG: BB#7
1424B		%vreg526<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg526
1440B		%vreg525<def> = LDRXui %vreg526<kill>, 0; mem:LD8[%strm24] GPR64common:%vreg525,%vreg526
1456B		%vreg523<def> = LDRWui %vreg525, 10; mem:LD4[%total_out_hi32] GPR32common:%vreg523 GPR64common:%vreg525
1472B		%vreg522<def> = ADDWri %vreg523<kill>, 1, 0; GPR32common:%vreg522,%vreg523
1488B		STRWui %vreg522<kill>, %vreg525<kill>, 10; mem:ST4[%total_out_hi32] GPR32common:%vreg522 GPR64common:%vreg525
	    Successors according to CFG: BB#9
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X8<def> = LDRXui %X8<kill>, 0; mem:LD8[%strm24]
> %W9<def> = LDRWui %X8, 10; mem:LD4[%total_out_hi32]
> %W9<def> = ADDWri %W9<kill>, 1, 0
> STRWui %W9<kill>, %X8<kill>, 10; mem:ST4[%total_out_hi32]
1504B	BB#9: derived from LLVM BB %if.end.26
	    Live Ins: %X19
	    Predecessors according to CFG: BB#7 BB#8
1520B		B <BB#3>
	    Successors according to CFG: BB#3
> B <BB#3>
1536B	BB#10: derived from LLVM BB %while.end
	    Live Ins: %X19
	    Predecessors according to CFG: BB#6
1584B		%vreg535<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg535
1592B		%vreg538<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg538
1600B		%vreg532<def> = MOVi64imm 64080; GPR64:%vreg532
1616B		%vreg533<def> = ADDXrr %vreg535<kill>, %vreg532<kill>; GPR64common:%vreg533 GPR64:%vreg535,%vreg532
1632B		%vreg534<def> = LDRWui %vreg533<kill>, 0; mem:LD4[%save_nblock] GPR32common:%vreg534 GPR64common:%vreg533
1640B		%vreg537<def> = LDRWui %vreg538<kill>, 273; mem:LD4[%nblock_used] GPR32:%vreg537 GPR64common:%vreg538
1648B		%vreg530<def> = ADDWri %vreg534<kill>, 1, 0; GPR32common:%vreg530,%vreg534
1664B		%WZR<def> = SUBSWrr %vreg537<kill>, %vreg530<kill>, %NZCV<imp-def>; GPR32:%vreg537 GPR32common:%vreg530
1680B		Bcc 1, <BB#12>, %NZCV<imp-use>
	    Successors according to CFG: BB#12 BB#11
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X10<def> = MOVi64imm 64080
> %X8<def> = ADDXrr %X8<kill>, %X10<kill>
> %W8<def> = LDRWui %X8<kill>, 0; mem:LD4[%save_nblock]
> %W9<def> = LDRWui %X9<kill>, 273; mem:LD4[%nblock_used]
> %W8<def> = ADDWri %W8<kill>, 1, 0
> %WZR<def> = SUBSWrr %W9<kill>, %W8<kill>, %NZCV<imp-def>
> Bcc 1, <BB#12>, %NZCV<imp-use>
1696B	BB#11: derived from LLVM BB %if.then.29
	    Live Ins: %X19
	    Predecessors according to CFG: BB#10
1712B		STRBBui %WZR, <fi#0>, 0; mem:ST1[FixedStack0]
1728B		B <BB#80>
	    Successors according to CFG: BB#80
> STRBBui %WZR, <fi#0>, 0; mem:ST1[FixedStack0]
> B <BB#80>
1744B	BB#12: derived from LLVM BB %if.end.30
	    Live Ins: %X19
	    Predecessors according to CFG: BB#10
1792B		%vreg547<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg547
1800B		%vreg550<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg550
1808B		%vreg544<def> = MOVi64imm 64080; GPR64:%vreg544
1824B		%vreg545<def> = ADDXrr %vreg547<kill>, %vreg544<kill>; GPR64common:%vreg545 GPR64:%vreg547,%vreg544
1840B		%vreg546<def> = LDRWui %vreg545<kill>, 0; mem:LD4[%save_nblock32] GPR32common:%vreg546 GPR64common:%vreg545
1848B		%vreg549<def> = LDRWui %vreg550<kill>, 273; mem:LD4[%nblock_used31] GPR32:%vreg549 GPR64common:%vreg550
1856B		%vreg542<def> = ADDWri %vreg546<kill>, 1, 0; GPR32common:%vreg542,%vreg546
1872B		%WZR<def> = SUBSWrr %vreg549<kill>, %vreg542<kill>, %NZCV<imp-def>; GPR32:%vreg549 GPR32common:%vreg542
1888B		Bcc 13, <BB#14>, %NZCV<imp-use>
	    Successors according to CFG: BB#14 BB#13
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X10<def> = MOVi64imm 64080
> %X8<def> = ADDXrr %X8<kill>, %X10<kill>
> %W8<def> = LDRWui %X8<kill>, 0; mem:LD4[%save_nblock32]
> %W9<def> = LDRWui %X9<kill>, 273; mem:LD4[%nblock_used31]
> %W8<def> = ADDWri %W8<kill>, 1, 0
> %WZR<def> = SUBSWrr %W9<kill>, %W8<kill>, %NZCV<imp-def>
> Bcc 13, <BB#14>, %NZCV<imp-use>
1904B	BB#13: derived from LLVM BB %if.then.36
	    Live Ins: %X19
	    Predecessors according to CFG: BB#12
1920B		%vreg1131<def> = MOVi32imm 1; GPR32:%vreg1131
1936B		STRBBui %vreg1131<kill>, <fi#0>, 0; mem:ST1[FixedStack0] GPR32:%vreg1131
1952B		B <BB#80>
	    Successors according to CFG: BB#80
> %W8<def> = MOVi32imm 1
> STRBBui %W8<kill>, <fi#0>, 0; mem:ST1[FixedStack0]
> B <BB#80>
1968B	BB#14: derived from LLVM BB %if.end.37
	    Live Ins: %X19
	    Predecessors according to CFG: BB#12
2000B		%vreg599<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg599
2008B		%vreg597<def> = MOVi32imm 1; GPR32:%vreg597
2016B		STRWui %vreg597<kill>, %vreg599<kill>, 4; mem:ST4[%state_out_len38] GPR32:%vreg597 GPR64common:%vreg599
2032B		%vreg596<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg596
2080B		%vreg591<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg591
2088B		%vreg593<def> = LDRWui %vreg596<kill>, 16; mem:LD4[%k0] GPR32:%vreg593 GPR64common:%vreg596
2096B		STRBBui %vreg593<kill>, %vreg591<kill>, 12; mem:ST1[%state_out_ch40] GPR32:%vreg593 GPR64common:%vreg591
2112B		%vreg588<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg588
2160B		%vreg581<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg581
2168B		%vreg587:sub_32<def,read-undef> = LDRWui %vreg588<kill>, 15; mem:LD4[%tPos] GPR64:%vreg587 GPR64common:%vreg588
2176B		%vreg580<def> = LDRXui %vreg581<kill>, 394; mem:LD8[%tt] GPR64:%vreg580 GPR64common:%vreg581
2192B		%vreg576<def> = MOVi64imm 4; GPR64:%vreg576
2208B		%vreg577<def> = MADDXrrr %vreg587<kill>, %vreg576<kill>, %XZR; GPR64:%vreg577,%vreg587,%vreg576
2224B		%vreg578<def> = ADDXrr %vreg580<kill>, %vreg577<kill>; GPR64common:%vreg578 GPR64:%vreg580,%vreg577
2240B		%vreg573<def> = LDRWui %vreg578<kill>, 0; mem:LD4[%arrayidx42] GPR32:%vreg573 GPR64common:%vreg578
2256B		%vreg571<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg571
2272B		STRWui %vreg573<kill>, %vreg571<kill>, 15; mem:ST4[%tPos43] GPR32:%vreg573 GPR64common:%vreg571
2288B		%vreg568<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg568
2304B		%vreg567<def> = LDRWui %vreg568<kill>, 15; mem:LD4[%tPos44] GPR32:%vreg567 GPR64common:%vreg568
2320B		%vreg563<def> = ANDWri %vreg567<kill>, 7; GPR32common:%vreg563 GPR32:%vreg567
2352B		STRBBui %vreg563<kill>, <fi#2>, 0; mem:ST1[FixedStack2] GPR32common:%vreg563
2368B		%vreg560<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg560
2384B		%vreg559<def> = LDRWui %vreg560, 15; mem:LD4[%tPos46] GPR32:%vreg559 GPR64common:%vreg560
2400B		%vreg558<def> = UBFMWri %vreg559<kill>, 8, 31; GPR32:%vreg558,%vreg559
2416B		STRWui %vreg558<kill>, %vreg560<kill>, 15; mem:ST4[%tPos46] GPR32:%vreg558 GPR64common:%vreg560
2432B		%vreg554<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg554
2448B		%vreg553<def> = LDRWui %vreg554<kill>, 6; mem:LD4[%rNToGo] GPR32:%vreg553 GPR64common:%vreg554
2464B		CBNZW %vreg553<kill>, <BB#18>; GPR32:%vreg553
	    Successors according to CFG: BB#18 BB#15
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = MOVi32imm 1
> STRWui %W9<kill>, %X8<kill>, 4; mem:ST4[%state_out_len38]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W8<def> = LDRWui %X8<kill>, 16; mem:LD4[%k0]
> STRBBui %W8<kill>, %X9<kill>, 12; mem:ST1[%state_out_ch40]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W8<def> = LDRWui %X8<kill>, 15, %X8<imp-def>; mem:LD4[%tPos]
> %X9<def> = LDRXui %X9<kill>, 394; mem:LD8[%tt]
> %X10<def> = MOVi64imm 4
> %X8<def> = MADDXrrr %X8<kill>, %X10<kill>, %XZR
> %X8<def> = ADDXrr %X9<kill>, %X8<kill>
> %W8<def> = LDRWui %X8<kill>, 0; mem:LD4[%arrayidx42]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRWui %W8<kill>, %X9<kill>, 15; mem:ST4[%tPos43]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W8<def> = LDRWui %X8<kill>, 15; mem:LD4[%tPos44]
> %W8<def> = ANDWri %W8<kill>, 7
> STRBBui %W8<kill>, <fi#2>, 0; mem:ST1[FixedStack2]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = LDRWui %X8, 15; mem:LD4[%tPos46]
> %W9<def> = UBFMWri %W9<kill>, 8, 31
> STRWui %W9<kill>, %X8<kill>, 15; mem:ST4[%tPos46]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W8<def> = LDRWui %X8<kill>, 6; mem:LD4[%rNToGo]
> CBNZW %W8<kill>, <BB#18>
2480B	BB#15: derived from LLVM BB %if.then.50
	    Live Ins: %X19
	    Predecessors according to CFG: BB#14
2528B		%vreg626<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg626
2544B		%vreg625<def> = LDRSWui %vreg626<kill>, 7; mem:LD4[%rTPos] GPR64:%vreg625 GPR64common:%vreg626
2552B		%vreg615<def> = ADRP <ga:@BZ2_rNums>[TF=1]; GPR64common:%vreg615
2560B		%vreg618<def> = MOVi64imm 4; GPR64:%vreg618
2568B		%vreg616<def> = ADDXri %vreg615<kill>, <ga:@BZ2_rNums>[TF=34], 0; GPR64common:%vreg616,%vreg615
2576B		%vreg619<def> = MADDXrrr %vreg625<kill>, %vreg618<kill>, %XZR; GPR64:%vreg619,%vreg625,%vreg618
2592B		%vreg620<def> = ADDXrr %vreg616<kill>, %vreg619<kill>; GPR64common:%vreg620,%vreg616 GPR64:%vreg619
2608B		%vreg614<def> = LDRWui %vreg620<kill>, 0; mem:LD4[%arrayidx52] GPR32:%vreg614 GPR64common:%vreg620
2624B		%vreg612<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg612
2640B		STRWui %vreg614<kill>, %vreg612<kill>, 6; mem:ST4[%rNToGo53] GPR32:%vreg614 GPR64common:%vreg612
2656B		%vreg609<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg609
2672B		%vreg608<def> = LDRWui %vreg609, 7; mem:LD4[%rTPos54] GPR32common:%vreg608 GPR64common:%vreg609
2688B		%vreg607<def> = ADDWri %vreg608<kill>, 1, 0; GPR32common:%vreg607,%vreg608
2704B		STRWui %vreg607<kill>, %vreg609<kill>, 7; mem:ST4[%rTPos54] GPR32common:%vreg607 GPR64common:%vreg609
2720B		%vreg603<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg603
2736B		%vreg602<def> = LDRWui %vreg603<kill>, 7; mem:LD4[%rTPos56] GPR32common:%vreg602 GPR64common:%vreg603
2752B		%WZR<def> = SUBSWri %vreg602<kill>, 512, 0, %NZCV<imp-def>; GPR32common:%vreg602
2768B		Bcc 1, <BB#17>, %NZCV<imp-use>
	    Successors according to CFG: BB#17 BB#16
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X8<def> = LDRSWui %X8<kill>, 7; mem:LD4[%rTPos]
> %X9<def> = ADRP <ga:@BZ2_rNums>[TF=1]
> %X10<def> = MOVi64imm 4
> %X9<def> = ADDXri %X9<kill>, <ga:@BZ2_rNums>[TF=34], 0
> %X8<def> = MADDXrrr %X8<kill>, %X10<kill>, %XZR
> %X8<def> = ADDXrr %X9<kill>, %X8<kill>
> %W8<def> = LDRWui %X8<kill>, 0; mem:LD4[%arrayidx52]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRWui %W8<kill>, %X9<kill>, 6; mem:ST4[%rNToGo53]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = LDRWui %X8, 7; mem:LD4[%rTPos54]
> %W9<def> = ADDWri %W9<kill>, 1, 0
> STRWui %W9<kill>, %X8<kill>, 7; mem:ST4[%rTPos54]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W8<def> = LDRWui %X8<kill>, 7; mem:LD4[%rTPos56]
> %WZR<def> = SUBSWri %W8<kill>, 512, 0, %NZCV<imp-def>
> Bcc 1, <BB#17>, %NZCV<imp-use>
2784B	BB#16: derived from LLVM BB %if.then.59
	    Live Ins: %X19
	    Predecessors according to CFG: BB#15
2800B		%vreg628<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg628
2816B		STRWui %WZR, %vreg628<kill>, 7; mem:ST4[%rTPos60] GPR64common:%vreg628
	    Successors according to CFG: BB#17
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRWui %WZR, %X8<kill>, 7; mem:ST4[%rTPos60]
2832B	BB#17: derived from LLVM BB %if.end.61
	    Live Ins: %X19
	    Predecessors according to CFG: BB#15 BB#16
2848B		B <BB#18>
	    Successors according to CFG: BB#18
> B <BB#18>
2864B	BB#18: derived from LLVM BB %if.end.62
	    Live Ins: %X19
	    Predecessors according to CFG: BB#14 BB#17
2872B		%vreg658<def> = COPY %WZR; GPR32:%vreg658
2912B		%vreg668<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg668
2928B		%vreg667<def> = LDRWui %vreg668, 6; mem:LD4[%rNToGo63] GPR32common:%vreg667 GPR64common:%vreg668
2944B		%vreg666<def> = SUBWri %vreg667<kill>, 1, 0; GPR32common:%vreg666,%vreg667
2960B		STRWui %vreg666<kill>, %vreg668<kill>, 6; mem:ST4[%rNToGo63] GPR32common:%vreg666 GPR64common:%vreg668
2976B		%vreg662<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg662
2992B		%vreg661<def> = LDRWui %vreg662<kill>, 6; mem:LD4[%rNToGo65] GPR32common:%vreg661 GPR64common:%vreg662
3040B		%vreg655<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg655
3048B		%vreg657<def> = MOVi32imm 1; GPR32:%vreg657
3056B		%WZR<def> = SUBSWri %vreg661<kill>, 1, 0, %NZCV<imp-def>; GPR32common:%vreg661
3064B		%vreg659<def> = CSELWr %vreg657<kill>, %vreg658<kill>, 0, %NZCV<imp-use>; GPR32:%vreg659,%vreg657,%vreg658
3072B		%vreg649<def> = EORWrr %vreg655<kill>, %vreg659<kill>; GPR32:%vreg649,%vreg655,%vreg659
3088B		STRBBui %vreg649<kill>, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg649
3104B		%vreg646<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg646
3120B		%vreg645<def> = LDRWui %vreg646, 273; mem:LD4[%nblock_used71] GPR32common:%vreg645 GPR64common:%vreg646
3136B		%vreg644<def> = ADDWri %vreg645<kill>, 1, 0; GPR32common:%vreg644,%vreg645
3152B		STRWui %vreg644<kill>, %vreg646<kill>, 273; mem:ST4[%nblock_used71] GPR32common:%vreg644 GPR64common:%vreg646
3200B		%vreg637<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg637
3208B		%vreg640<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg640
3216B		%vreg634<def> = MOVi64imm 64080; GPR64:%vreg634
3232B		%vreg635<def> = ADDXrr %vreg637<kill>, %vreg634<kill>; GPR64common:%vreg635 GPR64:%vreg637,%vreg634
3248B		%vreg636<def> = LDRWui %vreg635<kill>, 0; mem:LD4[%save_nblock74] GPR32common:%vreg636 GPR64common:%vreg635
3256B		%vreg639<def> = LDRWui %vreg640<kill>, 273; mem:LD4[%nblock_used73] GPR32:%vreg639 GPR64common:%vreg640
3264B		%vreg632<def> = ADDWri %vreg636<kill>, 1, 0; GPR32common:%vreg632,%vreg636
3280B		%WZR<def> = SUBSWrr %vreg639<kill>, %vreg632<kill>, %NZCV<imp-def>; GPR32:%vreg639 GPR32common:%vreg632
3296B		Bcc 1, <BB#20>, %NZCV<imp-use>
	    Successors according to CFG: BB#20 BB#19
> %W8<def> = COPY %WZR
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W10<def> = LDRWui %X9, 6; mem:LD4[%rNToGo63]
> %W10<def> = SUBWri %W10<kill>, 1, 0
> STRWui %W10<kill>, %X9<kill>, 6; mem:ST4[%rNToGo63]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = LDRWui %X9<kill>, 6; mem:LD4[%rNToGo65]
> %W10<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2]
> %W11<def> = MOVi32imm 1
> %WZR<def> = SUBSWri %W9<kill>, 1, 0, %NZCV<imp-def>
> %W8<def> = CSELWr %W11<kill>, %W8<kill>, 0, %NZCV<imp-use>
> %W8<def> = EORWrr %W10<kill>, %W8<kill>
> STRBBui %W8<kill>, <fi#2>, 0; mem:ST1[FixedStack2]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = LDRWui %X8, 273; mem:LD4[%nblock_used71]
> %W9<def> = ADDWri %W9<kill>, 1, 0
> STRWui %W9<kill>, %X8<kill>, 273; mem:ST4[%nblock_used71]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X10<def> = MOVi64imm 64080
> %X8<def> = ADDXrr %X8<kill>, %X10<kill>
> %W8<def> = LDRWui %X8<kill>, 0; mem:LD4[%save_nblock74]
> %W9<def> = LDRWui %X9<kill>, 273; mem:LD4[%nblock_used73]
> %W8<def> = ADDWri %W8<kill>, 1, 0
> %WZR<def> = SUBSWrr %W9<kill>, %W8<kill>, %NZCV<imp-def>
> Bcc 1, <BB#20>, %NZCV<imp-use>
3312B	BB#19: derived from LLVM BB %if.then.78
	    Live Ins: %X19
	    Predecessors according to CFG: BB#18
3328B		B <BB#2>
	    Successors according to CFG: BB#2
> B <BB#2>
3344B	BB#20: derived from LLVM BB %if.end.79
	    Live Ins: %X19
	    Predecessors according to CFG: BB#18
3376B		%vreg673<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg673
3384B		%vreg676<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg676
3392B		%vreg672<def> = LDRWui %vreg673<kill>, 16; mem:LD4[%k081] GPR32:%vreg672 GPR64common:%vreg673
3408B		%WZR<def> = SUBSWrr %vreg676<kill>, %vreg672<kill>, %NZCV<imp-def>; GPR32:%vreg676,%vreg672
3424B		Bcc 0, <BB#22>, %NZCV<imp-use>
	    Successors according to CFG: BB#22 BB#21
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2]
> %W8<def> = LDRWui %X8<kill>, 16; mem:LD4[%k081]
> %WZR<def> = SUBSWrr %W9<kill>, %W8<kill>, %NZCV<imp-def>
> Bcc 0, <BB#22>, %NZCV<imp-use>
3440B	BB#21: derived from LLVM BB %if.then.84
	    Live Ins: %X19
	    Predecessors according to CFG: BB#20
3456B		%vreg1130<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg1130
3472B		%vreg1127<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1127
3488B		STRWui %vreg1130<kill>, %vreg1127<kill>, 16; mem:ST4[%k086] GPR32:%vreg1130 GPR64common:%vreg1127
3504B		B <BB#2>
	    Successors according to CFG: BB#2
> %W8<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRWui %W8<kill>, %X9<kill>, 16; mem:ST4[%k086]
> B <BB#2>
3520B	BB#22: derived from LLVM BB %if.end.87
	    Live Ins: %X19
	    Predecessors according to CFG: BB#20
3552B		%vreg717<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg717
3560B		%vreg715<def> = MOVi32imm 2; GPR32:%vreg715
3568B		STRWui %vreg715<kill>, %vreg717<kill>, 4; mem:ST4[%state_out_len88] GPR32:%vreg715 GPR64common:%vreg717
3584B		%vreg714<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg714
3632B		%vreg707<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg707
3640B		%vreg713:sub_32<def,read-undef> = LDRWui %vreg714<kill>, 15; mem:LD4[%tPos89] GPR64:%vreg713 GPR64common:%vreg714
3648B		%vreg706<def> = LDRXui %vreg707<kill>, 394; mem:LD8[%tt91] GPR64:%vreg706 GPR64common:%vreg707
3664B		%vreg702<def> = MOVi64imm 4; GPR64:%vreg702
3680B		%vreg703<def> = MADDXrrr %vreg713<kill>, %vreg702<kill>, %XZR; GPR64:%vreg703,%vreg713,%vreg702
3696B		%vreg704<def> = ADDXrr %vreg706<kill>, %vreg703<kill>; GPR64common:%vreg704 GPR64:%vreg706,%vreg703
3712B		%vreg699<def> = LDRWui %vreg704<kill>, 0; mem:LD4[%arrayidx92] GPR32:%vreg699 GPR64common:%vreg704
3728B		%vreg697<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg697
3744B		STRWui %vreg699<kill>, %vreg697<kill>, 15; mem:ST4[%tPos93] GPR32:%vreg699 GPR64common:%vreg697
3760B		%vreg694<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg694
3776B		%vreg693<def> = LDRWui %vreg694<kill>, 15; mem:LD4[%tPos94] GPR32:%vreg693 GPR64common:%vreg694
3792B		%vreg689<def> = ANDWri %vreg693<kill>, 7; GPR32common:%vreg689 GPR32:%vreg693
3824B		STRBBui %vreg689<kill>, <fi#2>, 0; mem:ST1[FixedStack2] GPR32common:%vreg689
3840B		%vreg686<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg686
3856B		%vreg685<def> = LDRWui %vreg686, 15; mem:LD4[%tPos97] GPR32:%vreg685 GPR64common:%vreg686
3872B		%vreg684<def> = UBFMWri %vreg685<kill>, 8, 31; GPR32:%vreg684,%vreg685
3888B		STRWui %vreg684<kill>, %vreg686<kill>, 15; mem:ST4[%tPos97] GPR32:%vreg684 GPR64common:%vreg686
3904B		%vreg680<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg680
3920B		%vreg679<def> = LDRWui %vreg680<kill>, 6; mem:LD4[%rNToGo99] GPR32:%vreg679 GPR64common:%vreg680
3936B		CBNZW %vreg679<kill>, <BB#26>; GPR32:%vreg679
	    Successors according to CFG: BB#26 BB#23
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = MOVi32imm 2
> STRWui %W9<kill>, %X8<kill>, 4; mem:ST4[%state_out_len88]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W8<def> = LDRWui %X8<kill>, 15, %X8<imp-def>; mem:LD4[%tPos89]
> %X9<def> = LDRXui %X9<kill>, 394; mem:LD8[%tt91]
> %X10<def> = MOVi64imm 4
> %X8<def> = MADDXrrr %X8<kill>, %X10<kill>, %XZR
> %X8<def> = ADDXrr %X9<kill>, %X8<kill>
> %W8<def> = LDRWui %X8<kill>, 0; mem:LD4[%arrayidx92]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRWui %W8<kill>, %X9<kill>, 15; mem:ST4[%tPos93]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W8<def> = LDRWui %X8<kill>, 15; mem:LD4[%tPos94]
> %W8<def> = ANDWri %W8<kill>, 7
> STRBBui %W8<kill>, <fi#2>, 0; mem:ST1[FixedStack2]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = LDRWui %X8, 15; mem:LD4[%tPos97]
> %W9<def> = UBFMWri %W9<kill>, 8, 31
> STRWui %W9<kill>, %X8<kill>, 15; mem:ST4[%tPos97]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W8<def> = LDRWui %X8<kill>, 6; mem:LD4[%rNToGo99]
> CBNZW %W8<kill>, <BB#26>
3952B	BB#23: derived from LLVM BB %if.then.102
	    Live Ins: %X19
	    Predecessors according to CFG: BB#22
4000B		%vreg744<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg744
4016B		%vreg743<def> = LDRSWui %vreg744<kill>, 7; mem:LD4[%rTPos103] GPR64:%vreg743 GPR64common:%vreg744
4024B		%vreg733<def> = ADRP <ga:@BZ2_rNums>[TF=1]; GPR64common:%vreg733
4032B		%vreg736<def> = MOVi64imm 4; GPR64:%vreg736
4040B		%vreg734<def> = ADDXri %vreg733<kill>, <ga:@BZ2_rNums>[TF=34], 0; GPR64common:%vreg734,%vreg733
4048B		%vreg737<def> = MADDXrrr %vreg743<kill>, %vreg736<kill>, %XZR; GPR64:%vreg737,%vreg743,%vreg736
4064B		%vreg738<def> = ADDXrr %vreg734<kill>, %vreg737<kill>; GPR64common:%vreg738,%vreg734 GPR64:%vreg737
4080B		%vreg732<def> = LDRWui %vreg738<kill>, 0; mem:LD4[%arrayidx105] GPR32:%vreg732 GPR64common:%vreg738
4096B		%vreg730<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg730
4112B		STRWui %vreg732<kill>, %vreg730<kill>, 6; mem:ST4[%rNToGo106] GPR32:%vreg732 GPR64common:%vreg730
4128B		%vreg727<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg727
4144B		%vreg726<def> = LDRWui %vreg727, 7; mem:LD4[%rTPos107] GPR32common:%vreg726 GPR64common:%vreg727
4160B		%vreg725<def> = ADDWri %vreg726<kill>, 1, 0; GPR32common:%vreg725,%vreg726
4176B		STRWui %vreg725<kill>, %vreg727<kill>, 7; mem:ST4[%rTPos107] GPR32common:%vreg725 GPR64common:%vreg727
4192B		%vreg721<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg721
4208B		%vreg720<def> = LDRWui %vreg721<kill>, 7; mem:LD4[%rTPos109] GPR32common:%vreg720 GPR64common:%vreg721
4224B		%WZR<def> = SUBSWri %vreg720<kill>, 512, 0, %NZCV<imp-def>; GPR32common:%vreg720
4240B		Bcc 1, <BB#25>, %NZCV<imp-use>
	    Successors according to CFG: BB#25 BB#24
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X8<def> = LDRSWui %X8<kill>, 7; mem:LD4[%rTPos103]
> %X9<def> = ADRP <ga:@BZ2_rNums>[TF=1]
> %X10<def> = MOVi64imm 4
> %X9<def> = ADDXri %X9<kill>, <ga:@BZ2_rNums>[TF=34], 0
> %X8<def> = MADDXrrr %X8<kill>, %X10<kill>, %XZR
> %X8<def> = ADDXrr %X9<kill>, %X8<kill>
> %W8<def> = LDRWui %X8<kill>, 0; mem:LD4[%arrayidx105]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRWui %W8<kill>, %X9<kill>, 6; mem:ST4[%rNToGo106]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = LDRWui %X8, 7; mem:LD4[%rTPos107]
> %W9<def> = ADDWri %W9<kill>, 1, 0
> STRWui %W9<kill>, %X8<kill>, 7; mem:ST4[%rTPos107]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W8<def> = LDRWui %X8<kill>, 7; mem:LD4[%rTPos109]
> %WZR<def> = SUBSWri %W8<kill>, 512, 0, %NZCV<imp-def>
> Bcc 1, <BB#25>, %NZCV<imp-use>
4256B	BB#24: derived from LLVM BB %if.then.112
	    Live Ins: %X19
	    Predecessors according to CFG: BB#23
4272B		%vreg746<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg746
4288B		STRWui %WZR, %vreg746<kill>, 7; mem:ST4[%rTPos113] GPR64common:%vreg746
	    Successors according to CFG: BB#25
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRWui %WZR, %X8<kill>, 7; mem:ST4[%rTPos113]
4304B	BB#25: derived from LLVM BB %if.end.114
	    Live Ins: %X19
	    Predecessors according to CFG: BB#23 BB#24
4320B		B <BB#26>
	    Successors according to CFG: BB#26
> B <BB#26>
4336B	BB#26: derived from LLVM BB %if.end.115
	    Live Ins: %X19
	    Predecessors according to CFG: BB#22 BB#25
4344B		%vreg776<def> = COPY %WZR; GPR32:%vreg776
4384B		%vreg786<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg786
4400B		%vreg785<def> = LDRWui %vreg786, 6; mem:LD4[%rNToGo116] GPR32common:%vreg785 GPR64common:%vreg786
4416B		%vreg784<def> = SUBWri %vreg785<kill>, 1, 0; GPR32common:%vreg784,%vreg785
4432B		STRWui %vreg784<kill>, %vreg786<kill>, 6; mem:ST4[%rNToGo116] GPR32common:%vreg784 GPR64common:%vreg786
4448B		%vreg780<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg780
4464B		%vreg779<def> = LDRWui %vreg780<kill>, 6; mem:LD4[%rNToGo118] GPR32common:%vreg779 GPR64common:%vreg780
4512B		%vreg773<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg773
4520B		%vreg775<def> = MOVi32imm 1; GPR32:%vreg775
4528B		%WZR<def> = SUBSWri %vreg779<kill>, 1, 0, %NZCV<imp-def>; GPR32common:%vreg779
4536B		%vreg777<def> = CSELWr %vreg775<kill>, %vreg776<kill>, 0, %NZCV<imp-use>; GPR32:%vreg777,%vreg775,%vreg776
4544B		%vreg767<def> = EORWrr %vreg773<kill>, %vreg777<kill>; GPR32:%vreg767,%vreg773,%vreg777
4560B		STRBBui %vreg767<kill>, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg767
4576B		%vreg764<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg764
4592B		%vreg763<def> = LDRWui %vreg764, 273; mem:LD4[%nblock_used125] GPR32common:%vreg763 GPR64common:%vreg764
4608B		%vreg762<def> = ADDWri %vreg763<kill>, 1, 0; GPR32common:%vreg762,%vreg763
4624B		STRWui %vreg762<kill>, %vreg764<kill>, 273; mem:ST4[%nblock_used125] GPR32common:%vreg762 GPR64common:%vreg764
4672B		%vreg755<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg755
4680B		%vreg758<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg758
4688B		%vreg752<def> = MOVi64imm 64080; GPR64:%vreg752
4704B		%vreg753<def> = ADDXrr %vreg755<kill>, %vreg752<kill>; GPR64common:%vreg753 GPR64:%vreg755,%vreg752
4720B		%vreg754<def> = LDRWui %vreg753<kill>, 0; mem:LD4[%save_nblock128] GPR32common:%vreg754 GPR64common:%vreg753
4728B		%vreg757<def> = LDRWui %vreg758<kill>, 273; mem:LD4[%nblock_used127] GPR32:%vreg757 GPR64common:%vreg758
4736B		%vreg750<def> = ADDWri %vreg754<kill>, 1, 0; GPR32common:%vreg750,%vreg754
4752B		%WZR<def> = SUBSWrr %vreg757<kill>, %vreg750<kill>, %NZCV<imp-def>; GPR32:%vreg757 GPR32common:%vreg750
4768B		Bcc 1, <BB#28>, %NZCV<imp-use>
	    Successors according to CFG: BB#28 BB#27
> %W8<def> = COPY %WZR
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W10<def> = LDRWui %X9, 6; mem:LD4[%rNToGo116]
> %W10<def> = SUBWri %W10<kill>, 1, 0
> STRWui %W10<kill>, %X9<kill>, 6; mem:ST4[%rNToGo116]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = LDRWui %X9<kill>, 6; mem:LD4[%rNToGo118]
> %W10<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2]
> %W11<def> = MOVi32imm 1
> %WZR<def> = SUBSWri %W9<kill>, 1, 0, %NZCV<imp-def>
> %W8<def> = CSELWr %W11<kill>, %W8<kill>, 0, %NZCV<imp-use>
> %W8<def> = EORWrr %W10<kill>, %W8<kill>
> STRBBui %W8<kill>, <fi#2>, 0; mem:ST1[FixedStack2]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = LDRWui %X8, 273; mem:LD4[%nblock_used125]
> %W9<def> = ADDWri %W9<kill>, 1, 0
> STRWui %W9<kill>, %X8<kill>, 273; mem:ST4[%nblock_used125]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X10<def> = MOVi64imm 64080
> %X8<def> = ADDXrr %X8<kill>, %X10<kill>
> %W8<def> = LDRWui %X8<kill>, 0; mem:LD4[%save_nblock128]
> %W9<def> = LDRWui %X9<kill>, 273; mem:LD4[%nblock_used127]
> %W8<def> = ADDWri %W8<kill>, 1, 0
> %WZR<def> = SUBSWrr %W9<kill>, %W8<kill>, %NZCV<imp-def>
> Bcc 1, <BB#28>, %NZCV<imp-use>
4784B	BB#27: derived from LLVM BB %if.then.132
	    Live Ins: %X19
	    Predecessors according to CFG: BB#26
4800B		B <BB#2>
	    Successors according to CFG: BB#2
> B <BB#2>
4816B	BB#28: derived from LLVM BB %if.end.133
	    Live Ins: %X19
	    Predecessors according to CFG: BB#26
4848B		%vreg791<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg791
4856B		%vreg794<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg794
4864B		%vreg790<def> = LDRWui %vreg791<kill>, 16; mem:LD4[%k0135] GPR32:%vreg790 GPR64common:%vreg791
4880B		%WZR<def> = SUBSWrr %vreg794<kill>, %vreg790<kill>, %NZCV<imp-def>; GPR32:%vreg794,%vreg790
4896B		Bcc 0, <BB#30>, %NZCV<imp-use>
	    Successors according to CFG: BB#30 BB#29
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2]
> %W8<def> = LDRWui %X8<kill>, 16; mem:LD4[%k0135]
> %WZR<def> = SUBSWrr %W9<kill>, %W8<kill>, %NZCV<imp-def>
> Bcc 0, <BB#30>, %NZCV<imp-use>
4912B	BB#29: derived from LLVM BB %if.then.138
	    Live Ins: %X19
	    Predecessors according to CFG: BB#28
4928B		%vreg1124<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg1124
4944B		%vreg1121<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1121
4960B		STRWui %vreg1124<kill>, %vreg1121<kill>, 16; mem:ST4[%k0140] GPR32:%vreg1124 GPR64common:%vreg1121
4976B		B <BB#2>
	    Successors according to CFG: BB#2
> %W8<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRWui %W8<kill>, %X9<kill>, 16; mem:ST4[%k0140]
> B <BB#2>
4992B	BB#30: derived from LLVM BB %if.end.141
	    Live Ins: %X19
	    Predecessors according to CFG: BB#28
5024B		%vreg835<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg835
5032B		%vreg833<def> = MOVi32imm 3; GPR32:%vreg833
5040B		STRWui %vreg833<kill>, %vreg835<kill>, 4; mem:ST4[%state_out_len142] GPR32:%vreg833 GPR64common:%vreg835
5056B		%vreg832<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg832
5104B		%vreg825<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg825
5112B		%vreg831:sub_32<def,read-undef> = LDRWui %vreg832<kill>, 15; mem:LD4[%tPos143] GPR64:%vreg831 GPR64common:%vreg832
5120B		%vreg824<def> = LDRXui %vreg825<kill>, 394; mem:LD8[%tt145] GPR64:%vreg824 GPR64common:%vreg825
5136B		%vreg820<def> = MOVi64imm 4; GPR64:%vreg820
5152B		%vreg821<def> = MADDXrrr %vreg831<kill>, %vreg820<kill>, %XZR; GPR64:%vreg821,%vreg831,%vreg820
5168B		%vreg822<def> = ADDXrr %vreg824<kill>, %vreg821<kill>; GPR64common:%vreg822 GPR64:%vreg824,%vreg821
5184B		%vreg817<def> = LDRWui %vreg822<kill>, 0; mem:LD4[%arrayidx146] GPR32:%vreg817 GPR64common:%vreg822
5200B		%vreg815<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg815
5216B		STRWui %vreg817<kill>, %vreg815<kill>, 15; mem:ST4[%tPos147] GPR32:%vreg817 GPR64common:%vreg815
5232B		%vreg812<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg812
5248B		%vreg811<def> = LDRWui %vreg812<kill>, 15; mem:LD4[%tPos148] GPR32:%vreg811 GPR64common:%vreg812
5264B		%vreg807<def> = ANDWri %vreg811<kill>, 7; GPR32common:%vreg807 GPR32:%vreg811
5296B		STRBBui %vreg807<kill>, <fi#2>, 0; mem:ST1[FixedStack2] GPR32common:%vreg807
5312B		%vreg804<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg804
5328B		%vreg803<def> = LDRWui %vreg804, 15; mem:LD4[%tPos151] GPR32:%vreg803 GPR64common:%vreg804
5344B		%vreg802<def> = UBFMWri %vreg803<kill>, 8, 31; GPR32:%vreg802,%vreg803
5360B		STRWui %vreg802<kill>, %vreg804<kill>, 15; mem:ST4[%tPos151] GPR32:%vreg802 GPR64common:%vreg804
5376B		%vreg798<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg798
5392B		%vreg797<def> = LDRWui %vreg798<kill>, 6; mem:LD4[%rNToGo153] GPR32:%vreg797 GPR64common:%vreg798
5408B		CBNZW %vreg797<kill>, <BB#34>; GPR32:%vreg797
	    Successors according to CFG: BB#34 BB#31
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = MOVi32imm 3
> STRWui %W9<kill>, %X8<kill>, 4; mem:ST4[%state_out_len142]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W8<def> = LDRWui %X8<kill>, 15, %X8<imp-def>; mem:LD4[%tPos143]
> %X9<def> = LDRXui %X9<kill>, 394; mem:LD8[%tt145]
> %X10<def> = MOVi64imm 4
> %X8<def> = MADDXrrr %X8<kill>, %X10<kill>, %XZR
> %X8<def> = ADDXrr %X9<kill>, %X8<kill>
> %W8<def> = LDRWui %X8<kill>, 0; mem:LD4[%arrayidx146]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRWui %W8<kill>, %X9<kill>, 15; mem:ST4[%tPos147]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W8<def> = LDRWui %X8<kill>, 15; mem:LD4[%tPos148]
> %W8<def> = ANDWri %W8<kill>, 7
> STRBBui %W8<kill>, <fi#2>, 0; mem:ST1[FixedStack2]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = LDRWui %X8, 15; mem:LD4[%tPos151]
> %W9<def> = UBFMWri %W9<kill>, 8, 31
> STRWui %W9<kill>, %X8<kill>, 15; mem:ST4[%tPos151]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W8<def> = LDRWui %X8<kill>, 6; mem:LD4[%rNToGo153]
> CBNZW %W8<kill>, <BB#34>
5424B	BB#31: derived from LLVM BB %if.then.156
	    Live Ins: %X19
	    Predecessors according to CFG: BB#30
5472B		%vreg862<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg862
5488B		%vreg861<def> = LDRSWui %vreg862<kill>, 7; mem:LD4[%rTPos157] GPR64:%vreg861 GPR64common:%vreg862
5496B		%vreg851<def> = ADRP <ga:@BZ2_rNums>[TF=1]; GPR64common:%vreg851
5504B		%vreg854<def> = MOVi64imm 4; GPR64:%vreg854
5512B		%vreg852<def> = ADDXri %vreg851<kill>, <ga:@BZ2_rNums>[TF=34], 0; GPR64common:%vreg852,%vreg851
5520B		%vreg855<def> = MADDXrrr %vreg861<kill>, %vreg854<kill>, %XZR; GPR64:%vreg855,%vreg861,%vreg854
5536B		%vreg856<def> = ADDXrr %vreg852<kill>, %vreg855<kill>; GPR64common:%vreg856,%vreg852 GPR64:%vreg855
5552B		%vreg850<def> = LDRWui %vreg856<kill>, 0; mem:LD4[%arrayidx159] GPR32:%vreg850 GPR64common:%vreg856
5568B		%vreg848<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg848
5584B		STRWui %vreg850<kill>, %vreg848<kill>, 6; mem:ST4[%rNToGo160] GPR32:%vreg850 GPR64common:%vreg848
5600B		%vreg845<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg845
5616B		%vreg844<def> = LDRWui %vreg845, 7; mem:LD4[%rTPos161] GPR32common:%vreg844 GPR64common:%vreg845
5632B		%vreg843<def> = ADDWri %vreg844<kill>, 1, 0; GPR32common:%vreg843,%vreg844
5648B		STRWui %vreg843<kill>, %vreg845<kill>, 7; mem:ST4[%rTPos161] GPR32common:%vreg843 GPR64common:%vreg845
5664B		%vreg839<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg839
5680B		%vreg838<def> = LDRWui %vreg839<kill>, 7; mem:LD4[%rTPos163] GPR32common:%vreg838 GPR64common:%vreg839
5696B		%WZR<def> = SUBSWri %vreg838<kill>, 512, 0, %NZCV<imp-def>; GPR32common:%vreg838
5712B		Bcc 1, <BB#33>, %NZCV<imp-use>
	    Successors according to CFG: BB#33 BB#32
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X8<def> = LDRSWui %X8<kill>, 7; mem:LD4[%rTPos157]
> %X9<def> = ADRP <ga:@BZ2_rNums>[TF=1]
> %X10<def> = MOVi64imm 4
> %X9<def> = ADDXri %X9<kill>, <ga:@BZ2_rNums>[TF=34], 0
> %X8<def> = MADDXrrr %X8<kill>, %X10<kill>, %XZR
> %X8<def> = ADDXrr %X9<kill>, %X8<kill>
> %W8<def> = LDRWui %X8<kill>, 0; mem:LD4[%arrayidx159]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRWui %W8<kill>, %X9<kill>, 6; mem:ST4[%rNToGo160]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = LDRWui %X8, 7; mem:LD4[%rTPos161]
> %W9<def> = ADDWri %W9<kill>, 1, 0
> STRWui %W9<kill>, %X8<kill>, 7; mem:ST4[%rTPos161]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W8<def> = LDRWui %X8<kill>, 7; mem:LD4[%rTPos163]
> %WZR<def> = SUBSWri %W8<kill>, 512, 0, %NZCV<imp-def>
> Bcc 1, <BB#33>, %NZCV<imp-use>
5728B	BB#32: derived from LLVM BB %if.then.166
	    Live Ins: %X19
	    Predecessors according to CFG: BB#31
5744B		%vreg864<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg864
5760B		STRWui %WZR, %vreg864<kill>, 7; mem:ST4[%rTPos167] GPR64common:%vreg864
	    Successors according to CFG: BB#33
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRWui %WZR, %X8<kill>, 7; mem:ST4[%rTPos167]
5776B	BB#33: derived from LLVM BB %if.end.168
	    Live Ins: %X19
	    Predecessors according to CFG: BB#31 BB#32
5792B		B <BB#34>
	    Successors according to CFG: BB#34
> B <BB#34>
5808B	BB#34: derived from LLVM BB %if.end.169
	    Live Ins: %X19
	    Predecessors according to CFG: BB#30 BB#33
5816B		%vreg894<def> = COPY %WZR; GPR32:%vreg894
5856B		%vreg904<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg904
5872B		%vreg903<def> = LDRWui %vreg904, 6; mem:LD4[%rNToGo170] GPR32common:%vreg903 GPR64common:%vreg904
5888B		%vreg902<def> = SUBWri %vreg903<kill>, 1, 0; GPR32common:%vreg902,%vreg903
5904B		STRWui %vreg902<kill>, %vreg904<kill>, 6; mem:ST4[%rNToGo170] GPR32common:%vreg902 GPR64common:%vreg904
5920B		%vreg898<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg898
5936B		%vreg897<def> = LDRWui %vreg898<kill>, 6; mem:LD4[%rNToGo172] GPR32common:%vreg897 GPR64common:%vreg898
5984B		%vreg891<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg891
5992B		%vreg893<def> = MOVi32imm 1; GPR32:%vreg893
6000B		%WZR<def> = SUBSWri %vreg897<kill>, 1, 0, %NZCV<imp-def>; GPR32common:%vreg897
6008B		%vreg895<def> = CSELWr %vreg893<kill>, %vreg894<kill>, 0, %NZCV<imp-use>; GPR32:%vreg895,%vreg893,%vreg894
6016B		%vreg885<def> = EORWrr %vreg891<kill>, %vreg895<kill>; GPR32:%vreg885,%vreg891,%vreg895
6032B		STRBBui %vreg885<kill>, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg885
6048B		%vreg882<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg882
6064B		%vreg881<def> = LDRWui %vreg882, 273; mem:LD4[%nblock_used179] GPR32common:%vreg881 GPR64common:%vreg882
6080B		%vreg880<def> = ADDWri %vreg881<kill>, 1, 0; GPR32common:%vreg880,%vreg881
6096B		STRWui %vreg880<kill>, %vreg882<kill>, 273; mem:ST4[%nblock_used179] GPR32common:%vreg880 GPR64common:%vreg882
6144B		%vreg873<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg873
6152B		%vreg876<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg876
6160B		%vreg870<def> = MOVi64imm 64080; GPR64:%vreg870
6176B		%vreg871<def> = ADDXrr %vreg873<kill>, %vreg870<kill>; GPR64common:%vreg871 GPR64:%vreg873,%vreg870
6192B		%vreg872<def> = LDRWui %vreg871<kill>, 0; mem:LD4[%save_nblock182] GPR32common:%vreg872 GPR64common:%vreg871
6200B		%vreg875<def> = LDRWui %vreg876<kill>, 273; mem:LD4[%nblock_used181] GPR32:%vreg875 GPR64common:%vreg876
6208B		%vreg868<def> = ADDWri %vreg872<kill>, 1, 0; GPR32common:%vreg868,%vreg872
6224B		%WZR<def> = SUBSWrr %vreg875<kill>, %vreg868<kill>, %NZCV<imp-def>; GPR32:%vreg875 GPR32common:%vreg868
6240B		Bcc 1, <BB#36>, %NZCV<imp-use>
	    Successors according to CFG: BB#36 BB#35
> %W8<def> = COPY %WZR
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W10<def> = LDRWui %X9, 6; mem:LD4[%rNToGo170]
> %W10<def> = SUBWri %W10<kill>, 1, 0
> STRWui %W10<kill>, %X9<kill>, 6; mem:ST4[%rNToGo170]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = LDRWui %X9<kill>, 6; mem:LD4[%rNToGo172]
> %W10<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2]
> %W11<def> = MOVi32imm 1
> %WZR<def> = SUBSWri %W9<kill>, 1, 0, %NZCV<imp-def>
> %W8<def> = CSELWr %W11<kill>, %W8<kill>, 0, %NZCV<imp-use>
> %W8<def> = EORWrr %W10<kill>, %W8<kill>
> STRBBui %W8<kill>, <fi#2>, 0; mem:ST1[FixedStack2]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = LDRWui %X8, 273; mem:LD4[%nblock_used179]
> %W9<def> = ADDWri %W9<kill>, 1, 0
> STRWui %W9<kill>, %X8<kill>, 273; mem:ST4[%nblock_used179]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X10<def> = MOVi64imm 64080
> %X8<def> = ADDXrr %X8<kill>, %X10<kill>
> %W8<def> = LDRWui %X8<kill>, 0; mem:LD4[%save_nblock182]
> %W9<def> = LDRWui %X9<kill>, 273; mem:LD4[%nblock_used181]
> %W8<def> = ADDWri %W8<kill>, 1, 0
> %WZR<def> = SUBSWrr %W9<kill>, %W8<kill>, %NZCV<imp-def>
> Bcc 1, <BB#36>, %NZCV<imp-use>
6256B	BB#35: derived from LLVM BB %if.then.186
	    Live Ins: %X19
	    Predecessors according to CFG: BB#34
6272B		B <BB#2>
	    Successors according to CFG: BB#2
> B <BB#2>
6288B	BB#36: derived from LLVM BB %if.end.187
	    Live Ins: %X19
	    Predecessors according to CFG: BB#34
6320B		%vreg909<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg909
6328B		%vreg912<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg912
6336B		%vreg908<def> = LDRWui %vreg909<kill>, 16; mem:LD4[%k0189] GPR32:%vreg908 GPR64common:%vreg909
6352B		%WZR<def> = SUBSWrr %vreg912<kill>, %vreg908<kill>, %NZCV<imp-def>; GPR32:%vreg912,%vreg908
6368B		Bcc 0, <BB#38>, %NZCV<imp-use>
	    Successors according to CFG: BB#38 BB#37
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2]
> %W8<def> = LDRWui %X8<kill>, 16; mem:LD4[%k0189]
> %WZR<def> = SUBSWrr %W9<kill>, %W8<kill>, %NZCV<imp-def>
> Bcc 0, <BB#38>, %NZCV<imp-use>
6384B	BB#37: derived from LLVM BB %if.then.192
	    Live Ins: %X19
	    Predecessors according to CFG: BB#36
6400B		%vreg1118<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg1118
6416B		%vreg1115<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1115
6432B		STRWui %vreg1118<kill>, %vreg1115<kill>, 16; mem:ST4[%k0194] GPR32:%vreg1118 GPR64common:%vreg1115
6448B		B <BB#2>
	    Successors according to CFG: BB#2
> %W8<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRWui %W8<kill>, %X9<kill>, 16; mem:ST4[%k0194]
> B <BB#2>
6464B	BB#38: derived from LLVM BB %if.end.195
	    Live Ins: %X19
	    Predecessors according to CFG: BB#36
6480B		%vreg950<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg950
6528B		%vreg943<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg943
6536B		%vreg949:sub_32<def,read-undef> = LDRWui %vreg950<kill>, 15; mem:LD4[%tPos196] GPR64:%vreg949 GPR64common:%vreg950
6544B		%vreg942<def> = LDRXui %vreg943<kill>, 394; mem:LD8[%tt198] GPR64:%vreg942 GPR64common:%vreg943
6560B		%vreg938<def> = MOVi64imm 4; GPR64:%vreg938
6576B		%vreg939<def> = MADDXrrr %vreg949<kill>, %vreg938<kill>, %XZR; GPR64:%vreg939,%vreg949,%vreg938
6592B		%vreg940<def> = ADDXrr %vreg942<kill>, %vreg939<kill>; GPR64common:%vreg940 GPR64:%vreg942,%vreg939
6608B		%vreg935<def> = LDRWui %vreg940<kill>, 0; mem:LD4[%arrayidx199] GPR32:%vreg935 GPR64common:%vreg940
6624B		%vreg933<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg933
6640B		STRWui %vreg935<kill>, %vreg933<kill>, 15; mem:ST4[%tPos200] GPR32:%vreg935 GPR64common:%vreg933
6656B		%vreg930<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg930
6672B		%vreg929<def> = LDRWui %vreg930<kill>, 15; mem:LD4[%tPos201] GPR32:%vreg929 GPR64common:%vreg930
6688B		%vreg925<def> = ANDWri %vreg929<kill>, 7; GPR32common:%vreg925 GPR32:%vreg929
6720B		STRBBui %vreg925<kill>, <fi#2>, 0; mem:ST1[FixedStack2] GPR32common:%vreg925
6736B		%vreg922<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg922
6752B		%vreg921<def> = LDRWui %vreg922, 15; mem:LD4[%tPos204] GPR32:%vreg921 GPR64common:%vreg922
6768B		%vreg920<def> = UBFMWri %vreg921<kill>, 8, 31; GPR32:%vreg920,%vreg921
6784B		STRWui %vreg920<kill>, %vreg922<kill>, 15; mem:ST4[%tPos204] GPR32:%vreg920 GPR64common:%vreg922
6800B		%vreg916<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg916
6816B		%vreg915<def> = LDRWui %vreg916<kill>, 6; mem:LD4[%rNToGo206] GPR32:%vreg915 GPR64common:%vreg916
6832B		CBNZW %vreg915<kill>, <BB#42>; GPR32:%vreg915
	    Successors according to CFG: BB#42 BB#39
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W8<def> = LDRWui %X8<kill>, 15, %X8<imp-def>; mem:LD4[%tPos196]
> %X9<def> = LDRXui %X9<kill>, 394; mem:LD8[%tt198]
> %X10<def> = MOVi64imm 4
> %X8<def> = MADDXrrr %X8<kill>, %X10<kill>, %XZR
> %X8<def> = ADDXrr %X9<kill>, %X8<kill>
> %W8<def> = LDRWui %X8<kill>, 0; mem:LD4[%arrayidx199]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRWui %W8<kill>, %X9<kill>, 15; mem:ST4[%tPos200]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W8<def> = LDRWui %X8<kill>, 15; mem:LD4[%tPos201]
> %W8<def> = ANDWri %W8<kill>, 7
> STRBBui %W8<kill>, <fi#2>, 0; mem:ST1[FixedStack2]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = LDRWui %X8, 15; mem:LD4[%tPos204]
> %W9<def> = UBFMWri %W9<kill>, 8, 31
> STRWui %W9<kill>, %X8<kill>, 15; mem:ST4[%tPos204]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W8<def> = LDRWui %X8<kill>, 6; mem:LD4[%rNToGo206]
> CBNZW %W8<kill>, <BB#42>
6848B	BB#39: derived from LLVM BB %if.then.209
	    Live Ins: %X19
	    Predecessors according to CFG: BB#38
6896B		%vreg977<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg977
6912B		%vreg976<def> = LDRSWui %vreg977<kill>, 7; mem:LD4[%rTPos210] GPR64:%vreg976 GPR64common:%vreg977
6920B		%vreg966<def> = ADRP <ga:@BZ2_rNums>[TF=1]; GPR64common:%vreg966
6928B		%vreg969<def> = MOVi64imm 4; GPR64:%vreg969
6936B		%vreg967<def> = ADDXri %vreg966<kill>, <ga:@BZ2_rNums>[TF=34], 0; GPR64common:%vreg967,%vreg966
6944B		%vreg970<def> = MADDXrrr %vreg976<kill>, %vreg969<kill>, %XZR; GPR64:%vreg970,%vreg976,%vreg969
6960B		%vreg971<def> = ADDXrr %vreg967<kill>, %vreg970<kill>; GPR64common:%vreg971,%vreg967 GPR64:%vreg970
6976B		%vreg965<def> = LDRWui %vreg971<kill>, 0; mem:LD4[%arrayidx212] GPR32:%vreg965 GPR64common:%vreg971
6992B		%vreg963<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg963
7008B		STRWui %vreg965<kill>, %vreg963<kill>, 6; mem:ST4[%rNToGo213] GPR32:%vreg965 GPR64common:%vreg963
7024B		%vreg960<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg960
7040B		%vreg959<def> = LDRWui %vreg960, 7; mem:LD4[%rTPos214] GPR32common:%vreg959 GPR64common:%vreg960
7056B		%vreg958<def> = ADDWri %vreg959<kill>, 1, 0; GPR32common:%vreg958,%vreg959
7072B		STRWui %vreg958<kill>, %vreg960<kill>, 7; mem:ST4[%rTPos214] GPR32common:%vreg958 GPR64common:%vreg960
7088B		%vreg954<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg954
7104B		%vreg953<def> = LDRWui %vreg954<kill>, 7; mem:LD4[%rTPos216] GPR32common:%vreg953 GPR64common:%vreg954
7120B		%WZR<def> = SUBSWri %vreg953<kill>, 512, 0, %NZCV<imp-def>; GPR32common:%vreg953
7136B		Bcc 1, <BB#41>, %NZCV<imp-use>
	    Successors according to CFG: BB#41 BB#40
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X8<def> = LDRSWui %X8<kill>, 7; mem:LD4[%rTPos210]
> %X9<def> = ADRP <ga:@BZ2_rNums>[TF=1]
> %X10<def> = MOVi64imm 4
> %X9<def> = ADDXri %X9<kill>, <ga:@BZ2_rNums>[TF=34], 0
> %X8<def> = MADDXrrr %X8<kill>, %X10<kill>, %XZR
> %X8<def> = ADDXrr %X9<kill>, %X8<kill>
> %W8<def> = LDRWui %X8<kill>, 0; mem:LD4[%arrayidx212]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRWui %W8<kill>, %X9<kill>, 6; mem:ST4[%rNToGo213]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = LDRWui %X8, 7; mem:LD4[%rTPos214]
> %W9<def> = ADDWri %W9<kill>, 1, 0
> STRWui %W9<kill>, %X8<kill>, 7; mem:ST4[%rTPos214]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W8<def> = LDRWui %X8<kill>, 7; mem:LD4[%rTPos216]
> %WZR<def> = SUBSWri %W8<kill>, 512, 0, %NZCV<imp-def>
> Bcc 1, <BB#41>, %NZCV<imp-use>
7152B	BB#40: derived from LLVM BB %if.then.219
	    Live Ins: %X19
	    Predecessors according to CFG: BB#39
7168B		%vreg979<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg979
7184B		STRWui %WZR, %vreg979<kill>, 7; mem:ST4[%rTPos220] GPR64common:%vreg979
	    Successors according to CFG: BB#41
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRWui %WZR, %X8<kill>, 7; mem:ST4[%rTPos220]
7200B	BB#41: derived from LLVM BB %if.end.221
	    Live Ins: %X19
	    Predecessors according to CFG: BB#39 BB#40
7216B		B <BB#42>
	    Successors according to CFG: BB#42
> B <BB#42>
7232B	BB#42: derived from LLVM BB %if.end.222
	    Live Ins: %X19
	    Predecessors according to CFG: BB#38 BB#41
7240B		%vreg1047<def> = COPY %WZR; GPR32:%vreg1047
7280B		%vreg1057<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1057
7296B		%vreg1056<def> = LDRWui %vreg1057, 6; mem:LD4[%rNToGo223] GPR32common:%vreg1056 GPR64common:%vreg1057
7312B		%vreg1055<def> = SUBWri %vreg1056<kill>, 1, 0; GPR32common:%vreg1055,%vreg1056
7328B		STRWui %vreg1055<kill>, %vreg1057<kill>, 6; mem:ST4[%rNToGo223] GPR32common:%vreg1055 GPR64common:%vreg1057
7344B		%vreg1051<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1051
7360B		%vreg1050<def> = LDRWui %vreg1051<kill>, 6; mem:LD4[%rNToGo225] GPR32common:%vreg1050 GPR64common:%vreg1051
7408B		%vreg1044<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg1044
7416B		%vreg1046<def> = MOVi32imm 1; GPR32:%vreg1046
7424B		%WZR<def> = SUBSWri %vreg1050<kill>, 1, 0, %NZCV<imp-def>; GPR32common:%vreg1050
7432B		%vreg1048<def> = CSELWr %vreg1046<kill>, %vreg1047<kill>, 0, %NZCV<imp-use>; GPR32:%vreg1048,%vreg1046,%vreg1047
7440B		%vreg1038<def> = EORWrr %vreg1044<kill>, %vreg1048<kill>; GPR32:%vreg1038,%vreg1044,%vreg1048
7456B		STRBBui %vreg1038<kill>, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg1038
7472B		%vreg1035<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1035
7488B		%vreg1034<def> = LDRWui %vreg1035, 273; mem:LD4[%nblock_used232] GPR32common:%vreg1034 GPR64common:%vreg1035
7504B		%vreg1033<def> = ADDWri %vreg1034<kill>, 1, 0; GPR32common:%vreg1033,%vreg1034
7520B		STRWui %vreg1033<kill>, %vreg1035<kill>, 273; mem:ST4[%nblock_used232] GPR32common:%vreg1033 GPR64common:%vreg1035
7536B		%vreg1029<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32common:%vreg1029
7568B		%vreg1024<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1024
7576B		%vreg1026<def> = ADDWri %vreg1029<kill>, 4, 0; GPR32common:%vreg1026,%vreg1029
7584B		STRWui %vreg1026<kill>, %vreg1024<kill>, 4; mem:ST4[%state_out_len236] GPR32common:%vreg1026 GPR64common:%vreg1024
7600B		%vreg1021<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1021
7648B		%vreg1014<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1014
7656B		%vreg1020:sub_32<def,read-undef> = LDRWui %vreg1021<kill>, 15; mem:LD4[%tPos237] GPR64:%vreg1020 GPR64common:%vreg1021
7664B		%vreg1013<def> = LDRXui %vreg1014<kill>, 394; mem:LD8[%tt239] GPR64:%vreg1013 GPR64common:%vreg1014
7680B		%vreg1009<def> = MOVi64imm 4; GPR64:%vreg1009
7696B		%vreg1010<def> = MADDXrrr %vreg1020<kill>, %vreg1009<kill>, %XZR; GPR64:%vreg1010,%vreg1020,%vreg1009
7712B		%vreg1011<def> = ADDXrr %vreg1013<kill>, %vreg1010<kill>; GPR64common:%vreg1011 GPR64:%vreg1013,%vreg1010
7728B		%vreg1006<def> = LDRWui %vreg1011<kill>, 0; mem:LD4[%arrayidx240] GPR32:%vreg1006 GPR64common:%vreg1011
7744B		%vreg1004<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1004
7760B		STRWui %vreg1006<kill>, %vreg1004<kill>, 15; mem:ST4[%tPos241] GPR32:%vreg1006 GPR64common:%vreg1004
7776B		%vreg1001<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1001
7792B		%vreg1000<def> = LDRWui %vreg1001<kill>, 15; mem:LD4[%tPos242] GPR32:%vreg1000 GPR64common:%vreg1001
7856B		%vreg992<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg992
7860B		%vreg996<def> = ANDWri %vreg1000<kill>, 7; GPR32common:%vreg996 GPR32:%vreg1000
7864B		%vreg994<def> = UBFMWri %vreg996<kill>, 0, 7; GPR32:%vreg994 GPR32common:%vreg996
7872B		STRWui %vreg994<kill>, %vreg992<kill>, 16; mem:ST4[%k0246] GPR32:%vreg994 GPR64common:%vreg992
7888B		%vreg989<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg989
7904B		%vreg988<def> = LDRWui %vreg989, 15; mem:LD4[%tPos247] GPR32:%vreg988 GPR64common:%vreg989
7920B		%vreg987<def> = UBFMWri %vreg988<kill>, 8, 31; GPR32:%vreg987,%vreg988
7936B		STRWui %vreg987<kill>, %vreg989<kill>, 15; mem:ST4[%tPos247] GPR32:%vreg987 GPR64common:%vreg989
7952B		%vreg983<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg983
7968B		%vreg982<def> = LDRWui %vreg983<kill>, 6; mem:LD4[%rNToGo249] GPR32:%vreg982 GPR64common:%vreg983
7984B		CBNZW %vreg982<kill>, <BB#46>; GPR32:%vreg982
	    Successors according to CFG: BB#46 BB#43
> %W8<def> = COPY %WZR
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W10<def> = LDRWui %X9, 6; mem:LD4[%rNToGo223]
> %W10<def> = SUBWri %W10<kill>, 1, 0
> STRWui %W10<kill>, %X9<kill>, 6; mem:ST4[%rNToGo223]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = LDRWui %X9<kill>, 6; mem:LD4[%rNToGo225]
> %W10<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2]
> %W11<def> = MOVi32imm 1
> %WZR<def> = SUBSWri %W9<kill>, 1, 0, %NZCV<imp-def>
> %W8<def> = CSELWr %W11<kill>, %W8<kill>, 0, %NZCV<imp-use>
> %W8<def> = EORWrr %W10<kill>, %W8<kill>
> STRBBui %W8<kill>, <fi#2>, 0; mem:ST1[FixedStack2]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = LDRWui %X8, 273; mem:LD4[%nblock_used232]
> %W9<def> = ADDWri %W9<kill>, 1, 0
> STRWui %W9<kill>, %X8<kill>, 273; mem:ST4[%nblock_used232]
> %W8<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W8<def> = ADDWri %W8<kill>, 4, 0
> STRWui %W8<kill>, %X9<kill>, 4; mem:ST4[%state_out_len236]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W8<def> = LDRWui %X8<kill>, 15, %X8<imp-def>; mem:LD4[%tPos237]
> %X9<def> = LDRXui %X9<kill>, 394; mem:LD8[%tt239]
> %X10<def> = MOVi64imm 4
> %X8<def> = MADDXrrr %X8<kill>, %X10<kill>, %XZR
> %X8<def> = ADDXrr %X9<kill>, %X8<kill>
> %W8<def> = LDRWui %X8<kill>, 0; mem:LD4[%arrayidx240]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRWui %W8<kill>, %X9<kill>, 15; mem:ST4[%tPos241]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W8<def> = LDRWui %X8<kill>, 15; mem:LD4[%tPos242]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W8<def> = ANDWri %W8<kill>, 7
> %W8<def> = UBFMWri %W8<kill>, 0, 7
> STRWui %W8<kill>, %X9<kill>, 16; mem:ST4[%k0246]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = LDRWui %X8, 15; mem:LD4[%tPos247]
> %W9<def> = UBFMWri %W9<kill>, 8, 31
> STRWui %W9<kill>, %X8<kill>, 15; mem:ST4[%tPos247]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W8<def> = LDRWui %X8<kill>, 6; mem:LD4[%rNToGo249]
> CBNZW %W8<kill>, <BB#46>
8000B	BB#43: derived from LLVM BB %if.then.252
	    Live Ins: %X19
	    Predecessors according to CFG: BB#42
8048B		%vreg1084<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1084
8064B		%vreg1083<def> = LDRSWui %vreg1084<kill>, 7; mem:LD4[%rTPos253] GPR64:%vreg1083 GPR64common:%vreg1084
8072B		%vreg1073<def> = ADRP <ga:@BZ2_rNums>[TF=1]; GPR64common:%vreg1073
8080B		%vreg1076<def> = MOVi64imm 4; GPR64:%vreg1076
8088B		%vreg1074<def> = ADDXri %vreg1073<kill>, <ga:@BZ2_rNums>[TF=34], 0; GPR64common:%vreg1074,%vreg1073
8096B		%vreg1077<def> = MADDXrrr %vreg1083<kill>, %vreg1076<kill>, %XZR; GPR64:%vreg1077,%vreg1083,%vreg1076
8112B		%vreg1078<def> = ADDXrr %vreg1074<kill>, %vreg1077<kill>; GPR64common:%vreg1078,%vreg1074 GPR64:%vreg1077
8128B		%vreg1072<def> = LDRWui %vreg1078<kill>, 0; mem:LD4[%arrayidx255] GPR32:%vreg1072 GPR64common:%vreg1078
8144B		%vreg1070<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1070
8160B		STRWui %vreg1072<kill>, %vreg1070<kill>, 6; mem:ST4[%rNToGo256] GPR32:%vreg1072 GPR64common:%vreg1070
8176B		%vreg1067<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1067
8192B		%vreg1066<def> = LDRWui %vreg1067, 7; mem:LD4[%rTPos257] GPR32common:%vreg1066 GPR64common:%vreg1067
8208B		%vreg1065<def> = ADDWri %vreg1066<kill>, 1, 0; GPR32common:%vreg1065,%vreg1066
8224B		STRWui %vreg1065<kill>, %vreg1067<kill>, 7; mem:ST4[%rTPos257] GPR32common:%vreg1065 GPR64common:%vreg1067
8240B		%vreg1061<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1061
8256B		%vreg1060<def> = LDRWui %vreg1061<kill>, 7; mem:LD4[%rTPos259] GPR32common:%vreg1060 GPR64common:%vreg1061
8272B		%WZR<def> = SUBSWri %vreg1060<kill>, 512, 0, %NZCV<imp-def>; GPR32common:%vreg1060
8288B		Bcc 1, <BB#45>, %NZCV<imp-use>
	    Successors according to CFG: BB#45 BB#44
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X8<def> = LDRSWui %X8<kill>, 7; mem:LD4[%rTPos253]
> %X9<def> = ADRP <ga:@BZ2_rNums>[TF=1]
> %X10<def> = MOVi64imm 4
> %X9<def> = ADDXri %X9<kill>, <ga:@BZ2_rNums>[TF=34], 0
> %X8<def> = MADDXrrr %X8<kill>, %X10<kill>, %XZR
> %X8<def> = ADDXrr %X9<kill>, %X8<kill>
> %W8<def> = LDRWui %X8<kill>, 0; mem:LD4[%arrayidx255]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRWui %W8<kill>, %X9<kill>, 6; mem:ST4[%rNToGo256]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = LDRWui %X8, 7; mem:LD4[%rTPos257]
> %W9<def> = ADDWri %W9<kill>, 1, 0
> STRWui %W9<kill>, %X8<kill>, 7; mem:ST4[%rTPos257]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W8<def> = LDRWui %X8<kill>, 7; mem:LD4[%rTPos259]
> %WZR<def> = SUBSWri %W8<kill>, 512, 0, %NZCV<imp-def>
> Bcc 1, <BB#45>, %NZCV<imp-use>
8304B	BB#44: derived from LLVM BB %if.then.262
	    Live Ins: %X19
	    Predecessors according to CFG: BB#43
8320B		%vreg1086<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1086
8336B		STRWui %WZR, %vreg1086<kill>, 7; mem:ST4[%rTPos263] GPR64common:%vreg1086
	    Successors according to CFG: BB#45
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRWui %WZR, %X8<kill>, 7; mem:ST4[%rTPos263]
8352B	BB#45: derived from LLVM BB %if.end.264
	    Live Ins: %X19
	    Predecessors according to CFG: BB#43 BB#44
8368B		B <BB#46>
	    Successors according to CFG: BB#46
> B <BB#46>
8384B	BB#46: derived from LLVM BB %if.end.265
	    Live Ins: %X19
	    Predecessors according to CFG: BB#42 BB#45
8392B		%vreg1102<def> = COPY %WZR; GPR32:%vreg1102
8432B		%vreg1112<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1112
8448B		%vreg1111<def> = LDRWui %vreg1112, 6; mem:LD4[%rNToGo266] GPR32common:%vreg1111 GPR64common:%vreg1112
8464B		%vreg1110<def> = SUBWri %vreg1111<kill>, 1, 0; GPR32common:%vreg1110,%vreg1111
8480B		STRWui %vreg1110<kill>, %vreg1112<kill>, 6; mem:ST4[%rNToGo266] GPR32common:%vreg1110 GPR64common:%vreg1112
8496B		%vreg1106<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1106
8560B		%vreg1099<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1099
8568B		%vreg1105<def> = LDRWui %vreg1106<kill>, 6; mem:LD4[%rNToGo268] GPR32common:%vreg1105 GPR64common:%vreg1106
8576B		%vreg1098<def> = LDRWui %vreg1099, 16; mem:LD4[%k0272] GPR32:%vreg1098 GPR64common:%vreg1099
8584B		%WZR<def> = SUBSWri %vreg1105<kill>, 1, 0, %NZCV<imp-def>; GPR32common:%vreg1105
8592B		%vreg1101<def> = MOVi32imm 1; GPR32:%vreg1101
8600B		%vreg1103<def> = CSELWr %vreg1101<kill>, %vreg1102<kill>, 0, %NZCV<imp-use>; GPR32:%vreg1103,%vreg1101,%vreg1102
8608B		%vreg1097<def> = EORWrr %vreg1098<kill>, %vreg1103<kill>; GPR32:%vreg1097,%vreg1098,%vreg1103
8616B		STRWui %vreg1097<kill>, %vreg1099<kill>, 16; mem:ST4[%k0272] GPR32:%vreg1097 GPR64common:%vreg1099
8624B		%vreg1092<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg1092
8640B		%vreg1091<def> = LDRWui %vreg1092, 273; mem:LD4[%nblock_used274] GPR32common:%vreg1091 GPR64common:%vreg1092
8656B		%vreg1090<def> = ADDWri %vreg1091<kill>, 1, 0; GPR32common:%vreg1090,%vreg1091
8672B		STRWui %vreg1090<kill>, %vreg1092<kill>, 273; mem:ST4[%nblock_used274] GPR32common:%vreg1090 GPR64common:%vreg1092
8688B		B <BB#2>
	    Successors according to CFG: BB#2
> %W8<def> = COPY %WZR
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W10<def> = LDRWui %X9, 6; mem:LD4[%rNToGo266]
> %W10<def> = SUBWri %W10<kill>, 1, 0
> STRWui %W10<kill>, %X9<kill>, 6; mem:ST4[%rNToGo266]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X10<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = LDRWui %X9<kill>, 6; mem:LD4[%rNToGo268]
> %W11<def> = LDRWui %X10, 16; mem:LD4[%k0272]
> %WZR<def> = SUBSWri %W9<kill>, 1, 0, %NZCV<imp-def>
> %W9<def> = MOVi32imm 1
> %W8<def> = CSELWr %W9<kill>, %W8<kill>, 0, %NZCV<imp-use>
> %W8<def> = EORWrr %W11<kill>, %W8<kill>
> STRWui %W8<kill>, %X10<kill>, 16; mem:ST4[%k0272]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = LDRWui %X8, 273; mem:LD4[%nblock_used274]
> %W9<def> = ADDWri %W9<kill>, 1, 0
> STRWui %W9<kill>, %X8<kill>, 273; mem:ST4[%nblock_used274]
> B <BB#2>
8704B	BB#47: derived from LLVM BB %if.else
	    Live Ins: %X19
	    Predecessors according to CFG: BB#0
8720B		%vreg61<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg61
8736B		%vreg60<def> = LDRWui %vreg61<kill>, 796; mem:LD4[%calculatedBlockCRC276] GPR32:%vreg60 GPR64common:%vreg61
8752B		STRWui %vreg60<kill>, <fi#3>, 0; mem:ST4[FixedStack3] GPR32:%vreg60
8768B		%vreg57<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg57
8784B		%vreg56<def> = LDRBBui %vreg57<kill>, 12; mem:LD1[%state_out_ch277] GPR32:%vreg56 GPR64common:%vreg57
8800B		STRBBui %vreg56<kill>, <fi#4>, 0; mem:ST1[FixedStack4] GPR32:%vreg56
8816B		%vreg53<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg53
8832B		%vreg52<def> = LDRWui %vreg53<kill>, 4; mem:LD4[%state_out_len278] GPR32:%vreg52 GPR64common:%vreg53
8848B		STRWui %vreg52<kill>, <fi#5>, 0; mem:ST4[FixedStack5] GPR32:%vreg52
8864B		%vreg49<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg49
8880B		%vreg48<def> = LDRWui %vreg49<kill>, 273; mem:LD4[%nblock_used279] GPR32:%vreg48 GPR64common:%vreg49
8896B		STRWui %vreg48<kill>, <fi#6>, 0; mem:ST4[FixedStack6] GPR32:%vreg48
8912B		%vreg45<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg45
8928B		%vreg44<def> = LDRWui %vreg45<kill>, 16; mem:LD4[%k0280] GPR32:%vreg44 GPR64common:%vreg45
8944B		STRWui %vreg44<kill>, <fi#7>, 0; mem:ST4[FixedStack7] GPR32:%vreg44
8960B		%vreg41<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg41
8976B		%vreg40<def> = LDRXui %vreg41<kill>, 394; mem:LD8[%tt281] GPR64:%vreg40 GPR64common:%vreg41
8992B		STRXui %vreg40<kill>, <fi#8>, 0; mem:ST8[FixedStack8] GPR64:%vreg40
9008B		%vreg37<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg37
9024B		%vreg36<def> = LDRWui %vreg37<kill>, 15; mem:LD4[%tPos282] GPR32:%vreg36 GPR64common:%vreg37
9040B		STRWui %vreg36<kill>, <fi#9>, 0; mem:ST4[FixedStack9] GPR32:%vreg36
9056B		%vreg33<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg33
9072B		%vreg32<def> = LDRXui %vreg33<kill>, 0; mem:LD8[%strm283] GPR64common:%vreg32,%vreg33
9088B		%vreg30<def> = LDRXui %vreg32<kill>, 3; mem:LD8[%next_out284] GPR64:%vreg30 GPR64common:%vreg32
9104B		STRXui %vreg30<kill>, <fi#10>, 0; mem:ST8[FixedStack10] GPR64:%vreg30
9120B		%vreg27<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg27
9136B		%vreg26<def> = LDRXui %vreg27<kill>, 0; mem:LD8[%strm285] GPR64common:%vreg26,%vreg27
9152B		%vreg24<def> = LDRWui %vreg26<kill>, 8; mem:LD4[%avail_out286] GPR32:%vreg24 GPR64common:%vreg26
9168B		STRWui %vreg24<kill>, <fi#11>, 0; mem:ST4[FixedStack11] GPR32:%vreg24
9184B		%vreg21<def> = LDRWui <fi#11>, 0; mem:LD4[FixedStack11] GPR32:%vreg21
9200B		STRWui %vreg21<kill>, <fi#12>, 0; mem:ST4[FixedStack12] GPR32:%vreg21
9216B		%vreg19<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg19
9232B		%vreg16<def> = MOVi64imm 64080; GPR64:%vreg16
9248B		%vreg17<def> = ADDXrr %vreg19<kill>, %vreg16<kill>; GPR64common:%vreg17 GPR64:%vreg19,%vreg16
9264B		%vreg18<def> = LDRWui %vreg17<kill>, 0; mem:LD4[%save_nblock287] GPR32common:%vreg18 GPR64common:%vreg17
9280B		%vreg14<def> = ADDWri %vreg18<kill>, 1, 0; GPR32common:%vreg14,%vreg18
9296B		STRWui %vreg14<kill>, <fi#13>, 0; mem:ST4[FixedStack13] GPR32common:%vreg14
	    Successors according to CFG: BB#48
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W8<def> = LDRWui %X8<kill>, 796; mem:LD4[%calculatedBlockCRC276]
> STRWui %W8<kill>, <fi#3>, 0; mem:ST4[FixedStack3]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W8<def> = LDRBBui %X8<kill>, 12; mem:LD1[%state_out_ch277]
> STRBBui %W8<kill>, <fi#4>, 0; mem:ST1[FixedStack4]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W8<def> = LDRWui %X8<kill>, 4; mem:LD4[%state_out_len278]
> STRWui %W8<kill>, <fi#5>, 0; mem:ST4[FixedStack5]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W8<def> = LDRWui %X8<kill>, 273; mem:LD4[%nblock_used279]
> STRWui %W8<kill>, <fi#6>, 0; mem:ST4[FixedStack6]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W8<def> = LDRWui %X8<kill>, 16; mem:LD4[%k0280]
> STRWui %W8<kill>, <fi#7>, 0; mem:ST4[FixedStack7]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X8<def> = LDRXui %X8<kill>, 394; mem:LD8[%tt281]
> STRXui %X8<kill>, <fi#8>, 0; mem:ST8[FixedStack8]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W8<def> = LDRWui %X8<kill>, 15; mem:LD4[%tPos282]
> STRWui %W8<kill>, <fi#9>, 0; mem:ST4[FixedStack9]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X8<def> = LDRXui %X8<kill>, 0; mem:LD8[%strm283]
> %X8<def> = LDRXui %X8<kill>, 3; mem:LD8[%next_out284]
> STRXui %X8<kill>, <fi#10>, 0; mem:ST8[FixedStack10]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X8<def> = LDRXui %X8<kill>, 0; mem:LD8[%strm285]
> %W8<def> = LDRWui %X8<kill>, 8; mem:LD4[%avail_out286]
> STRWui %W8<kill>, <fi#11>, 0; mem:ST4[FixedStack11]
> %W8<def> = LDRWui <fi#11>, 0; mem:LD4[FixedStack11]
> STRWui %W8<kill>, <fi#12>, 0; mem:ST4[FixedStack12]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X9<def> = MOVi64imm 64080
> %X8<def> = ADDXrr %X8<kill>, %X9<kill>
> %W8<def> = LDRWui %X8<kill>, 0; mem:LD4[%save_nblock287]
> %W8<def> = ADDWri %W8<kill>, 1, 0
> STRWui %W8<kill>, <fi#13>, 0; mem:ST4[FixedStack13]
9312B	BB#48: derived from LLVM BB %while.body.289
	    Live Ins: %X19
	    Predecessors according to CFG: BB#47 BB#75 BB#74 BB#72 BB#70 BB#68
9328B		%vreg63<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32common:%vreg63
9344B		%WZR<def> = SUBSWri %vreg63<kill>, 0, 0, %NZCV<imp-def>; GPR32common:%vreg63
9360B		Bcc 13, <BB#59>, %NZCV<imp-use>
	    Successors according to CFG: BB#59 BB#49
> %W8<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5]
> %WZR<def> = SUBSWri %W8<kill>, 0, 0, %NZCV<imp-def>
> Bcc 13, <BB#59>, %NZCV<imp-use>
9376B	BB#49: derived from LLVM BB %if.then.292
	    Live Ins: %X19
	    Predecessors according to CFG: BB#48
9392B		B <BB#50>
	    Successors according to CFG: BB#50
> B <BB#50>
9408B	BB#50: derived from LLVM BB %while.body.294
	    Live Ins: %X19
	    Predecessors according to CFG: BB#49 BB#54
9424B		%vreg65<def> = LDRWui <fi#11>, 0; mem:LD4[FixedStack11] GPR32:%vreg65
9440B		CBNZW %vreg65<kill>, <BB#52>; GPR32:%vreg65
	    Successors according to CFG: BB#52 BB#51
> %W8<def> = LDRWui <fi#11>, 0; mem:LD4[FixedStack11]
> CBNZW %W8<kill>, <BB#52>
9456B	BB#51: derived from LLVM BB %if.then.297
	    Live Ins: %X19
	    Predecessors according to CFG: BB#50
9472B		B <BB#76>
	    Successors according to CFG: BB#76
> B <BB#76>
9488B	BB#52: derived from LLVM BB %if.end.298
	    Live Ins: %X19
	    Predecessors according to CFG: BB#50
9504B		%vreg67<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32common:%vreg67
9520B		%WZR<def> = SUBSWri %vreg67<kill>, 1, 0, %NZCV<imp-def>; GPR32common:%vreg67
9536B		Bcc 1, <BB#54>, %NZCV<imp-use>
	    Successors according to CFG: BB#54 BB#53
> %W8<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5]
> %WZR<def> = SUBSWri %W8<kill>, 1, 0, %NZCV<imp-def>
> Bcc 1, <BB#54>, %NZCV<imp-use>
9552B	BB#53: derived from LLVM BB %if.then.301
	    Live Ins: %X19
	    Predecessors according to CFG: BB#52
9568B		B <BB#55>
	    Successors according to CFG: BB#55
> B <BB#55>
9584B	BB#54: derived from LLVM BB %if.end.302
	    Live Ins: %X19
	    Predecessors according to CFG: BB#52
9632B		%vreg108<def> = LDRBBui <fi#4>, 0; mem:LD1[FixedStack4] GPR32:%vreg108
9648B		%vreg107<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg107
9656B		%vreg86<def> = ADRP <ga:@BZ2_crc32Table>[TF=1]; GPR64common:%vreg86
9664B		STRBBui %vreg108<kill>, %vreg107<kill>, 0; mem:ST1[%249] GPR32:%vreg108 GPR64common:%vreg107
9696B		%vreg103<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg103
9728B		%vreg100<def> = LDRBBui <fi#4>, 0; mem:LD1[FixedStack4] GPR32:%vreg100
9736B		%vreg87<def> = ADDXri %vreg86<kill>, <ga:@BZ2_crc32Table>[TF=34], 0; GPR64common:%vreg87,%vreg86
9744B		%vreg104<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg104
9752B		%vreg102<def> = UBFMWri %vreg103<kill>, 24, 31; GPR32:%vreg102,%vreg103
9760B		%vreg93:sub_32<def,read-undef> = EORWrr %vreg102<kill>, %vreg100<kill>; GPR64:%vreg93 GPR32:%vreg102,%vreg100
9776B		%vreg94<def> = UBFMXri %vreg93<kill>, 0, 31; GPR64:%vreg94,%vreg93
9792B		%vreg89<def> = MOVi64imm 4; GPR64:%vreg89
9808B		%vreg90<def> = MADDXrrr %vreg94<kill>, %vreg89<kill>, %XZR; GPR64:%vreg90,%vreg94,%vreg89
9824B		%vreg91<def> = ADDXrr %vreg87<kill>, %vreg90<kill>; GPR64common:%vreg91,%vreg87 GPR64:%vreg90
9840B		%vreg85<def> = LDRWui %vreg91<kill>, 0; mem:LD4[%arrayidx308] GPR32:%vreg85 GPR64common:%vreg91
9856B		%vreg83<def> = EORWrs %vreg85<kill>, %vreg104<kill>, 8; GPR32:%vreg83,%vreg85,%vreg104
9872B		STRWui %vreg83<kill>, <fi#3>, 0; mem:ST4[FixedStack3] GPR32:%vreg83
9888B		%vreg79<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32common:%vreg79
9904B		%vreg78<def> = SUBWri %vreg79<kill>, 1, 0; GPR32common:%vreg78,%vreg79
9920B		STRWui %vreg78<kill>, <fi#5>, 0; mem:ST4[FixedStack5] GPR32common:%vreg78
9936B		%vreg75<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg75
9952B		%vreg74<def> = ADDXri %vreg75<kill>, 1, 0; GPR64common:%vreg74,%vreg75
9968B		STRXui %vreg74<kill>, <fi#10>, 0; mem:ST8[FixedStack10] GPR64common:%vreg74
9984B		%vreg71<def> = LDRWui <fi#11>, 0; mem:LD4[FixedStack11] GPR32common:%vreg71
10000B		%vreg70<def> = SUBWri %vreg71<kill>, 1, 0; GPR32common:%vreg70,%vreg71
10016B		STRWui %vreg70<kill>, <fi#11>, 0; mem:ST4[FixedStack11] GPR32common:%vreg70
10032B		B <BB#50>
	    Successors according to CFG: BB#50
> %W8<def> = LDRBBui <fi#4>, 0; mem:LD1[FixedStack4]
> %X9<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10]
> %X10<def> = ADRP <ga:@BZ2_crc32Table>[TF=1]
> STRBBui %W8<kill>, %X9<kill>, 0; mem:ST1[%249]
> %W8<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3]
> %W9<def> = LDRBBui <fi#4>, 0; mem:LD1[FixedStack4]
> %X10<def> = ADDXri %X10<kill>, <ga:@BZ2_crc32Table>[TF=34], 0
> %W11<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3]
> %W8<def> = UBFMWri %W8<kill>, 24, 31
> %W8<def> = EORWrr %W8<kill>, %W9<kill>, %X8<imp-def>
> %X8<def> = UBFMXri %X8<kill>, 0, 31
> %X9<def> = MOVi64imm 4
> %X8<def> = MADDXrrr %X8<kill>, %X9<kill>, %XZR
> %X8<def> = ADDXrr %X10<kill>, %X8<kill>
> %W8<def> = LDRWui %X8<kill>, 0; mem:LD4[%arrayidx308]
> %W8<def> = EORWrs %W8<kill>, %W11<kill>, 8
> STRWui %W8<kill>, <fi#3>, 0; mem:ST4[FixedStack3]
> %W8<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5]
> %W8<def> = SUBWri %W8<kill>, 1, 0
> STRWui %W8<kill>, <fi#5>, 0; mem:ST4[FixedStack5]
> %X8<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10]
> %X8<def> = ADDXri %X8<kill>, 1, 0
> STRXui %X8<kill>, <fi#10>, 0; mem:ST8[FixedStack10]
> %W8<def> = LDRWui <fi#11>, 0; mem:LD4[FixedStack11]
> %W8<def> = SUBWri %W8<kill>, 1, 0
> STRWui %W8<kill>, <fi#11>, 0; mem:ST4[FixedStack11]
> B <BB#50>
10048B	BB#55: derived from LLVM BB %while.end.313
	    Live Ins: %X19
	    Predecessors according to CFG: BB#53
10064B		B <BB#56>
	    Successors according to CFG: BB#56
> B <BB#56>
10080B	BB#56: derived from LLVM BB %s_state_out_len_eq_one
	    Live Ins: %X19
	    Predecessors according to CFG: BB#55 BB#66 BB#64
10096B		%vreg110<def> = LDRWui <fi#11>, 0; mem:LD4[FixedStack11] GPR32:%vreg110
10112B		CBNZW %vreg110<kill>, <BB#58>; GPR32:%vreg110
	    Successors according to CFG: BB#58 BB#57
> %W8<def> = LDRWui <fi#11>, 0; mem:LD4[FixedStack11]
> CBNZW %W8<kill>, <BB#58>
10128B	BB#57: derived from LLVM BB %if.then.316
	    Live Ins: %X19
	    Predecessors according to CFG: BB#56
10144B		%vreg353<def> = MOVi32imm 1; GPR32:%vreg353
10160B		STRWui %vreg353<kill>, <fi#5>, 0; mem:ST4[FixedStack5] GPR32:%vreg353
10176B		B <BB#76>
	    Successors according to CFG: BB#76
> %W8<def> = MOVi32imm 1
> STRWui %W8<kill>, <fi#5>, 0; mem:ST4[FixedStack5]
> B <BB#76>
10192B	BB#58: derived from LLVM BB %if.end.317
	    Live Ins: %X19
	    Predecessors according to CFG: BB#56
10240B		%vreg147<def> = LDRBBui <fi#4>, 0; mem:LD1[FixedStack4] GPR32:%vreg147
10256B		%vreg146<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg146
10264B		%vreg125<def> = ADRP <ga:@BZ2_crc32Table>[TF=1]; GPR64common:%vreg125
10272B		STRBBui %vreg147<kill>, %vreg146<kill>, 0; mem:ST1[%259] GPR32:%vreg147 GPR64common:%vreg146
10304B		%vreg142<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg142
10336B		%vreg139<def> = LDRBBui <fi#4>, 0; mem:LD1[FixedStack4] GPR32:%vreg139
10344B		%vreg126<def> = ADDXri %vreg125<kill>, <ga:@BZ2_crc32Table>[TF=34], 0; GPR64common:%vreg126,%vreg125
10352B		%vreg143<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg143
10360B		%vreg141<def> = UBFMWri %vreg142<kill>, 24, 31; GPR32:%vreg141,%vreg142
10368B		%vreg132:sub_32<def,read-undef> = EORWrr %vreg141<kill>, %vreg139<kill>; GPR64:%vreg132 GPR32:%vreg141,%vreg139
10384B		%vreg133<def> = UBFMXri %vreg132<kill>, 0, 31; GPR64:%vreg133,%vreg132
10400B		%vreg128<def> = MOVi64imm 4; GPR64:%vreg128
10416B		%vreg129<def> = MADDXrrr %vreg133<kill>, %vreg128<kill>, %XZR; GPR64:%vreg129,%vreg133,%vreg128
10432B		%vreg130<def> = ADDXrr %vreg126<kill>, %vreg129<kill>; GPR64common:%vreg130,%vreg126 GPR64:%vreg129
10448B		%vreg124<def> = LDRWui %vreg130<kill>, 0; mem:LD4[%arrayidx323] GPR32:%vreg124 GPR64common:%vreg130
10464B		%vreg122<def> = EORWrs %vreg124<kill>, %vreg143<kill>, 8; GPR32:%vreg122,%vreg124,%vreg143
10480B		STRWui %vreg122<kill>, <fi#3>, 0; mem:ST4[FixedStack3] GPR32:%vreg122
10496B		%vreg118<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg118
10512B		%vreg117<def> = ADDXri %vreg118<kill>, 1, 0; GPR64common:%vreg117,%vreg118
10528B		STRXui %vreg117<kill>, <fi#10>, 0; mem:ST8[FixedStack10] GPR64common:%vreg117
10544B		%vreg114<def> = LDRWui <fi#11>, 0; mem:LD4[FixedStack11] GPR32common:%vreg114
10560B		%vreg113<def> = SUBWri %vreg114<kill>, 1, 0; GPR32common:%vreg113,%vreg114
10576B		STRWui %vreg113<kill>, <fi#11>, 0; mem:ST4[FixedStack11] GPR32common:%vreg113
	    Successors according to CFG: BB#59
> %W8<def> = LDRBBui <fi#4>, 0; mem:LD1[FixedStack4]
> %X9<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10]
> %X10<def> = ADRP <ga:@BZ2_crc32Table>[TF=1]
> STRBBui %W8<kill>, %X9<kill>, 0; mem:ST1[%259]
> %W8<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3]
> %W9<def> = LDRBBui <fi#4>, 0; mem:LD1[FixedStack4]
> %X10<def> = ADDXri %X10<kill>, <ga:@BZ2_crc32Table>[TF=34], 0
> %W11<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3]
> %W8<def> = UBFMWri %W8<kill>, 24, 31
> %W8<def> = EORWrr %W8<kill>, %W9<kill>, %X8<imp-def>
> %X8<def> = UBFMXri %X8<kill>, 0, 31
> %X9<def> = MOVi64imm 4
> %X8<def> = MADDXrrr %X8<kill>, %X9<kill>, %XZR
> %X8<def> = ADDXrr %X10<kill>, %X8<kill>
> %W8<def> = LDRWui %X8<kill>, 0; mem:LD4[%arrayidx323]
> %W8<def> = EORWrs %W8<kill>, %W11<kill>, 8
> STRWui %W8<kill>, <fi#3>, 0; mem:ST4[FixedStack3]
> %X8<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10]
> %X8<def> = ADDXri %X8<kill>, 1, 0
> STRXui %X8<kill>, <fi#10>, 0; mem:ST8[FixedStack10]
> %W8<def> = LDRWui <fi#11>, 0; mem:LD4[FixedStack11]
> %W8<def> = SUBWri %W8<kill>, 1, 0
> STRWui %W8<kill>, <fi#11>, 0; mem:ST4[FixedStack11]
10592B	BB#59: derived from LLVM BB %if.end.327
	    Live Ins: %X19
	    Predecessors according to CFG: BB#48 BB#58
10608B		%vreg151<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg151
10624B		%vreg150<def> = LDRWui <fi#13>, 0; mem:LD4[FixedStack13] GPR32:%vreg150
10640B		%WZR<def> = SUBSWrr %vreg151<kill>, %vreg150<kill>, %NZCV<imp-def>; GPR32:%vreg151,%vreg150
10656B		Bcc 13, <BB#61>, %NZCV<imp-use>
	    Successors according to CFG: BB#61 BB#60
> %W8<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6]
> %W9<def> = LDRWui <fi#13>, 0; mem:LD4[FixedStack13]
> %WZR<def> = SUBSWrr %W8<kill>, %W9<kill>, %NZCV<imp-def>
> Bcc 13, <BB#61>, %NZCV<imp-use>
10672B	BB#60: derived from LLVM BB %if.then.330
	    Live Ins: %X19
	    Predecessors according to CFG: BB#59
10688B		%vreg352<def> = MOVi32imm 1; GPR32:%vreg352
10704B		STRBBui %vreg352<kill>, <fi#0>, 0; mem:ST1[FixedStack0] GPR32:%vreg352
10720B		B <BB#80>
	    Successors according to CFG: BB#80
> %W8<def> = MOVi32imm 1
> STRBBui %W8<kill>, <fi#0>, 0; mem:ST1[FixedStack0]
> B <BB#80>
10736B	BB#61: derived from LLVM BB %if.end.331
	    Live Ins: %X19
	    Predecessors according to CFG: BB#59
10752B		%vreg155<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg155
10768B		%vreg154<def> = LDRWui <fi#13>, 0; mem:LD4[FixedStack13] GPR32:%vreg154
10784B		%WZR<def> = SUBSWrr %vreg155<kill>, %vreg154<kill>, %NZCV<imp-def>; GPR32:%vreg155,%vreg154
10800B		Bcc 1, <BB#63>, %NZCV<imp-use>
	    Successors according to CFG: BB#63 BB#62
> %W8<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6]
> %W9<def> = LDRWui <fi#13>, 0; mem:LD4[FixedStack13]
> %WZR<def> = SUBSWrr %W8<kill>, %W9<kill>, %NZCV<imp-def>
> Bcc 1, <BB#63>, %NZCV<imp-use>
10816B	BB#62: derived from LLVM BB %if.then.334
	    Live Ins: %X19
	    Predecessors according to CFG: BB#61
10832B		STRWui %WZR, <fi#5>, 0; mem:ST4[FixedStack5]
10848B		B <BB#76>
	    Successors according to CFG: BB#76
> STRWui %WZR, <fi#5>, 0; mem:ST4[FixedStack5]
> B <BB#76>
10864B	BB#63: derived from LLVM BB %if.end.335
	    Live Ins: %X19
	    Predecessors according to CFG: BB#61
10880B		%vreg192<def> = LDRWui <fi#7>, 0; mem:LD4[FixedStack7] GPR32:%vreg192
10912B		STRBBui %vreg192<kill>, <fi#4>, 0; mem:ST1[FixedStack4] GPR32:%vreg192
10928B		%vreg189:sub_32<def,read-undef> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR64:%vreg189
10960B		%vreg184<def> = LDRXui <fi#8>, 0; mem:LD8[FixedStack8] GPR64:%vreg184
10976B		%vreg181<def> = MOVi64imm 4; GPR64:%vreg181
10992B		%vreg182<def> = MADDXrrr %vreg189<kill>, %vreg181<kill>, %XZR; GPR64:%vreg182,%vreg189,%vreg181
11008B		%vreg183<def> = ADDXrr %vreg184<kill>, %vreg182<kill>; GPR64common:%vreg183 GPR64:%vreg184,%vreg182
11024B		%vreg178<def> = LDRWui %vreg183<kill>, 0; mem:LD4[%arrayidx338] GPR32:%vreg178 GPR64common:%vreg183
11040B		STRWui %vreg178<kill>, <fi#9>, 0; mem:ST4[FixedStack9] GPR32:%vreg178
11056B		%vreg175<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32:%vreg175
11072B		%vreg172<def> = ANDWri %vreg175<kill>, 7; GPR32common:%vreg172 GPR32:%vreg175
11104B		STRBBui %vreg172<kill>, <fi#2>, 0; mem:ST1[FixedStack2] GPR32common:%vreg172
11120B		%vreg169<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32:%vreg169
11136B		%vreg168<def> = UBFMWri %vreg169<kill>, 8, 31; GPR32:%vreg168,%vreg169
11152B		STRWui %vreg168<kill>, <fi#9>, 0; mem:ST4[FixedStack9] GPR32:%vreg168
11168B		%vreg165<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32common:%vreg165
11184B		%vreg164<def> = ADDWri %vreg165<kill>, 1, 0; GPR32common:%vreg164,%vreg165
11200B		STRWui %vreg164<kill>, <fi#6>, 0; mem:ST4[FixedStack6] GPR32common:%vreg164
11216B		%vreg161<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg161
11232B		%vreg158<def> = LDRWui <fi#7>, 0; mem:LD4[FixedStack7] GPR32:%vreg158
11248B		%WZR<def> = SUBSWrr %vreg161<kill>, %vreg158<kill>, %NZCV<imp-def>; GPR32:%vreg161,%vreg158
11264B		Bcc 0, <BB#65>, %NZCV<imp-use>
	    Successors according to CFG: BB#65 BB#64
> %W8<def> = LDRWui <fi#7>, 0; mem:LD4[FixedStack7]
> STRBBui %W8<kill>, <fi#4>, 0; mem:ST1[FixedStack4]
> %W8<def> = LDRWui <fi#9>, 0, %X8<imp-def>; mem:LD4[FixedStack9]
> %X9<def> = LDRXui <fi#8>, 0; mem:LD8[FixedStack8]
> %X10<def> = MOVi64imm 4
> %X8<def> = MADDXrrr %X8<kill>, %X10<kill>, %XZR
> %X8<def> = ADDXrr %X9<kill>, %X8<kill>
> %W8<def> = LDRWui %X8<kill>, 0; mem:LD4[%arrayidx338]
> STRWui %W8<kill>, <fi#9>, 0; mem:ST4[FixedStack9]
> %W8<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9]
> %W8<def> = ANDWri %W8<kill>, 7
> STRBBui %W8<kill>, <fi#2>, 0; mem:ST1[FixedStack2]
> %W8<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9]
> %W8<def> = UBFMWri %W8<kill>, 8, 31
> STRWui %W8<kill>, <fi#9>, 0; mem:ST4[FixedStack9]
> %W8<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6]
> %W8<def> = ADDWri %W8<kill>, 1, 0
> STRWui %W8<kill>, <fi#6>, 0; mem:ST4[FixedStack6]
> %W8<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2]
> %W9<def> = LDRWui <fi#7>, 0; mem:LD4[FixedStack7]
> %WZR<def> = SUBSWrr %W8<kill>, %W9<kill>, %NZCV<imp-def>
> Bcc 0, <BB#65>, %NZCV<imp-use>
11280B	BB#64: derived from LLVM BB %if.then.346
	    Live Ins: %X19
	    Predecessors according to CFG: BB#63
11296B		%vreg351<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg351
11312B		STRWui %vreg351<kill>, <fi#7>, 0; mem:ST4[FixedStack7] GPR32:%vreg351
11328B		B <BB#56>
	    Successors according to CFG: BB#56
> %W8<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2]
> STRWui %W8<kill>, <fi#7>, 0; mem:ST4[FixedStack7]
> B <BB#56>
11344B	BB#65: derived from LLVM BB %if.end.348
	    Live Ins: %X19
	    Predecessors according to CFG: BB#63
11360B		%vreg197<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg197
11376B		%vreg196<def> = LDRWui <fi#13>, 0; mem:LD4[FixedStack13] GPR32:%vreg196
11392B		%WZR<def> = SUBSWrr %vreg197<kill>, %vreg196<kill>, %NZCV<imp-def>; GPR32:%vreg197,%vreg196
11408B		Bcc 1, <BB#67>, %NZCV<imp-use>
	    Successors according to CFG: BB#67 BB#66
> %W8<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6]
> %W9<def> = LDRWui <fi#13>, 0; mem:LD4[FixedStack13]
> %WZR<def> = SUBSWrr %W8<kill>, %W9<kill>, %NZCV<imp-def>
> Bcc 1, <BB#67>, %NZCV<imp-use>
11424B	BB#66: derived from LLVM BB %if.then.351
	    Live Ins: %X19
	    Predecessors according to CFG: BB#65
11440B		B <BB#56>
	    Successors according to CFG: BB#56
> B <BB#56>
11456B	BB#67: derived from LLVM BB %if.end.352
	    Live Ins: %X19
	    Predecessors according to CFG: BB#65
11472B		%vreg230<def> = MOVi32imm 2; GPR32:%vreg230
11488B		STRWui %vreg230<kill>, <fi#5>, 0; mem:ST4[FixedStack5] GPR32:%vreg230
11504B		%vreg229:sub_32<def,read-undef> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR64:%vreg229
11536B		%vreg224<def> = LDRXui <fi#8>, 0; mem:LD8[FixedStack8] GPR64:%vreg224
11552B		%vreg221<def> = MOVi64imm 4; GPR64:%vreg221
11568B		%vreg222<def> = MADDXrrr %vreg229<kill>, %vreg221<kill>, %XZR; GPR64:%vreg222,%vreg229,%vreg221
11584B		%vreg223<def> = ADDXrr %vreg224<kill>, %vreg222<kill>; GPR64common:%vreg223 GPR64:%vreg224,%vreg222
11600B		%vreg218<def> = LDRWui %vreg223<kill>, 0; mem:LD4[%arrayidx354] GPR32:%vreg218 GPR64common:%vreg223
11616B		STRWui %vreg218<kill>, <fi#9>, 0; mem:ST4[FixedStack9] GPR32:%vreg218
11632B		%vreg215<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32:%vreg215
11648B		%vreg212<def> = ANDWri %vreg215<kill>, 7; GPR32common:%vreg212 GPR32:%vreg215
11680B		STRBBui %vreg212<kill>, <fi#2>, 0; mem:ST1[FixedStack2] GPR32common:%vreg212
11696B		%vreg209<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32:%vreg209
11712B		%vreg208<def> = UBFMWri %vreg209<kill>, 8, 31; GPR32:%vreg208,%vreg209
11728B		STRWui %vreg208<kill>, <fi#9>, 0; mem:ST4[FixedStack9] GPR32:%vreg208
11744B		%vreg205<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32common:%vreg205
11760B		%vreg204<def> = ADDWri %vreg205<kill>, 1, 0; GPR32common:%vreg204,%vreg205
11776B		STRWui %vreg204<kill>, <fi#6>, 0; mem:ST4[FixedStack6] GPR32common:%vreg204
11792B		%vreg201<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg201
11808B		%vreg200<def> = LDRWui <fi#13>, 0; mem:LD4[FixedStack13] GPR32:%vreg200
11824B		%WZR<def> = SUBSWrr %vreg201<kill>, %vreg200<kill>, %NZCV<imp-def>; GPR32:%vreg201,%vreg200
11840B		Bcc 1, <BB#69>, %NZCV<imp-use>
	    Successors according to CFG: BB#69 BB#68
> %W8<def> = MOVi32imm 2
> STRWui %W8<kill>, <fi#5>, 0; mem:ST4[FixedStack5]
> %W8<def> = LDRWui <fi#9>, 0, %X8<imp-def>; mem:LD4[FixedStack9]
> %X9<def> = LDRXui <fi#8>, 0; mem:LD8[FixedStack8]
> %X10<def> = MOVi64imm 4
> %X8<def> = MADDXrrr %X8<kill>, %X10<kill>, %XZR
> %X8<def> = ADDXrr %X9<kill>, %X8<kill>
> %W8<def> = LDRWui %X8<kill>, 0; mem:LD4[%arrayidx354]
> STRWui %W8<kill>, <fi#9>, 0; mem:ST4[FixedStack9]
> %W8<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9]
> %W8<def> = ANDWri %W8<kill>, 7
> STRBBui %W8<kill>, <fi#2>, 0; mem:ST1[FixedStack2]
> %W8<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9]
> %W8<def> = UBFMWri %W8<kill>, 8, 31
> STRWui %W8<kill>, <fi#9>, 0; mem:ST4[FixedStack9]
> %W8<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6]
> %W8<def> = ADDWri %W8<kill>, 1, 0
> STRWui %W8<kill>, <fi#6>, 0; mem:ST4[FixedStack6]
> %W8<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6]
> %W9<def> = LDRWui <fi#13>, 0; mem:LD4[FixedStack13]
> %WZR<def> = SUBSWrr %W8<kill>, %W9<kill>, %NZCV<imp-def>
> Bcc 1, <BB#69>, %NZCV<imp-use>
11856B	BB#68: derived from LLVM BB %if.then.361
	    Live Ins: %X19
	    Predecessors according to CFG: BB#67
11872B		B <BB#48>
	    Successors according to CFG: BB#48
> B <BB#48>
11888B	BB#69: derived from LLVM BB %if.end.362
	    Live Ins: %X19
	    Predecessors according to CFG: BB#67
11904B		%vreg236<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg236
11920B		%vreg233<def> = LDRWui <fi#7>, 0; mem:LD4[FixedStack7] GPR32:%vreg233
11936B		%WZR<def> = SUBSWrr %vreg236<kill>, %vreg233<kill>, %NZCV<imp-def>; GPR32:%vreg236,%vreg233
11952B		Bcc 0, <BB#71>, %NZCV<imp-use>
	    Successors according to CFG: BB#71 BB#70
> %W8<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2]
> %W9<def> = LDRWui <fi#7>, 0; mem:LD4[FixedStack7]
> %WZR<def> = SUBSWrr %W8<kill>, %W9<kill>, %NZCV<imp-def>
> Bcc 0, <BB#71>, %NZCV<imp-use>
11968B	BB#70: derived from LLVM BB %if.then.366
	    Live Ins: %X19
	    Predecessors according to CFG: BB#69
11984B		%vreg347<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg347
12000B		STRWui %vreg347<kill>, <fi#7>, 0; mem:ST4[FixedStack7] GPR32:%vreg347
12016B		B <BB#48>
	    Successors according to CFG: BB#48
> %W8<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2]
> STRWui %W8<kill>, <fi#7>, 0; mem:ST4[FixedStack7]
> B <BB#48>
12032B	BB#71: derived from LLVM BB %if.end.368
	    Live Ins: %X19
	    Predecessors according to CFG: BB#69
12048B		%vreg269<def> = MOVi32imm 3; GPR32:%vreg269
12064B		STRWui %vreg269<kill>, <fi#5>, 0; mem:ST4[FixedStack5] GPR32:%vreg269
12080B		%vreg268:sub_32<def,read-undef> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR64:%vreg268
12112B		%vreg263<def> = LDRXui <fi#8>, 0; mem:LD8[FixedStack8] GPR64:%vreg263
12128B		%vreg260<def> = MOVi64imm 4; GPR64:%vreg260
12144B		%vreg261<def> = MADDXrrr %vreg268<kill>, %vreg260<kill>, %XZR; GPR64:%vreg261,%vreg268,%vreg260
12160B		%vreg262<def> = ADDXrr %vreg263<kill>, %vreg261<kill>; GPR64common:%vreg262 GPR64:%vreg263,%vreg261
12176B		%vreg257<def> = LDRWui %vreg262<kill>, 0; mem:LD4[%arrayidx370] GPR32:%vreg257 GPR64common:%vreg262
12192B		STRWui %vreg257<kill>, <fi#9>, 0; mem:ST4[FixedStack9] GPR32:%vreg257
12208B		%vreg254<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32:%vreg254
12224B		%vreg251<def> = ANDWri %vreg254<kill>, 7; GPR32common:%vreg251 GPR32:%vreg254
12256B		STRBBui %vreg251<kill>, <fi#2>, 0; mem:ST1[FixedStack2] GPR32common:%vreg251
12272B		%vreg248<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32:%vreg248
12288B		%vreg247<def> = UBFMWri %vreg248<kill>, 8, 31; GPR32:%vreg247,%vreg248
12304B		STRWui %vreg247<kill>, <fi#9>, 0; mem:ST4[FixedStack9] GPR32:%vreg247
12320B		%vreg244<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32common:%vreg244
12336B		%vreg243<def> = ADDWri %vreg244<kill>, 1, 0; GPR32common:%vreg243,%vreg244
12352B		STRWui %vreg243<kill>, <fi#6>, 0; mem:ST4[FixedStack6] GPR32common:%vreg243
12368B		%vreg240<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg240
12384B		%vreg239<def> = LDRWui <fi#13>, 0; mem:LD4[FixedStack13] GPR32:%vreg239
12400B		%WZR<def> = SUBSWrr %vreg240<kill>, %vreg239<kill>, %NZCV<imp-def>; GPR32:%vreg240,%vreg239
12416B		Bcc 1, <BB#73>, %NZCV<imp-use>
	    Successors according to CFG: BB#73 BB#72
> %W8<def> = MOVi32imm 3
> STRWui %W8<kill>, <fi#5>, 0; mem:ST4[FixedStack5]
> %W8<def> = LDRWui <fi#9>, 0, %X8<imp-def>; mem:LD4[FixedStack9]
> %X9<def> = LDRXui <fi#8>, 0; mem:LD8[FixedStack8]
> %X10<def> = MOVi64imm 4
> %X8<def> = MADDXrrr %X8<kill>, %X10<kill>, %XZR
> %X8<def> = ADDXrr %X9<kill>, %X8<kill>
> %W8<def> = LDRWui %X8<kill>, 0; mem:LD4[%arrayidx370]
> STRWui %W8<kill>, <fi#9>, 0; mem:ST4[FixedStack9]
> %W8<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9]
> %W8<def> = ANDWri %W8<kill>, 7
> STRBBui %W8<kill>, <fi#2>, 0; mem:ST1[FixedStack2]
> %W8<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9]
> %W8<def> = UBFMWri %W8<kill>, 8, 31
> STRWui %W8<kill>, <fi#9>, 0; mem:ST4[FixedStack9]
> %W8<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6]
> %W8<def> = ADDWri %W8<kill>, 1, 0
> STRWui %W8<kill>, <fi#6>, 0; mem:ST4[FixedStack6]
> %W8<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6]
> %W9<def> = LDRWui <fi#13>, 0; mem:LD4[FixedStack13]
> %WZR<def> = SUBSWrr %W8<kill>, %W9<kill>, %NZCV<imp-def>
> Bcc 1, <BB#73>, %NZCV<imp-use>
12432B	BB#72: derived from LLVM BB %if.then.377
	    Live Ins: %X19
	    Predecessors according to CFG: BB#71
12448B		B <BB#48>
	    Successors according to CFG: BB#48
> B <BB#48>
12464B	BB#73: derived from LLVM BB %if.end.378
	    Live Ins: %X19
	    Predecessors according to CFG: BB#71
12480B		%vreg275<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg275
12496B		%vreg272<def> = LDRWui <fi#7>, 0; mem:LD4[FixedStack7] GPR32:%vreg272
12512B		%WZR<def> = SUBSWrr %vreg275<kill>, %vreg272<kill>, %NZCV<imp-def>; GPR32:%vreg275,%vreg272
12528B		Bcc 0, <BB#75>, %NZCV<imp-use>
	    Successors according to CFG: BB#75 BB#74
> %W8<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2]
> %W9<def> = LDRWui <fi#7>, 0; mem:LD4[FixedStack7]
> %WZR<def> = SUBSWrr %W8<kill>, %W9<kill>, %NZCV<imp-def>
> Bcc 0, <BB#75>, %NZCV<imp-use>
12544B	BB#74: derived from LLVM BB %if.then.382
	    Live Ins: %X19
	    Predecessors according to CFG: BB#73
12560B		%vreg343<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg343
12576B		STRWui %vreg343<kill>, <fi#7>, 0; mem:ST4[FixedStack7] GPR32:%vreg343
12592B		B <BB#48>
	    Successors according to CFG: BB#48
> %W8<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2]
> STRWui %W8<kill>, <fi#7>, 0; mem:ST4[FixedStack7]
> B <BB#48>
12608B	BB#75: derived from LLVM BB %if.end.384
	    Live Ins: %X19
	    Predecessors according to CFG: BB#73
12624B		%vreg339:sub_32<def,read-undef> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR64:%vreg339
12656B		%vreg334<def> = LDRXui <fi#8>, 0; mem:LD8[FixedStack8] GPR64:%vreg334
12672B		%vreg331<def> = MOVi64imm 4; GPR64:%vreg331
12688B		%vreg332<def> = MADDXrrr %vreg339<kill>, %vreg331<kill>, %XZR; GPR64:%vreg332,%vreg339,%vreg331
12704B		%vreg333<def> = ADDXrr %vreg334<kill>, %vreg332<kill>; GPR64common:%vreg333 GPR64:%vreg334,%vreg332
12720B		%vreg328<def> = LDRWui %vreg333<kill>, 0; mem:LD4[%arrayidx386] GPR32:%vreg328 GPR64common:%vreg333
12736B		STRWui %vreg328<kill>, <fi#9>, 0; mem:ST4[FixedStack9] GPR32:%vreg328
12752B		%vreg325<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32:%vreg325
12768B		%vreg322<def> = ANDWri %vreg325<kill>, 7; GPR32common:%vreg322 GPR32:%vreg325
12800B		STRBBui %vreg322<kill>, <fi#2>, 0; mem:ST1[FixedStack2] GPR32common:%vreg322
12816B		%vreg319<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32:%vreg319
12832B		%vreg318<def> = UBFMWri %vreg319<kill>, 8, 31; GPR32:%vreg318,%vreg319
12848B		STRWui %vreg318<kill>, <fi#9>, 0; mem:ST4[FixedStack9] GPR32:%vreg318
12864B		%vreg315<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32common:%vreg315
12880B		%vreg314<def> = ADDWri %vreg315<kill>, 1, 0; GPR32common:%vreg314,%vreg315
12896B		STRWui %vreg314<kill>, <fi#6>, 0; mem:ST4[FixedStack6] GPR32common:%vreg314
12912B		%vreg311<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32common:%vreg311
12928B		%vreg308<def> = ADDWri %vreg311<kill>, 4, 0; GPR32common:%vreg308,%vreg311
12944B		STRWui %vreg308<kill>, <fi#5>, 0; mem:ST4[FixedStack5] GPR32common:%vreg308
12960B		%vreg305:sub_32<def,read-undef> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR64:%vreg305
12992B		%vreg300<def> = LDRXui <fi#8>, 0; mem:LD8[FixedStack8] GPR64:%vreg300
13008B		%vreg297<def> = MOVi64imm 4; GPR64:%vreg297
13024B		%vreg298<def> = MADDXrrr %vreg305<kill>, %vreg297<kill>, %XZR; GPR64:%vreg298,%vreg305,%vreg297
13040B		%vreg299<def> = ADDXrr %vreg300<kill>, %vreg298<kill>; GPR64common:%vreg299 GPR64:%vreg300,%vreg298
13056B		%vreg294<def> = LDRWui %vreg299<kill>, 0; mem:LD4[%arrayidx394] GPR32:%vreg294 GPR64common:%vreg299
13072B		STRWui %vreg294<kill>, <fi#9>, 0; mem:ST4[FixedStack9] GPR32:%vreg294
13088B		%vreg291<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32:%vreg291
13104B		%vreg288<def> = ANDWri %vreg291<kill>, 7; GPR32common:%vreg288 GPR32:%vreg291
13136B		%vreg286<def> = UBFMWri %vreg288<kill>, 0, 7; GPR32:%vreg286 GPR32common:%vreg288
13152B		STRWui %vreg286<kill>, <fi#7>, 0; mem:ST4[FixedStack7] GPR32:%vreg286
13168B		%vreg283<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32:%vreg283
13184B		%vreg282<def> = UBFMWri %vreg283<kill>, 8, 31; GPR32:%vreg282,%vreg283
13200B		STRWui %vreg282<kill>, <fi#9>, 0; mem:ST4[FixedStack9] GPR32:%vreg282
13216B		%vreg279<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32common:%vreg279
13232B		%vreg278<def> = ADDWri %vreg279<kill>, 1, 0; GPR32common:%vreg278,%vreg279
13248B		STRWui %vreg278<kill>, <fi#6>, 0; mem:ST4[FixedStack6] GPR32common:%vreg278
13264B		B <BB#48>
	    Successors according to CFG: BB#48
> %W8<def> = LDRWui <fi#9>, 0, %X8<imp-def>; mem:LD4[FixedStack9]
> %X9<def> = LDRXui <fi#8>, 0; mem:LD8[FixedStack8]
> %X10<def> = MOVi64imm 4
> %X8<def> = MADDXrrr %X8<kill>, %X10<kill>, %XZR
> %X8<def> = ADDXrr %X9<kill>, %X8<kill>
> %W8<def> = LDRWui %X8<kill>, 0; mem:LD4[%arrayidx386]
> STRWui %W8<kill>, <fi#9>, 0; mem:ST4[FixedStack9]
> %W8<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9]
> %W8<def> = ANDWri %W8<kill>, 7
> STRBBui %W8<kill>, <fi#2>, 0; mem:ST1[FixedStack2]
> %W8<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9]
> %W8<def> = UBFMWri %W8<kill>, 8, 31
> STRWui %W8<kill>, <fi#9>, 0; mem:ST4[FixedStack9]
> %W8<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6]
> %W8<def> = ADDWri %W8<kill>, 1, 0
> STRWui %W8<kill>, <fi#6>, 0; mem:ST4[FixedStack6]
> %W8<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2]
> %W8<def> = ADDWri %W8<kill>, 4, 0
> STRWui %W8<kill>, <fi#5>, 0; mem:ST4[FixedStack5]
> %W8<def> = LDRWui <fi#9>, 0, %X8<imp-def>; mem:LD4[FixedStack9]
> %X9<def> = LDRXui <fi#8>, 0; mem:LD8[FixedStack8]
> %X10<def> = MOVi64imm 4
> %X8<def> = MADDXrrr %X8<kill>, %X10<kill>, %XZR
> %X8<def> = ADDXrr %X9<kill>, %X8<kill>
> %W8<def> = LDRWui %X8<kill>, 0; mem:LD4[%arrayidx394]
> STRWui %W8<kill>, <fi#9>, 0; mem:ST4[FixedStack9]
> %W8<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9]
> %W8<def> = ANDWri %W8<kill>, 7
> %W8<def> = UBFMWri %W8<kill>, 0, 7
> STRWui %W8<kill>, <fi#7>, 0; mem:ST4[FixedStack7]
> %W8<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9]
> %W8<def> = UBFMWri %W8<kill>, 8, 31
> STRWui %W8<kill>, <fi#9>, 0; mem:ST4[FixedStack9]
> %W8<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6]
> %W8<def> = ADDWri %W8<kill>, 1, 0
> STRWui %W8<kill>, <fi#6>, 0; mem:ST4[FixedStack6]
> B <BB#48>
13280B	BB#76: derived from LLVM BB %return_notr
	    Live Ins: %X19
	    Predecessors according to CFG: BB#62 BB#57 BB#51
13296B		%vreg381<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg381
13312B		%vreg380<def> = LDRXui %vreg381<kill>, 0; mem:LD8[%strm400] GPR64common:%vreg380,%vreg381
13328B		%vreg378<def> = LDRWui %vreg380<kill>, 9; mem:LD4[%total_out_lo32401] GPR32:%vreg378 GPR64common:%vreg380
13344B		STRWui %vreg378<kill>, <fi#14>, 0; mem:ST4[FixedStack14] GPR32:%vreg378
13408B		%vreg370<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg370
13424B		%vreg369<def> = LDRXui %vreg370<kill>, 0; mem:LD8[%strm402] GPR64common:%vreg369,%vreg370
13428B		%vreg375<def> = LDRWui <fi#12>, 0; mem:LD4[FixedStack12] GPR32:%vreg375
13432B		%vreg374<def> = LDRWui <fi#11>, 0; mem:LD4[FixedStack11] GPR32:%vreg374
13440B		%vreg367<def> = LDRWui %vreg369, 9; mem:LD4[%total_out_lo32403] GPR32:%vreg367 GPR64common:%vreg369
13448B		%vreg373<def> = SUBWrr %vreg375<kill>, %vreg374<kill>; GPR32:%vreg373,%vreg375,%vreg374
13456B		%vreg366<def> = ADDWrr %vreg367<kill>, %vreg373<kill>; GPR32:%vreg366,%vreg367,%vreg373
13472B		STRWui %vreg366<kill>, %vreg369<kill>, 9; mem:ST4[%total_out_lo32403] GPR32:%vreg366 GPR64common:%vreg369
13488B		%vreg361<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg361
13504B		%vreg360<def> = LDRXui %vreg361<kill>, 0; mem:LD8[%strm405] GPR64common:%vreg360,%vreg361
13520B		%vreg358<def> = LDRWui %vreg360<kill>, 9; mem:LD4[%total_out_lo32406] GPR32:%vreg358 GPR64common:%vreg360
13536B		%vreg356<def> = LDRWui <fi#14>, 0; mem:LD4[FixedStack14] GPR32:%vreg356
13552B		%WZR<def> = SUBSWrr %vreg358<kill>, %vreg356<kill>, %NZCV<imp-def>; GPR32:%vreg358,%vreg356
13568B		Bcc 2, <BB#78>, %NZCV<imp-use>
	    Successors according to CFG: BB#78 BB#77
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X8<def> = LDRXui %X8<kill>, 0; mem:LD8[%strm400]
> %W8<def> = LDRWui %X8<kill>, 9; mem:LD4[%total_out_lo32401]
> STRWui %W8<kill>, <fi#14>, 0; mem:ST4[FixedStack14]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X8<def> = LDRXui %X8<kill>, 0; mem:LD8[%strm402]
> %W9<def> = LDRWui <fi#12>, 0; mem:LD4[FixedStack12]
> %W10<def> = LDRWui <fi#11>, 0; mem:LD4[FixedStack11]
> %W11<def> = LDRWui %X8, 9; mem:LD4[%total_out_lo32403]
> %W9<def> = SUBWrr %W9<kill>, %W10<kill>
> %W9<def> = ADDWrr %W11<kill>, %W9<kill>
> STRWui %W9<kill>, %X8<kill>, 9; mem:ST4[%total_out_lo32403]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X8<def> = LDRXui %X8<kill>, 0; mem:LD8[%strm405]
> %W8<def> = LDRWui %X8<kill>, 9; mem:LD4[%total_out_lo32406]
> %W9<def> = LDRWui <fi#14>, 0; mem:LD4[FixedStack14]
> %WZR<def> = SUBSWrr %W8<kill>, %W9<kill>, %NZCV<imp-def>
> Bcc 2, <BB#78>, %NZCV<imp-use>
13584B	BB#77: derived from LLVM BB %if.then.409
	    Live Ins: %X19
	    Predecessors according to CFG: BB#76
13600B		%vreg389<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg389
13616B		%vreg388<def> = LDRXui %vreg389<kill>, 0; mem:LD8[%strm410] GPR64common:%vreg388,%vreg389
13632B		%vreg386<def> = LDRWui %vreg388, 10; mem:LD4[%total_out_hi32411] GPR32common:%vreg386 GPR64common:%vreg388
13648B		%vreg385<def> = ADDWri %vreg386<kill>, 1, 0; GPR32common:%vreg385,%vreg386
13664B		STRWui %vreg385<kill>, %vreg388<kill>, 10; mem:ST4[%total_out_hi32411] GPR32common:%vreg385 GPR64common:%vreg388
	    Successors according to CFG: BB#78
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X8<def> = LDRXui %X8<kill>, 0; mem:LD8[%strm410]
> %W9<def> = LDRWui %X8, 10; mem:LD4[%total_out_hi32411]
> %W9<def> = ADDWri %W9<kill>, 1, 0
> STRWui %W9<kill>, %X8<kill>, 10; mem:ST4[%total_out_hi32411]
13680B	BB#78: derived from LLVM BB %if.end.413
	    Live Ins: %X19
	    Predecessors according to CFG: BB#76 BB#77
13696B		%vreg429<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg429
13712B		%vreg428<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg428
13728B		STRWui %vreg429<kill>, %vreg428<kill>, 796; mem:ST4[%calculatedBlockCRC414] GPR32:%vreg429 GPR64common:%vreg428
13744B		%vreg425<def> = LDRBBui <fi#4>, 0; mem:LD1[FixedStack4] GPR32:%vreg425
13760B		%vreg424<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg424
13776B		STRBBui %vreg425<kill>, %vreg424<kill>, 12; mem:ST1[%state_out_ch415] GPR32:%vreg425 GPR64common:%vreg424
13792B		%vreg421<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32:%vreg421
13808B		%vreg420<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg420
13824B		STRWui %vreg421<kill>, %vreg420<kill>, 4; mem:ST4[%state_out_len416] GPR32:%vreg421 GPR64common:%vreg420
13840B		%vreg417<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg417
13856B		%vreg416<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg416
13872B		STRWui %vreg417<kill>, %vreg416<kill>, 273; mem:ST4[%nblock_used417] GPR32:%vreg417 GPR64common:%vreg416
13888B		%vreg413<def> = LDRWui <fi#7>, 0; mem:LD4[FixedStack7] GPR32:%vreg413
13904B		%vreg412<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg412
13920B		STRWui %vreg413<kill>, %vreg412<kill>, 16; mem:ST4[%k0418] GPR32:%vreg413 GPR64common:%vreg412
13936B		%vreg409<def> = LDRXui <fi#8>, 0; mem:LD8[FixedStack8] GPR64:%vreg409
13952B		%vreg408<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg408
13968B		STRXui %vreg409<kill>, %vreg408<kill>, 394; mem:ST8[%tt419] GPR64:%vreg409 GPR64common:%vreg408
13984B		%vreg405<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32:%vreg405
14000B		%vreg404<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg404
14016B		STRWui %vreg405<kill>, %vreg404<kill>, 15; mem:ST4[%tPos420] GPR32:%vreg405 GPR64common:%vreg404
14048B		%vreg400<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg400
14056B		%vreg401<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg401
14064B		%vreg399<def> = LDRXui %vreg400<kill>, 0; mem:LD8[%strm421] GPR64common:%vreg399,%vreg400
14080B		STRXui %vreg401<kill>, %vreg399<kill>, 3; mem:ST8[%next_out422] GPR64:%vreg401 GPR64common:%vreg399
14112B		%vreg394<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg394
14120B		%vreg395<def> = LDRWui <fi#11>, 0; mem:LD4[FixedStack11] GPR32:%vreg395
14128B		%vreg393<def> = LDRXui %vreg394<kill>, 0; mem:LD8[%strm423] GPR64common:%vreg393,%vreg394
14144B		STRWui %vreg395<kill>, %vreg393<kill>, 8; mem:ST4[%avail_out424] GPR32:%vreg395 GPR64common:%vreg393
	    Successors according to CFG: BB#79
> %W8<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRWui %W8<kill>, %X9<kill>, 796; mem:ST4[%calculatedBlockCRC414]
> %W8<def> = LDRBBui <fi#4>, 0; mem:LD1[FixedStack4]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRBBui %W8<kill>, %X9<kill>, 12; mem:ST1[%state_out_ch415]
> %W8<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRWui %W8<kill>, %X9<kill>, 4; mem:ST4[%state_out_len416]
> %W8<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRWui %W8<kill>, %X9<kill>, 273; mem:ST4[%nblock_used417]
> %W8<def> = LDRWui <fi#7>, 0; mem:LD4[FixedStack7]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRWui %W8<kill>, %X9<kill>, 16; mem:ST4[%k0418]
> %X8<def> = LDRXui <fi#8>, 0; mem:LD8[FixedStack8]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRXui %X8<kill>, %X9<kill>, 394; mem:ST8[%tt419]
> %W8<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRWui %W8<kill>, %X9<kill>, 15; mem:ST4[%tPos420]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X9<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10]
> %X8<def> = LDRXui %X8<kill>, 0; mem:LD8[%strm421]
> STRXui %X9<kill>, %X8<kill>, 3; mem:ST8[%next_out422]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = LDRWui <fi#11>, 0; mem:LD4[FixedStack11]
> %X8<def> = LDRXui %X8<kill>, 0; mem:LD8[%strm423]
> STRWui %W9<kill>, %X8<kill>, 8; mem:ST4[%avail_out424]
14160B	BB#79: derived from LLVM BB %if.end.425
	    Live Ins: %X19
	    Predecessors according to CFG: BB#78
14176B		STRBBui %WZR, <fi#0>, 0; mem:ST1[FixedStack0]
	    Successors according to CFG: BB#80
> STRBBui %WZR, <fi#0>, 0; mem:ST1[FixedStack0]
14192B	BB#80: derived from LLVM BB %return
	    Live Ins: %X19
	    Predecessors according to CFG: BB#60 BB#79 BB#13 BB#11 BB#4
14208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
14224B		%vreg1133<def> = MOVaddr <ga:@unRLE_obuf_to_output_FAST>[TF=1], <ga:@unRLE_obuf_to_output_FAST>[TF=34]; GPR64:%vreg1133
14240B		%X0<def> = COPY %vreg1133<kill>; GPR64:%vreg1133
14256B		%X1<def> = COPY %vreg10<kill>; GPR64:%vreg10
14272B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %SP<imp-def>
14288B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
14304B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
14320B		STACKMAP 1, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=1)
14336B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
14352B		%vreg1134<def> = LDRBBui <fi#0>, 0; mem:LD1[%retval] GPR32:%vreg1134
14384B		%W0<def> = COPY %vreg1134<kill>; GPR32:%vreg1134
14400B		RET_ReallyLR %W0<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = MOVaddr <ga:@unRLE_obuf_to_output_FAST>[TF=1], <ga:@unRLE_obuf_to_output_FAST>[TF=34]
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19<kill>
> BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %SP<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 1, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=1)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = LDRBBui <fi#0>, 0; mem:LD1[%retval]
> %W0<def> = COPY %W0<kill>
Deleting identity copy.
> RET_ReallyLR %W0<imp-use>
Computing live-in reg-units in ABI blocks.
0B	BB#0 W0#0 W30#0
Created 2 new intervals.
********** INTERVALS **********
W30 [0B,16r:0)[176r,176d:12)[224e,224d:6)[944r,944d:11)[992e,992d:5)[1264r,1264d:10)[1312e,1312d:4)[1568r,1568d:9)[1616e,1616d:3)[1808r,1808d:8)[1872e,1872d:2)[2080r,2080d:7)[2128e,2128d:1)  0@0B-phi 1@2128e 2@1872e 3@1616e 4@1312e 5@992e 6@224e 7@2080r 8@1808r 9@1568r 10@1264r 11@944r 12@176r
W0 [0B,32r:0)[144r,176r:7)[912r,944r:6)[1232r,1264r:5)[1536r,1568r:4)[1776r,1808r:3)[2048r,2080r:2)[2176r,2192r:1)  0@0B-phi 1@2176r 2@2048r 3@1776r 4@1536r 5@1232r 6@912r 7@144r
%vreg0 [32r,48r:0)  0@32r
%vreg1 [48r,256r:0)  0@48r
%vreg3 [272r,288r:0)  0@272r
%vreg4 [64r,80r:0)  0@64r
%vreg5 [80r,96r:0)  0@80r
%vreg6 [96r,144r:0)  0@96r
%vreg7 [112r,160r:0)  0@112r
%vreg8 [16r,2016r:0)  0@16r
%vreg10 [448r,464r:0)  0@448r
%vreg13 [416r,432r:0)  0@416r
%vreg15 [400r,416r:0)  0@400r
%vreg16 [384r,400r:0)  0@384r
%vreg19 [592r,608r:0)  0@592r
%vreg21 [576r,608r:0)  0@576r
%vreg22 [560r,576r:0)  0@560r
%vreg25 [736r,752r:0)  0@736r
%vreg26 [720r,736r:0)  0@720r
%vreg31 [880r,928r:0)  0@880r
%vreg33 [864r,880r:0)  0@864r
%vreg34 [848r,864r:0)  0@848r
%vreg36 [832r,912r:0)  0@832r
%vreg37 [816r,832r:0)  0@816r
%vreg39 [800r,944r:0)  0@800r
%vreg40 [784r,800r:0)  0@784r
%vreg43 [1056r,1072r:0)  0@1056r
%vreg44 [1040r,1056r:0)  0@1040r
%vreg49 [1200r,1248r:0)  0@1200r
%vreg51 [1184r,1200r:0)  0@1184r
%vreg52 [1168r,1184r:0)  0@1168r
%vreg54 [1152r,1232r:0)  0@1152r
%vreg55 [1136r,1152r:0)  0@1136r
%vreg57 [1120r,1264r:0)  0@1120r
%vreg58 [1104r,1120r:0)  0@1104r
%vreg61 [1376r,1392r:0)  0@1376r
%vreg62 [1360r,1376r:0)  0@1360r
%vreg67 [1504r,1552r:0)  0@1504r
%vreg68 [1488r,1504r:0)  0@1488r
%vreg70 [1472r,1536r:0)  0@1472r
%vreg71 [1456r,1472r:0)  0@1456r
%vreg73 [1440r,1568r:0)  0@1440r
%vreg74 [1424r,1440r:0)  0@1424r
%vreg75 [1840r,1920r:0)  0@1840r
%vreg77 [1904r,1920r:0)  0@1904r
%vreg82 [1744r,1792r:0)  0@1744r
%vreg83 [1728r,1744r:0)  0@1728r
%vreg85 [1712r,1776r:0)  0@1712r
%vreg86 [1696r,1712r:0)  0@1696r
%vreg88 [1680r,1808r:0)  0@1680r
%vreg89 [1664r,1680r:0)  0@1664r
%vreg90 [656r,672r:0)  0@656r
%vreg91 [496r,512r:0)  0@496r
%vreg92 [320r,336r:0)  0@320r
%vreg94 [2160r,2176r:0)  0@2160r
%vreg95 [1968r,1984r:0)  0@1968r
%vreg96 [1984r,2000r:0)  0@1984r
%vreg97 [2000r,2048r:0)  0@2000r
%vreg98 [2016r,2064r:0)  0@2016r
RegMasks: 176r 944r 1264r 1568r 1808r 2080r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzDecompressEnd: Post SSA
Frame Objects:
  fi#0: size=4, align=4, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=8, align=8, at location [SP]
Function Live Ins: %X0 in %vreg0, %LR in %vreg8

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %LR
16B		%vreg8<def> = COPY %LR; GPR64:%vreg8
32B		%vreg0<def> = COPY %X0; GPR64:%vreg0
48B		%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
64B		%vreg4<def> = ADRP <ga:@BZ2_bzDecompressEnd>[TF=1]; GPR64common:%vreg4
80B		%vreg5<def> = ADDXri %vreg4, <ga:@BZ2_bzDecompressEnd>[TF=34], 0; GPR64sp:%vreg5 GPR64common:%vreg4
96B		%vreg6<def> = COPY %vreg5; GPR64all:%vreg6 GPR64sp:%vreg5
112B		%vreg7<def> = COPY %vreg8; GPR64all:%vreg7 GPR64:%vreg8
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		%X0<def> = COPY %vreg6; GPR64all:%vreg6
160B		%X1<def> = COPY %vreg7; GPR64all:%vreg7
176B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
224B		STACKMAP 0, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, %vreg1, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1] GPR64:%vreg1
240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
256B		STRXui %vreg1, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg1
272B		%vreg3<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg3
288B		CBNZX %vreg3, <BB#2>; GPR64:%vreg3
	    Successors according to CFG: BB#2 BB#1

304B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
320B		%vreg92<def> = MOVi32imm 4294967294; GPR32:%vreg92
336B		STRWui %vreg92, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg92
352B		B <BB#13>
	    Successors according to CFG: BB#13

368B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0
384B		%vreg16<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg16
400B		%vreg15<def> = LDRXui %vreg16, 6; mem:LD8[%state] GPR64:%vreg15 GPR64common:%vreg16
416B		%vreg13<def> = COPY %vreg15; GPR64:%vreg13,%vreg15
432B		STRXui %vreg13, <fi#2>, 0; mem:ST8[FixedStack2] GPR64:%vreg13
448B		%vreg10<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg10
464B		CBNZX %vreg10, <BB#4>; GPR64:%vreg10
	    Successors according to CFG: BB#4 BB#3

480B	BB#3: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#2
496B		%vreg91<def> = MOVi32imm 4294967294; GPR32:%vreg91
512B		STRWui %vreg91, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg91
528B		B <BB#13>
	    Successors according to CFG: BB#13

544B	BB#4: derived from LLVM BB %if.end.3
	    Predecessors according to CFG: BB#2
560B		%vreg22<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg22
576B		%vreg21<def> = LDRXui %vreg22, 0; mem:LD8[%strm4] GPR64:%vreg21 GPR64common:%vreg22
592B		%vreg19<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg19
608B		%XZR<def> = SUBSXrr %vreg21, %vreg19, %NZCV<imp-def>; GPR64:%vreg21,%vreg19
624B		Bcc 0, <BB#6>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#6 BB#5

640B	BB#5: derived from LLVM BB %if.then.6
	    Predecessors according to CFG: BB#4
656B		%vreg90<def> = MOVi32imm 4294967294; GPR32:%vreg90
672B		STRWui %vreg90, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg90
688B		B <BB#13>
	    Successors according to CFG: BB#13

704B	BB#6: derived from LLVM BB %if.end.7
	    Predecessors according to CFG: BB#4
720B		%vreg26<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg26
736B		%vreg25<def> = LDRXui %vreg26, 394; mem:LD8[%tt] GPR64:%vreg25 GPR64common:%vreg26
752B		CBZX %vreg25, <BB#8>; GPR64:%vreg25
	    Successors according to CFG: BB#8 BB#7

768B	BB#7: derived from LLVM BB %if.then.9
	    Predecessors according to CFG: BB#6
784B		%vreg40<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg40
800B		%vreg39<def> = LDRXui %vreg40, 8; mem:LD8[%bzfree] GPR64:%vreg39 GPR64common:%vreg40
816B		%vreg37<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg37
832B		%vreg36<def> = LDRXui %vreg37, 9; mem:LD8[%opaque] GPR64:%vreg36 GPR64common:%vreg37
848B		%vreg34<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg34
864B		%vreg33<def> = LDRXui %vreg34, 394; mem:LD8[%tt10] GPR64:%vreg33 GPR64common:%vreg34
880B		%vreg31<def> = COPY %vreg33; GPR64all:%vreg31 GPR64:%vreg33
896B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
912B		%X0<def> = COPY %vreg36; GPR64:%vreg36
928B		%X1<def> = COPY %vreg31; GPR64all:%vreg31
944B		BLR %vreg39, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>; GPR64:%vreg39
960B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
976B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
992B		STACKMAP 1, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1]
1008B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#8

1024B	BB#8: derived from LLVM BB %if.end.11
	    Predecessors according to CFG: BB#6 BB#7
1040B		%vreg44<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg44
1056B		%vreg43<def> = LDRXui %vreg44, 395; mem:LD8[%ll16] GPR64:%vreg43 GPR64common:%vreg44
1072B		CBZX %vreg43, <BB#10>; GPR64:%vreg43
	    Successors according to CFG: BB#10 BB#9

1088B	BB#9: derived from LLVM BB %if.then.13
	    Predecessors according to CFG: BB#8
1104B		%vreg58<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg58
1120B		%vreg57<def> = LDRXui %vreg58, 8; mem:LD8[%bzfree14] GPR64:%vreg57 GPR64common:%vreg58
1136B		%vreg55<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg55
1152B		%vreg54<def> = LDRXui %vreg55, 9; mem:LD8[%opaque15] GPR64:%vreg54 GPR64common:%vreg55
1168B		%vreg52<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg52
1184B		%vreg51<def> = LDRXui %vreg52, 395; mem:LD8[%ll1616] GPR64:%vreg51 GPR64common:%vreg52
1200B		%vreg49<def> = COPY %vreg51; GPR64all:%vreg49 GPR64:%vreg51
1216B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1232B		%X0<def> = COPY %vreg54; GPR64:%vreg54
1248B		%X1<def> = COPY %vreg49; GPR64all:%vreg49
1264B		BLR %vreg57, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>; GPR64:%vreg57
1280B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1296B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1312B		STACKMAP 2, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1]
1328B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#10

1344B	BB#10: derived from LLVM BB %if.end.17
	    Predecessors according to CFG: BB#8 BB#9
1360B		%vreg62<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg62
1376B		%vreg61<def> = LDRXui %vreg62, 396; mem:LD8[%ll4] GPR64:%vreg61 GPR64common:%vreg62
1392B		CBZX %vreg61, <BB#12>; GPR64:%vreg61
	    Successors according to CFG: BB#12 BB#11

1408B	BB#11: derived from LLVM BB %if.then.19
	    Predecessors according to CFG: BB#10
1424B		%vreg74<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg74
1440B		%vreg73<def> = LDRXui %vreg74, 8; mem:LD8[%bzfree20] GPR64:%vreg73 GPR64common:%vreg74
1456B		%vreg71<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg71
1472B		%vreg70<def> = LDRXui %vreg71, 9; mem:LD8[%opaque21] GPR64:%vreg70 GPR64common:%vreg71
1488B		%vreg68<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg68
1504B		%vreg67<def> = LDRXui %vreg68, 396; mem:LD8[%ll422] GPR64:%vreg67 GPR64common:%vreg68
1520B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1536B		%X0<def> = COPY %vreg70; GPR64:%vreg70
1552B		%X1<def> = COPY %vreg67; GPR64:%vreg67
1568B		BLR %vreg73, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>; GPR64:%vreg73
1584B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1600B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1616B		STACKMAP 3, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack1]
1632B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#12

1648B	BB#12: derived from LLVM BB %if.end.23
	    Predecessors according to CFG: BB#10 BB#11
1664B		%vreg89<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg89
1680B		%vreg88<def> = LDRXui %vreg89, 8; mem:LD8[%bzfree24] GPR64:%vreg88 GPR64common:%vreg89
1696B		%vreg86<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg86
1712B		%vreg85<def> = LDRXui %vreg86, 9; mem:LD8[%opaque25] GPR64:%vreg85 GPR64common:%vreg86
1728B		%vreg83<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg83
1744B		%vreg82<def> = LDRXui %vreg83, 6; mem:LD8[%state26] GPR64:%vreg82 GPR64common:%vreg83
1760B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1776B		%X0<def> = COPY %vreg85; GPR64:%vreg85
1792B		%X1<def> = COPY %vreg82; GPR64:%vreg82
1808B		BLR %vreg88, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>; GPR64:%vreg88
1824B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1840B		%vreg75<def> = COPY %XZR; GPR64:%vreg75
1856B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1872B		STACKMAP 4, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack1]
1888B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1904B		%vreg77<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg77
1920B		STRXui %vreg75, %vreg77, 6; mem:ST8[%state27] GPR64:%vreg75 GPR64common:%vreg77
1936B		STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
	    Successors according to CFG: BB#13

1952B	BB#13: derived from LLVM BB %return
	    Predecessors according to CFG: BB#12 BB#5 BB#3 BB#1
1968B		%vreg95<def> = ADRP <ga:@BZ2_bzDecompressEnd>[TF=1]; GPR64common:%vreg95
1984B		%vreg96<def> = ADDXri %vreg95, <ga:@BZ2_bzDecompressEnd>[TF=34], 0; GPR64sp:%vreg96 GPR64common:%vreg95
2000B		%vreg97<def> = COPY %vreg96; GPR64all:%vreg97 GPR64sp:%vreg96
2016B		%vreg98<def> = COPY %vreg8; GPR64all:%vreg98 GPR64:%vreg8
2032B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2048B		%X0<def> = COPY %vreg97; GPR64all:%vreg97
2064B		%X1<def> = COPY %vreg98; GPR64all:%vreg98
2080B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
2096B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2112B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2128B		STACKMAP 5, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
2144B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2160B		%vreg94<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0] GPR32:%vreg94
2176B		%W0<def> = COPY %vreg94; GPR32:%vreg94
2192B		RET_ReallyLR %W0<imp-use>

# End machine code for function BZ2_bzDecompressEnd.

********** SIMPLE REGISTER COALESCING **********
********** Function: BZ2_bzDecompressEnd
********** JOINING INTERVALS ***********
if.end.11:
if.end.17:
return:
2048B	%X0<def> = COPY %vreg97; GPR64all:%vreg97
	Considering merging %vreg97 with %X0
	Can only merge into reserved registers.
2064B	%X1<def> = COPY %vreg98; GPR64all:%vreg98
	Considering merging %vreg98 with %X1
	Can only merge into reserved registers.
2176B	%W0<def> = COPY %vreg94; GPR32:%vreg94
	Considering merging %vreg94 with %W0
	Can only merge into reserved registers.
if.end:
if.end.3:
if.end.7:
if.end.23:
1776B	%X0<def> = COPY %vreg85; GPR64:%vreg85
	Considering merging %vreg85 with %X0
	Can only merge into reserved registers.
1792B	%X1<def> = COPY %vreg82; GPR64:%vreg82
	Considering merging %vreg82 with %X1
	Can only merge into reserved registers.
1840B	%vreg75<def> = COPY %XZR; GPR64:%vreg75
	Considering merging %vreg75 with %XZR
		RHS = %vreg75 [1840r,1920r:0)  0@1840r
		updated: 1920B	STRXui %XZR, %vreg77, 6; mem:ST8[%state27] GPR64common:%vreg77
	Success: %vreg75 -> %XZR
	Result = %XZR
entry:
16B	%vreg8<def> = COPY %LR; GPR64:%vreg8
	Considering merging %vreg8 with %LR
	Can only merge into reserved registers.
32B	%vreg0<def> = COPY %X0; GPR64:%vreg0
	Considering merging %vreg0 with %X0
	Can only merge into reserved registers.
144B	%X0<def> = COPY %vreg6; GPR64all:%vreg6
	Considering merging %vreg6 with %X0
	Can only merge into reserved registers.
160B	%X1<def> = COPY %vreg7; GPR64all:%vreg7
	Considering merging %vreg7 with %X1
	Can only merge into reserved registers.
if.then:
if.then.2:
if.then.6:
if.then.9:
912B	%X0<def> = COPY %vreg36; GPR64:%vreg36
	Considering merging %vreg36 with %X0
	Can only merge into reserved registers.
928B	%X1<def> = COPY %vreg31; GPR64all:%vreg31
	Considering merging %vreg31 with %X1
	Can only merge into reserved registers.
if.then.13:
1232B	%X0<def> = COPY %vreg54; GPR64:%vreg54
	Considering merging %vreg54 with %X0
	Can only merge into reserved registers.
1248B	%X1<def> = COPY %vreg49; GPR64all:%vreg49
	Considering merging %vreg49 with %X1
	Can only merge into reserved registers.
if.then.19:
1536B	%X0<def> = COPY %vreg70; GPR64:%vreg70
	Considering merging %vreg70 with %X0
	Can only merge into reserved registers.
1552B	%X1<def> = COPY %vreg67; GPR64:%vreg67
	Considering merging %vreg67 with %X1
	Can only merge into reserved registers.
2000B	%vreg97<def> = COPY %vreg96; GPR64all:%vreg97 GPR64sp:%vreg96
	Considering merging to GPR64sp with %vreg96 in %vreg97
		RHS = %vreg96 [1984r,2000r:0)  0@1984r
		LHS = %vreg97 [2000r,2048r:0)  0@2000r
		merge %vreg97:0@2000r into %vreg96:0@1984r --> @1984r
		erased:	2000r	%vreg97<def> = COPY %vreg96; GPR64all:%vreg97 GPR64sp:%vreg96
		updated: 1984B	%vreg97<def> = ADDXri %vreg95, <ga:@BZ2_bzDecompressEnd>[TF=34], 0; GPR64sp:%vreg97 GPR64common:%vreg95
	Success: %vreg96 -> %vreg97
	Result = %vreg97 [1984r,2048r:0)  0@1984r
2016B	%vreg98<def> = COPY %vreg8; GPR64all:%vreg98 GPR64:%vreg8
	Considering merging to GPR64 with %vreg8 in %vreg98
		RHS = %vreg8 [16r,2016r:0)  0@16r
		LHS = %vreg98 [2016r,2064r:0)  0@2016r
		merge %vreg98:0@2016r into %vreg8:0@16r --> @16r
		erased:	2016r	%vreg98<def> = COPY %vreg8; GPR64all:%vreg98 GPR64:%vreg8
		updated: 16B	%vreg98<def> = COPY %LR; GPR64:%vreg98
		updated: 112B	%vreg7<def> = COPY %vreg98; GPR64all:%vreg7 GPR64:%vreg98
	Success: %vreg8 -> %vreg98
	Result = %vreg98 [16r,2064r:0)  0@16r
416B	%vreg13<def> = COPY %vreg15; GPR64:%vreg13,%vreg15
	Considering merging to GPR64 with %vreg15 in %vreg13
		RHS = %vreg15 [400r,416r:0)  0@400r
		LHS = %vreg13 [416r,432r:0)  0@416r
		merge %vreg13:0@416r into %vreg15:0@400r --> @400r
		erased:	416r	%vreg13<def> = COPY %vreg15; GPR64:%vreg13,%vreg15
		updated: 400B	%vreg13<def> = LDRXui %vreg16, 6; mem:LD8[%state] GPR64:%vreg13 GPR64common:%vreg16
	Success: %vreg15 -> %vreg13
	Result = %vreg13 [400r,432r:0)  0@400r
48B	%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
	Considering merging to GPR64 with %vreg0 in %vreg1
		RHS = %vreg0 [32r,48r:0)  0@32r
		LHS = %vreg1 [48r,256r:0)  0@48r
		merge %vreg1:0@48r into %vreg0:0@32r --> @32r
		erased:	48r	%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
		updated: 32B	%vreg1<def> = COPY %X0; GPR64:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [32r,256r:0)  0@32r
96B	%vreg6<def> = COPY %vreg5; GPR64all:%vreg6 GPR64sp:%vreg5
	Considering merging to GPR64sp with %vreg5 in %vreg6
		RHS = %vreg5 [80r,96r:0)  0@80r
		LHS = %vreg6 [96r,144r:0)  0@96r
		merge %vreg6:0@96r into %vreg5:0@80r --> @80r
		erased:	96r	%vreg6<def> = COPY %vreg5; GPR64all:%vreg6 GPR64sp:%vreg5
		updated: 80B	%vreg6<def> = ADDXri %vreg4, <ga:@BZ2_bzDecompressEnd>[TF=34], 0; GPR64sp:%vreg6 GPR64common:%vreg4
	Success: %vreg5 -> %vreg6
	Result = %vreg6 [80r,144r:0)  0@80r
112B	%vreg7<def> = COPY %vreg98; GPR64all:%vreg7 GPR64:%vreg98
	Considering merging to GPR64 with %vreg98 in %vreg7
		RHS = %vreg98 [16r,2064r:0)  0@16r
		LHS = %vreg7 [112r,160r:0)  0@112r
		merge %vreg7:0@112r into %vreg98:0@16r --> @16r
		erased:	112r	%vreg7<def> = COPY %vreg98; GPR64all:%vreg7 GPR64:%vreg98
		updated: 16B	%vreg7<def> = COPY %LR; GPR64:%vreg7
		updated: 2064B	%X1<def> = COPY %vreg7; GPR64:%vreg7
	Success: %vreg98 -> %vreg7
	Result = %vreg7 [16r,2064r:0)  0@16r
880B	%vreg31<def> = COPY %vreg33; GPR64all:%vreg31 GPR64:%vreg33
	Considering merging to GPR64 with %vreg33 in %vreg31
		RHS = %vreg33 [864r,880r:0)  0@864r
		LHS = %vreg31 [880r,928r:0)  0@880r
		merge %vreg31:0@880r into %vreg33:0@864r --> @864r
		erased:	880r	%vreg31<def> = COPY %vreg33; GPR64all:%vreg31 GPR64:%vreg33
		updated: 864B	%vreg31<def> = LDRXui %vreg34, 394; mem:LD8[%tt10] GPR64:%vreg31 GPR64common:%vreg34
	Success: %vreg33 -> %vreg31
	Result = %vreg31 [864r,928r:0)  0@864r
1200B	%vreg49<def> = COPY %vreg51; GPR64all:%vreg49 GPR64:%vreg51
	Considering merging to GPR64 with %vreg51 in %vreg49
		RHS = %vreg51 [1184r,1200r:0)  0@1184r
		LHS = %vreg49 [1200r,1248r:0)  0@1200r
		merge %vreg49:0@1200r into %vreg51:0@1184r --> @1184r
		erased:	1200r	%vreg49<def> = COPY %vreg51; GPR64all:%vreg49 GPR64:%vreg51
		updated: 1184B	%vreg49<def> = LDRXui %vreg52, 395; mem:LD8[%ll1616] GPR64:%vreg49 GPR64common:%vreg52
	Success: %vreg51 -> %vreg49
	Result = %vreg49 [1184r,1248r:0)  0@1184r
2048B	%X0<def> = COPY %vreg97; GPR64sp:%vreg97
	Considering merging %vreg97 with %X0
	Can only merge into reserved registers.
2064B	%X1<def> = COPY %vreg7; GPR64:%vreg7
	Considering merging %vreg7 with %X1
	Can only merge into reserved registers.
144B	%X0<def> = COPY %vreg6; GPR64sp:%vreg6
	Considering merging %vreg6 with %X0
	Can only merge into reserved registers.
160B	%X1<def> = COPY %vreg7; GPR64:%vreg7
	Considering merging %vreg7 with %X1
	Can only merge into reserved registers.
928B	%X1<def> = COPY %vreg31; GPR64:%vreg31
	Considering merging %vreg31 with %X1
	Can only merge into reserved registers.
1248B	%X1<def> = COPY %vreg49; GPR64:%vreg49
	Considering merging %vreg49 with %X1
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
W30 [0B,16r:0)[176r,176d:12)[224e,224d:6)[944r,944d:11)[992e,992d:5)[1264r,1264d:10)[1312e,1312d:4)[1568r,1568d:9)[1616e,1616d:3)[1808r,1808d:8)[1872e,1872d:2)[2080r,2080d:7)[2128e,2128d:1)  0@0B-phi 1@2128e 2@1872e 3@1616e 4@1312e 5@992e 6@224e 7@2080r 8@1808r 9@1568r 10@1264r 11@944r 12@176r
WZR [608r,608d:0)  0@608r
W0 [0B,32r:0)[144r,176r:7)[912r,944r:6)[1232r,1264r:5)[1536r,1568r:4)[1776r,1808r:3)[2048r,2080r:2)[2176r,2192r:1)  0@0B-phi 1@2176r 2@2048r 3@1776r 4@1536r 5@1232r 6@912r 7@144r
%vreg1 [32r,256r:0)  0@32r
%vreg3 [272r,288r:0)  0@272r
%vreg4 [64r,80r:0)  0@64r
%vreg6 [80r,144r:0)  0@80r
%vreg7 [16r,2064r:0)  0@16r
%vreg10 [448r,464r:0)  0@448r
%vreg13 [400r,432r:0)  0@400r
%vreg16 [384r,400r:0)  0@384r
%vreg19 [592r,608r:0)  0@592r
%vreg21 [576r,608r:0)  0@576r
%vreg22 [560r,576r:0)  0@560r
%vreg25 [736r,752r:0)  0@736r
%vreg26 [720r,736r:0)  0@720r
%vreg31 [864r,928r:0)  0@864r
%vreg34 [848r,864r:0)  0@848r
%vreg36 [832r,912r:0)  0@832r
%vreg37 [816r,832r:0)  0@816r
%vreg39 [800r,944r:0)  0@800r
%vreg40 [784r,800r:0)  0@784r
%vreg43 [1056r,1072r:0)  0@1056r
%vreg44 [1040r,1056r:0)  0@1040r
%vreg49 [1184r,1248r:0)  0@1184r
%vreg52 [1168r,1184r:0)  0@1168r
%vreg54 [1152r,1232r:0)  0@1152r
%vreg55 [1136r,1152r:0)  0@1136r
%vreg57 [1120r,1264r:0)  0@1120r
%vreg58 [1104r,1120r:0)  0@1104r
%vreg61 [1376r,1392r:0)  0@1376r
%vreg62 [1360r,1376r:0)  0@1360r
%vreg67 [1504r,1552r:0)  0@1504r
%vreg68 [1488r,1504r:0)  0@1488r
%vreg70 [1472r,1536r:0)  0@1472r
%vreg71 [1456r,1472r:0)  0@1456r
%vreg73 [1440r,1568r:0)  0@1440r
%vreg74 [1424r,1440r:0)  0@1424r
%vreg77 [1904r,1920r:0)  0@1904r
%vreg82 [1744r,1792r:0)  0@1744r
%vreg83 [1728r,1744r:0)  0@1728r
%vreg85 [1712r,1776r:0)  0@1712r
%vreg86 [1696r,1712r:0)  0@1696r
%vreg88 [1680r,1808r:0)  0@1680r
%vreg89 [1664r,1680r:0)  0@1664r
%vreg90 [656r,672r:0)  0@656r
%vreg91 [496r,512r:0)  0@496r
%vreg92 [320r,336r:0)  0@320r
%vreg94 [2160r,2176r:0)  0@2160r
%vreg95 [1968r,1984r:0)  0@1968r
%vreg97 [1984r,2048r:0)  0@1984r
RegMasks: 176r 944r 1264r 1568r 1808r 2080r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzDecompressEnd: Post SSA
Frame Objects:
  fi#0: size=4, align=4, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=8, align=8, at location [SP]
Function Live Ins: %X0 in %vreg0, %LR in %vreg8

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %LR
16B		%vreg7<def> = COPY %LR; GPR64:%vreg7
32B		%vreg1<def> = COPY %X0; GPR64:%vreg1
64B		%vreg4<def> = ADRP <ga:@BZ2_bzDecompressEnd>[TF=1]; GPR64common:%vreg4
80B		%vreg6<def> = ADDXri %vreg4, <ga:@BZ2_bzDecompressEnd>[TF=34], 0; GPR64sp:%vreg6 GPR64common:%vreg4
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		%X0<def> = COPY %vreg6; GPR64sp:%vreg6
160B		%X1<def> = COPY %vreg7; GPR64:%vreg7
176B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
224B		STACKMAP 0, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, %vreg1, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1] GPR64:%vreg1
240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
256B		STRXui %vreg1, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg1
272B		%vreg3<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg3
288B		CBNZX %vreg3, <BB#2>; GPR64:%vreg3
	    Successors according to CFG: BB#2 BB#1

304B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
320B		%vreg92<def> = MOVi32imm 4294967294; GPR32:%vreg92
336B		STRWui %vreg92, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg92
352B		B <BB#13>
	    Successors according to CFG: BB#13

368B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0
384B		%vreg16<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg16
400B		%vreg13<def> = LDRXui %vreg16, 6; mem:LD8[%state] GPR64:%vreg13 GPR64common:%vreg16
432B		STRXui %vreg13, <fi#2>, 0; mem:ST8[FixedStack2] GPR64:%vreg13
448B		%vreg10<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg10
464B		CBNZX %vreg10, <BB#4>; GPR64:%vreg10
	    Successors according to CFG: BB#4 BB#3

480B	BB#3: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#2
496B		%vreg91<def> = MOVi32imm 4294967294; GPR32:%vreg91
512B		STRWui %vreg91, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg91
528B		B <BB#13>
	    Successors according to CFG: BB#13

544B	BB#4: derived from LLVM BB %if.end.3
	    Predecessors according to CFG: BB#2
560B		%vreg22<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg22
576B		%vreg21<def> = LDRXui %vreg22, 0; mem:LD8[%strm4] GPR64:%vreg21 GPR64common:%vreg22
592B		%vreg19<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg19
608B		%XZR<def> = SUBSXrr %vreg21, %vreg19, %NZCV<imp-def>; GPR64:%vreg21,%vreg19
624B		Bcc 0, <BB#6>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#6 BB#5

640B	BB#5: derived from LLVM BB %if.then.6
	    Predecessors according to CFG: BB#4
656B		%vreg90<def> = MOVi32imm 4294967294; GPR32:%vreg90
672B		STRWui %vreg90, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg90
688B		B <BB#13>
	    Successors according to CFG: BB#13

704B	BB#6: derived from LLVM BB %if.end.7
	    Predecessors according to CFG: BB#4
720B		%vreg26<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg26
736B		%vreg25<def> = LDRXui %vreg26, 394; mem:LD8[%tt] GPR64:%vreg25 GPR64common:%vreg26
752B		CBZX %vreg25, <BB#8>; GPR64:%vreg25
	    Successors according to CFG: BB#8 BB#7

768B	BB#7: derived from LLVM BB %if.then.9
	    Predecessors according to CFG: BB#6
784B		%vreg40<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg40
800B		%vreg39<def> = LDRXui %vreg40, 8; mem:LD8[%bzfree] GPR64:%vreg39 GPR64common:%vreg40
816B		%vreg37<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg37
832B		%vreg36<def> = LDRXui %vreg37, 9; mem:LD8[%opaque] GPR64:%vreg36 GPR64common:%vreg37
848B		%vreg34<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg34
864B		%vreg31<def> = LDRXui %vreg34, 394; mem:LD8[%tt10] GPR64:%vreg31 GPR64common:%vreg34
896B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
912B		%X0<def> = COPY %vreg36; GPR64:%vreg36
928B		%X1<def> = COPY %vreg31; GPR64:%vreg31
944B		BLR %vreg39, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>; GPR64:%vreg39
960B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
976B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
992B		STACKMAP 1, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1]
1008B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#8

1024B	BB#8: derived from LLVM BB %if.end.11
	    Predecessors according to CFG: BB#6 BB#7
1040B		%vreg44<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg44
1056B		%vreg43<def> = LDRXui %vreg44, 395; mem:LD8[%ll16] GPR64:%vreg43 GPR64common:%vreg44
1072B		CBZX %vreg43, <BB#10>; GPR64:%vreg43
	    Successors according to CFG: BB#10 BB#9

1088B	BB#9: derived from LLVM BB %if.then.13
	    Predecessors according to CFG: BB#8
1104B		%vreg58<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg58
1120B		%vreg57<def> = LDRXui %vreg58, 8; mem:LD8[%bzfree14] GPR64:%vreg57 GPR64common:%vreg58
1136B		%vreg55<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg55
1152B		%vreg54<def> = LDRXui %vreg55, 9; mem:LD8[%opaque15] GPR64:%vreg54 GPR64common:%vreg55
1168B		%vreg52<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg52
1184B		%vreg49<def> = LDRXui %vreg52, 395; mem:LD8[%ll1616] GPR64:%vreg49 GPR64common:%vreg52
1216B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1232B		%X0<def> = COPY %vreg54; GPR64:%vreg54
1248B		%X1<def> = COPY %vreg49; GPR64:%vreg49
1264B		BLR %vreg57, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>; GPR64:%vreg57
1280B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1296B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1312B		STACKMAP 2, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1]
1328B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#10

1344B	BB#10: derived from LLVM BB %if.end.17
	    Predecessors according to CFG: BB#8 BB#9
1360B		%vreg62<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg62
1376B		%vreg61<def> = LDRXui %vreg62, 396; mem:LD8[%ll4] GPR64:%vreg61 GPR64common:%vreg62
1392B		CBZX %vreg61, <BB#12>; GPR64:%vreg61
	    Successors according to CFG: BB#12 BB#11

1408B	BB#11: derived from LLVM BB %if.then.19
	    Predecessors according to CFG: BB#10
1424B		%vreg74<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg74
1440B		%vreg73<def> = LDRXui %vreg74, 8; mem:LD8[%bzfree20] GPR64:%vreg73 GPR64common:%vreg74
1456B		%vreg71<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg71
1472B		%vreg70<def> = LDRXui %vreg71, 9; mem:LD8[%opaque21] GPR64:%vreg70 GPR64common:%vreg71
1488B		%vreg68<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg68
1504B		%vreg67<def> = LDRXui %vreg68, 396; mem:LD8[%ll422] GPR64:%vreg67 GPR64common:%vreg68
1520B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1536B		%X0<def> = COPY %vreg70; GPR64:%vreg70
1552B		%X1<def> = COPY %vreg67; GPR64:%vreg67
1568B		BLR %vreg73, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>; GPR64:%vreg73
1584B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1600B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1616B		STACKMAP 3, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack1]
1632B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#12

1648B	BB#12: derived from LLVM BB %if.end.23
	    Predecessors according to CFG: BB#10 BB#11
1664B		%vreg89<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg89
1680B		%vreg88<def> = LDRXui %vreg89, 8; mem:LD8[%bzfree24] GPR64:%vreg88 GPR64common:%vreg89
1696B		%vreg86<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg86
1712B		%vreg85<def> = LDRXui %vreg86, 9; mem:LD8[%opaque25] GPR64:%vreg85 GPR64common:%vreg86
1728B		%vreg83<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg83
1744B		%vreg82<def> = LDRXui %vreg83, 6; mem:LD8[%state26] GPR64:%vreg82 GPR64common:%vreg83
1760B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1776B		%X0<def> = COPY %vreg85; GPR64:%vreg85
1792B		%X1<def> = COPY %vreg82; GPR64:%vreg82
1808B		BLR %vreg88, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>; GPR64:%vreg88
1824B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1856B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1872B		STACKMAP 4, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack1]
1888B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1904B		%vreg77<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg77
1920B		STRXui %XZR, %vreg77, 6; mem:ST8[%state27] GPR64common:%vreg77
1936B		STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
	    Successors according to CFG: BB#13

1952B	BB#13: derived from LLVM BB %return
	    Predecessors according to CFG: BB#12 BB#5 BB#3 BB#1
1968B		%vreg95<def> = ADRP <ga:@BZ2_bzDecompressEnd>[TF=1]; GPR64common:%vreg95
1984B		%vreg97<def> = ADDXri %vreg95, <ga:@BZ2_bzDecompressEnd>[TF=34], 0; GPR64sp:%vreg97 GPR64common:%vreg95
2032B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2048B		%X0<def> = COPY %vreg97; GPR64sp:%vreg97
2064B		%X1<def> = COPY %vreg7; GPR64:%vreg7
2080B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
2096B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2112B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2128B		STACKMAP 5, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
2144B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2160B		%vreg94<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0] GPR32:%vreg94
2176B		%W0<def> = COPY %vreg94; GPR32:%vreg94
2192B		RET_ReallyLR %W0<imp-use>

# End machine code for function BZ2_bzDecompressEnd.

handleMove 832B -> 856B: %vreg36<def> = LDRXui %vreg37, 9; mem:LD8[%opaque] GPR64:%vreg36 GPR64common:%vreg37
     %vreg36:	[832r,912r:0)  0@832r
        -->	[856r,912r:0)  0@856r
     %vreg37:	[816r,832r:0)  0@816r
        -->	[816r,856r:0)  0@816r
handleMove 800B -> 852B: %vreg39<def> = LDRXui %vreg40, 8; mem:LD8[%bzfree] GPR64:%vreg39 GPR64common:%vreg40
     %vreg39:	[800r,944r:0)  0@800r
        -->	[852r,944r:0)  0@852r
     %vreg40:	[784r,800r:0)  0@784r
        -->	[784r,852r:0)  0@784r
handleMove 1152B -> 1176B: %vreg54<def> = LDRXui %vreg55, 9; mem:LD8[%opaque15] GPR64:%vreg54 GPR64common:%vreg55
     %vreg54:	[1152r,1232r:0)  0@1152r
        -->	[1176r,1232r:0)  0@1176r
     %vreg55:	[1136r,1152r:0)  0@1136r
        -->	[1136r,1176r:0)  0@1136r
handleMove 1120B -> 1172B: %vreg57<def> = LDRXui %vreg58, 8; mem:LD8[%bzfree14] GPR64:%vreg57 GPR64common:%vreg58
     %vreg57:	[1120r,1264r:0)  0@1120r
        -->	[1172r,1264r:0)  0@1172r
     %vreg58:	[1104r,1120r:0)  0@1104r
        -->	[1104r,1172r:0)  0@1104r
handleMove 1472B -> 1496B: %vreg70<def> = LDRXui %vreg71, 9; mem:LD8[%opaque21] GPR64:%vreg70 GPR64common:%vreg71
     %vreg70:	[1472r,1536r:0)  0@1472r
        -->	[1496r,1536r:0)  0@1496r
     %vreg71:	[1456r,1472r:0)  0@1456r
        -->	[1456r,1496r:0)  0@1456r
handleMove 1440B -> 1492B: %vreg73<def> = LDRXui %vreg74, 8; mem:LD8[%bzfree20] GPR64:%vreg73 GPR64common:%vreg74
     %vreg73:	[1440r,1568r:0)  0@1440r
        -->	[1492r,1568r:0)  0@1492r
     %vreg74:	[1424r,1440r:0)  0@1424r
        -->	[1424r,1492r:0)  0@1424r
handleMove 1712B -> 1736B: %vreg85<def> = LDRXui %vreg86, 9; mem:LD8[%opaque25] GPR64:%vreg85 GPR64common:%vreg86
     %vreg85:	[1712r,1776r:0)  0@1712r
        -->	[1736r,1776r:0)  0@1736r
     %vreg86:	[1696r,1712r:0)  0@1696r
        -->	[1696r,1736r:0)  0@1696r
handleMove 1680B -> 1732B: %vreg88<def> = LDRXui %vreg89, 8; mem:LD8[%bzfree24] GPR64:%vreg88 GPR64common:%vreg89
     %vreg88:	[1680r,1808r:0)  0@1680r
        -->	[1732r,1808r:0)  0@1732r
     %vreg89:	[1664r,1680r:0)  0@1664r
        -->	[1664r,1732r:0)  0@1664r
********** GREEDY REGISTER ALLOCATION **********
********** Function: BZ2_bzDecompressEnd
********** INTERVALS **********
W30 [0B,16r:0)[176r,176d:12)[224e,224d:6)[944r,944d:11)[992e,992d:5)[1264r,1264d:10)[1312e,1312d:4)[1568r,1568d:9)[1616e,1616d:3)[1808r,1808d:8)[1872e,1872d:2)[2080r,2080d:7)[2128e,2128d:1)  0@0B-phi 1@2128e 2@1872e 3@1616e 4@1312e 5@992e 6@224e 7@2080r 8@1808r 9@1568r 10@1264r 11@944r 12@176r
WZR [608r,608d:0)  0@608r
W0 [0B,32r:0)[144r,176r:7)[912r,944r:6)[1232r,1264r:5)[1536r,1568r:4)[1776r,1808r:3)[2048r,2080r:2)[2176r,2192r:1)  0@0B-phi 1@2176r 2@2048r 3@1776r 4@1536r 5@1232r 6@912r 7@144r
%vreg1 [32r,256r:0)  0@32r
%vreg3 [272r,288r:0)  0@272r
%vreg4 [64r,80r:0)  0@64r
%vreg6 [80r,144r:0)  0@80r
%vreg7 [16r,2064r:0)  0@16r
%vreg10 [448r,464r:0)  0@448r
%vreg13 [400r,432r:0)  0@400r
%vreg16 [384r,400r:0)  0@384r
%vreg19 [592r,608r:0)  0@592r
%vreg21 [576r,608r:0)  0@576r
%vreg22 [560r,576r:0)  0@560r
%vreg25 [736r,752r:0)  0@736r
%vreg26 [720r,736r:0)  0@720r
%vreg31 [864r,928r:0)  0@864r
%vreg34 [848r,864r:0)  0@848r
%vreg36 [856r,912r:0)  0@856r
%vreg37 [816r,856r:0)  0@816r
%vreg39 [852r,944r:0)  0@852r
%vreg40 [784r,852r:0)  0@784r
%vreg43 [1056r,1072r:0)  0@1056r
%vreg44 [1040r,1056r:0)  0@1040r
%vreg49 [1184r,1248r:0)  0@1184r
%vreg52 [1168r,1184r:0)  0@1168r
%vreg54 [1176r,1232r:0)  0@1176r
%vreg55 [1136r,1176r:0)  0@1136r
%vreg57 [1172r,1264r:0)  0@1172r
%vreg58 [1104r,1172r:0)  0@1104r
%vreg61 [1376r,1392r:0)  0@1376r
%vreg62 [1360r,1376r:0)  0@1360r
%vreg67 [1504r,1552r:0)  0@1504r
%vreg68 [1488r,1504r:0)  0@1488r
%vreg70 [1496r,1536r:0)  0@1496r
%vreg71 [1456r,1496r:0)  0@1456r
%vreg73 [1492r,1568r:0)  0@1492r
%vreg74 [1424r,1492r:0)  0@1424r
%vreg77 [1904r,1920r:0)  0@1904r
%vreg82 [1744r,1792r:0)  0@1744r
%vreg83 [1728r,1744r:0)  0@1728r
%vreg85 [1736r,1776r:0)  0@1736r
%vreg86 [1696r,1736r:0)  0@1696r
%vreg88 [1732r,1808r:0)  0@1732r
%vreg89 [1664r,1732r:0)  0@1664r
%vreg90 [656r,672r:0)  0@656r
%vreg91 [496r,512r:0)  0@496r
%vreg92 [320r,336r:0)  0@320r
%vreg94 [2160r,2176r:0)  0@2160r
%vreg95 [1968r,1984r:0)  0@1968r
%vreg97 [1984r,2048r:0)  0@1984r
RegMasks: 176r 944r 1264r 1568r 1808r 2080r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzDecompressEnd: Post SSA
Frame Objects:
  fi#0: size=4, align=4, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=8, align=8, at location [SP]
Function Live Ins: %X0 in %vreg0, %LR in %vreg8

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %LR
16B		%vreg7<def> = COPY %LR; GPR64:%vreg7
32B		%vreg1<def> = COPY %X0; GPR64:%vreg1
64B		%vreg4<def> = ADRP <ga:@BZ2_bzDecompressEnd>[TF=1]; GPR64common:%vreg4
80B		%vreg6<def> = ADDXri %vreg4, <ga:@BZ2_bzDecompressEnd>[TF=34], 0; GPR64sp:%vreg6 GPR64common:%vreg4
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		%X0<def> = COPY %vreg6; GPR64sp:%vreg6
160B		%X1<def> = COPY %vreg7; GPR64:%vreg7
176B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
224B		STACKMAP 0, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, %vreg1, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1] GPR64:%vreg1
240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
256B		STRXui %vreg1, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg1
272B		%vreg3<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg3
288B		CBNZX %vreg3, <BB#2>; GPR64:%vreg3
	    Successors according to CFG: BB#2 BB#1

304B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
320B		%vreg92<def> = MOVi32imm 4294967294; GPR32:%vreg92
336B		STRWui %vreg92, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg92
352B		B <BB#13>
	    Successors according to CFG: BB#13

368B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0
384B		%vreg16<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg16
400B		%vreg13<def> = LDRXui %vreg16, 6; mem:LD8[%state] GPR64:%vreg13 GPR64common:%vreg16
432B		STRXui %vreg13, <fi#2>, 0; mem:ST8[FixedStack2] GPR64:%vreg13
448B		%vreg10<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg10
464B		CBNZX %vreg10, <BB#4>; GPR64:%vreg10
	    Successors according to CFG: BB#4 BB#3

480B	BB#3: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#2
496B		%vreg91<def> = MOVi32imm 4294967294; GPR32:%vreg91
512B		STRWui %vreg91, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg91
528B		B <BB#13>
	    Successors according to CFG: BB#13

544B	BB#4: derived from LLVM BB %if.end.3
	    Predecessors according to CFG: BB#2
560B		%vreg22<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg22
576B		%vreg21<def> = LDRXui %vreg22, 0; mem:LD8[%strm4] GPR64:%vreg21 GPR64common:%vreg22
592B		%vreg19<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg19
608B		%XZR<def> = SUBSXrr %vreg21, %vreg19, %NZCV<imp-def>; GPR64:%vreg21,%vreg19
624B		Bcc 0, <BB#6>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#6 BB#5

640B	BB#5: derived from LLVM BB %if.then.6
	    Predecessors according to CFG: BB#4
656B		%vreg90<def> = MOVi32imm 4294967294; GPR32:%vreg90
672B		STRWui %vreg90, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg90
688B		B <BB#13>
	    Successors according to CFG: BB#13

704B	BB#6: derived from LLVM BB %if.end.7
	    Predecessors according to CFG: BB#4
720B		%vreg26<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg26
736B		%vreg25<def> = LDRXui %vreg26, 394; mem:LD8[%tt] GPR64:%vreg25 GPR64common:%vreg26
752B		CBZX %vreg25, <BB#8>; GPR64:%vreg25
	    Successors according to CFG: BB#8 BB#7

768B	BB#7: derived from LLVM BB %if.then.9
	    Predecessors according to CFG: BB#6
784B		%vreg40<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg40
816B		%vreg37<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg37
848B		%vreg34<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg34
852B		%vreg39<def> = LDRXui %vreg40, 8; mem:LD8[%bzfree] GPR64:%vreg39 GPR64common:%vreg40
856B		%vreg36<def> = LDRXui %vreg37, 9; mem:LD8[%opaque] GPR64:%vreg36 GPR64common:%vreg37
864B		%vreg31<def> = LDRXui %vreg34, 394; mem:LD8[%tt10] GPR64:%vreg31 GPR64common:%vreg34
896B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
912B		%X0<def> = COPY %vreg36; GPR64:%vreg36
928B		%X1<def> = COPY %vreg31; GPR64:%vreg31
944B		BLR %vreg39, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>; GPR64:%vreg39
960B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
976B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
992B		STACKMAP 1, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1]
1008B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#8

1024B	BB#8: derived from LLVM BB %if.end.11
	    Predecessors according to CFG: BB#6 BB#7
1040B		%vreg44<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg44
1056B		%vreg43<def> = LDRXui %vreg44, 395; mem:LD8[%ll16] GPR64:%vreg43 GPR64common:%vreg44
1072B		CBZX %vreg43, <BB#10>; GPR64:%vreg43
	    Successors according to CFG: BB#10 BB#9

1088B	BB#9: derived from LLVM BB %if.then.13
	    Predecessors according to CFG: BB#8
1104B		%vreg58<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg58
1136B		%vreg55<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg55
1168B		%vreg52<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg52
1172B		%vreg57<def> = LDRXui %vreg58, 8; mem:LD8[%bzfree14] GPR64:%vreg57 GPR64common:%vreg58
1176B		%vreg54<def> = LDRXui %vreg55, 9; mem:LD8[%opaque15] GPR64:%vreg54 GPR64common:%vreg55
1184B		%vreg49<def> = LDRXui %vreg52, 395; mem:LD8[%ll1616] GPR64:%vreg49 GPR64common:%vreg52
1216B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1232B		%X0<def> = COPY %vreg54; GPR64:%vreg54
1248B		%X1<def> = COPY %vreg49; GPR64:%vreg49
1264B		BLR %vreg57, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>; GPR64:%vreg57
1280B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1296B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1312B		STACKMAP 2, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1]
1328B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#10

1344B	BB#10: derived from LLVM BB %if.end.17
	    Predecessors according to CFG: BB#8 BB#9
1360B		%vreg62<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg62
1376B		%vreg61<def> = LDRXui %vreg62, 396; mem:LD8[%ll4] GPR64:%vreg61 GPR64common:%vreg62
1392B		CBZX %vreg61, <BB#12>; GPR64:%vreg61
	    Successors according to CFG: BB#12 BB#11

1408B	BB#11: derived from LLVM BB %if.then.19
	    Predecessors according to CFG: BB#10
1424B		%vreg74<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg74
1456B		%vreg71<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg71
1488B		%vreg68<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg68
1492B		%vreg73<def> = LDRXui %vreg74, 8; mem:LD8[%bzfree20] GPR64:%vreg73 GPR64common:%vreg74
1496B		%vreg70<def> = LDRXui %vreg71, 9; mem:LD8[%opaque21] GPR64:%vreg70 GPR64common:%vreg71
1504B		%vreg67<def> = LDRXui %vreg68, 396; mem:LD8[%ll422] GPR64:%vreg67 GPR64common:%vreg68
1520B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1536B		%X0<def> = COPY %vreg70; GPR64:%vreg70
1552B		%X1<def> = COPY %vreg67; GPR64:%vreg67
1568B		BLR %vreg73, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>; GPR64:%vreg73
1584B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1600B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1616B		STACKMAP 3, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack1]
1632B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#12

1648B	BB#12: derived from LLVM BB %if.end.23
	    Predecessors according to CFG: BB#10 BB#11
1664B		%vreg89<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg89
1696B		%vreg86<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg86
1728B		%vreg83<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg83
1732B		%vreg88<def> = LDRXui %vreg89, 8; mem:LD8[%bzfree24] GPR64:%vreg88 GPR64common:%vreg89
1736B		%vreg85<def> = LDRXui %vreg86, 9; mem:LD8[%opaque25] GPR64:%vreg85 GPR64common:%vreg86
1744B		%vreg82<def> = LDRXui %vreg83, 6; mem:LD8[%state26] GPR64:%vreg82 GPR64common:%vreg83
1760B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1776B		%X0<def> = COPY %vreg85; GPR64:%vreg85
1792B		%X1<def> = COPY %vreg82; GPR64:%vreg82
1808B		BLR %vreg88, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>; GPR64:%vreg88
1824B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1856B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1872B		STACKMAP 4, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack1]
1888B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1904B		%vreg77<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg77
1920B		STRXui %XZR, %vreg77, 6; mem:ST8[%state27] GPR64common:%vreg77
1936B		STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
	    Successors according to CFG: BB#13

1952B	BB#13: derived from LLVM BB %return
	    Predecessors according to CFG: BB#12 BB#5 BB#3 BB#1
1968B		%vreg95<def> = ADRP <ga:@BZ2_bzDecompressEnd>[TF=1]; GPR64common:%vreg95
1984B		%vreg97<def> = ADDXri %vreg95, <ga:@BZ2_bzDecompressEnd>[TF=34], 0; GPR64sp:%vreg97 GPR64common:%vreg95
2032B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2048B		%X0<def> = COPY %vreg97; GPR64sp:%vreg97
2064B		%X1<def> = COPY %vreg7; GPR64:%vreg7
2080B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
2096B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2112B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2128B		STACKMAP 5, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
2144B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2160B		%vreg94<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0] GPR32:%vreg94
2176B		%W0<def> = COPY %vreg94; GPR32:%vreg94
2192B		RET_ReallyLR %W0<imp-use>

# End machine code for function BZ2_bzDecompressEnd.


selectOrSplit GPR64:%vreg7 [16r,2064r:0)  0@16r w=1.237745e-03
hints: %X1
missed hint %X1
assigning %vreg7 to %X19: W19 [16r,2064r:0)  0@16r

selectOrSplit GPR64:%vreg1 [32r,256r:0)  0@32r w=4.855769e-03
hints: %X0
missed hint %X0
assigning %vreg1 to %X20: W20 [32r,256r:0)  0@32r

selectOrSplit GPR64sp:%vreg6 [80r,144r:0)  0@80r w=4.353448e-03
hints: %X0
assigning %vreg6 to %X0: W0 [80r,144r:0)  0@80r

selectOrSplit GPR64:%vreg36 [856r,912r:0)  0@856r w=2.790441e-04
hints: %X0
assigning %vreg36 to %X0: W0 [856r,912r:0)  0@856r

selectOrSplit GPR64:%vreg31 [864r,928r:0)  0@864r w=2.742330e-04
hints: %X1
assigning %vreg31 to %X1: W1 [864r,928r:0)  0@864r

selectOrSplit GPR64:%vreg54 [1176r,1232r:0)  0@1176r w=2.790441e-04
hints: %X0
assigning %vreg54 to %X0: W0 [1176r,1232r:0)  0@1176r

selectOrSplit GPR64:%vreg49 [1184r,1248r:0)  0@1184r w=2.742330e-04
hints: %X1
assigning %vreg49 to %X1: W1 [1184r,1248r:0)  0@1184r

selectOrSplit GPR64:%vreg70 [1496r,1536r:0)  0@1496r w=2.891911e-04
hints: %X0
assigning %vreg70 to %X0: W0 [1496r,1536r:0)  0@1496r

selectOrSplit GPR64:%vreg67 [1504r,1552r:0)  0@1504r w=2.840270e-04
hints: %X1
assigning %vreg67 to %X1: W1 [1504r,1552r:0)  0@1504r

selectOrSplit GPR64:%vreg85 [1736r,1776r:0)  0@1736r w=5.422333e-04
hints: %X0
assigning %vreg85 to %X0: W0 [1736r,1776r:0)  0@1736r

selectOrSplit GPR64:%vreg82 [1744r,1792r:0)  0@1744r w=5.325506e-04
hints: %X1
assigning %vreg82 to %X1: W1 [1744r,1792r:0)  0@1744r

selectOrSplit GPR64sp:%vreg97 [1984r,2048r:0)  0@1984r w=4.353448e-03
hints: %X0
assigning %vreg97 to %X0: W0 [1984r,2048r:0)  0@1984r

selectOrSplit GPR32:%vreg94 [2160r,2176r:0)  0@2160r w=inf
hints: %W0
assigning %vreg94 to %W0: W0 [2160r,2176r:0)  0@2160r

selectOrSplit GPR64common:%vreg4 [64r,80r:0)  0@64r w=inf
assigning %vreg4 to %X8: W8 [64r,80r:0)  0@64r

selectOrSplit GPR64:%vreg3 [272r,288r:0)  0@272r w=inf
assigning %vreg3 to %X8: W8 [272r,288r:0)  0@272r

selectOrSplit GPR32:%vreg92 [320r,336r:0)  0@320r w=inf
assigning %vreg92 to %W8: W8 [320r,336r:0)  0@320r

selectOrSplit GPR64common:%vreg16 [384r,400r:0)  0@384r w=inf
assigning %vreg16 to %X8: W8 [384r,400r:0)  0@384r

selectOrSplit GPR64:%vreg13 [400r,432r:0)  0@400r w=inf
assigning %vreg13 to %X8: W8 [400r,432r:0)  0@400r

selectOrSplit GPR64:%vreg10 [448r,464r:0)  0@448r w=inf
assigning %vreg10 to %X8: W8 [448r,464r:0)  0@448r

selectOrSplit GPR32:%vreg91 [496r,512r:0)  0@496r w=inf
assigning %vreg91 to %W8: W8 [496r,512r:0)  0@496r

selectOrSplit GPR64common:%vreg22 [560r,576r:0)  0@560r w=inf
assigning %vreg22 to %X8: W8 [560r,576r:0)  0@560r

selectOrSplit GPR64:%vreg21 [576r,608r:0)  0@576r w=1.130067e-03
assigning %vreg21 to %X8: W8 [576r,608r:0)  0@576r

selectOrSplit GPR64:%vreg19 [592r,608r:0)  0@592r w=inf
assigning %vreg19 to %X9: W9 [592r,608r:0)  0@592r

selectOrSplit GPR32:%vreg90 [656r,672r:0)  0@656r w=inf
assigning %vreg90 to %W8: W8 [656r,672r:0)  0@656r

selectOrSplit GPR64common:%vreg26 [720r,736r:0)  0@720r w=inf
assigning %vreg26 to %X8: W8 [720r,736r:0)  0@720r

selectOrSplit GPR64:%vreg25 [736r,752r:0)  0@736r w=inf
assigning %vreg25 to %X8: W8 [736r,752r:0)  0@736r

selectOrSplit GPR64common:%vreg40 [784r,852r:0)  0@784r w=2.691971e-04
assigning %vreg40 to %X8: W8 [784r,852r:0)  0@784r

selectOrSplit GPR64common:%vreg37 [816r,856r:0)  0@816r w=2.863278e-04
assigning %vreg37 to %X9: W9 [816r,856r:0)  0@816r

selectOrSplit GPR64common:%vreg34 [848r,864r:0)  0@848r w=3.028467e-04
assigning %vreg34 to %X10: W10 [848r,864r:0)  0@848r

selectOrSplit GPR64:%vreg39 [852r,944r:0)  0@852r w=2.560655e-04
assigning %vreg39 to %X8: W8 [852r,944r:0)  0@852r

selectOrSplit GPR64common:%vreg44 [1040r,1056r:0)  0@1040r w=inf
assigning %vreg44 to %X8: W8 [1040r,1056r:0)  0@1040r

selectOrSplit GPR64:%vreg43 [1056r,1072r:0)  0@1056r w=inf
assigning %vreg43 to %X8: W8 [1056r,1072r:0)  0@1056r

selectOrSplit GPR64common:%vreg58 [1104r,1172r:0)  0@1104r w=2.691971e-04
assigning %vreg58 to %X8: W8 [1104r,1172r:0)  0@1104r

selectOrSplit GPR64common:%vreg55 [1136r,1176r:0)  0@1136r w=2.863278e-04
assigning %vreg55 to %X9: W9 [1136r,1176r:0)  0@1136r

selectOrSplit GPR64common:%vreg52 [1168r,1184r:0)  0@1168r w=3.028467e-04
assigning %vreg52 to %X10: W10 [1168r,1184r:0)  0@1168r

selectOrSplit GPR64:%vreg57 [1172r,1264r:0)  0@1172r w=2.560655e-04
assigning %vreg57 to %X8: W8 [1172r,1264r:0)  0@1172r

selectOrSplit GPR64common:%vreg62 [1360r,1376r:0)  0@1360r w=inf
assigning %vreg62 to %X8: W8 [1360r,1376r:0)  0@1360r

selectOrSplit GPR64:%vreg61 [1376r,1392r:0)  0@1376r w=inf
assigning %vreg61 to %X8: W8 [1376r,1392r:0)  0@1376r

selectOrSplit GPR64common:%vreg74 [1424r,1492r:0)  0@1424r w=2.691971e-04
assigning %vreg74 to %X8: W8 [1424r,1492r:0)  0@1424r

selectOrSplit GPR64common:%vreg71 [1456r,1496r:0)  0@1456r w=2.863278e-04
assigning %vreg71 to %X9: W9 [1456r,1496r:0)  0@1456r

selectOrSplit GPR64common:%vreg68 [1488r,1504r:0)  0@1488r w=3.028467e-04
assigning %vreg68 to %X10: W10 [1488r,1504r:0)  0@1488r

selectOrSplit GPR64:%vreg73 [1492r,1568r:0)  0@1492r w=2.646728e-04
assigning %vreg73 to %X8: W8 [1492r,1568r:0)  0@1492r

selectOrSplit GPR64common:%vreg89 [1664r,1732r:0)  0@1664r w=5.047446e-04
assigning %vreg89 to %X8: W8 [1664r,1732r:0)  0@1664r

selectOrSplit GPR64common:%vreg86 [1696r,1736r:0)  0@1696r w=5.368647e-04
assigning %vreg86 to %X9: W9 [1696r,1736r:0)  0@1696r

selectOrSplit GPR64common:%vreg83 [1728r,1744r:0)  0@1728r w=5.678377e-04
assigning %vreg83 to %X10: W10 [1728r,1744r:0)  0@1728r

selectOrSplit GPR64:%vreg88 [1732r,1808r:0)  0@1732r w=4.962615e-04
assigning %vreg88 to %X8: W8 [1732r,1808r:0)  0@1732r

selectOrSplit GPR64common:%vreg77 [1904r,1920r:0)  0@1904r w=inf
assigning %vreg77 to %X8: W8 [1904r,1920r:0)  0@1904r

selectOrSplit GPR64common:%vreg95 [1968r,1984r:0)  0@1968r w=inf
assigning %vreg95 to %X8: W8 [1968r,1984r:0)  0@1968r

********** STACK TRANSFORMATION METADATA **********
********** Function: BZ2_bzDecompressEnd
********** REGISTER MAP **********
[%vreg1 -> %X20] GPR64
[%vreg3 -> %X8] GPR64
[%vreg4 -> %X8] GPR64common
[%vreg6 -> %X0] GPR64sp
[%vreg7 -> %X19] GPR64
[%vreg10 -> %X8] GPR64
[%vreg13 -> %X8] GPR64
[%vreg16 -> %X8] GPR64common
[%vreg19 -> %X9] GPR64
[%vreg21 -> %X8] GPR64
[%vreg22 -> %X8] GPR64common
[%vreg25 -> %X8] GPR64
[%vreg26 -> %X8] GPR64common
[%vreg31 -> %X1] GPR64
[%vreg34 -> %X10] GPR64common
[%vreg36 -> %X0] GPR64
[%vreg37 -> %X9] GPR64common
[%vreg39 -> %X8] GPR64
[%vreg40 -> %X8] GPR64common
[%vreg43 -> %X8] GPR64
[%vreg44 -> %X8] GPR64common
[%vreg49 -> %X1] GPR64
[%vreg52 -> %X10] GPR64common
[%vreg54 -> %X0] GPR64
[%vreg55 -> %X9] GPR64common
[%vreg57 -> %X8] GPR64
[%vreg58 -> %X8] GPR64common
[%vreg61 -> %X8] GPR64
[%vreg62 -> %X8] GPR64common
[%vreg67 -> %X1] GPR64
[%vreg68 -> %X10] GPR64common
[%vreg70 -> %X0] GPR64
[%vreg71 -> %X9] GPR64common
[%vreg73 -> %X8] GPR64
[%vreg74 -> %X8] GPR64common
[%vreg77 -> %X8] GPR64common
[%vreg82 -> %X1] GPR64
[%vreg83 -> %X10] GPR64common
[%vreg85 -> %X0] GPR64
[%vreg86 -> %X9] GPR64common
[%vreg88 -> %X8] GPR64
[%vreg89 -> %X8] GPR64common
[%vreg90 -> %W8] GPR32
[%vreg91 -> %W8] GPR32
[%vreg92 -> %W8] GPR32
[%vreg94 -> %W0] GPR32
[%vreg95 -> %X8] GPR64common
[%vreg97 -> %X0] GPR64sp


Stackmap 0:
  STACKMAP 0, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, %vreg1, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1] GPR64:%vreg1

i32* %retval: in stack slot 0 (size: 4)
%struct.DState** %s: in stack slot 2 (size: 8)
%struct.bz_stream* %strm: in register %X20 (vreg 1)
%struct.bz_stream** %strm.addr: in stack slot 1 (size: 8)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1]

i32* %retval: in stack slot 0 (size: 4)
%struct.DState** %s: in stack slot 2 (size: 8)
%struct.bz_stream** %strm.addr: in stack slot 1 (size: 8)

Duplicate operand locations:


Stackmap 2:
  STACKMAP 2, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1]

i32* %retval: in stack slot 0 (size: 4)
%struct.DState** %s: in stack slot 2 (size: 8)
%struct.bz_stream** %strm.addr: in stack slot 1 (size: 8)

Duplicate operand locations:


Stackmap 3:
  STACKMAP 3, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack1]

i32* %retval: in stack slot 0 (size: 4)
%struct.bz_stream** %strm.addr: in stack slot 1 (size: 8)

Duplicate operand locations:


Stackmap 4:
  STACKMAP 4, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack1]

i32* %retval: in stack slot 0 (size: 4)
%struct.bz_stream** %strm.addr: in stack slot 1 (size: 8)

Duplicate operand locations:


Stackmap 5:
  STACKMAP 5, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)

i32* %retval: in stack slot 0 (size: 4)

Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, %vreg1, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1] GPR64:%vreg1
  -> Call instruction SlotIndex 176B, searching vregs 0 -> 99 and stack slots 0 -> 3
    + vreg7 is live in register but not in stackmap
      Defining instruction: %vreg7<def> = COPY %LR; GPR64:%vreg7
      Value: generated value, 1 instruction(s)

  STACKMAP 1, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1]
  -> Call instruction SlotIndex 944B, searching vregs 0 -> 99 and stack slots 0 -> 3
    + vreg7 is live in register but not in stackmap
      Defining instruction: %vreg7<def> = COPY %LR; GPR64:%vreg7
      Value: generated value, 1 instruction(s)

  STACKMAP 2, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1]
  -> Call instruction SlotIndex 1264B, searching vregs 0 -> 99 and stack slots 0 -> 3
    + vreg7 is live in register but not in stackmap
      Defining instruction: %vreg7<def> = COPY %LR; GPR64:%vreg7
      Value: generated value, 1 instruction(s)

  STACKMAP 3, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack1]
  -> Call instruction SlotIndex 1568B, searching vregs 0 -> 99 and stack slots 0 -> 3
    + vreg7 is live in register but not in stackmap
      Defining instruction: %vreg7<def> = COPY %LR; GPR64:%vreg7
      Value: generated value, 1 instruction(s)

  STACKMAP 4, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack1]
  -> Call instruction SlotIndex 1808B, searching vregs 0 -> 99 and stack slots 0 -> 3
    + vreg7 is live in register but not in stackmap
      Defining instruction: %vreg7<def> = COPY %LR; GPR64:%vreg7
      Value: generated value, 1 instruction(s)

  STACKMAP 5, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
  -> Call instruction SlotIndex 2080B, searching vregs 0 -> 99 and stack slots 0 -> 3

********** REWRITE VIRTUAL REGISTERS **********
********** Function: BZ2_bzDecompressEnd
********** REGISTER MAP **********
[%vreg1 -> %X20] GPR64
[%vreg3 -> %X8] GPR64
[%vreg4 -> %X8] GPR64common
[%vreg6 -> %X0] GPR64sp
[%vreg7 -> %X19] GPR64
[%vreg10 -> %X8] GPR64
[%vreg13 -> %X8] GPR64
[%vreg16 -> %X8] GPR64common
[%vreg19 -> %X9] GPR64
[%vreg21 -> %X8] GPR64
[%vreg22 -> %X8] GPR64common
[%vreg25 -> %X8] GPR64
[%vreg26 -> %X8] GPR64common
[%vreg31 -> %X1] GPR64
[%vreg34 -> %X10] GPR64common
[%vreg36 -> %X0] GPR64
[%vreg37 -> %X9] GPR64common
[%vreg39 -> %X8] GPR64
[%vreg40 -> %X8] GPR64common
[%vreg43 -> %X8] GPR64
[%vreg44 -> %X8] GPR64common
[%vreg49 -> %X1] GPR64
[%vreg52 -> %X10] GPR64common
[%vreg54 -> %X0] GPR64
[%vreg55 -> %X9] GPR64common
[%vreg57 -> %X8] GPR64
[%vreg58 -> %X8] GPR64common
[%vreg61 -> %X8] GPR64
[%vreg62 -> %X8] GPR64common
[%vreg67 -> %X1] GPR64
[%vreg68 -> %X10] GPR64common
[%vreg70 -> %X0] GPR64
[%vreg71 -> %X9] GPR64common
[%vreg73 -> %X8] GPR64
[%vreg74 -> %X8] GPR64common
[%vreg77 -> %X8] GPR64common
[%vreg82 -> %X1] GPR64
[%vreg83 -> %X10] GPR64common
[%vreg85 -> %X0] GPR64
[%vreg86 -> %X9] GPR64common
[%vreg88 -> %X8] GPR64
[%vreg89 -> %X8] GPR64common
[%vreg90 -> %W8] GPR32
[%vreg91 -> %W8] GPR32
[%vreg92 -> %W8] GPR32
[%vreg94 -> %W0] GPR32
[%vreg95 -> %X8] GPR64common
[%vreg97 -> %X0] GPR64sp

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %LR %X0
16B		%vreg7<def> = COPY %LR; GPR64:%vreg7
32B		%vreg1<def> = COPY %X0; GPR64:%vreg1
64B		%vreg4<def> = ADRP <ga:@BZ2_bzDecompressEnd>[TF=1]; GPR64common:%vreg4
80B		%vreg6<def> = ADDXri %vreg4<kill>, <ga:@BZ2_bzDecompressEnd>[TF=34], 0; GPR64sp:%vreg6 GPR64common:%vreg4
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		%X0<def> = COPY %vreg6<kill>; GPR64sp:%vreg6
160B		%X1<def> = COPY %vreg7; GPR64:%vreg7
176B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
224B		STACKMAP 0, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, %vreg1, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1] GPR64:%vreg1
240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
256B		STRXui %vreg1<kill>, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg1
272B		%vreg3<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg3
288B		CBNZX %vreg3<kill>, <BB#2>; GPR64:%vreg3
	    Successors according to CFG: BB#2 BB#1
> %X19<def> = COPY %LR
> %X20<def> = COPY %X0
> %X8<def> = ADRP <ga:@BZ2_bzDecompressEnd>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@BZ2_bzDecompressEnd>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19
> BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 0, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, %X20, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRXui %X20<kill>, <fi#1>, 0; mem:ST8[FixedStack1]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> CBNZX %X8<kill>, <BB#2>
304B	BB#1: derived from LLVM BB %if.then
	    Live Ins: %X19
	    Predecessors according to CFG: BB#0
320B		%vreg92<def> = MOVi32imm 4294967294; GPR32:%vreg92
336B		STRWui %vreg92<kill>, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg92
352B		B <BB#13>
	    Successors according to CFG: BB#13
> %W8<def> = MOVi32imm 4294967294
> STRWui %W8<kill>, <fi#0>, 0; mem:ST4[FixedStack0]
> B <BB#13>
368B	BB#2: derived from LLVM BB %if.end
	    Live Ins: %X19
	    Predecessors according to CFG: BB#0
384B		%vreg16<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg16
400B		%vreg13<def> = LDRXui %vreg16<kill>, 6; mem:LD8[%state] GPR64:%vreg13 GPR64common:%vreg16
432B		STRXui %vreg13<kill>, <fi#2>, 0; mem:ST8[FixedStack2] GPR64:%vreg13
448B		%vreg10<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg10
464B		CBNZX %vreg10<kill>, <BB#4>; GPR64:%vreg10
	    Successors according to CFG: BB#4 BB#3
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X8<def> = LDRXui %X8<kill>, 6; mem:LD8[%state]
> STRXui %X8<kill>, <fi#2>, 0; mem:ST8[FixedStack2]
> %X8<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2]
> CBNZX %X8<kill>, <BB#4>
480B	BB#3: derived from LLVM BB %if.then.2
	    Live Ins: %X19
	    Predecessors according to CFG: BB#2
496B		%vreg91<def> = MOVi32imm 4294967294; GPR32:%vreg91
512B		STRWui %vreg91<kill>, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg91
528B		B <BB#13>
	    Successors according to CFG: BB#13
> %W8<def> = MOVi32imm 4294967294
> STRWui %W8<kill>, <fi#0>, 0; mem:ST4[FixedStack0]
> B <BB#13>
544B	BB#4: derived from LLVM BB %if.end.3
	    Live Ins: %X19
	    Predecessors according to CFG: BB#2
560B		%vreg22<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg22
576B		%vreg21<def> = LDRXui %vreg22<kill>, 0; mem:LD8[%strm4] GPR64:%vreg21 GPR64common:%vreg22
592B		%vreg19<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg19
608B		%XZR<def> = SUBSXrr %vreg21<kill>, %vreg19<kill>, %NZCV<imp-def>; GPR64:%vreg21,%vreg19
624B		Bcc 0, <BB#6>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#6 BB#5
> %X8<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2]
> %X8<def> = LDRXui %X8<kill>, 0; mem:LD8[%strm4]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %XZR<def> = SUBSXrr %X8<kill>, %X9<kill>, %NZCV<imp-def>
> Bcc 0, <BB#6>, %NZCV<imp-use,kill>
640B	BB#5: derived from LLVM BB %if.then.6
	    Live Ins: %X19
	    Predecessors according to CFG: BB#4
656B		%vreg90<def> = MOVi32imm 4294967294; GPR32:%vreg90
672B		STRWui %vreg90<kill>, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg90
688B		B <BB#13>
	    Successors according to CFG: BB#13
> %W8<def> = MOVi32imm 4294967294
> STRWui %W8<kill>, <fi#0>, 0; mem:ST4[FixedStack0]
> B <BB#13>
704B	BB#6: derived from LLVM BB %if.end.7
	    Live Ins: %X19
	    Predecessors according to CFG: BB#4
720B		%vreg26<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg26
736B		%vreg25<def> = LDRXui %vreg26<kill>, 394; mem:LD8[%tt] GPR64:%vreg25 GPR64common:%vreg26
752B		CBZX %vreg25<kill>, <BB#8>; GPR64:%vreg25
	    Successors according to CFG: BB#8 BB#7
> %X8<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2]
> %X8<def> = LDRXui %X8<kill>, 394; mem:LD8[%tt]
> CBZX %X8<kill>, <BB#8>
768B	BB#7: derived from LLVM BB %if.then.9
	    Live Ins: %X19
	    Predecessors according to CFG: BB#6
784B		%vreg40<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg40
816B		%vreg37<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg37
848B		%vreg34<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg34
852B		%vreg39<def> = LDRXui %vreg40<kill>, 8; mem:LD8[%bzfree] GPR64:%vreg39 GPR64common:%vreg40
856B		%vreg36<def> = LDRXui %vreg37<kill>, 9; mem:LD8[%opaque] GPR64:%vreg36 GPR64common:%vreg37
864B		%vreg31<def> = LDRXui %vreg34<kill>, 394; mem:LD8[%tt10] GPR64:%vreg31 GPR64common:%vreg34
896B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
912B		%X0<def> = COPY %vreg36<kill>; GPR64:%vreg36
928B		%X1<def> = COPY %vreg31<kill>; GPR64:%vreg31
944B		BLR %vreg39<kill>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>; GPR64:%vreg39
960B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
976B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
992B		STACKMAP 1, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1]
1008B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#8
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X10<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2]
> %X8<def> = LDRXui %X8<kill>, 8; mem:LD8[%bzfree]
> %X0<def> = LDRXui %X9<kill>, 9; mem:LD8[%opaque]
> %X1<def> = LDRXui %X10<kill>, 394; mem:LD8[%tt10]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X1<kill>
Deleting identity copy.
> BLR %X8<kill>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 1, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1024B	BB#8: derived from LLVM BB %if.end.11
	    Live Ins: %X19
	    Predecessors according to CFG: BB#6 BB#7
1040B		%vreg44<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg44
1056B		%vreg43<def> = LDRXui %vreg44<kill>, 395; mem:LD8[%ll16] GPR64:%vreg43 GPR64common:%vreg44
1072B		CBZX %vreg43<kill>, <BB#10>; GPR64:%vreg43
	    Successors according to CFG: BB#10 BB#9
> %X8<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2]
> %X8<def> = LDRXui %X8<kill>, 395; mem:LD8[%ll16]
> CBZX %X8<kill>, <BB#10>
1088B	BB#9: derived from LLVM BB %if.then.13
	    Live Ins: %X19
	    Predecessors according to CFG: BB#8
1104B		%vreg58<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg58
1136B		%vreg55<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg55
1168B		%vreg52<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg52
1172B		%vreg57<def> = LDRXui %vreg58<kill>, 8; mem:LD8[%bzfree14] GPR64:%vreg57 GPR64common:%vreg58
1176B		%vreg54<def> = LDRXui %vreg55<kill>, 9; mem:LD8[%opaque15] GPR64:%vreg54 GPR64common:%vreg55
1184B		%vreg49<def> = LDRXui %vreg52<kill>, 395; mem:LD8[%ll1616] GPR64:%vreg49 GPR64common:%vreg52
1216B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1232B		%X0<def> = COPY %vreg54<kill>; GPR64:%vreg54
1248B		%X1<def> = COPY %vreg49<kill>; GPR64:%vreg49
1264B		BLR %vreg57<kill>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>; GPR64:%vreg57
1280B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1296B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1312B		STACKMAP 2, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1]
1328B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#10
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X10<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2]
> %X8<def> = LDRXui %X8<kill>, 8; mem:LD8[%bzfree14]
> %X0<def> = LDRXui %X9<kill>, 9; mem:LD8[%opaque15]
> %X1<def> = LDRXui %X10<kill>, 395; mem:LD8[%ll1616]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X1<kill>
Deleting identity copy.
> BLR %X8<kill>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 2, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1344B	BB#10: derived from LLVM BB %if.end.17
	    Live Ins: %X19
	    Predecessors according to CFG: BB#8 BB#9
1360B		%vreg62<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg62
1376B		%vreg61<def> = LDRXui %vreg62<kill>, 396; mem:LD8[%ll4] GPR64:%vreg61 GPR64common:%vreg62
1392B		CBZX %vreg61<kill>, <BB#12>; GPR64:%vreg61
	    Successors according to CFG: BB#12 BB#11
> %X8<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2]
> %X8<def> = LDRXui %X8<kill>, 396; mem:LD8[%ll4]
> CBZX %X8<kill>, <BB#12>
1408B	BB#11: derived from LLVM BB %if.then.19
	    Live Ins: %X19
	    Predecessors according to CFG: BB#10
1424B		%vreg74<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg74
1456B		%vreg71<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg71
1488B		%vreg68<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg68
1492B		%vreg73<def> = LDRXui %vreg74<kill>, 8; mem:LD8[%bzfree20] GPR64:%vreg73 GPR64common:%vreg74
1496B		%vreg70<def> = LDRXui %vreg71<kill>, 9; mem:LD8[%opaque21] GPR64:%vreg70 GPR64common:%vreg71
1504B		%vreg67<def> = LDRXui %vreg68<kill>, 396; mem:LD8[%ll422] GPR64:%vreg67 GPR64common:%vreg68
1520B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1536B		%X0<def> = COPY %vreg70<kill>; GPR64:%vreg70
1552B		%X1<def> = COPY %vreg67<kill>; GPR64:%vreg67
1568B		BLR %vreg73<kill>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>; GPR64:%vreg73
1584B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1600B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1616B		STACKMAP 3, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack1]
1632B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#12
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X10<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2]
> %X8<def> = LDRXui %X8<kill>, 8; mem:LD8[%bzfree20]
> %X0<def> = LDRXui %X9<kill>, 9; mem:LD8[%opaque21]
> %X1<def> = LDRXui %X10<kill>, 396; mem:LD8[%ll422]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X1<kill>
Deleting identity copy.
> BLR %X8<kill>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 3, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack1]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1648B	BB#12: derived from LLVM BB %if.end.23
	    Live Ins: %X19
	    Predecessors according to CFG: BB#10 BB#11
1664B		%vreg89<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg89
1696B		%vreg86<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg86
1728B		%vreg83<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg83
1732B		%vreg88<def> = LDRXui %vreg89<kill>, 8; mem:LD8[%bzfree24] GPR64:%vreg88 GPR64common:%vreg89
1736B		%vreg85<def> = LDRXui %vreg86<kill>, 9; mem:LD8[%opaque25] GPR64:%vreg85 GPR64common:%vreg86
1744B		%vreg82<def> = LDRXui %vreg83<kill>, 6; mem:LD8[%state26] GPR64:%vreg82 GPR64common:%vreg83
1760B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1776B		%X0<def> = COPY %vreg85<kill>; GPR64:%vreg85
1792B		%X1<def> = COPY %vreg82<kill>; GPR64:%vreg82
1808B		BLR %vreg88<kill>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>; GPR64:%vreg88
1824B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1856B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1872B		STACKMAP 4, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack1]
1888B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1904B		%vreg77<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg77
1920B		STRXui %XZR, %vreg77<kill>, 6; mem:ST8[%state27] GPR64common:%vreg77
1936B		STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
	    Successors according to CFG: BB#13
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X10<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X8<def> = LDRXui %X8<kill>, 8; mem:LD8[%bzfree24]
> %X0<def> = LDRXui %X9<kill>, 9; mem:LD8[%opaque25]
> %X1<def> = LDRXui %X10<kill>, 6; mem:LD8[%state26]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X1<kill>
Deleting identity copy.
> BLR %X8<kill>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 4, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack1]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRXui %XZR, %X8<kill>, 6; mem:ST8[%state27]
> STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
1952B	BB#13: derived from LLVM BB %return
	    Live Ins: %X19
	    Predecessors according to CFG: BB#12 BB#5 BB#3 BB#1
1968B		%vreg95<def> = ADRP <ga:@BZ2_bzDecompressEnd>[TF=1]; GPR64common:%vreg95
1984B		%vreg97<def> = ADDXri %vreg95<kill>, <ga:@BZ2_bzDecompressEnd>[TF=34], 0; GPR64sp:%vreg97 GPR64common:%vreg95
2032B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2048B		%X0<def> = COPY %vreg97<kill>; GPR64sp:%vreg97
2064B		%X1<def> = COPY %vreg7<kill>; GPR64:%vreg7
2080B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
2096B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2112B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2128B		STACKMAP 5, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
2144B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2160B		%vreg94<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0] GPR32:%vreg94
2176B		%W0<def> = COPY %vreg94<kill>; GPR32:%vreg94
2192B		RET_ReallyLR %W0<imp-use>
> %X8<def> = ADRP <ga:@BZ2_bzDecompressEnd>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@BZ2_bzDecompressEnd>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19<kill>
> BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 5, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0]
> %W0<def> = COPY %W0<kill>
Deleting identity copy.
> RET_ReallyLR %W0<imp-use>
Computing live-in reg-units in ABI blocks.
0B	BB#0 W0#0 W1#0 W2#0 W3#0 W4#0 W30#0
Created 6 new intervals.
********** INTERVALS **********
W30 [0B,16r:0)[304r,304d:12)[368e,368d:6)[1424r,1424d:11)[1488e,1488d:5)[1888r,1888d:10)[1952e,1952d:4)[3152r,3152d:9)[3216e,3216d:3)[3600r,3600d:8)[3664e,3664d:2)[4032r,4032d:7)[4080e,4080d:1)  0@0B-phi 1@4080e 2@3664e 3@3216e 4@1952e 5@1488e 6@368e 7@4032r 8@3600r 9@3152r 10@1888r 11@1424r 12@304r
W0 [0B,96r:0)[272r,304r:10)[1408r,1424r:9)[1424r,1456r:2)[1872r,1888r:8)[1888r,1920r:7)[3088r,3152r:6)[3152r,3184r:1)[3584r,3600r:5)[4000r,4032r:3)[4128r,4144r:4)  0@0B-phi 1@3152r 2@1424r 3@4000r 4@4128r 5@3584r 6@3088r 7@1888r 8@1872r 9@1408r 10@272r
W1 [0B,80r:0)[288r,304r:3)[3104r,3152r:1)[4016r,4032r:2)  0@0B-phi 1@3104r 2@4016r 3@288r
W2 [0B,64r:0)[3120r,3152r:1)  0@0B-phi 1@3120r
W3 [0B,48r:0)[3136r,3152r:1)  0@0B-phi 1@3136r
W4 [0B,32r:0)  0@0B-phi
%vreg0 [96r,112r:0)  0@96r
%vreg1 [112r,400r:0)  0@112r
%vreg2 [80r,128r:0)  0@80r
%vreg3 [128r,416r:0)  0@128r
%vreg4 [64r,144r:0)  0@64r
%vreg5 [144r,432r:0)  0@144r
%vreg6 [48r,160r:0)  0@48r
%vreg7 [160r,448r:0)  0@160r
%vreg8 [32r,176r:0)  0@32r
%vreg9 [176r,464r:0)  0@176r
%vreg11 [496r,512r:0)  0@496r
%vreg12 [336r,480r:0)  0@336r
%vreg13 [192r,208r:0)  0@192r
%vreg14 [208r,224r:0)  0@208r
%vreg15 [224r,272r:0)  0@224r
%vreg16 [240r,288r:0)  0@240r
%vreg17 [16r,3968r:0)  0@16r
%vreg19 [544r,560r:0)  0@544r
%vreg21 [592r,608r:0)  0@592r
%vreg23 [640r,656r:0)  0@640r
%vreg25 [688r,704r:0)  0@688r
%vreg27 [736r,752r:0)  0@736r
%vreg29 [800r,816r:0)  0@800r
%vreg31 [864r,880r:0)  0@864r
%vreg33 [912r,928r:0)  0@912r
%vreg35 [976r,992r:0)  0@976r
%vreg37 [1024r,1040r:0)  0@1024r
%vreg40 [1456r,1520r:0)  0@1456r
%vreg41 [1376r,1408r:0)  0@1376r
%vreg43 [2016r,2032r:0)  0@2016r
%vreg46 [1984r,2000r:0)  0@1984r
%vreg47 [1840r,1872r:0)  0@1840r
%vreg48 [1920r,1984r:0)  0@1920r
%vreg50 [2352r,2368r:0)  0@2352r
%vreg52 [2400r,2416r:0)  0@2400r
%vreg54 [2448r,2464r:0)  0@2448r
%vreg56 [2496r,2512r:0)  0@2496r
%vreg58 [2880r,2896r:0)  0@2880r
%vreg59 [2544r,2864r:0)  0@2544r
%vreg61 [2848r,2864r:0)  0@2848r
%vreg63 [2816r,2832r:0)  0@2816r
%vreg65 [2784r,2800r:0)  0@2784r
%vreg66 [2560r,2768r:0)  0@2560r
%vreg68 [2736r,2752r:0)  0@2736r
%vreg69 [2752r,2768r:0)  0@2752r
%vreg70 [2720r,2752r:0)  0@2720r
%vreg73 [2688r,2704r:0)  0@2688r
%vreg74 [2672r,2704r:0)  0@2672r
%vreg76 [2640r,2656r:0)  0@2640r
%vreg78 [2592r,2608r:0)  0@2592r
%vreg79 [2608r,2624r:0)  0@2608r
%vreg80 [2576r,2608r:0)  0@2576r
%vreg81 [2928r,2944r:0)  0@2928r
%vreg83 [3264r,3280r:0)  0@3264r
%vreg89 [3184r,3248r:0)  0@3184r
%vreg90 [3056r,3136r:0)  0@3056r
%vreg91 [3040r,3120r:0)  0@3040r
%vreg92 [3024r,3104r:0)  0@3024r
%vreg94 [2992r,3008r:0)  0@2992r
%vreg95 [3008r,3088r:0)  0@3008r
%vreg96 [2976r,3008r:0)  0@2976r
%vreg99 [3872r,3888r:0)  0@3872r
%vreg100 [3856r,3872r:0)  0@3856r
%vreg101 [3744r,3840r:0)  0@3744r
%vreg103 [3808r,3824r:0)  0@3808r
%vreg104 [3824r,3840r:0)  0@3824r
%vreg105 [3792r,3824r:0)  0@3792r
%vreg107 [3760r,3776r:0)  0@3760r
%vreg109 [3312r,3328r:0)  0@3312r
%vreg112 [3376r,3392r:0)  0@3376r
%vreg113 [3360r,3392r:0)  0@3360r
%vreg115 [3424r,3440r:0)  0@3424r
%vreg118 [3488r,3504r:0)  0@3488r
%vreg119 [3472r,3504r:0)  0@3472r
%vreg120 [3632r,3696r:0)  0@3632r
%vreg123 [3552r,3584r:0)  0@3552r
%vreg124 [3536r,3552r:0)  0@3536r
%vreg126 [2064r,2080r:0)  0@2064r
%vreg127 [2112r,2144r:0)  0@2112r
%vreg129 [2128r,2144r:0)  0@2128r
%vreg131 [2176r,2192r:0)  0@2176r
%vreg132 [2224r,2256r:0)  0@2224r
%vreg134 [2240r,2256r:0)  0@2240r
%vreg135 [2288r,2304r:0)  0@2288r
%vreg137 [1552r,1568r:0)  0@1552r
%vreg138 [1600r,1632r:0)  0@1600r
%vreg140 [1616r,1632r:0)  0@1616r
%vreg142 [1664r,1680r:0)  0@1664r
%vreg143 [1712r,1744r:0)  0@1712r
%vreg145 [1728r,1744r:0)  0@1728r
%vreg146 [1776r,1792r:0)  0@1776r
%vreg148 [1088r,1104r:0)  0@1088r
%vreg149 [1136r,1168r:0)  0@1136r
%vreg151 [1152r,1168r:0)  0@1152r
%vreg153 [1200r,1216r:0)  0@1200r
%vreg154 [1248r,1280r:0)  0@1248r
%vreg156 [1264r,1280r:0)  0@1264r
%vreg157 [1312r,1328r:0)  0@1312r
%vreg159 [4112r,4128r:0)  0@4112r
%vreg160 [3920r,3936r:0)  0@3920r
%vreg161 [3936r,3952r:0)  0@3936r
%vreg162 [3952r,4000r:0)  0@3952r
%vreg163 [3968r,4016r:0)  0@3968r
RegMasks: 304r 1424r 1888r 3152r 3600r 4032r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzWriteOpen: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=8, align=8, at location [SP]
  fi#3: size=4, align=4, at location [SP]
  fi#4: size=4, align=4, at location [SP]
  fi#5: size=4, align=4, at location [SP]
  fi#6: size=4, align=4, at location [SP]
  fi#7: size=8, align=8, at location [SP]
Function Live Ins: %X0 in %vreg0, %X1 in %vreg2, %W2 in %vreg4, %W3 in %vreg6, %W4 in %vreg8, %LR in %vreg17

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %X1 %W2 %W3 %W4 %LR
16B		%vreg17<def> = COPY %LR; GPR64:%vreg17
32B		%vreg8<def> = COPY %W4; GPR32:%vreg8
48B		%vreg6<def> = COPY %W3; GPR32:%vreg6
64B		%vreg4<def> = COPY %W2; GPR32:%vreg4
80B		%vreg2<def> = COPY %X1; GPR64:%vreg2
96B		%vreg0<def> = COPY %X0; GPR64:%vreg0
112B		%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
128B		%vreg3<def> = COPY %vreg2; GPR64:%vreg3,%vreg2
144B		%vreg5<def> = COPY %vreg4; GPR32:%vreg5,%vreg4
160B		%vreg7<def> = COPY %vreg6; GPR32:%vreg7,%vreg6
176B		%vreg9<def> = COPY %vreg8; GPR32:%vreg9,%vreg8
192B		%vreg13<def> = ADRP <ga:@BZ2_bzWriteOpen>[TF=1]; GPR64common:%vreg13
208B		%vreg14<def> = ADDXri %vreg13, <ga:@BZ2_bzWriteOpen>[TF=34], 0; GPR64sp:%vreg14 GPR64common:%vreg13
224B		%vreg15<def> = COPY %vreg14; GPR64all:%vreg15 GPR64sp:%vreg14
240B		%vreg16<def> = COPY %vreg17; GPR64all:%vreg16 GPR64:%vreg17
256B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
272B		%X0<def> = COPY %vreg15; GPR64all:%vreg15
288B		%X1<def> = COPY %vreg16; GPR64all:%vreg16
304B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
320B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
336B		%vreg12<def> = COPY %XZR; GPR64:%vreg12
352B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
368B		STACKMAP 0, 0, %vreg5, 0, <fi#3>, 0, %vreg1, 0, <fi#1>, 0, 0, <fi#7>, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, %vreg7, 0, <fi#4>, 0, %vreg9, 0, <fi#5>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) GPR32:%vreg5,%vreg7,%vreg9 GPR64:%vreg1,%vreg3
384B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
400B		STRXui %vreg1, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg1
416B		STRXui %vreg3, <fi#2>, 0; mem:ST8[FixedStack2] GPR64:%vreg3
432B		STRWui %vreg5, <fi#3>, 0; mem:ST4[FixedStack3] GPR32:%vreg5
448B		STRWui %vreg7, <fi#4>, 0; mem:ST4[FixedStack4] GPR32:%vreg7
464B		STRWui %vreg9, <fi#5>, 0; mem:ST4[FixedStack5] GPR32:%vreg9
480B		STRXui %vreg12, <fi#7>, 0; mem:ST8[FixedStack7] GPR64:%vreg12
496B		%vreg11<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg11
512B		CBZX %vreg11, <BB#2>; GPR64:%vreg11
	    Successors according to CFG: BB#2 BB#1

528B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
544B		%vreg19<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg19
560B		STRWui %WZR, %vreg19, 0; mem:ST4[%1] GPR64common:%vreg19
	    Successors according to CFG: BB#2

576B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#1
592B		%vreg21<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg21
608B		CBZX %vreg21, <BB#4>; GPR64:%vreg21
	    Successors according to CFG: BB#4 BB#3

624B	BB#3: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#2
640B		%vreg23<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg23
656B		STRWui %WZR, %vreg23, 1274; mem:ST4[%lastErr] GPR64common:%vreg23
	    Successors according to CFG: BB#4

672B	BB#4: derived from LLVM BB %if.end.3
	    Predecessors according to CFG: BB#2 BB#3
688B		%vreg25<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg25
704B		CBZX %vreg25, <BB#11>; GPR64:%vreg25
	    Successors according to CFG: BB#11 BB#5

720B	BB#5: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#4
736B		%vreg27<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32common:%vreg27
752B		%WZR<def> = SUBSWri %vreg27, 1, 0, %NZCV<imp-def>; GPR32common:%vreg27
768B		Bcc 11, <BB#11>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#11 BB#6

784B	BB#6: derived from LLVM BB %lor.lhs.false.6
	    Predecessors according to CFG: BB#5
800B		%vreg29<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32common:%vreg29
816B		%WZR<def> = SUBSWri %vreg29, 9, 0, %NZCV<imp-def>; GPR32common:%vreg29
832B		Bcc 12, <BB#11>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#11 BB#7

848B	BB#7: derived from LLVM BB %lor.lhs.false.8
	    Predecessors according to CFG: BB#6
864B		%vreg31<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32:%vreg31
880B		TBNZW %vreg31, 31, <BB#11>; GPR32:%vreg31
	    Successors according to CFG: BB#11 BB#8

896B	BB#8: derived from LLVM BB %lor.lhs.false.10
	    Predecessors according to CFG: BB#7
912B		%vreg33<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32common:%vreg33
928B		%WZR<def> = SUBSWri %vreg33, 250, 0, %NZCV<imp-def>; GPR32common:%vreg33
944B		Bcc 12, <BB#11>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#11 BB#9

960B	BB#9: derived from LLVM BB %lor.lhs.false.12
	    Predecessors according to CFG: BB#8
976B		%vreg35<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg35
992B		TBNZW %vreg35, 31, <BB#11>; GPR32:%vreg35
	    Successors according to CFG: BB#11 BB#10

1008B	BB#10: derived from LLVM BB %lor.lhs.false.14
	    Predecessors according to CFG: BB#9
1024B		%vreg37<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32common:%vreg37
1040B		%WZR<def> = SUBSWri %vreg37, 4, 0, %NZCV<imp-def>; GPR32common:%vreg37
1056B		Bcc 13, <BB#16>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#16 BB#11

1072B	BB#11: derived from LLVM BB %if.then.16
	    Predecessors according to CFG: BB#4 BB#5 BB#6 BB#7 BB#8 BB#9 BB#10
1088B		%vreg148<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg148
1104B		CBZX %vreg148, <BB#13>; GPR64:%vreg148
	    Successors according to CFG: BB#13 BB#12

1120B	BB#12: derived from LLVM BB %if.then.18
	    Predecessors according to CFG: BB#11
1136B		%vreg149<def> = MOVi32imm 4294967294; GPR32:%vreg149
1152B		%vreg151<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg151
1168B		STRWui %vreg149, %vreg151, 0; mem:ST4[%12] GPR32:%vreg149 GPR64common:%vreg151
	    Successors according to CFG: BB#13

1184B	BB#13: derived from LLVM BB %if.end.19
	    Predecessors according to CFG: BB#11 BB#12
1200B		%vreg153<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg153
1216B		CBZX %vreg153, <BB#15>; GPR64:%vreg153
	    Successors according to CFG: BB#15 BB#14

1232B	BB#14: derived from LLVM BB %if.then.21
	    Predecessors according to CFG: BB#13
1248B		%vreg154<def> = MOVi32imm 4294967294; GPR32:%vreg154
1264B		%vreg156<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg156
1280B		STRWui %vreg154, %vreg156, 1274; mem:ST4[%lastErr22] GPR32:%vreg154 GPR64common:%vreg156
	    Successors according to CFG: BB#15

1296B	BB#15: derived from LLVM BB %if.end.23
	    Predecessors according to CFG: BB#13 BB#14
1312B		%vreg157<def> = COPY %XZR; GPR64:%vreg157
1328B		STRXui %vreg157, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg157
1344B		B <BB#41>
	    Successors according to CFG: BB#41

1360B	BB#16: derived from LLVM BB %if.end.24
	    Predecessors according to CFG: BB#10
1376B		%vreg41<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg41
1392B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1408B		%X0<def> = COPY %vreg41; GPR64:%vreg41
1424B		BL <ga:@ferror>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
1440B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1456B		%vreg40<def> = COPY %W0; GPR32:%vreg40
1472B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1488B		STACKMAP 1, 0, 0, <fi#3>, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#2>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4)
1504B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1520B		CBZW %vreg40, <BB#22>; GPR32:%vreg40
	    Successors according to CFG: BB#22 BB#17

1536B	BB#17: derived from LLVM BB %if.then.25
	    Predecessors according to CFG: BB#16
1552B		%vreg137<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg137
1568B		CBZX %vreg137, <BB#19>; GPR64:%vreg137
	    Successors according to CFG: BB#19 BB#18

1584B	BB#18: derived from LLVM BB %if.then.27
	    Predecessors according to CFG: BB#17
1600B		%vreg138<def> = MOVi32imm 4294967290; GPR32:%vreg138
1616B		%vreg140<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg140
1632B		STRWui %vreg138, %vreg140, 0; mem:ST4[%17] GPR32:%vreg138 GPR64common:%vreg140
	    Successors according to CFG: BB#19

1648B	BB#19: derived from LLVM BB %if.end.28
	    Predecessors according to CFG: BB#17 BB#18
1664B		%vreg142<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg142
1680B		CBZX %vreg142, <BB#21>; GPR64:%vreg142
	    Successors according to CFG: BB#21 BB#20

1696B	BB#20: derived from LLVM BB %if.then.30
	    Predecessors according to CFG: BB#19
1712B		%vreg143<def> = MOVi32imm 4294967290; GPR32:%vreg143
1728B		%vreg145<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg145
1744B		STRWui %vreg143, %vreg145, 1274; mem:ST4[%lastErr31] GPR32:%vreg143 GPR64common:%vreg145
	    Successors according to CFG: BB#21

1760B	BB#21: derived from LLVM BB %if.end.32
	    Predecessors according to CFG: BB#19 BB#20
1776B		%vreg146<def> = COPY %XZR; GPR64:%vreg146
1792B		STRXui %vreg146, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg146
1808B		B <BB#41>
	    Successors according to CFG: BB#41

1824B	BB#22: derived from LLVM BB %if.end.33
	    Predecessors according to CFG: BB#16
1840B		%vreg47<def> = MOVi64imm 5104; GPR64:%vreg47
1856B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1872B		%X0<def> = COPY %vreg47; GPR64:%vreg47
1888B		BL <ga:@malloc>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X0<imp-def>
1904B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1920B		%vreg48<def> = COPY %X0; GPR64all:%vreg48
1936B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1952B		STACKMAP 2, 0, 0, <fi#3>, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#2>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4)
1968B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1984B		%vreg46<def> = COPY %vreg48; GPR64:%vreg46 GPR64all:%vreg48
2000B		STRXui %vreg46, <fi#7>, 0; mem:ST8[FixedStack7] GPR64:%vreg46
2016B		%vreg43<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg43
2032B		CBNZX %vreg43, <BB#28>; GPR64:%vreg43
	    Successors according to CFG: BB#28 BB#23

2048B	BB#23: derived from LLVM BB %if.then.36
	    Predecessors according to CFG: BB#22
2064B		%vreg126<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg126
2080B		CBZX %vreg126, <BB#25>; GPR64:%vreg126
	    Successors according to CFG: BB#25 BB#24

2096B	BB#24: derived from LLVM BB %if.then.38
	    Predecessors according to CFG: BB#23
2112B		%vreg127<def> = MOVi32imm 4294967293; GPR32:%vreg127
2128B		%vreg129<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg129
2144B		STRWui %vreg127, %vreg129, 0; mem:ST4[%23] GPR32:%vreg127 GPR64common:%vreg129
	    Successors according to CFG: BB#25

2160B	BB#25: derived from LLVM BB %if.end.39
	    Predecessors according to CFG: BB#23 BB#24
2176B		%vreg131<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg131
2192B		CBZX %vreg131, <BB#27>; GPR64:%vreg131
	    Successors according to CFG: BB#27 BB#26

2208B	BB#26: derived from LLVM BB %if.then.41
	    Predecessors according to CFG: BB#25
2224B		%vreg132<def> = MOVi32imm 4294967293; GPR32:%vreg132
2240B		%vreg134<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg134
2256B		STRWui %vreg132, %vreg134, 1274; mem:ST4[%lastErr42] GPR32:%vreg132 GPR64common:%vreg134
	    Successors according to CFG: BB#27

2272B	BB#27: derived from LLVM BB %if.end.43
	    Predecessors according to CFG: BB#25 BB#26
2288B		%vreg135<def> = COPY %XZR; GPR64:%vreg135
2304B		STRXui %vreg135, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg135
2320B		B <BB#41>
	    Successors according to CFG: BB#41

2336B	BB#28: derived from LLVM BB %if.end.44
	    Predecessors according to CFG: BB#22
2352B		%vreg50<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg50
2368B		CBZX %vreg50, <BB#30>; GPR64:%vreg50
	    Successors according to CFG: BB#30 BB#29

2384B	BB#29: derived from LLVM BB %if.then.46
	    Predecessors according to CFG: BB#28
2400B		%vreg52<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg52
2416B		STRWui %WZR, %vreg52, 0; mem:ST4[%27] GPR64common:%vreg52
	    Successors according to CFG: BB#30

2432B	BB#30: derived from LLVM BB %if.end.47
	    Predecessors according to CFG: BB#28 BB#29
2448B		%vreg54<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg54
2464B		CBZX %vreg54, <BB#32>; GPR64:%vreg54
	    Successors according to CFG: BB#32 BB#31

2480B	BB#31: derived from LLVM BB %if.then.49
	    Predecessors according to CFG: BB#30
2496B		%vreg56<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg56
2512B		STRWui %WZR, %vreg56, 1274; mem:ST4[%lastErr50] GPR64common:%vreg56
	    Successors according to CFG: BB#32

2528B	BB#32: derived from LLVM BB %if.end.51
	    Predecessors according to CFG: BB#30 BB#31
2544B		%vreg59<def> = COPY %XZR; GPR64:%vreg59
2560B		%vreg66<def> = MOVi32imm 1; GPR32:%vreg66
2576B		%vreg80<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg80
2592B		%vreg78<def> = MOVi64imm 5100; GPR64:%vreg78
2608B		%vreg79<def> = ADDXrr %vreg80, %vreg78; GPR64common:%vreg79 GPR64:%vreg80,%vreg78
2624B		STRBBui %WZR, %vreg79, 0; mem:ST1[%initialisedOk] GPR64common:%vreg79
2640B		%vreg76<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg76
2656B		STRWui %WZR, %vreg76, 1252; mem:ST4[%bufN] GPR64common:%vreg76
2672B		%vreg74<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg74
2688B		%vreg73<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg73
2704B		STRXui %vreg74, %vreg73, 0; mem:ST8[%handle] GPR64:%vreg74 GPR64common:%vreg73
2720B		%vreg70<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg70
2736B		%vreg68<def> = MOVi64imm 5012; GPR64:%vreg68
2752B		%vreg69<def> = ADDXrr %vreg70, %vreg68; GPR64common:%vreg69 GPR64:%vreg70,%vreg68
2768B		STRBBui %vreg66, %vreg69, 0; mem:ST1[%writing] GPR32:%vreg66 GPR64common:%vreg69
2784B		%vreg65<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg65
2800B		STRXui %vreg59, %vreg65, 634; mem:ST8[%bzalloc] GPR64:%vreg59 GPR64common:%vreg65
2816B		%vreg63<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg63
2832B		STRXui %vreg59, %vreg63, 635; mem:ST8[%bzfree] GPR64:%vreg59 GPR64common:%vreg63
2848B		%vreg61<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg61
2864B		STRXui %vreg59, %vreg61, 636; mem:ST8[%opaque] GPR64:%vreg59 GPR64common:%vreg61
2880B		%vreg58<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32:%vreg58
2896B		CBNZW %vreg58, <BB#34>; GPR32:%vreg58
	    Successors according to CFG: BB#34 BB#33

2912B	BB#33: derived from LLVM BB %if.then.55
	    Predecessors according to CFG: BB#32
2928B		%vreg81<def> = MOVi32imm 30; GPR32:%vreg81
2944B		STRWui %vreg81, <fi#5>, 0; mem:ST4[FixedStack5] GPR32:%vreg81
	    Successors according to CFG: BB#34

2960B	BB#34: derived from LLVM BB %if.end.56
	    Predecessors according to CFG: BB#32 BB#33
2976B		%vreg96<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg96
2992B		%vreg94<def> = MOVi64imm 5016; GPR64:%vreg94
3008B		%vreg95<def> = ADDXrr %vreg96, %vreg94; GPR64:%vreg95,%vreg96,%vreg94
3024B		%vreg92<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg92
3040B		%vreg91<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg91
3056B		%vreg90<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32:%vreg90
3072B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3088B		%X0<def> = COPY %vreg95; GPR64:%vreg95
3104B		%W1<def> = COPY %vreg92; GPR32:%vreg92
3120B		%W2<def> = COPY %vreg91; GPR32:%vreg91
3136B		%W3<def> = COPY %vreg90; GPR32:%vreg90
3152B		BL <ga:@BZ2_bzCompressInit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %W2<imp-use>, %W3<imp-use>, %W0<imp-def>
3168B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3184B		%vreg89<def> = COPY %W0; GPR32:%vreg89
3200B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3216B		STACKMAP 3, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack6](align=4) LD8[FixedStack0]
3232B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3248B		STRWui %vreg89, <fi#6>, 0; mem:ST4[FixedStack6] GPR32:%vreg89
3264B		%vreg83<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg83
3280B		CBZW %vreg83, <BB#40>; GPR32:%vreg83
	    Successors according to CFG: BB#40 BB#35

3296B	BB#35: derived from LLVM BB %if.then.60
	    Predecessors according to CFG: BB#34
3312B		%vreg109<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg109
3328B		CBZX %vreg109, <BB#37>; GPR64:%vreg109
	    Successors according to CFG: BB#37 BB#36

3344B	BB#36: derived from LLVM BB %if.then.62
	    Predecessors according to CFG: BB#35
3360B		%vreg113<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg113
3376B		%vreg112<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg112
3392B		STRWui %vreg113, %vreg112, 0; mem:ST4[%46] GPR32:%vreg113 GPR64common:%vreg112
	    Successors according to CFG: BB#37

3408B	BB#37: derived from LLVM BB %if.end.63
	    Predecessors according to CFG: BB#35 BB#36
3424B		%vreg115<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg115
3440B		CBZX %vreg115, <BB#39>; GPR64:%vreg115
	    Successors according to CFG: BB#39 BB#38

3456B	BB#38: derived from LLVM BB %if.then.65
	    Predecessors according to CFG: BB#37
3472B		%vreg119<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg119
3488B		%vreg118<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg118
3504B		STRWui %vreg119, %vreg118, 1274; mem:ST4[%lastErr66] GPR32:%vreg119 GPR64common:%vreg118
	    Successors according to CFG: BB#39

3520B	BB#39: derived from LLVM BB %if.end.67
	    Predecessors according to CFG: BB#37 BB#38
3536B		%vreg124<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg124
3552B		%vreg123<def> = COPY %vreg124; GPR64all:%vreg123 GPR64:%vreg124
3568B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3584B		%X0<def> = COPY %vreg123; GPR64all:%vreg123
3600B		BL <ga:@free>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>
3616B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3632B		%vreg120<def> = COPY %XZR; GPR64:%vreg120
3648B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3664B		STACKMAP 4, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0]
3680B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3696B		STRXui %vreg120, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg120
3712B		B <BB#41>
	    Successors according to CFG: BB#41

3728B	BB#40: derived from LLVM BB %if.end.68
	    Predecessors according to CFG: BB#34
3744B		%vreg101<def> = MOVi32imm 1; GPR32:%vreg101
3760B		%vreg107<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg107
3776B		STRWui %WZR, %vreg107, 1256; mem:ST4[%avail_in] GPR64common:%vreg107
3792B		%vreg105<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg105
3808B		%vreg103<def> = MOVi64imm 5100; GPR64:%vreg103
3824B		%vreg104<def> = ADDXrr %vreg105, %vreg103; GPR64common:%vreg104 GPR64:%vreg105,%vreg103
3840B		STRBBui %vreg101, %vreg104, 0; mem:ST1[%initialisedOk70] GPR32:%vreg101 GPR64common:%vreg104
3856B		%vreg100<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg100
3872B		%vreg99<def> = COPY %vreg100; GPR64:%vreg99,%vreg100
3888B		STRXui %vreg99, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg99
	    Successors according to CFG: BB#41

3904B	BB#41: derived from LLVM BB %return
	    Predecessors according to CFG: BB#40 BB#39 BB#27 BB#21 BB#15
3920B		%vreg160<def> = ADRP <ga:@BZ2_bzWriteOpen>[TF=1]; GPR64common:%vreg160
3936B		%vreg161<def> = ADDXri %vreg160, <ga:@BZ2_bzWriteOpen>[TF=34], 0; GPR64sp:%vreg161 GPR64common:%vreg160
3952B		%vreg162<def> = COPY %vreg161; GPR64all:%vreg162 GPR64sp:%vreg161
3968B		%vreg163<def> = COPY %vreg17; GPR64all:%vreg163 GPR64:%vreg17
3984B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4000B		%X0<def> = COPY %vreg162; GPR64all:%vreg162
4016B		%X1<def> = COPY %vreg163; GPR64all:%vreg163
4032B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
4048B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4064B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4080B		STACKMAP 5, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0]
4096B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4112B		%vreg159<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg159
4128B		%X0<def> = COPY %vreg159; GPR64:%vreg159
4144B		RET_ReallyLR %X0<imp-use>

# End machine code for function BZ2_bzWriteOpen.

********** SIMPLE REGISTER COALESCING **********
********** Function: BZ2_bzWriteOpen
********** JOINING INTERVALS ***********
if.then.16:
return:
4000B	%X0<def> = COPY %vreg162; GPR64all:%vreg162
	Considering merging %vreg162 with %X0
	Can only merge into reserved registers.
4016B	%X1<def> = COPY %vreg163; GPR64all:%vreg163
	Considering merging %vreg163 with %X1
	Can only merge into reserved registers.
4128B	%X0<def> = COPY %vreg159; GPR64:%vreg159
	Considering merging %vreg159 with %X0
	Can only merge into reserved registers.
if.end:
if.end.3:
if.end.19:
if.end.28:
if.end.39:
if.end.47:
if.end.51:
2544B	%vreg59<def> = COPY %XZR; GPR64:%vreg59
	Considering merging %vreg59 with %XZR
		RHS = %vreg59 [2544r,2864r:0)  0@2544r
		updated: 2864B	STRXui %XZR, %vreg61, 636; mem:ST8[%opaque] GPR64common:%vreg61
		updated: 2832B	STRXui %XZR, %vreg63, 635; mem:ST8[%bzfree] GPR64common:%vreg63
		updated: 2800B	STRXui %XZR, %vreg65, 634; mem:ST8[%bzalloc] GPR64common:%vreg65
	Success: %vreg59 -> %XZR
	Result = %XZR
if.end.56:
3088B	%X0<def> = COPY %vreg95; GPR64:%vreg95
	Considering merging %vreg95 with %X0
	Can only merge into reserved registers.
3104B	%W1<def> = COPY %vreg92; GPR32:%vreg92
	Considering merging %vreg92 with %W1
	Can only merge into reserved registers.
3120B	%W2<def> = COPY %vreg91; GPR32:%vreg91
	Considering merging %vreg91 with %W2
	Can only merge into reserved registers.
3136B	%W3<def> = COPY %vreg90; GPR32:%vreg90
	Considering merging %vreg90 with %W3
	Can only merge into reserved registers.
3184B	%vreg89<def> = COPY %W0; GPR32:%vreg89
	Considering merging %vreg89 with %W0
	Can only merge into reserved registers.
if.end.63:
lor.lhs.false:
lor.lhs.false.6:
lor.lhs.false.8:
lor.lhs.false.10:
lor.lhs.false.12:
lor.lhs.false.14:
if.end.23:
1312B	%vreg157<def> = COPY %XZR; GPR64:%vreg157
	Considering merging %vreg157 with %XZR
		RHS = %vreg157 [1312r,1328r:0)  0@1312r
		updated: 1328B	STRXui %XZR, <fi#0>, 0; mem:ST8[FixedStack0]
	Success: %vreg157 -> %XZR
	Result = %XZR
if.end.24:
1408B	%X0<def> = COPY %vreg41; GPR64:%vreg41
	Considering merging %vreg41 with %X0
	Can only merge into reserved registers.
1456B	%vreg40<def> = COPY %W0; GPR32:%vreg40
	Considering merging %vreg40 with %W0
	Can only merge into reserved registers.
if.then.25:
if.end.32:
1776B	%vreg146<def> = COPY %XZR; GPR64:%vreg146
	Considering merging %vreg146 with %XZR
		RHS = %vreg146 [1776r,1792r:0)  0@1776r
		updated: 1792B	STRXui %XZR, <fi#0>, 0; mem:ST8[FixedStack0]
	Success: %vreg146 -> %XZR
	Result = %XZR
if.end.33:
1872B	%X0<def> = COPY %vreg47; GPR64:%vreg47
	Considering merging %vreg47 with %X0
	Can only merge into reserved registers.
Remat: %X0<def> = MOVi64imm 5104
Shrink: %vreg47 [1840r,1872r:0)  0@1840r
All defs dead: 1840r	%vreg47<def,dead> = MOVi64imm 5104; GPR64:%vreg47
Shrunk: %vreg47 [1840r,1840d:0)  0@1840r
Deleting dead def 1840r	%vreg47<def,dead> = MOVi64imm 5104; GPR64:%vreg47
1920B	%vreg48<def> = COPY %X0; GPR64all:%vreg48
	Considering merging %vreg48 with %X0
	Can only merge into reserved registers.
if.then.36:
if.end.43:
2288B	%vreg135<def> = COPY %XZR; GPR64:%vreg135
	Considering merging %vreg135 with %XZR
		RHS = %vreg135 [2288r,2304r:0)  0@2288r
		updated: 2304B	STRXui %XZR, <fi#0>, 0; mem:ST8[FixedStack0]
	Success: %vreg135 -> %XZR
	Result = %XZR
if.end.44:
if.then.60:
if.end.67:
3584B	%X0<def> = COPY %vreg123; GPR64all:%vreg123
	Considering merging %vreg123 with %X0
	Can only merge into reserved registers.
3632B	%vreg120<def> = COPY %XZR; GPR64:%vreg120
	Considering merging %vreg120 with %XZR
		RHS = %vreg120 [3632r,3696r:0)  0@3632r
		updated: 3696B	STRXui %XZR, <fi#0>, 0; mem:ST8[FixedStack0]
	Success: %vreg120 -> %XZR
	Result = %XZR
entry:
16B	%vreg17<def> = COPY %LR; GPR64:%vreg17
	Considering merging %vreg17 with %LR
	Can only merge into reserved registers.
32B	%vreg8<def> = COPY %W4; GPR32:%vreg8
	Considering merging %vreg8 with %W4
	Can only merge into reserved registers.
48B	%vreg6<def> = COPY %W3; GPR32:%vreg6
	Considering merging %vreg6 with %W3
	Can only merge into reserved registers.
64B	%vreg4<def> = COPY %W2; GPR32:%vreg4
	Considering merging %vreg4 with %W2
	Can only merge into reserved registers.
80B	%vreg2<def> = COPY %X1; GPR64:%vreg2
	Considering merging %vreg2 with %X1
	Can only merge into reserved registers.
96B	%vreg0<def> = COPY %X0; GPR64:%vreg0
	Considering merging %vreg0 with %X0
	Can only merge into reserved registers.
272B	%X0<def> = COPY %vreg15; GPR64all:%vreg15
	Considering merging %vreg15 with %X0
	Can only merge into reserved registers.
288B	%X1<def> = COPY %vreg16; GPR64all:%vreg16
	Considering merging %vreg16 with %X1
	Can only merge into reserved registers.
336B	%vreg12<def> = COPY %XZR; GPR64:%vreg12
	Considering merging %vreg12 with %XZR
		RHS = %vreg12 [336r,480r:0)  0@336r
		updated: 480B	STRXui %XZR, <fi#7>, 0; mem:ST8[FixedStack7]
	Success: %vreg12 -> %XZR
	Result = %XZR
if.then:
if.then.2:
if.then.18:
if.then.21:
if.then.27:
if.then.30:
if.then.38:
if.then.41:
if.then.46:
if.then.49:
if.then.55:
if.then.62:
if.then.65:
if.end.68:
3952B	%vreg162<def> = COPY %vreg161; GPR64all:%vreg162 GPR64sp:%vreg161
	Considering merging to GPR64sp with %vreg161 in %vreg162
		RHS = %vreg161 [3936r,3952r:0)  0@3936r
		LHS = %vreg162 [3952r,4000r:0)  0@3952r
		merge %vreg162:0@3952r into %vreg161:0@3936r --> @3936r
		erased:	3952r	%vreg162<def> = COPY %vreg161; GPR64all:%vreg162 GPR64sp:%vreg161
		updated: 3936B	%vreg162<def> = ADDXri %vreg160, <ga:@BZ2_bzWriteOpen>[TF=34], 0; GPR64sp:%vreg162 GPR64common:%vreg160
	Success: %vreg161 -> %vreg162
	Result = %vreg162 [3936r,4000r:0)  0@3936r
3968B	%vreg163<def> = COPY %vreg17; GPR64all:%vreg163 GPR64:%vreg17
	Considering merging to GPR64 with %vreg17 in %vreg163
		RHS = %vreg17 [16r,3968r:0)  0@16r
		LHS = %vreg163 [3968r,4016r:0)  0@3968r
		merge %vreg163:0@3968r into %vreg17:0@16r --> @16r
		erased:	3968r	%vreg163<def> = COPY %vreg17; GPR64all:%vreg163 GPR64:%vreg17
		updated: 16B	%vreg163<def> = COPY %LR; GPR64:%vreg163
		updated: 240B	%vreg16<def> = COPY %vreg163; GPR64all:%vreg16 GPR64:%vreg163
	Success: %vreg17 -> %vreg163
	Result = %vreg163 [16r,4016r:0)  0@16r
1984B	%vreg46<def> = COPY %vreg48; GPR64:%vreg46 GPR64all:%vreg48
	Considering merging to GPR64 with %vreg48 in %vreg46
		RHS = %vreg48 [1920r,1984r:0)  0@1920r
		LHS = %vreg46 [1984r,2000r:0)  0@1984r
		merge %vreg46:0@1984r into %vreg48:0@1920r --> @1920r
		erased:	1984r	%vreg46<def> = COPY %vreg48; GPR64:%vreg46 GPR64all:%vreg48
		updated: 1920B	%vreg46<def> = COPY %X0; GPR64:%vreg46
	Success: %vreg48 -> %vreg46
	Result = %vreg46 [1920r,2000r:0)  0@1920r
3552B	%vreg123<def> = COPY %vreg124; GPR64all:%vreg123 GPR64:%vreg124
	Considering merging to GPR64 with %vreg124 in %vreg123
		RHS = %vreg124 [3536r,3552r:0)  0@3536r
		LHS = %vreg123 [3552r,3584r:0)  0@3552r
		merge %vreg123:0@3552r into %vreg124:0@3536r --> @3536r
		erased:	3552r	%vreg123<def> = COPY %vreg124; GPR64all:%vreg123 GPR64:%vreg124
		updated: 3536B	%vreg123<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg123
	Success: %vreg124 -> %vreg123
	Result = %vreg123 [3536r,3584r:0)  0@3536r
112B	%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
	Considering merging to GPR64 with %vreg0 in %vreg1
		RHS = %vreg0 [96r,112r:0)  0@96r
		LHS = %vreg1 [112r,400r:0)  0@112r
		merge %vreg1:0@112r into %vreg0:0@96r --> @96r
		erased:	112r	%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
		updated: 96B	%vreg1<def> = COPY %X0; GPR64:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [96r,400r:0)  0@96r
128B	%vreg3<def> = COPY %vreg2; GPR64:%vreg3,%vreg2
	Considering merging to GPR64 with %vreg2 in %vreg3
		RHS = %vreg2 [80r,128r:0)  0@80r
		LHS = %vreg3 [128r,416r:0)  0@128r
		merge %vreg3:0@128r into %vreg2:0@80r --> @80r
		erased:	128r	%vreg3<def> = COPY %vreg2; GPR64:%vreg3,%vreg2
		updated: 80B	%vreg3<def> = COPY %X1; GPR64:%vreg3
	Success: %vreg2 -> %vreg3
	Result = %vreg3 [80r,416r:0)  0@80r
144B	%vreg5<def> = COPY %vreg4; GPR32:%vreg5,%vreg4
	Considering merging to GPR32 with %vreg4 in %vreg5
		RHS = %vreg4 [64r,144r:0)  0@64r
		LHS = %vreg5 [144r,432r:0)  0@144r
		merge %vreg5:0@144r into %vreg4:0@64r --> @64r
		erased:	144r	%vreg5<def> = COPY %vreg4; GPR32:%vreg5,%vreg4
		updated: 64B	%vreg5<def> = COPY %W2; GPR32:%vreg5
	Success: %vreg4 -> %vreg5
	Result = %vreg5 [64r,432r:0)  0@64r
160B	%vreg7<def> = COPY %vreg6; GPR32:%vreg7,%vreg6
	Considering merging to GPR32 with %vreg6 in %vreg7
		RHS = %vreg6 [48r,160r:0)  0@48r
		LHS = %vreg7 [160r,448r:0)  0@160r
		merge %vreg7:0@160r into %vreg6:0@48r --> @48r
		erased:	160r	%vreg7<def> = COPY %vreg6; GPR32:%vreg7,%vreg6
		updated: 48B	%vreg7<def> = COPY %W3; GPR32:%vreg7
	Success: %vreg6 -> %vreg7
	Result = %vreg7 [48r,448r:0)  0@48r
176B	%vreg9<def> = COPY %vreg8; GPR32:%vreg9,%vreg8
	Considering merging to GPR32 with %vreg8 in %vreg9
		RHS = %vreg8 [32r,176r:0)  0@32r
		LHS = %vreg9 [176r,464r:0)  0@176r
		merge %vreg9:0@176r into %vreg8:0@32r --> @32r
		erased:	176r	%vreg9<def> = COPY %vreg8; GPR32:%vreg9,%vreg8
		updated: 32B	%vreg9<def> = COPY %W4; GPR32:%vreg9
	Success: %vreg8 -> %vreg9
	Result = %vreg9 [32r,464r:0)  0@32r
224B	%vreg15<def> = COPY %vreg14; GPR64all:%vreg15 GPR64sp:%vreg14
	Considering merging to GPR64sp with %vreg14 in %vreg15
		RHS = %vreg14 [208r,224r:0)  0@208r
		LHS = %vreg15 [224r,272r:0)  0@224r
		merge %vreg15:0@224r into %vreg14:0@208r --> @208r
		erased:	224r	%vreg15<def> = COPY %vreg14; GPR64all:%vreg15 GPR64sp:%vreg14
		updated: 208B	%vreg15<def> = ADDXri %vreg13, <ga:@BZ2_bzWriteOpen>[TF=34], 0; GPR64sp:%vreg15 GPR64common:%vreg13
	Success: %vreg14 -> %vreg15
	Result = %vreg15 [208r,272r:0)  0@208r
240B	%vreg16<def> = COPY %vreg163; GPR64all:%vreg16 GPR64:%vreg163
	Considering merging to GPR64 with %vreg163 in %vreg16
		RHS = %vreg163 [16r,4016r:0)  0@16r
		LHS = %vreg16 [240r,288r:0)  0@240r
		merge %vreg16:0@240r into %vreg163:0@16r --> @16r
		erased:	240r	%vreg16<def> = COPY %vreg163; GPR64all:%vreg16 GPR64:%vreg163
		updated: 16B	%vreg16<def> = COPY %LR; GPR64:%vreg16
		updated: 4016B	%X1<def> = COPY %vreg16; GPR64:%vreg16
	Success: %vreg163 -> %vreg16
	Result = %vreg16 [16r,4016r:0)  0@16r
3872B	%vreg99<def> = COPY %vreg100; GPR64:%vreg99,%vreg100
	Considering merging to GPR64 with %vreg100 in %vreg99
		RHS = %vreg100 [3856r,3872r:0)  0@3856r
		LHS = %vreg99 [3872r,3888r:0)  0@3872r
		merge %vreg99:0@3872r into %vreg100:0@3856r --> @3856r
		erased:	3872r	%vreg99<def> = COPY %vreg100; GPR64:%vreg99,%vreg100
		updated: 3856B	%vreg99<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg99
	Success: %vreg100 -> %vreg99
	Result = %vreg99 [3856r,3888r:0)  0@3856r
4000B	%X0<def> = COPY %vreg162; GPR64sp:%vreg162
	Considering merging %vreg162 with %X0
	Can only merge into reserved registers.
4016B	%X1<def> = COPY %vreg16; GPR64:%vreg16
	Considering merging %vreg16 with %X1
	Can only merge into reserved registers.
3584B	%X0<def> = COPY %vreg123; GPR64:%vreg123
	Considering merging %vreg123 with %X0
	Can only merge into reserved registers.
272B	%X0<def> = COPY %vreg15; GPR64sp:%vreg15
	Considering merging %vreg15 with %X0
	Can only merge into reserved registers.
288B	%X1<def> = COPY %vreg16; GPR64:%vreg16
	Considering merging %vreg16 with %X1
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
W30 [0B,16r:0)[304r,304d:12)[368e,368d:6)[1424r,1424d:11)[1488e,1488d:5)[1888r,1888d:10)[1952e,1952d:4)[3152r,3152d:9)[3216e,3216d:3)[3600r,3600d:8)[3664e,3664d:2)[4032r,4032d:7)[4080e,4080d:1)  0@0B-phi 1@4080e 2@3664e 3@3216e 4@1952e 5@1488e 6@368e 7@4032r 8@3600r 9@3152r 10@1888r 11@1424r 12@304r
WZR [752r,752d:3)[816r,816d:2)[928r,928d:1)[1040r,1040d:0)  0@1040r 1@928r 2@816r 3@752r
W0 [0B,96r:0)[272r,304r:10)[1408r,1424r:9)[1424r,1456r:2)[1872r,1888r:8)[1888r,1920r:7)[3088r,3152r:6)[3152r,3184r:1)[3584r,3600r:5)[4000r,4032r:3)[4128r,4144r:4)  0@0B-phi 1@3152r 2@1424r 3@4000r 4@4128r 5@3584r 6@3088r 7@1888r 8@1872r 9@1408r 10@272r
W1 [0B,80r:0)[288r,304r:3)[3104r,3152r:1)[4016r,4032r:2)  0@0B-phi 1@3104r 2@4016r 3@288r
W2 [0B,64r:0)[3120r,3152r:1)  0@0B-phi 1@3120r
W3 [0B,48r:0)[3136r,3152r:1)  0@0B-phi 1@3136r
W4 [0B,32r:0)  0@0B-phi
%vreg1 [96r,400r:0)  0@96r
%vreg3 [80r,416r:0)  0@80r
%vreg5 [64r,432r:0)  0@64r
%vreg7 [48r,448r:0)  0@48r
%vreg9 [32r,464r:0)  0@32r
%vreg11 [496r,512r:0)  0@496r
%vreg13 [192r,208r:0)  0@192r
%vreg15 [208r,272r:0)  0@208r
%vreg16 [16r,4016r:0)  0@16r
%vreg19 [544r,560r:0)  0@544r
%vreg21 [592r,608r:0)  0@592r
%vreg23 [640r,656r:0)  0@640r
%vreg25 [688r,704r:0)  0@688r
%vreg27 [736r,752r:0)  0@736r
%vreg29 [800r,816r:0)  0@800r
%vreg31 [864r,880r:0)  0@864r
%vreg33 [912r,928r:0)  0@912r
%vreg35 [976r,992r:0)  0@976r
%vreg37 [1024r,1040r:0)  0@1024r
%vreg40 [1456r,1520r:0)  0@1456r
%vreg41 [1376r,1408r:0)  0@1376r
%vreg43 [2016r,2032r:0)  0@2016r
%vreg46 [1920r,2000r:0)  0@1920r
%vreg50 [2352r,2368r:0)  0@2352r
%vreg52 [2400r,2416r:0)  0@2400r
%vreg54 [2448r,2464r:0)  0@2448r
%vreg56 [2496r,2512r:0)  0@2496r
%vreg58 [2880r,2896r:0)  0@2880r
%vreg61 [2848r,2864r:0)  0@2848r
%vreg63 [2816r,2832r:0)  0@2816r
%vreg65 [2784r,2800r:0)  0@2784r
%vreg66 [2560r,2768r:0)  0@2560r
%vreg68 [2736r,2752r:0)  0@2736r
%vreg69 [2752r,2768r:0)  0@2752r
%vreg70 [2720r,2752r:0)  0@2720r
%vreg73 [2688r,2704r:0)  0@2688r
%vreg74 [2672r,2704r:0)  0@2672r
%vreg76 [2640r,2656r:0)  0@2640r
%vreg78 [2592r,2608r:0)  0@2592r
%vreg79 [2608r,2624r:0)  0@2608r
%vreg80 [2576r,2608r:0)  0@2576r
%vreg81 [2928r,2944r:0)  0@2928r
%vreg83 [3264r,3280r:0)  0@3264r
%vreg89 [3184r,3248r:0)  0@3184r
%vreg90 [3056r,3136r:0)  0@3056r
%vreg91 [3040r,3120r:0)  0@3040r
%vreg92 [3024r,3104r:0)  0@3024r
%vreg94 [2992r,3008r:0)  0@2992r
%vreg95 [3008r,3088r:0)  0@3008r
%vreg96 [2976r,3008r:0)  0@2976r
%vreg99 [3856r,3888r:0)  0@3856r
%vreg101 [3744r,3840r:0)  0@3744r
%vreg103 [3808r,3824r:0)  0@3808r
%vreg104 [3824r,3840r:0)  0@3824r
%vreg105 [3792r,3824r:0)  0@3792r
%vreg107 [3760r,3776r:0)  0@3760r
%vreg109 [3312r,3328r:0)  0@3312r
%vreg112 [3376r,3392r:0)  0@3376r
%vreg113 [3360r,3392r:0)  0@3360r
%vreg115 [3424r,3440r:0)  0@3424r
%vreg118 [3488r,3504r:0)  0@3488r
%vreg119 [3472r,3504r:0)  0@3472r
%vreg123 [3536r,3584r:0)  0@3536r
%vreg126 [2064r,2080r:0)  0@2064r
%vreg127 [2112r,2144r:0)  0@2112r
%vreg129 [2128r,2144r:0)  0@2128r
%vreg131 [2176r,2192r:0)  0@2176r
%vreg132 [2224r,2256r:0)  0@2224r
%vreg134 [2240r,2256r:0)  0@2240r
%vreg137 [1552r,1568r:0)  0@1552r
%vreg138 [1600r,1632r:0)  0@1600r
%vreg140 [1616r,1632r:0)  0@1616r
%vreg142 [1664r,1680r:0)  0@1664r
%vreg143 [1712r,1744r:0)  0@1712r
%vreg145 [1728r,1744r:0)  0@1728r
%vreg148 [1088r,1104r:0)  0@1088r
%vreg149 [1136r,1168r:0)  0@1136r
%vreg151 [1152r,1168r:0)  0@1152r
%vreg153 [1200r,1216r:0)  0@1200r
%vreg154 [1248r,1280r:0)  0@1248r
%vreg156 [1264r,1280r:0)  0@1264r
%vreg159 [4112r,4128r:0)  0@4112r
%vreg160 [3920r,3936r:0)  0@3920r
%vreg162 [3936r,4000r:0)  0@3936r
RegMasks: 304r 1424r 1888r 3152r 3600r 4032r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzWriteOpen: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=8, align=8, at location [SP]
  fi#3: size=4, align=4, at location [SP]
  fi#4: size=4, align=4, at location [SP]
  fi#5: size=4, align=4, at location [SP]
  fi#6: size=4, align=4, at location [SP]
  fi#7: size=8, align=8, at location [SP]
Function Live Ins: %X0 in %vreg0, %X1 in %vreg2, %W2 in %vreg4, %W3 in %vreg6, %W4 in %vreg8, %LR in %vreg17

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %X1 %W2 %W3 %W4 %LR
16B		%vreg16<def> = COPY %LR; GPR64:%vreg16
32B		%vreg9<def> = COPY %W4; GPR32:%vreg9
48B		%vreg7<def> = COPY %W3; GPR32:%vreg7
64B		%vreg5<def> = COPY %W2; GPR32:%vreg5
80B		%vreg3<def> = COPY %X1; GPR64:%vreg3
96B		%vreg1<def> = COPY %X0; GPR64:%vreg1
192B		%vreg13<def> = ADRP <ga:@BZ2_bzWriteOpen>[TF=1]; GPR64common:%vreg13
208B		%vreg15<def> = ADDXri %vreg13, <ga:@BZ2_bzWriteOpen>[TF=34], 0; GPR64sp:%vreg15 GPR64common:%vreg13
256B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
272B		%X0<def> = COPY %vreg15; GPR64sp:%vreg15
288B		%X1<def> = COPY %vreg16; GPR64:%vreg16
304B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
320B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
352B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
368B		STACKMAP 0, 0, %vreg5, 0, <fi#3>, 0, %vreg1, 0, <fi#1>, 0, 0, <fi#7>, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, %vreg7, 0, <fi#4>, 0, %vreg9, 0, <fi#5>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) GPR32:%vreg5,%vreg7,%vreg9 GPR64:%vreg1,%vreg3
384B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
400B		STRXui %vreg1, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg1
416B		STRXui %vreg3, <fi#2>, 0; mem:ST8[FixedStack2] GPR64:%vreg3
432B		STRWui %vreg5, <fi#3>, 0; mem:ST4[FixedStack3] GPR32:%vreg5
448B		STRWui %vreg7, <fi#4>, 0; mem:ST4[FixedStack4] GPR32:%vreg7
464B		STRWui %vreg9, <fi#5>, 0; mem:ST4[FixedStack5] GPR32:%vreg9
480B		STRXui %XZR, <fi#7>, 0; mem:ST8[FixedStack7]
496B		%vreg11<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg11
512B		CBZX %vreg11, <BB#2>; GPR64:%vreg11
	    Successors according to CFG: BB#2 BB#1

528B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
544B		%vreg19<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg19
560B		STRWui %WZR, %vreg19, 0; mem:ST4[%1] GPR64common:%vreg19
	    Successors according to CFG: BB#2

576B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#1
592B		%vreg21<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg21
608B		CBZX %vreg21, <BB#4>; GPR64:%vreg21
	    Successors according to CFG: BB#4 BB#3

624B	BB#3: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#2
640B		%vreg23<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg23
656B		STRWui %WZR, %vreg23, 1274; mem:ST4[%lastErr] GPR64common:%vreg23
	    Successors according to CFG: BB#4

672B	BB#4: derived from LLVM BB %if.end.3
	    Predecessors according to CFG: BB#2 BB#3
688B		%vreg25<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg25
704B		CBZX %vreg25, <BB#11>; GPR64:%vreg25
	    Successors according to CFG: BB#11 BB#5

720B	BB#5: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#4
736B		%vreg27<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32common:%vreg27
752B		%WZR<def> = SUBSWri %vreg27, 1, 0, %NZCV<imp-def>; GPR32common:%vreg27
768B		Bcc 11, <BB#11>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#11 BB#6

784B	BB#6: derived from LLVM BB %lor.lhs.false.6
	    Predecessors according to CFG: BB#5
800B		%vreg29<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32common:%vreg29
816B		%WZR<def> = SUBSWri %vreg29, 9, 0, %NZCV<imp-def>; GPR32common:%vreg29
832B		Bcc 12, <BB#11>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#11 BB#7

848B	BB#7: derived from LLVM BB %lor.lhs.false.8
	    Predecessors according to CFG: BB#6
864B		%vreg31<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32:%vreg31
880B		TBNZW %vreg31, 31, <BB#11>; GPR32:%vreg31
	    Successors according to CFG: BB#11 BB#8

896B	BB#8: derived from LLVM BB %lor.lhs.false.10
	    Predecessors according to CFG: BB#7
912B		%vreg33<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32common:%vreg33
928B		%WZR<def> = SUBSWri %vreg33, 250, 0, %NZCV<imp-def>; GPR32common:%vreg33
944B		Bcc 12, <BB#11>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#11 BB#9

960B	BB#9: derived from LLVM BB %lor.lhs.false.12
	    Predecessors according to CFG: BB#8
976B		%vreg35<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg35
992B		TBNZW %vreg35, 31, <BB#11>; GPR32:%vreg35
	    Successors according to CFG: BB#11 BB#10

1008B	BB#10: derived from LLVM BB %lor.lhs.false.14
	    Predecessors according to CFG: BB#9
1024B		%vreg37<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32common:%vreg37
1040B		%WZR<def> = SUBSWri %vreg37, 4, 0, %NZCV<imp-def>; GPR32common:%vreg37
1056B		Bcc 13, <BB#16>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#16 BB#11

1072B	BB#11: derived from LLVM BB %if.then.16
	    Predecessors according to CFG: BB#4 BB#5 BB#6 BB#7 BB#8 BB#9 BB#10
1088B		%vreg148<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg148
1104B		CBZX %vreg148, <BB#13>; GPR64:%vreg148
	    Successors according to CFG: BB#13 BB#12

1120B	BB#12: derived from LLVM BB %if.then.18
	    Predecessors according to CFG: BB#11
1136B		%vreg149<def> = MOVi32imm 4294967294; GPR32:%vreg149
1152B		%vreg151<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg151
1168B		STRWui %vreg149, %vreg151, 0; mem:ST4[%12] GPR32:%vreg149 GPR64common:%vreg151
	    Successors according to CFG: BB#13

1184B	BB#13: derived from LLVM BB %if.end.19
	    Predecessors according to CFG: BB#11 BB#12
1200B		%vreg153<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg153
1216B		CBZX %vreg153, <BB#15>; GPR64:%vreg153
	    Successors according to CFG: BB#15 BB#14

1232B	BB#14: derived from LLVM BB %if.then.21
	    Predecessors according to CFG: BB#13
1248B		%vreg154<def> = MOVi32imm 4294967294; GPR32:%vreg154
1264B		%vreg156<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg156
1280B		STRWui %vreg154, %vreg156, 1274; mem:ST4[%lastErr22] GPR32:%vreg154 GPR64common:%vreg156
	    Successors according to CFG: BB#15

1296B	BB#15: derived from LLVM BB %if.end.23
	    Predecessors according to CFG: BB#13 BB#14
1328B		STRXui %XZR, <fi#0>, 0; mem:ST8[FixedStack0]
1344B		B <BB#41>
	    Successors according to CFG: BB#41

1360B	BB#16: derived from LLVM BB %if.end.24
	    Predecessors according to CFG: BB#10
1376B		%vreg41<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg41
1392B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1408B		%X0<def> = COPY %vreg41; GPR64:%vreg41
1424B		BL <ga:@ferror>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
1440B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1456B		%vreg40<def> = COPY %W0; GPR32:%vreg40
1472B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1488B		STACKMAP 1, 0, 0, <fi#3>, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#2>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4)
1504B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1520B		CBZW %vreg40, <BB#22>; GPR32:%vreg40
	    Successors according to CFG: BB#22 BB#17

1536B	BB#17: derived from LLVM BB %if.then.25
	    Predecessors according to CFG: BB#16
1552B		%vreg137<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg137
1568B		CBZX %vreg137, <BB#19>; GPR64:%vreg137
	    Successors according to CFG: BB#19 BB#18

1584B	BB#18: derived from LLVM BB %if.then.27
	    Predecessors according to CFG: BB#17
1600B		%vreg138<def> = MOVi32imm 4294967290; GPR32:%vreg138
1616B		%vreg140<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg140
1632B		STRWui %vreg138, %vreg140, 0; mem:ST4[%17] GPR32:%vreg138 GPR64common:%vreg140
	    Successors according to CFG: BB#19

1648B	BB#19: derived from LLVM BB %if.end.28
	    Predecessors according to CFG: BB#17 BB#18
1664B		%vreg142<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg142
1680B		CBZX %vreg142, <BB#21>; GPR64:%vreg142
	    Successors according to CFG: BB#21 BB#20

1696B	BB#20: derived from LLVM BB %if.then.30
	    Predecessors according to CFG: BB#19
1712B		%vreg143<def> = MOVi32imm 4294967290; GPR32:%vreg143
1728B		%vreg145<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg145
1744B		STRWui %vreg143, %vreg145, 1274; mem:ST4[%lastErr31] GPR32:%vreg143 GPR64common:%vreg145
	    Successors according to CFG: BB#21

1760B	BB#21: derived from LLVM BB %if.end.32
	    Predecessors according to CFG: BB#19 BB#20
1792B		STRXui %XZR, <fi#0>, 0; mem:ST8[FixedStack0]
1808B		B <BB#41>
	    Successors according to CFG: BB#41

1824B	BB#22: derived from LLVM BB %if.end.33
	    Predecessors according to CFG: BB#16
1856B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1872B		%X0<def> = MOVi64imm 5104
1888B		BL <ga:@malloc>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X0<imp-def>
1904B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1920B		%vreg46<def> = COPY %X0; GPR64:%vreg46
1936B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1952B		STACKMAP 2, 0, 0, <fi#3>, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#2>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4)
1968B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2000B		STRXui %vreg46, <fi#7>, 0; mem:ST8[FixedStack7] GPR64:%vreg46
2016B		%vreg43<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg43
2032B		CBNZX %vreg43, <BB#28>; GPR64:%vreg43
	    Successors according to CFG: BB#28 BB#23

2048B	BB#23: derived from LLVM BB %if.then.36
	    Predecessors according to CFG: BB#22
2064B		%vreg126<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg126
2080B		CBZX %vreg126, <BB#25>; GPR64:%vreg126
	    Successors according to CFG: BB#25 BB#24

2096B	BB#24: derived from LLVM BB %if.then.38
	    Predecessors according to CFG: BB#23
2112B		%vreg127<def> = MOVi32imm 4294967293; GPR32:%vreg127
2128B		%vreg129<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg129
2144B		STRWui %vreg127, %vreg129, 0; mem:ST4[%23] GPR32:%vreg127 GPR64common:%vreg129
	    Successors according to CFG: BB#25

2160B	BB#25: derived from LLVM BB %if.end.39
	    Predecessors according to CFG: BB#23 BB#24
2176B		%vreg131<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg131
2192B		CBZX %vreg131, <BB#27>; GPR64:%vreg131
	    Successors according to CFG: BB#27 BB#26

2208B	BB#26: derived from LLVM BB %if.then.41
	    Predecessors according to CFG: BB#25
2224B		%vreg132<def> = MOVi32imm 4294967293; GPR32:%vreg132
2240B		%vreg134<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg134
2256B		STRWui %vreg132, %vreg134, 1274; mem:ST4[%lastErr42] GPR32:%vreg132 GPR64common:%vreg134
	    Successors according to CFG: BB#27

2272B	BB#27: derived from LLVM BB %if.end.43
	    Predecessors according to CFG: BB#25 BB#26
2304B		STRXui %XZR, <fi#0>, 0; mem:ST8[FixedStack0]
2320B		B <BB#41>
	    Successors according to CFG: BB#41

2336B	BB#28: derived from LLVM BB %if.end.44
	    Predecessors according to CFG: BB#22
2352B		%vreg50<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg50
2368B		CBZX %vreg50, <BB#30>; GPR64:%vreg50
	    Successors according to CFG: BB#30 BB#29

2384B	BB#29: derived from LLVM BB %if.then.46
	    Predecessors according to CFG: BB#28
2400B		%vreg52<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg52
2416B		STRWui %WZR, %vreg52, 0; mem:ST4[%27] GPR64common:%vreg52
	    Successors according to CFG: BB#30

2432B	BB#30: derived from LLVM BB %if.end.47
	    Predecessors according to CFG: BB#28 BB#29
2448B		%vreg54<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg54
2464B		CBZX %vreg54, <BB#32>; GPR64:%vreg54
	    Successors according to CFG: BB#32 BB#31

2480B	BB#31: derived from LLVM BB %if.then.49
	    Predecessors according to CFG: BB#30
2496B		%vreg56<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg56
2512B		STRWui %WZR, %vreg56, 1274; mem:ST4[%lastErr50] GPR64common:%vreg56
	    Successors according to CFG: BB#32

2528B	BB#32: derived from LLVM BB %if.end.51
	    Predecessors according to CFG: BB#30 BB#31
2560B		%vreg66<def> = MOVi32imm 1; GPR32:%vreg66
2576B		%vreg80<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg80
2592B		%vreg78<def> = MOVi64imm 5100; GPR64:%vreg78
2608B		%vreg79<def> = ADDXrr %vreg80, %vreg78; GPR64common:%vreg79 GPR64:%vreg80,%vreg78
2624B		STRBBui %WZR, %vreg79, 0; mem:ST1[%initialisedOk] GPR64common:%vreg79
2640B		%vreg76<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg76
2656B		STRWui %WZR, %vreg76, 1252; mem:ST4[%bufN] GPR64common:%vreg76
2672B		%vreg74<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg74
2688B		%vreg73<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg73
2704B		STRXui %vreg74, %vreg73, 0; mem:ST8[%handle] GPR64:%vreg74 GPR64common:%vreg73
2720B		%vreg70<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg70
2736B		%vreg68<def> = MOVi64imm 5012; GPR64:%vreg68
2752B		%vreg69<def> = ADDXrr %vreg70, %vreg68; GPR64common:%vreg69 GPR64:%vreg70,%vreg68
2768B		STRBBui %vreg66, %vreg69, 0; mem:ST1[%writing] GPR32:%vreg66 GPR64common:%vreg69
2784B		%vreg65<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg65
2800B		STRXui %XZR, %vreg65, 634; mem:ST8[%bzalloc] GPR64common:%vreg65
2816B		%vreg63<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg63
2832B		STRXui %XZR, %vreg63, 635; mem:ST8[%bzfree] GPR64common:%vreg63
2848B		%vreg61<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg61
2864B		STRXui %XZR, %vreg61, 636; mem:ST8[%opaque] GPR64common:%vreg61
2880B		%vreg58<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32:%vreg58
2896B		CBNZW %vreg58, <BB#34>; GPR32:%vreg58
	    Successors according to CFG: BB#34 BB#33

2912B	BB#33: derived from LLVM BB %if.then.55
	    Predecessors according to CFG: BB#32
2928B		%vreg81<def> = MOVi32imm 30; GPR32:%vreg81
2944B		STRWui %vreg81, <fi#5>, 0; mem:ST4[FixedStack5] GPR32:%vreg81
	    Successors according to CFG: BB#34

2960B	BB#34: derived from LLVM BB %if.end.56
	    Predecessors according to CFG: BB#32 BB#33
2976B		%vreg96<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg96
2992B		%vreg94<def> = MOVi64imm 5016; GPR64:%vreg94
3008B		%vreg95<def> = ADDXrr %vreg96, %vreg94; GPR64:%vreg95,%vreg96,%vreg94
3024B		%vreg92<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg92
3040B		%vreg91<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg91
3056B		%vreg90<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32:%vreg90
3072B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3088B		%X0<def> = COPY %vreg95; GPR64:%vreg95
3104B		%W1<def> = COPY %vreg92; GPR32:%vreg92
3120B		%W2<def> = COPY %vreg91; GPR32:%vreg91
3136B		%W3<def> = COPY %vreg90; GPR32:%vreg90
3152B		BL <ga:@BZ2_bzCompressInit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %W2<imp-use>, %W3<imp-use>, %W0<imp-def>
3168B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3184B		%vreg89<def> = COPY %W0; GPR32:%vreg89
3200B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3216B		STACKMAP 3, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack6](align=4) LD8[FixedStack0]
3232B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3248B		STRWui %vreg89, <fi#6>, 0; mem:ST4[FixedStack6] GPR32:%vreg89
3264B		%vreg83<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg83
3280B		CBZW %vreg83, <BB#40>; GPR32:%vreg83
	    Successors according to CFG: BB#40 BB#35

3296B	BB#35: derived from LLVM BB %if.then.60
	    Predecessors according to CFG: BB#34
3312B		%vreg109<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg109
3328B		CBZX %vreg109, <BB#37>; GPR64:%vreg109
	    Successors according to CFG: BB#37 BB#36

3344B	BB#36: derived from LLVM BB %if.then.62
	    Predecessors according to CFG: BB#35
3360B		%vreg113<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg113
3376B		%vreg112<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg112
3392B		STRWui %vreg113, %vreg112, 0; mem:ST4[%46] GPR32:%vreg113 GPR64common:%vreg112
	    Successors according to CFG: BB#37

3408B	BB#37: derived from LLVM BB %if.end.63
	    Predecessors according to CFG: BB#35 BB#36
3424B		%vreg115<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg115
3440B		CBZX %vreg115, <BB#39>; GPR64:%vreg115
	    Successors according to CFG: BB#39 BB#38

3456B	BB#38: derived from LLVM BB %if.then.65
	    Predecessors according to CFG: BB#37
3472B		%vreg119<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg119
3488B		%vreg118<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg118
3504B		STRWui %vreg119, %vreg118, 1274; mem:ST4[%lastErr66] GPR32:%vreg119 GPR64common:%vreg118
	    Successors according to CFG: BB#39

3520B	BB#39: derived from LLVM BB %if.end.67
	    Predecessors according to CFG: BB#37 BB#38
3536B		%vreg123<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg123
3568B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3584B		%X0<def> = COPY %vreg123; GPR64:%vreg123
3600B		BL <ga:@free>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>
3616B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3648B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3664B		STACKMAP 4, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0]
3680B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3696B		STRXui %XZR, <fi#0>, 0; mem:ST8[FixedStack0]
3712B		B <BB#41>
	    Successors according to CFG: BB#41

3728B	BB#40: derived from LLVM BB %if.end.68
	    Predecessors according to CFG: BB#34
3744B		%vreg101<def> = MOVi32imm 1; GPR32:%vreg101
3760B		%vreg107<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg107
3776B		STRWui %WZR, %vreg107, 1256; mem:ST4[%avail_in] GPR64common:%vreg107
3792B		%vreg105<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg105
3808B		%vreg103<def> = MOVi64imm 5100; GPR64:%vreg103
3824B		%vreg104<def> = ADDXrr %vreg105, %vreg103; GPR64common:%vreg104 GPR64:%vreg105,%vreg103
3840B		STRBBui %vreg101, %vreg104, 0; mem:ST1[%initialisedOk70] GPR32:%vreg101 GPR64common:%vreg104
3856B		%vreg99<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg99
3888B		STRXui %vreg99, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg99
	    Successors according to CFG: BB#41

3904B	BB#41: derived from LLVM BB %return
	    Predecessors according to CFG: BB#40 BB#39 BB#27 BB#21 BB#15
3920B		%vreg160<def> = ADRP <ga:@BZ2_bzWriteOpen>[TF=1]; GPR64common:%vreg160
3936B		%vreg162<def> = ADDXri %vreg160, <ga:@BZ2_bzWriteOpen>[TF=34], 0; GPR64sp:%vreg162 GPR64common:%vreg160
3984B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4000B		%X0<def> = COPY %vreg162; GPR64sp:%vreg162
4016B		%X1<def> = COPY %vreg16; GPR64:%vreg16
4032B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
4048B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4064B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4080B		STACKMAP 5, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0]
4096B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4112B		%vreg159<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg159
4128B		%X0<def> = COPY %vreg159; GPR64:%vreg159
4144B		RET_ReallyLR %X0<imp-use>

# End machine code for function BZ2_bzWriteOpen.

handleMove 1136B -> 1160B: %vreg149<def> = MOVi32imm 4294967294; GPR32:%vreg149
     %vreg149:	[1136r,1168r:0)  0@1136r
        -->	[1160r,1168r:0)  0@1160r
handleMove 1248B -> 1272B: %vreg154<def> = MOVi32imm 4294967294; GPR32:%vreg154
     %vreg154:	[1248r,1280r:0)  0@1248r
        -->	[1272r,1280r:0)  0@1272r
handleMove 1600B -> 1624B: %vreg138<def> = MOVi32imm 4294967290; GPR32:%vreg138
     %vreg138:	[1600r,1632r:0)  0@1600r
        -->	[1624r,1632r:0)  0@1624r
handleMove 1712B -> 1736B: %vreg143<def> = MOVi32imm 4294967290; GPR32:%vreg143
     %vreg143:	[1712r,1744r:0)  0@1712r
        -->	[1736r,1744r:0)  0@1736r
handleMove 2112B -> 2136B: %vreg127<def> = MOVi32imm 4294967293; GPR32:%vreg127
     %vreg127:	[2112r,2144r:0)  0@2112r
        -->	[2136r,2144r:0)  0@2136r
handleMove 2224B -> 2248B: %vreg132<def> = MOVi32imm 4294967293; GPR32:%vreg132
     %vreg132:	[2224r,2256r:0)  0@2224r
        -->	[2248r,2256r:0)  0@2248r
AllocationOrder(GPR32sponly) = [ ]
handleMove 2560B -> 2728B: %vreg66<def> = MOVi32imm 1; GPR32:%vreg66
     %vreg66:	[2560r,2768r:0)  0@2560r
        -->	[2728r,2768r:0)  0@2728r
handleMove 3008B -> 3064B: %vreg95<def> = ADDXrr %vreg96, %vreg94; GPR64:%vreg95,%vreg96,%vreg94
     %vreg95:	[3008r,3088r:0)  0@3008r
        -->	[3064r,3088r:0)  0@3064r
     %vreg96:	[2976r,3008r:0)  0@2976r
        -->	[2976r,3064r:0)  0@2976r
     %vreg94:	[2992r,3008r:0)  0@2992r
        -->	[2992r,3064r:0)  0@2992r
handleMove 2992B -> 3060B: %vreg94<def> = MOVi64imm 5016; GPR64:%vreg94
     %vreg94:	[2992r,3064r:0)  0@2992r
        -->	[3060r,3064r:0)  0@3060r
handleMove 3744B -> 3800B: %vreg101<def> = MOVi32imm 1; GPR32:%vreg101
     %vreg101:	[3744r,3840r:0)  0@3744r
        -->	[3800r,3840r:0)  0@3800r
********** GREEDY REGISTER ALLOCATION **********
********** Function: BZ2_bzWriteOpen
********** INTERVALS **********
W30 [0B,16r:0)[304r,304d:12)[368e,368d:6)[1424r,1424d:11)[1488e,1488d:5)[1888r,1888d:10)[1952e,1952d:4)[3152r,3152d:9)[3216e,3216d:3)[3600r,3600d:8)[3664e,3664d:2)[4032r,4032d:7)[4080e,4080d:1)  0@0B-phi 1@4080e 2@3664e 3@3216e 4@1952e 5@1488e 6@368e 7@4032r 8@3600r 9@3152r 10@1888r 11@1424r 12@304r
WZR [752r,752d:3)[816r,816d:2)[928r,928d:1)[1040r,1040d:0)  0@1040r 1@928r 2@816r 3@752r
W0 [0B,96r:0)[272r,304r:10)[1408r,1424r:9)[1424r,1456r:2)[1872r,1888r:8)[1888r,1920r:7)[3088r,3152r:6)[3152r,3184r:1)[3584r,3600r:5)[4000r,4032r:3)[4128r,4144r:4)  0@0B-phi 1@3152r 2@1424r 3@4000r 4@4128r 5@3584r 6@3088r 7@1888r 8@1872r 9@1408r 10@272r
W1 [0B,80r:0)[288r,304r:3)[3104r,3152r:1)[4016r,4032r:2)  0@0B-phi 1@3104r 2@4016r 3@288r
W2 [0B,64r:0)[3120r,3152r:1)  0@0B-phi 1@3120r
W3 [0B,48r:0)[3136r,3152r:1)  0@0B-phi 1@3136r
W4 [0B,32r:0)  0@0B-phi
%vreg1 [96r,400r:0)  0@96r
%vreg3 [80r,416r:0)  0@80r
%vreg5 [64r,432r:0)  0@64r
%vreg7 [48r,448r:0)  0@48r
%vreg9 [32r,464r:0)  0@32r
%vreg11 [496r,512r:0)  0@496r
%vreg13 [192r,208r:0)  0@192r
%vreg15 [208r,272r:0)  0@208r
%vreg16 [16r,4016r:0)  0@16r
%vreg19 [544r,560r:0)  0@544r
%vreg21 [592r,608r:0)  0@592r
%vreg23 [640r,656r:0)  0@640r
%vreg25 [688r,704r:0)  0@688r
%vreg27 [736r,752r:0)  0@736r
%vreg29 [800r,816r:0)  0@800r
%vreg31 [864r,880r:0)  0@864r
%vreg33 [912r,928r:0)  0@912r
%vreg35 [976r,992r:0)  0@976r
%vreg37 [1024r,1040r:0)  0@1024r
%vreg40 [1456r,1520r:0)  0@1456r
%vreg41 [1376r,1408r:0)  0@1376r
%vreg43 [2016r,2032r:0)  0@2016r
%vreg46 [1920r,2000r:0)  0@1920r
%vreg50 [2352r,2368r:0)  0@2352r
%vreg52 [2400r,2416r:0)  0@2400r
%vreg54 [2448r,2464r:0)  0@2448r
%vreg56 [2496r,2512r:0)  0@2496r
%vreg58 [2880r,2896r:0)  0@2880r
%vreg61 [2848r,2864r:0)  0@2848r
%vreg63 [2816r,2832r:0)  0@2816r
%vreg65 [2784r,2800r:0)  0@2784r
%vreg66 [2728r,2768r:0)  0@2728r
%vreg68 [2736r,2752r:0)  0@2736r
%vreg69 [2752r,2768r:0)  0@2752r
%vreg70 [2720r,2752r:0)  0@2720r
%vreg73 [2688r,2704r:0)  0@2688r
%vreg74 [2672r,2704r:0)  0@2672r
%vreg76 [2640r,2656r:0)  0@2640r
%vreg78 [2592r,2608r:0)  0@2592r
%vreg79 [2608r,2624r:0)  0@2608r
%vreg80 [2576r,2608r:0)  0@2576r
%vreg81 [2928r,2944r:0)  0@2928r
%vreg83 [3264r,3280r:0)  0@3264r
%vreg89 [3184r,3248r:0)  0@3184r
%vreg90 [3056r,3136r:0)  0@3056r
%vreg91 [3040r,3120r:0)  0@3040r
%vreg92 [3024r,3104r:0)  0@3024r
%vreg94 [3060r,3064r:0)  0@3060r
%vreg95 [3064r,3088r:0)  0@3064r
%vreg96 [2976r,3064r:0)  0@2976r
%vreg99 [3856r,3888r:0)  0@3856r
%vreg101 [3800r,3840r:0)  0@3800r
%vreg103 [3808r,3824r:0)  0@3808r
%vreg104 [3824r,3840r:0)  0@3824r
%vreg105 [3792r,3824r:0)  0@3792r
%vreg107 [3760r,3776r:0)  0@3760r
%vreg109 [3312r,3328r:0)  0@3312r
%vreg112 [3376r,3392r:0)  0@3376r
%vreg113 [3360r,3392r:0)  0@3360r
%vreg115 [3424r,3440r:0)  0@3424r
%vreg118 [3488r,3504r:0)  0@3488r
%vreg119 [3472r,3504r:0)  0@3472r
%vreg123 [3536r,3584r:0)  0@3536r
%vreg126 [2064r,2080r:0)  0@2064r
%vreg127 [2136r,2144r:0)  0@2136r
%vreg129 [2128r,2144r:0)  0@2128r
%vreg131 [2176r,2192r:0)  0@2176r
%vreg132 [2248r,2256r:0)  0@2248r
%vreg134 [2240r,2256r:0)  0@2240r
%vreg137 [1552r,1568r:0)  0@1552r
%vreg138 [1624r,1632r:0)  0@1624r
%vreg140 [1616r,1632r:0)  0@1616r
%vreg142 [1664r,1680r:0)  0@1664r
%vreg143 [1736r,1744r:0)  0@1736r
%vreg145 [1728r,1744r:0)  0@1728r
%vreg148 [1088r,1104r:0)  0@1088r
%vreg149 [1160r,1168r:0)  0@1160r
%vreg151 [1152r,1168r:0)  0@1152r
%vreg153 [1200r,1216r:0)  0@1200r
%vreg154 [1272r,1280r:0)  0@1272r
%vreg156 [1264r,1280r:0)  0@1264r
%vreg159 [4112r,4128r:0)  0@4112r
%vreg160 [3920r,3936r:0)  0@3920r
%vreg162 [3936r,4000r:0)  0@3936r
RegMasks: 304r 1424r 1888r 3152r 3600r 4032r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzWriteOpen: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=8, align=8, at location [SP]
  fi#3: size=4, align=4, at location [SP]
  fi#4: size=4, align=4, at location [SP]
  fi#5: size=4, align=4, at location [SP]
  fi#6: size=4, align=4, at location [SP]
  fi#7: size=8, align=8, at location [SP]
Function Live Ins: %X0 in %vreg0, %X1 in %vreg2, %W2 in %vreg4, %W3 in %vreg6, %W4 in %vreg8, %LR in %vreg17

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %X1 %W2 %W3 %W4 %LR
16B		%vreg16<def> = COPY %LR; GPR64:%vreg16
32B		%vreg9<def> = COPY %W4; GPR32:%vreg9
48B		%vreg7<def> = COPY %W3; GPR32:%vreg7
64B		%vreg5<def> = COPY %W2; GPR32:%vreg5
80B		%vreg3<def> = COPY %X1; GPR64:%vreg3
96B		%vreg1<def> = COPY %X0; GPR64:%vreg1
192B		%vreg13<def> = ADRP <ga:@BZ2_bzWriteOpen>[TF=1]; GPR64common:%vreg13
208B		%vreg15<def> = ADDXri %vreg13, <ga:@BZ2_bzWriteOpen>[TF=34], 0; GPR64sp:%vreg15 GPR64common:%vreg13
256B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
272B		%X0<def> = COPY %vreg15; GPR64sp:%vreg15
288B		%X1<def> = COPY %vreg16; GPR64:%vreg16
304B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
320B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
352B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
368B		STACKMAP 0, 0, %vreg5, 0, <fi#3>, 0, %vreg1, 0, <fi#1>, 0, 0, <fi#7>, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, %vreg7, 0, <fi#4>, 0, %vreg9, 0, <fi#5>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) GPR32:%vreg5,%vreg7,%vreg9 GPR64:%vreg1,%vreg3
384B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
400B		STRXui %vreg1, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg1
416B		STRXui %vreg3, <fi#2>, 0; mem:ST8[FixedStack2] GPR64:%vreg3
432B		STRWui %vreg5, <fi#3>, 0; mem:ST4[FixedStack3] GPR32:%vreg5
448B		STRWui %vreg7, <fi#4>, 0; mem:ST4[FixedStack4] GPR32:%vreg7
464B		STRWui %vreg9, <fi#5>, 0; mem:ST4[FixedStack5] GPR32:%vreg9
480B		STRXui %XZR, <fi#7>, 0; mem:ST8[FixedStack7]
496B		%vreg11<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg11
512B		CBZX %vreg11, <BB#2>; GPR64:%vreg11
	    Successors according to CFG: BB#2 BB#1

528B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
544B		%vreg19<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg19
560B		STRWui %WZR, %vreg19, 0; mem:ST4[%1] GPR64common:%vreg19
	    Successors according to CFG: BB#2

576B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#1
592B		%vreg21<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg21
608B		CBZX %vreg21, <BB#4>; GPR64:%vreg21
	    Successors according to CFG: BB#4 BB#3

624B	BB#3: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#2
640B		%vreg23<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg23
656B		STRWui %WZR, %vreg23, 1274; mem:ST4[%lastErr] GPR64common:%vreg23
	    Successors according to CFG: BB#4

672B	BB#4: derived from LLVM BB %if.end.3
	    Predecessors according to CFG: BB#2 BB#3
688B		%vreg25<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg25
704B		CBZX %vreg25, <BB#11>; GPR64:%vreg25
	    Successors according to CFG: BB#11 BB#5

720B	BB#5: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#4
736B		%vreg27<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32common:%vreg27
752B		%WZR<def> = SUBSWri %vreg27, 1, 0, %NZCV<imp-def>; GPR32common:%vreg27
768B		Bcc 11, <BB#11>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#11 BB#6

784B	BB#6: derived from LLVM BB %lor.lhs.false.6
	    Predecessors according to CFG: BB#5
800B		%vreg29<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32common:%vreg29
816B		%WZR<def> = SUBSWri %vreg29, 9, 0, %NZCV<imp-def>; GPR32common:%vreg29
832B		Bcc 12, <BB#11>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#11 BB#7

848B	BB#7: derived from LLVM BB %lor.lhs.false.8
	    Predecessors according to CFG: BB#6
864B		%vreg31<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32:%vreg31
880B		TBNZW %vreg31, 31, <BB#11>; GPR32:%vreg31
	    Successors according to CFG: BB#11 BB#8

896B	BB#8: derived from LLVM BB %lor.lhs.false.10
	    Predecessors according to CFG: BB#7
912B		%vreg33<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32common:%vreg33
928B		%WZR<def> = SUBSWri %vreg33, 250, 0, %NZCV<imp-def>; GPR32common:%vreg33
944B		Bcc 12, <BB#11>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#11 BB#9

960B	BB#9: derived from LLVM BB %lor.lhs.false.12
	    Predecessors according to CFG: BB#8
976B		%vreg35<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg35
992B		TBNZW %vreg35, 31, <BB#11>; GPR32:%vreg35
	    Successors according to CFG: BB#11 BB#10

1008B	BB#10: derived from LLVM BB %lor.lhs.false.14
	    Predecessors according to CFG: BB#9
1024B		%vreg37<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32common:%vreg37
1040B		%WZR<def> = SUBSWri %vreg37, 4, 0, %NZCV<imp-def>; GPR32common:%vreg37
1056B		Bcc 13, <BB#16>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#16 BB#11

1072B	BB#11: derived from LLVM BB %if.then.16
	    Predecessors according to CFG: BB#4 BB#5 BB#6 BB#7 BB#8 BB#9 BB#10
1088B		%vreg148<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg148
1104B		CBZX %vreg148, <BB#13>; GPR64:%vreg148
	    Successors according to CFG: BB#13 BB#12

1120B	BB#12: derived from LLVM BB %if.then.18
	    Predecessors according to CFG: BB#11
1152B		%vreg151<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg151
1160B		%vreg149<def> = MOVi32imm 4294967294; GPR32:%vreg149
1168B		STRWui %vreg149, %vreg151, 0; mem:ST4[%12] GPR32:%vreg149 GPR64common:%vreg151
	    Successors according to CFG: BB#13

1184B	BB#13: derived from LLVM BB %if.end.19
	    Predecessors according to CFG: BB#11 BB#12
1200B		%vreg153<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg153
1216B		CBZX %vreg153, <BB#15>; GPR64:%vreg153
	    Successors according to CFG: BB#15 BB#14

1232B	BB#14: derived from LLVM BB %if.then.21
	    Predecessors according to CFG: BB#13
1264B		%vreg156<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg156
1272B		%vreg154<def> = MOVi32imm 4294967294; GPR32:%vreg154
1280B		STRWui %vreg154, %vreg156, 1274; mem:ST4[%lastErr22] GPR32:%vreg154 GPR64common:%vreg156
	    Successors according to CFG: BB#15

1296B	BB#15: derived from LLVM BB %if.end.23
	    Predecessors according to CFG: BB#13 BB#14
1328B		STRXui %XZR, <fi#0>, 0; mem:ST8[FixedStack0]
1344B		B <BB#41>
	    Successors according to CFG: BB#41

1360B	BB#16: derived from LLVM BB %if.end.24
	    Predecessors according to CFG: BB#10
1376B		%vreg41<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg41
1392B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1408B		%X0<def> = COPY %vreg41; GPR64:%vreg41
1424B		BL <ga:@ferror>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
1440B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1456B		%vreg40<def> = COPY %W0; GPR32:%vreg40
1472B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1488B		STACKMAP 1, 0, 0, <fi#3>, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#2>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4)
1504B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1520B		CBZW %vreg40, <BB#22>; GPR32:%vreg40
	    Successors according to CFG: BB#22 BB#17

1536B	BB#17: derived from LLVM BB %if.then.25
	    Predecessors according to CFG: BB#16
1552B		%vreg137<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg137
1568B		CBZX %vreg137, <BB#19>; GPR64:%vreg137
	    Successors according to CFG: BB#19 BB#18

1584B	BB#18: derived from LLVM BB %if.then.27
	    Predecessors according to CFG: BB#17
1616B		%vreg140<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg140
1624B		%vreg138<def> = MOVi32imm 4294967290; GPR32:%vreg138
1632B		STRWui %vreg138, %vreg140, 0; mem:ST4[%17] GPR32:%vreg138 GPR64common:%vreg140
	    Successors according to CFG: BB#19

1648B	BB#19: derived from LLVM BB %if.end.28
	    Predecessors according to CFG: BB#17 BB#18
1664B		%vreg142<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg142
1680B		CBZX %vreg142, <BB#21>; GPR64:%vreg142
	    Successors according to CFG: BB#21 BB#20

1696B	BB#20: derived from LLVM BB %if.then.30
	    Predecessors according to CFG: BB#19
1728B		%vreg145<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg145
1736B		%vreg143<def> = MOVi32imm 4294967290; GPR32:%vreg143
1744B		STRWui %vreg143, %vreg145, 1274; mem:ST4[%lastErr31] GPR32:%vreg143 GPR64common:%vreg145
	    Successors according to CFG: BB#21

1760B	BB#21: derived from LLVM BB %if.end.32
	    Predecessors according to CFG: BB#19 BB#20
1792B		STRXui %XZR, <fi#0>, 0; mem:ST8[FixedStack0]
1808B		B <BB#41>
	    Successors according to CFG: BB#41

1824B	BB#22: derived from LLVM BB %if.end.33
	    Predecessors according to CFG: BB#16
1856B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1872B		%X0<def> = MOVi64imm 5104
1888B		BL <ga:@malloc>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X0<imp-def>
1904B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1920B		%vreg46<def> = COPY %X0; GPR64:%vreg46
1936B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1952B		STACKMAP 2, 0, 0, <fi#3>, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#2>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4)
1968B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2000B		STRXui %vreg46, <fi#7>, 0; mem:ST8[FixedStack7] GPR64:%vreg46
2016B		%vreg43<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg43
2032B		CBNZX %vreg43, <BB#28>; GPR64:%vreg43
	    Successors according to CFG: BB#28 BB#23

2048B	BB#23: derived from LLVM BB %if.then.36
	    Predecessors according to CFG: BB#22
2064B		%vreg126<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg126
2080B		CBZX %vreg126, <BB#25>; GPR64:%vreg126
	    Successors according to CFG: BB#25 BB#24

2096B	BB#24: derived from LLVM BB %if.then.38
	    Predecessors according to CFG: BB#23
2128B		%vreg129<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg129
2136B		%vreg127<def> = MOVi32imm 4294967293; GPR32:%vreg127
2144B		STRWui %vreg127, %vreg129, 0; mem:ST4[%23] GPR32:%vreg127 GPR64common:%vreg129
	    Successors according to CFG: BB#25

2160B	BB#25: derived from LLVM BB %if.end.39
	    Predecessors according to CFG: BB#23 BB#24
2176B		%vreg131<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg131
2192B		CBZX %vreg131, <BB#27>; GPR64:%vreg131
	    Successors according to CFG: BB#27 BB#26

2208B	BB#26: derived from LLVM BB %if.then.41
	    Predecessors according to CFG: BB#25
2240B		%vreg134<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg134
2248B		%vreg132<def> = MOVi32imm 4294967293; GPR32:%vreg132
2256B		STRWui %vreg132, %vreg134, 1274; mem:ST4[%lastErr42] GPR32:%vreg132 GPR64common:%vreg134
	    Successors according to CFG: BB#27

2272B	BB#27: derived from LLVM BB %if.end.43
	    Predecessors according to CFG: BB#25 BB#26
2304B		STRXui %XZR, <fi#0>, 0; mem:ST8[FixedStack0]
2320B		B <BB#41>
	    Successors according to CFG: BB#41

2336B	BB#28: derived from LLVM BB %if.end.44
	    Predecessors according to CFG: BB#22
2352B		%vreg50<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg50
2368B		CBZX %vreg50, <BB#30>; GPR64:%vreg50
	    Successors according to CFG: BB#30 BB#29

2384B	BB#29: derived from LLVM BB %if.then.46
	    Predecessors according to CFG: BB#28
2400B		%vreg52<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg52
2416B		STRWui %WZR, %vreg52, 0; mem:ST4[%27] GPR64common:%vreg52
	    Successors according to CFG: BB#30

2432B	BB#30: derived from LLVM BB %if.end.47
	    Predecessors according to CFG: BB#28 BB#29
2448B		%vreg54<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg54
2464B		CBZX %vreg54, <BB#32>; GPR64:%vreg54
	    Successors according to CFG: BB#32 BB#31

2480B	BB#31: derived from LLVM BB %if.then.49
	    Predecessors according to CFG: BB#30
2496B		%vreg56<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg56
2512B		STRWui %WZR, %vreg56, 1274; mem:ST4[%lastErr50] GPR64common:%vreg56
	    Successors according to CFG: BB#32

2528B	BB#32: derived from LLVM BB %if.end.51
	    Predecessors according to CFG: BB#30 BB#31
2576B		%vreg80<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg80
2592B		%vreg78<def> = MOVi64imm 5100; GPR64:%vreg78
2608B		%vreg79<def> = ADDXrr %vreg80, %vreg78; GPR64common:%vreg79 GPR64:%vreg80,%vreg78
2624B		STRBBui %WZR, %vreg79, 0; mem:ST1[%initialisedOk] GPR64common:%vreg79
2640B		%vreg76<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg76
2656B		STRWui %WZR, %vreg76, 1252; mem:ST4[%bufN] GPR64common:%vreg76
2672B		%vreg74<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg74
2688B		%vreg73<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg73
2704B		STRXui %vreg74, %vreg73, 0; mem:ST8[%handle] GPR64:%vreg74 GPR64common:%vreg73
2720B		%vreg70<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg70
2728B		%vreg66<def> = MOVi32imm 1; GPR32:%vreg66
2736B		%vreg68<def> = MOVi64imm 5012; GPR64:%vreg68
2752B		%vreg69<def> = ADDXrr %vreg70, %vreg68; GPR64common:%vreg69 GPR64:%vreg70,%vreg68
2768B		STRBBui %vreg66, %vreg69, 0; mem:ST1[%writing] GPR32:%vreg66 GPR64common:%vreg69
2784B		%vreg65<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg65
2800B		STRXui %XZR, %vreg65, 634; mem:ST8[%bzalloc] GPR64common:%vreg65
2816B		%vreg63<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg63
2832B		STRXui %XZR, %vreg63, 635; mem:ST8[%bzfree] GPR64common:%vreg63
2848B		%vreg61<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg61
2864B		STRXui %XZR, %vreg61, 636; mem:ST8[%opaque] GPR64common:%vreg61
2880B		%vreg58<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32:%vreg58
2896B		CBNZW %vreg58, <BB#34>; GPR32:%vreg58
	    Successors according to CFG: BB#34 BB#33

2912B	BB#33: derived from LLVM BB %if.then.55
	    Predecessors according to CFG: BB#32
2928B		%vreg81<def> = MOVi32imm 30; GPR32:%vreg81
2944B		STRWui %vreg81, <fi#5>, 0; mem:ST4[FixedStack5] GPR32:%vreg81
	    Successors according to CFG: BB#34

2960B	BB#34: derived from LLVM BB %if.end.56
	    Predecessors according to CFG: BB#32 BB#33
2976B		%vreg96<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg96
3024B		%vreg92<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg92
3040B		%vreg91<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg91
3056B		%vreg90<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32:%vreg90
3060B		%vreg94<def> = MOVi64imm 5016; GPR64:%vreg94
3064B		%vreg95<def> = ADDXrr %vreg96, %vreg94; GPR64:%vreg95,%vreg96,%vreg94
3072B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3088B		%X0<def> = COPY %vreg95; GPR64:%vreg95
3104B		%W1<def> = COPY %vreg92; GPR32:%vreg92
3120B		%W2<def> = COPY %vreg91; GPR32:%vreg91
3136B		%W3<def> = COPY %vreg90; GPR32:%vreg90
3152B		BL <ga:@BZ2_bzCompressInit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %W2<imp-use>, %W3<imp-use>, %W0<imp-def>
3168B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3184B		%vreg89<def> = COPY %W0; GPR32:%vreg89
3200B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3216B		STACKMAP 3, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack6](align=4) LD8[FixedStack0]
3232B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3248B		STRWui %vreg89, <fi#6>, 0; mem:ST4[FixedStack6] GPR32:%vreg89
3264B		%vreg83<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg83
3280B		CBZW %vreg83, <BB#40>; GPR32:%vreg83
	    Successors according to CFG: BB#40 BB#35

3296B	BB#35: derived from LLVM BB %if.then.60
	    Predecessors according to CFG: BB#34
3312B		%vreg109<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg109
3328B		CBZX %vreg109, <BB#37>; GPR64:%vreg109
	    Successors according to CFG: BB#37 BB#36

3344B	BB#36: derived from LLVM BB %if.then.62
	    Predecessors according to CFG: BB#35
3360B		%vreg113<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg113
3376B		%vreg112<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg112
3392B		STRWui %vreg113, %vreg112, 0; mem:ST4[%46] GPR32:%vreg113 GPR64common:%vreg112
	    Successors according to CFG: BB#37

3408B	BB#37: derived from LLVM BB %if.end.63
	    Predecessors according to CFG: BB#35 BB#36
3424B		%vreg115<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg115
3440B		CBZX %vreg115, <BB#39>; GPR64:%vreg115
	    Successors according to CFG: BB#39 BB#38

3456B	BB#38: derived from LLVM BB %if.then.65
	    Predecessors according to CFG: BB#37
3472B		%vreg119<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg119
3488B		%vreg118<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg118
3504B		STRWui %vreg119, %vreg118, 1274; mem:ST4[%lastErr66] GPR32:%vreg119 GPR64common:%vreg118
	    Successors according to CFG: BB#39

3520B	BB#39: derived from LLVM BB %if.end.67
	    Predecessors according to CFG: BB#37 BB#38
3536B		%vreg123<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg123
3568B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3584B		%X0<def> = COPY %vreg123; GPR64:%vreg123
3600B		BL <ga:@free>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>
3616B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3648B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3664B		STACKMAP 4, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0]
3680B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3696B		STRXui %XZR, <fi#0>, 0; mem:ST8[FixedStack0]
3712B		B <BB#41>
	    Successors according to CFG: BB#41

3728B	BB#40: derived from LLVM BB %if.end.68
	    Predecessors according to CFG: BB#34
3760B		%vreg107<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg107
3776B		STRWui %WZR, %vreg107, 1256; mem:ST4[%avail_in] GPR64common:%vreg107
3792B		%vreg105<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg105
3800B		%vreg101<def> = MOVi32imm 1; GPR32:%vreg101
3808B		%vreg103<def> = MOVi64imm 5100; GPR64:%vreg103
3824B		%vreg104<def> = ADDXrr %vreg105, %vreg103; GPR64common:%vreg104 GPR64:%vreg105,%vreg103
3840B		STRBBui %vreg101, %vreg104, 0; mem:ST1[%initialisedOk70] GPR32:%vreg101 GPR64common:%vreg104
3856B		%vreg99<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg99
3888B		STRXui %vreg99, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg99
	    Successors according to CFG: BB#41

3904B	BB#41: derived from LLVM BB %return
	    Predecessors according to CFG: BB#40 BB#39 BB#27 BB#21 BB#15
3920B		%vreg160<def> = ADRP <ga:@BZ2_bzWriteOpen>[TF=1]; GPR64common:%vreg160
3936B		%vreg162<def> = ADDXri %vreg160, <ga:@BZ2_bzWriteOpen>[TF=34], 0; GPR64sp:%vreg162 GPR64common:%vreg160
3984B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4000B		%X0<def> = COPY %vreg162; GPR64sp:%vreg162
4016B		%X1<def> = COPY %vreg16; GPR64:%vreg16
4032B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
4048B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4064B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4080B		STACKMAP 5, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0]
4096B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4112B		%vreg159<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg159
4128B		%X0<def> = COPY %vreg159; GPR64:%vreg159
4144B		RET_ReallyLR %X0<imp-use>

# End machine code for function BZ2_bzWriteOpen.


selectOrSplit GPR64:%vreg16 [16r,4016r:0)  0@16r w=6.886364e-04
hints: %X1
missed hint %X1
Analyze counted 3 instrs in 2 blocks, through 40 blocks.
%X1	static = 1.0 worse than no bundles
%X8	static = 1.0 worse than no bundles
%X9	static = 1.0 worse than no bundles
%X10	static = 1.0 worse than no bundles
%X11	static = 1.0 worse than no bundles
%X12	static = 1.0 worse than no bundles
%X13	static = 1.0 worse than no bundles
%X14	static = 1.0 worse than no bundles
%X15	static = 1.0 worse than no bundles
%X16	static = 1.0 worse than no bundles
%X17	static = 1.0 worse than no bundles
%X18	static = 1.0 worse than no bundles
%X0	no positive bundles
%X2	static = 1.0 worse than no bundles
%X3	static = 1.0 worse than no bundles
%X4	static = 1.0 worse than no bundles
%X5	static = 1.0 worse than no bundles
%X6	static = 1.0 worse than no bundles
%X7	static = 1.0 worse than no bundles
assigning %vreg16 to %X19: W19 [16r,4016r:0)  0@16r

selectOrSplit GPR32:%vreg9 [32r,464r:0)  0@32r w=3.641827e-03
hints: %W4
missed hint %W4
Analyze counted 3 instrs in 1 blocks, through 0 blocks.
%W4	no positive bundles
%W8	no positive bundles
%W9	no positive bundles
%W10	no positive bundles
%W11	no positive bundles
%W12	no positive bundles
%W13	no positive bundles
%W14	no positive bundles
%W15	no positive bundles
%W16	no positive bundles
%W17	no positive bundles
%W18	no positive bundles
%W0	no positive bundles
%W1	no positive bundles
%W2	no positive bundles
%W3	no positive bundles
%W5	no positive bundles
%W6	no positive bundles
%W7	no positive bundles
%W19	no positive bundles
assigning %vreg9 to %W20: W20 [32r,464r:0)  0@32r

selectOrSplit GPR32:%vreg7 [48r,448r:0)  0@48r w=3.787500e-03
hints: %W3
missed hint %W3
Analyze counted 3 instrs in 1 blocks, through 0 blocks.
%W3	no positive bundles
%W8	no positive bundles
%W9	no positive bundles
%W10	no positive bundles
%W11	no positive bundles
%W12	no positive bundles
%W13	no positive bundles
%W14	no positive bundles
%W15	no positive bundles
%W16	no positive bundles
%W17	no positive bundles
%W18	no positive bundles
%W0	no positive bundles
%W1	no positive bundles
%W2	no positive bundles
%W4	no positive bundles
%W5	no positive bundles
%W6	no positive bundles
%W7	no positive bundles
%W19	no positive bundles
%W20	no positive bundles
assigning %vreg7 to %W21: W21 [48r,448r:0)  0@48r

selectOrSplit GPR32:%vreg5 [64r,432r:0)  0@64r w=3.945312e-03
hints: %W2
missed hint %W2
Analyze counted 3 instrs in 1 blocks, through 0 blocks.
%W2	no positive bundles
%W8	no positive bundles
%W9	no positive bundles
%W10	no positive bundles
%W11	no positive bundles
%W12	no positive bundles
%W13	no positive bundles
%W14	no positive bundles
%W15	no positive bundles
%W16	no positive bundles
%W17	no positive bundles
%W18	no positive bundles
%W0	no positive bundles
%W1	no positive bundles
%W3	no positive bundles
%W4	no positive bundles
%W5	no positive bundles
%W6	no positive bundles
%W7	no positive bundles
%W19	no positive bundles
%W20	no positive bundles
%W21	no positive bundles
assigning %vreg5 to %W22: W22 [64r,432r:0)  0@64r

selectOrSplit GPR64:%vreg3 [80r,416r:0)  0@80r w=4.116848e-03
hints: %X1
missed hint %X1
Analyze counted 3 instrs in 1 blocks, through 0 blocks.
%X1	no positive bundles
%X8	no positive bundles
%X9	no positive bundles
%X10	no positive bundles
%X11	no positive bundles
%X12	no positive bundles
%X13	no positive bundles
%X14	no positive bundles
%X15	no positive bundles
%X16	no positive bundles
%X17	no positive bundles
%X18	no positive bundles
%X0	no positive bundles
%X2	no positive bundles
%X3	no positive bundles
%X4	no positive bundles
%X5	no positive bundles
%X6	no positive bundles
%X7	no positive bundles
%X19	no positive bundles
%X20	no positive bundles
%X21	no positive bundles
%X22	no positive bundles
assigning %vreg3 to %X23: W23 [80r,416r:0)  0@80r

selectOrSplit GPR64:%vreg1 [96r,400r:0)  0@96r w=4.303977e-03
hints: %X0
missed hint %X0
Analyze counted 3 instrs in 1 blocks, through 0 blocks.
%X0	no positive bundles
%X8	no positive bundles
%X9	no positive bundles
%X10	no positive bundles
%X11	no positive bundles
%X12	no positive bundles
%X13	no positive bundles
%X14	no positive bundles
%X15	no positive bundles
%X16	no positive bundles
%X17	no positive bundles
%X18	no positive bundles
%X1	no positive bundles
%X2	no positive bundles
%X3	no positive bundles
%X4	no positive bundles
%X5	no positive bundles
%X6	no positive bundles
%X7	no positive bundles
%X19	no positive bundles
%X20	no positive bundles
%X21	no positive bundles
%X22	no positive bundles
%X23	no positive bundles
assigning %vreg1 to %X24: W24 [96r,400r:0)  0@96r

selectOrSplit GPR64sp:%vreg15 [208r,272r:0)  0@208r w=4.353448e-03
hints: %X0
assigning %vreg15 to %X0: W0 [208r,272r:0)  0@208r

selectOrSplit GPR64:%vreg41 [1376r,1408r:0)  0@1376r w=3.624749e-05
hints: %X0
assigning %vreg41 to %X0: W0 [1376r,1408r:0)  0@1376r

selectOrSplit GPR32:%vreg40 [1456r,1520r:0)  0@1456r w=3.374766e-05
hints: %W0
assigning %vreg40 to %W0: W0 [1456r,1520r:0)  0@1456r

selectOrSplit GPR64:%vreg46 [1920r,2000r:0)  0@1920r w=1.618293e-05
hints: %X0
assigning %vreg46 to %X0: W0 [1920r,2000r:0)  0@1920r

selectOrSplit GPR32:%vreg92 [3024r,3104r:0)  0@3024r w=7.963031e-06
hints: %W1
assigning %vreg92 to %W1: W1 [3024r,3104r:0)  0@3024r

selectOrSplit GPR32:%vreg91 [3040r,3120r:0)  0@3040r w=7.963031e-06
hints: %W2
assigning %vreg91 to %W2: W2 [3040r,3120r:0)  0@3040r

selectOrSplit GPR32:%vreg90 [3056r,3136r:0)  0@3056r w=7.963031e-06
hints: %W3
assigning %vreg90 to %W3: W3 [3056r,3136r:0)  0@3056r

selectOrSplit GPR64:%vreg95 [3064r,3088r:0)  0@3064r w=9.014751e-06
hints: %X0
assigning %vreg95 to %X0: W0 [3064r,3088r:0)  0@3064r

selectOrSplit GPR32:%vreg89 [3184r,3248r:0)  0@3184r w=8.237618e-06
hints: %W0
assigning %vreg89 to %W0: W0 [3184r,3248r:0)  0@3184r

selectOrSplit GPR64:%vreg123 [3536r,3584r:0)  0@3536r w=4.128299e-06
hints: %X0
assigning %vreg123 to %X0: W0 [3536r,3584r:0)  0@3536r

selectOrSplit GPR64sp:%vreg162 [3936r,4000r:0)  0@3936r w=4.353448e-03
hints: %X0
assigning %vreg162 to %X0: W0 [3936r,4000r:0)  0@3936r

selectOrSplit GPR64:%vreg159 [4112r,4128r:0)  0@4112r w=inf
hints: %X0
assigning %vreg159 to %X0: W0 [4112r,4128r:0)  0@4112r

selectOrSplit GPR64common:%vreg13 [192r,208r:0)  0@192r w=inf
assigning %vreg13 to %X8: W8 [192r,208r:0)  0@192r

selectOrSplit GPR64:%vreg11 [496r,512r:0)  0@496r w=inf
assigning %vreg11 to %X8: W8 [496r,512r:0)  0@496r

selectOrSplit GPR64common:%vreg19 [544r,560r:0)  0@544r w=inf
assigning %vreg19 to %X8: W8 [544r,560r:0)  0@544r

selectOrSplit GPR64:%vreg21 [592r,608r:0)  0@592r w=inf
assigning %vreg21 to %X8: W8 [592r,608r:0)  0@592r

selectOrSplit GPR64common:%vreg23 [640r,656r:0)  0@640r w=inf
assigning %vreg23 to %X8: W8 [640r,656r:0)  0@640r

selectOrSplit GPR64:%vreg25 [688r,704r:0)  0@688r w=inf
assigning %vreg25 to %X8: W8 [688r,704r:0)  0@688r

selectOrSplit GPR32common:%vreg27 [736r,752r:0)  0@736r w=inf
assigning %vreg27 to %W8: W8 [736r,752r:0)  0@736r

selectOrSplit GPR32common:%vreg29 [800r,816r:0)  0@800r w=inf
assigning %vreg29 to %W8: W8 [800r,816r:0)  0@800r

selectOrSplit GPR32:%vreg31 [864r,880r:0)  0@864r w=inf
assigning %vreg31 to %W8: W8 [864r,880r:0)  0@864r

selectOrSplit GPR32common:%vreg33 [912r,928r:0)  0@912r w=inf
assigning %vreg33 to %W8: W8 [912r,928r:0)  0@912r

selectOrSplit GPR32:%vreg35 [976r,992r:0)  0@976r w=inf
assigning %vreg35 to %W8: W8 [976r,992r:0)  0@976r

selectOrSplit GPR32common:%vreg37 [1024r,1040r:0)  0@1024r w=inf
assigning %vreg37 to %W8: W8 [1024r,1040r:0)  0@1024r

selectOrSplit GPR64:%vreg148 [1088r,1104r:0)  0@1088r w=inf
assigning %vreg148 to %X8: W8 [1088r,1104r:0)  0@1088r

selectOrSplit GPR64common:%vreg151 [1152r,1168r:0)  0@1152r w=2.384918e-03
assigning %vreg151 to %X8: W8 [1152r,1168r:0)  0@1152r

selectOrSplit GPR32:%vreg149 [1160r,1168r:0)  0@1160r w=inf
assigning %vreg149 to %W9: W9 [1160r,1168r:0)  0@1160r

selectOrSplit GPR64:%vreg153 [1200r,1216r:0)  0@1200r w=inf
assigning %vreg153 to %X8: W8 [1200r,1216r:0)  0@1200r

selectOrSplit GPR64common:%vreg156 [1264r,1280r:0)  0@1264r w=2.384918e-03
assigning %vreg156 to %X8: W8 [1264r,1280r:0)  0@1264r

selectOrSplit GPR32:%vreg154 [1272r,1280r:0)  0@1272r w=inf
assigning %vreg154 to %W9: W9 [1272r,1280r:0)  0@1272r

selectOrSplit GPR64:%vreg137 [1552r,1568r:0)  0@1552r w=inf
assigning %vreg137 to %X8: W8 [1552r,1568r:0)  0@1552r

selectOrSplit GPR64common:%vreg140 [1616r,1632r:0)  0@1616r w=9.097141e-06
assigning %vreg140 to %X8: W8 [1616r,1632r:0)  0@1616r

selectOrSplit GPR32:%vreg138 [1624r,1632r:0)  0@1624r w=inf
assigning %vreg138 to %W9: W9 [1624r,1632r:0)  0@1624r

selectOrSplit GPR64:%vreg142 [1664r,1680r:0)  0@1664r w=inf
assigning %vreg142 to %X8: W8 [1664r,1680r:0)  0@1664r

selectOrSplit GPR64common:%vreg145 [1728r,1744r:0)  0@1728r w=9.097141e-06
assigning %vreg145 to %X8: W8 [1728r,1744r:0)  0@1728r

selectOrSplit GPR32:%vreg143 [1736r,1744r:0)  0@1736r w=inf
assigning %vreg143 to %W9: W9 [1736r,1744r:0)  0@1736r

selectOrSplit GPR64:%vreg43 [2016r,2032r:0)  0@2016r w=inf
assigning %vreg43 to %X8: W8 [2016r,2032r:0)  0@2016r

selectOrSplit GPR64:%vreg126 [2064r,2080r:0)  0@2064r w=inf
assigning %vreg126 to %X8: W8 [2064r,2080r:0)  0@2064r

selectOrSplit GPR64common:%vreg129 [2128r,2144r:0)  0@2128r w=4.401842e-06
assigning %vreg129 to %X8: W8 [2128r,2144r:0)  0@2128r

selectOrSplit GPR32:%vreg127 [2136r,2144r:0)  0@2136r w=inf
assigning %vreg127 to %W9: W9 [2136r,2144r:0)  0@2136r

selectOrSplit GPR64:%vreg131 [2176r,2192r:0)  0@2176r w=inf
assigning %vreg131 to %X8: W8 [2176r,2192r:0)  0@2176r

selectOrSplit GPR64common:%vreg134 [2240r,2256r:0)  0@2240r w=4.401842e-06
assigning %vreg134 to %X8: W8 [2240r,2256r:0)  0@2240r

selectOrSplit GPR32:%vreg132 [2248r,2256r:0)  0@2248r w=inf
assigning %vreg132 to %W9: W9 [2248r,2256r:0)  0@2248r

selectOrSplit GPR64:%vreg50 [2352r,2368r:0)  0@2352r w=inf
assigning %vreg50 to %X8: W8 [2352r,2368r:0)  0@2352r

selectOrSplit GPR64common:%vreg52 [2400r,2416r:0)  0@2400r w=inf
assigning %vreg52 to %X8: W8 [2400r,2416r:0)  0@2400r

selectOrSplit GPR64:%vreg54 [2448r,2464r:0)  0@2448r w=inf
assigning %vreg54 to %X8: W8 [2448r,2464r:0)  0@2448r

selectOrSplit GPR64common:%vreg56 [2496r,2512r:0)  0@2496r w=inf
assigning %vreg56 to %X8: W8 [2496r,2512r:0)  0@2496r

selectOrSplit GPR64:%vreg80 [2576r,2608r:0)  0@2576r w=8.760210e-06
assigning %vreg80 to %X8: W8 [2576r,2608r:0)  0@2576r

selectOrSplit GPR64:%vreg78 [2592r,2608r:0)  0@2592r w=inf
assigning %vreg78 to %X9: W9 [2592r,2608r:0)  0@2592r

selectOrSplit GPR64common:%vreg79 [2608r,2624r:0)  0@2608r w=inf
assigning %vreg79 to %X8: W8 [2608r,2624r:0)  0@2608r

selectOrSplit GPR64common:%vreg76 [2640r,2656r:0)  0@2640r w=inf
assigning %vreg76 to %X8: W8 [2640r,2656r:0)  0@2640r

selectOrSplit GPR64:%vreg74 [2672r,2704r:0)  0@2672r w=8.760210e-06
assigning %vreg74 to %X8: W8 [2672r,2704r:0)  0@2672r

selectOrSplit GPR64common:%vreg73 [2688r,2704r:0)  0@2688r w=inf
assigning %vreg73 to %X9: W9 [2688r,2704r:0)  0@2688r

selectOrSplit GPR64:%vreg70 [2720r,2752r:0)  0@2720r w=8.760210e-06
assigning %vreg70 to %X8: W8 [2720r,2752r:0)  0@2720r

selectOrSplit GPR32:%vreg66 [2728r,2768r:0)  0@2728r w=4.300467e-06
assigning %vreg66 to %W9: W9 [2728r,2768r:0)  0@2728r

selectOrSplit GPR64:%vreg68 [2736r,2752r:0)  0@2736r w=inf
assigning %vreg68 to %X10: W10 [2736r,2752r:0)  0@2736r

selectOrSplit GPR64common:%vreg69 [2752r,2768r:0)  0@2752r w=inf
assigning %vreg69 to %X8: W8 [2752r,2768r:0)  0@2752r

selectOrSplit GPR64common:%vreg65 [2784r,2800r:0)  0@2784r w=inf
assigning %vreg65 to %X8: W8 [2784r,2800r:0)  0@2784r

selectOrSplit GPR64common:%vreg63 [2816r,2832r:0)  0@2816r w=inf
assigning %vreg63 to %X8: W8 [2816r,2832r:0)  0@2816r

selectOrSplit GPR64common:%vreg61 [2848r,2864r:0)  0@2848r w=inf
assigning %vreg61 to %X8: W8 [2848r,2864r:0)  0@2848r

selectOrSplit GPR32:%vreg58 [2880r,2896r:0)  0@2880r w=inf
assigning %vreg58 to %W8: W8 [2880r,2896r:0)  0@2880r

selectOrSplit GPR32:%vreg81 [2928r,2944r:0)  0@2928r w=inf
assigning %vreg81 to %W8: W8 [2928r,2944r:0)  0@2928r

selectOrSplit GPR64:%vreg96 [2976r,3064r:0)  0@2976r w=7.754940e-06
assigning %vreg96 to %X8: W8 [2976r,3064r:0)  0@2976r

selectOrSplit GPR64:%vreg94 [3060r,3064r:0)  0@3060r w=inf
assigning %vreg94 to %X9: W9 [3060r,3064r:0)  0@3060r

selectOrSplit GPR32:%vreg83 [3264r,3280r:0)  0@3264r w=inf
assigning %vreg83 to %W8: W8 [3264r,3280r:0)  0@3264r

selectOrSplit GPR64:%vreg109 [3312r,3328r:0)  0@3312r w=inf
assigning %vreg109 to %X8: W8 [3312r,3328r:0)  0@3312r

selectOrSplit GPR32:%vreg113 [3360r,3392r:0)  0@3360r w=2.260699e-06
assigning %vreg113 to %W8: W8 [3360r,3392r:0)  0@3360r

selectOrSplit GPR64common:%vreg112 [3376r,3392r:0)  0@3376r w=inf
assigning %vreg112 to %X9: W9 [3376r,3392r:0)  0@3376r

selectOrSplit GPR64:%vreg115 [3424r,3440r:0)  0@3424r w=inf
assigning %vreg115 to %X8: W8 [3424r,3440r:0)  0@3424r

selectOrSplit GPR32:%vreg119 [3472r,3504r:0)  0@3472r w=2.260699e-06
assigning %vreg119 to %W8: W8 [3472r,3504r:0)  0@3472r

selectOrSplit GPR64common:%vreg118 [3488r,3504r:0)  0@3488r w=inf
assigning %vreg118 to %X9: W9 [3488r,3504r:0)  0@3488r

selectOrSplit GPR64common:%vreg107 [3760r,3776r:0)  0@3760r w=inf
assigning %vreg107 to %X8: W8 [3760r,3776r:0)  0@3760r

selectOrSplit GPR64:%vreg105 [3792r,3824r:0)  0@3792r w=4.238811e-06
assigning %vreg105 to %X8: W8 [3792r,3824r:0)  0@3792r

selectOrSplit GPR32:%vreg101 [3800r,3840r:0)  0@3800r w=2.080871e-06
assigning %vreg101 to %W9: W9 [3800r,3840r:0)  0@3800r

selectOrSplit GPR64:%vreg103 [3808r,3824r:0)  0@3808r w=inf
assigning %vreg103 to %X10: W10 [3808r,3824r:0)  0@3808r

selectOrSplit GPR64common:%vreg104 [3824r,3840r:0)  0@3824r w=inf
assigning %vreg104 to %X8: W8 [3824r,3840r:0)  0@3824r

selectOrSplit GPR64:%vreg99 [3856r,3888r:0)  0@3856r w=inf
assigning %vreg99 to %X8: W8 [3856r,3888r:0)  0@3856r

selectOrSplit GPR64common:%vreg160 [3920r,3936r:0)  0@3920r w=inf
assigning %vreg160 to %X8: W8 [3920r,3936r:0)  0@3920r

********** STACK TRANSFORMATION METADATA **********
********** Function: BZ2_bzWriteOpen
********** REGISTER MAP **********
[%vreg1 -> %X24] GPR64
[%vreg3 -> %X23] GPR64
[%vreg5 -> %W22] GPR32
[%vreg7 -> %W21] GPR32
[%vreg9 -> %W20] GPR32
[%vreg11 -> %X8] GPR64
[%vreg13 -> %X8] GPR64common
[%vreg15 -> %X0] GPR64sp
[%vreg16 -> %X19] GPR64
[%vreg19 -> %X8] GPR64common
[%vreg21 -> %X8] GPR64
[%vreg23 -> %X8] GPR64common
[%vreg25 -> %X8] GPR64
[%vreg27 -> %W8] GPR32common
[%vreg29 -> %W8] GPR32common
[%vreg31 -> %W8] GPR32
[%vreg33 -> %W8] GPR32common
[%vreg35 -> %W8] GPR32
[%vreg37 -> %W8] GPR32common
[%vreg40 -> %W0] GPR32
[%vreg41 -> %X0] GPR64
[%vreg43 -> %X8] GPR64
[%vreg46 -> %X0] GPR64
[%vreg50 -> %X8] GPR64
[%vreg52 -> %X8] GPR64common
[%vreg54 -> %X8] GPR64
[%vreg56 -> %X8] GPR64common
[%vreg58 -> %W8] GPR32
[%vreg61 -> %X8] GPR64common
[%vreg63 -> %X8] GPR64common
[%vreg65 -> %X8] GPR64common
[%vreg66 -> %W9] GPR32
[%vreg68 -> %X10] GPR64
[%vreg69 -> %X8] GPR64common
[%vreg70 -> %X8] GPR64
[%vreg73 -> %X9] GPR64common
[%vreg74 -> %X8] GPR64
[%vreg76 -> %X8] GPR64common
[%vreg78 -> %X9] GPR64
[%vreg79 -> %X8] GPR64common
[%vreg80 -> %X8] GPR64
[%vreg81 -> %W8] GPR32
[%vreg83 -> %W8] GPR32
[%vreg89 -> %W0] GPR32
[%vreg90 -> %W3] GPR32
[%vreg91 -> %W2] GPR32
[%vreg92 -> %W1] GPR32
[%vreg94 -> %X9] GPR64
[%vreg95 -> %X0] GPR64
[%vreg96 -> %X8] GPR64
[%vreg99 -> %X8] GPR64
[%vreg101 -> %W9] GPR32
[%vreg103 -> %X10] GPR64
[%vreg104 -> %X8] GPR64common
[%vreg105 -> %X8] GPR64
[%vreg107 -> %X8] GPR64common
[%vreg109 -> %X8] GPR64
[%vreg112 -> %X9] GPR64common
[%vreg113 -> %W8] GPR32
[%vreg115 -> %X8] GPR64
[%vreg118 -> %X9] GPR64common
[%vreg119 -> %W8] GPR32
[%vreg123 -> %X0] GPR64
[%vreg126 -> %X8] GPR64
[%vreg127 -> %W9] GPR32
[%vreg129 -> %X8] GPR64common
[%vreg131 -> %X8] GPR64
[%vreg132 -> %W9] GPR32
[%vreg134 -> %X8] GPR64common
[%vreg137 -> %X8] GPR64
[%vreg138 -> %W9] GPR32
[%vreg140 -> %X8] GPR64common
[%vreg142 -> %X8] GPR64
[%vreg143 -> %W9] GPR32
[%vreg145 -> %X8] GPR64common
[%vreg148 -> %X8] GPR64
[%vreg149 -> %W9] GPR32
[%vreg151 -> %X8] GPR64common
[%vreg153 -> %X8] GPR64
[%vreg154 -> %W9] GPR32
[%vreg156 -> %X8] GPR64common
[%vreg159 -> %X0] GPR64
[%vreg160 -> %X8] GPR64common
[%vreg162 -> %X0] GPR64sp


Stackmap 0:
  STACKMAP 0, 0, %vreg5, 0, <fi#3>, 0, %vreg1, 0, <fi#1>, 0, 0, <fi#7>, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, %vreg7, 0, <fi#4>, 0, %vreg9, 0, <fi#5>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) GPR32:%vreg5,%vreg7,%vreg9 GPR64:%vreg1,%vreg3

i32 %blockSize100k: in register %W22 (vreg 5)
i32* %blockSize100k.addr: in stack slot 3 (size: 4)
i32* %bzerror: in register %X24 (vreg 1)
i32** %bzerror.addr: in stack slot 1 (size: 8)
%struct.bzFile** %bzf: in stack slot 7 (size: 8)
%struct._IO_FILE* %f: in register %X23 (vreg 3)
%struct._IO_FILE** %f.addr: in stack slot 2 (size: 8)
i32* %ret: in stack slot 6 (size: 4)
i8** %retval: in stack slot 0 (size: 8)
i32 %verbosity: in register %W21 (vreg 7)
i32* %verbosity.addr: in stack slot 4 (size: 4)
i32 %workFactor: in register %W20 (vreg 9)
i32* %workFactor.addr: in stack slot 5 (size: 4)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, 0, <fi#3>, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#2>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4)

i32* %blockSize100k.addr: in stack slot 3 (size: 4)
i32** %bzerror.addr: in stack slot 1 (size: 8)
%struct.bzFile** %bzf: in stack slot 7 (size: 8)
%struct._IO_FILE** %f.addr: in stack slot 2 (size: 8)
i32* %ret: in stack slot 6 (size: 4)
i8** %retval: in stack slot 0 (size: 8)
i32* %verbosity.addr: in stack slot 4 (size: 4)
i32* %workFactor.addr: in stack slot 5 (size: 4)

Duplicate operand locations:


Stackmap 2:
  STACKMAP 2, 0, 0, <fi#3>, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#2>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4)

i32* %blockSize100k.addr: in stack slot 3 (size: 4)
i32** %bzerror.addr: in stack slot 1 (size: 8)
%struct.bzFile** %bzf: in stack slot 7 (size: 8)
%struct._IO_FILE** %f.addr: in stack slot 2 (size: 8)
i32* %ret: in stack slot 6 (size: 4)
i8** %retval: in stack slot 0 (size: 8)
i32* %verbosity.addr: in stack slot 4 (size: 4)
i32* %workFactor.addr: in stack slot 5 (size: 4)

Duplicate operand locations:


Stackmap 3:
  STACKMAP 3, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack6](align=4) LD8[FixedStack0]

i32** %bzerror.addr: in stack slot 1 (size: 8)
%struct.bzFile** %bzf: in stack slot 7 (size: 8)
i32* %ret: in stack slot 6 (size: 4)
i8** %retval: in stack slot 0 (size: 8)

Duplicate operand locations:


Stackmap 4:
  STACKMAP 4, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0]

i8** %retval: in stack slot 0 (size: 8)

Duplicate operand locations:


Stackmap 5:
  STACKMAP 5, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0]

i8** %retval: in stack slot 0 (size: 8)

Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, %vreg5, 0, <fi#3>, 0, %vreg1, 0, <fi#1>, 0, 0, <fi#7>, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, %vreg7, 0, <fi#4>, 0, %vreg9, 0, <fi#5>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) GPR32:%vreg5,%vreg7,%vreg9 GPR64:%vreg1,%vreg3
  -> Call instruction SlotIndex 304B, searching vregs 0 -> 164 and stack slots 0 -> 8
    + vreg16 is live in register but not in stackmap
      Defining instruction: %vreg16<def> = COPY %LR; GPR64:%vreg16
      Value: generated value, 1 instruction(s)

  STACKMAP 1, 0, 0, <fi#3>, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#2>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4)
  -> Call instruction SlotIndex 1424B, searching vregs 0 -> 164 and stack slots 0 -> 8
    + vreg16 is live in register but not in stackmap
      Defining instruction: %vreg16<def> = COPY %LR; GPR64:%vreg16
      Value: generated value, 1 instruction(s)

  STACKMAP 2, 0, 0, <fi#3>, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#2>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4)
  -> Call instruction SlotIndex 1888B, searching vregs 0 -> 164 and stack slots 0 -> 8
    + vreg16 is live in register but not in stackmap
      Defining instruction: %vreg16<def> = COPY %LR; GPR64:%vreg16
      Value: generated value, 1 instruction(s)

  STACKMAP 3, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack6](align=4) LD8[FixedStack0]
  -> Call instruction SlotIndex 3152B, searching vregs 0 -> 164 and stack slots 0 -> 8
    + vreg16 is live in register but not in stackmap
      Defining instruction: %vreg16<def> = COPY %LR; GPR64:%vreg16
      Value: generated value, 1 instruction(s)

  STACKMAP 4, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0]
  -> Call instruction SlotIndex 3600B, searching vregs 0 -> 164 and stack slots 0 -> 8
    + vreg16 is live in register but not in stackmap
      Defining instruction: %vreg16<def> = COPY %LR; GPR64:%vreg16
      Value: generated value, 1 instruction(s)

  STACKMAP 5, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0]
  -> Call instruction SlotIndex 4032B, searching vregs 0 -> 164 and stack slots 0 -> 8

********** REWRITE VIRTUAL REGISTERS **********
********** Function: BZ2_bzWriteOpen
********** REGISTER MAP **********
[%vreg1 -> %X24] GPR64
[%vreg3 -> %X23] GPR64
[%vreg5 -> %W22] GPR32
[%vreg7 -> %W21] GPR32
[%vreg9 -> %W20] GPR32
[%vreg11 -> %X8] GPR64
[%vreg13 -> %X8] GPR64common
[%vreg15 -> %X0] GPR64sp
[%vreg16 -> %X19] GPR64
[%vreg19 -> %X8] GPR64common
[%vreg21 -> %X8] GPR64
[%vreg23 -> %X8] GPR64common
[%vreg25 -> %X8] GPR64
[%vreg27 -> %W8] GPR32common
[%vreg29 -> %W8] GPR32common
[%vreg31 -> %W8] GPR32
[%vreg33 -> %W8] GPR32common
[%vreg35 -> %W8] GPR32
[%vreg37 -> %W8] GPR32common
[%vreg40 -> %W0] GPR32
[%vreg41 -> %X0] GPR64
[%vreg43 -> %X8] GPR64
[%vreg46 -> %X0] GPR64
[%vreg50 -> %X8] GPR64
[%vreg52 -> %X8] GPR64common
[%vreg54 -> %X8] GPR64
[%vreg56 -> %X8] GPR64common
[%vreg58 -> %W8] GPR32
[%vreg61 -> %X8] GPR64common
[%vreg63 -> %X8] GPR64common
[%vreg65 -> %X8] GPR64common
[%vreg66 -> %W9] GPR32
[%vreg68 -> %X10] GPR64
[%vreg69 -> %X8] GPR64common
[%vreg70 -> %X8] GPR64
[%vreg73 -> %X9] GPR64common
[%vreg74 -> %X8] GPR64
[%vreg76 -> %X8] GPR64common
[%vreg78 -> %X9] GPR64
[%vreg79 -> %X8] GPR64common
[%vreg80 -> %X8] GPR64
[%vreg81 -> %W8] GPR32
[%vreg83 -> %W8] GPR32
[%vreg89 -> %W0] GPR32
[%vreg90 -> %W3] GPR32
[%vreg91 -> %W2] GPR32
[%vreg92 -> %W1] GPR32
[%vreg94 -> %X9] GPR64
[%vreg95 -> %X0] GPR64
[%vreg96 -> %X8] GPR64
[%vreg99 -> %X8] GPR64
[%vreg101 -> %W9] GPR32
[%vreg103 -> %X10] GPR64
[%vreg104 -> %X8] GPR64common
[%vreg105 -> %X8] GPR64
[%vreg107 -> %X8] GPR64common
[%vreg109 -> %X8] GPR64
[%vreg112 -> %X9] GPR64common
[%vreg113 -> %W8] GPR32
[%vreg115 -> %X8] GPR64
[%vreg118 -> %X9] GPR64common
[%vreg119 -> %W8] GPR32
[%vreg123 -> %X0] GPR64
[%vreg126 -> %X8] GPR64
[%vreg127 -> %W9] GPR32
[%vreg129 -> %X8] GPR64common
[%vreg131 -> %X8] GPR64
[%vreg132 -> %W9] GPR32
[%vreg134 -> %X8] GPR64common
[%vreg137 -> %X8] GPR64
[%vreg138 -> %W9] GPR32
[%vreg140 -> %X8] GPR64common
[%vreg142 -> %X8] GPR64
[%vreg143 -> %W9] GPR32
[%vreg145 -> %X8] GPR64common
[%vreg148 -> %X8] GPR64
[%vreg149 -> %W9] GPR32
[%vreg151 -> %X8] GPR64common
[%vreg153 -> %X8] GPR64
[%vreg154 -> %W9] GPR32
[%vreg156 -> %X8] GPR64common
[%vreg159 -> %X0] GPR64
[%vreg160 -> %X8] GPR64common
[%vreg162 -> %X0] GPR64sp

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %LR %W2 %W3 %W4 %X0 %X1
16B		%vreg16<def> = COPY %LR; GPR64:%vreg16
32B		%vreg9<def> = COPY %W4; GPR32:%vreg9
48B		%vreg7<def> = COPY %W3; GPR32:%vreg7
64B		%vreg5<def> = COPY %W2; GPR32:%vreg5
80B		%vreg3<def> = COPY %X1; GPR64:%vreg3
96B		%vreg1<def> = COPY %X0; GPR64:%vreg1
192B		%vreg13<def> = ADRP <ga:@BZ2_bzWriteOpen>[TF=1]; GPR64common:%vreg13
208B		%vreg15<def> = ADDXri %vreg13<kill>, <ga:@BZ2_bzWriteOpen>[TF=34], 0; GPR64sp:%vreg15 GPR64common:%vreg13
256B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
272B		%X0<def> = COPY %vreg15<kill>; GPR64sp:%vreg15
288B		%X1<def> = COPY %vreg16; GPR64:%vreg16
304B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
320B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
352B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
368B		STACKMAP 0, 0, %vreg5, 0, <fi#3>, 0, %vreg1, 0, <fi#1>, 0, 0, <fi#7>, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, %vreg7, 0, <fi#4>, 0, %vreg9, 0, <fi#5>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) GPR32:%vreg5,%vreg7,%vreg9 GPR64:%vreg1,%vreg3
384B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
400B		STRXui %vreg1<kill>, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg1
416B		STRXui %vreg3<kill>, <fi#2>, 0; mem:ST8[FixedStack2] GPR64:%vreg3
432B		STRWui %vreg5<kill>, <fi#3>, 0; mem:ST4[FixedStack3] GPR32:%vreg5
448B		STRWui %vreg7<kill>, <fi#4>, 0; mem:ST4[FixedStack4] GPR32:%vreg7
464B		STRWui %vreg9<kill>, <fi#5>, 0; mem:ST4[FixedStack5] GPR32:%vreg9
480B		STRXui %XZR, <fi#7>, 0; mem:ST8[FixedStack7]
496B		%vreg11<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg11
512B		CBZX %vreg11<kill>, <BB#2>; GPR64:%vreg11
	    Successors according to CFG: BB#2 BB#1
> %X19<def> = COPY %LR
> %W20<def> = COPY %W4
> %W21<def> = COPY %W3
> %W22<def> = COPY %W2
> %X23<def> = COPY %X1
> %X24<def> = COPY %X0
> %X8<def> = ADRP <ga:@BZ2_bzWriteOpen>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@BZ2_bzWriteOpen>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19
> BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 0, 0, %W22, 0, <fi#3>, 0, %X24, 0, <fi#1>, 0, 0, <fi#7>, 0, %X23, 0, <fi#2>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, %W21, 0, <fi#4>, 0, %W20, 0, <fi#5>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRXui %X24<kill>, <fi#1>, 0; mem:ST8[FixedStack1]
> STRXui %X23<kill>, <fi#2>, 0; mem:ST8[FixedStack2]
> STRWui %W22<kill>, <fi#3>, 0; mem:ST4[FixedStack3]
> STRWui %W21<kill>, <fi#4>, 0; mem:ST4[FixedStack4]
> STRWui %W20<kill>, <fi#5>, 0; mem:ST4[FixedStack5]
> STRXui %XZR, <fi#7>, 0; mem:ST8[FixedStack7]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> CBZX %X8<kill>, <BB#2>
528B	BB#1: derived from LLVM BB %if.then
	    Live Ins: %X19
	    Predecessors according to CFG: BB#0
544B		%vreg19<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg19
560B		STRWui %WZR, %vreg19<kill>, 0; mem:ST4[%1] GPR64common:%vreg19
	    Successors according to CFG: BB#2
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRWui %WZR, %X8<kill>, 0; mem:ST4[%1]
576B	BB#2: derived from LLVM BB %if.end
	    Live Ins: %X19
	    Predecessors according to CFG: BB#0 BB#1
592B		%vreg21<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg21
608B		CBZX %vreg21<kill>, <BB#4>; GPR64:%vreg21
	    Successors according to CFG: BB#4 BB#3
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> CBZX %X8<kill>, <BB#4>
624B	BB#3: derived from LLVM BB %if.then.2
	    Live Ins: %X19
	    Predecessors according to CFG: BB#2
640B		%vreg23<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg23
656B		STRWui %WZR, %vreg23<kill>, 1274; mem:ST4[%lastErr] GPR64common:%vreg23
	    Successors according to CFG: BB#4
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> STRWui %WZR, %X8<kill>, 1274; mem:ST4[%lastErr]
672B	BB#4: derived from LLVM BB %if.end.3
	    Live Ins: %X19
	    Predecessors according to CFG: BB#2 BB#3
688B		%vreg25<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg25
704B		CBZX %vreg25<kill>, <BB#11>; GPR64:%vreg25
	    Successors according to CFG: BB#11 BB#5
> %X8<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2]
> CBZX %X8<kill>, <BB#11>
720B	BB#5: derived from LLVM BB %lor.lhs.false
	    Live Ins: %X19
	    Predecessors according to CFG: BB#4
736B		%vreg27<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32common:%vreg27
752B		%WZR<def> = SUBSWri %vreg27<kill>, 1, 0, %NZCV<imp-def>; GPR32common:%vreg27
768B		Bcc 11, <BB#11>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#11 BB#6
> %W8<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3]
> %WZR<def> = SUBSWri %W8<kill>, 1, 0, %NZCV<imp-def>
> Bcc 11, <BB#11>, %NZCV<imp-use,kill>
784B	BB#6: derived from LLVM BB %lor.lhs.false.6
	    Live Ins: %X19
	    Predecessors according to CFG: BB#5
800B		%vreg29<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32common:%vreg29
816B		%WZR<def> = SUBSWri %vreg29<kill>, 9, 0, %NZCV<imp-def>; GPR32common:%vreg29
832B		Bcc 12, <BB#11>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#11 BB#7
> %W8<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3]
> %WZR<def> = SUBSWri %W8<kill>, 9, 0, %NZCV<imp-def>
> Bcc 12, <BB#11>, %NZCV<imp-use,kill>
848B	BB#7: derived from LLVM BB %lor.lhs.false.8
	    Live Ins: %X19
	    Predecessors according to CFG: BB#6
864B		%vreg31<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32:%vreg31
880B		TBNZW %vreg31<kill>, 31, <BB#11>; GPR32:%vreg31
	    Successors according to CFG: BB#11 BB#8
> %W8<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5]
> TBNZW %W8<kill>, 31, <BB#11>
896B	BB#8: derived from LLVM BB %lor.lhs.false.10
	    Live Ins: %X19
	    Predecessors according to CFG: BB#7
912B		%vreg33<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32common:%vreg33
928B		%WZR<def> = SUBSWri %vreg33<kill>, 250, 0, %NZCV<imp-def>; GPR32common:%vreg33
944B		Bcc 12, <BB#11>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#11 BB#9
> %W8<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5]
> %WZR<def> = SUBSWri %W8<kill>, 250, 0, %NZCV<imp-def>
> Bcc 12, <BB#11>, %NZCV<imp-use,kill>
960B	BB#9: derived from LLVM BB %lor.lhs.false.12
	    Live Ins: %X19
	    Predecessors according to CFG: BB#8
976B		%vreg35<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg35
992B		TBNZW %vreg35<kill>, 31, <BB#11>; GPR32:%vreg35
	    Successors according to CFG: BB#11 BB#10
> %W8<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4]
> TBNZW %W8<kill>, 31, <BB#11>
1008B	BB#10: derived from LLVM BB %lor.lhs.false.14
	    Live Ins: %X19
	    Predecessors according to CFG: BB#9
1024B		%vreg37<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32common:%vreg37
1040B		%WZR<def> = SUBSWri %vreg37<kill>, 4, 0, %NZCV<imp-def>; GPR32common:%vreg37
1056B		Bcc 13, <BB#16>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#16 BB#11
> %W8<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4]
> %WZR<def> = SUBSWri %W8<kill>, 4, 0, %NZCV<imp-def>
> Bcc 13, <BB#16>, %NZCV<imp-use,kill>
1072B	BB#11: derived from LLVM BB %if.then.16
	    Live Ins: %X19
	    Predecessors according to CFG: BB#4 BB#5 BB#6 BB#7 BB#8 BB#9 BB#10
1088B		%vreg148<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg148
1104B		CBZX %vreg148<kill>, <BB#13>; GPR64:%vreg148
	    Successors according to CFG: BB#13 BB#12
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> CBZX %X8<kill>, <BB#13>
1120B	BB#12: derived from LLVM BB %if.then.18
	    Live Ins: %X19
	    Predecessors according to CFG: BB#11
1152B		%vreg151<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg151
1160B		%vreg149<def> = MOVi32imm 4294967294; GPR32:%vreg149
1168B		STRWui %vreg149<kill>, %vreg151<kill>, 0; mem:ST4[%12] GPR32:%vreg149 GPR64common:%vreg151
	    Successors according to CFG: BB#13
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = MOVi32imm 4294967294
> STRWui %W9<kill>, %X8<kill>, 0; mem:ST4[%12]
1184B	BB#13: derived from LLVM BB %if.end.19
	    Live Ins: %X19
	    Predecessors according to CFG: BB#11 BB#12
1200B		%vreg153<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg153
1216B		CBZX %vreg153<kill>, <BB#15>; GPR64:%vreg153
	    Successors according to CFG: BB#15 BB#14
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> CBZX %X8<kill>, <BB#15>
1232B	BB#14: derived from LLVM BB %if.then.21
	    Live Ins: %X19
	    Predecessors according to CFG: BB#13
1264B		%vreg156<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg156
1272B		%vreg154<def> = MOVi32imm 4294967294; GPR32:%vreg154
1280B		STRWui %vreg154<kill>, %vreg156<kill>, 1274; mem:ST4[%lastErr22] GPR32:%vreg154 GPR64common:%vreg156
	    Successors according to CFG: BB#15
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> %W9<def> = MOVi32imm 4294967294
> STRWui %W9<kill>, %X8<kill>, 1274; mem:ST4[%lastErr22]
1296B	BB#15: derived from LLVM BB %if.end.23
	    Live Ins: %X19
	    Predecessors according to CFG: BB#13 BB#14
1328B		STRXui %XZR, <fi#0>, 0; mem:ST8[FixedStack0]
1344B		B <BB#41>
	    Successors according to CFG: BB#41
> STRXui %XZR, <fi#0>, 0; mem:ST8[FixedStack0]
> B <BB#41>
1360B	BB#16: derived from LLVM BB %if.end.24
	    Live Ins: %X19
	    Predecessors according to CFG: BB#10
1376B		%vreg41<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg41
1392B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1408B		%X0<def> = COPY %vreg41<kill>; GPR64:%vreg41
1424B		BL <ga:@ferror>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
1440B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1456B		%vreg40<def> = COPY %W0; GPR32:%vreg40
1472B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1488B		STACKMAP 1, 0, 0, <fi#3>, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#2>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4)
1504B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1520B		CBZW %vreg40<kill>, <BB#22>; GPR32:%vreg40
	    Successors according to CFG: BB#22 BB#17
> %X0<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BL <ga:@ferror>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = COPY %W0
Deleting identity copy.
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 1, 0, 0, <fi#3>, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#2>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> CBZW %W0<kill>, <BB#22>
1536B	BB#17: derived from LLVM BB %if.then.25
	    Live Ins: %X19
	    Predecessors according to CFG: BB#16
1552B		%vreg137<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg137
1568B		CBZX %vreg137<kill>, <BB#19>; GPR64:%vreg137
	    Successors according to CFG: BB#19 BB#18
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> CBZX %X8<kill>, <BB#19>
1584B	BB#18: derived from LLVM BB %if.then.27
	    Live Ins: %X19
	    Predecessors according to CFG: BB#17
1616B		%vreg140<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg140
1624B		%vreg138<def> = MOVi32imm 4294967290; GPR32:%vreg138
1632B		STRWui %vreg138<kill>, %vreg140<kill>, 0; mem:ST4[%17] GPR32:%vreg138 GPR64common:%vreg140
	    Successors according to CFG: BB#19
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = MOVi32imm 4294967290
> STRWui %W9<kill>, %X8<kill>, 0; mem:ST4[%17]
1648B	BB#19: derived from LLVM BB %if.end.28
	    Live Ins: %X19
	    Predecessors according to CFG: BB#17 BB#18
1664B		%vreg142<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg142
1680B		CBZX %vreg142<kill>, <BB#21>; GPR64:%vreg142
	    Successors according to CFG: BB#21 BB#20
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> CBZX %X8<kill>, <BB#21>
1696B	BB#20: derived from LLVM BB %if.then.30
	    Live Ins: %X19
	    Predecessors according to CFG: BB#19
1728B		%vreg145<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg145
1736B		%vreg143<def> = MOVi32imm 4294967290; GPR32:%vreg143
1744B		STRWui %vreg143<kill>, %vreg145<kill>, 1274; mem:ST4[%lastErr31] GPR32:%vreg143 GPR64common:%vreg145
	    Successors according to CFG: BB#21
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> %W9<def> = MOVi32imm 4294967290
> STRWui %W9<kill>, %X8<kill>, 1274; mem:ST4[%lastErr31]
1760B	BB#21: derived from LLVM BB %if.end.32
	    Live Ins: %X19
	    Predecessors according to CFG: BB#19 BB#20
1792B		STRXui %XZR, <fi#0>, 0; mem:ST8[FixedStack0]
1808B		B <BB#41>
	    Successors according to CFG: BB#41
> STRXui %XZR, <fi#0>, 0; mem:ST8[FixedStack0]
> B <BB#41>
1824B	BB#22: derived from LLVM BB %if.end.33
	    Live Ins: %X19
	    Predecessors according to CFG: BB#16
1856B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1872B		%X0<def> = MOVi64imm 5104
1888B		BL <ga:@malloc>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X0<imp-def>
1904B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1920B		%vreg46<def> = COPY %X0; GPR64:%vreg46
1936B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1952B		STACKMAP 2, 0, 0, <fi#3>, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#2>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4)
1968B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2000B		STRXui %vreg46<kill>, <fi#7>, 0; mem:ST8[FixedStack7] GPR64:%vreg46
2016B		%vreg43<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg43
2032B		CBNZX %vreg43<kill>, <BB#28>; GPR64:%vreg43
	    Successors according to CFG: BB#28 BB#23
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = MOVi64imm 5104
> BL <ga:@malloc>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0
Deleting identity copy.
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 2, 0, 0, <fi#3>, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#2>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRXui %X0<kill>, <fi#7>, 0; mem:ST8[FixedStack7]
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> CBNZX %X8<kill>, <BB#28>
2048B	BB#23: derived from LLVM BB %if.then.36
	    Live Ins: %X19
	    Predecessors according to CFG: BB#22
2064B		%vreg126<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg126
2080B		CBZX %vreg126<kill>, <BB#25>; GPR64:%vreg126
	    Successors according to CFG: BB#25 BB#24
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> CBZX %X8<kill>, <BB#25>
2096B	BB#24: derived from LLVM BB %if.then.38
	    Live Ins: %X19
	    Predecessors according to CFG: BB#23
2128B		%vreg129<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg129
2136B		%vreg127<def> = MOVi32imm 4294967293; GPR32:%vreg127
2144B		STRWui %vreg127<kill>, %vreg129<kill>, 0; mem:ST4[%23] GPR32:%vreg127 GPR64common:%vreg129
	    Successors according to CFG: BB#25
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = MOVi32imm 4294967293
> STRWui %W9<kill>, %X8<kill>, 0; mem:ST4[%23]
2160B	BB#25: derived from LLVM BB %if.end.39
	    Live Ins: %X19
	    Predecessors according to CFG: BB#23 BB#24
2176B		%vreg131<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg131
2192B		CBZX %vreg131<kill>, <BB#27>; GPR64:%vreg131
	    Successors according to CFG: BB#27 BB#26
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> CBZX %X8<kill>, <BB#27>
2208B	BB#26: derived from LLVM BB %if.then.41
	    Live Ins: %X19
	    Predecessors according to CFG: BB#25
2240B		%vreg134<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg134
2248B		%vreg132<def> = MOVi32imm 4294967293; GPR32:%vreg132
2256B		STRWui %vreg132<kill>, %vreg134<kill>, 1274; mem:ST4[%lastErr42] GPR32:%vreg132 GPR64common:%vreg134
	    Successors according to CFG: BB#27
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> %W9<def> = MOVi32imm 4294967293
> STRWui %W9<kill>, %X8<kill>, 1274; mem:ST4[%lastErr42]
2272B	BB#27: derived from LLVM BB %if.end.43
	    Live Ins: %X19
	    Predecessors according to CFG: BB#25 BB#26
2304B		STRXui %XZR, <fi#0>, 0; mem:ST8[FixedStack0]
2320B		B <BB#41>
	    Successors according to CFG: BB#41
> STRXui %XZR, <fi#0>, 0; mem:ST8[FixedStack0]
> B <BB#41>
2336B	BB#28: derived from LLVM BB %if.end.44
	    Live Ins: %X19
	    Predecessors according to CFG: BB#22
2352B		%vreg50<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg50
2368B		CBZX %vreg50<kill>, <BB#30>; GPR64:%vreg50
	    Successors according to CFG: BB#30 BB#29
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> CBZX %X8<kill>, <BB#30>
2384B	BB#29: derived from LLVM BB %if.then.46
	    Live Ins: %X19
	    Predecessors according to CFG: BB#28
2400B		%vreg52<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg52
2416B		STRWui %WZR, %vreg52<kill>, 0; mem:ST4[%27] GPR64common:%vreg52
	    Successors according to CFG: BB#30
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRWui %WZR, %X8<kill>, 0; mem:ST4[%27]
2432B	BB#30: derived from LLVM BB %if.end.47
	    Live Ins: %X19
	    Predecessors according to CFG: BB#28 BB#29
2448B		%vreg54<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg54
2464B		CBZX %vreg54<kill>, <BB#32>; GPR64:%vreg54
	    Successors according to CFG: BB#32 BB#31
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> CBZX %X8<kill>, <BB#32>
2480B	BB#31: derived from LLVM BB %if.then.49
	    Live Ins: %X19
	    Predecessors according to CFG: BB#30
2496B		%vreg56<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg56
2512B		STRWui %WZR, %vreg56<kill>, 1274; mem:ST4[%lastErr50] GPR64common:%vreg56
	    Successors according to CFG: BB#32
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> STRWui %WZR, %X8<kill>, 1274; mem:ST4[%lastErr50]
2528B	BB#32: derived from LLVM BB %if.end.51
	    Live Ins: %X19
	    Predecessors according to CFG: BB#30 BB#31
2576B		%vreg80<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg80
2592B		%vreg78<def> = MOVi64imm 5100; GPR64:%vreg78
2608B		%vreg79<def> = ADDXrr %vreg80<kill>, %vreg78<kill>; GPR64common:%vreg79 GPR64:%vreg80,%vreg78
2624B		STRBBui %WZR, %vreg79<kill>, 0; mem:ST1[%initialisedOk] GPR64common:%vreg79
2640B		%vreg76<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg76
2656B		STRWui %WZR, %vreg76<kill>, 1252; mem:ST4[%bufN] GPR64common:%vreg76
2672B		%vreg74<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg74
2688B		%vreg73<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg73
2704B		STRXui %vreg74<kill>, %vreg73<kill>, 0; mem:ST8[%handle] GPR64:%vreg74 GPR64common:%vreg73
2720B		%vreg70<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg70
2728B		%vreg66<def> = MOVi32imm 1; GPR32:%vreg66
2736B		%vreg68<def> = MOVi64imm 5012; GPR64:%vreg68
2752B		%vreg69<def> = ADDXrr %vreg70<kill>, %vreg68<kill>; GPR64common:%vreg69 GPR64:%vreg70,%vreg68
2768B		STRBBui %vreg66<kill>, %vreg69<kill>, 0; mem:ST1[%writing] GPR32:%vreg66 GPR64common:%vreg69
2784B		%vreg65<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg65
2800B		STRXui %XZR, %vreg65<kill>, 634; mem:ST8[%bzalloc] GPR64common:%vreg65
2816B		%vreg63<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg63
2832B		STRXui %XZR, %vreg63<kill>, 635; mem:ST8[%bzfree] GPR64common:%vreg63
2848B		%vreg61<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg61
2864B		STRXui %XZR, %vreg61<kill>, 636; mem:ST8[%opaque] GPR64common:%vreg61
2880B		%vreg58<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32:%vreg58
2896B		CBNZW %vreg58<kill>, <BB#34>; GPR32:%vreg58
	    Successors according to CFG: BB#34 BB#33
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> %X9<def> = MOVi64imm 5100
> %X8<def> = ADDXrr %X8<kill>, %X9<kill>
> STRBBui %WZR, %X8<kill>, 0; mem:ST1[%initialisedOk]
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> STRWui %WZR, %X8<kill>, 1252; mem:ST4[%bufN]
> %X8<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2]
> %X9<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> STRXui %X8<kill>, %X9<kill>, 0; mem:ST8[%handle]
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> %W9<def> = MOVi32imm 1
> %X10<def> = MOVi64imm 5012
> %X8<def> = ADDXrr %X8<kill>, %X10<kill>
> STRBBui %W9<kill>, %X8<kill>, 0; mem:ST1[%writing]
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> STRXui %XZR, %X8<kill>, 634; mem:ST8[%bzalloc]
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> STRXui %XZR, %X8<kill>, 635; mem:ST8[%bzfree]
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> STRXui %XZR, %X8<kill>, 636; mem:ST8[%opaque]
> %W8<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5]
> CBNZW %W8<kill>, <BB#34>
2912B	BB#33: derived from LLVM BB %if.then.55
	    Live Ins: %X19
	    Predecessors according to CFG: BB#32
2928B		%vreg81<def> = MOVi32imm 30; GPR32:%vreg81
2944B		STRWui %vreg81<kill>, <fi#5>, 0; mem:ST4[FixedStack5] GPR32:%vreg81
	    Successors according to CFG: BB#34
> %W8<def> = MOVi32imm 30
> STRWui %W8<kill>, <fi#5>, 0; mem:ST4[FixedStack5]
2960B	BB#34: derived from LLVM BB %if.end.56
	    Live Ins: %X19
	    Predecessors according to CFG: BB#32 BB#33
2976B		%vreg96<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg96
3024B		%vreg92<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg92
3040B		%vreg91<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg91
3056B		%vreg90<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32:%vreg90
3060B		%vreg94<def> = MOVi64imm 5016; GPR64:%vreg94
3064B		%vreg95<def> = ADDXrr %vreg96<kill>, %vreg94<kill>; GPR64:%vreg95,%vreg96,%vreg94
3072B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3088B		%X0<def> = COPY %vreg95<kill>; GPR64:%vreg95
3104B		%W1<def> = COPY %vreg92<kill>; GPR32:%vreg92
3120B		%W2<def> = COPY %vreg91<kill>; GPR32:%vreg91
3136B		%W3<def> = COPY %vreg90<kill>; GPR32:%vreg90
3152B		BL <ga:@BZ2_bzCompressInit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %W2<imp-use>, %W3<imp-use>, %W0<imp-def>
3168B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3184B		%vreg89<def> = COPY %W0; GPR32:%vreg89
3200B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3216B		STACKMAP 3, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack6](align=4) LD8[FixedStack0]
3232B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3248B		STRWui %vreg89<kill>, <fi#6>, 0; mem:ST4[FixedStack6] GPR32:%vreg89
3264B		%vreg83<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg83
3280B		CBZW %vreg83<kill>, <BB#40>; GPR32:%vreg83
	    Successors according to CFG: BB#40 BB#35
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> %W1<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3]
> %W2<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4]
> %W3<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5]
> %X9<def> = MOVi64imm 5016
> %X0<def> = ADDXrr %X8<kill>, %X9<kill>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %W1<def> = COPY %W1<kill>
Deleting identity copy.
> %W2<def> = COPY %W2<kill>
Deleting identity copy.
> %W3<def> = COPY %W3<kill>
Deleting identity copy.
> BL <ga:@BZ2_bzCompressInit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %W2<imp-use>, %W3<imp-use>, %W0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = COPY %W0
Deleting identity copy.
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 3, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack6](align=4) LD8[FixedStack0]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRWui %W0<kill>, <fi#6>, 0; mem:ST4[FixedStack6]
> %W8<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6]
> CBZW %W8<kill>, <BB#40>
3296B	BB#35: derived from LLVM BB %if.then.60
	    Live Ins: %X19
	    Predecessors according to CFG: BB#34
3312B		%vreg109<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg109
3328B		CBZX %vreg109<kill>, <BB#37>; GPR64:%vreg109
	    Successors according to CFG: BB#37 BB#36
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> CBZX %X8<kill>, <BB#37>
3344B	BB#36: derived from LLVM BB %if.then.62
	    Live Ins: %X19
	    Predecessors according to CFG: BB#35
3360B		%vreg113<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg113
3376B		%vreg112<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg112
3392B		STRWui %vreg113<kill>, %vreg112<kill>, 0; mem:ST4[%46] GPR32:%vreg113 GPR64common:%vreg112
	    Successors according to CFG: BB#37
> %W8<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRWui %W8<kill>, %X9<kill>, 0; mem:ST4[%46]
3408B	BB#37: derived from LLVM BB %if.end.63
	    Live Ins: %X19
	    Predecessors according to CFG: BB#35 BB#36
3424B		%vreg115<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg115
3440B		CBZX %vreg115<kill>, <BB#39>; GPR64:%vreg115
	    Successors according to CFG: BB#39 BB#38
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> CBZX %X8<kill>, <BB#39>
3456B	BB#38: derived from LLVM BB %if.then.65
	    Live Ins: %X19
	    Predecessors according to CFG: BB#37
3472B		%vreg119<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg119
3488B		%vreg118<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg118
3504B		STRWui %vreg119<kill>, %vreg118<kill>, 1274; mem:ST4[%lastErr66] GPR32:%vreg119 GPR64common:%vreg118
	    Successors according to CFG: BB#39
> %W8<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6]
> %X9<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> STRWui %W8<kill>, %X9<kill>, 1274; mem:ST4[%lastErr66]
3520B	BB#39: derived from LLVM BB %if.end.67
	    Live Ins: %X19
	    Predecessors according to CFG: BB#37 BB#38
3536B		%vreg123<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg123
3568B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3584B		%X0<def> = COPY %vreg123<kill>; GPR64:%vreg123
3600B		BL <ga:@free>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>
3616B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3648B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3664B		STACKMAP 4, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0]
3680B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3696B		STRXui %XZR, <fi#0>, 0; mem:ST8[FixedStack0]
3712B		B <BB#41>
	    Successors according to CFG: BB#41
> %X0<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BL <ga:@free>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 4, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRXui %XZR, <fi#0>, 0; mem:ST8[FixedStack0]
> B <BB#41>
3728B	BB#40: derived from LLVM BB %if.end.68
	    Live Ins: %X19
	    Predecessors according to CFG: BB#34
3760B		%vreg107<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg107
3776B		STRWui %WZR, %vreg107<kill>, 1256; mem:ST4[%avail_in] GPR64common:%vreg107
3792B		%vreg105<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg105
3800B		%vreg101<def> = MOVi32imm 1; GPR32:%vreg101
3808B		%vreg103<def> = MOVi64imm 5100; GPR64:%vreg103
3824B		%vreg104<def> = ADDXrr %vreg105<kill>, %vreg103<kill>; GPR64common:%vreg104 GPR64:%vreg105,%vreg103
3840B		STRBBui %vreg101<kill>, %vreg104<kill>, 0; mem:ST1[%initialisedOk70] GPR32:%vreg101 GPR64common:%vreg104
3856B		%vreg99<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg99
3888B		STRXui %vreg99<kill>, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg99
	    Successors according to CFG: BB#41
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> STRWui %WZR, %X8<kill>, 1256; mem:ST4[%avail_in]
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> %W9<def> = MOVi32imm 1
> %X10<def> = MOVi64imm 5100
> %X8<def> = ADDXrr %X8<kill>, %X10<kill>
> STRBBui %W9<kill>, %X8<kill>, 0; mem:ST1[%initialisedOk70]
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> STRXui %X8<kill>, <fi#0>, 0; mem:ST8[FixedStack0]
3904B	BB#41: derived from LLVM BB %return
	    Live Ins: %X19
	    Predecessors according to CFG: BB#40 BB#39 BB#27 BB#21 BB#15
3920B		%vreg160<def> = ADRP <ga:@BZ2_bzWriteOpen>[TF=1]; GPR64common:%vreg160
3936B		%vreg162<def> = ADDXri %vreg160<kill>, <ga:@BZ2_bzWriteOpen>[TF=34], 0; GPR64sp:%vreg162 GPR64common:%vreg160
3984B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4000B		%X0<def> = COPY %vreg162<kill>; GPR64sp:%vreg162
4016B		%X1<def> = COPY %vreg16<kill>; GPR64:%vreg16
4032B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
4048B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4064B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4080B		STACKMAP 5, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0]
4096B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4112B		%vreg159<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg159
4128B		%X0<def> = COPY %vreg159<kill>; GPR64:%vreg159
4144B		RET_ReallyLR %X0<imp-use>
> %X8<def> = ADRP <ga:@BZ2_bzWriteOpen>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@BZ2_bzWriteOpen>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19<kill>
> BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 5, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> RET_ReallyLR %X0<imp-use>
Computing live-in reg-units in ABI blocks.
0B	BB#0 W0#0 W1#0 W2#0 W3#0 W30#0
Created 5 new intervals.
********** INTERVALS **********
W30 [0B,16r:0)[272r,272d:12)[320e,320d:5)[1488r,1488d:11)[1552e,1552d:4)[2480r,2480d:10)[2544e,2544d:3)[3264r,3264d:9)[3328e,3328d:2)[3536r,3536d:8)[3600e,3600d:1)[4384r,4384d:6)[4432e,4432d:7)  0@0B-phi 1@3600e 2@3328e 3@2544e 4@1552e 5@320e 6@4384r 7@4432e 8@3536r 9@3264r 10@2480r 11@1488r 12@272r
W0 [0B,80r:0)[240r,272r:10)[1472r,1488r:9)[1488r,1520r:3)[2448r,2480r:8)[2480r,2512r:2)[3200r,3264r:7)[3264r,3296r:6)[3520r,3536r:5)[3536r,3568r:1)[4352r,4384r:4)  0@0B-phi 1@3536r 2@2480r 3@1488r 4@4352r 5@3520r 6@3264r 7@3200r 8@2448r 9@1472r 10@240r
W1 [0B,64r:0)[256r,272r:4)[2464r,2480r:1)[3216r,3264r:3)[4368r,4384r:2)  0@0B-phi 1@2464r 2@4368r 3@3216r 4@256r
W2 [0B,48r:0)[3232r,3264r:1)  0@0B-phi 1@3232r
W3 [0B,32r:0)[3248r,3264r:1)  0@0B-phi 1@3248r
%vreg0 [80r,96r:0)  0@80r
%vreg1 [96r,352r:0)  0@96r
%vreg2 [64r,112r:0)  0@64r
%vreg3 [112r,368r:0)  0@112r
%vreg4 [48r,128r:0)  0@48r
%vreg5 [128r,384r:0)  0@128r
%vreg6 [32r,144r:0)  0@32r
%vreg7 [144r,400r:0)  0@144r
%vreg9 [464r,480r:0)  0@464r
%vreg12 [432r,448r:0)  0@432r
%vreg13 [416r,432r:0)  0@416r
%vreg14 [160r,176r:0)  0@160r
%vreg15 [176r,192r:0)  0@176r
%vreg16 [192r,240r:0)  0@192r
%vreg17 [208r,256r:0)  0@208r
%vreg18 [16r,4320r:0)  0@16r
%vreg20 [512r,528r:0)  0@512r
%vreg22 [560r,576r:0)  0@560r
%vreg24 [608r,624r:0)  0@608r
%vreg26 [656r,672r:0)  0@656r
%vreg28 [704r,720r:0)  0@704r
%vreg30 [752r,768r:0)  0@752r
%vreg32 [1120r,1136r:0)  0@1120r
%vreg34 [1072r,1088r:0)  0@1072r
%vreg35 [1088r,1104r:0)  0@1088r
%vreg36 [1104r,1120r:0)  0@1104r
%vreg37 [1056r,1088r:0)  0@1056r
%vreg39 [1168r,1184r:0)  0@1168r
%vreg40 [1216r,1248r:0)  0@1216r
%vreg42 [1232r,1248r:0)  0@1232r
%vreg44 [1280r,1296r:0)  0@1280r
%vreg45 [1328r,1360r:0)  0@1328r
%vreg47 [1344r,1360r:0)  0@1344r
%vreg50 [1520r,1584r:0)  0@1520r
%vreg52 [1440r,1472r:0)  0@1440r
%vreg53 [1424r,1440r:0)  0@1424r
%vreg55 [1872r,1888r:0)  0@1872r
%vreg58 [2208r,2224r:0)  0@2208r
%vreg59 [2192r,2224r:0)  0@2192r
%vreg62 [2160r,2176r:0)  0@2160r
%vreg63 [2144r,2176r:0)  0@2144r
%vreg65 [2592r,2608r:0)  0@2592r
%vreg68 [2256r,2464r:0)  0@2256r
%vreg69 [2512r,2576r:0)  0@2512r
%vreg71 [2400r,2416r:0)  0@2400r
%vreg72 [2416r,2448r:0)  0@2416r
%vreg73 [2384r,2416r:0)  0@2384r
%vreg76 [2352r,2368r:0)  0@2352r
%vreg79 [2336r,2368r:0)  0@2336r
%vreg80 [2320r,2336r:0)  0@2320r
%vreg81 [2272r,2304r:0)  0@2272r
%vreg83 [2288r,2304r:0)  0@2288r
%vreg85 [2912r,2960r:0)  0@2912r
%vreg87 [2944r,2960r:0)  0@2944r
%vreg88 [2928r,2944r:0)  0@2928r
%vreg91 [3408r,3424r:0)  0@3408r
%vreg92 [3392r,3424r:0)  0@3392r
%vreg95 [3360r,3376r:0)  0@3360r
%vreg97 [3008r,3216r:0)  0@3008r
%vreg100 [3296r,3360r:0)  0@3296r
%vreg102 [3168r,3248r:0)  0@3168r
%vreg103 [3152r,3168r:0)  0@3152r
%vreg107 [3136r,3232r:0)  0@3136r
%vreg110 [3120r,3200r:0)  0@3120r
%vreg111 [3104r,3120r:0)  0@3104r
%vreg113 [3024r,3072r:0)  0@3024r
%vreg115 [3072r,3088r:0)  0@3072r
%vreg117 [3056r,3072r:0)  0@3056r
%vreg118 [3040r,3056r:0)  0@3040r
%vreg121 [3568r,3632r:0)  0@3568r
%vreg123 [3488r,3520r:0)  0@3488r
%vreg124 [3472r,3488r:0)  0@3472r
%vreg127 [3968r,3984r:0)  0@3968r
%vreg128 [3952r,3968r:0)  0@3952r
%vreg130 [4016r,4032r:0)  0@4016r
%vreg132 [4064r,4080r:0)  0@4064r
%vreg134 [4112r,4128r:0)  0@4112r
%vreg136 [4160r,4176r:0)  0@4160r
%vreg138 [3664r,3680r:0)  0@3664r
%vreg139 [3712r,3744r:0)  0@3712r
%vreg141 [3728r,3744r:0)  0@3728r
%vreg143 [3776r,3792r:0)  0@3776r
%vreg144 [3824r,3856r:0)  0@3824r
%vreg146 [3840r,3856r:0)  0@3840r
%vreg148 [2656r,2672r:0)  0@2656r
%vreg151 [2720r,2736r:0)  0@2720r
%vreg152 [2704r,2736r:0)  0@2704r
%vreg154 [2768r,2784r:0)  0@2768r
%vreg157 [2832r,2848r:0)  0@2832r
%vreg158 [2816r,2848r:0)  0@2816r
%vreg160 [1920r,1936r:0)  0@1920r
%vreg162 [1968r,1984r:0)  0@1968r
%vreg164 [2016r,2032r:0)  0@2016r
%vreg166 [2064r,2080r:0)  0@2064r
%vreg168 [1616r,1632r:0)  0@1616r
%vreg169 [1664r,1696r:0)  0@1664r
%vreg171 [1680r,1696r:0)  0@1680r
%vreg173 [1728r,1744r:0)  0@1728r
%vreg174 [1776r,1808r:0)  0@1776r
%vreg176 [1792r,1808r:0)  0@1792r
%vreg178 [800r,816r:0)  0@800r
%vreg179 [848r,880r:0)  0@848r
%vreg181 [864r,880r:0)  0@864r
%vreg183 [912r,928r:0)  0@912r
%vreg184 [960r,992r:0)  0@960r
%vreg186 [976r,992r:0)  0@976r
%vreg187 [4272r,4288r:0)  0@4272r
%vreg188 [4288r,4304r:0)  0@4288r
%vreg189 [4304r,4352r:0)  0@4304r
%vreg190 [4320r,4368r:0)  0@4320r
RegMasks: 272r 1488r 2480r 3264r 3536r 4384r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzWrite: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=8, align=8, at location [SP]
  fi#3: size=4, align=4, at location [SP]
  fi#4: size=4, align=4, at location [SP]
  fi#5: size=4, align=4, at location [SP]
  fi#6: size=4, align=4, at location [SP]
  fi#7: size=8, align=8, at location [SP]
Function Live Ins: %X0 in %vreg0, %X1 in %vreg2, %X2 in %vreg4, %W3 in %vreg6, %LR in %vreg18

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %X1 %X2 %W3 %LR
16B		%vreg18<def> = COPY %LR; GPR64:%vreg18
32B		%vreg6<def> = COPY %W3; GPR32:%vreg6
48B		%vreg4<def> = COPY %X2; GPR64:%vreg4
64B		%vreg2<def> = COPY %X1; GPR64:%vreg2
80B		%vreg0<def> = COPY %X0; GPR64:%vreg0
96B		%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
112B		%vreg3<def> = COPY %vreg2; GPR64:%vreg3,%vreg2
128B		%vreg5<def> = COPY %vreg4; GPR64:%vreg5,%vreg4
144B		%vreg7<def> = COPY %vreg6; GPR32:%vreg7,%vreg6
160B		%vreg14<def> = ADRP <ga:@BZ2_bzWrite>[TF=1]; GPR64common:%vreg14
176B		%vreg15<def> = ADDXri %vreg14, <ga:@BZ2_bzWrite>[TF=34], 0; GPR64sp:%vreg15 GPR64common:%vreg14
192B		%vreg16<def> = COPY %vreg15; GPR64all:%vreg16 GPR64sp:%vreg15
208B		%vreg17<def> = COPY %vreg18; GPR64all:%vreg17 GPR64:%vreg18
224B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
240B		%X0<def> = COPY %vreg16; GPR64all:%vreg16
256B		%X1<def> = COPY %vreg17; GPR64all:%vreg17
272B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
288B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
304B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
320B		STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg5, 0, <fi#2>, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#7>, 0, %vreg7, 0, <fi#3>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack0] LD8[FixedStack7] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) GPR64:%vreg3,%vreg5,%vreg1 GPR32:%vreg7
336B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
352B		STRXui %vreg1, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg1
368B		STRXui %vreg3, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg3
384B		STRXui %vreg5, <fi#2>, 0; mem:ST8[FixedStack2] GPR64:%vreg5
400B		STRWui %vreg7, <fi#3>, 0; mem:ST4[FixedStack3] GPR32:%vreg7
416B		%vreg13<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg13
432B		%vreg12<def> = COPY %vreg13; GPR64:%vreg12,%vreg13
448B		STRXui %vreg12, <fi#7>, 0; mem:ST8[FixedStack7] GPR64:%vreg12
464B		%vreg9<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg9
480B		CBZX %vreg9, <BB#2>; GPR64:%vreg9
	    Successors according to CFG: BB#2 BB#1

496B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
512B		%vreg20<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg20
528B		STRWui %WZR, %vreg20, 0; mem:ST4[%3] GPR64common:%vreg20
	    Successors according to CFG: BB#2

544B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#1
560B		%vreg22<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg22
576B		CBZX %vreg22, <BB#4>; GPR64:%vreg22
	    Successors according to CFG: BB#4 BB#3

592B	BB#3: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#2
608B		%vreg24<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg24
624B		STRWui %WZR, %vreg24, 1274; mem:ST4[%lastErr] GPR64common:%vreg24
	    Successors according to CFG: BB#4

640B	BB#4: derived from LLVM BB %if.end.3
	    Predecessors according to CFG: BB#2 BB#3
656B		%vreg26<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg26
672B		CBZX %vreg26, <BB#7>; GPR64:%vreg26
	    Successors according to CFG: BB#7 BB#5

688B	BB#5: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#4
704B		%vreg28<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg28
720B		CBZX %vreg28, <BB#7>; GPR64:%vreg28
	    Successors according to CFG: BB#7 BB#6

736B	BB#6: derived from LLVM BB %lor.lhs.false.6
	    Predecessors according to CFG: BB#5
752B		%vreg30<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg30
768B		TBZW %vreg30, 31, <BB#12>; GPR32:%vreg30
	    Successors according to CFG: BB#12 BB#7

784B	BB#7: derived from LLVM BB %if.then.8
	    Predecessors according to CFG: BB#4 BB#5 BB#6
800B		%vreg178<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg178
816B		CBZX %vreg178, <BB#9>; GPR64:%vreg178
	    Successors according to CFG: BB#9 BB#8

832B	BB#8: derived from LLVM BB %if.then.10
	    Predecessors according to CFG: BB#7
848B		%vreg179<def> = MOVi32imm 4294967294; GPR32:%vreg179
864B		%vreg181<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg181
880B		STRWui %vreg179, %vreg181, 0; mem:ST4[%10] GPR32:%vreg179 GPR64common:%vreg181
	    Successors according to CFG: BB#9

896B	BB#9: derived from LLVM BB %if.end.11
	    Predecessors according to CFG: BB#7 BB#8
912B		%vreg183<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg183
928B		CBZX %vreg183, <BB#11>; GPR64:%vreg183
	    Successors according to CFG: BB#11 BB#10

944B	BB#10: derived from LLVM BB %if.then.13
	    Predecessors according to CFG: BB#9
960B		%vreg184<def> = MOVi32imm 4294967294; GPR32:%vreg184
976B		%vreg186<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg186
992B		STRWui %vreg184, %vreg186, 1274; mem:ST4[%lastErr14] GPR32:%vreg184 GPR64common:%vreg186
	    Successors according to CFG: BB#11

1008B	BB#11: derived from LLVM BB %if.end.15
	    Predecessors according to CFG: BB#9 BB#10
1024B		B <BB#53>
	    Successors according to CFG: BB#53

1040B	BB#12: derived from LLVM BB %if.end.16
	    Predecessors according to CFG: BB#6
1056B		%vreg37<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg37
1072B		%vreg34<def> = MOVi64imm 5012; GPR64:%vreg34
1088B		%vreg35<def> = ADDXrr %vreg37, %vreg34; GPR64common:%vreg35 GPR64:%vreg37,%vreg34
1104B		%vreg36<def> = LDRBBui %vreg35, 0; mem:LD1[%writing] GPR32:%vreg36 GPR64common:%vreg35
1120B		%vreg32<def> = UBFMWri %vreg36, 0, 7; GPR32:%vreg32,%vreg36
1136B		CBNZW %vreg32, <BB#18>; GPR32:%vreg32
	    Successors according to CFG: BB#18 BB#13

1152B	BB#13: derived from LLVM BB %if.then.17
	    Predecessors according to CFG: BB#12
1168B		%vreg39<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg39
1184B		CBZX %vreg39, <BB#15>; GPR64:%vreg39
	    Successors according to CFG: BB#15 BB#14

1200B	BB#14: derived from LLVM BB %if.then.19
	    Predecessors according to CFG: BB#13
1216B		%vreg40<def> = MOVi32imm 4294967295; GPR32:%vreg40
1232B		%vreg42<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg42
1248B		STRWui %vreg40, %vreg42, 0; mem:ST4[%16] GPR32:%vreg40 GPR64common:%vreg42
	    Successors according to CFG: BB#15

1264B	BB#15: derived from LLVM BB %if.end.20
	    Predecessors according to CFG: BB#13 BB#14
1280B		%vreg44<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg44
1296B		CBZX %vreg44, <BB#17>; GPR64:%vreg44
	    Successors according to CFG: BB#17 BB#16

1312B	BB#16: derived from LLVM BB %if.then.22
	    Predecessors according to CFG: BB#15
1328B		%vreg45<def> = MOVi32imm 4294967295; GPR32:%vreg45
1344B		%vreg47<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg47
1360B		STRWui %vreg45, %vreg47, 1274; mem:ST4[%lastErr23] GPR32:%vreg45 GPR64common:%vreg47
	    Successors according to CFG: BB#17

1376B	BB#17: derived from LLVM BB %if.end.24
	    Predecessors according to CFG: BB#15 BB#16
1392B		B <BB#53>
	    Successors according to CFG: BB#53

1408B	BB#18: derived from LLVM BB %if.end.25
	    Predecessors according to CFG: BB#12
1424B		%vreg53<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg53
1440B		%vreg52<def> = LDRXui %vreg53, 0; mem:LD8[%handle] GPR64:%vreg52 GPR64common:%vreg53
1456B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1472B		%X0<def> = COPY %vreg52; GPR64:%vreg52
1488B		BL <ga:@ferror>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
1504B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1520B		%vreg50<def> = COPY %W0; GPR32:%vreg50
1536B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1552B		STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#7>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2] LD8[FixedStack0] LD8[FixedStack7] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4)
1568B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1584B		CBZW %vreg50, <BB#24>; GPR32:%vreg50
	    Successors according to CFG: BB#24 BB#19

1600B	BB#19: derived from LLVM BB %if.then.27
	    Predecessors according to CFG: BB#18
1616B		%vreg168<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg168
1632B		CBZX %vreg168, <BB#21>; GPR64:%vreg168
	    Successors according to CFG: BB#21 BB#20

1648B	BB#20: derived from LLVM BB %if.then.29
	    Predecessors according to CFG: BB#19
1664B		%vreg169<def> = MOVi32imm 4294967290; GPR32:%vreg169
1680B		%vreg171<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg171
1696B		STRWui %vreg169, %vreg171, 0; mem:ST4[%22] GPR32:%vreg169 GPR64common:%vreg171
	    Successors according to CFG: BB#21

1712B	BB#21: derived from LLVM BB %if.end.30
	    Predecessors according to CFG: BB#19 BB#20
1728B		%vreg173<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg173
1744B		CBZX %vreg173, <BB#23>; GPR64:%vreg173
	    Successors according to CFG: BB#23 BB#22

1760B	BB#22: derived from LLVM BB %if.then.32
	    Predecessors according to CFG: BB#21
1776B		%vreg174<def> = MOVi32imm 4294967290; GPR32:%vreg174
1792B		%vreg176<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg176
1808B		STRWui %vreg174, %vreg176, 1274; mem:ST4[%lastErr33] GPR32:%vreg174 GPR64common:%vreg176
	    Successors according to CFG: BB#23

1824B	BB#23: derived from LLVM BB %if.end.34
	    Predecessors according to CFG: BB#21 BB#22
1840B		B <BB#53>
	    Successors according to CFG: BB#53

1856B	BB#24: derived from LLVM BB %if.end.35
	    Predecessors according to CFG: BB#18
1872B		%vreg55<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg55
1888B		CBNZW %vreg55, <BB#30>; GPR32:%vreg55
	    Successors according to CFG: BB#30 BB#25

1904B	BB#25: derived from LLVM BB %if.then.37
	    Predecessors according to CFG: BB#24
1920B		%vreg160<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg160
1936B		CBZX %vreg160, <BB#27>; GPR64:%vreg160
	    Successors according to CFG: BB#27 BB#26

1952B	BB#26: derived from LLVM BB %if.then.39
	    Predecessors according to CFG: BB#25
1968B		%vreg162<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg162
1984B		STRWui %WZR, %vreg162, 0; mem:ST4[%27] GPR64common:%vreg162
	    Successors according to CFG: BB#27

2000B	BB#27: derived from LLVM BB %if.end.40
	    Predecessors according to CFG: BB#25 BB#26
2016B		%vreg164<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg164
2032B		CBZX %vreg164, <BB#29>; GPR64:%vreg164
	    Successors according to CFG: BB#29 BB#28

2048B	BB#28: derived from LLVM BB %if.then.42
	    Predecessors according to CFG: BB#27
2064B		%vreg166<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg166
2080B		STRWui %WZR, %vreg166, 1274; mem:ST4[%lastErr43] GPR64common:%vreg166
	    Successors according to CFG: BB#29

2096B	BB#29: derived from LLVM BB %if.end.44
	    Predecessors according to CFG: BB#27 BB#28
2112B		B <BB#53>
	    Successors according to CFG: BB#53

2128B	BB#30: derived from LLVM BB %if.end.45
	    Predecessors according to CFG: BB#24
2144B		%vreg63<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg63
2160B		%vreg62<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg62
2176B		STRWui %vreg63, %vreg62, 1256; mem:ST4[%avail_in] GPR32:%vreg63 GPR64common:%vreg62
2192B		%vreg59<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg59
2208B		%vreg58<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg58
2224B		STRXui %vreg59, %vreg58, 627; mem:ST8[%next_in] GPR64:%vreg59 GPR64common:%vreg58
	    Successors according to CFG: BB#31

2240B	BB#31: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#30 BB#52
2256B		%vreg68<def> = COPY %WZR; GPR32:%vreg68
2272B		%vreg81<def> = MOVi32imm 5000; GPR32:%vreg81
2288B		%vreg83<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg83
2304B		STRWui %vreg81, %vreg83, 1262; mem:ST4[%avail_out] GPR32:%vreg81 GPR64common:%vreg83
2320B		%vreg80<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg80
2336B		%vreg79<def> = ADDXri %vreg80, 8, 0; GPR64common:%vreg79,%vreg80
2352B		%vreg76<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg76
2368B		STRXui %vreg79, %vreg76, 630; mem:ST8[%next_out] GPR64common:%vreg79,%vreg76
2384B		%vreg73<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg73
2400B		%vreg71<def> = MOVi64imm 5016; GPR64:%vreg71
2416B		%vreg72<def> = ADDXrr %vreg73, %vreg71; GPR64:%vreg72,%vreg73,%vreg71
2432B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2448B		%X0<def> = COPY %vreg72; GPR64:%vreg72
2464B		%W1<def> = COPY %vreg68; GPR32:%vreg68
2480B		BL <ga:@BZ2_bzCompress>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %W0<imp-def>
2496B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2512B		%vreg69<def> = COPY %W0; GPR32:%vreg69
2528B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2544B		STACKMAP 2, 0, 0, <fi#0>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4)
2560B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2576B		STRWui %vreg69, <fi#6>, 0; mem:ST4[FixedStack6] GPR32:%vreg69
2592B		%vreg65<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32common:%vreg65
2608B		%WZR<def> = SUBSWri %vreg65, 1, 0, %NZCV<imp-def>; GPR32common:%vreg65
2624B		Bcc 0, <BB#37>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#37 BB#32

2640B	BB#32: derived from LLVM BB %if.then.53
	    Predecessors according to CFG: BB#31
2656B		%vreg148<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg148
2672B		CBZX %vreg148, <BB#34>; GPR64:%vreg148
	    Successors according to CFG: BB#34 BB#33

2688B	BB#33: derived from LLVM BB %if.then.55
	    Predecessors according to CFG: BB#32
2704B		%vreg152<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg152
2720B		%vreg151<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg151
2736B		STRWui %vreg152, %vreg151, 0; mem:ST4[%41] GPR32:%vreg152 GPR64common:%vreg151
	    Successors according to CFG: BB#34

2752B	BB#34: derived from LLVM BB %if.end.56
	    Predecessors according to CFG: BB#32 BB#33
2768B		%vreg154<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg154
2784B		CBZX %vreg154, <BB#36>; GPR64:%vreg154
	    Successors according to CFG: BB#36 BB#35

2800B	BB#35: derived from LLVM BB %if.then.58
	    Predecessors according to CFG: BB#34
2816B		%vreg158<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg158
2832B		%vreg157<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg157
2848B		STRWui %vreg158, %vreg157, 1274; mem:ST4[%lastErr59] GPR32:%vreg158 GPR64common:%vreg157
	    Successors according to CFG: BB#36

2864B	BB#36: derived from LLVM BB %if.end.60
	    Predecessors according to CFG: BB#34 BB#35
2880B		B <BB#53>
	    Successors according to CFG: BB#53

2896B	BB#37: derived from LLVM BB %if.end.61
	    Predecessors according to CFG: BB#31
2912B		%vreg85<def> = MOVi32imm 5000; GPR32:%vreg85
2928B		%vreg88<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg88
2944B		%vreg87<def> = LDRWui %vreg88, 1262; mem:LD4[%avail_out63] GPR32:%vreg87 GPR64common:%vreg88
2960B		%WZR<def> = SUBSWrr %vreg87, %vreg85, %NZCV<imp-def>; GPR32:%vreg87,%vreg85
2976B		Bcc 2, <BB#46>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#46 BB#38

2992B	BB#38: derived from LLVM BB %if.then.65
	    Predecessors according to CFG: BB#37
3008B		%vreg97<def> = MOVi64imm 1; GPR64:%vreg97
3024B		%vreg113<def> = MOVi32imm 5000; GPR32:%vreg113
3040B		%vreg118<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg118
3056B		%vreg117<def> = LDRWui %vreg118, 1262; mem:LD4[%avail_out67] GPR32:%vreg117 GPR64common:%vreg118
3072B		%vreg115<def> = SUBWrr %vreg113, %vreg117; GPR32:%vreg115,%vreg113,%vreg117
3088B		STRWui %vreg115, <fi#4>, 0; mem:ST4[FixedStack4] GPR32:%vreg115
3104B		%vreg111<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg111
3120B		%vreg110<def> = ADDXri %vreg111, 8, 0; GPR64sp:%vreg110 GPR64common:%vreg111
3136B		%vreg107<def> = LDRSWui <fi#4>, 0; mem:LD4[FixedStack4] GPR64:%vreg107
3152B		%vreg103<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg103
3168B		%vreg102<def> = LDRXui %vreg103, 0; mem:LD8[%handle70] GPR64:%vreg102 GPR64common:%vreg103
3184B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3200B		%X0<def> = COPY %vreg110; GPR64sp:%vreg110
3216B		%X1<def> = COPY %vreg97; GPR64:%vreg97
3232B		%X2<def> = COPY %vreg107; GPR64:%vreg107
3248B		%X3<def> = COPY %vreg102; GPR64:%vreg102
3264B		BL <ga:@fwrite>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %X2<imp-use>, %X3<imp-use>, %X0<imp-def>
3280B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3296B		%vreg100<def> = COPY %X0; GPR64all:%vreg100
3312B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3328B		STACKMAP 3, 0, 0, <fi#0>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4)
3344B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3360B		%vreg95<def> = COPY %vreg100:sub_32; GPR32:%vreg95 GPR64all:%vreg100
3376B		STRWui %vreg95, <fi#5>, 0; mem:ST4[FixedStack5] GPR32:%vreg95
3392B		%vreg92<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg92
3408B		%vreg91<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32:%vreg91
3424B		%WZR<def> = SUBSWrr %vreg92, %vreg91, %NZCV<imp-def>; GPR32:%vreg92,%vreg91
3440B		Bcc 1, <BB#40>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#40 BB#39

3456B	BB#39: derived from LLVM BB %lor.lhs.false.75
	    Predecessors according to CFG: BB#38
3472B		%vreg124<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg124
3488B		%vreg123<def> = LDRXui %vreg124, 0; mem:LD8[%handle76] GPR64:%vreg123 GPR64common:%vreg124
3504B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3520B		%X0<def> = COPY %vreg123; GPR64:%vreg123
3536B		BL <ga:@ferror>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
3552B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3568B		%vreg121<def> = COPY %W0; GPR32:%vreg121
3584B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3600B		STACKMAP 4, 0, 0, <fi#0>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4)
3616B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3632B		CBZW %vreg121, <BB#45>; GPR32:%vreg121
	    Successors according to CFG: BB#45 BB#40

3648B	BB#40: derived from LLVM BB %if.then.79
	    Predecessors according to CFG: BB#38 BB#39
3664B		%vreg138<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg138
3680B		CBZX %vreg138, <BB#42>; GPR64:%vreg138
	    Successors according to CFG: BB#42 BB#41

3696B	BB#41: derived from LLVM BB %if.then.82
	    Predecessors according to CFG: BB#40
3712B		%vreg139<def> = MOVi32imm 4294967290; GPR32:%vreg139
3728B		%vreg141<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg141
3744B		STRWui %vreg139, %vreg141, 0; mem:ST4[%58] GPR32:%vreg139 GPR64common:%vreg141
	    Successors according to CFG: BB#42

3760B	BB#42: derived from LLVM BB %if.end.83
	    Predecessors according to CFG: BB#40 BB#41
3776B		%vreg143<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg143
3792B		CBZX %vreg143, <BB#44>; GPR64:%vreg143
	    Successors according to CFG: BB#44 BB#43

3808B	BB#43: derived from LLVM BB %if.then.86
	    Predecessors according to CFG: BB#42
3824B		%vreg144<def> = MOVi32imm 4294967290; GPR32:%vreg144
3840B		%vreg146<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg146
3856B		STRWui %vreg144, %vreg146, 1274; mem:ST4[%lastErr87] GPR32:%vreg144 GPR64common:%vreg146
	    Successors according to CFG: BB#44

3872B	BB#44: derived from LLVM BB %if.end.88
	    Predecessors according to CFG: BB#42 BB#43
3888B		B <BB#53>
	    Successors according to CFG: BB#53

3904B	BB#45: derived from LLVM BB %if.end.89
	    Predecessors according to CFG: BB#39
3920B		B <BB#46>
	    Successors according to CFG: BB#46

3936B	BB#46: derived from LLVM BB %if.end.90
	    Predecessors according to CFG: BB#37 BB#45
3952B		%vreg128<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg128
3968B		%vreg127<def> = LDRWui %vreg128, 1256; mem:LD4[%avail_in92] GPR32:%vreg127 GPR64common:%vreg128
3984B		CBNZW %vreg127, <BB#52>; GPR32:%vreg127
	    Successors according to CFG: BB#52 BB#47

4000B	BB#47: derived from LLVM BB %if.then.95
	    Predecessors according to CFG: BB#46
4016B		%vreg130<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg130
4032B		CBZX %vreg130, <BB#49>; GPR64:%vreg130
	    Successors according to CFG: BB#49 BB#48

4048B	BB#48: derived from LLVM BB %if.then.98
	    Predecessors according to CFG: BB#47
4064B		%vreg132<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg132
4080B		STRWui %WZR, %vreg132, 0; mem:ST4[%64] GPR64common:%vreg132
	    Successors according to CFG: BB#49

4096B	BB#49: derived from LLVM BB %if.end.99
	    Predecessors according to CFG: BB#47 BB#48
4112B		%vreg134<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg134
4128B		CBZX %vreg134, <BB#51>; GPR64:%vreg134
	    Successors according to CFG: BB#51 BB#50

4144B	BB#50: derived from LLVM BB %if.then.102
	    Predecessors according to CFG: BB#49
4160B		%vreg136<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg136
4176B		STRWui %WZR, %vreg136, 1274; mem:ST4[%lastErr103] GPR64common:%vreg136
	    Successors according to CFG: BB#51

4192B	BB#51: derived from LLVM BB %if.end.104
	    Predecessors according to CFG: BB#49 BB#50
4208B		B <BB#53>
	    Successors according to CFG: BB#53

4224B	BB#52: derived from LLVM BB %if.end.105
	    Predecessors according to CFG: BB#46
4240B		B <BB#31>
	    Successors according to CFG: BB#31

4256B	BB#53: derived from LLVM BB %return
	    Predecessors according to CFG: BB#17 BB#51 BB#44 BB#36 BB#29 BB#23 BB#11
4272B		%vreg187<def> = ADRP <ga:@BZ2_bzWrite>[TF=1]; GPR64common:%vreg187
4288B		%vreg188<def> = ADDXri %vreg187, <ga:@BZ2_bzWrite>[TF=34], 0; GPR64sp:%vreg188 GPR64common:%vreg187
4304B		%vreg189<def> = COPY %vreg188; GPR64all:%vreg189 GPR64sp:%vreg188
4320B		%vreg190<def> = COPY %vreg18; GPR64all:%vreg190 GPR64:%vreg18
4336B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4352B		%X0<def> = COPY %vreg189; GPR64all:%vreg189
4368B		%X1<def> = COPY %vreg190; GPR64all:%vreg190
4384B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
4400B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4416B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4432B		STACKMAP 5, 0, %LR<earlyclobber,imp-def,dead>, ...
4448B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4464B		RET_ReallyLR

# End machine code for function BZ2_bzWrite.

********** SIMPLE REGISTER COALESCING **********
********** Function: BZ2_bzWrite
********** JOINING INTERVALS ***********
while.body:
2256B	%vreg68<def> = COPY %WZR; GPR32:%vreg68
	Considering merging %vreg68 with %WZR
		RHS = %vreg68 [2256r,2464r:0)  0@2256r
		updated: 2464B	%W1<def> = COPY %WZR
	Success: %vreg68 -> %WZR
	Result = %WZR
2448B	%X0<def> = COPY %vreg72; GPR64:%vreg72
	Considering merging %vreg72 with %X0
	Can only merge into reserved registers.
2464B	%W1<def> = COPY %WZR
	Not coalescable.
2512B	%vreg69<def> = COPY %W0; GPR32:%vreg69
	Considering merging %vreg69 with %W0
	Can only merge into reserved registers.
if.end.90:
if.end.61:
if.then.65:
3200B	%X0<def> = COPY %vreg110; GPR64sp:%vreg110
	Considering merging %vreg110 with %X0
	Can only merge into reserved registers.
3216B	%X1<def> = COPY %vreg97; GPR64:%vreg97
	Considering merging %vreg97 with %X1
	Can only merge into reserved registers.
Remat: %X1<def> = MOVi64imm 1
Shrink: %vreg97 [3008r,3216r:0)  0@3008r
All defs dead: 3008r	%vreg97<def,dead> = MOVi64imm 1; GPR64:%vreg97
Shrunk: %vreg97 [3008r,3008d:0)  0@3008r
Deleting dead def 3008r	%vreg97<def,dead> = MOVi64imm 1; GPR64:%vreg97
3232B	%X2<def> = COPY %vreg107; GPR64:%vreg107
	Considering merging %vreg107 with %X2
	Can only merge into reserved registers.
3248B	%X3<def> = COPY %vreg102; GPR64:%vreg102
	Considering merging %vreg102 with %X3
	Can only merge into reserved registers.
3296B	%vreg100<def> = COPY %X0; GPR64all:%vreg100
	Considering merging %vreg100 with %X0
	Can only merge into reserved registers.
lor.lhs.false.75:
3520B	%X0<def> = COPY %vreg123; GPR64:%vreg123
	Considering merging %vreg123 with %X0
	Can only merge into reserved registers.
3568B	%vreg121<def> = COPY %W0; GPR32:%vreg121
	Considering merging %vreg121 with %W0
	Can only merge into reserved registers.
if.end.89:
if.end.105:
3360B	%vreg95<def> = COPY %vreg100:sub_32; GPR32:%vreg95 GPR64all:%vreg100
	Considering merging to GPR64 with %vreg95 in %vreg100:sub_32
		RHS = %vreg95 [3360r,3376r:0)  0@3360r
		LHS = %vreg100 [3296r,3360r:0)  0@3296r
		merge %vreg95:0@3360r into %vreg100:0@3296r --> @3296r
		erased:	3360r	%vreg95<def> = COPY %vreg100:sub_32; GPR32:%vreg95 GPR64all:%vreg100
		updated: 3376B	STRWui %vreg100:sub_32, <fi#5>, 0; mem:ST4[FixedStack5] GPR64:%vreg100
	Success: %vreg95:sub_32 -> %vreg100
	Result = %vreg100 [3296r,3376r:0)  0@3296r
return:
4352B	%X0<def> = COPY %vreg189; GPR64all:%vreg189
	Considering merging %vreg189 with %X0
	Can only merge into reserved registers.
4368B	%X1<def> = COPY %vreg190; GPR64all:%vreg190
	Considering merging %vreg190 with %X1
	Can only merge into reserved registers.
if.then.8:
if.end:
if.end.3:
if.end.11:
if.end.20:
if.end.30:
if.end.40:
if.end.56:
if.then.79:
if.end.83:
if.end.99:
lor.lhs.false:
lor.lhs.false.6:
if.end.15:
if.end.16:
if.then.17:
if.end.24:
if.end.25:
1472B	%X0<def> = COPY %vreg52; GPR64:%vreg52
	Considering merging %vreg52 with %X0
	Can only merge into reserved registers.
1520B	%vreg50<def> = COPY %W0; GPR32:%vreg50
	Considering merging %vreg50 with %W0
	Can only merge into reserved registers.
if.then.27:
if.end.34:
if.end.35:
if.then.37:
if.end.44:
if.then.53:
if.end.60:
if.end.88:
if.then.95:
if.end.104:
entry:
16B	%vreg18<def> = COPY %LR; GPR64:%vreg18
	Considering merging %vreg18 with %LR
	Can only merge into reserved registers.
32B	%vreg6<def> = COPY %W3; GPR32:%vreg6
	Considering merging %vreg6 with %W3
	Can only merge into reserved registers.
48B	%vreg4<def> = COPY %X2; GPR64:%vreg4
	Considering merging %vreg4 with %X2
	Can only merge into reserved registers.
64B	%vreg2<def> = COPY %X1; GPR64:%vreg2
	Considering merging %vreg2 with %X1
	Can only merge into reserved registers.
80B	%vreg0<def> = COPY %X0; GPR64:%vreg0
	Considering merging %vreg0 with %X0
	Can only merge into reserved registers.
240B	%X0<def> = COPY %vreg16; GPR64all:%vreg16
	Considering merging %vreg16 with %X0
	Can only merge into reserved registers.
256B	%X1<def> = COPY %vreg17; GPR64all:%vreg17
	Considering merging %vreg17 with %X1
	Can only merge into reserved registers.
if.then:
if.then.2:
if.then.10:
if.then.13:
if.then.19:
if.then.22:
if.then.29:
if.then.32:
if.then.39:
if.then.42:
if.end.45:
if.then.55:
if.then.58:
if.then.82:
if.then.86:
if.then.98:
if.then.102:
4304B	%vreg189<def> = COPY %vreg188; GPR64all:%vreg189 GPR64sp:%vreg188
	Considering merging to GPR64sp with %vreg188 in %vreg189
		RHS = %vreg188 [4288r,4304r:0)  0@4288r
		LHS = %vreg189 [4304r,4352r:0)  0@4304r
		merge %vreg189:0@4304r into %vreg188:0@4288r --> @4288r
		erased:	4304r	%vreg189<def> = COPY %vreg188; GPR64all:%vreg189 GPR64sp:%vreg188
		updated: 4288B	%vreg189<def> = ADDXri %vreg187, <ga:@BZ2_bzWrite>[TF=34], 0; GPR64sp:%vreg189 GPR64common:%vreg187
	Success: %vreg188 -> %vreg189
	Result = %vreg189 [4288r,4352r:0)  0@4288r
4320B	%vreg190<def> = COPY %vreg18; GPR64all:%vreg190 GPR64:%vreg18
	Considering merging to GPR64 with %vreg18 in %vreg190
		RHS = %vreg18 [16r,4320r:0)  0@16r
		LHS = %vreg190 [4320r,4368r:0)  0@4320r
		merge %vreg190:0@4320r into %vreg18:0@16r --> @16r
		erased:	4320r	%vreg190<def> = COPY %vreg18; GPR64all:%vreg190 GPR64:%vreg18
		updated: 16B	%vreg190<def> = COPY %LR; GPR64:%vreg190
		updated: 208B	%vreg17<def> = COPY %vreg190; GPR64all:%vreg17 GPR64:%vreg190
	Success: %vreg18 -> %vreg190
	Result = %vreg190 [16r,4368r:0)  0@16r
96B	%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
	Considering merging to GPR64 with %vreg0 in %vreg1
		RHS = %vreg0 [80r,96r:0)  0@80r
		LHS = %vreg1 [96r,352r:0)  0@96r
		merge %vreg1:0@96r into %vreg0:0@80r --> @80r
		erased:	96r	%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
		updated: 80B	%vreg1<def> = COPY %X0; GPR64:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [80r,352r:0)  0@80r
112B	%vreg3<def> = COPY %vreg2; GPR64:%vreg3,%vreg2
	Considering merging to GPR64 with %vreg2 in %vreg3
		RHS = %vreg2 [64r,112r:0)  0@64r
		LHS = %vreg3 [112r,368r:0)  0@112r
		merge %vreg3:0@112r into %vreg2:0@64r --> @64r
		erased:	112r	%vreg3<def> = COPY %vreg2; GPR64:%vreg3,%vreg2
		updated: 64B	%vreg3<def> = COPY %X1; GPR64:%vreg3
	Success: %vreg2 -> %vreg3
	Result = %vreg3 [64r,368r:0)  0@64r
128B	%vreg5<def> = COPY %vreg4; GPR64:%vreg5,%vreg4
	Considering merging to GPR64 with %vreg4 in %vreg5
		RHS = %vreg4 [48r,128r:0)  0@48r
		LHS = %vreg5 [128r,384r:0)  0@128r
		merge %vreg5:0@128r into %vreg4:0@48r --> @48r
		erased:	128r	%vreg5<def> = COPY %vreg4; GPR64:%vreg5,%vreg4
		updated: 48B	%vreg5<def> = COPY %X2; GPR64:%vreg5
	Success: %vreg4 -> %vreg5
	Result = %vreg5 [48r,384r:0)  0@48r
144B	%vreg7<def> = COPY %vreg6; GPR32:%vreg7,%vreg6
	Considering merging to GPR32 with %vreg6 in %vreg7
		RHS = %vreg6 [32r,144r:0)  0@32r
		LHS = %vreg7 [144r,400r:0)  0@144r
		merge %vreg7:0@144r into %vreg6:0@32r --> @32r
		erased:	144r	%vreg7<def> = COPY %vreg6; GPR32:%vreg7,%vreg6
		updated: 32B	%vreg7<def> = COPY %W3; GPR32:%vreg7
	Success: %vreg6 -> %vreg7
	Result = %vreg7 [32r,400r:0)  0@32r
192B	%vreg16<def> = COPY %vreg15; GPR64all:%vreg16 GPR64sp:%vreg15
	Considering merging to GPR64sp with %vreg15 in %vreg16
		RHS = %vreg15 [176r,192r:0)  0@176r
		LHS = %vreg16 [192r,240r:0)  0@192r
		merge %vreg16:0@192r into %vreg15:0@176r --> @176r
		erased:	192r	%vreg16<def> = COPY %vreg15; GPR64all:%vreg16 GPR64sp:%vreg15
		updated: 176B	%vreg16<def> = ADDXri %vreg14, <ga:@BZ2_bzWrite>[TF=34], 0; GPR64sp:%vreg16 GPR64common:%vreg14
	Success: %vreg15 -> %vreg16
	Result = %vreg16 [176r,240r:0)  0@176r
208B	%vreg17<def> = COPY %vreg190; GPR64all:%vreg17 GPR64:%vreg190
	Considering merging to GPR64 with %vreg190 in %vreg17
		RHS = %vreg190 [16r,4368r:0)  0@16r
		LHS = %vreg17 [208r,256r:0)  0@208r
		merge %vreg17:0@208r into %vreg190:0@16r --> @16r
		erased:	208r	%vreg17<def> = COPY %vreg190; GPR64all:%vreg17 GPR64:%vreg190
		updated: 16B	%vreg17<def> = COPY %LR; GPR64:%vreg17
		updated: 4368B	%X1<def> = COPY %vreg17; GPR64:%vreg17
	Success: %vreg190 -> %vreg17
	Result = %vreg17 [16r,4368r:0)  0@16r
432B	%vreg12<def> = COPY %vreg13; GPR64:%vreg12,%vreg13
	Considering merging to GPR64 with %vreg13 in %vreg12
		RHS = %vreg13 [416r,432r:0)  0@416r
		LHS = %vreg12 [432r,448r:0)  0@432r
		merge %vreg12:0@432r into %vreg13:0@416r --> @416r
		erased:	432r	%vreg12<def> = COPY %vreg13; GPR64:%vreg12,%vreg13
		updated: 416B	%vreg12<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg12
	Success: %vreg13 -> %vreg12
	Result = %vreg12 [416r,448r:0)  0@416r
4352B	%X0<def> = COPY %vreg189; GPR64sp:%vreg189
	Considering merging %vreg189 with %X0
	Can only merge into reserved registers.
4368B	%X1<def> = COPY %vreg17; GPR64:%vreg17
	Considering merging %vreg17 with %X1
	Can only merge into reserved registers.
240B	%X0<def> = COPY %vreg16; GPR64sp:%vreg16
	Considering merging %vreg16 with %X0
	Can only merge into reserved registers.
256B	%X1<def> = COPY %vreg17; GPR64:%vreg17
	Considering merging %vreg17 with %X1
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
W30 [0B,16r:0)[272r,272d:12)[320e,320d:5)[1488r,1488d:11)[1552e,1552d:4)[2480r,2480d:10)[2544e,2544d:3)[3264r,3264d:9)[3328e,3328d:2)[3536r,3536d:8)[3600e,3600d:1)[4384r,4384d:6)[4432e,4432d:7)  0@0B-phi 1@3600e 2@3328e 3@2544e 4@1552e 5@320e 6@4384r 7@4432e 8@3536r 9@3264r 10@2480r 11@1488r 12@272r
WZR [2608r,2608d:2)[2960r,2960d:1)[3424r,3424d:0)  0@3424r 1@2960r 2@2608r
W0 [0B,80r:0)[240r,272r:10)[1472r,1488r:9)[1488r,1520r:3)[2448r,2480r:8)[2480r,2512r:2)[3200r,3264r:7)[3264r,3296r:6)[3520r,3536r:5)[3536r,3568r:1)[4352r,4384r:4)  0@0B-phi 1@3536r 2@2480r 3@1488r 4@4352r 5@3520r 6@3264r 7@3200r 8@2448r 9@1472r 10@240r
W1 [0B,64r:0)[256r,272r:4)[2464r,2480r:1)[3216r,3264r:3)[4368r,4384r:2)  0@0B-phi 1@2464r 2@4368r 3@3216r 4@256r
W2 [0B,48r:0)[3232r,3264r:1)  0@0B-phi 1@3232r
W3 [0B,32r:0)[3248r,3264r:1)  0@0B-phi 1@3248r
%vreg1 [80r,352r:0)  0@80r
%vreg3 [64r,368r:0)  0@64r
%vreg5 [48r,384r:0)  0@48r
%vreg7 [32r,400r:0)  0@32r
%vreg9 [464r,480r:0)  0@464r
%vreg12 [416r,448r:0)  0@416r
%vreg14 [160r,176r:0)  0@160r
%vreg16 [176r,240r:0)  0@176r
%vreg17 [16r,4368r:0)  0@16r
%vreg20 [512r,528r:0)  0@512r
%vreg22 [560r,576r:0)  0@560r
%vreg24 [608r,624r:0)  0@608r
%vreg26 [656r,672r:0)  0@656r
%vreg28 [704r,720r:0)  0@704r
%vreg30 [752r,768r:0)  0@752r
%vreg32 [1120r,1136r:0)  0@1120r
%vreg34 [1072r,1088r:0)  0@1072r
%vreg35 [1088r,1104r:0)  0@1088r
%vreg36 [1104r,1120r:0)  0@1104r
%vreg37 [1056r,1088r:0)  0@1056r
%vreg39 [1168r,1184r:0)  0@1168r
%vreg40 [1216r,1248r:0)  0@1216r
%vreg42 [1232r,1248r:0)  0@1232r
%vreg44 [1280r,1296r:0)  0@1280r
%vreg45 [1328r,1360r:0)  0@1328r
%vreg47 [1344r,1360r:0)  0@1344r
%vreg50 [1520r,1584r:0)  0@1520r
%vreg52 [1440r,1472r:0)  0@1440r
%vreg53 [1424r,1440r:0)  0@1424r
%vreg55 [1872r,1888r:0)  0@1872r
%vreg58 [2208r,2224r:0)  0@2208r
%vreg59 [2192r,2224r:0)  0@2192r
%vreg62 [2160r,2176r:0)  0@2160r
%vreg63 [2144r,2176r:0)  0@2144r
%vreg65 [2592r,2608r:0)  0@2592r
%vreg69 [2512r,2576r:0)  0@2512r
%vreg71 [2400r,2416r:0)  0@2400r
%vreg72 [2416r,2448r:0)  0@2416r
%vreg73 [2384r,2416r:0)  0@2384r
%vreg76 [2352r,2368r:0)  0@2352r
%vreg79 [2336r,2368r:0)  0@2336r
%vreg80 [2320r,2336r:0)  0@2320r
%vreg81 [2272r,2304r:0)  0@2272r
%vreg83 [2288r,2304r:0)  0@2288r
%vreg85 [2912r,2960r:0)  0@2912r
%vreg87 [2944r,2960r:0)  0@2944r
%vreg88 [2928r,2944r:0)  0@2928r
%vreg91 [3408r,3424r:0)  0@3408r
%vreg92 [3392r,3424r:0)  0@3392r
%vreg100 [3296r,3376r:0)  0@3296r
%vreg102 [3168r,3248r:0)  0@3168r
%vreg103 [3152r,3168r:0)  0@3152r
%vreg107 [3136r,3232r:0)  0@3136r
%vreg110 [3120r,3200r:0)  0@3120r
%vreg111 [3104r,3120r:0)  0@3104r
%vreg113 [3024r,3072r:0)  0@3024r
%vreg115 [3072r,3088r:0)  0@3072r
%vreg117 [3056r,3072r:0)  0@3056r
%vreg118 [3040r,3056r:0)  0@3040r
%vreg121 [3568r,3632r:0)  0@3568r
%vreg123 [3488r,3520r:0)  0@3488r
%vreg124 [3472r,3488r:0)  0@3472r
%vreg127 [3968r,3984r:0)  0@3968r
%vreg128 [3952r,3968r:0)  0@3952r
%vreg130 [4016r,4032r:0)  0@4016r
%vreg132 [4064r,4080r:0)  0@4064r
%vreg134 [4112r,4128r:0)  0@4112r
%vreg136 [4160r,4176r:0)  0@4160r
%vreg138 [3664r,3680r:0)  0@3664r
%vreg139 [3712r,3744r:0)  0@3712r
%vreg141 [3728r,3744r:0)  0@3728r
%vreg143 [3776r,3792r:0)  0@3776r
%vreg144 [3824r,3856r:0)  0@3824r
%vreg146 [3840r,3856r:0)  0@3840r
%vreg148 [2656r,2672r:0)  0@2656r
%vreg151 [2720r,2736r:0)  0@2720r
%vreg152 [2704r,2736r:0)  0@2704r
%vreg154 [2768r,2784r:0)  0@2768r
%vreg157 [2832r,2848r:0)  0@2832r
%vreg158 [2816r,2848r:0)  0@2816r
%vreg160 [1920r,1936r:0)  0@1920r
%vreg162 [1968r,1984r:0)  0@1968r
%vreg164 [2016r,2032r:0)  0@2016r
%vreg166 [2064r,2080r:0)  0@2064r
%vreg168 [1616r,1632r:0)  0@1616r
%vreg169 [1664r,1696r:0)  0@1664r
%vreg171 [1680r,1696r:0)  0@1680r
%vreg173 [1728r,1744r:0)  0@1728r
%vreg174 [1776r,1808r:0)  0@1776r
%vreg176 [1792r,1808r:0)  0@1792r
%vreg178 [800r,816r:0)  0@800r
%vreg179 [848r,880r:0)  0@848r
%vreg181 [864r,880r:0)  0@864r
%vreg183 [912r,928r:0)  0@912r
%vreg184 [960r,992r:0)  0@960r
%vreg186 [976r,992r:0)  0@976r
%vreg187 [4272r,4288r:0)  0@4272r
%vreg189 [4288r,4352r:0)  0@4288r
RegMasks: 272r 1488r 2480r 3264r 3536r 4384r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzWrite: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=8, align=8, at location [SP]
  fi#3: size=4, align=4, at location [SP]
  fi#4: size=4, align=4, at location [SP]
  fi#5: size=4, align=4, at location [SP]
  fi#6: size=4, align=4, at location [SP]
  fi#7: size=8, align=8, at location [SP]
Function Live Ins: %X0 in %vreg0, %X1 in %vreg2, %X2 in %vreg4, %W3 in %vreg6, %LR in %vreg18

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %X1 %X2 %W3 %LR
16B		%vreg17<def> = COPY %LR; GPR64:%vreg17
32B		%vreg7<def> = COPY %W3; GPR32:%vreg7
48B		%vreg5<def> = COPY %X2; GPR64:%vreg5
64B		%vreg3<def> = COPY %X1; GPR64:%vreg3
80B		%vreg1<def> = COPY %X0; GPR64:%vreg1
160B		%vreg14<def> = ADRP <ga:@BZ2_bzWrite>[TF=1]; GPR64common:%vreg14
176B		%vreg16<def> = ADDXri %vreg14, <ga:@BZ2_bzWrite>[TF=34], 0; GPR64sp:%vreg16 GPR64common:%vreg14
224B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
240B		%X0<def> = COPY %vreg16; GPR64sp:%vreg16
256B		%X1<def> = COPY %vreg17; GPR64:%vreg17
272B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
288B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
304B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
320B		STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg5, 0, <fi#2>, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#7>, 0, %vreg7, 0, <fi#3>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack0] LD8[FixedStack7] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) GPR64:%vreg3,%vreg5,%vreg1 GPR32:%vreg7
336B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
352B		STRXui %vreg1, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg1
368B		STRXui %vreg3, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg3
384B		STRXui %vreg5, <fi#2>, 0; mem:ST8[FixedStack2] GPR64:%vreg5
400B		STRWui %vreg7, <fi#3>, 0; mem:ST4[FixedStack3] GPR32:%vreg7
416B		%vreg12<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg12
448B		STRXui %vreg12, <fi#7>, 0; mem:ST8[FixedStack7] GPR64:%vreg12
464B		%vreg9<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg9
480B		CBZX %vreg9, <BB#2>; GPR64:%vreg9
	    Successors according to CFG: BB#2 BB#1

496B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
512B		%vreg20<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg20
528B		STRWui %WZR, %vreg20, 0; mem:ST4[%3] GPR64common:%vreg20
	    Successors according to CFG: BB#2

544B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#1
560B		%vreg22<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg22
576B		CBZX %vreg22, <BB#4>; GPR64:%vreg22
	    Successors according to CFG: BB#4 BB#3

592B	BB#3: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#2
608B		%vreg24<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg24
624B		STRWui %WZR, %vreg24, 1274; mem:ST4[%lastErr] GPR64common:%vreg24
	    Successors according to CFG: BB#4

640B	BB#4: derived from LLVM BB %if.end.3
	    Predecessors according to CFG: BB#2 BB#3
656B		%vreg26<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg26
672B		CBZX %vreg26, <BB#7>; GPR64:%vreg26
	    Successors according to CFG: BB#7 BB#5

688B	BB#5: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#4
704B		%vreg28<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg28
720B		CBZX %vreg28, <BB#7>; GPR64:%vreg28
	    Successors according to CFG: BB#7 BB#6

736B	BB#6: derived from LLVM BB %lor.lhs.false.6
	    Predecessors according to CFG: BB#5
752B		%vreg30<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg30
768B		TBZW %vreg30, 31, <BB#12>; GPR32:%vreg30
	    Successors according to CFG: BB#12 BB#7

784B	BB#7: derived from LLVM BB %if.then.8
	    Predecessors according to CFG: BB#4 BB#5 BB#6
800B		%vreg178<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg178
816B		CBZX %vreg178, <BB#9>; GPR64:%vreg178
	    Successors according to CFG: BB#9 BB#8

832B	BB#8: derived from LLVM BB %if.then.10
	    Predecessors according to CFG: BB#7
848B		%vreg179<def> = MOVi32imm 4294967294; GPR32:%vreg179
864B		%vreg181<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg181
880B		STRWui %vreg179, %vreg181, 0; mem:ST4[%10] GPR32:%vreg179 GPR64common:%vreg181
	    Successors according to CFG: BB#9

896B	BB#9: derived from LLVM BB %if.end.11
	    Predecessors according to CFG: BB#7 BB#8
912B		%vreg183<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg183
928B		CBZX %vreg183, <BB#11>; GPR64:%vreg183
	    Successors according to CFG: BB#11 BB#10

944B	BB#10: derived from LLVM BB %if.then.13
	    Predecessors according to CFG: BB#9
960B		%vreg184<def> = MOVi32imm 4294967294; GPR32:%vreg184
976B		%vreg186<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg186
992B		STRWui %vreg184, %vreg186, 1274; mem:ST4[%lastErr14] GPR32:%vreg184 GPR64common:%vreg186
	    Successors according to CFG: BB#11

1008B	BB#11: derived from LLVM BB %if.end.15
	    Predecessors according to CFG: BB#9 BB#10
1024B		B <BB#53>
	    Successors according to CFG: BB#53

1040B	BB#12: derived from LLVM BB %if.end.16
	    Predecessors according to CFG: BB#6
1056B		%vreg37<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg37
1072B		%vreg34<def> = MOVi64imm 5012; GPR64:%vreg34
1088B		%vreg35<def> = ADDXrr %vreg37, %vreg34; GPR64common:%vreg35 GPR64:%vreg37,%vreg34
1104B		%vreg36<def> = LDRBBui %vreg35, 0; mem:LD1[%writing] GPR32:%vreg36 GPR64common:%vreg35
1120B		%vreg32<def> = UBFMWri %vreg36, 0, 7; GPR32:%vreg32,%vreg36
1136B		CBNZW %vreg32, <BB#18>; GPR32:%vreg32
	    Successors according to CFG: BB#18 BB#13

1152B	BB#13: derived from LLVM BB %if.then.17
	    Predecessors according to CFG: BB#12
1168B		%vreg39<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg39
1184B		CBZX %vreg39, <BB#15>; GPR64:%vreg39
	    Successors according to CFG: BB#15 BB#14

1200B	BB#14: derived from LLVM BB %if.then.19
	    Predecessors according to CFG: BB#13
1216B		%vreg40<def> = MOVi32imm 4294967295; GPR32:%vreg40
1232B		%vreg42<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg42
1248B		STRWui %vreg40, %vreg42, 0; mem:ST4[%16] GPR32:%vreg40 GPR64common:%vreg42
	    Successors according to CFG: BB#15

1264B	BB#15: derived from LLVM BB %if.end.20
	    Predecessors according to CFG: BB#13 BB#14
1280B		%vreg44<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg44
1296B		CBZX %vreg44, <BB#17>; GPR64:%vreg44
	    Successors according to CFG: BB#17 BB#16

1312B	BB#16: derived from LLVM BB %if.then.22
	    Predecessors according to CFG: BB#15
1328B		%vreg45<def> = MOVi32imm 4294967295; GPR32:%vreg45
1344B		%vreg47<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg47
1360B		STRWui %vreg45, %vreg47, 1274; mem:ST4[%lastErr23] GPR32:%vreg45 GPR64common:%vreg47
	    Successors according to CFG: BB#17

1376B	BB#17: derived from LLVM BB %if.end.24
	    Predecessors according to CFG: BB#15 BB#16
1392B		B <BB#53>
	    Successors according to CFG: BB#53

1408B	BB#18: derived from LLVM BB %if.end.25
	    Predecessors according to CFG: BB#12
1424B		%vreg53<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg53
1440B		%vreg52<def> = LDRXui %vreg53, 0; mem:LD8[%handle] GPR64:%vreg52 GPR64common:%vreg53
1456B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1472B		%X0<def> = COPY %vreg52; GPR64:%vreg52
1488B		BL <ga:@ferror>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
1504B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1520B		%vreg50<def> = COPY %W0; GPR32:%vreg50
1536B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1552B		STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#7>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2] LD8[FixedStack0] LD8[FixedStack7] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4)
1568B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1584B		CBZW %vreg50, <BB#24>; GPR32:%vreg50
	    Successors according to CFG: BB#24 BB#19

1600B	BB#19: derived from LLVM BB %if.then.27
	    Predecessors according to CFG: BB#18
1616B		%vreg168<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg168
1632B		CBZX %vreg168, <BB#21>; GPR64:%vreg168
	    Successors according to CFG: BB#21 BB#20

1648B	BB#20: derived from LLVM BB %if.then.29
	    Predecessors according to CFG: BB#19
1664B		%vreg169<def> = MOVi32imm 4294967290; GPR32:%vreg169
1680B		%vreg171<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg171
1696B		STRWui %vreg169, %vreg171, 0; mem:ST4[%22] GPR32:%vreg169 GPR64common:%vreg171
	    Successors according to CFG: BB#21

1712B	BB#21: derived from LLVM BB %if.end.30
	    Predecessors according to CFG: BB#19 BB#20
1728B		%vreg173<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg173
1744B		CBZX %vreg173, <BB#23>; GPR64:%vreg173
	    Successors according to CFG: BB#23 BB#22

1760B	BB#22: derived from LLVM BB %if.then.32
	    Predecessors according to CFG: BB#21
1776B		%vreg174<def> = MOVi32imm 4294967290; GPR32:%vreg174
1792B		%vreg176<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg176
1808B		STRWui %vreg174, %vreg176, 1274; mem:ST4[%lastErr33] GPR32:%vreg174 GPR64common:%vreg176
	    Successors according to CFG: BB#23

1824B	BB#23: derived from LLVM BB %if.end.34
	    Predecessors according to CFG: BB#21 BB#22
1840B		B <BB#53>
	    Successors according to CFG: BB#53

1856B	BB#24: derived from LLVM BB %if.end.35
	    Predecessors according to CFG: BB#18
1872B		%vreg55<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg55
1888B		CBNZW %vreg55, <BB#30>; GPR32:%vreg55
	    Successors according to CFG: BB#30 BB#25

1904B	BB#25: derived from LLVM BB %if.then.37
	    Predecessors according to CFG: BB#24
1920B		%vreg160<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg160
1936B		CBZX %vreg160, <BB#27>; GPR64:%vreg160
	    Successors according to CFG: BB#27 BB#26

1952B	BB#26: derived from LLVM BB %if.then.39
	    Predecessors according to CFG: BB#25
1968B		%vreg162<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg162
1984B		STRWui %WZR, %vreg162, 0; mem:ST4[%27] GPR64common:%vreg162
	    Successors according to CFG: BB#27

2000B	BB#27: derived from LLVM BB %if.end.40
	    Predecessors according to CFG: BB#25 BB#26
2016B		%vreg164<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg164
2032B		CBZX %vreg164, <BB#29>; GPR64:%vreg164
	    Successors according to CFG: BB#29 BB#28

2048B	BB#28: derived from LLVM BB %if.then.42
	    Predecessors according to CFG: BB#27
2064B		%vreg166<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg166
2080B		STRWui %WZR, %vreg166, 1274; mem:ST4[%lastErr43] GPR64common:%vreg166
	    Successors according to CFG: BB#29

2096B	BB#29: derived from LLVM BB %if.end.44
	    Predecessors according to CFG: BB#27 BB#28
2112B		B <BB#53>
	    Successors according to CFG: BB#53

2128B	BB#30: derived from LLVM BB %if.end.45
	    Predecessors according to CFG: BB#24
2144B		%vreg63<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg63
2160B		%vreg62<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg62
2176B		STRWui %vreg63, %vreg62, 1256; mem:ST4[%avail_in] GPR32:%vreg63 GPR64common:%vreg62
2192B		%vreg59<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg59
2208B		%vreg58<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg58
2224B		STRXui %vreg59, %vreg58, 627; mem:ST8[%next_in] GPR64:%vreg59 GPR64common:%vreg58
	    Successors according to CFG: BB#31

2240B	BB#31: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#30 BB#52
2272B		%vreg81<def> = MOVi32imm 5000; GPR32:%vreg81
2288B		%vreg83<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg83
2304B		STRWui %vreg81, %vreg83, 1262; mem:ST4[%avail_out] GPR32:%vreg81 GPR64common:%vreg83
2320B		%vreg80<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg80
2336B		%vreg79<def> = ADDXri %vreg80, 8, 0; GPR64common:%vreg79,%vreg80
2352B		%vreg76<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg76
2368B		STRXui %vreg79, %vreg76, 630; mem:ST8[%next_out] GPR64common:%vreg79,%vreg76
2384B		%vreg73<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg73
2400B		%vreg71<def> = MOVi64imm 5016; GPR64:%vreg71
2416B		%vreg72<def> = ADDXrr %vreg73, %vreg71; GPR64:%vreg72,%vreg73,%vreg71
2432B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2448B		%X0<def> = COPY %vreg72; GPR64:%vreg72
2464B		%W1<def> = COPY %WZR
2480B		BL <ga:@BZ2_bzCompress>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %W0<imp-def>
2496B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2512B		%vreg69<def> = COPY %W0; GPR32:%vreg69
2528B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2544B		STACKMAP 2, 0, 0, <fi#0>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4)
2560B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2576B		STRWui %vreg69, <fi#6>, 0; mem:ST4[FixedStack6] GPR32:%vreg69
2592B		%vreg65<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32common:%vreg65
2608B		%WZR<def> = SUBSWri %vreg65, 1, 0, %NZCV<imp-def>; GPR32common:%vreg65
2624B		Bcc 0, <BB#37>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#37 BB#32

2640B	BB#32: derived from LLVM BB %if.then.53
	    Predecessors according to CFG: BB#31
2656B		%vreg148<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg148
2672B		CBZX %vreg148, <BB#34>; GPR64:%vreg148
	    Successors according to CFG: BB#34 BB#33

2688B	BB#33: derived from LLVM BB %if.then.55
	    Predecessors according to CFG: BB#32
2704B		%vreg152<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg152
2720B		%vreg151<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg151
2736B		STRWui %vreg152, %vreg151, 0; mem:ST4[%41] GPR32:%vreg152 GPR64common:%vreg151
	    Successors according to CFG: BB#34

2752B	BB#34: derived from LLVM BB %if.end.56
	    Predecessors according to CFG: BB#32 BB#33
2768B		%vreg154<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg154
2784B		CBZX %vreg154, <BB#36>; GPR64:%vreg154
	    Successors according to CFG: BB#36 BB#35

2800B	BB#35: derived from LLVM BB %if.then.58
	    Predecessors according to CFG: BB#34
2816B		%vreg158<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg158
2832B		%vreg157<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg157
2848B		STRWui %vreg158, %vreg157, 1274; mem:ST4[%lastErr59] GPR32:%vreg158 GPR64common:%vreg157
	    Successors according to CFG: BB#36

2864B	BB#36: derived from LLVM BB %if.end.60
	    Predecessors according to CFG: BB#34 BB#35
2880B		B <BB#53>
	    Successors according to CFG: BB#53

2896B	BB#37: derived from LLVM BB %if.end.61
	    Predecessors according to CFG: BB#31
2912B		%vreg85<def> = MOVi32imm 5000; GPR32:%vreg85
2928B		%vreg88<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg88
2944B		%vreg87<def> = LDRWui %vreg88, 1262; mem:LD4[%avail_out63] GPR32:%vreg87 GPR64common:%vreg88
2960B		%WZR<def> = SUBSWrr %vreg87, %vreg85, %NZCV<imp-def>; GPR32:%vreg87,%vreg85
2976B		Bcc 2, <BB#46>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#46 BB#38

2992B	BB#38: derived from LLVM BB %if.then.65
	    Predecessors according to CFG: BB#37
3024B		%vreg113<def> = MOVi32imm 5000; GPR32:%vreg113
3040B		%vreg118<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg118
3056B		%vreg117<def> = LDRWui %vreg118, 1262; mem:LD4[%avail_out67] GPR32:%vreg117 GPR64common:%vreg118
3072B		%vreg115<def> = SUBWrr %vreg113, %vreg117; GPR32:%vreg115,%vreg113,%vreg117
3088B		STRWui %vreg115, <fi#4>, 0; mem:ST4[FixedStack4] GPR32:%vreg115
3104B		%vreg111<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg111
3120B		%vreg110<def> = ADDXri %vreg111, 8, 0; GPR64sp:%vreg110 GPR64common:%vreg111
3136B		%vreg107<def> = LDRSWui <fi#4>, 0; mem:LD4[FixedStack4] GPR64:%vreg107
3152B		%vreg103<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg103
3168B		%vreg102<def> = LDRXui %vreg103, 0; mem:LD8[%handle70] GPR64:%vreg102 GPR64common:%vreg103
3184B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3200B		%X0<def> = COPY %vreg110; GPR64sp:%vreg110
3216B		%X1<def> = MOVi64imm 1
3232B		%X2<def> = COPY %vreg107; GPR64:%vreg107
3248B		%X3<def> = COPY %vreg102; GPR64:%vreg102
3264B		BL <ga:@fwrite>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %X2<imp-use>, %X3<imp-use>, %X0<imp-def>
3280B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3296B		%vreg100<def> = COPY %X0; GPR64:%vreg100
3312B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3328B		STACKMAP 3, 0, 0, <fi#0>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4)
3344B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3376B		STRWui %vreg100:sub_32, <fi#5>, 0; mem:ST4[FixedStack5] GPR64:%vreg100
3392B		%vreg92<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg92
3408B		%vreg91<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32:%vreg91
3424B		%WZR<def> = SUBSWrr %vreg92, %vreg91, %NZCV<imp-def>; GPR32:%vreg92,%vreg91
3440B		Bcc 1, <BB#40>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#40 BB#39

3456B	BB#39: derived from LLVM BB %lor.lhs.false.75
	    Predecessors according to CFG: BB#38
3472B		%vreg124<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg124
3488B		%vreg123<def> = LDRXui %vreg124, 0; mem:LD8[%handle76] GPR64:%vreg123 GPR64common:%vreg124
3504B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3520B		%X0<def> = COPY %vreg123; GPR64:%vreg123
3536B		BL <ga:@ferror>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
3552B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3568B		%vreg121<def> = COPY %W0; GPR32:%vreg121
3584B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3600B		STACKMAP 4, 0, 0, <fi#0>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4)
3616B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3632B		CBZW %vreg121, <BB#45>; GPR32:%vreg121
	    Successors according to CFG: BB#45 BB#40

3648B	BB#40: derived from LLVM BB %if.then.79
	    Predecessors according to CFG: BB#38 BB#39
3664B		%vreg138<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg138
3680B		CBZX %vreg138, <BB#42>; GPR64:%vreg138
	    Successors according to CFG: BB#42 BB#41

3696B	BB#41: derived from LLVM BB %if.then.82
	    Predecessors according to CFG: BB#40
3712B		%vreg139<def> = MOVi32imm 4294967290; GPR32:%vreg139
3728B		%vreg141<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg141
3744B		STRWui %vreg139, %vreg141, 0; mem:ST4[%58] GPR32:%vreg139 GPR64common:%vreg141
	    Successors according to CFG: BB#42

3760B	BB#42: derived from LLVM BB %if.end.83
	    Predecessors according to CFG: BB#40 BB#41
3776B		%vreg143<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg143
3792B		CBZX %vreg143, <BB#44>; GPR64:%vreg143
	    Successors according to CFG: BB#44 BB#43

3808B	BB#43: derived from LLVM BB %if.then.86
	    Predecessors according to CFG: BB#42
3824B		%vreg144<def> = MOVi32imm 4294967290; GPR32:%vreg144
3840B		%vreg146<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg146
3856B		STRWui %vreg144, %vreg146, 1274; mem:ST4[%lastErr87] GPR32:%vreg144 GPR64common:%vreg146
	    Successors according to CFG: BB#44

3872B	BB#44: derived from LLVM BB %if.end.88
	    Predecessors according to CFG: BB#42 BB#43
3888B		B <BB#53>
	    Successors according to CFG: BB#53

3904B	BB#45: derived from LLVM BB %if.end.89
	    Predecessors according to CFG: BB#39
3920B		B <BB#46>
	    Successors according to CFG: BB#46

3936B	BB#46: derived from LLVM BB %if.end.90
	    Predecessors according to CFG: BB#37 BB#45
3952B		%vreg128<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg128
3968B		%vreg127<def> = LDRWui %vreg128, 1256; mem:LD4[%avail_in92] GPR32:%vreg127 GPR64common:%vreg128
3984B		CBNZW %vreg127, <BB#52>; GPR32:%vreg127
	    Successors according to CFG: BB#52 BB#47

4000B	BB#47: derived from LLVM BB %if.then.95
	    Predecessors according to CFG: BB#46
4016B		%vreg130<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg130
4032B		CBZX %vreg130, <BB#49>; GPR64:%vreg130
	    Successors according to CFG: BB#49 BB#48

4048B	BB#48: derived from LLVM BB %if.then.98
	    Predecessors according to CFG: BB#47
4064B		%vreg132<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg132
4080B		STRWui %WZR, %vreg132, 0; mem:ST4[%64] GPR64common:%vreg132
	    Successors according to CFG: BB#49

4096B	BB#49: derived from LLVM BB %if.end.99
	    Predecessors according to CFG: BB#47 BB#48
4112B		%vreg134<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg134
4128B		CBZX %vreg134, <BB#51>; GPR64:%vreg134
	    Successors according to CFG: BB#51 BB#50

4144B	BB#50: derived from LLVM BB %if.then.102
	    Predecessors according to CFG: BB#49
4160B		%vreg136<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg136
4176B		STRWui %WZR, %vreg136, 1274; mem:ST4[%lastErr103] GPR64common:%vreg136
	    Successors according to CFG: BB#51

4192B	BB#51: derived from LLVM BB %if.end.104
	    Predecessors according to CFG: BB#49 BB#50
4208B		B <BB#53>
	    Successors according to CFG: BB#53

4224B	BB#52: derived from LLVM BB %if.end.105
	    Predecessors according to CFG: BB#46
4240B		B <BB#31>
	    Successors according to CFG: BB#31

4256B	BB#53: derived from LLVM BB %return
	    Predecessors according to CFG: BB#17 BB#51 BB#44 BB#36 BB#29 BB#23 BB#11
4272B		%vreg187<def> = ADRP <ga:@BZ2_bzWrite>[TF=1]; GPR64common:%vreg187
4288B		%vreg189<def> = ADDXri %vreg187, <ga:@BZ2_bzWrite>[TF=34], 0; GPR64sp:%vreg189 GPR64common:%vreg187
4336B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4352B		%X0<def> = COPY %vreg189; GPR64sp:%vreg189
4368B		%X1<def> = COPY %vreg17; GPR64:%vreg17
4384B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
4400B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4416B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4432B		STACKMAP 5, 0, %LR<earlyclobber,imp-def,dead>, ...
4448B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4464B		RET_ReallyLR

# End machine code for function BZ2_bzWrite.

handleMove 848B -> 872B: %vreg179<def> = MOVi32imm 4294967294; GPR32:%vreg179
     %vreg179:	[848r,880r:0)  0@848r
        -->	[872r,880r:0)  0@872r
handleMove 960B -> 984B: %vreg184<def> = MOVi32imm 4294967294; GPR32:%vreg184
     %vreg184:	[960r,992r:0)  0@960r
        -->	[984r,992r:0)  0@984r
handleMove 1216B -> 1240B: %vreg40<def> = MOVi32imm 4294967295; GPR32:%vreg40
     %vreg40:	[1216r,1248r:0)  0@1216r
        -->	[1240r,1248r:0)  0@1240r
handleMove 1328B -> 1352B: %vreg45<def> = MOVi32imm 4294967295; GPR32:%vreg45
     %vreg45:	[1328r,1360r:0)  0@1328r
        -->	[1352r,1360r:0)  0@1352r
handleMove 1664B -> 1688B: %vreg169<def> = MOVi32imm 4294967290; GPR32:%vreg169
     %vreg169:	[1664r,1696r:0)  0@1664r
        -->	[1688r,1696r:0)  0@1688r
handleMove 1776B -> 1800B: %vreg174<def> = MOVi32imm 4294967290; GPR32:%vreg174
     %vreg174:	[1776r,1808r:0)  0@1776r
        -->	[1800r,1808r:0)  0@1800r
handleMove 2464B -> 2440B: %W1<def> = COPY %WZR
     W1:	[0B,64r:0)[256r,272r:4)[2464r,2480r:1)[3216r,3264r:3)[4368r,4384r:2)  0@0B-phi 1@2464r 2@4368r 3@3216r 4@256r
        -->	[0B,64r:0)[256r,272r:4)[2440r,2480r:1)[3216r,3264r:3)[4368r,4384r:2)  0@0B-phi 1@2440r 2@4368r 3@3216r 4@256r
     WZR:	[2608r,2608d:2)[2960r,2960d:1)[3424r,3424d:0)  0@3424r 1@2960r 2@2608r
        -->	[2608r,2608d:2)[2960r,2960d:1)[3424r,3424d:0)  0@3424r 1@2960r 2@2608r
handleMove 2336B -> 2360B: %vreg79<def> = ADDXri %vreg80, 8, 0; GPR64common:%vreg79,%vreg80
     %vreg79:	[2336r,2368r:0)  0@2336r
        -->	[2360r,2368r:0)  0@2360r
     %vreg80:	[2320r,2336r:0)  0@2320r
        -->	[2320r,2360r:0)  0@2320r
handleMove 2272B -> 2296B: %vreg81<def> = MOVi32imm 5000; GPR32:%vreg81
     %vreg81:	[2272r,2304r:0)  0@2272r
        -->	[2296r,2304r:0)  0@2296r
handleMove 2912B -> 2952B: %vreg85<def> = MOVi32imm 5000; GPR32:%vreg85
     %vreg85:	[2912r,2960r:0)  0@2912r
        -->	[2952r,2960r:0)  0@2952r
handleMove 3216B -> 3192B: %X1<def> = MOVi64imm 1
     W1:	[0B,64r:0)[256r,272r:4)[2440r,2480r:1)[3216r,3264r:3)[4368r,4384r:2)  0@0B-phi 1@2440r 2@4368r 3@3216r 4@256r
        -->	[0B,64r:0)[256r,272r:4)[2440r,2480r:1)[3192r,3264r:3)[4368r,4384r:2)  0@0B-phi 1@2440r 2@4368r 3@3192r 4@256r
handleMove 3120B -> 3176B: %vreg110<def> = ADDXri %vreg111, 8, 0; GPR64sp:%vreg110 GPR64common:%vreg111
     %vreg110:	[3120r,3200r:0)  0@3120r
        -->	[3176r,3200r:0)  0@3176r
     %vreg111:	[3104r,3120r:0)  0@3104r
        -->	[3104r,3176r:0)  0@3104r
handleMove 3136B -> 3160B: %vreg107<def> = LDRSWui <fi#4>, 0; mem:LD4[FixedStack4] GPR64:%vreg107
     %vreg107:	[3136r,3232r:0)  0@3136r
        -->	[3160r,3232r:0)  0@3160r
handleMove 3104B -> 3156B: %vreg111<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg111
     %vreg111:	[3104r,3176r:0)  0@3104r
        -->	[3156r,3176r:0)  0@3156r
handleMove 3024B -> 3064B: %vreg113<def> = MOVi32imm 5000; GPR32:%vreg113
     %vreg113:	[3024r,3072r:0)  0@3024r
        -->	[3064r,3072r:0)  0@3064r
handleMove 3712B -> 3736B: %vreg139<def> = MOVi32imm 4294967290; GPR32:%vreg139
     %vreg139:	[3712r,3744r:0)  0@3712r
        -->	[3736r,3744r:0)  0@3736r
handleMove 3824B -> 3848B: %vreg144<def> = MOVi32imm 4294967290; GPR32:%vreg144
     %vreg144:	[3824r,3856r:0)  0@3824r
        -->	[3848r,3856r:0)  0@3848r
********** GREEDY REGISTER ALLOCATION **********
********** Function: BZ2_bzWrite
********** INTERVALS **********
W30 [0B,16r:0)[272r,272d:12)[320e,320d:5)[1488r,1488d:11)[1552e,1552d:4)[2480r,2480d:10)[2544e,2544d:3)[3264r,3264d:9)[3328e,3328d:2)[3536r,3536d:8)[3600e,3600d:1)[4384r,4384d:6)[4432e,4432d:7)  0@0B-phi 1@3600e 2@3328e 3@2544e 4@1552e 5@320e 6@4384r 7@4432e 8@3536r 9@3264r 10@2480r 11@1488r 12@272r
WZR [2608r,2608d:2)[2960r,2960d:1)[3424r,3424d:0)  0@3424r 1@2960r 2@2608r
W0 [0B,80r:0)[240r,272r:10)[1472r,1488r:9)[1488r,1520r:3)[2448r,2480r:8)[2480r,2512r:2)[3200r,3264r:7)[3264r,3296r:6)[3520r,3536r:5)[3536r,3568r:1)[4352r,4384r:4)  0@0B-phi 1@3536r 2@2480r 3@1488r 4@4352r 5@3520r 6@3264r 7@3200r 8@2448r 9@1472r 10@240r
W1 [0B,64r:0)[256r,272r:4)[2440r,2480r:1)[3192r,3264r:3)[4368r,4384r:2)  0@0B-phi 1@2440r 2@4368r 3@3192r 4@256r
W2 [0B,48r:0)[3232r,3264r:1)  0@0B-phi 1@3232r
W3 [0B,32r:0)[3248r,3264r:1)  0@0B-phi 1@3248r
%vreg1 [80r,352r:0)  0@80r
%vreg3 [64r,368r:0)  0@64r
%vreg5 [48r,384r:0)  0@48r
%vreg7 [32r,400r:0)  0@32r
%vreg9 [464r,480r:0)  0@464r
%vreg12 [416r,448r:0)  0@416r
%vreg14 [160r,176r:0)  0@160r
%vreg16 [176r,240r:0)  0@176r
%vreg17 [16r,4368r:0)  0@16r
%vreg20 [512r,528r:0)  0@512r
%vreg22 [560r,576r:0)  0@560r
%vreg24 [608r,624r:0)  0@608r
%vreg26 [656r,672r:0)  0@656r
%vreg28 [704r,720r:0)  0@704r
%vreg30 [752r,768r:0)  0@752r
%vreg32 [1120r,1136r:0)  0@1120r
%vreg34 [1072r,1088r:0)  0@1072r
%vreg35 [1088r,1104r:0)  0@1088r
%vreg36 [1104r,1120r:0)  0@1104r
%vreg37 [1056r,1088r:0)  0@1056r
%vreg39 [1168r,1184r:0)  0@1168r
%vreg40 [1240r,1248r:0)  0@1240r
%vreg42 [1232r,1248r:0)  0@1232r
%vreg44 [1280r,1296r:0)  0@1280r
%vreg45 [1352r,1360r:0)  0@1352r
%vreg47 [1344r,1360r:0)  0@1344r
%vreg50 [1520r,1584r:0)  0@1520r
%vreg52 [1440r,1472r:0)  0@1440r
%vreg53 [1424r,1440r:0)  0@1424r
%vreg55 [1872r,1888r:0)  0@1872r
%vreg58 [2208r,2224r:0)  0@2208r
%vreg59 [2192r,2224r:0)  0@2192r
%vreg62 [2160r,2176r:0)  0@2160r
%vreg63 [2144r,2176r:0)  0@2144r
%vreg65 [2592r,2608r:0)  0@2592r
%vreg69 [2512r,2576r:0)  0@2512r
%vreg71 [2400r,2416r:0)  0@2400r
%vreg72 [2416r,2448r:0)  0@2416r
%vreg73 [2384r,2416r:0)  0@2384r
%vreg76 [2352r,2368r:0)  0@2352r
%vreg79 [2360r,2368r:0)  0@2360r
%vreg80 [2320r,2360r:0)  0@2320r
%vreg81 [2296r,2304r:0)  0@2296r
%vreg83 [2288r,2304r:0)  0@2288r
%vreg85 [2952r,2960r:0)  0@2952r
%vreg87 [2944r,2960r:0)  0@2944r
%vreg88 [2928r,2944r:0)  0@2928r
%vreg91 [3408r,3424r:0)  0@3408r
%vreg92 [3392r,3424r:0)  0@3392r
%vreg100 [3296r,3376r:0)  0@3296r
%vreg102 [3168r,3248r:0)  0@3168r
%vreg103 [3152r,3168r:0)  0@3152r
%vreg107 [3160r,3232r:0)  0@3160r
%vreg110 [3176r,3200r:0)  0@3176r
%vreg111 [3156r,3176r:0)  0@3156r
%vreg113 [3064r,3072r:0)  0@3064r
%vreg115 [3072r,3088r:0)  0@3072r
%vreg117 [3056r,3072r:0)  0@3056r
%vreg118 [3040r,3056r:0)  0@3040r
%vreg121 [3568r,3632r:0)  0@3568r
%vreg123 [3488r,3520r:0)  0@3488r
%vreg124 [3472r,3488r:0)  0@3472r
%vreg127 [3968r,3984r:0)  0@3968r
%vreg128 [3952r,3968r:0)  0@3952r
%vreg130 [4016r,4032r:0)  0@4016r
%vreg132 [4064r,4080r:0)  0@4064r
%vreg134 [4112r,4128r:0)  0@4112r
%vreg136 [4160r,4176r:0)  0@4160r
%vreg138 [3664r,3680r:0)  0@3664r
%vreg139 [3736r,3744r:0)  0@3736r
%vreg141 [3728r,3744r:0)  0@3728r
%vreg143 [3776r,3792r:0)  0@3776r
%vreg144 [3848r,3856r:0)  0@3848r
%vreg146 [3840r,3856r:0)  0@3840r
%vreg148 [2656r,2672r:0)  0@2656r
%vreg151 [2720r,2736r:0)  0@2720r
%vreg152 [2704r,2736r:0)  0@2704r
%vreg154 [2768r,2784r:0)  0@2768r
%vreg157 [2832r,2848r:0)  0@2832r
%vreg158 [2816r,2848r:0)  0@2816r
%vreg160 [1920r,1936r:0)  0@1920r
%vreg162 [1968r,1984r:0)  0@1968r
%vreg164 [2016r,2032r:0)  0@2016r
%vreg166 [2064r,2080r:0)  0@2064r
%vreg168 [1616r,1632r:0)  0@1616r
%vreg169 [1688r,1696r:0)  0@1688r
%vreg171 [1680r,1696r:0)  0@1680r
%vreg173 [1728r,1744r:0)  0@1728r
%vreg174 [1800r,1808r:0)  0@1800r
%vreg176 [1792r,1808r:0)  0@1792r
%vreg178 [800r,816r:0)  0@800r
%vreg179 [872r,880r:0)  0@872r
%vreg181 [864r,880r:0)  0@864r
%vreg183 [912r,928r:0)  0@912r
%vreg184 [984r,992r:0)  0@984r
%vreg186 [976r,992r:0)  0@976r
%vreg187 [4272r,4288r:0)  0@4272r
%vreg189 [4288r,4352r:0)  0@4288r
RegMasks: 272r 1488r 2480r 3264r 3536r 4384r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzWrite: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=8, align=8, at location [SP]
  fi#3: size=4, align=4, at location [SP]
  fi#4: size=4, align=4, at location [SP]
  fi#5: size=4, align=4, at location [SP]
  fi#6: size=4, align=4, at location [SP]
  fi#7: size=8, align=8, at location [SP]
Function Live Ins: %X0 in %vreg0, %X1 in %vreg2, %X2 in %vreg4, %W3 in %vreg6, %LR in %vreg18

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %X1 %X2 %W3 %LR
16B		%vreg17<def> = COPY %LR; GPR64:%vreg17
32B		%vreg7<def> = COPY %W3; GPR32:%vreg7
48B		%vreg5<def> = COPY %X2; GPR64:%vreg5
64B		%vreg3<def> = COPY %X1; GPR64:%vreg3
80B		%vreg1<def> = COPY %X0; GPR64:%vreg1
160B		%vreg14<def> = ADRP <ga:@BZ2_bzWrite>[TF=1]; GPR64common:%vreg14
176B		%vreg16<def> = ADDXri %vreg14, <ga:@BZ2_bzWrite>[TF=34], 0; GPR64sp:%vreg16 GPR64common:%vreg14
224B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
240B		%X0<def> = COPY %vreg16; GPR64sp:%vreg16
256B		%X1<def> = COPY %vreg17; GPR64:%vreg17
272B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
288B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
304B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
320B		STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg5, 0, <fi#2>, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#7>, 0, %vreg7, 0, <fi#3>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack0] LD8[FixedStack7] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) GPR64:%vreg3,%vreg5,%vreg1 GPR32:%vreg7
336B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
352B		STRXui %vreg1, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg1
368B		STRXui %vreg3, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg3
384B		STRXui %vreg5, <fi#2>, 0; mem:ST8[FixedStack2] GPR64:%vreg5
400B		STRWui %vreg7, <fi#3>, 0; mem:ST4[FixedStack3] GPR32:%vreg7
416B		%vreg12<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg12
448B		STRXui %vreg12, <fi#7>, 0; mem:ST8[FixedStack7] GPR64:%vreg12
464B		%vreg9<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg9
480B		CBZX %vreg9, <BB#2>; GPR64:%vreg9
	    Successors according to CFG: BB#2 BB#1

496B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
512B		%vreg20<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg20
528B		STRWui %WZR, %vreg20, 0; mem:ST4[%3] GPR64common:%vreg20
	    Successors according to CFG: BB#2

544B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#1
560B		%vreg22<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg22
576B		CBZX %vreg22, <BB#4>; GPR64:%vreg22
	    Successors according to CFG: BB#4 BB#3

592B	BB#3: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#2
608B		%vreg24<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg24
624B		STRWui %WZR, %vreg24, 1274; mem:ST4[%lastErr] GPR64common:%vreg24
	    Successors according to CFG: BB#4

640B	BB#4: derived from LLVM BB %if.end.3
	    Predecessors according to CFG: BB#2 BB#3
656B		%vreg26<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg26
672B		CBZX %vreg26, <BB#7>; GPR64:%vreg26
	    Successors according to CFG: BB#7 BB#5

688B	BB#5: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#4
704B		%vreg28<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg28
720B		CBZX %vreg28, <BB#7>; GPR64:%vreg28
	    Successors according to CFG: BB#7 BB#6

736B	BB#6: derived from LLVM BB %lor.lhs.false.6
	    Predecessors according to CFG: BB#5
752B		%vreg30<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg30
768B		TBZW %vreg30, 31, <BB#12>; GPR32:%vreg30
	    Successors according to CFG: BB#12 BB#7

784B	BB#7: derived from LLVM BB %if.then.8
	    Predecessors according to CFG: BB#4 BB#5 BB#6
800B		%vreg178<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg178
816B		CBZX %vreg178, <BB#9>; GPR64:%vreg178
	    Successors according to CFG: BB#9 BB#8

832B	BB#8: derived from LLVM BB %if.then.10
	    Predecessors according to CFG: BB#7
864B		%vreg181<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg181
872B		%vreg179<def> = MOVi32imm 4294967294; GPR32:%vreg179
880B		STRWui %vreg179, %vreg181, 0; mem:ST4[%10] GPR32:%vreg179 GPR64common:%vreg181
	    Successors according to CFG: BB#9

896B	BB#9: derived from LLVM BB %if.end.11
	    Predecessors according to CFG: BB#7 BB#8
912B		%vreg183<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg183
928B		CBZX %vreg183, <BB#11>; GPR64:%vreg183
	    Successors according to CFG: BB#11 BB#10

944B	BB#10: derived from LLVM BB %if.then.13
	    Predecessors according to CFG: BB#9
976B		%vreg186<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg186
984B		%vreg184<def> = MOVi32imm 4294967294; GPR32:%vreg184
992B		STRWui %vreg184, %vreg186, 1274; mem:ST4[%lastErr14] GPR32:%vreg184 GPR64common:%vreg186
	    Successors according to CFG: BB#11

1008B	BB#11: derived from LLVM BB %if.end.15
	    Predecessors according to CFG: BB#9 BB#10
1024B		B <BB#53>
	    Successors according to CFG: BB#53

1040B	BB#12: derived from LLVM BB %if.end.16
	    Predecessors according to CFG: BB#6
1056B		%vreg37<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg37
1072B		%vreg34<def> = MOVi64imm 5012; GPR64:%vreg34
1088B		%vreg35<def> = ADDXrr %vreg37, %vreg34; GPR64common:%vreg35 GPR64:%vreg37,%vreg34
1104B		%vreg36<def> = LDRBBui %vreg35, 0; mem:LD1[%writing] GPR32:%vreg36 GPR64common:%vreg35
1120B		%vreg32<def> = UBFMWri %vreg36, 0, 7; GPR32:%vreg32,%vreg36
1136B		CBNZW %vreg32, <BB#18>; GPR32:%vreg32
	    Successors according to CFG: BB#18 BB#13

1152B	BB#13: derived from LLVM BB %if.then.17
	    Predecessors according to CFG: BB#12
1168B		%vreg39<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg39
1184B		CBZX %vreg39, <BB#15>; GPR64:%vreg39
	    Successors according to CFG: BB#15 BB#14

1200B	BB#14: derived from LLVM BB %if.then.19
	    Predecessors according to CFG: BB#13
1232B		%vreg42<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg42
1240B		%vreg40<def> = MOVi32imm 4294967295; GPR32:%vreg40
1248B		STRWui %vreg40, %vreg42, 0; mem:ST4[%16] GPR32:%vreg40 GPR64common:%vreg42
	    Successors according to CFG: BB#15

1264B	BB#15: derived from LLVM BB %if.end.20
	    Predecessors according to CFG: BB#13 BB#14
1280B		%vreg44<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg44
1296B		CBZX %vreg44, <BB#17>; GPR64:%vreg44
	    Successors according to CFG: BB#17 BB#16

1312B	BB#16: derived from LLVM BB %if.then.22
	    Predecessors according to CFG: BB#15
1344B		%vreg47<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg47
1352B		%vreg45<def> = MOVi32imm 4294967295; GPR32:%vreg45
1360B		STRWui %vreg45, %vreg47, 1274; mem:ST4[%lastErr23] GPR32:%vreg45 GPR64common:%vreg47
	    Successors according to CFG: BB#17

1376B	BB#17: derived from LLVM BB %if.end.24
	    Predecessors according to CFG: BB#15 BB#16
1392B		B <BB#53>
	    Successors according to CFG: BB#53

1408B	BB#18: derived from LLVM BB %if.end.25
	    Predecessors according to CFG: BB#12
1424B		%vreg53<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg53
1440B		%vreg52<def> = LDRXui %vreg53, 0; mem:LD8[%handle] GPR64:%vreg52 GPR64common:%vreg53
1456B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1472B		%X0<def> = COPY %vreg52; GPR64:%vreg52
1488B		BL <ga:@ferror>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
1504B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1520B		%vreg50<def> = COPY %W0; GPR32:%vreg50
1536B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1552B		STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#7>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2] LD8[FixedStack0] LD8[FixedStack7] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4)
1568B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1584B		CBZW %vreg50, <BB#24>; GPR32:%vreg50
	    Successors according to CFG: BB#24 BB#19

1600B	BB#19: derived from LLVM BB %if.then.27
	    Predecessors according to CFG: BB#18
1616B		%vreg168<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg168
1632B		CBZX %vreg168, <BB#21>; GPR64:%vreg168
	    Successors according to CFG: BB#21 BB#20

1648B	BB#20: derived from LLVM BB %if.then.29
	    Predecessors according to CFG: BB#19
1680B		%vreg171<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg171
1688B		%vreg169<def> = MOVi32imm 4294967290; GPR32:%vreg169
1696B		STRWui %vreg169, %vreg171, 0; mem:ST4[%22] GPR32:%vreg169 GPR64common:%vreg171
	    Successors according to CFG: BB#21

1712B	BB#21: derived from LLVM BB %if.end.30
	    Predecessors according to CFG: BB#19 BB#20
1728B		%vreg173<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg173
1744B		CBZX %vreg173, <BB#23>; GPR64:%vreg173
	    Successors according to CFG: BB#23 BB#22

1760B	BB#22: derived from LLVM BB %if.then.32
	    Predecessors according to CFG: BB#21
1792B		%vreg176<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg176
1800B		%vreg174<def> = MOVi32imm 4294967290; GPR32:%vreg174
1808B		STRWui %vreg174, %vreg176, 1274; mem:ST4[%lastErr33] GPR32:%vreg174 GPR64common:%vreg176
	    Successors according to CFG: BB#23

1824B	BB#23: derived from LLVM BB %if.end.34
	    Predecessors according to CFG: BB#21 BB#22
1840B		B <BB#53>
	    Successors according to CFG: BB#53

1856B	BB#24: derived from LLVM BB %if.end.35
	    Predecessors according to CFG: BB#18
1872B		%vreg55<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg55
1888B		CBNZW %vreg55, <BB#30>; GPR32:%vreg55
	    Successors according to CFG: BB#30 BB#25

1904B	BB#25: derived from LLVM BB %if.then.37
	    Predecessors according to CFG: BB#24
1920B		%vreg160<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg160
1936B		CBZX %vreg160, <BB#27>; GPR64:%vreg160
	    Successors according to CFG: BB#27 BB#26

1952B	BB#26: derived from LLVM BB %if.then.39
	    Predecessors according to CFG: BB#25
1968B		%vreg162<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg162
1984B		STRWui %WZR, %vreg162, 0; mem:ST4[%27] GPR64common:%vreg162
	    Successors according to CFG: BB#27

2000B	BB#27: derived from LLVM BB %if.end.40
	    Predecessors according to CFG: BB#25 BB#26
2016B		%vreg164<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg164
2032B		CBZX %vreg164, <BB#29>; GPR64:%vreg164
	    Successors according to CFG: BB#29 BB#28

2048B	BB#28: derived from LLVM BB %if.then.42
	    Predecessors according to CFG: BB#27
2064B		%vreg166<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg166
2080B		STRWui %WZR, %vreg166, 1274; mem:ST4[%lastErr43] GPR64common:%vreg166
	    Successors according to CFG: BB#29

2096B	BB#29: derived from LLVM BB %if.end.44
	    Predecessors according to CFG: BB#27 BB#28
2112B		B <BB#53>
	    Successors according to CFG: BB#53

2128B	BB#30: derived from LLVM BB %if.end.45
	    Predecessors according to CFG: BB#24
2144B		%vreg63<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg63
2160B		%vreg62<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg62
2176B		STRWui %vreg63, %vreg62, 1256; mem:ST4[%avail_in] GPR32:%vreg63 GPR64common:%vreg62
2192B		%vreg59<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg59
2208B		%vreg58<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg58
2224B		STRXui %vreg59, %vreg58, 627; mem:ST8[%next_in] GPR64:%vreg59 GPR64common:%vreg58
	    Successors according to CFG: BB#31

2240B	BB#31: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#30 BB#52
2288B		%vreg83<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg83
2296B		%vreg81<def> = MOVi32imm 5000; GPR32:%vreg81
2304B		STRWui %vreg81, %vreg83, 1262; mem:ST4[%avail_out] GPR32:%vreg81 GPR64common:%vreg83
2320B		%vreg80<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg80
2352B		%vreg76<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg76
2360B		%vreg79<def> = ADDXri %vreg80, 8, 0; GPR64common:%vreg79,%vreg80
2368B		STRXui %vreg79, %vreg76, 630; mem:ST8[%next_out] GPR64common:%vreg79,%vreg76
2384B		%vreg73<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg73
2400B		%vreg71<def> = MOVi64imm 5016; GPR64:%vreg71
2416B		%vreg72<def> = ADDXrr %vreg73, %vreg71; GPR64:%vreg72,%vreg73,%vreg71
2432B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2440B		%W1<def> = COPY %WZR
2448B		%X0<def> = COPY %vreg72; GPR64:%vreg72
2480B		BL <ga:@BZ2_bzCompress>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %W0<imp-def>
2496B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2512B		%vreg69<def> = COPY %W0; GPR32:%vreg69
2528B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2544B		STACKMAP 2, 0, 0, <fi#0>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4)
2560B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2576B		STRWui %vreg69, <fi#6>, 0; mem:ST4[FixedStack6] GPR32:%vreg69
2592B		%vreg65<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32common:%vreg65
2608B		%WZR<def> = SUBSWri %vreg65, 1, 0, %NZCV<imp-def>; GPR32common:%vreg65
2624B		Bcc 0, <BB#37>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#37 BB#32

2640B	BB#32: derived from LLVM BB %if.then.53
	    Predecessors according to CFG: BB#31
2656B		%vreg148<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg148
2672B		CBZX %vreg148, <BB#34>; GPR64:%vreg148
	    Successors according to CFG: BB#34 BB#33

2688B	BB#33: derived from LLVM BB %if.then.55
	    Predecessors according to CFG: BB#32
2704B		%vreg152<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg152
2720B		%vreg151<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg151
2736B		STRWui %vreg152, %vreg151, 0; mem:ST4[%41] GPR32:%vreg152 GPR64common:%vreg151
	    Successors according to CFG: BB#34

2752B	BB#34: derived from LLVM BB %if.end.56
	    Predecessors according to CFG: BB#32 BB#33
2768B		%vreg154<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg154
2784B		CBZX %vreg154, <BB#36>; GPR64:%vreg154
	    Successors according to CFG: BB#36 BB#35

2800B	BB#35: derived from LLVM BB %if.then.58
	    Predecessors according to CFG: BB#34
2816B		%vreg158<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg158
2832B		%vreg157<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg157
2848B		STRWui %vreg158, %vreg157, 1274; mem:ST4[%lastErr59] GPR32:%vreg158 GPR64common:%vreg157
	    Successors according to CFG: BB#36

2864B	BB#36: derived from LLVM BB %if.end.60
	    Predecessors according to CFG: BB#34 BB#35
2880B		B <BB#53>
	    Successors according to CFG: BB#53

2896B	BB#37: derived from LLVM BB %if.end.61
	    Predecessors according to CFG: BB#31
2928B		%vreg88<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg88
2944B		%vreg87<def> = LDRWui %vreg88, 1262; mem:LD4[%avail_out63] GPR32:%vreg87 GPR64common:%vreg88
2952B		%vreg85<def> = MOVi32imm 5000; GPR32:%vreg85
2960B		%WZR<def> = SUBSWrr %vreg87, %vreg85, %NZCV<imp-def>; GPR32:%vreg87,%vreg85
2976B		Bcc 2, <BB#46>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#46 BB#38

2992B	BB#38: derived from LLVM BB %if.then.65
	    Predecessors according to CFG: BB#37
3040B		%vreg118<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg118
3056B		%vreg117<def> = LDRWui %vreg118, 1262; mem:LD4[%avail_out67] GPR32:%vreg117 GPR64common:%vreg118
3064B		%vreg113<def> = MOVi32imm 5000; GPR32:%vreg113
3072B		%vreg115<def> = SUBWrr %vreg113, %vreg117; GPR32:%vreg115,%vreg113,%vreg117
3088B		STRWui %vreg115, <fi#4>, 0; mem:ST4[FixedStack4] GPR32:%vreg115
3152B		%vreg103<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg103
3156B		%vreg111<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg111
3160B		%vreg107<def> = LDRSWui <fi#4>, 0; mem:LD4[FixedStack4] GPR64:%vreg107
3168B		%vreg102<def> = LDRXui %vreg103, 0; mem:LD8[%handle70] GPR64:%vreg102 GPR64common:%vreg103
3176B		%vreg110<def> = ADDXri %vreg111, 8, 0; GPR64sp:%vreg110 GPR64common:%vreg111
3184B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3192B		%X1<def> = MOVi64imm 1
3200B		%X0<def> = COPY %vreg110; GPR64sp:%vreg110
3232B		%X2<def> = COPY %vreg107; GPR64:%vreg107
3248B		%X3<def> = COPY %vreg102; GPR64:%vreg102
3264B		BL <ga:@fwrite>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %X2<imp-use>, %X3<imp-use>, %X0<imp-def>
3280B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3296B		%vreg100<def> = COPY %X0; GPR64:%vreg100
3312B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3328B		STACKMAP 3, 0, 0, <fi#0>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4)
3344B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3376B		STRWui %vreg100:sub_32, <fi#5>, 0; mem:ST4[FixedStack5] GPR64:%vreg100
3392B		%vreg92<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg92
3408B		%vreg91<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32:%vreg91
3424B		%WZR<def> = SUBSWrr %vreg92, %vreg91, %NZCV<imp-def>; GPR32:%vreg92,%vreg91
3440B		Bcc 1, <BB#40>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#40 BB#39

3456B	BB#39: derived from LLVM BB %lor.lhs.false.75
	    Predecessors according to CFG: BB#38
3472B		%vreg124<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg124
3488B		%vreg123<def> = LDRXui %vreg124, 0; mem:LD8[%handle76] GPR64:%vreg123 GPR64common:%vreg124
3504B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3520B		%X0<def> = COPY %vreg123; GPR64:%vreg123
3536B		BL <ga:@ferror>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
3552B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3568B		%vreg121<def> = COPY %W0; GPR32:%vreg121
3584B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3600B		STACKMAP 4, 0, 0, <fi#0>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4)
3616B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3632B		CBZW %vreg121, <BB#45>; GPR32:%vreg121
	    Successors according to CFG: BB#45 BB#40

3648B	BB#40: derived from LLVM BB %if.then.79
	    Predecessors according to CFG: BB#38 BB#39
3664B		%vreg138<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg138
3680B		CBZX %vreg138, <BB#42>; GPR64:%vreg138
	    Successors according to CFG: BB#42 BB#41

3696B	BB#41: derived from LLVM BB %if.then.82
	    Predecessors according to CFG: BB#40
3728B		%vreg141<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg141
3736B		%vreg139<def> = MOVi32imm 4294967290; GPR32:%vreg139
3744B		STRWui %vreg139, %vreg141, 0; mem:ST4[%58] GPR32:%vreg139 GPR64common:%vreg141
	    Successors according to CFG: BB#42

3760B	BB#42: derived from LLVM BB %if.end.83
	    Predecessors according to CFG: BB#40 BB#41
3776B		%vreg143<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg143
3792B		CBZX %vreg143, <BB#44>; GPR64:%vreg143
	    Successors according to CFG: BB#44 BB#43

3808B	BB#43: derived from LLVM BB %if.then.86
	    Predecessors according to CFG: BB#42
3840B		%vreg146<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg146
3848B		%vreg144<def> = MOVi32imm 4294967290; GPR32:%vreg144
3856B		STRWui %vreg144, %vreg146, 1274; mem:ST4[%lastErr87] GPR32:%vreg144 GPR64common:%vreg146
	    Successors according to CFG: BB#44

3872B	BB#44: derived from LLVM BB %if.end.88
	    Predecessors according to CFG: BB#42 BB#43
3888B		B <BB#53>
	    Successors according to CFG: BB#53

3904B	BB#45: derived from LLVM BB %if.end.89
	    Predecessors according to CFG: BB#39
3920B		B <BB#46>
	    Successors according to CFG: BB#46

3936B	BB#46: derived from LLVM BB %if.end.90
	    Predecessors according to CFG: BB#37 BB#45
3952B		%vreg128<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg128
3968B		%vreg127<def> = LDRWui %vreg128, 1256; mem:LD4[%avail_in92] GPR32:%vreg127 GPR64common:%vreg128
3984B		CBNZW %vreg127, <BB#52>; GPR32:%vreg127
	    Successors according to CFG: BB#52 BB#47

4000B	BB#47: derived from LLVM BB %if.then.95
	    Predecessors according to CFG: BB#46
4016B		%vreg130<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg130
4032B		CBZX %vreg130, <BB#49>; GPR64:%vreg130
	    Successors according to CFG: BB#49 BB#48

4048B	BB#48: derived from LLVM BB %if.then.98
	    Predecessors according to CFG: BB#47
4064B		%vreg132<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg132
4080B		STRWui %WZR, %vreg132, 0; mem:ST4[%64] GPR64common:%vreg132
	    Successors according to CFG: BB#49

4096B	BB#49: derived from LLVM BB %if.end.99
	    Predecessors according to CFG: BB#47 BB#48
4112B		%vreg134<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg134
4128B		CBZX %vreg134, <BB#51>; GPR64:%vreg134
	    Successors according to CFG: BB#51 BB#50

4144B	BB#50: derived from LLVM BB %if.then.102
	    Predecessors according to CFG: BB#49
4160B		%vreg136<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg136
4176B		STRWui %WZR, %vreg136, 1274; mem:ST4[%lastErr103] GPR64common:%vreg136
	    Successors according to CFG: BB#51

4192B	BB#51: derived from LLVM BB %if.end.104
	    Predecessors according to CFG: BB#49 BB#50
4208B		B <BB#53>
	    Successors according to CFG: BB#53

4224B	BB#52: derived from LLVM BB %if.end.105
	    Predecessors according to CFG: BB#46
4240B		B <BB#31>
	    Successors according to CFG: BB#31

4256B	BB#53: derived from LLVM BB %return
	    Predecessors according to CFG: BB#17 BB#51 BB#44 BB#36 BB#29 BB#23 BB#11
4272B		%vreg187<def> = ADRP <ga:@BZ2_bzWrite>[TF=1]; GPR64common:%vreg187
4288B		%vreg189<def> = ADDXri %vreg187, <ga:@BZ2_bzWrite>[TF=34], 0; GPR64sp:%vreg189 GPR64common:%vreg187
4336B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4352B		%X0<def> = COPY %vreg189; GPR64sp:%vreg189
4368B		%X1<def> = COPY %vreg17; GPR64:%vreg17
4384B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
4400B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4416B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4432B		STACKMAP 5, 0, %LR<earlyclobber,imp-def,dead>, ...
4448B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4464B		RET_ReallyLR

# End machine code for function BZ2_bzWrite.


selectOrSplit GPR64:%vreg17 [16r,4368r:0)  0@16r w=6.376263e-04
hints: %X1
missed hint %X1
Analyze counted 3 instrs in 2 blocks, through 52 blocks.
%X1	static = 1.0 worse than no bundles
%X8	static = 1.0 worse than no bundles
%X9	static = 1.0 worse than no bundles
%X10	static = 1.0 worse than no bundles
%X11	static = 1.0 worse than no bundles
%X12	static = 1.0 worse than no bundles
%X13	static = 1.0 worse than no bundles
%X14	static = 1.0 worse than no bundles
%X15	static = 1.0 worse than no bundles
%X16	static = 1.0 worse than no bundles
%X17	static = 1.0 worse than no bundles
%X18	static = 1.0 worse than no bundles
%X0	no positive bundles
%X2	static = 1.0 worse than no bundles
%X3	static = 1.0 worse than no bundles
%X4	static = 1.0 worse than no bundles
%X5	static = 1.0 worse than no bundles
%X6	static = 1.0 worse than no bundles
%X7	static = 1.0 worse than no bundles
assigning %vreg17 to %X19: W19 [16r,4368r:0)  0@16r

selectOrSplit GPR32:%vreg7 [32r,400r:0)  0@32r w=3.945312e-03
hints: %W3
missed hint %W3
Analyze counted 3 instrs in 1 blocks, through 0 blocks.
%W3	no positive bundles
%W8	no positive bundles
%W9	no positive bundles
%W10	no positive bundles
%W11	no positive bundles
%W12	no positive bundles
%W13	no positive bundles
%W14	no positive bundles
%W15	no positive bundles
%W16	no positive bundles
%W17	no positive bundles
%W18	no positive bundles
%W0	no positive bundles
%W1	no positive bundles
%W2	no positive bundles
%W4	no positive bundles
%W5	no positive bundles
%W6	no positive bundles
%W7	no positive bundles
%W19	no positive bundles
assigning %vreg7 to %W20: W20 [32r,400r:0)  0@32r

selectOrSplit GPR64:%vreg5 [48r,384r:0)  0@48r w=4.116848e-03
hints: %X2
missed hint %X2
Analyze counted 3 instrs in 1 blocks, through 0 blocks.
%X2	no positive bundles
%X8	no positive bundles
%X9	no positive bundles
%X10	no positive bundles
%X11	no positive bundles
%X12	no positive bundles
%X13	no positive bundles
%X14	no positive bundles
%X15	no positive bundles
%X16	no positive bundles
%X17	no positive bundles
%X18	no positive bundles
%X0	no positive bundles
%X1	no positive bundles
%X3	no positive bundles
%X4	no positive bundles
%X5	no positive bundles
%X6	no positive bundles
%X7	no positive bundles
%X19	no positive bundles
%X20	no positive bundles
assigning %vreg5 to %X21: W21 [48r,384r:0)  0@48r

selectOrSplit GPR64:%vreg3 [64r,368r:0)  0@64r w=4.303977e-03
hints: %X1
missed hint %X1
Analyze counted 3 instrs in 1 blocks, through 0 blocks.
%X1	no positive bundles
%X8	no positive bundles
%X9	no positive bundles
%X10	no positive bundles
%X11	no positive bundles
%X12	no positive bundles
%X13	no positive bundles
%X14	no positive bundles
%X15	no positive bundles
%X16	no positive bundles
%X17	no positive bundles
%X18	no positive bundles
%X0	no positive bundles
%X2	no positive bundles
%X3	no positive bundles
%X4	no positive bundles
%X5	no positive bundles
%X6	no positive bundles
%X7	no positive bundles
%X19	no positive bundles
%X20	no positive bundles
%X21	no positive bundles
assigning %vreg3 to %X22: W22 [64r,368r:0)  0@64r

selectOrSplit GPR64:%vreg1 [80r,352r:0)  0@80r w=4.508928e-03
hints: %X0
missed hint %X0
Analyze counted 3 instrs in 1 blocks, through 0 blocks.
%X0	no positive bundles
%X8	no positive bundles
%X9	no positive bundles
%X10	no positive bundles
%X11	no positive bundles
%X12	no positive bundles
%X13	no positive bundles
%X14	no positive bundles
%X15	no positive bundles
%X16	no positive bundles
%X17	no positive bundles
%X18	no positive bundles
%X1	no positive bundles
%X2	no positive bundles
%X3	no positive bundles
%X4	no positive bundles
%X5	no positive bundles
%X6	no positive bundles
%X7	no positive bundles
%X19	no positive bundles
%X20	no positive bundles
%X21	no positive bundles
%X22	no positive bundles
assigning %vreg1 to %X23: W23 [80r,352r:0)  0@80r

selectOrSplit GPR64sp:%vreg16 [176r,240r:0)  0@176r w=4.353448e-03
hints: %X0
assigning %vreg16 to %X0: W0 [176r,240r:0)  0@176r

selectOrSplit GPR64:%vreg52 [1440r,1472r:0)  0@1440r w=2.916111e-04
hints: %X0
assigning %vreg52 to %X0: W0 [1440r,1472r:0)  0@1440r

selectOrSplit GPR32:%vreg50 [1520r,1584r:0)  0@1520r w=2.715000e-04
hints: %W0
assigning %vreg50 to %W0: W0 [1520r,1584r:0)  0@1520r

selectOrSplit GPR64:%vreg72 [2416r,2448r:0)  0@2416r w=8.592716e-05
hints: %X0
assigning %vreg72 to %X0: W0 [2416r,2448r:0)  0@2416r

selectOrSplit GPR32:%vreg69 [2512r,2576r:0)  0@2512r w=8.000115e-05
hints: %W0
assigning %vreg69 to %W0: W0 [2512r,2576r:0)  0@2512r

selectOrSplit GPR64:%vreg107 [3160r,3232r:0)  0@3160r w=1.919686e-05
hints: %X2
assigning %vreg107 to %X2: W2 [3160r,3232r:0)  0@3160r

selectOrSplit GPR64:%vreg102 [3168r,3248r:0)  0@3168r w=1.887691e-05
hints: %X3
assigning %vreg102 to %X3: W3 [3168r,3248r:0)  0@3168r

selectOrSplit GPR64sp:%vreg110 [3176r,3200r:0)  0@3176r w=2.137009e-05
hints: %X0
assigning %vreg110 to %X0: W0 [3176r,3200r:0)  0@3176r

selectOrSplit GPR64:%vreg100 [3296r,3376r:0)  0@3296r w=1.887691e-05
hints: %X0
assigning %vreg100 to %X0: W0 [3296r,3376r:0)  0@3296r

selectOrSplit GPR64:%vreg123 [3488r,3520r:0)  0@3488r w=1.014888e-05
hints: %X0
assigning %vreg123 to %X0: W0 [3488r,3520r:0)  0@3488r

selectOrSplit GPR32:%vreg121 [3568r,3632r:0)  0@3568r w=9.448955e-06
hints: %W0
assigning %vreg121 to %W0: W0 [3568r,3632r:0)  0@3568r

selectOrSplit GPR64sp:%vreg189 [4288r,4352r:0)  0@4288r w=4.353448e-03
hints: %X0
assigning %vreg189 to %X0: W0 [4288r,4352r:0)  0@4288r

selectOrSplit GPR64common:%vreg14 [160r,176r:0)  0@160r w=inf
assigning %vreg14 to %X8: W8 [160r,176r:0)  0@160r

selectOrSplit GPR64:%vreg12 [416r,448r:0)  0@416r w=inf
assigning %vreg12 to %X8: W8 [416r,448r:0)  0@416r

selectOrSplit GPR64:%vreg9 [464r,480r:0)  0@464r w=inf
assigning %vreg9 to %X8: W8 [464r,480r:0)  0@464r

selectOrSplit GPR64common:%vreg20 [512r,528r:0)  0@512r w=inf
assigning %vreg20 to %X8: W8 [512r,528r:0)  0@512r

selectOrSplit GPR64:%vreg22 [560r,576r:0)  0@560r w=inf
assigning %vreg22 to %X8: W8 [560r,576r:0)  0@560r

selectOrSplit GPR64common:%vreg24 [608r,624r:0)  0@608r w=inf
assigning %vreg24 to %X8: W8 [608r,624r:0)  0@608r

selectOrSplit GPR64:%vreg26 [656r,672r:0)  0@656r w=inf
assigning %vreg26 to %X8: W8 [656r,672r:0)  0@656r

selectOrSplit GPR64:%vreg28 [704r,720r:0)  0@704r w=inf
assigning %vreg28 to %X8: W8 [704r,720r:0)  0@704r

selectOrSplit GPR32:%vreg30 [752r,768r:0)  0@752r w=inf
assigning %vreg30 to %W8: W8 [752r,768r:0)  0@752r

selectOrSplit GPR64:%vreg178 [800r,816r:0)  0@800r w=inf
assigning %vreg178 to %X8: W8 [800r,816r:0)  0@800r

selectOrSplit GPR64common:%vreg181 [864r,880r:0)  0@864r w=2.102974e-03
assigning %vreg181 to %X8: W8 [864r,880r:0)  0@864r

selectOrSplit GPR32:%vreg179 [872r,880r:0)  0@872r w=inf
assigning %vreg179 to %W9: W9 [872r,880r:0)  0@872r

selectOrSplit GPR64:%vreg183 [912r,928r:0)  0@912r w=inf
assigning %vreg183 to %X8: W8 [912r,928r:0)  0@912r

selectOrSplit GPR64common:%vreg186 [976r,992r:0)  0@976r w=2.102974e-03
assigning %vreg186 to %X8: W8 [976r,992r:0)  0@976r

selectOrSplit GPR32:%vreg184 [984r,992r:0)  0@984r w=inf
assigning %vreg184 to %W9: W9 [984r,992r:0)  0@984r

selectOrSplit GPR64:%vreg37 [1056r,1088r:0)  0@1056r w=5.781176e-04
assigning %vreg37 to %X8: W8 [1056r,1088r:0)  0@1056r

selectOrSplit GPR64:%vreg34 [1072r,1088r:0)  0@1072r w=inf
assigning %vreg34 to %X9: W9 [1072r,1088r:0)  0@1072r

selectOrSplit GPR64common:%vreg35 [1088r,1104r:0)  0@1088r w=inf
assigning %vreg35 to %X8: W8 [1088r,1104r:0)  0@1088r

selectOrSplit GPR32:%vreg36 [1104r,1120r:0)  0@1104r w=inf
assigning %vreg36 to %W8: W8 [1104r,1120r:0)  0@1104r

selectOrSplit GPR32:%vreg32 [1120r,1136r:0)  0@1120r w=inf
assigning %vreg32 to %W8: W8 [1120r,1136r:0)  0@1120r

selectOrSplit GPR64:%vreg39 [1168r,1184r:0)  0@1168r w=inf
assigning %vreg39 to %X8: W8 [1168r,1184r:0)  0@1168r

selectOrSplit GPR64common:%vreg42 [1232r,1248r:0)  0@1232r w=1.495665e-04
assigning %vreg42 to %X8: W8 [1232r,1248r:0)  0@1232r

selectOrSplit GPR32:%vreg40 [1240r,1248r:0)  0@1240r w=inf
assigning %vreg40 to %W9: W9 [1240r,1248r:0)  0@1240r

selectOrSplit GPR64:%vreg44 [1280r,1296r:0)  0@1280r w=inf
assigning %vreg44 to %X8: W8 [1280r,1296r:0)  0@1280r

selectOrSplit GPR64common:%vreg47 [1344r,1360r:0)  0@1344r w=1.495665e-04
assigning %vreg47 to %X8: W8 [1344r,1360r:0)  0@1344r

selectOrSplit GPR32:%vreg45 [1352r,1360r:0)  0@1352r w=inf
assigning %vreg45 to %W9: W9 [1352r,1360r:0)  0@1352r

selectOrSplit GPR64common:%vreg53 [1424r,1440r:0)  0@1424r w=inf
assigning %vreg53 to %X8: W8 [1424r,1440r:0)  0@1424r

selectOrSplit GPR64:%vreg168 [1616r,1632r:0)  0@1616r w=inf
assigning %vreg168 to %X8: W8 [1616r,1632r:0)  0@1616r

selectOrSplit GPR64common:%vreg171 [1680r,1696r:0)  0@1680r w=7.443540e-05
assigning %vreg171 to %X8: W8 [1680r,1696r:0)  0@1680r

selectOrSplit GPR32:%vreg169 [1688r,1696r:0)  0@1688r w=inf
assigning %vreg169 to %W9: W9 [1688r,1696r:0)  0@1688r

selectOrSplit GPR64:%vreg173 [1728r,1744r:0)  0@1728r w=inf
assigning %vreg173 to %X8: W8 [1728r,1744r:0)  0@1728r

selectOrSplit GPR64common:%vreg176 [1792r,1808r:0)  0@1792r w=7.443540e-05
assigning %vreg176 to %X8: W8 [1792r,1808r:0)  0@1792r

selectOrSplit GPR32:%vreg174 [1800r,1808r:0)  0@1800r w=inf
assigning %vreg174 to %W9: W9 [1800r,1808r:0)  0@1800r

selectOrSplit GPR32:%vreg55 [1872r,1888r:0)  0@1872r w=inf
assigning %vreg55 to %W8: W8 [1872r,1888r:0)  0@1872r

selectOrSplit GPR64:%vreg160 [1920r,1936r:0)  0@1920r w=inf
assigning %vreg160 to %X8: W8 [1920r,1936r:0)  0@1920r

selectOrSplit GPR64common:%vreg162 [1968r,1984r:0)  0@1968r w=inf
assigning %vreg162 to %X8: W8 [1968r,1984r:0)  0@1968r

selectOrSplit GPR64:%vreg164 [2016r,2032r:0)  0@2016r w=inf
assigning %vreg164 to %X8: W8 [2016r,2032r:0)  0@2016r

selectOrSplit GPR64common:%vreg166 [2064r,2080r:0)  0@2064r w=inf
assigning %vreg166 to %X8: W8 [2064r,2080r:0)  0@2064r

selectOrSplit GPR32:%vreg63 [2144r,2176r:0)  0@2144r w=7.167854e-05
assigning %vreg63 to %W8: W8 [2144r,2176r:0)  0@2144r

selectOrSplit GPR64common:%vreg62 [2160r,2176r:0)  0@2160r w=inf
assigning %vreg62 to %X9: W9 [2160r,2176r:0)  0@2160r

selectOrSplit GPR64:%vreg59 [2192r,2224r:0)  0@2192r w=7.167854e-05
assigning %vreg59 to %X8: W8 [2192r,2224r:0)  0@2192r

selectOrSplit GPR64common:%vreg58 [2208r,2224r:0)  0@2208r w=inf
assigning %vreg58 to %X9: W9 [2208r,2224r:0)  0@2208r

selectOrSplit GPR64common:%vreg83 [2288r,2304r:0)  0@2288r w=8.834856e-05
assigning %vreg83 to %X8: W8 [2288r,2304r:0)  0@2288r

selectOrSplit GPR32:%vreg81 [2296r,2304r:0)  0@2296r w=inf
assigning %vreg81 to %W9: W9 [2296r,2304r:0)  0@2296r

selectOrSplit GPR64common:%vreg80 [2320r,2360r:0)  0@2320r w=8.352955e-05
assigning %vreg80 to %X8: W8 [2320r,2360r:0)  0@2320r

selectOrSplit GPR64common:%vreg76 [2352r,2368r:0)  0@2352r w=8.834856e-05
assigning %vreg76 to %X9: W9 [2352r,2368r:0)  0@2352r

selectOrSplit GPR64common:%vreg79 [2360r,2368r:0)  0@2360r w=inf
assigning %vreg79 to %X8: W8 [2360r,2368r:0)  0@2360r

selectOrSplit GPR64:%vreg73 [2384r,2416r:0)  0@2384r w=8.507640e-05
assigning %vreg73 to %X8: W8 [2384r,2416r:0)  0@2384r

selectOrSplit GPR64:%vreg71 [2400r,2416r:0)  0@2400r w=inf
assigning %vreg71 to %X9: W9 [2400r,2416r:0)  0@2400r

selectOrSplit GPR32common:%vreg65 [2592r,2608r:0)  0@2592r w=inf
assigning %vreg65 to %W8: W8 [2592r,2608r:0)  0@2592r

selectOrSplit GPR64:%vreg148 [2656r,2672r:0)  0@2656r w=inf
assigning %vreg148 to %X8: W8 [2656r,2672r:0)  0@2656r

selectOrSplit GPR32:%vreg152 [2704r,2736r:0)  0@2704r w=2.076668e-05
assigning %vreg152 to %W8: W8 [2704r,2736r:0)  0@2704r

selectOrSplit GPR64common:%vreg151 [2720r,2736r:0)  0@2720r w=inf
assigning %vreg151 to %X9: W9 [2720r,2736r:0)  0@2720r

selectOrSplit GPR64:%vreg154 [2768r,2784r:0)  0@2768r w=inf
assigning %vreg154 to %X8: W8 [2768r,2784r:0)  0@2768r

selectOrSplit GPR32:%vreg158 [2816r,2848r:0)  0@2816r w=2.076668e-05
assigning %vreg158 to %W8: W8 [2816r,2848r:0)  0@2816r

selectOrSplit GPR64common:%vreg157 [2832r,2848r:0)  0@2832r w=inf
assigning %vreg157 to %X9: W9 [2832r,2848r:0)  0@2832r

selectOrSplit GPR64common:%vreg88 [2928r,2944r:0)  0@2928r w=inf
assigning %vreg88 to %X8: W8 [2928r,2944r:0)  0@2928r

selectOrSplit GPR32:%vreg87 [2944r,2960r:0)  0@2944r w=4.382645e-05
assigning %vreg87 to %W8: W8 [2944r,2960r:0)  0@2944r

selectOrSplit GPR32:%vreg85 [2952r,2960r:0)  0@2952r w=inf
assigning %vreg85 to %W9: W9 [2952r,2960r:0)  0@2952r

selectOrSplit GPR64common:%vreg118 [3040r,3056r:0)  0@3040r w=inf
assigning %vreg118 to %X8: W8 [3040r,3056r:0)  0@3040r

selectOrSplit GPR32:%vreg117 [3056r,3072r:0)  0@3056r w=2.156540e-05
assigning %vreg117 to %W8: W8 [3056r,3072r:0)  0@3056r

selectOrSplit GPR32:%vreg113 [3064r,3072r:0)  0@3064r w=inf
assigning %vreg113 to %W9: W9 [3064r,3072r:0)  0@3064r

selectOrSplit GPR32:%vreg115 [3072r,3088r:0)  0@3072r w=inf
assigning %vreg115 to %W8: W8 [3072r,3088r:0)  0@3072r

selectOrSplit GPR64common:%vreg103 [3152r,3168r:0)  0@3152r w=2.156540e-05
assigning %vreg103 to %X8: W8 [3152r,3168r:0)  0@3152r

selectOrSplit GPR64common:%vreg111 [3156r,3176r:0)  0@3156r w=2.136001e-05
assigning %vreg111 to %X9: W9 [3156r,3176r:0)  0@3156r

selectOrSplit GPR32:%vreg92 [3392r,3424r:0)  0@3392r w=2.076668e-05
assigning %vreg92 to %W8: W8 [3392r,3424r:0)  0@3392r

selectOrSplit GPR32:%vreg91 [3408r,3424r:0)  0@3408r w=inf
assigning %vreg91 to %W9: W9 [3408r,3424r:0)  0@3408r

selectOrSplit GPR64common:%vreg124 [3472r,3488r:0)  0@3472r w=inf
assigning %vreg124 to %X8: W8 [3472r,3488r:0)  0@3472r

selectOrSplit GPR64:%vreg138 [3664r,3680r:0)  0@3664r w=inf
assigning %vreg138 to %X8: W8 [3664r,3680r:0)  0@3664r

selectOrSplit GPR64common:%vreg141 [3728r,3744r:0)  0@3728r w=8.347896e-06
assigning %vreg141 to %X8: W8 [3728r,3744r:0)  0@3728r

selectOrSplit GPR32:%vreg139 [3736r,3744r:0)  0@3736r w=inf
assigning %vreg139 to %W9: W9 [3736r,3744r:0)  0@3736r

selectOrSplit GPR64:%vreg143 [3776r,3792r:0)  0@3776r w=inf
assigning %vreg143 to %X8: W8 [3776r,3792r:0)  0@3776r

selectOrSplit GPR64common:%vreg146 [3840r,3856r:0)  0@3840r w=8.347896e-06
assigning %vreg146 to %X8: W8 [3840r,3856r:0)  0@3840r

selectOrSplit GPR32:%vreg144 [3848r,3856r:0)  0@3848r w=inf
assigning %vreg144 to %W9: W9 [3848r,3856r:0)  0@3848r

selectOrSplit GPR64common:%vreg128 [3952r,3968r:0)  0@3952r w=inf
assigning %vreg128 to %X8: W8 [3952r,3968r:0)  0@3952r

selectOrSplit GPR32:%vreg127 [3968r,3984r:0)  0@3968r w=inf
assigning %vreg127 to %W8: W8 [3968r,3984r:0)  0@3968r

selectOrSplit GPR64:%vreg130 [4016r,4032r:0)  0@4016r w=inf
assigning %vreg130 to %X8: W8 [4016r,4032r:0)  0@4016r

selectOrSplit GPR64common:%vreg132 [4064r,4080r:0)  0@4064r w=inf
assigning %vreg132 to %X8: W8 [4064r,4080r:0)  0@4064r

selectOrSplit GPR64:%vreg134 [4112r,4128r:0)  0@4112r w=inf
assigning %vreg134 to %X8: W8 [4112r,4128r:0)  0@4112r

selectOrSplit GPR64common:%vreg136 [4160r,4176r:0)  0@4160r w=inf
assigning %vreg136 to %X8: W8 [4160r,4176r:0)  0@4160r

selectOrSplit GPR64common:%vreg187 [4272r,4288r:0)  0@4272r w=inf
assigning %vreg187 to %X8: W8 [4272r,4288r:0)  0@4272r

********** STACK TRANSFORMATION METADATA **********
********** Function: BZ2_bzWrite
********** REGISTER MAP **********
[%vreg1 -> %X23] GPR64
[%vreg3 -> %X22] GPR64
[%vreg5 -> %X21] GPR64
[%vreg7 -> %W20] GPR32
[%vreg9 -> %X8] GPR64
[%vreg12 -> %X8] GPR64
[%vreg14 -> %X8] GPR64common
[%vreg16 -> %X0] GPR64sp
[%vreg17 -> %X19] GPR64
[%vreg20 -> %X8] GPR64common
[%vreg22 -> %X8] GPR64
[%vreg24 -> %X8] GPR64common
[%vreg26 -> %X8] GPR64
[%vreg28 -> %X8] GPR64
[%vreg30 -> %W8] GPR32
[%vreg32 -> %W8] GPR32
[%vreg34 -> %X9] GPR64
[%vreg35 -> %X8] GPR64common
[%vreg36 -> %W8] GPR32
[%vreg37 -> %X8] GPR64
[%vreg39 -> %X8] GPR64
[%vreg40 -> %W9] GPR32
[%vreg42 -> %X8] GPR64common
[%vreg44 -> %X8] GPR64
[%vreg45 -> %W9] GPR32
[%vreg47 -> %X8] GPR64common
[%vreg50 -> %W0] GPR32
[%vreg52 -> %X0] GPR64
[%vreg53 -> %X8] GPR64common
[%vreg55 -> %W8] GPR32
[%vreg58 -> %X9] GPR64common
[%vreg59 -> %X8] GPR64
[%vreg62 -> %X9] GPR64common
[%vreg63 -> %W8] GPR32
[%vreg65 -> %W8] GPR32common
[%vreg69 -> %W0] GPR32
[%vreg71 -> %X9] GPR64
[%vreg72 -> %X0] GPR64
[%vreg73 -> %X8] GPR64
[%vreg76 -> %X9] GPR64common
[%vreg79 -> %X8] GPR64common
[%vreg80 -> %X8] GPR64common
[%vreg81 -> %W9] GPR32
[%vreg83 -> %X8] GPR64common
[%vreg85 -> %W9] GPR32
[%vreg87 -> %W8] GPR32
[%vreg88 -> %X8] GPR64common
[%vreg91 -> %W9] GPR32
[%vreg92 -> %W8] GPR32
[%vreg100 -> %X0] GPR64
[%vreg102 -> %X3] GPR64
[%vreg103 -> %X8] GPR64common
[%vreg107 -> %X2] GPR64
[%vreg110 -> %X0] GPR64sp
[%vreg111 -> %X9] GPR64common
[%vreg113 -> %W9] GPR32
[%vreg115 -> %W8] GPR32
[%vreg117 -> %W8] GPR32
[%vreg118 -> %X8] GPR64common
[%vreg121 -> %W0] GPR32
[%vreg123 -> %X0] GPR64
[%vreg124 -> %X8] GPR64common
[%vreg127 -> %W8] GPR32
[%vreg128 -> %X8] GPR64common
[%vreg130 -> %X8] GPR64
[%vreg132 -> %X8] GPR64common
[%vreg134 -> %X8] GPR64
[%vreg136 -> %X8] GPR64common
[%vreg138 -> %X8] GPR64
[%vreg139 -> %W9] GPR32
[%vreg141 -> %X8] GPR64common
[%vreg143 -> %X8] GPR64
[%vreg144 -> %W9] GPR32
[%vreg146 -> %X8] GPR64common
[%vreg148 -> %X8] GPR64
[%vreg151 -> %X9] GPR64common
[%vreg152 -> %W8] GPR32
[%vreg154 -> %X8] GPR64
[%vreg157 -> %X9] GPR64common
[%vreg158 -> %W8] GPR32
[%vreg160 -> %X8] GPR64
[%vreg162 -> %X8] GPR64common
[%vreg164 -> %X8] GPR64
[%vreg166 -> %X8] GPR64common
[%vreg168 -> %X8] GPR64
[%vreg169 -> %W9] GPR32
[%vreg171 -> %X8] GPR64common
[%vreg173 -> %X8] GPR64
[%vreg174 -> %W9] GPR32
[%vreg176 -> %X8] GPR64common
[%vreg178 -> %X8] GPR64
[%vreg179 -> %W9] GPR32
[%vreg181 -> %X8] GPR64common
[%vreg183 -> %X8] GPR64
[%vreg184 -> %W9] GPR32
[%vreg186 -> %X8] GPR64common
[%vreg187 -> %X8] GPR64common
[%vreg189 -> %X0] GPR64sp


Stackmap 0:
  STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg5, 0, <fi#2>, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#7>, 0, %vreg7, 0, <fi#3>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack0] LD8[FixedStack7] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) GPR64:%vreg3,%vreg5,%vreg1 GPR32:%vreg7

i8* %b: in register %X22 (vreg 3)
i8** %b.addr: in stack slot 1 (size: 8)
i8* %buf: in register %X21 (vreg 5)
i8** %buf.addr: in stack slot 2 (size: 8)
i32* %bzerror: in register %X23 (vreg 1)
i32** %bzerror.addr: in stack slot 0 (size: 8)
%struct.bzFile** %bzf: in stack slot 7 (size: 8)
i32 %len: in register %W20 (vreg 7)
i32* %len.addr: in stack slot 3 (size: 4)
i32* %n: in stack slot 4 (size: 4)
i32* %n2: in stack slot 5 (size: 4)
i32* %ret: in stack slot 6 (size: 4)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#7>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2] LD8[FixedStack0] LD8[FixedStack7] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4)

i8** %buf.addr: in stack slot 2 (size: 8)
i32** %bzerror.addr: in stack slot 0 (size: 8)
%struct.bzFile** %bzf: in stack slot 7 (size: 8)
i32* %len.addr: in stack slot 3 (size: 4)
i32* %n: in stack slot 4 (size: 4)
i32* %n2: in stack slot 5 (size: 4)
i32* %ret: in stack slot 6 (size: 4)

Duplicate operand locations:


Stackmap 2:
  STACKMAP 2, 0, 0, <fi#0>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4)

i32** %bzerror.addr: in stack slot 0 (size: 8)
%struct.bzFile** %bzf: in stack slot 7 (size: 8)
i32* %n: in stack slot 4 (size: 4)
i32* %n2: in stack slot 5 (size: 4)
i32* %ret: in stack slot 6 (size: 4)

Duplicate operand locations:


Stackmap 3:
  STACKMAP 3, 0, 0, <fi#0>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4)

i32** %bzerror.addr: in stack slot 0 (size: 8)
%struct.bzFile** %bzf: in stack slot 7 (size: 8)
i32* %n: in stack slot 4 (size: 4)
i32* %n2: in stack slot 5 (size: 4)
i32* %ret: in stack slot 6 (size: 4)

Duplicate operand locations:


Stackmap 4:
  STACKMAP 4, 0, 0, <fi#0>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4)

i32** %bzerror.addr: in stack slot 0 (size: 8)
%struct.bzFile** %bzf: in stack slot 7 (size: 8)
i32* %n: in stack slot 4 (size: 4)
i32* %n2: in stack slot 5 (size: 4)
i32* %ret: in stack slot 6 (size: 4)

Duplicate operand locations:


Stackmap 5:
  STACKMAP 5, 0, %LR<earlyclobber,imp-def,dead>, ...


Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg5, 0, <fi#2>, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#7>, 0, %vreg7, 0, <fi#3>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack0] LD8[FixedStack7] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) GPR64:%vreg3,%vreg5,%vreg1 GPR32:%vreg7
  -> Call instruction SlotIndex 272B, searching vregs 0 -> 191 and stack slots 0 -> 8
    + vreg17 is live in register but not in stackmap
      Defining instruction: %vreg17<def> = COPY %LR; GPR64:%vreg17
      Value: generated value, 1 instruction(s)

  STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#7>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2] LD8[FixedStack0] LD8[FixedStack7] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4)
  -> Call instruction SlotIndex 1488B, searching vregs 0 -> 191 and stack slots 0 -> 8
    + vreg17 is live in register but not in stackmap
      Defining instruction: %vreg17<def> = COPY %LR; GPR64:%vreg17
      Value: generated value, 1 instruction(s)

  STACKMAP 2, 0, 0, <fi#0>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4)
  -> Call instruction SlotIndex 2480B, searching vregs 0 -> 191 and stack slots 0 -> 8
    + vreg17 is live in register but not in stackmap
      Defining instruction: %vreg17<def> = COPY %LR; GPR64:%vreg17
      Value: generated value, 1 instruction(s)

  STACKMAP 3, 0, 0, <fi#0>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4)
  -> Call instruction SlotIndex 3264B, searching vregs 0 -> 191 and stack slots 0 -> 8
    + vreg17 is live in register but not in stackmap
      Defining instruction: %vreg17<def> = COPY %LR; GPR64:%vreg17
      Value: generated value, 1 instruction(s)

  STACKMAP 4, 0, 0, <fi#0>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4)
  -> Call instruction SlotIndex 3536B, searching vregs 0 -> 191 and stack slots 0 -> 8
    + vreg17 is live in register but not in stackmap
      Defining instruction: %vreg17<def> = COPY %LR; GPR64:%vreg17
      Value: generated value, 1 instruction(s)

  STACKMAP 5, 0, %LR<earlyclobber,imp-def,dead>, ...
  -> Call instruction SlotIndex 4384B, searching vregs 0 -> 191 and stack slots 0 -> 8

********** REWRITE VIRTUAL REGISTERS **********
********** Function: BZ2_bzWrite
********** REGISTER MAP **********
[%vreg1 -> %X23] GPR64
[%vreg3 -> %X22] GPR64
[%vreg5 -> %X21] GPR64
[%vreg7 -> %W20] GPR32
[%vreg9 -> %X8] GPR64
[%vreg12 -> %X8] GPR64
[%vreg14 -> %X8] GPR64common
[%vreg16 -> %X0] GPR64sp
[%vreg17 -> %X19] GPR64
[%vreg20 -> %X8] GPR64common
[%vreg22 -> %X8] GPR64
[%vreg24 -> %X8] GPR64common
[%vreg26 -> %X8] GPR64
[%vreg28 -> %X8] GPR64
[%vreg30 -> %W8] GPR32
[%vreg32 -> %W8] GPR32
[%vreg34 -> %X9] GPR64
[%vreg35 -> %X8] GPR64common
[%vreg36 -> %W8] GPR32
[%vreg37 -> %X8] GPR64
[%vreg39 -> %X8] GPR64
[%vreg40 -> %W9] GPR32
[%vreg42 -> %X8] GPR64common
[%vreg44 -> %X8] GPR64
[%vreg45 -> %W9] GPR32
[%vreg47 -> %X8] GPR64common
[%vreg50 -> %W0] GPR32
[%vreg52 -> %X0] GPR64
[%vreg53 -> %X8] GPR64common
[%vreg55 -> %W8] GPR32
[%vreg58 -> %X9] GPR64common
[%vreg59 -> %X8] GPR64
[%vreg62 -> %X9] GPR64common
[%vreg63 -> %W8] GPR32
[%vreg65 -> %W8] GPR32common
[%vreg69 -> %W0] GPR32
[%vreg71 -> %X9] GPR64
[%vreg72 -> %X0] GPR64
[%vreg73 -> %X8] GPR64
[%vreg76 -> %X9] GPR64common
[%vreg79 -> %X8] GPR64common
[%vreg80 -> %X8] GPR64common
[%vreg81 -> %W9] GPR32
[%vreg83 -> %X8] GPR64common
[%vreg85 -> %W9] GPR32
[%vreg87 -> %W8] GPR32
[%vreg88 -> %X8] GPR64common
[%vreg91 -> %W9] GPR32
[%vreg92 -> %W8] GPR32
[%vreg100 -> %X0] GPR64
[%vreg102 -> %X3] GPR64
[%vreg103 -> %X8] GPR64common
[%vreg107 -> %X2] GPR64
[%vreg110 -> %X0] GPR64sp
[%vreg111 -> %X9] GPR64common
[%vreg113 -> %W9] GPR32
[%vreg115 -> %W8] GPR32
[%vreg117 -> %W8] GPR32
[%vreg118 -> %X8] GPR64common
[%vreg121 -> %W0] GPR32
[%vreg123 -> %X0] GPR64
[%vreg124 -> %X8] GPR64common
[%vreg127 -> %W8] GPR32
[%vreg128 -> %X8] GPR64common
[%vreg130 -> %X8] GPR64
[%vreg132 -> %X8] GPR64common
[%vreg134 -> %X8] GPR64
[%vreg136 -> %X8] GPR64common
[%vreg138 -> %X8] GPR64
[%vreg139 -> %W9] GPR32
[%vreg141 -> %X8] GPR64common
[%vreg143 -> %X8] GPR64
[%vreg144 -> %W9] GPR32
[%vreg146 -> %X8] GPR64common
[%vreg148 -> %X8] GPR64
[%vreg151 -> %X9] GPR64common
[%vreg152 -> %W8] GPR32
[%vreg154 -> %X8] GPR64
[%vreg157 -> %X9] GPR64common
[%vreg158 -> %W8] GPR32
[%vreg160 -> %X8] GPR64
[%vreg162 -> %X8] GPR64common
[%vreg164 -> %X8] GPR64
[%vreg166 -> %X8] GPR64common
[%vreg168 -> %X8] GPR64
[%vreg169 -> %W9] GPR32
[%vreg171 -> %X8] GPR64common
[%vreg173 -> %X8] GPR64
[%vreg174 -> %W9] GPR32
[%vreg176 -> %X8] GPR64common
[%vreg178 -> %X8] GPR64
[%vreg179 -> %W9] GPR32
[%vreg181 -> %X8] GPR64common
[%vreg183 -> %X8] GPR64
[%vreg184 -> %W9] GPR32
[%vreg186 -> %X8] GPR64common
[%vreg187 -> %X8] GPR64common
[%vreg189 -> %X0] GPR64sp

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %LR %W3 %X0 %X1 %X2
16B		%vreg17<def> = COPY %LR; GPR64:%vreg17
32B		%vreg7<def> = COPY %W3; GPR32:%vreg7
48B		%vreg5<def> = COPY %X2; GPR64:%vreg5
64B		%vreg3<def> = COPY %X1; GPR64:%vreg3
80B		%vreg1<def> = COPY %X0; GPR64:%vreg1
160B		%vreg14<def> = ADRP <ga:@BZ2_bzWrite>[TF=1]; GPR64common:%vreg14
176B		%vreg16<def> = ADDXri %vreg14<kill>, <ga:@BZ2_bzWrite>[TF=34], 0; GPR64sp:%vreg16 GPR64common:%vreg14
224B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
240B		%X0<def> = COPY %vreg16<kill>; GPR64sp:%vreg16
256B		%X1<def> = COPY %vreg17; GPR64:%vreg17
272B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
288B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
304B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
320B		STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg5, 0, <fi#2>, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#7>, 0, %vreg7, 0, <fi#3>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack0] LD8[FixedStack7] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) GPR64:%vreg3,%vreg5,%vreg1 GPR32:%vreg7
336B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
352B		STRXui %vreg1<kill>, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg1
368B		STRXui %vreg3<kill>, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg3
384B		STRXui %vreg5<kill>, <fi#2>, 0; mem:ST8[FixedStack2] GPR64:%vreg5
400B		STRWui %vreg7<kill>, <fi#3>, 0; mem:ST4[FixedStack3] GPR32:%vreg7
416B		%vreg12<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg12
448B		STRXui %vreg12<kill>, <fi#7>, 0; mem:ST8[FixedStack7] GPR64:%vreg12
464B		%vreg9<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg9
480B		CBZX %vreg9<kill>, <BB#2>; GPR64:%vreg9
	    Successors according to CFG: BB#2 BB#1
> %X19<def> = COPY %LR
> %W20<def> = COPY %W3
> %X21<def> = COPY %X2
> %X22<def> = COPY %X1
> %X23<def> = COPY %X0
> %X8<def> = ADRP <ga:@BZ2_bzWrite>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@BZ2_bzWrite>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19
> BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 0, 0, %X22, 0, <fi#1>, 0, %X21, 0, <fi#2>, 0, %X23, 0, <fi#0>, 0, 0, <fi#7>, 0, %W20, 0, <fi#3>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack0] LD8[FixedStack7] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRXui %X23<kill>, <fi#0>, 0; mem:ST8[FixedStack0]
> STRXui %X22<kill>, <fi#1>, 0; mem:ST8[FixedStack1]
> STRXui %X21<kill>, <fi#2>, 0; mem:ST8[FixedStack2]
> STRWui %W20<kill>, <fi#3>, 0; mem:ST4[FixedStack3]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRXui %X8<kill>, <fi#7>, 0; mem:ST8[FixedStack7]
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> CBZX %X8<kill>, <BB#2>
496B	BB#1: derived from LLVM BB %if.then
	    Live Ins: %X19
	    Predecessors according to CFG: BB#0
512B		%vreg20<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg20
528B		STRWui %WZR, %vreg20<kill>, 0; mem:ST4[%3] GPR64common:%vreg20
	    Successors according to CFG: BB#2
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> STRWui %WZR, %X8<kill>, 0; mem:ST4[%3]
544B	BB#2: derived from LLVM BB %if.end
	    Live Ins: %X19
	    Predecessors according to CFG: BB#0 BB#1
560B		%vreg22<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg22
576B		CBZX %vreg22<kill>, <BB#4>; GPR64:%vreg22
	    Successors according to CFG: BB#4 BB#3
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> CBZX %X8<kill>, <BB#4>
592B	BB#3: derived from LLVM BB %if.then.2
	    Live Ins: %X19
	    Predecessors according to CFG: BB#2
608B		%vreg24<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg24
624B		STRWui %WZR, %vreg24<kill>, 1274; mem:ST4[%lastErr] GPR64common:%vreg24
	    Successors according to CFG: BB#4
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> STRWui %WZR, %X8<kill>, 1274; mem:ST4[%lastErr]
640B	BB#4: derived from LLVM BB %if.end.3
	    Live Ins: %X19
	    Predecessors according to CFG: BB#2 BB#3
656B		%vreg26<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg26
672B		CBZX %vreg26<kill>, <BB#7>; GPR64:%vreg26
	    Successors according to CFG: BB#7 BB#5
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> CBZX %X8<kill>, <BB#7>
688B	BB#5: derived from LLVM BB %lor.lhs.false
	    Live Ins: %X19
	    Predecessors according to CFG: BB#4
704B		%vreg28<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg28
720B		CBZX %vreg28<kill>, <BB#7>; GPR64:%vreg28
	    Successors according to CFG: BB#7 BB#6
> %X8<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2]
> CBZX %X8<kill>, <BB#7>
736B	BB#6: derived from LLVM BB %lor.lhs.false.6
	    Live Ins: %X19
	    Predecessors according to CFG: BB#5
752B		%vreg30<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg30
768B		TBZW %vreg30<kill>, 31, <BB#12>; GPR32:%vreg30
	    Successors according to CFG: BB#12 BB#7
> %W8<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3]
> TBZW %W8<kill>, 31, <BB#12>
784B	BB#7: derived from LLVM BB %if.then.8
	    Live Ins: %X19
	    Predecessors according to CFG: BB#4 BB#5 BB#6
800B		%vreg178<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg178
816B		CBZX %vreg178<kill>, <BB#9>; GPR64:%vreg178
	    Successors according to CFG: BB#9 BB#8
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> CBZX %X8<kill>, <BB#9>
832B	BB#8: derived from LLVM BB %if.then.10
	    Live Ins: %X19
	    Predecessors according to CFG: BB#7
864B		%vreg181<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg181
872B		%vreg179<def> = MOVi32imm 4294967294; GPR32:%vreg179
880B		STRWui %vreg179<kill>, %vreg181<kill>, 0; mem:ST4[%10] GPR32:%vreg179 GPR64common:%vreg181
	    Successors according to CFG: BB#9
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %W9<def> = MOVi32imm 4294967294
> STRWui %W9<kill>, %X8<kill>, 0; mem:ST4[%10]
896B	BB#9: derived from LLVM BB %if.end.11
	    Live Ins: %X19
	    Predecessors according to CFG: BB#7 BB#8
912B		%vreg183<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg183
928B		CBZX %vreg183<kill>, <BB#11>; GPR64:%vreg183
	    Successors according to CFG: BB#11 BB#10
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> CBZX %X8<kill>, <BB#11>
944B	BB#10: derived from LLVM BB %if.then.13
	    Live Ins: %X19
	    Predecessors according to CFG: BB#9
976B		%vreg186<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg186
984B		%vreg184<def> = MOVi32imm 4294967294; GPR32:%vreg184
992B		STRWui %vreg184<kill>, %vreg186<kill>, 1274; mem:ST4[%lastErr14] GPR32:%vreg184 GPR64common:%vreg186
	    Successors according to CFG: BB#11
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> %W9<def> = MOVi32imm 4294967294
> STRWui %W9<kill>, %X8<kill>, 1274; mem:ST4[%lastErr14]
1008B	BB#11: derived from LLVM BB %if.end.15
	    Live Ins: %X19
	    Predecessors according to CFG: BB#9 BB#10
1024B		B <BB#53>
	    Successors according to CFG: BB#53
> B <BB#53>
1040B	BB#12: derived from LLVM BB %if.end.16
	    Live Ins: %X19
	    Predecessors according to CFG: BB#6
1056B		%vreg37<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg37
1072B		%vreg34<def> = MOVi64imm 5012; GPR64:%vreg34
1088B		%vreg35<def> = ADDXrr %vreg37<kill>, %vreg34<kill>; GPR64common:%vreg35 GPR64:%vreg37,%vreg34
1104B		%vreg36<def> = LDRBBui %vreg35<kill>, 0; mem:LD1[%writing] GPR32:%vreg36 GPR64common:%vreg35
1120B		%vreg32<def> = UBFMWri %vreg36<kill>, 0, 7; GPR32:%vreg32,%vreg36
1136B		CBNZW %vreg32<kill>, <BB#18>; GPR32:%vreg32
	    Successors according to CFG: BB#18 BB#13
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> %X9<def> = MOVi64imm 5012
> %X8<def> = ADDXrr %X8<kill>, %X9<kill>
> %W8<def> = LDRBBui %X8<kill>, 0; mem:LD1[%writing]
> %W8<def> = UBFMWri %W8<kill>, 0, 7
> CBNZW %W8<kill>, <BB#18>
1152B	BB#13: derived from LLVM BB %if.then.17
	    Live Ins: %X19
	    Predecessors according to CFG: BB#12
1168B		%vreg39<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg39
1184B		CBZX %vreg39<kill>, <BB#15>; GPR64:%vreg39
	    Successors according to CFG: BB#15 BB#14
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> CBZX %X8<kill>, <BB#15>
1200B	BB#14: derived from LLVM BB %if.then.19
	    Live Ins: %X19
	    Predecessors according to CFG: BB#13
1232B		%vreg42<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg42
1240B		%vreg40<def> = MOVi32imm 4294967295; GPR32:%vreg40
1248B		STRWui %vreg40<kill>, %vreg42<kill>, 0; mem:ST4[%16] GPR32:%vreg40 GPR64common:%vreg42
	    Successors according to CFG: BB#15
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %W9<def> = MOVi32imm 4294967295
> STRWui %W9<kill>, %X8<kill>, 0; mem:ST4[%16]
1264B	BB#15: derived from LLVM BB %if.end.20
	    Live Ins: %X19
	    Predecessors according to CFG: BB#13 BB#14
1280B		%vreg44<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg44
1296B		CBZX %vreg44<kill>, <BB#17>; GPR64:%vreg44
	    Successors according to CFG: BB#17 BB#16
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> CBZX %X8<kill>, <BB#17>
1312B	BB#16: derived from LLVM BB %if.then.22
	    Live Ins: %X19
	    Predecessors according to CFG: BB#15
1344B		%vreg47<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg47
1352B		%vreg45<def> = MOVi32imm 4294967295; GPR32:%vreg45
1360B		STRWui %vreg45<kill>, %vreg47<kill>, 1274; mem:ST4[%lastErr23] GPR32:%vreg45 GPR64common:%vreg47
	    Successors according to CFG: BB#17
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> %W9<def> = MOVi32imm 4294967295
> STRWui %W9<kill>, %X8<kill>, 1274; mem:ST4[%lastErr23]
1376B	BB#17: derived from LLVM BB %if.end.24
	    Live Ins: %X19
	    Predecessors according to CFG: BB#15 BB#16
1392B		B <BB#53>
	    Successors according to CFG: BB#53
> B <BB#53>
1408B	BB#18: derived from LLVM BB %if.end.25
	    Live Ins: %X19
	    Predecessors according to CFG: BB#12
1424B		%vreg53<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg53
1440B		%vreg52<def> = LDRXui %vreg53<kill>, 0; mem:LD8[%handle] GPR64:%vreg52 GPR64common:%vreg53
1456B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1472B		%X0<def> = COPY %vreg52<kill>; GPR64:%vreg52
1488B		BL <ga:@ferror>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
1504B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1520B		%vreg50<def> = COPY %W0; GPR32:%vreg50
1536B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1552B		STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#7>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2] LD8[FixedStack0] LD8[FixedStack7] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4)
1568B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1584B		CBZW %vreg50<kill>, <BB#24>; GPR32:%vreg50
	    Successors according to CFG: BB#24 BB#19
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> %X0<def> = LDRXui %X8<kill>, 0; mem:LD8[%handle]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BL <ga:@ferror>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = COPY %W0
Deleting identity copy.
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#7>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2] LD8[FixedStack0] LD8[FixedStack7] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> CBZW %W0<kill>, <BB#24>
1600B	BB#19: derived from LLVM BB %if.then.27
	    Live Ins: %X19
	    Predecessors according to CFG: BB#18
1616B		%vreg168<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg168
1632B		CBZX %vreg168<kill>, <BB#21>; GPR64:%vreg168
	    Successors according to CFG: BB#21 BB#20
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> CBZX %X8<kill>, <BB#21>
1648B	BB#20: derived from LLVM BB %if.then.29
	    Live Ins: %X19
	    Predecessors according to CFG: BB#19
1680B		%vreg171<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg171
1688B		%vreg169<def> = MOVi32imm 4294967290; GPR32:%vreg169
1696B		STRWui %vreg169<kill>, %vreg171<kill>, 0; mem:ST4[%22] GPR32:%vreg169 GPR64common:%vreg171
	    Successors according to CFG: BB#21
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %W9<def> = MOVi32imm 4294967290
> STRWui %W9<kill>, %X8<kill>, 0; mem:ST4[%22]
1712B	BB#21: derived from LLVM BB %if.end.30
	    Live Ins: %X19
	    Predecessors according to CFG: BB#19 BB#20
1728B		%vreg173<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg173
1744B		CBZX %vreg173<kill>, <BB#23>; GPR64:%vreg173
	    Successors according to CFG: BB#23 BB#22
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> CBZX %X8<kill>, <BB#23>
1760B	BB#22: derived from LLVM BB %if.then.32
	    Live Ins: %X19
	    Predecessors according to CFG: BB#21
1792B		%vreg176<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg176
1800B		%vreg174<def> = MOVi32imm 4294967290; GPR32:%vreg174
1808B		STRWui %vreg174<kill>, %vreg176<kill>, 1274; mem:ST4[%lastErr33] GPR32:%vreg174 GPR64common:%vreg176
	    Successors according to CFG: BB#23
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> %W9<def> = MOVi32imm 4294967290
> STRWui %W9<kill>, %X8<kill>, 1274; mem:ST4[%lastErr33]
1824B	BB#23: derived from LLVM BB %if.end.34
	    Live Ins: %X19
	    Predecessors according to CFG: BB#21 BB#22
1840B		B <BB#53>
	    Successors according to CFG: BB#53
> B <BB#53>
1856B	BB#24: derived from LLVM BB %if.end.35
	    Live Ins: %X19
	    Predecessors according to CFG: BB#18
1872B		%vreg55<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg55
1888B		CBNZW %vreg55<kill>, <BB#30>; GPR32:%vreg55
	    Successors according to CFG: BB#30 BB#25
> %W8<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3]
> CBNZW %W8<kill>, <BB#30>
1904B	BB#25: derived from LLVM BB %if.then.37
	    Live Ins: %X19
	    Predecessors according to CFG: BB#24
1920B		%vreg160<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg160
1936B		CBZX %vreg160<kill>, <BB#27>; GPR64:%vreg160
	    Successors according to CFG: BB#27 BB#26
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> CBZX %X8<kill>, <BB#27>
1952B	BB#26: derived from LLVM BB %if.then.39
	    Live Ins: %X19
	    Predecessors according to CFG: BB#25
1968B		%vreg162<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg162
1984B		STRWui %WZR, %vreg162<kill>, 0; mem:ST4[%27] GPR64common:%vreg162
	    Successors according to CFG: BB#27
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> STRWui %WZR, %X8<kill>, 0; mem:ST4[%27]
2000B	BB#27: derived from LLVM BB %if.end.40
	    Live Ins: %X19
	    Predecessors according to CFG: BB#25 BB#26
2016B		%vreg164<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg164
2032B		CBZX %vreg164<kill>, <BB#29>; GPR64:%vreg164
	    Successors according to CFG: BB#29 BB#28
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> CBZX %X8<kill>, <BB#29>
2048B	BB#28: derived from LLVM BB %if.then.42
	    Live Ins: %X19
	    Predecessors according to CFG: BB#27
2064B		%vreg166<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg166
2080B		STRWui %WZR, %vreg166<kill>, 1274; mem:ST4[%lastErr43] GPR64common:%vreg166
	    Successors according to CFG: BB#29
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> STRWui %WZR, %X8<kill>, 1274; mem:ST4[%lastErr43]
2096B	BB#29: derived from LLVM BB %if.end.44
	    Live Ins: %X19
	    Predecessors according to CFG: BB#27 BB#28
2112B		B <BB#53>
	    Successors according to CFG: BB#53
> B <BB#53>
2128B	BB#30: derived from LLVM BB %if.end.45
	    Live Ins: %X19
	    Predecessors according to CFG: BB#24
2144B		%vreg63<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg63
2160B		%vreg62<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg62
2176B		STRWui %vreg63<kill>, %vreg62<kill>, 1256; mem:ST4[%avail_in] GPR32:%vreg63 GPR64common:%vreg62
2192B		%vreg59<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg59
2208B		%vreg58<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg58
2224B		STRXui %vreg59<kill>, %vreg58<kill>, 627; mem:ST8[%next_in] GPR64:%vreg59 GPR64common:%vreg58
	    Successors according to CFG: BB#31
> %W8<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3]
> %X9<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> STRWui %W8<kill>, %X9<kill>, 1256; mem:ST4[%avail_in]
> %X8<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2]
> %X9<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> STRXui %X8<kill>, %X9<kill>, 627; mem:ST8[%next_in]
2240B	BB#31: derived from LLVM BB %while.body
	    Live Ins: %X19
	    Predecessors according to CFG: BB#30 BB#52
2288B		%vreg83<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg83
2296B		%vreg81<def> = MOVi32imm 5000; GPR32:%vreg81
2304B		STRWui %vreg81<kill>, %vreg83<kill>, 1262; mem:ST4[%avail_out] GPR32:%vreg81 GPR64common:%vreg83
2320B		%vreg80<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg80
2352B		%vreg76<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg76
2360B		%vreg79<def> = ADDXri %vreg80<kill>, 8, 0; GPR64common:%vreg79,%vreg80
2368B		STRXui %vreg79<kill>, %vreg76<kill>, 630; mem:ST8[%next_out] GPR64common:%vreg79,%vreg76
2384B		%vreg73<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg73
2400B		%vreg71<def> = MOVi64imm 5016; GPR64:%vreg71
2416B		%vreg72<def> = ADDXrr %vreg73<kill>, %vreg71<kill>; GPR64:%vreg72,%vreg73,%vreg71
2432B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2440B		%W1<def> = COPY %WZR
2448B		%X0<def> = COPY %vreg72<kill>; GPR64:%vreg72
2480B		BL <ga:@BZ2_bzCompress>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %W0<imp-def>
2496B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2512B		%vreg69<def> = COPY %W0; GPR32:%vreg69
2528B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2544B		STACKMAP 2, 0, 0, <fi#0>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4)
2560B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2576B		STRWui %vreg69<kill>, <fi#6>, 0; mem:ST4[FixedStack6] GPR32:%vreg69
2592B		%vreg65<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32common:%vreg65
2608B		%WZR<def> = SUBSWri %vreg65<kill>, 1, 0, %NZCV<imp-def>; GPR32common:%vreg65
2624B		Bcc 0, <BB#37>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#37 BB#32
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> %W9<def> = MOVi32imm 5000
> STRWui %W9<kill>, %X8<kill>, 1262; mem:ST4[%avail_out]
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> %X9<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> %X8<def> = ADDXri %X8<kill>, 8, 0
> STRXui %X8<kill>, %X9<kill>, 630; mem:ST8[%next_out]
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> %X9<def> = MOVi64imm 5016
> %X0<def> = ADDXrr %X8<kill>, %X9<kill>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %W1<def> = COPY %WZR
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BL <ga:@BZ2_bzCompress>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %W0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = COPY %W0
Deleting identity copy.
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 2, 0, 0, <fi#0>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRWui %W0<kill>, <fi#6>, 0; mem:ST4[FixedStack6]
> %W8<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6]
> %WZR<def> = SUBSWri %W8<kill>, 1, 0, %NZCV<imp-def>
> Bcc 0, <BB#37>, %NZCV<imp-use,kill>
2640B	BB#32: derived from LLVM BB %if.then.53
	    Live Ins: %X19
	    Predecessors according to CFG: BB#31
2656B		%vreg148<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg148
2672B		CBZX %vreg148<kill>, <BB#34>; GPR64:%vreg148
	    Successors according to CFG: BB#34 BB#33
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> CBZX %X8<kill>, <BB#34>
2688B	BB#33: derived from LLVM BB %if.then.55
	    Live Ins: %X19
	    Predecessors according to CFG: BB#32
2704B		%vreg152<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg152
2720B		%vreg151<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg151
2736B		STRWui %vreg152<kill>, %vreg151<kill>, 0; mem:ST4[%41] GPR32:%vreg152 GPR64common:%vreg151
	    Successors according to CFG: BB#34
> %W8<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6]
> %X9<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> STRWui %W8<kill>, %X9<kill>, 0; mem:ST4[%41]
2752B	BB#34: derived from LLVM BB %if.end.56
	    Live Ins: %X19
	    Predecessors according to CFG: BB#32 BB#33
2768B		%vreg154<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg154
2784B		CBZX %vreg154<kill>, <BB#36>; GPR64:%vreg154
	    Successors according to CFG: BB#36 BB#35
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> CBZX %X8<kill>, <BB#36>
2800B	BB#35: derived from LLVM BB %if.then.58
	    Live Ins: %X19
	    Predecessors according to CFG: BB#34
2816B		%vreg158<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg158
2832B		%vreg157<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg157
2848B		STRWui %vreg158<kill>, %vreg157<kill>, 1274; mem:ST4[%lastErr59] GPR32:%vreg158 GPR64common:%vreg157
	    Successors according to CFG: BB#36
> %W8<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6]
> %X9<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> STRWui %W8<kill>, %X9<kill>, 1274; mem:ST4[%lastErr59]
2864B	BB#36: derived from LLVM BB %if.end.60
	    Live Ins: %X19
	    Predecessors according to CFG: BB#34 BB#35
2880B		B <BB#53>
	    Successors according to CFG: BB#53
> B <BB#53>
2896B	BB#37: derived from LLVM BB %if.end.61
	    Live Ins: %X19
	    Predecessors according to CFG: BB#31
2928B		%vreg88<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg88
2944B		%vreg87<def> = LDRWui %vreg88<kill>, 1262; mem:LD4[%avail_out63] GPR32:%vreg87 GPR64common:%vreg88
2952B		%vreg85<def> = MOVi32imm 5000; GPR32:%vreg85
2960B		%WZR<def> = SUBSWrr %vreg87<kill>, %vreg85<kill>, %NZCV<imp-def>; GPR32:%vreg87,%vreg85
2976B		Bcc 2, <BB#46>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#46 BB#38
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> %W8<def> = LDRWui %X8<kill>, 1262; mem:LD4[%avail_out63]
> %W9<def> = MOVi32imm 5000
> %WZR<def> = SUBSWrr %W8<kill>, %W9<kill>, %NZCV<imp-def>
> Bcc 2, <BB#46>, %NZCV<imp-use,kill>
2992B	BB#38: derived from LLVM BB %if.then.65
	    Live Ins: %X19
	    Predecessors according to CFG: BB#37
3040B		%vreg118<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg118
3056B		%vreg117<def> = LDRWui %vreg118<kill>, 1262; mem:LD4[%avail_out67] GPR32:%vreg117 GPR64common:%vreg118
3064B		%vreg113<def> = MOVi32imm 5000; GPR32:%vreg113
3072B		%vreg115<def> = SUBWrr %vreg113<kill>, %vreg117<kill>; GPR32:%vreg115,%vreg113,%vreg117
3088B		STRWui %vreg115<kill>, <fi#4>, 0; mem:ST4[FixedStack4] GPR32:%vreg115
3152B		%vreg103<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg103
3156B		%vreg111<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg111
3160B		%vreg107<def> = LDRSWui <fi#4>, 0; mem:LD4[FixedStack4] GPR64:%vreg107
3168B		%vreg102<def> = LDRXui %vreg103<kill>, 0; mem:LD8[%handle70] GPR64:%vreg102 GPR64common:%vreg103
3176B		%vreg110<def> = ADDXri %vreg111<kill>, 8, 0; GPR64sp:%vreg110 GPR64common:%vreg111
3184B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3192B		%X1<def> = MOVi64imm 1
3200B		%X0<def> = COPY %vreg110<kill>; GPR64sp:%vreg110
3232B		%X2<def> = COPY %vreg107<kill>; GPR64:%vreg107
3248B		%X3<def> = COPY %vreg102<kill>; GPR64:%vreg102
3264B		BL <ga:@fwrite>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %X2<imp-use>, %X3<imp-use>, %X0<imp-def>
3280B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3296B		%vreg100<def> = COPY %X0; GPR64:%vreg100
3312B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3328B		STACKMAP 3, 0, 0, <fi#0>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4)
3344B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3376B		STRWui %vreg100:sub_32<kill>, <fi#5>, 0; mem:ST4[FixedStack5] GPR64:%vreg100
3392B		%vreg92<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg92
3408B		%vreg91<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32:%vreg91
3424B		%WZR<def> = SUBSWrr %vreg92<kill>, %vreg91<kill>, %NZCV<imp-def>; GPR32:%vreg92,%vreg91
3440B		Bcc 1, <BB#40>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#40 BB#39
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> %W8<def> = LDRWui %X8<kill>, 1262; mem:LD4[%avail_out67]
> %W9<def> = MOVi32imm 5000
> %W8<def> = SUBWrr %W9<kill>, %W8<kill>
> STRWui %W8<kill>, <fi#4>, 0; mem:ST4[FixedStack4]
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> %X9<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> %X2<def> = LDRSWui <fi#4>, 0; mem:LD4[FixedStack4]
> %X3<def> = LDRXui %X8<kill>, 0; mem:LD8[%handle70]
> %X0<def> = ADDXri %X9<kill>, 8, 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X1<def> = MOVi64imm 1
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X2<def> = COPY %X2<kill>
Deleting identity copy.
> %X3<def> = COPY %X3<kill>
Deleting identity copy.
> BL <ga:@fwrite>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %X2<imp-use>, %X3<imp-use>, %X0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0
Deleting identity copy.
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 3, 0, 0, <fi#0>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRWui %W0, <fi#5>, 0, %X0<imp-use,kill>; mem:ST4[FixedStack5]
> %W8<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4]
> %W9<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5]
> %WZR<def> = SUBSWrr %W8<kill>, %W9<kill>, %NZCV<imp-def>
> Bcc 1, <BB#40>, %NZCV<imp-use,kill>
3456B	BB#39: derived from LLVM BB %lor.lhs.false.75
	    Live Ins: %X19
	    Predecessors according to CFG: BB#38
3472B		%vreg124<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg124
3488B		%vreg123<def> = LDRXui %vreg124<kill>, 0; mem:LD8[%handle76] GPR64:%vreg123 GPR64common:%vreg124
3504B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3520B		%X0<def> = COPY %vreg123<kill>; GPR64:%vreg123
3536B		BL <ga:@ferror>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
3552B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3568B		%vreg121<def> = COPY %W0; GPR32:%vreg121
3584B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3600B		STACKMAP 4, 0, 0, <fi#0>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4)
3616B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3632B		CBZW %vreg121<kill>, <BB#45>; GPR32:%vreg121
	    Successors according to CFG: BB#45 BB#40
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> %X0<def> = LDRXui %X8<kill>, 0; mem:LD8[%handle76]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BL <ga:@ferror>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = COPY %W0
Deleting identity copy.
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 4, 0, 0, <fi#0>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> CBZW %W0<kill>, <BB#45>
3648B	BB#40: derived from LLVM BB %if.then.79
	    Live Ins: %X19
	    Predecessors according to CFG: BB#38 BB#39
3664B		%vreg138<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg138
3680B		CBZX %vreg138<kill>, <BB#42>; GPR64:%vreg138
	    Successors according to CFG: BB#42 BB#41
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> CBZX %X8<kill>, <BB#42>
3696B	BB#41: derived from LLVM BB %if.then.82
	    Live Ins: %X19
	    Predecessors according to CFG: BB#40
3728B		%vreg141<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg141
3736B		%vreg139<def> = MOVi32imm 4294967290; GPR32:%vreg139
3744B		STRWui %vreg139<kill>, %vreg141<kill>, 0; mem:ST4[%58] GPR32:%vreg139 GPR64common:%vreg141
	    Successors according to CFG: BB#42
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %W9<def> = MOVi32imm 4294967290
> STRWui %W9<kill>, %X8<kill>, 0; mem:ST4[%58]
3760B	BB#42: derived from LLVM BB %if.end.83
	    Live Ins: %X19
	    Predecessors according to CFG: BB#40 BB#41
3776B		%vreg143<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg143
3792B		CBZX %vreg143<kill>, <BB#44>; GPR64:%vreg143
	    Successors according to CFG: BB#44 BB#43
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> CBZX %X8<kill>, <BB#44>
3808B	BB#43: derived from LLVM BB %if.then.86
	    Live Ins: %X19
	    Predecessors according to CFG: BB#42
3840B		%vreg146<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg146
3848B		%vreg144<def> = MOVi32imm 4294967290; GPR32:%vreg144
3856B		STRWui %vreg144<kill>, %vreg146<kill>, 1274; mem:ST4[%lastErr87] GPR32:%vreg144 GPR64common:%vreg146
	    Successors according to CFG: BB#44
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> %W9<def> = MOVi32imm 4294967290
> STRWui %W9<kill>, %X8<kill>, 1274; mem:ST4[%lastErr87]
3872B	BB#44: derived from LLVM BB %if.end.88
	    Live Ins: %X19
	    Predecessors according to CFG: BB#42 BB#43
3888B		B <BB#53>
	    Successors according to CFG: BB#53
> B <BB#53>
3904B	BB#45: derived from LLVM BB %if.end.89
	    Live Ins: %X19
	    Predecessors according to CFG: BB#39
3920B		B <BB#46>
	    Successors according to CFG: BB#46
> B <BB#46>
3936B	BB#46: derived from LLVM BB %if.end.90
	    Live Ins: %X19
	    Predecessors according to CFG: BB#37 BB#45
3952B		%vreg128<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg128
3968B		%vreg127<def> = LDRWui %vreg128<kill>, 1256; mem:LD4[%avail_in92] GPR32:%vreg127 GPR64common:%vreg128
3984B		CBNZW %vreg127<kill>, <BB#52>; GPR32:%vreg127
	    Successors according to CFG: BB#52 BB#47
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> %W8<def> = LDRWui %X8<kill>, 1256; mem:LD4[%avail_in92]
> CBNZW %W8<kill>, <BB#52>
4000B	BB#47: derived from LLVM BB %if.then.95
	    Live Ins: %X19
	    Predecessors according to CFG: BB#46
4016B		%vreg130<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg130
4032B		CBZX %vreg130<kill>, <BB#49>; GPR64:%vreg130
	    Successors according to CFG: BB#49 BB#48
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> CBZX %X8<kill>, <BB#49>
4048B	BB#48: derived from LLVM BB %if.then.98
	    Live Ins: %X19
	    Predecessors according to CFG: BB#47
4064B		%vreg132<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg132
4080B		STRWui %WZR, %vreg132<kill>, 0; mem:ST4[%64] GPR64common:%vreg132
	    Successors according to CFG: BB#49
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> STRWui %WZR, %X8<kill>, 0; mem:ST4[%64]
4096B	BB#49: derived from LLVM BB %if.end.99
	    Live Ins: %X19
	    Predecessors according to CFG: BB#47 BB#48
4112B		%vreg134<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg134
4128B		CBZX %vreg134<kill>, <BB#51>; GPR64:%vreg134
	    Successors according to CFG: BB#51 BB#50
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> CBZX %X8<kill>, <BB#51>
4144B	BB#50: derived from LLVM BB %if.then.102
	    Live Ins: %X19
	    Predecessors according to CFG: BB#49
4160B		%vreg136<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg136
4176B		STRWui %WZR, %vreg136<kill>, 1274; mem:ST4[%lastErr103] GPR64common:%vreg136
	    Successors according to CFG: BB#51
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> STRWui %WZR, %X8<kill>, 1274; mem:ST4[%lastErr103]
4192B	BB#51: derived from LLVM BB %if.end.104
	    Live Ins: %X19
	    Predecessors according to CFG: BB#49 BB#50
4208B		B <BB#53>
	    Successors according to CFG: BB#53
> B <BB#53>
4224B	BB#52: derived from LLVM BB %if.end.105
	    Live Ins: %X19
	    Predecessors according to CFG: BB#46
4240B		B <BB#31>
	    Successors according to CFG: BB#31
> B <BB#31>
4256B	BB#53: derived from LLVM BB %return
	    Live Ins: %X19
	    Predecessors according to CFG: BB#17 BB#51 BB#44 BB#36 BB#29 BB#23 BB#11
4272B		%vreg187<def> = ADRP <ga:@BZ2_bzWrite>[TF=1]; GPR64common:%vreg187
4288B		%vreg189<def> = ADDXri %vreg187<kill>, <ga:@BZ2_bzWrite>[TF=34], 0; GPR64sp:%vreg189 GPR64common:%vreg187
4336B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4352B		%X0<def> = COPY %vreg189<kill>; GPR64sp:%vreg189
4368B		%X1<def> = COPY %vreg17<kill>; GPR64:%vreg17
4384B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
4400B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4416B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4432B		STACKMAP 5, 0, %LR<earlyclobber,imp-def,dead>, ...
4448B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4464B		RET_ReallyLR
> %X8<def> = ADRP <ga:@BZ2_bzWrite>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@BZ2_bzWrite>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19<kill>
> BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 5, 0, %LR<earlyclobber,imp-def,dead>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> RET_ReallyLR
Computing live-in reg-units in ABI blocks.
0B	BB#0 W0#0 W1#0 W2#0 W3#0 W4#0 W30#0
Created 6 new intervals.
********** INTERVALS **********
W30 [0B,16r:0)[304r,304d:2)[368e,368d:1)[688r,688d:3)[784e,784d:4)[880r,880d:5)[928e,928d:6)  0@0B-phi 1@368e 2@304r 3@688r 4@784e 5@880r 6@928e
W0 [0B,96r:0)[272r,304r:1)[576r,688r:2)[848r,880r:3)  0@0B-phi 1@272r 2@576r 3@848r
W1 [0B,80r:0)[288r,304r:1)[592r,688r:2)[864r,880r:3)  0@0B-phi 1@288r 2@592r 3@864r
W2 [0B,64r:0)[608r,688r:1)  0@0B-phi 1@608r
W3 [0B,48r:0)[624r,688r:1)  0@0B-phi 1@624r
W4 [0B,32r:0)[640r,688r:1)  0@0B-phi 1@640r
%vreg0 [96r,112r:0)  0@96r
%vreg1 [112r,400r:0)  0@112r
%vreg2 [80r,128r:0)  0@80r
%vreg3 [128r,416r:0)  0@128r
%vreg4 [64r,144r:0)  0@64r
%vreg5 [144r,432r:0)  0@144r
%vreg6 [48r,160r:0)  0@48r
%vreg7 [160r,448r:0)  0@160r
%vreg8 [32r,176r:0)  0@32r
%vreg9 [176r,464r:0)  0@176r
%vreg10 [720r,736r:0)  0@720r
%vreg11 [736r,752r:0)  0@736r
%vreg12 [752r,848r:0)  0@752r
%vreg13 [816r,864r:0)  0@816r
%vreg14 [16r,816r:0)  0@16r
%vreg19 [336r,672r:0)  0@336r
%vreg21 [544r,656r:0)  0@544r
%vreg22 [528r,624r:0)  0@528r
%vreg23 [512r,608r:0)  0@512r
%vreg24 [496r,592r:0)  0@496r
%vreg25 [480r,576r:0)  0@480r
%vreg26 [192r,208r:0)  0@192r
%vreg27 [208r,224r:0)  0@208r
%vreg28 [224r,272r:0)  0@224r
%vreg29 [240r,288r:0)  0@240r
RegMasks: 304r 688r 880r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzWriteClose: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=4, align=4, at location [SP]
  fi#3: size=8, align=8, at location [SP]
  fi#4: size=8, align=8, at location [SP]
Function Live Ins: %X0 in %vreg0, %X1 in %vreg2, %W2 in %vreg4, %X3 in %vreg6, %X4 in %vreg8, %LR in %vreg14

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %X1 %W2 %X3 %X4 %LR
16B		%vreg14<def> = COPY %LR; GPR64:%vreg14
32B		%vreg8<def> = COPY %X4; GPR64:%vreg8
48B		%vreg6<def> = COPY %X3; GPR64:%vreg6
64B		%vreg4<def> = COPY %W2; GPR32:%vreg4
80B		%vreg2<def> = COPY %X1; GPR64:%vreg2
96B		%vreg0<def> = COPY %X0; GPR64:%vreg0
112B		%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
128B		%vreg3<def> = COPY %vreg2; GPR64:%vreg3,%vreg2
144B		%vreg5<def> = COPY %vreg4; GPR32:%vreg5,%vreg4
160B		%vreg7<def> = COPY %vreg6; GPR64:%vreg7,%vreg6
176B		%vreg9<def> = COPY %vreg8; GPR64:%vreg9,%vreg8
192B		%vreg26<def> = ADRP <ga:@BZ2_bzWriteClose>[TF=1]; GPR64common:%vreg26
208B		%vreg27<def> = ADDXri %vreg26, <ga:@BZ2_bzWriteClose>[TF=34], 0; GPR64sp:%vreg27 GPR64common:%vreg26
224B		%vreg28<def> = COPY %vreg27; GPR64all:%vreg28 GPR64sp:%vreg27
240B		%vreg29<def> = COPY %vreg14; GPR64all:%vreg29 GPR64:%vreg14
256B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
272B		%X0<def> = COPY %vreg28; GPR64all:%vreg28
288B		%X1<def> = COPY %vreg29; GPR64all:%vreg29
304B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
320B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
336B		%vreg19<def> = COPY %XZR; GPR64:%vreg19
352B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
368B		STACKMAP 0, 0, %vreg5, 0, <fi#2>, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, %vreg7, 0, <fi#3>, 0, %vreg9, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack3] LD8[FixedStack4] GPR32:%vreg5 GPR64:%vreg3,%vreg1,%vreg7,%vreg9
384B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
400B		STRXui %vreg1, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg1
416B		STRXui %vreg3, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg3
432B		STRWui %vreg5, <fi#2>, 0; mem:ST4[FixedStack2] GPR32:%vreg5
448B		STRXui %vreg7, <fi#3>, 0; mem:ST8[FixedStack3] GPR64:%vreg7
464B		STRXui %vreg9, <fi#4>, 0; mem:ST8[FixedStack4] GPR64:%vreg9
480B		%vreg25<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg25
496B		%vreg24<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg24
512B		%vreg23<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg23
528B		%vreg22<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg22
544B		%vreg21<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64:%vreg21
560B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
576B		%X0<def> = COPY %vreg25; GPR64:%vreg25
592B		%X1<def> = COPY %vreg24; GPR64:%vreg24
608B		%W2<def> = COPY %vreg23; GPR32:%vreg23
624B		%X3<def> = COPY %vreg22; GPR64:%vreg22
640B		%X4<def> = COPY %vreg19; GPR64:%vreg19
656B		%X5<def> = COPY %vreg21; GPR64:%vreg21
672B		%X6<def> = COPY %vreg19; GPR64:%vreg19
688B		BL <ga:@BZ2_bzWriteClose64>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %W2<imp-use>, %X3<imp-use>, %X4<imp-use>, %X5<imp-use,kill>, %X6<imp-use,kill>
704B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
720B		%vreg10<def> = ADRP <ga:@BZ2_bzWriteClose>[TF=1]; GPR64common:%vreg10
736B		%vreg11<def> = ADDXri %vreg10, <ga:@BZ2_bzWriteClose>[TF=34], 0; GPR64sp:%vreg11 GPR64common:%vreg10
752B		%vreg12<def> = COPY %vreg11; GPR64all:%vreg12 GPR64sp:%vreg11
768B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
784B		STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...
800B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
816B		%vreg13<def> = COPY %vreg14; GPR64all:%vreg13 GPR64:%vreg14
832B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
848B		%X0<def> = COPY %vreg12; GPR64all:%vreg12
864B		%X1<def> = COPY %vreg13; GPR64all:%vreg13
880B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
896B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
912B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
928B		STACKMAP 2, 0, %LR<earlyclobber,imp-def,dead>, ...
944B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
960B		RET_ReallyLR

# End machine code for function BZ2_bzWriteClose.

********** SIMPLE REGISTER COALESCING **********
********** Function: BZ2_bzWriteClose
********** JOINING INTERVALS ***********
entry:
16B	%vreg14<def> = COPY %LR; GPR64:%vreg14
	Considering merging %vreg14 with %LR
	Can only merge into reserved registers.
32B	%vreg8<def> = COPY %X4; GPR64:%vreg8
	Considering merging %vreg8 with %X4
	Can only merge into reserved registers.
48B	%vreg6<def> = COPY %X3; GPR64:%vreg6
	Considering merging %vreg6 with %X3
	Can only merge into reserved registers.
64B	%vreg4<def> = COPY %W2; GPR32:%vreg4
	Considering merging %vreg4 with %W2
	Can only merge into reserved registers.
80B	%vreg2<def> = COPY %X1; GPR64:%vreg2
	Considering merging %vreg2 with %X1
	Can only merge into reserved registers.
96B	%vreg0<def> = COPY %X0; GPR64:%vreg0
	Considering merging %vreg0 with %X0
	Can only merge into reserved registers.
272B	%X0<def> = COPY %vreg28; GPR64all:%vreg28
	Considering merging %vreg28 with %X0
	Can only merge into reserved registers.
288B	%X1<def> = COPY %vreg29; GPR64all:%vreg29
	Considering merging %vreg29 with %X1
	Can only merge into reserved registers.
336B	%vreg19<def> = COPY %XZR; GPR64:%vreg19
	Considering merging %vreg19 with %XZR
		RHS = %vreg19 [336r,672r:0)  0@336r
		updated: 640B	%X4<def> = COPY %XZR
		updated: 672B	%X6<def> = COPY %XZR
	Success: %vreg19 -> %XZR
	Result = %XZR
576B	%X0<def> = COPY %vreg25; GPR64:%vreg25
	Considering merging %vreg25 with %X0
	Can only merge into reserved registers.
592B	%X1<def> = COPY %vreg24; GPR64:%vreg24
	Considering merging %vreg24 with %X1
	Can only merge into reserved registers.
608B	%W2<def> = COPY %vreg23; GPR32:%vreg23
	Considering merging %vreg23 with %W2
	Can only merge into reserved registers.
624B	%X3<def> = COPY %vreg22; GPR64:%vreg22
	Considering merging %vreg22 with %X3
	Can only merge into reserved registers.
640B	%X4<def> = COPY %XZR
	Not coalescable.
656B	%X5<def> = COPY %vreg21; GPR64:%vreg21
	Considering merging %vreg21 with %X5
	Can only merge into reserved registers.
672B	%X6<def> = COPY %XZR
	Not coalescable.
848B	%X0<def> = COPY %vreg12; GPR64all:%vreg12
	Considering merging %vreg12 with %X0
	Can only merge into reserved registers.
864B	%X1<def> = COPY %vreg13; GPR64all:%vreg13
	Considering merging %vreg13 with %X1
	Can only merge into reserved registers.
112B	%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
	Considering merging to GPR64 with %vreg0 in %vreg1
		RHS = %vreg0 [96r,112r:0)  0@96r
		LHS = %vreg1 [112r,400r:0)  0@112r
		merge %vreg1:0@112r into %vreg0:0@96r --> @96r
		erased:	112r	%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
		updated: 96B	%vreg1<def> = COPY %X0; GPR64:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [96r,400r:0)  0@96r
128B	%vreg3<def> = COPY %vreg2; GPR64:%vreg3,%vreg2
	Considering merging to GPR64 with %vreg2 in %vreg3
		RHS = %vreg2 [80r,128r:0)  0@80r
		LHS = %vreg3 [128r,416r:0)  0@128r
		merge %vreg3:0@128r into %vreg2:0@80r --> @80r
		erased:	128r	%vreg3<def> = COPY %vreg2; GPR64:%vreg3,%vreg2
		updated: 80B	%vreg3<def> = COPY %X1; GPR64:%vreg3
	Success: %vreg2 -> %vreg3
	Result = %vreg3 [80r,416r:0)  0@80r
144B	%vreg5<def> = COPY %vreg4; GPR32:%vreg5,%vreg4
	Considering merging to GPR32 with %vreg4 in %vreg5
		RHS = %vreg4 [64r,144r:0)  0@64r
		LHS = %vreg5 [144r,432r:0)  0@144r
		merge %vreg5:0@144r into %vreg4:0@64r --> @64r
		erased:	144r	%vreg5<def> = COPY %vreg4; GPR32:%vreg5,%vreg4
		updated: 64B	%vreg5<def> = COPY %W2; GPR32:%vreg5
	Success: %vreg4 -> %vreg5
	Result = %vreg5 [64r,432r:0)  0@64r
160B	%vreg7<def> = COPY %vreg6; GPR64:%vreg7,%vreg6
	Considering merging to GPR64 with %vreg6 in %vreg7
		RHS = %vreg6 [48r,160r:0)  0@48r
		LHS = %vreg7 [160r,448r:0)  0@160r
		merge %vreg7:0@160r into %vreg6:0@48r --> @48r
		erased:	160r	%vreg7<def> = COPY %vreg6; GPR64:%vreg7,%vreg6
		updated: 48B	%vreg7<def> = COPY %X3; GPR64:%vreg7
	Success: %vreg6 -> %vreg7
	Result = %vreg7 [48r,448r:0)  0@48r
176B	%vreg9<def> = COPY %vreg8; GPR64:%vreg9,%vreg8
	Considering merging to GPR64 with %vreg8 in %vreg9
		RHS = %vreg8 [32r,176r:0)  0@32r
		LHS = %vreg9 [176r,464r:0)  0@176r
		merge %vreg9:0@176r into %vreg8:0@32r --> @32r
		erased:	176r	%vreg9<def> = COPY %vreg8; GPR64:%vreg9,%vreg8
		updated: 32B	%vreg9<def> = COPY %X4; GPR64:%vreg9
	Success: %vreg8 -> %vreg9
	Result = %vreg9 [32r,464r:0)  0@32r
224B	%vreg28<def> = COPY %vreg27; GPR64all:%vreg28 GPR64sp:%vreg27
	Considering merging to GPR64sp with %vreg27 in %vreg28
		RHS = %vreg27 [208r,224r:0)  0@208r
		LHS = %vreg28 [224r,272r:0)  0@224r
		merge %vreg28:0@224r into %vreg27:0@208r --> @208r
		erased:	224r	%vreg28<def> = COPY %vreg27; GPR64all:%vreg28 GPR64sp:%vreg27
		updated: 208B	%vreg28<def> = ADDXri %vreg26, <ga:@BZ2_bzWriteClose>[TF=34], 0; GPR64sp:%vreg28 GPR64common:%vreg26
	Success: %vreg27 -> %vreg28
	Result = %vreg28 [208r,272r:0)  0@208r
240B	%vreg29<def> = COPY %vreg14; GPR64all:%vreg29 GPR64:%vreg14
	Considering merging to GPR64 with %vreg14 in %vreg29
		RHS = %vreg14 [16r,816r:0)  0@16r
		LHS = %vreg29 [240r,288r:0)  0@240r
		merge %vreg29:0@240r into %vreg14:0@16r --> @16r
		erased:	240r	%vreg29<def> = COPY %vreg14; GPR64all:%vreg29 GPR64:%vreg14
		updated: 16B	%vreg29<def> = COPY %LR; GPR64:%vreg29
		updated: 816B	%vreg13<def> = COPY %vreg29; GPR64all:%vreg13 GPR64:%vreg29
	Success: %vreg14 -> %vreg29
	Result = %vreg29 [16r,816r:0)  0@16r
752B	%vreg12<def> = COPY %vreg11; GPR64all:%vreg12 GPR64sp:%vreg11
	Considering merging to GPR64sp with %vreg11 in %vreg12
		RHS = %vreg11 [736r,752r:0)  0@736r
		LHS = %vreg12 [752r,848r:0)  0@752r
		merge %vreg12:0@752r into %vreg11:0@736r --> @736r
		erased:	752r	%vreg12<def> = COPY %vreg11; GPR64all:%vreg12 GPR64sp:%vreg11
		updated: 736B	%vreg12<def> = ADDXri %vreg10, <ga:@BZ2_bzWriteClose>[TF=34], 0; GPR64sp:%vreg12 GPR64common:%vreg10
	Success: %vreg11 -> %vreg12
	Result = %vreg12 [736r,848r:0)  0@736r
816B	%vreg13<def> = COPY %vreg29; GPR64all:%vreg13 GPR64:%vreg29
	Considering merging to GPR64 with %vreg29 in %vreg13
		RHS = %vreg29 [16r,816r:0)  0@16r
		LHS = %vreg13 [816r,864r:0)  0@816r
		merge %vreg13:0@816r into %vreg29:0@16r --> @16r
		erased:	816r	%vreg13<def> = COPY %vreg29; GPR64all:%vreg13 GPR64:%vreg29
		updated: 16B	%vreg13<def> = COPY %LR; GPR64:%vreg13
		updated: 288B	%X1<def> = COPY %vreg13; GPR64:%vreg13
	Success: %vreg29 -> %vreg13
	Result = %vreg13 [16r,864r:0)  0@16r
272B	%X0<def> = COPY %vreg28; GPR64sp:%vreg28
	Considering merging %vreg28 with %X0
	Can only merge into reserved registers.
288B	%X1<def> = COPY %vreg13; GPR64:%vreg13
	Considering merging %vreg13 with %X1
	Can only merge into reserved registers.
848B	%X0<def> = COPY %vreg12; GPR64sp:%vreg12
	Considering merging %vreg12 with %X0
	Can only merge into reserved registers.
864B	%X1<def> = COPY %vreg13; GPR64:%vreg13
	Considering merging %vreg13 with %X1
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
W30 [0B,16r:0)[304r,304d:2)[368e,368d:1)[688r,688d:3)[784e,784d:4)[880r,880d:5)[928e,928d:6)  0@0B-phi 1@368e 2@304r 3@688r 4@784e 5@880r 6@928e
WZR EMPTY
W0 [0B,96r:0)[272r,304r:1)[576r,688r:2)[848r,880r:3)  0@0B-phi 1@272r 2@576r 3@848r
W1 [0B,80r:0)[288r,304r:1)[592r,688r:2)[864r,880r:3)  0@0B-phi 1@288r 2@592r 3@864r
W2 [0B,64r:0)[608r,688r:1)  0@0B-phi 1@608r
W3 [0B,48r:0)[624r,688r:1)  0@0B-phi 1@624r
W4 [0B,32r:0)[640r,688r:1)  0@0B-phi 1@640r
%vreg1 [96r,400r:0)  0@96r
%vreg3 [80r,416r:0)  0@80r
%vreg5 [64r,432r:0)  0@64r
%vreg7 [48r,448r:0)  0@48r
%vreg9 [32r,464r:0)  0@32r
%vreg10 [720r,736r:0)  0@720r
%vreg12 [736r,848r:0)  0@736r
%vreg13 [16r,864r:0)  0@16r
%vreg21 [544r,656r:0)  0@544r
%vreg22 [528r,624r:0)  0@528r
%vreg23 [512r,608r:0)  0@512r
%vreg24 [496r,592r:0)  0@496r
%vreg25 [480r,576r:0)  0@480r
%vreg26 [192r,208r:0)  0@192r
%vreg28 [208r,272r:0)  0@208r
RegMasks: 304r 688r 880r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzWriteClose: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=4, align=4, at location [SP]
  fi#3: size=8, align=8, at location [SP]
  fi#4: size=8, align=8, at location [SP]
Function Live Ins: %X0 in %vreg0, %X1 in %vreg2, %W2 in %vreg4, %X3 in %vreg6, %X4 in %vreg8, %LR in %vreg14

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %X1 %W2 %X3 %X4 %LR
16B		%vreg13<def> = COPY %LR; GPR64:%vreg13
32B		%vreg9<def> = COPY %X4; GPR64:%vreg9
48B		%vreg7<def> = COPY %X3; GPR64:%vreg7
64B		%vreg5<def> = COPY %W2; GPR32:%vreg5
80B		%vreg3<def> = COPY %X1; GPR64:%vreg3
96B		%vreg1<def> = COPY %X0; GPR64:%vreg1
192B		%vreg26<def> = ADRP <ga:@BZ2_bzWriteClose>[TF=1]; GPR64common:%vreg26
208B		%vreg28<def> = ADDXri %vreg26, <ga:@BZ2_bzWriteClose>[TF=34], 0; GPR64sp:%vreg28 GPR64common:%vreg26
256B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
272B		%X0<def> = COPY %vreg28; GPR64sp:%vreg28
288B		%X1<def> = COPY %vreg13; GPR64:%vreg13
304B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
320B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
352B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
368B		STACKMAP 0, 0, %vreg5, 0, <fi#2>, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, %vreg7, 0, <fi#3>, 0, %vreg9, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack3] LD8[FixedStack4] GPR32:%vreg5 GPR64:%vreg3,%vreg1,%vreg7,%vreg9
384B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
400B		STRXui %vreg1, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg1
416B		STRXui %vreg3, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg3
432B		STRWui %vreg5, <fi#2>, 0; mem:ST4[FixedStack2] GPR32:%vreg5
448B		STRXui %vreg7, <fi#3>, 0; mem:ST8[FixedStack3] GPR64:%vreg7
464B		STRXui %vreg9, <fi#4>, 0; mem:ST8[FixedStack4] GPR64:%vreg9
480B		%vreg25<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg25
496B		%vreg24<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg24
512B		%vreg23<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg23
528B		%vreg22<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg22
544B		%vreg21<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64:%vreg21
560B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
576B		%X0<def> = COPY %vreg25; GPR64:%vreg25
592B		%X1<def> = COPY %vreg24; GPR64:%vreg24
608B		%W2<def> = COPY %vreg23; GPR32:%vreg23
624B		%X3<def> = COPY %vreg22; GPR64:%vreg22
640B		%X4<def> = COPY %XZR
656B		%X5<def> = COPY %vreg21; GPR64:%vreg21
672B		%X6<def> = COPY %XZR
688B		BL <ga:@BZ2_bzWriteClose64>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %W2<imp-use>, %X3<imp-use>, %X4<imp-use>, %X5<imp-use,kill>, %X6<imp-use,kill>
704B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
720B		%vreg10<def> = ADRP <ga:@BZ2_bzWriteClose>[TF=1]; GPR64common:%vreg10
736B		%vreg12<def> = ADDXri %vreg10, <ga:@BZ2_bzWriteClose>[TF=34], 0; GPR64sp:%vreg12 GPR64common:%vreg10
768B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
784B		STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...
800B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
832B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
848B		%X0<def> = COPY %vreg12; GPR64sp:%vreg12
864B		%X1<def> = COPY %vreg13; GPR64:%vreg13
880B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
896B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
912B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
928B		STACKMAP 2, 0, %LR<earlyclobber,imp-def,dead>, ...
944B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
960B		RET_ReallyLR

# End machine code for function BZ2_bzWriteClose.

handleMove 640B -> 568B: %X4<def> = COPY %XZR
     W4:	[0B,32r:0)[640r,688r:1)  0@0B-phi 1@640r
        -->	[0B,32r:0)[568r,688r:1)  0@0B-phi 1@568r
     WZR:	EMPTY
        -->	EMPTY
handleMove 672B -> 572B: %X6<def> = COPY %XZR
     W6:	[572r,688r:0)  0@572r
        -->	[572r,688r:0)  0@572r
     WZR:	EMPTY
        -->	EMPTY
********** GREEDY REGISTER ALLOCATION **********
********** Function: BZ2_bzWriteClose
********** INTERVALS **********
W30 [0B,16r:0)[304r,304d:2)[368e,368d:1)[688r,688d:3)[784e,784d:4)[880r,880d:5)[928e,928d:6)  0@0B-phi 1@368e 2@304r 3@688r 4@784e 5@880r 6@928e
WZR EMPTY
W0 [0B,96r:0)[272r,304r:1)[576r,688r:2)[848r,880r:3)  0@0B-phi 1@272r 2@576r 3@848r
W1 [0B,80r:0)[288r,304r:1)[592r,688r:2)[864r,880r:3)  0@0B-phi 1@288r 2@592r 3@864r
W2 [0B,64r:0)[608r,688r:1)  0@0B-phi 1@608r
W3 [0B,48r:0)[624r,688r:1)  0@0B-phi 1@624r
W4 [0B,32r:0)[568r,688r:1)  0@0B-phi 1@568r
W6 [572r,688r:0)  0@572r
%vreg1 [96r,400r:0)  0@96r
%vreg3 [80r,416r:0)  0@80r
%vreg5 [64r,432r:0)  0@64r
%vreg7 [48r,448r:0)  0@48r
%vreg9 [32r,464r:0)  0@32r
%vreg10 [720r,736r:0)  0@720r
%vreg12 [736r,848r:0)  0@736r
%vreg13 [16r,864r:0)  0@16r
%vreg21 [544r,656r:0)  0@544r
%vreg22 [528r,624r:0)  0@528r
%vreg23 [512r,608r:0)  0@512r
%vreg24 [496r,592r:0)  0@496r
%vreg25 [480r,576r:0)  0@480r
%vreg26 [192r,208r:0)  0@192r
%vreg28 [208r,272r:0)  0@208r
RegMasks: 304r 688r 880r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzWriteClose: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=4, align=4, at location [SP]
  fi#3: size=8, align=8, at location [SP]
  fi#4: size=8, align=8, at location [SP]
Function Live Ins: %X0 in %vreg0, %X1 in %vreg2, %W2 in %vreg4, %X3 in %vreg6, %X4 in %vreg8, %LR in %vreg14

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %X1 %W2 %X3 %X4 %LR
16B		%vreg13<def> = COPY %LR; GPR64:%vreg13
32B		%vreg9<def> = COPY %X4; GPR64:%vreg9
48B		%vreg7<def> = COPY %X3; GPR64:%vreg7
64B		%vreg5<def> = COPY %W2; GPR32:%vreg5
80B		%vreg3<def> = COPY %X1; GPR64:%vreg3
96B		%vreg1<def> = COPY %X0; GPR64:%vreg1
192B		%vreg26<def> = ADRP <ga:@BZ2_bzWriteClose>[TF=1]; GPR64common:%vreg26
208B		%vreg28<def> = ADDXri %vreg26, <ga:@BZ2_bzWriteClose>[TF=34], 0; GPR64sp:%vreg28 GPR64common:%vreg26
256B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
272B		%X0<def> = COPY %vreg28; GPR64sp:%vreg28
288B		%X1<def> = COPY %vreg13; GPR64:%vreg13
304B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
320B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
352B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
368B		STACKMAP 0, 0, %vreg5, 0, <fi#2>, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, %vreg7, 0, <fi#3>, 0, %vreg9, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack3] LD8[FixedStack4] GPR32:%vreg5 GPR64:%vreg3,%vreg1,%vreg7,%vreg9
384B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
400B		STRXui %vreg1, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg1
416B		STRXui %vreg3, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg3
432B		STRWui %vreg5, <fi#2>, 0; mem:ST4[FixedStack2] GPR32:%vreg5
448B		STRXui %vreg7, <fi#3>, 0; mem:ST8[FixedStack3] GPR64:%vreg7
464B		STRXui %vreg9, <fi#4>, 0; mem:ST8[FixedStack4] GPR64:%vreg9
480B		%vreg25<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg25
496B		%vreg24<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg24
512B		%vreg23<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg23
528B		%vreg22<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg22
544B		%vreg21<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64:%vreg21
560B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
568B		%X4<def> = COPY %XZR
572B		%X6<def> = COPY %XZR
576B		%X0<def> = COPY %vreg25; GPR64:%vreg25
592B		%X1<def> = COPY %vreg24; GPR64:%vreg24
608B		%W2<def> = COPY %vreg23; GPR32:%vreg23
624B		%X3<def> = COPY %vreg22; GPR64:%vreg22
656B		%X5<def> = COPY %vreg21; GPR64:%vreg21
688B		BL <ga:@BZ2_bzWriteClose64>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %W2<imp-use>, %X3<imp-use>, %X4<imp-use>, %X5<imp-use,kill>, %X6<imp-use>
704B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
720B		%vreg10<def> = ADRP <ga:@BZ2_bzWriteClose>[TF=1]; GPR64common:%vreg10
736B		%vreg12<def> = ADDXri %vreg10, <ga:@BZ2_bzWriteClose>[TF=34], 0; GPR64sp:%vreg12 GPR64common:%vreg10
768B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
784B		STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...
800B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
832B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
848B		%X0<def> = COPY %vreg12; GPR64sp:%vreg12
864B		%X1<def> = COPY %vreg13; GPR64:%vreg13
880B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
896B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
912B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
928B		STACKMAP 2, 0, %LR<earlyclobber,imp-def,dead>, ...
944B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
960B		RET_ReallyLR

# End machine code for function BZ2_bzWriteClose.


selectOrSplit GPR64:%vreg13 [16r,864r:0)  0@16r w=2.427885e-03
hints: %X1
missed hint %X1
assigning %vreg13 to %X19: W19 [16r,864r:0)  0@16r

selectOrSplit GPR64:%vreg9 [32r,464r:0)  0@32r w=3.641827e-03
hints: %X4
missed hint %X4
assigning %vreg9 to %X20: W20 [32r,464r:0)  0@32r

selectOrSplit GPR64:%vreg7 [48r,448r:0)  0@48r w=3.787500e-03
hints: %X3
missed hint %X3
assigning %vreg7 to %X21: W21 [48r,448r:0)  0@48r

selectOrSplit GPR32:%vreg5 [64r,432r:0)  0@64r w=3.945312e-03
hints: %W2
missed hint %W2
assigning %vreg5 to %W22: W22 [64r,432r:0)  0@64r

selectOrSplit GPR64:%vreg3 [80r,416r:0)  0@80r w=4.116848e-03
hints: %X1
missed hint %X1
assigning %vreg3 to %X23: W23 [80r,416r:0)  0@80r

selectOrSplit GPR64:%vreg1 [96r,400r:0)  0@96r w=4.303977e-03
hints: %X0
missed hint %X0
assigning %vreg1 to %X24: W24 [96r,400r:0)  0@96r

selectOrSplit GPR64sp:%vreg28 [208r,272r:0)  0@208r w=4.353448e-03
hints: %X0
assigning %vreg28 to %X0: W0 [208r,272r:0)  0@208r

selectOrSplit GPR64:%vreg25 [480r,576r:0)  0@480r w=4.072580e-03
hints: %X0
assigning %vreg25 to %X0: W0 [480r,576r:0)  0@480r

selectOrSplit GPR64:%vreg24 [496r,592r:0)  0@496r w=4.072580e-03
hints: %X1
assigning %vreg24 to %X1: W1 [496r,592r:0)  0@496r

selectOrSplit GPR32:%vreg23 [512r,608r:0)  0@512r w=4.072580e-03
hints: %W2
assigning %vreg23 to %W2: W2 [512r,608r:0)  0@512r

selectOrSplit GPR64:%vreg22 [528r,624r:0)  0@528r w=4.072580e-03
hints: %X3
assigning %vreg22 to %X3: W3 [528r,624r:0)  0@528r

selectOrSplit GPR64:%vreg21 [544r,656r:0)  0@544r w=3.945312e-03
hints: %X5
assigning %vreg21 to %X5: W5 [544r,656r:0)  0@544r

selectOrSplit GPR64sp:%vreg12 [736r,848r:0)  0@736r w=3.945312e-03
hints: %X0
assigning %vreg12 to %X0: W0 [736r,848r:0)  0@736r

selectOrSplit GPR64common:%vreg26 [192r,208r:0)  0@192r w=inf
assigning %vreg26 to %X8: W8 [192r,208r:0)  0@192r

selectOrSplit GPR64common:%vreg10 [720r,736r:0)  0@720r w=inf
assigning %vreg10 to %X8: W8 [720r,736r:0)  0@720r

********** STACK TRANSFORMATION METADATA **********
********** Function: BZ2_bzWriteClose
********** REGISTER MAP **********
[%vreg1 -> %X24] GPR64
[%vreg3 -> %X23] GPR64
[%vreg5 -> %W22] GPR32
[%vreg7 -> %X21] GPR64
[%vreg9 -> %X20] GPR64
[%vreg10 -> %X8] GPR64common
[%vreg12 -> %X0] GPR64sp
[%vreg13 -> %X19] GPR64
[%vreg21 -> %X5] GPR64
[%vreg22 -> %X3] GPR64
[%vreg23 -> %W2] GPR32
[%vreg24 -> %X1] GPR64
[%vreg25 -> %X0] GPR64
[%vreg26 -> %X8] GPR64common
[%vreg28 -> %X0] GPR64sp


Stackmap 0:
  STACKMAP 0, 0, %vreg5, 0, <fi#2>, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, %vreg7, 0, <fi#3>, 0, %vreg9, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack3] LD8[FixedStack4] GPR32:%vreg5 GPR64:%vreg3,%vreg1,%vreg7,%vreg9

i32 %abandon: in register %W22 (vreg 5)
i32* %abandon.addr: in stack slot 2 (size: 4)
i8* %b: in register %X23 (vreg 3)
i8** %b.addr: in stack slot 1 (size: 8)
i32* %bzerror: in register %X24 (vreg 1)
i32** %bzerror.addr: in stack slot 0 (size: 8)
i32* %nbytes_in: in register %X21 (vreg 7)
i32** %nbytes_in.addr: in stack slot 3 (size: 8)
i32* %nbytes_out: in register %X20 (vreg 9)
i32** %nbytes_out.addr: in stack slot 4 (size: 8)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...


Duplicate operand locations:


Stackmap 2:
  STACKMAP 2, 0, %LR<earlyclobber,imp-def,dead>, ...


Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, %vreg5, 0, <fi#2>, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, %vreg7, 0, <fi#3>, 0, %vreg9, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack3] LD8[FixedStack4] GPR32:%vreg5 GPR64:%vreg3,%vreg1,%vreg7,%vreg9
  -> Call instruction SlotIndex 304B, searching vregs 0 -> 30 and stack slots 0 -> 5
    + vreg13 is live in register but not in stackmap
      Defining instruction: %vreg13<def> = COPY %LR; GPR64:%vreg13
      Value: generated value, 1 instruction(s)

  STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...
  -> Call instruction SlotIndex 688B, searching vregs 0 -> 30 and stack slots 0 -> 5
    + vreg13 is live in register but not in stackmap
      Defining instruction: %vreg13<def> = COPY %LR; GPR64:%vreg13
      Value: generated value, 1 instruction(s)

  STACKMAP 2, 0, %LR<earlyclobber,imp-def,dead>, ...
  -> Call instruction SlotIndex 880B, searching vregs 0 -> 30 and stack slots 0 -> 5

********** REWRITE VIRTUAL REGISTERS **********
********** Function: BZ2_bzWriteClose
********** REGISTER MAP **********
[%vreg1 -> %X24] GPR64
[%vreg3 -> %X23] GPR64
[%vreg5 -> %W22] GPR32
[%vreg7 -> %X21] GPR64
[%vreg9 -> %X20] GPR64
[%vreg10 -> %X8] GPR64common
[%vreg12 -> %X0] GPR64sp
[%vreg13 -> %X19] GPR64
[%vreg21 -> %X5] GPR64
[%vreg22 -> %X3] GPR64
[%vreg23 -> %W2] GPR32
[%vreg24 -> %X1] GPR64
[%vreg25 -> %X0] GPR64
[%vreg26 -> %X8] GPR64common
[%vreg28 -> %X0] GPR64sp

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %LR %W2 %X0 %X1 %X3 %X4
16B		%vreg13<def> = COPY %LR; GPR64:%vreg13
32B		%vreg9<def> = COPY %X4; GPR64:%vreg9
48B		%vreg7<def> = COPY %X3; GPR64:%vreg7
64B		%vreg5<def> = COPY %W2; GPR32:%vreg5
80B		%vreg3<def> = COPY %X1; GPR64:%vreg3
96B		%vreg1<def> = COPY %X0; GPR64:%vreg1
192B		%vreg26<def> = ADRP <ga:@BZ2_bzWriteClose>[TF=1]; GPR64common:%vreg26
208B		%vreg28<def> = ADDXri %vreg26<kill>, <ga:@BZ2_bzWriteClose>[TF=34], 0; GPR64sp:%vreg28 GPR64common:%vreg26
256B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
272B		%X0<def> = COPY %vreg28<kill>; GPR64sp:%vreg28
288B		%X1<def> = COPY %vreg13; GPR64:%vreg13
304B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
320B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
352B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
368B		STACKMAP 0, 0, %vreg5, 0, <fi#2>, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, %vreg7, 0, <fi#3>, 0, %vreg9, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack3] LD8[FixedStack4] GPR32:%vreg5 GPR64:%vreg3,%vreg1,%vreg7,%vreg9
384B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
400B		STRXui %vreg1<kill>, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg1
416B		STRXui %vreg3<kill>, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg3
432B		STRWui %vreg5<kill>, <fi#2>, 0; mem:ST4[FixedStack2] GPR32:%vreg5
448B		STRXui %vreg7<kill>, <fi#3>, 0; mem:ST8[FixedStack3] GPR64:%vreg7
464B		STRXui %vreg9<kill>, <fi#4>, 0; mem:ST8[FixedStack4] GPR64:%vreg9
480B		%vreg25<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg25
496B		%vreg24<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg24
512B		%vreg23<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg23
528B		%vreg22<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg22
544B		%vreg21<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64:%vreg21
560B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
568B		%X4<def> = COPY %XZR
572B		%X6<def> = COPY %XZR
576B		%X0<def> = COPY %vreg25<kill>; GPR64:%vreg25
592B		%X1<def> = COPY %vreg24<kill>; GPR64:%vreg24
608B		%W2<def> = COPY %vreg23<kill>; GPR32:%vreg23
624B		%X3<def> = COPY %vreg22<kill>; GPR64:%vreg22
656B		%X5<def> = COPY %vreg21<kill>; GPR64:%vreg21
688B		BL <ga:@BZ2_bzWriteClose64>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %W2<imp-use>, %X3<imp-use>, %X4<imp-use>, %X5<imp-use>, %X6<imp-use>
704B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
720B		%vreg10<def> = ADRP <ga:@BZ2_bzWriteClose>[TF=1]; GPR64common:%vreg10
736B		%vreg12<def> = ADDXri %vreg10<kill>, <ga:@BZ2_bzWriteClose>[TF=34], 0; GPR64sp:%vreg12 GPR64common:%vreg10
768B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
784B		STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...
800B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
832B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
848B		%X0<def> = COPY %vreg12<kill>; GPR64sp:%vreg12
864B		%X1<def> = COPY %vreg13<kill>; GPR64:%vreg13
880B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
896B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
912B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
928B		STACKMAP 2, 0, %LR<earlyclobber,imp-def,dead>, ...
944B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
960B		RET_ReallyLR
> %X19<def> = COPY %LR
> %X20<def> = COPY %X4
> %X21<def> = COPY %X3
> %W22<def> = COPY %W2
> %X23<def> = COPY %X1
> %X24<def> = COPY %X0
> %X8<def> = ADRP <ga:@BZ2_bzWriteClose>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@BZ2_bzWriteClose>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19
> BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 0, 0, %W22, 0, <fi#2>, 0, %X23, 0, <fi#1>, 0, %X24, 0, <fi#0>, 0, %X21, 0, <fi#3>, 0, %X20, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack3] LD8[FixedStack4]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRXui %X24<kill>, <fi#0>, 0; mem:ST8[FixedStack0]
> STRXui %X23<kill>, <fi#1>, 0; mem:ST8[FixedStack1]
> STRWui %W22<kill>, <fi#2>, 0; mem:ST4[FixedStack2]
> STRXui %X21<kill>, <fi#3>, 0; mem:ST8[FixedStack3]
> STRXui %X20<kill>, <fi#4>, 0; mem:ST8[FixedStack4]
> %X0<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %X1<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W2<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2]
> %X3<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> %X5<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X4<def> = COPY %XZR
> %X6<def> = COPY %XZR
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X1<kill>
Deleting identity copy.
> %W2<def> = COPY %W2<kill>
Deleting identity copy.
> %X3<def> = COPY %X3<kill>
Deleting identity copy.
> %X5<def> = COPY %X5<kill>
Deleting identity copy.
> BL <ga:@BZ2_bzWriteClose64>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %W2<imp-use>, %X3<imp-use>, %X4<imp-use>, %X5<imp-use>, %X6<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X8<def> = ADRP <ga:@BZ2_bzWriteClose>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@BZ2_bzWriteClose>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19<kill>
> BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 2, 0, %LR<earlyclobber,imp-def,dead>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> RET_ReallyLR
Computing live-in reg-units in ABI blocks.
0B	BB#0 W0#0 W1#0 W2#0 W3#0 W4#0 W5#0 W6#0 W30#0
Created 8 new intervals.
********** INTERVALS **********
W30 [0B,16r:0)[368r,368d:22)[416e,416d:9)[1312r,1312d:21)[1376e,1376d:8)[2448r,2448d:20)[2512e,2512d:7)[3296r,3296d:19)[3360e,3360d:6)[3568r,3568d:18)[3632e,3632d:5)[4256r,4256d:17)[4320e,4320d:4)[4448r,4448d:15)[4512e,4512d:3)[4608r,4608d:16)[4672e,4672d:2)[5808r,5808d:12)[5872e,5872d:1)[5968r,5968d:13)[6016e,6016d:14)[6176r,6176d:10)[6224e,6224d:11)  0@0B-phi 1@5872e 2@4672e 3@4512e 4@4320e 5@3632e 6@3360e 7@2512e 8@1376e 9@416e 10@6176r 11@6224e 12@5808r 13@5968r 14@6016e 15@4448r 16@4608r 17@4256r 18@3568r 19@3296r 20@2448r 21@1312r 22@368r
W0 [0B,128r:0)[336r,368r:19)[1296r,1312r:18)[1312r,1344r:7)[2416r,2448r:17)[2448r,2480r:6)[3232r,3296r:16)[3296r,3328r:15)[3552r,3568r:14)[3568r,3600r:5)[4240r,4256r:13)[4256r,4288r:4)[4432r,4448r:11)[4448r,4480r:2)[4592r,4608r:12)[4608r,4640r:3)[5792r,5808r:9)[5808r,5840r:1)[5952r,5968r:10)[6144r,6176r:8)  0@0B-phi 1@5808r 2@4448r 3@4608r 4@4256r 5@3568r 6@2448r 7@1312r 8@6144r 9@5792r 10@5952r 11@4432r 12@4592r 13@4240r 14@3552r 15@3296r 16@3232r 17@2416r 18@1296r 19@336r
W1 [0B,112r:0)[352r,368r:4)[2432r,2448r:1)[3248r,3296r:3)[6160r,6176r:2)  0@0B-phi 1@2432r 2@6160r 3@3248r 4@352r
W2 [0B,96r:0)[3264r,3296r:1)  0@0B-phi 1@3264r
W3 [0B,80r:0)[3280r,3296r:1)  0@0B-phi 1@3280r
W4 [0B,64r:0)  0@0B-phi
W5 [0B,48r:0)  0@0B-phi
W6 [0B,32r:0)  0@0B-phi
%vreg0 [128r,144r:0)  0@128r
%vreg1 [144r,448r:0)  0@144r
%vreg2 [112r,160r:0)  0@112r
%vreg3 [160r,464r:0)  0@160r
%vreg4 [96r,176r:0)  0@96r
%vreg5 [176r,480r:0)  0@176r
%vreg6 [80r,192r:0)  0@80r
%vreg7 [192r,496r:0)  0@192r
%vreg8 [64r,208r:0)  0@64r
%vreg9 [208r,512r:0)  0@208r
%vreg10 [48r,224r:0)  0@48r
%vreg11 [224r,528r:0)  0@224r
%vreg12 [32r,240r:0)  0@32r
%vreg13 [240r,544r:0)  0@240r
%vreg15 [608r,624r:0)  0@608r
%vreg18 [576r,592r:0)  0@576r
%vreg19 [560r,576r:0)  0@560r
%vreg20 [256r,272r:0)  0@256r
%vreg21 [272r,288r:0)  0@272r
%vreg22 [288r,336r:0)  0@288r
%vreg23 [304r,352r:0)  0@304r
%vreg24 [16r,6112r:0)  0@16r
%vreg26 [944r,960r:0)  0@944r
%vreg28 [896r,912r:0)  0@896r
%vreg29 [912r,928r:0)  0@912r
%vreg30 [928r,944r:0)  0@928r
%vreg31 [880r,912r:0)  0@880r
%vreg33 [992r,1008r:0)  0@992r
%vreg34 [1040r,1072r:0)  0@1040r
%vreg36 [1056r,1072r:0)  0@1056r
%vreg38 [1104r,1120r:0)  0@1104r
%vreg39 [1152r,1184r:0)  0@1152r
%vreg41 [1168r,1184r:0)  0@1168r
%vreg44 [1344r,1408r:0)  0@1344r
%vreg46 [1264r,1296r:0)  0@1264r
%vreg47 [1248r,1264r:0)  0@1248r
%vreg49 [1696r,1712r:0)  0@1696r
%vreg51 [1744r,1760r:0)  0@1744r
%vreg53 [1792r,1808r:0)  0@1792r
%vreg55 [1840r,1856r:0)  0@1840r
%vreg57 [1888r,1904r:0)  0@1888r
%vreg59 [1936r,1952r:0)  0@1936r
%vreg61 [1984r,2000r:0)  0@1984r
%vreg63 [2032r,2048r:0)  0@2032r
%vreg65 [2080r,2096r:0)  0@2080r
%vreg68 [2144r,2160r:0)  0@2144r
%vreg69 [2128r,2144r:0)  0@2128r
%vreg71 [2560r,2576r:0)  0@2560r
%vreg74 [2224r,2432r:0)  0@2224r
%vreg75 [2480r,2544r:0)  0@2480r
%vreg77 [2368r,2384r:0)  0@2368r
%vreg78 [2384r,2416r:0)  0@2384r
%vreg79 [2352r,2384r:0)  0@2352r
%vreg82 [2320r,2336r:0)  0@2320r
%vreg85 [2304r,2336r:0)  0@2304r
%vreg86 [2288r,2304r:0)  0@2288r
%vreg87 [2240r,2272r:0)  0@2240r
%vreg89 [2256r,2272r:0)  0@2256r
%vreg91 [2624r,2640r:0)  0@2624r
%vreg93 [2944r,2992r:0)  0@2944r
%vreg95 [2976r,2992r:0)  0@2976r
%vreg96 [2960r,2976r:0)  0@2960r
%vreg99 [3440r,3456r:0)  0@3440r
%vreg100 [3424r,3456r:0)  0@3424r
%vreg103 [3392r,3408r:0)  0@3392r
%vreg105 [3040r,3248r:0)  0@3040r
%vreg108 [3328r,3392r:0)  0@3328r
%vreg110 [3200r,3280r:0)  0@3200r
%vreg111 [3184r,3200r:0)  0@3184r
%vreg115 [3168r,3264r:0)  0@3168r
%vreg118 [3152r,3232r:0)  0@3152r
%vreg119 [3136r,3152r:0)  0@3136r
%vreg121 [3056r,3104r:0)  0@3056r
%vreg123 [3104r,3120r:0)  0@3104r
%vreg125 [3088r,3104r:0)  0@3088r
%vreg126 [3072r,3088r:0)  0@3072r
%vreg129 [3600r,3664r:0)  0@3600r
%vreg131 [3520r,3552r:0)  0@3520r
%vreg132 [3504r,3520r:0)  0@3504r
%vreg134 [3984r,4000r:0)  0@3984r
%vreg136 [3696r,3712r:0)  0@3696r
%vreg137 [3744r,3776r:0)  0@3744r
%vreg139 [3760r,3776r:0)  0@3760r
%vreg141 [3808r,3824r:0)  0@3808r
%vreg142 [3856r,3888r:0)  0@3856r
%vreg144 [3872r,3888r:0)  0@3872r
%vreg146 [2688r,2704r:0)  0@2688r
%vreg149 [2752r,2768r:0)  0@2752r
%vreg150 [2736r,2768r:0)  0@2736r
%vreg152 [2800r,2816r:0)  0@2800r
%vreg155 [2864r,2880r:0)  0@2864r
%vreg156 [2848r,2880r:0)  0@2848r
%vreg158 [4144r,4160r:0)  0@4144r
%vreg161 [4288r,4352r:0)  0@4288r
%vreg163 [4208r,4240r:0)  0@4208r
%vreg164 [4192r,4208r:0)  0@4192r
%vreg167 [4640r,4704r:0)  0@4640r
%vreg169 [4560r,4592r:0)  0@4560r
%vreg170 [4544r,4560r:0)  0@4544r
%vreg172 [4480r,4480d:0)  0@4480r
%vreg174 [4400r,4432r:0)  0@4400r
%vreg175 [4384r,4400r:0)  0@4384r
%vreg177 [4736r,4752r:0)  0@4736r
%vreg178 [4784r,4816r:0)  0@4784r
%vreg180 [4800r,4816r:0)  0@4800r
%vreg182 [4848r,4864r:0)  0@4848r
%vreg183 [4896r,4928r:0)  0@4896r
%vreg185 [4912r,4928r:0)  0@4912r
%vreg187 [5024r,5040r:0)  0@5024r
%vreg190 [5104r,5120r:0)  0@5104r
%vreg192 [5088r,5120r:0)  0@5088r
%vreg193 [5072r,5088r:0)  0@5072r
%vreg195 [5152r,5168r:0)  0@5152r
%vreg198 [5232r,5248r:0)  0@5232r
%vreg200 [5216r,5248r:0)  0@5216r
%vreg201 [5200r,5216r:0)  0@5200r
%vreg203 [5280r,5296r:0)  0@5280r
%vreg206 [5360r,5376r:0)  0@5360r
%vreg208 [5344r,5376r:0)  0@5344r
%vreg209 [5328r,5344r:0)  0@5328r
%vreg211 [5408r,5424r:0)  0@5408r
%vreg214 [5488r,5504r:0)  0@5488r
%vreg216 [5472r,5504r:0)  0@5472r
%vreg217 [5456r,5472r:0)  0@5456r
%vreg219 [5536r,5552r:0)  0@5536r
%vreg221 [5584r,5600r:0)  0@5584r
%vreg223 [5632r,5648r:0)  0@5632r
%vreg225 [5680r,5696r:0)  0@5680r
%vreg228 [5920r,5952r:0)  0@5920r
%vreg229 [5904r,5920r:0)  0@5904r
%vreg231 [5840r,5840d:0)  0@5840r
%vreg233 [5744r,5760r:0)  0@5744r
%vreg234 [5760r,5792r:0)  0@5760r
%vreg235 [5728r,5760r:0)  0@5728r
%vreg237 [1440r,1456r:0)  0@1440r
%vreg238 [1488r,1520r:0)  0@1488r
%vreg240 [1504r,1520r:0)  0@1504r
%vreg242 [1552r,1568r:0)  0@1552r
%vreg243 [1600r,1632r:0)  0@1600r
%vreg245 [1616r,1632r:0)  0@1616r
%vreg247 [656r,672r:0)  0@656r
%vreg249 [704r,720r:0)  0@704r
%vreg251 [752r,768r:0)  0@752r
%vreg253 [800r,816r:0)  0@800r
%vreg254 [6064r,6080r:0)  0@6064r
%vreg255 [6080r,6096r:0)  0@6080r
%vreg256 [6096r,6144r:0)  0@6096r
%vreg257 [6112r,6160r:0)  0@6112r
RegMasks: 368r 1312r 2448r 3296r 3568r 4256r 4448r 4608r 5808r 5968r 6176r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzWriteClose64: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=4, align=4, at location [SP]
  fi#3: size=8, align=8, at location [SP]
  fi#4: size=8, align=8, at location [SP]
  fi#5: size=8, align=8, at location [SP]
  fi#6: size=8, align=8, at location [SP]
  fi#7: size=4, align=4, at location [SP]
  fi#8: size=4, align=4, at location [SP]
  fi#9: size=4, align=4, at location [SP]
  fi#10: size=8, align=8, at location [SP]
Function Live Ins: %X0 in %vreg0, %X1 in %vreg2, %W2 in %vreg4, %X3 in %vreg6, %X4 in %vreg8, %X5 in %vreg10, %X6 in %vreg12, %LR in %vreg24

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %X1 %W2 %X3 %X4 %X5 %X6 %LR
16B		%vreg24<def> = COPY %LR; GPR64:%vreg24
32B		%vreg12<def> = COPY %X6; GPR64:%vreg12
48B		%vreg10<def> = COPY %X5; GPR64:%vreg10
64B		%vreg8<def> = COPY %X4; GPR64:%vreg8
80B		%vreg6<def> = COPY %X3; GPR64:%vreg6
96B		%vreg4<def> = COPY %W2; GPR32:%vreg4
112B		%vreg2<def> = COPY %X1; GPR64:%vreg2
128B		%vreg0<def> = COPY %X0; GPR64:%vreg0
144B		%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
160B		%vreg3<def> = COPY %vreg2; GPR64:%vreg3,%vreg2
176B		%vreg5<def> = COPY %vreg4; GPR32:%vreg5,%vreg4
192B		%vreg7<def> = COPY %vreg6; GPR64:%vreg7,%vreg6
208B		%vreg9<def> = COPY %vreg8; GPR64:%vreg9,%vreg8
224B		%vreg11<def> = COPY %vreg10; GPR64:%vreg11,%vreg10
240B		%vreg13<def> = COPY %vreg12; GPR64:%vreg13,%vreg12
256B		%vreg20<def> = ADRP <ga:@BZ2_bzWriteClose64>[TF=1]; GPR64common:%vreg20
272B		%vreg21<def> = ADDXri %vreg20, <ga:@BZ2_bzWriteClose64>[TF=34], 0; GPR64sp:%vreg21 GPR64common:%vreg20
288B		%vreg22<def> = COPY %vreg21; GPR64all:%vreg22 GPR64sp:%vreg21
304B		%vreg23<def> = COPY %vreg24; GPR64all:%vreg23 GPR64:%vreg24
320B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
336B		%X0<def> = COPY %vreg22; GPR64all:%vreg22
352B		%X1<def> = COPY %vreg23; GPR64all:%vreg23
368B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
384B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
400B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
416B		STACKMAP 0, 0, %vreg5, 0, <fi#2>, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, %vreg9, 0, <fi#4>, 0, %vreg7, 0, <fi#3>, 0, %vreg13, 0, <fi#6>, 0, %vreg11, 0, <fi#5>, 0, 0, <fi#9>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4) GPR32:%vreg5 GPR64:%vreg3,%vreg1,%vreg9,%vreg7,%vreg13,%vreg11
432B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
448B		STRXui %vreg1, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg1
464B		STRXui %vreg3, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg3
480B		STRWui %vreg5, <fi#2>, 0; mem:ST4[FixedStack2] GPR32:%vreg5
496B		STRXui %vreg7, <fi#3>, 0; mem:ST8[FixedStack3] GPR64:%vreg7
512B		STRXui %vreg9, <fi#4>, 0; mem:ST8[FixedStack4] GPR64:%vreg9
528B		STRXui %vreg11, <fi#5>, 0; mem:ST8[FixedStack5] GPR64:%vreg11
544B		STRXui %vreg13, <fi#6>, 0; mem:ST8[FixedStack6] GPR64:%vreg13
560B		%vreg19<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg19
576B		%vreg18<def> = COPY %vreg19; GPR64:%vreg18,%vreg19
592B		STRXui %vreg18, <fi#10>, 0; mem:ST8[FixedStack10] GPR64:%vreg18
608B		%vreg15<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg15
624B		CBNZX %vreg15, <BB#6>; GPR64:%vreg15
	    Successors according to CFG: BB#6 BB#1

640B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
656B		%vreg247<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg247
672B		CBZX %vreg247, <BB#3>; GPR64:%vreg247
	    Successors according to CFG: BB#3 BB#2

688B	BB#2: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#1
704B		%vreg249<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg249
720B		STRWui %WZR, %vreg249, 0; mem:ST4[%4] GPR64common:%vreg249
	    Successors according to CFG: BB#3

736B	BB#3: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#1 BB#2
752B		%vreg251<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg251
768B		CBZX %vreg251, <BB#5>; GPR64:%vreg251
	    Successors according to CFG: BB#5 BB#4

784B	BB#4: derived from LLVM BB %if.then.4
	    Predecessors according to CFG: BB#3
800B		%vreg253<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg253
816B		STRWui %WZR, %vreg253, 1274; mem:ST4[%lastErr] GPR64common:%vreg253
	    Successors according to CFG: BB#5

832B	BB#5: derived from LLVM BB %if.end.5
	    Predecessors according to CFG: BB#3 BB#4
848B		B <BB#71>
	    Successors according to CFG: BB#71

864B	BB#6: derived from LLVM BB %if.end.6
	    Predecessors according to CFG: BB#0
880B		%vreg31<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg31
896B		%vreg28<def> = MOVi64imm 5012; GPR64:%vreg28
912B		%vreg29<def> = ADDXrr %vreg31, %vreg28; GPR64common:%vreg29 GPR64:%vreg31,%vreg28
928B		%vreg30<def> = LDRBBui %vreg29, 0; mem:LD1[%writing] GPR32:%vreg30 GPR64common:%vreg29
944B		%vreg26<def> = UBFMWri %vreg30, 0, 7; GPR32:%vreg26,%vreg30
960B		CBNZW %vreg26, <BB#12>; GPR32:%vreg26
	    Successors according to CFG: BB#12 BB#7

976B	BB#7: derived from LLVM BB %if.then.7
	    Predecessors according to CFG: BB#6
992B		%vreg33<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg33
1008B		CBZX %vreg33, <BB#9>; GPR64:%vreg33
	    Successors according to CFG: BB#9 BB#8

1024B	BB#8: derived from LLVM BB %if.then.9
	    Predecessors according to CFG: BB#7
1040B		%vreg34<def> = MOVi32imm 4294967295; GPR32:%vreg34
1056B		%vreg36<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg36
1072B		STRWui %vreg34, %vreg36, 0; mem:ST4[%10] GPR32:%vreg34 GPR64common:%vreg36
	    Successors according to CFG: BB#9

1088B	BB#9: derived from LLVM BB %if.end.10
	    Predecessors according to CFG: BB#7 BB#8
1104B		%vreg38<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg38
1120B		CBZX %vreg38, <BB#11>; GPR64:%vreg38
	    Successors according to CFG: BB#11 BB#10

1136B	BB#10: derived from LLVM BB %if.then.12
	    Predecessors according to CFG: BB#9
1152B		%vreg39<def> = MOVi32imm 4294967295; GPR32:%vreg39
1168B		%vreg41<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg41
1184B		STRWui %vreg39, %vreg41, 1274; mem:ST4[%lastErr13] GPR32:%vreg39 GPR64common:%vreg41
	    Successors according to CFG: BB#11

1200B	BB#11: derived from LLVM BB %if.end.14
	    Predecessors according to CFG: BB#9 BB#10
1216B		B <BB#71>
	    Successors according to CFG: BB#71

1232B	BB#12: derived from LLVM BB %if.end.15
	    Predecessors according to CFG: BB#6
1248B		%vreg47<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg47
1264B		%vreg46<def> = LDRXui %vreg47, 0; mem:LD8[%handle] GPR64:%vreg46 GPR64common:%vreg47
1280B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1296B		%X0<def> = COPY %vreg46; GPR64:%vreg46
1312B		BL <ga:@ferror>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
1328B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1344B		%vreg44<def> = COPY %W0; GPR32:%vreg44
1360B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1376B		STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, 0, <fi#9>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4)
1392B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1408B		CBZW %vreg44, <BB#18>; GPR32:%vreg44
	    Successors according to CFG: BB#18 BB#13

1424B	BB#13: derived from LLVM BB %if.then.17
	    Predecessors according to CFG: BB#12
1440B		%vreg237<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg237
1456B		CBZX %vreg237, <BB#15>; GPR64:%vreg237
	    Successors according to CFG: BB#15 BB#14

1472B	BB#14: derived from LLVM BB %if.then.19
	    Predecessors according to CFG: BB#13
1488B		%vreg238<def> = MOVi32imm 4294967290; GPR32:%vreg238
1504B		%vreg240<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg240
1520B		STRWui %vreg238, %vreg240, 0; mem:ST4[%16] GPR32:%vreg238 GPR64common:%vreg240
	    Successors according to CFG: BB#15

1536B	BB#15: derived from LLVM BB %if.end.20
	    Predecessors according to CFG: BB#13 BB#14
1552B		%vreg242<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg242
1568B		CBZX %vreg242, <BB#17>; GPR64:%vreg242
	    Successors according to CFG: BB#17 BB#16

1584B	BB#16: derived from LLVM BB %if.then.22
	    Predecessors according to CFG: BB#15
1600B		%vreg243<def> = MOVi32imm 4294967290; GPR32:%vreg243
1616B		%vreg245<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg245
1632B		STRWui %vreg243, %vreg245, 1274; mem:ST4[%lastErr23] GPR32:%vreg243 GPR64common:%vreg245
	    Successors according to CFG: BB#17

1648B	BB#17: derived from LLVM BB %if.end.24
	    Predecessors according to CFG: BB#15 BB#16
1664B		B <BB#71>
	    Successors according to CFG: BB#71

1680B	BB#18: derived from LLVM BB %if.end.25
	    Predecessors according to CFG: BB#12
1696B		%vreg49<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg49
1712B		CBZX %vreg49, <BB#20>; GPR64:%vreg49
	    Successors according to CFG: BB#20 BB#19

1728B	BB#19: derived from LLVM BB %if.then.27
	    Predecessors according to CFG: BB#18
1744B		%vreg51<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg51
1760B		STRWui %WZR, %vreg51, 0; mem:ST4[%20] GPR64common:%vreg51
	    Successors according to CFG: BB#20

1776B	BB#20: derived from LLVM BB %if.end.28
	    Predecessors according to CFG: BB#18 BB#19
1792B		%vreg53<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64:%vreg53
1808B		CBZX %vreg53, <BB#22>; GPR64:%vreg53
	    Successors according to CFG: BB#22 BB#21

1824B	BB#21: derived from LLVM BB %if.then.30
	    Predecessors according to CFG: BB#20
1840B		%vreg55<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg55
1856B		STRWui %WZR, %vreg55, 0; mem:ST4[%22] GPR64common:%vreg55
	    Successors according to CFG: BB#22

1872B	BB#22: derived from LLVM BB %if.end.31
	    Predecessors according to CFG: BB#20 BB#21
1888B		%vreg57<def> = LDRXui <fi#5>, 0; mem:LD8[FixedStack5] GPR64:%vreg57
1904B		CBZX %vreg57, <BB#24>; GPR64:%vreg57
	    Successors according to CFG: BB#24 BB#23

1920B	BB#23: derived from LLVM BB %if.then.33
	    Predecessors according to CFG: BB#22
1936B		%vreg59<def> = LDRXui <fi#5>, 0; mem:LD8[FixedStack5] GPR64common:%vreg59
1952B		STRWui %WZR, %vreg59, 0; mem:ST4[%24] GPR64common:%vreg59
	    Successors according to CFG: BB#24

1968B	BB#24: derived from LLVM BB %if.end.34
	    Predecessors according to CFG: BB#22 BB#23
1984B		%vreg61<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64:%vreg61
2000B		CBZX %vreg61, <BB#26>; GPR64:%vreg61
	    Successors according to CFG: BB#26 BB#25

2016B	BB#25: derived from LLVM BB %if.then.36
	    Predecessors according to CFG: BB#24
2032B		%vreg63<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg63
2048B		STRWui %WZR, %vreg63, 0; mem:ST4[%26] GPR64common:%vreg63
	    Successors according to CFG: BB#26

2064B	BB#26: derived from LLVM BB %if.end.37
	    Predecessors according to CFG: BB#24 BB#25
2080B		%vreg65<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg65
2096B		CBNZW %vreg65, <BB#49>; GPR32:%vreg65
	    Successors according to CFG: BB#49 BB#27

2112B	BB#27: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#26
2128B		%vreg69<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg69
2144B		%vreg68<def> = LDRWui %vreg69, 1274; mem:LD4[%lastErr39] GPR32:%vreg68 GPR64common:%vreg69
2160B		CBNZW %vreg68, <BB#49>; GPR32:%vreg68
	    Successors according to CFG: BB#49 BB#28

2176B	BB#28: derived from LLVM BB %if.then.41
	    Predecessors according to CFG: BB#27
2192B		B <BB#29>
	    Successors according to CFG: BB#29

2208B	BB#29: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#28 BB#47
2224B		%vreg74<def> = MOVi32imm 2; GPR32:%vreg74
2240B		%vreg87<def> = MOVi32imm 5000; GPR32:%vreg87
2256B		%vreg89<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg89
2272B		STRWui %vreg87, %vreg89, 1262; mem:ST4[%avail_out] GPR32:%vreg87 GPR64common:%vreg89
2288B		%vreg86<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg86
2304B		%vreg85<def> = ADDXri %vreg86, 8, 0; GPR64common:%vreg85,%vreg86
2320B		%vreg82<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg82
2336B		STRXui %vreg85, %vreg82, 630; mem:ST8[%next_out] GPR64common:%vreg85,%vreg82
2352B		%vreg79<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg79
2368B		%vreg77<def> = MOVi64imm 5016; GPR64:%vreg77
2384B		%vreg78<def> = ADDXrr %vreg79, %vreg77; GPR64:%vreg78,%vreg79,%vreg77
2400B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2416B		%X0<def> = COPY %vreg78; GPR64:%vreg78
2432B		%W1<def> = COPY %vreg74; GPR32:%vreg74
2448B		BL <ga:@BZ2_bzCompress>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %W0<imp-def>
2464B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2480B		%vreg75<def> = COPY %W0; GPR32:%vreg75
2496B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2512B		STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, 0, <fi#9>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4)
2528B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2544B		STRWui %vreg75, <fi#9>, 0; mem:ST4[FixedStack9] GPR32:%vreg75
2560B		%vreg71<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32common:%vreg71
2576B		%WZR<def> = SUBSWri %vreg71, 3, 0, %NZCV<imp-def>; GPR32common:%vreg71
2592B		Bcc 0, <BB#36>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#36 BB#30

2608B	BB#30: derived from LLVM BB %land.lhs.true.46
	    Predecessors according to CFG: BB#29
2624B		%vreg91<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32common:%vreg91
2640B		%WZR<def> = SUBSWri %vreg91, 4, 0, %NZCV<imp-def>; GPR32common:%vreg91
2656B		Bcc 0, <BB#36>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#36 BB#31

2672B	BB#31: derived from LLVM BB %if.then.48
	    Predecessors according to CFG: BB#30
2688B		%vreg146<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg146
2704B		CBZX %vreg146, <BB#33>; GPR64:%vreg146
	    Successors according to CFG: BB#33 BB#32

2720B	BB#32: derived from LLVM BB %if.then.50
	    Predecessors according to CFG: BB#31
2736B		%vreg150<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32:%vreg150
2752B		%vreg149<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg149
2768B		STRWui %vreg150, %vreg149, 0; mem:ST4[%38] GPR32:%vreg150 GPR64common:%vreg149
	    Successors according to CFG: BB#33

2784B	BB#33: derived from LLVM BB %if.end.51
	    Predecessors according to CFG: BB#31 BB#32
2800B		%vreg152<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg152
2816B		CBZX %vreg152, <BB#35>; GPR64:%vreg152
	    Successors according to CFG: BB#35 BB#34

2832B	BB#34: derived from LLVM BB %if.then.53
	    Predecessors according to CFG: BB#33
2848B		%vreg156<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32:%vreg156
2864B		%vreg155<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg155
2880B		STRWui %vreg156, %vreg155, 1274; mem:ST4[%lastErr54] GPR32:%vreg156 GPR64common:%vreg155
	    Successors according to CFG: BB#35

2896B	BB#35: derived from LLVM BB %if.end.55
	    Predecessors according to CFG: BB#33 BB#34
2912B		B <BB#71>
	    Successors according to CFG: BB#71

2928B	BB#36: derived from LLVM BB %if.end.56
	    Predecessors according to CFG: BB#29 BB#30
2944B		%vreg93<def> = MOVi32imm 5000; GPR32:%vreg93
2960B		%vreg96<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg96
2976B		%vreg95<def> = LDRWui %vreg96, 1262; mem:LD4[%avail_out58] GPR32:%vreg95 GPR64common:%vreg96
2992B		%WZR<def> = SUBSWrr %vreg95, %vreg93, %NZCV<imp-def>; GPR32:%vreg95,%vreg93
3008B		Bcc 2, <BB#45>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#45 BB#37

3024B	BB#37: derived from LLVM BB %if.then.60
	    Predecessors according to CFG: BB#36
3040B		%vreg105<def> = MOVi64imm 1; GPR64:%vreg105
3056B		%vreg121<def> = MOVi32imm 5000; GPR32:%vreg121
3072B		%vreg126<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg126
3088B		%vreg125<def> = LDRWui %vreg126, 1262; mem:LD4[%avail_out62] GPR32:%vreg125 GPR64common:%vreg126
3104B		%vreg123<def> = SUBWrr %vreg121, %vreg125; GPR32:%vreg123,%vreg121,%vreg125
3120B		STRWui %vreg123, <fi#7>, 0; mem:ST4[FixedStack7] GPR32:%vreg123
3136B		%vreg119<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg119
3152B		%vreg118<def> = ADDXri %vreg119, 8, 0; GPR64sp:%vreg118 GPR64common:%vreg119
3168B		%vreg115<def> = LDRSWui <fi#7>, 0; mem:LD4[FixedStack7] GPR64:%vreg115
3184B		%vreg111<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg111
3200B		%vreg110<def> = LDRXui %vreg111, 0; mem:LD8[%handle65] GPR64:%vreg110 GPR64common:%vreg111
3216B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3232B		%X0<def> = COPY %vreg118; GPR64sp:%vreg118
3248B		%X1<def> = COPY %vreg105; GPR64:%vreg105
3264B		%X2<def> = COPY %vreg115; GPR64:%vreg115
3280B		%X3<def> = COPY %vreg110; GPR64:%vreg110
3296B		BL <ga:@fwrite>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %X2<imp-use>, %X3<imp-use>, %X0<imp-def>
3312B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3328B		%vreg108<def> = COPY %X0; GPR64all:%vreg108
3344B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3360B		STACKMAP 3, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, 0, <fi#9>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4)
3376B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3392B		%vreg103<def> = COPY %vreg108:sub_32; GPR32:%vreg103 GPR64all:%vreg108
3408B		STRWui %vreg103, <fi#8>, 0; mem:ST4[FixedStack8] GPR32:%vreg103
3424B		%vreg100<def> = LDRWui <fi#7>, 0; mem:LD4[FixedStack7] GPR32:%vreg100
3440B		%vreg99<def> = LDRWui <fi#8>, 0; mem:LD4[FixedStack8] GPR32:%vreg99
3456B		%WZR<def> = SUBSWrr %vreg100, %vreg99, %NZCV<imp-def>; GPR32:%vreg100,%vreg99
3472B		Bcc 1, <BB#39>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#39 BB#38

3488B	BB#38: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#37
3504B		%vreg132<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg132
3520B		%vreg131<def> = LDRXui %vreg132, 0; mem:LD8[%handle70] GPR64:%vreg131 GPR64common:%vreg132
3536B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3552B		%X0<def> = COPY %vreg131; GPR64:%vreg131
3568B		BL <ga:@ferror>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
3584B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3600B		%vreg129<def> = COPY %W0; GPR32:%vreg129
3616B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3632B		STACKMAP 4, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, 0, <fi#9>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4)
3648B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3664B		CBZW %vreg129, <BB#44>; GPR32:%vreg129
	    Successors according to CFG: BB#44 BB#39

3680B	BB#39: derived from LLVM BB %if.then.73
	    Predecessors according to CFG: BB#37 BB#38
3696B		%vreg136<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg136
3712B		CBZX %vreg136, <BB#41>; GPR64:%vreg136
	    Successors according to CFG: BB#41 BB#40

3728B	BB#40: derived from LLVM BB %if.then.76
	    Predecessors according to CFG: BB#39
3744B		%vreg137<def> = MOVi32imm 4294967290; GPR32:%vreg137
3760B		%vreg139<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg139
3776B		STRWui %vreg137, %vreg139, 0; mem:ST4[%55] GPR32:%vreg137 GPR64common:%vreg139
	    Successors according to CFG: BB#41

3792B	BB#41: derived from LLVM BB %if.end.77
	    Predecessors according to CFG: BB#39 BB#40
3808B		%vreg141<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg141
3824B		CBZX %vreg141, <BB#43>; GPR64:%vreg141
	    Successors according to CFG: BB#43 BB#42

3840B	BB#42: derived from LLVM BB %if.then.80
	    Predecessors according to CFG: BB#41
3856B		%vreg142<def> = MOVi32imm 4294967290; GPR32:%vreg142
3872B		%vreg144<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg144
3888B		STRWui %vreg142, %vreg144, 1274; mem:ST4[%lastErr81] GPR32:%vreg142 GPR64common:%vreg144
	    Successors according to CFG: BB#43

3904B	BB#43: derived from LLVM BB %if.end.82
	    Predecessors according to CFG: BB#41 BB#42
3920B		B <BB#71>
	    Successors according to CFG: BB#71

3936B	BB#44: derived from LLVM BB %if.end.83
	    Predecessors according to CFG: BB#38
3952B		B <BB#45>
	    Successors according to CFG: BB#45

3968B	BB#45: derived from LLVM BB %if.end.84
	    Predecessors according to CFG: BB#36 BB#44
3984B		%vreg134<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32common:%vreg134
4000B		%WZR<def> = SUBSWri %vreg134, 4, 0, %NZCV<imp-def>; GPR32common:%vreg134
4016B		Bcc 1, <BB#47>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#47 BB#46

4032B	BB#46: derived from LLVM BB %if.then.87
	    Predecessors according to CFG: BB#45
4048B		B <BB#48>
	    Successors according to CFG: BB#48

4064B	BB#47: derived from LLVM BB %if.end.88
	    Predecessors according to CFG: BB#45
4080B		B <BB#29>
	    Successors according to CFG: BB#29

4096B	BB#48: derived from LLVM BB %while.end
	    Predecessors according to CFG: BB#46
4112B		B <BB#49>
	    Successors according to CFG: BB#49

4128B	BB#49: derived from LLVM BB %if.end.89
	    Predecessors according to CFG: BB#26 BB#27 BB#48
4144B		%vreg158<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg158
4160B		CBNZW %vreg158, <BB#58>; GPR32:%vreg158
	    Successors according to CFG: BB#58 BB#50

4176B	BB#50: derived from LLVM BB %land.lhs.true.91
	    Predecessors according to CFG: BB#49
4192B		%vreg164<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg164
4208B		%vreg163<def> = LDRXui %vreg164, 0; mem:LD8[%handle92] GPR64:%vreg163 GPR64common:%vreg164
4224B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4240B		%X0<def> = COPY %vreg163; GPR64:%vreg163
4256B		BL <ga:@ferror>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
4272B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4288B		%vreg161<def> = COPY %W0; GPR32:%vreg161
4304B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4320B		STACKMAP 5, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5]
4336B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4352B		CBNZW %vreg161, <BB#58>; GPR32:%vreg161
	    Successors according to CFG: BB#58 BB#51

4368B	BB#51: derived from LLVM BB %if.then.95
	    Predecessors according to CFG: BB#50
4384B		%vreg175<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg175
4400B		%vreg174<def> = LDRXui %vreg175, 0; mem:LD8[%handle96] GPR64:%vreg174 GPR64common:%vreg175
4416B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4432B		%X0<def> = COPY %vreg174; GPR64:%vreg174
4448B		BL <ga:@fflush>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
4464B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4480B		%vreg172<def,dead> = COPY %W0; GPR32all:%vreg172
4496B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4512B		STACKMAP 6, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5]
4528B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4544B		%vreg170<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg170
4560B		%vreg169<def> = LDRXui %vreg170, 0; mem:LD8[%handle98] GPR64:%vreg169 GPR64common:%vreg170
4576B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4592B		%X0<def> = COPY %vreg169; GPR64:%vreg169
4608B		BL <ga:@ferror>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
4624B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4640B		%vreg167<def> = COPY %W0; GPR32:%vreg167
4656B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4672B		STACKMAP 7, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5]
4688B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4704B		CBZW %vreg167, <BB#57>; GPR32:%vreg167
	    Successors according to CFG: BB#57 BB#52

4720B	BB#52: derived from LLVM BB %if.then.101
	    Predecessors according to CFG: BB#51
4736B		%vreg177<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg177
4752B		CBZX %vreg177, <BB#54>; GPR64:%vreg177
	    Successors according to CFG: BB#54 BB#53

4768B	BB#53: derived from LLVM BB %if.then.104
	    Predecessors according to CFG: BB#52
4784B		%vreg178<def> = MOVi32imm 4294967290; GPR32:%vreg178
4800B		%vreg180<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg180
4816B		STRWui %vreg178, %vreg180, 0; mem:ST4[%67] GPR32:%vreg178 GPR64common:%vreg180
	    Successors according to CFG: BB#54

4832B	BB#54: derived from LLVM BB %if.end.105
	    Predecessors according to CFG: BB#52 BB#53
4848B		%vreg182<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg182
4864B		CBZX %vreg182, <BB#56>; GPR64:%vreg182
	    Successors according to CFG: BB#56 BB#55

4880B	BB#55: derived from LLVM BB %if.then.108
	    Predecessors according to CFG: BB#54
4896B		%vreg183<def> = MOVi32imm 4294967290; GPR32:%vreg183
4912B		%vreg185<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg185
4928B		STRWui %vreg183, %vreg185, 1274; mem:ST4[%lastErr109] GPR32:%vreg183 GPR64common:%vreg185
	    Successors according to CFG: BB#56

4944B	BB#56: derived from LLVM BB %if.end.110
	    Predecessors according to CFG: BB#54 BB#55
4960B		B <BB#71>
	    Successors according to CFG: BB#71

4976B	BB#57: derived from LLVM BB %if.end.111
	    Predecessors according to CFG: BB#51
4992B		B <BB#58>
	    Successors according to CFG: BB#58

5008B	BB#58: derived from LLVM BB %if.end.112
	    Predecessors according to CFG: BB#49 BB#50 BB#57
5024B		%vreg187<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg187
5040B		CBZX %vreg187, <BB#60>; GPR64:%vreg187
	    Successors according to CFG: BB#60 BB#59

5056B	BB#59: derived from LLVM BB %if.then.115
	    Predecessors according to CFG: BB#58
5072B		%vreg193<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg193
5088B		%vreg192<def> = LDRWui %vreg193, 1257; mem:LD4[%total_in_lo32] GPR32:%vreg192 GPR64common:%vreg193
5104B		%vreg190<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg190
5120B		STRWui %vreg192, %vreg190, 0; mem:ST4[%73] GPR32:%vreg192 GPR64common:%vreg190
	    Successors according to CFG: BB#60

5136B	BB#60: derived from LLVM BB %if.end.117
	    Predecessors according to CFG: BB#58 BB#59
5152B		%vreg195<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64:%vreg195
5168B		CBZX %vreg195, <BB#62>; GPR64:%vreg195
	    Successors according to CFG: BB#62 BB#61

5184B	BB#61: derived from LLVM BB %if.then.120
	    Predecessors according to CFG: BB#60
5200B		%vreg201<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg201
5216B		%vreg200<def> = LDRWui %vreg201, 1258; mem:LD4[%total_in_hi32] GPR32:%vreg200 GPR64common:%vreg201
5232B		%vreg198<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg198
5248B		STRWui %vreg200, %vreg198, 0; mem:ST4[%77] GPR32:%vreg200 GPR64common:%vreg198
	    Successors according to CFG: BB#62

5264B	BB#62: derived from LLVM BB %if.end.122
	    Predecessors according to CFG: BB#60 BB#61
5280B		%vreg203<def> = LDRXui <fi#5>, 0; mem:LD8[FixedStack5] GPR64:%vreg203
5296B		CBZX %vreg203, <BB#64>; GPR64:%vreg203
	    Successors according to CFG: BB#64 BB#63

5312B	BB#63: derived from LLVM BB %if.then.125
	    Predecessors according to CFG: BB#62
5328B		%vreg209<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg209
5344B		%vreg208<def> = LDRWui %vreg209, 1263; mem:LD4[%total_out_lo32] GPR32:%vreg208 GPR64common:%vreg209
5360B		%vreg206<def> = LDRXui <fi#5>, 0; mem:LD8[FixedStack5] GPR64common:%vreg206
5376B		STRWui %vreg208, %vreg206, 0; mem:ST4[%81] GPR32:%vreg208 GPR64common:%vreg206
	    Successors according to CFG: BB#64

5392B	BB#64: derived from LLVM BB %if.end.127
	    Predecessors according to CFG: BB#62 BB#63
5408B		%vreg211<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64:%vreg211
5424B		CBZX %vreg211, <BB#66>; GPR64:%vreg211
	    Successors according to CFG: BB#66 BB#65

5440B	BB#65: derived from LLVM BB %if.then.130
	    Predecessors according to CFG: BB#64
5456B		%vreg217<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg217
5472B		%vreg216<def> = LDRWui %vreg217, 1264; mem:LD4[%total_out_hi32] GPR32:%vreg216 GPR64common:%vreg217
5488B		%vreg214<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg214
5504B		STRWui %vreg216, %vreg214, 0; mem:ST4[%85] GPR32:%vreg216 GPR64common:%vreg214
	    Successors according to CFG: BB#66

5520B	BB#66: derived from LLVM BB %if.end.132
	    Predecessors according to CFG: BB#64 BB#65
5536B		%vreg219<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg219
5552B		CBZX %vreg219, <BB#68>; GPR64:%vreg219
	    Successors according to CFG: BB#68 BB#67

5568B	BB#67: derived from LLVM BB %if.then.135
	    Predecessors according to CFG: BB#66
5584B		%vreg221<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg221
5600B		STRWui %WZR, %vreg221, 0; mem:ST4[%87] GPR64common:%vreg221
	    Successors according to CFG: BB#68

5616B	BB#68: derived from LLVM BB %if.end.136
	    Predecessors according to CFG: BB#66 BB#67
5632B		%vreg223<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg223
5648B		CBZX %vreg223, <BB#70>; GPR64:%vreg223
	    Successors according to CFG: BB#70 BB#69

5664B	BB#69: derived from LLVM BB %if.then.139
	    Predecessors according to CFG: BB#68
5680B		%vreg225<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg225
5696B		STRWui %WZR, %vreg225, 1274; mem:ST4[%lastErr140] GPR64common:%vreg225
	    Successors according to CFG: BB#70

5712B	BB#70: derived from LLVM BB %if.end.141
	    Predecessors according to CFG: BB#68 BB#69
5728B		%vreg235<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg235
5744B		%vreg233<def> = MOVi64imm 5016; GPR64:%vreg233
5760B		%vreg234<def> = ADDXrr %vreg235, %vreg233; GPR64:%vreg234,%vreg235,%vreg233
5776B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5792B		%X0<def> = COPY %vreg234; GPR64:%vreg234
5808B		BL <ga:@BZ2_bzCompressEnd>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
5824B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5840B		%vreg231<def,dead> = COPY %W0; GPR32all:%vreg231
5856B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5872B		STACKMAP 8, 0, 0, <fi#10>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack10]
5888B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5904B		%vreg229<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg229
5920B		%vreg228<def> = COPY %vreg229; GPR64all:%vreg228 GPR64:%vreg229
5936B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5952B		%X0<def> = COPY %vreg228; GPR64all:%vreg228
5968B		BL <ga:@free>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>
5984B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
6000B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
6016B		STACKMAP 9, 0, %LR<earlyclobber,imp-def,dead>, ...
6032B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#71

6048B	BB#71: derived from LLVM BB %return
	    Predecessors according to CFG: BB#11 BB#43 BB#35 BB#56 BB#70 BB#17 BB#5
6064B		%vreg254<def> = ADRP <ga:@BZ2_bzWriteClose64>[TF=1]; GPR64common:%vreg254
6080B		%vreg255<def> = ADDXri %vreg254, <ga:@BZ2_bzWriteClose64>[TF=34], 0; GPR64sp:%vreg255 GPR64common:%vreg254
6096B		%vreg256<def> = COPY %vreg255; GPR64all:%vreg256 GPR64sp:%vreg255
6112B		%vreg257<def> = COPY %vreg24; GPR64all:%vreg257 GPR64:%vreg24
6128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
6144B		%X0<def> = COPY %vreg256; GPR64all:%vreg256
6160B		%X1<def> = COPY %vreg257; GPR64all:%vreg257
6176B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
6192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
6208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
6224B		STACKMAP 10, 0, %LR<earlyclobber,imp-def,dead>, ...
6240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
6256B		RET_ReallyLR

# End machine code for function BZ2_bzWriteClose64.

********** SIMPLE REGISTER COALESCING **********
********** Function: BZ2_bzWriteClose64
********** JOINING INTERVALS ***********
while.body:
2416B	%X0<def> = COPY %vreg78; GPR64:%vreg78
	Considering merging %vreg78 with %X0
	Can only merge into reserved registers.
2432B	%W1<def> = COPY %vreg74; GPR32:%vreg74
	Considering merging %vreg74 with %W1
	Can only merge into reserved registers.
Remat: %W1<def> = MOVi32imm 2
Shrink: %vreg74 [2224r,2432r:0)  0@2224r
All defs dead: 2224r	%vreg74<def,dead> = MOVi32imm 2; GPR32:%vreg74
Shrunk: %vreg74 [2224r,2224d:0)  0@2224r
Deleting dead def 2224r	%vreg74<def,dead> = MOVi32imm 2; GPR32:%vreg74
2480B	%vreg75<def> = COPY %W0; GPR32:%vreg75
	Considering merging %vreg75 with %W0
	Can only merge into reserved registers.
if.end.56:
if.end.84:
land.lhs.true.46:
if.then.60:
3232B	%X0<def> = COPY %vreg118; GPR64sp:%vreg118
	Considering merging %vreg118 with %X0
	Can only merge into reserved registers.
3248B	%X1<def> = COPY %vreg105; GPR64:%vreg105
	Considering merging %vreg105 with %X1
	Can only merge into reserved registers.
Remat: %X1<def> = MOVi64imm 1
Shrink: %vreg105 [3040r,3248r:0)  0@3040r
All defs dead: 3040r	%vreg105<def,dead> = MOVi64imm 1; GPR64:%vreg105
Shrunk: %vreg105 [3040r,3040d:0)  0@3040r
Deleting dead def 3040r	%vreg105<def,dead> = MOVi64imm 1; GPR64:%vreg105
3264B	%X2<def> = COPY %vreg115; GPR64:%vreg115
	Considering merging %vreg115 with %X2
	Can only merge into reserved registers.
3280B	%X3<def> = COPY %vreg110; GPR64:%vreg110
	Considering merging %vreg110 with %X3
	Can only merge into reserved registers.
3328B	%vreg108<def> = COPY %X0; GPR64all:%vreg108
	Considering merging %vreg108 with %X0
	Can only merge into reserved registers.
lor.lhs.false:
3552B	%X0<def> = COPY %vreg131; GPR64:%vreg131
	Considering merging %vreg131 with %X0
	Can only merge into reserved registers.
3600B	%vreg129<def> = COPY %W0; GPR32:%vreg129
	Considering merging %vreg129 with %W0
	Can only merge into reserved registers.
if.end.83:
if.end.88:
3392B	%vreg103<def> = COPY %vreg108:sub_32; GPR32:%vreg103 GPR64all:%vreg108
	Considering merging to GPR64 with %vreg103 in %vreg108:sub_32
		RHS = %vreg103 [3392r,3408r:0)  0@3392r
		LHS = %vreg108 [3328r,3392r:0)  0@3328r
		merge %vreg103:0@3392r into %vreg108:0@3328r --> @3328r
		erased:	3392r	%vreg103<def> = COPY %vreg108:sub_32; GPR32:%vreg103 GPR64all:%vreg108
		updated: 3408B	STRWui %vreg108:sub_32, <fi#8>, 0; mem:ST4[FixedStack8] GPR64:%vreg108
	Success: %vreg103:sub_32 -> %vreg108
	Result = %vreg108 [3328r,3408r:0)  0@3328r
return:
6144B	%X0<def> = COPY %vreg256; GPR64all:%vreg256
	Considering merging %vreg256 with %X0
	Can only merge into reserved registers.
6160B	%X1<def> = COPY %vreg257; GPR64all:%vreg257
	Considering merging %vreg257 with %X1
	Can only merge into reserved registers.
if.end.89:
if.end.112:
if.end:
if.end.10:
if.end.20:
if.end.28:
if.end.31:
if.end.34:
if.end.37:
if.end.51:
if.then.73:
if.end.77:
if.end.105:
if.end.117:
if.end.122:
if.end.127:
if.end.132:
if.end.136:
if.then:
if.end.5:
if.end.6:
if.then.7:
if.end.14:
if.end.15:
1296B	%X0<def> = COPY %vreg46; GPR64:%vreg46
	Considering merging %vreg46 with %X0
	Can only merge into reserved registers.
1344B	%vreg44<def> = COPY %W0; GPR32:%vreg44
	Considering merging %vreg44 with %W0
	Can only merge into reserved registers.
if.then.17:
if.end.24:
if.end.25:
land.lhs.true:
if.then.48:
if.end.55:
if.end.82:
land.lhs.true.91:
4240B	%X0<def> = COPY %vreg163; GPR64:%vreg163
	Considering merging %vreg163 with %X0
	Can only merge into reserved registers.
4288B	%vreg161<def> = COPY %W0; GPR32:%vreg161
	Considering merging %vreg161 with %W0
	Can only merge into reserved registers.
if.then.95:
4432B	%X0<def> = COPY %vreg174; GPR64:%vreg174
	Considering merging %vreg174 with %X0
	Can only merge into reserved registers.
4480B	%vreg172<def,dead> = COPY %W0; GPR32all:%vreg172
	Considering merging %vreg172 with %W0
	Can only merge into reserved registers.
4592B	%X0<def> = COPY %vreg169; GPR64:%vreg169
	Considering merging %vreg169 with %X0
	Can only merge into reserved registers.
4640B	%vreg167<def> = COPY %W0; GPR32:%vreg167
	Considering merging %vreg167 with %W0
	Can only merge into reserved registers.
if.then.101:
if.end.110:
if.end.141:
5792B	%X0<def> = COPY %vreg234; GPR64:%vreg234
	Considering merging %vreg234 with %X0
	Can only merge into reserved registers.
5840B	%vreg231<def,dead> = COPY %W0; GPR32all:%vreg231
	Considering merging %vreg231 with %W0
	Can only merge into reserved registers.
5952B	%X0<def> = COPY %vreg228; GPR64all:%vreg228
	Considering merging %vreg228 with %X0
	Can only merge into reserved registers.
entry:
16B	%vreg24<def> = COPY %LR; GPR64:%vreg24
	Considering merging %vreg24 with %LR
	Can only merge into reserved registers.
32B	%vreg12<def> = COPY %X6; GPR64:%vreg12
	Considering merging %vreg12 with %X6
	Can only merge into reserved registers.
48B	%vreg10<def> = COPY %X5; GPR64:%vreg10
	Considering merging %vreg10 with %X5
	Can only merge into reserved registers.
64B	%vreg8<def> = COPY %X4; GPR64:%vreg8
	Considering merging %vreg8 with %X4
	Can only merge into reserved registers.
80B	%vreg6<def> = COPY %X3; GPR64:%vreg6
	Considering merging %vreg6 with %X3
	Can only merge into reserved registers.
96B	%vreg4<def> = COPY %W2; GPR32:%vreg4
	Considering merging %vreg4 with %W2
	Can only merge into reserved registers.
112B	%vreg2<def> = COPY %X1; GPR64:%vreg2
	Considering merging %vreg2 with %X1
	Can only merge into reserved registers.
128B	%vreg0<def> = COPY %X0; GPR64:%vreg0
	Considering merging %vreg0 with %X0
	Can only merge into reserved registers.
336B	%X0<def> = COPY %vreg22; GPR64all:%vreg22
	Considering merging %vreg22 with %X0
	Can only merge into reserved registers.
352B	%X1<def> = COPY %vreg23; GPR64all:%vreg23
	Considering merging %vreg23 with %X1
	Can only merge into reserved registers.
if.then.2:
if.then.4:
if.then.9:
if.then.12:
if.then.19:
if.then.22:
if.then.27:
if.then.30:
if.then.33:
if.then.36:
if.then.41:
if.then.50:
if.then.53:
if.then.76:
if.then.80:
if.then.87:
while.end:
if.then.104:
if.then.108:
if.end.111:
if.then.115:
if.then.120:
if.then.125:
if.then.130:
if.then.135:
if.then.139:
6096B	%vreg256<def> = COPY %vreg255; GPR64all:%vreg256 GPR64sp:%vreg255
	Considering merging to GPR64sp with %vreg255 in %vreg256
		RHS = %vreg255 [6080r,6096r:0)  0@6080r
		LHS = %vreg256 [6096r,6144r:0)  0@6096r
		merge %vreg256:0@6096r into %vreg255:0@6080r --> @6080r
		erased:	6096r	%vreg256<def> = COPY %vreg255; GPR64all:%vreg256 GPR64sp:%vreg255
		updated: 6080B	%vreg256<def> = ADDXri %vreg254, <ga:@BZ2_bzWriteClose64>[TF=34], 0; GPR64sp:%vreg256 GPR64common:%vreg254
	Success: %vreg255 -> %vreg256
	Result = %vreg256 [6080r,6144r:0)  0@6080r
6112B	%vreg257<def> = COPY %vreg24; GPR64all:%vreg257 GPR64:%vreg24
	Considering merging to GPR64 with %vreg24 in %vreg257
		RHS = %vreg24 [16r,6112r:0)  0@16r
		LHS = %vreg257 [6112r,6160r:0)  0@6112r
		merge %vreg257:0@6112r into %vreg24:0@16r --> @16r
		erased:	6112r	%vreg257<def> = COPY %vreg24; GPR64all:%vreg257 GPR64:%vreg24
		updated: 16B	%vreg257<def> = COPY %LR; GPR64:%vreg257
		updated: 304B	%vreg23<def> = COPY %vreg257; GPR64all:%vreg23 GPR64:%vreg257
	Success: %vreg24 -> %vreg257
	Result = %vreg257 [16r,6160r:0)  0@16r
5920B	%vreg228<def> = COPY %vreg229; GPR64all:%vreg228 GPR64:%vreg229
	Considering merging to GPR64 with %vreg229 in %vreg228
		RHS = %vreg229 [5904r,5920r:0)  0@5904r
		LHS = %vreg228 [5920r,5952r:0)  0@5920r
		merge %vreg228:0@5920r into %vreg229:0@5904r --> @5904r
		erased:	5920r	%vreg228<def> = COPY %vreg229; GPR64all:%vreg228 GPR64:%vreg229
		updated: 5904B	%vreg228<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg228
	Success: %vreg229 -> %vreg228
	Result = %vreg228 [5904r,5952r:0)  0@5904r
144B	%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
	Considering merging to GPR64 with %vreg0 in %vreg1
		RHS = %vreg0 [128r,144r:0)  0@128r
		LHS = %vreg1 [144r,448r:0)  0@144r
		merge %vreg1:0@144r into %vreg0:0@128r --> @128r
		erased:	144r	%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
		updated: 128B	%vreg1<def> = COPY %X0; GPR64:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [128r,448r:0)  0@128r
160B	%vreg3<def> = COPY %vreg2; GPR64:%vreg3,%vreg2
	Considering merging to GPR64 with %vreg2 in %vreg3
		RHS = %vreg2 [112r,160r:0)  0@112r
		LHS = %vreg3 [160r,464r:0)  0@160r
		merge %vreg3:0@160r into %vreg2:0@112r --> @112r
		erased:	160r	%vreg3<def> = COPY %vreg2; GPR64:%vreg3,%vreg2
		updated: 112B	%vreg3<def> = COPY %X1; GPR64:%vreg3
	Success: %vreg2 -> %vreg3
	Result = %vreg3 [112r,464r:0)  0@112r
176B	%vreg5<def> = COPY %vreg4; GPR32:%vreg5,%vreg4
	Considering merging to GPR32 with %vreg4 in %vreg5
		RHS = %vreg4 [96r,176r:0)  0@96r
		LHS = %vreg5 [176r,480r:0)  0@176r
		merge %vreg5:0@176r into %vreg4:0@96r --> @96r
		erased:	176r	%vreg5<def> = COPY %vreg4; GPR32:%vreg5,%vreg4
		updated: 96B	%vreg5<def> = COPY %W2; GPR32:%vreg5
	Success: %vreg4 -> %vreg5
	Result = %vreg5 [96r,480r:0)  0@96r
192B	%vreg7<def> = COPY %vreg6; GPR64:%vreg7,%vreg6
	Considering merging to GPR64 with %vreg6 in %vreg7
		RHS = %vreg6 [80r,192r:0)  0@80r
		LHS = %vreg7 [192r,496r:0)  0@192r
		merge %vreg7:0@192r into %vreg6:0@80r --> @80r
		erased:	192r	%vreg7<def> = COPY %vreg6; GPR64:%vreg7,%vreg6
		updated: 80B	%vreg7<def> = COPY %X3; GPR64:%vreg7
	Success: %vreg6 -> %vreg7
	Result = %vreg7 [80r,496r:0)  0@80r
208B	%vreg9<def> = COPY %vreg8; GPR64:%vreg9,%vreg8
	Considering merging to GPR64 with %vreg8 in %vreg9
		RHS = %vreg8 [64r,208r:0)  0@64r
		LHS = %vreg9 [208r,512r:0)  0@208r
		merge %vreg9:0@208r into %vreg8:0@64r --> @64r
		erased:	208r	%vreg9<def> = COPY %vreg8; GPR64:%vreg9,%vreg8
		updated: 64B	%vreg9<def> = COPY %X4; GPR64:%vreg9
	Success: %vreg8 -> %vreg9
	Result = %vreg9 [64r,512r:0)  0@64r
224B	%vreg11<def> = COPY %vreg10; GPR64:%vreg11,%vreg10
	Considering merging to GPR64 with %vreg10 in %vreg11
		RHS = %vreg10 [48r,224r:0)  0@48r
		LHS = %vreg11 [224r,528r:0)  0@224r
		merge %vreg11:0@224r into %vreg10:0@48r --> @48r
		erased:	224r	%vreg11<def> = COPY %vreg10; GPR64:%vreg11,%vreg10
		updated: 48B	%vreg11<def> = COPY %X5; GPR64:%vreg11
	Success: %vreg10 -> %vreg11
	Result = %vreg11 [48r,528r:0)  0@48r
240B	%vreg13<def> = COPY %vreg12; GPR64:%vreg13,%vreg12
	Considering merging to GPR64 with %vreg12 in %vreg13
		RHS = %vreg12 [32r,240r:0)  0@32r
		LHS = %vreg13 [240r,544r:0)  0@240r
		merge %vreg13:0@240r into %vreg12:0@32r --> @32r
		erased:	240r	%vreg13<def> = COPY %vreg12; GPR64:%vreg13,%vreg12
		updated: 32B	%vreg13<def> = COPY %X6; GPR64:%vreg13
	Success: %vreg12 -> %vreg13
	Result = %vreg13 [32r,544r:0)  0@32r
288B	%vreg22<def> = COPY %vreg21; GPR64all:%vreg22 GPR64sp:%vreg21
	Considering merging to GPR64sp with %vreg21 in %vreg22
		RHS = %vreg21 [272r,288r:0)  0@272r
		LHS = %vreg22 [288r,336r:0)  0@288r
		merge %vreg22:0@288r into %vreg21:0@272r --> @272r
		erased:	288r	%vreg22<def> = COPY %vreg21; GPR64all:%vreg22 GPR64sp:%vreg21
		updated: 272B	%vreg22<def> = ADDXri %vreg20, <ga:@BZ2_bzWriteClose64>[TF=34], 0; GPR64sp:%vreg22 GPR64common:%vreg20
	Success: %vreg21 -> %vreg22
	Result = %vreg22 [272r,336r:0)  0@272r
304B	%vreg23<def> = COPY %vreg257; GPR64all:%vreg23 GPR64:%vreg257
	Considering merging to GPR64 with %vreg257 in %vreg23
		RHS = %vreg257 [16r,6160r:0)  0@16r
		LHS = %vreg23 [304r,352r:0)  0@304r
		merge %vreg23:0@304r into %vreg257:0@16r --> @16r
		erased:	304r	%vreg23<def> = COPY %vreg257; GPR64all:%vreg23 GPR64:%vreg257
		updated: 16B	%vreg23<def> = COPY %LR; GPR64:%vreg23
		updated: 6160B	%X1<def> = COPY %vreg23; GPR64:%vreg23
	Success: %vreg257 -> %vreg23
	Result = %vreg23 [16r,6160r:0)  0@16r
576B	%vreg18<def> = COPY %vreg19; GPR64:%vreg18,%vreg19
	Considering merging to GPR64 with %vreg19 in %vreg18
		RHS = %vreg19 [560r,576r:0)  0@560r
		LHS = %vreg18 [576r,592r:0)  0@576r
		merge %vreg18:0@576r into %vreg19:0@560r --> @560r
		erased:	576r	%vreg18<def> = COPY %vreg19; GPR64:%vreg18,%vreg19
		updated: 560B	%vreg18<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg18
	Success: %vreg19 -> %vreg18
	Result = %vreg18 [560r,592r:0)  0@560r
6144B	%X0<def> = COPY %vreg256; GPR64sp:%vreg256
	Considering merging %vreg256 with %X0
	Can only merge into reserved registers.
6160B	%X1<def> = COPY %vreg23; GPR64:%vreg23
	Considering merging %vreg23 with %X1
	Can only merge into reserved registers.
5952B	%X0<def> = COPY %vreg228; GPR64:%vreg228
	Considering merging %vreg228 with %X0
	Can only merge into reserved registers.
336B	%X0<def> = COPY %vreg22; GPR64sp:%vreg22
	Considering merging %vreg22 with %X0
	Can only merge into reserved registers.
352B	%X1<def> = COPY %vreg23; GPR64:%vreg23
	Considering merging %vreg23 with %X1
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
W30 [0B,16r:0)[368r,368d:22)[416e,416d:9)[1312r,1312d:21)[1376e,1376d:8)[2448r,2448d:20)[2512e,2512d:7)[3296r,3296d:19)[3360e,3360d:6)[3568r,3568d:18)[3632e,3632d:5)[4256r,4256d:17)[4320e,4320d:4)[4448r,4448d:15)[4512e,4512d:3)[4608r,4608d:16)[4672e,4672d:2)[5808r,5808d:12)[5872e,5872d:1)[5968r,5968d:13)[6016e,6016d:14)[6176r,6176d:10)[6224e,6224d:11)  0@0B-phi 1@5872e 2@4672e 3@4512e 4@4320e 5@3632e 6@3360e 7@2512e 8@1376e 9@416e 10@6176r 11@6224e 12@5808r 13@5968r 14@6016e 15@4448r 16@4608r 17@4256r 18@3568r 19@3296r 20@2448r 21@1312r 22@368r
W0 [0B,128r:0)[336r,368r:19)[1296r,1312r:18)[1312r,1344r:7)[2416r,2448r:17)[2448r,2480r:6)[3232r,3296r:16)[3296r,3328r:15)[3552r,3568r:14)[3568r,3600r:5)[4240r,4256r:13)[4256r,4288r:4)[4432r,4448r:11)[4448r,4480r:2)[4592r,4608r:12)[4608r,4640r:3)[5792r,5808r:9)[5808r,5840r:1)[5952r,5968r:10)[6144r,6176r:8)  0@0B-phi 1@5808r 2@4448r 3@4608r 4@4256r 5@3568r 6@2448r 7@1312r 8@6144r 9@5792r 10@5952r 11@4432r 12@4592r 13@4240r 14@3552r 15@3296r 16@3232r 17@2416r 18@1296r 19@336r
W1 [0B,112r:0)[352r,368r:4)[2432r,2448r:1)[3248r,3296r:3)[6160r,6176r:2)  0@0B-phi 1@2432r 2@6160r 3@3248r 4@352r
W2 [0B,96r:0)[3264r,3296r:1)  0@0B-phi 1@3264r
W3 [0B,80r:0)[3280r,3296r:1)  0@0B-phi 1@3280r
W4 [0B,64r:0)  0@0B-phi
W5 [0B,48r:0)  0@0B-phi
W6 [0B,32r:0)  0@0B-phi
%vreg1 [128r,448r:0)  0@128r
%vreg3 [112r,464r:0)  0@112r
%vreg5 [96r,480r:0)  0@96r
%vreg7 [80r,496r:0)  0@80r
%vreg9 [64r,512r:0)  0@64r
%vreg11 [48r,528r:0)  0@48r
%vreg13 [32r,544r:0)  0@32r
%vreg15 [608r,624r:0)  0@608r
%vreg18 [560r,592r:0)  0@560r
%vreg20 [256r,272r:0)  0@256r
%vreg22 [272r,336r:0)  0@272r
%vreg23 [16r,6160r:0)  0@16r
%vreg26 [944r,960r:0)  0@944r
%vreg28 [896r,912r:0)  0@896r
%vreg29 [912r,928r:0)  0@912r
%vreg30 [928r,944r:0)  0@928r
%vreg31 [880r,912r:0)  0@880r
%vreg33 [992r,1008r:0)  0@992r
%vreg34 [1040r,1072r:0)  0@1040r
%vreg36 [1056r,1072r:0)  0@1056r
%vreg38 [1104r,1120r:0)  0@1104r
%vreg39 [1152r,1184r:0)  0@1152r
%vreg41 [1168r,1184r:0)  0@1168r
%vreg44 [1344r,1408r:0)  0@1344r
%vreg46 [1264r,1296r:0)  0@1264r
%vreg47 [1248r,1264r:0)  0@1248r
%vreg49 [1696r,1712r:0)  0@1696r
%vreg51 [1744r,1760r:0)  0@1744r
%vreg53 [1792r,1808r:0)  0@1792r
%vreg55 [1840r,1856r:0)  0@1840r
%vreg57 [1888r,1904r:0)  0@1888r
%vreg59 [1936r,1952r:0)  0@1936r
%vreg61 [1984r,2000r:0)  0@1984r
%vreg63 [2032r,2048r:0)  0@2032r
%vreg65 [2080r,2096r:0)  0@2080r
%vreg68 [2144r,2160r:0)  0@2144r
%vreg69 [2128r,2144r:0)  0@2128r
%vreg71 [2560r,2576r:0)  0@2560r
%vreg75 [2480r,2544r:0)  0@2480r
%vreg77 [2368r,2384r:0)  0@2368r
%vreg78 [2384r,2416r:0)  0@2384r
%vreg79 [2352r,2384r:0)  0@2352r
%vreg82 [2320r,2336r:0)  0@2320r
%vreg85 [2304r,2336r:0)  0@2304r
%vreg86 [2288r,2304r:0)  0@2288r
%vreg87 [2240r,2272r:0)  0@2240r
%vreg89 [2256r,2272r:0)  0@2256r
%vreg91 [2624r,2640r:0)  0@2624r
%vreg93 [2944r,2992r:0)  0@2944r
%vreg95 [2976r,2992r:0)  0@2976r
%vreg96 [2960r,2976r:0)  0@2960r
%vreg99 [3440r,3456r:0)  0@3440r
%vreg100 [3424r,3456r:0)  0@3424r
%vreg108 [3328r,3408r:0)  0@3328r
%vreg110 [3200r,3280r:0)  0@3200r
%vreg111 [3184r,3200r:0)  0@3184r
%vreg115 [3168r,3264r:0)  0@3168r
%vreg118 [3152r,3232r:0)  0@3152r
%vreg119 [3136r,3152r:0)  0@3136r
%vreg121 [3056r,3104r:0)  0@3056r
%vreg123 [3104r,3120r:0)  0@3104r
%vreg125 [3088r,3104r:0)  0@3088r
%vreg126 [3072r,3088r:0)  0@3072r
%vreg129 [3600r,3664r:0)  0@3600r
%vreg131 [3520r,3552r:0)  0@3520r
%vreg132 [3504r,3520r:0)  0@3504r
%vreg134 [3984r,4000r:0)  0@3984r
%vreg136 [3696r,3712r:0)  0@3696r
%vreg137 [3744r,3776r:0)  0@3744r
%vreg139 [3760r,3776r:0)  0@3760r
%vreg141 [3808r,3824r:0)  0@3808r
%vreg142 [3856r,3888r:0)  0@3856r
%vreg144 [3872r,3888r:0)  0@3872r
%vreg146 [2688r,2704r:0)  0@2688r
%vreg149 [2752r,2768r:0)  0@2752r
%vreg150 [2736r,2768r:0)  0@2736r
%vreg152 [2800r,2816r:0)  0@2800r
%vreg155 [2864r,2880r:0)  0@2864r
%vreg156 [2848r,2880r:0)  0@2848r
%vreg158 [4144r,4160r:0)  0@4144r
%vreg161 [4288r,4352r:0)  0@4288r
%vreg163 [4208r,4240r:0)  0@4208r
%vreg164 [4192r,4208r:0)  0@4192r
%vreg167 [4640r,4704r:0)  0@4640r
%vreg169 [4560r,4592r:0)  0@4560r
%vreg170 [4544r,4560r:0)  0@4544r
%vreg172 [4480r,4480d:0)  0@4480r
%vreg174 [4400r,4432r:0)  0@4400r
%vreg175 [4384r,4400r:0)  0@4384r
%vreg177 [4736r,4752r:0)  0@4736r
%vreg178 [4784r,4816r:0)  0@4784r
%vreg180 [4800r,4816r:0)  0@4800r
%vreg182 [4848r,4864r:0)  0@4848r
%vreg183 [4896r,4928r:0)  0@4896r
%vreg185 [4912r,4928r:0)  0@4912r
%vreg187 [5024r,5040r:0)  0@5024r
%vreg190 [5104r,5120r:0)  0@5104r
%vreg192 [5088r,5120r:0)  0@5088r
%vreg193 [5072r,5088r:0)  0@5072r
%vreg195 [5152r,5168r:0)  0@5152r
%vreg198 [5232r,5248r:0)  0@5232r
%vreg200 [5216r,5248r:0)  0@5216r
%vreg201 [5200r,5216r:0)  0@5200r
%vreg203 [5280r,5296r:0)  0@5280r
%vreg206 [5360r,5376r:0)  0@5360r
%vreg208 [5344r,5376r:0)  0@5344r
%vreg209 [5328r,5344r:0)  0@5328r
%vreg211 [5408r,5424r:0)  0@5408r
%vreg214 [5488r,5504r:0)  0@5488r
%vreg216 [5472r,5504r:0)  0@5472r
%vreg217 [5456r,5472r:0)  0@5456r
%vreg219 [5536r,5552r:0)  0@5536r
%vreg221 [5584r,5600r:0)  0@5584r
%vreg223 [5632r,5648r:0)  0@5632r
%vreg225 [5680r,5696r:0)  0@5680r
%vreg228 [5904r,5952r:0)  0@5904r
%vreg231 [5840r,5840d:0)  0@5840r
%vreg233 [5744r,5760r:0)  0@5744r
%vreg234 [5760r,5792r:0)  0@5760r
%vreg235 [5728r,5760r:0)  0@5728r
%vreg237 [1440r,1456r:0)  0@1440r
%vreg238 [1488r,1520r:0)  0@1488r
%vreg240 [1504r,1520r:0)  0@1504r
%vreg242 [1552r,1568r:0)  0@1552r
%vreg243 [1600r,1632r:0)  0@1600r
%vreg245 [1616r,1632r:0)  0@1616r
%vreg247 [656r,672r:0)  0@656r
%vreg249 [704r,720r:0)  0@704r
%vreg251 [752r,768r:0)  0@752r
%vreg253 [800r,816r:0)  0@800r
%vreg254 [6064r,6080r:0)  0@6064r
%vreg256 [6080r,6144r:0)  0@6080r
RegMasks: 368r 1312r 2448r 3296r 3568r 4256r 4448r 4608r 5808r 5968r 6176r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzWriteClose64: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=4, align=4, at location [SP]
  fi#3: size=8, align=8, at location [SP]
  fi#4: size=8, align=8, at location [SP]
  fi#5: size=8, align=8, at location [SP]
  fi#6: size=8, align=8, at location [SP]
  fi#7: size=4, align=4, at location [SP]
  fi#8: size=4, align=4, at location [SP]
  fi#9: size=4, align=4, at location [SP]
  fi#10: size=8, align=8, at location [SP]
Function Live Ins: %X0 in %vreg0, %X1 in %vreg2, %W2 in %vreg4, %X3 in %vreg6, %X4 in %vreg8, %X5 in %vreg10, %X6 in %vreg12, %LR in %vreg24

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %X1 %W2 %X3 %X4 %X5 %X6 %LR
16B		%vreg23<def> = COPY %LR; GPR64:%vreg23
32B		%vreg13<def> = COPY %X6; GPR64:%vreg13
48B		%vreg11<def> = COPY %X5; GPR64:%vreg11
64B		%vreg9<def> = COPY %X4; GPR64:%vreg9
80B		%vreg7<def> = COPY %X3; GPR64:%vreg7
96B		%vreg5<def> = COPY %W2; GPR32:%vreg5
112B		%vreg3<def> = COPY %X1; GPR64:%vreg3
128B		%vreg1<def> = COPY %X0; GPR64:%vreg1
256B		%vreg20<def> = ADRP <ga:@BZ2_bzWriteClose64>[TF=1]; GPR64common:%vreg20
272B		%vreg22<def> = ADDXri %vreg20, <ga:@BZ2_bzWriteClose64>[TF=34], 0; GPR64sp:%vreg22 GPR64common:%vreg20
320B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
336B		%X0<def> = COPY %vreg22; GPR64sp:%vreg22
352B		%X1<def> = COPY %vreg23; GPR64:%vreg23
368B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
384B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
400B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
416B		STACKMAP 0, 0, %vreg5, 0, <fi#2>, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, %vreg9, 0, <fi#4>, 0, %vreg7, 0, <fi#3>, 0, %vreg13, 0, <fi#6>, 0, %vreg11, 0, <fi#5>, 0, 0, <fi#9>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4) GPR32:%vreg5 GPR64:%vreg3,%vreg1,%vreg9,%vreg7,%vreg13,%vreg11
432B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
448B		STRXui %vreg1, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg1
464B		STRXui %vreg3, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg3
480B		STRWui %vreg5, <fi#2>, 0; mem:ST4[FixedStack2] GPR32:%vreg5
496B		STRXui %vreg7, <fi#3>, 0; mem:ST8[FixedStack3] GPR64:%vreg7
512B		STRXui %vreg9, <fi#4>, 0; mem:ST8[FixedStack4] GPR64:%vreg9
528B		STRXui %vreg11, <fi#5>, 0; mem:ST8[FixedStack5] GPR64:%vreg11
544B		STRXui %vreg13, <fi#6>, 0; mem:ST8[FixedStack6] GPR64:%vreg13
560B		%vreg18<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg18
592B		STRXui %vreg18, <fi#10>, 0; mem:ST8[FixedStack10] GPR64:%vreg18
608B		%vreg15<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg15
624B		CBNZX %vreg15, <BB#6>; GPR64:%vreg15
	    Successors according to CFG: BB#6 BB#1

640B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
656B		%vreg247<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg247
672B		CBZX %vreg247, <BB#3>; GPR64:%vreg247
	    Successors according to CFG: BB#3 BB#2

688B	BB#2: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#1
704B		%vreg249<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg249
720B		STRWui %WZR, %vreg249, 0; mem:ST4[%4] GPR64common:%vreg249
	    Successors according to CFG: BB#3

736B	BB#3: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#1 BB#2
752B		%vreg251<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg251
768B		CBZX %vreg251, <BB#5>; GPR64:%vreg251
	    Successors according to CFG: BB#5 BB#4

784B	BB#4: derived from LLVM BB %if.then.4
	    Predecessors according to CFG: BB#3
800B		%vreg253<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg253
816B		STRWui %WZR, %vreg253, 1274; mem:ST4[%lastErr] GPR64common:%vreg253
	    Successors according to CFG: BB#5

832B	BB#5: derived from LLVM BB %if.end.5
	    Predecessors according to CFG: BB#3 BB#4
848B		B <BB#71>
	    Successors according to CFG: BB#71

864B	BB#6: derived from LLVM BB %if.end.6
	    Predecessors according to CFG: BB#0
880B		%vreg31<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg31
896B		%vreg28<def> = MOVi64imm 5012; GPR64:%vreg28
912B		%vreg29<def> = ADDXrr %vreg31, %vreg28; GPR64common:%vreg29 GPR64:%vreg31,%vreg28
928B		%vreg30<def> = LDRBBui %vreg29, 0; mem:LD1[%writing] GPR32:%vreg30 GPR64common:%vreg29
944B		%vreg26<def> = UBFMWri %vreg30, 0, 7; GPR32:%vreg26,%vreg30
960B		CBNZW %vreg26, <BB#12>; GPR32:%vreg26
	    Successors according to CFG: BB#12 BB#7

976B	BB#7: derived from LLVM BB %if.then.7
	    Predecessors according to CFG: BB#6
992B		%vreg33<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg33
1008B		CBZX %vreg33, <BB#9>; GPR64:%vreg33
	    Successors according to CFG: BB#9 BB#8

1024B	BB#8: derived from LLVM BB %if.then.9
	    Predecessors according to CFG: BB#7
1040B		%vreg34<def> = MOVi32imm 4294967295; GPR32:%vreg34
1056B		%vreg36<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg36
1072B		STRWui %vreg34, %vreg36, 0; mem:ST4[%10] GPR32:%vreg34 GPR64common:%vreg36
	    Successors according to CFG: BB#9

1088B	BB#9: derived from LLVM BB %if.end.10
	    Predecessors according to CFG: BB#7 BB#8
1104B		%vreg38<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg38
1120B		CBZX %vreg38, <BB#11>; GPR64:%vreg38
	    Successors according to CFG: BB#11 BB#10

1136B	BB#10: derived from LLVM BB %if.then.12
	    Predecessors according to CFG: BB#9
1152B		%vreg39<def> = MOVi32imm 4294967295; GPR32:%vreg39
1168B		%vreg41<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg41
1184B		STRWui %vreg39, %vreg41, 1274; mem:ST4[%lastErr13] GPR32:%vreg39 GPR64common:%vreg41
	    Successors according to CFG: BB#11

1200B	BB#11: derived from LLVM BB %if.end.14
	    Predecessors according to CFG: BB#9 BB#10
1216B		B <BB#71>
	    Successors according to CFG: BB#71

1232B	BB#12: derived from LLVM BB %if.end.15
	    Predecessors according to CFG: BB#6
1248B		%vreg47<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg47
1264B		%vreg46<def> = LDRXui %vreg47, 0; mem:LD8[%handle] GPR64:%vreg46 GPR64common:%vreg47
1280B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1296B		%X0<def> = COPY %vreg46; GPR64:%vreg46
1312B		BL <ga:@ferror>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
1328B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1344B		%vreg44<def> = COPY %W0; GPR32:%vreg44
1360B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1376B		STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, 0, <fi#9>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4)
1392B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1408B		CBZW %vreg44, <BB#18>; GPR32:%vreg44
	    Successors according to CFG: BB#18 BB#13

1424B	BB#13: derived from LLVM BB %if.then.17
	    Predecessors according to CFG: BB#12
1440B		%vreg237<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg237
1456B		CBZX %vreg237, <BB#15>; GPR64:%vreg237
	    Successors according to CFG: BB#15 BB#14

1472B	BB#14: derived from LLVM BB %if.then.19
	    Predecessors according to CFG: BB#13
1488B		%vreg238<def> = MOVi32imm 4294967290; GPR32:%vreg238
1504B		%vreg240<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg240
1520B		STRWui %vreg238, %vreg240, 0; mem:ST4[%16] GPR32:%vreg238 GPR64common:%vreg240
	    Successors according to CFG: BB#15

1536B	BB#15: derived from LLVM BB %if.end.20
	    Predecessors according to CFG: BB#13 BB#14
1552B		%vreg242<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg242
1568B		CBZX %vreg242, <BB#17>; GPR64:%vreg242
	    Successors according to CFG: BB#17 BB#16

1584B	BB#16: derived from LLVM BB %if.then.22
	    Predecessors according to CFG: BB#15
1600B		%vreg243<def> = MOVi32imm 4294967290; GPR32:%vreg243
1616B		%vreg245<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg245
1632B		STRWui %vreg243, %vreg245, 1274; mem:ST4[%lastErr23] GPR32:%vreg243 GPR64common:%vreg245
	    Successors according to CFG: BB#17

1648B	BB#17: derived from LLVM BB %if.end.24
	    Predecessors according to CFG: BB#15 BB#16
1664B		B <BB#71>
	    Successors according to CFG: BB#71

1680B	BB#18: derived from LLVM BB %if.end.25
	    Predecessors according to CFG: BB#12
1696B		%vreg49<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg49
1712B		CBZX %vreg49, <BB#20>; GPR64:%vreg49
	    Successors according to CFG: BB#20 BB#19

1728B	BB#19: derived from LLVM BB %if.then.27
	    Predecessors according to CFG: BB#18
1744B		%vreg51<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg51
1760B		STRWui %WZR, %vreg51, 0; mem:ST4[%20] GPR64common:%vreg51
	    Successors according to CFG: BB#20

1776B	BB#20: derived from LLVM BB %if.end.28
	    Predecessors according to CFG: BB#18 BB#19
1792B		%vreg53<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64:%vreg53
1808B		CBZX %vreg53, <BB#22>; GPR64:%vreg53
	    Successors according to CFG: BB#22 BB#21

1824B	BB#21: derived from LLVM BB %if.then.30
	    Predecessors according to CFG: BB#20
1840B		%vreg55<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg55
1856B		STRWui %WZR, %vreg55, 0; mem:ST4[%22] GPR64common:%vreg55
	    Successors according to CFG: BB#22

1872B	BB#22: derived from LLVM BB %if.end.31
	    Predecessors according to CFG: BB#20 BB#21
1888B		%vreg57<def> = LDRXui <fi#5>, 0; mem:LD8[FixedStack5] GPR64:%vreg57
1904B		CBZX %vreg57, <BB#24>; GPR64:%vreg57
	    Successors according to CFG: BB#24 BB#23

1920B	BB#23: derived from LLVM BB %if.then.33
	    Predecessors according to CFG: BB#22
1936B		%vreg59<def> = LDRXui <fi#5>, 0; mem:LD8[FixedStack5] GPR64common:%vreg59
1952B		STRWui %WZR, %vreg59, 0; mem:ST4[%24] GPR64common:%vreg59
	    Successors according to CFG: BB#24

1968B	BB#24: derived from LLVM BB %if.end.34
	    Predecessors according to CFG: BB#22 BB#23
1984B		%vreg61<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64:%vreg61
2000B		CBZX %vreg61, <BB#26>; GPR64:%vreg61
	    Successors according to CFG: BB#26 BB#25

2016B	BB#25: derived from LLVM BB %if.then.36
	    Predecessors according to CFG: BB#24
2032B		%vreg63<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg63
2048B		STRWui %WZR, %vreg63, 0; mem:ST4[%26] GPR64common:%vreg63
	    Successors according to CFG: BB#26

2064B	BB#26: derived from LLVM BB %if.end.37
	    Predecessors according to CFG: BB#24 BB#25
2080B		%vreg65<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg65
2096B		CBNZW %vreg65, <BB#49>; GPR32:%vreg65
	    Successors according to CFG: BB#49 BB#27

2112B	BB#27: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#26
2128B		%vreg69<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg69
2144B		%vreg68<def> = LDRWui %vreg69, 1274; mem:LD4[%lastErr39] GPR32:%vreg68 GPR64common:%vreg69
2160B		CBNZW %vreg68, <BB#49>; GPR32:%vreg68
	    Successors according to CFG: BB#49 BB#28

2176B	BB#28: derived from LLVM BB %if.then.41
	    Predecessors according to CFG: BB#27
2192B		B <BB#29>
	    Successors according to CFG: BB#29

2208B	BB#29: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#28 BB#47
2240B		%vreg87<def> = MOVi32imm 5000; GPR32:%vreg87
2256B		%vreg89<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg89
2272B		STRWui %vreg87, %vreg89, 1262; mem:ST4[%avail_out] GPR32:%vreg87 GPR64common:%vreg89
2288B		%vreg86<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg86
2304B		%vreg85<def> = ADDXri %vreg86, 8, 0; GPR64common:%vreg85,%vreg86
2320B		%vreg82<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg82
2336B		STRXui %vreg85, %vreg82, 630; mem:ST8[%next_out] GPR64common:%vreg85,%vreg82
2352B		%vreg79<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg79
2368B		%vreg77<def> = MOVi64imm 5016; GPR64:%vreg77
2384B		%vreg78<def> = ADDXrr %vreg79, %vreg77; GPR64:%vreg78,%vreg79,%vreg77
2400B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2416B		%X0<def> = COPY %vreg78; GPR64:%vreg78
2432B		%W1<def> = MOVi32imm 2
2448B		BL <ga:@BZ2_bzCompress>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %W0<imp-def>
2464B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2480B		%vreg75<def> = COPY %W0; GPR32:%vreg75
2496B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2512B		STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, 0, <fi#9>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4)
2528B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2544B		STRWui %vreg75, <fi#9>, 0; mem:ST4[FixedStack9] GPR32:%vreg75
2560B		%vreg71<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32common:%vreg71
2576B		%WZR<def> = SUBSWri %vreg71, 3, 0, %NZCV<imp-def>; GPR32common:%vreg71
2592B		Bcc 0, <BB#36>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#36 BB#30

2608B	BB#30: derived from LLVM BB %land.lhs.true.46
	    Predecessors according to CFG: BB#29
2624B		%vreg91<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32common:%vreg91
2640B		%WZR<def> = SUBSWri %vreg91, 4, 0, %NZCV<imp-def>; GPR32common:%vreg91
2656B		Bcc 0, <BB#36>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#36 BB#31

2672B	BB#31: derived from LLVM BB %if.then.48
	    Predecessors according to CFG: BB#30
2688B		%vreg146<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg146
2704B		CBZX %vreg146, <BB#33>; GPR64:%vreg146
	    Successors according to CFG: BB#33 BB#32

2720B	BB#32: derived from LLVM BB %if.then.50
	    Predecessors according to CFG: BB#31
2736B		%vreg150<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32:%vreg150
2752B		%vreg149<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg149
2768B		STRWui %vreg150, %vreg149, 0; mem:ST4[%38] GPR32:%vreg150 GPR64common:%vreg149
	    Successors according to CFG: BB#33

2784B	BB#33: derived from LLVM BB %if.end.51
	    Predecessors according to CFG: BB#31 BB#32
2800B		%vreg152<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg152
2816B		CBZX %vreg152, <BB#35>; GPR64:%vreg152
	    Successors according to CFG: BB#35 BB#34

2832B	BB#34: derived from LLVM BB %if.then.53
	    Predecessors according to CFG: BB#33
2848B		%vreg156<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32:%vreg156
2864B		%vreg155<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg155
2880B		STRWui %vreg156, %vreg155, 1274; mem:ST4[%lastErr54] GPR32:%vreg156 GPR64common:%vreg155
	    Successors according to CFG: BB#35

2896B	BB#35: derived from LLVM BB %if.end.55
	    Predecessors according to CFG: BB#33 BB#34
2912B		B <BB#71>
	    Successors according to CFG: BB#71

2928B	BB#36: derived from LLVM BB %if.end.56
	    Predecessors according to CFG: BB#29 BB#30
2944B		%vreg93<def> = MOVi32imm 5000; GPR32:%vreg93
2960B		%vreg96<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg96
2976B		%vreg95<def> = LDRWui %vreg96, 1262; mem:LD4[%avail_out58] GPR32:%vreg95 GPR64common:%vreg96
2992B		%WZR<def> = SUBSWrr %vreg95, %vreg93, %NZCV<imp-def>; GPR32:%vreg95,%vreg93
3008B		Bcc 2, <BB#45>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#45 BB#37

3024B	BB#37: derived from LLVM BB %if.then.60
	    Predecessors according to CFG: BB#36
3056B		%vreg121<def> = MOVi32imm 5000; GPR32:%vreg121
3072B		%vreg126<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg126
3088B		%vreg125<def> = LDRWui %vreg126, 1262; mem:LD4[%avail_out62] GPR32:%vreg125 GPR64common:%vreg126
3104B		%vreg123<def> = SUBWrr %vreg121, %vreg125; GPR32:%vreg123,%vreg121,%vreg125
3120B		STRWui %vreg123, <fi#7>, 0; mem:ST4[FixedStack7] GPR32:%vreg123
3136B		%vreg119<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg119
3152B		%vreg118<def> = ADDXri %vreg119, 8, 0; GPR64sp:%vreg118 GPR64common:%vreg119
3168B		%vreg115<def> = LDRSWui <fi#7>, 0; mem:LD4[FixedStack7] GPR64:%vreg115
3184B		%vreg111<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg111
3200B		%vreg110<def> = LDRXui %vreg111, 0; mem:LD8[%handle65] GPR64:%vreg110 GPR64common:%vreg111
3216B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3232B		%X0<def> = COPY %vreg118; GPR64sp:%vreg118
3248B		%X1<def> = MOVi64imm 1
3264B		%X2<def> = COPY %vreg115; GPR64:%vreg115
3280B		%X3<def> = COPY %vreg110; GPR64:%vreg110
3296B		BL <ga:@fwrite>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %X2<imp-use>, %X3<imp-use>, %X0<imp-def>
3312B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3328B		%vreg108<def> = COPY %X0; GPR64:%vreg108
3344B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3360B		STACKMAP 3, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, 0, <fi#9>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4)
3376B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3408B		STRWui %vreg108:sub_32, <fi#8>, 0; mem:ST4[FixedStack8] GPR64:%vreg108
3424B		%vreg100<def> = LDRWui <fi#7>, 0; mem:LD4[FixedStack7] GPR32:%vreg100
3440B		%vreg99<def> = LDRWui <fi#8>, 0; mem:LD4[FixedStack8] GPR32:%vreg99
3456B		%WZR<def> = SUBSWrr %vreg100, %vreg99, %NZCV<imp-def>; GPR32:%vreg100,%vreg99
3472B		Bcc 1, <BB#39>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#39 BB#38

3488B	BB#38: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#37
3504B		%vreg132<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg132
3520B		%vreg131<def> = LDRXui %vreg132, 0; mem:LD8[%handle70] GPR64:%vreg131 GPR64common:%vreg132
3536B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3552B		%X0<def> = COPY %vreg131; GPR64:%vreg131
3568B		BL <ga:@ferror>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
3584B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3600B		%vreg129<def> = COPY %W0; GPR32:%vreg129
3616B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3632B		STACKMAP 4, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, 0, <fi#9>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4)
3648B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3664B		CBZW %vreg129, <BB#44>; GPR32:%vreg129
	    Successors according to CFG: BB#44 BB#39

3680B	BB#39: derived from LLVM BB %if.then.73
	    Predecessors according to CFG: BB#37 BB#38
3696B		%vreg136<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg136
3712B		CBZX %vreg136, <BB#41>; GPR64:%vreg136
	    Successors according to CFG: BB#41 BB#40

3728B	BB#40: derived from LLVM BB %if.then.76
	    Predecessors according to CFG: BB#39
3744B		%vreg137<def> = MOVi32imm 4294967290; GPR32:%vreg137
3760B		%vreg139<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg139
3776B		STRWui %vreg137, %vreg139, 0; mem:ST4[%55] GPR32:%vreg137 GPR64common:%vreg139
	    Successors according to CFG: BB#41

3792B	BB#41: derived from LLVM BB %if.end.77
	    Predecessors according to CFG: BB#39 BB#40
3808B		%vreg141<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg141
3824B		CBZX %vreg141, <BB#43>; GPR64:%vreg141
	    Successors according to CFG: BB#43 BB#42

3840B	BB#42: derived from LLVM BB %if.then.80
	    Predecessors according to CFG: BB#41
3856B		%vreg142<def> = MOVi32imm 4294967290; GPR32:%vreg142
3872B		%vreg144<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg144
3888B		STRWui %vreg142, %vreg144, 1274; mem:ST4[%lastErr81] GPR32:%vreg142 GPR64common:%vreg144
	    Successors according to CFG: BB#43

3904B	BB#43: derived from LLVM BB %if.end.82
	    Predecessors according to CFG: BB#41 BB#42
3920B		B <BB#71>
	    Successors according to CFG: BB#71

3936B	BB#44: derived from LLVM BB %if.end.83
	    Predecessors according to CFG: BB#38
3952B		B <BB#45>
	    Successors according to CFG: BB#45

3968B	BB#45: derived from LLVM BB %if.end.84
	    Predecessors according to CFG: BB#36 BB#44
3984B		%vreg134<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32common:%vreg134
4000B		%WZR<def> = SUBSWri %vreg134, 4, 0, %NZCV<imp-def>; GPR32common:%vreg134
4016B		Bcc 1, <BB#47>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#47 BB#46

4032B	BB#46: derived from LLVM BB %if.then.87
	    Predecessors according to CFG: BB#45
4048B		B <BB#48>
	    Successors according to CFG: BB#48

4064B	BB#47: derived from LLVM BB %if.end.88
	    Predecessors according to CFG: BB#45
4080B		B <BB#29>
	    Successors according to CFG: BB#29

4096B	BB#48: derived from LLVM BB %while.end
	    Predecessors according to CFG: BB#46
4112B		B <BB#49>
	    Successors according to CFG: BB#49

4128B	BB#49: derived from LLVM BB %if.end.89
	    Predecessors according to CFG: BB#26 BB#27 BB#48
4144B		%vreg158<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg158
4160B		CBNZW %vreg158, <BB#58>; GPR32:%vreg158
	    Successors according to CFG: BB#58 BB#50

4176B	BB#50: derived from LLVM BB %land.lhs.true.91
	    Predecessors according to CFG: BB#49
4192B		%vreg164<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg164
4208B		%vreg163<def> = LDRXui %vreg164, 0; mem:LD8[%handle92] GPR64:%vreg163 GPR64common:%vreg164
4224B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4240B		%X0<def> = COPY %vreg163; GPR64:%vreg163
4256B		BL <ga:@ferror>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
4272B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4288B		%vreg161<def> = COPY %W0; GPR32:%vreg161
4304B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4320B		STACKMAP 5, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5]
4336B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4352B		CBNZW %vreg161, <BB#58>; GPR32:%vreg161
	    Successors according to CFG: BB#58 BB#51

4368B	BB#51: derived from LLVM BB %if.then.95
	    Predecessors according to CFG: BB#50
4384B		%vreg175<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg175
4400B		%vreg174<def> = LDRXui %vreg175, 0; mem:LD8[%handle96] GPR64:%vreg174 GPR64common:%vreg175
4416B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4432B		%X0<def> = COPY %vreg174; GPR64:%vreg174
4448B		BL <ga:@fflush>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
4464B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4480B		%vreg172<def,dead> = COPY %W0; GPR32all:%vreg172
4496B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4512B		STACKMAP 6, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5]
4528B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4544B		%vreg170<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg170
4560B		%vreg169<def> = LDRXui %vreg170, 0; mem:LD8[%handle98] GPR64:%vreg169 GPR64common:%vreg170
4576B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4592B		%X0<def> = COPY %vreg169; GPR64:%vreg169
4608B		BL <ga:@ferror>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
4624B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4640B		%vreg167<def> = COPY %W0; GPR32:%vreg167
4656B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4672B		STACKMAP 7, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5]
4688B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4704B		CBZW %vreg167, <BB#57>; GPR32:%vreg167
	    Successors according to CFG: BB#57 BB#52

4720B	BB#52: derived from LLVM BB %if.then.101
	    Predecessors according to CFG: BB#51
4736B		%vreg177<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg177
4752B		CBZX %vreg177, <BB#54>; GPR64:%vreg177
	    Successors according to CFG: BB#54 BB#53

4768B	BB#53: derived from LLVM BB %if.then.104
	    Predecessors according to CFG: BB#52
4784B		%vreg178<def> = MOVi32imm 4294967290; GPR32:%vreg178
4800B		%vreg180<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg180
4816B		STRWui %vreg178, %vreg180, 0; mem:ST4[%67] GPR32:%vreg178 GPR64common:%vreg180
	    Successors according to CFG: BB#54

4832B	BB#54: derived from LLVM BB %if.end.105
	    Predecessors according to CFG: BB#52 BB#53
4848B		%vreg182<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg182
4864B		CBZX %vreg182, <BB#56>; GPR64:%vreg182
	    Successors according to CFG: BB#56 BB#55

4880B	BB#55: derived from LLVM BB %if.then.108
	    Predecessors according to CFG: BB#54
4896B		%vreg183<def> = MOVi32imm 4294967290; GPR32:%vreg183
4912B		%vreg185<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg185
4928B		STRWui %vreg183, %vreg185, 1274; mem:ST4[%lastErr109] GPR32:%vreg183 GPR64common:%vreg185
	    Successors according to CFG: BB#56

4944B	BB#56: derived from LLVM BB %if.end.110
	    Predecessors according to CFG: BB#54 BB#55
4960B		B <BB#71>
	    Successors according to CFG: BB#71

4976B	BB#57: derived from LLVM BB %if.end.111
	    Predecessors according to CFG: BB#51
4992B		B <BB#58>
	    Successors according to CFG: BB#58

5008B	BB#58: derived from LLVM BB %if.end.112
	    Predecessors according to CFG: BB#49 BB#50 BB#57
5024B		%vreg187<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg187
5040B		CBZX %vreg187, <BB#60>; GPR64:%vreg187
	    Successors according to CFG: BB#60 BB#59

5056B	BB#59: derived from LLVM BB %if.then.115
	    Predecessors according to CFG: BB#58
5072B		%vreg193<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg193
5088B		%vreg192<def> = LDRWui %vreg193, 1257; mem:LD4[%total_in_lo32] GPR32:%vreg192 GPR64common:%vreg193
5104B		%vreg190<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg190
5120B		STRWui %vreg192, %vreg190, 0; mem:ST4[%73] GPR32:%vreg192 GPR64common:%vreg190
	    Successors according to CFG: BB#60

5136B	BB#60: derived from LLVM BB %if.end.117
	    Predecessors according to CFG: BB#58 BB#59
5152B		%vreg195<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64:%vreg195
5168B		CBZX %vreg195, <BB#62>; GPR64:%vreg195
	    Successors according to CFG: BB#62 BB#61

5184B	BB#61: derived from LLVM BB %if.then.120
	    Predecessors according to CFG: BB#60
5200B		%vreg201<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg201
5216B		%vreg200<def> = LDRWui %vreg201, 1258; mem:LD4[%total_in_hi32] GPR32:%vreg200 GPR64common:%vreg201
5232B		%vreg198<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg198
5248B		STRWui %vreg200, %vreg198, 0; mem:ST4[%77] GPR32:%vreg200 GPR64common:%vreg198
	    Successors according to CFG: BB#62

5264B	BB#62: derived from LLVM BB %if.end.122
	    Predecessors according to CFG: BB#60 BB#61
5280B		%vreg203<def> = LDRXui <fi#5>, 0; mem:LD8[FixedStack5] GPR64:%vreg203
5296B		CBZX %vreg203, <BB#64>; GPR64:%vreg203
	    Successors according to CFG: BB#64 BB#63

5312B	BB#63: derived from LLVM BB %if.then.125
	    Predecessors according to CFG: BB#62
5328B		%vreg209<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg209
5344B		%vreg208<def> = LDRWui %vreg209, 1263; mem:LD4[%total_out_lo32] GPR32:%vreg208 GPR64common:%vreg209
5360B		%vreg206<def> = LDRXui <fi#5>, 0; mem:LD8[FixedStack5] GPR64common:%vreg206
5376B		STRWui %vreg208, %vreg206, 0; mem:ST4[%81] GPR32:%vreg208 GPR64common:%vreg206
	    Successors according to CFG: BB#64

5392B	BB#64: derived from LLVM BB %if.end.127
	    Predecessors according to CFG: BB#62 BB#63
5408B		%vreg211<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64:%vreg211
5424B		CBZX %vreg211, <BB#66>; GPR64:%vreg211
	    Successors according to CFG: BB#66 BB#65

5440B	BB#65: derived from LLVM BB %if.then.130
	    Predecessors according to CFG: BB#64
5456B		%vreg217<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg217
5472B		%vreg216<def> = LDRWui %vreg217, 1264; mem:LD4[%total_out_hi32] GPR32:%vreg216 GPR64common:%vreg217
5488B		%vreg214<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg214
5504B		STRWui %vreg216, %vreg214, 0; mem:ST4[%85] GPR32:%vreg216 GPR64common:%vreg214
	    Successors according to CFG: BB#66

5520B	BB#66: derived from LLVM BB %if.end.132
	    Predecessors according to CFG: BB#64 BB#65
5536B		%vreg219<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg219
5552B		CBZX %vreg219, <BB#68>; GPR64:%vreg219
	    Successors according to CFG: BB#68 BB#67

5568B	BB#67: derived from LLVM BB %if.then.135
	    Predecessors according to CFG: BB#66
5584B		%vreg221<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg221
5600B		STRWui %WZR, %vreg221, 0; mem:ST4[%87] GPR64common:%vreg221
	    Successors according to CFG: BB#68

5616B	BB#68: derived from LLVM BB %if.end.136
	    Predecessors according to CFG: BB#66 BB#67
5632B		%vreg223<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg223
5648B		CBZX %vreg223, <BB#70>; GPR64:%vreg223
	    Successors according to CFG: BB#70 BB#69

5664B	BB#69: derived from LLVM BB %if.then.139
	    Predecessors according to CFG: BB#68
5680B		%vreg225<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg225
5696B		STRWui %WZR, %vreg225, 1274; mem:ST4[%lastErr140] GPR64common:%vreg225
	    Successors according to CFG: BB#70

5712B	BB#70: derived from LLVM BB %if.end.141
	    Predecessors according to CFG: BB#68 BB#69
5728B		%vreg235<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg235
5744B		%vreg233<def> = MOVi64imm 5016; GPR64:%vreg233
5760B		%vreg234<def> = ADDXrr %vreg235, %vreg233; GPR64:%vreg234,%vreg235,%vreg233
5776B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5792B		%X0<def> = COPY %vreg234; GPR64:%vreg234
5808B		BL <ga:@BZ2_bzCompressEnd>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
5824B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5840B		%vreg231<def,dead> = COPY %W0; GPR32all:%vreg231
5856B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5872B		STACKMAP 8, 0, 0, <fi#10>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack10]
5888B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5904B		%vreg228<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg228
5936B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5952B		%X0<def> = COPY %vreg228; GPR64:%vreg228
5968B		BL <ga:@free>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>
5984B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
6000B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
6016B		STACKMAP 9, 0, %LR<earlyclobber,imp-def,dead>, ...
6032B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#71

6048B	BB#71: derived from LLVM BB %return
	    Predecessors according to CFG: BB#11 BB#43 BB#35 BB#56 BB#70 BB#17 BB#5
6064B		%vreg254<def> = ADRP <ga:@BZ2_bzWriteClose64>[TF=1]; GPR64common:%vreg254
6080B		%vreg256<def> = ADDXri %vreg254, <ga:@BZ2_bzWriteClose64>[TF=34], 0; GPR64sp:%vreg256 GPR64common:%vreg254
6128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
6144B		%X0<def> = COPY %vreg256; GPR64sp:%vreg256
6160B		%X1<def> = COPY %vreg23; GPR64:%vreg23
6176B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
6192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
6208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
6224B		STACKMAP 10, 0, %LR<earlyclobber,imp-def,dead>, ...
6240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
6256B		RET_ReallyLR

# End machine code for function BZ2_bzWriteClose64.

handleMove 1040B -> 1064B: %vreg34<def> = MOVi32imm 4294967295; GPR32:%vreg34
     %vreg34:	[1040r,1072r:0)  0@1040r
        -->	[1064r,1072r:0)  0@1064r
handleMove 1152B -> 1176B: %vreg39<def> = MOVi32imm 4294967295; GPR32:%vreg39
     %vreg39:	[1152r,1184r:0)  0@1152r
        -->	[1176r,1184r:0)  0@1176r
handleMove 1488B -> 1512B: %vreg238<def> = MOVi32imm 4294967290; GPR32:%vreg238
     %vreg238:	[1488r,1520r:0)  0@1488r
        -->	[1512r,1520r:0)  0@1512r
handleMove 1600B -> 1624B: %vreg243<def> = MOVi32imm 4294967290; GPR32:%vreg243
     %vreg243:	[1600r,1632r:0)  0@1600r
        -->	[1624r,1632r:0)  0@1624r
handleMove 2416B -> 2440B: %X0<def> = COPY %vreg78; GPR64:%vreg78
     W0:	[0B,128r:0)[336r,368r:19)[1296r,1312r:18)[1312r,1344r:7)[2416r,2448r:17)[2448r,2480r:6)[3232r,3296r:16)[3296r,3328r:15)[3552r,3568r:14)[3568r,3600r:5)[4240r,4256r:13)[4256r,4288r:4)[4432r,4448r:11)[4448r,4480r:2)[4592r,4608r:12)[4608r,4640r:3)[5792r,5808r:9)[5808r,5840r:1)[5952r,5968r:10)[6144r,6176r:8)  0@0B-phi 1@5808r 2@4448r 3@4608r 4@4256r 5@3568r 6@2448r 7@1312r 8@6144r 9@5792r 10@5952r 11@4432r 12@4592r 13@4240r 14@3552r 15@3296r 16@3232r 17@2416r 18@1296r 19@336r
        -->	[0B,128r:0)[336r,368r:19)[1296r,1312r:18)[1312r,1344r:7)[2440r,2448r:17)[2448r,2480r:6)[3232r,3296r:16)[3296r,3328r:15)[3552r,3568r:14)[3568r,3600r:5)[4240r,4256r:13)[4256r,4288r:4)[4432r,4448r:11)[4448r,4480r:2)[4592r,4608r:12)[4608r,4640r:3)[5792r,5808r:9)[5808r,5840r:1)[5952r,5968r:10)[6144r,6176r:8)  0@0B-phi 1@5808r 2@4448r 3@4608r 4@4256r 5@3568r 6@2448r 7@1312r 8@6144r 9@5792r 10@5952r 11@4432r 12@4592r 13@4240r 14@3552r 15@3296r 16@3232r 17@2440r 18@1296r 19@336r
     %vreg78:	[2384r,2416r:0)  0@2384r
        -->	[2384r,2440r:0)  0@2384r
handleMove 2304B -> 2328B: %vreg85<def> = ADDXri %vreg86, 8, 0; GPR64common:%vreg85,%vreg86
     %vreg85:	[2304r,2336r:0)  0@2304r
        -->	[2328r,2336r:0)  0@2328r
     %vreg86:	[2288r,2304r:0)  0@2288r
        -->	[2288r,2328r:0)  0@2288r
handleMove 2240B -> 2264B: %vreg87<def> = MOVi32imm 5000; GPR32:%vreg87
     %vreg87:	[2240r,2272r:0)  0@2240r
        -->	[2264r,2272r:0)  0@2264r
handleMove 2944B -> 2984B: %vreg93<def> = MOVi32imm 5000; GPR32:%vreg93
     %vreg93:	[2944r,2992r:0)  0@2944r
        -->	[2984r,2992r:0)  0@2984r
handleMove 3248B -> 3224B: %X1<def> = MOVi64imm 1
     W1:	[0B,112r:0)[352r,368r:4)[2432r,2448r:1)[3248r,3296r:3)[6160r,6176r:2)  0@0B-phi 1@2432r 2@6160r 3@3248r 4@352r
        -->	[0B,112r:0)[352r,368r:4)[2432r,2448r:1)[3224r,3296r:3)[6160r,6176r:2)  0@0B-phi 1@2432r 2@6160r 3@3224r 4@352r
handleMove 3152B -> 3208B: %vreg118<def> = ADDXri %vreg119, 8, 0; GPR64sp:%vreg118 GPR64common:%vreg119
     %vreg118:	[3152r,3232r:0)  0@3152r
        -->	[3208r,3232r:0)  0@3208r
     %vreg119:	[3136r,3152r:0)  0@3136r
        -->	[3136r,3208r:0)  0@3136r
handleMove 3168B -> 3192B: %vreg115<def> = LDRSWui <fi#7>, 0; mem:LD4[FixedStack7] GPR64:%vreg115
     %vreg115:	[3168r,3264r:0)  0@3168r
        -->	[3192r,3264r:0)  0@3192r
handleMove 3136B -> 3188B: %vreg119<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg119
     %vreg119:	[3136r,3208r:0)  0@3136r
        -->	[3188r,3208r:0)  0@3188r
handleMove 3056B -> 3096B: %vreg121<def> = MOVi32imm 5000; GPR32:%vreg121
     %vreg121:	[3056r,3104r:0)  0@3056r
        -->	[3096r,3104r:0)  0@3096r
handleMove 3744B -> 3768B: %vreg137<def> = MOVi32imm 4294967290; GPR32:%vreg137
     %vreg137:	[3744r,3776r:0)  0@3744r
        -->	[3768r,3776r:0)  0@3768r
handleMove 3856B -> 3880B: %vreg142<def> = MOVi32imm 4294967290; GPR32:%vreg142
     %vreg142:	[3856r,3888r:0)  0@3856r
        -->	[3880r,3888r:0)  0@3880r
handleMove 4784B -> 4808B: %vreg178<def> = MOVi32imm 4294967290; GPR32:%vreg178
     %vreg178:	[4784r,4816r:0)  0@4784r
        -->	[4808r,4816r:0)  0@4808r
handleMove 4896B -> 4920B: %vreg183<def> = MOVi32imm 4294967290; GPR32:%vreg183
     %vreg183:	[4896r,4928r:0)  0@4896r
        -->	[4920r,4928r:0)  0@4920r
********** GREEDY REGISTER ALLOCATION **********
********** Function: BZ2_bzWriteClose64
********** INTERVALS **********
W30 [0B,16r:0)[368r,368d:22)[416e,416d:9)[1312r,1312d:21)[1376e,1376d:8)[2448r,2448d:20)[2512e,2512d:7)[3296r,3296d:19)[3360e,3360d:6)[3568r,3568d:18)[3632e,3632d:5)[4256r,4256d:17)[4320e,4320d:4)[4448r,4448d:15)[4512e,4512d:3)[4608r,4608d:16)[4672e,4672d:2)[5808r,5808d:12)[5872e,5872d:1)[5968r,5968d:13)[6016e,6016d:14)[6176r,6176d:10)[6224e,6224d:11)  0@0B-phi 1@5872e 2@4672e 3@4512e 4@4320e 5@3632e 6@3360e 7@2512e 8@1376e 9@416e 10@6176r 11@6224e 12@5808r 13@5968r 14@6016e 15@4448r 16@4608r 17@4256r 18@3568r 19@3296r 20@2448r 21@1312r 22@368r
W0 [0B,128r:0)[336r,368r:19)[1296r,1312r:18)[1312r,1344r:7)[2440r,2448r:17)[2448r,2480r:6)[3232r,3296r:16)[3296r,3328r:15)[3552r,3568r:14)[3568r,3600r:5)[4240r,4256r:13)[4256r,4288r:4)[4432r,4448r:11)[4448r,4480r:2)[4592r,4608r:12)[4608r,4640r:3)[5792r,5808r:9)[5808r,5840r:1)[5952r,5968r:10)[6144r,6176r:8)  0@0B-phi 1@5808r 2@4448r 3@4608r 4@4256r 5@3568r 6@2448r 7@1312r 8@6144r 9@5792r 10@5952r 11@4432r 12@4592r 13@4240r 14@3552r 15@3296r 16@3232r 17@2440r 18@1296r 19@336r
W1 [0B,112r:0)[352r,368r:4)[2432r,2448r:1)[3224r,3296r:3)[6160r,6176r:2)  0@0B-phi 1@2432r 2@6160r 3@3224r 4@352r
W2 [0B,96r:0)[3264r,3296r:1)  0@0B-phi 1@3264r
W3 [0B,80r:0)[3280r,3296r:1)  0@0B-phi 1@3280r
W4 [0B,64r:0)  0@0B-phi
W5 [0B,48r:0)  0@0B-phi
W6 [0B,32r:0)  0@0B-phi
%vreg1 [128r,448r:0)  0@128r
%vreg3 [112r,464r:0)  0@112r
%vreg5 [96r,480r:0)  0@96r
%vreg7 [80r,496r:0)  0@80r
%vreg9 [64r,512r:0)  0@64r
%vreg11 [48r,528r:0)  0@48r
%vreg13 [32r,544r:0)  0@32r
%vreg15 [608r,624r:0)  0@608r
%vreg18 [560r,592r:0)  0@560r
%vreg20 [256r,272r:0)  0@256r
%vreg22 [272r,336r:0)  0@272r
%vreg23 [16r,6160r:0)  0@16r
%vreg26 [944r,960r:0)  0@944r
%vreg28 [896r,912r:0)  0@896r
%vreg29 [912r,928r:0)  0@912r
%vreg30 [928r,944r:0)  0@928r
%vreg31 [880r,912r:0)  0@880r
%vreg33 [992r,1008r:0)  0@992r
%vreg34 [1064r,1072r:0)  0@1064r
%vreg36 [1056r,1072r:0)  0@1056r
%vreg38 [1104r,1120r:0)  0@1104r
%vreg39 [1176r,1184r:0)  0@1176r
%vreg41 [1168r,1184r:0)  0@1168r
%vreg44 [1344r,1408r:0)  0@1344r
%vreg46 [1264r,1296r:0)  0@1264r
%vreg47 [1248r,1264r:0)  0@1248r
%vreg49 [1696r,1712r:0)  0@1696r
%vreg51 [1744r,1760r:0)  0@1744r
%vreg53 [1792r,1808r:0)  0@1792r
%vreg55 [1840r,1856r:0)  0@1840r
%vreg57 [1888r,1904r:0)  0@1888r
%vreg59 [1936r,1952r:0)  0@1936r
%vreg61 [1984r,2000r:0)  0@1984r
%vreg63 [2032r,2048r:0)  0@2032r
%vreg65 [2080r,2096r:0)  0@2080r
%vreg68 [2144r,2160r:0)  0@2144r
%vreg69 [2128r,2144r:0)  0@2128r
%vreg71 [2560r,2576r:0)  0@2560r
%vreg75 [2480r,2544r:0)  0@2480r
%vreg77 [2368r,2384r:0)  0@2368r
%vreg78 [2384r,2440r:0)  0@2384r
%vreg79 [2352r,2384r:0)  0@2352r
%vreg82 [2320r,2336r:0)  0@2320r
%vreg85 [2328r,2336r:0)  0@2328r
%vreg86 [2288r,2328r:0)  0@2288r
%vreg87 [2264r,2272r:0)  0@2264r
%vreg89 [2256r,2272r:0)  0@2256r
%vreg91 [2624r,2640r:0)  0@2624r
%vreg93 [2984r,2992r:0)  0@2984r
%vreg95 [2976r,2992r:0)  0@2976r
%vreg96 [2960r,2976r:0)  0@2960r
%vreg99 [3440r,3456r:0)  0@3440r
%vreg100 [3424r,3456r:0)  0@3424r
%vreg108 [3328r,3408r:0)  0@3328r
%vreg110 [3200r,3280r:0)  0@3200r
%vreg111 [3184r,3200r:0)  0@3184r
%vreg115 [3192r,3264r:0)  0@3192r
%vreg118 [3208r,3232r:0)  0@3208r
%vreg119 [3188r,3208r:0)  0@3188r
%vreg121 [3096r,3104r:0)  0@3096r
%vreg123 [3104r,3120r:0)  0@3104r
%vreg125 [3088r,3104r:0)  0@3088r
%vreg126 [3072r,3088r:0)  0@3072r
%vreg129 [3600r,3664r:0)  0@3600r
%vreg131 [3520r,3552r:0)  0@3520r
%vreg132 [3504r,3520r:0)  0@3504r
%vreg134 [3984r,4000r:0)  0@3984r
%vreg136 [3696r,3712r:0)  0@3696r
%vreg137 [3768r,3776r:0)  0@3768r
%vreg139 [3760r,3776r:0)  0@3760r
%vreg141 [3808r,3824r:0)  0@3808r
%vreg142 [3880r,3888r:0)  0@3880r
%vreg144 [3872r,3888r:0)  0@3872r
%vreg146 [2688r,2704r:0)  0@2688r
%vreg149 [2752r,2768r:0)  0@2752r
%vreg150 [2736r,2768r:0)  0@2736r
%vreg152 [2800r,2816r:0)  0@2800r
%vreg155 [2864r,2880r:0)  0@2864r
%vreg156 [2848r,2880r:0)  0@2848r
%vreg158 [4144r,4160r:0)  0@4144r
%vreg161 [4288r,4352r:0)  0@4288r
%vreg163 [4208r,4240r:0)  0@4208r
%vreg164 [4192r,4208r:0)  0@4192r
%vreg167 [4640r,4704r:0)  0@4640r
%vreg169 [4560r,4592r:0)  0@4560r
%vreg170 [4544r,4560r:0)  0@4544r
%vreg172 [4480r,4480d:0)  0@4480r
%vreg174 [4400r,4432r:0)  0@4400r
%vreg175 [4384r,4400r:0)  0@4384r
%vreg177 [4736r,4752r:0)  0@4736r
%vreg178 [4808r,4816r:0)  0@4808r
%vreg180 [4800r,4816r:0)  0@4800r
%vreg182 [4848r,4864r:0)  0@4848r
%vreg183 [4920r,4928r:0)  0@4920r
%vreg185 [4912r,4928r:0)  0@4912r
%vreg187 [5024r,5040r:0)  0@5024r
%vreg190 [5104r,5120r:0)  0@5104r
%vreg192 [5088r,5120r:0)  0@5088r
%vreg193 [5072r,5088r:0)  0@5072r
%vreg195 [5152r,5168r:0)  0@5152r
%vreg198 [5232r,5248r:0)  0@5232r
%vreg200 [5216r,5248r:0)  0@5216r
%vreg201 [5200r,5216r:0)  0@5200r
%vreg203 [5280r,5296r:0)  0@5280r
%vreg206 [5360r,5376r:0)  0@5360r
%vreg208 [5344r,5376r:0)  0@5344r
%vreg209 [5328r,5344r:0)  0@5328r
%vreg211 [5408r,5424r:0)  0@5408r
%vreg214 [5488r,5504r:0)  0@5488r
%vreg216 [5472r,5504r:0)  0@5472r
%vreg217 [5456r,5472r:0)  0@5456r
%vreg219 [5536r,5552r:0)  0@5536r
%vreg221 [5584r,5600r:0)  0@5584r
%vreg223 [5632r,5648r:0)  0@5632r
%vreg225 [5680r,5696r:0)  0@5680r
%vreg228 [5904r,5952r:0)  0@5904r
%vreg231 [5840r,5840d:0)  0@5840r
%vreg233 [5744r,5760r:0)  0@5744r
%vreg234 [5760r,5792r:0)  0@5760r
%vreg235 [5728r,5760r:0)  0@5728r
%vreg237 [1440r,1456r:0)  0@1440r
%vreg238 [1512r,1520r:0)  0@1512r
%vreg240 [1504r,1520r:0)  0@1504r
%vreg242 [1552r,1568r:0)  0@1552r
%vreg243 [1624r,1632r:0)  0@1624r
%vreg245 [1616r,1632r:0)  0@1616r
%vreg247 [656r,672r:0)  0@656r
%vreg249 [704r,720r:0)  0@704r
%vreg251 [752r,768r:0)  0@752r
%vreg253 [800r,816r:0)  0@800r
%vreg254 [6064r,6080r:0)  0@6064r
%vreg256 [6080r,6144r:0)  0@6080r
RegMasks: 368r 1312r 2448r 3296r 3568r 4256r 4448r 4608r 5808r 5968r 6176r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzWriteClose64: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=4, align=4, at location [SP]
  fi#3: size=8, align=8, at location [SP]
  fi#4: size=8, align=8, at location [SP]
  fi#5: size=8, align=8, at location [SP]
  fi#6: size=8, align=8, at location [SP]
  fi#7: size=4, align=4, at location [SP]
  fi#8: size=4, align=4, at location [SP]
  fi#9: size=4, align=4, at location [SP]
  fi#10: size=8, align=8, at location [SP]
Function Live Ins: %X0 in %vreg0, %X1 in %vreg2, %W2 in %vreg4, %X3 in %vreg6, %X4 in %vreg8, %X5 in %vreg10, %X6 in %vreg12, %LR in %vreg24

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %X1 %W2 %X3 %X4 %X5 %X6 %LR
16B		%vreg23<def> = COPY %LR; GPR64:%vreg23
32B		%vreg13<def> = COPY %X6; GPR64:%vreg13
48B		%vreg11<def> = COPY %X5; GPR64:%vreg11
64B		%vreg9<def> = COPY %X4; GPR64:%vreg9
80B		%vreg7<def> = COPY %X3; GPR64:%vreg7
96B		%vreg5<def> = COPY %W2; GPR32:%vreg5
112B		%vreg3<def> = COPY %X1; GPR64:%vreg3
128B		%vreg1<def> = COPY %X0; GPR64:%vreg1
256B		%vreg20<def> = ADRP <ga:@BZ2_bzWriteClose64>[TF=1]; GPR64common:%vreg20
272B		%vreg22<def> = ADDXri %vreg20, <ga:@BZ2_bzWriteClose64>[TF=34], 0; GPR64sp:%vreg22 GPR64common:%vreg20
320B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
336B		%X0<def> = COPY %vreg22; GPR64sp:%vreg22
352B		%X1<def> = COPY %vreg23; GPR64:%vreg23
368B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
384B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
400B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
416B		STACKMAP 0, 0, %vreg5, 0, <fi#2>, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, %vreg9, 0, <fi#4>, 0, %vreg7, 0, <fi#3>, 0, %vreg13, 0, <fi#6>, 0, %vreg11, 0, <fi#5>, 0, 0, <fi#9>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4) GPR32:%vreg5 GPR64:%vreg3,%vreg1,%vreg9,%vreg7,%vreg13,%vreg11
432B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
448B		STRXui %vreg1, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg1
464B		STRXui %vreg3, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg3
480B		STRWui %vreg5, <fi#2>, 0; mem:ST4[FixedStack2] GPR32:%vreg5
496B		STRXui %vreg7, <fi#3>, 0; mem:ST8[FixedStack3] GPR64:%vreg7
512B		STRXui %vreg9, <fi#4>, 0; mem:ST8[FixedStack4] GPR64:%vreg9
528B		STRXui %vreg11, <fi#5>, 0; mem:ST8[FixedStack5] GPR64:%vreg11
544B		STRXui %vreg13, <fi#6>, 0; mem:ST8[FixedStack6] GPR64:%vreg13
560B		%vreg18<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg18
592B		STRXui %vreg18, <fi#10>, 0; mem:ST8[FixedStack10] GPR64:%vreg18
608B		%vreg15<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg15
624B		CBNZX %vreg15, <BB#6>; GPR64:%vreg15
	    Successors according to CFG: BB#6 BB#1

640B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
656B		%vreg247<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg247
672B		CBZX %vreg247, <BB#3>; GPR64:%vreg247
	    Successors according to CFG: BB#3 BB#2

688B	BB#2: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#1
704B		%vreg249<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg249
720B		STRWui %WZR, %vreg249, 0; mem:ST4[%4] GPR64common:%vreg249
	    Successors according to CFG: BB#3

736B	BB#3: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#1 BB#2
752B		%vreg251<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg251
768B		CBZX %vreg251, <BB#5>; GPR64:%vreg251
	    Successors according to CFG: BB#5 BB#4

784B	BB#4: derived from LLVM BB %if.then.4
	    Predecessors according to CFG: BB#3
800B		%vreg253<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg253
816B		STRWui %WZR, %vreg253, 1274; mem:ST4[%lastErr] GPR64common:%vreg253
	    Successors according to CFG: BB#5

832B	BB#5: derived from LLVM BB %if.end.5
	    Predecessors according to CFG: BB#3 BB#4
848B		B <BB#71>
	    Successors according to CFG: BB#71

864B	BB#6: derived from LLVM BB %if.end.6
	    Predecessors according to CFG: BB#0
880B		%vreg31<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg31
896B		%vreg28<def> = MOVi64imm 5012; GPR64:%vreg28
912B		%vreg29<def> = ADDXrr %vreg31, %vreg28; GPR64common:%vreg29 GPR64:%vreg31,%vreg28
928B		%vreg30<def> = LDRBBui %vreg29, 0; mem:LD1[%writing] GPR32:%vreg30 GPR64common:%vreg29
944B		%vreg26<def> = UBFMWri %vreg30, 0, 7; GPR32:%vreg26,%vreg30
960B		CBNZW %vreg26, <BB#12>; GPR32:%vreg26
	    Successors according to CFG: BB#12 BB#7

976B	BB#7: derived from LLVM BB %if.then.7
	    Predecessors according to CFG: BB#6
992B		%vreg33<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg33
1008B		CBZX %vreg33, <BB#9>; GPR64:%vreg33
	    Successors according to CFG: BB#9 BB#8

1024B	BB#8: derived from LLVM BB %if.then.9
	    Predecessors according to CFG: BB#7
1056B		%vreg36<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg36
1064B		%vreg34<def> = MOVi32imm 4294967295; GPR32:%vreg34
1072B		STRWui %vreg34, %vreg36, 0; mem:ST4[%10] GPR32:%vreg34 GPR64common:%vreg36
	    Successors according to CFG: BB#9

1088B	BB#9: derived from LLVM BB %if.end.10
	    Predecessors according to CFG: BB#7 BB#8
1104B		%vreg38<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg38
1120B		CBZX %vreg38, <BB#11>; GPR64:%vreg38
	    Successors according to CFG: BB#11 BB#10

1136B	BB#10: derived from LLVM BB %if.then.12
	    Predecessors according to CFG: BB#9
1168B		%vreg41<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg41
1176B		%vreg39<def> = MOVi32imm 4294967295; GPR32:%vreg39
1184B		STRWui %vreg39, %vreg41, 1274; mem:ST4[%lastErr13] GPR32:%vreg39 GPR64common:%vreg41
	    Successors according to CFG: BB#11

1200B	BB#11: derived from LLVM BB %if.end.14
	    Predecessors according to CFG: BB#9 BB#10
1216B		B <BB#71>
	    Successors according to CFG: BB#71

1232B	BB#12: derived from LLVM BB %if.end.15
	    Predecessors according to CFG: BB#6
1248B		%vreg47<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg47
1264B		%vreg46<def> = LDRXui %vreg47, 0; mem:LD8[%handle] GPR64:%vreg46 GPR64common:%vreg47
1280B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1296B		%X0<def> = COPY %vreg46; GPR64:%vreg46
1312B		BL <ga:@ferror>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
1328B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1344B		%vreg44<def> = COPY %W0; GPR32:%vreg44
1360B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1376B		STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, 0, <fi#9>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4)
1392B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1408B		CBZW %vreg44, <BB#18>; GPR32:%vreg44
	    Successors according to CFG: BB#18 BB#13

1424B	BB#13: derived from LLVM BB %if.then.17
	    Predecessors according to CFG: BB#12
1440B		%vreg237<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg237
1456B		CBZX %vreg237, <BB#15>; GPR64:%vreg237
	    Successors according to CFG: BB#15 BB#14

1472B	BB#14: derived from LLVM BB %if.then.19
	    Predecessors according to CFG: BB#13
1504B		%vreg240<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg240
1512B		%vreg238<def> = MOVi32imm 4294967290; GPR32:%vreg238
1520B		STRWui %vreg238, %vreg240, 0; mem:ST4[%16] GPR32:%vreg238 GPR64common:%vreg240
	    Successors according to CFG: BB#15

1536B	BB#15: derived from LLVM BB %if.end.20
	    Predecessors according to CFG: BB#13 BB#14
1552B		%vreg242<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg242
1568B		CBZX %vreg242, <BB#17>; GPR64:%vreg242
	    Successors according to CFG: BB#17 BB#16

1584B	BB#16: derived from LLVM BB %if.then.22
	    Predecessors according to CFG: BB#15
1616B		%vreg245<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg245
1624B		%vreg243<def> = MOVi32imm 4294967290; GPR32:%vreg243
1632B		STRWui %vreg243, %vreg245, 1274; mem:ST4[%lastErr23] GPR32:%vreg243 GPR64common:%vreg245
	    Successors according to CFG: BB#17

1648B	BB#17: derived from LLVM BB %if.end.24
	    Predecessors according to CFG: BB#15 BB#16
1664B		B <BB#71>
	    Successors according to CFG: BB#71

1680B	BB#18: derived from LLVM BB %if.end.25
	    Predecessors according to CFG: BB#12
1696B		%vreg49<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg49
1712B		CBZX %vreg49, <BB#20>; GPR64:%vreg49
	    Successors according to CFG: BB#20 BB#19

1728B	BB#19: derived from LLVM BB %if.then.27
	    Predecessors according to CFG: BB#18
1744B		%vreg51<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg51
1760B		STRWui %WZR, %vreg51, 0; mem:ST4[%20] GPR64common:%vreg51
	    Successors according to CFG: BB#20

1776B	BB#20: derived from LLVM BB %if.end.28
	    Predecessors according to CFG: BB#18 BB#19
1792B		%vreg53<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64:%vreg53
1808B		CBZX %vreg53, <BB#22>; GPR64:%vreg53
	    Successors according to CFG: BB#22 BB#21

1824B	BB#21: derived from LLVM BB %if.then.30
	    Predecessors according to CFG: BB#20
1840B		%vreg55<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg55
1856B		STRWui %WZR, %vreg55, 0; mem:ST4[%22] GPR64common:%vreg55
	    Successors according to CFG: BB#22

1872B	BB#22: derived from LLVM BB %if.end.31
	    Predecessors according to CFG: BB#20 BB#21
1888B		%vreg57<def> = LDRXui <fi#5>, 0; mem:LD8[FixedStack5] GPR64:%vreg57
1904B		CBZX %vreg57, <BB#24>; GPR64:%vreg57
	    Successors according to CFG: BB#24 BB#23

1920B	BB#23: derived from LLVM BB %if.then.33
	    Predecessors according to CFG: BB#22
1936B		%vreg59<def> = LDRXui <fi#5>, 0; mem:LD8[FixedStack5] GPR64common:%vreg59
1952B		STRWui %WZR, %vreg59, 0; mem:ST4[%24] GPR64common:%vreg59
	    Successors according to CFG: BB#24

1968B	BB#24: derived from LLVM BB %if.end.34
	    Predecessors according to CFG: BB#22 BB#23
1984B		%vreg61<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64:%vreg61
2000B		CBZX %vreg61, <BB#26>; GPR64:%vreg61
	    Successors according to CFG: BB#26 BB#25

2016B	BB#25: derived from LLVM BB %if.then.36
	    Predecessors according to CFG: BB#24
2032B		%vreg63<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg63
2048B		STRWui %WZR, %vreg63, 0; mem:ST4[%26] GPR64common:%vreg63
	    Successors according to CFG: BB#26

2064B	BB#26: derived from LLVM BB %if.end.37
	    Predecessors according to CFG: BB#24 BB#25
2080B		%vreg65<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg65
2096B		CBNZW %vreg65, <BB#49>; GPR32:%vreg65
	    Successors according to CFG: BB#49 BB#27

2112B	BB#27: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#26
2128B		%vreg69<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg69
2144B		%vreg68<def> = LDRWui %vreg69, 1274; mem:LD4[%lastErr39] GPR32:%vreg68 GPR64common:%vreg69
2160B		CBNZW %vreg68, <BB#49>; GPR32:%vreg68
	    Successors according to CFG: BB#49 BB#28

2176B	BB#28: derived from LLVM BB %if.then.41
	    Predecessors according to CFG: BB#27
2192B		B <BB#29>
	    Successors according to CFG: BB#29

2208B	BB#29: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#28 BB#47
2256B		%vreg89<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg89
2264B		%vreg87<def> = MOVi32imm 5000; GPR32:%vreg87
2272B		STRWui %vreg87, %vreg89, 1262; mem:ST4[%avail_out] GPR32:%vreg87 GPR64common:%vreg89
2288B		%vreg86<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg86
2320B		%vreg82<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg82
2328B		%vreg85<def> = ADDXri %vreg86, 8, 0; GPR64common:%vreg85,%vreg86
2336B		STRXui %vreg85, %vreg82, 630; mem:ST8[%next_out] GPR64common:%vreg85,%vreg82
2352B		%vreg79<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg79
2368B		%vreg77<def> = MOVi64imm 5016; GPR64:%vreg77
2384B		%vreg78<def> = ADDXrr %vreg79, %vreg77; GPR64:%vreg78,%vreg79,%vreg77
2400B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2432B		%W1<def> = MOVi32imm 2
2440B		%X0<def> = COPY %vreg78; GPR64:%vreg78
2448B		BL <ga:@BZ2_bzCompress>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %W0<imp-def>
2464B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2480B		%vreg75<def> = COPY %W0; GPR32:%vreg75
2496B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2512B		STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, 0, <fi#9>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4)
2528B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2544B		STRWui %vreg75, <fi#9>, 0; mem:ST4[FixedStack9] GPR32:%vreg75
2560B		%vreg71<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32common:%vreg71
2576B		%WZR<def> = SUBSWri %vreg71, 3, 0, %NZCV<imp-def>; GPR32common:%vreg71
2592B		Bcc 0, <BB#36>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#36 BB#30

2608B	BB#30: derived from LLVM BB %land.lhs.true.46
	    Predecessors according to CFG: BB#29
2624B		%vreg91<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32common:%vreg91
2640B		%WZR<def> = SUBSWri %vreg91, 4, 0, %NZCV<imp-def>; GPR32common:%vreg91
2656B		Bcc 0, <BB#36>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#36 BB#31

2672B	BB#31: derived from LLVM BB %if.then.48
	    Predecessors according to CFG: BB#30
2688B		%vreg146<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg146
2704B		CBZX %vreg146, <BB#33>; GPR64:%vreg146
	    Successors according to CFG: BB#33 BB#32

2720B	BB#32: derived from LLVM BB %if.then.50
	    Predecessors according to CFG: BB#31
2736B		%vreg150<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32:%vreg150
2752B		%vreg149<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg149
2768B		STRWui %vreg150, %vreg149, 0; mem:ST4[%38] GPR32:%vreg150 GPR64common:%vreg149
	    Successors according to CFG: BB#33

2784B	BB#33: derived from LLVM BB %if.end.51
	    Predecessors according to CFG: BB#31 BB#32
2800B		%vreg152<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg152
2816B		CBZX %vreg152, <BB#35>; GPR64:%vreg152
	    Successors according to CFG: BB#35 BB#34

2832B	BB#34: derived from LLVM BB %if.then.53
	    Predecessors according to CFG: BB#33
2848B		%vreg156<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32:%vreg156
2864B		%vreg155<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg155
2880B		STRWui %vreg156, %vreg155, 1274; mem:ST4[%lastErr54] GPR32:%vreg156 GPR64common:%vreg155
	    Successors according to CFG: BB#35

2896B	BB#35: derived from LLVM BB %if.end.55
	    Predecessors according to CFG: BB#33 BB#34
2912B		B <BB#71>
	    Successors according to CFG: BB#71

2928B	BB#36: derived from LLVM BB %if.end.56
	    Predecessors according to CFG: BB#29 BB#30
2960B		%vreg96<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg96
2976B		%vreg95<def> = LDRWui %vreg96, 1262; mem:LD4[%avail_out58] GPR32:%vreg95 GPR64common:%vreg96
2984B		%vreg93<def> = MOVi32imm 5000; GPR32:%vreg93
2992B		%WZR<def> = SUBSWrr %vreg95, %vreg93, %NZCV<imp-def>; GPR32:%vreg95,%vreg93
3008B		Bcc 2, <BB#45>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#45 BB#37

3024B	BB#37: derived from LLVM BB %if.then.60
	    Predecessors according to CFG: BB#36
3072B		%vreg126<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg126
3088B		%vreg125<def> = LDRWui %vreg126, 1262; mem:LD4[%avail_out62] GPR32:%vreg125 GPR64common:%vreg126
3096B		%vreg121<def> = MOVi32imm 5000; GPR32:%vreg121
3104B		%vreg123<def> = SUBWrr %vreg121, %vreg125; GPR32:%vreg123,%vreg121,%vreg125
3120B		STRWui %vreg123, <fi#7>, 0; mem:ST4[FixedStack7] GPR32:%vreg123
3184B		%vreg111<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg111
3188B		%vreg119<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg119
3192B		%vreg115<def> = LDRSWui <fi#7>, 0; mem:LD4[FixedStack7] GPR64:%vreg115
3200B		%vreg110<def> = LDRXui %vreg111, 0; mem:LD8[%handle65] GPR64:%vreg110 GPR64common:%vreg111
3208B		%vreg118<def> = ADDXri %vreg119, 8, 0; GPR64sp:%vreg118 GPR64common:%vreg119
3216B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3224B		%X1<def> = MOVi64imm 1
3232B		%X0<def> = COPY %vreg118; GPR64sp:%vreg118
3264B		%X2<def> = COPY %vreg115; GPR64:%vreg115
3280B		%X3<def> = COPY %vreg110; GPR64:%vreg110
3296B		BL <ga:@fwrite>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %X2<imp-use>, %X3<imp-use>, %X0<imp-def>
3312B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3328B		%vreg108<def> = COPY %X0; GPR64:%vreg108
3344B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3360B		STACKMAP 3, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, 0, <fi#9>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4)
3376B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3408B		STRWui %vreg108:sub_32, <fi#8>, 0; mem:ST4[FixedStack8] GPR64:%vreg108
3424B		%vreg100<def> = LDRWui <fi#7>, 0; mem:LD4[FixedStack7] GPR32:%vreg100
3440B		%vreg99<def> = LDRWui <fi#8>, 0; mem:LD4[FixedStack8] GPR32:%vreg99
3456B		%WZR<def> = SUBSWrr %vreg100, %vreg99, %NZCV<imp-def>; GPR32:%vreg100,%vreg99
3472B		Bcc 1, <BB#39>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#39 BB#38

3488B	BB#38: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#37
3504B		%vreg132<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg132
3520B		%vreg131<def> = LDRXui %vreg132, 0; mem:LD8[%handle70] GPR64:%vreg131 GPR64common:%vreg132
3536B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3552B		%X0<def> = COPY %vreg131; GPR64:%vreg131
3568B		BL <ga:@ferror>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
3584B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3600B		%vreg129<def> = COPY %W0; GPR32:%vreg129
3616B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3632B		STACKMAP 4, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, 0, <fi#9>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4)
3648B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3664B		CBZW %vreg129, <BB#44>; GPR32:%vreg129
	    Successors according to CFG: BB#44 BB#39

3680B	BB#39: derived from LLVM BB %if.then.73
	    Predecessors according to CFG: BB#37 BB#38
3696B		%vreg136<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg136
3712B		CBZX %vreg136, <BB#41>; GPR64:%vreg136
	    Successors according to CFG: BB#41 BB#40

3728B	BB#40: derived from LLVM BB %if.then.76
	    Predecessors according to CFG: BB#39
3760B		%vreg139<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg139
3768B		%vreg137<def> = MOVi32imm 4294967290; GPR32:%vreg137
3776B		STRWui %vreg137, %vreg139, 0; mem:ST4[%55] GPR32:%vreg137 GPR64common:%vreg139
	    Successors according to CFG: BB#41

3792B	BB#41: derived from LLVM BB %if.end.77
	    Predecessors according to CFG: BB#39 BB#40
3808B		%vreg141<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg141
3824B		CBZX %vreg141, <BB#43>; GPR64:%vreg141
	    Successors according to CFG: BB#43 BB#42

3840B	BB#42: derived from LLVM BB %if.then.80
	    Predecessors according to CFG: BB#41
3872B		%vreg144<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg144
3880B		%vreg142<def> = MOVi32imm 4294967290; GPR32:%vreg142
3888B		STRWui %vreg142, %vreg144, 1274; mem:ST4[%lastErr81] GPR32:%vreg142 GPR64common:%vreg144
	    Successors according to CFG: BB#43

3904B	BB#43: derived from LLVM BB %if.end.82
	    Predecessors according to CFG: BB#41 BB#42
3920B		B <BB#71>
	    Successors according to CFG: BB#71

3936B	BB#44: derived from LLVM BB %if.end.83
	    Predecessors according to CFG: BB#38
3952B		B <BB#45>
	    Successors according to CFG: BB#45

3968B	BB#45: derived from LLVM BB %if.end.84
	    Predecessors according to CFG: BB#36 BB#44
3984B		%vreg134<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32common:%vreg134
4000B		%WZR<def> = SUBSWri %vreg134, 4, 0, %NZCV<imp-def>; GPR32common:%vreg134
4016B		Bcc 1, <BB#47>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#47 BB#46

4032B	BB#46: derived from LLVM BB %if.then.87
	    Predecessors according to CFG: BB#45
4048B		B <BB#48>
	    Successors according to CFG: BB#48

4064B	BB#47: derived from LLVM BB %if.end.88
	    Predecessors according to CFG: BB#45
4080B		B <BB#29>
	    Successors according to CFG: BB#29

4096B	BB#48: derived from LLVM BB %while.end
	    Predecessors according to CFG: BB#46
4112B		B <BB#49>
	    Successors according to CFG: BB#49

4128B	BB#49: derived from LLVM BB %if.end.89
	    Predecessors according to CFG: BB#26 BB#27 BB#48
4144B		%vreg158<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg158
4160B		CBNZW %vreg158, <BB#58>; GPR32:%vreg158
	    Successors according to CFG: BB#58 BB#50

4176B	BB#50: derived from LLVM BB %land.lhs.true.91
	    Predecessors according to CFG: BB#49
4192B		%vreg164<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg164
4208B		%vreg163<def> = LDRXui %vreg164, 0; mem:LD8[%handle92] GPR64:%vreg163 GPR64common:%vreg164
4224B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4240B		%X0<def> = COPY %vreg163; GPR64:%vreg163
4256B		BL <ga:@ferror>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
4272B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4288B		%vreg161<def> = COPY %W0; GPR32:%vreg161
4304B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4320B		STACKMAP 5, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5]
4336B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4352B		CBNZW %vreg161, <BB#58>; GPR32:%vreg161
	    Successors according to CFG: BB#58 BB#51

4368B	BB#51: derived from LLVM BB %if.then.95
	    Predecessors according to CFG: BB#50
4384B		%vreg175<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg175
4400B		%vreg174<def> = LDRXui %vreg175, 0; mem:LD8[%handle96] GPR64:%vreg174 GPR64common:%vreg175
4416B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4432B		%X0<def> = COPY %vreg174; GPR64:%vreg174
4448B		BL <ga:@fflush>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
4464B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4480B		%vreg172<def,dead> = COPY %W0; GPR32all:%vreg172
4496B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4512B		STACKMAP 6, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5]
4528B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4544B		%vreg170<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg170
4560B		%vreg169<def> = LDRXui %vreg170, 0; mem:LD8[%handle98] GPR64:%vreg169 GPR64common:%vreg170
4576B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4592B		%X0<def> = COPY %vreg169; GPR64:%vreg169
4608B		BL <ga:@ferror>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
4624B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4640B		%vreg167<def> = COPY %W0; GPR32:%vreg167
4656B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4672B		STACKMAP 7, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5]
4688B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4704B		CBZW %vreg167, <BB#57>; GPR32:%vreg167
	    Successors according to CFG: BB#57 BB#52

4720B	BB#52: derived from LLVM BB %if.then.101
	    Predecessors according to CFG: BB#51
4736B		%vreg177<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg177
4752B		CBZX %vreg177, <BB#54>; GPR64:%vreg177
	    Successors according to CFG: BB#54 BB#53

4768B	BB#53: derived from LLVM BB %if.then.104
	    Predecessors according to CFG: BB#52
4800B		%vreg180<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg180
4808B		%vreg178<def> = MOVi32imm 4294967290; GPR32:%vreg178
4816B		STRWui %vreg178, %vreg180, 0; mem:ST4[%67] GPR32:%vreg178 GPR64common:%vreg180
	    Successors according to CFG: BB#54

4832B	BB#54: derived from LLVM BB %if.end.105
	    Predecessors according to CFG: BB#52 BB#53
4848B		%vreg182<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg182
4864B		CBZX %vreg182, <BB#56>; GPR64:%vreg182
	    Successors according to CFG: BB#56 BB#55

4880B	BB#55: derived from LLVM BB %if.then.108
	    Predecessors according to CFG: BB#54
4912B		%vreg185<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg185
4920B		%vreg183<def> = MOVi32imm 4294967290; GPR32:%vreg183
4928B		STRWui %vreg183, %vreg185, 1274; mem:ST4[%lastErr109] GPR32:%vreg183 GPR64common:%vreg185
	    Successors according to CFG: BB#56

4944B	BB#56: derived from LLVM BB %if.end.110
	    Predecessors according to CFG: BB#54 BB#55
4960B		B <BB#71>
	    Successors according to CFG: BB#71

4976B	BB#57: derived from LLVM BB %if.end.111
	    Predecessors according to CFG: BB#51
4992B		B <BB#58>
	    Successors according to CFG: BB#58

5008B	BB#58: derived from LLVM BB %if.end.112
	    Predecessors according to CFG: BB#49 BB#50 BB#57
5024B		%vreg187<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg187
5040B		CBZX %vreg187, <BB#60>; GPR64:%vreg187
	    Successors according to CFG: BB#60 BB#59

5056B	BB#59: derived from LLVM BB %if.then.115
	    Predecessors according to CFG: BB#58
5072B		%vreg193<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg193
5088B		%vreg192<def> = LDRWui %vreg193, 1257; mem:LD4[%total_in_lo32] GPR32:%vreg192 GPR64common:%vreg193
5104B		%vreg190<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg190
5120B		STRWui %vreg192, %vreg190, 0; mem:ST4[%73] GPR32:%vreg192 GPR64common:%vreg190
	    Successors according to CFG: BB#60

5136B	BB#60: derived from LLVM BB %if.end.117
	    Predecessors according to CFG: BB#58 BB#59
5152B		%vreg195<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64:%vreg195
5168B		CBZX %vreg195, <BB#62>; GPR64:%vreg195
	    Successors according to CFG: BB#62 BB#61

5184B	BB#61: derived from LLVM BB %if.then.120
	    Predecessors according to CFG: BB#60
5200B		%vreg201<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg201
5216B		%vreg200<def> = LDRWui %vreg201, 1258; mem:LD4[%total_in_hi32] GPR32:%vreg200 GPR64common:%vreg201
5232B		%vreg198<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg198
5248B		STRWui %vreg200, %vreg198, 0; mem:ST4[%77] GPR32:%vreg200 GPR64common:%vreg198
	    Successors according to CFG: BB#62

5264B	BB#62: derived from LLVM BB %if.end.122
	    Predecessors according to CFG: BB#60 BB#61
5280B		%vreg203<def> = LDRXui <fi#5>, 0; mem:LD8[FixedStack5] GPR64:%vreg203
5296B		CBZX %vreg203, <BB#64>; GPR64:%vreg203
	    Successors according to CFG: BB#64 BB#63

5312B	BB#63: derived from LLVM BB %if.then.125
	    Predecessors according to CFG: BB#62
5328B		%vreg209<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg209
5344B		%vreg208<def> = LDRWui %vreg209, 1263; mem:LD4[%total_out_lo32] GPR32:%vreg208 GPR64common:%vreg209
5360B		%vreg206<def> = LDRXui <fi#5>, 0; mem:LD8[FixedStack5] GPR64common:%vreg206
5376B		STRWui %vreg208, %vreg206, 0; mem:ST4[%81] GPR32:%vreg208 GPR64common:%vreg206
	    Successors according to CFG: BB#64

5392B	BB#64: derived from LLVM BB %if.end.127
	    Predecessors according to CFG: BB#62 BB#63
5408B		%vreg211<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64:%vreg211
5424B		CBZX %vreg211, <BB#66>; GPR64:%vreg211
	    Successors according to CFG: BB#66 BB#65

5440B	BB#65: derived from LLVM BB %if.then.130
	    Predecessors according to CFG: BB#64
5456B		%vreg217<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg217
5472B		%vreg216<def> = LDRWui %vreg217, 1264; mem:LD4[%total_out_hi32] GPR32:%vreg216 GPR64common:%vreg217
5488B		%vreg214<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg214
5504B		STRWui %vreg216, %vreg214, 0; mem:ST4[%85] GPR32:%vreg216 GPR64common:%vreg214
	    Successors according to CFG: BB#66

5520B	BB#66: derived from LLVM BB %if.end.132
	    Predecessors according to CFG: BB#64 BB#65
5536B		%vreg219<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg219
5552B		CBZX %vreg219, <BB#68>; GPR64:%vreg219
	    Successors according to CFG: BB#68 BB#67

5568B	BB#67: derived from LLVM BB %if.then.135
	    Predecessors according to CFG: BB#66
5584B		%vreg221<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg221
5600B		STRWui %WZR, %vreg221, 0; mem:ST4[%87] GPR64common:%vreg221
	    Successors according to CFG: BB#68

5616B	BB#68: derived from LLVM BB %if.end.136
	    Predecessors according to CFG: BB#66 BB#67
5632B		%vreg223<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg223
5648B		CBZX %vreg223, <BB#70>; GPR64:%vreg223
	    Successors according to CFG: BB#70 BB#69

5664B	BB#69: derived from LLVM BB %if.then.139
	    Predecessors according to CFG: BB#68
5680B		%vreg225<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg225
5696B		STRWui %WZR, %vreg225, 1274; mem:ST4[%lastErr140] GPR64common:%vreg225
	    Successors according to CFG: BB#70

5712B	BB#70: derived from LLVM BB %if.end.141
	    Predecessors according to CFG: BB#68 BB#69
5728B		%vreg235<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg235
5744B		%vreg233<def> = MOVi64imm 5016; GPR64:%vreg233
5760B		%vreg234<def> = ADDXrr %vreg235, %vreg233; GPR64:%vreg234,%vreg235,%vreg233
5776B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5792B		%X0<def> = COPY %vreg234; GPR64:%vreg234
5808B		BL <ga:@BZ2_bzCompressEnd>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
5824B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5840B		%vreg231<def,dead> = COPY %W0; GPR32all:%vreg231
5856B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5872B		STACKMAP 8, 0, 0, <fi#10>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack10]
5888B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5904B		%vreg228<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg228
5936B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5952B		%X0<def> = COPY %vreg228; GPR64:%vreg228
5968B		BL <ga:@free>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>
5984B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
6000B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
6016B		STACKMAP 9, 0, %LR<earlyclobber,imp-def,dead>, ...
6032B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#71

6048B	BB#71: derived from LLVM BB %return
	    Predecessors according to CFG: BB#11 BB#43 BB#35 BB#56 BB#70 BB#17 BB#5
6064B		%vreg254<def> = ADRP <ga:@BZ2_bzWriteClose64>[TF=1]; GPR64common:%vreg254
6080B		%vreg256<def> = ADDXri %vreg254, <ga:@BZ2_bzWriteClose64>[TF=34], 0; GPR64sp:%vreg256 GPR64common:%vreg254
6128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
6144B		%X0<def> = COPY %vreg256; GPR64sp:%vreg256
6160B		%X1<def> = COPY %vreg23; GPR64:%vreg23
6176B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
6192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
6208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
6224B		STACKMAP 10, 0, %LR<earlyclobber,imp-def,dead>, ...
6240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
6256B		RET_ReallyLR

# End machine code for function BZ2_bzWriteClose64.


selectOrSplit GPR64:%vreg23 [16r,6160r:0)  0@16r w=4.630196e-04
hints: %X1
missed hint %X1
assigning %vreg23 to %X19: W19 [16r,6160r:0)  0@16r

selectOrSplit GPR64:%vreg13 [32r,544r:0)  0@32r w=3.322368e-03
hints: %X6
missed hint %X6
assigning %vreg13 to %X20: W20 [32r,544r:0)  0@32r

selectOrSplit GPR64:%vreg11 [48r,528r:0)  0@48r w=3.443182e-03
hints: %X5
missed hint %X5
assigning %vreg11 to %X21: W21 [48r,528r:0)  0@48r

selectOrSplit GPR64:%vreg9 [64r,512r:0)  0@64r w=3.573113e-03
hints: %X4
missed hint %X4
assigning %vreg9 to %X22: W22 [64r,512r:0)  0@64r

selectOrSplit GPR64:%vreg7 [80r,496r:0)  0@80r w=3.713235e-03
hints: %X3
missed hint %X3
assigning %vreg7 to %X23: W23 [80r,496r:0)  0@80r

selectOrSplit GPR32:%vreg5 [96r,480r:0)  0@96r w=3.864796e-03
hints: %W2
missed hint %W2
assigning %vreg5 to %W24: W24 [96r,480r:0)  0@96r

selectOrSplit GPR64:%vreg3 [112r,464r:0)  0@112r w=4.029255e-03
hints: %X1
missed hint %X1
assigning %vreg3 to %X25: W25 [112r,464r:0)  0@112r

selectOrSplit GPR64:%vreg1 [128r,448r:0)  0@128r w=4.208333e-03
hints: %X0
missed hint %X0
assigning %vreg1 to %X26: W26 [128r,448r:0)  0@128r

selectOrSplit GPR64sp:%vreg22 [272r,336r:0)  0@272r w=4.353448e-03
hints: %X0
assigning %vreg22 to %X0: W0 [272r,336r:0)  0@272r

selectOrSplit GPR64:%vreg46 [1264r,1296r:0)  0@1264r w=1.167863e-03
hints: %X0
assigning %vreg46 to %X0: W0 [1264r,1296r:0)  0@1264r

selectOrSplit GPR32:%vreg44 [1344r,1408r:0)  0@1344r w=1.087321e-03
hints: %W0
assigning %vreg44 to %W0: W0 [1344r,1408r:0)  0@1344r

selectOrSplit GPR64:%vreg78 [2384r,2440r:0)  0@2384r w=1.801603e-04
hints: %X0
assigning %vreg78 to %X0: W0 [2384r,2440r:0)  0@2384r

selectOrSplit GPR32:%vreg75 [2480r,2544r:0)  0@2480r w=1.770541e-04
hints: %W0
assigning %vreg75 to %W0: W0 [2480r,2544r:0)  0@2480r

selectOrSplit GPR64:%vreg115 [3192r,3264r:0)  0@3192r w=6.347823e-05
hints: %X2
assigning %vreg115 to %X2: W2 [3192r,3264r:0)  0@3192r

selectOrSplit GPR64:%vreg110 [3200r,3280r:0)  0@3200r w=6.242025e-05
hints: %X3
assigning %vreg110 to %X3: W3 [3200r,3280r:0)  0@3200r

selectOrSplit GPR64sp:%vreg118 [3208r,3232r:0)  0@3208r w=7.066444e-05
hints: %X0
assigning %vreg118 to %X0: W0 [3208r,3232r:0)  0@3208r

selectOrSplit GPR64:%vreg108 [3328r,3408r:0)  0@3328r w=6.242025e-05
hints: %X0
assigning %vreg108 to %X0: W0 [3328r,3408r:0)  0@3328r

selectOrSplit GPR64:%vreg131 [3520r,3552r:0)  0@3520r w=3.355927e-05
hints: %X0
assigning %vreg131 to %X0: W0 [3520r,3552r:0)  0@3520r

selectOrSplit GPR32:%vreg129 [3600r,3664r:0)  0@3600r w=3.124484e-05
hints: %W0
assigning %vreg129 to %W0: W0 [3600r,3664r:0)  0@3600r

selectOrSplit GPR64:%vreg163 [4208r,4240r:0)  0@4208r w=2.393895e-04
hints: %X0
assigning %vreg163 to %X0: W0 [4208r,4240r:0)  0@4208r

selectOrSplit GPR32:%vreg161 [4288r,4352r:0)  0@4288r w=2.228799e-04
hints: %W0
assigning %vreg161 to %W0: W0 [4288r,4352r:0)  0@4288r

selectOrSplit GPR64:%vreg174 [4400r,4432r:0)  0@4400r w=1.185761e-04
hints: %X0
assigning %vreg174 to %X0: W0 [4400r,4432r:0)  0@4400r

selectOrSplit GPR32all:%vreg172 [4480r,4480d:0)  0@4480r w=inf
hints: %W0
assigning %vreg172 to %W0: W0 [4480r,4480d:0)  0@4480r

selectOrSplit GPR64:%vreg169 [4560r,4592r:0)  0@4560r w=1.185761e-04
hints: %X0
assigning %vreg169 to %X0: W0 [4560r,4592r:0)  0@4560r

selectOrSplit GPR32:%vreg167 [4640r,4704r:0)  0@4640r w=1.103984e-04
hints: %W0
assigning %vreg167 to %W0: W0 [4640r,4704r:0)  0@4640r

selectOrSplit GPR64:%vreg234 [5760r,5792r:0)  0@5760r w=4.206096e-04
hints: %X0
assigning %vreg234 to %X0: W0 [5760r,5792r:0)  0@5760r

selectOrSplit GPR32all:%vreg231 [5840r,5840d:0)  0@5840r w=inf
hints: %W0
assigning %vreg231 to %W0: W0 [5840r,5840d:0)  0@5840r

selectOrSplit GPR64:%vreg228 [5904r,5952r:0)  0@5904r w=4.055878e-04
hints: %X0
assigning %vreg228 to %X0: W0 [5904r,5952r:0)  0@5904r

selectOrSplit GPR64sp:%vreg256 [6080r,6144r:0)  0@6080r w=4.353448e-03
hints: %X0
assigning %vreg256 to %X0: W0 [6080r,6144r:0)  0@6080r

selectOrSplit GPR64common:%vreg20 [256r,272r:0)  0@256r w=inf
assigning %vreg20 to %X8: W8 [256r,272r:0)  0@256r

selectOrSplit GPR64:%vreg18 [560r,592r:0)  0@560r w=inf
assigning %vreg18 to %X8: W8 [560r,592r:0)  0@560r

selectOrSplit GPR64:%vreg15 [608r,624r:0)  0@608r w=inf
assigning %vreg15 to %X8: W8 [608r,624r:0)  0@608r

selectOrSplit GPR64:%vreg247 [656r,672r:0)  0@656r w=inf
assigning %vreg247 to %X8: W8 [656r,672r:0)  0@656r

selectOrSplit GPR64common:%vreg249 [704r,720r:0)  0@704r w=inf
assigning %vreg249 to %X8: W8 [704r,720r:0)  0@704r

selectOrSplit GPR64:%vreg251 [752r,768r:0)  0@752r w=inf
assigning %vreg251 to %X8: W8 [752r,768r:0)  0@752r

selectOrSplit GPR64common:%vreg253 [800r,816r:0)  0@800r w=inf
assigning %vreg253 to %X8: W8 [800r,816r:0)  0@800r

selectOrSplit GPR64:%vreg31 [880r,912r:0)  0@880r w=2.314815e-03
assigning %vreg31 to %X8: W8 [880r,912r:0)  0@880r

selectOrSplit GPR64:%vreg28 [896r,912r:0)  0@896r w=inf
assigning %vreg28 to %X9: W9 [896r,912r:0)  0@896r

selectOrSplit GPR64common:%vreg29 [912r,928r:0)  0@912r w=inf
assigning %vreg29 to %X8: W8 [912r,928r:0)  0@912r

selectOrSplit GPR32:%vreg30 [928r,944r:0)  0@928r w=inf
assigning %vreg30 to %W8: W8 [928r,944r:0)  0@928r

selectOrSplit GPR32:%vreg26 [944r,960r:0)  0@944r w=inf
assigning %vreg26 to %W8: W8 [944r,960r:0)  0@944r

selectOrSplit GPR64:%vreg33 [992r,1008r:0)  0@992r w=inf
assigning %vreg33 to %X8: W8 [992r,1008r:0)  0@992r

selectOrSplit GPR64common:%vreg36 [1056r,1072r:0)  0@1056r w=6.003865e-04
assigning %vreg36 to %X8: W8 [1056r,1072r:0)  0@1056r

selectOrSplit GPR32:%vreg34 [1064r,1072r:0)  0@1064r w=inf
assigning %vreg34 to %W9: W9 [1064r,1072r:0)  0@1064r

selectOrSplit GPR64:%vreg38 [1104r,1120r:0)  0@1104r w=inf
assigning %vreg38 to %X8: W8 [1104r,1120r:0)  0@1104r

selectOrSplit GPR64common:%vreg41 [1168r,1184r:0)  0@1168r w=6.003865e-04
assigning %vreg41 to %X8: W8 [1168r,1184r:0)  0@1168r

selectOrSplit GPR32:%vreg39 [1176r,1184r:0)  0@1176r w=inf
assigning %vreg39 to %W9: W9 [1176r,1184r:0)  0@1176r

selectOrSplit GPR64common:%vreg47 [1248r,1264r:0)  0@1248r w=inf
assigning %vreg47 to %X8: W8 [1248r,1264r:0)  0@1248r

selectOrSplit GPR64:%vreg237 [1440r,1456r:0)  0@1440r w=inf
assigning %vreg237 to %X8: W8 [1440r,1456r:0)  0@1440r

selectOrSplit GPR64common:%vreg240 [1504r,1520r:0)  0@1504r w=2.990431e-04
assigning %vreg240 to %X8: W8 [1504r,1520r:0)  0@1504r

selectOrSplit GPR32:%vreg238 [1512r,1520r:0)  0@1512r w=inf
assigning %vreg238 to %W9: W9 [1512r,1520r:0)  0@1512r

selectOrSplit GPR64:%vreg242 [1552r,1568r:0)  0@1552r w=inf
assigning %vreg242 to %X8: W8 [1552r,1568r:0)  0@1552r

selectOrSplit GPR64common:%vreg245 [1616r,1632r:0)  0@1616r w=2.990431e-04
assigning %vreg245 to %X8: W8 [1616r,1632r:0)  0@1616r

selectOrSplit GPR32:%vreg243 [1624r,1632r:0)  0@1624r w=inf
assigning %vreg243 to %W9: W9 [1624r,1632r:0)  0@1624r

selectOrSplit GPR64:%vreg49 [1696r,1712r:0)  0@1696r w=inf
assigning %vreg49 to %X8: W8 [1696r,1712r:0)  0@1696r

selectOrSplit GPR64common:%vreg51 [1744r,1760r:0)  0@1744r w=inf
assigning %vreg51 to %X8: W8 [1744r,1760r:0)  0@1744r

selectOrSplit GPR64:%vreg53 [1792r,1808r:0)  0@1792r w=inf
assigning %vreg53 to %X8: W8 [1792r,1808r:0)  0@1792r

selectOrSplit GPR64common:%vreg55 [1840r,1856r:0)  0@1840r w=inf
assigning %vreg55 to %X8: W8 [1840r,1856r:0)  0@1840r

selectOrSplit GPR64:%vreg57 [1888r,1904r:0)  0@1888r w=inf
assigning %vreg57 to %X8: W8 [1888r,1904r:0)  0@1888r

selectOrSplit GPR64common:%vreg59 [1936r,1952r:0)  0@1936r w=inf
assigning %vreg59 to %X8: W8 [1936r,1952r:0)  0@1936r

selectOrSplit GPR64:%vreg61 [1984r,2000r:0)  0@1984r w=inf
assigning %vreg61 to %X8: W8 [1984r,2000r:0)  0@1984r

selectOrSplit GPR64common:%vreg63 [2032r,2048r:0)  0@2032r w=inf
assigning %vreg63 to %X8: W8 [2032r,2048r:0)  0@2032r

selectOrSplit GPR32:%vreg65 [2080r,2096r:0)  0@2080r w=inf
assigning %vreg65 to %W8: W8 [2080r,2096r:0)  0@2080r

selectOrSplit GPR64common:%vreg69 [2128r,2144r:0)  0@2128r w=inf
assigning %vreg69 to %X8: W8 [2128r,2144r:0)  0@2128r

selectOrSplit GPR32:%vreg68 [2144r,2160r:0)  0@2144r w=inf
assigning %vreg68 to %W8: W8 [2144r,2160r:0)  0@2144r

selectOrSplit GPR64common:%vreg89 [2256r,2272r:0)  0@2256r w=1.955281e-04
assigning %vreg89 to %X8: W8 [2256r,2272r:0)  0@2256r

selectOrSplit GPR32:%vreg87 [2264r,2272r:0)  0@2264r w=inf
assigning %vreg87 to %W9: W9 [2264r,2272r:0)  0@2264r

selectOrSplit GPR64common:%vreg86 [2288r,2328r:0)  0@2288r w=1.848630e-04
assigning %vreg86 to %X8: W8 [2288r,2328r:0)  0@2288r

selectOrSplit GPR64common:%vreg82 [2320r,2336r:0)  0@2320r w=1.955281e-04
assigning %vreg82 to %X9: W9 [2320r,2336r:0)  0@2320r

selectOrSplit GPR64common:%vreg85 [2328r,2336r:0)  0@2328r w=inf
assigning %vreg85 to %X8: W8 [2328r,2336r:0)  0@2328r

selectOrSplit GPR64:%vreg79 [2352r,2384r:0)  0@2352r w=1.882864e-04
assigning %vreg79 to %X8: W8 [2352r,2384r:0)  0@2352r

selectOrSplit GPR64:%vreg77 [2368r,2384r:0)  0@2368r w=inf
assigning %vreg77 to %X9: W9 [2368r,2384r:0)  0@2368r

selectOrSplit GPR32common:%vreg71 [2560r,2576r:0)  0@2560r w=inf
assigning %vreg71 to %W8: W8 [2560r,2576r:0)  0@2560r

selectOrSplit GPR32common:%vreg91 [2624r,2640r:0)  0@2624r w=inf
assigning %vreg91 to %W8: W8 [2624r,2640r:0)  0@2624r

selectOrSplit GPR64:%vreg146 [2688r,2704r:0)  0@2688r w=inf
assigning %vreg146 to %X8: W8 [2688r,2704r:0)  0@2688r

selectOrSplit GPR32:%vreg150 [2736r,2768r:0)  0@2736r w=2.215134e-05
assigning %vreg150 to %W8: W8 [2736r,2768r:0)  0@2736r

selectOrSplit GPR64common:%vreg149 [2752r,2768r:0)  0@2752r w=inf
assigning %vreg149 to %X9: W9 [2752r,2768r:0)  0@2752r

selectOrSplit GPR64:%vreg152 [2800r,2816r:0)  0@2800r w=inf
assigning %vreg152 to %X8: W8 [2800r,2816r:0)  0@2800r

selectOrSplit GPR32:%vreg156 [2848r,2880r:0)  0@2848r w=2.215134e-05
assigning %vreg156 to %W8: W8 [2848r,2880r:0)  0@2848r

selectOrSplit GPR64common:%vreg155 [2864r,2880r:0)  0@2864r w=inf
assigning %vreg155 to %X9: W9 [2864r,2880r:0)  0@2864r

selectOrSplit GPR64common:%vreg96 [2960r,2976r:0)  0@2960r w=inf
assigning %vreg96 to %X8: W8 [2960r,2976r:0)  0@2960r

selectOrSplit GPR32:%vreg95 [2976r,2992r:0)  0@2976r w=1.449209e-04
assigning %vreg95 to %W8: W8 [2976r,2992r:0)  0@2976r

selectOrSplit GPR32:%vreg93 [2984r,2992r:0)  0@2984r w=inf
assigning %vreg93 to %W9: W9 [2984r,2992r:0)  0@2984r

selectOrSplit GPR64common:%vreg126 [3072r,3088r:0)  0@3072r w=inf
assigning %vreg126 to %X8: W8 [3072r,3088r:0)  0@3072r

selectOrSplit GPR32:%vreg125 [3088r,3104r:0)  0@3088r w=7.131027e-05
assigning %vreg125 to %W8: W8 [3088r,3104r:0)  0@3088r

selectOrSplit GPR32:%vreg121 [3096r,3104r:0)  0@3096r w=inf
assigning %vreg121 to %W9: W9 [3096r,3104r:0)  0@3096r

selectOrSplit GPR32:%vreg123 [3104r,3120r:0)  0@3104r w=inf
assigning %vreg123 to %W8: W8 [3104r,3120r:0)  0@3104r

selectOrSplit GPR64common:%vreg111 [3184r,3200r:0)  0@3184r w=7.131027e-05
assigning %vreg111 to %X8: W8 [3184r,3200r:0)  0@3184r

selectOrSplit GPR64common:%vreg119 [3188r,3208r:0)  0@3188r w=7.063113e-05
assigning %vreg119 to %X9: W9 [3188r,3208r:0)  0@3188r

selectOrSplit GPR32:%vreg100 [3424r,3456r:0)  0@3424r w=6.866915e-05
assigning %vreg100 to %W8: W8 [3424r,3456r:0)  0@3424r

selectOrSplit GPR32:%vreg99 [3440r,3456r:0)  0@3440r w=inf
assigning %vreg99 to %W9: W9 [3440r,3456r:0)  0@3440r

selectOrSplit GPR64common:%vreg132 [3504r,3520r:0)  0@3504r w=inf
assigning %vreg132 to %X8: W8 [3504r,3520r:0)  0@3504r

selectOrSplit GPR64:%vreg136 [3696r,3712r:0)  0@3696r w=inf
assigning %vreg136 to %X8: W8 [3696r,3712r:0)  0@3696r

selectOrSplit GPR64common:%vreg139 [3760r,3776r:0)  0@3760r w=2.760398e-05
assigning %vreg139 to %X8: W8 [3760r,3776r:0)  0@3760r

selectOrSplit GPR32:%vreg137 [3768r,3776r:0)  0@3768r w=inf
assigning %vreg137 to %W9: W9 [3768r,3776r:0)  0@3768r

selectOrSplit GPR64:%vreg141 [3808r,3824r:0)  0@3808r w=inf
assigning %vreg141 to %X8: W8 [3808r,3824r:0)  0@3808r

selectOrSplit GPR64common:%vreg144 [3872r,3888r:0)  0@3872r w=2.760398e-05
assigning %vreg144 to %X8: W8 [3872r,3888r:0)  0@3872r

selectOrSplit GPR32:%vreg142 [3880r,3888r:0)  0@3880r w=inf
assigning %vreg142 to %W9: W9 [3880r,3888r:0)  0@3880r

selectOrSplit GPR32common:%vreg134 [3984r,4000r:0)  0@3984r w=inf
assigning %vreg134 to %W8: W8 [3984r,4000r:0)  0@3984r

selectOrSplit GPR32:%vreg158 [4144r,4160r:0)  0@4144r w=inf
assigning %vreg158 to %W8: W8 [4144r,4160r:0)  0@4144r

selectOrSplit GPR64common:%vreg164 [4192r,4208r:0)  0@4192r w=inf
assigning %vreg164 to %X8: W8 [4192r,4208r:0)  0@4192r

selectOrSplit GPR64common:%vreg175 [4384r,4400r:0)  0@4384r w=inf
assigning %vreg175 to %X8: W8 [4384r,4400r:0)  0@4384r

selectOrSplit GPR64common:%vreg170 [4544r,4560r:0)  0@4544r w=inf
assigning %vreg170 to %X8: W8 [4544r,4560r:0)  0@4544r

selectOrSplit GPR64:%vreg177 [4736r,4752r:0)  0@4736r w=inf
assigning %vreg177 to %X8: W8 [4736r,4752r:0)  0@4736r

selectOrSplit GPR64common:%vreg180 [4800r,4816r:0)  0@4800r w=2.990431e-05
assigning %vreg180 to %X8: W8 [4800r,4816r:0)  0@4800r

selectOrSplit GPR32:%vreg178 [4808r,4816r:0)  0@4808r w=inf
assigning %vreg178 to %W9: W9 [4808r,4816r:0)  0@4808r

selectOrSplit GPR64:%vreg182 [4848r,4864r:0)  0@4848r w=inf
assigning %vreg182 to %X8: W8 [4848r,4864r:0)  0@4848r

selectOrSplit GPR64common:%vreg185 [4912r,4928r:0)  0@4912r w=2.990431e-05
assigning %vreg185 to %X8: W8 [4912r,4928r:0)  0@4912r

selectOrSplit GPR32:%vreg183 [4920r,4928r:0)  0@4920r w=inf
assigning %vreg183 to %W9: W9 [4920r,4928r:0)  0@4920r

selectOrSplit GPR64:%vreg187 [5024r,5040r:0)  0@5024r w=inf
assigning %vreg187 to %X8: W8 [5024r,5040r:0)  0@5024r

selectOrSplit GPR64common:%vreg193 [5072r,5088r:0)  0@5072r w=inf
assigning %vreg193 to %X8: W8 [5072r,5088r:0)  0@5072r

selectOrSplit GPR32:%vreg192 [5088r,5120r:0)  0@5088r w=2.082226e-04
assigning %vreg192 to %W8: W8 [5088r,5120r:0)  0@5088r

selectOrSplit GPR64common:%vreg190 [5104r,5120r:0)  0@5104r w=inf
assigning %vreg190 to %X9: W9 [5104r,5120r:0)  0@5104r

selectOrSplit GPR64:%vreg195 [5152r,5168r:0)  0@5152r w=inf
assigning %vreg195 to %X8: W8 [5152r,5168r:0)  0@5152r

selectOrSplit GPR64common:%vreg201 [5200r,5216r:0)  0@5200r w=inf
assigning %vreg201 to %X8: W8 [5200r,5216r:0)  0@5200r

selectOrSplit GPR32:%vreg200 [5216r,5248r:0)  0@5216r w=2.082226e-04
assigning %vreg200 to %W8: W8 [5216r,5248r:0)  0@5216r

selectOrSplit GPR64common:%vreg198 [5232r,5248r:0)  0@5232r w=inf
assigning %vreg198 to %X9: W9 [5232r,5248r:0)  0@5232r

selectOrSplit GPR64:%vreg203 [5280r,5296r:0)  0@5280r w=inf
assigning %vreg203 to %X8: W8 [5280r,5296r:0)  0@5280r

selectOrSplit GPR64common:%vreg209 [5328r,5344r:0)  0@5328r w=inf
assigning %vreg209 to %X8: W8 [5328r,5344r:0)  0@5328r

selectOrSplit GPR32:%vreg208 [5344r,5376r:0)  0@5344r w=2.082226e-04
assigning %vreg208 to %W8: W8 [5344r,5376r:0)  0@5344r

selectOrSplit GPR64common:%vreg206 [5360r,5376r:0)  0@5360r w=inf
assigning %vreg206 to %X9: W9 [5360r,5376r:0)  0@5360r

selectOrSplit GPR64:%vreg211 [5408r,5424r:0)  0@5408r w=inf
assigning %vreg211 to %X8: W8 [5408r,5424r:0)  0@5408r

selectOrSplit GPR64common:%vreg217 [5456r,5472r:0)  0@5456r w=inf
assigning %vreg217 to %X8: W8 [5456r,5472r:0)  0@5456r

selectOrSplit GPR32:%vreg216 [5472r,5504r:0)  0@5472r w=2.082226e-04
assigning %vreg216 to %W8: W8 [5472r,5504r:0)  0@5472r

selectOrSplit GPR64common:%vreg214 [5488r,5504r:0)  0@5488r w=inf
assigning %vreg214 to %X9: W9 [5488r,5504r:0)  0@5488r

selectOrSplit GPR64:%vreg219 [5536r,5552r:0)  0@5536r w=inf
assigning %vreg219 to %X8: W8 [5536r,5552r:0)  0@5536r

selectOrSplit GPR64common:%vreg221 [5584r,5600r:0)  0@5584r w=inf
assigning %vreg221 to %X8: W8 [5584r,5600r:0)  0@5584r

selectOrSplit GPR64:%vreg223 [5632r,5648r:0)  0@5632r w=inf
assigning %vreg223 to %X8: W8 [5632r,5648r:0)  0@5632r

selectOrSplit GPR64common:%vreg225 [5680r,5696r:0)  0@5680r w=inf
assigning %vreg225 to %X8: W8 [5680r,5696r:0)  0@5680r

selectOrSplit GPR64:%vreg235 [5728r,5760r:0)  0@5728r w=4.164451e-04
assigning %vreg235 to %X8: W8 [5728r,5760r:0)  0@5728r

selectOrSplit GPR64:%vreg233 [5744r,5760r:0)  0@5744r w=inf
assigning %vreg233 to %X9: W9 [5744r,5760r:0)  0@5744r

selectOrSplit GPR64common:%vreg254 [6064r,6080r:0)  0@6064r w=inf
assigning %vreg254 to %X8: W8 [6064r,6080r:0)  0@6064r

********** STACK TRANSFORMATION METADATA **********
********** Function: BZ2_bzWriteClose64
********** REGISTER MAP **********
[%vreg1 -> %X26] GPR64
[%vreg3 -> %X25] GPR64
[%vreg5 -> %W24] GPR32
[%vreg7 -> %X23] GPR64
[%vreg9 -> %X22] GPR64
[%vreg11 -> %X21] GPR64
[%vreg13 -> %X20] GPR64
[%vreg15 -> %X8] GPR64
[%vreg18 -> %X8] GPR64
[%vreg20 -> %X8] GPR64common
[%vreg22 -> %X0] GPR64sp
[%vreg23 -> %X19] GPR64
[%vreg26 -> %W8] GPR32
[%vreg28 -> %X9] GPR64
[%vreg29 -> %X8] GPR64common
[%vreg30 -> %W8] GPR32
[%vreg31 -> %X8] GPR64
[%vreg33 -> %X8] GPR64
[%vreg34 -> %W9] GPR32
[%vreg36 -> %X8] GPR64common
[%vreg38 -> %X8] GPR64
[%vreg39 -> %W9] GPR32
[%vreg41 -> %X8] GPR64common
[%vreg44 -> %W0] GPR32
[%vreg46 -> %X0] GPR64
[%vreg47 -> %X8] GPR64common
[%vreg49 -> %X8] GPR64
[%vreg51 -> %X8] GPR64common
[%vreg53 -> %X8] GPR64
[%vreg55 -> %X8] GPR64common
[%vreg57 -> %X8] GPR64
[%vreg59 -> %X8] GPR64common
[%vreg61 -> %X8] GPR64
[%vreg63 -> %X8] GPR64common
[%vreg65 -> %W8] GPR32
[%vreg68 -> %W8] GPR32
[%vreg69 -> %X8] GPR64common
[%vreg71 -> %W8] GPR32common
[%vreg75 -> %W0] GPR32
[%vreg77 -> %X9] GPR64
[%vreg78 -> %X0] GPR64
[%vreg79 -> %X8] GPR64
[%vreg82 -> %X9] GPR64common
[%vreg85 -> %X8] GPR64common
[%vreg86 -> %X8] GPR64common
[%vreg87 -> %W9] GPR32
[%vreg89 -> %X8] GPR64common
[%vreg91 -> %W8] GPR32common
[%vreg93 -> %W9] GPR32
[%vreg95 -> %W8] GPR32
[%vreg96 -> %X8] GPR64common
[%vreg99 -> %W9] GPR32
[%vreg100 -> %W8] GPR32
[%vreg108 -> %X0] GPR64
[%vreg110 -> %X3] GPR64
[%vreg111 -> %X8] GPR64common
[%vreg115 -> %X2] GPR64
[%vreg118 -> %X0] GPR64sp
[%vreg119 -> %X9] GPR64common
[%vreg121 -> %W9] GPR32
[%vreg123 -> %W8] GPR32
[%vreg125 -> %W8] GPR32
[%vreg126 -> %X8] GPR64common
[%vreg129 -> %W0] GPR32
[%vreg131 -> %X0] GPR64
[%vreg132 -> %X8] GPR64common
[%vreg134 -> %W8] GPR32common
[%vreg136 -> %X8] GPR64
[%vreg137 -> %W9] GPR32
[%vreg139 -> %X8] GPR64common
[%vreg141 -> %X8] GPR64
[%vreg142 -> %W9] GPR32
[%vreg144 -> %X8] GPR64common
[%vreg146 -> %X8] GPR64
[%vreg149 -> %X9] GPR64common
[%vreg150 -> %W8] GPR32
[%vreg152 -> %X8] GPR64
[%vreg155 -> %X9] GPR64common
[%vreg156 -> %W8] GPR32
[%vreg158 -> %W8] GPR32
[%vreg161 -> %W0] GPR32
[%vreg163 -> %X0] GPR64
[%vreg164 -> %X8] GPR64common
[%vreg167 -> %W0] GPR32
[%vreg169 -> %X0] GPR64
[%vreg170 -> %X8] GPR64common
[%vreg172 -> %W0] GPR32all
[%vreg174 -> %X0] GPR64
[%vreg175 -> %X8] GPR64common
[%vreg177 -> %X8] GPR64
[%vreg178 -> %W9] GPR32
[%vreg180 -> %X8] GPR64common
[%vreg182 -> %X8] GPR64
[%vreg183 -> %W9] GPR32
[%vreg185 -> %X8] GPR64common
[%vreg187 -> %X8] GPR64
[%vreg190 -> %X9] GPR64common
[%vreg192 -> %W8] GPR32
[%vreg193 -> %X8] GPR64common
[%vreg195 -> %X8] GPR64
[%vreg198 -> %X9] GPR64common
[%vreg200 -> %W8] GPR32
[%vreg201 -> %X8] GPR64common
[%vreg203 -> %X8] GPR64
[%vreg206 -> %X9] GPR64common
[%vreg208 -> %W8] GPR32
[%vreg209 -> %X8] GPR64common
[%vreg211 -> %X8] GPR64
[%vreg214 -> %X9] GPR64common
[%vreg216 -> %W8] GPR32
[%vreg217 -> %X8] GPR64common
[%vreg219 -> %X8] GPR64
[%vreg221 -> %X8] GPR64common
[%vreg223 -> %X8] GPR64
[%vreg225 -> %X8] GPR64common
[%vreg228 -> %X0] GPR64
[%vreg231 -> %W0] GPR32all
[%vreg233 -> %X9] GPR64
[%vreg234 -> %X0] GPR64
[%vreg235 -> %X8] GPR64
[%vreg237 -> %X8] GPR64
[%vreg238 -> %W9] GPR32
[%vreg240 -> %X8] GPR64common
[%vreg242 -> %X8] GPR64
[%vreg243 -> %W9] GPR32
[%vreg245 -> %X8] GPR64common
[%vreg247 -> %X8] GPR64
[%vreg249 -> %X8] GPR64common
[%vreg251 -> %X8] GPR64
[%vreg253 -> %X8] GPR64common
[%vreg254 -> %X8] GPR64common
[%vreg256 -> %X0] GPR64sp


Stackmap 0:
  STACKMAP 0, 0, %vreg5, 0, <fi#2>, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, %vreg9, 0, <fi#4>, 0, %vreg7, 0, <fi#3>, 0, %vreg13, 0, <fi#6>, 0, %vreg11, 0, <fi#5>, 0, 0, <fi#9>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4) GPR32:%vreg5 GPR64:%vreg3,%vreg1,%vreg9,%vreg7,%vreg13,%vreg11

i32 %abandon: in register %W24 (vreg 5)
i32* %abandon.addr: in stack slot 2 (size: 4)
i8* %b: in register %X25 (vreg 3)
i8** %b.addr: in stack slot 1 (size: 8)
i32* %bzerror: in register %X26 (vreg 1)
i32** %bzerror.addr: in stack slot 0 (size: 8)
%struct.bzFile** %bzf: in stack slot 10 (size: 8)
i32* %n: in stack slot 7 (size: 4)
i32* %n2: in stack slot 8 (size: 4)
i32* %nbytes_in_hi32: in register %X22 (vreg 9)
i32** %nbytes_in_hi32.addr: in stack slot 4 (size: 8)
i32* %nbytes_in_lo32: in register %X23 (vreg 7)
i32** %nbytes_in_lo32.addr: in stack slot 3 (size: 8)
i32* %nbytes_out_hi32: in register %X20 (vreg 13)
i32** %nbytes_out_hi32.addr: in stack slot 6 (size: 8)
i32* %nbytes_out_lo32: in register %X21 (vreg 11)
i32** %nbytes_out_lo32.addr: in stack slot 5 (size: 8)
i32* %ret: in stack slot 9 (size: 4)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, 0, <fi#9>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4)

i32* %abandon.addr: in stack slot 2 (size: 4)
i32** %bzerror.addr: in stack slot 0 (size: 8)
%struct.bzFile** %bzf: in stack slot 10 (size: 8)
i32* %n: in stack slot 7 (size: 4)
i32* %n2: in stack slot 8 (size: 4)
i32** %nbytes_in_hi32.addr: in stack slot 4 (size: 8)
i32** %nbytes_in_lo32.addr: in stack slot 3 (size: 8)
i32** %nbytes_out_hi32.addr: in stack slot 6 (size: 8)
i32** %nbytes_out_lo32.addr: in stack slot 5 (size: 8)
i32* %ret: in stack slot 9 (size: 4)

Duplicate operand locations:


Stackmap 2:
  STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, 0, <fi#9>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4)

i32* %abandon.addr: in stack slot 2 (size: 4)
i32** %bzerror.addr: in stack slot 0 (size: 8)
%struct.bzFile** %bzf: in stack slot 10 (size: 8)
i32* %n: in stack slot 7 (size: 4)
i32* %n2: in stack slot 8 (size: 4)
i32** %nbytes_in_hi32.addr: in stack slot 4 (size: 8)
i32** %nbytes_in_lo32.addr: in stack slot 3 (size: 8)
i32** %nbytes_out_hi32.addr: in stack slot 6 (size: 8)
i32** %nbytes_out_lo32.addr: in stack slot 5 (size: 8)
i32* %ret: in stack slot 9 (size: 4)

Duplicate operand locations:


Stackmap 3:
  STACKMAP 3, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, 0, <fi#9>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4)

i32* %abandon.addr: in stack slot 2 (size: 4)
i32** %bzerror.addr: in stack slot 0 (size: 8)
%struct.bzFile** %bzf: in stack slot 10 (size: 8)
i32* %n: in stack slot 7 (size: 4)
i32* %n2: in stack slot 8 (size: 4)
i32** %nbytes_in_hi32.addr: in stack slot 4 (size: 8)
i32** %nbytes_in_lo32.addr: in stack slot 3 (size: 8)
i32** %nbytes_out_hi32.addr: in stack slot 6 (size: 8)
i32** %nbytes_out_lo32.addr: in stack slot 5 (size: 8)
i32* %ret: in stack slot 9 (size: 4)

Duplicate operand locations:


Stackmap 4:
  STACKMAP 4, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, 0, <fi#9>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4)

i32* %abandon.addr: in stack slot 2 (size: 4)
i32** %bzerror.addr: in stack slot 0 (size: 8)
%struct.bzFile** %bzf: in stack slot 10 (size: 8)
i32* %n: in stack slot 7 (size: 4)
i32* %n2: in stack slot 8 (size: 4)
i32** %nbytes_in_hi32.addr: in stack slot 4 (size: 8)
i32** %nbytes_in_lo32.addr: in stack slot 3 (size: 8)
i32** %nbytes_out_hi32.addr: in stack slot 6 (size: 8)
i32** %nbytes_out_lo32.addr: in stack slot 5 (size: 8)
i32* %ret: in stack slot 9 (size: 4)

Duplicate operand locations:


Stackmap 5:
  STACKMAP 5, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5]

i32** %bzerror.addr: in stack slot 0 (size: 8)
%struct.bzFile** %bzf: in stack slot 10 (size: 8)
i32** %nbytes_in_hi32.addr: in stack slot 4 (size: 8)
i32** %nbytes_in_lo32.addr: in stack slot 3 (size: 8)
i32** %nbytes_out_hi32.addr: in stack slot 6 (size: 8)
i32** %nbytes_out_lo32.addr: in stack slot 5 (size: 8)

Duplicate operand locations:


Stackmap 6:
  STACKMAP 6, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5]

i32** %bzerror.addr: in stack slot 0 (size: 8)
%struct.bzFile** %bzf: in stack slot 10 (size: 8)
i32** %nbytes_in_hi32.addr: in stack slot 4 (size: 8)
i32** %nbytes_in_lo32.addr: in stack slot 3 (size: 8)
i32** %nbytes_out_hi32.addr: in stack slot 6 (size: 8)
i32** %nbytes_out_lo32.addr: in stack slot 5 (size: 8)

Duplicate operand locations:


Stackmap 7:
  STACKMAP 7, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5]

i32** %bzerror.addr: in stack slot 0 (size: 8)
%struct.bzFile** %bzf: in stack slot 10 (size: 8)
i32** %nbytes_in_hi32.addr: in stack slot 4 (size: 8)
i32** %nbytes_in_lo32.addr: in stack slot 3 (size: 8)
i32** %nbytes_out_hi32.addr: in stack slot 6 (size: 8)
i32** %nbytes_out_lo32.addr: in stack slot 5 (size: 8)

Duplicate operand locations:


Stackmap 8:
  STACKMAP 8, 0, 0, <fi#10>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack10]

%struct.bzFile** %bzf: in stack slot 10 (size: 8)

Duplicate operand locations:


Stackmap 9:
  STACKMAP 9, 0, %LR<earlyclobber,imp-def,dead>, ...


Duplicate operand locations:


Stackmap 10:
  STACKMAP 10, 0, %LR<earlyclobber,imp-def,dead>, ...


Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, %vreg5, 0, <fi#2>, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, %vreg9, 0, <fi#4>, 0, %vreg7, 0, <fi#3>, 0, %vreg13, 0, <fi#6>, 0, %vreg11, 0, <fi#5>, 0, 0, <fi#9>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4) GPR32:%vreg5 GPR64:%vreg3,%vreg1,%vreg9,%vreg7,%vreg13,%vreg11
  -> Call instruction SlotIndex 368B, searching vregs 0 -> 258 and stack slots 0 -> 11
    + vreg23 is live in register but not in stackmap
      Defining instruction: %vreg23<def> = COPY %LR; GPR64:%vreg23
      Value: generated value, 1 instruction(s)

  STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, 0, <fi#9>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4)
  -> Call instruction SlotIndex 1312B, searching vregs 0 -> 258 and stack slots 0 -> 11
    + vreg23 is live in register but not in stackmap
      Defining instruction: %vreg23<def> = COPY %LR; GPR64:%vreg23
      Value: generated value, 1 instruction(s)

  STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, 0, <fi#9>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4)
  -> Call instruction SlotIndex 2448B, searching vregs 0 -> 258 and stack slots 0 -> 11
    + vreg23 is live in register but not in stackmap
      Defining instruction: %vreg23<def> = COPY %LR; GPR64:%vreg23
      Value: generated value, 1 instruction(s)

  STACKMAP 3, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, 0, <fi#9>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4)
  -> Call instruction SlotIndex 3296B, searching vregs 0 -> 258 and stack slots 0 -> 11
    + vreg23 is live in register but not in stackmap
      Defining instruction: %vreg23<def> = COPY %LR; GPR64:%vreg23
      Value: generated value, 1 instruction(s)

  STACKMAP 4, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, 0, <fi#9>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4)
  -> Call instruction SlotIndex 3568B, searching vregs 0 -> 258 and stack slots 0 -> 11
    + vreg23 is live in register but not in stackmap
      Defining instruction: %vreg23<def> = COPY %LR; GPR64:%vreg23
      Value: generated value, 1 instruction(s)

  STACKMAP 5, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5]
  -> Call instruction SlotIndex 4256B, searching vregs 0 -> 258 and stack slots 0 -> 11
    + vreg23 is live in register but not in stackmap
      Defining instruction: %vreg23<def> = COPY %LR; GPR64:%vreg23
      Value: generated value, 1 instruction(s)

  STACKMAP 6, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5]
  -> Call instruction SlotIndex 4448B, searching vregs 0 -> 258 and stack slots 0 -> 11
    + vreg23 is live in register but not in stackmap
      Defining instruction: %vreg23<def> = COPY %LR; GPR64:%vreg23
      Value: generated value, 1 instruction(s)

  STACKMAP 7, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5]
  -> Call instruction SlotIndex 4608B, searching vregs 0 -> 258 and stack slots 0 -> 11
    + vreg23 is live in register but not in stackmap
      Defining instruction: %vreg23<def> = COPY %LR; GPR64:%vreg23
      Value: generated value, 1 instruction(s)

  STACKMAP 8, 0, 0, <fi#10>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack10]
  -> Call instruction SlotIndex 5808B, searching vregs 0 -> 258 and stack slots 0 -> 11
    + vreg23 is live in register but not in stackmap
      Defining instruction: %vreg23<def> = COPY %LR; GPR64:%vreg23
      Value: generated value, 1 instruction(s)

  STACKMAP 9, 0, %LR<earlyclobber,imp-def,dead>, ...
  -> Call instruction SlotIndex 5968B, searching vregs 0 -> 258 and stack slots 0 -> 11
    + vreg23 is live in register but not in stackmap
      Defining instruction: %vreg23<def> = COPY %LR; GPR64:%vreg23
      Value: generated value, 1 instruction(s)

  STACKMAP 10, 0, %LR<earlyclobber,imp-def,dead>, ...
  -> Call instruction SlotIndex 6176B, searching vregs 0 -> 258 and stack slots 0 -> 11

********** REWRITE VIRTUAL REGISTERS **********
********** Function: BZ2_bzWriteClose64
********** REGISTER MAP **********
[%vreg1 -> %X26] GPR64
[%vreg3 -> %X25] GPR64
[%vreg5 -> %W24] GPR32
[%vreg7 -> %X23] GPR64
[%vreg9 -> %X22] GPR64
[%vreg11 -> %X21] GPR64
[%vreg13 -> %X20] GPR64
[%vreg15 -> %X8] GPR64
[%vreg18 -> %X8] GPR64
[%vreg20 -> %X8] GPR64common
[%vreg22 -> %X0] GPR64sp
[%vreg23 -> %X19] GPR64
[%vreg26 -> %W8] GPR32
[%vreg28 -> %X9] GPR64
[%vreg29 -> %X8] GPR64common
[%vreg30 -> %W8] GPR32
[%vreg31 -> %X8] GPR64
[%vreg33 -> %X8] GPR64
[%vreg34 -> %W9] GPR32
[%vreg36 -> %X8] GPR64common
[%vreg38 -> %X8] GPR64
[%vreg39 -> %W9] GPR32
[%vreg41 -> %X8] GPR64common
[%vreg44 -> %W0] GPR32
[%vreg46 -> %X0] GPR64
[%vreg47 -> %X8] GPR64common
[%vreg49 -> %X8] GPR64
[%vreg51 -> %X8] GPR64common
[%vreg53 -> %X8] GPR64
[%vreg55 -> %X8] GPR64common
[%vreg57 -> %X8] GPR64
[%vreg59 -> %X8] GPR64common
[%vreg61 -> %X8] GPR64
[%vreg63 -> %X8] GPR64common
[%vreg65 -> %W8] GPR32
[%vreg68 -> %W8] GPR32
[%vreg69 -> %X8] GPR64common
[%vreg71 -> %W8] GPR32common
[%vreg75 -> %W0] GPR32
[%vreg77 -> %X9] GPR64
[%vreg78 -> %X0] GPR64
[%vreg79 -> %X8] GPR64
[%vreg82 -> %X9] GPR64common
[%vreg85 -> %X8] GPR64common
[%vreg86 -> %X8] GPR64common
[%vreg87 -> %W9] GPR32
[%vreg89 -> %X8] GPR64common
[%vreg91 -> %W8] GPR32common
[%vreg93 -> %W9] GPR32
[%vreg95 -> %W8] GPR32
[%vreg96 -> %X8] GPR64common
[%vreg99 -> %W9] GPR32
[%vreg100 -> %W8] GPR32
[%vreg108 -> %X0] GPR64
[%vreg110 -> %X3] GPR64
[%vreg111 -> %X8] GPR64common
[%vreg115 -> %X2] GPR64
[%vreg118 -> %X0] GPR64sp
[%vreg119 -> %X9] GPR64common
[%vreg121 -> %W9] GPR32
[%vreg123 -> %W8] GPR32
[%vreg125 -> %W8] GPR32
[%vreg126 -> %X8] GPR64common
[%vreg129 -> %W0] GPR32
[%vreg131 -> %X0] GPR64
[%vreg132 -> %X8] GPR64common
[%vreg134 -> %W8] GPR32common
[%vreg136 -> %X8] GPR64
[%vreg137 -> %W9] GPR32
[%vreg139 -> %X8] GPR64common
[%vreg141 -> %X8] GPR64
[%vreg142 -> %W9] GPR32
[%vreg144 -> %X8] GPR64common
[%vreg146 -> %X8] GPR64
[%vreg149 -> %X9] GPR64common
[%vreg150 -> %W8] GPR32
[%vreg152 -> %X8] GPR64
[%vreg155 -> %X9] GPR64common
[%vreg156 -> %W8] GPR32
[%vreg158 -> %W8] GPR32
[%vreg161 -> %W0] GPR32
[%vreg163 -> %X0] GPR64
[%vreg164 -> %X8] GPR64common
[%vreg167 -> %W0] GPR32
[%vreg169 -> %X0] GPR64
[%vreg170 -> %X8] GPR64common
[%vreg172 -> %W0] GPR32all
[%vreg174 -> %X0] GPR64
[%vreg175 -> %X8] GPR64common
[%vreg177 -> %X8] GPR64
[%vreg178 -> %W9] GPR32
[%vreg180 -> %X8] GPR64common
[%vreg182 -> %X8] GPR64
[%vreg183 -> %W9] GPR32
[%vreg185 -> %X8] GPR64common
[%vreg187 -> %X8] GPR64
[%vreg190 -> %X9] GPR64common
[%vreg192 -> %W8] GPR32
[%vreg193 -> %X8] GPR64common
[%vreg195 -> %X8] GPR64
[%vreg198 -> %X9] GPR64common
[%vreg200 -> %W8] GPR32
[%vreg201 -> %X8] GPR64common
[%vreg203 -> %X8] GPR64
[%vreg206 -> %X9] GPR64common
[%vreg208 -> %W8] GPR32
[%vreg209 -> %X8] GPR64common
[%vreg211 -> %X8] GPR64
[%vreg214 -> %X9] GPR64common
[%vreg216 -> %W8] GPR32
[%vreg217 -> %X8] GPR64common
[%vreg219 -> %X8] GPR64
[%vreg221 -> %X8] GPR64common
[%vreg223 -> %X8] GPR64
[%vreg225 -> %X8] GPR64common
[%vreg228 -> %X0] GPR64
[%vreg231 -> %W0] GPR32all
[%vreg233 -> %X9] GPR64
[%vreg234 -> %X0] GPR64
[%vreg235 -> %X8] GPR64
[%vreg237 -> %X8] GPR64
[%vreg238 -> %W9] GPR32
[%vreg240 -> %X8] GPR64common
[%vreg242 -> %X8] GPR64
[%vreg243 -> %W9] GPR32
[%vreg245 -> %X8] GPR64common
[%vreg247 -> %X8] GPR64
[%vreg249 -> %X8] GPR64common
[%vreg251 -> %X8] GPR64
[%vreg253 -> %X8] GPR64common
[%vreg254 -> %X8] GPR64common
[%vreg256 -> %X0] GPR64sp

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %LR %W2 %X0 %X1 %X3 %X4 %X5 %X6
16B		%vreg23<def> = COPY %LR; GPR64:%vreg23
32B		%vreg13<def> = COPY %X6; GPR64:%vreg13
48B		%vreg11<def> = COPY %X5; GPR64:%vreg11
64B		%vreg9<def> = COPY %X4; GPR64:%vreg9
80B		%vreg7<def> = COPY %X3; GPR64:%vreg7
96B		%vreg5<def> = COPY %W2; GPR32:%vreg5
112B		%vreg3<def> = COPY %X1; GPR64:%vreg3
128B		%vreg1<def> = COPY %X0; GPR64:%vreg1
256B		%vreg20<def> = ADRP <ga:@BZ2_bzWriteClose64>[TF=1]; GPR64common:%vreg20
272B		%vreg22<def> = ADDXri %vreg20<kill>, <ga:@BZ2_bzWriteClose64>[TF=34], 0; GPR64sp:%vreg22 GPR64common:%vreg20
320B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
336B		%X0<def> = COPY %vreg22<kill>; GPR64sp:%vreg22
352B		%X1<def> = COPY %vreg23; GPR64:%vreg23
368B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
384B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
400B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
416B		STACKMAP 0, 0, %vreg5, 0, <fi#2>, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, %vreg9, 0, <fi#4>, 0, %vreg7, 0, <fi#3>, 0, %vreg13, 0, <fi#6>, 0, %vreg11, 0, <fi#5>, 0, 0, <fi#9>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4) GPR32:%vreg5 GPR64:%vreg3,%vreg1,%vreg9,%vreg7,%vreg13,%vreg11
432B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
448B		STRXui %vreg1<kill>, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg1
464B		STRXui %vreg3<kill>, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg3
480B		STRWui %vreg5<kill>, <fi#2>, 0; mem:ST4[FixedStack2] GPR32:%vreg5
496B		STRXui %vreg7<kill>, <fi#3>, 0; mem:ST8[FixedStack3] GPR64:%vreg7
512B		STRXui %vreg9<kill>, <fi#4>, 0; mem:ST8[FixedStack4] GPR64:%vreg9
528B		STRXui %vreg11<kill>, <fi#5>, 0; mem:ST8[FixedStack5] GPR64:%vreg11
544B		STRXui %vreg13<kill>, <fi#6>, 0; mem:ST8[FixedStack6] GPR64:%vreg13
560B		%vreg18<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg18
592B		STRXui %vreg18<kill>, <fi#10>, 0; mem:ST8[FixedStack10] GPR64:%vreg18
608B		%vreg15<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg15
624B		CBNZX %vreg15<kill>, <BB#6>; GPR64:%vreg15
	    Successors according to CFG: BB#6 BB#1
> %X19<def> = COPY %LR
> %X20<def> = COPY %X6
> %X21<def> = COPY %X5
> %X22<def> = COPY %X4
> %X23<def> = COPY %X3
> %W24<def> = COPY %W2
> %X25<def> = COPY %X1
> %X26<def> = COPY %X0
> %X8<def> = ADRP <ga:@BZ2_bzWriteClose64>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@BZ2_bzWriteClose64>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19
> BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 0, 0, %W24, 0, <fi#2>, 0, %X25, 0, <fi#1>, 0, %X26, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, %X22, 0, <fi#4>, 0, %X23, 0, <fi#3>, 0, %X20, 0, <fi#6>, 0, %X21, 0, <fi#5>, 0, 0, <fi#9>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRXui %X26<kill>, <fi#0>, 0; mem:ST8[FixedStack0]
> STRXui %X25<kill>, <fi#1>, 0; mem:ST8[FixedStack1]
> STRWui %W24<kill>, <fi#2>, 0; mem:ST4[FixedStack2]
> STRXui %X23<kill>, <fi#3>, 0; mem:ST8[FixedStack3]
> STRXui %X22<kill>, <fi#4>, 0; mem:ST8[FixedStack4]
> STRXui %X21<kill>, <fi#5>, 0; mem:ST8[FixedStack5]
> STRXui %X20<kill>, <fi#6>, 0; mem:ST8[FixedStack6]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRXui %X8<kill>, <fi#10>, 0; mem:ST8[FixedStack10]
> %X8<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10]
> CBNZX %X8<kill>, <BB#6>
640B	BB#1: derived from LLVM BB %if.then
	    Live Ins: %X19
	    Predecessors according to CFG: BB#0
656B		%vreg247<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg247
672B		CBZX %vreg247<kill>, <BB#3>; GPR64:%vreg247
	    Successors according to CFG: BB#3 BB#2
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> CBZX %X8<kill>, <BB#3>
688B	BB#2: derived from LLVM BB %if.then.2
	    Live Ins: %X19
	    Predecessors according to CFG: BB#1
704B		%vreg249<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg249
720B		STRWui %WZR, %vreg249<kill>, 0; mem:ST4[%4] GPR64common:%vreg249
	    Successors according to CFG: BB#3
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> STRWui %WZR, %X8<kill>, 0; mem:ST4[%4]
736B	BB#3: derived from LLVM BB %if.end
	    Live Ins: %X19
	    Predecessors according to CFG: BB#1 BB#2
752B		%vreg251<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg251
768B		CBZX %vreg251<kill>, <BB#5>; GPR64:%vreg251
	    Successors according to CFG: BB#5 BB#4
> %X8<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10]
> CBZX %X8<kill>, <BB#5>
784B	BB#4: derived from LLVM BB %if.then.4
	    Live Ins: %X19
	    Predecessors according to CFG: BB#3
800B		%vreg253<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg253
816B		STRWui %WZR, %vreg253<kill>, 1274; mem:ST4[%lastErr] GPR64common:%vreg253
	    Successors according to CFG: BB#5
> %X8<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10]
> STRWui %WZR, %X8<kill>, 1274; mem:ST4[%lastErr]
832B	BB#5: derived from LLVM BB %if.end.5
	    Live Ins: %X19
	    Predecessors according to CFG: BB#3 BB#4
848B		B <BB#71>
	    Successors according to CFG: BB#71
> B <BB#71>
864B	BB#6: derived from LLVM BB %if.end.6
	    Live Ins: %X19
	    Predecessors according to CFG: BB#0
880B		%vreg31<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg31
896B		%vreg28<def> = MOVi64imm 5012; GPR64:%vreg28
912B		%vreg29<def> = ADDXrr %vreg31<kill>, %vreg28<kill>; GPR64common:%vreg29 GPR64:%vreg31,%vreg28
928B		%vreg30<def> = LDRBBui %vreg29<kill>, 0; mem:LD1[%writing] GPR32:%vreg30 GPR64common:%vreg29
944B		%vreg26<def> = UBFMWri %vreg30<kill>, 0, 7; GPR32:%vreg26,%vreg30
960B		CBNZW %vreg26<kill>, <BB#12>; GPR32:%vreg26
	    Successors according to CFG: BB#12 BB#7
> %X8<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10]
> %X9<def> = MOVi64imm 5012
> %X8<def> = ADDXrr %X8<kill>, %X9<kill>
> %W8<def> = LDRBBui %X8<kill>, 0; mem:LD1[%writing]
> %W8<def> = UBFMWri %W8<kill>, 0, 7
> CBNZW %W8<kill>, <BB#12>
976B	BB#7: derived from LLVM BB %if.then.7
	    Live Ins: %X19
	    Predecessors according to CFG: BB#6
992B		%vreg33<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg33
1008B		CBZX %vreg33<kill>, <BB#9>; GPR64:%vreg33
	    Successors according to CFG: BB#9 BB#8
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> CBZX %X8<kill>, <BB#9>
1024B	BB#8: derived from LLVM BB %if.then.9
	    Live Ins: %X19
	    Predecessors according to CFG: BB#7
1056B		%vreg36<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg36
1064B		%vreg34<def> = MOVi32imm 4294967295; GPR32:%vreg34
1072B		STRWui %vreg34<kill>, %vreg36<kill>, 0; mem:ST4[%10] GPR32:%vreg34 GPR64common:%vreg36
	    Successors according to CFG: BB#9
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %W9<def> = MOVi32imm 4294967295
> STRWui %W9<kill>, %X8<kill>, 0; mem:ST4[%10]
1088B	BB#9: derived from LLVM BB %if.end.10
	    Live Ins: %X19
	    Predecessors according to CFG: BB#7 BB#8
1104B		%vreg38<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg38
1120B		CBZX %vreg38<kill>, <BB#11>; GPR64:%vreg38
	    Successors according to CFG: BB#11 BB#10
> %X8<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10]
> CBZX %X8<kill>, <BB#11>
1136B	BB#10: derived from LLVM BB %if.then.12
	    Live Ins: %X19
	    Predecessors according to CFG: BB#9
1168B		%vreg41<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg41
1176B		%vreg39<def> = MOVi32imm 4294967295; GPR32:%vreg39
1184B		STRWui %vreg39<kill>, %vreg41<kill>, 1274; mem:ST4[%lastErr13] GPR32:%vreg39 GPR64common:%vreg41
	    Successors according to CFG: BB#11
> %X8<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10]
> %W9<def> = MOVi32imm 4294967295
> STRWui %W9<kill>, %X8<kill>, 1274; mem:ST4[%lastErr13]
1200B	BB#11: derived from LLVM BB %if.end.14
	    Live Ins: %X19
	    Predecessors according to CFG: BB#9 BB#10
1216B		B <BB#71>
	    Successors according to CFG: BB#71
> B <BB#71>
1232B	BB#12: derived from LLVM BB %if.end.15
	    Live Ins: %X19
	    Predecessors according to CFG: BB#6
1248B		%vreg47<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg47
1264B		%vreg46<def> = LDRXui %vreg47<kill>, 0; mem:LD8[%handle] GPR64:%vreg46 GPR64common:%vreg47
1280B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1296B		%X0<def> = COPY %vreg46<kill>; GPR64:%vreg46
1312B		BL <ga:@ferror>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
1328B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1344B		%vreg44<def> = COPY %W0; GPR32:%vreg44
1360B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1376B		STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, 0, <fi#9>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4)
1392B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1408B		CBZW %vreg44<kill>, <BB#18>; GPR32:%vreg44
	    Successors according to CFG: BB#18 BB#13
> %X8<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10]
> %X0<def> = LDRXui %X8<kill>, 0; mem:LD8[%handle]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BL <ga:@ferror>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = COPY %W0
Deleting identity copy.
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, 0, <fi#9>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> CBZW %W0<kill>, <BB#18>
1424B	BB#13: derived from LLVM BB %if.then.17
	    Live Ins: %X19
	    Predecessors according to CFG: BB#12
1440B		%vreg237<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg237
1456B		CBZX %vreg237<kill>, <BB#15>; GPR64:%vreg237
	    Successors according to CFG: BB#15 BB#14
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> CBZX %X8<kill>, <BB#15>
1472B	BB#14: derived from LLVM BB %if.then.19
	    Live Ins: %X19
	    Predecessors according to CFG: BB#13
1504B		%vreg240<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg240
1512B		%vreg238<def> = MOVi32imm 4294967290; GPR32:%vreg238
1520B		STRWui %vreg238<kill>, %vreg240<kill>, 0; mem:ST4[%16] GPR32:%vreg238 GPR64common:%vreg240
	    Successors according to CFG: BB#15
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %W9<def> = MOVi32imm 4294967290
> STRWui %W9<kill>, %X8<kill>, 0; mem:ST4[%16]
1536B	BB#15: derived from LLVM BB %if.end.20
	    Live Ins: %X19
	    Predecessors according to CFG: BB#13 BB#14
1552B		%vreg242<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg242
1568B		CBZX %vreg242<kill>, <BB#17>; GPR64:%vreg242
	    Successors according to CFG: BB#17 BB#16
> %X8<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10]
> CBZX %X8<kill>, <BB#17>
1584B	BB#16: derived from LLVM BB %if.then.22
	    Live Ins: %X19
	    Predecessors according to CFG: BB#15
1616B		%vreg245<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg245
1624B		%vreg243<def> = MOVi32imm 4294967290; GPR32:%vreg243
1632B		STRWui %vreg243<kill>, %vreg245<kill>, 1274; mem:ST4[%lastErr23] GPR32:%vreg243 GPR64common:%vreg245
	    Successors according to CFG: BB#17
> %X8<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10]
> %W9<def> = MOVi32imm 4294967290
> STRWui %W9<kill>, %X8<kill>, 1274; mem:ST4[%lastErr23]
1648B	BB#17: derived from LLVM BB %if.end.24
	    Live Ins: %X19
	    Predecessors according to CFG: BB#15 BB#16
1664B		B <BB#71>
	    Successors according to CFG: BB#71
> B <BB#71>
1680B	BB#18: derived from LLVM BB %if.end.25
	    Live Ins: %X19
	    Predecessors according to CFG: BB#12
1696B		%vreg49<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg49
1712B		CBZX %vreg49<kill>, <BB#20>; GPR64:%vreg49
	    Successors according to CFG: BB#20 BB#19
> %X8<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> CBZX %X8<kill>, <BB#20>
1728B	BB#19: derived from LLVM BB %if.then.27
	    Live Ins: %X19
	    Predecessors according to CFG: BB#18
1744B		%vreg51<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg51
1760B		STRWui %WZR, %vreg51<kill>, 0; mem:ST4[%20] GPR64common:%vreg51
	    Successors according to CFG: BB#20
> %X8<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> STRWui %WZR, %X8<kill>, 0; mem:ST4[%20]
1776B	BB#20: derived from LLVM BB %if.end.28
	    Live Ins: %X19
	    Predecessors according to CFG: BB#18 BB#19
1792B		%vreg53<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64:%vreg53
1808B		CBZX %vreg53<kill>, <BB#22>; GPR64:%vreg53
	    Successors according to CFG: BB#22 BB#21
> %X8<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4]
> CBZX %X8<kill>, <BB#22>
1824B	BB#21: derived from LLVM BB %if.then.30
	    Live Ins: %X19
	    Predecessors according to CFG: BB#20
1840B		%vreg55<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg55
1856B		STRWui %WZR, %vreg55<kill>, 0; mem:ST4[%22] GPR64common:%vreg55
	    Successors according to CFG: BB#22
> %X8<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4]
> STRWui %WZR, %X8<kill>, 0; mem:ST4[%22]
1872B	BB#22: derived from LLVM BB %if.end.31
	    Live Ins: %X19
	    Predecessors according to CFG: BB#20 BB#21
1888B		%vreg57<def> = LDRXui <fi#5>, 0; mem:LD8[FixedStack5] GPR64:%vreg57
1904B		CBZX %vreg57<kill>, <BB#24>; GPR64:%vreg57
	    Successors according to CFG: BB#24 BB#23
> %X8<def> = LDRXui <fi#5>, 0; mem:LD8[FixedStack5]
> CBZX %X8<kill>, <BB#24>
1920B	BB#23: derived from LLVM BB %if.then.33
	    Live Ins: %X19
	    Predecessors according to CFG: BB#22
1936B		%vreg59<def> = LDRXui <fi#5>, 0; mem:LD8[FixedStack5] GPR64common:%vreg59
1952B		STRWui %WZR, %vreg59<kill>, 0; mem:ST4[%24] GPR64common:%vreg59
	    Successors according to CFG: BB#24
> %X8<def> = LDRXui <fi#5>, 0; mem:LD8[FixedStack5]
> STRWui %WZR, %X8<kill>, 0; mem:ST4[%24]
1968B	BB#24: derived from LLVM BB %if.end.34
	    Live Ins: %X19
	    Predecessors according to CFG: BB#22 BB#23
1984B		%vreg61<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64:%vreg61
2000B		CBZX %vreg61<kill>, <BB#26>; GPR64:%vreg61
	    Successors according to CFG: BB#26 BB#25
> %X8<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6]
> CBZX %X8<kill>, <BB#26>
2016B	BB#25: derived from LLVM BB %if.then.36
	    Live Ins: %X19
	    Predecessors according to CFG: BB#24
2032B		%vreg63<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg63
2048B		STRWui %WZR, %vreg63<kill>, 0; mem:ST4[%26] GPR64common:%vreg63
	    Successors according to CFG: BB#26
> %X8<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6]
> STRWui %WZR, %X8<kill>, 0; mem:ST4[%26]
2064B	BB#26: derived from LLVM BB %if.end.37
	    Live Ins: %X19
	    Predecessors according to CFG: BB#24 BB#25
2080B		%vreg65<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg65
2096B		CBNZW %vreg65<kill>, <BB#49>; GPR32:%vreg65
	    Successors according to CFG: BB#49 BB#27
> %W8<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2]
> CBNZW %W8<kill>, <BB#49>
2112B	BB#27: derived from LLVM BB %land.lhs.true
	    Live Ins: %X19
	    Predecessors according to CFG: BB#26
2128B		%vreg69<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg69
2144B		%vreg68<def> = LDRWui %vreg69<kill>, 1274; mem:LD4[%lastErr39] GPR32:%vreg68 GPR64common:%vreg69
2160B		CBNZW %vreg68<kill>, <BB#49>; GPR32:%vreg68
	    Successors according to CFG: BB#49 BB#28
> %X8<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10]
> %W8<def> = LDRWui %X8<kill>, 1274; mem:LD4[%lastErr39]
> CBNZW %W8<kill>, <BB#49>
2176B	BB#28: derived from LLVM BB %if.then.41
	    Live Ins: %X19
	    Predecessors according to CFG: BB#27
2192B		B <BB#29>
	    Successors according to CFG: BB#29
> B <BB#29>
2208B	BB#29: derived from LLVM BB %while.body
	    Live Ins: %X19
	    Predecessors according to CFG: BB#28 BB#47
2256B		%vreg89<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg89
2264B		%vreg87<def> = MOVi32imm 5000; GPR32:%vreg87
2272B		STRWui %vreg87<kill>, %vreg89<kill>, 1262; mem:ST4[%avail_out] GPR32:%vreg87 GPR64common:%vreg89
2288B		%vreg86<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg86
2320B		%vreg82<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg82
2328B		%vreg85<def> = ADDXri %vreg86<kill>, 8, 0; GPR64common:%vreg85,%vreg86
2336B		STRXui %vreg85<kill>, %vreg82<kill>, 630; mem:ST8[%next_out] GPR64common:%vreg85,%vreg82
2352B		%vreg79<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg79
2368B		%vreg77<def> = MOVi64imm 5016; GPR64:%vreg77
2384B		%vreg78<def> = ADDXrr %vreg79<kill>, %vreg77<kill>; GPR64:%vreg78,%vreg79,%vreg77
2400B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2432B		%W1<def> = MOVi32imm 2
2440B		%X0<def> = COPY %vreg78<kill>; GPR64:%vreg78
2448B		BL <ga:@BZ2_bzCompress>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %W0<imp-def>
2464B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2480B		%vreg75<def> = COPY %W0; GPR32:%vreg75
2496B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2512B		STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, 0, <fi#9>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4)
2528B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2544B		STRWui %vreg75<kill>, <fi#9>, 0; mem:ST4[FixedStack9] GPR32:%vreg75
2560B		%vreg71<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32common:%vreg71
2576B		%WZR<def> = SUBSWri %vreg71<kill>, 3, 0, %NZCV<imp-def>; GPR32common:%vreg71
2592B		Bcc 0, <BB#36>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#36 BB#30
> %X8<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10]
> %W9<def> = MOVi32imm 5000
> STRWui %W9<kill>, %X8<kill>, 1262; mem:ST4[%avail_out]
> %X8<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10]
> %X9<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10]
> %X8<def> = ADDXri %X8<kill>, 8, 0
> STRXui %X8<kill>, %X9<kill>, 630; mem:ST8[%next_out]
> %X8<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10]
> %X9<def> = MOVi64imm 5016
> %X0<def> = ADDXrr %X8<kill>, %X9<kill>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %W1<def> = MOVi32imm 2
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BL <ga:@BZ2_bzCompress>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %W0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = COPY %W0
Deleting identity copy.
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, 0, <fi#9>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRWui %W0<kill>, <fi#9>, 0; mem:ST4[FixedStack9]
> %W8<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9]
> %WZR<def> = SUBSWri %W8<kill>, 3, 0, %NZCV<imp-def>
> Bcc 0, <BB#36>, %NZCV<imp-use,kill>
2608B	BB#30: derived from LLVM BB %land.lhs.true.46
	    Live Ins: %X19
	    Predecessors according to CFG: BB#29
2624B		%vreg91<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32common:%vreg91
2640B		%WZR<def> = SUBSWri %vreg91<kill>, 4, 0, %NZCV<imp-def>; GPR32common:%vreg91
2656B		Bcc 0, <BB#36>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#36 BB#31
> %W8<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9]
> %WZR<def> = SUBSWri %W8<kill>, 4, 0, %NZCV<imp-def>
> Bcc 0, <BB#36>, %NZCV<imp-use,kill>
2672B	BB#31: derived from LLVM BB %if.then.48
	    Live Ins: %X19
	    Predecessors according to CFG: BB#30
2688B		%vreg146<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg146
2704B		CBZX %vreg146<kill>, <BB#33>; GPR64:%vreg146
	    Successors according to CFG: BB#33 BB#32
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> CBZX %X8<kill>, <BB#33>
2720B	BB#32: derived from LLVM BB %if.then.50
	    Live Ins: %X19
	    Predecessors according to CFG: BB#31
2736B		%vreg150<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32:%vreg150
2752B		%vreg149<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg149
2768B		STRWui %vreg150<kill>, %vreg149<kill>, 0; mem:ST4[%38] GPR32:%vreg150 GPR64common:%vreg149
	    Successors according to CFG: BB#33
> %W8<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9]
> %X9<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> STRWui %W8<kill>, %X9<kill>, 0; mem:ST4[%38]
2784B	BB#33: derived from LLVM BB %if.end.51
	    Live Ins: %X19
	    Predecessors according to CFG: BB#31 BB#32
2800B		%vreg152<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg152
2816B		CBZX %vreg152<kill>, <BB#35>; GPR64:%vreg152
	    Successors according to CFG: BB#35 BB#34
> %X8<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10]
> CBZX %X8<kill>, <BB#35>
2832B	BB#34: derived from LLVM BB %if.then.53
	    Live Ins: %X19
	    Predecessors according to CFG: BB#33
2848B		%vreg156<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32:%vreg156
2864B		%vreg155<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg155
2880B		STRWui %vreg156<kill>, %vreg155<kill>, 1274; mem:ST4[%lastErr54] GPR32:%vreg156 GPR64common:%vreg155
	    Successors according to CFG: BB#35
> %W8<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9]
> %X9<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10]
> STRWui %W8<kill>, %X9<kill>, 1274; mem:ST4[%lastErr54]
2896B	BB#35: derived from LLVM BB %if.end.55
	    Live Ins: %X19
	    Predecessors according to CFG: BB#33 BB#34
2912B		B <BB#71>
	    Successors according to CFG: BB#71
> B <BB#71>
2928B	BB#36: derived from LLVM BB %if.end.56
	    Live Ins: %X19
	    Predecessors according to CFG: BB#29 BB#30
2960B		%vreg96<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg96
2976B		%vreg95<def> = LDRWui %vreg96<kill>, 1262; mem:LD4[%avail_out58] GPR32:%vreg95 GPR64common:%vreg96
2984B		%vreg93<def> = MOVi32imm 5000; GPR32:%vreg93
2992B		%WZR<def> = SUBSWrr %vreg95<kill>, %vreg93<kill>, %NZCV<imp-def>; GPR32:%vreg95,%vreg93
3008B		Bcc 2, <BB#45>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#45 BB#37
> %X8<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10]
> %W8<def> = LDRWui %X8<kill>, 1262; mem:LD4[%avail_out58]
> %W9<def> = MOVi32imm 5000
> %WZR<def> = SUBSWrr %W8<kill>, %W9<kill>, %NZCV<imp-def>
> Bcc 2, <BB#45>, %NZCV<imp-use,kill>
3024B	BB#37: derived from LLVM BB %if.then.60
	    Live Ins: %X19
	    Predecessors according to CFG: BB#36
3072B		%vreg126<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg126
3088B		%vreg125<def> = LDRWui %vreg126<kill>, 1262; mem:LD4[%avail_out62] GPR32:%vreg125 GPR64common:%vreg126
3096B		%vreg121<def> = MOVi32imm 5000; GPR32:%vreg121
3104B		%vreg123<def> = SUBWrr %vreg121<kill>, %vreg125<kill>; GPR32:%vreg123,%vreg121,%vreg125
3120B		STRWui %vreg123<kill>, <fi#7>, 0; mem:ST4[FixedStack7] GPR32:%vreg123
3184B		%vreg111<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg111
3188B		%vreg119<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg119
3192B		%vreg115<def> = LDRSWui <fi#7>, 0; mem:LD4[FixedStack7] GPR64:%vreg115
3200B		%vreg110<def> = LDRXui %vreg111<kill>, 0; mem:LD8[%handle65] GPR64:%vreg110 GPR64common:%vreg111
3208B		%vreg118<def> = ADDXri %vreg119<kill>, 8, 0; GPR64sp:%vreg118 GPR64common:%vreg119
3216B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3224B		%X1<def> = MOVi64imm 1
3232B		%X0<def> = COPY %vreg118<kill>; GPR64sp:%vreg118
3264B		%X2<def> = COPY %vreg115<kill>; GPR64:%vreg115
3280B		%X3<def> = COPY %vreg110<kill>; GPR64:%vreg110
3296B		BL <ga:@fwrite>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %X2<imp-use>, %X3<imp-use>, %X0<imp-def>
3312B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3328B		%vreg108<def> = COPY %X0; GPR64:%vreg108
3344B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3360B		STACKMAP 3, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, 0, <fi#9>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4)
3376B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3408B		STRWui %vreg108:sub_32<kill>, <fi#8>, 0; mem:ST4[FixedStack8] GPR64:%vreg108
3424B		%vreg100<def> = LDRWui <fi#7>, 0; mem:LD4[FixedStack7] GPR32:%vreg100
3440B		%vreg99<def> = LDRWui <fi#8>, 0; mem:LD4[FixedStack8] GPR32:%vreg99
3456B		%WZR<def> = SUBSWrr %vreg100<kill>, %vreg99<kill>, %NZCV<imp-def>; GPR32:%vreg100,%vreg99
3472B		Bcc 1, <BB#39>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#39 BB#38
> %X8<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10]
> %W8<def> = LDRWui %X8<kill>, 1262; mem:LD4[%avail_out62]
> %W9<def> = MOVi32imm 5000
> %W8<def> = SUBWrr %W9<kill>, %W8<kill>
> STRWui %W8<kill>, <fi#7>, 0; mem:ST4[FixedStack7]
> %X8<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10]
> %X9<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10]
> %X2<def> = LDRSWui <fi#7>, 0; mem:LD4[FixedStack7]
> %X3<def> = LDRXui %X8<kill>, 0; mem:LD8[%handle65]
> %X0<def> = ADDXri %X9<kill>, 8, 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X1<def> = MOVi64imm 1
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X2<def> = COPY %X2<kill>
Deleting identity copy.
> %X3<def> = COPY %X3<kill>
Deleting identity copy.
> BL <ga:@fwrite>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %X2<imp-use>, %X3<imp-use>, %X0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0
Deleting identity copy.
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 3, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, 0, <fi#9>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRWui %W0, <fi#8>, 0, %X0<imp-use,kill>; mem:ST4[FixedStack8]
> %W8<def> = LDRWui <fi#7>, 0; mem:LD4[FixedStack7]
> %W9<def> = LDRWui <fi#8>, 0; mem:LD4[FixedStack8]
> %WZR<def> = SUBSWrr %W8<kill>, %W9<kill>, %NZCV<imp-def>
> Bcc 1, <BB#39>, %NZCV<imp-use,kill>
3488B	BB#38: derived from LLVM BB %lor.lhs.false
	    Live Ins: %X19
	    Predecessors according to CFG: BB#37
3504B		%vreg132<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg132
3520B		%vreg131<def> = LDRXui %vreg132<kill>, 0; mem:LD8[%handle70] GPR64:%vreg131 GPR64common:%vreg132
3536B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3552B		%X0<def> = COPY %vreg131<kill>; GPR64:%vreg131
3568B		BL <ga:@ferror>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
3584B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3600B		%vreg129<def> = COPY %W0; GPR32:%vreg129
3616B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3632B		STACKMAP 4, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, 0, <fi#9>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4)
3648B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3664B		CBZW %vreg129<kill>, <BB#44>; GPR32:%vreg129
	    Successors according to CFG: BB#44 BB#39
> %X8<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10]
> %X0<def> = LDRXui %X8<kill>, 0; mem:LD8[%handle70]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BL <ga:@ferror>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = COPY %W0
Deleting identity copy.
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 4, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, 0, <fi#9>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> CBZW %W0<kill>, <BB#44>
3680B	BB#39: derived from LLVM BB %if.then.73
	    Live Ins: %X19
	    Predecessors according to CFG: BB#37 BB#38
3696B		%vreg136<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg136
3712B		CBZX %vreg136<kill>, <BB#41>; GPR64:%vreg136
	    Successors according to CFG: BB#41 BB#40
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> CBZX %X8<kill>, <BB#41>
3728B	BB#40: derived from LLVM BB %if.then.76
	    Live Ins: %X19
	    Predecessors according to CFG: BB#39
3760B		%vreg139<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg139
3768B		%vreg137<def> = MOVi32imm 4294967290; GPR32:%vreg137
3776B		STRWui %vreg137<kill>, %vreg139<kill>, 0; mem:ST4[%55] GPR32:%vreg137 GPR64common:%vreg139
	    Successors according to CFG: BB#41
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %W9<def> = MOVi32imm 4294967290
> STRWui %W9<kill>, %X8<kill>, 0; mem:ST4[%55]
3792B	BB#41: derived from LLVM BB %if.end.77
	    Live Ins: %X19
	    Predecessors according to CFG: BB#39 BB#40
3808B		%vreg141<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg141
3824B		CBZX %vreg141<kill>, <BB#43>; GPR64:%vreg141
	    Successors according to CFG: BB#43 BB#42
> %X8<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10]
> CBZX %X8<kill>, <BB#43>
3840B	BB#42: derived from LLVM BB %if.then.80
	    Live Ins: %X19
	    Predecessors according to CFG: BB#41
3872B		%vreg144<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg144
3880B		%vreg142<def> = MOVi32imm 4294967290; GPR32:%vreg142
3888B		STRWui %vreg142<kill>, %vreg144<kill>, 1274; mem:ST4[%lastErr81] GPR32:%vreg142 GPR64common:%vreg144
	    Successors according to CFG: BB#43
> %X8<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10]
> %W9<def> = MOVi32imm 4294967290
> STRWui %W9<kill>, %X8<kill>, 1274; mem:ST4[%lastErr81]
3904B	BB#43: derived from LLVM BB %if.end.82
	    Live Ins: %X19
	    Predecessors according to CFG: BB#41 BB#42
3920B		B <BB#71>
	    Successors according to CFG: BB#71
> B <BB#71>
3936B	BB#44: derived from LLVM BB %if.end.83
	    Live Ins: %X19
	    Predecessors according to CFG: BB#38
3952B		B <BB#45>
	    Successors according to CFG: BB#45
> B <BB#45>
3968B	BB#45: derived from LLVM BB %if.end.84
	    Live Ins: %X19
	    Predecessors according to CFG: BB#36 BB#44
3984B		%vreg134<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32common:%vreg134
4000B		%WZR<def> = SUBSWri %vreg134<kill>, 4, 0, %NZCV<imp-def>; GPR32common:%vreg134
4016B		Bcc 1, <BB#47>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#47 BB#46
> %W8<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9]
> %WZR<def> = SUBSWri %W8<kill>, 4, 0, %NZCV<imp-def>
> Bcc 1, <BB#47>, %NZCV<imp-use,kill>
4032B	BB#46: derived from LLVM BB %if.then.87
	    Live Ins: %X19
	    Predecessors according to CFG: BB#45
4048B		B <BB#48>
	    Successors according to CFG: BB#48
> B <BB#48>
4064B	BB#47: derived from LLVM BB %if.end.88
	    Live Ins: %X19
	    Predecessors according to CFG: BB#45
4080B		B <BB#29>
	    Successors according to CFG: BB#29
> B <BB#29>
4096B	BB#48: derived from LLVM BB %while.end
	    Live Ins: %X19
	    Predecessors according to CFG: BB#46
4112B		B <BB#49>
	    Successors according to CFG: BB#49
> B <BB#49>
4128B	BB#49: derived from LLVM BB %if.end.89
	    Live Ins: %X19
	    Predecessors according to CFG: BB#26 BB#27 BB#48
4144B		%vreg158<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg158
4160B		CBNZW %vreg158<kill>, <BB#58>; GPR32:%vreg158
	    Successors according to CFG: BB#58 BB#50
> %W8<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2]
> CBNZW %W8<kill>, <BB#58>
4176B	BB#50: derived from LLVM BB %land.lhs.true.91
	    Live Ins: %X19
	    Predecessors according to CFG: BB#49
4192B		%vreg164<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg164
4208B		%vreg163<def> = LDRXui %vreg164<kill>, 0; mem:LD8[%handle92] GPR64:%vreg163 GPR64common:%vreg164
4224B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4240B		%X0<def> = COPY %vreg163<kill>; GPR64:%vreg163
4256B		BL <ga:@ferror>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
4272B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4288B		%vreg161<def> = COPY %W0; GPR32:%vreg161
4304B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4320B		STACKMAP 5, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5]
4336B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4352B		CBNZW %vreg161<kill>, <BB#58>; GPR32:%vreg161
	    Successors according to CFG: BB#58 BB#51
> %X8<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10]
> %X0<def> = LDRXui %X8<kill>, 0; mem:LD8[%handle92]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BL <ga:@ferror>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = COPY %W0
Deleting identity copy.
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 5, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> CBNZW %W0<kill>, <BB#58>
4368B	BB#51: derived from LLVM BB %if.then.95
	    Live Ins: %X19
	    Predecessors according to CFG: BB#50
4384B		%vreg175<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg175
4400B		%vreg174<def> = LDRXui %vreg175<kill>, 0; mem:LD8[%handle96] GPR64:%vreg174 GPR64common:%vreg175
4416B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4432B		%X0<def> = COPY %vreg174<kill>; GPR64:%vreg174
4448B		BL <ga:@fflush>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
4464B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4480B		%vreg172<def,dead> = COPY %W0; GPR32all:%vreg172
4496B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4512B		STACKMAP 6, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5]
4528B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4544B		%vreg170<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg170
4560B		%vreg169<def> = LDRXui %vreg170<kill>, 0; mem:LD8[%handle98] GPR64:%vreg169 GPR64common:%vreg170
4576B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4592B		%X0<def> = COPY %vreg169<kill>; GPR64:%vreg169
4608B		BL <ga:@ferror>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
4624B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4640B		%vreg167<def> = COPY %W0; GPR32:%vreg167
4656B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4672B		STACKMAP 7, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5]
4688B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4704B		CBZW %vreg167<kill>, <BB#57>; GPR32:%vreg167
	    Successors according to CFG: BB#57 BB#52
> %X8<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10]
> %X0<def> = LDRXui %X8<kill>, 0; mem:LD8[%handle96]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BL <ga:@fflush>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def,dead> = COPY %W0
Deleting identity copy.
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 6, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X8<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10]
> %X0<def> = LDRXui %X8<kill>, 0; mem:LD8[%handle98]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BL <ga:@ferror>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = COPY %W0
Deleting identity copy.
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 7, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> CBZW %W0<kill>, <BB#57>
4720B	BB#52: derived from LLVM BB %if.then.101
	    Live Ins: %X19
	    Predecessors according to CFG: BB#51
4736B		%vreg177<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg177
4752B		CBZX %vreg177<kill>, <BB#54>; GPR64:%vreg177
	    Successors according to CFG: BB#54 BB#53
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> CBZX %X8<kill>, <BB#54>
4768B	BB#53: derived from LLVM BB %if.then.104
	    Live Ins: %X19
	    Predecessors according to CFG: BB#52
4800B		%vreg180<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg180
4808B		%vreg178<def> = MOVi32imm 4294967290; GPR32:%vreg178
4816B		STRWui %vreg178<kill>, %vreg180<kill>, 0; mem:ST4[%67] GPR32:%vreg178 GPR64common:%vreg180
	    Successors according to CFG: BB#54
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %W9<def> = MOVi32imm 4294967290
> STRWui %W9<kill>, %X8<kill>, 0; mem:ST4[%67]
4832B	BB#54: derived from LLVM BB %if.end.105
	    Live Ins: %X19
	    Predecessors according to CFG: BB#52 BB#53
4848B		%vreg182<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg182
4864B		CBZX %vreg182<kill>, <BB#56>; GPR64:%vreg182
	    Successors according to CFG: BB#56 BB#55
> %X8<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10]
> CBZX %X8<kill>, <BB#56>
4880B	BB#55: derived from LLVM BB %if.then.108
	    Live Ins: %X19
	    Predecessors according to CFG: BB#54
4912B		%vreg185<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg185
4920B		%vreg183<def> = MOVi32imm 4294967290; GPR32:%vreg183
4928B		STRWui %vreg183<kill>, %vreg185<kill>, 1274; mem:ST4[%lastErr109] GPR32:%vreg183 GPR64common:%vreg185
	    Successors according to CFG: BB#56
> %X8<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10]
> %W9<def> = MOVi32imm 4294967290
> STRWui %W9<kill>, %X8<kill>, 1274; mem:ST4[%lastErr109]
4944B	BB#56: derived from LLVM BB %if.end.110
	    Live Ins: %X19
	    Predecessors according to CFG: BB#54 BB#55
4960B		B <BB#71>
	    Successors according to CFG: BB#71
> B <BB#71>
4976B	BB#57: derived from LLVM BB %if.end.111
	    Live Ins: %X19
	    Predecessors according to CFG: BB#51
4992B		B <BB#58>
	    Successors according to CFG: BB#58
> B <BB#58>
5008B	BB#58: derived from LLVM BB %if.end.112
	    Live Ins: %X19
	    Predecessors according to CFG: BB#49 BB#50 BB#57
5024B		%vreg187<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg187
5040B		CBZX %vreg187<kill>, <BB#60>; GPR64:%vreg187
	    Successors according to CFG: BB#60 BB#59
> %X8<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> CBZX %X8<kill>, <BB#60>
5056B	BB#59: derived from LLVM BB %if.then.115
	    Live Ins: %X19
	    Predecessors according to CFG: BB#58
5072B		%vreg193<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg193
5088B		%vreg192<def> = LDRWui %vreg193<kill>, 1257; mem:LD4[%total_in_lo32] GPR32:%vreg192 GPR64common:%vreg193
5104B		%vreg190<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg190
5120B		STRWui %vreg192<kill>, %vreg190<kill>, 0; mem:ST4[%73] GPR32:%vreg192 GPR64common:%vreg190
	    Successors according to CFG: BB#60
> %X8<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10]
> %W8<def> = LDRWui %X8<kill>, 1257; mem:LD4[%total_in_lo32]
> %X9<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> STRWui %W8<kill>, %X9<kill>, 0; mem:ST4[%73]
5136B	BB#60: derived from LLVM BB %if.end.117
	    Live Ins: %X19
	    Predecessors according to CFG: BB#58 BB#59
5152B		%vreg195<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64:%vreg195
5168B		CBZX %vreg195<kill>, <BB#62>; GPR64:%vreg195
	    Successors according to CFG: BB#62 BB#61
> %X8<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4]
> CBZX %X8<kill>, <BB#62>
5184B	BB#61: derived from LLVM BB %if.then.120
	    Live Ins: %X19
	    Predecessors according to CFG: BB#60
5200B		%vreg201<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg201
5216B		%vreg200<def> = LDRWui %vreg201<kill>, 1258; mem:LD4[%total_in_hi32] GPR32:%vreg200 GPR64common:%vreg201
5232B		%vreg198<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg198
5248B		STRWui %vreg200<kill>, %vreg198<kill>, 0; mem:ST4[%77] GPR32:%vreg200 GPR64common:%vreg198
	    Successors according to CFG: BB#62
> %X8<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10]
> %W8<def> = LDRWui %X8<kill>, 1258; mem:LD4[%total_in_hi32]
> %X9<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4]
> STRWui %W8<kill>, %X9<kill>, 0; mem:ST4[%77]
5264B	BB#62: derived from LLVM BB %if.end.122
	    Live Ins: %X19
	    Predecessors according to CFG: BB#60 BB#61
5280B		%vreg203<def> = LDRXui <fi#5>, 0; mem:LD8[FixedStack5] GPR64:%vreg203
5296B		CBZX %vreg203<kill>, <BB#64>; GPR64:%vreg203
	    Successors according to CFG: BB#64 BB#63
> %X8<def> = LDRXui <fi#5>, 0; mem:LD8[FixedStack5]
> CBZX %X8<kill>, <BB#64>
5312B	BB#63: derived from LLVM BB %if.then.125
	    Live Ins: %X19
	    Predecessors according to CFG: BB#62
5328B		%vreg209<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg209
5344B		%vreg208<def> = LDRWui %vreg209<kill>, 1263; mem:LD4[%total_out_lo32] GPR32:%vreg208 GPR64common:%vreg209
5360B		%vreg206<def> = LDRXui <fi#5>, 0; mem:LD8[FixedStack5] GPR64common:%vreg206
5376B		STRWui %vreg208<kill>, %vreg206<kill>, 0; mem:ST4[%81] GPR32:%vreg208 GPR64common:%vreg206
	    Successors according to CFG: BB#64
> %X8<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10]
> %W8<def> = LDRWui %X8<kill>, 1263; mem:LD4[%total_out_lo32]
> %X9<def> = LDRXui <fi#5>, 0; mem:LD8[FixedStack5]
> STRWui %W8<kill>, %X9<kill>, 0; mem:ST4[%81]
5392B	BB#64: derived from LLVM BB %if.end.127
	    Live Ins: %X19
	    Predecessors according to CFG: BB#62 BB#63
5408B		%vreg211<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64:%vreg211
5424B		CBZX %vreg211<kill>, <BB#66>; GPR64:%vreg211
	    Successors according to CFG: BB#66 BB#65
> %X8<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6]
> CBZX %X8<kill>, <BB#66>
5440B	BB#65: derived from LLVM BB %if.then.130
	    Live Ins: %X19
	    Predecessors according to CFG: BB#64
5456B		%vreg217<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg217
5472B		%vreg216<def> = LDRWui %vreg217<kill>, 1264; mem:LD4[%total_out_hi32] GPR32:%vreg216 GPR64common:%vreg217
5488B		%vreg214<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6] GPR64common:%vreg214
5504B		STRWui %vreg216<kill>, %vreg214<kill>, 0; mem:ST4[%85] GPR32:%vreg216 GPR64common:%vreg214
	    Successors according to CFG: BB#66
> %X8<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10]
> %W8<def> = LDRWui %X8<kill>, 1264; mem:LD4[%total_out_hi32]
> %X9<def> = LDRXui <fi#6>, 0; mem:LD8[FixedStack6]
> STRWui %W8<kill>, %X9<kill>, 0; mem:ST4[%85]
5520B	BB#66: derived from LLVM BB %if.end.132
	    Live Ins: %X19
	    Predecessors according to CFG: BB#64 BB#65
5536B		%vreg219<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg219
5552B		CBZX %vreg219<kill>, <BB#68>; GPR64:%vreg219
	    Successors according to CFG: BB#68 BB#67
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> CBZX %X8<kill>, <BB#68>
5568B	BB#67: derived from LLVM BB %if.then.135
	    Live Ins: %X19
	    Predecessors according to CFG: BB#66
5584B		%vreg221<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg221
5600B		STRWui %WZR, %vreg221<kill>, 0; mem:ST4[%87] GPR64common:%vreg221
	    Successors according to CFG: BB#68
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> STRWui %WZR, %X8<kill>, 0; mem:ST4[%87]
5616B	BB#68: derived from LLVM BB %if.end.136
	    Live Ins: %X19
	    Predecessors according to CFG: BB#66 BB#67
5632B		%vreg223<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg223
5648B		CBZX %vreg223<kill>, <BB#70>; GPR64:%vreg223
	    Successors according to CFG: BB#70 BB#69
> %X8<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10]
> CBZX %X8<kill>, <BB#70>
5664B	BB#69: derived from LLVM BB %if.then.139
	    Live Ins: %X19
	    Predecessors according to CFG: BB#68
5680B		%vreg225<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64common:%vreg225
5696B		STRWui %WZR, %vreg225<kill>, 1274; mem:ST4[%lastErr140] GPR64common:%vreg225
	    Successors according to CFG: BB#70
> %X8<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10]
> STRWui %WZR, %X8<kill>, 1274; mem:ST4[%lastErr140]
5712B	BB#70: derived from LLVM BB %if.end.141
	    Live Ins: %X19
	    Predecessors according to CFG: BB#68 BB#69
5728B		%vreg235<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg235
5744B		%vreg233<def> = MOVi64imm 5016; GPR64:%vreg233
5760B		%vreg234<def> = ADDXrr %vreg235<kill>, %vreg233<kill>; GPR64:%vreg234,%vreg235,%vreg233
5776B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5792B		%X0<def> = COPY %vreg234<kill>; GPR64:%vreg234
5808B		BL <ga:@BZ2_bzCompressEnd>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
5824B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5840B		%vreg231<def,dead> = COPY %W0; GPR32all:%vreg231
5856B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5872B		STACKMAP 8, 0, 0, <fi#10>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack10]
5888B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5904B		%vreg228<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg228
5936B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5952B		%X0<def> = COPY %vreg228<kill>; GPR64:%vreg228
5968B		BL <ga:@free>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>
5984B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
6000B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
6016B		STACKMAP 9, 0, %LR<earlyclobber,imp-def,dead>, ...
6032B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#71
> %X8<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10]
> %X9<def> = MOVi64imm 5016
> %X0<def> = ADDXrr %X8<kill>, %X9<kill>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BL <ga:@BZ2_bzCompressEnd>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def,dead> = COPY %W0
Deleting identity copy.
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 8, 0, 0, <fi#10>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack10]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BL <ga:@free>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 9, 0, %LR<earlyclobber,imp-def,dead>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
6048B	BB#71: derived from LLVM BB %return
	    Live Ins: %X19
	    Predecessors according to CFG: BB#11 BB#43 BB#35 BB#56 BB#70 BB#17 BB#5
6064B		%vreg254<def> = ADRP <ga:@BZ2_bzWriteClose64>[TF=1]; GPR64common:%vreg254
6080B		%vreg256<def> = ADDXri %vreg254<kill>, <ga:@BZ2_bzWriteClose64>[TF=34], 0; GPR64sp:%vreg256 GPR64common:%vreg254
6128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
6144B		%X0<def> = COPY %vreg256<kill>; GPR64sp:%vreg256
6160B		%X1<def> = COPY %vreg23<kill>; GPR64:%vreg23
6176B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
6192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
6208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
6224B		STACKMAP 10, 0, %LR<earlyclobber,imp-def,dead>, ...
6240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
6256B		RET_ReallyLR
> %X8<def> = ADRP <ga:@BZ2_bzWriteClose64>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@BZ2_bzWriteClose64>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19<kill>
> BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 10, 0, %LR<earlyclobber,imp-def,dead>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> RET_ReallyLR
Computing live-in reg-units in ABI blocks.
0B	BB#0 W0#0 W1#0 W2#0 W3#0 W4#0 W5#0 W30#0
Created 7 new intervals.
********** INTERVALS **********
W30 [0B,16r:0)[336r,336d:12)[400e,400d:6)[1616r,1616d:11)[1680e,1680d:5)[2080r,2080d:10)[2144e,2144d:4)[3600r,3600d:9)[3664e,3664d:3)[4048r,4048d:8)[4112e,4112d:2)[4576r,4576d:7)[4624e,4624d:1)  0@0B-phi 1@4624e 2@4112e 3@3664e 4@2144e 5@1680e 6@400e 7@4576r 8@4048r 9@3600r 10@2080r 11@1616r 12@336r
W0 [0B,112r:0)[304r,336r:10)[1600r,1616r:9)[1616r,1648r:2)[2064r,2080r:8)[2080r,2112r:7)[3552r,3600r:6)[3600r,3632r:1)[4032r,4048r:5)[4544r,4576r:3)[4672r,4688r:4)  0@0B-phi 1@3600r 2@1616r 3@4544r 4@4672r 5@4032r 6@3552r 7@2080r 8@2064r 9@1600r 10@304r
W1 [0B,96r:0)[320r,336r:3)[3568r,3600r:1)[4560r,4576r:2)  0@0B-phi 1@3568r 2@4560r 3@320r
W2 [0B,80r:0)[3584r,3600r:1)  0@0B-phi 1@3584r
W3 [0B,64r:0)  0@0B-phi
W4 [0B,48r:0)  0@0B-phi
W5 [0B,32r:0)  0@0B-phi
%vreg0 [112r,128r:0)  0@112r
%vreg1 [128r,432r:0)  0@128r
%vreg2 [96r,144r:0)  0@96r
%vreg3 [144r,448r:0)  0@144r
%vreg4 [80r,160r:0)  0@80r
%vreg5 [160r,464r:0)  0@160r
%vreg6 [64r,176r:0)  0@64r
%vreg7 [176r,480r:0)  0@176r
%vreg8 [48r,192r:0)  0@48r
%vreg9 [192r,496r:0)  0@192r
%vreg10 [32r,208r:0)  0@32r
%vreg11 [208r,512r:0)  0@208r
%vreg13 [544r,560r:0)  0@544r
%vreg14 [368r,528r:0)  0@368r
%vreg15 [224r,240r:0)  0@224r
%vreg16 [240r,256r:0)  0@240r
%vreg17 [256r,304r:0)  0@256r
%vreg18 [272r,320r:0)  0@272r
%vreg19 [16r,4512r:0)  0@16r
%vreg21 [592r,608r:0)  0@592r
%vreg23 [640r,656r:0)  0@640r
%vreg25 [688r,704r:0)  0@688r
%vreg27 [736r,752r:0)  0@736r
%vreg29 [784r,800r:0)  0@784r
%vreg31 [832r,848r:0)  0@832r
%vreg33 [896r,912r:0)  0@896r
%vreg35 [944r,960r:0)  0@944r
%vreg37 [1008r,1024r:0)  0@1008r
%vreg39 [1056r,1072r:0)  0@1056r
%vreg41 [1104r,1120r:0)  0@1104r
%vreg43 [1152r,1168r:0)  0@1152r
%vreg45 [1200r,1232r:0)  0@1200r
%vreg46 [1216r,1232r:0)  0@1216r
%vreg49 [1648r,1712r:0)  0@1648r
%vreg50 [1568r,1600r:0)  0@1568r
%vreg52 [2208r,2224r:0)  0@2208r
%vreg55 [2176r,2192r:0)  0@2176r
%vreg56 [2032r,2064r:0)  0@2032r
%vreg57 [2112r,2176r:0)  0@2112r
%vreg59 [2544r,2560r:0)  0@2544r
%vreg61 [2592r,2608r:0)  0@2592r
%vreg63 [2640r,2656r:0)  0@2640r
%vreg65 [2688r,2704r:0)  0@2688r
%vreg66 [2736r,3040r:0)  0@2736r
%vreg68 [3024r,3040r:0)  0@3024r
%vreg70 [2992r,3008r:0)  0@2992r
%vreg72 [2960r,2976r:0)  0@2960r
%vreg74 [2912r,2928r:0)  0@2912r
%vreg75 [2928r,2944r:0)  0@2928r
%vreg76 [2896r,2928r:0)  0@2896r
%vreg78 [2864r,2880r:0)  0@2864r
%vreg81 [2832r,2848r:0)  0@2832r
%vreg82 [2816r,2848r:0)  0@2816r
%vreg84 [2768r,2784r:0)  0@2768r
%vreg85 [2784r,2800r:0)  0@2784r
%vreg86 [2752r,2784r:0)  0@2752r
%vreg88 [3072r,3088r:0)  0@3072r
%vreg90 [3712r,3728r:0)  0@3712r
%vreg95 [3632r,3696r:0)  0@3632r
%vreg96 [3520r,3584r:0)  0@3520r
%vreg97 [3504r,3568r:0)  0@3504r
%vreg99 [3472r,3488r:0)  0@3472r
%vreg100 [3488r,3552r:0)  0@3488r
%vreg101 [3456r,3488r:0)  0@3456r
%vreg104 [4416r,4432r:0)  0@4416r
%vreg105 [4400r,4416r:0)  0@4400r
%vreg106 [4192r,4384r:0)  0@4192r
%vreg108 [4352r,4368r:0)  0@4352r
%vreg109 [4368r,4384r:0)  0@4368r
%vreg110 [4336r,4368r:0)  0@4336r
%vreg113 [4304r,4320r:0)  0@4304r
%vreg116 [4288r,4320r:0)  0@4288r
%vreg117 [4272r,4288r:0)  0@4272r
%vreg120 [4240r,4256r:0)  0@4240r
%vreg122 [4224r,4256r:0)  0@4224r
%vreg123 [4208r,4224r:0)  0@4208r
%vreg125 [3760r,3776r:0)  0@3760r
%vreg128 [3824r,3840r:0)  0@3824r
%vreg129 [3808r,3840r:0)  0@3808r
%vreg131 [3872r,3888r:0)  0@3872r
%vreg134 [3936r,3952r:0)  0@3936r
%vreg135 [3920r,3952r:0)  0@3920r
%vreg136 [4080r,4144r:0)  0@4080r
%vreg139 [4000r,4032r:0)  0@4000r
%vreg140 [3984r,4000r:0)  0@3984r
%vreg143 [3392r,3408r:0)  0@3392r
%vreg144 [3376r,3392r:0)  0@3376r
%vreg147 [3344r,3360r:0)  0@3344r
%vreg148 [3328r,3344r:0)  0@3328r
%vreg152 [3296r,3312r:0)  0@3296r
%vreg153 [3280r,3296r:0)  0@3280r
%vreg154 [3264r,3312r:0)  0@3264r
%vreg159 [3232r,3248r:0)  0@3232r
%vreg161 [3216r,3232r:0)  0@3216r
%vreg162 [3200r,3216r:0)  0@3200r
%vreg167 [3184r,3232r:0)  0@3184r
%vreg168 [3168r,3184r:0)  0@3168r
%vreg170 [3152r,3248r:0)  0@3152r
%vreg171 [3136r,3152r:0)  0@3136r
%vreg173 [2256r,2272r:0)  0@2256r
%vreg174 [2304r,2336r:0)  0@2304r
%vreg176 [2320r,2336r:0)  0@2320r
%vreg178 [2368r,2384r:0)  0@2368r
%vreg179 [2416r,2448r:0)  0@2416r
%vreg181 [2432r,2448r:0)  0@2432r
%vreg182 [2480r,2496r:0)  0@2480r
%vreg184 [1744r,1760r:0)  0@1744r
%vreg185 [1792r,1824r:0)  0@1792r
%vreg187 [1808r,1824r:0)  0@1808r
%vreg189 [1856r,1872r:0)  0@1856r
%vreg190 [1904r,1936r:0)  0@1904r
%vreg192 [1920r,1936r:0)  0@1920r
%vreg193 [1968r,1984r:0)  0@1968r
%vreg195 [1280r,1296r:0)  0@1280r
%vreg196 [1328r,1360r:0)  0@1328r
%vreg198 [1344r,1360r:0)  0@1344r
%vreg200 [1392r,1408r:0)  0@1392r
%vreg201 [1440r,1472r:0)  0@1440r
%vreg203 [1456r,1472r:0)  0@1456r
%vreg204 [1504r,1520r:0)  0@1504r
%vreg206 [4656r,4672r:0)  0@4656r
%vreg207 [4464r,4480r:0)  0@4464r
%vreg208 [4480r,4496r:0)  0@4480r
%vreg209 [4496r,4544r:0)  0@4496r
%vreg210 [4512r,4560r:0)  0@4512r
RegMasks: 336r 1616r 2080r 3600r 4048r 4576r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzReadOpen: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=8, align=8, at location [SP]
  fi#3: size=4, align=4, at location [SP]
  fi#4: size=4, align=4, at location [SP]
  fi#5: size=8, align=8, at location [SP]
  fi#6: size=4, align=4, at location [SP]
  fi#7: size=8, align=8, at location [SP]
  fi#8: size=4, align=4, at location [SP]
Function Live Ins: %X0 in %vreg0, %X1 in %vreg2, %W2 in %vreg4, %W3 in %vreg6, %X4 in %vreg8, %W5 in %vreg10, %LR in %vreg19

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %X1 %W2 %W3 %X4 %W5 %LR
16B		%vreg19<def> = COPY %LR; GPR64:%vreg19
32B		%vreg10<def> = COPY %W5; GPR32:%vreg10
48B		%vreg8<def> = COPY %X4; GPR64:%vreg8
64B		%vreg6<def> = COPY %W3; GPR32:%vreg6
80B		%vreg4<def> = COPY %W2; GPR32:%vreg4
96B		%vreg2<def> = COPY %X1; GPR64:%vreg2
112B		%vreg0<def> = COPY %X0; GPR64:%vreg0
128B		%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
144B		%vreg3<def> = COPY %vreg2; GPR64:%vreg3,%vreg2
160B		%vreg5<def> = COPY %vreg4; GPR32:%vreg5,%vreg4
176B		%vreg7<def> = COPY %vreg6; GPR32:%vreg7,%vreg6
192B		%vreg9<def> = COPY %vreg8; GPR64:%vreg9,%vreg8
208B		%vreg11<def> = COPY %vreg10; GPR32:%vreg11,%vreg10
224B		%vreg15<def> = ADRP <ga:@BZ2_bzReadOpen>[TF=1]; GPR64common:%vreg15
240B		%vreg16<def> = ADDXri %vreg15, <ga:@BZ2_bzReadOpen>[TF=34], 0; GPR64sp:%vreg16 GPR64common:%vreg15
256B		%vreg17<def> = COPY %vreg16; GPR64all:%vreg17 GPR64sp:%vreg16
272B		%vreg18<def> = COPY %vreg19; GPR64all:%vreg18 GPR64:%vreg19
288B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
304B		%X0<def> = COPY %vreg17; GPR64all:%vreg17
320B		%X1<def> = COPY %vreg18; GPR64all:%vreg18
336B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
352B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
368B		%vreg14<def> = COPY %XZR; GPR64:%vreg14
384B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
400B		STACKMAP 0, 0, %vreg1, 0, <fi#1>, 0, 0, <fi#7>, 0, %vreg3, 0, <fi#2>, 0, %vreg11, 0, <fi#6>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, %vreg7, 0, <fi#4>, 0, %vreg9, 0, <fi#5>, 0, %vreg5, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack8](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5] LD8[FixedStack3](align=4) GPR64:%vreg1,%vreg3,%vreg9 GPR32:%vreg11,%vreg7,%vreg5
416B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
432B		STRXui %vreg1, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg1
448B		STRXui %vreg3, <fi#2>, 0; mem:ST8[FixedStack2] GPR64:%vreg3
464B		STRWui %vreg5, <fi#3>, 0; mem:ST4[FixedStack3] GPR32:%vreg5
480B		STRWui %vreg7, <fi#4>, 0; mem:ST4[FixedStack4] GPR32:%vreg7
496B		STRXui %vreg9, <fi#5>, 0; mem:ST8[FixedStack5] GPR64:%vreg9
512B		STRWui %vreg11, <fi#6>, 0; mem:ST4[FixedStack6] GPR32:%vreg11
528B		STRXui %vreg14, <fi#7>, 0; mem:ST8[FixedStack7] GPR64:%vreg14
544B		%vreg13<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg13
560B		CBZX %vreg13, <BB#2>; GPR64:%vreg13
	    Successors according to CFG: BB#2 BB#1

576B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
592B		%vreg21<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg21
608B		STRWui %WZR, %vreg21, 0; mem:ST4[%1] GPR64common:%vreg21
	    Successors according to CFG: BB#2

624B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#1
640B		%vreg23<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg23
656B		CBZX %vreg23, <BB#4>; GPR64:%vreg23
	    Successors according to CFG: BB#4 BB#3

672B	BB#3: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#2
688B		%vreg25<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg25
704B		STRWui %WZR, %vreg25, 1274; mem:ST4[%lastErr] GPR64common:%vreg25
	    Successors according to CFG: BB#4

720B	BB#4: derived from LLVM BB %if.end.3
	    Predecessors according to CFG: BB#2 BB#3
736B		%vreg27<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg27
752B		CBZX %vreg27, <BB#14>; GPR64:%vreg27
	    Successors according to CFG: BB#14 BB#5

768B	BB#5: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#4
784B		%vreg29<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg29
800B		CBZW %vreg29, <BB#7>; GPR32:%vreg29
	    Successors according to CFG: BB#7 BB#6

816B	BB#6: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#5
832B		%vreg31<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32common:%vreg31
848B		%WZR<def> = SUBSWri %vreg31, 1, 0, %NZCV<imp-def>; GPR32common:%vreg31
864B		Bcc 1, <BB#14>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#14 BB#7

880B	BB#7: derived from LLVM BB %lor.lhs.false.7
	    Predecessors according to CFG: BB#5 BB#6
896B		%vreg33<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg33
912B		TBNZW %vreg33, 31, <BB#14>; GPR32:%vreg33
	    Successors according to CFG: BB#14 BB#8

928B	BB#8: derived from LLVM BB %lor.lhs.false.9
	    Predecessors according to CFG: BB#7
944B		%vreg35<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32common:%vreg35
960B		%WZR<def> = SUBSWri %vreg35, 4, 0, %NZCV<imp-def>; GPR32common:%vreg35
976B		Bcc 12, <BB#14>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#14 BB#9

992B	BB#9: derived from LLVM BB %lor.lhs.false.11
	    Predecessors according to CFG: BB#8
1008B		%vreg37<def> = LDRXui <fi#5>, 0; mem:LD8[FixedStack5] GPR64:%vreg37
1024B		CBNZX %vreg37, <BB#11>; GPR64:%vreg37
	    Successors according to CFG: BB#11 BB#10

1040B	BB#10: derived from LLVM BB %land.lhs.true.13
	    Predecessors according to CFG: BB#9
1056B		%vreg39<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg39
1072B		CBNZW %vreg39, <BB#14>; GPR32:%vreg39
	    Successors according to CFG: BB#14 BB#11

1088B	BB#11: derived from LLVM BB %lor.lhs.false.15
	    Predecessors according to CFG: BB#9 BB#10
1104B		%vreg41<def> = LDRXui <fi#5>, 0; mem:LD8[FixedStack5] GPR64:%vreg41
1120B		CBZX %vreg41, <BB#19>; GPR64:%vreg41
	    Successors according to CFG: BB#19 BB#12

1136B	BB#12: derived from LLVM BB %land.lhs.true.17
	    Predecessors according to CFG: BB#11
1152B		%vreg43<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg43
1168B		TBNZW %vreg43, 31, <BB#14>; GPR32:%vreg43
	    Successors according to CFG: BB#14 BB#13

1184B	BB#13: derived from LLVM BB %lor.lhs.false.19
	    Predecessors according to CFG: BB#12
1200B		%vreg45<def> = MOVi32imm 5000; GPR32:%vreg45
1216B		%vreg46<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg46
1232B		%WZR<def> = SUBSWrr %vreg46, %vreg45, %NZCV<imp-def>; GPR32:%vreg46,%vreg45
1248B		Bcc 13, <BB#19>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#19 BB#14

1264B	BB#14: derived from LLVM BB %if.then.21
	    Predecessors according to CFG: BB#4 BB#6 BB#7 BB#8 BB#10 BB#12 BB#13
1280B		%vreg195<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg195
1296B		CBZX %vreg195, <BB#16>; GPR64:%vreg195
	    Successors according to CFG: BB#16 BB#15

1312B	BB#15: derived from LLVM BB %if.then.23
	    Predecessors according to CFG: BB#14
1328B		%vreg196<def> = MOVi32imm 4294967294; GPR32:%vreg196
1344B		%vreg198<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg198
1360B		STRWui %vreg196, %vreg198, 0; mem:ST4[%15] GPR32:%vreg196 GPR64common:%vreg198
	    Successors according to CFG: BB#16

1376B	BB#16: derived from LLVM BB %if.end.24
	    Predecessors according to CFG: BB#14 BB#15
1392B		%vreg200<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg200
1408B		CBZX %vreg200, <BB#18>; GPR64:%vreg200
	    Successors according to CFG: BB#18 BB#17

1424B	BB#17: derived from LLVM BB %if.then.26
	    Predecessors according to CFG: BB#16
1440B		%vreg201<def> = MOVi32imm 4294967294; GPR32:%vreg201
1456B		%vreg203<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg203
1472B		STRWui %vreg201, %vreg203, 1274; mem:ST4[%lastErr27] GPR32:%vreg201 GPR64common:%vreg203
	    Successors according to CFG: BB#18

1488B	BB#18: derived from LLVM BB %if.end.28
	    Predecessors according to CFG: BB#16 BB#17
1504B		%vreg204<def> = COPY %XZR; GPR64:%vreg204
1520B		STRXui %vreg204, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg204
1536B		B <BB#45>
	    Successors according to CFG: BB#45

1552B	BB#19: derived from LLVM BB %if.end.29
	    Predecessors according to CFG: BB#11 BB#13
1568B		%vreg50<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg50
1584B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1600B		%X0<def> = COPY %vreg50; GPR64:%vreg50
1616B		BL <ga:@ferror>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
1632B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1648B		%vreg49<def> = COPY %W0; GPR32:%vreg49
1664B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1680B		STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#2>, 0, 0, <fi#6>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack8](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5] LD8[FixedStack3](align=4)
1696B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1712B		CBZW %vreg49, <BB#25>; GPR32:%vreg49
	    Successors according to CFG: BB#25 BB#20

1728B	BB#20: derived from LLVM BB %if.then.30
	    Predecessors according to CFG: BB#19
1744B		%vreg184<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg184
1760B		CBZX %vreg184, <BB#22>; GPR64:%vreg184
	    Successors according to CFG: BB#22 BB#21

1776B	BB#21: derived from LLVM BB %if.then.32
	    Predecessors according to CFG: BB#20
1792B		%vreg185<def> = MOVi32imm 4294967290; GPR32:%vreg185
1808B		%vreg187<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg187
1824B		STRWui %vreg185, %vreg187, 0; mem:ST4[%20] GPR32:%vreg185 GPR64common:%vreg187
	    Successors according to CFG: BB#22

1840B	BB#22: derived from LLVM BB %if.end.33
	    Predecessors according to CFG: BB#20 BB#21
1856B		%vreg189<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg189
1872B		CBZX %vreg189, <BB#24>; GPR64:%vreg189
	    Successors according to CFG: BB#24 BB#23

1888B	BB#23: derived from LLVM BB %if.then.35
	    Predecessors according to CFG: BB#22
1904B		%vreg190<def> = MOVi32imm 4294967290; GPR32:%vreg190
1920B		%vreg192<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg192
1936B		STRWui %vreg190, %vreg192, 1274; mem:ST4[%lastErr36] GPR32:%vreg190 GPR64common:%vreg192
	    Successors according to CFG: BB#24

1952B	BB#24: derived from LLVM BB %if.end.37
	    Predecessors according to CFG: BB#22 BB#23
1968B		%vreg193<def> = COPY %XZR; GPR64:%vreg193
1984B		STRXui %vreg193, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg193
2000B		B <BB#45>
	    Successors according to CFG: BB#45

2016B	BB#25: derived from LLVM BB %if.end.38
	    Predecessors according to CFG: BB#19
2032B		%vreg56<def> = MOVi64imm 5104; GPR64:%vreg56
2048B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2064B		%X0<def> = COPY %vreg56; GPR64:%vreg56
2080B		BL <ga:@malloc>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X0<imp-def>
2096B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2112B		%vreg57<def> = COPY %X0; GPR64all:%vreg57
2128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2144B		STACKMAP 2, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#2>, 0, 0, <fi#6>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack8](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5] LD8[FixedStack3](align=4)
2160B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2176B		%vreg55<def> = COPY %vreg57; GPR64:%vreg55 GPR64all:%vreg57
2192B		STRXui %vreg55, <fi#7>, 0; mem:ST8[FixedStack7] GPR64:%vreg55
2208B		%vreg52<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg52
2224B		CBNZX %vreg52, <BB#31>; GPR64:%vreg52
	    Successors according to CFG: BB#31 BB#26

2240B	BB#26: derived from LLVM BB %if.then.41
	    Predecessors according to CFG: BB#25
2256B		%vreg173<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg173
2272B		CBZX %vreg173, <BB#28>; GPR64:%vreg173
	    Successors according to CFG: BB#28 BB#27

2288B	BB#27: derived from LLVM BB %if.then.43
	    Predecessors according to CFG: BB#26
2304B		%vreg174<def> = MOVi32imm 4294967293; GPR32:%vreg174
2320B		%vreg176<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg176
2336B		STRWui %vreg174, %vreg176, 0; mem:ST4[%26] GPR32:%vreg174 GPR64common:%vreg176
	    Successors according to CFG: BB#28

2352B	BB#28: derived from LLVM BB %if.end.44
	    Predecessors according to CFG: BB#26 BB#27
2368B		%vreg178<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg178
2384B		CBZX %vreg178, <BB#30>; GPR64:%vreg178
	    Successors according to CFG: BB#30 BB#29

2400B	BB#29: derived from LLVM BB %if.then.46
	    Predecessors according to CFG: BB#28
2416B		%vreg179<def> = MOVi32imm 4294967293; GPR32:%vreg179
2432B		%vreg181<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg181
2448B		STRWui %vreg179, %vreg181, 1274; mem:ST4[%lastErr47] GPR32:%vreg179 GPR64common:%vreg181
	    Successors according to CFG: BB#30

2464B	BB#30: derived from LLVM BB %if.end.48
	    Predecessors according to CFG: BB#28 BB#29
2480B		%vreg182<def> = COPY %XZR; GPR64:%vreg182
2496B		STRXui %vreg182, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg182
2512B		B <BB#45>
	    Successors according to CFG: BB#45

2528B	BB#31: derived from LLVM BB %if.end.49
	    Predecessors according to CFG: BB#25
2544B		%vreg59<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg59
2560B		CBZX %vreg59, <BB#33>; GPR64:%vreg59
	    Successors according to CFG: BB#33 BB#32

2576B	BB#32: derived from LLVM BB %if.then.51
	    Predecessors according to CFG: BB#31
2592B		%vreg61<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg61
2608B		STRWui %WZR, %vreg61, 0; mem:ST4[%30] GPR64common:%vreg61
	    Successors according to CFG: BB#33

2624B	BB#33: derived from LLVM BB %if.end.52
	    Predecessors according to CFG: BB#31 BB#32
2640B		%vreg63<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg63
2656B		CBZX %vreg63, <BB#35>; GPR64:%vreg63
	    Successors according to CFG: BB#35 BB#34

2672B	BB#34: derived from LLVM BB %if.then.54
	    Predecessors according to CFG: BB#33
2688B		%vreg65<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg65
2704B		STRWui %WZR, %vreg65, 1274; mem:ST4[%lastErr55] GPR64common:%vreg65
	    Successors according to CFG: BB#35

2720B	BB#35: derived from LLVM BB %if.end.56
	    Predecessors according to CFG: BB#33 BB#34
2736B		%vreg66<def> = COPY %XZR; GPR64:%vreg66
2752B		%vreg86<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg86
2768B		%vreg84<def> = MOVi64imm 5100; GPR64:%vreg84
2784B		%vreg85<def> = ADDXrr %vreg86, %vreg84; GPR64common:%vreg85 GPR64:%vreg86,%vreg84
2800B		STRBBui %WZR, %vreg85, 0; mem:ST1[%initialisedOk] GPR64common:%vreg85
2816B		%vreg82<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg82
2832B		%vreg81<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg81
2848B		STRXui %vreg82, %vreg81, 0; mem:ST8[%handle] GPR64:%vreg82 GPR64common:%vreg81
2864B		%vreg78<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg78
2880B		STRWui %WZR, %vreg78, 1252; mem:ST4[%bufN] GPR64common:%vreg78
2896B		%vreg76<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg76
2912B		%vreg74<def> = MOVi64imm 5012; GPR64:%vreg74
2928B		%vreg75<def> = ADDXrr %vreg76, %vreg74; GPR64common:%vreg75 GPR64:%vreg76,%vreg74
2944B		STRBBui %WZR, %vreg75, 0; mem:ST1[%writing] GPR64common:%vreg75
2960B		%vreg72<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg72
2976B		STRXui %vreg66, %vreg72, 634; mem:ST8[%bzalloc] GPR64:%vreg66 GPR64common:%vreg72
2992B		%vreg70<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg70
3008B		STRXui %vreg66, %vreg70, 635; mem:ST8[%bzfree] GPR64:%vreg66 GPR64common:%vreg70
3024B		%vreg68<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg68
3040B		STRXui %vreg66, %vreg68, 636; mem:ST8[%opaque] GPR64:%vreg66 GPR64common:%vreg68
	    Successors according to CFG: BB#36

3056B	BB#36: derived from LLVM BB %while.cond
	    Predecessors according to CFG: BB#35 BB#37
3072B		%vreg88<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32common:%vreg88
3088B		%WZR<def> = SUBSWri %vreg88, 0, 0, %NZCV<imp-def>; GPR32common:%vreg88
3104B		Bcc 13, <BB#38>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#38 BB#37

3120B	BB#37: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#36
3136B		%vreg171<def> = LDRXui <fi#5>, 0; mem:LD8[FixedStack5] GPR64common:%vreg171
3152B		%vreg170<def> = LDRBBui %vreg171, 0; mem:LD1[%42] GPR32:%vreg170 GPR64common:%vreg171
3168B		%vreg168<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg168
3184B		%vreg167<def> = LDRSWui %vreg168, 1252; mem:LD4[%bufN60] GPR64:%vreg167 GPR64common:%vreg168
3200B		%vreg162<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg162
3216B		%vreg161<def> = ADDXri %vreg162, 8, 0; GPR64common:%vreg161,%vreg162
3232B		%vreg159<def> = ADDXrr %vreg161, %vreg167; GPR64common:%vreg159,%vreg161 GPR64:%vreg167
3248B		STRBBui %vreg170, %vreg159, 0; mem:ST1[%arrayidx] GPR32:%vreg170 GPR64common:%vreg159
3264B		%vreg154<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg154
3280B		%vreg153<def> = LDRWui %vreg154, 1252; mem:LD4[%bufN61] GPR32common:%vreg153 GPR64common:%vreg154
3296B		%vreg152<def> = ADDWri %vreg153, 1, 0; GPR32common:%vreg152,%vreg153
3312B		STRWui %vreg152, %vreg154, 1252; mem:ST4[%bufN61] GPR32common:%vreg152 GPR64common:%vreg154
3328B		%vreg148<def> = LDRXui <fi#5>, 0; mem:LD8[FixedStack5] GPR64common:%vreg148
3344B		%vreg147<def> = ADDXri %vreg148, 1, 0; GPR64common:%vreg147,%vreg148
3360B		STRXui %vreg147, <fi#5>, 0; mem:ST8[FixedStack5] GPR64common:%vreg147
3376B		%vreg144<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32common:%vreg144
3392B		%vreg143<def> = SUBWri %vreg144, 1, 0; GPR32common:%vreg143,%vreg144
3408B		STRWui %vreg143, <fi#6>, 0; mem:ST4[FixedStack6] GPR32common:%vreg143
3424B		B <BB#36>
	    Successors according to CFG: BB#36

3440B	BB#38: derived from LLVM BB %while.end
	    Predecessors according to CFG: BB#36
3456B		%vreg101<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg101
3472B		%vreg99<def> = MOVi64imm 5016; GPR64:%vreg99
3488B		%vreg100<def> = ADDXrr %vreg101, %vreg99; GPR64:%vreg100,%vreg101,%vreg99
3504B		%vreg97<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg97
3520B		%vreg96<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg96
3536B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3552B		%X0<def> = COPY %vreg100; GPR64:%vreg100
3568B		%W1<def> = COPY %vreg97; GPR32:%vreg97
3584B		%W2<def> = COPY %vreg96; GPR32:%vreg96
3600B		BL <ga:@BZ2_bzDecompressInit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %W2<imp-use>, %W0<imp-def>
3616B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3632B		%vreg95<def> = COPY %W0; GPR32:%vreg95
3648B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3664B		STACKMAP 3, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack8](align=4) LD8[FixedStack0]
3680B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3696B		STRWui %vreg95, <fi#8>, 0; mem:ST4[FixedStack8] GPR32:%vreg95
3712B		%vreg90<def> = LDRWui <fi#8>, 0; mem:LD4[FixedStack8] GPR32:%vreg90
3728B		CBZW %vreg90, <BB#44>; GPR32:%vreg90
	    Successors according to CFG: BB#44 BB#39

3744B	BB#39: derived from LLVM BB %if.then.65
	    Predecessors according to CFG: BB#38
3760B		%vreg125<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg125
3776B		CBZX %vreg125, <BB#41>; GPR64:%vreg125
	    Successors according to CFG: BB#41 BB#40

3792B	BB#40: derived from LLVM BB %if.then.67
	    Predecessors according to CFG: BB#39
3808B		%vreg129<def> = LDRWui <fi#8>, 0; mem:LD4[FixedStack8] GPR32:%vreg129
3824B		%vreg128<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg128
3840B		STRWui %vreg129, %vreg128, 0; mem:ST4[%57] GPR32:%vreg129 GPR64common:%vreg128
	    Successors according to CFG: BB#41

3856B	BB#41: derived from LLVM BB %if.end.68
	    Predecessors according to CFG: BB#39 BB#40
3872B		%vreg131<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg131
3888B		CBZX %vreg131, <BB#43>; GPR64:%vreg131
	    Successors according to CFG: BB#43 BB#42

3904B	BB#42: derived from LLVM BB %if.then.70
	    Predecessors according to CFG: BB#41
3920B		%vreg135<def> = LDRWui <fi#8>, 0; mem:LD4[FixedStack8] GPR32:%vreg135
3936B		%vreg134<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg134
3952B		STRWui %vreg135, %vreg134, 1274; mem:ST4[%lastErr71] GPR32:%vreg135 GPR64common:%vreg134
	    Successors according to CFG: BB#43

3968B	BB#43: derived from LLVM BB %if.end.72
	    Predecessors according to CFG: BB#41 BB#42
3984B		%vreg140<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg140
4000B		%vreg139<def> = COPY %vreg140; GPR64all:%vreg139 GPR64:%vreg140
4016B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4032B		%X0<def> = COPY %vreg139; GPR64all:%vreg139
4048B		BL <ga:@free>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>
4064B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4080B		%vreg136<def> = COPY %XZR; GPR64:%vreg136
4096B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4112B		STACKMAP 4, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0]
4128B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4144B		STRXui %vreg136, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg136
4160B		B <BB#45>
	    Successors according to CFG: BB#45

4176B	BB#44: derived from LLVM BB %if.end.73
	    Predecessors according to CFG: BB#38
4192B		%vreg106<def> = MOVi32imm 1; GPR32:%vreg106
4208B		%vreg123<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg123
4224B		%vreg122<def> = LDRWui %vreg123, 1252; mem:LD4[%bufN74] GPR32:%vreg122 GPR64common:%vreg123
4240B		%vreg120<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg120
4256B		STRWui %vreg122, %vreg120, 1256; mem:ST4[%avail_in] GPR32:%vreg122 GPR64common:%vreg120
4272B		%vreg117<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg117
4288B		%vreg116<def> = ADDXri %vreg117, 8, 0; GPR64common:%vreg116,%vreg117
4304B		%vreg113<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg113
4320B		STRXui %vreg116, %vreg113, 627; mem:ST8[%next_in] GPR64common:%vreg116,%vreg113
4336B		%vreg110<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg110
4352B		%vreg108<def> = MOVi64imm 5100; GPR64:%vreg108
4368B		%vreg109<def> = ADDXrr %vreg110, %vreg108; GPR64common:%vreg109 GPR64:%vreg110,%vreg108
4384B		STRBBui %vreg106, %vreg109, 0; mem:ST1[%initialisedOk78] GPR32:%vreg106 GPR64common:%vreg109
4400B		%vreg105<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg105
4416B		%vreg104<def> = COPY %vreg105; GPR64:%vreg104,%vreg105
4432B		STRXui %vreg104, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg104
	    Successors according to CFG: BB#45

4448B	BB#45: derived from LLVM BB %return
	    Predecessors according to CFG: BB#44 BB#43 BB#30 BB#24 BB#18
4464B		%vreg207<def> = ADRP <ga:@BZ2_bzReadOpen>[TF=1]; GPR64common:%vreg207
4480B		%vreg208<def> = ADDXri %vreg207, <ga:@BZ2_bzReadOpen>[TF=34], 0; GPR64sp:%vreg208 GPR64common:%vreg207
4496B		%vreg209<def> = COPY %vreg208; GPR64all:%vreg209 GPR64sp:%vreg208
4512B		%vreg210<def> = COPY %vreg19; GPR64all:%vreg210 GPR64:%vreg19
4528B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4544B		%X0<def> = COPY %vreg209; GPR64all:%vreg209
4560B		%X1<def> = COPY %vreg210; GPR64all:%vreg210
4576B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
4592B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4608B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4624B		STACKMAP 5, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0]
4640B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4656B		%vreg206<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg206
4672B		%X0<def> = COPY %vreg206; GPR64:%vreg206
4688B		RET_ReallyLR %X0<imp-use>

# End machine code for function BZ2_bzReadOpen.

********** SIMPLE REGISTER COALESCING **********
********** Function: BZ2_bzReadOpen
********** JOINING INTERVALS ***********
while.cond:
while.body:
if.then.21:
return:
4544B	%X0<def> = COPY %vreg209; GPR64all:%vreg209
	Considering merging %vreg209 with %X0
	Can only merge into reserved registers.
4560B	%X1<def> = COPY %vreg210; GPR64all:%vreg210
	Considering merging %vreg210 with %X1
	Can only merge into reserved registers.
4672B	%X0<def> = COPY %vreg206; GPR64:%vreg206
	Considering merging %vreg206 with %X0
	Can only merge into reserved registers.
if.end:
if.end.3:
lor.lhs.false.7:
lor.lhs.false.15:
if.end.24:
if.end.29:
1600B	%X0<def> = COPY %vreg50; GPR64:%vreg50
	Considering merging %vreg50 with %X0
	Can only merge into reserved registers.
1648B	%vreg49<def> = COPY %W0; GPR32:%vreg49
	Considering merging %vreg49 with %W0
	Can only merge into reserved registers.
if.end.33:
if.end.44:
if.end.52:
if.end.68:
lor.lhs.false:
land.lhs.true:
lor.lhs.false.9:
lor.lhs.false.11:
land.lhs.true.13:
land.lhs.true.17:
lor.lhs.false.19:
if.end.28:
1504B	%vreg204<def> = COPY %XZR; GPR64:%vreg204
	Considering merging %vreg204 with %XZR
		RHS = %vreg204 [1504r,1520r:0)  0@1504r
		updated: 1520B	STRXui %XZR, <fi#0>, 0; mem:ST8[FixedStack0]
	Success: %vreg204 -> %XZR
	Result = %XZR
if.then.30:
if.end.37:
1968B	%vreg193<def> = COPY %XZR; GPR64:%vreg193
	Considering merging %vreg193 with %XZR
		RHS = %vreg193 [1968r,1984r:0)  0@1968r
		updated: 1984B	STRXui %XZR, <fi#0>, 0; mem:ST8[FixedStack0]
	Success: %vreg193 -> %XZR
	Result = %XZR
if.end.38:
2064B	%X0<def> = COPY %vreg56; GPR64:%vreg56
	Considering merging %vreg56 with %X0
	Can only merge into reserved registers.
Remat: %X0<def> = MOVi64imm 5104
Shrink: %vreg56 [2032r,2064r:0)  0@2032r
All defs dead: 2032r	%vreg56<def,dead> = MOVi64imm 5104; GPR64:%vreg56
Shrunk: %vreg56 [2032r,2032d:0)  0@2032r
Deleting dead def 2032r	%vreg56<def,dead> = MOVi64imm 5104; GPR64:%vreg56
2112B	%vreg57<def> = COPY %X0; GPR64all:%vreg57
	Considering merging %vreg57 with %X0
	Can only merge into reserved registers.
if.then.41:
if.end.48:
2480B	%vreg182<def> = COPY %XZR; GPR64:%vreg182
	Considering merging %vreg182 with %XZR
		RHS = %vreg182 [2480r,2496r:0)  0@2480r
		updated: 2496B	STRXui %XZR, <fi#0>, 0; mem:ST8[FixedStack0]
	Success: %vreg182 -> %XZR
	Result = %XZR
if.end.49:
if.end.56:
2736B	%vreg66<def> = COPY %XZR; GPR64:%vreg66
	Considering merging %vreg66 with %XZR
		RHS = %vreg66 [2736r,3040r:0)  0@2736r
		updated: 3040B	STRXui %XZR, %vreg68, 636; mem:ST8[%opaque] GPR64common:%vreg68
		updated: 3008B	STRXui %XZR, %vreg70, 635; mem:ST8[%bzfree] GPR64common:%vreg70
		updated: 2976B	STRXui %XZR, %vreg72, 634; mem:ST8[%bzalloc] GPR64common:%vreg72
	Success: %vreg66 -> %XZR
	Result = %XZR
while.end:
3552B	%X0<def> = COPY %vreg100; GPR64:%vreg100
	Considering merging %vreg100 with %X0
	Can only merge into reserved registers.
3568B	%W1<def> = COPY %vreg97; GPR32:%vreg97
	Considering merging %vreg97 with %W1
	Can only merge into reserved registers.
3584B	%W2<def> = COPY %vreg96; GPR32:%vreg96
	Considering merging %vreg96 with %W2
	Can only merge into reserved registers.
3632B	%vreg95<def> = COPY %W0; GPR32:%vreg95
	Considering merging %vreg95 with %W0
	Can only merge into reserved registers.
if.then.65:
if.end.72:
4032B	%X0<def> = COPY %vreg139; GPR64all:%vreg139
	Considering merging %vreg139 with %X0
	Can only merge into reserved registers.
4080B	%vreg136<def> = COPY %XZR; GPR64:%vreg136
	Considering merging %vreg136 with %XZR
		RHS = %vreg136 [4080r,4144r:0)  0@4080r
		updated: 4144B	STRXui %XZR, <fi#0>, 0; mem:ST8[FixedStack0]
	Success: %vreg136 -> %XZR
	Result = %XZR
entry:
16B	%vreg19<def> = COPY %LR; GPR64:%vreg19
	Considering merging %vreg19 with %LR
	Can only merge into reserved registers.
32B	%vreg10<def> = COPY %W5; GPR32:%vreg10
	Considering merging %vreg10 with %W5
	Can only merge into reserved registers.
48B	%vreg8<def> = COPY %X4; GPR64:%vreg8
	Considering merging %vreg8 with %X4
	Can only merge into reserved registers.
64B	%vreg6<def> = COPY %W3; GPR32:%vreg6
	Considering merging %vreg6 with %W3
	Can only merge into reserved registers.
80B	%vreg4<def> = COPY %W2; GPR32:%vreg4
	Considering merging %vreg4 with %W2
	Can only merge into reserved registers.
96B	%vreg2<def> = COPY %X1; GPR64:%vreg2
	Considering merging %vreg2 with %X1
	Can only merge into reserved registers.
112B	%vreg0<def> = COPY %X0; GPR64:%vreg0
	Considering merging %vreg0 with %X0
	Can only merge into reserved registers.
304B	%X0<def> = COPY %vreg17; GPR64all:%vreg17
	Considering merging %vreg17 with %X0
	Can only merge into reserved registers.
320B	%X1<def> = COPY %vreg18; GPR64all:%vreg18
	Considering merging %vreg18 with %X1
	Can only merge into reserved registers.
368B	%vreg14<def> = COPY %XZR; GPR64:%vreg14
	Considering merging %vreg14 with %XZR
		RHS = %vreg14 [368r,528r:0)  0@368r
		updated: 528B	STRXui %XZR, <fi#7>, 0; mem:ST8[FixedStack7]
	Success: %vreg14 -> %XZR
	Result = %XZR
if.then:
if.then.2:
if.then.23:
if.then.26:
if.then.32:
if.then.35:
if.then.43:
if.then.46:
if.then.51:
if.then.54:
if.then.67:
if.then.70:
if.end.73:
4496B	%vreg209<def> = COPY %vreg208; GPR64all:%vreg209 GPR64sp:%vreg208
	Considering merging to GPR64sp with %vreg208 in %vreg209
		RHS = %vreg208 [4480r,4496r:0)  0@4480r
		LHS = %vreg209 [4496r,4544r:0)  0@4496r
		merge %vreg209:0@4496r into %vreg208:0@4480r --> @4480r
		erased:	4496r	%vreg209<def> = COPY %vreg208; GPR64all:%vreg209 GPR64sp:%vreg208
		updated: 4480B	%vreg209<def> = ADDXri %vreg207, <ga:@BZ2_bzReadOpen>[TF=34], 0; GPR64sp:%vreg209 GPR64common:%vreg207
	Success: %vreg208 -> %vreg209
	Result = %vreg209 [4480r,4544r:0)  0@4480r
4512B	%vreg210<def> = COPY %vreg19; GPR64all:%vreg210 GPR64:%vreg19
	Considering merging to GPR64 with %vreg19 in %vreg210
		RHS = %vreg19 [16r,4512r:0)  0@16r
		LHS = %vreg210 [4512r,4560r:0)  0@4512r
		merge %vreg210:0@4512r into %vreg19:0@16r --> @16r
		erased:	4512r	%vreg210<def> = COPY %vreg19; GPR64all:%vreg210 GPR64:%vreg19
		updated: 16B	%vreg210<def> = COPY %LR; GPR64:%vreg210
		updated: 272B	%vreg18<def> = COPY %vreg210; GPR64all:%vreg18 GPR64:%vreg210
	Success: %vreg19 -> %vreg210
	Result = %vreg210 [16r,4560r:0)  0@16r
2176B	%vreg55<def> = COPY %vreg57; GPR64:%vreg55 GPR64all:%vreg57
	Considering merging to GPR64 with %vreg57 in %vreg55
		RHS = %vreg57 [2112r,2176r:0)  0@2112r
		LHS = %vreg55 [2176r,2192r:0)  0@2176r
		merge %vreg55:0@2176r into %vreg57:0@2112r --> @2112r
		erased:	2176r	%vreg55<def> = COPY %vreg57; GPR64:%vreg55 GPR64all:%vreg57
		updated: 2112B	%vreg55<def> = COPY %X0; GPR64:%vreg55
	Success: %vreg57 -> %vreg55
	Result = %vreg55 [2112r,2192r:0)  0@2112r
4000B	%vreg139<def> = COPY %vreg140; GPR64all:%vreg139 GPR64:%vreg140
	Considering merging to GPR64 with %vreg140 in %vreg139
		RHS = %vreg140 [3984r,4000r:0)  0@3984r
		LHS = %vreg139 [4000r,4032r:0)  0@4000r
		merge %vreg139:0@4000r into %vreg140:0@3984r --> @3984r
		erased:	4000r	%vreg139<def> = COPY %vreg140; GPR64all:%vreg139 GPR64:%vreg140
		updated: 3984B	%vreg139<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg139
	Success: %vreg140 -> %vreg139
	Result = %vreg139 [3984r,4032r:0)  0@3984r
128B	%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
	Considering merging to GPR64 with %vreg0 in %vreg1
		RHS = %vreg0 [112r,128r:0)  0@112r
		LHS = %vreg1 [128r,432r:0)  0@128r
		merge %vreg1:0@128r into %vreg0:0@112r --> @112r
		erased:	128r	%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
		updated: 112B	%vreg1<def> = COPY %X0; GPR64:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [112r,432r:0)  0@112r
144B	%vreg3<def> = COPY %vreg2; GPR64:%vreg3,%vreg2
	Considering merging to GPR64 with %vreg2 in %vreg3
		RHS = %vreg2 [96r,144r:0)  0@96r
		LHS = %vreg3 [144r,448r:0)  0@144r
		merge %vreg3:0@144r into %vreg2:0@96r --> @96r
		erased:	144r	%vreg3<def> = COPY %vreg2; GPR64:%vreg3,%vreg2
		updated: 96B	%vreg3<def> = COPY %X1; GPR64:%vreg3
	Success: %vreg2 -> %vreg3
	Result = %vreg3 [96r,448r:0)  0@96r
160B	%vreg5<def> = COPY %vreg4; GPR32:%vreg5,%vreg4
	Considering merging to GPR32 with %vreg4 in %vreg5
		RHS = %vreg4 [80r,160r:0)  0@80r
		LHS = %vreg5 [160r,464r:0)  0@160r
		merge %vreg5:0@160r into %vreg4:0@80r --> @80r
		erased:	160r	%vreg5<def> = COPY %vreg4; GPR32:%vreg5,%vreg4
		updated: 80B	%vreg5<def> = COPY %W2; GPR32:%vreg5
	Success: %vreg4 -> %vreg5
	Result = %vreg5 [80r,464r:0)  0@80r
176B	%vreg7<def> = COPY %vreg6; GPR32:%vreg7,%vreg6
	Considering merging to GPR32 with %vreg6 in %vreg7
		RHS = %vreg6 [64r,176r:0)  0@64r
		LHS = %vreg7 [176r,480r:0)  0@176r
		merge %vreg7:0@176r into %vreg6:0@64r --> @64r
		erased:	176r	%vreg7<def> = COPY %vreg6; GPR32:%vreg7,%vreg6
		updated: 64B	%vreg7<def> = COPY %W3; GPR32:%vreg7
	Success: %vreg6 -> %vreg7
	Result = %vreg7 [64r,480r:0)  0@64r
192B	%vreg9<def> = COPY %vreg8; GPR64:%vreg9,%vreg8
	Considering merging to GPR64 with %vreg8 in %vreg9
		RHS = %vreg8 [48r,192r:0)  0@48r
		LHS = %vreg9 [192r,496r:0)  0@192r
		merge %vreg9:0@192r into %vreg8:0@48r --> @48r
		erased:	192r	%vreg9<def> = COPY %vreg8; GPR64:%vreg9,%vreg8
		updated: 48B	%vreg9<def> = COPY %X4; GPR64:%vreg9
	Success: %vreg8 -> %vreg9
	Result = %vreg9 [48r,496r:0)  0@48r
208B	%vreg11<def> = COPY %vreg10; GPR32:%vreg11,%vreg10
	Considering merging to GPR32 with %vreg10 in %vreg11
		RHS = %vreg10 [32r,208r:0)  0@32r
		LHS = %vreg11 [208r,512r:0)  0@208r
		merge %vreg11:0@208r into %vreg10:0@32r --> @32r
		erased:	208r	%vreg11<def> = COPY %vreg10; GPR32:%vreg11,%vreg10
		updated: 32B	%vreg11<def> = COPY %W5; GPR32:%vreg11
	Success: %vreg10 -> %vreg11
	Result = %vreg11 [32r,512r:0)  0@32r
256B	%vreg17<def> = COPY %vreg16; GPR64all:%vreg17 GPR64sp:%vreg16
	Considering merging to GPR64sp with %vreg16 in %vreg17
		RHS = %vreg16 [240r,256r:0)  0@240r
		LHS = %vreg17 [256r,304r:0)  0@256r
		merge %vreg17:0@256r into %vreg16:0@240r --> @240r
		erased:	256r	%vreg17<def> = COPY %vreg16; GPR64all:%vreg17 GPR64sp:%vreg16
		updated: 240B	%vreg17<def> = ADDXri %vreg15, <ga:@BZ2_bzReadOpen>[TF=34], 0; GPR64sp:%vreg17 GPR64common:%vreg15
	Success: %vreg16 -> %vreg17
	Result = %vreg17 [240r,304r:0)  0@240r
272B	%vreg18<def> = COPY %vreg210; GPR64all:%vreg18 GPR64:%vreg210
	Considering merging to GPR64 with %vreg210 in %vreg18
		RHS = %vreg210 [16r,4560r:0)  0@16r
		LHS = %vreg18 [272r,320r:0)  0@272r
		merge %vreg18:0@272r into %vreg210:0@16r --> @16r
		erased:	272r	%vreg18<def> = COPY %vreg210; GPR64all:%vreg18 GPR64:%vreg210
		updated: 16B	%vreg18<def> = COPY %LR; GPR64:%vreg18
		updated: 4560B	%X1<def> = COPY %vreg18; GPR64:%vreg18
	Success: %vreg210 -> %vreg18
	Result = %vreg18 [16r,4560r:0)  0@16r
4416B	%vreg104<def> = COPY %vreg105; GPR64:%vreg104,%vreg105
	Considering merging to GPR64 with %vreg105 in %vreg104
		RHS = %vreg105 [4400r,4416r:0)  0@4400r
		LHS = %vreg104 [4416r,4432r:0)  0@4416r
		merge %vreg104:0@4416r into %vreg105:0@4400r --> @4400r
		erased:	4416r	%vreg104<def> = COPY %vreg105; GPR64:%vreg104,%vreg105
		updated: 4400B	%vreg104<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg104
	Success: %vreg105 -> %vreg104
	Result = %vreg104 [4400r,4432r:0)  0@4400r
4544B	%X0<def> = COPY %vreg209; GPR64sp:%vreg209
	Considering merging %vreg209 with %X0
	Can only merge into reserved registers.
4560B	%X1<def> = COPY %vreg18; GPR64:%vreg18
	Considering merging %vreg18 with %X1
	Can only merge into reserved registers.
4032B	%X0<def> = COPY %vreg139; GPR64:%vreg139
	Considering merging %vreg139 with %X0
	Can only merge into reserved registers.
304B	%X0<def> = COPY %vreg17; GPR64sp:%vreg17
	Considering merging %vreg17 with %X0
	Can only merge into reserved registers.
320B	%X1<def> = COPY %vreg18; GPR64:%vreg18
	Considering merging %vreg18 with %X1
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
W30 [0B,16r:0)[336r,336d:12)[400e,400d:6)[1616r,1616d:11)[1680e,1680d:5)[2080r,2080d:10)[2144e,2144d:4)[3600r,3600d:9)[3664e,3664d:3)[4048r,4048d:8)[4112e,4112d:2)[4576r,4576d:7)[4624e,4624d:1)  0@0B-phi 1@4624e 2@4112e 3@3664e 4@2144e 5@1680e 6@400e 7@4576r 8@4048r 9@3600r 10@2080r 11@1616r 12@336r
WZR [848r,848d:3)[960r,960d:2)[1232r,1232d:1)[3088r,3088d:0)  0@3088r 1@1232r 2@960r 3@848r
W0 [0B,112r:0)[304r,336r:10)[1600r,1616r:9)[1616r,1648r:2)[2064r,2080r:8)[2080r,2112r:7)[3552r,3600r:6)[3600r,3632r:1)[4032r,4048r:5)[4544r,4576r:3)[4672r,4688r:4)  0@0B-phi 1@3600r 2@1616r 3@4544r 4@4672r 5@4032r 6@3552r 7@2080r 8@2064r 9@1600r 10@304r
W1 [0B,96r:0)[320r,336r:3)[3568r,3600r:1)[4560r,4576r:2)  0@0B-phi 1@3568r 2@4560r 3@320r
W2 [0B,80r:0)[3584r,3600r:1)  0@0B-phi 1@3584r
W3 [0B,64r:0)  0@0B-phi
W4 [0B,48r:0)  0@0B-phi
W5 [0B,32r:0)  0@0B-phi
%vreg1 [112r,432r:0)  0@112r
%vreg3 [96r,448r:0)  0@96r
%vreg5 [80r,464r:0)  0@80r
%vreg7 [64r,480r:0)  0@64r
%vreg9 [48r,496r:0)  0@48r
%vreg11 [32r,512r:0)  0@32r
%vreg13 [544r,560r:0)  0@544r
%vreg15 [224r,240r:0)  0@224r
%vreg17 [240r,304r:0)  0@240r
%vreg18 [16r,4560r:0)  0@16r
%vreg21 [592r,608r:0)  0@592r
%vreg23 [640r,656r:0)  0@640r
%vreg25 [688r,704r:0)  0@688r
%vreg27 [736r,752r:0)  0@736r
%vreg29 [784r,800r:0)  0@784r
%vreg31 [832r,848r:0)  0@832r
%vreg33 [896r,912r:0)  0@896r
%vreg35 [944r,960r:0)  0@944r
%vreg37 [1008r,1024r:0)  0@1008r
%vreg39 [1056r,1072r:0)  0@1056r
%vreg41 [1104r,1120r:0)  0@1104r
%vreg43 [1152r,1168r:0)  0@1152r
%vreg45 [1200r,1232r:0)  0@1200r
%vreg46 [1216r,1232r:0)  0@1216r
%vreg49 [1648r,1712r:0)  0@1648r
%vreg50 [1568r,1600r:0)  0@1568r
%vreg52 [2208r,2224r:0)  0@2208r
%vreg55 [2112r,2192r:0)  0@2112r
%vreg59 [2544r,2560r:0)  0@2544r
%vreg61 [2592r,2608r:0)  0@2592r
%vreg63 [2640r,2656r:0)  0@2640r
%vreg65 [2688r,2704r:0)  0@2688r
%vreg68 [3024r,3040r:0)  0@3024r
%vreg70 [2992r,3008r:0)  0@2992r
%vreg72 [2960r,2976r:0)  0@2960r
%vreg74 [2912r,2928r:0)  0@2912r
%vreg75 [2928r,2944r:0)  0@2928r
%vreg76 [2896r,2928r:0)  0@2896r
%vreg78 [2864r,2880r:0)  0@2864r
%vreg81 [2832r,2848r:0)  0@2832r
%vreg82 [2816r,2848r:0)  0@2816r
%vreg84 [2768r,2784r:0)  0@2768r
%vreg85 [2784r,2800r:0)  0@2784r
%vreg86 [2752r,2784r:0)  0@2752r
%vreg88 [3072r,3088r:0)  0@3072r
%vreg90 [3712r,3728r:0)  0@3712r
%vreg95 [3632r,3696r:0)  0@3632r
%vreg96 [3520r,3584r:0)  0@3520r
%vreg97 [3504r,3568r:0)  0@3504r
%vreg99 [3472r,3488r:0)  0@3472r
%vreg100 [3488r,3552r:0)  0@3488r
%vreg101 [3456r,3488r:0)  0@3456r
%vreg104 [4400r,4432r:0)  0@4400r
%vreg106 [4192r,4384r:0)  0@4192r
%vreg108 [4352r,4368r:0)  0@4352r
%vreg109 [4368r,4384r:0)  0@4368r
%vreg110 [4336r,4368r:0)  0@4336r
%vreg113 [4304r,4320r:0)  0@4304r
%vreg116 [4288r,4320r:0)  0@4288r
%vreg117 [4272r,4288r:0)  0@4272r
%vreg120 [4240r,4256r:0)  0@4240r
%vreg122 [4224r,4256r:0)  0@4224r
%vreg123 [4208r,4224r:0)  0@4208r
%vreg125 [3760r,3776r:0)  0@3760r
%vreg128 [3824r,3840r:0)  0@3824r
%vreg129 [3808r,3840r:0)  0@3808r
%vreg131 [3872r,3888r:0)  0@3872r
%vreg134 [3936r,3952r:0)  0@3936r
%vreg135 [3920r,3952r:0)  0@3920r
%vreg139 [3984r,4032r:0)  0@3984r
%vreg143 [3392r,3408r:0)  0@3392r
%vreg144 [3376r,3392r:0)  0@3376r
%vreg147 [3344r,3360r:0)  0@3344r
%vreg148 [3328r,3344r:0)  0@3328r
%vreg152 [3296r,3312r:0)  0@3296r
%vreg153 [3280r,3296r:0)  0@3280r
%vreg154 [3264r,3312r:0)  0@3264r
%vreg159 [3232r,3248r:0)  0@3232r
%vreg161 [3216r,3232r:0)  0@3216r
%vreg162 [3200r,3216r:0)  0@3200r
%vreg167 [3184r,3232r:0)  0@3184r
%vreg168 [3168r,3184r:0)  0@3168r
%vreg170 [3152r,3248r:0)  0@3152r
%vreg171 [3136r,3152r:0)  0@3136r
%vreg173 [2256r,2272r:0)  0@2256r
%vreg174 [2304r,2336r:0)  0@2304r
%vreg176 [2320r,2336r:0)  0@2320r
%vreg178 [2368r,2384r:0)  0@2368r
%vreg179 [2416r,2448r:0)  0@2416r
%vreg181 [2432r,2448r:0)  0@2432r
%vreg184 [1744r,1760r:0)  0@1744r
%vreg185 [1792r,1824r:0)  0@1792r
%vreg187 [1808r,1824r:0)  0@1808r
%vreg189 [1856r,1872r:0)  0@1856r
%vreg190 [1904r,1936r:0)  0@1904r
%vreg192 [1920r,1936r:0)  0@1920r
%vreg195 [1280r,1296r:0)  0@1280r
%vreg196 [1328r,1360r:0)  0@1328r
%vreg198 [1344r,1360r:0)  0@1344r
%vreg200 [1392r,1408r:0)  0@1392r
%vreg201 [1440r,1472r:0)  0@1440r
%vreg203 [1456r,1472r:0)  0@1456r
%vreg206 [4656r,4672r:0)  0@4656r
%vreg207 [4464r,4480r:0)  0@4464r
%vreg209 [4480r,4544r:0)  0@4480r
RegMasks: 336r 1616r 2080r 3600r 4048r 4576r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzReadOpen: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=8, align=8, at location [SP]
  fi#3: size=4, align=4, at location [SP]
  fi#4: size=4, align=4, at location [SP]
  fi#5: size=8, align=8, at location [SP]
  fi#6: size=4, align=4, at location [SP]
  fi#7: size=8, align=8, at location [SP]
  fi#8: size=4, align=4, at location [SP]
Function Live Ins: %X0 in %vreg0, %X1 in %vreg2, %W2 in %vreg4, %W3 in %vreg6, %X4 in %vreg8, %W5 in %vreg10, %LR in %vreg19

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %X1 %W2 %W3 %X4 %W5 %LR
16B		%vreg18<def> = COPY %LR; GPR64:%vreg18
32B		%vreg11<def> = COPY %W5; GPR32:%vreg11
48B		%vreg9<def> = COPY %X4; GPR64:%vreg9
64B		%vreg7<def> = COPY %W3; GPR32:%vreg7
80B		%vreg5<def> = COPY %W2; GPR32:%vreg5
96B		%vreg3<def> = COPY %X1; GPR64:%vreg3
112B		%vreg1<def> = COPY %X0; GPR64:%vreg1
224B		%vreg15<def> = ADRP <ga:@BZ2_bzReadOpen>[TF=1]; GPR64common:%vreg15
240B		%vreg17<def> = ADDXri %vreg15, <ga:@BZ2_bzReadOpen>[TF=34], 0; GPR64sp:%vreg17 GPR64common:%vreg15
288B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
304B		%X0<def> = COPY %vreg17; GPR64sp:%vreg17
320B		%X1<def> = COPY %vreg18; GPR64:%vreg18
336B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
352B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
384B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
400B		STACKMAP 0, 0, %vreg1, 0, <fi#1>, 0, 0, <fi#7>, 0, %vreg3, 0, <fi#2>, 0, %vreg11, 0, <fi#6>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, %vreg7, 0, <fi#4>, 0, %vreg9, 0, <fi#5>, 0, %vreg5, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack8](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5] LD8[FixedStack3](align=4) GPR64:%vreg1,%vreg3,%vreg9 GPR32:%vreg11,%vreg7,%vreg5
416B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
432B		STRXui %vreg1, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg1
448B		STRXui %vreg3, <fi#2>, 0; mem:ST8[FixedStack2] GPR64:%vreg3
464B		STRWui %vreg5, <fi#3>, 0; mem:ST4[FixedStack3] GPR32:%vreg5
480B		STRWui %vreg7, <fi#4>, 0; mem:ST4[FixedStack4] GPR32:%vreg7
496B		STRXui %vreg9, <fi#5>, 0; mem:ST8[FixedStack5] GPR64:%vreg9
512B		STRWui %vreg11, <fi#6>, 0; mem:ST4[FixedStack6] GPR32:%vreg11
528B		STRXui %XZR, <fi#7>, 0; mem:ST8[FixedStack7]
544B		%vreg13<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg13
560B		CBZX %vreg13, <BB#2>; GPR64:%vreg13
	    Successors according to CFG: BB#2 BB#1

576B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
592B		%vreg21<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg21
608B		STRWui %WZR, %vreg21, 0; mem:ST4[%1] GPR64common:%vreg21
	    Successors according to CFG: BB#2

624B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#1
640B		%vreg23<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg23
656B		CBZX %vreg23, <BB#4>; GPR64:%vreg23
	    Successors according to CFG: BB#4 BB#3

672B	BB#3: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#2
688B		%vreg25<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg25
704B		STRWui %WZR, %vreg25, 1274; mem:ST4[%lastErr] GPR64common:%vreg25
	    Successors according to CFG: BB#4

720B	BB#4: derived from LLVM BB %if.end.3
	    Predecessors according to CFG: BB#2 BB#3
736B		%vreg27<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg27
752B		CBZX %vreg27, <BB#14>; GPR64:%vreg27
	    Successors according to CFG: BB#14 BB#5

768B	BB#5: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#4
784B		%vreg29<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg29
800B		CBZW %vreg29, <BB#7>; GPR32:%vreg29
	    Successors according to CFG: BB#7 BB#6

816B	BB#6: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#5
832B		%vreg31<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32common:%vreg31
848B		%WZR<def> = SUBSWri %vreg31, 1, 0, %NZCV<imp-def>; GPR32common:%vreg31
864B		Bcc 1, <BB#14>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#14 BB#7

880B	BB#7: derived from LLVM BB %lor.lhs.false.7
	    Predecessors according to CFG: BB#5 BB#6
896B		%vreg33<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg33
912B		TBNZW %vreg33, 31, <BB#14>; GPR32:%vreg33
	    Successors according to CFG: BB#14 BB#8

928B	BB#8: derived from LLVM BB %lor.lhs.false.9
	    Predecessors according to CFG: BB#7
944B		%vreg35<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32common:%vreg35
960B		%WZR<def> = SUBSWri %vreg35, 4, 0, %NZCV<imp-def>; GPR32common:%vreg35
976B		Bcc 12, <BB#14>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#14 BB#9

992B	BB#9: derived from LLVM BB %lor.lhs.false.11
	    Predecessors according to CFG: BB#8
1008B		%vreg37<def> = LDRXui <fi#5>, 0; mem:LD8[FixedStack5] GPR64:%vreg37
1024B		CBNZX %vreg37, <BB#11>; GPR64:%vreg37
	    Successors according to CFG: BB#11 BB#10

1040B	BB#10: derived from LLVM BB %land.lhs.true.13
	    Predecessors according to CFG: BB#9
1056B		%vreg39<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg39
1072B		CBNZW %vreg39, <BB#14>; GPR32:%vreg39
	    Successors according to CFG: BB#14 BB#11

1088B	BB#11: derived from LLVM BB %lor.lhs.false.15
	    Predecessors according to CFG: BB#9 BB#10
1104B		%vreg41<def> = LDRXui <fi#5>, 0; mem:LD8[FixedStack5] GPR64:%vreg41
1120B		CBZX %vreg41, <BB#19>; GPR64:%vreg41
	    Successors according to CFG: BB#19 BB#12

1136B	BB#12: derived from LLVM BB %land.lhs.true.17
	    Predecessors according to CFG: BB#11
1152B		%vreg43<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg43
1168B		TBNZW %vreg43, 31, <BB#14>; GPR32:%vreg43
	    Successors according to CFG: BB#14 BB#13

1184B	BB#13: derived from LLVM BB %lor.lhs.false.19
	    Predecessors according to CFG: BB#12
1200B		%vreg45<def> = MOVi32imm 5000; GPR32:%vreg45
1216B		%vreg46<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg46
1232B		%WZR<def> = SUBSWrr %vreg46, %vreg45, %NZCV<imp-def>; GPR32:%vreg46,%vreg45
1248B		Bcc 13, <BB#19>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#19 BB#14

1264B	BB#14: derived from LLVM BB %if.then.21
	    Predecessors according to CFG: BB#4 BB#6 BB#7 BB#8 BB#10 BB#12 BB#13
1280B		%vreg195<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg195
1296B		CBZX %vreg195, <BB#16>; GPR64:%vreg195
	    Successors according to CFG: BB#16 BB#15

1312B	BB#15: derived from LLVM BB %if.then.23
	    Predecessors according to CFG: BB#14
1328B		%vreg196<def> = MOVi32imm 4294967294; GPR32:%vreg196
1344B		%vreg198<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg198
1360B		STRWui %vreg196, %vreg198, 0; mem:ST4[%15] GPR32:%vreg196 GPR64common:%vreg198
	    Successors according to CFG: BB#16

1376B	BB#16: derived from LLVM BB %if.end.24
	    Predecessors according to CFG: BB#14 BB#15
1392B		%vreg200<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg200
1408B		CBZX %vreg200, <BB#18>; GPR64:%vreg200
	    Successors according to CFG: BB#18 BB#17

1424B	BB#17: derived from LLVM BB %if.then.26
	    Predecessors according to CFG: BB#16
1440B		%vreg201<def> = MOVi32imm 4294967294; GPR32:%vreg201
1456B		%vreg203<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg203
1472B		STRWui %vreg201, %vreg203, 1274; mem:ST4[%lastErr27] GPR32:%vreg201 GPR64common:%vreg203
	    Successors according to CFG: BB#18

1488B	BB#18: derived from LLVM BB %if.end.28
	    Predecessors according to CFG: BB#16 BB#17
1520B		STRXui %XZR, <fi#0>, 0; mem:ST8[FixedStack0]
1536B		B <BB#45>
	    Successors according to CFG: BB#45

1552B	BB#19: derived from LLVM BB %if.end.29
	    Predecessors according to CFG: BB#11 BB#13
1568B		%vreg50<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg50
1584B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1600B		%X0<def> = COPY %vreg50; GPR64:%vreg50
1616B		BL <ga:@ferror>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
1632B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1648B		%vreg49<def> = COPY %W0; GPR32:%vreg49
1664B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1680B		STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#2>, 0, 0, <fi#6>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack8](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5] LD8[FixedStack3](align=4)
1696B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1712B		CBZW %vreg49, <BB#25>; GPR32:%vreg49
	    Successors according to CFG: BB#25 BB#20

1728B	BB#20: derived from LLVM BB %if.then.30
	    Predecessors according to CFG: BB#19
1744B		%vreg184<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg184
1760B		CBZX %vreg184, <BB#22>; GPR64:%vreg184
	    Successors according to CFG: BB#22 BB#21

1776B	BB#21: derived from LLVM BB %if.then.32
	    Predecessors according to CFG: BB#20
1792B		%vreg185<def> = MOVi32imm 4294967290; GPR32:%vreg185
1808B		%vreg187<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg187
1824B		STRWui %vreg185, %vreg187, 0; mem:ST4[%20] GPR32:%vreg185 GPR64common:%vreg187
	    Successors according to CFG: BB#22

1840B	BB#22: derived from LLVM BB %if.end.33
	    Predecessors according to CFG: BB#20 BB#21
1856B		%vreg189<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg189
1872B		CBZX %vreg189, <BB#24>; GPR64:%vreg189
	    Successors according to CFG: BB#24 BB#23

1888B	BB#23: derived from LLVM BB %if.then.35
	    Predecessors according to CFG: BB#22
1904B		%vreg190<def> = MOVi32imm 4294967290; GPR32:%vreg190
1920B		%vreg192<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg192
1936B		STRWui %vreg190, %vreg192, 1274; mem:ST4[%lastErr36] GPR32:%vreg190 GPR64common:%vreg192
	    Successors according to CFG: BB#24

1952B	BB#24: derived from LLVM BB %if.end.37
	    Predecessors according to CFG: BB#22 BB#23
1984B		STRXui %XZR, <fi#0>, 0; mem:ST8[FixedStack0]
2000B		B <BB#45>
	    Successors according to CFG: BB#45

2016B	BB#25: derived from LLVM BB %if.end.38
	    Predecessors according to CFG: BB#19
2048B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2064B		%X0<def> = MOVi64imm 5104
2080B		BL <ga:@malloc>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X0<imp-def>
2096B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2112B		%vreg55<def> = COPY %X0; GPR64:%vreg55
2128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2144B		STACKMAP 2, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#2>, 0, 0, <fi#6>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack8](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5] LD8[FixedStack3](align=4)
2160B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2192B		STRXui %vreg55, <fi#7>, 0; mem:ST8[FixedStack7] GPR64:%vreg55
2208B		%vreg52<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg52
2224B		CBNZX %vreg52, <BB#31>; GPR64:%vreg52
	    Successors according to CFG: BB#31 BB#26

2240B	BB#26: derived from LLVM BB %if.then.41
	    Predecessors according to CFG: BB#25
2256B		%vreg173<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg173
2272B		CBZX %vreg173, <BB#28>; GPR64:%vreg173
	    Successors according to CFG: BB#28 BB#27

2288B	BB#27: derived from LLVM BB %if.then.43
	    Predecessors according to CFG: BB#26
2304B		%vreg174<def> = MOVi32imm 4294967293; GPR32:%vreg174
2320B		%vreg176<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg176
2336B		STRWui %vreg174, %vreg176, 0; mem:ST4[%26] GPR32:%vreg174 GPR64common:%vreg176
	    Successors according to CFG: BB#28

2352B	BB#28: derived from LLVM BB %if.end.44
	    Predecessors according to CFG: BB#26 BB#27
2368B		%vreg178<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg178
2384B		CBZX %vreg178, <BB#30>; GPR64:%vreg178
	    Successors according to CFG: BB#30 BB#29

2400B	BB#29: derived from LLVM BB %if.then.46
	    Predecessors according to CFG: BB#28
2416B		%vreg179<def> = MOVi32imm 4294967293; GPR32:%vreg179
2432B		%vreg181<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg181
2448B		STRWui %vreg179, %vreg181, 1274; mem:ST4[%lastErr47] GPR32:%vreg179 GPR64common:%vreg181
	    Successors according to CFG: BB#30

2464B	BB#30: derived from LLVM BB %if.end.48
	    Predecessors according to CFG: BB#28 BB#29
2496B		STRXui %XZR, <fi#0>, 0; mem:ST8[FixedStack0]
2512B		B <BB#45>
	    Successors according to CFG: BB#45

2528B	BB#31: derived from LLVM BB %if.end.49
	    Predecessors according to CFG: BB#25
2544B		%vreg59<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg59
2560B		CBZX %vreg59, <BB#33>; GPR64:%vreg59
	    Successors according to CFG: BB#33 BB#32

2576B	BB#32: derived from LLVM BB %if.then.51
	    Predecessors according to CFG: BB#31
2592B		%vreg61<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg61
2608B		STRWui %WZR, %vreg61, 0; mem:ST4[%30] GPR64common:%vreg61
	    Successors according to CFG: BB#33

2624B	BB#33: derived from LLVM BB %if.end.52
	    Predecessors according to CFG: BB#31 BB#32
2640B		%vreg63<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg63
2656B		CBZX %vreg63, <BB#35>; GPR64:%vreg63
	    Successors according to CFG: BB#35 BB#34

2672B	BB#34: derived from LLVM BB %if.then.54
	    Predecessors according to CFG: BB#33
2688B		%vreg65<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg65
2704B		STRWui %WZR, %vreg65, 1274; mem:ST4[%lastErr55] GPR64common:%vreg65
	    Successors according to CFG: BB#35

2720B	BB#35: derived from LLVM BB %if.end.56
	    Predecessors according to CFG: BB#33 BB#34
2752B		%vreg86<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg86
2768B		%vreg84<def> = MOVi64imm 5100; GPR64:%vreg84
2784B		%vreg85<def> = ADDXrr %vreg86, %vreg84; GPR64common:%vreg85 GPR64:%vreg86,%vreg84
2800B		STRBBui %WZR, %vreg85, 0; mem:ST1[%initialisedOk] GPR64common:%vreg85
2816B		%vreg82<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg82
2832B		%vreg81<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg81
2848B		STRXui %vreg82, %vreg81, 0; mem:ST8[%handle] GPR64:%vreg82 GPR64common:%vreg81
2864B		%vreg78<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg78
2880B		STRWui %WZR, %vreg78, 1252; mem:ST4[%bufN] GPR64common:%vreg78
2896B		%vreg76<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg76
2912B		%vreg74<def> = MOVi64imm 5012; GPR64:%vreg74
2928B		%vreg75<def> = ADDXrr %vreg76, %vreg74; GPR64common:%vreg75 GPR64:%vreg76,%vreg74
2944B		STRBBui %WZR, %vreg75, 0; mem:ST1[%writing] GPR64common:%vreg75
2960B		%vreg72<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg72
2976B		STRXui %XZR, %vreg72, 634; mem:ST8[%bzalloc] GPR64common:%vreg72
2992B		%vreg70<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg70
3008B		STRXui %XZR, %vreg70, 635; mem:ST8[%bzfree] GPR64common:%vreg70
3024B		%vreg68<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg68
3040B		STRXui %XZR, %vreg68, 636; mem:ST8[%opaque] GPR64common:%vreg68
	    Successors according to CFG: BB#36

3056B	BB#36: derived from LLVM BB %while.cond
	    Predecessors according to CFG: BB#35 BB#37
3072B		%vreg88<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32common:%vreg88
3088B		%WZR<def> = SUBSWri %vreg88, 0, 0, %NZCV<imp-def>; GPR32common:%vreg88
3104B		Bcc 13, <BB#38>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#38 BB#37

3120B	BB#37: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#36
3136B		%vreg171<def> = LDRXui <fi#5>, 0; mem:LD8[FixedStack5] GPR64common:%vreg171
3152B		%vreg170<def> = LDRBBui %vreg171, 0; mem:LD1[%42] GPR32:%vreg170 GPR64common:%vreg171
3168B		%vreg168<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg168
3184B		%vreg167<def> = LDRSWui %vreg168, 1252; mem:LD4[%bufN60] GPR64:%vreg167 GPR64common:%vreg168
3200B		%vreg162<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg162
3216B		%vreg161<def> = ADDXri %vreg162, 8, 0; GPR64common:%vreg161,%vreg162
3232B		%vreg159<def> = ADDXrr %vreg161, %vreg167; GPR64common:%vreg159,%vreg161 GPR64:%vreg167
3248B		STRBBui %vreg170, %vreg159, 0; mem:ST1[%arrayidx] GPR32:%vreg170 GPR64common:%vreg159
3264B		%vreg154<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg154
3280B		%vreg153<def> = LDRWui %vreg154, 1252; mem:LD4[%bufN61] GPR32common:%vreg153 GPR64common:%vreg154
3296B		%vreg152<def> = ADDWri %vreg153, 1, 0; GPR32common:%vreg152,%vreg153
3312B		STRWui %vreg152, %vreg154, 1252; mem:ST4[%bufN61] GPR32common:%vreg152 GPR64common:%vreg154
3328B		%vreg148<def> = LDRXui <fi#5>, 0; mem:LD8[FixedStack5] GPR64common:%vreg148
3344B		%vreg147<def> = ADDXri %vreg148, 1, 0; GPR64common:%vreg147,%vreg148
3360B		STRXui %vreg147, <fi#5>, 0; mem:ST8[FixedStack5] GPR64common:%vreg147
3376B		%vreg144<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32common:%vreg144
3392B		%vreg143<def> = SUBWri %vreg144, 1, 0; GPR32common:%vreg143,%vreg144
3408B		STRWui %vreg143, <fi#6>, 0; mem:ST4[FixedStack6] GPR32common:%vreg143
3424B		B <BB#36>
	    Successors according to CFG: BB#36

3440B	BB#38: derived from LLVM BB %while.end
	    Predecessors according to CFG: BB#36
3456B		%vreg101<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg101
3472B		%vreg99<def> = MOVi64imm 5016; GPR64:%vreg99
3488B		%vreg100<def> = ADDXrr %vreg101, %vreg99; GPR64:%vreg100,%vreg101,%vreg99
3504B		%vreg97<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg97
3520B		%vreg96<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg96
3536B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3552B		%X0<def> = COPY %vreg100; GPR64:%vreg100
3568B		%W1<def> = COPY %vreg97; GPR32:%vreg97
3584B		%W2<def> = COPY %vreg96; GPR32:%vreg96
3600B		BL <ga:@BZ2_bzDecompressInit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %W2<imp-use>, %W0<imp-def>
3616B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3632B		%vreg95<def> = COPY %W0; GPR32:%vreg95
3648B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3664B		STACKMAP 3, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack8](align=4) LD8[FixedStack0]
3680B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3696B		STRWui %vreg95, <fi#8>, 0; mem:ST4[FixedStack8] GPR32:%vreg95
3712B		%vreg90<def> = LDRWui <fi#8>, 0; mem:LD4[FixedStack8] GPR32:%vreg90
3728B		CBZW %vreg90, <BB#44>; GPR32:%vreg90
	    Successors according to CFG: BB#44 BB#39

3744B	BB#39: derived from LLVM BB %if.then.65
	    Predecessors according to CFG: BB#38
3760B		%vreg125<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg125
3776B		CBZX %vreg125, <BB#41>; GPR64:%vreg125
	    Successors according to CFG: BB#41 BB#40

3792B	BB#40: derived from LLVM BB %if.then.67
	    Predecessors according to CFG: BB#39
3808B		%vreg129<def> = LDRWui <fi#8>, 0; mem:LD4[FixedStack8] GPR32:%vreg129
3824B		%vreg128<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg128
3840B		STRWui %vreg129, %vreg128, 0; mem:ST4[%57] GPR32:%vreg129 GPR64common:%vreg128
	    Successors according to CFG: BB#41

3856B	BB#41: derived from LLVM BB %if.end.68
	    Predecessors according to CFG: BB#39 BB#40
3872B		%vreg131<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg131
3888B		CBZX %vreg131, <BB#43>; GPR64:%vreg131
	    Successors according to CFG: BB#43 BB#42

3904B	BB#42: derived from LLVM BB %if.then.70
	    Predecessors according to CFG: BB#41
3920B		%vreg135<def> = LDRWui <fi#8>, 0; mem:LD4[FixedStack8] GPR32:%vreg135
3936B		%vreg134<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg134
3952B		STRWui %vreg135, %vreg134, 1274; mem:ST4[%lastErr71] GPR32:%vreg135 GPR64common:%vreg134
	    Successors according to CFG: BB#43

3968B	BB#43: derived from LLVM BB %if.end.72
	    Predecessors according to CFG: BB#41 BB#42
3984B		%vreg139<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg139
4016B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4032B		%X0<def> = COPY %vreg139; GPR64:%vreg139
4048B		BL <ga:@free>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>
4064B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4096B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4112B		STACKMAP 4, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0]
4128B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4144B		STRXui %XZR, <fi#0>, 0; mem:ST8[FixedStack0]
4160B		B <BB#45>
	    Successors according to CFG: BB#45

4176B	BB#44: derived from LLVM BB %if.end.73
	    Predecessors according to CFG: BB#38
4192B		%vreg106<def> = MOVi32imm 1; GPR32:%vreg106
4208B		%vreg123<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg123
4224B		%vreg122<def> = LDRWui %vreg123, 1252; mem:LD4[%bufN74] GPR32:%vreg122 GPR64common:%vreg123
4240B		%vreg120<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg120
4256B		STRWui %vreg122, %vreg120, 1256; mem:ST4[%avail_in] GPR32:%vreg122 GPR64common:%vreg120
4272B		%vreg117<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg117
4288B		%vreg116<def> = ADDXri %vreg117, 8, 0; GPR64common:%vreg116,%vreg117
4304B		%vreg113<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg113
4320B		STRXui %vreg116, %vreg113, 627; mem:ST8[%next_in] GPR64common:%vreg116,%vreg113
4336B		%vreg110<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg110
4352B		%vreg108<def> = MOVi64imm 5100; GPR64:%vreg108
4368B		%vreg109<def> = ADDXrr %vreg110, %vreg108; GPR64common:%vreg109 GPR64:%vreg110,%vreg108
4384B		STRBBui %vreg106, %vreg109, 0; mem:ST1[%initialisedOk78] GPR32:%vreg106 GPR64common:%vreg109
4400B		%vreg104<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg104
4432B		STRXui %vreg104, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg104
	    Successors according to CFG: BB#45

4448B	BB#45: derived from LLVM BB %return
	    Predecessors according to CFG: BB#44 BB#43 BB#30 BB#24 BB#18
4464B		%vreg207<def> = ADRP <ga:@BZ2_bzReadOpen>[TF=1]; GPR64common:%vreg207
4480B		%vreg209<def> = ADDXri %vreg207, <ga:@BZ2_bzReadOpen>[TF=34], 0; GPR64sp:%vreg209 GPR64common:%vreg207
4528B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4544B		%X0<def> = COPY %vreg209; GPR64sp:%vreg209
4560B		%X1<def> = COPY %vreg18; GPR64:%vreg18
4576B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
4592B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4608B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4624B		STACKMAP 5, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0]
4640B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4656B		%vreg206<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg206
4672B		%X0<def> = COPY %vreg206; GPR64:%vreg206
4688B		RET_ReallyLR %X0<imp-use>

# End machine code for function BZ2_bzReadOpen.

handleMove 1200B -> 1224B: %vreg45<def> = MOVi32imm 5000; GPR32:%vreg45
     %vreg45:	[1200r,1232r:0)  0@1200r
        -->	[1224r,1232r:0)  0@1224r
handleMove 1328B -> 1352B: %vreg196<def> = MOVi32imm 4294967294; GPR32:%vreg196
     %vreg196:	[1328r,1360r:0)  0@1328r
        -->	[1352r,1360r:0)  0@1352r
handleMove 1440B -> 1464B: %vreg201<def> = MOVi32imm 4294967294; GPR32:%vreg201
     %vreg201:	[1440r,1472r:0)  0@1440r
        -->	[1464r,1472r:0)  0@1464r
handleMove 1792B -> 1816B: %vreg185<def> = MOVi32imm 4294967290; GPR32:%vreg185
     %vreg185:	[1792r,1824r:0)  0@1792r
        -->	[1816r,1824r:0)  0@1816r
handleMove 1904B -> 1928B: %vreg190<def> = MOVi32imm 4294967290; GPR32:%vreg190
     %vreg190:	[1904r,1936r:0)  0@1904r
        -->	[1928r,1936r:0)  0@1928r
handleMove 2304B -> 2328B: %vreg174<def> = MOVi32imm 4294967293; GPR32:%vreg174
     %vreg174:	[2304r,2336r:0)  0@2304r
        -->	[2328r,2336r:0)  0@2328r
handleMove 2416B -> 2440B: %vreg179<def> = MOVi32imm 4294967293; GPR32:%vreg179
     %vreg179:	[2416r,2448r:0)  0@2416r
        -->	[2440r,2448r:0)  0@2440r
AllocationOrder(GPR32sponly) = [ ]
AllocationOrder(GPR32sponly) = [ ]
handleMove 3152B -> 3208B: %vreg170<def> = LDRBBui %vreg171, 0; mem:LD1[%42] GPR32:%vreg170 GPR64common:%vreg171
     %vreg170:	[3152r,3248r:0)  0@3152r
        -->	[3208r,3248r:0)  0@3208r
     %vreg171:	[3136r,3152r:0)  0@3136r
        -->	[3136r,3208r:0)  0@3136r
handleMove 3184B -> 3204B: %vreg167<def> = LDRSWui %vreg168, 1252; mem:LD4[%bufN60] GPR64:%vreg167 GPR64common:%vreg168
     %vreg167:	[3184r,3232r:0)  0@3184r
        -->	[3204r,3232r:0)  0@3204r
     %vreg168:	[3168r,3184r:0)  0@3168r
        -->	[3168r,3204r:0)  0@3168r
handleMove 3136B -> 3176B: %vreg171<def> = LDRXui <fi#5>, 0; mem:LD8[FixedStack5] GPR64common:%vreg171
     %vreg171:	[3136r,3208r:0)  0@3136r
        -->	[3176r,3208r:0)  0@3176r
handleMove 3488B -> 3528B: %vreg100<def> = ADDXrr %vreg101, %vreg99; GPR64:%vreg100,%vreg101,%vreg99
     %vreg100:	[3488r,3552r:0)  0@3488r
        -->	[3528r,3552r:0)  0@3528r
     %vreg101:	[3456r,3488r:0)  0@3456r
        -->	[3456r,3528r:0)  0@3456r
     %vreg99:	[3472r,3488r:0)  0@3472r
        -->	[3472r,3528r:0)  0@3472r
handleMove 3472B -> 3524B: %vreg99<def> = MOVi64imm 5016; GPR64:%vreg99
     %vreg99:	[3472r,3528r:0)  0@3472r
        -->	[3524r,3528r:0)  0@3524r
handleMove 4192B -> 4344B: %vreg106<def> = MOVi32imm 1; GPR32:%vreg106
     %vreg106:	[4192r,4384r:0)  0@4192r
        -->	[4344r,4384r:0)  0@4344r
handleMove 4288B -> 4312B: %vreg116<def> = ADDXri %vreg117, 8, 0; GPR64common:%vreg116,%vreg117
     %vreg116:	[4288r,4320r:0)  0@4288r
        -->	[4312r,4320r:0)  0@4312r
     %vreg117:	[4272r,4288r:0)  0@4272r
        -->	[4272r,4312r:0)  0@4272r
********** GREEDY REGISTER ALLOCATION **********
********** Function: BZ2_bzReadOpen
********** INTERVALS **********
W30 [0B,16r:0)[336r,336d:12)[400e,400d:6)[1616r,1616d:11)[1680e,1680d:5)[2080r,2080d:10)[2144e,2144d:4)[3600r,3600d:9)[3664e,3664d:3)[4048r,4048d:8)[4112e,4112d:2)[4576r,4576d:7)[4624e,4624d:1)  0@0B-phi 1@4624e 2@4112e 3@3664e 4@2144e 5@1680e 6@400e 7@4576r 8@4048r 9@3600r 10@2080r 11@1616r 12@336r
WZR [848r,848d:3)[960r,960d:2)[1232r,1232d:1)[3088r,3088d:0)  0@3088r 1@1232r 2@960r 3@848r
W0 [0B,112r:0)[304r,336r:10)[1600r,1616r:9)[1616r,1648r:2)[2064r,2080r:8)[2080r,2112r:7)[3552r,3600r:6)[3600r,3632r:1)[4032r,4048r:5)[4544r,4576r:3)[4672r,4688r:4)  0@0B-phi 1@3600r 2@1616r 3@4544r 4@4672r 5@4032r 6@3552r 7@2080r 8@2064r 9@1600r 10@304r
W1 [0B,96r:0)[320r,336r:3)[3568r,3600r:1)[4560r,4576r:2)  0@0B-phi 1@3568r 2@4560r 3@320r
W2 [0B,80r:0)[3584r,3600r:1)  0@0B-phi 1@3584r
W3 [0B,64r:0)  0@0B-phi
W4 [0B,48r:0)  0@0B-phi
W5 [0B,32r:0)  0@0B-phi
%vreg1 [112r,432r:0)  0@112r
%vreg3 [96r,448r:0)  0@96r
%vreg5 [80r,464r:0)  0@80r
%vreg7 [64r,480r:0)  0@64r
%vreg9 [48r,496r:0)  0@48r
%vreg11 [32r,512r:0)  0@32r
%vreg13 [544r,560r:0)  0@544r
%vreg15 [224r,240r:0)  0@224r
%vreg17 [240r,304r:0)  0@240r
%vreg18 [16r,4560r:0)  0@16r
%vreg21 [592r,608r:0)  0@592r
%vreg23 [640r,656r:0)  0@640r
%vreg25 [688r,704r:0)  0@688r
%vreg27 [736r,752r:0)  0@736r
%vreg29 [784r,800r:0)  0@784r
%vreg31 [832r,848r:0)  0@832r
%vreg33 [896r,912r:0)  0@896r
%vreg35 [944r,960r:0)  0@944r
%vreg37 [1008r,1024r:0)  0@1008r
%vreg39 [1056r,1072r:0)  0@1056r
%vreg41 [1104r,1120r:0)  0@1104r
%vreg43 [1152r,1168r:0)  0@1152r
%vreg45 [1224r,1232r:0)  0@1224r
%vreg46 [1216r,1232r:0)  0@1216r
%vreg49 [1648r,1712r:0)  0@1648r
%vreg50 [1568r,1600r:0)  0@1568r
%vreg52 [2208r,2224r:0)  0@2208r
%vreg55 [2112r,2192r:0)  0@2112r
%vreg59 [2544r,2560r:0)  0@2544r
%vreg61 [2592r,2608r:0)  0@2592r
%vreg63 [2640r,2656r:0)  0@2640r
%vreg65 [2688r,2704r:0)  0@2688r
%vreg68 [3024r,3040r:0)  0@3024r
%vreg70 [2992r,3008r:0)  0@2992r
%vreg72 [2960r,2976r:0)  0@2960r
%vreg74 [2912r,2928r:0)  0@2912r
%vreg75 [2928r,2944r:0)  0@2928r
%vreg76 [2896r,2928r:0)  0@2896r
%vreg78 [2864r,2880r:0)  0@2864r
%vreg81 [2832r,2848r:0)  0@2832r
%vreg82 [2816r,2848r:0)  0@2816r
%vreg84 [2768r,2784r:0)  0@2768r
%vreg85 [2784r,2800r:0)  0@2784r
%vreg86 [2752r,2784r:0)  0@2752r
%vreg88 [3072r,3088r:0)  0@3072r
%vreg90 [3712r,3728r:0)  0@3712r
%vreg95 [3632r,3696r:0)  0@3632r
%vreg96 [3520r,3584r:0)  0@3520r
%vreg97 [3504r,3568r:0)  0@3504r
%vreg99 [3524r,3528r:0)  0@3524r
%vreg100 [3528r,3552r:0)  0@3528r
%vreg101 [3456r,3528r:0)  0@3456r
%vreg104 [4400r,4432r:0)  0@4400r
%vreg106 [4344r,4384r:0)  0@4344r
%vreg108 [4352r,4368r:0)  0@4352r
%vreg109 [4368r,4384r:0)  0@4368r
%vreg110 [4336r,4368r:0)  0@4336r
%vreg113 [4304r,4320r:0)  0@4304r
%vreg116 [4312r,4320r:0)  0@4312r
%vreg117 [4272r,4312r:0)  0@4272r
%vreg120 [4240r,4256r:0)  0@4240r
%vreg122 [4224r,4256r:0)  0@4224r
%vreg123 [4208r,4224r:0)  0@4208r
%vreg125 [3760r,3776r:0)  0@3760r
%vreg128 [3824r,3840r:0)  0@3824r
%vreg129 [3808r,3840r:0)  0@3808r
%vreg131 [3872r,3888r:0)  0@3872r
%vreg134 [3936r,3952r:0)  0@3936r
%vreg135 [3920r,3952r:0)  0@3920r
%vreg139 [3984r,4032r:0)  0@3984r
%vreg143 [3392r,3408r:0)  0@3392r
%vreg144 [3376r,3392r:0)  0@3376r
%vreg147 [3344r,3360r:0)  0@3344r
%vreg148 [3328r,3344r:0)  0@3328r
%vreg152 [3296r,3312r:0)  0@3296r
%vreg153 [3280r,3296r:0)  0@3280r
%vreg154 [3264r,3312r:0)  0@3264r
%vreg159 [3232r,3248r:0)  0@3232r
%vreg161 [3216r,3232r:0)  0@3216r
%vreg162 [3200r,3216r:0)  0@3200r
%vreg167 [3204r,3232r:0)  0@3204r
%vreg168 [3168r,3204r:0)  0@3168r
%vreg170 [3208r,3248r:0)  0@3208r
%vreg171 [3176r,3208r:0)  0@3176r
%vreg173 [2256r,2272r:0)  0@2256r
%vreg174 [2328r,2336r:0)  0@2328r
%vreg176 [2320r,2336r:0)  0@2320r
%vreg178 [2368r,2384r:0)  0@2368r
%vreg179 [2440r,2448r:0)  0@2440r
%vreg181 [2432r,2448r:0)  0@2432r
%vreg184 [1744r,1760r:0)  0@1744r
%vreg185 [1816r,1824r:0)  0@1816r
%vreg187 [1808r,1824r:0)  0@1808r
%vreg189 [1856r,1872r:0)  0@1856r
%vreg190 [1928r,1936r:0)  0@1928r
%vreg192 [1920r,1936r:0)  0@1920r
%vreg195 [1280r,1296r:0)  0@1280r
%vreg196 [1352r,1360r:0)  0@1352r
%vreg198 [1344r,1360r:0)  0@1344r
%vreg200 [1392r,1408r:0)  0@1392r
%vreg201 [1464r,1472r:0)  0@1464r
%vreg203 [1456r,1472r:0)  0@1456r
%vreg206 [4656r,4672r:0)  0@4656r
%vreg207 [4464r,4480r:0)  0@4464r
%vreg209 [4480r,4544r:0)  0@4480r
RegMasks: 336r 1616r 2080r 3600r 4048r 4576r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzReadOpen: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=8, align=8, at location [SP]
  fi#3: size=4, align=4, at location [SP]
  fi#4: size=4, align=4, at location [SP]
  fi#5: size=8, align=8, at location [SP]
  fi#6: size=4, align=4, at location [SP]
  fi#7: size=8, align=8, at location [SP]
  fi#8: size=4, align=4, at location [SP]
Function Live Ins: %X0 in %vreg0, %X1 in %vreg2, %W2 in %vreg4, %W3 in %vreg6, %X4 in %vreg8, %W5 in %vreg10, %LR in %vreg19

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %X1 %W2 %W3 %X4 %W5 %LR
16B		%vreg18<def> = COPY %LR; GPR64:%vreg18
32B		%vreg11<def> = COPY %W5; GPR32:%vreg11
48B		%vreg9<def> = COPY %X4; GPR64:%vreg9
64B		%vreg7<def> = COPY %W3; GPR32:%vreg7
80B		%vreg5<def> = COPY %W2; GPR32:%vreg5
96B		%vreg3<def> = COPY %X1; GPR64:%vreg3
112B		%vreg1<def> = COPY %X0; GPR64:%vreg1
224B		%vreg15<def> = ADRP <ga:@BZ2_bzReadOpen>[TF=1]; GPR64common:%vreg15
240B		%vreg17<def> = ADDXri %vreg15, <ga:@BZ2_bzReadOpen>[TF=34], 0; GPR64sp:%vreg17 GPR64common:%vreg15
288B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
304B		%X0<def> = COPY %vreg17; GPR64sp:%vreg17
320B		%X1<def> = COPY %vreg18; GPR64:%vreg18
336B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
352B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
384B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
400B		STACKMAP 0, 0, %vreg1, 0, <fi#1>, 0, 0, <fi#7>, 0, %vreg3, 0, <fi#2>, 0, %vreg11, 0, <fi#6>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, %vreg7, 0, <fi#4>, 0, %vreg9, 0, <fi#5>, 0, %vreg5, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack8](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5] LD8[FixedStack3](align=4) GPR64:%vreg1,%vreg3,%vreg9 GPR32:%vreg11,%vreg7,%vreg5
416B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
432B		STRXui %vreg1, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg1
448B		STRXui %vreg3, <fi#2>, 0; mem:ST8[FixedStack2] GPR64:%vreg3
464B		STRWui %vreg5, <fi#3>, 0; mem:ST4[FixedStack3] GPR32:%vreg5
480B		STRWui %vreg7, <fi#4>, 0; mem:ST4[FixedStack4] GPR32:%vreg7
496B		STRXui %vreg9, <fi#5>, 0; mem:ST8[FixedStack5] GPR64:%vreg9
512B		STRWui %vreg11, <fi#6>, 0; mem:ST4[FixedStack6] GPR32:%vreg11
528B		STRXui %XZR, <fi#7>, 0; mem:ST8[FixedStack7]
544B		%vreg13<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg13
560B		CBZX %vreg13, <BB#2>; GPR64:%vreg13
	    Successors according to CFG: BB#2 BB#1

576B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
592B		%vreg21<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg21
608B		STRWui %WZR, %vreg21, 0; mem:ST4[%1] GPR64common:%vreg21
	    Successors according to CFG: BB#2

624B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#1
640B		%vreg23<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg23
656B		CBZX %vreg23, <BB#4>; GPR64:%vreg23
	    Successors according to CFG: BB#4 BB#3

672B	BB#3: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#2
688B		%vreg25<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg25
704B		STRWui %WZR, %vreg25, 1274; mem:ST4[%lastErr] GPR64common:%vreg25
	    Successors according to CFG: BB#4

720B	BB#4: derived from LLVM BB %if.end.3
	    Predecessors according to CFG: BB#2 BB#3
736B		%vreg27<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg27
752B		CBZX %vreg27, <BB#14>; GPR64:%vreg27
	    Successors according to CFG: BB#14 BB#5

768B	BB#5: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#4
784B		%vreg29<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg29
800B		CBZW %vreg29, <BB#7>; GPR32:%vreg29
	    Successors according to CFG: BB#7 BB#6

816B	BB#6: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#5
832B		%vreg31<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32common:%vreg31
848B		%WZR<def> = SUBSWri %vreg31, 1, 0, %NZCV<imp-def>; GPR32common:%vreg31
864B		Bcc 1, <BB#14>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#14 BB#7

880B	BB#7: derived from LLVM BB %lor.lhs.false.7
	    Predecessors according to CFG: BB#5 BB#6
896B		%vreg33<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg33
912B		TBNZW %vreg33, 31, <BB#14>; GPR32:%vreg33
	    Successors according to CFG: BB#14 BB#8

928B	BB#8: derived from LLVM BB %lor.lhs.false.9
	    Predecessors according to CFG: BB#7
944B		%vreg35<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32common:%vreg35
960B		%WZR<def> = SUBSWri %vreg35, 4, 0, %NZCV<imp-def>; GPR32common:%vreg35
976B		Bcc 12, <BB#14>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#14 BB#9

992B	BB#9: derived from LLVM BB %lor.lhs.false.11
	    Predecessors according to CFG: BB#8
1008B		%vreg37<def> = LDRXui <fi#5>, 0; mem:LD8[FixedStack5] GPR64:%vreg37
1024B		CBNZX %vreg37, <BB#11>; GPR64:%vreg37
	    Successors according to CFG: BB#11 BB#10

1040B	BB#10: derived from LLVM BB %land.lhs.true.13
	    Predecessors according to CFG: BB#9
1056B		%vreg39<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg39
1072B		CBNZW %vreg39, <BB#14>; GPR32:%vreg39
	    Successors according to CFG: BB#14 BB#11

1088B	BB#11: derived from LLVM BB %lor.lhs.false.15
	    Predecessors according to CFG: BB#9 BB#10
1104B		%vreg41<def> = LDRXui <fi#5>, 0; mem:LD8[FixedStack5] GPR64:%vreg41
1120B		CBZX %vreg41, <BB#19>; GPR64:%vreg41
	    Successors according to CFG: BB#19 BB#12

1136B	BB#12: derived from LLVM BB %land.lhs.true.17
	    Predecessors according to CFG: BB#11
1152B		%vreg43<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg43
1168B		TBNZW %vreg43, 31, <BB#14>; GPR32:%vreg43
	    Successors according to CFG: BB#14 BB#13

1184B	BB#13: derived from LLVM BB %lor.lhs.false.19
	    Predecessors according to CFG: BB#12
1216B		%vreg46<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg46
1224B		%vreg45<def> = MOVi32imm 5000; GPR32:%vreg45
1232B		%WZR<def> = SUBSWrr %vreg46, %vreg45, %NZCV<imp-def>; GPR32:%vreg46,%vreg45
1248B		Bcc 13, <BB#19>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#19 BB#14

1264B	BB#14: derived from LLVM BB %if.then.21
	    Predecessors according to CFG: BB#4 BB#6 BB#7 BB#8 BB#10 BB#12 BB#13
1280B		%vreg195<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg195
1296B		CBZX %vreg195, <BB#16>; GPR64:%vreg195
	    Successors according to CFG: BB#16 BB#15

1312B	BB#15: derived from LLVM BB %if.then.23
	    Predecessors according to CFG: BB#14
1344B		%vreg198<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg198
1352B		%vreg196<def> = MOVi32imm 4294967294; GPR32:%vreg196
1360B		STRWui %vreg196, %vreg198, 0; mem:ST4[%15] GPR32:%vreg196 GPR64common:%vreg198
	    Successors according to CFG: BB#16

1376B	BB#16: derived from LLVM BB %if.end.24
	    Predecessors according to CFG: BB#14 BB#15
1392B		%vreg200<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg200
1408B		CBZX %vreg200, <BB#18>; GPR64:%vreg200
	    Successors according to CFG: BB#18 BB#17

1424B	BB#17: derived from LLVM BB %if.then.26
	    Predecessors according to CFG: BB#16
1456B		%vreg203<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg203
1464B		%vreg201<def> = MOVi32imm 4294967294; GPR32:%vreg201
1472B		STRWui %vreg201, %vreg203, 1274; mem:ST4[%lastErr27] GPR32:%vreg201 GPR64common:%vreg203
	    Successors according to CFG: BB#18

1488B	BB#18: derived from LLVM BB %if.end.28
	    Predecessors according to CFG: BB#16 BB#17
1520B		STRXui %XZR, <fi#0>, 0; mem:ST8[FixedStack0]
1536B		B <BB#45>
	    Successors according to CFG: BB#45

1552B	BB#19: derived from LLVM BB %if.end.29
	    Predecessors according to CFG: BB#11 BB#13
1568B		%vreg50<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg50
1584B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1600B		%X0<def> = COPY %vreg50; GPR64:%vreg50
1616B		BL <ga:@ferror>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
1632B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1648B		%vreg49<def> = COPY %W0; GPR32:%vreg49
1664B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1680B		STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#2>, 0, 0, <fi#6>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack8](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5] LD8[FixedStack3](align=4)
1696B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1712B		CBZW %vreg49, <BB#25>; GPR32:%vreg49
	    Successors according to CFG: BB#25 BB#20

1728B	BB#20: derived from LLVM BB %if.then.30
	    Predecessors according to CFG: BB#19
1744B		%vreg184<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg184
1760B		CBZX %vreg184, <BB#22>; GPR64:%vreg184
	    Successors according to CFG: BB#22 BB#21

1776B	BB#21: derived from LLVM BB %if.then.32
	    Predecessors according to CFG: BB#20
1808B		%vreg187<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg187
1816B		%vreg185<def> = MOVi32imm 4294967290; GPR32:%vreg185
1824B		STRWui %vreg185, %vreg187, 0; mem:ST4[%20] GPR32:%vreg185 GPR64common:%vreg187
	    Successors according to CFG: BB#22

1840B	BB#22: derived from LLVM BB %if.end.33
	    Predecessors according to CFG: BB#20 BB#21
1856B		%vreg189<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg189
1872B		CBZX %vreg189, <BB#24>; GPR64:%vreg189
	    Successors according to CFG: BB#24 BB#23

1888B	BB#23: derived from LLVM BB %if.then.35
	    Predecessors according to CFG: BB#22
1920B		%vreg192<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg192
1928B		%vreg190<def> = MOVi32imm 4294967290; GPR32:%vreg190
1936B		STRWui %vreg190, %vreg192, 1274; mem:ST4[%lastErr36] GPR32:%vreg190 GPR64common:%vreg192
	    Successors according to CFG: BB#24

1952B	BB#24: derived from LLVM BB %if.end.37
	    Predecessors according to CFG: BB#22 BB#23
1984B		STRXui %XZR, <fi#0>, 0; mem:ST8[FixedStack0]
2000B		B <BB#45>
	    Successors according to CFG: BB#45

2016B	BB#25: derived from LLVM BB %if.end.38
	    Predecessors according to CFG: BB#19
2048B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2064B		%X0<def> = MOVi64imm 5104
2080B		BL <ga:@malloc>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X0<imp-def>
2096B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2112B		%vreg55<def> = COPY %X0; GPR64:%vreg55
2128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2144B		STACKMAP 2, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#2>, 0, 0, <fi#6>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack8](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5] LD8[FixedStack3](align=4)
2160B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2192B		STRXui %vreg55, <fi#7>, 0; mem:ST8[FixedStack7] GPR64:%vreg55
2208B		%vreg52<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg52
2224B		CBNZX %vreg52, <BB#31>; GPR64:%vreg52
	    Successors according to CFG: BB#31 BB#26

2240B	BB#26: derived from LLVM BB %if.then.41
	    Predecessors according to CFG: BB#25
2256B		%vreg173<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg173
2272B		CBZX %vreg173, <BB#28>; GPR64:%vreg173
	    Successors according to CFG: BB#28 BB#27

2288B	BB#27: derived from LLVM BB %if.then.43
	    Predecessors according to CFG: BB#26
2320B		%vreg176<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg176
2328B		%vreg174<def> = MOVi32imm 4294967293; GPR32:%vreg174
2336B		STRWui %vreg174, %vreg176, 0; mem:ST4[%26] GPR32:%vreg174 GPR64common:%vreg176
	    Successors according to CFG: BB#28

2352B	BB#28: derived from LLVM BB %if.end.44
	    Predecessors according to CFG: BB#26 BB#27
2368B		%vreg178<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg178
2384B		CBZX %vreg178, <BB#30>; GPR64:%vreg178
	    Successors according to CFG: BB#30 BB#29

2400B	BB#29: derived from LLVM BB %if.then.46
	    Predecessors according to CFG: BB#28
2432B		%vreg181<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg181
2440B		%vreg179<def> = MOVi32imm 4294967293; GPR32:%vreg179
2448B		STRWui %vreg179, %vreg181, 1274; mem:ST4[%lastErr47] GPR32:%vreg179 GPR64common:%vreg181
	    Successors according to CFG: BB#30

2464B	BB#30: derived from LLVM BB %if.end.48
	    Predecessors according to CFG: BB#28 BB#29
2496B		STRXui %XZR, <fi#0>, 0; mem:ST8[FixedStack0]
2512B		B <BB#45>
	    Successors according to CFG: BB#45

2528B	BB#31: derived from LLVM BB %if.end.49
	    Predecessors according to CFG: BB#25
2544B		%vreg59<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg59
2560B		CBZX %vreg59, <BB#33>; GPR64:%vreg59
	    Successors according to CFG: BB#33 BB#32

2576B	BB#32: derived from LLVM BB %if.then.51
	    Predecessors according to CFG: BB#31
2592B		%vreg61<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg61
2608B		STRWui %WZR, %vreg61, 0; mem:ST4[%30] GPR64common:%vreg61
	    Successors according to CFG: BB#33

2624B	BB#33: derived from LLVM BB %if.end.52
	    Predecessors according to CFG: BB#31 BB#32
2640B		%vreg63<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg63
2656B		CBZX %vreg63, <BB#35>; GPR64:%vreg63
	    Successors according to CFG: BB#35 BB#34

2672B	BB#34: derived from LLVM BB %if.then.54
	    Predecessors according to CFG: BB#33
2688B		%vreg65<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg65
2704B		STRWui %WZR, %vreg65, 1274; mem:ST4[%lastErr55] GPR64common:%vreg65
	    Successors according to CFG: BB#35

2720B	BB#35: derived from LLVM BB %if.end.56
	    Predecessors according to CFG: BB#33 BB#34
2752B		%vreg86<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg86
2768B		%vreg84<def> = MOVi64imm 5100; GPR64:%vreg84
2784B		%vreg85<def> = ADDXrr %vreg86, %vreg84; GPR64common:%vreg85 GPR64:%vreg86,%vreg84
2800B		STRBBui %WZR, %vreg85, 0; mem:ST1[%initialisedOk] GPR64common:%vreg85
2816B		%vreg82<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg82
2832B		%vreg81<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg81
2848B		STRXui %vreg82, %vreg81, 0; mem:ST8[%handle] GPR64:%vreg82 GPR64common:%vreg81
2864B		%vreg78<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg78
2880B		STRWui %WZR, %vreg78, 1252; mem:ST4[%bufN] GPR64common:%vreg78
2896B		%vreg76<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg76
2912B		%vreg74<def> = MOVi64imm 5012; GPR64:%vreg74
2928B		%vreg75<def> = ADDXrr %vreg76, %vreg74; GPR64common:%vreg75 GPR64:%vreg76,%vreg74
2944B		STRBBui %WZR, %vreg75, 0; mem:ST1[%writing] GPR64common:%vreg75
2960B		%vreg72<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg72
2976B		STRXui %XZR, %vreg72, 634; mem:ST8[%bzalloc] GPR64common:%vreg72
2992B		%vreg70<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg70
3008B		STRXui %XZR, %vreg70, 635; mem:ST8[%bzfree] GPR64common:%vreg70
3024B		%vreg68<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg68
3040B		STRXui %XZR, %vreg68, 636; mem:ST8[%opaque] GPR64common:%vreg68
	    Successors according to CFG: BB#36

3056B	BB#36: derived from LLVM BB %while.cond
	    Predecessors according to CFG: BB#35 BB#37
3072B		%vreg88<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32common:%vreg88
3088B		%WZR<def> = SUBSWri %vreg88, 0, 0, %NZCV<imp-def>; GPR32common:%vreg88
3104B		Bcc 13, <BB#38>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#38 BB#37

3120B	BB#37: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#36
3168B		%vreg168<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg168
3176B		%vreg171<def> = LDRXui <fi#5>, 0; mem:LD8[FixedStack5] GPR64common:%vreg171
3200B		%vreg162<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg162
3204B		%vreg167<def> = LDRSWui %vreg168, 1252; mem:LD4[%bufN60] GPR64:%vreg167 GPR64common:%vreg168
3208B		%vreg170<def> = LDRBBui %vreg171, 0; mem:LD1[%42] GPR32:%vreg170 GPR64common:%vreg171
3216B		%vreg161<def> = ADDXri %vreg162, 8, 0; GPR64common:%vreg161,%vreg162
3232B		%vreg159<def> = ADDXrr %vreg161, %vreg167; GPR64common:%vreg159,%vreg161 GPR64:%vreg167
3248B		STRBBui %vreg170, %vreg159, 0; mem:ST1[%arrayidx] GPR32:%vreg170 GPR64common:%vreg159
3264B		%vreg154<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg154
3280B		%vreg153<def> = LDRWui %vreg154, 1252; mem:LD4[%bufN61] GPR32common:%vreg153 GPR64common:%vreg154
3296B		%vreg152<def> = ADDWri %vreg153, 1, 0; GPR32common:%vreg152,%vreg153
3312B		STRWui %vreg152, %vreg154, 1252; mem:ST4[%bufN61] GPR32common:%vreg152 GPR64common:%vreg154
3328B		%vreg148<def> = LDRXui <fi#5>, 0; mem:LD8[FixedStack5] GPR64common:%vreg148
3344B		%vreg147<def> = ADDXri %vreg148, 1, 0; GPR64common:%vreg147,%vreg148
3360B		STRXui %vreg147, <fi#5>, 0; mem:ST8[FixedStack5] GPR64common:%vreg147
3376B		%vreg144<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32common:%vreg144
3392B		%vreg143<def> = SUBWri %vreg144, 1, 0; GPR32common:%vreg143,%vreg144
3408B		STRWui %vreg143, <fi#6>, 0; mem:ST4[FixedStack6] GPR32common:%vreg143
3424B		B <BB#36>
	    Successors according to CFG: BB#36

3440B	BB#38: derived from LLVM BB %while.end
	    Predecessors according to CFG: BB#36
3456B		%vreg101<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg101
3504B		%vreg97<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg97
3520B		%vreg96<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg96
3524B		%vreg99<def> = MOVi64imm 5016; GPR64:%vreg99
3528B		%vreg100<def> = ADDXrr %vreg101, %vreg99; GPR64:%vreg100,%vreg101,%vreg99
3536B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3552B		%X0<def> = COPY %vreg100; GPR64:%vreg100
3568B		%W1<def> = COPY %vreg97; GPR32:%vreg97
3584B		%W2<def> = COPY %vreg96; GPR32:%vreg96
3600B		BL <ga:@BZ2_bzDecompressInit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %W2<imp-use>, %W0<imp-def>
3616B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3632B		%vreg95<def> = COPY %W0; GPR32:%vreg95
3648B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3664B		STACKMAP 3, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack8](align=4) LD8[FixedStack0]
3680B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3696B		STRWui %vreg95, <fi#8>, 0; mem:ST4[FixedStack8] GPR32:%vreg95
3712B		%vreg90<def> = LDRWui <fi#8>, 0; mem:LD4[FixedStack8] GPR32:%vreg90
3728B		CBZW %vreg90, <BB#44>; GPR32:%vreg90
	    Successors according to CFG: BB#44 BB#39

3744B	BB#39: derived from LLVM BB %if.then.65
	    Predecessors according to CFG: BB#38
3760B		%vreg125<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg125
3776B		CBZX %vreg125, <BB#41>; GPR64:%vreg125
	    Successors according to CFG: BB#41 BB#40

3792B	BB#40: derived from LLVM BB %if.then.67
	    Predecessors according to CFG: BB#39
3808B		%vreg129<def> = LDRWui <fi#8>, 0; mem:LD4[FixedStack8] GPR32:%vreg129
3824B		%vreg128<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg128
3840B		STRWui %vreg129, %vreg128, 0; mem:ST4[%57] GPR32:%vreg129 GPR64common:%vreg128
	    Successors according to CFG: BB#41

3856B	BB#41: derived from LLVM BB %if.end.68
	    Predecessors according to CFG: BB#39 BB#40
3872B		%vreg131<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg131
3888B		CBZX %vreg131, <BB#43>; GPR64:%vreg131
	    Successors according to CFG: BB#43 BB#42

3904B	BB#42: derived from LLVM BB %if.then.70
	    Predecessors according to CFG: BB#41
3920B		%vreg135<def> = LDRWui <fi#8>, 0; mem:LD4[FixedStack8] GPR32:%vreg135
3936B		%vreg134<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg134
3952B		STRWui %vreg135, %vreg134, 1274; mem:ST4[%lastErr71] GPR32:%vreg135 GPR64common:%vreg134
	    Successors according to CFG: BB#43

3968B	BB#43: derived from LLVM BB %if.end.72
	    Predecessors according to CFG: BB#41 BB#42
3984B		%vreg139<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg139
4016B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4032B		%X0<def> = COPY %vreg139; GPR64:%vreg139
4048B		BL <ga:@free>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>
4064B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4096B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4112B		STACKMAP 4, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0]
4128B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4144B		STRXui %XZR, <fi#0>, 0; mem:ST8[FixedStack0]
4160B		B <BB#45>
	    Successors according to CFG: BB#45

4176B	BB#44: derived from LLVM BB %if.end.73
	    Predecessors according to CFG: BB#38
4208B		%vreg123<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg123
4224B		%vreg122<def> = LDRWui %vreg123, 1252; mem:LD4[%bufN74] GPR32:%vreg122 GPR64common:%vreg123
4240B		%vreg120<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg120
4256B		STRWui %vreg122, %vreg120, 1256; mem:ST4[%avail_in] GPR32:%vreg122 GPR64common:%vreg120
4272B		%vreg117<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg117
4304B		%vreg113<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg113
4312B		%vreg116<def> = ADDXri %vreg117, 8, 0; GPR64common:%vreg116,%vreg117
4320B		STRXui %vreg116, %vreg113, 627; mem:ST8[%next_in] GPR64common:%vreg116,%vreg113
4336B		%vreg110<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg110
4344B		%vreg106<def> = MOVi32imm 1; GPR32:%vreg106
4352B		%vreg108<def> = MOVi64imm 5100; GPR64:%vreg108
4368B		%vreg109<def> = ADDXrr %vreg110, %vreg108; GPR64common:%vreg109 GPR64:%vreg110,%vreg108
4384B		STRBBui %vreg106, %vreg109, 0; mem:ST1[%initialisedOk78] GPR32:%vreg106 GPR64common:%vreg109
4400B		%vreg104<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg104
4432B		STRXui %vreg104, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg104
	    Successors according to CFG: BB#45

4448B	BB#45: derived from LLVM BB %return
	    Predecessors according to CFG: BB#44 BB#43 BB#30 BB#24 BB#18
4464B		%vreg207<def> = ADRP <ga:@BZ2_bzReadOpen>[TF=1]; GPR64common:%vreg207
4480B		%vreg209<def> = ADDXri %vreg207, <ga:@BZ2_bzReadOpen>[TF=34], 0; GPR64sp:%vreg209 GPR64common:%vreg207
4528B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4544B		%X0<def> = COPY %vreg209; GPR64sp:%vreg209
4560B		%X1<def> = COPY %vreg18; GPR64:%vreg18
4576B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
4592B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4608B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4624B		STACKMAP 5, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0]
4640B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4656B		%vreg206<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg206
4672B		%X0<def> = COPY %vreg206; GPR64:%vreg206
4688B		RET_ReallyLR %X0<imp-use>

# End machine code for function BZ2_bzReadOpen.


selectOrSplit GPR64:%vreg18 [16r,4560r:0)  0@16r w=6.128641e-04
hints: %X1
missed hint %X1
assigning %vreg18 to %X19: W19 [16r,4560r:0)  0@16r

selectOrSplit GPR32:%vreg11 [32r,512r:0)  0@32r w=3.443182e-03
hints: %W5
missed hint %W5
assigning %vreg11 to %W20: W20 [32r,512r:0)  0@32r

selectOrSplit GPR64:%vreg9 [48r,496r:0)  0@48r w=3.573113e-03
hints: %X4
missed hint %X4
assigning %vreg9 to %X21: W21 [48r,496r:0)  0@48r

selectOrSplit GPR32:%vreg7 [64r,480r:0)  0@64r w=3.713235e-03
hints: %W3
missed hint %W3
assigning %vreg7 to %W22: W22 [64r,480r:0)  0@64r

selectOrSplit GPR32:%vreg5 [80r,464r:0)  0@80r w=3.864796e-03
hints: %W2
missed hint %W2
assigning %vreg5 to %W23: W23 [80r,464r:0)  0@80r

selectOrSplit GPR64:%vreg3 [96r,448r:0)  0@96r w=4.029255e-03
hints: %X1
missed hint %X1
assigning %vreg3 to %X24: W24 [96r,448r:0)  0@96r

selectOrSplit GPR64:%vreg1 [112r,432r:0)  0@112r w=4.208333e-03
hints: %X0
missed hint %X0
assigning %vreg1 to %X25: W25 [112r,432r:0)  0@112r

selectOrSplit GPR64sp:%vreg17 [240r,304r:0)  0@240r w=4.353448e-03
hints: %X0
assigning %vreg17 to %X0: W0 [240r,304r:0)  0@240r

selectOrSplit GPR64:%vreg50 [1568r,1600r:0)  0@1568r w=2.039295e-04
hints: %X0
assigning %vreg50 to %X0: W0 [1568r,1600r:0)  0@1568r

selectOrSplit GPR32:%vreg49 [1648r,1712r:0)  0@1648r w=1.898654e-04
hints: %W0
assigning %vreg49 to %W0: W0 [1648r,1712r:0)  0@1648r

selectOrSplit GPR64:%vreg55 [2112r,2192r:0)  0@2112r w=9.104567e-05
hints: %X0
assigning %vreg55 to %X0: W0 [2112r,2192r:0)  0@2112r

selectOrSplit GPR32:%vreg97 [3504r,3568r:0)  0@3504r w=4.634509e-05
hints: %W1
assigning %vreg97 to %W1: W1 [3504r,3568r:0)  0@3504r

selectOrSplit GPR32:%vreg96 [3520r,3584r:0)  0@3520r w=4.634509e-05
hints: %W2
assigning %vreg96 to %W2: W2 [3520r,3584r:0)  0@3520r

selectOrSplit GPR64:%vreg100 [3528r,3552r:0)  0@3528r w=5.071727e-05
hints: %X0
assigning %vreg100 to %X0: W0 [3528r,3552r:0)  0@3528r

selectOrSplit GPR32:%vreg95 [3632r,3696r:0)  0@3632r w=4.634509e-05
hints: %W0
assigning %vreg95 to %W0: W0 [3632r,3696r:0)  0@3632r

selectOrSplit GPR64:%vreg139 [3984r,4032r:0)  0@3984r w=2.322594e-05
hints: %X0
assigning %vreg139 to %X0: W0 [3984r,4032r:0)  0@3984r

selectOrSplit GPR64sp:%vreg209 [4480r,4544r:0)  0@4480r w=4.353448e-03
hints: %X0
assigning %vreg209 to %X0: W0 [4480r,4544r:0)  0@4480r

selectOrSplit GPR64:%vreg206 [4656r,4672r:0)  0@4656r w=inf
hints: %X0
assigning %vreg206 to %X0: W0 [4656r,4672r:0)  0@4656r

selectOrSplit GPR64common:%vreg15 [224r,240r:0)  0@224r w=inf
assigning %vreg15 to %X8: W8 [224r,240r:0)  0@224r

selectOrSplit GPR64:%vreg13 [544r,560r:0)  0@544r w=inf
assigning %vreg13 to %X8: W8 [544r,560r:0)  0@544r

selectOrSplit GPR64common:%vreg21 [592r,608r:0)  0@592r w=inf
assigning %vreg21 to %X8: W8 [592r,608r:0)  0@592r

selectOrSplit GPR64:%vreg23 [640r,656r:0)  0@640r w=inf
assigning %vreg23 to %X8: W8 [640r,656r:0)  0@640r

selectOrSplit GPR64common:%vreg25 [688r,704r:0)  0@688r w=inf
assigning %vreg25 to %X8: W8 [688r,704r:0)  0@688r

selectOrSplit GPR64:%vreg27 [736r,752r:0)  0@736r w=inf
assigning %vreg27 to %X8: W8 [736r,752r:0)  0@736r

selectOrSplit GPR32:%vreg29 [784r,800r:0)  0@784r w=inf
assigning %vreg29 to %W8: W8 [784r,800r:0)  0@784r

selectOrSplit GPR32common:%vreg31 [832r,848r:0)  0@832r w=inf
assigning %vreg31 to %W8: W8 [832r,848r:0)  0@832r

selectOrSplit GPR32:%vreg33 [896r,912r:0)  0@896r w=inf
assigning %vreg33 to %W8: W8 [896r,912r:0)  0@896r

selectOrSplit GPR32common:%vreg35 [944r,960r:0)  0@944r w=inf
assigning %vreg35 to %W8: W8 [944r,960r:0)  0@944r

selectOrSplit GPR64:%vreg37 [1008r,1024r:0)  0@1008r w=inf
assigning %vreg37 to %X8: W8 [1008r,1024r:0)  0@1008r

selectOrSplit GPR32:%vreg39 [1056r,1072r:0)  0@1056r w=inf
assigning %vreg39 to %W8: W8 [1056r,1072r:0)  0@1056r

selectOrSplit GPR64:%vreg41 [1104r,1120r:0)  0@1104r w=inf
assigning %vreg41 to %X8: W8 [1104r,1120r:0)  0@1104r

selectOrSplit GPR32:%vreg43 [1152r,1168r:0)  0@1152r w=inf
assigning %vreg43 to %W8: W8 [1152r,1168r:0)  0@1152r

selectOrSplit GPR32:%vreg46 [1216r,1232r:0)  0@1216r w=8.420066e-05
assigning %vreg46 to %W8: W8 [1216r,1232r:0)  0@1216r

selectOrSplit GPR32:%vreg45 [1224r,1232r:0)  0@1224r w=inf
assigning %vreg45 to %W9: W9 [1224r,1232r:0)  0@1224r

selectOrSplit GPR64:%vreg195 [1280r,1296r:0)  0@1280r w=inf
assigning %vreg195 to %X8: W8 [1280r,1296r:0)  0@1280r

selectOrSplit GPR64common:%vreg198 [1344r,1360r:0)  0@1344r w=2.298183e-03
assigning %vreg198 to %X8: W8 [1344r,1360r:0)  0@1344r

selectOrSplit GPR32:%vreg196 [1352r,1360r:0)  0@1352r w=inf
assigning %vreg196 to %W9: W9 [1352r,1360r:0)  0@1352r

selectOrSplit GPR64:%vreg200 [1392r,1408r:0)  0@1392r w=inf
assigning %vreg200 to %X8: W8 [1392r,1408r:0)  0@1392r

selectOrSplit GPR64common:%vreg203 [1456r,1472r:0)  0@1456r w=2.298183e-03
assigning %vreg203 to %X8: W8 [1456r,1472r:0)  0@1456r

selectOrSplit GPR32:%vreg201 [1464r,1472r:0)  0@1464r w=inf
assigning %vreg201 to %W9: W9 [1464r,1472r:0)  0@1464r

selectOrSplit GPR64:%vreg184 [1744r,1760r:0)  0@1744r w=inf
assigning %vreg184 to %X8: W8 [1744r,1760r:0)  0@1744r

selectOrSplit GPR64common:%vreg187 [1808r,1824r:0)  0@1808r w=5.118079e-05
assigning %vreg187 to %X8: W8 [1808r,1824r:0)  0@1808r

selectOrSplit GPR32:%vreg185 [1816r,1824r:0)  0@1816r w=inf
assigning %vreg185 to %W9: W9 [1816r,1824r:0)  0@1816r

selectOrSplit GPR64:%vreg189 [1856r,1872r:0)  0@1856r w=inf
assigning %vreg189 to %X8: W8 [1856r,1872r:0)  0@1856r

selectOrSplit GPR64common:%vreg192 [1920r,1936r:0)  0@1920r w=5.118079e-05
assigning %vreg192 to %X8: W8 [1920r,1936r:0)  0@1920r

selectOrSplit GPR32:%vreg190 [1928r,1936r:0)  0@1928r w=inf
assigning %vreg190 to %W9: W9 [1928r,1936r:0)  0@1928r

selectOrSplit GPR64:%vreg52 [2208r,2224r:0)  0@2208r w=inf
assigning %vreg52 to %X8: W8 [2208r,2224r:0)  0@2208r

selectOrSplit GPR64:%vreg173 [2256r,2272r:0)  0@2256r w=inf
assigning %vreg173 to %X8: W8 [2256r,2272r:0)  0@2256r

selectOrSplit GPR64common:%vreg176 [2320r,2336r:0)  0@2320r w=2.476490e-05
assigning %vreg176 to %X8: W8 [2320r,2336r:0)  0@2320r

selectOrSplit GPR32:%vreg174 [2328r,2336r:0)  0@2328r w=inf
assigning %vreg174 to %W9: W9 [2328r,2336r:0)  0@2328r

selectOrSplit GPR64:%vreg178 [2368r,2384r:0)  0@2368r w=inf
assigning %vreg178 to %X8: W8 [2368r,2384r:0)  0@2368r

selectOrSplit GPR64common:%vreg181 [2432r,2448r:0)  0@2432r w=2.476490e-05
assigning %vreg181 to %X8: W8 [2432r,2448r:0)  0@2432r

selectOrSplit GPR32:%vreg179 [2440r,2448r:0)  0@2440r w=inf
assigning %vreg179 to %W9: W9 [2440r,2448r:0)  0@2440r

selectOrSplit GPR64:%vreg59 [2544r,2560r:0)  0@2544r w=inf
assigning %vreg59 to %X8: W8 [2544r,2560r:0)  0@2544r

selectOrSplit GPR64common:%vreg61 [2592r,2608r:0)  0@2592r w=inf
assigning %vreg61 to %X8: W8 [2592r,2608r:0)  0@2592r

selectOrSplit GPR64:%vreg63 [2640r,2656r:0)  0@2640r w=inf
assigning %vreg63 to %X8: W8 [2640r,2656r:0)  0@2640r

selectOrSplit GPR64common:%vreg65 [2688r,2704r:0)  0@2688r w=inf
assigning %vreg65 to %X8: W8 [2688r,2704r:0)  0@2688r

selectOrSplit GPR64:%vreg86 [2752r,2784r:0)  0@2752r w=4.928521e-05
assigning %vreg86 to %X8: W8 [2752r,2784r:0)  0@2752r

selectOrSplit GPR64:%vreg84 [2768r,2784r:0)  0@2768r w=inf
assigning %vreg84 to %X9: W9 [2768r,2784r:0)  0@2768r

selectOrSplit GPR64common:%vreg85 [2784r,2800r:0)  0@2784r w=inf
assigning %vreg85 to %X8: W8 [2784r,2800r:0)  0@2784r

selectOrSplit GPR64:%vreg82 [2816r,2848r:0)  0@2816r w=4.928521e-05
assigning %vreg82 to %X8: W8 [2816r,2848r:0)  0@2816r

selectOrSplit GPR64common:%vreg81 [2832r,2848r:0)  0@2832r w=inf
assigning %vreg81 to %X9: W9 [2832r,2848r:0)  0@2832r

selectOrSplit GPR64common:%vreg78 [2864r,2880r:0)  0@2864r w=inf
assigning %vreg78 to %X8: W8 [2864r,2880r:0)  0@2864r

selectOrSplit GPR64:%vreg76 [2896r,2928r:0)  0@2896r w=4.928521e-05
assigning %vreg76 to %X8: W8 [2896r,2928r:0)  0@2896r

selectOrSplit GPR64:%vreg74 [2912r,2928r:0)  0@2912r w=inf
assigning %vreg74 to %X9: W9 [2912r,2928r:0)  0@2912r

selectOrSplit GPR64common:%vreg75 [2928r,2944r:0)  0@2928r w=inf
assigning %vreg75 to %X8: W8 [2928r,2944r:0)  0@2928r

selectOrSplit GPR64common:%vreg72 [2960r,2976r:0)  0@2960r w=inf
assigning %vreg72 to %X8: W8 [2960r,2976r:0)  0@2960r

selectOrSplit GPR64common:%vreg70 [2992r,3008r:0)  0@2992r w=inf
assigning %vreg70 to %X8: W8 [2992r,3008r:0)  0@2992r

selectOrSplit GPR64common:%vreg68 [3024r,3040r:0)  0@3024r w=inf
assigning %vreg68 to %X8: W8 [3024r,3040r:0)  0@3024r

selectOrSplit GPR32common:%vreg88 [3072r,3088r:0)  0@3072r w=inf
assigning %vreg88 to %W8: W8 [3072r,3088r:0)  0@3072r

selectOrSplit GPR64common:%vreg168 [3168r,3204r:0)  0@3168r w=4.883305e-05
assigning %vreg168 to %X8: W8 [3168r,3204r:0)  0@3168r

selectOrSplit GPR64common:%vreg171 [3176r,3208r:0)  0@3176r w=4.928521e-05
assigning %vreg171 to %X9: W9 [3176r,3208r:0)  0@3176r

selectOrSplit GPR64common:%vreg162 [3200r,3216r:0)  0@3200r w=5.118079e-05
assigning %vreg162 to %X10: W10 [3200r,3216r:0)  0@3200r

selectOrSplit GPR64:%vreg167 [3204r,3232r:0)  0@3204r w=4.974582e-05
assigning %vreg167 to %X8: W8 [3204r,3232r:0)  0@3204r

selectOrSplit GPR32:%vreg170 [3208r,3248r:0)  0@3208r w=4.838911e-05
assigning %vreg170 to %W9: W9 [3208r,3248r:0)  0@3208r

selectOrSplit GPR64common:%vreg161 [3216r,3232r:0)  0@3216r w=inf
assigning %vreg161 to %X10: W10 [3216r,3232r:0)  0@3216r

selectOrSplit GPR64common:%vreg159 [3232r,3248r:0)  0@3232r w=inf
assigning %vreg159 to %X8: W8 [3232r,3248r:0)  0@3232r

selectOrSplit GPR64common:%vreg154 [3264r,3312r:0)  0@3264r w=7.128753e-05
assigning %vreg154 to %X8: W8 [3264r,3312r:0)  0@3264r

selectOrSplit GPR32common:%vreg153 [3280r,3296r:0)  0@3280r w=inf
assigning %vreg153 to %W9: W9 [3280r,3296r:0)  0@3280r

selectOrSplit GPR32common:%vreg152 [3296r,3312r:0)  0@3296r w=inf
assigning %vreg152 to %W9: W9 [3296r,3312r:0)  0@3296r

selectOrSplit GPR64common:%vreg148 [3328r,3344r:0)  0@3328r w=inf
assigning %vreg148 to %X8: W8 [3328r,3344r:0)  0@3328r

selectOrSplit GPR64common:%vreg147 [3344r,3360r:0)  0@3344r w=inf
assigning %vreg147 to %X8: W8 [3344r,3360r:0)  0@3344r

selectOrSplit GPR32common:%vreg144 [3376r,3392r:0)  0@3376r w=inf
assigning %vreg144 to %W8: W8 [3376r,3392r:0)  0@3376r

selectOrSplit GPR32common:%vreg143 [3392r,3408r:0)  0@3392r w=inf
assigning %vreg143 to %W8: W8 [3392r,3408r:0)  0@3392r

selectOrSplit GPR64:%vreg101 [3456r,3528r:0)  0@3456r w=4.510850e-05
assigning %vreg101 to %X8: W8 [3456r,3528r:0)  0@3456r

selectOrSplit GPR64:%vreg99 [3524r,3528r:0)  0@3524r w=inf
assigning %vreg99 to %X9: W9 [3524r,3528r:0)  0@3524r

selectOrSplit GPR32:%vreg90 [3712r,3728r:0)  0@3712r w=inf
assigning %vreg90 to %W8: W8 [3712r,3728r:0)  0@3712r

selectOrSplit GPR64:%vreg125 [3760r,3776r:0)  0@3760r w=inf
assigning %vreg125 to %X8: W8 [3760r,3776r:0)  0@3760r

selectOrSplit GPR32:%vreg129 [3808r,3840r:0)  0@3808r w=1.112892e-05
assigning %vreg129 to %W8: W8 [3808r,3840r:0)  0@3808r

selectOrSplit GPR64common:%vreg128 [3824r,3840r:0)  0@3824r w=inf
assigning %vreg128 to %X9: W9 [3824r,3840r:0)  0@3824r

selectOrSplit GPR64:%vreg131 [3872r,3888r:0)  0@3872r w=inf
assigning %vreg131 to %X8: W8 [3872r,3888r:0)  0@3872r

selectOrSplit GPR32:%vreg135 [3920r,3952r:0)  0@3920r w=1.112892e-05
assigning %vreg135 to %W8: W8 [3920r,3952r:0)  0@3920r

selectOrSplit GPR64common:%vreg134 [3936r,3952r:0)  0@3936r w=inf
assigning %vreg134 to %X9: W9 [3936r,3952r:0)  0@3936r

selectOrSplit GPR64common:%vreg123 [4208r,4224r:0)  0@4208r w=inf
assigning %vreg123 to %X8: W8 [4208r,4224r:0)  0@4208r

selectOrSplit GPR32:%vreg122 [4224r,4256r:0)  0@4224r w=2.384768e-05
assigning %vreg122 to %W8: W8 [4224r,4256r:0)  0@4224r

selectOrSplit GPR64common:%vreg120 [4240r,4256r:0)  0@4240r w=inf
assigning %vreg120 to %X9: W9 [4240r,4256r:0)  0@4240r

selectOrSplit GPR64common:%vreg117 [4272r,4312r:0)  0@4272r w=2.341409e-05
assigning %vreg117 to %X8: W8 [4272r,4312r:0)  0@4272r

selectOrSplit GPR64common:%vreg113 [4304r,4320r:0)  0@4304r w=2.476490e-05
assigning %vreg113 to %X9: W9 [4304r,4320r:0)  0@4304r

selectOrSplit GPR64common:%vreg116 [4312r,4320r:0)  0@4312r w=inf
assigning %vreg116 to %X8: W8 [4312r,4320r:0)  0@4312r

selectOrSplit GPR64:%vreg110 [4336r,4368r:0)  0@4336r w=2.384768e-05
assigning %vreg110 to %X8: W8 [4336r,4368r:0)  0@4336r

selectOrSplit GPR32:%vreg106 [4344r,4384r:0)  0@4344r w=1.170704e-05
assigning %vreg106 to %W9: W9 [4344r,4384r:0)  0@4344r

selectOrSplit GPR64:%vreg108 [4352r,4368r:0)  0@4352r w=inf
assigning %vreg108 to %X10: W10 [4352r,4368r:0)  0@4352r

selectOrSplit GPR64common:%vreg109 [4368r,4384r:0)  0@4368r w=inf
assigning %vreg109 to %X8: W8 [4368r,4384r:0)  0@4368r

selectOrSplit GPR64:%vreg104 [4400r,4432r:0)  0@4400r w=inf
assigning %vreg104 to %X8: W8 [4400r,4432r:0)  0@4400r

selectOrSplit GPR64common:%vreg207 [4464r,4480r:0)  0@4464r w=inf
assigning %vreg207 to %X8: W8 [4464r,4480r:0)  0@4464r

********** STACK TRANSFORMATION METADATA **********
********** Function: BZ2_bzReadOpen
********** REGISTER MAP **********
[%vreg1 -> %X25] GPR64
[%vreg3 -> %X24] GPR64
[%vreg5 -> %W23] GPR32
[%vreg7 -> %W22] GPR32
[%vreg9 -> %X21] GPR64
[%vreg11 -> %W20] GPR32
[%vreg13 -> %X8] GPR64
[%vreg15 -> %X8] GPR64common
[%vreg17 -> %X0] GPR64sp
[%vreg18 -> %X19] GPR64
[%vreg21 -> %X8] GPR64common
[%vreg23 -> %X8] GPR64
[%vreg25 -> %X8] GPR64common
[%vreg27 -> %X8] GPR64
[%vreg29 -> %W8] GPR32
[%vreg31 -> %W8] GPR32common
[%vreg33 -> %W8] GPR32
[%vreg35 -> %W8] GPR32common
[%vreg37 -> %X8] GPR64
[%vreg39 -> %W8] GPR32
[%vreg41 -> %X8] GPR64
[%vreg43 -> %W8] GPR32
[%vreg45 -> %W9] GPR32
[%vreg46 -> %W8] GPR32
[%vreg49 -> %W0] GPR32
[%vreg50 -> %X0] GPR64
[%vreg52 -> %X8] GPR64
[%vreg55 -> %X0] GPR64
[%vreg59 -> %X8] GPR64
[%vreg61 -> %X8] GPR64common
[%vreg63 -> %X8] GPR64
[%vreg65 -> %X8] GPR64common
[%vreg68 -> %X8] GPR64common
[%vreg70 -> %X8] GPR64common
[%vreg72 -> %X8] GPR64common
[%vreg74 -> %X9] GPR64
[%vreg75 -> %X8] GPR64common
[%vreg76 -> %X8] GPR64
[%vreg78 -> %X8] GPR64common
[%vreg81 -> %X9] GPR64common
[%vreg82 -> %X8] GPR64
[%vreg84 -> %X9] GPR64
[%vreg85 -> %X8] GPR64common
[%vreg86 -> %X8] GPR64
[%vreg88 -> %W8] GPR32common
[%vreg90 -> %W8] GPR32
[%vreg95 -> %W0] GPR32
[%vreg96 -> %W2] GPR32
[%vreg97 -> %W1] GPR32
[%vreg99 -> %X9] GPR64
[%vreg100 -> %X0] GPR64
[%vreg101 -> %X8] GPR64
[%vreg104 -> %X8] GPR64
[%vreg106 -> %W9] GPR32
[%vreg108 -> %X10] GPR64
[%vreg109 -> %X8] GPR64common
[%vreg110 -> %X8] GPR64
[%vreg113 -> %X9] GPR64common
[%vreg116 -> %X8] GPR64common
[%vreg117 -> %X8] GPR64common
[%vreg120 -> %X9] GPR64common
[%vreg122 -> %W8] GPR32
[%vreg123 -> %X8] GPR64common
[%vreg125 -> %X8] GPR64
[%vreg128 -> %X9] GPR64common
[%vreg129 -> %W8] GPR32
[%vreg131 -> %X8] GPR64
[%vreg134 -> %X9] GPR64common
[%vreg135 -> %W8] GPR32
[%vreg139 -> %X0] GPR64
[%vreg143 -> %W8] GPR32common
[%vreg144 -> %W8] GPR32common
[%vreg147 -> %X8] GPR64common
[%vreg148 -> %X8] GPR64common
[%vreg152 -> %W9] GPR32common
[%vreg153 -> %W9] GPR32common
[%vreg154 -> %X8] GPR64common
[%vreg159 -> %X8] GPR64common
[%vreg161 -> %X10] GPR64common
[%vreg162 -> %X10] GPR64common
[%vreg167 -> %X8] GPR64
[%vreg168 -> %X8] GPR64common
[%vreg170 -> %W9] GPR32
[%vreg171 -> %X9] GPR64common
[%vreg173 -> %X8] GPR64
[%vreg174 -> %W9] GPR32
[%vreg176 -> %X8] GPR64common
[%vreg178 -> %X8] GPR64
[%vreg179 -> %W9] GPR32
[%vreg181 -> %X8] GPR64common
[%vreg184 -> %X8] GPR64
[%vreg185 -> %W9] GPR32
[%vreg187 -> %X8] GPR64common
[%vreg189 -> %X8] GPR64
[%vreg190 -> %W9] GPR32
[%vreg192 -> %X8] GPR64common
[%vreg195 -> %X8] GPR64
[%vreg196 -> %W9] GPR32
[%vreg198 -> %X8] GPR64common
[%vreg200 -> %X8] GPR64
[%vreg201 -> %W9] GPR32
[%vreg203 -> %X8] GPR64common
[%vreg206 -> %X0] GPR64
[%vreg207 -> %X8] GPR64common
[%vreg209 -> %X0] GPR64sp


Stackmap 0:
  STACKMAP 0, 0, %vreg1, 0, <fi#1>, 0, 0, <fi#7>, 0, %vreg3, 0, <fi#2>, 0, %vreg11, 0, <fi#6>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, %vreg7, 0, <fi#4>, 0, %vreg9, 0, <fi#5>, 0, %vreg5, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack8](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5] LD8[FixedStack3](align=4) GPR64:%vreg1,%vreg3,%vreg9 GPR32:%vreg11,%vreg7,%vreg5

i32* %bzerror: in register %X25 (vreg 1)
i32** %bzerror.addr: in stack slot 1 (size: 8)
%struct.bzFile** %bzf: in stack slot 7 (size: 8)
%struct._IO_FILE* %f: in register %X24 (vreg 3)
%struct._IO_FILE** %f.addr: in stack slot 2 (size: 8)
i32 %nUnused: in register %W20 (vreg 11)
i32* %nUnused.addr: in stack slot 6 (size: 4)
i32* %ret: in stack slot 8 (size: 4)
i8** %retval: in stack slot 0 (size: 8)
i32 %small: in register %W22 (vreg 7)
i32* %small.addr: in stack slot 4 (size: 4)
i8* %unused: in register %X21 (vreg 9)
i8** %unused.addr: in stack slot 5 (size: 8)
i32 %verbosity: in register %W23 (vreg 5)
i32* %verbosity.addr: in stack slot 3 (size: 4)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#2>, 0, 0, <fi#6>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack8](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5] LD8[FixedStack3](align=4)

i32** %bzerror.addr: in stack slot 1 (size: 8)
%struct.bzFile** %bzf: in stack slot 7 (size: 8)
%struct._IO_FILE** %f.addr: in stack slot 2 (size: 8)
i32* %nUnused.addr: in stack slot 6 (size: 4)
i32* %ret: in stack slot 8 (size: 4)
i8** %retval: in stack slot 0 (size: 8)
i32* %small.addr: in stack slot 4 (size: 4)
i8** %unused.addr: in stack slot 5 (size: 8)
i32* %verbosity.addr: in stack slot 3 (size: 4)

Duplicate operand locations:


Stackmap 2:
  STACKMAP 2, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#2>, 0, 0, <fi#6>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack8](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5] LD8[FixedStack3](align=4)

i32** %bzerror.addr: in stack slot 1 (size: 8)
%struct.bzFile** %bzf: in stack slot 7 (size: 8)
%struct._IO_FILE** %f.addr: in stack slot 2 (size: 8)
i32* %nUnused.addr: in stack slot 6 (size: 4)
i32* %ret: in stack slot 8 (size: 4)
i8** %retval: in stack slot 0 (size: 8)
i32* %small.addr: in stack slot 4 (size: 4)
i8** %unused.addr: in stack slot 5 (size: 8)
i32* %verbosity.addr: in stack slot 3 (size: 4)

Duplicate operand locations:


Stackmap 3:
  STACKMAP 3, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack8](align=4) LD8[FixedStack0]

i32** %bzerror.addr: in stack slot 1 (size: 8)
%struct.bzFile** %bzf: in stack slot 7 (size: 8)
i32* %ret: in stack slot 8 (size: 4)
i8** %retval: in stack slot 0 (size: 8)

Duplicate operand locations:


Stackmap 4:
  STACKMAP 4, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0]

i8** %retval: in stack slot 0 (size: 8)

Duplicate operand locations:


Stackmap 5:
  STACKMAP 5, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0]

i8** %retval: in stack slot 0 (size: 8)

Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, %vreg1, 0, <fi#1>, 0, 0, <fi#7>, 0, %vreg3, 0, <fi#2>, 0, %vreg11, 0, <fi#6>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, %vreg7, 0, <fi#4>, 0, %vreg9, 0, <fi#5>, 0, %vreg5, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack8](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5] LD8[FixedStack3](align=4) GPR64:%vreg1,%vreg3,%vreg9 GPR32:%vreg11,%vreg7,%vreg5
  -> Call instruction SlotIndex 336B, searching vregs 0 -> 211 and stack slots 0 -> 9
    + vreg18 is live in register but not in stackmap
      Defining instruction: %vreg18<def> = COPY %LR; GPR64:%vreg18
      Value: generated value, 1 instruction(s)

  STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#2>, 0, 0, <fi#6>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack8](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5] LD8[FixedStack3](align=4)
  -> Call instruction SlotIndex 1616B, searching vregs 0 -> 211 and stack slots 0 -> 9
    + vreg18 is live in register but not in stackmap
      Defining instruction: %vreg18<def> = COPY %LR; GPR64:%vreg18
      Value: generated value, 1 instruction(s)

  STACKMAP 2, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#2>, 0, 0, <fi#6>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack8](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5] LD8[FixedStack3](align=4)
  -> Call instruction SlotIndex 2080B, searching vregs 0 -> 211 and stack slots 0 -> 9
    + vreg18 is live in register but not in stackmap
      Defining instruction: %vreg18<def> = COPY %LR; GPR64:%vreg18
      Value: generated value, 1 instruction(s)

  STACKMAP 3, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack8](align=4) LD8[FixedStack0]
  -> Call instruction SlotIndex 3600B, searching vregs 0 -> 211 and stack slots 0 -> 9
    + vreg18 is live in register but not in stackmap
      Defining instruction: %vreg18<def> = COPY %LR; GPR64:%vreg18
      Value: generated value, 1 instruction(s)

  STACKMAP 4, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0]
  -> Call instruction SlotIndex 4048B, searching vregs 0 -> 211 and stack slots 0 -> 9
    + vreg18 is live in register but not in stackmap
      Defining instruction: %vreg18<def> = COPY %LR; GPR64:%vreg18
      Value: generated value, 1 instruction(s)

  STACKMAP 5, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0]
  -> Call instruction SlotIndex 4576B, searching vregs 0 -> 211 and stack slots 0 -> 9

********** REWRITE VIRTUAL REGISTERS **********
********** Function: BZ2_bzReadOpen
********** REGISTER MAP **********
[%vreg1 -> %X25] GPR64
[%vreg3 -> %X24] GPR64
[%vreg5 -> %W23] GPR32
[%vreg7 -> %W22] GPR32
[%vreg9 -> %X21] GPR64
[%vreg11 -> %W20] GPR32
[%vreg13 -> %X8] GPR64
[%vreg15 -> %X8] GPR64common
[%vreg17 -> %X0] GPR64sp
[%vreg18 -> %X19] GPR64
[%vreg21 -> %X8] GPR64common
[%vreg23 -> %X8] GPR64
[%vreg25 -> %X8] GPR64common
[%vreg27 -> %X8] GPR64
[%vreg29 -> %W8] GPR32
[%vreg31 -> %W8] GPR32common
[%vreg33 -> %W8] GPR32
[%vreg35 -> %W8] GPR32common
[%vreg37 -> %X8] GPR64
[%vreg39 -> %W8] GPR32
[%vreg41 -> %X8] GPR64
[%vreg43 -> %W8] GPR32
[%vreg45 -> %W9] GPR32
[%vreg46 -> %W8] GPR32
[%vreg49 -> %W0] GPR32
[%vreg50 -> %X0] GPR64
[%vreg52 -> %X8] GPR64
[%vreg55 -> %X0] GPR64
[%vreg59 -> %X8] GPR64
[%vreg61 -> %X8] GPR64common
[%vreg63 -> %X8] GPR64
[%vreg65 -> %X8] GPR64common
[%vreg68 -> %X8] GPR64common
[%vreg70 -> %X8] GPR64common
[%vreg72 -> %X8] GPR64common
[%vreg74 -> %X9] GPR64
[%vreg75 -> %X8] GPR64common
[%vreg76 -> %X8] GPR64
[%vreg78 -> %X8] GPR64common
[%vreg81 -> %X9] GPR64common
[%vreg82 -> %X8] GPR64
[%vreg84 -> %X9] GPR64
[%vreg85 -> %X8] GPR64common
[%vreg86 -> %X8] GPR64
[%vreg88 -> %W8] GPR32common
[%vreg90 -> %W8] GPR32
[%vreg95 -> %W0] GPR32
[%vreg96 -> %W2] GPR32
[%vreg97 -> %W1] GPR32
[%vreg99 -> %X9] GPR64
[%vreg100 -> %X0] GPR64
[%vreg101 -> %X8] GPR64
[%vreg104 -> %X8] GPR64
[%vreg106 -> %W9] GPR32
[%vreg108 -> %X10] GPR64
[%vreg109 -> %X8] GPR64common
[%vreg110 -> %X8] GPR64
[%vreg113 -> %X9] GPR64common
[%vreg116 -> %X8] GPR64common
[%vreg117 -> %X8] GPR64common
[%vreg120 -> %X9] GPR64common
[%vreg122 -> %W8] GPR32
[%vreg123 -> %X8] GPR64common
[%vreg125 -> %X8] GPR64
[%vreg128 -> %X9] GPR64common
[%vreg129 -> %W8] GPR32
[%vreg131 -> %X8] GPR64
[%vreg134 -> %X9] GPR64common
[%vreg135 -> %W8] GPR32
[%vreg139 -> %X0] GPR64
[%vreg143 -> %W8] GPR32common
[%vreg144 -> %W8] GPR32common
[%vreg147 -> %X8] GPR64common
[%vreg148 -> %X8] GPR64common
[%vreg152 -> %W9] GPR32common
[%vreg153 -> %W9] GPR32common
[%vreg154 -> %X8] GPR64common
[%vreg159 -> %X8] GPR64common
[%vreg161 -> %X10] GPR64common
[%vreg162 -> %X10] GPR64common
[%vreg167 -> %X8] GPR64
[%vreg168 -> %X8] GPR64common
[%vreg170 -> %W9] GPR32
[%vreg171 -> %X9] GPR64common
[%vreg173 -> %X8] GPR64
[%vreg174 -> %W9] GPR32
[%vreg176 -> %X8] GPR64common
[%vreg178 -> %X8] GPR64
[%vreg179 -> %W9] GPR32
[%vreg181 -> %X8] GPR64common
[%vreg184 -> %X8] GPR64
[%vreg185 -> %W9] GPR32
[%vreg187 -> %X8] GPR64common
[%vreg189 -> %X8] GPR64
[%vreg190 -> %W9] GPR32
[%vreg192 -> %X8] GPR64common
[%vreg195 -> %X8] GPR64
[%vreg196 -> %W9] GPR32
[%vreg198 -> %X8] GPR64common
[%vreg200 -> %X8] GPR64
[%vreg201 -> %W9] GPR32
[%vreg203 -> %X8] GPR64common
[%vreg206 -> %X0] GPR64
[%vreg207 -> %X8] GPR64common
[%vreg209 -> %X0] GPR64sp

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %LR %W2 %W3 %W5 %X0 %X1 %X4
16B		%vreg18<def> = COPY %LR; GPR64:%vreg18
32B		%vreg11<def> = COPY %W5; GPR32:%vreg11
48B		%vreg9<def> = COPY %X4; GPR64:%vreg9
64B		%vreg7<def> = COPY %W3; GPR32:%vreg7
80B		%vreg5<def> = COPY %W2; GPR32:%vreg5
96B		%vreg3<def> = COPY %X1; GPR64:%vreg3
112B		%vreg1<def> = COPY %X0; GPR64:%vreg1
224B		%vreg15<def> = ADRP <ga:@BZ2_bzReadOpen>[TF=1]; GPR64common:%vreg15
240B		%vreg17<def> = ADDXri %vreg15<kill>, <ga:@BZ2_bzReadOpen>[TF=34], 0; GPR64sp:%vreg17 GPR64common:%vreg15
288B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
304B		%X0<def> = COPY %vreg17<kill>; GPR64sp:%vreg17
320B		%X1<def> = COPY %vreg18; GPR64:%vreg18
336B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
352B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
384B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
400B		STACKMAP 0, 0, %vreg1, 0, <fi#1>, 0, 0, <fi#7>, 0, %vreg3, 0, <fi#2>, 0, %vreg11, 0, <fi#6>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, %vreg7, 0, <fi#4>, 0, %vreg9, 0, <fi#5>, 0, %vreg5, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack8](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5] LD8[FixedStack3](align=4) GPR64:%vreg1,%vreg3,%vreg9 GPR32:%vreg11,%vreg7,%vreg5
416B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
432B		STRXui %vreg1<kill>, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg1
448B		STRXui %vreg3<kill>, <fi#2>, 0; mem:ST8[FixedStack2] GPR64:%vreg3
464B		STRWui %vreg5<kill>, <fi#3>, 0; mem:ST4[FixedStack3] GPR32:%vreg5
480B		STRWui %vreg7<kill>, <fi#4>, 0; mem:ST4[FixedStack4] GPR32:%vreg7
496B		STRXui %vreg9<kill>, <fi#5>, 0; mem:ST8[FixedStack5] GPR64:%vreg9
512B		STRWui %vreg11<kill>, <fi#6>, 0; mem:ST4[FixedStack6] GPR32:%vreg11
528B		STRXui %XZR, <fi#7>, 0; mem:ST8[FixedStack7]
544B		%vreg13<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg13
560B		CBZX %vreg13<kill>, <BB#2>; GPR64:%vreg13
	    Successors according to CFG: BB#2 BB#1
> %X19<def> = COPY %LR
> %W20<def> = COPY %W5
> %X21<def> = COPY %X4
> %W22<def> = COPY %W3
> %W23<def> = COPY %W2
> %X24<def> = COPY %X1
> %X25<def> = COPY %X0
> %X8<def> = ADRP <ga:@BZ2_bzReadOpen>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@BZ2_bzReadOpen>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19
> BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 0, 0, %X25, 0, <fi#1>, 0, 0, <fi#7>, 0, %X24, 0, <fi#2>, 0, %W20, 0, <fi#6>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, %W22, 0, <fi#4>, 0, %X21, 0, <fi#5>, 0, %W23, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack8](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5] LD8[FixedStack3](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRXui %X25<kill>, <fi#1>, 0; mem:ST8[FixedStack1]
> STRXui %X24<kill>, <fi#2>, 0; mem:ST8[FixedStack2]
> STRWui %W23<kill>, <fi#3>, 0; mem:ST4[FixedStack3]
> STRWui %W22<kill>, <fi#4>, 0; mem:ST4[FixedStack4]
> STRXui %X21<kill>, <fi#5>, 0; mem:ST8[FixedStack5]
> STRWui %W20<kill>, <fi#6>, 0; mem:ST4[FixedStack6]
> STRXui %XZR, <fi#7>, 0; mem:ST8[FixedStack7]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> CBZX %X8<kill>, <BB#2>
576B	BB#1: derived from LLVM BB %if.then
	    Live Ins: %X19
	    Predecessors according to CFG: BB#0
592B		%vreg21<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg21
608B		STRWui %WZR, %vreg21<kill>, 0; mem:ST4[%1] GPR64common:%vreg21
	    Successors according to CFG: BB#2
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRWui %WZR, %X8<kill>, 0; mem:ST4[%1]
624B	BB#2: derived from LLVM BB %if.end
	    Live Ins: %X19
	    Predecessors according to CFG: BB#0 BB#1
640B		%vreg23<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg23
656B		CBZX %vreg23<kill>, <BB#4>; GPR64:%vreg23
	    Successors according to CFG: BB#4 BB#3
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> CBZX %X8<kill>, <BB#4>
672B	BB#3: derived from LLVM BB %if.then.2
	    Live Ins: %X19
	    Predecessors according to CFG: BB#2
688B		%vreg25<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg25
704B		STRWui %WZR, %vreg25<kill>, 1274; mem:ST4[%lastErr] GPR64common:%vreg25
	    Successors according to CFG: BB#4
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> STRWui %WZR, %X8<kill>, 1274; mem:ST4[%lastErr]
720B	BB#4: derived from LLVM BB %if.end.3
	    Live Ins: %X19
	    Predecessors according to CFG: BB#2 BB#3
736B		%vreg27<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg27
752B		CBZX %vreg27<kill>, <BB#14>; GPR64:%vreg27
	    Successors according to CFG: BB#14 BB#5
> %X8<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2]
> CBZX %X8<kill>, <BB#14>
768B	BB#5: derived from LLVM BB %lor.lhs.false
	    Live Ins: %X19
	    Predecessors according to CFG: BB#4
784B		%vreg29<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg29
800B		CBZW %vreg29<kill>, <BB#7>; GPR32:%vreg29
	    Successors according to CFG: BB#7 BB#6
> %W8<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4]
> CBZW %W8<kill>, <BB#7>
816B	BB#6: derived from LLVM BB %land.lhs.true
	    Live Ins: %X19
	    Predecessors according to CFG: BB#5
832B		%vreg31<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32common:%vreg31
848B		%WZR<def> = SUBSWri %vreg31<kill>, 1, 0, %NZCV<imp-def>; GPR32common:%vreg31
864B		Bcc 1, <BB#14>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#14 BB#7
> %W8<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4]
> %WZR<def> = SUBSWri %W8<kill>, 1, 0, %NZCV<imp-def>
> Bcc 1, <BB#14>, %NZCV<imp-use,kill>
880B	BB#7: derived from LLVM BB %lor.lhs.false.7
	    Live Ins: %X19
	    Predecessors according to CFG: BB#5 BB#6
896B		%vreg33<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg33
912B		TBNZW %vreg33<kill>, 31, <BB#14>; GPR32:%vreg33
	    Successors according to CFG: BB#14 BB#8
> %W8<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3]
> TBNZW %W8<kill>, 31, <BB#14>
928B	BB#8: derived from LLVM BB %lor.lhs.false.9
	    Live Ins: %X19
	    Predecessors according to CFG: BB#7
944B		%vreg35<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32common:%vreg35
960B		%WZR<def> = SUBSWri %vreg35<kill>, 4, 0, %NZCV<imp-def>; GPR32common:%vreg35
976B		Bcc 12, <BB#14>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#14 BB#9
> %W8<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3]
> %WZR<def> = SUBSWri %W8<kill>, 4, 0, %NZCV<imp-def>
> Bcc 12, <BB#14>, %NZCV<imp-use,kill>
992B	BB#9: derived from LLVM BB %lor.lhs.false.11
	    Live Ins: %X19
	    Predecessors according to CFG: BB#8
1008B		%vreg37<def> = LDRXui <fi#5>, 0; mem:LD8[FixedStack5] GPR64:%vreg37
1024B		CBNZX %vreg37<kill>, <BB#11>; GPR64:%vreg37
	    Successors according to CFG: BB#11 BB#10
> %X8<def> = LDRXui <fi#5>, 0; mem:LD8[FixedStack5]
> CBNZX %X8<kill>, <BB#11>
1040B	BB#10: derived from LLVM BB %land.lhs.true.13
	    Live Ins: %X19
	    Predecessors according to CFG: BB#9
1056B		%vreg39<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg39
1072B		CBNZW %vreg39<kill>, <BB#14>; GPR32:%vreg39
	    Successors according to CFG: BB#14 BB#11
> %W8<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6]
> CBNZW %W8<kill>, <BB#14>
1088B	BB#11: derived from LLVM BB %lor.lhs.false.15
	    Live Ins: %X19
	    Predecessors according to CFG: BB#9 BB#10
1104B		%vreg41<def> = LDRXui <fi#5>, 0; mem:LD8[FixedStack5] GPR64:%vreg41
1120B		CBZX %vreg41<kill>, <BB#19>; GPR64:%vreg41
	    Successors according to CFG: BB#19 BB#12
> %X8<def> = LDRXui <fi#5>, 0; mem:LD8[FixedStack5]
> CBZX %X8<kill>, <BB#19>
1136B	BB#12: derived from LLVM BB %land.lhs.true.17
	    Live Ins: %X19
	    Predecessors according to CFG: BB#11
1152B		%vreg43<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg43
1168B		TBNZW %vreg43<kill>, 31, <BB#14>; GPR32:%vreg43
	    Successors according to CFG: BB#14 BB#13
> %W8<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6]
> TBNZW %W8<kill>, 31, <BB#14>
1184B	BB#13: derived from LLVM BB %lor.lhs.false.19
	    Live Ins: %X19
	    Predecessors according to CFG: BB#12
1216B		%vreg46<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg46
1224B		%vreg45<def> = MOVi32imm 5000; GPR32:%vreg45
1232B		%WZR<def> = SUBSWrr %vreg46<kill>, %vreg45<kill>, %NZCV<imp-def>; GPR32:%vreg46,%vreg45
1248B		Bcc 13, <BB#19>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#19 BB#14
> %W8<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6]
> %W9<def> = MOVi32imm 5000
> %WZR<def> = SUBSWrr %W8<kill>, %W9<kill>, %NZCV<imp-def>
> Bcc 13, <BB#19>, %NZCV<imp-use,kill>
1264B	BB#14: derived from LLVM BB %if.then.21
	    Live Ins: %X19
	    Predecessors according to CFG: BB#4 BB#6 BB#7 BB#8 BB#10 BB#12 BB#13
1280B		%vreg195<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg195
1296B		CBZX %vreg195<kill>, <BB#16>; GPR64:%vreg195
	    Successors according to CFG: BB#16 BB#15
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> CBZX %X8<kill>, <BB#16>
1312B	BB#15: derived from LLVM BB %if.then.23
	    Live Ins: %X19
	    Predecessors according to CFG: BB#14
1344B		%vreg198<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg198
1352B		%vreg196<def> = MOVi32imm 4294967294; GPR32:%vreg196
1360B		STRWui %vreg196<kill>, %vreg198<kill>, 0; mem:ST4[%15] GPR32:%vreg196 GPR64common:%vreg198
	    Successors according to CFG: BB#16
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = MOVi32imm 4294967294
> STRWui %W9<kill>, %X8<kill>, 0; mem:ST4[%15]
1376B	BB#16: derived from LLVM BB %if.end.24
	    Live Ins: %X19
	    Predecessors according to CFG: BB#14 BB#15
1392B		%vreg200<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg200
1408B		CBZX %vreg200<kill>, <BB#18>; GPR64:%vreg200
	    Successors according to CFG: BB#18 BB#17
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> CBZX %X8<kill>, <BB#18>
1424B	BB#17: derived from LLVM BB %if.then.26
	    Live Ins: %X19
	    Predecessors according to CFG: BB#16
1456B		%vreg203<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg203
1464B		%vreg201<def> = MOVi32imm 4294967294; GPR32:%vreg201
1472B		STRWui %vreg201<kill>, %vreg203<kill>, 1274; mem:ST4[%lastErr27] GPR32:%vreg201 GPR64common:%vreg203
	    Successors according to CFG: BB#18
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> %W9<def> = MOVi32imm 4294967294
> STRWui %W9<kill>, %X8<kill>, 1274; mem:ST4[%lastErr27]
1488B	BB#18: derived from LLVM BB %if.end.28
	    Live Ins: %X19
	    Predecessors according to CFG: BB#16 BB#17
1520B		STRXui %XZR, <fi#0>, 0; mem:ST8[FixedStack0]
1536B		B <BB#45>
	    Successors according to CFG: BB#45
> STRXui %XZR, <fi#0>, 0; mem:ST8[FixedStack0]
> B <BB#45>
1552B	BB#19: derived from LLVM BB %if.end.29
	    Live Ins: %X19
	    Predecessors according to CFG: BB#11 BB#13
1568B		%vreg50<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg50
1584B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1600B		%X0<def> = COPY %vreg50<kill>; GPR64:%vreg50
1616B		BL <ga:@ferror>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
1632B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1648B		%vreg49<def> = COPY %W0; GPR32:%vreg49
1664B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1680B		STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#2>, 0, 0, <fi#6>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack8](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5] LD8[FixedStack3](align=4)
1696B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1712B		CBZW %vreg49<kill>, <BB#25>; GPR32:%vreg49
	    Successors according to CFG: BB#25 BB#20
> %X0<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BL <ga:@ferror>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = COPY %W0
Deleting identity copy.
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#2>, 0, 0, <fi#6>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack8](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5] LD8[FixedStack3](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> CBZW %W0<kill>, <BB#25>
1728B	BB#20: derived from LLVM BB %if.then.30
	    Live Ins: %X19
	    Predecessors according to CFG: BB#19
1744B		%vreg184<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg184
1760B		CBZX %vreg184<kill>, <BB#22>; GPR64:%vreg184
	    Successors according to CFG: BB#22 BB#21
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> CBZX %X8<kill>, <BB#22>
1776B	BB#21: derived from LLVM BB %if.then.32
	    Live Ins: %X19
	    Predecessors according to CFG: BB#20
1808B		%vreg187<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg187
1816B		%vreg185<def> = MOVi32imm 4294967290; GPR32:%vreg185
1824B		STRWui %vreg185<kill>, %vreg187<kill>, 0; mem:ST4[%20] GPR32:%vreg185 GPR64common:%vreg187
	    Successors according to CFG: BB#22
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = MOVi32imm 4294967290
> STRWui %W9<kill>, %X8<kill>, 0; mem:ST4[%20]
1840B	BB#22: derived from LLVM BB %if.end.33
	    Live Ins: %X19
	    Predecessors according to CFG: BB#20 BB#21
1856B		%vreg189<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg189
1872B		CBZX %vreg189<kill>, <BB#24>; GPR64:%vreg189
	    Successors according to CFG: BB#24 BB#23
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> CBZX %X8<kill>, <BB#24>
1888B	BB#23: derived from LLVM BB %if.then.35
	    Live Ins: %X19
	    Predecessors according to CFG: BB#22
1920B		%vreg192<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg192
1928B		%vreg190<def> = MOVi32imm 4294967290; GPR32:%vreg190
1936B		STRWui %vreg190<kill>, %vreg192<kill>, 1274; mem:ST4[%lastErr36] GPR32:%vreg190 GPR64common:%vreg192
	    Successors according to CFG: BB#24
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> %W9<def> = MOVi32imm 4294967290
> STRWui %W9<kill>, %X8<kill>, 1274; mem:ST4[%lastErr36]
1952B	BB#24: derived from LLVM BB %if.end.37
	    Live Ins: %X19
	    Predecessors according to CFG: BB#22 BB#23
1984B		STRXui %XZR, <fi#0>, 0; mem:ST8[FixedStack0]
2000B		B <BB#45>
	    Successors according to CFG: BB#45
> STRXui %XZR, <fi#0>, 0; mem:ST8[FixedStack0]
> B <BB#45>
2016B	BB#25: derived from LLVM BB %if.end.38
	    Live Ins: %X19
	    Predecessors according to CFG: BB#19
2048B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2064B		%X0<def> = MOVi64imm 5104
2080B		BL <ga:@malloc>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X0<imp-def>
2096B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2112B		%vreg55<def> = COPY %X0; GPR64:%vreg55
2128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2144B		STACKMAP 2, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#2>, 0, 0, <fi#6>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack8](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5] LD8[FixedStack3](align=4)
2160B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2192B		STRXui %vreg55<kill>, <fi#7>, 0; mem:ST8[FixedStack7] GPR64:%vreg55
2208B		%vreg52<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg52
2224B		CBNZX %vreg52<kill>, <BB#31>; GPR64:%vreg52
	    Successors according to CFG: BB#31 BB#26
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = MOVi64imm 5104
> BL <ga:@malloc>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0
Deleting identity copy.
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 2, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#2>, 0, 0, <fi#6>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#3>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack8](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5] LD8[FixedStack3](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRXui %X0<kill>, <fi#7>, 0; mem:ST8[FixedStack7]
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> CBNZX %X8<kill>, <BB#31>
2240B	BB#26: derived from LLVM BB %if.then.41
	    Live Ins: %X19
	    Predecessors according to CFG: BB#25
2256B		%vreg173<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg173
2272B		CBZX %vreg173<kill>, <BB#28>; GPR64:%vreg173
	    Successors according to CFG: BB#28 BB#27
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> CBZX %X8<kill>, <BB#28>
2288B	BB#27: derived from LLVM BB %if.then.43
	    Live Ins: %X19
	    Predecessors according to CFG: BB#26
2320B		%vreg176<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg176
2328B		%vreg174<def> = MOVi32imm 4294967293; GPR32:%vreg174
2336B		STRWui %vreg174<kill>, %vreg176<kill>, 0; mem:ST4[%26] GPR32:%vreg174 GPR64common:%vreg176
	    Successors according to CFG: BB#28
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = MOVi32imm 4294967293
> STRWui %W9<kill>, %X8<kill>, 0; mem:ST4[%26]
2352B	BB#28: derived from LLVM BB %if.end.44
	    Live Ins: %X19
	    Predecessors according to CFG: BB#26 BB#27
2368B		%vreg178<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg178
2384B		CBZX %vreg178<kill>, <BB#30>; GPR64:%vreg178
	    Successors according to CFG: BB#30 BB#29
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> CBZX %X8<kill>, <BB#30>
2400B	BB#29: derived from LLVM BB %if.then.46
	    Live Ins: %X19
	    Predecessors according to CFG: BB#28
2432B		%vreg181<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg181
2440B		%vreg179<def> = MOVi32imm 4294967293; GPR32:%vreg179
2448B		STRWui %vreg179<kill>, %vreg181<kill>, 1274; mem:ST4[%lastErr47] GPR32:%vreg179 GPR64common:%vreg181
	    Successors according to CFG: BB#30
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> %W9<def> = MOVi32imm 4294967293
> STRWui %W9<kill>, %X8<kill>, 1274; mem:ST4[%lastErr47]
2464B	BB#30: derived from LLVM BB %if.end.48
	    Live Ins: %X19
	    Predecessors according to CFG: BB#28 BB#29
2496B		STRXui %XZR, <fi#0>, 0; mem:ST8[FixedStack0]
2512B		B <BB#45>
	    Successors according to CFG: BB#45
> STRXui %XZR, <fi#0>, 0; mem:ST8[FixedStack0]
> B <BB#45>
2528B	BB#31: derived from LLVM BB %if.end.49
	    Live Ins: %X19
	    Predecessors according to CFG: BB#25
2544B		%vreg59<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg59
2560B		CBZX %vreg59<kill>, <BB#33>; GPR64:%vreg59
	    Successors according to CFG: BB#33 BB#32
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> CBZX %X8<kill>, <BB#33>
2576B	BB#32: derived from LLVM BB %if.then.51
	    Live Ins: %X19
	    Predecessors according to CFG: BB#31
2592B		%vreg61<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg61
2608B		STRWui %WZR, %vreg61<kill>, 0; mem:ST4[%30] GPR64common:%vreg61
	    Successors according to CFG: BB#33
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRWui %WZR, %X8<kill>, 0; mem:ST4[%30]
2624B	BB#33: derived from LLVM BB %if.end.52
	    Live Ins: %X19
	    Predecessors according to CFG: BB#31 BB#32
2640B		%vreg63<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg63
2656B		CBZX %vreg63<kill>, <BB#35>; GPR64:%vreg63
	    Successors according to CFG: BB#35 BB#34
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> CBZX %X8<kill>, <BB#35>
2672B	BB#34: derived from LLVM BB %if.then.54
	    Live Ins: %X19
	    Predecessors according to CFG: BB#33
2688B		%vreg65<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg65
2704B		STRWui %WZR, %vreg65<kill>, 1274; mem:ST4[%lastErr55] GPR64common:%vreg65
	    Successors according to CFG: BB#35
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> STRWui %WZR, %X8<kill>, 1274; mem:ST4[%lastErr55]
2720B	BB#35: derived from LLVM BB %if.end.56
	    Live Ins: %X19
	    Predecessors according to CFG: BB#33 BB#34
2752B		%vreg86<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg86
2768B		%vreg84<def> = MOVi64imm 5100; GPR64:%vreg84
2784B		%vreg85<def> = ADDXrr %vreg86<kill>, %vreg84<kill>; GPR64common:%vreg85 GPR64:%vreg86,%vreg84
2800B		STRBBui %WZR, %vreg85<kill>, 0; mem:ST1[%initialisedOk] GPR64common:%vreg85
2816B		%vreg82<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg82
2832B		%vreg81<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg81
2848B		STRXui %vreg82<kill>, %vreg81<kill>, 0; mem:ST8[%handle] GPR64:%vreg82 GPR64common:%vreg81
2864B		%vreg78<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg78
2880B		STRWui %WZR, %vreg78<kill>, 1252; mem:ST4[%bufN] GPR64common:%vreg78
2896B		%vreg76<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg76
2912B		%vreg74<def> = MOVi64imm 5012; GPR64:%vreg74
2928B		%vreg75<def> = ADDXrr %vreg76<kill>, %vreg74<kill>; GPR64common:%vreg75 GPR64:%vreg76,%vreg74
2944B		STRBBui %WZR, %vreg75<kill>, 0; mem:ST1[%writing] GPR64common:%vreg75
2960B		%vreg72<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg72
2976B		STRXui %XZR, %vreg72<kill>, 634; mem:ST8[%bzalloc] GPR64common:%vreg72
2992B		%vreg70<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg70
3008B		STRXui %XZR, %vreg70<kill>, 635; mem:ST8[%bzfree] GPR64common:%vreg70
3024B		%vreg68<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg68
3040B		STRXui %XZR, %vreg68<kill>, 636; mem:ST8[%opaque] GPR64common:%vreg68
	    Successors according to CFG: BB#36
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> %X9<def> = MOVi64imm 5100
> %X8<def> = ADDXrr %X8<kill>, %X9<kill>
> STRBBui %WZR, %X8<kill>, 0; mem:ST1[%initialisedOk]
> %X8<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2]
> %X9<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> STRXui %X8<kill>, %X9<kill>, 0; mem:ST8[%handle]
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> STRWui %WZR, %X8<kill>, 1252; mem:ST4[%bufN]
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> %X9<def> = MOVi64imm 5012
> %X8<def> = ADDXrr %X8<kill>, %X9<kill>
> STRBBui %WZR, %X8<kill>, 0; mem:ST1[%writing]
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> STRXui %XZR, %X8<kill>, 634; mem:ST8[%bzalloc]
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> STRXui %XZR, %X8<kill>, 635; mem:ST8[%bzfree]
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> STRXui %XZR, %X8<kill>, 636; mem:ST8[%opaque]
3056B	BB#36: derived from LLVM BB %while.cond
	    Live Ins: %X19
	    Predecessors according to CFG: BB#35 BB#37
3072B		%vreg88<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32common:%vreg88
3088B		%WZR<def> = SUBSWri %vreg88<kill>, 0, 0, %NZCV<imp-def>; GPR32common:%vreg88
3104B		Bcc 13, <BB#38>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#38 BB#37
> %W8<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6]
> %WZR<def> = SUBSWri %W8<kill>, 0, 0, %NZCV<imp-def>
> Bcc 13, <BB#38>, %NZCV<imp-use,kill>
3120B	BB#37: derived from LLVM BB %while.body
	    Live Ins: %X19
	    Predecessors according to CFG: BB#36
3168B		%vreg168<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg168
3176B		%vreg171<def> = LDRXui <fi#5>, 0; mem:LD8[FixedStack5] GPR64common:%vreg171
3200B		%vreg162<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg162
3204B		%vreg167<def> = LDRSWui %vreg168<kill>, 1252; mem:LD4[%bufN60] GPR64:%vreg167 GPR64common:%vreg168
3208B		%vreg170<def> = LDRBBui %vreg171<kill>, 0; mem:LD1[%42] GPR32:%vreg170 GPR64common:%vreg171
3216B		%vreg161<def> = ADDXri %vreg162<kill>, 8, 0; GPR64common:%vreg161,%vreg162
3232B		%vreg159<def> = ADDXrr %vreg161<kill>, %vreg167<kill>; GPR64common:%vreg159,%vreg161 GPR64:%vreg167
3248B		STRBBui %vreg170<kill>, %vreg159<kill>, 0; mem:ST1[%arrayidx] GPR32:%vreg170 GPR64common:%vreg159
3264B		%vreg154<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg154
3280B		%vreg153<def> = LDRWui %vreg154, 1252; mem:LD4[%bufN61] GPR32common:%vreg153 GPR64common:%vreg154
3296B		%vreg152<def> = ADDWri %vreg153<kill>, 1, 0; GPR32common:%vreg152,%vreg153
3312B		STRWui %vreg152<kill>, %vreg154<kill>, 1252; mem:ST4[%bufN61] GPR32common:%vreg152 GPR64common:%vreg154
3328B		%vreg148<def> = LDRXui <fi#5>, 0; mem:LD8[FixedStack5] GPR64common:%vreg148
3344B		%vreg147<def> = ADDXri %vreg148<kill>, 1, 0; GPR64common:%vreg147,%vreg148
3360B		STRXui %vreg147<kill>, <fi#5>, 0; mem:ST8[FixedStack5] GPR64common:%vreg147
3376B		%vreg144<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32common:%vreg144
3392B		%vreg143<def> = SUBWri %vreg144<kill>, 1, 0; GPR32common:%vreg143,%vreg144
3408B		STRWui %vreg143<kill>, <fi#6>, 0; mem:ST4[FixedStack6] GPR32common:%vreg143
3424B		B <BB#36>
	    Successors according to CFG: BB#36
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> %X9<def> = LDRXui <fi#5>, 0; mem:LD8[FixedStack5]
> %X10<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> %X8<def> = LDRSWui %X8<kill>, 1252; mem:LD4[%bufN60]
> %W9<def> = LDRBBui %X9<kill>, 0; mem:LD1[%42]
> %X10<def> = ADDXri %X10<kill>, 8, 0
> %X8<def> = ADDXrr %X10<kill>, %X8<kill>
> STRBBui %W9<kill>, %X8<kill>, 0; mem:ST1[%arrayidx]
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> %W9<def> = LDRWui %X8, 1252; mem:LD4[%bufN61]
> %W9<def> = ADDWri %W9<kill>, 1, 0
> STRWui %W9<kill>, %X8<kill>, 1252; mem:ST4[%bufN61]
> %X8<def> = LDRXui <fi#5>, 0; mem:LD8[FixedStack5]
> %X8<def> = ADDXri %X8<kill>, 1, 0
> STRXui %X8<kill>, <fi#5>, 0; mem:ST8[FixedStack5]
> %W8<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6]
> %W8<def> = SUBWri %W8<kill>, 1, 0
> STRWui %W8<kill>, <fi#6>, 0; mem:ST4[FixedStack6]
> B <BB#36>
3440B	BB#38: derived from LLVM BB %while.end
	    Live Ins: %X19
	    Predecessors according to CFG: BB#36
3456B		%vreg101<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg101
3504B		%vreg97<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg97
3520B		%vreg96<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg96
3524B		%vreg99<def> = MOVi64imm 5016; GPR64:%vreg99
3528B		%vreg100<def> = ADDXrr %vreg101<kill>, %vreg99<kill>; GPR64:%vreg100,%vreg101,%vreg99
3536B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3552B		%X0<def> = COPY %vreg100<kill>; GPR64:%vreg100
3568B		%W1<def> = COPY %vreg97<kill>; GPR32:%vreg97
3584B		%W2<def> = COPY %vreg96<kill>; GPR32:%vreg96
3600B		BL <ga:@BZ2_bzDecompressInit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %W2<imp-use>, %W0<imp-def>
3616B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3632B		%vreg95<def> = COPY %W0; GPR32:%vreg95
3648B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3664B		STACKMAP 3, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack8](align=4) LD8[FixedStack0]
3680B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3696B		STRWui %vreg95<kill>, <fi#8>, 0; mem:ST4[FixedStack8] GPR32:%vreg95
3712B		%vreg90<def> = LDRWui <fi#8>, 0; mem:LD4[FixedStack8] GPR32:%vreg90
3728B		CBZW %vreg90<kill>, <BB#44>; GPR32:%vreg90
	    Successors according to CFG: BB#44 BB#39
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> %W1<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3]
> %W2<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4]
> %X9<def> = MOVi64imm 5016
> %X0<def> = ADDXrr %X8<kill>, %X9<kill>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %W1<def> = COPY %W1<kill>
Deleting identity copy.
> %W2<def> = COPY %W2<kill>
Deleting identity copy.
> BL <ga:@BZ2_bzDecompressInit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %W2<imp-use>, %W0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = COPY %W0
Deleting identity copy.
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 3, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack8](align=4) LD8[FixedStack0]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRWui %W0<kill>, <fi#8>, 0; mem:ST4[FixedStack8]
> %W8<def> = LDRWui <fi#8>, 0; mem:LD4[FixedStack8]
> CBZW %W8<kill>, <BB#44>
3744B	BB#39: derived from LLVM BB %if.then.65
	    Live Ins: %X19
	    Predecessors according to CFG: BB#38
3760B		%vreg125<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg125
3776B		CBZX %vreg125<kill>, <BB#41>; GPR64:%vreg125
	    Successors according to CFG: BB#41 BB#40
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> CBZX %X8<kill>, <BB#41>
3792B	BB#40: derived from LLVM BB %if.then.67
	    Live Ins: %X19
	    Predecessors according to CFG: BB#39
3808B		%vreg129<def> = LDRWui <fi#8>, 0; mem:LD4[FixedStack8] GPR32:%vreg129
3824B		%vreg128<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg128
3840B		STRWui %vreg129<kill>, %vreg128<kill>, 0; mem:ST4[%57] GPR32:%vreg129 GPR64common:%vreg128
	    Successors according to CFG: BB#41
> %W8<def> = LDRWui <fi#8>, 0; mem:LD4[FixedStack8]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRWui %W8<kill>, %X9<kill>, 0; mem:ST4[%57]
3856B	BB#41: derived from LLVM BB %if.end.68
	    Live Ins: %X19
	    Predecessors according to CFG: BB#39 BB#40
3872B		%vreg131<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg131
3888B		CBZX %vreg131<kill>, <BB#43>; GPR64:%vreg131
	    Successors according to CFG: BB#43 BB#42
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> CBZX %X8<kill>, <BB#43>
3904B	BB#42: derived from LLVM BB %if.then.70
	    Live Ins: %X19
	    Predecessors according to CFG: BB#41
3920B		%vreg135<def> = LDRWui <fi#8>, 0; mem:LD4[FixedStack8] GPR32:%vreg135
3936B		%vreg134<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg134
3952B		STRWui %vreg135<kill>, %vreg134<kill>, 1274; mem:ST4[%lastErr71] GPR32:%vreg135 GPR64common:%vreg134
	    Successors according to CFG: BB#43
> %W8<def> = LDRWui <fi#8>, 0; mem:LD4[FixedStack8]
> %X9<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> STRWui %W8<kill>, %X9<kill>, 1274; mem:ST4[%lastErr71]
3968B	BB#43: derived from LLVM BB %if.end.72
	    Live Ins: %X19
	    Predecessors according to CFG: BB#41 BB#42
3984B		%vreg139<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg139
4016B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4032B		%X0<def> = COPY %vreg139<kill>; GPR64:%vreg139
4048B		BL <ga:@free>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>
4064B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4096B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4112B		STACKMAP 4, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0]
4128B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4144B		STRXui %XZR, <fi#0>, 0; mem:ST8[FixedStack0]
4160B		B <BB#45>
	    Successors according to CFG: BB#45
> %X0<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BL <ga:@free>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 4, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRXui %XZR, <fi#0>, 0; mem:ST8[FixedStack0]
> B <BB#45>
4176B	BB#44: derived from LLVM BB %if.end.73
	    Live Ins: %X19
	    Predecessors according to CFG: BB#38
4208B		%vreg123<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg123
4224B		%vreg122<def> = LDRWui %vreg123<kill>, 1252; mem:LD4[%bufN74] GPR32:%vreg122 GPR64common:%vreg123
4240B		%vreg120<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg120
4256B		STRWui %vreg122<kill>, %vreg120<kill>, 1256; mem:ST4[%avail_in] GPR32:%vreg122 GPR64common:%vreg120
4272B		%vreg117<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg117
4304B		%vreg113<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg113
4312B		%vreg116<def> = ADDXri %vreg117<kill>, 8, 0; GPR64common:%vreg116,%vreg117
4320B		STRXui %vreg116<kill>, %vreg113<kill>, 627; mem:ST8[%next_in] GPR64common:%vreg116,%vreg113
4336B		%vreg110<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg110
4344B		%vreg106<def> = MOVi32imm 1; GPR32:%vreg106
4352B		%vreg108<def> = MOVi64imm 5100; GPR64:%vreg108
4368B		%vreg109<def> = ADDXrr %vreg110<kill>, %vreg108<kill>; GPR64common:%vreg109 GPR64:%vreg110,%vreg108
4384B		STRBBui %vreg106<kill>, %vreg109<kill>, 0; mem:ST1[%initialisedOk78] GPR32:%vreg106 GPR64common:%vreg109
4400B		%vreg104<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg104
4432B		STRXui %vreg104<kill>, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg104
	    Successors according to CFG: BB#45
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> %W8<def> = LDRWui %X8<kill>, 1252; mem:LD4[%bufN74]
> %X9<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> STRWui %W8<kill>, %X9<kill>, 1256; mem:ST4[%avail_in]
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> %X9<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> %X8<def> = ADDXri %X8<kill>, 8, 0
> STRXui %X8<kill>, %X9<kill>, 627; mem:ST8[%next_in]
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> %W9<def> = MOVi32imm 1
> %X10<def> = MOVi64imm 5100
> %X8<def> = ADDXrr %X8<kill>, %X10<kill>
> STRBBui %W9<kill>, %X8<kill>, 0; mem:ST1[%initialisedOk78]
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> STRXui %X8<kill>, <fi#0>, 0; mem:ST8[FixedStack0]
4448B	BB#45: derived from LLVM BB %return
	    Live Ins: %X19
	    Predecessors according to CFG: BB#44 BB#43 BB#30 BB#24 BB#18
4464B		%vreg207<def> = ADRP <ga:@BZ2_bzReadOpen>[TF=1]; GPR64common:%vreg207
4480B		%vreg209<def> = ADDXri %vreg207<kill>, <ga:@BZ2_bzReadOpen>[TF=34], 0; GPR64sp:%vreg209 GPR64common:%vreg207
4528B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4544B		%X0<def> = COPY %vreg209<kill>; GPR64sp:%vreg209
4560B		%X1<def> = COPY %vreg18<kill>; GPR64:%vreg18
4576B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
4592B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4608B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4624B		STACKMAP 5, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0]
4640B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4656B		%vreg206<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg206
4672B		%X0<def> = COPY %vreg206<kill>; GPR64:%vreg206
4688B		RET_ReallyLR %X0<imp-use>
> %X8<def> = ADRP <ga:@BZ2_bzReadOpen>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@BZ2_bzReadOpen>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19<kill>
> BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 5, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> RET_ReallyLR %X0<imp-use>
Computing live-in reg-units in ABI blocks.
0B	BB#0 W0#0 W1#0 W30#0
Created 3 new intervals.
********** INTERVALS **********
W30 [0B,16r:0)[208r,208d:8)[256e,256d:2)[1392r,1392d:7)[1456e,1456d:1)[1568r,1568d:5)[1616e,1616d:6)[1776r,1776d:3)[1824e,1824d:4)  0@0B-phi 1@1456e 2@256e 3@1776r 4@1824e 5@1568r 6@1616e 7@1392r 8@208r
W0 [0B,48r:0)[176r,208r:5)[1376r,1392r:4)[1392r,1424r:1)[1552r,1568r:3)[1744r,1776r:2)  0@0B-phi 1@1392r 2@1744r 3@1552r 4@1376r 5@176r
W1 [0B,32r:0)[192r,208r:2)[1760r,1776r:1)  0@0B-phi 1@1760r 2@192r
%vreg0 [48r,64r:0)  0@48r
%vreg1 [64r,288r:0)  0@64r
%vreg2 [32r,80r:0)  0@32r
%vreg3 [80r,304r:0)  0@80r
%vreg5 [368r,384r:0)  0@368r
%vreg8 [336r,352r:0)  0@336r
%vreg9 [320r,336r:0)  0@320r
%vreg10 [96r,112r:0)  0@96r
%vreg11 [112r,128r:0)  0@112r
%vreg12 [128r,176r:0)  0@128r
%vreg13 [144r,192r:0)  0@144r
%vreg14 [16r,1712r:0)  0@16r
%vreg16 [416r,432r:0)  0@416r
%vreg18 [464r,480r:0)  0@464r
%vreg20 [512r,528r:0)  0@512r
%vreg22 [560r,576r:0)  0@560r
%vreg24 [896r,912r:0)  0@896r
%vreg26 [848r,864r:0)  0@848r
%vreg27 [864r,880r:0)  0@864r
%vreg28 [880r,896r:0)  0@880r
%vreg29 [832r,864r:0)  0@832r
%vreg31 [1264r,1280r:0)  0@1264r
%vreg33 [1216r,1232r:0)  0@1216r
%vreg34 [1232r,1248r:0)  0@1232r
%vreg35 [1248r,1264r:0)  0@1248r
%vreg36 [1200r,1232r:0)  0@1200r
%vreg38 [1424r,1424d:0)  0@1424r
%vreg40 [1328r,1344r:0)  0@1328r
%vreg41 [1344r,1376r:0)  0@1344r
%vreg42 [1312r,1344r:0)  0@1312r
%vreg45 [1520r,1552r:0)  0@1520r
%vreg46 [1504r,1520r:0)  0@1504r
%vreg48 [944r,960r:0)  0@944r
%vreg49 [992r,1024r:0)  0@992r
%vreg51 [1008r,1024r:0)  0@1008r
%vreg53 [1056r,1072r:0)  0@1056r
%vreg54 [1104r,1136r:0)  0@1104r
%vreg56 [1120r,1136r:0)  0@1120r
%vreg58 [608r,624r:0)  0@608r
%vreg60 [656r,672r:0)  0@656r
%vreg62 [704r,720r:0)  0@704r
%vreg64 [752r,768r:0)  0@752r
%vreg65 [1664r,1680r:0)  0@1664r
%vreg66 [1680r,1696r:0)  0@1680r
%vreg67 [1696r,1744r:0)  0@1696r
%vreg68 [1712r,1760r:0)  0@1712r
RegMasks: 208r 1392r 1568r 1776r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzReadClose: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=8, align=8, at location [SP]
Function Live Ins: %X0 in %vreg0, %X1 in %vreg2, %LR in %vreg14

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %X1 %LR
16B		%vreg14<def> = COPY %LR; GPR64:%vreg14
32B		%vreg2<def> = COPY %X1; GPR64:%vreg2
48B		%vreg0<def> = COPY %X0; GPR64:%vreg0
64B		%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
80B		%vreg3<def> = COPY %vreg2; GPR64:%vreg3,%vreg2
96B		%vreg10<def> = ADRP <ga:@BZ2_bzReadClose>[TF=1]; GPR64common:%vreg10
112B		%vreg11<def> = ADDXri %vreg10, <ga:@BZ2_bzReadClose>[TF=34], 0; GPR64sp:%vreg11 GPR64common:%vreg10
128B		%vreg12<def> = COPY %vreg11; GPR64all:%vreg12 GPR64sp:%vreg11
144B		%vreg13<def> = COPY %vreg14; GPR64all:%vreg13 GPR64:%vreg14
160B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
176B		%X0<def> = COPY %vreg12; GPR64all:%vreg12
192B		%X1<def> = COPY %vreg13; GPR64all:%vreg13
208B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
224B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
240B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
256B		STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack2] GPR64:%vreg3,%vreg1
272B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
288B		STRXui %vreg1, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg1
304B		STRXui %vreg3, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg3
320B		%vreg9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg9
336B		%vreg8<def> = COPY %vreg9; GPR64:%vreg8,%vreg9
352B		STRXui %vreg8, <fi#2>, 0; mem:ST8[FixedStack2] GPR64:%vreg8
368B		%vreg5<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg5
384B		CBZX %vreg5, <BB#2>; GPR64:%vreg5
	    Successors according to CFG: BB#2 BB#1

400B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
416B		%vreg16<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg16
432B		STRWui %WZR, %vreg16, 0; mem:ST4[%3] GPR64common:%vreg16
	    Successors according to CFG: BB#2

448B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#1
464B		%vreg18<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg18
480B		CBZX %vreg18, <BB#4>; GPR64:%vreg18
	    Successors according to CFG: BB#4 BB#3

496B	BB#3: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#2
512B		%vreg20<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg20
528B		STRWui %WZR, %vreg20, 1274; mem:ST4[%lastErr] GPR64common:%vreg20
	    Successors according to CFG: BB#4

544B	BB#4: derived from LLVM BB %if.end.3
	    Predecessors according to CFG: BB#2 BB#3
560B		%vreg22<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg22
576B		CBNZX %vreg22, <BB#10>; GPR64:%vreg22
	    Successors according to CFG: BB#10 BB#5

592B	BB#5: derived from LLVM BB %if.then.5
	    Predecessors according to CFG: BB#4
608B		%vreg58<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg58
624B		CBZX %vreg58, <BB#7>; GPR64:%vreg58
	    Successors according to CFG: BB#7 BB#6

640B	BB#6: derived from LLVM BB %if.then.7
	    Predecessors according to CFG: BB#5
656B		%vreg60<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg60
672B		STRWui %WZR, %vreg60, 0; mem:ST4[%8] GPR64common:%vreg60
	    Successors according to CFG: BB#7

688B	BB#7: derived from LLVM BB %if.end.8
	    Predecessors according to CFG: BB#5 BB#6
704B		%vreg62<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg62
720B		CBZX %vreg62, <BB#9>; GPR64:%vreg62
	    Successors according to CFG: BB#9 BB#8

736B	BB#8: derived from LLVM BB %if.then.10
	    Predecessors according to CFG: BB#7
752B		%vreg64<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg64
768B		STRWui %WZR, %vreg64, 1274; mem:ST4[%lastErr11] GPR64common:%vreg64
	    Successors according to CFG: BB#9

784B	BB#9: derived from LLVM BB %if.end.12
	    Predecessors according to CFG: BB#7 BB#8
800B		B <BB#19>
	    Successors according to CFG: BB#19

816B	BB#10: derived from LLVM BB %if.end.13
	    Predecessors according to CFG: BB#4
832B		%vreg29<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg29
848B		%vreg26<def> = MOVi64imm 5012; GPR64:%vreg26
864B		%vreg27<def> = ADDXrr %vreg29, %vreg26; GPR64common:%vreg27 GPR64:%vreg29,%vreg26
880B		%vreg28<def> = LDRBBui %vreg27, 0; mem:LD1[%writing] GPR32:%vreg28 GPR64common:%vreg27
896B		%vreg24<def> = UBFMWri %vreg28, 0, 7; GPR32:%vreg24,%vreg28
912B		CBZW %vreg24, <BB#16>; GPR32:%vreg24
	    Successors according to CFG: BB#16 BB#11

928B	BB#11: derived from LLVM BB %if.then.14
	    Predecessors according to CFG: BB#10
944B		%vreg48<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg48
960B		CBZX %vreg48, <BB#13>; GPR64:%vreg48
	    Successors according to CFG: BB#13 BB#12

976B	BB#12: derived from LLVM BB %if.then.16
	    Predecessors according to CFG: BB#11
992B		%vreg49<def> = MOVi32imm 4294967295; GPR32:%vreg49
1008B		%vreg51<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg51
1024B		STRWui %vreg49, %vreg51, 0; mem:ST4[%14] GPR32:%vreg49 GPR64common:%vreg51
	    Successors according to CFG: BB#13

1040B	BB#13: derived from LLVM BB %if.end.17
	    Predecessors according to CFG: BB#11 BB#12
1056B		%vreg53<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg53
1072B		CBZX %vreg53, <BB#15>; GPR64:%vreg53
	    Successors according to CFG: BB#15 BB#14

1088B	BB#14: derived from LLVM BB %if.then.19
	    Predecessors according to CFG: BB#13
1104B		%vreg54<def> = MOVi32imm 4294967295; GPR32:%vreg54
1120B		%vreg56<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg56
1136B		STRWui %vreg54, %vreg56, 1274; mem:ST4[%lastErr20] GPR32:%vreg54 GPR64common:%vreg56
	    Successors according to CFG: BB#15

1152B	BB#15: derived from LLVM BB %if.end.21
	    Predecessors according to CFG: BB#13 BB#14
1168B		B <BB#19>
	    Successors according to CFG: BB#19

1184B	BB#16: derived from LLVM BB %if.end.22
	    Predecessors according to CFG: BB#10
1200B		%vreg36<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg36
1216B		%vreg33<def> = MOVi64imm 5100; GPR64:%vreg33
1232B		%vreg34<def> = ADDXrr %vreg36, %vreg33; GPR64common:%vreg34 GPR64:%vreg36,%vreg33
1248B		%vreg35<def> = LDRBBui %vreg34, 0; mem:LD1[%initialisedOk] GPR32:%vreg35 GPR64common:%vreg34
1264B		%vreg31<def> = UBFMWri %vreg35, 0, 7; GPR32:%vreg31,%vreg35
1280B		CBZW %vreg31, <BB#18>; GPR32:%vreg31
	    Successors according to CFG: BB#18 BB#17

1296B	BB#17: derived from LLVM BB %if.then.24
	    Predecessors according to CFG: BB#16
1312B		%vreg42<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg42
1328B		%vreg40<def> = MOVi64imm 5016; GPR64:%vreg40
1344B		%vreg41<def> = ADDXrr %vreg42, %vreg40; GPR64:%vreg41,%vreg42,%vreg40
1360B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1376B		%X0<def> = COPY %vreg41; GPR64:%vreg41
1392B		BL <ga:@BZ2_bzDecompressEnd>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
1408B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1424B		%vreg38<def,dead> = COPY %W0; GPR32all:%vreg38
1440B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1456B		STACKMAP 1, 0, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2]
1472B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#18

1488B	BB#18: derived from LLVM BB %if.end.25
	    Predecessors according to CFG: BB#16 BB#17
1504B		%vreg46<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg46
1520B		%vreg45<def> = COPY %vreg46; GPR64all:%vreg45 GPR64:%vreg46
1536B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1552B		%X0<def> = COPY %vreg45; GPR64all:%vreg45
1568B		BL <ga:@free>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>
1584B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1600B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1616B		STACKMAP 2, 0, %LR<earlyclobber,imp-def,dead>, ...
1632B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#19

1648B	BB#19: derived from LLVM BB %return
	    Predecessors according to CFG: BB#18 BB#15 BB#9
1664B		%vreg65<def> = ADRP <ga:@BZ2_bzReadClose>[TF=1]; GPR64common:%vreg65
1680B		%vreg66<def> = ADDXri %vreg65, <ga:@BZ2_bzReadClose>[TF=34], 0; GPR64sp:%vreg66 GPR64common:%vreg65
1696B		%vreg67<def> = COPY %vreg66; GPR64all:%vreg67 GPR64sp:%vreg66
1712B		%vreg68<def> = COPY %vreg14; GPR64all:%vreg68 GPR64:%vreg14
1728B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1744B		%X0<def> = COPY %vreg67; GPR64all:%vreg67
1760B		%X1<def> = COPY %vreg68; GPR64all:%vreg68
1776B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
1792B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1808B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1824B		STACKMAP 3, 0, %LR<earlyclobber,imp-def,dead>, ...
1840B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1856B		RET_ReallyLR

# End machine code for function BZ2_bzReadClose.

********** SIMPLE REGISTER COALESCING **********
********** Function: BZ2_bzReadClose
********** JOINING INTERVALS ***********
if.end:
if.end.3:
if.end.8:
if.end.17:
if.then.5:
if.end.12:
if.end.13:
if.then.14:
if.end.21:
if.end.22:
if.end.25:
1552B	%X0<def> = COPY %vreg45; GPR64all:%vreg45
	Considering merging %vreg45 with %X0
	Can only merge into reserved registers.
return:
1744B	%X0<def> = COPY %vreg67; GPR64all:%vreg67
	Considering merging %vreg67 with %X0
	Can only merge into reserved registers.
1760B	%X1<def> = COPY %vreg68; GPR64all:%vreg68
	Considering merging %vreg68 with %X1
	Can only merge into reserved registers.
entry:
16B	%vreg14<def> = COPY %LR; GPR64:%vreg14
	Considering merging %vreg14 with %LR
	Can only merge into reserved registers.
32B	%vreg2<def> = COPY %X1; GPR64:%vreg2
	Considering merging %vreg2 with %X1
	Can only merge into reserved registers.
48B	%vreg0<def> = COPY %X0; GPR64:%vreg0
	Considering merging %vreg0 with %X0
	Can only merge into reserved registers.
176B	%X0<def> = COPY %vreg12; GPR64all:%vreg12
	Considering merging %vreg12 with %X0
	Can only merge into reserved registers.
192B	%X1<def> = COPY %vreg13; GPR64all:%vreg13
	Considering merging %vreg13 with %X1
	Can only merge into reserved registers.
if.then:
if.then.2:
if.then.7:
if.then.10:
if.then.16:
if.then.19:
if.then.24:
1376B	%X0<def> = COPY %vreg41; GPR64:%vreg41
	Considering merging %vreg41 with %X0
	Can only merge into reserved registers.
1424B	%vreg38<def,dead> = COPY %W0; GPR32all:%vreg38
	Considering merging %vreg38 with %W0
	Can only merge into reserved registers.
1520B	%vreg45<def> = COPY %vreg46; GPR64all:%vreg45 GPR64:%vreg46
	Considering merging to GPR64 with %vreg46 in %vreg45
		RHS = %vreg46 [1504r,1520r:0)  0@1504r
		LHS = %vreg45 [1520r,1552r:0)  0@1520r
		merge %vreg45:0@1520r into %vreg46:0@1504r --> @1504r
		erased:	1520r	%vreg45<def> = COPY %vreg46; GPR64all:%vreg45 GPR64:%vreg46
		updated: 1504B	%vreg45<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg45
	Success: %vreg46 -> %vreg45
	Result = %vreg45 [1504r,1552r:0)  0@1504r
1696B	%vreg67<def> = COPY %vreg66; GPR64all:%vreg67 GPR64sp:%vreg66
	Considering merging to GPR64sp with %vreg66 in %vreg67
		RHS = %vreg66 [1680r,1696r:0)  0@1680r
		LHS = %vreg67 [1696r,1744r:0)  0@1696r
		merge %vreg67:0@1696r into %vreg66:0@1680r --> @1680r
		erased:	1696r	%vreg67<def> = COPY %vreg66; GPR64all:%vreg67 GPR64sp:%vreg66
		updated: 1680B	%vreg67<def> = ADDXri %vreg65, <ga:@BZ2_bzReadClose>[TF=34], 0; GPR64sp:%vreg67 GPR64common:%vreg65
	Success: %vreg66 -> %vreg67
	Result = %vreg67 [1680r,1744r:0)  0@1680r
1712B	%vreg68<def> = COPY %vreg14; GPR64all:%vreg68 GPR64:%vreg14
	Considering merging to GPR64 with %vreg14 in %vreg68
		RHS = %vreg14 [16r,1712r:0)  0@16r
		LHS = %vreg68 [1712r,1760r:0)  0@1712r
		merge %vreg68:0@1712r into %vreg14:0@16r --> @16r
		erased:	1712r	%vreg68<def> = COPY %vreg14; GPR64all:%vreg68 GPR64:%vreg14
		updated: 16B	%vreg68<def> = COPY %LR; GPR64:%vreg68
		updated: 144B	%vreg13<def> = COPY %vreg68; GPR64all:%vreg13 GPR64:%vreg68
	Success: %vreg14 -> %vreg68
	Result = %vreg68 [16r,1760r:0)  0@16r
64B	%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
	Considering merging to GPR64 with %vreg0 in %vreg1
		RHS = %vreg0 [48r,64r:0)  0@48r
		LHS = %vreg1 [64r,288r:0)  0@64r
		merge %vreg1:0@64r into %vreg0:0@48r --> @48r
		erased:	64r	%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
		updated: 48B	%vreg1<def> = COPY %X0; GPR64:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [48r,288r:0)  0@48r
80B	%vreg3<def> = COPY %vreg2; GPR64:%vreg3,%vreg2
	Considering merging to GPR64 with %vreg2 in %vreg3
		RHS = %vreg2 [32r,80r:0)  0@32r
		LHS = %vreg3 [80r,304r:0)  0@80r
		merge %vreg3:0@80r into %vreg2:0@32r --> @32r
		erased:	80r	%vreg3<def> = COPY %vreg2; GPR64:%vreg3,%vreg2
		updated: 32B	%vreg3<def> = COPY %X1; GPR64:%vreg3
	Success: %vreg2 -> %vreg3
	Result = %vreg3 [32r,304r:0)  0@32r
128B	%vreg12<def> = COPY %vreg11; GPR64all:%vreg12 GPR64sp:%vreg11
	Considering merging to GPR64sp with %vreg11 in %vreg12
		RHS = %vreg11 [112r,128r:0)  0@112r
		LHS = %vreg12 [128r,176r:0)  0@128r
		merge %vreg12:0@128r into %vreg11:0@112r --> @112r
		erased:	128r	%vreg12<def> = COPY %vreg11; GPR64all:%vreg12 GPR64sp:%vreg11
		updated: 112B	%vreg12<def> = ADDXri %vreg10, <ga:@BZ2_bzReadClose>[TF=34], 0; GPR64sp:%vreg12 GPR64common:%vreg10
	Success: %vreg11 -> %vreg12
	Result = %vreg12 [112r,176r:0)  0@112r
144B	%vreg13<def> = COPY %vreg68; GPR64all:%vreg13 GPR64:%vreg68
	Considering merging to GPR64 with %vreg68 in %vreg13
		RHS = %vreg68 [16r,1760r:0)  0@16r
		LHS = %vreg13 [144r,192r:0)  0@144r
		merge %vreg13:0@144r into %vreg68:0@16r --> @16r
		erased:	144r	%vreg13<def> = COPY %vreg68; GPR64all:%vreg13 GPR64:%vreg68
		updated: 16B	%vreg13<def> = COPY %LR; GPR64:%vreg13
		updated: 1760B	%X1<def> = COPY %vreg13; GPR64:%vreg13
	Success: %vreg68 -> %vreg13
	Result = %vreg13 [16r,1760r:0)  0@16r
336B	%vreg8<def> = COPY %vreg9; GPR64:%vreg8,%vreg9
	Considering merging to GPR64 with %vreg9 in %vreg8
		RHS = %vreg9 [320r,336r:0)  0@320r
		LHS = %vreg8 [336r,352r:0)  0@336r
		merge %vreg8:0@336r into %vreg9:0@320r --> @320r
		erased:	336r	%vreg8<def> = COPY %vreg9; GPR64:%vreg8,%vreg9
		updated: 320B	%vreg8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg8
	Success: %vreg9 -> %vreg8
	Result = %vreg8 [320r,352r:0)  0@320r
1552B	%X0<def> = COPY %vreg45; GPR64:%vreg45
	Considering merging %vreg45 with %X0
	Can only merge into reserved registers.
1744B	%X0<def> = COPY %vreg67; GPR64sp:%vreg67
	Considering merging %vreg67 with %X0
	Can only merge into reserved registers.
1760B	%X1<def> = COPY %vreg13; GPR64:%vreg13
	Considering merging %vreg13 with %X1
	Can only merge into reserved registers.
176B	%X0<def> = COPY %vreg12; GPR64sp:%vreg12
	Considering merging %vreg12 with %X0
	Can only merge into reserved registers.
192B	%X1<def> = COPY %vreg13; GPR64:%vreg13
	Considering merging %vreg13 with %X1
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
W30 [0B,16r:0)[208r,208d:8)[256e,256d:2)[1392r,1392d:7)[1456e,1456d:1)[1568r,1568d:5)[1616e,1616d:6)[1776r,1776d:3)[1824e,1824d:4)  0@0B-phi 1@1456e 2@256e 3@1776r 4@1824e 5@1568r 6@1616e 7@1392r 8@208r
W0 [0B,48r:0)[176r,208r:5)[1376r,1392r:4)[1392r,1424r:1)[1552r,1568r:3)[1744r,1776r:2)  0@0B-phi 1@1392r 2@1744r 3@1552r 4@1376r 5@176r
W1 [0B,32r:0)[192r,208r:2)[1760r,1776r:1)  0@0B-phi 1@1760r 2@192r
%vreg1 [48r,288r:0)  0@48r
%vreg3 [32r,304r:0)  0@32r
%vreg5 [368r,384r:0)  0@368r
%vreg8 [320r,352r:0)  0@320r
%vreg10 [96r,112r:0)  0@96r
%vreg12 [112r,176r:0)  0@112r
%vreg13 [16r,1760r:0)  0@16r
%vreg16 [416r,432r:0)  0@416r
%vreg18 [464r,480r:0)  0@464r
%vreg20 [512r,528r:0)  0@512r
%vreg22 [560r,576r:0)  0@560r
%vreg24 [896r,912r:0)  0@896r
%vreg26 [848r,864r:0)  0@848r
%vreg27 [864r,880r:0)  0@864r
%vreg28 [880r,896r:0)  0@880r
%vreg29 [832r,864r:0)  0@832r
%vreg31 [1264r,1280r:0)  0@1264r
%vreg33 [1216r,1232r:0)  0@1216r
%vreg34 [1232r,1248r:0)  0@1232r
%vreg35 [1248r,1264r:0)  0@1248r
%vreg36 [1200r,1232r:0)  0@1200r
%vreg38 [1424r,1424d:0)  0@1424r
%vreg40 [1328r,1344r:0)  0@1328r
%vreg41 [1344r,1376r:0)  0@1344r
%vreg42 [1312r,1344r:0)  0@1312r
%vreg45 [1504r,1552r:0)  0@1504r
%vreg48 [944r,960r:0)  0@944r
%vreg49 [992r,1024r:0)  0@992r
%vreg51 [1008r,1024r:0)  0@1008r
%vreg53 [1056r,1072r:0)  0@1056r
%vreg54 [1104r,1136r:0)  0@1104r
%vreg56 [1120r,1136r:0)  0@1120r
%vreg58 [608r,624r:0)  0@608r
%vreg60 [656r,672r:0)  0@656r
%vreg62 [704r,720r:0)  0@704r
%vreg64 [752r,768r:0)  0@752r
%vreg65 [1664r,1680r:0)  0@1664r
%vreg67 [1680r,1744r:0)  0@1680r
RegMasks: 208r 1392r 1568r 1776r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzReadClose: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=8, align=8, at location [SP]
Function Live Ins: %X0 in %vreg0, %X1 in %vreg2, %LR in %vreg14

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %X1 %LR
16B		%vreg13<def> = COPY %LR; GPR64:%vreg13
32B		%vreg3<def> = COPY %X1; GPR64:%vreg3
48B		%vreg1<def> = COPY %X0; GPR64:%vreg1
96B		%vreg10<def> = ADRP <ga:@BZ2_bzReadClose>[TF=1]; GPR64common:%vreg10
112B		%vreg12<def> = ADDXri %vreg10, <ga:@BZ2_bzReadClose>[TF=34], 0; GPR64sp:%vreg12 GPR64common:%vreg10
160B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
176B		%X0<def> = COPY %vreg12; GPR64sp:%vreg12
192B		%X1<def> = COPY %vreg13; GPR64:%vreg13
208B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
224B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
240B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
256B		STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack2] GPR64:%vreg3,%vreg1
272B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
288B		STRXui %vreg1, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg1
304B		STRXui %vreg3, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg3
320B		%vreg8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg8
352B		STRXui %vreg8, <fi#2>, 0; mem:ST8[FixedStack2] GPR64:%vreg8
368B		%vreg5<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg5
384B		CBZX %vreg5, <BB#2>; GPR64:%vreg5
	    Successors according to CFG: BB#2 BB#1

400B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
416B		%vreg16<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg16
432B		STRWui %WZR, %vreg16, 0; mem:ST4[%3] GPR64common:%vreg16
	    Successors according to CFG: BB#2

448B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#1
464B		%vreg18<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg18
480B		CBZX %vreg18, <BB#4>; GPR64:%vreg18
	    Successors according to CFG: BB#4 BB#3

496B	BB#3: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#2
512B		%vreg20<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg20
528B		STRWui %WZR, %vreg20, 1274; mem:ST4[%lastErr] GPR64common:%vreg20
	    Successors according to CFG: BB#4

544B	BB#4: derived from LLVM BB %if.end.3
	    Predecessors according to CFG: BB#2 BB#3
560B		%vreg22<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg22
576B		CBNZX %vreg22, <BB#10>; GPR64:%vreg22
	    Successors according to CFG: BB#10 BB#5

592B	BB#5: derived from LLVM BB %if.then.5
	    Predecessors according to CFG: BB#4
608B		%vreg58<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg58
624B		CBZX %vreg58, <BB#7>; GPR64:%vreg58
	    Successors according to CFG: BB#7 BB#6

640B	BB#6: derived from LLVM BB %if.then.7
	    Predecessors according to CFG: BB#5
656B		%vreg60<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg60
672B		STRWui %WZR, %vreg60, 0; mem:ST4[%8] GPR64common:%vreg60
	    Successors according to CFG: BB#7

688B	BB#7: derived from LLVM BB %if.end.8
	    Predecessors according to CFG: BB#5 BB#6
704B		%vreg62<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg62
720B		CBZX %vreg62, <BB#9>; GPR64:%vreg62
	    Successors according to CFG: BB#9 BB#8

736B	BB#8: derived from LLVM BB %if.then.10
	    Predecessors according to CFG: BB#7
752B		%vreg64<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg64
768B		STRWui %WZR, %vreg64, 1274; mem:ST4[%lastErr11] GPR64common:%vreg64
	    Successors according to CFG: BB#9

784B	BB#9: derived from LLVM BB %if.end.12
	    Predecessors according to CFG: BB#7 BB#8
800B		B <BB#19>
	    Successors according to CFG: BB#19

816B	BB#10: derived from LLVM BB %if.end.13
	    Predecessors according to CFG: BB#4
832B		%vreg29<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg29
848B		%vreg26<def> = MOVi64imm 5012; GPR64:%vreg26
864B		%vreg27<def> = ADDXrr %vreg29, %vreg26; GPR64common:%vreg27 GPR64:%vreg29,%vreg26
880B		%vreg28<def> = LDRBBui %vreg27, 0; mem:LD1[%writing] GPR32:%vreg28 GPR64common:%vreg27
896B		%vreg24<def> = UBFMWri %vreg28, 0, 7; GPR32:%vreg24,%vreg28
912B		CBZW %vreg24, <BB#16>; GPR32:%vreg24
	    Successors according to CFG: BB#16 BB#11

928B	BB#11: derived from LLVM BB %if.then.14
	    Predecessors according to CFG: BB#10
944B		%vreg48<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg48
960B		CBZX %vreg48, <BB#13>; GPR64:%vreg48
	    Successors according to CFG: BB#13 BB#12

976B	BB#12: derived from LLVM BB %if.then.16
	    Predecessors according to CFG: BB#11
992B		%vreg49<def> = MOVi32imm 4294967295; GPR32:%vreg49
1008B		%vreg51<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg51
1024B		STRWui %vreg49, %vreg51, 0; mem:ST4[%14] GPR32:%vreg49 GPR64common:%vreg51
	    Successors according to CFG: BB#13

1040B	BB#13: derived from LLVM BB %if.end.17
	    Predecessors according to CFG: BB#11 BB#12
1056B		%vreg53<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg53
1072B		CBZX %vreg53, <BB#15>; GPR64:%vreg53
	    Successors according to CFG: BB#15 BB#14

1088B	BB#14: derived from LLVM BB %if.then.19
	    Predecessors according to CFG: BB#13
1104B		%vreg54<def> = MOVi32imm 4294967295; GPR32:%vreg54
1120B		%vreg56<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg56
1136B		STRWui %vreg54, %vreg56, 1274; mem:ST4[%lastErr20] GPR32:%vreg54 GPR64common:%vreg56
	    Successors according to CFG: BB#15

1152B	BB#15: derived from LLVM BB %if.end.21
	    Predecessors according to CFG: BB#13 BB#14
1168B		B <BB#19>
	    Successors according to CFG: BB#19

1184B	BB#16: derived from LLVM BB %if.end.22
	    Predecessors according to CFG: BB#10
1200B		%vreg36<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg36
1216B		%vreg33<def> = MOVi64imm 5100; GPR64:%vreg33
1232B		%vreg34<def> = ADDXrr %vreg36, %vreg33; GPR64common:%vreg34 GPR64:%vreg36,%vreg33
1248B		%vreg35<def> = LDRBBui %vreg34, 0; mem:LD1[%initialisedOk] GPR32:%vreg35 GPR64common:%vreg34
1264B		%vreg31<def> = UBFMWri %vreg35, 0, 7; GPR32:%vreg31,%vreg35
1280B		CBZW %vreg31, <BB#18>; GPR32:%vreg31
	    Successors according to CFG: BB#18 BB#17

1296B	BB#17: derived from LLVM BB %if.then.24
	    Predecessors according to CFG: BB#16
1312B		%vreg42<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg42
1328B		%vreg40<def> = MOVi64imm 5016; GPR64:%vreg40
1344B		%vreg41<def> = ADDXrr %vreg42, %vreg40; GPR64:%vreg41,%vreg42,%vreg40
1360B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1376B		%X0<def> = COPY %vreg41; GPR64:%vreg41
1392B		BL <ga:@BZ2_bzDecompressEnd>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
1408B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1424B		%vreg38<def,dead> = COPY %W0; GPR32all:%vreg38
1440B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1456B		STACKMAP 1, 0, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2]
1472B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#18

1488B	BB#18: derived from LLVM BB %if.end.25
	    Predecessors according to CFG: BB#16 BB#17
1504B		%vreg45<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg45
1536B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1552B		%X0<def> = COPY %vreg45; GPR64:%vreg45
1568B		BL <ga:@free>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>
1584B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1600B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1616B		STACKMAP 2, 0, %LR<earlyclobber,imp-def,dead>, ...
1632B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#19

1648B	BB#19: derived from LLVM BB %return
	    Predecessors according to CFG: BB#18 BB#15 BB#9
1664B		%vreg65<def> = ADRP <ga:@BZ2_bzReadClose>[TF=1]; GPR64common:%vreg65
1680B		%vreg67<def> = ADDXri %vreg65, <ga:@BZ2_bzReadClose>[TF=34], 0; GPR64sp:%vreg67 GPR64common:%vreg65
1728B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1744B		%X0<def> = COPY %vreg67; GPR64sp:%vreg67
1760B		%X1<def> = COPY %vreg13; GPR64:%vreg13
1776B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
1792B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1808B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1824B		STACKMAP 3, 0, %LR<earlyclobber,imp-def,dead>, ...
1840B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1856B		RET_ReallyLR

# End machine code for function BZ2_bzReadClose.

handleMove 992B -> 1016B: %vreg49<def> = MOVi32imm 4294967295; GPR32:%vreg49
     %vreg49:	[992r,1024r:0)  0@992r
        -->	[1016r,1024r:0)  0@1016r
handleMove 1104B -> 1128B: %vreg54<def> = MOVi32imm 4294967295; GPR32:%vreg54
     %vreg54:	[1104r,1136r:0)  0@1104r
        -->	[1128r,1136r:0)  0@1128r
********** GREEDY REGISTER ALLOCATION **********
********** Function: BZ2_bzReadClose
********** INTERVALS **********
W30 [0B,16r:0)[208r,208d:8)[256e,256d:2)[1392r,1392d:7)[1456e,1456d:1)[1568r,1568d:5)[1616e,1616d:6)[1776r,1776d:3)[1824e,1824d:4)  0@0B-phi 1@1456e 2@256e 3@1776r 4@1824e 5@1568r 6@1616e 7@1392r 8@208r
W0 [0B,48r:0)[176r,208r:5)[1376r,1392r:4)[1392r,1424r:1)[1552r,1568r:3)[1744r,1776r:2)  0@0B-phi 1@1392r 2@1744r 3@1552r 4@1376r 5@176r
W1 [0B,32r:0)[192r,208r:2)[1760r,1776r:1)  0@0B-phi 1@1760r 2@192r
%vreg1 [48r,288r:0)  0@48r
%vreg3 [32r,304r:0)  0@32r
%vreg5 [368r,384r:0)  0@368r
%vreg8 [320r,352r:0)  0@320r
%vreg10 [96r,112r:0)  0@96r
%vreg12 [112r,176r:0)  0@112r
%vreg13 [16r,1760r:0)  0@16r
%vreg16 [416r,432r:0)  0@416r
%vreg18 [464r,480r:0)  0@464r
%vreg20 [512r,528r:0)  0@512r
%vreg22 [560r,576r:0)  0@560r
%vreg24 [896r,912r:0)  0@896r
%vreg26 [848r,864r:0)  0@848r
%vreg27 [864r,880r:0)  0@864r
%vreg28 [880r,896r:0)  0@880r
%vreg29 [832r,864r:0)  0@832r
%vreg31 [1264r,1280r:0)  0@1264r
%vreg33 [1216r,1232r:0)  0@1216r
%vreg34 [1232r,1248r:0)  0@1232r
%vreg35 [1248r,1264r:0)  0@1248r
%vreg36 [1200r,1232r:0)  0@1200r
%vreg38 [1424r,1424d:0)  0@1424r
%vreg40 [1328r,1344r:0)  0@1328r
%vreg41 [1344r,1376r:0)  0@1344r
%vreg42 [1312r,1344r:0)  0@1312r
%vreg45 [1504r,1552r:0)  0@1504r
%vreg48 [944r,960r:0)  0@944r
%vreg49 [1016r,1024r:0)  0@1016r
%vreg51 [1008r,1024r:0)  0@1008r
%vreg53 [1056r,1072r:0)  0@1056r
%vreg54 [1128r,1136r:0)  0@1128r
%vreg56 [1120r,1136r:0)  0@1120r
%vreg58 [608r,624r:0)  0@608r
%vreg60 [656r,672r:0)  0@656r
%vreg62 [704r,720r:0)  0@704r
%vreg64 [752r,768r:0)  0@752r
%vreg65 [1664r,1680r:0)  0@1664r
%vreg67 [1680r,1744r:0)  0@1680r
RegMasks: 208r 1392r 1568r 1776r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzReadClose: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=8, align=8, at location [SP]
Function Live Ins: %X0 in %vreg0, %X1 in %vreg2, %LR in %vreg14

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %X1 %LR
16B		%vreg13<def> = COPY %LR; GPR64:%vreg13
32B		%vreg3<def> = COPY %X1; GPR64:%vreg3
48B		%vreg1<def> = COPY %X0; GPR64:%vreg1
96B		%vreg10<def> = ADRP <ga:@BZ2_bzReadClose>[TF=1]; GPR64common:%vreg10
112B		%vreg12<def> = ADDXri %vreg10, <ga:@BZ2_bzReadClose>[TF=34], 0; GPR64sp:%vreg12 GPR64common:%vreg10
160B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
176B		%X0<def> = COPY %vreg12; GPR64sp:%vreg12
192B		%X1<def> = COPY %vreg13; GPR64:%vreg13
208B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
224B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
240B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
256B		STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack2] GPR64:%vreg3,%vreg1
272B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
288B		STRXui %vreg1, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg1
304B		STRXui %vreg3, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg3
320B		%vreg8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg8
352B		STRXui %vreg8, <fi#2>, 0; mem:ST8[FixedStack2] GPR64:%vreg8
368B		%vreg5<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg5
384B		CBZX %vreg5, <BB#2>; GPR64:%vreg5
	    Successors according to CFG: BB#2 BB#1

400B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
416B		%vreg16<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg16
432B		STRWui %WZR, %vreg16, 0; mem:ST4[%3] GPR64common:%vreg16
	    Successors according to CFG: BB#2

448B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#1
464B		%vreg18<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg18
480B		CBZX %vreg18, <BB#4>; GPR64:%vreg18
	    Successors according to CFG: BB#4 BB#3

496B	BB#3: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#2
512B		%vreg20<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg20
528B		STRWui %WZR, %vreg20, 1274; mem:ST4[%lastErr] GPR64common:%vreg20
	    Successors according to CFG: BB#4

544B	BB#4: derived from LLVM BB %if.end.3
	    Predecessors according to CFG: BB#2 BB#3
560B		%vreg22<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg22
576B		CBNZX %vreg22, <BB#10>; GPR64:%vreg22
	    Successors according to CFG: BB#10 BB#5

592B	BB#5: derived from LLVM BB %if.then.5
	    Predecessors according to CFG: BB#4
608B		%vreg58<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg58
624B		CBZX %vreg58, <BB#7>; GPR64:%vreg58
	    Successors according to CFG: BB#7 BB#6

640B	BB#6: derived from LLVM BB %if.then.7
	    Predecessors according to CFG: BB#5
656B		%vreg60<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg60
672B		STRWui %WZR, %vreg60, 0; mem:ST4[%8] GPR64common:%vreg60
	    Successors according to CFG: BB#7

688B	BB#7: derived from LLVM BB %if.end.8
	    Predecessors according to CFG: BB#5 BB#6
704B		%vreg62<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg62
720B		CBZX %vreg62, <BB#9>; GPR64:%vreg62
	    Successors according to CFG: BB#9 BB#8

736B	BB#8: derived from LLVM BB %if.then.10
	    Predecessors according to CFG: BB#7
752B		%vreg64<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg64
768B		STRWui %WZR, %vreg64, 1274; mem:ST4[%lastErr11] GPR64common:%vreg64
	    Successors according to CFG: BB#9

784B	BB#9: derived from LLVM BB %if.end.12
	    Predecessors according to CFG: BB#7 BB#8
800B		B <BB#19>
	    Successors according to CFG: BB#19

816B	BB#10: derived from LLVM BB %if.end.13
	    Predecessors according to CFG: BB#4
832B		%vreg29<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg29
848B		%vreg26<def> = MOVi64imm 5012; GPR64:%vreg26
864B		%vreg27<def> = ADDXrr %vreg29, %vreg26; GPR64common:%vreg27 GPR64:%vreg29,%vreg26
880B		%vreg28<def> = LDRBBui %vreg27, 0; mem:LD1[%writing] GPR32:%vreg28 GPR64common:%vreg27
896B		%vreg24<def> = UBFMWri %vreg28, 0, 7; GPR32:%vreg24,%vreg28
912B		CBZW %vreg24, <BB#16>; GPR32:%vreg24
	    Successors according to CFG: BB#16 BB#11

928B	BB#11: derived from LLVM BB %if.then.14
	    Predecessors according to CFG: BB#10
944B		%vreg48<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg48
960B		CBZX %vreg48, <BB#13>; GPR64:%vreg48
	    Successors according to CFG: BB#13 BB#12

976B	BB#12: derived from LLVM BB %if.then.16
	    Predecessors according to CFG: BB#11
1008B		%vreg51<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg51
1016B		%vreg49<def> = MOVi32imm 4294967295; GPR32:%vreg49
1024B		STRWui %vreg49, %vreg51, 0; mem:ST4[%14] GPR32:%vreg49 GPR64common:%vreg51
	    Successors according to CFG: BB#13

1040B	BB#13: derived from LLVM BB %if.end.17
	    Predecessors according to CFG: BB#11 BB#12
1056B		%vreg53<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg53
1072B		CBZX %vreg53, <BB#15>; GPR64:%vreg53
	    Successors according to CFG: BB#15 BB#14

1088B	BB#14: derived from LLVM BB %if.then.19
	    Predecessors according to CFG: BB#13
1120B		%vreg56<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg56
1128B		%vreg54<def> = MOVi32imm 4294967295; GPR32:%vreg54
1136B		STRWui %vreg54, %vreg56, 1274; mem:ST4[%lastErr20] GPR32:%vreg54 GPR64common:%vreg56
	    Successors according to CFG: BB#15

1152B	BB#15: derived from LLVM BB %if.end.21
	    Predecessors according to CFG: BB#13 BB#14
1168B		B <BB#19>
	    Successors according to CFG: BB#19

1184B	BB#16: derived from LLVM BB %if.end.22
	    Predecessors according to CFG: BB#10
1200B		%vreg36<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg36
1216B		%vreg33<def> = MOVi64imm 5100; GPR64:%vreg33
1232B		%vreg34<def> = ADDXrr %vreg36, %vreg33; GPR64common:%vreg34 GPR64:%vreg36,%vreg33
1248B		%vreg35<def> = LDRBBui %vreg34, 0; mem:LD1[%initialisedOk] GPR32:%vreg35 GPR64common:%vreg34
1264B		%vreg31<def> = UBFMWri %vreg35, 0, 7; GPR32:%vreg31,%vreg35
1280B		CBZW %vreg31, <BB#18>; GPR32:%vreg31
	    Successors according to CFG: BB#18 BB#17

1296B	BB#17: derived from LLVM BB %if.then.24
	    Predecessors according to CFG: BB#16
1312B		%vreg42<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg42
1328B		%vreg40<def> = MOVi64imm 5016; GPR64:%vreg40
1344B		%vreg41<def> = ADDXrr %vreg42, %vreg40; GPR64:%vreg41,%vreg42,%vreg40
1360B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1376B		%X0<def> = COPY %vreg41; GPR64:%vreg41
1392B		BL <ga:@BZ2_bzDecompressEnd>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
1408B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1424B		%vreg38<def,dead> = COPY %W0; GPR32all:%vreg38
1440B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1456B		STACKMAP 1, 0, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2]
1472B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#18

1488B	BB#18: derived from LLVM BB %if.end.25
	    Predecessors according to CFG: BB#16 BB#17
1504B		%vreg45<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg45
1536B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1552B		%X0<def> = COPY %vreg45; GPR64:%vreg45
1568B		BL <ga:@free>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>
1584B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1600B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1616B		STACKMAP 2, 0, %LR<earlyclobber,imp-def,dead>, ...
1632B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#19

1648B	BB#19: derived from LLVM BB %return
	    Predecessors according to CFG: BB#18 BB#15 BB#9
1664B		%vreg65<def> = ADRP <ga:@BZ2_bzReadClose>[TF=1]; GPR64common:%vreg65
1680B		%vreg67<def> = ADDXri %vreg65, <ga:@BZ2_bzReadClose>[TF=34], 0; GPR64sp:%vreg67 GPR64common:%vreg65
1728B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1744B		%X0<def> = COPY %vreg67; GPR64sp:%vreg67
1760B		%X1<def> = COPY %vreg13; GPR64:%vreg13
1776B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
1792B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1808B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1824B		STACKMAP 3, 0, %LR<earlyclobber,imp-def,dead>, ...
1840B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1856B		RET_ReallyLR

# End machine code for function BZ2_bzReadClose.


selectOrSplit GPR64:%vreg13 [16r,1760r:0)  0@16r w=1.413246e-03
hints: %X1
missed hint %X1
assigning %vreg13 to %X19: W19 [16r,1760r:0)  0@16r

selectOrSplit GPR64:%vreg3 [32r,304r:0)  0@32r w=4.508928e-03
hints: %X1
missed hint %X1
assigning %vreg3 to %X20: W20 [32r,304r:0)  0@32r

selectOrSplit GPR64:%vreg1 [48r,288r:0)  0@48r w=4.734375e-03
hints: %X0
missed hint %X0
assigning %vreg1 to %X21: W21 [48r,288r:0)  0@48r

selectOrSplit GPR64sp:%vreg12 [112r,176r:0)  0@112r w=4.353448e-03
hints: %X0
assigning %vreg12 to %X0: W0 [112r,176r:0)  0@112r

selectOrSplit GPR64:%vreg41 [1344r,1376r:0)  0@1344r w=5.937684e-04
hints: %X0
assigning %vreg41 to %X0: W0 [1344r,1376r:0)  0@1344r

selectOrSplit GPR32all:%vreg38 [1424r,1424d:0)  0@1424r w=inf
hints: %W0
assigning %vreg38 to %W0: W0 [1424r,1424d:0)  0@1424r

selectOrSplit GPR64:%vreg45 [1504r,1552r:0)  0@1504r w=1.073555e-03
hints: %X0
assigning %vreg45 to %X0: W0 [1504r,1552r:0)  0@1504r

selectOrSplit GPR64sp:%vreg67 [1680r,1744r:0)  0@1680r w=4.353448e-03
hints: %X0
assigning %vreg67 to %X0: W0 [1680r,1744r:0)  0@1680r

selectOrSplit GPR64common:%vreg10 [96r,112r:0)  0@96r w=inf
assigning %vreg10 to %X8: W8 [96r,112r:0)  0@96r

selectOrSplit GPR64:%vreg8 [320r,352r:0)  0@320r w=inf
assigning %vreg8 to %X8: W8 [320r,352r:0)  0@320r

selectOrSplit GPR64:%vreg5 [368r,384r:0)  0@368r w=inf
assigning %vreg5 to %X8: W8 [368r,384r:0)  0@368r

selectOrSplit GPR64common:%vreg16 [416r,432r:0)  0@416r w=inf
assigning %vreg16 to %X8: W8 [416r,432r:0)  0@416r

selectOrSplit GPR64:%vreg18 [464r,480r:0)  0@464r w=inf
assigning %vreg18 to %X8: W8 [464r,480r:0)  0@464r

selectOrSplit GPR64common:%vreg20 [512r,528r:0)  0@512r w=inf
assigning %vreg20 to %X8: W8 [512r,528r:0)  0@512r

selectOrSplit GPR64:%vreg22 [560r,576r:0)  0@560r w=inf
assigning %vreg22 to %X8: W8 [560r,576r:0)  0@560r

selectOrSplit GPR64:%vreg58 [608r,624r:0)  0@608r w=inf
assigning %vreg58 to %X8: W8 [608r,624r:0)  0@608r

selectOrSplit GPR64common:%vreg60 [656r,672r:0)  0@656r w=inf
assigning %vreg60 to %X8: W8 [656r,672r:0)  0@656r

selectOrSplit GPR64:%vreg62 [704r,720r:0)  0@704r w=inf
assigning %vreg62 to %X8: W8 [704r,720r:0)  0@704r

selectOrSplit GPR64common:%vreg64 [752r,768r:0)  0@752r w=inf
assigning %vreg64 to %X8: W8 [752r,768r:0)  0@752r

selectOrSplit GPR64:%vreg29 [832r,864r:0)  0@832r w=2.278072e-03
assigning %vreg29 to %X8: W8 [832r,864r:0)  0@832r

selectOrSplit GPR64:%vreg26 [848r,864r:0)  0@848r w=inf
assigning %vreg26 to %X9: W9 [848r,864r:0)  0@848r

selectOrSplit GPR64common:%vreg27 [864r,880r:0)  0@864r w=inf
assigning %vreg27 to %X8: W8 [864r,880r:0)  0@864r

selectOrSplit GPR32:%vreg28 [880r,896r:0)  0@880r w=inf
assigning %vreg28 to %W8: W8 [880r,896r:0)  0@880r

selectOrSplit GPR32:%vreg24 [896r,912r:0)  0@896r w=inf
assigning %vreg24 to %W8: W8 [896r,912r:0)  0@896r

selectOrSplit GPR64:%vreg48 [944r,960r:0)  0@944r w=inf
assigning %vreg48 to %X8: W8 [944r,960r:0)  0@944r

selectOrSplit GPR64common:%vreg51 [1008r,1024r:0)  0@1008r w=6.105006e-04
assigning %vreg51 to %X8: W8 [1008r,1024r:0)  0@1008r

selectOrSplit GPR32:%vreg49 [1016r,1024r:0)  0@1016r w=inf
assigning %vreg49 to %W9: W9 [1016r,1024r:0)  0@1016r

selectOrSplit GPR64:%vreg53 [1056r,1072r:0)  0@1056r w=inf
assigning %vreg53 to %X8: W8 [1056r,1072r:0)  0@1056r

selectOrSplit GPR64common:%vreg56 [1120r,1136r:0)  0@1120r w=6.105006e-04
assigning %vreg56 to %X8: W8 [1120r,1136r:0)  0@1120r

selectOrSplit GPR32:%vreg54 [1128r,1136r:0)  0@1128r w=inf
assigning %vreg54 to %W9: W9 [1128r,1136r:0)  0@1128r

selectOrSplit GPR64:%vreg36 [1200r,1232r:0)  0@1200r w=1.102293e-03
assigning %vreg36 to %X8: W8 [1200r,1232r:0)  0@1200r

selectOrSplit GPR64:%vreg33 [1216r,1232r:0)  0@1216r w=inf
assigning %vreg33 to %X9: W9 [1216r,1232r:0)  0@1216r

selectOrSplit GPR64common:%vreg34 [1232r,1248r:0)  0@1232r w=inf
assigning %vreg34 to %X8: W8 [1232r,1248r:0)  0@1232r

selectOrSplit GPR32:%vreg35 [1248r,1264r:0)  0@1248r w=inf
assigning %vreg35 to %W8: W8 [1248r,1264r:0)  0@1248r

selectOrSplit GPR32:%vreg31 [1264r,1280r:0)  0@1264r w=inf
assigning %vreg31 to %W8: W8 [1264r,1280r:0)  0@1264r

selectOrSplit GPR64:%vreg42 [1312r,1344r:0)  0@1312r w=5.878895e-04
assigning %vreg42 to %X8: W8 [1312r,1344r:0)  0@1312r

selectOrSplit GPR64:%vreg40 [1328r,1344r:0)  0@1328r w=inf
assigning %vreg40 to %X9: W9 [1328r,1344r:0)  0@1328r

selectOrSplit GPR64common:%vreg65 [1664r,1680r:0)  0@1664r w=inf
assigning %vreg65 to %X8: W8 [1664r,1680r:0)  0@1664r

********** STACK TRANSFORMATION METADATA **********
********** Function: BZ2_bzReadClose
********** REGISTER MAP **********
[%vreg1 -> %X21] GPR64
[%vreg3 -> %X20] GPR64
[%vreg5 -> %X8] GPR64
[%vreg8 -> %X8] GPR64
[%vreg10 -> %X8] GPR64common
[%vreg12 -> %X0] GPR64sp
[%vreg13 -> %X19] GPR64
[%vreg16 -> %X8] GPR64common
[%vreg18 -> %X8] GPR64
[%vreg20 -> %X8] GPR64common
[%vreg22 -> %X8] GPR64
[%vreg24 -> %W8] GPR32
[%vreg26 -> %X9] GPR64
[%vreg27 -> %X8] GPR64common
[%vreg28 -> %W8] GPR32
[%vreg29 -> %X8] GPR64
[%vreg31 -> %W8] GPR32
[%vreg33 -> %X9] GPR64
[%vreg34 -> %X8] GPR64common
[%vreg35 -> %W8] GPR32
[%vreg36 -> %X8] GPR64
[%vreg38 -> %W0] GPR32all
[%vreg40 -> %X9] GPR64
[%vreg41 -> %X0] GPR64
[%vreg42 -> %X8] GPR64
[%vreg45 -> %X0] GPR64
[%vreg48 -> %X8] GPR64
[%vreg49 -> %W9] GPR32
[%vreg51 -> %X8] GPR64common
[%vreg53 -> %X8] GPR64
[%vreg54 -> %W9] GPR32
[%vreg56 -> %X8] GPR64common
[%vreg58 -> %X8] GPR64
[%vreg60 -> %X8] GPR64common
[%vreg62 -> %X8] GPR64
[%vreg64 -> %X8] GPR64common
[%vreg65 -> %X8] GPR64common
[%vreg67 -> %X0] GPR64sp


Stackmap 0:
  STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack2] GPR64:%vreg3,%vreg1

i8* %b: in register %X20 (vreg 3)
i8** %b.addr: in stack slot 1 (size: 8)
i32* %bzerror: in register %X21 (vreg 1)
i32** %bzerror.addr: in stack slot 0 (size: 8)
%struct.bzFile** %bzf: in stack slot 2 (size: 8)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2]

%struct.bzFile** %bzf: in stack slot 2 (size: 8)

Duplicate operand locations:


Stackmap 2:
  STACKMAP 2, 0, %LR<earlyclobber,imp-def,dead>, ...


Duplicate operand locations:


Stackmap 3:
  STACKMAP 3, 0, %LR<earlyclobber,imp-def,dead>, ...


Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack2] GPR64:%vreg3,%vreg1
  -> Call instruction SlotIndex 208B, searching vregs 0 -> 69 and stack slots 0 -> 3
    + vreg13 is live in register but not in stackmap
      Defining instruction: %vreg13<def> = COPY %LR; GPR64:%vreg13
      Value: generated value, 1 instruction(s)

  STACKMAP 1, 0, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2]
  -> Call instruction SlotIndex 1392B, searching vregs 0 -> 69 and stack slots 0 -> 3
    + vreg13 is live in register but not in stackmap
      Defining instruction: %vreg13<def> = COPY %LR; GPR64:%vreg13
      Value: generated value, 1 instruction(s)

  STACKMAP 2, 0, %LR<earlyclobber,imp-def,dead>, ...
  -> Call instruction SlotIndex 1568B, searching vregs 0 -> 69 and stack slots 0 -> 3
    + vreg13 is live in register but not in stackmap
      Defining instruction: %vreg13<def> = COPY %LR; GPR64:%vreg13
      Value: generated value, 1 instruction(s)

  STACKMAP 3, 0, %LR<earlyclobber,imp-def,dead>, ...
  -> Call instruction SlotIndex 1776B, searching vregs 0 -> 69 and stack slots 0 -> 3

********** REWRITE VIRTUAL REGISTERS **********
********** Function: BZ2_bzReadClose
********** REGISTER MAP **********
[%vreg1 -> %X21] GPR64
[%vreg3 -> %X20] GPR64
[%vreg5 -> %X8] GPR64
[%vreg8 -> %X8] GPR64
[%vreg10 -> %X8] GPR64common
[%vreg12 -> %X0] GPR64sp
[%vreg13 -> %X19] GPR64
[%vreg16 -> %X8] GPR64common
[%vreg18 -> %X8] GPR64
[%vreg20 -> %X8] GPR64common
[%vreg22 -> %X8] GPR64
[%vreg24 -> %W8] GPR32
[%vreg26 -> %X9] GPR64
[%vreg27 -> %X8] GPR64common
[%vreg28 -> %W8] GPR32
[%vreg29 -> %X8] GPR64
[%vreg31 -> %W8] GPR32
[%vreg33 -> %X9] GPR64
[%vreg34 -> %X8] GPR64common
[%vreg35 -> %W8] GPR32
[%vreg36 -> %X8] GPR64
[%vreg38 -> %W0] GPR32all
[%vreg40 -> %X9] GPR64
[%vreg41 -> %X0] GPR64
[%vreg42 -> %X8] GPR64
[%vreg45 -> %X0] GPR64
[%vreg48 -> %X8] GPR64
[%vreg49 -> %W9] GPR32
[%vreg51 -> %X8] GPR64common
[%vreg53 -> %X8] GPR64
[%vreg54 -> %W9] GPR32
[%vreg56 -> %X8] GPR64common
[%vreg58 -> %X8] GPR64
[%vreg60 -> %X8] GPR64common
[%vreg62 -> %X8] GPR64
[%vreg64 -> %X8] GPR64common
[%vreg65 -> %X8] GPR64common
[%vreg67 -> %X0] GPR64sp

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %LR %X0 %X1
16B		%vreg13<def> = COPY %LR; GPR64:%vreg13
32B		%vreg3<def> = COPY %X1; GPR64:%vreg3
48B		%vreg1<def> = COPY %X0; GPR64:%vreg1
96B		%vreg10<def> = ADRP <ga:@BZ2_bzReadClose>[TF=1]; GPR64common:%vreg10
112B		%vreg12<def> = ADDXri %vreg10<kill>, <ga:@BZ2_bzReadClose>[TF=34], 0; GPR64sp:%vreg12 GPR64common:%vreg10
160B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
176B		%X0<def> = COPY %vreg12<kill>; GPR64sp:%vreg12
192B		%X1<def> = COPY %vreg13; GPR64:%vreg13
208B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
224B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
240B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
256B		STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack2] GPR64:%vreg3,%vreg1
272B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
288B		STRXui %vreg1<kill>, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg1
304B		STRXui %vreg3<kill>, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg3
320B		%vreg8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg8
352B		STRXui %vreg8<kill>, <fi#2>, 0; mem:ST8[FixedStack2] GPR64:%vreg8
368B		%vreg5<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg5
384B		CBZX %vreg5<kill>, <BB#2>; GPR64:%vreg5
	    Successors according to CFG: BB#2 BB#1
> %X19<def> = COPY %LR
> %X20<def> = COPY %X1
> %X21<def> = COPY %X0
> %X8<def> = ADRP <ga:@BZ2_bzReadClose>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@BZ2_bzReadClose>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19
> BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 0, 0, %X20, 0, <fi#1>, 0, %X21, 0, <fi#0>, 0, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack2]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRXui %X21<kill>, <fi#0>, 0; mem:ST8[FixedStack0]
> STRXui %X20<kill>, <fi#1>, 0; mem:ST8[FixedStack1]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRXui %X8<kill>, <fi#2>, 0; mem:ST8[FixedStack2]
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> CBZX %X8<kill>, <BB#2>
400B	BB#1: derived from LLVM BB %if.then
	    Live Ins: %X19
	    Predecessors according to CFG: BB#0
416B		%vreg16<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg16
432B		STRWui %WZR, %vreg16<kill>, 0; mem:ST4[%3] GPR64common:%vreg16
	    Successors according to CFG: BB#2
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> STRWui %WZR, %X8<kill>, 0; mem:ST4[%3]
448B	BB#2: derived from LLVM BB %if.end
	    Live Ins: %X19
	    Predecessors according to CFG: BB#0 BB#1
464B		%vreg18<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg18
480B		CBZX %vreg18<kill>, <BB#4>; GPR64:%vreg18
	    Successors according to CFG: BB#4 BB#3
> %X8<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2]
> CBZX %X8<kill>, <BB#4>
496B	BB#3: derived from LLVM BB %if.then.2
	    Live Ins: %X19
	    Predecessors according to CFG: BB#2
512B		%vreg20<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg20
528B		STRWui %WZR, %vreg20<kill>, 1274; mem:ST4[%lastErr] GPR64common:%vreg20
	    Successors according to CFG: BB#4
> %X8<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2]
> STRWui %WZR, %X8<kill>, 1274; mem:ST4[%lastErr]
544B	BB#4: derived from LLVM BB %if.end.3
	    Live Ins: %X19
	    Predecessors according to CFG: BB#2 BB#3
560B		%vreg22<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg22
576B		CBNZX %vreg22<kill>, <BB#10>; GPR64:%vreg22
	    Successors according to CFG: BB#10 BB#5
> %X8<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2]
> CBNZX %X8<kill>, <BB#10>
592B	BB#5: derived from LLVM BB %if.then.5
	    Live Ins: %X19
	    Predecessors according to CFG: BB#4
608B		%vreg58<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg58
624B		CBZX %vreg58<kill>, <BB#7>; GPR64:%vreg58
	    Successors according to CFG: BB#7 BB#6
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> CBZX %X8<kill>, <BB#7>
640B	BB#6: derived from LLVM BB %if.then.7
	    Live Ins: %X19
	    Predecessors according to CFG: BB#5
656B		%vreg60<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg60
672B		STRWui %WZR, %vreg60<kill>, 0; mem:ST4[%8] GPR64common:%vreg60
	    Successors according to CFG: BB#7
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> STRWui %WZR, %X8<kill>, 0; mem:ST4[%8]
688B	BB#7: derived from LLVM BB %if.end.8
	    Live Ins: %X19
	    Predecessors according to CFG: BB#5 BB#6
704B		%vreg62<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg62
720B		CBZX %vreg62<kill>, <BB#9>; GPR64:%vreg62
	    Successors according to CFG: BB#9 BB#8
> %X8<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2]
> CBZX %X8<kill>, <BB#9>
736B	BB#8: derived from LLVM BB %if.then.10
	    Live Ins: %X19
	    Predecessors according to CFG: BB#7
752B		%vreg64<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg64
768B		STRWui %WZR, %vreg64<kill>, 1274; mem:ST4[%lastErr11] GPR64common:%vreg64
	    Successors according to CFG: BB#9
> %X8<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2]
> STRWui %WZR, %X8<kill>, 1274; mem:ST4[%lastErr11]
784B	BB#9: derived from LLVM BB %if.end.12
	    Live Ins: %X19
	    Predecessors according to CFG: BB#7 BB#8
800B		B <BB#19>
	    Successors according to CFG: BB#19
> B <BB#19>
816B	BB#10: derived from LLVM BB %if.end.13
	    Live Ins: %X19
	    Predecessors according to CFG: BB#4
832B		%vreg29<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg29
848B		%vreg26<def> = MOVi64imm 5012; GPR64:%vreg26
864B		%vreg27<def> = ADDXrr %vreg29<kill>, %vreg26<kill>; GPR64common:%vreg27 GPR64:%vreg29,%vreg26
880B		%vreg28<def> = LDRBBui %vreg27<kill>, 0; mem:LD1[%writing] GPR32:%vreg28 GPR64common:%vreg27
896B		%vreg24<def> = UBFMWri %vreg28<kill>, 0, 7; GPR32:%vreg24,%vreg28
912B		CBZW %vreg24<kill>, <BB#16>; GPR32:%vreg24
	    Successors according to CFG: BB#16 BB#11
> %X8<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2]
> %X9<def> = MOVi64imm 5012
> %X8<def> = ADDXrr %X8<kill>, %X9<kill>
> %W8<def> = LDRBBui %X8<kill>, 0; mem:LD1[%writing]
> %W8<def> = UBFMWri %W8<kill>, 0, 7
> CBZW %W8<kill>, <BB#16>
928B	BB#11: derived from LLVM BB %if.then.14
	    Live Ins: %X19
	    Predecessors according to CFG: BB#10
944B		%vreg48<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg48
960B		CBZX %vreg48<kill>, <BB#13>; GPR64:%vreg48
	    Successors according to CFG: BB#13 BB#12
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> CBZX %X8<kill>, <BB#13>
976B	BB#12: derived from LLVM BB %if.then.16
	    Live Ins: %X19
	    Predecessors according to CFG: BB#11
1008B		%vreg51<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg51
1016B		%vreg49<def> = MOVi32imm 4294967295; GPR32:%vreg49
1024B		STRWui %vreg49<kill>, %vreg51<kill>, 0; mem:ST4[%14] GPR32:%vreg49 GPR64common:%vreg51
	    Successors according to CFG: BB#13
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %W9<def> = MOVi32imm 4294967295
> STRWui %W9<kill>, %X8<kill>, 0; mem:ST4[%14]
1040B	BB#13: derived from LLVM BB %if.end.17
	    Live Ins: %X19
	    Predecessors according to CFG: BB#11 BB#12
1056B		%vreg53<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg53
1072B		CBZX %vreg53<kill>, <BB#15>; GPR64:%vreg53
	    Successors according to CFG: BB#15 BB#14
> %X8<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2]
> CBZX %X8<kill>, <BB#15>
1088B	BB#14: derived from LLVM BB %if.then.19
	    Live Ins: %X19
	    Predecessors according to CFG: BB#13
1120B		%vreg56<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg56
1128B		%vreg54<def> = MOVi32imm 4294967295; GPR32:%vreg54
1136B		STRWui %vreg54<kill>, %vreg56<kill>, 1274; mem:ST4[%lastErr20] GPR32:%vreg54 GPR64common:%vreg56
	    Successors according to CFG: BB#15
> %X8<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2]
> %W9<def> = MOVi32imm 4294967295
> STRWui %W9<kill>, %X8<kill>, 1274; mem:ST4[%lastErr20]
1152B	BB#15: derived from LLVM BB %if.end.21
	    Live Ins: %X19
	    Predecessors according to CFG: BB#13 BB#14
1168B		B <BB#19>
	    Successors according to CFG: BB#19
> B <BB#19>
1184B	BB#16: derived from LLVM BB %if.end.22
	    Live Ins: %X19
	    Predecessors according to CFG: BB#10
1200B		%vreg36<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg36
1216B		%vreg33<def> = MOVi64imm 5100; GPR64:%vreg33
1232B		%vreg34<def> = ADDXrr %vreg36<kill>, %vreg33<kill>; GPR64common:%vreg34 GPR64:%vreg36,%vreg33
1248B		%vreg35<def> = LDRBBui %vreg34<kill>, 0; mem:LD1[%initialisedOk] GPR32:%vreg35 GPR64common:%vreg34
1264B		%vreg31<def> = UBFMWri %vreg35<kill>, 0, 7; GPR32:%vreg31,%vreg35
1280B		CBZW %vreg31<kill>, <BB#18>; GPR32:%vreg31
	    Successors according to CFG: BB#18 BB#17
> %X8<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2]
> %X9<def> = MOVi64imm 5100
> %X8<def> = ADDXrr %X8<kill>, %X9<kill>
> %W8<def> = LDRBBui %X8<kill>, 0; mem:LD1[%initialisedOk]
> %W8<def> = UBFMWri %W8<kill>, 0, 7
> CBZW %W8<kill>, <BB#18>
1296B	BB#17: derived from LLVM BB %if.then.24
	    Live Ins: %X19
	    Predecessors according to CFG: BB#16
1312B		%vreg42<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg42
1328B		%vreg40<def> = MOVi64imm 5016; GPR64:%vreg40
1344B		%vreg41<def> = ADDXrr %vreg42<kill>, %vreg40<kill>; GPR64:%vreg41,%vreg42,%vreg40
1360B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1376B		%X0<def> = COPY %vreg41<kill>; GPR64:%vreg41
1392B		BL <ga:@BZ2_bzDecompressEnd>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
1408B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1424B		%vreg38<def,dead> = COPY %W0; GPR32all:%vreg38
1440B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1456B		STACKMAP 1, 0, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2]
1472B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#18
> %X8<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2]
> %X9<def> = MOVi64imm 5016
> %X0<def> = ADDXrr %X8<kill>, %X9<kill>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BL <ga:@BZ2_bzDecompressEnd>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def,dead> = COPY %W0
Deleting identity copy.
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 1, 0, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1488B	BB#18: derived from LLVM BB %if.end.25
	    Live Ins: %X19
	    Predecessors according to CFG: BB#16 BB#17
1504B		%vreg45<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg45
1536B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1552B		%X0<def> = COPY %vreg45<kill>; GPR64:%vreg45
1568B		BL <ga:@free>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>
1584B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1600B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1616B		STACKMAP 2, 0, %LR<earlyclobber,imp-def,dead>, ...
1632B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#19
> %X0<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BL <ga:@free>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 2, 0, %LR<earlyclobber,imp-def,dead>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1648B	BB#19: derived from LLVM BB %return
	    Live Ins: %X19
	    Predecessors according to CFG: BB#18 BB#15 BB#9
1664B		%vreg65<def> = ADRP <ga:@BZ2_bzReadClose>[TF=1]; GPR64common:%vreg65
1680B		%vreg67<def> = ADDXri %vreg65<kill>, <ga:@BZ2_bzReadClose>[TF=34], 0; GPR64sp:%vreg67 GPR64common:%vreg65
1728B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1744B		%X0<def> = COPY %vreg67<kill>; GPR64sp:%vreg67
1760B		%X1<def> = COPY %vreg13<kill>; GPR64:%vreg13
1776B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
1792B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1808B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1824B		STACKMAP 3, 0, %LR<earlyclobber,imp-def,dead>, ...
1840B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1856B		RET_ReallyLR
> %X8<def> = ADRP <ga:@BZ2_bzReadClose>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@BZ2_bzReadClose>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19<kill>
> BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 3, 0, %LR<earlyclobber,imp-def,dead>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> RET_ReallyLR
Computing live-in reg-units in ABI blocks.
0B	BB#0 W0#0 W1#0 W2#0 W3#0 W30#0
Created 5 new intervals.
********** INTERVALS **********
W30 [0B,16r:0)[272r,272d:16)[320e,320d:8)[1920r,1920d:15)[1984e,1984d:7)[2448r,2448d:14)[2528e,2528d:6)[2784r,2784d:12)[2848e,2848d:5)[2976r,2976d:13)[3040e,3040d:4)[3648r,3648d:11)[3712e,3712d:3)[4256r,4256d:10)[4336e,4336d:2)[5696r,5696d:9)[5744e,5744d:1)  0@0B-phi 1@5744e 2@4336e 3@3712e 4@3040e 5@2848e 6@2528e 7@1984e 8@320e 9@5696r 10@4256r 11@3648r 12@2784r 13@2976r 14@2448r 15@1920r 16@272r
W0 [0B,80r:0)[240r,272r:15)[1904r,1920r:14)[1920r,1952r:6)[2432r,2448r:13)[2448r,2480r:5)[2720r,2784r:11)[2784r,2816r:10)[2960r,2976r:12)[2976r,3008r:4)[3632r,3648r:9)[3648r,3680r:3)[4240r,4256r:8)[4256r,4288r:2)[5664r,5696r:7)[5792r,5808r:1)  0@0B-phi 1@5792r 2@4256r 3@3648r 4@2976r 5@2448r 6@1920r 7@5664r 8@4240r 9@3632r 10@2784r 11@2720r 12@2960r 13@2432r 14@1904r 15@240r
W1 [0B,64r:0)[256r,272r:3)[2736r,2784r:2)[5680r,5696r:1)  0@0B-phi 1@5680r 2@2736r 3@256r
W2 [0B,48r:0)[2752r,2784r:1)  0@0B-phi 1@2752r
W3 [0B,32r:0)[2768r,2784r:1)  0@0B-phi 1@2768r
%vreg0 [80r,96r:0)  0@80r
%vreg1 [96r,352r:0)  0@96r
%vreg2 [64r,112r:0)  0@64r
%vreg3 [112r,368r:0)  0@112r
%vreg4 [48r,128r:0)  0@48r
%vreg5 [128r,384r:0)  0@128r
%vreg6 [32r,144r:0)  0@32r
%vreg7 [144r,400r:0)  0@144r
%vreg9 [464r,480r:0)  0@464r
%vreg12 [432r,448r:0)  0@432r
%vreg13 [416r,432r:0)  0@416r
%vreg14 [160r,176r:0)  0@160r
%vreg15 [176r,192r:0)  0@176r
%vreg16 [192r,240r:0)  0@192r
%vreg17 [208r,256r:0)  0@208r
%vreg18 [16r,5632r:0)  0@16r
%vreg20 [512r,528r:0)  0@512r
%vreg22 [560r,576r:0)  0@560r
%vreg24 [608r,624r:0)  0@608r
%vreg26 [656r,672r:0)  0@656r
%vreg28 [704r,720r:0)  0@704r
%vreg30 [752r,768r:0)  0@752r
%vreg32 [1136r,1152r:0)  0@1136r
%vreg34 [1088r,1104r:0)  0@1088r
%vreg35 [1104r,1120r:0)  0@1104r
%vreg36 [1120r,1136r:0)  0@1120r
%vreg37 [1072r,1104r:0)  0@1072r
%vreg39 [1456r,1472r:0)  0@1456r
%vreg42 [1808r,1824r:0)  0@1808r
%vreg43 [1792r,1824r:0)  0@1792r
%vreg46 [1760r,1776r:0)  0@1760r
%vreg47 [1744r,1776r:0)  0@1744r
%vreg50 [1952r,2016r:0)  0@1952r
%vreg52 [1872r,1904r:0)  0@1872r
%vreg53 [1856r,1872r:0)  0@1856r
%vreg56 [2336r,2352r:0)  0@2336r
%vreg57 [2320r,2336r:0)  0@2320r
%vreg58 [2496r,2560r:0)  0@2496r
%vreg59 [2560r,2576r:0)  0@2560r
%vreg61 [2480r,2496r:0)  0@2480r
%vreg63 [2400r,2432r:0)  0@2400r
%vreg64 [2384r,2400r:0)  0@2384r
%vreg67 [3008r,3072r:0)  0@3008r
%vreg69 [2928r,2960r:0)  0@2928r
%vreg70 [2912r,2928r:0)  0@2912r
%vreg73 [2880r,2896r:0)  0@2880r
%vreg75 [2608r,2736r:0)  0@2608r
%vreg76 [2624r,2752r:0)  0@2624r
%vreg78 [2816r,2880r:0)  0@2816r
%vreg80 [2688r,2768r:0)  0@2688r
%vreg81 [2672r,2688r:0)  0@2672r
%vreg84 [2656r,2720r:0)  0@2656r
%vreg85 [2640r,2656r:0)  0@2640r
%vreg88 [3520r,3536r:0)  0@3520r
%vreg91 [3504r,3536r:0)  0@3504r
%vreg92 [3488r,3504r:0)  0@3488r
%vreg95 [3456r,3472r:0)  0@3456r
%vreg97 [3440r,3472r:0)  0@3440r
%vreg98 [3424r,3440r:0)  0@3424r
%vreg101 [3392r,3408r:0)  0@3392r
%vreg102 [3376r,3408r:0)  0@3376r
%vreg104 [3104r,3120r:0)  0@3104r
%vreg105 [3152r,3184r:0)  0@3152r
%vreg107 [3168r,3184r:0)  0@3168r
%vreg109 [3216r,3232r:0)  0@3216r
%vreg110 [3264r,3296r:0)  0@3264r
%vreg112 [3280r,3296r:0)  0@3280r
%vreg114 [3760r,3776r:0)  0@3760r
%vreg117 [3680r,3744r:0)  0@3680r
%vreg119 [3584r,3600r:0)  0@3584r
%vreg120 [3600r,3632r:0)  0@3600r
%vreg121 [3568r,3600r:0)  0@3568r
%vreg123 [3808r,3824r:0)  0@3808r
%vreg125 [4144r,4160r:0)  0@4144r
%vreg127 [4304r,4368r:0)  0@4304r
%vreg128 [4368r,4384r:0)  0@4368r
%vreg130 [4288r,4304r:0)  0@4288r
%vreg132 [4208r,4240r:0)  0@4208r
%vreg133 [4192r,4208r:0)  0@4192r
%vreg136 [4432r,4448r:0)  0@4432r
%vreg137 [4416r,4432r:0)  0@4416r
%vreg140 [4496r,4512r:0)  0@4496r
%vreg141 [4480r,4496r:0)  0@4480r
%vreg143 [4832r,4848r:0)  0@4832r
%vreg146 [5248r,5264r:0)  0@5248r
%vreg147 [5232r,5248r:0)  0@5232r
%vreg149 [5296r,5312r:0)  0@5296r
%vreg151 [5344r,5360r:0)  0@5344r
%vreg153 [5392r,5408r:0)  0@5392r
%vreg155 [5440r,5456r:0)  0@5440r
%vreg157 [5488r,5504r:0)  0@5488r
%vreg159 [4896r,4912r:0)  0@4896r
%vreg160 [4944r,4976r:0)  0@4944r
%vreg162 [4960r,4976r:0)  0@4960r
%vreg164 [5008r,5024r:0)  0@5008r
%vreg165 [5056r,5088r:0)  0@5056r
%vreg167 [5072r,5088r:0)  0@5072r
%vreg171 [5168r,5184r:0)  0@5168r
%vreg173 [5152r,5168r:0)  0@5152r
%vreg174 [5136r,5152r:0)  0@5136r
%vreg175 [5120r,5168r:0)  0@5120r
%vreg177 [4560r,4576r:0)  0@4560r
%vreg178 [4608r,4640r:0)  0@4608r
%vreg180 [4624r,4640r:0)  0@4624r
%vreg182 [4672r,4688r:0)  0@4672r
%vreg183 [4720r,4752r:0)  0@4720r
%vreg185 [4736r,4752r:0)  0@4736r
%vreg187 [3872r,3888r:0)  0@3872r
%vreg190 [3936r,3952r:0)  0@3936r
%vreg191 [3920r,3952r:0)  0@3920r
%vreg193 [3984r,4000r:0)  0@3984r
%vreg196 [4048r,4064r:0)  0@4048r
%vreg197 [4032r,4064r:0)  0@4032r
%vreg199 [2048r,2064r:0)  0@2048r
%vreg200 [2096r,2128r:0)  0@2096r
%vreg202 [2112r,2128r:0)  0@2112r
%vreg204 [2160r,2176r:0)  0@2160r
%vreg205 [2208r,2240r:0)  0@2208r
%vreg207 [2224r,2240r:0)  0@2224r
%vreg209 [1504r,1520r:0)  0@1504r
%vreg211 [1552r,1568r:0)  0@1552r
%vreg213 [1600r,1616r:0)  0@1600r
%vreg215 [1648r,1664r:0)  0@1648r
%vreg217 [1184r,1200r:0)  0@1184r
%vreg218 [1232r,1264r:0)  0@1232r
%vreg220 [1248r,1264r:0)  0@1248r
%vreg222 [1296r,1312r:0)  0@1296r
%vreg223 [1344r,1376r:0)  0@1344r
%vreg225 [1360r,1376r:0)  0@1360r
%vreg227 [800r,816r:0)  0@800r
%vreg228 [848r,880r:0)  0@848r
%vreg230 [864r,880r:0)  0@864r
%vreg232 [912r,928r:0)  0@912r
%vreg233 [960r,992r:0)  0@960r
%vreg235 [976r,992r:0)  0@976r
%vreg237 [5776r,5792r:0)  0@5776r
%vreg238 [5584r,5600r:0)  0@5584r
%vreg239 [5600r,5616r:0)  0@5600r
%vreg240 [5616r,5664r:0)  0@5616r
%vreg241 [5632r,5680r:0)  0@5632r
RegMasks: 272r 1920r 2448r 2784r 2976r 3648r 4256r 5696r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzRead: Post SSA
Frame Objects:
  fi#0: size=4, align=4, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=8, align=8, at location [SP]
  fi#3: size=8, align=8, at location [SP]
  fi#4: size=4, align=4, at location [SP]
  fi#5: size=4, align=4, at location [SP]
  fi#6: size=4, align=4, at location [SP]
  fi#7: size=8, align=8, at location [SP]
Function Live Ins: %X0 in %vreg0, %X1 in %vreg2, %X2 in %vreg4, %W3 in %vreg6, %LR in %vreg18

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %X1 %X2 %W3 %LR
16B		%vreg18<def> = COPY %LR; GPR64:%vreg18
32B		%vreg6<def> = COPY %W3; GPR32:%vreg6
48B		%vreg4<def> = COPY %X2; GPR64:%vreg4
64B		%vreg2<def> = COPY %X1; GPR64:%vreg2
80B		%vreg0<def> = COPY %X0; GPR64:%vreg0
96B		%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
112B		%vreg3<def> = COPY %vreg2; GPR64:%vreg3,%vreg2
128B		%vreg5<def> = COPY %vreg4; GPR64:%vreg5,%vreg4
144B		%vreg7<def> = COPY %vreg6; GPR32:%vreg7,%vreg6
160B		%vreg14<def> = ADRP <ga:@BZ2_bzRead>[TF=1]; GPR64common:%vreg14
176B		%vreg15<def> = ADDXri %vreg14, <ga:@BZ2_bzRead>[TF=34], 0; GPR64sp:%vreg15 GPR64common:%vreg14
192B		%vreg16<def> = COPY %vreg15; GPR64all:%vreg16 GPR64sp:%vreg15
208B		%vreg17<def> = COPY %vreg18; GPR64all:%vreg17 GPR64:%vreg18
224B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
240B		%X0<def> = COPY %vreg16; GPR64all:%vreg16
256B		%X1<def> = COPY %vreg17; GPR64all:%vreg17
272B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
288B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
304B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
320B		STACKMAP 0, 0, %vreg3, 0, <fi#2>, 0, %vreg5, 0, <fi#3>, 0, %vreg1, 0, <fi#1>, 0, 0, <fi#7>, 0, %vreg7, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2] LD8[FixedStack3] LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4) GPR64:%vreg3,%vreg5,%vreg1 GPR32:%vreg7
336B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
352B		STRXui %vreg1, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg1
368B		STRXui %vreg3, <fi#2>, 0; mem:ST8[FixedStack2] GPR64:%vreg3
384B		STRXui %vreg5, <fi#3>, 0; mem:ST8[FixedStack3] GPR64:%vreg5
400B		STRWui %vreg7, <fi#4>, 0; mem:ST4[FixedStack4] GPR32:%vreg7
416B		%vreg13<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg13
432B		%vreg12<def> = COPY %vreg13; GPR64:%vreg12,%vreg13
448B		STRXui %vreg12, <fi#7>, 0; mem:ST8[FixedStack7] GPR64:%vreg12
464B		%vreg9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg9
480B		CBZX %vreg9, <BB#2>; GPR64:%vreg9
	    Successors according to CFG: BB#2 BB#1

496B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
512B		%vreg20<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg20
528B		STRWui %WZR, %vreg20, 0; mem:ST4[%3] GPR64common:%vreg20
	    Successors according to CFG: BB#2

544B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#1
560B		%vreg22<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg22
576B		CBZX %vreg22, <BB#4>; GPR64:%vreg22
	    Successors according to CFG: BB#4 BB#3

592B	BB#3: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#2
608B		%vreg24<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg24
624B		STRWui %WZR, %vreg24, 1274; mem:ST4[%lastErr] GPR64common:%vreg24
	    Successors according to CFG: BB#4

640B	BB#4: derived from LLVM BB %if.end.3
	    Predecessors according to CFG: BB#2 BB#3
656B		%vreg26<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg26
672B		CBZX %vreg26, <BB#7>; GPR64:%vreg26
	    Successors according to CFG: BB#7 BB#5

688B	BB#5: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#4
704B		%vreg28<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg28
720B		CBZX %vreg28, <BB#7>; GPR64:%vreg28
	    Successors according to CFG: BB#7 BB#6

736B	BB#6: derived from LLVM BB %lor.lhs.false.6
	    Predecessors according to CFG: BB#5
752B		%vreg30<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg30
768B		TBZW %vreg30, 31, <BB#12>; GPR32:%vreg30
	    Successors according to CFG: BB#12 BB#7

784B	BB#7: derived from LLVM BB %if.then.8
	    Predecessors according to CFG: BB#4 BB#5 BB#6
800B		%vreg227<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg227
816B		CBZX %vreg227, <BB#9>; GPR64:%vreg227
	    Successors according to CFG: BB#9 BB#8

832B	BB#8: derived from LLVM BB %if.then.10
	    Predecessors according to CFG: BB#7
848B		%vreg228<def> = MOVi32imm 4294967294; GPR32:%vreg228
864B		%vreg230<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg230
880B		STRWui %vreg228, %vreg230, 0; mem:ST4[%10] GPR32:%vreg228 GPR64common:%vreg230
	    Successors according to CFG: BB#9

896B	BB#9: derived from LLVM BB %if.end.11
	    Predecessors according to CFG: BB#7 BB#8
912B		%vreg232<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg232
928B		CBZX %vreg232, <BB#11>; GPR64:%vreg232
	    Successors according to CFG: BB#11 BB#10

944B	BB#10: derived from LLVM BB %if.then.13
	    Predecessors according to CFG: BB#9
960B		%vreg233<def> = MOVi32imm 4294967294; GPR32:%vreg233
976B		%vreg235<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg235
992B		STRWui %vreg233, %vreg235, 1274; mem:ST4[%lastErr14] GPR32:%vreg233 GPR64common:%vreg235
	    Successors according to CFG: BB#11

1008B	BB#11: derived from LLVM BB %if.end.15
	    Predecessors according to CFG: BB#9 BB#10
1024B		STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
1040B		B <BB#69>
	    Successors according to CFG: BB#69

1056B	BB#12: derived from LLVM BB %if.end.16
	    Predecessors according to CFG: BB#6
1072B		%vreg37<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg37
1088B		%vreg34<def> = MOVi64imm 5012; GPR64:%vreg34
1104B		%vreg35<def> = ADDXrr %vreg37, %vreg34; GPR64common:%vreg35 GPR64:%vreg37,%vreg34
1120B		%vreg36<def> = LDRBBui %vreg35, 0; mem:LD1[%writing] GPR32:%vreg36 GPR64common:%vreg35
1136B		%vreg32<def> = UBFMWri %vreg36, 0, 7; GPR32:%vreg32,%vreg36
1152B		CBZW %vreg32, <BB#18>; GPR32:%vreg32
	    Successors according to CFG: BB#18 BB#13

1168B	BB#13: derived from LLVM BB %if.then.17
	    Predecessors according to CFG: BB#12
1184B		%vreg217<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg217
1200B		CBZX %vreg217, <BB#15>; GPR64:%vreg217
	    Successors according to CFG: BB#15 BB#14

1216B	BB#14: derived from LLVM BB %if.then.19
	    Predecessors according to CFG: BB#13
1232B		%vreg218<def> = MOVi32imm 4294967295; GPR32:%vreg218
1248B		%vreg220<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg220
1264B		STRWui %vreg218, %vreg220, 0; mem:ST4[%16] GPR32:%vreg218 GPR64common:%vreg220
	    Successors according to CFG: BB#15

1280B	BB#15: derived from LLVM BB %if.end.20
	    Predecessors according to CFG: BB#13 BB#14
1296B		%vreg222<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg222
1312B		CBZX %vreg222, <BB#17>; GPR64:%vreg222
	    Successors according to CFG: BB#17 BB#16

1328B	BB#16: derived from LLVM BB %if.then.22
	    Predecessors according to CFG: BB#15
1344B		%vreg223<def> = MOVi32imm 4294967295; GPR32:%vreg223
1360B		%vreg225<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg225
1376B		STRWui %vreg223, %vreg225, 1274; mem:ST4[%lastErr23] GPR32:%vreg223 GPR64common:%vreg225
	    Successors according to CFG: BB#17

1392B	BB#17: derived from LLVM BB %if.end.24
	    Predecessors according to CFG: BB#15 BB#16
1408B		STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
1424B		B <BB#69>
	    Successors according to CFG: BB#69

1440B	BB#18: derived from LLVM BB %if.end.25
	    Predecessors according to CFG: BB#12
1456B		%vreg39<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg39
1472B		CBNZW %vreg39, <BB#24>; GPR32:%vreg39
	    Successors according to CFG: BB#24 BB#19

1488B	BB#19: derived from LLVM BB %if.then.27
	    Predecessors according to CFG: BB#18
1504B		%vreg209<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg209
1520B		CBZX %vreg209, <BB#21>; GPR64:%vreg209
	    Successors according to CFG: BB#21 BB#20

1536B	BB#20: derived from LLVM BB %if.then.29
	    Predecessors according to CFG: BB#19
1552B		%vreg211<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg211
1568B		STRWui %WZR, %vreg211, 0; mem:ST4[%21] GPR64common:%vreg211
	    Successors according to CFG: BB#21

1584B	BB#21: derived from LLVM BB %if.end.30
	    Predecessors according to CFG: BB#19 BB#20
1600B		%vreg213<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg213
1616B		CBZX %vreg213, <BB#23>; GPR64:%vreg213
	    Successors according to CFG: BB#23 BB#22

1632B	BB#22: derived from LLVM BB %if.then.32
	    Predecessors according to CFG: BB#21
1648B		%vreg215<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg215
1664B		STRWui %WZR, %vreg215, 1274; mem:ST4[%lastErr33] GPR64common:%vreg215
	    Successors according to CFG: BB#23

1680B	BB#23: derived from LLVM BB %if.end.34
	    Predecessors according to CFG: BB#21 BB#22
1696B		STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
1712B		B <BB#69>
	    Successors according to CFG: BB#69

1728B	BB#24: derived from LLVM BB %if.end.35
	    Predecessors according to CFG: BB#18
1744B		%vreg47<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg47
1760B		%vreg46<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg46
1776B		STRWui %vreg47, %vreg46, 1262; mem:ST4[%avail_out] GPR32:%vreg47 GPR64common:%vreg46
1792B		%vreg43<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg43
1808B		%vreg42<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg42
1824B		STRXui %vreg43, %vreg42, 630; mem:ST8[%next_out] GPR64:%vreg43 GPR64common:%vreg42
	    Successors according to CFG: BB#25

1840B	BB#25: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#24 BB#68
1856B		%vreg53<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg53
1872B		%vreg52<def> = LDRXui %vreg53, 0; mem:LD8[%handle] GPR64:%vreg52 GPR64common:%vreg53
1888B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1904B		%X0<def> = COPY %vreg52; GPR64:%vreg52
1920B		BL <ga:@ferror>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
1936B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1952B		%vreg50<def> = COPY %W0; GPR32:%vreg50
1968B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1984B		STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
2000B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2016B		CBZW %vreg50, <BB#31>; GPR32:%vreg50
	    Successors according to CFG: BB#31 BB#26

2032B	BB#26: derived from LLVM BB %if.then.38
	    Predecessors according to CFG: BB#25
2048B		%vreg199<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg199
2064B		CBZX %vreg199, <BB#28>; GPR64:%vreg199
	    Successors according to CFG: BB#28 BB#27

2080B	BB#27: derived from LLVM BB %if.then.40
	    Predecessors according to CFG: BB#26
2096B		%vreg200<def> = MOVi32imm 4294967290; GPR32:%vreg200
2112B		%vreg202<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg202
2128B		STRWui %vreg200, %vreg202, 0; mem:ST4[%31] GPR32:%vreg200 GPR64common:%vreg202
	    Successors according to CFG: BB#28

2144B	BB#28: derived from LLVM BB %if.end.41
	    Predecessors according to CFG: BB#26 BB#27
2160B		%vreg204<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg204
2176B		CBZX %vreg204, <BB#30>; GPR64:%vreg204
	    Successors according to CFG: BB#30 BB#29

2192B	BB#29: derived from LLVM BB %if.then.43
	    Predecessors according to CFG: BB#28
2208B		%vreg205<def> = MOVi32imm 4294967290; GPR32:%vreg205
2224B		%vreg207<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg207
2240B		STRWui %vreg205, %vreg207, 1274; mem:ST4[%lastErr44] GPR32:%vreg205 GPR64common:%vreg207
	    Successors according to CFG: BB#30

2256B	BB#30: derived from LLVM BB %if.end.45
	    Predecessors according to CFG: BB#28 BB#29
2272B		STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
2288B		B <BB#69>
	    Successors according to CFG: BB#69

2304B	BB#31: derived from LLVM BB %if.end.46
	    Predecessors according to CFG: BB#25
2320B		%vreg57<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg57
2336B		%vreg56<def> = LDRWui %vreg57, 1256; mem:LD4[%avail_in] GPR32:%vreg56 GPR64common:%vreg57
2352B		CBNZW %vreg56, <BB#40>; GPR32:%vreg56
	    Successors according to CFG: BB#40 BB#32

2368B	BB#32: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#31
2384B		%vreg64<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg64
2400B		%vreg63<def> = LDRXui %vreg64, 0; mem:LD8[%handle49] GPR64:%vreg63 GPR64common:%vreg64
2416B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2432B		%X0<def> = COPY %vreg63; GPR64:%vreg63
2448B		BL <ga:@myfeof>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>
2464B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2480B		%vreg61<def> = COPY %W0; GPR32:%vreg61
2496B		%vreg58<def> = COPY %vreg61; GPR32:%vreg58,%vreg61
2512B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2528B		STACKMAP 2, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
2544B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2560B		%vreg59<def> = UBFMWri %vreg58, 0, 7; GPR32:%vreg59,%vreg58
2576B		CBNZW %vreg59, <BB#40>; GPR32:%vreg59
	    Successors according to CFG: BB#40 BB#33

2592B	BB#33: derived from LLVM BB %if.then.52
	    Predecessors according to CFG: BB#32
2608B		%vreg75<def> = MOVi64imm 1; GPR64:%vreg75
2624B		%vreg76<def> = MOVi64imm 5000; GPR64:%vreg76
2640B		%vreg85<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg85
2656B		%vreg84<def> = ADDXri %vreg85, 8, 0; GPR64sp:%vreg84 GPR64common:%vreg85
2672B		%vreg81<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg81
2688B		%vreg80<def> = LDRXui %vreg81, 0; mem:LD8[%handle54] GPR64:%vreg80 GPR64common:%vreg81
2704B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2720B		%X0<def> = COPY %vreg84; GPR64sp:%vreg84
2736B		%X1<def> = COPY %vreg75; GPR64:%vreg75
2752B		%X2<def> = COPY %vreg76; GPR64:%vreg76
2768B		%X3<def> = COPY %vreg80; GPR64:%vreg80
2784B		BL <ga:@fread>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %X2<imp-use>, %X3<imp-use>, %X0<imp-def>
2800B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2816B		%vreg78<def> = COPY %X0; GPR64all:%vreg78
2832B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2848B		STACKMAP 3, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
2864B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2880B		%vreg73<def> = COPY %vreg78:sub_32; GPR32:%vreg73 GPR64all:%vreg78
2896B		STRWui %vreg73, <fi#5>, 0; mem:ST4[FixedStack5] GPR32:%vreg73
2912B		%vreg70<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg70
2928B		%vreg69<def> = LDRXui %vreg70, 0; mem:LD8[%handle56] GPR64:%vreg69 GPR64common:%vreg70
2944B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2960B		%X0<def> = COPY %vreg69; GPR64:%vreg69
2976B		BL <ga:@ferror>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
2992B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3008B		%vreg67<def> = COPY %W0; GPR32:%vreg67
3024B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3040B		STACKMAP 4, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
3056B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3072B		CBZW %vreg67, <BB#39>; GPR32:%vreg67
	    Successors according to CFG: BB#39 BB#34

3088B	BB#34: derived from LLVM BB %if.then.59
	    Predecessors according to CFG: BB#33
3104B		%vreg104<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg104
3120B		CBZX %vreg104, <BB#36>; GPR64:%vreg104
	    Successors according to CFG: BB#36 BB#35

3136B	BB#35: derived from LLVM BB %if.then.62
	    Predecessors according to CFG: BB#34
3152B		%vreg105<def> = MOVi32imm 4294967290; GPR32:%vreg105
3168B		%vreg107<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg107
3184B		STRWui %vreg105, %vreg107, 0; mem:ST4[%44] GPR32:%vreg105 GPR64common:%vreg107
	    Successors according to CFG: BB#36

3200B	BB#36: derived from LLVM BB %if.end.63
	    Predecessors according to CFG: BB#34 BB#35
3216B		%vreg109<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg109
3232B		CBZX %vreg109, <BB#38>; GPR64:%vreg109
	    Successors according to CFG: BB#38 BB#37

3248B	BB#37: derived from LLVM BB %if.then.66
	    Predecessors according to CFG: BB#36
3264B		%vreg110<def> = MOVi32imm 4294967290; GPR32:%vreg110
3280B		%vreg112<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg112
3296B		STRWui %vreg110, %vreg112, 1274; mem:ST4[%lastErr67] GPR32:%vreg110 GPR64common:%vreg112
	    Successors according to CFG: BB#38

3312B	BB#38: derived from LLVM BB %if.end.68
	    Predecessors according to CFG: BB#36 BB#37
3328B		STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
3344B		B <BB#69>
	    Successors according to CFG: BB#69

3360B	BB#39: derived from LLVM BB %if.end.69
	    Predecessors according to CFG: BB#33
3376B		%vreg102<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32:%vreg102
3392B		%vreg101<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg101
3408B		STRWui %vreg102, %vreg101, 1252; mem:ST4[%bufN] GPR32:%vreg102 GPR64common:%vreg101
3424B		%vreg98<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg98
3440B		%vreg97<def> = LDRWui %vreg98, 1252; mem:LD4[%bufN70] GPR32:%vreg97 GPR64common:%vreg98
3456B		%vreg95<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg95
3472B		STRWui %vreg97, %vreg95, 1256; mem:ST4[%avail_in72] GPR32:%vreg97 GPR64common:%vreg95
3488B		%vreg92<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg92
3504B		%vreg91<def> = ADDXri %vreg92, 8, 0; GPR64common:%vreg91,%vreg92
3520B		%vreg88<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg88
3536B		STRXui %vreg91, %vreg88, 627; mem:ST8[%next_in] GPR64common:%vreg91,%vreg88
	    Successors according to CFG: BB#40

3552B	BB#40: derived from LLVM BB %if.end.76
	    Predecessors according to CFG: BB#31 BB#32 BB#39
3568B		%vreg121<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg121
3584B		%vreg119<def> = MOVi64imm 5016; GPR64:%vreg119
3600B		%vreg120<def> = ADDXrr %vreg121, %vreg119; GPR64:%vreg120,%vreg121,%vreg119
3616B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3632B		%X0<def> = COPY %vreg120; GPR64:%vreg120
3648B		BL <ga:@BZ2_bzDecompress>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
3664B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3680B		%vreg117<def> = COPY %W0; GPR32:%vreg117
3696B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3712B		STACKMAP 5, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
3728B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3744B		STRWui %vreg117, <fi#6>, 0; mem:ST4[FixedStack6] GPR32:%vreg117
3760B		%vreg114<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg114
3776B		CBZW %vreg114, <BB#47>; GPR32:%vreg114
	    Successors according to CFG: BB#47 BB#41

3792B	BB#41: derived from LLVM BB %land.lhs.true.81
	    Predecessors according to CFG: BB#40
3808B		%vreg123<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32common:%vreg123
3824B		%WZR<def> = SUBSWri %vreg123, 4, 0, %NZCV<imp-def>; GPR32common:%vreg123
3840B		Bcc 0, <BB#47>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#47 BB#42

3856B	BB#42: derived from LLVM BB %if.then.84
	    Predecessors according to CFG: BB#41
3872B		%vreg187<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg187
3888B		CBZX %vreg187, <BB#44>; GPR64:%vreg187
	    Successors according to CFG: BB#44 BB#43

3904B	BB#43: derived from LLVM BB %if.then.87
	    Predecessors according to CFG: BB#42
3920B		%vreg191<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg191
3936B		%vreg190<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg190
3952B		STRWui %vreg191, %vreg190, 0; mem:ST4[%59] GPR32:%vreg191 GPR64common:%vreg190
	    Successors according to CFG: BB#44

3968B	BB#44: derived from LLVM BB %if.end.88
	    Predecessors according to CFG: BB#42 BB#43
3984B		%vreg193<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg193
4000B		CBZX %vreg193, <BB#46>; GPR64:%vreg193
	    Successors according to CFG: BB#46 BB#45

4016B	BB#45: derived from LLVM BB %if.then.91
	    Predecessors according to CFG: BB#44
4032B		%vreg197<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg197
4048B		%vreg196<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg196
4064B		STRWui %vreg197, %vreg196, 1274; mem:ST4[%lastErr92] GPR32:%vreg197 GPR64common:%vreg196
	    Successors according to CFG: BB#46

4080B	BB#46: derived from LLVM BB %if.end.93
	    Predecessors according to CFG: BB#44 BB#45
4096B		STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
4112B		B <BB#69>
	    Successors according to CFG: BB#69

4128B	BB#47: derived from LLVM BB %if.end.94
	    Predecessors according to CFG: BB#40 BB#41
4144B		%vreg125<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg125
4160B		CBNZW %vreg125, <BB#56>; GPR32:%vreg125
	    Successors according to CFG: BB#56 BB#48

4176B	BB#48: derived from LLVM BB %land.lhs.true.97
	    Predecessors according to CFG: BB#47
4192B		%vreg133<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg133
4208B		%vreg132<def> = LDRXui %vreg133, 0; mem:LD8[%handle98] GPR64:%vreg132 GPR64common:%vreg133
4224B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4240B		%X0<def> = COPY %vreg132; GPR64:%vreg132
4256B		BL <ga:@myfeof>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>
4272B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4288B		%vreg130<def> = COPY %W0; GPR32:%vreg130
4304B		%vreg127<def> = COPY %vreg130; GPR32:%vreg127,%vreg130
4320B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4336B		STACKMAP 6, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
4352B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4368B		%vreg128<def> = UBFMWri %vreg127, 0, 7; GPR32:%vreg128,%vreg127
4384B		CBZW %vreg128, <BB#56>; GPR32:%vreg128
	    Successors according to CFG: BB#56 BB#49

4400B	BB#49: derived from LLVM BB %land.lhs.true.102
	    Predecessors according to CFG: BB#48
4416B		%vreg137<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg137
4432B		%vreg136<def> = LDRWui %vreg137, 1256; mem:LD4[%avail_in104] GPR32:%vreg136 GPR64common:%vreg137
4448B		CBNZW %vreg136, <BB#56>; GPR32:%vreg136
	    Successors according to CFG: BB#56 BB#50

4464B	BB#50: derived from LLVM BB %land.lhs.true.107
	    Predecessors according to CFG: BB#49
4480B		%vreg141<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg141
4496B		%vreg140<def> = LDRWui %vreg141, 1262; mem:LD4[%avail_out109] GPR32common:%vreg140 GPR64common:%vreg141
4512B		%WZR<def> = SUBSWri %vreg140, 0, 0, %NZCV<imp-def>; GPR32common:%vreg140
4528B		Bcc 9, <BB#56>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#56 BB#51

4544B	BB#51: derived from LLVM BB %if.then.112
	    Predecessors according to CFG: BB#50
4560B		%vreg177<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg177
4576B		CBZX %vreg177, <BB#53>; GPR64:%vreg177
	    Successors according to CFG: BB#53 BB#52

4592B	BB#52: derived from LLVM BB %if.then.115
	    Predecessors according to CFG: BB#51
4608B		%vreg178<def> = MOVi32imm 4294967289; GPR32:%vreg178
4624B		%vreg180<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg180
4640B		STRWui %vreg178, %vreg180, 0; mem:ST4[%71] GPR32:%vreg178 GPR64common:%vreg180
	    Successors according to CFG: BB#53

4656B	BB#53: derived from LLVM BB %if.end.116
	    Predecessors according to CFG: BB#51 BB#52
4672B		%vreg182<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg182
4688B		CBZX %vreg182, <BB#55>; GPR64:%vreg182
	    Successors according to CFG: BB#55 BB#54

4704B	BB#54: derived from LLVM BB %if.then.119
	    Predecessors according to CFG: BB#53
4720B		%vreg183<def> = MOVi32imm 4294967289; GPR32:%vreg183
4736B		%vreg185<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg185
4752B		STRWui %vreg183, %vreg185, 1274; mem:ST4[%lastErr120] GPR32:%vreg183 GPR64common:%vreg185
	    Successors according to CFG: BB#55

4768B	BB#55: derived from LLVM BB %if.end.121
	    Predecessors according to CFG: BB#53 BB#54
4784B		STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
4800B		B <BB#69>
	    Successors according to CFG: BB#69

4816B	BB#56: derived from LLVM BB %if.end.122
	    Predecessors according to CFG: BB#47 BB#48 BB#49 BB#50
4832B		%vreg143<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32common:%vreg143
4848B		%WZR<def> = SUBSWri %vreg143, 4, 0, %NZCV<imp-def>; GPR32common:%vreg143
4864B		Bcc 1, <BB#62>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#62 BB#57

4880B	BB#57: derived from LLVM BB %if.then.125
	    Predecessors according to CFG: BB#56
4896B		%vreg159<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg159
4912B		CBZX %vreg159, <BB#59>; GPR64:%vreg159
	    Successors according to CFG: BB#59 BB#58

4928B	BB#58: derived from LLVM BB %if.then.128
	    Predecessors according to CFG: BB#57
4944B		%vreg160<def> = MOVi32imm 4; GPR32:%vreg160
4960B		%vreg162<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg162
4976B		STRWui %vreg160, %vreg162, 0; mem:ST4[%76] GPR32:%vreg160 GPR64common:%vreg162
	    Successors according to CFG: BB#59

4992B	BB#59: derived from LLVM BB %if.end.129
	    Predecessors according to CFG: BB#57 BB#58
5008B		%vreg164<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg164
5024B		CBZX %vreg164, <BB#61>; GPR64:%vreg164
	    Successors according to CFG: BB#61 BB#60

5040B	BB#60: derived from LLVM BB %if.then.132
	    Predecessors according to CFG: BB#59
5056B		%vreg165<def> = MOVi32imm 4; GPR32:%vreg165
5072B		%vreg167<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg167
5088B		STRWui %vreg165, %vreg167, 1274; mem:ST4[%lastErr133] GPR32:%vreg165 GPR64common:%vreg167
	    Successors according to CFG: BB#61

5104B	BB#61: derived from LLVM BB %if.end.134
	    Predecessors according to CFG: BB#59 BB#60
5120B		%vreg175<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg175
5136B		%vreg174<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg174
5152B		%vreg173<def> = LDRWui %vreg174, 1262; mem:LD4[%avail_out136] GPR32:%vreg173 GPR64common:%vreg174
5168B		%vreg171<def> = SUBWrr %vreg175, %vreg173; GPR32:%vreg171,%vreg175,%vreg173
5184B		STRWui %vreg171, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg171
5200B		B <BB#69>
	    Successors according to CFG: BB#69

5216B	BB#62: derived from LLVM BB %if.end.137
	    Predecessors according to CFG: BB#56
5232B		%vreg147<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg147
5248B		%vreg146<def> = LDRWui %vreg147, 1262; mem:LD4[%avail_out139] GPR32:%vreg146 GPR64common:%vreg147
5264B		CBNZW %vreg146, <BB#68>; GPR32:%vreg146
	    Successors according to CFG: BB#68 BB#63

5280B	BB#63: derived from LLVM BB %if.then.142
	    Predecessors according to CFG: BB#62
5296B		%vreg149<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg149
5312B		CBZX %vreg149, <BB#65>; GPR64:%vreg149
	    Successors according to CFG: BB#65 BB#64

5328B	BB#64: derived from LLVM BB %if.then.145
	    Predecessors according to CFG: BB#63
5344B		%vreg151<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg151
5360B		STRWui %WZR, %vreg151, 0; mem:ST4[%85] GPR64common:%vreg151
	    Successors according to CFG: BB#65

5376B	BB#65: derived from LLVM BB %if.end.146
	    Predecessors according to CFG: BB#63 BB#64
5392B		%vreg153<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg153
5408B		CBZX %vreg153, <BB#67>; GPR64:%vreg153
	    Successors according to CFG: BB#67 BB#66

5424B	BB#66: derived from LLVM BB %if.then.149
	    Predecessors according to CFG: BB#65
5440B		%vreg155<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg155
5456B		STRWui %WZR, %vreg155, 1274; mem:ST4[%lastErr150] GPR64common:%vreg155
	    Successors according to CFG: BB#67

5472B	BB#67: derived from LLVM BB %if.end.151
	    Predecessors according to CFG: BB#65 BB#66
5488B		%vreg157<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg157
5504B		STRWui %vreg157, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg157
5520B		B <BB#69>
	    Successors according to CFG: BB#69

5536B	BB#68: derived from LLVM BB %if.end.152
	    Predecessors according to CFG: BB#62
5552B		B <BB#25>
	    Successors according to CFG: BB#25

5568B	BB#69: derived from LLVM BB %return
	    Predecessors according to CFG: BB#38 BB#67 BB#61 BB#55 BB#46 BB#30 BB#23 BB#17 BB#11
5584B		%vreg238<def> = ADRP <ga:@BZ2_bzRead>[TF=1]; GPR64common:%vreg238
5600B		%vreg239<def> = ADDXri %vreg238, <ga:@BZ2_bzRead>[TF=34], 0; GPR64sp:%vreg239 GPR64common:%vreg238
5616B		%vreg240<def> = COPY %vreg239; GPR64all:%vreg240 GPR64sp:%vreg239
5632B		%vreg241<def> = COPY %vreg18; GPR64all:%vreg241 GPR64:%vreg18
5648B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5664B		%X0<def> = COPY %vreg240; GPR64all:%vreg240
5680B		%X1<def> = COPY %vreg241; GPR64all:%vreg241
5696B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
5712B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5728B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5744B		STACKMAP 7, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
5760B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5776B		%vreg237<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0] GPR32:%vreg237
5792B		%W0<def> = COPY %vreg237; GPR32:%vreg237
5808B		RET_ReallyLR %W0<imp-use>

# End machine code for function BZ2_bzRead.

********** SIMPLE REGISTER COALESCING **********
********** Function: BZ2_bzRead
********** JOINING INTERVALS ***********
if.end.122:
if.end.76:
3632B	%X0<def> = COPY %vreg120; GPR64:%vreg120
	Considering merging %vreg120 with %X0
	Can only merge into reserved registers.
3680B	%vreg117<def> = COPY %W0; GPR32:%vreg117
	Considering merging %vreg117 with %W0
	Can only merge into reserved registers.
while.body:
1904B	%X0<def> = COPY %vreg52; GPR64:%vreg52
	Considering merging %vreg52 with %X0
	Can only merge into reserved registers.
1952B	%vreg50<def> = COPY %W0; GPR32:%vreg50
	Considering merging %vreg50 with %W0
	Can only merge into reserved registers.
if.end.94:
if.end.46:
land.lhs.true:
2432B	%X0<def> = COPY %vreg63; GPR64:%vreg63
	Considering merging %vreg63 with %X0
	Can only merge into reserved registers.
2480B	%vreg61<def> = COPY %W0; GPR32:%vreg61
	Considering merging %vreg61 with %W0
	Can only merge into reserved registers.
if.then.52:
2720B	%X0<def> = COPY %vreg84; GPR64sp:%vreg84
	Considering merging %vreg84 with %X0
	Can only merge into reserved registers.
2736B	%X1<def> = COPY %vreg75; GPR64:%vreg75
	Considering merging %vreg75 with %X1
	Can only merge into reserved registers.
Remat: %X1<def> = MOVi64imm 1
Shrink: %vreg75 [2608r,2736r:0)  0@2608r
All defs dead: 2608r	%vreg75<def,dead> = MOVi64imm 1; GPR64:%vreg75
Shrunk: %vreg75 [2608r,2608d:0)  0@2608r
Deleting dead def 2608r	%vreg75<def,dead> = MOVi64imm 1; GPR64:%vreg75
2752B	%X2<def> = COPY %vreg76; GPR64:%vreg76
	Considering merging %vreg76 with %X2
	Can only merge into reserved registers.
Remat: %X2<def> = MOVi64imm 5000
Shrink: %vreg76 [2624r,2752r:0)  0@2624r
All defs dead: 2624r	%vreg76<def,dead> = MOVi64imm 5000; GPR64:%vreg76
Shrunk: %vreg76 [2624r,2624d:0)  0@2624r
Deleting dead def 2624r	%vreg76<def,dead> = MOVi64imm 5000; GPR64:%vreg76
2768B	%X3<def> = COPY %vreg80; GPR64:%vreg80
	Considering merging %vreg80 with %X3
	Can only merge into reserved registers.
2816B	%vreg78<def> = COPY %X0; GPR64all:%vreg78
	Considering merging %vreg78 with %X0
	Can only merge into reserved registers.
2960B	%X0<def> = COPY %vreg69; GPR64:%vreg69
	Considering merging %vreg69 with %X0
	Can only merge into reserved registers.
3008B	%vreg67<def> = COPY %W0; GPR32:%vreg67
	Considering merging %vreg67 with %W0
	Can only merge into reserved registers.
land.lhs.true.81:
land.lhs.true.97:
4240B	%X0<def> = COPY %vreg132; GPR64:%vreg132
	Considering merging %vreg132 with %X0
	Can only merge into reserved registers.
4288B	%vreg130<def> = COPY %W0; GPR32:%vreg130
	Considering merging %vreg130 with %W0
	Can only merge into reserved registers.
land.lhs.true.102:
land.lhs.true.107:
if.end.137:
if.end.69:
if.end.152:
2496B	%vreg58<def> = COPY %vreg61; GPR32:%vreg58,%vreg61
	Considering merging to GPR32 with %vreg61 in %vreg58
		RHS = %vreg61 [2480r,2496r:0)  0@2480r
		LHS = %vreg58 [2496r,2560r:0)  0@2496r
		merge %vreg58:0@2496r into %vreg61:0@2480r --> @2480r
		erased:	2496r	%vreg58<def> = COPY %vreg61; GPR32:%vreg58,%vreg61
		updated: 2480B	%vreg58<def> = COPY %W0; GPR32:%vreg58
	Success: %vreg61 -> %vreg58
	Result = %vreg58 [2480r,2560r:0)  0@2480r
2880B	%vreg73<def> = COPY %vreg78:sub_32; GPR32:%vreg73 GPR64all:%vreg78
	Considering merging to GPR64 with %vreg73 in %vreg78:sub_32
		RHS = %vreg73 [2880r,2896r:0)  0@2880r
		LHS = %vreg78 [2816r,2880r:0)  0@2816r
		merge %vreg73:0@2880r into %vreg78:0@2816r --> @2816r
		erased:	2880r	%vreg73<def> = COPY %vreg78:sub_32; GPR32:%vreg73 GPR64all:%vreg78
		updated: 2896B	STRWui %vreg78:sub_32, <fi#5>, 0; mem:ST4[FixedStack5] GPR64:%vreg78
	Success: %vreg73:sub_32 -> %vreg78
	Result = %vreg78 [2816r,2896r:0)  0@2816r
4304B	%vreg127<def> = COPY %vreg130; GPR32:%vreg127,%vreg130
	Considering merging to GPR32 with %vreg130 in %vreg127
		RHS = %vreg130 [4288r,4304r:0)  0@4288r
		LHS = %vreg127 [4304r,4368r:0)  0@4304r
		merge %vreg127:0@4304r into %vreg130:0@4288r --> @4288r
		erased:	4304r	%vreg127<def> = COPY %vreg130; GPR32:%vreg127,%vreg130
		updated: 4288B	%vreg127<def> = COPY %W0; GPR32:%vreg127
	Success: %vreg130 -> %vreg127
	Result = %vreg127 [4288r,4368r:0)  0@4288r
return:
5664B	%X0<def> = COPY %vreg240; GPR64all:%vreg240
	Considering merging %vreg240 with %X0
	Can only merge into reserved registers.
5680B	%X1<def> = COPY %vreg241; GPR64all:%vreg241
	Considering merging %vreg241 with %X1
	Can only merge into reserved registers.
5792B	%W0<def> = COPY %vreg237; GPR32:%vreg237
	Considering merging %vreg237 with %W0
	Can only merge into reserved registers.
if.then.8:
if.end:
if.end.3:
if.end.11:
if.end.20:
if.end.30:
if.end.41:
if.end.63:
if.end.88:
if.end.116:
if.end.129:
if.end.146:
lor.lhs.false:
lor.lhs.false.6:
if.end.15:
if.end.16:
if.then.17:
if.end.24:
if.end.25:
if.then.27:
if.end.34:
if.then.38:
if.end.45:
if.then.59:
if.end.68:
if.then.84:
if.end.93:
if.then.112:
if.end.121:
if.then.125:
if.end.134:
if.then.142:
if.end.151:
entry:
16B	%vreg18<def> = COPY %LR; GPR64:%vreg18
	Considering merging %vreg18 with %LR
	Can only merge into reserved registers.
32B	%vreg6<def> = COPY %W3; GPR32:%vreg6
	Considering merging %vreg6 with %W3
	Can only merge into reserved registers.
48B	%vreg4<def> = COPY %X2; GPR64:%vreg4
	Considering merging %vreg4 with %X2
	Can only merge into reserved registers.
64B	%vreg2<def> = COPY %X1; GPR64:%vreg2
	Considering merging %vreg2 with %X1
	Can only merge into reserved registers.
80B	%vreg0<def> = COPY %X0; GPR64:%vreg0
	Considering merging %vreg0 with %X0
	Can only merge into reserved registers.
240B	%X0<def> = COPY %vreg16; GPR64all:%vreg16
	Considering merging %vreg16 with %X0
	Can only merge into reserved registers.
256B	%X1<def> = COPY %vreg17; GPR64all:%vreg17
	Considering merging %vreg17 with %X1
	Can only merge into reserved registers.
if.then:
if.then.2:
if.then.10:
if.then.13:
if.then.19:
if.then.22:
if.then.29:
if.then.32:
if.end.35:
if.then.40:
if.then.43:
if.then.62:
if.then.66:
if.then.87:
if.then.91:
if.then.115:
if.then.119:
if.then.128:
if.then.132:
if.then.145:
if.then.149:
5616B	%vreg240<def> = COPY %vreg239; GPR64all:%vreg240 GPR64sp:%vreg239
	Considering merging to GPR64sp with %vreg239 in %vreg240
		RHS = %vreg239 [5600r,5616r:0)  0@5600r
		LHS = %vreg240 [5616r,5664r:0)  0@5616r
		merge %vreg240:0@5616r into %vreg239:0@5600r --> @5600r
		erased:	5616r	%vreg240<def> = COPY %vreg239; GPR64all:%vreg240 GPR64sp:%vreg239
		updated: 5600B	%vreg240<def> = ADDXri %vreg238, <ga:@BZ2_bzRead>[TF=34], 0; GPR64sp:%vreg240 GPR64common:%vreg238
	Success: %vreg239 -> %vreg240
	Result = %vreg240 [5600r,5664r:0)  0@5600r
5632B	%vreg241<def> = COPY %vreg18; GPR64all:%vreg241 GPR64:%vreg18
	Considering merging to GPR64 with %vreg18 in %vreg241
		RHS = %vreg18 [16r,5632r:0)  0@16r
		LHS = %vreg241 [5632r,5680r:0)  0@5632r
		merge %vreg241:0@5632r into %vreg18:0@16r --> @16r
		erased:	5632r	%vreg241<def> = COPY %vreg18; GPR64all:%vreg241 GPR64:%vreg18
		updated: 16B	%vreg241<def> = COPY %LR; GPR64:%vreg241
		updated: 208B	%vreg17<def> = COPY %vreg241; GPR64all:%vreg17 GPR64:%vreg241
	Success: %vreg18 -> %vreg241
	Result = %vreg241 [16r,5680r:0)  0@16r
96B	%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
	Considering merging to GPR64 with %vreg0 in %vreg1
		RHS = %vreg0 [80r,96r:0)  0@80r
		LHS = %vreg1 [96r,352r:0)  0@96r
		merge %vreg1:0@96r into %vreg0:0@80r --> @80r
		erased:	96r	%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
		updated: 80B	%vreg1<def> = COPY %X0; GPR64:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [80r,352r:0)  0@80r
112B	%vreg3<def> = COPY %vreg2; GPR64:%vreg3,%vreg2
	Considering merging to GPR64 with %vreg2 in %vreg3
		RHS = %vreg2 [64r,112r:0)  0@64r
		LHS = %vreg3 [112r,368r:0)  0@112r
		merge %vreg3:0@112r into %vreg2:0@64r --> @64r
		erased:	112r	%vreg3<def> = COPY %vreg2; GPR64:%vreg3,%vreg2
		updated: 64B	%vreg3<def> = COPY %X1; GPR64:%vreg3
	Success: %vreg2 -> %vreg3
	Result = %vreg3 [64r,368r:0)  0@64r
128B	%vreg5<def> = COPY %vreg4; GPR64:%vreg5,%vreg4
	Considering merging to GPR64 with %vreg4 in %vreg5
		RHS = %vreg4 [48r,128r:0)  0@48r
		LHS = %vreg5 [128r,384r:0)  0@128r
		merge %vreg5:0@128r into %vreg4:0@48r --> @48r
		erased:	128r	%vreg5<def> = COPY %vreg4; GPR64:%vreg5,%vreg4
		updated: 48B	%vreg5<def> = COPY %X2; GPR64:%vreg5
	Success: %vreg4 -> %vreg5
	Result = %vreg5 [48r,384r:0)  0@48r
144B	%vreg7<def> = COPY %vreg6; GPR32:%vreg7,%vreg6
	Considering merging to GPR32 with %vreg6 in %vreg7
		RHS = %vreg6 [32r,144r:0)  0@32r
		LHS = %vreg7 [144r,400r:0)  0@144r
		merge %vreg7:0@144r into %vreg6:0@32r --> @32r
		erased:	144r	%vreg7<def> = COPY %vreg6; GPR32:%vreg7,%vreg6
		updated: 32B	%vreg7<def> = COPY %W3; GPR32:%vreg7
	Success: %vreg6 -> %vreg7
	Result = %vreg7 [32r,400r:0)  0@32r
192B	%vreg16<def> = COPY %vreg15; GPR64all:%vreg16 GPR64sp:%vreg15
	Considering merging to GPR64sp with %vreg15 in %vreg16
		RHS = %vreg15 [176r,192r:0)  0@176r
		LHS = %vreg16 [192r,240r:0)  0@192r
		merge %vreg16:0@192r into %vreg15:0@176r --> @176r
		erased:	192r	%vreg16<def> = COPY %vreg15; GPR64all:%vreg16 GPR64sp:%vreg15
		updated: 176B	%vreg16<def> = ADDXri %vreg14, <ga:@BZ2_bzRead>[TF=34], 0; GPR64sp:%vreg16 GPR64common:%vreg14
	Success: %vreg15 -> %vreg16
	Result = %vreg16 [176r,240r:0)  0@176r
208B	%vreg17<def> = COPY %vreg241; GPR64all:%vreg17 GPR64:%vreg241
	Considering merging to GPR64 with %vreg241 in %vreg17
		RHS = %vreg241 [16r,5680r:0)  0@16r
		LHS = %vreg17 [208r,256r:0)  0@208r
		merge %vreg17:0@208r into %vreg241:0@16r --> @16r
		erased:	208r	%vreg17<def> = COPY %vreg241; GPR64all:%vreg17 GPR64:%vreg241
		updated: 16B	%vreg17<def> = COPY %LR; GPR64:%vreg17
		updated: 5680B	%X1<def> = COPY %vreg17; GPR64:%vreg17
	Success: %vreg241 -> %vreg17
	Result = %vreg17 [16r,5680r:0)  0@16r
432B	%vreg12<def> = COPY %vreg13; GPR64:%vreg12,%vreg13
	Considering merging to GPR64 with %vreg13 in %vreg12
		RHS = %vreg13 [416r,432r:0)  0@416r
		LHS = %vreg12 [432r,448r:0)  0@432r
		merge %vreg12:0@432r into %vreg13:0@416r --> @416r
		erased:	432r	%vreg12<def> = COPY %vreg13; GPR64:%vreg12,%vreg13
		updated: 416B	%vreg12<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg12
	Success: %vreg13 -> %vreg12
	Result = %vreg12 [416r,448r:0)  0@416r
5664B	%X0<def> = COPY %vreg240; GPR64sp:%vreg240
	Considering merging %vreg240 with %X0
	Can only merge into reserved registers.
5680B	%X1<def> = COPY %vreg17; GPR64:%vreg17
	Considering merging %vreg17 with %X1
	Can only merge into reserved registers.
240B	%X0<def> = COPY %vreg16; GPR64sp:%vreg16
	Considering merging %vreg16 with %X0
	Can only merge into reserved registers.
256B	%X1<def> = COPY %vreg17; GPR64:%vreg17
	Considering merging %vreg17 with %X1
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
W30 [0B,16r:0)[272r,272d:16)[320e,320d:8)[1920r,1920d:15)[1984e,1984d:7)[2448r,2448d:14)[2528e,2528d:6)[2784r,2784d:12)[2848e,2848d:5)[2976r,2976d:13)[3040e,3040d:4)[3648r,3648d:11)[3712e,3712d:3)[4256r,4256d:10)[4336e,4336d:2)[5696r,5696d:9)[5744e,5744d:1)  0@0B-phi 1@5744e 2@4336e 3@3712e 4@3040e 5@2848e 6@2528e 7@1984e 8@320e 9@5696r 10@4256r 11@3648r 12@2784r 13@2976r 14@2448r 15@1920r 16@272r
W0 [0B,80r:0)[240r,272r:15)[1904r,1920r:14)[1920r,1952r:6)[2432r,2448r:13)[2448r,2480r:5)[2720r,2784r:11)[2784r,2816r:10)[2960r,2976r:12)[2976r,3008r:4)[3632r,3648r:9)[3648r,3680r:3)[4240r,4256r:8)[4256r,4288r:2)[5664r,5696r:7)[5792r,5808r:1)  0@0B-phi 1@5792r 2@4256r 3@3648r 4@2976r 5@2448r 6@1920r 7@5664r 8@4240r 9@3632r 10@2784r 11@2720r 12@2960r 13@2432r 14@1904r 15@240r
W1 [0B,64r:0)[256r,272r:3)[2736r,2784r:2)[5680r,5696r:1)  0@0B-phi 1@5680r 2@2736r 3@256r
W2 [0B,48r:0)[2752r,2784r:1)  0@0B-phi 1@2752r
W3 [0B,32r:0)[2768r,2784r:1)  0@0B-phi 1@2768r
%vreg1 [80r,352r:0)  0@80r
%vreg3 [64r,368r:0)  0@64r
%vreg5 [48r,384r:0)  0@48r
%vreg7 [32r,400r:0)  0@32r
%vreg9 [464r,480r:0)  0@464r
%vreg12 [416r,448r:0)  0@416r
%vreg14 [160r,176r:0)  0@160r
%vreg16 [176r,240r:0)  0@176r
%vreg17 [16r,5680r:0)  0@16r
%vreg20 [512r,528r:0)  0@512r
%vreg22 [560r,576r:0)  0@560r
%vreg24 [608r,624r:0)  0@608r
%vreg26 [656r,672r:0)  0@656r
%vreg28 [704r,720r:0)  0@704r
%vreg30 [752r,768r:0)  0@752r
%vreg32 [1136r,1152r:0)  0@1136r
%vreg34 [1088r,1104r:0)  0@1088r
%vreg35 [1104r,1120r:0)  0@1104r
%vreg36 [1120r,1136r:0)  0@1120r
%vreg37 [1072r,1104r:0)  0@1072r
%vreg39 [1456r,1472r:0)  0@1456r
%vreg42 [1808r,1824r:0)  0@1808r
%vreg43 [1792r,1824r:0)  0@1792r
%vreg46 [1760r,1776r:0)  0@1760r
%vreg47 [1744r,1776r:0)  0@1744r
%vreg50 [1952r,2016r:0)  0@1952r
%vreg52 [1872r,1904r:0)  0@1872r
%vreg53 [1856r,1872r:0)  0@1856r
%vreg56 [2336r,2352r:0)  0@2336r
%vreg57 [2320r,2336r:0)  0@2320r
%vreg58 [2480r,2560r:0)  0@2480r
%vreg59 [2560r,2576r:0)  0@2560r
%vreg63 [2400r,2432r:0)  0@2400r
%vreg64 [2384r,2400r:0)  0@2384r
%vreg67 [3008r,3072r:0)  0@3008r
%vreg69 [2928r,2960r:0)  0@2928r
%vreg70 [2912r,2928r:0)  0@2912r
%vreg78 [2816r,2896r:0)  0@2816r
%vreg80 [2688r,2768r:0)  0@2688r
%vreg81 [2672r,2688r:0)  0@2672r
%vreg84 [2656r,2720r:0)  0@2656r
%vreg85 [2640r,2656r:0)  0@2640r
%vreg88 [3520r,3536r:0)  0@3520r
%vreg91 [3504r,3536r:0)  0@3504r
%vreg92 [3488r,3504r:0)  0@3488r
%vreg95 [3456r,3472r:0)  0@3456r
%vreg97 [3440r,3472r:0)  0@3440r
%vreg98 [3424r,3440r:0)  0@3424r
%vreg101 [3392r,3408r:0)  0@3392r
%vreg102 [3376r,3408r:0)  0@3376r
%vreg104 [3104r,3120r:0)  0@3104r
%vreg105 [3152r,3184r:0)  0@3152r
%vreg107 [3168r,3184r:0)  0@3168r
%vreg109 [3216r,3232r:0)  0@3216r
%vreg110 [3264r,3296r:0)  0@3264r
%vreg112 [3280r,3296r:0)  0@3280r
%vreg114 [3760r,3776r:0)  0@3760r
%vreg117 [3680r,3744r:0)  0@3680r
%vreg119 [3584r,3600r:0)  0@3584r
%vreg120 [3600r,3632r:0)  0@3600r
%vreg121 [3568r,3600r:0)  0@3568r
%vreg123 [3808r,3824r:0)  0@3808r
%vreg125 [4144r,4160r:0)  0@4144r
%vreg127 [4288r,4368r:0)  0@4288r
%vreg128 [4368r,4384r:0)  0@4368r
%vreg132 [4208r,4240r:0)  0@4208r
%vreg133 [4192r,4208r:0)  0@4192r
%vreg136 [4432r,4448r:0)  0@4432r
%vreg137 [4416r,4432r:0)  0@4416r
%vreg140 [4496r,4512r:0)  0@4496r
%vreg141 [4480r,4496r:0)  0@4480r
%vreg143 [4832r,4848r:0)  0@4832r
%vreg146 [5248r,5264r:0)  0@5248r
%vreg147 [5232r,5248r:0)  0@5232r
%vreg149 [5296r,5312r:0)  0@5296r
%vreg151 [5344r,5360r:0)  0@5344r
%vreg153 [5392r,5408r:0)  0@5392r
%vreg155 [5440r,5456r:0)  0@5440r
%vreg157 [5488r,5504r:0)  0@5488r
%vreg159 [4896r,4912r:0)  0@4896r
%vreg160 [4944r,4976r:0)  0@4944r
%vreg162 [4960r,4976r:0)  0@4960r
%vreg164 [5008r,5024r:0)  0@5008r
%vreg165 [5056r,5088r:0)  0@5056r
%vreg167 [5072r,5088r:0)  0@5072r
%vreg171 [5168r,5184r:0)  0@5168r
%vreg173 [5152r,5168r:0)  0@5152r
%vreg174 [5136r,5152r:0)  0@5136r
%vreg175 [5120r,5168r:0)  0@5120r
%vreg177 [4560r,4576r:0)  0@4560r
%vreg178 [4608r,4640r:0)  0@4608r
%vreg180 [4624r,4640r:0)  0@4624r
%vreg182 [4672r,4688r:0)  0@4672r
%vreg183 [4720r,4752r:0)  0@4720r
%vreg185 [4736r,4752r:0)  0@4736r
%vreg187 [3872r,3888r:0)  0@3872r
%vreg190 [3936r,3952r:0)  0@3936r
%vreg191 [3920r,3952r:0)  0@3920r
%vreg193 [3984r,4000r:0)  0@3984r
%vreg196 [4048r,4064r:0)  0@4048r
%vreg197 [4032r,4064r:0)  0@4032r
%vreg199 [2048r,2064r:0)  0@2048r
%vreg200 [2096r,2128r:0)  0@2096r
%vreg202 [2112r,2128r:0)  0@2112r
%vreg204 [2160r,2176r:0)  0@2160r
%vreg205 [2208r,2240r:0)  0@2208r
%vreg207 [2224r,2240r:0)  0@2224r
%vreg209 [1504r,1520r:0)  0@1504r
%vreg211 [1552r,1568r:0)  0@1552r
%vreg213 [1600r,1616r:0)  0@1600r
%vreg215 [1648r,1664r:0)  0@1648r
%vreg217 [1184r,1200r:0)  0@1184r
%vreg218 [1232r,1264r:0)  0@1232r
%vreg220 [1248r,1264r:0)  0@1248r
%vreg222 [1296r,1312r:0)  0@1296r
%vreg223 [1344r,1376r:0)  0@1344r
%vreg225 [1360r,1376r:0)  0@1360r
%vreg227 [800r,816r:0)  0@800r
%vreg228 [848r,880r:0)  0@848r
%vreg230 [864r,880r:0)  0@864r
%vreg232 [912r,928r:0)  0@912r
%vreg233 [960r,992r:0)  0@960r
%vreg235 [976r,992r:0)  0@976r
%vreg237 [5776r,5792r:0)  0@5776r
%vreg238 [5584r,5600r:0)  0@5584r
%vreg240 [5600r,5664r:0)  0@5600r
RegMasks: 272r 1920r 2448r 2784r 2976r 3648r 4256r 5696r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzRead: Post SSA
Frame Objects:
  fi#0: size=4, align=4, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=8, align=8, at location [SP]
  fi#3: size=8, align=8, at location [SP]
  fi#4: size=4, align=4, at location [SP]
  fi#5: size=4, align=4, at location [SP]
  fi#6: size=4, align=4, at location [SP]
  fi#7: size=8, align=8, at location [SP]
Function Live Ins: %X0 in %vreg0, %X1 in %vreg2, %X2 in %vreg4, %W3 in %vreg6, %LR in %vreg18

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %X1 %X2 %W3 %LR
16B		%vreg17<def> = COPY %LR; GPR64:%vreg17
32B		%vreg7<def> = COPY %W3; GPR32:%vreg7
48B		%vreg5<def> = COPY %X2; GPR64:%vreg5
64B		%vreg3<def> = COPY %X1; GPR64:%vreg3
80B		%vreg1<def> = COPY %X0; GPR64:%vreg1
160B		%vreg14<def> = ADRP <ga:@BZ2_bzRead>[TF=1]; GPR64common:%vreg14
176B		%vreg16<def> = ADDXri %vreg14, <ga:@BZ2_bzRead>[TF=34], 0; GPR64sp:%vreg16 GPR64common:%vreg14
224B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
240B		%X0<def> = COPY %vreg16; GPR64sp:%vreg16
256B		%X1<def> = COPY %vreg17; GPR64:%vreg17
272B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
288B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
304B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
320B		STACKMAP 0, 0, %vreg3, 0, <fi#2>, 0, %vreg5, 0, <fi#3>, 0, %vreg1, 0, <fi#1>, 0, 0, <fi#7>, 0, %vreg7, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2] LD8[FixedStack3] LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4) GPR64:%vreg3,%vreg5,%vreg1 GPR32:%vreg7
336B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
352B		STRXui %vreg1, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg1
368B		STRXui %vreg3, <fi#2>, 0; mem:ST8[FixedStack2] GPR64:%vreg3
384B		STRXui %vreg5, <fi#3>, 0; mem:ST8[FixedStack3] GPR64:%vreg5
400B		STRWui %vreg7, <fi#4>, 0; mem:ST4[FixedStack4] GPR32:%vreg7
416B		%vreg12<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg12
448B		STRXui %vreg12, <fi#7>, 0; mem:ST8[FixedStack7] GPR64:%vreg12
464B		%vreg9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg9
480B		CBZX %vreg9, <BB#2>; GPR64:%vreg9
	    Successors according to CFG: BB#2 BB#1

496B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
512B		%vreg20<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg20
528B		STRWui %WZR, %vreg20, 0; mem:ST4[%3] GPR64common:%vreg20
	    Successors according to CFG: BB#2

544B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#1
560B		%vreg22<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg22
576B		CBZX %vreg22, <BB#4>; GPR64:%vreg22
	    Successors according to CFG: BB#4 BB#3

592B	BB#3: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#2
608B		%vreg24<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg24
624B		STRWui %WZR, %vreg24, 1274; mem:ST4[%lastErr] GPR64common:%vreg24
	    Successors according to CFG: BB#4

640B	BB#4: derived from LLVM BB %if.end.3
	    Predecessors according to CFG: BB#2 BB#3
656B		%vreg26<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg26
672B		CBZX %vreg26, <BB#7>; GPR64:%vreg26
	    Successors according to CFG: BB#7 BB#5

688B	BB#5: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#4
704B		%vreg28<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg28
720B		CBZX %vreg28, <BB#7>; GPR64:%vreg28
	    Successors according to CFG: BB#7 BB#6

736B	BB#6: derived from LLVM BB %lor.lhs.false.6
	    Predecessors according to CFG: BB#5
752B		%vreg30<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg30
768B		TBZW %vreg30, 31, <BB#12>; GPR32:%vreg30
	    Successors according to CFG: BB#12 BB#7

784B	BB#7: derived from LLVM BB %if.then.8
	    Predecessors according to CFG: BB#4 BB#5 BB#6
800B		%vreg227<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg227
816B		CBZX %vreg227, <BB#9>; GPR64:%vreg227
	    Successors according to CFG: BB#9 BB#8

832B	BB#8: derived from LLVM BB %if.then.10
	    Predecessors according to CFG: BB#7
848B		%vreg228<def> = MOVi32imm 4294967294; GPR32:%vreg228
864B		%vreg230<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg230
880B		STRWui %vreg228, %vreg230, 0; mem:ST4[%10] GPR32:%vreg228 GPR64common:%vreg230
	    Successors according to CFG: BB#9

896B	BB#9: derived from LLVM BB %if.end.11
	    Predecessors according to CFG: BB#7 BB#8
912B		%vreg232<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg232
928B		CBZX %vreg232, <BB#11>; GPR64:%vreg232
	    Successors according to CFG: BB#11 BB#10

944B	BB#10: derived from LLVM BB %if.then.13
	    Predecessors according to CFG: BB#9
960B		%vreg233<def> = MOVi32imm 4294967294; GPR32:%vreg233
976B		%vreg235<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg235
992B		STRWui %vreg233, %vreg235, 1274; mem:ST4[%lastErr14] GPR32:%vreg233 GPR64common:%vreg235
	    Successors according to CFG: BB#11

1008B	BB#11: derived from LLVM BB %if.end.15
	    Predecessors according to CFG: BB#9 BB#10
1024B		STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
1040B		B <BB#69>
	    Successors according to CFG: BB#69

1056B	BB#12: derived from LLVM BB %if.end.16
	    Predecessors according to CFG: BB#6
1072B		%vreg37<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg37
1088B		%vreg34<def> = MOVi64imm 5012; GPR64:%vreg34
1104B		%vreg35<def> = ADDXrr %vreg37, %vreg34; GPR64common:%vreg35 GPR64:%vreg37,%vreg34
1120B		%vreg36<def> = LDRBBui %vreg35, 0; mem:LD1[%writing] GPR32:%vreg36 GPR64common:%vreg35
1136B		%vreg32<def> = UBFMWri %vreg36, 0, 7; GPR32:%vreg32,%vreg36
1152B		CBZW %vreg32, <BB#18>; GPR32:%vreg32
	    Successors according to CFG: BB#18 BB#13

1168B	BB#13: derived from LLVM BB %if.then.17
	    Predecessors according to CFG: BB#12
1184B		%vreg217<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg217
1200B		CBZX %vreg217, <BB#15>; GPR64:%vreg217
	    Successors according to CFG: BB#15 BB#14

1216B	BB#14: derived from LLVM BB %if.then.19
	    Predecessors according to CFG: BB#13
1232B		%vreg218<def> = MOVi32imm 4294967295; GPR32:%vreg218
1248B		%vreg220<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg220
1264B		STRWui %vreg218, %vreg220, 0; mem:ST4[%16] GPR32:%vreg218 GPR64common:%vreg220
	    Successors according to CFG: BB#15

1280B	BB#15: derived from LLVM BB %if.end.20
	    Predecessors according to CFG: BB#13 BB#14
1296B		%vreg222<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg222
1312B		CBZX %vreg222, <BB#17>; GPR64:%vreg222
	    Successors according to CFG: BB#17 BB#16

1328B	BB#16: derived from LLVM BB %if.then.22
	    Predecessors according to CFG: BB#15
1344B		%vreg223<def> = MOVi32imm 4294967295; GPR32:%vreg223
1360B		%vreg225<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg225
1376B		STRWui %vreg223, %vreg225, 1274; mem:ST4[%lastErr23] GPR32:%vreg223 GPR64common:%vreg225
	    Successors according to CFG: BB#17

1392B	BB#17: derived from LLVM BB %if.end.24
	    Predecessors according to CFG: BB#15 BB#16
1408B		STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
1424B		B <BB#69>
	    Successors according to CFG: BB#69

1440B	BB#18: derived from LLVM BB %if.end.25
	    Predecessors according to CFG: BB#12
1456B		%vreg39<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg39
1472B		CBNZW %vreg39, <BB#24>; GPR32:%vreg39
	    Successors according to CFG: BB#24 BB#19

1488B	BB#19: derived from LLVM BB %if.then.27
	    Predecessors according to CFG: BB#18
1504B		%vreg209<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg209
1520B		CBZX %vreg209, <BB#21>; GPR64:%vreg209
	    Successors according to CFG: BB#21 BB#20

1536B	BB#20: derived from LLVM BB %if.then.29
	    Predecessors according to CFG: BB#19
1552B		%vreg211<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg211
1568B		STRWui %WZR, %vreg211, 0; mem:ST4[%21] GPR64common:%vreg211
	    Successors according to CFG: BB#21

1584B	BB#21: derived from LLVM BB %if.end.30
	    Predecessors according to CFG: BB#19 BB#20
1600B		%vreg213<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg213
1616B		CBZX %vreg213, <BB#23>; GPR64:%vreg213
	    Successors according to CFG: BB#23 BB#22

1632B	BB#22: derived from LLVM BB %if.then.32
	    Predecessors according to CFG: BB#21
1648B		%vreg215<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg215
1664B		STRWui %WZR, %vreg215, 1274; mem:ST4[%lastErr33] GPR64common:%vreg215
	    Successors according to CFG: BB#23

1680B	BB#23: derived from LLVM BB %if.end.34
	    Predecessors according to CFG: BB#21 BB#22
1696B		STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
1712B		B <BB#69>
	    Successors according to CFG: BB#69

1728B	BB#24: derived from LLVM BB %if.end.35
	    Predecessors according to CFG: BB#18
1744B		%vreg47<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg47
1760B		%vreg46<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg46
1776B		STRWui %vreg47, %vreg46, 1262; mem:ST4[%avail_out] GPR32:%vreg47 GPR64common:%vreg46
1792B		%vreg43<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg43
1808B		%vreg42<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg42
1824B		STRXui %vreg43, %vreg42, 630; mem:ST8[%next_out] GPR64:%vreg43 GPR64common:%vreg42
	    Successors according to CFG: BB#25

1840B	BB#25: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#24 BB#68
1856B		%vreg53<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg53
1872B		%vreg52<def> = LDRXui %vreg53, 0; mem:LD8[%handle] GPR64:%vreg52 GPR64common:%vreg53
1888B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1904B		%X0<def> = COPY %vreg52; GPR64:%vreg52
1920B		BL <ga:@ferror>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
1936B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1952B		%vreg50<def> = COPY %W0; GPR32:%vreg50
1968B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1984B		STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
2000B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2016B		CBZW %vreg50, <BB#31>; GPR32:%vreg50
	    Successors according to CFG: BB#31 BB#26

2032B	BB#26: derived from LLVM BB %if.then.38
	    Predecessors according to CFG: BB#25
2048B		%vreg199<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg199
2064B		CBZX %vreg199, <BB#28>; GPR64:%vreg199
	    Successors according to CFG: BB#28 BB#27

2080B	BB#27: derived from LLVM BB %if.then.40
	    Predecessors according to CFG: BB#26
2096B		%vreg200<def> = MOVi32imm 4294967290; GPR32:%vreg200
2112B		%vreg202<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg202
2128B		STRWui %vreg200, %vreg202, 0; mem:ST4[%31] GPR32:%vreg200 GPR64common:%vreg202
	    Successors according to CFG: BB#28

2144B	BB#28: derived from LLVM BB %if.end.41
	    Predecessors according to CFG: BB#26 BB#27
2160B		%vreg204<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg204
2176B		CBZX %vreg204, <BB#30>; GPR64:%vreg204
	    Successors according to CFG: BB#30 BB#29

2192B	BB#29: derived from LLVM BB %if.then.43
	    Predecessors according to CFG: BB#28
2208B		%vreg205<def> = MOVi32imm 4294967290; GPR32:%vreg205
2224B		%vreg207<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg207
2240B		STRWui %vreg205, %vreg207, 1274; mem:ST4[%lastErr44] GPR32:%vreg205 GPR64common:%vreg207
	    Successors according to CFG: BB#30

2256B	BB#30: derived from LLVM BB %if.end.45
	    Predecessors according to CFG: BB#28 BB#29
2272B		STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
2288B		B <BB#69>
	    Successors according to CFG: BB#69

2304B	BB#31: derived from LLVM BB %if.end.46
	    Predecessors according to CFG: BB#25
2320B		%vreg57<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg57
2336B		%vreg56<def> = LDRWui %vreg57, 1256; mem:LD4[%avail_in] GPR32:%vreg56 GPR64common:%vreg57
2352B		CBNZW %vreg56, <BB#40>; GPR32:%vreg56
	    Successors according to CFG: BB#40 BB#32

2368B	BB#32: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#31
2384B		%vreg64<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg64
2400B		%vreg63<def> = LDRXui %vreg64, 0; mem:LD8[%handle49] GPR64:%vreg63 GPR64common:%vreg64
2416B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2432B		%X0<def> = COPY %vreg63; GPR64:%vreg63
2448B		BL <ga:@myfeof>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>
2464B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2480B		%vreg58<def> = COPY %W0; GPR32:%vreg58
2512B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2528B		STACKMAP 2, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
2544B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2560B		%vreg59<def> = UBFMWri %vreg58, 0, 7; GPR32:%vreg59,%vreg58
2576B		CBNZW %vreg59, <BB#40>; GPR32:%vreg59
	    Successors according to CFG: BB#40 BB#33

2592B	BB#33: derived from LLVM BB %if.then.52
	    Predecessors according to CFG: BB#32
2640B		%vreg85<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg85
2656B		%vreg84<def> = ADDXri %vreg85, 8, 0; GPR64sp:%vreg84 GPR64common:%vreg85
2672B		%vreg81<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg81
2688B		%vreg80<def> = LDRXui %vreg81, 0; mem:LD8[%handle54] GPR64:%vreg80 GPR64common:%vreg81
2704B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2720B		%X0<def> = COPY %vreg84; GPR64sp:%vreg84
2736B		%X1<def> = MOVi64imm 1
2752B		%X2<def> = MOVi64imm 5000
2768B		%X3<def> = COPY %vreg80; GPR64:%vreg80
2784B		BL <ga:@fread>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %X2<imp-use>, %X3<imp-use>, %X0<imp-def>
2800B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2816B		%vreg78<def> = COPY %X0; GPR64:%vreg78
2832B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2848B		STACKMAP 3, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
2864B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2896B		STRWui %vreg78:sub_32, <fi#5>, 0; mem:ST4[FixedStack5] GPR64:%vreg78
2912B		%vreg70<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg70
2928B		%vreg69<def> = LDRXui %vreg70, 0; mem:LD8[%handle56] GPR64:%vreg69 GPR64common:%vreg70
2944B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2960B		%X0<def> = COPY %vreg69; GPR64:%vreg69
2976B		BL <ga:@ferror>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
2992B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3008B		%vreg67<def> = COPY %W0; GPR32:%vreg67
3024B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3040B		STACKMAP 4, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
3056B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3072B		CBZW %vreg67, <BB#39>; GPR32:%vreg67
	    Successors according to CFG: BB#39 BB#34

3088B	BB#34: derived from LLVM BB %if.then.59
	    Predecessors according to CFG: BB#33
3104B		%vreg104<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg104
3120B		CBZX %vreg104, <BB#36>; GPR64:%vreg104
	    Successors according to CFG: BB#36 BB#35

3136B	BB#35: derived from LLVM BB %if.then.62
	    Predecessors according to CFG: BB#34
3152B		%vreg105<def> = MOVi32imm 4294967290; GPR32:%vreg105
3168B		%vreg107<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg107
3184B		STRWui %vreg105, %vreg107, 0; mem:ST4[%44] GPR32:%vreg105 GPR64common:%vreg107
	    Successors according to CFG: BB#36

3200B	BB#36: derived from LLVM BB %if.end.63
	    Predecessors according to CFG: BB#34 BB#35
3216B		%vreg109<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg109
3232B		CBZX %vreg109, <BB#38>; GPR64:%vreg109
	    Successors according to CFG: BB#38 BB#37

3248B	BB#37: derived from LLVM BB %if.then.66
	    Predecessors according to CFG: BB#36
3264B		%vreg110<def> = MOVi32imm 4294967290; GPR32:%vreg110
3280B		%vreg112<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg112
3296B		STRWui %vreg110, %vreg112, 1274; mem:ST4[%lastErr67] GPR32:%vreg110 GPR64common:%vreg112
	    Successors according to CFG: BB#38

3312B	BB#38: derived from LLVM BB %if.end.68
	    Predecessors according to CFG: BB#36 BB#37
3328B		STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
3344B		B <BB#69>
	    Successors according to CFG: BB#69

3360B	BB#39: derived from LLVM BB %if.end.69
	    Predecessors according to CFG: BB#33
3376B		%vreg102<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32:%vreg102
3392B		%vreg101<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg101
3408B		STRWui %vreg102, %vreg101, 1252; mem:ST4[%bufN] GPR32:%vreg102 GPR64common:%vreg101
3424B		%vreg98<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg98
3440B		%vreg97<def> = LDRWui %vreg98, 1252; mem:LD4[%bufN70] GPR32:%vreg97 GPR64common:%vreg98
3456B		%vreg95<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg95
3472B		STRWui %vreg97, %vreg95, 1256; mem:ST4[%avail_in72] GPR32:%vreg97 GPR64common:%vreg95
3488B		%vreg92<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg92
3504B		%vreg91<def> = ADDXri %vreg92, 8, 0; GPR64common:%vreg91,%vreg92
3520B		%vreg88<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg88
3536B		STRXui %vreg91, %vreg88, 627; mem:ST8[%next_in] GPR64common:%vreg91,%vreg88
	    Successors according to CFG: BB#40

3552B	BB#40: derived from LLVM BB %if.end.76
	    Predecessors according to CFG: BB#31 BB#32 BB#39
3568B		%vreg121<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg121
3584B		%vreg119<def> = MOVi64imm 5016; GPR64:%vreg119
3600B		%vreg120<def> = ADDXrr %vreg121, %vreg119; GPR64:%vreg120,%vreg121,%vreg119
3616B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3632B		%X0<def> = COPY %vreg120; GPR64:%vreg120
3648B		BL <ga:@BZ2_bzDecompress>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
3664B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3680B		%vreg117<def> = COPY %W0; GPR32:%vreg117
3696B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3712B		STACKMAP 5, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
3728B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3744B		STRWui %vreg117, <fi#6>, 0; mem:ST4[FixedStack6] GPR32:%vreg117
3760B		%vreg114<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg114
3776B		CBZW %vreg114, <BB#47>; GPR32:%vreg114
	    Successors according to CFG: BB#47 BB#41

3792B	BB#41: derived from LLVM BB %land.lhs.true.81
	    Predecessors according to CFG: BB#40
3808B		%vreg123<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32common:%vreg123
3824B		%WZR<def> = SUBSWri %vreg123, 4, 0, %NZCV<imp-def>; GPR32common:%vreg123
3840B		Bcc 0, <BB#47>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#47 BB#42

3856B	BB#42: derived from LLVM BB %if.then.84
	    Predecessors according to CFG: BB#41
3872B		%vreg187<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg187
3888B		CBZX %vreg187, <BB#44>; GPR64:%vreg187
	    Successors according to CFG: BB#44 BB#43

3904B	BB#43: derived from LLVM BB %if.then.87
	    Predecessors according to CFG: BB#42
3920B		%vreg191<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg191
3936B		%vreg190<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg190
3952B		STRWui %vreg191, %vreg190, 0; mem:ST4[%59] GPR32:%vreg191 GPR64common:%vreg190
	    Successors according to CFG: BB#44

3968B	BB#44: derived from LLVM BB %if.end.88
	    Predecessors according to CFG: BB#42 BB#43
3984B		%vreg193<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg193
4000B		CBZX %vreg193, <BB#46>; GPR64:%vreg193
	    Successors according to CFG: BB#46 BB#45

4016B	BB#45: derived from LLVM BB %if.then.91
	    Predecessors according to CFG: BB#44
4032B		%vreg197<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg197
4048B		%vreg196<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg196
4064B		STRWui %vreg197, %vreg196, 1274; mem:ST4[%lastErr92] GPR32:%vreg197 GPR64common:%vreg196
	    Successors according to CFG: BB#46

4080B	BB#46: derived from LLVM BB %if.end.93
	    Predecessors according to CFG: BB#44 BB#45
4096B		STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
4112B		B <BB#69>
	    Successors according to CFG: BB#69

4128B	BB#47: derived from LLVM BB %if.end.94
	    Predecessors according to CFG: BB#40 BB#41
4144B		%vreg125<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg125
4160B		CBNZW %vreg125, <BB#56>; GPR32:%vreg125
	    Successors according to CFG: BB#56 BB#48

4176B	BB#48: derived from LLVM BB %land.lhs.true.97
	    Predecessors according to CFG: BB#47
4192B		%vreg133<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg133
4208B		%vreg132<def> = LDRXui %vreg133, 0; mem:LD8[%handle98] GPR64:%vreg132 GPR64common:%vreg133
4224B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4240B		%X0<def> = COPY %vreg132; GPR64:%vreg132
4256B		BL <ga:@myfeof>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>
4272B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4288B		%vreg127<def> = COPY %W0; GPR32:%vreg127
4320B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4336B		STACKMAP 6, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
4352B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4368B		%vreg128<def> = UBFMWri %vreg127, 0, 7; GPR32:%vreg128,%vreg127
4384B		CBZW %vreg128, <BB#56>; GPR32:%vreg128
	    Successors according to CFG: BB#56 BB#49

4400B	BB#49: derived from LLVM BB %land.lhs.true.102
	    Predecessors according to CFG: BB#48
4416B		%vreg137<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg137
4432B		%vreg136<def> = LDRWui %vreg137, 1256; mem:LD4[%avail_in104] GPR32:%vreg136 GPR64common:%vreg137
4448B		CBNZW %vreg136, <BB#56>; GPR32:%vreg136
	    Successors according to CFG: BB#56 BB#50

4464B	BB#50: derived from LLVM BB %land.lhs.true.107
	    Predecessors according to CFG: BB#49
4480B		%vreg141<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg141
4496B		%vreg140<def> = LDRWui %vreg141, 1262; mem:LD4[%avail_out109] GPR32common:%vreg140 GPR64common:%vreg141
4512B		%WZR<def> = SUBSWri %vreg140, 0, 0, %NZCV<imp-def>; GPR32common:%vreg140
4528B		Bcc 9, <BB#56>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#56 BB#51

4544B	BB#51: derived from LLVM BB %if.then.112
	    Predecessors according to CFG: BB#50
4560B		%vreg177<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg177
4576B		CBZX %vreg177, <BB#53>; GPR64:%vreg177
	    Successors according to CFG: BB#53 BB#52

4592B	BB#52: derived from LLVM BB %if.then.115
	    Predecessors according to CFG: BB#51
4608B		%vreg178<def> = MOVi32imm 4294967289; GPR32:%vreg178
4624B		%vreg180<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg180
4640B		STRWui %vreg178, %vreg180, 0; mem:ST4[%71] GPR32:%vreg178 GPR64common:%vreg180
	    Successors according to CFG: BB#53

4656B	BB#53: derived from LLVM BB %if.end.116
	    Predecessors according to CFG: BB#51 BB#52
4672B		%vreg182<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg182
4688B		CBZX %vreg182, <BB#55>; GPR64:%vreg182
	    Successors according to CFG: BB#55 BB#54

4704B	BB#54: derived from LLVM BB %if.then.119
	    Predecessors according to CFG: BB#53
4720B		%vreg183<def> = MOVi32imm 4294967289; GPR32:%vreg183
4736B		%vreg185<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg185
4752B		STRWui %vreg183, %vreg185, 1274; mem:ST4[%lastErr120] GPR32:%vreg183 GPR64common:%vreg185
	    Successors according to CFG: BB#55

4768B	BB#55: derived from LLVM BB %if.end.121
	    Predecessors according to CFG: BB#53 BB#54
4784B		STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
4800B		B <BB#69>
	    Successors according to CFG: BB#69

4816B	BB#56: derived from LLVM BB %if.end.122
	    Predecessors according to CFG: BB#47 BB#48 BB#49 BB#50
4832B		%vreg143<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32common:%vreg143
4848B		%WZR<def> = SUBSWri %vreg143, 4, 0, %NZCV<imp-def>; GPR32common:%vreg143
4864B		Bcc 1, <BB#62>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#62 BB#57

4880B	BB#57: derived from LLVM BB %if.then.125
	    Predecessors according to CFG: BB#56
4896B		%vreg159<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg159
4912B		CBZX %vreg159, <BB#59>; GPR64:%vreg159
	    Successors according to CFG: BB#59 BB#58

4928B	BB#58: derived from LLVM BB %if.then.128
	    Predecessors according to CFG: BB#57
4944B		%vreg160<def> = MOVi32imm 4; GPR32:%vreg160
4960B		%vreg162<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg162
4976B		STRWui %vreg160, %vreg162, 0; mem:ST4[%76] GPR32:%vreg160 GPR64common:%vreg162
	    Successors according to CFG: BB#59

4992B	BB#59: derived from LLVM BB %if.end.129
	    Predecessors according to CFG: BB#57 BB#58
5008B		%vreg164<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg164
5024B		CBZX %vreg164, <BB#61>; GPR64:%vreg164
	    Successors according to CFG: BB#61 BB#60

5040B	BB#60: derived from LLVM BB %if.then.132
	    Predecessors according to CFG: BB#59
5056B		%vreg165<def> = MOVi32imm 4; GPR32:%vreg165
5072B		%vreg167<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg167
5088B		STRWui %vreg165, %vreg167, 1274; mem:ST4[%lastErr133] GPR32:%vreg165 GPR64common:%vreg167
	    Successors according to CFG: BB#61

5104B	BB#61: derived from LLVM BB %if.end.134
	    Predecessors according to CFG: BB#59 BB#60
5120B		%vreg175<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg175
5136B		%vreg174<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg174
5152B		%vreg173<def> = LDRWui %vreg174, 1262; mem:LD4[%avail_out136] GPR32:%vreg173 GPR64common:%vreg174
5168B		%vreg171<def> = SUBWrr %vreg175, %vreg173; GPR32:%vreg171,%vreg175,%vreg173
5184B		STRWui %vreg171, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg171
5200B		B <BB#69>
	    Successors according to CFG: BB#69

5216B	BB#62: derived from LLVM BB %if.end.137
	    Predecessors according to CFG: BB#56
5232B		%vreg147<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg147
5248B		%vreg146<def> = LDRWui %vreg147, 1262; mem:LD4[%avail_out139] GPR32:%vreg146 GPR64common:%vreg147
5264B		CBNZW %vreg146, <BB#68>; GPR32:%vreg146
	    Successors according to CFG: BB#68 BB#63

5280B	BB#63: derived from LLVM BB %if.then.142
	    Predecessors according to CFG: BB#62
5296B		%vreg149<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg149
5312B		CBZX %vreg149, <BB#65>; GPR64:%vreg149
	    Successors according to CFG: BB#65 BB#64

5328B	BB#64: derived from LLVM BB %if.then.145
	    Predecessors according to CFG: BB#63
5344B		%vreg151<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg151
5360B		STRWui %WZR, %vreg151, 0; mem:ST4[%85] GPR64common:%vreg151
	    Successors according to CFG: BB#65

5376B	BB#65: derived from LLVM BB %if.end.146
	    Predecessors according to CFG: BB#63 BB#64
5392B		%vreg153<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg153
5408B		CBZX %vreg153, <BB#67>; GPR64:%vreg153
	    Successors according to CFG: BB#67 BB#66

5424B	BB#66: derived from LLVM BB %if.then.149
	    Predecessors according to CFG: BB#65
5440B		%vreg155<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg155
5456B		STRWui %WZR, %vreg155, 1274; mem:ST4[%lastErr150] GPR64common:%vreg155
	    Successors according to CFG: BB#67

5472B	BB#67: derived from LLVM BB %if.end.151
	    Predecessors according to CFG: BB#65 BB#66
5488B		%vreg157<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg157
5504B		STRWui %vreg157, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg157
5520B		B <BB#69>
	    Successors according to CFG: BB#69

5536B	BB#68: derived from LLVM BB %if.end.152
	    Predecessors according to CFG: BB#62
5552B		B <BB#25>
	    Successors according to CFG: BB#25

5568B	BB#69: derived from LLVM BB %return
	    Predecessors according to CFG: BB#38 BB#67 BB#61 BB#55 BB#46 BB#30 BB#23 BB#17 BB#11
5584B		%vreg238<def> = ADRP <ga:@BZ2_bzRead>[TF=1]; GPR64common:%vreg238
5600B		%vreg240<def> = ADDXri %vreg238, <ga:@BZ2_bzRead>[TF=34], 0; GPR64sp:%vreg240 GPR64common:%vreg238
5648B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5664B		%X0<def> = COPY %vreg240; GPR64sp:%vreg240
5680B		%X1<def> = COPY %vreg17; GPR64:%vreg17
5696B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
5712B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5728B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5744B		STACKMAP 7, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
5760B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5776B		%vreg237<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0] GPR32:%vreg237
5792B		%W0<def> = COPY %vreg237; GPR32:%vreg237
5808B		RET_ReallyLR %W0<imp-use>

# End machine code for function BZ2_bzRead.

handleMove 848B -> 872B: %vreg228<def> = MOVi32imm 4294967294; GPR32:%vreg228
     %vreg228:	[848r,880r:0)  0@848r
        -->	[872r,880r:0)  0@872r
handleMove 960B -> 984B: %vreg233<def> = MOVi32imm 4294967294; GPR32:%vreg233
     %vreg233:	[960r,992r:0)  0@960r
        -->	[984r,992r:0)  0@984r
handleMove 1232B -> 1256B: %vreg218<def> = MOVi32imm 4294967295; GPR32:%vreg218
     %vreg218:	[1232r,1264r:0)  0@1232r
        -->	[1256r,1264r:0)  0@1256r
handleMove 1344B -> 1368B: %vreg223<def> = MOVi32imm 4294967295; GPR32:%vreg223
     %vreg223:	[1344r,1376r:0)  0@1344r
        -->	[1368r,1376r:0)  0@1368r
handleMove 2096B -> 2120B: %vreg200<def> = MOVi32imm 4294967290; GPR32:%vreg200
     %vreg200:	[2096r,2128r:0)  0@2096r
        -->	[2120r,2128r:0)  0@2120r
handleMove 2208B -> 2232B: %vreg205<def> = MOVi32imm 4294967290; GPR32:%vreg205
     %vreg205:	[2208r,2240r:0)  0@2208r
        -->	[2232r,2240r:0)  0@2232r
handleMove 2736B -> 2712B: %X1<def> = MOVi64imm 1
     W1:	[0B,64r:0)[256r,272r:3)[2736r,2784r:2)[5680r,5696r:1)  0@0B-phi 1@5680r 2@2736r 3@256r
        -->	[0B,64r:0)[256r,272r:3)[2712r,2784r:2)[5680r,5696r:1)  0@0B-phi 1@5680r 2@2712r 3@256r
handleMove 2752B -> 2716B: %X2<def> = MOVi64imm 5000
     W2:	[0B,48r:0)[2752r,2784r:1)  0@0B-phi 1@2752r
        -->	[0B,48r:0)[2716r,2784r:1)  0@0B-phi 1@2716r
handleMove 2656B -> 2696B: %vreg84<def> = ADDXri %vreg85, 8, 0; GPR64sp:%vreg84 GPR64common:%vreg85
     %vreg84:	[2656r,2720r:0)  0@2656r
        -->	[2696r,2720r:0)  0@2696r
     %vreg85:	[2640r,2656r:0)  0@2640r
        -->	[2640r,2696r:0)  0@2640r
handleMove 2640B -> 2680B: %vreg85<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg85
     %vreg85:	[2640r,2696r:0)  0@2640r
        -->	[2680r,2696r:0)  0@2680r
handleMove 3152B -> 3176B: %vreg105<def> = MOVi32imm 4294967290; GPR32:%vreg105
     %vreg105:	[3152r,3184r:0)  0@3152r
        -->	[3176r,3184r:0)  0@3176r
handleMove 3264B -> 3288B: %vreg110<def> = MOVi32imm 4294967290; GPR32:%vreg110
     %vreg110:	[3264r,3296r:0)  0@3264r
        -->	[3288r,3296r:0)  0@3288r
handleMove 3504B -> 3528B: %vreg91<def> = ADDXri %vreg92, 8, 0; GPR64common:%vreg91,%vreg92
     %vreg91:	[3504r,3536r:0)  0@3504r
        -->	[3528r,3536r:0)  0@3528r
     %vreg92:	[3488r,3504r:0)  0@3488r
        -->	[3488r,3528r:0)  0@3488r
handleMove 4608B -> 4632B: %vreg178<def> = MOVi32imm 4294967289; GPR32:%vreg178
     %vreg178:	[4608r,4640r:0)  0@4608r
        -->	[4632r,4640r:0)  0@4632r
handleMove 4720B -> 4744B: %vreg183<def> = MOVi32imm 4294967289; GPR32:%vreg183
     %vreg183:	[4720r,4752r:0)  0@4720r
        -->	[4744r,4752r:0)  0@4744r
handleMove 4944B -> 4968B: %vreg160<def> = MOVi32imm 4; GPR32:%vreg160
     %vreg160:	[4944r,4976r:0)  0@4944r
        -->	[4968r,4976r:0)  0@4968r
handleMove 5056B -> 5080B: %vreg165<def> = MOVi32imm 4; GPR32:%vreg165
     %vreg165:	[5056r,5088r:0)  0@5056r
        -->	[5080r,5088r:0)  0@5080r
handleMove 5120B -> 5144B: %vreg175<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg175
     %vreg175:	[5120r,5168r:0)  0@5120r
        -->	[5144r,5168r:0)  0@5144r
********** GREEDY REGISTER ALLOCATION **********
********** Function: BZ2_bzRead
********** INTERVALS **********
W30 [0B,16r:0)[272r,272d:16)[320e,320d:8)[1920r,1920d:15)[1984e,1984d:7)[2448r,2448d:14)[2528e,2528d:6)[2784r,2784d:12)[2848e,2848d:5)[2976r,2976d:13)[3040e,3040d:4)[3648r,3648d:11)[3712e,3712d:3)[4256r,4256d:10)[4336e,4336d:2)[5696r,5696d:9)[5744e,5744d:1)  0@0B-phi 1@5744e 2@4336e 3@3712e 4@3040e 5@2848e 6@2528e 7@1984e 8@320e 9@5696r 10@4256r 11@3648r 12@2784r 13@2976r 14@2448r 15@1920r 16@272r
W0 [0B,80r:0)[240r,272r:15)[1904r,1920r:14)[1920r,1952r:6)[2432r,2448r:13)[2448r,2480r:5)[2720r,2784r:11)[2784r,2816r:10)[2960r,2976r:12)[2976r,3008r:4)[3632r,3648r:9)[3648r,3680r:3)[4240r,4256r:8)[4256r,4288r:2)[5664r,5696r:7)[5792r,5808r:1)  0@0B-phi 1@5792r 2@4256r 3@3648r 4@2976r 5@2448r 6@1920r 7@5664r 8@4240r 9@3632r 10@2784r 11@2720r 12@2960r 13@2432r 14@1904r 15@240r
W1 [0B,64r:0)[256r,272r:3)[2712r,2784r:2)[5680r,5696r:1)  0@0B-phi 1@5680r 2@2712r 3@256r
W2 [0B,48r:0)[2716r,2784r:1)  0@0B-phi 1@2716r
W3 [0B,32r:0)[2768r,2784r:1)  0@0B-phi 1@2768r
%vreg1 [80r,352r:0)  0@80r
%vreg3 [64r,368r:0)  0@64r
%vreg5 [48r,384r:0)  0@48r
%vreg7 [32r,400r:0)  0@32r
%vreg9 [464r,480r:0)  0@464r
%vreg12 [416r,448r:0)  0@416r
%vreg14 [160r,176r:0)  0@160r
%vreg16 [176r,240r:0)  0@176r
%vreg17 [16r,5680r:0)  0@16r
%vreg20 [512r,528r:0)  0@512r
%vreg22 [560r,576r:0)  0@560r
%vreg24 [608r,624r:0)  0@608r
%vreg26 [656r,672r:0)  0@656r
%vreg28 [704r,720r:0)  0@704r
%vreg30 [752r,768r:0)  0@752r
%vreg32 [1136r,1152r:0)  0@1136r
%vreg34 [1088r,1104r:0)  0@1088r
%vreg35 [1104r,1120r:0)  0@1104r
%vreg36 [1120r,1136r:0)  0@1120r
%vreg37 [1072r,1104r:0)  0@1072r
%vreg39 [1456r,1472r:0)  0@1456r
%vreg42 [1808r,1824r:0)  0@1808r
%vreg43 [1792r,1824r:0)  0@1792r
%vreg46 [1760r,1776r:0)  0@1760r
%vreg47 [1744r,1776r:0)  0@1744r
%vreg50 [1952r,2016r:0)  0@1952r
%vreg52 [1872r,1904r:0)  0@1872r
%vreg53 [1856r,1872r:0)  0@1856r
%vreg56 [2336r,2352r:0)  0@2336r
%vreg57 [2320r,2336r:0)  0@2320r
%vreg58 [2480r,2560r:0)  0@2480r
%vreg59 [2560r,2576r:0)  0@2560r
%vreg63 [2400r,2432r:0)  0@2400r
%vreg64 [2384r,2400r:0)  0@2384r
%vreg67 [3008r,3072r:0)  0@3008r
%vreg69 [2928r,2960r:0)  0@2928r
%vreg70 [2912r,2928r:0)  0@2912r
%vreg78 [2816r,2896r:0)  0@2816r
%vreg80 [2688r,2768r:0)  0@2688r
%vreg81 [2672r,2688r:0)  0@2672r
%vreg84 [2696r,2720r:0)  0@2696r
%vreg85 [2680r,2696r:0)  0@2680r
%vreg88 [3520r,3536r:0)  0@3520r
%vreg91 [3528r,3536r:0)  0@3528r
%vreg92 [3488r,3528r:0)  0@3488r
%vreg95 [3456r,3472r:0)  0@3456r
%vreg97 [3440r,3472r:0)  0@3440r
%vreg98 [3424r,3440r:0)  0@3424r
%vreg101 [3392r,3408r:0)  0@3392r
%vreg102 [3376r,3408r:0)  0@3376r
%vreg104 [3104r,3120r:0)  0@3104r
%vreg105 [3176r,3184r:0)  0@3176r
%vreg107 [3168r,3184r:0)  0@3168r
%vreg109 [3216r,3232r:0)  0@3216r
%vreg110 [3288r,3296r:0)  0@3288r
%vreg112 [3280r,3296r:0)  0@3280r
%vreg114 [3760r,3776r:0)  0@3760r
%vreg117 [3680r,3744r:0)  0@3680r
%vreg119 [3584r,3600r:0)  0@3584r
%vreg120 [3600r,3632r:0)  0@3600r
%vreg121 [3568r,3600r:0)  0@3568r
%vreg123 [3808r,3824r:0)  0@3808r
%vreg125 [4144r,4160r:0)  0@4144r
%vreg127 [4288r,4368r:0)  0@4288r
%vreg128 [4368r,4384r:0)  0@4368r
%vreg132 [4208r,4240r:0)  0@4208r
%vreg133 [4192r,4208r:0)  0@4192r
%vreg136 [4432r,4448r:0)  0@4432r
%vreg137 [4416r,4432r:0)  0@4416r
%vreg140 [4496r,4512r:0)  0@4496r
%vreg141 [4480r,4496r:0)  0@4480r
%vreg143 [4832r,4848r:0)  0@4832r
%vreg146 [5248r,5264r:0)  0@5248r
%vreg147 [5232r,5248r:0)  0@5232r
%vreg149 [5296r,5312r:0)  0@5296r
%vreg151 [5344r,5360r:0)  0@5344r
%vreg153 [5392r,5408r:0)  0@5392r
%vreg155 [5440r,5456r:0)  0@5440r
%vreg157 [5488r,5504r:0)  0@5488r
%vreg159 [4896r,4912r:0)  0@4896r
%vreg160 [4968r,4976r:0)  0@4968r
%vreg162 [4960r,4976r:0)  0@4960r
%vreg164 [5008r,5024r:0)  0@5008r
%vreg165 [5080r,5088r:0)  0@5080r
%vreg167 [5072r,5088r:0)  0@5072r
%vreg171 [5168r,5184r:0)  0@5168r
%vreg173 [5152r,5168r:0)  0@5152r
%vreg174 [5136r,5152r:0)  0@5136r
%vreg175 [5144r,5168r:0)  0@5144r
%vreg177 [4560r,4576r:0)  0@4560r
%vreg178 [4632r,4640r:0)  0@4632r
%vreg180 [4624r,4640r:0)  0@4624r
%vreg182 [4672r,4688r:0)  0@4672r
%vreg183 [4744r,4752r:0)  0@4744r
%vreg185 [4736r,4752r:0)  0@4736r
%vreg187 [3872r,3888r:0)  0@3872r
%vreg190 [3936r,3952r:0)  0@3936r
%vreg191 [3920r,3952r:0)  0@3920r
%vreg193 [3984r,4000r:0)  0@3984r
%vreg196 [4048r,4064r:0)  0@4048r
%vreg197 [4032r,4064r:0)  0@4032r
%vreg199 [2048r,2064r:0)  0@2048r
%vreg200 [2120r,2128r:0)  0@2120r
%vreg202 [2112r,2128r:0)  0@2112r
%vreg204 [2160r,2176r:0)  0@2160r
%vreg205 [2232r,2240r:0)  0@2232r
%vreg207 [2224r,2240r:0)  0@2224r
%vreg209 [1504r,1520r:0)  0@1504r
%vreg211 [1552r,1568r:0)  0@1552r
%vreg213 [1600r,1616r:0)  0@1600r
%vreg215 [1648r,1664r:0)  0@1648r
%vreg217 [1184r,1200r:0)  0@1184r
%vreg218 [1256r,1264r:0)  0@1256r
%vreg220 [1248r,1264r:0)  0@1248r
%vreg222 [1296r,1312r:0)  0@1296r
%vreg223 [1368r,1376r:0)  0@1368r
%vreg225 [1360r,1376r:0)  0@1360r
%vreg227 [800r,816r:0)  0@800r
%vreg228 [872r,880r:0)  0@872r
%vreg230 [864r,880r:0)  0@864r
%vreg232 [912r,928r:0)  0@912r
%vreg233 [984r,992r:0)  0@984r
%vreg235 [976r,992r:0)  0@976r
%vreg237 [5776r,5792r:0)  0@5776r
%vreg238 [5584r,5600r:0)  0@5584r
%vreg240 [5600r,5664r:0)  0@5600r
RegMasks: 272r 1920r 2448r 2784r 2976r 3648r 4256r 5696r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzRead: Post SSA
Frame Objects:
  fi#0: size=4, align=4, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=8, align=8, at location [SP]
  fi#3: size=8, align=8, at location [SP]
  fi#4: size=4, align=4, at location [SP]
  fi#5: size=4, align=4, at location [SP]
  fi#6: size=4, align=4, at location [SP]
  fi#7: size=8, align=8, at location [SP]
Function Live Ins: %X0 in %vreg0, %X1 in %vreg2, %X2 in %vreg4, %W3 in %vreg6, %LR in %vreg18

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %X1 %X2 %W3 %LR
16B		%vreg17<def> = COPY %LR; GPR64:%vreg17
32B		%vreg7<def> = COPY %W3; GPR32:%vreg7
48B		%vreg5<def> = COPY %X2; GPR64:%vreg5
64B		%vreg3<def> = COPY %X1; GPR64:%vreg3
80B		%vreg1<def> = COPY %X0; GPR64:%vreg1
160B		%vreg14<def> = ADRP <ga:@BZ2_bzRead>[TF=1]; GPR64common:%vreg14
176B		%vreg16<def> = ADDXri %vreg14, <ga:@BZ2_bzRead>[TF=34], 0; GPR64sp:%vreg16 GPR64common:%vreg14
224B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
240B		%X0<def> = COPY %vreg16; GPR64sp:%vreg16
256B		%X1<def> = COPY %vreg17; GPR64:%vreg17
272B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
288B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
304B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
320B		STACKMAP 0, 0, %vreg3, 0, <fi#2>, 0, %vreg5, 0, <fi#3>, 0, %vreg1, 0, <fi#1>, 0, 0, <fi#7>, 0, %vreg7, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2] LD8[FixedStack3] LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4) GPR64:%vreg3,%vreg5,%vreg1 GPR32:%vreg7
336B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
352B		STRXui %vreg1, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg1
368B		STRXui %vreg3, <fi#2>, 0; mem:ST8[FixedStack2] GPR64:%vreg3
384B		STRXui %vreg5, <fi#3>, 0; mem:ST8[FixedStack3] GPR64:%vreg5
400B		STRWui %vreg7, <fi#4>, 0; mem:ST4[FixedStack4] GPR32:%vreg7
416B		%vreg12<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg12
448B		STRXui %vreg12, <fi#7>, 0; mem:ST8[FixedStack7] GPR64:%vreg12
464B		%vreg9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg9
480B		CBZX %vreg9, <BB#2>; GPR64:%vreg9
	    Successors according to CFG: BB#2 BB#1

496B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
512B		%vreg20<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg20
528B		STRWui %WZR, %vreg20, 0; mem:ST4[%3] GPR64common:%vreg20
	    Successors according to CFG: BB#2

544B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#1
560B		%vreg22<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg22
576B		CBZX %vreg22, <BB#4>; GPR64:%vreg22
	    Successors according to CFG: BB#4 BB#3

592B	BB#3: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#2
608B		%vreg24<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg24
624B		STRWui %WZR, %vreg24, 1274; mem:ST4[%lastErr] GPR64common:%vreg24
	    Successors according to CFG: BB#4

640B	BB#4: derived from LLVM BB %if.end.3
	    Predecessors according to CFG: BB#2 BB#3
656B		%vreg26<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg26
672B		CBZX %vreg26, <BB#7>; GPR64:%vreg26
	    Successors according to CFG: BB#7 BB#5

688B	BB#5: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#4
704B		%vreg28<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg28
720B		CBZX %vreg28, <BB#7>; GPR64:%vreg28
	    Successors according to CFG: BB#7 BB#6

736B	BB#6: derived from LLVM BB %lor.lhs.false.6
	    Predecessors according to CFG: BB#5
752B		%vreg30<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg30
768B		TBZW %vreg30, 31, <BB#12>; GPR32:%vreg30
	    Successors according to CFG: BB#12 BB#7

784B	BB#7: derived from LLVM BB %if.then.8
	    Predecessors according to CFG: BB#4 BB#5 BB#6
800B		%vreg227<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg227
816B		CBZX %vreg227, <BB#9>; GPR64:%vreg227
	    Successors according to CFG: BB#9 BB#8

832B	BB#8: derived from LLVM BB %if.then.10
	    Predecessors according to CFG: BB#7
864B		%vreg230<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg230
872B		%vreg228<def> = MOVi32imm 4294967294; GPR32:%vreg228
880B		STRWui %vreg228, %vreg230, 0; mem:ST4[%10] GPR32:%vreg228 GPR64common:%vreg230
	    Successors according to CFG: BB#9

896B	BB#9: derived from LLVM BB %if.end.11
	    Predecessors according to CFG: BB#7 BB#8
912B		%vreg232<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg232
928B		CBZX %vreg232, <BB#11>; GPR64:%vreg232
	    Successors according to CFG: BB#11 BB#10

944B	BB#10: derived from LLVM BB %if.then.13
	    Predecessors according to CFG: BB#9
976B		%vreg235<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg235
984B		%vreg233<def> = MOVi32imm 4294967294; GPR32:%vreg233
992B		STRWui %vreg233, %vreg235, 1274; mem:ST4[%lastErr14] GPR32:%vreg233 GPR64common:%vreg235
	    Successors according to CFG: BB#11

1008B	BB#11: derived from LLVM BB %if.end.15
	    Predecessors according to CFG: BB#9 BB#10
1024B		STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
1040B		B <BB#69>
	    Successors according to CFG: BB#69

1056B	BB#12: derived from LLVM BB %if.end.16
	    Predecessors according to CFG: BB#6
1072B		%vreg37<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg37
1088B		%vreg34<def> = MOVi64imm 5012; GPR64:%vreg34
1104B		%vreg35<def> = ADDXrr %vreg37, %vreg34; GPR64common:%vreg35 GPR64:%vreg37,%vreg34
1120B		%vreg36<def> = LDRBBui %vreg35, 0; mem:LD1[%writing] GPR32:%vreg36 GPR64common:%vreg35
1136B		%vreg32<def> = UBFMWri %vreg36, 0, 7; GPR32:%vreg32,%vreg36
1152B		CBZW %vreg32, <BB#18>; GPR32:%vreg32
	    Successors according to CFG: BB#18 BB#13

1168B	BB#13: derived from LLVM BB %if.then.17
	    Predecessors according to CFG: BB#12
1184B		%vreg217<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg217
1200B		CBZX %vreg217, <BB#15>; GPR64:%vreg217
	    Successors according to CFG: BB#15 BB#14

1216B	BB#14: derived from LLVM BB %if.then.19
	    Predecessors according to CFG: BB#13
1248B		%vreg220<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg220
1256B		%vreg218<def> = MOVi32imm 4294967295; GPR32:%vreg218
1264B		STRWui %vreg218, %vreg220, 0; mem:ST4[%16] GPR32:%vreg218 GPR64common:%vreg220
	    Successors according to CFG: BB#15

1280B	BB#15: derived from LLVM BB %if.end.20
	    Predecessors according to CFG: BB#13 BB#14
1296B		%vreg222<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg222
1312B		CBZX %vreg222, <BB#17>; GPR64:%vreg222
	    Successors according to CFG: BB#17 BB#16

1328B	BB#16: derived from LLVM BB %if.then.22
	    Predecessors according to CFG: BB#15
1360B		%vreg225<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg225
1368B		%vreg223<def> = MOVi32imm 4294967295; GPR32:%vreg223
1376B		STRWui %vreg223, %vreg225, 1274; mem:ST4[%lastErr23] GPR32:%vreg223 GPR64common:%vreg225
	    Successors according to CFG: BB#17

1392B	BB#17: derived from LLVM BB %if.end.24
	    Predecessors according to CFG: BB#15 BB#16
1408B		STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
1424B		B <BB#69>
	    Successors according to CFG: BB#69

1440B	BB#18: derived from LLVM BB %if.end.25
	    Predecessors according to CFG: BB#12
1456B		%vreg39<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg39
1472B		CBNZW %vreg39, <BB#24>; GPR32:%vreg39
	    Successors according to CFG: BB#24 BB#19

1488B	BB#19: derived from LLVM BB %if.then.27
	    Predecessors according to CFG: BB#18
1504B		%vreg209<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg209
1520B		CBZX %vreg209, <BB#21>; GPR64:%vreg209
	    Successors according to CFG: BB#21 BB#20

1536B	BB#20: derived from LLVM BB %if.then.29
	    Predecessors according to CFG: BB#19
1552B		%vreg211<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg211
1568B		STRWui %WZR, %vreg211, 0; mem:ST4[%21] GPR64common:%vreg211
	    Successors according to CFG: BB#21

1584B	BB#21: derived from LLVM BB %if.end.30
	    Predecessors according to CFG: BB#19 BB#20
1600B		%vreg213<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg213
1616B		CBZX %vreg213, <BB#23>; GPR64:%vreg213
	    Successors according to CFG: BB#23 BB#22

1632B	BB#22: derived from LLVM BB %if.then.32
	    Predecessors according to CFG: BB#21
1648B		%vreg215<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg215
1664B		STRWui %WZR, %vreg215, 1274; mem:ST4[%lastErr33] GPR64common:%vreg215
	    Successors according to CFG: BB#23

1680B	BB#23: derived from LLVM BB %if.end.34
	    Predecessors according to CFG: BB#21 BB#22
1696B		STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
1712B		B <BB#69>
	    Successors according to CFG: BB#69

1728B	BB#24: derived from LLVM BB %if.end.35
	    Predecessors according to CFG: BB#18
1744B		%vreg47<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg47
1760B		%vreg46<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg46
1776B		STRWui %vreg47, %vreg46, 1262; mem:ST4[%avail_out] GPR32:%vreg47 GPR64common:%vreg46
1792B		%vreg43<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg43
1808B		%vreg42<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg42
1824B		STRXui %vreg43, %vreg42, 630; mem:ST8[%next_out] GPR64:%vreg43 GPR64common:%vreg42
	    Successors according to CFG: BB#25

1840B	BB#25: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#24 BB#68
1856B		%vreg53<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg53
1872B		%vreg52<def> = LDRXui %vreg53, 0; mem:LD8[%handle] GPR64:%vreg52 GPR64common:%vreg53
1888B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1904B		%X0<def> = COPY %vreg52; GPR64:%vreg52
1920B		BL <ga:@ferror>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
1936B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1952B		%vreg50<def> = COPY %W0; GPR32:%vreg50
1968B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1984B		STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
2000B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2016B		CBZW %vreg50, <BB#31>; GPR32:%vreg50
	    Successors according to CFG: BB#31 BB#26

2032B	BB#26: derived from LLVM BB %if.then.38
	    Predecessors according to CFG: BB#25
2048B		%vreg199<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg199
2064B		CBZX %vreg199, <BB#28>; GPR64:%vreg199
	    Successors according to CFG: BB#28 BB#27

2080B	BB#27: derived from LLVM BB %if.then.40
	    Predecessors according to CFG: BB#26
2112B		%vreg202<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg202
2120B		%vreg200<def> = MOVi32imm 4294967290; GPR32:%vreg200
2128B		STRWui %vreg200, %vreg202, 0; mem:ST4[%31] GPR32:%vreg200 GPR64common:%vreg202
	    Successors according to CFG: BB#28

2144B	BB#28: derived from LLVM BB %if.end.41
	    Predecessors according to CFG: BB#26 BB#27
2160B		%vreg204<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg204
2176B		CBZX %vreg204, <BB#30>; GPR64:%vreg204
	    Successors according to CFG: BB#30 BB#29

2192B	BB#29: derived from LLVM BB %if.then.43
	    Predecessors according to CFG: BB#28
2224B		%vreg207<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg207
2232B		%vreg205<def> = MOVi32imm 4294967290; GPR32:%vreg205
2240B		STRWui %vreg205, %vreg207, 1274; mem:ST4[%lastErr44] GPR32:%vreg205 GPR64common:%vreg207
	    Successors according to CFG: BB#30

2256B	BB#30: derived from LLVM BB %if.end.45
	    Predecessors according to CFG: BB#28 BB#29
2272B		STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
2288B		B <BB#69>
	    Successors according to CFG: BB#69

2304B	BB#31: derived from LLVM BB %if.end.46
	    Predecessors according to CFG: BB#25
2320B		%vreg57<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg57
2336B		%vreg56<def> = LDRWui %vreg57, 1256; mem:LD4[%avail_in] GPR32:%vreg56 GPR64common:%vreg57
2352B		CBNZW %vreg56, <BB#40>; GPR32:%vreg56
	    Successors according to CFG: BB#40 BB#32

2368B	BB#32: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#31
2384B		%vreg64<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg64
2400B		%vreg63<def> = LDRXui %vreg64, 0; mem:LD8[%handle49] GPR64:%vreg63 GPR64common:%vreg64
2416B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2432B		%X0<def> = COPY %vreg63; GPR64:%vreg63
2448B		BL <ga:@myfeof>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>
2464B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2480B		%vreg58<def> = COPY %W0; GPR32:%vreg58
2512B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2528B		STACKMAP 2, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
2544B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2560B		%vreg59<def> = UBFMWri %vreg58, 0, 7; GPR32:%vreg59,%vreg58
2576B		CBNZW %vreg59, <BB#40>; GPR32:%vreg59
	    Successors according to CFG: BB#40 BB#33

2592B	BB#33: derived from LLVM BB %if.then.52
	    Predecessors according to CFG: BB#32
2672B		%vreg81<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg81
2680B		%vreg85<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg85
2688B		%vreg80<def> = LDRXui %vreg81, 0; mem:LD8[%handle54] GPR64:%vreg80 GPR64common:%vreg81
2696B		%vreg84<def> = ADDXri %vreg85, 8, 0; GPR64sp:%vreg84 GPR64common:%vreg85
2704B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2712B		%X1<def> = MOVi64imm 1
2716B		%X2<def> = MOVi64imm 5000
2720B		%X0<def> = COPY %vreg84; GPR64sp:%vreg84
2768B		%X3<def> = COPY %vreg80; GPR64:%vreg80
2784B		BL <ga:@fread>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %X2<imp-use>, %X3<imp-use>, %X0<imp-def>
2800B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2816B		%vreg78<def> = COPY %X0; GPR64:%vreg78
2832B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2848B		STACKMAP 3, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
2864B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2896B		STRWui %vreg78:sub_32, <fi#5>, 0; mem:ST4[FixedStack5] GPR64:%vreg78
2912B		%vreg70<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg70
2928B		%vreg69<def> = LDRXui %vreg70, 0; mem:LD8[%handle56] GPR64:%vreg69 GPR64common:%vreg70
2944B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2960B		%X0<def> = COPY %vreg69; GPR64:%vreg69
2976B		BL <ga:@ferror>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
2992B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3008B		%vreg67<def> = COPY %W0; GPR32:%vreg67
3024B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3040B		STACKMAP 4, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
3056B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3072B		CBZW %vreg67, <BB#39>; GPR32:%vreg67
	    Successors according to CFG: BB#39 BB#34

3088B	BB#34: derived from LLVM BB %if.then.59
	    Predecessors according to CFG: BB#33
3104B		%vreg104<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg104
3120B		CBZX %vreg104, <BB#36>; GPR64:%vreg104
	    Successors according to CFG: BB#36 BB#35

3136B	BB#35: derived from LLVM BB %if.then.62
	    Predecessors according to CFG: BB#34
3168B		%vreg107<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg107
3176B		%vreg105<def> = MOVi32imm 4294967290; GPR32:%vreg105
3184B		STRWui %vreg105, %vreg107, 0; mem:ST4[%44] GPR32:%vreg105 GPR64common:%vreg107
	    Successors according to CFG: BB#36

3200B	BB#36: derived from LLVM BB %if.end.63
	    Predecessors according to CFG: BB#34 BB#35
3216B		%vreg109<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg109
3232B		CBZX %vreg109, <BB#38>; GPR64:%vreg109
	    Successors according to CFG: BB#38 BB#37

3248B	BB#37: derived from LLVM BB %if.then.66
	    Predecessors according to CFG: BB#36
3280B		%vreg112<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg112
3288B		%vreg110<def> = MOVi32imm 4294967290; GPR32:%vreg110
3296B		STRWui %vreg110, %vreg112, 1274; mem:ST4[%lastErr67] GPR32:%vreg110 GPR64common:%vreg112
	    Successors according to CFG: BB#38

3312B	BB#38: derived from LLVM BB %if.end.68
	    Predecessors according to CFG: BB#36 BB#37
3328B		STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
3344B		B <BB#69>
	    Successors according to CFG: BB#69

3360B	BB#39: derived from LLVM BB %if.end.69
	    Predecessors according to CFG: BB#33
3376B		%vreg102<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32:%vreg102
3392B		%vreg101<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg101
3408B		STRWui %vreg102, %vreg101, 1252; mem:ST4[%bufN] GPR32:%vreg102 GPR64common:%vreg101
3424B		%vreg98<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg98
3440B		%vreg97<def> = LDRWui %vreg98, 1252; mem:LD4[%bufN70] GPR32:%vreg97 GPR64common:%vreg98
3456B		%vreg95<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg95
3472B		STRWui %vreg97, %vreg95, 1256; mem:ST4[%avail_in72] GPR32:%vreg97 GPR64common:%vreg95
3488B		%vreg92<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg92
3520B		%vreg88<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg88
3528B		%vreg91<def> = ADDXri %vreg92, 8, 0; GPR64common:%vreg91,%vreg92
3536B		STRXui %vreg91, %vreg88, 627; mem:ST8[%next_in] GPR64common:%vreg91,%vreg88
	    Successors according to CFG: BB#40

3552B	BB#40: derived from LLVM BB %if.end.76
	    Predecessors according to CFG: BB#31 BB#32 BB#39
3568B		%vreg121<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg121
3584B		%vreg119<def> = MOVi64imm 5016; GPR64:%vreg119
3600B		%vreg120<def> = ADDXrr %vreg121, %vreg119; GPR64:%vreg120,%vreg121,%vreg119
3616B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3632B		%X0<def> = COPY %vreg120; GPR64:%vreg120
3648B		BL <ga:@BZ2_bzDecompress>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
3664B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3680B		%vreg117<def> = COPY %W0; GPR32:%vreg117
3696B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3712B		STACKMAP 5, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
3728B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3744B		STRWui %vreg117, <fi#6>, 0; mem:ST4[FixedStack6] GPR32:%vreg117
3760B		%vreg114<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg114
3776B		CBZW %vreg114, <BB#47>; GPR32:%vreg114
	    Successors according to CFG: BB#47 BB#41

3792B	BB#41: derived from LLVM BB %land.lhs.true.81
	    Predecessors according to CFG: BB#40
3808B		%vreg123<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32common:%vreg123
3824B		%WZR<def> = SUBSWri %vreg123, 4, 0, %NZCV<imp-def>; GPR32common:%vreg123
3840B		Bcc 0, <BB#47>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#47 BB#42

3856B	BB#42: derived from LLVM BB %if.then.84
	    Predecessors according to CFG: BB#41
3872B		%vreg187<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg187
3888B		CBZX %vreg187, <BB#44>; GPR64:%vreg187
	    Successors according to CFG: BB#44 BB#43

3904B	BB#43: derived from LLVM BB %if.then.87
	    Predecessors according to CFG: BB#42
3920B		%vreg191<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg191
3936B		%vreg190<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg190
3952B		STRWui %vreg191, %vreg190, 0; mem:ST4[%59] GPR32:%vreg191 GPR64common:%vreg190
	    Successors according to CFG: BB#44

3968B	BB#44: derived from LLVM BB %if.end.88
	    Predecessors according to CFG: BB#42 BB#43
3984B		%vreg193<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg193
4000B		CBZX %vreg193, <BB#46>; GPR64:%vreg193
	    Successors according to CFG: BB#46 BB#45

4016B	BB#45: derived from LLVM BB %if.then.91
	    Predecessors according to CFG: BB#44
4032B		%vreg197<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg197
4048B		%vreg196<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg196
4064B		STRWui %vreg197, %vreg196, 1274; mem:ST4[%lastErr92] GPR32:%vreg197 GPR64common:%vreg196
	    Successors according to CFG: BB#46

4080B	BB#46: derived from LLVM BB %if.end.93
	    Predecessors according to CFG: BB#44 BB#45
4096B		STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
4112B		B <BB#69>
	    Successors according to CFG: BB#69

4128B	BB#47: derived from LLVM BB %if.end.94
	    Predecessors according to CFG: BB#40 BB#41
4144B		%vreg125<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg125
4160B		CBNZW %vreg125, <BB#56>; GPR32:%vreg125
	    Successors according to CFG: BB#56 BB#48

4176B	BB#48: derived from LLVM BB %land.lhs.true.97
	    Predecessors according to CFG: BB#47
4192B		%vreg133<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg133
4208B		%vreg132<def> = LDRXui %vreg133, 0; mem:LD8[%handle98] GPR64:%vreg132 GPR64common:%vreg133
4224B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4240B		%X0<def> = COPY %vreg132; GPR64:%vreg132
4256B		BL <ga:@myfeof>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>
4272B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4288B		%vreg127<def> = COPY %W0; GPR32:%vreg127
4320B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4336B		STACKMAP 6, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
4352B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4368B		%vreg128<def> = UBFMWri %vreg127, 0, 7; GPR32:%vreg128,%vreg127
4384B		CBZW %vreg128, <BB#56>; GPR32:%vreg128
	    Successors according to CFG: BB#56 BB#49

4400B	BB#49: derived from LLVM BB %land.lhs.true.102
	    Predecessors according to CFG: BB#48
4416B		%vreg137<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg137
4432B		%vreg136<def> = LDRWui %vreg137, 1256; mem:LD4[%avail_in104] GPR32:%vreg136 GPR64common:%vreg137
4448B		CBNZW %vreg136, <BB#56>; GPR32:%vreg136
	    Successors according to CFG: BB#56 BB#50

4464B	BB#50: derived from LLVM BB %land.lhs.true.107
	    Predecessors according to CFG: BB#49
4480B		%vreg141<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg141
4496B		%vreg140<def> = LDRWui %vreg141, 1262; mem:LD4[%avail_out109] GPR32common:%vreg140 GPR64common:%vreg141
4512B		%WZR<def> = SUBSWri %vreg140, 0, 0, %NZCV<imp-def>; GPR32common:%vreg140
4528B		Bcc 9, <BB#56>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#56 BB#51

4544B	BB#51: derived from LLVM BB %if.then.112
	    Predecessors according to CFG: BB#50
4560B		%vreg177<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg177
4576B		CBZX %vreg177, <BB#53>; GPR64:%vreg177
	    Successors according to CFG: BB#53 BB#52

4592B	BB#52: derived from LLVM BB %if.then.115
	    Predecessors according to CFG: BB#51
4624B		%vreg180<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg180
4632B		%vreg178<def> = MOVi32imm 4294967289; GPR32:%vreg178
4640B		STRWui %vreg178, %vreg180, 0; mem:ST4[%71] GPR32:%vreg178 GPR64common:%vreg180
	    Successors according to CFG: BB#53

4656B	BB#53: derived from LLVM BB %if.end.116
	    Predecessors according to CFG: BB#51 BB#52
4672B		%vreg182<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg182
4688B		CBZX %vreg182, <BB#55>; GPR64:%vreg182
	    Successors according to CFG: BB#55 BB#54

4704B	BB#54: derived from LLVM BB %if.then.119
	    Predecessors according to CFG: BB#53
4736B		%vreg185<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg185
4744B		%vreg183<def> = MOVi32imm 4294967289; GPR32:%vreg183
4752B		STRWui %vreg183, %vreg185, 1274; mem:ST4[%lastErr120] GPR32:%vreg183 GPR64common:%vreg185
	    Successors according to CFG: BB#55

4768B	BB#55: derived from LLVM BB %if.end.121
	    Predecessors according to CFG: BB#53 BB#54
4784B		STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
4800B		B <BB#69>
	    Successors according to CFG: BB#69

4816B	BB#56: derived from LLVM BB %if.end.122
	    Predecessors according to CFG: BB#47 BB#48 BB#49 BB#50
4832B		%vreg143<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32common:%vreg143
4848B		%WZR<def> = SUBSWri %vreg143, 4, 0, %NZCV<imp-def>; GPR32common:%vreg143
4864B		Bcc 1, <BB#62>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#62 BB#57

4880B	BB#57: derived from LLVM BB %if.then.125
	    Predecessors according to CFG: BB#56
4896B		%vreg159<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg159
4912B		CBZX %vreg159, <BB#59>; GPR64:%vreg159
	    Successors according to CFG: BB#59 BB#58

4928B	BB#58: derived from LLVM BB %if.then.128
	    Predecessors according to CFG: BB#57
4960B		%vreg162<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg162
4968B		%vreg160<def> = MOVi32imm 4; GPR32:%vreg160
4976B		STRWui %vreg160, %vreg162, 0; mem:ST4[%76] GPR32:%vreg160 GPR64common:%vreg162
	    Successors according to CFG: BB#59

4992B	BB#59: derived from LLVM BB %if.end.129
	    Predecessors according to CFG: BB#57 BB#58
5008B		%vreg164<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg164
5024B		CBZX %vreg164, <BB#61>; GPR64:%vreg164
	    Successors according to CFG: BB#61 BB#60

5040B	BB#60: derived from LLVM BB %if.then.132
	    Predecessors according to CFG: BB#59
5072B		%vreg167<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg167
5080B		%vreg165<def> = MOVi32imm 4; GPR32:%vreg165
5088B		STRWui %vreg165, %vreg167, 1274; mem:ST4[%lastErr133] GPR32:%vreg165 GPR64common:%vreg167
	    Successors according to CFG: BB#61

5104B	BB#61: derived from LLVM BB %if.end.134
	    Predecessors according to CFG: BB#59 BB#60
5136B		%vreg174<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg174
5144B		%vreg175<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg175
5152B		%vreg173<def> = LDRWui %vreg174, 1262; mem:LD4[%avail_out136] GPR32:%vreg173 GPR64common:%vreg174
5168B		%vreg171<def> = SUBWrr %vreg175, %vreg173; GPR32:%vreg171,%vreg175,%vreg173
5184B		STRWui %vreg171, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg171
5200B		B <BB#69>
	    Successors according to CFG: BB#69

5216B	BB#62: derived from LLVM BB %if.end.137
	    Predecessors according to CFG: BB#56
5232B		%vreg147<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg147
5248B		%vreg146<def> = LDRWui %vreg147, 1262; mem:LD4[%avail_out139] GPR32:%vreg146 GPR64common:%vreg147
5264B		CBNZW %vreg146, <BB#68>; GPR32:%vreg146
	    Successors according to CFG: BB#68 BB#63

5280B	BB#63: derived from LLVM BB %if.then.142
	    Predecessors according to CFG: BB#62
5296B		%vreg149<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg149
5312B		CBZX %vreg149, <BB#65>; GPR64:%vreg149
	    Successors according to CFG: BB#65 BB#64

5328B	BB#64: derived from LLVM BB %if.then.145
	    Predecessors according to CFG: BB#63
5344B		%vreg151<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg151
5360B		STRWui %WZR, %vreg151, 0; mem:ST4[%85] GPR64common:%vreg151
	    Successors according to CFG: BB#65

5376B	BB#65: derived from LLVM BB %if.end.146
	    Predecessors according to CFG: BB#63 BB#64
5392B		%vreg153<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg153
5408B		CBZX %vreg153, <BB#67>; GPR64:%vreg153
	    Successors according to CFG: BB#67 BB#66

5424B	BB#66: derived from LLVM BB %if.then.149
	    Predecessors according to CFG: BB#65
5440B		%vreg155<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg155
5456B		STRWui %WZR, %vreg155, 1274; mem:ST4[%lastErr150] GPR64common:%vreg155
	    Successors according to CFG: BB#67

5472B	BB#67: derived from LLVM BB %if.end.151
	    Predecessors according to CFG: BB#65 BB#66
5488B		%vreg157<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg157
5504B		STRWui %vreg157, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg157
5520B		B <BB#69>
	    Successors according to CFG: BB#69

5536B	BB#68: derived from LLVM BB %if.end.152
	    Predecessors according to CFG: BB#62
5552B		B <BB#25>
	    Successors according to CFG: BB#25

5568B	BB#69: derived from LLVM BB %return
	    Predecessors according to CFG: BB#38 BB#67 BB#61 BB#55 BB#46 BB#30 BB#23 BB#17 BB#11
5584B		%vreg238<def> = ADRP <ga:@BZ2_bzRead>[TF=1]; GPR64common:%vreg238
5600B		%vreg240<def> = ADDXri %vreg238, <ga:@BZ2_bzRead>[TF=34], 0; GPR64sp:%vreg240 GPR64common:%vreg238
5648B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5664B		%X0<def> = COPY %vreg240; GPR64sp:%vreg240
5680B		%X1<def> = COPY %vreg17; GPR64:%vreg17
5696B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
5712B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5728B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5744B		STACKMAP 7, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
5760B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5776B		%vreg237<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0] GPR32:%vreg237
5792B		%W0<def> = COPY %vreg237; GPR32:%vreg237
5808B		RET_ReallyLR %W0<imp-use>

# End machine code for function BZ2_bzRead.


selectOrSplit GPR64:%vreg17 [16r,5680r:0)  0@16r w=4.996702e-04
hints: %X1
missed hint %X1
Analyze counted 3 instrs in 2 blocks, through 68 blocks.
%X1	static = 1.0 worse than no bundles
%X8	static = 1.0 worse than no bundles
%X9	static = 1.0 worse than no bundles
%X10	static = 1.0 worse than no bundles
%X11	static = 1.0 worse than no bundles
%X12	static = 1.0 worse than no bundles
%X13	static = 1.0 worse than no bundles
%X14	static = 1.0 worse than no bundles
%X15	static = 1.0 worse than no bundles
%X16	static = 1.0 worse than no bundles
%X17	static = 1.0 worse than no bundles
%X18	static = 1.0 worse than no bundles
%X0	no positive bundles
%X2	static = 1.0 worse than no bundles
%X3	static = 1.0 worse than no bundles
%X4	static = 1.0 worse than no bundles
%X5	static = 1.0 worse than no bundles
%X6	static = 1.0 worse than no bundles
%X7	static = 1.0 worse than no bundles
assigning %vreg17 to %X19: W19 [16r,5680r:0)  0@16r

selectOrSplit GPR32:%vreg7 [32r,400r:0)  0@32r w=3.945312e-03
hints: %W3
missed hint %W3
Analyze counted 3 instrs in 1 blocks, through 0 blocks.
%W3	no positive bundles
%W8	no positive bundles
%W9	no positive bundles
%W10	no positive bundles
%W11	no positive bundles
%W12	no positive bundles
%W13	no positive bundles
%W14	no positive bundles
%W15	no positive bundles
%W16	no positive bundles
%W17	no positive bundles
%W18	no positive bundles
%W0	no positive bundles
%W1	no positive bundles
%W2	no positive bundles
%W4	no positive bundles
%W5	no positive bundles
%W6	no positive bundles
%W7	no positive bundles
%W19	no positive bundles
assigning %vreg7 to %W20: W20 [32r,400r:0)  0@32r

selectOrSplit GPR64:%vreg5 [48r,384r:0)  0@48r w=4.116848e-03
hints: %X2
missed hint %X2
Analyze counted 3 instrs in 1 blocks, through 0 blocks.
%X2	no positive bundles
%X8	no positive bundles
%X9	no positive bundles
%X10	no positive bundles
%X11	no positive bundles
%X12	no positive bundles
%X13	no positive bundles
%X14	no positive bundles
%X15	no positive bundles
%X16	no positive bundles
%X17	no positive bundles
%X18	no positive bundles
%X0	no positive bundles
%X1	no positive bundles
%X3	no positive bundles
%X4	no positive bundles
%X5	no positive bundles
%X6	no positive bundles
%X7	no positive bundles
%X19	no positive bundles
%X20	no positive bundles
assigning %vreg5 to %X21: W21 [48r,384r:0)  0@48r

selectOrSplit GPR64:%vreg3 [64r,368r:0)  0@64r w=4.303977e-03
hints: %X1
missed hint %X1
Analyze counted 3 instrs in 1 blocks, through 0 blocks.
%X1	no positive bundles
%X8	no positive bundles
%X9	no positive bundles
%X10	no positive bundles
%X11	no positive bundles
%X12	no positive bundles
%X13	no positive bundles
%X14	no positive bundles
%X15	no positive bundles
%X16	no positive bundles
%X17	no positive bundles
%X18	no positive bundles
%X0	no positive bundles
%X2	no positive bundles
%X3	no positive bundles
%X4	no positive bundles
%X5	no positive bundles
%X6	no positive bundles
%X7	no positive bundles
%X19	no positive bundles
%X20	no positive bundles
%X21	no positive bundles
assigning %vreg3 to %X22: W22 [64r,368r:0)  0@64r

selectOrSplit GPR64:%vreg1 [80r,352r:0)  0@80r w=4.508928e-03
hints: %X0
missed hint %X0
Analyze counted 3 instrs in 1 blocks, through 0 blocks.
%X0	no positive bundles
%X8	no positive bundles
%X9	no positive bundles
%X10	no positive bundles
%X11	no positive bundles
%X12	no positive bundles
%X13	no positive bundles
%X14	no positive bundles
%X15	no positive bundles
%X16	no positive bundles
%X17	no positive bundles
%X18	no positive bundles
%X1	no positive bundles
%X2	no positive bundles
%X3	no positive bundles
%X4	no positive bundles
%X5	no positive bundles
%X6	no positive bundles
%X7	no positive bundles
%X19	no positive bundles
%X20	no positive bundles
%X21	no positive bundles
%X22	no positive bundles
assigning %vreg1 to %X23: W23 [80r,352r:0)  0@80r

selectOrSplit GPR64sp:%vreg16 [176r,240r:0)  0@176r w=4.353448e-03
hints: %X0
assigning %vreg16 to %X0: W0 [176r,240r:0)  0@176r

selectOrSplit GPR64:%vreg52 [1872r,1904r:0)  0@1872r w=1.582584e-04
hints: %X0
assigning %vreg52 to %X0: W0 [1872r,1904r:0)  0@1872r

selectOrSplit GPR32:%vreg50 [1952r,2016r:0)  0@1952r w=1.473440e-04
hints: %W0
assigning %vreg50 to %W0: W0 [1952r,2016r:0)  0@1952r

selectOrSplit GPR64:%vreg63 [2400r,2432r:0)  0@2400r w=3.956459e-05
hints: %X0
assigning %vreg63 to %X0: W0 [2400r,2432r:0)  0@2400r

selectOrSplit GPR32:%vreg58 [2480r,2560r:0)  0@2480r w=3.560813e-05
hints: %W0
assigning %vreg58 to %W0: W0 [2480r,2560r:0)  0@2480r

selectOrSplit GPR64:%vreg80 [2688r,2768r:0)  0@2688r w=1.771276e-05
hints: %X3
assigning %vreg80 to %X3: W3 [2688r,2768r:0)  0@2688r

selectOrSplit GPR64sp:%vreg84 [2696r,2720r:0)  0@2696r w=2.005219e-05
hints: %X0
assigning %vreg84 to %X0: W0 [2696r,2720r:0)  0@2696r

selectOrSplit GPR64:%vreg78 [2816r,2896r:0)  0@2816r w=1.771276e-05
hints: %X0
assigning %vreg78 to %X0: W0 [2816r,2896r:0)  0@2816r

selectOrSplit GPR64:%vreg69 [2928r,2960r:0)  0@2928r w=1.968085e-05
hints: %X0
assigning %vreg69 to %X0: W0 [2928r,2960r:0)  0@2928r

selectOrSplit GPR32:%vreg67 [3008r,3072r:0)  0@3008r w=1.832355e-05
hints: %W0
assigning %vreg67 to %W0: W0 [3008r,3072r:0)  0@3008r

selectOrSplit GPR64:%vreg120 [3600r,3632r:0)  0@3600r w=6.918731e-05
hints: %X0
assigning %vreg120 to %X0: W0 [3600r,3632r:0)  0@3600r

selectOrSplit GPR32:%vreg117 [3680r,3744r:0)  0@3680r w=6.441577e-05
hints: %W0
assigning %vreg117 to %W0: W0 [3680r,3744r:0)  0@3680r

selectOrSplit GPR64:%vreg132 [4208r,4240r:0)  0@4208r w=2.576771e-05
hints: %X0
assigning %vreg132 to %X0: W0 [4208r,4240r:0)  0@4208r

selectOrSplit GPR32:%vreg127 [4288r,4368r:0)  0@4288r w=2.319094e-05
hints: %W0
assigning %vreg127 to %W0: W0 [4288r,4368r:0)  0@4288r

selectOrSplit GPR64sp:%vreg240 [5600r,5664r:0)  0@5600r w=4.353448e-03
hints: %X0
assigning %vreg240 to %X0: W0 [5600r,5664r:0)  0@5600r

selectOrSplit GPR32:%vreg237 [5776r,5792r:0)  0@5776r w=inf
hints: %W0
assigning %vreg237 to %W0: W0 [5776r,5792r:0)  0@5776r

selectOrSplit GPR64common:%vreg14 [160r,176r:0)  0@160r w=inf
assigning %vreg14 to %X8: W8 [160r,176r:0)  0@160r

selectOrSplit GPR64:%vreg12 [416r,448r:0)  0@416r w=inf
assigning %vreg12 to %X8: W8 [416r,448r:0)  0@416r

selectOrSplit GPR64:%vreg9 [464r,480r:0)  0@464r w=inf
assigning %vreg9 to %X8: W8 [464r,480r:0)  0@464r

selectOrSplit GPR64common:%vreg20 [512r,528r:0)  0@512r w=inf
assigning %vreg20 to %X8: W8 [512r,528r:0)  0@512r

selectOrSplit GPR64:%vreg22 [560r,576r:0)  0@560r w=inf
assigning %vreg22 to %X8: W8 [560r,576r:0)  0@560r

selectOrSplit GPR64common:%vreg24 [608r,624r:0)  0@608r w=inf
assigning %vreg24 to %X8: W8 [608r,624r:0)  0@608r

selectOrSplit GPR64:%vreg26 [656r,672r:0)  0@656r w=inf
assigning %vreg26 to %X8: W8 [656r,672r:0)  0@656r

selectOrSplit GPR64:%vreg28 [704r,720r:0)  0@704r w=inf
assigning %vreg28 to %X8: W8 [704r,720r:0)  0@704r

selectOrSplit GPR32:%vreg30 [752r,768r:0)  0@752r w=inf
assigning %vreg30 to %W8: W8 [752r,768r:0)  0@752r

selectOrSplit GPR64:%vreg227 [800r,816r:0)  0@800r w=inf
assigning %vreg227 to %X8: W8 [800r,816r:0)  0@800r

selectOrSplit GPR64common:%vreg230 [864r,880r:0)  0@864r w=2.103235e-03
assigning %vreg230 to %X8: W8 [864r,880r:0)  0@864r

selectOrSplit GPR32:%vreg228 [872r,880r:0)  0@872r w=inf
assigning %vreg228 to %W9: W9 [872r,880r:0)  0@872r

selectOrSplit GPR64:%vreg232 [912r,928r:0)  0@912r w=inf
assigning %vreg232 to %X8: W8 [912r,928r:0)  0@912r

selectOrSplit GPR64common:%vreg235 [976r,992r:0)  0@976r w=2.103235e-03
assigning %vreg235 to %X8: W8 [976r,992r:0)  0@976r

selectOrSplit GPR32:%vreg233 [984r,992r:0)  0@984r w=inf
assigning %vreg233 to %W9: W9 [984r,992r:0)  0@984r

selectOrSplit GPR64:%vreg37 [1072r,1104r:0)  0@1072r w=5.785531e-04
assigning %vreg37 to %X8: W8 [1072r,1104r:0)  0@1072r

selectOrSplit GPR64:%vreg34 [1088r,1104r:0)  0@1088r w=inf
assigning %vreg34 to %X9: W9 [1088r,1104r:0)  0@1088r

selectOrSplit GPR64common:%vreg35 [1104r,1120r:0)  0@1104r w=inf
assigning %vreg35 to %X8: W8 [1104r,1120r:0)  0@1104r

selectOrSplit GPR32:%vreg36 [1120r,1136r:0)  0@1120r w=inf
assigning %vreg36 to %W8: W8 [1120r,1136r:0)  0@1120r

selectOrSplit GPR32:%vreg32 [1136r,1152r:0)  0@1136r w=inf
assigning %vreg32 to %W8: W8 [1136r,1152r:0)  0@1136r

selectOrSplit GPR64:%vreg217 [1184r,1200r:0)  0@1184r w=inf
assigning %vreg217 to %X8: W8 [1184r,1200r:0)  0@1184r

selectOrSplit GPR64common:%vreg220 [1248r,1264r:0)  0@1248r w=1.502013e-04
assigning %vreg220 to %X8: W8 [1248r,1264r:0)  0@1248r

selectOrSplit GPR32:%vreg218 [1256r,1264r:0)  0@1256r w=inf
assigning %vreg218 to %W9: W9 [1256r,1264r:0)  0@1256r

selectOrSplit GPR64:%vreg222 [1296r,1312r:0)  0@1296r w=inf
assigning %vreg222 to %X8: W8 [1296r,1312r:0)  0@1296r

selectOrSplit GPR64common:%vreg225 [1360r,1376r:0)  0@1360r w=1.502013e-04
assigning %vreg225 to %X8: W8 [1360r,1376r:0)  0@1360r

selectOrSplit GPR32:%vreg223 [1368r,1376r:0)  0@1368r w=inf
assigning %vreg223 to %W9: W9 [1368r,1376r:0)  0@1368r

selectOrSplit GPR32:%vreg39 [1456r,1472r:0)  0@1456r w=inf
assigning %vreg39 to %W8: W8 [1456r,1472r:0)  0@1456r

selectOrSplit GPR64:%vreg209 [1504r,1520r:0)  0@1504r w=inf
assigning %vreg209 to %X8: W8 [1504r,1520r:0)  0@1504r

selectOrSplit GPR64common:%vreg211 [1552r,1568r:0)  0@1552r w=inf
assigning %vreg211 to %X8: W8 [1552r,1568r:0)  0@1552r

selectOrSplit GPR64:%vreg213 [1600r,1616r:0)  0@1600r w=inf
assigning %vreg213 to %X8: W8 [1600r,1616r:0)  0@1600r

selectOrSplit GPR64common:%vreg215 [1648r,1664r:0)  0@1648r w=inf
assigning %vreg215 to %X8: W8 [1648r,1664r:0)  0@1648r

selectOrSplit GPR32:%vreg47 [1744r,1776r:0)  0@1744r w=1.446383e-04
assigning %vreg47 to %W8: W8 [1744r,1776r:0)  0@1744r

selectOrSplit GPR64common:%vreg46 [1760r,1776r:0)  0@1760r w=inf
assigning %vreg46 to %X9: W9 [1760r,1776r:0)  0@1760r

selectOrSplit GPR64:%vreg43 [1792r,1824r:0)  0@1792r w=1.446383e-04
assigning %vreg43 to %X8: W8 [1792r,1824r:0)  0@1792r

selectOrSplit GPR64common:%vreg42 [1808r,1824r:0)  0@1808r w=inf
assigning %vreg42 to %X9: W9 [1808r,1824r:0)  0@1808r

selectOrSplit GPR64common:%vreg53 [1856r,1872r:0)  0@1856r w=inf
assigning %vreg53 to %X8: W8 [1856r,1872r:0)  0@1856r

selectOrSplit GPR64:%vreg199 [2048r,2064r:0)  0@2048r w=inf
assigning %vreg199 to %X8: W8 [2048r,2064r:0)  0@2048r

selectOrSplit GPR64common:%vreg202 [2112r,2128r:0)  0@2112r w=4.067951e-05
assigning %vreg202 to %X8: W8 [2112r,2128r:0)  0@2112r

selectOrSplit GPR32:%vreg200 [2120r,2128r:0)  0@2120r w=inf
assigning %vreg200 to %W9: W9 [2120r,2128r:0)  0@2120r

selectOrSplit GPR64:%vreg204 [2160r,2176r:0)  0@2160r w=inf
assigning %vreg204 to %X8: W8 [2160r,2176r:0)  0@2160r

selectOrSplit GPR64common:%vreg207 [2224r,2240r:0)  0@2224r w=4.067951e-05
assigning %vreg207 to %X8: W8 [2224r,2240r:0)  0@2224r

selectOrSplit GPR32:%vreg205 [2232r,2240r:0)  0@2232r w=inf
assigning %vreg205 to %W9: W9 [2232r,2240r:0)  0@2232r

selectOrSplit GPR64common:%vreg57 [2320r,2336r:0)  0@2320r w=inf
assigning %vreg57 to %X8: W8 [2320r,2336r:0)  0@2320r

selectOrSplit GPR32:%vreg56 [2336r,2352r:0)  0@2336r w=inf
assigning %vreg56 to %W8: W8 [2336r,2352r:0)  0@2336r

selectOrSplit GPR64common:%vreg64 [2384r,2400r:0)  0@2384r w=inf
assigning %vreg64 to %X8: W8 [2384r,2400r:0)  0@2384r

selectOrSplit GPR32:%vreg59 [2560r,2576r:0)  0@2560r w=inf
assigning %vreg59 to %W8: W8 [2560r,2576r:0)  0@2560r

selectOrSplit GPR64common:%vreg81 [2672r,2688r:0)  0@2672r w=2.023545e-05
assigning %vreg81 to %X8: W8 [2672r,2688r:0)  0@2672r

selectOrSplit GPR64common:%vreg85 [2680r,2696r:0)  0@2680r w=2.023545e-05
assigning %vreg85 to %X9: W9 [2680r,2696r:0)  0@2680r

selectOrSplit GPR64common:%vreg70 [2912r,2928r:0)  0@2912r w=inf
assigning %vreg70 to %X8: W8 [2912r,2928r:0)  0@2912r

selectOrSplit GPR64:%vreg104 [3104r,3120r:0)  0@3104r w=inf
assigning %vreg104 to %X8: W8 [3104r,3120r:0)  0@3104r

selectOrSplit GPR64common:%vreg107 [3168r,3184r:0)  0@3168r w=5.006709e-06
assigning %vreg107 to %X8: W8 [3168r,3184r:0)  0@3168r

selectOrSplit GPR32:%vreg105 [3176r,3184r:0)  0@3176r w=inf
assigning %vreg105 to %W9: W9 [3176r,3184r:0)  0@3176r

selectOrSplit GPR64:%vreg109 [3216r,3232r:0)  0@3216r w=inf
assigning %vreg109 to %X8: W8 [3216r,3232r:0)  0@3216r

selectOrSplit GPR64common:%vreg112 [3280r,3296r:0)  0@3280r w=5.006709e-06
assigning %vreg112 to %X8: W8 [3280r,3296r:0)  0@3280r

selectOrSplit GPR32:%vreg110 [3288r,3296r:0)  0@3288r w=inf
assigning %vreg110 to %W9: W9 [3288r,3296r:0)  0@3288r

selectOrSplit GPR32:%vreg102 [3376r,3408r:0)  0@3376r w=9.642551e-06
assigning %vreg102 to %W8: W8 [3376r,3408r:0)  0@3376r

selectOrSplit GPR64common:%vreg101 [3392r,3408r:0)  0@3392r w=inf
assigning %vreg101 to %X9: W9 [3392r,3408r:0)  0@3392r

selectOrSplit GPR64common:%vreg98 [3424r,3440r:0)  0@3424r w=inf
assigning %vreg98 to %X8: W8 [3424r,3440r:0)  0@3424r

selectOrSplit GPR32:%vreg97 [3440r,3472r:0)  0@3440r w=9.642551e-06
assigning %vreg97 to %W8: W8 [3440r,3472r:0)  0@3440r

selectOrSplit GPR64common:%vreg95 [3456r,3472r:0)  0@3456r w=inf
assigning %vreg95 to %X9: W9 [3456r,3472r:0)  0@3456r

selectOrSplit GPR64common:%vreg92 [3488r,3528r:0)  0@3488r w=9.467231e-06
assigning %vreg92 to %X8: W8 [3488r,3528r:0)  0@3488r

selectOrSplit GPR64common:%vreg88 [3520r,3536r:0)  0@3520r w=1.001342e-05
assigning %vreg88 to %X9: W9 [3520r,3536r:0)  0@3520r

selectOrSplit GPR64common:%vreg91 [3528r,3536r:0)  0@3528r w=inf
assigning %vreg91 to %X8: W8 [3528r,3536r:0)  0@3528r

selectOrSplit GPR64:%vreg121 [3568r,3600r:0)  0@3568r w=6.850229e-05
assigning %vreg121 to %X8: W8 [3568r,3600r:0)  0@3568r

selectOrSplit GPR64:%vreg119 [3584r,3600r:0)  0@3584r w=inf
assigning %vreg119 to %X9: W9 [3584r,3600r:0)  0@3584r

selectOrSplit GPR32:%vreg114 [3760r,3776r:0)  0@3760r w=inf
assigning %vreg114 to %W8: W8 [3760r,3776r:0)  0@3760r

selectOrSplit GPR32common:%vreg123 [3808r,3824r:0)  0@3808r w=inf
assigning %vreg123 to %W8: W8 [3808r,3824r:0)  0@3808r

selectOrSplit GPR64:%vreg187 [3872r,3888r:0)  0@3872r w=inf
assigning %vreg187 to %X8: W8 [3872r,3888r:0)  0@3872r

selectOrSplit GPR32:%vreg191 [3920r,3952r:0)  0@3920r w=8.437232e-06
assigning %vreg191 to %W8: W8 [3920r,3952r:0)  0@3920r

selectOrSplit GPR64common:%vreg190 [3936r,3952r:0)  0@3936r w=inf
assigning %vreg190 to %X9: W9 [3936r,3952r:0)  0@3936r

selectOrSplit GPR64:%vreg193 [3984r,4000r:0)  0@3984r w=inf
assigning %vreg193 to %X8: W8 [3984r,4000r:0)  0@3984r

selectOrSplit GPR32:%vreg197 [4032r,4064r:0)  0@4032r w=8.437232e-06
assigning %vreg197 to %W8: W8 [4032r,4064r:0)  0@4032r

selectOrSplit GPR64common:%vreg196 [4048r,4064r:0)  0@4048r w=inf
assigning %vreg196 to %X9: W9 [4048r,4064r:0)  0@4048r

selectOrSplit GPR32:%vreg125 [4144r,4160r:0)  0@4144r w=inf
assigning %vreg125 to %W8: W8 [4144r,4160r:0)  0@4144r

selectOrSplit GPR64common:%vreg133 [4192r,4208r:0)  0@4192r w=inf
assigning %vreg133 to %X8: W8 [4192r,4208r:0)  0@4192r

selectOrSplit GPR32:%vreg128 [4368r,4384r:0)  0@4368r w=inf
assigning %vreg128 to %W8: W8 [4368r,4384r:0)  0@4368r

selectOrSplit GPR64common:%vreg137 [4416r,4432r:0)  0@4416r w=inf
assigning %vreg137 to %X8: W8 [4416r,4432r:0)  0@4416r

selectOrSplit GPR32:%vreg136 [4432r,4448r:0)  0@4432r w=inf
assigning %vreg136 to %W8: W8 [4432r,4448r:0)  0@4432r

selectOrSplit GPR64common:%vreg141 [4480r,4496r:0)  0@4480r w=inf
assigning %vreg141 to %X8: W8 [4480r,4496r:0)  0@4480r

selectOrSplit GPR32common:%vreg140 [4496r,4512r:0)  0@4496r w=inf
assigning %vreg140 to %W8: W8 [4496r,4512r:0)  0@4496r

selectOrSplit GPR64:%vreg177 [4560r,4576r:0)  0@4560r w=inf
assigning %vreg177 to %X8: W8 [4560r,4576r:0)  0@4560r

selectOrSplit GPR64common:%vreg180 [4624r,4640r:0)  0@4624r w=1.668903e-06
assigning %vreg180 to %X8: W8 [4624r,4640r:0)  0@4624r

selectOrSplit GPR32:%vreg178 [4632r,4640r:0)  0@4632r w=inf
assigning %vreg178 to %W9: W9 [4632r,4640r:0)  0@4632r

selectOrSplit GPR64:%vreg182 [4672r,4688r:0)  0@4672r w=inf
assigning %vreg182 to %X8: W8 [4672r,4688r:0)  0@4672r

selectOrSplit GPR64common:%vreg185 [4736r,4752r:0)  0@4736r w=1.668903e-06
assigning %vreg185 to %X8: W8 [4736r,4752r:0)  0@4736r

selectOrSplit GPR32:%vreg183 [4744r,4752r:0)  0@4744r w=inf
assigning %vreg183 to %W9: W9 [4744r,4752r:0)  0@4744r

selectOrSplit GPR32common:%vreg143 [4832r,4848r:0)  0@4832r w=inf
assigning %vreg143 to %W8: W8 [4832r,4848r:0)  0@4832r

selectOrSplit GPR64:%vreg159 [4896r,4912r:0)  0@4896r w=inf
assigning %vreg159 to %X8: W8 [4896r,4912r:0)  0@4896r

selectOrSplit GPR64common:%vreg162 [4960r,4976r:0)  0@4960r w=1.251677e-05
assigning %vreg162 to %X8: W8 [4960r,4976r:0)  0@4960r

selectOrSplit GPR32:%vreg160 [4968r,4976r:0)  0@4968r w=inf
assigning %vreg160 to %W9: W9 [4968r,4976r:0)  0@4968r

selectOrSplit GPR64:%vreg164 [5008r,5024r:0)  0@5008r w=inf
assigning %vreg164 to %X8: W8 [5008r,5024r:0)  0@5008r

selectOrSplit GPR64common:%vreg167 [5072r,5088r:0)  0@5072r w=1.251677e-05
assigning %vreg167 to %X8: W8 [5072r,5088r:0)  0@5072r

selectOrSplit GPR32:%vreg165 [5080r,5088r:0)  0@5080r w=inf
assigning %vreg165 to %W9: W9 [5080r,5088r:0)  0@5080r

selectOrSplit GPR64common:%vreg174 [5136r,5152r:0)  0@5136r w=2.482493e-05
assigning %vreg174 to %X8: W8 [5136r,5152r:0)  0@5136r

selectOrSplit GPR32:%vreg175 [5144r,5168r:0)  0@5144r w=2.435654e-05
assigning %vreg175 to %W9: W9 [5144r,5168r:0)  0@5144r

selectOrSplit GPR32:%vreg173 [5152r,5168r:0)  0@5152r w=inf
assigning %vreg173 to %W8: W8 [5152r,5168r:0)  0@5152r

selectOrSplit GPR32:%vreg171 [5168r,5184r:0)  0@5168r w=inf
assigning %vreg171 to %W8: W8 [5168r,5184r:0)  0@5168r

selectOrSplit GPR64common:%vreg147 [5232r,5248r:0)  0@5232r w=inf
assigning %vreg147 to %X8: W8 [5232r,5248r:0)  0@5232r

selectOrSplit GPR32:%vreg146 [5248r,5264r:0)  0@5248r w=inf
assigning %vreg146 to %W8: W8 [5248r,5264r:0)  0@5248r

selectOrSplit GPR64:%vreg149 [5296r,5312r:0)  0@5296r w=inf
assigning %vreg149 to %X8: W8 [5296r,5312r:0)  0@5296r

selectOrSplit GPR64common:%vreg151 [5344r,5360r:0)  0@5344r w=inf
assigning %vreg151 to %X8: W8 [5344r,5360r:0)  0@5344r

selectOrSplit GPR64:%vreg153 [5392r,5408r:0)  0@5392r w=inf
assigning %vreg153 to %X8: W8 [5392r,5408r:0)  0@5392r

selectOrSplit GPR64common:%vreg155 [5440r,5456r:0)  0@5440r w=inf
assigning %vreg155 to %X8: W8 [5440r,5456r:0)  0@5440r

selectOrSplit GPR32:%vreg157 [5488r,5504r:0)  0@5488r w=inf
assigning %vreg157 to %W8: W8 [5488r,5504r:0)  0@5488r

selectOrSplit GPR64common:%vreg238 [5584r,5600r:0)  0@5584r w=inf
assigning %vreg238 to %X8: W8 [5584r,5600r:0)  0@5584r

********** STACK TRANSFORMATION METADATA **********
********** Function: BZ2_bzRead
********** REGISTER MAP **********
[%vreg1 -> %X23] GPR64
[%vreg3 -> %X22] GPR64
[%vreg5 -> %X21] GPR64
[%vreg7 -> %W20] GPR32
[%vreg9 -> %X8] GPR64
[%vreg12 -> %X8] GPR64
[%vreg14 -> %X8] GPR64common
[%vreg16 -> %X0] GPR64sp
[%vreg17 -> %X19] GPR64
[%vreg20 -> %X8] GPR64common
[%vreg22 -> %X8] GPR64
[%vreg24 -> %X8] GPR64common
[%vreg26 -> %X8] GPR64
[%vreg28 -> %X8] GPR64
[%vreg30 -> %W8] GPR32
[%vreg32 -> %W8] GPR32
[%vreg34 -> %X9] GPR64
[%vreg35 -> %X8] GPR64common
[%vreg36 -> %W8] GPR32
[%vreg37 -> %X8] GPR64
[%vreg39 -> %W8] GPR32
[%vreg42 -> %X9] GPR64common
[%vreg43 -> %X8] GPR64
[%vreg46 -> %X9] GPR64common
[%vreg47 -> %W8] GPR32
[%vreg50 -> %W0] GPR32
[%vreg52 -> %X0] GPR64
[%vreg53 -> %X8] GPR64common
[%vreg56 -> %W8] GPR32
[%vreg57 -> %X8] GPR64common
[%vreg58 -> %W0] GPR32
[%vreg59 -> %W8] GPR32
[%vreg63 -> %X0] GPR64
[%vreg64 -> %X8] GPR64common
[%vreg67 -> %W0] GPR32
[%vreg69 -> %X0] GPR64
[%vreg70 -> %X8] GPR64common
[%vreg78 -> %X0] GPR64
[%vreg80 -> %X3] GPR64
[%vreg81 -> %X8] GPR64common
[%vreg84 -> %X0] GPR64sp
[%vreg85 -> %X9] GPR64common
[%vreg88 -> %X9] GPR64common
[%vreg91 -> %X8] GPR64common
[%vreg92 -> %X8] GPR64common
[%vreg95 -> %X9] GPR64common
[%vreg97 -> %W8] GPR32
[%vreg98 -> %X8] GPR64common
[%vreg101 -> %X9] GPR64common
[%vreg102 -> %W8] GPR32
[%vreg104 -> %X8] GPR64
[%vreg105 -> %W9] GPR32
[%vreg107 -> %X8] GPR64common
[%vreg109 -> %X8] GPR64
[%vreg110 -> %W9] GPR32
[%vreg112 -> %X8] GPR64common
[%vreg114 -> %W8] GPR32
[%vreg117 -> %W0] GPR32
[%vreg119 -> %X9] GPR64
[%vreg120 -> %X0] GPR64
[%vreg121 -> %X8] GPR64
[%vreg123 -> %W8] GPR32common
[%vreg125 -> %W8] GPR32
[%vreg127 -> %W0] GPR32
[%vreg128 -> %W8] GPR32
[%vreg132 -> %X0] GPR64
[%vreg133 -> %X8] GPR64common
[%vreg136 -> %W8] GPR32
[%vreg137 -> %X8] GPR64common
[%vreg140 -> %W8] GPR32common
[%vreg141 -> %X8] GPR64common
[%vreg143 -> %W8] GPR32common
[%vreg146 -> %W8] GPR32
[%vreg147 -> %X8] GPR64common
[%vreg149 -> %X8] GPR64
[%vreg151 -> %X8] GPR64common
[%vreg153 -> %X8] GPR64
[%vreg155 -> %X8] GPR64common
[%vreg157 -> %W8] GPR32
[%vreg159 -> %X8] GPR64
[%vreg160 -> %W9] GPR32
[%vreg162 -> %X8] GPR64common
[%vreg164 -> %X8] GPR64
[%vreg165 -> %W9] GPR32
[%vreg167 -> %X8] GPR64common
[%vreg171 -> %W8] GPR32
[%vreg173 -> %W8] GPR32
[%vreg174 -> %X8] GPR64common
[%vreg175 -> %W9] GPR32
[%vreg177 -> %X8] GPR64
[%vreg178 -> %W9] GPR32
[%vreg180 -> %X8] GPR64common
[%vreg182 -> %X8] GPR64
[%vreg183 -> %W9] GPR32
[%vreg185 -> %X8] GPR64common
[%vreg187 -> %X8] GPR64
[%vreg190 -> %X9] GPR64common
[%vreg191 -> %W8] GPR32
[%vreg193 -> %X8] GPR64
[%vreg196 -> %X9] GPR64common
[%vreg197 -> %W8] GPR32
[%vreg199 -> %X8] GPR64
[%vreg200 -> %W9] GPR32
[%vreg202 -> %X8] GPR64common
[%vreg204 -> %X8] GPR64
[%vreg205 -> %W9] GPR32
[%vreg207 -> %X8] GPR64common
[%vreg209 -> %X8] GPR64
[%vreg211 -> %X8] GPR64common
[%vreg213 -> %X8] GPR64
[%vreg215 -> %X8] GPR64common
[%vreg217 -> %X8] GPR64
[%vreg218 -> %W9] GPR32
[%vreg220 -> %X8] GPR64common
[%vreg222 -> %X8] GPR64
[%vreg223 -> %W9] GPR32
[%vreg225 -> %X8] GPR64common
[%vreg227 -> %X8] GPR64
[%vreg228 -> %W9] GPR32
[%vreg230 -> %X8] GPR64common
[%vreg232 -> %X8] GPR64
[%vreg233 -> %W9] GPR32
[%vreg235 -> %X8] GPR64common
[%vreg237 -> %W0] GPR32
[%vreg238 -> %X8] GPR64common
[%vreg240 -> %X0] GPR64sp


Stackmap 0:
  STACKMAP 0, 0, %vreg3, 0, <fi#2>, 0, %vreg5, 0, <fi#3>, 0, %vreg1, 0, <fi#1>, 0, 0, <fi#7>, 0, %vreg7, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2] LD8[FixedStack3] LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4) GPR64:%vreg3,%vreg5,%vreg1 GPR32:%vreg7

i8* %b: in register %X22 (vreg 3)
i8** %b.addr: in stack slot 2 (size: 8)
i8* %buf: in register %X21 (vreg 5)
i8** %buf.addr: in stack slot 3 (size: 8)
i32* %bzerror: in register %X23 (vreg 1)
i32** %bzerror.addr: in stack slot 1 (size: 8)
%struct.bzFile** %bzf: in stack slot 7 (size: 8)
i32 %len: in register %W20 (vreg 7)
i32* %len.addr: in stack slot 4 (size: 4)
i32* %n: in stack slot 5 (size: 4)
i32* %ret: in stack slot 6 (size: 4)
i32* %retval: in stack slot 0 (size: 4)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)

i32** %bzerror.addr: in stack slot 1 (size: 8)
%struct.bzFile** %bzf: in stack slot 7 (size: 8)
i32* %len.addr: in stack slot 4 (size: 4)
i32* %n: in stack slot 5 (size: 4)
i32* %ret: in stack slot 6 (size: 4)
i32* %retval: in stack slot 0 (size: 4)

Duplicate operand locations:


Stackmap 2:
  STACKMAP 2, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)

i32** %bzerror.addr: in stack slot 1 (size: 8)
%struct.bzFile** %bzf: in stack slot 7 (size: 8)
i32* %len.addr: in stack slot 4 (size: 4)
i32* %n: in stack slot 5 (size: 4)
i32* %ret: in stack slot 6 (size: 4)
i32* %retval: in stack slot 0 (size: 4)

Duplicate operand locations:


Stackmap 3:
  STACKMAP 3, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)

i32** %bzerror.addr: in stack slot 1 (size: 8)
%struct.bzFile** %bzf: in stack slot 7 (size: 8)
i32* %len.addr: in stack slot 4 (size: 4)
i32* %n: in stack slot 5 (size: 4)
i32* %ret: in stack slot 6 (size: 4)
i32* %retval: in stack slot 0 (size: 4)

Duplicate operand locations:


Stackmap 4:
  STACKMAP 4, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)

i32** %bzerror.addr: in stack slot 1 (size: 8)
%struct.bzFile** %bzf: in stack slot 7 (size: 8)
i32* %len.addr: in stack slot 4 (size: 4)
i32* %n: in stack slot 5 (size: 4)
i32* %ret: in stack slot 6 (size: 4)
i32* %retval: in stack slot 0 (size: 4)

Duplicate operand locations:


Stackmap 5:
  STACKMAP 5, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)

i32** %bzerror.addr: in stack slot 1 (size: 8)
%struct.bzFile** %bzf: in stack slot 7 (size: 8)
i32* %len.addr: in stack slot 4 (size: 4)
i32* %n: in stack slot 5 (size: 4)
i32* %ret: in stack slot 6 (size: 4)
i32* %retval: in stack slot 0 (size: 4)

Duplicate operand locations:


Stackmap 6:
  STACKMAP 6, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)

i32** %bzerror.addr: in stack slot 1 (size: 8)
%struct.bzFile** %bzf: in stack slot 7 (size: 8)
i32* %len.addr: in stack slot 4 (size: 4)
i32* %n: in stack slot 5 (size: 4)
i32* %ret: in stack slot 6 (size: 4)
i32* %retval: in stack slot 0 (size: 4)

Duplicate operand locations:


Stackmap 7:
  STACKMAP 7, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)

i32* %retval: in stack slot 0 (size: 4)

Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, %vreg3, 0, <fi#2>, 0, %vreg5, 0, <fi#3>, 0, %vreg1, 0, <fi#1>, 0, 0, <fi#7>, 0, %vreg7, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2] LD8[FixedStack3] LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4) GPR64:%vreg3,%vreg5,%vreg1 GPR32:%vreg7
  -> Call instruction SlotIndex 272B, searching vregs 0 -> 242 and stack slots 0 -> 8
    + vreg17 is live in register but not in stackmap
      Defining instruction: %vreg17<def> = COPY %LR; GPR64:%vreg17
      Value: generated value, 1 instruction(s)

  STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
  -> Call instruction SlotIndex 1920B, searching vregs 0 -> 242 and stack slots 0 -> 8
    + vreg17 is live in register but not in stackmap
      Defining instruction: %vreg17<def> = COPY %LR; GPR64:%vreg17
      Value: generated value, 1 instruction(s)

  STACKMAP 2, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
  -> Call instruction SlotIndex 2448B, searching vregs 0 -> 242 and stack slots 0 -> 8
    + vreg17 is live in register but not in stackmap
      Defining instruction: %vreg17<def> = COPY %LR; GPR64:%vreg17
      Value: generated value, 1 instruction(s)

  STACKMAP 3, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
  -> Call instruction SlotIndex 2784B, searching vregs 0 -> 242 and stack slots 0 -> 8
    + vreg17 is live in register but not in stackmap
      Defining instruction: %vreg17<def> = COPY %LR; GPR64:%vreg17
      Value: generated value, 1 instruction(s)

  STACKMAP 4, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
  -> Call instruction SlotIndex 2976B, searching vregs 0 -> 242 and stack slots 0 -> 8
    + vreg17 is live in register but not in stackmap
      Defining instruction: %vreg17<def> = COPY %LR; GPR64:%vreg17
      Value: generated value, 1 instruction(s)

  STACKMAP 5, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
  -> Call instruction SlotIndex 3648B, searching vregs 0 -> 242 and stack slots 0 -> 8
    + vreg17 is live in register but not in stackmap
      Defining instruction: %vreg17<def> = COPY %LR; GPR64:%vreg17
      Value: generated value, 1 instruction(s)

  STACKMAP 6, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
  -> Call instruction SlotIndex 4256B, searching vregs 0 -> 242 and stack slots 0 -> 8
    + vreg17 is live in register but not in stackmap
      Defining instruction: %vreg17<def> = COPY %LR; GPR64:%vreg17
      Value: generated value, 1 instruction(s)

  STACKMAP 7, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
  -> Call instruction SlotIndex 5696B, searching vregs 0 -> 242 and stack slots 0 -> 8

********** REWRITE VIRTUAL REGISTERS **********
********** Function: BZ2_bzRead
********** REGISTER MAP **********
[%vreg1 -> %X23] GPR64
[%vreg3 -> %X22] GPR64
[%vreg5 -> %X21] GPR64
[%vreg7 -> %W20] GPR32
[%vreg9 -> %X8] GPR64
[%vreg12 -> %X8] GPR64
[%vreg14 -> %X8] GPR64common
[%vreg16 -> %X0] GPR64sp
[%vreg17 -> %X19] GPR64
[%vreg20 -> %X8] GPR64common
[%vreg22 -> %X8] GPR64
[%vreg24 -> %X8] GPR64common
[%vreg26 -> %X8] GPR64
[%vreg28 -> %X8] GPR64
[%vreg30 -> %W8] GPR32
[%vreg32 -> %W8] GPR32
[%vreg34 -> %X9] GPR64
[%vreg35 -> %X8] GPR64common
[%vreg36 -> %W8] GPR32
[%vreg37 -> %X8] GPR64
[%vreg39 -> %W8] GPR32
[%vreg42 -> %X9] GPR64common
[%vreg43 -> %X8] GPR64
[%vreg46 -> %X9] GPR64common
[%vreg47 -> %W8] GPR32
[%vreg50 -> %W0] GPR32
[%vreg52 -> %X0] GPR64
[%vreg53 -> %X8] GPR64common
[%vreg56 -> %W8] GPR32
[%vreg57 -> %X8] GPR64common
[%vreg58 -> %W0] GPR32
[%vreg59 -> %W8] GPR32
[%vreg63 -> %X0] GPR64
[%vreg64 -> %X8] GPR64common
[%vreg67 -> %W0] GPR32
[%vreg69 -> %X0] GPR64
[%vreg70 -> %X8] GPR64common
[%vreg78 -> %X0] GPR64
[%vreg80 -> %X3] GPR64
[%vreg81 -> %X8] GPR64common
[%vreg84 -> %X0] GPR64sp
[%vreg85 -> %X9] GPR64common
[%vreg88 -> %X9] GPR64common
[%vreg91 -> %X8] GPR64common
[%vreg92 -> %X8] GPR64common
[%vreg95 -> %X9] GPR64common
[%vreg97 -> %W8] GPR32
[%vreg98 -> %X8] GPR64common
[%vreg101 -> %X9] GPR64common
[%vreg102 -> %W8] GPR32
[%vreg104 -> %X8] GPR64
[%vreg105 -> %W9] GPR32
[%vreg107 -> %X8] GPR64common
[%vreg109 -> %X8] GPR64
[%vreg110 -> %W9] GPR32
[%vreg112 -> %X8] GPR64common
[%vreg114 -> %W8] GPR32
[%vreg117 -> %W0] GPR32
[%vreg119 -> %X9] GPR64
[%vreg120 -> %X0] GPR64
[%vreg121 -> %X8] GPR64
[%vreg123 -> %W8] GPR32common
[%vreg125 -> %W8] GPR32
[%vreg127 -> %W0] GPR32
[%vreg128 -> %W8] GPR32
[%vreg132 -> %X0] GPR64
[%vreg133 -> %X8] GPR64common
[%vreg136 -> %W8] GPR32
[%vreg137 -> %X8] GPR64common
[%vreg140 -> %W8] GPR32common
[%vreg141 -> %X8] GPR64common
[%vreg143 -> %W8] GPR32common
[%vreg146 -> %W8] GPR32
[%vreg147 -> %X8] GPR64common
[%vreg149 -> %X8] GPR64
[%vreg151 -> %X8] GPR64common
[%vreg153 -> %X8] GPR64
[%vreg155 -> %X8] GPR64common
[%vreg157 -> %W8] GPR32
[%vreg159 -> %X8] GPR64
[%vreg160 -> %W9] GPR32
[%vreg162 -> %X8] GPR64common
[%vreg164 -> %X8] GPR64
[%vreg165 -> %W9] GPR32
[%vreg167 -> %X8] GPR64common
[%vreg171 -> %W8] GPR32
[%vreg173 -> %W8] GPR32
[%vreg174 -> %X8] GPR64common
[%vreg175 -> %W9] GPR32
[%vreg177 -> %X8] GPR64
[%vreg178 -> %W9] GPR32
[%vreg180 -> %X8] GPR64common
[%vreg182 -> %X8] GPR64
[%vreg183 -> %W9] GPR32
[%vreg185 -> %X8] GPR64common
[%vreg187 -> %X8] GPR64
[%vreg190 -> %X9] GPR64common
[%vreg191 -> %W8] GPR32
[%vreg193 -> %X8] GPR64
[%vreg196 -> %X9] GPR64common
[%vreg197 -> %W8] GPR32
[%vreg199 -> %X8] GPR64
[%vreg200 -> %W9] GPR32
[%vreg202 -> %X8] GPR64common
[%vreg204 -> %X8] GPR64
[%vreg205 -> %W9] GPR32
[%vreg207 -> %X8] GPR64common
[%vreg209 -> %X8] GPR64
[%vreg211 -> %X8] GPR64common
[%vreg213 -> %X8] GPR64
[%vreg215 -> %X8] GPR64common
[%vreg217 -> %X8] GPR64
[%vreg218 -> %W9] GPR32
[%vreg220 -> %X8] GPR64common
[%vreg222 -> %X8] GPR64
[%vreg223 -> %W9] GPR32
[%vreg225 -> %X8] GPR64common
[%vreg227 -> %X8] GPR64
[%vreg228 -> %W9] GPR32
[%vreg230 -> %X8] GPR64common
[%vreg232 -> %X8] GPR64
[%vreg233 -> %W9] GPR32
[%vreg235 -> %X8] GPR64common
[%vreg237 -> %W0] GPR32
[%vreg238 -> %X8] GPR64common
[%vreg240 -> %X0] GPR64sp

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %LR %W3 %X0 %X1 %X2
16B		%vreg17<def> = COPY %LR; GPR64:%vreg17
32B		%vreg7<def> = COPY %W3; GPR32:%vreg7
48B		%vreg5<def> = COPY %X2; GPR64:%vreg5
64B		%vreg3<def> = COPY %X1; GPR64:%vreg3
80B		%vreg1<def> = COPY %X0; GPR64:%vreg1
160B		%vreg14<def> = ADRP <ga:@BZ2_bzRead>[TF=1]; GPR64common:%vreg14
176B		%vreg16<def> = ADDXri %vreg14<kill>, <ga:@BZ2_bzRead>[TF=34], 0; GPR64sp:%vreg16 GPR64common:%vreg14
224B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
240B		%X0<def> = COPY %vreg16<kill>; GPR64sp:%vreg16
256B		%X1<def> = COPY %vreg17; GPR64:%vreg17
272B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
288B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
304B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
320B		STACKMAP 0, 0, %vreg3, 0, <fi#2>, 0, %vreg5, 0, <fi#3>, 0, %vreg1, 0, <fi#1>, 0, 0, <fi#7>, 0, %vreg7, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2] LD8[FixedStack3] LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4) GPR64:%vreg3,%vreg5,%vreg1 GPR32:%vreg7
336B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
352B		STRXui %vreg1<kill>, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg1
368B		STRXui %vreg3<kill>, <fi#2>, 0; mem:ST8[FixedStack2] GPR64:%vreg3
384B		STRXui %vreg5<kill>, <fi#3>, 0; mem:ST8[FixedStack3] GPR64:%vreg5
400B		STRWui %vreg7<kill>, <fi#4>, 0; mem:ST4[FixedStack4] GPR32:%vreg7
416B		%vreg12<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg12
448B		STRXui %vreg12<kill>, <fi#7>, 0; mem:ST8[FixedStack7] GPR64:%vreg12
464B		%vreg9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg9
480B		CBZX %vreg9<kill>, <BB#2>; GPR64:%vreg9
	    Successors according to CFG: BB#2 BB#1
> %X19<def> = COPY %LR
> %W20<def> = COPY %W3
> %X21<def> = COPY %X2
> %X22<def> = COPY %X1
> %X23<def> = COPY %X0
> %X8<def> = ADRP <ga:@BZ2_bzRead>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@BZ2_bzRead>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19
> BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 0, 0, %X22, 0, <fi#2>, 0, %X21, 0, <fi#3>, 0, %X23, 0, <fi#1>, 0, 0, <fi#7>, 0, %W20, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2] LD8[FixedStack3] LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRXui %X23<kill>, <fi#1>, 0; mem:ST8[FixedStack1]
> STRXui %X22<kill>, <fi#2>, 0; mem:ST8[FixedStack2]
> STRXui %X21<kill>, <fi#3>, 0; mem:ST8[FixedStack3]
> STRWui %W20<kill>, <fi#4>, 0; mem:ST4[FixedStack4]
> %X8<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2]
> STRXui %X8<kill>, <fi#7>, 0; mem:ST8[FixedStack7]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> CBZX %X8<kill>, <BB#2>
496B	BB#1: derived from LLVM BB %if.then
	    Live Ins: %X19
	    Predecessors according to CFG: BB#0
512B		%vreg20<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg20
528B		STRWui %WZR, %vreg20<kill>, 0; mem:ST4[%3] GPR64common:%vreg20
	    Successors according to CFG: BB#2
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRWui %WZR, %X8<kill>, 0; mem:ST4[%3]
544B	BB#2: derived from LLVM BB %if.end
	    Live Ins: %X19
	    Predecessors according to CFG: BB#0 BB#1
560B		%vreg22<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg22
576B		CBZX %vreg22<kill>, <BB#4>; GPR64:%vreg22
	    Successors according to CFG: BB#4 BB#3
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> CBZX %X8<kill>, <BB#4>
592B	BB#3: derived from LLVM BB %if.then.2
	    Live Ins: %X19
	    Predecessors according to CFG: BB#2
608B		%vreg24<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg24
624B		STRWui %WZR, %vreg24<kill>, 1274; mem:ST4[%lastErr] GPR64common:%vreg24
	    Successors according to CFG: BB#4
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> STRWui %WZR, %X8<kill>, 1274; mem:ST4[%lastErr]
640B	BB#4: derived from LLVM BB %if.end.3
	    Live Ins: %X19
	    Predecessors according to CFG: BB#2 BB#3
656B		%vreg26<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg26
672B		CBZX %vreg26<kill>, <BB#7>; GPR64:%vreg26
	    Successors according to CFG: BB#7 BB#5
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> CBZX %X8<kill>, <BB#7>
688B	BB#5: derived from LLVM BB %lor.lhs.false
	    Live Ins: %X19
	    Predecessors according to CFG: BB#4
704B		%vreg28<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg28
720B		CBZX %vreg28<kill>, <BB#7>; GPR64:%vreg28
	    Successors according to CFG: BB#7 BB#6
> %X8<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> CBZX %X8<kill>, <BB#7>
736B	BB#6: derived from LLVM BB %lor.lhs.false.6
	    Live Ins: %X19
	    Predecessors according to CFG: BB#5
752B		%vreg30<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg30
768B		TBZW %vreg30<kill>, 31, <BB#12>; GPR32:%vreg30
	    Successors according to CFG: BB#12 BB#7
> %W8<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4]
> TBZW %W8<kill>, 31, <BB#12>
784B	BB#7: derived from LLVM BB %if.then.8
	    Live Ins: %X19
	    Predecessors according to CFG: BB#4 BB#5 BB#6
800B		%vreg227<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg227
816B		CBZX %vreg227<kill>, <BB#9>; GPR64:%vreg227
	    Successors according to CFG: BB#9 BB#8
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> CBZX %X8<kill>, <BB#9>
832B	BB#8: derived from LLVM BB %if.then.10
	    Live Ins: %X19
	    Predecessors according to CFG: BB#7
864B		%vreg230<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg230
872B		%vreg228<def> = MOVi32imm 4294967294; GPR32:%vreg228
880B		STRWui %vreg228<kill>, %vreg230<kill>, 0; mem:ST4[%10] GPR32:%vreg228 GPR64common:%vreg230
	    Successors according to CFG: BB#9
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = MOVi32imm 4294967294
> STRWui %W9<kill>, %X8<kill>, 0; mem:ST4[%10]
896B	BB#9: derived from LLVM BB %if.end.11
	    Live Ins: %X19
	    Predecessors according to CFG: BB#7 BB#8
912B		%vreg232<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg232
928B		CBZX %vreg232<kill>, <BB#11>; GPR64:%vreg232
	    Successors according to CFG: BB#11 BB#10
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> CBZX %X8<kill>, <BB#11>
944B	BB#10: derived from LLVM BB %if.then.13
	    Live Ins: %X19
	    Predecessors according to CFG: BB#9
976B		%vreg235<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg235
984B		%vreg233<def> = MOVi32imm 4294967294; GPR32:%vreg233
992B		STRWui %vreg233<kill>, %vreg235<kill>, 1274; mem:ST4[%lastErr14] GPR32:%vreg233 GPR64common:%vreg235
	    Successors according to CFG: BB#11
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> %W9<def> = MOVi32imm 4294967294
> STRWui %W9<kill>, %X8<kill>, 1274; mem:ST4[%lastErr14]
1008B	BB#11: derived from LLVM BB %if.end.15
	    Live Ins: %X19
	    Predecessors according to CFG: BB#9 BB#10
1024B		STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
1040B		B <BB#69>
	    Successors according to CFG: BB#69
> STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
> B <BB#69>
1056B	BB#12: derived from LLVM BB %if.end.16
	    Live Ins: %X19
	    Predecessors according to CFG: BB#6
1072B		%vreg37<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg37
1088B		%vreg34<def> = MOVi64imm 5012; GPR64:%vreg34
1104B		%vreg35<def> = ADDXrr %vreg37<kill>, %vreg34<kill>; GPR64common:%vreg35 GPR64:%vreg37,%vreg34
1120B		%vreg36<def> = LDRBBui %vreg35<kill>, 0; mem:LD1[%writing] GPR32:%vreg36 GPR64common:%vreg35
1136B		%vreg32<def> = UBFMWri %vreg36<kill>, 0, 7; GPR32:%vreg32,%vreg36
1152B		CBZW %vreg32<kill>, <BB#18>; GPR32:%vreg32
	    Successors according to CFG: BB#18 BB#13
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> %X9<def> = MOVi64imm 5012
> %X8<def> = ADDXrr %X8<kill>, %X9<kill>
> %W8<def> = LDRBBui %X8<kill>, 0; mem:LD1[%writing]
> %W8<def> = UBFMWri %W8<kill>, 0, 7
> CBZW %W8<kill>, <BB#18>
1168B	BB#13: derived from LLVM BB %if.then.17
	    Live Ins: %X19
	    Predecessors according to CFG: BB#12
1184B		%vreg217<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg217
1200B		CBZX %vreg217<kill>, <BB#15>; GPR64:%vreg217
	    Successors according to CFG: BB#15 BB#14
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> CBZX %X8<kill>, <BB#15>
1216B	BB#14: derived from LLVM BB %if.then.19
	    Live Ins: %X19
	    Predecessors according to CFG: BB#13
1248B		%vreg220<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg220
1256B		%vreg218<def> = MOVi32imm 4294967295; GPR32:%vreg218
1264B		STRWui %vreg218<kill>, %vreg220<kill>, 0; mem:ST4[%16] GPR32:%vreg218 GPR64common:%vreg220
	    Successors according to CFG: BB#15
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = MOVi32imm 4294967295
> STRWui %W9<kill>, %X8<kill>, 0; mem:ST4[%16]
1280B	BB#15: derived from LLVM BB %if.end.20
	    Live Ins: %X19
	    Predecessors according to CFG: BB#13 BB#14
1296B		%vreg222<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg222
1312B		CBZX %vreg222<kill>, <BB#17>; GPR64:%vreg222
	    Successors according to CFG: BB#17 BB#16
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> CBZX %X8<kill>, <BB#17>
1328B	BB#16: derived from LLVM BB %if.then.22
	    Live Ins: %X19
	    Predecessors according to CFG: BB#15
1360B		%vreg225<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg225
1368B		%vreg223<def> = MOVi32imm 4294967295; GPR32:%vreg223
1376B		STRWui %vreg223<kill>, %vreg225<kill>, 1274; mem:ST4[%lastErr23] GPR32:%vreg223 GPR64common:%vreg225
	    Successors according to CFG: BB#17
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> %W9<def> = MOVi32imm 4294967295
> STRWui %W9<kill>, %X8<kill>, 1274; mem:ST4[%lastErr23]
1392B	BB#17: derived from LLVM BB %if.end.24
	    Live Ins: %X19
	    Predecessors according to CFG: BB#15 BB#16
1408B		STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
1424B		B <BB#69>
	    Successors according to CFG: BB#69
> STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
> B <BB#69>
1440B	BB#18: derived from LLVM BB %if.end.25
	    Live Ins: %X19
	    Predecessors according to CFG: BB#12
1456B		%vreg39<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg39
1472B		CBNZW %vreg39<kill>, <BB#24>; GPR32:%vreg39
	    Successors according to CFG: BB#24 BB#19
> %W8<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4]
> CBNZW %W8<kill>, <BB#24>
1488B	BB#19: derived from LLVM BB %if.then.27
	    Live Ins: %X19
	    Predecessors according to CFG: BB#18
1504B		%vreg209<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg209
1520B		CBZX %vreg209<kill>, <BB#21>; GPR64:%vreg209
	    Successors according to CFG: BB#21 BB#20
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> CBZX %X8<kill>, <BB#21>
1536B	BB#20: derived from LLVM BB %if.then.29
	    Live Ins: %X19
	    Predecessors according to CFG: BB#19
1552B		%vreg211<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg211
1568B		STRWui %WZR, %vreg211<kill>, 0; mem:ST4[%21] GPR64common:%vreg211
	    Successors according to CFG: BB#21
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRWui %WZR, %X8<kill>, 0; mem:ST4[%21]
1584B	BB#21: derived from LLVM BB %if.end.30
	    Live Ins: %X19
	    Predecessors according to CFG: BB#19 BB#20
1600B		%vreg213<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg213
1616B		CBZX %vreg213<kill>, <BB#23>; GPR64:%vreg213
	    Successors according to CFG: BB#23 BB#22
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> CBZX %X8<kill>, <BB#23>
1632B	BB#22: derived from LLVM BB %if.then.32
	    Live Ins: %X19
	    Predecessors according to CFG: BB#21
1648B		%vreg215<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg215
1664B		STRWui %WZR, %vreg215<kill>, 1274; mem:ST4[%lastErr33] GPR64common:%vreg215
	    Successors according to CFG: BB#23
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> STRWui %WZR, %X8<kill>, 1274; mem:ST4[%lastErr33]
1680B	BB#23: derived from LLVM BB %if.end.34
	    Live Ins: %X19
	    Predecessors according to CFG: BB#21 BB#22
1696B		STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
1712B		B <BB#69>
	    Successors according to CFG: BB#69
> STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
> B <BB#69>
1728B	BB#24: derived from LLVM BB %if.end.35
	    Live Ins: %X19
	    Predecessors according to CFG: BB#18
1744B		%vreg47<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg47
1760B		%vreg46<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg46
1776B		STRWui %vreg47<kill>, %vreg46<kill>, 1262; mem:ST4[%avail_out] GPR32:%vreg47 GPR64common:%vreg46
1792B		%vreg43<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg43
1808B		%vreg42<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg42
1824B		STRXui %vreg43<kill>, %vreg42<kill>, 630; mem:ST8[%next_out] GPR64:%vreg43 GPR64common:%vreg42
	    Successors according to CFG: BB#25
> %W8<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4]
> %X9<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> STRWui %W8<kill>, %X9<kill>, 1262; mem:ST4[%avail_out]
> %X8<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> %X9<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> STRXui %X8<kill>, %X9<kill>, 630; mem:ST8[%next_out]
1840B	BB#25: derived from LLVM BB %while.body
	    Live Ins: %X19
	    Predecessors according to CFG: BB#24 BB#68
1856B		%vreg53<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg53
1872B		%vreg52<def> = LDRXui %vreg53<kill>, 0; mem:LD8[%handle] GPR64:%vreg52 GPR64common:%vreg53
1888B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1904B		%X0<def> = COPY %vreg52<kill>; GPR64:%vreg52
1920B		BL <ga:@ferror>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
1936B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1952B		%vreg50<def> = COPY %W0; GPR32:%vreg50
1968B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1984B		STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
2000B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2016B		CBZW %vreg50<kill>, <BB#31>; GPR32:%vreg50
	    Successors according to CFG: BB#31 BB#26
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> %X0<def> = LDRXui %X8<kill>, 0; mem:LD8[%handle]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BL <ga:@ferror>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = COPY %W0
Deleting identity copy.
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> CBZW %W0<kill>, <BB#31>
2032B	BB#26: derived from LLVM BB %if.then.38
	    Live Ins: %X19
	    Predecessors according to CFG: BB#25
2048B		%vreg199<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg199
2064B		CBZX %vreg199<kill>, <BB#28>; GPR64:%vreg199
	    Successors according to CFG: BB#28 BB#27
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> CBZX %X8<kill>, <BB#28>
2080B	BB#27: derived from LLVM BB %if.then.40
	    Live Ins: %X19
	    Predecessors according to CFG: BB#26
2112B		%vreg202<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg202
2120B		%vreg200<def> = MOVi32imm 4294967290; GPR32:%vreg200
2128B		STRWui %vreg200<kill>, %vreg202<kill>, 0; mem:ST4[%31] GPR32:%vreg200 GPR64common:%vreg202
	    Successors according to CFG: BB#28
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = MOVi32imm 4294967290
> STRWui %W9<kill>, %X8<kill>, 0; mem:ST4[%31]
2144B	BB#28: derived from LLVM BB %if.end.41
	    Live Ins: %X19
	    Predecessors according to CFG: BB#26 BB#27
2160B		%vreg204<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg204
2176B		CBZX %vreg204<kill>, <BB#30>; GPR64:%vreg204
	    Successors according to CFG: BB#30 BB#29
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> CBZX %X8<kill>, <BB#30>
2192B	BB#29: derived from LLVM BB %if.then.43
	    Live Ins: %X19
	    Predecessors according to CFG: BB#28
2224B		%vreg207<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg207
2232B		%vreg205<def> = MOVi32imm 4294967290; GPR32:%vreg205
2240B		STRWui %vreg205<kill>, %vreg207<kill>, 1274; mem:ST4[%lastErr44] GPR32:%vreg205 GPR64common:%vreg207
	    Successors according to CFG: BB#30
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> %W9<def> = MOVi32imm 4294967290
> STRWui %W9<kill>, %X8<kill>, 1274; mem:ST4[%lastErr44]
2256B	BB#30: derived from LLVM BB %if.end.45
	    Live Ins: %X19
	    Predecessors according to CFG: BB#28 BB#29
2272B		STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
2288B		B <BB#69>
	    Successors according to CFG: BB#69
> STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
> B <BB#69>
2304B	BB#31: derived from LLVM BB %if.end.46
	    Live Ins: %X19
	    Predecessors according to CFG: BB#25
2320B		%vreg57<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg57
2336B		%vreg56<def> = LDRWui %vreg57<kill>, 1256; mem:LD4[%avail_in] GPR32:%vreg56 GPR64common:%vreg57
2352B		CBNZW %vreg56<kill>, <BB#40>; GPR32:%vreg56
	    Successors according to CFG: BB#40 BB#32
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> %W8<def> = LDRWui %X8<kill>, 1256; mem:LD4[%avail_in]
> CBNZW %W8<kill>, <BB#40>
2368B	BB#32: derived from LLVM BB %land.lhs.true
	    Live Ins: %X19
	    Predecessors according to CFG: BB#31
2384B		%vreg64<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg64
2400B		%vreg63<def> = LDRXui %vreg64<kill>, 0; mem:LD8[%handle49] GPR64:%vreg63 GPR64common:%vreg64
2416B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2432B		%X0<def> = COPY %vreg63<kill>; GPR64:%vreg63
2448B		BL <ga:@myfeof>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>
2464B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2480B		%vreg58<def> = COPY %W0; GPR32:%vreg58
2512B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2528B		STACKMAP 2, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
2544B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2560B		%vreg59<def> = UBFMWri %vreg58<kill>, 0, 7; GPR32:%vreg59,%vreg58
2576B		CBNZW %vreg59<kill>, <BB#40>; GPR32:%vreg59
	    Successors according to CFG: BB#40 BB#33
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> %X0<def> = LDRXui %X8<kill>, 0; mem:LD8[%handle49]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BL <ga:@myfeof>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = COPY %W0
Deleting identity copy.
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 2, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W8<def> = UBFMWri %W0<kill>, 0, 7
> CBNZW %W8<kill>, <BB#40>
2592B	BB#33: derived from LLVM BB %if.then.52
	    Live Ins: %X19
	    Predecessors according to CFG: BB#32
2672B		%vreg81<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg81
2680B		%vreg85<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg85
2688B		%vreg80<def> = LDRXui %vreg81<kill>, 0; mem:LD8[%handle54] GPR64:%vreg80 GPR64common:%vreg81
2696B		%vreg84<def> = ADDXri %vreg85<kill>, 8, 0; GPR64sp:%vreg84 GPR64common:%vreg85
2704B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2712B		%X1<def> = MOVi64imm 1
2716B		%X2<def> = MOVi64imm 5000
2720B		%X0<def> = COPY %vreg84<kill>; GPR64sp:%vreg84
2768B		%X3<def> = COPY %vreg80<kill>; GPR64:%vreg80
2784B		BL <ga:@fread>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %X2<imp-use>, %X3<imp-use>, %X0<imp-def>
2800B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2816B		%vreg78<def> = COPY %X0; GPR64:%vreg78
2832B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2848B		STACKMAP 3, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
2864B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2896B		STRWui %vreg78:sub_32<kill>, <fi#5>, 0; mem:ST4[FixedStack5] GPR64:%vreg78
2912B		%vreg70<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg70
2928B		%vreg69<def> = LDRXui %vreg70<kill>, 0; mem:LD8[%handle56] GPR64:%vreg69 GPR64common:%vreg70
2944B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2960B		%X0<def> = COPY %vreg69<kill>; GPR64:%vreg69
2976B		BL <ga:@ferror>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
2992B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3008B		%vreg67<def> = COPY %W0; GPR32:%vreg67
3024B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3040B		STACKMAP 4, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
3056B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3072B		CBZW %vreg67<kill>, <BB#39>; GPR32:%vreg67
	    Successors according to CFG: BB#39 BB#34
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> %X9<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> %X3<def> = LDRXui %X8<kill>, 0; mem:LD8[%handle54]
> %X0<def> = ADDXri %X9<kill>, 8, 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X1<def> = MOVi64imm 1
> %X2<def> = MOVi64imm 5000
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X3<def> = COPY %X3<kill>
Deleting identity copy.
> BL <ga:@fread>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %X2<imp-use>, %X3<imp-use>, %X0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0
Deleting identity copy.
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 3, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRWui %W0, <fi#5>, 0, %X0<imp-use,kill>; mem:ST4[FixedStack5]
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> %X0<def> = LDRXui %X8<kill>, 0; mem:LD8[%handle56]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BL <ga:@ferror>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = COPY %W0
Deleting identity copy.
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 4, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> CBZW %W0<kill>, <BB#39>
3088B	BB#34: derived from LLVM BB %if.then.59
	    Live Ins: %X19
	    Predecessors according to CFG: BB#33
3104B		%vreg104<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg104
3120B		CBZX %vreg104<kill>, <BB#36>; GPR64:%vreg104
	    Successors according to CFG: BB#36 BB#35
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> CBZX %X8<kill>, <BB#36>
3136B	BB#35: derived from LLVM BB %if.then.62
	    Live Ins: %X19
	    Predecessors according to CFG: BB#34
3168B		%vreg107<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg107
3176B		%vreg105<def> = MOVi32imm 4294967290; GPR32:%vreg105
3184B		STRWui %vreg105<kill>, %vreg107<kill>, 0; mem:ST4[%44] GPR32:%vreg105 GPR64common:%vreg107
	    Successors according to CFG: BB#36
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = MOVi32imm 4294967290
> STRWui %W9<kill>, %X8<kill>, 0; mem:ST4[%44]
3200B	BB#36: derived from LLVM BB %if.end.63
	    Live Ins: %X19
	    Predecessors according to CFG: BB#34 BB#35
3216B		%vreg109<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg109
3232B		CBZX %vreg109<kill>, <BB#38>; GPR64:%vreg109
	    Successors according to CFG: BB#38 BB#37
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> CBZX %X8<kill>, <BB#38>
3248B	BB#37: derived from LLVM BB %if.then.66
	    Live Ins: %X19
	    Predecessors according to CFG: BB#36
3280B		%vreg112<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg112
3288B		%vreg110<def> = MOVi32imm 4294967290; GPR32:%vreg110
3296B		STRWui %vreg110<kill>, %vreg112<kill>, 1274; mem:ST4[%lastErr67] GPR32:%vreg110 GPR64common:%vreg112
	    Successors according to CFG: BB#38
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> %W9<def> = MOVi32imm 4294967290
> STRWui %W9<kill>, %X8<kill>, 1274; mem:ST4[%lastErr67]
3312B	BB#38: derived from LLVM BB %if.end.68
	    Live Ins: %X19
	    Predecessors according to CFG: BB#36 BB#37
3328B		STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
3344B		B <BB#69>
	    Successors according to CFG: BB#69
> STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
> B <BB#69>
3360B	BB#39: derived from LLVM BB %if.end.69
	    Live Ins: %X19
	    Predecessors according to CFG: BB#33
3376B		%vreg102<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32:%vreg102
3392B		%vreg101<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg101
3408B		STRWui %vreg102<kill>, %vreg101<kill>, 1252; mem:ST4[%bufN] GPR32:%vreg102 GPR64common:%vreg101
3424B		%vreg98<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg98
3440B		%vreg97<def> = LDRWui %vreg98<kill>, 1252; mem:LD4[%bufN70] GPR32:%vreg97 GPR64common:%vreg98
3456B		%vreg95<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg95
3472B		STRWui %vreg97<kill>, %vreg95<kill>, 1256; mem:ST4[%avail_in72] GPR32:%vreg97 GPR64common:%vreg95
3488B		%vreg92<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg92
3520B		%vreg88<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg88
3528B		%vreg91<def> = ADDXri %vreg92<kill>, 8, 0; GPR64common:%vreg91,%vreg92
3536B		STRXui %vreg91<kill>, %vreg88<kill>, 627; mem:ST8[%next_in] GPR64common:%vreg91,%vreg88
	    Successors according to CFG: BB#40
> %W8<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5]
> %X9<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> STRWui %W8<kill>, %X9<kill>, 1252; mem:ST4[%bufN]
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> %W8<def> = LDRWui %X8<kill>, 1252; mem:LD4[%bufN70]
> %X9<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> STRWui %W8<kill>, %X9<kill>, 1256; mem:ST4[%avail_in72]
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> %X9<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> %X8<def> = ADDXri %X8<kill>, 8, 0
> STRXui %X8<kill>, %X9<kill>, 627; mem:ST8[%next_in]
3552B	BB#40: derived from LLVM BB %if.end.76
	    Live Ins: %X19
	    Predecessors according to CFG: BB#31 BB#32 BB#39
3568B		%vreg121<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg121
3584B		%vreg119<def> = MOVi64imm 5016; GPR64:%vreg119
3600B		%vreg120<def> = ADDXrr %vreg121<kill>, %vreg119<kill>; GPR64:%vreg120,%vreg121,%vreg119
3616B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3632B		%X0<def> = COPY %vreg120<kill>; GPR64:%vreg120
3648B		BL <ga:@BZ2_bzDecompress>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
3664B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3680B		%vreg117<def> = COPY %W0; GPR32:%vreg117
3696B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3712B		STACKMAP 5, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
3728B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3744B		STRWui %vreg117<kill>, <fi#6>, 0; mem:ST4[FixedStack6] GPR32:%vreg117
3760B		%vreg114<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg114
3776B		CBZW %vreg114<kill>, <BB#47>; GPR32:%vreg114
	    Successors according to CFG: BB#47 BB#41
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> %X9<def> = MOVi64imm 5016
> %X0<def> = ADDXrr %X8<kill>, %X9<kill>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BL <ga:@BZ2_bzDecompress>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = COPY %W0
Deleting identity copy.
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 5, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRWui %W0<kill>, <fi#6>, 0; mem:ST4[FixedStack6]
> %W8<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6]
> CBZW %W8<kill>, <BB#47>
3792B	BB#41: derived from LLVM BB %land.lhs.true.81
	    Live Ins: %X19
	    Predecessors according to CFG: BB#40
3808B		%vreg123<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32common:%vreg123
3824B		%WZR<def> = SUBSWri %vreg123<kill>, 4, 0, %NZCV<imp-def>; GPR32common:%vreg123
3840B		Bcc 0, <BB#47>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#47 BB#42
> %W8<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6]
> %WZR<def> = SUBSWri %W8<kill>, 4, 0, %NZCV<imp-def>
> Bcc 0, <BB#47>, %NZCV<imp-use,kill>
3856B	BB#42: derived from LLVM BB %if.then.84
	    Live Ins: %X19
	    Predecessors according to CFG: BB#41
3872B		%vreg187<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg187
3888B		CBZX %vreg187<kill>, <BB#44>; GPR64:%vreg187
	    Successors according to CFG: BB#44 BB#43
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> CBZX %X8<kill>, <BB#44>
3904B	BB#43: derived from LLVM BB %if.then.87
	    Live Ins: %X19
	    Predecessors according to CFG: BB#42
3920B		%vreg191<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg191
3936B		%vreg190<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg190
3952B		STRWui %vreg191<kill>, %vreg190<kill>, 0; mem:ST4[%59] GPR32:%vreg191 GPR64common:%vreg190
	    Successors according to CFG: BB#44
> %W8<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRWui %W8<kill>, %X9<kill>, 0; mem:ST4[%59]
3968B	BB#44: derived from LLVM BB %if.end.88
	    Live Ins: %X19
	    Predecessors according to CFG: BB#42 BB#43
3984B		%vreg193<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg193
4000B		CBZX %vreg193<kill>, <BB#46>; GPR64:%vreg193
	    Successors according to CFG: BB#46 BB#45
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> CBZX %X8<kill>, <BB#46>
4016B	BB#45: derived from LLVM BB %if.then.91
	    Live Ins: %X19
	    Predecessors according to CFG: BB#44
4032B		%vreg197<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg197
4048B		%vreg196<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg196
4064B		STRWui %vreg197<kill>, %vreg196<kill>, 1274; mem:ST4[%lastErr92] GPR32:%vreg197 GPR64common:%vreg196
	    Successors according to CFG: BB#46
> %W8<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6]
> %X9<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> STRWui %W8<kill>, %X9<kill>, 1274; mem:ST4[%lastErr92]
4080B	BB#46: derived from LLVM BB %if.end.93
	    Live Ins: %X19
	    Predecessors according to CFG: BB#44 BB#45
4096B		STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
4112B		B <BB#69>
	    Successors according to CFG: BB#69
> STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
> B <BB#69>
4128B	BB#47: derived from LLVM BB %if.end.94
	    Live Ins: %X19
	    Predecessors according to CFG: BB#40 BB#41
4144B		%vreg125<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg125
4160B		CBNZW %vreg125<kill>, <BB#56>; GPR32:%vreg125
	    Successors according to CFG: BB#56 BB#48
> %W8<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6]
> CBNZW %W8<kill>, <BB#56>
4176B	BB#48: derived from LLVM BB %land.lhs.true.97
	    Live Ins: %X19
	    Predecessors according to CFG: BB#47
4192B		%vreg133<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg133
4208B		%vreg132<def> = LDRXui %vreg133<kill>, 0; mem:LD8[%handle98] GPR64:%vreg132 GPR64common:%vreg133
4224B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4240B		%X0<def> = COPY %vreg132<kill>; GPR64:%vreg132
4256B		BL <ga:@myfeof>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>
4272B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4288B		%vreg127<def> = COPY %W0; GPR32:%vreg127
4320B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4336B		STACKMAP 6, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
4352B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4368B		%vreg128<def> = UBFMWri %vreg127<kill>, 0, 7; GPR32:%vreg128,%vreg127
4384B		CBZW %vreg128<kill>, <BB#56>; GPR32:%vreg128
	    Successors according to CFG: BB#56 BB#49
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> %X0<def> = LDRXui %X8<kill>, 0; mem:LD8[%handle98]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BL <ga:@myfeof>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %SP<imp-def>, %W0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = COPY %W0
Deleting identity copy.
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 6, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W8<def> = UBFMWri %W0<kill>, 0, 7
> CBZW %W8<kill>, <BB#56>
4400B	BB#49: derived from LLVM BB %land.lhs.true.102
	    Live Ins: %X19
	    Predecessors according to CFG: BB#48
4416B		%vreg137<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg137
4432B		%vreg136<def> = LDRWui %vreg137<kill>, 1256; mem:LD4[%avail_in104] GPR32:%vreg136 GPR64common:%vreg137
4448B		CBNZW %vreg136<kill>, <BB#56>; GPR32:%vreg136
	    Successors according to CFG: BB#56 BB#50
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> %W8<def> = LDRWui %X8<kill>, 1256; mem:LD4[%avail_in104]
> CBNZW %W8<kill>, <BB#56>
4464B	BB#50: derived from LLVM BB %land.lhs.true.107
	    Live Ins: %X19
	    Predecessors according to CFG: BB#49
4480B		%vreg141<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg141
4496B		%vreg140<def> = LDRWui %vreg141<kill>, 1262; mem:LD4[%avail_out109] GPR32common:%vreg140 GPR64common:%vreg141
4512B		%WZR<def> = SUBSWri %vreg140<kill>, 0, 0, %NZCV<imp-def>; GPR32common:%vreg140
4528B		Bcc 9, <BB#56>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#56 BB#51
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> %W8<def> = LDRWui %X8<kill>, 1262; mem:LD4[%avail_out109]
> %WZR<def> = SUBSWri %W8<kill>, 0, 0, %NZCV<imp-def>
> Bcc 9, <BB#56>, %NZCV<imp-use,kill>
4544B	BB#51: derived from LLVM BB %if.then.112
	    Live Ins: %X19
	    Predecessors according to CFG: BB#50
4560B		%vreg177<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg177
4576B		CBZX %vreg177<kill>, <BB#53>; GPR64:%vreg177
	    Successors according to CFG: BB#53 BB#52
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> CBZX %X8<kill>, <BB#53>
4592B	BB#52: derived from LLVM BB %if.then.115
	    Live Ins: %X19
	    Predecessors according to CFG: BB#51
4624B		%vreg180<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg180
4632B		%vreg178<def> = MOVi32imm 4294967289; GPR32:%vreg178
4640B		STRWui %vreg178<kill>, %vreg180<kill>, 0; mem:ST4[%71] GPR32:%vreg178 GPR64common:%vreg180
	    Successors according to CFG: BB#53
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = MOVi32imm 4294967289
> STRWui %W9<kill>, %X8<kill>, 0; mem:ST4[%71]
4656B	BB#53: derived from LLVM BB %if.end.116
	    Live Ins: %X19
	    Predecessors according to CFG: BB#51 BB#52
4672B		%vreg182<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg182
4688B		CBZX %vreg182<kill>, <BB#55>; GPR64:%vreg182
	    Successors according to CFG: BB#55 BB#54
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> CBZX %X8<kill>, <BB#55>
4704B	BB#54: derived from LLVM BB %if.then.119
	    Live Ins: %X19
	    Predecessors according to CFG: BB#53
4736B		%vreg185<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg185
4744B		%vreg183<def> = MOVi32imm 4294967289; GPR32:%vreg183
4752B		STRWui %vreg183<kill>, %vreg185<kill>, 1274; mem:ST4[%lastErr120] GPR32:%vreg183 GPR64common:%vreg185
	    Successors according to CFG: BB#55
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> %W9<def> = MOVi32imm 4294967289
> STRWui %W9<kill>, %X8<kill>, 1274; mem:ST4[%lastErr120]
4768B	BB#55: derived from LLVM BB %if.end.121
	    Live Ins: %X19
	    Predecessors according to CFG: BB#53 BB#54
4784B		STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
4800B		B <BB#69>
	    Successors according to CFG: BB#69
> STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
> B <BB#69>
4816B	BB#56: derived from LLVM BB %if.end.122
	    Live Ins: %X19
	    Predecessors according to CFG: BB#47 BB#48 BB#49 BB#50
4832B		%vreg143<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32common:%vreg143
4848B		%WZR<def> = SUBSWri %vreg143<kill>, 4, 0, %NZCV<imp-def>; GPR32common:%vreg143
4864B		Bcc 1, <BB#62>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#62 BB#57
> %W8<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6]
> %WZR<def> = SUBSWri %W8<kill>, 4, 0, %NZCV<imp-def>
> Bcc 1, <BB#62>, %NZCV<imp-use,kill>
4880B	BB#57: derived from LLVM BB %if.then.125
	    Live Ins: %X19
	    Predecessors according to CFG: BB#56
4896B		%vreg159<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg159
4912B		CBZX %vreg159<kill>, <BB#59>; GPR64:%vreg159
	    Successors according to CFG: BB#59 BB#58
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> CBZX %X8<kill>, <BB#59>
4928B	BB#58: derived from LLVM BB %if.then.128
	    Live Ins: %X19
	    Predecessors according to CFG: BB#57
4960B		%vreg162<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg162
4968B		%vreg160<def> = MOVi32imm 4; GPR32:%vreg160
4976B		STRWui %vreg160<kill>, %vreg162<kill>, 0; mem:ST4[%76] GPR32:%vreg160 GPR64common:%vreg162
	    Successors according to CFG: BB#59
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W9<def> = MOVi32imm 4
> STRWui %W9<kill>, %X8<kill>, 0; mem:ST4[%76]
4992B	BB#59: derived from LLVM BB %if.end.129
	    Live Ins: %X19
	    Predecessors according to CFG: BB#57 BB#58
5008B		%vreg164<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg164
5024B		CBZX %vreg164<kill>, <BB#61>; GPR64:%vreg164
	    Successors according to CFG: BB#61 BB#60
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> CBZX %X8<kill>, <BB#61>
5040B	BB#60: derived from LLVM BB %if.then.132
	    Live Ins: %X19
	    Predecessors according to CFG: BB#59
5072B		%vreg167<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg167
5080B		%vreg165<def> = MOVi32imm 4; GPR32:%vreg165
5088B		STRWui %vreg165<kill>, %vreg167<kill>, 1274; mem:ST4[%lastErr133] GPR32:%vreg165 GPR64common:%vreg167
	    Successors according to CFG: BB#61
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> %W9<def> = MOVi32imm 4
> STRWui %W9<kill>, %X8<kill>, 1274; mem:ST4[%lastErr133]
5104B	BB#61: derived from LLVM BB %if.end.134
	    Live Ins: %X19
	    Predecessors according to CFG: BB#59 BB#60
5136B		%vreg174<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg174
5144B		%vreg175<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg175
5152B		%vreg173<def> = LDRWui %vreg174<kill>, 1262; mem:LD4[%avail_out136] GPR32:%vreg173 GPR64common:%vreg174
5168B		%vreg171<def> = SUBWrr %vreg175<kill>, %vreg173<kill>; GPR32:%vreg171,%vreg175,%vreg173
5184B		STRWui %vreg171<kill>, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg171
5200B		B <BB#69>
	    Successors according to CFG: BB#69
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> %W9<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4]
> %W8<def> = LDRWui %X8<kill>, 1262; mem:LD4[%avail_out136]
> %W8<def> = SUBWrr %W9<kill>, %W8<kill>
> STRWui %W8<kill>, <fi#0>, 0; mem:ST4[FixedStack0]
> B <BB#69>
5216B	BB#62: derived from LLVM BB %if.end.137
	    Live Ins: %X19
	    Predecessors according to CFG: BB#56
5232B		%vreg147<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg147
5248B		%vreg146<def> = LDRWui %vreg147<kill>, 1262; mem:LD4[%avail_out139] GPR32:%vreg146 GPR64common:%vreg147
5264B		CBNZW %vreg146<kill>, <BB#68>; GPR32:%vreg146
	    Successors according to CFG: BB#68 BB#63
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> %W8<def> = LDRWui %X8<kill>, 1262; mem:LD4[%avail_out139]
> CBNZW %W8<kill>, <BB#68>
5280B	BB#63: derived from LLVM BB %if.then.142
	    Live Ins: %X19
	    Predecessors according to CFG: BB#62
5296B		%vreg149<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg149
5312B		CBZX %vreg149<kill>, <BB#65>; GPR64:%vreg149
	    Successors according to CFG: BB#65 BB#64
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> CBZX %X8<kill>, <BB#65>
5328B	BB#64: derived from LLVM BB %if.then.145
	    Live Ins: %X19
	    Predecessors according to CFG: BB#63
5344B		%vreg151<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg151
5360B		STRWui %WZR, %vreg151<kill>, 0; mem:ST4[%85] GPR64common:%vreg151
	    Successors according to CFG: BB#65
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRWui %WZR, %X8<kill>, 0; mem:ST4[%85]
5376B	BB#65: derived from LLVM BB %if.end.146
	    Live Ins: %X19
	    Predecessors according to CFG: BB#63 BB#64
5392B		%vreg153<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64:%vreg153
5408B		CBZX %vreg153<kill>, <BB#67>; GPR64:%vreg153
	    Successors according to CFG: BB#67 BB#66
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> CBZX %X8<kill>, <BB#67>
5424B	BB#66: derived from LLVM BB %if.then.149
	    Live Ins: %X19
	    Predecessors according to CFG: BB#65
5440B		%vreg155<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7] GPR64common:%vreg155
5456B		STRWui %WZR, %vreg155<kill>, 1274; mem:ST4[%lastErr150] GPR64common:%vreg155
	    Successors according to CFG: BB#67
> %X8<def> = LDRXui <fi#7>, 0; mem:LD8[FixedStack7]
> STRWui %WZR, %X8<kill>, 1274; mem:ST4[%lastErr150]
5472B	BB#67: derived from LLVM BB %if.end.151
	    Live Ins: %X19
	    Predecessors according to CFG: BB#65 BB#66
5488B		%vreg157<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg157
5504B		STRWui %vreg157<kill>, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg157
5520B		B <BB#69>
	    Successors according to CFG: BB#69
> %W8<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4]
> STRWui %W8<kill>, <fi#0>, 0; mem:ST4[FixedStack0]
> B <BB#69>
5536B	BB#68: derived from LLVM BB %if.end.152
	    Live Ins: %X19
	    Predecessors according to CFG: BB#62
5552B		B <BB#25>
	    Successors according to CFG: BB#25
> B <BB#25>
5568B	BB#69: derived from LLVM BB %return
	    Live Ins: %X19
	    Predecessors according to CFG: BB#38 BB#67 BB#61 BB#55 BB#46 BB#30 BB#23 BB#17 BB#11
5584B		%vreg238<def> = ADRP <ga:@BZ2_bzRead>[TF=1]; GPR64common:%vreg238
5600B		%vreg240<def> = ADDXri %vreg238<kill>, <ga:@BZ2_bzRead>[TF=34], 0; GPR64sp:%vreg240 GPR64common:%vreg238
5648B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5664B		%X0<def> = COPY %vreg240<kill>; GPR64sp:%vreg240
5680B		%X1<def> = COPY %vreg17<kill>; GPR64:%vreg17
5696B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
5712B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5728B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5744B		STACKMAP 7, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
5760B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5776B		%vreg237<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0] GPR32:%vreg237
5792B		%W0<def> = COPY %vreg237<kill>; GPR32:%vreg237
5808B		RET_ReallyLR %W0<imp-use>
> %X8<def> = ADRP <ga:@BZ2_bzRead>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@BZ2_bzRead>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19<kill>
> BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 7, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0]
> %W0<def> = COPY %W0<kill>
Deleting identity copy.
> RET_ReallyLR %W0<imp-use>
Computing live-in reg-units in ABI blocks.
0B	BB#0 W0#0 W30#0
Created 2 new intervals.
********** INTERVALS **********
W30 [0B,16r:0)[176r,176d:7)[224e,224d:4)[320r,320d:8)[384e,384d:3)[640r,640d:6)[704e,704d:2)[832r,832d:5)[880e,880d:1)  0@0B-phi 1@880e 2@704e 3@384e 4@224e 5@832r 6@640r 7@176r 8@320r
W0 [0B,32r:0)[144r,176r:6)[304r,320r:7)[320r,352r:4)[608r,640r:3)[640r,672r:2)[800r,832r:5)[944r,960r:1)  0@0B-phi 1@944r 2@640r 3@608r 4@320r 5@800r 6@144r 7@304r
%vreg0 [32r,48r:0)  0@32r
%vreg1 [48r,256r:0)  0@48r
%vreg3 [432r,448r:0)  0@432r
%vreg6 [352r,416r:0)  0@352r
%vreg7 [272r,304r:0)  0@272r
%vreg8 [64r,80r:0)  0@64r
%vreg9 [80r,96r:0)  0@80r
%vreg10 [96r,144r:0)  0@96r
%vreg11 [112r,160r:0)  0@112r
%vreg12 [16r,816r:0)  0@16r
%vreg15 [672r,672d:0)  0@672r
%vreg16 [576r,624r:0)  0@576r
%vreg17 [560r,608r:0)  0@560r
%vreg18 [496r,512r:0)  0@496r
%vreg19 [928r,928d:0)  0@928r
%vreg20 [784r,800r:0)  0@784r
%vreg21 [912r,944r:0)  0@912r
RegMasks: 176r 320r 640r 832r
********** MACHINEINSTRS **********
# Machine code for function myfeof: Post SSA
Frame Objects:
  fi#0: size=1, align=1, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=4, align=4, at location [SP]
Function Live Ins: %X0 in %vreg0, %LR in %vreg12

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %LR
16B		%vreg12<def> = COPY %LR; GPR64:%vreg12
32B		%vreg0<def> = COPY %X0; GPR64:%vreg0
48B		%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
64B		%vreg8<def> = ADRP <ga:@myfeof>[TF=1]; GPR64common:%vreg8
80B		%vreg9<def> = ADDXri %vreg8, <ga:@myfeof>[TF=34], 0; GPR64sp:%vreg9 GPR64common:%vreg8
96B		%vreg10<def> = COPY %vreg9; GPR64all:%vreg10 GPR64sp:%vreg9
112B		%vreg11<def> = COPY %vreg12; GPR64all:%vreg11 GPR64:%vreg12
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		%X0<def> = COPY %vreg10; GPR64all:%vreg10
160B		%X1<def> = COPY %vreg11; GPR64all:%vreg11
176B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
224B		STACKMAP 0, 0, 0, <fi#2>, 0, %vreg1, 0, <fi#1>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack1] LD8[FixedStack0](align=1) GPR64:%vreg1
240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
256B		STRXui %vreg1, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg1
272B		%vreg7<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg7
288B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
304B		%X0<def> = COPY %vreg7; GPR64:%vreg7
320B		BL <ga:@fgetc>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
336B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
352B		%vreg6<def> = COPY %W0; GPR32:%vreg6
368B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
384B		STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack1] LD8[FixedStack0](align=1)
400B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
416B		STRWui %vreg6, <fi#2>, 0; mem:ST4[FixedStack2] GPR32:%vreg6
432B		%vreg3<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32common:%vreg3
448B		%WZR<def> = ADDSWri %vreg3, 1, 0, %NZCV<imp-def>; GPR32common:%vreg3
464B		Bcc 1, <BB#2>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

480B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
496B		%vreg18<def> = MOVi32imm 1; GPR32:%vreg18
512B		STRBBui %vreg18, <fi#0>, 0; mem:ST1[FixedStack0] GPR32:%vreg18
528B		B <BB#3>
	    Successors according to CFG: BB#3

544B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0
560B		%vreg17<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg17
576B		%vreg16<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg16
592B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
608B		%W0<def> = COPY %vreg17; GPR32:%vreg17
624B		%X1<def> = COPY %vreg16; GPR64:%vreg16
640B		BL <ga:@ungetc>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use,kill>, %W0<imp-def>
656B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
672B		%vreg15<def,dead> = COPY %W0; GPR32all:%vreg15
688B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
704B		STACKMAP 2, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=1)
720B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
736B		STRBBui %WZR, <fi#0>, 0; mem:ST1[FixedStack0]
	    Successors according to CFG: BB#3

752B	BB#3: derived from LLVM BB %return
	    Predecessors according to CFG: BB#2 BB#1
768B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
784B		%vreg20<def> = MOVaddr <ga:@myfeof>[TF=1], <ga:@myfeof>[TF=34]; GPR64:%vreg20
800B		%X0<def> = COPY %vreg20; GPR64:%vreg20
816B		%X1<def> = COPY %vreg12; GPR64:%vreg12
832B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %SP<imp-def>
848B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
864B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
880B		STACKMAP 3, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=1)
896B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
912B		%vreg21<def> = LDRBBui <fi#0>, 0; mem:LD1[%retval] GPR32:%vreg21
928B		%vreg19<def,dead> = COPY %vreg21; GPR32all:%vreg19 GPR32:%vreg21
944B		%W0<def> = COPY %vreg21; GPR32:%vreg21
960B		RET_ReallyLR %W0<imp-use>

# End machine code for function myfeof.

********** SIMPLE REGISTER COALESCING **********
********** Function: myfeof
********** JOINING INTERVALS ***********
entry:
16B	%vreg12<def> = COPY %LR; GPR64:%vreg12
	Considering merging %vreg12 with %LR
	Can only merge into reserved registers.
32B	%vreg0<def> = COPY %X0; GPR64:%vreg0
	Considering merging %vreg0 with %X0
	Can only merge into reserved registers.
144B	%X0<def> = COPY %vreg10; GPR64all:%vreg10
	Considering merging %vreg10 with %X0
	Can only merge into reserved registers.
160B	%X1<def> = COPY %vreg11; GPR64all:%vreg11
	Considering merging %vreg11 with %X1
	Can only merge into reserved registers.
304B	%X0<def> = COPY %vreg7; GPR64:%vreg7
	Considering merging %vreg7 with %X0
	Can only merge into reserved registers.
352B	%vreg6<def> = COPY %W0; GPR32:%vreg6
	Considering merging %vreg6 with %W0
	Can only merge into reserved registers.
if.then:
if.end:
608B	%W0<def> = COPY %vreg17; GPR32:%vreg17
	Considering merging %vreg17 with %W0
	Can only merge into reserved registers.
624B	%X1<def> = COPY %vreg16; GPR64:%vreg16
	Considering merging %vreg16 with %X1
	Can only merge into reserved registers.
672B	%vreg15<def,dead> = COPY %W0; GPR32all:%vreg15
	Considering merging %vreg15 with %W0
	Can only merge into reserved registers.
return:
800B	%X0<def> = COPY %vreg20; GPR64:%vreg20
	Considering merging %vreg20 with %X0
	Can only merge into reserved registers.
816B	%X1<def> = COPY %vreg12; GPR64:%vreg12
	Considering merging %vreg12 with %X1
	Can only merge into reserved registers.
944B	%W0<def> = COPY %vreg21; GPR32:%vreg21
	Considering merging %vreg21 with %W0
	Can only merge into reserved registers.
48B	%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
	Considering merging to GPR64 with %vreg0 in %vreg1
		RHS = %vreg0 [32r,48r:0)  0@32r
		LHS = %vreg1 [48r,256r:0)  0@48r
		merge %vreg1:0@48r into %vreg0:0@32r --> @32r
		erased:	48r	%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
		updated: 32B	%vreg1<def> = COPY %X0; GPR64:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [32r,256r:0)  0@32r
96B	%vreg10<def> = COPY %vreg9; GPR64all:%vreg10 GPR64sp:%vreg9
	Considering merging to GPR64sp with %vreg9 in %vreg10
		RHS = %vreg9 [80r,96r:0)  0@80r
		LHS = %vreg10 [96r,144r:0)  0@96r
		merge %vreg10:0@96r into %vreg9:0@80r --> @80r
		erased:	96r	%vreg10<def> = COPY %vreg9; GPR64all:%vreg10 GPR64sp:%vreg9
		updated: 80B	%vreg10<def> = ADDXri %vreg8, <ga:@myfeof>[TF=34], 0; GPR64sp:%vreg10 GPR64common:%vreg8
	Success: %vreg9 -> %vreg10
	Result = %vreg10 [80r,144r:0)  0@80r
112B	%vreg11<def> = COPY %vreg12; GPR64all:%vreg11 GPR64:%vreg12
	Considering merging to GPR64 with %vreg12 in %vreg11
		RHS = %vreg12 [16r,816r:0)  0@16r
		LHS = %vreg11 [112r,160r:0)  0@112r
		merge %vreg11:0@112r into %vreg12:0@16r --> @16r
		erased:	112r	%vreg11<def> = COPY %vreg12; GPR64all:%vreg11 GPR64:%vreg12
		updated: 16B	%vreg11<def> = COPY %LR; GPR64:%vreg11
		updated: 816B	%X1<def> = COPY %vreg11; GPR64:%vreg11
	Success: %vreg12 -> %vreg11
	Result = %vreg11 [16r,816r:0)  0@16r
928B	%vreg19<def,dead> = COPY %vreg21; GPR32all:%vreg19 GPR32:%vreg21
	Copy is dead.
Deleting dead def 928r	%vreg19<def,dead> = COPY %vreg21; GPR32all:%vreg19 GPR32:%vreg21
Shrink: %vreg21 [912r,944r:0)  0@912r
Shrunk: %vreg21 [912r,944r:0)  0@912r
144B	%X0<def> = COPY %vreg10; GPR64sp:%vreg10
	Considering merging %vreg10 with %X0
	Can only merge into reserved registers.
160B	%X1<def> = COPY %vreg11; GPR64:%vreg11
	Considering merging %vreg11 with %X1
	Can only merge into reserved registers.
816B	%X1<def> = COPY %vreg11; GPR64:%vreg11
	Considering merging %vreg11 with %X1
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
W30 [0B,16r:0)[176r,176d:7)[224e,224d:4)[320r,320d:8)[384e,384d:3)[640r,640d:6)[704e,704d:2)[832r,832d:5)[880e,880d:1)  0@0B-phi 1@880e 2@704e 3@384e 4@224e 5@832r 6@640r 7@176r 8@320r
W0 [0B,32r:0)[144r,176r:6)[304r,320r:7)[320r,352r:4)[608r,640r:3)[640r,672r:2)[800r,832r:5)[944r,960r:1)  0@0B-phi 1@944r 2@640r 3@608r 4@320r 5@800r 6@144r 7@304r
%vreg1 [32r,256r:0)  0@32r
%vreg3 [432r,448r:0)  0@432r
%vreg6 [352r,416r:0)  0@352r
%vreg7 [272r,304r:0)  0@272r
%vreg8 [64r,80r:0)  0@64r
%vreg10 [80r,144r:0)  0@80r
%vreg11 [16r,816r:0)  0@16r
%vreg15 [672r,672d:0)  0@672r
%vreg16 [576r,624r:0)  0@576r
%vreg17 [560r,608r:0)  0@560r
%vreg18 [496r,512r:0)  0@496r
%vreg20 [784r,800r:0)  0@784r
%vreg21 [912r,944r:0)  0@912r
RegMasks: 176r 320r 640r 832r
********** MACHINEINSTRS **********
# Machine code for function myfeof: Post SSA
Frame Objects:
  fi#0: size=1, align=1, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=4, align=4, at location [SP]
Function Live Ins: %X0 in %vreg0, %LR in %vreg12

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %LR
16B		%vreg11<def> = COPY %LR; GPR64:%vreg11
32B		%vreg1<def> = COPY %X0; GPR64:%vreg1
64B		%vreg8<def> = ADRP <ga:@myfeof>[TF=1]; GPR64common:%vreg8
80B		%vreg10<def> = ADDXri %vreg8, <ga:@myfeof>[TF=34], 0; GPR64sp:%vreg10 GPR64common:%vreg8
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		%X0<def> = COPY %vreg10; GPR64sp:%vreg10
160B		%X1<def> = COPY %vreg11; GPR64:%vreg11
176B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
224B		STACKMAP 0, 0, 0, <fi#2>, 0, %vreg1, 0, <fi#1>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack1] LD8[FixedStack0](align=1) GPR64:%vreg1
240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
256B		STRXui %vreg1, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg1
272B		%vreg7<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg7
288B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
304B		%X0<def> = COPY %vreg7; GPR64:%vreg7
320B		BL <ga:@fgetc>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
336B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
352B		%vreg6<def> = COPY %W0; GPR32:%vreg6
368B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
384B		STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack1] LD8[FixedStack0](align=1)
400B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
416B		STRWui %vreg6, <fi#2>, 0; mem:ST4[FixedStack2] GPR32:%vreg6
432B		%vreg3<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32common:%vreg3
448B		%WZR<def> = ADDSWri %vreg3, 1, 0, %NZCV<imp-def>; GPR32common:%vreg3
464B		Bcc 1, <BB#2>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

480B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
496B		%vreg18<def> = MOVi32imm 1; GPR32:%vreg18
512B		STRBBui %vreg18, <fi#0>, 0; mem:ST1[FixedStack0] GPR32:%vreg18
528B		B <BB#3>
	    Successors according to CFG: BB#3

544B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0
560B		%vreg17<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg17
576B		%vreg16<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg16
592B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
608B		%W0<def> = COPY %vreg17; GPR32:%vreg17
624B		%X1<def> = COPY %vreg16; GPR64:%vreg16
640B		BL <ga:@ungetc>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use,kill>, %W0<imp-def>
656B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
672B		%vreg15<def,dead> = COPY %W0; GPR32all:%vreg15
688B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
704B		STACKMAP 2, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=1)
720B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
736B		STRBBui %WZR, <fi#0>, 0; mem:ST1[FixedStack0]
	    Successors according to CFG: BB#3

752B	BB#3: derived from LLVM BB %return
	    Predecessors according to CFG: BB#2 BB#1
768B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
784B		%vreg20<def> = MOVaddr <ga:@myfeof>[TF=1], <ga:@myfeof>[TF=34]; GPR64:%vreg20
800B		%X0<def> = COPY %vreg20; GPR64:%vreg20
816B		%X1<def> = COPY %vreg11; GPR64:%vreg11
832B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %SP<imp-def>
848B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
864B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
880B		STACKMAP 3, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=1)
896B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
912B		%vreg21<def> = LDRBBui <fi#0>, 0; mem:LD1[%retval] GPR32:%vreg21
944B		%W0<def> = COPY %vreg21; GPR32:%vreg21
960B		RET_ReallyLR %W0<imp-use>

# End machine code for function myfeof.

********** GREEDY REGISTER ALLOCATION **********
********** Function: myfeof
********** INTERVALS **********
W30 [0B,16r:0)[176r,176d:7)[224e,224d:4)[320r,320d:8)[384e,384d:3)[640r,640d:6)[704e,704d:2)[832r,832d:5)[880e,880d:1)  0@0B-phi 1@880e 2@704e 3@384e 4@224e 5@832r 6@640r 7@176r 8@320r
W0 [0B,32r:0)[144r,176r:6)[304r,320r:7)[320r,352r:4)[608r,640r:3)[640r,672r:2)[800r,832r:5)[944r,960r:1)  0@0B-phi 1@944r 2@640r 3@608r 4@320r 5@800r 6@144r 7@304r
%vreg1 [32r,256r:0)  0@32r
%vreg3 [432r,448r:0)  0@432r
%vreg6 [352r,416r:0)  0@352r
%vreg7 [272r,304r:0)  0@272r
%vreg8 [64r,80r:0)  0@64r
%vreg10 [80r,144r:0)  0@80r
%vreg11 [16r,816r:0)  0@16r
%vreg15 [672r,672d:0)  0@672r
%vreg16 [576r,624r:0)  0@576r
%vreg17 [560r,608r:0)  0@560r
%vreg18 [496r,512r:0)  0@496r
%vreg20 [784r,800r:0)  0@784r
%vreg21 [912r,944r:0)  0@912r
RegMasks: 176r 320r 640r 832r
********** MACHINEINSTRS **********
# Machine code for function myfeof: Post SSA
Frame Objects:
  fi#0: size=1, align=1, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=4, align=4, at location [SP]
Function Live Ins: %X0 in %vreg0, %LR in %vreg12

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %LR
16B		%vreg11<def> = COPY %LR; GPR64:%vreg11
32B		%vreg1<def> = COPY %X0; GPR64:%vreg1
64B		%vreg8<def> = ADRP <ga:@myfeof>[TF=1]; GPR64common:%vreg8
80B		%vreg10<def> = ADDXri %vreg8, <ga:@myfeof>[TF=34], 0; GPR64sp:%vreg10 GPR64common:%vreg8
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		%X0<def> = COPY %vreg10; GPR64sp:%vreg10
160B		%X1<def> = COPY %vreg11; GPR64:%vreg11
176B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
224B		STACKMAP 0, 0, 0, <fi#2>, 0, %vreg1, 0, <fi#1>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack1] LD8[FixedStack0](align=1) GPR64:%vreg1
240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
256B		STRXui %vreg1, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg1
272B		%vreg7<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg7
288B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
304B		%X0<def> = COPY %vreg7; GPR64:%vreg7
320B		BL <ga:@fgetc>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
336B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
352B		%vreg6<def> = COPY %W0; GPR32:%vreg6
368B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
384B		STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack1] LD8[FixedStack0](align=1)
400B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
416B		STRWui %vreg6, <fi#2>, 0; mem:ST4[FixedStack2] GPR32:%vreg6
432B		%vreg3<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32common:%vreg3
448B		%WZR<def> = ADDSWri %vreg3, 1, 0, %NZCV<imp-def>; GPR32common:%vreg3
464B		Bcc 1, <BB#2>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

480B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
496B		%vreg18<def> = MOVi32imm 1; GPR32:%vreg18
512B		STRBBui %vreg18, <fi#0>, 0; mem:ST1[FixedStack0] GPR32:%vreg18
528B		B <BB#3>
	    Successors according to CFG: BB#3

544B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0
560B		%vreg17<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg17
576B		%vreg16<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg16
592B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
608B		%W0<def> = COPY %vreg17; GPR32:%vreg17
624B		%X1<def> = COPY %vreg16; GPR64:%vreg16
640B		BL <ga:@ungetc>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use,kill>, %W0<imp-def>
656B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
672B		%vreg15<def,dead> = COPY %W0; GPR32all:%vreg15
688B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
704B		STACKMAP 2, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=1)
720B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
736B		STRBBui %WZR, <fi#0>, 0; mem:ST1[FixedStack0]
	    Successors according to CFG: BB#3

752B	BB#3: derived from LLVM BB %return
	    Predecessors according to CFG: BB#2 BB#1
768B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
784B		%vreg20<def> = MOVaddr <ga:@myfeof>[TF=1], <ga:@myfeof>[TF=34]; GPR64:%vreg20
800B		%X0<def> = COPY %vreg20; GPR64:%vreg20
816B		%X1<def> = COPY %vreg11; GPR64:%vreg11
832B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %SP<imp-def>
848B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
864B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
880B		STACKMAP 3, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=1)
896B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
912B		%vreg21<def> = LDRBBui <fi#0>, 0; mem:LD1[%retval] GPR32:%vreg21
944B		%W0<def> = COPY %vreg21; GPR32:%vreg21
960B		RET_ReallyLR %W0<imp-use>

# End machine code for function myfeof.


selectOrSplit GPR64:%vreg11 [16r,816r:0)  0@16r w=2.525000e-03
hints: %X1
missed hint %X1
assigning %vreg11 to %X19: W19 [16r,816r:0)  0@16r

selectOrSplit GPR64:%vreg1 [32r,256r:0)  0@32r w=4.855769e-03
hints: %X0
missed hint %X0
assigning %vreg1 to %X20: W20 [32r,256r:0)  0@32r

selectOrSplit GPR64sp:%vreg10 [80r,144r:0)  0@80r w=4.353448e-03
hints: %X0
assigning %vreg10 to %X0: W0 [80r,144r:0)  0@80r

selectOrSplit GPR64:%vreg7 [272r,304r:0)  0@272r w=4.675926e-03
hints: %X0
assigning %vreg7 to %X0: W0 [272r,304r:0)  0@272r

selectOrSplit GPR32:%vreg6 [352r,416r:0)  0@352r w=4.353448e-03
hints: %W0
assigning %vreg6 to %W0: W0 [352r,416r:0)  0@352r

selectOrSplit GPR32:%vreg17 [560r,608r:0)  0@560r w=2.254464e-03
hints: %W0
assigning %vreg17 to %W0: W0 [560r,608r:0)  0@560r

selectOrSplit GPR64:%vreg16 [576r,624r:0)  0@576r w=2.254464e-03
hints: %X1
assigning %vreg16 to %X1: W1 [576r,624r:0)  0@576r

selectOrSplit GPR32all:%vreg15 [672r,672d:0)  0@672r w=inf
hints: %W0
assigning %vreg15 to %W0: W0 [672r,672d:0)  0@672r

selectOrSplit GPR64:%vreg20 [784r,800r:0)  0@784r w=inf
hints: %X0
assigning %vreg20 to %X0: W0 [784r,800r:0)  0@784r

selectOrSplit GPR32:%vreg21 [912r,944r:0)  0@912r w=inf
hints: %W0
assigning %vreg21 to %W0: W0 [912r,944r:0)  0@912r

selectOrSplit GPR64common:%vreg8 [64r,80r:0)  0@64r w=inf
assigning %vreg8 to %X8: W8 [64r,80r:0)  0@64r

selectOrSplit GPR32common:%vreg3 [432r,448r:0)  0@432r w=inf
assigning %vreg3 to %W8: W8 [432r,448r:0)  0@432r

selectOrSplit GPR32:%vreg18 [496r,512r:0)  0@496r w=inf
assigning %vreg18 to %W8: W8 [496r,512r:0)  0@496r

********** STACK TRANSFORMATION METADATA **********
********** Function: myfeof
********** REGISTER MAP **********
[%vreg1 -> %X20] GPR64
[%vreg3 -> %W8] GPR32common
[%vreg6 -> %W0] GPR32
[%vreg7 -> %X0] GPR64
[%vreg8 -> %X8] GPR64common
[%vreg10 -> %X0] GPR64sp
[%vreg11 -> %X19] GPR64
[%vreg15 -> %W0] GPR32all
[%vreg16 -> %X1] GPR64
[%vreg17 -> %W0] GPR32
[%vreg18 -> %W8] GPR32
[%vreg20 -> %X0] GPR64
[%vreg21 -> %W0] GPR32


Stackmap 0:
  STACKMAP 0, 0, 0, <fi#2>, 0, %vreg1, 0, <fi#1>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack1] LD8[FixedStack0](align=1) GPR64:%vreg1

i32* %c: in stack slot 2 (size: 4)
%struct._IO_FILE* %f: in register %X20 (vreg 1)
%struct._IO_FILE** %f.addr: in stack slot 1 (size: 8)
i8* %retval: in stack slot 0 (size: 1)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack1] LD8[FixedStack0](align=1)

i32* %c: in stack slot 2 (size: 4)
%struct._IO_FILE** %f.addr: in stack slot 1 (size: 8)
i8* %retval: in stack slot 0 (size: 1)

Duplicate operand locations:


Stackmap 2:
  STACKMAP 2, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=1)

i8* %retval: in stack slot 0 (size: 1)

Duplicate operand locations:


Stackmap 3:
  STACKMAP 3, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=1)

i8* %retval: in stack slot 0 (size: 1)

Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, 0, <fi#2>, 0, %vreg1, 0, <fi#1>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack1] LD8[FixedStack0](align=1) GPR64:%vreg1
  -> Call instruction SlotIndex 176B, searching vregs 0 -> 22 and stack slots 0 -> 3
    + vreg11 is live in register but not in stackmap
      Defining instruction: %vreg11<def> = COPY %LR; GPR64:%vreg11
      Value: generated value, 1 instruction(s)

  STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack1] LD8[FixedStack0](align=1)
  -> Call instruction SlotIndex 320B, searching vregs 0 -> 22 and stack slots 0 -> 3
    + vreg11 is live in register but not in stackmap
      Defining instruction: %vreg11<def> = COPY %LR; GPR64:%vreg11
      Value: generated value, 1 instruction(s)

  STACKMAP 2, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=1)
  -> Call instruction SlotIndex 640B, searching vregs 0 -> 22 and stack slots 0 -> 3
    + vreg11 is live in register but not in stackmap
      Defining instruction: %vreg11<def> = COPY %LR; GPR64:%vreg11
      Value: generated value, 1 instruction(s)

  STACKMAP 3, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=1)
  -> Call instruction SlotIndex 832B, searching vregs 0 -> 22 and stack slots 0 -> 3

********** REWRITE VIRTUAL REGISTERS **********
********** Function: myfeof
********** REGISTER MAP **********
[%vreg1 -> %X20] GPR64
[%vreg3 -> %W8] GPR32common
[%vreg6 -> %W0] GPR32
[%vreg7 -> %X0] GPR64
[%vreg8 -> %X8] GPR64common
[%vreg10 -> %X0] GPR64sp
[%vreg11 -> %X19] GPR64
[%vreg15 -> %W0] GPR32all
[%vreg16 -> %X1] GPR64
[%vreg17 -> %W0] GPR32
[%vreg18 -> %W8] GPR32
[%vreg20 -> %X0] GPR64
[%vreg21 -> %W0] GPR32

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %LR %X0
16B		%vreg11<def> = COPY %LR; GPR64:%vreg11
32B		%vreg1<def> = COPY %X0; GPR64:%vreg1
64B		%vreg8<def> = ADRP <ga:@myfeof>[TF=1]; GPR64common:%vreg8
80B		%vreg10<def> = ADDXri %vreg8<kill>, <ga:@myfeof>[TF=34], 0; GPR64sp:%vreg10 GPR64common:%vreg8
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		%X0<def> = COPY %vreg10<kill>; GPR64sp:%vreg10
160B		%X1<def> = COPY %vreg11; GPR64:%vreg11
176B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
224B		STACKMAP 0, 0, 0, <fi#2>, 0, %vreg1, 0, <fi#1>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack1] LD8[FixedStack0](align=1) GPR64:%vreg1
240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
256B		STRXui %vreg1<kill>, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg1
272B		%vreg7<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg7
288B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
304B		%X0<def> = COPY %vreg7<kill>; GPR64:%vreg7
320B		BL <ga:@fgetc>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
336B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
352B		%vreg6<def> = COPY %W0; GPR32:%vreg6
368B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
384B		STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack1] LD8[FixedStack0](align=1)
400B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
416B		STRWui %vreg6<kill>, <fi#2>, 0; mem:ST4[FixedStack2] GPR32:%vreg6
432B		%vreg3<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32common:%vreg3
448B		%WZR<def> = ADDSWri %vreg3<kill>, 1, 0, %NZCV<imp-def>; GPR32common:%vreg3
464B		Bcc 1, <BB#2>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1
> %X19<def> = COPY %LR
> %X20<def> = COPY %X0
> %X8<def> = ADRP <ga:@myfeof>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@myfeof>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19
> BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 0, 0, 0, <fi#2>, 0, %X20, 0, <fi#1>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack1] LD8[FixedStack0](align=1)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRXui %X20<kill>, <fi#1>, 0; mem:ST8[FixedStack1]
> %X0<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BL <ga:@fgetc>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = COPY %W0
Deleting identity copy.
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack1] LD8[FixedStack0](align=1)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRWui %W0<kill>, <fi#2>, 0; mem:ST4[FixedStack2]
> %W8<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2]
> %WZR<def> = ADDSWri %W8<kill>, 1, 0, %NZCV<imp-def>
> Bcc 1, <BB#2>, %NZCV<imp-use,kill>
480B	BB#1: derived from LLVM BB %if.then
	    Live Ins: %X19
	    Predecessors according to CFG: BB#0
496B		%vreg18<def> = MOVi32imm 1; GPR32:%vreg18
512B		STRBBui %vreg18<kill>, <fi#0>, 0; mem:ST1[FixedStack0] GPR32:%vreg18
528B		B <BB#3>
	    Successors according to CFG: BB#3
> %W8<def> = MOVi32imm 1
> STRBBui %W8<kill>, <fi#0>, 0; mem:ST1[FixedStack0]
> B <BB#3>
544B	BB#2: derived from LLVM BB %if.end
	    Live Ins: %X19
	    Predecessors according to CFG: BB#0
560B		%vreg17<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg17
576B		%vreg16<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg16
592B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
608B		%W0<def> = COPY %vreg17<kill>; GPR32:%vreg17
624B		%X1<def> = COPY %vreg16<kill>; GPR64:%vreg16
640B		BL <ga:@ungetc>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use>, %W0<imp-def>
656B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
672B		%vreg15<def,dead> = COPY %W0; GPR32all:%vreg15
688B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
704B		STACKMAP 2, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=1)
720B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
736B		STRBBui %WZR, <fi#0>, 0; mem:ST1[FixedStack0]
	    Successors according to CFG: BB#3
> %W0<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2]
> %X1<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = COPY %W0<kill>
Deleting identity copy.
> %X1<def> = COPY %X1<kill>
Deleting identity copy.
> BL <ga:@ungetc>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use>, %W0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def,dead> = COPY %W0
Deleting identity copy.
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 2, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=1)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRBBui %WZR, <fi#0>, 0; mem:ST1[FixedStack0]
752B	BB#3: derived from LLVM BB %return
	    Live Ins: %X19
	    Predecessors according to CFG: BB#2 BB#1
768B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
784B		%vreg20<def> = MOVaddr <ga:@myfeof>[TF=1], <ga:@myfeof>[TF=34]; GPR64:%vreg20
800B		%X0<def> = COPY %vreg20<kill>; GPR64:%vreg20
816B		%X1<def> = COPY %vreg11<kill>; GPR64:%vreg11
832B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %SP<imp-def>
848B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
864B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
880B		STACKMAP 3, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=1)
896B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
912B		%vreg21<def> = LDRBBui <fi#0>, 0; mem:LD1[%retval] GPR32:%vreg21
944B		%W0<def> = COPY %vreg21<kill>; GPR32:%vreg21
960B		RET_ReallyLR %W0<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = MOVaddr <ga:@myfeof>[TF=1], <ga:@myfeof>[TF=34]
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19<kill>
> BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %SP<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 3, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=1)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = LDRBBui <fi#0>, 0; mem:LD1[%retval]
> %W0<def> = COPY %W0<kill>
Deleting identity copy.
> RET_ReallyLR %W0<imp-use>
Computing live-in reg-units in ABI blocks.
0B	BB#0 W0#0 W1#0 W2#0 W3#0 W30#0
Created 5 new intervals.
********** INTERVALS **********
W30 [0B,16r:0)[272r,272d:4)[320e,320d:1)[1904r,1904d:2)[1952e,1952d:3)  0@0B-phi 1@320e 2@1904r 3@1952e 4@272r
W0 [0B,80r:0)[240r,272r:2)[1872r,1904r:1)  0@0B-phi 1@1872r 2@240r
W1 [0B,64r:0)[256r,272r:2)[1888r,1904r:1)  0@0B-phi 1@1888r 2@256r
W2 [0B,48r:0)  0@0B-phi
W3 [0B,32r:0)  0@0B-phi
%vreg0 [80r,96r:0)  0@80r
%vreg1 [96r,352r:0)  0@96r
%vreg2 [64r,112r:0)  0@64r
%vreg3 [112r,368r:0)  0@112r
%vreg4 [48r,128r:0)  0@48r
%vreg5 [128r,384r:0)  0@128r
%vreg6 [32r,144r:0)  0@32r
%vreg7 [144r,400r:0)  0@144r
%vreg9 [464r,480r:0)  0@464r
%vreg12 [432r,448r:0)  0@432r
%vreg13 [416r,432r:0)  0@416r
%vreg14 [160r,176r:0)  0@160r
%vreg15 [176r,192r:0)  0@176r
%vreg16 [192r,240r:0)  0@192r
%vreg17 [208r,256r:0)  0@208r
%vreg18 [16r,1840r:0)  0@16r
%vreg21 [784r,800r:0)  0@784r
%vreg22 [768r,784r:0)  0@768r
%vreg24 [1104r,1120r:0)  0@1104r
%vreg26 [1152r,1168r:0)  0@1152r
%vreg28 [1456r,1472r:0)  0@1456r
%vreg30 [1504r,1520r:0)  0@1504r
%vreg32 [1552r,1568r:0)  0@1552r
%vreg34 [1600r,1616r:0)  0@1600r
%vreg37 [1744r,1760r:0)  0@1744r
%vreg39 [1728r,1760r:0)  0@1728r
%vreg40 [1712r,1728r:0)  0@1712r
%vreg43 [1680r,1696r:0)  0@1680r
%vreg45 [1664r,1696r:0)  0@1664r
%vreg46 [1648r,1664r:0)  0@1648r
%vreg48 [1200r,1216r:0)  0@1200r
%vreg49 [1248r,1280r:0)  0@1248r
%vreg51 [1264r,1280r:0)  0@1264r
%vreg53 [1312r,1328r:0)  0@1312r
%vreg54 [1360r,1392r:0)  0@1360r
%vreg56 [1376r,1392r:0)  0@1376r
%vreg58 [848r,864r:0)  0@848r
%vreg59 [896r,928r:0)  0@896r
%vreg61 [912r,928r:0)  0@912r
%vreg63 [960r,976r:0)  0@960r
%vreg64 [1008r,1040r:0)  0@1008r
%vreg66 [1024r,1040r:0)  0@1024r
%vreg68 [512r,528r:0)  0@512r
%vreg69 [560r,592r:0)  0@560r
%vreg71 [576r,592r:0)  0@576r
%vreg73 [624r,640r:0)  0@624r
%vreg74 [672r,704r:0)  0@672r
%vreg76 [688r,704r:0)  0@688r
%vreg77 [1792r,1808r:0)  0@1792r
%vreg78 [1808r,1824r:0)  0@1808r
%vreg79 [1824r,1872r:0)  0@1824r
%vreg80 [1840r,1888r:0)  0@1840r
RegMasks: 272r 1904r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzReadGetUnused: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=8, align=8, at location [SP]
  fi#3: size=8, align=8, at location [SP]
  fi#4: size=8, align=8, at location [SP]
Function Live Ins: %X0 in %vreg0, %X1 in %vreg2, %X2 in %vreg4, %X3 in %vreg6, %LR in %vreg18

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %X1 %X2 %X3 %LR
16B		%vreg18<def> = COPY %LR; GPR64:%vreg18
32B		%vreg6<def> = COPY %X3; GPR64:%vreg6
48B		%vreg4<def> = COPY %X2; GPR64:%vreg4
64B		%vreg2<def> = COPY %X1; GPR64:%vreg2
80B		%vreg0<def> = COPY %X0; GPR64:%vreg0
96B		%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
112B		%vreg3<def> = COPY %vreg2; GPR64:%vreg3,%vreg2
128B		%vreg5<def> = COPY %vreg4; GPR64:%vreg5,%vreg4
144B		%vreg7<def> = COPY %vreg6; GPR64:%vreg7,%vreg6
160B		%vreg14<def> = ADRP <ga:@BZ2_bzReadGetUnused>[TF=1]; GPR64common:%vreg14
176B		%vreg15<def> = ADDXri %vreg14, <ga:@BZ2_bzReadGetUnused>[TF=34], 0; GPR64sp:%vreg15 GPR64common:%vreg14
192B		%vreg16<def> = COPY %vreg15; GPR64all:%vreg16 GPR64sp:%vreg15
208B		%vreg17<def> = COPY %vreg18; GPR64all:%vreg17 GPR64:%vreg18
224B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
240B		%X0<def> = COPY %vreg16; GPR64all:%vreg16
256B		%X1<def> = COPY %vreg17; GPR64all:%vreg17
272B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
288B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
304B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
320B		STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#4>, 0, %vreg7, 0, <fi#3>, 0, %vreg5, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack2] GPR64:%vreg3,%vreg1,%vreg7,%vreg5
336B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
352B		STRXui %vreg1, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg1
368B		STRXui %vreg3, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg3
384B		STRXui %vreg5, <fi#2>, 0; mem:ST8[FixedStack2] GPR64:%vreg5
400B		STRXui %vreg7, <fi#3>, 0; mem:ST8[FixedStack3] GPR64:%vreg7
416B		%vreg13<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg13
432B		%vreg12<def> = COPY %vreg13; GPR64:%vreg12,%vreg13
448B		STRXui %vreg12, <fi#4>, 0; mem:ST8[FixedStack4] GPR64:%vreg12
464B		%vreg9<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64:%vreg9
480B		CBNZX %vreg9, <BB#6>; GPR64:%vreg9
	    Successors according to CFG: BB#6 BB#1

496B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
512B		%vreg68<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg68
528B		CBZX %vreg68, <BB#3>; GPR64:%vreg68
	    Successors according to CFG: BB#3 BB#2

544B	BB#2: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#1
560B		%vreg69<def> = MOVi32imm 4294967294; GPR32:%vreg69
576B		%vreg71<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg71
592B		STRWui %vreg69, %vreg71, 0; mem:ST4[%4] GPR32:%vreg69 GPR64common:%vreg71
	    Successors according to CFG: BB#3

608B	BB#3: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#1 BB#2
624B		%vreg73<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64:%vreg73
640B		CBZX %vreg73, <BB#5>; GPR64:%vreg73
	    Successors according to CFG: BB#5 BB#4

656B	BB#4: derived from LLVM BB %if.then.4
	    Predecessors according to CFG: BB#3
672B		%vreg74<def> = MOVi32imm 4294967294; GPR32:%vreg74
688B		%vreg76<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg76
704B		STRWui %vreg74, %vreg76, 1274; mem:ST4[%lastErr] GPR32:%vreg74 GPR64common:%vreg76
	    Successors according to CFG: BB#5

720B	BB#5: derived from LLVM BB %if.end.5
	    Predecessors according to CFG: BB#3 BB#4
736B		B <BB#24>
	    Successors according to CFG: BB#24

752B	BB#6: derived from LLVM BB %if.end.6
	    Predecessors according to CFG: BB#0
768B		%vreg22<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg22
784B		%vreg21<def> = LDRWui %vreg22, 1274; mem:LD4[%lastErr7] GPR32common:%vreg21 GPR64common:%vreg22
800B		%WZR<def> = SUBSWri %vreg21, 4, 0, %NZCV<imp-def>; GPR32common:%vreg21
816B		Bcc 0, <BB#12>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#12 BB#7

832B	BB#7: derived from LLVM BB %if.then.9
	    Predecessors according to CFG: BB#6
848B		%vreg58<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg58
864B		CBZX %vreg58, <BB#9>; GPR64:%vreg58
	    Successors according to CFG: BB#9 BB#8

880B	BB#8: derived from LLVM BB %if.then.11
	    Predecessors according to CFG: BB#7
896B		%vreg59<def> = MOVi32imm 4294967295; GPR32:%vreg59
912B		%vreg61<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg61
928B		STRWui %vreg59, %vreg61, 0; mem:ST4[%10] GPR32:%vreg59 GPR64common:%vreg61
	    Successors according to CFG: BB#9

944B	BB#9: derived from LLVM BB %if.end.12
	    Predecessors according to CFG: BB#7 BB#8
960B		%vreg63<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64:%vreg63
976B		CBZX %vreg63, <BB#11>; GPR64:%vreg63
	    Successors according to CFG: BB#11 BB#10

992B	BB#10: derived from LLVM BB %if.then.14
	    Predecessors according to CFG: BB#9
1008B		%vreg64<def> = MOVi32imm 4294967295; GPR32:%vreg64
1024B		%vreg66<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg66
1040B		STRWui %vreg64, %vreg66, 1274; mem:ST4[%lastErr15] GPR32:%vreg64 GPR64common:%vreg66
	    Successors according to CFG: BB#11

1056B	BB#11: derived from LLVM BB %if.end.16
	    Predecessors according to CFG: BB#9 BB#10
1072B		B <BB#24>
	    Successors according to CFG: BB#24

1088B	BB#12: derived from LLVM BB %if.end.17
	    Predecessors according to CFG: BB#6
1104B		%vreg24<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg24
1120B		CBZX %vreg24, <BB#14>; GPR64:%vreg24
	    Successors according to CFG: BB#14 BB#13

1136B	BB#13: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#12
1152B		%vreg26<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg26
1168B		CBNZX %vreg26, <BB#19>; GPR64:%vreg26
	    Successors according to CFG: BB#19 BB#14

1184B	BB#14: derived from LLVM BB %if.then.20
	    Predecessors according to CFG: BB#12 BB#13
1200B		%vreg48<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg48
1216B		CBZX %vreg48, <BB#16>; GPR64:%vreg48
	    Successors according to CFG: BB#16 BB#15

1232B	BB#15: derived from LLVM BB %if.then.22
	    Predecessors according to CFG: BB#14
1248B		%vreg49<def> = MOVi32imm 4294967294; GPR32:%vreg49
1264B		%vreg51<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg51
1280B		STRWui %vreg49, %vreg51, 0; mem:ST4[%16] GPR32:%vreg49 GPR64common:%vreg51
	    Successors according to CFG: BB#16

1296B	BB#16: derived from LLVM BB %if.end.23
	    Predecessors according to CFG: BB#14 BB#15
1312B		%vreg53<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64:%vreg53
1328B		CBZX %vreg53, <BB#18>; GPR64:%vreg53
	    Successors according to CFG: BB#18 BB#17

1344B	BB#17: derived from LLVM BB %if.then.25
	    Predecessors according to CFG: BB#16
1360B		%vreg54<def> = MOVi32imm 4294967294; GPR32:%vreg54
1376B		%vreg56<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg56
1392B		STRWui %vreg54, %vreg56, 1274; mem:ST4[%lastErr26] GPR32:%vreg54 GPR64common:%vreg56
	    Successors according to CFG: BB#18

1408B	BB#18: derived from LLVM BB %if.end.27
	    Predecessors according to CFG: BB#16 BB#17
1424B		B <BB#24>
	    Successors according to CFG: BB#24

1440B	BB#19: derived from LLVM BB %if.end.28
	    Predecessors according to CFG: BB#13
1456B		%vreg28<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg28
1472B		CBZX %vreg28, <BB#21>; GPR64:%vreg28
	    Successors according to CFG: BB#21 BB#20

1488B	BB#20: derived from LLVM BB %if.then.30
	    Predecessors according to CFG: BB#19
1504B		%vreg30<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg30
1520B		STRWui %WZR, %vreg30, 0; mem:ST4[%20] GPR64common:%vreg30
	    Successors according to CFG: BB#21

1536B	BB#21: derived from LLVM BB %if.end.31
	    Predecessors according to CFG: BB#19 BB#20
1552B		%vreg32<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64:%vreg32
1568B		CBZX %vreg32, <BB#23>; GPR64:%vreg32
	    Successors according to CFG: BB#23 BB#22

1584B	BB#22: derived from LLVM BB %if.then.33
	    Predecessors according to CFG: BB#21
1600B		%vreg34<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg34
1616B		STRWui %WZR, %vreg34, 1274; mem:ST4[%lastErr34] GPR64common:%vreg34
	    Successors according to CFG: BB#23

1632B	BB#23: derived from LLVM BB %if.end.35
	    Predecessors according to CFG: BB#21 BB#22
1648B		%vreg46<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg46
1664B		%vreg45<def> = LDRWui %vreg46, 1256; mem:LD4[%avail_in] GPR32:%vreg45 GPR64common:%vreg46
1680B		%vreg43<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg43
1696B		STRWui %vreg45, %vreg43, 0; mem:ST4[%25] GPR32:%vreg45 GPR64common:%vreg43
1712B		%vreg40<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg40
1728B		%vreg39<def> = LDRXui %vreg40, 627; mem:LD8[%next_in] GPR64:%vreg39 GPR64common:%vreg40
1744B		%vreg37<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg37
1760B		STRXui %vreg39, %vreg37, 0; mem:ST8[%28] GPR64:%vreg39 GPR64common:%vreg37
	    Successors according to CFG: BB#24

1776B	BB#24: derived from LLVM BB %return
	    Predecessors according to CFG: BB#23 BB#18 BB#11 BB#5
1792B		%vreg77<def> = ADRP <ga:@BZ2_bzReadGetUnused>[TF=1]; GPR64common:%vreg77
1808B		%vreg78<def> = ADDXri %vreg77, <ga:@BZ2_bzReadGetUnused>[TF=34], 0; GPR64sp:%vreg78 GPR64common:%vreg77
1824B		%vreg79<def> = COPY %vreg78; GPR64all:%vreg79 GPR64sp:%vreg78
1840B		%vreg80<def> = COPY %vreg18; GPR64all:%vreg80 GPR64:%vreg18
1856B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1872B		%X0<def> = COPY %vreg79; GPR64all:%vreg79
1888B		%X1<def> = COPY %vreg80; GPR64all:%vreg80
1904B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
1920B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1936B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1952B		STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...
1968B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1984B		RET_ReallyLR

# End machine code for function BZ2_bzReadGetUnused.

********** SIMPLE REGISTER COALESCING **********
********** Function: BZ2_bzReadGetUnused
********** JOINING INTERVALS ***********
if.end:
if.end.12:
if.then.20:
if.end.23:
if.end.31:
return:
1872B	%X0<def> = COPY %vreg79; GPR64all:%vreg79
	Considering merging %vreg79 with %X0
	Can only merge into reserved registers.
1888B	%X1<def> = COPY %vreg80; GPR64all:%vreg80
	Considering merging %vreg80 with %X1
	Can only merge into reserved registers.
if.then:
if.end.5:
if.end.6:
if.then.9:
if.end.16:
if.end.17:
lor.lhs.false:
if.end.27:
if.end.28:
if.end.35:
entry:
16B	%vreg18<def> = COPY %LR; GPR64:%vreg18
	Considering merging %vreg18 with %LR
	Can only merge into reserved registers.
32B	%vreg6<def> = COPY %X3; GPR64:%vreg6
	Considering merging %vreg6 with %X3
	Can only merge into reserved registers.
48B	%vreg4<def> = COPY %X2; GPR64:%vreg4
	Considering merging %vreg4 with %X2
	Can only merge into reserved registers.
64B	%vreg2<def> = COPY %X1; GPR64:%vreg2
	Considering merging %vreg2 with %X1
	Can only merge into reserved registers.
80B	%vreg0<def> = COPY %X0; GPR64:%vreg0
	Considering merging %vreg0 with %X0
	Can only merge into reserved registers.
240B	%X0<def> = COPY %vreg16; GPR64all:%vreg16
	Considering merging %vreg16 with %X0
	Can only merge into reserved registers.
256B	%X1<def> = COPY %vreg17; GPR64all:%vreg17
	Considering merging %vreg17 with %X1
	Can only merge into reserved registers.
if.then.2:
if.then.4:
if.then.11:
if.then.14:
if.then.22:
if.then.25:
if.then.30:
if.then.33:
1824B	%vreg79<def> = COPY %vreg78; GPR64all:%vreg79 GPR64sp:%vreg78
	Considering merging to GPR64sp with %vreg78 in %vreg79
		RHS = %vreg78 [1808r,1824r:0)  0@1808r
		LHS = %vreg79 [1824r,1872r:0)  0@1824r
		merge %vreg79:0@1824r into %vreg78:0@1808r --> @1808r
		erased:	1824r	%vreg79<def> = COPY %vreg78; GPR64all:%vreg79 GPR64sp:%vreg78
		updated: 1808B	%vreg79<def> = ADDXri %vreg77, <ga:@BZ2_bzReadGetUnused>[TF=34], 0; GPR64sp:%vreg79 GPR64common:%vreg77
	Success: %vreg78 -> %vreg79
	Result = %vreg79 [1808r,1872r:0)  0@1808r
1840B	%vreg80<def> = COPY %vreg18; GPR64all:%vreg80 GPR64:%vreg18
	Considering merging to GPR64 with %vreg18 in %vreg80
		RHS = %vreg18 [16r,1840r:0)  0@16r
		LHS = %vreg80 [1840r,1888r:0)  0@1840r
		merge %vreg80:0@1840r into %vreg18:0@16r --> @16r
		erased:	1840r	%vreg80<def> = COPY %vreg18; GPR64all:%vreg80 GPR64:%vreg18
		updated: 16B	%vreg80<def> = COPY %LR; GPR64:%vreg80
		updated: 208B	%vreg17<def> = COPY %vreg80; GPR64all:%vreg17 GPR64:%vreg80
	Success: %vreg18 -> %vreg80
	Result = %vreg80 [16r,1888r:0)  0@16r
96B	%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
	Considering merging to GPR64 with %vreg0 in %vreg1
		RHS = %vreg0 [80r,96r:0)  0@80r
		LHS = %vreg1 [96r,352r:0)  0@96r
		merge %vreg1:0@96r into %vreg0:0@80r --> @80r
		erased:	96r	%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
		updated: 80B	%vreg1<def> = COPY %X0; GPR64:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [80r,352r:0)  0@80r
112B	%vreg3<def> = COPY %vreg2; GPR64:%vreg3,%vreg2
	Considering merging to GPR64 with %vreg2 in %vreg3
		RHS = %vreg2 [64r,112r:0)  0@64r
		LHS = %vreg3 [112r,368r:0)  0@112r
		merge %vreg3:0@112r into %vreg2:0@64r --> @64r
		erased:	112r	%vreg3<def> = COPY %vreg2; GPR64:%vreg3,%vreg2
		updated: 64B	%vreg3<def> = COPY %X1; GPR64:%vreg3
	Success: %vreg2 -> %vreg3
	Result = %vreg3 [64r,368r:0)  0@64r
128B	%vreg5<def> = COPY %vreg4; GPR64:%vreg5,%vreg4
	Considering merging to GPR64 with %vreg4 in %vreg5
		RHS = %vreg4 [48r,128r:0)  0@48r
		LHS = %vreg5 [128r,384r:0)  0@128r
		merge %vreg5:0@128r into %vreg4:0@48r --> @48r
		erased:	128r	%vreg5<def> = COPY %vreg4; GPR64:%vreg5,%vreg4
		updated: 48B	%vreg5<def> = COPY %X2; GPR64:%vreg5
	Success: %vreg4 -> %vreg5
	Result = %vreg5 [48r,384r:0)  0@48r
144B	%vreg7<def> = COPY %vreg6; GPR64:%vreg7,%vreg6
	Considering merging to GPR64 with %vreg6 in %vreg7
		RHS = %vreg6 [32r,144r:0)  0@32r
		LHS = %vreg7 [144r,400r:0)  0@144r
		merge %vreg7:0@144r into %vreg6:0@32r --> @32r
		erased:	144r	%vreg7<def> = COPY %vreg6; GPR64:%vreg7,%vreg6
		updated: 32B	%vreg7<def> = COPY %X3; GPR64:%vreg7
	Success: %vreg6 -> %vreg7
	Result = %vreg7 [32r,400r:0)  0@32r
192B	%vreg16<def> = COPY %vreg15; GPR64all:%vreg16 GPR64sp:%vreg15
	Considering merging to GPR64sp with %vreg15 in %vreg16
		RHS = %vreg15 [176r,192r:0)  0@176r
		LHS = %vreg16 [192r,240r:0)  0@192r
		merge %vreg16:0@192r into %vreg15:0@176r --> @176r
		erased:	192r	%vreg16<def> = COPY %vreg15; GPR64all:%vreg16 GPR64sp:%vreg15
		updated: 176B	%vreg16<def> = ADDXri %vreg14, <ga:@BZ2_bzReadGetUnused>[TF=34], 0; GPR64sp:%vreg16 GPR64common:%vreg14
	Success: %vreg15 -> %vreg16
	Result = %vreg16 [176r,240r:0)  0@176r
208B	%vreg17<def> = COPY %vreg80; GPR64all:%vreg17 GPR64:%vreg80
	Considering merging to GPR64 with %vreg80 in %vreg17
		RHS = %vreg80 [16r,1888r:0)  0@16r
		LHS = %vreg17 [208r,256r:0)  0@208r
		merge %vreg17:0@208r into %vreg80:0@16r --> @16r
		erased:	208r	%vreg17<def> = COPY %vreg80; GPR64all:%vreg17 GPR64:%vreg80
		updated: 16B	%vreg17<def> = COPY %LR; GPR64:%vreg17
		updated: 1888B	%X1<def> = COPY %vreg17; GPR64:%vreg17
	Success: %vreg80 -> %vreg17
	Result = %vreg17 [16r,1888r:0)  0@16r
432B	%vreg12<def> = COPY %vreg13; GPR64:%vreg12,%vreg13
	Considering merging to GPR64 with %vreg13 in %vreg12
		RHS = %vreg13 [416r,432r:0)  0@416r
		LHS = %vreg12 [432r,448r:0)  0@432r
		merge %vreg12:0@432r into %vreg13:0@416r --> @416r
		erased:	432r	%vreg12<def> = COPY %vreg13; GPR64:%vreg12,%vreg13
		updated: 416B	%vreg12<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg12
	Success: %vreg13 -> %vreg12
	Result = %vreg12 [416r,448r:0)  0@416r
1872B	%X0<def> = COPY %vreg79; GPR64sp:%vreg79
	Considering merging %vreg79 with %X0
	Can only merge into reserved registers.
1888B	%X1<def> = COPY %vreg17; GPR64:%vreg17
	Considering merging %vreg17 with %X1
	Can only merge into reserved registers.
240B	%X0<def> = COPY %vreg16; GPR64sp:%vreg16
	Considering merging %vreg16 with %X0
	Can only merge into reserved registers.
256B	%X1<def> = COPY %vreg17; GPR64:%vreg17
	Considering merging %vreg17 with %X1
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
W30 [0B,16r:0)[272r,272d:4)[320e,320d:1)[1904r,1904d:2)[1952e,1952d:3)  0@0B-phi 1@320e 2@1904r 3@1952e 4@272r
W0 [0B,80r:0)[240r,272r:2)[1872r,1904r:1)  0@0B-phi 1@1872r 2@240r
W1 [0B,64r:0)[256r,272r:2)[1888r,1904r:1)  0@0B-phi 1@1888r 2@256r
W2 [0B,48r:0)  0@0B-phi
W3 [0B,32r:0)  0@0B-phi
%vreg1 [80r,352r:0)  0@80r
%vreg3 [64r,368r:0)  0@64r
%vreg5 [48r,384r:0)  0@48r
%vreg7 [32r,400r:0)  0@32r
%vreg9 [464r,480r:0)  0@464r
%vreg12 [416r,448r:0)  0@416r
%vreg14 [160r,176r:0)  0@160r
%vreg16 [176r,240r:0)  0@176r
%vreg17 [16r,1888r:0)  0@16r
%vreg21 [784r,800r:0)  0@784r
%vreg22 [768r,784r:0)  0@768r
%vreg24 [1104r,1120r:0)  0@1104r
%vreg26 [1152r,1168r:0)  0@1152r
%vreg28 [1456r,1472r:0)  0@1456r
%vreg30 [1504r,1520r:0)  0@1504r
%vreg32 [1552r,1568r:0)  0@1552r
%vreg34 [1600r,1616r:0)  0@1600r
%vreg37 [1744r,1760r:0)  0@1744r
%vreg39 [1728r,1760r:0)  0@1728r
%vreg40 [1712r,1728r:0)  0@1712r
%vreg43 [1680r,1696r:0)  0@1680r
%vreg45 [1664r,1696r:0)  0@1664r
%vreg46 [1648r,1664r:0)  0@1648r
%vreg48 [1200r,1216r:0)  0@1200r
%vreg49 [1248r,1280r:0)  0@1248r
%vreg51 [1264r,1280r:0)  0@1264r
%vreg53 [1312r,1328r:0)  0@1312r
%vreg54 [1360r,1392r:0)  0@1360r
%vreg56 [1376r,1392r:0)  0@1376r
%vreg58 [848r,864r:0)  0@848r
%vreg59 [896r,928r:0)  0@896r
%vreg61 [912r,928r:0)  0@912r
%vreg63 [960r,976r:0)  0@960r
%vreg64 [1008r,1040r:0)  0@1008r
%vreg66 [1024r,1040r:0)  0@1024r
%vreg68 [512r,528r:0)  0@512r
%vreg69 [560r,592r:0)  0@560r
%vreg71 [576r,592r:0)  0@576r
%vreg73 [624r,640r:0)  0@624r
%vreg74 [672r,704r:0)  0@672r
%vreg76 [688r,704r:0)  0@688r
%vreg77 [1792r,1808r:0)  0@1792r
%vreg79 [1808r,1872r:0)  0@1808r
RegMasks: 272r 1904r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzReadGetUnused: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=8, align=8, at location [SP]
  fi#3: size=8, align=8, at location [SP]
  fi#4: size=8, align=8, at location [SP]
Function Live Ins: %X0 in %vreg0, %X1 in %vreg2, %X2 in %vreg4, %X3 in %vreg6, %LR in %vreg18

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %X1 %X2 %X3 %LR
16B		%vreg17<def> = COPY %LR; GPR64:%vreg17
32B		%vreg7<def> = COPY %X3; GPR64:%vreg7
48B		%vreg5<def> = COPY %X2; GPR64:%vreg5
64B		%vreg3<def> = COPY %X1; GPR64:%vreg3
80B		%vreg1<def> = COPY %X0; GPR64:%vreg1
160B		%vreg14<def> = ADRP <ga:@BZ2_bzReadGetUnused>[TF=1]; GPR64common:%vreg14
176B		%vreg16<def> = ADDXri %vreg14, <ga:@BZ2_bzReadGetUnused>[TF=34], 0; GPR64sp:%vreg16 GPR64common:%vreg14
224B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
240B		%X0<def> = COPY %vreg16; GPR64sp:%vreg16
256B		%X1<def> = COPY %vreg17; GPR64:%vreg17
272B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
288B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
304B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
320B		STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#4>, 0, %vreg7, 0, <fi#3>, 0, %vreg5, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack2] GPR64:%vreg3,%vreg1,%vreg7,%vreg5
336B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
352B		STRXui %vreg1, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg1
368B		STRXui %vreg3, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg3
384B		STRXui %vreg5, <fi#2>, 0; mem:ST8[FixedStack2] GPR64:%vreg5
400B		STRXui %vreg7, <fi#3>, 0; mem:ST8[FixedStack3] GPR64:%vreg7
416B		%vreg12<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg12
448B		STRXui %vreg12, <fi#4>, 0; mem:ST8[FixedStack4] GPR64:%vreg12
464B		%vreg9<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64:%vreg9
480B		CBNZX %vreg9, <BB#6>; GPR64:%vreg9
	    Successors according to CFG: BB#6 BB#1

496B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
512B		%vreg68<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg68
528B		CBZX %vreg68, <BB#3>; GPR64:%vreg68
	    Successors according to CFG: BB#3 BB#2

544B	BB#2: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#1
560B		%vreg69<def> = MOVi32imm 4294967294; GPR32:%vreg69
576B		%vreg71<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg71
592B		STRWui %vreg69, %vreg71, 0; mem:ST4[%4] GPR32:%vreg69 GPR64common:%vreg71
	    Successors according to CFG: BB#3

608B	BB#3: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#1 BB#2
624B		%vreg73<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64:%vreg73
640B		CBZX %vreg73, <BB#5>; GPR64:%vreg73
	    Successors according to CFG: BB#5 BB#4

656B	BB#4: derived from LLVM BB %if.then.4
	    Predecessors according to CFG: BB#3
672B		%vreg74<def> = MOVi32imm 4294967294; GPR32:%vreg74
688B		%vreg76<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg76
704B		STRWui %vreg74, %vreg76, 1274; mem:ST4[%lastErr] GPR32:%vreg74 GPR64common:%vreg76
	    Successors according to CFG: BB#5

720B	BB#5: derived from LLVM BB %if.end.5
	    Predecessors according to CFG: BB#3 BB#4
736B		B <BB#24>
	    Successors according to CFG: BB#24

752B	BB#6: derived from LLVM BB %if.end.6
	    Predecessors according to CFG: BB#0
768B		%vreg22<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg22
784B		%vreg21<def> = LDRWui %vreg22, 1274; mem:LD4[%lastErr7] GPR32common:%vreg21 GPR64common:%vreg22
800B		%WZR<def> = SUBSWri %vreg21, 4, 0, %NZCV<imp-def>; GPR32common:%vreg21
816B		Bcc 0, <BB#12>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#12 BB#7

832B	BB#7: derived from LLVM BB %if.then.9
	    Predecessors according to CFG: BB#6
848B		%vreg58<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg58
864B		CBZX %vreg58, <BB#9>; GPR64:%vreg58
	    Successors according to CFG: BB#9 BB#8

880B	BB#8: derived from LLVM BB %if.then.11
	    Predecessors according to CFG: BB#7
896B		%vreg59<def> = MOVi32imm 4294967295; GPR32:%vreg59
912B		%vreg61<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg61
928B		STRWui %vreg59, %vreg61, 0; mem:ST4[%10] GPR32:%vreg59 GPR64common:%vreg61
	    Successors according to CFG: BB#9

944B	BB#9: derived from LLVM BB %if.end.12
	    Predecessors according to CFG: BB#7 BB#8
960B		%vreg63<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64:%vreg63
976B		CBZX %vreg63, <BB#11>; GPR64:%vreg63
	    Successors according to CFG: BB#11 BB#10

992B	BB#10: derived from LLVM BB %if.then.14
	    Predecessors according to CFG: BB#9
1008B		%vreg64<def> = MOVi32imm 4294967295; GPR32:%vreg64
1024B		%vreg66<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg66
1040B		STRWui %vreg64, %vreg66, 1274; mem:ST4[%lastErr15] GPR32:%vreg64 GPR64common:%vreg66
	    Successors according to CFG: BB#11

1056B	BB#11: derived from LLVM BB %if.end.16
	    Predecessors according to CFG: BB#9 BB#10
1072B		B <BB#24>
	    Successors according to CFG: BB#24

1088B	BB#12: derived from LLVM BB %if.end.17
	    Predecessors according to CFG: BB#6
1104B		%vreg24<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg24
1120B		CBZX %vreg24, <BB#14>; GPR64:%vreg24
	    Successors according to CFG: BB#14 BB#13

1136B	BB#13: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#12
1152B		%vreg26<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg26
1168B		CBNZX %vreg26, <BB#19>; GPR64:%vreg26
	    Successors according to CFG: BB#19 BB#14

1184B	BB#14: derived from LLVM BB %if.then.20
	    Predecessors according to CFG: BB#12 BB#13
1200B		%vreg48<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg48
1216B		CBZX %vreg48, <BB#16>; GPR64:%vreg48
	    Successors according to CFG: BB#16 BB#15

1232B	BB#15: derived from LLVM BB %if.then.22
	    Predecessors according to CFG: BB#14
1248B		%vreg49<def> = MOVi32imm 4294967294; GPR32:%vreg49
1264B		%vreg51<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg51
1280B		STRWui %vreg49, %vreg51, 0; mem:ST4[%16] GPR32:%vreg49 GPR64common:%vreg51
	    Successors according to CFG: BB#16

1296B	BB#16: derived from LLVM BB %if.end.23
	    Predecessors according to CFG: BB#14 BB#15
1312B		%vreg53<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64:%vreg53
1328B		CBZX %vreg53, <BB#18>; GPR64:%vreg53
	    Successors according to CFG: BB#18 BB#17

1344B	BB#17: derived from LLVM BB %if.then.25
	    Predecessors according to CFG: BB#16
1360B		%vreg54<def> = MOVi32imm 4294967294; GPR32:%vreg54
1376B		%vreg56<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg56
1392B		STRWui %vreg54, %vreg56, 1274; mem:ST4[%lastErr26] GPR32:%vreg54 GPR64common:%vreg56
	    Successors according to CFG: BB#18

1408B	BB#18: derived from LLVM BB %if.end.27
	    Predecessors according to CFG: BB#16 BB#17
1424B		B <BB#24>
	    Successors according to CFG: BB#24

1440B	BB#19: derived from LLVM BB %if.end.28
	    Predecessors according to CFG: BB#13
1456B		%vreg28<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg28
1472B		CBZX %vreg28, <BB#21>; GPR64:%vreg28
	    Successors according to CFG: BB#21 BB#20

1488B	BB#20: derived from LLVM BB %if.then.30
	    Predecessors according to CFG: BB#19
1504B		%vreg30<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg30
1520B		STRWui %WZR, %vreg30, 0; mem:ST4[%20] GPR64common:%vreg30
	    Successors according to CFG: BB#21

1536B	BB#21: derived from LLVM BB %if.end.31
	    Predecessors according to CFG: BB#19 BB#20
1552B		%vreg32<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64:%vreg32
1568B		CBZX %vreg32, <BB#23>; GPR64:%vreg32
	    Successors according to CFG: BB#23 BB#22

1584B	BB#22: derived from LLVM BB %if.then.33
	    Predecessors according to CFG: BB#21
1600B		%vreg34<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg34
1616B		STRWui %WZR, %vreg34, 1274; mem:ST4[%lastErr34] GPR64common:%vreg34
	    Successors according to CFG: BB#23

1632B	BB#23: derived from LLVM BB %if.end.35
	    Predecessors according to CFG: BB#21 BB#22
1648B		%vreg46<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg46
1664B		%vreg45<def> = LDRWui %vreg46, 1256; mem:LD4[%avail_in] GPR32:%vreg45 GPR64common:%vreg46
1680B		%vreg43<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg43
1696B		STRWui %vreg45, %vreg43, 0; mem:ST4[%25] GPR32:%vreg45 GPR64common:%vreg43
1712B		%vreg40<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg40
1728B		%vreg39<def> = LDRXui %vreg40, 627; mem:LD8[%next_in] GPR64:%vreg39 GPR64common:%vreg40
1744B		%vreg37<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg37
1760B		STRXui %vreg39, %vreg37, 0; mem:ST8[%28] GPR64:%vreg39 GPR64common:%vreg37
	    Successors according to CFG: BB#24

1776B	BB#24: derived from LLVM BB %return
	    Predecessors according to CFG: BB#23 BB#18 BB#11 BB#5
1792B		%vreg77<def> = ADRP <ga:@BZ2_bzReadGetUnused>[TF=1]; GPR64common:%vreg77
1808B		%vreg79<def> = ADDXri %vreg77, <ga:@BZ2_bzReadGetUnused>[TF=34], 0; GPR64sp:%vreg79 GPR64common:%vreg77
1856B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1872B		%X0<def> = COPY %vreg79; GPR64sp:%vreg79
1888B		%X1<def> = COPY %vreg17; GPR64:%vreg17
1904B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
1920B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1936B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1952B		STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...
1968B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1984B		RET_ReallyLR

# End machine code for function BZ2_bzReadGetUnused.

handleMove 560B -> 584B: %vreg69<def> = MOVi32imm 4294967294; GPR32:%vreg69
     %vreg69:	[560r,592r:0)  0@560r
        -->	[584r,592r:0)  0@584r
handleMove 672B -> 696B: %vreg74<def> = MOVi32imm 4294967294; GPR32:%vreg74
     %vreg74:	[672r,704r:0)  0@672r
        -->	[696r,704r:0)  0@696r
handleMove 896B -> 920B: %vreg59<def> = MOVi32imm 4294967295; GPR32:%vreg59
     %vreg59:	[896r,928r:0)  0@896r
        -->	[920r,928r:0)  0@920r
handleMove 1008B -> 1032B: %vreg64<def> = MOVi32imm 4294967295; GPR32:%vreg64
     %vreg64:	[1008r,1040r:0)  0@1008r
        -->	[1032r,1040r:0)  0@1032r
handleMove 1248B -> 1272B: %vreg49<def> = MOVi32imm 4294967294; GPR32:%vreg49
     %vreg49:	[1248r,1280r:0)  0@1248r
        -->	[1272r,1280r:0)  0@1272r
handleMove 1360B -> 1384B: %vreg54<def> = MOVi32imm 4294967294; GPR32:%vreg54
     %vreg54:	[1360r,1392r:0)  0@1360r
        -->	[1384r,1392r:0)  0@1384r
handleMove 1664B -> 1688B: %vreg45<def> = LDRWui %vreg46, 1256; mem:LD4[%avail_in] GPR32:%vreg45 GPR64common:%vreg46
     %vreg45:	[1664r,1696r:0)  0@1664r
        -->	[1688r,1696r:0)  0@1688r
     %vreg46:	[1648r,1664r:0)  0@1648r
        -->	[1648r,1688r:0)  0@1648r
********** GREEDY REGISTER ALLOCATION **********
********** Function: BZ2_bzReadGetUnused
********** INTERVALS **********
W30 [0B,16r:0)[272r,272d:4)[320e,320d:1)[1904r,1904d:2)[1952e,1952d:3)  0@0B-phi 1@320e 2@1904r 3@1952e 4@272r
W0 [0B,80r:0)[240r,272r:2)[1872r,1904r:1)  0@0B-phi 1@1872r 2@240r
W1 [0B,64r:0)[256r,272r:2)[1888r,1904r:1)  0@0B-phi 1@1888r 2@256r
W2 [0B,48r:0)  0@0B-phi
W3 [0B,32r:0)  0@0B-phi
%vreg1 [80r,352r:0)  0@80r
%vreg3 [64r,368r:0)  0@64r
%vreg5 [48r,384r:0)  0@48r
%vreg7 [32r,400r:0)  0@32r
%vreg9 [464r,480r:0)  0@464r
%vreg12 [416r,448r:0)  0@416r
%vreg14 [160r,176r:0)  0@160r
%vreg16 [176r,240r:0)  0@176r
%vreg17 [16r,1888r:0)  0@16r
%vreg21 [784r,800r:0)  0@784r
%vreg22 [768r,784r:0)  0@768r
%vreg24 [1104r,1120r:0)  0@1104r
%vreg26 [1152r,1168r:0)  0@1152r
%vreg28 [1456r,1472r:0)  0@1456r
%vreg30 [1504r,1520r:0)  0@1504r
%vreg32 [1552r,1568r:0)  0@1552r
%vreg34 [1600r,1616r:0)  0@1600r
%vreg37 [1744r,1760r:0)  0@1744r
%vreg39 [1728r,1760r:0)  0@1728r
%vreg40 [1712r,1728r:0)  0@1712r
%vreg43 [1680r,1696r:0)  0@1680r
%vreg45 [1688r,1696r:0)  0@1688r
%vreg46 [1648r,1688r:0)  0@1648r
%vreg48 [1200r,1216r:0)  0@1200r
%vreg49 [1272r,1280r:0)  0@1272r
%vreg51 [1264r,1280r:0)  0@1264r
%vreg53 [1312r,1328r:0)  0@1312r
%vreg54 [1384r,1392r:0)  0@1384r
%vreg56 [1376r,1392r:0)  0@1376r
%vreg58 [848r,864r:0)  0@848r
%vreg59 [920r,928r:0)  0@920r
%vreg61 [912r,928r:0)  0@912r
%vreg63 [960r,976r:0)  0@960r
%vreg64 [1032r,1040r:0)  0@1032r
%vreg66 [1024r,1040r:0)  0@1024r
%vreg68 [512r,528r:0)  0@512r
%vreg69 [584r,592r:0)  0@584r
%vreg71 [576r,592r:0)  0@576r
%vreg73 [624r,640r:0)  0@624r
%vreg74 [696r,704r:0)  0@696r
%vreg76 [688r,704r:0)  0@688r
%vreg77 [1792r,1808r:0)  0@1792r
%vreg79 [1808r,1872r:0)  0@1808r
RegMasks: 272r 1904r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzReadGetUnused: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=8, align=8, at location [SP]
  fi#3: size=8, align=8, at location [SP]
  fi#4: size=8, align=8, at location [SP]
Function Live Ins: %X0 in %vreg0, %X1 in %vreg2, %X2 in %vreg4, %X3 in %vreg6, %LR in %vreg18

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %X1 %X2 %X3 %LR
16B		%vreg17<def> = COPY %LR; GPR64:%vreg17
32B		%vreg7<def> = COPY %X3; GPR64:%vreg7
48B		%vreg5<def> = COPY %X2; GPR64:%vreg5
64B		%vreg3<def> = COPY %X1; GPR64:%vreg3
80B		%vreg1<def> = COPY %X0; GPR64:%vreg1
160B		%vreg14<def> = ADRP <ga:@BZ2_bzReadGetUnused>[TF=1]; GPR64common:%vreg14
176B		%vreg16<def> = ADDXri %vreg14, <ga:@BZ2_bzReadGetUnused>[TF=34], 0; GPR64sp:%vreg16 GPR64common:%vreg14
224B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
240B		%X0<def> = COPY %vreg16; GPR64sp:%vreg16
256B		%X1<def> = COPY %vreg17; GPR64:%vreg17
272B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
288B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
304B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
320B		STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#4>, 0, %vreg7, 0, <fi#3>, 0, %vreg5, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack2] GPR64:%vreg3,%vreg1,%vreg7,%vreg5
336B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
352B		STRXui %vreg1, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg1
368B		STRXui %vreg3, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg3
384B		STRXui %vreg5, <fi#2>, 0; mem:ST8[FixedStack2] GPR64:%vreg5
400B		STRXui %vreg7, <fi#3>, 0; mem:ST8[FixedStack3] GPR64:%vreg7
416B		%vreg12<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg12
448B		STRXui %vreg12, <fi#4>, 0; mem:ST8[FixedStack4] GPR64:%vreg12
464B		%vreg9<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64:%vreg9
480B		CBNZX %vreg9, <BB#6>; GPR64:%vreg9
	    Successors according to CFG: BB#6 BB#1

496B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
512B		%vreg68<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg68
528B		CBZX %vreg68, <BB#3>; GPR64:%vreg68
	    Successors according to CFG: BB#3 BB#2

544B	BB#2: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#1
576B		%vreg71<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg71
584B		%vreg69<def> = MOVi32imm 4294967294; GPR32:%vreg69
592B		STRWui %vreg69, %vreg71, 0; mem:ST4[%4] GPR32:%vreg69 GPR64common:%vreg71
	    Successors according to CFG: BB#3

608B	BB#3: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#1 BB#2
624B		%vreg73<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64:%vreg73
640B		CBZX %vreg73, <BB#5>; GPR64:%vreg73
	    Successors according to CFG: BB#5 BB#4

656B	BB#4: derived from LLVM BB %if.then.4
	    Predecessors according to CFG: BB#3
688B		%vreg76<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg76
696B		%vreg74<def> = MOVi32imm 4294967294; GPR32:%vreg74
704B		STRWui %vreg74, %vreg76, 1274; mem:ST4[%lastErr] GPR32:%vreg74 GPR64common:%vreg76
	    Successors according to CFG: BB#5

720B	BB#5: derived from LLVM BB %if.end.5
	    Predecessors according to CFG: BB#3 BB#4
736B		B <BB#24>
	    Successors according to CFG: BB#24

752B	BB#6: derived from LLVM BB %if.end.6
	    Predecessors according to CFG: BB#0
768B		%vreg22<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg22
784B		%vreg21<def> = LDRWui %vreg22, 1274; mem:LD4[%lastErr7] GPR32common:%vreg21 GPR64common:%vreg22
800B		%WZR<def> = SUBSWri %vreg21, 4, 0, %NZCV<imp-def>; GPR32common:%vreg21
816B		Bcc 0, <BB#12>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#12 BB#7

832B	BB#7: derived from LLVM BB %if.then.9
	    Predecessors according to CFG: BB#6
848B		%vreg58<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg58
864B		CBZX %vreg58, <BB#9>; GPR64:%vreg58
	    Successors according to CFG: BB#9 BB#8

880B	BB#8: derived from LLVM BB %if.then.11
	    Predecessors according to CFG: BB#7
912B		%vreg61<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg61
920B		%vreg59<def> = MOVi32imm 4294967295; GPR32:%vreg59
928B		STRWui %vreg59, %vreg61, 0; mem:ST4[%10] GPR32:%vreg59 GPR64common:%vreg61
	    Successors according to CFG: BB#9

944B	BB#9: derived from LLVM BB %if.end.12
	    Predecessors according to CFG: BB#7 BB#8
960B		%vreg63<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64:%vreg63
976B		CBZX %vreg63, <BB#11>; GPR64:%vreg63
	    Successors according to CFG: BB#11 BB#10

992B	BB#10: derived from LLVM BB %if.then.14
	    Predecessors according to CFG: BB#9
1024B		%vreg66<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg66
1032B		%vreg64<def> = MOVi32imm 4294967295; GPR32:%vreg64
1040B		STRWui %vreg64, %vreg66, 1274; mem:ST4[%lastErr15] GPR32:%vreg64 GPR64common:%vreg66
	    Successors according to CFG: BB#11

1056B	BB#11: derived from LLVM BB %if.end.16
	    Predecessors according to CFG: BB#9 BB#10
1072B		B <BB#24>
	    Successors according to CFG: BB#24

1088B	BB#12: derived from LLVM BB %if.end.17
	    Predecessors according to CFG: BB#6
1104B		%vreg24<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg24
1120B		CBZX %vreg24, <BB#14>; GPR64:%vreg24
	    Successors according to CFG: BB#14 BB#13

1136B	BB#13: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#12
1152B		%vreg26<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg26
1168B		CBNZX %vreg26, <BB#19>; GPR64:%vreg26
	    Successors according to CFG: BB#19 BB#14

1184B	BB#14: derived from LLVM BB %if.then.20
	    Predecessors according to CFG: BB#12 BB#13
1200B		%vreg48<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg48
1216B		CBZX %vreg48, <BB#16>; GPR64:%vreg48
	    Successors according to CFG: BB#16 BB#15

1232B	BB#15: derived from LLVM BB %if.then.22
	    Predecessors according to CFG: BB#14
1264B		%vreg51<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg51
1272B		%vreg49<def> = MOVi32imm 4294967294; GPR32:%vreg49
1280B		STRWui %vreg49, %vreg51, 0; mem:ST4[%16] GPR32:%vreg49 GPR64common:%vreg51
	    Successors according to CFG: BB#16

1296B	BB#16: derived from LLVM BB %if.end.23
	    Predecessors according to CFG: BB#14 BB#15
1312B		%vreg53<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64:%vreg53
1328B		CBZX %vreg53, <BB#18>; GPR64:%vreg53
	    Successors according to CFG: BB#18 BB#17

1344B	BB#17: derived from LLVM BB %if.then.25
	    Predecessors according to CFG: BB#16
1376B		%vreg56<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg56
1384B		%vreg54<def> = MOVi32imm 4294967294; GPR32:%vreg54
1392B		STRWui %vreg54, %vreg56, 1274; mem:ST4[%lastErr26] GPR32:%vreg54 GPR64common:%vreg56
	    Successors according to CFG: BB#18

1408B	BB#18: derived from LLVM BB %if.end.27
	    Predecessors according to CFG: BB#16 BB#17
1424B		B <BB#24>
	    Successors according to CFG: BB#24

1440B	BB#19: derived from LLVM BB %if.end.28
	    Predecessors according to CFG: BB#13
1456B		%vreg28<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg28
1472B		CBZX %vreg28, <BB#21>; GPR64:%vreg28
	    Successors according to CFG: BB#21 BB#20

1488B	BB#20: derived from LLVM BB %if.then.30
	    Predecessors according to CFG: BB#19
1504B		%vreg30<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg30
1520B		STRWui %WZR, %vreg30, 0; mem:ST4[%20] GPR64common:%vreg30
	    Successors according to CFG: BB#21

1536B	BB#21: derived from LLVM BB %if.end.31
	    Predecessors according to CFG: BB#19 BB#20
1552B		%vreg32<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64:%vreg32
1568B		CBZX %vreg32, <BB#23>; GPR64:%vreg32
	    Successors according to CFG: BB#23 BB#22

1584B	BB#22: derived from LLVM BB %if.then.33
	    Predecessors according to CFG: BB#21
1600B		%vreg34<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg34
1616B		STRWui %WZR, %vreg34, 1274; mem:ST4[%lastErr34] GPR64common:%vreg34
	    Successors according to CFG: BB#23

1632B	BB#23: derived from LLVM BB %if.end.35
	    Predecessors according to CFG: BB#21 BB#22
1648B		%vreg46<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg46
1680B		%vreg43<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg43
1688B		%vreg45<def> = LDRWui %vreg46, 1256; mem:LD4[%avail_in] GPR32:%vreg45 GPR64common:%vreg46
1696B		STRWui %vreg45, %vreg43, 0; mem:ST4[%25] GPR32:%vreg45 GPR64common:%vreg43
1712B		%vreg40<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg40
1728B		%vreg39<def> = LDRXui %vreg40, 627; mem:LD8[%next_in] GPR64:%vreg39 GPR64common:%vreg40
1744B		%vreg37<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg37
1760B		STRXui %vreg39, %vreg37, 0; mem:ST8[%28] GPR64:%vreg39 GPR64common:%vreg37
	    Successors according to CFG: BB#24

1776B	BB#24: derived from LLVM BB %return
	    Predecessors according to CFG: BB#23 BB#18 BB#11 BB#5
1792B		%vreg77<def> = ADRP <ga:@BZ2_bzReadGetUnused>[TF=1]; GPR64common:%vreg77
1808B		%vreg79<def> = ADDXri %vreg77, <ga:@BZ2_bzReadGetUnused>[TF=34], 0; GPR64sp:%vreg79 GPR64common:%vreg77
1856B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1872B		%X0<def> = COPY %vreg79; GPR64sp:%vreg79
1888B		%X1<def> = COPY %vreg17; GPR64:%vreg17
1904B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
1920B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1936B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1952B		STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...
1968B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1984B		RET_ReallyLR

# End machine code for function BZ2_bzReadGetUnused.


selectOrSplit GPR64:%vreg17 [16r,1888r:0)  0@16r w=1.333627e-03
hints: %X1
missed hint %X1
assigning %vreg17 to %X19: W19 [16r,1888r:0)  0@16r

selectOrSplit GPR64:%vreg7 [32r,400r:0)  0@32r w=3.945312e-03
hints: %X3
missed hint %X3
assigning %vreg7 to %X20: W20 [32r,400r:0)  0@32r

selectOrSplit GPR64:%vreg5 [48r,384r:0)  0@48r w=4.116848e-03
hints: %X2
missed hint %X2
assigning %vreg5 to %X21: W21 [48r,384r:0)  0@48r

selectOrSplit GPR64:%vreg3 [64r,368r:0)  0@64r w=4.303977e-03
hints: %X1
missed hint %X1
assigning %vreg3 to %X22: W22 [64r,368r:0)  0@64r

selectOrSplit GPR64:%vreg1 [80r,352r:0)  0@80r w=4.508928e-03
hints: %X0
missed hint %X0
assigning %vreg1 to %X23: W23 [80r,352r:0)  0@80r

selectOrSplit GPR64sp:%vreg16 [176r,240r:0)  0@176r w=4.353448e-03
hints: %X0
assigning %vreg16 to %X0: W0 [176r,240r:0)  0@176r

selectOrSplit GPR64sp:%vreg79 [1808r,1872r:0)  0@1808r w=4.353448e-03
hints: %X0
assigning %vreg79 to %X0: W0 [1808r,1872r:0)  0@1808r

selectOrSplit GPR64common:%vreg14 [160r,176r:0)  0@160r w=inf
assigning %vreg14 to %X8: W8 [160r,176r:0)  0@160r

selectOrSplit GPR64:%vreg12 [416r,448r:0)  0@416r w=inf
assigning %vreg12 to %X8: W8 [416r,448r:0)  0@416r

selectOrSplit GPR64:%vreg9 [464r,480r:0)  0@464r w=inf
assigning %vreg9 to %X8: W8 [464r,480r:0)  0@464r

selectOrSplit GPR64:%vreg68 [512r,528r:0)  0@512r w=inf
assigning %vreg68 to %X8: W8 [512r,528r:0)  0@512r

selectOrSplit GPR64common:%vreg71 [576r,592r:0)  0@576r w=1.187783e-03
assigning %vreg71 to %X8: W8 [576r,592r:0)  0@576r

selectOrSplit GPR32:%vreg69 [584r,592r:0)  0@584r w=inf
assigning %vreg69 to %W9: W9 [584r,592r:0)  0@584r

selectOrSplit GPR64:%vreg73 [624r,640r:0)  0@624r w=inf
assigning %vreg73 to %X8: W8 [624r,640r:0)  0@624r

selectOrSplit GPR64common:%vreg76 [688r,704r:0)  0@688r w=1.187783e-03
assigning %vreg76 to %X8: W8 [688r,704r:0)  0@688r

selectOrSplit GPR32:%vreg74 [696r,704r:0)  0@696r w=inf
assigning %vreg74 to %W9: W9 [696r,704r:0)  0@696r

selectOrSplit GPR64common:%vreg22 [768r,784r:0)  0@768r w=inf
assigning %vreg22 to %X8: W8 [768r,784r:0)  0@768r

selectOrSplit GPR32common:%vreg21 [784r,800r:0)  0@784r w=inf
assigning %vreg21 to %W8: W8 [784r,800r:0)  0@784r

selectOrSplit GPR64:%vreg58 [848r,864r:0)  0@848r w=inf
assigning %vreg58 to %X8: W8 [848r,864r:0)  0@848r

selectOrSplit GPR64common:%vreg61 [912r,928r:0)  0@912r w=5.844646e-04
assigning %vreg61 to %X8: W8 [912r,928r:0)  0@912r

selectOrSplit GPR32:%vreg59 [920r,928r:0)  0@920r w=inf
assigning %vreg59 to %W9: W9 [920r,928r:0)  0@920r

selectOrSplit GPR64:%vreg63 [960r,976r:0)  0@960r w=inf
assigning %vreg63 to %X8: W8 [960r,976r:0)  0@960r

selectOrSplit GPR64common:%vreg66 [1024r,1040r:0)  0@1024r w=5.844646e-04
assigning %vreg66 to %X8: W8 [1024r,1040r:0)  0@1024r

selectOrSplit GPR32:%vreg64 [1032r,1040r:0)  0@1032r w=inf
assigning %vreg64 to %W9: W9 [1032r,1040r:0)  0@1032r

selectOrSplit GPR64:%vreg24 [1104r,1120r:0)  0@1104r w=inf
assigning %vreg24 to %X8: W8 [1104r,1120r:0)  0@1104r

selectOrSplit GPR64:%vreg26 [1152r,1168r:0)  0@1152r w=inf
assigning %vreg26 to %X8: W8 [1152r,1168r:0)  0@1152r

selectOrSplit GPR64:%vreg48 [1200r,1216r:0)  0@1200r w=inf
assigning %vreg48 to %X8: W8 [1200r,1216r:0)  0@1200r

selectOrSplit GPR64common:%vreg51 [1264r,1280r:0)  0@1264r w=4.336350e-04
assigning %vreg51 to %X8: W8 [1264r,1280r:0)  0@1264r

selectOrSplit GPR32:%vreg49 [1272r,1280r:0)  0@1272r w=inf
assigning %vreg49 to %W9: W9 [1272r,1280r:0)  0@1272r

selectOrSplit GPR64:%vreg53 [1312r,1328r:0)  0@1312r w=inf
assigning %vreg53 to %X8: W8 [1312r,1328r:0)  0@1312r

selectOrSplit GPR64common:%vreg56 [1376r,1392r:0)  0@1376r w=4.336350e-04
assigning %vreg56 to %X8: W8 [1376r,1392r:0)  0@1376r

selectOrSplit GPR32:%vreg54 [1384r,1392r:0)  0@1384r w=inf
assigning %vreg54 to %W9: W9 [1384r,1392r:0)  0@1384r

selectOrSplit GPR64:%vreg28 [1456r,1472r:0)  0@1456r w=inf
assigning %vreg28 to %X8: W8 [1456r,1472r:0)  0@1456r

selectOrSplit GPR64common:%vreg30 [1504r,1520r:0)  0@1504r w=inf
assigning %vreg30 to %X8: W8 [1504r,1520r:0)  0@1504r

selectOrSplit GPR64:%vreg32 [1552r,1568r:0)  0@1552r w=inf
assigning %vreg32 to %X8: W8 [1552r,1568r:0)  0@1552r

selectOrSplit GPR64common:%vreg34 [1600r,1616r:0)  0@1600r w=inf
assigning %vreg34 to %X8: W8 [1600r,1616r:0)  0@1600r

selectOrSplit GPR64common:%vreg46 [1648r,1688r:0)  0@1648r w=2.673797e-04
assigning %vreg46 to %X8: W8 [1648r,1688r:0)  0@1648r

selectOrSplit GPR64common:%vreg43 [1680r,1696r:0)  0@1680r w=2.828054e-04
assigning %vreg43 to %X9: W9 [1680r,1696r:0)  0@1680r

selectOrSplit GPR32:%vreg45 [1688r,1696r:0)  0@1688r w=inf
assigning %vreg45 to %W8: W8 [1688r,1696r:0)  0@1688r

selectOrSplit GPR64common:%vreg40 [1712r,1728r:0)  0@1712r w=inf
assigning %vreg40 to %X8: W8 [1712r,1728r:0)  0@1712r

selectOrSplit GPR64:%vreg39 [1728r,1760r:0)  0@1728r w=2.723312e-04
assigning %vreg39 to %X8: W8 [1728r,1760r:0)  0@1728r

selectOrSplit GPR64common:%vreg37 [1744r,1760r:0)  0@1744r w=inf
assigning %vreg37 to %X9: W9 [1744r,1760r:0)  0@1744r

selectOrSplit GPR64common:%vreg77 [1792r,1808r:0)  0@1792r w=inf
assigning %vreg77 to %X8: W8 [1792r,1808r:0)  0@1792r

********** STACK TRANSFORMATION METADATA **********
********** Function: BZ2_bzReadGetUnused
********** REGISTER MAP **********
[%vreg1 -> %X23] GPR64
[%vreg3 -> %X22] GPR64
[%vreg5 -> %X21] GPR64
[%vreg7 -> %X20] GPR64
[%vreg9 -> %X8] GPR64
[%vreg12 -> %X8] GPR64
[%vreg14 -> %X8] GPR64common
[%vreg16 -> %X0] GPR64sp
[%vreg17 -> %X19] GPR64
[%vreg21 -> %W8] GPR32common
[%vreg22 -> %X8] GPR64common
[%vreg24 -> %X8] GPR64
[%vreg26 -> %X8] GPR64
[%vreg28 -> %X8] GPR64
[%vreg30 -> %X8] GPR64common
[%vreg32 -> %X8] GPR64
[%vreg34 -> %X8] GPR64common
[%vreg37 -> %X9] GPR64common
[%vreg39 -> %X8] GPR64
[%vreg40 -> %X8] GPR64common
[%vreg43 -> %X9] GPR64common
[%vreg45 -> %W8] GPR32
[%vreg46 -> %X8] GPR64common
[%vreg48 -> %X8] GPR64
[%vreg49 -> %W9] GPR32
[%vreg51 -> %X8] GPR64common
[%vreg53 -> %X8] GPR64
[%vreg54 -> %W9] GPR32
[%vreg56 -> %X8] GPR64common
[%vreg58 -> %X8] GPR64
[%vreg59 -> %W9] GPR32
[%vreg61 -> %X8] GPR64common
[%vreg63 -> %X8] GPR64
[%vreg64 -> %W9] GPR32
[%vreg66 -> %X8] GPR64common
[%vreg68 -> %X8] GPR64
[%vreg69 -> %W9] GPR32
[%vreg71 -> %X8] GPR64common
[%vreg73 -> %X8] GPR64
[%vreg74 -> %W9] GPR32
[%vreg76 -> %X8] GPR64common
[%vreg77 -> %X8] GPR64common
[%vreg79 -> %X0] GPR64sp


Stackmap 0:
  STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#4>, 0, %vreg7, 0, <fi#3>, 0, %vreg5, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack2] GPR64:%vreg3,%vreg1,%vreg7,%vreg5

i8* %b: in register %X22 (vreg 3)
i8** %b.addr: in stack slot 1 (size: 8)
i32* %bzerror: in register %X23 (vreg 1)
i32** %bzerror.addr: in stack slot 0 (size: 8)
%struct.bzFile** %bzf: in stack slot 4 (size: 8)
i32* %nUnused: in register %X20 (vreg 7)
i32** %nUnused.addr: in stack slot 3 (size: 8)
i8** %unused: in register %X21 (vreg 5)
i8*** %unused.addr: in stack slot 2 (size: 8)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...


Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#4>, 0, %vreg7, 0, <fi#3>, 0, %vreg5, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack2] GPR64:%vreg3,%vreg1,%vreg7,%vreg5
  -> Call instruction SlotIndex 272B, searching vregs 0 -> 81 and stack slots 0 -> 5
    + vreg17 is live in register but not in stackmap
      Defining instruction: %vreg17<def> = COPY %LR; GPR64:%vreg17
      Value: generated value, 1 instruction(s)

  STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...
  -> Call instruction SlotIndex 1904B, searching vregs 0 -> 81 and stack slots 0 -> 5

********** REWRITE VIRTUAL REGISTERS **********
********** Function: BZ2_bzReadGetUnused
********** REGISTER MAP **********
[%vreg1 -> %X23] GPR64
[%vreg3 -> %X22] GPR64
[%vreg5 -> %X21] GPR64
[%vreg7 -> %X20] GPR64
[%vreg9 -> %X8] GPR64
[%vreg12 -> %X8] GPR64
[%vreg14 -> %X8] GPR64common
[%vreg16 -> %X0] GPR64sp
[%vreg17 -> %X19] GPR64
[%vreg21 -> %W8] GPR32common
[%vreg22 -> %X8] GPR64common
[%vreg24 -> %X8] GPR64
[%vreg26 -> %X8] GPR64
[%vreg28 -> %X8] GPR64
[%vreg30 -> %X8] GPR64common
[%vreg32 -> %X8] GPR64
[%vreg34 -> %X8] GPR64common
[%vreg37 -> %X9] GPR64common
[%vreg39 -> %X8] GPR64
[%vreg40 -> %X8] GPR64common
[%vreg43 -> %X9] GPR64common
[%vreg45 -> %W8] GPR32
[%vreg46 -> %X8] GPR64common
[%vreg48 -> %X8] GPR64
[%vreg49 -> %W9] GPR32
[%vreg51 -> %X8] GPR64common
[%vreg53 -> %X8] GPR64
[%vreg54 -> %W9] GPR32
[%vreg56 -> %X8] GPR64common
[%vreg58 -> %X8] GPR64
[%vreg59 -> %W9] GPR32
[%vreg61 -> %X8] GPR64common
[%vreg63 -> %X8] GPR64
[%vreg64 -> %W9] GPR32
[%vreg66 -> %X8] GPR64common
[%vreg68 -> %X8] GPR64
[%vreg69 -> %W9] GPR32
[%vreg71 -> %X8] GPR64common
[%vreg73 -> %X8] GPR64
[%vreg74 -> %W9] GPR32
[%vreg76 -> %X8] GPR64common
[%vreg77 -> %X8] GPR64common
[%vreg79 -> %X0] GPR64sp

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %LR %X0 %X1 %X2 %X3
16B		%vreg17<def> = COPY %LR; GPR64:%vreg17
32B		%vreg7<def> = COPY %X3; GPR64:%vreg7
48B		%vreg5<def> = COPY %X2; GPR64:%vreg5
64B		%vreg3<def> = COPY %X1; GPR64:%vreg3
80B		%vreg1<def> = COPY %X0; GPR64:%vreg1
160B		%vreg14<def> = ADRP <ga:@BZ2_bzReadGetUnused>[TF=1]; GPR64common:%vreg14
176B		%vreg16<def> = ADDXri %vreg14<kill>, <ga:@BZ2_bzReadGetUnused>[TF=34], 0; GPR64sp:%vreg16 GPR64common:%vreg14
224B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
240B		%X0<def> = COPY %vreg16<kill>; GPR64sp:%vreg16
256B		%X1<def> = COPY %vreg17; GPR64:%vreg17
272B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
288B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
304B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
320B		STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#4>, 0, %vreg7, 0, <fi#3>, 0, %vreg5, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack2] GPR64:%vreg3,%vreg1,%vreg7,%vreg5
336B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
352B		STRXui %vreg1<kill>, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg1
368B		STRXui %vreg3<kill>, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg3
384B		STRXui %vreg5<kill>, <fi#2>, 0; mem:ST8[FixedStack2] GPR64:%vreg5
400B		STRXui %vreg7<kill>, <fi#3>, 0; mem:ST8[FixedStack3] GPR64:%vreg7
416B		%vreg12<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg12
448B		STRXui %vreg12<kill>, <fi#4>, 0; mem:ST8[FixedStack4] GPR64:%vreg12
464B		%vreg9<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64:%vreg9
480B		CBNZX %vreg9<kill>, <BB#6>; GPR64:%vreg9
	    Successors according to CFG: BB#6 BB#1
> %X19<def> = COPY %LR
> %X20<def> = COPY %X3
> %X21<def> = COPY %X2
> %X22<def> = COPY %X1
> %X23<def> = COPY %X0
> %X8<def> = ADRP <ga:@BZ2_bzReadGetUnused>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@BZ2_bzReadGetUnused>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19
> BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 0, 0, %X22, 0, <fi#1>, 0, %X23, 0, <fi#0>, 0, 0, <fi#4>, 0, %X20, 0, <fi#3>, 0, %X21, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack2]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRXui %X23<kill>, <fi#0>, 0; mem:ST8[FixedStack0]
> STRXui %X22<kill>, <fi#1>, 0; mem:ST8[FixedStack1]
> STRXui %X21<kill>, <fi#2>, 0; mem:ST8[FixedStack2]
> STRXui %X20<kill>, <fi#3>, 0; mem:ST8[FixedStack3]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRXui %X8<kill>, <fi#4>, 0; mem:ST8[FixedStack4]
> %X8<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4]
> CBNZX %X8<kill>, <BB#6>
496B	BB#1: derived from LLVM BB %if.then
	    Live Ins: %X19
	    Predecessors according to CFG: BB#0
512B		%vreg68<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg68
528B		CBZX %vreg68<kill>, <BB#3>; GPR64:%vreg68
	    Successors according to CFG: BB#3 BB#2
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> CBZX %X8<kill>, <BB#3>
544B	BB#2: derived from LLVM BB %if.then.2
	    Live Ins: %X19
	    Predecessors according to CFG: BB#1
576B		%vreg71<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg71
584B		%vreg69<def> = MOVi32imm 4294967294; GPR32:%vreg69
592B		STRWui %vreg69<kill>, %vreg71<kill>, 0; mem:ST4[%4] GPR32:%vreg69 GPR64common:%vreg71
	    Successors according to CFG: BB#3
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %W9<def> = MOVi32imm 4294967294
> STRWui %W9<kill>, %X8<kill>, 0; mem:ST4[%4]
608B	BB#3: derived from LLVM BB %if.end
	    Live Ins: %X19
	    Predecessors according to CFG: BB#1 BB#2
624B		%vreg73<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64:%vreg73
640B		CBZX %vreg73<kill>, <BB#5>; GPR64:%vreg73
	    Successors according to CFG: BB#5 BB#4
> %X8<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4]
> CBZX %X8<kill>, <BB#5>
656B	BB#4: derived from LLVM BB %if.then.4
	    Live Ins: %X19
	    Predecessors according to CFG: BB#3
688B		%vreg76<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg76
696B		%vreg74<def> = MOVi32imm 4294967294; GPR32:%vreg74
704B		STRWui %vreg74<kill>, %vreg76<kill>, 1274; mem:ST4[%lastErr] GPR32:%vreg74 GPR64common:%vreg76
	    Successors according to CFG: BB#5
> %X8<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4]
> %W9<def> = MOVi32imm 4294967294
> STRWui %W9<kill>, %X8<kill>, 1274; mem:ST4[%lastErr]
720B	BB#5: derived from LLVM BB %if.end.5
	    Live Ins: %X19
	    Predecessors according to CFG: BB#3 BB#4
736B		B <BB#24>
	    Successors according to CFG: BB#24
> B <BB#24>
752B	BB#6: derived from LLVM BB %if.end.6
	    Live Ins: %X19
	    Predecessors according to CFG: BB#0
768B		%vreg22<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg22
784B		%vreg21<def> = LDRWui %vreg22<kill>, 1274; mem:LD4[%lastErr7] GPR32common:%vreg21 GPR64common:%vreg22
800B		%WZR<def> = SUBSWri %vreg21<kill>, 4, 0, %NZCV<imp-def>; GPR32common:%vreg21
816B		Bcc 0, <BB#12>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#12 BB#7
> %X8<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4]
> %W8<def> = LDRWui %X8<kill>, 1274; mem:LD4[%lastErr7]
> %WZR<def> = SUBSWri %W8<kill>, 4, 0, %NZCV<imp-def>
> Bcc 0, <BB#12>, %NZCV<imp-use,kill>
832B	BB#7: derived from LLVM BB %if.then.9
	    Live Ins: %X19
	    Predecessors according to CFG: BB#6
848B		%vreg58<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg58
864B		CBZX %vreg58<kill>, <BB#9>; GPR64:%vreg58
	    Successors according to CFG: BB#9 BB#8
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> CBZX %X8<kill>, <BB#9>
880B	BB#8: derived from LLVM BB %if.then.11
	    Live Ins: %X19
	    Predecessors according to CFG: BB#7
912B		%vreg61<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg61
920B		%vreg59<def> = MOVi32imm 4294967295; GPR32:%vreg59
928B		STRWui %vreg59<kill>, %vreg61<kill>, 0; mem:ST4[%10] GPR32:%vreg59 GPR64common:%vreg61
	    Successors according to CFG: BB#9
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %W9<def> = MOVi32imm 4294967295
> STRWui %W9<kill>, %X8<kill>, 0; mem:ST4[%10]
944B	BB#9: derived from LLVM BB %if.end.12
	    Live Ins: %X19
	    Predecessors according to CFG: BB#7 BB#8
960B		%vreg63<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64:%vreg63
976B		CBZX %vreg63<kill>, <BB#11>; GPR64:%vreg63
	    Successors according to CFG: BB#11 BB#10
> %X8<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4]
> CBZX %X8<kill>, <BB#11>
992B	BB#10: derived from LLVM BB %if.then.14
	    Live Ins: %X19
	    Predecessors according to CFG: BB#9
1024B		%vreg66<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg66
1032B		%vreg64<def> = MOVi32imm 4294967295; GPR32:%vreg64
1040B		STRWui %vreg64<kill>, %vreg66<kill>, 1274; mem:ST4[%lastErr15] GPR32:%vreg64 GPR64common:%vreg66
	    Successors according to CFG: BB#11
> %X8<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4]
> %W9<def> = MOVi32imm 4294967295
> STRWui %W9<kill>, %X8<kill>, 1274; mem:ST4[%lastErr15]
1056B	BB#11: derived from LLVM BB %if.end.16
	    Live Ins: %X19
	    Predecessors according to CFG: BB#9 BB#10
1072B		B <BB#24>
	    Successors according to CFG: BB#24
> B <BB#24>
1088B	BB#12: derived from LLVM BB %if.end.17
	    Live Ins: %X19
	    Predecessors according to CFG: BB#6
1104B		%vreg24<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg24
1120B		CBZX %vreg24<kill>, <BB#14>; GPR64:%vreg24
	    Successors according to CFG: BB#14 BB#13
> %X8<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2]
> CBZX %X8<kill>, <BB#14>
1136B	BB#13: derived from LLVM BB %lor.lhs.false
	    Live Ins: %X19
	    Predecessors according to CFG: BB#12
1152B		%vreg26<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg26
1168B		CBNZX %vreg26<kill>, <BB#19>; GPR64:%vreg26
	    Successors according to CFG: BB#19 BB#14
> %X8<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> CBNZX %X8<kill>, <BB#19>
1184B	BB#14: derived from LLVM BB %if.then.20
	    Live Ins: %X19
	    Predecessors according to CFG: BB#12 BB#13
1200B		%vreg48<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg48
1216B		CBZX %vreg48<kill>, <BB#16>; GPR64:%vreg48
	    Successors according to CFG: BB#16 BB#15
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> CBZX %X8<kill>, <BB#16>
1232B	BB#15: derived from LLVM BB %if.then.22
	    Live Ins: %X19
	    Predecessors according to CFG: BB#14
1264B		%vreg51<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg51
1272B		%vreg49<def> = MOVi32imm 4294967294; GPR32:%vreg49
1280B		STRWui %vreg49<kill>, %vreg51<kill>, 0; mem:ST4[%16] GPR32:%vreg49 GPR64common:%vreg51
	    Successors according to CFG: BB#16
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %W9<def> = MOVi32imm 4294967294
> STRWui %W9<kill>, %X8<kill>, 0; mem:ST4[%16]
1296B	BB#16: derived from LLVM BB %if.end.23
	    Live Ins: %X19
	    Predecessors according to CFG: BB#14 BB#15
1312B		%vreg53<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64:%vreg53
1328B		CBZX %vreg53<kill>, <BB#18>; GPR64:%vreg53
	    Successors according to CFG: BB#18 BB#17
> %X8<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4]
> CBZX %X8<kill>, <BB#18>
1344B	BB#17: derived from LLVM BB %if.then.25
	    Live Ins: %X19
	    Predecessors according to CFG: BB#16
1376B		%vreg56<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg56
1384B		%vreg54<def> = MOVi32imm 4294967294; GPR32:%vreg54
1392B		STRWui %vreg54<kill>, %vreg56<kill>, 1274; mem:ST4[%lastErr26] GPR32:%vreg54 GPR64common:%vreg56
	    Successors according to CFG: BB#18
> %X8<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4]
> %W9<def> = MOVi32imm 4294967294
> STRWui %W9<kill>, %X8<kill>, 1274; mem:ST4[%lastErr26]
1408B	BB#18: derived from LLVM BB %if.end.27
	    Live Ins: %X19
	    Predecessors according to CFG: BB#16 BB#17
1424B		B <BB#24>
	    Successors according to CFG: BB#24
> B <BB#24>
1440B	BB#19: derived from LLVM BB %if.end.28
	    Live Ins: %X19
	    Predecessors according to CFG: BB#13
1456B		%vreg28<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg28
1472B		CBZX %vreg28<kill>, <BB#21>; GPR64:%vreg28
	    Successors according to CFG: BB#21 BB#20
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> CBZX %X8<kill>, <BB#21>
1488B	BB#20: derived from LLVM BB %if.then.30
	    Live Ins: %X19
	    Predecessors according to CFG: BB#19
1504B		%vreg30<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg30
1520B		STRWui %WZR, %vreg30<kill>, 0; mem:ST4[%20] GPR64common:%vreg30
	    Successors according to CFG: BB#21
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> STRWui %WZR, %X8<kill>, 0; mem:ST4[%20]
1536B	BB#21: derived from LLVM BB %if.end.31
	    Live Ins: %X19
	    Predecessors according to CFG: BB#19 BB#20
1552B		%vreg32<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64:%vreg32
1568B		CBZX %vreg32<kill>, <BB#23>; GPR64:%vreg32
	    Successors according to CFG: BB#23 BB#22
> %X8<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4]
> CBZX %X8<kill>, <BB#23>
1584B	BB#22: derived from LLVM BB %if.then.33
	    Live Ins: %X19
	    Predecessors according to CFG: BB#21
1600B		%vreg34<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg34
1616B		STRWui %WZR, %vreg34<kill>, 1274; mem:ST4[%lastErr34] GPR64common:%vreg34
	    Successors according to CFG: BB#23
> %X8<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4]
> STRWui %WZR, %X8<kill>, 1274; mem:ST4[%lastErr34]
1632B	BB#23: derived from LLVM BB %if.end.35
	    Live Ins: %X19
	    Predecessors according to CFG: BB#21 BB#22
1648B		%vreg46<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg46
1680B		%vreg43<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg43
1688B		%vreg45<def> = LDRWui %vreg46<kill>, 1256; mem:LD4[%avail_in] GPR32:%vreg45 GPR64common:%vreg46
1696B		STRWui %vreg45<kill>, %vreg43<kill>, 0; mem:ST4[%25] GPR32:%vreg45 GPR64common:%vreg43
1712B		%vreg40<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4] GPR64common:%vreg40
1728B		%vreg39<def> = LDRXui %vreg40<kill>, 627; mem:LD8[%next_in] GPR64:%vreg39 GPR64common:%vreg40
1744B		%vreg37<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg37
1760B		STRXui %vreg39<kill>, %vreg37<kill>, 0; mem:ST8[%28] GPR64:%vreg39 GPR64common:%vreg37
	    Successors according to CFG: BB#24
> %X8<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4]
> %X9<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> %W8<def> = LDRWui %X8<kill>, 1256; mem:LD4[%avail_in]
> STRWui %W8<kill>, %X9<kill>, 0; mem:ST4[%25]
> %X8<def> = LDRXui <fi#4>, 0; mem:LD8[FixedStack4]
> %X8<def> = LDRXui %X8<kill>, 627; mem:LD8[%next_in]
> %X9<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2]
> STRXui %X8<kill>, %X9<kill>, 0; mem:ST8[%28]
1776B	BB#24: derived from LLVM BB %return
	    Live Ins: %X19
	    Predecessors according to CFG: BB#23 BB#18 BB#11 BB#5
1792B		%vreg77<def> = ADRP <ga:@BZ2_bzReadGetUnused>[TF=1]; GPR64common:%vreg77
1808B		%vreg79<def> = ADDXri %vreg77<kill>, <ga:@BZ2_bzReadGetUnused>[TF=34], 0; GPR64sp:%vreg79 GPR64common:%vreg77
1856B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1872B		%X0<def> = COPY %vreg79<kill>; GPR64sp:%vreg79
1888B		%X1<def> = COPY %vreg17<kill>; GPR64:%vreg17
1904B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
1920B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1936B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1952B		STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...
1968B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1984B		RET_ReallyLR
> %X8<def> = ADRP <ga:@BZ2_bzReadGetUnused>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@BZ2_bzReadGetUnused>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19<kill>
> BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> RET_ReallyLR
Computing live-in reg-units in ABI blocks.
0B	BB#0 W0#0 W1#0 W2#0 W3#0 W4#0 W5#0 W6#0 W30#0
Created 8 new intervals.
********** INTERVALS **********
W30 [0B,16r:0)[368r,368d:14)[416e,416d:7)[1424r,1424d:13)[1488e,1488d:6)[1872r,1872d:12)[1936e,1936d:5)[2304r,2304d:11)[2368e,2368d:4)[2496r,2496d:9)[2576e,2576d:3)[2704r,2704d:10)[2768e,2768d:2)[2960r,2960d:8)[3008e,3008d:1)  0@0B-phi 1@3008e 2@2768e 3@2576e 4@2368e 5@1936e 6@1488e 7@416e 8@2960r 9@2496r 10@2704r 11@2304r 12@1872r 13@1424r 14@368r
W0 [0B,128r:0)[336r,368r:13)[1360r,1424r:12)[1424r,1456r:6)[1840r,1872r:11)[1872r,1904r:5)[2288r,2304r:10)[2304r,2336r:4)[2480r,2496r:8)[2496r,2528r:2)[2688r,2704r:9)[2704r,2736r:3)[2928r,2960r:7)[3056r,3072r:1)  0@0B-phi 1@3056r 2@2496r 3@2704r 4@2304r 5@1872r 6@1424r 7@2928r 8@2480r 9@2688r 10@2288r 11@1840r 12@1360r 13@336r
W1 [0B,112r:0)[352r,368r:4)[1376r,1424r:2)[1856r,1872r:1)[2944r,2960r:3)  0@0B-phi 1@1856r 2@1376r 3@2944r 4@352r
W2 [0B,96r:0)[1392r,1424r:1)  0@0B-phi 1@1392r
W3 [0B,80r:0)[1408r,1424r:1)  0@0B-phi 1@1408r
W4 [0B,64r:0)  0@0B-phi
W5 [0B,48r:0)  0@0B-phi
W6 [0B,32r:0)  0@0B-phi
%vreg0 [128r,144r:0)  0@128r
%vreg1 [144r,448r:0)  0@144r
%vreg2 [112r,160r:0)  0@112r
%vreg3 [160r,464r:0)  0@160r
%vreg4 [96r,176r:0)  0@96r
%vreg5 [176r,480r:0)  0@176r
%vreg6 [80r,192r:0)  0@80r
%vreg7 [192r,496r:0)  0@192r
%vreg8 [64r,208r:0)  0@64r
%vreg9 [208r,512r:0)  0@208r
%vreg10 [48r,224r:0)  0@48r
%vreg11 [224r,528r:0)  0@224r
%vreg12 [32r,240r:0)  0@32r
%vreg13 [240r,544r:0)  0@240r
%vreg15 [560r,576r:0)  0@560r
%vreg16 [256r,272r:0)  0@256r
%vreg17 [272r,288r:0)  0@272r
%vreg18 [288r,336r:0)  0@288r
%vreg19 [304r,352r:0)  0@304r
%vreg20 [16r,2896r:0)  0@16r
%vreg22 [608r,624r:0)  0@608r
%vreg24 [656r,672r:0)  0@656r
%vreg26 [704r,720r:0)  0@704r
%vreg28 [768r,784r:0)  0@768r
%vreg30 [832r,848r:0)  0@832r
%vreg32 [880r,896r:0)  0@880r
%vreg34 [944r,960r:0)  0@944r
%vreg36 [992r,1008r:0)  0@992r
%vreg38 [1120r,1136r:0)  0@1120r
%vreg39 [1168r,1184r:0)  0@1168r
%vreg41 [1536r,1552r:0)  0@1536r
%vreg43 [1216r,1360r:0)  0@1216r
%vreg47 [1456r,1520r:0)  0@1456r
%vreg48 [1328r,1408r:0)  0@1328r
%vreg49 [1312r,1392r:0)  0@1312r
%vreg50 [1296r,1376r:0)  0@1296r
%vreg51 [1232r,1280r:0)  0@1232r
%vreg53 [1984r,2000r:0)  0@1984r
%vreg55 [1648r,1840r:0)  0@1648r
%vreg56 [1664r,1856r:0)  0@1664r
%vreg57 [1904r,1968r:0)  0@1904r
%vreg60 [1792r,1808r:0)  0@1792r
%vreg61 [1776r,1792r:0)  0@1776r
%vreg63 [1744r,1760r:0)  0@1744r
%vreg65 [1712r,1728r:0)  0@1712r
%vreg67 [1680r,1696r:0)  0@1680r
%vreg69 [2080r,2096r:0)  0@2080r
%vreg70 [2176r,2288r:0)  0@2176r
%vreg71 [2336r,2336d:0)  0@2336r
%vreg76 [2240r,2256r:0)  0@2240r
%vreg77 [2224r,2240r:0)  0@2224r
%vreg78 [2208r,2256r:0)  0@2208r
%vreg79 [2192r,2240r:0)  0@2192r
%vreg81 [2800r,2816r:0)  0@2800r
%vreg82 [2656r,2688r:0)  0@2656r
%vreg83 [2736r,2736d:0)  0@2736r
%vreg84 [2544r,2608r:0)  0@2544r
%vreg85 [2448r,2480r:0)  0@2448r
%vreg86 [2528r,2528d:0)  0@2528r
%vreg88 [1584r,1600r:0)  0@1584r
%vreg89 [1056r,1072r:0)  0@1056r
%vreg91 [3040r,3056r:0)  0@3040r
%vreg92 [2848r,2864r:0)  0@2848r
%vreg93 [2864r,2880r:0)  0@2864r
%vreg94 [2880r,2928r:0)  0@2880r
%vreg95 [2896r,2944r:0)  0@2896r
RegMasks: 368r 1424r 1872r 2304r 2496r 2704r 2960r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzBuffToBuffCompress: Post SSA
Frame Objects:
  fi#0: size=4, align=4, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=8, align=8, at location [SP]
  fi#3: size=8, align=8, at location [SP]
  fi#4: size=4, align=4, at location [SP]
  fi#5: size=4, align=4, at location [SP]
  fi#6: size=4, align=4, at location [SP]
  fi#7: size=4, align=4, at location [SP]
  fi#8: size=80, align=8, at location [SP]
  fi#9: size=4, align=4, at location [SP]
Function Live Ins: %X0 in %vreg0, %X1 in %vreg2, %X2 in %vreg4, %W3 in %vreg6, %W4 in %vreg8, %W5 in %vreg10, %W6 in %vreg12, %LR in %vreg20

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %X1 %X2 %W3 %W4 %W5 %W6 %LR
16B		%vreg20<def> = COPY %LR; GPR64:%vreg20
32B		%vreg12<def> = COPY %W6; GPR32:%vreg12
48B		%vreg10<def> = COPY %W5; GPR32:%vreg10
64B		%vreg8<def> = COPY %W4; GPR32:%vreg8
80B		%vreg6<def> = COPY %W3; GPR32:%vreg6
96B		%vreg4<def> = COPY %X2; GPR64:%vreg4
112B		%vreg2<def> = COPY %X1; GPR64:%vreg2
128B		%vreg0<def> = COPY %X0; GPR64:%vreg0
144B		%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
160B		%vreg3<def> = COPY %vreg2; GPR64:%vreg3,%vreg2
176B		%vreg5<def> = COPY %vreg4; GPR64:%vreg5,%vreg4
192B		%vreg7<def> = COPY %vreg6; GPR32:%vreg7,%vreg6
208B		%vreg9<def> = COPY %vreg8; GPR32:%vreg9,%vreg8
224B		%vreg11<def> = COPY %vreg10; GPR32:%vreg11,%vreg10
240B		%vreg13<def> = COPY %vreg12; GPR32:%vreg13,%vreg12
256B		%vreg16<def> = ADRP <ga:@BZ2_bzBuffToBuffCompress>[TF=1]; GPR64common:%vreg16
272B		%vreg17<def> = ADDXri %vreg16, <ga:@BZ2_bzBuffToBuffCompress>[TF=34], 0; GPR64sp:%vreg17 GPR64common:%vreg16
288B		%vreg18<def> = COPY %vreg17; GPR64all:%vreg18 GPR64sp:%vreg17
304B		%vreg19<def> = COPY %vreg20; GPR64all:%vreg19 GPR64:%vreg20
320B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
336B		%X0<def> = COPY %vreg18; GPR64all:%vreg18
352B		%X1<def> = COPY %vreg19; GPR64all:%vreg19
368B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
384B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
400B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
416B		STACKMAP 0, 0, %vreg9, 0, <fi#5>, 0, %vreg1, 0, <fi#1>, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#9>, 0, 0, <fi#0>, 0, %vreg5, 0, <fi#3>, 0, %vreg7, 0, <fi#4>, 0, 0, <fi#8>, 0, %vreg11, 0, <fi#6>, 0, %vreg13, 0, <fi#7>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack5](align=4) LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack9](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3] LD8[FixedStack4](align=4) LD8[FixedStack8] LD8[FixedStack6](align=4) LD8[FixedStack7](align=4) GPR32:%vreg9,%vreg7,%vreg11,%vreg13 GPR64:%vreg1,%vreg3,%vreg5
432B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
448B		STRXui %vreg1, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg1
464B		STRXui %vreg3, <fi#2>, 0; mem:ST8[FixedStack2] GPR64:%vreg3
480B		STRXui %vreg5, <fi#3>, 0; mem:ST8[FixedStack3] GPR64:%vreg5
496B		STRWui %vreg7, <fi#4>, 0; mem:ST4[FixedStack4] GPR32:%vreg7
512B		STRWui %vreg9, <fi#5>, 0; mem:ST4[FixedStack5] GPR32:%vreg9
528B		STRWui %vreg11, <fi#6>, 0; mem:ST4[FixedStack6] GPR32:%vreg11
544B		STRWui %vreg13, <fi#7>, 0; mem:ST4[FixedStack7] GPR32:%vreg13
560B		%vreg15<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg15
576B		CBZX %vreg15, <BB#9>; GPR64:%vreg15
	    Successors according to CFG: BB#9 BB#1

592B	BB#1: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#0
608B		%vreg22<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg22
624B		CBZX %vreg22, <BB#9>; GPR64:%vreg22
	    Successors according to CFG: BB#9 BB#2

640B	BB#2: derived from LLVM BB %lor.lhs.false.2
	    Predecessors according to CFG: BB#1
656B		%vreg24<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg24
672B		CBZX %vreg24, <BB#9>; GPR64:%vreg24
	    Successors according to CFG: BB#9 BB#3

688B	BB#3: derived from LLVM BB %lor.lhs.false.4
	    Predecessors according to CFG: BB#2
704B		%vreg26<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32common:%vreg26
720B		%WZR<def> = SUBSWri %vreg26, 1, 0, %NZCV<imp-def>; GPR32common:%vreg26
736B		Bcc 11, <BB#9>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#9 BB#4

752B	BB#4: derived from LLVM BB %lor.lhs.false.6
	    Predecessors according to CFG: BB#3
768B		%vreg28<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32common:%vreg28
784B		%WZR<def> = SUBSWri %vreg28, 9, 0, %NZCV<imp-def>; GPR32common:%vreg28
800B		Bcc 12, <BB#9>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#9 BB#5

816B	BB#5: derived from LLVM BB %lor.lhs.false.8
	    Predecessors according to CFG: BB#4
832B		%vreg30<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg30
848B		TBNZW %vreg30, 31, <BB#9>; GPR32:%vreg30
	    Successors according to CFG: BB#9 BB#6

864B	BB#6: derived from LLVM BB %lor.lhs.false.10
	    Predecessors according to CFG: BB#5
880B		%vreg32<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32common:%vreg32
896B		%WZR<def> = SUBSWri %vreg32, 4, 0, %NZCV<imp-def>; GPR32common:%vreg32
912B		Bcc 12, <BB#9>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#9 BB#7

928B	BB#7: derived from LLVM BB %lor.lhs.false.12
	    Predecessors according to CFG: BB#6
944B		%vreg34<def> = LDRWui <fi#7>, 0; mem:LD4[FixedStack7] GPR32:%vreg34
960B		TBNZW %vreg34, 31, <BB#9>; GPR32:%vreg34
	    Successors according to CFG: BB#9 BB#8

976B	BB#8: derived from LLVM BB %lor.lhs.false.14
	    Predecessors according to CFG: BB#7
992B		%vreg36<def> = LDRWui <fi#7>, 0; mem:LD4[FixedStack7] GPR32common:%vreg36
1008B		%WZR<def> = SUBSWri %vreg36, 250, 0, %NZCV<imp-def>; GPR32common:%vreg36
1024B		Bcc 13, <BB#10>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#10 BB#9

1040B	BB#9: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0 BB#1 BB#2 BB#3 BB#4 BB#5 BB#6 BB#7 BB#8
1056B		%vreg89<def> = MOVi32imm 4294967294; GPR32:%vreg89
1072B		STRWui %vreg89, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg89
1088B		B <BB#21>
	    Successors according to CFG: BB#21

1104B	BB#10: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#8
1120B		%vreg38<def> = LDRWui <fi#7>, 0; mem:LD4[FixedStack7] GPR32:%vreg38
1136B		CBNZW %vreg38, <BB#12>; GPR32:%vreg38
	    Successors according to CFG: BB#12 BB#11

1152B	BB#11: derived from LLVM BB %if.then.17
	    Predecessors according to CFG: BB#10
1168B		%vreg39<def> = MOVi32imm 30; GPR32:%vreg39
1184B		STRWui %vreg39, <fi#7>, 0; mem:ST4[FixedStack7] GPR32:%vreg39
	    Successors according to CFG: BB#12

1200B	BB#12: derived from LLVM BB %if.end.18
	    Predecessors according to CFG: BB#10 BB#11
1216B		%vreg43<def> = ADDXri <fi#8>, 0, 0; GPR64sp:%vreg43
1232B		%vreg51<def> = COPY %XZR; GPR64:%vreg51
1248B		STRXui %vreg51, <fi#8>, 7; mem:ST80[FixedStack8(align=8)+7](align=1) GPR64:%vreg51
1264B		STRXui %vreg51, <fi#8>, 8; mem:ST80[FixedStack8+8](align=8) GPR64:%vreg51
1280B		STRXui %vreg51, <fi#8>, 9; mem:ST80[FixedStack8(align=8)+9](align=1) GPR64:%vreg51
1296B		%vreg50<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32:%vreg50
1312B		%vreg49<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg49
1328B		%vreg48<def> = LDRWui <fi#7>, 0; mem:LD4[FixedStack7] GPR32:%vreg48
1344B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1360B		%X0<def> = COPY %vreg43; GPR64sp:%vreg43
1376B		%W1<def> = COPY %vreg50; GPR32:%vreg50
1392B		%W2<def> = COPY %vreg49; GPR32:%vreg49
1408B		%W3<def> = COPY %vreg48; GPR32:%vreg48
1424B		BL <ga:@BZ2_bzCompressInit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %W2<imp-use>, %W3<imp-use>, %W0<imp-def>
1440B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1456B		%vreg47<def> = COPY %W0; GPR32:%vreg47
1472B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1488B		STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#9>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, 0, <fi#8>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack9](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3] LD8[FixedStack4](align=4) LD8[FixedStack8]
1504B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1520B		STRWui %vreg47, <fi#9>, 0; mem:ST4[FixedStack9] GPR32:%vreg47
1536B		%vreg41<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32:%vreg41
1552B		CBZW %vreg41, <BB#14>; GPR32:%vreg41
	    Successors according to CFG: BB#14 BB#13

1568B	BB#13: derived from LLVM BB %if.then.20
	    Predecessors according to CFG: BB#12
1584B		%vreg88<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32:%vreg88
1600B		STRWui %vreg88, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg88
1616B		B <BB#21>
	    Successors according to CFG: BB#21

1632B	BB#14: derived from LLVM BB %if.end.21
	    Predecessors according to CFG: BB#12
1648B		%vreg55<def> = ADDXri <fi#8>, 0, 0; GPR64sp:%vreg55
1664B		%vreg56<def> = MOVi32imm 2; GPR32:%vreg56
1680B		%vreg67<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg67
1696B		STRXui %vreg67, <fi#8>, 0; mem:ST80[FixedStack8](align=8) GPR64:%vreg67
1712B		%vreg65<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg65
1728B		STRXui %vreg65, <fi#8>, 3; mem:ST80[FixedStack8(align=8)+3](align=1) GPR64:%vreg65
1744B		%vreg63<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg63
1760B		STRWui %vreg63, <fi#8>, 2; mem:ST80[FixedStack8(align=8)+2](align=2) GPR32:%vreg63
1776B		%vreg61<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg61
1792B		%vreg60<def> = LDRWui %vreg61, 0; mem:LD4[%18] GPR32:%vreg60 GPR64common:%vreg61
1808B		STRWui %vreg60, <fi#8>, 8; mem:ST80[FixedStack8+8](align=8) GPR32:%vreg60
1824B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1840B		%X0<def> = COPY %vreg55; GPR64sp:%vreg55
1856B		%W1<def> = COPY %vreg56; GPR32:%vreg56
1872B		BL <ga:@BZ2_bzCompress>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %W0<imp-def>
1888B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1904B		%vreg57<def> = COPY %W0; GPR32:%vreg57
1920B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1936B		STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#9>, 0, 0, <fi#0>, 0, 0, <fi#8>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2] LD8[FixedStack9](align=4) LD8[FixedStack0](align=4) LD8[FixedStack8]
1952B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1968B		STRWui %vreg57, <fi#9>, 0; mem:ST4[FixedStack9] GPR32:%vreg57
1984B		%vreg53<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32common:%vreg53
2000B		%WZR<def> = SUBSWri %vreg53, 3, 0, %NZCV<imp-def>; GPR32common:%vreg53
2016B		Bcc 1, <BB#16>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#16 BB#15

2032B	BB#15: derived from LLVM BB %if.then.24
	    Predecessors according to CFG: BB#14
2048B		B <BB#19>
	    Successors according to CFG: BB#19

2064B	BB#16: derived from LLVM BB %if.end.25
	    Predecessors according to CFG: BB#14
2080B		%vreg69<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32common:%vreg69
2096B		%WZR<def> = SUBSWri %vreg69, 4, 0, %NZCV<imp-def>; GPR32common:%vreg69
2112B		Bcc 0, <BB#18>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#18 BB#17

2128B	BB#17: derived from LLVM BB %if.then.27
	    Predecessors according to CFG: BB#16
2144B		B <BB#20>
	    Successors according to CFG: BB#20

2160B	BB#18: derived from LLVM BB %if.end.28
	    Predecessors according to CFG: BB#16
2176B		%vreg70<def> = ADDXri <fi#8>, 0, 0; GPR64sp:%vreg70
2192B		%vreg79<def> = LDRWui <fi#8>, 8; mem:LD80[FixedStack8+8](align=8) GPR32:%vreg79
2208B		%vreg78<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg78
2224B		%vreg77<def> = LDRWui %vreg78, 0; mem:LD4[%23] GPR32:%vreg77 GPR64common:%vreg78
2240B		%vreg76<def> = SUBWrr %vreg77, %vreg79; GPR32:%vreg76,%vreg77,%vreg79
2256B		STRWui %vreg76, %vreg78, 0; mem:ST4[%23] GPR32:%vreg76 GPR64common:%vreg78
2272B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2288B		%X0<def> = COPY %vreg70; GPR64sp:%vreg70
2304B		BL <ga:@BZ2_bzCompressEnd>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
2320B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2336B		%vreg71<def,dead> = COPY %W0; GPR32all:%vreg71
2352B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2368B		STACKMAP 3, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
2384B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2400B		STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
2416B		B <BB#21>
	    Successors according to CFG: BB#21

2432B	BB#19: derived from LLVM BB %output_overflow
	    Predecessors according to CFG: BB#15
2448B		%vreg85<def> = ADDXri <fi#8>, 0, 0; GPR64sp:%vreg85
2464B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2480B		%X0<def> = COPY %vreg85; GPR64sp:%vreg85
2496B		BL <ga:@BZ2_bzCompressEnd>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
2512B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2528B		%vreg86<def,dead> = COPY %W0; GPR32all:%vreg86
2544B		%vreg84<def> = MOVi32imm 4294967288; GPR32:%vreg84
2560B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2576B		STACKMAP 4, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
2592B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2608B		STRWui %vreg84, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg84
2624B		B <BB#21>
	    Successors according to CFG: BB#21

2640B	BB#20: derived from LLVM BB %errhandler
	    Predecessors according to CFG: BB#17
2656B		%vreg82<def> = ADDXri <fi#8>, 0, 0; GPR64sp:%vreg82
2672B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2688B		%X0<def> = COPY %vreg82; GPR64sp:%vreg82
2704B		BL <ga:@BZ2_bzCompressEnd>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
2720B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2736B		%vreg83<def,dead> = COPY %W0; GPR32all:%vreg83
2752B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2768B		STACKMAP 5, 0, 0, <fi#9>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack9](align=4) LD8[FixedStack0](align=4)
2784B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2800B		%vreg81<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32:%vreg81
2816B		STRWui %vreg81, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg81
	    Successors according to CFG: BB#21

2832B	BB#21: derived from LLVM BB %return
	    Predecessors according to CFG: BB#18 BB#20 BB#19 BB#13 BB#9
2848B		%vreg92<def> = ADRP <ga:@BZ2_bzBuffToBuffCompress>[TF=1]; GPR64common:%vreg92
2864B		%vreg93<def> = ADDXri %vreg92, <ga:@BZ2_bzBuffToBuffCompress>[TF=34], 0; GPR64sp:%vreg93 GPR64common:%vreg92
2880B		%vreg94<def> = COPY %vreg93; GPR64all:%vreg94 GPR64sp:%vreg93
2896B		%vreg95<def> = COPY %vreg20; GPR64all:%vreg95 GPR64:%vreg20
2912B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2928B		%X0<def> = COPY %vreg94; GPR64all:%vreg94
2944B		%X1<def> = COPY %vreg95; GPR64all:%vreg95
2960B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
2976B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2992B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3008B		STACKMAP 6, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
3024B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3040B		%vreg91<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0] GPR32:%vreg91
3056B		%W0<def> = COPY %vreg91; GPR32:%vreg91
3072B		RET_ReallyLR %W0<imp-use>

# End machine code for function BZ2_bzBuffToBuffCompress.

********** SIMPLE REGISTER COALESCING **********
********** Function: BZ2_bzBuffToBuffCompress
********** JOINING INTERVALS ***********
if.then:
return:
2928B	%X0<def> = COPY %vreg94; GPR64all:%vreg94
	Considering merging %vreg94 with %X0
	Can only merge into reserved registers.
2944B	%X1<def> = COPY %vreg95; GPR64all:%vreg95
	Considering merging %vreg95 with %X1
	Can only merge into reserved registers.
3056B	%W0<def> = COPY %vreg91; GPR32:%vreg91
	Considering merging %vreg91 with %W0
	Can only merge into reserved registers.
if.end.18:
1232B	%vreg51<def> = COPY %XZR; GPR64:%vreg51
	Considering merging %vreg51 with %XZR
		RHS = %vreg51 [1232r,1280r:0)  0@1232r
		updated: 1280B	STRXui %XZR, <fi#8>, 9; mem:ST80[FixedStack8(align=8)+9](align=1)
		updated: 1264B	STRXui %XZR, <fi#8>, 8; mem:ST80[FixedStack8+8](align=8)
		updated: 1248B	STRXui %XZR, <fi#8>, 7; mem:ST80[FixedStack8(align=8)+7](align=1)
	Success: %vreg51 -> %XZR
	Result = %XZR
1360B	%X0<def> = COPY %vreg43; GPR64sp:%vreg43
	Considering merging %vreg43 with %X0
	Can only merge into reserved registers.
Remat: %X0<def> = ADDXri <fi#8>, 0, 0
Shrink: %vreg43 [1216r,1360r:0)  0@1216r
All defs dead: 1216r	%vreg43<def,dead> = ADDXri <fi#8>, 0, 0; GPR64sp:%vreg43
Shrunk: %vreg43 [1216r,1216d:0)  0@1216r
Deleting dead def 1216r	%vreg43<def,dead> = ADDXri <fi#8>, 0, 0; GPR64sp:%vreg43
1376B	%W1<def> = COPY %vreg50; GPR32:%vreg50
	Considering merging %vreg50 with %W1
	Can only merge into reserved registers.
1392B	%W2<def> = COPY %vreg49; GPR32:%vreg49
	Considering merging %vreg49 with %W2
	Can only merge into reserved registers.
1408B	%W3<def> = COPY %vreg48; GPR32:%vreg48
	Considering merging %vreg48 with %W3
	Can only merge into reserved registers.
1456B	%vreg47<def> = COPY %W0; GPR32:%vreg47
	Considering merging %vreg47 with %W0
	Can only merge into reserved registers.
lor.lhs.false:
lor.lhs.false.2:
lor.lhs.false.4:
lor.lhs.false.6:
lor.lhs.false.8:
lor.lhs.false.10:
lor.lhs.false.12:
lor.lhs.false.14:
if.end:
if.end.21:
1840B	%X0<def> = COPY %vreg55; GPR64sp:%vreg55
	Considering merging %vreg55 with %X0
	Can only merge into reserved registers.
Remat: %X0<def> = ADDXri <fi#8>, 0, 0
Shrink: %vreg55 [1648r,1840r:0)  0@1648r
All defs dead: 1648r	%vreg55<def,dead> = ADDXri <fi#8>, 0, 0; GPR64sp:%vreg55
Shrunk: %vreg55 [1648r,1648d:0)  0@1648r
Deleting dead def 1648r	%vreg55<def,dead> = ADDXri <fi#8>, 0, 0; GPR64sp:%vreg55
1856B	%W1<def> = COPY %vreg56; GPR32:%vreg56
	Considering merging %vreg56 with %W1
	Can only merge into reserved registers.
Remat: %W1<def> = MOVi32imm 2
Shrink: %vreg56 [1664r,1856r:0)  0@1664r
All defs dead: 1664r	%vreg56<def,dead> = MOVi32imm 2; GPR32:%vreg56
Shrunk: %vreg56 [1664r,1664d:0)  0@1664r
Deleting dead def 1664r	%vreg56<def,dead> = MOVi32imm 2; GPR32:%vreg56
1904B	%vreg57<def> = COPY %W0; GPR32:%vreg57
	Considering merging %vreg57 with %W0
	Can only merge into reserved registers.
if.end.25:
entry:
16B	%vreg20<def> = COPY %LR; GPR64:%vreg20
	Considering merging %vreg20 with %LR
	Can only merge into reserved registers.
32B	%vreg12<def> = COPY %W6; GPR32:%vreg12
	Considering merging %vreg12 with %W6
	Can only merge into reserved registers.
48B	%vreg10<def> = COPY %W5; GPR32:%vreg10
	Considering merging %vreg10 with %W5
	Can only merge into reserved registers.
64B	%vreg8<def> = COPY %W4; GPR32:%vreg8
	Considering merging %vreg8 with %W4
	Can only merge into reserved registers.
80B	%vreg6<def> = COPY %W3; GPR32:%vreg6
	Considering merging %vreg6 with %W3
	Can only merge into reserved registers.
96B	%vreg4<def> = COPY %X2; GPR64:%vreg4
	Considering merging %vreg4 with %X2
	Can only merge into reserved registers.
112B	%vreg2<def> = COPY %X1; GPR64:%vreg2
	Considering merging %vreg2 with %X1
	Can only merge into reserved registers.
128B	%vreg0<def> = COPY %X0; GPR64:%vreg0
	Considering merging %vreg0 with %X0
	Can only merge into reserved registers.
336B	%X0<def> = COPY %vreg18; GPR64all:%vreg18
	Considering merging %vreg18 with %X0
	Can only merge into reserved registers.
352B	%X1<def> = COPY %vreg19; GPR64all:%vreg19
	Considering merging %vreg19 with %X1
	Can only merge into reserved registers.
if.then.17:
if.then.20:
if.then.24:
if.then.27:
if.end.28:
2288B	%X0<def> = COPY %vreg70; GPR64sp:%vreg70
	Considering merging %vreg70 with %X0
	Can only merge into reserved registers.
Remat: %X0<def> = ADDXri <fi#8>, 0, 0
Shrink: %vreg70 [2176r,2288r:0)  0@2176r
All defs dead: 2176r	%vreg70<def,dead> = ADDXri <fi#8>, 0, 0; GPR64sp:%vreg70
Shrunk: %vreg70 [2176r,2176d:0)  0@2176r
Deleting dead def 2176r	%vreg70<def,dead> = ADDXri <fi#8>, 0, 0; GPR64sp:%vreg70
2336B	%vreg71<def,dead> = COPY %W0; GPR32all:%vreg71
	Considering merging %vreg71 with %W0
	Can only merge into reserved registers.
output_overflow:
2480B	%X0<def> = COPY %vreg85; GPR64sp:%vreg85
	Considering merging %vreg85 with %X0
	Can only merge into reserved registers.
Remat: %X0<def> = ADDXri <fi#8>, 0, 0
Shrink: %vreg85 [2448r,2480r:0)  0@2448r
All defs dead: 2448r	%vreg85<def,dead> = ADDXri <fi#8>, 0, 0; GPR64sp:%vreg85
Shrunk: %vreg85 [2448r,2448d:0)  0@2448r
Deleting dead def 2448r	%vreg85<def,dead> = ADDXri <fi#8>, 0, 0; GPR64sp:%vreg85
2528B	%vreg86<def,dead> = COPY %W0; GPR32all:%vreg86
	Considering merging %vreg86 with %W0
	Can only merge into reserved registers.
errhandler:
2688B	%X0<def> = COPY %vreg82; GPR64sp:%vreg82
	Considering merging %vreg82 with %X0
	Can only merge into reserved registers.
Remat: %X0<def> = ADDXri <fi#8>, 0, 0
Shrink: %vreg82 [2656r,2688r:0)  0@2656r
All defs dead: 2656r	%vreg82<def,dead> = ADDXri <fi#8>, 0, 0; GPR64sp:%vreg82
Shrunk: %vreg82 [2656r,2656d:0)  0@2656r
Deleting dead def 2656r	%vreg82<def,dead> = ADDXri <fi#8>, 0, 0; GPR64sp:%vreg82
2736B	%vreg83<def,dead> = COPY %W0; GPR32all:%vreg83
	Considering merging %vreg83 with %W0
	Can only merge into reserved registers.
2880B	%vreg94<def> = COPY %vreg93; GPR64all:%vreg94 GPR64sp:%vreg93
	Considering merging to GPR64sp with %vreg93 in %vreg94
		RHS = %vreg93 [2864r,2880r:0)  0@2864r
		LHS = %vreg94 [2880r,2928r:0)  0@2880r
		merge %vreg94:0@2880r into %vreg93:0@2864r --> @2864r
		erased:	2880r	%vreg94<def> = COPY %vreg93; GPR64all:%vreg94 GPR64sp:%vreg93
		updated: 2864B	%vreg94<def> = ADDXri %vreg92, <ga:@BZ2_bzBuffToBuffCompress>[TF=34], 0; GPR64sp:%vreg94 GPR64common:%vreg92
	Success: %vreg93 -> %vreg94
	Result = %vreg94 [2864r,2928r:0)  0@2864r
2896B	%vreg95<def> = COPY %vreg20; GPR64all:%vreg95 GPR64:%vreg20
	Considering merging to GPR64 with %vreg20 in %vreg95
		RHS = %vreg20 [16r,2896r:0)  0@16r
		LHS = %vreg95 [2896r,2944r:0)  0@2896r
		merge %vreg95:0@2896r into %vreg20:0@16r --> @16r
		erased:	2896r	%vreg95<def> = COPY %vreg20; GPR64all:%vreg95 GPR64:%vreg20
		updated: 16B	%vreg95<def> = COPY %LR; GPR64:%vreg95
		updated: 304B	%vreg19<def> = COPY %vreg95; GPR64all:%vreg19 GPR64:%vreg95
	Success: %vreg20 -> %vreg95
	Result = %vreg95 [16r,2944r:0)  0@16r
144B	%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
	Considering merging to GPR64 with %vreg0 in %vreg1
		RHS = %vreg0 [128r,144r:0)  0@128r
		LHS = %vreg1 [144r,448r:0)  0@144r
		merge %vreg1:0@144r into %vreg0:0@128r --> @128r
		erased:	144r	%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
		updated: 128B	%vreg1<def> = COPY %X0; GPR64:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [128r,448r:0)  0@128r
160B	%vreg3<def> = COPY %vreg2; GPR64:%vreg3,%vreg2
	Considering merging to GPR64 with %vreg2 in %vreg3
		RHS = %vreg2 [112r,160r:0)  0@112r
		LHS = %vreg3 [160r,464r:0)  0@160r
		merge %vreg3:0@160r into %vreg2:0@112r --> @112r
		erased:	160r	%vreg3<def> = COPY %vreg2; GPR64:%vreg3,%vreg2
		updated: 112B	%vreg3<def> = COPY %X1; GPR64:%vreg3
	Success: %vreg2 -> %vreg3
	Result = %vreg3 [112r,464r:0)  0@112r
176B	%vreg5<def> = COPY %vreg4; GPR64:%vreg5,%vreg4
	Considering merging to GPR64 with %vreg4 in %vreg5
		RHS = %vreg4 [96r,176r:0)  0@96r
		LHS = %vreg5 [176r,480r:0)  0@176r
		merge %vreg5:0@176r into %vreg4:0@96r --> @96r
		erased:	176r	%vreg5<def> = COPY %vreg4; GPR64:%vreg5,%vreg4
		updated: 96B	%vreg5<def> = COPY %X2; GPR64:%vreg5
	Success: %vreg4 -> %vreg5
	Result = %vreg5 [96r,480r:0)  0@96r
192B	%vreg7<def> = COPY %vreg6; GPR32:%vreg7,%vreg6
	Considering merging to GPR32 with %vreg6 in %vreg7
		RHS = %vreg6 [80r,192r:0)  0@80r
		LHS = %vreg7 [192r,496r:0)  0@192r
		merge %vreg7:0@192r into %vreg6:0@80r --> @80r
		erased:	192r	%vreg7<def> = COPY %vreg6; GPR32:%vreg7,%vreg6
		updated: 80B	%vreg7<def> = COPY %W3; GPR32:%vreg7
	Success: %vreg6 -> %vreg7
	Result = %vreg7 [80r,496r:0)  0@80r
208B	%vreg9<def> = COPY %vreg8; GPR32:%vreg9,%vreg8
	Considering merging to GPR32 with %vreg8 in %vreg9
		RHS = %vreg8 [64r,208r:0)  0@64r
		LHS = %vreg9 [208r,512r:0)  0@208r
		merge %vreg9:0@208r into %vreg8:0@64r --> @64r
		erased:	208r	%vreg9<def> = COPY %vreg8; GPR32:%vreg9,%vreg8
		updated: 64B	%vreg9<def> = COPY %W4; GPR32:%vreg9
	Success: %vreg8 -> %vreg9
	Result = %vreg9 [64r,512r:0)  0@64r
224B	%vreg11<def> = COPY %vreg10; GPR32:%vreg11,%vreg10
	Considering merging to GPR32 with %vreg10 in %vreg11
		RHS = %vreg10 [48r,224r:0)  0@48r
		LHS = %vreg11 [224r,528r:0)  0@224r
		merge %vreg11:0@224r into %vreg10:0@48r --> @48r
		erased:	224r	%vreg11<def> = COPY %vreg10; GPR32:%vreg11,%vreg10
		updated: 48B	%vreg11<def> = COPY %W5; GPR32:%vreg11
	Success: %vreg10 -> %vreg11
	Result = %vreg11 [48r,528r:0)  0@48r
240B	%vreg13<def> = COPY %vreg12; GPR32:%vreg13,%vreg12
	Considering merging to GPR32 with %vreg12 in %vreg13
		RHS = %vreg12 [32r,240r:0)  0@32r
		LHS = %vreg13 [240r,544r:0)  0@240r
		merge %vreg13:0@240r into %vreg12:0@32r --> @32r
		erased:	240r	%vreg13<def> = COPY %vreg12; GPR32:%vreg13,%vreg12
		updated: 32B	%vreg13<def> = COPY %W6; GPR32:%vreg13
	Success: %vreg12 -> %vreg13
	Result = %vreg13 [32r,544r:0)  0@32r
288B	%vreg18<def> = COPY %vreg17; GPR64all:%vreg18 GPR64sp:%vreg17
	Considering merging to GPR64sp with %vreg17 in %vreg18
		RHS = %vreg17 [272r,288r:0)  0@272r
		LHS = %vreg18 [288r,336r:0)  0@288r
		merge %vreg18:0@288r into %vreg17:0@272r --> @272r
		erased:	288r	%vreg18<def> = COPY %vreg17; GPR64all:%vreg18 GPR64sp:%vreg17
		updated: 272B	%vreg18<def> = ADDXri %vreg16, <ga:@BZ2_bzBuffToBuffCompress>[TF=34], 0; GPR64sp:%vreg18 GPR64common:%vreg16
	Success: %vreg17 -> %vreg18
	Result = %vreg18 [272r,336r:0)  0@272r
304B	%vreg19<def> = COPY %vreg95; GPR64all:%vreg19 GPR64:%vreg95
	Considering merging to GPR64 with %vreg95 in %vreg19
		RHS = %vreg95 [16r,2944r:0)  0@16r
		LHS = %vreg19 [304r,352r:0)  0@304r
		merge %vreg19:0@304r into %vreg95:0@16r --> @16r
		erased:	304r	%vreg19<def> = COPY %vreg95; GPR64all:%vreg19 GPR64:%vreg95
		updated: 16B	%vreg19<def> = COPY %LR; GPR64:%vreg19
		updated: 2944B	%X1<def> = COPY %vreg19; GPR64:%vreg19
	Success: %vreg95 -> %vreg19
	Result = %vreg19 [16r,2944r:0)  0@16r
2928B	%X0<def> = COPY %vreg94; GPR64sp:%vreg94
	Considering merging %vreg94 with %X0
	Can only merge into reserved registers.
2944B	%X1<def> = COPY %vreg19; GPR64:%vreg19
	Considering merging %vreg19 with %X1
	Can only merge into reserved registers.
336B	%X0<def> = COPY %vreg18; GPR64sp:%vreg18
	Considering merging %vreg18 with %X0
	Can only merge into reserved registers.
352B	%X1<def> = COPY %vreg19; GPR64:%vreg19
	Considering merging %vreg19 with %X1
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
W30 [0B,16r:0)[368r,368d:14)[416e,416d:7)[1424r,1424d:13)[1488e,1488d:6)[1872r,1872d:12)[1936e,1936d:5)[2304r,2304d:11)[2368e,2368d:4)[2496r,2496d:9)[2576e,2576d:3)[2704r,2704d:10)[2768e,2768d:2)[2960r,2960d:8)[3008e,3008d:1)  0@0B-phi 1@3008e 2@2768e 3@2576e 4@2368e 5@1936e 6@1488e 7@416e 8@2960r 9@2496r 10@2704r 11@2304r 12@1872r 13@1424r 14@368r
WZR [720r,720d:5)[784r,784d:4)[896r,896d:3)[1008r,1008d:2)[2000r,2000d:1)[2096r,2096d:0)  0@2096r 1@2000r 2@1008r 3@896r 4@784r 5@720r
W0 [0B,128r:0)[336r,368r:13)[1360r,1424r:12)[1424r,1456r:6)[1840r,1872r:11)[1872r,1904r:5)[2288r,2304r:10)[2304r,2336r:4)[2480r,2496r:8)[2496r,2528r:2)[2688r,2704r:9)[2704r,2736r:3)[2928r,2960r:7)[3056r,3072r:1)  0@0B-phi 1@3056r 2@2496r 3@2704r 4@2304r 5@1872r 6@1424r 7@2928r 8@2480r 9@2688r 10@2288r 11@1840r 12@1360r 13@336r
W1 [0B,112r:0)[352r,368r:4)[1376r,1424r:2)[1856r,1872r:1)[2944r,2960r:3)  0@0B-phi 1@1856r 2@1376r 3@2944r 4@352r
W2 [0B,96r:0)[1392r,1424r:1)  0@0B-phi 1@1392r
W3 [0B,80r:0)[1408r,1424r:1)  0@0B-phi 1@1408r
W4 [0B,64r:0)  0@0B-phi
W5 [0B,48r:0)  0@0B-phi
W6 [0B,32r:0)  0@0B-phi
%vreg1 [128r,448r:0)  0@128r
%vreg3 [112r,464r:0)  0@112r
%vreg5 [96r,480r:0)  0@96r
%vreg7 [80r,496r:0)  0@80r
%vreg9 [64r,512r:0)  0@64r
%vreg11 [48r,528r:0)  0@48r
%vreg13 [32r,544r:0)  0@32r
%vreg15 [560r,576r:0)  0@560r
%vreg16 [256r,272r:0)  0@256r
%vreg18 [272r,336r:0)  0@272r
%vreg19 [16r,2944r:0)  0@16r
%vreg22 [608r,624r:0)  0@608r
%vreg24 [656r,672r:0)  0@656r
%vreg26 [704r,720r:0)  0@704r
%vreg28 [768r,784r:0)  0@768r
%vreg30 [832r,848r:0)  0@832r
%vreg32 [880r,896r:0)  0@880r
%vreg34 [944r,960r:0)  0@944r
%vreg36 [992r,1008r:0)  0@992r
%vreg38 [1120r,1136r:0)  0@1120r
%vreg39 [1168r,1184r:0)  0@1168r
%vreg41 [1536r,1552r:0)  0@1536r
%vreg47 [1456r,1520r:0)  0@1456r
%vreg48 [1328r,1408r:0)  0@1328r
%vreg49 [1312r,1392r:0)  0@1312r
%vreg50 [1296r,1376r:0)  0@1296r
%vreg53 [1984r,2000r:0)  0@1984r
%vreg57 [1904r,1968r:0)  0@1904r
%vreg60 [1792r,1808r:0)  0@1792r
%vreg61 [1776r,1792r:0)  0@1776r
%vreg63 [1744r,1760r:0)  0@1744r
%vreg65 [1712r,1728r:0)  0@1712r
%vreg67 [1680r,1696r:0)  0@1680r
%vreg69 [2080r,2096r:0)  0@2080r
%vreg71 [2336r,2336d:0)  0@2336r
%vreg76 [2240r,2256r:0)  0@2240r
%vreg77 [2224r,2240r:0)  0@2224r
%vreg78 [2208r,2256r:0)  0@2208r
%vreg79 [2192r,2240r:0)  0@2192r
%vreg81 [2800r,2816r:0)  0@2800r
%vreg83 [2736r,2736d:0)  0@2736r
%vreg84 [2544r,2608r:0)  0@2544r
%vreg86 [2528r,2528d:0)  0@2528r
%vreg88 [1584r,1600r:0)  0@1584r
%vreg89 [1056r,1072r:0)  0@1056r
%vreg91 [3040r,3056r:0)  0@3040r
%vreg92 [2848r,2864r:0)  0@2848r
%vreg94 [2864r,2928r:0)  0@2864r
RegMasks: 368r 1424r 1872r 2304r 2496r 2704r 2960r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzBuffToBuffCompress: Post SSA
Frame Objects:
  fi#0: size=4, align=4, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=8, align=8, at location [SP]
  fi#3: size=8, align=8, at location [SP]
  fi#4: size=4, align=4, at location [SP]
  fi#5: size=4, align=4, at location [SP]
  fi#6: size=4, align=4, at location [SP]
  fi#7: size=4, align=4, at location [SP]
  fi#8: size=80, align=8, at location [SP]
  fi#9: size=4, align=4, at location [SP]
Function Live Ins: %X0 in %vreg0, %X1 in %vreg2, %X2 in %vreg4, %W3 in %vreg6, %W4 in %vreg8, %W5 in %vreg10, %W6 in %vreg12, %LR in %vreg20

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %X1 %X2 %W3 %W4 %W5 %W6 %LR
16B		%vreg19<def> = COPY %LR; GPR64:%vreg19
32B		%vreg13<def> = COPY %W6; GPR32:%vreg13
48B		%vreg11<def> = COPY %W5; GPR32:%vreg11
64B		%vreg9<def> = COPY %W4; GPR32:%vreg9
80B		%vreg7<def> = COPY %W3; GPR32:%vreg7
96B		%vreg5<def> = COPY %X2; GPR64:%vreg5
112B		%vreg3<def> = COPY %X1; GPR64:%vreg3
128B		%vreg1<def> = COPY %X0; GPR64:%vreg1
256B		%vreg16<def> = ADRP <ga:@BZ2_bzBuffToBuffCompress>[TF=1]; GPR64common:%vreg16
272B		%vreg18<def> = ADDXri %vreg16, <ga:@BZ2_bzBuffToBuffCompress>[TF=34], 0; GPR64sp:%vreg18 GPR64common:%vreg16
320B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
336B		%X0<def> = COPY %vreg18; GPR64sp:%vreg18
352B		%X1<def> = COPY %vreg19; GPR64:%vreg19
368B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
384B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
400B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
416B		STACKMAP 0, 0, %vreg9, 0, <fi#5>, 0, %vreg1, 0, <fi#1>, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#9>, 0, 0, <fi#0>, 0, %vreg5, 0, <fi#3>, 0, %vreg7, 0, <fi#4>, 0, 0, <fi#8>, 0, %vreg11, 0, <fi#6>, 0, %vreg13, 0, <fi#7>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack5](align=4) LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack9](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3] LD8[FixedStack4](align=4) LD8[FixedStack8] LD8[FixedStack6](align=4) LD8[FixedStack7](align=4) GPR32:%vreg9,%vreg7,%vreg11,%vreg13 GPR64:%vreg1,%vreg3,%vreg5
432B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
448B		STRXui %vreg1, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg1
464B		STRXui %vreg3, <fi#2>, 0; mem:ST8[FixedStack2] GPR64:%vreg3
480B		STRXui %vreg5, <fi#3>, 0; mem:ST8[FixedStack3] GPR64:%vreg5
496B		STRWui %vreg7, <fi#4>, 0; mem:ST4[FixedStack4] GPR32:%vreg7
512B		STRWui %vreg9, <fi#5>, 0; mem:ST4[FixedStack5] GPR32:%vreg9
528B		STRWui %vreg11, <fi#6>, 0; mem:ST4[FixedStack6] GPR32:%vreg11
544B		STRWui %vreg13, <fi#7>, 0; mem:ST4[FixedStack7] GPR32:%vreg13
560B		%vreg15<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg15
576B		CBZX %vreg15, <BB#9>; GPR64:%vreg15
	    Successors according to CFG: BB#9 BB#1

592B	BB#1: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#0
608B		%vreg22<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg22
624B		CBZX %vreg22, <BB#9>; GPR64:%vreg22
	    Successors according to CFG: BB#9 BB#2

640B	BB#2: derived from LLVM BB %lor.lhs.false.2
	    Predecessors according to CFG: BB#1
656B		%vreg24<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg24
672B		CBZX %vreg24, <BB#9>; GPR64:%vreg24
	    Successors according to CFG: BB#9 BB#3

688B	BB#3: derived from LLVM BB %lor.lhs.false.4
	    Predecessors according to CFG: BB#2
704B		%vreg26<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32common:%vreg26
720B		%WZR<def> = SUBSWri %vreg26, 1, 0, %NZCV<imp-def>; GPR32common:%vreg26
736B		Bcc 11, <BB#9>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#9 BB#4

752B	BB#4: derived from LLVM BB %lor.lhs.false.6
	    Predecessors according to CFG: BB#3
768B		%vreg28<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32common:%vreg28
784B		%WZR<def> = SUBSWri %vreg28, 9, 0, %NZCV<imp-def>; GPR32common:%vreg28
800B		Bcc 12, <BB#9>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#9 BB#5

816B	BB#5: derived from LLVM BB %lor.lhs.false.8
	    Predecessors according to CFG: BB#4
832B		%vreg30<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg30
848B		TBNZW %vreg30, 31, <BB#9>; GPR32:%vreg30
	    Successors according to CFG: BB#9 BB#6

864B	BB#6: derived from LLVM BB %lor.lhs.false.10
	    Predecessors according to CFG: BB#5
880B		%vreg32<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32common:%vreg32
896B		%WZR<def> = SUBSWri %vreg32, 4, 0, %NZCV<imp-def>; GPR32common:%vreg32
912B		Bcc 12, <BB#9>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#9 BB#7

928B	BB#7: derived from LLVM BB %lor.lhs.false.12
	    Predecessors according to CFG: BB#6
944B		%vreg34<def> = LDRWui <fi#7>, 0; mem:LD4[FixedStack7] GPR32:%vreg34
960B		TBNZW %vreg34, 31, <BB#9>; GPR32:%vreg34
	    Successors according to CFG: BB#9 BB#8

976B	BB#8: derived from LLVM BB %lor.lhs.false.14
	    Predecessors according to CFG: BB#7
992B		%vreg36<def> = LDRWui <fi#7>, 0; mem:LD4[FixedStack7] GPR32common:%vreg36
1008B		%WZR<def> = SUBSWri %vreg36, 250, 0, %NZCV<imp-def>; GPR32common:%vreg36
1024B		Bcc 13, <BB#10>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#10 BB#9

1040B	BB#9: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0 BB#1 BB#2 BB#3 BB#4 BB#5 BB#6 BB#7 BB#8
1056B		%vreg89<def> = MOVi32imm 4294967294; GPR32:%vreg89
1072B		STRWui %vreg89, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg89
1088B		B <BB#21>
	    Successors according to CFG: BB#21

1104B	BB#10: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#8
1120B		%vreg38<def> = LDRWui <fi#7>, 0; mem:LD4[FixedStack7] GPR32:%vreg38
1136B		CBNZW %vreg38, <BB#12>; GPR32:%vreg38
	    Successors according to CFG: BB#12 BB#11

1152B	BB#11: derived from LLVM BB %if.then.17
	    Predecessors according to CFG: BB#10
1168B		%vreg39<def> = MOVi32imm 30; GPR32:%vreg39
1184B		STRWui %vreg39, <fi#7>, 0; mem:ST4[FixedStack7] GPR32:%vreg39
	    Successors according to CFG: BB#12

1200B	BB#12: derived from LLVM BB %if.end.18
	    Predecessors according to CFG: BB#10 BB#11
1248B		STRXui %XZR, <fi#8>, 7; mem:ST80[FixedStack8(align=8)+7](align=1)
1264B		STRXui %XZR, <fi#8>, 8; mem:ST80[FixedStack8+8](align=8)
1280B		STRXui %XZR, <fi#8>, 9; mem:ST80[FixedStack8(align=8)+9](align=1)
1296B		%vreg50<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32:%vreg50
1312B		%vreg49<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg49
1328B		%vreg48<def> = LDRWui <fi#7>, 0; mem:LD4[FixedStack7] GPR32:%vreg48
1344B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1360B		%X0<def> = ADDXri <fi#8>, 0, 0
1376B		%W1<def> = COPY %vreg50; GPR32:%vreg50
1392B		%W2<def> = COPY %vreg49; GPR32:%vreg49
1408B		%W3<def> = COPY %vreg48; GPR32:%vreg48
1424B		BL <ga:@BZ2_bzCompressInit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %W2<imp-use>, %W3<imp-use>, %W0<imp-def>
1440B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1456B		%vreg47<def> = COPY %W0; GPR32:%vreg47
1472B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1488B		STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#9>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, 0, <fi#8>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack9](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3] LD8[FixedStack4](align=4) LD8[FixedStack8]
1504B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1520B		STRWui %vreg47, <fi#9>, 0; mem:ST4[FixedStack9] GPR32:%vreg47
1536B		%vreg41<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32:%vreg41
1552B		CBZW %vreg41, <BB#14>; GPR32:%vreg41
	    Successors according to CFG: BB#14 BB#13

1568B	BB#13: derived from LLVM BB %if.then.20
	    Predecessors according to CFG: BB#12
1584B		%vreg88<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32:%vreg88
1600B		STRWui %vreg88, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg88
1616B		B <BB#21>
	    Successors according to CFG: BB#21

1632B	BB#14: derived from LLVM BB %if.end.21
	    Predecessors according to CFG: BB#12
1680B		%vreg67<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg67
1696B		STRXui %vreg67, <fi#8>, 0; mem:ST80[FixedStack8](align=8) GPR64:%vreg67
1712B		%vreg65<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg65
1728B		STRXui %vreg65, <fi#8>, 3; mem:ST80[FixedStack8(align=8)+3](align=1) GPR64:%vreg65
1744B		%vreg63<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg63
1760B		STRWui %vreg63, <fi#8>, 2; mem:ST80[FixedStack8(align=8)+2](align=2) GPR32:%vreg63
1776B		%vreg61<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg61
1792B		%vreg60<def> = LDRWui %vreg61, 0; mem:LD4[%18] GPR32:%vreg60 GPR64common:%vreg61
1808B		STRWui %vreg60, <fi#8>, 8; mem:ST80[FixedStack8+8](align=8) GPR32:%vreg60
1824B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1840B		%X0<def> = ADDXri <fi#8>, 0, 0
1856B		%W1<def> = MOVi32imm 2
1872B		BL <ga:@BZ2_bzCompress>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %W0<imp-def>
1888B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1904B		%vreg57<def> = COPY %W0; GPR32:%vreg57
1920B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1936B		STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#9>, 0, 0, <fi#0>, 0, 0, <fi#8>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2] LD8[FixedStack9](align=4) LD8[FixedStack0](align=4) LD8[FixedStack8]
1952B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1968B		STRWui %vreg57, <fi#9>, 0; mem:ST4[FixedStack9] GPR32:%vreg57
1984B		%vreg53<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32common:%vreg53
2000B		%WZR<def> = SUBSWri %vreg53, 3, 0, %NZCV<imp-def>; GPR32common:%vreg53
2016B		Bcc 1, <BB#16>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#16 BB#15

2032B	BB#15: derived from LLVM BB %if.then.24
	    Predecessors according to CFG: BB#14
2048B		B <BB#19>
	    Successors according to CFG: BB#19

2064B	BB#16: derived from LLVM BB %if.end.25
	    Predecessors according to CFG: BB#14
2080B		%vreg69<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32common:%vreg69
2096B		%WZR<def> = SUBSWri %vreg69, 4, 0, %NZCV<imp-def>; GPR32common:%vreg69
2112B		Bcc 0, <BB#18>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#18 BB#17

2128B	BB#17: derived from LLVM BB %if.then.27
	    Predecessors according to CFG: BB#16
2144B		B <BB#20>
	    Successors according to CFG: BB#20

2160B	BB#18: derived from LLVM BB %if.end.28
	    Predecessors according to CFG: BB#16
2192B		%vreg79<def> = LDRWui <fi#8>, 8; mem:LD80[FixedStack8+8](align=8) GPR32:%vreg79
2208B		%vreg78<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg78
2224B		%vreg77<def> = LDRWui %vreg78, 0; mem:LD4[%23] GPR32:%vreg77 GPR64common:%vreg78
2240B		%vreg76<def> = SUBWrr %vreg77, %vreg79; GPR32:%vreg76,%vreg77,%vreg79
2256B		STRWui %vreg76, %vreg78, 0; mem:ST4[%23] GPR32:%vreg76 GPR64common:%vreg78
2272B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2288B		%X0<def> = ADDXri <fi#8>, 0, 0
2304B		BL <ga:@BZ2_bzCompressEnd>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
2320B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2336B		%vreg71<def,dead> = COPY %W0; GPR32all:%vreg71
2352B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2368B		STACKMAP 3, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
2384B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2400B		STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
2416B		B <BB#21>
	    Successors according to CFG: BB#21

2432B	BB#19: derived from LLVM BB %output_overflow
	    Predecessors according to CFG: BB#15
2464B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2480B		%X0<def> = ADDXri <fi#8>, 0, 0
2496B		BL <ga:@BZ2_bzCompressEnd>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
2512B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2528B		%vreg86<def,dead> = COPY %W0; GPR32all:%vreg86
2544B		%vreg84<def> = MOVi32imm 4294967288; GPR32:%vreg84
2560B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2576B		STACKMAP 4, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
2592B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2608B		STRWui %vreg84, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg84
2624B		B <BB#21>
	    Successors according to CFG: BB#21

2640B	BB#20: derived from LLVM BB %errhandler
	    Predecessors according to CFG: BB#17
2672B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2688B		%X0<def> = ADDXri <fi#8>, 0, 0
2704B		BL <ga:@BZ2_bzCompressEnd>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
2720B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2736B		%vreg83<def,dead> = COPY %W0; GPR32all:%vreg83
2752B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2768B		STACKMAP 5, 0, 0, <fi#9>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack9](align=4) LD8[FixedStack0](align=4)
2784B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2800B		%vreg81<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32:%vreg81
2816B		STRWui %vreg81, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg81
	    Successors according to CFG: BB#21

2832B	BB#21: derived from LLVM BB %return
	    Predecessors according to CFG: BB#18 BB#20 BB#19 BB#13 BB#9
2848B		%vreg92<def> = ADRP <ga:@BZ2_bzBuffToBuffCompress>[TF=1]; GPR64common:%vreg92
2864B		%vreg94<def> = ADDXri %vreg92, <ga:@BZ2_bzBuffToBuffCompress>[TF=34], 0; GPR64sp:%vreg94 GPR64common:%vreg92
2912B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2928B		%X0<def> = COPY %vreg94; GPR64sp:%vreg94
2944B		%X1<def> = COPY %vreg19; GPR64:%vreg19
2960B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
2976B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2992B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3008B		STACKMAP 6, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
3024B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3040B		%vreg91<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0] GPR32:%vreg91
3056B		%W0<def> = COPY %vreg91; GPR32:%vreg91
3072B		RET_ReallyLR %W0<imp-use>

# End machine code for function BZ2_bzBuffToBuffCompress.

handleMove 2192B -> 2216B: %vreg79<def> = LDRWui <fi#8>, 8; mem:LD80[FixedStack8+8](align=8) GPR32:%vreg79
     %vreg79:	[2192r,2240r:0)  0@2192r
        -->	[2216r,2240r:0)  0@2216r
********** GREEDY REGISTER ALLOCATION **********
********** Function: BZ2_bzBuffToBuffCompress
********** INTERVALS **********
W30 [0B,16r:0)[368r,368d:14)[416e,416d:7)[1424r,1424d:13)[1488e,1488d:6)[1872r,1872d:12)[1936e,1936d:5)[2304r,2304d:11)[2368e,2368d:4)[2496r,2496d:9)[2576e,2576d:3)[2704r,2704d:10)[2768e,2768d:2)[2960r,2960d:8)[3008e,3008d:1)  0@0B-phi 1@3008e 2@2768e 3@2576e 4@2368e 5@1936e 6@1488e 7@416e 8@2960r 9@2496r 10@2704r 11@2304r 12@1872r 13@1424r 14@368r
WZR [720r,720d:5)[784r,784d:4)[896r,896d:3)[1008r,1008d:2)[2000r,2000d:1)[2096r,2096d:0)  0@2096r 1@2000r 2@1008r 3@896r 4@784r 5@720r
W0 [0B,128r:0)[336r,368r:13)[1360r,1424r:12)[1424r,1456r:6)[1840r,1872r:11)[1872r,1904r:5)[2288r,2304r:10)[2304r,2336r:4)[2480r,2496r:8)[2496r,2528r:2)[2688r,2704r:9)[2704r,2736r:3)[2928r,2960r:7)[3056r,3072r:1)  0@0B-phi 1@3056r 2@2496r 3@2704r 4@2304r 5@1872r 6@1424r 7@2928r 8@2480r 9@2688r 10@2288r 11@1840r 12@1360r 13@336r
W1 [0B,112r:0)[352r,368r:4)[1376r,1424r:2)[1856r,1872r:1)[2944r,2960r:3)  0@0B-phi 1@1856r 2@1376r 3@2944r 4@352r
W2 [0B,96r:0)[1392r,1424r:1)  0@0B-phi 1@1392r
W3 [0B,80r:0)[1408r,1424r:1)  0@0B-phi 1@1408r
W4 [0B,64r:0)  0@0B-phi
W5 [0B,48r:0)  0@0B-phi
W6 [0B,32r:0)  0@0B-phi
%vreg1 [128r,448r:0)  0@128r
%vreg3 [112r,464r:0)  0@112r
%vreg5 [96r,480r:0)  0@96r
%vreg7 [80r,496r:0)  0@80r
%vreg9 [64r,512r:0)  0@64r
%vreg11 [48r,528r:0)  0@48r
%vreg13 [32r,544r:0)  0@32r
%vreg15 [560r,576r:0)  0@560r
%vreg16 [256r,272r:0)  0@256r
%vreg18 [272r,336r:0)  0@272r
%vreg19 [16r,2944r:0)  0@16r
%vreg22 [608r,624r:0)  0@608r
%vreg24 [656r,672r:0)  0@656r
%vreg26 [704r,720r:0)  0@704r
%vreg28 [768r,784r:0)  0@768r
%vreg30 [832r,848r:0)  0@832r
%vreg32 [880r,896r:0)  0@880r
%vreg34 [944r,960r:0)  0@944r
%vreg36 [992r,1008r:0)  0@992r
%vreg38 [1120r,1136r:0)  0@1120r
%vreg39 [1168r,1184r:0)  0@1168r
%vreg41 [1536r,1552r:0)  0@1536r
%vreg47 [1456r,1520r:0)  0@1456r
%vreg48 [1328r,1408r:0)  0@1328r
%vreg49 [1312r,1392r:0)  0@1312r
%vreg50 [1296r,1376r:0)  0@1296r
%vreg53 [1984r,2000r:0)  0@1984r
%vreg57 [1904r,1968r:0)  0@1904r
%vreg60 [1792r,1808r:0)  0@1792r
%vreg61 [1776r,1792r:0)  0@1776r
%vreg63 [1744r,1760r:0)  0@1744r
%vreg65 [1712r,1728r:0)  0@1712r
%vreg67 [1680r,1696r:0)  0@1680r
%vreg69 [2080r,2096r:0)  0@2080r
%vreg71 [2336r,2336d:0)  0@2336r
%vreg76 [2240r,2256r:0)  0@2240r
%vreg77 [2224r,2240r:0)  0@2224r
%vreg78 [2208r,2256r:0)  0@2208r
%vreg79 [2216r,2240r:0)  0@2216r
%vreg81 [2800r,2816r:0)  0@2800r
%vreg83 [2736r,2736d:0)  0@2736r
%vreg84 [2544r,2608r:0)  0@2544r
%vreg86 [2528r,2528d:0)  0@2528r
%vreg88 [1584r,1600r:0)  0@1584r
%vreg89 [1056r,1072r:0)  0@1056r
%vreg91 [3040r,3056r:0)  0@3040r
%vreg92 [2848r,2864r:0)  0@2848r
%vreg94 [2864r,2928r:0)  0@2864r
RegMasks: 368r 1424r 1872r 2304r 2496r 2704r 2960r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzBuffToBuffCompress: Post SSA
Frame Objects:
  fi#0: size=4, align=4, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=8, align=8, at location [SP]
  fi#3: size=8, align=8, at location [SP]
  fi#4: size=4, align=4, at location [SP]
  fi#5: size=4, align=4, at location [SP]
  fi#6: size=4, align=4, at location [SP]
  fi#7: size=4, align=4, at location [SP]
  fi#8: size=80, align=8, at location [SP]
  fi#9: size=4, align=4, at location [SP]
Function Live Ins: %X0 in %vreg0, %X1 in %vreg2, %X2 in %vreg4, %W3 in %vreg6, %W4 in %vreg8, %W5 in %vreg10, %W6 in %vreg12, %LR in %vreg20

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %X1 %X2 %W3 %W4 %W5 %W6 %LR
16B		%vreg19<def> = COPY %LR; GPR64:%vreg19
32B		%vreg13<def> = COPY %W6; GPR32:%vreg13
48B		%vreg11<def> = COPY %W5; GPR32:%vreg11
64B		%vreg9<def> = COPY %W4; GPR32:%vreg9
80B		%vreg7<def> = COPY %W3; GPR32:%vreg7
96B		%vreg5<def> = COPY %X2; GPR64:%vreg5
112B		%vreg3<def> = COPY %X1; GPR64:%vreg3
128B		%vreg1<def> = COPY %X0; GPR64:%vreg1
256B		%vreg16<def> = ADRP <ga:@BZ2_bzBuffToBuffCompress>[TF=1]; GPR64common:%vreg16
272B		%vreg18<def> = ADDXri %vreg16, <ga:@BZ2_bzBuffToBuffCompress>[TF=34], 0; GPR64sp:%vreg18 GPR64common:%vreg16
320B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
336B		%X0<def> = COPY %vreg18; GPR64sp:%vreg18
352B		%X1<def> = COPY %vreg19; GPR64:%vreg19
368B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
384B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
400B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
416B		STACKMAP 0, 0, %vreg9, 0, <fi#5>, 0, %vreg1, 0, <fi#1>, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#9>, 0, 0, <fi#0>, 0, %vreg5, 0, <fi#3>, 0, %vreg7, 0, <fi#4>, 0, 0, <fi#8>, 0, %vreg11, 0, <fi#6>, 0, %vreg13, 0, <fi#7>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack5](align=4) LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack9](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3] LD8[FixedStack4](align=4) LD8[FixedStack8] LD8[FixedStack6](align=4) LD8[FixedStack7](align=4) GPR32:%vreg9,%vreg7,%vreg11,%vreg13 GPR64:%vreg1,%vreg3,%vreg5
432B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
448B		STRXui %vreg1, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg1
464B		STRXui %vreg3, <fi#2>, 0; mem:ST8[FixedStack2] GPR64:%vreg3
480B		STRXui %vreg5, <fi#3>, 0; mem:ST8[FixedStack3] GPR64:%vreg5
496B		STRWui %vreg7, <fi#4>, 0; mem:ST4[FixedStack4] GPR32:%vreg7
512B		STRWui %vreg9, <fi#5>, 0; mem:ST4[FixedStack5] GPR32:%vreg9
528B		STRWui %vreg11, <fi#6>, 0; mem:ST4[FixedStack6] GPR32:%vreg11
544B		STRWui %vreg13, <fi#7>, 0; mem:ST4[FixedStack7] GPR32:%vreg13
560B		%vreg15<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg15
576B		CBZX %vreg15, <BB#9>; GPR64:%vreg15
	    Successors according to CFG: BB#9 BB#1

592B	BB#1: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#0
608B		%vreg22<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg22
624B		CBZX %vreg22, <BB#9>; GPR64:%vreg22
	    Successors according to CFG: BB#9 BB#2

640B	BB#2: derived from LLVM BB %lor.lhs.false.2
	    Predecessors according to CFG: BB#1
656B		%vreg24<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg24
672B		CBZX %vreg24, <BB#9>; GPR64:%vreg24
	    Successors according to CFG: BB#9 BB#3

688B	BB#3: derived from LLVM BB %lor.lhs.false.4
	    Predecessors according to CFG: BB#2
704B		%vreg26<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32common:%vreg26
720B		%WZR<def> = SUBSWri %vreg26, 1, 0, %NZCV<imp-def>; GPR32common:%vreg26
736B		Bcc 11, <BB#9>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#9 BB#4

752B	BB#4: derived from LLVM BB %lor.lhs.false.6
	    Predecessors according to CFG: BB#3
768B		%vreg28<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32common:%vreg28
784B		%WZR<def> = SUBSWri %vreg28, 9, 0, %NZCV<imp-def>; GPR32common:%vreg28
800B		Bcc 12, <BB#9>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#9 BB#5

816B	BB#5: derived from LLVM BB %lor.lhs.false.8
	    Predecessors according to CFG: BB#4
832B		%vreg30<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg30
848B		TBNZW %vreg30, 31, <BB#9>; GPR32:%vreg30
	    Successors according to CFG: BB#9 BB#6

864B	BB#6: derived from LLVM BB %lor.lhs.false.10
	    Predecessors according to CFG: BB#5
880B		%vreg32<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32common:%vreg32
896B		%WZR<def> = SUBSWri %vreg32, 4, 0, %NZCV<imp-def>; GPR32common:%vreg32
912B		Bcc 12, <BB#9>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#9 BB#7

928B	BB#7: derived from LLVM BB %lor.lhs.false.12
	    Predecessors according to CFG: BB#6
944B		%vreg34<def> = LDRWui <fi#7>, 0; mem:LD4[FixedStack7] GPR32:%vreg34
960B		TBNZW %vreg34, 31, <BB#9>; GPR32:%vreg34
	    Successors according to CFG: BB#9 BB#8

976B	BB#8: derived from LLVM BB %lor.lhs.false.14
	    Predecessors according to CFG: BB#7
992B		%vreg36<def> = LDRWui <fi#7>, 0; mem:LD4[FixedStack7] GPR32common:%vreg36
1008B		%WZR<def> = SUBSWri %vreg36, 250, 0, %NZCV<imp-def>; GPR32common:%vreg36
1024B		Bcc 13, <BB#10>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#10 BB#9

1040B	BB#9: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0 BB#1 BB#2 BB#3 BB#4 BB#5 BB#6 BB#7 BB#8
1056B		%vreg89<def> = MOVi32imm 4294967294; GPR32:%vreg89
1072B		STRWui %vreg89, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg89
1088B		B <BB#21>
	    Successors according to CFG: BB#21

1104B	BB#10: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#8
1120B		%vreg38<def> = LDRWui <fi#7>, 0; mem:LD4[FixedStack7] GPR32:%vreg38
1136B		CBNZW %vreg38, <BB#12>; GPR32:%vreg38
	    Successors according to CFG: BB#12 BB#11

1152B	BB#11: derived from LLVM BB %if.then.17
	    Predecessors according to CFG: BB#10
1168B		%vreg39<def> = MOVi32imm 30; GPR32:%vreg39
1184B		STRWui %vreg39, <fi#7>, 0; mem:ST4[FixedStack7] GPR32:%vreg39
	    Successors according to CFG: BB#12

1200B	BB#12: derived from LLVM BB %if.end.18
	    Predecessors according to CFG: BB#10 BB#11
1248B		STRXui %XZR, <fi#8>, 7; mem:ST80[FixedStack8(align=8)+7](align=1)
1264B		STRXui %XZR, <fi#8>, 8; mem:ST80[FixedStack8+8](align=8)
1280B		STRXui %XZR, <fi#8>, 9; mem:ST80[FixedStack8(align=8)+9](align=1)
1296B		%vreg50<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32:%vreg50
1312B		%vreg49<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg49
1328B		%vreg48<def> = LDRWui <fi#7>, 0; mem:LD4[FixedStack7] GPR32:%vreg48
1344B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1360B		%X0<def> = ADDXri <fi#8>, 0, 0
1376B		%W1<def> = COPY %vreg50; GPR32:%vreg50
1392B		%W2<def> = COPY %vreg49; GPR32:%vreg49
1408B		%W3<def> = COPY %vreg48; GPR32:%vreg48
1424B		BL <ga:@BZ2_bzCompressInit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %W2<imp-use>, %W3<imp-use>, %W0<imp-def>
1440B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1456B		%vreg47<def> = COPY %W0; GPR32:%vreg47
1472B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1488B		STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#9>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, 0, <fi#8>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack9](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3] LD8[FixedStack4](align=4) LD8[FixedStack8]
1504B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1520B		STRWui %vreg47, <fi#9>, 0; mem:ST4[FixedStack9] GPR32:%vreg47
1536B		%vreg41<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32:%vreg41
1552B		CBZW %vreg41, <BB#14>; GPR32:%vreg41
	    Successors according to CFG: BB#14 BB#13

1568B	BB#13: derived from LLVM BB %if.then.20
	    Predecessors according to CFG: BB#12
1584B		%vreg88<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32:%vreg88
1600B		STRWui %vreg88, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg88
1616B		B <BB#21>
	    Successors according to CFG: BB#21

1632B	BB#14: derived from LLVM BB %if.end.21
	    Predecessors according to CFG: BB#12
1680B		%vreg67<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg67
1696B		STRXui %vreg67, <fi#8>, 0; mem:ST80[FixedStack8](align=8) GPR64:%vreg67
1712B		%vreg65<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg65
1728B		STRXui %vreg65, <fi#8>, 3; mem:ST80[FixedStack8(align=8)+3](align=1) GPR64:%vreg65
1744B		%vreg63<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg63
1760B		STRWui %vreg63, <fi#8>, 2; mem:ST80[FixedStack8(align=8)+2](align=2) GPR32:%vreg63
1776B		%vreg61<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg61
1792B		%vreg60<def> = LDRWui %vreg61, 0; mem:LD4[%18] GPR32:%vreg60 GPR64common:%vreg61
1808B		STRWui %vreg60, <fi#8>, 8; mem:ST80[FixedStack8+8](align=8) GPR32:%vreg60
1824B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1840B		%X0<def> = ADDXri <fi#8>, 0, 0
1856B		%W1<def> = MOVi32imm 2
1872B		BL <ga:@BZ2_bzCompress>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %W0<imp-def>
1888B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1904B		%vreg57<def> = COPY %W0; GPR32:%vreg57
1920B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1936B		STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#9>, 0, 0, <fi#0>, 0, 0, <fi#8>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2] LD8[FixedStack9](align=4) LD8[FixedStack0](align=4) LD8[FixedStack8]
1952B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1968B		STRWui %vreg57, <fi#9>, 0; mem:ST4[FixedStack9] GPR32:%vreg57
1984B		%vreg53<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32common:%vreg53
2000B		%WZR<def> = SUBSWri %vreg53, 3, 0, %NZCV<imp-def>; GPR32common:%vreg53
2016B		Bcc 1, <BB#16>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#16 BB#15

2032B	BB#15: derived from LLVM BB %if.then.24
	    Predecessors according to CFG: BB#14
2048B		B <BB#19>
	    Successors according to CFG: BB#19

2064B	BB#16: derived from LLVM BB %if.end.25
	    Predecessors according to CFG: BB#14
2080B		%vreg69<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32common:%vreg69
2096B		%WZR<def> = SUBSWri %vreg69, 4, 0, %NZCV<imp-def>; GPR32common:%vreg69
2112B		Bcc 0, <BB#18>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#18 BB#17

2128B	BB#17: derived from LLVM BB %if.then.27
	    Predecessors according to CFG: BB#16
2144B		B <BB#20>
	    Successors according to CFG: BB#20

2160B	BB#18: derived from LLVM BB %if.end.28
	    Predecessors according to CFG: BB#16
2208B		%vreg78<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg78
2216B		%vreg79<def> = LDRWui <fi#8>, 8; mem:LD80[FixedStack8+8](align=8) GPR32:%vreg79
2224B		%vreg77<def> = LDRWui %vreg78, 0; mem:LD4[%23] GPR32:%vreg77 GPR64common:%vreg78
2240B		%vreg76<def> = SUBWrr %vreg77, %vreg79; GPR32:%vreg76,%vreg77,%vreg79
2256B		STRWui %vreg76, %vreg78, 0; mem:ST4[%23] GPR32:%vreg76 GPR64common:%vreg78
2272B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2288B		%X0<def> = ADDXri <fi#8>, 0, 0
2304B		BL <ga:@BZ2_bzCompressEnd>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
2320B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2336B		%vreg71<def,dead> = COPY %W0; GPR32all:%vreg71
2352B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2368B		STACKMAP 3, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
2384B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2400B		STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
2416B		B <BB#21>
	    Successors according to CFG: BB#21

2432B	BB#19: derived from LLVM BB %output_overflow
	    Predecessors according to CFG: BB#15
2464B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2480B		%X0<def> = ADDXri <fi#8>, 0, 0
2496B		BL <ga:@BZ2_bzCompressEnd>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
2512B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2528B		%vreg86<def,dead> = COPY %W0; GPR32all:%vreg86
2544B		%vreg84<def> = MOVi32imm 4294967288; GPR32:%vreg84
2560B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2576B		STACKMAP 4, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
2592B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2608B		STRWui %vreg84, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg84
2624B		B <BB#21>
	    Successors according to CFG: BB#21

2640B	BB#20: derived from LLVM BB %errhandler
	    Predecessors according to CFG: BB#17
2672B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2688B		%X0<def> = ADDXri <fi#8>, 0, 0
2704B		BL <ga:@BZ2_bzCompressEnd>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
2720B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2736B		%vreg83<def,dead> = COPY %W0; GPR32all:%vreg83
2752B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2768B		STACKMAP 5, 0, 0, <fi#9>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack9](align=4) LD8[FixedStack0](align=4)
2784B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2800B		%vreg81<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32:%vreg81
2816B		STRWui %vreg81, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg81
	    Successors according to CFG: BB#21

2832B	BB#21: derived from LLVM BB %return
	    Predecessors according to CFG: BB#18 BB#20 BB#19 BB#13 BB#9
2848B		%vreg92<def> = ADRP <ga:@BZ2_bzBuffToBuffCompress>[TF=1]; GPR64common:%vreg92
2864B		%vreg94<def> = ADDXri %vreg92, <ga:@BZ2_bzBuffToBuffCompress>[TF=34], 0; GPR64sp:%vreg94 GPR64common:%vreg92
2912B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2928B		%X0<def> = COPY %vreg94; GPR64sp:%vreg94
2944B		%X1<def> = COPY %vreg19; GPR64:%vreg19
2960B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
2976B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2992B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3008B		STACKMAP 6, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
3024B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3040B		%vreg91<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0] GPR32:%vreg91
3056B		%W0<def> = COPY %vreg91; GPR32:%vreg91
3072B		RET_ReallyLR %W0<imp-use>

# End machine code for function BZ2_bzBuffToBuffCompress.


selectOrSplit GPR64:%vreg19 [16r,2944r:0)  0@16r w=9.104567e-04
hints: %X1
missed hint %X1
Analyze counted 3 instrs in 2 blocks, through 20 blocks.
%X1	static = 1.0 worse than no bundles
%X8	static = 1.0 worse than no bundles
%X9	static = 1.0 worse than no bundles
%X10	static = 1.0 worse than no bundles
%X11	static = 1.0 worse than no bundles
%X12	static = 1.0 worse than no bundles
%X13	static = 1.0 worse than no bundles
%X14	static = 1.0 worse than no bundles
%X15	static = 1.0 worse than no bundles
%X16	static = 1.0 worse than no bundles
%X17	static = 1.0 worse than no bundles
%X18	static = 1.0 worse than no bundles
%X0	no positive bundles
%X2	static = 1.0 worse than no bundles
%X3	static = 1.0 worse than no bundles
%X4	static = 1.0 worse than no bundles
%X5	static = 1.0 worse than no bundles
%X6	static = 1.0 worse than no bundles
%X7	static = 1.0 worse than no bundles
assigning %vreg19 to %X19: W19 [16r,2944r:0)  0@16r

selectOrSplit GPR32:%vreg13 [32r,544r:0)  0@32r w=3.322368e-03
hints: %W6
missed hint %W6
Analyze counted 3 instrs in 1 blocks, through 0 blocks.
%W6	no positive bundles
%W8	no positive bundles
%W9	no positive bundles
%W10	no positive bundles
%W11	no positive bundles
%W12	no positive bundles
%W13	no positive bundles
%W14	no positive bundles
%W15	no positive bundles
%W16	no positive bundles
%W17	no positive bundles
%W18	no positive bundles
%W0	no positive bundles
%W1	no positive bundles
%W2	no positive bundles
%W3	no positive bundles
%W4	no positive bundles
%W5	no positive bundles
%W7	no positive bundles
%W19	no positive bundles
assigning %vreg13 to %W20: W20 [32r,544r:0)  0@32r

selectOrSplit GPR32:%vreg11 [48r,528r:0)  0@48r w=3.443182e-03
hints: %W5
missed hint %W5
Analyze counted 3 instrs in 1 blocks, through 0 blocks.
%W5	no positive bundles
%W8	no positive bundles
%W9	no positive bundles
%W10	no positive bundles
%W11	no positive bundles
%W12	no positive bundles
%W13	no positive bundles
%W14	no positive bundles
%W15	no positive bundles
%W16	no positive bundles
%W17	no positive bundles
%W18	no positive bundles
%W0	no positive bundles
%W1	no positive bundles
%W2	no positive bundles
%W3	no positive bundles
%W4	no positive bundles
%W6	no positive bundles
%W7	no positive bundles
%W19	no positive bundles
%W20	no positive bundles
assigning %vreg11 to %W21: W21 [48r,528r:0)  0@48r

selectOrSplit GPR32:%vreg9 [64r,512r:0)  0@64r w=3.573113e-03
hints: %W4
missed hint %W4
Analyze counted 3 instrs in 1 blocks, through 0 blocks.
%W4	no positive bundles
%W8	no positive bundles
%W9	no positive bundles
%W10	no positive bundles
%W11	no positive bundles
%W12	no positive bundles
%W13	no positive bundles
%W14	no positive bundles
%W15	no positive bundles
%W16	no positive bundles
%W17	no positive bundles
%W18	no positive bundles
%W0	no positive bundles
%W1	no positive bundles
%W2	no positive bundles
%W3	no positive bundles
%W5	no positive bundles
%W6	no positive bundles
%W7	no positive bundles
%W19	no positive bundles
%W20	no positive bundles
%W21	no positive bundles
assigning %vreg9 to %W22: W22 [64r,512r:0)  0@64r

selectOrSplit GPR32:%vreg7 [80r,496r:0)  0@80r w=3.713235e-03
hints: %W3
missed hint %W3
Analyze counted 3 instrs in 1 blocks, through 0 blocks.
%W3	no positive bundles
%W8	no positive bundles
%W9	no positive bundles
%W10	no positive bundles
%W11	no positive bundles
%W12	no positive bundles
%W13	no positive bundles
%W14	no positive bundles
%W15	no positive bundles
%W16	no positive bundles
%W17	no positive bundles
%W18	no positive bundles
%W0	no positive bundles
%W1	no positive bundles
%W2	no positive bundles
%W4	no positive bundles
%W5	no positive bundles
%W6	no positive bundles
%W7	no positive bundles
%W19	no positive bundles
%W20	no positive bundles
%W21	no positive bundles
%W22	no positive bundles
assigning %vreg7 to %W23: W23 [80r,496r:0)  0@80r

selectOrSplit GPR64:%vreg5 [96r,480r:0)  0@96r w=3.864796e-03
hints: %X2
missed hint %X2
Analyze counted 3 instrs in 1 blocks, through 0 blocks.
%X2	no positive bundles
%X8	no positive bundles
%X9	no positive bundles
%X10	no positive bundles
%X11	no positive bundles
%X12	no positive bundles
%X13	no positive bundles
%X14	no positive bundles
%X15	no positive bundles
%X16	no positive bundles
%X17	no positive bundles
%X18	no positive bundles
%X0	no positive bundles
%X1	no positive bundles
%X3	no positive bundles
%X4	no positive bundles
%X5	no positive bundles
%X6	no positive bundles
%X7	no positive bundles
%X19	no positive bundles
%X20	no positive bundles
%X21	no positive bundles
%X22	no positive bundles
%X23	no positive bundles
assigning %vreg5 to %X24: W24 [96r,480r:0)  0@96r

selectOrSplit GPR64:%vreg3 [112r,464r:0)  0@112r w=4.029255e-03
hints: %X1
missed hint %X1
Analyze counted 3 instrs in 1 blocks, through 0 blocks.
%X1	no positive bundles
%X8	no positive bundles
%X9	no positive bundles
%X10	no positive bundles
%X11	no positive bundles
%X12	no positive bundles
%X13	no positive bundles
%X14	no positive bundles
%X15	no positive bundles
%X16	no positive bundles
%X17	no positive bundles
%X18	no positive bundles
%X0	no positive bundles
%X2	no positive bundles
%X3	no positive bundles
%X4	no positive bundles
%X5	no positive bundles
%X6	no positive bundles
%X7	no positive bundles
%X19	no positive bundles
%X20	no positive bundles
%X21	no positive bundles
%X22	no positive bundles
%X23	no positive bundles
%X24	no positive bundles
assigning %vreg3 to %X25: W25 [112r,464r:0)  0@112r

selectOrSplit GPR64:%vreg1 [128r,448r:0)  0@128r w=4.208333e-03
hints: %X0
missed hint %X0
Analyze counted 3 instrs in 1 blocks, through 0 blocks.
%X0	no positive bundles
%X8	no positive bundles
%X9	no positive bundles
%X10	no positive bundles
%X11	no positive bundles
%X12	no positive bundles
%X13	no positive bundles
%X14	no positive bundles
%X15	no positive bundles
%X16	no positive bundles
%X17	no positive bundles
%X18	no positive bundles
%X1	no positive bundles
%X2	no positive bundles
%X3	no positive bundles
%X4	no positive bundles
%X5	no positive bundles
%X6	no positive bundles
%X7	no positive bundles
%X19	no positive bundles
%X20	no positive bundles
%X21	no positive bundles
%X22	no positive bundles
%X23	no positive bundles
%X24	no positive bundles
%X25	no positive bundles
assigning %vreg1 to %X26: W26 [128r,448r:0)  0@128r

selectOrSplit GPR64sp:%vreg18 [272r,336r:0)  0@272r w=4.353448e-03
hints: %X0
assigning %vreg18 to %X0: W0 [272r,336r:0)  0@272r

selectOrSplit GPR32:%vreg50 [1296r,1376r:0)  0@1296r w=8.091220e-06
hints: %W1
assigning %vreg50 to %W1: W1 [1296r,1376r:0)  0@1296r

selectOrSplit GPR32:%vreg49 [1312r,1392r:0)  0@1312r w=8.091220e-06
hints: %W2
assigning %vreg49 to %W2: W2 [1312r,1392r:0)  0@1312r

selectOrSplit GPR32:%vreg48 [1328r,1408r:0)  0@1328r w=8.091220e-06
hints: %W3
assigning %vreg48 to %W3: W3 [1328r,1408r:0)  0@1328r

selectOrSplit GPR32:%vreg47 [1456r,1520r:0)  0@1456r w=8.370227e-06
hints: %W0
assigning %vreg47 to %W0: W0 [1456r,1520r:0)  0@1456r

selectOrSplit GPR32:%vreg57 [1904r,1968r:0)  0@1904r w=4.118683e-06
hints: %W0
assigning %vreg57 to %W0: W0 [1904r,1968r:0)  0@1904r

selectOrSplit GPR32all:%vreg71 [2336r,2336d:0)  0@2336r w=inf
hints: %W0
assigning %vreg71 to %W0: W0 [2336r,2336d:0)  0@2336r

selectOrSplit GPR32all:%vreg86 [2528r,2528d:0)  0@2528r w=inf
hints: %W0
assigning %vreg86 to %W0: W0 [2528r,2528d:0)  0@2528r

selectOrSplit GPR32all:%vreg83 [2736r,2736d:0)  0@2736r w=inf
hints: %W0
assigning %vreg83 to %W0: W0 [2736r,2736d:0)  0@2736r

selectOrSplit GPR64sp:%vreg94 [2864r,2928r:0)  0@2864r w=4.353448e-03
hints: %X0
assigning %vreg94 to %X0: W0 [2864r,2928r:0)  0@2864r

selectOrSplit GPR32:%vreg91 [3040r,3056r:0)  0@3040r w=inf
hints: %W0
assigning %vreg91 to %W0: W0 [3040r,3056r:0)  0@3040r

selectOrSplit GPR64common:%vreg16 [256r,272r:0)  0@256r w=inf
assigning %vreg16 to %X8: W8 [256r,272r:0)  0@256r

selectOrSplit GPR64:%vreg15 [560r,576r:0)  0@560r w=inf
assigning %vreg15 to %X8: W8 [560r,576r:0)  0@560r

selectOrSplit GPR64:%vreg22 [608r,624r:0)  0@608r w=inf
assigning %vreg22 to %X8: W8 [608r,624r:0)  0@608r

selectOrSplit GPR64:%vreg24 [656r,672r:0)  0@656r w=inf
assigning %vreg24 to %X8: W8 [656r,672r:0)  0@656r

selectOrSplit GPR32common:%vreg26 [704r,720r:0)  0@704r w=inf
assigning %vreg26 to %W8: W8 [704r,720r:0)  0@704r

selectOrSplit GPR32common:%vreg28 [768r,784r:0)  0@768r w=inf
assigning %vreg28 to %W8: W8 [768r,784r:0)  0@768r

selectOrSplit GPR32:%vreg30 [832r,848r:0)  0@832r w=inf
assigning %vreg30 to %W8: W8 [832r,848r:0)  0@832r

selectOrSplit GPR32common:%vreg32 [880r,896r:0)  0@880r w=inf
assigning %vreg32 to %W8: W8 [880r,896r:0)  0@880r

selectOrSplit GPR32:%vreg34 [944r,960r:0)  0@944r w=inf
assigning %vreg34 to %W8: W8 [944r,960r:0)  0@944r

selectOrSplit GPR32common:%vreg36 [992r,1008r:0)  0@992r w=inf
assigning %vreg36 to %W8: W8 [992r,1008r:0)  0@992r

selectOrSplit GPR32:%vreg89 [1056r,1072r:0)  0@1056r w=inf
assigning %vreg89 to %W8: W8 [1056r,1072r:0)  0@1056r

selectOrSplit GPR32:%vreg38 [1120r,1136r:0)  0@1120r w=inf
assigning %vreg38 to %W8: W8 [1120r,1136r:0)  0@1120r

selectOrSplit GPR32:%vreg39 [1168r,1184r:0)  0@1168r w=inf
assigning %vreg39 to %W8: W8 [1168r,1184r:0)  0@1168r

selectOrSplit GPR32:%vreg41 [1536r,1552r:0)  0@1536r w=inf
assigning %vreg41 to %W8: W8 [1536r,1552r:0)  0@1536r

selectOrSplit GPR32:%vreg88 [1584r,1600r:0)  0@1584r w=inf
assigning %vreg88 to %W8: W8 [1584r,1600r:0)  0@1584r

selectOrSplit GPR64:%vreg67 [1680r,1696r:0)  0@1680r w=inf
assigning %vreg67 to %X8: W8 [1680r,1696r:0)  0@1680r

selectOrSplit GPR64:%vreg65 [1712r,1728r:0)  0@1712r w=inf
assigning %vreg65 to %X8: W8 [1712r,1728r:0)  0@1712r

selectOrSplit GPR32:%vreg63 [1744r,1760r:0)  0@1744r w=inf
assigning %vreg63 to %W8: W8 [1744r,1760r:0)  0@1744r

selectOrSplit GPR64common:%vreg61 [1776r,1792r:0)  0@1776r w=inf
assigning %vreg61 to %X8: W8 [1776r,1792r:0)  0@1776r

selectOrSplit GPR32:%vreg60 [1792r,1808r:0)  0@1792r w=inf
assigning %vreg60 to %W8: W8 [1792r,1808r:0)  0@1792r

selectOrSplit GPR32common:%vreg53 [1984r,2000r:0)  0@1984r w=inf
assigning %vreg53 to %W8: W8 [1984r,2000r:0)  0@1984r

selectOrSplit GPR32common:%vreg69 [2080r,2096r:0)  0@2080r w=inf
assigning %vreg69 to %W8: W8 [2080r,2096r:0)  0@2080r

selectOrSplit GPR64common:%vreg78 [2208r,2256r:0)  0@2208r w=1.634920e-06
assigning %vreg78 to %X8: W8 [2208r,2256r:0)  0@2208r

selectOrSplit GPR32:%vreg79 [2216r,2240r:0)  0@2216r w=1.151642e-06
assigning %vreg79 to %W9: W9 [2216r,2240r:0)  0@2216r

selectOrSplit GPR32:%vreg77 [2224r,2240r:0)  0@2224r w=inf
assigning %vreg77 to %W10: W10 [2224r,2240r:0)  0@2224r

selectOrSplit GPR32:%vreg76 [2240r,2256r:0)  0@2240r w=inf
assigning %vreg76 to %W9: W9 [2240r,2256r:0)  0@2240r

selectOrSplit GPR32:%vreg84 [2544r,2608r:0)  0@2544r w=9.865897e-07
assigning %vreg84 to %W8: W8 [2544r,2608r:0)  0@2544r

selectOrSplit GPR32:%vreg81 [2800r,2816r:0)  0@2800r w=inf
assigning %vreg81 to %W8: W8 [2800r,2816r:0)  0@2800r

selectOrSplit GPR64common:%vreg92 [2848r,2864r:0)  0@2848r w=inf
assigning %vreg92 to %X8: W8 [2848r,2864r:0)  0@2848r

********** STACK TRANSFORMATION METADATA **********
********** Function: BZ2_bzBuffToBuffCompress
********** REGISTER MAP **********
[%vreg1 -> %X26] GPR64
[%vreg3 -> %X25] GPR64
[%vreg5 -> %X24] GPR64
[%vreg7 -> %W23] GPR32
[%vreg9 -> %W22] GPR32
[%vreg11 -> %W21] GPR32
[%vreg13 -> %W20] GPR32
[%vreg15 -> %X8] GPR64
[%vreg16 -> %X8] GPR64common
[%vreg18 -> %X0] GPR64sp
[%vreg19 -> %X19] GPR64
[%vreg22 -> %X8] GPR64
[%vreg24 -> %X8] GPR64
[%vreg26 -> %W8] GPR32common
[%vreg28 -> %W8] GPR32common
[%vreg30 -> %W8] GPR32
[%vreg32 -> %W8] GPR32common
[%vreg34 -> %W8] GPR32
[%vreg36 -> %W8] GPR32common
[%vreg38 -> %W8] GPR32
[%vreg39 -> %W8] GPR32
[%vreg41 -> %W8] GPR32
[%vreg47 -> %W0] GPR32
[%vreg48 -> %W3] GPR32
[%vreg49 -> %W2] GPR32
[%vreg50 -> %W1] GPR32
[%vreg53 -> %W8] GPR32common
[%vreg57 -> %W0] GPR32
[%vreg60 -> %W8] GPR32
[%vreg61 -> %X8] GPR64common
[%vreg63 -> %W8] GPR32
[%vreg65 -> %X8] GPR64
[%vreg67 -> %X8] GPR64
[%vreg69 -> %W8] GPR32common
[%vreg71 -> %W0] GPR32all
[%vreg76 -> %W9] GPR32
[%vreg77 -> %W10] GPR32
[%vreg78 -> %X8] GPR64common
[%vreg79 -> %W9] GPR32
[%vreg81 -> %W8] GPR32
[%vreg83 -> %W0] GPR32all
[%vreg84 -> %W8] GPR32
[%vreg86 -> %W0] GPR32all
[%vreg88 -> %W8] GPR32
[%vreg89 -> %W8] GPR32
[%vreg91 -> %W0] GPR32
[%vreg92 -> %X8] GPR64common
[%vreg94 -> %X0] GPR64sp


Stackmap 0:
  STACKMAP 0, 0, %vreg9, 0, <fi#5>, 0, %vreg1, 0, <fi#1>, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#9>, 0, 0, <fi#0>, 0, %vreg5, 0, <fi#3>, 0, %vreg7, 0, <fi#4>, 0, 0, <fi#8>, 0, %vreg11, 0, <fi#6>, 0, %vreg13, 0, <fi#7>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack5](align=4) LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack9](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3] LD8[FixedStack4](align=4) LD8[FixedStack8] LD8[FixedStack6](align=4) LD8[FixedStack7](align=4) GPR32:%vreg9,%vreg7,%vreg11,%vreg13 GPR64:%vreg1,%vreg3,%vreg5

i32 %blockSize100k: in register %W22 (vreg 9)
i32* %blockSize100k.addr: in stack slot 5 (size: 4)
i8* %dest: in register %X26 (vreg 1)
i8** %dest.addr: in stack slot 1 (size: 8)
i32* %destLen: in register %X25 (vreg 3)
i32** %destLen.addr: in stack slot 2 (size: 8)
i32* %ret: in stack slot 9 (size: 4)
i32* %retval: in stack slot 0 (size: 4)
i8* %source: in register %X24 (vreg 5)
i8** %source.addr: in stack slot 3 (size: 8)
i32 %sourceLen: in register %W23 (vreg 7)
i32* %sourceLen.addr: in stack slot 4 (size: 4)
%struct.bz_stream* %strm: in stack slot 8 (size: 80)
i32 %verbosity: in register %W21 (vreg 11)
i32* %verbosity.addr: in stack slot 6 (size: 4)
i32 %workFactor: in register %W20 (vreg 13)
i32* %workFactor.addr: in stack slot 7 (size: 4)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#9>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, 0, <fi#8>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack9](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3] LD8[FixedStack4](align=4) LD8[FixedStack8]

i8** %dest.addr: in stack slot 1 (size: 8)
i32** %destLen.addr: in stack slot 2 (size: 8)
i32* %ret: in stack slot 9 (size: 4)
i32* %retval: in stack slot 0 (size: 4)
i8** %source.addr: in stack slot 3 (size: 8)
i32* %sourceLen.addr: in stack slot 4 (size: 4)
%struct.bz_stream* %strm: in stack slot 8 (size: 80)

Duplicate operand locations:


Stackmap 2:
  STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#9>, 0, 0, <fi#0>, 0, 0, <fi#8>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2] LD8[FixedStack9](align=4) LD8[FixedStack0](align=4) LD8[FixedStack8]

i32** %destLen.addr: in stack slot 2 (size: 8)
i32* %ret: in stack slot 9 (size: 4)
i32* %retval: in stack slot 0 (size: 4)
%struct.bz_stream* %strm: in stack slot 8 (size: 80)

Duplicate operand locations:


Stackmap 3:
  STACKMAP 3, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)

i32* %retval: in stack slot 0 (size: 4)

Duplicate operand locations:


Stackmap 4:
  STACKMAP 4, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)

i32* %retval: in stack slot 0 (size: 4)

Duplicate operand locations:


Stackmap 5:
  STACKMAP 5, 0, 0, <fi#9>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack9](align=4) LD8[FixedStack0](align=4)

i32* %ret: in stack slot 9 (size: 4)
i32* %retval: in stack slot 0 (size: 4)

Duplicate operand locations:


Stackmap 6:
  STACKMAP 6, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)

i32* %retval: in stack slot 0 (size: 4)

Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, %vreg9, 0, <fi#5>, 0, %vreg1, 0, <fi#1>, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#9>, 0, 0, <fi#0>, 0, %vreg5, 0, <fi#3>, 0, %vreg7, 0, <fi#4>, 0, 0, <fi#8>, 0, %vreg11, 0, <fi#6>, 0, %vreg13, 0, <fi#7>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack5](align=4) LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack9](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3] LD8[FixedStack4](align=4) LD8[FixedStack8] LD8[FixedStack6](align=4) LD8[FixedStack7](align=4) GPR32:%vreg9,%vreg7,%vreg11,%vreg13 GPR64:%vreg1,%vreg3,%vreg5
  -> Call instruction SlotIndex 368B, searching vregs 0 -> 96 and stack slots 0 -> 10
    + vreg19 is live in register but not in stackmap
      Defining instruction: %vreg19<def> = COPY %LR; GPR64:%vreg19
      Value: generated value, 1 instruction(s)

  STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#9>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, 0, <fi#8>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack9](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3] LD8[FixedStack4](align=4) LD8[FixedStack8]
  -> Call instruction SlotIndex 1424B, searching vregs 0 -> 96 and stack slots 0 -> 10
    + vreg19 is live in register but not in stackmap
      Defining instruction: %vreg19<def> = COPY %LR; GPR64:%vreg19
      Value: generated value, 1 instruction(s)

  STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#9>, 0, 0, <fi#0>, 0, 0, <fi#8>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2] LD8[FixedStack9](align=4) LD8[FixedStack0](align=4) LD8[FixedStack8]
  -> Call instruction SlotIndex 1872B, searching vregs 0 -> 96 and stack slots 0 -> 10
    + vreg19 is live in register but not in stackmap
      Defining instruction: %vreg19<def> = COPY %LR; GPR64:%vreg19
      Value: generated value, 1 instruction(s)

  STACKMAP 3, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
  -> Call instruction SlotIndex 2304B, searching vregs 0 -> 96 and stack slots 0 -> 10
    + vreg19 is live in register but not in stackmap
      Defining instruction: %vreg19<def> = COPY %LR; GPR64:%vreg19
      Value: generated value, 1 instruction(s)

  STACKMAP 4, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
  -> Call instruction SlotIndex 2496B, searching vregs 0 -> 96 and stack slots 0 -> 10
    + vreg19 is live in register but not in stackmap
      Defining instruction: %vreg19<def> = COPY %LR; GPR64:%vreg19
      Value: generated value, 1 instruction(s)

  STACKMAP 5, 0, 0, <fi#9>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack9](align=4) LD8[FixedStack0](align=4)
  -> Call instruction SlotIndex 2704B, searching vregs 0 -> 96 and stack slots 0 -> 10
    + vreg19 is live in register but not in stackmap
      Defining instruction: %vreg19<def> = COPY %LR; GPR64:%vreg19
      Value: generated value, 1 instruction(s)

  STACKMAP 6, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
  -> Call instruction SlotIndex 2960B, searching vregs 0 -> 96 and stack slots 0 -> 10

********** REWRITE VIRTUAL REGISTERS **********
********** Function: BZ2_bzBuffToBuffCompress
********** REGISTER MAP **********
[%vreg1 -> %X26] GPR64
[%vreg3 -> %X25] GPR64
[%vreg5 -> %X24] GPR64
[%vreg7 -> %W23] GPR32
[%vreg9 -> %W22] GPR32
[%vreg11 -> %W21] GPR32
[%vreg13 -> %W20] GPR32
[%vreg15 -> %X8] GPR64
[%vreg16 -> %X8] GPR64common
[%vreg18 -> %X0] GPR64sp
[%vreg19 -> %X19] GPR64
[%vreg22 -> %X8] GPR64
[%vreg24 -> %X8] GPR64
[%vreg26 -> %W8] GPR32common
[%vreg28 -> %W8] GPR32common
[%vreg30 -> %W8] GPR32
[%vreg32 -> %W8] GPR32common
[%vreg34 -> %W8] GPR32
[%vreg36 -> %W8] GPR32common
[%vreg38 -> %W8] GPR32
[%vreg39 -> %W8] GPR32
[%vreg41 -> %W8] GPR32
[%vreg47 -> %W0] GPR32
[%vreg48 -> %W3] GPR32
[%vreg49 -> %W2] GPR32
[%vreg50 -> %W1] GPR32
[%vreg53 -> %W8] GPR32common
[%vreg57 -> %W0] GPR32
[%vreg60 -> %W8] GPR32
[%vreg61 -> %X8] GPR64common
[%vreg63 -> %W8] GPR32
[%vreg65 -> %X8] GPR64
[%vreg67 -> %X8] GPR64
[%vreg69 -> %W8] GPR32common
[%vreg71 -> %W0] GPR32all
[%vreg76 -> %W9] GPR32
[%vreg77 -> %W10] GPR32
[%vreg78 -> %X8] GPR64common
[%vreg79 -> %W9] GPR32
[%vreg81 -> %W8] GPR32
[%vreg83 -> %W0] GPR32all
[%vreg84 -> %W8] GPR32
[%vreg86 -> %W0] GPR32all
[%vreg88 -> %W8] GPR32
[%vreg89 -> %W8] GPR32
[%vreg91 -> %W0] GPR32
[%vreg92 -> %X8] GPR64common
[%vreg94 -> %X0] GPR64sp

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %LR %W3 %W4 %W5 %W6 %X0 %X1 %X2
16B		%vreg19<def> = COPY %LR; GPR64:%vreg19
32B		%vreg13<def> = COPY %W6; GPR32:%vreg13
48B		%vreg11<def> = COPY %W5; GPR32:%vreg11
64B		%vreg9<def> = COPY %W4; GPR32:%vreg9
80B		%vreg7<def> = COPY %W3; GPR32:%vreg7
96B		%vreg5<def> = COPY %X2; GPR64:%vreg5
112B		%vreg3<def> = COPY %X1; GPR64:%vreg3
128B		%vreg1<def> = COPY %X0; GPR64:%vreg1
256B		%vreg16<def> = ADRP <ga:@BZ2_bzBuffToBuffCompress>[TF=1]; GPR64common:%vreg16
272B		%vreg18<def> = ADDXri %vreg16<kill>, <ga:@BZ2_bzBuffToBuffCompress>[TF=34], 0; GPR64sp:%vreg18 GPR64common:%vreg16
320B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
336B		%X0<def> = COPY %vreg18<kill>; GPR64sp:%vreg18
352B		%X1<def> = COPY %vreg19; GPR64:%vreg19
368B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
384B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
400B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
416B		STACKMAP 0, 0, %vreg9, 0, <fi#5>, 0, %vreg1, 0, <fi#1>, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#9>, 0, 0, <fi#0>, 0, %vreg5, 0, <fi#3>, 0, %vreg7, 0, <fi#4>, 0, 0, <fi#8>, 0, %vreg11, 0, <fi#6>, 0, %vreg13, 0, <fi#7>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack5](align=4) LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack9](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3] LD8[FixedStack4](align=4) LD8[FixedStack8] LD8[FixedStack6](align=4) LD8[FixedStack7](align=4) GPR32:%vreg9,%vreg7,%vreg11,%vreg13 GPR64:%vreg1,%vreg3,%vreg5
432B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
448B		STRXui %vreg1<kill>, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg1
464B		STRXui %vreg3<kill>, <fi#2>, 0; mem:ST8[FixedStack2] GPR64:%vreg3
480B		STRXui %vreg5<kill>, <fi#3>, 0; mem:ST8[FixedStack3] GPR64:%vreg5
496B		STRWui %vreg7<kill>, <fi#4>, 0; mem:ST4[FixedStack4] GPR32:%vreg7
512B		STRWui %vreg9<kill>, <fi#5>, 0; mem:ST4[FixedStack5] GPR32:%vreg9
528B		STRWui %vreg11<kill>, <fi#6>, 0; mem:ST4[FixedStack6] GPR32:%vreg11
544B		STRWui %vreg13<kill>, <fi#7>, 0; mem:ST4[FixedStack7] GPR32:%vreg13
560B		%vreg15<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg15
576B		CBZX %vreg15<kill>, <BB#9>; GPR64:%vreg15
	    Successors according to CFG: BB#9 BB#1
> %X19<def> = COPY %LR
> %W20<def> = COPY %W6
> %W21<def> = COPY %W5
> %W22<def> = COPY %W4
> %W23<def> = COPY %W3
> %X24<def> = COPY %X2
> %X25<def> = COPY %X1
> %X26<def> = COPY %X0
> %X8<def> = ADRP <ga:@BZ2_bzBuffToBuffCompress>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@BZ2_bzBuffToBuffCompress>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19
> BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 0, 0, %W22, 0, <fi#5>, 0, %X26, 0, <fi#1>, 0, %X25, 0, <fi#2>, 0, 0, <fi#9>, 0, 0, <fi#0>, 0, %X24, 0, <fi#3>, 0, %W23, 0, <fi#4>, 0, 0, <fi#8>, 0, %W21, 0, <fi#6>, 0, %W20, 0, <fi#7>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack5](align=4) LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack9](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3] LD8[FixedStack4](align=4) LD8[FixedStack8] LD8[FixedStack6](align=4) LD8[FixedStack7](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRXui %X26<kill>, <fi#1>, 0; mem:ST8[FixedStack1]
> STRXui %X25<kill>, <fi#2>, 0; mem:ST8[FixedStack2]
> STRXui %X24<kill>, <fi#3>, 0; mem:ST8[FixedStack3]
> STRWui %W23<kill>, <fi#4>, 0; mem:ST4[FixedStack4]
> STRWui %W22<kill>, <fi#5>, 0; mem:ST4[FixedStack5]
> STRWui %W21<kill>, <fi#6>, 0; mem:ST4[FixedStack6]
> STRWui %W20<kill>, <fi#7>, 0; mem:ST4[FixedStack7]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> CBZX %X8<kill>, <BB#9>
592B	BB#1: derived from LLVM BB %lor.lhs.false
	    Live Ins: %X19
	    Predecessors according to CFG: BB#0
608B		%vreg22<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg22
624B		CBZX %vreg22<kill>, <BB#9>; GPR64:%vreg22
	    Successors according to CFG: BB#9 BB#2
> %X8<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2]
> CBZX %X8<kill>, <BB#9>
640B	BB#2: derived from LLVM BB %lor.lhs.false.2
	    Live Ins: %X19
	    Predecessors according to CFG: BB#1
656B		%vreg24<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg24
672B		CBZX %vreg24<kill>, <BB#9>; GPR64:%vreg24
	    Successors according to CFG: BB#9 BB#3
> %X8<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> CBZX %X8<kill>, <BB#9>
688B	BB#3: derived from LLVM BB %lor.lhs.false.4
	    Live Ins: %X19
	    Predecessors according to CFG: BB#2
704B		%vreg26<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32common:%vreg26
720B		%WZR<def> = SUBSWri %vreg26<kill>, 1, 0, %NZCV<imp-def>; GPR32common:%vreg26
736B		Bcc 11, <BB#9>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#9 BB#4
> %W8<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5]
> %WZR<def> = SUBSWri %W8<kill>, 1, 0, %NZCV<imp-def>
> Bcc 11, <BB#9>, %NZCV<imp-use,kill>
752B	BB#4: derived from LLVM BB %lor.lhs.false.6
	    Live Ins: %X19
	    Predecessors according to CFG: BB#3
768B		%vreg28<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32common:%vreg28
784B		%WZR<def> = SUBSWri %vreg28<kill>, 9, 0, %NZCV<imp-def>; GPR32common:%vreg28
800B		Bcc 12, <BB#9>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#9 BB#5
> %W8<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5]
> %WZR<def> = SUBSWri %W8<kill>, 9, 0, %NZCV<imp-def>
> Bcc 12, <BB#9>, %NZCV<imp-use,kill>
816B	BB#5: derived from LLVM BB %lor.lhs.false.8
	    Live Ins: %X19
	    Predecessors according to CFG: BB#4
832B		%vreg30<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg30
848B		TBNZW %vreg30<kill>, 31, <BB#9>; GPR32:%vreg30
	    Successors according to CFG: BB#9 BB#6
> %W8<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6]
> TBNZW %W8<kill>, 31, <BB#9>
864B	BB#6: derived from LLVM BB %lor.lhs.false.10
	    Live Ins: %X19
	    Predecessors according to CFG: BB#5
880B		%vreg32<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32common:%vreg32
896B		%WZR<def> = SUBSWri %vreg32<kill>, 4, 0, %NZCV<imp-def>; GPR32common:%vreg32
912B		Bcc 12, <BB#9>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#9 BB#7
> %W8<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6]
> %WZR<def> = SUBSWri %W8<kill>, 4, 0, %NZCV<imp-def>
> Bcc 12, <BB#9>, %NZCV<imp-use,kill>
928B	BB#7: derived from LLVM BB %lor.lhs.false.12
	    Live Ins: %X19
	    Predecessors according to CFG: BB#6
944B		%vreg34<def> = LDRWui <fi#7>, 0; mem:LD4[FixedStack7] GPR32:%vreg34
960B		TBNZW %vreg34<kill>, 31, <BB#9>; GPR32:%vreg34
	    Successors according to CFG: BB#9 BB#8
> %W8<def> = LDRWui <fi#7>, 0; mem:LD4[FixedStack7]
> TBNZW %W8<kill>, 31, <BB#9>
976B	BB#8: derived from LLVM BB %lor.lhs.false.14
	    Live Ins: %X19
	    Predecessors according to CFG: BB#7
992B		%vreg36<def> = LDRWui <fi#7>, 0; mem:LD4[FixedStack7] GPR32common:%vreg36
1008B		%WZR<def> = SUBSWri %vreg36<kill>, 250, 0, %NZCV<imp-def>; GPR32common:%vreg36
1024B		Bcc 13, <BB#10>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#10 BB#9
> %W8<def> = LDRWui <fi#7>, 0; mem:LD4[FixedStack7]
> %WZR<def> = SUBSWri %W8<kill>, 250, 0, %NZCV<imp-def>
> Bcc 13, <BB#10>, %NZCV<imp-use,kill>
1040B	BB#9: derived from LLVM BB %if.then
	    Live Ins: %X19
	    Predecessors according to CFG: BB#0 BB#1 BB#2 BB#3 BB#4 BB#5 BB#6 BB#7 BB#8
1056B		%vreg89<def> = MOVi32imm 4294967294; GPR32:%vreg89
1072B		STRWui %vreg89<kill>, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg89
1088B		B <BB#21>
	    Successors according to CFG: BB#21
> %W8<def> = MOVi32imm 4294967294
> STRWui %W8<kill>, <fi#0>, 0; mem:ST4[FixedStack0]
> B <BB#21>
1104B	BB#10: derived from LLVM BB %if.end
	    Live Ins: %X19
	    Predecessors according to CFG: BB#8
1120B		%vreg38<def> = LDRWui <fi#7>, 0; mem:LD4[FixedStack7] GPR32:%vreg38
1136B		CBNZW %vreg38<kill>, <BB#12>; GPR32:%vreg38
	    Successors according to CFG: BB#12 BB#11
> %W8<def> = LDRWui <fi#7>, 0; mem:LD4[FixedStack7]
> CBNZW %W8<kill>, <BB#12>
1152B	BB#11: derived from LLVM BB %if.then.17
	    Live Ins: %X19
	    Predecessors according to CFG: BB#10
1168B		%vreg39<def> = MOVi32imm 30; GPR32:%vreg39
1184B		STRWui %vreg39<kill>, <fi#7>, 0; mem:ST4[FixedStack7] GPR32:%vreg39
	    Successors according to CFG: BB#12
> %W8<def> = MOVi32imm 30
> STRWui %W8<kill>, <fi#7>, 0; mem:ST4[FixedStack7]
1200B	BB#12: derived from LLVM BB %if.end.18
	    Live Ins: %X19
	    Predecessors according to CFG: BB#10 BB#11
1248B		STRXui %XZR, <fi#8>, 7; mem:ST80[FixedStack8(align=8)+7](align=1)
1264B		STRXui %XZR, <fi#8>, 8; mem:ST80[FixedStack8+8](align=8)
1280B		STRXui %XZR, <fi#8>, 9; mem:ST80[FixedStack8(align=8)+9](align=1)
1296B		%vreg50<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32:%vreg50
1312B		%vreg49<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg49
1328B		%vreg48<def> = LDRWui <fi#7>, 0; mem:LD4[FixedStack7] GPR32:%vreg48
1344B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1360B		%X0<def> = ADDXri <fi#8>, 0, 0
1376B		%W1<def> = COPY %vreg50<kill>; GPR32:%vreg50
1392B		%W2<def> = COPY %vreg49<kill>; GPR32:%vreg49
1408B		%W3<def> = COPY %vreg48<kill>; GPR32:%vreg48
1424B		BL <ga:@BZ2_bzCompressInit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %W2<imp-use>, %W3<imp-use>, %W0<imp-def>
1440B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1456B		%vreg47<def> = COPY %W0; GPR32:%vreg47
1472B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1488B		STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#9>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, 0, <fi#8>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack9](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3] LD8[FixedStack4](align=4) LD8[FixedStack8]
1504B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1520B		STRWui %vreg47<kill>, <fi#9>, 0; mem:ST4[FixedStack9] GPR32:%vreg47
1536B		%vreg41<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32:%vreg41
1552B		CBZW %vreg41<kill>, <BB#14>; GPR32:%vreg41
	    Successors according to CFG: BB#14 BB#13
> STRXui %XZR, <fi#8>, 7; mem:ST80[FixedStack8(align=8)+7](align=1)
> STRXui %XZR, <fi#8>, 8; mem:ST80[FixedStack8+8](align=8)
> STRXui %XZR, <fi#8>, 9; mem:ST80[FixedStack8(align=8)+9](align=1)
> %W1<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5]
> %W2<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6]
> %W3<def> = LDRWui <fi#7>, 0; mem:LD4[FixedStack7]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = ADDXri <fi#8>, 0, 0
> %W1<def> = COPY %W1<kill>
Deleting identity copy.
> %W2<def> = COPY %W2<kill>
Deleting identity copy.
> %W3<def> = COPY %W3<kill>
Deleting identity copy.
> BL <ga:@BZ2_bzCompressInit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %W2<imp-use>, %W3<imp-use>, %W0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = COPY %W0
Deleting identity copy.
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#9>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, 0, <fi#8>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack9](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3] LD8[FixedStack4](align=4) LD8[FixedStack8]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRWui %W0<kill>, <fi#9>, 0; mem:ST4[FixedStack9]
> %W8<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9]
> CBZW %W8<kill>, <BB#14>
1568B	BB#13: derived from LLVM BB %if.then.20
	    Live Ins: %X19
	    Predecessors according to CFG: BB#12
1584B		%vreg88<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32:%vreg88
1600B		STRWui %vreg88<kill>, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg88
1616B		B <BB#21>
	    Successors according to CFG: BB#21
> %W8<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9]
> STRWui %W8<kill>, <fi#0>, 0; mem:ST4[FixedStack0]
> B <BB#21>
1632B	BB#14: derived from LLVM BB %if.end.21
	    Live Ins: %X19
	    Predecessors according to CFG: BB#12
1680B		%vreg67<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg67
1696B		STRXui %vreg67<kill>, <fi#8>, 0; mem:ST80[FixedStack8](align=8) GPR64:%vreg67
1712B		%vreg65<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg65
1728B		STRXui %vreg65<kill>, <fi#8>, 3; mem:ST80[FixedStack8(align=8)+3](align=1) GPR64:%vreg65
1744B		%vreg63<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg63
1760B		STRWui %vreg63<kill>, <fi#8>, 2; mem:ST80[FixedStack8(align=8)+2](align=2) GPR32:%vreg63
1776B		%vreg61<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg61
1792B		%vreg60<def> = LDRWui %vreg61<kill>, 0; mem:LD4[%18] GPR32:%vreg60 GPR64common:%vreg61
1808B		STRWui %vreg60<kill>, <fi#8>, 8; mem:ST80[FixedStack8+8](align=8) GPR32:%vreg60
1824B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1840B		%X0<def> = ADDXri <fi#8>, 0, 0
1856B		%W1<def> = MOVi32imm 2
1872B		BL <ga:@BZ2_bzCompress>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %W0<imp-def>
1888B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1904B		%vreg57<def> = COPY %W0; GPR32:%vreg57
1920B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1936B		STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#9>, 0, 0, <fi#0>, 0, 0, <fi#8>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2] LD8[FixedStack9](align=4) LD8[FixedStack0](align=4) LD8[FixedStack8]
1952B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1968B		STRWui %vreg57<kill>, <fi#9>, 0; mem:ST4[FixedStack9] GPR32:%vreg57
1984B		%vreg53<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32common:%vreg53
2000B		%WZR<def> = SUBSWri %vreg53<kill>, 3, 0, %NZCV<imp-def>; GPR32common:%vreg53
2016B		Bcc 1, <BB#16>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#16 BB#15
> %X8<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> STRXui %X8<kill>, <fi#8>, 0; mem:ST80[FixedStack8](align=8)
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRXui %X8<kill>, <fi#8>, 3; mem:ST80[FixedStack8(align=8)+3](align=1)
> %W8<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4]
> STRWui %W8<kill>, <fi#8>, 2; mem:ST80[FixedStack8(align=8)+2](align=2)
> %X8<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2]
> %W8<def> = LDRWui %X8<kill>, 0; mem:LD4[%18]
> STRWui %W8<kill>, <fi#8>, 8; mem:ST80[FixedStack8+8](align=8)
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = ADDXri <fi#8>, 0, 0
> %W1<def> = MOVi32imm 2
> BL <ga:@BZ2_bzCompress>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %W0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = COPY %W0
Deleting identity copy.
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#9>, 0, 0, <fi#0>, 0, 0, <fi#8>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2] LD8[FixedStack9](align=4) LD8[FixedStack0](align=4) LD8[FixedStack8]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRWui %W0<kill>, <fi#9>, 0; mem:ST4[FixedStack9]
> %W8<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9]
> %WZR<def> = SUBSWri %W8<kill>, 3, 0, %NZCV<imp-def>
> Bcc 1, <BB#16>, %NZCV<imp-use,kill>
2032B	BB#15: derived from LLVM BB %if.then.24
	    Live Ins: %X19
	    Predecessors according to CFG: BB#14
2048B		B <BB#19>
	    Successors according to CFG: BB#19
> B <BB#19>
2064B	BB#16: derived from LLVM BB %if.end.25
	    Live Ins: %X19
	    Predecessors according to CFG: BB#14
2080B		%vreg69<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32common:%vreg69
2096B		%WZR<def> = SUBSWri %vreg69<kill>, 4, 0, %NZCV<imp-def>; GPR32common:%vreg69
2112B		Bcc 0, <BB#18>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#18 BB#17
> %W8<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9]
> %WZR<def> = SUBSWri %W8<kill>, 4, 0, %NZCV<imp-def>
> Bcc 0, <BB#18>, %NZCV<imp-use,kill>
2128B	BB#17: derived from LLVM BB %if.then.27
	    Live Ins: %X19
	    Predecessors according to CFG: BB#16
2144B		B <BB#20>
	    Successors according to CFG: BB#20
> B <BB#20>
2160B	BB#18: derived from LLVM BB %if.end.28
	    Live Ins: %X19
	    Predecessors according to CFG: BB#16
2208B		%vreg78<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg78
2216B		%vreg79<def> = LDRWui <fi#8>, 8; mem:LD80[FixedStack8+8](align=8) GPR32:%vreg79
2224B		%vreg77<def> = LDRWui %vreg78, 0; mem:LD4[%23] GPR32:%vreg77 GPR64common:%vreg78
2240B		%vreg76<def> = SUBWrr %vreg77<kill>, %vreg79<kill>; GPR32:%vreg76,%vreg77,%vreg79
2256B		STRWui %vreg76<kill>, %vreg78<kill>, 0; mem:ST4[%23] GPR32:%vreg76 GPR64common:%vreg78
2272B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2288B		%X0<def> = ADDXri <fi#8>, 0, 0
2304B		BL <ga:@BZ2_bzCompressEnd>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
2320B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2336B		%vreg71<def,dead> = COPY %W0; GPR32all:%vreg71
2352B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2368B		STACKMAP 3, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
2384B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2400B		STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
2416B		B <BB#21>
	    Successors according to CFG: BB#21
> %X8<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2]
> %W9<def> = LDRWui <fi#8>, 8; mem:LD80[FixedStack8+8](align=8)
> %W10<def> = LDRWui %X8, 0; mem:LD4[%23]
> %W9<def> = SUBWrr %W10<kill>, %W9<kill>
> STRWui %W9<kill>, %X8<kill>, 0; mem:ST4[%23]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = ADDXri <fi#8>, 0, 0
> BL <ga:@BZ2_bzCompressEnd>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def,dead> = COPY %W0
Deleting identity copy.
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 3, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
> B <BB#21>
2432B	BB#19: derived from LLVM BB %output_overflow
	    Live Ins: %X19
	    Predecessors according to CFG: BB#15
2464B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2480B		%X0<def> = ADDXri <fi#8>, 0, 0
2496B		BL <ga:@BZ2_bzCompressEnd>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
2512B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2528B		%vreg86<def,dead> = COPY %W0; GPR32all:%vreg86
2544B		%vreg84<def> = MOVi32imm 4294967288; GPR32:%vreg84
2560B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2576B		STACKMAP 4, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
2592B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2608B		STRWui %vreg84<kill>, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg84
2624B		B <BB#21>
	    Successors according to CFG: BB#21
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = ADDXri <fi#8>, 0, 0
> BL <ga:@BZ2_bzCompressEnd>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def,dead> = COPY %W0
Deleting identity copy.
> %W8<def> = MOVi32imm 4294967288
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 4, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRWui %W8<kill>, <fi#0>, 0; mem:ST4[FixedStack0]
> B <BB#21>
2640B	BB#20: derived from LLVM BB %errhandler
	    Live Ins: %X19
	    Predecessors according to CFG: BB#17
2672B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2688B		%X0<def> = ADDXri <fi#8>, 0, 0
2704B		BL <ga:@BZ2_bzCompressEnd>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
2720B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2736B		%vreg83<def,dead> = COPY %W0; GPR32all:%vreg83
2752B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2768B		STACKMAP 5, 0, 0, <fi#9>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack9](align=4) LD8[FixedStack0](align=4)
2784B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2800B		%vreg81<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9] GPR32:%vreg81
2816B		STRWui %vreg81<kill>, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg81
	    Successors according to CFG: BB#21
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = ADDXri <fi#8>, 0, 0
> BL <ga:@BZ2_bzCompressEnd>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def,dead> = COPY %W0
Deleting identity copy.
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 5, 0, 0, <fi#9>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack9](align=4) LD8[FixedStack0](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W8<def> = LDRWui <fi#9>, 0; mem:LD4[FixedStack9]
> STRWui %W8<kill>, <fi#0>, 0; mem:ST4[FixedStack0]
2832B	BB#21: derived from LLVM BB %return
	    Live Ins: %X19
	    Predecessors according to CFG: BB#18 BB#20 BB#19 BB#13 BB#9
2848B		%vreg92<def> = ADRP <ga:@BZ2_bzBuffToBuffCompress>[TF=1]; GPR64common:%vreg92
2864B		%vreg94<def> = ADDXri %vreg92<kill>, <ga:@BZ2_bzBuffToBuffCompress>[TF=34], 0; GPR64sp:%vreg94 GPR64common:%vreg92
2912B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2928B		%X0<def> = COPY %vreg94<kill>; GPR64sp:%vreg94
2944B		%X1<def> = COPY %vreg19<kill>; GPR64:%vreg19
2960B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
2976B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2992B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3008B		STACKMAP 6, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
3024B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3040B		%vreg91<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0] GPR32:%vreg91
3056B		%W0<def> = COPY %vreg91<kill>; GPR32:%vreg91
3072B		RET_ReallyLR %W0<imp-use>
> %X8<def> = ADRP <ga:@BZ2_bzBuffToBuffCompress>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@BZ2_bzBuffToBuffCompress>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19<kill>
> BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 6, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0]
> %W0<def> = COPY %W0<kill>
Deleting identity copy.
> RET_ReallyLR %W0<imp-use>
Computing live-in reg-units in ABI blocks.
0B	BB#0 W0#0 W1#0 W2#0 W3#0 W4#0 W5#0 W30#0
Created 7 new intervals.
********** INTERVALS **********
W30 [0B,16r:0)[336r,336d:16)[384e,384d:8)[1120r,1120d:15)[1184e,1184d:7)[1536r,1536d:14)[1600e,1600d:6)[1952r,1952d:13)[2016e,2016d:5)[2208r,2208d:10)[2288e,2288d:4)[2416r,2416d:11)[2496e,2496d:3)[2624r,2624d:12)[2688e,2688d:2)[2880r,2880d:9)[2928e,2928d:1)  0@0B-phi 1@2928e 2@2688e 3@2496e 4@2288e 5@2016e 6@1600e 7@1184e 8@384e 9@2880r 10@2208r 11@2416r 12@2624r 13@1952r 14@1536r 15@1120r 16@336r
W0 [0B,112r:0)[304r,336r:15)[1072r,1120r:14)[1120r,1152r:7)[1520r,1536r:13)[1536r,1568r:6)[1936r,1952r:12)[1952r,1984r:5)[2192r,2208r:9)[2208r,2240r:2)[2400r,2416r:10)[2416r,2448r:3)[2608r,2624r:11)[2624r,2656r:4)[2848r,2880r:8)[2976r,2992r:1)  0@0B-phi 1@2976r 2@2208r 3@2416r 4@2624r 5@1952r 6@1536r 7@1120r 8@2848r 9@2192r 10@2400r 11@2608r 12@1936r 13@1520r 14@1072r 15@304r
W1 [0B,96r:0)[320r,336r:3)[1088r,1120r:1)[2864r,2880r:2)  0@0B-phi 1@1088r 2@2864r 3@320r
W2 [0B,80r:0)[1104r,1120r:1)  0@0B-phi 1@1104r
W3 [0B,64r:0)  0@0B-phi
W4 [0B,48r:0)  0@0B-phi
W5 [0B,32r:0)  0@0B-phi
%vreg0 [112r,128r:0)  0@112r
%vreg1 [128r,416r:0)  0@128r
%vreg2 [96r,144r:0)  0@96r
%vreg3 [144r,432r:0)  0@144r
%vreg4 [80r,160r:0)  0@80r
%vreg5 [160r,448r:0)  0@160r
%vreg6 [64r,176r:0)  0@64r
%vreg7 [176r,464r:0)  0@176r
%vreg8 [48r,192r:0)  0@48r
%vreg9 [192r,480r:0)  0@192r
%vreg10 [32r,208r:0)  0@32r
%vreg11 [208r,496r:0)  0@208r
%vreg13 [512r,528r:0)  0@512r
%vreg14 [224r,240r:0)  0@224r
%vreg15 [240r,256r:0)  0@240r
%vreg16 [256r,304r:0)  0@256r
%vreg17 [272r,320r:0)  0@272r
%vreg18 [16r,2816r:0)  0@16r
%vreg20 [560r,576r:0)  0@560r
%vreg22 [608r,624r:0)  0@608r
%vreg24 [656r,672r:0)  0@656r
%vreg26 [704r,720r:0)  0@704r
%vreg28 [768r,784r:0)  0@768r
%vreg30 [816r,832r:0)  0@816r
%vreg32 [1232r,1248r:0)  0@1232r
%vreg34 [944r,1072r:0)  0@944r
%vreg37 [1152r,1216r:0)  0@1152r
%vreg38 [1040r,1104r:0)  0@1040r
%vreg39 [1024r,1088r:0)  0@1024r
%vreg40 [960r,1008r:0)  0@960r
%vreg42 [1648r,1664r:0)  0@1648r
%vreg44 [1344r,1520r:0)  0@1344r
%vreg45 [1568r,1632r:0)  0@1568r
%vreg48 [1472r,1488r:0)  0@1472r
%vreg49 [1456r,1472r:0)  0@1456r
%vreg51 [1424r,1440r:0)  0@1424r
%vreg53 [1392r,1408r:0)  0@1392r
%vreg55 [1360r,1376r:0)  0@1360r
%vreg57 [1728r,1744r:0)  0@1728r
%vreg58 [1824r,1936r:0)  0@1824r
%vreg59 [1984r,1984d:0)  0@1984r
%vreg64 [1888r,1904r:0)  0@1888r
%vreg65 [1872r,1888r:0)  0@1872r
%vreg66 [1856r,1904r:0)  0@1856r
%vreg67 [1840r,1888r:0)  0@1840r
%vreg69 [2720r,2736r:0)  0@2720r
%vreg70 [2576r,2608r:0)  0@2576r
%vreg71 [2656r,2656d:0)  0@2656r
%vreg73 [2096r,2112r:0)  0@2096r
%vreg74 [2464r,2528r:0)  0@2464r
%vreg75 [2368r,2400r:0)  0@2368r
%vreg76 [2448r,2448d:0)  0@2448r
%vreg77 [2256r,2320r:0)  0@2256r
%vreg78 [2160r,2192r:0)  0@2160r
%vreg79 [2240r,2240d:0)  0@2240r
%vreg81 [1280r,1296r:0)  0@1280r
%vreg82 [880r,896r:0)  0@880r
%vreg84 [2960r,2976r:0)  0@2960r
%vreg85 [2768r,2784r:0)  0@2768r
%vreg86 [2784r,2800r:0)  0@2784r
%vreg87 [2800r,2848r:0)  0@2800r
%vreg88 [2816r,2864r:0)  0@2816r
RegMasks: 336r 1120r 1536r 1952r 2208r 2416r 2624r 2880r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzBuffToBuffDecompress: Post SSA
Frame Objects:
  fi#0: size=4, align=4, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=8, align=8, at location [SP]
  fi#3: size=8, align=8, at location [SP]
  fi#4: size=4, align=4, at location [SP]
  fi#5: size=4, align=4, at location [SP]
  fi#6: size=4, align=4, at location [SP]
  fi#7: size=80, align=8, at location [SP]
  fi#8: size=4, align=4, at location [SP]
Function Live Ins: %X0 in %vreg0, %X1 in %vreg2, %X2 in %vreg4, %W3 in %vreg6, %W4 in %vreg8, %W5 in %vreg10, %LR in %vreg18

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %X1 %X2 %W3 %W4 %W5 %LR
16B		%vreg18<def> = COPY %LR; GPR64:%vreg18
32B		%vreg10<def> = COPY %W5; GPR32:%vreg10
48B		%vreg8<def> = COPY %W4; GPR32:%vreg8
64B		%vreg6<def> = COPY %W3; GPR32:%vreg6
80B		%vreg4<def> = COPY %X2; GPR64:%vreg4
96B		%vreg2<def> = COPY %X1; GPR64:%vreg2
112B		%vreg0<def> = COPY %X0; GPR64:%vreg0
128B		%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
144B		%vreg3<def> = COPY %vreg2; GPR64:%vreg3,%vreg2
160B		%vreg5<def> = COPY %vreg4; GPR64:%vreg5,%vreg4
176B		%vreg7<def> = COPY %vreg6; GPR32:%vreg7,%vreg6
192B		%vreg9<def> = COPY %vreg8; GPR32:%vreg9,%vreg8
208B		%vreg11<def> = COPY %vreg10; GPR32:%vreg11,%vreg10
224B		%vreg14<def> = ADRP <ga:@BZ2_bzBuffToBuffDecompress>[TF=1]; GPR64common:%vreg14
240B		%vreg15<def> = ADDXri %vreg14, <ga:@BZ2_bzBuffToBuffDecompress>[TF=34], 0; GPR64sp:%vreg15 GPR64common:%vreg14
256B		%vreg16<def> = COPY %vreg15; GPR64all:%vreg16 GPR64sp:%vreg15
272B		%vreg17<def> = COPY %vreg18; GPR64all:%vreg17 GPR64:%vreg18
288B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
304B		%X0<def> = COPY %vreg16; GPR64all:%vreg16
320B		%X1<def> = COPY %vreg17; GPR64all:%vreg17
336B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
352B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
368B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
384B		STACKMAP 0, 0, %vreg1, 0, <fi#1>, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, %vreg9, 0, <fi#5>, 0, %vreg5, 0, <fi#3>, 0, %vreg7, 0, <fi#4>, 0, 0, <fi#7>, 0, %vreg11, 0, <fi#6>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack8](align=4) LD8[FixedStack0](align=4) LD8[FixedStack5](align=4) LD8[FixedStack3] LD8[FixedStack4](align=4) LD8[FixedStack7] LD8[FixedStack6](align=4) GPR64:%vreg1,%vreg3,%vreg5 GPR32:%vreg9,%vreg7,%vreg11
400B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
416B		STRXui %vreg1, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg1
432B		STRXui %vreg3, <fi#2>, 0; mem:ST8[FixedStack2] GPR64:%vreg3
448B		STRXui %vreg5, <fi#3>, 0; mem:ST8[FixedStack3] GPR64:%vreg5
464B		STRWui %vreg7, <fi#4>, 0; mem:ST4[FixedStack4] GPR32:%vreg7
480B		STRWui %vreg9, <fi#5>, 0; mem:ST4[FixedStack5] GPR32:%vreg9
496B		STRWui %vreg11, <fi#6>, 0; mem:ST4[FixedStack6] GPR32:%vreg11
512B		%vreg13<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg13
528B		CBZX %vreg13, <BB#7>; GPR64:%vreg13
	    Successors according to CFG: BB#7 BB#1

544B	BB#1: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#0
560B		%vreg20<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg20
576B		CBZX %vreg20, <BB#7>; GPR64:%vreg20
	    Successors according to CFG: BB#7 BB#2

592B	BB#2: derived from LLVM BB %lor.lhs.false.2
	    Predecessors according to CFG: BB#1
608B		%vreg22<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg22
624B		CBZX %vreg22, <BB#7>; GPR64:%vreg22
	    Successors according to CFG: BB#7 BB#3

640B	BB#3: derived from LLVM BB %lor.lhs.false.4
	    Predecessors according to CFG: BB#2
656B		%vreg24<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32:%vreg24
672B		CBZW %vreg24, <BB#5>; GPR32:%vreg24
	    Successors according to CFG: BB#5 BB#4

688B	BB#4: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#3
704B		%vreg26<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32common:%vreg26
720B		%WZR<def> = SUBSWri %vreg26, 1, 0, %NZCV<imp-def>; GPR32common:%vreg26
736B		Bcc 1, <BB#7>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#7 BB#5

752B	BB#5: derived from LLVM BB %lor.lhs.false.7
	    Predecessors according to CFG: BB#3 BB#4
768B		%vreg28<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg28
784B		TBNZW %vreg28, 31, <BB#7>; GPR32:%vreg28
	    Successors according to CFG: BB#7 BB#6

800B	BB#6: derived from LLVM BB %lor.lhs.false.9
	    Predecessors according to CFG: BB#5
816B		%vreg30<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32common:%vreg30
832B		%WZR<def> = SUBSWri %vreg30, 4, 0, %NZCV<imp-def>; GPR32common:%vreg30
848B		Bcc 13, <BB#8>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#8 BB#7

864B	BB#7: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0 BB#1 BB#2 BB#4 BB#5 BB#6
880B		%vreg82<def> = MOVi32imm 4294967294; GPR32:%vreg82
896B		STRWui %vreg82, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg82
912B		B <BB#19>
	    Successors according to CFG: BB#19

928B	BB#8: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#6
944B		%vreg34<def> = ADDXri <fi#7>, 0, 0; GPR64sp:%vreg34
960B		%vreg40<def> = COPY %XZR; GPR64:%vreg40
976B		STRXui %vreg40, <fi#7>, 7; mem:ST80[FixedStack7(align=8)+7](align=1) GPR64:%vreg40
992B		STRXui %vreg40, <fi#7>, 8; mem:ST80[FixedStack7+8](align=8) GPR64:%vreg40
1008B		STRXui %vreg40, <fi#7>, 9; mem:ST80[FixedStack7(align=8)+9](align=1) GPR64:%vreg40
1024B		%vreg39<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg39
1040B		%vreg38<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32:%vreg38
1056B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1072B		%X0<def> = COPY %vreg34; GPR64sp:%vreg34
1088B		%W1<def> = COPY %vreg39; GPR32:%vreg39
1104B		%W2<def> = COPY %vreg38; GPR32:%vreg38
1120B		BL <ga:@BZ2_bzDecompressInit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %W2<imp-use>, %W0<imp-def>
1136B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1152B		%vreg37<def> = COPY %W0; GPR32:%vreg37
1168B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1184B		STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, 0, <fi#7>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack8](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3] LD8[FixedStack4](align=4) LD8[FixedStack7]
1200B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1216B		STRWui %vreg37, <fi#8>, 0; mem:ST4[FixedStack8] GPR32:%vreg37
1232B		%vreg32<def> = LDRWui <fi#8>, 0; mem:LD4[FixedStack8] GPR32:%vreg32
1248B		CBZW %vreg32, <BB#10>; GPR32:%vreg32
	    Successors according to CFG: BB#10 BB#9

1264B	BB#9: derived from LLVM BB %if.then.12
	    Predecessors according to CFG: BB#8
1280B		%vreg81<def> = LDRWui <fi#8>, 0; mem:LD4[FixedStack8] GPR32:%vreg81
1296B		STRWui %vreg81, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg81
1312B		B <BB#19>
	    Successors according to CFG: BB#19

1328B	BB#10: derived from LLVM BB %if.end.13
	    Predecessors according to CFG: BB#8
1344B		%vreg44<def> = ADDXri <fi#7>, 0, 0; GPR64sp:%vreg44
1360B		%vreg55<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg55
1376B		STRXui %vreg55, <fi#7>, 0; mem:ST80[FixedStack7](align=8) GPR64:%vreg55
1392B		%vreg53<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg53
1408B		STRXui %vreg53, <fi#7>, 3; mem:ST80[FixedStack7(align=8)+3](align=1) GPR64:%vreg53
1424B		%vreg51<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg51
1440B		STRWui %vreg51, <fi#7>, 2; mem:ST80[FixedStack7(align=8)+2](align=2) GPR32:%vreg51
1456B		%vreg49<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg49
1472B		%vreg48<def> = LDRWui %vreg49, 0; mem:LD4[%14] GPR32:%vreg48 GPR64common:%vreg49
1488B		STRWui %vreg48, <fi#7>, 8; mem:ST80[FixedStack7+8](align=8) GPR32:%vreg48
1504B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1520B		%X0<def> = COPY %vreg44; GPR64sp:%vreg44
1536B		BL <ga:@BZ2_bzDecompress>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
1552B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1568B		%vreg45<def> = COPY %W0; GPR32:%vreg45
1584B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1600B		STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, 0, <fi#7>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2] LD8[FixedStack8](align=4) LD8[FixedStack0](align=4) LD8[FixedStack7]
1616B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1632B		STRWui %vreg45, <fi#8>, 0; mem:ST4[FixedStack8] GPR32:%vreg45
1648B		%vreg42<def> = LDRWui <fi#8>, 0; mem:LD4[FixedStack8] GPR32:%vreg42
1664B		CBNZW %vreg42, <BB#12>; GPR32:%vreg42
	    Successors according to CFG: BB#12 BB#11

1680B	BB#11: derived from LLVM BB %if.then.16
	    Predecessors according to CFG: BB#10
1696B		B <BB#15>
	    Successors according to CFG: BB#15

1712B	BB#12: derived from LLVM BB %if.end.17
	    Predecessors according to CFG: BB#10
1728B		%vreg57<def> = LDRWui <fi#8>, 0; mem:LD4[FixedStack8] GPR32common:%vreg57
1744B		%WZR<def> = SUBSWri %vreg57, 4, 0, %NZCV<imp-def>; GPR32common:%vreg57
1760B		Bcc 0, <BB#14>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#14 BB#13

1776B	BB#13: derived from LLVM BB %if.then.19
	    Predecessors according to CFG: BB#12
1792B		B <BB#18>
	    Successors according to CFG: BB#18

1808B	BB#14: derived from LLVM BB %if.end.20
	    Predecessors according to CFG: BB#12
1824B		%vreg58<def> = ADDXri <fi#7>, 0, 0; GPR64sp:%vreg58
1840B		%vreg67<def> = LDRWui <fi#7>, 8; mem:LD80[FixedStack7+8](align=8) GPR32:%vreg67
1856B		%vreg66<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg66
1872B		%vreg65<def> = LDRWui %vreg66, 0; mem:LD4[%19] GPR32:%vreg65 GPR64common:%vreg66
1888B		%vreg64<def> = SUBWrr %vreg65, %vreg67; GPR32:%vreg64,%vreg65,%vreg67
1904B		STRWui %vreg64, %vreg66, 0; mem:ST4[%19] GPR32:%vreg64 GPR64common:%vreg66
1920B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1936B		%X0<def> = COPY %vreg58; GPR64sp:%vreg58
1952B		BL <ga:@BZ2_bzDecompressEnd>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
1968B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1984B		%vreg59<def,dead> = COPY %W0; GPR32all:%vreg59
2000B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2016B		STACKMAP 3, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
2032B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2048B		STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
2064B		B <BB#19>
	    Successors according to CFG: BB#19

2080B	BB#15: derived from LLVM BB %output_overflow_or_eof
	    Predecessors according to CFG: BB#11
2096B		%vreg73<def> = LDRWui <fi#7>, 8; mem:LD80[FixedStack7+8](align=8) GPR32common:%vreg73
2112B		%WZR<def> = SUBSWri %vreg73, 0, 0, %NZCV<imp-def>; GPR32common:%vreg73
2128B		Bcc 9, <BB#17>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#17 BB#16

2144B	BB#16: derived from LLVM BB %if.then.25
	    Predecessors according to CFG: BB#15
2160B		%vreg78<def> = ADDXri <fi#7>, 0, 0; GPR64sp:%vreg78
2176B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2192B		%X0<def> = COPY %vreg78; GPR64sp:%vreg78
2208B		BL <ga:@BZ2_bzDecompressEnd>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
2224B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2240B		%vreg79<def,dead> = COPY %W0; GPR32all:%vreg79
2256B		%vreg77<def> = MOVi32imm 4294967289; GPR32:%vreg77
2272B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2288B		STACKMAP 4, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
2304B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2320B		STRWui %vreg77, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg77
2336B		B <BB#19>
	    Successors according to CFG: BB#19

2352B	BB#17: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#15
2368B		%vreg75<def> = ADDXri <fi#7>, 0, 0; GPR64sp:%vreg75
2384B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2400B		%X0<def> = COPY %vreg75; GPR64sp:%vreg75
2416B		BL <ga:@BZ2_bzDecompressEnd>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
2432B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2448B		%vreg76<def,dead> = COPY %W0; GPR32all:%vreg76
2464B		%vreg74<def> = MOVi32imm 4294967288; GPR32:%vreg74
2480B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2496B		STACKMAP 5, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
2512B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2528B		STRWui %vreg74, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg74
2544B		B <BB#19>
	    Successors according to CFG: BB#19

2560B	BB#18: derived from LLVM BB %errhandler
	    Predecessors according to CFG: BB#13
2576B		%vreg70<def> = ADDXri <fi#7>, 0, 0; GPR64sp:%vreg70
2592B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2608B		%X0<def> = COPY %vreg70; GPR64sp:%vreg70
2624B		BL <ga:@BZ2_bzDecompressEnd>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
2640B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2656B		%vreg71<def,dead> = COPY %W0; GPR32all:%vreg71
2672B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2688B		STACKMAP 6, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack8](align=4) LD8[FixedStack0](align=4)
2704B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2720B		%vreg69<def> = LDRWui <fi#8>, 0; mem:LD4[FixedStack8] GPR32:%vreg69
2736B		STRWui %vreg69, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg69
	    Successors according to CFG: BB#19

2752B	BB#19: derived from LLVM BB %return
	    Predecessors according to CFG: BB#14 BB#18 BB#17 BB#16 BB#9 BB#7
2768B		%vreg85<def> = ADRP <ga:@BZ2_bzBuffToBuffDecompress>[TF=1]; GPR64common:%vreg85
2784B		%vreg86<def> = ADDXri %vreg85, <ga:@BZ2_bzBuffToBuffDecompress>[TF=34], 0; GPR64sp:%vreg86 GPR64common:%vreg85
2800B		%vreg87<def> = COPY %vreg86; GPR64all:%vreg87 GPR64sp:%vreg86
2816B		%vreg88<def> = COPY %vreg18; GPR64all:%vreg88 GPR64:%vreg18
2832B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2848B		%X0<def> = COPY %vreg87; GPR64all:%vreg87
2864B		%X1<def> = COPY %vreg88; GPR64all:%vreg88
2880B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
2896B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2912B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2928B		STACKMAP 7, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
2944B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2960B		%vreg84<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0] GPR32:%vreg84
2976B		%W0<def> = COPY %vreg84; GPR32:%vreg84
2992B		RET_ReallyLR %W0<imp-use>

# End machine code for function BZ2_bzBuffToBuffDecompress.

********** SIMPLE REGISTER COALESCING **********
********** Function: BZ2_bzBuffToBuffDecompress
********** JOINING INTERVALS ***********
if.then:
return:
2848B	%X0<def> = COPY %vreg87; GPR64all:%vreg87
	Considering merging %vreg87 with %X0
	Can only merge into reserved registers.
2864B	%X1<def> = COPY %vreg88; GPR64all:%vreg88
	Considering merging %vreg88 with %X1
	Can only merge into reserved registers.
2976B	%W0<def> = COPY %vreg84; GPR32:%vreg84
	Considering merging %vreg84 with %W0
	Can only merge into reserved registers.
lor.lhs.false.7:
lor.lhs.false:
lor.lhs.false.2:
lor.lhs.false.4:
land.lhs.true:
lor.lhs.false.9:
if.end:
960B	%vreg40<def> = COPY %XZR; GPR64:%vreg40
	Considering merging %vreg40 with %XZR
		RHS = %vreg40 [960r,1008r:0)  0@960r
		updated: 1008B	STRXui %XZR, <fi#7>, 9; mem:ST80[FixedStack7(align=8)+9](align=1)
		updated: 992B	STRXui %XZR, <fi#7>, 8; mem:ST80[FixedStack7+8](align=8)
		updated: 976B	STRXui %XZR, <fi#7>, 7; mem:ST80[FixedStack7(align=8)+7](align=1)
	Success: %vreg40 -> %XZR
	Result = %XZR
1072B	%X0<def> = COPY %vreg34; GPR64sp:%vreg34
	Considering merging %vreg34 with %X0
	Can only merge into reserved registers.
Remat: %X0<def> = ADDXri <fi#7>, 0, 0
Shrink: %vreg34 [944r,1072r:0)  0@944r
All defs dead: 944r	%vreg34<def,dead> = ADDXri <fi#7>, 0, 0; GPR64sp:%vreg34
Shrunk: %vreg34 [944r,944d:0)  0@944r
Deleting dead def 944r	%vreg34<def,dead> = ADDXri <fi#7>, 0, 0; GPR64sp:%vreg34
1088B	%W1<def> = COPY %vreg39; GPR32:%vreg39
	Considering merging %vreg39 with %W1
	Can only merge into reserved registers.
1104B	%W2<def> = COPY %vreg38; GPR32:%vreg38
	Considering merging %vreg38 with %W2
	Can only merge into reserved registers.
1152B	%vreg37<def> = COPY %W0; GPR32:%vreg37
	Considering merging %vreg37 with %W0
	Can only merge into reserved registers.
if.end.13:
1520B	%X0<def> = COPY %vreg44; GPR64sp:%vreg44
	Considering merging %vreg44 with %X0
	Can only merge into reserved registers.
Remat: %X0<def> = ADDXri <fi#7>, 0, 0
Shrink: %vreg44 [1344r,1520r:0)  0@1344r
All defs dead: 1344r	%vreg44<def,dead> = ADDXri <fi#7>, 0, 0; GPR64sp:%vreg44
Shrunk: %vreg44 [1344r,1344d:0)  0@1344r
Deleting dead def 1344r	%vreg44<def,dead> = ADDXri <fi#7>, 0, 0; GPR64sp:%vreg44
1568B	%vreg45<def> = COPY %W0; GPR32:%vreg45
	Considering merging %vreg45 with %W0
	Can only merge into reserved registers.
if.end.17:
output_overflow_or_eof:
entry:
16B	%vreg18<def> = COPY %LR; GPR64:%vreg18
	Considering merging %vreg18 with %LR
	Can only merge into reserved registers.
32B	%vreg10<def> = COPY %W5; GPR32:%vreg10
	Considering merging %vreg10 with %W5
	Can only merge into reserved registers.
48B	%vreg8<def> = COPY %W4; GPR32:%vreg8
	Considering merging %vreg8 with %W4
	Can only merge into reserved registers.
64B	%vreg6<def> = COPY %W3; GPR32:%vreg6
	Considering merging %vreg6 with %W3
	Can only merge into reserved registers.
80B	%vreg4<def> = COPY %X2; GPR64:%vreg4
	Considering merging %vreg4 with %X2
	Can only merge into reserved registers.
96B	%vreg2<def> = COPY %X1; GPR64:%vreg2
	Considering merging %vreg2 with %X1
	Can only merge into reserved registers.
112B	%vreg0<def> = COPY %X0; GPR64:%vreg0
	Considering merging %vreg0 with %X0
	Can only merge into reserved registers.
304B	%X0<def> = COPY %vreg16; GPR64all:%vreg16
	Considering merging %vreg16 with %X0
	Can only merge into reserved registers.
320B	%X1<def> = COPY %vreg17; GPR64all:%vreg17
	Considering merging %vreg17 with %X1
	Can only merge into reserved registers.
if.then.12:
if.then.16:
if.then.19:
if.end.20:
1936B	%X0<def> = COPY %vreg58; GPR64sp:%vreg58
	Considering merging %vreg58 with %X0
	Can only merge into reserved registers.
Remat: %X0<def> = ADDXri <fi#7>, 0, 0
Shrink: %vreg58 [1824r,1936r:0)  0@1824r
All defs dead: 1824r	%vreg58<def,dead> = ADDXri <fi#7>, 0, 0; GPR64sp:%vreg58
Shrunk: %vreg58 [1824r,1824d:0)  0@1824r
Deleting dead def 1824r	%vreg58<def,dead> = ADDXri <fi#7>, 0, 0; GPR64sp:%vreg58
1984B	%vreg59<def,dead> = COPY %W0; GPR32all:%vreg59
	Considering merging %vreg59 with %W0
	Can only merge into reserved registers.
if.then.25:
2192B	%X0<def> = COPY %vreg78; GPR64sp:%vreg78
	Considering merging %vreg78 with %X0
	Can only merge into reserved registers.
Remat: %X0<def> = ADDXri <fi#7>, 0, 0
Shrink: %vreg78 [2160r,2192r:0)  0@2160r
All defs dead: 2160r	%vreg78<def,dead> = ADDXri <fi#7>, 0, 0; GPR64sp:%vreg78
Shrunk: %vreg78 [2160r,2160d:0)  0@2160r
Deleting dead def 2160r	%vreg78<def,dead> = ADDXri <fi#7>, 0, 0; GPR64sp:%vreg78
2240B	%vreg79<def,dead> = COPY %W0; GPR32all:%vreg79
	Considering merging %vreg79 with %W0
	Can only merge into reserved registers.
if.else:
2400B	%X0<def> = COPY %vreg75; GPR64sp:%vreg75
	Considering merging %vreg75 with %X0
	Can only merge into reserved registers.
Remat: %X0<def> = ADDXri <fi#7>, 0, 0
Shrink: %vreg75 [2368r,2400r:0)  0@2368r
All defs dead: 2368r	%vreg75<def,dead> = ADDXri <fi#7>, 0, 0; GPR64sp:%vreg75
Shrunk: %vreg75 [2368r,2368d:0)  0@2368r
Deleting dead def 2368r	%vreg75<def,dead> = ADDXri <fi#7>, 0, 0; GPR64sp:%vreg75
2448B	%vreg76<def,dead> = COPY %W0; GPR32all:%vreg76
	Considering merging %vreg76 with %W0
	Can only merge into reserved registers.
errhandler:
2608B	%X0<def> = COPY %vreg70; GPR64sp:%vreg70
	Considering merging %vreg70 with %X0
	Can only merge into reserved registers.
Remat: %X0<def> = ADDXri <fi#7>, 0, 0
Shrink: %vreg70 [2576r,2608r:0)  0@2576r
All defs dead: 2576r	%vreg70<def,dead> = ADDXri <fi#7>, 0, 0; GPR64sp:%vreg70
Shrunk: %vreg70 [2576r,2576d:0)  0@2576r
Deleting dead def 2576r	%vreg70<def,dead> = ADDXri <fi#7>, 0, 0; GPR64sp:%vreg70
2656B	%vreg71<def,dead> = COPY %W0; GPR32all:%vreg71
	Considering merging %vreg71 with %W0
	Can only merge into reserved registers.
2800B	%vreg87<def> = COPY %vreg86; GPR64all:%vreg87 GPR64sp:%vreg86
	Considering merging to GPR64sp with %vreg86 in %vreg87
		RHS = %vreg86 [2784r,2800r:0)  0@2784r
		LHS = %vreg87 [2800r,2848r:0)  0@2800r
		merge %vreg87:0@2800r into %vreg86:0@2784r --> @2784r
		erased:	2800r	%vreg87<def> = COPY %vreg86; GPR64all:%vreg87 GPR64sp:%vreg86
		updated: 2784B	%vreg87<def> = ADDXri %vreg85, <ga:@BZ2_bzBuffToBuffDecompress>[TF=34], 0; GPR64sp:%vreg87 GPR64common:%vreg85
	Success: %vreg86 -> %vreg87
	Result = %vreg87 [2784r,2848r:0)  0@2784r
2816B	%vreg88<def> = COPY %vreg18; GPR64all:%vreg88 GPR64:%vreg18
	Considering merging to GPR64 with %vreg18 in %vreg88
		RHS = %vreg18 [16r,2816r:0)  0@16r
		LHS = %vreg88 [2816r,2864r:0)  0@2816r
		merge %vreg88:0@2816r into %vreg18:0@16r --> @16r
		erased:	2816r	%vreg88<def> = COPY %vreg18; GPR64all:%vreg88 GPR64:%vreg18
		updated: 16B	%vreg88<def> = COPY %LR; GPR64:%vreg88
		updated: 272B	%vreg17<def> = COPY %vreg88; GPR64all:%vreg17 GPR64:%vreg88
	Success: %vreg18 -> %vreg88
	Result = %vreg88 [16r,2864r:0)  0@16r
128B	%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
	Considering merging to GPR64 with %vreg0 in %vreg1
		RHS = %vreg0 [112r,128r:0)  0@112r
		LHS = %vreg1 [128r,416r:0)  0@128r
		merge %vreg1:0@128r into %vreg0:0@112r --> @112r
		erased:	128r	%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
		updated: 112B	%vreg1<def> = COPY %X0; GPR64:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [112r,416r:0)  0@112r
144B	%vreg3<def> = COPY %vreg2; GPR64:%vreg3,%vreg2
	Considering merging to GPR64 with %vreg2 in %vreg3
		RHS = %vreg2 [96r,144r:0)  0@96r
		LHS = %vreg3 [144r,432r:0)  0@144r
		merge %vreg3:0@144r into %vreg2:0@96r --> @96r
		erased:	144r	%vreg3<def> = COPY %vreg2; GPR64:%vreg3,%vreg2
		updated: 96B	%vreg3<def> = COPY %X1; GPR64:%vreg3
	Success: %vreg2 -> %vreg3
	Result = %vreg3 [96r,432r:0)  0@96r
160B	%vreg5<def> = COPY %vreg4; GPR64:%vreg5,%vreg4
	Considering merging to GPR64 with %vreg4 in %vreg5
		RHS = %vreg4 [80r,160r:0)  0@80r
		LHS = %vreg5 [160r,448r:0)  0@160r
		merge %vreg5:0@160r into %vreg4:0@80r --> @80r
		erased:	160r	%vreg5<def> = COPY %vreg4; GPR64:%vreg5,%vreg4
		updated: 80B	%vreg5<def> = COPY %X2; GPR64:%vreg5
	Success: %vreg4 -> %vreg5
	Result = %vreg5 [80r,448r:0)  0@80r
176B	%vreg7<def> = COPY %vreg6; GPR32:%vreg7,%vreg6
	Considering merging to GPR32 with %vreg6 in %vreg7
		RHS = %vreg6 [64r,176r:0)  0@64r
		LHS = %vreg7 [176r,464r:0)  0@176r
		merge %vreg7:0@176r into %vreg6:0@64r --> @64r
		erased:	176r	%vreg7<def> = COPY %vreg6; GPR32:%vreg7,%vreg6
		updated: 64B	%vreg7<def> = COPY %W3; GPR32:%vreg7
	Success: %vreg6 -> %vreg7
	Result = %vreg7 [64r,464r:0)  0@64r
192B	%vreg9<def> = COPY %vreg8; GPR32:%vreg9,%vreg8
	Considering merging to GPR32 with %vreg8 in %vreg9
		RHS = %vreg8 [48r,192r:0)  0@48r
		LHS = %vreg9 [192r,480r:0)  0@192r
		merge %vreg9:0@192r into %vreg8:0@48r --> @48r
		erased:	192r	%vreg9<def> = COPY %vreg8; GPR32:%vreg9,%vreg8
		updated: 48B	%vreg9<def> = COPY %W4; GPR32:%vreg9
	Success: %vreg8 -> %vreg9
	Result = %vreg9 [48r,480r:0)  0@48r
208B	%vreg11<def> = COPY %vreg10; GPR32:%vreg11,%vreg10
	Considering merging to GPR32 with %vreg10 in %vreg11
		RHS = %vreg10 [32r,208r:0)  0@32r
		LHS = %vreg11 [208r,496r:0)  0@208r
		merge %vreg11:0@208r into %vreg10:0@32r --> @32r
		erased:	208r	%vreg11<def> = COPY %vreg10; GPR32:%vreg11,%vreg10
		updated: 32B	%vreg11<def> = COPY %W5; GPR32:%vreg11
	Success: %vreg10 -> %vreg11
	Result = %vreg11 [32r,496r:0)  0@32r
256B	%vreg16<def> = COPY %vreg15; GPR64all:%vreg16 GPR64sp:%vreg15
	Considering merging to GPR64sp with %vreg15 in %vreg16
		RHS = %vreg15 [240r,256r:0)  0@240r
		LHS = %vreg16 [256r,304r:0)  0@256r
		merge %vreg16:0@256r into %vreg15:0@240r --> @240r
		erased:	256r	%vreg16<def> = COPY %vreg15; GPR64all:%vreg16 GPR64sp:%vreg15
		updated: 240B	%vreg16<def> = ADDXri %vreg14, <ga:@BZ2_bzBuffToBuffDecompress>[TF=34], 0; GPR64sp:%vreg16 GPR64common:%vreg14
	Success: %vreg15 -> %vreg16
	Result = %vreg16 [240r,304r:0)  0@240r
272B	%vreg17<def> = COPY %vreg88; GPR64all:%vreg17 GPR64:%vreg88
	Considering merging to GPR64 with %vreg88 in %vreg17
		RHS = %vreg88 [16r,2864r:0)  0@16r
		LHS = %vreg17 [272r,320r:0)  0@272r
		merge %vreg17:0@272r into %vreg88:0@16r --> @16r
		erased:	272r	%vreg17<def> = COPY %vreg88; GPR64all:%vreg17 GPR64:%vreg88
		updated: 16B	%vreg17<def> = COPY %LR; GPR64:%vreg17
		updated: 2864B	%X1<def> = COPY %vreg17; GPR64:%vreg17
	Success: %vreg88 -> %vreg17
	Result = %vreg17 [16r,2864r:0)  0@16r
2848B	%X0<def> = COPY %vreg87; GPR64sp:%vreg87
	Considering merging %vreg87 with %X0
	Can only merge into reserved registers.
2864B	%X1<def> = COPY %vreg17; GPR64:%vreg17
	Considering merging %vreg17 with %X1
	Can only merge into reserved registers.
304B	%X0<def> = COPY %vreg16; GPR64sp:%vreg16
	Considering merging %vreg16 with %X0
	Can only merge into reserved registers.
320B	%X1<def> = COPY %vreg17; GPR64:%vreg17
	Considering merging %vreg17 with %X1
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
W30 [0B,16r:0)[336r,336d:16)[384e,384d:8)[1120r,1120d:15)[1184e,1184d:7)[1536r,1536d:14)[1600e,1600d:6)[1952r,1952d:13)[2016e,2016d:5)[2208r,2208d:10)[2288e,2288d:4)[2416r,2416d:11)[2496e,2496d:3)[2624r,2624d:12)[2688e,2688d:2)[2880r,2880d:9)[2928e,2928d:1)  0@0B-phi 1@2928e 2@2688e 3@2496e 4@2288e 5@2016e 6@1600e 7@1184e 8@384e 9@2880r 10@2208r 11@2416r 12@2624r 13@1952r 14@1536r 15@1120r 16@336r
WZR [720r,720d:3)[832r,832d:2)[1744r,1744d:1)[2112r,2112d:0)  0@2112r 1@1744r 2@832r 3@720r
W0 [0B,112r:0)[304r,336r:15)[1072r,1120r:14)[1120r,1152r:7)[1520r,1536r:13)[1536r,1568r:6)[1936r,1952r:12)[1952r,1984r:5)[2192r,2208r:9)[2208r,2240r:2)[2400r,2416r:10)[2416r,2448r:3)[2608r,2624r:11)[2624r,2656r:4)[2848r,2880r:8)[2976r,2992r:1)  0@0B-phi 1@2976r 2@2208r 3@2416r 4@2624r 5@1952r 6@1536r 7@1120r 8@2848r 9@2192r 10@2400r 11@2608r 12@1936r 13@1520r 14@1072r 15@304r
W1 [0B,96r:0)[320r,336r:3)[1088r,1120r:1)[2864r,2880r:2)  0@0B-phi 1@1088r 2@2864r 3@320r
W2 [0B,80r:0)[1104r,1120r:1)  0@0B-phi 1@1104r
W3 [0B,64r:0)  0@0B-phi
W4 [0B,48r:0)  0@0B-phi
W5 [0B,32r:0)  0@0B-phi
%vreg1 [112r,416r:0)  0@112r
%vreg3 [96r,432r:0)  0@96r
%vreg5 [80r,448r:0)  0@80r
%vreg7 [64r,464r:0)  0@64r
%vreg9 [48r,480r:0)  0@48r
%vreg11 [32r,496r:0)  0@32r
%vreg13 [512r,528r:0)  0@512r
%vreg14 [224r,240r:0)  0@224r
%vreg16 [240r,304r:0)  0@240r
%vreg17 [16r,2864r:0)  0@16r
%vreg20 [560r,576r:0)  0@560r
%vreg22 [608r,624r:0)  0@608r
%vreg24 [656r,672r:0)  0@656r
%vreg26 [704r,720r:0)  0@704r
%vreg28 [768r,784r:0)  0@768r
%vreg30 [816r,832r:0)  0@816r
%vreg32 [1232r,1248r:0)  0@1232r
%vreg37 [1152r,1216r:0)  0@1152r
%vreg38 [1040r,1104r:0)  0@1040r
%vreg39 [1024r,1088r:0)  0@1024r
%vreg42 [1648r,1664r:0)  0@1648r
%vreg45 [1568r,1632r:0)  0@1568r
%vreg48 [1472r,1488r:0)  0@1472r
%vreg49 [1456r,1472r:0)  0@1456r
%vreg51 [1424r,1440r:0)  0@1424r
%vreg53 [1392r,1408r:0)  0@1392r
%vreg55 [1360r,1376r:0)  0@1360r
%vreg57 [1728r,1744r:0)  0@1728r
%vreg59 [1984r,1984d:0)  0@1984r
%vreg64 [1888r,1904r:0)  0@1888r
%vreg65 [1872r,1888r:0)  0@1872r
%vreg66 [1856r,1904r:0)  0@1856r
%vreg67 [1840r,1888r:0)  0@1840r
%vreg69 [2720r,2736r:0)  0@2720r
%vreg71 [2656r,2656d:0)  0@2656r
%vreg73 [2096r,2112r:0)  0@2096r
%vreg74 [2464r,2528r:0)  0@2464r
%vreg76 [2448r,2448d:0)  0@2448r
%vreg77 [2256r,2320r:0)  0@2256r
%vreg79 [2240r,2240d:0)  0@2240r
%vreg81 [1280r,1296r:0)  0@1280r
%vreg82 [880r,896r:0)  0@880r
%vreg84 [2960r,2976r:0)  0@2960r
%vreg85 [2768r,2784r:0)  0@2768r
%vreg87 [2784r,2848r:0)  0@2784r
RegMasks: 336r 1120r 1536r 1952r 2208r 2416r 2624r 2880r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzBuffToBuffDecompress: Post SSA
Frame Objects:
  fi#0: size=4, align=4, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=8, align=8, at location [SP]
  fi#3: size=8, align=8, at location [SP]
  fi#4: size=4, align=4, at location [SP]
  fi#5: size=4, align=4, at location [SP]
  fi#6: size=4, align=4, at location [SP]
  fi#7: size=80, align=8, at location [SP]
  fi#8: size=4, align=4, at location [SP]
Function Live Ins: %X0 in %vreg0, %X1 in %vreg2, %X2 in %vreg4, %W3 in %vreg6, %W4 in %vreg8, %W5 in %vreg10, %LR in %vreg18

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %X1 %X2 %W3 %W4 %W5 %LR
16B		%vreg17<def> = COPY %LR; GPR64:%vreg17
32B		%vreg11<def> = COPY %W5; GPR32:%vreg11
48B		%vreg9<def> = COPY %W4; GPR32:%vreg9
64B		%vreg7<def> = COPY %W3; GPR32:%vreg7
80B		%vreg5<def> = COPY %X2; GPR64:%vreg5
96B		%vreg3<def> = COPY %X1; GPR64:%vreg3
112B		%vreg1<def> = COPY %X0; GPR64:%vreg1
224B		%vreg14<def> = ADRP <ga:@BZ2_bzBuffToBuffDecompress>[TF=1]; GPR64common:%vreg14
240B		%vreg16<def> = ADDXri %vreg14, <ga:@BZ2_bzBuffToBuffDecompress>[TF=34], 0; GPR64sp:%vreg16 GPR64common:%vreg14
288B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
304B		%X0<def> = COPY %vreg16; GPR64sp:%vreg16
320B		%X1<def> = COPY %vreg17; GPR64:%vreg17
336B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
352B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
368B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
384B		STACKMAP 0, 0, %vreg1, 0, <fi#1>, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, %vreg9, 0, <fi#5>, 0, %vreg5, 0, <fi#3>, 0, %vreg7, 0, <fi#4>, 0, 0, <fi#7>, 0, %vreg11, 0, <fi#6>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack8](align=4) LD8[FixedStack0](align=4) LD8[FixedStack5](align=4) LD8[FixedStack3] LD8[FixedStack4](align=4) LD8[FixedStack7] LD8[FixedStack6](align=4) GPR64:%vreg1,%vreg3,%vreg5 GPR32:%vreg9,%vreg7,%vreg11
400B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
416B		STRXui %vreg1, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg1
432B		STRXui %vreg3, <fi#2>, 0; mem:ST8[FixedStack2] GPR64:%vreg3
448B		STRXui %vreg5, <fi#3>, 0; mem:ST8[FixedStack3] GPR64:%vreg5
464B		STRWui %vreg7, <fi#4>, 0; mem:ST4[FixedStack4] GPR32:%vreg7
480B		STRWui %vreg9, <fi#5>, 0; mem:ST4[FixedStack5] GPR32:%vreg9
496B		STRWui %vreg11, <fi#6>, 0; mem:ST4[FixedStack6] GPR32:%vreg11
512B		%vreg13<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg13
528B		CBZX %vreg13, <BB#7>; GPR64:%vreg13
	    Successors according to CFG: BB#7 BB#1

544B	BB#1: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#0
560B		%vreg20<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg20
576B		CBZX %vreg20, <BB#7>; GPR64:%vreg20
	    Successors according to CFG: BB#7 BB#2

592B	BB#2: derived from LLVM BB %lor.lhs.false.2
	    Predecessors according to CFG: BB#1
608B		%vreg22<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg22
624B		CBZX %vreg22, <BB#7>; GPR64:%vreg22
	    Successors according to CFG: BB#7 BB#3

640B	BB#3: derived from LLVM BB %lor.lhs.false.4
	    Predecessors according to CFG: BB#2
656B		%vreg24<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32:%vreg24
672B		CBZW %vreg24, <BB#5>; GPR32:%vreg24
	    Successors according to CFG: BB#5 BB#4

688B	BB#4: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#3
704B		%vreg26<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32common:%vreg26
720B		%WZR<def> = SUBSWri %vreg26, 1, 0, %NZCV<imp-def>; GPR32common:%vreg26
736B		Bcc 1, <BB#7>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#7 BB#5

752B	BB#5: derived from LLVM BB %lor.lhs.false.7
	    Predecessors according to CFG: BB#3 BB#4
768B		%vreg28<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg28
784B		TBNZW %vreg28, 31, <BB#7>; GPR32:%vreg28
	    Successors according to CFG: BB#7 BB#6

800B	BB#6: derived from LLVM BB %lor.lhs.false.9
	    Predecessors according to CFG: BB#5
816B		%vreg30<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32common:%vreg30
832B		%WZR<def> = SUBSWri %vreg30, 4, 0, %NZCV<imp-def>; GPR32common:%vreg30
848B		Bcc 13, <BB#8>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#8 BB#7

864B	BB#7: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0 BB#1 BB#2 BB#4 BB#5 BB#6
880B		%vreg82<def> = MOVi32imm 4294967294; GPR32:%vreg82
896B		STRWui %vreg82, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg82
912B		B <BB#19>
	    Successors according to CFG: BB#19

928B	BB#8: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#6
976B		STRXui %XZR, <fi#7>, 7; mem:ST80[FixedStack7(align=8)+7](align=1)
992B		STRXui %XZR, <fi#7>, 8; mem:ST80[FixedStack7+8](align=8)
1008B		STRXui %XZR, <fi#7>, 9; mem:ST80[FixedStack7(align=8)+9](align=1)
1024B		%vreg39<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg39
1040B		%vreg38<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32:%vreg38
1056B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1072B		%X0<def> = ADDXri <fi#7>, 0, 0
1088B		%W1<def> = COPY %vreg39; GPR32:%vreg39
1104B		%W2<def> = COPY %vreg38; GPR32:%vreg38
1120B		BL <ga:@BZ2_bzDecompressInit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %W2<imp-use>, %W0<imp-def>
1136B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1152B		%vreg37<def> = COPY %W0; GPR32:%vreg37
1168B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1184B		STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, 0, <fi#7>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack8](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3] LD8[FixedStack4](align=4) LD8[FixedStack7]
1200B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1216B		STRWui %vreg37, <fi#8>, 0; mem:ST4[FixedStack8] GPR32:%vreg37
1232B		%vreg32<def> = LDRWui <fi#8>, 0; mem:LD4[FixedStack8] GPR32:%vreg32
1248B		CBZW %vreg32, <BB#10>; GPR32:%vreg32
	    Successors according to CFG: BB#10 BB#9

1264B	BB#9: derived from LLVM BB %if.then.12
	    Predecessors according to CFG: BB#8
1280B		%vreg81<def> = LDRWui <fi#8>, 0; mem:LD4[FixedStack8] GPR32:%vreg81
1296B		STRWui %vreg81, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg81
1312B		B <BB#19>
	    Successors according to CFG: BB#19

1328B	BB#10: derived from LLVM BB %if.end.13
	    Predecessors according to CFG: BB#8
1360B		%vreg55<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg55
1376B		STRXui %vreg55, <fi#7>, 0; mem:ST80[FixedStack7](align=8) GPR64:%vreg55
1392B		%vreg53<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg53
1408B		STRXui %vreg53, <fi#7>, 3; mem:ST80[FixedStack7(align=8)+3](align=1) GPR64:%vreg53
1424B		%vreg51<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg51
1440B		STRWui %vreg51, <fi#7>, 2; mem:ST80[FixedStack7(align=8)+2](align=2) GPR32:%vreg51
1456B		%vreg49<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg49
1472B		%vreg48<def> = LDRWui %vreg49, 0; mem:LD4[%14] GPR32:%vreg48 GPR64common:%vreg49
1488B		STRWui %vreg48, <fi#7>, 8; mem:ST80[FixedStack7+8](align=8) GPR32:%vreg48
1504B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1520B		%X0<def> = ADDXri <fi#7>, 0, 0
1536B		BL <ga:@BZ2_bzDecompress>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
1552B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1568B		%vreg45<def> = COPY %W0; GPR32:%vreg45
1584B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1600B		STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, 0, <fi#7>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2] LD8[FixedStack8](align=4) LD8[FixedStack0](align=4) LD8[FixedStack7]
1616B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1632B		STRWui %vreg45, <fi#8>, 0; mem:ST4[FixedStack8] GPR32:%vreg45
1648B		%vreg42<def> = LDRWui <fi#8>, 0; mem:LD4[FixedStack8] GPR32:%vreg42
1664B		CBNZW %vreg42, <BB#12>; GPR32:%vreg42
	    Successors according to CFG: BB#12 BB#11

1680B	BB#11: derived from LLVM BB %if.then.16
	    Predecessors according to CFG: BB#10
1696B		B <BB#15>
	    Successors according to CFG: BB#15

1712B	BB#12: derived from LLVM BB %if.end.17
	    Predecessors according to CFG: BB#10
1728B		%vreg57<def> = LDRWui <fi#8>, 0; mem:LD4[FixedStack8] GPR32common:%vreg57
1744B		%WZR<def> = SUBSWri %vreg57, 4, 0, %NZCV<imp-def>; GPR32common:%vreg57
1760B		Bcc 0, <BB#14>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#14 BB#13

1776B	BB#13: derived from LLVM BB %if.then.19
	    Predecessors according to CFG: BB#12
1792B		B <BB#18>
	    Successors according to CFG: BB#18

1808B	BB#14: derived from LLVM BB %if.end.20
	    Predecessors according to CFG: BB#12
1840B		%vreg67<def> = LDRWui <fi#7>, 8; mem:LD80[FixedStack7+8](align=8) GPR32:%vreg67
1856B		%vreg66<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg66
1872B		%vreg65<def> = LDRWui %vreg66, 0; mem:LD4[%19] GPR32:%vreg65 GPR64common:%vreg66
1888B		%vreg64<def> = SUBWrr %vreg65, %vreg67; GPR32:%vreg64,%vreg65,%vreg67
1904B		STRWui %vreg64, %vreg66, 0; mem:ST4[%19] GPR32:%vreg64 GPR64common:%vreg66
1920B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1936B		%X0<def> = ADDXri <fi#7>, 0, 0
1952B		BL <ga:@BZ2_bzDecompressEnd>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
1968B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1984B		%vreg59<def,dead> = COPY %W0; GPR32all:%vreg59
2000B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2016B		STACKMAP 3, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
2032B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2048B		STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
2064B		B <BB#19>
	    Successors according to CFG: BB#19

2080B	BB#15: derived from LLVM BB %output_overflow_or_eof
	    Predecessors according to CFG: BB#11
2096B		%vreg73<def> = LDRWui <fi#7>, 8; mem:LD80[FixedStack7+8](align=8) GPR32common:%vreg73
2112B		%WZR<def> = SUBSWri %vreg73, 0, 0, %NZCV<imp-def>; GPR32common:%vreg73
2128B		Bcc 9, <BB#17>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#17 BB#16

2144B	BB#16: derived from LLVM BB %if.then.25
	    Predecessors according to CFG: BB#15
2176B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2192B		%X0<def> = ADDXri <fi#7>, 0, 0
2208B		BL <ga:@BZ2_bzDecompressEnd>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
2224B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2240B		%vreg79<def,dead> = COPY %W0; GPR32all:%vreg79
2256B		%vreg77<def> = MOVi32imm 4294967289; GPR32:%vreg77
2272B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2288B		STACKMAP 4, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
2304B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2320B		STRWui %vreg77, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg77
2336B		B <BB#19>
	    Successors according to CFG: BB#19

2352B	BB#17: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#15
2384B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2400B		%X0<def> = ADDXri <fi#7>, 0, 0
2416B		BL <ga:@BZ2_bzDecompressEnd>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
2432B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2448B		%vreg76<def,dead> = COPY %W0; GPR32all:%vreg76
2464B		%vreg74<def> = MOVi32imm 4294967288; GPR32:%vreg74
2480B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2496B		STACKMAP 5, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
2512B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2528B		STRWui %vreg74, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg74
2544B		B <BB#19>
	    Successors according to CFG: BB#19

2560B	BB#18: derived from LLVM BB %errhandler
	    Predecessors according to CFG: BB#13
2592B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2608B		%X0<def> = ADDXri <fi#7>, 0, 0
2624B		BL <ga:@BZ2_bzDecompressEnd>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
2640B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2656B		%vreg71<def,dead> = COPY %W0; GPR32all:%vreg71
2672B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2688B		STACKMAP 6, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack8](align=4) LD8[FixedStack0](align=4)
2704B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2720B		%vreg69<def> = LDRWui <fi#8>, 0; mem:LD4[FixedStack8] GPR32:%vreg69
2736B		STRWui %vreg69, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg69
	    Successors according to CFG: BB#19

2752B	BB#19: derived from LLVM BB %return
	    Predecessors according to CFG: BB#14 BB#18 BB#17 BB#16 BB#9 BB#7
2768B		%vreg85<def> = ADRP <ga:@BZ2_bzBuffToBuffDecompress>[TF=1]; GPR64common:%vreg85
2784B		%vreg87<def> = ADDXri %vreg85, <ga:@BZ2_bzBuffToBuffDecompress>[TF=34], 0; GPR64sp:%vreg87 GPR64common:%vreg85
2832B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2848B		%X0<def> = COPY %vreg87; GPR64sp:%vreg87
2864B		%X1<def> = COPY %vreg17; GPR64:%vreg17
2880B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
2896B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2912B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2928B		STACKMAP 7, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
2944B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2960B		%vreg84<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0] GPR32:%vreg84
2976B		%W0<def> = COPY %vreg84; GPR32:%vreg84
2992B		RET_ReallyLR %W0<imp-use>

# End machine code for function BZ2_bzBuffToBuffDecompress.

handleMove 1840B -> 1864B: %vreg67<def> = LDRWui <fi#7>, 8; mem:LD80[FixedStack7+8](align=8) GPR32:%vreg67
     %vreg67:	[1840r,1888r:0)  0@1840r
        -->	[1864r,1888r:0)  0@1864r
********** GREEDY REGISTER ALLOCATION **********
********** Function: BZ2_bzBuffToBuffDecompress
********** INTERVALS **********
W30 [0B,16r:0)[336r,336d:16)[384e,384d:8)[1120r,1120d:15)[1184e,1184d:7)[1536r,1536d:14)[1600e,1600d:6)[1952r,1952d:13)[2016e,2016d:5)[2208r,2208d:10)[2288e,2288d:4)[2416r,2416d:11)[2496e,2496d:3)[2624r,2624d:12)[2688e,2688d:2)[2880r,2880d:9)[2928e,2928d:1)  0@0B-phi 1@2928e 2@2688e 3@2496e 4@2288e 5@2016e 6@1600e 7@1184e 8@384e 9@2880r 10@2208r 11@2416r 12@2624r 13@1952r 14@1536r 15@1120r 16@336r
WZR [720r,720d:3)[832r,832d:2)[1744r,1744d:1)[2112r,2112d:0)  0@2112r 1@1744r 2@832r 3@720r
W0 [0B,112r:0)[304r,336r:15)[1072r,1120r:14)[1120r,1152r:7)[1520r,1536r:13)[1536r,1568r:6)[1936r,1952r:12)[1952r,1984r:5)[2192r,2208r:9)[2208r,2240r:2)[2400r,2416r:10)[2416r,2448r:3)[2608r,2624r:11)[2624r,2656r:4)[2848r,2880r:8)[2976r,2992r:1)  0@0B-phi 1@2976r 2@2208r 3@2416r 4@2624r 5@1952r 6@1536r 7@1120r 8@2848r 9@2192r 10@2400r 11@2608r 12@1936r 13@1520r 14@1072r 15@304r
W1 [0B,96r:0)[320r,336r:3)[1088r,1120r:1)[2864r,2880r:2)  0@0B-phi 1@1088r 2@2864r 3@320r
W2 [0B,80r:0)[1104r,1120r:1)  0@0B-phi 1@1104r
W3 [0B,64r:0)  0@0B-phi
W4 [0B,48r:0)  0@0B-phi
W5 [0B,32r:0)  0@0B-phi
%vreg1 [112r,416r:0)  0@112r
%vreg3 [96r,432r:0)  0@96r
%vreg5 [80r,448r:0)  0@80r
%vreg7 [64r,464r:0)  0@64r
%vreg9 [48r,480r:0)  0@48r
%vreg11 [32r,496r:0)  0@32r
%vreg13 [512r,528r:0)  0@512r
%vreg14 [224r,240r:0)  0@224r
%vreg16 [240r,304r:0)  0@240r
%vreg17 [16r,2864r:0)  0@16r
%vreg20 [560r,576r:0)  0@560r
%vreg22 [608r,624r:0)  0@608r
%vreg24 [656r,672r:0)  0@656r
%vreg26 [704r,720r:0)  0@704r
%vreg28 [768r,784r:0)  0@768r
%vreg30 [816r,832r:0)  0@816r
%vreg32 [1232r,1248r:0)  0@1232r
%vreg37 [1152r,1216r:0)  0@1152r
%vreg38 [1040r,1104r:0)  0@1040r
%vreg39 [1024r,1088r:0)  0@1024r
%vreg42 [1648r,1664r:0)  0@1648r
%vreg45 [1568r,1632r:0)  0@1568r
%vreg48 [1472r,1488r:0)  0@1472r
%vreg49 [1456r,1472r:0)  0@1456r
%vreg51 [1424r,1440r:0)  0@1424r
%vreg53 [1392r,1408r:0)  0@1392r
%vreg55 [1360r,1376r:0)  0@1360r
%vreg57 [1728r,1744r:0)  0@1728r
%vreg59 [1984r,1984d:0)  0@1984r
%vreg64 [1888r,1904r:0)  0@1888r
%vreg65 [1872r,1888r:0)  0@1872r
%vreg66 [1856r,1904r:0)  0@1856r
%vreg67 [1864r,1888r:0)  0@1864r
%vreg69 [2720r,2736r:0)  0@2720r
%vreg71 [2656r,2656d:0)  0@2656r
%vreg73 [2096r,2112r:0)  0@2096r
%vreg74 [2464r,2528r:0)  0@2464r
%vreg76 [2448r,2448d:0)  0@2448r
%vreg77 [2256r,2320r:0)  0@2256r
%vreg79 [2240r,2240d:0)  0@2240r
%vreg81 [1280r,1296r:0)  0@1280r
%vreg82 [880r,896r:0)  0@880r
%vreg84 [2960r,2976r:0)  0@2960r
%vreg85 [2768r,2784r:0)  0@2768r
%vreg87 [2784r,2848r:0)  0@2784r
RegMasks: 336r 1120r 1536r 1952r 2208r 2416r 2624r 2880r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzBuffToBuffDecompress: Post SSA
Frame Objects:
  fi#0: size=4, align=4, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=8, align=8, at location [SP]
  fi#3: size=8, align=8, at location [SP]
  fi#4: size=4, align=4, at location [SP]
  fi#5: size=4, align=4, at location [SP]
  fi#6: size=4, align=4, at location [SP]
  fi#7: size=80, align=8, at location [SP]
  fi#8: size=4, align=4, at location [SP]
Function Live Ins: %X0 in %vreg0, %X1 in %vreg2, %X2 in %vreg4, %W3 in %vreg6, %W4 in %vreg8, %W5 in %vreg10, %LR in %vreg18

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %X1 %X2 %W3 %W4 %W5 %LR
16B		%vreg17<def> = COPY %LR; GPR64:%vreg17
32B		%vreg11<def> = COPY %W5; GPR32:%vreg11
48B		%vreg9<def> = COPY %W4; GPR32:%vreg9
64B		%vreg7<def> = COPY %W3; GPR32:%vreg7
80B		%vreg5<def> = COPY %X2; GPR64:%vreg5
96B		%vreg3<def> = COPY %X1; GPR64:%vreg3
112B		%vreg1<def> = COPY %X0; GPR64:%vreg1
224B		%vreg14<def> = ADRP <ga:@BZ2_bzBuffToBuffDecompress>[TF=1]; GPR64common:%vreg14
240B		%vreg16<def> = ADDXri %vreg14, <ga:@BZ2_bzBuffToBuffDecompress>[TF=34], 0; GPR64sp:%vreg16 GPR64common:%vreg14
288B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
304B		%X0<def> = COPY %vreg16; GPR64sp:%vreg16
320B		%X1<def> = COPY %vreg17; GPR64:%vreg17
336B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
352B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
368B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
384B		STACKMAP 0, 0, %vreg1, 0, <fi#1>, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, %vreg9, 0, <fi#5>, 0, %vreg5, 0, <fi#3>, 0, %vreg7, 0, <fi#4>, 0, 0, <fi#7>, 0, %vreg11, 0, <fi#6>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack8](align=4) LD8[FixedStack0](align=4) LD8[FixedStack5](align=4) LD8[FixedStack3] LD8[FixedStack4](align=4) LD8[FixedStack7] LD8[FixedStack6](align=4) GPR64:%vreg1,%vreg3,%vreg5 GPR32:%vreg9,%vreg7,%vreg11
400B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
416B		STRXui %vreg1, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg1
432B		STRXui %vreg3, <fi#2>, 0; mem:ST8[FixedStack2] GPR64:%vreg3
448B		STRXui %vreg5, <fi#3>, 0; mem:ST8[FixedStack3] GPR64:%vreg5
464B		STRWui %vreg7, <fi#4>, 0; mem:ST4[FixedStack4] GPR32:%vreg7
480B		STRWui %vreg9, <fi#5>, 0; mem:ST4[FixedStack5] GPR32:%vreg9
496B		STRWui %vreg11, <fi#6>, 0; mem:ST4[FixedStack6] GPR32:%vreg11
512B		%vreg13<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg13
528B		CBZX %vreg13, <BB#7>; GPR64:%vreg13
	    Successors according to CFG: BB#7 BB#1

544B	BB#1: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#0
560B		%vreg20<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg20
576B		CBZX %vreg20, <BB#7>; GPR64:%vreg20
	    Successors according to CFG: BB#7 BB#2

592B	BB#2: derived from LLVM BB %lor.lhs.false.2
	    Predecessors according to CFG: BB#1
608B		%vreg22<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg22
624B		CBZX %vreg22, <BB#7>; GPR64:%vreg22
	    Successors according to CFG: BB#7 BB#3

640B	BB#3: derived from LLVM BB %lor.lhs.false.4
	    Predecessors according to CFG: BB#2
656B		%vreg24<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32:%vreg24
672B		CBZW %vreg24, <BB#5>; GPR32:%vreg24
	    Successors according to CFG: BB#5 BB#4

688B	BB#4: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#3
704B		%vreg26<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32common:%vreg26
720B		%WZR<def> = SUBSWri %vreg26, 1, 0, %NZCV<imp-def>; GPR32common:%vreg26
736B		Bcc 1, <BB#7>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#7 BB#5

752B	BB#5: derived from LLVM BB %lor.lhs.false.7
	    Predecessors according to CFG: BB#3 BB#4
768B		%vreg28<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg28
784B		TBNZW %vreg28, 31, <BB#7>; GPR32:%vreg28
	    Successors according to CFG: BB#7 BB#6

800B	BB#6: derived from LLVM BB %lor.lhs.false.9
	    Predecessors according to CFG: BB#5
816B		%vreg30<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32common:%vreg30
832B		%WZR<def> = SUBSWri %vreg30, 4, 0, %NZCV<imp-def>; GPR32common:%vreg30
848B		Bcc 13, <BB#8>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#8 BB#7

864B	BB#7: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0 BB#1 BB#2 BB#4 BB#5 BB#6
880B		%vreg82<def> = MOVi32imm 4294967294; GPR32:%vreg82
896B		STRWui %vreg82, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg82
912B		B <BB#19>
	    Successors according to CFG: BB#19

928B	BB#8: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#6
976B		STRXui %XZR, <fi#7>, 7; mem:ST80[FixedStack7(align=8)+7](align=1)
992B		STRXui %XZR, <fi#7>, 8; mem:ST80[FixedStack7+8](align=8)
1008B		STRXui %XZR, <fi#7>, 9; mem:ST80[FixedStack7(align=8)+9](align=1)
1024B		%vreg39<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg39
1040B		%vreg38<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32:%vreg38
1056B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1072B		%X0<def> = ADDXri <fi#7>, 0, 0
1088B		%W1<def> = COPY %vreg39; GPR32:%vreg39
1104B		%W2<def> = COPY %vreg38; GPR32:%vreg38
1120B		BL <ga:@BZ2_bzDecompressInit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %W2<imp-use>, %W0<imp-def>
1136B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1152B		%vreg37<def> = COPY %W0; GPR32:%vreg37
1168B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1184B		STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, 0, <fi#7>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack8](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3] LD8[FixedStack4](align=4) LD8[FixedStack7]
1200B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1216B		STRWui %vreg37, <fi#8>, 0; mem:ST4[FixedStack8] GPR32:%vreg37
1232B		%vreg32<def> = LDRWui <fi#8>, 0; mem:LD4[FixedStack8] GPR32:%vreg32
1248B		CBZW %vreg32, <BB#10>; GPR32:%vreg32
	    Successors according to CFG: BB#10 BB#9

1264B	BB#9: derived from LLVM BB %if.then.12
	    Predecessors according to CFG: BB#8
1280B		%vreg81<def> = LDRWui <fi#8>, 0; mem:LD4[FixedStack8] GPR32:%vreg81
1296B		STRWui %vreg81, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg81
1312B		B <BB#19>
	    Successors according to CFG: BB#19

1328B	BB#10: derived from LLVM BB %if.end.13
	    Predecessors according to CFG: BB#8
1360B		%vreg55<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg55
1376B		STRXui %vreg55, <fi#7>, 0; mem:ST80[FixedStack7](align=8) GPR64:%vreg55
1392B		%vreg53<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg53
1408B		STRXui %vreg53, <fi#7>, 3; mem:ST80[FixedStack7(align=8)+3](align=1) GPR64:%vreg53
1424B		%vreg51<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg51
1440B		STRWui %vreg51, <fi#7>, 2; mem:ST80[FixedStack7(align=8)+2](align=2) GPR32:%vreg51
1456B		%vreg49<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg49
1472B		%vreg48<def> = LDRWui %vreg49, 0; mem:LD4[%14] GPR32:%vreg48 GPR64common:%vreg49
1488B		STRWui %vreg48, <fi#7>, 8; mem:ST80[FixedStack7+8](align=8) GPR32:%vreg48
1504B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1520B		%X0<def> = ADDXri <fi#7>, 0, 0
1536B		BL <ga:@BZ2_bzDecompress>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
1552B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1568B		%vreg45<def> = COPY %W0; GPR32:%vreg45
1584B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1600B		STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, 0, <fi#7>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2] LD8[FixedStack8](align=4) LD8[FixedStack0](align=4) LD8[FixedStack7]
1616B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1632B		STRWui %vreg45, <fi#8>, 0; mem:ST4[FixedStack8] GPR32:%vreg45
1648B		%vreg42<def> = LDRWui <fi#8>, 0; mem:LD4[FixedStack8] GPR32:%vreg42
1664B		CBNZW %vreg42, <BB#12>; GPR32:%vreg42
	    Successors according to CFG: BB#12 BB#11

1680B	BB#11: derived from LLVM BB %if.then.16
	    Predecessors according to CFG: BB#10
1696B		B <BB#15>
	    Successors according to CFG: BB#15

1712B	BB#12: derived from LLVM BB %if.end.17
	    Predecessors according to CFG: BB#10
1728B		%vreg57<def> = LDRWui <fi#8>, 0; mem:LD4[FixedStack8] GPR32common:%vreg57
1744B		%WZR<def> = SUBSWri %vreg57, 4, 0, %NZCV<imp-def>; GPR32common:%vreg57
1760B		Bcc 0, <BB#14>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#14 BB#13

1776B	BB#13: derived from LLVM BB %if.then.19
	    Predecessors according to CFG: BB#12
1792B		B <BB#18>
	    Successors according to CFG: BB#18

1808B	BB#14: derived from LLVM BB %if.end.20
	    Predecessors according to CFG: BB#12
1856B		%vreg66<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg66
1864B		%vreg67<def> = LDRWui <fi#7>, 8; mem:LD80[FixedStack7+8](align=8) GPR32:%vreg67
1872B		%vreg65<def> = LDRWui %vreg66, 0; mem:LD4[%19] GPR32:%vreg65 GPR64common:%vreg66
1888B		%vreg64<def> = SUBWrr %vreg65, %vreg67; GPR32:%vreg64,%vreg65,%vreg67
1904B		STRWui %vreg64, %vreg66, 0; mem:ST4[%19] GPR32:%vreg64 GPR64common:%vreg66
1920B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1936B		%X0<def> = ADDXri <fi#7>, 0, 0
1952B		BL <ga:@BZ2_bzDecompressEnd>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
1968B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1984B		%vreg59<def,dead> = COPY %W0; GPR32all:%vreg59
2000B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2016B		STACKMAP 3, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
2032B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2048B		STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
2064B		B <BB#19>
	    Successors according to CFG: BB#19

2080B	BB#15: derived from LLVM BB %output_overflow_or_eof
	    Predecessors according to CFG: BB#11
2096B		%vreg73<def> = LDRWui <fi#7>, 8; mem:LD80[FixedStack7+8](align=8) GPR32common:%vreg73
2112B		%WZR<def> = SUBSWri %vreg73, 0, 0, %NZCV<imp-def>; GPR32common:%vreg73
2128B		Bcc 9, <BB#17>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#17 BB#16

2144B	BB#16: derived from LLVM BB %if.then.25
	    Predecessors according to CFG: BB#15
2176B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2192B		%X0<def> = ADDXri <fi#7>, 0, 0
2208B		BL <ga:@BZ2_bzDecompressEnd>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
2224B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2240B		%vreg79<def,dead> = COPY %W0; GPR32all:%vreg79
2256B		%vreg77<def> = MOVi32imm 4294967289; GPR32:%vreg77
2272B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2288B		STACKMAP 4, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
2304B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2320B		STRWui %vreg77, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg77
2336B		B <BB#19>
	    Successors according to CFG: BB#19

2352B	BB#17: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#15
2384B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2400B		%X0<def> = ADDXri <fi#7>, 0, 0
2416B		BL <ga:@BZ2_bzDecompressEnd>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
2432B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2448B		%vreg76<def,dead> = COPY %W0; GPR32all:%vreg76
2464B		%vreg74<def> = MOVi32imm 4294967288; GPR32:%vreg74
2480B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2496B		STACKMAP 5, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
2512B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2528B		STRWui %vreg74, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg74
2544B		B <BB#19>
	    Successors according to CFG: BB#19

2560B	BB#18: derived from LLVM BB %errhandler
	    Predecessors according to CFG: BB#13
2592B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2608B		%X0<def> = ADDXri <fi#7>, 0, 0
2624B		BL <ga:@BZ2_bzDecompressEnd>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
2640B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2656B		%vreg71<def,dead> = COPY %W0; GPR32all:%vreg71
2672B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2688B		STACKMAP 6, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack8](align=4) LD8[FixedStack0](align=4)
2704B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2720B		%vreg69<def> = LDRWui <fi#8>, 0; mem:LD4[FixedStack8] GPR32:%vreg69
2736B		STRWui %vreg69, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg69
	    Successors according to CFG: BB#19

2752B	BB#19: derived from LLVM BB %return
	    Predecessors according to CFG: BB#14 BB#18 BB#17 BB#16 BB#9 BB#7
2768B		%vreg85<def> = ADRP <ga:@BZ2_bzBuffToBuffDecompress>[TF=1]; GPR64common:%vreg85
2784B		%vreg87<def> = ADDXri %vreg85, <ga:@BZ2_bzBuffToBuffDecompress>[TF=34], 0; GPR64sp:%vreg87 GPR64common:%vreg85
2832B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2848B		%X0<def> = COPY %vreg87; GPR64sp:%vreg87
2864B		%X1<def> = COPY %vreg17; GPR64:%vreg17
2880B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
2896B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2912B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2928B		STACKMAP 7, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
2944B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2960B		%vreg84<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0] GPR32:%vreg84
2976B		%W0<def> = COPY %vreg84; GPR32:%vreg84
2992B		RET_ReallyLR %W0<imp-use>

# End machine code for function BZ2_bzBuffToBuffDecompress.


selectOrSplit GPR64:%vreg17 [16r,2864r:0)  0@16r w=9.328818e-04
hints: %X1
missed hint %X1
assigning %vreg17 to %X19: W19 [16r,2864r:0)  0@16r

selectOrSplit GPR32:%vreg11 [32r,496r:0)  0@32r w=3.506945e-03
hints: %W5
missed hint %W5
assigning %vreg11 to %W20: W20 [32r,496r:0)  0@32r

selectOrSplit GPR32:%vreg9 [48r,480r:0)  0@48r w=3.641827e-03
hints: %W4
missed hint %W4
assigning %vreg9 to %W21: W21 [48r,480r:0)  0@48r

selectOrSplit GPR32:%vreg7 [64r,464r:0)  0@64r w=3.787500e-03
hints: %W3
missed hint %W3
assigning %vreg7 to %W22: W22 [64r,464r:0)  0@64r

selectOrSplit GPR64:%vreg5 [80r,448r:0)  0@80r w=3.945312e-03
hints: %X2
missed hint %X2
assigning %vreg5 to %X23: W23 [80r,448r:0)  0@80r

selectOrSplit GPR64:%vreg3 [96r,432r:0)  0@96r w=4.116848e-03
hints: %X1
missed hint %X1
assigning %vreg3 to %X24: W24 [96r,432r:0)  0@96r

selectOrSplit GPR64:%vreg1 [112r,416r:0)  0@112r w=4.303977e-03
hints: %X0
missed hint %X0
assigning %vreg1 to %X25: W25 [112r,416r:0)  0@112r

selectOrSplit GPR64sp:%vreg16 [240r,304r:0)  0@240r w=4.353448e-03
hints: %X0
assigning %vreg16 to %X0: W0 [240r,304r:0)  0@240r

selectOrSplit GPR32:%vreg39 [1024r,1088r:0)  0@1024r w=1.004642e-04
hints: %W1
assigning %vreg39 to %W1: W1 [1024r,1088r:0)  0@1024r

selectOrSplit GPR32:%vreg38 [1040r,1104r:0)  0@1040r w=1.004642e-04
hints: %W2
assigning %vreg38 to %W2: W2 [1040r,1104r:0)  0@1040r

selectOrSplit GPR32:%vreg37 [1152r,1216r:0)  0@1152r w=1.004642e-04
hints: %W0
assigning %vreg37 to %W0: W0 [1152r,1216r:0)  0@1152r

selectOrSplit GPR32:%vreg45 [1568r,1632r:0)  0@1568r w=4.943476e-05
hints: %W0
assigning %vreg45 to %W0: W0 [1568r,1632r:0)  0@1568r

selectOrSplit GPR32all:%vreg59 [1984r,1984d:0)  0@1984r w=inf
hints: %W0
assigning %vreg59 to %W0: W0 [1984r,1984d:0)  0@1984r

selectOrSplit GPR32all:%vreg79 [2240r,2240d:0)  0@2240r w=inf
hints: %W0
assigning %vreg79 to %W0: W0 [2240r,2240d:0)  0@2240r

selectOrSplit GPR32all:%vreg76 [2448r,2448d:0)  0@2448r w=inf
hints: %W0
assigning %vreg76 to %W0: W0 [2448r,2448d:0)  0@2448r

selectOrSplit GPR32all:%vreg71 [2656r,2656d:0)  0@2656r w=inf
hints: %W0
assigning %vreg71 to %W0: W0 [2656r,2656d:0)  0@2656r

selectOrSplit GPR64sp:%vreg87 [2784r,2848r:0)  0@2784r w=4.353448e-03
hints: %X0
assigning %vreg87 to %X0: W0 [2784r,2848r:0)  0@2784r

selectOrSplit GPR32:%vreg84 [2960r,2976r:0)  0@2960r w=inf
hints: %W0
assigning %vreg84 to %W0: W0 [2960r,2976r:0)  0@2960r

selectOrSplit GPR64common:%vreg14 [224r,240r:0)  0@224r w=inf
assigning %vreg14 to %X8: W8 [224r,240r:0)  0@224r

selectOrSplit GPR64:%vreg13 [512r,528r:0)  0@512r w=inf
assigning %vreg13 to %X8: W8 [512r,528r:0)  0@512r

selectOrSplit GPR64:%vreg20 [560r,576r:0)  0@560r w=inf
assigning %vreg20 to %X8: W8 [560r,576r:0)  0@560r

selectOrSplit GPR64:%vreg22 [608r,624r:0)  0@608r w=inf
assigning %vreg22 to %X8: W8 [608r,624r:0)  0@608r

selectOrSplit GPR32:%vreg24 [656r,672r:0)  0@656r w=inf
assigning %vreg24 to %W8: W8 [656r,672r:0)  0@656r

selectOrSplit GPR32common:%vreg26 [704r,720r:0)  0@704r w=inf
assigning %vreg26 to %W8: W8 [704r,720r:0)  0@704r

selectOrSplit GPR32:%vreg28 [768r,784r:0)  0@768r w=inf
assigning %vreg28 to %W8: W8 [768r,784r:0)  0@768r

selectOrSplit GPR32common:%vreg30 [816r,832r:0)  0@816r w=inf
assigning %vreg30 to %W8: W8 [816r,832r:0)  0@816r

selectOrSplit GPR32:%vreg82 [880r,896r:0)  0@880r w=inf
assigning %vreg82 to %W8: W8 [880r,896r:0)  0@880r

selectOrSplit GPR32:%vreg32 [1232r,1248r:0)  0@1232r w=inf
assigning %vreg32 to %W8: W8 [1232r,1248r:0)  0@1232r

selectOrSplit GPR32:%vreg81 [1280r,1296r:0)  0@1280r w=inf
assigning %vreg81 to %W8: W8 [1280r,1296r:0)  0@1280r

selectOrSplit GPR64:%vreg55 [1360r,1376r:0)  0@1360r w=inf
assigning %vreg55 to %X8: W8 [1360r,1376r:0)  0@1360r

selectOrSplit GPR64:%vreg53 [1392r,1408r:0)  0@1392r w=inf
assigning %vreg53 to %X8: W8 [1392r,1408r:0)  0@1392r

selectOrSplit GPR32:%vreg51 [1424r,1440r:0)  0@1424r w=inf
assigning %vreg51 to %W8: W8 [1424r,1440r:0)  0@1424r

selectOrSplit GPR64common:%vreg49 [1456r,1472r:0)  0@1456r w=inf
assigning %vreg49 to %X8: W8 [1456r,1472r:0)  0@1456r

selectOrSplit GPR32:%vreg48 [1472r,1488r:0)  0@1472r w=inf
assigning %vreg48 to %W8: W8 [1472r,1488r:0)  0@1472r

selectOrSplit GPR32:%vreg42 [1648r,1664r:0)  0@1648r w=inf
assigning %vreg42 to %W8: W8 [1648r,1664r:0)  0@1648r

selectOrSplit GPR32common:%vreg57 [1728r,1744r:0)  0@1728r w=inf
assigning %vreg57 to %W8: W8 [1728r,1744r:0)  0@1728r

selectOrSplit GPR64common:%vreg66 [1856r,1904r:0)  0@1856r w=1.962323e-05
assigning %vreg66 to %X8: W8 [1856r,1904r:0)  0@1856r

selectOrSplit GPR32:%vreg67 [1864r,1888r:0)  0@1864r w=1.382266e-05
assigning %vreg67 to %W9: W9 [1864r,1888r:0)  0@1864r

selectOrSplit GPR32:%vreg65 [1872r,1888r:0)  0@1872r w=inf
assigning %vreg65 to %W10: W10 [1872r,1888r:0)  0@1872r

selectOrSplit GPR32:%vreg64 [1888r,1904r:0)  0@1888r w=inf
assigning %vreg64 to %W9: W9 [1888r,1904r:0)  0@1888r

selectOrSplit GPR32common:%vreg73 [2096r,2112r:0)  0@2096r w=inf
assigning %vreg73 to %W8: W8 [2096r,2112r:0)  0@2096r

selectOrSplit GPR32:%vreg77 [2256r,2320r:0)  0@2256r w=6.315523e-06
assigning %vreg77 to %W8: W8 [2256r,2320r:0)  0@2256r

selectOrSplit GPR32:%vreg74 [2464r,2528r:0)  0@2464r w=6.315523e-06
assigning %vreg74 to %W8: W8 [2464r,2528r:0)  0@2464r

selectOrSplit GPR32:%vreg69 [2720r,2736r:0)  0@2720r w=inf
assigning %vreg69 to %W8: W8 [2720r,2736r:0)  0@2720r

selectOrSplit GPR64common:%vreg85 [2768r,2784r:0)  0@2768r w=inf
assigning %vreg85 to %X8: W8 [2768r,2784r:0)  0@2768r

********** STACK TRANSFORMATION METADATA **********
********** Function: BZ2_bzBuffToBuffDecompress
********** REGISTER MAP **********
[%vreg1 -> %X25] GPR64
[%vreg3 -> %X24] GPR64
[%vreg5 -> %X23] GPR64
[%vreg7 -> %W22] GPR32
[%vreg9 -> %W21] GPR32
[%vreg11 -> %W20] GPR32
[%vreg13 -> %X8] GPR64
[%vreg14 -> %X8] GPR64common
[%vreg16 -> %X0] GPR64sp
[%vreg17 -> %X19] GPR64
[%vreg20 -> %X8] GPR64
[%vreg22 -> %X8] GPR64
[%vreg24 -> %W8] GPR32
[%vreg26 -> %W8] GPR32common
[%vreg28 -> %W8] GPR32
[%vreg30 -> %W8] GPR32common
[%vreg32 -> %W8] GPR32
[%vreg37 -> %W0] GPR32
[%vreg38 -> %W2] GPR32
[%vreg39 -> %W1] GPR32
[%vreg42 -> %W8] GPR32
[%vreg45 -> %W0] GPR32
[%vreg48 -> %W8] GPR32
[%vreg49 -> %X8] GPR64common
[%vreg51 -> %W8] GPR32
[%vreg53 -> %X8] GPR64
[%vreg55 -> %X8] GPR64
[%vreg57 -> %W8] GPR32common
[%vreg59 -> %W0] GPR32all
[%vreg64 -> %W9] GPR32
[%vreg65 -> %W10] GPR32
[%vreg66 -> %X8] GPR64common
[%vreg67 -> %W9] GPR32
[%vreg69 -> %W8] GPR32
[%vreg71 -> %W0] GPR32all
[%vreg73 -> %W8] GPR32common
[%vreg74 -> %W8] GPR32
[%vreg76 -> %W0] GPR32all
[%vreg77 -> %W8] GPR32
[%vreg79 -> %W0] GPR32all
[%vreg81 -> %W8] GPR32
[%vreg82 -> %W8] GPR32
[%vreg84 -> %W0] GPR32
[%vreg85 -> %X8] GPR64common
[%vreg87 -> %X0] GPR64sp


Stackmap 0:
  STACKMAP 0, 0, %vreg1, 0, <fi#1>, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, %vreg9, 0, <fi#5>, 0, %vreg5, 0, <fi#3>, 0, %vreg7, 0, <fi#4>, 0, 0, <fi#7>, 0, %vreg11, 0, <fi#6>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack8](align=4) LD8[FixedStack0](align=4) LD8[FixedStack5](align=4) LD8[FixedStack3] LD8[FixedStack4](align=4) LD8[FixedStack7] LD8[FixedStack6](align=4) GPR64:%vreg1,%vreg3,%vreg5 GPR32:%vreg9,%vreg7,%vreg11

i8* %dest: in register %X25 (vreg 1)
i8** %dest.addr: in stack slot 1 (size: 8)
i32* %destLen: in register %X24 (vreg 3)
i32** %destLen.addr: in stack slot 2 (size: 8)
i32* %ret: in stack slot 8 (size: 4)
i32* %retval: in stack slot 0 (size: 4)
i32 %small: in register %W21 (vreg 9)
i32* %small.addr: in stack slot 5 (size: 4)
i8* %source: in register %X23 (vreg 5)
i8** %source.addr: in stack slot 3 (size: 8)
i32 %sourceLen: in register %W22 (vreg 7)
i32* %sourceLen.addr: in stack slot 4 (size: 4)
%struct.bz_stream* %strm: in stack slot 7 (size: 80)
i32 %verbosity: in register %W20 (vreg 11)
i32* %verbosity.addr: in stack slot 6 (size: 4)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, 0, <fi#7>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack8](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3] LD8[FixedStack4](align=4) LD8[FixedStack7]

i8** %dest.addr: in stack slot 1 (size: 8)
i32** %destLen.addr: in stack slot 2 (size: 8)
i32* %ret: in stack slot 8 (size: 4)
i32* %retval: in stack slot 0 (size: 4)
i8** %source.addr: in stack slot 3 (size: 8)
i32* %sourceLen.addr: in stack slot 4 (size: 4)
%struct.bz_stream* %strm: in stack slot 7 (size: 80)

Duplicate operand locations:


Stackmap 2:
  STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, 0, <fi#7>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2] LD8[FixedStack8](align=4) LD8[FixedStack0](align=4) LD8[FixedStack7]

i32** %destLen.addr: in stack slot 2 (size: 8)
i32* %ret: in stack slot 8 (size: 4)
i32* %retval: in stack slot 0 (size: 4)
%struct.bz_stream* %strm: in stack slot 7 (size: 80)

Duplicate operand locations:


Stackmap 3:
  STACKMAP 3, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)

i32* %retval: in stack slot 0 (size: 4)

Duplicate operand locations:


Stackmap 4:
  STACKMAP 4, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)

i32* %retval: in stack slot 0 (size: 4)

Duplicate operand locations:


Stackmap 5:
  STACKMAP 5, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)

i32* %retval: in stack slot 0 (size: 4)

Duplicate operand locations:


Stackmap 6:
  STACKMAP 6, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack8](align=4) LD8[FixedStack0](align=4)

i32* %ret: in stack slot 8 (size: 4)
i32* %retval: in stack slot 0 (size: 4)

Duplicate operand locations:


Stackmap 7:
  STACKMAP 7, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)

i32* %retval: in stack slot 0 (size: 4)

Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, %vreg1, 0, <fi#1>, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, %vreg9, 0, <fi#5>, 0, %vreg5, 0, <fi#3>, 0, %vreg7, 0, <fi#4>, 0, 0, <fi#7>, 0, %vreg11, 0, <fi#6>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack8](align=4) LD8[FixedStack0](align=4) LD8[FixedStack5](align=4) LD8[FixedStack3] LD8[FixedStack4](align=4) LD8[FixedStack7] LD8[FixedStack6](align=4) GPR64:%vreg1,%vreg3,%vreg5 GPR32:%vreg9,%vreg7,%vreg11
  -> Call instruction SlotIndex 336B, searching vregs 0 -> 89 and stack slots 0 -> 9
    + vreg17 is live in register but not in stackmap
      Defining instruction: %vreg17<def> = COPY %LR; GPR64:%vreg17
      Value: generated value, 1 instruction(s)

  STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, 0, <fi#7>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack8](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3] LD8[FixedStack4](align=4) LD8[FixedStack7]
  -> Call instruction SlotIndex 1120B, searching vregs 0 -> 89 and stack slots 0 -> 9
    + vreg17 is live in register but not in stackmap
      Defining instruction: %vreg17<def> = COPY %LR; GPR64:%vreg17
      Value: generated value, 1 instruction(s)

  STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, 0, <fi#7>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2] LD8[FixedStack8](align=4) LD8[FixedStack0](align=4) LD8[FixedStack7]
  -> Call instruction SlotIndex 1536B, searching vregs 0 -> 89 and stack slots 0 -> 9
    + vreg17 is live in register but not in stackmap
      Defining instruction: %vreg17<def> = COPY %LR; GPR64:%vreg17
      Value: generated value, 1 instruction(s)

  STACKMAP 3, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
  -> Call instruction SlotIndex 1952B, searching vregs 0 -> 89 and stack slots 0 -> 9
    + vreg17 is live in register but not in stackmap
      Defining instruction: %vreg17<def> = COPY %LR; GPR64:%vreg17
      Value: generated value, 1 instruction(s)

  STACKMAP 4, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
  -> Call instruction SlotIndex 2208B, searching vregs 0 -> 89 and stack slots 0 -> 9
    + vreg17 is live in register but not in stackmap
      Defining instruction: %vreg17<def> = COPY %LR; GPR64:%vreg17
      Value: generated value, 1 instruction(s)

  STACKMAP 5, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
  -> Call instruction SlotIndex 2416B, searching vregs 0 -> 89 and stack slots 0 -> 9
    + vreg17 is live in register but not in stackmap
      Defining instruction: %vreg17<def> = COPY %LR; GPR64:%vreg17
      Value: generated value, 1 instruction(s)

  STACKMAP 6, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack8](align=4) LD8[FixedStack0](align=4)
  -> Call instruction SlotIndex 2624B, searching vregs 0 -> 89 and stack slots 0 -> 9
    + vreg17 is live in register but not in stackmap
      Defining instruction: %vreg17<def> = COPY %LR; GPR64:%vreg17
      Value: generated value, 1 instruction(s)

  STACKMAP 7, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
  -> Call instruction SlotIndex 2880B, searching vregs 0 -> 89 and stack slots 0 -> 9

********** REWRITE VIRTUAL REGISTERS **********
********** Function: BZ2_bzBuffToBuffDecompress
********** REGISTER MAP **********
[%vreg1 -> %X25] GPR64
[%vreg3 -> %X24] GPR64
[%vreg5 -> %X23] GPR64
[%vreg7 -> %W22] GPR32
[%vreg9 -> %W21] GPR32
[%vreg11 -> %W20] GPR32
[%vreg13 -> %X8] GPR64
[%vreg14 -> %X8] GPR64common
[%vreg16 -> %X0] GPR64sp
[%vreg17 -> %X19] GPR64
[%vreg20 -> %X8] GPR64
[%vreg22 -> %X8] GPR64
[%vreg24 -> %W8] GPR32
[%vreg26 -> %W8] GPR32common
[%vreg28 -> %W8] GPR32
[%vreg30 -> %W8] GPR32common
[%vreg32 -> %W8] GPR32
[%vreg37 -> %W0] GPR32
[%vreg38 -> %W2] GPR32
[%vreg39 -> %W1] GPR32
[%vreg42 -> %W8] GPR32
[%vreg45 -> %W0] GPR32
[%vreg48 -> %W8] GPR32
[%vreg49 -> %X8] GPR64common
[%vreg51 -> %W8] GPR32
[%vreg53 -> %X8] GPR64
[%vreg55 -> %X8] GPR64
[%vreg57 -> %W8] GPR32common
[%vreg59 -> %W0] GPR32all
[%vreg64 -> %W9] GPR32
[%vreg65 -> %W10] GPR32
[%vreg66 -> %X8] GPR64common
[%vreg67 -> %W9] GPR32
[%vreg69 -> %W8] GPR32
[%vreg71 -> %W0] GPR32all
[%vreg73 -> %W8] GPR32common
[%vreg74 -> %W8] GPR32
[%vreg76 -> %W0] GPR32all
[%vreg77 -> %W8] GPR32
[%vreg79 -> %W0] GPR32all
[%vreg81 -> %W8] GPR32
[%vreg82 -> %W8] GPR32
[%vreg84 -> %W0] GPR32
[%vreg85 -> %X8] GPR64common
[%vreg87 -> %X0] GPR64sp

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %LR %W3 %W4 %W5 %X0 %X1 %X2
16B		%vreg17<def> = COPY %LR; GPR64:%vreg17
32B		%vreg11<def> = COPY %W5; GPR32:%vreg11
48B		%vreg9<def> = COPY %W4; GPR32:%vreg9
64B		%vreg7<def> = COPY %W3; GPR32:%vreg7
80B		%vreg5<def> = COPY %X2; GPR64:%vreg5
96B		%vreg3<def> = COPY %X1; GPR64:%vreg3
112B		%vreg1<def> = COPY %X0; GPR64:%vreg1
224B		%vreg14<def> = ADRP <ga:@BZ2_bzBuffToBuffDecompress>[TF=1]; GPR64common:%vreg14
240B		%vreg16<def> = ADDXri %vreg14<kill>, <ga:@BZ2_bzBuffToBuffDecompress>[TF=34], 0; GPR64sp:%vreg16 GPR64common:%vreg14
288B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
304B		%X0<def> = COPY %vreg16<kill>; GPR64sp:%vreg16
320B		%X1<def> = COPY %vreg17; GPR64:%vreg17
336B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
352B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
368B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
384B		STACKMAP 0, 0, %vreg1, 0, <fi#1>, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, %vreg9, 0, <fi#5>, 0, %vreg5, 0, <fi#3>, 0, %vreg7, 0, <fi#4>, 0, 0, <fi#7>, 0, %vreg11, 0, <fi#6>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack8](align=4) LD8[FixedStack0](align=4) LD8[FixedStack5](align=4) LD8[FixedStack3] LD8[FixedStack4](align=4) LD8[FixedStack7] LD8[FixedStack6](align=4) GPR64:%vreg1,%vreg3,%vreg5 GPR32:%vreg9,%vreg7,%vreg11
400B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
416B		STRXui %vreg1<kill>, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg1
432B		STRXui %vreg3<kill>, <fi#2>, 0; mem:ST8[FixedStack2] GPR64:%vreg3
448B		STRXui %vreg5<kill>, <fi#3>, 0; mem:ST8[FixedStack3] GPR64:%vreg5
464B		STRWui %vreg7<kill>, <fi#4>, 0; mem:ST4[FixedStack4] GPR32:%vreg7
480B		STRWui %vreg9<kill>, <fi#5>, 0; mem:ST4[FixedStack5] GPR32:%vreg9
496B		STRWui %vreg11<kill>, <fi#6>, 0; mem:ST4[FixedStack6] GPR32:%vreg11
512B		%vreg13<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg13
528B		CBZX %vreg13<kill>, <BB#7>; GPR64:%vreg13
	    Successors according to CFG: BB#7 BB#1
> %X19<def> = COPY %LR
> %W20<def> = COPY %W5
> %W21<def> = COPY %W4
> %W22<def> = COPY %W3
> %X23<def> = COPY %X2
> %X24<def> = COPY %X1
> %X25<def> = COPY %X0
> %X8<def> = ADRP <ga:@BZ2_bzBuffToBuffDecompress>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@BZ2_bzBuffToBuffDecompress>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19
> BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 0, 0, %X25, 0, <fi#1>, 0, %X24, 0, <fi#2>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, %W21, 0, <fi#5>, 0, %X23, 0, <fi#3>, 0, %W22, 0, <fi#4>, 0, 0, <fi#7>, 0, %W20, 0, <fi#6>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack8](align=4) LD8[FixedStack0](align=4) LD8[FixedStack5](align=4) LD8[FixedStack3] LD8[FixedStack4](align=4) LD8[FixedStack7] LD8[FixedStack6](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRXui %X25<kill>, <fi#1>, 0; mem:ST8[FixedStack1]
> STRXui %X24<kill>, <fi#2>, 0; mem:ST8[FixedStack2]
> STRXui %X23<kill>, <fi#3>, 0; mem:ST8[FixedStack3]
> STRWui %W22<kill>, <fi#4>, 0; mem:ST4[FixedStack4]
> STRWui %W21<kill>, <fi#5>, 0; mem:ST4[FixedStack5]
> STRWui %W20<kill>, <fi#6>, 0; mem:ST4[FixedStack6]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> CBZX %X8<kill>, <BB#7>
544B	BB#1: derived from LLVM BB %lor.lhs.false
	    Live Ins: %X19
	    Predecessors according to CFG: BB#0
560B		%vreg20<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg20
576B		CBZX %vreg20<kill>, <BB#7>; GPR64:%vreg20
	    Successors according to CFG: BB#7 BB#2
> %X8<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2]
> CBZX %X8<kill>, <BB#7>
592B	BB#2: derived from LLVM BB %lor.lhs.false.2
	    Live Ins: %X19
	    Predecessors according to CFG: BB#1
608B		%vreg22<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg22
624B		CBZX %vreg22<kill>, <BB#7>; GPR64:%vreg22
	    Successors according to CFG: BB#7 BB#3
> %X8<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> CBZX %X8<kill>, <BB#7>
640B	BB#3: derived from LLVM BB %lor.lhs.false.4
	    Live Ins: %X19
	    Predecessors according to CFG: BB#2
656B		%vreg24<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32:%vreg24
672B		CBZW %vreg24<kill>, <BB#5>; GPR32:%vreg24
	    Successors according to CFG: BB#5 BB#4
> %W8<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5]
> CBZW %W8<kill>, <BB#5>
688B	BB#4: derived from LLVM BB %land.lhs.true
	    Live Ins: %X19
	    Predecessors according to CFG: BB#3
704B		%vreg26<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32common:%vreg26
720B		%WZR<def> = SUBSWri %vreg26<kill>, 1, 0, %NZCV<imp-def>; GPR32common:%vreg26
736B		Bcc 1, <BB#7>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#7 BB#5
> %W8<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5]
> %WZR<def> = SUBSWri %W8<kill>, 1, 0, %NZCV<imp-def>
> Bcc 1, <BB#7>, %NZCV<imp-use,kill>
752B	BB#5: derived from LLVM BB %lor.lhs.false.7
	    Live Ins: %X19
	    Predecessors according to CFG: BB#3 BB#4
768B		%vreg28<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg28
784B		TBNZW %vreg28<kill>, 31, <BB#7>; GPR32:%vreg28
	    Successors according to CFG: BB#7 BB#6
> %W8<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6]
> TBNZW %W8<kill>, 31, <BB#7>
800B	BB#6: derived from LLVM BB %lor.lhs.false.9
	    Live Ins: %X19
	    Predecessors according to CFG: BB#5
816B		%vreg30<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32common:%vreg30
832B		%WZR<def> = SUBSWri %vreg30<kill>, 4, 0, %NZCV<imp-def>; GPR32common:%vreg30
848B		Bcc 13, <BB#8>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#8 BB#7
> %W8<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6]
> %WZR<def> = SUBSWri %W8<kill>, 4, 0, %NZCV<imp-def>
> Bcc 13, <BB#8>, %NZCV<imp-use,kill>
864B	BB#7: derived from LLVM BB %if.then
	    Live Ins: %X19
	    Predecessors according to CFG: BB#0 BB#1 BB#2 BB#4 BB#5 BB#6
880B		%vreg82<def> = MOVi32imm 4294967294; GPR32:%vreg82
896B		STRWui %vreg82<kill>, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg82
912B		B <BB#19>
	    Successors according to CFG: BB#19
> %W8<def> = MOVi32imm 4294967294
> STRWui %W8<kill>, <fi#0>, 0; mem:ST4[FixedStack0]
> B <BB#19>
928B	BB#8: derived from LLVM BB %if.end
	    Live Ins: %X19
	    Predecessors according to CFG: BB#6
976B		STRXui %XZR, <fi#7>, 7; mem:ST80[FixedStack7(align=8)+7](align=1)
992B		STRXui %XZR, <fi#7>, 8; mem:ST80[FixedStack7+8](align=8)
1008B		STRXui %XZR, <fi#7>, 9; mem:ST80[FixedStack7(align=8)+9](align=1)
1024B		%vreg39<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6] GPR32:%vreg39
1040B		%vreg38<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32:%vreg38
1056B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1072B		%X0<def> = ADDXri <fi#7>, 0, 0
1088B		%W1<def> = COPY %vreg39<kill>; GPR32:%vreg39
1104B		%W2<def> = COPY %vreg38<kill>; GPR32:%vreg38
1120B		BL <ga:@BZ2_bzDecompressInit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %W2<imp-use>, %W0<imp-def>
1136B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1152B		%vreg37<def> = COPY %W0; GPR32:%vreg37
1168B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1184B		STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, 0, <fi#7>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack8](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3] LD8[FixedStack4](align=4) LD8[FixedStack7]
1200B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1216B		STRWui %vreg37<kill>, <fi#8>, 0; mem:ST4[FixedStack8] GPR32:%vreg37
1232B		%vreg32<def> = LDRWui <fi#8>, 0; mem:LD4[FixedStack8] GPR32:%vreg32
1248B		CBZW %vreg32<kill>, <BB#10>; GPR32:%vreg32
	    Successors according to CFG: BB#10 BB#9
> STRXui %XZR, <fi#7>, 7; mem:ST80[FixedStack7(align=8)+7](align=1)
> STRXui %XZR, <fi#7>, 8; mem:ST80[FixedStack7+8](align=8)
> STRXui %XZR, <fi#7>, 9; mem:ST80[FixedStack7(align=8)+9](align=1)
> %W1<def> = LDRWui <fi#6>, 0; mem:LD4[FixedStack6]
> %W2<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = ADDXri <fi#7>, 0, 0
> %W1<def> = COPY %W1<kill>
Deleting identity copy.
> %W2<def> = COPY %W2<kill>
Deleting identity copy.
> BL <ga:@BZ2_bzDecompressInit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %W2<imp-use>, %W0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = COPY %W0
Deleting identity copy.
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, 0, <fi#7>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack8](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3] LD8[FixedStack4](align=4) LD8[FixedStack7]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRWui %W0<kill>, <fi#8>, 0; mem:ST4[FixedStack8]
> %W8<def> = LDRWui <fi#8>, 0; mem:LD4[FixedStack8]
> CBZW %W8<kill>, <BB#10>
1264B	BB#9: derived from LLVM BB %if.then.12
	    Live Ins: %X19
	    Predecessors according to CFG: BB#8
1280B		%vreg81<def> = LDRWui <fi#8>, 0; mem:LD4[FixedStack8] GPR32:%vreg81
1296B		STRWui %vreg81<kill>, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg81
1312B		B <BB#19>
	    Successors according to CFG: BB#19
> %W8<def> = LDRWui <fi#8>, 0; mem:LD4[FixedStack8]
> STRWui %W8<kill>, <fi#0>, 0; mem:ST4[FixedStack0]
> B <BB#19>
1328B	BB#10: derived from LLVM BB %if.end.13
	    Live Ins: %X19
	    Predecessors according to CFG: BB#8
1360B		%vreg55<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg55
1376B		STRXui %vreg55<kill>, <fi#7>, 0; mem:ST80[FixedStack7](align=8) GPR64:%vreg55
1392B		%vreg53<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg53
1408B		STRXui %vreg53<kill>, <fi#7>, 3; mem:ST80[FixedStack7(align=8)+3](align=1) GPR64:%vreg53
1424B		%vreg51<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg51
1440B		STRWui %vreg51<kill>, <fi#7>, 2; mem:ST80[FixedStack7(align=8)+2](align=2) GPR32:%vreg51
1456B		%vreg49<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg49
1472B		%vreg48<def> = LDRWui %vreg49<kill>, 0; mem:LD4[%14] GPR32:%vreg48 GPR64common:%vreg49
1488B		STRWui %vreg48<kill>, <fi#7>, 8; mem:ST80[FixedStack7+8](align=8) GPR32:%vreg48
1504B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1520B		%X0<def> = ADDXri <fi#7>, 0, 0
1536B		BL <ga:@BZ2_bzDecompress>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
1552B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1568B		%vreg45<def> = COPY %W0; GPR32:%vreg45
1584B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1600B		STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, 0, <fi#7>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2] LD8[FixedStack8](align=4) LD8[FixedStack0](align=4) LD8[FixedStack7]
1616B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1632B		STRWui %vreg45<kill>, <fi#8>, 0; mem:ST4[FixedStack8] GPR32:%vreg45
1648B		%vreg42<def> = LDRWui <fi#8>, 0; mem:LD4[FixedStack8] GPR32:%vreg42
1664B		CBNZW %vreg42<kill>, <BB#12>; GPR32:%vreg42
	    Successors according to CFG: BB#12 BB#11
> %X8<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> STRXui %X8<kill>, <fi#7>, 0; mem:ST80[FixedStack7](align=8)
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRXui %X8<kill>, <fi#7>, 3; mem:ST80[FixedStack7(align=8)+3](align=1)
> %W8<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4]
> STRWui %W8<kill>, <fi#7>, 2; mem:ST80[FixedStack7(align=8)+2](align=2)
> %X8<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2]
> %W8<def> = LDRWui %X8<kill>, 0; mem:LD4[%14]
> STRWui %W8<kill>, <fi#7>, 8; mem:ST80[FixedStack7+8](align=8)
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = ADDXri <fi#7>, 0, 0
> BL <ga:@BZ2_bzDecompress>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = COPY %W0
Deleting identity copy.
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, 0, <fi#7>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2] LD8[FixedStack8](align=4) LD8[FixedStack0](align=4) LD8[FixedStack7]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRWui %W0<kill>, <fi#8>, 0; mem:ST4[FixedStack8]
> %W8<def> = LDRWui <fi#8>, 0; mem:LD4[FixedStack8]
> CBNZW %W8<kill>, <BB#12>
1680B	BB#11: derived from LLVM BB %if.then.16
	    Live Ins: %X19
	    Predecessors according to CFG: BB#10
1696B		B <BB#15>
	    Successors according to CFG: BB#15
> B <BB#15>
1712B	BB#12: derived from LLVM BB %if.end.17
	    Live Ins: %X19
	    Predecessors according to CFG: BB#10
1728B		%vreg57<def> = LDRWui <fi#8>, 0; mem:LD4[FixedStack8] GPR32common:%vreg57
1744B		%WZR<def> = SUBSWri %vreg57<kill>, 4, 0, %NZCV<imp-def>; GPR32common:%vreg57
1760B		Bcc 0, <BB#14>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#14 BB#13
> %W8<def> = LDRWui <fi#8>, 0; mem:LD4[FixedStack8]
> %WZR<def> = SUBSWri %W8<kill>, 4, 0, %NZCV<imp-def>
> Bcc 0, <BB#14>, %NZCV<imp-use,kill>
1776B	BB#13: derived from LLVM BB %if.then.19
	    Live Ins: %X19
	    Predecessors according to CFG: BB#12
1792B		B <BB#18>
	    Successors according to CFG: BB#18
> B <BB#18>
1808B	BB#14: derived from LLVM BB %if.end.20
	    Live Ins: %X19
	    Predecessors according to CFG: BB#12
1856B		%vreg66<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64common:%vreg66
1864B		%vreg67<def> = LDRWui <fi#7>, 8; mem:LD80[FixedStack7+8](align=8) GPR32:%vreg67
1872B		%vreg65<def> = LDRWui %vreg66, 0; mem:LD4[%19] GPR32:%vreg65 GPR64common:%vreg66
1888B		%vreg64<def> = SUBWrr %vreg65<kill>, %vreg67<kill>; GPR32:%vreg64,%vreg65,%vreg67
1904B		STRWui %vreg64<kill>, %vreg66<kill>, 0; mem:ST4[%19] GPR32:%vreg64 GPR64common:%vreg66
1920B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1936B		%X0<def> = ADDXri <fi#7>, 0, 0
1952B		BL <ga:@BZ2_bzDecompressEnd>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
1968B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1984B		%vreg59<def,dead> = COPY %W0; GPR32all:%vreg59
2000B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2016B		STACKMAP 3, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
2032B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2048B		STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
2064B		B <BB#19>
	    Successors according to CFG: BB#19
> %X8<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2]
> %W9<def> = LDRWui <fi#7>, 8; mem:LD80[FixedStack7+8](align=8)
> %W10<def> = LDRWui %X8, 0; mem:LD4[%19]
> %W9<def> = SUBWrr %W10<kill>, %W9<kill>
> STRWui %W9<kill>, %X8<kill>, 0; mem:ST4[%19]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = ADDXri <fi#7>, 0, 0
> BL <ga:@BZ2_bzDecompressEnd>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def,dead> = COPY %W0
Deleting identity copy.
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 3, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
> B <BB#19>
2080B	BB#15: derived from LLVM BB %output_overflow_or_eof
	    Live Ins: %X19
	    Predecessors according to CFG: BB#11
2096B		%vreg73<def> = LDRWui <fi#7>, 8; mem:LD80[FixedStack7+8](align=8) GPR32common:%vreg73
2112B		%WZR<def> = SUBSWri %vreg73<kill>, 0, 0, %NZCV<imp-def>; GPR32common:%vreg73
2128B		Bcc 9, <BB#17>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#17 BB#16
> %W8<def> = LDRWui <fi#7>, 8; mem:LD80[FixedStack7+8](align=8)
> %WZR<def> = SUBSWri %W8<kill>, 0, 0, %NZCV<imp-def>
> Bcc 9, <BB#17>, %NZCV<imp-use,kill>
2144B	BB#16: derived from LLVM BB %if.then.25
	    Live Ins: %X19
	    Predecessors according to CFG: BB#15
2176B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2192B		%X0<def> = ADDXri <fi#7>, 0, 0
2208B		BL <ga:@BZ2_bzDecompressEnd>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
2224B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2240B		%vreg79<def,dead> = COPY %W0; GPR32all:%vreg79
2256B		%vreg77<def> = MOVi32imm 4294967289; GPR32:%vreg77
2272B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2288B		STACKMAP 4, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
2304B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2320B		STRWui %vreg77<kill>, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg77
2336B		B <BB#19>
	    Successors according to CFG: BB#19
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = ADDXri <fi#7>, 0, 0
> BL <ga:@BZ2_bzDecompressEnd>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def,dead> = COPY %W0
Deleting identity copy.
> %W8<def> = MOVi32imm 4294967289
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 4, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRWui %W8<kill>, <fi#0>, 0; mem:ST4[FixedStack0]
> B <BB#19>
2352B	BB#17: derived from LLVM BB %if.else
	    Live Ins: %X19
	    Predecessors according to CFG: BB#15
2384B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2400B		%X0<def> = ADDXri <fi#7>, 0, 0
2416B		BL <ga:@BZ2_bzDecompressEnd>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
2432B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2448B		%vreg76<def,dead> = COPY %W0; GPR32all:%vreg76
2464B		%vreg74<def> = MOVi32imm 4294967288; GPR32:%vreg74
2480B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2496B		STACKMAP 5, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
2512B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2528B		STRWui %vreg74<kill>, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg74
2544B		B <BB#19>
	    Successors according to CFG: BB#19
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = ADDXri <fi#7>, 0, 0
> BL <ga:@BZ2_bzDecompressEnd>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def,dead> = COPY %W0
Deleting identity copy.
> %W8<def> = MOVi32imm 4294967288
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 5, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRWui %W8<kill>, <fi#0>, 0; mem:ST4[FixedStack0]
> B <BB#19>
2560B	BB#18: derived from LLVM BB %errhandler
	    Live Ins: %X19
	    Predecessors according to CFG: BB#13
2592B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2608B		%X0<def> = ADDXri <fi#7>, 0, 0
2624B		BL <ga:@BZ2_bzDecompressEnd>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
2640B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2656B		%vreg71<def,dead> = COPY %W0; GPR32all:%vreg71
2672B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2688B		STACKMAP 6, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack8](align=4) LD8[FixedStack0](align=4)
2704B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2720B		%vreg69<def> = LDRWui <fi#8>, 0; mem:LD4[FixedStack8] GPR32:%vreg69
2736B		STRWui %vreg69<kill>, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg69
	    Successors according to CFG: BB#19
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = ADDXri <fi#7>, 0, 0
> BL <ga:@BZ2_bzDecompressEnd>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def,dead> = COPY %W0
Deleting identity copy.
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 6, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack8](align=4) LD8[FixedStack0](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W8<def> = LDRWui <fi#8>, 0; mem:LD4[FixedStack8]
> STRWui %W8<kill>, <fi#0>, 0; mem:ST4[FixedStack0]
2752B	BB#19: derived from LLVM BB %return
	    Live Ins: %X19
	    Predecessors according to CFG: BB#14 BB#18 BB#17 BB#16 BB#9 BB#7
2768B		%vreg85<def> = ADRP <ga:@BZ2_bzBuffToBuffDecompress>[TF=1]; GPR64common:%vreg85
2784B		%vreg87<def> = ADDXri %vreg85<kill>, <ga:@BZ2_bzBuffToBuffDecompress>[TF=34], 0; GPR64sp:%vreg87 GPR64common:%vreg85
2832B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2848B		%X0<def> = COPY %vreg87<kill>; GPR64sp:%vreg87
2864B		%X1<def> = COPY %vreg17<kill>; GPR64:%vreg17
2880B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
2896B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2912B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2928B		STACKMAP 7, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
2944B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2960B		%vreg84<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0] GPR32:%vreg84
2976B		%W0<def> = COPY %vreg84<kill>; GPR32:%vreg84
2992B		RET_ReallyLR %W0<imp-use>
> %X8<def> = ADRP <ga:@BZ2_bzBuffToBuffDecompress>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@BZ2_bzBuffToBuffDecompress>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19<kill>
> BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 7, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0]
> %W0<def> = COPY %W0<kill>
Deleting identity copy.
> RET_ReallyLR %W0<imp-use>
Computing live-in reg-units in ABI blocks.
0B	BB#0 W0#0 W1#0 W30#0
Created 3 new intervals.
********** INTERVALS **********
W30 [0B,16r:0)[208r,208d:2)[288e,288d:1)[464r,464d:3)[576e,576d:4)[672r,672d:5)[720e,720d:6)  0@0B-phi 1@288e 2@208r 3@464r 4@576e 5@672r 6@720e
W0 [0B,48r:0)[176r,208r:1)[400r,464r:3)[464r,496r:2)[640r,672r:4)[752r,768r:5)  0@0B-phi 1@176r 2@464r 3@400r 4@640r 5@752r
W1 [0B,32r:0)[192r,208r:2)[416r,464r:1)[656r,672r:3)  0@0B-phi 1@416r 2@192r 3@656r
%vreg0 [48r,64r:0)  0@48r
%vreg1 [64r,320r:0)  0@64r
%vreg2 [32r,80r:0)  0@32r
%vreg3 [80r,336r:0)  0@80r
%vreg5 [512r,528r:0)  0@512r
%vreg6 [528r,544r:0)  0@528r
%vreg7 [544r,640r:0)  0@544r
%vreg8 [608r,656r:0)  0@608r
%vreg9 [16r,608r:0)  0@16r
%vreg11 [240r,416r:0)  0@240r
%vreg13 [256r,448r:0)  0@256r
%vreg14 [496r,752r:0)  0@496r
%vreg15 [368r,432r:0)  0@368r
%vreg16 [352r,400r:0)  0@352r
%vreg17 [96r,112r:0)  0@96r
%vreg18 [112r,128r:0)  0@112r
%vreg19 [128r,176r:0)  0@128r
%vreg20 [144r,192r:0)  0@144r
RegMasks: 208r 464r 672r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzopen: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
  fi#1: size=8, align=8, at location [SP]
Function Live Ins: %X0 in %vreg0, %X1 in %vreg2, %LR in %vreg9

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %X1 %LR
16B		%vreg9<def> = COPY %LR; GPR64:%vreg9
32B		%vreg2<def> = COPY %X1; GPR64:%vreg2
48B		%vreg0<def> = COPY %X0; GPR64:%vreg0
64B		%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
80B		%vreg3<def> = COPY %vreg2; GPR64:%vreg3,%vreg2
96B		%vreg17<def> = ADRP <ga:@BZ2_bzopen>[TF=1]; GPR64common:%vreg17
112B		%vreg18<def> = ADDXri %vreg17, <ga:@BZ2_bzopen>[TF=34], 0; GPR64sp:%vreg18 GPR64common:%vreg17
128B		%vreg19<def> = COPY %vreg18; GPR64all:%vreg19 GPR64sp:%vreg18
144B		%vreg20<def> = COPY %vreg9; GPR64all:%vreg20 GPR64:%vreg9
160B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
176B		%X0<def> = COPY %vreg19; GPR64all:%vreg19
192B		%X1<def> = COPY %vreg20; GPR64all:%vreg20
208B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
224B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
240B		%vreg11<def> = MOVi32imm 4294967295; GPR32:%vreg11
256B		%vreg13<def> = COPY %WZR; GPR32:%vreg13
272B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
288B		STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack0] GPR64:%vreg3,%vreg1
304B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
320B		STRXui %vreg1, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg1
336B		STRXui %vreg3, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg3
352B		%vreg16<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg16
368B		%vreg15<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg15
384B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
400B		%X0<def> = COPY %vreg16; GPR64:%vreg16
416B		%W1<def> = COPY %vreg11; GPR32:%vreg11
432B		%X2<def> = COPY %vreg15; GPR64:%vreg15
448B		%W3<def> = COPY %vreg13; GPR32:%vreg13
464B		BL <ga:@bzopen_or_bzdopen>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %X2<imp-use,kill>, %W3<imp-use,kill>, %X0<imp-def>
480B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
496B		%vreg14<def> = COPY %X0; GPR64all:%vreg14
512B		%vreg5<def> = ADRP <ga:@BZ2_bzopen>[TF=1]; GPR64common:%vreg5
528B		%vreg6<def> = ADDXri %vreg5, <ga:@BZ2_bzopen>[TF=34], 0; GPR64sp:%vreg6 GPR64common:%vreg5
544B		%vreg7<def> = COPY %vreg6; GPR64all:%vreg7 GPR64sp:%vreg6
560B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
576B		STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...
592B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
608B		%vreg8<def> = COPY %vreg9; GPR64all:%vreg8 GPR64:%vreg9
624B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
640B		%X0<def> = COPY %vreg7; GPR64all:%vreg7
656B		%X1<def> = COPY %vreg8; GPR64all:%vreg8
672B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
688B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
704B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
720B		STACKMAP 2, 0, %vreg14, %LR<earlyclobber,imp-def,dead>, ...; GPR64all:%vreg14
736B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
752B		%X0<def> = COPY %vreg14; GPR64all:%vreg14
768B		RET_ReallyLR %X0<imp-use>

# End machine code for function BZ2_bzopen.

********** SIMPLE REGISTER COALESCING **********
********** Function: BZ2_bzopen
********** JOINING INTERVALS ***********
entry:
16B	%vreg9<def> = COPY %LR; GPR64:%vreg9
	Considering merging %vreg9 with %LR
	Can only merge into reserved registers.
32B	%vreg2<def> = COPY %X1; GPR64:%vreg2
	Considering merging %vreg2 with %X1
	Can only merge into reserved registers.
48B	%vreg0<def> = COPY %X0; GPR64:%vreg0
	Considering merging %vreg0 with %X0
	Can only merge into reserved registers.
176B	%X0<def> = COPY %vreg19; GPR64all:%vreg19
	Considering merging %vreg19 with %X0
	Can only merge into reserved registers.
192B	%X1<def> = COPY %vreg20; GPR64all:%vreg20
	Considering merging %vreg20 with %X1
	Can only merge into reserved registers.
256B	%vreg13<def> = COPY %WZR; GPR32:%vreg13
	Considering merging %vreg13 with %WZR
		RHS = %vreg13 [256r,448r:0)  0@256r
		updated: 448B	%W3<def> = COPY %WZR
	Success: %vreg13 -> %WZR
	Result = %WZR
400B	%X0<def> = COPY %vreg16; GPR64:%vreg16
	Considering merging %vreg16 with %X0
	Can only merge into reserved registers.
416B	%W1<def> = COPY %vreg11; GPR32:%vreg11
	Considering merging %vreg11 with %W1
	Can only merge into reserved registers.
Remat: %W1<def> = MOVi32imm 4294967295
Shrink: %vreg11 [240r,416r:0)  0@240r
All defs dead: 240r	%vreg11<def,dead> = MOVi32imm 4294967295; GPR32:%vreg11
Shrunk: %vreg11 [240r,240d:0)  0@240r
Deleting dead def 240r	%vreg11<def,dead> = MOVi32imm 4294967295; GPR32:%vreg11
432B	%X2<def> = COPY %vreg15; GPR64:%vreg15
	Considering merging %vreg15 with %X2
	Can only merge into reserved registers.
448B	%W3<def> = COPY %WZR
	Not coalescable.
496B	%vreg14<def> = COPY %X0; GPR64all:%vreg14
	Considering merging %vreg14 with %X0
	Can only merge into reserved registers.
640B	%X0<def> = COPY %vreg7; GPR64all:%vreg7
	Considering merging %vreg7 with %X0
	Can only merge into reserved registers.
656B	%X1<def> = COPY %vreg8; GPR64all:%vreg8
	Considering merging %vreg8 with %X1
	Can only merge into reserved registers.
752B	%X0<def> = COPY %vreg14; GPR64all:%vreg14
	Considering merging %vreg14 with %X0
	Can only merge into reserved registers.
64B	%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
	Considering merging to GPR64 with %vreg0 in %vreg1
		RHS = %vreg0 [48r,64r:0)  0@48r
		LHS = %vreg1 [64r,320r:0)  0@64r
		merge %vreg1:0@64r into %vreg0:0@48r --> @48r
		erased:	64r	%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
		updated: 48B	%vreg1<def> = COPY %X0; GPR64:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [48r,320r:0)  0@48r
80B	%vreg3<def> = COPY %vreg2; GPR64:%vreg3,%vreg2
	Considering merging to GPR64 with %vreg2 in %vreg3
		RHS = %vreg2 [32r,80r:0)  0@32r
		LHS = %vreg3 [80r,336r:0)  0@80r
		merge %vreg3:0@80r into %vreg2:0@32r --> @32r
		erased:	80r	%vreg3<def> = COPY %vreg2; GPR64:%vreg3,%vreg2
		updated: 32B	%vreg3<def> = COPY %X1; GPR64:%vreg3
	Success: %vreg2 -> %vreg3
	Result = %vreg3 [32r,336r:0)  0@32r
128B	%vreg19<def> = COPY %vreg18; GPR64all:%vreg19 GPR64sp:%vreg18
	Considering merging to GPR64sp with %vreg18 in %vreg19
		RHS = %vreg18 [112r,128r:0)  0@112r
		LHS = %vreg19 [128r,176r:0)  0@128r
		merge %vreg19:0@128r into %vreg18:0@112r --> @112r
		erased:	128r	%vreg19<def> = COPY %vreg18; GPR64all:%vreg19 GPR64sp:%vreg18
		updated: 112B	%vreg19<def> = ADDXri %vreg17, <ga:@BZ2_bzopen>[TF=34], 0; GPR64sp:%vreg19 GPR64common:%vreg17
	Success: %vreg18 -> %vreg19
	Result = %vreg19 [112r,176r:0)  0@112r
144B	%vreg20<def> = COPY %vreg9; GPR64all:%vreg20 GPR64:%vreg9
	Considering merging to GPR64 with %vreg9 in %vreg20
		RHS = %vreg9 [16r,608r:0)  0@16r
		LHS = %vreg20 [144r,192r:0)  0@144r
		merge %vreg20:0@144r into %vreg9:0@16r --> @16r
		erased:	144r	%vreg20<def> = COPY %vreg9; GPR64all:%vreg20 GPR64:%vreg9
		updated: 16B	%vreg20<def> = COPY %LR; GPR64:%vreg20
		updated: 608B	%vreg8<def> = COPY %vreg20; GPR64all:%vreg8 GPR64:%vreg20
	Success: %vreg9 -> %vreg20
	Result = %vreg20 [16r,608r:0)  0@16r
544B	%vreg7<def> = COPY %vreg6; GPR64all:%vreg7 GPR64sp:%vreg6
	Considering merging to GPR64sp with %vreg6 in %vreg7
		RHS = %vreg6 [528r,544r:0)  0@528r
		LHS = %vreg7 [544r,640r:0)  0@544r
		merge %vreg7:0@544r into %vreg6:0@528r --> @528r
		erased:	544r	%vreg7<def> = COPY %vreg6; GPR64all:%vreg7 GPR64sp:%vreg6
		updated: 528B	%vreg7<def> = ADDXri %vreg5, <ga:@BZ2_bzopen>[TF=34], 0; GPR64sp:%vreg7 GPR64common:%vreg5
	Success: %vreg6 -> %vreg7
	Result = %vreg7 [528r,640r:0)  0@528r
608B	%vreg8<def> = COPY %vreg20; GPR64all:%vreg8 GPR64:%vreg20
	Considering merging to GPR64 with %vreg20 in %vreg8
		RHS = %vreg20 [16r,608r:0)  0@16r
		LHS = %vreg8 [608r,656r:0)  0@608r
		merge %vreg8:0@608r into %vreg20:0@16r --> @16r
		erased:	608r	%vreg8<def> = COPY %vreg20; GPR64all:%vreg8 GPR64:%vreg20
		updated: 16B	%vreg8<def> = COPY %LR; GPR64:%vreg8
		updated: 192B	%X1<def> = COPY %vreg8; GPR64:%vreg8
	Success: %vreg20 -> %vreg8
	Result = %vreg8 [16r,656r:0)  0@16r
176B	%X0<def> = COPY %vreg19; GPR64sp:%vreg19
	Considering merging %vreg19 with %X0
	Can only merge into reserved registers.
192B	%X1<def> = COPY %vreg8; GPR64:%vreg8
	Considering merging %vreg8 with %X1
	Can only merge into reserved registers.
640B	%X0<def> = COPY %vreg7; GPR64sp:%vreg7
	Considering merging %vreg7 with %X0
	Can only merge into reserved registers.
656B	%X1<def> = COPY %vreg8; GPR64:%vreg8
	Considering merging %vreg8 with %X1
	Can only merge into reserved registers.
752B	%X0<def> = COPY %vreg14; GPR64all:%vreg14
	Considering merging %vreg14 with %X0
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
W30 [0B,16r:0)[208r,208d:2)[288e,288d:1)[464r,464d:3)[576e,576d:4)[672r,672d:5)[720e,720d:6)  0@0B-phi 1@288e 2@208r 3@464r 4@576e 5@672r 6@720e
WZR EMPTY
W0 [0B,48r:0)[176r,208r:1)[400r,464r:3)[464r,496r:2)[640r,672r:4)[752r,768r:5)  0@0B-phi 1@176r 2@464r 3@400r 4@640r 5@752r
W1 [0B,32r:0)[192r,208r:2)[416r,464r:1)[656r,672r:3)  0@0B-phi 1@416r 2@192r 3@656r
%vreg1 [48r,320r:0)  0@48r
%vreg3 [32r,336r:0)  0@32r
%vreg5 [512r,528r:0)  0@512r
%vreg7 [528r,640r:0)  0@528r
%vreg8 [16r,656r:0)  0@16r
%vreg14 [496r,752r:0)  0@496r
%vreg15 [368r,432r:0)  0@368r
%vreg16 [352r,400r:0)  0@352r
%vreg17 [96r,112r:0)  0@96r
%vreg19 [112r,176r:0)  0@112r
RegMasks: 208r 464r 672r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzopen: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
  fi#1: size=8, align=8, at location [SP]
Function Live Ins: %X0 in %vreg0, %X1 in %vreg2, %LR in %vreg9

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %X1 %LR
16B		%vreg8<def> = COPY %LR; GPR64:%vreg8
32B		%vreg3<def> = COPY %X1; GPR64:%vreg3
48B		%vreg1<def> = COPY %X0; GPR64:%vreg1
96B		%vreg17<def> = ADRP <ga:@BZ2_bzopen>[TF=1]; GPR64common:%vreg17
112B		%vreg19<def> = ADDXri %vreg17, <ga:@BZ2_bzopen>[TF=34], 0; GPR64sp:%vreg19 GPR64common:%vreg17
160B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
176B		%X0<def> = COPY %vreg19; GPR64sp:%vreg19
192B		%X1<def> = COPY %vreg8; GPR64:%vreg8
208B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
224B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
272B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
288B		STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack0] GPR64:%vreg3,%vreg1
304B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
320B		STRXui %vreg1, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg1
336B		STRXui %vreg3, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg3
352B		%vreg16<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg16
368B		%vreg15<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg15
384B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
400B		%X0<def> = COPY %vreg16; GPR64:%vreg16
416B		%W1<def> = MOVi32imm 4294967295
432B		%X2<def> = COPY %vreg15; GPR64:%vreg15
448B		%W3<def> = COPY %WZR
464B		BL <ga:@bzopen_or_bzdopen>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %X2<imp-use,kill>, %W3<imp-use,kill>, %X0<imp-def>
480B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
496B		%vreg14<def> = COPY %X0; GPR64all:%vreg14
512B		%vreg5<def> = ADRP <ga:@BZ2_bzopen>[TF=1]; GPR64common:%vreg5
528B		%vreg7<def> = ADDXri %vreg5, <ga:@BZ2_bzopen>[TF=34], 0; GPR64sp:%vreg7 GPR64common:%vreg5
560B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
576B		STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...
592B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
624B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
640B		%X0<def> = COPY %vreg7; GPR64sp:%vreg7
656B		%X1<def> = COPY %vreg8; GPR64:%vreg8
672B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
688B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
704B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
720B		STACKMAP 2, 0, %vreg14, %LR<earlyclobber,imp-def,dead>, ...; GPR64all:%vreg14
736B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
752B		%X0<def> = COPY %vreg14; GPR64all:%vreg14
768B		RET_ReallyLR %X0<imp-use>

# End machine code for function BZ2_bzopen.

handleMove 448B -> 392B: %W3<def> = COPY %WZR
     W3:	[392r,464r:0)  0@392r
        -->	[392r,464r:0)  0@392r
     WZR:	EMPTY
        -->	EMPTY
handleMove 416B -> 396B: %W1<def> = MOVi32imm 4294967295
     W1:	[0B,32r:0)[192r,208r:2)[416r,464r:1)[656r,672r:3)  0@0B-phi 1@416r 2@192r 3@656r
        -->	[0B,32r:0)[192r,208r:2)[396r,464r:1)[656r,672r:3)  0@0B-phi 1@396r 2@192r 3@656r
********** GREEDY REGISTER ALLOCATION **********
********** Function: BZ2_bzopen
********** INTERVALS **********
W30 [0B,16r:0)[208r,208d:2)[288e,288d:1)[464r,464d:3)[576e,576d:4)[672r,672d:5)[720e,720d:6)  0@0B-phi 1@288e 2@208r 3@464r 4@576e 5@672r 6@720e
WZR EMPTY
W0 [0B,48r:0)[176r,208r:1)[400r,464r:3)[464r,496r:2)[640r,672r:4)[752r,768r:5)  0@0B-phi 1@176r 2@464r 3@400r 4@640r 5@752r
W1 [0B,32r:0)[192r,208r:2)[396r,464r:1)[656r,672r:3)  0@0B-phi 1@396r 2@192r 3@656r
W3 [392r,464r:0)  0@392r
%vreg1 [48r,320r:0)  0@48r
%vreg3 [32r,336r:0)  0@32r
%vreg5 [512r,528r:0)  0@512r
%vreg7 [528r,640r:0)  0@528r
%vreg8 [16r,656r:0)  0@16r
%vreg14 [496r,752r:0)  0@496r
%vreg15 [368r,432r:0)  0@368r
%vreg16 [352r,400r:0)  0@352r
%vreg17 [96r,112r:0)  0@96r
%vreg19 [112r,176r:0)  0@112r
RegMasks: 208r 464r 672r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzopen: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
  fi#1: size=8, align=8, at location [SP]
Function Live Ins: %X0 in %vreg0, %X1 in %vreg2, %LR in %vreg9

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %X1 %LR
16B		%vreg8<def> = COPY %LR; GPR64:%vreg8
32B		%vreg3<def> = COPY %X1; GPR64:%vreg3
48B		%vreg1<def> = COPY %X0; GPR64:%vreg1
96B		%vreg17<def> = ADRP <ga:@BZ2_bzopen>[TF=1]; GPR64common:%vreg17
112B		%vreg19<def> = ADDXri %vreg17, <ga:@BZ2_bzopen>[TF=34], 0; GPR64sp:%vreg19 GPR64common:%vreg17
160B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
176B		%X0<def> = COPY %vreg19; GPR64sp:%vreg19
192B		%X1<def> = COPY %vreg8; GPR64:%vreg8
208B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
224B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
272B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
288B		STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack0] GPR64:%vreg3,%vreg1
304B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
320B		STRXui %vreg1, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg1
336B		STRXui %vreg3, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg3
352B		%vreg16<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg16
368B		%vreg15<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg15
384B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
392B		%W3<def> = COPY %WZR
396B		%W1<def> = MOVi32imm 4294967295
400B		%X0<def> = COPY %vreg16; GPR64:%vreg16
432B		%X2<def> = COPY %vreg15; GPR64:%vreg15
464B		BL <ga:@bzopen_or_bzdopen>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %X2<imp-use,kill>, %W3<imp-use>, %X0<imp-def>
480B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
496B		%vreg14<def> = COPY %X0; GPR64all:%vreg14
512B		%vreg5<def> = ADRP <ga:@BZ2_bzopen>[TF=1]; GPR64common:%vreg5
528B		%vreg7<def> = ADDXri %vreg5, <ga:@BZ2_bzopen>[TF=34], 0; GPR64sp:%vreg7 GPR64common:%vreg5
560B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
576B		STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...
592B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
624B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
640B		%X0<def> = COPY %vreg7; GPR64sp:%vreg7
656B		%X1<def> = COPY %vreg8; GPR64:%vreg8
672B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
688B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
704B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
720B		STACKMAP 2, 0, %vreg14, %LR<earlyclobber,imp-def,dead>, ...; GPR64all:%vreg14
736B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
752B		%X0<def> = COPY %vreg14; GPR64all:%vreg14
768B		RET_ReallyLR %X0<imp-use>

# End machine code for function BZ2_bzopen.


selectOrSplit GPR64:%vreg8 [16r,656r:0)  0@16r w=2.913462e-03
hints: %X1
missed hint %X1
assigning %vreg8 to %X19: W19 [16r,656r:0)  0@16r

selectOrSplit GPR64:%vreg3 [32r,336r:0)  0@32r w=4.303977e-03
hints: %X1
missed hint %X1
assigning %vreg3 to %X20: W20 [32r,336r:0)  0@32r

selectOrSplit GPR64:%vreg1 [48r,320r:0)  0@48r w=4.508928e-03
hints: %X0
missed hint %X0
assigning %vreg1 to %X21: W21 [48r,320r:0)  0@48r

selectOrSplit GPR64sp:%vreg19 [112r,176r:0)  0@112r w=4.353448e-03
hints: %X0
assigning %vreg19 to %X0: W0 [112r,176r:0)  0@112r

selectOrSplit GPR64:%vreg16 [352r,400r:0)  0@352r w=4.508928e-03
hints: %X0
assigning %vreg16 to %X0: W0 [352r,400r:0)  0@352r

selectOrSplit GPR64:%vreg15 [368r,432r:0)  0@368r w=4.353448e-03
hints: %X2
assigning %vreg15 to %X2: W2 [368r,432r:0)  0@368r

selectOrSplit GPR64all:%vreg14 [496r,752r:0)  0@496r w=4.618902e-03
hints: %X0
missed hint %X0
assigning %vreg14 to %X20: W20 [496r,752r:0)  0@496r

selectOrSplit GPR64sp:%vreg7 [528r,640r:0)  0@528r w=3.945312e-03
hints: %X0
assigning %vreg7 to %X0: W0 [528r,640r:0)  0@528r

selectOrSplit GPR64common:%vreg17 [96r,112r:0)  0@96r w=inf
assigning %vreg17 to %X8: W8 [96r,112r:0)  0@96r

selectOrSplit GPR64common:%vreg5 [512r,528r:0)  0@512r w=inf
assigning %vreg5 to %X8: W8 [512r,528r:0)  0@512r

********** STACK TRANSFORMATION METADATA **********
********** Function: BZ2_bzopen
********** REGISTER MAP **********
[%vreg1 -> %X21] GPR64
[%vreg3 -> %X20] GPR64
[%vreg5 -> %X8] GPR64common
[%vreg7 -> %X0] GPR64sp
[%vreg8 -> %X19] GPR64
[%vreg14 -> %X20] GPR64all
[%vreg15 -> %X2] GPR64
[%vreg16 -> %X0] GPR64
[%vreg17 -> %X8] GPR64common
[%vreg19 -> %X0] GPR64sp


Stackmap 0:
  STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack0] GPR64:%vreg3,%vreg1

i8* %mode: in register %X20 (vreg 3)
i8** %mode.addr: in stack slot 1 (size: 8)
i8* %path: in register %X21 (vreg 1)
i8** %path.addr: in stack slot 0 (size: 8)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...


Duplicate operand locations:


Stackmap 2:
  STACKMAP 2, 0, %vreg14, %LR<earlyclobber,imp-def,dead>, ...; GPR64all:%vreg14

i8* %call: in register %X20 (vreg 14)

Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack0] GPR64:%vreg3,%vreg1
  -> Call instruction SlotIndex 208B, searching vregs 0 -> 21 and stack slots 0 -> 2
    + vreg8 is live in register but not in stackmap
      Defining instruction: %vreg8<def> = COPY %LR; GPR64:%vreg8
      Value: generated value, 1 instruction(s)

  STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...
  -> Call instruction SlotIndex 464B, searching vregs 0 -> 21 and stack slots 0 -> 2
    + vreg8 is live in register but not in stackmap
      Defining instruction: %vreg8<def> = COPY %LR; GPR64:%vreg8
      Value: generated value, 1 instruction(s)

  STACKMAP 2, 0, %vreg14, %LR<earlyclobber,imp-def,dead>, ...; GPR64all:%vreg14
  -> Call instruction SlotIndex 672B, searching vregs 0 -> 21 and stack slots 0 -> 2

********** REWRITE VIRTUAL REGISTERS **********
********** Function: BZ2_bzopen
********** REGISTER MAP **********
[%vreg1 -> %X21] GPR64
[%vreg3 -> %X20] GPR64
[%vreg5 -> %X8] GPR64common
[%vreg7 -> %X0] GPR64sp
[%vreg8 -> %X19] GPR64
[%vreg14 -> %X20] GPR64all
[%vreg15 -> %X2] GPR64
[%vreg16 -> %X0] GPR64
[%vreg17 -> %X8] GPR64common
[%vreg19 -> %X0] GPR64sp

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %LR %X0 %X1
16B		%vreg8<def> = COPY %LR; GPR64:%vreg8
32B		%vreg3<def> = COPY %X1; GPR64:%vreg3
48B		%vreg1<def> = COPY %X0; GPR64:%vreg1
96B		%vreg17<def> = ADRP <ga:@BZ2_bzopen>[TF=1]; GPR64common:%vreg17
112B		%vreg19<def> = ADDXri %vreg17<kill>, <ga:@BZ2_bzopen>[TF=34], 0; GPR64sp:%vreg19 GPR64common:%vreg17
160B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
176B		%X0<def> = COPY %vreg19<kill>; GPR64sp:%vreg19
192B		%X1<def> = COPY %vreg8; GPR64:%vreg8
208B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
224B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
272B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
288B		STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack0] GPR64:%vreg3,%vreg1
304B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
320B		STRXui %vreg1<kill>, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg1
336B		STRXui %vreg3<kill>, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg3
352B		%vreg16<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg16
368B		%vreg15<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg15
384B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
392B		%W3<def> = COPY %WZR
396B		%W1<def> = MOVi32imm 4294967295
400B		%X0<def> = COPY %vreg16<kill>; GPR64:%vreg16
432B		%X2<def> = COPY %vreg15<kill>; GPR64:%vreg15
464B		BL <ga:@bzopen_or_bzdopen>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %X2<imp-use>, %W3<imp-use>, %X0<imp-def>
480B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
496B		%vreg14<def> = COPY %X0; GPR64all:%vreg14
512B		%vreg5<def> = ADRP <ga:@BZ2_bzopen>[TF=1]; GPR64common:%vreg5
528B		%vreg7<def> = ADDXri %vreg5<kill>, <ga:@BZ2_bzopen>[TF=34], 0; GPR64sp:%vreg7 GPR64common:%vreg5
560B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
576B		STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...
592B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
624B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
640B		%X0<def> = COPY %vreg7<kill>; GPR64sp:%vreg7
656B		%X1<def> = COPY %vreg8<kill>; GPR64:%vreg8
672B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
688B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
704B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
720B		STACKMAP 2, 0, %vreg14, %LR<earlyclobber,imp-def,dead>, ...; GPR64all:%vreg14
736B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
752B		%X0<def> = COPY %vreg14<kill>; GPR64all:%vreg14
768B		RET_ReallyLR %X0<imp-use>
> %X19<def> = COPY %LR
> %X20<def> = COPY %X1
> %X21<def> = COPY %X0
> %X8<def> = ADRP <ga:@BZ2_bzopen>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@BZ2_bzopen>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19
> BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 0, 0, %X20, 0, <fi#1>, 0, %X21, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack0]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRXui %X21<kill>, <fi#0>, 0; mem:ST8[FixedStack0]
> STRXui %X20<kill>, <fi#1>, 0; mem:ST8[FixedStack1]
> %X0<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %X2<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %W3<def> = COPY %WZR
> %W1<def> = MOVi32imm 4294967295
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X2<def> = COPY %X2<kill>
Deleting identity copy.
> BL <ga:@bzopen_or_bzdopen>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %X2<imp-use>, %W3<imp-use>, %X0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X20<def> = COPY %X0
> %X8<def> = ADRP <ga:@BZ2_bzopen>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@BZ2_bzopen>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19<kill>
> BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 2, 0, %X20, %LR<earlyclobber,imp-def,dead>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X20<kill>
> RET_ReallyLR %X0<imp-use>
Computing live-in reg-units in ABI blocks.
0B	BB#0 W0#0 W1#0 W2#0 W3#0 W30#0
Created 5 new intervals.
********** INTERVALS **********
W30 [0B,16r:0)[272r,272d:20)[416e,416d:10)[640r,640d:21)[1904r,1904d:18)[2016e,2016d:9)[2096r,2096d:19)[2160e,2160d:8)[2368r,2368d:16)[2448e,2448d:7)[2880r,2880d:15)[2944e,2944d:6)[3120r,3120d:17)[3184e,3184d:5)[3808r,3808d:13)[3872e,3872d:4)[4160r,4160d:14)[4224e,4224d:3)[4608r,4608d:12)[4672e,4672d:2)[4944r,4944d:11)[4992e,4992d:1)  0@0B-phi 1@4992e 2@4672e 3@4224e 4@3872e 5@3184e 6@2944e 7@2448e 8@2160e 9@2016e 10@416e 11@4944r 12@4608r 13@3808r 14@4160r 15@2880r 16@2368r 17@3120r 18@1904r 19@2096r 20@272r 21@640r
W0 [0B,80r:0)[240r,272r:19)[576r,640r:20)[1872r,1904r:16)[1904r,1936r:15)[2064r,2096r:18)[2096r,2128r:17)[2336r,2368r:13)[2368r,2400r:2)[2848r,2880r:12)[2880r,2912r:11)[3088r,3120r:3)[3120r,3152r:14)[3728r,3808r:8)[3808r,3840r:7)[4064r,4160r:10)[4160r,4192r:9)[4592r,4608r:6)[4608r,4640r:1)[4912r,4944r:4)[5040r,5056r:5)  0@0B-phi 1@4608r 2@2368r 3@3088r 4@4912r 5@5040r 6@4592r 7@3808r 8@3728r 9@4160r 10@4064r 11@2880r 12@2848r 13@2336r 14@3120r 15@1904r 16@1872r 17@2096r 18@2064r 19@240r 20@576r
W1 [0B,64r:0)[256r,272r:10)[608r,640r:1)[1888r,1904r:8)[2080r,2096r:9)[2352r,2368r:6)[2864r,2880r:5)[3104r,3120r:7)[3744r,3808r:3)[4080r,4160r:4)[4928r,4944r:2)  0@0B-phi 1@608r 2@4928r 3@3744r 4@4080r 5@2864r 6@2352r 7@3104r 8@1888r 9@2080r 10@256r
W2 [0B,48r:0)[624r,640r:3)[3760r,3808r:1)[4096r,4160r:2)  0@0B-phi 1@3760r 2@4096r 3@624r
W3 [0B,32r:0)[3776r,3808r:1)[4112r,4160r:2)  0@0B-phi 1@3776r 2@4112r
%vreg2 [2736r,2752r:0)  0@2736r
%vreg3 [80r,96r:0)  0@80r
%vreg4 [96r,448r:0)  0@96r
%vreg5 [64r,112r:0)  0@64r
%vreg6 [112r,464r:0)  0@112r
%vreg7 [48r,128r:0)  0@48r
%vreg8 [128r,480r:0)  0@128r
%vreg9 [32r,144r:0)  0@32r
%vreg10 [144r,496r:0)  0@144r
%vreg12 [768r,784r:0)  0@768r
%vreg13 [304r,720r:0)  0@304r
%vreg14 [320r,688r:0)  0@320r
%vreg16 [336r,592r:0)  0@336r
%vreg17 [592r,608r:0)  0@592r
%vreg18 [352r,624r:0)  0@352r
%vreg19 [368r,544r:0)  0@368r
%vreg20 [544r,576r:0)  0@544r
%vreg21 [384r,512r:0)  0@384r
%vreg22 [160r,176r:0)  0@160r
%vreg23 [176r,192r:0)  0@176r
%vreg24 [192r,240r:0)  0@192r
%vreg25 [208r,256r:0)  0@208r
%vreg26 [16r,4880r:0)  0@16r
%vreg28 [944r,960r:0)  0@944r
%vreg30 [928r,944r:0)  0@928r
%vreg31 [912r,928r:0)  0@912r
%vreg33 [2192r,2208r:0)  0@2192r
%vreg35 [1952r,1968r:0)  0@1952r
%vreg36 [1968r,2080r:0)  0@1968r
%vreg37 [2128r,2128d:0)  0@2128r
%vreg38 [1984r,2064r:0)  0@1984r
%vreg41 [1936r,1936d:0)  0@1936r
%vreg43 [1728r,1744r:0)  0@1728r
%vreg44 [1744r,1840r:0)  0@1744r
%vreg45 [1760r,1776r:0)  0@1760r
%vreg46 [1776r,1840r:0)  0@1776r
%vreg47 [1840r,1888r:0)  0@1840r
%vreg48 [1808r,1824r:0)  0@1808r
%vreg49 [1792r,1872r:0)  0@1792r
%vreg53 [3152r,3216r:0)  0@3152r
%vreg54 [3040r,3104r:0)  0@3040r
%vreg55 [3056r,3088r:0)  0@3056r
%vreg57 [2240r,2256r:0)  0@2240r
%vreg58 [2416r,2480r:0)  0@2416r
%vreg60 [2320r,2352r:0)  0@2320r
%vreg61 [2400r,2416r:0)  0@2400r
%vreg62 [2288r,2336r:0)  0@2288r
%vreg66 [2912r,2976r:0)  0@2912r
%vreg67 [2800r,2864r:0)  0@2800r
%vreg68 [2816r,2848r:0)  0@2816r
%vreg70 [2512r,2528r:0)  0@2512r
%vreg71 [2656r,2672r:0)  0@2656r
%vreg72 [2672r,2688r:0)  0@2672r
%vreg73 [2688r,2704r:0)  0@2688r
%vreg74 [2560r,2576r:0)  0@2560r
%vreg75 [2576r,2592r:0)  0@2576r
%vreg76 [2592r,2608r:0)  0@2592r
%vreg78 [3248r,3264r:0)  0@3248r
%vreg80 [3360r,3376r:0)  0@3360r
%vreg82 [3952r,4064r:0)  0@3952r
%vreg88 [4192r,4256r:0)  0@4192r
%vreg89 [4032r,4144r:0)  0@4032r
%vreg90 [3968r,4128r:0)  0@3968r
%vreg91 [4016r,4112r:0)  0@4016r
%vreg92 [4000r,4096r:0)  0@4000r
%vreg93 [3984r,4080r:0)  0@3984r
%vreg95 [3408r,3424r:0)  0@3408r
%vreg96 [3472r,3488r:0)  0@3472r
%vreg98 [3520r,3536r:0)  0@3520r
%vreg99 [3584r,3600r:0)  0@3584r
%vreg101 [3632r,3728r:0)  0@3632r
%vreg106 [3840r,3904r:0)  0@3840r
%vreg107 [3696r,3792r:0)  0@3696r
%vreg108 [3680r,3776r:0)  0@3680r
%vreg109 [3664r,3760r:0)  0@3664r
%vreg110 [3648r,3744r:0)  0@3648r
%vreg112 [4288r,4304r:0)  0@4288r
%vreg114 [4784r,4800r:0)  0@4784r
%vreg117 [4336r,4352r:0)  0@4336r
%vreg118 [4352r,4384r:0)  0@4352r
%vreg119 [4384r,4400r:0)  0@4384r
%vreg120 [4368r,4400r:0)  0@4368r
%vreg123 [4448r,4464r:0)  0@4448r
%vreg124 [4464r,4496r:0)  0@4464r
%vreg125 [4496r,4512r:0)  0@4496r
%vreg126 [4480r,4512r:0)  0@4480r
%vreg128 [4640r,4640d:0)  0@4640r
%vreg129 [4560r,4592r:0)  0@4560r
%vreg130 [4720r,4736r:0)  0@4720r
%vreg131 [3296r,3312r:0)  0@3296r
%vreg132 [1024r,1168r:0)  0@1024r
%vreg133 [992r,1008r:0)  0@992r
%vreg134 [1008r,1040r:0)  0@1008r
%vreg135 [1040r,1040d:0)  0@1040r
%vreg136 [1104r,1104d:0)  0@1104r
%vreg137 [1168r,1168d:0)  0@1168r
%vreg138 [1344r,1360r:0)  0@1344r
%vreg139 [1280r,1296r:0)  0@1280r
%vreg142 [1472r,1488r:0)  0@1472r
%vreg146 [1456r,1472r:0)  0@1456r
%vreg147 [1440r,1456r:0)  0@1440r
%vreg158 [1568r,1584r:0)  0@1568r
%vreg162 [1552r,1568r:0)  0@1552r
%vreg163 [1536r,1552r:0)  0@1536r
%vreg166 [1664r,1680r:0)  0@1664r
%vreg167 [1648r,1664r:0)  0@1648r
%vreg168 [816r,832r:0)  0@816r
%vreg170 [5024r,5040r:0)  0@5024r
%vreg171 [4832r,4848r:0)  0@4832r
%vreg172 [4848r,4864r:0)  0@4848r
%vreg173 [4864r,4912r:0)  0@4864r
%vreg174 [4880r,4928r:0)  0@4880r
%vreg175 [2608r,2640B:1)[2704r,2720B:0)[2720B,2736r:2)  0@2704r 1@2608r 2@2720B-phi
RegMasks: 272r 640r 1904r 2096r 2368r 2880r 3120r 3808r 4160r 4608r 4944r
********** MACHINEINSTRS **********
# Machine code for function bzopen_or_bzdopen: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=4, align=4, at location [SP]
  fi#3: size=8, align=8, at location [SP]
  fi#4: size=4, align=4, at location [SP]
  fi#5: size=4, align=4, at location [SP]
  fi#6: size=5000, align=16, at location [SP]
  fi#7: size=4, align=4, at location [SP]
  fi#8: size=4, align=4, at location [SP]
  fi#9: size=10, align=1, at location [SP]
  fi#10: size=8, align=8, at location [SP]
  fi#11: size=8, align=8, at location [SP]
  fi#12: size=4, align=4, at location [SP]
  fi#13: size=4, align=4, at location [SP]
  fi#14: size=4, align=4, at location [SP]
  fi#15: size=4, align=4, at location [SP]
Function Live Ins: %X0 in %vreg3, %W1 in %vreg5, %X2 in %vreg7, %W3 in %vreg9, %LR in %vreg26

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %W1 %X2 %W3 %LR
16B		%vreg26<def> = COPY %LR; GPR64:%vreg26
32B		%vreg9<def> = COPY %W3; GPR32:%vreg9
48B		%vreg7<def> = COPY %X2; GPR64:%vreg7
64B		%vreg5<def> = COPY %W1; GPR32:%vreg5
80B		%vreg3<def> = COPY %X0; GPR64:%vreg3
96B		%vreg4<def> = COPY %vreg3; GPR64:%vreg4,%vreg3
112B		%vreg6<def> = COPY %vreg5; GPR32:%vreg6,%vreg5
128B		%vreg8<def> = COPY %vreg7; GPR64:%vreg8,%vreg7
144B		%vreg10<def> = COPY %vreg9; GPR32:%vreg10,%vreg9
160B		%vreg22<def> = ADRP <ga:@bzopen_or_bzdopen>[TF=1]; GPR64common:%vreg22
176B		%vreg23<def> = ADDXri %vreg22, <ga:@bzopen_or_bzdopen>[TF=34], 0; GPR64sp:%vreg23 GPR64common:%vreg22
192B		%vreg24<def> = COPY %vreg23; GPR64all:%vreg24 GPR64sp:%vreg23
208B		%vreg25<def> = COPY %vreg26; GPR64all:%vreg25 GPR64:%vreg26
224B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
240B		%X0<def> = COPY %vreg24; GPR64all:%vreg24
256B		%X1<def> = COPY %vreg25; GPR64all:%vreg25
272B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
288B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
304B		%vreg13<def> = MOVi32imm 30; GPR32:%vreg13
320B		%vreg14<def> = COPY %XZR; GPR64:%vreg14
336B		%vreg16<def> = COPY %WZR; GPR32:%vreg16
352B		%vreg18<def> = MOVi64imm 10; GPR64:%vreg18
368B		%vreg19<def> = ADDXri <fi#9>, 0, 0; GPR64sp:%vreg19
384B		%vreg21<def> = MOVi32imm 9; GPR32:%vreg21
400B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
416B		STACKMAP 0, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, %vreg6, 0, <fi#2>, 0, 0, <fi#10>, 0, %vreg8, 0, <fi#3>, 0, 0, <fi#9>, 0, 0, <fi#15>, 0, %vreg10, 0, <fi#4>, 0, %vreg4, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack2](align=4) LD8[FixedStack10] LD8[FixedStack3] LD8[FixedStack9](align=1) LD8[FixedStack15](align=4) LD8[FixedStack4](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4) GPR32:%vreg6,%vreg10 GPR64:%vreg8,%vreg4
432B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
448B		STRXui %vreg4, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg4
464B		STRWui %vreg6, <fi#2>, 0; mem:ST4[FixedStack2] GPR32:%vreg6
480B		STRXui %vreg8, <fi#3>, 0; mem:ST8[FixedStack3] GPR64:%vreg8
496B		STRWui %vreg10, <fi#4>, 0; mem:ST4[FixedStack4] GPR32:%vreg10
512B		STRWui %vreg21, <fi#7>, 0; mem:ST4[FixedStack7] GPR32:%vreg21
528B		STRWui %WZR, <fi#8>, 0; mem:ST4[FixedStack8]
544B		%vreg20<def> = COPY %vreg19; GPR64all:%vreg20 GPR64sp:%vreg19
560B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
576B		%X0<def> = COPY %vreg20; GPR64all:%vreg20
592B		%vreg17<def> = UBFMWri %vreg16, 0, 7; GPR32:%vreg17,%vreg16
608B		%W1<def> = COPY %vreg17; GPR32:%vreg17
624B		%X2<def> = COPY %vreg18; GPR64:%vreg18
640B		BL <MCSym=memset>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %X2<imp-use>
656B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
672B		STRXui %vreg14, <fi#10>, 0; mem:ST8[FixedStack10] GPR64:%vreg14
688B		STRXui %vreg14, <fi#11>, 0; mem:ST8[FixedStack11] GPR64:%vreg14
704B		STRWui %WZR, <fi#12>, 0; mem:ST4[FixedStack12]
720B		STRWui %vreg13, <fi#13>, 0; mem:ST4[FixedStack13] GPR32:%vreg13
736B		STRWui %WZR, <fi#14>, 0; mem:ST4[FixedStack14]
752B		STRWui %WZR, <fi#15>, 0; mem:ST4[FixedStack15]
768B		%vreg12<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg12
784B		CBNZX %vreg12, <BB#2>; GPR64:%vreg12
	    Successors according to CFG: BB#2 BB#1

800B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
816B		%vreg168<def> = COPY %XZR; GPR64:%vreg168
832B		STRXui %vreg168, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg168
848B		B <BB#40>
	    Successors according to CFG: BB#40

864B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0
880B		B <BB#3>
	    Successors according to CFG: BB#3

896B	BB#3: derived from LLVM BB %while.cond
	    Predecessors according to CFG: BB#2 BB#14
912B		%vreg31<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg31
928B		%vreg30<def> = LDRBBui %vreg31, 0; mem:LD1[%2] GPR32:%vreg30 GPR64common:%vreg31
944B		%vreg28<def> = UBFMWri %vreg30, 0, 7; GPR32:%vreg28,%vreg30
960B		CBZW %vreg28, <BB#15>; GPR32:%vreg28
	    Successors according to CFG: BB#15 BB#4

976B	BB#4: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#3
992B		%vreg133<def> = LDRXui <fi#3>, 0; mem:LD8[%mode.addr] GPR64common:%vreg133
1008B		%vreg134<def> = LDRSBWui %vreg133, 0; mem:LD1[%4] GPR32common:%vreg134 GPR64common:%vreg133
1024B		%vreg132<def> = COPY %vreg134; GPR32sp:%vreg132 GPR32common:%vreg134
1040B		%vreg135<def,dead> = SUBSWri %vreg134, 114, 0, %NZCV<imp-def>; GPR32:%vreg135 GPR32common:%vreg134
1056B		Bcc 0, <BB#7>, %NZCV<imp-use,kill>
1072B		B <BB#5>
	    Successors according to CFG: BB#7 BB#5

1088B	BB#5: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#4
1104B		%vreg136<def,dead> = SUBSWri %vreg132, 115, 0, %NZCV<imp-def>; GPR32:%vreg136 GPR32sp:%vreg132
1120B		Bcc 0, <BB#9>, %NZCV<imp-use,kill>
1136B		B <BB#6>
	    Successors according to CFG: BB#9 BB#6

1152B	BB#6: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#5
1168B		%vreg137<def,dead> = SUBSWri %vreg132, 119, 0, %NZCV<imp-def>; GPR32:%vreg137 GPR32sp:%vreg132
1184B		Bcc 0, <BB#8>, %NZCV<imp-use,kill>
1200B		B <BB#10>
	    Successors according to CFG: BB#8 BB#10

1216B	BB#7: derived from LLVM BB %sw.bb
	    Predecessors according to CFG: BB#4
1232B		STRWui %WZR, <fi#8>, 0; mem:ST4[FixedStack8]
1248B		B <BB#14>
	    Successors according to CFG: BB#14

1264B	BB#8: derived from LLVM BB %sw.bb.1
	    Predecessors according to CFG: BB#6
1280B		%vreg139<def> = MOVi32imm 1; GPR32:%vreg139
1296B		STRWui %vreg139, <fi#8>, 0; mem:ST4[FixedStack8] GPR32:%vreg139
1312B		B <BB#14>
	    Successors according to CFG: BB#14

1328B	BB#9: derived from LLVM BB %sw.bb.2
	    Predecessors according to CFG: BB#5
1344B		%vreg138<def> = MOVi32imm 1; GPR32:%vreg138
1360B		STRWui %vreg138, <fi#14>, 0; mem:ST4[FixedStack14] GPR32:%vreg138
1376B		B <BB#14>
	    Successors according to CFG: BB#14

1392B	BB#10: derived from LLVM BB %sw.default
	    Predecessors according to CFG: BB#6
1408B		B <BB#11>
	    Successors according to CFG: BB#11

1424B	BB#11: derived from LLVM BB %cond.false
	    Predecessors according to CFG: BB#10
1440B		%vreg147<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg147
1456B		%vreg146<def> = LDRSBWui %vreg147, 0; mem:LD1[%8] GPR32common:%vreg146 GPR64common:%vreg147
1472B		%vreg142<def> = SUBWri %vreg146, 48, 0; GPR32sp:%vreg142 GPR32common:%vreg146
1488B		%WZR<def> = SUBSWri %vreg142, 10, 0, %NZCV<imp-def>; GPR32sp:%vreg142
1504B		Bcc 2, <BB#13>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#13 BB#12

1520B	BB#12: derived from LLVM BB %if.then.8
	    Predecessors according to CFG: BB#11
1536B		%vreg163<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg163
1552B		%vreg162<def> = LDRSBWui %vreg163, 0; mem:LD1[%10] GPR32common:%vreg162 GPR64common:%vreg163
1568B		%vreg158<def> = SUBWri %vreg162, 48, 0; GPR32common:%vreg158,%vreg162
1584B		STRWui %vreg158, <fi#7>, 0; mem:ST4[FixedStack7] GPR32common:%vreg158
	    Successors according to CFG: BB#13

1600B	BB#13: derived from LLVM BB %if.end.11
	    Predecessors according to CFG: BB#11 BB#12
1616B		B <BB#14>
	    Successors according to CFG: BB#14

1632B	BB#14: derived from LLVM BB %sw.epilog
	    Predecessors according to CFG: BB#9 BB#8 BB#7 BB#13
1648B		%vreg167<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg167
1664B		%vreg166<def> = ADDXri %vreg167, 1, 0; GPR64common:%vreg166,%vreg167
1680B		STRXui %vreg166, <fi#3>, 0; mem:ST8[FixedStack3] GPR64common:%vreg166
1696B		B <BB#3>
	    Successors according to CFG: BB#3

1712B	BB#15: derived from LLVM BB %while.end
	    Predecessors according to CFG: BB#3
1728B		%vreg43<def> = ADRP <ga:@bzlib__str_6_w_>[TF=1]; GPR64common:%vreg43
1744B		%vreg44<def> = ADDXri %vreg43, <ga:@bzlib__str_6_w_>[TF=34], 0; GPR64common:%vreg44,%vreg43
1760B		%vreg45<def> = ADRP <ga:@bzlib__str_7_r_>[TF=1]; GPR64common:%vreg45
1776B		%vreg46<def> = ADDXri %vreg45, <ga:@bzlib__str_7_r_>[TF=34], 0; GPR64common:%vreg46,%vreg45
1792B		%vreg49<def> = ADDXri <fi#9>, 0, 0; GPR64sp:%vreg49
1808B		%vreg48<def> = LDRWui <fi#8>, 0; mem:LD4[FixedStack8] GPR32common:%vreg48
1824B		%WZR<def> = SUBSWri %vreg48, 0, 0, %NZCV<imp-def>; GPR32common:%vreg48
1840B		%vreg47<def> = CSELXr %vreg44, %vreg46, 1, %NZCV<imp-use,kill>; GPR64:%vreg47 GPR64common:%vreg44,%vreg46
1856B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1872B		%X0<def> = COPY %vreg49; GPR64sp:%vreg49
1888B		%X1<def> = COPY %vreg47; GPR64:%vreg47
1904B		BL <ga:@strcat>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %X0<imp-def>
1920B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1936B		%vreg41<def,dead> = COPY %X0; GPR64all:%vreg41
1952B		%vreg35<def> = ADRP <ga:@bzlib__str_8_b_>[TF=1]; GPR64common:%vreg35
1968B		%vreg36<def> = ADDXri %vreg35, <ga:@bzlib__str_8_b_>[TF=34], 0; GPR64sp:%vreg36 GPR64common:%vreg35
1984B		%vreg38<def> = ADDXri <fi#9>, 0, 0; GPR64sp:%vreg38
2000B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2016B		STACKMAP 2, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#2>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, 0, <fi#15>, 0, 0, <fi#4>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack2](align=4) LD8[FixedStack10] LD8[FixedStack9](align=1) LD8[FixedStack15](align=4) LD8[FixedStack4](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)
2032B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2048B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2064B		%X0<def> = COPY %vreg38; GPR64sp:%vreg38
2080B		%X1<def> = COPY %vreg36; GPR64sp:%vreg36
2096B		BL <ga:@strcat>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %X0<imp-def>
2112B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2128B		%vreg37<def,dead> = COPY %X0; GPR64all:%vreg37
2144B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2160B		STACKMAP 3, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#2>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, 0, <fi#15>, 0, 0, <fi#4>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack2](align=4) LD8[FixedStack10] LD8[FixedStack9](align=1) LD8[FixedStack15](align=4) LD8[FixedStack4](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)
2176B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2192B		%vreg33<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg33
2208B		CBNZW %vreg33, <BB#24>; GPR32:%vreg33
	    Successors according to CFG: BB#24 BB#16

2224B	BB#16: derived from LLVM BB %if.then.18
	    Predecessors according to CFG: BB#15
2240B		%vreg57<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg57
2256B		CBZX %vreg57, <BB#18>; GPR64:%vreg57
	    Successors according to CFG: BB#18 BB#17

2272B	BB#17: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#16
2288B		%vreg62<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg62
2304B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2320B		%vreg60<def> = MOVaddr <ga:@bzlib__str_9_>[TF=1], <ga:@bzlib__str_9_>[TF=34]; GPR64:%vreg60
2336B		%X0<def> = COPY %vreg62; GPR64:%vreg62
2352B		%X1<def> = COPY %vreg60; GPR64:%vreg60
2368B		BL <ga:@strcmp>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %SP<imp-def>, %W0<imp-def>
2384B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2400B		%vreg61<def> = COPY %W0; GPR32:%vreg61
2416B		%vreg58<def> = COPY %vreg61; GPR32:%vreg58,%vreg61
2432B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2448B		STACKMAP 4, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, 0, <fi#15>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack9](align=1) LD8[FixedStack15](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)
2464B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2480B		CBNZW %vreg58, <BB#22>; GPR32:%vreg58
	    Successors according to CFG: BB#22 BB#18

2496B	BB#18: derived from LLVM BB %if.then.24
	    Predecessors according to CFG: BB#16 BB#17
2512B		%vreg70<def> = LDRWui <fi#8>, 0; mem:LD4[FixedStack8] GPR32:%vreg70
2528B		CBZW %vreg70, <BB#20>; GPR32:%vreg70
	    Successors according to CFG: BB#20 BB#19

2544B	BB#19: derived from LLVM BB %cond.true.26
	    Predecessors according to CFG: BB#18
2560B		%vreg74<def> = ADRP <ga:@stdout>[TF=1]; GPR64common:%vreg74
2576B		%vreg75<def> = ADDXri %vreg74, <ga:@stdout>[TF=34], 0; GPR64sp:%vreg75 GPR64common:%vreg74
2592B		%vreg76<def> = LDRXui %vreg75, 0; mem:LD8[@stdout] GPR64:%vreg76 GPR64sp:%vreg75
2608B		%vreg175<def> = COPY %vreg76; GPR64:%vreg175,%vreg76
2624B		B <BB#21>
	    Successors according to CFG: BB#21

2640B	BB#20: derived from LLVM BB %cond.false.27
	    Predecessors according to CFG: BB#18
2656B		%vreg71<def> = ADRP <ga:@stdin>[TF=1]; GPR64common:%vreg71
2672B		%vreg72<def> = ADDXri %vreg71, <ga:@stdin>[TF=34], 0; GPR64sp:%vreg72 GPR64common:%vreg71
2688B		%vreg73<def> = LDRXui %vreg72, 0; mem:LD8[@stdin] GPR64:%vreg73 GPR64sp:%vreg72
2704B		%vreg175<def> = COPY %vreg73; GPR64:%vreg175,%vreg73
	    Successors according to CFG: BB#21

2720B	BB#21: derived from LLVM BB %cond.end
	    Predecessors according to CFG: BB#20 BB#19
2736B		%vreg2<def> = COPY %vreg175; GPR64:%vreg2,%vreg175
2752B		STRXui %vreg2, <fi#10>, 0; mem:ST8[FixedStack10] GPR64:%vreg2
2768B		B <BB#23>
	    Successors according to CFG: BB#23

2784B	BB#22: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#17
2800B		%vreg67<def> = ADDXri <fi#9>, 0, 0; GPR64sp:%vreg67
2816B		%vreg68<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg68
2832B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2848B		%X0<def> = COPY %vreg68; GPR64:%vreg68
2864B		%X1<def> = COPY %vreg67; GPR64sp:%vreg67
2880B		BL <ga:@fopen>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %X0<imp-def>
2896B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2912B		%vreg66<def> = COPY %X0; GPR64:%vreg66
2928B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2944B		STACKMAP 5, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#15>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack15](align=4) LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)
2960B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2976B		STRXui %vreg66, <fi#10>, 0; mem:ST8[FixedStack10] GPR64:%vreg66
	    Successors according to CFG: BB#23

2992B	BB#23: derived from LLVM BB %if.end.31
	    Predecessors according to CFG: BB#22 BB#21
3008B		B <BB#25>
	    Successors according to CFG: BB#25

3024B	BB#24: derived from LLVM BB %if.else.32
	    Predecessors according to CFG: BB#15
3040B		%vreg54<def> = ADDXri <fi#9>, 0, 0; GPR64sp:%vreg54
3056B		%vreg55<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg55
3072B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3088B		%W0<def> = COPY %vreg55; GPR32:%vreg55
3104B		%X1<def> = COPY %vreg54; GPR64sp:%vreg54
3120B		BL <ga:@fdopen>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use>, %X0<imp-def>
3136B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3152B		%vreg53<def> = COPY %X0; GPR64:%vreg53
3168B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3184B		STACKMAP 6, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#15>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack15](align=4) LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)
3200B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3216B		STRXui %vreg53, <fi#10>, 0; mem:ST8[FixedStack10] GPR64:%vreg53
	    Successors according to CFG: BB#25

3232B	BB#25: derived from LLVM BB %if.end.35
	    Predecessors according to CFG: BB#24 BB#23
3248B		%vreg78<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg78
3264B		CBNZX %vreg78, <BB#27>; GPR64:%vreg78
	    Successors according to CFG: BB#27 BB#26

3280B	BB#26: derived from LLVM BB %if.then.38
	    Predecessors according to CFG: BB#25
3296B		%vreg131<def> = COPY %XZR; GPR64:%vreg131
3312B		STRXui %vreg131, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg131
3328B		B <BB#40>
	    Successors according to CFG: BB#40

3344B	BB#27: derived from LLVM BB %if.end.39
	    Predecessors according to CFG: BB#25
3360B		%vreg80<def> = LDRWui <fi#8>, 0; mem:LD4[FixedStack8] GPR32:%vreg80
3376B		CBZW %vreg80, <BB#33>; GPR32:%vreg80
	    Successors according to CFG: BB#33 BB#28

3392B	BB#28: derived from LLVM BB %if.then.41
	    Predecessors according to CFG: BB#27
3408B		%vreg95<def> = LDRWui <fi#7>, 0; mem:LD4[FixedStack7] GPR32common:%vreg95
3424B		%WZR<def> = SUBSWri %vreg95, 1, 0, %NZCV<imp-def>; GPR32common:%vreg95
3440B		Bcc 10, <BB#30>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#30 BB#29

3456B	BB#29: derived from LLVM BB %if.then.44
	    Predecessors according to CFG: BB#28
3472B		%vreg96<def> = MOVi32imm 1; GPR32:%vreg96
3488B		STRWui %vreg96, <fi#7>, 0; mem:ST4[FixedStack7] GPR32:%vreg96
	    Successors according to CFG: BB#30

3504B	BB#30: derived from LLVM BB %if.end.45
	    Predecessors according to CFG: BB#28 BB#29
3520B		%vreg98<def> = LDRWui <fi#7>, 0; mem:LD4[FixedStack7] GPR32common:%vreg98
3536B		%WZR<def> = SUBSWri %vreg98, 9, 0, %NZCV<imp-def>; GPR32common:%vreg98
3552B		Bcc 13, <BB#32>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#32 BB#31

3568B	BB#31: derived from LLVM BB %if.then.48
	    Predecessors according to CFG: BB#30
3584B		%vreg99<def> = MOVi32imm 9; GPR32:%vreg99
3600B		STRWui %vreg99, <fi#7>, 0; mem:ST4[FixedStack7] GPR32:%vreg99
	    Successors according to CFG: BB#32

3616B	BB#32: derived from LLVM BB %if.end.49
	    Predecessors according to CFG: BB#30 BB#31
3632B		%vreg101<def> = ADDXri <fi#5>, 0, 0; GPR64sp:%vreg101
3648B		%vreg110<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg110
3664B		%vreg109<def> = LDRWui <fi#7>, 0; mem:LD4[FixedStack7] GPR32:%vreg109
3680B		%vreg108<def> = LDRWui <fi#12>, 0; mem:LD4[FixedStack12] GPR32:%vreg108
3696B		%vreg107<def> = LDRWui <fi#13>, 0; mem:LD4[FixedStack13] GPR32:%vreg107
3712B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3728B		%X0<def> = COPY %vreg101; GPR64sp:%vreg101
3744B		%X1<def> = COPY %vreg110; GPR64:%vreg110
3760B		%W2<def> = COPY %vreg109; GPR32:%vreg109
3776B		%W3<def> = COPY %vreg108; GPR32:%vreg108
3792B		%W4<def> = COPY %vreg107; GPR32:%vreg107
3808B		BL <ga:@BZ2_bzWriteOpen>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %W2<imp-use>, %W3<imp-use>, %W4<imp-use,kill>, %X0<imp-def>
3824B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3840B		%vreg106<def> = COPY %X0; GPR64:%vreg106
3856B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3872B		STACKMAP 7, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack0]
3888B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3904B		STRXui %vreg106, <fi#11>, 0; mem:ST8[FixedStack11] GPR64:%vreg106
3920B		B <BB#34>
	    Successors according to CFG: BB#34

3936B	BB#33: derived from LLVM BB %if.else.51
	    Predecessors according to CFG: BB#27
3952B		%vreg82<def> = ADDXri <fi#5>, 0, 0; GPR64sp:%vreg82
3968B		%vreg90<def> = ADDXri <fi#6>, 0, 0; GPR64sp:%vreg90
3984B		%vreg93<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg93
4000B		%vreg92<def> = LDRWui <fi#12>, 0; mem:LD4[FixedStack12] GPR32:%vreg92
4016B		%vreg91<def> = LDRWui <fi#14>, 0; mem:LD4[FixedStack14] GPR32:%vreg91
4032B		%vreg89<def> = LDRWui <fi#15>, 0; mem:LD4[FixedStack15] GPR32:%vreg89
4048B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4064B		%X0<def> = COPY %vreg82; GPR64sp:%vreg82
4080B		%X1<def> = COPY %vreg93; GPR64:%vreg93
4096B		%W2<def> = COPY %vreg92; GPR32:%vreg92
4112B		%W3<def> = COPY %vreg91; GPR32:%vreg91
4128B		%X4<def> = COPY %vreg90; GPR64sp:%vreg90
4144B		%W5<def> = COPY %vreg89; GPR32:%vreg89
4160B		BL <ga:@BZ2_bzReadOpen>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %W2<imp-use>, %W3<imp-use>, %X4<imp-use,kill>, %W5<imp-use,kill>, %X0<imp-def>
4176B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4192B		%vreg88<def> = COPY %X0; GPR64:%vreg88
4208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4224B		STACKMAP 8, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack0]
4240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4256B		STRXui %vreg88, <fi#11>, 0; mem:ST8[FixedStack11] GPR64:%vreg88
	    Successors according to CFG: BB#34

4272B	BB#34: derived from LLVM BB %if.end.54
	    Predecessors according to CFG: BB#33 BB#32
4288B		%vreg112<def> = LDRXui <fi#11>, 0; mem:LD8[FixedStack11] GPR64:%vreg112
4304B		CBNZX %vreg112, <BB#39>; GPR64:%vreg112
	    Successors according to CFG: BB#39 BB#35

4320B	BB#35: derived from LLVM BB %if.then.57
	    Predecessors according to CFG: BB#34
4336B		%vreg117<def> = ADRP <ga:@stdin>[TF=1]; GPR64common:%vreg117
4352B		%vreg118<def> = ADDXri %vreg117, <ga:@stdin>[TF=34], 0; GPR64sp:%vreg118 GPR64common:%vreg117
4368B		%vreg120<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg120
4384B		%vreg119<def> = LDRXui %vreg118, 0; mem:LD8[@stdin] GPR64:%vreg119 GPR64sp:%vreg118
4400B		%XZR<def> = SUBSXrr %vreg120, %vreg119, %NZCV<imp-def>; GPR64:%vreg120,%vreg119
4416B		Bcc 0, <BB#38>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#38 BB#36

4432B	BB#36: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#35
4448B		%vreg123<def> = ADRP <ga:@stdout>[TF=1]; GPR64common:%vreg123
4464B		%vreg124<def> = ADDXri %vreg123, <ga:@stdout>[TF=34], 0; GPR64sp:%vreg124 GPR64common:%vreg123
4480B		%vreg126<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg126
4496B		%vreg125<def> = LDRXui %vreg124, 0; mem:LD8[@stdout] GPR64:%vreg125 GPR64sp:%vreg124
4512B		%XZR<def> = SUBSXrr %vreg126, %vreg125, %NZCV<imp-def>; GPR64:%vreg126,%vreg125
4528B		Bcc 0, <BB#38>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#38 BB#37

4544B	BB#37: derived from LLVM BB %if.then.62
	    Predecessors according to CFG: BB#36
4560B		%vreg129<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg129
4576B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4592B		%X0<def> = COPY %vreg129; GPR64:%vreg129
4608B		BL <ga:@fclose>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
4624B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4640B		%vreg128<def,dead> = COPY %W0; GPR32all:%vreg128
4656B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4672B		STACKMAP 9, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0]
4688B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#38

4704B	BB#38: derived from LLVM BB %if.end.64
	    Predecessors according to CFG: BB#35 BB#36 BB#37
4720B		%vreg130<def> = COPY %XZR; GPR64:%vreg130
4736B		STRXui %vreg130, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg130
4752B		B <BB#40>
	    Successors according to CFG: BB#40

4768B	BB#39: derived from LLVM BB %if.end.65
	    Predecessors according to CFG: BB#34
4784B		%vreg114<def> = LDRXui <fi#11>, 0; mem:LD8[FixedStack11] GPR64:%vreg114
4800B		STRXui %vreg114, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg114
	    Successors according to CFG: BB#40

4816B	BB#40: derived from LLVM BB %return
	    Predecessors according to CFG: BB#39 BB#38 BB#26 BB#1
4832B		%vreg171<def> = ADRP <ga:@bzopen_or_bzdopen>[TF=1]; GPR64common:%vreg171
4848B		%vreg172<def> = ADDXri %vreg171, <ga:@bzopen_or_bzdopen>[TF=34], 0; GPR64sp:%vreg172 GPR64common:%vreg171
4864B		%vreg173<def> = COPY %vreg172; GPR64all:%vreg173 GPR64sp:%vreg172
4880B		%vreg174<def> = COPY %vreg26; GPR64all:%vreg174 GPR64:%vreg26
4896B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4912B		%X0<def> = COPY %vreg173; GPR64all:%vreg173
4928B		%X1<def> = COPY %vreg174; GPR64all:%vreg174
4944B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
4960B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4976B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4992B		STACKMAP 10, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0]
5008B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5024B		%vreg170<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg170
5040B		%X0<def> = COPY %vreg170; GPR64:%vreg170
5056B		RET_ReallyLR %X0<imp-use>

# End machine code for function bzopen_or_bzdopen.

********** SIMPLE REGISTER COALESCING **********
********** Function: bzopen_or_bzdopen
********** JOINING INTERVALS ***********
sw.epilog:
while.cond:
while.body:
while.body:
while.body:
cond.false:
if.end.11:
sw.bb:
sw.bb.1:
sw.bb.2:
sw.default:
if.then.8:
1024B	%vreg132<def> = COPY %vreg134; GPR32sp:%vreg132 GPR32common:%vreg134
	Considering merging to GPR32common with %vreg134 in %vreg132
		RHS = %vreg134 [1008r,1040r:0)  0@1008r
		LHS = %vreg132 [1024r,1168r:0)  0@1024r
		merge %vreg132:0@1024r into %vreg134:0@1008r --> @1008r
		erased:	1024r	%vreg132<def> = COPY %vreg134; GPR32sp:%vreg132 GPR32common:%vreg134
		updated: 1008B	%vreg132<def> = LDRSBWui %vreg133, 0; mem:LD1[%4] GPR32common:%vreg132 GPR64common:%vreg133
		updated: 1040B	%vreg135<def,dead> = SUBSWri %vreg132, 114, 0, %NZCV<imp-def>; GPR32:%vreg135 GPR32common:%vreg132
	Success: %vreg134 -> %vreg132
	Result = %vreg132 [1008r,1168r:0)  0@1008r
if.then.24:
if.end.35:
if.end.45:
if.end.54:
if.end.64:
4720B	%vreg130<def> = COPY %XZR; GPR64:%vreg130
	Considering merging %vreg130 with %XZR
		RHS = %vreg130 [4720r,4736r:0)  0@4720r
		updated: 4736B	STRXui %XZR, <fi#0>, 0; mem:ST8[FixedStack0]
	Success: %vreg130 -> %XZR
	Result = %XZR
return:
4912B	%X0<def> = COPY %vreg173; GPR64all:%vreg173
	Considering merging %vreg173 with %X0
	Can only merge into reserved registers.
4928B	%X1<def> = COPY %vreg174; GPR64all:%vreg174
	Considering merging %vreg174 with %X1
	Can only merge into reserved registers.
5040B	%X0<def> = COPY %vreg170; GPR64:%vreg170
	Considering merging %vreg170 with %X0
	Can only merge into reserved registers.
while.end:
1872B	%X0<def> = COPY %vreg49; GPR64sp:%vreg49
	Considering merging %vreg49 with %X0
	Can only merge into reserved registers.
Remat: %X0<def> = ADDXri <fi#9>, 0, 0
Shrink: %vreg49 [1792r,1872r:0)  0@1792r
All defs dead: 1792r	%vreg49<def,dead> = ADDXri <fi#9>, 0, 0; GPR64sp:%vreg49
Shrunk: %vreg49 [1792r,1792d:0)  0@1792r
Deleting dead def 1792r	%vreg49<def,dead> = ADDXri <fi#9>, 0, 0; GPR64sp:%vreg49
1888B	%X1<def> = COPY %vreg47; GPR64:%vreg47
	Considering merging %vreg47 with %X1
	Can only merge into reserved registers.
1936B	%vreg41<def,dead> = COPY %X0; GPR64all:%vreg41
	Considering merging %vreg41 with %X0
	Can only merge into reserved registers.
2064B	%X0<def> = COPY %vreg38; GPR64sp:%vreg38
	Considering merging %vreg38 with %X0
	Can only merge into reserved registers.
Remat: %X0<def> = ADDXri <fi#9>, 0, 0
Shrink: %vreg38 [1984r,2064r:0)  0@1984r
All defs dead: 1984r	%vreg38<def,dead> = ADDXri <fi#9>, 0, 0; GPR64sp:%vreg38
Shrunk: %vreg38 [1984r,1984d:0)  0@1984r
Deleting dead def 1984r	%vreg38<def,dead> = ADDXri <fi#9>, 0, 0; GPR64sp:%vreg38
2080B	%X1<def> = COPY %vreg36; GPR64sp:%vreg36
	Considering merging %vreg36 with %X1
	Can only merge into reserved registers.
2128B	%vreg37<def,dead> = COPY %X0; GPR64all:%vreg37
	Considering merging %vreg37 with %X0
	Can only merge into reserved registers.
if.then.18:
lor.lhs.false:
2336B	%X0<def> = COPY %vreg62; GPR64:%vreg62
	Considering merging %vreg62 with %X0
	Can only merge into reserved registers.
2352B	%X1<def> = COPY %vreg60; GPR64:%vreg60
	Considering merging %vreg60 with %X1
	Can only merge into reserved registers.
2400B	%vreg61<def> = COPY %W0; GPR32:%vreg61
	Considering merging %vreg61 with %W0
	Can only merge into reserved registers.
cond.end:
if.end.31:
if.end.39:
if.then.41:
if.end.49:
3728B	%X0<def> = COPY %vreg101; GPR64sp:%vreg101
	Considering merging %vreg101 with %X0
	Can only merge into reserved registers.
Remat: %X0<def> = ADDXri <fi#5>, 0, 0
Shrink: %vreg101 [3632r,3728r:0)  0@3632r
All defs dead: 3632r	%vreg101<def,dead> = ADDXri <fi#5>, 0, 0; GPR64sp:%vreg101
Shrunk: %vreg101 [3632r,3632d:0)  0@3632r
Deleting dead def 3632r	%vreg101<def,dead> = ADDXri <fi#5>, 0, 0; GPR64sp:%vreg101
3744B	%X1<def> = COPY %vreg110; GPR64:%vreg110
	Considering merging %vreg110 with %X1
	Can only merge into reserved registers.
3760B	%W2<def> = COPY %vreg109; GPR32:%vreg109
	Considering merging %vreg109 with %W2
	Can only merge into reserved registers.
3776B	%W3<def> = COPY %vreg108; GPR32:%vreg108
	Considering merging %vreg108 with %W3
	Can only merge into reserved registers.
3792B	%W4<def> = COPY %vreg107; GPR32:%vreg107
	Considering merging %vreg107 with %W4
	Can only merge into reserved registers.
3840B	%vreg106<def> = COPY %X0; GPR64:%vreg106
	Considering merging %vreg106 with %X0
	Can only merge into reserved registers.
if.then.57:
land.lhs.true:
entry:
16B	%vreg26<def> = COPY %LR; GPR64:%vreg26
	Considering merging %vreg26 with %LR
	Can only merge into reserved registers.
32B	%vreg9<def> = COPY %W3; GPR32:%vreg9
	Considering merging %vreg9 with %W3
	Can only merge into reserved registers.
48B	%vreg7<def> = COPY %X2; GPR64:%vreg7
	Considering merging %vreg7 with %X2
	Can only merge into reserved registers.
64B	%vreg5<def> = COPY %W1; GPR32:%vreg5
	Considering merging %vreg5 with %W1
	Can only merge into reserved registers.
80B	%vreg3<def> = COPY %X0; GPR64:%vreg3
	Considering merging %vreg3 with %X0
	Can only merge into reserved registers.
240B	%X0<def> = COPY %vreg24; GPR64all:%vreg24
	Considering merging %vreg24 with %X0
	Can only merge into reserved registers.
256B	%X1<def> = COPY %vreg25; GPR64all:%vreg25
	Considering merging %vreg25 with %X1
	Can only merge into reserved registers.
320B	%vreg14<def> = COPY %XZR; GPR64:%vreg14
	Considering merging %vreg14 with %XZR
		RHS = %vreg14 [320r,688r:0)  0@320r
		updated: 688B	STRXui %XZR, <fi#11>, 0; mem:ST8[FixedStack11]
		updated: 672B	STRXui %XZR, <fi#10>, 0; mem:ST8[FixedStack10]
	Success: %vreg14 -> %XZR
	Result = %XZR
336B	%vreg16<def> = COPY %WZR; GPR32:%vreg16
	Considering merging %vreg16 with %WZR
		RHS = %vreg16 [336r,592r:0)  0@336r
		updated: 592B	%vreg17<def> = UBFMWri %WZR, 0, 7; GPR32:%vreg17
	Success: %vreg16 -> %WZR
	Result = %WZR
576B	%X0<def> = COPY %vreg20; GPR64all:%vreg20
	Considering merging %vreg20 with %X0
	Can only merge into reserved registers.
608B	%W1<def> = COPY %vreg17; GPR32:%vreg17
	Considering merging %vreg17 with %W1
	Can only merge into reserved registers.
624B	%X2<def> = COPY %vreg18; GPR64:%vreg18
	Considering merging %vreg18 with %X2
	Can only merge into reserved registers.
Remat: %X2<def> = MOVi64imm 10
Shrink: %vreg18 [352r,624r:0)  0@352r
All defs dead: 352r	%vreg18<def,dead> = MOVi64imm 10; GPR64:%vreg18
Shrunk: %vreg18 [352r,352d:0)  0@352r
Deleting dead def 352r	%vreg18<def,dead> = MOVi64imm 10; GPR64:%vreg18
if.then:
816B	%vreg168<def> = COPY %XZR; GPR64:%vreg168
	Considering merging %vreg168 with %XZR
		RHS = %vreg168 [816r,832r:0)  0@816r
		updated: 832B	STRXui %XZR, <fi#0>, 0; mem:ST8[FixedStack0]
	Success: %vreg168 -> %XZR
	Result = %XZR
if.end:
cond.true.26:
cond.false.27:
if.else:
2848B	%X0<def> = COPY %vreg68; GPR64:%vreg68
	Considering merging %vreg68 with %X0
	Can only merge into reserved registers.
2864B	%X1<def> = COPY %vreg67; GPR64sp:%vreg67
	Considering merging %vreg67 with %X1
	Can only merge into reserved registers.
Remat: %X1<def> = ADDXri <fi#9>, 0, 0
Shrink: %vreg67 [2800r,2864r:0)  0@2800r
All defs dead: 2800r	%vreg67<def,dead> = ADDXri <fi#9>, 0, 0; GPR64sp:%vreg67
Shrunk: %vreg67 [2800r,2800d:0)  0@2800r
Deleting dead def 2800r	%vreg67<def,dead> = ADDXri <fi#9>, 0, 0; GPR64sp:%vreg67
2912B	%vreg66<def> = COPY %X0; GPR64:%vreg66
	Considering merging %vreg66 with %X0
	Can only merge into reserved registers.
if.else.32:
3088B	%W0<def> = COPY %vreg55; GPR32:%vreg55
	Considering merging %vreg55 with %W0
	Can only merge into reserved registers.
3104B	%X1<def> = COPY %vreg54; GPR64sp:%vreg54
	Considering merging %vreg54 with %X1
	Can only merge into reserved registers.
Remat: %X1<def> = ADDXri <fi#9>, 0, 0
Shrink: %vreg54 [3040r,3104r:0)  0@3040r
All defs dead: 3040r	%vreg54<def,dead> = ADDXri <fi#9>, 0, 0; GPR64sp:%vreg54
Shrunk: %vreg54 [3040r,3040d:0)  0@3040r
Deleting dead def 3040r	%vreg54<def,dead> = ADDXri <fi#9>, 0, 0; GPR64sp:%vreg54
3152B	%vreg53<def> = COPY %X0; GPR64:%vreg53
	Considering merging %vreg53 with %X0
	Can only merge into reserved registers.
if.then.38:
3296B	%vreg131<def> = COPY %XZR; GPR64:%vreg131
	Considering merging %vreg131 with %XZR
		RHS = %vreg131 [3296r,3312r:0)  0@3296r
		updated: 3312B	STRXui %XZR, <fi#0>, 0; mem:ST8[FixedStack0]
	Success: %vreg131 -> %XZR
	Result = %XZR
if.then.44:
if.then.48:
if.else.51:
4064B	%X0<def> = COPY %vreg82; GPR64sp:%vreg82
	Considering merging %vreg82 with %X0
	Can only merge into reserved registers.
Remat: %X0<def> = ADDXri <fi#5>, 0, 0
Shrink: %vreg82 [3952r,4064r:0)  0@3952r
All defs dead: 3952r	%vreg82<def,dead> = ADDXri <fi#5>, 0, 0; GPR64sp:%vreg82
Shrunk: %vreg82 [3952r,3952d:0)  0@3952r
Deleting dead def 3952r	%vreg82<def,dead> = ADDXri <fi#5>, 0, 0; GPR64sp:%vreg82
4080B	%X1<def> = COPY %vreg93; GPR64:%vreg93
	Considering merging %vreg93 with %X1
	Can only merge into reserved registers.
4096B	%W2<def> = COPY %vreg92; GPR32:%vreg92
	Considering merging %vreg92 with %W2
	Can only merge into reserved registers.
4112B	%W3<def> = COPY %vreg91; GPR32:%vreg91
	Considering merging %vreg91 with %W3
	Can only merge into reserved registers.
4128B	%X4<def> = COPY %vreg90; GPR64sp:%vreg90
	Considering merging %vreg90 with %X4
	Can only merge into reserved registers.
Remat: %X4<def> = ADDXri <fi#6>, 0, 0
Shrink: %vreg90 [3968r,4128r:0)  0@3968r
All defs dead: 3968r	%vreg90<def,dead> = ADDXri <fi#6>, 0, 0; GPR64sp:%vreg90
Shrunk: %vreg90 [3968r,3968d:0)  0@3968r
Deleting dead def 3968r	%vreg90<def,dead> = ADDXri <fi#6>, 0, 0; GPR64sp:%vreg90
4144B	%W5<def> = COPY %vreg89; GPR32:%vreg89
	Considering merging %vreg89 with %W5
	Can only merge into reserved registers.
4192B	%vreg88<def> = COPY %X0; GPR64:%vreg88
	Considering merging %vreg88 with %X0
	Can only merge into reserved registers.
if.then.62:
4592B	%X0<def> = COPY %vreg129; GPR64:%vreg129
	Considering merging %vreg129 with %X0
	Can only merge into reserved registers.
4640B	%vreg128<def,dead> = COPY %W0; GPR32all:%vreg128
	Considering merging %vreg128 with %W0
	Can only merge into reserved registers.
if.end.65:
4864B	%vreg173<def> = COPY %vreg172; GPR64all:%vreg173 GPR64sp:%vreg172
	Considering merging to GPR64sp with %vreg172 in %vreg173
		RHS = %vreg172 [4848r,4864r:0)  0@4848r
		LHS = %vreg173 [4864r,4912r:0)  0@4864r
		merge %vreg173:0@4864r into %vreg172:0@4848r --> @4848r
		erased:	4864r	%vreg173<def> = COPY %vreg172; GPR64all:%vreg173 GPR64sp:%vreg172
		updated: 4848B	%vreg173<def> = ADDXri %vreg171, <ga:@bzopen_or_bzdopen>[TF=34], 0; GPR64sp:%vreg173 GPR64common:%vreg171
	Success: %vreg172 -> %vreg173
	Result = %vreg173 [4848r,4912r:0)  0@4848r
4880B	%vreg174<def> = COPY %vreg26; GPR64all:%vreg174 GPR64:%vreg26
	Considering merging to GPR64 with %vreg26 in %vreg174
		RHS = %vreg26 [16r,4880r:0)  0@16r
		LHS = %vreg174 [4880r,4928r:0)  0@4880r
		merge %vreg174:0@4880r into %vreg26:0@16r --> @16r
		erased:	4880r	%vreg174<def> = COPY %vreg26; GPR64all:%vreg174 GPR64:%vreg26
		updated: 16B	%vreg174<def> = COPY %LR; GPR64:%vreg174
		updated: 208B	%vreg25<def> = COPY %vreg174; GPR64all:%vreg25 GPR64:%vreg174
	Success: %vreg26 -> %vreg174
	Result = %vreg174 [16r,4928r:0)  0@16r
2416B	%vreg58<def> = COPY %vreg61; GPR32:%vreg58,%vreg61
	Considering merging to GPR32 with %vreg61 in %vreg58
		RHS = %vreg61 [2400r,2416r:0)  0@2400r
		LHS = %vreg58 [2416r,2480r:0)  0@2416r
		merge %vreg58:0@2416r into %vreg61:0@2400r --> @2400r
		erased:	2416r	%vreg58<def> = COPY %vreg61; GPR32:%vreg58,%vreg61
		updated: 2400B	%vreg58<def> = COPY %W0; GPR32:%vreg58
	Success: %vreg61 -> %vreg58
	Result = %vreg58 [2400r,2480r:0)  0@2400r
2736B	%vreg2<def> = COPY %vreg175; GPR64:%vreg2,%vreg175
	Considering merging to GPR64 with %vreg2 in %vreg175
		RHS = %vreg2 [2736r,2752r:0)  0@2736r
		LHS = %vreg175 [2608r,2640B:1)[2704r,2720B:0)[2720B,2736r:2)  0@2704r 1@2608r 2@2720B-phi
		merge %vreg2:0@2736r into %vreg175:2@2720B --> @2720B
		erased:	2736r	%vreg2<def> = COPY %vreg175; GPR64:%vreg2,%vreg175
		updated: 2752B	STRXui %vreg175, <fi#10>, 0; mem:ST8[FixedStack10] GPR64:%vreg175
	Success: %vreg2 -> %vreg175
	Result = %vreg175 [2608r,2640B:1)[2704r,2720B:0)[2720B,2752r:2)  0@2704r 1@2608r 2@2720B-phi
96B	%vreg4<def> = COPY %vreg3; GPR64:%vreg4,%vreg3
	Considering merging to GPR64 with %vreg3 in %vreg4
		RHS = %vreg3 [80r,96r:0)  0@80r
		LHS = %vreg4 [96r,448r:0)  0@96r
		merge %vreg4:0@96r into %vreg3:0@80r --> @80r
		erased:	96r	%vreg4<def> = COPY %vreg3; GPR64:%vreg4,%vreg3
		updated: 80B	%vreg4<def> = COPY %X0; GPR64:%vreg4
	Success: %vreg3 -> %vreg4
	Result = %vreg4 [80r,448r:0)  0@80r
112B	%vreg6<def> = COPY %vreg5; GPR32:%vreg6,%vreg5
	Considering merging to GPR32 with %vreg5 in %vreg6
		RHS = %vreg5 [64r,112r:0)  0@64r
		LHS = %vreg6 [112r,464r:0)  0@112r
		merge %vreg6:0@112r into %vreg5:0@64r --> @64r
		erased:	112r	%vreg6<def> = COPY %vreg5; GPR32:%vreg6,%vreg5
		updated: 64B	%vreg6<def> = COPY %W1; GPR32:%vreg6
	Success: %vreg5 -> %vreg6
	Result = %vreg6 [64r,464r:0)  0@64r
128B	%vreg8<def> = COPY %vreg7; GPR64:%vreg8,%vreg7
	Considering merging to GPR64 with %vreg7 in %vreg8
		RHS = %vreg7 [48r,128r:0)  0@48r
		LHS = %vreg8 [128r,480r:0)  0@128r
		merge %vreg8:0@128r into %vreg7:0@48r --> @48r
		erased:	128r	%vreg8<def> = COPY %vreg7; GPR64:%vreg8,%vreg7
		updated: 48B	%vreg8<def> = COPY %X2; GPR64:%vreg8
	Success: %vreg7 -> %vreg8
	Result = %vreg8 [48r,480r:0)  0@48r
144B	%vreg10<def> = COPY %vreg9; GPR32:%vreg10,%vreg9
	Considering merging to GPR32 with %vreg9 in %vreg10
		RHS = %vreg9 [32r,144r:0)  0@32r
		LHS = %vreg10 [144r,496r:0)  0@144r
		merge %vreg10:0@144r into %vreg9:0@32r --> @32r
		erased:	144r	%vreg10<def> = COPY %vreg9; GPR32:%vreg10,%vreg9
		updated: 32B	%vreg10<def> = COPY %W3; GPR32:%vreg10
	Success: %vreg9 -> %vreg10
	Result = %vreg10 [32r,496r:0)  0@32r
192B	%vreg24<def> = COPY %vreg23; GPR64all:%vreg24 GPR64sp:%vreg23
	Considering merging to GPR64sp with %vreg23 in %vreg24
		RHS = %vreg23 [176r,192r:0)  0@176r
		LHS = %vreg24 [192r,240r:0)  0@192r
		merge %vreg24:0@192r into %vreg23:0@176r --> @176r
		erased:	192r	%vreg24<def> = COPY %vreg23; GPR64all:%vreg24 GPR64sp:%vreg23
		updated: 176B	%vreg24<def> = ADDXri %vreg22, <ga:@bzopen_or_bzdopen>[TF=34], 0; GPR64sp:%vreg24 GPR64common:%vreg22
	Success: %vreg23 -> %vreg24
	Result = %vreg24 [176r,240r:0)  0@176r
208B	%vreg25<def> = COPY %vreg174; GPR64all:%vreg25 GPR64:%vreg174
	Considering merging to GPR64 with %vreg174 in %vreg25
		RHS = %vreg174 [16r,4928r:0)  0@16r
		LHS = %vreg25 [208r,256r:0)  0@208r
		merge %vreg25:0@208r into %vreg174:0@16r --> @16r
		erased:	208r	%vreg25<def> = COPY %vreg174; GPR64all:%vreg25 GPR64:%vreg174
		updated: 16B	%vreg25<def> = COPY %LR; GPR64:%vreg25
		updated: 4928B	%X1<def> = COPY %vreg25; GPR64:%vreg25
	Success: %vreg174 -> %vreg25
	Result = %vreg25 [16r,4928r:0)  0@16r
544B	%vreg20<def> = COPY %vreg19; GPR64all:%vreg20 GPR64sp:%vreg19
	Considering merging to GPR64sp with %vreg19 in %vreg20
		RHS = %vreg19 [368r,544r:0)  0@368r
		LHS = %vreg20 [544r,576r:0)  0@544r
		merge %vreg20:0@544r into %vreg19:0@368r --> @368r
		erased:	544r	%vreg20<def> = COPY %vreg19; GPR64all:%vreg20 GPR64sp:%vreg19
		updated: 368B	%vreg20<def> = ADDXri <fi#9>, 0, 0; GPR64sp:%vreg20
	Success: %vreg19 -> %vreg20
	Result = %vreg20 [368r,576r:0)  0@368r
2608B	%vreg175<def> = COPY %vreg76; GPR64:%vreg175,%vreg76
	Considering merging to GPR64 with %vreg76 in %vreg175
		RHS = %vreg76 [2592r,2608r:0)  0@2592r
		LHS = %vreg175 [2608r,2640B:1)[2704r,2720B:0)[2720B,2752r:2)  0@2704r 1@2608r 2@2720B-phi
		merge %vreg175:1@2608r into %vreg76:0@2592r --> @2592r
		erased:	2608r	%vreg175<def> = COPY %vreg76; GPR64:%vreg175,%vreg76
		updated: 2592B	%vreg175<def> = LDRXui %vreg75, 0; mem:LD8[@stdout] GPR64:%vreg175 GPR64sp:%vreg75
	Success: %vreg76 -> %vreg175
	Result = %vreg175 [2592r,2640B:1)[2704r,2720B:0)[2720B,2752r:2)  0@2704r 1@2592r 2@2720B-phi
2704B	%vreg175<def> = COPY %vreg73; GPR64:%vreg175,%vreg73
	Considering merging to GPR64 with %vreg73 in %vreg175
		RHS = %vreg73 [2688r,2704r:0)  0@2688r
		LHS = %vreg175 [2592r,2640B:1)[2704r,2720B:0)[2720B,2752r:2)  0@2704r 1@2592r 2@2720B-phi
		merge %vreg175:0@2704r into %vreg73:0@2688r --> @2688r
		erased:	2704r	%vreg175<def> = COPY %vreg73; GPR64:%vreg175,%vreg73
		updated: 2688B	%vreg175<def> = LDRXui %vreg72, 0; mem:LD8[@stdin] GPR64:%vreg175 GPR64sp:%vreg72
	Success: %vreg73 -> %vreg175
	Result = %vreg175 [2592r,2640B:1)[2688r,2720B:0)[2720B,2752r:2)  0@2688r 1@2592r 2@2720B-phi
4912B	%X0<def> = COPY %vreg173; GPR64sp:%vreg173
	Considering merging %vreg173 with %X0
	Can only merge into reserved registers.
4928B	%X1<def> = COPY %vreg25; GPR64:%vreg25
	Considering merging %vreg25 with %X1
	Can only merge into reserved registers.
240B	%X0<def> = COPY %vreg24; GPR64sp:%vreg24
	Considering merging %vreg24 with %X0
	Can only merge into reserved registers.
256B	%X1<def> = COPY %vreg25; GPR64:%vreg25
	Considering merging %vreg25 with %X1
	Can only merge into reserved registers.
576B	%X0<def> = COPY %vreg20; GPR64sp:%vreg20
	Considering merging %vreg20 with %X0
	Can only merge into reserved registers.
Remat: %X0<def> = ADDXri <fi#9>, 0, 0
Shrink: %vreg20 [368r,576r:0)  0@368r
All defs dead: 368r	%vreg20<def,dead> = ADDXri <fi#9>, 0, 0; GPR64sp:%vreg20
Shrunk: %vreg20 [368r,368d:0)  0@368r
Deleting dead def 368r	%vreg20<def,dead> = ADDXri <fi#9>, 0, 0; GPR64sp:%vreg20
4928B	%X1<def> = COPY %vreg25; GPR64:%vreg25
	Considering merging %vreg25 with %X1
	Can only merge into reserved registers.
256B	%X1<def> = COPY %vreg25; GPR64:%vreg25
	Considering merging %vreg25 with %X1
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
W30 [0B,16r:0)[272r,272d:20)[416e,416d:10)[640r,640d:21)[1904r,1904d:18)[2016e,2016d:9)[2096r,2096d:19)[2160e,2160d:8)[2368r,2368d:16)[2448e,2448d:7)[2880r,2880d:15)[2944e,2944d:6)[3120r,3120d:17)[3184e,3184d:5)[3808r,3808d:13)[3872e,3872d:4)[4160r,4160d:14)[4224e,4224d:3)[4608r,4608d:12)[4672e,4672d:2)[4944r,4944d:11)[4992e,4992d:1)  0@0B-phi 1@4992e 2@4672e 3@4224e 4@3872e 5@3184e 6@2944e 7@2448e 8@2160e 9@2016e 10@416e 11@4944r 12@4608r 13@3808r 14@4160r 15@2880r 16@2368r 17@3120r 18@1904r 19@2096r 20@272r 21@640r
WZR [1488r,1488d:0)[1824r,1824d:3)[3424r,3424d:2)[3536r,3536d:1)[4400r,4400d:5)[4512r,4512d:4)  0@1488r 1@3536r 2@3424r 3@1824r 4@4512r 5@4400r
W0 [0B,80r:0)[240r,272r:19)[576r,640r:20)[1872r,1904r:16)[1904r,1936r:15)[2064r,2096r:18)[2096r,2128r:17)[2336r,2368r:13)[2368r,2400r:2)[2848r,2880r:12)[2880r,2912r:11)[3088r,3120r:3)[3120r,3152r:14)[3728r,3808r:8)[3808r,3840r:7)[4064r,4160r:10)[4160r,4192r:9)[4592r,4608r:6)[4608r,4640r:1)[4912r,4944r:4)[5040r,5056r:5)  0@0B-phi 1@4608r 2@2368r 3@3088r 4@4912r 5@5040r 6@4592r 7@3808r 8@3728r 9@4160r 10@4064r 11@2880r 12@2848r 13@2336r 14@3120r 15@1904r 16@1872r 17@2096r 18@2064r 19@240r 20@576r
W1 [0B,64r:0)[256r,272r:10)[608r,640r:1)[1888r,1904r:8)[2080r,2096r:9)[2352r,2368r:6)[2864r,2880r:5)[3104r,3120r:7)[3744r,3808r:3)[4080r,4160r:4)[4928r,4944r:2)  0@0B-phi 1@608r 2@4928r 3@3744r 4@4080r 5@2864r 6@2352r 7@3104r 8@1888r 9@2080r 10@256r
W2 [0B,48r:0)[624r,640r:3)[3760r,3808r:1)[4096r,4160r:2)  0@0B-phi 1@3760r 2@4096r 3@624r
W3 [0B,32r:0)[3776r,3808r:1)[4112r,4160r:2)  0@0B-phi 1@3776r 2@4112r
%vreg4 [80r,448r:0)  0@80r
%vreg6 [64r,464r:0)  0@64r
%vreg8 [48r,480r:0)  0@48r
%vreg10 [32r,496r:0)  0@32r
%vreg12 [768r,784r:0)  0@768r
%vreg13 [304r,720r:0)  0@304r
%vreg17 [592r,608r:0)  0@592r
%vreg21 [384r,512r:0)  0@384r
%vreg22 [160r,176r:0)  0@160r
%vreg24 [176r,240r:0)  0@176r
%vreg25 [16r,4928r:0)  0@16r
%vreg28 [944r,960r:0)  0@944r
%vreg30 [928r,944r:0)  0@928r
%vreg31 [912r,928r:0)  0@912r
%vreg33 [2192r,2208r:0)  0@2192r
%vreg35 [1952r,1968r:0)  0@1952r
%vreg36 [1968r,2080r:0)  0@1968r
%vreg37 [2128r,2128d:0)  0@2128r
%vreg41 [1936r,1936d:0)  0@1936r
%vreg43 [1728r,1744r:0)  0@1728r
%vreg44 [1744r,1840r:0)  0@1744r
%vreg45 [1760r,1776r:0)  0@1760r
%vreg46 [1776r,1840r:0)  0@1776r
%vreg47 [1840r,1888r:0)  0@1840r
%vreg48 [1808r,1824r:0)  0@1808r
%vreg53 [3152r,3216r:0)  0@3152r
%vreg55 [3056r,3088r:0)  0@3056r
%vreg57 [2240r,2256r:0)  0@2240r
%vreg58 [2400r,2480r:0)  0@2400r
%vreg60 [2320r,2352r:0)  0@2320r
%vreg62 [2288r,2336r:0)  0@2288r
%vreg66 [2912r,2976r:0)  0@2912r
%vreg68 [2816r,2848r:0)  0@2816r
%vreg70 [2512r,2528r:0)  0@2512r
%vreg71 [2656r,2672r:0)  0@2656r
%vreg72 [2672r,2688r:0)  0@2672r
%vreg74 [2560r,2576r:0)  0@2560r
%vreg75 [2576r,2592r:0)  0@2576r
%vreg78 [3248r,3264r:0)  0@3248r
%vreg80 [3360r,3376r:0)  0@3360r
%vreg88 [4192r,4256r:0)  0@4192r
%vreg89 [4032r,4144r:0)  0@4032r
%vreg91 [4016r,4112r:0)  0@4016r
%vreg92 [4000r,4096r:0)  0@4000r
%vreg93 [3984r,4080r:0)  0@3984r
%vreg95 [3408r,3424r:0)  0@3408r
%vreg96 [3472r,3488r:0)  0@3472r
%vreg98 [3520r,3536r:0)  0@3520r
%vreg99 [3584r,3600r:0)  0@3584r
%vreg106 [3840r,3904r:0)  0@3840r
%vreg107 [3696r,3792r:0)  0@3696r
%vreg108 [3680r,3776r:0)  0@3680r
%vreg109 [3664r,3760r:0)  0@3664r
%vreg110 [3648r,3744r:0)  0@3648r
%vreg112 [4288r,4304r:0)  0@4288r
%vreg114 [4784r,4800r:0)  0@4784r
%vreg117 [4336r,4352r:0)  0@4336r
%vreg118 [4352r,4384r:0)  0@4352r
%vreg119 [4384r,4400r:0)  0@4384r
%vreg120 [4368r,4400r:0)  0@4368r
%vreg123 [4448r,4464r:0)  0@4448r
%vreg124 [4464r,4496r:0)  0@4464r
%vreg125 [4496r,4512r:0)  0@4496r
%vreg126 [4480r,4512r:0)  0@4480r
%vreg128 [4640r,4640d:0)  0@4640r
%vreg129 [4560r,4592r:0)  0@4560r
%vreg132 [1008r,1168r:0)  0@1008r
%vreg133 [992r,1008r:0)  0@992r
%vreg135 [1040r,1040d:0)  0@1040r
%vreg136 [1104r,1104d:0)  0@1104r
%vreg137 [1168r,1168d:0)  0@1168r
%vreg138 [1344r,1360r:0)  0@1344r
%vreg139 [1280r,1296r:0)  0@1280r
%vreg142 [1472r,1488r:0)  0@1472r
%vreg146 [1456r,1472r:0)  0@1456r
%vreg147 [1440r,1456r:0)  0@1440r
%vreg158 [1568r,1584r:0)  0@1568r
%vreg162 [1552r,1568r:0)  0@1552r
%vreg163 [1536r,1552r:0)  0@1536r
%vreg166 [1664r,1680r:0)  0@1664r
%vreg167 [1648r,1664r:0)  0@1648r
%vreg170 [5024r,5040r:0)  0@5024r
%vreg171 [4832r,4848r:0)  0@4832r
%vreg173 [4848r,4912r:0)  0@4848r
%vreg175 [2592r,2640B:1)[2688r,2720B:0)[2720B,2752r:2)  0@2688r 1@2592r 2@2720B-phi
RegMasks: 272r 640r 1904r 2096r 2368r 2880r 3120r 3808r 4160r 4608r 4944r
********** MACHINEINSTRS **********
# Machine code for function bzopen_or_bzdopen: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=4, align=4, at location [SP]
  fi#3: size=8, align=8, at location [SP]
  fi#4: size=4, align=4, at location [SP]
  fi#5: size=4, align=4, at location [SP]
  fi#6: size=5000, align=16, at location [SP]
  fi#7: size=4, align=4, at location [SP]
  fi#8: size=4, align=4, at location [SP]
  fi#9: size=10, align=1, at location [SP]
  fi#10: size=8, align=8, at location [SP]
  fi#11: size=8, align=8, at location [SP]
  fi#12: size=4, align=4, at location [SP]
  fi#13: size=4, align=4, at location [SP]
  fi#14: size=4, align=4, at location [SP]
  fi#15: size=4, align=4, at location [SP]
Function Live Ins: %X0 in %vreg3, %W1 in %vreg5, %X2 in %vreg7, %W3 in %vreg9, %LR in %vreg26

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %W1 %X2 %W3 %LR
16B		%vreg25<def> = COPY %LR; GPR64:%vreg25
32B		%vreg10<def> = COPY %W3; GPR32:%vreg10
48B		%vreg8<def> = COPY %X2; GPR64:%vreg8
64B		%vreg6<def> = COPY %W1; GPR32:%vreg6
80B		%vreg4<def> = COPY %X0; GPR64:%vreg4
160B		%vreg22<def> = ADRP <ga:@bzopen_or_bzdopen>[TF=1]; GPR64common:%vreg22
176B		%vreg24<def> = ADDXri %vreg22, <ga:@bzopen_or_bzdopen>[TF=34], 0; GPR64sp:%vreg24 GPR64common:%vreg22
224B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
240B		%X0<def> = COPY %vreg24; GPR64sp:%vreg24
256B		%X1<def> = COPY %vreg25; GPR64:%vreg25
272B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
288B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
304B		%vreg13<def> = MOVi32imm 30; GPR32:%vreg13
384B		%vreg21<def> = MOVi32imm 9; GPR32:%vreg21
400B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
416B		STACKMAP 0, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, %vreg6, 0, <fi#2>, 0, 0, <fi#10>, 0, %vreg8, 0, <fi#3>, 0, 0, <fi#9>, 0, 0, <fi#15>, 0, %vreg10, 0, <fi#4>, 0, %vreg4, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack2](align=4) LD8[FixedStack10] LD8[FixedStack3] LD8[FixedStack9](align=1) LD8[FixedStack15](align=4) LD8[FixedStack4](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4) GPR32:%vreg6,%vreg10 GPR64:%vreg8,%vreg4
432B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
448B		STRXui %vreg4, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg4
464B		STRWui %vreg6, <fi#2>, 0; mem:ST4[FixedStack2] GPR32:%vreg6
480B		STRXui %vreg8, <fi#3>, 0; mem:ST8[FixedStack3] GPR64:%vreg8
496B		STRWui %vreg10, <fi#4>, 0; mem:ST4[FixedStack4] GPR32:%vreg10
512B		STRWui %vreg21, <fi#7>, 0; mem:ST4[FixedStack7] GPR32:%vreg21
528B		STRWui %WZR, <fi#8>, 0; mem:ST4[FixedStack8]
560B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
576B		%X0<def> = ADDXri <fi#9>, 0, 0
592B		%vreg17<def> = UBFMWri %WZR, 0, 7; GPR32:%vreg17
608B		%W1<def> = COPY %vreg17; GPR32:%vreg17
624B		%X2<def> = MOVi64imm 10
640B		BL <MCSym=memset>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %X2<imp-use>
656B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
672B		STRXui %XZR, <fi#10>, 0; mem:ST8[FixedStack10]
688B		STRXui %XZR, <fi#11>, 0; mem:ST8[FixedStack11]
704B		STRWui %WZR, <fi#12>, 0; mem:ST4[FixedStack12]
720B		STRWui %vreg13, <fi#13>, 0; mem:ST4[FixedStack13] GPR32:%vreg13
736B		STRWui %WZR, <fi#14>, 0; mem:ST4[FixedStack14]
752B		STRWui %WZR, <fi#15>, 0; mem:ST4[FixedStack15]
768B		%vreg12<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg12
784B		CBNZX %vreg12, <BB#2>; GPR64:%vreg12
	    Successors according to CFG: BB#2 BB#1

800B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
832B		STRXui %XZR, <fi#0>, 0; mem:ST8[FixedStack0]
848B		B <BB#40>
	    Successors according to CFG: BB#40

864B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0
880B		B <BB#3>
	    Successors according to CFG: BB#3

896B	BB#3: derived from LLVM BB %while.cond
	    Predecessors according to CFG: BB#2 BB#14
912B		%vreg31<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg31
928B		%vreg30<def> = LDRBBui %vreg31, 0; mem:LD1[%2] GPR32:%vreg30 GPR64common:%vreg31
944B		%vreg28<def> = UBFMWri %vreg30, 0, 7; GPR32:%vreg28,%vreg30
960B		CBZW %vreg28, <BB#15>; GPR32:%vreg28
	    Successors according to CFG: BB#15 BB#4

976B	BB#4: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#3
992B		%vreg133<def> = LDRXui <fi#3>, 0; mem:LD8[%mode.addr] GPR64common:%vreg133
1008B		%vreg132<def> = LDRSBWui %vreg133, 0; mem:LD1[%4] GPR32common:%vreg132 GPR64common:%vreg133
1040B		%vreg135<def,dead> = SUBSWri %vreg132, 114, 0, %NZCV<imp-def>; GPR32:%vreg135 GPR32common:%vreg132
1056B		Bcc 0, <BB#7>, %NZCV<imp-use,kill>
1072B		B <BB#5>
	    Successors according to CFG: BB#7 BB#5

1088B	BB#5: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#4
1104B		%vreg136<def,dead> = SUBSWri %vreg132, 115, 0, %NZCV<imp-def>; GPR32:%vreg136 GPR32common:%vreg132
1120B		Bcc 0, <BB#9>, %NZCV<imp-use,kill>
1136B		B <BB#6>
	    Successors according to CFG: BB#9 BB#6

1152B	BB#6: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#5
1168B		%vreg137<def,dead> = SUBSWri %vreg132, 119, 0, %NZCV<imp-def>; GPR32:%vreg137 GPR32common:%vreg132
1184B		Bcc 0, <BB#8>, %NZCV<imp-use,kill>
1200B		B <BB#10>
	    Successors according to CFG: BB#8 BB#10

1216B	BB#7: derived from LLVM BB %sw.bb
	    Predecessors according to CFG: BB#4
1232B		STRWui %WZR, <fi#8>, 0; mem:ST4[FixedStack8]
1248B		B <BB#14>
	    Successors according to CFG: BB#14

1264B	BB#8: derived from LLVM BB %sw.bb.1
	    Predecessors according to CFG: BB#6
1280B		%vreg139<def> = MOVi32imm 1; GPR32:%vreg139
1296B		STRWui %vreg139, <fi#8>, 0; mem:ST4[FixedStack8] GPR32:%vreg139
1312B		B <BB#14>
	    Successors according to CFG: BB#14

1328B	BB#9: derived from LLVM BB %sw.bb.2
	    Predecessors according to CFG: BB#5
1344B		%vreg138<def> = MOVi32imm 1; GPR32:%vreg138
1360B		STRWui %vreg138, <fi#14>, 0; mem:ST4[FixedStack14] GPR32:%vreg138
1376B		B <BB#14>
	    Successors according to CFG: BB#14

1392B	BB#10: derived from LLVM BB %sw.default
	    Predecessors according to CFG: BB#6
1408B		B <BB#11>
	    Successors according to CFG: BB#11

1424B	BB#11: derived from LLVM BB %cond.false
	    Predecessors according to CFG: BB#10
1440B		%vreg147<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg147
1456B		%vreg146<def> = LDRSBWui %vreg147, 0; mem:LD1[%8] GPR32common:%vreg146 GPR64common:%vreg147
1472B		%vreg142<def> = SUBWri %vreg146, 48, 0; GPR32sp:%vreg142 GPR32common:%vreg146
1488B		%WZR<def> = SUBSWri %vreg142, 10, 0, %NZCV<imp-def>; GPR32sp:%vreg142
1504B		Bcc 2, <BB#13>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#13 BB#12

1520B	BB#12: derived from LLVM BB %if.then.8
	    Predecessors according to CFG: BB#11
1536B		%vreg163<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg163
1552B		%vreg162<def> = LDRSBWui %vreg163, 0; mem:LD1[%10] GPR32common:%vreg162 GPR64common:%vreg163
1568B		%vreg158<def> = SUBWri %vreg162, 48, 0; GPR32common:%vreg158,%vreg162
1584B		STRWui %vreg158, <fi#7>, 0; mem:ST4[FixedStack7] GPR32common:%vreg158
	    Successors according to CFG: BB#13

1600B	BB#13: derived from LLVM BB %if.end.11
	    Predecessors according to CFG: BB#11 BB#12
1616B		B <BB#14>
	    Successors according to CFG: BB#14

1632B	BB#14: derived from LLVM BB %sw.epilog
	    Predecessors according to CFG: BB#9 BB#8 BB#7 BB#13
1648B		%vreg167<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg167
1664B		%vreg166<def> = ADDXri %vreg167, 1, 0; GPR64common:%vreg166,%vreg167
1680B		STRXui %vreg166, <fi#3>, 0; mem:ST8[FixedStack3] GPR64common:%vreg166
1696B		B <BB#3>
	    Successors according to CFG: BB#3

1712B	BB#15: derived from LLVM BB %while.end
	    Predecessors according to CFG: BB#3
1728B		%vreg43<def> = ADRP <ga:@bzlib__str_6_w_>[TF=1]; GPR64common:%vreg43
1744B		%vreg44<def> = ADDXri %vreg43, <ga:@bzlib__str_6_w_>[TF=34], 0; GPR64common:%vreg44,%vreg43
1760B		%vreg45<def> = ADRP <ga:@bzlib__str_7_r_>[TF=1]; GPR64common:%vreg45
1776B		%vreg46<def> = ADDXri %vreg45, <ga:@bzlib__str_7_r_>[TF=34], 0; GPR64common:%vreg46,%vreg45
1808B		%vreg48<def> = LDRWui <fi#8>, 0; mem:LD4[FixedStack8] GPR32common:%vreg48
1824B		%WZR<def> = SUBSWri %vreg48, 0, 0, %NZCV<imp-def>; GPR32common:%vreg48
1840B		%vreg47<def> = CSELXr %vreg44, %vreg46, 1, %NZCV<imp-use,kill>; GPR64:%vreg47 GPR64common:%vreg44,%vreg46
1856B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1872B		%X0<def> = ADDXri <fi#9>, 0, 0
1888B		%X1<def> = COPY %vreg47; GPR64:%vreg47
1904B		BL <ga:@strcat>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %X0<imp-def>
1920B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1936B		%vreg41<def,dead> = COPY %X0; GPR64all:%vreg41
1952B		%vreg35<def> = ADRP <ga:@bzlib__str_8_b_>[TF=1]; GPR64common:%vreg35
1968B		%vreg36<def> = ADDXri %vreg35, <ga:@bzlib__str_8_b_>[TF=34], 0; GPR64sp:%vreg36 GPR64common:%vreg35
2000B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2016B		STACKMAP 2, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#2>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, 0, <fi#15>, 0, 0, <fi#4>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack2](align=4) LD8[FixedStack10] LD8[FixedStack9](align=1) LD8[FixedStack15](align=4) LD8[FixedStack4](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)
2032B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2048B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2064B		%X0<def> = ADDXri <fi#9>, 0, 0
2080B		%X1<def> = COPY %vreg36; GPR64sp:%vreg36
2096B		BL <ga:@strcat>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %X0<imp-def>
2112B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2128B		%vreg37<def,dead> = COPY %X0; GPR64all:%vreg37
2144B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2160B		STACKMAP 3, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#2>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, 0, <fi#15>, 0, 0, <fi#4>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack2](align=4) LD8[FixedStack10] LD8[FixedStack9](align=1) LD8[FixedStack15](align=4) LD8[FixedStack4](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)
2176B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2192B		%vreg33<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg33
2208B		CBNZW %vreg33, <BB#24>; GPR32:%vreg33
	    Successors according to CFG: BB#24 BB#16

2224B	BB#16: derived from LLVM BB %if.then.18
	    Predecessors according to CFG: BB#15
2240B		%vreg57<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg57
2256B		CBZX %vreg57, <BB#18>; GPR64:%vreg57
	    Successors according to CFG: BB#18 BB#17

2272B	BB#17: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#16
2288B		%vreg62<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg62
2304B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2320B		%vreg60<def> = MOVaddr <ga:@bzlib__str_9_>[TF=1], <ga:@bzlib__str_9_>[TF=34]; GPR64:%vreg60
2336B		%X0<def> = COPY %vreg62; GPR64:%vreg62
2352B		%X1<def> = COPY %vreg60; GPR64:%vreg60
2368B		BL <ga:@strcmp>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %SP<imp-def>, %W0<imp-def>
2384B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2400B		%vreg58<def> = COPY %W0; GPR32:%vreg58
2432B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2448B		STACKMAP 4, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, 0, <fi#15>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack9](align=1) LD8[FixedStack15](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)
2464B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2480B		CBNZW %vreg58, <BB#22>; GPR32:%vreg58
	    Successors according to CFG: BB#22 BB#18

2496B	BB#18: derived from LLVM BB %if.then.24
	    Predecessors according to CFG: BB#16 BB#17
2512B		%vreg70<def> = LDRWui <fi#8>, 0; mem:LD4[FixedStack8] GPR32:%vreg70
2528B		CBZW %vreg70, <BB#20>; GPR32:%vreg70
	    Successors according to CFG: BB#20 BB#19

2544B	BB#19: derived from LLVM BB %cond.true.26
	    Predecessors according to CFG: BB#18
2560B		%vreg74<def> = ADRP <ga:@stdout>[TF=1]; GPR64common:%vreg74
2576B		%vreg75<def> = ADDXri %vreg74, <ga:@stdout>[TF=34], 0; GPR64sp:%vreg75 GPR64common:%vreg74
2592B		%vreg175<def> = LDRXui %vreg75, 0; mem:LD8[@stdout] GPR64:%vreg175 GPR64sp:%vreg75
2624B		B <BB#21>
	    Successors according to CFG: BB#21

2640B	BB#20: derived from LLVM BB %cond.false.27
	    Predecessors according to CFG: BB#18
2656B		%vreg71<def> = ADRP <ga:@stdin>[TF=1]; GPR64common:%vreg71
2672B		%vreg72<def> = ADDXri %vreg71, <ga:@stdin>[TF=34], 0; GPR64sp:%vreg72 GPR64common:%vreg71
2688B		%vreg175<def> = LDRXui %vreg72, 0; mem:LD8[@stdin] GPR64:%vreg175 GPR64sp:%vreg72
	    Successors according to CFG: BB#21

2720B	BB#21: derived from LLVM BB %cond.end
	    Predecessors according to CFG: BB#20 BB#19
2752B		STRXui %vreg175, <fi#10>, 0; mem:ST8[FixedStack10] GPR64:%vreg175
2768B		B <BB#23>
	    Successors according to CFG: BB#23

2784B	BB#22: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#17
2816B		%vreg68<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg68
2832B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2848B		%X0<def> = COPY %vreg68; GPR64:%vreg68
2864B		%X1<def> = ADDXri <fi#9>, 0, 0
2880B		BL <ga:@fopen>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %X0<imp-def>
2896B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2912B		%vreg66<def> = COPY %X0; GPR64:%vreg66
2928B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2944B		STACKMAP 5, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#15>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack15](align=4) LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)
2960B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2976B		STRXui %vreg66, <fi#10>, 0; mem:ST8[FixedStack10] GPR64:%vreg66
	    Successors according to CFG: BB#23

2992B	BB#23: derived from LLVM BB %if.end.31
	    Predecessors according to CFG: BB#22 BB#21
3008B		B <BB#25>
	    Successors according to CFG: BB#25

3024B	BB#24: derived from LLVM BB %if.else.32
	    Predecessors according to CFG: BB#15
3056B		%vreg55<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg55
3072B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3088B		%W0<def> = COPY %vreg55; GPR32:%vreg55
3104B		%X1<def> = ADDXri <fi#9>, 0, 0
3120B		BL <ga:@fdopen>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use>, %X0<imp-def>
3136B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3152B		%vreg53<def> = COPY %X0; GPR64:%vreg53
3168B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3184B		STACKMAP 6, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#15>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack15](align=4) LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)
3200B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3216B		STRXui %vreg53, <fi#10>, 0; mem:ST8[FixedStack10] GPR64:%vreg53
	    Successors according to CFG: BB#25

3232B	BB#25: derived from LLVM BB %if.end.35
	    Predecessors according to CFG: BB#24 BB#23
3248B		%vreg78<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg78
3264B		CBNZX %vreg78, <BB#27>; GPR64:%vreg78
	    Successors according to CFG: BB#27 BB#26

3280B	BB#26: derived from LLVM BB %if.then.38
	    Predecessors according to CFG: BB#25
3312B		STRXui %XZR, <fi#0>, 0; mem:ST8[FixedStack0]
3328B		B <BB#40>
	    Successors according to CFG: BB#40

3344B	BB#27: derived from LLVM BB %if.end.39
	    Predecessors according to CFG: BB#25
3360B		%vreg80<def> = LDRWui <fi#8>, 0; mem:LD4[FixedStack8] GPR32:%vreg80
3376B		CBZW %vreg80, <BB#33>; GPR32:%vreg80
	    Successors according to CFG: BB#33 BB#28

3392B	BB#28: derived from LLVM BB %if.then.41
	    Predecessors according to CFG: BB#27
3408B		%vreg95<def> = LDRWui <fi#7>, 0; mem:LD4[FixedStack7] GPR32common:%vreg95
3424B		%WZR<def> = SUBSWri %vreg95, 1, 0, %NZCV<imp-def>; GPR32common:%vreg95
3440B		Bcc 10, <BB#30>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#30 BB#29

3456B	BB#29: derived from LLVM BB %if.then.44
	    Predecessors according to CFG: BB#28
3472B		%vreg96<def> = MOVi32imm 1; GPR32:%vreg96
3488B		STRWui %vreg96, <fi#7>, 0; mem:ST4[FixedStack7] GPR32:%vreg96
	    Successors according to CFG: BB#30

3504B	BB#30: derived from LLVM BB %if.end.45
	    Predecessors according to CFG: BB#28 BB#29
3520B		%vreg98<def> = LDRWui <fi#7>, 0; mem:LD4[FixedStack7] GPR32common:%vreg98
3536B		%WZR<def> = SUBSWri %vreg98, 9, 0, %NZCV<imp-def>; GPR32common:%vreg98
3552B		Bcc 13, <BB#32>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#32 BB#31

3568B	BB#31: derived from LLVM BB %if.then.48
	    Predecessors according to CFG: BB#30
3584B		%vreg99<def> = MOVi32imm 9; GPR32:%vreg99
3600B		STRWui %vreg99, <fi#7>, 0; mem:ST4[FixedStack7] GPR32:%vreg99
	    Successors according to CFG: BB#32

3616B	BB#32: derived from LLVM BB %if.end.49
	    Predecessors according to CFG: BB#30 BB#31
3648B		%vreg110<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg110
3664B		%vreg109<def> = LDRWui <fi#7>, 0; mem:LD4[FixedStack7] GPR32:%vreg109
3680B		%vreg108<def> = LDRWui <fi#12>, 0; mem:LD4[FixedStack12] GPR32:%vreg108
3696B		%vreg107<def> = LDRWui <fi#13>, 0; mem:LD4[FixedStack13] GPR32:%vreg107
3712B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3728B		%X0<def> = ADDXri <fi#5>, 0, 0
3744B		%X1<def> = COPY %vreg110; GPR64:%vreg110
3760B		%W2<def> = COPY %vreg109; GPR32:%vreg109
3776B		%W3<def> = COPY %vreg108; GPR32:%vreg108
3792B		%W4<def> = COPY %vreg107; GPR32:%vreg107
3808B		BL <ga:@BZ2_bzWriteOpen>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %W2<imp-use>, %W3<imp-use>, %W4<imp-use,kill>, %X0<imp-def>
3824B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3840B		%vreg106<def> = COPY %X0; GPR64:%vreg106
3856B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3872B		STACKMAP 7, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack0]
3888B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3904B		STRXui %vreg106, <fi#11>, 0; mem:ST8[FixedStack11] GPR64:%vreg106
3920B		B <BB#34>
	    Successors according to CFG: BB#34

3936B	BB#33: derived from LLVM BB %if.else.51
	    Predecessors according to CFG: BB#27
3984B		%vreg93<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg93
4000B		%vreg92<def> = LDRWui <fi#12>, 0; mem:LD4[FixedStack12] GPR32:%vreg92
4016B		%vreg91<def> = LDRWui <fi#14>, 0; mem:LD4[FixedStack14] GPR32:%vreg91
4032B		%vreg89<def> = LDRWui <fi#15>, 0; mem:LD4[FixedStack15] GPR32:%vreg89
4048B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4064B		%X0<def> = ADDXri <fi#5>, 0, 0
4080B		%X1<def> = COPY %vreg93; GPR64:%vreg93
4096B		%W2<def> = COPY %vreg92; GPR32:%vreg92
4112B		%W3<def> = COPY %vreg91; GPR32:%vreg91
4128B		%X4<def> = ADDXri <fi#6>, 0, 0
4144B		%W5<def> = COPY %vreg89; GPR32:%vreg89
4160B		BL <ga:@BZ2_bzReadOpen>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %W2<imp-use>, %W3<imp-use>, %X4<imp-use,kill>, %W5<imp-use,kill>, %X0<imp-def>
4176B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4192B		%vreg88<def> = COPY %X0; GPR64:%vreg88
4208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4224B		STACKMAP 8, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack0]
4240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4256B		STRXui %vreg88, <fi#11>, 0; mem:ST8[FixedStack11] GPR64:%vreg88
	    Successors according to CFG: BB#34

4272B	BB#34: derived from LLVM BB %if.end.54
	    Predecessors according to CFG: BB#33 BB#32
4288B		%vreg112<def> = LDRXui <fi#11>, 0; mem:LD8[FixedStack11] GPR64:%vreg112
4304B		CBNZX %vreg112, <BB#39>; GPR64:%vreg112
	    Successors according to CFG: BB#39 BB#35

4320B	BB#35: derived from LLVM BB %if.then.57
	    Predecessors according to CFG: BB#34
4336B		%vreg117<def> = ADRP <ga:@stdin>[TF=1]; GPR64common:%vreg117
4352B		%vreg118<def> = ADDXri %vreg117, <ga:@stdin>[TF=34], 0; GPR64sp:%vreg118 GPR64common:%vreg117
4368B		%vreg120<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg120
4384B		%vreg119<def> = LDRXui %vreg118, 0; mem:LD8[@stdin] GPR64:%vreg119 GPR64sp:%vreg118
4400B		%XZR<def> = SUBSXrr %vreg120, %vreg119, %NZCV<imp-def>; GPR64:%vreg120,%vreg119
4416B		Bcc 0, <BB#38>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#38 BB#36

4432B	BB#36: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#35
4448B		%vreg123<def> = ADRP <ga:@stdout>[TF=1]; GPR64common:%vreg123
4464B		%vreg124<def> = ADDXri %vreg123, <ga:@stdout>[TF=34], 0; GPR64sp:%vreg124 GPR64common:%vreg123
4480B		%vreg126<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg126
4496B		%vreg125<def> = LDRXui %vreg124, 0; mem:LD8[@stdout] GPR64:%vreg125 GPR64sp:%vreg124
4512B		%XZR<def> = SUBSXrr %vreg126, %vreg125, %NZCV<imp-def>; GPR64:%vreg126,%vreg125
4528B		Bcc 0, <BB#38>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#38 BB#37

4544B	BB#37: derived from LLVM BB %if.then.62
	    Predecessors according to CFG: BB#36
4560B		%vreg129<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg129
4576B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4592B		%X0<def> = COPY %vreg129; GPR64:%vreg129
4608B		BL <ga:@fclose>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
4624B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4640B		%vreg128<def,dead> = COPY %W0; GPR32all:%vreg128
4656B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4672B		STACKMAP 9, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0]
4688B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#38

4704B	BB#38: derived from LLVM BB %if.end.64
	    Predecessors according to CFG: BB#35 BB#36 BB#37
4736B		STRXui %XZR, <fi#0>, 0; mem:ST8[FixedStack0]
4752B		B <BB#40>
	    Successors according to CFG: BB#40

4768B	BB#39: derived from LLVM BB %if.end.65
	    Predecessors according to CFG: BB#34
4784B		%vreg114<def> = LDRXui <fi#11>, 0; mem:LD8[FixedStack11] GPR64:%vreg114
4800B		STRXui %vreg114, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg114
	    Successors according to CFG: BB#40

4816B	BB#40: derived from LLVM BB %return
	    Predecessors according to CFG: BB#39 BB#38 BB#26 BB#1
4832B		%vreg171<def> = ADRP <ga:@bzopen_or_bzdopen>[TF=1]; GPR64common:%vreg171
4848B		%vreg173<def> = ADDXri %vreg171, <ga:@bzopen_or_bzdopen>[TF=34], 0; GPR64sp:%vreg173 GPR64common:%vreg171
4896B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4912B		%X0<def> = COPY %vreg173; GPR64sp:%vreg173
4928B		%X1<def> = COPY %vreg25; GPR64:%vreg25
4944B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
4960B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4976B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4992B		STACKMAP 10, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0]
5008B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5024B		%vreg170<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg170
5040B		%X0<def> = COPY %vreg170; GPR64:%vreg170
5056B		RET_ReallyLR %X0<imp-use>

# End machine code for function bzopen_or_bzdopen.

handleMove 608B -> 632B: %W1<def> = COPY %vreg17; GPR32:%vreg17
     W1:	[0B,64r:0)[256r,272r:10)[608r,640r:1)[1888r,1904r:8)[2080r,2096r:9)[2352r,2368r:6)[2864r,2880r:5)[3104r,3120r:7)[3744r,3808r:3)[4080r,4160r:4)[4928r,4944r:2)  0@0B-phi 1@608r 2@4928r 3@3744r 4@4080r 5@2864r 6@2352r 7@3104r 8@1888r 9@2080r 10@256r
        -->	[0B,64r:0)[256r,272r:10)[632r,640r:1)[1888r,1904r:8)[2080r,2096r:9)[2352r,2368r:6)[2864r,2880r:5)[3104r,3120r:7)[3744r,3808r:3)[4080r,4160r:4)[4928r,4944r:2)  0@0B-phi 1@632r 2@4928r 3@3744r 4@4080r 5@2864r 6@2352r 7@3104r 8@1888r 9@2080r 10@256r
     %vreg17:	[592r,608r:0)  0@592r
        -->	[592r,632r:0)  0@592r
handleMove 1776B -> 1816B: %vreg46<def> = ADDXri %vreg45, <ga:@bzlib__str_7_r_>[TF=34], 0; GPR64common:%vreg46,%vreg45
     %vreg46:	[1776r,1840r:0)  0@1776r
        -->	[1816r,1840r:0)  0@1816r
     %vreg45:	[1760r,1776r:0)  0@1760r
        -->	[1760r,1816r:0)  0@1760r
handleMove 1760B -> 1812B: %vreg45<def> = ADRP <ga:@bzlib__str_7_r_>[TF=1]; GPR64common:%vreg45
     %vreg45:	[1760r,1816r:0)  0@1760r
        -->	[1812r,1816r:0)  0@1812r
handleMove 1744B -> 1816B: %vreg44<def> = ADDXri %vreg43, <ga:@bzlib__str_6_w_>[TF=34], 0; GPR64common:%vreg44,%vreg43
     %vreg44:	[1744r,1848r:0)  0@1744r
        -->	[1816r,1848r:0)  0@1816r
     %vreg43:	[1728r,1744r:0)  0@1728r
        -->	[1728r,1816r:0)  0@1728r
handleMove 2848B -> 2872B: %X0<def> = COPY %vreg68; GPR64:%vreg68
     W0:	[0B,80r:0)[240r,272r:19)[576r,640r:20)[1872r,1904r:16)[1904r,1936r:15)[2064r,2096r:18)[2096r,2128r:17)[2336r,2368r:13)[2368r,2400r:2)[2848r,2880r:12)[2880r,2912r:11)[3088r,3120r:3)[3120r,3152r:14)[3728r,3808r:8)[3808r,3840r:7)[4064r,4160r:10)[4160r,4192r:9)[4592r,4608r:6)[4608r,4640r:1)[4912r,4944r:4)[5040r,5056r:5)  0@0B-phi 1@4608r 2@2368r 3@3088r 4@4912r 5@5040r 6@4592r 7@3808r 8@3728r 9@4160r 10@4064r 11@2880r 12@2848r 13@2336r 14@3120r 15@1904r 16@1872r 17@2096r 18@2064r 19@240r 20@576r
        -->	[0B,80r:0)[240r,272r:19)[576r,640r:20)[1872r,1904r:16)[1904r,1936r:15)[2064r,2096r:18)[2096r,2128r:17)[2336r,2368r:13)[2368r,2400r:2)[2872r,2880r:12)[2880r,2912r:11)[3088r,3120r:3)[3120r,3152r:14)[3728r,3808r:8)[3808r,3840r:7)[4064r,4160r:10)[4160r,4192r:9)[4592r,4608r:6)[4608r,4640r:1)[4912r,4944r:4)[5040r,5056r:5)  0@0B-phi 1@4608r 2@2368r 3@3088r 4@4912r 5@5040r 6@4592r 7@3808r 8@3728r 9@4160r 10@4064r 11@2880r 12@2872r 13@2336r 14@3120r 15@1904r 16@1872r 17@2096r 18@2064r 19@240r 20@576r
     %vreg68:	[2816r,2848r:0)  0@2816r
        -->	[2816r,2872r:0)  0@2816r
handleMove 3088B -> 3112B: %W0<def> = COPY %vreg55; GPR32:%vreg55
     W0:	[0B,80r:0)[240r,272r:19)[576r,640r:20)[1872r,1904r:16)[1904r,1936r:15)[2064r,2096r:18)[2096r,2128r:17)[2336r,2368r:13)[2368r,2400r:2)[2872r,2880r:12)[2880r,2912r:11)[3088r,3120r:3)[3120r,3152r:14)[3728r,3808r:8)[3808r,3840r:7)[4064r,4160r:10)[4160r,4192r:9)[4592r,4608r:6)[4608r,4640r:1)[4912r,4944r:4)[5040r,5056r:5)  0@0B-phi 1@4608r 2@2368r 3@3088r 4@4912r 5@5040r 6@4592r 7@3808r 8@3728r 9@4160r 10@4064r 11@2880r 12@2872r 13@2336r 14@3120r 15@1904r 16@1872r 17@2096r 18@2064r 19@240r 20@576r
        -->	[0B,80r:0)[240r,272r:19)[576r,640r:20)[1872r,1904r:16)[1904r,1936r:15)[2064r,2096r:18)[2096r,2128r:17)[2336r,2368r:13)[2368r,2400r:2)[2872r,2880r:12)[2880r,2912r:11)[3112r,3120r:3)[3120r,3152r:14)[3728r,3808r:8)[3808r,3840r:7)[4064r,4160r:10)[4160r,4192r:9)[4592r,4608r:6)[4608r,4640r:1)[4912r,4944r:4)[5040r,5056r:5)  0@0B-phi 1@4608r 2@2368r 3@3112r 4@4912r 5@5040r 6@4592r 7@3808r 8@3728r 9@4160r 10@4064r 11@2880r 12@2872r 13@2336r 14@3120r 15@1904r 16@1872r 17@2096r 18@2064r 19@240r 20@576r
     %vreg55:	[3056r,3088r:0)  0@3056r
        -->	[3056r,3112r:0)  0@3056r
handleMove 4128B -> 4072B: %X4<def> = ADDXri <fi#6>, 0, 0
     W4:	[3792r,3808r:0)[4072r,4160r:1)  0@3792r 1@4072r
        -->	[3792r,3808r:0)[4072r,4160r:1)  0@3792r 1@4072r
********** GREEDY REGISTER ALLOCATION **********
********** Function: bzopen_or_bzdopen
********** INTERVALS **********
W30 [0B,16r:0)[272r,272d:20)[416e,416d:10)[640r,640d:21)[1904r,1904d:18)[2016e,2016d:9)[2096r,2096d:19)[2160e,2160d:8)[2368r,2368d:16)[2448e,2448d:7)[2880r,2880d:15)[2944e,2944d:6)[3120r,3120d:17)[3184e,3184d:5)[3808r,3808d:13)[3872e,3872d:4)[4160r,4160d:14)[4224e,4224d:3)[4608r,4608d:12)[4672e,4672d:2)[4944r,4944d:11)[4992e,4992d:1)  0@0B-phi 1@4992e 2@4672e 3@4224e 4@3872e 5@3184e 6@2944e 7@2448e 8@2160e 9@2016e 10@416e 11@4944r 12@4608r 13@3808r 14@4160r 15@2880r 16@2368r 17@3120r 18@1904r 19@2096r 20@272r 21@640r
WZR [1488r,1488d:0)[1840r,1840d:3)[3424r,3424d:2)[3536r,3536d:1)[4400r,4400d:5)[4512r,4512d:4)  0@1488r 1@3536r 2@3424r 3@1840r 4@4512r 5@4400r
W0 [0B,80r:0)[240r,272r:19)[576r,640r:20)[1872r,1904r:16)[1904r,1936r:15)[2064r,2096r:18)[2096r,2128r:17)[2336r,2368r:13)[2368r,2400r:2)[2872r,2880r:12)[2880r,2912r:11)[3112r,3120r:3)[3120r,3152r:14)[3728r,3808r:8)[3808r,3840r:7)[4064r,4160r:10)[4160r,4192r:9)[4592r,4608r:6)[4608r,4640r:1)[4912r,4944r:4)[5040r,5056r:5)  0@0B-phi 1@4608r 2@2368r 3@3112r 4@4912r 5@5040r 6@4592r 7@3808r 8@3728r 9@4160r 10@4064r 11@2880r 12@2872r 13@2336r 14@3120r 15@1904r 16@1872r 17@2096r 18@2064r 19@240r 20@576r
W1 [0B,64r:0)[256r,272r:10)[632r,640r:1)[1888r,1904r:8)[2080r,2096r:9)[2352r,2368r:6)[2864r,2880r:5)[3104r,3120r:7)[3744r,3808r:3)[4080r,4160r:4)[4928r,4944r:2)  0@0B-phi 1@632r 2@4928r 3@3744r 4@4080r 5@2864r 6@2352r 7@3104r 8@1888r 9@2080r 10@256r
W2 [0B,48r:0)[624r,640r:3)[3760r,3808r:1)[4096r,4160r:2)  0@0B-phi 1@3760r 2@4096r 3@624r
W3 [0B,32r:0)[3776r,3808r:1)[4112r,4160r:2)  0@0B-phi 1@3776r 2@4112r
W4 [3792r,3808r:0)[4072r,4160r:1)  0@3792r 1@4072r
%vreg4 [80r,448r:0)  0@80r
%vreg6 [64r,464r:0)  0@64r
%vreg8 [48r,480r:0)  0@48r
%vreg10 [32r,496r:0)  0@32r
%vreg12 [768r,784r:0)  0@768r
%vreg13 [304r,720r:0)  0@304r
%vreg17 [592r,632r:0)  0@592r
%vreg21 [384r,512r:0)  0@384r
%vreg22 [160r,176r:0)  0@160r
%vreg24 [176r,240r:0)  0@176r
%vreg25 [16r,4928r:0)  0@16r
%vreg28 [944r,960r:0)  0@944r
%vreg30 [928r,944r:0)  0@928r
%vreg31 [912r,928r:0)  0@912r
%vreg33 [2192r,2208r:0)  0@2192r
%vreg35 [1952r,1968r:0)  0@1952r
%vreg36 [1968r,2080r:0)  0@1968r
%vreg37 [2128r,2128d:0)  0@2128r
%vreg41 [1936r,1936d:0)  0@1936r
%vreg43 [1728r,1816r:0)  0@1728r
%vreg44 [1816r,1848r:0)  0@1816r
%vreg45 [1824r,1832r:0)  0@1824r
%vreg46 [1832r,1848r:0)  0@1832r
%vreg47 [1848r,1888r:0)  0@1848r
%vreg48 [1808r,1840r:0)  0@1808r
%vreg53 [3152r,3216r:0)  0@3152r
%vreg55 [3056r,3112r:0)  0@3056r
%vreg57 [2240r,2256r:0)  0@2240r
%vreg58 [2400r,2480r:0)  0@2400r
%vreg60 [2320r,2352r:0)  0@2320r
%vreg62 [2288r,2336r:0)  0@2288r
%vreg66 [2912r,2976r:0)  0@2912r
%vreg68 [2816r,2872r:0)  0@2816r
%vreg70 [2512r,2528r:0)  0@2512r
%vreg71 [2656r,2672r:0)  0@2656r
%vreg72 [2672r,2688r:0)  0@2672r
%vreg74 [2560r,2576r:0)  0@2560r
%vreg75 [2576r,2592r:0)  0@2576r
%vreg78 [3248r,3264r:0)  0@3248r
%vreg80 [3360r,3376r:0)  0@3360r
%vreg88 [4192r,4256r:0)  0@4192r
%vreg89 [4032r,4144r:0)  0@4032r
%vreg91 [4016r,4112r:0)  0@4016r
%vreg92 [4000r,4096r:0)  0@4000r
%vreg93 [3984r,4080r:0)  0@3984r
%vreg95 [3408r,3424r:0)  0@3408r
%vreg96 [3472r,3488r:0)  0@3472r
%vreg98 [3520r,3536r:0)  0@3520r
%vreg99 [3584r,3600r:0)  0@3584r
%vreg106 [3840r,3904r:0)  0@3840r
%vreg107 [3696r,3792r:0)  0@3696r
%vreg108 [3680r,3776r:0)  0@3680r
%vreg109 [3664r,3760r:0)  0@3664r
%vreg110 [3648r,3744r:0)  0@3648r
%vreg112 [4288r,4304r:0)  0@4288r
%vreg114 [4784r,4800r:0)  0@4784r
%vreg117 [4336r,4352r:0)  0@4336r
%vreg118 [4352r,4384r:0)  0@4352r
%vreg119 [4384r,4400r:0)  0@4384r
%vreg120 [4368r,4400r:0)  0@4368r
%vreg123 [4448r,4464r:0)  0@4448r
%vreg124 [4464r,4496r:0)  0@4464r
%vreg125 [4496r,4512r:0)  0@4496r
%vreg126 [4480r,4512r:0)  0@4480r
%vreg128 [4640r,4640d:0)  0@4640r
%vreg129 [4560r,4592r:0)  0@4560r
%vreg132 [1008r,1168r:0)  0@1008r
%vreg133 [992r,1008r:0)  0@992r
%vreg135 [1040r,1040d:0)  0@1040r
%vreg136 [1104r,1104d:0)  0@1104r
%vreg137 [1168r,1168d:0)  0@1168r
%vreg138 [1344r,1360r:0)  0@1344r
%vreg139 [1280r,1296r:0)  0@1280r
%vreg142 [1472r,1488r:0)  0@1472r
%vreg146 [1456r,1472r:0)  0@1456r
%vreg147 [1440r,1456r:0)  0@1440r
%vreg158 [1568r,1584r:0)  0@1568r
%vreg162 [1552r,1568r:0)  0@1552r
%vreg163 [1536r,1552r:0)  0@1536r
%vreg166 [1664r,1680r:0)  0@1664r
%vreg167 [1648r,1664r:0)  0@1648r
%vreg170 [5024r,5040r:0)  0@5024r
%vreg171 [4832r,4848r:0)  0@4832r
%vreg173 [4848r,4912r:0)  0@4848r
%vreg175 [2592r,2640B:1)[2688r,2720B:0)[2720B,2752r:2)  0@2688r 1@2592r 2@2720B-phi
RegMasks: 272r 640r 1904r 2096r 2368r 2880r 3120r 3808r 4160r 4608r 4944r
********** MACHINEINSTRS **********
# Machine code for function bzopen_or_bzdopen: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=4, align=4, at location [SP]
  fi#3: size=8, align=8, at location [SP]
  fi#4: size=4, align=4, at location [SP]
  fi#5: size=4, align=4, at location [SP]
  fi#6: size=5000, align=16, at location [SP]
  fi#7: size=4, align=4, at location [SP]
  fi#8: size=4, align=4, at location [SP]
  fi#9: size=10, align=1, at location [SP]
  fi#10: size=8, align=8, at location [SP]
  fi#11: size=8, align=8, at location [SP]
  fi#12: size=4, align=4, at location [SP]
  fi#13: size=4, align=4, at location [SP]
  fi#14: size=4, align=4, at location [SP]
  fi#15: size=4, align=4, at location [SP]
Function Live Ins: %X0 in %vreg3, %W1 in %vreg5, %X2 in %vreg7, %W3 in %vreg9, %LR in %vreg26

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %W1 %X2 %W3 %LR
16B		%vreg25<def> = COPY %LR; GPR64:%vreg25
32B		%vreg10<def> = COPY %W3; GPR32:%vreg10
48B		%vreg8<def> = COPY %X2; GPR64:%vreg8
64B		%vreg6<def> = COPY %W1; GPR32:%vreg6
80B		%vreg4<def> = COPY %X0; GPR64:%vreg4
160B		%vreg22<def> = ADRP <ga:@bzopen_or_bzdopen>[TF=1]; GPR64common:%vreg22
176B		%vreg24<def> = ADDXri %vreg22, <ga:@bzopen_or_bzdopen>[TF=34], 0; GPR64sp:%vreg24 GPR64common:%vreg22
224B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
240B		%X0<def> = COPY %vreg24; GPR64sp:%vreg24
256B		%X1<def> = COPY %vreg25; GPR64:%vreg25
272B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
288B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
304B		%vreg13<def> = MOVi32imm 30; GPR32:%vreg13
384B		%vreg21<def> = MOVi32imm 9; GPR32:%vreg21
400B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
416B		STACKMAP 0, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, %vreg6, 0, <fi#2>, 0, 0, <fi#10>, 0, %vreg8, 0, <fi#3>, 0, 0, <fi#9>, 0, 0, <fi#15>, 0, %vreg10, 0, <fi#4>, 0, %vreg4, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack2](align=4) LD8[FixedStack10] LD8[FixedStack3] LD8[FixedStack9](align=1) LD8[FixedStack15](align=4) LD8[FixedStack4](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4) GPR32:%vreg6,%vreg10 GPR64:%vreg8,%vreg4
432B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
448B		STRXui %vreg4, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg4
464B		STRWui %vreg6, <fi#2>, 0; mem:ST4[FixedStack2] GPR32:%vreg6
480B		STRXui %vreg8, <fi#3>, 0; mem:ST8[FixedStack3] GPR64:%vreg8
496B		STRWui %vreg10, <fi#4>, 0; mem:ST4[FixedStack4] GPR32:%vreg10
512B		STRWui %vreg21, <fi#7>, 0; mem:ST4[FixedStack7] GPR32:%vreg21
528B		STRWui %WZR, <fi#8>, 0; mem:ST4[FixedStack8]
560B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
576B		%X0<def> = ADDXri <fi#9>, 0, 0
592B		%vreg17<def> = UBFMWri %WZR, 0, 7; GPR32:%vreg17
624B		%X2<def> = MOVi64imm 10
632B		%W1<def> = COPY %vreg17; GPR32:%vreg17
640B		BL <MCSym=memset>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %X2<imp-use>
656B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
672B		STRXui %XZR, <fi#10>, 0; mem:ST8[FixedStack10]
688B		STRXui %XZR, <fi#11>, 0; mem:ST8[FixedStack11]
704B		STRWui %WZR, <fi#12>, 0; mem:ST4[FixedStack12]
720B		STRWui %vreg13, <fi#13>, 0; mem:ST4[FixedStack13] GPR32:%vreg13
736B		STRWui %WZR, <fi#14>, 0; mem:ST4[FixedStack14]
752B		STRWui %WZR, <fi#15>, 0; mem:ST4[FixedStack15]
768B		%vreg12<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg12
784B		CBNZX %vreg12, <BB#2>; GPR64:%vreg12
	    Successors according to CFG: BB#2 BB#1

800B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
832B		STRXui %XZR, <fi#0>, 0; mem:ST8[FixedStack0]
848B		B <BB#40>
	    Successors according to CFG: BB#40

864B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0
880B		B <BB#3>
	    Successors according to CFG: BB#3

896B	BB#3: derived from LLVM BB %while.cond
	    Predecessors according to CFG: BB#2 BB#14
912B		%vreg31<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg31
928B		%vreg30<def> = LDRBBui %vreg31, 0; mem:LD1[%2] GPR32:%vreg30 GPR64common:%vreg31
944B		%vreg28<def> = UBFMWri %vreg30, 0, 7; GPR32:%vreg28,%vreg30
960B		CBZW %vreg28, <BB#15>; GPR32:%vreg28
	    Successors according to CFG: BB#15 BB#4

976B	BB#4: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#3
992B		%vreg133<def> = LDRXui <fi#3>, 0; mem:LD8[%mode.addr] GPR64common:%vreg133
1008B		%vreg132<def> = LDRSBWui %vreg133, 0; mem:LD1[%4] GPR32common:%vreg132 GPR64common:%vreg133
1040B		%vreg135<def,dead> = SUBSWri %vreg132, 114, 0, %NZCV<imp-def>; GPR32:%vreg135 GPR32common:%vreg132
1056B		Bcc 0, <BB#7>, %NZCV<imp-use,kill>
1072B		B <BB#5>
	    Successors according to CFG: BB#7 BB#5

1088B	BB#5: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#4
1104B		%vreg136<def,dead> = SUBSWri %vreg132, 115, 0, %NZCV<imp-def>; GPR32:%vreg136 GPR32common:%vreg132
1120B		Bcc 0, <BB#9>, %NZCV<imp-use,kill>
1136B		B <BB#6>
	    Successors according to CFG: BB#9 BB#6

1152B	BB#6: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#5
1168B		%vreg137<def,dead> = SUBSWri %vreg132, 119, 0, %NZCV<imp-def>; GPR32:%vreg137 GPR32common:%vreg132
1184B		Bcc 0, <BB#8>, %NZCV<imp-use,kill>
1200B		B <BB#10>
	    Successors according to CFG: BB#8 BB#10

1216B	BB#7: derived from LLVM BB %sw.bb
	    Predecessors according to CFG: BB#4
1232B		STRWui %WZR, <fi#8>, 0; mem:ST4[FixedStack8]
1248B		B <BB#14>
	    Successors according to CFG: BB#14

1264B	BB#8: derived from LLVM BB %sw.bb.1
	    Predecessors according to CFG: BB#6
1280B		%vreg139<def> = MOVi32imm 1; GPR32:%vreg139
1296B		STRWui %vreg139, <fi#8>, 0; mem:ST4[FixedStack8] GPR32:%vreg139
1312B		B <BB#14>
	    Successors according to CFG: BB#14

1328B	BB#9: derived from LLVM BB %sw.bb.2
	    Predecessors according to CFG: BB#5
1344B		%vreg138<def> = MOVi32imm 1; GPR32:%vreg138
1360B		STRWui %vreg138, <fi#14>, 0; mem:ST4[FixedStack14] GPR32:%vreg138
1376B		B <BB#14>
	    Successors according to CFG: BB#14

1392B	BB#10: derived from LLVM BB %sw.default
	    Predecessors according to CFG: BB#6
1408B		B <BB#11>
	    Successors according to CFG: BB#11

1424B	BB#11: derived from LLVM BB %cond.false
	    Predecessors according to CFG: BB#10
1440B		%vreg147<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg147
1456B		%vreg146<def> = LDRSBWui %vreg147, 0; mem:LD1[%8] GPR32common:%vreg146 GPR64common:%vreg147
1472B		%vreg142<def> = SUBWri %vreg146, 48, 0; GPR32sp:%vreg142 GPR32common:%vreg146
1488B		%WZR<def> = SUBSWri %vreg142, 10, 0, %NZCV<imp-def>; GPR32sp:%vreg142
1504B		Bcc 2, <BB#13>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#13 BB#12

1520B	BB#12: derived from LLVM BB %if.then.8
	    Predecessors according to CFG: BB#11
1536B		%vreg163<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg163
1552B		%vreg162<def> = LDRSBWui %vreg163, 0; mem:LD1[%10] GPR32common:%vreg162 GPR64common:%vreg163
1568B		%vreg158<def> = SUBWri %vreg162, 48, 0; GPR32common:%vreg158,%vreg162
1584B		STRWui %vreg158, <fi#7>, 0; mem:ST4[FixedStack7] GPR32common:%vreg158
	    Successors according to CFG: BB#13

1600B	BB#13: derived from LLVM BB %if.end.11
	    Predecessors according to CFG: BB#11 BB#12
1616B		B <BB#14>
	    Successors according to CFG: BB#14

1632B	BB#14: derived from LLVM BB %sw.epilog
	    Predecessors according to CFG: BB#9 BB#8 BB#7 BB#13
1648B		%vreg167<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg167
1664B		%vreg166<def> = ADDXri %vreg167, 1, 0; GPR64common:%vreg166,%vreg167
1680B		STRXui %vreg166, <fi#3>, 0; mem:ST8[FixedStack3] GPR64common:%vreg166
1696B		B <BB#3>
	    Successors according to CFG: BB#3

1712B	BB#15: derived from LLVM BB %while.end
	    Predecessors according to CFG: BB#3
1728B		%vreg43<def> = ADRP <ga:@bzlib__str_6_w_>[TF=1]; GPR64common:%vreg43
1808B		%vreg48<def> = LDRWui <fi#8>, 0; mem:LD4[FixedStack8] GPR32common:%vreg48
1816B		%vreg44<def> = ADDXri %vreg43, <ga:@bzlib__str_6_w_>[TF=34], 0; GPR64common:%vreg44,%vreg43
1824B		%vreg45<def> = ADRP <ga:@bzlib__str_7_r_>[TF=1]; GPR64common:%vreg45
1832B		%vreg46<def> = ADDXri %vreg45, <ga:@bzlib__str_7_r_>[TF=34], 0; GPR64common:%vreg46,%vreg45
1840B		%WZR<def> = SUBSWri %vreg48, 0, 0, %NZCV<imp-def>; GPR32common:%vreg48
1848B		%vreg47<def> = CSELXr %vreg44, %vreg46, 1, %NZCV<imp-use,kill>; GPR64:%vreg47 GPR64common:%vreg44,%vreg46
1856B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1872B		%X0<def> = ADDXri <fi#9>, 0, 0
1888B		%X1<def> = COPY %vreg47; GPR64:%vreg47
1904B		BL <ga:@strcat>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %X0<imp-def>
1920B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1936B		%vreg41<def,dead> = COPY %X0; GPR64all:%vreg41
1952B		%vreg35<def> = ADRP <ga:@bzlib__str_8_b_>[TF=1]; GPR64common:%vreg35
1968B		%vreg36<def> = ADDXri %vreg35, <ga:@bzlib__str_8_b_>[TF=34], 0; GPR64sp:%vreg36 GPR64common:%vreg35
2000B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2016B		STACKMAP 2, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#2>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, 0, <fi#15>, 0, 0, <fi#4>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack2](align=4) LD8[FixedStack10] LD8[FixedStack9](align=1) LD8[FixedStack15](align=4) LD8[FixedStack4](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)
2032B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2048B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2064B		%X0<def> = ADDXri <fi#9>, 0, 0
2080B		%X1<def> = COPY %vreg36; GPR64sp:%vreg36
2096B		BL <ga:@strcat>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %X0<imp-def>
2112B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2128B		%vreg37<def,dead> = COPY %X0; GPR64all:%vreg37
2144B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2160B		STACKMAP 3, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#2>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, 0, <fi#15>, 0, 0, <fi#4>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack2](align=4) LD8[FixedStack10] LD8[FixedStack9](align=1) LD8[FixedStack15](align=4) LD8[FixedStack4](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)
2176B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2192B		%vreg33<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg33
2208B		CBNZW %vreg33, <BB#24>; GPR32:%vreg33
	    Successors according to CFG: BB#24 BB#16

2224B	BB#16: derived from LLVM BB %if.then.18
	    Predecessors according to CFG: BB#15
2240B		%vreg57<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg57
2256B		CBZX %vreg57, <BB#18>; GPR64:%vreg57
	    Successors according to CFG: BB#18 BB#17

2272B	BB#17: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#16
2288B		%vreg62<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg62
2304B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2320B		%vreg60<def> = MOVaddr <ga:@bzlib__str_9_>[TF=1], <ga:@bzlib__str_9_>[TF=34]; GPR64:%vreg60
2336B		%X0<def> = COPY %vreg62; GPR64:%vreg62
2352B		%X1<def> = COPY %vreg60; GPR64:%vreg60
2368B		BL <ga:@strcmp>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %SP<imp-def>, %W0<imp-def>
2384B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2400B		%vreg58<def> = COPY %W0; GPR32:%vreg58
2432B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2448B		STACKMAP 4, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, 0, <fi#15>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack9](align=1) LD8[FixedStack15](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)
2464B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2480B		CBNZW %vreg58, <BB#22>; GPR32:%vreg58
	    Successors according to CFG: BB#22 BB#18

2496B	BB#18: derived from LLVM BB %if.then.24
	    Predecessors according to CFG: BB#16 BB#17
2512B		%vreg70<def> = LDRWui <fi#8>, 0; mem:LD4[FixedStack8] GPR32:%vreg70
2528B		CBZW %vreg70, <BB#20>; GPR32:%vreg70
	    Successors according to CFG: BB#20 BB#19

2544B	BB#19: derived from LLVM BB %cond.true.26
	    Predecessors according to CFG: BB#18
2560B		%vreg74<def> = ADRP <ga:@stdout>[TF=1]; GPR64common:%vreg74
2576B		%vreg75<def> = ADDXri %vreg74, <ga:@stdout>[TF=34], 0; GPR64sp:%vreg75 GPR64common:%vreg74
2592B		%vreg175<def> = LDRXui %vreg75, 0; mem:LD8[@stdout] GPR64:%vreg175 GPR64sp:%vreg75
2624B		B <BB#21>
	    Successors according to CFG: BB#21

2640B	BB#20: derived from LLVM BB %cond.false.27
	    Predecessors according to CFG: BB#18
2656B		%vreg71<def> = ADRP <ga:@stdin>[TF=1]; GPR64common:%vreg71
2672B		%vreg72<def> = ADDXri %vreg71, <ga:@stdin>[TF=34], 0; GPR64sp:%vreg72 GPR64common:%vreg71
2688B		%vreg175<def> = LDRXui %vreg72, 0; mem:LD8[@stdin] GPR64:%vreg175 GPR64sp:%vreg72
	    Successors according to CFG: BB#21

2720B	BB#21: derived from LLVM BB %cond.end
	    Predecessors according to CFG: BB#20 BB#19
2752B		STRXui %vreg175, <fi#10>, 0; mem:ST8[FixedStack10] GPR64:%vreg175
2768B		B <BB#23>
	    Successors according to CFG: BB#23

2784B	BB#22: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#17
2816B		%vreg68<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg68
2832B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2864B		%X1<def> = ADDXri <fi#9>, 0, 0
2872B		%X0<def> = COPY %vreg68; GPR64:%vreg68
2880B		BL <ga:@fopen>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %X0<imp-def>
2896B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2912B		%vreg66<def> = COPY %X0; GPR64:%vreg66
2928B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2944B		STACKMAP 5, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#15>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack15](align=4) LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)
2960B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2976B		STRXui %vreg66, <fi#10>, 0; mem:ST8[FixedStack10] GPR64:%vreg66
	    Successors according to CFG: BB#23

2992B	BB#23: derived from LLVM BB %if.end.31
	    Predecessors according to CFG: BB#22 BB#21
3008B		B <BB#25>
	    Successors according to CFG: BB#25

3024B	BB#24: derived from LLVM BB %if.else.32
	    Predecessors according to CFG: BB#15
3056B		%vreg55<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg55
3072B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3104B		%X1<def> = ADDXri <fi#9>, 0, 0
3112B		%W0<def> = COPY %vreg55; GPR32:%vreg55
3120B		BL <ga:@fdopen>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use>, %X0<imp-def>
3136B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3152B		%vreg53<def> = COPY %X0; GPR64:%vreg53
3168B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3184B		STACKMAP 6, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#15>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack15](align=4) LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)
3200B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3216B		STRXui %vreg53, <fi#10>, 0; mem:ST8[FixedStack10] GPR64:%vreg53
	    Successors according to CFG: BB#25

3232B	BB#25: derived from LLVM BB %if.end.35
	    Predecessors according to CFG: BB#24 BB#23
3248B		%vreg78<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg78
3264B		CBNZX %vreg78, <BB#27>; GPR64:%vreg78
	    Successors according to CFG: BB#27 BB#26

3280B	BB#26: derived from LLVM BB %if.then.38
	    Predecessors according to CFG: BB#25
3312B		STRXui %XZR, <fi#0>, 0; mem:ST8[FixedStack0]
3328B		B <BB#40>
	    Successors according to CFG: BB#40

3344B	BB#27: derived from LLVM BB %if.end.39
	    Predecessors according to CFG: BB#25
3360B		%vreg80<def> = LDRWui <fi#8>, 0; mem:LD4[FixedStack8] GPR32:%vreg80
3376B		CBZW %vreg80, <BB#33>; GPR32:%vreg80
	    Successors according to CFG: BB#33 BB#28

3392B	BB#28: derived from LLVM BB %if.then.41
	    Predecessors according to CFG: BB#27
3408B		%vreg95<def> = LDRWui <fi#7>, 0; mem:LD4[FixedStack7] GPR32common:%vreg95
3424B		%WZR<def> = SUBSWri %vreg95, 1, 0, %NZCV<imp-def>; GPR32common:%vreg95
3440B		Bcc 10, <BB#30>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#30 BB#29

3456B	BB#29: derived from LLVM BB %if.then.44
	    Predecessors according to CFG: BB#28
3472B		%vreg96<def> = MOVi32imm 1; GPR32:%vreg96
3488B		STRWui %vreg96, <fi#7>, 0; mem:ST4[FixedStack7] GPR32:%vreg96
	    Successors according to CFG: BB#30

3504B	BB#30: derived from LLVM BB %if.end.45
	    Predecessors according to CFG: BB#28 BB#29
3520B		%vreg98<def> = LDRWui <fi#7>, 0; mem:LD4[FixedStack7] GPR32common:%vreg98
3536B		%WZR<def> = SUBSWri %vreg98, 9, 0, %NZCV<imp-def>; GPR32common:%vreg98
3552B		Bcc 13, <BB#32>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#32 BB#31

3568B	BB#31: derived from LLVM BB %if.then.48
	    Predecessors according to CFG: BB#30
3584B		%vreg99<def> = MOVi32imm 9; GPR32:%vreg99
3600B		STRWui %vreg99, <fi#7>, 0; mem:ST4[FixedStack7] GPR32:%vreg99
	    Successors according to CFG: BB#32

3616B	BB#32: derived from LLVM BB %if.end.49
	    Predecessors according to CFG: BB#30 BB#31
3648B		%vreg110<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg110
3664B		%vreg109<def> = LDRWui <fi#7>, 0; mem:LD4[FixedStack7] GPR32:%vreg109
3680B		%vreg108<def> = LDRWui <fi#12>, 0; mem:LD4[FixedStack12] GPR32:%vreg108
3696B		%vreg107<def> = LDRWui <fi#13>, 0; mem:LD4[FixedStack13] GPR32:%vreg107
3712B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3728B		%X0<def> = ADDXri <fi#5>, 0, 0
3744B		%X1<def> = COPY %vreg110; GPR64:%vreg110
3760B		%W2<def> = COPY %vreg109; GPR32:%vreg109
3776B		%W3<def> = COPY %vreg108; GPR32:%vreg108
3792B		%W4<def> = COPY %vreg107; GPR32:%vreg107
3808B		BL <ga:@BZ2_bzWriteOpen>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %W2<imp-use>, %W3<imp-use>, %W4<imp-use>, %X0<imp-def>
3824B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3840B		%vreg106<def> = COPY %X0; GPR64:%vreg106
3856B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3872B		STACKMAP 7, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack0]
3888B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3904B		STRXui %vreg106, <fi#11>, 0; mem:ST8[FixedStack11] GPR64:%vreg106
3920B		B <BB#34>
	    Successors according to CFG: BB#34

3936B	BB#33: derived from LLVM BB %if.else.51
	    Predecessors according to CFG: BB#27
3984B		%vreg93<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg93
4000B		%vreg92<def> = LDRWui <fi#12>, 0; mem:LD4[FixedStack12] GPR32:%vreg92
4016B		%vreg91<def> = LDRWui <fi#14>, 0; mem:LD4[FixedStack14] GPR32:%vreg91
4032B		%vreg89<def> = LDRWui <fi#15>, 0; mem:LD4[FixedStack15] GPR32:%vreg89
4048B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4064B		%X0<def> = ADDXri <fi#5>, 0, 0
4072B		%X4<def> = ADDXri <fi#6>, 0, 0
4080B		%X1<def> = COPY %vreg93; GPR64:%vreg93
4096B		%W2<def> = COPY %vreg92; GPR32:%vreg92
4112B		%W3<def> = COPY %vreg91; GPR32:%vreg91
4144B		%W5<def> = COPY %vreg89; GPR32:%vreg89
4160B		BL <ga:@BZ2_bzReadOpen>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %W2<imp-use>, %W3<imp-use>, %X4<imp-use>, %W5<imp-use,kill>, %X0<imp-def>
4176B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4192B		%vreg88<def> = COPY %X0; GPR64:%vreg88
4208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4224B		STACKMAP 8, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack0]
4240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4256B		STRXui %vreg88, <fi#11>, 0; mem:ST8[FixedStack11] GPR64:%vreg88
	    Successors according to CFG: BB#34

4272B	BB#34: derived from LLVM BB %if.end.54
	    Predecessors according to CFG: BB#33 BB#32
4288B		%vreg112<def> = LDRXui <fi#11>, 0; mem:LD8[FixedStack11] GPR64:%vreg112
4304B		CBNZX %vreg112, <BB#39>; GPR64:%vreg112
	    Successors according to CFG: BB#39 BB#35

4320B	BB#35: derived from LLVM BB %if.then.57
	    Predecessors according to CFG: BB#34
4336B		%vreg117<def> = ADRP <ga:@stdin>[TF=1]; GPR64common:%vreg117
4352B		%vreg118<def> = ADDXri %vreg117, <ga:@stdin>[TF=34], 0; GPR64sp:%vreg118 GPR64common:%vreg117
4368B		%vreg120<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg120
4384B		%vreg119<def> = LDRXui %vreg118, 0; mem:LD8[@stdin] GPR64:%vreg119 GPR64sp:%vreg118
4400B		%XZR<def> = SUBSXrr %vreg120, %vreg119, %NZCV<imp-def>; GPR64:%vreg120,%vreg119
4416B		Bcc 0, <BB#38>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#38 BB#36

4432B	BB#36: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#35
4448B		%vreg123<def> = ADRP <ga:@stdout>[TF=1]; GPR64common:%vreg123
4464B		%vreg124<def> = ADDXri %vreg123, <ga:@stdout>[TF=34], 0; GPR64sp:%vreg124 GPR64common:%vreg123
4480B		%vreg126<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg126
4496B		%vreg125<def> = LDRXui %vreg124, 0; mem:LD8[@stdout] GPR64:%vreg125 GPR64sp:%vreg124
4512B		%XZR<def> = SUBSXrr %vreg126, %vreg125, %NZCV<imp-def>; GPR64:%vreg126,%vreg125
4528B		Bcc 0, <BB#38>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#38 BB#37

4544B	BB#37: derived from LLVM BB %if.then.62
	    Predecessors according to CFG: BB#36
4560B		%vreg129<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg129
4576B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4592B		%X0<def> = COPY %vreg129; GPR64:%vreg129
4608B		BL <ga:@fclose>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
4624B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4640B		%vreg128<def,dead> = COPY %W0; GPR32all:%vreg128
4656B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4672B		STACKMAP 9, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0]
4688B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#38

4704B	BB#38: derived from LLVM BB %if.end.64
	    Predecessors according to CFG: BB#35 BB#36 BB#37
4736B		STRXui %XZR, <fi#0>, 0; mem:ST8[FixedStack0]
4752B		B <BB#40>
	    Successors according to CFG: BB#40

4768B	BB#39: derived from LLVM BB %if.end.65
	    Predecessors according to CFG: BB#34
4784B		%vreg114<def> = LDRXui <fi#11>, 0; mem:LD8[FixedStack11] GPR64:%vreg114
4800B		STRXui %vreg114, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg114
	    Successors according to CFG: BB#40

4816B	BB#40: derived from LLVM BB %return
	    Predecessors according to CFG: BB#39 BB#38 BB#26 BB#1
4832B		%vreg171<def> = ADRP <ga:@bzopen_or_bzdopen>[TF=1]; GPR64common:%vreg171
4848B		%vreg173<def> = ADDXri %vreg171, <ga:@bzopen_or_bzdopen>[TF=34], 0; GPR64sp:%vreg173 GPR64common:%vreg171
4896B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4912B		%X0<def> = COPY %vreg173; GPR64sp:%vreg173
4928B		%X1<def> = COPY %vreg25; GPR64:%vreg25
4944B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
4960B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4976B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4992B		STACKMAP 10, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0]
5008B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5024B		%vreg170<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg170
5040B		%X0<def> = COPY %vreg170; GPR64:%vreg170
5056B		RET_ReallyLR %X0<imp-use>

# End machine code for function bzopen_or_bzdopen.


selectOrSplit GPR64:%vreg25 [16r,4928r:0)  0@16r w=5.704066e-04
hints: %X1
missed hint %X1
assigning %vreg25 to %X19: W19 [16r,4928r:0)  0@16r

selectOrSplit GPR32:%vreg10 [32r,496r:0)  0@32r w=3.506945e-03
hints: %W3
missed hint %W3
assigning %vreg10 to %W20: W20 [32r,496r:0)  0@32r

selectOrSplit GPR64:%vreg8 [48r,480r:0)  0@48r w=3.641827e-03
hints: %X2
missed hint %X2
assigning %vreg8 to %X21: W21 [48r,480r:0)  0@48r

selectOrSplit GPR32:%vreg6 [64r,464r:0)  0@64r w=3.787500e-03
hints: %W1
missed hint %W1
assigning %vreg6 to %W22: W22 [64r,464r:0)  0@64r

selectOrSplit GPR64:%vreg4 [80r,448r:0)  0@80r w=3.945312e-03
hints: %X0
missed hint %X0
assigning %vreg4 to %X23: W23 [80r,448r:0)  0@80r

selectOrSplit GPR64sp:%vreg24 [176r,240r:0)  0@176r w=4.353448e-03
hints: %X0
assigning %vreg24 to %X0: W0 [176r,240r:0)  0@176r

selectOrSplit GPR32:%vreg17 [592r,632r:0)  0@592r w=4.590909e-03
hints: %W1
assigning %vreg17 to %W1: W1 [592r,632r:0)  0@592r

selectOrSplit GPR64:%vreg47 [1848r,1888r:0)  0@1848r w=2.295454e-03
hints: %X1
assigning %vreg47 to %X1: W1 [1848r,1888r:0)  0@1848r

selectOrSplit GPR64all:%vreg41 [1936r,1936d:0)  0@1936r w=inf
hints: %X0
assigning %vreg41 to %X0: W0 [1936r,1936d:0)  0@1936r

selectOrSplit GPR64sp:%vreg36 [1968r,2080r:0)  0@1968r w=1.972656e-03
hints: %X1
assigning %vreg36 to %X1: W1 [1968r,2080r:0)  0@1968r

selectOrSplit GPR64all:%vreg37 [2128r,2128d:0)  0@2128r w=inf
hints: %X0
assigning %vreg37 to %X0: W0 [2128r,2128d:0)  0@2128r

selectOrSplit GPR64:%vreg62 [2288r,2336r:0)  0@2288r w=5.636160e-04
hints: %X0
assigning %vreg62 to %X0: W0 [2288r,2336r:0)  0@2288r

selectOrSplit GPR64:%vreg60 [2320r,2352r:0)  0@2320r w=2.922454e-04
hints: %X1
assigning %vreg60 to %X1: W1 [2320r,2352r:0)  0@2320r

selectOrSplit GPR32:%vreg58 [2400r,2480r:0)  0@2400r w=5.260417e-04
hints: %W0
assigning %vreg58 to %W0: W0 [2400r,2480r:0)  0@2400r

selectOrSplit GPR64:%vreg68 [2816r,2872r:0)  0@2816r w=2.768640e-04
hints: %X0
assigning %vreg68 to %X0: W0 [2816r,2872r:0)  0@2816r

selectOrSplit GPR64:%vreg66 [2912r,2976r:0)  0@2912r w=2.720905e-04
hints: %X0
assigning %vreg66 to %X0: W0 [2912r,2976r:0)  0@2912r

selectOrSplit GPR32:%vreg55 [3056r,3112r:0)  0@3056r w=1.107456e-03
hints: %W0
assigning %vreg55 to %W0: W0 [3056r,3112r:0)  0@3056r

selectOrSplit GPR64:%vreg53 [3152r,3216r:0)  0@3152r w=1.088362e-03
hints: %X0
assigning %vreg53 to %X0: W0 [3152r,3216r:0)  0@3152r

selectOrSplit GPR64:%vreg110 [3648r,3744r:0)  0@3648r w=5.090726e-04
hints: %X1
assigning %vreg110 to %X1: W1 [3648r,3744r:0)  0@3648r

selectOrSplit GPR32:%vreg109 [3664r,3760r:0)  0@3664r w=5.090726e-04
hints: %W2
assigning %vreg109 to %W2: W2 [3664r,3760r:0)  0@3664r

selectOrSplit GPR32:%vreg108 [3680r,3776r:0)  0@3680r w=5.090726e-04
hints: %W3
assigning %vreg108 to %W3: W3 [3680r,3776r:0)  0@3680r

selectOrSplit GPR32:%vreg107 [3696r,3792r:0)  0@3696r w=5.090726e-04
hints: %W4
assigning %vreg107 to %W4: W4 [3696r,3792r:0)  0@3696r

selectOrSplit GPR64:%vreg106 [3840r,3904r:0)  0@3840r w=5.441810e-04
hints: %X0
assigning %vreg106 to %X0: W0 [3840r,3904r:0)  0@3840r

selectOrSplit GPR64:%vreg93 [3984r,4080r:0)  0@3984r w=5.090726e-04
hints: %X1
assigning %vreg93 to %X1: W1 [3984r,4080r:0)  0@3984r

selectOrSplit GPR32:%vreg92 [4000r,4096r:0)  0@4000r w=5.090726e-04
hints: %W2
assigning %vreg92 to %W2: W2 [4000r,4096r:0)  0@4000r

selectOrSplit GPR32:%vreg91 [4016r,4112r:0)  0@4016r w=5.090726e-04
hints: %W3
assigning %vreg91 to %W3: W3 [4016r,4112r:0)  0@4016r

selectOrSplit GPR32:%vreg89 [4032r,4144r:0)  0@4032r w=4.931641e-04
hints: %W5
assigning %vreg89 to %W5: W5 [4032r,4144r:0)  0@4032r

selectOrSplit GPR64:%vreg88 [4192r,4256r:0)  0@4192r w=5.441810e-04
hints: %X0
assigning %vreg88 to %X0: W0 [4192r,4256r:0)  0@4192r

selectOrSplit GPR64:%vreg129 [4560r,4592r:0)  0@4560r w=1.461227e-04
hints: %X0
assigning %vreg129 to %X0: W0 [4560r,4592r:0)  0@4560r

selectOrSplit GPR32all:%vreg128 [4640r,4640d:0)  0@4640r w=inf
hints: %W0
assigning %vreg128 to %W0: W0 [4640r,4640d:0)  0@4640r

selectOrSplit GPR64sp:%vreg173 [4848r,4912r:0)  0@4848r w=4.353448e-03
hints: %X0
assigning %vreg173 to %X0: W0 [4848r,4912r:0)  0@4848r

selectOrSplit GPR64:%vreg170 [5024r,5040r:0)  0@5024r w=inf
hints: %X0
assigning %vreg170 to %X0: W0 [5024r,5040r:0)  0@5024r

selectOrSplit GPR32common:%vreg132 [1008r,1168r:0)  0@1008r w=2.455357e-03
assigning %vreg132 to %W8: W8 [1008r,1168r:0)  0@1008r

selectOrSplit GPR64:%vreg175 [2592r,2640B:1)[2688r,2720B:0)[2720B,2752r:2)  0@2688r 1@2592r 2@2720B-phi w=7.352941e-04
assigning %vreg175 to %X8: W8 [2592r,2640B:1)[2688r,2720B:0)[2720B,2752r:2)  0@2688r 1@2592r 2@2720B-phi

selectOrSplit GPR64common:%vreg22 [160r,176r:0)  0@160r w=inf
assigning %vreg22 to %X8: W8 [160r,176r:0)  0@160r

selectOrSplit GPR32:%vreg13 [304r,720r:0)  0@304r w=1.225490e-03
assigning %vreg13 to %W24: W24 [304r,720r:0)  0@304r

selectOrSplit GPR32:%vreg21 [384r,512r:0)  0@384r w=1.893939e-03
assigning %vreg21 to %W8: W8 [384r,512r:0)  0@384r

selectOrSplit GPR64:%vreg12 [768r,784r:0)  0@768r w=inf
assigning %vreg12 to %X8: W8 [768r,784r:0)  0@768r

selectOrSplit GPR64common:%vreg31 [912r,928r:0)  0@912r w=inf
assigning %vreg31 to %X8: W8 [912r,928r:0)  0@912r

selectOrSplit GPR32:%vreg30 [928r,944r:0)  0@928r w=inf
assigning %vreg30 to %W8: W8 [928r,944r:0)  0@928r

selectOrSplit GPR32:%vreg28 [944r,960r:0)  0@944r w=inf
assigning %vreg28 to %W8: W8 [944r,960r:0)  0@944r

selectOrSplit GPR64common:%vreg133 [992r,1008r:0)  0@992r w=inf
assigning %vreg133 to %X8: W8 [992r,1008r:0)  0@992r

selectOrSplit GPR32:%vreg135 [1040r,1040d:0)  0@1040r w=inf
assigning %vreg135 to %W9: W9 [1040r,1040d:0)  0@1040r

selectOrSplit GPR32:%vreg136 [1104r,1104d:0)  0@1104r w=inf
assigning %vreg136 to %W9: W9 [1104r,1104d:0)  0@1104r

selectOrSplit GPR32:%vreg137 [1168r,1168d:0)  0@1168r w=inf
assigning %vreg137 to %W8: W8 [1168r,1168d:0)  0@1168r

selectOrSplit GPR32:%vreg139 [1280r,1296r:0)  0@1280r w=inf
assigning %vreg139 to %W8: W8 [1280r,1296r:0)  0@1280r

selectOrSplit GPR32:%vreg138 [1344r,1360r:0)  0@1344r w=inf
assigning %vreg138 to %W8: W8 [1344r,1360r:0)  0@1344r

selectOrSplit GPR64common:%vreg147 [1440r,1456r:0)  0@1440r w=inf
assigning %vreg147 to %X8: W8 [1440r,1456r:0)  0@1440r

selectOrSplit GPR32common:%vreg146 [1456r,1472r:0)  0@1456r w=inf
assigning %vreg146 to %W8: W8 [1456r,1472r:0)  0@1456r

selectOrSplit GPR32sp:%vreg142 [1472r,1488r:0)  0@1472r w=inf
assigning %vreg142 to %W8: W8 [1472r,1488r:0)  0@1472r

selectOrSplit GPR64common:%vreg163 [1536r,1552r:0)  0@1536r w=inf
assigning %vreg163 to %X8: W8 [1536r,1552r:0)  0@1536r

selectOrSplit GPR32common:%vreg162 [1552r,1568r:0)  0@1552r w=inf
assigning %vreg162 to %W8: W8 [1552r,1568r:0)  0@1552r

selectOrSplit GPR32common:%vreg158 [1568r,1584r:0)  0@1568r w=inf
assigning %vreg158 to %W8: W8 [1568r,1584r:0)  0@1568r

selectOrSplit GPR64common:%vreg167 [1648r,1664r:0)  0@1648r w=inf
assigning %vreg167 to %X8: W8 [1648r,1664r:0)  0@1648r

selectOrSplit GPR64common:%vreg166 [1664r,1680r:0)  0@1664r w=inf
assigning %vreg166 to %X8: W8 [1664r,1680r:0)  0@1664r

selectOrSplit GPR64common:%vreg43 [1728r,1816r:0)  0@1728r w=1.024590e-03
assigning %vreg43 to %X8: W8 [1728r,1816r:0)  0@1728r

selectOrSplit GPR32common:%vreg48 [1808r,1840r:0)  0@1808r w=2.314815e-03
assigning %vreg48 to %W9: W9 [1808r,1840r:0)  0@1808r

selectOrSplit GPR64common:%vreg44 [1816r,1848r:0)  0@1816r w=2.314815e-03
assigning %vreg44 to %X8: W8 [1816r,1848r:0)  0@1816r

selectOrSplit GPR64common:%vreg45 [1824r,1832r:0)  0@1824r w=inf
assigning %vreg45 to %X10: W10 [1824r,1832r:0)  0@1824r

selectOrSplit GPR64common:%vreg46 [1832r,1848r:0)  0@1832r w=2.403846e-03
assigning %vreg46 to %X10: W10 [1832r,1848r:0)  0@1832r

selectOrSplit GPR64common:%vreg35 [1952r,1968r:0)  0@1952r w=inf
assigning %vreg35 to %X8: W8 [1952r,1968r:0)  0@1952r

selectOrSplit GPR32:%vreg33 [2192r,2208r:0)  0@2192r w=inf
assigning %vreg33 to %W8: W8 [2192r,2208r:0)  0@2192r

selectOrSplit GPR64:%vreg57 [2240r,2256r:0)  0@2240r w=inf
assigning %vreg57 to %X8: W8 [2240r,2256r:0)  0@2240r

selectOrSplit GPR32:%vreg70 [2512r,2528r:0)  0@2512r w=inf
assigning %vreg70 to %W8: W8 [2512r,2528r:0)  0@2512r

selectOrSplit GPR64common:%vreg74 [2560r,2576r:0)  0@2560r w=inf
assigning %vreg74 to %X8: W8 [2560r,2576r:0)  0@2560r

selectOrSplit GPR64sp:%vreg75 [2576r,2592r:0)  0@2576r w=inf
assigning %vreg75 to %X8: W8 [2576r,2592r:0)  0@2576r

selectOrSplit GPR64common:%vreg71 [2656r,2672r:0)  0@2656r w=inf
assigning %vreg71 to %X8: W8 [2656r,2672r:0)  0@2656r

selectOrSplit GPR64sp:%vreg72 [2672r,2688r:0)  0@2672r w=inf
assigning %vreg72 to %X8: W8 [2672r,2688r:0)  0@2672r

selectOrSplit GPR64:%vreg78 [3248r,3264r:0)  0@3248r w=inf
assigning %vreg78 to %X8: W8 [3248r,3264r:0)  0@3248r

selectOrSplit GPR32:%vreg80 [3360r,3376r:0)  0@3360r w=inf
assigning %vreg80 to %W8: W8 [3360r,3376r:0)  0@3360r

selectOrSplit GPR32common:%vreg95 [3408r,3424r:0)  0@3408r w=inf
assigning %vreg95 to %W8: W8 [3408r,3424r:0)  0@3408r

selectOrSplit GPR32:%vreg96 [3472r,3488r:0)  0@3472r w=inf
assigning %vreg96 to %W8: W8 [3472r,3488r:0)  0@3472r

selectOrSplit GPR32common:%vreg98 [3520r,3536r:0)  0@3520r w=inf
assigning %vreg98 to %W8: W8 [3520r,3536r:0)  0@3520r

selectOrSplit GPR32:%vreg99 [3584r,3600r:0)  0@3584r w=inf
assigning %vreg99 to %W8: W8 [3584r,3600r:0)  0@3584r

selectOrSplit GPR64:%vreg112 [4288r,4304r:0)  0@4288r w=inf
assigning %vreg112 to %X8: W8 [4288r,4304r:0)  0@4288r

selectOrSplit GPR64common:%vreg117 [4336r,4352r:0)  0@4336r w=inf
assigning %vreg117 to %X8: W8 [4336r,4352r:0)  0@4336r

selectOrSplit GPR64sp:%vreg118 [4352r,4384r:0)  0@4352r w=5.787037e-04
assigning %vreg118 to %X8: W8 [4352r,4384r:0)  0@4352r

selectOrSplit GPR64:%vreg120 [4368r,4400r:0)  0@4368r w=5.787037e-04
assigning %vreg120 to %X9: W9 [4368r,4400r:0)  0@4368r

selectOrSplit GPR64:%vreg119 [4384r,4400r:0)  0@4384r w=inf
assigning %vreg119 to %X8: W8 [4384r,4400r:0)  0@4384r

selectOrSplit GPR64common:%vreg123 [4448r,4464r:0)  0@4448r w=inf
assigning %vreg123 to %X8: W8 [4448r,4464r:0)  0@4448r

selectOrSplit GPR64sp:%vreg124 [4464r,4496r:0)  0@4464r w=2.893519e-04
assigning %vreg124 to %X8: W8 [4464r,4496r:0)  0@4464r

selectOrSplit GPR64:%vreg126 [4480r,4512r:0)  0@4480r w=2.893519e-04
assigning %vreg126 to %X9: W9 [4480r,4512r:0)  0@4480r

selectOrSplit GPR64:%vreg125 [4496r,4512r:0)  0@4496r w=inf
assigning %vreg125 to %X8: W8 [4496r,4512r:0)  0@4496r

selectOrSplit GPR64:%vreg114 [4784r,4800r:0)  0@4784r w=inf
assigning %vreg114 to %X8: W8 [4784r,4800r:0)  0@4784r

selectOrSplit GPR64common:%vreg171 [4832r,4848r:0)  0@4832r w=inf
assigning %vreg171 to %X8: W8 [4832r,4848r:0)  0@4832r

********** STACK TRANSFORMATION METADATA **********
********** Function: bzopen_or_bzdopen
********** REGISTER MAP **********
[%vreg4 -> %X23] GPR64
[%vreg6 -> %W22] GPR32
[%vreg8 -> %X21] GPR64
[%vreg10 -> %W20] GPR32
[%vreg12 -> %X8] GPR64
[%vreg13 -> %W24] GPR32
[%vreg17 -> %W1] GPR32
[%vreg21 -> %W8] GPR32
[%vreg22 -> %X8] GPR64common
[%vreg24 -> %X0] GPR64sp
[%vreg25 -> %X19] GPR64
[%vreg28 -> %W8] GPR32
[%vreg30 -> %W8] GPR32
[%vreg31 -> %X8] GPR64common
[%vreg33 -> %W8] GPR32
[%vreg35 -> %X8] GPR64common
[%vreg36 -> %X1] GPR64sp
[%vreg37 -> %X0] GPR64all
[%vreg41 -> %X0] GPR64all
[%vreg43 -> %X8] GPR64common
[%vreg44 -> %X8] GPR64common
[%vreg45 -> %X10] GPR64common
[%vreg46 -> %X10] GPR64common
[%vreg47 -> %X1] GPR64
[%vreg48 -> %W9] GPR32common
[%vreg53 -> %X0] GPR64
[%vreg55 -> %W0] GPR32
[%vreg57 -> %X8] GPR64
[%vreg58 -> %W0] GPR32
[%vreg60 -> %X1] GPR64
[%vreg62 -> %X0] GPR64
[%vreg66 -> %X0] GPR64
[%vreg68 -> %X0] GPR64
[%vreg70 -> %W8] GPR32
[%vreg71 -> %X8] GPR64common
[%vreg72 -> %X8] GPR64sp
[%vreg74 -> %X8] GPR64common
[%vreg75 -> %X8] GPR64sp
[%vreg78 -> %X8] GPR64
[%vreg80 -> %W8] GPR32
[%vreg88 -> %X0] GPR64
[%vreg89 -> %W5] GPR32
[%vreg91 -> %W3] GPR32
[%vreg92 -> %W2] GPR32
[%vreg93 -> %X1] GPR64
[%vreg95 -> %W8] GPR32common
[%vreg96 -> %W8] GPR32
[%vreg98 -> %W8] GPR32common
[%vreg99 -> %W8] GPR32
[%vreg106 -> %X0] GPR64
[%vreg107 -> %W4] GPR32
[%vreg108 -> %W3] GPR32
[%vreg109 -> %W2] GPR32
[%vreg110 -> %X1] GPR64
[%vreg112 -> %X8] GPR64
[%vreg114 -> %X8] GPR64
[%vreg117 -> %X8] GPR64common
[%vreg118 -> %X8] GPR64sp
[%vreg119 -> %X8] GPR64
[%vreg120 -> %X9] GPR64
[%vreg123 -> %X8] GPR64common
[%vreg124 -> %X8] GPR64sp
[%vreg125 -> %X8] GPR64
[%vreg126 -> %X9] GPR64
[%vreg128 -> %W0] GPR32all
[%vreg129 -> %X0] GPR64
[%vreg132 -> %W8] GPR32common
[%vreg133 -> %X8] GPR64common
[%vreg135 -> %W9] GPR32
[%vreg136 -> %W9] GPR32
[%vreg137 -> %W8] GPR32
[%vreg138 -> %W8] GPR32
[%vreg139 -> %W8] GPR32
[%vreg142 -> %W8] GPR32sp
[%vreg146 -> %W8] GPR32common
[%vreg147 -> %X8] GPR64common
[%vreg158 -> %W8] GPR32common
[%vreg162 -> %W8] GPR32common
[%vreg163 -> %X8] GPR64common
[%vreg166 -> %X8] GPR64common
[%vreg167 -> %X8] GPR64common
[%vreg170 -> %X0] GPR64
[%vreg171 -> %X8] GPR64common
[%vreg173 -> %X0] GPR64sp
[%vreg175 -> %X8] GPR64


Stackmap 0:
  STACKMAP 0, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, %vreg6, 0, <fi#2>, 0, 0, <fi#10>, 0, %vreg8, 0, <fi#3>, 0, 0, <fi#9>, 0, 0, <fi#15>, 0, %vreg10, 0, <fi#4>, 0, %vreg4, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack2](align=4) LD8[FixedStack10] LD8[FixedStack3] LD8[FixedStack9](align=1) LD8[FixedStack15](align=4) LD8[FixedStack4](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4) GPR32:%vreg6,%vreg10 GPR64:%vreg8,%vreg4

i32* %blockSize100k: in stack slot 7 (size: 4)
i32* %bzerr: in stack slot 5 (size: 4)
i8** %bzfp: in stack slot 11 (size: 8)
i32 %fd: in register %W22 (vreg 6)
i32* %fd.addr: in stack slot 2 (size: 4)
%struct._IO_FILE** %fp: in stack slot 10 (size: 8)
i8* %mode: in register %X21 (vreg 8)
i8** %mode.addr: in stack slot 3 (size: 8)
[10 x i8]* %mode2: in stack slot 9 (size: 10)
i32* %nUnused: in stack slot 15 (size: 4)
i32 %open_mode: in register %W20 (vreg 10)
i32* %open_mode.addr: in stack slot 4 (size: 4)
i8* %path: in register %X23 (vreg 4)
i8** %path.addr: in stack slot 1 (size: 8)
i8** %retval: in stack slot 0 (size: 8)
i32* %smallMode: in stack slot 14 (size: 4)
[5000 x i8]* %unused: in stack slot 6 (size: 5000)
i32* %verbosity: in stack slot 12 (size: 4)
i32* %workFactor: in stack slot 13 (size: 4)
i32* %writing: in stack slot 8 (size: 4)

Duplicate operand locations:


Stackmap 2:
  STACKMAP 2, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#2>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, 0, <fi#15>, 0, 0, <fi#4>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack2](align=4) LD8[FixedStack10] LD8[FixedStack9](align=1) LD8[FixedStack15](align=4) LD8[FixedStack4](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)

i32* %blockSize100k: in stack slot 7 (size: 4)
i32* %bzerr: in stack slot 5 (size: 4)
i8** %bzfp: in stack slot 11 (size: 8)
i32* %fd.addr: in stack slot 2 (size: 4)
%struct._IO_FILE** %fp: in stack slot 10 (size: 8)
[10 x i8]* %mode2: in stack slot 9 (size: 10)
i32* %nUnused: in stack slot 15 (size: 4)
i32* %open_mode.addr: in stack slot 4 (size: 4)
i8** %path.addr: in stack slot 1 (size: 8)
i8** %retval: in stack slot 0 (size: 8)
i32* %smallMode: in stack slot 14 (size: 4)
[5000 x i8]* %unused: in stack slot 6 (size: 5000)
i32* %verbosity: in stack slot 12 (size: 4)
i32* %workFactor: in stack slot 13 (size: 4)
i32* %writing: in stack slot 8 (size: 4)

Duplicate operand locations:


Stackmap 3:
  STACKMAP 3, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#2>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, 0, <fi#15>, 0, 0, <fi#4>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack2](align=4) LD8[FixedStack10] LD8[FixedStack9](align=1) LD8[FixedStack15](align=4) LD8[FixedStack4](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)

i32* %blockSize100k: in stack slot 7 (size: 4)
i32* %bzerr: in stack slot 5 (size: 4)
i8** %bzfp: in stack slot 11 (size: 8)
i32* %fd.addr: in stack slot 2 (size: 4)
%struct._IO_FILE** %fp: in stack slot 10 (size: 8)
[10 x i8]* %mode2: in stack slot 9 (size: 10)
i32* %nUnused: in stack slot 15 (size: 4)
i32* %open_mode.addr: in stack slot 4 (size: 4)
i8** %path.addr: in stack slot 1 (size: 8)
i8** %retval: in stack slot 0 (size: 8)
i32* %smallMode: in stack slot 14 (size: 4)
[5000 x i8]* %unused: in stack slot 6 (size: 5000)
i32* %verbosity: in stack slot 12 (size: 4)
i32* %workFactor: in stack slot 13 (size: 4)
i32* %writing: in stack slot 8 (size: 4)

Duplicate operand locations:


Stackmap 4:
  STACKMAP 4, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, 0, <fi#15>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack9](align=1) LD8[FixedStack15](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)

i32* %blockSize100k: in stack slot 7 (size: 4)
i32* %bzerr: in stack slot 5 (size: 4)
i8** %bzfp: in stack slot 11 (size: 8)
%struct._IO_FILE** %fp: in stack slot 10 (size: 8)
[10 x i8]* %mode2: in stack slot 9 (size: 10)
i32* %nUnused: in stack slot 15 (size: 4)
i8** %path.addr: in stack slot 1 (size: 8)
i8** %retval: in stack slot 0 (size: 8)
i32* %smallMode: in stack slot 14 (size: 4)
[5000 x i8]* %unused: in stack slot 6 (size: 5000)
i32* %verbosity: in stack slot 12 (size: 4)
i32* %workFactor: in stack slot 13 (size: 4)
i32* %writing: in stack slot 8 (size: 4)

Duplicate operand locations:


Stackmap 5:
  STACKMAP 5, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#15>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack15](align=4) LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)

i32* %blockSize100k: in stack slot 7 (size: 4)
i32* %bzerr: in stack slot 5 (size: 4)
i8** %bzfp: in stack slot 11 (size: 8)
%struct._IO_FILE** %fp: in stack slot 10 (size: 8)
i32* %nUnused: in stack slot 15 (size: 4)
i8** %retval: in stack slot 0 (size: 8)
i32* %smallMode: in stack slot 14 (size: 4)
[5000 x i8]* %unused: in stack slot 6 (size: 5000)
i32* %verbosity: in stack slot 12 (size: 4)
i32* %workFactor: in stack slot 13 (size: 4)
i32* %writing: in stack slot 8 (size: 4)

Duplicate operand locations:


Stackmap 6:
  STACKMAP 6, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#15>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack15](align=4) LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)

i32* %blockSize100k: in stack slot 7 (size: 4)
i32* %bzerr: in stack slot 5 (size: 4)
i8** %bzfp: in stack slot 11 (size: 8)
%struct._IO_FILE** %fp: in stack slot 10 (size: 8)
i32* %nUnused: in stack slot 15 (size: 4)
i8** %retval: in stack slot 0 (size: 8)
i32* %smallMode: in stack slot 14 (size: 4)
[5000 x i8]* %unused: in stack slot 6 (size: 5000)
i32* %verbosity: in stack slot 12 (size: 4)
i32* %workFactor: in stack slot 13 (size: 4)
i32* %writing: in stack slot 8 (size: 4)

Duplicate operand locations:


Stackmap 7:
  STACKMAP 7, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack0]

i8** %bzfp: in stack slot 11 (size: 8)
%struct._IO_FILE** %fp: in stack slot 10 (size: 8)
i8** %retval: in stack slot 0 (size: 8)

Duplicate operand locations:


Stackmap 8:
  STACKMAP 8, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack0]

i8** %bzfp: in stack slot 11 (size: 8)
%struct._IO_FILE** %fp: in stack slot 10 (size: 8)
i8** %retval: in stack slot 0 (size: 8)

Duplicate operand locations:


Stackmap 9:
  STACKMAP 9, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0]

i8** %retval: in stack slot 0 (size: 8)

Duplicate operand locations:


Stackmap 10:
  STACKMAP 10, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0]

i8** %retval: in stack slot 0 (size: 8)

Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, %vreg6, 0, <fi#2>, 0, 0, <fi#10>, 0, %vreg8, 0, <fi#3>, 0, 0, <fi#9>, 0, 0, <fi#15>, 0, %vreg10, 0, <fi#4>, 0, %vreg4, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack2](align=4) LD8[FixedStack10] LD8[FixedStack3] LD8[FixedStack9](align=1) LD8[FixedStack15](align=4) LD8[FixedStack4](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4) GPR32:%vreg6,%vreg10 GPR64:%vreg8,%vreg4
  -> Call instruction SlotIndex 272B, searching vregs 0 -> 176 and stack slots 0 -> 16
    + vreg25 is live in register but not in stackmap
      Defining instruction: %vreg25<def> = COPY %LR; GPR64:%vreg25
      Value: generated value, 1 instruction(s)

  STACKMAP 2, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#2>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, 0, <fi#15>, 0, 0, <fi#4>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack2](align=4) LD8[FixedStack10] LD8[FixedStack9](align=1) LD8[FixedStack15](align=4) LD8[FixedStack4](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)
  -> Call instruction SlotIndex 1904B, searching vregs 0 -> 176 and stack slots 0 -> 16
    + vreg25 is live in register but not in stackmap
      Defining instruction: %vreg25<def> = COPY %LR; GPR64:%vreg25
      Value: generated value, 1 instruction(s)

  STACKMAP 3, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#2>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, 0, <fi#15>, 0, 0, <fi#4>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack2](align=4) LD8[FixedStack10] LD8[FixedStack9](align=1) LD8[FixedStack15](align=4) LD8[FixedStack4](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)
  -> Call instruction SlotIndex 2096B, searching vregs 0 -> 176 and stack slots 0 -> 16
    + vreg25 is live in register but not in stackmap
      Defining instruction: %vreg25<def> = COPY %LR; GPR64:%vreg25
      Value: generated value, 1 instruction(s)

  STACKMAP 4, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, 0, <fi#15>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack9](align=1) LD8[FixedStack15](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)
  -> Call instruction SlotIndex 2368B, searching vregs 0 -> 176 and stack slots 0 -> 16
    + vreg25 is live in register but not in stackmap
      Defining instruction: %vreg25<def> = COPY %LR; GPR64:%vreg25
      Value: generated value, 1 instruction(s)

  STACKMAP 5, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#15>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack15](align=4) LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)
  -> Call instruction SlotIndex 2880B, searching vregs 0 -> 176 and stack slots 0 -> 16
    + vreg25 is live in register but not in stackmap
      Defining instruction: %vreg25<def> = COPY %LR; GPR64:%vreg25
      Value: generated value, 1 instruction(s)

  STACKMAP 6, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#15>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack15](align=4) LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)
  -> Call instruction SlotIndex 3120B, searching vregs 0 -> 176 and stack slots 0 -> 16
    + vreg25 is live in register but not in stackmap
      Defining instruction: %vreg25<def> = COPY %LR; GPR64:%vreg25
      Value: generated value, 1 instruction(s)

  STACKMAP 7, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack0]
  -> Call instruction SlotIndex 3808B, searching vregs 0 -> 176 and stack slots 0 -> 16
    + vreg25 is live in register but not in stackmap
      Defining instruction: %vreg25<def> = COPY %LR; GPR64:%vreg25
      Value: generated value, 1 instruction(s)

  STACKMAP 8, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack0]
  -> Call instruction SlotIndex 4160B, searching vregs 0 -> 176 and stack slots 0 -> 16
    + vreg25 is live in register but not in stackmap
      Defining instruction: %vreg25<def> = COPY %LR; GPR64:%vreg25
      Value: generated value, 1 instruction(s)

  STACKMAP 9, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0]
  -> Call instruction SlotIndex 4608B, searching vregs 0 -> 176 and stack slots 0 -> 16
    + vreg25 is live in register but not in stackmap
      Defining instruction: %vreg25<def> = COPY %LR; GPR64:%vreg25
      Value: generated value, 1 instruction(s)

  STACKMAP 10, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0]
  -> Call instruction SlotIndex 4944B, searching vregs 0 -> 176 and stack slots 0 -> 16

********** REWRITE VIRTUAL REGISTERS **********
********** Function: bzopen_or_bzdopen
********** REGISTER MAP **********
[%vreg4 -> %X23] GPR64
[%vreg6 -> %W22] GPR32
[%vreg8 -> %X21] GPR64
[%vreg10 -> %W20] GPR32
[%vreg12 -> %X8] GPR64
[%vreg13 -> %W24] GPR32
[%vreg17 -> %W1] GPR32
[%vreg21 -> %W8] GPR32
[%vreg22 -> %X8] GPR64common
[%vreg24 -> %X0] GPR64sp
[%vreg25 -> %X19] GPR64
[%vreg28 -> %W8] GPR32
[%vreg30 -> %W8] GPR32
[%vreg31 -> %X8] GPR64common
[%vreg33 -> %W8] GPR32
[%vreg35 -> %X8] GPR64common
[%vreg36 -> %X1] GPR64sp
[%vreg37 -> %X0] GPR64all
[%vreg41 -> %X0] GPR64all
[%vreg43 -> %X8] GPR64common
[%vreg44 -> %X8] GPR64common
[%vreg45 -> %X10] GPR64common
[%vreg46 -> %X10] GPR64common
[%vreg47 -> %X1] GPR64
[%vreg48 -> %W9] GPR32common
[%vreg53 -> %X0] GPR64
[%vreg55 -> %W0] GPR32
[%vreg57 -> %X8] GPR64
[%vreg58 -> %W0] GPR32
[%vreg60 -> %X1] GPR64
[%vreg62 -> %X0] GPR64
[%vreg66 -> %X0] GPR64
[%vreg68 -> %X0] GPR64
[%vreg70 -> %W8] GPR32
[%vreg71 -> %X8] GPR64common
[%vreg72 -> %X8] GPR64sp
[%vreg74 -> %X8] GPR64common
[%vreg75 -> %X8] GPR64sp
[%vreg78 -> %X8] GPR64
[%vreg80 -> %W8] GPR32
[%vreg88 -> %X0] GPR64
[%vreg89 -> %W5] GPR32
[%vreg91 -> %W3] GPR32
[%vreg92 -> %W2] GPR32
[%vreg93 -> %X1] GPR64
[%vreg95 -> %W8] GPR32common
[%vreg96 -> %W8] GPR32
[%vreg98 -> %W8] GPR32common
[%vreg99 -> %W8] GPR32
[%vreg106 -> %X0] GPR64
[%vreg107 -> %W4] GPR32
[%vreg108 -> %W3] GPR32
[%vreg109 -> %W2] GPR32
[%vreg110 -> %X1] GPR64
[%vreg112 -> %X8] GPR64
[%vreg114 -> %X8] GPR64
[%vreg117 -> %X8] GPR64common
[%vreg118 -> %X8] GPR64sp
[%vreg119 -> %X8] GPR64
[%vreg120 -> %X9] GPR64
[%vreg123 -> %X8] GPR64common
[%vreg124 -> %X8] GPR64sp
[%vreg125 -> %X8] GPR64
[%vreg126 -> %X9] GPR64
[%vreg128 -> %W0] GPR32all
[%vreg129 -> %X0] GPR64
[%vreg132 -> %W8] GPR32common
[%vreg133 -> %X8] GPR64common
[%vreg135 -> %W9] GPR32
[%vreg136 -> %W9] GPR32
[%vreg137 -> %W8] GPR32
[%vreg138 -> %W8] GPR32
[%vreg139 -> %W8] GPR32
[%vreg142 -> %W8] GPR32sp
[%vreg146 -> %W8] GPR32common
[%vreg147 -> %X8] GPR64common
[%vreg158 -> %W8] GPR32common
[%vreg162 -> %W8] GPR32common
[%vreg163 -> %X8] GPR64common
[%vreg166 -> %X8] GPR64common
[%vreg167 -> %X8] GPR64common
[%vreg170 -> %X0] GPR64
[%vreg171 -> %X8] GPR64common
[%vreg173 -> %X0] GPR64sp
[%vreg175 -> %X8] GPR64

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %LR %W1 %W3 %X0 %X2
16B		%vreg25<def> = COPY %LR; GPR64:%vreg25
32B		%vreg10<def> = COPY %W3; GPR32:%vreg10
48B		%vreg8<def> = COPY %X2; GPR64:%vreg8
64B		%vreg6<def> = COPY %W1; GPR32:%vreg6
80B		%vreg4<def> = COPY %X0; GPR64:%vreg4
160B		%vreg22<def> = ADRP <ga:@bzopen_or_bzdopen>[TF=1]; GPR64common:%vreg22
176B		%vreg24<def> = ADDXri %vreg22<kill>, <ga:@bzopen_or_bzdopen>[TF=34], 0; GPR64sp:%vreg24 GPR64common:%vreg22
224B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
240B		%X0<def> = COPY %vreg24<kill>; GPR64sp:%vreg24
256B		%X1<def> = COPY %vreg25; GPR64:%vreg25
272B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
288B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
304B		%vreg13<def> = MOVi32imm 30; GPR32:%vreg13
384B		%vreg21<def> = MOVi32imm 9; GPR32:%vreg21
400B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
416B		STACKMAP 0, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, %vreg6, 0, <fi#2>, 0, 0, <fi#10>, 0, %vreg8, 0, <fi#3>, 0, 0, <fi#9>, 0, 0, <fi#15>, 0, %vreg10, 0, <fi#4>, 0, %vreg4, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack2](align=4) LD8[FixedStack10] LD8[FixedStack3] LD8[FixedStack9](align=1) LD8[FixedStack15](align=4) LD8[FixedStack4](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4) GPR32:%vreg6,%vreg10 GPR64:%vreg8,%vreg4
432B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
448B		STRXui %vreg4<kill>, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg4
464B		STRWui %vreg6<kill>, <fi#2>, 0; mem:ST4[FixedStack2] GPR32:%vreg6
480B		STRXui %vreg8<kill>, <fi#3>, 0; mem:ST8[FixedStack3] GPR64:%vreg8
496B		STRWui %vreg10<kill>, <fi#4>, 0; mem:ST4[FixedStack4] GPR32:%vreg10
512B		STRWui %vreg21<kill>, <fi#7>, 0; mem:ST4[FixedStack7] GPR32:%vreg21
528B		STRWui %WZR, <fi#8>, 0; mem:ST4[FixedStack8]
560B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
576B		%X0<def> = ADDXri <fi#9>, 0, 0
592B		%vreg17<def> = UBFMWri %WZR, 0, 7; GPR32:%vreg17
624B		%X2<def> = MOVi64imm 10
632B		%W1<def> = COPY %vreg17<kill>; GPR32:%vreg17
640B		BL <MCSym=memset>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %X2<imp-use>
656B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
672B		STRXui %XZR, <fi#10>, 0; mem:ST8[FixedStack10]
688B		STRXui %XZR, <fi#11>, 0; mem:ST8[FixedStack11]
704B		STRWui %WZR, <fi#12>, 0; mem:ST4[FixedStack12]
720B		STRWui %vreg13<kill>, <fi#13>, 0; mem:ST4[FixedStack13] GPR32:%vreg13
736B		STRWui %WZR, <fi#14>, 0; mem:ST4[FixedStack14]
752B		STRWui %WZR, <fi#15>, 0; mem:ST4[FixedStack15]
768B		%vreg12<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64:%vreg12
784B		CBNZX %vreg12<kill>, <BB#2>; GPR64:%vreg12
	    Successors according to CFG: BB#2 BB#1
> %X19<def> = COPY %LR
> %W20<def> = COPY %W3
> %X21<def> = COPY %X2
> %W22<def> = COPY %W1
> %X23<def> = COPY %X0
> %X8<def> = ADRP <ga:@bzopen_or_bzdopen>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@bzopen_or_bzdopen>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19
> BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W24<def> = MOVi32imm 30
> %W8<def> = MOVi32imm 9
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 0, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, %W22, 0, <fi#2>, 0, 0, <fi#10>, 0, %X21, 0, <fi#3>, 0, 0, <fi#9>, 0, 0, <fi#15>, 0, %W20, 0, <fi#4>, 0, %X23, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack2](align=4) LD8[FixedStack10] LD8[FixedStack3] LD8[FixedStack9](align=1) LD8[FixedStack15](align=4) LD8[FixedStack4](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRXui %X23<kill>, <fi#1>, 0; mem:ST8[FixedStack1]
> STRWui %W22<kill>, <fi#2>, 0; mem:ST4[FixedStack2]
> STRXui %X21<kill>, <fi#3>, 0; mem:ST8[FixedStack3]
> STRWui %W20<kill>, <fi#4>, 0; mem:ST4[FixedStack4]
> STRWui %W8<kill>, <fi#7>, 0; mem:ST4[FixedStack7]
> STRWui %WZR, <fi#8>, 0; mem:ST4[FixedStack8]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = ADDXri <fi#9>, 0, 0
> %W1<def> = UBFMWri %WZR, 0, 7
> %X2<def> = MOVi64imm 10
> %W1<def> = COPY %W1<kill>
Deleting identity copy.
> BL <MCSym=memset>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %X2<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRXui %XZR, <fi#10>, 0; mem:ST8[FixedStack10]
> STRXui %XZR, <fi#11>, 0; mem:ST8[FixedStack11]
> STRWui %WZR, <fi#12>, 0; mem:ST4[FixedStack12]
> STRWui %W24<kill>, <fi#13>, 0; mem:ST4[FixedStack13]
> STRWui %WZR, <fi#14>, 0; mem:ST4[FixedStack14]
> STRWui %WZR, <fi#15>, 0; mem:ST4[FixedStack15]
> %X8<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> CBNZX %X8<kill>, <BB#2>
800B	BB#1: derived from LLVM BB %if.then
	    Live Ins: %X19
	    Predecessors according to CFG: BB#0
832B		STRXui %XZR, <fi#0>, 0; mem:ST8[FixedStack0]
848B		B <BB#40>
	    Successors according to CFG: BB#40
> STRXui %XZR, <fi#0>, 0; mem:ST8[FixedStack0]
> B <BB#40>
864B	BB#2: derived from LLVM BB %if.end
	    Live Ins: %X19
	    Predecessors according to CFG: BB#0
880B		B <BB#3>
	    Successors according to CFG: BB#3
> B <BB#3>
896B	BB#3: derived from LLVM BB %while.cond
	    Live Ins: %X19
	    Predecessors according to CFG: BB#2 BB#14
912B		%vreg31<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg31
928B		%vreg30<def> = LDRBBui %vreg31<kill>, 0; mem:LD1[%2] GPR32:%vreg30 GPR64common:%vreg31
944B		%vreg28<def> = UBFMWri %vreg30<kill>, 0, 7; GPR32:%vreg28,%vreg30
960B		CBZW %vreg28<kill>, <BB#15>; GPR32:%vreg28
	    Successors according to CFG: BB#15 BB#4
> %X8<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> %W8<def> = LDRBBui %X8<kill>, 0; mem:LD1[%2]
> %W8<def> = UBFMWri %W8<kill>, 0, 7
> CBZW %W8<kill>, <BB#15>
976B	BB#4: derived from LLVM BB %while.body
	    Live Ins: %X19
	    Predecessors according to CFG: BB#3
992B		%vreg133<def> = LDRXui <fi#3>, 0; mem:LD8[%mode.addr] GPR64common:%vreg133
1008B		%vreg132<def> = LDRSBWui %vreg133<kill>, 0; mem:LD1[%4] GPR32common:%vreg132 GPR64common:%vreg133
1040B		%vreg135<def,dead> = SUBSWri %vreg132, 114, 0, %NZCV<imp-def>; GPR32:%vreg135 GPR32common:%vreg132
1056B		Bcc 0, <BB#7>, %NZCV<imp-use,kill>
1072B		B <BB#5>
	    Successors according to CFG: BB#7 BB#5
> %X8<def> = LDRXui <fi#3>, 0; mem:LD8[%mode.addr]
> %W8<def> = LDRSBWui %X8<kill>, 0; mem:LD1[%4]
> %W9<def,dead> = SUBSWri %W8, 114, 0, %NZCV<imp-def>
> Bcc 0, <BB#7>, %NZCV<imp-use,kill>
> B <BB#5>
1088B	BB#5: derived from LLVM BB %while.body
	    Live Ins: %W8 %X19
	    Predecessors according to CFG: BB#4
1104B		%vreg136<def,dead> = SUBSWri %vreg132, 115, 0, %NZCV<imp-def>; GPR32:%vreg136 GPR32common:%vreg132
1120B		Bcc 0, <BB#9>, %NZCV<imp-use,kill>
1136B		B <BB#6>
	    Successors according to CFG: BB#9 BB#6
> %W9<def,dead> = SUBSWri %W8, 115, 0, %NZCV<imp-def>
> Bcc 0, <BB#9>, %NZCV<imp-use,kill>
> B <BB#6>
1152B	BB#6: derived from LLVM BB %while.body
	    Live Ins: %W8 %X19
	    Predecessors according to CFG: BB#5
1168B		%vreg137<def,dead> = SUBSWri %vreg132<kill>, 119, 0, %NZCV<imp-def>; GPR32:%vreg137 GPR32common:%vreg132
1184B		Bcc 0, <BB#8>, %NZCV<imp-use,kill>
1200B		B <BB#10>
	    Successors according to CFG: BB#8 BB#10
> %W8<def,dead> = SUBSWri %W8<kill>, 119, 0, %NZCV<imp-def>
> Bcc 0, <BB#8>, %NZCV<imp-use,kill>
> B <BB#10>
1216B	BB#7: derived from LLVM BB %sw.bb
	    Live Ins: %X19
	    Predecessors according to CFG: BB#4
1232B		STRWui %WZR, <fi#8>, 0; mem:ST4[FixedStack8]
1248B		B <BB#14>
	    Successors according to CFG: BB#14
> STRWui %WZR, <fi#8>, 0; mem:ST4[FixedStack8]
> B <BB#14>
1264B	BB#8: derived from LLVM BB %sw.bb.1
	    Live Ins: %X19
	    Predecessors according to CFG: BB#6
1280B		%vreg139<def> = MOVi32imm 1; GPR32:%vreg139
1296B		STRWui %vreg139<kill>, <fi#8>, 0; mem:ST4[FixedStack8] GPR32:%vreg139
1312B		B <BB#14>
	    Successors according to CFG: BB#14
> %W8<def> = MOVi32imm 1
> STRWui %W8<kill>, <fi#8>, 0; mem:ST4[FixedStack8]
> B <BB#14>
1328B	BB#9: derived from LLVM BB %sw.bb.2
	    Live Ins: %X19
	    Predecessors according to CFG: BB#5
1344B		%vreg138<def> = MOVi32imm 1; GPR32:%vreg138
1360B		STRWui %vreg138<kill>, <fi#14>, 0; mem:ST4[FixedStack14] GPR32:%vreg138
1376B		B <BB#14>
	    Successors according to CFG: BB#14
> %W8<def> = MOVi32imm 1
> STRWui %W8<kill>, <fi#14>, 0; mem:ST4[FixedStack14]
> B <BB#14>
1392B	BB#10: derived from LLVM BB %sw.default
	    Live Ins: %X19
	    Predecessors according to CFG: BB#6
1408B		B <BB#11>
	    Successors according to CFG: BB#11
> B <BB#11>
1424B	BB#11: derived from LLVM BB %cond.false
	    Live Ins: %X19
	    Predecessors according to CFG: BB#10
1440B		%vreg147<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg147
1456B		%vreg146<def> = LDRSBWui %vreg147<kill>, 0; mem:LD1[%8] GPR32common:%vreg146 GPR64common:%vreg147
1472B		%vreg142<def> = SUBWri %vreg146<kill>, 48, 0; GPR32sp:%vreg142 GPR32common:%vreg146
1488B		%WZR<def> = SUBSWri %vreg142<kill>, 10, 0, %NZCV<imp-def>; GPR32sp:%vreg142
1504B		Bcc 2, <BB#13>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#13 BB#12
> %X8<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> %W8<def> = LDRSBWui %X8<kill>, 0; mem:LD1[%8]
> %W8<def> = SUBWri %W8<kill>, 48, 0
> %WZR<def> = SUBSWri %W8<kill>, 10, 0, %NZCV<imp-def>
> Bcc 2, <BB#13>, %NZCV<imp-use,kill>
1520B	BB#12: derived from LLVM BB %if.then.8
	    Live Ins: %X19
	    Predecessors according to CFG: BB#11
1536B		%vreg163<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg163
1552B		%vreg162<def> = LDRSBWui %vreg163<kill>, 0; mem:LD1[%10] GPR32common:%vreg162 GPR64common:%vreg163
1568B		%vreg158<def> = SUBWri %vreg162<kill>, 48, 0; GPR32common:%vreg158,%vreg162
1584B		STRWui %vreg158<kill>, <fi#7>, 0; mem:ST4[FixedStack7] GPR32common:%vreg158
	    Successors according to CFG: BB#13
> %X8<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> %W8<def> = LDRSBWui %X8<kill>, 0; mem:LD1[%10]
> %W8<def> = SUBWri %W8<kill>, 48, 0
> STRWui %W8<kill>, <fi#7>, 0; mem:ST4[FixedStack7]
1600B	BB#13: derived from LLVM BB %if.end.11
	    Live Ins: %X19
	    Predecessors according to CFG: BB#11 BB#12
1616B		B <BB#14>
	    Successors according to CFG: BB#14
> B <BB#14>
1632B	BB#14: derived from LLVM BB %sw.epilog
	    Live Ins: %X19
	    Predecessors according to CFG: BB#9 BB#8 BB#7 BB#13
1648B		%vreg167<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3] GPR64common:%vreg167
1664B		%vreg166<def> = ADDXri %vreg167<kill>, 1, 0; GPR64common:%vreg166,%vreg167
1680B		STRXui %vreg166<kill>, <fi#3>, 0; mem:ST8[FixedStack3] GPR64common:%vreg166
1696B		B <BB#3>
	    Successors according to CFG: BB#3
> %X8<def> = LDRXui <fi#3>, 0; mem:LD8[FixedStack3]
> %X8<def> = ADDXri %X8<kill>, 1, 0
> STRXui %X8<kill>, <fi#3>, 0; mem:ST8[FixedStack3]
> B <BB#3>
1712B	BB#15: derived from LLVM BB %while.end
	    Live Ins: %X19
	    Predecessors according to CFG: BB#3
1728B		%vreg43<def> = ADRP <ga:@bzlib__str_6_w_>[TF=1]; GPR64common:%vreg43
1808B		%vreg48<def> = LDRWui <fi#8>, 0; mem:LD4[FixedStack8] GPR32common:%vreg48
1816B		%vreg44<def> = ADDXri %vreg43<kill>, <ga:@bzlib__str_6_w_>[TF=34], 0; GPR64common:%vreg44,%vreg43
1824B		%vreg45<def> = ADRP <ga:@bzlib__str_7_r_>[TF=1]; GPR64common:%vreg45
1832B		%vreg46<def> = ADDXri %vreg45<kill>, <ga:@bzlib__str_7_r_>[TF=34], 0; GPR64common:%vreg46,%vreg45
1840B		%WZR<def> = SUBSWri %vreg48<kill>, 0, 0, %NZCV<imp-def>; GPR32common:%vreg48
1848B		%vreg47<def> = CSELXr %vreg44<kill>, %vreg46<kill>, 1, %NZCV<imp-use,kill>; GPR64:%vreg47 GPR64common:%vreg44,%vreg46
1856B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1872B		%X0<def> = ADDXri <fi#9>, 0, 0
1888B		%X1<def> = COPY %vreg47<kill>; GPR64:%vreg47
1904B		BL <ga:@strcat>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %X0<imp-def>
1920B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1936B		%vreg41<def,dead> = COPY %X0; GPR64all:%vreg41
1952B		%vreg35<def> = ADRP <ga:@bzlib__str_8_b_>[TF=1]; GPR64common:%vreg35
1968B		%vreg36<def> = ADDXri %vreg35<kill>, <ga:@bzlib__str_8_b_>[TF=34], 0; GPR64sp:%vreg36 GPR64common:%vreg35
2000B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2016B		STACKMAP 2, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#2>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, 0, <fi#15>, 0, 0, <fi#4>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack2](align=4) LD8[FixedStack10] LD8[FixedStack9](align=1) LD8[FixedStack15](align=4) LD8[FixedStack4](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)
2032B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2048B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2064B		%X0<def> = ADDXri <fi#9>, 0, 0
2080B		%X1<def> = COPY %vreg36<kill>; GPR64sp:%vreg36
2096B		BL <ga:@strcat>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %X0<imp-def>
2112B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2128B		%vreg37<def,dead> = COPY %X0; GPR64all:%vreg37
2144B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2160B		STACKMAP 3, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#2>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, 0, <fi#15>, 0, 0, <fi#4>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack2](align=4) LD8[FixedStack10] LD8[FixedStack9](align=1) LD8[FixedStack15](align=4) LD8[FixedStack4](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)
2176B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2192B		%vreg33<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg33
2208B		CBNZW %vreg33<kill>, <BB#24>; GPR32:%vreg33
	    Successors according to CFG: BB#24 BB#16
> %X8<def> = ADRP <ga:@bzlib__str_6_w_>[TF=1]
> %W9<def> = LDRWui <fi#8>, 0; mem:LD4[FixedStack8]
> %X8<def> = ADDXri %X8<kill>, <ga:@bzlib__str_6_w_>[TF=34], 0
> %X10<def> = ADRP <ga:@bzlib__str_7_r_>[TF=1]
> %X10<def> = ADDXri %X10<kill>, <ga:@bzlib__str_7_r_>[TF=34], 0
> %WZR<def> = SUBSWri %W9<kill>, 0, 0, %NZCV<imp-def>
> %X1<def> = CSELXr %X8<kill>, %X10<kill>, 1, %NZCV<imp-use,kill>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = ADDXri <fi#9>, 0, 0
> %X1<def> = COPY %X1<kill>
Deleting identity copy.
> BL <ga:@strcat>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %X0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X0<def,dead> = COPY %X0
Deleting identity copy.
> %X8<def> = ADRP <ga:@bzlib__str_8_b_>[TF=1]
> %X1<def> = ADDXri %X8<kill>, <ga:@bzlib__str_8_b_>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 2, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#2>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, 0, <fi#15>, 0, 0, <fi#4>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack2](align=4) LD8[FixedStack10] LD8[FixedStack9](align=1) LD8[FixedStack15](align=4) LD8[FixedStack4](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = ADDXri <fi#9>, 0, 0
> %X1<def> = COPY %X1<kill>
Deleting identity copy.
> BL <ga:@strcat>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %X0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X0<def,dead> = COPY %X0
Deleting identity copy.
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 3, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#2>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, 0, <fi#15>, 0, 0, <fi#4>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack2](align=4) LD8[FixedStack10] LD8[FixedStack9](align=1) LD8[FixedStack15](align=4) LD8[FixedStack4](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W8<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4]
> CBNZW %W8<kill>, <BB#24>
2224B	BB#16: derived from LLVM BB %if.then.18
	    Live Ins: %X19
	    Predecessors according to CFG: BB#15
2240B		%vreg57<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg57
2256B		CBZX %vreg57<kill>, <BB#18>; GPR64:%vreg57
	    Successors according to CFG: BB#18 BB#17
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> CBZX %X8<kill>, <BB#18>
2272B	BB#17: derived from LLVM BB %lor.lhs.false
	    Live Ins: %X19
	    Predecessors according to CFG: BB#16
2288B		%vreg62<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg62
2304B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2320B		%vreg60<def> = MOVaddr <ga:@bzlib__str_9_>[TF=1], <ga:@bzlib__str_9_>[TF=34]; GPR64:%vreg60
2336B		%X0<def> = COPY %vreg62<kill>; GPR64:%vreg62
2352B		%X1<def> = COPY %vreg60<kill>; GPR64:%vreg60
2368B		BL <ga:@strcmp>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %SP<imp-def>, %W0<imp-def>
2384B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2400B		%vreg58<def> = COPY %W0; GPR32:%vreg58
2432B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2448B		STACKMAP 4, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, 0, <fi#15>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack9](align=1) LD8[FixedStack15](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)
2464B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2480B		CBNZW %vreg58<kill>, <BB#22>; GPR32:%vreg58
	    Successors according to CFG: BB#22 BB#18
> %X0<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X1<def> = MOVaddr <ga:@bzlib__str_9_>[TF=1], <ga:@bzlib__str_9_>[TF=34]
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X1<kill>
Deleting identity copy.
> BL <ga:@strcmp>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %SP<imp-def>, %W0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = COPY %W0
Deleting identity copy.
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 4, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, 0, <fi#15>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack9](align=1) LD8[FixedStack15](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> CBNZW %W0<kill>, <BB#22>
2496B	BB#18: derived from LLVM BB %if.then.24
	    Live Ins: %X19
	    Predecessors according to CFG: BB#16 BB#17
2512B		%vreg70<def> = LDRWui <fi#8>, 0; mem:LD4[FixedStack8] GPR32:%vreg70
2528B		CBZW %vreg70<kill>, <BB#20>; GPR32:%vreg70
	    Successors according to CFG: BB#20 BB#19
> %W8<def> = LDRWui <fi#8>, 0; mem:LD4[FixedStack8]
> CBZW %W8<kill>, <BB#20>
2544B	BB#19: derived from LLVM BB %cond.true.26
	    Live Ins: %X19
	    Predecessors according to CFG: BB#18
2560B		%vreg74<def> = ADRP <ga:@stdout>[TF=1]; GPR64common:%vreg74
2576B		%vreg75<def> = ADDXri %vreg74<kill>, <ga:@stdout>[TF=34], 0; GPR64sp:%vreg75 GPR64common:%vreg74
2592B		%vreg175<def> = LDRXui %vreg75<kill>, 0; mem:LD8[@stdout] GPR64:%vreg175 GPR64sp:%vreg75
2624B		B <BB#21>
	    Successors according to CFG: BB#21
> %X8<def> = ADRP <ga:@stdout>[TF=1]
> %X8<def> = ADDXri %X8<kill>, <ga:@stdout>[TF=34], 0
> %X8<def> = LDRXui %X8<kill>, 0; mem:LD8[@stdout]
> B <BB#21>
2640B	BB#20: derived from LLVM BB %cond.false.27
	    Live Ins: %X19
	    Predecessors according to CFG: BB#18
2656B		%vreg71<def> = ADRP <ga:@stdin>[TF=1]; GPR64common:%vreg71
2672B		%vreg72<def> = ADDXri %vreg71<kill>, <ga:@stdin>[TF=34], 0; GPR64sp:%vreg72 GPR64common:%vreg71
2688B		%vreg175<def> = LDRXui %vreg72<kill>, 0; mem:LD8[@stdin] GPR64:%vreg175 GPR64sp:%vreg72
	    Successors according to CFG: BB#21
> %X8<def> = ADRP <ga:@stdin>[TF=1]
> %X8<def> = ADDXri %X8<kill>, <ga:@stdin>[TF=34], 0
> %X8<def> = LDRXui %X8<kill>, 0; mem:LD8[@stdin]
2720B	BB#21: derived from LLVM BB %cond.end
	    Live Ins: %X8 %X19
	    Predecessors according to CFG: BB#20 BB#19
2752B		STRXui %vreg175<kill>, <fi#10>, 0; mem:ST8[FixedStack10] GPR64:%vreg175
2768B		B <BB#23>
	    Successors according to CFG: BB#23
> STRXui %X8<kill>, <fi#10>, 0; mem:ST8[FixedStack10]
> B <BB#23>
2784B	BB#22: derived from LLVM BB %if.else
	    Live Ins: %X19
	    Predecessors according to CFG: BB#17
2816B		%vreg68<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg68
2832B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2864B		%X1<def> = ADDXri <fi#9>, 0, 0
2872B		%X0<def> = COPY %vreg68<kill>; GPR64:%vreg68
2880B		BL <ga:@fopen>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %X0<imp-def>
2896B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2912B		%vreg66<def> = COPY %X0; GPR64:%vreg66
2928B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2944B		STACKMAP 5, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#15>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack15](align=4) LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)
2960B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2976B		STRXui %vreg66<kill>, <fi#10>, 0; mem:ST8[FixedStack10] GPR64:%vreg66
	    Successors according to CFG: BB#23
> %X0<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X1<def> = ADDXri <fi#9>, 0, 0
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BL <ga:@fopen>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %X0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0
Deleting identity copy.
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 5, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#15>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack15](align=4) LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRXui %X0<kill>, <fi#10>, 0; mem:ST8[FixedStack10]
2992B	BB#23: derived from LLVM BB %if.end.31
	    Live Ins: %X19
	    Predecessors according to CFG: BB#22 BB#21
3008B		B <BB#25>
	    Successors according to CFG: BB#25
> B <BB#25>
3024B	BB#24: derived from LLVM BB %if.else.32
	    Live Ins: %X19
	    Predecessors according to CFG: BB#15
3056B		%vreg55<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg55
3072B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3104B		%X1<def> = ADDXri <fi#9>, 0, 0
3112B		%W0<def> = COPY %vreg55<kill>; GPR32:%vreg55
3120B		BL <ga:@fdopen>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use>, %X0<imp-def>
3136B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3152B		%vreg53<def> = COPY %X0; GPR64:%vreg53
3168B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3184B		STACKMAP 6, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#15>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack15](align=4) LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)
3200B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3216B		STRXui %vreg53<kill>, <fi#10>, 0; mem:ST8[FixedStack10] GPR64:%vreg53
	    Successors according to CFG: BB#25
> %W0<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X1<def> = ADDXri <fi#9>, 0, 0
> %W0<def> = COPY %W0<kill>
Deleting identity copy.
> BL <ga:@fdopen>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %W0<imp-use>, %X1<imp-use>, %X0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0
Deleting identity copy.
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 6, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#15>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack15](align=4) LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRXui %X0<kill>, <fi#10>, 0; mem:ST8[FixedStack10]
3232B	BB#25: derived from LLVM BB %if.end.35
	    Live Ins: %X19
	    Predecessors according to CFG: BB#24 BB#23
3248B		%vreg78<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg78
3264B		CBNZX %vreg78<kill>, <BB#27>; GPR64:%vreg78
	    Successors according to CFG: BB#27 BB#26
> %X8<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10]
> CBNZX %X8<kill>, <BB#27>
3280B	BB#26: derived from LLVM BB %if.then.38
	    Live Ins: %X19
	    Predecessors according to CFG: BB#25
3312B		STRXui %XZR, <fi#0>, 0; mem:ST8[FixedStack0]
3328B		B <BB#40>
	    Successors according to CFG: BB#40
> STRXui %XZR, <fi#0>, 0; mem:ST8[FixedStack0]
> B <BB#40>
3344B	BB#27: derived from LLVM BB %if.end.39
	    Live Ins: %X19
	    Predecessors according to CFG: BB#25
3360B		%vreg80<def> = LDRWui <fi#8>, 0; mem:LD4[FixedStack8] GPR32:%vreg80
3376B		CBZW %vreg80<kill>, <BB#33>; GPR32:%vreg80
	    Successors according to CFG: BB#33 BB#28
> %W8<def> = LDRWui <fi#8>, 0; mem:LD4[FixedStack8]
> CBZW %W8<kill>, <BB#33>
3392B	BB#28: derived from LLVM BB %if.then.41
	    Live Ins: %X19
	    Predecessors according to CFG: BB#27
3408B		%vreg95<def> = LDRWui <fi#7>, 0; mem:LD4[FixedStack7] GPR32common:%vreg95
3424B		%WZR<def> = SUBSWri %vreg95<kill>, 1, 0, %NZCV<imp-def>; GPR32common:%vreg95
3440B		Bcc 10, <BB#30>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#30 BB#29
> %W8<def> = LDRWui <fi#7>, 0; mem:LD4[FixedStack7]
> %WZR<def> = SUBSWri %W8<kill>, 1, 0, %NZCV<imp-def>
> Bcc 10, <BB#30>, %NZCV<imp-use,kill>
3456B	BB#29: derived from LLVM BB %if.then.44
	    Live Ins: %X19
	    Predecessors according to CFG: BB#28
3472B		%vreg96<def> = MOVi32imm 1; GPR32:%vreg96
3488B		STRWui %vreg96<kill>, <fi#7>, 0; mem:ST4[FixedStack7] GPR32:%vreg96
	    Successors according to CFG: BB#30
> %W8<def> = MOVi32imm 1
> STRWui %W8<kill>, <fi#7>, 0; mem:ST4[FixedStack7]
3504B	BB#30: derived from LLVM BB %if.end.45
	    Live Ins: %X19
	    Predecessors according to CFG: BB#28 BB#29
3520B		%vreg98<def> = LDRWui <fi#7>, 0; mem:LD4[FixedStack7] GPR32common:%vreg98
3536B		%WZR<def> = SUBSWri %vreg98<kill>, 9, 0, %NZCV<imp-def>; GPR32common:%vreg98
3552B		Bcc 13, <BB#32>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#32 BB#31
> %W8<def> = LDRWui <fi#7>, 0; mem:LD4[FixedStack7]
> %WZR<def> = SUBSWri %W8<kill>, 9, 0, %NZCV<imp-def>
> Bcc 13, <BB#32>, %NZCV<imp-use,kill>
3568B	BB#31: derived from LLVM BB %if.then.48
	    Live Ins: %X19
	    Predecessors according to CFG: BB#30
3584B		%vreg99<def> = MOVi32imm 9; GPR32:%vreg99
3600B		STRWui %vreg99<kill>, <fi#7>, 0; mem:ST4[FixedStack7] GPR32:%vreg99
	    Successors according to CFG: BB#32
> %W8<def> = MOVi32imm 9
> STRWui %W8<kill>, <fi#7>, 0; mem:ST4[FixedStack7]
3616B	BB#32: derived from LLVM BB %if.end.49
	    Live Ins: %X19
	    Predecessors according to CFG: BB#30 BB#31
3648B		%vreg110<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg110
3664B		%vreg109<def> = LDRWui <fi#7>, 0; mem:LD4[FixedStack7] GPR32:%vreg109
3680B		%vreg108<def> = LDRWui <fi#12>, 0; mem:LD4[FixedStack12] GPR32:%vreg108
3696B		%vreg107<def> = LDRWui <fi#13>, 0; mem:LD4[FixedStack13] GPR32:%vreg107
3712B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3728B		%X0<def> = ADDXri <fi#5>, 0, 0
3744B		%X1<def> = COPY %vreg110<kill>; GPR64:%vreg110
3760B		%W2<def> = COPY %vreg109<kill>; GPR32:%vreg109
3776B		%W3<def> = COPY %vreg108<kill>; GPR32:%vreg108
3792B		%W4<def> = COPY %vreg107<kill>; GPR32:%vreg107
3808B		BL <ga:@BZ2_bzWriteOpen>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %W2<imp-use>, %W3<imp-use>, %W4<imp-use>, %X0<imp-def>
3824B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3840B		%vreg106<def> = COPY %X0; GPR64:%vreg106
3856B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3872B		STACKMAP 7, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack0]
3888B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3904B		STRXui %vreg106<kill>, <fi#11>, 0; mem:ST8[FixedStack11] GPR64:%vreg106
3920B		B <BB#34>
	    Successors according to CFG: BB#34
> %X1<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10]
> %W2<def> = LDRWui <fi#7>, 0; mem:LD4[FixedStack7]
> %W3<def> = LDRWui <fi#12>, 0; mem:LD4[FixedStack12]
> %W4<def> = LDRWui <fi#13>, 0; mem:LD4[FixedStack13]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = ADDXri <fi#5>, 0, 0
> %X1<def> = COPY %X1<kill>
Deleting identity copy.
> %W2<def> = COPY %W2<kill>
Deleting identity copy.
> %W3<def> = COPY %W3<kill>
Deleting identity copy.
> %W4<def> = COPY %W4<kill>
Deleting identity copy.
> BL <ga:@BZ2_bzWriteOpen>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %W2<imp-use>, %W3<imp-use>, %W4<imp-use>, %X0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0
Deleting identity copy.
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 7, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack0]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRXui %X0<kill>, <fi#11>, 0; mem:ST8[FixedStack11]
> B <BB#34>
3936B	BB#33: derived from LLVM BB %if.else.51
	    Live Ins: %X19
	    Predecessors according to CFG: BB#27
3984B		%vreg93<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg93
4000B		%vreg92<def> = LDRWui <fi#12>, 0; mem:LD4[FixedStack12] GPR32:%vreg92
4016B		%vreg91<def> = LDRWui <fi#14>, 0; mem:LD4[FixedStack14] GPR32:%vreg91
4032B		%vreg89<def> = LDRWui <fi#15>, 0; mem:LD4[FixedStack15] GPR32:%vreg89
4048B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4064B		%X0<def> = ADDXri <fi#5>, 0, 0
4072B		%X4<def> = ADDXri <fi#6>, 0, 0
4080B		%X1<def> = COPY %vreg93<kill>; GPR64:%vreg93
4096B		%W2<def> = COPY %vreg92<kill>; GPR32:%vreg92
4112B		%W3<def> = COPY %vreg91<kill>; GPR32:%vreg91
4144B		%W5<def> = COPY %vreg89<kill>; GPR32:%vreg89
4160B		BL <ga:@BZ2_bzReadOpen>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %W2<imp-use>, %W3<imp-use>, %X4<imp-use>, %W5<imp-use>, %X0<imp-def>
4176B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4192B		%vreg88<def> = COPY %X0; GPR64:%vreg88
4208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4224B		STACKMAP 8, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack0]
4240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4256B		STRXui %vreg88<kill>, <fi#11>, 0; mem:ST8[FixedStack11] GPR64:%vreg88
	    Successors according to CFG: BB#34
> %X1<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10]
> %W2<def> = LDRWui <fi#12>, 0; mem:LD4[FixedStack12]
> %W3<def> = LDRWui <fi#14>, 0; mem:LD4[FixedStack14]
> %W5<def> = LDRWui <fi#15>, 0; mem:LD4[FixedStack15]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = ADDXri <fi#5>, 0, 0
> %X4<def> = ADDXri <fi#6>, 0, 0
> %X1<def> = COPY %X1<kill>
Deleting identity copy.
> %W2<def> = COPY %W2<kill>
Deleting identity copy.
> %W3<def> = COPY %W3<kill>
Deleting identity copy.
> %W5<def> = COPY %W5<kill>
Deleting identity copy.
> BL <ga:@BZ2_bzReadOpen>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %W2<imp-use>, %W3<imp-use>, %X4<imp-use>, %W5<imp-use>, %X0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0
Deleting identity copy.
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 8, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack0]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRXui %X0<kill>, <fi#11>, 0; mem:ST8[FixedStack11]
4272B	BB#34: derived from LLVM BB %if.end.54
	    Live Ins: %X19
	    Predecessors according to CFG: BB#33 BB#32
4288B		%vreg112<def> = LDRXui <fi#11>, 0; mem:LD8[FixedStack11] GPR64:%vreg112
4304B		CBNZX %vreg112<kill>, <BB#39>; GPR64:%vreg112
	    Successors according to CFG: BB#39 BB#35
> %X8<def> = LDRXui <fi#11>, 0; mem:LD8[FixedStack11]
> CBNZX %X8<kill>, <BB#39>
4320B	BB#35: derived from LLVM BB %if.then.57
	    Live Ins: %X19
	    Predecessors according to CFG: BB#34
4336B		%vreg117<def> = ADRP <ga:@stdin>[TF=1]; GPR64common:%vreg117
4352B		%vreg118<def> = ADDXri %vreg117<kill>, <ga:@stdin>[TF=34], 0; GPR64sp:%vreg118 GPR64common:%vreg117
4368B		%vreg120<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg120
4384B		%vreg119<def> = LDRXui %vreg118<kill>, 0; mem:LD8[@stdin] GPR64:%vreg119 GPR64sp:%vreg118
4400B		%XZR<def> = SUBSXrr %vreg120<kill>, %vreg119<kill>, %NZCV<imp-def>; GPR64:%vreg120,%vreg119
4416B		Bcc 0, <BB#38>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#38 BB#36
> %X8<def> = ADRP <ga:@stdin>[TF=1]
> %X8<def> = ADDXri %X8<kill>, <ga:@stdin>[TF=34], 0
> %X9<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10]
> %X8<def> = LDRXui %X8<kill>, 0; mem:LD8[@stdin]
> %XZR<def> = SUBSXrr %X9<kill>, %X8<kill>, %NZCV<imp-def>
> Bcc 0, <BB#38>, %NZCV<imp-use,kill>
4432B	BB#36: derived from LLVM BB %land.lhs.true
	    Live Ins: %X19
	    Predecessors according to CFG: BB#35
4448B		%vreg123<def> = ADRP <ga:@stdout>[TF=1]; GPR64common:%vreg123
4464B		%vreg124<def> = ADDXri %vreg123<kill>, <ga:@stdout>[TF=34], 0; GPR64sp:%vreg124 GPR64common:%vreg123
4480B		%vreg126<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg126
4496B		%vreg125<def> = LDRXui %vreg124<kill>, 0; mem:LD8[@stdout] GPR64:%vreg125 GPR64sp:%vreg124
4512B		%XZR<def> = SUBSXrr %vreg126<kill>, %vreg125<kill>, %NZCV<imp-def>; GPR64:%vreg126,%vreg125
4528B		Bcc 0, <BB#38>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#38 BB#37
> %X8<def> = ADRP <ga:@stdout>[TF=1]
> %X8<def> = ADDXri %X8<kill>, <ga:@stdout>[TF=34], 0
> %X9<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10]
> %X8<def> = LDRXui %X8<kill>, 0; mem:LD8[@stdout]
> %XZR<def> = SUBSXrr %X9<kill>, %X8<kill>, %NZCV<imp-def>
> Bcc 0, <BB#38>, %NZCV<imp-use,kill>
4544B	BB#37: derived from LLVM BB %if.then.62
	    Live Ins: %X19
	    Predecessors according to CFG: BB#36
4560B		%vreg129<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10] GPR64:%vreg129
4576B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4592B		%X0<def> = COPY %vreg129<kill>; GPR64:%vreg129
4608B		BL <ga:@fclose>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
4624B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4640B		%vreg128<def,dead> = COPY %W0; GPR32all:%vreg128
4656B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4672B		STACKMAP 9, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0]
4688B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#38
> %X0<def> = LDRXui <fi#10>, 0; mem:LD8[FixedStack10]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BL <ga:@fclose>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def,dead> = COPY %W0
Deleting identity copy.
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 9, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4704B	BB#38: derived from LLVM BB %if.end.64
	    Live Ins: %X19
	    Predecessors according to CFG: BB#35 BB#36 BB#37
4736B		STRXui %XZR, <fi#0>, 0; mem:ST8[FixedStack0]
4752B		B <BB#40>
	    Successors according to CFG: BB#40
> STRXui %XZR, <fi#0>, 0; mem:ST8[FixedStack0]
> B <BB#40>
4768B	BB#39: derived from LLVM BB %if.end.65
	    Live Ins: %X19
	    Predecessors according to CFG: BB#34
4784B		%vreg114<def> = LDRXui <fi#11>, 0; mem:LD8[FixedStack11] GPR64:%vreg114
4800B		STRXui %vreg114<kill>, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg114
	    Successors according to CFG: BB#40
> %X8<def> = LDRXui <fi#11>, 0; mem:LD8[FixedStack11]
> STRXui %X8<kill>, <fi#0>, 0; mem:ST8[FixedStack0]
4816B	BB#40: derived from LLVM BB %return
	    Live Ins: %X19
	    Predecessors according to CFG: BB#39 BB#38 BB#26 BB#1
4832B		%vreg171<def> = ADRP <ga:@bzopen_or_bzdopen>[TF=1]; GPR64common:%vreg171
4848B		%vreg173<def> = ADDXri %vreg171<kill>, <ga:@bzopen_or_bzdopen>[TF=34], 0; GPR64sp:%vreg173 GPR64common:%vreg171
4896B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4912B		%X0<def> = COPY %vreg173<kill>; GPR64sp:%vreg173
4928B		%X1<def> = COPY %vreg25<kill>; GPR64:%vreg25
4944B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
4960B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4976B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4992B		STACKMAP 10, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0]
5008B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5024B		%vreg170<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg170
5040B		%X0<def> = COPY %vreg170<kill>; GPR64:%vreg170
5056B		RET_ReallyLR %X0<imp-use>
> %X8<def> = ADRP <ga:@bzopen_or_bzdopen>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@bzopen_or_bzdopen>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19<kill>
> BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 10, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> RET_ReallyLR %X0<imp-use>
Computing live-in reg-units in ABI blocks.
0B	BB#0 W0#0 W1#0 W30#0
Created 3 new intervals.
********** INTERVALS **********
W30 [0B,16r:0)[208r,208d:2)[288e,288d:1)[464r,464d:3)[576e,576d:4)[672r,672d:5)[720e,720d:6)  0@0B-phi 1@288e 2@208r 3@464r 4@576e 5@672r 6@720e
W0 [0B,48r:0)[176r,208r:1)[400r,464r:3)[464r,496r:2)[640r,672r:4)[752r,768r:5)  0@0B-phi 1@176r 2@464r 3@400r 4@640r 5@752r
W1 [0B,32r:0)[192r,208r:2)[416r,464r:1)[656r,672r:3)  0@0B-phi 1@416r 2@192r 3@656r
%vreg0 [48r,64r:0)  0@48r
%vreg1 [64r,320r:0)  0@64r
%vreg2 [32r,80r:0)  0@32r
%vreg3 [80r,336r:0)  0@80r
%vreg5 [512r,528r:0)  0@512r
%vreg6 [528r,544r:0)  0@528r
%vreg7 [544r,640r:0)  0@544r
%vreg8 [608r,656r:0)  0@608r
%vreg9 [16r,608r:0)  0@16r
%vreg10 [240r,400r:0)  0@240r
%vreg13 [256r,448r:0)  0@256r
%vreg14 [496r,752r:0)  0@496r
%vreg15 [368r,432r:0)  0@368r
%vreg16 [352r,416r:0)  0@352r
%vreg17 [96r,112r:0)  0@96r
%vreg18 [112r,128r:0)  0@112r
%vreg19 [128r,176r:0)  0@128r
%vreg20 [144r,192r:0)  0@144r
RegMasks: 208r 464r 672r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzdopen: Post SSA
Frame Objects:
  fi#0: size=4, align=4, at location [SP]
  fi#1: size=8, align=8, at location [SP]
Function Live Ins: %W0 in %vreg0, %X1 in %vreg2, %LR in %vreg9

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %W0 %X1 %LR
16B		%vreg9<def> = COPY %LR; GPR64:%vreg9
32B		%vreg2<def> = COPY %X1; GPR64:%vreg2
48B		%vreg0<def> = COPY %W0; GPR32:%vreg0
64B		%vreg1<def> = COPY %vreg0; GPR32:%vreg1,%vreg0
80B		%vreg3<def> = COPY %vreg2; GPR64:%vreg3,%vreg2
96B		%vreg17<def> = ADRP <ga:@BZ2_bzdopen>[TF=1]; GPR64common:%vreg17
112B		%vreg18<def> = ADDXri %vreg17, <ga:@BZ2_bzdopen>[TF=34], 0; GPR64sp:%vreg18 GPR64common:%vreg17
128B		%vreg19<def> = COPY %vreg18; GPR64all:%vreg19 GPR64sp:%vreg18
144B		%vreg20<def> = COPY %vreg9; GPR64all:%vreg20 GPR64:%vreg9
160B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
176B		%X0<def> = COPY %vreg19; GPR64all:%vreg19
192B		%X1<def> = COPY %vreg20; GPR64all:%vreg20
208B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
224B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
240B		%vreg10<def> = COPY %XZR; GPR64:%vreg10
256B		%vreg13<def> = MOVi32imm 1; GPR32:%vreg13
272B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
288B		STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, %vreg3, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack1] GPR32:%vreg1 GPR64:%vreg3
304B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
320B		STRWui %vreg1, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg1
336B		STRXui %vreg3, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg3
352B		%vreg16<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0] GPR32:%vreg16
368B		%vreg15<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg15
384B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
400B		%X0<def> = COPY %vreg10; GPR64:%vreg10
416B		%W1<def> = COPY %vreg16; GPR32:%vreg16
432B		%X2<def> = COPY %vreg15; GPR64:%vreg15
448B		%W3<def> = COPY %vreg13; GPR32:%vreg13
464B		BL <ga:@bzopen_or_bzdopen>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %X2<imp-use,kill>, %W3<imp-use,kill>, %X0<imp-def>
480B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
496B		%vreg14<def> = COPY %X0; GPR64all:%vreg14
512B		%vreg5<def> = ADRP <ga:@BZ2_bzdopen>[TF=1]; GPR64common:%vreg5
528B		%vreg6<def> = ADDXri %vreg5, <ga:@BZ2_bzdopen>[TF=34], 0; GPR64sp:%vreg6 GPR64common:%vreg5
544B		%vreg7<def> = COPY %vreg6; GPR64all:%vreg7 GPR64sp:%vreg6
560B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
576B		STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...
592B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
608B		%vreg8<def> = COPY %vreg9; GPR64all:%vreg8 GPR64:%vreg9
624B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
640B		%X0<def> = COPY %vreg7; GPR64all:%vreg7
656B		%X1<def> = COPY %vreg8; GPR64all:%vreg8
672B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
688B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
704B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
720B		STACKMAP 2, 0, %vreg14, %LR<earlyclobber,imp-def,dead>, ...; GPR64all:%vreg14
736B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
752B		%X0<def> = COPY %vreg14; GPR64all:%vreg14
768B		RET_ReallyLR %X0<imp-use>

# End machine code for function BZ2_bzdopen.

********** SIMPLE REGISTER COALESCING **********
********** Function: BZ2_bzdopen
********** JOINING INTERVALS ***********
entry:
16B	%vreg9<def> = COPY %LR; GPR64:%vreg9
	Considering merging %vreg9 with %LR
	Can only merge into reserved registers.
32B	%vreg2<def> = COPY %X1; GPR64:%vreg2
	Considering merging %vreg2 with %X1
	Can only merge into reserved registers.
48B	%vreg0<def> = COPY %W0; GPR32:%vreg0
	Considering merging %vreg0 with %W0
	Can only merge into reserved registers.
176B	%X0<def> = COPY %vreg19; GPR64all:%vreg19
	Considering merging %vreg19 with %X0
	Can only merge into reserved registers.
192B	%X1<def> = COPY %vreg20; GPR64all:%vreg20
	Considering merging %vreg20 with %X1
	Can only merge into reserved registers.
240B	%vreg10<def> = COPY %XZR; GPR64:%vreg10
	Considering merging %vreg10 with %XZR
		RHS = %vreg10 [240r,400r:0)  0@240r
		updated: 400B	%X0<def> = COPY %XZR
	Success: %vreg10 -> %XZR
	Result = %XZR
400B	%X0<def> = COPY %XZR
	Not coalescable.
416B	%W1<def> = COPY %vreg16; GPR32:%vreg16
	Considering merging %vreg16 with %W1
	Can only merge into reserved registers.
432B	%X2<def> = COPY %vreg15; GPR64:%vreg15
	Considering merging %vreg15 with %X2
	Can only merge into reserved registers.
448B	%W3<def> = COPY %vreg13; GPR32:%vreg13
	Considering merging %vreg13 with %W3
	Can only merge into reserved registers.
Remat: %W3<def> = MOVi32imm 1
Shrink: %vreg13 [256r,448r:0)  0@256r
All defs dead: 256r	%vreg13<def,dead> = MOVi32imm 1; GPR32:%vreg13
Shrunk: %vreg13 [256r,256d:0)  0@256r
Deleting dead def 256r	%vreg13<def,dead> = MOVi32imm 1; GPR32:%vreg13
496B	%vreg14<def> = COPY %X0; GPR64all:%vreg14
	Considering merging %vreg14 with %X0
	Can only merge into reserved registers.
640B	%X0<def> = COPY %vreg7; GPR64all:%vreg7
	Considering merging %vreg7 with %X0
	Can only merge into reserved registers.
656B	%X1<def> = COPY %vreg8; GPR64all:%vreg8
	Considering merging %vreg8 with %X1
	Can only merge into reserved registers.
752B	%X0<def> = COPY %vreg14; GPR64all:%vreg14
	Considering merging %vreg14 with %X0
	Can only merge into reserved registers.
64B	%vreg1<def> = COPY %vreg0; GPR32:%vreg1,%vreg0
	Considering merging to GPR32 with %vreg0 in %vreg1
		RHS = %vreg0 [48r,64r:0)  0@48r
		LHS = %vreg1 [64r,320r:0)  0@64r
		merge %vreg1:0@64r into %vreg0:0@48r --> @48r
		erased:	64r	%vreg1<def> = COPY %vreg0; GPR32:%vreg1,%vreg0
		updated: 48B	%vreg1<def> = COPY %W0; GPR32:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [48r,320r:0)  0@48r
80B	%vreg3<def> = COPY %vreg2; GPR64:%vreg3,%vreg2
	Considering merging to GPR64 with %vreg2 in %vreg3
		RHS = %vreg2 [32r,80r:0)  0@32r
		LHS = %vreg3 [80r,336r:0)  0@80r
		merge %vreg3:0@80r into %vreg2:0@32r --> @32r
		erased:	80r	%vreg3<def> = COPY %vreg2; GPR64:%vreg3,%vreg2
		updated: 32B	%vreg3<def> = COPY %X1; GPR64:%vreg3
	Success: %vreg2 -> %vreg3
	Result = %vreg3 [32r,336r:0)  0@32r
128B	%vreg19<def> = COPY %vreg18; GPR64all:%vreg19 GPR64sp:%vreg18
	Considering merging to GPR64sp with %vreg18 in %vreg19
		RHS = %vreg18 [112r,128r:0)  0@112r
		LHS = %vreg19 [128r,176r:0)  0@128r
		merge %vreg19:0@128r into %vreg18:0@112r --> @112r
		erased:	128r	%vreg19<def> = COPY %vreg18; GPR64all:%vreg19 GPR64sp:%vreg18
		updated: 112B	%vreg19<def> = ADDXri %vreg17, <ga:@BZ2_bzdopen>[TF=34], 0; GPR64sp:%vreg19 GPR64common:%vreg17
	Success: %vreg18 -> %vreg19
	Result = %vreg19 [112r,176r:0)  0@112r
144B	%vreg20<def> = COPY %vreg9; GPR64all:%vreg20 GPR64:%vreg9
	Considering merging to GPR64 with %vreg9 in %vreg20
		RHS = %vreg9 [16r,608r:0)  0@16r
		LHS = %vreg20 [144r,192r:0)  0@144r
		merge %vreg20:0@144r into %vreg9:0@16r --> @16r
		erased:	144r	%vreg20<def> = COPY %vreg9; GPR64all:%vreg20 GPR64:%vreg9
		updated: 16B	%vreg20<def> = COPY %LR; GPR64:%vreg20
		updated: 608B	%vreg8<def> = COPY %vreg20; GPR64all:%vreg8 GPR64:%vreg20
	Success: %vreg9 -> %vreg20
	Result = %vreg20 [16r,608r:0)  0@16r
544B	%vreg7<def> = COPY %vreg6; GPR64all:%vreg7 GPR64sp:%vreg6
	Considering merging to GPR64sp with %vreg6 in %vreg7
		RHS = %vreg6 [528r,544r:0)  0@528r
		LHS = %vreg7 [544r,640r:0)  0@544r
		merge %vreg7:0@544r into %vreg6:0@528r --> @528r
		erased:	544r	%vreg7<def> = COPY %vreg6; GPR64all:%vreg7 GPR64sp:%vreg6
		updated: 528B	%vreg7<def> = ADDXri %vreg5, <ga:@BZ2_bzdopen>[TF=34], 0; GPR64sp:%vreg7 GPR64common:%vreg5
	Success: %vreg6 -> %vreg7
	Result = %vreg7 [528r,640r:0)  0@528r
608B	%vreg8<def> = COPY %vreg20; GPR64all:%vreg8 GPR64:%vreg20
	Considering merging to GPR64 with %vreg20 in %vreg8
		RHS = %vreg20 [16r,608r:0)  0@16r
		LHS = %vreg8 [608r,656r:0)  0@608r
		merge %vreg8:0@608r into %vreg20:0@16r --> @16r
		erased:	608r	%vreg8<def> = COPY %vreg20; GPR64all:%vreg8 GPR64:%vreg20
		updated: 16B	%vreg8<def> = COPY %LR; GPR64:%vreg8
		updated: 192B	%X1<def> = COPY %vreg8; GPR64:%vreg8
	Success: %vreg20 -> %vreg8
	Result = %vreg8 [16r,656r:0)  0@16r
176B	%X0<def> = COPY %vreg19; GPR64sp:%vreg19
	Considering merging %vreg19 with %X0
	Can only merge into reserved registers.
192B	%X1<def> = COPY %vreg8; GPR64:%vreg8
	Considering merging %vreg8 with %X1
	Can only merge into reserved registers.
640B	%X0<def> = COPY %vreg7; GPR64sp:%vreg7
	Considering merging %vreg7 with %X0
	Can only merge into reserved registers.
656B	%X1<def> = COPY %vreg8; GPR64:%vreg8
	Considering merging %vreg8 with %X1
	Can only merge into reserved registers.
752B	%X0<def> = COPY %vreg14; GPR64all:%vreg14
	Considering merging %vreg14 with %X0
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
W30 [0B,16r:0)[208r,208d:2)[288e,288d:1)[464r,464d:3)[576e,576d:4)[672r,672d:5)[720e,720d:6)  0@0B-phi 1@288e 2@208r 3@464r 4@576e 5@672r 6@720e
WZR EMPTY
W0 [0B,48r:0)[176r,208r:1)[400r,464r:3)[464r,496r:2)[640r,672r:4)[752r,768r:5)  0@0B-phi 1@176r 2@464r 3@400r 4@640r 5@752r
W1 [0B,32r:0)[192r,208r:2)[416r,464r:1)[656r,672r:3)  0@0B-phi 1@416r 2@192r 3@656r
%vreg1 [48r,320r:0)  0@48r
%vreg3 [32r,336r:0)  0@32r
%vreg5 [512r,528r:0)  0@512r
%vreg7 [528r,640r:0)  0@528r
%vreg8 [16r,656r:0)  0@16r
%vreg14 [496r,752r:0)  0@496r
%vreg15 [368r,432r:0)  0@368r
%vreg16 [352r,416r:0)  0@352r
%vreg17 [96r,112r:0)  0@96r
%vreg19 [112r,176r:0)  0@112r
RegMasks: 208r 464r 672r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzdopen: Post SSA
Frame Objects:
  fi#0: size=4, align=4, at location [SP]
  fi#1: size=8, align=8, at location [SP]
Function Live Ins: %W0 in %vreg0, %X1 in %vreg2, %LR in %vreg9

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %W0 %X1 %LR
16B		%vreg8<def> = COPY %LR; GPR64:%vreg8
32B		%vreg3<def> = COPY %X1; GPR64:%vreg3
48B		%vreg1<def> = COPY %W0; GPR32:%vreg1
96B		%vreg17<def> = ADRP <ga:@BZ2_bzdopen>[TF=1]; GPR64common:%vreg17
112B		%vreg19<def> = ADDXri %vreg17, <ga:@BZ2_bzdopen>[TF=34], 0; GPR64sp:%vreg19 GPR64common:%vreg17
160B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
176B		%X0<def> = COPY %vreg19; GPR64sp:%vreg19
192B		%X1<def> = COPY %vreg8; GPR64:%vreg8
208B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
224B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
272B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
288B		STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, %vreg3, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack1] GPR32:%vreg1 GPR64:%vreg3
304B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
320B		STRWui %vreg1, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg1
336B		STRXui %vreg3, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg3
352B		%vreg16<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0] GPR32:%vreg16
368B		%vreg15<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg15
384B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
400B		%X0<def> = COPY %XZR
416B		%W1<def> = COPY %vreg16; GPR32:%vreg16
432B		%X2<def> = COPY %vreg15; GPR64:%vreg15
448B		%W3<def> = MOVi32imm 1
464B		BL <ga:@bzopen_or_bzdopen>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %X2<imp-use,kill>, %W3<imp-use,kill>, %X0<imp-def>
480B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
496B		%vreg14<def> = COPY %X0; GPR64all:%vreg14
512B		%vreg5<def> = ADRP <ga:@BZ2_bzdopen>[TF=1]; GPR64common:%vreg5
528B		%vreg7<def> = ADDXri %vreg5, <ga:@BZ2_bzdopen>[TF=34], 0; GPR64sp:%vreg7 GPR64common:%vreg5
560B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
576B		STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...
592B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
624B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
640B		%X0<def> = COPY %vreg7; GPR64sp:%vreg7
656B		%X1<def> = COPY %vreg8; GPR64:%vreg8
672B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
688B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
704B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
720B		STACKMAP 2, 0, %vreg14, %LR<earlyclobber,imp-def,dead>, ...; GPR64all:%vreg14
736B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
752B		%X0<def> = COPY %vreg14; GPR64all:%vreg14
768B		RET_ReallyLR %X0<imp-use>

# End machine code for function BZ2_bzdopen.

handleMove 448B -> 408B: %W3<def> = MOVi32imm 1
     W3:	[408r,464r:0)  0@408r
        -->	[408r,464r:0)  0@408r
********** GREEDY REGISTER ALLOCATION **********
********** Function: BZ2_bzdopen
********** INTERVALS **********
W30 [0B,16r:0)[208r,208d:2)[288e,288d:1)[464r,464d:3)[576e,576d:4)[672r,672d:5)[720e,720d:6)  0@0B-phi 1@288e 2@208r 3@464r 4@576e 5@672r 6@720e
WZR EMPTY
W0 [0B,48r:0)[176r,208r:1)[400r,464r:3)[464r,496r:2)[640r,672r:4)[752r,768r:5)  0@0B-phi 1@176r 2@464r 3@400r 4@640r 5@752r
W1 [0B,32r:0)[192r,208r:2)[416r,464r:1)[656r,672r:3)  0@0B-phi 1@416r 2@192r 3@656r
W3 [408r,464r:0)  0@408r
%vreg1 [48r,320r:0)  0@48r
%vreg3 [32r,336r:0)  0@32r
%vreg5 [512r,528r:0)  0@512r
%vreg7 [528r,640r:0)  0@528r
%vreg8 [16r,656r:0)  0@16r
%vreg14 [496r,752r:0)  0@496r
%vreg15 [368r,432r:0)  0@368r
%vreg16 [352r,416r:0)  0@352r
%vreg17 [96r,112r:0)  0@96r
%vreg19 [112r,176r:0)  0@112r
RegMasks: 208r 464r 672r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzdopen: Post SSA
Frame Objects:
  fi#0: size=4, align=4, at location [SP]
  fi#1: size=8, align=8, at location [SP]
Function Live Ins: %W0 in %vreg0, %X1 in %vreg2, %LR in %vreg9

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %W0 %X1 %LR
16B		%vreg8<def> = COPY %LR; GPR64:%vreg8
32B		%vreg3<def> = COPY %X1; GPR64:%vreg3
48B		%vreg1<def> = COPY %W0; GPR32:%vreg1
96B		%vreg17<def> = ADRP <ga:@BZ2_bzdopen>[TF=1]; GPR64common:%vreg17
112B		%vreg19<def> = ADDXri %vreg17, <ga:@BZ2_bzdopen>[TF=34], 0; GPR64sp:%vreg19 GPR64common:%vreg17
160B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
176B		%X0<def> = COPY %vreg19; GPR64sp:%vreg19
192B		%X1<def> = COPY %vreg8; GPR64:%vreg8
208B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
224B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
272B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
288B		STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, %vreg3, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack1] GPR32:%vreg1 GPR64:%vreg3
304B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
320B		STRWui %vreg1, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg1
336B		STRXui %vreg3, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg3
352B		%vreg16<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0] GPR32:%vreg16
368B		%vreg15<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg15
384B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
400B		%X0<def> = COPY %XZR
408B		%W3<def> = MOVi32imm 1
416B		%W1<def> = COPY %vreg16; GPR32:%vreg16
432B		%X2<def> = COPY %vreg15; GPR64:%vreg15
464B		BL <ga:@bzopen_or_bzdopen>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %X2<imp-use,kill>, %W3<imp-use>, %X0<imp-def>
480B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
496B		%vreg14<def> = COPY %X0; GPR64all:%vreg14
512B		%vreg5<def> = ADRP <ga:@BZ2_bzdopen>[TF=1]; GPR64common:%vreg5
528B		%vreg7<def> = ADDXri %vreg5, <ga:@BZ2_bzdopen>[TF=34], 0; GPR64sp:%vreg7 GPR64common:%vreg5
560B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
576B		STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...
592B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
624B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
640B		%X0<def> = COPY %vreg7; GPR64sp:%vreg7
656B		%X1<def> = COPY %vreg8; GPR64:%vreg8
672B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
688B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
704B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
720B		STACKMAP 2, 0, %vreg14, %LR<earlyclobber,imp-def,dead>, ...; GPR64all:%vreg14
736B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
752B		%X0<def> = COPY %vreg14; GPR64all:%vreg14
768B		RET_ReallyLR %X0<imp-use>

# End machine code for function BZ2_bzdopen.


selectOrSplit GPR64:%vreg8 [16r,656r:0)  0@16r w=2.913462e-03
hints: %X1
missed hint %X1
assigning %vreg8 to %X19: W19 [16r,656r:0)  0@16r

selectOrSplit GPR64:%vreg3 [32r,336r:0)  0@32r w=4.303977e-03
hints: %X1
missed hint %X1
assigning %vreg3 to %X20: W20 [32r,336r:0)  0@32r

selectOrSplit GPR32:%vreg1 [48r,320r:0)  0@48r w=4.508928e-03
hints: %W0
missed hint %W0
assigning %vreg1 to %W21: W21 [48r,320r:0)  0@48r

selectOrSplit GPR64sp:%vreg19 [112r,176r:0)  0@112r w=4.353448e-03
hints: %X0
assigning %vreg19 to %X0: W0 [112r,176r:0)  0@112r

selectOrSplit GPR32:%vreg16 [352r,416r:0)  0@352r w=4.353448e-03
hints: %W1
assigning %vreg16 to %W1: W1 [352r,416r:0)  0@352r

selectOrSplit GPR64:%vreg15 [368r,432r:0)  0@368r w=4.353448e-03
hints: %X2
assigning %vreg15 to %X2: W2 [368r,432r:0)  0@368r

selectOrSplit GPR64all:%vreg14 [496r,752r:0)  0@496r w=4.618902e-03
hints: %X0
missed hint %X0
assigning %vreg14 to %X20: W20 [496r,752r:0)  0@496r

selectOrSplit GPR64sp:%vreg7 [528r,640r:0)  0@528r w=3.945312e-03
hints: %X0
assigning %vreg7 to %X0: W0 [528r,640r:0)  0@528r

selectOrSplit GPR64common:%vreg17 [96r,112r:0)  0@96r w=inf
assigning %vreg17 to %X8: W8 [96r,112r:0)  0@96r

selectOrSplit GPR64common:%vreg5 [512r,528r:0)  0@512r w=inf
assigning %vreg5 to %X8: W8 [512r,528r:0)  0@512r

********** STACK TRANSFORMATION METADATA **********
********** Function: BZ2_bzdopen
********** REGISTER MAP **********
[%vreg1 -> %W21] GPR32
[%vreg3 -> %X20] GPR64
[%vreg5 -> %X8] GPR64common
[%vreg7 -> %X0] GPR64sp
[%vreg8 -> %X19] GPR64
[%vreg14 -> %X20] GPR64all
[%vreg15 -> %X2] GPR64
[%vreg16 -> %W1] GPR32
[%vreg17 -> %X8] GPR64common
[%vreg19 -> %X0] GPR64sp


Stackmap 0:
  STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, %vreg3, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack1] GPR32:%vreg1 GPR64:%vreg3

i32 %fd: in register %W21 (vreg 1)
i32* %fd.addr: in stack slot 0 (size: 4)
i8* %mode: in register %X20 (vreg 3)
i8** %mode.addr: in stack slot 1 (size: 8)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...


Duplicate operand locations:


Stackmap 2:
  STACKMAP 2, 0, %vreg14, %LR<earlyclobber,imp-def,dead>, ...; GPR64all:%vreg14

i8* %call: in register %X20 (vreg 14)

Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, %vreg3, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack1] GPR32:%vreg1 GPR64:%vreg3
  -> Call instruction SlotIndex 208B, searching vregs 0 -> 21 and stack slots 0 -> 2
    + vreg8 is live in register but not in stackmap
      Defining instruction: %vreg8<def> = COPY %LR; GPR64:%vreg8
      Value: generated value, 1 instruction(s)

  STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...
  -> Call instruction SlotIndex 464B, searching vregs 0 -> 21 and stack slots 0 -> 2
    + vreg8 is live in register but not in stackmap
      Defining instruction: %vreg8<def> = COPY %LR; GPR64:%vreg8
      Value: generated value, 1 instruction(s)

  STACKMAP 2, 0, %vreg14, %LR<earlyclobber,imp-def,dead>, ...; GPR64all:%vreg14
  -> Call instruction SlotIndex 672B, searching vregs 0 -> 21 and stack slots 0 -> 2

********** REWRITE VIRTUAL REGISTERS **********
********** Function: BZ2_bzdopen
********** REGISTER MAP **********
[%vreg1 -> %W21] GPR32
[%vreg3 -> %X20] GPR64
[%vreg5 -> %X8] GPR64common
[%vreg7 -> %X0] GPR64sp
[%vreg8 -> %X19] GPR64
[%vreg14 -> %X20] GPR64all
[%vreg15 -> %X2] GPR64
[%vreg16 -> %W1] GPR32
[%vreg17 -> %X8] GPR64common
[%vreg19 -> %X0] GPR64sp

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %LR %W0 %X1
16B		%vreg8<def> = COPY %LR; GPR64:%vreg8
32B		%vreg3<def> = COPY %X1; GPR64:%vreg3
48B		%vreg1<def> = COPY %W0; GPR32:%vreg1
96B		%vreg17<def> = ADRP <ga:@BZ2_bzdopen>[TF=1]; GPR64common:%vreg17
112B		%vreg19<def> = ADDXri %vreg17<kill>, <ga:@BZ2_bzdopen>[TF=34], 0; GPR64sp:%vreg19 GPR64common:%vreg17
160B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
176B		%X0<def> = COPY %vreg19<kill>; GPR64sp:%vreg19
192B		%X1<def> = COPY %vreg8; GPR64:%vreg8
208B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
224B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
272B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
288B		STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, %vreg3, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack1] GPR32:%vreg1 GPR64:%vreg3
304B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
320B		STRWui %vreg1<kill>, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg1
336B		STRXui %vreg3<kill>, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg3
352B		%vreg16<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0] GPR32:%vreg16
368B		%vreg15<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg15
384B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
400B		%X0<def> = COPY %XZR
408B		%W3<def> = MOVi32imm 1
416B		%W1<def> = COPY %vreg16<kill>; GPR32:%vreg16
432B		%X2<def> = COPY %vreg15<kill>; GPR64:%vreg15
464B		BL <ga:@bzopen_or_bzdopen>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %X2<imp-use>, %W3<imp-use>, %X0<imp-def>
480B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
496B		%vreg14<def> = COPY %X0; GPR64all:%vreg14
512B		%vreg5<def> = ADRP <ga:@BZ2_bzdopen>[TF=1]; GPR64common:%vreg5
528B		%vreg7<def> = ADDXri %vreg5<kill>, <ga:@BZ2_bzdopen>[TF=34], 0; GPR64sp:%vreg7 GPR64common:%vreg5
560B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
576B		STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...
592B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
624B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
640B		%X0<def> = COPY %vreg7<kill>; GPR64sp:%vreg7
656B		%X1<def> = COPY %vreg8<kill>; GPR64:%vreg8
672B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
688B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
704B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
720B		STACKMAP 2, 0, %vreg14, %LR<earlyclobber,imp-def,dead>, ...; GPR64all:%vreg14
736B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
752B		%X0<def> = COPY %vreg14<kill>; GPR64all:%vreg14
768B		RET_ReallyLR %X0<imp-use>
> %X19<def> = COPY %LR
> %X20<def> = COPY %X1
> %W21<def> = COPY %W0
> %X8<def> = ADRP <ga:@BZ2_bzdopen>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@BZ2_bzdopen>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19
> BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 0, 0, %W21, 0, <fi#0>, 0, %X20, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack1]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRWui %W21<kill>, <fi#0>, 0; mem:ST4[FixedStack0]
> STRXui %X20<kill>, <fi#1>, 0; mem:ST8[FixedStack1]
> %W1<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0]
> %X2<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %XZR
> %W3<def> = MOVi32imm 1
> %W1<def> = COPY %W1<kill>
Deleting identity copy.
> %X2<def> = COPY %X2<kill>
Deleting identity copy.
> BL <ga:@bzopen_or_bzdopen>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W1<imp-use>, %X2<imp-use>, %W3<imp-use>, %X0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X20<def> = COPY %X0
> %X8<def> = ADRP <ga:@BZ2_bzdopen>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@BZ2_bzdopen>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19<kill>
> BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 2, 0, %X20, %LR<earlyclobber,imp-def,dead>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X20<kill>
> RET_ReallyLR %X0<imp-use>
Computing live-in reg-units in ABI blocks.
0B	BB#0 W0#0 W1#0 W2#0 W30#0
Created 4 new intervals.
********** INTERVALS **********
W30 [0B,16r:0)[240r,240d:6)[288e,288d:3)[640r,640d:5)[704e,704d:2)[1088r,1088d:4)[1136e,1136d:1)  0@0B-phi 1@1136e 2@704e 3@288e 4@1088r 5@640r 6@240r
W0 [0B,64r:0)[208r,240r:5)[576r,640r:4)[640r,672r:2)[1056r,1088r:3)[1184r,1200r:1)  0@0B-phi 1@1184r 2@640r 3@1056r 4@576r 5@208r
W1 [0B,48r:0)[224r,240r:3)[592r,640r:2)[1072r,1088r:1)  0@0B-phi 1@1072r 2@592r 3@224r
W2 [0B,32r:0)[608r,640r:1)  0@0B-phi 1@608r
%vreg0 [64r,80r:0)  0@64r
%vreg1 [80r,320r:0)  0@80r
%vreg2 [48r,96r:0)  0@48r
%vreg3 [96r,336r:0)  0@96r
%vreg4 [32r,112r:0)  0@32r
%vreg5 [112r,352r:0)  0@112r
%vreg8 [384r,400r:0)  0@384r
%vreg9 [368r,384r:0)  0@368r
%vreg10 [128r,144r:0)  0@128r
%vreg11 [144r,160r:0)  0@144r
%vreg12 [160r,208r:0)  0@160r
%vreg13 [176r,224r:0)  0@176r
%vreg14 [16r,1024r:0)  0@16r
%vreg16 [752r,768r:0)  0@752r
%vreg18 [496r,576r:0)  0@496r
%vreg22 [672r,736r:0)  0@672r
%vreg23 [544r,624r:0)  0@544r
%vreg24 [528r,608r:0)  0@528r
%vreg25 [512r,592r:0)  0@512r
%vreg27 [800r,816r:0)  0@800r
%vreg28 [928r,944r:0)  0@928r
%vreg30 [864r,880r:0)  0@864r
%vreg32 [1168r,1184r:0)  0@1168r
%vreg33 [976r,992r:0)  0@976r
%vreg34 [992r,1008r:0)  0@992r
%vreg35 [1008r,1056r:0)  0@1008r
%vreg36 [1024r,1072r:0)  0@1024r
RegMasks: 240r 640r 1088r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzread: Post SSA
Frame Objects:
  fi#0: size=4, align=4, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=8, align=8, at location [SP]
  fi#3: size=4, align=4, at location [SP]
  fi#4: size=4, align=4, at location [SP]
  fi#5: size=4, align=4, at location [SP]
Function Live Ins: %X0 in %vreg0, %X1 in %vreg2, %W2 in %vreg4, %LR in %vreg14

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %X1 %W2 %LR
16B		%vreg14<def> = COPY %LR; GPR64:%vreg14
32B		%vreg4<def> = COPY %W2; GPR32:%vreg4
48B		%vreg2<def> = COPY %X1; GPR64:%vreg2
64B		%vreg0<def> = COPY %X0; GPR64:%vreg0
80B		%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
96B		%vreg3<def> = COPY %vreg2; GPR64:%vreg3,%vreg2
112B		%vreg5<def> = COPY %vreg4; GPR32:%vreg5,%vreg4
128B		%vreg10<def> = ADRP <ga:@BZ2_bzread>[TF=1]; GPR64common:%vreg10
144B		%vreg11<def> = ADDXri %vreg10, <ga:@BZ2_bzread>[TF=34], 0; GPR64sp:%vreg11 GPR64common:%vreg10
160B		%vreg12<def> = COPY %vreg11; GPR64all:%vreg12 GPR64sp:%vreg11
176B		%vreg13<def> = COPY %vreg14; GPR64all:%vreg13 GPR64:%vreg14
192B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
208B		%X0<def> = COPY %vreg12; GPR64all:%vreg12
224B		%X1<def> = COPY %vreg13; GPR64all:%vreg13
240B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
256B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
272B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
288B		STACKMAP 0, 0, %vreg1, 0, <fi#1>, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#4>, 0, %vreg5, 0, <fi#3>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack4](align=4) LD8[FixedStack3](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4) GPR64:%vreg1,%vreg3 GPR32:%vreg5
304B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
320B		STRXui %vreg1, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg1
336B		STRXui %vreg3, <fi#2>, 0; mem:ST8[FixedStack2] GPR64:%vreg3
352B		STRWui %vreg5, <fi#3>, 0; mem:ST4[FixedStack3] GPR32:%vreg5
368B		%vreg9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg9
384B		%vreg8<def> = LDRWui %vreg9, 1274; mem:LD4[%lastErr] GPR32common:%vreg8 GPR64common:%vreg9
400B		%WZR<def> = SUBSWri %vreg8, 4, 0, %NZCV<imp-def>; GPR32common:%vreg8
416B		Bcc 1, <BB#2>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

432B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
448B		STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
464B		B <BB#6>
	    Successors according to CFG: BB#6

480B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0
496B		%vreg18<def> = ADDXri <fi#4>, 0, 0; GPR64sp:%vreg18
512B		%vreg25<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg25
528B		%vreg24<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg24
544B		%vreg23<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg23
560B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
576B		%X0<def> = COPY %vreg18; GPR64sp:%vreg18
592B		%X1<def> = COPY %vreg25; GPR64:%vreg25
608B		%X2<def> = COPY %vreg24; GPR64:%vreg24
624B		%W3<def> = COPY %vreg23; GPR32:%vreg23
640B		BL <ga:@BZ2_bzRead>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %X2<imp-use>, %W3<imp-use,kill>, %W0<imp-def>
656B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
672B		%vreg22<def> = COPY %W0; GPR32:%vreg22
688B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
704B		STACKMAP 1, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4)
720B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
736B		STRWui %vreg22, <fi#5>, 0; mem:ST4[FixedStack5] GPR32:%vreg22
752B		%vreg16<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg16
768B		CBZW %vreg16, <BB#4>; GPR32:%vreg16
	    Successors according to CFG: BB#4 BB#3

784B	BB#3: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#2
800B		%vreg27<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32common:%vreg27
816B		%WZR<def> = SUBSWri %vreg27, 4, 0, %NZCV<imp-def>; GPR32common:%vreg27
832B		Bcc 1, <BB#5>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#5 BB#4

848B	BB#4: derived from LLVM BB %if.then.3
	    Predecessors according to CFG: BB#2 BB#3
864B		%vreg30<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32:%vreg30
880B		STRWui %vreg30, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg30
896B		B <BB#6>
	    Successors according to CFG: BB#6

912B	BB#5: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#3
928B		%vreg28<def> = MOVi32imm 4294967295; GPR32:%vreg28
944B		STRWui %vreg28, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg28
	    Successors according to CFG: BB#6

960B	BB#6: derived from LLVM BB %return
	    Predecessors according to CFG: BB#5 BB#4 BB#1
976B		%vreg33<def> = ADRP <ga:@BZ2_bzread>[TF=1]; GPR64common:%vreg33
992B		%vreg34<def> = ADDXri %vreg33, <ga:@BZ2_bzread>[TF=34], 0; GPR64sp:%vreg34 GPR64common:%vreg33
1008B		%vreg35<def> = COPY %vreg34; GPR64all:%vreg35 GPR64sp:%vreg34
1024B		%vreg36<def> = COPY %vreg14; GPR64all:%vreg36 GPR64:%vreg14
1040B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1056B		%X0<def> = COPY %vreg35; GPR64all:%vreg35
1072B		%X1<def> = COPY %vreg36; GPR64all:%vreg36
1088B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
1104B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1120B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1136B		STACKMAP 2, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
1152B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1168B		%vreg32<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0] GPR32:%vreg32
1184B		%W0<def> = COPY %vreg32; GPR32:%vreg32
1200B		RET_ReallyLR %W0<imp-use>

# End machine code for function BZ2_bzread.

********** SIMPLE REGISTER COALESCING **********
********** Function: BZ2_bzread
********** JOINING INTERVALS ***********
if.end:
576B	%X0<def> = COPY %vreg18; GPR64sp:%vreg18
	Considering merging %vreg18 with %X0
	Can only merge into reserved registers.
Remat: %X0<def> = ADDXri <fi#4>, 0, 0
Shrink: %vreg18 [496r,576r:0)  0@496r
All defs dead: 496r	%vreg18<def,dead> = ADDXri <fi#4>, 0, 0; GPR64sp:%vreg18
Shrunk: %vreg18 [496r,496d:0)  0@496r
Deleting dead def 496r	%vreg18<def,dead> = ADDXri <fi#4>, 0, 0; GPR64sp:%vreg18
592B	%X1<def> = COPY %vreg25; GPR64:%vreg25
	Considering merging %vreg25 with %X1
	Can only merge into reserved registers.
608B	%X2<def> = COPY %vreg24; GPR64:%vreg24
	Considering merging %vreg24 with %X2
	Can only merge into reserved registers.
624B	%W3<def> = COPY %vreg23; GPR32:%vreg23
	Considering merging %vreg23 with %W3
	Can only merge into reserved registers.
672B	%vreg22<def> = COPY %W0; GPR32:%vreg22
	Considering merging %vreg22 with %W0
	Can only merge into reserved registers.
lor.lhs.false:
if.then.3:
return:
1056B	%X0<def> = COPY %vreg35; GPR64all:%vreg35
	Considering merging %vreg35 with %X0
	Can only merge into reserved registers.
1072B	%X1<def> = COPY %vreg36; GPR64all:%vreg36
	Considering merging %vreg36 with %X1
	Can only merge into reserved registers.
1184B	%W0<def> = COPY %vreg32; GPR32:%vreg32
	Considering merging %vreg32 with %W0
	Can only merge into reserved registers.
entry:
16B	%vreg14<def> = COPY %LR; GPR64:%vreg14
	Considering merging %vreg14 with %LR
	Can only merge into reserved registers.
32B	%vreg4<def> = COPY %W2; GPR32:%vreg4
	Considering merging %vreg4 with %W2
	Can only merge into reserved registers.
48B	%vreg2<def> = COPY %X1; GPR64:%vreg2
	Considering merging %vreg2 with %X1
	Can only merge into reserved registers.
64B	%vreg0<def> = COPY %X0; GPR64:%vreg0
	Considering merging %vreg0 with %X0
	Can only merge into reserved registers.
208B	%X0<def> = COPY %vreg12; GPR64all:%vreg12
	Considering merging %vreg12 with %X0
	Can only merge into reserved registers.
224B	%X1<def> = COPY %vreg13; GPR64all:%vreg13
	Considering merging %vreg13 with %X1
	Can only merge into reserved registers.
if.then:
if.else:
1008B	%vreg35<def> = COPY %vreg34; GPR64all:%vreg35 GPR64sp:%vreg34
	Considering merging to GPR64sp with %vreg34 in %vreg35
		RHS = %vreg34 [992r,1008r:0)  0@992r
		LHS = %vreg35 [1008r,1056r:0)  0@1008r
		merge %vreg35:0@1008r into %vreg34:0@992r --> @992r
		erased:	1008r	%vreg35<def> = COPY %vreg34; GPR64all:%vreg35 GPR64sp:%vreg34
		updated: 992B	%vreg35<def> = ADDXri %vreg33, <ga:@BZ2_bzread>[TF=34], 0; GPR64sp:%vreg35 GPR64common:%vreg33
	Success: %vreg34 -> %vreg35
	Result = %vreg35 [992r,1056r:0)  0@992r
1024B	%vreg36<def> = COPY %vreg14; GPR64all:%vreg36 GPR64:%vreg14
	Considering merging to GPR64 with %vreg14 in %vreg36
		RHS = %vreg14 [16r,1024r:0)  0@16r
		LHS = %vreg36 [1024r,1072r:0)  0@1024r
		merge %vreg36:0@1024r into %vreg14:0@16r --> @16r
		erased:	1024r	%vreg36<def> = COPY %vreg14; GPR64all:%vreg36 GPR64:%vreg14
		updated: 16B	%vreg36<def> = COPY %LR; GPR64:%vreg36
		updated: 176B	%vreg13<def> = COPY %vreg36; GPR64all:%vreg13 GPR64:%vreg36
	Success: %vreg14 -> %vreg36
	Result = %vreg36 [16r,1072r:0)  0@16r
80B	%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
	Considering merging to GPR64 with %vreg0 in %vreg1
		RHS = %vreg0 [64r,80r:0)  0@64r
		LHS = %vreg1 [80r,320r:0)  0@80r
		merge %vreg1:0@80r into %vreg0:0@64r --> @64r
		erased:	80r	%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
		updated: 64B	%vreg1<def> = COPY %X0; GPR64:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [64r,320r:0)  0@64r
96B	%vreg3<def> = COPY %vreg2; GPR64:%vreg3,%vreg2
	Considering merging to GPR64 with %vreg2 in %vreg3
		RHS = %vreg2 [48r,96r:0)  0@48r
		LHS = %vreg3 [96r,336r:0)  0@96r
		merge %vreg3:0@96r into %vreg2:0@48r --> @48r
		erased:	96r	%vreg3<def> = COPY %vreg2; GPR64:%vreg3,%vreg2
		updated: 48B	%vreg3<def> = COPY %X1; GPR64:%vreg3
	Success: %vreg2 -> %vreg3
	Result = %vreg3 [48r,336r:0)  0@48r
112B	%vreg5<def> = COPY %vreg4; GPR32:%vreg5,%vreg4
	Considering merging to GPR32 with %vreg4 in %vreg5
		RHS = %vreg4 [32r,112r:0)  0@32r
		LHS = %vreg5 [112r,352r:0)  0@112r
		merge %vreg5:0@112r into %vreg4:0@32r --> @32r
		erased:	112r	%vreg5<def> = COPY %vreg4; GPR32:%vreg5,%vreg4
		updated: 32B	%vreg5<def> = COPY %W2; GPR32:%vreg5
	Success: %vreg4 -> %vreg5
	Result = %vreg5 [32r,352r:0)  0@32r
160B	%vreg12<def> = COPY %vreg11; GPR64all:%vreg12 GPR64sp:%vreg11
	Considering merging to GPR64sp with %vreg11 in %vreg12
		RHS = %vreg11 [144r,160r:0)  0@144r
		LHS = %vreg12 [160r,208r:0)  0@160r
		merge %vreg12:0@160r into %vreg11:0@144r --> @144r
		erased:	160r	%vreg12<def> = COPY %vreg11; GPR64all:%vreg12 GPR64sp:%vreg11
		updated: 144B	%vreg12<def> = ADDXri %vreg10, <ga:@BZ2_bzread>[TF=34], 0; GPR64sp:%vreg12 GPR64common:%vreg10
	Success: %vreg11 -> %vreg12
	Result = %vreg12 [144r,208r:0)  0@144r
176B	%vreg13<def> = COPY %vreg36; GPR64all:%vreg13 GPR64:%vreg36
	Considering merging to GPR64 with %vreg36 in %vreg13
		RHS = %vreg36 [16r,1072r:0)  0@16r
		LHS = %vreg13 [176r,224r:0)  0@176r
		merge %vreg13:0@176r into %vreg36:0@16r --> @16r
		erased:	176r	%vreg13<def> = COPY %vreg36; GPR64all:%vreg13 GPR64:%vreg36
		updated: 16B	%vreg13<def> = COPY %LR; GPR64:%vreg13
		updated: 1072B	%X1<def> = COPY %vreg13; GPR64:%vreg13
	Success: %vreg36 -> %vreg13
	Result = %vreg13 [16r,1072r:0)  0@16r
1056B	%X0<def> = COPY %vreg35; GPR64sp:%vreg35
	Considering merging %vreg35 with %X0
	Can only merge into reserved registers.
1072B	%X1<def> = COPY %vreg13; GPR64:%vreg13
	Considering merging %vreg13 with %X1
	Can only merge into reserved registers.
208B	%X0<def> = COPY %vreg12; GPR64sp:%vreg12
	Considering merging %vreg12 with %X0
	Can only merge into reserved registers.
224B	%X1<def> = COPY %vreg13; GPR64:%vreg13
	Considering merging %vreg13 with %X1
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
W30 [0B,16r:0)[240r,240d:6)[288e,288d:3)[640r,640d:5)[704e,704d:2)[1088r,1088d:4)[1136e,1136d:1)  0@0B-phi 1@1136e 2@704e 3@288e 4@1088r 5@640r 6@240r
W0 [0B,64r:0)[208r,240r:5)[576r,640r:4)[640r,672r:2)[1056r,1088r:3)[1184r,1200r:1)  0@0B-phi 1@1184r 2@640r 3@1056r 4@576r 5@208r
W1 [0B,48r:0)[224r,240r:3)[592r,640r:2)[1072r,1088r:1)  0@0B-phi 1@1072r 2@592r 3@224r
W2 [0B,32r:0)[608r,640r:1)  0@0B-phi 1@608r
%vreg1 [64r,320r:0)  0@64r
%vreg3 [48r,336r:0)  0@48r
%vreg5 [32r,352r:0)  0@32r
%vreg8 [384r,400r:0)  0@384r
%vreg9 [368r,384r:0)  0@368r
%vreg10 [128r,144r:0)  0@128r
%vreg12 [144r,208r:0)  0@144r
%vreg13 [16r,1072r:0)  0@16r
%vreg16 [752r,768r:0)  0@752r
%vreg22 [672r,736r:0)  0@672r
%vreg23 [544r,624r:0)  0@544r
%vreg24 [528r,608r:0)  0@528r
%vreg25 [512r,592r:0)  0@512r
%vreg27 [800r,816r:0)  0@800r
%vreg28 [928r,944r:0)  0@928r
%vreg30 [864r,880r:0)  0@864r
%vreg32 [1168r,1184r:0)  0@1168r
%vreg33 [976r,992r:0)  0@976r
%vreg35 [992r,1056r:0)  0@992r
RegMasks: 240r 640r 1088r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzread: Post SSA
Frame Objects:
  fi#0: size=4, align=4, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=8, align=8, at location [SP]
  fi#3: size=4, align=4, at location [SP]
  fi#4: size=4, align=4, at location [SP]
  fi#5: size=4, align=4, at location [SP]
Function Live Ins: %X0 in %vreg0, %X1 in %vreg2, %W2 in %vreg4, %LR in %vreg14

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %X1 %W2 %LR
16B		%vreg13<def> = COPY %LR; GPR64:%vreg13
32B		%vreg5<def> = COPY %W2; GPR32:%vreg5
48B		%vreg3<def> = COPY %X1; GPR64:%vreg3
64B		%vreg1<def> = COPY %X0; GPR64:%vreg1
128B		%vreg10<def> = ADRP <ga:@BZ2_bzread>[TF=1]; GPR64common:%vreg10
144B		%vreg12<def> = ADDXri %vreg10, <ga:@BZ2_bzread>[TF=34], 0; GPR64sp:%vreg12 GPR64common:%vreg10
192B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
208B		%X0<def> = COPY %vreg12; GPR64sp:%vreg12
224B		%X1<def> = COPY %vreg13; GPR64:%vreg13
240B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
256B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
272B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
288B		STACKMAP 0, 0, %vreg1, 0, <fi#1>, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#4>, 0, %vreg5, 0, <fi#3>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack4](align=4) LD8[FixedStack3](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4) GPR64:%vreg1,%vreg3 GPR32:%vreg5
304B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
320B		STRXui %vreg1, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg1
336B		STRXui %vreg3, <fi#2>, 0; mem:ST8[FixedStack2] GPR64:%vreg3
352B		STRWui %vreg5, <fi#3>, 0; mem:ST4[FixedStack3] GPR32:%vreg5
368B		%vreg9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg9
384B		%vreg8<def> = LDRWui %vreg9, 1274; mem:LD4[%lastErr] GPR32common:%vreg8 GPR64common:%vreg9
400B		%WZR<def> = SUBSWri %vreg8, 4, 0, %NZCV<imp-def>; GPR32common:%vreg8
416B		Bcc 1, <BB#2>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

432B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
448B		STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
464B		B <BB#6>
	    Successors according to CFG: BB#6

480B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0
512B		%vreg25<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg25
528B		%vreg24<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg24
544B		%vreg23<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg23
560B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
576B		%X0<def> = ADDXri <fi#4>, 0, 0
592B		%X1<def> = COPY %vreg25; GPR64:%vreg25
608B		%X2<def> = COPY %vreg24; GPR64:%vreg24
624B		%W3<def> = COPY %vreg23; GPR32:%vreg23
640B		BL <ga:@BZ2_bzRead>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %X2<imp-use>, %W3<imp-use,kill>, %W0<imp-def>
656B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
672B		%vreg22<def> = COPY %W0; GPR32:%vreg22
688B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
704B		STACKMAP 1, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4)
720B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
736B		STRWui %vreg22, <fi#5>, 0; mem:ST4[FixedStack5] GPR32:%vreg22
752B		%vreg16<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg16
768B		CBZW %vreg16, <BB#4>; GPR32:%vreg16
	    Successors according to CFG: BB#4 BB#3

784B	BB#3: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#2
800B		%vreg27<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32common:%vreg27
816B		%WZR<def> = SUBSWri %vreg27, 4, 0, %NZCV<imp-def>; GPR32common:%vreg27
832B		Bcc 1, <BB#5>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#5 BB#4

848B	BB#4: derived from LLVM BB %if.then.3
	    Predecessors according to CFG: BB#2 BB#3
864B		%vreg30<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32:%vreg30
880B		STRWui %vreg30, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg30
896B		B <BB#6>
	    Successors according to CFG: BB#6

912B	BB#5: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#3
928B		%vreg28<def> = MOVi32imm 4294967295; GPR32:%vreg28
944B		STRWui %vreg28, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg28
	    Successors according to CFG: BB#6

960B	BB#6: derived from LLVM BB %return
	    Predecessors according to CFG: BB#5 BB#4 BB#1
976B		%vreg33<def> = ADRP <ga:@BZ2_bzread>[TF=1]; GPR64common:%vreg33
992B		%vreg35<def> = ADDXri %vreg33, <ga:@BZ2_bzread>[TF=34], 0; GPR64sp:%vreg35 GPR64common:%vreg33
1040B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1056B		%X0<def> = COPY %vreg35; GPR64sp:%vreg35
1072B		%X1<def> = COPY %vreg13; GPR64:%vreg13
1088B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
1104B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1120B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1136B		STACKMAP 2, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
1152B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1168B		%vreg32<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0] GPR32:%vreg32
1184B		%W0<def> = COPY %vreg32; GPR32:%vreg32
1200B		RET_ReallyLR %W0<imp-use>

# End machine code for function BZ2_bzread.

********** GREEDY REGISTER ALLOCATION **********
********** Function: BZ2_bzread
********** INTERVALS **********
W30 [0B,16r:0)[240r,240d:6)[288e,288d:3)[640r,640d:5)[704e,704d:2)[1088r,1088d:4)[1136e,1136d:1)  0@0B-phi 1@1136e 2@704e 3@288e 4@1088r 5@640r 6@240r
W0 [0B,64r:0)[208r,240r:5)[576r,640r:4)[640r,672r:2)[1056r,1088r:3)[1184r,1200r:1)  0@0B-phi 1@1184r 2@640r 3@1056r 4@576r 5@208r
W1 [0B,48r:0)[224r,240r:3)[592r,640r:2)[1072r,1088r:1)  0@0B-phi 1@1072r 2@592r 3@224r
W2 [0B,32r:0)[608r,640r:1)  0@0B-phi 1@608r
%vreg1 [64r,320r:0)  0@64r
%vreg3 [48r,336r:0)  0@48r
%vreg5 [32r,352r:0)  0@32r
%vreg8 [384r,400r:0)  0@384r
%vreg9 [368r,384r:0)  0@368r
%vreg10 [128r,144r:0)  0@128r
%vreg12 [144r,208r:0)  0@144r
%vreg13 [16r,1072r:0)  0@16r
%vreg16 [752r,768r:0)  0@752r
%vreg22 [672r,736r:0)  0@672r
%vreg23 [544r,624r:0)  0@544r
%vreg24 [528r,608r:0)  0@528r
%vreg25 [512r,592r:0)  0@512r
%vreg27 [800r,816r:0)  0@800r
%vreg28 [928r,944r:0)  0@928r
%vreg30 [864r,880r:0)  0@864r
%vreg32 [1168r,1184r:0)  0@1168r
%vreg33 [976r,992r:0)  0@976r
%vreg35 [992r,1056r:0)  0@992r
RegMasks: 240r 640r 1088r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzread: Post SSA
Frame Objects:
  fi#0: size=4, align=4, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=8, align=8, at location [SP]
  fi#3: size=4, align=4, at location [SP]
  fi#4: size=4, align=4, at location [SP]
  fi#5: size=4, align=4, at location [SP]
Function Live Ins: %X0 in %vreg0, %X1 in %vreg2, %W2 in %vreg4, %LR in %vreg14

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %X1 %W2 %LR
16B		%vreg13<def> = COPY %LR; GPR64:%vreg13
32B		%vreg5<def> = COPY %W2; GPR32:%vreg5
48B		%vreg3<def> = COPY %X1; GPR64:%vreg3
64B		%vreg1<def> = COPY %X0; GPR64:%vreg1
128B		%vreg10<def> = ADRP <ga:@BZ2_bzread>[TF=1]; GPR64common:%vreg10
144B		%vreg12<def> = ADDXri %vreg10, <ga:@BZ2_bzread>[TF=34], 0; GPR64sp:%vreg12 GPR64common:%vreg10
192B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
208B		%X0<def> = COPY %vreg12; GPR64sp:%vreg12
224B		%X1<def> = COPY %vreg13; GPR64:%vreg13
240B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
256B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
272B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
288B		STACKMAP 0, 0, %vreg1, 0, <fi#1>, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#4>, 0, %vreg5, 0, <fi#3>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack4](align=4) LD8[FixedStack3](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4) GPR64:%vreg1,%vreg3 GPR32:%vreg5
304B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
320B		STRXui %vreg1, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg1
336B		STRXui %vreg3, <fi#2>, 0; mem:ST8[FixedStack2] GPR64:%vreg3
352B		STRWui %vreg5, <fi#3>, 0; mem:ST4[FixedStack3] GPR32:%vreg5
368B		%vreg9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg9
384B		%vreg8<def> = LDRWui %vreg9, 1274; mem:LD4[%lastErr] GPR32common:%vreg8 GPR64common:%vreg9
400B		%WZR<def> = SUBSWri %vreg8, 4, 0, %NZCV<imp-def>; GPR32common:%vreg8
416B		Bcc 1, <BB#2>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

432B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
448B		STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
464B		B <BB#6>
	    Successors according to CFG: BB#6

480B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0
512B		%vreg25<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg25
528B		%vreg24<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg24
544B		%vreg23<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg23
560B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
576B		%X0<def> = ADDXri <fi#4>, 0, 0
592B		%X1<def> = COPY %vreg25; GPR64:%vreg25
608B		%X2<def> = COPY %vreg24; GPR64:%vreg24
624B		%W3<def> = COPY %vreg23; GPR32:%vreg23
640B		BL <ga:@BZ2_bzRead>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %X2<imp-use>, %W3<imp-use,kill>, %W0<imp-def>
656B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
672B		%vreg22<def> = COPY %W0; GPR32:%vreg22
688B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
704B		STACKMAP 1, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4)
720B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
736B		STRWui %vreg22, <fi#5>, 0; mem:ST4[FixedStack5] GPR32:%vreg22
752B		%vreg16<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg16
768B		CBZW %vreg16, <BB#4>; GPR32:%vreg16
	    Successors according to CFG: BB#4 BB#3

784B	BB#3: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#2
800B		%vreg27<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32common:%vreg27
816B		%WZR<def> = SUBSWri %vreg27, 4, 0, %NZCV<imp-def>; GPR32common:%vreg27
832B		Bcc 1, <BB#5>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#5 BB#4

848B	BB#4: derived from LLVM BB %if.then.3
	    Predecessors according to CFG: BB#2 BB#3
864B		%vreg30<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32:%vreg30
880B		STRWui %vreg30, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg30
896B		B <BB#6>
	    Successors according to CFG: BB#6

912B	BB#5: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#3
928B		%vreg28<def> = MOVi32imm 4294967295; GPR32:%vreg28
944B		STRWui %vreg28, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg28
	    Successors according to CFG: BB#6

960B	BB#6: derived from LLVM BB %return
	    Predecessors according to CFG: BB#5 BB#4 BB#1
976B		%vreg33<def> = ADRP <ga:@BZ2_bzread>[TF=1]; GPR64common:%vreg33
992B		%vreg35<def> = ADDXri %vreg33, <ga:@BZ2_bzread>[TF=34], 0; GPR64sp:%vreg35 GPR64common:%vreg33
1040B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1056B		%X0<def> = COPY %vreg35; GPR64sp:%vreg35
1072B		%X1<def> = COPY %vreg13; GPR64:%vreg13
1088B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
1104B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1120B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1136B		STACKMAP 2, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
1152B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1168B		%vreg32<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0] GPR32:%vreg32
1184B		%W0<def> = COPY %vreg32; GPR32:%vreg32
1200B		RET_ReallyLR %W0<imp-use>

# End machine code for function BZ2_bzread.


selectOrSplit GPR64:%vreg13 [16r,1072r:0)  0@16r w=2.081044e-03
hints: %X1
missed hint %X1
assigning %vreg13 to %X19: W19 [16r,1072r:0)  0@16r

selectOrSplit GPR32:%vreg5 [32r,352r:0)  0@32r w=4.208333e-03
hints: %W2
missed hint %W2
assigning %vreg5 to %W20: W20 [32r,352r:0)  0@32r

selectOrSplit GPR64:%vreg3 [48r,336r:0)  0@48r w=4.404070e-03
hints: %X1
missed hint %X1
assigning %vreg3 to %X21: W21 [48r,336r:0)  0@48r

selectOrSplit GPR64:%vreg1 [64r,320r:0)  0@64r w=4.618902e-03
hints: %X0
missed hint %X0
assigning %vreg1 to %X22: W22 [64r,320r:0)  0@64r

selectOrSplit GPR64sp:%vreg12 [144r,208r:0)  0@144r w=4.353448e-03
hints: %X0
assigning %vreg12 to %X0: W0 [144r,208r:0)  0@144r

selectOrSplit GPR64:%vreg25 [512r,592r:0)  0@512r w=2.070767e-03
hints: %X1
assigning %vreg25 to %X1: W1 [512r,592r:0)  0@512r

selectOrSplit GPR64:%vreg24 [528r,608r:0)  0@528r w=2.070767e-03
hints: %X2
assigning %vreg24 to %X2: W2 [528r,608r:0)  0@528r

selectOrSplit GPR32:%vreg23 [544r,624r:0)  0@544r w=2.070767e-03
hints: %W3
assigning %vreg23 to %W3: W3 [544r,624r:0)  0@544r

selectOrSplit GPR32:%vreg22 [672r,736r:0)  0@672r w=2.142173e-03
hints: %W0
assigning %vreg22 to %W0: W0 [672r,736r:0)  0@672r

selectOrSplit GPR64sp:%vreg35 [992r,1056r:0)  0@992r w=4.353448e-03
hints: %X0
assigning %vreg35 to %X0: W0 [992r,1056r:0)  0@992r

selectOrSplit GPR32:%vreg32 [1168r,1184r:0)  0@1168r w=inf
hints: %W0
assigning %vreg32 to %W0: W0 [1168r,1184r:0)  0@1168r

selectOrSplit GPR64common:%vreg10 [128r,144r:0)  0@128r w=inf
assigning %vreg10 to %X8: W8 [128r,144r:0)  0@128r

selectOrSplit GPR64common:%vreg9 [368r,384r:0)  0@368r w=inf
assigning %vreg9 to %X8: W8 [368r,384r:0)  0@368r

selectOrSplit GPR32common:%vreg8 [384r,400r:0)  0@384r w=inf
assigning %vreg8 to %W8: W8 [384r,400r:0)  0@384r

selectOrSplit GPR32:%vreg16 [752r,768r:0)  0@752r w=inf
assigning %vreg16 to %W8: W8 [752r,768r:0)  0@752r

selectOrSplit GPR32common:%vreg27 [800r,816r:0)  0@800r w=inf
assigning %vreg27 to %W8: W8 [800r,816r:0)  0@800r

selectOrSplit GPR32:%vreg30 [864r,880r:0)  0@864r w=inf
assigning %vreg30 to %W8: W8 [864r,880r:0)  0@864r

selectOrSplit GPR32:%vreg28 [928r,944r:0)  0@928r w=inf
assigning %vreg28 to %W8: W8 [928r,944r:0)  0@928r

selectOrSplit GPR64common:%vreg33 [976r,992r:0)  0@976r w=inf
assigning %vreg33 to %X8: W8 [976r,992r:0)  0@976r

********** STACK TRANSFORMATION METADATA **********
********** Function: BZ2_bzread
********** REGISTER MAP **********
[%vreg1 -> %X22] GPR64
[%vreg3 -> %X21] GPR64
[%vreg5 -> %W20] GPR32
[%vreg8 -> %W8] GPR32common
[%vreg9 -> %X8] GPR64common
[%vreg10 -> %X8] GPR64common
[%vreg12 -> %X0] GPR64sp
[%vreg13 -> %X19] GPR64
[%vreg16 -> %W8] GPR32
[%vreg22 -> %W0] GPR32
[%vreg23 -> %W3] GPR32
[%vreg24 -> %X2] GPR64
[%vreg25 -> %X1] GPR64
[%vreg27 -> %W8] GPR32common
[%vreg28 -> %W8] GPR32
[%vreg30 -> %W8] GPR32
[%vreg32 -> %W0] GPR32
[%vreg33 -> %X8] GPR64common
[%vreg35 -> %X0] GPR64sp


Stackmap 0:
  STACKMAP 0, 0, %vreg1, 0, <fi#1>, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#4>, 0, %vreg5, 0, <fi#3>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack4](align=4) LD8[FixedStack3](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4) GPR64:%vreg1,%vreg3 GPR32:%vreg5

i8* %b: in register %X22 (vreg 1)
i8** %b.addr: in stack slot 1 (size: 8)
i8* %buf: in register %X21 (vreg 3)
i8** %buf.addr: in stack slot 2 (size: 8)
i32* %bzerr: in stack slot 4 (size: 4)
i32 %len: in register %W20 (vreg 5)
i32* %len.addr: in stack slot 3 (size: 4)
i32* %nread: in stack slot 5 (size: 4)
i32* %retval: in stack slot 0 (size: 4)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4)

i32* %bzerr: in stack slot 4 (size: 4)
i32* %nread: in stack slot 5 (size: 4)
i32* %retval: in stack slot 0 (size: 4)

Duplicate operand locations:


Stackmap 2:
  STACKMAP 2, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)

i32* %retval: in stack slot 0 (size: 4)

Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, %vreg1, 0, <fi#1>, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#4>, 0, %vreg5, 0, <fi#3>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack4](align=4) LD8[FixedStack3](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4) GPR64:%vreg1,%vreg3 GPR32:%vreg5
  -> Call instruction SlotIndex 240B, searching vregs 0 -> 37 and stack slots 0 -> 6
    + vreg13 is live in register but not in stackmap
      Defining instruction: %vreg13<def> = COPY %LR; GPR64:%vreg13
      Value: generated value, 1 instruction(s)

  STACKMAP 1, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4)
  -> Call instruction SlotIndex 640B, searching vregs 0 -> 37 and stack slots 0 -> 6
    + vreg13 is live in register but not in stackmap
      Defining instruction: %vreg13<def> = COPY %LR; GPR64:%vreg13
      Value: generated value, 1 instruction(s)

  STACKMAP 2, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
  -> Call instruction SlotIndex 1088B, searching vregs 0 -> 37 and stack slots 0 -> 6

********** REWRITE VIRTUAL REGISTERS **********
********** Function: BZ2_bzread
********** REGISTER MAP **********
[%vreg1 -> %X22] GPR64
[%vreg3 -> %X21] GPR64
[%vreg5 -> %W20] GPR32
[%vreg8 -> %W8] GPR32common
[%vreg9 -> %X8] GPR64common
[%vreg10 -> %X8] GPR64common
[%vreg12 -> %X0] GPR64sp
[%vreg13 -> %X19] GPR64
[%vreg16 -> %W8] GPR32
[%vreg22 -> %W0] GPR32
[%vreg23 -> %W3] GPR32
[%vreg24 -> %X2] GPR64
[%vreg25 -> %X1] GPR64
[%vreg27 -> %W8] GPR32common
[%vreg28 -> %W8] GPR32
[%vreg30 -> %W8] GPR32
[%vreg32 -> %W0] GPR32
[%vreg33 -> %X8] GPR64common
[%vreg35 -> %X0] GPR64sp

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %LR %W2 %X0 %X1
16B		%vreg13<def> = COPY %LR; GPR64:%vreg13
32B		%vreg5<def> = COPY %W2; GPR32:%vreg5
48B		%vreg3<def> = COPY %X1; GPR64:%vreg3
64B		%vreg1<def> = COPY %X0; GPR64:%vreg1
128B		%vreg10<def> = ADRP <ga:@BZ2_bzread>[TF=1]; GPR64common:%vreg10
144B		%vreg12<def> = ADDXri %vreg10<kill>, <ga:@BZ2_bzread>[TF=34], 0; GPR64sp:%vreg12 GPR64common:%vreg10
192B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
208B		%X0<def> = COPY %vreg12<kill>; GPR64sp:%vreg12
224B		%X1<def> = COPY %vreg13; GPR64:%vreg13
240B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
256B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
272B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
288B		STACKMAP 0, 0, %vreg1, 0, <fi#1>, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#4>, 0, %vreg5, 0, <fi#3>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack4](align=4) LD8[FixedStack3](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4) GPR64:%vreg1,%vreg3 GPR32:%vreg5
304B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
320B		STRXui %vreg1<kill>, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg1
336B		STRXui %vreg3<kill>, <fi#2>, 0; mem:ST8[FixedStack2] GPR64:%vreg3
352B		STRWui %vreg5<kill>, <fi#3>, 0; mem:ST4[FixedStack3] GPR32:%vreg5
368B		%vreg9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg9
384B		%vreg8<def> = LDRWui %vreg9<kill>, 1274; mem:LD4[%lastErr] GPR32common:%vreg8 GPR64common:%vreg9
400B		%WZR<def> = SUBSWri %vreg8<kill>, 4, 0, %NZCV<imp-def>; GPR32common:%vreg8
416B		Bcc 1, <BB#2>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1
> %X19<def> = COPY %LR
> %W20<def> = COPY %W2
> %X21<def> = COPY %X1
> %X22<def> = COPY %X0
> %X8<def> = ADRP <ga:@BZ2_bzread>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@BZ2_bzread>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19
> BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 0, 0, %X22, 0, <fi#1>, 0, %X21, 0, <fi#2>, 0, 0, <fi#4>, 0, %W20, 0, <fi#3>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack4](align=4) LD8[FixedStack3](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRXui %X22<kill>, <fi#1>, 0; mem:ST8[FixedStack1]
> STRXui %X21<kill>, <fi#2>, 0; mem:ST8[FixedStack2]
> STRWui %W20<kill>, <fi#3>, 0; mem:ST4[FixedStack3]
> %X8<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %W8<def> = LDRWui %X8<kill>, 1274; mem:LD4[%lastErr]
> %WZR<def> = SUBSWri %W8<kill>, 4, 0, %NZCV<imp-def>
> Bcc 1, <BB#2>, %NZCV<imp-use,kill>
432B	BB#1: derived from LLVM BB %if.then
	    Live Ins: %X19
	    Predecessors according to CFG: BB#0
448B		STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
464B		B <BB#6>
	    Successors according to CFG: BB#6
> STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
> B <BB#6>
480B	BB#2: derived from LLVM BB %if.end
	    Live Ins: %X19
	    Predecessors according to CFG: BB#0
512B		%vreg25<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg25
528B		%vreg24<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg24
544B		%vreg23<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg23
560B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
576B		%X0<def> = ADDXri <fi#4>, 0, 0
592B		%X1<def> = COPY %vreg25<kill>; GPR64:%vreg25
608B		%X2<def> = COPY %vreg24<kill>; GPR64:%vreg24
624B		%W3<def> = COPY %vreg23<kill>; GPR32:%vreg23
640B		BL <ga:@BZ2_bzRead>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %X2<imp-use>, %W3<imp-use>, %W0<imp-def>
656B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
672B		%vreg22<def> = COPY %W0; GPR32:%vreg22
688B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
704B		STACKMAP 1, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4)
720B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
736B		STRWui %vreg22<kill>, <fi#5>, 0; mem:ST4[FixedStack5] GPR32:%vreg22
752B		%vreg16<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg16
768B		CBZW %vreg16<kill>, <BB#4>; GPR32:%vreg16
	    Successors according to CFG: BB#4 BB#3
> %X1<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X2<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2]
> %W3<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = ADDXri <fi#4>, 0, 0
> %X1<def> = COPY %X1<kill>
Deleting identity copy.
> %X2<def> = COPY %X2<kill>
Deleting identity copy.
> %W3<def> = COPY %W3<kill>
Deleting identity copy.
> BL <ga:@BZ2_bzRead>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %X2<imp-use>, %W3<imp-use>, %W0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = COPY %W0
Deleting identity copy.
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 1, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRWui %W0<kill>, <fi#5>, 0; mem:ST4[FixedStack5]
> %W8<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4]
> CBZW %W8<kill>, <BB#4>
784B	BB#3: derived from LLVM BB %lor.lhs.false
	    Live Ins: %X19
	    Predecessors according to CFG: BB#2
800B		%vreg27<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32common:%vreg27
816B		%WZR<def> = SUBSWri %vreg27<kill>, 4, 0, %NZCV<imp-def>; GPR32common:%vreg27
832B		Bcc 1, <BB#5>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#5 BB#4
> %W8<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4]
> %WZR<def> = SUBSWri %W8<kill>, 4, 0, %NZCV<imp-def>
> Bcc 1, <BB#5>, %NZCV<imp-use,kill>
848B	BB#4: derived from LLVM BB %if.then.3
	    Live Ins: %X19
	    Predecessors according to CFG: BB#2 BB#3
864B		%vreg30<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5] GPR32:%vreg30
880B		STRWui %vreg30<kill>, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg30
896B		B <BB#6>
	    Successors according to CFG: BB#6
> %W8<def> = LDRWui <fi#5>, 0; mem:LD4[FixedStack5]
> STRWui %W8<kill>, <fi#0>, 0; mem:ST4[FixedStack0]
> B <BB#6>
912B	BB#5: derived from LLVM BB %if.else
	    Live Ins: %X19
	    Predecessors according to CFG: BB#3
928B		%vreg28<def> = MOVi32imm 4294967295; GPR32:%vreg28
944B		STRWui %vreg28<kill>, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg28
	    Successors according to CFG: BB#6
> %W8<def> = MOVi32imm 4294967295
> STRWui %W8<kill>, <fi#0>, 0; mem:ST4[FixedStack0]
960B	BB#6: derived from LLVM BB %return
	    Live Ins: %X19
	    Predecessors according to CFG: BB#5 BB#4 BB#1
976B		%vreg33<def> = ADRP <ga:@BZ2_bzread>[TF=1]; GPR64common:%vreg33
992B		%vreg35<def> = ADDXri %vreg33<kill>, <ga:@BZ2_bzread>[TF=34], 0; GPR64sp:%vreg35 GPR64common:%vreg33
1040B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1056B		%X0<def> = COPY %vreg35<kill>; GPR64sp:%vreg35
1072B		%X1<def> = COPY %vreg13<kill>; GPR64:%vreg13
1088B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
1104B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1120B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1136B		STACKMAP 2, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
1152B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1168B		%vreg32<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0] GPR32:%vreg32
1184B		%W0<def> = COPY %vreg32<kill>; GPR32:%vreg32
1200B		RET_ReallyLR %W0<imp-use>
> %X8<def> = ADRP <ga:@BZ2_bzread>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@BZ2_bzread>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19<kill>
> BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 2, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0]
> %W0<def> = COPY %W0<kill>
Deleting identity copy.
> RET_ReallyLR %W0<imp-use>
Computing live-in reg-units in ABI blocks.
0B	BB#0 W0#0 W1#0 W2#0 W30#0
Created 4 new intervals.
********** INTERVALS **********
W30 [0B,16r:0)[240r,240d:5)[304e,304d:3)[512r,512d:6)[560e,560d:2)[864r,864d:4)[912e,912d:1)  0@0B-phi 1@912e 2@560e 3@304e 4@864r 5@240r 6@512r
W0 [0B,64r:0)[208r,240r:3)[448r,512r:4)[832r,864r:2)[960r,976r:1)  0@0B-phi 1@960r 2@832r 3@208r 4@448r
W1 [0B,48r:0)[224r,240r:2)[464r,512r:3)[848r,864r:1)  0@0B-phi 1@848r 2@224r 3@464r
W2 [0B,32r:0)[480r,512r:1)  0@0B-phi 1@480r
%vreg0 [64r,80r:0)  0@64r
%vreg1 [80r,336r:0)  0@80r
%vreg2 [48r,96r:0)  0@48r
%vreg3 [96r,352r:0)  0@96r
%vreg4 [32r,112r:0)  0@32r
%vreg5 [112r,368r:0)  0@112r
%vreg7 [592r,608r:0)  0@592r
%vreg8 [272r,448r:0)  0@272r
%vreg12 [416r,496r:0)  0@416r
%vreg13 [400r,480r:0)  0@400r
%vreg14 [384r,464r:0)  0@384r
%vreg15 [128r,144r:0)  0@128r
%vreg16 [144r,160r:0)  0@144r
%vreg17 [160r,208r:0)  0@160r
%vreg18 [176r,224r:0)  0@176r
%vreg19 [16r,800r:0)  0@16r
%vreg20 [704r,720r:0)  0@704r
%vreg22 [640r,656r:0)  0@640r
%vreg24 [944r,960r:0)  0@944r
%vreg25 [752r,768r:0)  0@752r
%vreg26 [768r,784r:0)  0@768r
%vreg27 [784r,832r:0)  0@784r
%vreg28 [800r,848r:0)  0@800r
RegMasks: 240r 512r 864r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzwrite: Post SSA
Frame Objects:
  fi#0: size=4, align=4, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=8, align=8, at location [SP]
  fi#3: size=4, align=4, at location [SP]
  fi#4: size=4, align=4, at location [SP]
Function Live Ins: %X0 in %vreg0, %X1 in %vreg2, %W2 in %vreg4, %LR in %vreg19

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %X1 %W2 %LR
16B		%vreg19<def> = COPY %LR; GPR64:%vreg19
32B		%vreg4<def> = COPY %W2; GPR32:%vreg4
48B		%vreg2<def> = COPY %X1; GPR64:%vreg2
64B		%vreg0<def> = COPY %X0; GPR64:%vreg0
80B		%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
96B		%vreg3<def> = COPY %vreg2; GPR64:%vreg3,%vreg2
112B		%vreg5<def> = COPY %vreg4; GPR32:%vreg5,%vreg4
128B		%vreg15<def> = ADRP <ga:@BZ2_bzwrite>[TF=1]; GPR64common:%vreg15
144B		%vreg16<def> = ADDXri %vreg15, <ga:@BZ2_bzwrite>[TF=34], 0; GPR64sp:%vreg16 GPR64common:%vreg15
160B		%vreg17<def> = COPY %vreg16; GPR64all:%vreg17 GPR64sp:%vreg16
176B		%vreg18<def> = COPY %vreg19; GPR64all:%vreg18 GPR64:%vreg19
192B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
208B		%X0<def> = COPY %vreg17; GPR64all:%vreg17
224B		%X1<def> = COPY %vreg18; GPR64all:%vreg18
240B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
256B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
272B		%vreg8<def> = ADDXri <fi#4>, 0, 0; GPR64sp:%vreg8
288B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
304B		STACKMAP 0, 0, %vreg1, 0, <fi#1>, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#4>, 0, %vreg5, 0, <fi#3>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack4](align=4) LD8[FixedStack3](align=4) LD8[FixedStack0](align=4) GPR64:%vreg1,%vreg3 GPR32:%vreg5
320B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
336B		STRXui %vreg1, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg1
352B		STRXui %vreg3, <fi#2>, 0; mem:ST8[FixedStack2] GPR64:%vreg3
368B		STRWui %vreg5, <fi#3>, 0; mem:ST4[FixedStack3] GPR32:%vreg5
384B		%vreg14<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg14
400B		%vreg13<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg13
416B		%vreg12<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg12
432B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
448B		%X0<def> = COPY %vreg8; GPR64sp:%vreg8
464B		%X1<def> = COPY %vreg14; GPR64:%vreg14
480B		%X2<def> = COPY %vreg13; GPR64:%vreg13
496B		%W3<def> = COPY %vreg12; GPR32:%vreg12
512B		BL <ga:@BZ2_bzWrite>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %X2<imp-use>, %W3<imp-use,kill>
528B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
544B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
560B		STACKMAP 1, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack4](align=4) LD8[FixedStack3](align=4) LD8[FixedStack0](align=4)
576B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
592B		%vreg7<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg7
608B		CBNZW %vreg7, <BB#2>; GPR32:%vreg7
	    Successors according to CFG: BB#2 BB#1

624B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
640B		%vreg22<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg22
656B		STRWui %vreg22, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg22
672B		B <BB#3>
	    Successors according to CFG: BB#3

688B	BB#2: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#0
704B		%vreg20<def> = MOVi32imm 4294967295; GPR32:%vreg20
720B		STRWui %vreg20, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg20
	    Successors according to CFG: BB#3

736B	BB#3: derived from LLVM BB %return
	    Predecessors according to CFG: BB#2 BB#1
752B		%vreg25<def> = ADRP <ga:@BZ2_bzwrite>[TF=1]; GPR64common:%vreg25
768B		%vreg26<def> = ADDXri %vreg25, <ga:@BZ2_bzwrite>[TF=34], 0; GPR64sp:%vreg26 GPR64common:%vreg25
784B		%vreg27<def> = COPY %vreg26; GPR64all:%vreg27 GPR64sp:%vreg26
800B		%vreg28<def> = COPY %vreg19; GPR64all:%vreg28 GPR64:%vreg19
816B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
832B		%X0<def> = COPY %vreg27; GPR64all:%vreg27
848B		%X1<def> = COPY %vreg28; GPR64all:%vreg28
864B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
880B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
896B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
912B		STACKMAP 2, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
928B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
944B		%vreg24<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0] GPR32:%vreg24
960B		%W0<def> = COPY %vreg24; GPR32:%vreg24
976B		RET_ReallyLR %W0<imp-use>

# End machine code for function BZ2_bzwrite.

********** SIMPLE REGISTER COALESCING **********
********** Function: BZ2_bzwrite
********** JOINING INTERVALS ***********
entry:
16B	%vreg19<def> = COPY %LR; GPR64:%vreg19
	Considering merging %vreg19 with %LR
	Can only merge into reserved registers.
32B	%vreg4<def> = COPY %W2; GPR32:%vreg4
	Considering merging %vreg4 with %W2
	Can only merge into reserved registers.
48B	%vreg2<def> = COPY %X1; GPR64:%vreg2
	Considering merging %vreg2 with %X1
	Can only merge into reserved registers.
64B	%vreg0<def> = COPY %X0; GPR64:%vreg0
	Considering merging %vreg0 with %X0
	Can only merge into reserved registers.
208B	%X0<def> = COPY %vreg17; GPR64all:%vreg17
	Considering merging %vreg17 with %X0
	Can only merge into reserved registers.
224B	%X1<def> = COPY %vreg18; GPR64all:%vreg18
	Considering merging %vreg18 with %X1
	Can only merge into reserved registers.
448B	%X0<def> = COPY %vreg8; GPR64sp:%vreg8
	Considering merging %vreg8 with %X0
	Can only merge into reserved registers.
Remat: %X0<def> = ADDXri <fi#4>, 0, 0
Shrink: %vreg8 [272r,448r:0)  0@272r
All defs dead: 272r	%vreg8<def,dead> = ADDXri <fi#4>, 0, 0; GPR64sp:%vreg8
Shrunk: %vreg8 [272r,272d:0)  0@272r
Deleting dead def 272r	%vreg8<def,dead> = ADDXri <fi#4>, 0, 0; GPR64sp:%vreg8
464B	%X1<def> = COPY %vreg14; GPR64:%vreg14
	Considering merging %vreg14 with %X1
	Can only merge into reserved registers.
480B	%X2<def> = COPY %vreg13; GPR64:%vreg13
	Considering merging %vreg13 with %X2
	Can only merge into reserved registers.
496B	%W3<def> = COPY %vreg12; GPR32:%vreg12
	Considering merging %vreg12 with %W3
	Can only merge into reserved registers.
if.then:
if.else:
return:
832B	%X0<def> = COPY %vreg27; GPR64all:%vreg27
	Considering merging %vreg27 with %X0
	Can only merge into reserved registers.
848B	%X1<def> = COPY %vreg28; GPR64all:%vreg28
	Considering merging %vreg28 with %X1
	Can only merge into reserved registers.
960B	%W0<def> = COPY %vreg24; GPR32:%vreg24
	Considering merging %vreg24 with %W0
	Can only merge into reserved registers.
80B	%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
	Considering merging to GPR64 with %vreg0 in %vreg1
		RHS = %vreg0 [64r,80r:0)  0@64r
		LHS = %vreg1 [80r,336r:0)  0@80r
		merge %vreg1:0@80r into %vreg0:0@64r --> @64r
		erased:	80r	%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
		updated: 64B	%vreg1<def> = COPY %X0; GPR64:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [64r,336r:0)  0@64r
96B	%vreg3<def> = COPY %vreg2; GPR64:%vreg3,%vreg2
	Considering merging to GPR64 with %vreg2 in %vreg3
		RHS = %vreg2 [48r,96r:0)  0@48r
		LHS = %vreg3 [96r,352r:0)  0@96r
		merge %vreg3:0@96r into %vreg2:0@48r --> @48r
		erased:	96r	%vreg3<def> = COPY %vreg2; GPR64:%vreg3,%vreg2
		updated: 48B	%vreg3<def> = COPY %X1; GPR64:%vreg3
	Success: %vreg2 -> %vreg3
	Result = %vreg3 [48r,352r:0)  0@48r
112B	%vreg5<def> = COPY %vreg4; GPR32:%vreg5,%vreg4
	Considering merging to GPR32 with %vreg4 in %vreg5
		RHS = %vreg4 [32r,112r:0)  0@32r
		LHS = %vreg5 [112r,368r:0)  0@112r
		merge %vreg5:0@112r into %vreg4:0@32r --> @32r
		erased:	112r	%vreg5<def> = COPY %vreg4; GPR32:%vreg5,%vreg4
		updated: 32B	%vreg5<def> = COPY %W2; GPR32:%vreg5
	Success: %vreg4 -> %vreg5
	Result = %vreg5 [32r,368r:0)  0@32r
160B	%vreg17<def> = COPY %vreg16; GPR64all:%vreg17 GPR64sp:%vreg16
	Considering merging to GPR64sp with %vreg16 in %vreg17
		RHS = %vreg16 [144r,160r:0)  0@144r
		LHS = %vreg17 [160r,208r:0)  0@160r
		merge %vreg17:0@160r into %vreg16:0@144r --> @144r
		erased:	160r	%vreg17<def> = COPY %vreg16; GPR64all:%vreg17 GPR64sp:%vreg16
		updated: 144B	%vreg17<def> = ADDXri %vreg15, <ga:@BZ2_bzwrite>[TF=34], 0; GPR64sp:%vreg17 GPR64common:%vreg15
	Success: %vreg16 -> %vreg17
	Result = %vreg17 [144r,208r:0)  0@144r
176B	%vreg18<def> = COPY %vreg19; GPR64all:%vreg18 GPR64:%vreg19
	Considering merging to GPR64 with %vreg19 in %vreg18
		RHS = %vreg19 [16r,800r:0)  0@16r
		LHS = %vreg18 [176r,224r:0)  0@176r
		merge %vreg18:0@176r into %vreg19:0@16r --> @16r
		erased:	176r	%vreg18<def> = COPY %vreg19; GPR64all:%vreg18 GPR64:%vreg19
		updated: 16B	%vreg18<def> = COPY %LR; GPR64:%vreg18
		updated: 800B	%vreg28<def> = COPY %vreg18; GPR64all:%vreg28 GPR64:%vreg18
	Success: %vreg19 -> %vreg18
	Result = %vreg18 [16r,800r:0)  0@16r
784B	%vreg27<def> = COPY %vreg26; GPR64all:%vreg27 GPR64sp:%vreg26
	Considering merging to GPR64sp with %vreg26 in %vreg27
		RHS = %vreg26 [768r,784r:0)  0@768r
		LHS = %vreg27 [784r,832r:0)  0@784r
		merge %vreg27:0@784r into %vreg26:0@768r --> @768r
		erased:	784r	%vreg27<def> = COPY %vreg26; GPR64all:%vreg27 GPR64sp:%vreg26
		updated: 768B	%vreg27<def> = ADDXri %vreg25, <ga:@BZ2_bzwrite>[TF=34], 0; GPR64sp:%vreg27 GPR64common:%vreg25
	Success: %vreg26 -> %vreg27
	Result = %vreg27 [768r,832r:0)  0@768r
800B	%vreg28<def> = COPY %vreg18; GPR64all:%vreg28 GPR64:%vreg18
	Considering merging to GPR64 with %vreg18 in %vreg28
		RHS = %vreg18 [16r,800r:0)  0@16r
		LHS = %vreg28 [800r,848r:0)  0@800r
		merge %vreg28:0@800r into %vreg18:0@16r --> @16r
		erased:	800r	%vreg28<def> = COPY %vreg18; GPR64all:%vreg28 GPR64:%vreg18
		updated: 16B	%vreg28<def> = COPY %LR; GPR64:%vreg28
		updated: 224B	%X1<def> = COPY %vreg28; GPR64:%vreg28
	Success: %vreg18 -> %vreg28
	Result = %vreg28 [16r,848r:0)  0@16r
208B	%X0<def> = COPY %vreg17; GPR64sp:%vreg17
	Considering merging %vreg17 with %X0
	Can only merge into reserved registers.
224B	%X1<def> = COPY %vreg28; GPR64:%vreg28
	Considering merging %vreg28 with %X1
	Can only merge into reserved registers.
832B	%X0<def> = COPY %vreg27; GPR64sp:%vreg27
	Considering merging %vreg27 with %X0
	Can only merge into reserved registers.
848B	%X1<def> = COPY %vreg28; GPR64:%vreg28
	Considering merging %vreg28 with %X1
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
W30 [0B,16r:0)[240r,240d:5)[304e,304d:3)[512r,512d:6)[560e,560d:2)[864r,864d:4)[912e,912d:1)  0@0B-phi 1@912e 2@560e 3@304e 4@864r 5@240r 6@512r
W0 [0B,64r:0)[208r,240r:3)[448r,512r:4)[832r,864r:2)[960r,976r:1)  0@0B-phi 1@960r 2@832r 3@208r 4@448r
W1 [0B,48r:0)[224r,240r:2)[464r,512r:3)[848r,864r:1)  0@0B-phi 1@848r 2@224r 3@464r
W2 [0B,32r:0)[480r,512r:1)  0@0B-phi 1@480r
%vreg1 [64r,336r:0)  0@64r
%vreg3 [48r,352r:0)  0@48r
%vreg5 [32r,368r:0)  0@32r
%vreg7 [592r,608r:0)  0@592r
%vreg12 [416r,496r:0)  0@416r
%vreg13 [400r,480r:0)  0@400r
%vreg14 [384r,464r:0)  0@384r
%vreg15 [128r,144r:0)  0@128r
%vreg17 [144r,208r:0)  0@144r
%vreg20 [704r,720r:0)  0@704r
%vreg22 [640r,656r:0)  0@640r
%vreg24 [944r,960r:0)  0@944r
%vreg25 [752r,768r:0)  0@752r
%vreg27 [768r,832r:0)  0@768r
%vreg28 [16r,848r:0)  0@16r
RegMasks: 240r 512r 864r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzwrite: Post SSA
Frame Objects:
  fi#0: size=4, align=4, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=8, align=8, at location [SP]
  fi#3: size=4, align=4, at location [SP]
  fi#4: size=4, align=4, at location [SP]
Function Live Ins: %X0 in %vreg0, %X1 in %vreg2, %W2 in %vreg4, %LR in %vreg19

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %X1 %W2 %LR
16B		%vreg28<def> = COPY %LR; GPR64:%vreg28
32B		%vreg5<def> = COPY %W2; GPR32:%vreg5
48B		%vreg3<def> = COPY %X1; GPR64:%vreg3
64B		%vreg1<def> = COPY %X0; GPR64:%vreg1
128B		%vreg15<def> = ADRP <ga:@BZ2_bzwrite>[TF=1]; GPR64common:%vreg15
144B		%vreg17<def> = ADDXri %vreg15, <ga:@BZ2_bzwrite>[TF=34], 0; GPR64sp:%vreg17 GPR64common:%vreg15
192B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
208B		%X0<def> = COPY %vreg17; GPR64sp:%vreg17
224B		%X1<def> = COPY %vreg28; GPR64:%vreg28
240B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
256B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
288B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
304B		STACKMAP 0, 0, %vreg1, 0, <fi#1>, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#4>, 0, %vreg5, 0, <fi#3>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack4](align=4) LD8[FixedStack3](align=4) LD8[FixedStack0](align=4) GPR64:%vreg1,%vreg3 GPR32:%vreg5
320B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
336B		STRXui %vreg1, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg1
352B		STRXui %vreg3, <fi#2>, 0; mem:ST8[FixedStack2] GPR64:%vreg3
368B		STRWui %vreg5, <fi#3>, 0; mem:ST4[FixedStack3] GPR32:%vreg5
384B		%vreg14<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg14
400B		%vreg13<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg13
416B		%vreg12<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg12
432B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
448B		%X0<def> = ADDXri <fi#4>, 0, 0
464B		%X1<def> = COPY %vreg14; GPR64:%vreg14
480B		%X2<def> = COPY %vreg13; GPR64:%vreg13
496B		%W3<def> = COPY %vreg12; GPR32:%vreg12
512B		BL <ga:@BZ2_bzWrite>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %X2<imp-use>, %W3<imp-use,kill>
528B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
544B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
560B		STACKMAP 1, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack4](align=4) LD8[FixedStack3](align=4) LD8[FixedStack0](align=4)
576B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
592B		%vreg7<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg7
608B		CBNZW %vreg7, <BB#2>; GPR32:%vreg7
	    Successors according to CFG: BB#2 BB#1

624B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
640B		%vreg22<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg22
656B		STRWui %vreg22, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg22
672B		B <BB#3>
	    Successors according to CFG: BB#3

688B	BB#2: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#0
704B		%vreg20<def> = MOVi32imm 4294967295; GPR32:%vreg20
720B		STRWui %vreg20, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg20
	    Successors according to CFG: BB#3

736B	BB#3: derived from LLVM BB %return
	    Predecessors according to CFG: BB#2 BB#1
752B		%vreg25<def> = ADRP <ga:@BZ2_bzwrite>[TF=1]; GPR64common:%vreg25
768B		%vreg27<def> = ADDXri %vreg25, <ga:@BZ2_bzwrite>[TF=34], 0; GPR64sp:%vreg27 GPR64common:%vreg25
816B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
832B		%X0<def> = COPY %vreg27; GPR64sp:%vreg27
848B		%X1<def> = COPY %vreg28; GPR64:%vreg28
864B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
880B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
896B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
912B		STACKMAP 2, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
928B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
944B		%vreg24<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0] GPR32:%vreg24
960B		%W0<def> = COPY %vreg24; GPR32:%vreg24
976B		RET_ReallyLR %W0<imp-use>

# End machine code for function BZ2_bzwrite.

********** GREEDY REGISTER ALLOCATION **********
********** Function: BZ2_bzwrite
********** INTERVALS **********
W30 [0B,16r:0)[240r,240d:5)[304e,304d:3)[512r,512d:6)[560e,560d:2)[864r,864d:4)[912e,912d:1)  0@0B-phi 1@912e 2@560e 3@304e 4@864r 5@240r 6@512r
W0 [0B,64r:0)[208r,240r:3)[448r,512r:4)[832r,864r:2)[960r,976r:1)  0@0B-phi 1@960r 2@832r 3@208r 4@448r
W1 [0B,48r:0)[224r,240r:2)[464r,512r:3)[848r,864r:1)  0@0B-phi 1@848r 2@224r 3@464r
W2 [0B,32r:0)[480r,512r:1)  0@0B-phi 1@480r
%vreg1 [64r,336r:0)  0@64r
%vreg3 [48r,352r:0)  0@48r
%vreg5 [32r,368r:0)  0@32r
%vreg7 [592r,608r:0)  0@592r
%vreg12 [416r,496r:0)  0@416r
%vreg13 [400r,480r:0)  0@400r
%vreg14 [384r,464r:0)  0@384r
%vreg15 [128r,144r:0)  0@128r
%vreg17 [144r,208r:0)  0@144r
%vreg20 [704r,720r:0)  0@704r
%vreg22 [640r,656r:0)  0@640r
%vreg24 [944r,960r:0)  0@944r
%vreg25 [752r,768r:0)  0@752r
%vreg27 [768r,832r:0)  0@768r
%vreg28 [16r,848r:0)  0@16r
RegMasks: 240r 512r 864r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzwrite: Post SSA
Frame Objects:
  fi#0: size=4, align=4, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=8, align=8, at location [SP]
  fi#3: size=4, align=4, at location [SP]
  fi#4: size=4, align=4, at location [SP]
Function Live Ins: %X0 in %vreg0, %X1 in %vreg2, %W2 in %vreg4, %LR in %vreg19

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %X1 %W2 %LR
16B		%vreg28<def> = COPY %LR; GPR64:%vreg28
32B		%vreg5<def> = COPY %W2; GPR32:%vreg5
48B		%vreg3<def> = COPY %X1; GPR64:%vreg3
64B		%vreg1<def> = COPY %X0; GPR64:%vreg1
128B		%vreg15<def> = ADRP <ga:@BZ2_bzwrite>[TF=1]; GPR64common:%vreg15
144B		%vreg17<def> = ADDXri %vreg15, <ga:@BZ2_bzwrite>[TF=34], 0; GPR64sp:%vreg17 GPR64common:%vreg15
192B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
208B		%X0<def> = COPY %vreg17; GPR64sp:%vreg17
224B		%X1<def> = COPY %vreg28; GPR64:%vreg28
240B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
256B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
288B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
304B		STACKMAP 0, 0, %vreg1, 0, <fi#1>, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#4>, 0, %vreg5, 0, <fi#3>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack4](align=4) LD8[FixedStack3](align=4) LD8[FixedStack0](align=4) GPR64:%vreg1,%vreg3 GPR32:%vreg5
320B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
336B		STRXui %vreg1, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg1
352B		STRXui %vreg3, <fi#2>, 0; mem:ST8[FixedStack2] GPR64:%vreg3
368B		STRWui %vreg5, <fi#3>, 0; mem:ST4[FixedStack3] GPR32:%vreg5
384B		%vreg14<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg14
400B		%vreg13<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg13
416B		%vreg12<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg12
432B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
448B		%X0<def> = ADDXri <fi#4>, 0, 0
464B		%X1<def> = COPY %vreg14; GPR64:%vreg14
480B		%X2<def> = COPY %vreg13; GPR64:%vreg13
496B		%W3<def> = COPY %vreg12; GPR32:%vreg12
512B		BL <ga:@BZ2_bzWrite>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %X2<imp-use>, %W3<imp-use,kill>
528B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
544B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
560B		STACKMAP 1, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack4](align=4) LD8[FixedStack3](align=4) LD8[FixedStack0](align=4)
576B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
592B		%vreg7<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg7
608B		CBNZW %vreg7, <BB#2>; GPR32:%vreg7
	    Successors according to CFG: BB#2 BB#1

624B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
640B		%vreg22<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg22
656B		STRWui %vreg22, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg22
672B		B <BB#3>
	    Successors according to CFG: BB#3

688B	BB#2: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#0
704B		%vreg20<def> = MOVi32imm 4294967295; GPR32:%vreg20
720B		STRWui %vreg20, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg20
	    Successors according to CFG: BB#3

736B	BB#3: derived from LLVM BB %return
	    Predecessors according to CFG: BB#2 BB#1
752B		%vreg25<def> = ADRP <ga:@BZ2_bzwrite>[TF=1]; GPR64common:%vreg25
768B		%vreg27<def> = ADDXri %vreg25, <ga:@BZ2_bzwrite>[TF=34], 0; GPR64sp:%vreg27 GPR64common:%vreg25
816B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
832B		%X0<def> = COPY %vreg27; GPR64sp:%vreg27
848B		%X1<def> = COPY %vreg28; GPR64:%vreg28
864B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
880B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
896B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
912B		STACKMAP 2, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
928B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
944B		%vreg24<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0] GPR32:%vreg24
960B		%W0<def> = COPY %vreg24; GPR32:%vreg24
976B		RET_ReallyLR %W0<imp-use>

# End machine code for function BZ2_bzwrite.


selectOrSplit GPR64:%vreg28 [16r,848r:0)  0@16r w=2.459415e-03
hints: %X1
missed hint %X1
assigning %vreg28 to %X19: W19 [16r,848r:0)  0@16r

selectOrSplit GPR32:%vreg5 [32r,368r:0)  0@32r w=4.116848e-03
hints: %W2
missed hint %W2
assigning %vreg5 to %W20: W20 [32r,368r:0)  0@32r

selectOrSplit GPR64:%vreg3 [48r,352r:0)  0@48r w=4.303977e-03
hints: %X1
missed hint %X1
assigning %vreg3 to %X21: W21 [48r,352r:0)  0@48r

selectOrSplit GPR64:%vreg1 [64r,336r:0)  0@64r w=4.508928e-03
hints: %X0
missed hint %X0
assigning %vreg1 to %X22: W22 [64r,336r:0)  0@64r

selectOrSplit GPR64sp:%vreg17 [144r,208r:0)  0@144r w=4.353448e-03
hints: %X0
assigning %vreg17 to %X0: W0 [144r,208r:0)  0@144r

selectOrSplit GPR64:%vreg14 [384r,464r:0)  0@384r w=4.208333e-03
hints: %X1
assigning %vreg14 to %X1: W1 [384r,464r:0)  0@384r

selectOrSplit GPR64:%vreg13 [400r,480r:0)  0@400r w=4.208333e-03
hints: %X2
assigning %vreg13 to %X2: W2 [400r,480r:0)  0@400r

selectOrSplit GPR32:%vreg12 [416r,496r:0)  0@416r w=4.208333e-03
hints: %W3
assigning %vreg12 to %W3: W3 [416r,496r:0)  0@416r

selectOrSplit GPR64sp:%vreg27 [768r,832r:0)  0@768r w=4.353448e-03
hints: %X0
assigning %vreg27 to %X0: W0 [768r,832r:0)  0@768r

selectOrSplit GPR32:%vreg24 [944r,960r:0)  0@944r w=inf
hints: %W0
assigning %vreg24 to %W0: W0 [944r,960r:0)  0@944r

selectOrSplit GPR64common:%vreg15 [128r,144r:0)  0@128r w=inf
assigning %vreg15 to %X8: W8 [128r,144r:0)  0@128r

selectOrSplit GPR32:%vreg7 [592r,608r:0)  0@592r w=inf
assigning %vreg7 to %W8: W8 [592r,608r:0)  0@592r

selectOrSplit GPR32:%vreg22 [640r,656r:0)  0@640r w=inf
assigning %vreg22 to %W8: W8 [640r,656r:0)  0@640r

selectOrSplit GPR32:%vreg20 [704r,720r:0)  0@704r w=inf
assigning %vreg20 to %W8: W8 [704r,720r:0)  0@704r

selectOrSplit GPR64common:%vreg25 [752r,768r:0)  0@752r w=inf
assigning %vreg25 to %X8: W8 [752r,768r:0)  0@752r

********** STACK TRANSFORMATION METADATA **********
********** Function: BZ2_bzwrite
********** REGISTER MAP **********
[%vreg1 -> %X22] GPR64
[%vreg3 -> %X21] GPR64
[%vreg5 -> %W20] GPR32
[%vreg7 -> %W8] GPR32
[%vreg12 -> %W3] GPR32
[%vreg13 -> %X2] GPR64
[%vreg14 -> %X1] GPR64
[%vreg15 -> %X8] GPR64common
[%vreg17 -> %X0] GPR64sp
[%vreg20 -> %W8] GPR32
[%vreg22 -> %W8] GPR32
[%vreg24 -> %W0] GPR32
[%vreg25 -> %X8] GPR64common
[%vreg27 -> %X0] GPR64sp
[%vreg28 -> %X19] GPR64


Stackmap 0:
  STACKMAP 0, 0, %vreg1, 0, <fi#1>, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#4>, 0, %vreg5, 0, <fi#3>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack4](align=4) LD8[FixedStack3](align=4) LD8[FixedStack0](align=4) GPR64:%vreg1,%vreg3 GPR32:%vreg5

i8* %b: in register %X22 (vreg 1)
i8** %b.addr: in stack slot 1 (size: 8)
i8* %buf: in register %X21 (vreg 3)
i8** %buf.addr: in stack slot 2 (size: 8)
i32* %bzerr: in stack slot 4 (size: 4)
i32 %len: in register %W20 (vreg 5)
i32* %len.addr: in stack slot 3 (size: 4)
i32* %retval: in stack slot 0 (size: 4)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack4](align=4) LD8[FixedStack3](align=4) LD8[FixedStack0](align=4)

i32* %bzerr: in stack slot 4 (size: 4)
i32* %len.addr: in stack slot 3 (size: 4)
i32* %retval: in stack slot 0 (size: 4)

Duplicate operand locations:


Stackmap 2:
  STACKMAP 2, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)

i32* %retval: in stack slot 0 (size: 4)

Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, %vreg1, 0, <fi#1>, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#4>, 0, %vreg5, 0, <fi#3>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack4](align=4) LD8[FixedStack3](align=4) LD8[FixedStack0](align=4) GPR64:%vreg1,%vreg3 GPR32:%vreg5
  -> Call instruction SlotIndex 240B, searching vregs 0 -> 29 and stack slots 0 -> 5
    + vreg28 is live in register but not in stackmap
      Defining instruction: %vreg28<def> = COPY %LR; GPR64:%vreg28
      Value: generated value, 1 instruction(s)

  STACKMAP 1, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack4](align=4) LD8[FixedStack3](align=4) LD8[FixedStack0](align=4)
  -> Call instruction SlotIndex 512B, searching vregs 0 -> 29 and stack slots 0 -> 5
    + vreg28 is live in register but not in stackmap
      Defining instruction: %vreg28<def> = COPY %LR; GPR64:%vreg28
      Value: generated value, 1 instruction(s)

  STACKMAP 2, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
  -> Call instruction SlotIndex 864B, searching vregs 0 -> 29 and stack slots 0 -> 5

********** REWRITE VIRTUAL REGISTERS **********
********** Function: BZ2_bzwrite
********** REGISTER MAP **********
[%vreg1 -> %X22] GPR64
[%vreg3 -> %X21] GPR64
[%vreg5 -> %W20] GPR32
[%vreg7 -> %W8] GPR32
[%vreg12 -> %W3] GPR32
[%vreg13 -> %X2] GPR64
[%vreg14 -> %X1] GPR64
[%vreg15 -> %X8] GPR64common
[%vreg17 -> %X0] GPR64sp
[%vreg20 -> %W8] GPR32
[%vreg22 -> %W8] GPR32
[%vreg24 -> %W0] GPR32
[%vreg25 -> %X8] GPR64common
[%vreg27 -> %X0] GPR64sp
[%vreg28 -> %X19] GPR64

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %LR %W2 %X0 %X1
16B		%vreg28<def> = COPY %LR; GPR64:%vreg28
32B		%vreg5<def> = COPY %W2; GPR32:%vreg5
48B		%vreg3<def> = COPY %X1; GPR64:%vreg3
64B		%vreg1<def> = COPY %X0; GPR64:%vreg1
128B		%vreg15<def> = ADRP <ga:@BZ2_bzwrite>[TF=1]; GPR64common:%vreg15
144B		%vreg17<def> = ADDXri %vreg15<kill>, <ga:@BZ2_bzwrite>[TF=34], 0; GPR64sp:%vreg17 GPR64common:%vreg15
192B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
208B		%X0<def> = COPY %vreg17<kill>; GPR64sp:%vreg17
224B		%X1<def> = COPY %vreg28; GPR64:%vreg28
240B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
256B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
288B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
304B		STACKMAP 0, 0, %vreg1, 0, <fi#1>, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#4>, 0, %vreg5, 0, <fi#3>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack4](align=4) LD8[FixedStack3](align=4) LD8[FixedStack0](align=4) GPR64:%vreg1,%vreg3 GPR32:%vreg5
320B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
336B		STRXui %vreg1<kill>, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg1
352B		STRXui %vreg3<kill>, <fi#2>, 0; mem:ST8[FixedStack2] GPR64:%vreg3
368B		STRWui %vreg5<kill>, <fi#3>, 0; mem:ST4[FixedStack3] GPR32:%vreg5
384B		%vreg14<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64:%vreg14
400B		%vreg13<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg13
416B		%vreg12<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg12
432B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
448B		%X0<def> = ADDXri <fi#4>, 0, 0
464B		%X1<def> = COPY %vreg14<kill>; GPR64:%vreg14
480B		%X2<def> = COPY %vreg13<kill>; GPR64:%vreg13
496B		%W3<def> = COPY %vreg12<kill>; GPR32:%vreg12
512B		BL <ga:@BZ2_bzWrite>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %X2<imp-use>, %W3<imp-use>
528B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
544B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
560B		STACKMAP 1, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack4](align=4) LD8[FixedStack3](align=4) LD8[FixedStack0](align=4)
576B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
592B		%vreg7<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg7
608B		CBNZW %vreg7<kill>, <BB#2>; GPR32:%vreg7
	    Successors according to CFG: BB#2 BB#1
> %X19<def> = COPY %LR
> %W20<def> = COPY %W2
> %X21<def> = COPY %X1
> %X22<def> = COPY %X0
> %X8<def> = ADRP <ga:@BZ2_bzwrite>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@BZ2_bzwrite>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19
> BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 0, 0, %X22, 0, <fi#1>, 0, %X21, 0, <fi#2>, 0, 0, <fi#4>, 0, %W20, 0, <fi#3>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack4](align=4) LD8[FixedStack3](align=4) LD8[FixedStack0](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRXui %X22<kill>, <fi#1>, 0; mem:ST8[FixedStack1]
> STRXui %X21<kill>, <fi#2>, 0; mem:ST8[FixedStack2]
> STRWui %W20<kill>, <fi#3>, 0; mem:ST4[FixedStack3]
> %X1<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> %X2<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2]
> %W3<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = ADDXri <fi#4>, 0, 0
> %X1<def> = COPY %X1<kill>
Deleting identity copy.
> %X2<def> = COPY %X2<kill>
Deleting identity copy.
> %W3<def> = COPY %W3<kill>
Deleting identity copy.
> BL <ga:@BZ2_bzWrite>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %X2<imp-use>, %W3<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 1, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack4](align=4) LD8[FixedStack3](align=4) LD8[FixedStack0](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W8<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4]
> CBNZW %W8<kill>, <BB#2>
624B	BB#1: derived from LLVM BB %if.then
	    Live Ins: %X19
	    Predecessors according to CFG: BB#0
640B		%vreg22<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3] GPR32:%vreg22
656B		STRWui %vreg22<kill>, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg22
672B		B <BB#3>
	    Successors according to CFG: BB#3
> %W8<def> = LDRWui <fi#3>, 0; mem:LD4[FixedStack3]
> STRWui %W8<kill>, <fi#0>, 0; mem:ST4[FixedStack0]
> B <BB#3>
688B	BB#2: derived from LLVM BB %if.else
	    Live Ins: %X19
	    Predecessors according to CFG: BB#0
704B		%vreg20<def> = MOVi32imm 4294967295; GPR32:%vreg20
720B		STRWui %vreg20<kill>, <fi#0>, 0; mem:ST4[FixedStack0] GPR32:%vreg20
	    Successors according to CFG: BB#3
> %W8<def> = MOVi32imm 4294967295
> STRWui %W8<kill>, <fi#0>, 0; mem:ST4[FixedStack0]
736B	BB#3: derived from LLVM BB %return
	    Live Ins: %X19
	    Predecessors according to CFG: BB#2 BB#1
752B		%vreg25<def> = ADRP <ga:@BZ2_bzwrite>[TF=1]; GPR64common:%vreg25
768B		%vreg27<def> = ADDXri %vreg25<kill>, <ga:@BZ2_bzwrite>[TF=34], 0; GPR64sp:%vreg27 GPR64common:%vreg25
816B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
832B		%X0<def> = COPY %vreg27<kill>; GPR64sp:%vreg27
848B		%X1<def> = COPY %vreg28<kill>; GPR64:%vreg28
864B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
880B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
896B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
912B		STACKMAP 2, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
928B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
944B		%vreg24<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0] GPR32:%vreg24
960B		%W0<def> = COPY %vreg24<kill>; GPR32:%vreg24
976B		RET_ReallyLR %W0<imp-use>
> %X8<def> = ADRP <ga:@BZ2_bzwrite>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@BZ2_bzwrite>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19<kill>
> BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 2, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = LDRWui <fi#0>, 0; mem:LD4[FixedStack0]
> %W0<def> = COPY %W0<kill>
Deleting identity copy.
> RET_ReallyLR %W0<imp-use>
Computing live-in reg-units in ABI blocks.
0B	BB#0 W0#0 W30#0
Created 2 new intervals.
********** INTERVALS **********
W30 [0B,16r:0)[176r,176d:2)[272e,272d:1)[384r,384d:3)[448e,448d:4)  0@0B-phi 1@272e 2@176r 3@384r 4@448e
W0 [0B,32r:0)[144r,176r:2)[352r,384r:3)[480r,496r:1)  0@0B-phi 1@480r 2@144r 3@352r
%vreg0 [32r,48r:0)  0@32r
%vreg1 [48r,304r:0)  0@48r
%vreg2 [416r,480r:0)  0@416r
%vreg3 [208r,224r:0)  0@208r
%vreg4 [224r,240r:0)  0@224r
%vreg5 [240r,352r:0)  0@240r
%vreg6 [320r,368r:0)  0@320r
%vreg7 [16r,320r:0)  0@16r
%vreg8 [64r,80r:0)  0@64r
%vreg9 [80r,96r:0)  0@80r
%vreg10 [96r,144r:0)  0@96r
%vreg11 [112r,160r:0)  0@112r
RegMasks: 176r 384r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzflush: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
Function Live Ins: %X0 in %vreg0, %LR in %vreg7

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %LR
16B		%vreg7<def> = COPY %LR; GPR64:%vreg7
32B		%vreg0<def> = COPY %X0; GPR64:%vreg0
48B		%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
64B		%vreg8<def> = ADRP <ga:@BZ2_bzflush>[TF=1]; GPR64common:%vreg8
80B		%vreg9<def> = ADDXri %vreg8, <ga:@BZ2_bzflush>[TF=34], 0; GPR64sp:%vreg9 GPR64common:%vreg8
96B		%vreg10<def> = COPY %vreg9; GPR64all:%vreg10 GPR64sp:%vreg9
112B		%vreg11<def> = COPY %vreg7; GPR64all:%vreg11 GPR64:%vreg7
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		%X0<def> = COPY %vreg10; GPR64all:%vreg10
160B		%X1<def> = COPY %vreg11; GPR64all:%vreg11
176B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		%vreg3<def> = ADRP <ga:@BZ2_bzflush>[TF=1]; GPR64common:%vreg3
224B		%vreg4<def> = ADDXri %vreg3, <ga:@BZ2_bzflush>[TF=34], 0; GPR64sp:%vreg4 GPR64common:%vreg3
240B		%vreg5<def> = COPY %vreg4; GPR64all:%vreg5 GPR64sp:%vreg4
256B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
272B		STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] GPR64:%vreg1
288B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
304B		STRXui %vreg1, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg1
320B		%vreg6<def> = COPY %vreg7; GPR64all:%vreg6 GPR64:%vreg7
336B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
352B		%X0<def> = COPY %vreg5; GPR64all:%vreg5
368B		%X1<def> = COPY %vreg6; GPR64all:%vreg6
384B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
400B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
416B		%vreg2<def> = COPY %WZR; GPR32:%vreg2
432B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
448B		STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...
464B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
480B		%W0<def> = COPY %vreg2; GPR32:%vreg2
496B		RET_ReallyLR %W0<imp-use>

# End machine code for function BZ2_bzflush.

********** SIMPLE REGISTER COALESCING **********
********** Function: BZ2_bzflush
********** JOINING INTERVALS ***********
entry:
16B	%vreg7<def> = COPY %LR; GPR64:%vreg7
	Considering merging %vreg7 with %LR
	Can only merge into reserved registers.
32B	%vreg0<def> = COPY %X0; GPR64:%vreg0
	Considering merging %vreg0 with %X0
	Can only merge into reserved registers.
144B	%X0<def> = COPY %vreg10; GPR64all:%vreg10
	Considering merging %vreg10 with %X0
	Can only merge into reserved registers.
160B	%X1<def> = COPY %vreg11; GPR64all:%vreg11
	Considering merging %vreg11 with %X1
	Can only merge into reserved registers.
352B	%X0<def> = COPY %vreg5; GPR64all:%vreg5
	Considering merging %vreg5 with %X0
	Can only merge into reserved registers.
368B	%X1<def> = COPY %vreg6; GPR64all:%vreg6
	Considering merging %vreg6 with %X1
	Can only merge into reserved registers.
416B	%vreg2<def> = COPY %WZR; GPR32:%vreg2
	Considering merging %vreg2 with %WZR
		RHS = %vreg2 [416r,480r:0)  0@416r
		updated: 480B	%W0<def> = COPY %WZR
	Success: %vreg2 -> %WZR
	Result = %WZR
480B	%W0<def> = COPY %WZR
	Not coalescable.
48B	%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
	Considering merging to GPR64 with %vreg0 in %vreg1
		RHS = %vreg0 [32r,48r:0)  0@32r
		LHS = %vreg1 [48r,304r:0)  0@48r
		merge %vreg1:0@48r into %vreg0:0@32r --> @32r
		erased:	48r	%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
		updated: 32B	%vreg1<def> = COPY %X0; GPR64:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [32r,304r:0)  0@32r
96B	%vreg10<def> = COPY %vreg9; GPR64all:%vreg10 GPR64sp:%vreg9
	Considering merging to GPR64sp with %vreg9 in %vreg10
		RHS = %vreg9 [80r,96r:0)  0@80r
		LHS = %vreg10 [96r,144r:0)  0@96r
		merge %vreg10:0@96r into %vreg9:0@80r --> @80r
		erased:	96r	%vreg10<def> = COPY %vreg9; GPR64all:%vreg10 GPR64sp:%vreg9
		updated: 80B	%vreg10<def> = ADDXri %vreg8, <ga:@BZ2_bzflush>[TF=34], 0; GPR64sp:%vreg10 GPR64common:%vreg8
	Success: %vreg9 -> %vreg10
	Result = %vreg10 [80r,144r:0)  0@80r
112B	%vreg11<def> = COPY %vreg7; GPR64all:%vreg11 GPR64:%vreg7
	Considering merging to GPR64 with %vreg7 in %vreg11
		RHS = %vreg7 [16r,320r:0)  0@16r
		LHS = %vreg11 [112r,160r:0)  0@112r
		merge %vreg11:0@112r into %vreg7:0@16r --> @16r
		erased:	112r	%vreg11<def> = COPY %vreg7; GPR64all:%vreg11 GPR64:%vreg7
		updated: 16B	%vreg11<def> = COPY %LR; GPR64:%vreg11
		updated: 320B	%vreg6<def> = COPY %vreg11; GPR64all:%vreg6 GPR64:%vreg11
	Success: %vreg7 -> %vreg11
	Result = %vreg11 [16r,320r:0)  0@16r
240B	%vreg5<def> = COPY %vreg4; GPR64all:%vreg5 GPR64sp:%vreg4
	Considering merging to GPR64sp with %vreg4 in %vreg5
		RHS = %vreg4 [224r,240r:0)  0@224r
		LHS = %vreg5 [240r,352r:0)  0@240r
		merge %vreg5:0@240r into %vreg4:0@224r --> @224r
		erased:	240r	%vreg5<def> = COPY %vreg4; GPR64all:%vreg5 GPR64sp:%vreg4
		updated: 224B	%vreg5<def> = ADDXri %vreg3, <ga:@BZ2_bzflush>[TF=34], 0; GPR64sp:%vreg5 GPR64common:%vreg3
	Success: %vreg4 -> %vreg5
	Result = %vreg5 [224r,352r:0)  0@224r
320B	%vreg6<def> = COPY %vreg11; GPR64all:%vreg6 GPR64:%vreg11
	Considering merging to GPR64 with %vreg11 in %vreg6
		RHS = %vreg11 [16r,320r:0)  0@16r
		LHS = %vreg6 [320r,368r:0)  0@320r
		merge %vreg6:0@320r into %vreg11:0@16r --> @16r
		erased:	320r	%vreg6<def> = COPY %vreg11; GPR64all:%vreg6 GPR64:%vreg11
		updated: 16B	%vreg6<def> = COPY %LR; GPR64:%vreg6
		updated: 160B	%X1<def> = COPY %vreg6; GPR64:%vreg6
	Success: %vreg11 -> %vreg6
	Result = %vreg6 [16r,368r:0)  0@16r
144B	%X0<def> = COPY %vreg10; GPR64sp:%vreg10
	Considering merging %vreg10 with %X0
	Can only merge into reserved registers.
160B	%X1<def> = COPY %vreg6; GPR64:%vreg6
	Considering merging %vreg6 with %X1
	Can only merge into reserved registers.
352B	%X0<def> = COPY %vreg5; GPR64sp:%vreg5
	Considering merging %vreg5 with %X0
	Can only merge into reserved registers.
368B	%X1<def> = COPY %vreg6; GPR64:%vreg6
	Considering merging %vreg6 with %X1
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
W30 [0B,16r:0)[176r,176d:2)[272e,272d:1)[384r,384d:3)[448e,448d:4)  0@0B-phi 1@272e 2@176r 3@384r 4@448e
WZR EMPTY
W0 [0B,32r:0)[144r,176r:2)[352r,384r:3)[480r,496r:1)  0@0B-phi 1@480r 2@144r 3@352r
%vreg1 [32r,304r:0)  0@32r
%vreg3 [208r,224r:0)  0@208r
%vreg5 [224r,352r:0)  0@224r
%vreg6 [16r,368r:0)  0@16r
%vreg8 [64r,80r:0)  0@64r
%vreg10 [80r,144r:0)  0@80r
RegMasks: 176r 384r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzflush: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
Function Live Ins: %X0 in %vreg0, %LR in %vreg7

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %LR
16B		%vreg6<def> = COPY %LR; GPR64:%vreg6
32B		%vreg1<def> = COPY %X0; GPR64:%vreg1
64B		%vreg8<def> = ADRP <ga:@BZ2_bzflush>[TF=1]; GPR64common:%vreg8
80B		%vreg10<def> = ADDXri %vreg8, <ga:@BZ2_bzflush>[TF=34], 0; GPR64sp:%vreg10 GPR64common:%vreg8
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		%X0<def> = COPY %vreg10; GPR64sp:%vreg10
160B		%X1<def> = COPY %vreg6; GPR64:%vreg6
176B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		%vreg3<def> = ADRP <ga:@BZ2_bzflush>[TF=1]; GPR64common:%vreg3
224B		%vreg5<def> = ADDXri %vreg3, <ga:@BZ2_bzflush>[TF=34], 0; GPR64sp:%vreg5 GPR64common:%vreg3
256B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
272B		STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] GPR64:%vreg1
288B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
304B		STRXui %vreg1, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg1
336B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
352B		%X0<def> = COPY %vreg5; GPR64sp:%vreg5
368B		%X1<def> = COPY %vreg6; GPR64:%vreg6
384B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
400B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
432B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
448B		STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...
464B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
480B		%W0<def> = COPY %WZR
496B		RET_ReallyLR %W0<imp-use>

# End machine code for function BZ2_bzflush.

********** GREEDY REGISTER ALLOCATION **********
********** Function: BZ2_bzflush
********** INTERVALS **********
W30 [0B,16r:0)[176r,176d:2)[272e,272d:1)[384r,384d:3)[448e,448d:4)  0@0B-phi 1@272e 2@176r 3@384r 4@448e
WZR EMPTY
W0 [0B,32r:0)[144r,176r:2)[352r,384r:3)[480r,496r:1)  0@0B-phi 1@480r 2@144r 3@352r
%vreg1 [32r,304r:0)  0@32r
%vreg3 [208r,224r:0)  0@208r
%vreg5 [224r,352r:0)  0@224r
%vreg6 [16r,368r:0)  0@16r
%vreg8 [64r,80r:0)  0@64r
%vreg10 [80r,144r:0)  0@80r
RegMasks: 176r 384r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzflush: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
Function Live Ins: %X0 in %vreg0, %LR in %vreg7

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %LR
16B		%vreg6<def> = COPY %LR; GPR64:%vreg6
32B		%vreg1<def> = COPY %X0; GPR64:%vreg1
64B		%vreg8<def> = ADRP <ga:@BZ2_bzflush>[TF=1]; GPR64common:%vreg8
80B		%vreg10<def> = ADDXri %vreg8, <ga:@BZ2_bzflush>[TF=34], 0; GPR64sp:%vreg10 GPR64common:%vreg8
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		%X0<def> = COPY %vreg10; GPR64sp:%vreg10
160B		%X1<def> = COPY %vreg6; GPR64:%vreg6
176B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		%vreg3<def> = ADRP <ga:@BZ2_bzflush>[TF=1]; GPR64common:%vreg3
224B		%vreg5<def> = ADDXri %vreg3, <ga:@BZ2_bzflush>[TF=34], 0; GPR64sp:%vreg5 GPR64common:%vreg3
256B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
272B		STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] GPR64:%vreg1
288B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
304B		STRXui %vreg1, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg1
336B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
352B		%X0<def> = COPY %vreg5; GPR64sp:%vreg5
368B		%X1<def> = COPY %vreg6; GPR64:%vreg6
384B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
400B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
432B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
448B		STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...
464B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
480B		%W0<def> = COPY %WZR
496B		RET_ReallyLR %W0<imp-use>

# End machine code for function BZ2_bzflush.


selectOrSplit GPR64:%vreg6 [16r,368r:0)  0@16r w=4.029255e-03
hints: %X1
missed hint %X1
assigning %vreg6 to %X19: W19 [16r,368r:0)  0@16r

selectOrSplit GPR64:%vreg1 [32r,304r:0)  0@32r w=4.508928e-03
hints: %X0
missed hint %X0
assigning %vreg1 to %X20: W20 [32r,304r:0)  0@32r

selectOrSplit GPR64sp:%vreg10 [80r,144r:0)  0@80r w=4.353448e-03
hints: %X0
assigning %vreg10 to %X0: W0 [80r,144r:0)  0@80r

selectOrSplit GPR64sp:%vreg5 [224r,352r:0)  0@224r w=3.825758e-03
hints: %X0
assigning %vreg5 to %X0: W0 [224r,352r:0)  0@224r

selectOrSplit GPR64common:%vreg8 [64r,80r:0)  0@64r w=inf
assigning %vreg8 to %X8: W8 [64r,80r:0)  0@64r

selectOrSplit GPR64common:%vreg3 [208r,224r:0)  0@208r w=inf
assigning %vreg3 to %X8: W8 [208r,224r:0)  0@208r

********** STACK TRANSFORMATION METADATA **********
********** Function: BZ2_bzflush
********** REGISTER MAP **********
[%vreg1 -> %X20] GPR64
[%vreg3 -> %X8] GPR64common
[%vreg5 -> %X0] GPR64sp
[%vreg6 -> %X19] GPR64
[%vreg8 -> %X8] GPR64common
[%vreg10 -> %X0] GPR64sp


Stackmap 0:
  STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] GPR64:%vreg1

i8* %b: in register %X20 (vreg 1)
i8** %b.addr: in stack slot 0 (size: 8)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...


Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] GPR64:%vreg1
  -> Call instruction SlotIndex 176B, searching vregs 0 -> 12 and stack slots 0 -> 1
    + vreg6 is live in register but not in stackmap
      Defining instruction: %vreg6<def> = COPY %LR; GPR64:%vreg6
      Value: generated value, 1 instruction(s)

  STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...
  -> Call instruction SlotIndex 384B, searching vregs 0 -> 12 and stack slots 0 -> 1

********** REWRITE VIRTUAL REGISTERS **********
********** Function: BZ2_bzflush
********** REGISTER MAP **********
[%vreg1 -> %X20] GPR64
[%vreg3 -> %X8] GPR64common
[%vreg5 -> %X0] GPR64sp
[%vreg6 -> %X19] GPR64
[%vreg8 -> %X8] GPR64common
[%vreg10 -> %X0] GPR64sp

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %LR %X0
16B		%vreg6<def> = COPY %LR; GPR64:%vreg6
32B		%vreg1<def> = COPY %X0; GPR64:%vreg1
64B		%vreg8<def> = ADRP <ga:@BZ2_bzflush>[TF=1]; GPR64common:%vreg8
80B		%vreg10<def> = ADDXri %vreg8<kill>, <ga:@BZ2_bzflush>[TF=34], 0; GPR64sp:%vreg10 GPR64common:%vreg8
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		%X0<def> = COPY %vreg10<kill>; GPR64sp:%vreg10
160B		%X1<def> = COPY %vreg6; GPR64:%vreg6
176B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		%vreg3<def> = ADRP <ga:@BZ2_bzflush>[TF=1]; GPR64common:%vreg3
224B		%vreg5<def> = ADDXri %vreg3<kill>, <ga:@BZ2_bzflush>[TF=34], 0; GPR64sp:%vreg5 GPR64common:%vreg3
256B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
272B		STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] GPR64:%vreg1
288B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
304B		STRXui %vreg1<kill>, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg1
336B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
352B		%X0<def> = COPY %vreg5<kill>; GPR64sp:%vreg5
368B		%X1<def> = COPY %vreg6<kill>; GPR64:%vreg6
384B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
400B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
432B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
448B		STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...
464B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
480B		%W0<def> = COPY %WZR
496B		RET_ReallyLR %W0<imp-use>
> %X19<def> = COPY %LR
> %X20<def> = COPY %X0
> %X8<def> = ADRP <ga:@BZ2_bzflush>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@BZ2_bzflush>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19
> BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X8<def> = ADRP <ga:@BZ2_bzflush>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@BZ2_bzflush>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 0, 0, %X20, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRXui %X20<kill>, <fi#0>, 0; mem:ST8[FixedStack0]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19<kill>
> BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = COPY %WZR
> RET_ReallyLR %W0<imp-use>
Computing live-in reg-units in ABI blocks.
0B	BB#0 W0#0 W30#0
Created 2 new intervals.
********** INTERVALS **********
W30 [0B,16r:0)[176r,176d:12)[224e,224d:4)[672r,672d:10)[720e,720d:3)[944r,944d:9)[992e,992d:2)[1152r,1152d:11)[1200e,1200d:1)[1520r,1520d:7)[1584e,1584d:8)[1744r,1744d:5)[1792e,1792d:6)  0@0B-phi 1@1200e 2@992e 3@720e 4@224e 5@1744r 6@1792e 7@1520r 8@1584e 9@944r 10@672r 11@1152r 12@176r
W0 [0B,32r:0)[144r,176r:7)[592r,672r:5)[864r,944r:4)[1120r,1152r:6)[1504r,1520r:3)[1520r,1552r:1)[1712r,1744r:2)  0@0B-phi 1@1520r 2@1712r 3@1504r 4@864r 5@592r 6@1120r 7@144r
%vreg0 [32r,48r:0)  0@32r
%vreg1 [48r,256r:0)  0@48r
%vreg3 [320r,336r:0)  0@320r
%vreg6 [288r,304r:0)  0@288r
%vreg7 [272r,288r:0)  0@272r
%vreg8 [64r,80r:0)  0@64r
%vreg9 [80r,96r:0)  0@80r
%vreg10 [96r,144r:0)  0@96r
%vreg11 [112r,160r:0)  0@112r
%vreg12 [16r,1680r:0)  0@16r
%vreg14 [464r,480r:0)  0@464r
%vreg16 [416r,432r:0)  0@416r
%vreg17 [432r,448r:0)  0@432r
%vreg18 [448r,464r:0)  0@448r
%vreg19 [400r,432r:0)  0@400r
%vreg20 [1072r,1120r:0)  0@1072r
%vreg22 [1088r,1136r:0)  0@1088r
%vreg24 [752r,768r:0)  0@752r
%vreg25 [512r,592r:0)  0@512r
%vreg27 [528r,624r:0)  0@528r
%vreg28 [544r,656r:0)  0@544r
%vreg29 [560r,608r:0)  0@560r
%vreg30 [800r,928r:0)  0@800r
%vreg32 [816r,896r:0)  0@816r
%vreg33 [832r,880r:0)  0@832r
%vreg36 [1248r,1264r:0)  0@1248r
%vreg37 [1264r,1296r:0)  0@1264r
%vreg38 [1296r,1312r:0)  0@1296r
%vreg39 [1280r,1312r:0)  0@1280r
%vreg42 [1360r,1376r:0)  0@1360r
%vreg43 [1376r,1408r:0)  0@1376r
%vreg44 [1408r,1424r:0)  0@1408r
%vreg45 [1392r,1424r:0)  0@1392r
%vreg47 [1552r,1552d:0)  0@1552r
%vreg48 [1472r,1504r:0)  0@1472r
%vreg49 [1632r,1648r:0)  0@1632r
%vreg50 [1648r,1664r:0)  0@1648r
%vreg51 [1664r,1712r:0)  0@1664r
%vreg52 [1680r,1728r:0)  0@1680r
RegMasks: 176r 672r 944r 1152r 1520r 1744r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzclose: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
  fi#1: size=4, align=4, at location [SP]
  fi#2: size=8, align=8, at location [SP]
Function Live Ins: %X0 in %vreg0, %LR in %vreg12

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %LR
16B		%vreg12<def> = COPY %LR; GPR64:%vreg12
32B		%vreg0<def> = COPY %X0; GPR64:%vreg0
48B		%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
64B		%vreg8<def> = ADRP <ga:@BZ2_bzclose>[TF=1]; GPR64common:%vreg8
80B		%vreg9<def> = ADDXri %vreg8, <ga:@BZ2_bzclose>[TF=34], 0; GPR64sp:%vreg9 GPR64common:%vreg8
96B		%vreg10<def> = COPY %vreg9; GPR64all:%vreg10 GPR64sp:%vreg9
112B		%vreg11<def> = COPY %vreg12; GPR64all:%vreg11 GPR64:%vreg12
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		%X0<def> = COPY %vreg10; GPR64all:%vreg10
160B		%X1<def> = COPY %vreg11; GPR64all:%vreg11
176B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
224B		STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] LD8[FixedStack1](align=4) LD8[FixedStack2] GPR64:%vreg1
240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
256B		STRXui %vreg1, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg1
272B		%vreg7<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg7
288B		%vreg6<def> = LDRXui %vreg7, 0; mem:LD8[%handle] GPR64:%vreg6 GPR64common:%vreg7
304B		STRXui %vreg6, <fi#2>, 0; mem:ST8[FixedStack2] GPR64:%vreg6
320B		%vreg3<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg3
336B		CBNZX %vreg3, <BB#2>; GPR64:%vreg3
	    Successors according to CFG: BB#2 BB#1

352B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
368B		B <BB#10>
	    Successors according to CFG: BB#10

384B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0
400B		%vreg19<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg19
416B		%vreg16<def> = MOVi64imm 5012; GPR64:%vreg16
432B		%vreg17<def> = ADDXrr %vreg19, %vreg16; GPR64common:%vreg17 GPR64:%vreg19,%vreg16
448B		%vreg18<def> = LDRBBui %vreg17, 0; mem:LD1[%writing] GPR32:%vreg18 GPR64common:%vreg17
464B		%vreg14<def> = UBFMWri %vreg18, 0, 7; GPR32:%vreg14,%vreg18
480B		CBZW %vreg14, <BB#6>; GPR32:%vreg14
	    Successors according to CFG: BB#6 BB#3

496B	BB#3: derived from LLVM BB %if.then.1
	    Predecessors according to CFG: BB#2
512B		%vreg25<def> = ADDXri <fi#1>, 0, 0; GPR64sp:%vreg25
528B		%vreg27<def> = COPY %WZR; GPR32:%vreg27
544B		%vreg28<def> = COPY %XZR; GPR64:%vreg28
560B		%vreg29<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg29
576B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
592B		%X0<def> = COPY %vreg25; GPR64sp:%vreg25
608B		%X1<def> = COPY %vreg29; GPR64:%vreg29
624B		%W2<def> = COPY %vreg27; GPR32:%vreg27
640B		%X3<def> = COPY %vreg28; GPR64:%vreg28
656B		%X4<def> = COPY %vreg28; GPR64:%vreg28
672B		BL <ga:@BZ2_bzWriteClose>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %W2<imp-use,kill>, %X3<imp-use,kill>, %X4<imp-use,kill>
688B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
704B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
720B		STACKMAP 1, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] LD8[FixedStack1](align=4) LD8[FixedStack2]
736B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
752B		%vreg24<def> = LDRWui <fi#1>, 0; mem:LD4[FixedStack1] GPR32:%vreg24
768B		CBZW %vreg24, <BB#5>; GPR32:%vreg24
	    Successors according to CFG: BB#5 BB#4

784B	BB#4: derived from LLVM BB %if.then.3
	    Predecessors according to CFG: BB#3
800B		%vreg30<def> = COPY %XZR; GPR64:%vreg30
816B		%vreg32<def> = MOVi32imm 1; GPR32:%vreg32
832B		%vreg33<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg33
848B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
864B		%X0<def> = COPY %vreg30; GPR64:%vreg30
880B		%X1<def> = COPY %vreg33; GPR64:%vreg33
896B		%W2<def> = COPY %vreg32; GPR32:%vreg32
912B		%X3<def> = COPY %vreg30; GPR64:%vreg30
928B		%X4<def> = COPY %vreg30; GPR64:%vreg30
944B		BL <ga:@BZ2_bzWriteClose>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %W2<imp-use,kill>, %X3<imp-use,kill>, %X4<imp-use,kill>
960B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
976B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
992B		STACKMAP 2, 0, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2]
1008B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#5

1024B	BB#5: derived from LLVM BB %if.end.4
	    Predecessors according to CFG: BB#3 BB#4
1040B		B <BB#7>
	    Successors according to CFG: BB#7

1056B	BB#6: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#2
1072B		%vreg20<def> = ADDXri <fi#1>, 0, 0; GPR64sp:%vreg20
1088B		%vreg22<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg22
1104B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1120B		%X0<def> = COPY %vreg20; GPR64sp:%vreg20
1136B		%X1<def> = COPY %vreg22; GPR64:%vreg22
1152B		BL <ga:@BZ2_bzReadClose>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
1168B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1184B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1200B		STACKMAP 3, 0, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2]
1216B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#7

1232B	BB#7: derived from LLVM BB %if.end.5
	    Predecessors according to CFG: BB#6 BB#5
1248B		%vreg36<def> = ADRP <ga:@stdin>[TF=1]; GPR64common:%vreg36
1264B		%vreg37<def> = ADDXri %vreg36, <ga:@stdin>[TF=34], 0; GPR64sp:%vreg37 GPR64common:%vreg36
1280B		%vreg39<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg39
1296B		%vreg38<def> = LDRXui %vreg37, 0; mem:LD8[@stdin] GPR64:%vreg38 GPR64sp:%vreg37
1312B		%XZR<def> = SUBSXrr %vreg39, %vreg38, %NZCV<imp-def>; GPR64:%vreg39,%vreg38
1328B		Bcc 0, <BB#10>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#10 BB#8

1344B	BB#8: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#7
1360B		%vreg42<def> = ADRP <ga:@stdout>[TF=1]; GPR64common:%vreg42
1376B		%vreg43<def> = ADDXri %vreg42, <ga:@stdout>[TF=34], 0; GPR64sp:%vreg43 GPR64common:%vreg42
1392B		%vreg45<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg45
1408B		%vreg44<def> = LDRXui %vreg43, 0; mem:LD8[@stdout] GPR64:%vreg44 GPR64sp:%vreg43
1424B		%XZR<def> = SUBSXrr %vreg45, %vreg44, %NZCV<imp-def>; GPR64:%vreg45,%vreg44
1440B		Bcc 0, <BB#10>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#10 BB#9

1456B	BB#9: derived from LLVM BB %if.then.8
	    Predecessors according to CFG: BB#8
1472B		%vreg48<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg48
1488B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1504B		%X0<def> = COPY %vreg48; GPR64:%vreg48
1520B		BL <ga:@fclose>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
1536B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1552B		%vreg47<def,dead> = COPY %W0; GPR32all:%vreg47
1568B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1584B		STACKMAP 4, 0, %LR<earlyclobber,imp-def,dead>, ...
1600B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#10

1616B	BB#10: derived from LLVM BB %if.end.9
	    Predecessors according to CFG: BB#7 BB#8 BB#9 BB#1
1632B		%vreg49<def> = ADRP <ga:@BZ2_bzclose>[TF=1]; GPR64common:%vreg49
1648B		%vreg50<def> = ADDXri %vreg49, <ga:@BZ2_bzclose>[TF=34], 0; GPR64sp:%vreg50 GPR64common:%vreg49
1664B		%vreg51<def> = COPY %vreg50; GPR64all:%vreg51 GPR64sp:%vreg50
1680B		%vreg52<def> = COPY %vreg12; GPR64all:%vreg52 GPR64:%vreg12
1696B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1712B		%X0<def> = COPY %vreg51; GPR64all:%vreg51
1728B		%X1<def> = COPY %vreg52; GPR64all:%vreg52
1744B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
1760B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1776B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1792B		STACKMAP 5, 0, %LR<earlyclobber,imp-def,dead>, ...
1808B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1824B		RET_ReallyLR

# End machine code for function BZ2_bzclose.

********** SIMPLE REGISTER COALESCING **********
********** Function: BZ2_bzclose
********** JOINING INTERVALS ***********
if.end.5:
if.end.9:
1712B	%X0<def> = COPY %vreg51; GPR64all:%vreg51
	Considering merging %vreg51 with %X0
	Can only merge into reserved registers.
1728B	%X1<def> = COPY %vreg52; GPR64all:%vreg52
	Considering merging %vreg52 with %X1
	Can only merge into reserved registers.
if.end:
if.then.1:
528B	%vreg27<def> = COPY %WZR; GPR32:%vreg27
	Considering merging %vreg27 with %WZR
		RHS = %vreg27 [528r,624r:0)  0@528r
		updated: 624B	%W2<def> = COPY %WZR
	Success: %vreg27 -> %WZR
	Result = %WZR
544B	%vreg28<def> = COPY %XZR; GPR64:%vreg28
	Considering merging %vreg28 with %XZR
		RHS = %vreg28 [544r,656r:0)  0@544r
		updated: 640B	%X3<def> = COPY %XZR
		updated: 656B	%X4<def> = COPY %XZR
	Success: %vreg28 -> %XZR
	Result = %XZR
592B	%X0<def> = COPY %vreg25; GPR64sp:%vreg25
	Considering merging %vreg25 with %X0
	Can only merge into reserved registers.
Remat: %X0<def> = ADDXri <fi#1>, 0, 0
Shrink: %vreg25 [512r,592r:0)  0@512r
All defs dead: 512r	%vreg25<def,dead> = ADDXri <fi#1>, 0, 0; GPR64sp:%vreg25
Shrunk: %vreg25 [512r,512d:0)  0@512r
Deleting dead def 512r	%vreg25<def,dead> = ADDXri <fi#1>, 0, 0; GPR64sp:%vreg25
608B	%X1<def> = COPY %vreg29; GPR64:%vreg29
	Considering merging %vreg29 with %X1
	Can only merge into reserved registers.
624B	%W2<def> = COPY %WZR
	Not coalescable.
640B	%X3<def> = COPY %XZR
	Not coalescable.
656B	%X4<def> = COPY %XZR
	Not coalescable.
if.end.4:
land.lhs.true:
entry:
16B	%vreg12<def> = COPY %LR; GPR64:%vreg12
	Considering merging %vreg12 with %LR
	Can only merge into reserved registers.
32B	%vreg0<def> = COPY %X0; GPR64:%vreg0
	Considering merging %vreg0 with %X0
	Can only merge into reserved registers.
144B	%X0<def> = COPY %vreg10; GPR64all:%vreg10
	Considering merging %vreg10 with %X0
	Can only merge into reserved registers.
160B	%X1<def> = COPY %vreg11; GPR64all:%vreg11
	Considering merging %vreg11 with %X1
	Can only merge into reserved registers.
if.then:
if.then.3:
800B	%vreg30<def> = COPY %XZR; GPR64:%vreg30
	Considering merging %vreg30 with %XZR
		RHS = %vreg30 [800r,928r:0)  0@800r
		updated: 864B	%X0<def> = COPY %XZR
		updated: 912B	%X3<def> = COPY %XZR
		updated: 928B	%X4<def> = COPY %XZR
	Success: %vreg30 -> %XZR
	Result = %XZR
864B	%X0<def> = COPY %XZR
	Not coalescable.
880B	%X1<def> = COPY %vreg33; GPR64:%vreg33
	Considering merging %vreg33 with %X1
	Can only merge into reserved registers.
896B	%W2<def> = COPY %vreg32; GPR32:%vreg32
	Considering merging %vreg32 with %W2
	Can only merge into reserved registers.
Remat: %W2<def> = MOVi32imm 1
Shrink: %vreg32 [816r,896r:0)  0@816r
All defs dead: 816r	%vreg32<def,dead> = MOVi32imm 1; GPR32:%vreg32
Shrunk: %vreg32 [816r,816d:0)  0@816r
Deleting dead def 816r	%vreg32<def,dead> = MOVi32imm 1; GPR32:%vreg32
912B	%X3<def> = COPY %XZR
	Not coalescable.
928B	%X4<def> = COPY %XZR
	Not coalescable.
if.else:
1120B	%X0<def> = COPY %vreg20; GPR64sp:%vreg20
	Considering merging %vreg20 with %X0
	Can only merge into reserved registers.
Remat: %X0<def> = ADDXri <fi#1>, 0, 0
Shrink: %vreg20 [1072r,1120r:0)  0@1072r
All defs dead: 1072r	%vreg20<def,dead> = ADDXri <fi#1>, 0, 0; GPR64sp:%vreg20
Shrunk: %vreg20 [1072r,1072d:0)  0@1072r
Deleting dead def 1072r	%vreg20<def,dead> = ADDXri <fi#1>, 0, 0; GPR64sp:%vreg20
1136B	%X1<def> = COPY %vreg22; GPR64:%vreg22
	Considering merging %vreg22 with %X1
	Can only merge into reserved registers.
if.then.8:
1504B	%X0<def> = COPY %vreg48; GPR64:%vreg48
	Considering merging %vreg48 with %X0
	Can only merge into reserved registers.
1552B	%vreg47<def,dead> = COPY %W0; GPR32all:%vreg47
	Considering merging %vreg47 with %W0
	Can only merge into reserved registers.
1664B	%vreg51<def> = COPY %vreg50; GPR64all:%vreg51 GPR64sp:%vreg50
	Considering merging to GPR64sp with %vreg50 in %vreg51
		RHS = %vreg50 [1648r,1664r:0)  0@1648r
		LHS = %vreg51 [1664r,1712r:0)  0@1664r
		merge %vreg51:0@1664r into %vreg50:0@1648r --> @1648r
		erased:	1664r	%vreg51<def> = COPY %vreg50; GPR64all:%vreg51 GPR64sp:%vreg50
		updated: 1648B	%vreg51<def> = ADDXri %vreg49, <ga:@BZ2_bzclose>[TF=34], 0; GPR64sp:%vreg51 GPR64common:%vreg49
	Success: %vreg50 -> %vreg51
	Result = %vreg51 [1648r,1712r:0)  0@1648r
1680B	%vreg52<def> = COPY %vreg12; GPR64all:%vreg52 GPR64:%vreg12
	Considering merging to GPR64 with %vreg12 in %vreg52
		RHS = %vreg12 [16r,1680r:0)  0@16r
		LHS = %vreg52 [1680r,1728r:0)  0@1680r
		merge %vreg52:0@1680r into %vreg12:0@16r --> @16r
		erased:	1680r	%vreg52<def> = COPY %vreg12; GPR64all:%vreg52 GPR64:%vreg12
		updated: 16B	%vreg52<def> = COPY %LR; GPR64:%vreg52
		updated: 112B	%vreg11<def> = COPY %vreg52; GPR64all:%vreg11 GPR64:%vreg52
	Success: %vreg12 -> %vreg52
	Result = %vreg52 [16r,1728r:0)  0@16r
48B	%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
	Considering merging to GPR64 with %vreg0 in %vreg1
		RHS = %vreg0 [32r,48r:0)  0@32r
		LHS = %vreg1 [48r,256r:0)  0@48r
		merge %vreg1:0@48r into %vreg0:0@32r --> @32r
		erased:	48r	%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
		updated: 32B	%vreg1<def> = COPY %X0; GPR64:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [32r,256r:0)  0@32r
96B	%vreg10<def> = COPY %vreg9; GPR64all:%vreg10 GPR64sp:%vreg9
	Considering merging to GPR64sp with %vreg9 in %vreg10
		RHS = %vreg9 [80r,96r:0)  0@80r
		LHS = %vreg10 [96r,144r:0)  0@96r
		merge %vreg10:0@96r into %vreg9:0@80r --> @80r
		erased:	96r	%vreg10<def> = COPY %vreg9; GPR64all:%vreg10 GPR64sp:%vreg9
		updated: 80B	%vreg10<def> = ADDXri %vreg8, <ga:@BZ2_bzclose>[TF=34], 0; GPR64sp:%vreg10 GPR64common:%vreg8
	Success: %vreg9 -> %vreg10
	Result = %vreg10 [80r,144r:0)  0@80r
112B	%vreg11<def> = COPY %vreg52; GPR64all:%vreg11 GPR64:%vreg52
	Considering merging to GPR64 with %vreg52 in %vreg11
		RHS = %vreg52 [16r,1728r:0)  0@16r
		LHS = %vreg11 [112r,160r:0)  0@112r
		merge %vreg11:0@112r into %vreg52:0@16r --> @16r
		erased:	112r	%vreg11<def> = COPY %vreg52; GPR64all:%vreg11 GPR64:%vreg52
		updated: 16B	%vreg11<def> = COPY %LR; GPR64:%vreg11
		updated: 1728B	%X1<def> = COPY %vreg11; GPR64:%vreg11
	Success: %vreg52 -> %vreg11
	Result = %vreg11 [16r,1728r:0)  0@16r
1712B	%X0<def> = COPY %vreg51; GPR64sp:%vreg51
	Considering merging %vreg51 with %X0
	Can only merge into reserved registers.
1728B	%X1<def> = COPY %vreg11; GPR64:%vreg11
	Considering merging %vreg11 with %X1
	Can only merge into reserved registers.
144B	%X0<def> = COPY %vreg10; GPR64sp:%vreg10
	Considering merging %vreg10 with %X0
	Can only merge into reserved registers.
160B	%X1<def> = COPY %vreg11; GPR64:%vreg11
	Considering merging %vreg11 with %X1
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
W30 [0B,16r:0)[176r,176d:12)[224e,224d:4)[672r,672d:10)[720e,720d:3)[944r,944d:9)[992e,992d:2)[1152r,1152d:11)[1200e,1200d:1)[1520r,1520d:7)[1584e,1584d:8)[1744r,1744d:5)[1792e,1792d:6)  0@0B-phi 1@1200e 2@992e 3@720e 4@224e 5@1744r 6@1792e 7@1520r 8@1584e 9@944r 10@672r 11@1152r 12@176r
WZR [1312r,1312d:1)[1424r,1424d:0)  0@1424r 1@1312r
W0 [0B,32r:0)[144r,176r:7)[592r,672r:5)[864r,944r:4)[1120r,1152r:6)[1504r,1520r:3)[1520r,1552r:1)[1712r,1744r:2)  0@0B-phi 1@1520r 2@1712r 3@1504r 4@864r 5@592r 6@1120r 7@144r
%vreg1 [32r,256r:0)  0@32r
%vreg3 [320r,336r:0)  0@320r
%vreg6 [288r,304r:0)  0@288r
%vreg7 [272r,288r:0)  0@272r
%vreg8 [64r,80r:0)  0@64r
%vreg10 [80r,144r:0)  0@80r
%vreg11 [16r,1728r:0)  0@16r
%vreg14 [464r,480r:0)  0@464r
%vreg16 [416r,432r:0)  0@416r
%vreg17 [432r,448r:0)  0@432r
%vreg18 [448r,464r:0)  0@448r
%vreg19 [400r,432r:0)  0@400r
%vreg22 [1088r,1136r:0)  0@1088r
%vreg24 [752r,768r:0)  0@752r
%vreg29 [560r,608r:0)  0@560r
%vreg33 [832r,880r:0)  0@832r
%vreg36 [1248r,1264r:0)  0@1248r
%vreg37 [1264r,1296r:0)  0@1264r
%vreg38 [1296r,1312r:0)  0@1296r
%vreg39 [1280r,1312r:0)  0@1280r
%vreg42 [1360r,1376r:0)  0@1360r
%vreg43 [1376r,1408r:0)  0@1376r
%vreg44 [1408r,1424r:0)  0@1408r
%vreg45 [1392r,1424r:0)  0@1392r
%vreg47 [1552r,1552d:0)  0@1552r
%vreg48 [1472r,1504r:0)  0@1472r
%vreg49 [1632r,1648r:0)  0@1632r
%vreg51 [1648r,1712r:0)  0@1648r
RegMasks: 176r 672r 944r 1152r 1520r 1744r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzclose: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
  fi#1: size=4, align=4, at location [SP]
  fi#2: size=8, align=8, at location [SP]
Function Live Ins: %X0 in %vreg0, %LR in %vreg12

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %LR
16B		%vreg11<def> = COPY %LR; GPR64:%vreg11
32B		%vreg1<def> = COPY %X0; GPR64:%vreg1
64B		%vreg8<def> = ADRP <ga:@BZ2_bzclose>[TF=1]; GPR64common:%vreg8
80B		%vreg10<def> = ADDXri %vreg8, <ga:@BZ2_bzclose>[TF=34], 0; GPR64sp:%vreg10 GPR64common:%vreg8
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		%X0<def> = COPY %vreg10; GPR64sp:%vreg10
160B		%X1<def> = COPY %vreg11; GPR64:%vreg11
176B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
224B		STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] LD8[FixedStack1](align=4) LD8[FixedStack2] GPR64:%vreg1
240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
256B		STRXui %vreg1, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg1
272B		%vreg7<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg7
288B		%vreg6<def> = LDRXui %vreg7, 0; mem:LD8[%handle] GPR64:%vreg6 GPR64common:%vreg7
304B		STRXui %vreg6, <fi#2>, 0; mem:ST8[FixedStack2] GPR64:%vreg6
320B		%vreg3<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg3
336B		CBNZX %vreg3, <BB#2>; GPR64:%vreg3
	    Successors according to CFG: BB#2 BB#1

352B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
368B		B <BB#10>
	    Successors according to CFG: BB#10

384B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0
400B		%vreg19<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg19
416B		%vreg16<def> = MOVi64imm 5012; GPR64:%vreg16
432B		%vreg17<def> = ADDXrr %vreg19, %vreg16; GPR64common:%vreg17 GPR64:%vreg19,%vreg16
448B		%vreg18<def> = LDRBBui %vreg17, 0; mem:LD1[%writing] GPR32:%vreg18 GPR64common:%vreg17
464B		%vreg14<def> = UBFMWri %vreg18, 0, 7; GPR32:%vreg14,%vreg18
480B		CBZW %vreg14, <BB#6>; GPR32:%vreg14
	    Successors according to CFG: BB#6 BB#3

496B	BB#3: derived from LLVM BB %if.then.1
	    Predecessors according to CFG: BB#2
560B		%vreg29<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg29
576B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
592B		%X0<def> = ADDXri <fi#1>, 0, 0
608B		%X1<def> = COPY %vreg29; GPR64:%vreg29
624B		%W2<def> = COPY %WZR
640B		%X3<def> = COPY %XZR
656B		%X4<def> = COPY %XZR
672B		BL <ga:@BZ2_bzWriteClose>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %W2<imp-use,kill>, %X3<imp-use,kill>, %X4<imp-use,kill>
688B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
704B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
720B		STACKMAP 1, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] LD8[FixedStack1](align=4) LD8[FixedStack2]
736B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
752B		%vreg24<def> = LDRWui <fi#1>, 0; mem:LD4[FixedStack1] GPR32:%vreg24
768B		CBZW %vreg24, <BB#5>; GPR32:%vreg24
	    Successors according to CFG: BB#5 BB#4

784B	BB#4: derived from LLVM BB %if.then.3
	    Predecessors according to CFG: BB#3
832B		%vreg33<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg33
848B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
864B		%X0<def> = COPY %XZR
880B		%X1<def> = COPY %vreg33; GPR64:%vreg33
896B		%W2<def> = MOVi32imm 1
912B		%X3<def> = COPY %XZR
928B		%X4<def> = COPY %XZR
944B		BL <ga:@BZ2_bzWriteClose>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %W2<imp-use,kill>, %X3<imp-use,kill>, %X4<imp-use,kill>
960B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
976B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
992B		STACKMAP 2, 0, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2]
1008B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#5

1024B	BB#5: derived from LLVM BB %if.end.4
	    Predecessors according to CFG: BB#3 BB#4
1040B		B <BB#7>
	    Successors according to CFG: BB#7

1056B	BB#6: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#2
1088B		%vreg22<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg22
1104B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1120B		%X0<def> = ADDXri <fi#1>, 0, 0
1136B		%X1<def> = COPY %vreg22; GPR64:%vreg22
1152B		BL <ga:@BZ2_bzReadClose>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
1168B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1184B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1200B		STACKMAP 3, 0, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2]
1216B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#7

1232B	BB#7: derived from LLVM BB %if.end.5
	    Predecessors according to CFG: BB#6 BB#5
1248B		%vreg36<def> = ADRP <ga:@stdin>[TF=1]; GPR64common:%vreg36
1264B		%vreg37<def> = ADDXri %vreg36, <ga:@stdin>[TF=34], 0; GPR64sp:%vreg37 GPR64common:%vreg36
1280B		%vreg39<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg39
1296B		%vreg38<def> = LDRXui %vreg37, 0; mem:LD8[@stdin] GPR64:%vreg38 GPR64sp:%vreg37
1312B		%XZR<def> = SUBSXrr %vreg39, %vreg38, %NZCV<imp-def>; GPR64:%vreg39,%vreg38
1328B		Bcc 0, <BB#10>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#10 BB#8

1344B	BB#8: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#7
1360B		%vreg42<def> = ADRP <ga:@stdout>[TF=1]; GPR64common:%vreg42
1376B		%vreg43<def> = ADDXri %vreg42, <ga:@stdout>[TF=34], 0; GPR64sp:%vreg43 GPR64common:%vreg42
1392B		%vreg45<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg45
1408B		%vreg44<def> = LDRXui %vreg43, 0; mem:LD8[@stdout] GPR64:%vreg44 GPR64sp:%vreg43
1424B		%XZR<def> = SUBSXrr %vreg45, %vreg44, %NZCV<imp-def>; GPR64:%vreg45,%vreg44
1440B		Bcc 0, <BB#10>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#10 BB#9

1456B	BB#9: derived from LLVM BB %if.then.8
	    Predecessors according to CFG: BB#8
1472B		%vreg48<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg48
1488B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1504B		%X0<def> = COPY %vreg48; GPR64:%vreg48
1520B		BL <ga:@fclose>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
1536B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1552B		%vreg47<def,dead> = COPY %W0; GPR32all:%vreg47
1568B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1584B		STACKMAP 4, 0, %LR<earlyclobber,imp-def,dead>, ...
1600B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#10

1616B	BB#10: derived from LLVM BB %if.end.9
	    Predecessors according to CFG: BB#7 BB#8 BB#9 BB#1
1632B		%vreg49<def> = ADRP <ga:@BZ2_bzclose>[TF=1]; GPR64common:%vreg49
1648B		%vreg51<def> = ADDXri %vreg49, <ga:@BZ2_bzclose>[TF=34], 0; GPR64sp:%vreg51 GPR64common:%vreg49
1696B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1712B		%X0<def> = COPY %vreg51; GPR64sp:%vreg51
1728B		%X1<def> = COPY %vreg11; GPR64:%vreg11
1744B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
1760B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1776B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1792B		STACKMAP 5, 0, %LR<earlyclobber,imp-def,dead>, ...
1808B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1824B		RET_ReallyLR

# End machine code for function BZ2_bzclose.

handleMove 624B -> 584B: %W2<def> = COPY %WZR
     W2:	[584r,672r:1)[896r,944r:0)  0@896r 1@584r
        -->	[584r,672r:1)[896r,944r:0)  0@896r 1@584r
     WZR:	[1312r,1312d:1)[1424r,1424d:0)  0@1424r 1@1312r
        -->	[1312r,1312d:1)[1424r,1424d:0)  0@1424r 1@1312r
handleMove 640B -> 588B: %X3<def> = COPY %XZR
     W3:	[588r,672r:1)[912r,944r:0)  0@912r 1@588r
        -->	[588r,672r:1)[912r,944r:0)  0@912r 1@588r
     WZR:	[1312r,1312d:1)[1424r,1424d:0)  0@1424r 1@1312r
        -->	[1312r,1312d:1)[1424r,1424d:0)  0@1424r 1@1312r
handleMove 912B -> 872B: %X3<def> = COPY %XZR
     W3:	[588r,672r:1)[912r,944r:0)  0@912r 1@588r
        -->	[588r,672r:1)[872r,944r:0)  0@872r 1@588r
     WZR:	[1312r,1312d:1)[1424r,1424d:0)  0@1424r 1@1312r
        -->	[1312r,1312d:1)[1424r,1424d:0)  0@1424r 1@1312r
handleMove 880B -> 904B: %X1<def> = COPY %vreg33; GPR64:%vreg33
     W1:	[160r,176r:4)[608r,672r:2)[904r,944r:1)[1136r,1152r:3)[1728r,1744r:0)  0@1728r 1@904r 2@608r 3@1136r 4@160r
        -->	[160r,176r:4)[608r,672r:2)[904r,944r:1)[1136r,1152r:3)[1728r,1744r:0)  0@1728r 1@904r 2@608r 3@1136r 4@160r
     %vreg33:	[832r,880r:0)  0@832r
        -->	[832r,904r:0)  0@832r
********** GREEDY REGISTER ALLOCATION **********
********** Function: BZ2_bzclose
********** INTERVALS **********
W30 [0B,16r:0)[176r,176d:12)[224e,224d:4)[672r,672d:10)[720e,720d:3)[944r,944d:9)[992e,992d:2)[1152r,1152d:11)[1200e,1200d:1)[1520r,1520d:7)[1584e,1584d:8)[1744r,1744d:5)[1792e,1792d:6)  0@0B-phi 1@1200e 2@992e 3@720e 4@224e 5@1744r 6@1792e 7@1520r 8@1584e 9@944r 10@672r 11@1152r 12@176r
WZR [1312r,1312d:1)[1424r,1424d:0)  0@1424r 1@1312r
W0 [0B,32r:0)[144r,176r:7)[592r,672r:5)[864r,944r:4)[1120r,1152r:6)[1504r,1520r:3)[1520r,1552r:1)[1712r,1744r:2)  0@0B-phi 1@1520r 2@1712r 3@1504r 4@864r 5@592r 6@1120r 7@144r
W1 [160r,176r:4)[608r,672r:2)[904r,944r:1)[1136r,1152r:3)[1728r,1744r:0)  0@1728r 1@904r 2@608r 3@1136r 4@160r
W2 [584r,672r:1)[896r,944r:0)  0@896r 1@584r
W3 [588r,672r:1)[872r,944r:0)  0@872r 1@588r
%vreg1 [32r,256r:0)  0@32r
%vreg3 [320r,336r:0)  0@320r
%vreg6 [288r,304r:0)  0@288r
%vreg7 [272r,288r:0)  0@272r
%vreg8 [64r,80r:0)  0@64r
%vreg10 [80r,144r:0)  0@80r
%vreg11 [16r,1728r:0)  0@16r
%vreg14 [464r,480r:0)  0@464r
%vreg16 [416r,432r:0)  0@416r
%vreg17 [432r,448r:0)  0@432r
%vreg18 [448r,464r:0)  0@448r
%vreg19 [400r,432r:0)  0@400r
%vreg22 [1088r,1136r:0)  0@1088r
%vreg24 [752r,768r:0)  0@752r
%vreg29 [560r,608r:0)  0@560r
%vreg33 [832r,904r:0)  0@832r
%vreg36 [1248r,1264r:0)  0@1248r
%vreg37 [1264r,1296r:0)  0@1264r
%vreg38 [1296r,1312r:0)  0@1296r
%vreg39 [1280r,1312r:0)  0@1280r
%vreg42 [1360r,1376r:0)  0@1360r
%vreg43 [1376r,1408r:0)  0@1376r
%vreg44 [1408r,1424r:0)  0@1408r
%vreg45 [1392r,1424r:0)  0@1392r
%vreg47 [1552r,1552d:0)  0@1552r
%vreg48 [1472r,1504r:0)  0@1472r
%vreg49 [1632r,1648r:0)  0@1632r
%vreg51 [1648r,1712r:0)  0@1648r
RegMasks: 176r 672r 944r 1152r 1520r 1744r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzclose: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
  fi#1: size=4, align=4, at location [SP]
  fi#2: size=8, align=8, at location [SP]
Function Live Ins: %X0 in %vreg0, %LR in %vreg12

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %LR
16B		%vreg11<def> = COPY %LR; GPR64:%vreg11
32B		%vreg1<def> = COPY %X0; GPR64:%vreg1
64B		%vreg8<def> = ADRP <ga:@BZ2_bzclose>[TF=1]; GPR64common:%vreg8
80B		%vreg10<def> = ADDXri %vreg8, <ga:@BZ2_bzclose>[TF=34], 0; GPR64sp:%vreg10 GPR64common:%vreg8
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		%X0<def> = COPY %vreg10; GPR64sp:%vreg10
160B		%X1<def> = COPY %vreg11; GPR64:%vreg11
176B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
224B		STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] LD8[FixedStack1](align=4) LD8[FixedStack2] GPR64:%vreg1
240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
256B		STRXui %vreg1, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg1
272B		%vreg7<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg7
288B		%vreg6<def> = LDRXui %vreg7, 0; mem:LD8[%handle] GPR64:%vreg6 GPR64common:%vreg7
304B		STRXui %vreg6, <fi#2>, 0; mem:ST8[FixedStack2] GPR64:%vreg6
320B		%vreg3<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg3
336B		CBNZX %vreg3, <BB#2>; GPR64:%vreg3
	    Successors according to CFG: BB#2 BB#1

352B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
368B		B <BB#10>
	    Successors according to CFG: BB#10

384B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0
400B		%vreg19<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg19
416B		%vreg16<def> = MOVi64imm 5012; GPR64:%vreg16
432B		%vreg17<def> = ADDXrr %vreg19, %vreg16; GPR64common:%vreg17 GPR64:%vreg19,%vreg16
448B		%vreg18<def> = LDRBBui %vreg17, 0; mem:LD1[%writing] GPR32:%vreg18 GPR64common:%vreg17
464B		%vreg14<def> = UBFMWri %vreg18, 0, 7; GPR32:%vreg14,%vreg18
480B		CBZW %vreg14, <BB#6>; GPR32:%vreg14
	    Successors according to CFG: BB#6 BB#3

496B	BB#3: derived from LLVM BB %if.then.1
	    Predecessors according to CFG: BB#2
560B		%vreg29<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg29
576B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
584B		%W2<def> = COPY %WZR
588B		%X3<def> = COPY %XZR
592B		%X0<def> = ADDXri <fi#1>, 0, 0
608B		%X1<def> = COPY %vreg29; GPR64:%vreg29
656B		%X4<def> = COPY %XZR
672B		BL <ga:@BZ2_bzWriteClose>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %W2<imp-use>, %X3<imp-use>, %X4<imp-use,kill>
688B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
704B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
720B		STACKMAP 1, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] LD8[FixedStack1](align=4) LD8[FixedStack2]
736B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
752B		%vreg24<def> = LDRWui <fi#1>, 0; mem:LD4[FixedStack1] GPR32:%vreg24
768B		CBZW %vreg24, <BB#5>; GPR32:%vreg24
	    Successors according to CFG: BB#5 BB#4

784B	BB#4: derived from LLVM BB %if.then.3
	    Predecessors according to CFG: BB#3
832B		%vreg33<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg33
848B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
864B		%X0<def> = COPY %XZR
872B		%X3<def> = COPY %XZR
896B		%W2<def> = MOVi32imm 1
904B		%X1<def> = COPY %vreg33; GPR64:%vreg33
928B		%X4<def> = COPY %XZR
944B		BL <ga:@BZ2_bzWriteClose>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %W2<imp-use>, %X3<imp-use>, %X4<imp-use,kill>
960B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
976B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
992B		STACKMAP 2, 0, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2]
1008B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#5

1024B	BB#5: derived from LLVM BB %if.end.4
	    Predecessors according to CFG: BB#3 BB#4
1040B		B <BB#7>
	    Successors according to CFG: BB#7

1056B	BB#6: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#2
1088B		%vreg22<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg22
1104B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1120B		%X0<def> = ADDXri <fi#1>, 0, 0
1136B		%X1<def> = COPY %vreg22; GPR64:%vreg22
1152B		BL <ga:@BZ2_bzReadClose>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
1168B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1184B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1200B		STACKMAP 3, 0, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2]
1216B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#7

1232B	BB#7: derived from LLVM BB %if.end.5
	    Predecessors according to CFG: BB#6 BB#5
1248B		%vreg36<def> = ADRP <ga:@stdin>[TF=1]; GPR64common:%vreg36
1264B		%vreg37<def> = ADDXri %vreg36, <ga:@stdin>[TF=34], 0; GPR64sp:%vreg37 GPR64common:%vreg36
1280B		%vreg39<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg39
1296B		%vreg38<def> = LDRXui %vreg37, 0; mem:LD8[@stdin] GPR64:%vreg38 GPR64sp:%vreg37
1312B		%XZR<def> = SUBSXrr %vreg39, %vreg38, %NZCV<imp-def>; GPR64:%vreg39,%vreg38
1328B		Bcc 0, <BB#10>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#10 BB#8

1344B	BB#8: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#7
1360B		%vreg42<def> = ADRP <ga:@stdout>[TF=1]; GPR64common:%vreg42
1376B		%vreg43<def> = ADDXri %vreg42, <ga:@stdout>[TF=34], 0; GPR64sp:%vreg43 GPR64common:%vreg42
1392B		%vreg45<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg45
1408B		%vreg44<def> = LDRXui %vreg43, 0; mem:LD8[@stdout] GPR64:%vreg44 GPR64sp:%vreg43
1424B		%XZR<def> = SUBSXrr %vreg45, %vreg44, %NZCV<imp-def>; GPR64:%vreg45,%vreg44
1440B		Bcc 0, <BB#10>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#10 BB#9

1456B	BB#9: derived from LLVM BB %if.then.8
	    Predecessors according to CFG: BB#8
1472B		%vreg48<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg48
1488B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1504B		%X0<def> = COPY %vreg48; GPR64:%vreg48
1520B		BL <ga:@fclose>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
1536B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1552B		%vreg47<def,dead> = COPY %W0; GPR32all:%vreg47
1568B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1584B		STACKMAP 4, 0, %LR<earlyclobber,imp-def,dead>, ...
1600B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#10

1616B	BB#10: derived from LLVM BB %if.end.9
	    Predecessors according to CFG: BB#7 BB#8 BB#9 BB#1
1632B		%vreg49<def> = ADRP <ga:@BZ2_bzclose>[TF=1]; GPR64common:%vreg49
1648B		%vreg51<def> = ADDXri %vreg49, <ga:@BZ2_bzclose>[TF=34], 0; GPR64sp:%vreg51 GPR64common:%vreg49
1696B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1712B		%X0<def> = COPY %vreg51; GPR64sp:%vreg51
1728B		%X1<def> = COPY %vreg11; GPR64:%vreg11
1744B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
1760B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1776B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1792B		STACKMAP 5, 0, %LR<earlyclobber,imp-def,dead>, ...
1808B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1824B		RET_ReallyLR

# End machine code for function BZ2_bzclose.


selectOrSplit GPR64:%vreg11 [16r,1728r:0)  0@16r w=1.434659e-03
hints: %X1
missed hint %X1
assigning %vreg11 to %X19: W19 [16r,1728r:0)  0@16r

selectOrSplit GPR64:%vreg1 [32r,256r:0)  0@32r w=4.855769e-03
hints: %X0
missed hint %X0
assigning %vreg1 to %X20: W20 [32r,256r:0)  0@32r

selectOrSplit GPR64sp:%vreg10 [80r,144r:0)  0@80r w=4.353448e-03
hints: %X0
assigning %vreg10 to %X0: W0 [80r,144r:0)  0@80r

selectOrSplit GPR64:%vreg29 [560r,608r:0)  0@560r w=1.073555e-03
hints: %X1
assigning %vreg29 to %X1: W1 [560r,608r:0)  0@560r

selectOrSplit GPR64:%vreg33 [832r,904r:0)  0@832r w=5.434491e-04
hints: %X1
assigning %vreg33 to %X1: W1 [832r,904r:0)  0@832r

selectOrSplit GPR64:%vreg22 [1088r,1136r:0)  0@1088r w=1.073555e-03
hints: %X1
assigning %vreg22 to %X1: W1 [1088r,1136r:0)  0@1088r

selectOrSplit GPR64:%vreg48 [1472r,1504r:0)  0@1472r w=5.937684e-04
hints: %X0
assigning %vreg48 to %X0: W0 [1472r,1504r:0)  0@1472r

selectOrSplit GPR32all:%vreg47 [1552r,1552d:0)  0@1552r w=inf
hints: %W0
assigning %vreg47 to %W0: W0 [1552r,1552d:0)  0@1552r

selectOrSplit GPR64sp:%vreg51 [1648r,1712r:0)  0@1648r w=4.353448e-03
hints: %X0
assigning %vreg51 to %X0: W0 [1648r,1712r:0)  0@1648r

selectOrSplit GPR64common:%vreg8 [64r,80r:0)  0@64r w=inf
assigning %vreg8 to %X8: W8 [64r,80r:0)  0@64r

selectOrSplit GPR64common:%vreg7 [272r,288r:0)  0@272r w=inf
assigning %vreg7 to %X8: W8 [272r,288r:0)  0@272r

selectOrSplit GPR64:%vreg6 [288r,304r:0)  0@288r w=inf
assigning %vreg6 to %X8: W8 [288r,304r:0)  0@288r

selectOrSplit GPR64:%vreg3 [320r,336r:0)  0@320r w=inf
assigning %vreg3 to %X8: W8 [320r,336r:0)  0@320r

selectOrSplit GPR64:%vreg19 [400r,432r:0)  0@400r w=2.278072e-03
assigning %vreg19 to %X8: W8 [400r,432r:0)  0@400r

selectOrSplit GPR64:%vreg16 [416r,432r:0)  0@416r w=inf
assigning %vreg16 to %X9: W9 [416r,432r:0)  0@416r

selectOrSplit GPR64common:%vreg17 [432r,448r:0)  0@432r w=inf
assigning %vreg17 to %X8: W8 [432r,448r:0)  0@432r

selectOrSplit GPR32:%vreg18 [448r,464r:0)  0@448r w=inf
assigning %vreg18 to %W8: W8 [448r,464r:0)  0@448r

selectOrSplit GPR32:%vreg14 [464r,480r:0)  0@464r w=inf
assigning %vreg14 to %W8: W8 [464r,480r:0)  0@464r

selectOrSplit GPR32:%vreg24 [752r,768r:0)  0@752r w=inf
assigning %vreg24 to %W8: W8 [752r,768r:0)  0@752r

selectOrSplit GPR64common:%vreg36 [1248r,1264r:0)  0@1248r w=inf
assigning %vreg36 to %X8: W8 [1248r,1264r:0)  0@1248r

selectOrSplit GPR64sp:%vreg37 [1264r,1296r:0)  0@1264r w=2.278072e-03
assigning %vreg37 to %X8: W8 [1264r,1296r:0)  0@1264r

selectOrSplit GPR64:%vreg39 [1280r,1312r:0)  0@1280r w=2.278072e-03
assigning %vreg39 to %X9: W9 [1280r,1312r:0)  0@1280r

selectOrSplit GPR64:%vreg38 [1296r,1312r:0)  0@1296r w=inf
assigning %vreg38 to %X8: W8 [1296r,1312r:0)  0@1296r

selectOrSplit GPR64common:%vreg42 [1360r,1376r:0)  0@1360r w=inf
assigning %vreg42 to %X8: W8 [1360r,1376r:0)  0@1360r

selectOrSplit GPR64sp:%vreg43 [1376r,1408r:0)  0@1376r w=1.102293e-03
assigning %vreg43 to %X8: W8 [1376r,1408r:0)  0@1376r

selectOrSplit GPR64:%vreg45 [1392r,1424r:0)  0@1392r w=1.102293e-03
assigning %vreg45 to %X9: W9 [1392r,1424r:0)  0@1392r

selectOrSplit GPR64:%vreg44 [1408r,1424r:0)  0@1408r w=inf
assigning %vreg44 to %X8: W8 [1408r,1424r:0)  0@1408r

selectOrSplit GPR64common:%vreg49 [1632r,1648r:0)  0@1632r w=inf
assigning %vreg49 to %X8: W8 [1632r,1648r:0)  0@1632r

********** STACK TRANSFORMATION METADATA **********
********** Function: BZ2_bzclose
********** REGISTER MAP **********
[%vreg1 -> %X20] GPR64
[%vreg3 -> %X8] GPR64
[%vreg6 -> %X8] GPR64
[%vreg7 -> %X8] GPR64common
[%vreg8 -> %X8] GPR64common
[%vreg10 -> %X0] GPR64sp
[%vreg11 -> %X19] GPR64
[%vreg14 -> %W8] GPR32
[%vreg16 -> %X9] GPR64
[%vreg17 -> %X8] GPR64common
[%vreg18 -> %W8] GPR32
[%vreg19 -> %X8] GPR64
[%vreg22 -> %X1] GPR64
[%vreg24 -> %W8] GPR32
[%vreg29 -> %X1] GPR64
[%vreg33 -> %X1] GPR64
[%vreg36 -> %X8] GPR64common
[%vreg37 -> %X8] GPR64sp
[%vreg38 -> %X8] GPR64
[%vreg39 -> %X9] GPR64
[%vreg42 -> %X8] GPR64common
[%vreg43 -> %X8] GPR64sp
[%vreg44 -> %X8] GPR64
[%vreg45 -> %X9] GPR64
[%vreg47 -> %W0] GPR32all
[%vreg48 -> %X0] GPR64
[%vreg49 -> %X8] GPR64common
[%vreg51 -> %X0] GPR64sp


Stackmap 0:
  STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] LD8[FixedStack1](align=4) LD8[FixedStack2] GPR64:%vreg1

i8* %b: in register %X20 (vreg 1)
i8** %b.addr: in stack slot 0 (size: 8)
i32* %bzerr: in stack slot 1 (size: 4)
%struct._IO_FILE** %fp: in stack slot 2 (size: 8)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] LD8[FixedStack1](align=4) LD8[FixedStack2]

i8** %b.addr: in stack slot 0 (size: 8)
i32* %bzerr: in stack slot 1 (size: 4)
%struct._IO_FILE** %fp: in stack slot 2 (size: 8)

Duplicate operand locations:


Stackmap 2:
  STACKMAP 2, 0, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2]

%struct._IO_FILE** %fp: in stack slot 2 (size: 8)

Duplicate operand locations:


Stackmap 3:
  STACKMAP 3, 0, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2]

%struct._IO_FILE** %fp: in stack slot 2 (size: 8)

Duplicate operand locations:


Stackmap 4:
  STACKMAP 4, 0, %LR<earlyclobber,imp-def,dead>, ...


Duplicate operand locations:


Stackmap 5:
  STACKMAP 5, 0, %LR<earlyclobber,imp-def,dead>, ...


Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] LD8[FixedStack1](align=4) LD8[FixedStack2] GPR64:%vreg1
  -> Call instruction SlotIndex 176B, searching vregs 0 -> 53 and stack slots 0 -> 3
    + vreg11 is live in register but not in stackmap
      Defining instruction: %vreg11<def> = COPY %LR; GPR64:%vreg11
      Value: generated value, 1 instruction(s)

  STACKMAP 1, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] LD8[FixedStack1](align=4) LD8[FixedStack2]
  -> Call instruction SlotIndex 672B, searching vregs 0 -> 53 and stack slots 0 -> 3
    + vreg11 is live in register but not in stackmap
      Defining instruction: %vreg11<def> = COPY %LR; GPR64:%vreg11
      Value: generated value, 1 instruction(s)

  STACKMAP 2, 0, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2]
  -> Call instruction SlotIndex 944B, searching vregs 0 -> 53 and stack slots 0 -> 3
    + vreg11 is live in register but not in stackmap
      Defining instruction: %vreg11<def> = COPY %LR; GPR64:%vreg11
      Value: generated value, 1 instruction(s)

  STACKMAP 3, 0, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2]
  -> Call instruction SlotIndex 1152B, searching vregs 0 -> 53 and stack slots 0 -> 3
    + vreg11 is live in register but not in stackmap
      Defining instruction: %vreg11<def> = COPY %LR; GPR64:%vreg11
      Value: generated value, 1 instruction(s)

  STACKMAP 4, 0, %LR<earlyclobber,imp-def,dead>, ...
  -> Call instruction SlotIndex 1520B, searching vregs 0 -> 53 and stack slots 0 -> 3
    + vreg11 is live in register but not in stackmap
      Defining instruction: %vreg11<def> = COPY %LR; GPR64:%vreg11
      Value: generated value, 1 instruction(s)

  STACKMAP 5, 0, %LR<earlyclobber,imp-def,dead>, ...
  -> Call instruction SlotIndex 1744B, searching vregs 0 -> 53 and stack slots 0 -> 3

********** REWRITE VIRTUAL REGISTERS **********
********** Function: BZ2_bzclose
********** REGISTER MAP **********
[%vreg1 -> %X20] GPR64
[%vreg3 -> %X8] GPR64
[%vreg6 -> %X8] GPR64
[%vreg7 -> %X8] GPR64common
[%vreg8 -> %X8] GPR64common
[%vreg10 -> %X0] GPR64sp
[%vreg11 -> %X19] GPR64
[%vreg14 -> %W8] GPR32
[%vreg16 -> %X9] GPR64
[%vreg17 -> %X8] GPR64common
[%vreg18 -> %W8] GPR32
[%vreg19 -> %X8] GPR64
[%vreg22 -> %X1] GPR64
[%vreg24 -> %W8] GPR32
[%vreg29 -> %X1] GPR64
[%vreg33 -> %X1] GPR64
[%vreg36 -> %X8] GPR64common
[%vreg37 -> %X8] GPR64sp
[%vreg38 -> %X8] GPR64
[%vreg39 -> %X9] GPR64
[%vreg42 -> %X8] GPR64common
[%vreg43 -> %X8] GPR64sp
[%vreg44 -> %X8] GPR64
[%vreg45 -> %X9] GPR64
[%vreg47 -> %W0] GPR32all
[%vreg48 -> %X0] GPR64
[%vreg49 -> %X8] GPR64common
[%vreg51 -> %X0] GPR64sp

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %LR %X0
16B		%vreg11<def> = COPY %LR; GPR64:%vreg11
32B		%vreg1<def> = COPY %X0; GPR64:%vreg1
64B		%vreg8<def> = ADRP <ga:@BZ2_bzclose>[TF=1]; GPR64common:%vreg8
80B		%vreg10<def> = ADDXri %vreg8<kill>, <ga:@BZ2_bzclose>[TF=34], 0; GPR64sp:%vreg10 GPR64common:%vreg8
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		%X0<def> = COPY %vreg10<kill>; GPR64sp:%vreg10
160B		%X1<def> = COPY %vreg11; GPR64:%vreg11
176B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
224B		STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] LD8[FixedStack1](align=4) LD8[FixedStack2] GPR64:%vreg1
240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
256B		STRXui %vreg1<kill>, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg1
272B		%vreg7<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg7
288B		%vreg6<def> = LDRXui %vreg7<kill>, 0; mem:LD8[%handle] GPR64:%vreg6 GPR64common:%vreg7
304B		STRXui %vreg6<kill>, <fi#2>, 0; mem:ST8[FixedStack2] GPR64:%vreg6
320B		%vreg3<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg3
336B		CBNZX %vreg3<kill>, <BB#2>; GPR64:%vreg3
	    Successors according to CFG: BB#2 BB#1
> %X19<def> = COPY %LR
> %X20<def> = COPY %X0
> %X8<def> = ADRP <ga:@BZ2_bzclose>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@BZ2_bzclose>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19
> BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 0, 0, %X20, 0, <fi#0>, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] LD8[FixedStack1](align=4) LD8[FixedStack2]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRXui %X20<kill>, <fi#0>, 0; mem:ST8[FixedStack0]
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %X8<def> = LDRXui %X8<kill>, 0; mem:LD8[%handle]
> STRXui %X8<kill>, <fi#2>, 0; mem:ST8[FixedStack2]
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> CBNZX %X8<kill>, <BB#2>
352B	BB#1: derived from LLVM BB %if.then
	    Live Ins: %X19
	    Predecessors according to CFG: BB#0
368B		B <BB#10>
	    Successors according to CFG: BB#10
> B <BB#10>
384B	BB#2: derived from LLVM BB %if.end
	    Live Ins: %X19
	    Predecessors according to CFG: BB#0
400B		%vreg19<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg19
416B		%vreg16<def> = MOVi64imm 5012; GPR64:%vreg16
432B		%vreg17<def> = ADDXrr %vreg19<kill>, %vreg16<kill>; GPR64common:%vreg17 GPR64:%vreg19,%vreg16
448B		%vreg18<def> = LDRBBui %vreg17<kill>, 0; mem:LD1[%writing] GPR32:%vreg18 GPR64common:%vreg17
464B		%vreg14<def> = UBFMWri %vreg18<kill>, 0, 7; GPR32:%vreg14,%vreg18
480B		CBZW %vreg14<kill>, <BB#6>; GPR32:%vreg14
	    Successors according to CFG: BB#6 BB#3
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %X9<def> = MOVi64imm 5012
> %X8<def> = ADDXrr %X8<kill>, %X9<kill>
> %W8<def> = LDRBBui %X8<kill>, 0; mem:LD1[%writing]
> %W8<def> = UBFMWri %W8<kill>, 0, 7
> CBZW %W8<kill>, <BB#6>
496B	BB#3: derived from LLVM BB %if.then.1
	    Live Ins: %X19
	    Predecessors according to CFG: BB#2
560B		%vreg29<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg29
576B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
584B		%W2<def> = COPY %WZR
588B		%X3<def> = COPY %XZR
592B		%X0<def> = ADDXri <fi#1>, 0, 0
608B		%X1<def> = COPY %vreg29<kill>; GPR64:%vreg29
656B		%X4<def> = COPY %XZR
672B		BL <ga:@BZ2_bzWriteClose>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %W2<imp-use>, %X3<imp-use>, %X4<imp-use,kill>
688B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
704B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
720B		STACKMAP 1, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] LD8[FixedStack1](align=4) LD8[FixedStack2]
736B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
752B		%vreg24<def> = LDRWui <fi#1>, 0; mem:LD4[FixedStack1] GPR32:%vreg24
768B		CBZW %vreg24<kill>, <BB#5>; GPR32:%vreg24
	    Successors according to CFG: BB#5 BB#4
> %X1<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %W2<def> = COPY %WZR
> %X3<def> = COPY %XZR
> %X0<def> = ADDXri <fi#1>, 0, 0
> %X1<def> = COPY %X1<kill>
Deleting identity copy.
> %X4<def> = COPY %XZR
> BL <ga:@BZ2_bzWriteClose>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %W2<imp-use>, %X3<imp-use>, %X4<imp-use,kill>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 1, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] LD8[FixedStack1](align=4) LD8[FixedStack2]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W8<def> = LDRWui <fi#1>, 0; mem:LD4[FixedStack1]
> CBZW %W8<kill>, <BB#5>
784B	BB#4: derived from LLVM BB %if.then.3
	    Live Ins: %X19
	    Predecessors according to CFG: BB#3
832B		%vreg33<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg33
848B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
864B		%X0<def> = COPY %XZR
872B		%X3<def> = COPY %XZR
896B		%W2<def> = MOVi32imm 1
904B		%X1<def> = COPY %vreg33<kill>; GPR64:%vreg33
928B		%X4<def> = COPY %XZR
944B		BL <ga:@BZ2_bzWriteClose>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %W2<imp-use>, %X3<imp-use>, %X4<imp-use,kill>
960B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
976B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
992B		STACKMAP 2, 0, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2]
1008B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#5
> %X1<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %XZR
> %X3<def> = COPY %XZR
> %W2<def> = MOVi32imm 1
> %X1<def> = COPY %X1<kill>
Deleting identity copy.
> %X4<def> = COPY %XZR
> BL <ga:@BZ2_bzWriteClose>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>, %W2<imp-use>, %X3<imp-use>, %X4<imp-use,kill>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 2, 0, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1024B	BB#5: derived from LLVM BB %if.end.4
	    Live Ins: %X19
	    Predecessors according to CFG: BB#3 BB#4
1040B		B <BB#7>
	    Successors according to CFG: BB#7
> B <BB#7>
1056B	BB#6: derived from LLVM BB %if.else
	    Live Ins: %X19
	    Predecessors according to CFG: BB#2
1088B		%vreg22<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg22
1104B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1120B		%X0<def> = ADDXri <fi#1>, 0, 0
1136B		%X1<def> = COPY %vreg22<kill>; GPR64:%vreg22
1152B		BL <ga:@BZ2_bzReadClose>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
1168B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1184B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1200B		STACKMAP 3, 0, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2]
1216B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#7
> %X1<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = ADDXri <fi#1>, 0, 0
> %X1<def> = COPY %X1<kill>
Deleting identity copy.
> BL <ga:@BZ2_bzReadClose>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 3, 0, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1232B	BB#7: derived from LLVM BB %if.end.5
	    Live Ins: %X19
	    Predecessors according to CFG: BB#6 BB#5
1248B		%vreg36<def> = ADRP <ga:@stdin>[TF=1]; GPR64common:%vreg36
1264B		%vreg37<def> = ADDXri %vreg36<kill>, <ga:@stdin>[TF=34], 0; GPR64sp:%vreg37 GPR64common:%vreg36
1280B		%vreg39<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg39
1296B		%vreg38<def> = LDRXui %vreg37<kill>, 0; mem:LD8[@stdin] GPR64:%vreg38 GPR64sp:%vreg37
1312B		%XZR<def> = SUBSXrr %vreg39<kill>, %vreg38<kill>, %NZCV<imp-def>; GPR64:%vreg39,%vreg38
1328B		Bcc 0, <BB#10>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#10 BB#8
> %X8<def> = ADRP <ga:@stdin>[TF=1]
> %X8<def> = ADDXri %X8<kill>, <ga:@stdin>[TF=34], 0
> %X9<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2]
> %X8<def> = LDRXui %X8<kill>, 0; mem:LD8[@stdin]
> %XZR<def> = SUBSXrr %X9<kill>, %X8<kill>, %NZCV<imp-def>
> Bcc 0, <BB#10>, %NZCV<imp-use,kill>
1344B	BB#8: derived from LLVM BB %land.lhs.true
	    Live Ins: %X19
	    Predecessors according to CFG: BB#7
1360B		%vreg42<def> = ADRP <ga:@stdout>[TF=1]; GPR64common:%vreg42
1376B		%vreg43<def> = ADDXri %vreg42<kill>, <ga:@stdout>[TF=34], 0; GPR64sp:%vreg43 GPR64common:%vreg42
1392B		%vreg45<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg45
1408B		%vreg44<def> = LDRXui %vreg43<kill>, 0; mem:LD8[@stdout] GPR64:%vreg44 GPR64sp:%vreg43
1424B		%XZR<def> = SUBSXrr %vreg45<kill>, %vreg44<kill>, %NZCV<imp-def>; GPR64:%vreg45,%vreg44
1440B		Bcc 0, <BB#10>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#10 BB#9
> %X8<def> = ADRP <ga:@stdout>[TF=1]
> %X8<def> = ADDXri %X8<kill>, <ga:@stdout>[TF=34], 0
> %X9<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2]
> %X8<def> = LDRXui %X8<kill>, 0; mem:LD8[@stdout]
> %XZR<def> = SUBSXrr %X9<kill>, %X8<kill>, %NZCV<imp-def>
> Bcc 0, <BB#10>, %NZCV<imp-use,kill>
1456B	BB#9: derived from LLVM BB %if.then.8
	    Live Ins: %X19
	    Predecessors according to CFG: BB#8
1472B		%vreg48<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2] GPR64:%vreg48
1488B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1504B		%X0<def> = COPY %vreg48<kill>; GPR64:%vreg48
1520B		BL <ga:@fclose>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
1536B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1552B		%vreg47<def,dead> = COPY %W0; GPR32all:%vreg47
1568B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1584B		STACKMAP 4, 0, %LR<earlyclobber,imp-def,dead>, ...
1600B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#10
> %X0<def> = LDRXui <fi#2>, 0; mem:LD8[FixedStack2]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BL <ga:@fclose>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %W0<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def,dead> = COPY %W0
Deleting identity copy.
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 4, 0, %LR<earlyclobber,imp-def,dead>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1616B	BB#10: derived from LLVM BB %if.end.9
	    Live Ins: %X19
	    Predecessors according to CFG: BB#7 BB#8 BB#9 BB#1
1632B		%vreg49<def> = ADRP <ga:@BZ2_bzclose>[TF=1]; GPR64common:%vreg49
1648B		%vreg51<def> = ADDXri %vreg49<kill>, <ga:@BZ2_bzclose>[TF=34], 0; GPR64sp:%vreg51 GPR64common:%vreg49
1696B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1712B		%X0<def> = COPY %vreg51<kill>; GPR64sp:%vreg51
1728B		%X1<def> = COPY %vreg11<kill>; GPR64:%vreg11
1744B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
1760B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1776B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1792B		STACKMAP 5, 0, %LR<earlyclobber,imp-def,dead>, ...
1808B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1824B		RET_ReallyLR
> %X8<def> = ADRP <ga:@BZ2_bzclose>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@BZ2_bzclose>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19<kill>
> BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 5, 0, %LR<earlyclobber,imp-def,dead>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> RET_ReallyLR
Computing live-in reg-units in ABI blocks.
0B	BB#0 W0#0 W1#0 W30#0
Created 3 new intervals.
********** INTERVALS **********
W30 [0B,16r:0)[208r,208d:4)[256e,256d:1)[800r,800d:2)[848e,848d:3)  0@0B-phi 1@256e 2@800r 3@848e 4@208r
W0 [0B,48r:0)[176r,208r:3)[768r,800r:1)[880r,896r:2)  0@0B-phi 1@768r 2@880r 3@176r
W1 [0B,32r:0)[192r,208r:2)[784r,800r:1)  0@0B-phi 1@784r 2@192r
%vreg0 [48r,64r:0)  0@48r
%vreg1 [64r,288r:0)  0@64r
%vreg2 [32r,80r:0)  0@32r
%vreg3 [80r,304r:0)  0@80r
%vreg5 [368r,384r:0)  0@368r
%vreg8 [336r,352r:0)  0@336r
%vreg9 [320r,336r:0)  0@320r
%vreg10 [96r,112r:0)  0@96r
%vreg11 [112r,128r:0)  0@112r
%vreg12 [128r,176r:0)  0@128r
%vreg13 [144r,192r:0)  0@144r
%vreg14 [16r,736r:0)  0@16r
%vreg16 [464r,480r:0)  0@464r
%vreg17 [480r,496r:0)  0@480r
%vreg18 [496r,768r:0)  0@496r
%vreg19 [736r,784r:0)  0@736r
%vreg21 [720r,880r:0)  0@720r
%vreg22 [512r,528r:0)  0@512r
%vreg23 [528r,704r:0)  0@528r
%vreg25 [672r,688r:0)  0@672r
%vreg26 [688r,704r:0)  0@688r
%vreg27 [704r,720r:0)  0@704r
%vreg29 [640r,656r:0)  0@640r
%vreg30 [656r,688r:0)  0@656r
%vreg32 [544r,624r:0)  0@544r
%vreg33 [624r,640r:0)  0@624r
%vreg34 [608r,624r:0)  0@608r
%vreg37 [576r,592r:0)  0@576r
%vreg38 [560r,592r:0)  0@560r
RegMasks: 208r 800r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzerror: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=4, align=4, at location [SP]
Function Live Ins: %X0 in %vreg0, %X1 in %vreg2, %LR in %vreg14

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %X1 %LR
16B		%vreg14<def> = COPY %LR; GPR64:%vreg14
32B		%vreg2<def> = COPY %X1; GPR64:%vreg2
48B		%vreg0<def> = COPY %X0; GPR64:%vreg0
64B		%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
80B		%vreg3<def> = COPY %vreg2; GPR64:%vreg3,%vreg2
96B		%vreg10<def> = ADRP <ga:@BZ2_bzerror>[TF=1]; GPR64common:%vreg10
112B		%vreg11<def> = ADDXri %vreg10, <ga:@BZ2_bzerror>[TF=34], 0; GPR64sp:%vreg11 GPR64common:%vreg10
128B		%vreg12<def> = COPY %vreg11; GPR64all:%vreg12 GPR64sp:%vreg11
144B		%vreg13<def> = COPY %vreg14; GPR64all:%vreg13 GPR64:%vreg14
160B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
176B		%X0<def> = COPY %vreg12; GPR64all:%vreg12
192B		%X1<def> = COPY %vreg13; GPR64all:%vreg13
208B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
224B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
240B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
256B		STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#2>, 0, %vreg3, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] LD8[FixedStack2](align=4) LD8[FixedStack1] GPR64:%vreg1,%vreg3
272B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
288B		STRXui %vreg1, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg1
304B		STRXui %vreg3, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg3
320B		%vreg9<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg9
336B		%vreg8<def> = LDRWui %vreg9, 1274; mem:LD4[%lastErr] GPR32:%vreg8 GPR64common:%vreg9
352B		STRWui %vreg8, <fi#2>, 0; mem:ST4[FixedStack2] GPR32:%vreg8
368B		%vreg5<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32common:%vreg5
384B		%WZR<def> = SUBSWri %vreg5, 0, 0, %NZCV<imp-def>; GPR32common:%vreg5
400B		Bcc 13, <BB#2>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

416B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
432B		STRWui %WZR, <fi#2>, 0; mem:ST4[FixedStack2]
	    Successors according to CFG: BB#2

448B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#1
464B		%vreg16<def> = ADRP <ga:@BZ2_bzerror>[TF=1]; GPR64common:%vreg16
480B		%vreg17<def> = ADDXri %vreg16, <ga:@BZ2_bzerror>[TF=34], 0; GPR64sp:%vreg17 GPR64common:%vreg16
496B		%vreg18<def> = COPY %vreg17; GPR64all:%vreg18 GPR64sp:%vreg17
512B		%vreg22<def> = ADRP <ga:@bzerrorstrings>[TF=1]; GPR64common:%vreg22
528B		%vreg23<def> = ADDXri %vreg22, <ga:@bzerrorstrings>[TF=34], 0; GPR64common:%vreg23,%vreg22
544B		%vreg32<def> = MOVi32imm 4294967295; GPR32:%vreg32
560B		%vreg38<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg38
576B		%vreg37<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg37
592B		STRWui %vreg38, %vreg37, 0; mem:ST4[%5] GPR32:%vreg38 GPR64common:%vreg37
608B		%vreg34<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg34
624B		%vreg33<def> = MADDWrrr %vreg34, %vreg32, %WZR; GPR32:%vreg33,%vreg34,%vreg32
640B		%vreg29<def> = SUBREG_TO_REG 0, %vreg33, 15; GPR64:%vreg29 GPR32:%vreg33
656B		%vreg30<def> = SBFMXri %vreg29, 0, 31; GPR64:%vreg30,%vreg29
672B		%vreg25<def> = MOVi64imm 8; GPR64:%vreg25
688B		%vreg26<def> = MADDXrrr %vreg30, %vreg25, %XZR; GPR64:%vreg26,%vreg30,%vreg25
704B		%vreg27<def> = ADDXrr %vreg23, %vreg26; GPR64common:%vreg27,%vreg23 GPR64:%vreg26
720B		%vreg21<def> = LDRXui %vreg27, 0; mem:LD8[%arrayidx] GPR64:%vreg21 GPR64common:%vreg27
736B		%vreg19<def> = COPY %vreg14; GPR64all:%vreg19 GPR64:%vreg14
752B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
768B		%X0<def> = COPY %vreg18; GPR64all:%vreg18
784B		%X1<def> = COPY %vreg19; GPR64all:%vreg19
800B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
816B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
832B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
848B		STACKMAP 1, 0, %vreg21, %LR<earlyclobber,imp-def,dead>, ...; GPR64:%vreg21
864B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
880B		%X0<def> = COPY %vreg21; GPR64:%vreg21
896B		RET_ReallyLR %X0<imp-use>

# End machine code for function BZ2_bzerror.

********** SIMPLE REGISTER COALESCING **********
********** Function: BZ2_bzerror
********** JOINING INTERVALS ***********
entry:
16B	%vreg14<def> = COPY %LR; GPR64:%vreg14
	Considering merging %vreg14 with %LR
	Can only merge into reserved registers.
32B	%vreg2<def> = COPY %X1; GPR64:%vreg2
	Considering merging %vreg2 with %X1
	Can only merge into reserved registers.
48B	%vreg0<def> = COPY %X0; GPR64:%vreg0
	Considering merging %vreg0 with %X0
	Can only merge into reserved registers.
176B	%X0<def> = COPY %vreg12; GPR64all:%vreg12
	Considering merging %vreg12 with %X0
	Can only merge into reserved registers.
192B	%X1<def> = COPY %vreg13; GPR64all:%vreg13
	Considering merging %vreg13 with %X1
	Can only merge into reserved registers.
if.then:
if.end:
640B	%vreg29<def> = SUBREG_TO_REG 0, %vreg33, 15; GPR64:%vreg29 GPR32:%vreg33
	Considering merging to GPR64 with %vreg33 in %vreg29:sub_32
		RHS = %vreg33 [624r,640r:0)  0@624r
		LHS = %vreg29 [640r,656r:0)  0@640r
		merge %vreg29:0@640r into %vreg33:0@624r --> @624r
		erased:	640r	%vreg29<def> = SUBREG_TO_REG 0, %vreg33, 15; GPR64:%vreg29 GPR32:%vreg33
		updated: 624B	%vreg29:sub_32<def,read-undef> = MADDWrrr %vreg34, %vreg32, %WZR; GPR64:%vreg29 GPR32:%vreg34,%vreg32
	Success: %vreg33:sub_32 -> %vreg29
	Result = %vreg29 [624r,656r:0)  0@624r
768B	%X0<def> = COPY %vreg18; GPR64all:%vreg18
	Considering merging %vreg18 with %X0
	Can only merge into reserved registers.
784B	%X1<def> = COPY %vreg19; GPR64all:%vreg19
	Considering merging %vreg19 with %X1
	Can only merge into reserved registers.
880B	%X0<def> = COPY %vreg21; GPR64:%vreg21
	Considering merging %vreg21 with %X0
	Can only merge into reserved registers.
64B	%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
	Considering merging to GPR64 with %vreg0 in %vreg1
		RHS = %vreg0 [48r,64r:0)  0@48r
		LHS = %vreg1 [64r,288r:0)  0@64r
		merge %vreg1:0@64r into %vreg0:0@48r --> @48r
		erased:	64r	%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
		updated: 48B	%vreg1<def> = COPY %X0; GPR64:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [48r,288r:0)  0@48r
80B	%vreg3<def> = COPY %vreg2; GPR64:%vreg3,%vreg2
	Considering merging to GPR64 with %vreg2 in %vreg3
		RHS = %vreg2 [32r,80r:0)  0@32r
		LHS = %vreg3 [80r,304r:0)  0@80r
		merge %vreg3:0@80r into %vreg2:0@32r --> @32r
		erased:	80r	%vreg3<def> = COPY %vreg2; GPR64:%vreg3,%vreg2
		updated: 32B	%vreg3<def> = COPY %X1; GPR64:%vreg3
	Success: %vreg2 -> %vreg3
	Result = %vreg3 [32r,304r:0)  0@32r
128B	%vreg12<def> = COPY %vreg11; GPR64all:%vreg12 GPR64sp:%vreg11
	Considering merging to GPR64sp with %vreg11 in %vreg12
		RHS = %vreg11 [112r,128r:0)  0@112r
		LHS = %vreg12 [128r,176r:0)  0@128r
		merge %vreg12:0@128r into %vreg11:0@112r --> @112r
		erased:	128r	%vreg12<def> = COPY %vreg11; GPR64all:%vreg12 GPR64sp:%vreg11
		updated: 112B	%vreg12<def> = ADDXri %vreg10, <ga:@BZ2_bzerror>[TF=34], 0; GPR64sp:%vreg12 GPR64common:%vreg10
	Success: %vreg11 -> %vreg12
	Result = %vreg12 [112r,176r:0)  0@112r
144B	%vreg13<def> = COPY %vreg14; GPR64all:%vreg13 GPR64:%vreg14
	Considering merging to GPR64 with %vreg14 in %vreg13
		RHS = %vreg14 [16r,736r:0)  0@16r
		LHS = %vreg13 [144r,192r:0)  0@144r
		merge %vreg13:0@144r into %vreg14:0@16r --> @16r
		erased:	144r	%vreg13<def> = COPY %vreg14; GPR64all:%vreg13 GPR64:%vreg14
		updated: 16B	%vreg13<def> = COPY %LR; GPR64:%vreg13
		updated: 736B	%vreg19<def> = COPY %vreg13; GPR64all:%vreg19 GPR64:%vreg13
	Success: %vreg14 -> %vreg13
	Result = %vreg13 [16r,736r:0)  0@16r
496B	%vreg18<def> = COPY %vreg17; GPR64all:%vreg18 GPR64sp:%vreg17
	Considering merging to GPR64sp with %vreg17 in %vreg18
		RHS = %vreg17 [480r,496r:0)  0@480r
		LHS = %vreg18 [496r,768r:0)  0@496r
		merge %vreg18:0@496r into %vreg17:0@480r --> @480r
		erased:	496r	%vreg18<def> = COPY %vreg17; GPR64all:%vreg18 GPR64sp:%vreg17
		updated: 480B	%vreg18<def> = ADDXri %vreg16, <ga:@BZ2_bzerror>[TF=34], 0; GPR64sp:%vreg18 GPR64common:%vreg16
	Success: %vreg17 -> %vreg18
	Result = %vreg18 [480r,768r:0)  0@480r
736B	%vreg19<def> = COPY %vreg13; GPR64all:%vreg19 GPR64:%vreg13
	Considering merging to GPR64 with %vreg13 in %vreg19
		RHS = %vreg13 [16r,736r:0)  0@16r
		LHS = %vreg19 [736r,784r:0)  0@736r
		merge %vreg19:0@736r into %vreg13:0@16r --> @16r
		erased:	736r	%vreg19<def> = COPY %vreg13; GPR64all:%vreg19 GPR64:%vreg13
		updated: 16B	%vreg19<def> = COPY %LR; GPR64:%vreg19
		updated: 192B	%X1<def> = COPY %vreg19; GPR64:%vreg19
	Success: %vreg13 -> %vreg19
	Result = %vreg19 [16r,784r:0)  0@16r
176B	%X0<def> = COPY %vreg12; GPR64sp:%vreg12
	Considering merging %vreg12 with %X0
	Can only merge into reserved registers.
192B	%X1<def> = COPY %vreg19; GPR64:%vreg19
	Considering merging %vreg19 with %X1
	Can only merge into reserved registers.
768B	%X0<def> = COPY %vreg18; GPR64sp:%vreg18
	Considering merging %vreg18 with %X0
	Can only merge into reserved registers.
784B	%X1<def> = COPY %vreg19; GPR64:%vreg19
	Considering merging %vreg19 with %X1
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
W30 [0B,16r:0)[208r,208d:4)[256e,256d:1)[800r,800d:2)[848e,848d:3)  0@0B-phi 1@256e 2@800r 3@848e 4@208r
W0 [0B,48r:0)[176r,208r:3)[768r,800r:1)[880r,896r:2)  0@0B-phi 1@768r 2@880r 3@176r
W1 [0B,32r:0)[192r,208r:2)[784r,800r:1)  0@0B-phi 1@784r 2@192r
%vreg1 [48r,288r:0)  0@48r
%vreg3 [32r,304r:0)  0@32r
%vreg5 [368r,384r:0)  0@368r
%vreg8 [336r,352r:0)  0@336r
%vreg9 [320r,336r:0)  0@320r
%vreg10 [96r,112r:0)  0@96r
%vreg12 [112r,176r:0)  0@112r
%vreg16 [464r,480r:0)  0@464r
%vreg18 [480r,768r:0)  0@480r
%vreg19 [16r,784r:0)  0@16r
%vreg21 [720r,880r:0)  0@720r
%vreg22 [512r,528r:0)  0@512r
%vreg23 [528r,704r:0)  0@528r
%vreg25 [672r,688r:0)  0@672r
%vreg26 [688r,704r:0)  0@688r
%vreg27 [704r,720r:0)  0@704r
%vreg29 [624r,656r:0)  0@624r
%vreg30 [656r,688r:0)  0@656r
%vreg32 [544r,624r:0)  0@544r
%vreg34 [608r,624r:0)  0@608r
%vreg37 [576r,592r:0)  0@576r
%vreg38 [560r,592r:0)  0@560r
RegMasks: 208r 800r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzerror: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=4, align=4, at location [SP]
Function Live Ins: %X0 in %vreg0, %X1 in %vreg2, %LR in %vreg14

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %X1 %LR
16B		%vreg19<def> = COPY %LR; GPR64:%vreg19
32B		%vreg3<def> = COPY %X1; GPR64:%vreg3
48B		%vreg1<def> = COPY %X0; GPR64:%vreg1
96B		%vreg10<def> = ADRP <ga:@BZ2_bzerror>[TF=1]; GPR64common:%vreg10
112B		%vreg12<def> = ADDXri %vreg10, <ga:@BZ2_bzerror>[TF=34], 0; GPR64sp:%vreg12 GPR64common:%vreg10
160B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
176B		%X0<def> = COPY %vreg12; GPR64sp:%vreg12
192B		%X1<def> = COPY %vreg19; GPR64:%vreg19
208B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
224B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
240B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
256B		STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#2>, 0, %vreg3, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] LD8[FixedStack2](align=4) LD8[FixedStack1] GPR64:%vreg1,%vreg3
272B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
288B		STRXui %vreg1, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg1
304B		STRXui %vreg3, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg3
320B		%vreg9<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg9
336B		%vreg8<def> = LDRWui %vreg9, 1274; mem:LD4[%lastErr] GPR32:%vreg8 GPR64common:%vreg9
352B		STRWui %vreg8, <fi#2>, 0; mem:ST4[FixedStack2] GPR32:%vreg8
368B		%vreg5<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32common:%vreg5
384B		%WZR<def> = SUBSWri %vreg5, 0, 0, %NZCV<imp-def>; GPR32common:%vreg5
400B		Bcc 13, <BB#2>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

416B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
432B		STRWui %WZR, <fi#2>, 0; mem:ST4[FixedStack2]
	    Successors according to CFG: BB#2

448B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#1
464B		%vreg16<def> = ADRP <ga:@BZ2_bzerror>[TF=1]; GPR64common:%vreg16
480B		%vreg18<def> = ADDXri %vreg16, <ga:@BZ2_bzerror>[TF=34], 0; GPR64sp:%vreg18 GPR64common:%vreg16
512B		%vreg22<def> = ADRP <ga:@bzerrorstrings>[TF=1]; GPR64common:%vreg22
528B		%vreg23<def> = ADDXri %vreg22, <ga:@bzerrorstrings>[TF=34], 0; GPR64common:%vreg23,%vreg22
544B		%vreg32<def> = MOVi32imm 4294967295; GPR32:%vreg32
560B		%vreg38<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg38
576B		%vreg37<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg37
592B		STRWui %vreg38, %vreg37, 0; mem:ST4[%5] GPR32:%vreg38 GPR64common:%vreg37
608B		%vreg34<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg34
624B		%vreg29:sub_32<def,read-undef> = MADDWrrr %vreg34, %vreg32, %WZR; GPR64:%vreg29 GPR32:%vreg34,%vreg32
656B		%vreg30<def> = SBFMXri %vreg29, 0, 31; GPR64:%vreg30,%vreg29
672B		%vreg25<def> = MOVi64imm 8; GPR64:%vreg25
688B		%vreg26<def> = MADDXrrr %vreg30, %vreg25, %XZR; GPR64:%vreg26,%vreg30,%vreg25
704B		%vreg27<def> = ADDXrr %vreg23, %vreg26; GPR64common:%vreg27,%vreg23 GPR64:%vreg26
720B		%vreg21<def> = LDRXui %vreg27, 0; mem:LD8[%arrayidx] GPR64:%vreg21 GPR64common:%vreg27
752B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
768B		%X0<def> = COPY %vreg18; GPR64sp:%vreg18
784B		%X1<def> = COPY %vreg19; GPR64:%vreg19
800B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
816B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
832B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
848B		STACKMAP 1, 0, %vreg21, %LR<earlyclobber,imp-def,dead>, ...; GPR64:%vreg21
864B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
880B		%X0<def> = COPY %vreg21; GPR64:%vreg21
896B		RET_ReallyLR %X0<imp-use>

# End machine code for function BZ2_bzerror.

handleMove 480B -> 728B: %vreg18<def> = ADDXri %vreg16, <ga:@BZ2_bzerror>[TF=34], 0; GPR64sp:%vreg18 GPR64common:%vreg16
     %vreg18:	[480r,768r:0)  0@480r
        -->	[728r,768r:0)  0@728r
     %vreg16:	[464r,480r:0)  0@464r
        -->	[464r,728r:0)  0@464r
handleMove 464B -> 724B: %vreg16<def> = ADRP <ga:@BZ2_bzerror>[TF=1]; GPR64common:%vreg16
     %vreg16:	[464r,728r:0)  0@464r
        -->	[724r,728r:0)  0@724r
handleMove 528B -> 616B: %vreg23<def> = ADDXri %vreg22, <ga:@bzerrorstrings>[TF=34], 0; GPR64common:%vreg23,%vreg22
     %vreg23:	[528r,704r:0)  0@528r
        -->	[616r,704r:0)  0@616r
     %vreg22:	[512r,528r:0)  0@512r
        -->	[512r,616r:0)  0@512r
handleMove 544B -> 612B: %vreg32<def> = MOVi32imm 4294967295; GPR32:%vreg32
     %vreg32:	[544r,624r:0)  0@544r
        -->	[612r,624r:0)  0@612r
handleMove 512B -> 616B: %vreg22<def> = ADRP <ga:@bzerrorstrings>[TF=1]; GPR64common:%vreg22
     %vreg22:	[512r,632r:0)  0@512r
        -->	[616r,632r:0)  0@616r
********** GREEDY REGISTER ALLOCATION **********
********** Function: BZ2_bzerror
********** INTERVALS **********
W30 [0B,16r:0)[208r,208d:4)[256e,256d:1)[800r,800d:2)[848e,848d:3)  0@0B-phi 1@256e 2@800r 3@848e 4@208r
W0 [0B,48r:0)[176r,208r:3)[768r,800r:1)[880r,896r:2)  0@0B-phi 1@768r 2@880r 3@176r
W1 [0B,32r:0)[192r,208r:2)[784r,800r:1)  0@0B-phi 1@784r 2@192r
%vreg1 [48r,288r:0)  0@48r
%vreg3 [32r,304r:0)  0@32r
%vreg5 [368r,384r:0)  0@368r
%vreg8 [336r,352r:0)  0@336r
%vreg9 [320r,336r:0)  0@320r
%vreg10 [96r,112r:0)  0@96r
%vreg12 [112r,176r:0)  0@112r
%vreg16 [724r,728r:0)  0@724r
%vreg18 [728r,768r:0)  0@728r
%vreg19 [16r,784r:0)  0@16r
%vreg21 [720r,880r:0)  0@720r
%vreg22 [616r,632r:0)  0@616r
%vreg23 [632r,704r:0)  0@632r
%vreg25 [672r,688r:0)  0@672r
%vreg26 [688r,704r:0)  0@688r
%vreg27 [704r,720r:0)  0@704r
%vreg29 [640r,656r:0)  0@640r
%vreg30 [656r,688r:0)  0@656r
%vreg32 [624r,640r:0)  0@624r
%vreg34 [608r,640r:0)  0@608r
%vreg37 [576r,592r:0)  0@576r
%vreg38 [560r,592r:0)  0@560r
RegMasks: 208r 800r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzerror: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
  fi#1: size=8, align=8, at location [SP]
  fi#2: size=4, align=4, at location [SP]
Function Live Ins: %X0 in %vreg0, %X1 in %vreg2, %LR in %vreg14

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %X1 %LR
16B		%vreg19<def> = COPY %LR; GPR64:%vreg19
32B		%vreg3<def> = COPY %X1; GPR64:%vreg3
48B		%vreg1<def> = COPY %X0; GPR64:%vreg1
96B		%vreg10<def> = ADRP <ga:@BZ2_bzerror>[TF=1]; GPR64common:%vreg10
112B		%vreg12<def> = ADDXri %vreg10, <ga:@BZ2_bzerror>[TF=34], 0; GPR64sp:%vreg12 GPR64common:%vreg10
160B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
176B		%X0<def> = COPY %vreg12; GPR64sp:%vreg12
192B		%X1<def> = COPY %vreg19; GPR64:%vreg19
208B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
224B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
240B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
256B		STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#2>, 0, %vreg3, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] LD8[FixedStack2](align=4) LD8[FixedStack1] GPR64:%vreg1,%vreg3
272B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
288B		STRXui %vreg1, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg1
304B		STRXui %vreg3, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg3
320B		%vreg9<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg9
336B		%vreg8<def> = LDRWui %vreg9, 1274; mem:LD4[%lastErr] GPR32:%vreg8 GPR64common:%vreg9
352B		STRWui %vreg8, <fi#2>, 0; mem:ST4[FixedStack2] GPR32:%vreg8
368B		%vreg5<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32common:%vreg5
384B		%WZR<def> = SUBSWri %vreg5, 0, 0, %NZCV<imp-def>; GPR32common:%vreg5
400B		Bcc 13, <BB#2>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

416B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
432B		STRWui %WZR, <fi#2>, 0; mem:ST4[FixedStack2]
	    Successors according to CFG: BB#2

448B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#1
560B		%vreg38<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg38
576B		%vreg37<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg37
592B		STRWui %vreg38, %vreg37, 0; mem:ST4[%5] GPR32:%vreg38 GPR64common:%vreg37
608B		%vreg34<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg34
616B		%vreg22<def> = ADRP <ga:@bzerrorstrings>[TF=1]; GPR64common:%vreg22
624B		%vreg32<def> = MOVi32imm 4294967295; GPR32:%vreg32
632B		%vreg23<def> = ADDXri %vreg22, <ga:@bzerrorstrings>[TF=34], 0; GPR64common:%vreg23,%vreg22
640B		%vreg29:sub_32<def,read-undef> = MADDWrrr %vreg34, %vreg32, %WZR; GPR64:%vreg29 GPR32:%vreg34,%vreg32
656B		%vreg30<def> = SBFMXri %vreg29, 0, 31; GPR64:%vreg30,%vreg29
672B		%vreg25<def> = MOVi64imm 8; GPR64:%vreg25
688B		%vreg26<def> = MADDXrrr %vreg30, %vreg25, %XZR; GPR64:%vreg26,%vreg30,%vreg25
704B		%vreg27<def> = ADDXrr %vreg23, %vreg26; GPR64common:%vreg27,%vreg23 GPR64:%vreg26
720B		%vreg21<def> = LDRXui %vreg27, 0; mem:LD8[%arrayidx] GPR64:%vreg21 GPR64common:%vreg27
724B		%vreg16<def> = ADRP <ga:@BZ2_bzerror>[TF=1]; GPR64common:%vreg16
728B		%vreg18<def> = ADDXri %vreg16, <ga:@BZ2_bzerror>[TF=34], 0; GPR64sp:%vreg18 GPR64common:%vreg16
752B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
768B		%X0<def> = COPY %vreg18; GPR64sp:%vreg18
784B		%X1<def> = COPY %vreg19; GPR64:%vreg19
800B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
816B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
832B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
848B		STACKMAP 1, 0, %vreg21, %LR<earlyclobber,imp-def,dead>, ...; GPR64:%vreg21
864B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
880B		%X0<def> = COPY %vreg21; GPR64:%vreg21
896B		RET_ReallyLR %X0<imp-use>

# End machine code for function BZ2_bzerror.


selectOrSplit GPR64:%vreg19 [16r,784r:0)  0@16r w=2.594178e-03
hints: %X1
missed hint %X1
assigning %vreg19 to %X19: W19 [16r,784r:0)  0@16r

selectOrSplit GPR64:%vreg3 [32r,304r:0)  0@32r w=4.508928e-03
hints: %X1
missed hint %X1
assigning %vreg3 to %X20: W20 [32r,304r:0)  0@32r

selectOrSplit GPR64:%vreg1 [48r,288r:0)  0@48r w=4.734375e-03
hints: %X0
missed hint %X0
assigning %vreg1 to %X21: W21 [48r,288r:0)  0@48r

selectOrSplit GPR64sp:%vreg12 [112r,176r:0)  0@112r w=4.353448e-03
hints: %X0
assigning %vreg12 to %X0: W0 [112r,176r:0)  0@112r

selectOrSplit GPR64:%vreg21 [720r,880r:0)  0@720r w=5.410714e-03
hints: %X0
missed hint %X0
assigning %vreg21 to %X20: W20 [720r,880r:0)  0@720r

selectOrSplit GPR64sp:%vreg18 [728r,768r:0)  0@728r w=4.590909e-03
hints: %X0
assigning %vreg18 to %X0: W0 [728r,768r:0)  0@728r

selectOrSplit GPR64common:%vreg10 [96r,112r:0)  0@96r w=inf
assigning %vreg10 to %X8: W8 [96r,112r:0)  0@96r

selectOrSplit GPR64common:%vreg9 [320r,336r:0)  0@320r w=inf
assigning %vreg9 to %X8: W8 [320r,336r:0)  0@320r

selectOrSplit GPR32:%vreg8 [336r,352r:0)  0@336r w=inf
assigning %vreg8 to %W8: W8 [336r,352r:0)  0@336r

selectOrSplit GPR32common:%vreg5 [368r,384r:0)  0@368r w=inf
assigning %vreg5 to %W8: W8 [368r,384r:0)  0@368r

selectOrSplit GPR32:%vreg38 [560r,592r:0)  0@560r w=4.629630e-03
assigning %vreg38 to %W8: W8 [560r,592r:0)  0@560r

selectOrSplit GPR64common:%vreg37 [576r,592r:0)  0@576r w=inf
assigning %vreg37 to %X9: W9 [576r,592r:0)  0@576r

selectOrSplit GPR32:%vreg34 [608r,640r:0)  0@608r w=4.629630e-03
assigning %vreg34 to %W8: W8 [608r,640r:0)  0@608r

selectOrSplit GPR64common:%vreg22 [616r,632r:0)  0@616r w=2.403846e-03
assigning %vreg22 to %X9: W9 [616r,632r:0)  0@616r

selectOrSplit GPR32:%vreg32 [624r,640r:0)  0@624r w=2.403846e-03
assigning %vreg32 to %W10: W10 [624r,640r:0)  0@624r

selectOrSplit GPR64common:%vreg23 [632r,704r:0)  0@632r w=4.237288e-03
assigning %vreg23 to %X9: W9 [632r,704r:0)  0@632r

selectOrSplit GPR64:%vreg29 [640r,656r:0)  0@640r w=inf
assigning %vreg29 to %X8: W8 [640r,656r:0)  0@640r

selectOrSplit GPR64:%vreg30 [656r,688r:0)  0@656r w=4.629630e-03
assigning %vreg30 to %X8: W8 [656r,688r:0)  0@656r

selectOrSplit GPR64:%vreg25 [672r,688r:0)  0@672r w=inf
assigning %vreg25 to %X10: W10 [672r,688r:0)  0@672r

selectOrSplit GPR64:%vreg26 [688r,704r:0)  0@688r w=inf
assigning %vreg26 to %X8: W8 [688r,704r:0)  0@688r

selectOrSplit GPR64common:%vreg27 [704r,720r:0)  0@704r w=inf
assigning %vreg27 to %X8: W8 [704r,720r:0)  0@704r

selectOrSplit GPR64common:%vreg16 [724r,728r:0)  0@724r w=inf
assigning %vreg16 to %X8: W8 [724r,728r:0)  0@724r

********** STACK TRANSFORMATION METADATA **********
********** Function: BZ2_bzerror
********** REGISTER MAP **********
[%vreg1 -> %X21] GPR64
[%vreg3 -> %X20] GPR64
[%vreg5 -> %W8] GPR32common
[%vreg8 -> %W8] GPR32
[%vreg9 -> %X8] GPR64common
[%vreg10 -> %X8] GPR64common
[%vreg12 -> %X0] GPR64sp
[%vreg16 -> %X8] GPR64common
[%vreg18 -> %X0] GPR64sp
[%vreg19 -> %X19] GPR64
[%vreg21 -> %X20] GPR64
[%vreg22 -> %X9] GPR64common
[%vreg23 -> %X9] GPR64common
[%vreg25 -> %X10] GPR64
[%vreg26 -> %X8] GPR64
[%vreg27 -> %X8] GPR64common
[%vreg29 -> %X8] GPR64
[%vreg30 -> %X8] GPR64
[%vreg32 -> %W10] GPR32
[%vreg34 -> %W8] GPR32
[%vreg37 -> %X9] GPR64common
[%vreg38 -> %W8] GPR32


Stackmap 0:
  STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#2>, 0, %vreg3, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] LD8[FixedStack2](align=4) LD8[FixedStack1] GPR64:%vreg1,%vreg3

i8* %b: in register %X21 (vreg 1)
i8** %b.addr: in stack slot 0 (size: 8)
i32* %err: in stack slot 2 (size: 4)
i32* %errnum: in register %X20 (vreg 3)
i32** %errnum.addr: in stack slot 1 (size: 8)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, %vreg21, %LR<earlyclobber,imp-def,dead>, ...; GPR64:%vreg21

i8* %7: in register %X20 (vreg 21)

Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#2>, 0, %vreg3, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] LD8[FixedStack2](align=4) LD8[FixedStack1] GPR64:%vreg1,%vreg3
  -> Call instruction SlotIndex 208B, searching vregs 0 -> 39 and stack slots 0 -> 3
    + vreg19 is live in register but not in stackmap
      Defining instruction: %vreg19<def> = COPY %LR; GPR64:%vreg19
      Value: generated value, 1 instruction(s)

  STACKMAP 1, 0, %vreg21, %LR<earlyclobber,imp-def,dead>, ...; GPR64:%vreg21
  -> Call instruction SlotIndex 800B, searching vregs 0 -> 39 and stack slots 0 -> 3

********** REWRITE VIRTUAL REGISTERS **********
********** Function: BZ2_bzerror
********** REGISTER MAP **********
[%vreg1 -> %X21] GPR64
[%vreg3 -> %X20] GPR64
[%vreg5 -> %W8] GPR32common
[%vreg8 -> %W8] GPR32
[%vreg9 -> %X8] GPR64common
[%vreg10 -> %X8] GPR64common
[%vreg12 -> %X0] GPR64sp
[%vreg16 -> %X8] GPR64common
[%vreg18 -> %X0] GPR64sp
[%vreg19 -> %X19] GPR64
[%vreg21 -> %X20] GPR64
[%vreg22 -> %X9] GPR64common
[%vreg23 -> %X9] GPR64common
[%vreg25 -> %X10] GPR64
[%vreg26 -> %X8] GPR64
[%vreg27 -> %X8] GPR64common
[%vreg29 -> %X8] GPR64
[%vreg30 -> %X8] GPR64
[%vreg32 -> %W10] GPR32
[%vreg34 -> %W8] GPR32
[%vreg37 -> %X9] GPR64common
[%vreg38 -> %W8] GPR32

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %LR %X0 %X1
16B		%vreg19<def> = COPY %LR; GPR64:%vreg19
32B		%vreg3<def> = COPY %X1; GPR64:%vreg3
48B		%vreg1<def> = COPY %X0; GPR64:%vreg1
96B		%vreg10<def> = ADRP <ga:@BZ2_bzerror>[TF=1]; GPR64common:%vreg10
112B		%vreg12<def> = ADDXri %vreg10<kill>, <ga:@BZ2_bzerror>[TF=34], 0; GPR64sp:%vreg12 GPR64common:%vreg10
160B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
176B		%X0<def> = COPY %vreg12<kill>; GPR64sp:%vreg12
192B		%X1<def> = COPY %vreg19; GPR64:%vreg19
208B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
224B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
240B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
256B		STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#2>, 0, %vreg3, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] LD8[FixedStack2](align=4) LD8[FixedStack1] GPR64:%vreg1,%vreg3
272B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
288B		STRXui %vreg1<kill>, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg1
304B		STRXui %vreg3<kill>, <fi#1>, 0; mem:ST8[FixedStack1] GPR64:%vreg3
320B		%vreg9<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg9
336B		%vreg8<def> = LDRWui %vreg9<kill>, 1274; mem:LD4[%lastErr] GPR32:%vreg8 GPR64common:%vreg9
352B		STRWui %vreg8<kill>, <fi#2>, 0; mem:ST4[FixedStack2] GPR32:%vreg8
368B		%vreg5<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32common:%vreg5
384B		%WZR<def> = SUBSWri %vreg5<kill>, 0, 0, %NZCV<imp-def>; GPR32common:%vreg5
400B		Bcc 13, <BB#2>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1
> %X19<def> = COPY %LR
> %X20<def> = COPY %X1
> %X21<def> = COPY %X0
> %X8<def> = ADRP <ga:@BZ2_bzerror>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@BZ2_bzerror>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19
> BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 0, 0, %X21, 0, <fi#0>, 0, 0, <fi#2>, 0, %X20, 0, <fi#1>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] LD8[FixedStack2](align=4) LD8[FixedStack1]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRXui %X21<kill>, <fi#0>, 0; mem:ST8[FixedStack0]
> STRXui %X20<kill>, <fi#1>, 0; mem:ST8[FixedStack1]
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %W8<def> = LDRWui %X8<kill>, 1274; mem:LD4[%lastErr]
> STRWui %W8<kill>, <fi#2>, 0; mem:ST4[FixedStack2]
> %W8<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2]
> %WZR<def> = SUBSWri %W8<kill>, 0, 0, %NZCV<imp-def>
> Bcc 13, <BB#2>, %NZCV<imp-use,kill>
416B	BB#1: derived from LLVM BB %if.then
	    Live Ins: %X19
	    Predecessors according to CFG: BB#0
432B		STRWui %WZR, <fi#2>, 0; mem:ST4[FixedStack2]
	    Successors according to CFG: BB#2
> STRWui %WZR, <fi#2>, 0; mem:ST4[FixedStack2]
448B	BB#2: derived from LLVM BB %if.end
	    Live Ins: %X19
	    Predecessors according to CFG: BB#0 BB#1
560B		%vreg38<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg38
576B		%vreg37<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1] GPR64common:%vreg37
592B		STRWui %vreg38<kill>, %vreg37<kill>, 0; mem:ST4[%5] GPR32:%vreg38 GPR64common:%vreg37
608B		%vreg34<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg34
616B		%vreg22<def> = ADRP <ga:@bzerrorstrings>[TF=1]; GPR64common:%vreg22
624B		%vreg32<def> = MOVi32imm 4294967295; GPR32:%vreg32
632B		%vreg23<def> = ADDXri %vreg22<kill>, <ga:@bzerrorstrings>[TF=34], 0; GPR64common:%vreg23,%vreg22
640B		%vreg29:sub_32<def,read-undef> = MADDWrrr %vreg34<kill>, %vreg32<kill>, %WZR; GPR64:%vreg29 GPR32:%vreg34,%vreg32
656B		%vreg30<def> = SBFMXri %vreg29<kill>, 0, 31; GPR64:%vreg30,%vreg29
672B		%vreg25<def> = MOVi64imm 8; GPR64:%vreg25
688B		%vreg26<def> = MADDXrrr %vreg30<kill>, %vreg25<kill>, %XZR; GPR64:%vreg26,%vreg30,%vreg25
704B		%vreg27<def> = ADDXrr %vreg23<kill>, %vreg26<kill>; GPR64common:%vreg27,%vreg23 GPR64:%vreg26
720B		%vreg21<def> = LDRXui %vreg27<kill>, 0; mem:LD8[%arrayidx] GPR64:%vreg21 GPR64common:%vreg27
724B		%vreg16<def> = ADRP <ga:@BZ2_bzerror>[TF=1]; GPR64common:%vreg16
728B		%vreg18<def> = ADDXri %vreg16<kill>, <ga:@BZ2_bzerror>[TF=34], 0; GPR64sp:%vreg18 GPR64common:%vreg16
752B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
768B		%X0<def> = COPY %vreg18<kill>; GPR64sp:%vreg18
784B		%X1<def> = COPY %vreg19<kill>; GPR64:%vreg19
800B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
816B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
832B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
848B		STACKMAP 1, 0, %vreg21, %LR<earlyclobber,imp-def,dead>, ...; GPR64:%vreg21
864B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
880B		%X0<def> = COPY %vreg21<kill>; GPR64:%vreg21
896B		RET_ReallyLR %X0<imp-use>
> %W8<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2]
> %X9<def> = LDRXui <fi#1>, 0; mem:LD8[FixedStack1]
> STRWui %W8<kill>, %X9<kill>, 0; mem:ST4[%5]
> %W8<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2]
> %X9<def> = ADRP <ga:@bzerrorstrings>[TF=1]
> %W10<def> = MOVi32imm 4294967295
> %X9<def> = ADDXri %X9<kill>, <ga:@bzerrorstrings>[TF=34], 0
> %W8<def> = MADDWrrr %W8<kill>, %W10<kill>, %WZR, %X8<imp-def>
> %X8<def> = SBFMXri %X8<kill>, 0, 31
> %X10<def> = MOVi64imm 8
> %X8<def> = MADDXrrr %X8<kill>, %X10<kill>, %XZR
> %X8<def> = ADDXrr %X9<kill>, %X8<kill>
> %X20<def> = LDRXui %X8<kill>, 0; mem:LD8[%arrayidx]
> %X8<def> = ADRP <ga:@BZ2_bzerror>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@BZ2_bzerror>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19<kill>
> BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 1, 0, %X20, %LR<earlyclobber,imp-def,dead>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X20<kill>
> RET_ReallyLR %X0<imp-use>
Computing live-in reg-units in ABI blocks.
0B	BB#0 W0#0 W30#0
Created 2 new intervals.
********** INTERVALS **********
W30 [0B,16r:0)[176r,176d:4)[224e,224d:1)[1360r,1360d:3)[1408e,1408d:2)  0@0B-phi 1@224e 2@1408e 3@1360r 4@176r
W0 [0B,32r:0)[144r,176r:3)[1328r,1360r:2)[1440r,1456r:1)  0@0B-phi 1@1440r 2@1328r 3@144r
%vreg0 [32r,48r:0)  0@32r
%vreg1 [48r,256r:0)  0@48r
%vreg2 [64r,80r:0)  0@64r
%vreg3 [80r,96r:0)  0@80r
%vreg4 [96r,144r:0)  0@96r
%vreg5 [112r,160r:0)  0@112r
%vreg6 [16r,1344r:0)  0@16r
%vreg9 [336r,352r:0)  0@336r
%vreg11 [320r,336r:0)  0@320r
%vreg12 [304r,320r:0)  0@304r
%vreg16 [464r,480r:0)  0@464r
%vreg17 [448r,464r:0)  0@448r
%vreg19 [432r,480r:0)  0@432r
%vreg20 [416r,432r:0)  0@416r
%vreg23 [1088r,1104r:0)  0@1088r
%vreg25 [1072r,1088r:0)  0@1072r
%vreg26 [1056r,1072r:0)  0@1056r
%vreg30 [1024r,1040r:0)  0@1024r
%vreg31 [1008r,1024r:0)  0@1008r
%vreg33 [992r,1040r:0)  0@992r
%vreg34 [976r,992r:0)  0@976r
%vreg38 [944r,960r:0)  0@944r
%vreg39 [928r,944r:0)  0@928r
%vreg41 [912r,960r:0)  0@912r
%vreg42 [896r,912r:0)  0@896r
%vreg46 [864r,880r:0)  0@864r
%vreg47 [848r,864r:0)  0@848r
%vreg49 [832r,880r:0)  0@832r
%vreg50 [816r,832r:0)  0@816r
%vreg54 [784r,800r:0)  0@784r
%vreg55 [768r,784r:0)  0@768r
%vreg56 [752r,800r:0)  0@752r
%vreg60 [720r,736r:0)  0@720r
%vreg62 [704r,720r:0)  0@704r
%vreg63 [688r,704r:0)  0@688r
%vreg65 [672r,736r:0)  0@672r
%vreg68 [656r,672r:0)  0@656r
%vreg70 [640r,656r:0)  0@640r
%vreg71 [624r,640r:0)  0@624r
%vreg76 [608r,656r:0)  0@608r
%vreg77 [592r,608r:0)  0@592r
%vreg78 [560r,576r:0)  0@560r
%vreg82 [1184r,1200r:0)  0@1184r
%vreg83 [1168r,1184r:0)  0@1168r
%vreg85 [1152r,1200r:0)  0@1152r
%vreg86 [1136r,1152r:0)  0@1136r
%vreg87 [1280r,1280d:0)  0@1280r
%vreg88 [1264r,1440r:0)  0@1264r
%vreg89 [1312r,1328r:0)  0@1312r
RegMasks: 176r 1360r
********** MACHINEINSTRS **********
# Machine code for function copy_output_until_stop: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
  fi#1: size=1, align=1, at location [SP]
Function Live Ins: %X0 in %vreg0, %LR in %vreg6

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %LR
16B		%vreg6<def> = COPY %LR; GPR64:%vreg6
32B		%vreg0<def> = COPY %X0; GPR64:%vreg0
48B		%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
64B		%vreg2<def> = ADRP <ga:@copy_output_until_stop>[TF=1]; GPR64common:%vreg2
80B		%vreg3<def> = ADDXri %vreg2, <ga:@copy_output_until_stop>[TF=34], 0; GPR64sp:%vreg3 GPR64common:%vreg2
96B		%vreg4<def> = COPY %vreg3; GPR64all:%vreg4 GPR64sp:%vreg3
112B		%vreg5<def> = COPY %vreg6; GPR64all:%vreg5 GPR64:%vreg6
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		%X0<def> = COPY %vreg4; GPR64all:%vreg4
160B		%X1<def> = COPY %vreg5; GPR64all:%vreg5
176B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
224B		STACKMAP 0, 0, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack0] GPR64:%vreg1
240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
256B		STRXui %vreg1, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg1
272B		STRBBui %WZR, <fi#1>, 0; mem:ST1[FixedStack1]
	    Successors according to CFG: BB#1

288B	BB#1: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#0 BB#7
304B		%vreg12<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg12
320B		%vreg11<def> = LDRXui %vreg12, 0; mem:LD8[%strm] GPR64common:%vreg11,%vreg12
336B		%vreg9<def> = LDRWui %vreg11, 8; mem:LD4[%avail_out] GPR32:%vreg9 GPR64common:%vreg11
352B		CBNZW %vreg9, <BB#3>; GPR32:%vreg9
	    Successors according to CFG: BB#3 BB#2

368B	BB#2: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#1
384B		B <BB#8>
	    Successors according to CFG: BB#8

400B	BB#3: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#1
416B		%vreg20<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg20
432B		%vreg19<def> = LDRWui %vreg20, 30; mem:LD4[%state_out_pos] GPR32:%vreg19 GPR64common:%vreg20
448B		%vreg17<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg17
464B		%vreg16<def> = LDRWui %vreg17, 29; mem:LD4[%numZ] GPR32:%vreg16 GPR64common:%vreg17
480B		%WZR<def> = SUBSWrr %vreg19, %vreg16, %NZCV<imp-def>; GPR32:%vreg19,%vreg16
496B		Bcc 11, <BB#5>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#5 BB#4

512B	BB#4: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#3
528B		B <BB#8>
	    Successors according to CFG: BB#8

544B	BB#5: derived from LLVM BB %if.end.3
	    Predecessors according to CFG: BB#3
560B		%vreg78<def> = MOVi32imm 1; GPR32:%vreg78
576B		STRBBui %vreg78, <fi#1>, 0; mem:ST1[FixedStack1] GPR32:%vreg78
592B		%vreg77<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg77
608B		%vreg76<def> = LDRSWui %vreg77, 30; mem:LD4[%state_out_pos4] GPR64:%vreg76 GPR64common:%vreg77
624B		%vreg71<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg71
640B		%vreg70<def> = LDRXui %vreg71, 10; mem:LD8[%zbits] GPR64:%vreg70 GPR64common:%vreg71
656B		%vreg68<def> = ADDXrr %vreg70, %vreg76; GPR64common:%vreg68 GPR64:%vreg70,%vreg76
672B		%vreg65<def> = LDRBBui %vreg68, 0; mem:LD1[%arrayidx] GPR32:%vreg65 GPR64common:%vreg68
688B		%vreg63<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg63
704B		%vreg62<def> = LDRXui %vreg63, 0; mem:LD8[%strm5] GPR64common:%vreg62,%vreg63
720B		%vreg60<def> = LDRXui %vreg62, 3; mem:LD8[%next_out] GPR64common:%vreg60,%vreg62
736B		STRBBui %vreg65, %vreg60, 0; mem:ST1[%14] GPR32:%vreg65 GPR64common:%vreg60
752B		%vreg56<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg56
768B		%vreg55<def> = LDRWui %vreg56, 30; mem:LD4[%state_out_pos6] GPR32common:%vreg55 GPR64common:%vreg56
784B		%vreg54<def> = ADDWri %vreg55, 1, 0; GPR32common:%vreg54,%vreg55
800B		STRWui %vreg54, %vreg56, 30; mem:ST4[%state_out_pos6] GPR32common:%vreg54 GPR64common:%vreg56
816B		%vreg50<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg50
832B		%vreg49<def> = LDRXui %vreg50, 0; mem:LD8[%strm7] GPR64common:%vreg49,%vreg50
848B		%vreg47<def> = LDRWui %vreg49, 8; mem:LD4[%avail_out8] GPR32common:%vreg47 GPR64common:%vreg49
864B		%vreg46<def> = SUBWri %vreg47, 1, 0; GPR32common:%vreg46,%vreg47
880B		STRWui %vreg46, %vreg49, 8; mem:ST4[%avail_out8] GPR32common:%vreg46 GPR64common:%vreg49
896B		%vreg42<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg42
912B		%vreg41<def> = LDRXui %vreg42, 0; mem:LD8[%strm9] GPR64common:%vreg41,%vreg42
928B		%vreg39<def> = LDRXui %vreg41, 3; mem:LD8[%next_out10] GPR64common:%vreg39,%vreg41
944B		%vreg38<def> = ADDXri %vreg39, 1, 0; GPR64common:%vreg38,%vreg39
960B		STRXui %vreg38, %vreg41, 3; mem:ST8[%next_out10] GPR64common:%vreg38,%vreg41
976B		%vreg34<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg34
992B		%vreg33<def> = LDRXui %vreg34, 0; mem:LD8[%strm11] GPR64common:%vreg33,%vreg34
1008B		%vreg31<def> = LDRWui %vreg33, 9; mem:LD4[%total_out_lo32] GPR32common:%vreg31 GPR64common:%vreg33
1024B		%vreg30<def> = ADDWri %vreg31, 1, 0; GPR32common:%vreg30,%vreg31
1040B		STRWui %vreg30, %vreg33, 9; mem:ST4[%total_out_lo32] GPR32common:%vreg30 GPR64common:%vreg33
1056B		%vreg26<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg26
1072B		%vreg25<def> = LDRXui %vreg26, 0; mem:LD8[%strm13] GPR64common:%vreg25,%vreg26
1088B		%vreg23<def> = LDRWui %vreg25, 9; mem:LD4[%total_out_lo3214] GPR32:%vreg23 GPR64common:%vreg25
1104B		CBNZW %vreg23, <BB#7>; GPR32:%vreg23
	    Successors according to CFG: BB#7 BB#6

1120B	BB#6: derived from LLVM BB %if.then.16
	    Predecessors according to CFG: BB#5
1136B		%vreg86<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg86
1152B		%vreg85<def> = LDRXui %vreg86, 0; mem:LD8[%strm17] GPR64common:%vreg85,%vreg86
1168B		%vreg83<def> = LDRWui %vreg85, 10; mem:LD4[%total_out_hi32] GPR32common:%vreg83 GPR64common:%vreg85
1184B		%vreg82<def> = ADDWri %vreg83, 1, 0; GPR32common:%vreg82,%vreg83
1200B		STRWui %vreg82, %vreg85, 10; mem:ST4[%total_out_hi32] GPR32common:%vreg82 GPR64common:%vreg85
	    Successors according to CFG: BB#7

1216B	BB#7: derived from LLVM BB %if.end.19
	    Predecessors according to CFG: BB#5 BB#6
1232B		B <BB#1>
	    Successors according to CFG: BB#1

1248B	BB#8: derived from LLVM BB %while.end
	    Predecessors according to CFG: BB#4 BB#2
1264B		%vreg88<def> = LDRBBui <fi#1>, 0; mem:LD1[%progress_out] GPR32:%vreg88
1280B		%vreg87<def,dead> = COPY %vreg88; GPR32all:%vreg87 GPR32:%vreg88
1296B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1312B		%vreg89<def> = MOVaddr <ga:@copy_output_until_stop>[TF=1], <ga:@copy_output_until_stop>[TF=34]; GPR64:%vreg89
1328B		%X0<def> = COPY %vreg89; GPR64:%vreg89
1344B		%X1<def> = COPY %vreg6; GPR64:%vreg6
1360B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %SP<imp-def>
1376B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1392B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1408B		STACKMAP 1, 0, %vreg88, %LR<earlyclobber,imp-def,dead>, ...; GPR32:%vreg88
1424B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1440B		%W0<def> = COPY %vreg88; GPR32:%vreg88
1456B		RET_ReallyLR %W0<imp-use>

# End machine code for function copy_output_until_stop.

********** SIMPLE REGISTER COALESCING **********
********** Function: copy_output_until_stop
********** JOINING INTERVALS ***********
while.body:
if.end:
if.end.3:
if.end.19:
if.then.16:
if.then:
if.then.2:
while.end:
1328B	%X0<def> = COPY %vreg89; GPR64:%vreg89
	Considering merging %vreg89 with %X0
	Can only merge into reserved registers.
1344B	%X1<def> = COPY %vreg6; GPR64:%vreg6
	Considering merging %vreg6 with %X1
	Can only merge into reserved registers.
1440B	%W0<def> = COPY %vreg88; GPR32:%vreg88
	Considering merging %vreg88 with %W0
	Can only merge into reserved registers.
entry:
16B	%vreg6<def> = COPY %LR; GPR64:%vreg6
	Considering merging %vreg6 with %LR
	Can only merge into reserved registers.
32B	%vreg0<def> = COPY %X0; GPR64:%vreg0
	Considering merging %vreg0 with %X0
	Can only merge into reserved registers.
144B	%X0<def> = COPY %vreg4; GPR64all:%vreg4
	Considering merging %vreg4 with %X0
	Can only merge into reserved registers.
160B	%X1<def> = COPY %vreg5; GPR64all:%vreg5
	Considering merging %vreg5 with %X1
	Can only merge into reserved registers.
1280B	%vreg87<def,dead> = COPY %vreg88; GPR32all:%vreg87 GPR32:%vreg88
	Copy is dead.
Deleting dead def 1280r	%vreg87<def,dead> = COPY %vreg88; GPR32all:%vreg87 GPR32:%vreg88
Shrink: %vreg88 [1264r,1440r:0)  0@1264r
Shrunk: %vreg88 [1264r,1440r:0)  0@1264r
48B	%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
	Considering merging to GPR64 with %vreg0 in %vreg1
		RHS = %vreg0 [32r,48r:0)  0@32r
		LHS = %vreg1 [48r,256r:0)  0@48r
		merge %vreg1:0@48r into %vreg0:0@32r --> @32r
		erased:	48r	%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
		updated: 32B	%vreg1<def> = COPY %X0; GPR64:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [32r,256r:0)  0@32r
96B	%vreg4<def> = COPY %vreg3; GPR64all:%vreg4 GPR64sp:%vreg3
	Considering merging to GPR64sp with %vreg3 in %vreg4
		RHS = %vreg3 [80r,96r:0)  0@80r
		LHS = %vreg4 [96r,144r:0)  0@96r
		merge %vreg4:0@96r into %vreg3:0@80r --> @80r
		erased:	96r	%vreg4<def> = COPY %vreg3; GPR64all:%vreg4 GPR64sp:%vreg3
		updated: 80B	%vreg4<def> = ADDXri %vreg2, <ga:@copy_output_until_stop>[TF=34], 0; GPR64sp:%vreg4 GPR64common:%vreg2
	Success: %vreg3 -> %vreg4
	Result = %vreg4 [80r,144r:0)  0@80r
112B	%vreg5<def> = COPY %vreg6; GPR64all:%vreg5 GPR64:%vreg6
	Considering merging to GPR64 with %vreg6 in %vreg5
		RHS = %vreg6 [16r,1344r:0)  0@16r
		LHS = %vreg5 [112r,160r:0)  0@112r
		merge %vreg5:0@112r into %vreg6:0@16r --> @16r
		erased:	112r	%vreg5<def> = COPY %vreg6; GPR64all:%vreg5 GPR64:%vreg6
		updated: 16B	%vreg5<def> = COPY %LR; GPR64:%vreg5
		updated: 1344B	%X1<def> = COPY %vreg5; GPR64:%vreg5
	Success: %vreg6 -> %vreg5
	Result = %vreg5 [16r,1344r:0)  0@16r
1344B	%X1<def> = COPY %vreg5; GPR64:%vreg5
	Considering merging %vreg5 with %X1
	Can only merge into reserved registers.
144B	%X0<def> = COPY %vreg4; GPR64sp:%vreg4
	Considering merging %vreg4 with %X0
	Can only merge into reserved registers.
160B	%X1<def> = COPY %vreg5; GPR64:%vreg5
	Considering merging %vreg5 with %X1
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
W30 [0B,16r:0)[176r,176d:4)[224e,224d:1)[1360r,1360d:3)[1408e,1408d:2)  0@0B-phi 1@224e 2@1408e 3@1360r 4@176r
W0 [0B,32r:0)[144r,176r:3)[1328r,1360r:2)[1440r,1456r:1)  0@0B-phi 1@1440r 2@1328r 3@144r
%vreg1 [32r,256r:0)  0@32r
%vreg2 [64r,80r:0)  0@64r
%vreg4 [80r,144r:0)  0@80r
%vreg5 [16r,1344r:0)  0@16r
%vreg9 [336r,352r:0)  0@336r
%vreg11 [320r,336r:0)  0@320r
%vreg12 [304r,320r:0)  0@304r
%vreg16 [464r,480r:0)  0@464r
%vreg17 [448r,464r:0)  0@448r
%vreg19 [432r,480r:0)  0@432r
%vreg20 [416r,432r:0)  0@416r
%vreg23 [1088r,1104r:0)  0@1088r
%vreg25 [1072r,1088r:0)  0@1072r
%vreg26 [1056r,1072r:0)  0@1056r
%vreg30 [1024r,1040r:0)  0@1024r
%vreg31 [1008r,1024r:0)  0@1008r
%vreg33 [992r,1040r:0)  0@992r
%vreg34 [976r,992r:0)  0@976r
%vreg38 [944r,960r:0)  0@944r
%vreg39 [928r,944r:0)  0@928r
%vreg41 [912r,960r:0)  0@912r
%vreg42 [896r,912r:0)  0@896r
%vreg46 [864r,880r:0)  0@864r
%vreg47 [848r,864r:0)  0@848r
%vreg49 [832r,880r:0)  0@832r
%vreg50 [816r,832r:0)  0@816r
%vreg54 [784r,800r:0)  0@784r
%vreg55 [768r,784r:0)  0@768r
%vreg56 [752r,800r:0)  0@752r
%vreg60 [720r,736r:0)  0@720r
%vreg62 [704r,720r:0)  0@704r
%vreg63 [688r,704r:0)  0@688r
%vreg65 [672r,736r:0)  0@672r
%vreg68 [656r,672r:0)  0@656r
%vreg70 [640r,656r:0)  0@640r
%vreg71 [624r,640r:0)  0@624r
%vreg76 [608r,656r:0)  0@608r
%vreg77 [592r,608r:0)  0@592r
%vreg78 [560r,576r:0)  0@560r
%vreg82 [1184r,1200r:0)  0@1184r
%vreg83 [1168r,1184r:0)  0@1168r
%vreg85 [1152r,1200r:0)  0@1152r
%vreg86 [1136r,1152r:0)  0@1136r
%vreg88 [1264r,1440r:0)  0@1264r
%vreg89 [1312r,1328r:0)  0@1312r
RegMasks: 176r 1360r
********** MACHINEINSTRS **********
# Machine code for function copy_output_until_stop: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
  fi#1: size=1, align=1, at location [SP]
Function Live Ins: %X0 in %vreg0, %LR in %vreg6

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %LR
16B		%vreg5<def> = COPY %LR; GPR64:%vreg5
32B		%vreg1<def> = COPY %X0; GPR64:%vreg1
64B		%vreg2<def> = ADRP <ga:@copy_output_until_stop>[TF=1]; GPR64common:%vreg2
80B		%vreg4<def> = ADDXri %vreg2, <ga:@copy_output_until_stop>[TF=34], 0; GPR64sp:%vreg4 GPR64common:%vreg2
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		%X0<def> = COPY %vreg4; GPR64sp:%vreg4
160B		%X1<def> = COPY %vreg5; GPR64:%vreg5
176B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
224B		STACKMAP 0, 0, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack0] GPR64:%vreg1
240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
256B		STRXui %vreg1, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg1
272B		STRBBui %WZR, <fi#1>, 0; mem:ST1[FixedStack1]
	    Successors according to CFG: BB#1

288B	BB#1: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#0 BB#7
304B		%vreg12<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg12
320B		%vreg11<def> = LDRXui %vreg12, 0; mem:LD8[%strm] GPR64common:%vreg11,%vreg12
336B		%vreg9<def> = LDRWui %vreg11, 8; mem:LD4[%avail_out] GPR32:%vreg9 GPR64common:%vreg11
352B		CBNZW %vreg9, <BB#3>; GPR32:%vreg9
	    Successors according to CFG: BB#3 BB#2

368B	BB#2: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#1
384B		B <BB#8>
	    Successors according to CFG: BB#8

400B	BB#3: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#1
416B		%vreg20<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg20
432B		%vreg19<def> = LDRWui %vreg20, 30; mem:LD4[%state_out_pos] GPR32:%vreg19 GPR64common:%vreg20
448B		%vreg17<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg17
464B		%vreg16<def> = LDRWui %vreg17, 29; mem:LD4[%numZ] GPR32:%vreg16 GPR64common:%vreg17
480B		%WZR<def> = SUBSWrr %vreg19, %vreg16, %NZCV<imp-def>; GPR32:%vreg19,%vreg16
496B		Bcc 11, <BB#5>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#5 BB#4

512B	BB#4: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#3
528B		B <BB#8>
	    Successors according to CFG: BB#8

544B	BB#5: derived from LLVM BB %if.end.3
	    Predecessors according to CFG: BB#3
560B		%vreg78<def> = MOVi32imm 1; GPR32:%vreg78
576B		STRBBui %vreg78, <fi#1>, 0; mem:ST1[FixedStack1] GPR32:%vreg78
592B		%vreg77<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg77
608B		%vreg76<def> = LDRSWui %vreg77, 30; mem:LD4[%state_out_pos4] GPR64:%vreg76 GPR64common:%vreg77
624B		%vreg71<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg71
640B		%vreg70<def> = LDRXui %vreg71, 10; mem:LD8[%zbits] GPR64:%vreg70 GPR64common:%vreg71
656B		%vreg68<def> = ADDXrr %vreg70, %vreg76; GPR64common:%vreg68 GPR64:%vreg70,%vreg76
672B		%vreg65<def> = LDRBBui %vreg68, 0; mem:LD1[%arrayidx] GPR32:%vreg65 GPR64common:%vreg68
688B		%vreg63<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg63
704B		%vreg62<def> = LDRXui %vreg63, 0; mem:LD8[%strm5] GPR64common:%vreg62,%vreg63
720B		%vreg60<def> = LDRXui %vreg62, 3; mem:LD8[%next_out] GPR64common:%vreg60,%vreg62
736B		STRBBui %vreg65, %vreg60, 0; mem:ST1[%14] GPR32:%vreg65 GPR64common:%vreg60
752B		%vreg56<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg56
768B		%vreg55<def> = LDRWui %vreg56, 30; mem:LD4[%state_out_pos6] GPR32common:%vreg55 GPR64common:%vreg56
784B		%vreg54<def> = ADDWri %vreg55, 1, 0; GPR32common:%vreg54,%vreg55
800B		STRWui %vreg54, %vreg56, 30; mem:ST4[%state_out_pos6] GPR32common:%vreg54 GPR64common:%vreg56
816B		%vreg50<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg50
832B		%vreg49<def> = LDRXui %vreg50, 0; mem:LD8[%strm7] GPR64common:%vreg49,%vreg50
848B		%vreg47<def> = LDRWui %vreg49, 8; mem:LD4[%avail_out8] GPR32common:%vreg47 GPR64common:%vreg49
864B		%vreg46<def> = SUBWri %vreg47, 1, 0; GPR32common:%vreg46,%vreg47
880B		STRWui %vreg46, %vreg49, 8; mem:ST4[%avail_out8] GPR32common:%vreg46 GPR64common:%vreg49
896B		%vreg42<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg42
912B		%vreg41<def> = LDRXui %vreg42, 0; mem:LD8[%strm9] GPR64common:%vreg41,%vreg42
928B		%vreg39<def> = LDRXui %vreg41, 3; mem:LD8[%next_out10] GPR64common:%vreg39,%vreg41
944B		%vreg38<def> = ADDXri %vreg39, 1, 0; GPR64common:%vreg38,%vreg39
960B		STRXui %vreg38, %vreg41, 3; mem:ST8[%next_out10] GPR64common:%vreg38,%vreg41
976B		%vreg34<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg34
992B		%vreg33<def> = LDRXui %vreg34, 0; mem:LD8[%strm11] GPR64common:%vreg33,%vreg34
1008B		%vreg31<def> = LDRWui %vreg33, 9; mem:LD4[%total_out_lo32] GPR32common:%vreg31 GPR64common:%vreg33
1024B		%vreg30<def> = ADDWri %vreg31, 1, 0; GPR32common:%vreg30,%vreg31
1040B		STRWui %vreg30, %vreg33, 9; mem:ST4[%total_out_lo32] GPR32common:%vreg30 GPR64common:%vreg33
1056B		%vreg26<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg26
1072B		%vreg25<def> = LDRXui %vreg26, 0; mem:LD8[%strm13] GPR64common:%vreg25,%vreg26
1088B		%vreg23<def> = LDRWui %vreg25, 9; mem:LD4[%total_out_lo3214] GPR32:%vreg23 GPR64common:%vreg25
1104B		CBNZW %vreg23, <BB#7>; GPR32:%vreg23
	    Successors according to CFG: BB#7 BB#6

1120B	BB#6: derived from LLVM BB %if.then.16
	    Predecessors according to CFG: BB#5
1136B		%vreg86<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg86
1152B		%vreg85<def> = LDRXui %vreg86, 0; mem:LD8[%strm17] GPR64common:%vreg85,%vreg86
1168B		%vreg83<def> = LDRWui %vreg85, 10; mem:LD4[%total_out_hi32] GPR32common:%vreg83 GPR64common:%vreg85
1184B		%vreg82<def> = ADDWri %vreg83, 1, 0; GPR32common:%vreg82,%vreg83
1200B		STRWui %vreg82, %vreg85, 10; mem:ST4[%total_out_hi32] GPR32common:%vreg82 GPR64common:%vreg85
	    Successors according to CFG: BB#7

1216B	BB#7: derived from LLVM BB %if.end.19
	    Predecessors according to CFG: BB#5 BB#6
1232B		B <BB#1>
	    Successors according to CFG: BB#1

1248B	BB#8: derived from LLVM BB %while.end
	    Predecessors according to CFG: BB#4 BB#2
1264B		%vreg88<def> = LDRBBui <fi#1>, 0; mem:LD1[%progress_out] GPR32:%vreg88
1296B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1312B		%vreg89<def> = MOVaddr <ga:@copy_output_until_stop>[TF=1], <ga:@copy_output_until_stop>[TF=34]; GPR64:%vreg89
1328B		%X0<def> = COPY %vreg89; GPR64:%vreg89
1344B		%X1<def> = COPY %vreg5; GPR64:%vreg5
1360B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %SP<imp-def>
1376B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1392B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1408B		STACKMAP 1, 0, %vreg88, %LR<earlyclobber,imp-def,dead>, ...; GPR32:%vreg88
1424B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1440B		%W0<def> = COPY %vreg88; GPR32:%vreg88
1456B		RET_ReallyLR %W0<imp-use>

# End machine code for function copy_output_until_stop.

handleMove 432B -> 456B: %vreg19<def> = LDRWui %vreg20, 30; mem:LD4[%state_out_pos] GPR32:%vreg19 GPR64common:%vreg20
     %vreg19:	[432r,480r:0)  0@432r
        -->	[456r,480r:0)  0@456r
     %vreg20:	[416r,432r:0)  0@416r
        -->	[416r,456r:0)  0@416r
AllocationOrder(GPR32sponly) = [ ]
handleMove 672B -> 712B: %vreg65<def> = LDRBBui %vreg68, 0; mem:LD1[%arrayidx] GPR32:%vreg65 GPR64common:%vreg68
     %vreg65:	[672r,736r:0)  0@672r
        -->	[712r,736r:0)  0@712r
     %vreg68:	[656r,672r:0)  0@656r
        -->	[656r,712r:0)  0@656r
handleMove 656B -> 708B: %vreg68<def> = ADDXrr %vreg70, %vreg76; GPR64common:%vreg68 GPR64:%vreg70,%vreg76
     %vreg68:	[656r,712r:0)  0@656r
        -->	[708r,712r:0)  0@708r
     %vreg70:	[640r,656r:0)  0@640r
        -->	[640r,708r:0)  0@640r
     %vreg76:	[608r,656r:0)  0@608r
        -->	[608r,708r:0)  0@608r
handleMove 640B -> 696B: %vreg70<def> = LDRXui %vreg71, 10; mem:LD8[%zbits] GPR64:%vreg70 GPR64common:%vreg71
     %vreg70:	[640r,708r:0)  0@640r
        -->	[696r,708r:0)  0@696r
     %vreg71:	[624r,640r:0)  0@624r
        -->	[624r,696r:0)  0@624r
handleMove 608B -> 692B: %vreg76<def> = LDRSWui %vreg77, 30; mem:LD4[%state_out_pos4] GPR64:%vreg76 GPR64common:%vreg77
     %vreg76:	[608r,708r:0)  0@608r
        -->	[692r,708r:0)  0@692r
     %vreg77:	[592r,608r:0)  0@592r
        -->	[592r,692r:0)  0@592r
********** GREEDY REGISTER ALLOCATION **********
********** Function: copy_output_until_stop
********** INTERVALS **********
W30 [0B,16r:0)[176r,176d:4)[224e,224d:1)[1360r,1360d:3)[1408e,1408d:2)  0@0B-phi 1@224e 2@1408e 3@1360r 4@176r
W0 [0B,32r:0)[144r,176r:3)[1328r,1360r:2)[1440r,1456r:1)  0@0B-phi 1@1440r 2@1328r 3@144r
%vreg1 [32r,256r:0)  0@32r
%vreg2 [64r,80r:0)  0@64r
%vreg4 [80r,144r:0)  0@80r
%vreg5 [16r,1344r:0)  0@16r
%vreg9 [336r,352r:0)  0@336r
%vreg11 [320r,336r:0)  0@320r
%vreg12 [304r,320r:0)  0@304r
%vreg16 [464r,480r:0)  0@464r
%vreg17 [448r,464r:0)  0@448r
%vreg19 [456r,480r:0)  0@456r
%vreg20 [416r,456r:0)  0@416r
%vreg23 [1088r,1104r:0)  0@1088r
%vreg25 [1072r,1088r:0)  0@1072r
%vreg26 [1056r,1072r:0)  0@1056r
%vreg30 [1024r,1040r:0)  0@1024r
%vreg31 [1008r,1024r:0)  0@1008r
%vreg33 [992r,1040r:0)  0@992r
%vreg34 [976r,992r:0)  0@976r
%vreg38 [944r,960r:0)  0@944r
%vreg39 [928r,944r:0)  0@928r
%vreg41 [912r,960r:0)  0@912r
%vreg42 [896r,912r:0)  0@896r
%vreg46 [864r,880r:0)  0@864r
%vreg47 [848r,864r:0)  0@848r
%vreg49 [832r,880r:0)  0@832r
%vreg50 [816r,832r:0)  0@816r
%vreg54 [784r,800r:0)  0@784r
%vreg55 [768r,784r:0)  0@768r
%vreg56 [752r,800r:0)  0@752r
%vreg60 [720r,736r:0)  0@720r
%vreg62 [704r,720r:0)  0@704r
%vreg63 [688r,704r:0)  0@688r
%vreg65 [712r,736r:0)  0@712r
%vreg68 [708r,712r:0)  0@708r
%vreg70 [696r,708r:0)  0@696r
%vreg71 [624r,696r:0)  0@624r
%vreg76 [692r,708r:0)  0@692r
%vreg77 [592r,692r:0)  0@592r
%vreg78 [560r,576r:0)  0@560r
%vreg82 [1184r,1200r:0)  0@1184r
%vreg83 [1168r,1184r:0)  0@1168r
%vreg85 [1152r,1200r:0)  0@1152r
%vreg86 [1136r,1152r:0)  0@1136r
%vreg88 [1264r,1440r:0)  0@1264r
%vreg89 [1312r,1328r:0)  0@1312r
RegMasks: 176r 1360r
********** MACHINEINSTRS **********
# Machine code for function copy_output_until_stop: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
  fi#1: size=1, align=1, at location [SP]
Function Live Ins: %X0 in %vreg0, %LR in %vreg6

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %LR
16B		%vreg5<def> = COPY %LR; GPR64:%vreg5
32B		%vreg1<def> = COPY %X0; GPR64:%vreg1
64B		%vreg2<def> = ADRP <ga:@copy_output_until_stop>[TF=1]; GPR64common:%vreg2
80B		%vreg4<def> = ADDXri %vreg2, <ga:@copy_output_until_stop>[TF=34], 0; GPR64sp:%vreg4 GPR64common:%vreg2
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		%X0<def> = COPY %vreg4; GPR64sp:%vreg4
160B		%X1<def> = COPY %vreg5; GPR64:%vreg5
176B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
224B		STACKMAP 0, 0, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack0] GPR64:%vreg1
240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
256B		STRXui %vreg1, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg1
272B		STRBBui %WZR, <fi#1>, 0; mem:ST1[FixedStack1]
	    Successors according to CFG: BB#1

288B	BB#1: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#0 BB#7
304B		%vreg12<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg12
320B		%vreg11<def> = LDRXui %vreg12, 0; mem:LD8[%strm] GPR64common:%vreg11,%vreg12
336B		%vreg9<def> = LDRWui %vreg11, 8; mem:LD4[%avail_out] GPR32:%vreg9 GPR64common:%vreg11
352B		CBNZW %vreg9, <BB#3>; GPR32:%vreg9
	    Successors according to CFG: BB#3 BB#2

368B	BB#2: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#1
384B		B <BB#8>
	    Successors according to CFG: BB#8

400B	BB#3: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#1
416B		%vreg20<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg20
448B		%vreg17<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg17
456B		%vreg19<def> = LDRWui %vreg20, 30; mem:LD4[%state_out_pos] GPR32:%vreg19 GPR64common:%vreg20
464B		%vreg16<def> = LDRWui %vreg17, 29; mem:LD4[%numZ] GPR32:%vreg16 GPR64common:%vreg17
480B		%WZR<def> = SUBSWrr %vreg19, %vreg16, %NZCV<imp-def>; GPR32:%vreg19,%vreg16
496B		Bcc 11, <BB#5>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#5 BB#4

512B	BB#4: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#3
528B		B <BB#8>
	    Successors according to CFG: BB#8

544B	BB#5: derived from LLVM BB %if.end.3
	    Predecessors according to CFG: BB#3
560B		%vreg78<def> = MOVi32imm 1; GPR32:%vreg78
576B		STRBBui %vreg78, <fi#1>, 0; mem:ST1[FixedStack1] GPR32:%vreg78
592B		%vreg77<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg77
624B		%vreg71<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg71
688B		%vreg63<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg63
692B		%vreg76<def> = LDRSWui %vreg77, 30; mem:LD4[%state_out_pos4] GPR64:%vreg76 GPR64common:%vreg77
696B		%vreg70<def> = LDRXui %vreg71, 10; mem:LD8[%zbits] GPR64:%vreg70 GPR64common:%vreg71
704B		%vreg62<def> = LDRXui %vreg63, 0; mem:LD8[%strm5] GPR64common:%vreg62,%vreg63
708B		%vreg68<def> = ADDXrr %vreg70, %vreg76; GPR64common:%vreg68 GPR64:%vreg70,%vreg76
712B		%vreg65<def> = LDRBBui %vreg68, 0; mem:LD1[%arrayidx] GPR32:%vreg65 GPR64common:%vreg68
720B		%vreg60<def> = LDRXui %vreg62, 3; mem:LD8[%next_out] GPR64common:%vreg60,%vreg62
736B		STRBBui %vreg65, %vreg60, 0; mem:ST1[%14] GPR32:%vreg65 GPR64common:%vreg60
752B		%vreg56<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg56
768B		%vreg55<def> = LDRWui %vreg56, 30; mem:LD4[%state_out_pos6] GPR32common:%vreg55 GPR64common:%vreg56
784B		%vreg54<def> = ADDWri %vreg55, 1, 0; GPR32common:%vreg54,%vreg55
800B		STRWui %vreg54, %vreg56, 30; mem:ST4[%state_out_pos6] GPR32common:%vreg54 GPR64common:%vreg56
816B		%vreg50<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg50
832B		%vreg49<def> = LDRXui %vreg50, 0; mem:LD8[%strm7] GPR64common:%vreg49,%vreg50
848B		%vreg47<def> = LDRWui %vreg49, 8; mem:LD4[%avail_out8] GPR32common:%vreg47 GPR64common:%vreg49
864B		%vreg46<def> = SUBWri %vreg47, 1, 0; GPR32common:%vreg46,%vreg47
880B		STRWui %vreg46, %vreg49, 8; mem:ST4[%avail_out8] GPR32common:%vreg46 GPR64common:%vreg49
896B		%vreg42<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg42
912B		%vreg41<def> = LDRXui %vreg42, 0; mem:LD8[%strm9] GPR64common:%vreg41,%vreg42
928B		%vreg39<def> = LDRXui %vreg41, 3; mem:LD8[%next_out10] GPR64common:%vreg39,%vreg41
944B		%vreg38<def> = ADDXri %vreg39, 1, 0; GPR64common:%vreg38,%vreg39
960B		STRXui %vreg38, %vreg41, 3; mem:ST8[%next_out10] GPR64common:%vreg38,%vreg41
976B		%vreg34<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg34
992B		%vreg33<def> = LDRXui %vreg34, 0; mem:LD8[%strm11] GPR64common:%vreg33,%vreg34
1008B		%vreg31<def> = LDRWui %vreg33, 9; mem:LD4[%total_out_lo32] GPR32common:%vreg31 GPR64common:%vreg33
1024B		%vreg30<def> = ADDWri %vreg31, 1, 0; GPR32common:%vreg30,%vreg31
1040B		STRWui %vreg30, %vreg33, 9; mem:ST4[%total_out_lo32] GPR32common:%vreg30 GPR64common:%vreg33
1056B		%vreg26<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg26
1072B		%vreg25<def> = LDRXui %vreg26, 0; mem:LD8[%strm13] GPR64common:%vreg25,%vreg26
1088B		%vreg23<def> = LDRWui %vreg25, 9; mem:LD4[%total_out_lo3214] GPR32:%vreg23 GPR64common:%vreg25
1104B		CBNZW %vreg23, <BB#7>; GPR32:%vreg23
	    Successors according to CFG: BB#7 BB#6

1120B	BB#6: derived from LLVM BB %if.then.16
	    Predecessors according to CFG: BB#5
1136B		%vreg86<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg86
1152B		%vreg85<def> = LDRXui %vreg86, 0; mem:LD8[%strm17] GPR64common:%vreg85,%vreg86
1168B		%vreg83<def> = LDRWui %vreg85, 10; mem:LD4[%total_out_hi32] GPR32common:%vreg83 GPR64common:%vreg85
1184B		%vreg82<def> = ADDWri %vreg83, 1, 0; GPR32common:%vreg82,%vreg83
1200B		STRWui %vreg82, %vreg85, 10; mem:ST4[%total_out_hi32] GPR32common:%vreg82 GPR64common:%vreg85
	    Successors according to CFG: BB#7

1216B	BB#7: derived from LLVM BB %if.end.19
	    Predecessors according to CFG: BB#5 BB#6
1232B		B <BB#1>
	    Successors according to CFG: BB#1

1248B	BB#8: derived from LLVM BB %while.end
	    Predecessors according to CFG: BB#4 BB#2
1264B		%vreg88<def> = LDRBBui <fi#1>, 0; mem:LD1[%progress_out] GPR32:%vreg88
1296B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1312B		%vreg89<def> = MOVaddr <ga:@copy_output_until_stop>[TF=1], <ga:@copy_output_until_stop>[TF=34]; GPR64:%vreg89
1328B		%X0<def> = COPY %vreg89; GPR64:%vreg89
1344B		%X1<def> = COPY %vreg5; GPR64:%vreg5
1360B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %SP<imp-def>
1376B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1392B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1408B		STACKMAP 1, 0, %vreg88, %LR<earlyclobber,imp-def,dead>, ...; GPR32:%vreg88
1424B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1440B		%W0<def> = COPY %vreg88; GPR32:%vreg88
1456B		RET_ReallyLR %W0<imp-use>

# End machine code for function copy_output_until_stop.


selectOrSplit GPR64:%vreg5 [16r,1344r:0)  0@16r w=1.753472e-03
hints: %X1
missed hint %X1
assigning %vreg5 to %X19: W19 [16r,1344r:0)  0@16r

selectOrSplit GPR64:%vreg1 [32r,256r:0)  0@32r w=4.855769e-03
hints: %X0
missed hint %X0
assigning %vreg1 to %X20: W20 [32r,256r:0)  0@32r

selectOrSplit GPR64sp:%vreg4 [80r,144r:0)  0@80r w=4.353448e-03
hints: %X0
assigning %vreg4 to %X0: W0 [80r,144r:0)  0@80r

selectOrSplit GPR32:%vreg88 [1264r,1440r:0)  0@1264r w=5.260416e-03
hints: %W0
missed hint %W0
assigning %vreg88 to %W20: W20 [1264r,1440r:0)  0@1264r

selectOrSplit GPR64:%vreg89 [1312r,1328r:0)  0@1312r w=inf
hints: %X0
assigning %vreg89 to %X0: W0 [1312r,1328r:0)  0@1312r

selectOrSplit GPR64common:%vreg2 [64r,80r:0)  0@64r w=inf
assigning %vreg2 to %X8: W8 [64r,80r:0)  0@64r

selectOrSplit GPR64common:%vreg12 [304r,320r:0)  0@304r w=inf
assigning %vreg12 to %X8: W8 [304r,320r:0)  0@304r

selectOrSplit GPR64common:%vreg11 [320r,336r:0)  0@320r w=inf
assigning %vreg11 to %X8: W8 [320r,336r:0)  0@320r

selectOrSplit GPR32:%vreg9 [336r,352r:0)  0@336r w=inf
assigning %vreg9 to %W8: W8 [336r,352r:0)  0@336r

selectOrSplit GPR64common:%vreg20 [416r,456r:0)  0@416r w=2.998066e-03
assigning %vreg20 to %X8: W8 [416r,456r:0)  0@416r

selectOrSplit GPR64common:%vreg17 [448r,464r:0)  0@448r w=3.171031e-03
assigning %vreg17 to %X9: W9 [448r,464r:0)  0@448r

selectOrSplit GPR32:%vreg19 [456r,480r:0)  0@456r w=3.111200e-03
assigning %vreg19 to %W8: W8 [456r,480r:0)  0@456r

selectOrSplit GPR32:%vreg16 [464r,480r:0)  0@464r w=inf
assigning %vreg16 to %W9: W9 [464r,480r:0)  0@464r

selectOrSplit GPR32:%vreg78 [560r,576r:0)  0@560r w=inf
assigning %vreg78 to %W8: W8 [560r,576r:0)  0@560r

selectOrSplit GPR64common:%vreg77 [592r,692r:0)  0@592r w=1.276596e-03
assigning %vreg77 to %X8: W8 [592r,692r:0)  0@592r

selectOrSplit GPR64common:%vreg71 [624r,696r:0)  0@624r w=1.352326e-03
assigning %vreg71 to %X9: W9 [624r,696r:0)  0@624r

selectOrSplit GPR64common:%vreg63 [688r,704r:0)  0@688r w=1.534370e-03
assigning %vreg63 to %X10: W10 [688r,704r:0)  0@688r

selectOrSplit GPR64:%vreg76 [692r,708r:0)  0@692r w=1.534370e-03
assigning %vreg76 to %X8: W8 [692r,708r:0)  0@692r

selectOrSplit GPR64:%vreg70 [696r,708r:0)  0@696r w=1.549267e-03
assigning %vreg70 to %X9: W9 [696r,708r:0)  0@696r

selectOrSplit GPR64common:%vreg62 [704r,720r:0)  0@704r w=1.534370e-03
assigning %vreg62 to %X10: W10 [704r,720r:0)  0@704r

selectOrSplit GPR64common:%vreg68 [708r,712r:0)  0@708r w=inf
assigning %vreg68 to %X8: W8 [708r,712r:0)  0@708r

selectOrSplit GPR32:%vreg65 [712r,736r:0)  0@712r w=1.505419e-03
assigning %vreg65 to %W8: W8 [712r,736r:0)  0@712r

selectOrSplit GPR64common:%vreg60 [720r,736r:0)  0@720r w=inf
assigning %vreg60 to %X9: W9 [720r,736r:0)  0@720r

selectOrSplit GPR64common:%vreg56 [752r,800r:0)  0@752r w=2.137158e-03
assigning %vreg56 to %X8: W8 [752r,800r:0)  0@752r

selectOrSplit GPR32common:%vreg55 [768r,784r:0)  0@768r w=inf
assigning %vreg55 to %W9: W9 [768r,784r:0)  0@768r

selectOrSplit GPR32common:%vreg54 [784r,800r:0)  0@784r w=inf
assigning %vreg54 to %W9: W9 [784r,800r:0)  0@784r

selectOrSplit GPR64common:%vreg50 [816r,832r:0)  0@816r w=inf
assigning %vreg50 to %X8: W8 [816r,832r:0)  0@816r

selectOrSplit GPR64common:%vreg49 [832r,880r:0)  0@832r w=2.137158e-03
assigning %vreg49 to %X8: W8 [832r,880r:0)  0@832r

selectOrSplit GPR32common:%vreg47 [848r,864r:0)  0@848r w=inf
assigning %vreg47 to %W9: W9 [848r,864r:0)  0@848r

selectOrSplit GPR32common:%vreg46 [864r,880r:0)  0@864r w=inf
assigning %vreg46 to %W9: W9 [864r,880r:0)  0@864r

selectOrSplit GPR64common:%vreg42 [896r,912r:0)  0@896r w=inf
assigning %vreg42 to %X8: W8 [896r,912r:0)  0@896r

selectOrSplit GPR64common:%vreg41 [912r,960r:0)  0@912r w=2.137158e-03
assigning %vreg41 to %X8: W8 [912r,960r:0)  0@912r

selectOrSplit GPR64common:%vreg39 [928r,944r:0)  0@928r w=inf
assigning %vreg39 to %X9: W9 [928r,944r:0)  0@928r

selectOrSplit GPR64common:%vreg38 [944r,960r:0)  0@944r w=inf
assigning %vreg38 to %X9: W9 [944r,960r:0)  0@944r

selectOrSplit GPR64common:%vreg34 [976r,992r:0)  0@976r w=inf
assigning %vreg34 to %X8: W8 [976r,992r:0)  0@976r

selectOrSplit GPR64common:%vreg33 [992r,1040r:0)  0@992r w=2.137158e-03
assigning %vreg33 to %X8: W8 [992r,1040r:0)  0@992r

selectOrSplit GPR32common:%vreg31 [1008r,1024r:0)  0@1008r w=inf
assigning %vreg31 to %W9: W9 [1008r,1024r:0)  0@1008r

selectOrSplit GPR32common:%vreg30 [1024r,1040r:0)  0@1024r w=inf
assigning %vreg30 to %W9: W9 [1024r,1040r:0)  0@1024r

selectOrSplit GPR64common:%vreg26 [1056r,1072r:0)  0@1056r w=inf
assigning %vreg26 to %X8: W8 [1056r,1072r:0)  0@1056r

selectOrSplit GPR64common:%vreg25 [1072r,1088r:0)  0@1072r w=inf
assigning %vreg25 to %X8: W8 [1072r,1088r:0)  0@1072r

selectOrSplit GPR32:%vreg23 [1088r,1104r:0)  0@1088r w=inf
assigning %vreg23 to %W8: W8 [1088r,1104r:0)  0@1088r

selectOrSplit GPR64common:%vreg86 [1136r,1152r:0)  0@1136r w=inf
assigning %vreg86 to %X8: W8 [1136r,1152r:0)  0@1136r

selectOrSplit GPR64common:%vreg85 [1152r,1200r:0)  0@1152r w=1.139818e-03
assigning %vreg85 to %X8: W8 [1152r,1200r:0)  0@1152r

selectOrSplit GPR32common:%vreg83 [1168r,1184r:0)  0@1168r w=inf
assigning %vreg83 to %W9: W9 [1168r,1184r:0)  0@1168r

selectOrSplit GPR32common:%vreg82 [1184r,1200r:0)  0@1184r w=inf
assigning %vreg82 to %W9: W9 [1184r,1200r:0)  0@1184r

********** STACK TRANSFORMATION METADATA **********
********** Function: copy_output_until_stop
********** REGISTER MAP **********
[%vreg1 -> %X20] GPR64
[%vreg2 -> %X8] GPR64common
[%vreg4 -> %X0] GPR64sp
[%vreg5 -> %X19] GPR64
[%vreg9 -> %W8] GPR32
[%vreg11 -> %X8] GPR64common
[%vreg12 -> %X8] GPR64common
[%vreg16 -> %W9] GPR32
[%vreg17 -> %X9] GPR64common
[%vreg19 -> %W8] GPR32
[%vreg20 -> %X8] GPR64common
[%vreg23 -> %W8] GPR32
[%vreg25 -> %X8] GPR64common
[%vreg26 -> %X8] GPR64common
[%vreg30 -> %W9] GPR32common
[%vreg31 -> %W9] GPR32common
[%vreg33 -> %X8] GPR64common
[%vreg34 -> %X8] GPR64common
[%vreg38 -> %X9] GPR64common
[%vreg39 -> %X9] GPR64common
[%vreg41 -> %X8] GPR64common
[%vreg42 -> %X8] GPR64common
[%vreg46 -> %W9] GPR32common
[%vreg47 -> %W9] GPR32common
[%vreg49 -> %X8] GPR64common
[%vreg50 -> %X8] GPR64common
[%vreg54 -> %W9] GPR32common
[%vreg55 -> %W9] GPR32common
[%vreg56 -> %X8] GPR64common
[%vreg60 -> %X9] GPR64common
[%vreg62 -> %X10] GPR64common
[%vreg63 -> %X10] GPR64common
[%vreg65 -> %W8] GPR32
[%vreg68 -> %X8] GPR64common
[%vreg70 -> %X9] GPR64
[%vreg71 -> %X9] GPR64common
[%vreg76 -> %X8] GPR64
[%vreg77 -> %X8] GPR64common
[%vreg78 -> %W8] GPR32
[%vreg82 -> %W9] GPR32common
[%vreg83 -> %W9] GPR32common
[%vreg85 -> %X8] GPR64common
[%vreg86 -> %X8] GPR64common
[%vreg88 -> %W20] GPR32
[%vreg89 -> %X0] GPR64


Stackmap 0:
  STACKMAP 0, 0, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack0] GPR64:%vreg1

i8* %progress_out: in stack slot 1 (size: 1)
%struct.EState* %s: in register %X20 (vreg 1)
%struct.EState** %s.addr: in stack slot 0 (size: 8)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, %vreg88, %LR<earlyclobber,imp-def,dead>, ...; GPR32:%vreg88

i8 %32: in register %W20 (vreg 88)

Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack0] GPR64:%vreg1
  -> Call instruction SlotIndex 176B, searching vregs 0 -> 90 and stack slots 0 -> 2
    + vreg5 is live in register but not in stackmap
      Defining instruction: %vreg5<def> = COPY %LR; GPR64:%vreg5
      Value: generated value, 1 instruction(s)

  STACKMAP 1, 0, %vreg88, %LR<earlyclobber,imp-def,dead>, ...; GPR32:%vreg88
  -> Call instruction SlotIndex 1360B, searching vregs 0 -> 90 and stack slots 0 -> 2

********** REWRITE VIRTUAL REGISTERS **********
********** Function: copy_output_until_stop
********** REGISTER MAP **********
[%vreg1 -> %X20] GPR64
[%vreg2 -> %X8] GPR64common
[%vreg4 -> %X0] GPR64sp
[%vreg5 -> %X19] GPR64
[%vreg9 -> %W8] GPR32
[%vreg11 -> %X8] GPR64common
[%vreg12 -> %X8] GPR64common
[%vreg16 -> %W9] GPR32
[%vreg17 -> %X9] GPR64common
[%vreg19 -> %W8] GPR32
[%vreg20 -> %X8] GPR64common
[%vreg23 -> %W8] GPR32
[%vreg25 -> %X8] GPR64common
[%vreg26 -> %X8] GPR64common
[%vreg30 -> %W9] GPR32common
[%vreg31 -> %W9] GPR32common
[%vreg33 -> %X8] GPR64common
[%vreg34 -> %X8] GPR64common
[%vreg38 -> %X9] GPR64common
[%vreg39 -> %X9] GPR64common
[%vreg41 -> %X8] GPR64common
[%vreg42 -> %X8] GPR64common
[%vreg46 -> %W9] GPR32common
[%vreg47 -> %W9] GPR32common
[%vreg49 -> %X8] GPR64common
[%vreg50 -> %X8] GPR64common
[%vreg54 -> %W9] GPR32common
[%vreg55 -> %W9] GPR32common
[%vreg56 -> %X8] GPR64common
[%vreg60 -> %X9] GPR64common
[%vreg62 -> %X10] GPR64common
[%vreg63 -> %X10] GPR64common
[%vreg65 -> %W8] GPR32
[%vreg68 -> %X8] GPR64common
[%vreg70 -> %X9] GPR64
[%vreg71 -> %X9] GPR64common
[%vreg76 -> %X8] GPR64
[%vreg77 -> %X8] GPR64common
[%vreg78 -> %W8] GPR32
[%vreg82 -> %W9] GPR32common
[%vreg83 -> %W9] GPR32common
[%vreg85 -> %X8] GPR64common
[%vreg86 -> %X8] GPR64common
[%vreg88 -> %W20] GPR32
[%vreg89 -> %X0] GPR64

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %LR %X0
16B		%vreg5<def> = COPY %LR; GPR64:%vreg5
32B		%vreg1<def> = COPY %X0; GPR64:%vreg1
64B		%vreg2<def> = ADRP <ga:@copy_output_until_stop>[TF=1]; GPR64common:%vreg2
80B		%vreg4<def> = ADDXri %vreg2<kill>, <ga:@copy_output_until_stop>[TF=34], 0; GPR64sp:%vreg4 GPR64common:%vreg2
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		%X0<def> = COPY %vreg4<kill>; GPR64sp:%vreg4
160B		%X1<def> = COPY %vreg5; GPR64:%vreg5
176B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
224B		STACKMAP 0, 0, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack0] GPR64:%vreg1
240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
256B		STRXui %vreg1<kill>, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg1
272B		STRBBui %WZR, <fi#1>, 0; mem:ST1[FixedStack1]
	    Successors according to CFG: BB#1
> %X19<def> = COPY %LR
> %X20<def> = COPY %X0
> %X8<def> = ADRP <ga:@copy_output_until_stop>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@copy_output_until_stop>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19
> BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 0, 0, 0, <fi#1>, 0, %X20, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack0]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRXui %X20<kill>, <fi#0>, 0; mem:ST8[FixedStack0]
> STRBBui %WZR, <fi#1>, 0; mem:ST1[FixedStack1]
288B	BB#1: derived from LLVM BB %while.body
	    Live Ins: %X19
	    Predecessors according to CFG: BB#0 BB#7
304B		%vreg12<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg12
320B		%vreg11<def> = LDRXui %vreg12<kill>, 0; mem:LD8[%strm] GPR64common:%vreg11,%vreg12
336B		%vreg9<def> = LDRWui %vreg11<kill>, 8; mem:LD4[%avail_out] GPR32:%vreg9 GPR64common:%vreg11
352B		CBNZW %vreg9<kill>, <BB#3>; GPR32:%vreg9
	    Successors according to CFG: BB#3 BB#2
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %X8<def> = LDRXui %X8<kill>, 0; mem:LD8[%strm]
> %W8<def> = LDRWui %X8<kill>, 8; mem:LD4[%avail_out]
> CBNZW %W8<kill>, <BB#3>
368B	BB#2: derived from LLVM BB %if.then
	    Live Ins: %X19
	    Predecessors according to CFG: BB#1
384B		B <BB#8>
	    Successors according to CFG: BB#8
> B <BB#8>
400B	BB#3: derived from LLVM BB %if.end
	    Live Ins: %X19
	    Predecessors according to CFG: BB#1
416B		%vreg20<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg20
448B		%vreg17<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg17
456B		%vreg19<def> = LDRWui %vreg20<kill>, 30; mem:LD4[%state_out_pos] GPR32:%vreg19 GPR64common:%vreg20
464B		%vreg16<def> = LDRWui %vreg17<kill>, 29; mem:LD4[%numZ] GPR32:%vreg16 GPR64common:%vreg17
480B		%WZR<def> = SUBSWrr %vreg19<kill>, %vreg16<kill>, %NZCV<imp-def>; GPR32:%vreg19,%vreg16
496B		Bcc 11, <BB#5>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#5 BB#4
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %X9<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %W8<def> = LDRWui %X8<kill>, 30; mem:LD4[%state_out_pos]
> %W9<def> = LDRWui %X9<kill>, 29; mem:LD4[%numZ]
> %WZR<def> = SUBSWrr %W8<kill>, %W9<kill>, %NZCV<imp-def>
> Bcc 11, <BB#5>, %NZCV<imp-use,kill>
512B	BB#4: derived from LLVM BB %if.then.2
	    Live Ins: %X19
	    Predecessors according to CFG: BB#3
528B		B <BB#8>
	    Successors according to CFG: BB#8
> B <BB#8>
544B	BB#5: derived from LLVM BB %if.end.3
	    Live Ins: %X19
	    Predecessors according to CFG: BB#3
560B		%vreg78<def> = MOVi32imm 1; GPR32:%vreg78
576B		STRBBui %vreg78<kill>, <fi#1>, 0; mem:ST1[FixedStack1] GPR32:%vreg78
592B		%vreg77<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg77
624B		%vreg71<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg71
688B		%vreg63<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg63
692B		%vreg76<def> = LDRSWui %vreg77<kill>, 30; mem:LD4[%state_out_pos4] GPR64:%vreg76 GPR64common:%vreg77
696B		%vreg70<def> = LDRXui %vreg71<kill>, 10; mem:LD8[%zbits] GPR64:%vreg70 GPR64common:%vreg71
704B		%vreg62<def> = LDRXui %vreg63<kill>, 0; mem:LD8[%strm5] GPR64common:%vreg62,%vreg63
708B		%vreg68<def> = ADDXrr %vreg70<kill>, %vreg76<kill>; GPR64common:%vreg68 GPR64:%vreg70,%vreg76
712B		%vreg65<def> = LDRBBui %vreg68<kill>, 0; mem:LD1[%arrayidx] GPR32:%vreg65 GPR64common:%vreg68
720B		%vreg60<def> = LDRXui %vreg62<kill>, 3; mem:LD8[%next_out] GPR64common:%vreg60,%vreg62
736B		STRBBui %vreg65<kill>, %vreg60<kill>, 0; mem:ST1[%14] GPR32:%vreg65 GPR64common:%vreg60
752B		%vreg56<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg56
768B		%vreg55<def> = LDRWui %vreg56, 30; mem:LD4[%state_out_pos6] GPR32common:%vreg55 GPR64common:%vreg56
784B		%vreg54<def> = ADDWri %vreg55<kill>, 1, 0; GPR32common:%vreg54,%vreg55
800B		STRWui %vreg54<kill>, %vreg56<kill>, 30; mem:ST4[%state_out_pos6] GPR32common:%vreg54 GPR64common:%vreg56
816B		%vreg50<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg50
832B		%vreg49<def> = LDRXui %vreg50<kill>, 0; mem:LD8[%strm7] GPR64common:%vreg49,%vreg50
848B		%vreg47<def> = LDRWui %vreg49, 8; mem:LD4[%avail_out8] GPR32common:%vreg47 GPR64common:%vreg49
864B		%vreg46<def> = SUBWri %vreg47<kill>, 1, 0; GPR32common:%vreg46,%vreg47
880B		STRWui %vreg46<kill>, %vreg49<kill>, 8; mem:ST4[%avail_out8] GPR32common:%vreg46 GPR64common:%vreg49
896B		%vreg42<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg42
912B		%vreg41<def> = LDRXui %vreg42<kill>, 0; mem:LD8[%strm9] GPR64common:%vreg41,%vreg42
928B		%vreg39<def> = LDRXui %vreg41, 3; mem:LD8[%next_out10] GPR64common:%vreg39,%vreg41
944B		%vreg38<def> = ADDXri %vreg39<kill>, 1, 0; GPR64common:%vreg38,%vreg39
960B		STRXui %vreg38<kill>, %vreg41<kill>, 3; mem:ST8[%next_out10] GPR64common:%vreg38,%vreg41
976B		%vreg34<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg34
992B		%vreg33<def> = LDRXui %vreg34<kill>, 0; mem:LD8[%strm11] GPR64common:%vreg33,%vreg34
1008B		%vreg31<def> = LDRWui %vreg33, 9; mem:LD4[%total_out_lo32] GPR32common:%vreg31 GPR64common:%vreg33
1024B		%vreg30<def> = ADDWri %vreg31<kill>, 1, 0; GPR32common:%vreg30,%vreg31
1040B		STRWui %vreg30<kill>, %vreg33<kill>, 9; mem:ST4[%total_out_lo32] GPR32common:%vreg30 GPR64common:%vreg33
1056B		%vreg26<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg26
1072B		%vreg25<def> = LDRXui %vreg26<kill>, 0; mem:LD8[%strm13] GPR64common:%vreg25,%vreg26
1088B		%vreg23<def> = LDRWui %vreg25<kill>, 9; mem:LD4[%total_out_lo3214] GPR32:%vreg23 GPR64common:%vreg25
1104B		CBNZW %vreg23<kill>, <BB#7>; GPR32:%vreg23
	    Successors according to CFG: BB#7 BB#6
> %W8<def> = MOVi32imm 1
> STRBBui %W8<kill>, <fi#1>, 0; mem:ST1[FixedStack1]
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %X9<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %X10<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %X8<def> = LDRSWui %X8<kill>, 30; mem:LD4[%state_out_pos4]
> %X9<def> = LDRXui %X9<kill>, 10; mem:LD8[%zbits]
> %X10<def> = LDRXui %X10<kill>, 0; mem:LD8[%strm5]
> %X8<def> = ADDXrr %X9<kill>, %X8<kill>
> %W8<def> = LDRBBui %X8<kill>, 0; mem:LD1[%arrayidx]
> %X9<def> = LDRXui %X10<kill>, 3; mem:LD8[%next_out]
> STRBBui %W8<kill>, %X9<kill>, 0; mem:ST1[%14]
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %W9<def> = LDRWui %X8, 30; mem:LD4[%state_out_pos6]
> %W9<def> = ADDWri %W9<kill>, 1, 0
> STRWui %W9<kill>, %X8<kill>, 30; mem:ST4[%state_out_pos6]
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %X8<def> = LDRXui %X8<kill>, 0; mem:LD8[%strm7]
> %W9<def> = LDRWui %X8, 8; mem:LD4[%avail_out8]
> %W9<def> = SUBWri %W9<kill>, 1, 0
> STRWui %W9<kill>, %X8<kill>, 8; mem:ST4[%avail_out8]
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %X8<def> = LDRXui %X8<kill>, 0; mem:LD8[%strm9]
> %X9<def> = LDRXui %X8, 3; mem:LD8[%next_out10]
> %X9<def> = ADDXri %X9<kill>, 1, 0
> STRXui %X9<kill>, %X8<kill>, 3; mem:ST8[%next_out10]
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %X8<def> = LDRXui %X8<kill>, 0; mem:LD8[%strm11]
> %W9<def> = LDRWui %X8, 9; mem:LD4[%total_out_lo32]
> %W9<def> = ADDWri %W9<kill>, 1, 0
> STRWui %W9<kill>, %X8<kill>, 9; mem:ST4[%total_out_lo32]
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %X8<def> = LDRXui %X8<kill>, 0; mem:LD8[%strm13]
> %W8<def> = LDRWui %X8<kill>, 9; mem:LD4[%total_out_lo3214]
> CBNZW %W8<kill>, <BB#7>
1120B	BB#6: derived from LLVM BB %if.then.16
	    Live Ins: %X19
	    Predecessors according to CFG: BB#5
1136B		%vreg86<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg86
1152B		%vreg85<def> = LDRXui %vreg86<kill>, 0; mem:LD8[%strm17] GPR64common:%vreg85,%vreg86
1168B		%vreg83<def> = LDRWui %vreg85, 10; mem:LD4[%total_out_hi32] GPR32common:%vreg83 GPR64common:%vreg85
1184B		%vreg82<def> = ADDWri %vreg83<kill>, 1, 0; GPR32common:%vreg82,%vreg83
1200B		STRWui %vreg82<kill>, %vreg85<kill>, 10; mem:ST4[%total_out_hi32] GPR32common:%vreg82 GPR64common:%vreg85
	    Successors according to CFG: BB#7
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %X8<def> = LDRXui %X8<kill>, 0; mem:LD8[%strm17]
> %W9<def> = LDRWui %X8, 10; mem:LD4[%total_out_hi32]
> %W9<def> = ADDWri %W9<kill>, 1, 0
> STRWui %W9<kill>, %X8<kill>, 10; mem:ST4[%total_out_hi32]
1216B	BB#7: derived from LLVM BB %if.end.19
	    Live Ins: %X19
	    Predecessors according to CFG: BB#5 BB#6
1232B		B <BB#1>
	    Successors according to CFG: BB#1
> B <BB#1>
1248B	BB#8: derived from LLVM BB %while.end
	    Live Ins: %X19
	    Predecessors according to CFG: BB#4 BB#2
1264B		%vreg88<def> = LDRBBui <fi#1>, 0; mem:LD1[%progress_out] GPR32:%vreg88
1296B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1312B		%vreg89<def> = MOVaddr <ga:@copy_output_until_stop>[TF=1], <ga:@copy_output_until_stop>[TF=34]; GPR64:%vreg89
1328B		%X0<def> = COPY %vreg89<kill>; GPR64:%vreg89
1344B		%X1<def> = COPY %vreg5<kill>; GPR64:%vreg5
1360B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %SP<imp-def>
1376B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1392B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1408B		STACKMAP 1, 0, %vreg88, %LR<earlyclobber,imp-def,dead>, ...; GPR32:%vreg88
1424B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
1440B		%W0<def> = COPY %vreg88<kill>; GPR32:%vreg88
1456B		RET_ReallyLR %W0<imp-use>
> %W20<def> = LDRBBui <fi#1>, 0; mem:LD1[%progress_out]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = MOVaddr <ga:@copy_output_until_stop>[TF=1], <ga:@copy_output_until_stop>[TF=34]
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19<kill>
> BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %SP<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 1, 0, %W20, %LR<earlyclobber,imp-def,dead>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = COPY %W20<kill>
> RET_ReallyLR %W0<imp-use>
Computing live-in reg-units in ABI blocks.
0B	BB#0 W0#0 W30#0
Created 2 new intervals.
********** INTERVALS **********
W30 [0B,16r:0)[176r,176d:8)[224e,224d:3)[1984r,1984d:6)[2032e,2032d:2)[4512r,4512d:7)[4560e,4560d:1)[5488r,5488d:5)[5536e,5536d:4)  0@0B-phi 1@4560e 2@2032e 3@224e 4@5536e 5@5488r 6@1984r 7@4512r 8@176r
W0 [0B,32r:0)[144r,176r:5)[1968r,1984r:3)[4496r,4512r:4)[5456r,5488r:2)[5568r,5584r:1)  0@0B-phi 1@5568r 2@5456r 3@1968r 4@4496r 5@144r
%vreg0 [32r,48r:0)  0@32r
%vreg1 [48r,256r:0)  0@48r
%vreg4 [304r,320r:0)  0@304r
%vreg5 [288r,304r:0)  0@288r
%vreg6 [64r,80r:0)  0@64r
%vreg7 [80r,96r:0)  0@80r
%vreg8 [96r,144r:0)  0@96r
%vreg9 [112r,160r:0)  0@112r
%vreg10 [16r,5472r:0)  0@16r
%vreg14 [2880r,2896r:0)  0@2880r
%vreg15 [2864r,2880r:0)  0@2864r
%vreg17 [2848r,2896r:0)  0@2848r
%vreg18 [2832r,2848r:0)  0@2832r
%vreg21 [3008r,3024r:0)  0@3008r
%vreg23 [2992r,3008r:0)  0@2992r
%vreg24 [2976r,2992r:0)  0@2976r
%vreg27 [3104r,3120r:0)  0@3104r
%vreg28 [3088r,3104r:0)  0@3088r
%vreg32 [3328r,3344r:0)  0@3328r
%vreg33 [3312r,3328r:0)  0@3312r
%vreg34 [3296r,3344r:0)  0@3296r
%vreg39 [3264r,3280r:0)  0@3264r
%vreg41 [3248r,3264r:0)  0@3248r
%vreg43 [3232r,3248r:0)  0@3232r
%vreg44 [3216r,3232r:0)  0@3216r
%vreg45 [3184r,3200r:0)  0@3184r
%vreg48 [3408r,3424r:0)  0@3408r
%vreg49 [3392r,3408r:0)  0@3392r
%vreg53 [4240r,4256r:0)  0@4240r
%vreg54 [4224r,4240r:0)  0@4224r
%vreg55 [4208r,4256r:0)  0@4208r
%vreg58 [4320r,4336r:0)  0@4320r
%vreg59 [4304r,4320r:0)  0@4304r
%vreg63 [4768r,4784r:0)  0@4768r
%vreg64 [4752r,4768r:0)  0@4752r
%vreg65 [4736r,4784r:0)  0@4736r
%vreg68 [4400r,4416r:0)  0@4400r
%vreg69 [4384r,4400r:0)  0@4384r
%vreg71 [4464r,4496r:0)  0@4464r
%vreg72 [4608r,4688r:0)  0@4608r
%vreg74 [4672r,4688r:0)  0@4672r
%vreg77 [4640r,4656r:0)  0@4640r
%vreg78 [4624r,4656r:0)  0@4624r
%vreg81 [4144r,4160r:0)  0@4144r
%vreg82 [4128r,4160r:0)  0@4128r
%vreg86 [4096r,4112r:0)  0@4096r
%vreg87 [4080r,4096r:0)  0@4080r
%vreg88 [4064r,4112r:0)  0@4064r
%vreg93 [4032r,4048r:0)  0@4032r
%vreg95 [4016r,4032r:0)  0@4016r
%vreg96 [4000r,4016r:0)  0@4000r
%vreg101 [3984r,4032r:0)  0@3984r
%vreg102 [3968r,3984r:0)  0@3968r
%vreg103 [3952r,4048r:0)  0@3952r
%vreg104 [3472r,3936r:0)  0@3472r
%vreg108 [3920r,3936r:0)  0@3920r
%vreg110 [3904r,3920r:0)  0@3904r
%vreg111 [3888r,3904r:0)  0@3888r
%vreg116 [3856r,3872r:0)  0@3856r
%vreg117 [3872r,3920r:0)  0@3872r
%vreg118 [3840r,3856r:0)  0@3840r
%vreg121 [3808r,3824r:0)  0@3808r
%vreg124 [3792r,3824r:0)  0@3792r
%vreg126 [3776r,3792r:0)  0@3776r
%vreg127 [3488r,3504r:0)  0@3488r
%vreg128 [3504r,3760r:0)  0@3504r
%vreg130 [3728r,3744r:0)  0@3728r
%vreg131 [3744r,3760r:0)  0@3744r
%vreg132 [3760r,3776r:0)  0@3760r
%vreg134 [3696r,3712r:0)  0@3696r
%vreg135 [3712r,3744r:0)  0@3712r
%vreg138 [3680r,3696r:0)  0@3680r
%vreg141 [3664r,3680r:0)  0@3664r
%vreg143 [3648r,3680r:0)  0@3648r
%vreg145 [3632r,3648r:0)  0@3632r
%vreg146 [3616r,3632r:0)  0@3616r
%vreg148 [3600r,3792r:0)  0@3600r
%vreg149 [3584r,3600r:0)  0@3584r
%vreg152 [3552r,3568r:0)  0@3552r
%vreg154 [3536r,3552r:0)  0@3536r
%vreg155 [3520r,3536r:0)  0@3520r
%vreg158 [5120r,5136r:0)  0@5120r
%vreg160 [5104r,5120r:0)  0@5104r
%vreg161 [5088r,5104r:0)  0@5088r
%vreg165 [5056r,5072r:0)  0@5056r
%vreg166 [5040r,5056r:0)  0@5040r
%vreg168 [5024r,5072r:0)  0@5024r
%vreg169 [5008r,5024r:0)  0@5008r
%vreg173 [4976r,4992r:0)  0@4976r
%vreg174 [4960r,4976r:0)  0@4960r
%vreg176 [4944r,4992r:0)  0@4944r
%vreg177 [4928r,4944r:0)  0@4928r
%vreg181 [4896r,4912r:0)  0@4896r
%vreg182 [4880r,4896r:0)  0@4880r
%vreg184 [4864r,4912r:0)  0@4864r
%vreg185 [4848r,4864r:0)  0@4848r
%vreg189 [5216r,5232r:0)  0@5216r
%vreg190 [5200r,5216r:0)  0@5200r
%vreg192 [5184r,5232r:0)  0@5184r
%vreg193 [5168r,5184r:0)  0@5168r
%vreg197 [5296r,5312r:0)  0@5296r
%vreg198 [5280r,5296r:0)  0@5280r
%vreg199 [5264r,5312r:0)  0@5264r
%vreg203 [448r,464r:0)  0@448r
%vreg204 [432r,448r:0)  0@432r
%vreg206 [416r,464r:0)  0@416r
%vreg207 [400r,416r:0)  0@400r
%vreg210 [576r,592r:0)  0@576r
%vreg212 [560r,576r:0)  0@560r
%vreg213 [544r,560r:0)  0@544r
%vreg217 [800r,816r:0)  0@800r
%vreg218 [784r,800r:0)  0@784r
%vreg219 [768r,816r:0)  0@768r
%vreg224 [736r,752r:0)  0@736r
%vreg226 [720r,736r:0)  0@720r
%vreg228 [704r,720r:0)  0@704r
%vreg229 [688r,704r:0)  0@688r
%vreg230 [656r,672r:0)  0@656r
%vreg233 [880r,896r:0)  0@880r
%vreg234 [864r,880r:0)  0@864r
%vreg238 [1712r,1728r:0)  0@1712r
%vreg239 [1696r,1712r:0)  0@1696r
%vreg240 [1680r,1728r:0)  0@1680r
%vreg243 [1792r,1808r:0)  0@1792r
%vreg244 [1776r,1792r:0)  0@1776r
%vreg248 [2240r,2256r:0)  0@2240r
%vreg249 [2224r,2240r:0)  0@2224r
%vreg250 [2208r,2256r:0)  0@2208r
%vreg253 [1872r,1888r:0)  0@1872r
%vreg254 [1856r,1872r:0)  0@1856r
%vreg256 [1936r,1968r:0)  0@1936r
%vreg257 [2080r,2160r:0)  0@2080r
%vreg259 [2144r,2160r:0)  0@2144r
%vreg262 [2112r,2128r:0)  0@2112r
%vreg263 [2096r,2128r:0)  0@2096r
%vreg266 [1616r,1632r:0)  0@1616r
%vreg267 [1600r,1632r:0)  0@1600r
%vreg271 [1568r,1584r:0)  0@1568r
%vreg272 [1552r,1568r:0)  0@1552r
%vreg273 [1536r,1584r:0)  0@1536r
%vreg278 [1504r,1520r:0)  0@1504r
%vreg280 [1488r,1504r:0)  0@1488r
%vreg281 [1472r,1488r:0)  0@1472r
%vreg286 [1456r,1504r:0)  0@1456r
%vreg287 [1440r,1456r:0)  0@1440r
%vreg288 [1424r,1520r:0)  0@1424r
%vreg289 [944r,1408r:0)  0@944r
%vreg293 [1392r,1408r:0)  0@1392r
%vreg295 [1376r,1392r:0)  0@1376r
%vreg296 [1360r,1376r:0)  0@1360r
%vreg301 [1328r,1344r:0)  0@1328r
%vreg302 [1344r,1392r:0)  0@1344r
%vreg303 [1312r,1328r:0)  0@1312r
%vreg306 [1280r,1296r:0)  0@1280r
%vreg309 [1264r,1296r:0)  0@1264r
%vreg311 [1248r,1264r:0)  0@1248r
%vreg312 [960r,976r:0)  0@960r
%vreg313 [976r,1232r:0)  0@976r
%vreg315 [1200r,1216r:0)  0@1200r
%vreg316 [1216r,1232r:0)  0@1216r
%vreg317 [1232r,1248r:0)  0@1232r
%vreg319 [1168r,1184r:0)  0@1168r
%vreg320 [1184r,1216r:0)  0@1184r
%vreg323 [1152r,1168r:0)  0@1152r
%vreg326 [1136r,1152r:0)  0@1136r
%vreg328 [1120r,1152r:0)  0@1120r
%vreg330 [1104r,1120r:0)  0@1104r
%vreg331 [1088r,1104r:0)  0@1088r
%vreg333 [1072r,1264r:0)  0@1072r
%vreg334 [1056r,1072r:0)  0@1056r
%vreg337 [1024r,1040r:0)  0@1024r
%vreg339 [1008r,1024r:0)  0@1008r
%vreg340 [992r,1008r:0)  0@992r
%vreg343 [2592r,2608r:0)  0@2592r
%vreg345 [2576r,2592r:0)  0@2576r
%vreg346 [2560r,2576r:0)  0@2560r
%vreg350 [2528r,2544r:0)  0@2528r
%vreg351 [2512r,2528r:0)  0@2512r
%vreg353 [2496r,2544r:0)  0@2496r
%vreg354 [2480r,2496r:0)  0@2480r
%vreg358 [2448r,2464r:0)  0@2448r
%vreg359 [2432r,2448r:0)  0@2432r
%vreg361 [2416r,2464r:0)  0@2416r
%vreg362 [2400r,2416r:0)  0@2400r
%vreg366 [2368r,2384r:0)  0@2368r
%vreg367 [2352r,2368r:0)  0@2352r
%vreg369 [2336r,2384r:0)  0@2336r
%vreg370 [2320r,2336r:0)  0@2320r
%vreg374 [2688r,2704r:0)  0@2688r
%vreg375 [2672r,2688r:0)  0@2672r
%vreg377 [2656r,2704r:0)  0@2656r
%vreg378 [2640r,2656r:0)  0@2640r
%vreg379 [5408r,5408d:0)  0@5408r
%vreg380 [5392r,5568r:0)  0@5392r
%vreg381 [5440r,5456r:0)  0@5440r
RegMasks: 176r 1984r 4512r 5488r
********** MACHINEINSTRS **********
# Machine code for function copy_input_until_stop: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
  fi#1: size=1, align=1, at location [SP]
  fi#2: size=4, align=4, at location [SP]
  fi#3: size=1, align=1, at location [SP]
  fi#4: size=4, align=4, at location [SP]
  fi#5: size=1, align=1, at location [SP]
Function Live Ins: %X0 in %vreg0, %LR in %vreg10

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %LR
16B		%vreg10<def> = COPY %LR; GPR64:%vreg10
32B		%vreg0<def> = COPY %X0; GPR64:%vreg0
48B		%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
64B		%vreg6<def> = ADRP <ga:@copy_input_until_stop>[TF=1]; GPR64common:%vreg6
80B		%vreg7<def> = ADDXri %vreg6, <ga:@copy_input_until_stop>[TF=34], 0; GPR64sp:%vreg7 GPR64common:%vreg6
96B		%vreg8<def> = COPY %vreg7; GPR64all:%vreg8 GPR64sp:%vreg7
112B		%vreg9<def> = COPY %vreg10; GPR64all:%vreg9 GPR64:%vreg10
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		%X0<def> = COPY %vreg8; GPR64all:%vreg8
160B		%X1<def> = COPY %vreg9; GPR64all:%vreg9
176B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
224B		STACKMAP 0, 0, 0, <fi#3>, 0, 0, <fi#5>, 0, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack3](align=1) LD8[FixedStack5](align=1) LD8[FixedStack1](align=1) LD8[FixedStack0] LD8[FixedStack2](align=4) LD8[FixedStack4](align=4) GPR64:%vreg1
240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
256B		STRXui %vreg1, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg1
272B		STRBBui %WZR, <fi#1>, 0; mem:ST1[FixedStack1]
288B		%vreg5<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg5
304B		%vreg4<def> = LDRWui %vreg5, 2; mem:LD4[%mode] GPR32common:%vreg4 GPR64common:%vreg5
320B		%WZR<def> = SUBSWri %vreg4, 2, 0, %NZCV<imp-def>; GPR32common:%vreg4
336B		Bcc 1, <BB#20>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#20 BB#1

352B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
368B		B <BB#2>
	    Successors according to CFG: BB#2

384B	BB#2: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#1 BB#18
400B		%vreg207<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg207
416B		%vreg206<def> = LDRWui %vreg207, 27; mem:LD4[%nblock] GPR32:%vreg206 GPR64common:%vreg207
432B		%vreg204<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg204
448B		%vreg203<def> = LDRWui %vreg204, 28; mem:LD4[%nblockMAX] GPR32:%vreg203 GPR64common:%vreg204
464B		%WZR<def> = SUBSWrr %vreg206, %vreg203, %NZCV<imp-def>; GPR32:%vreg206,%vreg203
480B		Bcc 11, <BB#4>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#4 BB#3

496B	BB#3: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#2
512B		B <BB#19>
	    Successors according to CFG: BB#19

528B	BB#4: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#2
544B		%vreg213<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg213
560B		%vreg212<def> = LDRXui %vreg213, 0; mem:LD8[%strm] GPR64common:%vreg212,%vreg213
576B		%vreg210<def> = LDRWui %vreg212, 2; mem:LD4[%avail_in] GPR32:%vreg210 GPR64common:%vreg212
592B		CBNZW %vreg210, <BB#6>; GPR32:%vreg210
	    Successors according to CFG: BB#6 BB#5

608B	BB#5: derived from LLVM BB %if.then.4
	    Predecessors according to CFG: BB#4
624B		B <BB#19>
	    Successors according to CFG: BB#19

640B	BB#6: derived from LLVM BB %if.end.5
	    Predecessors according to CFG: BB#4
656B		%vreg230<def> = MOVi32imm 1; GPR32:%vreg230
672B		STRBBui %vreg230, <fi#1>, 0; mem:ST1[FixedStack1] GPR32:%vreg230
688B		%vreg229<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg229
704B		%vreg228<def> = LDRXui %vreg229, 0; mem:LD8[%strm6] GPR64common:%vreg228,%vreg229
720B		%vreg226<def> = LDRXui %vreg228, 0; mem:LD8[%next_in] GPR64common:%vreg226,%vreg228
736B		%vreg224<def> = LDRBBui %vreg226, 0; mem:LD1[%11] GPR32:%vreg224 GPR64common:%vreg226
752B		STRWui %vreg224, <fi#2>, 0; mem:ST4[FixedStack2] GPR32:%vreg224
768B		%vreg219<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg219
784B		%vreg218<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg218
800B		%vreg217<def> = LDRWui %vreg218, 23; mem:LD4[%state_in_ch] GPR32:%vreg217 GPR64common:%vreg218
816B		%WZR<def> = SUBSWrr %vreg219, %vreg217, %NZCV<imp-def>; GPR32:%vreg219,%vreg217
832B		Bcc 0, <BB#9>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#9 BB#7

848B	BB#7: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#6
864B		%vreg234<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg234
880B		%vreg233<def> = LDRWui %vreg234, 24; mem:LD4[%state_in_len] GPR32common:%vreg233 GPR64common:%vreg234
896B		%WZR<def> = SUBSWri %vreg233, 1, 0, %NZCV<imp-def>; GPR32common:%vreg233
912B		Bcc 1, <BB#9>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#9 BB#8

928B	BB#8: derived from LLVM BB %if.then.11
	    Predecessors according to CFG: BB#7
944B		%vreg289<def> = MOVi32imm 1; GPR32:%vreg289
960B		%vreg312<def> = ADRP <ga:@BZ2_crc32Table>[TF=1]; GPR64common:%vreg312
976B		%vreg313<def> = ADDXri %vreg312, <ga:@BZ2_crc32Table>[TF=34], 0; GPR64common:%vreg313,%vreg312
992B		%vreg340<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg340
1008B		%vreg339<def> = LDRWui %vreg340, 23; mem:LD4[%state_in_ch12] GPR32:%vreg339 GPR64common:%vreg340
1024B		%vreg337<def> = COPY %vreg339; GPR32:%vreg337,%vreg339
1040B		STRBBui %vreg337, <fi#3>, 0; mem:ST1[FixedStack3] GPR32:%vreg337
1056B		%vreg334<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg334
1072B		%vreg333<def> = LDRWui %vreg334, 162; mem:LD4[%blockCRC] GPR32:%vreg333 GPR64common:%vreg334
1088B		%vreg331<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg331
1104B		%vreg330<def> = LDRWui %vreg331, 162; mem:LD4[%blockCRC14] GPR32:%vreg330 GPR64common:%vreg331
1120B		%vreg328<def> = UBFMWri %vreg330, 24, 31; GPR32:%vreg328,%vreg330
1136B		%vreg326<def> = LDRBBui <fi#3>, 0; mem:LD1[FixedStack3] GPR32:%vreg326
1152B		%vreg323<def> = EORWrr %vreg328, %vreg326; GPR32:%vreg323,%vreg328,%vreg326
1168B		%vreg319<def> = SUBREG_TO_REG 0, %vreg323, 15; GPR64:%vreg319 GPR32:%vreg323
1184B		%vreg320<def> = UBFMXri %vreg319, 0, 31; GPR64:%vreg320,%vreg319
1200B		%vreg315<def> = MOVi64imm 4; GPR64:%vreg315
1216B		%vreg316<def> = MADDXrrr %vreg320, %vreg315, %XZR; GPR64:%vreg316,%vreg320,%vreg315
1232B		%vreg317<def> = ADDXrr %vreg313, %vreg316; GPR64common:%vreg317,%vreg313 GPR64:%vreg316
1248B		%vreg311<def> = LDRWui %vreg317, 0; mem:LD4[%arrayidx] GPR32:%vreg311 GPR64common:%vreg317
1264B		%vreg309<def> = EORWrs %vreg311, %vreg333, 8; GPR32:%vreg309,%vreg311,%vreg333
1280B		%vreg306<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg306
1296B		STRWui %vreg309, %vreg306, 162; mem:ST4[%blockCRC17] GPR32:%vreg309 GPR64common:%vreg306
1312B		%vreg303<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg303
1328B		%vreg301<def> = LDRWui %vreg303, 23; mem:LD4[%state_in_ch18] GPR32:%vreg301 GPR64common:%vreg303
1344B		%vreg302<def> = SUBREG_TO_REG 0, %vreg301, 15; GPR64:%vreg302 GPR32:%vreg301
1360B		%vreg296<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg296
1376B		%vreg295<def> = ADDXri %vreg296, 128, 0; GPR64common:%vreg295,%vreg296
1392B		%vreg293<def> = ADDXrr %vreg295, %vreg302; GPR64common:%vreg293,%vreg295 GPR64:%vreg302
1408B		STRBBui %vreg289, %vreg293, 0; mem:ST1[%arrayidx20] GPR32:%vreg289 GPR64common:%vreg293
1424B		%vreg288<def> = LDRBBui <fi#3>, 0; mem:LD1[FixedStack3] GPR32:%vreg288
1440B		%vreg287<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg287
1456B		%vreg286<def> = LDRSWui %vreg287, 27; mem:LD4[%nblock21] GPR64:%vreg286 GPR64common:%vreg287
1472B		%vreg281<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg281
1488B		%vreg280<def> = LDRXui %vreg281, 8; mem:LD8[%block] GPR64:%vreg280 GPR64common:%vreg281
1504B		%vreg278<def> = ADDXrr %vreg280, %vreg286; GPR64common:%vreg278 GPR64:%vreg280,%vreg286
1520B		STRBBui %vreg288, %vreg278, 0; mem:ST1[%arrayidx23] GPR32:%vreg288 GPR64common:%vreg278
1536B		%vreg273<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg273
1552B		%vreg272<def> = LDRWui %vreg273, 27; mem:LD4[%nblock24] GPR32common:%vreg272 GPR64common:%vreg273
1568B		%vreg271<def> = ADDWri %vreg272, 1, 0; GPR32common:%vreg271,%vreg272
1584B		STRWui %vreg271, %vreg273, 27; mem:ST4[%nblock24] GPR32common:%vreg271 GPR64common:%vreg273
1600B		%vreg267<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg267
1616B		%vreg266<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg266
1632B		STRWui %vreg267, %vreg266, 23; mem:ST4[%state_in_ch25] GPR32:%vreg267 GPR64common:%vreg266
1648B		B <BB#16>
	    Successors according to CFG: BB#16

1664B	BB#9: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#6 BB#7
1680B		%vreg240<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg240
1696B		%vreg239<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg239
1712B		%vreg238<def> = LDRWui %vreg239, 23; mem:LD4[%state_in_ch26] GPR32:%vreg238 GPR64common:%vreg239
1728B		%WZR<def> = SUBSWrr %vreg240, %vreg238, %NZCV<imp-def>; GPR32:%vreg240,%vreg238
1744B		Bcc 1, <BB#11>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#11 BB#10

1760B	BB#10: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#9
1776B		%vreg244<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg244
1792B		%vreg243<def> = LDRWui %vreg244, 24; mem:LD4[%state_in_len29] GPR32common:%vreg243 GPR64common:%vreg244
1808B		%WZR<def> = SUBSWri %vreg243, 255, 0, %NZCV<imp-def>; GPR32common:%vreg243
1824B		Bcc 1, <BB#14>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#14 BB#11

1840B	BB#11: derived from LLVM BB %if.then.32
	    Predecessors according to CFG: BB#9 BB#10
1856B		%vreg254<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg254
1872B		%vreg253<def> = LDRWui %vreg254, 23; mem:LD4[%state_in_ch33] GPR32common:%vreg253 GPR64common:%vreg254
1888B		%WZR<def> = SUBSWri %vreg253, 256, 0, %NZCV<imp-def>; GPR32common:%vreg253
1904B		Bcc 2, <BB#13>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#13 BB#12

1920B	BB#12: derived from LLVM BB %if.then.36
	    Predecessors according to CFG: BB#11
1936B		%vreg256<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg256
1952B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1968B		%X0<def> = COPY %vreg256; GPR64:%vreg256
1984B		BL <ga:@add_pair_to_block>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>
2000B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2016B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2032B		STACKMAP 1, 0, 0, <fi#3>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack3](align=1) LD8[FixedStack1](align=1) LD8[FixedStack0] LD8[FixedStack2](align=4)
2048B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#13

2064B	BB#13: derived from LLVM BB %if.end.37
	    Predecessors according to CFG: BB#11 BB#12
2080B		%vreg257<def> = MOVi32imm 1; GPR32:%vreg257
2096B		%vreg263<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg263
2112B		%vreg262<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg262
2128B		STRWui %vreg263, %vreg262, 23; mem:ST4[%state_in_ch38] GPR32:%vreg263 GPR64common:%vreg262
2144B		%vreg259<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg259
2160B		STRWui %vreg257, %vreg259, 24; mem:ST4[%state_in_len39] GPR32:%vreg257 GPR64common:%vreg259
2176B		B <BB#15>
	    Successors according to CFG: BB#15

2192B	BB#14: derived from LLVM BB %if.else.40
	    Predecessors according to CFG: BB#10
2208B		%vreg250<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg250
2224B		%vreg249<def> = LDRWui %vreg250, 24; mem:LD4[%state_in_len41] GPR32common:%vreg249 GPR64common:%vreg250
2240B		%vreg248<def> = ADDWri %vreg249, 1, 0; GPR32common:%vreg248,%vreg249
2256B		STRWui %vreg248, %vreg250, 24; mem:ST4[%state_in_len41] GPR32common:%vreg248 GPR64common:%vreg250
	    Successors according to CFG: BB#15

2272B	BB#15: derived from LLVM BB %if.end.43
	    Predecessors according to CFG: BB#14 BB#13
2288B		B <BB#16>
	    Successors according to CFG: BB#16

2304B	BB#16: derived from LLVM BB %if.end.44
	    Predecessors according to CFG: BB#15 BB#8
2320B		%vreg370<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg370
2336B		%vreg369<def> = LDRXui %vreg370, 0; mem:LD8[%strm45] GPR64common:%vreg369,%vreg370
2352B		%vreg367<def> = LDRXui %vreg369, 0; mem:LD8[%next_in46] GPR64common:%vreg367,%vreg369
2368B		%vreg366<def> = ADDXri %vreg367, 1, 0; GPR64common:%vreg366,%vreg367
2384B		STRXui %vreg366, %vreg369, 0; mem:ST8[%next_in46] GPR64common:%vreg366,%vreg369
2400B		%vreg362<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg362
2416B		%vreg361<def> = LDRXui %vreg362, 0; mem:LD8[%strm47] GPR64common:%vreg361,%vreg362
2432B		%vreg359<def> = LDRWui %vreg361, 2; mem:LD4[%avail_in48] GPR32common:%vreg359 GPR64common:%vreg361
2448B		%vreg358<def> = SUBWri %vreg359, 1, 0; GPR32common:%vreg358,%vreg359
2464B		STRWui %vreg358, %vreg361, 2; mem:ST4[%avail_in48] GPR32common:%vreg358 GPR64common:%vreg361
2480B		%vreg354<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg354
2496B		%vreg353<def> = LDRXui %vreg354, 0; mem:LD8[%strm49] GPR64common:%vreg353,%vreg354
2512B		%vreg351<def> = LDRWui %vreg353, 3; mem:LD4[%total_in_lo32] GPR32common:%vreg351 GPR64common:%vreg353
2528B		%vreg350<def> = ADDWri %vreg351, 1, 0; GPR32common:%vreg350,%vreg351
2544B		STRWui %vreg350, %vreg353, 3; mem:ST4[%total_in_lo32] GPR32common:%vreg350 GPR64common:%vreg353
2560B		%vreg346<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg346
2576B		%vreg345<def> = LDRXui %vreg346, 0; mem:LD8[%strm51] GPR64common:%vreg345,%vreg346
2592B		%vreg343<def> = LDRWui %vreg345, 3; mem:LD4[%total_in_lo3252] GPR32:%vreg343 GPR64common:%vreg345
2608B		CBNZW %vreg343, <BB#18>; GPR32:%vreg343
	    Successors according to CFG: BB#18 BB#17

2624B	BB#17: derived from LLVM BB %if.then.55
	    Predecessors according to CFG: BB#16
2640B		%vreg378<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg378
2656B		%vreg377<def> = LDRXui %vreg378, 0; mem:LD8[%strm56] GPR64common:%vreg377,%vreg378
2672B		%vreg375<def> = LDRWui %vreg377, 4; mem:LD4[%total_in_hi32] GPR32common:%vreg375 GPR64common:%vreg377
2688B		%vreg374<def> = ADDWri %vreg375, 1, 0; GPR32common:%vreg374,%vreg375
2704B		STRWui %vreg374, %vreg377, 4; mem:ST4[%total_in_hi32] GPR32common:%vreg374 GPR64common:%vreg377
	    Successors according to CFG: BB#18

2720B	BB#18: derived from LLVM BB %if.end.58
	    Predecessors according to CFG: BB#16 BB#17
2736B		B <BB#2>
	    Successors according to CFG: BB#2

2752B	BB#19: derived from LLVM BB %while.end
	    Predecessors according to CFG: BB#5 BB#3
2768B		B <BB#41>
	    Successors according to CFG: BB#41

2784B	BB#20: derived from LLVM BB %if.else.59
	    Predecessors according to CFG: BB#0
2800B		B <BB#21>
	    Successors according to CFG: BB#21

2816B	BB#21: derived from LLVM BB %while.body.60
	    Predecessors according to CFG: BB#20 BB#39
2832B		%vreg18<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg18
2848B		%vreg17<def> = LDRWui %vreg18, 27; mem:LD4[%nblock61] GPR32:%vreg17 GPR64common:%vreg18
2864B		%vreg15<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg15
2880B		%vreg14<def> = LDRWui %vreg15, 28; mem:LD4[%nblockMAX62] GPR32:%vreg14 GPR64common:%vreg15
2896B		%WZR<def> = SUBSWrr %vreg17, %vreg14, %NZCV<imp-def>; GPR32:%vreg17,%vreg14
2912B		Bcc 11, <BB#23>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#23 BB#22

2928B	BB#22: derived from LLVM BB %if.then.65
	    Predecessors according to CFG: BB#21
2944B		B <BB#40>
	    Successors according to CFG: BB#40

2960B	BB#23: derived from LLVM BB %if.end.66
	    Predecessors according to CFG: BB#21
2976B		%vreg24<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg24
2992B		%vreg23<def> = LDRXui %vreg24, 0; mem:LD8[%strm67] GPR64common:%vreg23,%vreg24
3008B		%vreg21<def> = LDRWui %vreg23, 2; mem:LD4[%avail_in68] GPR32:%vreg21 GPR64common:%vreg23
3024B		CBNZW %vreg21, <BB#25>; GPR32:%vreg21
	    Successors according to CFG: BB#25 BB#24

3040B	BB#24: derived from LLVM BB %if.then.71
	    Predecessors according to CFG: BB#23
3056B		B <BB#40>
	    Successors according to CFG: BB#40

3072B	BB#25: derived from LLVM BB %if.end.72
	    Predecessors according to CFG: BB#23
3088B		%vreg28<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg28
3104B		%vreg27<def> = LDRWui %vreg28, 4; mem:LD4[%avail_in_expect] GPR32:%vreg27 GPR64common:%vreg28
3120B		CBNZW %vreg27, <BB#27>; GPR32:%vreg27
	    Successors according to CFG: BB#27 BB#26

3136B	BB#26: derived from LLVM BB %if.then.75
	    Predecessors according to CFG: BB#25
3152B		B <BB#40>
	    Successors according to CFG: BB#40

3168B	BB#27: derived from LLVM BB %if.end.76
	    Predecessors according to CFG: BB#25
3184B		%vreg45<def> = MOVi32imm 1; GPR32:%vreg45
3200B		STRBBui %vreg45, <fi#1>, 0; mem:ST1[FixedStack1] GPR32:%vreg45
3216B		%vreg44<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg44
3232B		%vreg43<def> = LDRXui %vreg44, 0; mem:LD8[%strm78] GPR64common:%vreg43,%vreg44
3248B		%vreg41<def> = LDRXui %vreg43, 0; mem:LD8[%next_in79] GPR64common:%vreg41,%vreg43
3264B		%vreg39<def> = LDRBBui %vreg41, 0; mem:LD1[%78] GPR32:%vreg39 GPR64common:%vreg41
3280B		STRWui %vreg39, <fi#4>, 0; mem:ST4[FixedStack4] GPR32:%vreg39
3296B		%vreg34<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg34
3312B		%vreg33<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg33
3328B		%vreg32<def> = LDRWui %vreg33, 23; mem:LD4[%state_in_ch81] GPR32:%vreg32 GPR64common:%vreg33
3344B		%WZR<def> = SUBSWrr %vreg34, %vreg32, %NZCV<imp-def>; GPR32:%vreg34,%vreg32
3360B		Bcc 0, <BB#30>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#30 BB#28

3376B	BB#28: derived from LLVM BB %land.lhs.true.84
	    Predecessors according to CFG: BB#27
3392B		%vreg49<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg49
3408B		%vreg48<def> = LDRWui %vreg49, 24; mem:LD4[%state_in_len85] GPR32common:%vreg48 GPR64common:%vreg49
3424B		%WZR<def> = SUBSWri %vreg48, 1, 0, %NZCV<imp-def>; GPR32common:%vreg48
3440B		Bcc 1, <BB#30>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#30 BB#29

3456B	BB#29: derived from LLVM BB %if.then.88
	    Predecessors according to CFG: BB#28
3472B		%vreg104<def> = MOVi32imm 1; GPR32:%vreg104
3488B		%vreg127<def> = ADRP <ga:@BZ2_crc32Table>[TF=1]; GPR64common:%vreg127
3504B		%vreg128<def> = ADDXri %vreg127, <ga:@BZ2_crc32Table>[TF=34], 0; GPR64common:%vreg128,%vreg127
3520B		%vreg155<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg155
3536B		%vreg154<def> = LDRWui %vreg155, 23; mem:LD4[%state_in_ch90] GPR32:%vreg154 GPR64common:%vreg155
3552B		%vreg152<def> = COPY %vreg154; GPR32:%vreg152,%vreg154
3568B		STRBBui %vreg152, <fi#5>, 0; mem:ST1[FixedStack5] GPR32:%vreg152
3584B		%vreg149<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg149
3600B		%vreg148<def> = LDRWui %vreg149, 162; mem:LD4[%blockCRC92] GPR32:%vreg148 GPR64common:%vreg149
3616B		%vreg146<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg146
3632B		%vreg145<def> = LDRWui %vreg146, 162; mem:LD4[%blockCRC94] GPR32:%vreg145 GPR64common:%vreg146
3648B		%vreg143<def> = UBFMWri %vreg145, 24, 31; GPR32:%vreg143,%vreg145
3664B		%vreg141<def> = LDRBBui <fi#5>, 0; mem:LD1[FixedStack5] GPR32:%vreg141
3680B		%vreg138<def> = EORWrr %vreg143, %vreg141; GPR32:%vreg138,%vreg143,%vreg141
3696B		%vreg134<def> = SUBREG_TO_REG 0, %vreg138, 15; GPR64:%vreg134 GPR32:%vreg138
3712B		%vreg135<def> = UBFMXri %vreg134, 0, 31; GPR64:%vreg135,%vreg134
3728B		%vreg130<def> = MOVi64imm 4; GPR64:%vreg130
3744B		%vreg131<def> = MADDXrrr %vreg135, %vreg130, %XZR; GPR64:%vreg131,%vreg135,%vreg130
3760B		%vreg132<def> = ADDXrr %vreg128, %vreg131; GPR64common:%vreg132,%vreg128 GPR64:%vreg131
3776B		%vreg126<def> = LDRWui %vreg132, 0; mem:LD4[%arrayidx99] GPR32:%vreg126 GPR64common:%vreg132
3792B		%vreg124<def> = EORWrs %vreg126, %vreg148, 8; GPR32:%vreg124,%vreg126,%vreg148
3808B		%vreg121<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg121
3824B		STRWui %vreg124, %vreg121, 162; mem:ST4[%blockCRC101] GPR32:%vreg124 GPR64common:%vreg121
3840B		%vreg118<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg118
3856B		%vreg116<def> = LDRWui %vreg118, 23; mem:LD4[%state_in_ch102] GPR32:%vreg116 GPR64common:%vreg118
3872B		%vreg117<def> = SUBREG_TO_REG 0, %vreg116, 15; GPR64:%vreg117 GPR32:%vreg116
3888B		%vreg111<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg111
3904B		%vreg110<def> = ADDXri %vreg111, 128, 0; GPR64common:%vreg110,%vreg111
3920B		%vreg108<def> = ADDXrr %vreg110, %vreg117; GPR64common:%vreg108,%vreg110 GPR64:%vreg117
3936B		STRBBui %vreg104, %vreg108, 0; mem:ST1[%arrayidx105] GPR32:%vreg104 GPR64common:%vreg108
3952B		%vreg103<def> = LDRBBui <fi#5>, 0; mem:LD1[FixedStack5] GPR32:%vreg103
3968B		%vreg102<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg102
3984B		%vreg101<def> = LDRSWui %vreg102, 27; mem:LD4[%nblock106] GPR64:%vreg101 GPR64common:%vreg102
4000B		%vreg96<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg96
4016B		%vreg95<def> = LDRXui %vreg96, 8; mem:LD8[%block108] GPR64:%vreg95 GPR64common:%vreg96
4032B		%vreg93<def> = ADDXrr %vreg95, %vreg101; GPR64common:%vreg93 GPR64:%vreg95,%vreg101
4048B		STRBBui %vreg103, %vreg93, 0; mem:ST1[%arrayidx109] GPR32:%vreg103 GPR64common:%vreg93
4064B		%vreg88<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg88
4080B		%vreg87<def> = LDRWui %vreg88, 27; mem:LD4[%nblock110] GPR32common:%vreg87 GPR64common:%vreg88
4096B		%vreg86<def> = ADDWri %vreg87, 1, 0; GPR32common:%vreg86,%vreg87
4112B		STRWui %vreg86, %vreg88, 27; mem:ST4[%nblock110] GPR32common:%vreg86 GPR64common:%vreg88
4128B		%vreg82<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg82
4144B		%vreg81<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg81
4160B		STRWui %vreg82, %vreg81, 23; mem:ST4[%state_in_ch112] GPR32:%vreg82 GPR64common:%vreg81
4176B		B <BB#37>
	    Successors according to CFG: BB#37

4192B	BB#30: derived from LLVM BB %if.else.113
	    Predecessors according to CFG: BB#27 BB#28
4208B		%vreg55<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg55
4224B		%vreg54<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg54
4240B		%vreg53<def> = LDRWui %vreg54, 23; mem:LD4[%state_in_ch114] GPR32:%vreg53 GPR64common:%vreg54
4256B		%WZR<def> = SUBSWrr %vreg55, %vreg53, %NZCV<imp-def>; GPR32:%vreg55,%vreg53
4272B		Bcc 1, <BB#32>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#32 BB#31

4288B	BB#31: derived from LLVM BB %lor.lhs.false.117
	    Predecessors according to CFG: BB#30
4304B		%vreg59<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg59
4320B		%vreg58<def> = LDRWui %vreg59, 24; mem:LD4[%state_in_len118] GPR32common:%vreg58 GPR64common:%vreg59
4336B		%WZR<def> = SUBSWri %vreg58, 255, 0, %NZCV<imp-def>; GPR32common:%vreg58
4352B		Bcc 1, <BB#35>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#35 BB#32

4368B	BB#32: derived from LLVM BB %if.then.121
	    Predecessors according to CFG: BB#30 BB#31
4384B		%vreg69<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg69
4400B		%vreg68<def> = LDRWui %vreg69, 23; mem:LD4[%state_in_ch122] GPR32common:%vreg68 GPR64common:%vreg69
4416B		%WZR<def> = SUBSWri %vreg68, 256, 0, %NZCV<imp-def>; GPR32common:%vreg68
4432B		Bcc 2, <BB#34>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#34 BB#33

4448B	BB#33: derived from LLVM BB %if.then.125
	    Predecessors according to CFG: BB#32
4464B		%vreg71<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg71
4480B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4496B		%X0<def> = COPY %vreg71; GPR64:%vreg71
4512B		BL <ga:@add_pair_to_block>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>
4528B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4544B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4560B		STACKMAP 2, 0, 0, <fi#5>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack5](align=1) LD8[FixedStack1](align=1) LD8[FixedStack0] LD8[FixedStack4](align=4)
4576B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#34

4592B	BB#34: derived from LLVM BB %if.end.126
	    Predecessors according to CFG: BB#32 BB#33
4608B		%vreg72<def> = MOVi32imm 1; GPR32:%vreg72
4624B		%vreg78<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg78
4640B		%vreg77<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg77
4656B		STRWui %vreg78, %vreg77, 23; mem:ST4[%state_in_ch127] GPR32:%vreg78 GPR64common:%vreg77
4672B		%vreg74<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg74
4688B		STRWui %vreg72, %vreg74, 24; mem:ST4[%state_in_len128] GPR32:%vreg72 GPR64common:%vreg74
4704B		B <BB#36>
	    Successors according to CFG: BB#36

4720B	BB#35: derived from LLVM BB %if.else.129
	    Predecessors according to CFG: BB#31
4736B		%vreg65<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg65
4752B		%vreg64<def> = LDRWui %vreg65, 24; mem:LD4[%state_in_len130] GPR32common:%vreg64 GPR64common:%vreg65
4768B		%vreg63<def> = ADDWri %vreg64, 1, 0; GPR32common:%vreg63,%vreg64
4784B		STRWui %vreg63, %vreg65, 24; mem:ST4[%state_in_len130] GPR32common:%vreg63 GPR64common:%vreg65
	    Successors according to CFG: BB#36

4800B	BB#36: derived from LLVM BB %if.end.132
	    Predecessors according to CFG: BB#35 BB#34
4816B		B <BB#37>
	    Successors according to CFG: BB#37

4832B	BB#37: derived from LLVM BB %if.end.133
	    Predecessors according to CFG: BB#36 BB#29
4848B		%vreg185<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg185
4864B		%vreg184<def> = LDRXui %vreg185, 0; mem:LD8[%strm134] GPR64common:%vreg184,%vreg185
4880B		%vreg182<def> = LDRXui %vreg184, 0; mem:LD8[%next_in135] GPR64common:%vreg182,%vreg184
4896B		%vreg181<def> = ADDXri %vreg182, 1, 0; GPR64common:%vreg181,%vreg182
4912B		STRXui %vreg181, %vreg184, 0; mem:ST8[%next_in135] GPR64common:%vreg181,%vreg184
4928B		%vreg177<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg177
4944B		%vreg176<def> = LDRXui %vreg177, 0; mem:LD8[%strm137] GPR64common:%vreg176,%vreg177
4960B		%vreg174<def> = LDRWui %vreg176, 2; mem:LD4[%avail_in138] GPR32common:%vreg174 GPR64common:%vreg176
4976B		%vreg173<def> = SUBWri %vreg174, 1, 0; GPR32common:%vreg173,%vreg174
4992B		STRWui %vreg173, %vreg176, 2; mem:ST4[%avail_in138] GPR32common:%vreg173 GPR64common:%vreg176
5008B		%vreg169<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg169
5024B		%vreg168<def> = LDRXui %vreg169, 0; mem:LD8[%strm140] GPR64common:%vreg168,%vreg169
5040B		%vreg166<def> = LDRWui %vreg168, 3; mem:LD4[%total_in_lo32141] GPR32common:%vreg166 GPR64common:%vreg168
5056B		%vreg165<def> = ADDWri %vreg166, 1, 0; GPR32common:%vreg165,%vreg166
5072B		STRWui %vreg165, %vreg168, 3; mem:ST4[%total_in_lo32141] GPR32common:%vreg165 GPR64common:%vreg168
5088B		%vreg161<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg161
5104B		%vreg160<def> = LDRXui %vreg161, 0; mem:LD8[%strm143] GPR64common:%vreg160,%vreg161
5120B		%vreg158<def> = LDRWui %vreg160, 3; mem:LD4[%total_in_lo32144] GPR32:%vreg158 GPR64common:%vreg160
5136B		CBNZW %vreg158, <BB#39>; GPR32:%vreg158
	    Successors according to CFG: BB#39 BB#38

5152B	BB#38: derived from LLVM BB %if.then.147
	    Predecessors according to CFG: BB#37
5168B		%vreg193<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg193
5184B		%vreg192<def> = LDRXui %vreg193, 0; mem:LD8[%strm148] GPR64common:%vreg192,%vreg193
5200B		%vreg190<def> = LDRWui %vreg192, 4; mem:LD4[%total_in_hi32149] GPR32common:%vreg190 GPR64common:%vreg192
5216B		%vreg189<def> = ADDWri %vreg190, 1, 0; GPR32common:%vreg189,%vreg190
5232B		STRWui %vreg189, %vreg192, 4; mem:ST4[%total_in_hi32149] GPR32common:%vreg189 GPR64common:%vreg192
	    Successors according to CFG: BB#39

5248B	BB#39: derived from LLVM BB %if.end.151
	    Predecessors according to CFG: BB#37 BB#38
5264B		%vreg199<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg199
5280B		%vreg198<def> = LDRWui %vreg199, 4; mem:LD4[%avail_in_expect152] GPR32common:%vreg198 GPR64common:%vreg199
5296B		%vreg197<def> = SUBWri %vreg198, 1, 0; GPR32common:%vreg197,%vreg198
5312B		STRWui %vreg197, %vreg199, 4; mem:ST4[%avail_in_expect152] GPR32common:%vreg197 GPR64common:%vreg199
5328B		B <BB#21>
	    Successors according to CFG: BB#21

5344B	BB#40: derived from LLVM BB %while.end.154
	    Predecessors according to CFG: BB#26 BB#24 BB#22
5360B		B <BB#41>
	    Successors according to CFG: BB#41

5376B	BB#41: derived from LLVM BB %if.end.155
	    Predecessors according to CFG: BB#40 BB#19
5392B		%vreg380<def> = LDRBBui <fi#1>, 0; mem:LD1[%progress_in] GPR32:%vreg380
5408B		%vreg379<def,dead> = COPY %vreg380; GPR32all:%vreg379 GPR32:%vreg380
5424B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5440B		%vreg381<def> = MOVaddr <ga:@copy_input_until_stop>[TF=1], <ga:@copy_input_until_stop>[TF=34]; GPR64:%vreg381
5456B		%X0<def> = COPY %vreg381; GPR64:%vreg381
5472B		%X1<def> = COPY %vreg10; GPR64:%vreg10
5488B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %SP<imp-def>
5504B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5520B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5536B		STACKMAP 3, 0, %vreg380, %LR<earlyclobber,imp-def,dead>, ...; GPR32:%vreg380
5552B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5568B		%W0<def> = COPY %vreg380; GPR32:%vreg380
5584B		RET_ReallyLR %W0<imp-use>

# End machine code for function copy_input_until_stop.

********** SIMPLE REGISTER COALESCING **********
********** Function: copy_input_until_stop
********** JOINING INTERVALS ***********
while.body:
if.else:
if.then.32:
if.end.44:
while.body.60:
if.else.113:
if.then.121:
if.end.133:
if.end:
if.end.5:
land.lhs.true:
lor.lhs.false:
if.end.37:
if.end.43:
if.end.58:
if.end.66:
if.end.72:
if.end.76:
land.lhs.true.84:
lor.lhs.false.117:
if.end.126:
if.end.132:
if.end.151:
if.then.11:
1168B	%vreg319<def> = SUBREG_TO_REG 0, %vreg323, 15; GPR64:%vreg319 GPR32:%vreg323
	Considering merging to GPR64 with %vreg323 in %vreg319:sub_32
		RHS = %vreg323 [1152r,1168r:0)  0@1152r
		LHS = %vreg319 [1168r,1184r:0)  0@1168r
		merge %vreg319:0@1168r into %vreg323:0@1152r --> @1152r
		erased:	1168r	%vreg319<def> = SUBREG_TO_REG 0, %vreg323, 15; GPR64:%vreg319 GPR32:%vreg323
		updated: 1152B	%vreg319:sub_32<def,read-undef> = EORWrr %vreg328, %vreg326; GPR64:%vreg319 GPR32:%vreg328,%vreg326
	Success: %vreg323:sub_32 -> %vreg319
	Result = %vreg319 [1152r,1184r:0)  0@1152r
1344B	%vreg302<def> = SUBREG_TO_REG 0, %vreg301, 15; GPR64:%vreg302 GPR32:%vreg301
	Considering merging to GPR64 with %vreg301 in %vreg302:sub_32
		RHS = %vreg301 [1328r,1344r:0)  0@1328r
		LHS = %vreg302 [1344r,1392r:0)  0@1344r
		merge %vreg302:0@1344r into %vreg301:0@1328r --> @1328r
		erased:	1344r	%vreg302<def> = SUBREG_TO_REG 0, %vreg301, 15; GPR64:%vreg302 GPR32:%vreg301
		updated: 1328B	%vreg302:sub_32<def,read-undef> = LDRWui %vreg303, 23; mem:LD4[%state_in_ch18] GPR64:%vreg302 GPR64common:%vreg303
	Success: %vreg301:sub_32 -> %vreg302
	Result = %vreg302 [1328r,1392r:0)  0@1328r
if.then.36:
1968B	%X0<def> = COPY %vreg256; GPR64:%vreg256
	Considering merging %vreg256 with %X0
	Can only merge into reserved registers.
if.else.40:
if.then.55:
if.then.88:
3696B	%vreg134<def> = SUBREG_TO_REG 0, %vreg138, 15; GPR64:%vreg134 GPR32:%vreg138
	Considering merging to GPR64 with %vreg138 in %vreg134:sub_32
		RHS = %vreg138 [3680r,3696r:0)  0@3680r
		LHS = %vreg134 [3696r,3712r:0)  0@3696r
		merge %vreg134:0@3696r into %vreg138:0@3680r --> @3680r
		erased:	3696r	%vreg134<def> = SUBREG_TO_REG 0, %vreg138, 15; GPR64:%vreg134 GPR32:%vreg138
		updated: 3680B	%vreg134:sub_32<def,read-undef> = EORWrr %vreg143, %vreg141; GPR64:%vreg134 GPR32:%vreg143,%vreg141
	Success: %vreg138:sub_32 -> %vreg134
	Result = %vreg134 [3680r,3712r:0)  0@3680r
3872B	%vreg117<def> = SUBREG_TO_REG 0, %vreg116, 15; GPR64:%vreg117 GPR32:%vreg116
	Considering merging to GPR64 with %vreg116 in %vreg117:sub_32
		RHS = %vreg116 [3856r,3872r:0)  0@3856r
		LHS = %vreg117 [3872r,3920r:0)  0@3872r
		merge %vreg117:0@3872r into %vreg116:0@3856r --> @3856r
		erased:	3872r	%vreg117<def> = SUBREG_TO_REG 0, %vreg116, 15; GPR64:%vreg117 GPR32:%vreg116
		updated: 3856B	%vreg117:sub_32<def,read-undef> = LDRWui %vreg118, 23; mem:LD4[%state_in_ch102] GPR64:%vreg117 GPR64common:%vreg118
	Success: %vreg116:sub_32 -> %vreg117
	Result = %vreg117 [3856r,3920r:0)  0@3856r
if.then.125:
4496B	%X0<def> = COPY %vreg71; GPR64:%vreg71
	Considering merging %vreg71 with %X0
	Can only merge into reserved registers.
if.else.129:
if.then.147:
1024B	%vreg337<def> = COPY %vreg339; GPR32:%vreg337,%vreg339
	Considering merging to GPR32 with %vreg339 in %vreg337
		RHS = %vreg339 [1008r,1024r:0)  0@1008r
		LHS = %vreg337 [1024r,1040r:0)  0@1024r
		merge %vreg337:0@1024r into %vreg339:0@1008r --> @1008r
		erased:	1024r	%vreg337<def> = COPY %vreg339; GPR32:%vreg337,%vreg339
		updated: 1008B	%vreg337<def> = LDRWui %vreg340, 23; mem:LD4[%state_in_ch12] GPR32:%vreg337 GPR64common:%vreg340
	Success: %vreg339 -> %vreg337
	Result = %vreg337 [1008r,1040r:0)  0@1008r
3552B	%vreg152<def> = COPY %vreg154; GPR32:%vreg152,%vreg154
	Considering merging to GPR32 with %vreg154 in %vreg152
		RHS = %vreg154 [3536r,3552r:0)  0@3536r
		LHS = %vreg152 [3552r,3568r:0)  0@3552r
		merge %vreg152:0@3552r into %vreg154:0@3536r --> @3536r
		erased:	3552r	%vreg152<def> = COPY %vreg154; GPR32:%vreg152,%vreg154
		updated: 3536B	%vreg152<def> = LDRWui %vreg155, 23; mem:LD4[%state_in_ch90] GPR32:%vreg152 GPR64common:%vreg155
	Success: %vreg154 -> %vreg152
	Result = %vreg152 [3536r,3568r:0)  0@3536r
while.end.154:
while.end:
entry:
16B	%vreg10<def> = COPY %LR; GPR64:%vreg10
	Considering merging %vreg10 with %LR
	Can only merge into reserved registers.
32B	%vreg0<def> = COPY %X0; GPR64:%vreg0
	Considering merging %vreg0 with %X0
	Can only merge into reserved registers.
144B	%X0<def> = COPY %vreg8; GPR64all:%vreg8
	Considering merging %vreg8 with %X0
	Can only merge into reserved registers.
160B	%X1<def> = COPY %vreg9; GPR64all:%vreg9
	Considering merging %vreg9 with %X1
	Can only merge into reserved registers.
if.then:
if.then.2:
if.then.4:
if.else.59:
if.then.65:
if.then.71:
if.then.75:
if.end.155:
5456B	%X0<def> = COPY %vreg381; GPR64:%vreg381
	Considering merging %vreg381 with %X0
	Can only merge into reserved registers.
5472B	%X1<def> = COPY %vreg10; GPR64:%vreg10
	Considering merging %vreg10 with %X1
	Can only merge into reserved registers.
5568B	%W0<def> = COPY %vreg380; GPR32:%vreg380
	Considering merging %vreg380 with %W0
	Can only merge into reserved registers.
48B	%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
	Considering merging to GPR64 with %vreg0 in %vreg1
		RHS = %vreg0 [32r,48r:0)  0@32r
		LHS = %vreg1 [48r,256r:0)  0@48r
		merge %vreg1:0@48r into %vreg0:0@32r --> @32r
		erased:	48r	%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
		updated: 32B	%vreg1<def> = COPY %X0; GPR64:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [32r,256r:0)  0@32r
96B	%vreg8<def> = COPY %vreg7; GPR64all:%vreg8 GPR64sp:%vreg7
	Considering merging to GPR64sp with %vreg7 in %vreg8
		RHS = %vreg7 [80r,96r:0)  0@80r
		LHS = %vreg8 [96r,144r:0)  0@96r
		merge %vreg8:0@96r into %vreg7:0@80r --> @80r
		erased:	96r	%vreg8<def> = COPY %vreg7; GPR64all:%vreg8 GPR64sp:%vreg7
		updated: 80B	%vreg8<def> = ADDXri %vreg6, <ga:@copy_input_until_stop>[TF=34], 0; GPR64sp:%vreg8 GPR64common:%vreg6
	Success: %vreg7 -> %vreg8
	Result = %vreg8 [80r,144r:0)  0@80r
112B	%vreg9<def> = COPY %vreg10; GPR64all:%vreg9 GPR64:%vreg10
	Considering merging to GPR64 with %vreg10 in %vreg9
		RHS = %vreg10 [16r,5472r:0)  0@16r
		LHS = %vreg9 [112r,160r:0)  0@112r
		merge %vreg9:0@112r into %vreg10:0@16r --> @16r
		erased:	112r	%vreg9<def> = COPY %vreg10; GPR64all:%vreg9 GPR64:%vreg10
		updated: 16B	%vreg9<def> = COPY %LR; GPR64:%vreg9
		updated: 5472B	%X1<def> = COPY %vreg9; GPR64:%vreg9
	Success: %vreg10 -> %vreg9
	Result = %vreg9 [16r,5472r:0)  0@16r
5408B	%vreg379<def,dead> = COPY %vreg380; GPR32all:%vreg379 GPR32:%vreg380
	Copy is dead.
Deleting dead def 5408r	%vreg379<def,dead> = COPY %vreg380; GPR32all:%vreg379 GPR32:%vreg380
Shrink: %vreg380 [5392r,5568r:0)  0@5392r
Shrunk: %vreg380 [5392r,5568r:0)  0@5392r
144B	%X0<def> = COPY %vreg8; GPR64sp:%vreg8
	Considering merging %vreg8 with %X0
	Can only merge into reserved registers.
160B	%X1<def> = COPY %vreg9; GPR64:%vreg9
	Considering merging %vreg9 with %X1
	Can only merge into reserved registers.
5472B	%X1<def> = COPY %vreg9; GPR64:%vreg9
	Considering merging %vreg9 with %X1
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
W30 [0B,16r:0)[176r,176d:8)[224e,224d:3)[1984r,1984d:6)[2032e,2032d:2)[4512r,4512d:7)[4560e,4560d:1)[5488r,5488d:5)[5536e,5536d:4)  0@0B-phi 1@4560e 2@2032e 3@224e 4@5536e 5@5488r 6@1984r 7@4512r 8@176r
W0 [0B,32r:0)[144r,176r:5)[1968r,1984r:3)[4496r,4512r:4)[5456r,5488r:2)[5568r,5584r:1)  0@0B-phi 1@5568r 2@5456r 3@1968r 4@4496r 5@144r
%vreg1 [32r,256r:0)  0@32r
%vreg4 [304r,320r:0)  0@304r
%vreg5 [288r,304r:0)  0@288r
%vreg6 [64r,80r:0)  0@64r
%vreg8 [80r,144r:0)  0@80r
%vreg9 [16r,5472r:0)  0@16r
%vreg14 [2880r,2896r:0)  0@2880r
%vreg15 [2864r,2880r:0)  0@2864r
%vreg17 [2848r,2896r:0)  0@2848r
%vreg18 [2832r,2848r:0)  0@2832r
%vreg21 [3008r,3024r:0)  0@3008r
%vreg23 [2992r,3008r:0)  0@2992r
%vreg24 [2976r,2992r:0)  0@2976r
%vreg27 [3104r,3120r:0)  0@3104r
%vreg28 [3088r,3104r:0)  0@3088r
%vreg32 [3328r,3344r:0)  0@3328r
%vreg33 [3312r,3328r:0)  0@3312r
%vreg34 [3296r,3344r:0)  0@3296r
%vreg39 [3264r,3280r:0)  0@3264r
%vreg41 [3248r,3264r:0)  0@3248r
%vreg43 [3232r,3248r:0)  0@3232r
%vreg44 [3216r,3232r:0)  0@3216r
%vreg45 [3184r,3200r:0)  0@3184r
%vreg48 [3408r,3424r:0)  0@3408r
%vreg49 [3392r,3408r:0)  0@3392r
%vreg53 [4240r,4256r:0)  0@4240r
%vreg54 [4224r,4240r:0)  0@4224r
%vreg55 [4208r,4256r:0)  0@4208r
%vreg58 [4320r,4336r:0)  0@4320r
%vreg59 [4304r,4320r:0)  0@4304r
%vreg63 [4768r,4784r:0)  0@4768r
%vreg64 [4752r,4768r:0)  0@4752r
%vreg65 [4736r,4784r:0)  0@4736r
%vreg68 [4400r,4416r:0)  0@4400r
%vreg69 [4384r,4400r:0)  0@4384r
%vreg71 [4464r,4496r:0)  0@4464r
%vreg72 [4608r,4688r:0)  0@4608r
%vreg74 [4672r,4688r:0)  0@4672r
%vreg77 [4640r,4656r:0)  0@4640r
%vreg78 [4624r,4656r:0)  0@4624r
%vreg81 [4144r,4160r:0)  0@4144r
%vreg82 [4128r,4160r:0)  0@4128r
%vreg86 [4096r,4112r:0)  0@4096r
%vreg87 [4080r,4096r:0)  0@4080r
%vreg88 [4064r,4112r:0)  0@4064r
%vreg93 [4032r,4048r:0)  0@4032r
%vreg95 [4016r,4032r:0)  0@4016r
%vreg96 [4000r,4016r:0)  0@4000r
%vreg101 [3984r,4032r:0)  0@3984r
%vreg102 [3968r,3984r:0)  0@3968r
%vreg103 [3952r,4048r:0)  0@3952r
%vreg104 [3472r,3936r:0)  0@3472r
%vreg108 [3920r,3936r:0)  0@3920r
%vreg110 [3904r,3920r:0)  0@3904r
%vreg111 [3888r,3904r:0)  0@3888r
%vreg117 [3856r,3920r:0)  0@3856r
%vreg118 [3840r,3856r:0)  0@3840r
%vreg121 [3808r,3824r:0)  0@3808r
%vreg124 [3792r,3824r:0)  0@3792r
%vreg126 [3776r,3792r:0)  0@3776r
%vreg127 [3488r,3504r:0)  0@3488r
%vreg128 [3504r,3760r:0)  0@3504r
%vreg130 [3728r,3744r:0)  0@3728r
%vreg131 [3744r,3760r:0)  0@3744r
%vreg132 [3760r,3776r:0)  0@3760r
%vreg134 [3680r,3712r:0)  0@3680r
%vreg135 [3712r,3744r:0)  0@3712r
%vreg141 [3664r,3680r:0)  0@3664r
%vreg143 [3648r,3680r:0)  0@3648r
%vreg145 [3632r,3648r:0)  0@3632r
%vreg146 [3616r,3632r:0)  0@3616r
%vreg148 [3600r,3792r:0)  0@3600r
%vreg149 [3584r,3600r:0)  0@3584r
%vreg152 [3536r,3568r:0)  0@3536r
%vreg155 [3520r,3536r:0)  0@3520r
%vreg158 [5120r,5136r:0)  0@5120r
%vreg160 [5104r,5120r:0)  0@5104r
%vreg161 [5088r,5104r:0)  0@5088r
%vreg165 [5056r,5072r:0)  0@5056r
%vreg166 [5040r,5056r:0)  0@5040r
%vreg168 [5024r,5072r:0)  0@5024r
%vreg169 [5008r,5024r:0)  0@5008r
%vreg173 [4976r,4992r:0)  0@4976r
%vreg174 [4960r,4976r:0)  0@4960r
%vreg176 [4944r,4992r:0)  0@4944r
%vreg177 [4928r,4944r:0)  0@4928r
%vreg181 [4896r,4912r:0)  0@4896r
%vreg182 [4880r,4896r:0)  0@4880r
%vreg184 [4864r,4912r:0)  0@4864r
%vreg185 [4848r,4864r:0)  0@4848r
%vreg189 [5216r,5232r:0)  0@5216r
%vreg190 [5200r,5216r:0)  0@5200r
%vreg192 [5184r,5232r:0)  0@5184r
%vreg193 [5168r,5184r:0)  0@5168r
%vreg197 [5296r,5312r:0)  0@5296r
%vreg198 [5280r,5296r:0)  0@5280r
%vreg199 [5264r,5312r:0)  0@5264r
%vreg203 [448r,464r:0)  0@448r
%vreg204 [432r,448r:0)  0@432r
%vreg206 [416r,464r:0)  0@416r
%vreg207 [400r,416r:0)  0@400r
%vreg210 [576r,592r:0)  0@576r
%vreg212 [560r,576r:0)  0@560r
%vreg213 [544r,560r:0)  0@544r
%vreg217 [800r,816r:0)  0@800r
%vreg218 [784r,800r:0)  0@784r
%vreg219 [768r,816r:0)  0@768r
%vreg224 [736r,752r:0)  0@736r
%vreg226 [720r,736r:0)  0@720r
%vreg228 [704r,720r:0)  0@704r
%vreg229 [688r,704r:0)  0@688r
%vreg230 [656r,672r:0)  0@656r
%vreg233 [880r,896r:0)  0@880r
%vreg234 [864r,880r:0)  0@864r
%vreg238 [1712r,1728r:0)  0@1712r
%vreg239 [1696r,1712r:0)  0@1696r
%vreg240 [1680r,1728r:0)  0@1680r
%vreg243 [1792r,1808r:0)  0@1792r
%vreg244 [1776r,1792r:0)  0@1776r
%vreg248 [2240r,2256r:0)  0@2240r
%vreg249 [2224r,2240r:0)  0@2224r
%vreg250 [2208r,2256r:0)  0@2208r
%vreg253 [1872r,1888r:0)  0@1872r
%vreg254 [1856r,1872r:0)  0@1856r
%vreg256 [1936r,1968r:0)  0@1936r
%vreg257 [2080r,2160r:0)  0@2080r
%vreg259 [2144r,2160r:0)  0@2144r
%vreg262 [2112r,2128r:0)  0@2112r
%vreg263 [2096r,2128r:0)  0@2096r
%vreg266 [1616r,1632r:0)  0@1616r
%vreg267 [1600r,1632r:0)  0@1600r
%vreg271 [1568r,1584r:0)  0@1568r
%vreg272 [1552r,1568r:0)  0@1552r
%vreg273 [1536r,1584r:0)  0@1536r
%vreg278 [1504r,1520r:0)  0@1504r
%vreg280 [1488r,1504r:0)  0@1488r
%vreg281 [1472r,1488r:0)  0@1472r
%vreg286 [1456r,1504r:0)  0@1456r
%vreg287 [1440r,1456r:0)  0@1440r
%vreg288 [1424r,1520r:0)  0@1424r
%vreg289 [944r,1408r:0)  0@944r
%vreg293 [1392r,1408r:0)  0@1392r
%vreg295 [1376r,1392r:0)  0@1376r
%vreg296 [1360r,1376r:0)  0@1360r
%vreg302 [1328r,1392r:0)  0@1328r
%vreg303 [1312r,1328r:0)  0@1312r
%vreg306 [1280r,1296r:0)  0@1280r
%vreg309 [1264r,1296r:0)  0@1264r
%vreg311 [1248r,1264r:0)  0@1248r
%vreg312 [960r,976r:0)  0@960r
%vreg313 [976r,1232r:0)  0@976r
%vreg315 [1200r,1216r:0)  0@1200r
%vreg316 [1216r,1232r:0)  0@1216r
%vreg317 [1232r,1248r:0)  0@1232r
%vreg319 [1152r,1184r:0)  0@1152r
%vreg320 [1184r,1216r:0)  0@1184r
%vreg326 [1136r,1152r:0)  0@1136r
%vreg328 [1120r,1152r:0)  0@1120r
%vreg330 [1104r,1120r:0)  0@1104r
%vreg331 [1088r,1104r:0)  0@1088r
%vreg333 [1072r,1264r:0)  0@1072r
%vreg334 [1056r,1072r:0)  0@1056r
%vreg337 [1008r,1040r:0)  0@1008r
%vreg340 [992r,1008r:0)  0@992r
%vreg343 [2592r,2608r:0)  0@2592r
%vreg345 [2576r,2592r:0)  0@2576r
%vreg346 [2560r,2576r:0)  0@2560r
%vreg350 [2528r,2544r:0)  0@2528r
%vreg351 [2512r,2528r:0)  0@2512r
%vreg353 [2496r,2544r:0)  0@2496r
%vreg354 [2480r,2496r:0)  0@2480r
%vreg358 [2448r,2464r:0)  0@2448r
%vreg359 [2432r,2448r:0)  0@2432r
%vreg361 [2416r,2464r:0)  0@2416r
%vreg362 [2400r,2416r:0)  0@2400r
%vreg366 [2368r,2384r:0)  0@2368r
%vreg367 [2352r,2368r:0)  0@2352r
%vreg369 [2336r,2384r:0)  0@2336r
%vreg370 [2320r,2336r:0)  0@2320r
%vreg374 [2688r,2704r:0)  0@2688r
%vreg375 [2672r,2688r:0)  0@2672r
%vreg377 [2656r,2704r:0)  0@2656r
%vreg378 [2640r,2656r:0)  0@2640r
%vreg380 [5392r,5568r:0)  0@5392r
%vreg381 [5440r,5456r:0)  0@5440r
RegMasks: 176r 1984r 4512r 5488r
********** MACHINEINSTRS **********
# Machine code for function copy_input_until_stop: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
  fi#1: size=1, align=1, at location [SP]
  fi#2: size=4, align=4, at location [SP]
  fi#3: size=1, align=1, at location [SP]
  fi#4: size=4, align=4, at location [SP]
  fi#5: size=1, align=1, at location [SP]
Function Live Ins: %X0 in %vreg0, %LR in %vreg10

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %LR
16B		%vreg9<def> = COPY %LR; GPR64:%vreg9
32B		%vreg1<def> = COPY %X0; GPR64:%vreg1
64B		%vreg6<def> = ADRP <ga:@copy_input_until_stop>[TF=1]; GPR64common:%vreg6
80B		%vreg8<def> = ADDXri %vreg6, <ga:@copy_input_until_stop>[TF=34], 0; GPR64sp:%vreg8 GPR64common:%vreg6
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		%X0<def> = COPY %vreg8; GPR64sp:%vreg8
160B		%X1<def> = COPY %vreg9; GPR64:%vreg9
176B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
224B		STACKMAP 0, 0, 0, <fi#3>, 0, 0, <fi#5>, 0, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack3](align=1) LD8[FixedStack5](align=1) LD8[FixedStack1](align=1) LD8[FixedStack0] LD8[FixedStack2](align=4) LD8[FixedStack4](align=4) GPR64:%vreg1
240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
256B		STRXui %vreg1, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg1
272B		STRBBui %WZR, <fi#1>, 0; mem:ST1[FixedStack1]
288B		%vreg5<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg5
304B		%vreg4<def> = LDRWui %vreg5, 2; mem:LD4[%mode] GPR32common:%vreg4 GPR64common:%vreg5
320B		%WZR<def> = SUBSWri %vreg4, 2, 0, %NZCV<imp-def>; GPR32common:%vreg4
336B		Bcc 1, <BB#20>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#20 BB#1

352B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
368B		B <BB#2>
	    Successors according to CFG: BB#2

384B	BB#2: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#1 BB#18
400B		%vreg207<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg207
416B		%vreg206<def> = LDRWui %vreg207, 27; mem:LD4[%nblock] GPR32:%vreg206 GPR64common:%vreg207
432B		%vreg204<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg204
448B		%vreg203<def> = LDRWui %vreg204, 28; mem:LD4[%nblockMAX] GPR32:%vreg203 GPR64common:%vreg204
464B		%WZR<def> = SUBSWrr %vreg206, %vreg203, %NZCV<imp-def>; GPR32:%vreg206,%vreg203
480B		Bcc 11, <BB#4>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#4 BB#3

496B	BB#3: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#2
512B		B <BB#19>
	    Successors according to CFG: BB#19

528B	BB#4: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#2
544B		%vreg213<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg213
560B		%vreg212<def> = LDRXui %vreg213, 0; mem:LD8[%strm] GPR64common:%vreg212,%vreg213
576B		%vreg210<def> = LDRWui %vreg212, 2; mem:LD4[%avail_in] GPR32:%vreg210 GPR64common:%vreg212
592B		CBNZW %vreg210, <BB#6>; GPR32:%vreg210
	    Successors according to CFG: BB#6 BB#5

608B	BB#5: derived from LLVM BB %if.then.4
	    Predecessors according to CFG: BB#4
624B		B <BB#19>
	    Successors according to CFG: BB#19

640B	BB#6: derived from LLVM BB %if.end.5
	    Predecessors according to CFG: BB#4
656B		%vreg230<def> = MOVi32imm 1; GPR32:%vreg230
672B		STRBBui %vreg230, <fi#1>, 0; mem:ST1[FixedStack1] GPR32:%vreg230
688B		%vreg229<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg229
704B		%vreg228<def> = LDRXui %vreg229, 0; mem:LD8[%strm6] GPR64common:%vreg228,%vreg229
720B		%vreg226<def> = LDRXui %vreg228, 0; mem:LD8[%next_in] GPR64common:%vreg226,%vreg228
736B		%vreg224<def> = LDRBBui %vreg226, 0; mem:LD1[%11] GPR32:%vreg224 GPR64common:%vreg226
752B		STRWui %vreg224, <fi#2>, 0; mem:ST4[FixedStack2] GPR32:%vreg224
768B		%vreg219<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg219
784B		%vreg218<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg218
800B		%vreg217<def> = LDRWui %vreg218, 23; mem:LD4[%state_in_ch] GPR32:%vreg217 GPR64common:%vreg218
816B		%WZR<def> = SUBSWrr %vreg219, %vreg217, %NZCV<imp-def>; GPR32:%vreg219,%vreg217
832B		Bcc 0, <BB#9>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#9 BB#7

848B	BB#7: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#6
864B		%vreg234<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg234
880B		%vreg233<def> = LDRWui %vreg234, 24; mem:LD4[%state_in_len] GPR32common:%vreg233 GPR64common:%vreg234
896B		%WZR<def> = SUBSWri %vreg233, 1, 0, %NZCV<imp-def>; GPR32common:%vreg233
912B		Bcc 1, <BB#9>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#9 BB#8

928B	BB#8: derived from LLVM BB %if.then.11
	    Predecessors according to CFG: BB#7
944B		%vreg289<def> = MOVi32imm 1; GPR32:%vreg289
960B		%vreg312<def> = ADRP <ga:@BZ2_crc32Table>[TF=1]; GPR64common:%vreg312
976B		%vreg313<def> = ADDXri %vreg312, <ga:@BZ2_crc32Table>[TF=34], 0; GPR64common:%vreg313,%vreg312
992B		%vreg340<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg340
1008B		%vreg337<def> = LDRWui %vreg340, 23; mem:LD4[%state_in_ch12] GPR32:%vreg337 GPR64common:%vreg340
1040B		STRBBui %vreg337, <fi#3>, 0; mem:ST1[FixedStack3] GPR32:%vreg337
1056B		%vreg334<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg334
1072B		%vreg333<def> = LDRWui %vreg334, 162; mem:LD4[%blockCRC] GPR32:%vreg333 GPR64common:%vreg334
1088B		%vreg331<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg331
1104B		%vreg330<def> = LDRWui %vreg331, 162; mem:LD4[%blockCRC14] GPR32:%vreg330 GPR64common:%vreg331
1120B		%vreg328<def> = UBFMWri %vreg330, 24, 31; GPR32:%vreg328,%vreg330
1136B		%vreg326<def> = LDRBBui <fi#3>, 0; mem:LD1[FixedStack3] GPR32:%vreg326
1152B		%vreg319:sub_32<def,read-undef> = EORWrr %vreg328, %vreg326; GPR64:%vreg319 GPR32:%vreg328,%vreg326
1184B		%vreg320<def> = UBFMXri %vreg319, 0, 31; GPR64:%vreg320,%vreg319
1200B		%vreg315<def> = MOVi64imm 4; GPR64:%vreg315
1216B		%vreg316<def> = MADDXrrr %vreg320, %vreg315, %XZR; GPR64:%vreg316,%vreg320,%vreg315
1232B		%vreg317<def> = ADDXrr %vreg313, %vreg316; GPR64common:%vreg317,%vreg313 GPR64:%vreg316
1248B		%vreg311<def> = LDRWui %vreg317, 0; mem:LD4[%arrayidx] GPR32:%vreg311 GPR64common:%vreg317
1264B		%vreg309<def> = EORWrs %vreg311, %vreg333, 8; GPR32:%vreg309,%vreg311,%vreg333
1280B		%vreg306<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg306
1296B		STRWui %vreg309, %vreg306, 162; mem:ST4[%blockCRC17] GPR32:%vreg309 GPR64common:%vreg306
1312B		%vreg303<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg303
1328B		%vreg302:sub_32<def,read-undef> = LDRWui %vreg303, 23; mem:LD4[%state_in_ch18] GPR64:%vreg302 GPR64common:%vreg303
1360B		%vreg296<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg296
1376B		%vreg295<def> = ADDXri %vreg296, 128, 0; GPR64common:%vreg295,%vreg296
1392B		%vreg293<def> = ADDXrr %vreg295, %vreg302; GPR64common:%vreg293,%vreg295 GPR64:%vreg302
1408B		STRBBui %vreg289, %vreg293, 0; mem:ST1[%arrayidx20] GPR32:%vreg289 GPR64common:%vreg293
1424B		%vreg288<def> = LDRBBui <fi#3>, 0; mem:LD1[FixedStack3] GPR32:%vreg288
1440B		%vreg287<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg287
1456B		%vreg286<def> = LDRSWui %vreg287, 27; mem:LD4[%nblock21] GPR64:%vreg286 GPR64common:%vreg287
1472B		%vreg281<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg281
1488B		%vreg280<def> = LDRXui %vreg281, 8; mem:LD8[%block] GPR64:%vreg280 GPR64common:%vreg281
1504B		%vreg278<def> = ADDXrr %vreg280, %vreg286; GPR64common:%vreg278 GPR64:%vreg280,%vreg286
1520B		STRBBui %vreg288, %vreg278, 0; mem:ST1[%arrayidx23] GPR32:%vreg288 GPR64common:%vreg278
1536B		%vreg273<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg273
1552B		%vreg272<def> = LDRWui %vreg273, 27; mem:LD4[%nblock24] GPR32common:%vreg272 GPR64common:%vreg273
1568B		%vreg271<def> = ADDWri %vreg272, 1, 0; GPR32common:%vreg271,%vreg272
1584B		STRWui %vreg271, %vreg273, 27; mem:ST4[%nblock24] GPR32common:%vreg271 GPR64common:%vreg273
1600B		%vreg267<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg267
1616B		%vreg266<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg266
1632B		STRWui %vreg267, %vreg266, 23; mem:ST4[%state_in_ch25] GPR32:%vreg267 GPR64common:%vreg266
1648B		B <BB#16>
	    Successors according to CFG: BB#16

1664B	BB#9: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#6 BB#7
1680B		%vreg240<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg240
1696B		%vreg239<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg239
1712B		%vreg238<def> = LDRWui %vreg239, 23; mem:LD4[%state_in_ch26] GPR32:%vreg238 GPR64common:%vreg239
1728B		%WZR<def> = SUBSWrr %vreg240, %vreg238, %NZCV<imp-def>; GPR32:%vreg240,%vreg238
1744B		Bcc 1, <BB#11>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#11 BB#10

1760B	BB#10: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#9
1776B		%vreg244<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg244
1792B		%vreg243<def> = LDRWui %vreg244, 24; mem:LD4[%state_in_len29] GPR32common:%vreg243 GPR64common:%vreg244
1808B		%WZR<def> = SUBSWri %vreg243, 255, 0, %NZCV<imp-def>; GPR32common:%vreg243
1824B		Bcc 1, <BB#14>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#14 BB#11

1840B	BB#11: derived from LLVM BB %if.then.32
	    Predecessors according to CFG: BB#9 BB#10
1856B		%vreg254<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg254
1872B		%vreg253<def> = LDRWui %vreg254, 23; mem:LD4[%state_in_ch33] GPR32common:%vreg253 GPR64common:%vreg254
1888B		%WZR<def> = SUBSWri %vreg253, 256, 0, %NZCV<imp-def>; GPR32common:%vreg253
1904B		Bcc 2, <BB#13>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#13 BB#12

1920B	BB#12: derived from LLVM BB %if.then.36
	    Predecessors according to CFG: BB#11
1936B		%vreg256<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg256
1952B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1968B		%X0<def> = COPY %vreg256; GPR64:%vreg256
1984B		BL <ga:@add_pair_to_block>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>
2000B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2016B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2032B		STACKMAP 1, 0, 0, <fi#3>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack3](align=1) LD8[FixedStack1](align=1) LD8[FixedStack0] LD8[FixedStack2](align=4)
2048B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#13

2064B	BB#13: derived from LLVM BB %if.end.37
	    Predecessors according to CFG: BB#11 BB#12
2080B		%vreg257<def> = MOVi32imm 1; GPR32:%vreg257
2096B		%vreg263<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg263
2112B		%vreg262<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg262
2128B		STRWui %vreg263, %vreg262, 23; mem:ST4[%state_in_ch38] GPR32:%vreg263 GPR64common:%vreg262
2144B		%vreg259<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg259
2160B		STRWui %vreg257, %vreg259, 24; mem:ST4[%state_in_len39] GPR32:%vreg257 GPR64common:%vreg259
2176B		B <BB#15>
	    Successors according to CFG: BB#15

2192B	BB#14: derived from LLVM BB %if.else.40
	    Predecessors according to CFG: BB#10
2208B		%vreg250<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg250
2224B		%vreg249<def> = LDRWui %vreg250, 24; mem:LD4[%state_in_len41] GPR32common:%vreg249 GPR64common:%vreg250
2240B		%vreg248<def> = ADDWri %vreg249, 1, 0; GPR32common:%vreg248,%vreg249
2256B		STRWui %vreg248, %vreg250, 24; mem:ST4[%state_in_len41] GPR32common:%vreg248 GPR64common:%vreg250
	    Successors according to CFG: BB#15

2272B	BB#15: derived from LLVM BB %if.end.43
	    Predecessors according to CFG: BB#14 BB#13
2288B		B <BB#16>
	    Successors according to CFG: BB#16

2304B	BB#16: derived from LLVM BB %if.end.44
	    Predecessors according to CFG: BB#15 BB#8
2320B		%vreg370<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg370
2336B		%vreg369<def> = LDRXui %vreg370, 0; mem:LD8[%strm45] GPR64common:%vreg369,%vreg370
2352B		%vreg367<def> = LDRXui %vreg369, 0; mem:LD8[%next_in46] GPR64common:%vreg367,%vreg369
2368B		%vreg366<def> = ADDXri %vreg367, 1, 0; GPR64common:%vreg366,%vreg367
2384B		STRXui %vreg366, %vreg369, 0; mem:ST8[%next_in46] GPR64common:%vreg366,%vreg369
2400B		%vreg362<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg362
2416B		%vreg361<def> = LDRXui %vreg362, 0; mem:LD8[%strm47] GPR64common:%vreg361,%vreg362
2432B		%vreg359<def> = LDRWui %vreg361, 2; mem:LD4[%avail_in48] GPR32common:%vreg359 GPR64common:%vreg361
2448B		%vreg358<def> = SUBWri %vreg359, 1, 0; GPR32common:%vreg358,%vreg359
2464B		STRWui %vreg358, %vreg361, 2; mem:ST4[%avail_in48] GPR32common:%vreg358 GPR64common:%vreg361
2480B		%vreg354<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg354
2496B		%vreg353<def> = LDRXui %vreg354, 0; mem:LD8[%strm49] GPR64common:%vreg353,%vreg354
2512B		%vreg351<def> = LDRWui %vreg353, 3; mem:LD4[%total_in_lo32] GPR32common:%vreg351 GPR64common:%vreg353
2528B		%vreg350<def> = ADDWri %vreg351, 1, 0; GPR32common:%vreg350,%vreg351
2544B		STRWui %vreg350, %vreg353, 3; mem:ST4[%total_in_lo32] GPR32common:%vreg350 GPR64common:%vreg353
2560B		%vreg346<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg346
2576B		%vreg345<def> = LDRXui %vreg346, 0; mem:LD8[%strm51] GPR64common:%vreg345,%vreg346
2592B		%vreg343<def> = LDRWui %vreg345, 3; mem:LD4[%total_in_lo3252] GPR32:%vreg343 GPR64common:%vreg345
2608B		CBNZW %vreg343, <BB#18>; GPR32:%vreg343
	    Successors according to CFG: BB#18 BB#17

2624B	BB#17: derived from LLVM BB %if.then.55
	    Predecessors according to CFG: BB#16
2640B		%vreg378<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg378
2656B		%vreg377<def> = LDRXui %vreg378, 0; mem:LD8[%strm56] GPR64common:%vreg377,%vreg378
2672B		%vreg375<def> = LDRWui %vreg377, 4; mem:LD4[%total_in_hi32] GPR32common:%vreg375 GPR64common:%vreg377
2688B		%vreg374<def> = ADDWri %vreg375, 1, 0; GPR32common:%vreg374,%vreg375
2704B		STRWui %vreg374, %vreg377, 4; mem:ST4[%total_in_hi32] GPR32common:%vreg374 GPR64common:%vreg377
	    Successors according to CFG: BB#18

2720B	BB#18: derived from LLVM BB %if.end.58
	    Predecessors according to CFG: BB#16 BB#17
2736B		B <BB#2>
	    Successors according to CFG: BB#2

2752B	BB#19: derived from LLVM BB %while.end
	    Predecessors according to CFG: BB#5 BB#3
2768B		B <BB#41>
	    Successors according to CFG: BB#41

2784B	BB#20: derived from LLVM BB %if.else.59
	    Predecessors according to CFG: BB#0
2800B		B <BB#21>
	    Successors according to CFG: BB#21

2816B	BB#21: derived from LLVM BB %while.body.60
	    Predecessors according to CFG: BB#20 BB#39
2832B		%vreg18<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg18
2848B		%vreg17<def> = LDRWui %vreg18, 27; mem:LD4[%nblock61] GPR32:%vreg17 GPR64common:%vreg18
2864B		%vreg15<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg15
2880B		%vreg14<def> = LDRWui %vreg15, 28; mem:LD4[%nblockMAX62] GPR32:%vreg14 GPR64common:%vreg15
2896B		%WZR<def> = SUBSWrr %vreg17, %vreg14, %NZCV<imp-def>; GPR32:%vreg17,%vreg14
2912B		Bcc 11, <BB#23>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#23 BB#22

2928B	BB#22: derived from LLVM BB %if.then.65
	    Predecessors according to CFG: BB#21
2944B		B <BB#40>
	    Successors according to CFG: BB#40

2960B	BB#23: derived from LLVM BB %if.end.66
	    Predecessors according to CFG: BB#21
2976B		%vreg24<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg24
2992B		%vreg23<def> = LDRXui %vreg24, 0; mem:LD8[%strm67] GPR64common:%vreg23,%vreg24
3008B		%vreg21<def> = LDRWui %vreg23, 2; mem:LD4[%avail_in68] GPR32:%vreg21 GPR64common:%vreg23
3024B		CBNZW %vreg21, <BB#25>; GPR32:%vreg21
	    Successors according to CFG: BB#25 BB#24

3040B	BB#24: derived from LLVM BB %if.then.71
	    Predecessors according to CFG: BB#23
3056B		B <BB#40>
	    Successors according to CFG: BB#40

3072B	BB#25: derived from LLVM BB %if.end.72
	    Predecessors according to CFG: BB#23
3088B		%vreg28<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg28
3104B		%vreg27<def> = LDRWui %vreg28, 4; mem:LD4[%avail_in_expect] GPR32:%vreg27 GPR64common:%vreg28
3120B		CBNZW %vreg27, <BB#27>; GPR32:%vreg27
	    Successors according to CFG: BB#27 BB#26

3136B	BB#26: derived from LLVM BB %if.then.75
	    Predecessors according to CFG: BB#25
3152B		B <BB#40>
	    Successors according to CFG: BB#40

3168B	BB#27: derived from LLVM BB %if.end.76
	    Predecessors according to CFG: BB#25
3184B		%vreg45<def> = MOVi32imm 1; GPR32:%vreg45
3200B		STRBBui %vreg45, <fi#1>, 0; mem:ST1[FixedStack1] GPR32:%vreg45
3216B		%vreg44<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg44
3232B		%vreg43<def> = LDRXui %vreg44, 0; mem:LD8[%strm78] GPR64common:%vreg43,%vreg44
3248B		%vreg41<def> = LDRXui %vreg43, 0; mem:LD8[%next_in79] GPR64common:%vreg41,%vreg43
3264B		%vreg39<def> = LDRBBui %vreg41, 0; mem:LD1[%78] GPR32:%vreg39 GPR64common:%vreg41
3280B		STRWui %vreg39, <fi#4>, 0; mem:ST4[FixedStack4] GPR32:%vreg39
3296B		%vreg34<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg34
3312B		%vreg33<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg33
3328B		%vreg32<def> = LDRWui %vreg33, 23; mem:LD4[%state_in_ch81] GPR32:%vreg32 GPR64common:%vreg33
3344B		%WZR<def> = SUBSWrr %vreg34, %vreg32, %NZCV<imp-def>; GPR32:%vreg34,%vreg32
3360B		Bcc 0, <BB#30>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#30 BB#28

3376B	BB#28: derived from LLVM BB %land.lhs.true.84
	    Predecessors according to CFG: BB#27
3392B		%vreg49<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg49
3408B		%vreg48<def> = LDRWui %vreg49, 24; mem:LD4[%state_in_len85] GPR32common:%vreg48 GPR64common:%vreg49
3424B		%WZR<def> = SUBSWri %vreg48, 1, 0, %NZCV<imp-def>; GPR32common:%vreg48
3440B		Bcc 1, <BB#30>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#30 BB#29

3456B	BB#29: derived from LLVM BB %if.then.88
	    Predecessors according to CFG: BB#28
3472B		%vreg104<def> = MOVi32imm 1; GPR32:%vreg104
3488B		%vreg127<def> = ADRP <ga:@BZ2_crc32Table>[TF=1]; GPR64common:%vreg127
3504B		%vreg128<def> = ADDXri %vreg127, <ga:@BZ2_crc32Table>[TF=34], 0; GPR64common:%vreg128,%vreg127
3520B		%vreg155<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg155
3536B		%vreg152<def> = LDRWui %vreg155, 23; mem:LD4[%state_in_ch90] GPR32:%vreg152 GPR64common:%vreg155
3568B		STRBBui %vreg152, <fi#5>, 0; mem:ST1[FixedStack5] GPR32:%vreg152
3584B		%vreg149<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg149
3600B		%vreg148<def> = LDRWui %vreg149, 162; mem:LD4[%blockCRC92] GPR32:%vreg148 GPR64common:%vreg149
3616B		%vreg146<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg146
3632B		%vreg145<def> = LDRWui %vreg146, 162; mem:LD4[%blockCRC94] GPR32:%vreg145 GPR64common:%vreg146
3648B		%vreg143<def> = UBFMWri %vreg145, 24, 31; GPR32:%vreg143,%vreg145
3664B		%vreg141<def> = LDRBBui <fi#5>, 0; mem:LD1[FixedStack5] GPR32:%vreg141
3680B		%vreg134:sub_32<def,read-undef> = EORWrr %vreg143, %vreg141; GPR64:%vreg134 GPR32:%vreg143,%vreg141
3712B		%vreg135<def> = UBFMXri %vreg134, 0, 31; GPR64:%vreg135,%vreg134
3728B		%vreg130<def> = MOVi64imm 4; GPR64:%vreg130
3744B		%vreg131<def> = MADDXrrr %vreg135, %vreg130, %XZR; GPR64:%vreg131,%vreg135,%vreg130
3760B		%vreg132<def> = ADDXrr %vreg128, %vreg131; GPR64common:%vreg132,%vreg128 GPR64:%vreg131
3776B		%vreg126<def> = LDRWui %vreg132, 0; mem:LD4[%arrayidx99] GPR32:%vreg126 GPR64common:%vreg132
3792B		%vreg124<def> = EORWrs %vreg126, %vreg148, 8; GPR32:%vreg124,%vreg126,%vreg148
3808B		%vreg121<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg121
3824B		STRWui %vreg124, %vreg121, 162; mem:ST4[%blockCRC101] GPR32:%vreg124 GPR64common:%vreg121
3840B		%vreg118<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg118
3856B		%vreg117:sub_32<def,read-undef> = LDRWui %vreg118, 23; mem:LD4[%state_in_ch102] GPR64:%vreg117 GPR64common:%vreg118
3888B		%vreg111<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg111
3904B		%vreg110<def> = ADDXri %vreg111, 128, 0; GPR64common:%vreg110,%vreg111
3920B		%vreg108<def> = ADDXrr %vreg110, %vreg117; GPR64common:%vreg108,%vreg110 GPR64:%vreg117
3936B		STRBBui %vreg104, %vreg108, 0; mem:ST1[%arrayidx105] GPR32:%vreg104 GPR64common:%vreg108
3952B		%vreg103<def> = LDRBBui <fi#5>, 0; mem:LD1[FixedStack5] GPR32:%vreg103
3968B		%vreg102<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg102
3984B		%vreg101<def> = LDRSWui %vreg102, 27; mem:LD4[%nblock106] GPR64:%vreg101 GPR64common:%vreg102
4000B		%vreg96<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg96
4016B		%vreg95<def> = LDRXui %vreg96, 8; mem:LD8[%block108] GPR64:%vreg95 GPR64common:%vreg96
4032B		%vreg93<def> = ADDXrr %vreg95, %vreg101; GPR64common:%vreg93 GPR64:%vreg95,%vreg101
4048B		STRBBui %vreg103, %vreg93, 0; mem:ST1[%arrayidx109] GPR32:%vreg103 GPR64common:%vreg93
4064B		%vreg88<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg88
4080B		%vreg87<def> = LDRWui %vreg88, 27; mem:LD4[%nblock110] GPR32common:%vreg87 GPR64common:%vreg88
4096B		%vreg86<def> = ADDWri %vreg87, 1, 0; GPR32common:%vreg86,%vreg87
4112B		STRWui %vreg86, %vreg88, 27; mem:ST4[%nblock110] GPR32common:%vreg86 GPR64common:%vreg88
4128B		%vreg82<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg82
4144B		%vreg81<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg81
4160B		STRWui %vreg82, %vreg81, 23; mem:ST4[%state_in_ch112] GPR32:%vreg82 GPR64common:%vreg81
4176B		B <BB#37>
	    Successors according to CFG: BB#37

4192B	BB#30: derived from LLVM BB %if.else.113
	    Predecessors according to CFG: BB#27 BB#28
4208B		%vreg55<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg55
4224B		%vreg54<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg54
4240B		%vreg53<def> = LDRWui %vreg54, 23; mem:LD4[%state_in_ch114] GPR32:%vreg53 GPR64common:%vreg54
4256B		%WZR<def> = SUBSWrr %vreg55, %vreg53, %NZCV<imp-def>; GPR32:%vreg55,%vreg53
4272B		Bcc 1, <BB#32>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#32 BB#31

4288B	BB#31: derived from LLVM BB %lor.lhs.false.117
	    Predecessors according to CFG: BB#30
4304B		%vreg59<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg59
4320B		%vreg58<def> = LDRWui %vreg59, 24; mem:LD4[%state_in_len118] GPR32common:%vreg58 GPR64common:%vreg59
4336B		%WZR<def> = SUBSWri %vreg58, 255, 0, %NZCV<imp-def>; GPR32common:%vreg58
4352B		Bcc 1, <BB#35>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#35 BB#32

4368B	BB#32: derived from LLVM BB %if.then.121
	    Predecessors according to CFG: BB#30 BB#31
4384B		%vreg69<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg69
4400B		%vreg68<def> = LDRWui %vreg69, 23; mem:LD4[%state_in_ch122] GPR32common:%vreg68 GPR64common:%vreg69
4416B		%WZR<def> = SUBSWri %vreg68, 256, 0, %NZCV<imp-def>; GPR32common:%vreg68
4432B		Bcc 2, <BB#34>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#34 BB#33

4448B	BB#33: derived from LLVM BB %if.then.125
	    Predecessors according to CFG: BB#32
4464B		%vreg71<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg71
4480B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4496B		%X0<def> = COPY %vreg71; GPR64:%vreg71
4512B		BL <ga:@add_pair_to_block>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>
4528B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4544B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4560B		STACKMAP 2, 0, 0, <fi#5>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack5](align=1) LD8[FixedStack1](align=1) LD8[FixedStack0] LD8[FixedStack4](align=4)
4576B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#34

4592B	BB#34: derived from LLVM BB %if.end.126
	    Predecessors according to CFG: BB#32 BB#33
4608B		%vreg72<def> = MOVi32imm 1; GPR32:%vreg72
4624B		%vreg78<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg78
4640B		%vreg77<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg77
4656B		STRWui %vreg78, %vreg77, 23; mem:ST4[%state_in_ch127] GPR32:%vreg78 GPR64common:%vreg77
4672B		%vreg74<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg74
4688B		STRWui %vreg72, %vreg74, 24; mem:ST4[%state_in_len128] GPR32:%vreg72 GPR64common:%vreg74
4704B		B <BB#36>
	    Successors according to CFG: BB#36

4720B	BB#35: derived from LLVM BB %if.else.129
	    Predecessors according to CFG: BB#31
4736B		%vreg65<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg65
4752B		%vreg64<def> = LDRWui %vreg65, 24; mem:LD4[%state_in_len130] GPR32common:%vreg64 GPR64common:%vreg65
4768B		%vreg63<def> = ADDWri %vreg64, 1, 0; GPR32common:%vreg63,%vreg64
4784B		STRWui %vreg63, %vreg65, 24; mem:ST4[%state_in_len130] GPR32common:%vreg63 GPR64common:%vreg65
	    Successors according to CFG: BB#36

4800B	BB#36: derived from LLVM BB %if.end.132
	    Predecessors according to CFG: BB#35 BB#34
4816B		B <BB#37>
	    Successors according to CFG: BB#37

4832B	BB#37: derived from LLVM BB %if.end.133
	    Predecessors according to CFG: BB#36 BB#29
4848B		%vreg185<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg185
4864B		%vreg184<def> = LDRXui %vreg185, 0; mem:LD8[%strm134] GPR64common:%vreg184,%vreg185
4880B		%vreg182<def> = LDRXui %vreg184, 0; mem:LD8[%next_in135] GPR64common:%vreg182,%vreg184
4896B		%vreg181<def> = ADDXri %vreg182, 1, 0; GPR64common:%vreg181,%vreg182
4912B		STRXui %vreg181, %vreg184, 0; mem:ST8[%next_in135] GPR64common:%vreg181,%vreg184
4928B		%vreg177<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg177
4944B		%vreg176<def> = LDRXui %vreg177, 0; mem:LD8[%strm137] GPR64common:%vreg176,%vreg177
4960B		%vreg174<def> = LDRWui %vreg176, 2; mem:LD4[%avail_in138] GPR32common:%vreg174 GPR64common:%vreg176
4976B		%vreg173<def> = SUBWri %vreg174, 1, 0; GPR32common:%vreg173,%vreg174
4992B		STRWui %vreg173, %vreg176, 2; mem:ST4[%avail_in138] GPR32common:%vreg173 GPR64common:%vreg176
5008B		%vreg169<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg169
5024B		%vreg168<def> = LDRXui %vreg169, 0; mem:LD8[%strm140] GPR64common:%vreg168,%vreg169
5040B		%vreg166<def> = LDRWui %vreg168, 3; mem:LD4[%total_in_lo32141] GPR32common:%vreg166 GPR64common:%vreg168
5056B		%vreg165<def> = ADDWri %vreg166, 1, 0; GPR32common:%vreg165,%vreg166
5072B		STRWui %vreg165, %vreg168, 3; mem:ST4[%total_in_lo32141] GPR32common:%vreg165 GPR64common:%vreg168
5088B		%vreg161<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg161
5104B		%vreg160<def> = LDRXui %vreg161, 0; mem:LD8[%strm143] GPR64common:%vreg160,%vreg161
5120B		%vreg158<def> = LDRWui %vreg160, 3; mem:LD4[%total_in_lo32144] GPR32:%vreg158 GPR64common:%vreg160
5136B		CBNZW %vreg158, <BB#39>; GPR32:%vreg158
	    Successors according to CFG: BB#39 BB#38

5152B	BB#38: derived from LLVM BB %if.then.147
	    Predecessors according to CFG: BB#37
5168B		%vreg193<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg193
5184B		%vreg192<def> = LDRXui %vreg193, 0; mem:LD8[%strm148] GPR64common:%vreg192,%vreg193
5200B		%vreg190<def> = LDRWui %vreg192, 4; mem:LD4[%total_in_hi32149] GPR32common:%vreg190 GPR64common:%vreg192
5216B		%vreg189<def> = ADDWri %vreg190, 1, 0; GPR32common:%vreg189,%vreg190
5232B		STRWui %vreg189, %vreg192, 4; mem:ST4[%total_in_hi32149] GPR32common:%vreg189 GPR64common:%vreg192
	    Successors according to CFG: BB#39

5248B	BB#39: derived from LLVM BB %if.end.151
	    Predecessors according to CFG: BB#37 BB#38
5264B		%vreg199<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg199
5280B		%vreg198<def> = LDRWui %vreg199, 4; mem:LD4[%avail_in_expect152] GPR32common:%vreg198 GPR64common:%vreg199
5296B		%vreg197<def> = SUBWri %vreg198, 1, 0; GPR32common:%vreg197,%vreg198
5312B		STRWui %vreg197, %vreg199, 4; mem:ST4[%avail_in_expect152] GPR32common:%vreg197 GPR64common:%vreg199
5328B		B <BB#21>
	    Successors according to CFG: BB#21

5344B	BB#40: derived from LLVM BB %while.end.154
	    Predecessors according to CFG: BB#26 BB#24 BB#22
5360B		B <BB#41>
	    Successors according to CFG: BB#41

5376B	BB#41: derived from LLVM BB %if.end.155
	    Predecessors according to CFG: BB#40 BB#19
5392B		%vreg380<def> = LDRBBui <fi#1>, 0; mem:LD1[%progress_in] GPR32:%vreg380
5424B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5440B		%vreg381<def> = MOVaddr <ga:@copy_input_until_stop>[TF=1], <ga:@copy_input_until_stop>[TF=34]; GPR64:%vreg381
5456B		%X0<def> = COPY %vreg381; GPR64:%vreg381
5472B		%X1<def> = COPY %vreg9; GPR64:%vreg9
5488B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %SP<imp-def>
5504B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5520B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5536B		STACKMAP 3, 0, %vreg380, %LR<earlyclobber,imp-def,dead>, ...; GPR32:%vreg380
5552B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5568B		%W0<def> = COPY %vreg380; GPR32:%vreg380
5584B		RET_ReallyLR %W0<imp-use>

# End machine code for function copy_input_until_stop.

handleMove 416B -> 440B: %vreg206<def> = LDRWui %vreg207, 27; mem:LD4[%nblock] GPR32:%vreg206 GPR64common:%vreg207
     %vreg206:	[416r,464r:0)  0@416r
        -->	[440r,464r:0)  0@440r
     %vreg207:	[400r,416r:0)  0@400r
        -->	[400r,440r:0)  0@400r
handleMove 768B -> 792B: %vreg219<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg219
     %vreg219:	[768r,816r:0)  0@768r
        -->	[792r,816r:0)  0@792r
AllocationOrder(GPR32sponly) = [ ]
handleMove 1424B -> 1496B: %vreg288<def> = LDRBBui <fi#3>, 0; mem:LD1[FixedStack3] GPR32:%vreg288
     %vreg288:	[1424r,1520r:0)  0@1424r
        -->	[1496r,1520r:0)  0@1496r
handleMove 1456B -> 1480B: %vreg286<def> = LDRSWui %vreg287, 27; mem:LD4[%nblock21] GPR64:%vreg286 GPR64common:%vreg287
     %vreg286:	[1456r,1504r:0)  0@1456r
        -->	[1480r,1504r:0)  0@1480r
     %vreg287:	[1440r,1456r:0)  0@1440r
        -->	[1440r,1480r:0)  0@1440r
handleMove 944B -> 1368B: %vreg289<def> = MOVi32imm 1; GPR32:%vreg289
     %vreg289:	[944r,1408r:0)  0@944r
        -->	[1368r,1408r:0)  0@1368r
handleMove 1328B -> 1364B: %vreg302:sub_32<def,read-undef> = LDRWui %vreg303, 23; mem:LD4[%state_in_ch18] GPR64:%vreg302 GPR64common:%vreg303
     %vreg302:	[1328r,1392r:0)  0@1328r
        -->	[1364r,1392r:0)  0@1364r
     %vreg303:	[1312r,1328r:0)  0@1312r
        -->	[1312r,1364r:0)  0@1312r
handleMove 1264B -> 1288B: %vreg309<def> = EORWrs %vreg311, %vreg333, 8; GPR32:%vreg309,%vreg311,%vreg333
     %vreg309:	[1264r,1296r:0)  0@1264r
        -->	[1288r,1296r:0)  0@1288r
     %vreg311:	[1248r,1264r:0)  0@1248r
        -->	[1248r,1288r:0)  0@1248r
     %vreg333:	[1072r,1264r:0)  0@1072r
        -->	[1072r,1288r:0)  0@1072r
handleMove 1184B -> 1208B: %vreg320<def> = UBFMXri %vreg319, 0, 31; GPR64:%vreg320,%vreg319
     %vreg320:	[1184r,1216r:0)  0@1184r
        -->	[1208r,1216r:0)  0@1208r
     %vreg319:	[1152r,1184r:0)  0@1152r
        -->	[1152r,1208r:0)  0@1152r
handleMove 1152B -> 1204B: %vreg319:sub_32<def,read-undef> = EORWrr %vreg328, %vreg326; GPR64:%vreg319 GPR32:%vreg328,%vreg326
     %vreg319:	[1152r,1208r:0)  0@1152r
        -->	[1204r,1208r:0)  0@1204r
     %vreg328:	[1120r,1152r:0)  0@1120r
        -->	[1120r,1204r:0)  0@1120r
     %vreg326:	[1136r,1152r:0)  0@1136r
        -->	[1136r,1204r:0)  0@1136r
handleMove 1120B -> 1208B: %vreg328<def> = UBFMWri %vreg330, 24, 31; GPR32:%vreg328,%vreg330
     %vreg328:	[1120r,1216r:0)  0@1120r
        -->	[1208r,1216r:0)  0@1208r
     %vreg330:	[1104r,1120r:0)  0@1104r
        -->	[1104r,1208r:0)  0@1104r
handleMove 1072B -> 1204B: %vreg333<def> = LDRWui %vreg334, 162; mem:LD4[%blockCRC] GPR32:%vreg333 GPR64common:%vreg334
     %vreg333:	[1072r,1288r:0)  0@1072r
        -->	[1204r,1288r:0)  0@1204r
     %vreg334:	[1056r,1072r:0)  0@1056r
        -->	[1056r,1204r:0)  0@1056r
handleMove 976B -> 1208B: %vreg313<def> = ADDXri %vreg312, <ga:@BZ2_crc32Table>[TF=34], 0; GPR64common:%vreg313,%vreg312
     %vreg313:	[976r,1256r:0)  0@976r
        -->	[1208r,1256r:0)  0@1208r
     %vreg312:	[960r,976r:0)  0@960r
        -->	[960r,1208r:0)  0@960r
handleMove 1136B -> 1204B: %vreg326<def> = LDRBBui <fi#3>, 0; mem:LD1[FixedStack3] GPR32:%vreg326
     %vreg326:	[1136r,1232r:0)  0@1136r
        -->	[1204r,1232r:0)  0@1204r
handleMove 1104B -> 1208B: %vreg330<def> = LDRWui %vreg331, 162; mem:LD4[%blockCRC14] GPR32:%vreg330 GPR64common:%vreg331
     %vreg330:	[1104r,1240r:0)  0@1104r
        -->	[1208r,1240r:0)  0@1208r
     %vreg331:	[1088r,1104r:0)  0@1088r
        -->	[1088r,1208r:0)  0@1088r
handleMove 1056B -> 1204B: %vreg334<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg334
     %vreg334:	[1056r,1232r:0)  0@1056r
        -->	[1204r,1232r:0)  0@1204r
handleMove 960B -> 1096B: %vreg312<def> = ADRP <ga:@BZ2_crc32Table>[TF=1]; GPR64common:%vreg312
     %vreg312:	[960r,1224r:0)  0@960r
        -->	[1096r,1224r:0)  0@1096r
handleMove 1680B -> 1704B: %vreg240<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg240
     %vreg240:	[1680r,1728r:0)  0@1680r
        -->	[1704r,1728r:0)  0@1704r
handleMove 2080B -> 2152B: %vreg257<def> = MOVi32imm 1; GPR32:%vreg257
     %vreg257:	[2080r,2160r:0)  0@2080r
        -->	[2152r,2160r:0)  0@2152r
AllocationOrder(GPR32sponly) = [ ]
handleMove 2848B -> 2872B: %vreg17<def> = LDRWui %vreg18, 27; mem:LD4[%nblock61] GPR32:%vreg17 GPR64common:%vreg18
     %vreg17:	[2848r,2896r:0)  0@2848r
        -->	[2872r,2896r:0)  0@2872r
     %vreg18:	[2832r,2848r:0)  0@2832r
        -->	[2832r,2872r:0)  0@2832r
handleMove 3296B -> 3320B: %vreg34<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg34
     %vreg34:	[3296r,3344r:0)  0@3296r
        -->	[3320r,3344r:0)  0@3320r
AllocationOrder(GPR32sponly) = [ ]
handleMove 3952B -> 4024B: %vreg103<def> = LDRBBui <fi#5>, 0; mem:LD1[FixedStack5] GPR32:%vreg103
     %vreg103:	[3952r,4048r:0)  0@3952r
        -->	[4024r,4048r:0)  0@4024r
handleMove 3984B -> 4008B: %vreg101<def> = LDRSWui %vreg102, 27; mem:LD4[%nblock106] GPR64:%vreg101 GPR64common:%vreg102
     %vreg101:	[3984r,4032r:0)  0@3984r
        -->	[4008r,4032r:0)  0@4008r
     %vreg102:	[3968r,3984r:0)  0@3968r
        -->	[3968r,4008r:0)  0@3968r
handleMove 3472B -> 3896B: %vreg104<def> = MOVi32imm 1; GPR32:%vreg104
     %vreg104:	[3472r,3936r:0)  0@3472r
        -->	[3896r,3936r:0)  0@3896r
handleMove 3856B -> 3892B: %vreg117:sub_32<def,read-undef> = LDRWui %vreg118, 23; mem:LD4[%state_in_ch102] GPR64:%vreg117 GPR64common:%vreg118
     %vreg117:	[3856r,3920r:0)  0@3856r
        -->	[3892r,3920r:0)  0@3892r
     %vreg118:	[3840r,3856r:0)  0@3840r
        -->	[3840r,3892r:0)  0@3840r
handleMove 3792B -> 3816B: %vreg124<def> = EORWrs %vreg126, %vreg148, 8; GPR32:%vreg124,%vreg126,%vreg148
     %vreg124:	[3792r,3824r:0)  0@3792r
        -->	[3816r,3824r:0)  0@3816r
     %vreg126:	[3776r,3792r:0)  0@3776r
        -->	[3776r,3816r:0)  0@3776r
     %vreg148:	[3600r,3792r:0)  0@3600r
        -->	[3600r,3816r:0)  0@3600r
handleMove 3712B -> 3736B: %vreg135<def> = UBFMXri %vreg134, 0, 31; GPR64:%vreg135,%vreg134
     %vreg135:	[3712r,3744r:0)  0@3712r
        -->	[3736r,3744r:0)  0@3736r
     %vreg134:	[3680r,3712r:0)  0@3680r
        -->	[3680r,3736r:0)  0@3680r
handleMove 3680B -> 3732B: %vreg134:sub_32<def,read-undef> = EORWrr %vreg143, %vreg141; GPR64:%vreg134 GPR32:%vreg143,%vreg141
     %vreg134:	[3680r,3736r:0)  0@3680r
        -->	[3732r,3736r:0)  0@3732r
     %vreg143:	[3648r,3680r:0)  0@3648r
        -->	[3648r,3732r:0)  0@3648r
     %vreg141:	[3664r,3680r:0)  0@3664r
        -->	[3664r,3732r:0)  0@3664r
handleMove 3648B -> 3736B: %vreg143<def> = UBFMWri %vreg145, 24, 31; GPR32:%vreg143,%vreg145
     %vreg143:	[3648r,3744r:0)  0@3648r
        -->	[3736r,3744r:0)  0@3736r
     %vreg145:	[3632r,3648r:0)  0@3632r
        -->	[3632r,3736r:0)  0@3632r
handleMove 3600B -> 3732B: %vreg148<def> = LDRWui %vreg149, 162; mem:LD4[%blockCRC92] GPR32:%vreg148 GPR64common:%vreg149
     %vreg148:	[3600r,3816r:0)  0@3600r
        -->	[3732r,3816r:0)  0@3732r
     %vreg149:	[3584r,3600r:0)  0@3584r
        -->	[3584r,3732r:0)  0@3584r
handleMove 3504B -> 3736B: %vreg128<def> = ADDXri %vreg127, <ga:@BZ2_crc32Table>[TF=34], 0; GPR64common:%vreg128,%vreg127
     %vreg128:	[3504r,3784r:0)  0@3504r
        -->	[3736r,3784r:0)  0@3736r
     %vreg127:	[3488r,3504r:0)  0@3488r
        -->	[3488r,3736r:0)  0@3488r
handleMove 3664B -> 3732B: %vreg141<def> = LDRBBui <fi#5>, 0; mem:LD1[FixedStack5] GPR32:%vreg141
     %vreg141:	[3664r,3760r:0)  0@3664r
        -->	[3732r,3760r:0)  0@3732r
handleMove 3632B -> 3736B: %vreg145<def> = LDRWui %vreg146, 162; mem:LD4[%blockCRC94] GPR32:%vreg145 GPR64common:%vreg146
     %vreg145:	[3632r,3768r:0)  0@3632r
        -->	[3736r,3768r:0)  0@3736r
     %vreg146:	[3616r,3632r:0)  0@3616r
        -->	[3616r,3736r:0)  0@3616r
handleMove 3584B -> 3732B: %vreg149<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg149
     %vreg149:	[3584r,3760r:0)  0@3584r
        -->	[3732r,3760r:0)  0@3732r
handleMove 3488B -> 3624B: %vreg127<def> = ADRP <ga:@BZ2_crc32Table>[TF=1]; GPR64common:%vreg127
     %vreg127:	[3488r,3752r:0)  0@3488r
        -->	[3624r,3752r:0)  0@3624r
handleMove 4208B -> 4232B: %vreg55<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg55
     %vreg55:	[4208r,4256r:0)  0@4208r
        -->	[4232r,4256r:0)  0@4232r
handleMove 4608B -> 4680B: %vreg72<def> = MOVi32imm 1; GPR32:%vreg72
     %vreg72:	[4608r,4688r:0)  0@4608r
        -->	[4680r,4688r:0)  0@4680r
AllocationOrder(GPR32sponly) = [ ]
********** GREEDY REGISTER ALLOCATION **********
********** Function: copy_input_until_stop
********** INTERVALS **********
W30 [0B,16r:0)[176r,176d:8)[224e,224d:3)[1984r,1984d:6)[2032e,2032d:2)[4512r,4512d:7)[4560e,4560d:1)[5488r,5488d:5)[5536e,5536d:4)  0@0B-phi 1@4560e 2@2032e 3@224e 4@5536e 5@5488r 6@1984r 7@4512r 8@176r
W0 [0B,32r:0)[144r,176r:5)[1968r,1984r:3)[4496r,4512r:4)[5456r,5488r:2)[5568r,5584r:1)  0@0B-phi 1@5568r 2@5456r 3@1968r 4@4496r 5@144r
%vreg1 [32r,256r:0)  0@32r
%vreg4 [304r,320r:0)  0@304r
%vreg5 [288r,304r:0)  0@288r
%vreg6 [64r,80r:0)  0@64r
%vreg8 [80r,144r:0)  0@80r
%vreg9 [16r,5472r:0)  0@16r
%vreg14 [2880r,2896r:0)  0@2880r
%vreg15 [2864r,2880r:0)  0@2864r
%vreg17 [2872r,2896r:0)  0@2872r
%vreg18 [2832r,2872r:0)  0@2832r
%vreg21 [3008r,3024r:0)  0@3008r
%vreg23 [2992r,3008r:0)  0@2992r
%vreg24 [2976r,2992r:0)  0@2976r
%vreg27 [3104r,3120r:0)  0@3104r
%vreg28 [3088r,3104r:0)  0@3088r
%vreg32 [3328r,3344r:0)  0@3328r
%vreg33 [3312r,3328r:0)  0@3312r
%vreg34 [3320r,3344r:0)  0@3320r
%vreg39 [3264r,3280r:0)  0@3264r
%vreg41 [3248r,3264r:0)  0@3248r
%vreg43 [3232r,3248r:0)  0@3232r
%vreg44 [3216r,3232r:0)  0@3216r
%vreg45 [3184r,3200r:0)  0@3184r
%vreg48 [3408r,3424r:0)  0@3408r
%vreg49 [3392r,3408r:0)  0@3392r
%vreg53 [4240r,4256r:0)  0@4240r
%vreg54 [4224r,4240r:0)  0@4224r
%vreg55 [4232r,4256r:0)  0@4232r
%vreg58 [4320r,4336r:0)  0@4320r
%vreg59 [4304r,4320r:0)  0@4304r
%vreg63 [4768r,4784r:0)  0@4768r
%vreg64 [4752r,4768r:0)  0@4752r
%vreg65 [4736r,4784r:0)  0@4736r
%vreg68 [4400r,4416r:0)  0@4400r
%vreg69 [4384r,4400r:0)  0@4384r
%vreg71 [4464r,4496r:0)  0@4464r
%vreg72 [4680r,4688r:0)  0@4680r
%vreg74 [4672r,4688r:0)  0@4672r
%vreg77 [4640r,4656r:0)  0@4640r
%vreg78 [4624r,4656r:0)  0@4624r
%vreg81 [4144r,4160r:0)  0@4144r
%vreg82 [4128r,4160r:0)  0@4128r
%vreg86 [4096r,4112r:0)  0@4096r
%vreg87 [4080r,4096r:0)  0@4080r
%vreg88 [4064r,4112r:0)  0@4064r
%vreg93 [4032r,4048r:0)  0@4032r
%vreg95 [4016r,4032r:0)  0@4016r
%vreg96 [4000r,4016r:0)  0@4000r
%vreg101 [4008r,4032r:0)  0@4008r
%vreg102 [3968r,4008r:0)  0@3968r
%vreg103 [4024r,4048r:0)  0@4024r
%vreg104 [3896r,3936r:0)  0@3896r
%vreg108 [3920r,3936r:0)  0@3920r
%vreg110 [3904r,3920r:0)  0@3904r
%vreg111 [3888r,3904r:0)  0@3888r
%vreg117 [3892r,3920r:0)  0@3892r
%vreg118 [3848r,3892r:0)  0@3848r
%vreg121 [3824r,3840r:0)  0@3824r
%vreg124 [3832r,3840r:0)  0@3832r
%vreg126 [3808r,3832r:0)  0@3808r
%vreg127 [3624r,3752r:0)  0@3624r
%vreg128 [3752r,3800r:0)  0@3752r
%vreg130 [3728r,3792r:0)  0@3728r
%vreg131 [3792r,3800r:0)  0@3792r
%vreg132 [3800r,3808r:0)  0@3800r
%vreg134 [3776r,3784r:0)  0@3776r
%vreg135 [3784r,3792r:0)  0@3784r
%vreg141 [3744r,3776r:0)  0@3744r
%vreg143 [3768r,3776r:0)  0@3768r
%vreg145 [3736r,3768r:0)  0@3736r
%vreg146 [3616r,3736r:0)  0@3616r
%vreg148 [3760r,3832r:0)  0@3760r
%vreg149 [3732r,3760r:0)  0@3732r
%vreg152 [3536r,3568r:0)  0@3536r
%vreg155 [3520r,3536r:0)  0@3520r
%vreg158 [5120r,5136r:0)  0@5120r
%vreg160 [5104r,5120r:0)  0@5104r
%vreg161 [5088r,5104r:0)  0@5088r
%vreg165 [5056r,5072r:0)  0@5056r
%vreg166 [5040r,5056r:0)  0@5040r
%vreg168 [5024r,5072r:0)  0@5024r
%vreg169 [5008r,5024r:0)  0@5008r
%vreg173 [4976r,4992r:0)  0@4976r
%vreg174 [4960r,4976r:0)  0@4960r
%vreg176 [4944r,4992r:0)  0@4944r
%vreg177 [4928r,4944r:0)  0@4928r
%vreg181 [4896r,4912r:0)  0@4896r
%vreg182 [4880r,4896r:0)  0@4880r
%vreg184 [4864r,4912r:0)  0@4864r
%vreg185 [4848r,4864r:0)  0@4848r
%vreg189 [5216r,5232r:0)  0@5216r
%vreg190 [5200r,5216r:0)  0@5200r
%vreg192 [5184r,5232r:0)  0@5184r
%vreg193 [5168r,5184r:0)  0@5168r
%vreg197 [5296r,5312r:0)  0@5296r
%vreg198 [5280r,5296r:0)  0@5280r
%vreg199 [5264r,5312r:0)  0@5264r
%vreg203 [448r,464r:0)  0@448r
%vreg204 [432r,448r:0)  0@432r
%vreg206 [440r,464r:0)  0@440r
%vreg207 [400r,440r:0)  0@400r
%vreg210 [576r,592r:0)  0@576r
%vreg212 [560r,576r:0)  0@560r
%vreg213 [544r,560r:0)  0@544r
%vreg217 [800r,816r:0)  0@800r
%vreg218 [784r,800r:0)  0@784r
%vreg219 [792r,816r:0)  0@792r
%vreg224 [736r,752r:0)  0@736r
%vreg226 [720r,736r:0)  0@720r
%vreg228 [704r,720r:0)  0@704r
%vreg229 [688r,704r:0)  0@688r
%vreg230 [656r,672r:0)  0@656r
%vreg233 [880r,896r:0)  0@880r
%vreg234 [864r,880r:0)  0@864r
%vreg238 [1712r,1728r:0)  0@1712r
%vreg239 [1696r,1712r:0)  0@1696r
%vreg240 [1704r,1728r:0)  0@1704r
%vreg243 [1792r,1808r:0)  0@1792r
%vreg244 [1776r,1792r:0)  0@1776r
%vreg248 [2240r,2256r:0)  0@2240r
%vreg249 [2224r,2240r:0)  0@2224r
%vreg250 [2208r,2256r:0)  0@2208r
%vreg253 [1872r,1888r:0)  0@1872r
%vreg254 [1856r,1872r:0)  0@1856r
%vreg256 [1936r,1968r:0)  0@1936r
%vreg257 [2152r,2160r:0)  0@2152r
%vreg259 [2144r,2160r:0)  0@2144r
%vreg262 [2112r,2128r:0)  0@2112r
%vreg263 [2096r,2128r:0)  0@2096r
%vreg266 [1616r,1632r:0)  0@1616r
%vreg267 [1600r,1632r:0)  0@1600r
%vreg271 [1568r,1584r:0)  0@1568r
%vreg272 [1552r,1568r:0)  0@1552r
%vreg273 [1536r,1584r:0)  0@1536r
%vreg278 [1504r,1520r:0)  0@1504r
%vreg280 [1488r,1504r:0)  0@1488r
%vreg281 [1472r,1488r:0)  0@1472r
%vreg286 [1480r,1504r:0)  0@1480r
%vreg287 [1440r,1480r:0)  0@1440r
%vreg288 [1496r,1520r:0)  0@1496r
%vreg289 [1368r,1408r:0)  0@1368r
%vreg293 [1392r,1408r:0)  0@1392r
%vreg295 [1376r,1392r:0)  0@1376r
%vreg296 [1360r,1376r:0)  0@1360r
%vreg302 [1364r,1392r:0)  0@1364r
%vreg303 [1320r,1364r:0)  0@1320r
%vreg306 [1296r,1312r:0)  0@1296r
%vreg309 [1304r,1312r:0)  0@1304r
%vreg311 [1280r,1304r:0)  0@1280r
%vreg312 [1096r,1224r:0)  0@1096r
%vreg313 [1224r,1272r:0)  0@1224r
%vreg315 [1200r,1264r:0)  0@1200r
%vreg316 [1264r,1272r:0)  0@1264r
%vreg317 [1272r,1280r:0)  0@1272r
%vreg319 [1248r,1256r:0)  0@1248r
%vreg320 [1256r,1264r:0)  0@1256r
%vreg326 [1216r,1248r:0)  0@1216r
%vreg328 [1240r,1248r:0)  0@1240r
%vreg330 [1208r,1240r:0)  0@1208r
%vreg331 [1088r,1208r:0)  0@1088r
%vreg333 [1232r,1304r:0)  0@1232r
%vreg334 [1204r,1232r:0)  0@1204r
%vreg337 [1008r,1040r:0)  0@1008r
%vreg340 [992r,1008r:0)  0@992r
%vreg343 [2592r,2608r:0)  0@2592r
%vreg345 [2576r,2592r:0)  0@2576r
%vreg346 [2560r,2576r:0)  0@2560r
%vreg350 [2528r,2544r:0)  0@2528r
%vreg351 [2512r,2528r:0)  0@2512r
%vreg353 [2496r,2544r:0)  0@2496r
%vreg354 [2480r,2496r:0)  0@2480r
%vreg358 [2448r,2464r:0)  0@2448r
%vreg359 [2432r,2448r:0)  0@2432r
%vreg361 [2416r,2464r:0)  0@2416r
%vreg362 [2400r,2416r:0)  0@2400r
%vreg366 [2368r,2384r:0)  0@2368r
%vreg367 [2352r,2368r:0)  0@2352r
%vreg369 [2336r,2384r:0)  0@2336r
%vreg370 [2320r,2336r:0)  0@2320r
%vreg374 [2688r,2704r:0)  0@2688r
%vreg375 [2672r,2688r:0)  0@2672r
%vreg377 [2656r,2704r:0)  0@2656r
%vreg378 [2640r,2656r:0)  0@2640r
%vreg380 [5392r,5568r:0)  0@5392r
%vreg381 [5440r,5456r:0)  0@5440r
RegMasks: 176r 1984r 4512r 5488r
********** MACHINEINSTRS **********
# Machine code for function copy_input_until_stop: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
  fi#1: size=1, align=1, at location [SP]
  fi#2: size=4, align=4, at location [SP]
  fi#3: size=1, align=1, at location [SP]
  fi#4: size=4, align=4, at location [SP]
  fi#5: size=1, align=1, at location [SP]
Function Live Ins: %X0 in %vreg0, %LR in %vreg10

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %LR
16B		%vreg9<def> = COPY %LR; GPR64:%vreg9
32B		%vreg1<def> = COPY %X0; GPR64:%vreg1
64B		%vreg6<def> = ADRP <ga:@copy_input_until_stop>[TF=1]; GPR64common:%vreg6
80B		%vreg8<def> = ADDXri %vreg6, <ga:@copy_input_until_stop>[TF=34], 0; GPR64sp:%vreg8 GPR64common:%vreg6
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		%X0<def> = COPY %vreg8; GPR64sp:%vreg8
160B		%X1<def> = COPY %vreg9; GPR64:%vreg9
176B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
224B		STACKMAP 0, 0, 0, <fi#3>, 0, 0, <fi#5>, 0, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack3](align=1) LD8[FixedStack5](align=1) LD8[FixedStack1](align=1) LD8[FixedStack0] LD8[FixedStack2](align=4) LD8[FixedStack4](align=4) GPR64:%vreg1
240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
256B		STRXui %vreg1, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg1
272B		STRBBui %WZR, <fi#1>, 0; mem:ST1[FixedStack1]
288B		%vreg5<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg5
304B		%vreg4<def> = LDRWui %vreg5, 2; mem:LD4[%mode] GPR32common:%vreg4 GPR64common:%vreg5
320B		%WZR<def> = SUBSWri %vreg4, 2, 0, %NZCV<imp-def>; GPR32common:%vreg4
336B		Bcc 1, <BB#20>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#20 BB#1

352B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
368B		B <BB#2>
	    Successors according to CFG: BB#2

384B	BB#2: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#1 BB#18
400B		%vreg207<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg207
432B		%vreg204<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg204
440B		%vreg206<def> = LDRWui %vreg207, 27; mem:LD4[%nblock] GPR32:%vreg206 GPR64common:%vreg207
448B		%vreg203<def> = LDRWui %vreg204, 28; mem:LD4[%nblockMAX] GPR32:%vreg203 GPR64common:%vreg204
464B		%WZR<def> = SUBSWrr %vreg206, %vreg203, %NZCV<imp-def>; GPR32:%vreg206,%vreg203
480B		Bcc 11, <BB#4>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#4 BB#3

496B	BB#3: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#2
512B		B <BB#19>
	    Successors according to CFG: BB#19

528B	BB#4: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#2
544B		%vreg213<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg213
560B		%vreg212<def> = LDRXui %vreg213, 0; mem:LD8[%strm] GPR64common:%vreg212,%vreg213
576B		%vreg210<def> = LDRWui %vreg212, 2; mem:LD4[%avail_in] GPR32:%vreg210 GPR64common:%vreg212
592B		CBNZW %vreg210, <BB#6>; GPR32:%vreg210
	    Successors according to CFG: BB#6 BB#5

608B	BB#5: derived from LLVM BB %if.then.4
	    Predecessors according to CFG: BB#4
624B		B <BB#19>
	    Successors according to CFG: BB#19

640B	BB#6: derived from LLVM BB %if.end.5
	    Predecessors according to CFG: BB#4
656B		%vreg230<def> = MOVi32imm 1; GPR32:%vreg230
672B		STRBBui %vreg230, <fi#1>, 0; mem:ST1[FixedStack1] GPR32:%vreg230
688B		%vreg229<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg229
704B		%vreg228<def> = LDRXui %vreg229, 0; mem:LD8[%strm6] GPR64common:%vreg228,%vreg229
720B		%vreg226<def> = LDRXui %vreg228, 0; mem:LD8[%next_in] GPR64common:%vreg226,%vreg228
736B		%vreg224<def> = LDRBBui %vreg226, 0; mem:LD1[%11] GPR32:%vreg224 GPR64common:%vreg226
752B		STRWui %vreg224, <fi#2>, 0; mem:ST4[FixedStack2] GPR32:%vreg224
784B		%vreg218<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg218
792B		%vreg219<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg219
800B		%vreg217<def> = LDRWui %vreg218, 23; mem:LD4[%state_in_ch] GPR32:%vreg217 GPR64common:%vreg218
816B		%WZR<def> = SUBSWrr %vreg219, %vreg217, %NZCV<imp-def>; GPR32:%vreg219,%vreg217
832B		Bcc 0, <BB#9>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#9 BB#7

848B	BB#7: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#6
864B		%vreg234<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg234
880B		%vreg233<def> = LDRWui %vreg234, 24; mem:LD4[%state_in_len] GPR32common:%vreg233 GPR64common:%vreg234
896B		%WZR<def> = SUBSWri %vreg233, 1, 0, %NZCV<imp-def>; GPR32common:%vreg233
912B		Bcc 1, <BB#9>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#9 BB#8

928B	BB#8: derived from LLVM BB %if.then.11
	    Predecessors according to CFG: BB#7
992B		%vreg340<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg340
1008B		%vreg337<def> = LDRWui %vreg340, 23; mem:LD4[%state_in_ch12] GPR32:%vreg337 GPR64common:%vreg340
1040B		STRBBui %vreg337, <fi#3>, 0; mem:ST1[FixedStack3] GPR32:%vreg337
1088B		%vreg331<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg331
1096B		%vreg312<def> = ADRP <ga:@BZ2_crc32Table>[TF=1]; GPR64common:%vreg312
1200B		%vreg315<def> = MOVi64imm 4; GPR64:%vreg315
1204B		%vreg334<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg334
1208B		%vreg330<def> = LDRWui %vreg331, 162; mem:LD4[%blockCRC14] GPR32:%vreg330 GPR64common:%vreg331
1216B		%vreg326<def> = LDRBBui <fi#3>, 0; mem:LD1[FixedStack3] GPR32:%vreg326
1224B		%vreg313<def> = ADDXri %vreg312, <ga:@BZ2_crc32Table>[TF=34], 0; GPR64common:%vreg313,%vreg312
1232B		%vreg333<def> = LDRWui %vreg334, 162; mem:LD4[%blockCRC] GPR32:%vreg333 GPR64common:%vreg334
1240B		%vreg328<def> = UBFMWri %vreg330, 24, 31; GPR32:%vreg328,%vreg330
1248B		%vreg319:sub_32<def,read-undef> = EORWrr %vreg328, %vreg326; GPR64:%vreg319 GPR32:%vreg328,%vreg326
1256B		%vreg320<def> = UBFMXri %vreg319, 0, 31; GPR64:%vreg320,%vreg319
1264B		%vreg316<def> = MADDXrrr %vreg320, %vreg315, %XZR; GPR64:%vreg316,%vreg320,%vreg315
1272B		%vreg317<def> = ADDXrr %vreg313, %vreg316; GPR64common:%vreg317,%vreg313 GPR64:%vreg316
1280B		%vreg311<def> = LDRWui %vreg317, 0; mem:LD4[%arrayidx] GPR32:%vreg311 GPR64common:%vreg317
1296B		%vreg306<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg306
1304B		%vreg309<def> = EORWrs %vreg311, %vreg333, 8; GPR32:%vreg309,%vreg311,%vreg333
1312B		STRWui %vreg309, %vreg306, 162; mem:ST4[%blockCRC17] GPR32:%vreg309 GPR64common:%vreg306
1320B		%vreg303<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg303
1360B		%vreg296<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg296
1364B		%vreg302:sub_32<def,read-undef> = LDRWui %vreg303, 23; mem:LD4[%state_in_ch18] GPR64:%vreg302 GPR64common:%vreg303
1368B		%vreg289<def> = MOVi32imm 1; GPR32:%vreg289
1376B		%vreg295<def> = ADDXri %vreg296, 128, 0; GPR64common:%vreg295,%vreg296
1392B		%vreg293<def> = ADDXrr %vreg295, %vreg302; GPR64common:%vreg293,%vreg295 GPR64:%vreg302
1408B		STRBBui %vreg289, %vreg293, 0; mem:ST1[%arrayidx20] GPR32:%vreg289 GPR64common:%vreg293
1440B		%vreg287<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg287
1472B		%vreg281<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg281
1480B		%vreg286<def> = LDRSWui %vreg287, 27; mem:LD4[%nblock21] GPR64:%vreg286 GPR64common:%vreg287
1488B		%vreg280<def> = LDRXui %vreg281, 8; mem:LD8[%block] GPR64:%vreg280 GPR64common:%vreg281
1496B		%vreg288<def> = LDRBBui <fi#3>, 0; mem:LD1[FixedStack3] GPR32:%vreg288
1504B		%vreg278<def> = ADDXrr %vreg280, %vreg286; GPR64common:%vreg278 GPR64:%vreg280,%vreg286
1520B		STRBBui %vreg288, %vreg278, 0; mem:ST1[%arrayidx23] GPR32:%vreg288 GPR64common:%vreg278
1536B		%vreg273<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg273
1552B		%vreg272<def> = LDRWui %vreg273, 27; mem:LD4[%nblock24] GPR32common:%vreg272 GPR64common:%vreg273
1568B		%vreg271<def> = ADDWri %vreg272, 1, 0; GPR32common:%vreg271,%vreg272
1584B		STRWui %vreg271, %vreg273, 27; mem:ST4[%nblock24] GPR32common:%vreg271 GPR64common:%vreg273
1600B		%vreg267<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg267
1616B		%vreg266<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg266
1632B		STRWui %vreg267, %vreg266, 23; mem:ST4[%state_in_ch25] GPR32:%vreg267 GPR64common:%vreg266
1648B		B <BB#16>
	    Successors according to CFG: BB#16

1664B	BB#9: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#6 BB#7
1696B		%vreg239<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg239
1704B		%vreg240<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg240
1712B		%vreg238<def> = LDRWui %vreg239, 23; mem:LD4[%state_in_ch26] GPR32:%vreg238 GPR64common:%vreg239
1728B		%WZR<def> = SUBSWrr %vreg240, %vreg238, %NZCV<imp-def>; GPR32:%vreg240,%vreg238
1744B		Bcc 1, <BB#11>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#11 BB#10

1760B	BB#10: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#9
1776B		%vreg244<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg244
1792B		%vreg243<def> = LDRWui %vreg244, 24; mem:LD4[%state_in_len29] GPR32common:%vreg243 GPR64common:%vreg244
1808B		%WZR<def> = SUBSWri %vreg243, 255, 0, %NZCV<imp-def>; GPR32common:%vreg243
1824B		Bcc 1, <BB#14>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#14 BB#11

1840B	BB#11: derived from LLVM BB %if.then.32
	    Predecessors according to CFG: BB#9 BB#10
1856B		%vreg254<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg254
1872B		%vreg253<def> = LDRWui %vreg254, 23; mem:LD4[%state_in_ch33] GPR32common:%vreg253 GPR64common:%vreg254
1888B		%WZR<def> = SUBSWri %vreg253, 256, 0, %NZCV<imp-def>; GPR32common:%vreg253
1904B		Bcc 2, <BB#13>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#13 BB#12

1920B	BB#12: derived from LLVM BB %if.then.36
	    Predecessors according to CFG: BB#11
1936B		%vreg256<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg256
1952B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1968B		%X0<def> = COPY %vreg256; GPR64:%vreg256
1984B		BL <ga:@add_pair_to_block>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>
2000B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2016B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2032B		STACKMAP 1, 0, 0, <fi#3>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack3](align=1) LD8[FixedStack1](align=1) LD8[FixedStack0] LD8[FixedStack2](align=4)
2048B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#13

2064B	BB#13: derived from LLVM BB %if.end.37
	    Predecessors according to CFG: BB#11 BB#12
2096B		%vreg263<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg263
2112B		%vreg262<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg262
2128B		STRWui %vreg263, %vreg262, 23; mem:ST4[%state_in_ch38] GPR32:%vreg263 GPR64common:%vreg262
2144B		%vreg259<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg259
2152B		%vreg257<def> = MOVi32imm 1; GPR32:%vreg257
2160B		STRWui %vreg257, %vreg259, 24; mem:ST4[%state_in_len39] GPR32:%vreg257 GPR64common:%vreg259
2176B		B <BB#15>
	    Successors according to CFG: BB#15

2192B	BB#14: derived from LLVM BB %if.else.40
	    Predecessors according to CFG: BB#10
2208B		%vreg250<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg250
2224B		%vreg249<def> = LDRWui %vreg250, 24; mem:LD4[%state_in_len41] GPR32common:%vreg249 GPR64common:%vreg250
2240B		%vreg248<def> = ADDWri %vreg249, 1, 0; GPR32common:%vreg248,%vreg249
2256B		STRWui %vreg248, %vreg250, 24; mem:ST4[%state_in_len41] GPR32common:%vreg248 GPR64common:%vreg250
	    Successors according to CFG: BB#15

2272B	BB#15: derived from LLVM BB %if.end.43
	    Predecessors according to CFG: BB#14 BB#13
2288B		B <BB#16>
	    Successors according to CFG: BB#16

2304B	BB#16: derived from LLVM BB %if.end.44
	    Predecessors according to CFG: BB#15 BB#8
2320B		%vreg370<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg370
2336B		%vreg369<def> = LDRXui %vreg370, 0; mem:LD8[%strm45] GPR64common:%vreg369,%vreg370
2352B		%vreg367<def> = LDRXui %vreg369, 0; mem:LD8[%next_in46] GPR64common:%vreg367,%vreg369
2368B		%vreg366<def> = ADDXri %vreg367, 1, 0; GPR64common:%vreg366,%vreg367
2384B		STRXui %vreg366, %vreg369, 0; mem:ST8[%next_in46] GPR64common:%vreg366,%vreg369
2400B		%vreg362<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg362
2416B		%vreg361<def> = LDRXui %vreg362, 0; mem:LD8[%strm47] GPR64common:%vreg361,%vreg362
2432B		%vreg359<def> = LDRWui %vreg361, 2; mem:LD4[%avail_in48] GPR32common:%vreg359 GPR64common:%vreg361
2448B		%vreg358<def> = SUBWri %vreg359, 1, 0; GPR32common:%vreg358,%vreg359
2464B		STRWui %vreg358, %vreg361, 2; mem:ST4[%avail_in48] GPR32common:%vreg358 GPR64common:%vreg361
2480B		%vreg354<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg354
2496B		%vreg353<def> = LDRXui %vreg354, 0; mem:LD8[%strm49] GPR64common:%vreg353,%vreg354
2512B		%vreg351<def> = LDRWui %vreg353, 3; mem:LD4[%total_in_lo32] GPR32common:%vreg351 GPR64common:%vreg353
2528B		%vreg350<def> = ADDWri %vreg351, 1, 0; GPR32common:%vreg350,%vreg351
2544B		STRWui %vreg350, %vreg353, 3; mem:ST4[%total_in_lo32] GPR32common:%vreg350 GPR64common:%vreg353
2560B		%vreg346<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg346
2576B		%vreg345<def> = LDRXui %vreg346, 0; mem:LD8[%strm51] GPR64common:%vreg345,%vreg346
2592B		%vreg343<def> = LDRWui %vreg345, 3; mem:LD4[%total_in_lo3252] GPR32:%vreg343 GPR64common:%vreg345
2608B		CBNZW %vreg343, <BB#18>; GPR32:%vreg343
	    Successors according to CFG: BB#18 BB#17

2624B	BB#17: derived from LLVM BB %if.then.55
	    Predecessors according to CFG: BB#16
2640B		%vreg378<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg378
2656B		%vreg377<def> = LDRXui %vreg378, 0; mem:LD8[%strm56] GPR64common:%vreg377,%vreg378
2672B		%vreg375<def> = LDRWui %vreg377, 4; mem:LD4[%total_in_hi32] GPR32common:%vreg375 GPR64common:%vreg377
2688B		%vreg374<def> = ADDWri %vreg375, 1, 0; GPR32common:%vreg374,%vreg375
2704B		STRWui %vreg374, %vreg377, 4; mem:ST4[%total_in_hi32] GPR32common:%vreg374 GPR64common:%vreg377
	    Successors according to CFG: BB#18

2720B	BB#18: derived from LLVM BB %if.end.58
	    Predecessors according to CFG: BB#16 BB#17
2736B		B <BB#2>
	    Successors according to CFG: BB#2

2752B	BB#19: derived from LLVM BB %while.end
	    Predecessors according to CFG: BB#5 BB#3
2768B		B <BB#41>
	    Successors according to CFG: BB#41

2784B	BB#20: derived from LLVM BB %if.else.59
	    Predecessors according to CFG: BB#0
2800B		B <BB#21>
	    Successors according to CFG: BB#21

2816B	BB#21: derived from LLVM BB %while.body.60
	    Predecessors according to CFG: BB#20 BB#39
2832B		%vreg18<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg18
2864B		%vreg15<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg15
2872B		%vreg17<def> = LDRWui %vreg18, 27; mem:LD4[%nblock61] GPR32:%vreg17 GPR64common:%vreg18
2880B		%vreg14<def> = LDRWui %vreg15, 28; mem:LD4[%nblockMAX62] GPR32:%vreg14 GPR64common:%vreg15
2896B		%WZR<def> = SUBSWrr %vreg17, %vreg14, %NZCV<imp-def>; GPR32:%vreg17,%vreg14
2912B		Bcc 11, <BB#23>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#23 BB#22

2928B	BB#22: derived from LLVM BB %if.then.65
	    Predecessors according to CFG: BB#21
2944B		B <BB#40>
	    Successors according to CFG: BB#40

2960B	BB#23: derived from LLVM BB %if.end.66
	    Predecessors according to CFG: BB#21
2976B		%vreg24<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg24
2992B		%vreg23<def> = LDRXui %vreg24, 0; mem:LD8[%strm67] GPR64common:%vreg23,%vreg24
3008B		%vreg21<def> = LDRWui %vreg23, 2; mem:LD4[%avail_in68] GPR32:%vreg21 GPR64common:%vreg23
3024B		CBNZW %vreg21, <BB#25>; GPR32:%vreg21
	    Successors according to CFG: BB#25 BB#24

3040B	BB#24: derived from LLVM BB %if.then.71
	    Predecessors according to CFG: BB#23
3056B		B <BB#40>
	    Successors according to CFG: BB#40

3072B	BB#25: derived from LLVM BB %if.end.72
	    Predecessors according to CFG: BB#23
3088B		%vreg28<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg28
3104B		%vreg27<def> = LDRWui %vreg28, 4; mem:LD4[%avail_in_expect] GPR32:%vreg27 GPR64common:%vreg28
3120B		CBNZW %vreg27, <BB#27>; GPR32:%vreg27
	    Successors according to CFG: BB#27 BB#26

3136B	BB#26: derived from LLVM BB %if.then.75
	    Predecessors according to CFG: BB#25
3152B		B <BB#40>
	    Successors according to CFG: BB#40

3168B	BB#27: derived from LLVM BB %if.end.76
	    Predecessors according to CFG: BB#25
3184B		%vreg45<def> = MOVi32imm 1; GPR32:%vreg45
3200B		STRBBui %vreg45, <fi#1>, 0; mem:ST1[FixedStack1] GPR32:%vreg45
3216B		%vreg44<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg44
3232B		%vreg43<def> = LDRXui %vreg44, 0; mem:LD8[%strm78] GPR64common:%vreg43,%vreg44
3248B		%vreg41<def> = LDRXui %vreg43, 0; mem:LD8[%next_in79] GPR64common:%vreg41,%vreg43
3264B		%vreg39<def> = LDRBBui %vreg41, 0; mem:LD1[%78] GPR32:%vreg39 GPR64common:%vreg41
3280B		STRWui %vreg39, <fi#4>, 0; mem:ST4[FixedStack4] GPR32:%vreg39
3312B		%vreg33<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg33
3320B		%vreg34<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg34
3328B		%vreg32<def> = LDRWui %vreg33, 23; mem:LD4[%state_in_ch81] GPR32:%vreg32 GPR64common:%vreg33
3344B		%WZR<def> = SUBSWrr %vreg34, %vreg32, %NZCV<imp-def>; GPR32:%vreg34,%vreg32
3360B		Bcc 0, <BB#30>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#30 BB#28

3376B	BB#28: derived from LLVM BB %land.lhs.true.84
	    Predecessors according to CFG: BB#27
3392B		%vreg49<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg49
3408B		%vreg48<def> = LDRWui %vreg49, 24; mem:LD4[%state_in_len85] GPR32common:%vreg48 GPR64common:%vreg49
3424B		%WZR<def> = SUBSWri %vreg48, 1, 0, %NZCV<imp-def>; GPR32common:%vreg48
3440B		Bcc 1, <BB#30>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#30 BB#29

3456B	BB#29: derived from LLVM BB %if.then.88
	    Predecessors according to CFG: BB#28
3520B		%vreg155<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg155
3536B		%vreg152<def> = LDRWui %vreg155, 23; mem:LD4[%state_in_ch90] GPR32:%vreg152 GPR64common:%vreg155
3568B		STRBBui %vreg152, <fi#5>, 0; mem:ST1[FixedStack5] GPR32:%vreg152
3616B		%vreg146<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg146
3624B		%vreg127<def> = ADRP <ga:@BZ2_crc32Table>[TF=1]; GPR64common:%vreg127
3728B		%vreg130<def> = MOVi64imm 4; GPR64:%vreg130
3732B		%vreg149<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg149
3736B		%vreg145<def> = LDRWui %vreg146, 162; mem:LD4[%blockCRC94] GPR32:%vreg145 GPR64common:%vreg146
3744B		%vreg141<def> = LDRBBui <fi#5>, 0; mem:LD1[FixedStack5] GPR32:%vreg141
3752B		%vreg128<def> = ADDXri %vreg127, <ga:@BZ2_crc32Table>[TF=34], 0; GPR64common:%vreg128,%vreg127
3760B		%vreg148<def> = LDRWui %vreg149, 162; mem:LD4[%blockCRC92] GPR32:%vreg148 GPR64common:%vreg149
3768B		%vreg143<def> = UBFMWri %vreg145, 24, 31; GPR32:%vreg143,%vreg145
3776B		%vreg134:sub_32<def,read-undef> = EORWrr %vreg143, %vreg141; GPR64:%vreg134 GPR32:%vreg143,%vreg141
3784B		%vreg135<def> = UBFMXri %vreg134, 0, 31; GPR64:%vreg135,%vreg134
3792B		%vreg131<def> = MADDXrrr %vreg135, %vreg130, %XZR; GPR64:%vreg131,%vreg135,%vreg130
3800B		%vreg132<def> = ADDXrr %vreg128, %vreg131; GPR64common:%vreg132,%vreg128 GPR64:%vreg131
3808B		%vreg126<def> = LDRWui %vreg132, 0; mem:LD4[%arrayidx99] GPR32:%vreg126 GPR64common:%vreg132
3824B		%vreg121<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg121
3832B		%vreg124<def> = EORWrs %vreg126, %vreg148, 8; GPR32:%vreg124,%vreg126,%vreg148
3840B		STRWui %vreg124, %vreg121, 162; mem:ST4[%blockCRC101] GPR32:%vreg124 GPR64common:%vreg121
3848B		%vreg118<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg118
3888B		%vreg111<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg111
3892B		%vreg117:sub_32<def,read-undef> = LDRWui %vreg118, 23; mem:LD4[%state_in_ch102] GPR64:%vreg117 GPR64common:%vreg118
3896B		%vreg104<def> = MOVi32imm 1; GPR32:%vreg104
3904B		%vreg110<def> = ADDXri %vreg111, 128, 0; GPR64common:%vreg110,%vreg111
3920B		%vreg108<def> = ADDXrr %vreg110, %vreg117; GPR64common:%vreg108,%vreg110 GPR64:%vreg117
3936B		STRBBui %vreg104, %vreg108, 0; mem:ST1[%arrayidx105] GPR32:%vreg104 GPR64common:%vreg108
3968B		%vreg102<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg102
4000B		%vreg96<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg96
4008B		%vreg101<def> = LDRSWui %vreg102, 27; mem:LD4[%nblock106] GPR64:%vreg101 GPR64common:%vreg102
4016B		%vreg95<def> = LDRXui %vreg96, 8; mem:LD8[%block108] GPR64:%vreg95 GPR64common:%vreg96
4024B		%vreg103<def> = LDRBBui <fi#5>, 0; mem:LD1[FixedStack5] GPR32:%vreg103
4032B		%vreg93<def> = ADDXrr %vreg95, %vreg101; GPR64common:%vreg93 GPR64:%vreg95,%vreg101
4048B		STRBBui %vreg103, %vreg93, 0; mem:ST1[%arrayidx109] GPR32:%vreg103 GPR64common:%vreg93
4064B		%vreg88<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg88
4080B		%vreg87<def> = LDRWui %vreg88, 27; mem:LD4[%nblock110] GPR32common:%vreg87 GPR64common:%vreg88
4096B		%vreg86<def> = ADDWri %vreg87, 1, 0; GPR32common:%vreg86,%vreg87
4112B		STRWui %vreg86, %vreg88, 27; mem:ST4[%nblock110] GPR32common:%vreg86 GPR64common:%vreg88
4128B		%vreg82<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg82
4144B		%vreg81<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg81
4160B		STRWui %vreg82, %vreg81, 23; mem:ST4[%state_in_ch112] GPR32:%vreg82 GPR64common:%vreg81
4176B		B <BB#37>
	    Successors according to CFG: BB#37

4192B	BB#30: derived from LLVM BB %if.else.113
	    Predecessors according to CFG: BB#27 BB#28
4224B		%vreg54<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg54
4232B		%vreg55<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg55
4240B		%vreg53<def> = LDRWui %vreg54, 23; mem:LD4[%state_in_ch114] GPR32:%vreg53 GPR64common:%vreg54
4256B		%WZR<def> = SUBSWrr %vreg55, %vreg53, %NZCV<imp-def>; GPR32:%vreg55,%vreg53
4272B		Bcc 1, <BB#32>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#32 BB#31

4288B	BB#31: derived from LLVM BB %lor.lhs.false.117
	    Predecessors according to CFG: BB#30
4304B		%vreg59<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg59
4320B		%vreg58<def> = LDRWui %vreg59, 24; mem:LD4[%state_in_len118] GPR32common:%vreg58 GPR64common:%vreg59
4336B		%WZR<def> = SUBSWri %vreg58, 255, 0, %NZCV<imp-def>; GPR32common:%vreg58
4352B		Bcc 1, <BB#35>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#35 BB#32

4368B	BB#32: derived from LLVM BB %if.then.121
	    Predecessors according to CFG: BB#30 BB#31
4384B		%vreg69<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg69
4400B		%vreg68<def> = LDRWui %vreg69, 23; mem:LD4[%state_in_ch122] GPR32common:%vreg68 GPR64common:%vreg69
4416B		%WZR<def> = SUBSWri %vreg68, 256, 0, %NZCV<imp-def>; GPR32common:%vreg68
4432B		Bcc 2, <BB#34>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#34 BB#33

4448B	BB#33: derived from LLVM BB %if.then.125
	    Predecessors according to CFG: BB#32
4464B		%vreg71<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg71
4480B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4496B		%X0<def> = COPY %vreg71; GPR64:%vreg71
4512B		BL <ga:@add_pair_to_block>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>
4528B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4544B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4560B		STACKMAP 2, 0, 0, <fi#5>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack5](align=1) LD8[FixedStack1](align=1) LD8[FixedStack0] LD8[FixedStack4](align=4)
4576B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#34

4592B	BB#34: derived from LLVM BB %if.end.126
	    Predecessors according to CFG: BB#32 BB#33
4624B		%vreg78<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg78
4640B		%vreg77<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg77
4656B		STRWui %vreg78, %vreg77, 23; mem:ST4[%state_in_ch127] GPR32:%vreg78 GPR64common:%vreg77
4672B		%vreg74<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg74
4680B		%vreg72<def> = MOVi32imm 1; GPR32:%vreg72
4688B		STRWui %vreg72, %vreg74, 24; mem:ST4[%state_in_len128] GPR32:%vreg72 GPR64common:%vreg74
4704B		B <BB#36>
	    Successors according to CFG: BB#36

4720B	BB#35: derived from LLVM BB %if.else.129
	    Predecessors according to CFG: BB#31
4736B		%vreg65<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg65
4752B		%vreg64<def> = LDRWui %vreg65, 24; mem:LD4[%state_in_len130] GPR32common:%vreg64 GPR64common:%vreg65
4768B		%vreg63<def> = ADDWri %vreg64, 1, 0; GPR32common:%vreg63,%vreg64
4784B		STRWui %vreg63, %vreg65, 24; mem:ST4[%state_in_len130] GPR32common:%vreg63 GPR64common:%vreg65
	    Successors according to CFG: BB#36

4800B	BB#36: derived from LLVM BB %if.end.132
	    Predecessors according to CFG: BB#35 BB#34
4816B		B <BB#37>
	    Successors according to CFG: BB#37

4832B	BB#37: derived from LLVM BB %if.end.133
	    Predecessors according to CFG: BB#36 BB#29
4848B		%vreg185<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg185
4864B		%vreg184<def> = LDRXui %vreg185, 0; mem:LD8[%strm134] GPR64common:%vreg184,%vreg185
4880B		%vreg182<def> = LDRXui %vreg184, 0; mem:LD8[%next_in135] GPR64common:%vreg182,%vreg184
4896B		%vreg181<def> = ADDXri %vreg182, 1, 0; GPR64common:%vreg181,%vreg182
4912B		STRXui %vreg181, %vreg184, 0; mem:ST8[%next_in135] GPR64common:%vreg181,%vreg184
4928B		%vreg177<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg177
4944B		%vreg176<def> = LDRXui %vreg177, 0; mem:LD8[%strm137] GPR64common:%vreg176,%vreg177
4960B		%vreg174<def> = LDRWui %vreg176, 2; mem:LD4[%avail_in138] GPR32common:%vreg174 GPR64common:%vreg176
4976B		%vreg173<def> = SUBWri %vreg174, 1, 0; GPR32common:%vreg173,%vreg174
4992B		STRWui %vreg173, %vreg176, 2; mem:ST4[%avail_in138] GPR32common:%vreg173 GPR64common:%vreg176
5008B		%vreg169<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg169
5024B		%vreg168<def> = LDRXui %vreg169, 0; mem:LD8[%strm140] GPR64common:%vreg168,%vreg169
5040B		%vreg166<def> = LDRWui %vreg168, 3; mem:LD4[%total_in_lo32141] GPR32common:%vreg166 GPR64common:%vreg168
5056B		%vreg165<def> = ADDWri %vreg166, 1, 0; GPR32common:%vreg165,%vreg166
5072B		STRWui %vreg165, %vreg168, 3; mem:ST4[%total_in_lo32141] GPR32common:%vreg165 GPR64common:%vreg168
5088B		%vreg161<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg161
5104B		%vreg160<def> = LDRXui %vreg161, 0; mem:LD8[%strm143] GPR64common:%vreg160,%vreg161
5120B		%vreg158<def> = LDRWui %vreg160, 3; mem:LD4[%total_in_lo32144] GPR32:%vreg158 GPR64common:%vreg160
5136B		CBNZW %vreg158, <BB#39>; GPR32:%vreg158
	    Successors according to CFG: BB#39 BB#38

5152B	BB#38: derived from LLVM BB %if.then.147
	    Predecessors according to CFG: BB#37
5168B		%vreg193<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg193
5184B		%vreg192<def> = LDRXui %vreg193, 0; mem:LD8[%strm148] GPR64common:%vreg192,%vreg193
5200B		%vreg190<def> = LDRWui %vreg192, 4; mem:LD4[%total_in_hi32149] GPR32common:%vreg190 GPR64common:%vreg192
5216B		%vreg189<def> = ADDWri %vreg190, 1, 0; GPR32common:%vreg189,%vreg190
5232B		STRWui %vreg189, %vreg192, 4; mem:ST4[%total_in_hi32149] GPR32common:%vreg189 GPR64common:%vreg192
	    Successors according to CFG: BB#39

5248B	BB#39: derived from LLVM BB %if.end.151
	    Predecessors according to CFG: BB#37 BB#38
5264B		%vreg199<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg199
5280B		%vreg198<def> = LDRWui %vreg199, 4; mem:LD4[%avail_in_expect152] GPR32common:%vreg198 GPR64common:%vreg199
5296B		%vreg197<def> = SUBWri %vreg198, 1, 0; GPR32common:%vreg197,%vreg198
5312B		STRWui %vreg197, %vreg199, 4; mem:ST4[%avail_in_expect152] GPR32common:%vreg197 GPR64common:%vreg199
5328B		B <BB#21>
	    Successors according to CFG: BB#21

5344B	BB#40: derived from LLVM BB %while.end.154
	    Predecessors according to CFG: BB#26 BB#24 BB#22
5360B		B <BB#41>
	    Successors according to CFG: BB#41

5376B	BB#41: derived from LLVM BB %if.end.155
	    Predecessors according to CFG: BB#40 BB#19
5392B		%vreg380<def> = LDRBBui <fi#1>, 0; mem:LD1[%progress_in] GPR32:%vreg380
5424B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5440B		%vreg381<def> = MOVaddr <ga:@copy_input_until_stop>[TF=1], <ga:@copy_input_until_stop>[TF=34]; GPR64:%vreg381
5456B		%X0<def> = COPY %vreg381; GPR64:%vreg381
5472B		%X1<def> = COPY %vreg9; GPR64:%vreg9
5488B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %SP<imp-def>
5504B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5520B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5536B		STACKMAP 3, 0, %vreg380, %LR<earlyclobber,imp-def,dead>, ...; GPR32:%vreg380
5552B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5568B		%W0<def> = COPY %vreg380; GPR32:%vreg380
5584B		RET_ReallyLR %W0<imp-use>

# End machine code for function copy_input_until_stop.


selectOrSplit GPR64:%vreg9 [16r,5472r:0)  0@16r w=5.174180e-04
hints: %X1
missed hint %X1
assigning %vreg9 to %X19: W19 [16r,5472r:0)  0@16r

selectOrSplit GPR64:%vreg1 [32r,256r:0)  0@32r w=4.855769e-03
hints: %X0
missed hint %X0
assigning %vreg1 to %X20: W20 [32r,256r:0)  0@32r

selectOrSplit GPR64sp:%vreg8 [80r,144r:0)  0@80r w=4.353448e-03
hints: %X0
assigning %vreg8 to %X0: W0 [80r,144r:0)  0@80r

selectOrSplit GPR64:%vreg256 [1936r,1968r:0)  0@1936r w=2.114740e-04
hints: %X0
assigning %vreg256 to %X0: W0 [1936r,1968r:0)  0@1936r

selectOrSplit GPR64:%vreg71 [4464r,4496r:0)  0@4464r w=8.615609e-05
hints: %X0
assigning %vreg71 to %X0: W0 [4464r,4496r:0)  0@4464r

selectOrSplit GPR32:%vreg380 [5392r,5568r:0)  0@5392r w=5.260417e-03
hints: %W0
missed hint %W0
assigning %vreg380 to %W20: W20 [5392r,5568r:0)  0@5392r

selectOrSplit GPR64:%vreg381 [5440r,5456r:0)  0@5440r w=inf
hints: %X0
assigning %vreg381 to %X0: W0 [5440r,5456r:0)  0@5440r

selectOrSplit GPR64common:%vreg6 [64r,80r:0)  0@64r w=inf
assigning %vreg6 to %X8: W8 [64r,80r:0)  0@64r

selectOrSplit GPR64common:%vreg5 [288r,304r:0)  0@288r w=inf
assigning %vreg5 to %X8: W8 [288r,304r:0)  0@288r

selectOrSplit GPR32common:%vreg4 [304r,320r:0)  0@304r w=inf
assigning %vreg4 to %W8: W8 [304r,320r:0)  0@304r

selectOrSplit GPR64common:%vreg207 [400r,440r:0)  0@400r w=3.030303e-03
assigning %vreg207 to %X8: W8 [400r,440r:0)  0@400r

selectOrSplit GPR64common:%vreg204 [432r,448r:0)  0@432r w=3.205128e-03
assigning %vreg204 to %X9: W9 [432r,448r:0)  0@432r

selectOrSplit GPR32:%vreg206 [440r,464r:0)  0@440r w=3.144654e-03
assigning %vreg206 to %W8: W8 [440r,464r:0)  0@440r

selectOrSplit GPR32:%vreg203 [448r,464r:0)  0@448r w=inf
assigning %vreg203 to %W9: W9 [448r,464r:0)  0@448r

selectOrSplit GPR64common:%vreg213 [544r,560r:0)  0@544r w=inf
assigning %vreg213 to %X8: W8 [544r,560r:0)  0@544r

selectOrSplit GPR64common:%vreg212 [560r,576r:0)  0@560r w=inf
assigning %vreg212 to %X8: W8 [560r,576r:0)  0@560r

selectOrSplit GPR32:%vreg210 [576r,592r:0)  0@576r w=inf
assigning %vreg210 to %W8: W8 [576r,592r:0)  0@576r

selectOrSplit GPR32:%vreg230 [656r,672r:0)  0@656r w=inf
assigning %vreg230 to %W8: W8 [656r,672r:0)  0@656r

selectOrSplit GPR64common:%vreg229 [688r,704r:0)  0@688r w=inf
assigning %vreg229 to %X8: W8 [688r,704r:0)  0@688r

selectOrSplit GPR64common:%vreg228 [704r,720r:0)  0@704r w=inf
assigning %vreg228 to %X8: W8 [704r,720r:0)  0@704r

selectOrSplit GPR64common:%vreg226 [720r,736r:0)  0@720r w=inf
assigning %vreg226 to %X8: W8 [720r,736r:0)  0@720r

selectOrSplit GPR32:%vreg224 [736r,752r:0)  0@736r w=inf
assigning %vreg224 to %W8: W8 [736r,752r:0)  0@736r

selectOrSplit GPR64common:%vreg218 [784r,800r:0)  0@784r w=7.972555e-04
assigning %vreg218 to %X8: W8 [784r,800r:0)  0@784r

selectOrSplit GPR32:%vreg219 [792r,816r:0)  0@792r w=7.822129e-04
assigning %vreg219 to %W9: W9 [792r,816r:0)  0@792r

selectOrSplit GPR32:%vreg217 [800r,816r:0)  0@800r w=inf
assigning %vreg217 to %W8: W8 [800r,816r:0)  0@800r

selectOrSplit GPR64common:%vreg234 [864r,880r:0)  0@864r w=inf
assigning %vreg234 to %X8: W8 [864r,880r:0)  0@864r

selectOrSplit GPR32common:%vreg233 [880r,896r:0)  0@880r w=inf
assigning %vreg233 to %W8: W8 [880r,896r:0)  0@880r

selectOrSplit GPR64common:%vreg340 [992r,1008r:0)  0@992r w=inf
assigning %vreg340 to %X8: W8 [992r,1008r:0)  0@992r

selectOrSplit GPR32:%vreg337 [1008r,1040r:0)  0@1008r w=inf
assigning %vreg337 to %W8: W8 [1008r,1040r:0)  0@1008r

selectOrSplit GPR64common:%vreg331 [1088r,1208r:0)  0@1088r w=1.546193e-04
assigning %vreg331 to %X8: W8 [1088r,1208r:0)  0@1088r

selectOrSplit GPR64common:%vreg312 [1096r,1224r:0)  0@1096r w=7.613827e-05
assigning %vreg312 to %X9: W9 [1096r,1224r:0)  0@1096r

selectOrSplit GPR64:%vreg315 [1200r,1264r:0)  0@1200r w=8.664010e-05
assigning %vreg315 to %X10: W10 [1200r,1264r:0)  0@1200r

selectOrSplit GPR64common:%vreg334 [1204r,1232r:0)  0@1204r w=1.878552e-04
assigning %vreg334 to %X11: W11 [1204r,1232r:0)  0@1204r

selectOrSplit GPR32:%vreg330 [1208r,1240r:0)  0@1208r w=1.861158e-04
assigning %vreg330 to %W8: W8 [1208r,1240r:0)  0@1208r

selectOrSplit GPR32:%vreg326 [1216r,1248r:0)  0@1216r w=1.861158e-04
assigning %vreg326 to %W12: W12 [1216r,1248r:0)  0@1216r

selectOrSplit GPR64common:%vreg313 [1224r,1272r:0)  0@1224r w=1.794688e-04
assigning %vreg313 to %X9: W9 [1224r,1272r:0)  0@1224r

selectOrSplit GPR32:%vreg333 [1232r,1304r:0)  0@1232r w=1.703432e-04
assigning %vreg333 to %W11: W11 [1232r,1304r:0)  0@1232r

selectOrSplit GPR32:%vreg328 [1240r,1248r:0)  0@1240r w=inf
assigning %vreg328 to %W8: W8 [1240r,1248r:0)  0@1240r

selectOrSplit GPR64:%vreg319 [1248r,1256r:0)  0@1248r w=inf
assigning %vreg319 to %X8: W8 [1248r,1256r:0)  0@1248r

selectOrSplit GPR64:%vreg320 [1256r,1264r:0)  0@1256r w=inf
assigning %vreg320 to %X8: W8 [1256r,1264r:0)  0@1256r

selectOrSplit GPR64:%vreg316 [1264r,1272r:0)  0@1264r w=inf
assigning %vreg316 to %X8: W8 [1264r,1272r:0)  0@1264r

selectOrSplit GPR64common:%vreg317 [1272r,1280r:0)  0@1272r w=inf
assigning %vreg317 to %X8: W8 [1272r,1280r:0)  0@1272r

selectOrSplit GPR32:%vreg311 [1280r,1304r:0)  0@1280r w=1.896274e-04
assigning %vreg311 to %W8: W8 [1280r,1304r:0)  0@1280r

selectOrSplit GPR64common:%vreg306 [1296r,1312r:0)  0@1296r w=1.932741e-04
assigning %vreg306 to %X9: W9 [1296r,1312r:0)  0@1296r

selectOrSplit GPR32:%vreg309 [1304r,1312r:0)  0@1304r w=inf
assigning %vreg309 to %W8: W8 [1304r,1312r:0)  0@1304r

selectOrSplit GPR64common:%vreg303 [1320r,1364r:0)  0@1320r w=1.810856e-04
assigning %vreg303 to %X8: W8 [1320r,1364r:0)  0@1320r

selectOrSplit GPR64common:%vreg296 [1360r,1376r:0)  0@1360r w=1.932741e-04
assigning %vreg296 to %X9: W9 [1360r,1376r:0)  0@1360r

selectOrSplit GPR64:%vreg302 [1364r,1392r:0)  0@1364r w=1.878552e-04
assigning %vreg302 to %X8: W8 [1364r,1392r:0)  0@1364r

selectOrSplit GPR32:%vreg289 [1368r,1408r:0)  0@1368r w=9.136592e-05
assigning %vreg289 to %W10: W10 [1368r,1408r:0)  0@1368r

selectOrSplit GPR64common:%vreg295 [1376r,1392r:0)  0@1376r w=inf
assigning %vreg295 to %X9: W9 [1376r,1392r:0)  0@1376r

selectOrSplit GPR64common:%vreg293 [1392r,1408r:0)  0@1392r w=inf
assigning %vreg293 to %X8: W8 [1392r,1408r:0)  0@1392r

selectOrSplit GPR64common:%vreg287 [1440r,1480r:0)  0@1440r w=1.827318e-04
assigning %vreg287 to %X8: W8 [1440r,1480r:0)  0@1440r

selectOrSplit GPR64common:%vreg281 [1472r,1488r:0)  0@1472r w=1.932741e-04
assigning %vreg281 to %X9: W9 [1472r,1488r:0)  0@1472r

selectOrSplit GPR64:%vreg286 [1480r,1504r:0)  0@1480r w=1.896274e-04
assigning %vreg286 to %X8: W8 [1480r,1504r:0)  0@1480r

selectOrSplit GPR64:%vreg280 [1488r,1504r:0)  0@1488r w=1.932741e-04
assigning %vreg280 to %X9: W9 [1488r,1504r:0)  0@1488r

selectOrSplit GPR32:%vreg288 [1496r,1520r:0)  0@1496r w=1.896274e-04
assigning %vreg288 to %W10: W10 [1496r,1520r:0)  0@1496r

selectOrSplit GPR64common:%vreg278 [1504r,1520r:0)  0@1504r w=inf
assigning %vreg278 to %X8: W8 [1504r,1520r:0)  0@1504r

selectOrSplit GPR64common:%vreg273 [1536r,1584r:0)  0@1536r w=2.692032e-04
assigning %vreg273 to %X8: W8 [1536r,1584r:0)  0@1536r

selectOrSplit GPR32common:%vreg272 [1552r,1568r:0)  0@1552r w=inf
assigning %vreg272 to %W9: W9 [1552r,1568r:0)  0@1552r

selectOrSplit GPR32common:%vreg271 [1568r,1584r:0)  0@1568r w=inf
assigning %vreg271 to %W9: W9 [1568r,1584r:0)  0@1568r

selectOrSplit GPR32:%vreg267 [1600r,1632r:0)  0@1600r w=1.861158e-04
assigning %vreg267 to %W8: W8 [1600r,1632r:0)  0@1600r

selectOrSplit GPR64common:%vreg266 [1616r,1632r:0)  0@1616r w=inf
assigning %vreg266 to %X9: W9 [1616r,1632r:0)  0@1616r

selectOrSplit GPR64common:%vreg239 [1696r,1712r:0)  0@1696r w=5.959283e-04
assigning %vreg239 to %X8: W8 [1696r,1712r:0)  0@1696r

selectOrSplit GPR32:%vreg240 [1704r,1728r:0)  0@1704r w=5.846844e-04
assigning %vreg240 to %W9: W9 [1704r,1728r:0)  0@1704r

selectOrSplit GPR32:%vreg238 [1712r,1728r:0)  0@1712r w=inf
assigning %vreg238 to %W8: W8 [1712r,1728r:0)  0@1712r

selectOrSplit GPR64common:%vreg244 [1776r,1792r:0)  0@1776r w=inf
assigning %vreg244 to %X8: W8 [1776r,1792r:0)  0@1776r

selectOrSplit GPR32common:%vreg243 [1792r,1808r:0)  0@1792r w=inf
assigning %vreg243 to %W8: W8 [1792r,1808r:0)  0@1792r

selectOrSplit GPR64common:%vreg254 [1856r,1872r:0)  0@1856r w=inf
assigning %vreg254 to %X8: W8 [1856r,1872r:0)  0@1856r

selectOrSplit GPR32common:%vreg253 [1872r,1888r:0)  0@1872r w=inf
assigning %vreg253 to %W8: W8 [1872r,1888r:0)  0@1872r

selectOrSplit GPR32:%vreg263 [2096r,2128r:0)  0@2096r w=4.265153e-04
assigning %vreg263 to %W8: W8 [2096r,2128r:0)  0@2096r

selectOrSplit GPR64common:%vreg262 [2112r,2128r:0)  0@2112r w=inf
assigning %vreg262 to %X9: W9 [2112r,2128r:0)  0@2112r

selectOrSplit GPR64common:%vreg259 [2144r,2160r:0)  0@2144r w=4.429197e-04
assigning %vreg259 to %X8: W8 [2144r,2160r:0)  0@2144r

selectOrSplit GPR32:%vreg257 [2152r,2160r:0)  0@2152r w=inf
assigning %vreg257 to %W9: W9 [2152r,2160r:0)  0@2152r

selectOrSplit GPR64common:%vreg250 [2208r,2256r:0)  0@2208r w=2.019024e-04
assigning %vreg250 to %X8: W8 [2208r,2256r:0)  0@2208r

selectOrSplit GPR32common:%vreg249 [2224r,2240r:0)  0@2224r w=inf
assigning %vreg249 to %W9: W9 [2224r,2240r:0)  0@2224r

selectOrSplit GPR32common:%vreg248 [2240r,2256r:0)  0@2240r w=inf
assigning %vreg248 to %W9: W9 [2240r,2256r:0)  0@2240r

selectOrSplit GPR64common:%vreg370 [2320r,2336r:0)  0@2320r w=inf
assigning %vreg370 to %X8: W8 [2320r,2336r:0)  0@2320r

selectOrSplit GPR64common:%vreg369 [2336r,2384r:0)  0@2336r w=1.110463e-03
assigning %vreg369 to %X8: W8 [2336r,2384r:0)  0@2336r

selectOrSplit GPR64common:%vreg367 [2352r,2368r:0)  0@2352r w=inf
assigning %vreg367 to %X9: W9 [2352r,2368r:0)  0@2352r

selectOrSplit GPR64common:%vreg366 [2368r,2384r:0)  0@2368r w=inf
assigning %vreg366 to %X9: W9 [2368r,2384r:0)  0@2368r

selectOrSplit GPR64common:%vreg362 [2400r,2416r:0)  0@2400r w=inf
assigning %vreg362 to %X8: W8 [2400r,2416r:0)  0@2400r

selectOrSplit GPR64common:%vreg361 [2416r,2464r:0)  0@2416r w=1.110463e-03
assigning %vreg361 to %X8: W8 [2416r,2464r:0)  0@2416r

selectOrSplit GPR32common:%vreg359 [2432r,2448r:0)  0@2432r w=inf
assigning %vreg359 to %W9: W9 [2432r,2448r:0)  0@2432r

selectOrSplit GPR32common:%vreg358 [2448r,2464r:0)  0@2448r w=inf
assigning %vreg358 to %W9: W9 [2448r,2464r:0)  0@2448r

selectOrSplit GPR64common:%vreg354 [2480r,2496r:0)  0@2480r w=inf
assigning %vreg354 to %X8: W8 [2480r,2496r:0)  0@2480r

selectOrSplit GPR64common:%vreg353 [2496r,2544r:0)  0@2496r w=1.110463e-03
assigning %vreg353 to %X8: W8 [2496r,2544r:0)  0@2496r

selectOrSplit GPR32common:%vreg351 [2512r,2528r:0)  0@2512r w=inf
assigning %vreg351 to %W9: W9 [2512r,2528r:0)  0@2512r

selectOrSplit GPR32common:%vreg350 [2528r,2544r:0)  0@2528r w=inf
assigning %vreg350 to %W9: W9 [2528r,2544r:0)  0@2528r

selectOrSplit GPR64common:%vreg346 [2560r,2576r:0)  0@2560r w=inf
assigning %vreg346 to %X8: W8 [2560r,2576r:0)  0@2560r

selectOrSplit GPR64common:%vreg345 [2576r,2592r:0)  0@2576r w=inf
assigning %vreg345 to %X8: W8 [2576r,2592r:0)  0@2576r

selectOrSplit GPR32:%vreg343 [2592r,2608r:0)  0@2592r w=inf
assigning %vreg343 to %W8: W8 [2592r,2608r:0)  0@2592r

selectOrSplit GPR64common:%vreg378 [2640r,2656r:0)  0@2640r w=inf
assigning %vreg378 to %X8: W8 [2640r,2656r:0)  0@2640r

selectOrSplit GPR64common:%vreg377 [2656r,2704r:0)  0@2656r w=5.496231e-04
assigning %vreg377 to %X8: W8 [2656r,2704r:0)  0@2656r

selectOrSplit GPR32common:%vreg375 [2672r,2688r:0)  0@2672r w=inf
assigning %vreg375 to %W9: W9 [2672r,2688r:0)  0@2672r

selectOrSplit GPR32common:%vreg374 [2688r,2704r:0)  0@2688r w=inf
assigning %vreg374 to %W9: W9 [2688r,2704r:0)  0@2688r

selectOrSplit GPR64common:%vreg18 [2832r,2872r:0)  0@2832r w=2.596315e-03
assigning %vreg18 to %X8: W8 [2832r,2872r:0)  0@2832r

selectOrSplit GPR64common:%vreg15 [2864r,2880r:0)  0@2864r w=2.746102e-03
assigning %vreg15 to %X9: W9 [2864r,2880r:0)  0@2864r

selectOrSplit GPR32:%vreg17 [2872r,2896r:0)  0@2872r w=2.694289e-03
assigning %vreg17 to %W8: W8 [2872r,2896r:0)  0@2872r

selectOrSplit GPR32:%vreg14 [2880r,2896r:0)  0@2880r w=inf
assigning %vreg14 to %W9: W9 [2880r,2896r:0)  0@2880r

selectOrSplit GPR64common:%vreg24 [2976r,2992r:0)  0@2976r w=inf
assigning %vreg24 to %X8: W8 [2976r,2992r:0)  0@2976r

selectOrSplit GPR64common:%vreg23 [2992r,3008r:0)  0@2992r w=inf
assigning %vreg23 to %X8: W8 [2992r,3008r:0)  0@2992r

selectOrSplit GPR32:%vreg21 [3008r,3024r:0)  0@3008r w=inf
assigning %vreg21 to %W8: W8 [3008r,3024r:0)  0@3008r

selectOrSplit GPR64common:%vreg28 [3088r,3104r:0)  0@3088r w=inf
assigning %vreg28 to %X8: W8 [3088r,3104r:0)  0@3088r

selectOrSplit GPR32:%vreg27 [3104r,3120r:0)  0@3104r w=inf
assigning %vreg27 to %W8: W8 [3104r,3120r:0)  0@3104r

selectOrSplit GPR32:%vreg45 [3184r,3200r:0)  0@3184r w=inf
assigning %vreg45 to %W8: W8 [3184r,3200r:0)  0@3184r

selectOrSplit GPR64common:%vreg44 [3216r,3232r:0)  0@3216r w=inf
assigning %vreg44 to %X8: W8 [3216r,3232r:0)  0@3216r

selectOrSplit GPR64common:%vreg43 [3232r,3248r:0)  0@3232r w=inf
assigning %vreg43 to %X8: W8 [3232r,3248r:0)  0@3232r

selectOrSplit GPR64common:%vreg41 [3248r,3264r:0)  0@3248r w=inf
assigning %vreg41 to %X8: W8 [3248r,3264r:0)  0@3248r

selectOrSplit GPR32:%vreg39 [3264r,3280r:0)  0@3264r w=inf
assigning %vreg39 to %W8: W8 [3264r,3280r:0)  0@3264r

selectOrSplit GPR64common:%vreg33 [3312r,3328r:0)  0@3312r w=3.382296e-04
assigning %vreg33 to %X8: W8 [3312r,3328r:0)  0@3312r

selectOrSplit GPR32:%vreg34 [3320r,3344r:0)  0@3320r w=3.318479e-04
assigning %vreg34 to %W9: W9 [3320r,3344r:0)  0@3320r

selectOrSplit GPR32:%vreg32 [3328r,3344r:0)  0@3328r w=inf
assigning %vreg32 to %W8: W8 [3328r,3344r:0)  0@3328r

selectOrSplit GPR64common:%vreg49 [3392r,3408r:0)  0@3392r w=inf
assigning %vreg49 to %X8: W8 [3392r,3408r:0)  0@3392r

selectOrSplit GPR32common:%vreg48 [3408r,3424r:0)  0@3408r w=inf
assigning %vreg48 to %W8: W8 [3408r,3424r:0)  0@3408r

selectOrSplit GPR64common:%vreg155 [3520r,3536r:0)  0@3520r w=inf
assigning %vreg155 to %X8: W8 [3520r,3536r:0)  0@3520r

selectOrSplit GPR32:%vreg152 [3536r,3568r:0)  0@3536r w=inf
assigning %vreg152 to %W8: W8 [3536r,3568r:0)  0@3536r

selectOrSplit GPR64common:%vreg146 [3616r,3736r:0)  0@3616r w=6.442468e-05
assigning %vreg146 to %X8: W8 [3616r,3736r:0)  0@3616r

selectOrSplit GPR64common:%vreg127 [3624r,3752r:0)  0@3624r w=3.172428e-05
assigning %vreg127 to %X9: W9 [3624r,3752r:0)  0@3624r

selectOrSplit GPR64:%vreg130 [3728r,3792r:0)  0@3728r w=3.610004e-05
assigning %vreg130 to %X10: W10 [3728r,3792r:0)  0@3728r

selectOrSplit GPR64common:%vreg149 [3732r,3760r:0)  0@3732r w=7.827298e-05
assigning %vreg149 to %X11: W11 [3732r,3760r:0)  0@3732r

selectOrSplit GPR32:%vreg145 [3736r,3768r:0)  0@3736r w=7.754823e-05
assigning %vreg145 to %W8: W8 [3736r,3768r:0)  0@3736r

selectOrSplit GPR32:%vreg141 [3744r,3776r:0)  0@3744r w=7.754823e-05
assigning %vreg141 to %W12: W12 [3744r,3776r:0)  0@3744r

selectOrSplit GPR64common:%vreg128 [3752r,3800r:0)  0@3752r w=7.477865e-05
assigning %vreg128 to %X9: W9 [3752r,3800r:0)  0@3752r

selectOrSplit GPR32:%vreg148 [3760r,3832r:0)  0@3760r w=7.097635e-05
assigning %vreg148 to %W11: W11 [3760r,3832r:0)  0@3760r

selectOrSplit GPR32:%vreg143 [3768r,3776r:0)  0@3768r w=inf
assigning %vreg143 to %W8: W8 [3768r,3776r:0)  0@3768r

selectOrSplit GPR64:%vreg134 [3776r,3784r:0)  0@3776r w=inf
assigning %vreg134 to %X8: W8 [3776r,3784r:0)  0@3776r

selectOrSplit GPR64:%vreg135 [3784r,3792r:0)  0@3784r w=inf
assigning %vreg135 to %X8: W8 [3784r,3792r:0)  0@3784r

selectOrSplit GPR64:%vreg131 [3792r,3800r:0)  0@3792r w=inf
assigning %vreg131 to %X8: W8 [3792r,3800r:0)  0@3792r

selectOrSplit GPR64common:%vreg132 [3800r,3808r:0)  0@3800r w=inf
assigning %vreg132 to %X8: W8 [3800r,3808r:0)  0@3800r

selectOrSplit GPR32:%vreg126 [3808r,3832r:0)  0@3808r w=7.901141e-05
assigning %vreg126 to %W8: W8 [3808r,3832r:0)  0@3808r

selectOrSplit GPR64common:%vreg121 [3824r,3840r:0)  0@3824r w=8.053085e-05
assigning %vreg121 to %X9: W9 [3824r,3840r:0)  0@3824r

selectOrSplit GPR32:%vreg124 [3832r,3840r:0)  0@3832r w=inf
assigning %vreg124 to %W8: W8 [3832r,3840r:0)  0@3832r

selectOrSplit GPR64common:%vreg118 [3848r,3892r:0)  0@3848r w=7.545234e-05
assigning %vreg118 to %X8: W8 [3848r,3892r:0)  0@3848r

selectOrSplit GPR64common:%vreg111 [3888r,3904r:0)  0@3888r w=8.053085e-05
assigning %vreg111 to %X9: W9 [3888r,3904r:0)  0@3888r

selectOrSplit GPR64:%vreg117 [3892r,3920r:0)  0@3892r w=7.827298e-05
assigning %vreg117 to %X8: W8 [3892r,3920r:0)  0@3892r

selectOrSplit GPR32:%vreg104 [3896r,3936r:0)  0@3896r w=3.806913e-05
assigning %vreg104 to %W10: W10 [3896r,3936r:0)  0@3896r

selectOrSplit GPR64common:%vreg110 [3904r,3920r:0)  0@3904r w=inf
assigning %vreg110 to %X9: W9 [3904r,3920r:0)  0@3904r

selectOrSplit GPR64common:%vreg108 [3920r,3936r:0)  0@3920r w=inf
assigning %vreg108 to %X8: W8 [3920r,3936r:0)  0@3920r

selectOrSplit GPR64common:%vreg102 [3968r,4008r:0)  0@3968r w=7.613826e-05
assigning %vreg102 to %X8: W8 [3968r,4008r:0)  0@3968r

selectOrSplit GPR64common:%vreg96 [4000r,4016r:0)  0@4000r w=8.053085e-05
assigning %vreg96 to %X9: W9 [4000r,4016r:0)  0@4000r

selectOrSplit GPR64:%vreg101 [4008r,4032r:0)  0@4008r w=7.901141e-05
assigning %vreg101 to %X8: W8 [4008r,4032r:0)  0@4008r

selectOrSplit GPR64:%vreg95 [4016r,4032r:0)  0@4016r w=8.053085e-05
assigning %vreg95 to %X9: W9 [4016r,4032r:0)  0@4016r

selectOrSplit GPR32:%vreg103 [4024r,4048r:0)  0@4024r w=7.901141e-05
assigning %vreg103 to %W10: W10 [4024r,4048r:0)  0@4024r

selectOrSplit GPR64common:%vreg93 [4032r,4048r:0)  0@4032r w=inf
assigning %vreg93 to %X8: W8 [4032r,4048r:0)  0@4032r

selectOrSplit GPR64common:%vreg88 [4064r,4112r:0)  0@4064r w=1.121680e-04
assigning %vreg88 to %X8: W8 [4064r,4112r:0)  0@4064r

selectOrSplit GPR32common:%vreg87 [4080r,4096r:0)  0@4080r w=inf
assigning %vreg87 to %W9: W9 [4080r,4096r:0)  0@4080r

selectOrSplit GPR32common:%vreg86 [4096r,4112r:0)  0@4096r w=inf
assigning %vreg86 to %W9: W9 [4096r,4112r:0)  0@4096r

selectOrSplit GPR32:%vreg82 [4128r,4160r:0)  0@4128r w=7.754823e-05
assigning %vreg82 to %W8: W8 [4128r,4160r:0)  0@4128r

selectOrSplit GPR64common:%vreg81 [4144r,4160r:0)  0@4144r w=inf
assigning %vreg81 to %X9: W9 [4144r,4160r:0)  0@4144r

selectOrSplit GPR64common:%vreg54 [4224r,4240r:0)  0@4224r w=2.496456e-04
assigning %vreg54 to %X8: W8 [4224r,4240r:0)  0@4224r

selectOrSplit GPR32:%vreg55 [4232r,4256r:0)  0@4232r w=2.449354e-04
assigning %vreg55 to %W9: W9 [4232r,4256r:0)  0@4232r

selectOrSplit GPR32:%vreg53 [4240r,4256r:0)  0@4240r w=inf
assigning %vreg53 to %W8: W8 [4240r,4256r:0)  0@4240r

selectOrSplit GPR64common:%vreg59 [4304r,4320r:0)  0@4304r w=inf
assigning %vreg59 to %X8: W8 [4304r,4320r:0)  0@4304r

selectOrSplit GPR32common:%vreg58 [4320r,4336r:0)  0@4320r w=inf
assigning %vreg58 to %W8: W8 [4320r,4336r:0)  0@4320r

selectOrSplit GPR64common:%vreg69 [4384r,4400r:0)  0@4384r w=inf
assigning %vreg69 to %X8: W8 [4384r,4400r:0)  0@4384r

selectOrSplit GPR32common:%vreg68 [4400r,4416r:0)  0@4400r w=inf
assigning %vreg68 to %W8: W8 [4400r,4416r:0)  0@4400r

selectOrSplit GPR32:%vreg78 [4624r,4656r:0)  0@4624r w=1.783609e-04
assigning %vreg78 to %W8: W8 [4624r,4656r:0)  0@4624r

selectOrSplit GPR64common:%vreg77 [4640r,4656r:0)  0@4640r w=inf
assigning %vreg77 to %X9: W9 [4640r,4656r:0)  0@4640r

selectOrSplit GPR64common:%vreg74 [4672r,4688r:0)  0@4672r w=1.852210e-04
assigning %vreg74 to %X8: W8 [4672r,4688r:0)  0@4672r

selectOrSplit GPR32:%vreg72 [4680r,4688r:0)  0@4680r w=inf
assigning %vreg72 to %W9: W9 [4680r,4688r:0)  0@4680r

selectOrSplit GPR64common:%vreg65 [4736r,4784r:0)  0@4736r w=8.973439e-05
assigning %vreg65 to %X8: W8 [4736r,4784r:0)  0@4736r

selectOrSplit GPR32common:%vreg64 [4752r,4768r:0)  0@4752r w=inf
assigning %vreg64 to %W9: W9 [4752r,4768r:0)  0@4752r

selectOrSplit GPR32common:%vreg63 [4768r,4784r:0)  0@4768r w=inf
assigning %vreg63 to %W9: W9 [4768r,4784r:0)  0@4768r

selectOrSplit GPR64common:%vreg185 [4848r,4864r:0)  0@4848r w=inf
assigning %vreg185 to %X8: W8 [4848r,4864r:0)  0@4848r

selectOrSplit GPR64common:%vreg184 [4864r,4912r:0)  0@4864r w=4.711055e-04
assigning %vreg184 to %X8: W8 [4864r,4912r:0)  0@4864r

selectOrSplit GPR64common:%vreg182 [4880r,4896r:0)  0@4880r w=inf
assigning %vreg182 to %X9: W9 [4880r,4896r:0)  0@4880r

selectOrSplit GPR64common:%vreg181 [4896r,4912r:0)  0@4896r w=inf
assigning %vreg181 to %X9: W9 [4896r,4912r:0)  0@4896r

selectOrSplit GPR64common:%vreg177 [4928r,4944r:0)  0@4928r w=inf
assigning %vreg177 to %X8: W8 [4928r,4944r:0)  0@4928r

selectOrSplit GPR64common:%vreg176 [4944r,4992r:0)  0@4944r w=4.711055e-04
assigning %vreg176 to %X8: W8 [4944r,4992r:0)  0@4944r

selectOrSplit GPR32common:%vreg174 [4960r,4976r:0)  0@4960r w=inf
assigning %vreg174 to %W9: W9 [4960r,4976r:0)  0@4960r

selectOrSplit GPR32common:%vreg173 [4976r,4992r:0)  0@4976r w=inf
assigning %vreg173 to %W9: W9 [4976r,4992r:0)  0@4976r

selectOrSplit GPR64common:%vreg169 [5008r,5024r:0)  0@5008r w=inf
assigning %vreg169 to %X8: W8 [5008r,5024r:0)  0@5008r

selectOrSplit GPR64common:%vreg168 [5024r,5072r:0)  0@5024r w=4.711055e-04
assigning %vreg168 to %X8: W8 [5024r,5072r:0)  0@5024r

selectOrSplit GPR32common:%vreg166 [5040r,5056r:0)  0@5040r w=inf
assigning %vreg166 to %W9: W9 [5040r,5056r:0)  0@5040r

selectOrSplit GPR32common:%vreg165 [5056r,5072r:0)  0@5056r w=inf
assigning %vreg165 to %W9: W9 [5056r,5072r:0)  0@5056r

selectOrSplit GPR64common:%vreg161 [5088r,5104r:0)  0@5088r w=inf
assigning %vreg161 to %X8: W8 [5088r,5104r:0)  0@5088r

selectOrSplit GPR64common:%vreg160 [5104r,5120r:0)  0@5104r w=inf
assigning %vreg160 to %X8: W8 [5104r,5120r:0)  0@5104r

selectOrSplit GPR32:%vreg158 [5120r,5136r:0)  0@5120r w=inf
assigning %vreg158 to %W8: W8 [5120r,5136r:0)  0@5120r

selectOrSplit GPR64common:%vreg193 [5168r,5184r:0)  0@5168r w=inf
assigning %vreg193 to %X8: W8 [5168r,5184r:0)  0@5168r

selectOrSplit GPR64common:%vreg192 [5184r,5232r:0)  0@5184r w=2.355528e-04
assigning %vreg192 to %X8: W8 [5184r,5232r:0)  0@5184r

selectOrSplit GPR32common:%vreg190 [5200r,5216r:0)  0@5200r w=inf
assigning %vreg190 to %W9: W9 [5200r,5216r:0)  0@5200r

selectOrSplit GPR32common:%vreg189 [5216r,5232r:0)  0@5216r w=inf
assigning %vreg189 to %W9: W9 [5216r,5232r:0)  0@5216r

selectOrSplit GPR64common:%vreg199 [5264r,5312r:0)  0@5264r w=4.711055e-04
assigning %vreg199 to %X8: W8 [5264r,5312r:0)  0@5264r

selectOrSplit GPR32common:%vreg198 [5280r,5296r:0)  0@5280r w=inf
assigning %vreg198 to %W9: W9 [5280r,5296r:0)  0@5280r

selectOrSplit GPR32common:%vreg197 [5296r,5312r:0)  0@5296r w=inf
assigning %vreg197 to %W9: W9 [5296r,5312r:0)  0@5296r

********** STACK TRANSFORMATION METADATA **********
********** Function: copy_input_until_stop
********** REGISTER MAP **********
[%vreg1 -> %X20] GPR64
[%vreg4 -> %W8] GPR32common
[%vreg5 -> %X8] GPR64common
[%vreg6 -> %X8] GPR64common
[%vreg8 -> %X0] GPR64sp
[%vreg9 -> %X19] GPR64
[%vreg14 -> %W9] GPR32
[%vreg15 -> %X9] GPR64common
[%vreg17 -> %W8] GPR32
[%vreg18 -> %X8] GPR64common
[%vreg21 -> %W8] GPR32
[%vreg23 -> %X8] GPR64common
[%vreg24 -> %X8] GPR64common
[%vreg27 -> %W8] GPR32
[%vreg28 -> %X8] GPR64common
[%vreg32 -> %W8] GPR32
[%vreg33 -> %X8] GPR64common
[%vreg34 -> %W9] GPR32
[%vreg39 -> %W8] GPR32
[%vreg41 -> %X8] GPR64common
[%vreg43 -> %X8] GPR64common
[%vreg44 -> %X8] GPR64common
[%vreg45 -> %W8] GPR32
[%vreg48 -> %W8] GPR32common
[%vreg49 -> %X8] GPR64common
[%vreg53 -> %W8] GPR32
[%vreg54 -> %X8] GPR64common
[%vreg55 -> %W9] GPR32
[%vreg58 -> %W8] GPR32common
[%vreg59 -> %X8] GPR64common
[%vreg63 -> %W9] GPR32common
[%vreg64 -> %W9] GPR32common
[%vreg65 -> %X8] GPR64common
[%vreg68 -> %W8] GPR32common
[%vreg69 -> %X8] GPR64common
[%vreg71 -> %X0] GPR64
[%vreg72 -> %W9] GPR32
[%vreg74 -> %X8] GPR64common
[%vreg77 -> %X9] GPR64common
[%vreg78 -> %W8] GPR32
[%vreg81 -> %X9] GPR64common
[%vreg82 -> %W8] GPR32
[%vreg86 -> %W9] GPR32common
[%vreg87 -> %W9] GPR32common
[%vreg88 -> %X8] GPR64common
[%vreg93 -> %X8] GPR64common
[%vreg95 -> %X9] GPR64
[%vreg96 -> %X9] GPR64common
[%vreg101 -> %X8] GPR64
[%vreg102 -> %X8] GPR64common
[%vreg103 -> %W10] GPR32
[%vreg104 -> %W10] GPR32
[%vreg108 -> %X8] GPR64common
[%vreg110 -> %X9] GPR64common
[%vreg111 -> %X9] GPR64common
[%vreg117 -> %X8] GPR64
[%vreg118 -> %X8] GPR64common
[%vreg121 -> %X9] GPR64common
[%vreg124 -> %W8] GPR32
[%vreg126 -> %W8] GPR32
[%vreg127 -> %X9] GPR64common
[%vreg128 -> %X9] GPR64common
[%vreg130 -> %X10] GPR64
[%vreg131 -> %X8] GPR64
[%vreg132 -> %X8] GPR64common
[%vreg134 -> %X8] GPR64
[%vreg135 -> %X8] GPR64
[%vreg141 -> %W12] GPR32
[%vreg143 -> %W8] GPR32
[%vreg145 -> %W8] GPR32
[%vreg146 -> %X8] GPR64common
[%vreg148 -> %W11] GPR32
[%vreg149 -> %X11] GPR64common
[%vreg152 -> %W8] GPR32
[%vreg155 -> %X8] GPR64common
[%vreg158 -> %W8] GPR32
[%vreg160 -> %X8] GPR64common
[%vreg161 -> %X8] GPR64common
[%vreg165 -> %W9] GPR32common
[%vreg166 -> %W9] GPR32common
[%vreg168 -> %X8] GPR64common
[%vreg169 -> %X8] GPR64common
[%vreg173 -> %W9] GPR32common
[%vreg174 -> %W9] GPR32common
[%vreg176 -> %X8] GPR64common
[%vreg177 -> %X8] GPR64common
[%vreg181 -> %X9] GPR64common
[%vreg182 -> %X9] GPR64common
[%vreg184 -> %X8] GPR64common
[%vreg185 -> %X8] GPR64common
[%vreg189 -> %W9] GPR32common
[%vreg190 -> %W9] GPR32common
[%vreg192 -> %X8] GPR64common
[%vreg193 -> %X8] GPR64common
[%vreg197 -> %W9] GPR32common
[%vreg198 -> %W9] GPR32common
[%vreg199 -> %X8] GPR64common
[%vreg203 -> %W9] GPR32
[%vreg204 -> %X9] GPR64common
[%vreg206 -> %W8] GPR32
[%vreg207 -> %X8] GPR64common
[%vreg210 -> %W8] GPR32
[%vreg212 -> %X8] GPR64common
[%vreg213 -> %X8] GPR64common
[%vreg217 -> %W8] GPR32
[%vreg218 -> %X8] GPR64common
[%vreg219 -> %W9] GPR32
[%vreg224 -> %W8] GPR32
[%vreg226 -> %X8] GPR64common
[%vreg228 -> %X8] GPR64common
[%vreg229 -> %X8] GPR64common
[%vreg230 -> %W8] GPR32
[%vreg233 -> %W8] GPR32common
[%vreg234 -> %X8] GPR64common
[%vreg238 -> %W8] GPR32
[%vreg239 -> %X8] GPR64common
[%vreg240 -> %W9] GPR32
[%vreg243 -> %W8] GPR32common
[%vreg244 -> %X8] GPR64common
[%vreg248 -> %W9] GPR32common
[%vreg249 -> %W9] GPR32common
[%vreg250 -> %X8] GPR64common
[%vreg253 -> %W8] GPR32common
[%vreg254 -> %X8] GPR64common
[%vreg256 -> %X0] GPR64
[%vreg257 -> %W9] GPR32
[%vreg259 -> %X8] GPR64common
[%vreg262 -> %X9] GPR64common
[%vreg263 -> %W8] GPR32
[%vreg266 -> %X9] GPR64common
[%vreg267 -> %W8] GPR32
[%vreg271 -> %W9] GPR32common
[%vreg272 -> %W9] GPR32common
[%vreg273 -> %X8] GPR64common
[%vreg278 -> %X8] GPR64common
[%vreg280 -> %X9] GPR64
[%vreg281 -> %X9] GPR64common
[%vreg286 -> %X8] GPR64
[%vreg287 -> %X8] GPR64common
[%vreg288 -> %W10] GPR32
[%vreg289 -> %W10] GPR32
[%vreg293 -> %X8] GPR64common
[%vreg295 -> %X9] GPR64common
[%vreg296 -> %X9] GPR64common
[%vreg302 -> %X8] GPR64
[%vreg303 -> %X8] GPR64common
[%vreg306 -> %X9] GPR64common
[%vreg309 -> %W8] GPR32
[%vreg311 -> %W8] GPR32
[%vreg312 -> %X9] GPR64common
[%vreg313 -> %X9] GPR64common
[%vreg315 -> %X10] GPR64
[%vreg316 -> %X8] GPR64
[%vreg317 -> %X8] GPR64common
[%vreg319 -> %X8] GPR64
[%vreg320 -> %X8] GPR64
[%vreg326 -> %W12] GPR32
[%vreg328 -> %W8] GPR32
[%vreg330 -> %W8] GPR32
[%vreg331 -> %X8] GPR64common
[%vreg333 -> %W11] GPR32
[%vreg334 -> %X11] GPR64common
[%vreg337 -> %W8] GPR32
[%vreg340 -> %X8] GPR64common
[%vreg343 -> %W8] GPR32
[%vreg345 -> %X8] GPR64common
[%vreg346 -> %X8] GPR64common
[%vreg350 -> %W9] GPR32common
[%vreg351 -> %W9] GPR32common
[%vreg353 -> %X8] GPR64common
[%vreg354 -> %X8] GPR64common
[%vreg358 -> %W9] GPR32common
[%vreg359 -> %W9] GPR32common
[%vreg361 -> %X8] GPR64common
[%vreg362 -> %X8] GPR64common
[%vreg366 -> %X9] GPR64common
[%vreg367 -> %X9] GPR64common
[%vreg369 -> %X8] GPR64common
[%vreg370 -> %X8] GPR64common
[%vreg374 -> %W9] GPR32common
[%vreg375 -> %W9] GPR32common
[%vreg377 -> %X8] GPR64common
[%vreg378 -> %X8] GPR64common
[%vreg380 -> %W20] GPR32
[%vreg381 -> %X0] GPR64


Stackmap 0:
  STACKMAP 0, 0, 0, <fi#3>, 0, 0, <fi#5>, 0, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack3](align=1) LD8[FixedStack5](align=1) LD8[FixedStack1](align=1) LD8[FixedStack0] LD8[FixedStack2](align=4) LD8[FixedStack4](align=4) GPR64:%vreg1

i8* %ch: in stack slot 3 (size: 1)
i8* %ch89: in stack slot 5 (size: 1)
i8* %progress_in: in stack slot 1 (size: 1)
%struct.EState* %s: in register %X20 (vreg 1)
%struct.EState** %s.addr: in stack slot 0 (size: 8)
i32* %zchh: in stack slot 2 (size: 4)
i32* %zchh77: in stack slot 4 (size: 4)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, 0, <fi#3>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack3](align=1) LD8[FixedStack1](align=1) LD8[FixedStack0] LD8[FixedStack2](align=4)

i8* %ch: in stack slot 3 (size: 1)
i8* %progress_in: in stack slot 1 (size: 1)
%struct.EState** %s.addr: in stack slot 0 (size: 8)
i32* %zchh: in stack slot 2 (size: 4)

Duplicate operand locations:


Stackmap 2:
  STACKMAP 2, 0, 0, <fi#5>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack5](align=1) LD8[FixedStack1](align=1) LD8[FixedStack0] LD8[FixedStack4](align=4)

i8* %ch89: in stack slot 5 (size: 1)
i8* %progress_in: in stack slot 1 (size: 1)
%struct.EState** %s.addr: in stack slot 0 (size: 8)
i32* %zchh77: in stack slot 4 (size: 4)

Duplicate operand locations:


Stackmap 3:
  STACKMAP 3, 0, %vreg380, %LR<earlyclobber,imp-def,dead>, ...; GPR32:%vreg380

i8 %136: in register %W20 (vreg 380)

Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, 0, <fi#3>, 0, 0, <fi#5>, 0, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack3](align=1) LD8[FixedStack5](align=1) LD8[FixedStack1](align=1) LD8[FixedStack0] LD8[FixedStack2](align=4) LD8[FixedStack4](align=4) GPR64:%vreg1
  -> Call instruction SlotIndex 176B, searching vregs 0 -> 382 and stack slots 0 -> 6
    + vreg9 is live in register but not in stackmap
      Defining instruction: %vreg9<def> = COPY %LR; GPR64:%vreg9
      Value: generated value, 1 instruction(s)

  STACKMAP 1, 0, 0, <fi#3>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack3](align=1) LD8[FixedStack1](align=1) LD8[FixedStack0] LD8[FixedStack2](align=4)
  -> Call instruction SlotIndex 1984B, searching vregs 0 -> 382 and stack slots 0 -> 6
    + vreg9 is live in register but not in stackmap
      Defining instruction: %vreg9<def> = COPY %LR; GPR64:%vreg9
      Value: generated value, 1 instruction(s)

  STACKMAP 2, 0, 0, <fi#5>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack5](align=1) LD8[FixedStack1](align=1) LD8[FixedStack0] LD8[FixedStack4](align=4)
  -> Call instruction SlotIndex 4512B, searching vregs 0 -> 382 and stack slots 0 -> 6
    + vreg9 is live in register but not in stackmap
      Defining instruction: %vreg9<def> = COPY %LR; GPR64:%vreg9
      Value: generated value, 1 instruction(s)

  STACKMAP 3, 0, %vreg380, %LR<earlyclobber,imp-def,dead>, ...; GPR32:%vreg380
  -> Call instruction SlotIndex 5488B, searching vregs 0 -> 382 and stack slots 0 -> 6

********** REWRITE VIRTUAL REGISTERS **********
********** Function: copy_input_until_stop
********** REGISTER MAP **********
[%vreg1 -> %X20] GPR64
[%vreg4 -> %W8] GPR32common
[%vreg5 -> %X8] GPR64common
[%vreg6 -> %X8] GPR64common
[%vreg8 -> %X0] GPR64sp
[%vreg9 -> %X19] GPR64
[%vreg14 -> %W9] GPR32
[%vreg15 -> %X9] GPR64common
[%vreg17 -> %W8] GPR32
[%vreg18 -> %X8] GPR64common
[%vreg21 -> %W8] GPR32
[%vreg23 -> %X8] GPR64common
[%vreg24 -> %X8] GPR64common
[%vreg27 -> %W8] GPR32
[%vreg28 -> %X8] GPR64common
[%vreg32 -> %W8] GPR32
[%vreg33 -> %X8] GPR64common
[%vreg34 -> %W9] GPR32
[%vreg39 -> %W8] GPR32
[%vreg41 -> %X8] GPR64common
[%vreg43 -> %X8] GPR64common
[%vreg44 -> %X8] GPR64common
[%vreg45 -> %W8] GPR32
[%vreg48 -> %W8] GPR32common
[%vreg49 -> %X8] GPR64common
[%vreg53 -> %W8] GPR32
[%vreg54 -> %X8] GPR64common
[%vreg55 -> %W9] GPR32
[%vreg58 -> %W8] GPR32common
[%vreg59 -> %X8] GPR64common
[%vreg63 -> %W9] GPR32common
[%vreg64 -> %W9] GPR32common
[%vreg65 -> %X8] GPR64common
[%vreg68 -> %W8] GPR32common
[%vreg69 -> %X8] GPR64common
[%vreg71 -> %X0] GPR64
[%vreg72 -> %W9] GPR32
[%vreg74 -> %X8] GPR64common
[%vreg77 -> %X9] GPR64common
[%vreg78 -> %W8] GPR32
[%vreg81 -> %X9] GPR64common
[%vreg82 -> %W8] GPR32
[%vreg86 -> %W9] GPR32common
[%vreg87 -> %W9] GPR32common
[%vreg88 -> %X8] GPR64common
[%vreg93 -> %X8] GPR64common
[%vreg95 -> %X9] GPR64
[%vreg96 -> %X9] GPR64common
[%vreg101 -> %X8] GPR64
[%vreg102 -> %X8] GPR64common
[%vreg103 -> %W10] GPR32
[%vreg104 -> %W10] GPR32
[%vreg108 -> %X8] GPR64common
[%vreg110 -> %X9] GPR64common
[%vreg111 -> %X9] GPR64common
[%vreg117 -> %X8] GPR64
[%vreg118 -> %X8] GPR64common
[%vreg121 -> %X9] GPR64common
[%vreg124 -> %W8] GPR32
[%vreg126 -> %W8] GPR32
[%vreg127 -> %X9] GPR64common
[%vreg128 -> %X9] GPR64common
[%vreg130 -> %X10] GPR64
[%vreg131 -> %X8] GPR64
[%vreg132 -> %X8] GPR64common
[%vreg134 -> %X8] GPR64
[%vreg135 -> %X8] GPR64
[%vreg141 -> %W12] GPR32
[%vreg143 -> %W8] GPR32
[%vreg145 -> %W8] GPR32
[%vreg146 -> %X8] GPR64common
[%vreg148 -> %W11] GPR32
[%vreg149 -> %X11] GPR64common
[%vreg152 -> %W8] GPR32
[%vreg155 -> %X8] GPR64common
[%vreg158 -> %W8] GPR32
[%vreg160 -> %X8] GPR64common
[%vreg161 -> %X8] GPR64common
[%vreg165 -> %W9] GPR32common
[%vreg166 -> %W9] GPR32common
[%vreg168 -> %X8] GPR64common
[%vreg169 -> %X8] GPR64common
[%vreg173 -> %W9] GPR32common
[%vreg174 -> %W9] GPR32common
[%vreg176 -> %X8] GPR64common
[%vreg177 -> %X8] GPR64common
[%vreg181 -> %X9] GPR64common
[%vreg182 -> %X9] GPR64common
[%vreg184 -> %X8] GPR64common
[%vreg185 -> %X8] GPR64common
[%vreg189 -> %W9] GPR32common
[%vreg190 -> %W9] GPR32common
[%vreg192 -> %X8] GPR64common
[%vreg193 -> %X8] GPR64common
[%vreg197 -> %W9] GPR32common
[%vreg198 -> %W9] GPR32common
[%vreg199 -> %X8] GPR64common
[%vreg203 -> %W9] GPR32
[%vreg204 -> %X9] GPR64common
[%vreg206 -> %W8] GPR32
[%vreg207 -> %X8] GPR64common
[%vreg210 -> %W8] GPR32
[%vreg212 -> %X8] GPR64common
[%vreg213 -> %X8] GPR64common
[%vreg217 -> %W8] GPR32
[%vreg218 -> %X8] GPR64common
[%vreg219 -> %W9] GPR32
[%vreg224 -> %W8] GPR32
[%vreg226 -> %X8] GPR64common
[%vreg228 -> %X8] GPR64common
[%vreg229 -> %X8] GPR64common
[%vreg230 -> %W8] GPR32
[%vreg233 -> %W8] GPR32common
[%vreg234 -> %X8] GPR64common
[%vreg238 -> %W8] GPR32
[%vreg239 -> %X8] GPR64common
[%vreg240 -> %W9] GPR32
[%vreg243 -> %W8] GPR32common
[%vreg244 -> %X8] GPR64common
[%vreg248 -> %W9] GPR32common
[%vreg249 -> %W9] GPR32common
[%vreg250 -> %X8] GPR64common
[%vreg253 -> %W8] GPR32common
[%vreg254 -> %X8] GPR64common
[%vreg256 -> %X0] GPR64
[%vreg257 -> %W9] GPR32
[%vreg259 -> %X8] GPR64common
[%vreg262 -> %X9] GPR64common
[%vreg263 -> %W8] GPR32
[%vreg266 -> %X9] GPR64common
[%vreg267 -> %W8] GPR32
[%vreg271 -> %W9] GPR32common
[%vreg272 -> %W9] GPR32common
[%vreg273 -> %X8] GPR64common
[%vreg278 -> %X8] GPR64common
[%vreg280 -> %X9] GPR64
[%vreg281 -> %X9] GPR64common
[%vreg286 -> %X8] GPR64
[%vreg287 -> %X8] GPR64common
[%vreg288 -> %W10] GPR32
[%vreg289 -> %W10] GPR32
[%vreg293 -> %X8] GPR64common
[%vreg295 -> %X9] GPR64common
[%vreg296 -> %X9] GPR64common
[%vreg302 -> %X8] GPR64
[%vreg303 -> %X8] GPR64common
[%vreg306 -> %X9] GPR64common
[%vreg309 -> %W8] GPR32
[%vreg311 -> %W8] GPR32
[%vreg312 -> %X9] GPR64common
[%vreg313 -> %X9] GPR64common
[%vreg315 -> %X10] GPR64
[%vreg316 -> %X8] GPR64
[%vreg317 -> %X8] GPR64common
[%vreg319 -> %X8] GPR64
[%vreg320 -> %X8] GPR64
[%vreg326 -> %W12] GPR32
[%vreg328 -> %W8] GPR32
[%vreg330 -> %W8] GPR32
[%vreg331 -> %X8] GPR64common
[%vreg333 -> %W11] GPR32
[%vreg334 -> %X11] GPR64common
[%vreg337 -> %W8] GPR32
[%vreg340 -> %X8] GPR64common
[%vreg343 -> %W8] GPR32
[%vreg345 -> %X8] GPR64common
[%vreg346 -> %X8] GPR64common
[%vreg350 -> %W9] GPR32common
[%vreg351 -> %W9] GPR32common
[%vreg353 -> %X8] GPR64common
[%vreg354 -> %X8] GPR64common
[%vreg358 -> %W9] GPR32common
[%vreg359 -> %W9] GPR32common
[%vreg361 -> %X8] GPR64common
[%vreg362 -> %X8] GPR64common
[%vreg366 -> %X9] GPR64common
[%vreg367 -> %X9] GPR64common
[%vreg369 -> %X8] GPR64common
[%vreg370 -> %X8] GPR64common
[%vreg374 -> %W9] GPR32common
[%vreg375 -> %W9] GPR32common
[%vreg377 -> %X8] GPR64common
[%vreg378 -> %X8] GPR64common
[%vreg380 -> %W20] GPR32
[%vreg381 -> %X0] GPR64

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %LR %X0
16B		%vreg9<def> = COPY %LR; GPR64:%vreg9
32B		%vreg1<def> = COPY %X0; GPR64:%vreg1
64B		%vreg6<def> = ADRP <ga:@copy_input_until_stop>[TF=1]; GPR64common:%vreg6
80B		%vreg8<def> = ADDXri %vreg6<kill>, <ga:@copy_input_until_stop>[TF=34], 0; GPR64sp:%vreg8 GPR64common:%vreg6
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		%X0<def> = COPY %vreg8<kill>; GPR64sp:%vreg8
160B		%X1<def> = COPY %vreg9; GPR64:%vreg9
176B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
224B		STACKMAP 0, 0, 0, <fi#3>, 0, 0, <fi#5>, 0, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack3](align=1) LD8[FixedStack5](align=1) LD8[FixedStack1](align=1) LD8[FixedStack0] LD8[FixedStack2](align=4) LD8[FixedStack4](align=4) GPR64:%vreg1
240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
256B		STRXui %vreg1<kill>, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg1
272B		STRBBui %WZR, <fi#1>, 0; mem:ST1[FixedStack1]
288B		%vreg5<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg5
304B		%vreg4<def> = LDRWui %vreg5<kill>, 2; mem:LD4[%mode] GPR32common:%vreg4 GPR64common:%vreg5
320B		%WZR<def> = SUBSWri %vreg4<kill>, 2, 0, %NZCV<imp-def>; GPR32common:%vreg4
336B		Bcc 1, <BB#20>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#20 BB#1
> %X19<def> = COPY %LR
> %X20<def> = COPY %X0
> %X8<def> = ADRP <ga:@copy_input_until_stop>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@copy_input_until_stop>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19
> BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 0, 0, 0, <fi#3>, 0, 0, <fi#5>, 0, 0, <fi#1>, 0, %X20, 0, <fi#0>, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack3](align=1) LD8[FixedStack5](align=1) LD8[FixedStack1](align=1) LD8[FixedStack0] LD8[FixedStack2](align=4) LD8[FixedStack4](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRXui %X20<kill>, <fi#0>, 0; mem:ST8[FixedStack0]
> STRBBui %WZR, <fi#1>, 0; mem:ST1[FixedStack1]
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %W8<def> = LDRWui %X8<kill>, 2; mem:LD4[%mode]
> %WZR<def> = SUBSWri %W8<kill>, 2, 0, %NZCV<imp-def>
> Bcc 1, <BB#20>, %NZCV<imp-use,kill>
352B	BB#1: derived from LLVM BB %if.then
	    Live Ins: %X19
	    Predecessors according to CFG: BB#0
368B		B <BB#2>
	    Successors according to CFG: BB#2
> B <BB#2>
384B	BB#2: derived from LLVM BB %while.body
	    Live Ins: %X19
	    Predecessors according to CFG: BB#1 BB#18
400B		%vreg207<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg207
432B		%vreg204<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg204
440B		%vreg206<def> = LDRWui %vreg207<kill>, 27; mem:LD4[%nblock] GPR32:%vreg206 GPR64common:%vreg207
448B		%vreg203<def> = LDRWui %vreg204<kill>, 28; mem:LD4[%nblockMAX] GPR32:%vreg203 GPR64common:%vreg204
464B		%WZR<def> = SUBSWrr %vreg206<kill>, %vreg203<kill>, %NZCV<imp-def>; GPR32:%vreg206,%vreg203
480B		Bcc 11, <BB#4>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#4 BB#3
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %X9<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %W8<def> = LDRWui %X8<kill>, 27; mem:LD4[%nblock]
> %W9<def> = LDRWui %X9<kill>, 28; mem:LD4[%nblockMAX]
> %WZR<def> = SUBSWrr %W8<kill>, %W9<kill>, %NZCV<imp-def>
> Bcc 11, <BB#4>, %NZCV<imp-use,kill>
496B	BB#3: derived from LLVM BB %if.then.2
	    Live Ins: %X19
	    Predecessors according to CFG: BB#2
512B		B <BB#19>
	    Successors according to CFG: BB#19
> B <BB#19>
528B	BB#4: derived from LLVM BB %if.end
	    Live Ins: %X19
	    Predecessors according to CFG: BB#2
544B		%vreg213<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg213
560B		%vreg212<def> = LDRXui %vreg213<kill>, 0; mem:LD8[%strm] GPR64common:%vreg212,%vreg213
576B		%vreg210<def> = LDRWui %vreg212<kill>, 2; mem:LD4[%avail_in] GPR32:%vreg210 GPR64common:%vreg212
592B		CBNZW %vreg210<kill>, <BB#6>; GPR32:%vreg210
	    Successors according to CFG: BB#6 BB#5
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %X8<def> = LDRXui %X8<kill>, 0; mem:LD8[%strm]
> %W8<def> = LDRWui %X8<kill>, 2; mem:LD4[%avail_in]
> CBNZW %W8<kill>, <BB#6>
608B	BB#5: derived from LLVM BB %if.then.4
	    Live Ins: %X19
	    Predecessors according to CFG: BB#4
624B		B <BB#19>
	    Successors according to CFG: BB#19
> B <BB#19>
640B	BB#6: derived from LLVM BB %if.end.5
	    Live Ins: %X19
	    Predecessors according to CFG: BB#4
656B		%vreg230<def> = MOVi32imm 1; GPR32:%vreg230
672B		STRBBui %vreg230<kill>, <fi#1>, 0; mem:ST1[FixedStack1] GPR32:%vreg230
688B		%vreg229<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg229
704B		%vreg228<def> = LDRXui %vreg229<kill>, 0; mem:LD8[%strm6] GPR64common:%vreg228,%vreg229
720B		%vreg226<def> = LDRXui %vreg228<kill>, 0; mem:LD8[%next_in] GPR64common:%vreg226,%vreg228
736B		%vreg224<def> = LDRBBui %vreg226<kill>, 0; mem:LD1[%11] GPR32:%vreg224 GPR64common:%vreg226
752B		STRWui %vreg224<kill>, <fi#2>, 0; mem:ST4[FixedStack2] GPR32:%vreg224
784B		%vreg218<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg218
792B		%vreg219<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg219
800B		%vreg217<def> = LDRWui %vreg218<kill>, 23; mem:LD4[%state_in_ch] GPR32:%vreg217 GPR64common:%vreg218
816B		%WZR<def> = SUBSWrr %vreg219<kill>, %vreg217<kill>, %NZCV<imp-def>; GPR32:%vreg219,%vreg217
832B		Bcc 0, <BB#9>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#9 BB#7
> %W8<def> = MOVi32imm 1
> STRBBui %W8<kill>, <fi#1>, 0; mem:ST1[FixedStack1]
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %X8<def> = LDRXui %X8<kill>, 0; mem:LD8[%strm6]
> %X8<def> = LDRXui %X8<kill>, 0; mem:LD8[%next_in]
> %W8<def> = LDRBBui %X8<kill>, 0; mem:LD1[%11]
> STRWui %W8<kill>, <fi#2>, 0; mem:ST4[FixedStack2]
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %W9<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2]
> %W8<def> = LDRWui %X8<kill>, 23; mem:LD4[%state_in_ch]
> %WZR<def> = SUBSWrr %W9<kill>, %W8<kill>, %NZCV<imp-def>
> Bcc 0, <BB#9>, %NZCV<imp-use,kill>
848B	BB#7: derived from LLVM BB %land.lhs.true
	    Live Ins: %X19
	    Predecessors according to CFG: BB#6
864B		%vreg234<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg234
880B		%vreg233<def> = LDRWui %vreg234<kill>, 24; mem:LD4[%state_in_len] GPR32common:%vreg233 GPR64common:%vreg234
896B		%WZR<def> = SUBSWri %vreg233<kill>, 1, 0, %NZCV<imp-def>; GPR32common:%vreg233
912B		Bcc 1, <BB#9>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#9 BB#8
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %W8<def> = LDRWui %X8<kill>, 24; mem:LD4[%state_in_len]
> %WZR<def> = SUBSWri %W8<kill>, 1, 0, %NZCV<imp-def>
> Bcc 1, <BB#9>, %NZCV<imp-use,kill>
928B	BB#8: derived from LLVM BB %if.then.11
	    Live Ins: %X19
	    Predecessors according to CFG: BB#7
992B		%vreg340<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg340
1008B		%vreg337<def> = LDRWui %vreg340<kill>, 23; mem:LD4[%state_in_ch12] GPR32:%vreg337 GPR64common:%vreg340
1040B		STRBBui %vreg337<kill>, <fi#3>, 0; mem:ST1[FixedStack3] GPR32:%vreg337
1088B		%vreg331<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg331
1096B		%vreg312<def> = ADRP <ga:@BZ2_crc32Table>[TF=1]; GPR64common:%vreg312
1200B		%vreg315<def> = MOVi64imm 4; GPR64:%vreg315
1204B		%vreg334<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg334
1208B		%vreg330<def> = LDRWui %vreg331<kill>, 162; mem:LD4[%blockCRC14] GPR32:%vreg330 GPR64common:%vreg331
1216B		%vreg326<def> = LDRBBui <fi#3>, 0; mem:LD1[FixedStack3] GPR32:%vreg326
1224B		%vreg313<def> = ADDXri %vreg312<kill>, <ga:@BZ2_crc32Table>[TF=34], 0; GPR64common:%vreg313,%vreg312
1232B		%vreg333<def> = LDRWui %vreg334<kill>, 162; mem:LD4[%blockCRC] GPR32:%vreg333 GPR64common:%vreg334
1240B		%vreg328<def> = UBFMWri %vreg330<kill>, 24, 31; GPR32:%vreg328,%vreg330
1248B		%vreg319:sub_32<def,read-undef> = EORWrr %vreg328<kill>, %vreg326<kill>; GPR64:%vreg319 GPR32:%vreg328,%vreg326
1256B		%vreg320<def> = UBFMXri %vreg319<kill>, 0, 31; GPR64:%vreg320,%vreg319
1264B		%vreg316<def> = MADDXrrr %vreg320<kill>, %vreg315<kill>, %XZR; GPR64:%vreg316,%vreg320,%vreg315
1272B		%vreg317<def> = ADDXrr %vreg313<kill>, %vreg316<kill>; GPR64common:%vreg317,%vreg313 GPR64:%vreg316
1280B		%vreg311<def> = LDRWui %vreg317<kill>, 0; mem:LD4[%arrayidx] GPR32:%vreg311 GPR64common:%vreg317
1296B		%vreg306<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg306
1304B		%vreg309<def> = EORWrs %vreg311<kill>, %vreg333<kill>, 8; GPR32:%vreg309,%vreg311,%vreg333
1312B		STRWui %vreg309<kill>, %vreg306<kill>, 162; mem:ST4[%blockCRC17] GPR32:%vreg309 GPR64common:%vreg306
1320B		%vreg303<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg303
1360B		%vreg296<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg296
1364B		%vreg302:sub_32<def,read-undef> = LDRWui %vreg303<kill>, 23; mem:LD4[%state_in_ch18] GPR64:%vreg302 GPR64common:%vreg303
1368B		%vreg289<def> = MOVi32imm 1; GPR32:%vreg289
1376B		%vreg295<def> = ADDXri %vreg296<kill>, 128, 0; GPR64common:%vreg295,%vreg296
1392B		%vreg293<def> = ADDXrr %vreg295<kill>, %vreg302<kill>; GPR64common:%vreg293,%vreg295 GPR64:%vreg302
1408B		STRBBui %vreg289<kill>, %vreg293<kill>, 0; mem:ST1[%arrayidx20] GPR32:%vreg289 GPR64common:%vreg293
1440B		%vreg287<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg287
1472B		%vreg281<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg281
1480B		%vreg286<def> = LDRSWui %vreg287<kill>, 27; mem:LD4[%nblock21] GPR64:%vreg286 GPR64common:%vreg287
1488B		%vreg280<def> = LDRXui %vreg281<kill>, 8; mem:LD8[%block] GPR64:%vreg280 GPR64common:%vreg281
1496B		%vreg288<def> = LDRBBui <fi#3>, 0; mem:LD1[FixedStack3] GPR32:%vreg288
1504B		%vreg278<def> = ADDXrr %vreg280<kill>, %vreg286<kill>; GPR64common:%vreg278 GPR64:%vreg280,%vreg286
1520B		STRBBui %vreg288<kill>, %vreg278<kill>, 0; mem:ST1[%arrayidx23] GPR32:%vreg288 GPR64common:%vreg278
1536B		%vreg273<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg273
1552B		%vreg272<def> = LDRWui %vreg273, 27; mem:LD4[%nblock24] GPR32common:%vreg272 GPR64common:%vreg273
1568B		%vreg271<def> = ADDWri %vreg272<kill>, 1, 0; GPR32common:%vreg271,%vreg272
1584B		STRWui %vreg271<kill>, %vreg273<kill>, 27; mem:ST4[%nblock24] GPR32common:%vreg271 GPR64common:%vreg273
1600B		%vreg267<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg267
1616B		%vreg266<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg266
1632B		STRWui %vreg267<kill>, %vreg266<kill>, 23; mem:ST4[%state_in_ch25] GPR32:%vreg267 GPR64common:%vreg266
1648B		B <BB#16>
	    Successors according to CFG: BB#16
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %W8<def> = LDRWui %X8<kill>, 23; mem:LD4[%state_in_ch12]
> STRBBui %W8<kill>, <fi#3>, 0; mem:ST1[FixedStack3]
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %X9<def> = ADRP <ga:@BZ2_crc32Table>[TF=1]
> %X10<def> = MOVi64imm 4
> %X11<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %W8<def> = LDRWui %X8<kill>, 162; mem:LD4[%blockCRC14]
> %W12<def> = LDRBBui <fi#3>, 0; mem:LD1[FixedStack3]
> %X9<def> = ADDXri %X9<kill>, <ga:@BZ2_crc32Table>[TF=34], 0
> %W11<def> = LDRWui %X11<kill>, 162; mem:LD4[%blockCRC]
> %W8<def> = UBFMWri %W8<kill>, 24, 31
> %W8<def> = EORWrr %W8<kill>, %W12<kill>, %X8<imp-def>
> %X8<def> = UBFMXri %X8<kill>, 0, 31
> %X8<def> = MADDXrrr %X8<kill>, %X10<kill>, %XZR
> %X8<def> = ADDXrr %X9<kill>, %X8<kill>
> %W8<def> = LDRWui %X8<kill>, 0; mem:LD4[%arrayidx]
> %X9<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %W8<def> = EORWrs %W8<kill>, %W11<kill>, 8
> STRWui %W8<kill>, %X9<kill>, 162; mem:ST4[%blockCRC17]
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %X9<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %W8<def> = LDRWui %X8<kill>, 23, %X8<imp-def>; mem:LD4[%state_in_ch18]
> %W10<def> = MOVi32imm 1
> %X9<def> = ADDXri %X9<kill>, 128, 0
> %X8<def> = ADDXrr %X9<kill>, %X8<kill>
> STRBBui %W10<kill>, %X8<kill>, 0; mem:ST1[%arrayidx20]
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %X9<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %X8<def> = LDRSWui %X8<kill>, 27; mem:LD4[%nblock21]
> %X9<def> = LDRXui %X9<kill>, 8; mem:LD8[%block]
> %W10<def> = LDRBBui <fi#3>, 0; mem:LD1[FixedStack3]
> %X8<def> = ADDXrr %X9<kill>, %X8<kill>
> STRBBui %W10<kill>, %X8<kill>, 0; mem:ST1[%arrayidx23]
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %W9<def> = LDRWui %X8, 27; mem:LD4[%nblock24]
> %W9<def> = ADDWri %W9<kill>, 1, 0
> STRWui %W9<kill>, %X8<kill>, 27; mem:ST4[%nblock24]
> %W8<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2]
> %X9<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> STRWui %W8<kill>, %X9<kill>, 23; mem:ST4[%state_in_ch25]
> B <BB#16>
1664B	BB#9: derived from LLVM BB %if.else
	    Live Ins: %X19
	    Predecessors according to CFG: BB#6 BB#7
1696B		%vreg239<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg239
1704B		%vreg240<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg240
1712B		%vreg238<def> = LDRWui %vreg239<kill>, 23; mem:LD4[%state_in_ch26] GPR32:%vreg238 GPR64common:%vreg239
1728B		%WZR<def> = SUBSWrr %vreg240<kill>, %vreg238<kill>, %NZCV<imp-def>; GPR32:%vreg240,%vreg238
1744B		Bcc 1, <BB#11>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#11 BB#10
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %W9<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2]
> %W8<def> = LDRWui %X8<kill>, 23; mem:LD4[%state_in_ch26]
> %WZR<def> = SUBSWrr %W9<kill>, %W8<kill>, %NZCV<imp-def>
> Bcc 1, <BB#11>, %NZCV<imp-use,kill>
1760B	BB#10: derived from LLVM BB %lor.lhs.false
	    Live Ins: %X19
	    Predecessors according to CFG: BB#9
1776B		%vreg244<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg244
1792B		%vreg243<def> = LDRWui %vreg244<kill>, 24; mem:LD4[%state_in_len29] GPR32common:%vreg243 GPR64common:%vreg244
1808B		%WZR<def> = SUBSWri %vreg243<kill>, 255, 0, %NZCV<imp-def>; GPR32common:%vreg243
1824B		Bcc 1, <BB#14>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#14 BB#11
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %W8<def> = LDRWui %X8<kill>, 24; mem:LD4[%state_in_len29]
> %WZR<def> = SUBSWri %W8<kill>, 255, 0, %NZCV<imp-def>
> Bcc 1, <BB#14>, %NZCV<imp-use,kill>
1840B	BB#11: derived from LLVM BB %if.then.32
	    Live Ins: %X19
	    Predecessors according to CFG: BB#9 BB#10
1856B		%vreg254<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg254
1872B		%vreg253<def> = LDRWui %vreg254<kill>, 23; mem:LD4[%state_in_ch33] GPR32common:%vreg253 GPR64common:%vreg254
1888B		%WZR<def> = SUBSWri %vreg253<kill>, 256, 0, %NZCV<imp-def>; GPR32common:%vreg253
1904B		Bcc 2, <BB#13>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#13 BB#12
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %W8<def> = LDRWui %X8<kill>, 23; mem:LD4[%state_in_ch33]
> %WZR<def> = SUBSWri %W8<kill>, 256, 0, %NZCV<imp-def>
> Bcc 2, <BB#13>, %NZCV<imp-use,kill>
1920B	BB#12: derived from LLVM BB %if.then.36
	    Live Ins: %X19
	    Predecessors according to CFG: BB#11
1936B		%vreg256<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg256
1952B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
1968B		%X0<def> = COPY %vreg256<kill>; GPR64:%vreg256
1984B		BL <ga:@add_pair_to_block>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>
2000B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2016B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
2032B		STACKMAP 1, 0, 0, <fi#3>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack3](align=1) LD8[FixedStack1](align=1) LD8[FixedStack0] LD8[FixedStack2](align=4)
2048B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#13
> %X0<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BL <ga:@add_pair_to_block>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 1, 0, 0, <fi#3>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack3](align=1) LD8[FixedStack1](align=1) LD8[FixedStack0] LD8[FixedStack2](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
2064B	BB#13: derived from LLVM BB %if.end.37
	    Live Ins: %X19
	    Predecessors according to CFG: BB#11 BB#12
2096B		%vreg263<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2] GPR32:%vreg263
2112B		%vreg262<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg262
2128B		STRWui %vreg263<kill>, %vreg262<kill>, 23; mem:ST4[%state_in_ch38] GPR32:%vreg263 GPR64common:%vreg262
2144B		%vreg259<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg259
2152B		%vreg257<def> = MOVi32imm 1; GPR32:%vreg257
2160B		STRWui %vreg257<kill>, %vreg259<kill>, 24; mem:ST4[%state_in_len39] GPR32:%vreg257 GPR64common:%vreg259
2176B		B <BB#15>
	    Successors according to CFG: BB#15
> %W8<def> = LDRWui <fi#2>, 0; mem:LD4[FixedStack2]
> %X9<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> STRWui %W8<kill>, %X9<kill>, 23; mem:ST4[%state_in_ch38]
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %W9<def> = MOVi32imm 1
> STRWui %W9<kill>, %X8<kill>, 24; mem:ST4[%state_in_len39]
> B <BB#15>
2192B	BB#14: derived from LLVM BB %if.else.40
	    Live Ins: %X19
	    Predecessors according to CFG: BB#10
2208B		%vreg250<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg250
2224B		%vreg249<def> = LDRWui %vreg250, 24; mem:LD4[%state_in_len41] GPR32common:%vreg249 GPR64common:%vreg250
2240B		%vreg248<def> = ADDWri %vreg249<kill>, 1, 0; GPR32common:%vreg248,%vreg249
2256B		STRWui %vreg248<kill>, %vreg250<kill>, 24; mem:ST4[%state_in_len41] GPR32common:%vreg248 GPR64common:%vreg250
	    Successors according to CFG: BB#15
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %W9<def> = LDRWui %X8, 24; mem:LD4[%state_in_len41]
> %W9<def> = ADDWri %W9<kill>, 1, 0
> STRWui %W9<kill>, %X8<kill>, 24; mem:ST4[%state_in_len41]
2272B	BB#15: derived from LLVM BB %if.end.43
	    Live Ins: %X19
	    Predecessors according to CFG: BB#14 BB#13
2288B		B <BB#16>
	    Successors according to CFG: BB#16
> B <BB#16>
2304B	BB#16: derived from LLVM BB %if.end.44
	    Live Ins: %X19
	    Predecessors according to CFG: BB#15 BB#8
2320B		%vreg370<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg370
2336B		%vreg369<def> = LDRXui %vreg370<kill>, 0; mem:LD8[%strm45] GPR64common:%vreg369,%vreg370
2352B		%vreg367<def> = LDRXui %vreg369, 0; mem:LD8[%next_in46] GPR64common:%vreg367,%vreg369
2368B		%vreg366<def> = ADDXri %vreg367<kill>, 1, 0; GPR64common:%vreg366,%vreg367
2384B		STRXui %vreg366<kill>, %vreg369<kill>, 0; mem:ST8[%next_in46] GPR64common:%vreg366,%vreg369
2400B		%vreg362<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg362
2416B		%vreg361<def> = LDRXui %vreg362<kill>, 0; mem:LD8[%strm47] GPR64common:%vreg361,%vreg362
2432B		%vreg359<def> = LDRWui %vreg361, 2; mem:LD4[%avail_in48] GPR32common:%vreg359 GPR64common:%vreg361
2448B		%vreg358<def> = SUBWri %vreg359<kill>, 1, 0; GPR32common:%vreg358,%vreg359
2464B		STRWui %vreg358<kill>, %vreg361<kill>, 2; mem:ST4[%avail_in48] GPR32common:%vreg358 GPR64common:%vreg361
2480B		%vreg354<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg354
2496B		%vreg353<def> = LDRXui %vreg354<kill>, 0; mem:LD8[%strm49] GPR64common:%vreg353,%vreg354
2512B		%vreg351<def> = LDRWui %vreg353, 3; mem:LD4[%total_in_lo32] GPR32common:%vreg351 GPR64common:%vreg353
2528B		%vreg350<def> = ADDWri %vreg351<kill>, 1, 0; GPR32common:%vreg350,%vreg351
2544B		STRWui %vreg350<kill>, %vreg353<kill>, 3; mem:ST4[%total_in_lo32] GPR32common:%vreg350 GPR64common:%vreg353
2560B		%vreg346<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg346
2576B		%vreg345<def> = LDRXui %vreg346<kill>, 0; mem:LD8[%strm51] GPR64common:%vreg345,%vreg346
2592B		%vreg343<def> = LDRWui %vreg345<kill>, 3; mem:LD4[%total_in_lo3252] GPR32:%vreg343 GPR64common:%vreg345
2608B		CBNZW %vreg343<kill>, <BB#18>; GPR32:%vreg343
	    Successors according to CFG: BB#18 BB#17
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %X8<def> = LDRXui %X8<kill>, 0; mem:LD8[%strm45]
> %X9<def> = LDRXui %X8, 0; mem:LD8[%next_in46]
> %X9<def> = ADDXri %X9<kill>, 1, 0
> STRXui %X9<kill>, %X8<kill>, 0; mem:ST8[%next_in46]
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %X8<def> = LDRXui %X8<kill>, 0; mem:LD8[%strm47]
> %W9<def> = LDRWui %X8, 2; mem:LD4[%avail_in48]
> %W9<def> = SUBWri %W9<kill>, 1, 0
> STRWui %W9<kill>, %X8<kill>, 2; mem:ST4[%avail_in48]
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %X8<def> = LDRXui %X8<kill>, 0; mem:LD8[%strm49]
> %W9<def> = LDRWui %X8, 3; mem:LD4[%total_in_lo32]
> %W9<def> = ADDWri %W9<kill>, 1, 0
> STRWui %W9<kill>, %X8<kill>, 3; mem:ST4[%total_in_lo32]
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %X8<def> = LDRXui %X8<kill>, 0; mem:LD8[%strm51]
> %W8<def> = LDRWui %X8<kill>, 3; mem:LD4[%total_in_lo3252]
> CBNZW %W8<kill>, <BB#18>
2624B	BB#17: derived from LLVM BB %if.then.55
	    Live Ins: %X19
	    Predecessors according to CFG: BB#16
2640B		%vreg378<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg378
2656B		%vreg377<def> = LDRXui %vreg378<kill>, 0; mem:LD8[%strm56] GPR64common:%vreg377,%vreg378
2672B		%vreg375<def> = LDRWui %vreg377, 4; mem:LD4[%total_in_hi32] GPR32common:%vreg375 GPR64common:%vreg377
2688B		%vreg374<def> = ADDWri %vreg375<kill>, 1, 0; GPR32common:%vreg374,%vreg375
2704B		STRWui %vreg374<kill>, %vreg377<kill>, 4; mem:ST4[%total_in_hi32] GPR32common:%vreg374 GPR64common:%vreg377
	    Successors according to CFG: BB#18
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %X8<def> = LDRXui %X8<kill>, 0; mem:LD8[%strm56]
> %W9<def> = LDRWui %X8, 4; mem:LD4[%total_in_hi32]
> %W9<def> = ADDWri %W9<kill>, 1, 0
> STRWui %W9<kill>, %X8<kill>, 4; mem:ST4[%total_in_hi32]
2720B	BB#18: derived from LLVM BB %if.end.58
	    Live Ins: %X19
	    Predecessors according to CFG: BB#16 BB#17
2736B		B <BB#2>
	    Successors according to CFG: BB#2
> B <BB#2>
2752B	BB#19: derived from LLVM BB %while.end
	    Live Ins: %X19
	    Predecessors according to CFG: BB#5 BB#3
2768B		B <BB#41>
	    Successors according to CFG: BB#41
> B <BB#41>
2784B	BB#20: derived from LLVM BB %if.else.59
	    Live Ins: %X19
	    Predecessors according to CFG: BB#0
2800B		B <BB#21>
	    Successors according to CFG: BB#21
> B <BB#21>
2816B	BB#21: derived from LLVM BB %while.body.60
	    Live Ins: %X19
	    Predecessors according to CFG: BB#20 BB#39
2832B		%vreg18<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg18
2864B		%vreg15<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg15
2872B		%vreg17<def> = LDRWui %vreg18<kill>, 27; mem:LD4[%nblock61] GPR32:%vreg17 GPR64common:%vreg18
2880B		%vreg14<def> = LDRWui %vreg15<kill>, 28; mem:LD4[%nblockMAX62] GPR32:%vreg14 GPR64common:%vreg15
2896B		%WZR<def> = SUBSWrr %vreg17<kill>, %vreg14<kill>, %NZCV<imp-def>; GPR32:%vreg17,%vreg14
2912B		Bcc 11, <BB#23>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#23 BB#22
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %X9<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %W8<def> = LDRWui %X8<kill>, 27; mem:LD4[%nblock61]
> %W9<def> = LDRWui %X9<kill>, 28; mem:LD4[%nblockMAX62]
> %WZR<def> = SUBSWrr %W8<kill>, %W9<kill>, %NZCV<imp-def>
> Bcc 11, <BB#23>, %NZCV<imp-use,kill>
2928B	BB#22: derived from LLVM BB %if.then.65
	    Live Ins: %X19
	    Predecessors according to CFG: BB#21
2944B		B <BB#40>
	    Successors according to CFG: BB#40
> B <BB#40>
2960B	BB#23: derived from LLVM BB %if.end.66
	    Live Ins: %X19
	    Predecessors according to CFG: BB#21
2976B		%vreg24<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg24
2992B		%vreg23<def> = LDRXui %vreg24<kill>, 0; mem:LD8[%strm67] GPR64common:%vreg23,%vreg24
3008B		%vreg21<def> = LDRWui %vreg23<kill>, 2; mem:LD4[%avail_in68] GPR32:%vreg21 GPR64common:%vreg23
3024B		CBNZW %vreg21<kill>, <BB#25>; GPR32:%vreg21
	    Successors according to CFG: BB#25 BB#24
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %X8<def> = LDRXui %X8<kill>, 0; mem:LD8[%strm67]
> %W8<def> = LDRWui %X8<kill>, 2; mem:LD4[%avail_in68]
> CBNZW %W8<kill>, <BB#25>
3040B	BB#24: derived from LLVM BB %if.then.71
	    Live Ins: %X19
	    Predecessors according to CFG: BB#23
3056B		B <BB#40>
	    Successors according to CFG: BB#40
> B <BB#40>
3072B	BB#25: derived from LLVM BB %if.end.72
	    Live Ins: %X19
	    Predecessors according to CFG: BB#23
3088B		%vreg28<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg28
3104B		%vreg27<def> = LDRWui %vreg28<kill>, 4; mem:LD4[%avail_in_expect] GPR32:%vreg27 GPR64common:%vreg28
3120B		CBNZW %vreg27<kill>, <BB#27>; GPR32:%vreg27
	    Successors according to CFG: BB#27 BB#26
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %W8<def> = LDRWui %X8<kill>, 4; mem:LD4[%avail_in_expect]
> CBNZW %W8<kill>, <BB#27>
3136B	BB#26: derived from LLVM BB %if.then.75
	    Live Ins: %X19
	    Predecessors according to CFG: BB#25
3152B		B <BB#40>
	    Successors according to CFG: BB#40
> B <BB#40>
3168B	BB#27: derived from LLVM BB %if.end.76
	    Live Ins: %X19
	    Predecessors according to CFG: BB#25
3184B		%vreg45<def> = MOVi32imm 1; GPR32:%vreg45
3200B		STRBBui %vreg45<kill>, <fi#1>, 0; mem:ST1[FixedStack1] GPR32:%vreg45
3216B		%vreg44<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg44
3232B		%vreg43<def> = LDRXui %vreg44<kill>, 0; mem:LD8[%strm78] GPR64common:%vreg43,%vreg44
3248B		%vreg41<def> = LDRXui %vreg43<kill>, 0; mem:LD8[%next_in79] GPR64common:%vreg41,%vreg43
3264B		%vreg39<def> = LDRBBui %vreg41<kill>, 0; mem:LD1[%78] GPR32:%vreg39 GPR64common:%vreg41
3280B		STRWui %vreg39<kill>, <fi#4>, 0; mem:ST4[FixedStack4] GPR32:%vreg39
3312B		%vreg33<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg33
3320B		%vreg34<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg34
3328B		%vreg32<def> = LDRWui %vreg33<kill>, 23; mem:LD4[%state_in_ch81] GPR32:%vreg32 GPR64common:%vreg33
3344B		%WZR<def> = SUBSWrr %vreg34<kill>, %vreg32<kill>, %NZCV<imp-def>; GPR32:%vreg34,%vreg32
3360B		Bcc 0, <BB#30>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#30 BB#28
> %W8<def> = MOVi32imm 1
> STRBBui %W8<kill>, <fi#1>, 0; mem:ST1[FixedStack1]
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %X8<def> = LDRXui %X8<kill>, 0; mem:LD8[%strm78]
> %X8<def> = LDRXui %X8<kill>, 0; mem:LD8[%next_in79]
> %W8<def> = LDRBBui %X8<kill>, 0; mem:LD1[%78]
> STRWui %W8<kill>, <fi#4>, 0; mem:ST4[FixedStack4]
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %W9<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4]
> %W8<def> = LDRWui %X8<kill>, 23; mem:LD4[%state_in_ch81]
> %WZR<def> = SUBSWrr %W9<kill>, %W8<kill>, %NZCV<imp-def>
> Bcc 0, <BB#30>, %NZCV<imp-use,kill>
3376B	BB#28: derived from LLVM BB %land.lhs.true.84
	    Live Ins: %X19
	    Predecessors according to CFG: BB#27
3392B		%vreg49<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg49
3408B		%vreg48<def> = LDRWui %vreg49<kill>, 24; mem:LD4[%state_in_len85] GPR32common:%vreg48 GPR64common:%vreg49
3424B		%WZR<def> = SUBSWri %vreg48<kill>, 1, 0, %NZCV<imp-def>; GPR32common:%vreg48
3440B		Bcc 1, <BB#30>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#30 BB#29
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %W8<def> = LDRWui %X8<kill>, 24; mem:LD4[%state_in_len85]
> %WZR<def> = SUBSWri %W8<kill>, 1, 0, %NZCV<imp-def>
> Bcc 1, <BB#30>, %NZCV<imp-use,kill>
3456B	BB#29: derived from LLVM BB %if.then.88
	    Live Ins: %X19
	    Predecessors according to CFG: BB#28
3520B		%vreg155<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg155
3536B		%vreg152<def> = LDRWui %vreg155<kill>, 23; mem:LD4[%state_in_ch90] GPR32:%vreg152 GPR64common:%vreg155
3568B		STRBBui %vreg152<kill>, <fi#5>, 0; mem:ST1[FixedStack5] GPR32:%vreg152
3616B		%vreg146<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg146
3624B		%vreg127<def> = ADRP <ga:@BZ2_crc32Table>[TF=1]; GPR64common:%vreg127
3728B		%vreg130<def> = MOVi64imm 4; GPR64:%vreg130
3732B		%vreg149<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg149
3736B		%vreg145<def> = LDRWui %vreg146<kill>, 162; mem:LD4[%blockCRC94] GPR32:%vreg145 GPR64common:%vreg146
3744B		%vreg141<def> = LDRBBui <fi#5>, 0; mem:LD1[FixedStack5] GPR32:%vreg141
3752B		%vreg128<def> = ADDXri %vreg127<kill>, <ga:@BZ2_crc32Table>[TF=34], 0; GPR64common:%vreg128,%vreg127
3760B		%vreg148<def> = LDRWui %vreg149<kill>, 162; mem:LD4[%blockCRC92] GPR32:%vreg148 GPR64common:%vreg149
3768B		%vreg143<def> = UBFMWri %vreg145<kill>, 24, 31; GPR32:%vreg143,%vreg145
3776B		%vreg134:sub_32<def,read-undef> = EORWrr %vreg143<kill>, %vreg141<kill>; GPR64:%vreg134 GPR32:%vreg143,%vreg141
3784B		%vreg135<def> = UBFMXri %vreg134<kill>, 0, 31; GPR64:%vreg135,%vreg134
3792B		%vreg131<def> = MADDXrrr %vreg135<kill>, %vreg130<kill>, %XZR; GPR64:%vreg131,%vreg135,%vreg130
3800B		%vreg132<def> = ADDXrr %vreg128<kill>, %vreg131<kill>; GPR64common:%vreg132,%vreg128 GPR64:%vreg131
3808B		%vreg126<def> = LDRWui %vreg132<kill>, 0; mem:LD4[%arrayidx99] GPR32:%vreg126 GPR64common:%vreg132
3824B		%vreg121<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg121
3832B		%vreg124<def> = EORWrs %vreg126<kill>, %vreg148<kill>, 8; GPR32:%vreg124,%vreg126,%vreg148
3840B		STRWui %vreg124<kill>, %vreg121<kill>, 162; mem:ST4[%blockCRC101] GPR32:%vreg124 GPR64common:%vreg121
3848B		%vreg118<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg118
3888B		%vreg111<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg111
3892B		%vreg117:sub_32<def,read-undef> = LDRWui %vreg118<kill>, 23; mem:LD4[%state_in_ch102] GPR64:%vreg117 GPR64common:%vreg118
3896B		%vreg104<def> = MOVi32imm 1; GPR32:%vreg104
3904B		%vreg110<def> = ADDXri %vreg111<kill>, 128, 0; GPR64common:%vreg110,%vreg111
3920B		%vreg108<def> = ADDXrr %vreg110<kill>, %vreg117<kill>; GPR64common:%vreg108,%vreg110 GPR64:%vreg117
3936B		STRBBui %vreg104<kill>, %vreg108<kill>, 0; mem:ST1[%arrayidx105] GPR32:%vreg104 GPR64common:%vreg108
3968B		%vreg102<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg102
4000B		%vreg96<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg96
4008B		%vreg101<def> = LDRSWui %vreg102<kill>, 27; mem:LD4[%nblock106] GPR64:%vreg101 GPR64common:%vreg102
4016B		%vreg95<def> = LDRXui %vreg96<kill>, 8; mem:LD8[%block108] GPR64:%vreg95 GPR64common:%vreg96
4024B		%vreg103<def> = LDRBBui <fi#5>, 0; mem:LD1[FixedStack5] GPR32:%vreg103
4032B		%vreg93<def> = ADDXrr %vreg95<kill>, %vreg101<kill>; GPR64common:%vreg93 GPR64:%vreg95,%vreg101
4048B		STRBBui %vreg103<kill>, %vreg93<kill>, 0; mem:ST1[%arrayidx109] GPR32:%vreg103 GPR64common:%vreg93
4064B		%vreg88<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg88
4080B		%vreg87<def> = LDRWui %vreg88, 27; mem:LD4[%nblock110] GPR32common:%vreg87 GPR64common:%vreg88
4096B		%vreg86<def> = ADDWri %vreg87<kill>, 1, 0; GPR32common:%vreg86,%vreg87
4112B		STRWui %vreg86<kill>, %vreg88<kill>, 27; mem:ST4[%nblock110] GPR32common:%vreg86 GPR64common:%vreg88
4128B		%vreg82<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg82
4144B		%vreg81<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg81
4160B		STRWui %vreg82<kill>, %vreg81<kill>, 23; mem:ST4[%state_in_ch112] GPR32:%vreg82 GPR64common:%vreg81
4176B		B <BB#37>
	    Successors according to CFG: BB#37
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %W8<def> = LDRWui %X8<kill>, 23; mem:LD4[%state_in_ch90]
> STRBBui %W8<kill>, <fi#5>, 0; mem:ST1[FixedStack5]
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %X9<def> = ADRP <ga:@BZ2_crc32Table>[TF=1]
> %X10<def> = MOVi64imm 4
> %X11<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %W8<def> = LDRWui %X8<kill>, 162; mem:LD4[%blockCRC94]
> %W12<def> = LDRBBui <fi#5>, 0; mem:LD1[FixedStack5]
> %X9<def> = ADDXri %X9<kill>, <ga:@BZ2_crc32Table>[TF=34], 0
> %W11<def> = LDRWui %X11<kill>, 162; mem:LD4[%blockCRC92]
> %W8<def> = UBFMWri %W8<kill>, 24, 31
> %W8<def> = EORWrr %W8<kill>, %W12<kill>, %X8<imp-def>
> %X8<def> = UBFMXri %X8<kill>, 0, 31
> %X8<def> = MADDXrrr %X8<kill>, %X10<kill>, %XZR
> %X8<def> = ADDXrr %X9<kill>, %X8<kill>
> %W8<def> = LDRWui %X8<kill>, 0; mem:LD4[%arrayidx99]
> %X9<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %W8<def> = EORWrs %W8<kill>, %W11<kill>, 8
> STRWui %W8<kill>, %X9<kill>, 162; mem:ST4[%blockCRC101]
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %X9<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %W8<def> = LDRWui %X8<kill>, 23, %X8<imp-def>; mem:LD4[%state_in_ch102]
> %W10<def> = MOVi32imm 1
> %X9<def> = ADDXri %X9<kill>, 128, 0
> %X8<def> = ADDXrr %X9<kill>, %X8<kill>
> STRBBui %W10<kill>, %X8<kill>, 0; mem:ST1[%arrayidx105]
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %X9<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %X8<def> = LDRSWui %X8<kill>, 27; mem:LD4[%nblock106]
> %X9<def> = LDRXui %X9<kill>, 8; mem:LD8[%block108]
> %W10<def> = LDRBBui <fi#5>, 0; mem:LD1[FixedStack5]
> %X8<def> = ADDXrr %X9<kill>, %X8<kill>
> STRBBui %W10<kill>, %X8<kill>, 0; mem:ST1[%arrayidx109]
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %W9<def> = LDRWui %X8, 27; mem:LD4[%nblock110]
> %W9<def> = ADDWri %W9<kill>, 1, 0
> STRWui %W9<kill>, %X8<kill>, 27; mem:ST4[%nblock110]
> %W8<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4]
> %X9<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> STRWui %W8<kill>, %X9<kill>, 23; mem:ST4[%state_in_ch112]
> B <BB#37>
4192B	BB#30: derived from LLVM BB %if.else.113
	    Live Ins: %X19
	    Predecessors according to CFG: BB#27 BB#28
4224B		%vreg54<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg54
4232B		%vreg55<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg55
4240B		%vreg53<def> = LDRWui %vreg54<kill>, 23; mem:LD4[%state_in_ch114] GPR32:%vreg53 GPR64common:%vreg54
4256B		%WZR<def> = SUBSWrr %vreg55<kill>, %vreg53<kill>, %NZCV<imp-def>; GPR32:%vreg55,%vreg53
4272B		Bcc 1, <BB#32>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#32 BB#31
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %W9<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4]
> %W8<def> = LDRWui %X8<kill>, 23; mem:LD4[%state_in_ch114]
> %WZR<def> = SUBSWrr %W9<kill>, %W8<kill>, %NZCV<imp-def>
> Bcc 1, <BB#32>, %NZCV<imp-use,kill>
4288B	BB#31: derived from LLVM BB %lor.lhs.false.117
	    Live Ins: %X19
	    Predecessors according to CFG: BB#30
4304B		%vreg59<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg59
4320B		%vreg58<def> = LDRWui %vreg59<kill>, 24; mem:LD4[%state_in_len118] GPR32common:%vreg58 GPR64common:%vreg59
4336B		%WZR<def> = SUBSWri %vreg58<kill>, 255, 0, %NZCV<imp-def>; GPR32common:%vreg58
4352B		Bcc 1, <BB#35>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#35 BB#32
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %W8<def> = LDRWui %X8<kill>, 24; mem:LD4[%state_in_len118]
> %WZR<def> = SUBSWri %W8<kill>, 255, 0, %NZCV<imp-def>
> Bcc 1, <BB#35>, %NZCV<imp-use,kill>
4368B	BB#32: derived from LLVM BB %if.then.121
	    Live Ins: %X19
	    Predecessors according to CFG: BB#30 BB#31
4384B		%vreg69<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg69
4400B		%vreg68<def> = LDRWui %vreg69<kill>, 23; mem:LD4[%state_in_ch122] GPR32common:%vreg68 GPR64common:%vreg69
4416B		%WZR<def> = SUBSWri %vreg68<kill>, 256, 0, %NZCV<imp-def>; GPR32common:%vreg68
4432B		Bcc 2, <BB#34>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#34 BB#33
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %W8<def> = LDRWui %X8<kill>, 23; mem:LD4[%state_in_ch122]
> %WZR<def> = SUBSWri %W8<kill>, 256, 0, %NZCV<imp-def>
> Bcc 2, <BB#34>, %NZCV<imp-use,kill>
4448B	BB#33: derived from LLVM BB %if.then.125
	    Live Ins: %X19
	    Predecessors according to CFG: BB#32
4464B		%vreg71<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg71
4480B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4496B		%X0<def> = COPY %vreg71<kill>; GPR64:%vreg71
4512B		BL <ga:@add_pair_to_block>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>
4528B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4544B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
4560B		STACKMAP 2, 0, 0, <fi#5>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack5](align=1) LD8[FixedStack1](align=1) LD8[FixedStack0] LD8[FixedStack4](align=4)
4576B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#34
> %X0<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BL <ga:@add_pair_to_block>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 2, 0, 0, <fi#5>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack5](align=1) LD8[FixedStack1](align=1) LD8[FixedStack0] LD8[FixedStack4](align=4)
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
4592B	BB#34: derived from LLVM BB %if.end.126
	    Live Ins: %X19
	    Predecessors according to CFG: BB#32 BB#33
4624B		%vreg78<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4] GPR32:%vreg78
4640B		%vreg77<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg77
4656B		STRWui %vreg78<kill>, %vreg77<kill>, 23; mem:ST4[%state_in_ch127] GPR32:%vreg78 GPR64common:%vreg77
4672B		%vreg74<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg74
4680B		%vreg72<def> = MOVi32imm 1; GPR32:%vreg72
4688B		STRWui %vreg72<kill>, %vreg74<kill>, 24; mem:ST4[%state_in_len128] GPR32:%vreg72 GPR64common:%vreg74
4704B		B <BB#36>
	    Successors according to CFG: BB#36
> %W8<def> = LDRWui <fi#4>, 0; mem:LD4[FixedStack4]
> %X9<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> STRWui %W8<kill>, %X9<kill>, 23; mem:ST4[%state_in_ch127]
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %W9<def> = MOVi32imm 1
> STRWui %W9<kill>, %X8<kill>, 24; mem:ST4[%state_in_len128]
> B <BB#36>
4720B	BB#35: derived from LLVM BB %if.else.129
	    Live Ins: %X19
	    Predecessors according to CFG: BB#31
4736B		%vreg65<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg65
4752B		%vreg64<def> = LDRWui %vreg65, 24; mem:LD4[%state_in_len130] GPR32common:%vreg64 GPR64common:%vreg65
4768B		%vreg63<def> = ADDWri %vreg64<kill>, 1, 0; GPR32common:%vreg63,%vreg64
4784B		STRWui %vreg63<kill>, %vreg65<kill>, 24; mem:ST4[%state_in_len130] GPR32common:%vreg63 GPR64common:%vreg65
	    Successors according to CFG: BB#36
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %W9<def> = LDRWui %X8, 24; mem:LD4[%state_in_len130]
> %W9<def> = ADDWri %W9<kill>, 1, 0
> STRWui %W9<kill>, %X8<kill>, 24; mem:ST4[%state_in_len130]
4800B	BB#36: derived from LLVM BB %if.end.132
	    Live Ins: %X19
	    Predecessors according to CFG: BB#35 BB#34
4816B		B <BB#37>
	    Successors according to CFG: BB#37
> B <BB#37>
4832B	BB#37: derived from LLVM BB %if.end.133
	    Live Ins: %X19
	    Predecessors according to CFG: BB#36 BB#29
4848B		%vreg185<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg185
4864B		%vreg184<def> = LDRXui %vreg185<kill>, 0; mem:LD8[%strm134] GPR64common:%vreg184,%vreg185
4880B		%vreg182<def> = LDRXui %vreg184, 0; mem:LD8[%next_in135] GPR64common:%vreg182,%vreg184
4896B		%vreg181<def> = ADDXri %vreg182<kill>, 1, 0; GPR64common:%vreg181,%vreg182
4912B		STRXui %vreg181<kill>, %vreg184<kill>, 0; mem:ST8[%next_in135] GPR64common:%vreg181,%vreg184
4928B		%vreg177<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg177
4944B		%vreg176<def> = LDRXui %vreg177<kill>, 0; mem:LD8[%strm137] GPR64common:%vreg176,%vreg177
4960B		%vreg174<def> = LDRWui %vreg176, 2; mem:LD4[%avail_in138] GPR32common:%vreg174 GPR64common:%vreg176
4976B		%vreg173<def> = SUBWri %vreg174<kill>, 1, 0; GPR32common:%vreg173,%vreg174
4992B		STRWui %vreg173<kill>, %vreg176<kill>, 2; mem:ST4[%avail_in138] GPR32common:%vreg173 GPR64common:%vreg176
5008B		%vreg169<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg169
5024B		%vreg168<def> = LDRXui %vreg169<kill>, 0; mem:LD8[%strm140] GPR64common:%vreg168,%vreg169
5040B		%vreg166<def> = LDRWui %vreg168, 3; mem:LD4[%total_in_lo32141] GPR32common:%vreg166 GPR64common:%vreg168
5056B		%vreg165<def> = ADDWri %vreg166<kill>, 1, 0; GPR32common:%vreg165,%vreg166
5072B		STRWui %vreg165<kill>, %vreg168<kill>, 3; mem:ST4[%total_in_lo32141] GPR32common:%vreg165 GPR64common:%vreg168
5088B		%vreg161<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg161
5104B		%vreg160<def> = LDRXui %vreg161<kill>, 0; mem:LD8[%strm143] GPR64common:%vreg160,%vreg161
5120B		%vreg158<def> = LDRWui %vreg160<kill>, 3; mem:LD4[%total_in_lo32144] GPR32:%vreg158 GPR64common:%vreg160
5136B		CBNZW %vreg158<kill>, <BB#39>; GPR32:%vreg158
	    Successors according to CFG: BB#39 BB#38
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %X8<def> = LDRXui %X8<kill>, 0; mem:LD8[%strm134]
> %X9<def> = LDRXui %X8, 0; mem:LD8[%next_in135]
> %X9<def> = ADDXri %X9<kill>, 1, 0
> STRXui %X9<kill>, %X8<kill>, 0; mem:ST8[%next_in135]
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %X8<def> = LDRXui %X8<kill>, 0; mem:LD8[%strm137]
> %W9<def> = LDRWui %X8, 2; mem:LD4[%avail_in138]
> %W9<def> = SUBWri %W9<kill>, 1, 0
> STRWui %W9<kill>, %X8<kill>, 2; mem:ST4[%avail_in138]
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %X8<def> = LDRXui %X8<kill>, 0; mem:LD8[%strm140]
> %W9<def> = LDRWui %X8, 3; mem:LD4[%total_in_lo32141]
> %W9<def> = ADDWri %W9<kill>, 1, 0
> STRWui %W9<kill>, %X8<kill>, 3; mem:ST4[%total_in_lo32141]
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %X8<def> = LDRXui %X8<kill>, 0; mem:LD8[%strm143]
> %W8<def> = LDRWui %X8<kill>, 3; mem:LD4[%total_in_lo32144]
> CBNZW %W8<kill>, <BB#39>
5152B	BB#38: derived from LLVM BB %if.then.147
	    Live Ins: %X19
	    Predecessors according to CFG: BB#37
5168B		%vreg193<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg193
5184B		%vreg192<def> = LDRXui %vreg193<kill>, 0; mem:LD8[%strm148] GPR64common:%vreg192,%vreg193
5200B		%vreg190<def> = LDRWui %vreg192, 4; mem:LD4[%total_in_hi32149] GPR32common:%vreg190 GPR64common:%vreg192
5216B		%vreg189<def> = ADDWri %vreg190<kill>, 1, 0; GPR32common:%vreg189,%vreg190
5232B		STRWui %vreg189<kill>, %vreg192<kill>, 4; mem:ST4[%total_in_hi32149] GPR32common:%vreg189 GPR64common:%vreg192
	    Successors according to CFG: BB#39
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %X8<def> = LDRXui %X8<kill>, 0; mem:LD8[%strm148]
> %W9<def> = LDRWui %X8, 4; mem:LD4[%total_in_hi32149]
> %W9<def> = ADDWri %W9<kill>, 1, 0
> STRWui %W9<kill>, %X8<kill>, 4; mem:ST4[%total_in_hi32149]
5248B	BB#39: derived from LLVM BB %if.end.151
	    Live Ins: %X19
	    Predecessors according to CFG: BB#37 BB#38
5264B		%vreg199<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg199
5280B		%vreg198<def> = LDRWui %vreg199, 4; mem:LD4[%avail_in_expect152] GPR32common:%vreg198 GPR64common:%vreg199
5296B		%vreg197<def> = SUBWri %vreg198<kill>, 1, 0; GPR32common:%vreg197,%vreg198
5312B		STRWui %vreg197<kill>, %vreg199<kill>, 4; mem:ST4[%avail_in_expect152] GPR32common:%vreg197 GPR64common:%vreg199
5328B		B <BB#21>
	    Successors according to CFG: BB#21
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %W9<def> = LDRWui %X8, 4; mem:LD4[%avail_in_expect152]
> %W9<def> = SUBWri %W9<kill>, 1, 0
> STRWui %W9<kill>, %X8<kill>, 4; mem:ST4[%avail_in_expect152]
> B <BB#21>
5344B	BB#40: derived from LLVM BB %while.end.154
	    Live Ins: %X19
	    Predecessors according to CFG: BB#26 BB#24 BB#22
5360B		B <BB#41>
	    Successors according to CFG: BB#41
> B <BB#41>
5376B	BB#41: derived from LLVM BB %if.end.155
	    Live Ins: %X19
	    Predecessors according to CFG: BB#40 BB#19
5392B		%vreg380<def> = LDRBBui <fi#1>, 0; mem:LD1[%progress_in] GPR32:%vreg380
5424B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5440B		%vreg381<def> = MOVaddr <ga:@copy_input_until_stop>[TF=1], <ga:@copy_input_until_stop>[TF=34]; GPR64:%vreg381
5456B		%X0<def> = COPY %vreg381<kill>; GPR64:%vreg381
5472B		%X1<def> = COPY %vreg9<kill>; GPR64:%vreg9
5488B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %SP<imp-def>
5504B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5520B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
5536B		STACKMAP 3, 0, %vreg380, %LR<earlyclobber,imp-def,dead>, ...; GPR32:%vreg380
5552B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
5568B		%W0<def> = COPY %vreg380<kill>; GPR32:%vreg380
5584B		RET_ReallyLR %W0<imp-use>
> %W20<def> = LDRBBui <fi#1>, 0; mem:LD1[%progress_in]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = MOVaddr <ga:@copy_input_until_stop>[TF=1], <ga:@copy_input_until_stop>[TF=34]
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19<kill>
> BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>, %SP<imp-def>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 3, 0, %W20, %LR<earlyclobber,imp-def,dead>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %W0<def> = COPY %W20<kill>
> RET_ReallyLR %W0<imp-use>
Computing live-in reg-units in ABI blocks.
0B	BB#0 W0#0 W30#0
Created 2 new intervals.
********** INTERVALS **********
W30 [0B,16r:0)[176r,176d:8)[224e,224d:2)[400r,400d:7)[448e,448d:1)[544r,544d:3)[640e,640d:4)[736r,736d:5)[784e,784d:6)  0@0B-phi 1@448e 2@224e 3@544r 4@640e 5@736r 6@784e 7@400r 8@176r
W0 [0B,32r:0)[144r,176r:4)[384r,400r:3)[528r,544r:1)[704r,736r:2)  0@0B-phi 1@528r 2@704r 3@384r 4@144r
%vreg0 [32r,48r:0)  0@32r
%vreg1 [48r,256r:0)  0@48r
%vreg4 [288r,304r:0)  0@288r
%vreg5 [272r,288r:0)  0@272r
%vreg6 [64r,80r:0)  0@64r
%vreg7 [80r,96r:0)  0@80r
%vreg8 [96r,144r:0)  0@96r
%vreg9 [112r,160r:0)  0@112r
%vreg10 [16r,672r:0)  0@16r
%vreg12 [352r,384r:0)  0@352r
%vreg13 [576r,592r:0)  0@576r
%vreg14 [592r,608r:0)  0@592r
%vreg15 [608r,704r:0)  0@608r
%vreg16 [672r,720r:0)  0@672r
%vreg18 [496r,528r:0)  0@496r
RegMasks: 176r 400r 544r 736r
********** MACHINEINSTRS **********
# Machine code for function flush_RL: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
Function Live Ins: %X0 in %vreg0, %LR in %vreg10

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %LR
16B		%vreg10<def> = COPY %LR; GPR64:%vreg10
32B		%vreg0<def> = COPY %X0; GPR64:%vreg0
48B		%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
64B		%vreg6<def> = ADRP <ga:@flush_RL>[TF=1]; GPR64common:%vreg6
80B		%vreg7<def> = ADDXri %vreg6, <ga:@flush_RL>[TF=34], 0; GPR64sp:%vreg7 GPR64common:%vreg6
96B		%vreg8<def> = COPY %vreg7; GPR64all:%vreg8 GPR64sp:%vreg7
112B		%vreg9<def> = COPY %vreg10; GPR64all:%vreg9 GPR64:%vreg10
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		%X0<def> = COPY %vreg8; GPR64all:%vreg8
160B		%X1<def> = COPY %vreg9; GPR64all:%vreg9
176B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
224B		STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] GPR64:%vreg1
240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
256B		STRXui %vreg1, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg1
272B		%vreg5<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg5
288B		%vreg4<def> = LDRWui %vreg5, 23; mem:LD4[%state_in_ch] GPR32common:%vreg4 GPR64common:%vreg5
304B		%WZR<def> = SUBSWri %vreg4, 256, 0, %NZCV<imp-def>; GPR32common:%vreg4
320B		Bcc 2, <BB#2>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

336B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
352B		%vreg12<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg12
368B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
384B		%X0<def> = COPY %vreg12; GPR64:%vreg12
400B		BL <ga:@add_pair_to_block>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>
416B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
432B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
448B		STACKMAP 1, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0]
464B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#2

480B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#1
496B		%vreg18<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg18
512B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
528B		%X0<def> = COPY %vreg18; GPR64:%vreg18
544B		BL <ga:@init_RL>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>
560B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
576B		%vreg13<def> = ADRP <ga:@flush_RL>[TF=1]; GPR64common:%vreg13
592B		%vreg14<def> = ADDXri %vreg13, <ga:@flush_RL>[TF=34], 0; GPR64sp:%vreg14 GPR64common:%vreg13
608B		%vreg15<def> = COPY %vreg14; GPR64all:%vreg15 GPR64sp:%vreg14
624B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
640B		STACKMAP 2, 0, %LR<earlyclobber,imp-def,dead>, ...
656B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
672B		%vreg16<def> = COPY %vreg10; GPR64all:%vreg16 GPR64:%vreg10
688B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
704B		%X0<def> = COPY %vreg15; GPR64all:%vreg15
720B		%X1<def> = COPY %vreg16; GPR64all:%vreg16
736B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
752B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
768B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
784B		STACKMAP 3, 0, %LR<earlyclobber,imp-def,dead>, ...
800B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
816B		RET_ReallyLR

# End machine code for function flush_RL.

********** SIMPLE REGISTER COALESCING **********
********** Function: flush_RL
********** JOINING INTERVALS ***********
entry:
16B	%vreg10<def> = COPY %LR; GPR64:%vreg10
	Considering merging %vreg10 with %LR
	Can only merge into reserved registers.
32B	%vreg0<def> = COPY %X0; GPR64:%vreg0
	Considering merging %vreg0 with %X0
	Can only merge into reserved registers.
144B	%X0<def> = COPY %vreg8; GPR64all:%vreg8
	Considering merging %vreg8 with %X0
	Can only merge into reserved registers.
160B	%X1<def> = COPY %vreg9; GPR64all:%vreg9
	Considering merging %vreg9 with %X1
	Can only merge into reserved registers.
if.then:
384B	%X0<def> = COPY %vreg12; GPR64:%vreg12
	Considering merging %vreg12 with %X0
	Can only merge into reserved registers.
if.end:
528B	%X0<def> = COPY %vreg18; GPR64:%vreg18
	Considering merging %vreg18 with %X0
	Can only merge into reserved registers.
704B	%X0<def> = COPY %vreg15; GPR64all:%vreg15
	Considering merging %vreg15 with %X0
	Can only merge into reserved registers.
720B	%X1<def> = COPY %vreg16; GPR64all:%vreg16
	Considering merging %vreg16 with %X1
	Can only merge into reserved registers.
48B	%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
	Considering merging to GPR64 with %vreg0 in %vreg1
		RHS = %vreg0 [32r,48r:0)  0@32r
		LHS = %vreg1 [48r,256r:0)  0@48r
		merge %vreg1:0@48r into %vreg0:0@32r --> @32r
		erased:	48r	%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
		updated: 32B	%vreg1<def> = COPY %X0; GPR64:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [32r,256r:0)  0@32r
96B	%vreg8<def> = COPY %vreg7; GPR64all:%vreg8 GPR64sp:%vreg7
	Considering merging to GPR64sp with %vreg7 in %vreg8
		RHS = %vreg7 [80r,96r:0)  0@80r
		LHS = %vreg8 [96r,144r:0)  0@96r
		merge %vreg8:0@96r into %vreg7:0@80r --> @80r
		erased:	96r	%vreg8<def> = COPY %vreg7; GPR64all:%vreg8 GPR64sp:%vreg7
		updated: 80B	%vreg8<def> = ADDXri %vreg6, <ga:@flush_RL>[TF=34], 0; GPR64sp:%vreg8 GPR64common:%vreg6
	Success: %vreg7 -> %vreg8
	Result = %vreg8 [80r,144r:0)  0@80r
112B	%vreg9<def> = COPY %vreg10; GPR64all:%vreg9 GPR64:%vreg10
	Considering merging to GPR64 with %vreg10 in %vreg9
		RHS = %vreg10 [16r,672r:0)  0@16r
		LHS = %vreg9 [112r,160r:0)  0@112r
		merge %vreg9:0@112r into %vreg10:0@16r --> @16r
		erased:	112r	%vreg9<def> = COPY %vreg10; GPR64all:%vreg9 GPR64:%vreg10
		updated: 16B	%vreg9<def> = COPY %LR; GPR64:%vreg9
		updated: 672B	%vreg16<def> = COPY %vreg9; GPR64all:%vreg16 GPR64:%vreg9
	Success: %vreg10 -> %vreg9
	Result = %vreg9 [16r,672r:0)  0@16r
608B	%vreg15<def> = COPY %vreg14; GPR64all:%vreg15 GPR64sp:%vreg14
	Considering merging to GPR64sp with %vreg14 in %vreg15
		RHS = %vreg14 [592r,608r:0)  0@592r
		LHS = %vreg15 [608r,704r:0)  0@608r
		merge %vreg15:0@608r into %vreg14:0@592r --> @592r
		erased:	608r	%vreg15<def> = COPY %vreg14; GPR64all:%vreg15 GPR64sp:%vreg14
		updated: 592B	%vreg15<def> = ADDXri %vreg13, <ga:@flush_RL>[TF=34], 0; GPR64sp:%vreg15 GPR64common:%vreg13
	Success: %vreg14 -> %vreg15
	Result = %vreg15 [592r,704r:0)  0@592r
672B	%vreg16<def> = COPY %vreg9; GPR64all:%vreg16 GPR64:%vreg9
	Considering merging to GPR64 with %vreg9 in %vreg16
		RHS = %vreg9 [16r,672r:0)  0@16r
		LHS = %vreg16 [672r,720r:0)  0@672r
		merge %vreg16:0@672r into %vreg9:0@16r --> @16r
		erased:	672r	%vreg16<def> = COPY %vreg9; GPR64all:%vreg16 GPR64:%vreg9
		updated: 16B	%vreg16<def> = COPY %LR; GPR64:%vreg16
		updated: 160B	%X1<def> = COPY %vreg16; GPR64:%vreg16
	Success: %vreg9 -> %vreg16
	Result = %vreg16 [16r,720r:0)  0@16r
144B	%X0<def> = COPY %vreg8; GPR64sp:%vreg8
	Considering merging %vreg8 with %X0
	Can only merge into reserved registers.
160B	%X1<def> = COPY %vreg16; GPR64:%vreg16
	Considering merging %vreg16 with %X1
	Can only merge into reserved registers.
704B	%X0<def> = COPY %vreg15; GPR64sp:%vreg15
	Considering merging %vreg15 with %X0
	Can only merge into reserved registers.
720B	%X1<def> = COPY %vreg16; GPR64:%vreg16
	Considering merging %vreg16 with %X1
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
W30 [0B,16r:0)[176r,176d:8)[224e,224d:2)[400r,400d:7)[448e,448d:1)[544r,544d:3)[640e,640d:4)[736r,736d:5)[784e,784d:6)  0@0B-phi 1@448e 2@224e 3@544r 4@640e 5@736r 6@784e 7@400r 8@176r
W0 [0B,32r:0)[144r,176r:4)[384r,400r:3)[528r,544r:1)[704r,736r:2)  0@0B-phi 1@528r 2@704r 3@384r 4@144r
%vreg1 [32r,256r:0)  0@32r
%vreg4 [288r,304r:0)  0@288r
%vreg5 [272r,288r:0)  0@272r
%vreg6 [64r,80r:0)  0@64r
%vreg8 [80r,144r:0)  0@80r
%vreg12 [352r,384r:0)  0@352r
%vreg13 [576r,592r:0)  0@576r
%vreg15 [592r,704r:0)  0@592r
%vreg16 [16r,720r:0)  0@16r
%vreg18 [496r,528r:0)  0@496r
RegMasks: 176r 400r 544r 736r
********** MACHINEINSTRS **********
# Machine code for function flush_RL: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
Function Live Ins: %X0 in %vreg0, %LR in %vreg10

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %LR
16B		%vreg16<def> = COPY %LR; GPR64:%vreg16
32B		%vreg1<def> = COPY %X0; GPR64:%vreg1
64B		%vreg6<def> = ADRP <ga:@flush_RL>[TF=1]; GPR64common:%vreg6
80B		%vreg8<def> = ADDXri %vreg6, <ga:@flush_RL>[TF=34], 0; GPR64sp:%vreg8 GPR64common:%vreg6
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		%X0<def> = COPY %vreg8; GPR64sp:%vreg8
160B		%X1<def> = COPY %vreg16; GPR64:%vreg16
176B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
224B		STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] GPR64:%vreg1
240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
256B		STRXui %vreg1, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg1
272B		%vreg5<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg5
288B		%vreg4<def> = LDRWui %vreg5, 23; mem:LD4[%state_in_ch] GPR32common:%vreg4 GPR64common:%vreg5
304B		%WZR<def> = SUBSWri %vreg4, 256, 0, %NZCV<imp-def>; GPR32common:%vreg4
320B		Bcc 2, <BB#2>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

336B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
352B		%vreg12<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg12
368B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
384B		%X0<def> = COPY %vreg12; GPR64:%vreg12
400B		BL <ga:@add_pair_to_block>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>
416B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
432B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
448B		STACKMAP 1, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0]
464B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#2

480B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#1
496B		%vreg18<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg18
512B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
528B		%X0<def> = COPY %vreg18; GPR64:%vreg18
544B		BL <ga:@init_RL>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>
560B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
576B		%vreg13<def> = ADRP <ga:@flush_RL>[TF=1]; GPR64common:%vreg13
592B		%vreg15<def> = ADDXri %vreg13, <ga:@flush_RL>[TF=34], 0; GPR64sp:%vreg15 GPR64common:%vreg13
624B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
640B		STACKMAP 2, 0, %LR<earlyclobber,imp-def,dead>, ...
656B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
688B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
704B		%X0<def> = COPY %vreg15; GPR64sp:%vreg15
720B		%X1<def> = COPY %vreg16; GPR64:%vreg16
736B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
752B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
768B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
784B		STACKMAP 3, 0, %LR<earlyclobber,imp-def,dead>, ...
800B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
816B		RET_ReallyLR

# End machine code for function flush_RL.

********** GREEDY REGISTER ALLOCATION **********
********** Function: flush_RL
********** INTERVALS **********
W30 [0B,16r:0)[176r,176d:8)[224e,224d:2)[400r,400d:7)[448e,448d:1)[544r,544d:3)[640e,640d:4)[736r,736d:5)[784e,784d:6)  0@0B-phi 1@448e 2@224e 3@544r 4@640e 5@736r 6@784e 7@400r 8@176r
W0 [0B,32r:0)[144r,176r:4)[384r,400r:3)[528r,544r:1)[704r,736r:2)  0@0B-phi 1@528r 2@704r 3@384r 4@144r
%vreg1 [32r,256r:0)  0@32r
%vreg4 [288r,304r:0)  0@288r
%vreg5 [272r,288r:0)  0@272r
%vreg6 [64r,80r:0)  0@64r
%vreg8 [80r,144r:0)  0@80r
%vreg12 [352r,384r:0)  0@352r
%vreg13 [576r,592r:0)  0@576r
%vreg15 [592r,704r:0)  0@592r
%vreg16 [16r,720r:0)  0@16r
%vreg18 [496r,528r:0)  0@496r
RegMasks: 176r 400r 544r 736r
********** MACHINEINSTRS **********
# Machine code for function flush_RL: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
Function Live Ins: %X0 in %vreg0, %LR in %vreg10

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %LR
16B		%vreg16<def> = COPY %LR; GPR64:%vreg16
32B		%vreg1<def> = COPY %X0; GPR64:%vreg1
64B		%vreg6<def> = ADRP <ga:@flush_RL>[TF=1]; GPR64common:%vreg6
80B		%vreg8<def> = ADDXri %vreg6, <ga:@flush_RL>[TF=34], 0; GPR64sp:%vreg8 GPR64common:%vreg6
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		%X0<def> = COPY %vreg8; GPR64sp:%vreg8
160B		%X1<def> = COPY %vreg16; GPR64:%vreg16
176B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
224B		STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] GPR64:%vreg1
240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
256B		STRXui %vreg1, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg1
272B		%vreg5<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg5
288B		%vreg4<def> = LDRWui %vreg5, 23; mem:LD4[%state_in_ch] GPR32common:%vreg4 GPR64common:%vreg5
304B		%WZR<def> = SUBSWri %vreg4, 256, 0, %NZCV<imp-def>; GPR32common:%vreg4
320B		Bcc 2, <BB#2>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

336B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
352B		%vreg12<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg12
368B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
384B		%X0<def> = COPY %vreg12; GPR64:%vreg12
400B		BL <ga:@add_pair_to_block>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>
416B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
432B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
448B		STACKMAP 1, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0]
464B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#2

480B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#1
496B		%vreg18<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg18
512B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
528B		%X0<def> = COPY %vreg18; GPR64:%vreg18
544B		BL <ga:@init_RL>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>
560B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
576B		%vreg13<def> = ADRP <ga:@flush_RL>[TF=1]; GPR64common:%vreg13
592B		%vreg15<def> = ADDXri %vreg13, <ga:@flush_RL>[TF=34], 0; GPR64sp:%vreg15 GPR64common:%vreg13
624B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
640B		STACKMAP 2, 0, %LR<earlyclobber,imp-def,dead>, ...
656B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
688B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
704B		%X0<def> = COPY %vreg15; GPR64sp:%vreg15
720B		%X1<def> = COPY %vreg16; GPR64:%vreg16
736B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
752B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
768B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
784B		STACKMAP 3, 0, %LR<earlyclobber,imp-def,dead>, ...
800B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
816B		RET_ReallyLR

# End machine code for function flush_RL.


selectOrSplit GPR64:%vreg16 [16r,720r:0)  0@16r w=2.744565e-03
hints: %X1
missed hint %X1
assigning %vreg16 to %X19: W19 [16r,720r:0)  0@16r

selectOrSplit GPR64:%vreg1 [32r,256r:0)  0@32r w=4.855769e-03
hints: %X0
missed hint %X0
assigning %vreg1 to %X20: W20 [32r,256r:0)  0@32r

selectOrSplit GPR64sp:%vreg8 [80r,144r:0)  0@80r w=4.353448e-03
hints: %X0
assigning %vreg8 to %X0: W0 [80r,144r:0)  0@80r

selectOrSplit GPR64:%vreg12 [352r,384r:0)  0@352r w=2.337963e-03
hints: %X0
assigning %vreg12 to %X0: W0 [352r,384r:0)  0@352r

selectOrSplit GPR64:%vreg18 [496r,528r:0)  0@496r w=4.675926e-03
hints: %X0
assigning %vreg18 to %X0: W0 [496r,528r:0)  0@496r

selectOrSplit GPR64sp:%vreg15 [592r,704r:0)  0@592r w=3.945312e-03
hints: %X0
assigning %vreg15 to %X0: W0 [592r,704r:0)  0@592r

selectOrSplit GPR64common:%vreg6 [64r,80r:0)  0@64r w=inf
assigning %vreg6 to %X8: W8 [64r,80r:0)  0@64r

selectOrSplit GPR64common:%vreg5 [272r,288r:0)  0@272r w=inf
assigning %vreg5 to %X8: W8 [272r,288r:0)  0@272r

selectOrSplit GPR32common:%vreg4 [288r,304r:0)  0@288r w=inf
assigning %vreg4 to %W8: W8 [288r,304r:0)  0@288r

selectOrSplit GPR64common:%vreg13 [576r,592r:0)  0@576r w=inf
assigning %vreg13 to %X8: W8 [576r,592r:0)  0@576r

********** STACK TRANSFORMATION METADATA **********
********** Function: flush_RL
********** REGISTER MAP **********
[%vreg1 -> %X20] GPR64
[%vreg4 -> %W8] GPR32common
[%vreg5 -> %X8] GPR64common
[%vreg6 -> %X8] GPR64common
[%vreg8 -> %X0] GPR64sp
[%vreg12 -> %X0] GPR64
[%vreg13 -> %X8] GPR64common
[%vreg15 -> %X0] GPR64sp
[%vreg16 -> %X19] GPR64
[%vreg18 -> %X0] GPR64


Stackmap 0:
  STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] GPR64:%vreg1

%struct.EState* %s: in register %X20 (vreg 1)
%struct.EState** %s.addr: in stack slot 0 (size: 8)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0]

%struct.EState** %s.addr: in stack slot 0 (size: 8)

Duplicate operand locations:


Stackmap 2:
  STACKMAP 2, 0, %LR<earlyclobber,imp-def,dead>, ...


Duplicate operand locations:


Stackmap 3:
  STACKMAP 3, 0, %LR<earlyclobber,imp-def,dead>, ...


Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] GPR64:%vreg1
  -> Call instruction SlotIndex 176B, searching vregs 0 -> 19 and stack slots 0 -> 1
    + vreg16 is live in register but not in stackmap
      Defining instruction: %vreg16<def> = COPY %LR; GPR64:%vreg16
      Value: generated value, 1 instruction(s)

  STACKMAP 1, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0]
  -> Call instruction SlotIndex 400B, searching vregs 0 -> 19 and stack slots 0 -> 1
    + vreg16 is live in register but not in stackmap
      Defining instruction: %vreg16<def> = COPY %LR; GPR64:%vreg16
      Value: generated value, 1 instruction(s)

  STACKMAP 2, 0, %LR<earlyclobber,imp-def,dead>, ...
  -> Call instruction SlotIndex 544B, searching vregs 0 -> 19 and stack slots 0 -> 1
    + vreg16 is live in register but not in stackmap
      Defining instruction: %vreg16<def> = COPY %LR; GPR64:%vreg16
      Value: generated value, 1 instruction(s)

  STACKMAP 3, 0, %LR<earlyclobber,imp-def,dead>, ...
  -> Call instruction SlotIndex 736B, searching vregs 0 -> 19 and stack slots 0 -> 1

********** REWRITE VIRTUAL REGISTERS **********
********** Function: flush_RL
********** REGISTER MAP **********
[%vreg1 -> %X20] GPR64
[%vreg4 -> %W8] GPR32common
[%vreg5 -> %X8] GPR64common
[%vreg6 -> %X8] GPR64common
[%vreg8 -> %X0] GPR64sp
[%vreg12 -> %X0] GPR64
[%vreg13 -> %X8] GPR64common
[%vreg15 -> %X0] GPR64sp
[%vreg16 -> %X19] GPR64
[%vreg18 -> %X0] GPR64

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %LR %X0
16B		%vreg16<def> = COPY %LR; GPR64:%vreg16
32B		%vreg1<def> = COPY %X0; GPR64:%vreg1
64B		%vreg6<def> = ADRP <ga:@flush_RL>[TF=1]; GPR64common:%vreg6
80B		%vreg8<def> = ADDXri %vreg6<kill>, <ga:@flush_RL>[TF=34], 0; GPR64sp:%vreg8 GPR64common:%vreg6
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		%X0<def> = COPY %vreg8<kill>; GPR64sp:%vreg8
160B		%X1<def> = COPY %vreg16; GPR64:%vreg16
176B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
224B		STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0] GPR64:%vreg1
240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
256B		STRXui %vreg1<kill>, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg1
272B		%vreg5<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg5
288B		%vreg4<def> = LDRWui %vreg5<kill>, 23; mem:LD4[%state_in_ch] GPR32common:%vreg4 GPR64common:%vreg5
304B		%WZR<def> = SUBSWri %vreg4<kill>, 256, 0, %NZCV<imp-def>; GPR32common:%vreg4
320B		Bcc 2, <BB#2>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1
> %X19<def> = COPY %LR
> %X20<def> = COPY %X0
> %X8<def> = ADRP <ga:@flush_RL>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@flush_RL>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19
> BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 0, 0, %X20, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRXui %X20<kill>, <fi#0>, 0; mem:ST8[FixedStack0]
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %W8<def> = LDRWui %X8<kill>, 23; mem:LD4[%state_in_ch]
> %WZR<def> = SUBSWri %W8<kill>, 256, 0, %NZCV<imp-def>
> Bcc 2, <BB#2>, %NZCV<imp-use,kill>
336B	BB#1: derived from LLVM BB %if.then
	    Live Ins: %X19
	    Predecessors according to CFG: BB#0
352B		%vreg12<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg12
368B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
384B		%X0<def> = COPY %vreg12<kill>; GPR64:%vreg12
400B		BL <ga:@add_pair_to_block>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>
416B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
432B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
448B		STACKMAP 1, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0]
464B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
	    Successors according to CFG: BB#2
> %X0<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BL <ga:@add_pair_to_block>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 1, 0, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack0]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
480B	BB#2: derived from LLVM BB %if.end
	    Live Ins: %X19
	    Predecessors according to CFG: BB#0 BB#1
496B		%vreg18<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64:%vreg18
512B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
528B		%X0<def> = COPY %vreg18<kill>; GPR64:%vreg18
544B		BL <ga:@init_RL>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>
560B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
576B		%vreg13<def> = ADRP <ga:@flush_RL>[TF=1]; GPR64common:%vreg13
592B		%vreg15<def> = ADDXri %vreg13<kill>, <ga:@flush_RL>[TF=34], 0; GPR64sp:%vreg15 GPR64common:%vreg13
624B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
640B		STACKMAP 2, 0, %LR<earlyclobber,imp-def,dead>, ...
656B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
688B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
704B		%X0<def> = COPY %vreg15<kill>; GPR64sp:%vreg15
720B		%X1<def> = COPY %vreg16<kill>; GPR64:%vreg16
736B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
752B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
768B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
784B		STACKMAP 3, 0, %LR<earlyclobber,imp-def,dead>, ...
800B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
816B		RET_ReallyLR
> %X0<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> BL <ga:@init_RL>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> %X8<def> = ADRP <ga:@flush_RL>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@flush_RL>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 2, 0, %LR<earlyclobber,imp-def,dead>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19<kill>
> BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 3, 0, %LR<earlyclobber,imp-def,dead>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> RET_ReallyLR
Computing live-in reg-units in ABI blocks.
0B	BB#0 W0#0 W30#0
Created 2 new intervals.
********** INTERVALS **********
W30 [0B,16r:0)[176r,176d:4)[224e,224d:1)[3552r,3552d:2)[3600e,3600d:3)  0@0B-phi 1@224e 2@3552r 3@3600e 4@176r
W0 [0B,32r:0)[144r,176r:2)[3520r,3552r:1)  0@0B-phi 1@3520r 2@144r
%vreg0 [32r,48r:0)  0@32r
%vreg1 [48r,256r:0)  0@48r
%vreg4 [304r,320r:0)  0@304r
%vreg6 [288r,304r:0)  0@288r
%vreg7 [272r,288r:0)  0@272r
%vreg8 [64r,80r:0)  0@64r
%vreg9 [80r,96r:0)  0@80r
%vreg10 [96r,144r:0)  0@96r
%vreg11 [112r,160r:0)  0@112r
%vreg12 [16r,3488r:0)  0@16r
%vreg16 [400r,416r:0)  0@400r
%vreg17 [384r,400r:0)  0@384r
%vreg18 [368r,416r:0)  0@368r
%vreg19 [976r,1120r:0)  0@976r
%vreg20 [848r,896r:0)  0@848r
%vreg21 [864r,880r:0)  0@864r
%vreg22 [880r,896r:0)  0@880r
%vreg23 [896r,928r:0)  0@896r
%vreg24 [912r,928r:0)  0@912r
%vreg25 [944r,960r:0)  0@944r
%vreg26 [960r,992r:0)  0@960r
%vreg27 [992r,992d:0)  0@992r
%vreg28 [1056r,1056d:0)  0@1056r
%vreg29 [1120r,1120d:0)  0@1120r
%vreg33 [2272r,2288r:0)  0@2272r
%vreg34 [2256r,2272r:0)  0@2256r
%vreg35 [2240r,2288r:0)  0@2240r
%vreg40 [2208r,2224r:0)  0@2208r
%vreg42 [2192r,2208r:0)  0@2192r
%vreg43 [2176r,2192r:0)  0@2176r
%vreg48 [2160r,2208r:0)  0@2160r
%vreg49 [2144r,2160r:0)  0@2144r
%vreg50 [2128r,2224r:0)  0@2128r
%vreg54 [2096r,2112r:0)  0@2096r
%vreg55 [2080r,2096r:0)  0@2080r
%vreg56 [2064r,2112r:0)  0@2064r
%vreg61 [2032r,2048r:0)  0@2032r
%vreg63 [2016r,2032r:0)  0@2016r
%vreg64 [2000r,2016r:0)  0@2000r
%vreg69 [1984r,2032r:0)  0@1984r
%vreg70 [1968r,1984r:0)  0@1968r
%vreg71 [1952r,2048r:0)  0@1952r
%vreg75 [1920r,1936r:0)  0@1920r
%vreg76 [1904r,1920r:0)  0@1904r
%vreg77 [1888r,1936r:0)  0@1888r
%vreg82 [1856r,1872r:0)  0@1856r
%vreg84 [1840r,1856r:0)  0@1840r
%vreg85 [1824r,1840r:0)  0@1824r
%vreg90 [1808r,1856r:0)  0@1808r
%vreg91 [1792r,1808r:0)  0@1792r
%vreg92 [1776r,1872r:0)  0@1776r
%vreg96 [1712r,1728r:0)  0@1712r
%vreg97 [1696r,1712r:0)  0@1696r
%vreg98 [1680r,1728r:0)  0@1680r
%vreg103 [1648r,1664r:0)  0@1648r
%vreg105 [1632r,1648r:0)  0@1632r
%vreg106 [1616r,1632r:0)  0@1616r
%vreg111 [1600r,1648r:0)  0@1600r
%vreg112 [1584r,1600r:0)  0@1584r
%vreg113 [1568r,1664r:0)  0@1568r
%vreg117 [1536r,1552r:0)  0@1536r
%vreg118 [1520r,1536r:0)  0@1520r
%vreg119 [1504r,1552r:0)  0@1504r
%vreg124 [1472r,1488r:0)  0@1472r
%vreg126 [1456r,1472r:0)  0@1456r
%vreg127 [1440r,1456r:0)  0@1440r
%vreg132 [1424r,1472r:0)  0@1424r
%vreg133 [1408r,1424r:0)  0@1408r
%vreg134 [1392r,1488r:0)  0@1392r
%vreg138 [1328r,1344r:0)  0@1328r
%vreg139 [1312r,1328r:0)  0@1312r
%vreg140 [1296r,1344r:0)  0@1296r
%vreg145 [1264r,1280r:0)  0@1264r
%vreg147 [1248r,1264r:0)  0@1248r
%vreg148 [1232r,1248r:0)  0@1232r
%vreg153 [1216r,1264r:0)  0@1216r
%vreg154 [1200r,1216r:0)  0@1200r
%vreg155 [1184r,1280r:0)  0@1184r
%vreg159 [3392r,3408r:0)  0@3392r
%vreg160 [3376r,3392r:0)  0@3376r
%vreg161 [3360r,3408r:0)  0@3360r
%vreg166 [3328r,3344r:0)  0@3328r
%vreg168 [3312r,3328r:0)  0@3312r
%vreg169 [3296r,3312r:0)  0@3296r
%vreg174 [3280r,3328r:0)  0@3280r
%vreg175 [3264r,3280r:0)  0@3264r
%vreg177 [3248r,3344r:0)  0@3248r
%vreg179 [3232r,3248r:0)  0@3232r
%vreg181 [3216r,3232r:0)  0@3216r
%vreg182 [3200r,3216r:0)  0@3200r
%vreg186 [3168r,3184r:0)  0@3168r
%vreg187 [3152r,3168r:0)  0@3152r
%vreg188 [3136r,3184r:0)  0@3136r
%vreg193 [3104r,3120r:0)  0@3104r
%vreg195 [3088r,3104r:0)  0@3088r
%vreg196 [3072r,3088r:0)  0@3072r
%vreg201 [3056r,3104r:0)  0@3056r
%vreg202 [3040r,3056r:0)  0@3040r
%vreg203 [3024r,3120r:0)  0@3024r
%vreg207 [2992r,3008r:0)  0@2992r
%vreg208 [2976r,2992r:0)  0@2976r
%vreg209 [2960r,3008r:0)  0@2960r
%vreg214 [2928r,2944r:0)  0@2928r
%vreg216 [2912r,2928r:0)  0@2912r
%vreg217 [2896r,2912r:0)  0@2896r
%vreg222 [2880r,2928r:0)  0@2880r
%vreg223 [2864r,2880r:0)  0@2864r
%vreg224 [2848r,2944r:0)  0@2848r
%vreg228 [2816r,2832r:0)  0@2816r
%vreg229 [2800r,2816r:0)  0@2800r
%vreg230 [2784r,2832r:0)  0@2784r
%vreg235 [2752r,2768r:0)  0@2752r
%vreg237 [2736r,2752r:0)  0@2736r
%vreg238 [2720r,2736r:0)  0@2720r
%vreg243 [2704r,2752r:0)  0@2704r
%vreg244 [2688r,2704r:0)  0@2688r
%vreg245 [2672r,2768r:0)  0@2672r
%vreg249 [2640r,2656r:0)  0@2640r
%vreg250 [2624r,2640r:0)  0@2624r
%vreg251 [2608r,2656r:0)  0@2608r
%vreg256 [2576r,2592r:0)  0@2576r
%vreg258 [2560r,2576r:0)  0@2560r
%vreg259 [2544r,2560r:0)  0@2544r
%vreg264 [2528r,2576r:0)  0@2528r
%vreg265 [2512r,2528r:0)  0@2512r
%vreg266 [2496r,2592r:0)  0@2496r
%vreg267 [2336r,2480r:0)  0@2336r
%vreg271 [2464r,2480r:0)  0@2464r
%vreg273 [2448r,2464r:0)  0@2448r
%vreg274 [2432r,2448r:0)  0@2432r
%vreg276 [2400r,2416r:0)  0@2400r
%vreg277 [2416r,2464r:0)  0@2416r
%vreg279 [2384r,2400r:0)  0@2384r
%vreg281 [2368r,2384r:0)  0@2368r
%vreg282 [2352r,2368r:0)  0@2352r
%vreg283 [3440r,3456r:0)  0@3440r
%vreg284 [3456r,3472r:0)  0@3456r
%vreg285 [3472r,3520r:0)  0@3472r
%vreg286 [3488r,3536r:0)  0@3488r
%vreg289 [720r,736r:0)  0@720r
%vreg292 [704r,736r:0)  0@704r
%vreg294 [688r,704r:0)  0@688r
%vreg295 [464r,480r:0)  0@464r
%vreg296 [480r,672r:0)  0@480r
%vreg298 [640r,656r:0)  0@640r
%vreg299 [656r,672r:0)  0@656r
%vreg300 [672r,688r:0)  0@672r
%vreg302 [608r,624r:0)  0@608r
%vreg303 [624r,656r:0)  0@624r
%vreg306 [592r,608r:0)  0@592r
%vreg309 [576r,592r:0)  0@576r
%vreg311 [560r,592r:0)  0@560r
%vreg313 [544r,560r:0)  0@544r
%vreg314 [528r,544r:0)  0@528r
%vreg316 [512r,704r:0)  0@512r
%vreg317 [496r,512r:0)  0@496r
%vreg320 [784r,800r:0)  0@784r
%vreg321 [768r,784r:0)  0@768r
RegMasks: 176r 3552r
********** MACHINEINSTRS **********
# Machine code for function add_pair_to_block: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
  fi#1: size=4, align=4, at location [SP]
  fi#2: size=1, align=1, at location [SP]
Function Live Ins: %X0 in %vreg0, %LR in %vreg12

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %LR
16B		%vreg12<def> = COPY %LR; GPR64:%vreg12
32B		%vreg0<def> = COPY %X0; GPR64:%vreg0
48B		%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
64B		%vreg8<def> = ADRP <ga:@add_pair_to_block>[TF=1]; GPR64common:%vreg8
80B		%vreg9<def> = ADDXri %vreg8, <ga:@add_pair_to_block>[TF=34], 0; GPR64sp:%vreg9 GPR64common:%vreg8
96B		%vreg10<def> = COPY %vreg9; GPR64all:%vreg10 GPR64sp:%vreg9
112B		%vreg11<def> = COPY %vreg12; GPR64all:%vreg11 GPR64:%vreg12
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		%X0<def> = COPY %vreg10; GPR64all:%vreg10
160B		%X1<def> = COPY %vreg11; GPR64all:%vreg11
176B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
224B		STACKMAP 0, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack1](align=4) LD8[FixedStack0] GPR64:%vreg1
240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
256B		STRXui %vreg1, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg1
272B		%vreg7<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg7
288B		%vreg6<def> = LDRWui %vreg7, 23; mem:LD4[%state_in_ch] GPR32:%vreg6 GPR64common:%vreg7
304B		%vreg4<def> = COPY %vreg6; GPR32:%vreg4,%vreg6
320B		STRBBui %vreg4, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg4
336B		STRWui %WZR, <fi#1>, 0; mem:ST4[FixedStack1]
	    Successors according to CFG: BB#1

352B	BB#1: derived from LLVM BB %for.cond
	    Predecessors according to CFG: BB#0 BB#3
368B		%vreg18<def> = LDRWui <fi#1>, 0; mem:LD4[FixedStack1] GPR32:%vreg18
384B		%vreg17<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg17
400B		%vreg16<def> = LDRWui %vreg17, 24; mem:LD4[%state_in_len] GPR32:%vreg16 GPR64common:%vreg17
416B		%WZR<def> = SUBSWrr %vreg18, %vreg16, %NZCV<imp-def>; GPR32:%vreg18,%vreg16
432B		Bcc 10, <BB#4>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#4 BB#2

448B	BB#2: derived from LLVM BB %for.body
	    Predecessors according to CFG: BB#1
464B		%vreg295<def> = ADRP <ga:@BZ2_crc32Table>[TF=1]; GPR64common:%vreg295
480B		%vreg296<def> = ADDXri %vreg295, <ga:@BZ2_crc32Table>[TF=34], 0; GPR64common:%vreg296,%vreg295
496B		%vreg317<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg317
512B		%vreg316<def> = LDRWui %vreg317, 162; mem:LD4[%blockCRC] GPR32:%vreg316 GPR64common:%vreg317
528B		%vreg314<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg314
544B		%vreg313<def> = LDRWui %vreg314, 162; mem:LD4[%blockCRC2] GPR32:%vreg313 GPR64common:%vreg314
560B		%vreg311<def> = UBFMWri %vreg313, 24, 31; GPR32:%vreg311,%vreg313
576B		%vreg309<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg309
592B		%vreg306<def> = EORWrr %vreg311, %vreg309; GPR32:%vreg306,%vreg311,%vreg309
608B		%vreg302<def> = SUBREG_TO_REG 0, %vreg306, 15; GPR64:%vreg302 GPR32:%vreg306
624B		%vreg303<def> = UBFMXri %vreg302, 0, 31; GPR64:%vreg303,%vreg302
640B		%vreg298<def> = MOVi64imm 4; GPR64:%vreg298
656B		%vreg299<def> = MADDXrrr %vreg303, %vreg298, %XZR; GPR64:%vreg299,%vreg303,%vreg298
672B		%vreg300<def> = ADDXrr %vreg296, %vreg299; GPR64common:%vreg300,%vreg296 GPR64:%vreg299
688B		%vreg294<def> = LDRWui %vreg300, 0; mem:LD4[%arrayidx] GPR32:%vreg294 GPR64common:%vreg300
704B		%vreg292<def> = EORWrs %vreg294, %vreg316, 8; GPR32:%vreg292,%vreg294,%vreg316
720B		%vreg289<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg289
736B		STRWui %vreg292, %vreg289, 162; mem:ST4[%blockCRC5] GPR32:%vreg292 GPR64common:%vreg289
	    Successors according to CFG: BB#3

752B	BB#3: derived from LLVM BB %for.inc
	    Predecessors according to CFG: BB#2
768B		%vreg321<def> = LDRWui <fi#1>, 0; mem:LD4[FixedStack1] GPR32common:%vreg321
784B		%vreg320<def> = ADDWri %vreg321, 1, 0; GPR32common:%vreg320,%vreg321
800B		STRWui %vreg320, <fi#1>, 0; mem:ST4[FixedStack1] GPR32common:%vreg320
816B		B <BB#1>
	    Successors according to CFG: BB#1

832B	BB#4: derived from LLVM BB %for.end
	    Predecessors according to CFG: BB#1
848B		%vreg20<def> = LDRXui <fi#0>, 0; mem:LD8[%s.addr] GPR64common:%vreg20
864B		%vreg21<def> = LDRWui %vreg20, 23; mem:LD4[%state_in_ch6] GPR32:%vreg21 GPR64common:%vreg20
880B		%vreg22<def> = SUBREG_TO_REG 0, %vreg21, 15; GPR64:%vreg22 GPR32:%vreg21
896B		%vreg23<def> = ADDXrr %vreg20, %vreg22; GPR64common:%vreg23,%vreg20 GPR64:%vreg22
912B		%vreg24<def> = MOVi32imm 1; GPR32:%vreg24
928B		STRBBui %vreg24, %vreg23, 128; mem:ST1[%arrayidx8] GPR32:%vreg24 GPR64common:%vreg23
944B		%vreg25<def> = LDRXui <fi#0>, 0; mem:LD8[%s.addr] GPR64common:%vreg25
960B		%vreg26<def> = LDRWui %vreg25, 24; mem:LD4[%state_in_len9] GPR32common:%vreg26 GPR64common:%vreg25
976B		%vreg19<def> = COPY %vreg26; GPR32sp:%vreg19 GPR32common:%vreg26
992B		%vreg27<def,dead> = SUBSWri %vreg26, 1, 0, %NZCV<imp-def>; GPR32:%vreg27 GPR32common:%vreg26
1008B		Bcc 0, <BB#7>, %NZCV<imp-use,kill>
1024B		B <BB#5>
	    Successors according to CFG: BB#7 BB#5

1040B	BB#5: derived from LLVM BB %for.end
	    Predecessors according to CFG: BB#4
1056B		%vreg28<def,dead> = SUBSWri %vreg19, 2, 0, %NZCV<imp-def>; GPR32:%vreg28 GPR32sp:%vreg19
1072B		Bcc 0, <BB#8>, %NZCV<imp-use,kill>
1088B		B <BB#6>
	    Successors according to CFG: BB#8 BB#6

1104B	BB#6: derived from LLVM BB %for.end
	    Predecessors according to CFG: BB#5
1120B		%vreg29<def,dead> = SUBSWri %vreg19, 3, 0, %NZCV<imp-def>; GPR32:%vreg29 GPR32sp:%vreg19
1136B		Bcc 0, <BB#9>, %NZCV<imp-use,kill>
1152B		B <BB#10>
	    Successors according to CFG: BB#9 BB#10

1168B	BB#7: derived from LLVM BB %sw.bb
	    Predecessors according to CFG: BB#4
1184B		%vreg155<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg155
1200B		%vreg154<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg154
1216B		%vreg153<def> = LDRSWui %vreg154, 27; mem:LD4[%nblock] GPR64:%vreg153 GPR64common:%vreg154
1232B		%vreg148<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg148
1248B		%vreg147<def> = LDRXui %vreg148, 8; mem:LD8[%block] GPR64:%vreg147 GPR64common:%vreg148
1264B		%vreg145<def> = ADDXrr %vreg147, %vreg153; GPR64common:%vreg145 GPR64:%vreg147,%vreg153
1280B		STRBBui %vreg155, %vreg145, 0; mem:ST1[%arrayidx11] GPR32:%vreg155 GPR64common:%vreg145
1296B		%vreg140<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg140
1312B		%vreg139<def> = LDRWui %vreg140, 27; mem:LD4[%nblock12] GPR32common:%vreg139 GPR64common:%vreg140
1328B		%vreg138<def> = ADDWri %vreg139, 1, 0; GPR32common:%vreg138,%vreg139
1344B		STRWui %vreg138, %vreg140, 27; mem:ST4[%nblock12] GPR32common:%vreg138 GPR64common:%vreg140
1360B		B <BB#11>
	    Successors according to CFG: BB#11

1376B	BB#8: derived from LLVM BB %sw.bb.14
	    Predecessors according to CFG: BB#5
1392B		%vreg134<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg134
1408B		%vreg133<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg133
1424B		%vreg132<def> = LDRSWui %vreg133, 27; mem:LD4[%nblock15] GPR64:%vreg132 GPR64common:%vreg133
1440B		%vreg127<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg127
1456B		%vreg126<def> = LDRXui %vreg127, 8; mem:LD8[%block17] GPR64:%vreg126 GPR64common:%vreg127
1472B		%vreg124<def> = ADDXrr %vreg126, %vreg132; GPR64common:%vreg124 GPR64:%vreg126,%vreg132
1488B		STRBBui %vreg134, %vreg124, 0; mem:ST1[%arrayidx18] GPR32:%vreg134 GPR64common:%vreg124
1504B		%vreg119<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg119
1520B		%vreg118<def> = LDRWui %vreg119, 27; mem:LD4[%nblock19] GPR32common:%vreg118 GPR64common:%vreg119
1536B		%vreg117<def> = ADDWri %vreg118, 1, 0; GPR32common:%vreg117,%vreg118
1552B		STRWui %vreg117, %vreg119, 27; mem:ST4[%nblock19] GPR32common:%vreg117 GPR64common:%vreg119
1568B		%vreg113<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg113
1584B		%vreg112<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg112
1600B		%vreg111<def> = LDRSWui %vreg112, 27; mem:LD4[%nblock21] GPR64:%vreg111 GPR64common:%vreg112
1616B		%vreg106<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg106
1632B		%vreg105<def> = LDRXui %vreg106, 8; mem:LD8[%block23] GPR64:%vreg105 GPR64common:%vreg106
1648B		%vreg103<def> = ADDXrr %vreg105, %vreg111; GPR64common:%vreg103 GPR64:%vreg105,%vreg111
1664B		STRBBui %vreg113, %vreg103, 0; mem:ST1[%arrayidx24] GPR32:%vreg113 GPR64common:%vreg103
1680B		%vreg98<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg98
1696B		%vreg97<def> = LDRWui %vreg98, 27; mem:LD4[%nblock25] GPR32common:%vreg97 GPR64common:%vreg98
1712B		%vreg96<def> = ADDWri %vreg97, 1, 0; GPR32common:%vreg96,%vreg97
1728B		STRWui %vreg96, %vreg98, 27; mem:ST4[%nblock25] GPR32common:%vreg96 GPR64common:%vreg98
1744B		B <BB#11>
	    Successors according to CFG: BB#11

1760B	BB#9: derived from LLVM BB %sw.bb.27
	    Predecessors according to CFG: BB#6
1776B		%vreg92<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg92
1792B		%vreg91<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg91
1808B		%vreg90<def> = LDRSWui %vreg91, 27; mem:LD4[%nblock28] GPR64:%vreg90 GPR64common:%vreg91
1824B		%vreg85<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg85
1840B		%vreg84<def> = LDRXui %vreg85, 8; mem:LD8[%block30] GPR64:%vreg84 GPR64common:%vreg85
1856B		%vreg82<def> = ADDXrr %vreg84, %vreg90; GPR64common:%vreg82 GPR64:%vreg84,%vreg90
1872B		STRBBui %vreg92, %vreg82, 0; mem:ST1[%arrayidx31] GPR32:%vreg92 GPR64common:%vreg82
1888B		%vreg77<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg77
1904B		%vreg76<def> = LDRWui %vreg77, 27; mem:LD4[%nblock32] GPR32common:%vreg76 GPR64common:%vreg77
1920B		%vreg75<def> = ADDWri %vreg76, 1, 0; GPR32common:%vreg75,%vreg76
1936B		STRWui %vreg75, %vreg77, 27; mem:ST4[%nblock32] GPR32common:%vreg75 GPR64common:%vreg77
1952B		%vreg71<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg71
1968B		%vreg70<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg70
1984B		%vreg69<def> = LDRSWui %vreg70, 27; mem:LD4[%nblock34] GPR64:%vreg69 GPR64common:%vreg70
2000B		%vreg64<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg64
2016B		%vreg63<def> = LDRXui %vreg64, 8; mem:LD8[%block36] GPR64:%vreg63 GPR64common:%vreg64
2032B		%vreg61<def> = ADDXrr %vreg63, %vreg69; GPR64common:%vreg61 GPR64:%vreg63,%vreg69
2048B		STRBBui %vreg71, %vreg61, 0; mem:ST1[%arrayidx37] GPR32:%vreg71 GPR64common:%vreg61
2064B		%vreg56<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg56
2080B		%vreg55<def> = LDRWui %vreg56, 27; mem:LD4[%nblock38] GPR32common:%vreg55 GPR64common:%vreg56
2096B		%vreg54<def> = ADDWri %vreg55, 1, 0; GPR32common:%vreg54,%vreg55
2112B		STRWui %vreg54, %vreg56, 27; mem:ST4[%nblock38] GPR32common:%vreg54 GPR64common:%vreg56
2128B		%vreg50<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg50
2144B		%vreg49<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg49
2160B		%vreg48<def> = LDRSWui %vreg49, 27; mem:LD4[%nblock40] GPR64:%vreg48 GPR64common:%vreg49
2176B		%vreg43<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg43
2192B		%vreg42<def> = LDRXui %vreg43, 8; mem:LD8[%block42] GPR64:%vreg42 GPR64common:%vreg43
2208B		%vreg40<def> = ADDXrr %vreg42, %vreg48; GPR64common:%vreg40 GPR64:%vreg42,%vreg48
2224B		STRBBui %vreg50, %vreg40, 0; mem:ST1[%arrayidx43] GPR32:%vreg50 GPR64common:%vreg40
2240B		%vreg35<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg35
2256B		%vreg34<def> = LDRWui %vreg35, 27; mem:LD4[%nblock44] GPR32common:%vreg34 GPR64common:%vreg35
2272B		%vreg33<def> = ADDWri %vreg34, 1, 0; GPR32common:%vreg33,%vreg34
2288B		STRWui %vreg33, %vreg35, 27; mem:ST4[%nblock44] GPR32common:%vreg33 GPR64common:%vreg35
2304B		B <BB#11>
	    Successors according to CFG: BB#11

2320B	BB#10: derived from LLVM BB %sw.default
	    Predecessors according to CFG: BB#6
2336B		%vreg267<def> = MOVi32imm 1; GPR32:%vreg267
2352B		%vreg282<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg282
2368B		%vreg281<def> = LDRWui %vreg282, 24; mem:LD4[%state_in_len46] GPR32common:%vreg281 GPR64common:%vreg282
2384B		%vreg279<def> = SUBWri %vreg281, 4, 0; GPR32sp:%vreg279 GPR32common:%vreg281
2400B		%vreg276<def> = SUBREG_TO_REG 0, %vreg279, 15; GPR64:%vreg276 GPR32sp:%vreg279
2416B		%vreg277<def> = SBFMXri %vreg276, 0, 31; GPR64:%vreg277,%vreg276
2432B		%vreg274<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg274
2448B		%vreg273<def> = ADDXri %vreg274, 128, 0; GPR64common:%vreg273,%vreg274
2464B		%vreg271<def> = ADDXrr %vreg273, %vreg277; GPR64common:%vreg271,%vreg273 GPR64:%vreg277
2480B		STRBBui %vreg267, %vreg271, 0; mem:ST1[%arrayidx49] GPR32:%vreg267 GPR64common:%vreg271
2496B		%vreg266<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg266
2512B		%vreg265<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg265
2528B		%vreg264<def> = LDRSWui %vreg265, 27; mem:LD4[%nblock50] GPR64:%vreg264 GPR64common:%vreg265
2544B		%vreg259<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg259
2560B		%vreg258<def> = LDRXui %vreg259, 8; mem:LD8[%block52] GPR64:%vreg258 GPR64common:%vreg259
2576B		%vreg256<def> = ADDXrr %vreg258, %vreg264; GPR64common:%vreg256 GPR64:%vreg258,%vreg264
2592B		STRBBui %vreg266, %vreg256, 0; mem:ST1[%arrayidx53] GPR32:%vreg266 GPR64common:%vreg256
2608B		%vreg251<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg251
2624B		%vreg250<def> = LDRWui %vreg251, 27; mem:LD4[%nblock54] GPR32common:%vreg250 GPR64common:%vreg251
2640B		%vreg249<def> = ADDWri %vreg250, 1, 0; GPR32common:%vreg249,%vreg250
2656B		STRWui %vreg249, %vreg251, 27; mem:ST4[%nblock54] GPR32common:%vreg249 GPR64common:%vreg251
2672B		%vreg245<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg245
2688B		%vreg244<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg244
2704B		%vreg243<def> = LDRSWui %vreg244, 27; mem:LD4[%nblock56] GPR64:%vreg243 GPR64common:%vreg244
2720B		%vreg238<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg238
2736B		%vreg237<def> = LDRXui %vreg238, 8; mem:LD8[%block58] GPR64:%vreg237 GPR64common:%vreg238
2752B		%vreg235<def> = ADDXrr %vreg237, %vreg243; GPR64common:%vreg235 GPR64:%vreg237,%vreg243
2768B		STRBBui %vreg245, %vreg235, 0; mem:ST1[%arrayidx59] GPR32:%vreg245 GPR64common:%vreg235
2784B		%vreg230<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg230
2800B		%vreg229<def> = LDRWui %vreg230, 27; mem:LD4[%nblock60] GPR32common:%vreg229 GPR64common:%vreg230
2816B		%vreg228<def> = ADDWri %vreg229, 1, 0; GPR32common:%vreg228,%vreg229
2832B		STRWui %vreg228, %vreg230, 27; mem:ST4[%nblock60] GPR32common:%vreg228 GPR64common:%vreg230
2848B		%vreg224<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg224
2864B		%vreg223<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg223
2880B		%vreg222<def> = LDRSWui %vreg223, 27; mem:LD4[%nblock62] GPR64:%vreg222 GPR64common:%vreg223
2896B		%vreg217<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg217
2912B		%vreg216<def> = LDRXui %vreg217, 8; mem:LD8[%block64] GPR64:%vreg216 GPR64common:%vreg217
2928B		%vreg214<def> = ADDXrr %vreg216, %vreg222; GPR64common:%vreg214 GPR64:%vreg216,%vreg222
2944B		STRBBui %vreg224, %vreg214, 0; mem:ST1[%arrayidx65] GPR32:%vreg224 GPR64common:%vreg214
2960B		%vreg209<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg209
2976B		%vreg208<def> = LDRWui %vreg209, 27; mem:LD4[%nblock66] GPR32common:%vreg208 GPR64common:%vreg209
2992B		%vreg207<def> = ADDWri %vreg208, 1, 0; GPR32common:%vreg207,%vreg208
3008B		STRWui %vreg207, %vreg209, 27; mem:ST4[%nblock66] GPR32common:%vreg207 GPR64common:%vreg209
3024B		%vreg203<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg203
3040B		%vreg202<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg202
3056B		%vreg201<def> = LDRSWui %vreg202, 27; mem:LD4[%nblock68] GPR64:%vreg201 GPR64common:%vreg202
3072B		%vreg196<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg196
3088B		%vreg195<def> = LDRXui %vreg196, 8; mem:LD8[%block70] GPR64:%vreg195 GPR64common:%vreg196
3104B		%vreg193<def> = ADDXrr %vreg195, %vreg201; GPR64common:%vreg193 GPR64:%vreg195,%vreg201
3120B		STRBBui %vreg203, %vreg193, 0; mem:ST1[%arrayidx71] GPR32:%vreg203 GPR64common:%vreg193
3136B		%vreg188<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg188
3152B		%vreg187<def> = LDRWui %vreg188, 27; mem:LD4[%nblock72] GPR32common:%vreg187 GPR64common:%vreg188
3168B		%vreg186<def> = ADDWri %vreg187, 1, 0; GPR32common:%vreg186,%vreg187
3184B		STRWui %vreg186, %vreg188, 27; mem:ST4[%nblock72] GPR32common:%vreg186 GPR64common:%vreg188
3200B		%vreg182<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg182
3216B		%vreg181<def> = LDRWui %vreg182, 24; mem:LD4[%state_in_len74] GPR32common:%vreg181 GPR64common:%vreg182
3232B		%vreg179<def> = SUBWri %vreg181, 4, 0; GPR32sp:%vreg179 GPR32common:%vreg181
3248B		%vreg177<def> = COPY %vreg179; GPR32:%vreg177 GPR32sp:%vreg179
3264B		%vreg175<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg175
3280B		%vreg174<def> = LDRSWui %vreg175, 27; mem:LD4[%nblock77] GPR64:%vreg174 GPR64common:%vreg175
3296B		%vreg169<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg169
3312B		%vreg168<def> = LDRXui %vreg169, 8; mem:LD8[%block79] GPR64:%vreg168 GPR64common:%vreg169
3328B		%vreg166<def> = ADDXrr %vreg168, %vreg174; GPR64common:%vreg166 GPR64:%vreg168,%vreg174
3344B		STRBBui %vreg177, %vreg166, 0; mem:ST1[%arrayidx80] GPR32:%vreg177 GPR64common:%vreg166
3360B		%vreg161<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg161
3376B		%vreg160<def> = LDRWui %vreg161, 27; mem:LD4[%nblock81] GPR32common:%vreg160 GPR64common:%vreg161
3392B		%vreg159<def> = ADDWri %vreg160, 1, 0; GPR32common:%vreg159,%vreg160
3408B		STRWui %vreg159, %vreg161, 27; mem:ST4[%nblock81] GPR32common:%vreg159 GPR64common:%vreg161
	    Successors according to CFG: BB#11

3424B	BB#11: derived from LLVM BB %sw.epilog
	    Predecessors according to CFG: BB#9 BB#8 BB#7 BB#10
3440B		%vreg283<def> = ADRP <ga:@add_pair_to_block>[TF=1]; GPR64common:%vreg283
3456B		%vreg284<def> = ADDXri %vreg283, <ga:@add_pair_to_block>[TF=34], 0; GPR64sp:%vreg284 GPR64common:%vreg283
3472B		%vreg285<def> = COPY %vreg284; GPR64all:%vreg285 GPR64sp:%vreg284
3488B		%vreg286<def> = COPY %vreg12; GPR64all:%vreg286 GPR64:%vreg12
3504B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3520B		%X0<def> = COPY %vreg285; GPR64all:%vreg285
3536B		%X1<def> = COPY %vreg286; GPR64all:%vreg286
3552B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
3568B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3584B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3600B		STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...
3616B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3632B		RET_ReallyLR

# End machine code for function add_pair_to_block.

********** SIMPLE REGISTER COALESCING **********
********** Function: add_pair_to_block
********** JOINING INTERVALS ***********
for.cond:
for.body:
608B	%vreg302<def> = SUBREG_TO_REG 0, %vreg306, 15; GPR64:%vreg302 GPR32:%vreg306
	Considering merging to GPR64 with %vreg306 in %vreg302:sub_32
		RHS = %vreg306 [592r,608r:0)  0@592r
		LHS = %vreg302 [608r,624r:0)  0@608r
		merge %vreg302:0@608r into %vreg306:0@592r --> @592r
		erased:	608r	%vreg302<def> = SUBREG_TO_REG 0, %vreg306, 15; GPR64:%vreg302 GPR32:%vreg306
		updated: 592B	%vreg302:sub_32<def,read-undef> = EORWrr %vreg311, %vreg309; GPR64:%vreg302 GPR32:%vreg311,%vreg309
	Success: %vreg306:sub_32 -> %vreg302
	Result = %vreg302 [592r,624r:0)  0@592r
for.inc:
sw.epilog:
3520B	%X0<def> = COPY %vreg285; GPR64all:%vreg285
	Considering merging %vreg285 with %X0
	Can only merge into reserved registers.
3536B	%X1<def> = COPY %vreg286; GPR64all:%vreg286
	Considering merging %vreg286 with %X1
	Can only merge into reserved registers.
for.end:
880B	%vreg22<def> = SUBREG_TO_REG 0, %vreg21, 15; GPR64:%vreg22 GPR32:%vreg21
	Considering merging to GPR64 with %vreg21 in %vreg22:sub_32
		RHS = %vreg21 [864r,880r:0)  0@864r
		LHS = %vreg22 [880r,896r:0)  0@880r
		merge %vreg22:0@880r into %vreg21:0@864r --> @864r
		erased:	880r	%vreg22<def> = SUBREG_TO_REG 0, %vreg21, 15; GPR64:%vreg22 GPR32:%vreg21
		updated: 864B	%vreg22:sub_32<def,read-undef> = LDRWui %vreg20, 23; mem:LD4[%state_in_ch6] GPR64:%vreg22 GPR64common:%vreg20
	Success: %vreg21:sub_32 -> %vreg22
	Result = %vreg22 [864r,896r:0)  0@864r
for.end:
for.end:
sw.bb:
sw.bb.14:
sw.bb.27:
sw.default:
2400B	%vreg276<def> = SUBREG_TO_REG 0, %vreg279, 15; GPR64:%vreg276 GPR32sp:%vreg279
	Considering merging to GPR64common with %vreg279 in %vreg276:sub_32
		RHS = %vreg279 [2384r,2400r:0)  0@2384r
		LHS = %vreg276 [2400r,2416r:0)  0@2400r
		merge %vreg276:0@2400r into %vreg279:0@2384r --> @2384r
		erased:	2400r	%vreg276<def> = SUBREG_TO_REG 0, %vreg279, 15; GPR64:%vreg276 GPR32sp:%vreg279
		updated: 2384B	%vreg276:sub_32<def,read-undef> = SUBWri %vreg281, 4, 0; GPR64common:%vreg276 GPR32common:%vreg281
	Success: %vreg279:sub_32 -> %vreg276
	Result = %vreg276 [2384r,2416r:0)  0@2384r
entry:
16B	%vreg12<def> = COPY %LR; GPR64:%vreg12
	Considering merging %vreg12 with %LR
	Can only merge into reserved registers.
32B	%vreg0<def> = COPY %X0; GPR64:%vreg0
	Considering merging %vreg0 with %X0
	Can only merge into reserved registers.
144B	%X0<def> = COPY %vreg10; GPR64all:%vreg10
	Considering merging %vreg10 with %X0
	Can only merge into reserved registers.
160B	%X1<def> = COPY %vreg11; GPR64all:%vreg11
	Considering merging %vreg11 with %X1
	Can only merge into reserved registers.
3472B	%vreg285<def> = COPY %vreg284; GPR64all:%vreg285 GPR64sp:%vreg284
	Considering merging to GPR64sp with %vreg284 in %vreg285
		RHS = %vreg284 [3456r,3472r:0)  0@3456r
		LHS = %vreg285 [3472r,3520r:0)  0@3472r
		merge %vreg285:0@3472r into %vreg284:0@3456r --> @3456r
		erased:	3472r	%vreg285<def> = COPY %vreg284; GPR64all:%vreg285 GPR64sp:%vreg284
		updated: 3456B	%vreg285<def> = ADDXri %vreg283, <ga:@add_pair_to_block>[TF=34], 0; GPR64sp:%vreg285 GPR64common:%vreg283
	Success: %vreg284 -> %vreg285
	Result = %vreg285 [3456r,3520r:0)  0@3456r
3488B	%vreg286<def> = COPY %vreg12; GPR64all:%vreg286 GPR64:%vreg12
	Considering merging to GPR64 with %vreg12 in %vreg286
		RHS = %vreg12 [16r,3488r:0)  0@16r
		LHS = %vreg286 [3488r,3536r:0)  0@3488r
		merge %vreg286:0@3488r into %vreg12:0@16r --> @16r
		erased:	3488r	%vreg286<def> = COPY %vreg12; GPR64all:%vreg286 GPR64:%vreg12
		updated: 16B	%vreg286<def> = COPY %LR; GPR64:%vreg286
		updated: 112B	%vreg11<def> = COPY %vreg286; GPR64all:%vreg11 GPR64:%vreg286
	Success: %vreg12 -> %vreg286
	Result = %vreg286 [16r,3536r:0)  0@16r
976B	%vreg19<def> = COPY %vreg26; GPR32sp:%vreg19 GPR32common:%vreg26
	Considering merging to GPR32common with %vreg26 in %vreg19
		RHS = %vreg26 [960r,992r:0)  0@960r
		LHS = %vreg19 [976r,1120r:0)  0@976r
		merge %vreg19:0@976r into %vreg26:0@960r --> @960r
		erased:	976r	%vreg19<def> = COPY %vreg26; GPR32sp:%vreg19 GPR32common:%vreg26
		updated: 960B	%vreg19<def> = LDRWui %vreg25, 24; mem:LD4[%state_in_len9] GPR32common:%vreg19 GPR64common:%vreg25
		updated: 992B	%vreg27<def,dead> = SUBSWri %vreg19, 1, 0, %NZCV<imp-def>; GPR32:%vreg27 GPR32common:%vreg19
	Success: %vreg26 -> %vreg19
	Result = %vreg19 [960r,1120r:0)  0@960r
3248B	%vreg177<def> = COPY %vreg179; GPR32:%vreg177 GPR32sp:%vreg179
	Considering merging to GPR32common with %vreg179 in %vreg177
		RHS = %vreg179 [3232r,3248r:0)  0@3232r
		LHS = %vreg177 [3248r,3344r:0)  0@3248r
		merge %vreg177:0@3248r into %vreg179:0@3232r --> @3232r
		erased:	3248r	%vreg177<def> = COPY %vreg179; GPR32:%vreg177 GPR32sp:%vreg179
		updated: 3232B	%vreg177<def> = SUBWri %vreg181, 4, 0; GPR32common:%vreg177,%vreg181
	Success: %vreg179 -> %vreg177
	Result = %vreg177 [3232r,3344r:0)  0@3232r
48B	%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
	Considering merging to GPR64 with %vreg0 in %vreg1
		RHS = %vreg0 [32r,48r:0)  0@32r
		LHS = %vreg1 [48r,256r:0)  0@48r
		merge %vreg1:0@48r into %vreg0:0@32r --> @32r
		erased:	48r	%vreg1<def> = COPY %vreg0; GPR64:%vreg1,%vreg0
		updated: 32B	%vreg1<def> = COPY %X0; GPR64:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [32r,256r:0)  0@32r
96B	%vreg10<def> = COPY %vreg9; GPR64all:%vreg10 GPR64sp:%vreg9
	Considering merging to GPR64sp with %vreg9 in %vreg10
		RHS = %vreg9 [80r,96r:0)  0@80r
		LHS = %vreg10 [96r,144r:0)  0@96r
		merge %vreg10:0@96r into %vreg9:0@80r --> @80r
		erased:	96r	%vreg10<def> = COPY %vreg9; GPR64all:%vreg10 GPR64sp:%vreg9
		updated: 80B	%vreg10<def> = ADDXri %vreg8, <ga:@add_pair_to_block>[TF=34], 0; GPR64sp:%vreg10 GPR64common:%vreg8
	Success: %vreg9 -> %vreg10
	Result = %vreg10 [80r,144r:0)  0@80r
112B	%vreg11<def> = COPY %vreg286; GPR64all:%vreg11 GPR64:%vreg286
	Considering merging to GPR64 with %vreg286 in %vreg11
		RHS = %vreg286 [16r,3536r:0)  0@16r
		LHS = %vreg11 [112r,160r:0)  0@112r
		merge %vreg11:0@112r into %vreg286:0@16r --> @16r
		erased:	112r	%vreg11<def> = COPY %vreg286; GPR64all:%vreg11 GPR64:%vreg286
		updated: 16B	%vreg11<def> = COPY %LR; GPR64:%vreg11
		updated: 3536B	%X1<def> = COPY %vreg11; GPR64:%vreg11
	Success: %vreg286 -> %vreg11
	Result = %vreg11 [16r,3536r:0)  0@16r
304B	%vreg4<def> = COPY %vreg6; GPR32:%vreg4,%vreg6
	Considering merging to GPR32 with %vreg6 in %vreg4
		RHS = %vreg6 [288r,304r:0)  0@288r
		LHS = %vreg4 [304r,320r:0)  0@304r
		merge %vreg4:0@304r into %vreg6:0@288r --> @288r
		erased:	304r	%vreg4<def> = COPY %vreg6; GPR32:%vreg4,%vreg6
		updated: 288B	%vreg4<def> = LDRWui %vreg7, 23; mem:LD4[%state_in_ch] GPR32:%vreg4 GPR64common:%vreg7
	Success: %vreg6 -> %vreg4
	Result = %vreg4 [288r,320r:0)  0@288r
3520B	%X0<def> = COPY %vreg285; GPR64sp:%vreg285
	Considering merging %vreg285 with %X0
	Can only merge into reserved registers.
3536B	%X1<def> = COPY %vreg11; GPR64:%vreg11
	Considering merging %vreg11 with %X1
	Can only merge into reserved registers.
144B	%X0<def> = COPY %vreg10; GPR64sp:%vreg10
	Considering merging %vreg10 with %X0
	Can only merge into reserved registers.
160B	%X1<def> = COPY %vreg11; GPR64:%vreg11
	Considering merging %vreg11 with %X1
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
W30 [0B,16r:0)[176r,176d:4)[224e,224d:1)[3552r,3552d:2)[3600e,3600d:3)  0@0B-phi 1@224e 2@3552r 3@3600e 4@176r
W0 [0B,32r:0)[144r,176r:2)[3520r,3552r:1)  0@0B-phi 1@3520r 2@144r
%vreg1 [32r,256r:0)  0@32r
%vreg4 [288r,320r:0)  0@288r
%vreg7 [272r,288r:0)  0@272r
%vreg8 [64r,80r:0)  0@64r
%vreg10 [80r,144r:0)  0@80r
%vreg11 [16r,3536r:0)  0@16r
%vreg16 [400r,416r:0)  0@400r
%vreg17 [384r,400r:0)  0@384r
%vreg18 [368r,416r:0)  0@368r
%vreg19 [960r,1120r:0)  0@960r
%vreg20 [848r,896r:0)  0@848r
%vreg22 [864r,896r:0)  0@864r
%vreg23 [896r,928r:0)  0@896r
%vreg24 [912r,928r:0)  0@912r
%vreg25 [944r,960r:0)  0@944r
%vreg27 [992r,992d:0)  0@992r
%vreg28 [1056r,1056d:0)  0@1056r
%vreg29 [1120r,1120d:0)  0@1120r
%vreg33 [2272r,2288r:0)  0@2272r
%vreg34 [2256r,2272r:0)  0@2256r
%vreg35 [2240r,2288r:0)  0@2240r
%vreg40 [2208r,2224r:0)  0@2208r
%vreg42 [2192r,2208r:0)  0@2192r
%vreg43 [2176r,2192r:0)  0@2176r
%vreg48 [2160r,2208r:0)  0@2160r
%vreg49 [2144r,2160r:0)  0@2144r
%vreg50 [2128r,2224r:0)  0@2128r
%vreg54 [2096r,2112r:0)  0@2096r
%vreg55 [2080r,2096r:0)  0@2080r
%vreg56 [2064r,2112r:0)  0@2064r
%vreg61 [2032r,2048r:0)  0@2032r
%vreg63 [2016r,2032r:0)  0@2016r
%vreg64 [2000r,2016r:0)  0@2000r
%vreg69 [1984r,2032r:0)  0@1984r
%vreg70 [1968r,1984r:0)  0@1968r
%vreg71 [1952r,2048r:0)  0@1952r
%vreg75 [1920r,1936r:0)  0@1920r
%vreg76 [1904r,1920r:0)  0@1904r
%vreg77 [1888r,1936r:0)  0@1888r
%vreg82 [1856r,1872r:0)  0@1856r
%vreg84 [1840r,1856r:0)  0@1840r
%vreg85 [1824r,1840r:0)  0@1824r
%vreg90 [1808r,1856r:0)  0@1808r
%vreg91 [1792r,1808r:0)  0@1792r
%vreg92 [1776r,1872r:0)  0@1776r
%vreg96 [1712r,1728r:0)  0@1712r
%vreg97 [1696r,1712r:0)  0@1696r
%vreg98 [1680r,1728r:0)  0@1680r
%vreg103 [1648r,1664r:0)  0@1648r
%vreg105 [1632r,1648r:0)  0@1632r
%vreg106 [1616r,1632r:0)  0@1616r
%vreg111 [1600r,1648r:0)  0@1600r
%vreg112 [1584r,1600r:0)  0@1584r
%vreg113 [1568r,1664r:0)  0@1568r
%vreg117 [1536r,1552r:0)  0@1536r
%vreg118 [1520r,1536r:0)  0@1520r
%vreg119 [1504r,1552r:0)  0@1504r
%vreg124 [1472r,1488r:0)  0@1472r
%vreg126 [1456r,1472r:0)  0@1456r
%vreg127 [1440r,1456r:0)  0@1440r
%vreg132 [1424r,1472r:0)  0@1424r
%vreg133 [1408r,1424r:0)  0@1408r
%vreg134 [1392r,1488r:0)  0@1392r
%vreg138 [1328r,1344r:0)  0@1328r
%vreg139 [1312r,1328r:0)  0@1312r
%vreg140 [1296r,1344r:0)  0@1296r
%vreg145 [1264r,1280r:0)  0@1264r
%vreg147 [1248r,1264r:0)  0@1248r
%vreg148 [1232r,1248r:0)  0@1232r
%vreg153 [1216r,1264r:0)  0@1216r
%vreg154 [1200r,1216r:0)  0@1200r
%vreg155 [1184r,1280r:0)  0@1184r
%vreg159 [3392r,3408r:0)  0@3392r
%vreg160 [3376r,3392r:0)  0@3376r
%vreg161 [3360r,3408r:0)  0@3360r
%vreg166 [3328r,3344r:0)  0@3328r
%vreg168 [3312r,3328r:0)  0@3312r
%vreg169 [3296r,3312r:0)  0@3296r
%vreg174 [3280r,3328r:0)  0@3280r
%vreg175 [3264r,3280r:0)  0@3264r
%vreg177 [3232r,3344r:0)  0@3232r
%vreg181 [3216r,3232r:0)  0@3216r
%vreg182 [3200r,3216r:0)  0@3200r
%vreg186 [3168r,3184r:0)  0@3168r
%vreg187 [3152r,3168r:0)  0@3152r
%vreg188 [3136r,3184r:0)  0@3136r
%vreg193 [3104r,3120r:0)  0@3104r
%vreg195 [3088r,3104r:0)  0@3088r
%vreg196 [3072r,3088r:0)  0@3072r
%vreg201 [3056r,3104r:0)  0@3056r
%vreg202 [3040r,3056r:0)  0@3040r
%vreg203 [3024r,3120r:0)  0@3024r
%vreg207 [2992r,3008r:0)  0@2992r
%vreg208 [2976r,2992r:0)  0@2976r
%vreg209 [2960r,3008r:0)  0@2960r
%vreg214 [2928r,2944r:0)  0@2928r
%vreg216 [2912r,2928r:0)  0@2912r
%vreg217 [2896r,2912r:0)  0@2896r
%vreg222 [2880r,2928r:0)  0@2880r
%vreg223 [2864r,2880r:0)  0@2864r
%vreg224 [2848r,2944r:0)  0@2848r
%vreg228 [2816r,2832r:0)  0@2816r
%vreg229 [2800r,2816r:0)  0@2800r
%vreg230 [2784r,2832r:0)  0@2784r
%vreg235 [2752r,2768r:0)  0@2752r
%vreg237 [2736r,2752r:0)  0@2736r
%vreg238 [2720r,2736r:0)  0@2720r
%vreg243 [2704r,2752r:0)  0@2704r
%vreg244 [2688r,2704r:0)  0@2688r
%vreg245 [2672r,2768r:0)  0@2672r
%vreg249 [2640r,2656r:0)  0@2640r
%vreg250 [2624r,2640r:0)  0@2624r
%vreg251 [2608r,2656r:0)  0@2608r
%vreg256 [2576r,2592r:0)  0@2576r
%vreg258 [2560r,2576r:0)  0@2560r
%vreg259 [2544r,2560r:0)  0@2544r
%vreg264 [2528r,2576r:0)  0@2528r
%vreg265 [2512r,2528r:0)  0@2512r
%vreg266 [2496r,2592r:0)  0@2496r
%vreg267 [2336r,2480r:0)  0@2336r
%vreg271 [2464r,2480r:0)  0@2464r
%vreg273 [2448r,2464r:0)  0@2448r
%vreg274 [2432r,2448r:0)  0@2432r
%vreg276 [2384r,2416r:0)  0@2384r
%vreg277 [2416r,2464r:0)  0@2416r
%vreg281 [2368r,2384r:0)  0@2368r
%vreg282 [2352r,2368r:0)  0@2352r
%vreg283 [3440r,3456r:0)  0@3440r
%vreg285 [3456r,3520r:0)  0@3456r
%vreg289 [720r,736r:0)  0@720r
%vreg292 [704r,736r:0)  0@704r
%vreg294 [688r,704r:0)  0@688r
%vreg295 [464r,480r:0)  0@464r
%vreg296 [480r,672r:0)  0@480r
%vreg298 [640r,656r:0)  0@640r
%vreg299 [656r,672r:0)  0@656r
%vreg300 [672r,688r:0)  0@672r
%vreg302 [592r,624r:0)  0@592r
%vreg303 [624r,656r:0)  0@624r
%vreg309 [576r,592r:0)  0@576r
%vreg311 [560r,592r:0)  0@560r
%vreg313 [544r,560r:0)  0@544r
%vreg314 [528r,544r:0)  0@528r
%vreg316 [512r,704r:0)  0@512r
%vreg317 [496r,512r:0)  0@496r
%vreg320 [784r,800r:0)  0@784r
%vreg321 [768r,784r:0)  0@768r
RegMasks: 176r 3552r
********** MACHINEINSTRS **********
# Machine code for function add_pair_to_block: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
  fi#1: size=4, align=4, at location [SP]
  fi#2: size=1, align=1, at location [SP]
Function Live Ins: %X0 in %vreg0, %LR in %vreg12

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %LR
16B		%vreg11<def> = COPY %LR; GPR64:%vreg11
32B		%vreg1<def> = COPY %X0; GPR64:%vreg1
64B		%vreg8<def> = ADRP <ga:@add_pair_to_block>[TF=1]; GPR64common:%vreg8
80B		%vreg10<def> = ADDXri %vreg8, <ga:@add_pair_to_block>[TF=34], 0; GPR64sp:%vreg10 GPR64common:%vreg8
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		%X0<def> = COPY %vreg10; GPR64sp:%vreg10
160B		%X1<def> = COPY %vreg11; GPR64:%vreg11
176B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
224B		STACKMAP 0, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack1](align=4) LD8[FixedStack0] GPR64:%vreg1
240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
256B		STRXui %vreg1, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg1
272B		%vreg7<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg7
288B		%vreg4<def> = LDRWui %vreg7, 23; mem:LD4[%state_in_ch] GPR32:%vreg4 GPR64common:%vreg7
320B		STRBBui %vreg4, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg4
336B		STRWui %WZR, <fi#1>, 0; mem:ST4[FixedStack1]
	    Successors according to CFG: BB#1

352B	BB#1: derived from LLVM BB %for.cond
	    Predecessors according to CFG: BB#0 BB#3
368B		%vreg18<def> = LDRWui <fi#1>, 0; mem:LD4[FixedStack1] GPR32:%vreg18
384B		%vreg17<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg17
400B		%vreg16<def> = LDRWui %vreg17, 24; mem:LD4[%state_in_len] GPR32:%vreg16 GPR64common:%vreg17
416B		%WZR<def> = SUBSWrr %vreg18, %vreg16, %NZCV<imp-def>; GPR32:%vreg18,%vreg16
432B		Bcc 10, <BB#4>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#4 BB#2

448B	BB#2: derived from LLVM BB %for.body
	    Predecessors according to CFG: BB#1
464B		%vreg295<def> = ADRP <ga:@BZ2_crc32Table>[TF=1]; GPR64common:%vreg295
480B		%vreg296<def> = ADDXri %vreg295, <ga:@BZ2_crc32Table>[TF=34], 0; GPR64common:%vreg296,%vreg295
496B		%vreg317<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg317
512B		%vreg316<def> = LDRWui %vreg317, 162; mem:LD4[%blockCRC] GPR32:%vreg316 GPR64common:%vreg317
528B		%vreg314<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg314
544B		%vreg313<def> = LDRWui %vreg314, 162; mem:LD4[%blockCRC2] GPR32:%vreg313 GPR64common:%vreg314
560B		%vreg311<def> = UBFMWri %vreg313, 24, 31; GPR32:%vreg311,%vreg313
576B		%vreg309<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg309
592B		%vreg302:sub_32<def,read-undef> = EORWrr %vreg311, %vreg309; GPR64:%vreg302 GPR32:%vreg311,%vreg309
624B		%vreg303<def> = UBFMXri %vreg302, 0, 31; GPR64:%vreg303,%vreg302
640B		%vreg298<def> = MOVi64imm 4; GPR64:%vreg298
656B		%vreg299<def> = MADDXrrr %vreg303, %vreg298, %XZR; GPR64:%vreg299,%vreg303,%vreg298
672B		%vreg300<def> = ADDXrr %vreg296, %vreg299; GPR64common:%vreg300,%vreg296 GPR64:%vreg299
688B		%vreg294<def> = LDRWui %vreg300, 0; mem:LD4[%arrayidx] GPR32:%vreg294 GPR64common:%vreg300
704B		%vreg292<def> = EORWrs %vreg294, %vreg316, 8; GPR32:%vreg292,%vreg294,%vreg316
720B		%vreg289<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg289
736B		STRWui %vreg292, %vreg289, 162; mem:ST4[%blockCRC5] GPR32:%vreg292 GPR64common:%vreg289
	    Successors according to CFG: BB#3

752B	BB#3: derived from LLVM BB %for.inc
	    Predecessors according to CFG: BB#2
768B		%vreg321<def> = LDRWui <fi#1>, 0; mem:LD4[FixedStack1] GPR32common:%vreg321
784B		%vreg320<def> = ADDWri %vreg321, 1, 0; GPR32common:%vreg320,%vreg321
800B		STRWui %vreg320, <fi#1>, 0; mem:ST4[FixedStack1] GPR32common:%vreg320
816B		B <BB#1>
	    Successors according to CFG: BB#1

832B	BB#4: derived from LLVM BB %for.end
	    Predecessors according to CFG: BB#1
848B		%vreg20<def> = LDRXui <fi#0>, 0; mem:LD8[%s.addr] GPR64common:%vreg20
864B		%vreg22:sub_32<def,read-undef> = LDRWui %vreg20, 23; mem:LD4[%state_in_ch6] GPR64:%vreg22 GPR64common:%vreg20
896B		%vreg23<def> = ADDXrr %vreg20, %vreg22; GPR64common:%vreg23,%vreg20 GPR64:%vreg22
912B		%vreg24<def> = MOVi32imm 1; GPR32:%vreg24
928B		STRBBui %vreg24, %vreg23, 128; mem:ST1[%arrayidx8] GPR32:%vreg24 GPR64common:%vreg23
944B		%vreg25<def> = LDRXui <fi#0>, 0; mem:LD8[%s.addr] GPR64common:%vreg25
960B		%vreg19<def> = LDRWui %vreg25, 24; mem:LD4[%state_in_len9] GPR32common:%vreg19 GPR64common:%vreg25
992B		%vreg27<def,dead> = SUBSWri %vreg19, 1, 0, %NZCV<imp-def>; GPR32:%vreg27 GPR32common:%vreg19
1008B		Bcc 0, <BB#7>, %NZCV<imp-use,kill>
1024B		B <BB#5>
	    Successors according to CFG: BB#7 BB#5

1040B	BB#5: derived from LLVM BB %for.end
	    Predecessors according to CFG: BB#4
1056B		%vreg28<def,dead> = SUBSWri %vreg19, 2, 0, %NZCV<imp-def>; GPR32:%vreg28 GPR32common:%vreg19
1072B		Bcc 0, <BB#8>, %NZCV<imp-use,kill>
1088B		B <BB#6>
	    Successors according to CFG: BB#8 BB#6

1104B	BB#6: derived from LLVM BB %for.end
	    Predecessors according to CFG: BB#5
1120B		%vreg29<def,dead> = SUBSWri %vreg19, 3, 0, %NZCV<imp-def>; GPR32:%vreg29 GPR32common:%vreg19
1136B		Bcc 0, <BB#9>, %NZCV<imp-use,kill>
1152B		B <BB#10>
	    Successors according to CFG: BB#9 BB#10

1168B	BB#7: derived from LLVM BB %sw.bb
	    Predecessors according to CFG: BB#4
1184B		%vreg155<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg155
1200B		%vreg154<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg154
1216B		%vreg153<def> = LDRSWui %vreg154, 27; mem:LD4[%nblock] GPR64:%vreg153 GPR64common:%vreg154
1232B		%vreg148<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg148
1248B		%vreg147<def> = LDRXui %vreg148, 8; mem:LD8[%block] GPR64:%vreg147 GPR64common:%vreg148
1264B		%vreg145<def> = ADDXrr %vreg147, %vreg153; GPR64common:%vreg145 GPR64:%vreg147,%vreg153
1280B		STRBBui %vreg155, %vreg145, 0; mem:ST1[%arrayidx11] GPR32:%vreg155 GPR64common:%vreg145
1296B		%vreg140<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg140
1312B		%vreg139<def> = LDRWui %vreg140, 27; mem:LD4[%nblock12] GPR32common:%vreg139 GPR64common:%vreg140
1328B		%vreg138<def> = ADDWri %vreg139, 1, 0; GPR32common:%vreg138,%vreg139
1344B		STRWui %vreg138, %vreg140, 27; mem:ST4[%nblock12] GPR32common:%vreg138 GPR64common:%vreg140
1360B		B <BB#11>
	    Successors according to CFG: BB#11

1376B	BB#8: derived from LLVM BB %sw.bb.14
	    Predecessors according to CFG: BB#5
1392B		%vreg134<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg134
1408B		%vreg133<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg133
1424B		%vreg132<def> = LDRSWui %vreg133, 27; mem:LD4[%nblock15] GPR64:%vreg132 GPR64common:%vreg133
1440B		%vreg127<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg127
1456B		%vreg126<def> = LDRXui %vreg127, 8; mem:LD8[%block17] GPR64:%vreg126 GPR64common:%vreg127
1472B		%vreg124<def> = ADDXrr %vreg126, %vreg132; GPR64common:%vreg124 GPR64:%vreg126,%vreg132
1488B		STRBBui %vreg134, %vreg124, 0; mem:ST1[%arrayidx18] GPR32:%vreg134 GPR64common:%vreg124
1504B		%vreg119<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg119
1520B		%vreg118<def> = LDRWui %vreg119, 27; mem:LD4[%nblock19] GPR32common:%vreg118 GPR64common:%vreg119
1536B		%vreg117<def> = ADDWri %vreg118, 1, 0; GPR32common:%vreg117,%vreg118
1552B		STRWui %vreg117, %vreg119, 27; mem:ST4[%nblock19] GPR32common:%vreg117 GPR64common:%vreg119
1568B		%vreg113<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg113
1584B		%vreg112<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg112
1600B		%vreg111<def> = LDRSWui %vreg112, 27; mem:LD4[%nblock21] GPR64:%vreg111 GPR64common:%vreg112
1616B		%vreg106<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg106
1632B		%vreg105<def> = LDRXui %vreg106, 8; mem:LD8[%block23] GPR64:%vreg105 GPR64common:%vreg106
1648B		%vreg103<def> = ADDXrr %vreg105, %vreg111; GPR64common:%vreg103 GPR64:%vreg105,%vreg111
1664B		STRBBui %vreg113, %vreg103, 0; mem:ST1[%arrayidx24] GPR32:%vreg113 GPR64common:%vreg103
1680B		%vreg98<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg98
1696B		%vreg97<def> = LDRWui %vreg98, 27; mem:LD4[%nblock25] GPR32common:%vreg97 GPR64common:%vreg98
1712B		%vreg96<def> = ADDWri %vreg97, 1, 0; GPR32common:%vreg96,%vreg97
1728B		STRWui %vreg96, %vreg98, 27; mem:ST4[%nblock25] GPR32common:%vreg96 GPR64common:%vreg98
1744B		B <BB#11>
	    Successors according to CFG: BB#11

1760B	BB#9: derived from LLVM BB %sw.bb.27
	    Predecessors according to CFG: BB#6
1776B		%vreg92<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg92
1792B		%vreg91<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg91
1808B		%vreg90<def> = LDRSWui %vreg91, 27; mem:LD4[%nblock28] GPR64:%vreg90 GPR64common:%vreg91
1824B		%vreg85<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg85
1840B		%vreg84<def> = LDRXui %vreg85, 8; mem:LD8[%block30] GPR64:%vreg84 GPR64common:%vreg85
1856B		%vreg82<def> = ADDXrr %vreg84, %vreg90; GPR64common:%vreg82 GPR64:%vreg84,%vreg90
1872B		STRBBui %vreg92, %vreg82, 0; mem:ST1[%arrayidx31] GPR32:%vreg92 GPR64common:%vreg82
1888B		%vreg77<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg77
1904B		%vreg76<def> = LDRWui %vreg77, 27; mem:LD4[%nblock32] GPR32common:%vreg76 GPR64common:%vreg77
1920B		%vreg75<def> = ADDWri %vreg76, 1, 0; GPR32common:%vreg75,%vreg76
1936B		STRWui %vreg75, %vreg77, 27; mem:ST4[%nblock32] GPR32common:%vreg75 GPR64common:%vreg77
1952B		%vreg71<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg71
1968B		%vreg70<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg70
1984B		%vreg69<def> = LDRSWui %vreg70, 27; mem:LD4[%nblock34] GPR64:%vreg69 GPR64common:%vreg70
2000B		%vreg64<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg64
2016B		%vreg63<def> = LDRXui %vreg64, 8; mem:LD8[%block36] GPR64:%vreg63 GPR64common:%vreg64
2032B		%vreg61<def> = ADDXrr %vreg63, %vreg69; GPR64common:%vreg61 GPR64:%vreg63,%vreg69
2048B		STRBBui %vreg71, %vreg61, 0; mem:ST1[%arrayidx37] GPR32:%vreg71 GPR64common:%vreg61
2064B		%vreg56<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg56
2080B		%vreg55<def> = LDRWui %vreg56, 27; mem:LD4[%nblock38] GPR32common:%vreg55 GPR64common:%vreg56
2096B		%vreg54<def> = ADDWri %vreg55, 1, 0; GPR32common:%vreg54,%vreg55
2112B		STRWui %vreg54, %vreg56, 27; mem:ST4[%nblock38] GPR32common:%vreg54 GPR64common:%vreg56
2128B		%vreg50<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg50
2144B		%vreg49<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg49
2160B		%vreg48<def> = LDRSWui %vreg49, 27; mem:LD4[%nblock40] GPR64:%vreg48 GPR64common:%vreg49
2176B		%vreg43<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg43
2192B		%vreg42<def> = LDRXui %vreg43, 8; mem:LD8[%block42] GPR64:%vreg42 GPR64common:%vreg43
2208B		%vreg40<def> = ADDXrr %vreg42, %vreg48; GPR64common:%vreg40 GPR64:%vreg42,%vreg48
2224B		STRBBui %vreg50, %vreg40, 0; mem:ST1[%arrayidx43] GPR32:%vreg50 GPR64common:%vreg40
2240B		%vreg35<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg35
2256B		%vreg34<def> = LDRWui %vreg35, 27; mem:LD4[%nblock44] GPR32common:%vreg34 GPR64common:%vreg35
2272B		%vreg33<def> = ADDWri %vreg34, 1, 0; GPR32common:%vreg33,%vreg34
2288B		STRWui %vreg33, %vreg35, 27; mem:ST4[%nblock44] GPR32common:%vreg33 GPR64common:%vreg35
2304B		B <BB#11>
	    Successors according to CFG: BB#11

2320B	BB#10: derived from LLVM BB %sw.default
	    Predecessors according to CFG: BB#6
2336B		%vreg267<def> = MOVi32imm 1; GPR32:%vreg267
2352B		%vreg282<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg282
2368B		%vreg281<def> = LDRWui %vreg282, 24; mem:LD4[%state_in_len46] GPR32common:%vreg281 GPR64common:%vreg282
2384B		%vreg276:sub_32<def,read-undef> = SUBWri %vreg281, 4, 0; GPR64common:%vreg276 GPR32common:%vreg281
2416B		%vreg277<def> = SBFMXri %vreg276, 0, 31; GPR64:%vreg277 GPR64common:%vreg276
2432B		%vreg274<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg274
2448B		%vreg273<def> = ADDXri %vreg274, 128, 0; GPR64common:%vreg273,%vreg274
2464B		%vreg271<def> = ADDXrr %vreg273, %vreg277; GPR64common:%vreg271,%vreg273 GPR64:%vreg277
2480B		STRBBui %vreg267, %vreg271, 0; mem:ST1[%arrayidx49] GPR32:%vreg267 GPR64common:%vreg271
2496B		%vreg266<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg266
2512B		%vreg265<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg265
2528B		%vreg264<def> = LDRSWui %vreg265, 27; mem:LD4[%nblock50] GPR64:%vreg264 GPR64common:%vreg265
2544B		%vreg259<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg259
2560B		%vreg258<def> = LDRXui %vreg259, 8; mem:LD8[%block52] GPR64:%vreg258 GPR64common:%vreg259
2576B		%vreg256<def> = ADDXrr %vreg258, %vreg264; GPR64common:%vreg256 GPR64:%vreg258,%vreg264
2592B		STRBBui %vreg266, %vreg256, 0; mem:ST1[%arrayidx53] GPR32:%vreg266 GPR64common:%vreg256
2608B		%vreg251<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg251
2624B		%vreg250<def> = LDRWui %vreg251, 27; mem:LD4[%nblock54] GPR32common:%vreg250 GPR64common:%vreg251
2640B		%vreg249<def> = ADDWri %vreg250, 1, 0; GPR32common:%vreg249,%vreg250
2656B		STRWui %vreg249, %vreg251, 27; mem:ST4[%nblock54] GPR32common:%vreg249 GPR64common:%vreg251
2672B		%vreg245<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg245
2688B		%vreg244<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg244
2704B		%vreg243<def> = LDRSWui %vreg244, 27; mem:LD4[%nblock56] GPR64:%vreg243 GPR64common:%vreg244
2720B		%vreg238<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg238
2736B		%vreg237<def> = LDRXui %vreg238, 8; mem:LD8[%block58] GPR64:%vreg237 GPR64common:%vreg238
2752B		%vreg235<def> = ADDXrr %vreg237, %vreg243; GPR64common:%vreg235 GPR64:%vreg237,%vreg243
2768B		STRBBui %vreg245, %vreg235, 0; mem:ST1[%arrayidx59] GPR32:%vreg245 GPR64common:%vreg235
2784B		%vreg230<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg230
2800B		%vreg229<def> = LDRWui %vreg230, 27; mem:LD4[%nblock60] GPR32common:%vreg229 GPR64common:%vreg230
2816B		%vreg228<def> = ADDWri %vreg229, 1, 0; GPR32common:%vreg228,%vreg229
2832B		STRWui %vreg228, %vreg230, 27; mem:ST4[%nblock60] GPR32common:%vreg228 GPR64common:%vreg230
2848B		%vreg224<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg224
2864B		%vreg223<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg223
2880B		%vreg222<def> = LDRSWui %vreg223, 27; mem:LD4[%nblock62] GPR64:%vreg222 GPR64common:%vreg223
2896B		%vreg217<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg217
2912B		%vreg216<def> = LDRXui %vreg217, 8; mem:LD8[%block64] GPR64:%vreg216 GPR64common:%vreg217
2928B		%vreg214<def> = ADDXrr %vreg216, %vreg222; GPR64common:%vreg214 GPR64:%vreg216,%vreg222
2944B		STRBBui %vreg224, %vreg214, 0; mem:ST1[%arrayidx65] GPR32:%vreg224 GPR64common:%vreg214
2960B		%vreg209<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg209
2976B		%vreg208<def> = LDRWui %vreg209, 27; mem:LD4[%nblock66] GPR32common:%vreg208 GPR64common:%vreg209
2992B		%vreg207<def> = ADDWri %vreg208, 1, 0; GPR32common:%vreg207,%vreg208
3008B		STRWui %vreg207, %vreg209, 27; mem:ST4[%nblock66] GPR32common:%vreg207 GPR64common:%vreg209
3024B		%vreg203<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg203
3040B		%vreg202<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg202
3056B		%vreg201<def> = LDRSWui %vreg202, 27; mem:LD4[%nblock68] GPR64:%vreg201 GPR64common:%vreg202
3072B		%vreg196<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg196
3088B		%vreg195<def> = LDRXui %vreg196, 8; mem:LD8[%block70] GPR64:%vreg195 GPR64common:%vreg196
3104B		%vreg193<def> = ADDXrr %vreg195, %vreg201; GPR64common:%vreg193 GPR64:%vreg195,%vreg201
3120B		STRBBui %vreg203, %vreg193, 0; mem:ST1[%arrayidx71] GPR32:%vreg203 GPR64common:%vreg193
3136B		%vreg188<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg188
3152B		%vreg187<def> = LDRWui %vreg188, 27; mem:LD4[%nblock72] GPR32common:%vreg187 GPR64common:%vreg188
3168B		%vreg186<def> = ADDWri %vreg187, 1, 0; GPR32common:%vreg186,%vreg187
3184B		STRWui %vreg186, %vreg188, 27; mem:ST4[%nblock72] GPR32common:%vreg186 GPR64common:%vreg188
3200B		%vreg182<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg182
3216B		%vreg181<def> = LDRWui %vreg182, 24; mem:LD4[%state_in_len74] GPR32common:%vreg181 GPR64common:%vreg182
3232B		%vreg177<def> = SUBWri %vreg181, 4, 0; GPR32common:%vreg177,%vreg181
3264B		%vreg175<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg175
3280B		%vreg174<def> = LDRSWui %vreg175, 27; mem:LD4[%nblock77] GPR64:%vreg174 GPR64common:%vreg175
3296B		%vreg169<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg169
3312B		%vreg168<def> = LDRXui %vreg169, 8; mem:LD8[%block79] GPR64:%vreg168 GPR64common:%vreg169
3328B		%vreg166<def> = ADDXrr %vreg168, %vreg174; GPR64common:%vreg166 GPR64:%vreg168,%vreg174
3344B		STRBBui %vreg177, %vreg166, 0; mem:ST1[%arrayidx80] GPR32common:%vreg177 GPR64common:%vreg166
3360B		%vreg161<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg161
3376B		%vreg160<def> = LDRWui %vreg161, 27; mem:LD4[%nblock81] GPR32common:%vreg160 GPR64common:%vreg161
3392B		%vreg159<def> = ADDWri %vreg160, 1, 0; GPR32common:%vreg159,%vreg160
3408B		STRWui %vreg159, %vreg161, 27; mem:ST4[%nblock81] GPR32common:%vreg159 GPR64common:%vreg161
	    Successors according to CFG: BB#11

3424B	BB#11: derived from LLVM BB %sw.epilog
	    Predecessors according to CFG: BB#9 BB#8 BB#7 BB#10
3440B		%vreg283<def> = ADRP <ga:@add_pair_to_block>[TF=1]; GPR64common:%vreg283
3456B		%vreg285<def> = ADDXri %vreg283, <ga:@add_pair_to_block>[TF=34], 0; GPR64sp:%vreg285 GPR64common:%vreg283
3504B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3520B		%X0<def> = COPY %vreg285; GPR64sp:%vreg285
3536B		%X1<def> = COPY %vreg11; GPR64:%vreg11
3552B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
3568B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3584B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3600B		STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...
3616B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3632B		RET_ReallyLR

# End machine code for function add_pair_to_block.

handleMove 368B -> 392B: %vreg18<def> = LDRWui <fi#1>, 0; mem:LD4[FixedStack1] GPR32:%vreg18
     %vreg18:	[368r,416r:0)  0@368r
        -->	[392r,416r:0)  0@392r
AllocationOrder(GPR32sponly) = [ ]
handleMove 704B -> 728B: %vreg292<def> = EORWrs %vreg294, %vreg316, 8; GPR32:%vreg292,%vreg294,%vreg316
     %vreg292:	[704r,736r:0)  0@704r
        -->	[728r,736r:0)  0@728r
     %vreg294:	[688r,704r:0)  0@688r
        -->	[688r,728r:0)  0@688r
     %vreg316:	[512r,704r:0)  0@512r
        -->	[512r,728r:0)  0@512r
handleMove 560B -> 584B: %vreg311<def> = UBFMWri %vreg313, 24, 31; GPR32:%vreg311,%vreg313
     %vreg311:	[560r,592r:0)  0@560r
        -->	[584r,592r:0)  0@584r
     %vreg313:	[544r,560r:0)  0@544r
        -->	[544r,584r:0)  0@544r
handleMove 512B -> 580B: %vreg316<def> = LDRWui %vreg317, 162; mem:LD4[%blockCRC] GPR32:%vreg316 GPR64common:%vreg317
     %vreg316:	[512r,728r:0)  0@512r
        -->	[580r,728r:0)  0@580r
     %vreg317:	[496r,512r:0)  0@496r
        -->	[496r,580r:0)  0@496r
handleMove 480B -> 584B: %vreg296<def> = ADDXri %vreg295, <ga:@BZ2_crc32Table>[TF=34], 0; GPR64common:%vreg296,%vreg295
     %vreg296:	[480r,672r:0)  0@480r
        -->	[584r,672r:0)  0@584r
     %vreg295:	[464r,480r:0)  0@464r
        -->	[464r,584r:0)  0@464r
handleMove 496B -> 536B: %vreg317<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg317
     %vreg317:	[496r,592r:0)  0@496r
        -->	[536r,592r:0)  0@536r
handleMove 464B -> 532B: %vreg295<def> = ADRP <ga:@BZ2_crc32Table>[TF=1]; GPR64common:%vreg295
     %vreg295:	[464r,584r:0)  0@464r
        -->	[532r,584r:0)  0@532r
handleMove 1184B -> 1256B: %vreg155<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg155
     %vreg155:	[1184r,1280r:0)  0@1184r
        -->	[1256r,1280r:0)  0@1256r
handleMove 1216B -> 1240B: %vreg153<def> = LDRSWui %vreg154, 27; mem:LD4[%nblock] GPR64:%vreg153 GPR64common:%vreg154
     %vreg153:	[1216r,1264r:0)  0@1216r
        -->	[1240r,1264r:0)  0@1240r
     %vreg154:	[1200r,1216r:0)  0@1200r
        -->	[1200r,1240r:0)  0@1200r
AllocationOrder(GPR32sponly) = [ ]
handleMove 1568B -> 1640B: %vreg113<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg113
     %vreg113:	[1568r,1664r:0)  0@1568r
        -->	[1640r,1664r:0)  0@1640r
handleMove 1600B -> 1624B: %vreg111<def> = LDRSWui %vreg112, 27; mem:LD4[%nblock21] GPR64:%vreg111 GPR64common:%vreg112
     %vreg111:	[1600r,1648r:0)  0@1600r
        -->	[1624r,1648r:0)  0@1624r
     %vreg112:	[1584r,1600r:0)  0@1584r
        -->	[1584r,1624r:0)  0@1584r
handleMove 1392B -> 1464B: %vreg134<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg134
     %vreg134:	[1392r,1488r:0)  0@1392r
        -->	[1464r,1488r:0)  0@1464r
handleMove 1424B -> 1448B: %vreg132<def> = LDRSWui %vreg133, 27; mem:LD4[%nblock15] GPR64:%vreg132 GPR64common:%vreg133
     %vreg132:	[1424r,1472r:0)  0@1424r
        -->	[1448r,1472r:0)  0@1448r
     %vreg133:	[1408r,1424r:0)  0@1408r
        -->	[1408r,1448r:0)  0@1408r
AllocationOrder(GPR32sponly) = [ ]
handleMove 2128B -> 2200B: %vreg50<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg50
     %vreg50:	[2128r,2224r:0)  0@2128r
        -->	[2200r,2224r:0)  0@2200r
handleMove 2160B -> 2184B: %vreg48<def> = LDRSWui %vreg49, 27; mem:LD4[%nblock40] GPR64:%vreg48 GPR64common:%vreg49
     %vreg48:	[2160r,2208r:0)  0@2160r
        -->	[2184r,2208r:0)  0@2184r
     %vreg49:	[2144r,2160r:0)  0@2144r
        -->	[2144r,2184r:0)  0@2144r
handleMove 1952B -> 2024B: %vreg71<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg71
     %vreg71:	[1952r,2048r:0)  0@1952r
        -->	[2024r,2048r:0)  0@2024r
handleMove 1984B -> 2008B: %vreg69<def> = LDRSWui %vreg70, 27; mem:LD4[%nblock34] GPR64:%vreg69 GPR64common:%vreg70
     %vreg69:	[1984r,2032r:0)  0@1984r
        -->	[2008r,2032r:0)  0@2008r
     %vreg70:	[1968r,1984r:0)  0@1968r
        -->	[1968r,2008r:0)  0@1968r
handleMove 1776B -> 1848B: %vreg92<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg92
     %vreg92:	[1776r,1872r:0)  0@1776r
        -->	[1848r,1872r:0)  0@1848r
handleMove 1808B -> 1832B: %vreg90<def> = LDRSWui %vreg91, 27; mem:LD4[%nblock28] GPR64:%vreg90 GPR64common:%vreg91
     %vreg90:	[1808r,1856r:0)  0@1808r
        -->	[1832r,1856r:0)  0@1832r
     %vreg91:	[1792r,1808r:0)  0@1792r
        -->	[1792r,1832r:0)  0@1792r
AllocationOrder(GPR32sponly) = [ ]
handleMove 3232B -> 3320B: %vreg177<def> = SUBWri %vreg181, 4, 0; GPR32common:%vreg177,%vreg181
     %vreg177:	[3232r,3344r:0)  0@3232r
        -->	[3320r,3344r:0)  0@3320r
     %vreg181:	[3216r,3232r:0)  0@3216r
        -->	[3216r,3320r:0)  0@3216r
handleMove 3280B -> 3304B: %vreg174<def> = LDRSWui %vreg175, 27; mem:LD4[%nblock77] GPR64:%vreg174 GPR64common:%vreg175
     %vreg174:	[3280r,3328r:0)  0@3280r
        -->	[3304r,3328r:0)  0@3304r
     %vreg175:	[3264r,3280r:0)  0@3264r
        -->	[3264r,3304r:0)  0@3264r
handleMove 3216B -> 3300B: %vreg181<def> = LDRWui %vreg182, 24; mem:LD4[%state_in_len74] GPR32common:%vreg181 GPR64common:%vreg182
     %vreg181:	[3216r,3320r:0)  0@3216r
        -->	[3300r,3320r:0)  0@3300r
     %vreg182:	[3200r,3216r:0)  0@3200r
        -->	[3200r,3300r:0)  0@3200r
handleMove 3024B -> 3096B: %vreg203<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg203
     %vreg203:	[3024r,3120r:0)  0@3024r
        -->	[3096r,3120r:0)  0@3096r
handleMove 3056B -> 3080B: %vreg201<def> = LDRSWui %vreg202, 27; mem:LD4[%nblock68] GPR64:%vreg201 GPR64common:%vreg202
     %vreg201:	[3056r,3104r:0)  0@3056r
        -->	[3080r,3104r:0)  0@3080r
     %vreg202:	[3040r,3056r:0)  0@3040r
        -->	[3040r,3080r:0)  0@3040r
handleMove 2848B -> 2920B: %vreg224<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg224
     %vreg224:	[2848r,2944r:0)  0@2848r
        -->	[2920r,2944r:0)  0@2920r
handleMove 2880B -> 2904B: %vreg222<def> = LDRSWui %vreg223, 27; mem:LD4[%nblock62] GPR64:%vreg222 GPR64common:%vreg223
     %vreg222:	[2880r,2928r:0)  0@2880r
        -->	[2904r,2928r:0)  0@2904r
     %vreg223:	[2864r,2880r:0)  0@2864r
        -->	[2864r,2904r:0)  0@2864r
handleMove 2672B -> 2744B: %vreg245<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg245
     %vreg245:	[2672r,2768r:0)  0@2672r
        -->	[2744r,2768r:0)  0@2744r
handleMove 2704B -> 2728B: %vreg243<def> = LDRSWui %vreg244, 27; mem:LD4[%nblock56] GPR64:%vreg243 GPR64common:%vreg244
     %vreg243:	[2704r,2752r:0)  0@2704r
        -->	[2728r,2752r:0)  0@2728r
     %vreg244:	[2688r,2704r:0)  0@2688r
        -->	[2688r,2728r:0)  0@2688r
handleMove 2496B -> 2568B: %vreg266<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg266
     %vreg266:	[2496r,2592r:0)  0@2496r
        -->	[2568r,2592r:0)  0@2568r
handleMove 2528B -> 2552B: %vreg264<def> = LDRSWui %vreg265, 27; mem:LD4[%nblock50] GPR64:%vreg264 GPR64common:%vreg265
     %vreg264:	[2528r,2576r:0)  0@2528r
        -->	[2552r,2576r:0)  0@2552r
     %vreg265:	[2512r,2528r:0)  0@2512r
        -->	[2512r,2552r:0)  0@2512r
handleMove 2416B -> 2456B: %vreg277<def> = SBFMXri %vreg276, 0, 31; GPR64:%vreg277 GPR64common:%vreg276
     %vreg277:	[2416r,2464r:0)  0@2416r
        -->	[2456r,2464r:0)  0@2456r
     %vreg276:	[2384r,2416r:0)  0@2384r
        -->	[2384r,2456r:0)  0@2384r
handleMove 2384B -> 2452B: %vreg276:sub_32<def,read-undef> = SUBWri %vreg281, 4, 0; GPR64common:%vreg276 GPR32common:%vreg281
     %vreg276:	[2384r,2456r:0)  0@2384r
        -->	[2452r,2456r:0)  0@2452r
     %vreg281:	[2368r,2384r:0)  0@2368r
        -->	[2368r,2452r:0)  0@2368r
handleMove 2336B -> 2440B: %vreg267<def> = MOVi32imm 1; GPR32:%vreg267
     %vreg267:	[2336r,2480r:0)  0@2336r
        -->	[2440r,2480r:0)  0@2440r
handleMove 2368B -> 2436B: %vreg281<def> = LDRWui %vreg282, 24; mem:LD4[%state_in_len46] GPR32common:%vreg281 GPR64common:%vreg282
     %vreg281:	[2368r,2452r:0)  0@2368r
        -->	[2436r,2452r:0)  0@2436r
     %vreg282:	[2352r,2368r:0)  0@2352r
        -->	[2352r,2436r:0)  0@2352r
********** GREEDY REGISTER ALLOCATION **********
********** Function: add_pair_to_block
********** INTERVALS **********
W30 [0B,16r:0)[176r,176d:4)[224e,224d:1)[3552r,3552d:2)[3600e,3600d:3)  0@0B-phi 1@224e 2@3552r 3@3600e 4@176r
W0 [0B,32r:0)[144r,176r:2)[3520r,3552r:1)  0@0B-phi 1@3520r 2@144r
%vreg1 [32r,256r:0)  0@32r
%vreg4 [288r,320r:0)  0@288r
%vreg7 [272r,288r:0)  0@272r
%vreg8 [64r,80r:0)  0@64r
%vreg10 [80r,144r:0)  0@80r
%vreg11 [16r,3536r:0)  0@16r
%vreg16 [400r,416r:0)  0@400r
%vreg17 [384r,400r:0)  0@384r
%vreg18 [392r,416r:0)  0@392r
%vreg19 [960r,1120r:0)  0@960r
%vreg20 [848r,896r:0)  0@848r
%vreg22 [864r,896r:0)  0@864r
%vreg23 [896r,928r:0)  0@896r
%vreg24 [912r,928r:0)  0@912r
%vreg25 [944r,960r:0)  0@944r
%vreg27 [992r,992d:0)  0@992r
%vreg28 [1056r,1056d:0)  0@1056r
%vreg29 [1120r,1120d:0)  0@1120r
%vreg33 [2272r,2288r:0)  0@2272r
%vreg34 [2256r,2272r:0)  0@2256r
%vreg35 [2240r,2288r:0)  0@2240r
%vreg40 [2208r,2224r:0)  0@2208r
%vreg42 [2192r,2208r:0)  0@2192r
%vreg43 [2176r,2192r:0)  0@2176r
%vreg48 [2184r,2208r:0)  0@2184r
%vreg49 [2144r,2184r:0)  0@2144r
%vreg50 [2200r,2224r:0)  0@2200r
%vreg54 [2096r,2112r:0)  0@2096r
%vreg55 [2080r,2096r:0)  0@2080r
%vreg56 [2064r,2112r:0)  0@2064r
%vreg61 [2032r,2048r:0)  0@2032r
%vreg63 [2016r,2032r:0)  0@2016r
%vreg64 [2000r,2016r:0)  0@2000r
%vreg69 [2008r,2032r:0)  0@2008r
%vreg70 [1968r,2008r:0)  0@1968r
%vreg71 [2024r,2048r:0)  0@2024r
%vreg75 [1920r,1936r:0)  0@1920r
%vreg76 [1904r,1920r:0)  0@1904r
%vreg77 [1888r,1936r:0)  0@1888r
%vreg82 [1856r,1872r:0)  0@1856r
%vreg84 [1840r,1856r:0)  0@1840r
%vreg85 [1824r,1840r:0)  0@1824r
%vreg90 [1832r,1856r:0)  0@1832r
%vreg91 [1792r,1832r:0)  0@1792r
%vreg92 [1848r,1872r:0)  0@1848r
%vreg96 [1712r,1728r:0)  0@1712r
%vreg97 [1696r,1712r:0)  0@1696r
%vreg98 [1680r,1728r:0)  0@1680r
%vreg103 [1648r,1664r:0)  0@1648r
%vreg105 [1632r,1648r:0)  0@1632r
%vreg106 [1616r,1632r:0)  0@1616r
%vreg111 [1624r,1648r:0)  0@1624r
%vreg112 [1584r,1624r:0)  0@1584r
%vreg113 [1640r,1664r:0)  0@1640r
%vreg117 [1536r,1552r:0)  0@1536r
%vreg118 [1520r,1536r:0)  0@1520r
%vreg119 [1504r,1552r:0)  0@1504r
%vreg124 [1472r,1488r:0)  0@1472r
%vreg126 [1456r,1472r:0)  0@1456r
%vreg127 [1440r,1456r:0)  0@1440r
%vreg132 [1448r,1472r:0)  0@1448r
%vreg133 [1408r,1448r:0)  0@1408r
%vreg134 [1464r,1488r:0)  0@1464r
%vreg138 [1328r,1344r:0)  0@1328r
%vreg139 [1312r,1328r:0)  0@1312r
%vreg140 [1296r,1344r:0)  0@1296r
%vreg145 [1264r,1280r:0)  0@1264r
%vreg147 [1248r,1264r:0)  0@1248r
%vreg148 [1232r,1248r:0)  0@1232r
%vreg153 [1240r,1264r:0)  0@1240r
%vreg154 [1200r,1240r:0)  0@1200r
%vreg155 [1256r,1280r:0)  0@1256r
%vreg159 [3392r,3408r:0)  0@3392r
%vreg160 [3376r,3392r:0)  0@3376r
%vreg161 [3360r,3408r:0)  0@3360r
%vreg166 [3328r,3344r:0)  0@3328r
%vreg168 [3312r,3328r:0)  0@3312r
%vreg169 [3296r,3312r:0)  0@3296r
%vreg174 [3304r,3328r:0)  0@3304r
%vreg175 [3264r,3304r:0)  0@3264r
%vreg177 [3320r,3344r:0)  0@3320r
%vreg181 [3300r,3320r:0)  0@3300r
%vreg182 [3200r,3300r:0)  0@3200r
%vreg186 [3168r,3184r:0)  0@3168r
%vreg187 [3152r,3168r:0)  0@3152r
%vreg188 [3136r,3184r:0)  0@3136r
%vreg193 [3104r,3120r:0)  0@3104r
%vreg195 [3088r,3104r:0)  0@3088r
%vreg196 [3072r,3088r:0)  0@3072r
%vreg201 [3080r,3104r:0)  0@3080r
%vreg202 [3040r,3080r:0)  0@3040r
%vreg203 [3096r,3120r:0)  0@3096r
%vreg207 [2992r,3008r:0)  0@2992r
%vreg208 [2976r,2992r:0)  0@2976r
%vreg209 [2960r,3008r:0)  0@2960r
%vreg214 [2928r,2944r:0)  0@2928r
%vreg216 [2912r,2928r:0)  0@2912r
%vreg217 [2896r,2912r:0)  0@2896r
%vreg222 [2904r,2928r:0)  0@2904r
%vreg223 [2864r,2904r:0)  0@2864r
%vreg224 [2920r,2944r:0)  0@2920r
%vreg228 [2816r,2832r:0)  0@2816r
%vreg229 [2800r,2816r:0)  0@2800r
%vreg230 [2784r,2832r:0)  0@2784r
%vreg235 [2752r,2768r:0)  0@2752r
%vreg237 [2736r,2752r:0)  0@2736r
%vreg238 [2720r,2736r:0)  0@2720r
%vreg243 [2728r,2752r:0)  0@2728r
%vreg244 [2688r,2728r:0)  0@2688r
%vreg245 [2744r,2768r:0)  0@2744r
%vreg249 [2640r,2656r:0)  0@2640r
%vreg250 [2624r,2640r:0)  0@2624r
%vreg251 [2608r,2656r:0)  0@2608r
%vreg256 [2576r,2592r:0)  0@2576r
%vreg258 [2560r,2576r:0)  0@2560r
%vreg259 [2544r,2560r:0)  0@2544r
%vreg264 [2552r,2576r:0)  0@2552r
%vreg265 [2512r,2552r:0)  0@2512r
%vreg266 [2568r,2592r:0)  0@2568r
%vreg267 [2440r,2480r:0)  0@2440r
%vreg271 [2464r,2480r:0)  0@2464r
%vreg273 [2448r,2464r:0)  0@2448r
%vreg274 [2432r,2448r:0)  0@2432r
%vreg276 [2452r,2456r:0)  0@2452r
%vreg277 [2456r,2464r:0)  0@2456r
%vreg281 [2436r,2452r:0)  0@2436r
%vreg282 [2352r,2436r:0)  0@2352r
%vreg283 [3440r,3456r:0)  0@3440r
%vreg285 [3456r,3520r:0)  0@3456r
%vreg289 [720r,736r:0)  0@720r
%vreg292 [728r,736r:0)  0@728r
%vreg294 [688r,728r:0)  0@688r
%vreg295 [532r,584r:0)  0@532r
%vreg296 [584r,672r:0)  0@584r
%vreg298 [640r,656r:0)  0@640r
%vreg299 [656r,672r:0)  0@656r
%vreg300 [672r,688r:0)  0@672r
%vreg302 [608r,624r:0)  0@608r
%vreg303 [624r,656r:0)  0@624r
%vreg309 [576r,608r:0)  0@576r
%vreg311 [600r,608r:0)  0@600r
%vreg313 [544r,600r:0)  0@544r
%vreg314 [528r,544r:0)  0@528r
%vreg316 [592r,728r:0)  0@592r
%vreg317 [536r,592r:0)  0@536r
%vreg320 [784r,800r:0)  0@784r
%vreg321 [768r,784r:0)  0@768r
RegMasks: 176r 3552r
********** MACHINEINSTRS **********
# Machine code for function add_pair_to_block: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
  fi#1: size=4, align=4, at location [SP]
  fi#2: size=1, align=1, at location [SP]
Function Live Ins: %X0 in %vreg0, %LR in %vreg12

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %X0 %LR
16B		%vreg11<def> = COPY %LR; GPR64:%vreg11
32B		%vreg1<def> = COPY %X0; GPR64:%vreg1
64B		%vreg8<def> = ADRP <ga:@add_pair_to_block>[TF=1]; GPR64common:%vreg8
80B		%vreg10<def> = ADDXri %vreg8, <ga:@add_pair_to_block>[TF=34], 0; GPR64sp:%vreg10 GPR64common:%vreg8
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		%X0<def> = COPY %vreg10; GPR64sp:%vreg10
160B		%X1<def> = COPY %vreg11; GPR64:%vreg11
176B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
224B		STACKMAP 0, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack1](align=4) LD8[FixedStack0] GPR64:%vreg1
240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
256B		STRXui %vreg1, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg1
272B		%vreg7<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg7
288B		%vreg4<def> = LDRWui %vreg7, 23; mem:LD4[%state_in_ch] GPR32:%vreg4 GPR64common:%vreg7
320B		STRBBui %vreg4, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg4
336B		STRWui %WZR, <fi#1>, 0; mem:ST4[FixedStack1]
	    Successors according to CFG: BB#1

352B	BB#1: derived from LLVM BB %for.cond
	    Predecessors according to CFG: BB#0 BB#3
384B		%vreg17<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg17
392B		%vreg18<def> = LDRWui <fi#1>, 0; mem:LD4[FixedStack1] GPR32:%vreg18
400B		%vreg16<def> = LDRWui %vreg17, 24; mem:LD4[%state_in_len] GPR32:%vreg16 GPR64common:%vreg17
416B		%WZR<def> = SUBSWrr %vreg18, %vreg16, %NZCV<imp-def>; GPR32:%vreg18,%vreg16
432B		Bcc 10, <BB#4>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#4 BB#2

448B	BB#2: derived from LLVM BB %for.body
	    Predecessors according to CFG: BB#1
528B		%vreg314<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg314
532B		%vreg295<def> = ADRP <ga:@BZ2_crc32Table>[TF=1]; GPR64common:%vreg295
536B		%vreg317<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg317
544B		%vreg313<def> = LDRWui %vreg314, 162; mem:LD4[%blockCRC2] GPR32:%vreg313 GPR64common:%vreg314
576B		%vreg309<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg309
584B		%vreg296<def> = ADDXri %vreg295, <ga:@BZ2_crc32Table>[TF=34], 0; GPR64common:%vreg296,%vreg295
592B		%vreg316<def> = LDRWui %vreg317, 162; mem:LD4[%blockCRC] GPR32:%vreg316 GPR64common:%vreg317
600B		%vreg311<def> = UBFMWri %vreg313, 24, 31; GPR32:%vreg311,%vreg313
608B		%vreg302:sub_32<def,read-undef> = EORWrr %vreg311, %vreg309; GPR64:%vreg302 GPR32:%vreg311,%vreg309
624B		%vreg303<def> = UBFMXri %vreg302, 0, 31; GPR64:%vreg303,%vreg302
640B		%vreg298<def> = MOVi64imm 4; GPR64:%vreg298
656B		%vreg299<def> = MADDXrrr %vreg303, %vreg298, %XZR; GPR64:%vreg299,%vreg303,%vreg298
672B		%vreg300<def> = ADDXrr %vreg296, %vreg299; GPR64common:%vreg300,%vreg296 GPR64:%vreg299
688B		%vreg294<def> = LDRWui %vreg300, 0; mem:LD4[%arrayidx] GPR32:%vreg294 GPR64common:%vreg300
720B		%vreg289<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg289
728B		%vreg292<def> = EORWrs %vreg294, %vreg316, 8; GPR32:%vreg292,%vreg294,%vreg316
736B		STRWui %vreg292, %vreg289, 162; mem:ST4[%blockCRC5] GPR32:%vreg292 GPR64common:%vreg289
	    Successors according to CFG: BB#3

752B	BB#3: derived from LLVM BB %for.inc
	    Predecessors according to CFG: BB#2
768B		%vreg321<def> = LDRWui <fi#1>, 0; mem:LD4[FixedStack1] GPR32common:%vreg321
784B		%vreg320<def> = ADDWri %vreg321, 1, 0; GPR32common:%vreg320,%vreg321
800B		STRWui %vreg320, <fi#1>, 0; mem:ST4[FixedStack1] GPR32common:%vreg320
816B		B <BB#1>
	    Successors according to CFG: BB#1

832B	BB#4: derived from LLVM BB %for.end
	    Predecessors according to CFG: BB#1
848B		%vreg20<def> = LDRXui <fi#0>, 0; mem:LD8[%s.addr] GPR64common:%vreg20
864B		%vreg22:sub_32<def,read-undef> = LDRWui %vreg20, 23; mem:LD4[%state_in_ch6] GPR64:%vreg22 GPR64common:%vreg20
896B		%vreg23<def> = ADDXrr %vreg20, %vreg22; GPR64common:%vreg23,%vreg20 GPR64:%vreg22
912B		%vreg24<def> = MOVi32imm 1; GPR32:%vreg24
928B		STRBBui %vreg24, %vreg23, 128; mem:ST1[%arrayidx8] GPR32:%vreg24 GPR64common:%vreg23
944B		%vreg25<def> = LDRXui <fi#0>, 0; mem:LD8[%s.addr] GPR64common:%vreg25
960B		%vreg19<def> = LDRWui %vreg25, 24; mem:LD4[%state_in_len9] GPR32common:%vreg19 GPR64common:%vreg25
992B		%vreg27<def,dead> = SUBSWri %vreg19, 1, 0, %NZCV<imp-def>; GPR32:%vreg27 GPR32common:%vreg19
1008B		Bcc 0, <BB#7>, %NZCV<imp-use,kill>
1024B		B <BB#5>
	    Successors according to CFG: BB#7 BB#5

1040B	BB#5: derived from LLVM BB %for.end
	    Predecessors according to CFG: BB#4
1056B		%vreg28<def,dead> = SUBSWri %vreg19, 2, 0, %NZCV<imp-def>; GPR32:%vreg28 GPR32common:%vreg19
1072B		Bcc 0, <BB#8>, %NZCV<imp-use,kill>
1088B		B <BB#6>
	    Successors according to CFG: BB#8 BB#6

1104B	BB#6: derived from LLVM BB %for.end
	    Predecessors according to CFG: BB#5
1120B		%vreg29<def,dead> = SUBSWri %vreg19, 3, 0, %NZCV<imp-def>; GPR32:%vreg29 GPR32common:%vreg19
1136B		Bcc 0, <BB#9>, %NZCV<imp-use,kill>
1152B		B <BB#10>
	    Successors according to CFG: BB#9 BB#10

1168B	BB#7: derived from LLVM BB %sw.bb
	    Predecessors according to CFG: BB#4
1200B		%vreg154<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg154
1232B		%vreg148<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg148
1240B		%vreg153<def> = LDRSWui %vreg154, 27; mem:LD4[%nblock] GPR64:%vreg153 GPR64common:%vreg154
1248B		%vreg147<def> = LDRXui %vreg148, 8; mem:LD8[%block] GPR64:%vreg147 GPR64common:%vreg148
1256B		%vreg155<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg155
1264B		%vreg145<def> = ADDXrr %vreg147, %vreg153; GPR64common:%vreg145 GPR64:%vreg147,%vreg153
1280B		STRBBui %vreg155, %vreg145, 0; mem:ST1[%arrayidx11] GPR32:%vreg155 GPR64common:%vreg145
1296B		%vreg140<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg140
1312B		%vreg139<def> = LDRWui %vreg140, 27; mem:LD4[%nblock12] GPR32common:%vreg139 GPR64common:%vreg140
1328B		%vreg138<def> = ADDWri %vreg139, 1, 0; GPR32common:%vreg138,%vreg139
1344B		STRWui %vreg138, %vreg140, 27; mem:ST4[%nblock12] GPR32common:%vreg138 GPR64common:%vreg140
1360B		B <BB#11>
	    Successors according to CFG: BB#11

1376B	BB#8: derived from LLVM BB %sw.bb.14
	    Predecessors according to CFG: BB#5
1408B		%vreg133<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg133
1440B		%vreg127<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg127
1448B		%vreg132<def> = LDRSWui %vreg133, 27; mem:LD4[%nblock15] GPR64:%vreg132 GPR64common:%vreg133
1456B		%vreg126<def> = LDRXui %vreg127, 8; mem:LD8[%block17] GPR64:%vreg126 GPR64common:%vreg127
1464B		%vreg134<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg134
1472B		%vreg124<def> = ADDXrr %vreg126, %vreg132; GPR64common:%vreg124 GPR64:%vreg126,%vreg132
1488B		STRBBui %vreg134, %vreg124, 0; mem:ST1[%arrayidx18] GPR32:%vreg134 GPR64common:%vreg124
1504B		%vreg119<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg119
1520B		%vreg118<def> = LDRWui %vreg119, 27; mem:LD4[%nblock19] GPR32common:%vreg118 GPR64common:%vreg119
1536B		%vreg117<def> = ADDWri %vreg118, 1, 0; GPR32common:%vreg117,%vreg118
1552B		STRWui %vreg117, %vreg119, 27; mem:ST4[%nblock19] GPR32common:%vreg117 GPR64common:%vreg119
1584B		%vreg112<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg112
1616B		%vreg106<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg106
1624B		%vreg111<def> = LDRSWui %vreg112, 27; mem:LD4[%nblock21] GPR64:%vreg111 GPR64common:%vreg112
1632B		%vreg105<def> = LDRXui %vreg106, 8; mem:LD8[%block23] GPR64:%vreg105 GPR64common:%vreg106
1640B		%vreg113<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg113
1648B		%vreg103<def> = ADDXrr %vreg105, %vreg111; GPR64common:%vreg103 GPR64:%vreg105,%vreg111
1664B		STRBBui %vreg113, %vreg103, 0; mem:ST1[%arrayidx24] GPR32:%vreg113 GPR64common:%vreg103
1680B		%vreg98<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg98
1696B		%vreg97<def> = LDRWui %vreg98, 27; mem:LD4[%nblock25] GPR32common:%vreg97 GPR64common:%vreg98
1712B		%vreg96<def> = ADDWri %vreg97, 1, 0; GPR32common:%vreg96,%vreg97
1728B		STRWui %vreg96, %vreg98, 27; mem:ST4[%nblock25] GPR32common:%vreg96 GPR64common:%vreg98
1744B		B <BB#11>
	    Successors according to CFG: BB#11

1760B	BB#9: derived from LLVM BB %sw.bb.27
	    Predecessors according to CFG: BB#6
1792B		%vreg91<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg91
1824B		%vreg85<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg85
1832B		%vreg90<def> = LDRSWui %vreg91, 27; mem:LD4[%nblock28] GPR64:%vreg90 GPR64common:%vreg91
1840B		%vreg84<def> = LDRXui %vreg85, 8; mem:LD8[%block30] GPR64:%vreg84 GPR64common:%vreg85
1848B		%vreg92<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg92
1856B		%vreg82<def> = ADDXrr %vreg84, %vreg90; GPR64common:%vreg82 GPR64:%vreg84,%vreg90
1872B		STRBBui %vreg92, %vreg82, 0; mem:ST1[%arrayidx31] GPR32:%vreg92 GPR64common:%vreg82
1888B		%vreg77<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg77
1904B		%vreg76<def> = LDRWui %vreg77, 27; mem:LD4[%nblock32] GPR32common:%vreg76 GPR64common:%vreg77
1920B		%vreg75<def> = ADDWri %vreg76, 1, 0; GPR32common:%vreg75,%vreg76
1936B		STRWui %vreg75, %vreg77, 27; mem:ST4[%nblock32] GPR32common:%vreg75 GPR64common:%vreg77
1968B		%vreg70<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg70
2000B		%vreg64<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg64
2008B		%vreg69<def> = LDRSWui %vreg70, 27; mem:LD4[%nblock34] GPR64:%vreg69 GPR64common:%vreg70
2016B		%vreg63<def> = LDRXui %vreg64, 8; mem:LD8[%block36] GPR64:%vreg63 GPR64common:%vreg64
2024B		%vreg71<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg71
2032B		%vreg61<def> = ADDXrr %vreg63, %vreg69; GPR64common:%vreg61 GPR64:%vreg63,%vreg69
2048B		STRBBui %vreg71, %vreg61, 0; mem:ST1[%arrayidx37] GPR32:%vreg71 GPR64common:%vreg61
2064B		%vreg56<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg56
2080B		%vreg55<def> = LDRWui %vreg56, 27; mem:LD4[%nblock38] GPR32common:%vreg55 GPR64common:%vreg56
2096B		%vreg54<def> = ADDWri %vreg55, 1, 0; GPR32common:%vreg54,%vreg55
2112B		STRWui %vreg54, %vreg56, 27; mem:ST4[%nblock38] GPR32common:%vreg54 GPR64common:%vreg56
2144B		%vreg49<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg49
2176B		%vreg43<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg43
2184B		%vreg48<def> = LDRSWui %vreg49, 27; mem:LD4[%nblock40] GPR64:%vreg48 GPR64common:%vreg49
2192B		%vreg42<def> = LDRXui %vreg43, 8; mem:LD8[%block42] GPR64:%vreg42 GPR64common:%vreg43
2200B		%vreg50<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg50
2208B		%vreg40<def> = ADDXrr %vreg42, %vreg48; GPR64common:%vreg40 GPR64:%vreg42,%vreg48
2224B		STRBBui %vreg50, %vreg40, 0; mem:ST1[%arrayidx43] GPR32:%vreg50 GPR64common:%vreg40
2240B		%vreg35<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg35
2256B		%vreg34<def> = LDRWui %vreg35, 27; mem:LD4[%nblock44] GPR32common:%vreg34 GPR64common:%vreg35
2272B		%vreg33<def> = ADDWri %vreg34, 1, 0; GPR32common:%vreg33,%vreg34
2288B		STRWui %vreg33, %vreg35, 27; mem:ST4[%nblock44] GPR32common:%vreg33 GPR64common:%vreg35
2304B		B <BB#11>
	    Successors according to CFG: BB#11

2320B	BB#10: derived from LLVM BB %sw.default
	    Predecessors according to CFG: BB#6
2352B		%vreg282<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg282
2432B		%vreg274<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg274
2436B		%vreg281<def> = LDRWui %vreg282, 24; mem:LD4[%state_in_len46] GPR32common:%vreg281 GPR64common:%vreg282
2440B		%vreg267<def> = MOVi32imm 1; GPR32:%vreg267
2448B		%vreg273<def> = ADDXri %vreg274, 128, 0; GPR64common:%vreg273,%vreg274
2452B		%vreg276:sub_32<def,read-undef> = SUBWri %vreg281, 4, 0; GPR64common:%vreg276 GPR32common:%vreg281
2456B		%vreg277<def> = SBFMXri %vreg276, 0, 31; GPR64:%vreg277 GPR64common:%vreg276
2464B		%vreg271<def> = ADDXrr %vreg273, %vreg277; GPR64common:%vreg271,%vreg273 GPR64:%vreg277
2480B		STRBBui %vreg267, %vreg271, 0; mem:ST1[%arrayidx49] GPR32:%vreg267 GPR64common:%vreg271
2512B		%vreg265<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg265
2544B		%vreg259<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg259
2552B		%vreg264<def> = LDRSWui %vreg265, 27; mem:LD4[%nblock50] GPR64:%vreg264 GPR64common:%vreg265
2560B		%vreg258<def> = LDRXui %vreg259, 8; mem:LD8[%block52] GPR64:%vreg258 GPR64common:%vreg259
2568B		%vreg266<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg266
2576B		%vreg256<def> = ADDXrr %vreg258, %vreg264; GPR64common:%vreg256 GPR64:%vreg258,%vreg264
2592B		STRBBui %vreg266, %vreg256, 0; mem:ST1[%arrayidx53] GPR32:%vreg266 GPR64common:%vreg256
2608B		%vreg251<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg251
2624B		%vreg250<def> = LDRWui %vreg251, 27; mem:LD4[%nblock54] GPR32common:%vreg250 GPR64common:%vreg251
2640B		%vreg249<def> = ADDWri %vreg250, 1, 0; GPR32common:%vreg249,%vreg250
2656B		STRWui %vreg249, %vreg251, 27; mem:ST4[%nblock54] GPR32common:%vreg249 GPR64common:%vreg251
2688B		%vreg244<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg244
2720B		%vreg238<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg238
2728B		%vreg243<def> = LDRSWui %vreg244, 27; mem:LD4[%nblock56] GPR64:%vreg243 GPR64common:%vreg244
2736B		%vreg237<def> = LDRXui %vreg238, 8; mem:LD8[%block58] GPR64:%vreg237 GPR64common:%vreg238
2744B		%vreg245<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg245
2752B		%vreg235<def> = ADDXrr %vreg237, %vreg243; GPR64common:%vreg235 GPR64:%vreg237,%vreg243
2768B		STRBBui %vreg245, %vreg235, 0; mem:ST1[%arrayidx59] GPR32:%vreg245 GPR64common:%vreg235
2784B		%vreg230<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg230
2800B		%vreg229<def> = LDRWui %vreg230, 27; mem:LD4[%nblock60] GPR32common:%vreg229 GPR64common:%vreg230
2816B		%vreg228<def> = ADDWri %vreg229, 1, 0; GPR32common:%vreg228,%vreg229
2832B		STRWui %vreg228, %vreg230, 27; mem:ST4[%nblock60] GPR32common:%vreg228 GPR64common:%vreg230
2864B		%vreg223<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg223
2896B		%vreg217<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg217
2904B		%vreg222<def> = LDRSWui %vreg223, 27; mem:LD4[%nblock62] GPR64:%vreg222 GPR64common:%vreg223
2912B		%vreg216<def> = LDRXui %vreg217, 8; mem:LD8[%block64] GPR64:%vreg216 GPR64common:%vreg217
2920B		%vreg224<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg224
2928B		%vreg214<def> = ADDXrr %vreg216, %vreg222; GPR64common:%vreg214 GPR64:%vreg216,%vreg222
2944B		STRBBui %vreg224, %vreg214, 0; mem:ST1[%arrayidx65] GPR32:%vreg224 GPR64common:%vreg214
2960B		%vreg209<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg209
2976B		%vreg208<def> = LDRWui %vreg209, 27; mem:LD4[%nblock66] GPR32common:%vreg208 GPR64common:%vreg209
2992B		%vreg207<def> = ADDWri %vreg208, 1, 0; GPR32common:%vreg207,%vreg208
3008B		STRWui %vreg207, %vreg209, 27; mem:ST4[%nblock66] GPR32common:%vreg207 GPR64common:%vreg209
3040B		%vreg202<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg202
3072B		%vreg196<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg196
3080B		%vreg201<def> = LDRSWui %vreg202, 27; mem:LD4[%nblock68] GPR64:%vreg201 GPR64common:%vreg202
3088B		%vreg195<def> = LDRXui %vreg196, 8; mem:LD8[%block70] GPR64:%vreg195 GPR64common:%vreg196
3096B		%vreg203<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg203
3104B		%vreg193<def> = ADDXrr %vreg195, %vreg201; GPR64common:%vreg193 GPR64:%vreg195,%vreg201
3120B		STRBBui %vreg203, %vreg193, 0; mem:ST1[%arrayidx71] GPR32:%vreg203 GPR64common:%vreg193
3136B		%vreg188<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg188
3152B		%vreg187<def> = LDRWui %vreg188, 27; mem:LD4[%nblock72] GPR32common:%vreg187 GPR64common:%vreg188
3168B		%vreg186<def> = ADDWri %vreg187, 1, 0; GPR32common:%vreg186,%vreg187
3184B		STRWui %vreg186, %vreg188, 27; mem:ST4[%nblock72] GPR32common:%vreg186 GPR64common:%vreg188
3200B		%vreg182<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg182
3264B		%vreg175<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg175
3296B		%vreg169<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg169
3300B		%vreg181<def> = LDRWui %vreg182, 24; mem:LD4[%state_in_len74] GPR32common:%vreg181 GPR64common:%vreg182
3304B		%vreg174<def> = LDRSWui %vreg175, 27; mem:LD4[%nblock77] GPR64:%vreg174 GPR64common:%vreg175
3312B		%vreg168<def> = LDRXui %vreg169, 8; mem:LD8[%block79] GPR64:%vreg168 GPR64common:%vreg169
3320B		%vreg177<def> = SUBWri %vreg181, 4, 0; GPR32common:%vreg177,%vreg181
3328B		%vreg166<def> = ADDXrr %vreg168, %vreg174; GPR64common:%vreg166 GPR64:%vreg168,%vreg174
3344B		STRBBui %vreg177, %vreg166, 0; mem:ST1[%arrayidx80] GPR32common:%vreg177 GPR64common:%vreg166
3360B		%vreg161<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg161
3376B		%vreg160<def> = LDRWui %vreg161, 27; mem:LD4[%nblock81] GPR32common:%vreg160 GPR64common:%vreg161
3392B		%vreg159<def> = ADDWri %vreg160, 1, 0; GPR32common:%vreg159,%vreg160
3408B		STRWui %vreg159, %vreg161, 27; mem:ST4[%nblock81] GPR32common:%vreg159 GPR64common:%vreg161
	    Successors according to CFG: BB#11

3424B	BB#11: derived from LLVM BB %sw.epilog
	    Predecessors according to CFG: BB#9 BB#8 BB#7 BB#10
3440B		%vreg283<def> = ADRP <ga:@add_pair_to_block>[TF=1]; GPR64common:%vreg283
3456B		%vreg285<def> = ADDXri %vreg283, <ga:@add_pair_to_block>[TF=34], 0; GPR64sp:%vreg285 GPR64common:%vreg283
3504B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3520B		%X0<def> = COPY %vreg285; GPR64sp:%vreg285
3536B		%X1<def> = COPY %vreg11; GPR64:%vreg11
3552B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
3568B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3584B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3600B		STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...
3616B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3632B		RET_ReallyLR

# End machine code for function add_pair_to_block.


selectOrSplit GPR64:%vreg11 [16r,3536r:0)  0@16r w=7.729592e-04
hints: %X1
missed hint %X1
assigning %vreg11 to %X19: W19 [16r,3536r:0)  0@16r

selectOrSplit GPR64:%vreg1 [32r,256r:0)  0@32r w=4.855769e-03
hints: %X0
missed hint %X0
assigning %vreg1 to %X20: W20 [32r,256r:0)  0@32r

selectOrSplit GPR64sp:%vreg10 [80r,144r:0)  0@80r w=4.353448e-03
hints: %X0
assigning %vreg10 to %X0: W0 [80r,144r:0)  0@80r

selectOrSplit GPR64sp:%vreg285 [3456r,3520r:0)  0@3456r w=4.353448e-03
hints: %X0
assigning %vreg285 to %X0: W0 [3456r,3520r:0)  0@3456r

selectOrSplit GPR32common:%vreg19 [960r,1120r:0)  0@960r w=4.910714e-03
assigning %vreg19 to %W8: W8 [960r,1120r:0)  0@960r

selectOrSplit GPR64common:%vreg8 [64r,80r:0)  0@64r w=inf
assigning %vreg8 to %X8: W8 [64r,80r:0)  0@64r

selectOrSplit GPR64common:%vreg7 [272r,288r:0)  0@272r w=inf
assigning %vreg7 to %X8: W8 [272r,288r:0)  0@272r

selectOrSplit GPR32:%vreg4 [288r,320r:0)  0@288r w=inf
assigning %vreg4 to %W8: W8 [288r,320r:0)  0@288r

selectOrSplit GPR64common:%vreg17 [384r,400r:0)  0@384r w=9.540264e-03
assigning %vreg17 to %X8: W8 [384r,400r:0)  0@384r

selectOrSplit GPR32:%vreg18 [392r,416r:0)  0@392r w=9.360259e-03
assigning %vreg18 to %W9: W9 [392r,416r:0)  0@392r

selectOrSplit GPR32:%vreg16 [400r,416r:0)  0@400r w=inf
assigning %vreg16 to %W8: W8 [400r,416r:0)  0@400r

selectOrSplit GPR64common:%vreg314 [528r,544r:0)  0@528r w=4.732572e-03
assigning %vreg314 to %X8: W8 [528r,544r:0)  0@528r

selectOrSplit GPR64common:%vreg295 [532r,584r:0)  0@532r w=2.177821e-03
assigning %vreg295 to %X9: W9 [532r,584r:0)  0@532r

selectOrSplit GPR64common:%vreg317 [536r,592r:0)  0@536r w=4.317434e-03
assigning %vreg317 to %X10: W10 [536r,592r:0)  0@536r

selectOrSplit GPR32:%vreg313 [544r,600r:0)  0@544r w=4.317434e-03
assigning %vreg313 to %W8: W8 [544r,600r:0)  0@544r

selectOrSplit GPR32:%vreg309 [576r,608r:0)  0@576r w=4.557292e-03
assigning %vreg309 to %W11: W11 [576r,608r:0)  0@576r

selectOrSplit GPR64common:%vreg296 [584r,672r:0)  0@584r w=4.034324e-03
assigning %vreg296 to %X9: W9 [584r,672r:0)  0@584r

selectOrSplit GPR32:%vreg316 [592r,728r:0)  0@592r w=3.673041e-03
assigning %vreg316 to %W10: W10 [592r,728r:0)  0@592r

selectOrSplit GPR32:%vreg311 [600r,608r:0)  0@600r w=inf
assigning %vreg311 to %W8: W8 [600r,608r:0)  0@600r

selectOrSplit GPR64:%vreg302 [608r,624r:0)  0@608r w=inf
assigning %vreg302 to %X8: W8 [608r,624r:0)  0@608r

selectOrSplit GPR64:%vreg303 [624r,656r:0)  0@624r w=4.557292e-03
assigning %vreg303 to %X8: W8 [624r,656r:0)  0@624r

selectOrSplit GPR64:%vreg298 [640r,656r:0)  0@640r w=inf
assigning %vreg298 to %X11: W11 [640r,656r:0)  0@640r

selectOrSplit GPR64:%vreg299 [656r,672r:0)  0@656r w=inf
assigning %vreg299 to %X8: W8 [656r,672r:0)  0@656r

selectOrSplit GPR64common:%vreg300 [672r,688r:0)  0@672r w=inf
assigning %vreg300 to %X8: W8 [672r,688r:0)  0@672r

selectOrSplit GPR32:%vreg294 [688r,728r:0)  0@688r w=4.474432e-03
assigning %vreg294 to %W8: W8 [688r,728r:0)  0@688r

selectOrSplit GPR64common:%vreg289 [720r,736r:0)  0@720r w=4.732572e-03
assigning %vreg289 to %X9: W9 [720r,736r:0)  0@720r

selectOrSplit GPR32:%vreg292 [728r,736r:0)  0@728r w=inf
assigning %vreg292 to %W8: W8 [728r,736r:0)  0@728r

selectOrSplit GPR32common:%vreg321 [768r,784r:0)  0@768r w=inf
assigning %vreg321 to %W8: W8 [768r,784r:0)  0@768r

selectOrSplit GPR32common:%vreg320 [784r,800r:0)  0@784r w=inf
assigning %vreg320 to %W8: W8 [784r,800r:0)  0@784r

selectOrSplit GPR64common:%vreg20 [848r,896r:0)  0@848r w=6.696429e-03
assigning %vreg20 to %X8: W8 [848r,896r:0)  0@848r

selectOrSplit GPR64:%vreg22 [864r,896r:0)  0@864r w=inf
assigning %vreg22 to %X9: W9 [864r,896r:0)  0@864r

selectOrSplit GPR64common:%vreg23 [896r,928r:0)  0@896r w=4.629630e-03
assigning %vreg23 to %X8: W8 [896r,928r:0)  0@896r

selectOrSplit GPR32:%vreg24 [912r,928r:0)  0@912r w=inf
assigning %vreg24 to %W9: W9 [912r,928r:0)  0@912r

selectOrSplit GPR64common:%vreg25 [944r,960r:0)  0@944r w=inf
assigning %vreg25 to %X8: W8 [944r,960r:0)  0@944r

selectOrSplit GPR32:%vreg27 [992r,992d:0)  0@992r w=inf
assigning %vreg27 to %W9: W9 [992r,992d:0)  0@992r

selectOrSplit GPR32:%vreg28 [1056r,1056d:0)  0@1056r w=inf
assigning %vreg28 to %W9: W9 [1056r,1056d:0)  0@1056r

selectOrSplit GPR32:%vreg29 [1120r,1120d:0)  0@1120r w=inf
assigning %vreg29 to %W8: W8 [1120r,1120d:0)  0@1120r

selectOrSplit GPR64common:%vreg154 [1200r,1240r:0)  0@1200r w=2.272727e-03
assigning %vreg154 to %X8: W8 [1200r,1240r:0)  0@1200r

selectOrSplit GPR64common:%vreg148 [1232r,1248r:0)  0@1232r w=2.403846e-03
assigning %vreg148 to %X9: W9 [1232r,1248r:0)  0@1232r

selectOrSplit GPR64:%vreg153 [1240r,1264r:0)  0@1240r w=2.358491e-03
assigning %vreg153 to %X8: W8 [1240r,1264r:0)  0@1240r

selectOrSplit GPR64:%vreg147 [1248r,1264r:0)  0@1248r w=2.403846e-03
assigning %vreg147 to %X9: W9 [1248r,1264r:0)  0@1248r

selectOrSplit GPR32:%vreg155 [1256r,1280r:0)  0@1256r w=2.358491e-03
assigning %vreg155 to %W10: W10 [1256r,1280r:0)  0@1256r

selectOrSplit GPR64common:%vreg145 [1264r,1280r:0)  0@1264r w=inf
assigning %vreg145 to %X8: W8 [1264r,1280r:0)  0@1264r

selectOrSplit GPR64common:%vreg140 [1296r,1344r:0)  0@1296r w=3.348214e-03
assigning %vreg140 to %X8: W8 [1296r,1344r:0)  0@1296r

selectOrSplit GPR32common:%vreg139 [1312r,1328r:0)  0@1312r w=inf
assigning %vreg139 to %W9: W9 [1312r,1328r:0)  0@1312r

selectOrSplit GPR32common:%vreg138 [1328r,1344r:0)  0@1328r w=inf
assigning %vreg138 to %W9: W9 [1328r,1344r:0)  0@1328r

selectOrSplit GPR64common:%vreg133 [1408r,1448r:0)  0@1408r w=1.136364e-03
assigning %vreg133 to %X8: W8 [1408r,1448r:0)  0@1408r

selectOrSplit GPR64common:%vreg127 [1440r,1456r:0)  0@1440r w=1.201923e-03
assigning %vreg127 to %X9: W9 [1440r,1456r:0)  0@1440r

selectOrSplit GPR64:%vreg132 [1448r,1472r:0)  0@1448r w=1.179245e-03
assigning %vreg132 to %X8: W8 [1448r,1472r:0)  0@1448r

selectOrSplit GPR64:%vreg126 [1456r,1472r:0)  0@1456r w=1.201923e-03
assigning %vreg126 to %X9: W9 [1456r,1472r:0)  0@1456r

selectOrSplit GPR32:%vreg134 [1464r,1488r:0)  0@1464r w=1.179245e-03
assigning %vreg134 to %W10: W10 [1464r,1488r:0)  0@1464r

selectOrSplit GPR64common:%vreg124 [1472r,1488r:0)  0@1472r w=inf
assigning %vreg124 to %X8: W8 [1472r,1488r:0)  0@1472r

selectOrSplit GPR64common:%vreg119 [1504r,1552r:0)  0@1504r w=1.674107e-03
assigning %vreg119 to %X8: W8 [1504r,1552r:0)  0@1504r

selectOrSplit GPR32common:%vreg118 [1520r,1536r:0)  0@1520r w=inf
assigning %vreg118 to %W9: W9 [1520r,1536r:0)  0@1520r

selectOrSplit GPR32common:%vreg117 [1536r,1552r:0)  0@1536r w=inf
assigning %vreg117 to %W9: W9 [1536r,1552r:0)  0@1536r

selectOrSplit GPR64common:%vreg112 [1584r,1624r:0)  0@1584r w=1.136364e-03
assigning %vreg112 to %X8: W8 [1584r,1624r:0)  0@1584r

selectOrSplit GPR64common:%vreg106 [1616r,1632r:0)  0@1616r w=1.201923e-03
assigning %vreg106 to %X9: W9 [1616r,1632r:0)  0@1616r

selectOrSplit GPR64:%vreg111 [1624r,1648r:0)  0@1624r w=1.179245e-03
assigning %vreg111 to %X8: W8 [1624r,1648r:0)  0@1624r

selectOrSplit GPR64:%vreg105 [1632r,1648r:0)  0@1632r w=1.201923e-03
assigning %vreg105 to %X9: W9 [1632r,1648r:0)  0@1632r

selectOrSplit GPR32:%vreg113 [1640r,1664r:0)  0@1640r w=1.179245e-03
assigning %vreg113 to %W10: W10 [1640r,1664r:0)  0@1640r

selectOrSplit GPR64common:%vreg103 [1648r,1664r:0)  0@1648r w=inf
assigning %vreg103 to %X8: W8 [1648r,1664r:0)  0@1648r

selectOrSplit GPR64common:%vreg98 [1680r,1728r:0)  0@1680r w=1.674107e-03
assigning %vreg98 to %X8: W8 [1680r,1728r:0)  0@1680r

selectOrSplit GPR32common:%vreg97 [1696r,1712r:0)  0@1696r w=inf
assigning %vreg97 to %W9: W9 [1696r,1712r:0)  0@1696r

selectOrSplit GPR32common:%vreg96 [1712r,1728r:0)  0@1712r w=inf
assigning %vreg96 to %W9: W9 [1712r,1728r:0)  0@1712r

selectOrSplit GPR64common:%vreg91 [1792r,1832r:0)  0@1792r w=5.681818e-04
assigning %vreg91 to %X8: W8 [1792r,1832r:0)  0@1792r

selectOrSplit GPR64common:%vreg85 [1824r,1840r:0)  0@1824r w=6.009616e-04
assigning %vreg85 to %X9: W9 [1824r,1840r:0)  0@1824r

selectOrSplit GPR64:%vreg90 [1832r,1856r:0)  0@1832r w=5.896227e-04
assigning %vreg90 to %X8: W8 [1832r,1856r:0)  0@1832r

selectOrSplit GPR64:%vreg84 [1840r,1856r:0)  0@1840r w=6.009616e-04
assigning %vreg84 to %X9: W9 [1840r,1856r:0)  0@1840r

selectOrSplit GPR32:%vreg92 [1848r,1872r:0)  0@1848r w=5.896227e-04
assigning %vreg92 to %W10: W10 [1848r,1872r:0)  0@1848r

selectOrSplit GPR64common:%vreg82 [1856r,1872r:0)  0@1856r w=inf
assigning %vreg82 to %X8: W8 [1856r,1872r:0)  0@1856r

selectOrSplit GPR64common:%vreg77 [1888r,1936r:0)  0@1888r w=8.370536e-04
assigning %vreg77 to %X8: W8 [1888r,1936r:0)  0@1888r

selectOrSplit GPR32common:%vreg76 [1904r,1920r:0)  0@1904r w=inf
assigning %vreg76 to %W9: W9 [1904r,1920r:0)  0@1904r

selectOrSplit GPR32common:%vreg75 [1920r,1936r:0)  0@1920r w=inf
assigning %vreg75 to %W9: W9 [1920r,1936r:0)  0@1920r

selectOrSplit GPR64common:%vreg70 [1968r,2008r:0)  0@1968r w=5.681818e-04
assigning %vreg70 to %X8: W8 [1968r,2008r:0)  0@1968r

selectOrSplit GPR64common:%vreg64 [2000r,2016r:0)  0@2000r w=6.009616e-04
assigning %vreg64 to %X9: W9 [2000r,2016r:0)  0@2000r

selectOrSplit GPR64:%vreg69 [2008r,2032r:0)  0@2008r w=5.896227e-04
assigning %vreg69 to %X8: W8 [2008r,2032r:0)  0@2008r

selectOrSplit GPR64:%vreg63 [2016r,2032r:0)  0@2016r w=6.009616e-04
assigning %vreg63 to %X9: W9 [2016r,2032r:0)  0@2016r

selectOrSplit GPR32:%vreg71 [2024r,2048r:0)  0@2024r w=5.896227e-04
assigning %vreg71 to %W10: W10 [2024r,2048r:0)  0@2024r

selectOrSplit GPR64common:%vreg61 [2032r,2048r:0)  0@2032r w=inf
assigning %vreg61 to %X8: W8 [2032r,2048r:0)  0@2032r

selectOrSplit GPR64common:%vreg56 [2064r,2112r:0)  0@2064r w=8.370536e-04
assigning %vreg56 to %X8: W8 [2064r,2112r:0)  0@2064r

selectOrSplit GPR32common:%vreg55 [2080r,2096r:0)  0@2080r w=inf
assigning %vreg55 to %W9: W9 [2080r,2096r:0)  0@2080r

selectOrSplit GPR32common:%vreg54 [2096r,2112r:0)  0@2096r w=inf
assigning %vreg54 to %W9: W9 [2096r,2112r:0)  0@2096r

selectOrSplit GPR64common:%vreg49 [2144r,2184r:0)  0@2144r w=5.681818e-04
assigning %vreg49 to %X8: W8 [2144r,2184r:0)  0@2144r

selectOrSplit GPR64common:%vreg43 [2176r,2192r:0)  0@2176r w=6.009616e-04
assigning %vreg43 to %X9: W9 [2176r,2192r:0)  0@2176r

selectOrSplit GPR64:%vreg48 [2184r,2208r:0)  0@2184r w=5.896227e-04
assigning %vreg48 to %X8: W8 [2184r,2208r:0)  0@2184r

selectOrSplit GPR64:%vreg42 [2192r,2208r:0)  0@2192r w=6.009616e-04
assigning %vreg42 to %X9: W9 [2192r,2208r:0)  0@2192r

selectOrSplit GPR32:%vreg50 [2200r,2224r:0)  0@2200r w=5.896227e-04
assigning %vreg50 to %W10: W10 [2200r,2224r:0)  0@2200r

selectOrSplit GPR64common:%vreg40 [2208r,2224r:0)  0@2208r w=inf
assigning %vreg40 to %X8: W8 [2208r,2224r:0)  0@2208r

selectOrSplit GPR64common:%vreg35 [2240r,2288r:0)  0@2240r w=8.370536e-04
assigning %vreg35 to %X8: W8 [2240r,2288r:0)  0@2240r

selectOrSplit GPR32common:%vreg34 [2256r,2272r:0)  0@2256r w=inf
assigning %vreg34 to %W9: W9 [2256r,2272r:0)  0@2256r

selectOrSplit GPR32common:%vreg33 [2272r,2288r:0)  0@2272r w=inf
assigning %vreg33 to %W9: W9 [2272r,2288r:0)  0@2272r

selectOrSplit GPR64common:%vreg282 [2352r,2436r:0)  0@2352r w=5.165289e-04
assigning %vreg282 to %X8: W8 [2352r,2436r:0)  0@2352r

selectOrSplit GPR64common:%vreg274 [2432r,2448r:0)  0@2432r w=6.009616e-04
assigning %vreg274 to %X9: W9 [2432r,2448r:0)  0@2432r

selectOrSplit GPR32common:%vreg281 [2436r,2452r:0)  0@2436r w=6.009616e-04
assigning %vreg281 to %W8: W8 [2436r,2452r:0)  0@2436r

selectOrSplit GPR32:%vreg267 [2440r,2480r:0)  0@2440r w=2.840909e-04
assigning %vreg267 to %W10: W10 [2440r,2480r:0)  0@2440r

selectOrSplit GPR64common:%vreg273 [2448r,2464r:0)  0@2448r w=6.009616e-04
assigning %vreg273 to %X9: W9 [2448r,2464r:0)  0@2448r

selectOrSplit GPR64common:%vreg276 [2452r,2456r:0)  0@2452r w=inf
assigning %vreg276 to %X8: W8 [2452r,2456r:0)  0@2452r

selectOrSplit GPR64:%vreg277 [2456r,2464r:0)  0@2456r w=inf
assigning %vreg277 to %X8: W8 [2456r,2464r:0)  0@2456r

selectOrSplit GPR64common:%vreg271 [2464r,2480r:0)  0@2464r w=inf
assigning %vreg271 to %X8: W8 [2464r,2480r:0)  0@2464r

selectOrSplit GPR64common:%vreg265 [2512r,2552r:0)  0@2512r w=5.681818e-04
assigning %vreg265 to %X8: W8 [2512r,2552r:0)  0@2512r

selectOrSplit GPR64common:%vreg259 [2544r,2560r:0)  0@2544r w=6.009616e-04
assigning %vreg259 to %X9: W9 [2544r,2560r:0)  0@2544r

selectOrSplit GPR64:%vreg264 [2552r,2576r:0)  0@2552r w=5.896227e-04
assigning %vreg264 to %X8: W8 [2552r,2576r:0)  0@2552r

selectOrSplit GPR64:%vreg258 [2560r,2576r:0)  0@2560r w=6.009616e-04
assigning %vreg258 to %X9: W9 [2560r,2576r:0)  0@2560r

selectOrSplit GPR32:%vreg266 [2568r,2592r:0)  0@2568r w=5.896227e-04
assigning %vreg266 to %W10: W10 [2568r,2592r:0)  0@2568r

selectOrSplit GPR64common:%vreg256 [2576r,2592r:0)  0@2576r w=inf
assigning %vreg256 to %X8: W8 [2576r,2592r:0)  0@2576r

selectOrSplit GPR64common:%vreg251 [2608r,2656r:0)  0@2608r w=8.370536e-04
assigning %vreg251 to %X8: W8 [2608r,2656r:0)  0@2608r

selectOrSplit GPR32common:%vreg250 [2624r,2640r:0)  0@2624r w=inf
assigning %vreg250 to %W9: W9 [2624r,2640r:0)  0@2624r

selectOrSplit GPR32common:%vreg249 [2640r,2656r:0)  0@2640r w=inf
assigning %vreg249 to %W9: W9 [2640r,2656r:0)  0@2640r

selectOrSplit GPR64common:%vreg244 [2688r,2728r:0)  0@2688r w=5.681818e-04
assigning %vreg244 to %X8: W8 [2688r,2728r:0)  0@2688r

selectOrSplit GPR64common:%vreg238 [2720r,2736r:0)  0@2720r w=6.009616e-04
assigning %vreg238 to %X9: W9 [2720r,2736r:0)  0@2720r

selectOrSplit GPR64:%vreg243 [2728r,2752r:0)  0@2728r w=5.896227e-04
assigning %vreg243 to %X8: W8 [2728r,2752r:0)  0@2728r

selectOrSplit GPR64:%vreg237 [2736r,2752r:0)  0@2736r w=6.009616e-04
assigning %vreg237 to %X9: W9 [2736r,2752r:0)  0@2736r

selectOrSplit GPR32:%vreg245 [2744r,2768r:0)  0@2744r w=5.896227e-04
assigning %vreg245 to %W10: W10 [2744r,2768r:0)  0@2744r

selectOrSplit GPR64common:%vreg235 [2752r,2768r:0)  0@2752r w=inf
assigning %vreg235 to %X8: W8 [2752r,2768r:0)  0@2752r

selectOrSplit GPR64common:%vreg230 [2784r,2832r:0)  0@2784r w=8.370536e-04
assigning %vreg230 to %X8: W8 [2784r,2832r:0)  0@2784r

selectOrSplit GPR32common:%vreg229 [2800r,2816r:0)  0@2800r w=inf
assigning %vreg229 to %W9: W9 [2800r,2816r:0)  0@2800r

selectOrSplit GPR32common:%vreg228 [2816r,2832r:0)  0@2816r w=inf
assigning %vreg228 to %W9: W9 [2816r,2832r:0)  0@2816r

selectOrSplit GPR64common:%vreg223 [2864r,2904r:0)  0@2864r w=5.681818e-04
assigning %vreg223 to %X8: W8 [2864r,2904r:0)  0@2864r

selectOrSplit GPR64common:%vreg217 [2896r,2912r:0)  0@2896r w=6.009616e-04
assigning %vreg217 to %X9: W9 [2896r,2912r:0)  0@2896r

selectOrSplit GPR64:%vreg222 [2904r,2928r:0)  0@2904r w=5.896227e-04
assigning %vreg222 to %X8: W8 [2904r,2928r:0)  0@2904r

selectOrSplit GPR64:%vreg216 [2912r,2928r:0)  0@2912r w=6.009616e-04
assigning %vreg216 to %X9: W9 [2912r,2928r:0)  0@2912r

selectOrSplit GPR32:%vreg224 [2920r,2944r:0)  0@2920r w=5.896227e-04
assigning %vreg224 to %W10: W10 [2920r,2944r:0)  0@2920r

selectOrSplit GPR64common:%vreg214 [2928r,2944r:0)  0@2928r w=inf
assigning %vreg214 to %X8: W8 [2928r,2944r:0)  0@2928r

selectOrSplit GPR64common:%vreg209 [2960r,3008r:0)  0@2960r w=8.370536e-04
assigning %vreg209 to %X8: W8 [2960r,3008r:0)  0@2960r

selectOrSplit GPR32common:%vreg208 [2976r,2992r:0)  0@2976r w=inf
assigning %vreg208 to %W9: W9 [2976r,2992r:0)  0@2976r

selectOrSplit GPR32common:%vreg207 [2992r,3008r:0)  0@2992r w=inf
assigning %vreg207 to %W9: W9 [2992r,3008r:0)  0@2992r

selectOrSplit GPR64common:%vreg202 [3040r,3080r:0)  0@3040r w=5.681818e-04
assigning %vreg202 to %X8: W8 [3040r,3080r:0)  0@3040r

selectOrSplit GPR64common:%vreg196 [3072r,3088r:0)  0@3072r w=6.009616e-04
assigning %vreg196 to %X9: W9 [3072r,3088r:0)  0@3072r

selectOrSplit GPR64:%vreg201 [3080r,3104r:0)  0@3080r w=5.896227e-04
assigning %vreg201 to %X8: W8 [3080r,3104r:0)  0@3080r

selectOrSplit GPR64:%vreg195 [3088r,3104r:0)  0@3088r w=6.009616e-04
assigning %vreg195 to %X9: W9 [3088r,3104r:0)  0@3088r

selectOrSplit GPR32:%vreg203 [3096r,3120r:0)  0@3096r w=5.896227e-04
assigning %vreg203 to %W10: W10 [3096r,3120r:0)  0@3096r

selectOrSplit GPR64common:%vreg193 [3104r,3120r:0)  0@3104r w=inf
assigning %vreg193 to %X8: W8 [3104r,3120r:0)  0@3104r

selectOrSplit GPR64common:%vreg188 [3136r,3184r:0)  0@3136r w=8.370536e-04
assigning %vreg188 to %X8: W8 [3136r,3184r:0)  0@3136r

selectOrSplit GPR32common:%vreg187 [3152r,3168r:0)  0@3152r w=inf
assigning %vreg187 to %W9: W9 [3152r,3168r:0)  0@3152r

selectOrSplit GPR32common:%vreg186 [3168r,3184r:0)  0@3168r w=inf
assigning %vreg186 to %W9: W9 [3168r,3184r:0)  0@3168r

selectOrSplit GPR64common:%vreg182 [3200r,3300r:0)  0@3200r w=5.000000e-04
assigning %vreg182 to %X8: W8 [3200r,3300r:0)  0@3200r

selectOrSplit GPR64common:%vreg175 [3264r,3304r:0)  0@3264r w=5.681818e-04
assigning %vreg175 to %X9: W9 [3264r,3304r:0)  0@3264r

selectOrSplit GPR64common:%vreg169 [3296r,3312r:0)  0@3296r w=6.009616e-04
assigning %vreg169 to %X10: W10 [3296r,3312r:0)  0@3296r

selectOrSplit GPR32common:%vreg181 [3300r,3320r:0)  0@3300r w=5.952381e-04
assigning %vreg181 to %W8: W8 [3300r,3320r:0)  0@3300r

selectOrSplit GPR64:%vreg174 [3304r,3328r:0)  0@3304r w=5.896227e-04
assigning %vreg174 to %X9: W9 [3304r,3328r:0)  0@3304r

selectOrSplit GPR64:%vreg168 [3312r,3328r:0)  0@3312r w=6.009616e-04
assigning %vreg168 to %X10: W10 [3312r,3328r:0)  0@3312r

selectOrSplit GPR32common:%vreg177 [3320r,3344r:0)  0@3320r w=5.896227e-04
assigning %vreg177 to %W8: W8 [3320r,3344r:0)  0@3320r

selectOrSplit GPR64common:%vreg166 [3328r,3344r:0)  0@3328r w=inf
assigning %vreg166 to %X9: W9 [3328r,3344r:0)  0@3328r

selectOrSplit GPR64common:%vreg161 [3360r,3408r:0)  0@3360r w=8.370536e-04
assigning %vreg161 to %X8: W8 [3360r,3408r:0)  0@3360r

selectOrSplit GPR32common:%vreg160 [3376r,3392r:0)  0@3376r w=inf
assigning %vreg160 to %W9: W9 [3376r,3392r:0)  0@3376r

selectOrSplit GPR32common:%vreg159 [3392r,3408r:0)  0@3392r w=inf
assigning %vreg159 to %W9: W9 [3392r,3408r:0)  0@3392r

selectOrSplit GPR64common:%vreg283 [3440r,3456r:0)  0@3440r w=inf
assigning %vreg283 to %X8: W8 [3440r,3456r:0)  0@3440r

********** STACK TRANSFORMATION METADATA **********
********** Function: add_pair_to_block
********** REGISTER MAP **********
[%vreg1 -> %X20] GPR64
[%vreg4 -> %W8] GPR32
[%vreg7 -> %X8] GPR64common
[%vreg8 -> %X8] GPR64common
[%vreg10 -> %X0] GPR64sp
[%vreg11 -> %X19] GPR64
[%vreg16 -> %W8] GPR32
[%vreg17 -> %X8] GPR64common
[%vreg18 -> %W9] GPR32
[%vreg19 -> %W8] GPR32common
[%vreg20 -> %X8] GPR64common
[%vreg22 -> %X9] GPR64
[%vreg23 -> %X8] GPR64common
[%vreg24 -> %W9] GPR32
[%vreg25 -> %X8] GPR64common
[%vreg27 -> %W9] GPR32
[%vreg28 -> %W9] GPR32
[%vreg29 -> %W8] GPR32
[%vreg33 -> %W9] GPR32common
[%vreg34 -> %W9] GPR32common
[%vreg35 -> %X8] GPR64common
[%vreg40 -> %X8] GPR64common
[%vreg42 -> %X9] GPR64
[%vreg43 -> %X9] GPR64common
[%vreg48 -> %X8] GPR64
[%vreg49 -> %X8] GPR64common
[%vreg50 -> %W10] GPR32
[%vreg54 -> %W9] GPR32common
[%vreg55 -> %W9] GPR32common
[%vreg56 -> %X8] GPR64common
[%vreg61 -> %X8] GPR64common
[%vreg63 -> %X9] GPR64
[%vreg64 -> %X9] GPR64common
[%vreg69 -> %X8] GPR64
[%vreg70 -> %X8] GPR64common
[%vreg71 -> %W10] GPR32
[%vreg75 -> %W9] GPR32common
[%vreg76 -> %W9] GPR32common
[%vreg77 -> %X8] GPR64common
[%vreg82 -> %X8] GPR64common
[%vreg84 -> %X9] GPR64
[%vreg85 -> %X9] GPR64common
[%vreg90 -> %X8] GPR64
[%vreg91 -> %X8] GPR64common
[%vreg92 -> %W10] GPR32
[%vreg96 -> %W9] GPR32common
[%vreg97 -> %W9] GPR32common
[%vreg98 -> %X8] GPR64common
[%vreg103 -> %X8] GPR64common
[%vreg105 -> %X9] GPR64
[%vreg106 -> %X9] GPR64common
[%vreg111 -> %X8] GPR64
[%vreg112 -> %X8] GPR64common
[%vreg113 -> %W10] GPR32
[%vreg117 -> %W9] GPR32common
[%vreg118 -> %W9] GPR32common
[%vreg119 -> %X8] GPR64common
[%vreg124 -> %X8] GPR64common
[%vreg126 -> %X9] GPR64
[%vreg127 -> %X9] GPR64common
[%vreg132 -> %X8] GPR64
[%vreg133 -> %X8] GPR64common
[%vreg134 -> %W10] GPR32
[%vreg138 -> %W9] GPR32common
[%vreg139 -> %W9] GPR32common
[%vreg140 -> %X8] GPR64common
[%vreg145 -> %X8] GPR64common
[%vreg147 -> %X9] GPR64
[%vreg148 -> %X9] GPR64common
[%vreg153 -> %X8] GPR64
[%vreg154 -> %X8] GPR64common
[%vreg155 -> %W10] GPR32
[%vreg159 -> %W9] GPR32common
[%vreg160 -> %W9] GPR32common
[%vreg161 -> %X8] GPR64common
[%vreg166 -> %X9] GPR64common
[%vreg168 -> %X10] GPR64
[%vreg169 -> %X10] GPR64common
[%vreg174 -> %X9] GPR64
[%vreg175 -> %X9] GPR64common
[%vreg177 -> %W8] GPR32common
[%vreg181 -> %W8] GPR32common
[%vreg182 -> %X8] GPR64common
[%vreg186 -> %W9] GPR32common
[%vreg187 -> %W9] GPR32common
[%vreg188 -> %X8] GPR64common
[%vreg193 -> %X8] GPR64common
[%vreg195 -> %X9] GPR64
[%vreg196 -> %X9] GPR64common
[%vreg201 -> %X8] GPR64
[%vreg202 -> %X8] GPR64common
[%vreg203 -> %W10] GPR32
[%vreg207 -> %W9] GPR32common
[%vreg208 -> %W9] GPR32common
[%vreg209 -> %X8] GPR64common
[%vreg214 -> %X8] GPR64common
[%vreg216 -> %X9] GPR64
[%vreg217 -> %X9] GPR64common
[%vreg222 -> %X8] GPR64
[%vreg223 -> %X8] GPR64common
[%vreg224 -> %W10] GPR32
[%vreg228 -> %W9] GPR32common
[%vreg229 -> %W9] GPR32common
[%vreg230 -> %X8] GPR64common
[%vreg235 -> %X8] GPR64common
[%vreg237 -> %X9] GPR64
[%vreg238 -> %X9] GPR64common
[%vreg243 -> %X8] GPR64
[%vreg244 -> %X8] GPR64common
[%vreg245 -> %W10] GPR32
[%vreg249 -> %W9] GPR32common
[%vreg250 -> %W9] GPR32common
[%vreg251 -> %X8] GPR64common
[%vreg256 -> %X8] GPR64common
[%vreg258 -> %X9] GPR64
[%vreg259 -> %X9] GPR64common
[%vreg264 -> %X8] GPR64
[%vreg265 -> %X8] GPR64common
[%vreg266 -> %W10] GPR32
[%vreg267 -> %W10] GPR32
[%vreg271 -> %X8] GPR64common
[%vreg273 -> %X9] GPR64common
[%vreg274 -> %X9] GPR64common
[%vreg276 -> %X8] GPR64common
[%vreg277 -> %X8] GPR64
[%vreg281 -> %W8] GPR32common
[%vreg282 -> %X8] GPR64common
[%vreg283 -> %X8] GPR64common
[%vreg285 -> %X0] GPR64sp
[%vreg289 -> %X9] GPR64common
[%vreg292 -> %W8] GPR32
[%vreg294 -> %W8] GPR32
[%vreg295 -> %X9] GPR64common
[%vreg296 -> %X9] GPR64common
[%vreg298 -> %X11] GPR64
[%vreg299 -> %X8] GPR64
[%vreg300 -> %X8] GPR64common
[%vreg302 -> %X8] GPR64
[%vreg303 -> %X8] GPR64
[%vreg309 -> %W11] GPR32
[%vreg311 -> %W8] GPR32
[%vreg313 -> %W8] GPR32
[%vreg314 -> %X8] GPR64common
[%vreg316 -> %W10] GPR32
[%vreg317 -> %X10] GPR64common
[%vreg320 -> %W8] GPR32common
[%vreg321 -> %W8] GPR32common


Stackmap 0:
  STACKMAP 0, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack1](align=4) LD8[FixedStack0] GPR64:%vreg1

i8* %ch: in stack slot 2 (size: 1)
i32* %i: in stack slot 1 (size: 4)
%struct.EState* %s: in register %X20 (vreg 1)
%struct.EState** %s.addr: in stack slot 0 (size: 8)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...


Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack1](align=4) LD8[FixedStack0] GPR64:%vreg1
  -> Call instruction SlotIndex 176B, searching vregs 0 -> 322 and stack slots 0 -> 3
    + vreg11 is live in register but not in stackmap
      Defining instruction: %vreg11<def> = COPY %LR; GPR64:%vreg11
      Value: generated value, 1 instruction(s)

  STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...
  -> Call instruction SlotIndex 3552B, searching vregs 0 -> 322 and stack slots 0 -> 3

********** REWRITE VIRTUAL REGISTERS **********
********** Function: add_pair_to_block
********** REGISTER MAP **********
[%vreg1 -> %X20] GPR64
[%vreg4 -> %W8] GPR32
[%vreg7 -> %X8] GPR64common
[%vreg8 -> %X8] GPR64common
[%vreg10 -> %X0] GPR64sp
[%vreg11 -> %X19] GPR64
[%vreg16 -> %W8] GPR32
[%vreg17 -> %X8] GPR64common
[%vreg18 -> %W9] GPR32
[%vreg19 -> %W8] GPR32common
[%vreg20 -> %X8] GPR64common
[%vreg22 -> %X9] GPR64
[%vreg23 -> %X8] GPR64common
[%vreg24 -> %W9] GPR32
[%vreg25 -> %X8] GPR64common
[%vreg27 -> %W9] GPR32
[%vreg28 -> %W9] GPR32
[%vreg29 -> %W8] GPR32
[%vreg33 -> %W9] GPR32common
[%vreg34 -> %W9] GPR32common
[%vreg35 -> %X8] GPR64common
[%vreg40 -> %X8] GPR64common
[%vreg42 -> %X9] GPR64
[%vreg43 -> %X9] GPR64common
[%vreg48 -> %X8] GPR64
[%vreg49 -> %X8] GPR64common
[%vreg50 -> %W10] GPR32
[%vreg54 -> %W9] GPR32common
[%vreg55 -> %W9] GPR32common
[%vreg56 -> %X8] GPR64common
[%vreg61 -> %X8] GPR64common
[%vreg63 -> %X9] GPR64
[%vreg64 -> %X9] GPR64common
[%vreg69 -> %X8] GPR64
[%vreg70 -> %X8] GPR64common
[%vreg71 -> %W10] GPR32
[%vreg75 -> %W9] GPR32common
[%vreg76 -> %W9] GPR32common
[%vreg77 -> %X8] GPR64common
[%vreg82 -> %X8] GPR64common
[%vreg84 -> %X9] GPR64
[%vreg85 -> %X9] GPR64common
[%vreg90 -> %X8] GPR64
[%vreg91 -> %X8] GPR64common
[%vreg92 -> %W10] GPR32
[%vreg96 -> %W9] GPR32common
[%vreg97 -> %W9] GPR32common
[%vreg98 -> %X8] GPR64common
[%vreg103 -> %X8] GPR64common
[%vreg105 -> %X9] GPR64
[%vreg106 -> %X9] GPR64common
[%vreg111 -> %X8] GPR64
[%vreg112 -> %X8] GPR64common
[%vreg113 -> %W10] GPR32
[%vreg117 -> %W9] GPR32common
[%vreg118 -> %W9] GPR32common
[%vreg119 -> %X8] GPR64common
[%vreg124 -> %X8] GPR64common
[%vreg126 -> %X9] GPR64
[%vreg127 -> %X9] GPR64common
[%vreg132 -> %X8] GPR64
[%vreg133 -> %X8] GPR64common
[%vreg134 -> %W10] GPR32
[%vreg138 -> %W9] GPR32common
[%vreg139 -> %W9] GPR32common
[%vreg140 -> %X8] GPR64common
[%vreg145 -> %X8] GPR64common
[%vreg147 -> %X9] GPR64
[%vreg148 -> %X9] GPR64common
[%vreg153 -> %X8] GPR64
[%vreg154 -> %X8] GPR64common
[%vreg155 -> %W10] GPR32
[%vreg159 -> %W9] GPR32common
[%vreg160 -> %W9] GPR32common
[%vreg161 -> %X8] GPR64common
[%vreg166 -> %X9] GPR64common
[%vreg168 -> %X10] GPR64
[%vreg169 -> %X10] GPR64common
[%vreg174 -> %X9] GPR64
[%vreg175 -> %X9] GPR64common
[%vreg177 -> %W8] GPR32common
[%vreg181 -> %W8] GPR32common
[%vreg182 -> %X8] GPR64common
[%vreg186 -> %W9] GPR32common
[%vreg187 -> %W9] GPR32common
[%vreg188 -> %X8] GPR64common
[%vreg193 -> %X8] GPR64common
[%vreg195 -> %X9] GPR64
[%vreg196 -> %X9] GPR64common
[%vreg201 -> %X8] GPR64
[%vreg202 -> %X8] GPR64common
[%vreg203 -> %W10] GPR32
[%vreg207 -> %W9] GPR32common
[%vreg208 -> %W9] GPR32common
[%vreg209 -> %X8] GPR64common
[%vreg214 -> %X8] GPR64common
[%vreg216 -> %X9] GPR64
[%vreg217 -> %X9] GPR64common
[%vreg222 -> %X8] GPR64
[%vreg223 -> %X8] GPR64common
[%vreg224 -> %W10] GPR32
[%vreg228 -> %W9] GPR32common
[%vreg229 -> %W9] GPR32common
[%vreg230 -> %X8] GPR64common
[%vreg235 -> %X8] GPR64common
[%vreg237 -> %X9] GPR64
[%vreg238 -> %X9] GPR64common
[%vreg243 -> %X8] GPR64
[%vreg244 -> %X8] GPR64common
[%vreg245 -> %W10] GPR32
[%vreg249 -> %W9] GPR32common
[%vreg250 -> %W9] GPR32common
[%vreg251 -> %X8] GPR64common
[%vreg256 -> %X8] GPR64common
[%vreg258 -> %X9] GPR64
[%vreg259 -> %X9] GPR64common
[%vreg264 -> %X8] GPR64
[%vreg265 -> %X8] GPR64common
[%vreg266 -> %W10] GPR32
[%vreg267 -> %W10] GPR32
[%vreg271 -> %X8] GPR64common
[%vreg273 -> %X9] GPR64common
[%vreg274 -> %X9] GPR64common
[%vreg276 -> %X8] GPR64common
[%vreg277 -> %X8] GPR64
[%vreg281 -> %W8] GPR32common
[%vreg282 -> %X8] GPR64common
[%vreg283 -> %X8] GPR64common
[%vreg285 -> %X0] GPR64sp
[%vreg289 -> %X9] GPR64common
[%vreg292 -> %W8] GPR32
[%vreg294 -> %W8] GPR32
[%vreg295 -> %X9] GPR64common
[%vreg296 -> %X9] GPR64common
[%vreg298 -> %X11] GPR64
[%vreg299 -> %X8] GPR64
[%vreg300 -> %X8] GPR64common
[%vreg302 -> %X8] GPR64
[%vreg303 -> %X8] GPR64
[%vreg309 -> %W11] GPR32
[%vreg311 -> %W8] GPR32
[%vreg313 -> %W8] GPR32
[%vreg314 -> %X8] GPR64common
[%vreg316 -> %W10] GPR32
[%vreg317 -> %X10] GPR64common
[%vreg320 -> %W8] GPR32common
[%vreg321 -> %W8] GPR32common

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %LR %X0
16B		%vreg11<def> = COPY %LR; GPR64:%vreg11
32B		%vreg1<def> = COPY %X0; GPR64:%vreg1
64B		%vreg8<def> = ADRP <ga:@add_pair_to_block>[TF=1]; GPR64common:%vreg8
80B		%vreg10<def> = ADDXri %vreg8<kill>, <ga:@add_pair_to_block>[TF=34], 0; GPR64sp:%vreg10 GPR64common:%vreg8
128B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
144B		%X0<def> = COPY %vreg10<kill>; GPR64sp:%vreg10
160B		%X1<def> = COPY %vreg11; GPR64:%vreg11
176B		BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
192B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
208B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
224B		STACKMAP 0, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack1](align=4) LD8[FixedStack0] GPR64:%vreg1
240B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
256B		STRXui %vreg1<kill>, <fi#0>, 0; mem:ST8[FixedStack0] GPR64:%vreg1
272B		%vreg7<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg7
288B		%vreg4<def> = LDRWui %vreg7<kill>, 23; mem:LD4[%state_in_ch] GPR32:%vreg4 GPR64common:%vreg7
320B		STRBBui %vreg4<kill>, <fi#2>, 0; mem:ST1[FixedStack2] GPR32:%vreg4
336B		STRWui %WZR, <fi#1>, 0; mem:ST4[FixedStack1]
	    Successors according to CFG: BB#1
> %X19<def> = COPY %LR
> %X20<def> = COPY %X0
> %X8<def> = ADRP <ga:@add_pair_to_block>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@add_pair_to_block>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19
> BL <ga:@__cyg_profile_func_enter>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 0, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, %X20, 0, <fi#0>, 0, %LR<earlyclobber,imp-def,dead>, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack1](align=4) LD8[FixedStack0]
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> STRXui %X20<kill>, <fi#0>, 0; mem:ST8[FixedStack0]
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %W8<def> = LDRWui %X8<kill>, 23; mem:LD4[%state_in_ch]
> STRBBui %W8<kill>, <fi#2>, 0; mem:ST1[FixedStack2]
> STRWui %WZR, <fi#1>, 0; mem:ST4[FixedStack1]
352B	BB#1: derived from LLVM BB %for.cond
	    Live Ins: %X19
	    Predecessors according to CFG: BB#0 BB#3
384B		%vreg17<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg17
392B		%vreg18<def> = LDRWui <fi#1>, 0; mem:LD4[FixedStack1] GPR32:%vreg18
400B		%vreg16<def> = LDRWui %vreg17<kill>, 24; mem:LD4[%state_in_len] GPR32:%vreg16 GPR64common:%vreg17
416B		%WZR<def> = SUBSWrr %vreg18<kill>, %vreg16<kill>, %NZCV<imp-def>; GPR32:%vreg18,%vreg16
432B		Bcc 10, <BB#4>, %NZCV<imp-use,kill>
	    Successors according to CFG: BB#4 BB#2
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %W9<def> = LDRWui <fi#1>, 0; mem:LD4[FixedStack1]
> %W8<def> = LDRWui %X8<kill>, 24; mem:LD4[%state_in_len]
> %WZR<def> = SUBSWrr %W9<kill>, %W8<kill>, %NZCV<imp-def>
> Bcc 10, <BB#4>, %NZCV<imp-use,kill>
448B	BB#2: derived from LLVM BB %for.body
	    Live Ins: %X19
	    Predecessors according to CFG: BB#1
528B		%vreg314<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg314
532B		%vreg295<def> = ADRP <ga:@BZ2_crc32Table>[TF=1]; GPR64common:%vreg295
536B		%vreg317<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg317
544B		%vreg313<def> = LDRWui %vreg314<kill>, 162; mem:LD4[%blockCRC2] GPR32:%vreg313 GPR64common:%vreg314
576B		%vreg309<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg309
584B		%vreg296<def> = ADDXri %vreg295<kill>, <ga:@BZ2_crc32Table>[TF=34], 0; GPR64common:%vreg296,%vreg295
592B		%vreg316<def> = LDRWui %vreg317<kill>, 162; mem:LD4[%blockCRC] GPR32:%vreg316 GPR64common:%vreg317
600B		%vreg311<def> = UBFMWri %vreg313<kill>, 24, 31; GPR32:%vreg311,%vreg313
608B		%vreg302:sub_32<def,read-undef> = EORWrr %vreg311<kill>, %vreg309<kill>; GPR64:%vreg302 GPR32:%vreg311,%vreg309
624B		%vreg303<def> = UBFMXri %vreg302<kill>, 0, 31; GPR64:%vreg303,%vreg302
640B		%vreg298<def> = MOVi64imm 4; GPR64:%vreg298
656B		%vreg299<def> = MADDXrrr %vreg303<kill>, %vreg298<kill>, %XZR; GPR64:%vreg299,%vreg303,%vreg298
672B		%vreg300<def> = ADDXrr %vreg296<kill>, %vreg299<kill>; GPR64common:%vreg300,%vreg296 GPR64:%vreg299
688B		%vreg294<def> = LDRWui %vreg300<kill>, 0; mem:LD4[%arrayidx] GPR32:%vreg294 GPR64common:%vreg300
720B		%vreg289<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg289
728B		%vreg292<def> = EORWrs %vreg294<kill>, %vreg316<kill>, 8; GPR32:%vreg292,%vreg294,%vreg316
736B		STRWui %vreg292<kill>, %vreg289<kill>, 162; mem:ST4[%blockCRC5] GPR32:%vreg292 GPR64common:%vreg289
	    Successors according to CFG: BB#3
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %X9<def> = ADRP <ga:@BZ2_crc32Table>[TF=1]
> %X10<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %W8<def> = LDRWui %X8<kill>, 162; mem:LD4[%blockCRC2]
> %W11<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2]
> %X9<def> = ADDXri %X9<kill>, <ga:@BZ2_crc32Table>[TF=34], 0
> %W10<def> = LDRWui %X10<kill>, 162; mem:LD4[%blockCRC]
> %W8<def> = UBFMWri %W8<kill>, 24, 31
> %W8<def> = EORWrr %W8<kill>, %W11<kill>, %X8<imp-def>
> %X8<def> = UBFMXri %X8<kill>, 0, 31
> %X11<def> = MOVi64imm 4
> %X8<def> = MADDXrrr %X8<kill>, %X11<kill>, %XZR
> %X8<def> = ADDXrr %X9<kill>, %X8<kill>
> %W8<def> = LDRWui %X8<kill>, 0; mem:LD4[%arrayidx]
> %X9<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %W8<def> = EORWrs %W8<kill>, %W10<kill>, 8
> STRWui %W8<kill>, %X9<kill>, 162; mem:ST4[%blockCRC5]
752B	BB#3: derived from LLVM BB %for.inc
	    Live Ins: %X19
	    Predecessors according to CFG: BB#2
768B		%vreg321<def> = LDRWui <fi#1>, 0; mem:LD4[FixedStack1] GPR32common:%vreg321
784B		%vreg320<def> = ADDWri %vreg321<kill>, 1, 0; GPR32common:%vreg320,%vreg321
800B		STRWui %vreg320<kill>, <fi#1>, 0; mem:ST4[FixedStack1] GPR32common:%vreg320
816B		B <BB#1>
	    Successors according to CFG: BB#1
> %W8<def> = LDRWui <fi#1>, 0; mem:LD4[FixedStack1]
> %W8<def> = ADDWri %W8<kill>, 1, 0
> STRWui %W8<kill>, <fi#1>, 0; mem:ST4[FixedStack1]
> B <BB#1>
832B	BB#4: derived from LLVM BB %for.end
	    Live Ins: %X19
	    Predecessors according to CFG: BB#1
848B		%vreg20<def> = LDRXui <fi#0>, 0; mem:LD8[%s.addr] GPR64common:%vreg20
864B		%vreg22:sub_32<def,read-undef> = LDRWui %vreg20, 23; mem:LD4[%state_in_ch6] GPR64:%vreg22 GPR64common:%vreg20
896B		%vreg23<def> = ADDXrr %vreg20<kill>, %vreg22<kill>; GPR64common:%vreg23,%vreg20 GPR64:%vreg22
912B		%vreg24<def> = MOVi32imm 1; GPR32:%vreg24
928B		STRBBui %vreg24<kill>, %vreg23<kill>, 128; mem:ST1[%arrayidx8] GPR32:%vreg24 GPR64common:%vreg23
944B		%vreg25<def> = LDRXui <fi#0>, 0; mem:LD8[%s.addr] GPR64common:%vreg25
960B		%vreg19<def> = LDRWui %vreg25<kill>, 24; mem:LD4[%state_in_len9] GPR32common:%vreg19 GPR64common:%vreg25
992B		%vreg27<def,dead> = SUBSWri %vreg19, 1, 0, %NZCV<imp-def>; GPR32:%vreg27 GPR32common:%vreg19
1008B		Bcc 0, <BB#7>, %NZCV<imp-use,kill>
1024B		B <BB#5>
	    Successors according to CFG: BB#7 BB#5
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[%s.addr]
> %W9<def> = LDRWui %X8, 23, %X9<imp-def>; mem:LD4[%state_in_ch6]
> %X8<def> = ADDXrr %X8<kill>, %X9<kill>
> %W9<def> = MOVi32imm 1
> STRBBui %W9<kill>, %X8<kill>, 128; mem:ST1[%arrayidx8]
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[%s.addr]
> %W8<def> = LDRWui %X8<kill>, 24; mem:LD4[%state_in_len9]
> %W9<def,dead> = SUBSWri %W8, 1, 0, %NZCV<imp-def>
> Bcc 0, <BB#7>, %NZCV<imp-use,kill>
> B <BB#5>
1040B	BB#5: derived from LLVM BB %for.end
	    Live Ins: %W8 %X19
	    Predecessors according to CFG: BB#4
1056B		%vreg28<def,dead> = SUBSWri %vreg19, 2, 0, %NZCV<imp-def>; GPR32:%vreg28 GPR32common:%vreg19
1072B		Bcc 0, <BB#8>, %NZCV<imp-use,kill>
1088B		B <BB#6>
	    Successors according to CFG: BB#8 BB#6
> %W9<def,dead> = SUBSWri %W8, 2, 0, %NZCV<imp-def>
> Bcc 0, <BB#8>, %NZCV<imp-use,kill>
> B <BB#6>
1104B	BB#6: derived from LLVM BB %for.end
	    Live Ins: %W8 %X19
	    Predecessors according to CFG: BB#5
1120B		%vreg29<def,dead> = SUBSWri %vreg19<kill>, 3, 0, %NZCV<imp-def>; GPR32:%vreg29 GPR32common:%vreg19
1136B		Bcc 0, <BB#9>, %NZCV<imp-use,kill>
1152B		B <BB#10>
	    Successors according to CFG: BB#9 BB#10
> %W8<def,dead> = SUBSWri %W8<kill>, 3, 0, %NZCV<imp-def>
> Bcc 0, <BB#9>, %NZCV<imp-use,kill>
> B <BB#10>
1168B	BB#7: derived from LLVM BB %sw.bb
	    Live Ins: %X19
	    Predecessors according to CFG: BB#4
1200B		%vreg154<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg154
1232B		%vreg148<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg148
1240B		%vreg153<def> = LDRSWui %vreg154<kill>, 27; mem:LD4[%nblock] GPR64:%vreg153 GPR64common:%vreg154
1248B		%vreg147<def> = LDRXui %vreg148<kill>, 8; mem:LD8[%block] GPR64:%vreg147 GPR64common:%vreg148
1256B		%vreg155<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg155
1264B		%vreg145<def> = ADDXrr %vreg147<kill>, %vreg153<kill>; GPR64common:%vreg145 GPR64:%vreg147,%vreg153
1280B		STRBBui %vreg155<kill>, %vreg145<kill>, 0; mem:ST1[%arrayidx11] GPR32:%vreg155 GPR64common:%vreg145
1296B		%vreg140<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg140
1312B		%vreg139<def> = LDRWui %vreg140, 27; mem:LD4[%nblock12] GPR32common:%vreg139 GPR64common:%vreg140
1328B		%vreg138<def> = ADDWri %vreg139<kill>, 1, 0; GPR32common:%vreg138,%vreg139
1344B		STRWui %vreg138<kill>, %vreg140<kill>, 27; mem:ST4[%nblock12] GPR32common:%vreg138 GPR64common:%vreg140
1360B		B <BB#11>
	    Successors according to CFG: BB#11
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %X9<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %X8<def> = LDRSWui %X8<kill>, 27; mem:LD4[%nblock]
> %X9<def> = LDRXui %X9<kill>, 8; mem:LD8[%block]
> %W10<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2]
> %X8<def> = ADDXrr %X9<kill>, %X8<kill>
> STRBBui %W10<kill>, %X8<kill>, 0; mem:ST1[%arrayidx11]
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %W9<def> = LDRWui %X8, 27; mem:LD4[%nblock12]
> %W9<def> = ADDWri %W9<kill>, 1, 0
> STRWui %W9<kill>, %X8<kill>, 27; mem:ST4[%nblock12]
> B <BB#11>
1376B	BB#8: derived from LLVM BB %sw.bb.14
	    Live Ins: %X19
	    Predecessors according to CFG: BB#5
1408B		%vreg133<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg133
1440B		%vreg127<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg127
1448B		%vreg132<def> = LDRSWui %vreg133<kill>, 27; mem:LD4[%nblock15] GPR64:%vreg132 GPR64common:%vreg133
1456B		%vreg126<def> = LDRXui %vreg127<kill>, 8; mem:LD8[%block17] GPR64:%vreg126 GPR64common:%vreg127
1464B		%vreg134<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg134
1472B		%vreg124<def> = ADDXrr %vreg126<kill>, %vreg132<kill>; GPR64common:%vreg124 GPR64:%vreg126,%vreg132
1488B		STRBBui %vreg134<kill>, %vreg124<kill>, 0; mem:ST1[%arrayidx18] GPR32:%vreg134 GPR64common:%vreg124
1504B		%vreg119<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg119
1520B		%vreg118<def> = LDRWui %vreg119, 27; mem:LD4[%nblock19] GPR32common:%vreg118 GPR64common:%vreg119
1536B		%vreg117<def> = ADDWri %vreg118<kill>, 1, 0; GPR32common:%vreg117,%vreg118
1552B		STRWui %vreg117<kill>, %vreg119<kill>, 27; mem:ST4[%nblock19] GPR32common:%vreg117 GPR64common:%vreg119
1584B		%vreg112<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg112
1616B		%vreg106<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg106
1624B		%vreg111<def> = LDRSWui %vreg112<kill>, 27; mem:LD4[%nblock21] GPR64:%vreg111 GPR64common:%vreg112
1632B		%vreg105<def> = LDRXui %vreg106<kill>, 8; mem:LD8[%block23] GPR64:%vreg105 GPR64common:%vreg106
1640B		%vreg113<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg113
1648B		%vreg103<def> = ADDXrr %vreg105<kill>, %vreg111<kill>; GPR64common:%vreg103 GPR64:%vreg105,%vreg111
1664B		STRBBui %vreg113<kill>, %vreg103<kill>, 0; mem:ST1[%arrayidx24] GPR32:%vreg113 GPR64common:%vreg103
1680B		%vreg98<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg98
1696B		%vreg97<def> = LDRWui %vreg98, 27; mem:LD4[%nblock25] GPR32common:%vreg97 GPR64common:%vreg98
1712B		%vreg96<def> = ADDWri %vreg97<kill>, 1, 0; GPR32common:%vreg96,%vreg97
1728B		STRWui %vreg96<kill>, %vreg98<kill>, 27; mem:ST4[%nblock25] GPR32common:%vreg96 GPR64common:%vreg98
1744B		B <BB#11>
	    Successors according to CFG: BB#11
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %X9<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %X8<def> = LDRSWui %X8<kill>, 27; mem:LD4[%nblock15]
> %X9<def> = LDRXui %X9<kill>, 8; mem:LD8[%block17]
> %W10<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2]
> %X8<def> = ADDXrr %X9<kill>, %X8<kill>
> STRBBui %W10<kill>, %X8<kill>, 0; mem:ST1[%arrayidx18]
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %W9<def> = LDRWui %X8, 27; mem:LD4[%nblock19]
> %W9<def> = ADDWri %W9<kill>, 1, 0
> STRWui %W9<kill>, %X8<kill>, 27; mem:ST4[%nblock19]
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %X9<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %X8<def> = LDRSWui %X8<kill>, 27; mem:LD4[%nblock21]
> %X9<def> = LDRXui %X9<kill>, 8; mem:LD8[%block23]
> %W10<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2]
> %X8<def> = ADDXrr %X9<kill>, %X8<kill>
> STRBBui %W10<kill>, %X8<kill>, 0; mem:ST1[%arrayidx24]
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %W9<def> = LDRWui %X8, 27; mem:LD4[%nblock25]
> %W9<def> = ADDWri %W9<kill>, 1, 0
> STRWui %W9<kill>, %X8<kill>, 27; mem:ST4[%nblock25]
> B <BB#11>
1760B	BB#9: derived from LLVM BB %sw.bb.27
	    Live Ins: %X19
	    Predecessors according to CFG: BB#6
1792B		%vreg91<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg91
1824B		%vreg85<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg85
1832B		%vreg90<def> = LDRSWui %vreg91<kill>, 27; mem:LD4[%nblock28] GPR64:%vreg90 GPR64common:%vreg91
1840B		%vreg84<def> = LDRXui %vreg85<kill>, 8; mem:LD8[%block30] GPR64:%vreg84 GPR64common:%vreg85
1848B		%vreg92<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg92
1856B		%vreg82<def> = ADDXrr %vreg84<kill>, %vreg90<kill>; GPR64common:%vreg82 GPR64:%vreg84,%vreg90
1872B		STRBBui %vreg92<kill>, %vreg82<kill>, 0; mem:ST1[%arrayidx31] GPR32:%vreg92 GPR64common:%vreg82
1888B		%vreg77<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg77
1904B		%vreg76<def> = LDRWui %vreg77, 27; mem:LD4[%nblock32] GPR32common:%vreg76 GPR64common:%vreg77
1920B		%vreg75<def> = ADDWri %vreg76<kill>, 1, 0; GPR32common:%vreg75,%vreg76
1936B		STRWui %vreg75<kill>, %vreg77<kill>, 27; mem:ST4[%nblock32] GPR32common:%vreg75 GPR64common:%vreg77
1968B		%vreg70<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg70
2000B		%vreg64<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg64
2008B		%vreg69<def> = LDRSWui %vreg70<kill>, 27; mem:LD4[%nblock34] GPR64:%vreg69 GPR64common:%vreg70
2016B		%vreg63<def> = LDRXui %vreg64<kill>, 8; mem:LD8[%block36] GPR64:%vreg63 GPR64common:%vreg64
2024B		%vreg71<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg71
2032B		%vreg61<def> = ADDXrr %vreg63<kill>, %vreg69<kill>; GPR64common:%vreg61 GPR64:%vreg63,%vreg69
2048B		STRBBui %vreg71<kill>, %vreg61<kill>, 0; mem:ST1[%arrayidx37] GPR32:%vreg71 GPR64common:%vreg61
2064B		%vreg56<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg56
2080B		%vreg55<def> = LDRWui %vreg56, 27; mem:LD4[%nblock38] GPR32common:%vreg55 GPR64common:%vreg56
2096B		%vreg54<def> = ADDWri %vreg55<kill>, 1, 0; GPR32common:%vreg54,%vreg55
2112B		STRWui %vreg54<kill>, %vreg56<kill>, 27; mem:ST4[%nblock38] GPR32common:%vreg54 GPR64common:%vreg56
2144B		%vreg49<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg49
2176B		%vreg43<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg43
2184B		%vreg48<def> = LDRSWui %vreg49<kill>, 27; mem:LD4[%nblock40] GPR64:%vreg48 GPR64common:%vreg49
2192B		%vreg42<def> = LDRXui %vreg43<kill>, 8; mem:LD8[%block42] GPR64:%vreg42 GPR64common:%vreg43
2200B		%vreg50<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg50
2208B		%vreg40<def> = ADDXrr %vreg42<kill>, %vreg48<kill>; GPR64common:%vreg40 GPR64:%vreg42,%vreg48
2224B		STRBBui %vreg50<kill>, %vreg40<kill>, 0; mem:ST1[%arrayidx43] GPR32:%vreg50 GPR64common:%vreg40
2240B		%vreg35<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg35
2256B		%vreg34<def> = LDRWui %vreg35, 27; mem:LD4[%nblock44] GPR32common:%vreg34 GPR64common:%vreg35
2272B		%vreg33<def> = ADDWri %vreg34<kill>, 1, 0; GPR32common:%vreg33,%vreg34
2288B		STRWui %vreg33<kill>, %vreg35<kill>, 27; mem:ST4[%nblock44] GPR32common:%vreg33 GPR64common:%vreg35
2304B		B <BB#11>
	    Successors according to CFG: BB#11
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %X9<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %X8<def> = LDRSWui %X8<kill>, 27; mem:LD4[%nblock28]
> %X9<def> = LDRXui %X9<kill>, 8; mem:LD8[%block30]
> %W10<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2]
> %X8<def> = ADDXrr %X9<kill>, %X8<kill>
> STRBBui %W10<kill>, %X8<kill>, 0; mem:ST1[%arrayidx31]
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %W9<def> = LDRWui %X8, 27; mem:LD4[%nblock32]
> %W9<def> = ADDWri %W9<kill>, 1, 0
> STRWui %W9<kill>, %X8<kill>, 27; mem:ST4[%nblock32]
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %X9<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %X8<def> = LDRSWui %X8<kill>, 27; mem:LD4[%nblock34]
> %X9<def> = LDRXui %X9<kill>, 8; mem:LD8[%block36]
> %W10<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2]
> %X8<def> = ADDXrr %X9<kill>, %X8<kill>
> STRBBui %W10<kill>, %X8<kill>, 0; mem:ST1[%arrayidx37]
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %W9<def> = LDRWui %X8, 27; mem:LD4[%nblock38]
> %W9<def> = ADDWri %W9<kill>, 1, 0
> STRWui %W9<kill>, %X8<kill>, 27; mem:ST4[%nblock38]
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %X9<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %X8<def> = LDRSWui %X8<kill>, 27; mem:LD4[%nblock40]
> %X9<def> = LDRXui %X9<kill>, 8; mem:LD8[%block42]
> %W10<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2]
> %X8<def> = ADDXrr %X9<kill>, %X8<kill>
> STRBBui %W10<kill>, %X8<kill>, 0; mem:ST1[%arrayidx43]
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %W9<def> = LDRWui %X8, 27; mem:LD4[%nblock44]
> %W9<def> = ADDWri %W9<kill>, 1, 0
> STRWui %W9<kill>, %X8<kill>, 27; mem:ST4[%nblock44]
> B <BB#11>
2320B	BB#10: derived from LLVM BB %sw.default
	    Live Ins: %X19
	    Predecessors according to CFG: BB#6
2352B		%vreg282<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg282
2432B		%vreg274<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg274
2436B		%vreg281<def> = LDRWui %vreg282<kill>, 24; mem:LD4[%state_in_len46] GPR32common:%vreg281 GPR64common:%vreg282
2440B		%vreg267<def> = MOVi32imm 1; GPR32:%vreg267
2448B		%vreg273<def> = ADDXri %vreg274<kill>, 128, 0; GPR64common:%vreg273,%vreg274
2452B		%vreg276:sub_32<def,read-undef> = SUBWri %vreg281<kill>, 4, 0; GPR64common:%vreg276 GPR32common:%vreg281
2456B		%vreg277<def> = SBFMXri %vreg276<kill>, 0, 31; GPR64:%vreg277 GPR64common:%vreg276
2464B		%vreg271<def> = ADDXrr %vreg273<kill>, %vreg277<kill>; GPR64common:%vreg271,%vreg273 GPR64:%vreg277
2480B		STRBBui %vreg267<kill>, %vreg271<kill>, 0; mem:ST1[%arrayidx49] GPR32:%vreg267 GPR64common:%vreg271
2512B		%vreg265<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg265
2544B		%vreg259<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg259
2552B		%vreg264<def> = LDRSWui %vreg265<kill>, 27; mem:LD4[%nblock50] GPR64:%vreg264 GPR64common:%vreg265
2560B		%vreg258<def> = LDRXui %vreg259<kill>, 8; mem:LD8[%block52] GPR64:%vreg258 GPR64common:%vreg259
2568B		%vreg266<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg266
2576B		%vreg256<def> = ADDXrr %vreg258<kill>, %vreg264<kill>; GPR64common:%vreg256 GPR64:%vreg258,%vreg264
2592B		STRBBui %vreg266<kill>, %vreg256<kill>, 0; mem:ST1[%arrayidx53] GPR32:%vreg266 GPR64common:%vreg256
2608B		%vreg251<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg251
2624B		%vreg250<def> = LDRWui %vreg251, 27; mem:LD4[%nblock54] GPR32common:%vreg250 GPR64common:%vreg251
2640B		%vreg249<def> = ADDWri %vreg250<kill>, 1, 0; GPR32common:%vreg249,%vreg250
2656B		STRWui %vreg249<kill>, %vreg251<kill>, 27; mem:ST4[%nblock54] GPR32common:%vreg249 GPR64common:%vreg251
2688B		%vreg244<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg244
2720B		%vreg238<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg238
2728B		%vreg243<def> = LDRSWui %vreg244<kill>, 27; mem:LD4[%nblock56] GPR64:%vreg243 GPR64common:%vreg244
2736B		%vreg237<def> = LDRXui %vreg238<kill>, 8; mem:LD8[%block58] GPR64:%vreg237 GPR64common:%vreg238
2744B		%vreg245<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg245
2752B		%vreg235<def> = ADDXrr %vreg237<kill>, %vreg243<kill>; GPR64common:%vreg235 GPR64:%vreg237,%vreg243
2768B		STRBBui %vreg245<kill>, %vreg235<kill>, 0; mem:ST1[%arrayidx59] GPR32:%vreg245 GPR64common:%vreg235
2784B		%vreg230<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg230
2800B		%vreg229<def> = LDRWui %vreg230, 27; mem:LD4[%nblock60] GPR32common:%vreg229 GPR64common:%vreg230
2816B		%vreg228<def> = ADDWri %vreg229<kill>, 1, 0; GPR32common:%vreg228,%vreg229
2832B		STRWui %vreg228<kill>, %vreg230<kill>, 27; mem:ST4[%nblock60] GPR32common:%vreg228 GPR64common:%vreg230
2864B		%vreg223<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg223
2896B		%vreg217<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg217
2904B		%vreg222<def> = LDRSWui %vreg223<kill>, 27; mem:LD4[%nblock62] GPR64:%vreg222 GPR64common:%vreg223
2912B		%vreg216<def> = LDRXui %vreg217<kill>, 8; mem:LD8[%block64] GPR64:%vreg216 GPR64common:%vreg217
2920B		%vreg224<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg224
2928B		%vreg214<def> = ADDXrr %vreg216<kill>, %vreg222<kill>; GPR64common:%vreg214 GPR64:%vreg216,%vreg222
2944B		STRBBui %vreg224<kill>, %vreg214<kill>, 0; mem:ST1[%arrayidx65] GPR32:%vreg224 GPR64common:%vreg214
2960B		%vreg209<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg209
2976B		%vreg208<def> = LDRWui %vreg209, 27; mem:LD4[%nblock66] GPR32common:%vreg208 GPR64common:%vreg209
2992B		%vreg207<def> = ADDWri %vreg208<kill>, 1, 0; GPR32common:%vreg207,%vreg208
3008B		STRWui %vreg207<kill>, %vreg209<kill>, 27; mem:ST4[%nblock66] GPR32common:%vreg207 GPR64common:%vreg209
3040B		%vreg202<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg202
3072B		%vreg196<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg196
3080B		%vreg201<def> = LDRSWui %vreg202<kill>, 27; mem:LD4[%nblock68] GPR64:%vreg201 GPR64common:%vreg202
3088B		%vreg195<def> = LDRXui %vreg196<kill>, 8; mem:LD8[%block70] GPR64:%vreg195 GPR64common:%vreg196
3096B		%vreg203<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2] GPR32:%vreg203
3104B		%vreg193<def> = ADDXrr %vreg195<kill>, %vreg201<kill>; GPR64common:%vreg193 GPR64:%vreg195,%vreg201
3120B		STRBBui %vreg203<kill>, %vreg193<kill>, 0; mem:ST1[%arrayidx71] GPR32:%vreg203 GPR64common:%vreg193
3136B		%vreg188<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg188
3152B		%vreg187<def> = LDRWui %vreg188, 27; mem:LD4[%nblock72] GPR32common:%vreg187 GPR64common:%vreg188
3168B		%vreg186<def> = ADDWri %vreg187<kill>, 1, 0; GPR32common:%vreg186,%vreg187
3184B		STRWui %vreg186<kill>, %vreg188<kill>, 27; mem:ST4[%nblock72] GPR32common:%vreg186 GPR64common:%vreg188
3200B		%vreg182<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg182
3264B		%vreg175<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg175
3296B		%vreg169<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg169
3300B		%vreg181<def> = LDRWui %vreg182<kill>, 24; mem:LD4[%state_in_len74] GPR32common:%vreg181 GPR64common:%vreg182
3304B		%vreg174<def> = LDRSWui %vreg175<kill>, 27; mem:LD4[%nblock77] GPR64:%vreg174 GPR64common:%vreg175
3312B		%vreg168<def> = LDRXui %vreg169<kill>, 8; mem:LD8[%block79] GPR64:%vreg168 GPR64common:%vreg169
3320B		%vreg177<def> = SUBWri %vreg181<kill>, 4, 0; GPR32common:%vreg177,%vreg181
3328B		%vreg166<def> = ADDXrr %vreg168<kill>, %vreg174<kill>; GPR64common:%vreg166 GPR64:%vreg168,%vreg174
3344B		STRBBui %vreg177<kill>, %vreg166<kill>, 0; mem:ST1[%arrayidx80] GPR32common:%vreg177 GPR64common:%vreg166
3360B		%vreg161<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0] GPR64common:%vreg161
3376B		%vreg160<def> = LDRWui %vreg161, 27; mem:LD4[%nblock81] GPR32common:%vreg160 GPR64common:%vreg161
3392B		%vreg159<def> = ADDWri %vreg160<kill>, 1, 0; GPR32common:%vreg159,%vreg160
3408B		STRWui %vreg159<kill>, %vreg161<kill>, 27; mem:ST4[%nblock81] GPR32common:%vreg159 GPR64common:%vreg161
	    Successors according to CFG: BB#11
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %X9<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %W8<def> = LDRWui %X8<kill>, 24; mem:LD4[%state_in_len46]
> %W10<def> = MOVi32imm 1
> %X9<def> = ADDXri %X9<kill>, 128, 0
> %W8<def> = SUBWri %W8<kill>, 4, 0, %X8<imp-def>
> %X8<def> = SBFMXri %X8<kill>, 0, 31
> %X8<def> = ADDXrr %X9<kill>, %X8<kill>
> STRBBui %W10<kill>, %X8<kill>, 0; mem:ST1[%arrayidx49]
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %X9<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %X8<def> = LDRSWui %X8<kill>, 27; mem:LD4[%nblock50]
> %X9<def> = LDRXui %X9<kill>, 8; mem:LD8[%block52]
> %W10<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2]
> %X8<def> = ADDXrr %X9<kill>, %X8<kill>
> STRBBui %W10<kill>, %X8<kill>, 0; mem:ST1[%arrayidx53]
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %W9<def> = LDRWui %X8, 27; mem:LD4[%nblock54]
> %W9<def> = ADDWri %W9<kill>, 1, 0
> STRWui %W9<kill>, %X8<kill>, 27; mem:ST4[%nblock54]
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %X9<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %X8<def> = LDRSWui %X8<kill>, 27; mem:LD4[%nblock56]
> %X9<def> = LDRXui %X9<kill>, 8; mem:LD8[%block58]
> %W10<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2]
> %X8<def> = ADDXrr %X9<kill>, %X8<kill>
> STRBBui %W10<kill>, %X8<kill>, 0; mem:ST1[%arrayidx59]
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %W9<def> = LDRWui %X8, 27; mem:LD4[%nblock60]
> %W9<def> = ADDWri %W9<kill>, 1, 0
> STRWui %W9<kill>, %X8<kill>, 27; mem:ST4[%nblock60]
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %X9<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %X8<def> = LDRSWui %X8<kill>, 27; mem:LD4[%nblock62]
> %X9<def> = LDRXui %X9<kill>, 8; mem:LD8[%block64]
> %W10<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2]
> %X8<def> = ADDXrr %X9<kill>, %X8<kill>
> STRBBui %W10<kill>, %X8<kill>, 0; mem:ST1[%arrayidx65]
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %W9<def> = LDRWui %X8, 27; mem:LD4[%nblock66]
> %W9<def> = ADDWri %W9<kill>, 1, 0
> STRWui %W9<kill>, %X8<kill>, 27; mem:ST4[%nblock66]
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %X9<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %X8<def> = LDRSWui %X8<kill>, 27; mem:LD4[%nblock68]
> %X9<def> = LDRXui %X9<kill>, 8; mem:LD8[%block70]
> %W10<def> = LDRBBui <fi#2>, 0; mem:LD1[FixedStack2]
> %X8<def> = ADDXrr %X9<kill>, %X8<kill>
> STRBBui %W10<kill>, %X8<kill>, 0; mem:ST1[%arrayidx71]
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %W9<def> = LDRWui %X8, 27; mem:LD4[%nblock72]
> %W9<def> = ADDWri %W9<kill>, 1, 0
> STRWui %W9<kill>, %X8<kill>, 27; mem:ST4[%nblock72]
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %X9<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %X10<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %W8<def> = LDRWui %X8<kill>, 24; mem:LD4[%state_in_len74]
> %X9<def> = LDRSWui %X9<kill>, 27; mem:LD4[%nblock77]
> %X10<def> = LDRXui %X10<kill>, 8; mem:LD8[%block79]
> %W8<def> = SUBWri %W8<kill>, 4, 0
> %X9<def> = ADDXrr %X10<kill>, %X9<kill>
> STRBBui %W8<kill>, %X9<kill>, 0; mem:ST1[%arrayidx80]
> %X8<def> = LDRXui <fi#0>, 0; mem:LD8[FixedStack0]
> %W9<def> = LDRWui %X8, 27; mem:LD4[%nblock81]
> %W9<def> = ADDWri %W9<kill>, 1, 0
> STRWui %W9<kill>, %X8<kill>, 27; mem:ST4[%nblock81]
3424B	BB#11: derived from LLVM BB %sw.epilog
	    Live Ins: %X19
	    Predecessors according to CFG: BB#9 BB#8 BB#7 BB#10
3440B		%vreg283<def> = ADRP <ga:@add_pair_to_block>[TF=1]; GPR64common:%vreg283
3456B		%vreg285<def> = ADDXri %vreg283<kill>, <ga:@add_pair_to_block>[TF=34], 0; GPR64sp:%vreg285 GPR64common:%vreg283
3504B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3520B		%X0<def> = COPY %vreg285<kill>; GPR64sp:%vreg285
3536B		%X1<def> = COPY %vreg11<kill>; GPR64:%vreg11
3552B		BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
3568B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3584B		ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
3600B		STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...
3616B		ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
3632B		RET_ReallyLR
> %X8<def> = ADRP <ga:@add_pair_to_block>[TF=1]
> %X0<def> = ADDXri %X8<kill>, <ga:@add_pair_to_block>[TF=34], 0
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> %X0<def> = COPY %X0<kill>
Deleting identity copy.
> %X1<def> = COPY %X19<kill>
> BL <ga:@__cyg_profile_func_exit>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %X0<imp-use>, %X1<imp-use,kill>
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> ADJCALLSTACKDOWN 0, %SP<imp-def>, %SP<imp-use>
> STACKMAP 1, 0, %LR<earlyclobber,imp-def,dead>, ...
> ADJCALLSTACKUP 0, 0, %SP<imp-def>, %SP<imp-use>
> RET_ReallyLR
Computing live-in reg-units in ABI blocks.
0B	BB#0 DIL#0
Created 1 new intervals.
********** INTERVALS **********
DIL [0B,16r:0)[112r,144r:3)[416r,496r:4)[688r,736r:2)[880r,896r:1)  0@0B-phi 1@880r 2@688r 3@112r 4@416r
%vreg0 [16r,32r:0)  0@16r
%vreg1 [32r,224r:0)  0@32r
%vreg4 [336r,432r:0)  0@336r
%vreg7 [528r,528d:0)  0@528r
%vreg8 [320r,464r:0)  0@320r
%vreg9 [256r,448r:0)  0@256r
%vreg10 [240r,416r:0)  0@240r
%vreg11 [48r,64r:0)  0@48r
%vreg12 [64r,112r:0)  0@64r
%vreg13 [80r,128r:0)  0@80r
%vreg15 [640r,704r:0)  0@640r
%vreg16 [768r,768d:0)  0@768r
%vreg17 [656r,688r:0)  0@656r
%vreg18 [848r,880r:0)  0@848r
RegMasks: 144r 288r 496r 736r 896r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bz__AssertH__fail: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=4, align=4, at location [SP+8]
Function Live Ins: %EDI in %vreg0

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %EDI
16B		%vreg0<def> = COPY %EDI; GR32:%vreg0
32B		%vreg1<def> = COPY %vreg0; GR32:%vreg1,%vreg0
48B		%vreg11<def> = MOV64ri <ga:@BZ2_bz__AssertH__fail>; GR64:%vreg11
64B		%vreg12<def> = COPY %vreg11; GR64:%vreg12,%vreg11
80B		%vreg13<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg13
96B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
112B		%RDI<def> = COPY %vreg12; GR64:%vreg12
128B		%RSI<def> = COPY %vreg13; GR64:%vreg13
144B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
160B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
192B		STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4) GR32:%vreg1
208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1; mem:ST4[%errcode.addr] GR32:%vreg1
240B		%vreg10<def> = MOV64rm %noreg, 1, %noreg, <ga:@stderr>, %noreg; mem:LD8[@stderr] GR64:%vreg10
256B		%vreg9<def> = MOV32rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD4[%errcode.addr] GR32:%vreg9
272B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
288B		CALL64pcrel32 <ga:@BZ2_bzlibVersion>, <regmask>, %RSP<imp-use>, %RAX<imp-def>
304B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
320B		%vreg8<def> = COPY %RAX<kill>; GR64:%vreg8
336B		%vreg4<def> = MOV64ri <ga:@bzlib__str___bzip2_li>; GR64:%vreg4
352B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
368B		STACKMAP 1, 0, 0, <fi#0>, 0, %vreg9, %vreg10, ...; mem:LD8[FixedStack0](align=4) GR32:%vreg9 GR64:%vreg10
384B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
400B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
416B		%RDI<def> = COPY %vreg10; GR64:%vreg10
432B		%RSI<def> = COPY %vreg4; GR64:%vreg4
448B		%EDX<def> = COPY %vreg9; GR32:%vreg9
464B		%RCX<def> = COPY %vreg8; GR64:%vreg8
480B		%AL<def> = MOV8ri 0
496B		CALL64pcrel32 <ga:@fprintf>, <regmask>, %RSP<imp-use>, %AL<imp-use,kill>, %RDI<imp-use>, %RSI<imp-use,kill>, %EDX<imp-use,kill>, %RCX<imp-use,kill>, %EAX<imp-def>
512B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
528B		%vreg7<def,dead> = COPY %EAX<kill>; GR32:%vreg7
544B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
560B		STACKMAP 2, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
576B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
592B		CMP32mi <fi#0>, 1, %noreg, 0, %noreg, 1007, %EFLAGS<imp-def>; mem:LD4[%errcode.addr]
608B		JNE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

624B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
640B		%vreg15<def> = MOV64ri <ga:@bzlib__str_1______A_spe>; GR64:%vreg15
656B		%vreg17<def> = MOV64rm %noreg, 1, %noreg, <ga:@stderr>, %noreg; mem:LD8[@stderr] GR64:%vreg17
672B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
688B		%RDI<def> = COPY %vreg17; GR64:%vreg17
704B		%RSI<def> = COPY %vreg15; GR64:%vreg15
720B		%AL<def> = MOV8ri 0
736B		CALL64pcrel32 <ga:@fprintf>, <regmask>, %RSP<imp-use>, %AL<imp-use,kill>, %RDI<imp-use>, %RSI<imp-use,kill>, %EAX<imp-def>
752B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
768B		%vreg16<def,dead> = COPY %EAX<kill>; GR32:%vreg16
784B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
800B		STACKMAP 3, 0, ...
816B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#2

832B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#1
848B		%vreg18<def> = MOV32ri 3; GR32:%vreg18
864B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
880B		%EDI<def> = COPY %vreg18; GR32:%vreg18
896B		CALL64pcrel32 <ga:@exit>, <regmask>, %RSP<imp-use>, %EDI<imp-use>
912B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
928B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
944B		STACKMAP 4, 0, ...
960B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>

# End machine code for function BZ2_bz__AssertH__fail.

********** SIMPLE REGISTER COALESCING **********
********** Function: BZ2_bz__AssertH__fail
********** JOINING INTERVALS ***********
entry:
16B	%vreg0<def> = COPY %EDI; GR32:%vreg0
	Considering merging %vreg0 with %EDI
	Can only merge into reserved registers.
112B	%RDI<def> = COPY %vreg12; GR64:%vreg12
	Considering merging %vreg12 with %RDI
	Can only merge into reserved registers.
128B	%RSI<def> = COPY %vreg13; GR64:%vreg13
	Considering merging %vreg13 with %RSI
	Can only merge into reserved registers.
320B	%vreg8<def> = COPY %RAX<kill>; GR64:%vreg8
	Considering merging %vreg8 with %RAX
	Can only merge into reserved registers.
416B	%RDI<def> = COPY %vreg10; GR64:%vreg10
	Considering merging %vreg10 with %RDI
	Can only merge into reserved registers.
432B	%RSI<def> = COPY %vreg4; GR64:%vreg4
	Considering merging %vreg4 with %RSI
	Can only merge into reserved registers.
448B	%EDX<def> = COPY %vreg9; GR32:%vreg9
	Considering merging %vreg9 with %EDX
	Can only merge into reserved registers.
464B	%RCX<def> = COPY %vreg8; GR64:%vreg8
	Considering merging %vreg8 with %RCX
	Can only merge into reserved registers.
528B	%vreg7<def,dead> = COPY %EAX<kill>; GR32:%vreg7
	Considering merging %vreg7 with %EAX
	Can only merge into reserved registers.
if.then:
688B	%RDI<def> = COPY %vreg17; GR64:%vreg17
	Considering merging %vreg17 with %RDI
	Can only merge into reserved registers.
704B	%RSI<def> = COPY %vreg15; GR64:%vreg15
	Considering merging %vreg15 with %RSI
	Can only merge into reserved registers.
768B	%vreg16<def,dead> = COPY %EAX<kill>; GR32:%vreg16
	Considering merging %vreg16 with %EAX
	Can only merge into reserved registers.
if.end:
880B	%EDI<def> = COPY %vreg18; GR32:%vreg18
	Considering merging %vreg18 with %EDI
	Can only merge into reserved registers.
Remat: %EDI<def> = MOV32ri 3
Shrink: %vreg18 [848r,880r:0)  0@848r
All defs dead: 848r	%vreg18<def,dead> = MOV32ri 3; GR32:%vreg18
Shrunk: %vreg18 [848r,848d:0)  0@848r
Deleting dead def 848r	%vreg18<def,dead> = MOV32ri 3; GR32:%vreg18
32B	%vreg1<def> = COPY %vreg0; GR32:%vreg1,%vreg0
	Considering merging to GR32 with %vreg0 in %vreg1
		RHS = %vreg0 [16r,32r:0)  0@16r
		LHS = %vreg1 [32r,224r:0)  0@32r
		merge %vreg1:0@32r into %vreg0:0@16r --> @16r
		erased:	32r	%vreg1<def> = COPY %vreg0; GR32:%vreg1,%vreg0
AllocationOrder(GR32) = [ %EAX %ECX %EDX %ESI %EDI %R8D %R9D %R10D %R11D %EBX %R14D %R15D %R12D %R13D ]
		updated: 16B	%vreg1<def> = COPY %EDI; GR32:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [16r,224r:0)  0@16r
64B	%vreg12<def> = COPY %vreg11; GR64:%vreg12,%vreg11
	Considering merging to GR64 with %vreg11 in %vreg12
		RHS = %vreg11 [48r,64r:0)  0@48r
		LHS = %vreg12 [64r,112r:0)  0@64r
		merge %vreg12:0@64r into %vreg11:0@48r --> @48r
		erased:	64r	%vreg12<def> = COPY %vreg11; GR64:%vreg12,%vreg11
AllocationOrder(GR64) = [ %RAX %RCX %RDX %RSI %RDI %R8 %R9 %R10 %R11 %RBX %R14 %R15 %R12 %R13 ]
		updated: 48B	%vreg12<def> = MOV64ri <ga:@BZ2_bz__AssertH__fail>; GR64:%vreg12
	Success: %vreg11 -> %vreg12
	Result = %vreg12 [48r,112r:0)  0@48r
112B	%RDI<def> = COPY %vreg12; GR64:%vreg12
	Considering merging %vreg12 with %RDI
	Can only merge into reserved registers.
464B	%RCX<def> = COPY %vreg8; GR64:%vreg8
	Considering merging %vreg8 with %RCX
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
DIL [0B,16r:0)[112r,144r:3)[416r,496r:4)[688r,736r:2)[880r,896r:1)  0@0B-phi 1@880r 2@688r 3@112r 4@416r
%vreg1 [16r,224r:0)  0@16r
%vreg4 [336r,432r:0)  0@336r
%vreg7 [528r,528d:0)  0@528r
%vreg8 [320r,464r:0)  0@320r
%vreg9 [256r,448r:0)  0@256r
%vreg10 [240r,416r:0)  0@240r
%vreg12 [48r,112r:0)  0@48r
%vreg13 [80r,128r:0)  0@80r
%vreg15 [640r,704r:0)  0@640r
%vreg16 [768r,768d:0)  0@768r
%vreg17 [656r,688r:0)  0@656r
RegMasks: 144r 288r 496r 736r 896r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bz__AssertH__fail: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=4, align=4, at location [SP+8]
Function Live Ins: %EDI in %vreg0

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %EDI
16B		%vreg1<def> = COPY %EDI; GR32:%vreg1
48B		%vreg12<def> = MOV64ri <ga:@BZ2_bz__AssertH__fail>; GR64:%vreg12
80B		%vreg13<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg13
96B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
112B		%RDI<def> = COPY %vreg12; GR64:%vreg12
128B		%RSI<def> = COPY %vreg13; GR64:%vreg13
144B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
160B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
192B		STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4) GR32:%vreg1
208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1; mem:ST4[%errcode.addr] GR32:%vreg1
240B		%vreg10<def> = MOV64rm %noreg, 1, %noreg, <ga:@stderr>, %noreg; mem:LD8[@stderr] GR64:%vreg10
256B		%vreg9<def> = MOV32rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD4[%errcode.addr] GR32:%vreg9
272B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
288B		CALL64pcrel32 <ga:@BZ2_bzlibVersion>, <regmask>, %RSP<imp-use>, %RAX<imp-def>
304B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
320B		%vreg8<def> = COPY %RAX<kill>; GR64:%vreg8
336B		%vreg4<def> = MOV64ri <ga:@bzlib__str___bzip2_li>; GR64:%vreg4
352B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
368B		STACKMAP 1, 0, 0, <fi#0>, 0, %vreg9, %vreg10, ...; mem:LD8[FixedStack0](align=4) GR32:%vreg9 GR64:%vreg10
384B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
400B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
416B		%RDI<def> = COPY %vreg10; GR64:%vreg10
432B		%RSI<def> = COPY %vreg4; GR64:%vreg4
448B		%EDX<def> = COPY %vreg9; GR32:%vreg9
464B		%RCX<def> = COPY %vreg8; GR64:%vreg8
480B		%AL<def> = MOV8ri 0
496B		CALL64pcrel32 <ga:@fprintf>, <regmask>, %RSP<imp-use>, %AL<imp-use,kill>, %RDI<imp-use>, %RSI<imp-use,kill>, %EDX<imp-use,kill>, %RCX<imp-use,kill>, %EAX<imp-def>
512B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
528B		%vreg7<def,dead> = COPY %EAX<kill>; GR32:%vreg7
544B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
560B		STACKMAP 2, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
576B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
592B		CMP32mi <fi#0>, 1, %noreg, 0, %noreg, 1007, %EFLAGS<imp-def>; mem:LD4[%errcode.addr]
608B		JNE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

624B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
640B		%vreg15<def> = MOV64ri <ga:@bzlib__str_1______A_spe>; GR64:%vreg15
656B		%vreg17<def> = MOV64rm %noreg, 1, %noreg, <ga:@stderr>, %noreg; mem:LD8[@stderr] GR64:%vreg17
672B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
688B		%RDI<def> = COPY %vreg17; GR64:%vreg17
704B		%RSI<def> = COPY %vreg15; GR64:%vreg15
720B		%AL<def> = MOV8ri 0
736B		CALL64pcrel32 <ga:@fprintf>, <regmask>, %RSP<imp-use>, %AL<imp-use,kill>, %RDI<imp-use>, %RSI<imp-use,kill>, %EAX<imp-def>
752B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
768B		%vreg16<def,dead> = COPY %EAX<kill>; GR32:%vreg16
784B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
800B		STACKMAP 3, 0, ...
816B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#2

832B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#1
864B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
880B		%EDI<def> = MOV32ri 3
896B		CALL64pcrel32 <ga:@exit>, <regmask>, %RSP<imp-use>, %EDI<imp-use>
912B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
928B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
944B		STACKMAP 4, 0, ...
960B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>

# End machine code for function BZ2_bz__AssertH__fail.

AllocationOrder(GR32) = [ %EAX %ECX %EDX %ESI %EDI %R8D %R9D %R10D %R11D %EBX %R14D %R15D %R12D %R13D ]
AllocationOrder(GR16) = [ %AX %CX %DX %SI %DI %R8W %R9W %R10W %R11W %BX %R14W %R15W %R12W %R13W ]
AllocationOrder(GR8) = [ %AL %CL %DL %SIL %DIL %R8B %R9B %R10B %R11B %BL %R14B %R15B %R12B %R13B ]
handleMove 464B -> 488B: %RCX<def> = COPY %vreg8; GR64:%vreg8
     CH:	[488r,496r:0)  0@488r
        -->	[488r,496r:0)  0@488r
     CL:	[488r,496r:0)  0@488r
        -->	[488r,496r:0)  0@488r
     %vreg8:	[320r,464r:0)  0@320r
        -->	[320r,488r:0)  0@320r
handleMove 448B -> 484B: %EDX<def> = COPY %vreg9; GR32:%vreg9
     DH:	[484r,496r:0)  0@484r
        -->	[484r,496r:0)  0@484r
     DL:	[484r,496r:0)  0@484r
        -->	[484r,496r:0)  0@484r
     %vreg9:	[256r,448r:0)  0@256r
        -->	[256r,484r:0)  0@256r
handleMove 432B -> 488B: %RSI<def> = COPY %vreg4; GR64:%vreg4
     SIL:	[128r,144r:1)[488r,512r:2)[704r,736r:0)  0@704r 1@128r 2@488r
        -->	[128r,144r:1)[488r,512r:2)[704r,736r:0)  0@704r 1@128r 2@488r
     %vreg4:	[336r,432r:0)  0@336r
        -->	[336r,488r:0)  0@336r
handleMove 416B -> 484B: %RDI<def> = COPY %vreg10; GR64:%vreg10
     DIL:	[0B,16r:0)[112r,144r:3)[416r,512r:4)[688r,736r:2)[880r,896r:1)  0@0B-phi 1@880r 2@688r 3@112r 4@416r
        -->	[0B,16r:0)[112r,144r:3)[484r,512r:4)[688r,736r:2)[880r,896r:1)  0@0B-phi 1@880r 2@688r 3@112r 4@484r
     %vreg10:	[240r,416r:0)  0@240r
        -->	[240r,484r:0)  0@240r
handleMove 704B -> 728B: %RSI<def> = COPY %vreg15; GR64:%vreg15
     SIL:	[128r,144r:1)[488r,512r:2)[704r,736r:0)  0@704r 1@128r 2@488r
        -->	[128r,144r:1)[488r,512r:2)[728r,736r:0)  0@728r 1@128r 2@488r
     %vreg15:	[640r,704r:0)  0@640r
        -->	[640r,728r:0)  0@640r
handleMove 688B -> 724B: %RDI<def> = COPY %vreg17; GR64:%vreg17
     DIL:	[0B,16r:0)[112r,144r:3)[484r,512r:4)[688r,736r:2)[880r,896r:1)  0@0B-phi 1@880r 2@688r 3@112r 4@484r
        -->	[0B,16r:0)[112r,144r:3)[484r,512r:4)[724r,736r:2)[880r,896r:1)  0@0B-phi 1@880r 2@724r 3@112r 4@484r
     %vreg17:	[656r,688r:0)  0@656r
        -->	[656r,724r:0)  0@656r
********** GREEDY REGISTER ALLOCATION **********
********** Function: BZ2_bz__AssertH__fail
********** INTERVALS **********
CH [504r,512r:0)  0@504r
CL [504r,512r:0)  0@504r
DH [496r,512r:0)  0@496r
DIL [0B,16r:0)[112r,144r:3)[484r,512r:4)[724r,736r:2)[880r,896r:1)  0@0B-phi 1@880r 2@724r 3@112r 4@484r
DL [496r,512r:0)  0@496r
SIL [128r,144r:1)[488r,512r:2)[728r,736r:0)  0@728r 1@128r 2@488r
%vreg1 [16r,224r:0)  0@16r
%vreg4 [336r,488r:0)  0@336r
%vreg7 [528r,528d:0)  0@528r
%vreg8 [320r,504r:0)  0@320r
%vreg9 [256r,496r:0)  0@256r
%vreg10 [240r,484r:0)  0@240r
%vreg12 [48r,112r:0)  0@48r
%vreg13 [80r,128r:0)  0@80r
%vreg15 [640r,728r:0)  0@640r
%vreg16 [768r,768d:0)  0@768r
%vreg17 [656r,724r:0)  0@656r
RegMasks: 144r 288r 512r 736r 896r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bz__AssertH__fail: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=4, align=4, at location [SP+8]
Function Live Ins: %EDI in %vreg0

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %EDI
16B		%vreg1<def> = COPY %EDI; GR32:%vreg1
48B		%vreg12<def> = MOV64ri <ga:@BZ2_bz__AssertH__fail>; GR64:%vreg12
80B		%vreg13<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg13
96B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
112B		%RDI<def> = COPY %vreg12; GR64:%vreg12
128B		%RSI<def> = COPY %vreg13; GR64:%vreg13
144B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
160B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
192B		STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4) GR32:%vreg1
208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1; mem:ST4[%errcode.addr] GR32:%vreg1
240B		%vreg10<def> = MOV64rm %noreg, 1, %noreg, <ga:@stderr>, %noreg; mem:LD8[@stderr] GR64:%vreg10
256B		%vreg9<def> = MOV32rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD4[%errcode.addr] GR32:%vreg9
272B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
288B		CALL64pcrel32 <ga:@BZ2_bzlibVersion>, <regmask>, %RSP<imp-use>, %RAX<imp-def>
304B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
320B		%vreg8<def> = COPY %RAX<kill>; GR64:%vreg8
336B		%vreg4<def> = MOV64ri <ga:@bzlib__str___bzip2_li>; GR64:%vreg4
352B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
368B		STACKMAP 1, 0, 0, <fi#0>, 0, %vreg9, %vreg10, ...; mem:LD8[FixedStack0](align=4) GR32:%vreg9 GR64:%vreg10
384B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
400B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
480B		%AL<def> = MOV8ri 0
484B		%RDI<def> = COPY %vreg10; GR64:%vreg10
488B		%RSI<def> = COPY %vreg4; GR64:%vreg4
496B		%EDX<def> = COPY %vreg9; GR32:%vreg9
504B		%RCX<def> = COPY %vreg8; GR64:%vreg8
512B		CALL64pcrel32 <ga:@fprintf>, <regmask>, %RSP<imp-use>, %AL<imp-use,kill>, %RDI<imp-use>, %RSI<imp-use>, %EDX<imp-use>, %RCX<imp-use>, %EAX<imp-def>
520B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
528B		%vreg7<def,dead> = COPY %EAX<kill>; GR32:%vreg7
544B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
560B		STACKMAP 2, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
576B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
592B		CMP32mi <fi#0>, 1, %noreg, 0, %noreg, 1007, %EFLAGS<imp-def>; mem:LD4[%errcode.addr]
608B		JNE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

624B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
640B		%vreg15<def> = MOV64ri <ga:@bzlib__str_1______A_spe>; GR64:%vreg15
656B		%vreg17<def> = MOV64rm %noreg, 1, %noreg, <ga:@stderr>, %noreg; mem:LD8[@stderr] GR64:%vreg17
672B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
720B		%AL<def> = MOV8ri 0
724B		%RDI<def> = COPY %vreg17; GR64:%vreg17
728B		%RSI<def> = COPY %vreg15; GR64:%vreg15
736B		CALL64pcrel32 <ga:@fprintf>, <regmask>, %RSP<imp-use>, %AL<imp-use,kill>, %RDI<imp-use>, %RSI<imp-use>, %EAX<imp-def>
752B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
768B		%vreg16<def,dead> = COPY %EAX<kill>; GR32:%vreg16
784B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
800B		STACKMAP 3, 0, ...
816B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#2

832B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#1
864B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
880B		%EDI<def> = MOV32ri 3
896B		CALL64pcrel32 <ga:@exit>, <regmask>, %RSP<imp-use>, %EDI<imp-use>
912B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
928B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
944B		STACKMAP 4, 0, ...
960B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>

# End machine code for function BZ2_bz__AssertH__fail.


selectOrSplit GR32:%vreg1 [16r,224r:0)  0@16r w=4.983553e-03
AllocationOrder(GR32) = [ %EAX %ECX %EDX %ESI %EDI %R8D %R9D %R10D %R11D %EBX %R14D %R15D %R12D %R13D ]
hints: %EDI
missed hint %EDI
assigning %vreg1 to %EBX: BH [16r,224r:0)  0@16r BL [16r,224r:0)  0@16r

selectOrSplit GR64:%vreg12 [48r,112r:0)  0@48r w=2.176724e-03
AllocationOrder(GR64) = [ %RAX %RCX %RDX %RSI %RDI %R8 %R9 %R10 %R11 %RBX %R14 %R15 %R12 %R13 ]
hints: %RDI
assigning %vreg12 to %RDI: DIL [48r,112r:0)  0@48r

selectOrSplit GR64:%vreg13 [80r,128r:0)  0@80r w=4.508928e-03
hints: %RSI
assigning %vreg13 to %RSI: SIL [80r,128r:0)  0@80r

selectOrSplit GR64:%vreg10 [240r,484r:0)  0@240r w=2.352485e-03
hints: %RDI
missed hint %RDI
assigning %vreg10 to %RBX: BH [240r,484r:0)  0@240r BL [240r,484r:0)  0@240r

selectOrSplit GR32:%vreg9 [256r,496r:0)  0@256r w=4.734375e-03
hints: %EDX
missed hint %EDX
%R14D is available at cost 1
Only trying the first 10 regs.
should evict: %vreg10 [240r,484r:0)  0@240r w= 2.352485e-03
hints: %RDI
can reassign: %vreg10 [240r,484r:0)  0@240r from %EBX to %RDI
should evict: %vreg10 [240r,484r:0)  0@240r w= 2.352485e-03
hints: %RDI
can reassign: %vreg10 [240r,484r:0)  0@240r from %EBX to %RDI
evicting %EBX interference: Cascade 1
unassigning %vreg10 from %RBX: BH BL
assigning %vreg9 to %EBX: BH [256r,496r:0)  0@256r BL [256r,496r:0)  0@256r
queuing new interval: %vreg10 [240r,484r:0)  0@240r

selectOrSplit GR64:%vreg10 [240r,484r:0)  0@240r w=2.352485e-03
hints: %RDI
missed hint %RDI
%R14 is available at cost 1
Only trying the first 10 regs.
assigning %vreg10 to %R14: R14B [240r,484r:0)  0@240r

selectOrSplit GR64:%vreg8 [320r,504r:0)  0@320r w=3.458904e-03
hints: %RAX
missed hint %RAX
assigning %vreg8 to %RCX: CH [320r,504r:0)  0@320r CL [320r,504r:0)  0@320r

selectOrSplit GR64:%vreg4 [336r,488r:0)  0@336r w=1.829710e-03
hints: %RSI
assigning %vreg4 to %RSI: SIL [336r,488r:0)  0@336r

selectOrSplit GR32:%vreg7 [528r,528d:0)  0@528r w=inf
hints: %EAX
assigning %vreg7 to %EAX: AH [528r,528d:0)  0@528r AL [528r,528d:0)  0@528r

selectOrSplit GR64:%vreg15 [640r,728r:0)  0@640r w=1.034836e-03
hints: %RSI
assigning %vreg15 to %RSI: SIL [640r,728r:0)  0@640r

selectOrSplit GR64:%vreg17 [656r,724r:0)  0@656r w=1.079060e-03
hints: %RDI
assigning %vreg17 to %RDI: DIL [656r,724r:0)  0@656r

selectOrSplit GR32:%vreg16 [768r,768d:0)  0@768r w=inf
hints: %EAX
assigning %vreg16 to %EAX: AH [768r,768d:0)  0@768r AL [768r,768d:0)  0@768r

********** STACK TRANSFORMATION METADATA **********
********** Function: BZ2_bz__AssertH__fail
********** REGISTER MAP **********
[%vreg1 -> %EBX] GR32
[%vreg4 -> %RSI] GR64
[%vreg7 -> %EAX] GR32
[%vreg8 -> %RCX] GR64
[%vreg9 -> %EBX] GR32
[%vreg10 -> %R14] GR64
[%vreg12 -> %RDI] GR64
[%vreg13 -> %RSI] GR64
[%vreg15 -> %RSI] GR64
[%vreg16 -> %EAX] GR32
[%vreg17 -> %RDI] GR64


Stackmap 0:
  STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4) GR32:%vreg1

i32 %errcode: in register %EBX (vreg 1)
i32* %errcode.addr: in stack slot 0 (size: 4)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, 0, <fi#0>, 0, %vreg9, %vreg10, ...; mem:LD8[FixedStack0](align=4) GR32:%vreg9 GR64:%vreg10

i32* %errcode.addr: in stack slot 0 (size: 4)
i32 %1: in register %EBX (vreg 9)
%struct._IO_FILE* %0: in register %R14 (vreg 10)

Duplicate operand locations:


Stackmap 2:
  STACKMAP 2, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)

i32* %errcode.addr: in stack slot 0 (size: 4)

Duplicate operand locations:


Stackmap 3:
  STACKMAP 3, 0, ...


Duplicate operand locations:


Stackmap 4:
  STACKMAP 4, 0, ...


Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4) GR32:%vreg1
  -> Call instruction SlotIndex 144B, searching vregs 0 -> 19 and stack slots -1 -> 1

  STACKMAP 1, 0, 0, <fi#0>, 0, %vreg9, %vreg10, ...; mem:LD8[FixedStack0](align=4) GR32:%vreg9 GR64:%vreg10
  -> Call instruction SlotIndex 288B, searching vregs 0 -> 19 and stack slots -1 -> 1

  STACKMAP 2, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
  -> Call instruction SlotIndex 512B, searching vregs 0 -> 19 and stack slots -1 -> 1

  STACKMAP 3, 0, ...
  -> Call instruction SlotIndex 736B, searching vregs 0 -> 19 and stack slots -1 -> 1

  STACKMAP 4, 0, ...
  -> Call instruction SlotIndex 896B, searching vregs 0 -> 19 and stack slots -1 -> 1

********** REWRITE VIRTUAL REGISTERS **********
********** Function: BZ2_bz__AssertH__fail
********** REGISTER MAP **********
[%vreg1 -> %EBX] GR32
[%vreg4 -> %RSI] GR64
[%vreg7 -> %EAX] GR32
[%vreg8 -> %RCX] GR64
[%vreg9 -> %EBX] GR32
[%vreg10 -> %R14] GR64
[%vreg12 -> %RDI] GR64
[%vreg13 -> %RSI] GR64
[%vreg15 -> %RSI] GR64
[%vreg16 -> %EAX] GR32
[%vreg17 -> %RDI] GR64

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %EDI
16B		%vreg1<def> = COPY %EDI; GR32:%vreg1
48B		%vreg12<def> = MOV64ri <ga:@BZ2_bz__AssertH__fail>; GR64:%vreg12
80B		%vreg13<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg13
96B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
112B		%RDI<def> = COPY %vreg12<kill>; GR64:%vreg12
128B		%RSI<def> = COPY %vreg13<kill>; GR64:%vreg13
144B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
160B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
192B		STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4) GR32:%vreg1
208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1<kill>; mem:ST4[%errcode.addr] GR32:%vreg1
240B		%vreg10<def> = MOV64rm %noreg, 1, %noreg, <ga:@stderr>, %noreg; mem:LD8[@stderr] GR64:%vreg10
256B		%vreg9<def> = MOV32rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD4[%errcode.addr] GR32:%vreg9
272B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
288B		CALL64pcrel32 <ga:@BZ2_bzlibVersion>, <regmask>, %RSP<imp-use>, %RAX<imp-def>
304B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
320B		%vreg8<def> = COPY %RAX; GR64:%vreg8
336B		%vreg4<def> = MOV64ri <ga:@bzlib__str___bzip2_li>; GR64:%vreg4
352B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
368B		STACKMAP 1, 0, 0, <fi#0>, 0, %vreg9, %vreg10, ...; mem:LD8[FixedStack0](align=4) GR32:%vreg9 GR64:%vreg10
384B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
400B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
480B		%AL<def> = MOV8ri 0
484B		%RDI<def> = COPY %vreg10<kill>; GR64:%vreg10
488B		%RSI<def> = COPY %vreg4<kill>; GR64:%vreg4
496B		%EDX<def> = COPY %vreg9<kill>; GR32:%vreg9
504B		%RCX<def> = COPY %vreg8<kill>; GR64:%vreg8
512B		CALL64pcrel32 <ga:@fprintf>, <regmask>, %RSP<imp-use>, %AL<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %EDX<imp-use>, %RCX<imp-use>, %EAX<imp-def>
520B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
528B		%vreg7<def,dead> = COPY %EAX; GR32:%vreg7
544B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
560B		STACKMAP 2, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
576B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
592B		CMP32mi <fi#0>, 1, %noreg, 0, %noreg, 1007, %EFLAGS<imp-def>; mem:LD4[%errcode.addr]
608B		JNE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1
> %EBX<def> = COPY %EDI
> %RDI<def> = MOV64ri <ga:@BZ2_bz__AssertH__fail>
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 0, 0, %EBX, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %EBX<kill>; mem:ST4[%errcode.addr]
> %R14<def> = MOV64rm %noreg, 1, %noreg, <ga:@stderr>, %noreg; mem:LD8[@stderr]
> %EBX<def> = MOV32rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD4[%errcode.addr]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> CALL64pcrel32 <ga:@BZ2_bzlibVersion>, <regmask>, %RSP<imp-use>, %RAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RCX<def> = COPY %RAX
> %RSI<def> = MOV64ri <ga:@bzlib__str___bzip2_li>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 1, 0, 0, <fi#0>, 0, %EBX, %R14, ...; mem:LD8[FixedStack0](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %AL<def> = MOV8ri 0
> %RDI<def> = COPY %R14<kill>
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> %EDX<def> = COPY %EBX<kill>
> %RCX<def> = COPY %RCX<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@fprintf>, <regmask>, %RSP<imp-use>, %AL<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %EDX<imp-use>, %RCX<imp-use>, %EAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def,dead> = COPY %EAX
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 2, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> CMP32mi <fi#0>, 1, %noreg, 0, %noreg, 1007, %EFLAGS<imp-def>; mem:LD4[%errcode.addr]
> JNE_1 <BB#2>, %EFLAGS<imp-use,kill>
624B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
640B		%vreg15<def> = MOV64ri <ga:@bzlib__str_1______A_spe>; GR64:%vreg15
656B		%vreg17<def> = MOV64rm %noreg, 1, %noreg, <ga:@stderr>, %noreg; mem:LD8[@stderr] GR64:%vreg17
672B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
720B		%AL<def> = MOV8ri 0
724B		%RDI<def> = COPY %vreg17<kill>; GR64:%vreg17
728B		%RSI<def> = COPY %vreg15<kill>; GR64:%vreg15
736B		CALL64pcrel32 <ga:@fprintf>, <regmask>, %RSP<imp-use>, %AL<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %EAX<imp-def>
752B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
768B		%vreg16<def,dead> = COPY %EAX; GR32:%vreg16
784B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
800B		STACKMAP 3, 0, ...
816B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#2
> %RSI<def> = MOV64ri <ga:@bzlib__str_1______A_spe>
> %RDI<def> = MOV64rm %noreg, 1, %noreg, <ga:@stderr>, %noreg; mem:LD8[@stderr]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %AL<def> = MOV8ri 0
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@fprintf>, <regmask>, %RSP<imp-use>, %AL<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %EAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def,dead> = COPY %EAX
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 3, 0, ...
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
832B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#1
864B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
880B		%EDI<def> = MOV32ri 3
896B		CALL64pcrel32 <ga:@exit>, <regmask>, %RSP<imp-use>, %EDI<imp-use>
912B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
928B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
944B		STACKMAP 4, 0, ...
960B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EDI<def> = MOV32ri 3
> CALL64pcrel32 <ga:@exit>, <regmask>, %RSP<imp-use>, %EDI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 4, 0, ...
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
Computing live-in reg-units in ABI blocks.
Created 0 new intervals.
********** INTERVALS **********
%vreg0 [320r,384r:0)  0@320r
%vreg1 [144r,160r:0)  0@144r
%vreg2 [160r,256r:0)  0@160r
%vreg3 [224r,272r:0)  0@224r
%vreg4 [16r,32r:0)  0@16r
%vreg5 [32r,80r:0)  0@32r
%vreg6 [48r,96r:0)  0@48r
RegMasks: 112r 288r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzlibVersion: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]

0B	BB#0: derived from LLVM BB %entry
16B		%vreg4<def> = MOV64ri <ga:@BZ2_bzlibVersion>; GR64:%vreg4
32B		%vreg5<def> = COPY %vreg4; GR64:%vreg5,%vreg4
48B		%vreg6<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg6
64B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
80B		%RDI<def> = COPY %vreg5; GR64:%vreg5
96B		%RSI<def> = COPY %vreg6; GR64:%vreg6
112B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use,kill>, %RSI<imp-use,kill>
128B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
144B		%vreg1<def> = MOV64ri <ga:@BZ2_bzlibVersion>; GR64:%vreg1
160B		%vreg2<def> = COPY %vreg1; GR64:%vreg2,%vreg1
176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
192B		STACKMAP 0, 0, ...
208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		%vreg3<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg3
240B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
256B		%RDI<def> = COPY %vreg2; GR64:%vreg2
272B		%RSI<def> = COPY %vreg3; GR64:%vreg3
288B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use,kill>, %RSI<imp-use,kill>
304B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
320B		%vreg0<def> = MOV64ri <ga:@bzlib__str_5_1_0_3__15_>; GR64:%vreg0
336B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
352B		STACKMAP 1, 0, ...
368B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
384B		%RAX<def> = COPY %vreg0; GR64:%vreg0
400B		RETQ %RAX<imp-use,kill>

# End machine code for function BZ2_bzlibVersion.

********** SIMPLE REGISTER COALESCING **********
********** Function: BZ2_bzlibVersion
********** JOINING INTERVALS ***********
entry:
80B	%RDI<def> = COPY %vreg5; GR64:%vreg5
	Considering merging %vreg5 with %RDI
	Can only merge into reserved registers.
96B	%RSI<def> = COPY %vreg6; GR64:%vreg6
	Considering merging %vreg6 with %RSI
	Can only merge into reserved registers.
256B	%RDI<def> = COPY %vreg2; GR64:%vreg2
	Considering merging %vreg2 with %RDI
	Can only merge into reserved registers.
272B	%RSI<def> = COPY %vreg3; GR64:%vreg3
	Considering merging %vreg3 with %RSI
	Can only merge into reserved registers.
384B	%RAX<def> = COPY %vreg0; GR64:%vreg0
	Considering merging %vreg0 with %RAX
	Can only merge into reserved registers.
32B	%vreg5<def> = COPY %vreg4; GR64:%vreg5,%vreg4
	Considering merging to GR64 with %vreg4 in %vreg5
		RHS = %vreg4 [16r,32r:0)  0@16r
		LHS = %vreg5 [32r,80r:0)  0@32r
		merge %vreg5:0@32r into %vreg4:0@16r --> @16r
		erased:	32r	%vreg5<def> = COPY %vreg4; GR64:%vreg5,%vreg4
		updated: 16B	%vreg5<def> = MOV64ri <ga:@BZ2_bzlibVersion>; GR64:%vreg5
	Success: %vreg4 -> %vreg5
	Result = %vreg5 [16r,80r:0)  0@16r
160B	%vreg2<def> = COPY %vreg1; GR64:%vreg2,%vreg1
	Considering merging to GR64 with %vreg1 in %vreg2
		RHS = %vreg1 [144r,160r:0)  0@144r
		LHS = %vreg2 [160r,256r:0)  0@160r
		merge %vreg2:0@160r into %vreg1:0@144r --> @144r
		erased:	160r	%vreg2<def> = COPY %vreg1; GR64:%vreg2,%vreg1
		updated: 144B	%vreg2<def> = MOV64ri <ga:@BZ2_bzlibVersion>; GR64:%vreg2
	Success: %vreg1 -> %vreg2
	Result = %vreg2 [144r,256r:0)  0@144r
80B	%RDI<def> = COPY %vreg5; GR64:%vreg5
	Considering merging %vreg5 with %RDI
	Can only merge into reserved registers.
256B	%RDI<def> = COPY %vreg2; GR64:%vreg2
	Considering merging %vreg2 with %RDI
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
%vreg0 [320r,384r:0)  0@320r
%vreg2 [144r,256r:0)  0@144r
%vreg3 [224r,272r:0)  0@224r
%vreg5 [16r,80r:0)  0@16r
%vreg6 [48r,96r:0)  0@48r
RegMasks: 112r 288r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzlibVersion: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]

0B	BB#0: derived from LLVM BB %entry
16B		%vreg5<def> = MOV64ri <ga:@BZ2_bzlibVersion>; GR64:%vreg5
48B		%vreg6<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg6
64B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
80B		%RDI<def> = COPY %vreg5; GR64:%vreg5
96B		%RSI<def> = COPY %vreg6; GR64:%vreg6
112B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use,kill>, %RSI<imp-use,kill>
128B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
144B		%vreg2<def> = MOV64ri <ga:@BZ2_bzlibVersion>; GR64:%vreg2
176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
192B		STACKMAP 0, 0, ...
208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		%vreg3<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg3
240B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
256B		%RDI<def> = COPY %vreg2; GR64:%vreg2
272B		%RSI<def> = COPY %vreg3; GR64:%vreg3
288B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use,kill>, %RSI<imp-use,kill>
304B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
320B		%vreg0<def> = MOV64ri <ga:@bzlib__str_5_1_0_3__15_>; GR64:%vreg0
336B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
352B		STACKMAP 1, 0, ...
368B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
384B		%RAX<def> = COPY %vreg0; GR64:%vreg0
400B		RETQ %RAX<imp-use,kill>

# End machine code for function BZ2_bzlibVersion.

********** GREEDY REGISTER ALLOCATION **********
********** Function: BZ2_bzlibVersion
********** INTERVALS **********
%vreg0 [320r,384r:0)  0@320r
%vreg2 [144r,256r:0)  0@144r
%vreg3 [224r,272r:0)  0@224r
%vreg5 [16r,80r:0)  0@16r
%vreg6 [48r,96r:0)  0@48r
RegMasks: 112r 288r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzlibVersion: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]

0B	BB#0: derived from LLVM BB %entry
16B		%vreg5<def> = MOV64ri <ga:@BZ2_bzlibVersion>; GR64:%vreg5
48B		%vreg6<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg6
64B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
80B		%RDI<def> = COPY %vreg5; GR64:%vreg5
96B		%RSI<def> = COPY %vreg6; GR64:%vreg6
112B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use,kill>, %RSI<imp-use,kill>
128B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
144B		%vreg2<def> = MOV64ri <ga:@BZ2_bzlibVersion>; GR64:%vreg2
176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
192B		STACKMAP 0, 0, ...
208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		%vreg3<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg3
240B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
256B		%RDI<def> = COPY %vreg2; GR64:%vreg2
272B		%RSI<def> = COPY %vreg3; GR64:%vreg3
288B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use,kill>, %RSI<imp-use,kill>
304B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
320B		%vreg0<def> = MOV64ri <ga:@bzlib__str_5_1_0_3__15_>; GR64:%vreg0
336B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
352B		STACKMAP 1, 0, ...
368B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
384B		%RAX<def> = COPY %vreg0; GR64:%vreg0
400B		RETQ %RAX<imp-use,kill>

# End machine code for function BZ2_bzlibVersion.


selectOrSplit GR64:%vreg5 [16r,80r:0)  0@16r w=2.176724e-03
hints: %RDI
assigning %vreg5 to %RDI: DIL [16r,80r:0)  0@16r

selectOrSplit GR64:%vreg6 [48r,96r:0)  0@48r w=4.508928e-03
hints: %RSI
assigning %vreg6 to %RSI: SIL [48r,96r:0)  0@48r

selectOrSplit GR64:%vreg2 [144r,256r:0)  0@144r w=1.972656e-03
hints: %RDI
assigning %vreg2 to %RDI: DIL [144r,256r:0)  0@144r

selectOrSplit GR64:%vreg3 [224r,272r:0)  0@224r w=4.508928e-03
hints: %RSI
assigning %vreg3 to %RSI: SIL [224r,272r:0)  0@224r

selectOrSplit GR64:%vreg0 [320r,384r:0)  0@320r w=2.176724e-03
hints: %RAX
assigning %vreg0 to %RAX: AH [320r,384r:0)  0@320r AL [320r,384r:0)  0@320r

********** STACK TRANSFORMATION METADATA **********
********** Function: BZ2_bzlibVersion
********** REGISTER MAP **********
[%vreg0 -> %RAX] GR64
[%vreg2 -> %RDI] GR64
[%vreg3 -> %RSI] GR64
[%vreg5 -> %RDI] GR64
[%vreg6 -> %RSI] GR64


Stackmap 0:
  STACKMAP 0, 0, ...


Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, ...


Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, ...
  -> Call instruction SlotIndex 112B, searching vregs 0 -> 7 and stack slots -1 -> 0

  STACKMAP 1, 0, ...
  -> Call instruction SlotIndex 288B, searching vregs 0 -> 7 and stack slots -1 -> 0

********** REWRITE VIRTUAL REGISTERS **********
********** Function: BZ2_bzlibVersion
********** REGISTER MAP **********
[%vreg0 -> %RAX] GR64
[%vreg2 -> %RDI] GR64
[%vreg3 -> %RSI] GR64
[%vreg5 -> %RDI] GR64
[%vreg6 -> %RSI] GR64

0B	BB#0: derived from LLVM BB %entry
16B		%vreg5<def> = MOV64ri <ga:@BZ2_bzlibVersion>; GR64:%vreg5
48B		%vreg6<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg6
64B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
80B		%RDI<def> = COPY %vreg5<kill>; GR64:%vreg5
96B		%RSI<def> = COPY %vreg6<kill>; GR64:%vreg6
112B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
128B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
144B		%vreg2<def> = MOV64ri <ga:@BZ2_bzlibVersion>; GR64:%vreg2
176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
192B		STACKMAP 0, 0, ...
208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		%vreg3<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg3
240B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
256B		%RDI<def> = COPY %vreg2<kill>; GR64:%vreg2
272B		%RSI<def> = COPY %vreg3<kill>; GR64:%vreg3
288B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
304B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
320B		%vreg0<def> = MOV64ri <ga:@bzlib__str_5_1_0_3__15_>; GR64:%vreg0
336B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
352B		STACKMAP 1, 0, ...
368B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
384B		%RAX<def> = COPY %vreg0<kill>; GR64:%vreg0
400B		RETQ %RAX<imp-use>
> %RDI<def> = MOV64ri <ga:@BZ2_bzlibVersion>
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = MOV64ri <ga:@BZ2_bzlibVersion>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 0, 0, ...
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RAX<def> = MOV64ri <ga:@bzlib__str_5_1_0_3__15_>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 1, 0, ...
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RAX<def> = COPY %RAX<kill>
Deleting identity copy.
> RETQ %RAX<imp-use>
Computing live-in reg-units in ABI blocks.
0B	BB#0 DIL#0 SIL#0 DH#0 DL#0 CH#0 CL#0
Created 6 new intervals.
********** INTERVALS **********
CH [0B,16r:0)  0@0B-phi
CL [0B,16r:0)  0@0B-phi
DH [0B,32r:0)[1360r,1376r:4)[1968r,1984r:1)[2368r,2384r:2)[2672r,2688r:3)  0@0B-phi 1@1968r 2@2368r 3@2672r 4@1360r
DIL [0B,64r:0)[208r,240r:12)[1328r,1376r:11)[1936r,1984r:8)[2336r,2384r:9)[2640r,2688r:10)[3216r,3248r:5)[3536r,3568r:4)[3856r,3888r:3)[4144r,4176r:2)[5152r,5168r:6)[5280r,5296r:7)[5472r,5504r:1)  0@0B-phi 1@5472r 2@4144r 3@3856r 4@3536r 5@3216r 6@5152r 7@5280r 8@1936r 9@2336r 10@2640r 11@1328r 12@208r
DL [0B,32r:0)[1360r,1376r:4)[1968r,1984r:1)[2368r,2384r:2)[2672r,2688r:3)  0@0B-phi 1@1968r 2@2368r 3@2672r 4@1360r
SIL [0B,48r:0)[224r,240r:10)[1344r,1376r:4)[1952r,1984r:1)[2352r,2384r:2)[2656r,2688r:3)[3232r,3248r:9)[3552r,3568r:8)[3872r,3888r:7)[4160r,4176r:6)[5488r,5504r:5)  0@0B-phi 1@1952r 2@2352r 3@2656r 4@1344r 5@5488r 6@4160r 7@3872r 8@3552r 9@3232r 10@224r
%vreg0 [64r,80r:0)  0@64r
%vreg1 [80r,320r:0)  0@80r
%vreg2 [48r,96r:0)  0@48r
%vreg3 [96r,336r:0)  0@96r
%vreg4 [32r,112r:0)  0@32r
%vreg5 [112r,352r:0)  0@112r
%vreg6 [16r,128r:0)  0@16r
%vreg7 [128r,368r:0)  0@128r
%vreg9 [432r,496r:0)  0@432r
%vreg10 [144r,160r:0)  0@144r
%vreg11 [160r,208r:0)  0@160r
%vreg12 [176r,224r:0)  0@176r
%vreg21 [960r,976r:0)  0@960r
%vreg23 [1024r,1056r:0)  0@1024r
%vreg24 [1040r,1056r:0)  0@1040r
%vreg27 [1088r,1104r:0)  0@1088r
%vreg29 [1152r,1184r:0)  0@1152r
%vreg30 [1168r,1184r:0)  0@1168r
%vreg34 [1472r,1488r:0)  0@1472r
%vreg36 [1216r,1344r:0)  0@1216r
%vreg37 [1232r,1360r:0)  0@1232r
%vreg39 [1408r,1472r:0)  0@1408r
%vreg41 [1296r,1328r:0)  0@1296r
%vreg42 [1280r,1296r:0)  0@1280r
%vreg44 [1264r,1376r:0)  0@1264r
%vreg45 [1248r,1264r:0)  0@1248r
%vreg48 [2832r,2848r:0)  0@2832r
%vreg51 [2800r,2816r:0)  0@2800r
%vreg53 [2784r,2816r:0)  0@2784r
%vreg55 [2432r,2656r:0)  0@2432r
%vreg56 [2448r,2672r:0)  0@2448r
%vreg58 [2720r,2784r:0)  0@2720r
%vreg60 [2608r,2640r:0)  0@2608r
%vreg61 [2592r,2608r:0)  0@2592r
%vreg63 [2576r,2688r:0)  0@2576r
%vreg64 [2560r,2576r:0)  0@2560r
%vreg67 [2528r,2544r:0)  0@2528r
%vreg69 [2512r,2544r:0)  0@2512r
%vreg72 [2032r,2368r:0)  0@2032r
%vreg74 [2416r,2512r:0)  0@2416r
%vreg76 [2304r,2352r:0)  0@2304r
%vreg78 [2272r,2288r:0)[2288r,2304r:1)  0@2272r 1@2288r
%vreg80 [2256r,2272r:0)  0@2256r
%vreg82 [2224r,2240r:0)[2240r,2256r:1)  0@2224r 1@2240r
%vreg83 [2208r,2224r:0)  0@2208r
%vreg85 [2192r,2336r:0)  0@2192r
%vreg86 [2176r,2192r:0)  0@2176r
%vreg88 [2160r,2384r:0)  0@2160r
%vreg89 [2144r,2160r:0)  0@2144r
%vreg92 [2112r,2128r:0)  0@2112r
%vreg94 [2096r,2128r:0)  0@2096r
%vreg97 [1600r,1968r:0)  0@1600r
%vreg99 [2016r,2096r:0)  0@2016r
%vreg101 [1904r,1952r:0)  0@1904r
%vreg103 [1872r,1888r:0)[1888r,1904r:1)  0@1872r 1@1888r
%vreg105 [1856r,1872r:0)  0@1856r
%vreg107 [1840r,1936r:0)  0@1840r
%vreg108 [1824r,1840r:0)  0@1824r
%vreg110 [1808r,1984r:0)  0@1808r
%vreg111 [1792r,1808r:0)  0@1792r
%vreg114 [1760r,1776r:0)  0@1760r
%vreg116 [1728r,1744r:0)  0@1728r
%vreg118 [1696r,1712r:0)  0@1696r
%vreg120 [1664r,1680r:0)  0@1664r
%vreg123 [1632r,1648r:0)  0@1632r
%vreg124 [1616r,1648r:0)  0@1616r
%vreg127 [2896r,2912r:0)  0@2896r
%vreg130 [2960r,2976r:0)  0@2960r
%vreg132 [5248r,5280r:0)  0@5248r
%vreg134 [5120r,5152r:0)  0@5120r
%vreg136 [5088r,5104r:0)  0@5088r
%vreg138 [5056r,5072r:0)  0@5056r
%vreg140 [5024r,5040r:0)  0@5024r
%vreg142 [4992r,5008r:0)  0@4992r
%vreg145 [4960r,4976r:0)  0@4960r
%vreg147 [4944r,4976r:0)  0@4944r
%vreg148 [4928r,4944r:0)  0@4928r
%vreg151 [4896r,4912r:0)  0@4896r
%vreg153 [4880r,4912r:0)  0@4880r
%vreg154 [4864r,4880r:0)  0@4864r
%vreg156 [4832r,4848r:0)  0@4832r
%vreg159 [4800r,4816r:0)  0@4800r
%vreg161 [4784r,4816r:0)  0@4784r
%vreg163 [4768r,4784r:0)  0@4768r
%vreg164 [4752r,4768r:0)  0@4752r
%vreg167 [4720r,4736r:0)  0@4720r
%vreg169 [4704r,4736r:0)  0@4704r
%vreg171 [4688r,4704r:0)  0@4688r
%vreg172 [4672r,4688r:0)  0@4672r
%vreg175 [4640r,4656r:0)  0@4640r
%vreg176 [4624r,4656r:0)  0@4624r
%vreg179 [4592r,4608r:0)  0@4592r
%vreg180 [4576r,4608r:0)  0@4576r
%vreg183 [4544r,4560r:0)  0@4544r
%vreg185 [4512r,4528r:0)[4528r,4560r:1)  0@4512r 1@4528r
%vreg187 [4496r,4512r:0)  0@4496r
%vreg190 [4464r,4480r:0)  0@4464r
%vreg191 [4448r,4480r:0)  0@4448r
%vreg193 [4416r,4432r:0)  0@4416r
%vreg195 [4384r,4400r:0)  0@4384r
%vreg197 [4352r,4368r:0)  0@4352r
%vreg199 [4320r,4336r:0)  0@4320r
%vreg202 [3024r,3040r:0)  0@3024r
%vreg207 [3184r,3232r:0)  0@3184r
%vreg209 [3168r,3184r:0)  0@3168r
%vreg210 [3152r,3168r:0)  0@3152r
%vreg212 [3136r,3216r:0)  0@3136r
%vreg213 [3120r,3136r:0)  0@3120r
%vreg215 [3104r,3248r:0)  0@3104r
%vreg216 [3088r,3104r:0)  0@3088r
%vreg219 [3344r,3360r:0)  0@3344r
%vreg224 [3504r,3552r:0)  0@3504r
%vreg226 [3488r,3504r:0)  0@3488r
%vreg227 [3472r,3488r:0)  0@3472r
%vreg229 [3456r,3536r:0)  0@3456r
%vreg230 [3440r,3456r:0)  0@3440r
%vreg232 [3424r,3568r:0)  0@3424r
%vreg233 [3408r,3424r:0)  0@3408r
%vreg236 [3664r,3680r:0)  0@3664r
%vreg241 [3824r,3872r:0)  0@3824r
%vreg243 [3808r,3824r:0)  0@3808r
%vreg244 [3792r,3808r:0)  0@3792r
%vreg246 [3776r,3856r:0)  0@3776r
%vreg247 [3760r,3776r:0)  0@3760r
%vreg249 [3744r,3888r:0)  0@3744r
%vreg250 [3728r,3744r:0)  0@3728r
%vreg256 [4112r,4160r:0)  0@4112r
%vreg257 [4096r,4112r:0)  0@4096r
%vreg259 [4080r,4144r:0)  0@4080r
%vreg260 [4064r,4080r:0)  0@4064r
%vreg262 [4048r,4176r:0)  0@4048r
%vreg263 [4032r,4048r:0)  0@4032r
%vreg265 [5584r,5600r:0)  0@5584r
%vreg266 [5408r,5424r:0)  0@5408r
%vreg267 [5424r,5472r:0)  0@5424r
%vreg268 [5440r,5488r:0)  0@5440r
RegMasks: 240r 400r 1376r 1984r 2384r 2688r 3248r 3568r 3888r 4176r 5168r 5296r 5504r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzCompressInit: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=4, align=4, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=4, align=4, at location [SP+8]
  fi#3: size=4, align=4, at location [SP+8]
  fi#4: size=4, align=4, at location [SP+8]
  fi#5: size=4, align=4, at location [SP+8]
  fi#6: size=8, align=8, at location [SP+8]
Function Live Ins: %RDI in %vreg0, %ESI in %vreg2, %EDX in %vreg4, %ECX in %vreg6

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI %ESI %EDX %ECX
16B		%vreg6<def> = COPY %ECX; GR32:%vreg6
32B		%vreg4<def> = COPY %EDX; GR32:%vreg4
48B		%vreg2<def> = COPY %ESI; GR32:%vreg2
64B		%vreg0<def> = COPY %RDI; GR64:%vreg0
80B		%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
96B		%vreg3<def> = COPY %vreg2; GR32:%vreg3,%vreg2
112B		%vreg5<def> = COPY %vreg4; GR32:%vreg5,%vreg4
128B		%vreg7<def> = COPY %vreg6; GR32:%vreg7,%vreg6
144B		%vreg10<def> = MOV64ri <ga:@BZ2_bzCompressInit>; GR64:%vreg10
160B		%vreg11<def> = COPY %vreg10; GR64:%vreg11,%vreg10
176B		%vreg12<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg12
192B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
208B		%RDI<def> = COPY %vreg11; GR64:%vreg11
224B		%RSI<def> = COPY %vreg12; GR64:%vreg12
240B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
256B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
272B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
288B		STACKMAP 0, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, %vreg1, 0, <fi#1>, 0, %vreg5, 0, <fi#3>, 0, %vreg7, 0, <fi#4>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4) GR32:%vreg3,%vreg5,%vreg7 GR64:%vreg1
304B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
320B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%strm.addr] GR64:%vreg1
336B		MOV32mr <fi#2>, 1, %noreg, 0, %noreg, %vreg3; mem:ST4[%blockSize100k.addr] GR32:%vreg3
352B		MOV32mr <fi#3>, 1, %noreg, 0, %noreg, %vreg5; mem:ST4[%verbosity.addr] GR32:%vreg5
368B		MOV32mr <fi#4>, 1, %noreg, 0, %noreg, %vreg7; mem:ST4[%workFactor.addr] GR32:%vreg7
384B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
400B		CALL64pcrel32 <ga:@bz_config_ok>, <regmask>, %RSP<imp-use>, %EAX<imp-def>
416B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
432B		%vreg9<def> = COPY %EAX<kill>; GR32:%vreg9
448B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
464B		STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)
480B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
496B		CMP32ri8 %vreg9, 0, %EFLAGS<imp-def>; GR32:%vreg9
512B		JNE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

528B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
544B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -9; mem:ST4[%retval]
560B		JMP_1 <BB#29>
	    Successors according to CFG: BB#29

576B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0
592B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%strm.addr]
608B		JE_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#3

624B	BB#3: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#2
640B		CMP32mi8 <fi#2>, 1, %noreg, 0, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%blockSize100k.addr]
656B		JL_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#4

672B	BB#4: derived from LLVM BB %lor.lhs.false.2
	    Predecessors according to CFG: BB#3
688B		CMP32mi8 <fi#2>, 1, %noreg, 0, %noreg, 9, %EFLAGS<imp-def>; mem:LD4[%blockSize100k.addr]
704B		JG_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#5

720B	BB#5: derived from LLVM BB %lor.lhs.false.4
	    Predecessors according to CFG: BB#4
736B		CMP32mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%workFactor.addr]
752B		JL_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#6

768B	BB#6: derived from LLVM BB %lor.lhs.false.6
	    Predecessors according to CFG: BB#5
784B		CMP32mi <fi#4>, 1, %noreg, 0, %noreg, 250, %EFLAGS<imp-def>; mem:LD4[%workFactor.addr]
800B		JLE_1 <BB#8>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#8 BB#7

816B	BB#7: derived from LLVM BB %if.then.8
	    Predecessors according to CFG: BB#2 BB#3 BB#4 BB#5 BB#6
832B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
848B		JMP_1 <BB#29>
	    Successors according to CFG: BB#29

864B	BB#8: derived from LLVM BB %if.end.9
	    Predecessors according to CFG: BB#6
880B		CMP32mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%workFactor.addr]
896B		JNE_1 <BB#10>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#10 BB#9

912B	BB#9: derived from LLVM BB %if.then.11
	    Predecessors according to CFG: BB#8
928B		MOV32mi <fi#4>, 1, %noreg, 0, %noreg, 30; mem:ST4[%workFactor.addr]
	    Successors according to CFG: BB#10

944B	BB#10: derived from LLVM BB %if.end.12
	    Predecessors according to CFG: BB#8 BB#9
960B		%vreg21<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg21
976B		CMP64mi8 %vreg21, 1, %noreg, 56, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzalloc] GR64:%vreg21
992B		JNE_1 <BB#12>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#12 BB#11

1008B	BB#11: derived from LLVM BB %if.then.14
	    Predecessors according to CFG: BB#10
1024B		%vreg23<def> = MOV64ri <ga:@default_bzalloc>; GR64:%vreg23
1040B		%vreg24<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg24
1056B		MOV64mr %vreg24, 1, %noreg, 56, %noreg, %vreg23; mem:ST8[%bzalloc15] GR64:%vreg24,%vreg23
	    Successors according to CFG: BB#12

1072B	BB#12: derived from LLVM BB %if.end.16
	    Predecessors according to CFG: BB#10 BB#11
1088B		%vreg27<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg27
1104B		CMP64mi8 %vreg27, 1, %noreg, 64, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzfree] GR64:%vreg27
1120B		JNE_1 <BB#14>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#14 BB#13

1136B	BB#13: derived from LLVM BB %if.then.18
	    Predecessors according to CFG: BB#12
1152B		%vreg29<def> = MOV64ri <ga:@default_bzfree>; GR64:%vreg29
1168B		%vreg30<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg30
1184B		MOV64mr %vreg30, 1, %noreg, 64, %noreg, %vreg29; mem:ST8[%bzfree19] GR64:%vreg30,%vreg29
	    Successors according to CFG: BB#14

1200B	BB#14: derived from LLVM BB %if.end.20
	    Predecessors according to CFG: BB#12 BB#13
1216B		%vreg36<def> = MOV32ri 55768; GR32:%vreg36
1232B		%vreg37<def> = MOV32ri 1; GR32:%vreg37
1248B		%vreg45<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg45
1264B		%vreg44<def> = MOV64rm %vreg45, 1, %noreg, 56, %noreg; mem:LD8[%bzalloc21] GR64:%vreg44,%vreg45
1280B		%vreg42<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg42
1296B		%vreg41<def> = MOV64rm %vreg42, 1, %noreg, 72, %noreg; mem:LD8[%opaque] GR64:%vreg41,%vreg42
1312B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1328B		%RDI<def> = COPY %vreg41; GR64:%vreg41
1344B		%ESI<def> = COPY %vreg36; GR32:%vreg36
1360B		%EDX<def> = COPY %vreg37; GR32:%vreg37
1376B		CALL64r %vreg44, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %EDX<imp-use>, %RAX<imp-def>; GR64:%vreg44
1392B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1408B		%vreg39<def> = COPY %RAX<kill>; GR64:%vreg39
1424B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1440B		STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)
1456B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1472B		%vreg34<def> = COPY %vreg39; GR64:%vreg34,%vreg39
1488B		MOV64mr <fi#6>, 1, %noreg, 0, %noreg, %vreg34; mem:ST8[%s] GR64:%vreg34
1504B		CMP64mi8 <fi#6>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%s]
1520B		JNE_1 <BB#16>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#16 BB#15

1536B	BB#15: derived from LLVM BB %if.then.24
	    Predecessors according to CFG: BB#14
1552B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -3; mem:ST4[%retval]
1568B		JMP_1 <BB#29>
	    Successors according to CFG: BB#29

1584B	BB#16: derived from LLVM BB %if.end.25
	    Predecessors according to CFG: BB#14
1600B		%vreg97<def> = MOV32ri 1; GR32:%vreg97
1616B		%vreg124<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg124
1632B		%vreg123<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg123
1648B		MOV64mr %vreg123, 1, %noreg, 0, %noreg, %vreg124; mem:ST8[%strm26] GR64:%vreg123,%vreg124
1664B		%vreg120<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg120
1680B		MOV64mi32 %vreg120, 1, %noreg, 24, %noreg, 0; mem:ST8[%arr1] GR64:%vreg120
1696B		%vreg118<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg118
1712B		MOV64mi32 %vreg118, 1, %noreg, 32, %noreg, 0; mem:ST8[%arr2] GR64:%vreg118
1728B		%vreg116<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg116
1744B		MOV64mi32 %vreg116, 1, %noreg, 40, %noreg, 0; mem:ST8[%ftab] GR64:%vreg116
1760B		%vreg114<def> = IMUL32rmi <fi#2>, 1, %noreg, 0, %noreg, 100000, %EFLAGS<imp-def,dead>; mem:LD4[%blockSize100k.addr] GR32:%vreg114
1776B		MOV32mr <fi#5>, 1, %noreg, 0, %noreg, %vreg114; mem:ST4[%n] GR32:%vreg114
1792B		%vreg111<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg111
1808B		%vreg110<def> = MOV64rm %vreg111, 1, %noreg, 56, %noreg; mem:LD8[%bzalloc27] GR64:%vreg110,%vreg111
1824B		%vreg108<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg108
1840B		%vreg107<def> = MOV64rm %vreg108, 1, %noreg, 72, %noreg; mem:LD8[%opaque28] GR64:%vreg107,%vreg108
1856B		%vreg105<def> = MOVSX64rm32 <fi#5>, 1, %noreg, 0, %noreg; mem:LD4[%n] GR64:%vreg105
1872B		%vreg103<def> = COPY %vreg105; GR64:%vreg103,%vreg105
1888B		%vreg103<def,tied1> = SHL64ri %vreg103<tied0>, 2, %EFLAGS<imp-def,dead>; GR64:%vreg103
1904B		%vreg101<def> = COPY %vreg103:sub_32bit; GR32:%vreg101 GR64:%vreg103
1920B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1936B		%RDI<def> = COPY %vreg107; GR64:%vreg107
1952B		%ESI<def> = COPY %vreg101; GR32:%vreg101
1968B		%EDX<def> = COPY %vreg97; GR32:%vreg97
1984B		CALL64r %vreg110, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %EDX<imp-use>, %RAX<imp-def>; GR64:%vreg110
2000B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2016B		%vreg99<def> = COPY %RAX<kill>; GR64:%vreg99
2032B		%vreg72<def> = MOV32ri 1; GR32:%vreg72
2048B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2064B		STACKMAP 3, 0, 0, <fi#2>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)
2080B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2096B		%vreg94<def> = COPY %vreg99; GR64:%vreg94,%vreg99
2112B		%vreg92<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg92
2128B		MOV64mr %vreg92, 1, %noreg, 24, %noreg, %vreg94; mem:ST8[%arr132] GR64:%vreg92,%vreg94
2144B		%vreg89<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg89
2160B		%vreg88<def> = MOV64rm %vreg89, 1, %noreg, 56, %noreg; mem:LD8[%bzalloc33] GR64:%vreg88,%vreg89
2176B		%vreg86<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg86
2192B		%vreg85<def> = MOV64rm %vreg86, 1, %noreg, 72, %noreg; mem:LD8[%opaque34] GR64:%vreg85,%vreg86
2208B		%vreg83<def> = MOV32rm <fi#5>, 1, %noreg, 0, %noreg; mem:LD4[%n] GR32:%vreg83
2224B		%vreg82<def> = COPY %vreg83; GR32:%vreg82,%vreg83
2240B		%vreg82<def,tied1> = ADD32ri8 %vreg82<tied0>, 34, %EFLAGS<imp-def,dead>; GR32:%vreg82
2256B		%vreg80<def> = MOVSX64rr32 %vreg82; GR64:%vreg80 GR32:%vreg82
2272B		%vreg78<def> = COPY %vreg80; GR64:%vreg78,%vreg80
2288B		%vreg78<def,tied1> = SHL64ri %vreg78<tied0>, 2, %EFLAGS<imp-def,dead>; GR64:%vreg78
2304B		%vreg76<def> = COPY %vreg78:sub_32bit; GR32:%vreg76 GR64:%vreg78
2320B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2336B		%RDI<def> = COPY %vreg85; GR64:%vreg85
2352B		%ESI<def> = COPY %vreg76; GR32:%vreg76
2368B		%EDX<def> = COPY %vreg72; GR32:%vreg72
2384B		CALL64r %vreg88, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %EDX<imp-use>, %RAX<imp-def>; GR64:%vreg88
2400B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2416B		%vreg74<def> = COPY %RAX<kill>; GR64:%vreg74
2432B		%vreg55<def> = MOV32ri 262148; GR32:%vreg55
2448B		%vreg56<def> = MOV32ri 1; GR32:%vreg56
2464B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2480B		STACKMAP 4, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)
2496B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2512B		%vreg69<def> = COPY %vreg74; GR64:%vreg69,%vreg74
2528B		%vreg67<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg67
2544B		MOV64mr %vreg67, 1, %noreg, 32, %noreg, %vreg69; mem:ST8[%arr239] GR64:%vreg67,%vreg69
2560B		%vreg64<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg64
2576B		%vreg63<def> = MOV64rm %vreg64, 1, %noreg, 56, %noreg; mem:LD8[%bzalloc40] GR64:%vreg63,%vreg64
2592B		%vreg61<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg61
2608B		%vreg60<def> = MOV64rm %vreg61, 1, %noreg, 72, %noreg; mem:LD8[%opaque41] GR64:%vreg60,%vreg61
2624B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2640B		%RDI<def> = COPY %vreg60; GR64:%vreg60
2656B		%ESI<def> = COPY %vreg55; GR32:%vreg55
2672B		%EDX<def> = COPY %vreg56; GR32:%vreg56
2688B		CALL64r %vreg63, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %EDX<imp-use>, %RAX<imp-def>; GR64:%vreg63
2704B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2720B		%vreg58<def> = COPY %RAX<kill>; GR64:%vreg58
2736B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2752B		STACKMAP 5, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)
2768B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2784B		%vreg53<def> = COPY %vreg58; GR64:%vreg53,%vreg58
2800B		%vreg51<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg51
2816B		MOV64mr %vreg51, 1, %noreg, 40, %noreg, %vreg53; mem:ST8[%ftab43] GR64:%vreg51,%vreg53
2832B		%vreg48<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg48
2848B		CMP64mi8 %vreg48, 1, %noreg, 24, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%arr144] GR64:%vreg48
2864B		JE_1 <BB#19>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#19 BB#17

2880B	BB#17: derived from LLVM BB %lor.lhs.false.47
	    Predecessors according to CFG: BB#16
2896B		%vreg127<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg127
2912B		CMP64mi8 %vreg127, 1, %noreg, 32, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%arr248] GR64:%vreg127
2928B		JE_1 <BB#19>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#19 BB#18

2944B	BB#18: derived from LLVM BB %lor.lhs.false.51
	    Predecessors according to CFG: BB#17
2960B		%vreg130<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg130
2976B		CMP64mi8 %vreg130, 1, %noreg, 40, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%ftab52] GR64:%vreg130
2992B		JNE_1 <BB#28>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#28 BB#19

3008B	BB#19: derived from LLVM BB %if.then.55
	    Predecessors according to CFG: BB#16 BB#17 BB#18
3024B		%vreg202<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg202
3040B		CMP64mi8 %vreg202, 1, %noreg, 24, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%arr156] GR64:%vreg202
3056B		JE_1 <BB#21>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#21 BB#20

3072B	BB#20: derived from LLVM BB %if.then.59
	    Predecessors according to CFG: BB#19
3088B		%vreg216<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg216
3104B		%vreg215<def> = MOV64rm %vreg216, 1, %noreg, 64, %noreg; mem:LD8[%bzfree60] GR64:%vreg215,%vreg216
3120B		%vreg213<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg213
3136B		%vreg212<def> = MOV64rm %vreg213, 1, %noreg, 72, %noreg; mem:LD8[%opaque61] GR64:%vreg212,%vreg213
3152B		%vreg210<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg210
3168B		%vreg209<def> = MOV64rm %vreg210, 1, %noreg, 24, %noreg; mem:LD8[%arr162] GR64:%vreg209,%vreg210
3184B		%vreg207<def> = COPY %vreg209; GR64:%vreg207,%vreg209
3200B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3216B		%RDI<def> = COPY %vreg212; GR64:%vreg212
3232B		%RSI<def> = COPY %vreg207; GR64:%vreg207
3248B		CALL64r %vreg215, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>; GR64:%vreg215
3264B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3280B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3296B		STACKMAP 6, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1]
3312B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#21

3328B	BB#21: derived from LLVM BB %if.end.63
	    Predecessors according to CFG: BB#19 BB#20
3344B		%vreg219<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg219
3360B		CMP64mi8 %vreg219, 1, %noreg, 32, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%arr264] GR64:%vreg219
3376B		JE_1 <BB#23>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#23 BB#22

3392B	BB#22: derived from LLVM BB %if.then.67
	    Predecessors according to CFG: BB#21
3408B		%vreg233<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg233
3424B		%vreg232<def> = MOV64rm %vreg233, 1, %noreg, 64, %noreg; mem:LD8[%bzfree68] GR64:%vreg232,%vreg233
3440B		%vreg230<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg230
3456B		%vreg229<def> = MOV64rm %vreg230, 1, %noreg, 72, %noreg; mem:LD8[%opaque69] GR64:%vreg229,%vreg230
3472B		%vreg227<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg227
3488B		%vreg226<def> = MOV64rm %vreg227, 1, %noreg, 32, %noreg; mem:LD8[%arr270] GR64:%vreg226,%vreg227
3504B		%vreg224<def> = COPY %vreg226; GR64:%vreg224,%vreg226
3520B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3536B		%RDI<def> = COPY %vreg229; GR64:%vreg229
3552B		%RSI<def> = COPY %vreg224; GR64:%vreg224
3568B		CALL64r %vreg232, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>; GR64:%vreg232
3584B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3600B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3616B		STACKMAP 7, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1]
3632B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#23

3648B	BB#23: derived from LLVM BB %if.end.71
	    Predecessors according to CFG: BB#21 BB#22
3664B		%vreg236<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg236
3680B		CMP64mi8 %vreg236, 1, %noreg, 40, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%ftab72] GR64:%vreg236
3696B		JE_1 <BB#25>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#25 BB#24

3712B	BB#24: derived from LLVM BB %if.then.75
	    Predecessors according to CFG: BB#23
3728B		%vreg250<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg250
3744B		%vreg249<def> = MOV64rm %vreg250, 1, %noreg, 64, %noreg; mem:LD8[%bzfree76] GR64:%vreg249,%vreg250
3760B		%vreg247<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg247
3776B		%vreg246<def> = MOV64rm %vreg247, 1, %noreg, 72, %noreg; mem:LD8[%opaque77] GR64:%vreg246,%vreg247
3792B		%vreg244<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg244
3808B		%vreg243<def> = MOV64rm %vreg244, 1, %noreg, 40, %noreg; mem:LD8[%ftab78] GR64:%vreg243,%vreg244
3824B		%vreg241<def> = COPY %vreg243; GR64:%vreg241,%vreg243
3840B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3856B		%RDI<def> = COPY %vreg246; GR64:%vreg246
3872B		%RSI<def> = COPY %vreg241; GR64:%vreg241
3888B		CALL64r %vreg249, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>; GR64:%vreg249
3904B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3920B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3936B		STACKMAP 8, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1]
3952B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#25

3968B	BB#25: derived from LLVM BB %if.end.79
	    Predecessors according to CFG: BB#23 BB#24
3984B		CMP64mi8 <fi#6>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%s]
4000B		JE_1 <BB#27>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#27 BB#26

4016B	BB#26: derived from LLVM BB %if.then.82
	    Predecessors according to CFG: BB#25
4032B		%vreg263<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg263
4048B		%vreg262<def> = MOV64rm %vreg263, 1, %noreg, 64, %noreg; mem:LD8[%bzfree83] GR64:%vreg262,%vreg263
4064B		%vreg260<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg260
4080B		%vreg259<def> = MOV64rm %vreg260, 1, %noreg, 72, %noreg; mem:LD8[%opaque84] GR64:%vreg259,%vreg260
4096B		%vreg257<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg257
4112B		%vreg256<def> = COPY %vreg257; GR64:%vreg256,%vreg257
4128B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4144B		%RDI<def> = COPY %vreg259; GR64:%vreg259
4160B		%RSI<def> = COPY %vreg256; GR64:%vreg256
4176B		CALL64r %vreg262, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>; GR64:%vreg262
4192B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4208B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4224B		STACKMAP 9, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
4240B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#27

4256B	BB#27: derived from LLVM BB %if.end.85
	    Predecessors according to CFG: BB#25 BB#26
4272B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -3; mem:ST4[%retval]
4288B		JMP_1 <BB#29>
	    Successors according to CFG: BB#29

4304B	BB#28: derived from LLVM BB %if.end.86
	    Predecessors according to CFG: BB#18
4320B		%vreg199<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg199
4336B		MOV32mi %vreg199, 1, %noreg, 660, %noreg, 0; mem:ST4[%blockNo] GR64:%vreg199
4352B		%vreg197<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg197
4368B		MOV32mi %vreg197, 1, %noreg, 12, %noreg, 2; mem:ST4[%state] GR64:%vreg197
4384B		%vreg195<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg195
4400B		MOV32mi %vreg195, 1, %noreg, 8, %noreg, 2; mem:ST4[%mode] GR64:%vreg195
4416B		%vreg193<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg193
4432B		MOV32mi %vreg193, 1, %noreg, 652, %noreg, 0; mem:ST4[%combinedCRC] GR64:%vreg193
4448B		%vreg191<def> = MOV32rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD4[%blockSize100k.addr] GR32:%vreg191
4464B		%vreg190<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg190
4480B		MOV32mr %vreg190, 1, %noreg, 664, %noreg, %vreg191; mem:ST4[%blockSize100k87] GR64:%vreg190 GR32:%vreg191
4496B		%vreg187<def> = IMUL32rmi <fi#2>, 1, %noreg, 0, %noreg, 100000, %EFLAGS<imp-def,dead>; mem:LD4[%blockSize100k.addr] GR32:%vreg187
4512B		%vreg185<def> = COPY %vreg187; GR32:%vreg185,%vreg187
4528B		%vreg185<def,tied1> = SUB32ri8 %vreg185<tied0>, 19, %EFLAGS<imp-def,dead>; GR32:%vreg185
4544B		%vreg183<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg183
4560B		MOV32mr %vreg183, 1, %noreg, 112, %noreg, %vreg185; mem:ST4[%nblockMAX] GR64:%vreg183 GR32:%vreg185
4576B		%vreg180<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%verbosity.addr] GR32:%vreg180
4592B		%vreg179<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg179
4608B		MOV32mr %vreg179, 1, %noreg, 656, %noreg, %vreg180; mem:ST4[%verbosity89] GR64:%vreg179 GR32:%vreg180
4624B		%vreg176<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%workFactor.addr] GR32:%vreg176
4640B		%vreg175<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg175
4656B		MOV32mr %vreg175, 1, %noreg, 88, %noreg, %vreg176; mem:ST4[%workFactor90] GR64:%vreg175 GR32:%vreg176
4672B		%vreg172<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg172
4688B		%vreg171<def> = MOV64rm %vreg172, 1, %noreg, 32, %noreg; mem:LD8[%arr291] GR64:%vreg171,%vreg172
4704B		%vreg169<def> = COPY %vreg171; GR64:%vreg169,%vreg171
4720B		%vreg167<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg167
4736B		MOV64mr %vreg167, 1, %noreg, 64, %noreg, %vreg169; mem:ST8[%block] GR64:%vreg167,%vreg169
4752B		%vreg164<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg164
4768B		%vreg163<def> = MOV64rm %vreg164, 1, %noreg, 24, %noreg; mem:LD8[%arr192] GR64:%vreg163,%vreg164
4784B		%vreg161<def> = COPY %vreg163; GR64:%vreg161,%vreg163
4800B		%vreg159<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg159
4816B		MOV64mr %vreg159, 1, %noreg, 72, %noreg, %vreg161; mem:ST8[%mtfv] GR64:%vreg159,%vreg161
4832B		%vreg156<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg156
4848B		MOV64mi32 %vreg156, 1, %noreg, 80, %noreg, 0; mem:ST8[%zbits] GR64:%vreg156
4864B		%vreg154<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg154
4880B		%vreg153<def> = MOV64rm %vreg154, 1, %noreg, 24, %noreg; mem:LD8[%arr193] GR64:%vreg153,%vreg154
4896B		%vreg151<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg151
4912B		MOV64mr %vreg151, 1, %noreg, 56, %noreg, %vreg153; mem:ST8[%ptr] GR64:%vreg151,%vreg153
4928B		%vreg148<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg148
4944B		%vreg147<def> = COPY %vreg148; GR64:%vreg147,%vreg148
4960B		%vreg145<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg145
4976B		MOV64mr %vreg145, 1, %noreg, 48, %noreg, %vreg147; mem:ST8[%state94] GR64:%vreg145,%vreg147
4992B		%vreg142<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg142
5008B		MOV32mi %vreg142, 1, %noreg, 12, %noreg, 0; mem:ST4[%total_in_lo32] GR64:%vreg142
5024B		%vreg140<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg140
5040B		MOV32mi %vreg140, 1, %noreg, 16, %noreg, 0; mem:ST4[%total_in_hi32] GR64:%vreg140
5056B		%vreg138<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg138
5072B		MOV32mi %vreg138, 1, %noreg, 36, %noreg, 0; mem:ST4[%total_out_lo32] GR64:%vreg138
5088B		%vreg136<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg136
5104B		MOV32mi %vreg136, 1, %noreg, 40, %noreg, 0; mem:ST4[%total_out_hi32] GR64:%vreg136
5120B		%vreg134<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg134
5136B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5152B		%RDI<def> = COPY %vreg134; GR64:%vreg134
5168B		CALL64pcrel32 <ga:@init_RL>, <regmask>, %RSP<imp-use>, %RDI<imp-use>
5184B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5200B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5216B		STACKMAP 10, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack6]
5232B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5248B		%vreg132<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg132
5264B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5280B		%RDI<def> = COPY %vreg132; GR64:%vreg132
5296B		CALL64pcrel32 <ga:@prepare_new_block>, <regmask>, %RSP<imp-use>, %RDI<imp-use>
5312B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5328B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5344B		STACKMAP 11, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
5360B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5376B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
	    Successors according to CFG: BB#29

5392B	BB#29: derived from LLVM BB %return
	    Predecessors according to CFG: BB#1 BB#28 BB#27 BB#15 BB#7
5408B		%vreg266<def> = MOV64ri <ga:@BZ2_bzCompressInit>; GR64:%vreg266
5424B		%vreg267<def> = COPY %vreg266; GR64:%vreg267,%vreg266
5440B		%vreg268<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg268
5456B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5472B		%RDI<def> = COPY %vreg267; GR64:%vreg267
5488B		%RSI<def> = COPY %vreg268; GR64:%vreg268
5504B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
5520B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5536B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5552B		STACKMAP 12, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
5568B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5584B		%vreg265<def> = MOV32rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD4[%retval] GR32:%vreg265
5600B		%EAX<def> = COPY %vreg265; GR32:%vreg265
5616B		RETQ %EAX<imp-use,kill>

# End machine code for function BZ2_bzCompressInit.

********** SIMPLE REGISTER COALESCING **********
********** Function: BZ2_bzCompressInit
********** JOINING INTERVALS ***********
if.then.8:
if.then.55:
return:
5472B	%RDI<def> = COPY %vreg267; GR64:%vreg267
	Considering merging %vreg267 with %RDI
	Can only merge into reserved registers.
5488B	%RSI<def> = COPY %vreg268; GR64:%vreg268
	Considering merging %vreg268 with %RSI
	Can only merge into reserved registers.
5600B	%EAX<def> = COPY %vreg265; GR32:%vreg265
	Considering merging %vreg265 with %EAX
	Can only merge into reserved registers.
if.end.12:
if.end.16:
if.end.20:
1328B	%RDI<def> = COPY %vreg41; GR64:%vreg41
	Considering merging %vreg41 with %RDI
	Can only merge into reserved registers.
1344B	%ESI<def> = COPY %vreg36; GR32:%vreg36
	Considering merging %vreg36 with %ESI
	Can only merge into reserved registers.
Remat: %ESI<def> = MOV32ri 55768
Shrink: %vreg36 [1216r,1344r:0)  0@1216r
All defs dead: 1216r	%vreg36<def,dead> = MOV32ri 55768; GR32:%vreg36
Shrunk: %vreg36 [1216r,1216d:0)  0@1216r
Deleting dead def 1216r	%vreg36<def,dead> = MOV32ri 55768; GR32:%vreg36
1360B	%EDX<def> = COPY %vreg37; GR32:%vreg37
	Considering merging %vreg37 with %EDX
	Can only merge into reserved registers.
Remat: %EDX<def> = MOV32ri 1
Shrink: %vreg37 [1232r,1360r:0)  0@1232r
All defs dead: 1232r	%vreg37<def,dead> = MOV32ri 1; GR32:%vreg37
Shrunk: %vreg37 [1232r,1232d:0)  0@1232r
Deleting dead def 1232r	%vreg37<def,dead> = MOV32ri 1; GR32:%vreg37
1408B	%vreg39<def> = COPY %RAX<kill>; GR64:%vreg39
	Considering merging %vreg39 with %RAX
	Can only merge into reserved registers.
if.end.63:
if.end.71:
if.end.79:
if.end:
lor.lhs.false:
lor.lhs.false.2:
lor.lhs.false.4:
lor.lhs.false.6:
if.end.9:
if.end.25:
1936B	%RDI<def> = COPY %vreg107; GR64:%vreg107
	Considering merging %vreg107 with %RDI
	Can only merge into reserved registers.
1952B	%ESI<def> = COPY %vreg101; GR32:%vreg101
	Considering merging %vreg101 with %ESI
	Can only merge into reserved registers.
1968B	%EDX<def> = COPY %vreg97; GR32:%vreg97
	Considering merging %vreg97 with %EDX
	Can only merge into reserved registers.
Remat: %EDX<def> = MOV32ri 1
Shrink: %vreg97 [1600r,1968r:0)  0@1600r
All defs dead: 1600r	%vreg97<def,dead> = MOV32ri 1; GR32:%vreg97
Shrunk: %vreg97 [1600r,1600d:0)  0@1600r
Deleting dead def 1600r	%vreg97<def,dead> = MOV32ri 1; GR32:%vreg97
2016B	%vreg99<def> = COPY %RAX<kill>; GR64:%vreg99
	Considering merging %vreg99 with %RAX
	Can only merge into reserved registers.
2336B	%RDI<def> = COPY %vreg85; GR64:%vreg85
	Considering merging %vreg85 with %RDI
	Can only merge into reserved registers.
2352B	%ESI<def> = COPY %vreg76; GR32:%vreg76
	Considering merging %vreg76 with %ESI
	Can only merge into reserved registers.
2368B	%EDX<def> = COPY %vreg72; GR32:%vreg72
	Considering merging %vreg72 with %EDX
	Can only merge into reserved registers.
Remat: %EDX<def> = MOV32ri 1
Shrink: %vreg72 [2032r,2368r:0)  0@2032r
All defs dead: 2032r	%vreg72<def,dead> = MOV32ri 1; GR32:%vreg72
Shrunk: %vreg72 [2032r,2032d:0)  0@2032r
Deleting dead def 2032r	%vreg72<def,dead> = MOV32ri 1; GR32:%vreg72
2416B	%vreg74<def> = COPY %RAX<kill>; GR64:%vreg74
	Considering merging %vreg74 with %RAX
	Can only merge into reserved registers.
2640B	%RDI<def> = COPY %vreg60; GR64:%vreg60
	Considering merging %vreg60 with %RDI
	Can only merge into reserved registers.
2656B	%ESI<def> = COPY %vreg55; GR32:%vreg55
	Considering merging %vreg55 with %ESI
	Can only merge into reserved registers.
Remat: %ESI<def> = MOV32ri 262148
Shrink: %vreg55 [2432r,2656r:0)  0@2432r
All defs dead: 2432r	%vreg55<def,dead> = MOV32ri 262148; GR32:%vreg55
Shrunk: %vreg55 [2432r,2432d:0)  0@2432r
Deleting dead def 2432r	%vreg55<def,dead> = MOV32ri 262148; GR32:%vreg55
2672B	%EDX<def> = COPY %vreg56; GR32:%vreg56
	Considering merging %vreg56 with %EDX
	Can only merge into reserved registers.
Remat: %EDX<def> = MOV32ri 1
Shrink: %vreg56 [2448r,2672r:0)  0@2448r
All defs dead: 2448r	%vreg56<def,dead> = MOV32ri 1; GR32:%vreg56
Shrunk: %vreg56 [2448r,2448d:0)  0@2448r
Deleting dead def 2448r	%vreg56<def,dead> = MOV32ri 1; GR32:%vreg56
2720B	%vreg58<def> = COPY %RAX<kill>; GR64:%vreg58
	Considering merging %vreg58 with %RAX
	Can only merge into reserved registers.
lor.lhs.false.47:
lor.lhs.false.51:
if.end.85:
entry:
16B	%vreg6<def> = COPY %ECX; GR32:%vreg6
	Considering merging %vreg6 with %ECX
	Can only merge into reserved registers.
32B	%vreg4<def> = COPY %EDX; GR32:%vreg4
	Considering merging %vreg4 with %EDX
	Can only merge into reserved registers.
48B	%vreg2<def> = COPY %ESI; GR32:%vreg2
	Considering merging %vreg2 with %ESI
	Can only merge into reserved registers.
64B	%vreg0<def> = COPY %RDI; GR64:%vreg0
	Considering merging %vreg0 with %RDI
	Can only merge into reserved registers.
208B	%RDI<def> = COPY %vreg11; GR64:%vreg11
	Considering merging %vreg11 with %RDI
	Can only merge into reserved registers.
224B	%RSI<def> = COPY %vreg12; GR64:%vreg12
	Considering merging %vreg12 with %RSI
	Can only merge into reserved registers.
432B	%vreg9<def> = COPY %EAX<kill>; GR32:%vreg9
	Considering merging %vreg9 with %EAX
	Can only merge into reserved registers.
if.then:
if.then.11:
if.then.14:
if.then.18:
if.then.24:
if.then.59:
3216B	%RDI<def> = COPY %vreg212; GR64:%vreg212
	Considering merging %vreg212 with %RDI
	Can only merge into reserved registers.
3232B	%RSI<def> = COPY %vreg207; GR64:%vreg207
	Considering merging %vreg207 with %RSI
	Can only merge into reserved registers.
if.then.67:
3536B	%RDI<def> = COPY %vreg229; GR64:%vreg229
	Considering merging %vreg229 with %RDI
	Can only merge into reserved registers.
3552B	%RSI<def> = COPY %vreg224; GR64:%vreg224
	Considering merging %vreg224 with %RSI
	Can only merge into reserved registers.
if.then.75:
3856B	%RDI<def> = COPY %vreg246; GR64:%vreg246
	Considering merging %vreg246 with %RDI
	Can only merge into reserved registers.
3872B	%RSI<def> = COPY %vreg241; GR64:%vreg241
	Considering merging %vreg241 with %RSI
	Can only merge into reserved registers.
if.then.82:
4144B	%RDI<def> = COPY %vreg259; GR64:%vreg259
	Considering merging %vreg259 with %RDI
	Can only merge into reserved registers.
4160B	%RSI<def> = COPY %vreg256; GR64:%vreg256
	Considering merging %vreg256 with %RSI
	Can only merge into reserved registers.
if.end.86:
5152B	%RDI<def> = COPY %vreg134; GR64:%vreg134
	Considering merging %vreg134 with %RDI
	Can only merge into reserved registers.
5280B	%RDI<def> = COPY %vreg132; GR64:%vreg132
	Considering merging %vreg132 with %RDI
	Can only merge into reserved registers.
5424B	%vreg267<def> = COPY %vreg266; GR64:%vreg267,%vreg266
	Considering merging to GR64 with %vreg266 in %vreg267
		RHS = %vreg266 [5408r,5424r:0)  0@5408r
		LHS = %vreg267 [5424r,5472r:0)  0@5424r
		merge %vreg267:0@5424r into %vreg266:0@5408r --> @5408r
		erased:	5424r	%vreg267<def> = COPY %vreg266; GR64:%vreg267,%vreg266
		updated: 5408B	%vreg267<def> = MOV64ri <ga:@BZ2_bzCompressInit>; GR64:%vreg267
	Success: %vreg266 -> %vreg267
	Result = %vreg267 [5408r,5472r:0)  0@5408r
1472B	%vreg34<def> = COPY %vreg39; GR64:%vreg34,%vreg39
	Considering merging to GR64 with %vreg39 in %vreg34
		RHS = %vreg39 [1408r,1472r:0)  0@1408r
		LHS = %vreg34 [1472r,1488r:0)  0@1472r
		merge %vreg34:0@1472r into %vreg39:0@1408r --> @1408r
		erased:	1472r	%vreg34<def> = COPY %vreg39; GR64:%vreg34,%vreg39
		updated: 1408B	%vreg34<def> = COPY %RAX<kill>; GR64:%vreg34
	Success: %vreg39 -> %vreg34
	Result = %vreg34 [1408r,1488r:0)  0@1408r
1872B	%vreg103<def> = COPY %vreg105; GR64:%vreg103,%vreg105
	Considering merging to GR64 with %vreg105 in %vreg103
		RHS = %vreg105 [1856r,1872r:0)  0@1856r
		LHS = %vreg103 [1872r,1888r:0)[1888r,1904r:1)  0@1872r 1@1888r
		merge %vreg103:0@1872r into %vreg105:0@1856r --> @1856r
		erased:	1872r	%vreg103<def> = COPY %vreg105; GR64:%vreg103,%vreg105
		updated: 1856B	%vreg103<def> = MOVSX64rm32 <fi#5>, 1, %noreg, 0, %noreg; mem:LD4[%n] GR64:%vreg103
	Success: %vreg105 -> %vreg103
	Result = %vreg103 [1856r,1888r:0)[1888r,1904r:1)  0@1856r 1@1888r
1904B	%vreg101<def> = COPY %vreg103:sub_32bit; GR32:%vreg101 GR64:%vreg103
	Considering merging to GR64_with_sub_8bit with %vreg101 in %vreg103:sub_32bit
		RHS = %vreg101 [1904r,1952r:0)  0@1904r
		LHS = %vreg103 [1856r,1888r:0)[1888r,1904r:1)  0@1856r 1@1888r
		merge %vreg101:0@1904r into %vreg103:1@1888r --> @1888r
		erased:	1904r	%vreg101<def> = COPY %vreg103:sub_32bit; GR32:%vreg101 GR64:%vreg103
AllocationOrder(GR64_with_sub_8bit) = [ %RAX %RCX %RDX %RSI %RDI %R8 %R9 %R10 %R11 %RBX %R14 %R15 %R12 %R13 ]
		updated: 1952B	%ESI<def> = COPY %vreg103:sub_32bit; GR64_with_sub_8bit:%vreg103
	Success: %vreg101:sub_32bit -> %vreg103
	Result = %vreg103 [1856r,1888r:0)[1888r,1952r:1)  0@1856r 1@1888r
2096B	%vreg94<def> = COPY %vreg99; GR64:%vreg94,%vreg99
	Considering merging to GR64 with %vreg99 in %vreg94
		RHS = %vreg99 [2016r,2096r:0)  0@2016r
		LHS = %vreg94 [2096r,2128r:0)  0@2096r
		merge %vreg94:0@2096r into %vreg99:0@2016r --> @2016r
		erased:	2096r	%vreg94<def> = COPY %vreg99; GR64:%vreg94,%vreg99
		updated: 2016B	%vreg94<def> = COPY %RAX<kill>; GR64:%vreg94
	Success: %vreg99 -> %vreg94
	Result = %vreg94 [2016r,2128r:0)  0@2016r
2224B	%vreg82<def> = COPY %vreg83; GR32:%vreg82,%vreg83
	Considering merging to GR32 with %vreg83 in %vreg82
		RHS = %vreg83 [2208r,2224r:0)  0@2208r
		LHS = %vreg82 [2224r,2240r:0)[2240r,2256r:1)  0@2224r 1@2240r
		merge %vreg82:0@2224r into %vreg83:0@2208r --> @2208r
		erased:	2224r	%vreg82<def> = COPY %vreg83; GR32:%vreg82,%vreg83
		updated: 2208B	%vreg82<def> = MOV32rm <fi#5>, 1, %noreg, 0, %noreg; mem:LD4[%n] GR32:%vreg82
	Success: %vreg83 -> %vreg82
	Result = %vreg82 [2208r,2240r:0)[2240r,2256r:1)  0@2208r 1@2240r
2272B	%vreg78<def> = COPY %vreg80; GR64:%vreg78,%vreg80
	Considering merging to GR64 with %vreg80 in %vreg78
		RHS = %vreg80 [2256r,2272r:0)  0@2256r
		LHS = %vreg78 [2272r,2288r:0)[2288r,2304r:1)  0@2272r 1@2288r
		merge %vreg78:0@2272r into %vreg80:0@2256r --> @2256r
		erased:	2272r	%vreg78<def> = COPY %vreg80; GR64:%vreg78,%vreg80
		updated: 2256B	%vreg78<def> = MOVSX64rr32 %vreg82; GR64:%vreg78 GR32:%vreg82
	Success: %vreg80 -> %vreg78
	Result = %vreg78 [2256r,2288r:0)[2288r,2304r:1)  0@2256r 1@2288r
2304B	%vreg76<def> = COPY %vreg78:sub_32bit; GR32:%vreg76 GR64:%vreg78
	Considering merging to GR64_with_sub_8bit with %vreg76 in %vreg78:sub_32bit
		RHS = %vreg76 [2304r,2352r:0)  0@2304r
		LHS = %vreg78 [2256r,2288r:0)[2288r,2304r:1)  0@2256r 1@2288r
		merge %vreg76:0@2304r into %vreg78:1@2288r --> @2288r
		erased:	2304r	%vreg76<def> = COPY %vreg78:sub_32bit; GR32:%vreg76 GR64:%vreg78
		updated: 2352B	%ESI<def> = COPY %vreg78:sub_32bit; GR64_with_sub_8bit:%vreg78
	Success: %vreg76:sub_32bit -> %vreg78
	Result = %vreg78 [2256r,2288r:0)[2288r,2352r:1)  0@2256r 1@2288r
2512B	%vreg69<def> = COPY %vreg74; GR64:%vreg69,%vreg74
	Considering merging to GR64 with %vreg74 in %vreg69
		RHS = %vreg74 [2416r,2512r:0)  0@2416r
		LHS = %vreg69 [2512r,2544r:0)  0@2512r
		merge %vreg69:0@2512r into %vreg74:0@2416r --> @2416r
		erased:	2512r	%vreg69<def> = COPY %vreg74; GR64:%vreg69,%vreg74
		updated: 2416B	%vreg69<def> = COPY %RAX<kill>; GR64:%vreg69
	Success: %vreg74 -> %vreg69
	Result = %vreg69 [2416r,2544r:0)  0@2416r
2784B	%vreg53<def> = COPY %vreg58; GR64:%vreg53,%vreg58
	Considering merging to GR64 with %vreg58 in %vreg53
		RHS = %vreg58 [2720r,2784r:0)  0@2720r
		LHS = %vreg53 [2784r,2816r:0)  0@2784r
		merge %vreg53:0@2784r into %vreg58:0@2720r --> @2720r
		erased:	2784r	%vreg53<def> = COPY %vreg58; GR64:%vreg53,%vreg58
		updated: 2720B	%vreg53<def> = COPY %RAX<kill>; GR64:%vreg53
	Success: %vreg58 -> %vreg53
	Result = %vreg53 [2720r,2816r:0)  0@2720r
80B	%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
	Considering merging to GR64 with %vreg0 in %vreg1
		RHS = %vreg0 [64r,80r:0)  0@64r
		LHS = %vreg1 [80r,320r:0)  0@80r
		merge %vreg1:0@80r into %vreg0:0@64r --> @64r
		erased:	80r	%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
		updated: 64B	%vreg1<def> = COPY %RDI; GR64:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [64r,320r:0)  0@64r
96B	%vreg3<def> = COPY %vreg2; GR32:%vreg3,%vreg2
	Considering merging to GR32 with %vreg2 in %vreg3
		RHS = %vreg2 [48r,96r:0)  0@48r
		LHS = %vreg3 [96r,336r:0)  0@96r
		merge %vreg3:0@96r into %vreg2:0@48r --> @48r
		erased:	96r	%vreg3<def> = COPY %vreg2; GR32:%vreg3,%vreg2
		updated: 48B	%vreg3<def> = COPY %ESI; GR32:%vreg3
	Success: %vreg2 -> %vreg3
	Result = %vreg3 [48r,336r:0)  0@48r
112B	%vreg5<def> = COPY %vreg4; GR32:%vreg5,%vreg4
	Considering merging to GR32 with %vreg4 in %vreg5
		RHS = %vreg4 [32r,112r:0)  0@32r
		LHS = %vreg5 [112r,352r:0)  0@112r
		merge %vreg5:0@112r into %vreg4:0@32r --> @32r
		erased:	112r	%vreg5<def> = COPY %vreg4; GR32:%vreg5,%vreg4
		updated: 32B	%vreg5<def> = COPY %EDX; GR32:%vreg5
	Success: %vreg4 -> %vreg5
	Result = %vreg5 [32r,352r:0)  0@32r
128B	%vreg7<def> = COPY %vreg6; GR32:%vreg7,%vreg6
	Considering merging to GR32 with %vreg6 in %vreg7
		RHS = %vreg6 [16r,128r:0)  0@16r
		LHS = %vreg7 [128r,368r:0)  0@128r
		merge %vreg7:0@128r into %vreg6:0@16r --> @16r
		erased:	128r	%vreg7<def> = COPY %vreg6; GR32:%vreg7,%vreg6
		updated: 16B	%vreg7<def> = COPY %ECX; GR32:%vreg7
	Success: %vreg6 -> %vreg7
	Result = %vreg7 [16r,368r:0)  0@16r
160B	%vreg11<def> = COPY %vreg10; GR64:%vreg11,%vreg10
	Considering merging to GR64 with %vreg10 in %vreg11
		RHS = %vreg10 [144r,160r:0)  0@144r
		LHS = %vreg11 [160r,208r:0)  0@160r
		merge %vreg11:0@160r into %vreg10:0@144r --> @144r
		erased:	160r	%vreg11<def> = COPY %vreg10; GR64:%vreg11,%vreg10
		updated: 144B	%vreg11<def> = MOV64ri <ga:@BZ2_bzCompressInit>; GR64:%vreg11
	Success: %vreg10 -> %vreg11
	Result = %vreg11 [144r,208r:0)  0@144r
3184B	%vreg207<def> = COPY %vreg209; GR64:%vreg207,%vreg209
	Considering merging to GR64 with %vreg209 in %vreg207
		RHS = %vreg209 [3168r,3184r:0)  0@3168r
		LHS = %vreg207 [3184r,3232r:0)  0@3184r
		merge %vreg207:0@3184r into %vreg209:0@3168r --> @3168r
		erased:	3184r	%vreg207<def> = COPY %vreg209; GR64:%vreg207,%vreg209
		updated: 3168B	%vreg207<def> = MOV64rm %vreg210, 1, %noreg, 24, %noreg; mem:LD8[%arr162] GR64:%vreg207,%vreg210
	Success: %vreg209 -> %vreg207
	Result = %vreg207 [3168r,3232r:0)  0@3168r
3504B	%vreg224<def> = COPY %vreg226; GR64:%vreg224,%vreg226
	Considering merging to GR64 with %vreg226 in %vreg224
		RHS = %vreg226 [3488r,3504r:0)  0@3488r
		LHS = %vreg224 [3504r,3552r:0)  0@3504r
		merge %vreg224:0@3504r into %vreg226:0@3488r --> @3488r
		erased:	3504r	%vreg224<def> = COPY %vreg226; GR64:%vreg224,%vreg226
		updated: 3488B	%vreg224<def> = MOV64rm %vreg227, 1, %noreg, 32, %noreg; mem:LD8[%arr270] GR64:%vreg224,%vreg227
	Success: %vreg226 -> %vreg224
	Result = %vreg224 [3488r,3552r:0)  0@3488r
3824B	%vreg241<def> = COPY %vreg243; GR64:%vreg241,%vreg243
	Considering merging to GR64 with %vreg243 in %vreg241
		RHS = %vreg243 [3808r,3824r:0)  0@3808r
		LHS = %vreg241 [3824r,3872r:0)  0@3824r
		merge %vreg241:0@3824r into %vreg243:0@3808r --> @3808r
		erased:	3824r	%vreg241<def> = COPY %vreg243; GR64:%vreg241,%vreg243
		updated: 3808B	%vreg241<def> = MOV64rm %vreg244, 1, %noreg, 40, %noreg; mem:LD8[%ftab78] GR64:%vreg241,%vreg244
	Success: %vreg243 -> %vreg241
	Result = %vreg241 [3808r,3872r:0)  0@3808r
4112B	%vreg256<def> = COPY %vreg257; GR64:%vreg256,%vreg257
	Considering merging to GR64 with %vreg257 in %vreg256
		RHS = %vreg257 [4096r,4112r:0)  0@4096r
		LHS = %vreg256 [4112r,4160r:0)  0@4112r
		merge %vreg256:0@4112r into %vreg257:0@4096r --> @4096r
		erased:	4112r	%vreg256<def> = COPY %vreg257; GR64:%vreg256,%vreg257
		updated: 4096B	%vreg256<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg256
	Success: %vreg257 -> %vreg256
	Result = %vreg256 [4096r,4160r:0)  0@4096r
4512B	%vreg185<def> = COPY %vreg187; GR32:%vreg185,%vreg187
	Considering merging to GR32 with %vreg187 in %vreg185
		RHS = %vreg187 [4496r,4512r:0)  0@4496r
		LHS = %vreg185 [4512r,4528r:0)[4528r,4560r:1)  0@4512r 1@4528r
		merge %vreg185:0@4512r into %vreg187:0@4496r --> @4496r
		erased:	4512r	%vreg185<def> = COPY %vreg187; GR32:%vreg185,%vreg187
		updated: 4496B	%vreg185<def> = IMUL32rmi <fi#2>, 1, %noreg, 0, %noreg, 100000, %EFLAGS<imp-def,dead>; mem:LD4[%blockSize100k.addr] GR32:%vreg185
	Success: %vreg187 -> %vreg185
	Result = %vreg185 [4496r,4528r:0)[4528r,4560r:1)  0@4496r 1@4528r
4704B	%vreg169<def> = COPY %vreg171; GR64:%vreg169,%vreg171
	Considering merging to GR64 with %vreg171 in %vreg169
		RHS = %vreg171 [4688r,4704r:0)  0@4688r
		LHS = %vreg169 [4704r,4736r:0)  0@4704r
		merge %vreg169:0@4704r into %vreg171:0@4688r --> @4688r
		erased:	4704r	%vreg169<def> = COPY %vreg171; GR64:%vreg169,%vreg171
		updated: 4688B	%vreg169<def> = MOV64rm %vreg172, 1, %noreg, 32, %noreg; mem:LD8[%arr291] GR64:%vreg169,%vreg172
	Success: %vreg171 -> %vreg169
	Result = %vreg169 [4688r,4736r:0)  0@4688r
4784B	%vreg161<def> = COPY %vreg163; GR64:%vreg161,%vreg163
	Considering merging to GR64 with %vreg163 in %vreg161
		RHS = %vreg163 [4768r,4784r:0)  0@4768r
		LHS = %vreg161 [4784r,4816r:0)  0@4784r
		merge %vreg161:0@4784r into %vreg163:0@4768r --> @4768r
		erased:	4784r	%vreg161<def> = COPY %vreg163; GR64:%vreg161,%vreg163
		updated: 4768B	%vreg161<def> = MOV64rm %vreg164, 1, %noreg, 24, %noreg; mem:LD8[%arr192] GR64:%vreg161,%vreg164
	Success: %vreg163 -> %vreg161
	Result = %vreg161 [4768r,4816r:0)  0@4768r
4944B	%vreg147<def> = COPY %vreg148; GR64:%vreg147,%vreg148
	Considering merging to GR64 with %vreg148 in %vreg147
		RHS = %vreg148 [4928r,4944r:0)  0@4928r
		LHS = %vreg147 [4944r,4976r:0)  0@4944r
		merge %vreg147:0@4944r into %vreg148:0@4928r --> @4928r
		erased:	4944r	%vreg147<def> = COPY %vreg148; GR64:%vreg147,%vreg148
		updated: 4928B	%vreg147<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg147
	Success: %vreg148 -> %vreg147
	Result = %vreg147 [4928r,4976r:0)  0@4928r
5472B	%RDI<def> = COPY %vreg267; GR64:%vreg267
	Considering merging %vreg267 with %RDI
	Can only merge into reserved registers.
1952B	%ESI<def> = COPY %vreg103:sub_32bit; GR64_with_sub_8bit:%vreg103
	Considering merging %vreg103 with %RSI
	Can only merge into reserved registers.
2352B	%ESI<def> = COPY %vreg78:sub_32bit; GR64_with_sub_8bit:%vreg78
	Considering merging %vreg78 with %RSI
	Can only merge into reserved registers.
208B	%RDI<def> = COPY %vreg11; GR64:%vreg11
	Considering merging %vreg11 with %RDI
	Can only merge into reserved registers.
3232B	%RSI<def> = COPY %vreg207; GR64:%vreg207
	Considering merging %vreg207 with %RSI
	Can only merge into reserved registers.
3552B	%RSI<def> = COPY %vreg224; GR64:%vreg224
	Considering merging %vreg224 with %RSI
	Can only merge into reserved registers.
3872B	%RSI<def> = COPY %vreg241; GR64:%vreg241
	Considering merging %vreg241 with %RSI
	Can only merge into reserved registers.
4160B	%RSI<def> = COPY %vreg256; GR64:%vreg256
	Considering merging %vreg256 with %RSI
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
CH [0B,16r:0)  0@0B-phi
CL [0B,16r:0)  0@0B-phi
DH [0B,32r:0)[1360r,1376r:4)[1968r,1984r:1)[2368r,2384r:2)[2672r,2688r:3)  0@0B-phi 1@1968r 2@2368r 3@2672r 4@1360r
DIL [0B,64r:0)[208r,240r:12)[1328r,1376r:11)[1936r,1984r:8)[2336r,2384r:9)[2640r,2688r:10)[3216r,3248r:5)[3536r,3568r:4)[3856r,3888r:3)[4144r,4176r:2)[5152r,5168r:6)[5280r,5296r:7)[5472r,5504r:1)  0@0B-phi 1@5472r 2@4144r 3@3856r 4@3536r 5@3216r 6@5152r 7@5280r 8@1936r 9@2336r 10@2640r 11@1328r 12@208r
DL [0B,32r:0)[1360r,1376r:4)[1968r,1984r:1)[2368r,2384r:2)[2672r,2688r:3)  0@0B-phi 1@1968r 2@2368r 3@2672r 4@1360r
SIL [0B,48r:0)[224r,240r:10)[1344r,1376r:4)[1952r,1984r:1)[2352r,2384r:2)[2656r,2688r:3)[3232r,3248r:9)[3552r,3568r:8)[3872r,3888r:7)[4160r,4176r:6)[5488r,5504r:5)  0@0B-phi 1@1952r 2@2352r 3@2656r 4@1344r 5@5488r 6@4160r 7@3872r 8@3552r 9@3232r 10@224r
%vreg1 [64r,320r:0)  0@64r
%vreg3 [48r,336r:0)  0@48r
%vreg5 [32r,352r:0)  0@32r
%vreg7 [16r,368r:0)  0@16r
%vreg9 [432r,496r:0)  0@432r
%vreg11 [144r,208r:0)  0@144r
%vreg12 [176r,224r:0)  0@176r
%vreg21 [960r,976r:0)  0@960r
%vreg23 [1024r,1056r:0)  0@1024r
%vreg24 [1040r,1056r:0)  0@1040r
%vreg27 [1088r,1104r:0)  0@1088r
%vreg29 [1152r,1184r:0)  0@1152r
%vreg30 [1168r,1184r:0)  0@1168r
%vreg34 [1408r,1488r:0)  0@1408r
%vreg41 [1296r,1328r:0)  0@1296r
%vreg42 [1280r,1296r:0)  0@1280r
%vreg44 [1264r,1376r:0)  0@1264r
%vreg45 [1248r,1264r:0)  0@1248r
%vreg48 [2832r,2848r:0)  0@2832r
%vreg51 [2800r,2816r:0)  0@2800r
%vreg53 [2720r,2816r:0)  0@2720r
%vreg60 [2608r,2640r:0)  0@2608r
%vreg61 [2592r,2608r:0)  0@2592r
%vreg63 [2576r,2688r:0)  0@2576r
%vreg64 [2560r,2576r:0)  0@2560r
%vreg67 [2528r,2544r:0)  0@2528r
%vreg69 [2416r,2544r:0)  0@2416r
%vreg78 [2256r,2288r:0)[2288r,2352r:1)  0@2256r 1@2288r
%vreg82 [2208r,2240r:0)[2240r,2256r:1)  0@2208r 1@2240r
%vreg85 [2192r,2336r:0)  0@2192r
%vreg86 [2176r,2192r:0)  0@2176r
%vreg88 [2160r,2384r:0)  0@2160r
%vreg89 [2144r,2160r:0)  0@2144r
%vreg92 [2112r,2128r:0)  0@2112r
%vreg94 [2016r,2128r:0)  0@2016r
%vreg103 [1856r,1888r:0)[1888r,1952r:1)  0@1856r 1@1888r
%vreg107 [1840r,1936r:0)  0@1840r
%vreg108 [1824r,1840r:0)  0@1824r
%vreg110 [1808r,1984r:0)  0@1808r
%vreg111 [1792r,1808r:0)  0@1792r
%vreg114 [1760r,1776r:0)  0@1760r
%vreg116 [1728r,1744r:0)  0@1728r
%vreg118 [1696r,1712r:0)  0@1696r
%vreg120 [1664r,1680r:0)  0@1664r
%vreg123 [1632r,1648r:0)  0@1632r
%vreg124 [1616r,1648r:0)  0@1616r
%vreg127 [2896r,2912r:0)  0@2896r
%vreg130 [2960r,2976r:0)  0@2960r
%vreg132 [5248r,5280r:0)  0@5248r
%vreg134 [5120r,5152r:0)  0@5120r
%vreg136 [5088r,5104r:0)  0@5088r
%vreg138 [5056r,5072r:0)  0@5056r
%vreg140 [5024r,5040r:0)  0@5024r
%vreg142 [4992r,5008r:0)  0@4992r
%vreg145 [4960r,4976r:0)  0@4960r
%vreg147 [4928r,4976r:0)  0@4928r
%vreg151 [4896r,4912r:0)  0@4896r
%vreg153 [4880r,4912r:0)  0@4880r
%vreg154 [4864r,4880r:0)  0@4864r
%vreg156 [4832r,4848r:0)  0@4832r
%vreg159 [4800r,4816r:0)  0@4800r
%vreg161 [4768r,4816r:0)  0@4768r
%vreg164 [4752r,4768r:0)  0@4752r
%vreg167 [4720r,4736r:0)  0@4720r
%vreg169 [4688r,4736r:0)  0@4688r
%vreg172 [4672r,4688r:0)  0@4672r
%vreg175 [4640r,4656r:0)  0@4640r
%vreg176 [4624r,4656r:0)  0@4624r
%vreg179 [4592r,4608r:0)  0@4592r
%vreg180 [4576r,4608r:0)  0@4576r
%vreg183 [4544r,4560r:0)  0@4544r
%vreg185 [4496r,4528r:0)[4528r,4560r:1)  0@4496r 1@4528r
%vreg190 [4464r,4480r:0)  0@4464r
%vreg191 [4448r,4480r:0)  0@4448r
%vreg193 [4416r,4432r:0)  0@4416r
%vreg195 [4384r,4400r:0)  0@4384r
%vreg197 [4352r,4368r:0)  0@4352r
%vreg199 [4320r,4336r:0)  0@4320r
%vreg202 [3024r,3040r:0)  0@3024r
%vreg207 [3168r,3232r:0)  0@3168r
%vreg210 [3152r,3168r:0)  0@3152r
%vreg212 [3136r,3216r:0)  0@3136r
%vreg213 [3120r,3136r:0)  0@3120r
%vreg215 [3104r,3248r:0)  0@3104r
%vreg216 [3088r,3104r:0)  0@3088r
%vreg219 [3344r,3360r:0)  0@3344r
%vreg224 [3488r,3552r:0)  0@3488r
%vreg227 [3472r,3488r:0)  0@3472r
%vreg229 [3456r,3536r:0)  0@3456r
%vreg230 [3440r,3456r:0)  0@3440r
%vreg232 [3424r,3568r:0)  0@3424r
%vreg233 [3408r,3424r:0)  0@3408r
%vreg236 [3664r,3680r:0)  0@3664r
%vreg241 [3808r,3872r:0)  0@3808r
%vreg244 [3792r,3808r:0)  0@3792r
%vreg246 [3776r,3856r:0)  0@3776r
%vreg247 [3760r,3776r:0)  0@3760r
%vreg249 [3744r,3888r:0)  0@3744r
%vreg250 [3728r,3744r:0)  0@3728r
%vreg256 [4096r,4160r:0)  0@4096r
%vreg259 [4080r,4144r:0)  0@4080r
%vreg260 [4064r,4080r:0)  0@4064r
%vreg262 [4048r,4176r:0)  0@4048r
%vreg263 [4032r,4048r:0)  0@4032r
%vreg265 [5584r,5600r:0)  0@5584r
%vreg267 [5408r,5472r:0)  0@5408r
%vreg268 [5440r,5488r:0)  0@5440r
RegMasks: 240r 400r 1376r 1984r 2384r 2688r 3248r 3568r 3888r 4176r 5168r 5296r 5504r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzCompressInit: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=4, align=4, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=4, align=4, at location [SP+8]
  fi#3: size=4, align=4, at location [SP+8]
  fi#4: size=4, align=4, at location [SP+8]
  fi#5: size=4, align=4, at location [SP+8]
  fi#6: size=8, align=8, at location [SP+8]
Function Live Ins: %RDI in %vreg0, %ESI in %vreg2, %EDX in %vreg4, %ECX in %vreg6

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI %ESI %EDX %ECX
16B		%vreg7<def> = COPY %ECX; GR32:%vreg7
32B		%vreg5<def> = COPY %EDX; GR32:%vreg5
48B		%vreg3<def> = COPY %ESI; GR32:%vreg3
64B		%vreg1<def> = COPY %RDI; GR64:%vreg1
144B		%vreg11<def> = MOV64ri <ga:@BZ2_bzCompressInit>; GR64:%vreg11
176B		%vreg12<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg12
192B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
208B		%RDI<def> = COPY %vreg11; GR64:%vreg11
224B		%RSI<def> = COPY %vreg12; GR64:%vreg12
240B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
256B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
272B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
288B		STACKMAP 0, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, %vreg1, 0, <fi#1>, 0, %vreg5, 0, <fi#3>, 0, %vreg7, 0, <fi#4>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4) GR32:%vreg3,%vreg5,%vreg7 GR64:%vreg1
304B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
320B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%strm.addr] GR64:%vreg1
336B		MOV32mr <fi#2>, 1, %noreg, 0, %noreg, %vreg3; mem:ST4[%blockSize100k.addr] GR32:%vreg3
352B		MOV32mr <fi#3>, 1, %noreg, 0, %noreg, %vreg5; mem:ST4[%verbosity.addr] GR32:%vreg5
368B		MOV32mr <fi#4>, 1, %noreg, 0, %noreg, %vreg7; mem:ST4[%workFactor.addr] GR32:%vreg7
384B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
400B		CALL64pcrel32 <ga:@bz_config_ok>, <regmask>, %RSP<imp-use>, %EAX<imp-def>
416B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
432B		%vreg9<def> = COPY %EAX<kill>; GR32:%vreg9
448B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
464B		STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)
480B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
496B		CMP32ri8 %vreg9, 0, %EFLAGS<imp-def>; GR32:%vreg9
512B		JNE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

528B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
544B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -9; mem:ST4[%retval]
560B		JMP_1 <BB#29>
	    Successors according to CFG: BB#29

576B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0
592B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%strm.addr]
608B		JE_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#3

624B	BB#3: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#2
640B		CMP32mi8 <fi#2>, 1, %noreg, 0, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%blockSize100k.addr]
656B		JL_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#4

672B	BB#4: derived from LLVM BB %lor.lhs.false.2
	    Predecessors according to CFG: BB#3
688B		CMP32mi8 <fi#2>, 1, %noreg, 0, %noreg, 9, %EFLAGS<imp-def>; mem:LD4[%blockSize100k.addr]
704B		JG_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#5

720B	BB#5: derived from LLVM BB %lor.lhs.false.4
	    Predecessors according to CFG: BB#4
736B		CMP32mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%workFactor.addr]
752B		JL_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#6

768B	BB#6: derived from LLVM BB %lor.lhs.false.6
	    Predecessors according to CFG: BB#5
784B		CMP32mi <fi#4>, 1, %noreg, 0, %noreg, 250, %EFLAGS<imp-def>; mem:LD4[%workFactor.addr]
800B		JLE_1 <BB#8>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#8 BB#7

816B	BB#7: derived from LLVM BB %if.then.8
	    Predecessors according to CFG: BB#2 BB#3 BB#4 BB#5 BB#6
832B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
848B		JMP_1 <BB#29>
	    Successors according to CFG: BB#29

864B	BB#8: derived from LLVM BB %if.end.9
	    Predecessors according to CFG: BB#6
880B		CMP32mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%workFactor.addr]
896B		JNE_1 <BB#10>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#10 BB#9

912B	BB#9: derived from LLVM BB %if.then.11
	    Predecessors according to CFG: BB#8
928B		MOV32mi <fi#4>, 1, %noreg, 0, %noreg, 30; mem:ST4[%workFactor.addr]
	    Successors according to CFG: BB#10

944B	BB#10: derived from LLVM BB %if.end.12
	    Predecessors according to CFG: BB#8 BB#9
960B		%vreg21<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg21
976B		CMP64mi8 %vreg21, 1, %noreg, 56, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzalloc] GR64:%vreg21
992B		JNE_1 <BB#12>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#12 BB#11

1008B	BB#11: derived from LLVM BB %if.then.14
	    Predecessors according to CFG: BB#10
1024B		%vreg23<def> = MOV64ri <ga:@default_bzalloc>; GR64:%vreg23
1040B		%vreg24<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg24
1056B		MOV64mr %vreg24, 1, %noreg, 56, %noreg, %vreg23; mem:ST8[%bzalloc15] GR64:%vreg24,%vreg23
	    Successors according to CFG: BB#12

1072B	BB#12: derived from LLVM BB %if.end.16
	    Predecessors according to CFG: BB#10 BB#11
1088B		%vreg27<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg27
1104B		CMP64mi8 %vreg27, 1, %noreg, 64, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzfree] GR64:%vreg27
1120B		JNE_1 <BB#14>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#14 BB#13

1136B	BB#13: derived from LLVM BB %if.then.18
	    Predecessors according to CFG: BB#12
1152B		%vreg29<def> = MOV64ri <ga:@default_bzfree>; GR64:%vreg29
1168B		%vreg30<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg30
1184B		MOV64mr %vreg30, 1, %noreg, 64, %noreg, %vreg29; mem:ST8[%bzfree19] GR64:%vreg30,%vreg29
	    Successors according to CFG: BB#14

1200B	BB#14: derived from LLVM BB %if.end.20
	    Predecessors according to CFG: BB#12 BB#13
1248B		%vreg45<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg45
1264B		%vreg44<def> = MOV64rm %vreg45, 1, %noreg, 56, %noreg; mem:LD8[%bzalloc21] GR64:%vreg44,%vreg45
1280B		%vreg42<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg42
1296B		%vreg41<def> = MOV64rm %vreg42, 1, %noreg, 72, %noreg; mem:LD8[%opaque] GR64:%vreg41,%vreg42
1312B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1328B		%RDI<def> = COPY %vreg41; GR64:%vreg41
1344B		%ESI<def> = MOV32ri 55768
1360B		%EDX<def> = MOV32ri 1
1376B		CALL64r %vreg44, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %EDX<imp-use>, %RAX<imp-def>; GR64:%vreg44
1392B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1408B		%vreg34<def> = COPY %RAX<kill>; GR64:%vreg34
1424B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1440B		STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)
1456B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1488B		MOV64mr <fi#6>, 1, %noreg, 0, %noreg, %vreg34; mem:ST8[%s] GR64:%vreg34
1504B		CMP64mi8 <fi#6>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%s]
1520B		JNE_1 <BB#16>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#16 BB#15

1536B	BB#15: derived from LLVM BB %if.then.24
	    Predecessors according to CFG: BB#14
1552B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -3; mem:ST4[%retval]
1568B		JMP_1 <BB#29>
	    Successors according to CFG: BB#29

1584B	BB#16: derived from LLVM BB %if.end.25
	    Predecessors according to CFG: BB#14
1616B		%vreg124<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg124
1632B		%vreg123<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg123
1648B		MOV64mr %vreg123, 1, %noreg, 0, %noreg, %vreg124; mem:ST8[%strm26] GR64:%vreg123,%vreg124
1664B		%vreg120<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg120
1680B		MOV64mi32 %vreg120, 1, %noreg, 24, %noreg, 0; mem:ST8[%arr1] GR64:%vreg120
1696B		%vreg118<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg118
1712B		MOV64mi32 %vreg118, 1, %noreg, 32, %noreg, 0; mem:ST8[%arr2] GR64:%vreg118
1728B		%vreg116<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg116
1744B		MOV64mi32 %vreg116, 1, %noreg, 40, %noreg, 0; mem:ST8[%ftab] GR64:%vreg116
1760B		%vreg114<def> = IMUL32rmi <fi#2>, 1, %noreg, 0, %noreg, 100000, %EFLAGS<imp-def,dead>; mem:LD4[%blockSize100k.addr] GR32:%vreg114
1776B		MOV32mr <fi#5>, 1, %noreg, 0, %noreg, %vreg114; mem:ST4[%n] GR32:%vreg114
1792B		%vreg111<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg111
1808B		%vreg110<def> = MOV64rm %vreg111, 1, %noreg, 56, %noreg; mem:LD8[%bzalloc27] GR64:%vreg110,%vreg111
1824B		%vreg108<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg108
1840B		%vreg107<def> = MOV64rm %vreg108, 1, %noreg, 72, %noreg; mem:LD8[%opaque28] GR64:%vreg107,%vreg108
1856B		%vreg103<def> = MOVSX64rm32 <fi#5>, 1, %noreg, 0, %noreg; mem:LD4[%n] GR64_with_sub_8bit:%vreg103
1888B		%vreg103<def,tied1> = SHL64ri %vreg103<tied0>, 2, %EFLAGS<imp-def,dead>; GR64_with_sub_8bit:%vreg103
1920B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1936B		%RDI<def> = COPY %vreg107; GR64:%vreg107
1952B		%ESI<def> = COPY %vreg103:sub_32bit; GR64_with_sub_8bit:%vreg103
1968B		%EDX<def> = MOV32ri 1
1984B		CALL64r %vreg110, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %EDX<imp-use>, %RAX<imp-def>; GR64:%vreg110
2000B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2016B		%vreg94<def> = COPY %RAX<kill>; GR64:%vreg94
2048B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2064B		STACKMAP 3, 0, 0, <fi#2>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)
2080B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2112B		%vreg92<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg92
2128B		MOV64mr %vreg92, 1, %noreg, 24, %noreg, %vreg94; mem:ST8[%arr132] GR64:%vreg92,%vreg94
2144B		%vreg89<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg89
2160B		%vreg88<def> = MOV64rm %vreg89, 1, %noreg, 56, %noreg; mem:LD8[%bzalloc33] GR64:%vreg88,%vreg89
2176B		%vreg86<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg86
2192B		%vreg85<def> = MOV64rm %vreg86, 1, %noreg, 72, %noreg; mem:LD8[%opaque34] GR64:%vreg85,%vreg86
2208B		%vreg82<def> = MOV32rm <fi#5>, 1, %noreg, 0, %noreg; mem:LD4[%n] GR32:%vreg82
2240B		%vreg82<def,tied1> = ADD32ri8 %vreg82<tied0>, 34, %EFLAGS<imp-def,dead>; GR32:%vreg82
2256B		%vreg78<def> = MOVSX64rr32 %vreg82; GR64_with_sub_8bit:%vreg78 GR32:%vreg82
2288B		%vreg78<def,tied1> = SHL64ri %vreg78<tied0>, 2, %EFLAGS<imp-def,dead>; GR64_with_sub_8bit:%vreg78
2320B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2336B		%RDI<def> = COPY %vreg85; GR64:%vreg85
2352B		%ESI<def> = COPY %vreg78:sub_32bit; GR64_with_sub_8bit:%vreg78
2368B		%EDX<def> = MOV32ri 1
2384B		CALL64r %vreg88, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %EDX<imp-use>, %RAX<imp-def>; GR64:%vreg88
2400B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2416B		%vreg69<def> = COPY %RAX<kill>; GR64:%vreg69
2464B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2480B		STACKMAP 4, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)
2496B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2528B		%vreg67<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg67
2544B		MOV64mr %vreg67, 1, %noreg, 32, %noreg, %vreg69; mem:ST8[%arr239] GR64:%vreg67,%vreg69
2560B		%vreg64<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg64
2576B		%vreg63<def> = MOV64rm %vreg64, 1, %noreg, 56, %noreg; mem:LD8[%bzalloc40] GR64:%vreg63,%vreg64
2592B		%vreg61<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg61
2608B		%vreg60<def> = MOV64rm %vreg61, 1, %noreg, 72, %noreg; mem:LD8[%opaque41] GR64:%vreg60,%vreg61
2624B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2640B		%RDI<def> = COPY %vreg60; GR64:%vreg60
2656B		%ESI<def> = MOV32ri 262148
2672B		%EDX<def> = MOV32ri 1
2688B		CALL64r %vreg63, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %EDX<imp-use>, %RAX<imp-def>; GR64:%vreg63
2704B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2720B		%vreg53<def> = COPY %RAX<kill>; GR64:%vreg53
2736B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2752B		STACKMAP 5, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)
2768B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2800B		%vreg51<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg51
2816B		MOV64mr %vreg51, 1, %noreg, 40, %noreg, %vreg53; mem:ST8[%ftab43] GR64:%vreg51,%vreg53
2832B		%vreg48<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg48
2848B		CMP64mi8 %vreg48, 1, %noreg, 24, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%arr144] GR64:%vreg48
2864B		JE_1 <BB#19>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#19 BB#17

2880B	BB#17: derived from LLVM BB %lor.lhs.false.47
	    Predecessors according to CFG: BB#16
2896B		%vreg127<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg127
2912B		CMP64mi8 %vreg127, 1, %noreg, 32, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%arr248] GR64:%vreg127
2928B		JE_1 <BB#19>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#19 BB#18

2944B	BB#18: derived from LLVM BB %lor.lhs.false.51
	    Predecessors according to CFG: BB#17
2960B		%vreg130<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg130
2976B		CMP64mi8 %vreg130, 1, %noreg, 40, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%ftab52] GR64:%vreg130
2992B		JNE_1 <BB#28>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#28 BB#19

3008B	BB#19: derived from LLVM BB %if.then.55
	    Predecessors according to CFG: BB#16 BB#17 BB#18
3024B		%vreg202<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg202
3040B		CMP64mi8 %vreg202, 1, %noreg, 24, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%arr156] GR64:%vreg202
3056B		JE_1 <BB#21>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#21 BB#20

3072B	BB#20: derived from LLVM BB %if.then.59
	    Predecessors according to CFG: BB#19
3088B		%vreg216<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg216
3104B		%vreg215<def> = MOV64rm %vreg216, 1, %noreg, 64, %noreg; mem:LD8[%bzfree60] GR64:%vreg215,%vreg216
3120B		%vreg213<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg213
3136B		%vreg212<def> = MOV64rm %vreg213, 1, %noreg, 72, %noreg; mem:LD8[%opaque61] GR64:%vreg212,%vreg213
3152B		%vreg210<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg210
3168B		%vreg207<def> = MOV64rm %vreg210, 1, %noreg, 24, %noreg; mem:LD8[%arr162] GR64:%vreg207,%vreg210
3200B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3216B		%RDI<def> = COPY %vreg212; GR64:%vreg212
3232B		%RSI<def> = COPY %vreg207; GR64:%vreg207
3248B		CALL64r %vreg215, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>; GR64:%vreg215
3264B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3280B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3296B		STACKMAP 6, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1]
3312B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#21

3328B	BB#21: derived from LLVM BB %if.end.63
	    Predecessors according to CFG: BB#19 BB#20
3344B		%vreg219<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg219
3360B		CMP64mi8 %vreg219, 1, %noreg, 32, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%arr264] GR64:%vreg219
3376B		JE_1 <BB#23>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#23 BB#22

3392B	BB#22: derived from LLVM BB %if.then.67
	    Predecessors according to CFG: BB#21
3408B		%vreg233<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg233
3424B		%vreg232<def> = MOV64rm %vreg233, 1, %noreg, 64, %noreg; mem:LD8[%bzfree68] GR64:%vreg232,%vreg233
3440B		%vreg230<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg230
3456B		%vreg229<def> = MOV64rm %vreg230, 1, %noreg, 72, %noreg; mem:LD8[%opaque69] GR64:%vreg229,%vreg230
3472B		%vreg227<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg227
3488B		%vreg224<def> = MOV64rm %vreg227, 1, %noreg, 32, %noreg; mem:LD8[%arr270] GR64:%vreg224,%vreg227
3520B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3536B		%RDI<def> = COPY %vreg229; GR64:%vreg229
3552B		%RSI<def> = COPY %vreg224; GR64:%vreg224
3568B		CALL64r %vreg232, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>; GR64:%vreg232
3584B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3600B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3616B		STACKMAP 7, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1]
3632B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#23

3648B	BB#23: derived from LLVM BB %if.end.71
	    Predecessors according to CFG: BB#21 BB#22
3664B		%vreg236<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg236
3680B		CMP64mi8 %vreg236, 1, %noreg, 40, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%ftab72] GR64:%vreg236
3696B		JE_1 <BB#25>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#25 BB#24

3712B	BB#24: derived from LLVM BB %if.then.75
	    Predecessors according to CFG: BB#23
3728B		%vreg250<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg250
3744B		%vreg249<def> = MOV64rm %vreg250, 1, %noreg, 64, %noreg; mem:LD8[%bzfree76] GR64:%vreg249,%vreg250
3760B		%vreg247<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg247
3776B		%vreg246<def> = MOV64rm %vreg247, 1, %noreg, 72, %noreg; mem:LD8[%opaque77] GR64:%vreg246,%vreg247
3792B		%vreg244<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg244
3808B		%vreg241<def> = MOV64rm %vreg244, 1, %noreg, 40, %noreg; mem:LD8[%ftab78] GR64:%vreg241,%vreg244
3840B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3856B		%RDI<def> = COPY %vreg246; GR64:%vreg246
3872B		%RSI<def> = COPY %vreg241; GR64:%vreg241
3888B		CALL64r %vreg249, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>; GR64:%vreg249
3904B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3920B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3936B		STACKMAP 8, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1]
3952B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#25

3968B	BB#25: derived from LLVM BB %if.end.79
	    Predecessors according to CFG: BB#23 BB#24
3984B		CMP64mi8 <fi#6>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%s]
4000B		JE_1 <BB#27>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#27 BB#26

4016B	BB#26: derived from LLVM BB %if.then.82
	    Predecessors according to CFG: BB#25
4032B		%vreg263<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg263
4048B		%vreg262<def> = MOV64rm %vreg263, 1, %noreg, 64, %noreg; mem:LD8[%bzfree83] GR64:%vreg262,%vreg263
4064B		%vreg260<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg260
4080B		%vreg259<def> = MOV64rm %vreg260, 1, %noreg, 72, %noreg; mem:LD8[%opaque84] GR64:%vreg259,%vreg260
4096B		%vreg256<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg256
4128B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4144B		%RDI<def> = COPY %vreg259; GR64:%vreg259
4160B		%RSI<def> = COPY %vreg256; GR64:%vreg256
4176B		CALL64r %vreg262, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>; GR64:%vreg262
4192B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4208B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4224B		STACKMAP 9, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
4240B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#27

4256B	BB#27: derived from LLVM BB %if.end.85
	    Predecessors according to CFG: BB#25 BB#26
4272B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -3; mem:ST4[%retval]
4288B		JMP_1 <BB#29>
	    Successors according to CFG: BB#29

4304B	BB#28: derived from LLVM BB %if.end.86
	    Predecessors according to CFG: BB#18
4320B		%vreg199<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg199
4336B		MOV32mi %vreg199, 1, %noreg, 660, %noreg, 0; mem:ST4[%blockNo] GR64:%vreg199
4352B		%vreg197<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg197
4368B		MOV32mi %vreg197, 1, %noreg, 12, %noreg, 2; mem:ST4[%state] GR64:%vreg197
4384B		%vreg195<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg195
4400B		MOV32mi %vreg195, 1, %noreg, 8, %noreg, 2; mem:ST4[%mode] GR64:%vreg195
4416B		%vreg193<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg193
4432B		MOV32mi %vreg193, 1, %noreg, 652, %noreg, 0; mem:ST4[%combinedCRC] GR64:%vreg193
4448B		%vreg191<def> = MOV32rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD4[%blockSize100k.addr] GR32:%vreg191
4464B		%vreg190<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg190
4480B		MOV32mr %vreg190, 1, %noreg, 664, %noreg, %vreg191; mem:ST4[%blockSize100k87] GR64:%vreg190 GR32:%vreg191
4496B		%vreg185<def> = IMUL32rmi <fi#2>, 1, %noreg, 0, %noreg, 100000, %EFLAGS<imp-def,dead>; mem:LD4[%blockSize100k.addr] GR32:%vreg185
4528B		%vreg185<def,tied1> = SUB32ri8 %vreg185<tied0>, 19, %EFLAGS<imp-def,dead>; GR32:%vreg185
4544B		%vreg183<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg183
4560B		MOV32mr %vreg183, 1, %noreg, 112, %noreg, %vreg185; mem:ST4[%nblockMAX] GR64:%vreg183 GR32:%vreg185
4576B		%vreg180<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%verbosity.addr] GR32:%vreg180
4592B		%vreg179<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg179
4608B		MOV32mr %vreg179, 1, %noreg, 656, %noreg, %vreg180; mem:ST4[%verbosity89] GR64:%vreg179 GR32:%vreg180
4624B		%vreg176<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%workFactor.addr] GR32:%vreg176
4640B		%vreg175<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg175
4656B		MOV32mr %vreg175, 1, %noreg, 88, %noreg, %vreg176; mem:ST4[%workFactor90] GR64:%vreg175 GR32:%vreg176
4672B		%vreg172<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg172
4688B		%vreg169<def> = MOV64rm %vreg172, 1, %noreg, 32, %noreg; mem:LD8[%arr291] GR64:%vreg169,%vreg172
4720B		%vreg167<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg167
4736B		MOV64mr %vreg167, 1, %noreg, 64, %noreg, %vreg169; mem:ST8[%block] GR64:%vreg167,%vreg169
4752B		%vreg164<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg164
4768B		%vreg161<def> = MOV64rm %vreg164, 1, %noreg, 24, %noreg; mem:LD8[%arr192] GR64:%vreg161,%vreg164
4800B		%vreg159<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg159
4816B		MOV64mr %vreg159, 1, %noreg, 72, %noreg, %vreg161; mem:ST8[%mtfv] GR64:%vreg159,%vreg161
4832B		%vreg156<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg156
4848B		MOV64mi32 %vreg156, 1, %noreg, 80, %noreg, 0; mem:ST8[%zbits] GR64:%vreg156
4864B		%vreg154<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg154
4880B		%vreg153<def> = MOV64rm %vreg154, 1, %noreg, 24, %noreg; mem:LD8[%arr193] GR64:%vreg153,%vreg154
4896B		%vreg151<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg151
4912B		MOV64mr %vreg151, 1, %noreg, 56, %noreg, %vreg153; mem:ST8[%ptr] GR64:%vreg151,%vreg153
4928B		%vreg147<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg147
4960B		%vreg145<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg145
4976B		MOV64mr %vreg145, 1, %noreg, 48, %noreg, %vreg147; mem:ST8[%state94] GR64:%vreg145,%vreg147
4992B		%vreg142<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg142
5008B		MOV32mi %vreg142, 1, %noreg, 12, %noreg, 0; mem:ST4[%total_in_lo32] GR64:%vreg142
5024B		%vreg140<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg140
5040B		MOV32mi %vreg140, 1, %noreg, 16, %noreg, 0; mem:ST4[%total_in_hi32] GR64:%vreg140
5056B		%vreg138<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg138
5072B		MOV32mi %vreg138, 1, %noreg, 36, %noreg, 0; mem:ST4[%total_out_lo32] GR64:%vreg138
5088B		%vreg136<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg136
5104B		MOV32mi %vreg136, 1, %noreg, 40, %noreg, 0; mem:ST4[%total_out_hi32] GR64:%vreg136
5120B		%vreg134<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg134
5136B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5152B		%RDI<def> = COPY %vreg134; GR64:%vreg134
5168B		CALL64pcrel32 <ga:@init_RL>, <regmask>, %RSP<imp-use>, %RDI<imp-use>
5184B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5200B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5216B		STACKMAP 10, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack6]
5232B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5248B		%vreg132<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg132
5264B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5280B		%RDI<def> = COPY %vreg132; GR64:%vreg132
5296B		CALL64pcrel32 <ga:@prepare_new_block>, <regmask>, %RSP<imp-use>, %RDI<imp-use>
5312B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5328B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5344B		STACKMAP 11, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
5360B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5376B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
	    Successors according to CFG: BB#29

5392B	BB#29: derived from LLVM BB %return
	    Predecessors according to CFG: BB#1 BB#28 BB#27 BB#15 BB#7
5408B		%vreg267<def> = MOV64ri <ga:@BZ2_bzCompressInit>; GR64:%vreg267
5440B		%vreg268<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg268
5456B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5472B		%RDI<def> = COPY %vreg267; GR64:%vreg267
5488B		%RSI<def> = COPY %vreg268; GR64:%vreg268
5504B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
5520B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5536B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5552B		STACKMAP 12, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
5568B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5584B		%vreg265<def> = MOV32rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD4[%retval] GR32:%vreg265
5600B		%EAX<def> = COPY %vreg265; GR32:%vreg265
5616B		RETQ %EAX<imp-use,kill>

# End machine code for function BZ2_bzCompressInit.

handleMove 1328B -> 1368B: %RDI<def> = COPY %vreg41; GR64:%vreg41
     DIL:	[0B,64r:0)[208r,240r:12)[1328r,1376r:11)[1936r,1984r:8)[2336r,2384r:9)[2640r,2688r:10)[3216r,3248r:5)[3536r,3568r:4)[3856r,3888r:3)[4144r,4176r:2)[5152r,5168r:6)[5280r,5296r:7)[5472r,5504r:1)  0@0B-phi 1@5472r 2@4144r 3@3856r 4@3536r 5@3216r 6@5152r 7@5280r 8@1936r 9@2336r 10@2640r 11@1328r 12@208r
        -->	[0B,64r:0)[208r,240r:12)[1368r,1376r:11)[1936r,1984r:8)[2336r,2384r:9)[2640r,2688r:10)[3216r,3248r:5)[3536r,3568r:4)[3856r,3888r:3)[4144r,4176r:2)[5152r,5168r:6)[5280r,5296r:7)[5472r,5504r:1)  0@0B-phi 1@5472r 2@4144r 3@3856r 4@3536r 5@3216r 6@5152r 7@5280r 8@1936r 9@2336r 10@2640r 11@1368r 12@208r
     %vreg41:	[1296r,1328r:0)  0@1296r
        -->	[1296r,1368r:0)  0@1296r
handleMove 2640B -> 2680B: %RDI<def> = COPY %vreg60; GR64:%vreg60
     DIL:	[0B,64r:0)[208r,240r:12)[1368r,1376r:11)[1936r,1984r:8)[2336r,2384r:9)[2640r,2688r:10)[3216r,3248r:5)[3536r,3568r:4)[3856r,3888r:3)[4144r,4176r:2)[5152r,5168r:6)[5280r,5296r:7)[5472r,5504r:1)  0@0B-phi 1@5472r 2@4144r 3@3856r 4@3536r 5@3216r 6@5152r 7@5280r 8@1936r 9@2336r 10@2640r 11@1368r 12@208r
        -->	[0B,64r:0)[208r,240r:12)[1368r,1376r:11)[1936r,1984r:8)[2336r,2384r:9)[2680r,2688r:10)[3216r,3248r:5)[3536r,3568r:4)[3856r,3888r:3)[4144r,4176r:2)[5152r,5168r:6)[5280r,5296r:7)[5472r,5504r:1)  0@0B-phi 1@5472r 2@4144r 3@3856r 4@3536r 5@3216r 6@5152r 7@5280r 8@1936r 9@2336r 10@2680r 11@1368r 12@208r
     %vreg60:	[2608r,2640r:0)  0@2608r
        -->	[2608r,2680r:0)  0@2608r
handleMove 2352B -> 2376B: %ESI<def> = COPY %vreg78:sub_32bit; GR64_with_sub_8bit:%vreg78
     SIL:	[0B,48r:0)[224r,240r:10)[1344r,1376r:4)[1952r,1984r:1)[2352r,2384r:2)[2656r,2688r:3)[3232r,3248r:9)[3552r,3568r:8)[3872r,3888r:7)[4160r,4176r:6)[5488r,5504r:5)  0@0B-phi 1@1952r 2@2352r 3@2656r 4@1344r 5@5488r 6@4160r 7@3872r 8@3552r 9@3232r 10@224r
        -->	[0B,48r:0)[224r,240r:10)[1344r,1376r:4)[1952r,1984r:1)[2376r,2384r:2)[2656r,2688r:3)[3232r,3248r:9)[3552r,3568r:8)[3872r,3888r:7)[4160r,4176r:6)[5488r,5504r:5)  0@0B-phi 1@1952r 2@2376r 3@2656r 4@1344r 5@5488r 6@4160r 7@3872r 8@3552r 9@3232r 10@224r
     %vreg78:	[2256r,2288r:0)[2288r,2352r:1)  0@2256r 1@2288r
        -->	[2256r,2288r:0)[2288r,2376r:1)  0@2256r 1@2288r
handleMove 2336B -> 2372B: %RDI<def> = COPY %vreg85; GR64:%vreg85
     DIL:	[0B,64r:0)[208r,240r:12)[1368r,1376r:11)[1936r,1984r:8)[2336r,2384r:9)[2680r,2688r:10)[3216r,3248r:5)[3536r,3568r:4)[3856r,3888r:3)[4144r,4176r:2)[5152r,5168r:6)[5280r,5296r:7)[5472r,5504r:1)  0@0B-phi 1@5472r 2@4144r 3@3856r 4@3536r 5@3216r 6@5152r 7@5280r 8@1936r 9@2336r 10@2680r 11@1368r 12@208r
        -->	[0B,64r:0)[208r,240r:12)[1368r,1376r:11)[1936r,1984r:8)[2372r,2384r:9)[2680r,2688r:10)[3216r,3248r:5)[3536r,3568r:4)[3856r,3888r:3)[4144r,4176r:2)[5152r,5168r:6)[5280r,5296r:7)[5472r,5504r:1)  0@0B-phi 1@5472r 2@4144r 3@3856r 4@3536r 5@3216r 6@5152r 7@5280r 8@1936r 9@2372r 10@2680r 11@1368r 12@208r
     %vreg85:	[2192r,2336r:0)  0@2192r
        -->	[2192r,2372r:0)  0@2192r
AllocationOrder(GR8_ABCD_H) = [ %AH %CH %DH %BH ] (sub-class)
AllocationOrder(GR8_ABCD_L) = [ %AL %CL %DL %BL ] (sub-class)
AllocationOrder(BNDR) = [ %BND0 %BND1 %BND2 %BND3 ]
AllocationOrder(SEGMENT_REG) = [ ]
AllocationOrder(RFP32) = [ %FP0 %FP1 %FP2 %FP3 %FP4 %FP5 %FP6 ]
AllocationOrder(GR8_NOREX) = [ %AL %CL %DL %BL ]
AllocationOrder(VK1) = [ %K0 %K1 %K2 %K3 %K4 %K5 %K6 %K7 ]
AllocationOrder(DEBUG_REG) = [ %DR0 %DR1 %DR2 %DR3 %DR4 %DR5 %DR6 %DR7 ]
AllocationOrder(VR64) = [ %MM0 %MM1 %MM2 %MM3 %MM4 %MM5 %MM6 %MM7 ]
AllocationOrder(GR64) = [ %RAX %RCX %RDX %RSI %RDI %R8 %R9 %R10 %R11 %RBX %R14 %R15 %R12 %R13 ]
AllocationOrder(GR64_NOREX_and_GR64_TC) = [ %RAX %RCX %RDX %RSI %RDI ] (sub-class)
AllocationOrder(GR64_TCW64) = [ %RAX %RCX %RDX %R8 %R9 %R11 ] (sub-class)
AllocationOrder(FR32) = [ %XMM0 %XMM1 %XMM2 %XMM3 %XMM4 %XMM5 %XMM6 %XMM7 %XMM8 %XMM9 %XMM10 %XMM11 %XMM12 %XMM13 %XMM14 %XMM15 ]
AllocationOrder(CONTROL_REG) = [ %CR0 %CR1 %CR2 %CR3 %CR4 %CR5 %CR6 %CR7 %CR8 %CR9 %CR10 %CR11 %CR12 %CR13 %CR14 %CR15 ]
AllocationOrder(GR64_NOREX) = [ %RAX %RCX %RDX %RSI %RDI %RBX ] (sub-class)
AllocationOrder(GR8) = [ %AL %CL %DL %SIL %DIL %R8B %R9B %R10B %R11B %BL %R14B %R15B %R12B %R13B ]
AllocationOrder(GR64_TC) = [ %RAX %RCX %RDX %RSI %RDI %R8 %R9 %R11 ] (sub-class)
AllocationOrder(GR8) = [ %AL %CL %DL %SIL %DIL %R8B %R9B %R10B %R11B %BL %R14B %R15B %R12B %R13B ]
AllocationOrder(GR64_NOREX) = [ %RAX %RCX %RDX %RSI %RDI %RBX ] (sub-class)
AllocationOrder(GR8) = [ %AL %CL %DL %SIL %DIL %R8B %R9B %R10B %R11B %BL %R14B %R15B %R12B %R13B ]
AllocationOrder(GR8) = [ %AL %CL %DL %SIL %DIL %R8B %R9B %R10B %R11B %BL %R14B %R15B %R12B %R13B ]
AllocationOrder(FR32X) = [ %XMM0 %XMM1 %XMM2 %XMM3 %XMM4 %XMM5 %XMM6 %XMM7 %XMM8 %XMM9 %XMM10 %XMM11 %XMM12 %XMM13 %XMM14 %XMM15 ]
AllocationOrder(GR64) = [ %RAX %RCX %RDX %RSI %RDI %R8 %R9 %R10 %R11 %RBX %R14 %R15 %R12 %R13 ]
handleMove 1952B -> 1976B: %ESI<def> = COPY %vreg103:sub_32bit; GR64_with_sub_8bit:%vreg103
     SIL:	[0B,48r:0)[224r,240r:10)[1344r,1376r:4)[1952r,1984r:1)[2376r,2384r:2)[2656r,2688r:3)[3232r,3248r:9)[3552r,3568r:8)[3872r,3888r:7)[4160r,4176r:6)[5488r,5504r:5)  0@0B-phi 1@1952r 2@2376r 3@2656r 4@1344r 5@5488r 6@4160r 7@3872r 8@3552r 9@3232r 10@224r
        -->	[0B,48r:0)[224r,240r:10)[1344r,1376r:4)[1976r,1984r:1)[2376r,2384r:2)[2656r,2688r:3)[3232r,3248r:9)[3552r,3568r:8)[3872r,3888r:7)[4160r,4176r:6)[5488r,5504r:5)  0@0B-phi 1@1976r 2@2376r 3@2656r 4@1344r 5@5488r 6@4160r 7@3872r 8@3552r 9@3232r 10@224r
     %vreg103:	[1856r,1888r:0)[1888r,1952r:1)  0@1856r 1@1888r
        -->	[1856r,1888r:0)[1888r,1976r:1)  0@1856r 1@1888r
handleMove 1936B -> 1972B: %RDI<def> = COPY %vreg107; GR64:%vreg107
     DIL:	[0B,64r:0)[208r,240r:12)[1368r,1376r:11)[1936r,1984r:8)[2372r,2384r:9)[2680r,2688r:10)[3216r,3248r:5)[3536r,3568r:4)[3856r,3888r:3)[4144r,4176r:2)[5152r,5168r:6)[5280r,5296r:7)[5472r,5504r:1)  0@0B-phi 1@5472r 2@4144r 3@3856r 4@3536r 5@3216r 6@5152r 7@5280r 8@1936r 9@2372r 10@2680r 11@1368r 12@208r
        -->	[0B,64r:0)[208r,240r:12)[1368r,1376r:11)[1972r,1984r:8)[2372r,2384r:9)[2680r,2688r:10)[3216r,3248r:5)[3536r,3568r:4)[3856r,3888r:3)[4144r,4176r:2)[5152r,5168r:6)[5280r,5296r:7)[5472r,5504r:1)  0@0B-phi 1@5472r 2@4144r 3@3856r 4@3536r 5@3216r 6@5152r 7@5280r 8@1972r 9@2372r 10@2680r 11@1368r 12@208r
     %vreg107:	[1840r,1936r:0)  0@1840r
        -->	[1840r,1972r:0)  0@1840r
AllocationOrder(SEGMENT_REG) = [ ]
AllocationOrder(SEGMENT_REG) = [ ]
********** GREEDY REGISTER ALLOCATION **********
********** Function: BZ2_bzCompressInit
********** INTERVALS **********
CH [0B,16r:0)  0@0B-phi
CL [0B,16r:0)  0@0B-phi
DH [0B,32r:0)[1360r,1376r:4)[1968r,1984r:1)[2368r,2384r:2)[2672r,2688r:3)  0@0B-phi 1@1968r 2@2368r 3@2672r 4@1360r
DIL [0B,64r:0)[208r,240r:12)[1368r,1376r:11)[1972r,1984r:8)[2372r,2384r:9)[2680r,2688r:10)[3216r,3248r:5)[3536r,3568r:4)[3856r,3888r:3)[4144r,4176r:2)[5152r,5168r:6)[5280r,5296r:7)[5472r,5504r:1)  0@0B-phi 1@5472r 2@4144r 3@3856r 4@3536r 5@3216r 6@5152r 7@5280r 8@1972r 9@2372r 10@2680r 11@1368r 12@208r
DL [0B,32r:0)[1360r,1376r:4)[1968r,1984r:1)[2368r,2384r:2)[2672r,2688r:3)  0@0B-phi 1@1968r 2@2368r 3@2672r 4@1360r
SIL [0B,48r:0)[224r,240r:10)[1344r,1376r:4)[1976r,1984r:1)[2376r,2384r:2)[2656r,2688r:3)[3232r,3248r:9)[3552r,3568r:8)[3872r,3888r:7)[4160r,4176r:6)[5488r,5504r:5)  0@0B-phi 1@1976r 2@2376r 3@2656r 4@1344r 5@5488r 6@4160r 7@3872r 8@3552r 9@3232r 10@224r
%vreg1 [64r,320r:0)  0@64r
%vreg3 [48r,336r:0)  0@48r
%vreg5 [32r,352r:0)  0@32r
%vreg7 [16r,368r:0)  0@16r
%vreg9 [432r,496r:0)  0@432r
%vreg11 [144r,208r:0)  0@144r
%vreg12 [176r,224r:0)  0@176r
%vreg21 [960r,976r:0)  0@960r
%vreg23 [1024r,1056r:0)  0@1024r
%vreg24 [1040r,1056r:0)  0@1040r
%vreg27 [1088r,1104r:0)  0@1088r
%vreg29 [1152r,1184r:0)  0@1152r
%vreg30 [1168r,1184r:0)  0@1168r
%vreg34 [1408r,1488r:0)  0@1408r
%vreg41 [1296r,1368r:0)  0@1296r
%vreg42 [1280r,1296r:0)  0@1280r
%vreg44 [1264r,1376r:0)  0@1264r
%vreg45 [1248r,1264r:0)  0@1248r
%vreg48 [2832r,2848r:0)  0@2832r
%vreg51 [2800r,2816r:0)  0@2800r
%vreg53 [2720r,2816r:0)  0@2720r
%vreg60 [2608r,2680r:0)  0@2608r
%vreg61 [2592r,2608r:0)  0@2592r
%vreg63 [2576r,2688r:0)  0@2576r
%vreg64 [2560r,2576r:0)  0@2560r
%vreg67 [2528r,2544r:0)  0@2528r
%vreg69 [2416r,2544r:0)  0@2416r
%vreg78 [2256r,2288r:0)[2288r,2376r:1)  0@2256r 1@2288r
%vreg82 [2208r,2240r:0)[2240r,2256r:1)  0@2208r 1@2240r
%vreg85 [2192r,2372r:0)  0@2192r
%vreg86 [2176r,2192r:0)  0@2176r
%vreg88 [2160r,2384r:0)  0@2160r
%vreg89 [2144r,2160r:0)  0@2144r
%vreg92 [2112r,2128r:0)  0@2112r
%vreg94 [2016r,2128r:0)  0@2016r
%vreg103 [1856r,1888r:0)[1888r,1976r:1)  0@1856r 1@1888r
%vreg107 [1840r,1972r:0)  0@1840r
%vreg108 [1824r,1840r:0)  0@1824r
%vreg110 [1808r,1984r:0)  0@1808r
%vreg111 [1792r,1808r:0)  0@1792r
%vreg114 [1760r,1776r:0)  0@1760r
%vreg116 [1728r,1744r:0)  0@1728r
%vreg118 [1696r,1712r:0)  0@1696r
%vreg120 [1664r,1680r:0)  0@1664r
%vreg123 [1632r,1648r:0)  0@1632r
%vreg124 [1616r,1648r:0)  0@1616r
%vreg127 [2896r,2912r:0)  0@2896r
%vreg130 [2960r,2976r:0)  0@2960r
%vreg132 [5248r,5280r:0)  0@5248r
%vreg134 [5120r,5152r:0)  0@5120r
%vreg136 [5088r,5104r:0)  0@5088r
%vreg138 [5056r,5072r:0)  0@5056r
%vreg140 [5024r,5040r:0)  0@5024r
%vreg142 [4992r,5008r:0)  0@4992r
%vreg145 [4960r,4976r:0)  0@4960r
%vreg147 [4928r,4976r:0)  0@4928r
%vreg151 [4896r,4912r:0)  0@4896r
%vreg153 [4880r,4912r:0)  0@4880r
%vreg154 [4864r,4880r:0)  0@4864r
%vreg156 [4832r,4848r:0)  0@4832r
%vreg159 [4800r,4816r:0)  0@4800r
%vreg161 [4768r,4816r:0)  0@4768r
%vreg164 [4752r,4768r:0)  0@4752r
%vreg167 [4720r,4736r:0)  0@4720r
%vreg169 [4688r,4736r:0)  0@4688r
%vreg172 [4672r,4688r:0)  0@4672r
%vreg175 [4640r,4656r:0)  0@4640r
%vreg176 [4624r,4656r:0)  0@4624r
%vreg179 [4592r,4608r:0)  0@4592r
%vreg180 [4576r,4608r:0)  0@4576r
%vreg183 [4544r,4560r:0)  0@4544r
%vreg185 [4496r,4528r:0)[4528r,4560r:1)  0@4496r 1@4528r
%vreg190 [4464r,4480r:0)  0@4464r
%vreg191 [4448r,4480r:0)  0@4448r
%vreg193 [4416r,4432r:0)  0@4416r
%vreg195 [4384r,4400r:0)  0@4384r
%vreg197 [4352r,4368r:0)  0@4352r
%vreg199 [4320r,4336r:0)  0@4320r
%vreg202 [3024r,3040r:0)  0@3024r
%vreg207 [3168r,3232r:0)  0@3168r
%vreg210 [3152r,3168r:0)  0@3152r
%vreg212 [3136r,3216r:0)  0@3136r
%vreg213 [3120r,3136r:0)  0@3120r
%vreg215 [3104r,3248r:0)  0@3104r
%vreg216 [3088r,3104r:0)  0@3088r
%vreg219 [3344r,3360r:0)  0@3344r
%vreg224 [3488r,3552r:0)  0@3488r
%vreg227 [3472r,3488r:0)  0@3472r
%vreg229 [3456r,3536r:0)  0@3456r
%vreg230 [3440r,3456r:0)  0@3440r
%vreg232 [3424r,3568r:0)  0@3424r
%vreg233 [3408r,3424r:0)  0@3408r
%vreg236 [3664r,3680r:0)  0@3664r
%vreg241 [3808r,3872r:0)  0@3808r
%vreg244 [3792r,3808r:0)  0@3792r
%vreg246 [3776r,3856r:0)  0@3776r
%vreg247 [3760r,3776r:0)  0@3760r
%vreg249 [3744r,3888r:0)  0@3744r
%vreg250 [3728r,3744r:0)  0@3728r
%vreg256 [4096r,4160r:0)  0@4096r
%vreg259 [4080r,4144r:0)  0@4080r
%vreg260 [4064r,4080r:0)  0@4064r
%vreg262 [4048r,4176r:0)  0@4048r
%vreg263 [4032r,4048r:0)  0@4032r
%vreg265 [5584r,5600r:0)  0@5584r
%vreg267 [5408r,5472r:0)  0@5408r
%vreg268 [5440r,5488r:0)  0@5440r
RegMasks: 240r 400r 1376r 1984r 2384r 2688r 3248r 3568r 3888r 4176r 5168r 5296r 5504r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzCompressInit: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=4, align=4, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=4, align=4, at location [SP+8]
  fi#3: size=4, align=4, at location [SP+8]
  fi#4: size=4, align=4, at location [SP+8]
  fi#5: size=4, align=4, at location [SP+8]
  fi#6: size=8, align=8, at location [SP+8]
Function Live Ins: %RDI in %vreg0, %ESI in %vreg2, %EDX in %vreg4, %ECX in %vreg6

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI %ESI %EDX %ECX
16B		%vreg7<def> = COPY %ECX; GR32:%vreg7
32B		%vreg5<def> = COPY %EDX; GR32:%vreg5
48B		%vreg3<def> = COPY %ESI; GR32:%vreg3
64B		%vreg1<def> = COPY %RDI; GR64:%vreg1
144B		%vreg11<def> = MOV64ri <ga:@BZ2_bzCompressInit>; GR64:%vreg11
176B		%vreg12<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg12
192B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
208B		%RDI<def> = COPY %vreg11; GR64:%vreg11
224B		%RSI<def> = COPY %vreg12; GR64:%vreg12
240B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
256B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
272B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
288B		STACKMAP 0, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, %vreg1, 0, <fi#1>, 0, %vreg5, 0, <fi#3>, 0, %vreg7, 0, <fi#4>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4) GR32:%vreg3,%vreg5,%vreg7 GR64:%vreg1
304B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
320B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%strm.addr] GR64:%vreg1
336B		MOV32mr <fi#2>, 1, %noreg, 0, %noreg, %vreg3; mem:ST4[%blockSize100k.addr] GR32:%vreg3
352B		MOV32mr <fi#3>, 1, %noreg, 0, %noreg, %vreg5; mem:ST4[%verbosity.addr] GR32:%vreg5
368B		MOV32mr <fi#4>, 1, %noreg, 0, %noreg, %vreg7; mem:ST4[%workFactor.addr] GR32:%vreg7
384B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
400B		CALL64pcrel32 <ga:@bz_config_ok>, <regmask>, %RSP<imp-use>, %EAX<imp-def>
416B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
432B		%vreg9<def> = COPY %EAX<kill>; GR32:%vreg9
448B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
464B		STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)
480B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
496B		CMP32ri8 %vreg9, 0, %EFLAGS<imp-def>; GR32:%vreg9
512B		JNE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

528B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
544B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -9; mem:ST4[%retval]
560B		JMP_1 <BB#29>
	    Successors according to CFG: BB#29

576B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0
592B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%strm.addr]
608B		JE_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#3

624B	BB#3: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#2
640B		CMP32mi8 <fi#2>, 1, %noreg, 0, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%blockSize100k.addr]
656B		JL_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#4

672B	BB#4: derived from LLVM BB %lor.lhs.false.2
	    Predecessors according to CFG: BB#3
688B		CMP32mi8 <fi#2>, 1, %noreg, 0, %noreg, 9, %EFLAGS<imp-def>; mem:LD4[%blockSize100k.addr]
704B		JG_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#5

720B	BB#5: derived from LLVM BB %lor.lhs.false.4
	    Predecessors according to CFG: BB#4
736B		CMP32mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%workFactor.addr]
752B		JL_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#6

768B	BB#6: derived from LLVM BB %lor.lhs.false.6
	    Predecessors according to CFG: BB#5
784B		CMP32mi <fi#4>, 1, %noreg, 0, %noreg, 250, %EFLAGS<imp-def>; mem:LD4[%workFactor.addr]
800B		JLE_1 <BB#8>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#8 BB#7

816B	BB#7: derived from LLVM BB %if.then.8
	    Predecessors according to CFG: BB#2 BB#3 BB#4 BB#5 BB#6
832B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
848B		JMP_1 <BB#29>
	    Successors according to CFG: BB#29

864B	BB#8: derived from LLVM BB %if.end.9
	    Predecessors according to CFG: BB#6
880B		CMP32mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%workFactor.addr]
896B		JNE_1 <BB#10>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#10 BB#9

912B	BB#9: derived from LLVM BB %if.then.11
	    Predecessors according to CFG: BB#8
928B		MOV32mi <fi#4>, 1, %noreg, 0, %noreg, 30; mem:ST4[%workFactor.addr]
	    Successors according to CFG: BB#10

944B	BB#10: derived from LLVM BB %if.end.12
	    Predecessors according to CFG: BB#8 BB#9
960B		%vreg21<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg21
976B		CMP64mi8 %vreg21, 1, %noreg, 56, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzalloc] GR64:%vreg21
992B		JNE_1 <BB#12>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#12 BB#11

1008B	BB#11: derived from LLVM BB %if.then.14
	    Predecessors according to CFG: BB#10
1024B		%vreg23<def> = MOV64ri <ga:@default_bzalloc>; GR64:%vreg23
1040B		%vreg24<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg24
1056B		MOV64mr %vreg24, 1, %noreg, 56, %noreg, %vreg23; mem:ST8[%bzalloc15] GR64:%vreg24,%vreg23
	    Successors according to CFG: BB#12

1072B	BB#12: derived from LLVM BB %if.end.16
	    Predecessors according to CFG: BB#10 BB#11
1088B		%vreg27<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg27
1104B		CMP64mi8 %vreg27, 1, %noreg, 64, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzfree] GR64:%vreg27
1120B		JNE_1 <BB#14>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#14 BB#13

1136B	BB#13: derived from LLVM BB %if.then.18
	    Predecessors according to CFG: BB#12
1152B		%vreg29<def> = MOV64ri <ga:@default_bzfree>; GR64:%vreg29
1168B		%vreg30<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg30
1184B		MOV64mr %vreg30, 1, %noreg, 64, %noreg, %vreg29; mem:ST8[%bzfree19] GR64:%vreg30,%vreg29
	    Successors according to CFG: BB#14

1200B	BB#14: derived from LLVM BB %if.end.20
	    Predecessors according to CFG: BB#12 BB#13
1248B		%vreg45<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg45
1264B		%vreg44<def> = MOV64rm %vreg45, 1, %noreg, 56, %noreg; mem:LD8[%bzalloc21] GR64:%vreg44,%vreg45
1280B		%vreg42<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg42
1296B		%vreg41<def> = MOV64rm %vreg42, 1, %noreg, 72, %noreg; mem:LD8[%opaque] GR64:%vreg41,%vreg42
1312B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1344B		%ESI<def> = MOV32ri 55768
1360B		%EDX<def> = MOV32ri 1
1368B		%RDI<def> = COPY %vreg41; GR64:%vreg41
1376B		CALL64r %vreg44, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %EDX<imp-use>, %RAX<imp-def>; GR64:%vreg44
1392B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1408B		%vreg34<def> = COPY %RAX<kill>; GR64:%vreg34
1424B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1440B		STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)
1456B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1488B		MOV64mr <fi#6>, 1, %noreg, 0, %noreg, %vreg34; mem:ST8[%s] GR64:%vreg34
1504B		CMP64mi8 <fi#6>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%s]
1520B		JNE_1 <BB#16>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#16 BB#15

1536B	BB#15: derived from LLVM BB %if.then.24
	    Predecessors according to CFG: BB#14
1552B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -3; mem:ST4[%retval]
1568B		JMP_1 <BB#29>
	    Successors according to CFG: BB#29

1584B	BB#16: derived from LLVM BB %if.end.25
	    Predecessors according to CFG: BB#14
1616B		%vreg124<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg124
1632B		%vreg123<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg123
1648B		MOV64mr %vreg123, 1, %noreg, 0, %noreg, %vreg124; mem:ST8[%strm26] GR64:%vreg123,%vreg124
1664B		%vreg120<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg120
1680B		MOV64mi32 %vreg120, 1, %noreg, 24, %noreg, 0; mem:ST8[%arr1] GR64:%vreg120
1696B		%vreg118<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg118
1712B		MOV64mi32 %vreg118, 1, %noreg, 32, %noreg, 0; mem:ST8[%arr2] GR64:%vreg118
1728B		%vreg116<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg116
1744B		MOV64mi32 %vreg116, 1, %noreg, 40, %noreg, 0; mem:ST8[%ftab] GR64:%vreg116
1760B		%vreg114<def> = IMUL32rmi <fi#2>, 1, %noreg, 0, %noreg, 100000, %EFLAGS<imp-def,dead>; mem:LD4[%blockSize100k.addr] GR32:%vreg114
1776B		MOV32mr <fi#5>, 1, %noreg, 0, %noreg, %vreg114; mem:ST4[%n] GR32:%vreg114
1792B		%vreg111<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg111
1808B		%vreg110<def> = MOV64rm %vreg111, 1, %noreg, 56, %noreg; mem:LD8[%bzalloc27] GR64:%vreg110,%vreg111
1824B		%vreg108<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg108
1840B		%vreg107<def> = MOV64rm %vreg108, 1, %noreg, 72, %noreg; mem:LD8[%opaque28] GR64:%vreg107,%vreg108
1856B		%vreg103<def> = MOVSX64rm32 <fi#5>, 1, %noreg, 0, %noreg; mem:LD4[%n] GR64_with_sub_8bit:%vreg103
1888B		%vreg103<def,tied1> = SHL64ri %vreg103<tied0>, 2, %EFLAGS<imp-def,dead>; GR64_with_sub_8bit:%vreg103
1920B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1968B		%EDX<def> = MOV32ri 1
1972B		%RDI<def> = COPY %vreg107; GR64:%vreg107
1976B		%ESI<def> = COPY %vreg103:sub_32bit; GR64_with_sub_8bit:%vreg103
1984B		CALL64r %vreg110, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %EDX<imp-use>, %RAX<imp-def>; GR64:%vreg110
2000B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2016B		%vreg94<def> = COPY %RAX<kill>; GR64:%vreg94
2048B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2064B		STACKMAP 3, 0, 0, <fi#2>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)
2080B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2112B		%vreg92<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg92
2128B		MOV64mr %vreg92, 1, %noreg, 24, %noreg, %vreg94; mem:ST8[%arr132] GR64:%vreg92,%vreg94
2144B		%vreg89<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg89
2160B		%vreg88<def> = MOV64rm %vreg89, 1, %noreg, 56, %noreg; mem:LD8[%bzalloc33] GR64:%vreg88,%vreg89
2176B		%vreg86<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg86
2192B		%vreg85<def> = MOV64rm %vreg86, 1, %noreg, 72, %noreg; mem:LD8[%opaque34] GR64:%vreg85,%vreg86
2208B		%vreg82<def> = MOV32rm <fi#5>, 1, %noreg, 0, %noreg; mem:LD4[%n] GR32:%vreg82
2240B		%vreg82<def,tied1> = ADD32ri8 %vreg82<tied0>, 34, %EFLAGS<imp-def,dead>; GR32:%vreg82
2256B		%vreg78<def> = MOVSX64rr32 %vreg82; GR64_with_sub_8bit:%vreg78 GR32:%vreg82
2288B		%vreg78<def,tied1> = SHL64ri %vreg78<tied0>, 2, %EFLAGS<imp-def,dead>; GR64_with_sub_8bit:%vreg78
2320B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2368B		%EDX<def> = MOV32ri 1
2372B		%RDI<def> = COPY %vreg85; GR64:%vreg85
2376B		%ESI<def> = COPY %vreg78:sub_32bit; GR64_with_sub_8bit:%vreg78
2384B		CALL64r %vreg88, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %EDX<imp-use>, %RAX<imp-def>; GR64:%vreg88
2400B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2416B		%vreg69<def> = COPY %RAX<kill>; GR64:%vreg69
2464B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2480B		STACKMAP 4, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)
2496B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2528B		%vreg67<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg67
2544B		MOV64mr %vreg67, 1, %noreg, 32, %noreg, %vreg69; mem:ST8[%arr239] GR64:%vreg67,%vreg69
2560B		%vreg64<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg64
2576B		%vreg63<def> = MOV64rm %vreg64, 1, %noreg, 56, %noreg; mem:LD8[%bzalloc40] GR64:%vreg63,%vreg64
2592B		%vreg61<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg61
2608B		%vreg60<def> = MOV64rm %vreg61, 1, %noreg, 72, %noreg; mem:LD8[%opaque41] GR64:%vreg60,%vreg61
2624B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2656B		%ESI<def> = MOV32ri 262148
2672B		%EDX<def> = MOV32ri 1
2680B		%RDI<def> = COPY %vreg60; GR64:%vreg60
2688B		CALL64r %vreg63, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %EDX<imp-use>, %RAX<imp-def>; GR64:%vreg63
2704B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2720B		%vreg53<def> = COPY %RAX<kill>; GR64:%vreg53
2736B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2752B		STACKMAP 5, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)
2768B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2800B		%vreg51<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg51
2816B		MOV64mr %vreg51, 1, %noreg, 40, %noreg, %vreg53; mem:ST8[%ftab43] GR64:%vreg51,%vreg53
2832B		%vreg48<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg48
2848B		CMP64mi8 %vreg48, 1, %noreg, 24, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%arr144] GR64:%vreg48
2864B		JE_1 <BB#19>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#19 BB#17

2880B	BB#17: derived from LLVM BB %lor.lhs.false.47
	    Predecessors according to CFG: BB#16
2896B		%vreg127<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg127
2912B		CMP64mi8 %vreg127, 1, %noreg, 32, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%arr248] GR64:%vreg127
2928B		JE_1 <BB#19>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#19 BB#18

2944B	BB#18: derived from LLVM BB %lor.lhs.false.51
	    Predecessors according to CFG: BB#17
2960B		%vreg130<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg130
2976B		CMP64mi8 %vreg130, 1, %noreg, 40, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%ftab52] GR64:%vreg130
2992B		JNE_1 <BB#28>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#28 BB#19

3008B	BB#19: derived from LLVM BB %if.then.55
	    Predecessors according to CFG: BB#16 BB#17 BB#18
3024B		%vreg202<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg202
3040B		CMP64mi8 %vreg202, 1, %noreg, 24, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%arr156] GR64:%vreg202
3056B		JE_1 <BB#21>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#21 BB#20

3072B	BB#20: derived from LLVM BB %if.then.59
	    Predecessors according to CFG: BB#19
3088B		%vreg216<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg216
3104B		%vreg215<def> = MOV64rm %vreg216, 1, %noreg, 64, %noreg; mem:LD8[%bzfree60] GR64:%vreg215,%vreg216
3120B		%vreg213<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg213
3136B		%vreg212<def> = MOV64rm %vreg213, 1, %noreg, 72, %noreg; mem:LD8[%opaque61] GR64:%vreg212,%vreg213
3152B		%vreg210<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg210
3168B		%vreg207<def> = MOV64rm %vreg210, 1, %noreg, 24, %noreg; mem:LD8[%arr162] GR64:%vreg207,%vreg210
3200B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3216B		%RDI<def> = COPY %vreg212; GR64:%vreg212
3232B		%RSI<def> = COPY %vreg207; GR64:%vreg207
3248B		CALL64r %vreg215, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>; GR64:%vreg215
3264B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3280B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3296B		STACKMAP 6, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1]
3312B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#21

3328B	BB#21: derived from LLVM BB %if.end.63
	    Predecessors according to CFG: BB#19 BB#20
3344B		%vreg219<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg219
3360B		CMP64mi8 %vreg219, 1, %noreg, 32, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%arr264] GR64:%vreg219
3376B		JE_1 <BB#23>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#23 BB#22

3392B	BB#22: derived from LLVM BB %if.then.67
	    Predecessors according to CFG: BB#21
3408B		%vreg233<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg233
3424B		%vreg232<def> = MOV64rm %vreg233, 1, %noreg, 64, %noreg; mem:LD8[%bzfree68] GR64:%vreg232,%vreg233
3440B		%vreg230<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg230
3456B		%vreg229<def> = MOV64rm %vreg230, 1, %noreg, 72, %noreg; mem:LD8[%opaque69] GR64:%vreg229,%vreg230
3472B		%vreg227<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg227
3488B		%vreg224<def> = MOV64rm %vreg227, 1, %noreg, 32, %noreg; mem:LD8[%arr270] GR64:%vreg224,%vreg227
3520B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3536B		%RDI<def> = COPY %vreg229; GR64:%vreg229
3552B		%RSI<def> = COPY %vreg224; GR64:%vreg224
3568B		CALL64r %vreg232, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>; GR64:%vreg232
3584B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3600B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3616B		STACKMAP 7, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1]
3632B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#23

3648B	BB#23: derived from LLVM BB %if.end.71
	    Predecessors according to CFG: BB#21 BB#22
3664B		%vreg236<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg236
3680B		CMP64mi8 %vreg236, 1, %noreg, 40, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%ftab72] GR64:%vreg236
3696B		JE_1 <BB#25>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#25 BB#24

3712B	BB#24: derived from LLVM BB %if.then.75
	    Predecessors according to CFG: BB#23
3728B		%vreg250<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg250
3744B		%vreg249<def> = MOV64rm %vreg250, 1, %noreg, 64, %noreg; mem:LD8[%bzfree76] GR64:%vreg249,%vreg250
3760B		%vreg247<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg247
3776B		%vreg246<def> = MOV64rm %vreg247, 1, %noreg, 72, %noreg; mem:LD8[%opaque77] GR64:%vreg246,%vreg247
3792B		%vreg244<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg244
3808B		%vreg241<def> = MOV64rm %vreg244, 1, %noreg, 40, %noreg; mem:LD8[%ftab78] GR64:%vreg241,%vreg244
3840B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3856B		%RDI<def> = COPY %vreg246; GR64:%vreg246
3872B		%RSI<def> = COPY %vreg241; GR64:%vreg241
3888B		CALL64r %vreg249, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>; GR64:%vreg249
3904B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3920B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3936B		STACKMAP 8, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1]
3952B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#25

3968B	BB#25: derived from LLVM BB %if.end.79
	    Predecessors according to CFG: BB#23 BB#24
3984B		CMP64mi8 <fi#6>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%s]
4000B		JE_1 <BB#27>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#27 BB#26

4016B	BB#26: derived from LLVM BB %if.then.82
	    Predecessors according to CFG: BB#25
4032B		%vreg263<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg263
4048B		%vreg262<def> = MOV64rm %vreg263, 1, %noreg, 64, %noreg; mem:LD8[%bzfree83] GR64:%vreg262,%vreg263
4064B		%vreg260<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg260
4080B		%vreg259<def> = MOV64rm %vreg260, 1, %noreg, 72, %noreg; mem:LD8[%opaque84] GR64:%vreg259,%vreg260
4096B		%vreg256<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg256
4128B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4144B		%RDI<def> = COPY %vreg259; GR64:%vreg259
4160B		%RSI<def> = COPY %vreg256; GR64:%vreg256
4176B		CALL64r %vreg262, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>; GR64:%vreg262
4192B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4208B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4224B		STACKMAP 9, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
4240B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#27

4256B	BB#27: derived from LLVM BB %if.end.85
	    Predecessors according to CFG: BB#25 BB#26
4272B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -3; mem:ST4[%retval]
4288B		JMP_1 <BB#29>
	    Successors according to CFG: BB#29

4304B	BB#28: derived from LLVM BB %if.end.86
	    Predecessors according to CFG: BB#18
4320B		%vreg199<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg199
4336B		MOV32mi %vreg199, 1, %noreg, 660, %noreg, 0; mem:ST4[%blockNo] GR64:%vreg199
4352B		%vreg197<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg197
4368B		MOV32mi %vreg197, 1, %noreg, 12, %noreg, 2; mem:ST4[%state] GR64:%vreg197
4384B		%vreg195<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg195
4400B		MOV32mi %vreg195, 1, %noreg, 8, %noreg, 2; mem:ST4[%mode] GR64:%vreg195
4416B		%vreg193<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg193
4432B		MOV32mi %vreg193, 1, %noreg, 652, %noreg, 0; mem:ST4[%combinedCRC] GR64:%vreg193
4448B		%vreg191<def> = MOV32rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD4[%blockSize100k.addr] GR32:%vreg191
4464B		%vreg190<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg190
4480B		MOV32mr %vreg190, 1, %noreg, 664, %noreg, %vreg191; mem:ST4[%blockSize100k87] GR64:%vreg190 GR32:%vreg191
4496B		%vreg185<def> = IMUL32rmi <fi#2>, 1, %noreg, 0, %noreg, 100000, %EFLAGS<imp-def,dead>; mem:LD4[%blockSize100k.addr] GR32:%vreg185
4528B		%vreg185<def,tied1> = SUB32ri8 %vreg185<tied0>, 19, %EFLAGS<imp-def,dead>; GR32:%vreg185
4544B		%vreg183<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg183
4560B		MOV32mr %vreg183, 1, %noreg, 112, %noreg, %vreg185; mem:ST4[%nblockMAX] GR64:%vreg183 GR32:%vreg185
4576B		%vreg180<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%verbosity.addr] GR32:%vreg180
4592B		%vreg179<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg179
4608B		MOV32mr %vreg179, 1, %noreg, 656, %noreg, %vreg180; mem:ST4[%verbosity89] GR64:%vreg179 GR32:%vreg180
4624B		%vreg176<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%workFactor.addr] GR32:%vreg176
4640B		%vreg175<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg175
4656B		MOV32mr %vreg175, 1, %noreg, 88, %noreg, %vreg176; mem:ST4[%workFactor90] GR64:%vreg175 GR32:%vreg176
4672B		%vreg172<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg172
4688B		%vreg169<def> = MOV64rm %vreg172, 1, %noreg, 32, %noreg; mem:LD8[%arr291] GR64:%vreg169,%vreg172
4720B		%vreg167<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg167
4736B		MOV64mr %vreg167, 1, %noreg, 64, %noreg, %vreg169; mem:ST8[%block] GR64:%vreg167,%vreg169
4752B		%vreg164<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg164
4768B		%vreg161<def> = MOV64rm %vreg164, 1, %noreg, 24, %noreg; mem:LD8[%arr192] GR64:%vreg161,%vreg164
4800B		%vreg159<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg159
4816B		MOV64mr %vreg159, 1, %noreg, 72, %noreg, %vreg161; mem:ST8[%mtfv] GR64:%vreg159,%vreg161
4832B		%vreg156<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg156
4848B		MOV64mi32 %vreg156, 1, %noreg, 80, %noreg, 0; mem:ST8[%zbits] GR64:%vreg156
4864B		%vreg154<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg154
4880B		%vreg153<def> = MOV64rm %vreg154, 1, %noreg, 24, %noreg; mem:LD8[%arr193] GR64:%vreg153,%vreg154
4896B		%vreg151<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg151
4912B		MOV64mr %vreg151, 1, %noreg, 56, %noreg, %vreg153; mem:ST8[%ptr] GR64:%vreg151,%vreg153
4928B		%vreg147<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg147
4960B		%vreg145<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg145
4976B		MOV64mr %vreg145, 1, %noreg, 48, %noreg, %vreg147; mem:ST8[%state94] GR64:%vreg145,%vreg147
4992B		%vreg142<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg142
5008B		MOV32mi %vreg142, 1, %noreg, 12, %noreg, 0; mem:ST4[%total_in_lo32] GR64:%vreg142
5024B		%vreg140<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg140
5040B		MOV32mi %vreg140, 1, %noreg, 16, %noreg, 0; mem:ST4[%total_in_hi32] GR64:%vreg140
5056B		%vreg138<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg138
5072B		MOV32mi %vreg138, 1, %noreg, 36, %noreg, 0; mem:ST4[%total_out_lo32] GR64:%vreg138
5088B		%vreg136<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg136
5104B		MOV32mi %vreg136, 1, %noreg, 40, %noreg, 0; mem:ST4[%total_out_hi32] GR64:%vreg136
5120B		%vreg134<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg134
5136B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5152B		%RDI<def> = COPY %vreg134; GR64:%vreg134
5168B		CALL64pcrel32 <ga:@init_RL>, <regmask>, %RSP<imp-use>, %RDI<imp-use>
5184B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5200B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5216B		STACKMAP 10, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack6]
5232B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5248B		%vreg132<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg132
5264B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5280B		%RDI<def> = COPY %vreg132; GR64:%vreg132
5296B		CALL64pcrel32 <ga:@prepare_new_block>, <regmask>, %RSP<imp-use>, %RDI<imp-use>
5312B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5328B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5344B		STACKMAP 11, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
5360B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5376B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
	    Successors according to CFG: BB#29

5392B	BB#29: derived from LLVM BB %return
	    Predecessors according to CFG: BB#1 BB#28 BB#27 BB#15 BB#7
5408B		%vreg267<def> = MOV64ri <ga:@BZ2_bzCompressInit>; GR64:%vreg267
5440B		%vreg268<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg268
5456B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5472B		%RDI<def> = COPY %vreg267; GR64:%vreg267
5488B		%RSI<def> = COPY %vreg268; GR64:%vreg268
5504B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
5520B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5536B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5552B		STACKMAP 12, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
5568B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5584B		%vreg265<def> = MOV32rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD4[%retval] GR32:%vreg265
5600B		%EAX<def> = COPY %vreg265; GR32:%vreg265
5616B		RETQ %EAX<imp-use,kill>

# End machine code for function BZ2_bzCompressInit.


selectOrSplit GR32:%vreg7 [16r,368r:0)  0@16r w=4.029255e-03
hints: %ECX
missed hint %ECX
assigning %vreg7 to %EBX: BH [16r,368r:0)  0@16r BL [16r,368r:0)  0@16r

selectOrSplit GR32:%vreg5 [32r,352r:0)  0@32r w=4.208333e-03
hints: %EDX
missed hint %EDX
%R14D is available at cost 1
Only trying the first 10 regs.
should evict: %vreg7 [16r,368r:0)  0@16r w= 4.029255e-03
hints: %ECX
can reassign: %vreg7 [16r,368r:0)  0@16r from %EBX to %ECX
should evict: %vreg7 [16r,368r:0)  0@16r w= 4.029255e-03
hints: %ECX
can reassign: %vreg7 [16r,368r:0)  0@16r from %EBX to %ECX
evicting %EBX interference: Cascade 1
unassigning %vreg7 from %EBX: BH BL
assigning %vreg5 to %EBX: BH [32r,352r:0)  0@32r BL [32r,352r:0)  0@32r
queuing new interval: %vreg7 [16r,368r:0)  0@16r

selectOrSplit GR32:%vreg7 [16r,368r:0)  0@16r w=4.029255e-03
hints: %ECX
missed hint %ECX
%R14D is available at cost 1
Only trying the first 10 regs.
assigning %vreg7 to %R14D: R14B [16r,368r:0)  0@16r

selectOrSplit GR32:%vreg3 [48r,336r:0)  0@48r w=4.404070e-03
hints: %ESI
missed hint %ESI
%R15D is available at cost 1
Only trying the first 10 regs.
should evict: %vreg5 [32r,352r:0)  0@32r w= 4.208333e-03
hints: %EDX
can reassign: %vreg5 [32r,352r:0)  0@32r from %EBX to %EDX
should evict: %vreg5 [32r,352r:0)  0@32r w= 4.208333e-03
hints: %EDX
can reassign: %vreg5 [32r,352r:0)  0@32r from %EBX to %EDX
evicting %EBX interference: Cascade 2
unassigning %vreg5 from %EBX: BH BL
assigning %vreg3 to %EBX: BH [48r,336r:0)  0@48r BL [48r,336r:0)  0@48r
queuing new interval: %vreg5 [32r,352r:0)  0@32r

selectOrSplit GR32:%vreg5 [32r,352r:0)  0@32r w=4.208333e-03
hints: %EDX
missed hint %EDX
%R15D is available at cost 1
Only trying the first 10 regs.
assigning %vreg5 to %R15D: R15B [32r,352r:0)  0@32r

selectOrSplit GR64:%vreg1 [64r,320r:0)  0@64r w=4.618902e-03
hints: %RDI
missed hint %RDI
%R12 is available at cost 1
Only trying the first 10 regs.
should evict: %vreg3 [48r,336r:0)  0@48r w= 4.404070e-03
hints: %ESI
can reassign: %vreg3 [48r,336r:0)  0@48r from %RBX to %ESI
should evict: %vreg3 [48r,336r:0)  0@48r w= 4.404070e-03
hints: %ESI
can reassign: %vreg3 [48r,336r:0)  0@48r from %RBX to %ESI
evicting %RBX interference: Cascade 3
unassigning %vreg3 from %EBX: BH BL
assigning %vreg1 to %RBX: BH [64r,320r:0)  0@64r BL [64r,320r:0)  0@64r
queuing new interval: %vreg3 [48r,336r:0)  0@48r

selectOrSplit GR32:%vreg3 [48r,336r:0)  0@48r w=4.404070e-03
hints: %ESI
missed hint %ESI
%R12D is available at cost 1
Only trying the first 10 regs.
assigning %vreg3 to %R12D: R12B [48r,336r:0)  0@48r

selectOrSplit GR64:%vreg11 [144r,208r:0)  0@144r w=2.176724e-03
hints: %RDI
assigning %vreg11 to %RDI: DIL [144r,208r:0)  0@144r

selectOrSplit GR64:%vreg12 [176r,224r:0)  0@176r w=4.508928e-03
hints: %RSI
assigning %vreg12 to %RSI: SIL [176r,224r:0)  0@176r

selectOrSplit GR32:%vreg9 [432r,496r:0)  0@432r w=4.353448e-03
hints: %EAX
assigning %vreg9 to %EAX: AH [432r,496r:0)  0@432r AL [432r,496r:0)  0@432r

selectOrSplit GR64:%vreg41 [1296r,1368r:0)  0@1296r w=6.635539e-05
hints: %RDI
assigning %vreg41 to %RDI: DIL [1296r,1368r:0)  0@1296r

selectOrSplit GR64:%vreg34 [1408r,1488r:0)  0@1408r w=6.524946e-05
hints: %RAX
assigning %vreg34 to %RAX: AH [1408r,1488r:0)  0@1408r AL [1408r,1488r:0)  0@1408r

selectOrSplit GR64:%vreg107 [1840r,1972r:0)  0@1840r w=2.920407e-05
hints: %RDI
assigning %vreg107 to %RDI: DIL [1840r,1972r:0)  0@1840r

selectOrSplit GR64_with_sub_8bit:%vreg103 [1856r,1888r:0)[1888r,1976r:1)  0@1856r 1@1888r w=5.975602e-05
AllocationOrder(GR64_with_sub_8bit) = [ %RAX %RCX %RDX %RSI %RDI %R8 %R9 %R10 %R11 %RBX %R14 %R15 %R12 %R13 ]
hints: %RSI
assigning %vreg103 to %RSI: SIL [1856r,1888r:0)[1888r,1976r:1)  0@1856r 1@1888r

selectOrSplit GR64:%vreg94 [2016r,2128r:0)  0@2016r w=3.034485e-05
hints: %RAX
assigning %vreg94 to %RAX: AH [2016r,2128r:0)  0@2016r AL [2016r,2128r:0)  0@2016r

selectOrSplit GR64:%vreg85 [2192r,2372r:0)  0@2192r w=2.678718e-05
hints: %RDI
assigning %vreg85 to %RDI: DIL [2192r,2372r:0)  0@2192r

selectOrSplit GR64_with_sub_8bit:%vreg78 [2256r,2288r:0)[2288r,2376r:1)  0@2256r 1@2288r w=5.975602e-05
hints: %RSI
assigning %vreg78 to %RSI: SIL [2256r,2288r:0)[2288r,2376r:1)  0@2256r 1@2288r

selectOrSplit GR64:%vreg69 [2416r,2544r:0)  0@2416r w=2.942531e-05
hints: %RAX
assigning %vreg69 to %RAX: AH [2416r,2544r:0)  0@2416r AL [2416r,2544r:0)  0@2416r

selectOrSplit GR64:%vreg60 [2608r,2680r:0)  0@2608r w=3.291645e-05
hints: %RDI
assigning %vreg60 to %RDI: DIL [2608r,2680r:0)  0@2608r

selectOrSplit GR64:%vreg53 [2720r,2816r:0)  0@2720r w=3.132372e-05
hints: %RAX
assigning %vreg53 to %RAX: AH [2720r,2816r:0)  0@2720r AL [2720r,2816r:0)  0@2720r

selectOrSplit GR64:%vreg212 [3136r,3216r:0)  0@3136r w=1.387193e-05
hints: %RDI
assigning %vreg212 to %RDI: DIL [3136r,3216r:0)  0@3136r

selectOrSplit GR64:%vreg207 [3168r,3232r:0)  0@3168r w=1.435027e-05
hints: %RSI
assigning %vreg207 to %RSI: SIL [3168r,3232r:0)  0@3168r

selectOrSplit GR64:%vreg229 [3456r,3536r:0)  0@3456r w=1.387193e-05
hints: %RDI
assigning %vreg229 to %RDI: DIL [3456r,3536r:0)  0@3456r

selectOrSplit GR64:%vreg224 [3488r,3552r:0)  0@3488r w=1.435027e-05
hints: %RSI
assigning %vreg224 to %RSI: SIL [3488r,3552r:0)  0@3488r

selectOrSplit GR64:%vreg246 [3776r,3856r:0)  0@3776r w=1.387193e-05
hints: %RDI
assigning %vreg246 to %RDI: DIL [3776r,3856r:0)  0@3776r

selectOrSplit GR64:%vreg241 [3808r,3872r:0)  0@3808r w=1.435027e-05
hints: %RSI
assigning %vreg241 to %RSI: SIL [3808r,3872r:0)  0@3808r

selectOrSplit GR64:%vreg259 [4080r,4144r:0)  0@4080r w=1.435027e-05
hints: %RDI
assigning %vreg259 to %RDI: DIL [4080r,4144r:0)  0@4080r

selectOrSplit GR64:%vreg256 [4096r,4160r:0)  0@4096r w=1.435027e-05
hints: %RSI
assigning %vreg256 to %RSI: SIL [4096r,4160r:0)  0@4096r

selectOrSplit GR64:%vreg134 [5120r,5152r:0)  0@5120r w=4.566891e-06
hints: %RDI
assigning %vreg134 to %RDI: DIL [5120r,5152r:0)  0@5120r

selectOrSplit GR64:%vreg132 [5248r,5280r:0)  0@5248r w=4.566891e-06
hints: %RDI
assigning %vreg132 to %RDI: DIL [5248r,5280r:0)  0@5248r

selectOrSplit GR64:%vreg267 [5408r,5472r:0)  0@5408r w=2.176724e-03
hints: %RDI
assigning %vreg267 to %RDI: DIL [5408r,5472r:0)  0@5408r

selectOrSplit GR64:%vreg268 [5440r,5488r:0)  0@5440r w=4.508928e-03
hints: %RSI
assigning %vreg268 to %RSI: SIL [5440r,5488r:0)  0@5440r

selectOrSplit GR32:%vreg265 [5584r,5600r:0)  0@5584r w=inf
hints: %EAX
assigning %vreg265 to %EAX: AH [5584r,5600r:0)  0@5584r AL [5584r,5600r:0)  0@5584r

selectOrSplit GR64:%vreg21 [960r,976r:0)  0@960r w=inf
assigning %vreg21 to %RAX: AH [960r,976r:0)  0@960r AL [960r,976r:0)  0@960r

selectOrSplit GR64:%vreg23 [1024r,1056r:0)  0@1024r w=1.780409e-05
assigning %vreg23 to %RAX: AH [1024r,1056r:0)  0@1024r AL [1024r,1056r:0)  0@1024r

selectOrSplit GR64:%vreg24 [1040r,1056r:0)  0@1040r w=inf
assigning %vreg24 to %RCX: CH [1040r,1056r:0)  0@1040r CL [1040r,1056r:0)  0@1040r

selectOrSplit GR64:%vreg27 [1088r,1104r:0)  0@1088r w=inf
assigning %vreg27 to %RAX: AH [1088r,1104r:0)  0@1088r AL [1088r,1104r:0)  0@1088r

selectOrSplit GR64:%vreg29 [1152r,1184r:0)  0@1152r w=1.780409e-05
assigning %vreg29 to %RAX: AH [1152r,1184r:0)  0@1152r AL [1152r,1184r:0)  0@1152r

selectOrSplit GR64:%vreg30 [1168r,1184r:0)  0@1168r w=inf
assigning %vreg30 to %RCX: CH [1168r,1184r:0)  0@1168r CL [1168r,1184r:0)  0@1168r

selectOrSplit GR64:%vreg45 [1248r,1264r:0)  0@1248r w=inf
assigning %vreg45 to %RAX: AH [1248r,1264r:0)  0@1248r AL [1248r,1264r:0)  0@1248r

selectOrSplit GR64:%vreg44 [1264r,1376r:0)  0@1264r w=6.056571e-05
assigning %vreg44 to %RAX: AH [1264r,1376r:0)  0@1264r AL [1264r,1376r:0)  0@1264r

selectOrSplit GR64:%vreg42 [1280r,1296r:0)  0@1280r w=inf
assigning %vreg42 to %RCX: CH [1280r,1296r:0)  0@1280r CL [1280r,1296r:0)  0@1280r

selectOrSplit GR64:%vreg124 [1616r,1648r:0)  0@1616r w=3.560819e-05
assigning %vreg124 to %RAX: AH [1616r,1648r:0)  0@1616r AL [1616r,1648r:0)  0@1616r

selectOrSplit GR64:%vreg123 [1632r,1648r:0)  0@1632r w=inf
assigning %vreg123 to %RCX: CH [1632r,1648r:0)  0@1632r CL [1632r,1648r:0)  0@1632r

selectOrSplit GR64:%vreg120 [1664r,1680r:0)  0@1664r w=inf
assigning %vreg120 to %RAX: AH [1664r,1680r:0)  0@1664r AL [1664r,1680r:0)  0@1664r

selectOrSplit GR64:%vreg118 [1696r,1712r:0)  0@1696r w=inf
assigning %vreg118 to %RAX: AH [1696r,1712r:0)  0@1696r AL [1696r,1712r:0)  0@1696r

selectOrSplit GR64:%vreg116 [1728r,1744r:0)  0@1728r w=inf
assigning %vreg116 to %RAX: AH [1728r,1744r:0)  0@1728r AL [1728r,1744r:0)  0@1728r

selectOrSplit GR32:%vreg114 [1760r,1776r:0)  0@1760r w=inf
assigning %vreg114 to %EAX: AH [1760r,1776r:0)  0@1760r AL [1760r,1776r:0)  0@1760r

selectOrSplit GR64:%vreg111 [1792r,1808r:0)  0@1792r w=inf
assigning %vreg111 to %RAX: AH [1792r,1808r:0)  0@1792r AL [1792r,1808r:0)  0@1792r

selectOrSplit GR64:%vreg110 [1808r,1984r:0)  0@1808r w=2.670614e-05
assigning %vreg110 to %RAX: AH [1808r,1984r:0)  0@1808r AL [1808r,1984r:0)  0@1808r

selectOrSplit GR64:%vreg108 [1824r,1840r:0)  0@1824r w=inf
assigning %vreg108 to %RCX: CH [1824r,1840r:0)  0@1824r CL [1824r,1840r:0)  0@1824r

selectOrSplit GR64:%vreg92 [2112r,2128r:0)  0@2112r w=inf
assigning %vreg92 to %RCX: CH [2112r,2128r:0)  0@2112r CL [2112r,2128r:0)  0@2112r

selectOrSplit GR64:%vreg89 [2144r,2160r:0)  0@2144r w=inf
assigning %vreg89 to %RAX: AH [2144r,2160r:0)  0@2144r AL [2144r,2160r:0)  0@2144r

selectOrSplit GR64:%vreg88 [2160r,2384r:0)  0@2160r w=2.465182e-05
assigning %vreg88 to %RAX: AH [2160r,2384r:0)  0@2160r AL [2160r,2384r:0)  0@2160r

selectOrSplit GR64:%vreg86 [2176r,2192r:0)  0@2176r w=inf
assigning %vreg86 to %RCX: CH [2176r,2192r:0)  0@2176r CL [2176r,2192r:0)  0@2176r

selectOrSplit GR32:%vreg82 [2208r,2240r:0)[2240r,2256r:1)  0@2208r 1@2240r w=inf
assigning %vreg82 to %ECX: CH [2208r,2240r:0)[2240r,2256r:1)  0@2208r 1@2240r CL [2208r,2240r:0)[2240r,2256r:1)  0@2208r 1@2240r

selectOrSplit GR64:%vreg67 [2528r,2544r:0)  0@2528r w=inf
assigning %vreg67 to %RCX: CH [2528r,2544r:0)  0@2528r CL [2528r,2544r:0)  0@2528r

selectOrSplit GR64:%vreg64 [2560r,2576r:0)  0@2560r w=inf
assigning %vreg64 to %RAX: AH [2560r,2576r:0)  0@2560r AL [2560r,2576r:0)  0@2560r

selectOrSplit GR64:%vreg63 [2576r,2688r:0)  0@2576r w=3.004441e-05
assigning %vreg63 to %RAX: AH [2576r,2688r:0)  0@2576r AL [2576r,2688r:0)  0@2576r

selectOrSplit GR64:%vreg61 [2592r,2608r:0)  0@2592r w=inf
assigning %vreg61 to %RCX: CH [2592r,2608r:0)  0@2592r CL [2592r,2608r:0)  0@2592r

selectOrSplit GR64:%vreg51 [2800r,2816r:0)  0@2800r w=inf
assigning %vreg51 to %RCX: CH [2800r,2816r:0)  0@2800r CL [2800r,2816r:0)  0@2800r

selectOrSplit GR64:%vreg48 [2832r,2848r:0)  0@2832r w=inf
assigning %vreg48 to %RAX: AH [2832r,2848r:0)  0@2832r AL [2832r,2848r:0)  0@2832r

selectOrSplit GR64:%vreg127 [2896r,2912r:0)  0@2896r w=inf
assigning %vreg127 to %RAX: AH [2896r,2912r:0)  0@2896r AL [2896r,2912r:0)  0@2896r

selectOrSplit GR64:%vreg130 [2960r,2976r:0)  0@2960r w=inf
assigning %vreg130 to %RAX: AH [2960r,2976r:0)  0@2960r AL [2960r,2976r:0)  0@2960r

selectOrSplit GR64:%vreg202 [3024r,3040r:0)  0@3024r w=inf
assigning %vreg202 to %RAX: AH [3024r,3040r:0)  0@3024r AL [3024r,3040r:0)  0@3024r

selectOrSplit GR64:%vreg216 [3088r,3104r:0)  0@3088r w=inf
assigning %vreg216 to %RAX: AH [3088r,3104r:0)  0@3088r AL [3088r,3104r:0)  0@3088r

selectOrSplit GR64:%vreg215 [3104r,3248r:0)  0@3104r w=1.211875e-05
assigning %vreg215 to %RAX: AH [3104r,3248r:0)  0@3104r AL [3104r,3248r:0)  0@3104r

selectOrSplit GR64:%vreg213 [3120r,3136r:0)  0@3120r w=inf
assigning %vreg213 to %RCX: CH [3120r,3136r:0)  0@3120r CL [3120r,3136r:0)  0@3120r

selectOrSplit GR64:%vreg210 [3152r,3168r:0)  0@3152r w=inf
assigning %vreg210 to %RCX: CH [3152r,3168r:0)  0@3152r CL [3152r,3168r:0)  0@3152r

selectOrSplit GR64:%vreg219 [3344r,3360r:0)  0@3344r w=inf
assigning %vreg219 to %RAX: AH [3344r,3360r:0)  0@3344r AL [3344r,3360r:0)  0@3344r

selectOrSplit GR64:%vreg233 [3408r,3424r:0)  0@3408r w=inf
assigning %vreg233 to %RAX: AH [3408r,3424r:0)  0@3408r AL [3408r,3424r:0)  0@3408r

selectOrSplit GR64:%vreg232 [3424r,3568r:0)  0@3424r w=1.211875e-05
assigning %vreg232 to %RAX: AH [3424r,3568r:0)  0@3424r AL [3424r,3568r:0)  0@3424r

selectOrSplit GR64:%vreg230 [3440r,3456r:0)  0@3440r w=inf
assigning %vreg230 to %RCX: CH [3440r,3456r:0)  0@3440r CL [3440r,3456r:0)  0@3440r

selectOrSplit GR64:%vreg227 [3472r,3488r:0)  0@3472r w=inf
assigning %vreg227 to %RCX: CH [3472r,3488r:0)  0@3472r CL [3472r,3488r:0)  0@3472r

selectOrSplit GR64:%vreg236 [3664r,3680r:0)  0@3664r w=inf
assigning %vreg236 to %RAX: AH [3664r,3680r:0)  0@3664r AL [3664r,3680r:0)  0@3664r

selectOrSplit GR64:%vreg250 [3728r,3744r:0)  0@3728r w=inf
assigning %vreg250 to %RAX: AH [3728r,3744r:0)  0@3728r AL [3728r,3744r:0)  0@3728r

selectOrSplit GR64:%vreg249 [3744r,3888r:0)  0@3744r w=1.211875e-05
assigning %vreg249 to %RAX: AH [3744r,3888r:0)  0@3744r AL [3744r,3888r:0)  0@3744r

selectOrSplit GR64:%vreg247 [3760r,3776r:0)  0@3760r w=inf
assigning %vreg247 to %RCX: CH [3760r,3776r:0)  0@3760r CL [3760r,3776r:0)  0@3760r

selectOrSplit GR64:%vreg244 [3792r,3808r:0)  0@3792r w=inf
assigning %vreg244 to %RCX: CH [3792r,3808r:0)  0@3792r CL [3792r,3808r:0)  0@3792r

selectOrSplit GR64:%vreg263 [4032r,4048r:0)  0@4032r w=inf
assigning %vreg263 to %RAX: AH [4032r,4048r:0)  0@4032r AL [4032r,4048r:0)  0@4032r

selectOrSplit GR64:%vreg262 [4048r,4176r:0)  0@4048r w=1.248599e-05
assigning %vreg262 to %RAX: AH [4048r,4176r:0)  0@4048r AL [4048r,4176r:0)  0@4048r

selectOrSplit GR64:%vreg260 [4064r,4080r:0)  0@4064r w=inf
assigning %vreg260 to %RCX: CH [4064r,4080r:0)  0@4064r CL [4064r,4080r:0)  0@4064r

selectOrSplit GR64:%vreg199 [4320r,4336r:0)  0@4320r w=inf
assigning %vreg199 to %RAX: AH [4320r,4336r:0)  0@4320r AL [4320r,4336r:0)  0@4320r

selectOrSplit GR64:%vreg197 [4352r,4368r:0)  0@4352r w=inf
assigning %vreg197 to %RAX: AH [4352r,4368r:0)  0@4352r AL [4352r,4368r:0)  0@4352r

selectOrSplit GR64:%vreg195 [4384r,4400r:0)  0@4384r w=inf
assigning %vreg195 to %RAX: AH [4384r,4400r:0)  0@4384r AL [4384r,4400r:0)  0@4384r

selectOrSplit GR64:%vreg193 [4416r,4432r:0)  0@4416r w=inf
assigning %vreg193 to %RAX: AH [4416r,4432r:0)  0@4416r AL [4416r,4432r:0)  0@4416r

selectOrSplit GR32:%vreg191 [4448r,4480r:0)  0@4448r w=4.521675e-06
assigning %vreg191 to %EAX: AH [4448r,4480r:0)  0@4448r AL [4448r,4480r:0)  0@4448r

selectOrSplit GR64:%vreg190 [4464r,4480r:0)  0@4464r w=inf
assigning %vreg190 to %RCX: CH [4464r,4480r:0)  0@4464r CL [4464r,4480r:0)  0@4464r

selectOrSplit GR32:%vreg185 [4496r,4528r:0)[4528r,4560r:1)  0@4496r 1@4528r w=8.419670e-06
assigning %vreg185 to %EAX: AH [4496r,4528r:0)[4528r,4560r:1)  0@4496r 1@4528r AL [4496r,4528r:0)[4528r,4560r:1)  0@4496r 1@4528r

selectOrSplit GR64:%vreg183 [4544r,4560r:0)  0@4544r w=inf
assigning %vreg183 to %RCX: CH [4544r,4560r:0)  0@4544r CL [4544r,4560r:0)  0@4544r

selectOrSplit GR32:%vreg180 [4576r,4608r:0)  0@4576r w=4.521675e-06
assigning %vreg180 to %EAX: AH [4576r,4608r:0)  0@4576r AL [4576r,4608r:0)  0@4576r

selectOrSplit GR64:%vreg179 [4592r,4608r:0)  0@4592r w=inf
assigning %vreg179 to %RCX: CH [4592r,4608r:0)  0@4592r CL [4592r,4608r:0)  0@4592r

selectOrSplit GR32:%vreg176 [4624r,4656r:0)  0@4624r w=4.521675e-06
assigning %vreg176 to %EAX: AH [4624r,4656r:0)  0@4624r AL [4624r,4656r:0)  0@4624r

selectOrSplit GR64:%vreg175 [4640r,4656r:0)  0@4640r w=inf
assigning %vreg175 to %RCX: CH [4640r,4656r:0)  0@4640r CL [4640r,4656r:0)  0@4640r

selectOrSplit GR64:%vreg172 [4672r,4688r:0)  0@4672r w=inf
assigning %vreg172 to %RAX: AH [4672r,4688r:0)  0@4672r AL [4672r,4688r:0)  0@4672r

selectOrSplit GR64:%vreg169 [4688r,4736r:0)  0@4688r w=4.360186e-06
assigning %vreg169 to %RAX: AH [4688r,4736r:0)  0@4688r AL [4688r,4736r:0)  0@4688r

selectOrSplit GR64:%vreg167 [4720r,4736r:0)  0@4720r w=inf
assigning %vreg167 to %RCX: CH [4720r,4736r:0)  0@4720r CL [4720r,4736r:0)  0@4720r

selectOrSplit GR64:%vreg164 [4752r,4768r:0)  0@4752r w=inf
assigning %vreg164 to %RAX: AH [4752r,4768r:0)  0@4752r AL [4752r,4768r:0)  0@4752r

selectOrSplit GR64:%vreg161 [4768r,4816r:0)  0@4768r w=4.360186e-06
assigning %vreg161 to %RAX: AH [4768r,4816r:0)  0@4768r AL [4768r,4816r:0)  0@4768r

selectOrSplit GR64:%vreg159 [4800r,4816r:0)  0@4800r w=inf
assigning %vreg159 to %RCX: CH [4800r,4816r:0)  0@4800r CL [4800r,4816r:0)  0@4800r

selectOrSplit GR64:%vreg156 [4832r,4848r:0)  0@4832r w=inf
assigning %vreg156 to %RAX: AH [4832r,4848r:0)  0@4832r AL [4832r,4848r:0)  0@4832r

selectOrSplit GR64:%vreg154 [4864r,4880r:0)  0@4864r w=inf
assigning %vreg154 to %RAX: AH [4864r,4880r:0)  0@4864r AL [4864r,4880r:0)  0@4864r

selectOrSplit GR64:%vreg153 [4880r,4912r:0)  0@4880r w=4.521675e-06
assigning %vreg153 to %RAX: AH [4880r,4912r:0)  0@4880r AL [4880r,4912r:0)  0@4880r

selectOrSplit GR64:%vreg151 [4896r,4912r:0)  0@4896r w=inf
assigning %vreg151 to %RCX: CH [4896r,4912r:0)  0@4896r CL [4896r,4912r:0)  0@4896r

selectOrSplit GR64:%vreg147 [4928r,4976r:0)  0@4928r w=4.360186e-06
assigning %vreg147 to %RAX: AH [4928r,4976r:0)  0@4928r AL [4928r,4976r:0)  0@4928r

selectOrSplit GR64:%vreg145 [4960r,4976r:0)  0@4960r w=inf
assigning %vreg145 to %RCX: CH [4960r,4976r:0)  0@4960r CL [4960r,4976r:0)  0@4960r

selectOrSplit GR64:%vreg142 [4992r,5008r:0)  0@4992r w=inf
assigning %vreg142 to %RAX: AH [4992r,5008r:0)  0@4992r AL [4992r,5008r:0)  0@4992r

selectOrSplit GR64:%vreg140 [5024r,5040r:0)  0@5024r w=inf
assigning %vreg140 to %RAX: AH [5024r,5040r:0)  0@5024r AL [5024r,5040r:0)  0@5024r

selectOrSplit GR64:%vreg138 [5056r,5072r:0)  0@5056r w=inf
assigning %vreg138 to %RAX: AH [5056r,5072r:0)  0@5056r AL [5056r,5072r:0)  0@5056r

selectOrSplit GR64:%vreg136 [5088r,5104r:0)  0@5088r w=inf
assigning %vreg136 to %RAX: AH [5088r,5104r:0)  0@5088r AL [5088r,5104r:0)  0@5088r

********** STACK TRANSFORMATION METADATA **********
********** Function: BZ2_bzCompressInit
********** REGISTER MAP **********
[%vreg1 -> %RBX] GR64
[%vreg3 -> %R12D] GR32
[%vreg5 -> %R15D] GR32
[%vreg7 -> %R14D] GR32
[%vreg9 -> %EAX] GR32
[%vreg11 -> %RDI] GR64
[%vreg12 -> %RSI] GR64
[%vreg21 -> %RAX] GR64
[%vreg23 -> %RAX] GR64
[%vreg24 -> %RCX] GR64
[%vreg27 -> %RAX] GR64
[%vreg29 -> %RAX] GR64
[%vreg30 -> %RCX] GR64
[%vreg34 -> %RAX] GR64
[%vreg41 -> %RDI] GR64
[%vreg42 -> %RCX] GR64
[%vreg44 -> %RAX] GR64
[%vreg45 -> %RAX] GR64
[%vreg48 -> %RAX] GR64
[%vreg51 -> %RCX] GR64
[%vreg53 -> %RAX] GR64
[%vreg60 -> %RDI] GR64
[%vreg61 -> %RCX] GR64
[%vreg63 -> %RAX] GR64
[%vreg64 -> %RAX] GR64
[%vreg67 -> %RCX] GR64
[%vreg69 -> %RAX] GR64
[%vreg78 -> %RSI] GR64_with_sub_8bit
[%vreg82 -> %ECX] GR32
[%vreg85 -> %RDI] GR64
[%vreg86 -> %RCX] GR64
[%vreg88 -> %RAX] GR64
[%vreg89 -> %RAX] GR64
[%vreg92 -> %RCX] GR64
[%vreg94 -> %RAX] GR64
[%vreg103 -> %RSI] GR64_with_sub_8bit
[%vreg107 -> %RDI] GR64
[%vreg108 -> %RCX] GR64
[%vreg110 -> %RAX] GR64
[%vreg111 -> %RAX] GR64
[%vreg114 -> %EAX] GR32
[%vreg116 -> %RAX] GR64
[%vreg118 -> %RAX] GR64
[%vreg120 -> %RAX] GR64
[%vreg123 -> %RCX] GR64
[%vreg124 -> %RAX] GR64
[%vreg127 -> %RAX] GR64
[%vreg130 -> %RAX] GR64
[%vreg132 -> %RDI] GR64
[%vreg134 -> %RDI] GR64
[%vreg136 -> %RAX] GR64
[%vreg138 -> %RAX] GR64
[%vreg140 -> %RAX] GR64
[%vreg142 -> %RAX] GR64
[%vreg145 -> %RCX] GR64
[%vreg147 -> %RAX] GR64
[%vreg151 -> %RCX] GR64
[%vreg153 -> %RAX] GR64
[%vreg154 -> %RAX] GR64
[%vreg156 -> %RAX] GR64
[%vreg159 -> %RCX] GR64
[%vreg161 -> %RAX] GR64
[%vreg164 -> %RAX] GR64
[%vreg167 -> %RCX] GR64
[%vreg169 -> %RAX] GR64
[%vreg172 -> %RAX] GR64
[%vreg175 -> %RCX] GR64
[%vreg176 -> %EAX] GR32
[%vreg179 -> %RCX] GR64
[%vreg180 -> %EAX] GR32
[%vreg183 -> %RCX] GR64
[%vreg185 -> %EAX] GR32
[%vreg190 -> %RCX] GR64
[%vreg191 -> %EAX] GR32
[%vreg193 -> %RAX] GR64
[%vreg195 -> %RAX] GR64
[%vreg197 -> %RAX] GR64
[%vreg199 -> %RAX] GR64
[%vreg202 -> %RAX] GR64
[%vreg207 -> %RSI] GR64
[%vreg210 -> %RCX] GR64
[%vreg212 -> %RDI] GR64
[%vreg213 -> %RCX] GR64
[%vreg215 -> %RAX] GR64
[%vreg216 -> %RAX] GR64
[%vreg219 -> %RAX] GR64
[%vreg224 -> %RSI] GR64
[%vreg227 -> %RCX] GR64
[%vreg229 -> %RDI] GR64
[%vreg230 -> %RCX] GR64
[%vreg232 -> %RAX] GR64
[%vreg233 -> %RAX] GR64
[%vreg236 -> %RAX] GR64
[%vreg241 -> %RSI] GR64
[%vreg244 -> %RCX] GR64
[%vreg246 -> %RDI] GR64
[%vreg247 -> %RCX] GR64
[%vreg249 -> %RAX] GR64
[%vreg250 -> %RAX] GR64
[%vreg256 -> %RSI] GR64
[%vreg259 -> %RDI] GR64
[%vreg260 -> %RCX] GR64
[%vreg262 -> %RAX] GR64
[%vreg263 -> %RAX] GR64
[%vreg265 -> %EAX] GR32
[%vreg267 -> %RDI] GR64
[%vreg268 -> %RSI] GR64


Stackmap 0:
  STACKMAP 0, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, %vreg1, 0, <fi#1>, 0, %vreg5, 0, <fi#3>, 0, %vreg7, 0, <fi#4>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4) GR32:%vreg3,%vreg5,%vreg7 GR64:%vreg1

i32 %blockSize100k: in register %R12D (vreg 3)
i32* %blockSize100k.addr: in stack slot 2 (size: 4)
i32* %n: in stack slot 5 (size: 4)
i32* %retval: in stack slot 0 (size: 4)
%struct.EState** %s: in stack slot 6 (size: 8)
%struct.bz_stream* %strm: in register %RBX (vreg 1)
%struct.bz_stream** %strm.addr: in stack slot 1 (size: 8)
i32 %verbosity: in register %R15D (vreg 5)
i32* %verbosity.addr: in stack slot 3 (size: 4)
i32 %workFactor: in register %R14D (vreg 7)
i32* %workFactor.addr: in stack slot 4 (size: 4)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)

i32* %blockSize100k.addr: in stack slot 2 (size: 4)
i32* %n: in stack slot 5 (size: 4)
i32* %retval: in stack slot 0 (size: 4)
%struct.EState** %s: in stack slot 6 (size: 8)
%struct.bz_stream** %strm.addr: in stack slot 1 (size: 8)
i32* %verbosity.addr: in stack slot 3 (size: 4)
i32* %workFactor.addr: in stack slot 4 (size: 4)

Duplicate operand locations:


Stackmap 2:
  STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)

i32* %blockSize100k.addr: in stack slot 2 (size: 4)
i32* %n: in stack slot 5 (size: 4)
i32* %retval: in stack slot 0 (size: 4)
%struct.EState** %s: in stack slot 6 (size: 8)
%struct.bz_stream** %strm.addr: in stack slot 1 (size: 8)
i32* %verbosity.addr: in stack slot 3 (size: 4)
i32* %workFactor.addr: in stack slot 4 (size: 4)

Duplicate operand locations:


Stackmap 3:
  STACKMAP 3, 0, 0, <fi#2>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)

i32* %blockSize100k.addr: in stack slot 2 (size: 4)
i32* %n: in stack slot 5 (size: 4)
i32* %retval: in stack slot 0 (size: 4)
%struct.EState** %s: in stack slot 6 (size: 8)
%struct.bz_stream** %strm.addr: in stack slot 1 (size: 8)
i32* %verbosity.addr: in stack slot 3 (size: 4)
i32* %workFactor.addr: in stack slot 4 (size: 4)

Duplicate operand locations:


Stackmap 4:
  STACKMAP 4, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)

i32* %blockSize100k.addr: in stack slot 2 (size: 4)
i32* %retval: in stack slot 0 (size: 4)
%struct.EState** %s: in stack slot 6 (size: 8)
%struct.bz_stream** %strm.addr: in stack slot 1 (size: 8)
i32* %verbosity.addr: in stack slot 3 (size: 4)
i32* %workFactor.addr: in stack slot 4 (size: 4)

Duplicate operand locations:


Stackmap 5:
  STACKMAP 5, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)

i32* %blockSize100k.addr: in stack slot 2 (size: 4)
i32* %retval: in stack slot 0 (size: 4)
%struct.EState** %s: in stack slot 6 (size: 8)
%struct.bz_stream** %strm.addr: in stack slot 1 (size: 8)
i32* %verbosity.addr: in stack slot 3 (size: 4)
i32* %workFactor.addr: in stack slot 4 (size: 4)

Duplicate operand locations:


Stackmap 6:
  STACKMAP 6, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1]

i32* %retval: in stack slot 0 (size: 4)
%struct.EState** %s: in stack slot 6 (size: 8)
%struct.bz_stream** %strm.addr: in stack slot 1 (size: 8)

Duplicate operand locations:


Stackmap 7:
  STACKMAP 7, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1]

i32* %retval: in stack slot 0 (size: 4)
%struct.EState** %s: in stack slot 6 (size: 8)
%struct.bz_stream** %strm.addr: in stack slot 1 (size: 8)

Duplicate operand locations:


Stackmap 8:
  STACKMAP 8, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1]

i32* %retval: in stack slot 0 (size: 4)
%struct.EState** %s: in stack slot 6 (size: 8)
%struct.bz_stream** %strm.addr: in stack slot 1 (size: 8)

Duplicate operand locations:


Stackmap 9:
  STACKMAP 9, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)

i32* %retval: in stack slot 0 (size: 4)

Duplicate operand locations:


Stackmap 10:
  STACKMAP 10, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack6]

i32* %retval: in stack slot 0 (size: 4)
%struct.EState** %s: in stack slot 6 (size: 8)

Duplicate operand locations:


Stackmap 11:
  STACKMAP 11, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)

i32* %retval: in stack slot 0 (size: 4)

Duplicate operand locations:


Stackmap 12:
  STACKMAP 12, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)

i32* %retval: in stack slot 0 (size: 4)

Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, %vreg1, 0, <fi#1>, 0, %vreg5, 0, <fi#3>, 0, %vreg7, 0, <fi#4>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4) GR32:%vreg3,%vreg5,%vreg7 GR64:%vreg1
  -> Call instruction SlotIndex 240B, searching vregs 0 -> 269 and stack slots -1 -> 7

  STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)
  -> Call instruction SlotIndex 400B, searching vregs 0 -> 269 and stack slots -1 -> 7

  STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)
  -> Call instruction SlotIndex 1376B, searching vregs 0 -> 269 and stack slots -1 -> 7

  STACKMAP 3, 0, 0, <fi#2>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)
  -> Call instruction SlotIndex 1984B, searching vregs 0 -> 269 and stack slots -1 -> 7

  STACKMAP 4, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)
  -> Call instruction SlotIndex 2384B, searching vregs 0 -> 269 and stack slots -1 -> 7

  STACKMAP 5, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)
  -> Call instruction SlotIndex 2688B, searching vregs 0 -> 269 and stack slots -1 -> 7

  STACKMAP 6, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1]
  -> Call instruction SlotIndex 3248B, searching vregs 0 -> 269 and stack slots -1 -> 7

  STACKMAP 7, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1]
  -> Call instruction SlotIndex 3568B, searching vregs 0 -> 269 and stack slots -1 -> 7

  STACKMAP 8, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1]
  -> Call instruction SlotIndex 3888B, searching vregs 0 -> 269 and stack slots -1 -> 7

  STACKMAP 9, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
  -> Call instruction SlotIndex 4176B, searching vregs 0 -> 269 and stack slots -1 -> 7

  STACKMAP 10, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack6]
  -> Call instruction SlotIndex 5168B, searching vregs 0 -> 269 and stack slots -1 -> 7

  STACKMAP 11, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
  -> Call instruction SlotIndex 5296B, searching vregs 0 -> 269 and stack slots -1 -> 7

  STACKMAP 12, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
  -> Call instruction SlotIndex 5504B, searching vregs 0 -> 269 and stack slots -1 -> 7

********** REWRITE VIRTUAL REGISTERS **********
********** Function: BZ2_bzCompressInit
********** REGISTER MAP **********
[%vreg1 -> %RBX] GR64
[%vreg3 -> %R12D] GR32
[%vreg5 -> %R15D] GR32
[%vreg7 -> %R14D] GR32
[%vreg9 -> %EAX] GR32
[%vreg11 -> %RDI] GR64
[%vreg12 -> %RSI] GR64
[%vreg21 -> %RAX] GR64
[%vreg23 -> %RAX] GR64
[%vreg24 -> %RCX] GR64
[%vreg27 -> %RAX] GR64
[%vreg29 -> %RAX] GR64
[%vreg30 -> %RCX] GR64
[%vreg34 -> %RAX] GR64
[%vreg41 -> %RDI] GR64
[%vreg42 -> %RCX] GR64
[%vreg44 -> %RAX] GR64
[%vreg45 -> %RAX] GR64
[%vreg48 -> %RAX] GR64
[%vreg51 -> %RCX] GR64
[%vreg53 -> %RAX] GR64
[%vreg60 -> %RDI] GR64
[%vreg61 -> %RCX] GR64
[%vreg63 -> %RAX] GR64
[%vreg64 -> %RAX] GR64
[%vreg67 -> %RCX] GR64
[%vreg69 -> %RAX] GR64
[%vreg78 -> %RSI] GR64_with_sub_8bit
[%vreg82 -> %ECX] GR32
[%vreg85 -> %RDI] GR64
[%vreg86 -> %RCX] GR64
[%vreg88 -> %RAX] GR64
[%vreg89 -> %RAX] GR64
[%vreg92 -> %RCX] GR64
[%vreg94 -> %RAX] GR64
[%vreg103 -> %RSI] GR64_with_sub_8bit
[%vreg107 -> %RDI] GR64
[%vreg108 -> %RCX] GR64
[%vreg110 -> %RAX] GR64
[%vreg111 -> %RAX] GR64
[%vreg114 -> %EAX] GR32
[%vreg116 -> %RAX] GR64
[%vreg118 -> %RAX] GR64
[%vreg120 -> %RAX] GR64
[%vreg123 -> %RCX] GR64
[%vreg124 -> %RAX] GR64
[%vreg127 -> %RAX] GR64
[%vreg130 -> %RAX] GR64
[%vreg132 -> %RDI] GR64
[%vreg134 -> %RDI] GR64
[%vreg136 -> %RAX] GR64
[%vreg138 -> %RAX] GR64
[%vreg140 -> %RAX] GR64
[%vreg142 -> %RAX] GR64
[%vreg145 -> %RCX] GR64
[%vreg147 -> %RAX] GR64
[%vreg151 -> %RCX] GR64
[%vreg153 -> %RAX] GR64
[%vreg154 -> %RAX] GR64
[%vreg156 -> %RAX] GR64
[%vreg159 -> %RCX] GR64
[%vreg161 -> %RAX] GR64
[%vreg164 -> %RAX] GR64
[%vreg167 -> %RCX] GR64
[%vreg169 -> %RAX] GR64
[%vreg172 -> %RAX] GR64
[%vreg175 -> %RCX] GR64
[%vreg176 -> %EAX] GR32
[%vreg179 -> %RCX] GR64
[%vreg180 -> %EAX] GR32
[%vreg183 -> %RCX] GR64
[%vreg185 -> %EAX] GR32
[%vreg190 -> %RCX] GR64
[%vreg191 -> %EAX] GR32
[%vreg193 -> %RAX] GR64
[%vreg195 -> %RAX] GR64
[%vreg197 -> %RAX] GR64
[%vreg199 -> %RAX] GR64
[%vreg202 -> %RAX] GR64
[%vreg207 -> %RSI] GR64
[%vreg210 -> %RCX] GR64
[%vreg212 -> %RDI] GR64
[%vreg213 -> %RCX] GR64
[%vreg215 -> %RAX] GR64
[%vreg216 -> %RAX] GR64
[%vreg219 -> %RAX] GR64
[%vreg224 -> %RSI] GR64
[%vreg227 -> %RCX] GR64
[%vreg229 -> %RDI] GR64
[%vreg230 -> %RCX] GR64
[%vreg232 -> %RAX] GR64
[%vreg233 -> %RAX] GR64
[%vreg236 -> %RAX] GR64
[%vreg241 -> %RSI] GR64
[%vreg244 -> %RCX] GR64
[%vreg246 -> %RDI] GR64
[%vreg247 -> %RCX] GR64
[%vreg249 -> %RAX] GR64
[%vreg250 -> %RAX] GR64
[%vreg256 -> %RSI] GR64
[%vreg259 -> %RDI] GR64
[%vreg260 -> %RCX] GR64
[%vreg262 -> %RAX] GR64
[%vreg263 -> %RAX] GR64
[%vreg265 -> %EAX] GR32
[%vreg267 -> %RDI] GR64
[%vreg268 -> %RSI] GR64

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %ECX %EDX %ESI %RDI
16B		%vreg7<def> = COPY %ECX; GR32:%vreg7
32B		%vreg5<def> = COPY %EDX; GR32:%vreg5
48B		%vreg3<def> = COPY %ESI; GR32:%vreg3
64B		%vreg1<def> = COPY %RDI; GR64:%vreg1
144B		%vreg11<def> = MOV64ri <ga:@BZ2_bzCompressInit>; GR64:%vreg11
176B		%vreg12<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg12
192B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
208B		%RDI<def> = COPY %vreg11<kill>; GR64:%vreg11
224B		%RSI<def> = COPY %vreg12<kill>; GR64:%vreg12
240B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
256B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
272B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
288B		STACKMAP 0, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, %vreg1, 0, <fi#1>, 0, %vreg5, 0, <fi#3>, 0, %vreg7, 0, <fi#4>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4) GR32:%vreg3,%vreg5,%vreg7 GR64:%vreg1
304B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
320B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg1<kill>; mem:ST8[%strm.addr] GR64:%vreg1
336B		MOV32mr <fi#2>, 1, %noreg, 0, %noreg, %vreg3<kill>; mem:ST4[%blockSize100k.addr] GR32:%vreg3
352B		MOV32mr <fi#3>, 1, %noreg, 0, %noreg, %vreg5<kill>; mem:ST4[%verbosity.addr] GR32:%vreg5
368B		MOV32mr <fi#4>, 1, %noreg, 0, %noreg, %vreg7<kill>; mem:ST4[%workFactor.addr] GR32:%vreg7
384B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
400B		CALL64pcrel32 <ga:@bz_config_ok>, <regmask>, %RSP<imp-use>, %EAX<imp-def>
416B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
432B		%vreg9<def> = COPY %EAX; GR32:%vreg9
448B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
464B		STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)
480B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
496B		CMP32ri8 %vreg9<kill>, 0, %EFLAGS<imp-def>; GR32:%vreg9
512B		JNE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1
> %R14D<def> = COPY %ECX
> %R15D<def> = COPY %EDX
> %R12D<def> = COPY %ESI
> %RBX<def> = COPY %RDI
> %RDI<def> = MOV64ri <ga:@BZ2_bzCompressInit>
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 0, 0, %R12D, 0, <fi#2>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, %RBX, 0, <fi#1>, 0, %R15D, 0, <fi#3>, 0, %R14D, 0, <fi#4>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %RBX<kill>; mem:ST8[%strm.addr]
> MOV32mr <fi#2>, 1, %noreg, 0, %noreg, %R12D<kill>; mem:ST4[%blockSize100k.addr]
> MOV32mr <fi#3>, 1, %noreg, 0, %noreg, %R15D<kill>; mem:ST4[%verbosity.addr]
> MOV32mr <fi#4>, 1, %noreg, 0, %noreg, %R14D<kill>; mem:ST4[%workFactor.addr]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> CALL64pcrel32 <ga:@bz_config_ok>, <regmask>, %RSP<imp-use>, %EAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def> = COPY %EAX
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> CMP32ri8 %EAX<kill>, 0, %EFLAGS<imp-def>
> JNE_1 <BB#2>, %EFLAGS<imp-use,kill>
528B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
544B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -9; mem:ST4[%retval]
560B		JMP_1 <BB#29>
	    Successors according to CFG: BB#29
> MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -9; mem:ST4[%retval]
> JMP_1 <BB#29>
576B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0
592B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%strm.addr]
608B		JE_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#3
> CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%strm.addr]
> JE_1 <BB#7>, %EFLAGS<imp-use,kill>
624B	BB#3: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#2
640B		CMP32mi8 <fi#2>, 1, %noreg, 0, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%blockSize100k.addr]
656B		JL_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#4
> CMP32mi8 <fi#2>, 1, %noreg, 0, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%blockSize100k.addr]
> JL_1 <BB#7>, %EFLAGS<imp-use,kill>
672B	BB#4: derived from LLVM BB %lor.lhs.false.2
	    Predecessors according to CFG: BB#3
688B		CMP32mi8 <fi#2>, 1, %noreg, 0, %noreg, 9, %EFLAGS<imp-def>; mem:LD4[%blockSize100k.addr]
704B		JG_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#5
> CMP32mi8 <fi#2>, 1, %noreg, 0, %noreg, 9, %EFLAGS<imp-def>; mem:LD4[%blockSize100k.addr]
> JG_1 <BB#7>, %EFLAGS<imp-use,kill>
720B	BB#5: derived from LLVM BB %lor.lhs.false.4
	    Predecessors according to CFG: BB#4
736B		CMP32mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%workFactor.addr]
752B		JL_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#6
> CMP32mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%workFactor.addr]
> JL_1 <BB#7>, %EFLAGS<imp-use,kill>
768B	BB#6: derived from LLVM BB %lor.lhs.false.6
	    Predecessors according to CFG: BB#5
784B		CMP32mi <fi#4>, 1, %noreg, 0, %noreg, 250, %EFLAGS<imp-def>; mem:LD4[%workFactor.addr]
800B		JLE_1 <BB#8>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#8 BB#7
> CMP32mi <fi#4>, 1, %noreg, 0, %noreg, 250, %EFLAGS<imp-def>; mem:LD4[%workFactor.addr]
> JLE_1 <BB#8>, %EFLAGS<imp-use,kill>
816B	BB#7: derived from LLVM BB %if.then.8
	    Predecessors according to CFG: BB#2 BB#3 BB#4 BB#5 BB#6
832B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
848B		JMP_1 <BB#29>
	    Successors according to CFG: BB#29
> MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
> JMP_1 <BB#29>
864B	BB#8: derived from LLVM BB %if.end.9
	    Predecessors according to CFG: BB#6
880B		CMP32mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%workFactor.addr]
896B		JNE_1 <BB#10>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#10 BB#9
> CMP32mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%workFactor.addr]
> JNE_1 <BB#10>, %EFLAGS<imp-use,kill>
912B	BB#9: derived from LLVM BB %if.then.11
	    Predecessors according to CFG: BB#8
928B		MOV32mi <fi#4>, 1, %noreg, 0, %noreg, 30; mem:ST4[%workFactor.addr]
	    Successors according to CFG: BB#10
> MOV32mi <fi#4>, 1, %noreg, 0, %noreg, 30; mem:ST4[%workFactor.addr]
944B	BB#10: derived from LLVM BB %if.end.12
	    Predecessors according to CFG: BB#8 BB#9
960B		%vreg21<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg21
976B		CMP64mi8 %vreg21<kill>, 1, %noreg, 56, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzalloc] GR64:%vreg21
992B		JNE_1 <BB#12>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#12 BB#11
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr]
> CMP64mi8 %RAX<kill>, 1, %noreg, 56, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzalloc]
> JNE_1 <BB#12>, %EFLAGS<imp-use,kill>
1008B	BB#11: derived from LLVM BB %if.then.14
	    Predecessors according to CFG: BB#10
1024B		%vreg23<def> = MOV64ri <ga:@default_bzalloc>; GR64:%vreg23
1040B		%vreg24<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg24
1056B		MOV64mr %vreg24<kill>, 1, %noreg, 56, %noreg, %vreg23<kill>; mem:ST8[%bzalloc15] GR64:%vreg24,%vreg23
	    Successors according to CFG: BB#12
> %RAX<def> = MOV64ri <ga:@default_bzalloc>
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr]
> MOV64mr %RCX<kill>, 1, %noreg, 56, %noreg, %RAX<kill>; mem:ST8[%bzalloc15]
1072B	BB#12: derived from LLVM BB %if.end.16
	    Predecessors according to CFG: BB#10 BB#11
1088B		%vreg27<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg27
1104B		CMP64mi8 %vreg27<kill>, 1, %noreg, 64, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzfree] GR64:%vreg27
1120B		JNE_1 <BB#14>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#14 BB#13
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr]
> CMP64mi8 %RAX<kill>, 1, %noreg, 64, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzfree]
> JNE_1 <BB#14>, %EFLAGS<imp-use,kill>
1136B	BB#13: derived from LLVM BB %if.then.18
	    Predecessors according to CFG: BB#12
1152B		%vreg29<def> = MOV64ri <ga:@default_bzfree>; GR64:%vreg29
1168B		%vreg30<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg30
1184B		MOV64mr %vreg30<kill>, 1, %noreg, 64, %noreg, %vreg29<kill>; mem:ST8[%bzfree19] GR64:%vreg30,%vreg29
	    Successors according to CFG: BB#14
> %RAX<def> = MOV64ri <ga:@default_bzfree>
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr]
> MOV64mr %RCX<kill>, 1, %noreg, 64, %noreg, %RAX<kill>; mem:ST8[%bzfree19]
1200B	BB#14: derived from LLVM BB %if.end.20
	    Predecessors according to CFG: BB#12 BB#13
1248B		%vreg45<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg45
1264B		%vreg44<def> = MOV64rm %vreg45<kill>, 1, %noreg, 56, %noreg; mem:LD8[%bzalloc21] GR64:%vreg44,%vreg45
1280B		%vreg42<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg42
1296B		%vreg41<def> = MOV64rm %vreg42<kill>, 1, %noreg, 72, %noreg; mem:LD8[%opaque] GR64:%vreg41,%vreg42
1312B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1344B		%ESI<def> = MOV32ri 55768
1360B		%EDX<def> = MOV32ri 1
1368B		%RDI<def> = COPY %vreg41<kill>; GR64:%vreg41
1376B		CALL64r %vreg44<kill>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %EDX<imp-use>, %RAX<imp-def>; GR64:%vreg44
1392B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1408B		%vreg34<def> = COPY %RAX; GR64:%vreg34
1424B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1440B		STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)
1456B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1488B		MOV64mr <fi#6>, 1, %noreg, 0, %noreg, %vreg34<kill>; mem:ST8[%s] GR64:%vreg34
1504B		CMP64mi8 <fi#6>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%s]
1520B		JNE_1 <BB#16>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#16 BB#15
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 56, %noreg; mem:LD8[%bzalloc21]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr]
> %RDI<def> = MOV64rm %RCX<kill>, 1, %noreg, 72, %noreg; mem:LD8[%opaque]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %ESI<def> = MOV32ri 55768
> %EDX<def> = MOV32ri 1
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> CALL64r %RAX<kill>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %EDX<imp-use>, %RAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RAX<def> = COPY %RAX
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV64mr <fi#6>, 1, %noreg, 0, %noreg, %RAX<kill>; mem:ST8[%s]
> CMP64mi8 <fi#6>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%s]
> JNE_1 <BB#16>, %EFLAGS<imp-use,kill>
1536B	BB#15: derived from LLVM BB %if.then.24
	    Predecessors according to CFG: BB#14
1552B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -3; mem:ST4[%retval]
1568B		JMP_1 <BB#29>
	    Successors according to CFG: BB#29
> MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -3; mem:ST4[%retval]
> JMP_1 <BB#29>
1584B	BB#16: derived from LLVM BB %if.end.25
	    Predecessors according to CFG: BB#14
1616B		%vreg124<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg124
1632B		%vreg123<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg123
1648B		MOV64mr %vreg123<kill>, 1, %noreg, 0, %noreg, %vreg124<kill>; mem:ST8[%strm26] GR64:%vreg123,%vreg124
1664B		%vreg120<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg120
1680B		MOV64mi32 %vreg120<kill>, 1, %noreg, 24, %noreg, 0; mem:ST8[%arr1] GR64:%vreg120
1696B		%vreg118<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg118
1712B		MOV64mi32 %vreg118<kill>, 1, %noreg, 32, %noreg, 0; mem:ST8[%arr2] GR64:%vreg118
1728B		%vreg116<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg116
1744B		MOV64mi32 %vreg116<kill>, 1, %noreg, 40, %noreg, 0; mem:ST8[%ftab] GR64:%vreg116
1760B		%vreg114<def> = IMUL32rmi <fi#2>, 1, %noreg, 0, %noreg, 100000, %EFLAGS<imp-def,dead>; mem:LD4[%blockSize100k.addr] GR32:%vreg114
1776B		MOV32mr <fi#5>, 1, %noreg, 0, %noreg, %vreg114<kill>; mem:ST4[%n] GR32:%vreg114
1792B		%vreg111<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg111
1808B		%vreg110<def> = MOV64rm %vreg111<kill>, 1, %noreg, 56, %noreg; mem:LD8[%bzalloc27] GR64:%vreg110,%vreg111
1824B		%vreg108<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg108
1840B		%vreg107<def> = MOV64rm %vreg108<kill>, 1, %noreg, 72, %noreg; mem:LD8[%opaque28] GR64:%vreg107,%vreg108
1856B		%vreg103<def> = MOVSX64rm32 <fi#5>, 1, %noreg, 0, %noreg; mem:LD4[%n] GR64_with_sub_8bit:%vreg103
1888B		%vreg103<def,tied1> = SHL64ri %vreg103<kill,tied0>, 2, %EFLAGS<imp-def,dead>; GR64_with_sub_8bit:%vreg103
1920B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1968B		%EDX<def> = MOV32ri 1
1972B		%RDI<def> = COPY %vreg107<kill>; GR64:%vreg107
1976B		%ESI<def> = COPY %vreg103:sub_32bit<kill>; GR64_with_sub_8bit:%vreg103
1984B		CALL64r %vreg110<kill>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %EDX<imp-use>, %RAX<imp-def>; GR64:%vreg110
2000B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2016B		%vreg94<def> = COPY %RAX; GR64:%vreg94
2048B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2064B		STACKMAP 3, 0, 0, <fi#2>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)
2080B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2112B		%vreg92<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg92
2128B		MOV64mr %vreg92<kill>, 1, %noreg, 24, %noreg, %vreg94<kill>; mem:ST8[%arr132] GR64:%vreg92,%vreg94
2144B		%vreg89<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg89
2160B		%vreg88<def> = MOV64rm %vreg89<kill>, 1, %noreg, 56, %noreg; mem:LD8[%bzalloc33] GR64:%vreg88,%vreg89
2176B		%vreg86<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg86
2192B		%vreg85<def> = MOV64rm %vreg86<kill>, 1, %noreg, 72, %noreg; mem:LD8[%opaque34] GR64:%vreg85,%vreg86
2208B		%vreg82<def> = MOV32rm <fi#5>, 1, %noreg, 0, %noreg; mem:LD4[%n] GR32:%vreg82
2240B		%vreg82<def,tied1> = ADD32ri8 %vreg82<kill,tied0>, 34, %EFLAGS<imp-def,dead>; GR32:%vreg82
2256B		%vreg78<def> = MOVSX64rr32 %vreg82<kill>; GR64_with_sub_8bit:%vreg78 GR32:%vreg82
2288B		%vreg78<def,tied1> = SHL64ri %vreg78<kill,tied0>, 2, %EFLAGS<imp-def,dead>; GR64_with_sub_8bit:%vreg78
2320B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2368B		%EDX<def> = MOV32ri 1
2372B		%RDI<def> = COPY %vreg85<kill>; GR64:%vreg85
2376B		%ESI<def> = COPY %vreg78:sub_32bit<kill>; GR64_with_sub_8bit:%vreg78
2384B		CALL64r %vreg88<kill>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %EDX<imp-use>, %RAX<imp-def>; GR64:%vreg88
2400B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2416B		%vreg69<def> = COPY %RAX; GR64:%vreg69
2464B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2480B		STACKMAP 4, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)
2496B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2528B		%vreg67<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg67
2544B		MOV64mr %vreg67<kill>, 1, %noreg, 32, %noreg, %vreg69<kill>; mem:ST8[%arr239] GR64:%vreg67,%vreg69
2560B		%vreg64<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg64
2576B		%vreg63<def> = MOV64rm %vreg64<kill>, 1, %noreg, 56, %noreg; mem:LD8[%bzalloc40] GR64:%vreg63,%vreg64
2592B		%vreg61<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg61
2608B		%vreg60<def> = MOV64rm %vreg61<kill>, 1, %noreg, 72, %noreg; mem:LD8[%opaque41] GR64:%vreg60,%vreg61
2624B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2656B		%ESI<def> = MOV32ri 262148
2672B		%EDX<def> = MOV32ri 1
2680B		%RDI<def> = COPY %vreg60<kill>; GR64:%vreg60
2688B		CALL64r %vreg63<kill>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %EDX<imp-use>, %RAX<imp-def>; GR64:%vreg63
2704B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2720B		%vreg53<def> = COPY %RAX; GR64:%vreg53
2736B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2752B		STACKMAP 5, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)
2768B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2800B		%vreg51<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg51
2816B		MOV64mr %vreg51<kill>, 1, %noreg, 40, %noreg, %vreg53<kill>; mem:ST8[%ftab43] GR64:%vreg51,%vreg53
2832B		%vreg48<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg48
2848B		CMP64mi8 %vreg48<kill>, 1, %noreg, 24, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%arr144] GR64:%vreg48
2864B		JE_1 <BB#19>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#19 BB#17
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr]
> %RCX<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> MOV64mr %RCX<kill>, 1, %noreg, 0, %noreg, %RAX<kill>; mem:ST8[%strm26]
> %RAX<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> MOV64mi32 %RAX<kill>, 1, %noreg, 24, %noreg, 0; mem:ST8[%arr1]
> %RAX<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> MOV64mi32 %RAX<kill>, 1, %noreg, 32, %noreg, 0; mem:ST8[%arr2]
> %RAX<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> MOV64mi32 %RAX<kill>, 1, %noreg, 40, %noreg, 0; mem:ST8[%ftab]
> %EAX<def> = IMUL32rmi <fi#2>, 1, %noreg, 0, %noreg, 100000, %EFLAGS<imp-def,dead>; mem:LD4[%blockSize100k.addr]
> MOV32mr <fi#5>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%n]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 56, %noreg; mem:LD8[%bzalloc27]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr]
> %RDI<def> = MOV64rm %RCX<kill>, 1, %noreg, 72, %noreg; mem:LD8[%opaque28]
> %RSI<def> = MOVSX64rm32 <fi#5>, 1, %noreg, 0, %noreg; mem:LD4[%n]
> %RSI<def,tied1> = SHL64ri %RSI<kill,tied0>, 2, %EFLAGS<imp-def,dead>
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EDX<def> = MOV32ri 1
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %ESI<def> = COPY %ESI, %RSI<imp-use,kill>
Deleting identity copy.
> CALL64r %RAX<kill>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %EDX<imp-use>, %RAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RAX<def> = COPY %RAX
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 3, 0, 0, <fi#2>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RCX<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> MOV64mr %RCX<kill>, 1, %noreg, 24, %noreg, %RAX<kill>; mem:ST8[%arr132]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 56, %noreg; mem:LD8[%bzalloc33]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr]
> %RDI<def> = MOV64rm %RCX<kill>, 1, %noreg, 72, %noreg; mem:LD8[%opaque34]
> %ECX<def> = MOV32rm <fi#5>, 1, %noreg, 0, %noreg; mem:LD4[%n]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 34, %EFLAGS<imp-def,dead>
> %RSI<def> = MOVSX64rr32 %ECX<kill>
> %RSI<def,tied1> = SHL64ri %RSI<kill,tied0>, 2, %EFLAGS<imp-def,dead>
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EDX<def> = MOV32ri 1
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %ESI<def> = COPY %ESI, %RSI<imp-use,kill>
Deleting identity copy.
> CALL64r %RAX<kill>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %EDX<imp-use>, %RAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RAX<def> = COPY %RAX
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 4, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RCX<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> MOV64mr %RCX<kill>, 1, %noreg, 32, %noreg, %RAX<kill>; mem:ST8[%arr239]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 56, %noreg; mem:LD8[%bzalloc40]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr]
> %RDI<def> = MOV64rm %RCX<kill>, 1, %noreg, 72, %noreg; mem:LD8[%opaque41]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %ESI<def> = MOV32ri 262148
> %EDX<def> = MOV32ri 1
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> CALL64r %RAX<kill>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %EDX<imp-use>, %RAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RAX<def> = COPY %RAX
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 5, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RCX<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> MOV64mr %RCX<kill>, 1, %noreg, 40, %noreg, %RAX<kill>; mem:ST8[%ftab43]
> %RAX<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> CMP64mi8 %RAX<kill>, 1, %noreg, 24, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%arr144]
> JE_1 <BB#19>, %EFLAGS<imp-use,kill>
2880B	BB#17: derived from LLVM BB %lor.lhs.false.47
	    Predecessors according to CFG: BB#16
2896B		%vreg127<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg127
2912B		CMP64mi8 %vreg127<kill>, 1, %noreg, 32, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%arr248] GR64:%vreg127
2928B		JE_1 <BB#19>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#19 BB#18
> %RAX<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> CMP64mi8 %RAX<kill>, 1, %noreg, 32, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%arr248]
> JE_1 <BB#19>, %EFLAGS<imp-use,kill>
2944B	BB#18: derived from LLVM BB %lor.lhs.false.51
	    Predecessors according to CFG: BB#17
2960B		%vreg130<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg130
2976B		CMP64mi8 %vreg130<kill>, 1, %noreg, 40, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%ftab52] GR64:%vreg130
2992B		JNE_1 <BB#28>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#28 BB#19
> %RAX<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> CMP64mi8 %RAX<kill>, 1, %noreg, 40, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%ftab52]
> JNE_1 <BB#28>, %EFLAGS<imp-use,kill>
3008B	BB#19: derived from LLVM BB %if.then.55
	    Predecessors according to CFG: BB#16 BB#17 BB#18
3024B		%vreg202<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg202
3040B		CMP64mi8 %vreg202<kill>, 1, %noreg, 24, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%arr156] GR64:%vreg202
3056B		JE_1 <BB#21>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#21 BB#20
> %RAX<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> CMP64mi8 %RAX<kill>, 1, %noreg, 24, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%arr156]
> JE_1 <BB#21>, %EFLAGS<imp-use,kill>
3072B	BB#20: derived from LLVM BB %if.then.59
	    Predecessors according to CFG: BB#19
3088B		%vreg216<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg216
3104B		%vreg215<def> = MOV64rm %vreg216<kill>, 1, %noreg, 64, %noreg; mem:LD8[%bzfree60] GR64:%vreg215,%vreg216
3120B		%vreg213<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg213
3136B		%vreg212<def> = MOV64rm %vreg213<kill>, 1, %noreg, 72, %noreg; mem:LD8[%opaque61] GR64:%vreg212,%vreg213
3152B		%vreg210<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg210
3168B		%vreg207<def> = MOV64rm %vreg210<kill>, 1, %noreg, 24, %noreg; mem:LD8[%arr162] GR64:%vreg207,%vreg210
3200B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3216B		%RDI<def> = COPY %vreg212<kill>; GR64:%vreg212
3232B		%RSI<def> = COPY %vreg207<kill>; GR64:%vreg207
3248B		CALL64r %vreg215<kill>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>; GR64:%vreg215
3264B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3280B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3296B		STACKMAP 6, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1]
3312B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#21
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 64, %noreg; mem:LD8[%bzfree60]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr]
> %RDI<def> = MOV64rm %RCX<kill>, 1, %noreg, 72, %noreg; mem:LD8[%opaque61]
> %RCX<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> %RSI<def> = MOV64rm %RCX<kill>, 1, %noreg, 24, %noreg; mem:LD8[%arr162]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64r %RAX<kill>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 6, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3328B	BB#21: derived from LLVM BB %if.end.63
	    Predecessors according to CFG: BB#19 BB#20
3344B		%vreg219<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg219
3360B		CMP64mi8 %vreg219<kill>, 1, %noreg, 32, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%arr264] GR64:%vreg219
3376B		JE_1 <BB#23>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#23 BB#22
> %RAX<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> CMP64mi8 %RAX<kill>, 1, %noreg, 32, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%arr264]
> JE_1 <BB#23>, %EFLAGS<imp-use,kill>
3392B	BB#22: derived from LLVM BB %if.then.67
	    Predecessors according to CFG: BB#21
3408B		%vreg233<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg233
3424B		%vreg232<def> = MOV64rm %vreg233<kill>, 1, %noreg, 64, %noreg; mem:LD8[%bzfree68] GR64:%vreg232,%vreg233
3440B		%vreg230<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg230
3456B		%vreg229<def> = MOV64rm %vreg230<kill>, 1, %noreg, 72, %noreg; mem:LD8[%opaque69] GR64:%vreg229,%vreg230
3472B		%vreg227<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg227
3488B		%vreg224<def> = MOV64rm %vreg227<kill>, 1, %noreg, 32, %noreg; mem:LD8[%arr270] GR64:%vreg224,%vreg227
3520B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3536B		%RDI<def> = COPY %vreg229<kill>; GR64:%vreg229
3552B		%RSI<def> = COPY %vreg224<kill>; GR64:%vreg224
3568B		CALL64r %vreg232<kill>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>; GR64:%vreg232
3584B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3600B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3616B		STACKMAP 7, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1]
3632B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#23
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 64, %noreg; mem:LD8[%bzfree68]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr]
> %RDI<def> = MOV64rm %RCX<kill>, 1, %noreg, 72, %noreg; mem:LD8[%opaque69]
> %RCX<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> %RSI<def> = MOV64rm %RCX<kill>, 1, %noreg, 32, %noreg; mem:LD8[%arr270]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64r %RAX<kill>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 7, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3648B	BB#23: derived from LLVM BB %if.end.71
	    Predecessors according to CFG: BB#21 BB#22
3664B		%vreg236<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg236
3680B		CMP64mi8 %vreg236<kill>, 1, %noreg, 40, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%ftab72] GR64:%vreg236
3696B		JE_1 <BB#25>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#25 BB#24
> %RAX<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> CMP64mi8 %RAX<kill>, 1, %noreg, 40, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%ftab72]
> JE_1 <BB#25>, %EFLAGS<imp-use,kill>
3712B	BB#24: derived from LLVM BB %if.then.75
	    Predecessors according to CFG: BB#23
3728B		%vreg250<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg250
3744B		%vreg249<def> = MOV64rm %vreg250<kill>, 1, %noreg, 64, %noreg; mem:LD8[%bzfree76] GR64:%vreg249,%vreg250
3760B		%vreg247<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg247
3776B		%vreg246<def> = MOV64rm %vreg247<kill>, 1, %noreg, 72, %noreg; mem:LD8[%opaque77] GR64:%vreg246,%vreg247
3792B		%vreg244<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg244
3808B		%vreg241<def> = MOV64rm %vreg244<kill>, 1, %noreg, 40, %noreg; mem:LD8[%ftab78] GR64:%vreg241,%vreg244
3840B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3856B		%RDI<def> = COPY %vreg246<kill>; GR64:%vreg246
3872B		%RSI<def> = COPY %vreg241<kill>; GR64:%vreg241
3888B		CALL64r %vreg249<kill>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>; GR64:%vreg249
3904B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3920B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3936B		STACKMAP 8, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1]
3952B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#25
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 64, %noreg; mem:LD8[%bzfree76]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr]
> %RDI<def> = MOV64rm %RCX<kill>, 1, %noreg, 72, %noreg; mem:LD8[%opaque77]
> %RCX<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> %RSI<def> = MOV64rm %RCX<kill>, 1, %noreg, 40, %noreg; mem:LD8[%ftab78]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64r %RAX<kill>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 8, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack6] LD8[FixedStack1]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3968B	BB#25: derived from LLVM BB %if.end.79
	    Predecessors according to CFG: BB#23 BB#24
3984B		CMP64mi8 <fi#6>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%s]
4000B		JE_1 <BB#27>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#27 BB#26
> CMP64mi8 <fi#6>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%s]
> JE_1 <BB#27>, %EFLAGS<imp-use,kill>
4016B	BB#26: derived from LLVM BB %if.then.82
	    Predecessors according to CFG: BB#25
4032B		%vreg263<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg263
4048B		%vreg262<def> = MOV64rm %vreg263<kill>, 1, %noreg, 64, %noreg; mem:LD8[%bzfree83] GR64:%vreg262,%vreg263
4064B		%vreg260<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg260
4080B		%vreg259<def> = MOV64rm %vreg260<kill>, 1, %noreg, 72, %noreg; mem:LD8[%opaque84] GR64:%vreg259,%vreg260
4096B		%vreg256<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg256
4128B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4144B		%RDI<def> = COPY %vreg259<kill>; GR64:%vreg259
4160B		%RSI<def> = COPY %vreg256<kill>; GR64:%vreg256
4176B		CALL64r %vreg262<kill>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>; GR64:%vreg262
4192B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4208B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4224B		STACKMAP 9, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
4240B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#27
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 64, %noreg; mem:LD8[%bzfree83]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr]
> %RDI<def> = MOV64rm %RCX<kill>, 1, %noreg, 72, %noreg; mem:LD8[%opaque84]
> %RSI<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64r %RAX<kill>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 9, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4256B	BB#27: derived from LLVM BB %if.end.85
	    Predecessors according to CFG: BB#25 BB#26
4272B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -3; mem:ST4[%retval]
4288B		JMP_1 <BB#29>
	    Successors according to CFG: BB#29
> MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -3; mem:ST4[%retval]
> JMP_1 <BB#29>
4304B	BB#28: derived from LLVM BB %if.end.86
	    Predecessors according to CFG: BB#18
4320B		%vreg199<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg199
4336B		MOV32mi %vreg199<kill>, 1, %noreg, 660, %noreg, 0; mem:ST4[%blockNo] GR64:%vreg199
4352B		%vreg197<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg197
4368B		MOV32mi %vreg197<kill>, 1, %noreg, 12, %noreg, 2; mem:ST4[%state] GR64:%vreg197
4384B		%vreg195<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg195
4400B		MOV32mi %vreg195<kill>, 1, %noreg, 8, %noreg, 2; mem:ST4[%mode] GR64:%vreg195
4416B		%vreg193<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg193
4432B		MOV32mi %vreg193<kill>, 1, %noreg, 652, %noreg, 0; mem:ST4[%combinedCRC] GR64:%vreg193
4448B		%vreg191<def> = MOV32rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD4[%blockSize100k.addr] GR32:%vreg191
4464B		%vreg190<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg190
4480B		MOV32mr %vreg190<kill>, 1, %noreg, 664, %noreg, %vreg191<kill>; mem:ST4[%blockSize100k87] GR64:%vreg190 GR32:%vreg191
4496B		%vreg185<def> = IMUL32rmi <fi#2>, 1, %noreg, 0, %noreg, 100000, %EFLAGS<imp-def,dead>; mem:LD4[%blockSize100k.addr] GR32:%vreg185
4528B		%vreg185<def,tied1> = SUB32ri8 %vreg185<kill,tied0>, 19, %EFLAGS<imp-def,dead>; GR32:%vreg185
4544B		%vreg183<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg183
4560B		MOV32mr %vreg183<kill>, 1, %noreg, 112, %noreg, %vreg185<kill>; mem:ST4[%nblockMAX] GR64:%vreg183 GR32:%vreg185
4576B		%vreg180<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%verbosity.addr] GR32:%vreg180
4592B		%vreg179<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg179
4608B		MOV32mr %vreg179<kill>, 1, %noreg, 656, %noreg, %vreg180<kill>; mem:ST4[%verbosity89] GR64:%vreg179 GR32:%vreg180
4624B		%vreg176<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%workFactor.addr] GR32:%vreg176
4640B		%vreg175<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg175
4656B		MOV32mr %vreg175<kill>, 1, %noreg, 88, %noreg, %vreg176<kill>; mem:ST4[%workFactor90] GR64:%vreg175 GR32:%vreg176
4672B		%vreg172<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg172
4688B		%vreg169<def> = MOV64rm %vreg172<kill>, 1, %noreg, 32, %noreg; mem:LD8[%arr291] GR64:%vreg169,%vreg172
4720B		%vreg167<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg167
4736B		MOV64mr %vreg167<kill>, 1, %noreg, 64, %noreg, %vreg169<kill>; mem:ST8[%block] GR64:%vreg167,%vreg169
4752B		%vreg164<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg164
4768B		%vreg161<def> = MOV64rm %vreg164<kill>, 1, %noreg, 24, %noreg; mem:LD8[%arr192] GR64:%vreg161,%vreg164
4800B		%vreg159<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg159
4816B		MOV64mr %vreg159<kill>, 1, %noreg, 72, %noreg, %vreg161<kill>; mem:ST8[%mtfv] GR64:%vreg159,%vreg161
4832B		%vreg156<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg156
4848B		MOV64mi32 %vreg156<kill>, 1, %noreg, 80, %noreg, 0; mem:ST8[%zbits] GR64:%vreg156
4864B		%vreg154<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg154
4880B		%vreg153<def> = MOV64rm %vreg154<kill>, 1, %noreg, 24, %noreg; mem:LD8[%arr193] GR64:%vreg153,%vreg154
4896B		%vreg151<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg151
4912B		MOV64mr %vreg151<kill>, 1, %noreg, 56, %noreg, %vreg153<kill>; mem:ST8[%ptr] GR64:%vreg151,%vreg153
4928B		%vreg147<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg147
4960B		%vreg145<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg145
4976B		MOV64mr %vreg145<kill>, 1, %noreg, 48, %noreg, %vreg147<kill>; mem:ST8[%state94] GR64:%vreg145,%vreg147
4992B		%vreg142<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg142
5008B		MOV32mi %vreg142<kill>, 1, %noreg, 12, %noreg, 0; mem:ST4[%total_in_lo32] GR64:%vreg142
5024B		%vreg140<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg140
5040B		MOV32mi %vreg140<kill>, 1, %noreg, 16, %noreg, 0; mem:ST4[%total_in_hi32] GR64:%vreg140
5056B		%vreg138<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg138
5072B		MOV32mi %vreg138<kill>, 1, %noreg, 36, %noreg, 0; mem:ST4[%total_out_lo32] GR64:%vreg138
5088B		%vreg136<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg136
5104B		MOV32mi %vreg136<kill>, 1, %noreg, 40, %noreg, 0; mem:ST4[%total_out_hi32] GR64:%vreg136
5120B		%vreg134<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg134
5136B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5152B		%RDI<def> = COPY %vreg134<kill>; GR64:%vreg134
5168B		CALL64pcrel32 <ga:@init_RL>, <regmask>, %RSP<imp-use>, %RDI<imp-use>
5184B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5200B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5216B		STACKMAP 10, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack6]
5232B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5248B		%vreg132<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg132
5264B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5280B		%RDI<def> = COPY %vreg132<kill>; GR64:%vreg132
5296B		CALL64pcrel32 <ga:@prepare_new_block>, <regmask>, %RSP<imp-use>, %RDI<imp-use>
5312B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5328B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5344B		STACKMAP 11, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
5360B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5376B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
	    Successors according to CFG: BB#29
> %RAX<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> MOV32mi %RAX<kill>, 1, %noreg, 660, %noreg, 0; mem:ST4[%blockNo]
> %RAX<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> MOV32mi %RAX<kill>, 1, %noreg, 12, %noreg, 2; mem:ST4[%state]
> %RAX<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> MOV32mi %RAX<kill>, 1, %noreg, 8, %noreg, 2; mem:ST4[%mode]
> %RAX<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> MOV32mi %RAX<kill>, 1, %noreg, 652, %noreg, 0; mem:ST4[%combinedCRC]
> %EAX<def> = MOV32rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD4[%blockSize100k.addr]
> %RCX<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> MOV32mr %RCX<kill>, 1, %noreg, 664, %noreg, %EAX<kill>; mem:ST4[%blockSize100k87]
> %EAX<def> = IMUL32rmi <fi#2>, 1, %noreg, 0, %noreg, 100000, %EFLAGS<imp-def,dead>; mem:LD4[%blockSize100k.addr]
> %EAX<def,tied1> = SUB32ri8 %EAX<kill,tied0>, 19, %EFLAGS<imp-def,dead>
> %RCX<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> MOV32mr %RCX<kill>, 1, %noreg, 112, %noreg, %EAX<kill>; mem:ST4[%nblockMAX]
> %EAX<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%verbosity.addr]
> %RCX<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> MOV32mr %RCX<kill>, 1, %noreg, 656, %noreg, %EAX<kill>; mem:ST4[%verbosity89]
> %EAX<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%workFactor.addr]
> %RCX<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> MOV32mr %RCX<kill>, 1, %noreg, 88, %noreg, %EAX<kill>; mem:ST4[%workFactor90]
> %RAX<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 32, %noreg; mem:LD8[%arr291]
> %RCX<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> MOV64mr %RCX<kill>, 1, %noreg, 64, %noreg, %RAX<kill>; mem:ST8[%block]
> %RAX<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 24, %noreg; mem:LD8[%arr192]
> %RCX<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> MOV64mr %RCX<kill>, 1, %noreg, 72, %noreg, %RAX<kill>; mem:ST8[%mtfv]
> %RAX<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> MOV64mi32 %RAX<kill>, 1, %noreg, 80, %noreg, 0; mem:ST8[%zbits]
> %RAX<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 24, %noreg; mem:LD8[%arr193]
> %RCX<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> MOV64mr %RCX<kill>, 1, %noreg, 56, %noreg, %RAX<kill>; mem:ST8[%ptr]
> %RAX<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr]
> MOV64mr %RCX<kill>, 1, %noreg, 48, %noreg, %RAX<kill>; mem:ST8[%state94]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 12, %noreg, 0; mem:ST4[%total_in_lo32]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 16, %noreg, 0; mem:ST4[%total_in_hi32]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 36, %noreg, 0; mem:ST4[%total_out_lo32]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 40, %noreg, 0; mem:ST4[%total_out_hi32]
> %RDI<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@init_RL>, <regmask>, %RSP<imp-use>, %RDI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 10, 0, 0, <fi#0>, 0, 0, <fi#6>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack6]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@prepare_new_block>, <regmask>, %RSP<imp-use>, %RDI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 11, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
5392B	BB#29: derived from LLVM BB %return
	    Predecessors according to CFG: BB#1 BB#28 BB#27 BB#15 BB#7
5408B		%vreg267<def> = MOV64ri <ga:@BZ2_bzCompressInit>; GR64:%vreg267
5440B		%vreg268<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg268
5456B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5472B		%RDI<def> = COPY %vreg267<kill>; GR64:%vreg267
5488B		%RSI<def> = COPY %vreg268<kill>; GR64:%vreg268
5504B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
5520B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5536B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5552B		STACKMAP 12, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
5568B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5584B		%vreg265<def> = MOV32rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD4[%retval] GR32:%vreg265
5600B		%EAX<def> = COPY %vreg265<kill>; GR32:%vreg265
5616B		RETQ %EAX<imp-use>
> %RDI<def> = MOV64ri <ga:@BZ2_bzCompressInit>
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 12, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def> = MOV32rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD4[%retval]
> %EAX<def> = COPY %EAX<kill>
Deleting identity copy.
> RETQ %EAX<imp-use>
Computing live-in reg-units in ABI blocks.
Created 0 new intervals.
********** INTERVALS **********
%vreg0 [320r,384r:0)  0@320r
%vreg1 [144r,160r:0)  0@144r
%vreg2 [160r,256r:0)  0@160r
%vreg3 [224r,272r:0)  0@224r
%vreg4 [16r,32r:0)  0@16r
%vreg5 [32r,80r:0)  0@32r
%vreg6 [48r,96r:0)  0@48r
RegMasks: 112r 288r
********** MACHINEINSTRS **********
# Machine code for function bz_config_ok: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]

0B	BB#0: derived from LLVM BB %entry
16B		%vreg4<def> = MOV64ri <ga:@bz_config_ok>; GR64:%vreg4
32B		%vreg5<def> = COPY %vreg4; GR64:%vreg5,%vreg4
48B		%vreg6<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg6
64B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
80B		%RDI<def> = COPY %vreg5; GR64:%vreg5
96B		%RSI<def> = COPY %vreg6; GR64:%vreg6
112B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use,kill>, %RSI<imp-use,kill>
128B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
144B		%vreg1<def> = MOV64ri <ga:@bz_config_ok>; GR64:%vreg1
160B		%vreg2<def> = COPY %vreg1; GR64:%vreg2,%vreg1
176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
192B		STACKMAP 0, 0, ...
208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		%vreg3<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg3
240B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
256B		%RDI<def> = COPY %vreg2; GR64:%vreg2
272B		%RSI<def> = COPY %vreg3; GR64:%vreg3
288B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use,kill>, %RSI<imp-use,kill>
304B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
320B		%vreg0<def> = MOV32ri 1; GR32:%vreg0
336B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
352B		STACKMAP 1, 0, ...
368B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
384B		%EAX<def> = COPY %vreg0; GR32:%vreg0
400B		RETQ %EAX<imp-use,kill>

# End machine code for function bz_config_ok.

********** SIMPLE REGISTER COALESCING **********
********** Function: bz_config_ok
********** JOINING INTERVALS ***********
entry:
80B	%RDI<def> = COPY %vreg5; GR64:%vreg5
	Considering merging %vreg5 with %RDI
	Can only merge into reserved registers.
96B	%RSI<def> = COPY %vreg6; GR64:%vreg6
	Considering merging %vreg6 with %RSI
	Can only merge into reserved registers.
256B	%RDI<def> = COPY %vreg2; GR64:%vreg2
	Considering merging %vreg2 with %RDI
	Can only merge into reserved registers.
272B	%RSI<def> = COPY %vreg3; GR64:%vreg3
	Considering merging %vreg3 with %RSI
	Can only merge into reserved registers.
384B	%EAX<def> = COPY %vreg0; GR32:%vreg0
	Considering merging %vreg0 with %EAX
	Can only merge into reserved registers.
Remat: %EAX<def> = MOV32ri 1
Shrink: %vreg0 [320r,384r:0)  0@320r
All defs dead: 320r	%vreg0<def,dead> = MOV32ri 1; GR32:%vreg0
Shrunk: %vreg0 [320r,320d:0)  0@320r
Deleting dead def 320r	%vreg0<def,dead> = MOV32ri 1; GR32:%vreg0
32B	%vreg5<def> = COPY %vreg4; GR64:%vreg5,%vreg4
	Considering merging to GR64 with %vreg4 in %vreg5
		RHS = %vreg4 [16r,32r:0)  0@16r
		LHS = %vreg5 [32r,80r:0)  0@32r
		merge %vreg5:0@32r into %vreg4:0@16r --> @16r
		erased:	32r	%vreg5<def> = COPY %vreg4; GR64:%vreg5,%vreg4
		updated: 16B	%vreg5<def> = MOV64ri <ga:@bz_config_ok>; GR64:%vreg5
	Success: %vreg4 -> %vreg5
	Result = %vreg5 [16r,80r:0)  0@16r
160B	%vreg2<def> = COPY %vreg1; GR64:%vreg2,%vreg1
	Considering merging to GR64 with %vreg1 in %vreg2
		RHS = %vreg1 [144r,160r:0)  0@144r
		LHS = %vreg2 [160r,256r:0)  0@160r
		merge %vreg2:0@160r into %vreg1:0@144r --> @144r
		erased:	160r	%vreg2<def> = COPY %vreg1; GR64:%vreg2,%vreg1
		updated: 144B	%vreg2<def> = MOV64ri <ga:@bz_config_ok>; GR64:%vreg2
	Success: %vreg1 -> %vreg2
	Result = %vreg2 [144r,256r:0)  0@144r
80B	%RDI<def> = COPY %vreg5; GR64:%vreg5
	Considering merging %vreg5 with %RDI
	Can only merge into reserved registers.
256B	%RDI<def> = COPY %vreg2; GR64:%vreg2
	Considering merging %vreg2 with %RDI
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
%vreg2 [144r,256r:0)  0@144r
%vreg3 [224r,272r:0)  0@224r
%vreg5 [16r,80r:0)  0@16r
%vreg6 [48r,96r:0)  0@48r
RegMasks: 112r 288r
********** MACHINEINSTRS **********
# Machine code for function bz_config_ok: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]

0B	BB#0: derived from LLVM BB %entry
16B		%vreg5<def> = MOV64ri <ga:@bz_config_ok>; GR64:%vreg5
48B		%vreg6<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg6
64B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
80B		%RDI<def> = COPY %vreg5; GR64:%vreg5
96B		%RSI<def> = COPY %vreg6; GR64:%vreg6
112B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use,kill>, %RSI<imp-use,kill>
128B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
144B		%vreg2<def> = MOV64ri <ga:@bz_config_ok>; GR64:%vreg2
176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
192B		STACKMAP 0, 0, ...
208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		%vreg3<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg3
240B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
256B		%RDI<def> = COPY %vreg2; GR64:%vreg2
272B		%RSI<def> = COPY %vreg3; GR64:%vreg3
288B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use,kill>, %RSI<imp-use,kill>
304B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
336B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
352B		STACKMAP 1, 0, ...
368B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
384B		%EAX<def> = MOV32ri 1
400B		RETQ %EAX<imp-use,kill>

# End machine code for function bz_config_ok.

********** GREEDY REGISTER ALLOCATION **********
********** Function: bz_config_ok
********** INTERVALS **********
%vreg2 [144r,256r:0)  0@144r
%vreg3 [224r,272r:0)  0@224r
%vreg5 [16r,80r:0)  0@16r
%vreg6 [48r,96r:0)  0@48r
RegMasks: 112r 288r
********** MACHINEINSTRS **********
# Machine code for function bz_config_ok: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]

0B	BB#0: derived from LLVM BB %entry
16B		%vreg5<def> = MOV64ri <ga:@bz_config_ok>; GR64:%vreg5
48B		%vreg6<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg6
64B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
80B		%RDI<def> = COPY %vreg5; GR64:%vreg5
96B		%RSI<def> = COPY %vreg6; GR64:%vreg6
112B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use,kill>, %RSI<imp-use,kill>
128B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
144B		%vreg2<def> = MOV64ri <ga:@bz_config_ok>; GR64:%vreg2
176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
192B		STACKMAP 0, 0, ...
208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		%vreg3<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg3
240B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
256B		%RDI<def> = COPY %vreg2; GR64:%vreg2
272B		%RSI<def> = COPY %vreg3; GR64:%vreg3
288B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use,kill>, %RSI<imp-use,kill>
304B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
336B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
352B		STACKMAP 1, 0, ...
368B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
384B		%EAX<def> = MOV32ri 1
400B		RETQ %EAX<imp-use,kill>

# End machine code for function bz_config_ok.


selectOrSplit GR64:%vreg5 [16r,80r:0)  0@16r w=2.176724e-03
hints: %RDI
assigning %vreg5 to %RDI: DIL [16r,80r:0)  0@16r

selectOrSplit GR64:%vreg6 [48r,96r:0)  0@48r w=4.508928e-03
hints: %RSI
assigning %vreg6 to %RSI: SIL [48r,96r:0)  0@48r

selectOrSplit GR64:%vreg2 [144r,256r:0)  0@144r w=1.972656e-03
hints: %RDI
assigning %vreg2 to %RDI: DIL [144r,256r:0)  0@144r

selectOrSplit GR64:%vreg3 [224r,272r:0)  0@224r w=4.508928e-03
hints: %RSI
assigning %vreg3 to %RSI: SIL [224r,272r:0)  0@224r

********** STACK TRANSFORMATION METADATA **********
********** Function: bz_config_ok
********** REGISTER MAP **********
[%vreg2 -> %RDI] GR64
[%vreg3 -> %RSI] GR64
[%vreg5 -> %RDI] GR64
[%vreg6 -> %RSI] GR64


Stackmap 0:
  STACKMAP 0, 0, ...


Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, ...


Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, ...
  -> Call instruction SlotIndex 112B, searching vregs 0 -> 7 and stack slots -1 -> 0

  STACKMAP 1, 0, ...
  -> Call instruction SlotIndex 288B, searching vregs 0 -> 7 and stack slots -1 -> 0

********** REWRITE VIRTUAL REGISTERS **********
********** Function: bz_config_ok
********** REGISTER MAP **********
[%vreg2 -> %RDI] GR64
[%vreg3 -> %RSI] GR64
[%vreg5 -> %RDI] GR64
[%vreg6 -> %RSI] GR64

0B	BB#0: derived from LLVM BB %entry
16B		%vreg5<def> = MOV64ri <ga:@bz_config_ok>; GR64:%vreg5
48B		%vreg6<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg6
64B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
80B		%RDI<def> = COPY %vreg5<kill>; GR64:%vreg5
96B		%RSI<def> = COPY %vreg6<kill>; GR64:%vreg6
112B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
128B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
144B		%vreg2<def> = MOV64ri <ga:@bz_config_ok>; GR64:%vreg2
176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
192B		STACKMAP 0, 0, ...
208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		%vreg3<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg3
240B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
256B		%RDI<def> = COPY %vreg2<kill>; GR64:%vreg2
272B		%RSI<def> = COPY %vreg3<kill>; GR64:%vreg3
288B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
304B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
336B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
352B		STACKMAP 1, 0, ...
368B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
384B		%EAX<def> = MOV32ri 1
400B		RETQ %EAX<imp-use,kill>
> %RDI<def> = MOV64ri <ga:@bz_config_ok>
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = MOV64ri <ga:@bz_config_ok>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 0, 0, ...
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 1, 0, ...
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def> = MOV32ri 1
> RETQ %EAX<imp-use,kill>
Computing live-in reg-units in ABI blocks.
0B	BB#0 DIL#0 SIL#0 DH#0 DL#0
Created 4 new intervals.
********** INTERVALS **********
DH [0B,16r:0)  0@0B-phi
DIL [0B,48r:0)[176r,208r:1)[416r,432r:2)[624r,656r:3)  0@0B-phi 1@176r 2@416r 3@624r
DL [0B,16r:0)  0@0B-phi
SIL [0B,32r:0)[192r,208r:1)[640r,656r:2)  0@0B-phi 1@192r 2@640r
%vreg0 [48r,64r:0)  0@48r
%vreg1 [64r,288r:0)  0@64r
%vreg2 [32r,80r:0)  0@32r
%vreg3 [80r,304r:0)  0@80r
%vreg4 [16r,96r:0)  0@16r
%vreg5 [96r,320r:0)  0@96r
%vreg7 [480r,496r:0)  0@480r
%vreg8 [496r,624r:0)  0@496r
%vreg9 [592r,640r:0)  0@592r
%vreg10 [576r,736r:0)  0@576r
%vreg13 [464r,560r:0)  0@464r
%vreg15 [384r,416r:0)  0@384r
%vreg18 [352r,368r:0)[368r,384r:1)  0@352r 1@368r
%vreg19 [336r,352r:0)  0@336r
%vreg20 [112r,128r:0)  0@112r
%vreg21 [128r,176r:0)  0@128r
%vreg22 [144r,192r:0)  0@144r
RegMasks: 208r 432r 656r
********** MACHINEINSTRS **********
# Machine code for function default_bzalloc: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=8, align=8, at location [SP+8]
  fi#1: size=4, align=4, at location [SP+8]
  fi#2: size=4, align=4, at location [SP+8]
  fi#3: size=8, align=8, at location [SP+8]
Function Live Ins: %RDI in %vreg0, %ESI in %vreg2, %EDX in %vreg4

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI %ESI %EDX
16B		%vreg4<def> = COPY %EDX; GR32:%vreg4
32B		%vreg2<def> = COPY %ESI; GR32:%vreg2
48B		%vreg0<def> = COPY %RDI; GR64:%vreg0
64B		%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
80B		%vreg3<def> = COPY %vreg2; GR32:%vreg3,%vreg2
96B		%vreg5<def> = COPY %vreg4; GR32:%vreg5,%vreg4
112B		%vreg20<def> = MOV64ri <ga:@default_bzalloc>; GR64:%vreg20
128B		%vreg21<def> = COPY %vreg20; GR64:%vreg21,%vreg20
144B		%vreg22<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg22
160B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		%RDI<def> = COPY %vreg21; GR64:%vreg21
192B		%RSI<def> = COPY %vreg22; GR64:%vreg22
208B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
224B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
240B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
256B		STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, %vreg5, 0, <fi#2>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1](align=4) LD8[FixedStack0] LD8[FixedStack2](align=4) LD8[FixedStack3] GR32:%vreg3,%vreg5 GR64:%vreg1
272B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
288B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%opaque.addr] GR64:%vreg1
304B		MOV32mr <fi#1>, 1, %noreg, 0, %noreg, %vreg3; mem:ST4[%items.addr] GR32:%vreg3
320B		MOV32mr <fi#2>, 1, %noreg, 0, %noreg, %vreg5; mem:ST4[%size.addr] GR32:%vreg5
336B		%vreg19<def> = MOV32rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD4[%items.addr] GR32:%vreg19
352B		%vreg18<def> = COPY %vreg19; GR32:%vreg18,%vreg19
368B		%vreg18<def,tied1> = IMUL32rm %vreg18<tied0>, <fi#2>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%size.addr] GR32:%vreg18
384B		%vreg15<def> = MOVSX64rr32 %vreg18; GR64:%vreg15 GR32:%vreg18
400B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
416B		%RDI<def> = COPY %vreg15; GR64:%vreg15
432B		CALL64pcrel32 <ga:@malloc>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RAX<imp-def>
448B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
464B		%vreg13<def> = COPY %RAX<kill>; GR64:%vreg13
480B		%vreg7<def> = MOV64ri <ga:@default_bzalloc>; GR64:%vreg7
496B		%vreg8<def> = COPY %vreg7; GR64:%vreg8,%vreg7
512B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
528B		STACKMAP 1, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack3]
544B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
560B		MOV64mr <fi#3>, 1, %noreg, 0, %noreg, %vreg13; mem:ST8[%v] GR64:%vreg13
576B		%vreg10<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%v] GR64:%vreg10
592B		%vreg9<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg9
608B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
624B		%RDI<def> = COPY %vreg8; GR64:%vreg8
640B		%RSI<def> = COPY %vreg9; GR64:%vreg9
656B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
672B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
688B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
704B		STACKMAP 2, 0, %vreg10, ...; GR64:%vreg10
720B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
736B		%RAX<def> = COPY %vreg10; GR64:%vreg10
752B		RETQ %RAX<imp-use,kill>

# End machine code for function default_bzalloc.

********** SIMPLE REGISTER COALESCING **********
********** Function: default_bzalloc
********** JOINING INTERVALS ***********
entry:
16B	%vreg4<def> = COPY %EDX; GR32:%vreg4
	Considering merging %vreg4 with %EDX
	Can only merge into reserved registers.
32B	%vreg2<def> = COPY %ESI; GR32:%vreg2
	Considering merging %vreg2 with %ESI
	Can only merge into reserved registers.
48B	%vreg0<def> = COPY %RDI; GR64:%vreg0
	Considering merging %vreg0 with %RDI
	Can only merge into reserved registers.
176B	%RDI<def> = COPY %vreg21; GR64:%vreg21
	Considering merging %vreg21 with %RDI
	Can only merge into reserved registers.
192B	%RSI<def> = COPY %vreg22; GR64:%vreg22
	Considering merging %vreg22 with %RSI
	Can only merge into reserved registers.
416B	%RDI<def> = COPY %vreg15; GR64:%vreg15
	Considering merging %vreg15 with %RDI
	Can only merge into reserved registers.
464B	%vreg13<def> = COPY %RAX<kill>; GR64:%vreg13
	Considering merging %vreg13 with %RAX
	Can only merge into reserved registers.
624B	%RDI<def> = COPY %vreg8; GR64:%vreg8
	Considering merging %vreg8 with %RDI
	Can only merge into reserved registers.
640B	%RSI<def> = COPY %vreg9; GR64:%vreg9
	Considering merging %vreg9 with %RSI
	Can only merge into reserved registers.
736B	%RAX<def> = COPY %vreg10; GR64:%vreg10
	Considering merging %vreg10 with %RAX
	Can only merge into reserved registers.
64B	%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
	Considering merging to GR64 with %vreg0 in %vreg1
		RHS = %vreg0 [48r,64r:0)  0@48r
		LHS = %vreg1 [64r,288r:0)  0@64r
		merge %vreg1:0@64r into %vreg0:0@48r --> @48r
		erased:	64r	%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
		updated: 48B	%vreg1<def> = COPY %RDI; GR64:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [48r,288r:0)  0@48r
80B	%vreg3<def> = COPY %vreg2; GR32:%vreg3,%vreg2
	Considering merging to GR32 with %vreg2 in %vreg3
		RHS = %vreg2 [32r,80r:0)  0@32r
		LHS = %vreg3 [80r,304r:0)  0@80r
		merge %vreg3:0@80r into %vreg2:0@32r --> @32r
		erased:	80r	%vreg3<def> = COPY %vreg2; GR32:%vreg3,%vreg2
		updated: 32B	%vreg3<def> = COPY %ESI; GR32:%vreg3
	Success: %vreg2 -> %vreg3
	Result = %vreg3 [32r,304r:0)  0@32r
96B	%vreg5<def> = COPY %vreg4; GR32:%vreg5,%vreg4
	Considering merging to GR32 with %vreg4 in %vreg5
		RHS = %vreg4 [16r,96r:0)  0@16r
		LHS = %vreg5 [96r,320r:0)  0@96r
		merge %vreg5:0@96r into %vreg4:0@16r --> @16r
		erased:	96r	%vreg5<def> = COPY %vreg4; GR32:%vreg5,%vreg4
		updated: 16B	%vreg5<def> = COPY %EDX; GR32:%vreg5
	Success: %vreg4 -> %vreg5
	Result = %vreg5 [16r,320r:0)  0@16r
128B	%vreg21<def> = COPY %vreg20; GR64:%vreg21,%vreg20
	Considering merging to GR64 with %vreg20 in %vreg21
		RHS = %vreg20 [112r,128r:0)  0@112r
		LHS = %vreg21 [128r,176r:0)  0@128r
		merge %vreg21:0@128r into %vreg20:0@112r --> @112r
		erased:	128r	%vreg21<def> = COPY %vreg20; GR64:%vreg21,%vreg20
		updated: 112B	%vreg21<def> = MOV64ri <ga:@default_bzalloc>; GR64:%vreg21
	Success: %vreg20 -> %vreg21
	Result = %vreg21 [112r,176r:0)  0@112r
352B	%vreg18<def> = COPY %vreg19; GR32:%vreg18,%vreg19
	Considering merging to GR32 with %vreg19 in %vreg18
		RHS = %vreg19 [336r,352r:0)  0@336r
		LHS = %vreg18 [352r,368r:0)[368r,384r:1)  0@352r 1@368r
		merge %vreg18:0@352r into %vreg19:0@336r --> @336r
		erased:	352r	%vreg18<def> = COPY %vreg19; GR32:%vreg18,%vreg19
		updated: 336B	%vreg18<def> = MOV32rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD4[%items.addr] GR32:%vreg18
	Success: %vreg19 -> %vreg18
	Result = %vreg18 [336r,368r:0)[368r,384r:1)  0@336r 1@368r
496B	%vreg8<def> = COPY %vreg7; GR64:%vreg8,%vreg7
	Considering merging to GR64 with %vreg7 in %vreg8
		RHS = %vreg7 [480r,496r:0)  0@480r
		LHS = %vreg8 [496r,624r:0)  0@496r
		merge %vreg8:0@496r into %vreg7:0@480r --> @480r
		erased:	496r	%vreg8<def> = COPY %vreg7; GR64:%vreg8,%vreg7
		updated: 480B	%vreg8<def> = MOV64ri <ga:@default_bzalloc>; GR64:%vreg8
	Success: %vreg7 -> %vreg8
	Result = %vreg8 [480r,624r:0)  0@480r
176B	%RDI<def> = COPY %vreg21; GR64:%vreg21
	Considering merging %vreg21 with %RDI
	Can only merge into reserved registers.
624B	%RDI<def> = COPY %vreg8; GR64:%vreg8
	Considering merging %vreg8 with %RDI
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
DH [0B,16r:0)  0@0B-phi
DIL [0B,48r:0)[176r,208r:1)[416r,432r:2)[624r,656r:3)  0@0B-phi 1@176r 2@416r 3@624r
DL [0B,16r:0)  0@0B-phi
SIL [0B,32r:0)[192r,208r:1)[640r,656r:2)  0@0B-phi 1@192r 2@640r
%vreg1 [48r,288r:0)  0@48r
%vreg3 [32r,304r:0)  0@32r
%vreg5 [16r,320r:0)  0@16r
%vreg8 [480r,624r:0)  0@480r
%vreg9 [592r,640r:0)  0@592r
%vreg10 [576r,736r:0)  0@576r
%vreg13 [464r,560r:0)  0@464r
%vreg15 [384r,416r:0)  0@384r
%vreg18 [336r,368r:0)[368r,384r:1)  0@336r 1@368r
%vreg21 [112r,176r:0)  0@112r
%vreg22 [144r,192r:0)  0@144r
RegMasks: 208r 432r 656r
********** MACHINEINSTRS **********
# Machine code for function default_bzalloc: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=8, align=8, at location [SP+8]
  fi#1: size=4, align=4, at location [SP+8]
  fi#2: size=4, align=4, at location [SP+8]
  fi#3: size=8, align=8, at location [SP+8]
Function Live Ins: %RDI in %vreg0, %ESI in %vreg2, %EDX in %vreg4

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI %ESI %EDX
16B		%vreg5<def> = COPY %EDX; GR32:%vreg5
32B		%vreg3<def> = COPY %ESI; GR32:%vreg3
48B		%vreg1<def> = COPY %RDI; GR64:%vreg1
112B		%vreg21<def> = MOV64ri <ga:@default_bzalloc>; GR64:%vreg21
144B		%vreg22<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg22
160B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		%RDI<def> = COPY %vreg21; GR64:%vreg21
192B		%RSI<def> = COPY %vreg22; GR64:%vreg22
208B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
224B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
240B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
256B		STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, %vreg5, 0, <fi#2>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1](align=4) LD8[FixedStack0] LD8[FixedStack2](align=4) LD8[FixedStack3] GR32:%vreg3,%vreg5 GR64:%vreg1
272B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
288B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%opaque.addr] GR64:%vreg1
304B		MOV32mr <fi#1>, 1, %noreg, 0, %noreg, %vreg3; mem:ST4[%items.addr] GR32:%vreg3
320B		MOV32mr <fi#2>, 1, %noreg, 0, %noreg, %vreg5; mem:ST4[%size.addr] GR32:%vreg5
336B		%vreg18<def> = MOV32rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD4[%items.addr] GR32:%vreg18
368B		%vreg18<def,tied1> = IMUL32rm %vreg18<tied0>, <fi#2>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%size.addr] GR32:%vreg18
384B		%vreg15<def> = MOVSX64rr32 %vreg18; GR64:%vreg15 GR32:%vreg18
400B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
416B		%RDI<def> = COPY %vreg15; GR64:%vreg15
432B		CALL64pcrel32 <ga:@malloc>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RAX<imp-def>
448B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
464B		%vreg13<def> = COPY %RAX<kill>; GR64:%vreg13
480B		%vreg8<def> = MOV64ri <ga:@default_bzalloc>; GR64:%vreg8
512B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
528B		STACKMAP 1, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack3]
544B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
560B		MOV64mr <fi#3>, 1, %noreg, 0, %noreg, %vreg13; mem:ST8[%v] GR64:%vreg13
576B		%vreg10<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%v] GR64:%vreg10
592B		%vreg9<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg9
608B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
624B		%RDI<def> = COPY %vreg8; GR64:%vreg8
640B		%RSI<def> = COPY %vreg9; GR64:%vreg9
656B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
672B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
688B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
704B		STACKMAP 2, 0, %vreg10, ...; GR64:%vreg10
720B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
736B		%RAX<def> = COPY %vreg10; GR64:%vreg10
752B		RETQ %RAX<imp-use,kill>

# End machine code for function default_bzalloc.

********** GREEDY REGISTER ALLOCATION **********
********** Function: default_bzalloc
********** INTERVALS **********
DH [0B,16r:0)  0@0B-phi
DIL [0B,48r:0)[176r,208r:1)[416r,432r:2)[624r,656r:3)  0@0B-phi 1@176r 2@416r 3@624r
DL [0B,16r:0)  0@0B-phi
SIL [0B,32r:0)[192r,208r:1)[640r,656r:2)  0@0B-phi 1@192r 2@640r
%vreg1 [48r,288r:0)  0@48r
%vreg3 [32r,304r:0)  0@32r
%vreg5 [16r,320r:0)  0@16r
%vreg8 [480r,624r:0)  0@480r
%vreg9 [592r,640r:0)  0@592r
%vreg10 [576r,736r:0)  0@576r
%vreg13 [464r,560r:0)  0@464r
%vreg15 [384r,416r:0)  0@384r
%vreg18 [336r,368r:0)[368r,384r:1)  0@336r 1@368r
%vreg21 [112r,176r:0)  0@112r
%vreg22 [144r,192r:0)  0@144r
RegMasks: 208r 432r 656r
********** MACHINEINSTRS **********
# Machine code for function default_bzalloc: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=8, align=8, at location [SP+8]
  fi#1: size=4, align=4, at location [SP+8]
  fi#2: size=4, align=4, at location [SP+8]
  fi#3: size=8, align=8, at location [SP+8]
Function Live Ins: %RDI in %vreg0, %ESI in %vreg2, %EDX in %vreg4

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI %ESI %EDX
16B		%vreg5<def> = COPY %EDX; GR32:%vreg5
32B		%vreg3<def> = COPY %ESI; GR32:%vreg3
48B		%vreg1<def> = COPY %RDI; GR64:%vreg1
112B		%vreg21<def> = MOV64ri <ga:@default_bzalloc>; GR64:%vreg21
144B		%vreg22<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg22
160B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		%RDI<def> = COPY %vreg21; GR64:%vreg21
192B		%RSI<def> = COPY %vreg22; GR64:%vreg22
208B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
224B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
240B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
256B		STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, %vreg5, 0, <fi#2>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1](align=4) LD8[FixedStack0] LD8[FixedStack2](align=4) LD8[FixedStack3] GR32:%vreg3,%vreg5 GR64:%vreg1
272B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
288B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%opaque.addr] GR64:%vreg1
304B		MOV32mr <fi#1>, 1, %noreg, 0, %noreg, %vreg3; mem:ST4[%items.addr] GR32:%vreg3
320B		MOV32mr <fi#2>, 1, %noreg, 0, %noreg, %vreg5; mem:ST4[%size.addr] GR32:%vreg5
336B		%vreg18<def> = MOV32rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD4[%items.addr] GR32:%vreg18
368B		%vreg18<def,tied1> = IMUL32rm %vreg18<tied0>, <fi#2>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%size.addr] GR32:%vreg18
384B		%vreg15<def> = MOVSX64rr32 %vreg18; GR64:%vreg15 GR32:%vreg18
400B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
416B		%RDI<def> = COPY %vreg15; GR64:%vreg15
432B		CALL64pcrel32 <ga:@malloc>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RAX<imp-def>
448B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
464B		%vreg13<def> = COPY %RAX<kill>; GR64:%vreg13
480B		%vreg8<def> = MOV64ri <ga:@default_bzalloc>; GR64:%vreg8
512B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
528B		STACKMAP 1, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack3]
544B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
560B		MOV64mr <fi#3>, 1, %noreg, 0, %noreg, %vreg13; mem:ST8[%v] GR64:%vreg13
576B		%vreg10<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%v] GR64:%vreg10
592B		%vreg9<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg9
608B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
624B		%RDI<def> = COPY %vreg8; GR64:%vreg8
640B		%RSI<def> = COPY %vreg9; GR64:%vreg9
656B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
672B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
688B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
704B		STACKMAP 2, 0, %vreg10, ...; GR64:%vreg10
720B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
736B		%RAX<def> = COPY %vreg10; GR64:%vreg10
752B		RETQ %RAX<imp-use,kill>

# End machine code for function default_bzalloc.


selectOrSplit GR32:%vreg5 [16r,320r:0)  0@16r w=4.303977e-03
hints: %EDX
missed hint %EDX
assigning %vreg5 to %EBX: BH [16r,320r:0)  0@16r BL [16r,320r:0)  0@16r

selectOrSplit GR32:%vreg3 [32r,304r:0)  0@32r w=4.508928e-03
hints: %ESI
missed hint %ESI
%R14D is available at cost 1
Only trying the first 10 regs.
should evict: %vreg5 [16r,320r:0)  0@16r w= 4.303977e-03
hints: %EDX
can reassign: %vreg5 [16r,320r:0)  0@16r from %EBX to %EDX
should evict: %vreg5 [16r,320r:0)  0@16r w= 4.303977e-03
hints: %EDX
can reassign: %vreg5 [16r,320r:0)  0@16r from %EBX to %EDX
evicting %EBX interference: Cascade 1
unassigning %vreg5 from %EBX: BH BL
assigning %vreg3 to %EBX: BH [32r,304r:0)  0@32r BL [32r,304r:0)  0@32r
queuing new interval: %vreg5 [16r,320r:0)  0@16r

selectOrSplit GR32:%vreg5 [16r,320r:0)  0@16r w=4.303977e-03
hints: %EDX
missed hint %EDX
%R14D is available at cost 1
Only trying the first 10 regs.
assigning %vreg5 to %R14D: R14B [16r,320r:0)  0@16r

selectOrSplit GR64:%vreg1 [48r,288r:0)  0@48r w=4.734375e-03
hints: %RDI
missed hint %RDI
%R15 is available at cost 1
Only trying the first 10 regs.
should evict: %vreg3 [32r,304r:0)  0@32r w= 4.508928e-03
hints: %ESI
can reassign: %vreg3 [32r,304r:0)  0@32r from %RBX to %ESI
should evict: %vreg3 [32r,304r:0)  0@32r w= 4.508928e-03
hints: %ESI
can reassign: %vreg3 [32r,304r:0)  0@32r from %RBX to %ESI
evicting %RBX interference: Cascade 2
unassigning %vreg3 from %EBX: BH BL
assigning %vreg1 to %RBX: BH [48r,288r:0)  0@48r BL [48r,288r:0)  0@48r
queuing new interval: %vreg3 [32r,304r:0)  0@32r

selectOrSplit GR32:%vreg3 [32r,304r:0)  0@32r w=4.508928e-03
hints: %ESI
missed hint %ESI
%R15D is available at cost 1
Only trying the first 10 regs.
assigning %vreg3 to %R15D: R15B [32r,304r:0)  0@32r

selectOrSplit GR64:%vreg21 [112r,176r:0)  0@112r w=2.176724e-03
hints: %RDI
assigning %vreg21 to %RDI: DIL [112r,176r:0)  0@112r

selectOrSplit GR64:%vreg22 [144r,192r:0)  0@144r w=4.508928e-03
hints: %RSI
assigning %vreg22 to %RSI: SIL [144r,192r:0)  0@144r

selectOrSplit GR64:%vreg15 [384r,416r:0)  0@384r w=4.675926e-03
hints: %RDI
assigning %vreg15 to %RDI: DIL [384r,416r:0)  0@384r

selectOrSplit GR64:%vreg13 [464r,560r:0)  0@464r w=4.072580e-03
hints: %RAX
assigning %vreg13 to %RAX: AH [464r,560r:0)  0@464r AL [464r,560r:0)  0@464r

selectOrSplit GR64:%vreg8 [480r,624r:0)  0@480r w=1.856618e-03
hints: %RDI
assigning %vreg8 to %RDI: DIL [480r,624r:0)  0@480r

selectOrSplit GR64:%vreg10 [576r,736r:0)  0@576r w=5.410714e-03
hints: %RAX
missed hint %RAX
assigning %vreg10 to %RBX: BH [576r,736r:0)  0@576r BL [576r,736r:0)  0@576r

selectOrSplit GR64:%vreg9 [592r,640r:0)  0@592r w=4.508928e-03
hints: %RSI
assigning %vreg9 to %RSI: SIL [592r,640r:0)  0@592r

selectOrSplit GR32:%vreg18 [336r,368r:0)[368r,384r:1)  0@336r 1@368r w=inf
assigning %vreg18 to %EAX: AH [336r,368r:0)[368r,384r:1)  0@336r 1@368r AL [336r,368r:0)[368r,384r:1)  0@336r 1@368r

********** STACK TRANSFORMATION METADATA **********
********** Function: default_bzalloc
********** REGISTER MAP **********
[%vreg1 -> %RBX] GR64
[%vreg3 -> %R15D] GR32
[%vreg5 -> %R14D] GR32
[%vreg8 -> %RDI] GR64
[%vreg9 -> %RSI] GR64
[%vreg10 -> %RBX] GR64
[%vreg13 -> %RAX] GR64
[%vreg15 -> %RDI] GR64
[%vreg18 -> %EAX] GR32
[%vreg21 -> %RDI] GR64
[%vreg22 -> %RSI] GR64


Stackmap 0:
  STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, %vreg5, 0, <fi#2>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1](align=4) LD8[FixedStack0] LD8[FixedStack2](align=4) LD8[FixedStack3] GR32:%vreg3,%vreg5 GR64:%vreg1

i32 %items: in register %R15D (vreg 3)
i32* %items.addr: in stack slot 1 (size: 4)
i8* %opaque: in register %RBX (vreg 1)
i8** %opaque.addr: in stack slot 0 (size: 8)
i32 %size: in register %R14D (vreg 5)
i32* %size.addr: in stack slot 2 (size: 4)
i8** %v: in stack slot 3 (size: 8)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack3]

i8** %v: in stack slot 3 (size: 8)

Duplicate operand locations:


Stackmap 2:
  STACKMAP 2, 0, %vreg10, ...; GR64:%vreg10

i8* %2: in register %RBX (vreg 10)

Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, %vreg5, 0, <fi#2>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1](align=4) LD8[FixedStack0] LD8[FixedStack2](align=4) LD8[FixedStack3] GR32:%vreg3,%vreg5 GR64:%vreg1
  -> Call instruction SlotIndex 208B, searching vregs 0 -> 23 and stack slots -1 -> 4

  STACKMAP 1, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack3]
  -> Call instruction SlotIndex 432B, searching vregs 0 -> 23 and stack slots -1 -> 4

  STACKMAP 2, 0, %vreg10, ...; GR64:%vreg10
  -> Call instruction SlotIndex 656B, searching vregs 0 -> 23 and stack slots -1 -> 4

********** REWRITE VIRTUAL REGISTERS **********
********** Function: default_bzalloc
********** REGISTER MAP **********
[%vreg1 -> %RBX] GR64
[%vreg3 -> %R15D] GR32
[%vreg5 -> %R14D] GR32
[%vreg8 -> %RDI] GR64
[%vreg9 -> %RSI] GR64
[%vreg10 -> %RBX] GR64
[%vreg13 -> %RAX] GR64
[%vreg15 -> %RDI] GR64
[%vreg18 -> %EAX] GR32
[%vreg21 -> %RDI] GR64
[%vreg22 -> %RSI] GR64

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %EDX %ESI %RDI
16B		%vreg5<def> = COPY %EDX; GR32:%vreg5
32B		%vreg3<def> = COPY %ESI; GR32:%vreg3
48B		%vreg1<def> = COPY %RDI; GR64:%vreg1
112B		%vreg21<def> = MOV64ri <ga:@default_bzalloc>; GR64:%vreg21
144B		%vreg22<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg22
160B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		%RDI<def> = COPY %vreg21<kill>; GR64:%vreg21
192B		%RSI<def> = COPY %vreg22<kill>; GR64:%vreg22
208B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
224B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
240B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
256B		STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, %vreg5, 0, <fi#2>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1](align=4) LD8[FixedStack0] LD8[FixedStack2](align=4) LD8[FixedStack3] GR32:%vreg3,%vreg5 GR64:%vreg1
272B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
288B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1<kill>; mem:ST8[%opaque.addr] GR64:%vreg1
304B		MOV32mr <fi#1>, 1, %noreg, 0, %noreg, %vreg3<kill>; mem:ST4[%items.addr] GR32:%vreg3
320B		MOV32mr <fi#2>, 1, %noreg, 0, %noreg, %vreg5<kill>; mem:ST4[%size.addr] GR32:%vreg5
336B		%vreg18<def> = MOV32rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD4[%items.addr] GR32:%vreg18
368B		%vreg18<def,tied1> = IMUL32rm %vreg18<kill,tied0>, <fi#2>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%size.addr] GR32:%vreg18
384B		%vreg15<def> = MOVSX64rr32 %vreg18<kill>; GR64:%vreg15 GR32:%vreg18
400B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
416B		%RDI<def> = COPY %vreg15<kill>; GR64:%vreg15
432B		CALL64pcrel32 <ga:@malloc>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RAX<imp-def>
448B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
464B		%vreg13<def> = COPY %RAX; GR64:%vreg13
480B		%vreg8<def> = MOV64ri <ga:@default_bzalloc>; GR64:%vreg8
512B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
528B		STACKMAP 1, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack3]
544B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
560B		MOV64mr <fi#3>, 1, %noreg, 0, %noreg, %vreg13<kill>; mem:ST8[%v] GR64:%vreg13
576B		%vreg10<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%v] GR64:%vreg10
592B		%vreg9<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg9
608B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
624B		%RDI<def> = COPY %vreg8<kill>; GR64:%vreg8
640B		%RSI<def> = COPY %vreg9<kill>; GR64:%vreg9
656B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
672B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
688B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
704B		STACKMAP 2, 0, %vreg10, ...; GR64:%vreg10
720B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
736B		%RAX<def> = COPY %vreg10<kill>; GR64:%vreg10
752B		RETQ %RAX<imp-use>
> %R14D<def> = COPY %EDX
> %R15D<def> = COPY %ESI
> %RBX<def> = COPY %RDI
> %RDI<def> = MOV64ri <ga:@default_bzalloc>
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 0, 0, %R15D, 0, <fi#1>, 0, %RBX, 0, <fi#0>, 0, %R14D, 0, <fi#2>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1](align=4) LD8[FixedStack0] LD8[FixedStack2](align=4) LD8[FixedStack3]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %RBX<kill>; mem:ST8[%opaque.addr]
> MOV32mr <fi#1>, 1, %noreg, 0, %noreg, %R15D<kill>; mem:ST4[%items.addr]
> MOV32mr <fi#2>, 1, %noreg, 0, %noreg, %R14D<kill>; mem:ST4[%size.addr]
> %EAX<def> = MOV32rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD4[%items.addr]
> %EAX<def,tied1> = IMUL32rm %EAX<kill,tied0>, <fi#2>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%size.addr]
> %RDI<def> = MOVSX64rr32 %EAX<kill>
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@malloc>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RAX<def> = COPY %RAX
Deleting identity copy.
> %RDI<def> = MOV64ri <ga:@default_bzalloc>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 1, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack3]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV64mr <fi#3>, 1, %noreg, 0, %noreg, %RAX<kill>; mem:ST8[%v]
> %RBX<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%v]
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 2, 0, %RBX, ...
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RAX<def> = COPY %RBX<kill>
> RETQ %RAX<imp-use>
Computing live-in reg-units in ABI blocks.
0B	BB#0 DIL#0 SIL#0
Created 2 new intervals.
********** INTERVALS **********
DIL [0B,32r:0)[144r,176r:3)[368r,384r:2)[544r,576r:1)  0@0B-phi 1@544r 2@368r 3@144r
SIL [0B,16r:0)[160r,176r:2)[560r,576r:1)  0@0B-phi 1@560r 2@160r
%vreg0 [32r,48r:0)  0@32r
%vreg1 [48r,256r:0)  0@48r
%vreg2 [16r,64r:0)  0@16r
%vreg3 [64r,272r:0)  0@64r
%vreg5 [80r,96r:0)  0@80r
%vreg6 [96r,144r:0)  0@96r
%vreg7 [112r,160r:0)  0@112r
%vreg9 [336r,368r:0)  0@336r
%vreg10 [480r,496r:0)  0@480r
%vreg11 [496r,544r:0)  0@496r
%vreg12 [512r,560r:0)  0@512r
RegMasks: 176r 384r 576r
********** MACHINEINSTRS **********
# Machine code for function default_bzfree: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=8, align=8, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
Function Live Ins: %RDI in %vreg0, %RSI in %vreg2

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI %RSI
16B		%vreg2<def> = COPY %RSI; GR64:%vreg2
32B		%vreg0<def> = COPY %RDI; GR64:%vreg0
48B		%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
64B		%vreg3<def> = COPY %vreg2; GR64:%vreg3,%vreg2
80B		%vreg5<def> = MOV64ri <ga:@default_bzfree>; GR64:%vreg5
96B		%vreg6<def> = COPY %vreg5; GR64:%vreg6,%vreg5
112B		%vreg7<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg7
128B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
144B		%RDI<def> = COPY %vreg6; GR64:%vreg6
160B		%RSI<def> = COPY %vreg7; GR64:%vreg7
176B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
192B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
208B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack0] GR64:%vreg3,%vreg1
240B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
256B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%opaque.addr] GR64:%vreg1
272B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg3; mem:ST8[%addr.addr] GR64:%vreg3
288B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%addr.addr]
304B		JE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

320B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
336B		%vreg9<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%addr.addr] GR64:%vreg9
352B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
368B		%RDI<def> = COPY %vreg9; GR64:%vreg9
384B		CALL64pcrel32 <ga:@free>, <regmask>, %RSP<imp-use>, %RDI<imp-use>
400B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
416B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
432B		STACKMAP 1, 0, ...
448B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#2

464B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#1
480B		%vreg10<def> = MOV64ri <ga:@default_bzfree>; GR64:%vreg10
496B		%vreg11<def> = COPY %vreg10; GR64:%vreg11,%vreg10
512B		%vreg12<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg12
528B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
544B		%RDI<def> = COPY %vreg11; GR64:%vreg11
560B		%RSI<def> = COPY %vreg12; GR64:%vreg12
576B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
592B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
608B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
624B		STACKMAP 2, 0, ...
640B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
656B		RETQ

# End machine code for function default_bzfree.

********** SIMPLE REGISTER COALESCING **********
********** Function: default_bzfree
********** JOINING INTERVALS ***********
entry:
16B	%vreg2<def> = COPY %RSI; GR64:%vreg2
	Considering merging %vreg2 with %RSI
	Can only merge into reserved registers.
32B	%vreg0<def> = COPY %RDI; GR64:%vreg0
	Considering merging %vreg0 with %RDI
	Can only merge into reserved registers.
144B	%RDI<def> = COPY %vreg6; GR64:%vreg6
	Considering merging %vreg6 with %RDI
	Can only merge into reserved registers.
160B	%RSI<def> = COPY %vreg7; GR64:%vreg7
	Considering merging %vreg7 with %RSI
	Can only merge into reserved registers.
if.then:
368B	%RDI<def> = COPY %vreg9; GR64:%vreg9
	Considering merging %vreg9 with %RDI
	Can only merge into reserved registers.
if.end:
544B	%RDI<def> = COPY %vreg11; GR64:%vreg11
	Considering merging %vreg11 with %RDI
	Can only merge into reserved registers.
560B	%RSI<def> = COPY %vreg12; GR64:%vreg12
	Considering merging %vreg12 with %RSI
	Can only merge into reserved registers.
48B	%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
	Considering merging to GR64 with %vreg0 in %vreg1
		RHS = %vreg0 [32r,48r:0)  0@32r
		LHS = %vreg1 [48r,256r:0)  0@48r
		merge %vreg1:0@48r into %vreg0:0@32r --> @32r
		erased:	48r	%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
		updated: 32B	%vreg1<def> = COPY %RDI; GR64:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [32r,256r:0)  0@32r
64B	%vreg3<def> = COPY %vreg2; GR64:%vreg3,%vreg2
	Considering merging to GR64 with %vreg2 in %vreg3
		RHS = %vreg2 [16r,64r:0)  0@16r
		LHS = %vreg3 [64r,272r:0)  0@64r
		merge %vreg3:0@64r into %vreg2:0@16r --> @16r
		erased:	64r	%vreg3<def> = COPY %vreg2; GR64:%vreg3,%vreg2
		updated: 16B	%vreg3<def> = COPY %RSI; GR64:%vreg3
	Success: %vreg2 -> %vreg3
	Result = %vreg3 [16r,272r:0)  0@16r
96B	%vreg6<def> = COPY %vreg5; GR64:%vreg6,%vreg5
	Considering merging to GR64 with %vreg5 in %vreg6
		RHS = %vreg5 [80r,96r:0)  0@80r
		LHS = %vreg6 [96r,144r:0)  0@96r
		merge %vreg6:0@96r into %vreg5:0@80r --> @80r
		erased:	96r	%vreg6<def> = COPY %vreg5; GR64:%vreg6,%vreg5
		updated: 80B	%vreg6<def> = MOV64ri <ga:@default_bzfree>; GR64:%vreg6
	Success: %vreg5 -> %vreg6
	Result = %vreg6 [80r,144r:0)  0@80r
496B	%vreg11<def> = COPY %vreg10; GR64:%vreg11,%vreg10
	Considering merging to GR64 with %vreg10 in %vreg11
		RHS = %vreg10 [480r,496r:0)  0@480r
		LHS = %vreg11 [496r,544r:0)  0@496r
		merge %vreg11:0@496r into %vreg10:0@480r --> @480r
		erased:	496r	%vreg11<def> = COPY %vreg10; GR64:%vreg11,%vreg10
		updated: 480B	%vreg11<def> = MOV64ri <ga:@default_bzfree>; GR64:%vreg11
	Success: %vreg10 -> %vreg11
	Result = %vreg11 [480r,544r:0)  0@480r
144B	%RDI<def> = COPY %vreg6; GR64:%vreg6
	Considering merging %vreg6 with %RDI
	Can only merge into reserved registers.
544B	%RDI<def> = COPY %vreg11; GR64:%vreg11
	Considering merging %vreg11 with %RDI
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
DIL [0B,32r:0)[144r,176r:3)[368r,384r:2)[544r,576r:1)  0@0B-phi 1@544r 2@368r 3@144r
SIL [0B,16r:0)[160r,176r:2)[560r,576r:1)  0@0B-phi 1@560r 2@160r
%vreg1 [32r,256r:0)  0@32r
%vreg3 [16r,272r:0)  0@16r
%vreg6 [80r,144r:0)  0@80r
%vreg7 [112r,160r:0)  0@112r
%vreg9 [336r,368r:0)  0@336r
%vreg11 [480r,544r:0)  0@480r
%vreg12 [512r,560r:0)  0@512r
RegMasks: 176r 384r 576r
********** MACHINEINSTRS **********
# Machine code for function default_bzfree: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=8, align=8, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
Function Live Ins: %RDI in %vreg0, %RSI in %vreg2

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI %RSI
16B		%vreg3<def> = COPY %RSI; GR64:%vreg3
32B		%vreg1<def> = COPY %RDI; GR64:%vreg1
80B		%vreg6<def> = MOV64ri <ga:@default_bzfree>; GR64:%vreg6
112B		%vreg7<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg7
128B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
144B		%RDI<def> = COPY %vreg6; GR64:%vreg6
160B		%RSI<def> = COPY %vreg7; GR64:%vreg7
176B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
192B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
208B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack0] GR64:%vreg3,%vreg1
240B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
256B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%opaque.addr] GR64:%vreg1
272B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg3; mem:ST8[%addr.addr] GR64:%vreg3
288B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%addr.addr]
304B		JE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

320B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
336B		%vreg9<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%addr.addr] GR64:%vreg9
352B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
368B		%RDI<def> = COPY %vreg9; GR64:%vreg9
384B		CALL64pcrel32 <ga:@free>, <regmask>, %RSP<imp-use>, %RDI<imp-use>
400B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
416B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
432B		STACKMAP 1, 0, ...
448B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#2

464B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#1
480B		%vreg11<def> = MOV64ri <ga:@default_bzfree>; GR64:%vreg11
512B		%vreg12<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg12
528B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
544B		%RDI<def> = COPY %vreg11; GR64:%vreg11
560B		%RSI<def> = COPY %vreg12; GR64:%vreg12
576B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
592B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
608B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
624B		STACKMAP 2, 0, ...
640B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
656B		RETQ

# End machine code for function default_bzfree.

********** GREEDY REGISTER ALLOCATION **********
********** Function: default_bzfree
********** INTERVALS **********
DIL [0B,32r:0)[144r,176r:3)[368r,384r:2)[544r,576r:1)  0@0B-phi 1@544r 2@368r 3@144r
SIL [0B,16r:0)[160r,176r:2)[560r,576r:1)  0@0B-phi 1@560r 2@160r
%vreg1 [32r,256r:0)  0@32r
%vreg3 [16r,272r:0)  0@16r
%vreg6 [80r,144r:0)  0@80r
%vreg7 [112r,160r:0)  0@112r
%vreg9 [336r,368r:0)  0@336r
%vreg11 [480r,544r:0)  0@480r
%vreg12 [512r,560r:0)  0@512r
RegMasks: 176r 384r 576r
********** MACHINEINSTRS **********
# Machine code for function default_bzfree: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=8, align=8, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
Function Live Ins: %RDI in %vreg0, %RSI in %vreg2

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI %RSI
16B		%vreg3<def> = COPY %RSI; GR64:%vreg3
32B		%vreg1<def> = COPY %RDI; GR64:%vreg1
80B		%vreg6<def> = MOV64ri <ga:@default_bzfree>; GR64:%vreg6
112B		%vreg7<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg7
128B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
144B		%RDI<def> = COPY %vreg6; GR64:%vreg6
160B		%RSI<def> = COPY %vreg7; GR64:%vreg7
176B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
192B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
208B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack0] GR64:%vreg3,%vreg1
240B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
256B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%opaque.addr] GR64:%vreg1
272B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg3; mem:ST8[%addr.addr] GR64:%vreg3
288B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%addr.addr]
304B		JE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

320B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
336B		%vreg9<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%addr.addr] GR64:%vreg9
352B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
368B		%RDI<def> = COPY %vreg9; GR64:%vreg9
384B		CALL64pcrel32 <ga:@free>, <regmask>, %RSP<imp-use>, %RDI<imp-use>
400B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
416B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
432B		STACKMAP 1, 0, ...
448B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#2

464B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#1
480B		%vreg11<def> = MOV64ri <ga:@default_bzfree>; GR64:%vreg11
512B		%vreg12<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg12
528B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
544B		%RDI<def> = COPY %vreg11; GR64:%vreg11
560B		%RSI<def> = COPY %vreg12; GR64:%vreg12
576B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
592B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
608B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
624B		STACKMAP 2, 0, ...
640B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
656B		RETQ

# End machine code for function default_bzfree.


selectOrSplit GR64:%vreg3 [16r,272r:0)  0@16r w=4.618902e-03
hints: %RSI
missed hint %RSI
assigning %vreg3 to %RBX: BH [16r,272r:0)  0@16r BL [16r,272r:0)  0@16r

selectOrSplit GR64:%vreg1 [32r,256r:0)  0@32r w=4.855769e-03
hints: %RDI
missed hint %RDI
%R14 is available at cost 1
Only trying the first 10 regs.
should evict: %vreg3 [16r,272r:0)  0@16r w= 4.618902e-03
hints: %RSI
can reassign: %vreg3 [16r,272r:0)  0@16r from %RBX to %RSI
should evict: %vreg3 [16r,272r:0)  0@16r w= 4.618902e-03
hints: %RSI
can reassign: %vreg3 [16r,272r:0)  0@16r from %RBX to %RSI
evicting %RBX interference: Cascade 1
unassigning %vreg3 from %RBX: BH BL
assigning %vreg1 to %RBX: BH [32r,256r:0)  0@32r BL [32r,256r:0)  0@32r
queuing new interval: %vreg3 [16r,272r:0)  0@16r

selectOrSplit GR64:%vreg3 [16r,272r:0)  0@16r w=4.618902e-03
hints: %RSI
missed hint %RSI
%R14 is available at cost 1
Only trying the first 10 regs.
assigning %vreg3 to %R14: R14B [16r,272r:0)  0@16r

selectOrSplit GR64:%vreg6 [80r,144r:0)  0@80r w=2.176724e-03
hints: %RDI
assigning %vreg6 to %RDI: DIL [80r,144r:0)  0@80r

selectOrSplit GR64:%vreg7 [112r,160r:0)  0@112r w=4.508928e-03
hints: %RSI
assigning %vreg7 to %RSI: SIL [112r,160r:0)  0@112r

selectOrSplit GR64:%vreg9 [336r,368r:0)  0@336r w=2.337963e-03
hints: %RDI
assigning %vreg9 to %RDI: DIL [336r,368r:0)  0@336r

selectOrSplit GR64:%vreg11 [480r,544r:0)  0@480r w=2.176724e-03
hints: %RDI
assigning %vreg11 to %RDI: DIL [480r,544r:0)  0@480r

selectOrSplit GR64:%vreg12 [512r,560r:0)  0@512r w=4.508928e-03
hints: %RSI
assigning %vreg12 to %RSI: SIL [512r,560r:0)  0@512r

********** STACK TRANSFORMATION METADATA **********
********** Function: default_bzfree
********** REGISTER MAP **********
[%vreg1 -> %RBX] GR64
[%vreg3 -> %R14] GR64
[%vreg6 -> %RDI] GR64
[%vreg7 -> %RSI] GR64
[%vreg9 -> %RDI] GR64
[%vreg11 -> %RDI] GR64
[%vreg12 -> %RSI] GR64


Stackmap 0:
  STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack0] GR64:%vreg3,%vreg1

i8* %addr: in register %R14 (vreg 3)
i8** %addr.addr: in stack slot 1 (size: 8)
i8* %opaque: in register %RBX (vreg 1)
i8** %opaque.addr: in stack slot 0 (size: 8)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, ...


Duplicate operand locations:


Stackmap 2:
  STACKMAP 2, 0, ...


Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack0] GR64:%vreg3,%vreg1
  -> Call instruction SlotIndex 176B, searching vregs 0 -> 13 and stack slots -1 -> 2

  STACKMAP 1, 0, ...
  -> Call instruction SlotIndex 384B, searching vregs 0 -> 13 and stack slots -1 -> 2

  STACKMAP 2, 0, ...
  -> Call instruction SlotIndex 576B, searching vregs 0 -> 13 and stack slots -1 -> 2

********** REWRITE VIRTUAL REGISTERS **********
********** Function: default_bzfree
********** REGISTER MAP **********
[%vreg1 -> %RBX] GR64
[%vreg3 -> %R14] GR64
[%vreg6 -> %RDI] GR64
[%vreg7 -> %RSI] GR64
[%vreg9 -> %RDI] GR64
[%vreg11 -> %RDI] GR64
[%vreg12 -> %RSI] GR64

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI %RSI
16B		%vreg3<def> = COPY %RSI; GR64:%vreg3
32B		%vreg1<def> = COPY %RDI; GR64:%vreg1
80B		%vreg6<def> = MOV64ri <ga:@default_bzfree>; GR64:%vreg6
112B		%vreg7<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg7
128B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
144B		%RDI<def> = COPY %vreg6<kill>; GR64:%vreg6
160B		%RSI<def> = COPY %vreg7<kill>; GR64:%vreg7
176B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
192B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
208B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack0] GR64:%vreg3,%vreg1
240B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
256B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1<kill>; mem:ST8[%opaque.addr] GR64:%vreg1
272B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg3<kill>; mem:ST8[%addr.addr] GR64:%vreg3
288B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%addr.addr]
304B		JE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1
> %R14<def> = COPY %RSI
> %RBX<def> = COPY %RDI
> %RDI<def> = MOV64ri <ga:@default_bzfree>
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 0, 0, %R14, 0, <fi#1>, 0, %RBX, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack0]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %RBX<kill>; mem:ST8[%opaque.addr]
> MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %R14<kill>; mem:ST8[%addr.addr]
> CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%addr.addr]
> JE_1 <BB#2>, %EFLAGS<imp-use,kill>
320B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
336B		%vreg9<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%addr.addr] GR64:%vreg9
352B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
368B		%RDI<def> = COPY %vreg9<kill>; GR64:%vreg9
384B		CALL64pcrel32 <ga:@free>, <regmask>, %RSP<imp-use>, %RDI<imp-use>
400B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
416B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
432B		STACKMAP 1, 0, ...
448B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#2
> %RDI<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%addr.addr]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@free>, <regmask>, %RSP<imp-use>, %RDI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 1, 0, ...
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
464B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#1
480B		%vreg11<def> = MOV64ri <ga:@default_bzfree>; GR64:%vreg11
512B		%vreg12<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg12
528B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
544B		%RDI<def> = COPY %vreg11<kill>; GR64:%vreg11
560B		%RSI<def> = COPY %vreg12<kill>; GR64:%vreg12
576B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
592B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
608B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
624B		STACKMAP 2, 0, ...
640B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
656B		RETQ
> %RDI<def> = MOV64ri <ga:@default_bzfree>
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 2, 0, ...
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> RETQ
Computing live-in reg-units in ABI blocks.
0B	BB#0 DIL#0
Created 1 new intervals.
********** INTERVALS **********
DIL [0B,16r:0)[112r,144r:1)[368r,400r:2)  0@0B-phi 1@112r 2@368r
%vreg0 [16r,32r:0)  0@16r
%vreg1 [32r,256r:0)  0@32r
%vreg2 [176r,192r:0)  0@176r
%vreg3 [192r,368r:0)  0@192r
%vreg4 [336r,384r:0)  0@336r
%vreg6 [304r,320r:0)  0@304r
%vreg8 [272r,288r:0)  0@272r
%vreg9 [48r,64r:0)  0@48r
%vreg10 [64r,112r:0)  0@64r
%vreg11 [80r,128r:0)  0@80r
RegMasks: 144r 400r
********** MACHINEINSTRS **********
# Machine code for function init_RL: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=8, align=8, at location [SP+8]
Function Live Ins: %RDI in %vreg0

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI
16B		%vreg0<def> = COPY %RDI; GR64:%vreg0
32B		%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
48B		%vreg9<def> = MOV64ri <ga:@init_RL>; GR64:%vreg9
64B		%vreg10<def> = COPY %vreg9; GR64:%vreg10,%vreg9
80B		%vreg11<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg11
96B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
112B		%RDI<def> = COPY %vreg10; GR64:%vreg10
128B		%RSI<def> = COPY %vreg11; GR64:%vreg11
144B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
160B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		%vreg2<def> = MOV64ri <ga:@init_RL>; GR64:%vreg2
192B		%vreg3<def> = COPY %vreg2; GR64:%vreg3,%vreg2
208B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0] GR64:%vreg1
240B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
256B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%s.addr] GR64:%vreg1
272B		%vreg8<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg8
288B		MOV32mi %vreg8, 1, %noreg, 92, %noreg, 256; mem:ST4[%state_in_ch] GR64:%vreg8
304B		%vreg6<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg6
320B		MOV32mi %vreg6, 1, %noreg, 96, %noreg, 0; mem:ST4[%state_in_len] GR64:%vreg6
336B		%vreg4<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg4
352B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
368B		%RDI<def> = COPY %vreg3; GR64:%vreg3
384B		%RSI<def> = COPY %vreg4; GR64:%vreg4
400B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
416B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
432B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
448B		STACKMAP 1, 0, ...
464B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
480B		RETQ

# End machine code for function init_RL.

********** SIMPLE REGISTER COALESCING **********
********** Function: init_RL
********** JOINING INTERVALS ***********
entry:
16B	%vreg0<def> = COPY %RDI; GR64:%vreg0
	Considering merging %vreg0 with %RDI
	Can only merge into reserved registers.
112B	%RDI<def> = COPY %vreg10; GR64:%vreg10
	Considering merging %vreg10 with %RDI
	Can only merge into reserved registers.
128B	%RSI<def> = COPY %vreg11; GR64:%vreg11
	Considering merging %vreg11 with %RSI
	Can only merge into reserved registers.
368B	%RDI<def> = COPY %vreg3; GR64:%vreg3
	Considering merging %vreg3 with %RDI
	Can only merge into reserved registers.
384B	%RSI<def> = COPY %vreg4; GR64:%vreg4
	Considering merging %vreg4 with %RSI
	Can only merge into reserved registers.
32B	%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
	Considering merging to GR64 with %vreg0 in %vreg1
		RHS = %vreg0 [16r,32r:0)  0@16r
		LHS = %vreg1 [32r,256r:0)  0@32r
		merge %vreg1:0@32r into %vreg0:0@16r --> @16r
		erased:	32r	%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
		updated: 16B	%vreg1<def> = COPY %RDI; GR64:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [16r,256r:0)  0@16r
64B	%vreg10<def> = COPY %vreg9; GR64:%vreg10,%vreg9
	Considering merging to GR64 with %vreg9 in %vreg10
		RHS = %vreg9 [48r,64r:0)  0@48r
		LHS = %vreg10 [64r,112r:0)  0@64r
		merge %vreg10:0@64r into %vreg9:0@48r --> @48r
		erased:	64r	%vreg10<def> = COPY %vreg9; GR64:%vreg10,%vreg9
		updated: 48B	%vreg10<def> = MOV64ri <ga:@init_RL>; GR64:%vreg10
	Success: %vreg9 -> %vreg10
	Result = %vreg10 [48r,112r:0)  0@48r
192B	%vreg3<def> = COPY %vreg2; GR64:%vreg3,%vreg2
	Considering merging to GR64 with %vreg2 in %vreg3
		RHS = %vreg2 [176r,192r:0)  0@176r
		LHS = %vreg3 [192r,368r:0)  0@192r
		merge %vreg3:0@192r into %vreg2:0@176r --> @176r
		erased:	192r	%vreg3<def> = COPY %vreg2; GR64:%vreg3,%vreg2
		updated: 176B	%vreg3<def> = MOV64ri <ga:@init_RL>; GR64:%vreg3
	Success: %vreg2 -> %vreg3
	Result = %vreg3 [176r,368r:0)  0@176r
112B	%RDI<def> = COPY %vreg10; GR64:%vreg10
	Considering merging %vreg10 with %RDI
	Can only merge into reserved registers.
368B	%RDI<def> = COPY %vreg3; GR64:%vreg3
	Considering merging %vreg3 with %RDI
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
DIL [0B,16r:0)[112r,144r:1)[368r,400r:2)  0@0B-phi 1@112r 2@368r
%vreg1 [16r,256r:0)  0@16r
%vreg3 [176r,368r:0)  0@176r
%vreg4 [336r,384r:0)  0@336r
%vreg6 [304r,320r:0)  0@304r
%vreg8 [272r,288r:0)  0@272r
%vreg10 [48r,112r:0)  0@48r
%vreg11 [80r,128r:0)  0@80r
RegMasks: 144r 400r
********** MACHINEINSTRS **********
# Machine code for function init_RL: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=8, align=8, at location [SP+8]
Function Live Ins: %RDI in %vreg0

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI
16B		%vreg1<def> = COPY %RDI; GR64:%vreg1
48B		%vreg10<def> = MOV64ri <ga:@init_RL>; GR64:%vreg10
80B		%vreg11<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg11
96B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
112B		%RDI<def> = COPY %vreg10; GR64:%vreg10
128B		%RSI<def> = COPY %vreg11; GR64:%vreg11
144B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
160B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		%vreg3<def> = MOV64ri <ga:@init_RL>; GR64:%vreg3
208B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0] GR64:%vreg1
240B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
256B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%s.addr] GR64:%vreg1
272B		%vreg8<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg8
288B		MOV32mi %vreg8, 1, %noreg, 92, %noreg, 256; mem:ST4[%state_in_ch] GR64:%vreg8
304B		%vreg6<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg6
320B		MOV32mi %vreg6, 1, %noreg, 96, %noreg, 0; mem:ST4[%state_in_len] GR64:%vreg6
336B		%vreg4<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg4
352B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
368B		%RDI<def> = COPY %vreg3; GR64:%vreg3
384B		%RSI<def> = COPY %vreg4; GR64:%vreg4
400B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
416B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
432B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
448B		STACKMAP 1, 0, ...
464B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
480B		RETQ

# End machine code for function init_RL.

********** GREEDY REGISTER ALLOCATION **********
********** Function: init_RL
********** INTERVALS **********
DIL [0B,16r:0)[112r,144r:1)[368r,400r:2)  0@0B-phi 1@112r 2@368r
%vreg1 [16r,256r:0)  0@16r
%vreg3 [176r,368r:0)  0@176r
%vreg4 [336r,384r:0)  0@336r
%vreg6 [304r,320r:0)  0@304r
%vreg8 [272r,288r:0)  0@272r
%vreg10 [48r,112r:0)  0@48r
%vreg11 [80r,128r:0)  0@80r
RegMasks: 144r 400r
********** MACHINEINSTRS **********
# Machine code for function init_RL: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=8, align=8, at location [SP+8]
Function Live Ins: %RDI in %vreg0

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI
16B		%vreg1<def> = COPY %RDI; GR64:%vreg1
48B		%vreg10<def> = MOV64ri <ga:@init_RL>; GR64:%vreg10
80B		%vreg11<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg11
96B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
112B		%RDI<def> = COPY %vreg10; GR64:%vreg10
128B		%RSI<def> = COPY %vreg11; GR64:%vreg11
144B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
160B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		%vreg3<def> = MOV64ri <ga:@init_RL>; GR64:%vreg3
208B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0] GR64:%vreg1
240B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
256B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%s.addr] GR64:%vreg1
272B		%vreg8<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg8
288B		MOV32mi %vreg8, 1, %noreg, 92, %noreg, 256; mem:ST4[%state_in_ch] GR64:%vreg8
304B		%vreg6<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg6
320B		MOV32mi %vreg6, 1, %noreg, 96, %noreg, 0; mem:ST4[%state_in_len] GR64:%vreg6
336B		%vreg4<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg4
352B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
368B		%RDI<def> = COPY %vreg3; GR64:%vreg3
384B		%RSI<def> = COPY %vreg4; GR64:%vreg4
400B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
416B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
432B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
448B		STACKMAP 1, 0, ...
464B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
480B		RETQ

# End machine code for function init_RL.


selectOrSplit GR64:%vreg1 [16r,256r:0)  0@16r w=4.734375e-03
hints: %RDI
missed hint %RDI
assigning %vreg1 to %RBX: BH [16r,256r:0)  0@16r BL [16r,256r:0)  0@16r

selectOrSplit GR64:%vreg10 [48r,112r:0)  0@48r w=2.176724e-03
hints: %RDI
assigning %vreg10 to %RDI: DIL [48r,112r:0)  0@48r

selectOrSplit GR64:%vreg11 [80r,128r:0)  0@80r w=4.508928e-03
hints: %RSI
assigning %vreg11 to %RSI: SIL [80r,128r:0)  0@80r

selectOrSplit GR64:%vreg3 [176r,368r:0)  0@176r w=1.706081e-03
hints: %RDI
assigning %vreg3 to %RDI: DIL [176r,368r:0)  0@176r

selectOrSplit GR64:%vreg4 [336r,384r:0)  0@336r w=4.508928e-03
hints: %RSI
assigning %vreg4 to %RSI: SIL [336r,384r:0)  0@336r

selectOrSplit GR64:%vreg8 [272r,288r:0)  0@272r w=inf
assigning %vreg8 to %RAX: AH [272r,288r:0)  0@272r AL [272r,288r:0)  0@272r

selectOrSplit GR64:%vreg6 [304r,320r:0)  0@304r w=inf
assigning %vreg6 to %RAX: AH [304r,320r:0)  0@304r AL [304r,320r:0)  0@304r

********** STACK TRANSFORMATION METADATA **********
********** Function: init_RL
********** REGISTER MAP **********
[%vreg1 -> %RBX] GR64
[%vreg3 -> %RDI] GR64
[%vreg4 -> %RSI] GR64
[%vreg6 -> %RAX] GR64
[%vreg8 -> %RAX] GR64
[%vreg10 -> %RDI] GR64
[%vreg11 -> %RSI] GR64


Stackmap 0:
  STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0] GR64:%vreg1

%struct.EState* %s: in register %RBX (vreg 1)
%struct.EState** %s.addr: in stack slot 0 (size: 8)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, ...


Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0] GR64:%vreg1
  -> Call instruction SlotIndex 144B, searching vregs 0 -> 12 and stack slots -1 -> 1

  STACKMAP 1, 0, ...
  -> Call instruction SlotIndex 400B, searching vregs 0 -> 12 and stack slots -1 -> 1

********** REWRITE VIRTUAL REGISTERS **********
********** Function: init_RL
********** REGISTER MAP **********
[%vreg1 -> %RBX] GR64
[%vreg3 -> %RDI] GR64
[%vreg4 -> %RSI] GR64
[%vreg6 -> %RAX] GR64
[%vreg8 -> %RAX] GR64
[%vreg10 -> %RDI] GR64
[%vreg11 -> %RSI] GR64

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI
16B		%vreg1<def> = COPY %RDI; GR64:%vreg1
48B		%vreg10<def> = MOV64ri <ga:@init_RL>; GR64:%vreg10
80B		%vreg11<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg11
96B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
112B		%RDI<def> = COPY %vreg10<kill>; GR64:%vreg10
128B		%RSI<def> = COPY %vreg11<kill>; GR64:%vreg11
144B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
160B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		%vreg3<def> = MOV64ri <ga:@init_RL>; GR64:%vreg3
208B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0] GR64:%vreg1
240B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
256B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1<kill>; mem:ST8[%s.addr] GR64:%vreg1
272B		%vreg8<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg8
288B		MOV32mi %vreg8<kill>, 1, %noreg, 92, %noreg, 256; mem:ST4[%state_in_ch] GR64:%vreg8
304B		%vreg6<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg6
320B		MOV32mi %vreg6<kill>, 1, %noreg, 96, %noreg, 0; mem:ST4[%state_in_len] GR64:%vreg6
336B		%vreg4<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg4
352B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
368B		%RDI<def> = COPY %vreg3<kill>; GR64:%vreg3
384B		%RSI<def> = COPY %vreg4<kill>; GR64:%vreg4
400B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
416B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
432B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
448B		STACKMAP 1, 0, ...
464B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
480B		RETQ
> %RBX<def> = COPY %RDI
> %RDI<def> = MOV64ri <ga:@init_RL>
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = MOV64ri <ga:@init_RL>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 0, 0, %RBX, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %RBX<kill>; mem:ST8[%s.addr]
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 92, %noreg, 256; mem:ST4[%state_in_ch]
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 96, %noreg, 0; mem:ST4[%state_in_len]
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 1, 0, ...
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> RETQ
Computing live-in reg-units in ABI blocks.
0B	BB#0 DIL#0
Created 1 new intervals.
********** INTERVALS **********
DIL [0B,16r:0)[112r,144r:2)[752r,784r:1)  0@0B-phi 1@752r 2@112r
%vreg0 [16r,32r:0)  0@16r
%vreg1 [32r,224r:0)  0@32r
%vreg3 [336r,352r:0)  0@336r
%vreg5 [304r,320r:0)  0@304r
%vreg7 [272r,288r:0)  0@272r
%vreg9 [240r,256r:0)  0@240r
%vreg10 [48r,64r:0)  0@48r
%vreg11 [64r,112r:0)  0@64r
%vreg12 [80r,128r:0)  0@80r
%vreg14 [608r,624r:0)  0@608r
%vreg15 [624r,752r:0)  0@624r
%vreg16 [720r,768r:0)  0@720r
%vreg20 [672r,688r:0)[688r,704r:1)  0@672r 1@688r
%vreg21 [656r,672r:0)  0@656r
%vreg22 [640r,704r:0)  0@640r
%vreg25 [464r,480r:0)  0@464r
%vreg27 [448r,480r:0)  0@448r
%vreg30 [528r,544r:0)[544r,560r:1)  0@528r 1@544r
%vreg31 [512r,528r:0)  0@512r
RegMasks: 144r 784r
********** MACHINEINSTRS **********
# Machine code for function prepare_new_block: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=8, align=8, at location [SP+8]
  fi#1: size=4, align=4, at location [SP+8]
Function Live Ins: %RDI in %vreg0

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI
16B		%vreg0<def> = COPY %RDI; GR64:%vreg0
32B		%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
48B		%vreg10<def> = MOV64ri <ga:@prepare_new_block>; GR64:%vreg10
64B		%vreg11<def> = COPY %vreg10; GR64:%vreg11,%vreg10
80B		%vreg12<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg12
96B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
112B		%RDI<def> = COPY %vreg11; GR64:%vreg11
128B		%RSI<def> = COPY %vreg12; GR64:%vreg12
144B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
160B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
192B		STACKMAP 0, 0, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1](align=4) LD8[FixedStack0] GR64:%vreg1
208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%s.addr] GR64:%vreg1
240B		%vreg9<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg9
256B		MOV32mi %vreg9, 1, %noreg, 108, %noreg, 0; mem:ST4[%nblock] GR64:%vreg9
272B		%vreg7<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg7
288B		MOV32mi %vreg7, 1, %noreg, 116, %noreg, 0; mem:ST4[%numZ] GR64:%vreg7
304B		%vreg5<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg5
320B		MOV32mi %vreg5, 1, %noreg, 120, %noreg, 0; mem:ST4[%state_out_pos] GR64:%vreg5
336B		%vreg3<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg3
352B		MOV32mi %vreg3, 1, %noreg, 648, %noreg, -1; mem:ST4[%blockCRC] GR64:%vreg3
368B		MOV32mi <fi#1>, 1, %noreg, 0, %noreg, 0; mem:ST4[%i]
	    Successors according to CFG: BB#1

384B	BB#1: derived from LLVM BB %for.cond
	    Predecessors according to CFG: BB#0 BB#3
400B		CMP32mi <fi#1>, 1, %noreg, 0, %noreg, 256, %EFLAGS<imp-def>; mem:LD4[%i]
416B		JGE_1 <BB#4>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#4 BB#2

432B	BB#2: derived from LLVM BB %for.body
	    Predecessors according to CFG: BB#1
448B		%vreg27<def> = MOVSX64rm32 <fi#1>, 1, %noreg, 0, %noreg; mem:LD4[%i] GR64_NOSP:%vreg27
464B		%vreg25<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg25
480B		MOV8mi %vreg25, 1, %vreg27, 128, %noreg, 0; mem:ST1[%arrayidx] GR64:%vreg25 GR64_NOSP:%vreg27
	    Successors according to CFG: BB#3

496B	BB#3: derived from LLVM BB %for.inc
	    Predecessors according to CFG: BB#2
512B		%vreg31<def> = MOV32rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD4[%i] GR32:%vreg31
528B		%vreg30<def> = COPY %vreg31; GR32:%vreg30,%vreg31
544B		%vreg30<def,tied1> = ADD32ri8 %vreg30<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg30
560B		MOV32mr <fi#1>, 1, %noreg, 0, %noreg, %vreg30; mem:ST4[%i] GR32:%vreg30
576B		JMP_1 <BB#1>
	    Successors according to CFG: BB#1

592B	BB#4: derived from LLVM BB %for.end
	    Predecessors according to CFG: BB#1
608B		%vreg14<def> = MOV64ri <ga:@prepare_new_block>; GR64:%vreg14
624B		%vreg15<def> = COPY %vreg14; GR64:%vreg15,%vreg14
640B		%vreg22<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg22
656B		%vreg21<def> = MOV32rm %vreg22, 1, %noreg, 660, %noreg; mem:LD4[%blockNo] GR32:%vreg21 GR64:%vreg22
672B		%vreg20<def> = COPY %vreg21; GR32:%vreg20,%vreg21
688B		%vreg20<def,tied1> = ADD32ri8 %vreg20<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg20
704B		MOV32mr %vreg22, 1, %noreg, 660, %noreg, %vreg20; mem:ST4[%blockNo] GR64:%vreg22 GR32:%vreg20
720B		%vreg16<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg16
736B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
752B		%RDI<def> = COPY %vreg15; GR64:%vreg15
768B		%RSI<def> = COPY %vreg16; GR64:%vreg16
784B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
800B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
816B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
832B		STACKMAP 1, 0, ...
848B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
864B		RETQ

# End machine code for function prepare_new_block.

********** SIMPLE REGISTER COALESCING **********
********** Function: prepare_new_block
********** JOINING INTERVALS ***********
for.cond:
for.body:
for.inc:
528B	%vreg30<def> = COPY %vreg31; GR32:%vreg30,%vreg31
	Considering merging to GR32 with %vreg31 in %vreg30
		RHS = %vreg31 [512r,528r:0)  0@512r
		LHS = %vreg30 [528r,544r:0)[544r,560r:1)  0@528r 1@544r
		merge %vreg30:0@528r into %vreg31:0@512r --> @512r
		erased:	528r	%vreg30<def> = COPY %vreg31; GR32:%vreg30,%vreg31
		updated: 512B	%vreg30<def> = MOV32rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD4[%i] GR32:%vreg30
	Success: %vreg31 -> %vreg30
	Result = %vreg30 [512r,544r:0)[544r,560r:1)  0@512r 1@544r
entry:
16B	%vreg0<def> = COPY %RDI; GR64:%vreg0
	Considering merging %vreg0 with %RDI
	Can only merge into reserved registers.
112B	%RDI<def> = COPY %vreg11; GR64:%vreg11
	Considering merging %vreg11 with %RDI
	Can only merge into reserved registers.
128B	%RSI<def> = COPY %vreg12; GR64:%vreg12
	Considering merging %vreg12 with %RSI
	Can only merge into reserved registers.
for.end:
752B	%RDI<def> = COPY %vreg15; GR64:%vreg15
	Considering merging %vreg15 with %RDI
	Can only merge into reserved registers.
768B	%RSI<def> = COPY %vreg16; GR64:%vreg16
	Considering merging %vreg16 with %RSI
	Can only merge into reserved registers.
32B	%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
	Considering merging to GR64 with %vreg0 in %vreg1
		RHS = %vreg0 [16r,32r:0)  0@16r
		LHS = %vreg1 [32r,224r:0)  0@32r
		merge %vreg1:0@32r into %vreg0:0@16r --> @16r
		erased:	32r	%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
		updated: 16B	%vreg1<def> = COPY %RDI; GR64:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [16r,224r:0)  0@16r
64B	%vreg11<def> = COPY %vreg10; GR64:%vreg11,%vreg10
	Considering merging to GR64 with %vreg10 in %vreg11
		RHS = %vreg10 [48r,64r:0)  0@48r
		LHS = %vreg11 [64r,112r:0)  0@64r
		merge %vreg11:0@64r into %vreg10:0@48r --> @48r
		erased:	64r	%vreg11<def> = COPY %vreg10; GR64:%vreg11,%vreg10
		updated: 48B	%vreg11<def> = MOV64ri <ga:@prepare_new_block>; GR64:%vreg11
	Success: %vreg10 -> %vreg11
	Result = %vreg11 [48r,112r:0)  0@48r
624B	%vreg15<def> = COPY %vreg14; GR64:%vreg15,%vreg14
	Considering merging to GR64 with %vreg14 in %vreg15
		RHS = %vreg14 [608r,624r:0)  0@608r
		LHS = %vreg15 [624r,752r:0)  0@624r
		merge %vreg15:0@624r into %vreg14:0@608r --> @608r
		erased:	624r	%vreg15<def> = COPY %vreg14; GR64:%vreg15,%vreg14
		updated: 608B	%vreg15<def> = MOV64ri <ga:@prepare_new_block>; GR64:%vreg15
	Success: %vreg14 -> %vreg15
	Result = %vreg15 [608r,752r:0)  0@608r
672B	%vreg20<def> = COPY %vreg21; GR32:%vreg20,%vreg21
	Considering merging to GR32 with %vreg21 in %vreg20
		RHS = %vreg21 [656r,672r:0)  0@656r
		LHS = %vreg20 [672r,688r:0)[688r,704r:1)  0@672r 1@688r
		merge %vreg20:0@672r into %vreg21:0@656r --> @656r
		erased:	672r	%vreg20<def> = COPY %vreg21; GR32:%vreg20,%vreg21
		updated: 656B	%vreg20<def> = MOV32rm %vreg22, 1, %noreg, 660, %noreg; mem:LD4[%blockNo] GR32:%vreg20 GR64:%vreg22
	Success: %vreg21 -> %vreg20
	Result = %vreg20 [656r,688r:0)[688r,704r:1)  0@656r 1@688r
112B	%RDI<def> = COPY %vreg11; GR64:%vreg11
	Considering merging %vreg11 with %RDI
	Can only merge into reserved registers.
752B	%RDI<def> = COPY %vreg15; GR64:%vreg15
	Considering merging %vreg15 with %RDI
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
DIL [0B,16r:0)[112r,144r:2)[752r,784r:1)  0@0B-phi 1@752r 2@112r
%vreg1 [16r,224r:0)  0@16r
%vreg3 [336r,352r:0)  0@336r
%vreg5 [304r,320r:0)  0@304r
%vreg7 [272r,288r:0)  0@272r
%vreg9 [240r,256r:0)  0@240r
%vreg11 [48r,112r:0)  0@48r
%vreg12 [80r,128r:0)  0@80r
%vreg15 [608r,752r:0)  0@608r
%vreg16 [720r,768r:0)  0@720r
%vreg20 [656r,688r:0)[688r,704r:1)  0@656r 1@688r
%vreg22 [640r,704r:0)  0@640r
%vreg25 [464r,480r:0)  0@464r
%vreg27 [448r,480r:0)  0@448r
%vreg30 [512r,544r:0)[544r,560r:1)  0@512r 1@544r
RegMasks: 144r 784r
********** MACHINEINSTRS **********
# Machine code for function prepare_new_block: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=8, align=8, at location [SP+8]
  fi#1: size=4, align=4, at location [SP+8]
Function Live Ins: %RDI in %vreg0

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI
16B		%vreg1<def> = COPY %RDI; GR64:%vreg1
48B		%vreg11<def> = MOV64ri <ga:@prepare_new_block>; GR64:%vreg11
80B		%vreg12<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg12
96B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
112B		%RDI<def> = COPY %vreg11; GR64:%vreg11
128B		%RSI<def> = COPY %vreg12; GR64:%vreg12
144B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
160B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
192B		STACKMAP 0, 0, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1](align=4) LD8[FixedStack0] GR64:%vreg1
208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%s.addr] GR64:%vreg1
240B		%vreg9<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg9
256B		MOV32mi %vreg9, 1, %noreg, 108, %noreg, 0; mem:ST4[%nblock] GR64:%vreg9
272B		%vreg7<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg7
288B		MOV32mi %vreg7, 1, %noreg, 116, %noreg, 0; mem:ST4[%numZ] GR64:%vreg7
304B		%vreg5<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg5
320B		MOV32mi %vreg5, 1, %noreg, 120, %noreg, 0; mem:ST4[%state_out_pos] GR64:%vreg5
336B		%vreg3<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg3
352B		MOV32mi %vreg3, 1, %noreg, 648, %noreg, -1; mem:ST4[%blockCRC] GR64:%vreg3
368B		MOV32mi <fi#1>, 1, %noreg, 0, %noreg, 0; mem:ST4[%i]
	    Successors according to CFG: BB#1

384B	BB#1: derived from LLVM BB %for.cond
	    Predecessors according to CFG: BB#0 BB#3
400B		CMP32mi <fi#1>, 1, %noreg, 0, %noreg, 256, %EFLAGS<imp-def>; mem:LD4[%i]
416B		JGE_1 <BB#4>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#4 BB#2

432B	BB#2: derived from LLVM BB %for.body
	    Predecessors according to CFG: BB#1
448B		%vreg27<def> = MOVSX64rm32 <fi#1>, 1, %noreg, 0, %noreg; mem:LD4[%i] GR64_NOSP:%vreg27
464B		%vreg25<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg25
480B		MOV8mi %vreg25, 1, %vreg27, 128, %noreg, 0; mem:ST1[%arrayidx] GR64:%vreg25 GR64_NOSP:%vreg27
	    Successors according to CFG: BB#3

496B	BB#3: derived from LLVM BB %for.inc
	    Predecessors according to CFG: BB#2
512B		%vreg30<def> = MOV32rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD4[%i] GR32:%vreg30
544B		%vreg30<def,tied1> = ADD32ri8 %vreg30<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg30
560B		MOV32mr <fi#1>, 1, %noreg, 0, %noreg, %vreg30; mem:ST4[%i] GR32:%vreg30
576B		JMP_1 <BB#1>
	    Successors according to CFG: BB#1

592B	BB#4: derived from LLVM BB %for.end
	    Predecessors according to CFG: BB#1
608B		%vreg15<def> = MOV64ri <ga:@prepare_new_block>; GR64:%vreg15
640B		%vreg22<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg22
656B		%vreg20<def> = MOV32rm %vreg22, 1, %noreg, 660, %noreg; mem:LD4[%blockNo] GR32:%vreg20 GR64:%vreg22
688B		%vreg20<def,tied1> = ADD32ri8 %vreg20<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg20
704B		MOV32mr %vreg22, 1, %noreg, 660, %noreg, %vreg20; mem:ST4[%blockNo] GR64:%vreg22 GR32:%vreg20
720B		%vreg16<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg16
736B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
752B		%RDI<def> = COPY %vreg15; GR64:%vreg15
768B		%RSI<def> = COPY %vreg16; GR64:%vreg16
784B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
800B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
816B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
832B		STACKMAP 1, 0, ...
848B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
864B		RETQ

# End machine code for function prepare_new_block.

AllocationOrder(SEGMENT_REG) = [ ]
********** GREEDY REGISTER ALLOCATION **********
********** Function: prepare_new_block
********** INTERVALS **********
DIL [0B,16r:0)[112r,144r:2)[752r,784r:1)  0@0B-phi 1@752r 2@112r
%vreg1 [16r,224r:0)  0@16r
%vreg3 [336r,352r:0)  0@336r
%vreg5 [304r,320r:0)  0@304r
%vreg7 [272r,288r:0)  0@272r
%vreg9 [240r,256r:0)  0@240r
%vreg11 [48r,112r:0)  0@48r
%vreg12 [80r,128r:0)  0@80r
%vreg15 [608r,752r:0)  0@608r
%vreg16 [720r,768r:0)  0@720r
%vreg20 [656r,688r:0)[688r,704r:1)  0@656r 1@688r
%vreg22 [640r,704r:0)  0@640r
%vreg25 [464r,480r:0)  0@464r
%vreg27 [448r,480r:0)  0@448r
%vreg30 [512r,544r:0)[544r,560r:1)  0@512r 1@544r
RegMasks: 144r 784r
********** MACHINEINSTRS **********
# Machine code for function prepare_new_block: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=8, align=8, at location [SP+8]
  fi#1: size=4, align=4, at location [SP+8]
Function Live Ins: %RDI in %vreg0

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI
16B		%vreg1<def> = COPY %RDI; GR64:%vreg1
48B		%vreg11<def> = MOV64ri <ga:@prepare_new_block>; GR64:%vreg11
80B		%vreg12<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg12
96B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
112B		%RDI<def> = COPY %vreg11; GR64:%vreg11
128B		%RSI<def> = COPY %vreg12; GR64:%vreg12
144B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
160B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
192B		STACKMAP 0, 0, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1](align=4) LD8[FixedStack0] GR64:%vreg1
208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%s.addr] GR64:%vreg1
240B		%vreg9<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg9
256B		MOV32mi %vreg9, 1, %noreg, 108, %noreg, 0; mem:ST4[%nblock] GR64:%vreg9
272B		%vreg7<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg7
288B		MOV32mi %vreg7, 1, %noreg, 116, %noreg, 0; mem:ST4[%numZ] GR64:%vreg7
304B		%vreg5<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg5
320B		MOV32mi %vreg5, 1, %noreg, 120, %noreg, 0; mem:ST4[%state_out_pos] GR64:%vreg5
336B		%vreg3<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg3
352B		MOV32mi %vreg3, 1, %noreg, 648, %noreg, -1; mem:ST4[%blockCRC] GR64:%vreg3
368B		MOV32mi <fi#1>, 1, %noreg, 0, %noreg, 0; mem:ST4[%i]
	    Successors according to CFG: BB#1

384B	BB#1: derived from LLVM BB %for.cond
	    Predecessors according to CFG: BB#0 BB#3
400B		CMP32mi <fi#1>, 1, %noreg, 0, %noreg, 256, %EFLAGS<imp-def>; mem:LD4[%i]
416B		JGE_1 <BB#4>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#4 BB#2

432B	BB#2: derived from LLVM BB %for.body
	    Predecessors according to CFG: BB#1
448B		%vreg27<def> = MOVSX64rm32 <fi#1>, 1, %noreg, 0, %noreg; mem:LD4[%i] GR64_NOSP:%vreg27
464B		%vreg25<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg25
480B		MOV8mi %vreg25, 1, %vreg27, 128, %noreg, 0; mem:ST1[%arrayidx] GR64:%vreg25 GR64_NOSP:%vreg27
	    Successors according to CFG: BB#3

496B	BB#3: derived from LLVM BB %for.inc
	    Predecessors according to CFG: BB#2
512B		%vreg30<def> = MOV32rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD4[%i] GR32:%vreg30
544B		%vreg30<def,tied1> = ADD32ri8 %vreg30<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg30
560B		MOV32mr <fi#1>, 1, %noreg, 0, %noreg, %vreg30; mem:ST4[%i] GR32:%vreg30
576B		JMP_1 <BB#1>
	    Successors according to CFG: BB#1

592B	BB#4: derived from LLVM BB %for.end
	    Predecessors according to CFG: BB#1
608B		%vreg15<def> = MOV64ri <ga:@prepare_new_block>; GR64:%vreg15
640B		%vreg22<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg22
656B		%vreg20<def> = MOV32rm %vreg22, 1, %noreg, 660, %noreg; mem:LD4[%blockNo] GR32:%vreg20 GR64:%vreg22
688B		%vreg20<def,tied1> = ADD32ri8 %vreg20<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg20
704B		MOV32mr %vreg22, 1, %noreg, 660, %noreg, %vreg20; mem:ST4[%blockNo] GR64:%vreg22 GR32:%vreg20
720B		%vreg16<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg16
736B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
752B		%RDI<def> = COPY %vreg15; GR64:%vreg15
768B		%RSI<def> = COPY %vreg16; GR64:%vreg16
784B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
800B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
816B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
832B		STACKMAP 1, 0, ...
848B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
864B		RETQ

# End machine code for function prepare_new_block.


selectOrSplit GR64:%vreg1 [16r,224r:0)  0@16r w=4.983553e-03
hints: %RDI
missed hint %RDI
assigning %vreg1 to %RBX: BH [16r,224r:0)  0@16r BL [16r,224r:0)  0@16r

selectOrSplit GR64:%vreg11 [48r,112r:0)  0@48r w=2.176724e-03
hints: %RDI
assigning %vreg11 to %RDI: DIL [48r,112r:0)  0@48r

selectOrSplit GR64:%vreg12 [80r,128r:0)  0@80r w=4.508928e-03
hints: %RSI
assigning %vreg12 to %RSI: SIL [80r,128r:0)  0@80r

selectOrSplit GR64:%vreg15 [608r,752r:0)  0@608r w=1.856618e-03
hints: %RDI
assigning %vreg15 to %RDI: DIL [608r,752r:0)  0@608r

selectOrSplit GR64:%vreg16 [720r,768r:0)  0@720r w=4.508928e-03
hints: %RSI
assigning %vreg16 to %RSI: SIL [720r,768r:0)  0@720r

selectOrSplit GR64:%vreg9 [240r,256r:0)  0@240r w=inf
assigning %vreg9 to %RAX: AH [240r,256r:0)  0@240r AL [240r,256r:0)  0@240r

selectOrSplit GR64:%vreg7 [272r,288r:0)  0@272r w=inf
assigning %vreg7 to %RAX: AH [272r,288r:0)  0@272r AL [272r,288r:0)  0@272r

selectOrSplit GR64:%vreg5 [304r,320r:0)  0@304r w=inf
assigning %vreg5 to %RAX: AH [304r,320r:0)  0@304r AL [304r,320r:0)  0@304r

selectOrSplit GR64:%vreg3 [336r,352r:0)  0@336r w=inf
assigning %vreg3 to %RAX: AH [336r,352r:0)  0@336r AL [336r,352r:0)  0@336r

selectOrSplit GR64_NOSP:%vreg27 [448r,480r:0)  0@448r w=4.629630e-03
AllocationOrder(GR64_NOSP) = [ %RAX %RCX %RDX %RSI %RDI %R8 %R9 %R10 %R11 %RBX %R14 %R15 %R12 %R13 ]
assigning %vreg27 to %RAX: AH [448r,480r:0)  0@448r AL [448r,480r:0)  0@448r

selectOrSplit GR64:%vreg25 [464r,480r:0)  0@464r w=inf
assigning %vreg25 to %RCX: CH [464r,480r:0)  0@464r CL [464r,480r:0)  0@464r

selectOrSplit GR32:%vreg30 [512r,544r:0)[544r,560r:1)  0@512r 1@544r w=inf
assigning %vreg30 to %EAX: AH [512r,544r:0)[544r,560r:1)  0@512r 1@544r AL [512r,544r:0)[544r,560r:1)  0@512r 1@544r

selectOrSplit GR64:%vreg22 [640r,704r:0)  0@640r w=6.465517e-03
assigning %vreg22 to %RAX: AH [640r,704r:0)  0@640r AL [640r,704r:0)  0@640r

selectOrSplit GR32:%vreg20 [656r,688r:0)[688r,704r:1)  0@656r 1@688r w=inf
assigning %vreg20 to %ECX: CH [656r,688r:0)[688r,704r:1)  0@656r 1@688r CL [656r,688r:0)[688r,704r:1)  0@656r 1@688r

********** STACK TRANSFORMATION METADATA **********
********** Function: prepare_new_block
********** REGISTER MAP **********
[%vreg1 -> %RBX] GR64
[%vreg3 -> %RAX] GR64
[%vreg5 -> %RAX] GR64
[%vreg7 -> %RAX] GR64
[%vreg9 -> %RAX] GR64
[%vreg11 -> %RDI] GR64
[%vreg12 -> %RSI] GR64
[%vreg15 -> %RDI] GR64
[%vreg16 -> %RSI] GR64
[%vreg20 -> %ECX] GR32
[%vreg22 -> %RAX] GR64
[%vreg25 -> %RCX] GR64
[%vreg27 -> %RAX] GR64_NOSP
[%vreg30 -> %EAX] GR32


Stackmap 0:
  STACKMAP 0, 0, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1](align=4) LD8[FixedStack0] GR64:%vreg1

i32* %i: in stack slot 1 (size: 4)
%struct.EState* %s: in register %RBX (vreg 1)
%struct.EState** %s.addr: in stack slot 0 (size: 8)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, ...


Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1](align=4) LD8[FixedStack0] GR64:%vreg1
  -> Call instruction SlotIndex 144B, searching vregs 0 -> 32 and stack slots -1 -> 2

  STACKMAP 1, 0, ...
  -> Call instruction SlotIndex 784B, searching vregs 0 -> 32 and stack slots -1 -> 2

********** REWRITE VIRTUAL REGISTERS **********
********** Function: prepare_new_block
********** REGISTER MAP **********
[%vreg1 -> %RBX] GR64
[%vreg3 -> %RAX] GR64
[%vreg5 -> %RAX] GR64
[%vreg7 -> %RAX] GR64
[%vreg9 -> %RAX] GR64
[%vreg11 -> %RDI] GR64
[%vreg12 -> %RSI] GR64
[%vreg15 -> %RDI] GR64
[%vreg16 -> %RSI] GR64
[%vreg20 -> %ECX] GR32
[%vreg22 -> %RAX] GR64
[%vreg25 -> %RCX] GR64
[%vreg27 -> %RAX] GR64_NOSP
[%vreg30 -> %EAX] GR32

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI
16B		%vreg1<def> = COPY %RDI; GR64:%vreg1
48B		%vreg11<def> = MOV64ri <ga:@prepare_new_block>; GR64:%vreg11
80B		%vreg12<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg12
96B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
112B		%RDI<def> = COPY %vreg11<kill>; GR64:%vreg11
128B		%RSI<def> = COPY %vreg12<kill>; GR64:%vreg12
144B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
160B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
192B		STACKMAP 0, 0, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1](align=4) LD8[FixedStack0] GR64:%vreg1
208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1<kill>; mem:ST8[%s.addr] GR64:%vreg1
240B		%vreg9<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg9
256B		MOV32mi %vreg9<kill>, 1, %noreg, 108, %noreg, 0; mem:ST4[%nblock] GR64:%vreg9
272B		%vreg7<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg7
288B		MOV32mi %vreg7<kill>, 1, %noreg, 116, %noreg, 0; mem:ST4[%numZ] GR64:%vreg7
304B		%vreg5<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg5
320B		MOV32mi %vreg5<kill>, 1, %noreg, 120, %noreg, 0; mem:ST4[%state_out_pos] GR64:%vreg5
336B		%vreg3<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg3
352B		MOV32mi %vreg3<kill>, 1, %noreg, 648, %noreg, -1; mem:ST4[%blockCRC] GR64:%vreg3
368B		MOV32mi <fi#1>, 1, %noreg, 0, %noreg, 0; mem:ST4[%i]
	    Successors according to CFG: BB#1
> %RBX<def> = COPY %RDI
> %RDI<def> = MOV64ri <ga:@prepare_new_block>
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 0, 0, 0, <fi#1>, 0, %RBX, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1](align=4) LD8[FixedStack0]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %RBX<kill>; mem:ST8[%s.addr]
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 108, %noreg, 0; mem:ST4[%nblock]
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 116, %noreg, 0; mem:ST4[%numZ]
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 120, %noreg, 0; mem:ST4[%state_out_pos]
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 648, %noreg, -1; mem:ST4[%blockCRC]
> MOV32mi <fi#1>, 1, %noreg, 0, %noreg, 0; mem:ST4[%i]
384B	BB#1: derived from LLVM BB %for.cond
	    Predecessors according to CFG: BB#0 BB#3
400B		CMP32mi <fi#1>, 1, %noreg, 0, %noreg, 256, %EFLAGS<imp-def>; mem:LD4[%i]
416B		JGE_1 <BB#4>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#4 BB#2
> CMP32mi <fi#1>, 1, %noreg, 0, %noreg, 256, %EFLAGS<imp-def>; mem:LD4[%i]
> JGE_1 <BB#4>, %EFLAGS<imp-use,kill>
432B	BB#2: derived from LLVM BB %for.body
	    Predecessors according to CFG: BB#1
448B		%vreg27<def> = MOVSX64rm32 <fi#1>, 1, %noreg, 0, %noreg; mem:LD4[%i] GR64_NOSP:%vreg27
464B		%vreg25<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg25
480B		MOV8mi %vreg25<kill>, 1, %vreg27<kill>, 128, %noreg, 0; mem:ST1[%arrayidx] GR64:%vreg25 GR64_NOSP:%vreg27
	    Successors according to CFG: BB#3
> %RAX<def> = MOVSX64rm32 <fi#1>, 1, %noreg, 0, %noreg; mem:LD4[%i]
> %RCX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV8mi %RCX<kill>, 1, %RAX<kill>, 128, %noreg, 0; mem:ST1[%arrayidx]
496B	BB#3: derived from LLVM BB %for.inc
	    Predecessors according to CFG: BB#2
512B		%vreg30<def> = MOV32rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD4[%i] GR32:%vreg30
544B		%vreg30<def,tied1> = ADD32ri8 %vreg30<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg30
560B		MOV32mr <fi#1>, 1, %noreg, 0, %noreg, %vreg30<kill>; mem:ST4[%i] GR32:%vreg30
576B		JMP_1 <BB#1>
	    Successors according to CFG: BB#1
> %EAX<def> = MOV32rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD4[%i]
> %EAX<def,tied1> = ADD32ri8 %EAX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV32mr <fi#1>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%i]
> JMP_1 <BB#1>
592B	BB#4: derived from LLVM BB %for.end
	    Predecessors according to CFG: BB#1
608B		%vreg15<def> = MOV64ri <ga:@prepare_new_block>; GR64:%vreg15
640B		%vreg22<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg22
656B		%vreg20<def> = MOV32rm %vreg22, 1, %noreg, 660, %noreg; mem:LD4[%blockNo] GR32:%vreg20 GR64:%vreg22
688B		%vreg20<def,tied1> = ADD32ri8 %vreg20<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg20
704B		MOV32mr %vreg22<kill>, 1, %noreg, 660, %noreg, %vreg20<kill>; mem:ST4[%blockNo] GR64:%vreg22 GR32:%vreg20
720B		%vreg16<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg16
736B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
752B		%RDI<def> = COPY %vreg15<kill>; GR64:%vreg15
768B		%RSI<def> = COPY %vreg16<kill>; GR64:%vreg16
784B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
800B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
816B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
832B		STACKMAP 1, 0, ...
848B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
864B		RETQ
> %RDI<def> = MOV64ri <ga:@prepare_new_block>
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 660, %noreg; mem:LD4[%blockNo]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 660, %noreg, %ECX<kill>; mem:ST4[%blockNo]
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 1, 0, ...
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> RETQ
Computing live-in reg-units in ABI blocks.
0B	BB#0 DIL#0 SIL#0
Created 2 new intervals.
********** INTERVALS **********
DIL [0B,32r:0)[144r,176r:7)[1024r,1040r:2)[1984r,2000r:4)[2208r,2224r:3)[2880r,2896r:6)[3200r,3216r:5)[3680r,3712r:1)  0@0B-phi 1@3680r 2@1024r 3@2208r 4@1984r 5@3200r 6@2880r 7@144r
SIL [0B,16r:0)[160r,176r:2)[3696r,3712r:1)  0@0B-phi 1@3696r 2@160r
%vreg0 [32r,48r:0)  0@32r
%vreg1 [48r,256r:0)  0@48r
%vreg2 [16r,64r:0)  0@16r
%vreg3 [64r,272r:0)  0@64r
%vreg5 [80r,96r:0)  0@80r
%vreg6 [96r,144r:0)  0@96r
%vreg7 [112r,160r:0)  0@112r
%vreg11 [416r,432r:0)  0@416r
%vreg13 [400r,416r:0)  0@400r
%vreg14 [384r,400r:0)  0@384r
%vreg18 [560r,576r:0)  0@560r
%vreg19 [544r,560r:0)  0@544r
%vreg20 [768r,848r:0)  0@768r
%vreg21 [704r,720r:0)  0@704r
%vreg22 [720r,736r:0)  0@720r
%vreg23 [736r,752r:0)[752r,784r:1)  0@736r 1@752r
%vreg24 [784r,800r:0)[800r,800d:1)  0@784r 1@800r
%vreg25 [848r,864r:0)  0@848r
%vreg31 [2736r,2752r:0)  0@2736r
%vreg32 [2720r,2736r:0)  0@2720r
%vreg34 [2704r,2752r:0)  0@2704r
%vreg35 [2688r,2704r:0)  0@2688r
%vreg39 [2928r,2992r:0)  0@2928r
%vreg40 [2848r,2880r:0)  0@2848r
%vreg43 [3104r,3120r:0)  0@3104r
%vreg46 [3248r,3312r:0)  0@3248r
%vreg47 [3168r,3200r:0)  0@3168r
%vreg51 [3392r,3408r:0)  0@3392r
%vreg53 [3376r,3408r:0)  0@3376r
%vreg54 [3360r,3376r:0)  0@3360r
%vreg56 [3504r,3520r:0)  0@3504r
%vreg62 [1840r,1856r:0)  0@1840r
%vreg63 [1824r,1840r:0)  0@1824r
%vreg65 [1808r,1856r:0)  0@1808r
%vreg66 [1792r,1808r:0)  0@1792r
%vreg69 [2112r,2128r:0)  0@2112r
%vreg72 [2032r,2096r:0)  0@2032r
%vreg73 [1952r,1984r:0)  0@1952r
%vreg76 [2256r,2320r:0)  0@2256r
%vreg77 [2176r,2208r:0)  0@2176r
%vreg81 [2400r,2416r:0)  0@2400r
%vreg83 [2384r,2416r:0)  0@2384r
%vreg84 [2368r,2384r:0)  0@2368r
%vreg86 [2512r,2528r:0)  0@2512r
%vreg91 [1584r,1600r:0)  0@1584r
%vreg94 [1552r,1568r:0)  0@1552r
%vreg96 [1536r,1568r:0)  0@1536r
%vreg97 [1520r,1536r:0)  0@1520r
%vreg99 [1408r,1424r:0)  0@1408r
%vreg102 [1376r,1392r:0)  0@1376r
%vreg104 [1360r,1392r:0)  0@1360r
%vreg105 [1344r,1360r:0)  0@1344r
%vreg108 [1088r,1216r:0)  0@1088r
%vreg109 [1104r,1232r:0)  0@1104r
%vreg110 [1216r,1232r:0)[1232r,1248r:1)  0@1216r 1@1232r
%vreg112 [1184r,1200r:0)  0@1184r
%vreg115 [1072r,1168r:0)  0@1072r
%vreg116 [992r,1024r:0)  0@992r
%vreg118 [3792r,3808r:0)  0@3792r
%vreg119 [3616r,3632r:0)  0@3616r
%vreg120 [3632r,3680r:0)  0@3632r
%vreg121 [3648r,3696r:0)  0@3648r
RegMasks: 176r 1040r 2000r 2224r 2896r 3216r 3712r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzCompress: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=4, align=4, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=4, align=4, at location [SP+8]
  fi#3: size=1, align=1, at location [SP+8]
  fi#4: size=8, align=8, at location [SP+8]
Jump Tables:
  jt#0:  BB#9 BB#10 BB#17 BB#26
Function Live Ins: %RDI in %vreg0, %ESI in %vreg2

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI %ESI
16B		%vreg2<def> = COPY %ESI; GR32:%vreg2
32B		%vreg0<def> = COPY %RDI; GR64:%vreg0
48B		%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
64B		%vreg3<def> = COPY %vreg2; GR32:%vreg3,%vreg2
80B		%vreg5<def> = MOV64ri <ga:@BZ2_bzCompress>; GR64:%vreg5
96B		%vreg6<def> = COPY %vreg5; GR64:%vreg6,%vreg5
112B		%vreg7<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg7
128B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
144B		%RDI<def> = COPY %vreg6; GR64:%vreg6
160B		%RSI<def> = COPY %vreg7; GR64:%vreg7
176B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
192B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
208B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		STACKMAP 0, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#3>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, %vreg1, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack3](align=1) LD8[FixedStack0](align=4) LD8[FixedStack4] LD8[FixedStack1] GR32:%vreg3 GR64:%vreg1
240B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
256B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%strm.addr] GR64:%vreg1
272B		MOV32mr <fi#2>, 1, %noreg, 0, %noreg, %vreg3; mem:ST4[%action.addr] GR32:%vreg3
288B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%strm.addr]
304B		JNE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

320B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
336B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
352B		JMP_1 <BB#38>
	    Successors according to CFG: BB#38

368B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0
384B		%vreg14<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg14
400B		%vreg13<def> = MOV64rm %vreg14, 1, %noreg, 48, %noreg; mem:LD8[%state] GR64:%vreg13,%vreg14
416B		%vreg11<def> = COPY %vreg13; GR64:%vreg11,%vreg13
432B		MOV64mr <fi#4>, 1, %noreg, 0, %noreg, %vreg11; mem:ST8[%s] GR64:%vreg11
448B		CMP64mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%s]
464B		JNE_1 <BB#4>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#4 BB#3

480B	BB#3: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#2
496B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
512B		JMP_1 <BB#38>
	    Successors according to CFG: BB#38

528B	BB#4: derived from LLVM BB %if.end.3
	    Predecessors according to CFG: BB#2
544B		%vreg19<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg19
560B		%vreg18<def> = MOV64rm %vreg19, 1, %noreg, 0, %noreg; mem:LD8[%strm4] GR64:%vreg18,%vreg19
576B		CMP64rm %vreg18, <fi#1>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD8[%strm.addr] GR64:%vreg18
592B		JE_1 <BB#6>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#6 BB#5

608B	BB#5: derived from LLVM BB %if.then.6
	    Predecessors according to CFG: BB#4
624B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
640B		JMP_1 <BB#38>
	    Successors according to CFG: BB#38

656B	BB#6: derived from LLVM BB %if.end.7
	    Predecessors according to CFG: BB#4
672B		JMP_1 <BB#7>
	    Successors according to CFG: BB#7

688B	BB#7: derived from LLVM BB %preswitch
	    Predecessors according to CFG: BB#6 BB#15 BB#13
704B		%vreg21<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg21
720B		%vreg22<def> = MOV32rm %vreg21, 1, %noreg, 8, %noreg; mem:LD4[%mode] GR32:%vreg22 GR64:%vreg21
736B		%vreg23<def> = COPY %vreg22; GR32:%vreg23,%vreg22
752B		%vreg23<def,tied1> = DEC32r %vreg23<tied0>, %EFLAGS<imp-def,dead>; GR32:%vreg23
768B		%vreg20<def> = SUBREG_TO_REG 0, %vreg23, 4; GR64_NOSP:%vreg20 GR32:%vreg23
784B		%vreg24<def> = COPY %vreg23; GR32:%vreg24,%vreg23
800B		%vreg24<def,dead,tied1> = SUB32ri8 %vreg24<tied0>, 3, %EFLAGS<imp-def>; GR32:%vreg24
816B		JA_1 <BB#37>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#37 BB#8

832B	BB#8: derived from LLVM BB %preswitch
	    Predecessors according to CFG: BB#7
848B		%vreg25<def> = MOV64rm %noreg, 8, %vreg20, <jt#0>, %noreg; mem:LD8[JumpTable] GR64:%vreg25 GR64_NOSP:%vreg20
864B		JMP64r %vreg25; GR64:%vreg25
	    Successors according to CFG: BB#9 BB#10 BB#17 BB#26

880B	BB#9: derived from LLVM BB %sw.bb
	    Predecessors according to CFG: BB#8
896B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -1; mem:ST4[%retval]
912B		JMP_1 <BB#38>
	    Successors according to CFG: BB#38

928B	BB#10: derived from LLVM BB %sw.bb.8
	    Predecessors according to CFG: BB#8
944B		CMP32mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%action.addr]
960B		JNE_1 <BB#12>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#12 BB#11

976B	BB#11: derived from LLVM BB %if.then.10
	    Predecessors according to CFG: BB#10
992B		%vreg116<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg116
1008B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1024B		%RDI<def> = COPY %vreg116; GR64:%vreg116
1040B		CALL64pcrel32 <ga:@handle_compress>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %AL<imp-def>
1056B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1072B		%vreg115<def> = COPY %AL<kill>; GR8:%vreg115
1088B		%vreg108<def> = MOV32ri 4294967294; GR32:%vreg108
1104B		%vreg109<def> = MOV32ri 1; GR32:%vreg109
1120B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1136B		STACKMAP 1, 0, 0, <fi#3>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack3](align=1) LD8[FixedStack0](align=4)
1152B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1168B		MOV8mr <fi#3>, 1, %noreg, 0, %noreg, %vreg115; mem:ST1[%progress] GR8:%vreg115
1184B		%vreg112<def> = MOVZX32rm8 <fi#3>, 1, %noreg, 0, %noreg; mem:LD1[%progress] GR32:%vreg112
1200B		CMP32ri8 %vreg112, 0, %EFLAGS<imp-def>; GR32:%vreg112
1216B		%vreg110<def> = COPY %vreg108; GR32:%vreg110,%vreg108
1232B		%vreg110<def,tied1> = CMOVNE32rr %vreg110<tied0>, %vreg109, %EFLAGS<imp-use,kill>; GR32:%vreg110,%vreg109
1248B		MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %vreg110; mem:ST4[%retval] GR32:%vreg110
1264B		JMP_1 <BB#38>
	    Successors according to CFG: BB#38

1280B	BB#12: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#10
1296B		CMP32mi8 <fi#2>, 1, %noreg, 0, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%action.addr]
1312B		JNE_1 <BB#14>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#14 BB#13

1328B	BB#13: derived from LLVM BB %if.then.13
	    Predecessors according to CFG: BB#12
1344B		%vreg105<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg105
1360B		%vreg104<def> = MOV32rm %vreg105, 1, %noreg, 8, %noreg; mem:LD4[%avail_in] GR32:%vreg104 GR64:%vreg105
1376B		%vreg102<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg102
1392B		MOV32mr %vreg102, 1, %noreg, 16, %noreg, %vreg104; mem:ST4[%avail_in_expect] GR64:%vreg102 GR32:%vreg104
1408B		%vreg99<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg99
1424B		MOV32mi %vreg99, 1, %noreg, 8, %noreg, 3; mem:ST4[%mode14] GR64:%vreg99
1440B		JMP_1 <BB#7>
	    Successors according to CFG: BB#7

1456B	BB#14: derived from LLVM BB %if.else.15
	    Predecessors according to CFG: BB#12
1472B		CMP32mi8 <fi#2>, 1, %noreg, 0, %noreg, 2, %EFLAGS<imp-def>; mem:LD4[%action.addr]
1488B		JNE_1 <BB#16>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#16 BB#15

1504B	BB#15: derived from LLVM BB %if.then.18
	    Predecessors according to CFG: BB#14
1520B		%vreg97<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg97
1536B		%vreg96<def> = MOV32rm %vreg97, 1, %noreg, 8, %noreg; mem:LD4[%avail_in19] GR32:%vreg96 GR64:%vreg97
1552B		%vreg94<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg94
1568B		MOV32mr %vreg94, 1, %noreg, 16, %noreg, %vreg96; mem:ST4[%avail_in_expect20] GR64:%vreg94 GR32:%vreg96
1584B		%vreg91<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg91
1600B		MOV32mi %vreg91, 1, %noreg, 8, %noreg, 4; mem:ST4[%mode21] GR64:%vreg91
1616B		JMP_1 <BB#7>
	    Successors according to CFG: BB#7

1632B	BB#16: derived from LLVM BB %if.else.22
	    Predecessors according to CFG: BB#14
1648B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
1664B		JMP_1 <BB#38>
	    Successors according to CFG: BB#38

1680B	BB#17: derived from LLVM BB %sw.bb.23
	    Predecessors according to CFG: BB#8
1696B		CMP32mi8 <fi#2>, 1, %noreg, 0, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%action.addr]
1712B		JE_1 <BB#19>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#19 BB#18

1728B	BB#18: derived from LLVM BB %if.then.26
	    Predecessors according to CFG: BB#17
1744B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -1; mem:ST4[%retval]
1760B		JMP_1 <BB#38>
	    Successors according to CFG: BB#38

1776B	BB#19: derived from LLVM BB %if.end.27
	    Predecessors according to CFG: BB#17
1792B		%vreg66<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg66
1808B		%vreg65<def> = MOV32rm %vreg66, 1, %noreg, 16, %noreg; mem:LD4[%avail_in_expect28] GR32:%vreg65 GR64:%vreg66
1824B		%vreg63<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg63
1840B		%vreg62<def> = MOV64rm %vreg63, 1, %noreg, 0, %noreg; mem:LD8[%strm29] GR64:%vreg62,%vreg63
1856B		CMP32rm %vreg65, %vreg62, 1, %noreg, 8, %noreg, %EFLAGS<imp-def>; mem:LD4[%avail_in30] GR32:%vreg65 GR64:%vreg62
1872B		JE_1 <BB#21>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#21 BB#20

1888B	BB#20: derived from LLVM BB %if.then.33
	    Predecessors according to CFG: BB#19
1904B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -1; mem:ST4[%retval]
1920B		JMP_1 <BB#38>
	    Successors according to CFG: BB#38

1936B	BB#21: derived from LLVM BB %if.end.34
	    Predecessors according to CFG: BB#19
1952B		%vreg73<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg73
1968B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1984B		%RDI<def> = COPY %vreg73; GR64:%vreg73
2000B		CALL64pcrel32 <ga:@handle_compress>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %AL<imp-def>
2016B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2032B		%vreg72<def> = COPY %AL<kill>; GR8:%vreg72
2048B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2064B		STACKMAP 2, 0, 0, <fi#3>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack3](align=1) LD8[FixedStack0](align=4) LD8[FixedStack4]
2080B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2096B		MOV8mr <fi#3>, 1, %noreg, 0, %noreg, %vreg72; mem:ST1[%progress] GR8:%vreg72
2112B		%vreg69<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg69
2128B		CMP32mi8 %vreg69, 1, %noreg, 16, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_in_expect36] GR64:%vreg69
2144B		JA_1 <BB#24>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#24 BB#22

2160B	BB#22: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#21
2176B		%vreg77<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg77
2192B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2208B		%RDI<def> = COPY %vreg77; GR64:%vreg77
2224B		CALL64pcrel32 <ga:@isempty_RL>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %AL<imp-def>
2240B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2256B		%vreg76<def> = COPY %AL<kill>; GR8:%vreg76
2272B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2288B		STACKMAP 3, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack4]
2304B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2320B		CMP8ri %vreg76, 0, %EFLAGS<imp-def>; GR8:%vreg76
2336B		JE_1 <BB#24>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#24 BB#23

2352B	BB#23: derived from LLVM BB %lor.lhs.false.41
	    Predecessors according to CFG: BB#22
2368B		%vreg84<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg84
2384B		%vreg83<def> = MOV32rm %vreg84, 1, %noreg, 120, %noreg; mem:LD4[%state_out_pos] GR32:%vreg83 GR64:%vreg84
2400B		%vreg81<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg81
2416B		CMP32rm %vreg83, %vreg81, 1, %noreg, 116, %noreg, %EFLAGS<imp-def>; mem:LD4[%numZ] GR32:%vreg83 GR64:%vreg81
2432B		JGE_1 <BB#25>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#25 BB#24

2448B	BB#24: derived from LLVM BB %if.then.44
	    Predecessors according to CFG: BB#21 BB#22 BB#23
2464B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 2; mem:ST4[%retval]
2480B		JMP_1 <BB#38>
	    Successors according to CFG: BB#38

2496B	BB#25: derived from LLVM BB %if.end.45
	    Predecessors according to CFG: BB#23
2512B		%vreg86<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg86
2528B		MOV32mi %vreg86, 1, %noreg, 8, %noreg, 2; mem:ST4[%mode46] GR64:%vreg86
2544B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 1; mem:ST4[%retval]
2560B		JMP_1 <BB#38>
	    Successors according to CFG: BB#38

2576B	BB#26: derived from LLVM BB %sw.bb.47
	    Predecessors according to CFG: BB#8
2592B		CMP32mi8 <fi#2>, 1, %noreg, 0, %noreg, 2, %EFLAGS<imp-def>; mem:LD4[%action.addr]
2608B		JE_1 <BB#28>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#28 BB#27

2624B	BB#27: derived from LLVM BB %if.then.50
	    Predecessors according to CFG: BB#26
2640B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -1; mem:ST4[%retval]
2656B		JMP_1 <BB#38>
	    Successors according to CFG: BB#38

2672B	BB#28: derived from LLVM BB %if.end.51
	    Predecessors according to CFG: BB#26
2688B		%vreg35<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg35
2704B		%vreg34<def> = MOV32rm %vreg35, 1, %noreg, 16, %noreg; mem:LD4[%avail_in_expect52] GR32:%vreg34 GR64:%vreg35
2720B		%vreg32<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg32
2736B		%vreg31<def> = MOV64rm %vreg32, 1, %noreg, 0, %noreg; mem:LD8[%strm53] GR64:%vreg31,%vreg32
2752B		CMP32rm %vreg34, %vreg31, 1, %noreg, 8, %noreg, %EFLAGS<imp-def>; mem:LD4[%avail_in54] GR32:%vreg34 GR64:%vreg31
2768B		JE_1 <BB#30>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#30 BB#29

2784B	BB#29: derived from LLVM BB %if.then.57
	    Predecessors according to CFG: BB#28
2800B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -1; mem:ST4[%retval]
2816B		JMP_1 <BB#38>
	    Successors according to CFG: BB#38

2832B	BB#30: derived from LLVM BB %if.end.58
	    Predecessors according to CFG: BB#28
2848B		%vreg40<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg40
2864B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2880B		%RDI<def> = COPY %vreg40; GR64:%vreg40
2896B		CALL64pcrel32 <ga:@handle_compress>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %AL<imp-def>
2912B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2928B		%vreg39<def> = COPY %AL<kill>; GR8:%vreg39
2944B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2960B		STACKMAP 4, 0, 0, <fi#3>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack3](align=1) LD8[FixedStack0](align=4) LD8[FixedStack4]
2976B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2992B		MOV8mr <fi#3>, 1, %noreg, 0, %noreg, %vreg39; mem:ST1[%progress] GR8:%vreg39
3008B		CMP8mi <fi#3>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD1[%progress]
3024B		JNE_1 <BB#32>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#32 BB#31

3040B	BB#31: derived from LLVM BB %if.then.61
	    Predecessors according to CFG: BB#30
3056B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -1; mem:ST4[%retval]
3072B		JMP_1 <BB#38>
	    Successors according to CFG: BB#38

3088B	BB#32: derived from LLVM BB %if.end.62
	    Predecessors according to CFG: BB#30
3104B		%vreg43<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg43
3120B		CMP32mi8 %vreg43, 1, %noreg, 16, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_in_expect63] GR64:%vreg43
3136B		JA_1 <BB#35>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#35 BB#33

3152B	BB#33: derived from LLVM BB %lor.lhs.false.66
	    Predecessors according to CFG: BB#32
3168B		%vreg47<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg47
3184B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3200B		%RDI<def> = COPY %vreg47; GR64:%vreg47
3216B		CALL64pcrel32 <ga:@isempty_RL>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %AL<imp-def>
3232B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3248B		%vreg46<def> = COPY %AL<kill>; GR8:%vreg46
3264B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3280B		STACKMAP 5, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack4]
3296B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3312B		CMP8ri %vreg46, 0, %EFLAGS<imp-def>; GR8:%vreg46
3328B		JE_1 <BB#35>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#35 BB#34

3344B	BB#34: derived from LLVM BB %lor.lhs.false.69
	    Predecessors according to CFG: BB#33
3360B		%vreg54<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg54
3376B		%vreg53<def> = MOV32rm %vreg54, 1, %noreg, 120, %noreg; mem:LD4[%state_out_pos70] GR32:%vreg53 GR64:%vreg54
3392B		%vreg51<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg51
3408B		CMP32rm %vreg53, %vreg51, 1, %noreg, 116, %noreg, %EFLAGS<imp-def>; mem:LD4[%numZ71] GR32:%vreg53 GR64:%vreg51
3424B		JGE_1 <BB#36>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#36 BB#35

3440B	BB#35: derived from LLVM BB %if.then.74
	    Predecessors according to CFG: BB#32 BB#33 BB#34
3456B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 3; mem:ST4[%retval]
3472B		JMP_1 <BB#38>
	    Successors according to CFG: BB#38

3488B	BB#36: derived from LLVM BB %if.end.75
	    Predecessors according to CFG: BB#34
3504B		%vreg56<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg56
3520B		MOV32mi %vreg56, 1, %noreg, 8, %noreg, 1; mem:ST4[%mode76] GR64:%vreg56
3536B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 4; mem:ST4[%retval]
3552B		JMP_1 <BB#38>
	    Successors according to CFG: BB#38

3568B	BB#37: derived from LLVM BB %sw.epilog
	    Predecessors according to CFG: BB#7
3584B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
	    Successors according to CFG: BB#38

3600B	BB#38: derived from LLVM BB %return
	    Predecessors according to CFG: BB#31 BB#36 BB#35 BB#29 BB#27 BB#25 BB#24 BB#20 BB#18 BB#16 BB#11 BB#9 BB#37 BB#5 BB#3 BB#1
3616B		%vreg119<def> = MOV64ri <ga:@BZ2_bzCompress>; GR64:%vreg119
3632B		%vreg120<def> = COPY %vreg119; GR64:%vreg120,%vreg119
3648B		%vreg121<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg121
3664B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3680B		%RDI<def> = COPY %vreg120; GR64:%vreg120
3696B		%RSI<def> = COPY %vreg121; GR64:%vreg121
3712B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
3728B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3744B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3760B		STACKMAP 6, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
3776B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3792B		%vreg118<def> = MOV32rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD4[%retval] GR32:%vreg118
3808B		%EAX<def> = COPY %vreg118; GR32:%vreg118
3824B		RETQ %EAX<imp-use,kill>

# End machine code for function BZ2_bzCompress.

********** SIMPLE REGISTER COALESCING **********
********** Function: BZ2_bzCompress
********** JOINING INTERVALS ***********
preswitch:
768B	%vreg20<def> = SUBREG_TO_REG 0, %vreg23, 4; GR64_NOSP:%vreg20 GR32:%vreg23
	Considering merging to GR64_NOSP with %vreg23 in %vreg20:sub_32bit
		RHS = %vreg23 [736r,752r:0)[752r,784r:1)  0@736r 1@752r
		LHS = %vreg20 [768r,848r:0)  0@768r
		merge %vreg20:0@768r into %vreg23:1@752r --> @752r
		erased:	768r	%vreg20<def> = SUBREG_TO_REG 0, %vreg23, 4; GR64_NOSP:%vreg20 GR32:%vreg23
AllocationOrder(GR64_NOSP) = [ %RAX %RCX %RDX %RSI %RDI %R8 %R9 %R10 %R11 %RBX %R14 %R15 %R12 %R13 ]
		updated: 736B	%vreg20:sub_32bit<def,read-undef> = COPY %vreg22; GR64_NOSP:%vreg20 GR32:%vreg22
		updated: 752B	%vreg20:sub_32bit<def,tied1> = DEC32r %vreg20:sub_32bit<tied0>, %EFLAGS<imp-def,dead>; GR64_NOSP:%vreg20
		updated: 784B	%vreg24<def> = COPY %vreg20:sub_32bit; GR32:%vreg24 GR64_NOSP:%vreg20
	Success: %vreg23:sub_32bit -> %vreg20
	Result = %vreg20 [736r,752r:1)[752r,848r:0)  0@752r 1@736r
preswitch:
sw.bb.8:
if.else:
if.else.15:
if.then.13:
if.then.18:
736B	%vreg20:sub_32bit<def,read-undef> = COPY %vreg22; GR64_NOSP:%vreg20 GR32:%vreg22
	Considering merging to GR64_NOSP with %vreg22 in %vreg20:sub_32bit
		RHS = %vreg22 [720r,736r:0)  0@720r
		LHS = %vreg20 [736r,752r:1)[752r,848r:0)  0@752r 1@736r
		merge %vreg20:1@736r into %vreg22:0@720r --> @720r
		erased:	736r	%vreg20:sub_32bit<def,read-undef> = COPY %vreg22; GR64_NOSP:%vreg20 GR32:%vreg22
		updated: 720B	%vreg20:sub_32bit<def,read-undef> = MOV32rm %vreg21, 1, %noreg, 8, %noreg; mem:LD4[%mode] GR64_NOSP:%vreg20 GR64:%vreg21
	Success: %vreg22:sub_32bit -> %vreg20
	Result = %vreg20 [720r,752r:0)[752r,848r:1)  0@720r 1@752r
784B	%vreg24<def> = COPY %vreg20:sub_32bit; GR32:%vreg24 GR64_NOSP:%vreg20
	Considering merging to GR64_NOSP with %vreg24 in %vreg20:sub_32bit
		RHS = %vreg24 [784r,800r:0)[800r,800d:1)  0@784r 1@800r
		LHS = %vreg20 [720r,752r:0)[752r,848r:1)  0@720r 1@752r
		merge %vreg24:0@784r into %vreg20:1@752r --> @752r
		interference at %vreg24:1@800r
	Interference!
return:
3680B	%RDI<def> = COPY %vreg120; GR64:%vreg120
	Considering merging %vreg120 with %RDI
	Can only merge into reserved registers.
3696B	%RSI<def> = COPY %vreg121; GR64:%vreg121
	Considering merging %vreg121 with %RSI
	Can only merge into reserved registers.
3808B	%EAX<def> = COPY %vreg118; GR32:%vreg118
	Considering merging %vreg118 with %EAX
	Can only merge into reserved registers.
if.then.44:
if.then.74:
if.end:
if.end.3:
sw.bb.23:
if.end.27:
if.end.34:
1984B	%RDI<def> = COPY %vreg73; GR64:%vreg73
	Considering merging %vreg73 with %RDI
	Can only merge into reserved registers.
2032B	%vreg72<def> = COPY %AL<kill>; GR8:%vreg72
	Considering merging %vreg72 with %AL
	Can only merge into reserved registers.
lor.lhs.false:
2208B	%RDI<def> = COPY %vreg77; GR64:%vreg77
	Considering merging %vreg77 with %RDI
	Can only merge into reserved registers.
2256B	%vreg76<def> = COPY %AL<kill>; GR8:%vreg76
	Considering merging %vreg76 with %AL
	Can only merge into reserved registers.
lor.lhs.false.41:
sw.bb.47:
if.end.51:
if.end.58:
2880B	%RDI<def> = COPY %vreg40; GR64:%vreg40
	Considering merging %vreg40 with %RDI
	Can only merge into reserved registers.
2928B	%vreg39<def> = COPY %AL<kill>; GR8:%vreg39
	Considering merging %vreg39 with %AL
	Can only merge into reserved registers.
if.end.62:
lor.lhs.false.66:
3200B	%RDI<def> = COPY %vreg47; GR64:%vreg47
	Considering merging %vreg47 with %RDI
	Can only merge into reserved registers.
3248B	%vreg46<def> = COPY %AL<kill>; GR8:%vreg46
	Considering merging %vreg46 with %AL
	Can only merge into reserved registers.
lor.lhs.false.69:
entry:
16B	%vreg2<def> = COPY %ESI; GR32:%vreg2
	Considering merging %vreg2 with %ESI
	Can only merge into reserved registers.
32B	%vreg0<def> = COPY %RDI; GR64:%vreg0
	Considering merging %vreg0 with %RDI
	Can only merge into reserved registers.
144B	%RDI<def> = COPY %vreg6; GR64:%vreg6
	Considering merging %vreg6 with %RDI
	Can only merge into reserved registers.
160B	%RSI<def> = COPY %vreg7; GR64:%vreg7
	Considering merging %vreg7 with %RSI
	Can only merge into reserved registers.
if.then:
if.then.2:
if.then.6:
if.end.7:
sw.bb:
if.then.10:
1024B	%RDI<def> = COPY %vreg116; GR64:%vreg116
	Considering merging %vreg116 with %RDI
	Can only merge into reserved registers.
1072B	%vreg115<def> = COPY %AL<kill>; GR8:%vreg115
	Considering merging %vreg115 with %AL
	Can only merge into reserved registers.
if.else.22:
if.then.26:
if.then.33:
if.end.45:
if.then.50:
if.then.57:
if.then.61:
if.end.75:
sw.epilog:
3632B	%vreg120<def> = COPY %vreg119; GR64:%vreg120,%vreg119
	Considering merging to GR64 with %vreg119 in %vreg120
		RHS = %vreg119 [3616r,3632r:0)  0@3616r
		LHS = %vreg120 [3632r,3680r:0)  0@3632r
		merge %vreg120:0@3632r into %vreg119:0@3616r --> @3616r
		erased:	3632r	%vreg120<def> = COPY %vreg119; GR64:%vreg120,%vreg119
		updated: 3616B	%vreg120<def> = MOV64ri <ga:@BZ2_bzCompress>; GR64:%vreg120
	Success: %vreg119 -> %vreg120
	Result = %vreg120 [3616r,3680r:0)  0@3616r
416B	%vreg11<def> = COPY %vreg13; GR64:%vreg11,%vreg13
	Considering merging to GR64 with %vreg13 in %vreg11
		RHS = %vreg13 [400r,416r:0)  0@400r
		LHS = %vreg11 [416r,432r:0)  0@416r
		merge %vreg11:0@416r into %vreg13:0@400r --> @400r
		erased:	416r	%vreg11<def> = COPY %vreg13; GR64:%vreg11,%vreg13
		updated: 400B	%vreg11<def> = MOV64rm %vreg14, 1, %noreg, 48, %noreg; mem:LD8[%state] GR64:%vreg11,%vreg14
	Success: %vreg13 -> %vreg11
	Result = %vreg11 [400r,432r:0)  0@400r
48B	%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
	Considering merging to GR64 with %vreg0 in %vreg1
		RHS = %vreg0 [32r,48r:0)  0@32r
		LHS = %vreg1 [48r,256r:0)  0@48r
		merge %vreg1:0@48r into %vreg0:0@32r --> @32r
		erased:	48r	%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
		updated: 32B	%vreg1<def> = COPY %RDI; GR64:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [32r,256r:0)  0@32r
64B	%vreg3<def> = COPY %vreg2; GR32:%vreg3,%vreg2
	Considering merging to GR32 with %vreg2 in %vreg3
		RHS = %vreg2 [16r,64r:0)  0@16r
		LHS = %vreg3 [64r,272r:0)  0@64r
		merge %vreg3:0@64r into %vreg2:0@16r --> @16r
		erased:	64r	%vreg3<def> = COPY %vreg2; GR32:%vreg3,%vreg2
		updated: 16B	%vreg3<def> = COPY %ESI; GR32:%vreg3
	Success: %vreg2 -> %vreg3
	Result = %vreg3 [16r,272r:0)  0@16r
96B	%vreg6<def> = COPY %vreg5; GR64:%vreg6,%vreg5
	Considering merging to GR64 with %vreg5 in %vreg6
		RHS = %vreg5 [80r,96r:0)  0@80r
		LHS = %vreg6 [96r,144r:0)  0@96r
		merge %vreg6:0@96r into %vreg5:0@80r --> @80r
		erased:	96r	%vreg6<def> = COPY %vreg5; GR64:%vreg6,%vreg5
		updated: 80B	%vreg6<def> = MOV64ri <ga:@BZ2_bzCompress>; GR64:%vreg6
	Success: %vreg5 -> %vreg6
	Result = %vreg6 [80r,144r:0)  0@80r
1216B	%vreg110<def> = COPY %vreg108; GR32:%vreg110,%vreg108
	Considering merging to GR32 with %vreg108 in %vreg110
		RHS = %vreg108 [1088r,1216r:0)  0@1088r
		LHS = %vreg110 [1216r,1232r:0)[1232r,1248r:1)  0@1216r 1@1232r
		merge %vreg110:0@1216r into %vreg108:0@1088r --> @1088r
		erased:	1216r	%vreg110<def> = COPY %vreg108; GR32:%vreg110,%vreg108
		updated: 1088B	%vreg110<def> = MOV32ri 4294967294; GR32:%vreg110
	Success: %vreg108 -> %vreg110
	Result = %vreg110 [1088r,1232r:0)[1232r,1248r:1)  0@1088r 1@1232r
784B	%vreg24<def> = COPY %vreg20:sub_32bit; GR32:%vreg24 GR64_NOSP:%vreg20
	Considering merging to GR64_NOSP with %vreg24 in %vreg20:sub_32bit
		RHS = %vreg24 [784r,800r:0)[800r,800d:1)  0@784r 1@800r
		LHS = %vreg20 [720r,752r:0)[752r,848r:1)  0@720r 1@752r
		merge %vreg24:0@784r into %vreg20:1@752r --> @752r
		interference at %vreg24:1@800r
	Interference!
3680B	%RDI<def> = COPY %vreg120; GR64:%vreg120
	Considering merging %vreg120 with %RDI
	Can only merge into reserved registers.
144B	%RDI<def> = COPY %vreg6; GR64:%vreg6
	Considering merging %vreg6 with %RDI
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
DIL [0B,32r:0)[144r,176r:7)[1024r,1040r:2)[1984r,2000r:4)[2208r,2224r:3)[2880r,2896r:6)[3200r,3216r:5)[3680r,3712r:1)  0@0B-phi 1@3680r 2@1024r 3@2208r 4@1984r 5@3200r 6@2880r 7@144r
SIL [0B,16r:0)[160r,176r:2)[3696r,3712r:1)  0@0B-phi 1@3696r 2@160r
%vreg1 [32r,256r:0)  0@32r
%vreg3 [16r,272r:0)  0@16r
%vreg6 [80r,144r:0)  0@80r
%vreg7 [112r,160r:0)  0@112r
%vreg11 [400r,432r:0)  0@400r
%vreg14 [384r,400r:0)  0@384r
%vreg18 [560r,576r:0)  0@560r
%vreg19 [544r,560r:0)  0@544r
%vreg20 [720r,752r:0)[752r,848r:1)  0@720r 1@752r
%vreg21 [704r,720r:0)  0@704r
%vreg24 [784r,800r:0)[800r,800d:1)  0@784r 1@800r
%vreg25 [848r,864r:0)  0@848r
%vreg31 [2736r,2752r:0)  0@2736r
%vreg32 [2720r,2736r:0)  0@2720r
%vreg34 [2704r,2752r:0)  0@2704r
%vreg35 [2688r,2704r:0)  0@2688r
%vreg39 [2928r,2992r:0)  0@2928r
%vreg40 [2848r,2880r:0)  0@2848r
%vreg43 [3104r,3120r:0)  0@3104r
%vreg46 [3248r,3312r:0)  0@3248r
%vreg47 [3168r,3200r:0)  0@3168r
%vreg51 [3392r,3408r:0)  0@3392r
%vreg53 [3376r,3408r:0)  0@3376r
%vreg54 [3360r,3376r:0)  0@3360r
%vreg56 [3504r,3520r:0)  0@3504r
%vreg62 [1840r,1856r:0)  0@1840r
%vreg63 [1824r,1840r:0)  0@1824r
%vreg65 [1808r,1856r:0)  0@1808r
%vreg66 [1792r,1808r:0)  0@1792r
%vreg69 [2112r,2128r:0)  0@2112r
%vreg72 [2032r,2096r:0)  0@2032r
%vreg73 [1952r,1984r:0)  0@1952r
%vreg76 [2256r,2320r:0)  0@2256r
%vreg77 [2176r,2208r:0)  0@2176r
%vreg81 [2400r,2416r:0)  0@2400r
%vreg83 [2384r,2416r:0)  0@2384r
%vreg84 [2368r,2384r:0)  0@2368r
%vreg86 [2512r,2528r:0)  0@2512r
%vreg91 [1584r,1600r:0)  0@1584r
%vreg94 [1552r,1568r:0)  0@1552r
%vreg96 [1536r,1568r:0)  0@1536r
%vreg97 [1520r,1536r:0)  0@1520r
%vreg99 [1408r,1424r:0)  0@1408r
%vreg102 [1376r,1392r:0)  0@1376r
%vreg104 [1360r,1392r:0)  0@1360r
%vreg105 [1344r,1360r:0)  0@1344r
%vreg109 [1104r,1232r:0)  0@1104r
%vreg110 [1088r,1232r:0)[1232r,1248r:1)  0@1088r 1@1232r
%vreg112 [1184r,1200r:0)  0@1184r
%vreg115 [1072r,1168r:0)  0@1072r
%vreg116 [992r,1024r:0)  0@992r
%vreg118 [3792r,3808r:0)  0@3792r
%vreg120 [3616r,3680r:0)  0@3616r
%vreg121 [3648r,3696r:0)  0@3648r
RegMasks: 176r 1040r 2000r 2224r 2896r 3216r 3712r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzCompress: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=4, align=4, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=4, align=4, at location [SP+8]
  fi#3: size=1, align=1, at location [SP+8]
  fi#4: size=8, align=8, at location [SP+8]
Jump Tables:
  jt#0:  BB#9 BB#10 BB#17 BB#26
Function Live Ins: %RDI in %vreg0, %ESI in %vreg2

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI %ESI
16B		%vreg3<def> = COPY %ESI; GR32:%vreg3
32B		%vreg1<def> = COPY %RDI; GR64:%vreg1
80B		%vreg6<def> = MOV64ri <ga:@BZ2_bzCompress>; GR64:%vreg6
112B		%vreg7<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg7
128B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
144B		%RDI<def> = COPY %vreg6; GR64:%vreg6
160B		%RSI<def> = COPY %vreg7; GR64:%vreg7
176B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
192B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
208B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		STACKMAP 0, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#3>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, %vreg1, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack3](align=1) LD8[FixedStack0](align=4) LD8[FixedStack4] LD8[FixedStack1] GR32:%vreg3 GR64:%vreg1
240B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
256B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%strm.addr] GR64:%vreg1
272B		MOV32mr <fi#2>, 1, %noreg, 0, %noreg, %vreg3; mem:ST4[%action.addr] GR32:%vreg3
288B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%strm.addr]
304B		JNE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

320B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
336B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
352B		JMP_1 <BB#38>
	    Successors according to CFG: BB#38

368B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0
384B		%vreg14<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg14
400B		%vreg11<def> = MOV64rm %vreg14, 1, %noreg, 48, %noreg; mem:LD8[%state] GR64:%vreg11,%vreg14
432B		MOV64mr <fi#4>, 1, %noreg, 0, %noreg, %vreg11; mem:ST8[%s] GR64:%vreg11
448B		CMP64mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%s]
464B		JNE_1 <BB#4>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#4 BB#3

480B	BB#3: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#2
496B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
512B		JMP_1 <BB#38>
	    Successors according to CFG: BB#38

528B	BB#4: derived from LLVM BB %if.end.3
	    Predecessors according to CFG: BB#2
544B		%vreg19<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg19
560B		%vreg18<def> = MOV64rm %vreg19, 1, %noreg, 0, %noreg; mem:LD8[%strm4] GR64:%vreg18,%vreg19
576B		CMP64rm %vreg18, <fi#1>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD8[%strm.addr] GR64:%vreg18
592B		JE_1 <BB#6>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#6 BB#5

608B	BB#5: derived from LLVM BB %if.then.6
	    Predecessors according to CFG: BB#4
624B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
640B		JMP_1 <BB#38>
	    Successors according to CFG: BB#38

656B	BB#6: derived from LLVM BB %if.end.7
	    Predecessors according to CFG: BB#4
672B		JMP_1 <BB#7>
	    Successors according to CFG: BB#7

688B	BB#7: derived from LLVM BB %preswitch
	    Predecessors according to CFG: BB#6 BB#15 BB#13
704B		%vreg21<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg21
720B		%vreg20:sub_32bit<def,read-undef> = MOV32rm %vreg21, 1, %noreg, 8, %noreg; mem:LD4[%mode] GR64_NOSP:%vreg20 GR64:%vreg21
752B		%vreg20:sub_32bit<def,tied1> = DEC32r %vreg20:sub_32bit<tied0>, %EFLAGS<imp-def,dead>; GR64_NOSP:%vreg20
784B		%vreg24<def> = COPY %vreg20:sub_32bit; GR32:%vreg24 GR64_NOSP:%vreg20
800B		%vreg24<def,dead,tied1> = SUB32ri8 %vreg24<tied0>, 3, %EFLAGS<imp-def>; GR32:%vreg24
816B		JA_1 <BB#37>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#37 BB#8

832B	BB#8: derived from LLVM BB %preswitch
	    Predecessors according to CFG: BB#7
848B		%vreg25<def> = MOV64rm %noreg, 8, %vreg20, <jt#0>, %noreg; mem:LD8[JumpTable] GR64:%vreg25 GR64_NOSP:%vreg20
864B		JMP64r %vreg25; GR64:%vreg25
	    Successors according to CFG: BB#9 BB#10 BB#17 BB#26

880B	BB#9: derived from LLVM BB %sw.bb
	    Predecessors according to CFG: BB#8
896B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -1; mem:ST4[%retval]
912B		JMP_1 <BB#38>
	    Successors according to CFG: BB#38

928B	BB#10: derived from LLVM BB %sw.bb.8
	    Predecessors according to CFG: BB#8
944B		CMP32mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%action.addr]
960B		JNE_1 <BB#12>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#12 BB#11

976B	BB#11: derived from LLVM BB %if.then.10
	    Predecessors according to CFG: BB#10
992B		%vreg116<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg116
1008B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1024B		%RDI<def> = COPY %vreg116; GR64:%vreg116
1040B		CALL64pcrel32 <ga:@handle_compress>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %AL<imp-def>
1056B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1072B		%vreg115<def> = COPY %AL<kill>; GR8:%vreg115
1088B		%vreg110<def> = MOV32ri 4294967294; GR32:%vreg110
1104B		%vreg109<def> = MOV32ri 1; GR32:%vreg109
1120B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1136B		STACKMAP 1, 0, 0, <fi#3>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack3](align=1) LD8[FixedStack0](align=4)
1152B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1168B		MOV8mr <fi#3>, 1, %noreg, 0, %noreg, %vreg115; mem:ST1[%progress] GR8:%vreg115
1184B		%vreg112<def> = MOVZX32rm8 <fi#3>, 1, %noreg, 0, %noreg; mem:LD1[%progress] GR32:%vreg112
1200B		CMP32ri8 %vreg112, 0, %EFLAGS<imp-def>; GR32:%vreg112
1232B		%vreg110<def,tied1> = CMOVNE32rr %vreg110<tied0>, %vreg109, %EFLAGS<imp-use,kill>; GR32:%vreg110,%vreg109
1248B		MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %vreg110; mem:ST4[%retval] GR32:%vreg110
1264B		JMP_1 <BB#38>
	    Successors according to CFG: BB#38

1280B	BB#12: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#10
1296B		CMP32mi8 <fi#2>, 1, %noreg, 0, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%action.addr]
1312B		JNE_1 <BB#14>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#14 BB#13

1328B	BB#13: derived from LLVM BB %if.then.13
	    Predecessors according to CFG: BB#12
1344B		%vreg105<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg105
1360B		%vreg104<def> = MOV32rm %vreg105, 1, %noreg, 8, %noreg; mem:LD4[%avail_in] GR32:%vreg104 GR64:%vreg105
1376B		%vreg102<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg102
1392B		MOV32mr %vreg102, 1, %noreg, 16, %noreg, %vreg104; mem:ST4[%avail_in_expect] GR64:%vreg102 GR32:%vreg104
1408B		%vreg99<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg99
1424B		MOV32mi %vreg99, 1, %noreg, 8, %noreg, 3; mem:ST4[%mode14] GR64:%vreg99
1440B		JMP_1 <BB#7>
	    Successors according to CFG: BB#7

1456B	BB#14: derived from LLVM BB %if.else.15
	    Predecessors according to CFG: BB#12
1472B		CMP32mi8 <fi#2>, 1, %noreg, 0, %noreg, 2, %EFLAGS<imp-def>; mem:LD4[%action.addr]
1488B		JNE_1 <BB#16>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#16 BB#15

1504B	BB#15: derived from LLVM BB %if.then.18
	    Predecessors according to CFG: BB#14
1520B		%vreg97<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg97
1536B		%vreg96<def> = MOV32rm %vreg97, 1, %noreg, 8, %noreg; mem:LD4[%avail_in19] GR32:%vreg96 GR64:%vreg97
1552B		%vreg94<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg94
1568B		MOV32mr %vreg94, 1, %noreg, 16, %noreg, %vreg96; mem:ST4[%avail_in_expect20] GR64:%vreg94 GR32:%vreg96
1584B		%vreg91<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg91
1600B		MOV32mi %vreg91, 1, %noreg, 8, %noreg, 4; mem:ST4[%mode21] GR64:%vreg91
1616B		JMP_1 <BB#7>
	    Successors according to CFG: BB#7

1632B	BB#16: derived from LLVM BB %if.else.22
	    Predecessors according to CFG: BB#14
1648B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
1664B		JMP_1 <BB#38>
	    Successors according to CFG: BB#38

1680B	BB#17: derived from LLVM BB %sw.bb.23
	    Predecessors according to CFG: BB#8
1696B		CMP32mi8 <fi#2>, 1, %noreg, 0, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%action.addr]
1712B		JE_1 <BB#19>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#19 BB#18

1728B	BB#18: derived from LLVM BB %if.then.26
	    Predecessors according to CFG: BB#17
1744B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -1; mem:ST4[%retval]
1760B		JMP_1 <BB#38>
	    Successors according to CFG: BB#38

1776B	BB#19: derived from LLVM BB %if.end.27
	    Predecessors according to CFG: BB#17
1792B		%vreg66<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg66
1808B		%vreg65<def> = MOV32rm %vreg66, 1, %noreg, 16, %noreg; mem:LD4[%avail_in_expect28] GR32:%vreg65 GR64:%vreg66
1824B		%vreg63<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg63
1840B		%vreg62<def> = MOV64rm %vreg63, 1, %noreg, 0, %noreg; mem:LD8[%strm29] GR64:%vreg62,%vreg63
1856B		CMP32rm %vreg65, %vreg62, 1, %noreg, 8, %noreg, %EFLAGS<imp-def>; mem:LD4[%avail_in30] GR32:%vreg65 GR64:%vreg62
1872B		JE_1 <BB#21>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#21 BB#20

1888B	BB#20: derived from LLVM BB %if.then.33
	    Predecessors according to CFG: BB#19
1904B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -1; mem:ST4[%retval]
1920B		JMP_1 <BB#38>
	    Successors according to CFG: BB#38

1936B	BB#21: derived from LLVM BB %if.end.34
	    Predecessors according to CFG: BB#19
1952B		%vreg73<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg73
1968B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1984B		%RDI<def> = COPY %vreg73; GR64:%vreg73
2000B		CALL64pcrel32 <ga:@handle_compress>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %AL<imp-def>
2016B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2032B		%vreg72<def> = COPY %AL<kill>; GR8:%vreg72
2048B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2064B		STACKMAP 2, 0, 0, <fi#3>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack3](align=1) LD8[FixedStack0](align=4) LD8[FixedStack4]
2080B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2096B		MOV8mr <fi#3>, 1, %noreg, 0, %noreg, %vreg72; mem:ST1[%progress] GR8:%vreg72
2112B		%vreg69<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg69
2128B		CMP32mi8 %vreg69, 1, %noreg, 16, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_in_expect36] GR64:%vreg69
2144B		JA_1 <BB#24>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#24 BB#22

2160B	BB#22: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#21
2176B		%vreg77<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg77
2192B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2208B		%RDI<def> = COPY %vreg77; GR64:%vreg77
2224B		CALL64pcrel32 <ga:@isempty_RL>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %AL<imp-def>
2240B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2256B		%vreg76<def> = COPY %AL<kill>; GR8:%vreg76
2272B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2288B		STACKMAP 3, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack4]
2304B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2320B		CMP8ri %vreg76, 0, %EFLAGS<imp-def>; GR8:%vreg76
2336B		JE_1 <BB#24>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#24 BB#23

2352B	BB#23: derived from LLVM BB %lor.lhs.false.41
	    Predecessors according to CFG: BB#22
2368B		%vreg84<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg84
2384B		%vreg83<def> = MOV32rm %vreg84, 1, %noreg, 120, %noreg; mem:LD4[%state_out_pos] GR32:%vreg83 GR64:%vreg84
2400B		%vreg81<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg81
2416B		CMP32rm %vreg83, %vreg81, 1, %noreg, 116, %noreg, %EFLAGS<imp-def>; mem:LD4[%numZ] GR32:%vreg83 GR64:%vreg81
2432B		JGE_1 <BB#25>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#25 BB#24

2448B	BB#24: derived from LLVM BB %if.then.44
	    Predecessors according to CFG: BB#21 BB#22 BB#23
2464B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 2; mem:ST4[%retval]
2480B		JMP_1 <BB#38>
	    Successors according to CFG: BB#38

2496B	BB#25: derived from LLVM BB %if.end.45
	    Predecessors according to CFG: BB#23
2512B		%vreg86<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg86
2528B		MOV32mi %vreg86, 1, %noreg, 8, %noreg, 2; mem:ST4[%mode46] GR64:%vreg86
2544B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 1; mem:ST4[%retval]
2560B		JMP_1 <BB#38>
	    Successors according to CFG: BB#38

2576B	BB#26: derived from LLVM BB %sw.bb.47
	    Predecessors according to CFG: BB#8
2592B		CMP32mi8 <fi#2>, 1, %noreg, 0, %noreg, 2, %EFLAGS<imp-def>; mem:LD4[%action.addr]
2608B		JE_1 <BB#28>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#28 BB#27

2624B	BB#27: derived from LLVM BB %if.then.50
	    Predecessors according to CFG: BB#26
2640B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -1; mem:ST4[%retval]
2656B		JMP_1 <BB#38>
	    Successors according to CFG: BB#38

2672B	BB#28: derived from LLVM BB %if.end.51
	    Predecessors according to CFG: BB#26
2688B		%vreg35<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg35
2704B		%vreg34<def> = MOV32rm %vreg35, 1, %noreg, 16, %noreg; mem:LD4[%avail_in_expect52] GR32:%vreg34 GR64:%vreg35
2720B		%vreg32<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg32
2736B		%vreg31<def> = MOV64rm %vreg32, 1, %noreg, 0, %noreg; mem:LD8[%strm53] GR64:%vreg31,%vreg32
2752B		CMP32rm %vreg34, %vreg31, 1, %noreg, 8, %noreg, %EFLAGS<imp-def>; mem:LD4[%avail_in54] GR32:%vreg34 GR64:%vreg31
2768B		JE_1 <BB#30>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#30 BB#29

2784B	BB#29: derived from LLVM BB %if.then.57
	    Predecessors according to CFG: BB#28
2800B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -1; mem:ST4[%retval]
2816B		JMP_1 <BB#38>
	    Successors according to CFG: BB#38

2832B	BB#30: derived from LLVM BB %if.end.58
	    Predecessors according to CFG: BB#28
2848B		%vreg40<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg40
2864B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2880B		%RDI<def> = COPY %vreg40; GR64:%vreg40
2896B		CALL64pcrel32 <ga:@handle_compress>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %AL<imp-def>
2912B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2928B		%vreg39<def> = COPY %AL<kill>; GR8:%vreg39
2944B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2960B		STACKMAP 4, 0, 0, <fi#3>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack3](align=1) LD8[FixedStack0](align=4) LD8[FixedStack4]
2976B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2992B		MOV8mr <fi#3>, 1, %noreg, 0, %noreg, %vreg39; mem:ST1[%progress] GR8:%vreg39
3008B		CMP8mi <fi#3>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD1[%progress]
3024B		JNE_1 <BB#32>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#32 BB#31

3040B	BB#31: derived from LLVM BB %if.then.61
	    Predecessors according to CFG: BB#30
3056B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -1; mem:ST4[%retval]
3072B		JMP_1 <BB#38>
	    Successors according to CFG: BB#38

3088B	BB#32: derived from LLVM BB %if.end.62
	    Predecessors according to CFG: BB#30
3104B		%vreg43<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg43
3120B		CMP32mi8 %vreg43, 1, %noreg, 16, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_in_expect63] GR64:%vreg43
3136B		JA_1 <BB#35>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#35 BB#33

3152B	BB#33: derived from LLVM BB %lor.lhs.false.66
	    Predecessors according to CFG: BB#32
3168B		%vreg47<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg47
3184B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3200B		%RDI<def> = COPY %vreg47; GR64:%vreg47
3216B		CALL64pcrel32 <ga:@isempty_RL>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %AL<imp-def>
3232B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3248B		%vreg46<def> = COPY %AL<kill>; GR8:%vreg46
3264B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3280B		STACKMAP 5, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack4]
3296B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3312B		CMP8ri %vreg46, 0, %EFLAGS<imp-def>; GR8:%vreg46
3328B		JE_1 <BB#35>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#35 BB#34

3344B	BB#34: derived from LLVM BB %lor.lhs.false.69
	    Predecessors according to CFG: BB#33
3360B		%vreg54<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg54
3376B		%vreg53<def> = MOV32rm %vreg54, 1, %noreg, 120, %noreg; mem:LD4[%state_out_pos70] GR32:%vreg53 GR64:%vreg54
3392B		%vreg51<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg51
3408B		CMP32rm %vreg53, %vreg51, 1, %noreg, 116, %noreg, %EFLAGS<imp-def>; mem:LD4[%numZ71] GR32:%vreg53 GR64:%vreg51
3424B		JGE_1 <BB#36>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#36 BB#35

3440B	BB#35: derived from LLVM BB %if.then.74
	    Predecessors according to CFG: BB#32 BB#33 BB#34
3456B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 3; mem:ST4[%retval]
3472B		JMP_1 <BB#38>
	    Successors according to CFG: BB#38

3488B	BB#36: derived from LLVM BB %if.end.75
	    Predecessors according to CFG: BB#34
3504B		%vreg56<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg56
3520B		MOV32mi %vreg56, 1, %noreg, 8, %noreg, 1; mem:ST4[%mode76] GR64:%vreg56
3536B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 4; mem:ST4[%retval]
3552B		JMP_1 <BB#38>
	    Successors according to CFG: BB#38

3568B	BB#37: derived from LLVM BB %sw.epilog
	    Predecessors according to CFG: BB#7
3584B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
	    Successors according to CFG: BB#38

3600B	BB#38: derived from LLVM BB %return
	    Predecessors according to CFG: BB#31 BB#36 BB#35 BB#29 BB#27 BB#25 BB#24 BB#20 BB#18 BB#16 BB#11 BB#9 BB#37 BB#5 BB#3 BB#1
3616B		%vreg120<def> = MOV64ri <ga:@BZ2_bzCompress>; GR64:%vreg120
3648B		%vreg121<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg121
3664B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3680B		%RDI<def> = COPY %vreg120; GR64:%vreg120
3696B		%RSI<def> = COPY %vreg121; GR64:%vreg121
3712B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
3728B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3744B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3760B		STACKMAP 6, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
3776B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3792B		%vreg118<def> = MOV32rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD4[%retval] GR32:%vreg118
3808B		%EAX<def> = COPY %vreg118; GR32:%vreg118
3824B		RETQ %EAX<imp-use,kill>

# End machine code for function BZ2_bzCompress.

********** GREEDY REGISTER ALLOCATION **********
********** Function: BZ2_bzCompress
********** INTERVALS **********
DIL [0B,32r:0)[144r,176r:7)[1024r,1040r:2)[1984r,2000r:4)[2208r,2224r:3)[2880r,2896r:6)[3200r,3216r:5)[3680r,3712r:1)  0@0B-phi 1@3680r 2@1024r 3@2208r 4@1984r 5@3200r 6@2880r 7@144r
SIL [0B,16r:0)[160r,176r:2)[3696r,3712r:1)  0@0B-phi 1@3696r 2@160r
%vreg1 [32r,256r:0)  0@32r
%vreg3 [16r,272r:0)  0@16r
%vreg6 [80r,144r:0)  0@80r
%vreg7 [112r,160r:0)  0@112r
%vreg11 [400r,432r:0)  0@400r
%vreg14 [384r,400r:0)  0@384r
%vreg18 [560r,576r:0)  0@560r
%vreg19 [544r,560r:0)  0@544r
%vreg20 [720r,752r:0)[752r,848r:1)  0@720r 1@752r
%vreg21 [704r,720r:0)  0@704r
%vreg24 [784r,800r:0)[800r,800d:1)  0@784r 1@800r
%vreg25 [848r,864r:0)  0@848r
%vreg31 [2736r,2752r:0)  0@2736r
%vreg32 [2720r,2736r:0)  0@2720r
%vreg34 [2704r,2752r:0)  0@2704r
%vreg35 [2688r,2704r:0)  0@2688r
%vreg39 [2928r,2992r:0)  0@2928r
%vreg40 [2848r,2880r:0)  0@2848r
%vreg43 [3104r,3120r:0)  0@3104r
%vreg46 [3248r,3312r:0)  0@3248r
%vreg47 [3168r,3200r:0)  0@3168r
%vreg51 [3392r,3408r:0)  0@3392r
%vreg53 [3376r,3408r:0)  0@3376r
%vreg54 [3360r,3376r:0)  0@3360r
%vreg56 [3504r,3520r:0)  0@3504r
%vreg62 [1840r,1856r:0)  0@1840r
%vreg63 [1824r,1840r:0)  0@1824r
%vreg65 [1808r,1856r:0)  0@1808r
%vreg66 [1792r,1808r:0)  0@1792r
%vreg69 [2112r,2128r:0)  0@2112r
%vreg72 [2032r,2096r:0)  0@2032r
%vreg73 [1952r,1984r:0)  0@1952r
%vreg76 [2256r,2320r:0)  0@2256r
%vreg77 [2176r,2208r:0)  0@2176r
%vreg81 [2400r,2416r:0)  0@2400r
%vreg83 [2384r,2416r:0)  0@2384r
%vreg84 [2368r,2384r:0)  0@2368r
%vreg86 [2512r,2528r:0)  0@2512r
%vreg91 [1584r,1600r:0)  0@1584r
%vreg94 [1552r,1568r:0)  0@1552r
%vreg96 [1536r,1568r:0)  0@1536r
%vreg97 [1520r,1536r:0)  0@1520r
%vreg99 [1408r,1424r:0)  0@1408r
%vreg102 [1376r,1392r:0)  0@1376r
%vreg104 [1360r,1392r:0)  0@1360r
%vreg105 [1344r,1360r:0)  0@1344r
%vreg109 [1104r,1232r:0)  0@1104r
%vreg110 [1088r,1232r:0)[1232r,1248r:1)  0@1088r 1@1232r
%vreg112 [1184r,1200r:0)  0@1184r
%vreg115 [1072r,1168r:0)  0@1072r
%vreg116 [992r,1024r:0)  0@992r
%vreg118 [3792r,3808r:0)  0@3792r
%vreg120 [3616r,3680r:0)  0@3616r
%vreg121 [3648r,3696r:0)  0@3648r
RegMasks: 176r 1040r 2000r 2224r 2896r 3216r 3712r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzCompress: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=4, align=4, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=4, align=4, at location [SP+8]
  fi#3: size=1, align=1, at location [SP+8]
  fi#4: size=8, align=8, at location [SP+8]
Jump Tables:
  jt#0:  BB#9 BB#10 BB#17 BB#26
Function Live Ins: %RDI in %vreg0, %ESI in %vreg2

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI %ESI
16B		%vreg3<def> = COPY %ESI; GR32:%vreg3
32B		%vreg1<def> = COPY %RDI; GR64:%vreg1
80B		%vreg6<def> = MOV64ri <ga:@BZ2_bzCompress>; GR64:%vreg6
112B		%vreg7<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg7
128B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
144B		%RDI<def> = COPY %vreg6; GR64:%vreg6
160B		%RSI<def> = COPY %vreg7; GR64:%vreg7
176B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
192B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
208B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		STACKMAP 0, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#3>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, %vreg1, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack3](align=1) LD8[FixedStack0](align=4) LD8[FixedStack4] LD8[FixedStack1] GR32:%vreg3 GR64:%vreg1
240B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
256B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%strm.addr] GR64:%vreg1
272B		MOV32mr <fi#2>, 1, %noreg, 0, %noreg, %vreg3; mem:ST4[%action.addr] GR32:%vreg3
288B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%strm.addr]
304B		JNE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

320B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
336B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
352B		JMP_1 <BB#38>
	    Successors according to CFG: BB#38

368B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0
384B		%vreg14<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg14
400B		%vreg11<def> = MOV64rm %vreg14, 1, %noreg, 48, %noreg; mem:LD8[%state] GR64:%vreg11,%vreg14
432B		MOV64mr <fi#4>, 1, %noreg, 0, %noreg, %vreg11; mem:ST8[%s] GR64:%vreg11
448B		CMP64mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%s]
464B		JNE_1 <BB#4>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#4 BB#3

480B	BB#3: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#2
496B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
512B		JMP_1 <BB#38>
	    Successors according to CFG: BB#38

528B	BB#4: derived from LLVM BB %if.end.3
	    Predecessors according to CFG: BB#2
544B		%vreg19<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg19
560B		%vreg18<def> = MOV64rm %vreg19, 1, %noreg, 0, %noreg; mem:LD8[%strm4] GR64:%vreg18,%vreg19
576B		CMP64rm %vreg18, <fi#1>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD8[%strm.addr] GR64:%vreg18
592B		JE_1 <BB#6>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#6 BB#5

608B	BB#5: derived from LLVM BB %if.then.6
	    Predecessors according to CFG: BB#4
624B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
640B		JMP_1 <BB#38>
	    Successors according to CFG: BB#38

656B	BB#6: derived from LLVM BB %if.end.7
	    Predecessors according to CFG: BB#4
672B		JMP_1 <BB#7>
	    Successors according to CFG: BB#7

688B	BB#7: derived from LLVM BB %preswitch
	    Predecessors according to CFG: BB#6 BB#15 BB#13
704B		%vreg21<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg21
720B		%vreg20:sub_32bit<def,read-undef> = MOV32rm %vreg21, 1, %noreg, 8, %noreg; mem:LD4[%mode] GR64_NOSP:%vreg20 GR64:%vreg21
752B		%vreg20:sub_32bit<def,tied1> = DEC32r %vreg20:sub_32bit<tied0>, %EFLAGS<imp-def,dead>; GR64_NOSP:%vreg20
784B		%vreg24<def> = COPY %vreg20:sub_32bit; GR32:%vreg24 GR64_NOSP:%vreg20
800B		%vreg24<def,dead,tied1> = SUB32ri8 %vreg24<tied0>, 3, %EFLAGS<imp-def>; GR32:%vreg24
816B		JA_1 <BB#37>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#37 BB#8

832B	BB#8: derived from LLVM BB %preswitch
	    Predecessors according to CFG: BB#7
848B		%vreg25<def> = MOV64rm %noreg, 8, %vreg20, <jt#0>, %noreg; mem:LD8[JumpTable] GR64:%vreg25 GR64_NOSP:%vreg20
864B		JMP64r %vreg25; GR64:%vreg25
	    Successors according to CFG: BB#9 BB#10 BB#17 BB#26

880B	BB#9: derived from LLVM BB %sw.bb
	    Predecessors according to CFG: BB#8
896B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -1; mem:ST4[%retval]
912B		JMP_1 <BB#38>
	    Successors according to CFG: BB#38

928B	BB#10: derived from LLVM BB %sw.bb.8
	    Predecessors according to CFG: BB#8
944B		CMP32mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%action.addr]
960B		JNE_1 <BB#12>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#12 BB#11

976B	BB#11: derived from LLVM BB %if.then.10
	    Predecessors according to CFG: BB#10
992B		%vreg116<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg116
1008B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1024B		%RDI<def> = COPY %vreg116; GR64:%vreg116
1040B		CALL64pcrel32 <ga:@handle_compress>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %AL<imp-def>
1056B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1072B		%vreg115<def> = COPY %AL<kill>; GR8:%vreg115
1088B		%vreg110<def> = MOV32ri 4294967294; GR32:%vreg110
1104B		%vreg109<def> = MOV32ri 1; GR32:%vreg109
1120B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1136B		STACKMAP 1, 0, 0, <fi#3>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack3](align=1) LD8[FixedStack0](align=4)
1152B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1168B		MOV8mr <fi#3>, 1, %noreg, 0, %noreg, %vreg115; mem:ST1[%progress] GR8:%vreg115
1184B		%vreg112<def> = MOVZX32rm8 <fi#3>, 1, %noreg, 0, %noreg; mem:LD1[%progress] GR32:%vreg112
1200B		CMP32ri8 %vreg112, 0, %EFLAGS<imp-def>; GR32:%vreg112
1232B		%vreg110<def,tied1> = CMOVNE32rr %vreg110<tied0>, %vreg109, %EFLAGS<imp-use,kill>; GR32:%vreg110,%vreg109
1248B		MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %vreg110; mem:ST4[%retval] GR32:%vreg110
1264B		JMP_1 <BB#38>
	    Successors according to CFG: BB#38

1280B	BB#12: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#10
1296B		CMP32mi8 <fi#2>, 1, %noreg, 0, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%action.addr]
1312B		JNE_1 <BB#14>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#14 BB#13

1328B	BB#13: derived from LLVM BB %if.then.13
	    Predecessors according to CFG: BB#12
1344B		%vreg105<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg105
1360B		%vreg104<def> = MOV32rm %vreg105, 1, %noreg, 8, %noreg; mem:LD4[%avail_in] GR32:%vreg104 GR64:%vreg105
1376B		%vreg102<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg102
1392B		MOV32mr %vreg102, 1, %noreg, 16, %noreg, %vreg104; mem:ST4[%avail_in_expect] GR64:%vreg102 GR32:%vreg104
1408B		%vreg99<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg99
1424B		MOV32mi %vreg99, 1, %noreg, 8, %noreg, 3; mem:ST4[%mode14] GR64:%vreg99
1440B		JMP_1 <BB#7>
	    Successors according to CFG: BB#7

1456B	BB#14: derived from LLVM BB %if.else.15
	    Predecessors according to CFG: BB#12
1472B		CMP32mi8 <fi#2>, 1, %noreg, 0, %noreg, 2, %EFLAGS<imp-def>; mem:LD4[%action.addr]
1488B		JNE_1 <BB#16>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#16 BB#15

1504B	BB#15: derived from LLVM BB %if.then.18
	    Predecessors according to CFG: BB#14
1520B		%vreg97<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg97
1536B		%vreg96<def> = MOV32rm %vreg97, 1, %noreg, 8, %noreg; mem:LD4[%avail_in19] GR32:%vreg96 GR64:%vreg97
1552B		%vreg94<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg94
1568B		MOV32mr %vreg94, 1, %noreg, 16, %noreg, %vreg96; mem:ST4[%avail_in_expect20] GR64:%vreg94 GR32:%vreg96
1584B		%vreg91<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg91
1600B		MOV32mi %vreg91, 1, %noreg, 8, %noreg, 4; mem:ST4[%mode21] GR64:%vreg91
1616B		JMP_1 <BB#7>
	    Successors according to CFG: BB#7

1632B	BB#16: derived from LLVM BB %if.else.22
	    Predecessors according to CFG: BB#14
1648B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
1664B		JMP_1 <BB#38>
	    Successors according to CFG: BB#38

1680B	BB#17: derived from LLVM BB %sw.bb.23
	    Predecessors according to CFG: BB#8
1696B		CMP32mi8 <fi#2>, 1, %noreg, 0, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%action.addr]
1712B		JE_1 <BB#19>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#19 BB#18

1728B	BB#18: derived from LLVM BB %if.then.26
	    Predecessors according to CFG: BB#17
1744B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -1; mem:ST4[%retval]
1760B		JMP_1 <BB#38>
	    Successors according to CFG: BB#38

1776B	BB#19: derived from LLVM BB %if.end.27
	    Predecessors according to CFG: BB#17
1792B		%vreg66<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg66
1808B		%vreg65<def> = MOV32rm %vreg66, 1, %noreg, 16, %noreg; mem:LD4[%avail_in_expect28] GR32:%vreg65 GR64:%vreg66
1824B		%vreg63<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg63
1840B		%vreg62<def> = MOV64rm %vreg63, 1, %noreg, 0, %noreg; mem:LD8[%strm29] GR64:%vreg62,%vreg63
1856B		CMP32rm %vreg65, %vreg62, 1, %noreg, 8, %noreg, %EFLAGS<imp-def>; mem:LD4[%avail_in30] GR32:%vreg65 GR64:%vreg62
1872B		JE_1 <BB#21>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#21 BB#20

1888B	BB#20: derived from LLVM BB %if.then.33
	    Predecessors according to CFG: BB#19
1904B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -1; mem:ST4[%retval]
1920B		JMP_1 <BB#38>
	    Successors according to CFG: BB#38

1936B	BB#21: derived from LLVM BB %if.end.34
	    Predecessors according to CFG: BB#19
1952B		%vreg73<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg73
1968B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1984B		%RDI<def> = COPY %vreg73; GR64:%vreg73
2000B		CALL64pcrel32 <ga:@handle_compress>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %AL<imp-def>
2016B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2032B		%vreg72<def> = COPY %AL<kill>; GR8:%vreg72
2048B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2064B		STACKMAP 2, 0, 0, <fi#3>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack3](align=1) LD8[FixedStack0](align=4) LD8[FixedStack4]
2080B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2096B		MOV8mr <fi#3>, 1, %noreg, 0, %noreg, %vreg72; mem:ST1[%progress] GR8:%vreg72
2112B		%vreg69<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg69
2128B		CMP32mi8 %vreg69, 1, %noreg, 16, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_in_expect36] GR64:%vreg69
2144B		JA_1 <BB#24>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#24 BB#22

2160B	BB#22: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#21
2176B		%vreg77<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg77
2192B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2208B		%RDI<def> = COPY %vreg77; GR64:%vreg77
2224B		CALL64pcrel32 <ga:@isempty_RL>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %AL<imp-def>
2240B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2256B		%vreg76<def> = COPY %AL<kill>; GR8:%vreg76
2272B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2288B		STACKMAP 3, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack4]
2304B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2320B		CMP8ri %vreg76, 0, %EFLAGS<imp-def>; GR8:%vreg76
2336B		JE_1 <BB#24>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#24 BB#23

2352B	BB#23: derived from LLVM BB %lor.lhs.false.41
	    Predecessors according to CFG: BB#22
2368B		%vreg84<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg84
2384B		%vreg83<def> = MOV32rm %vreg84, 1, %noreg, 120, %noreg; mem:LD4[%state_out_pos] GR32:%vreg83 GR64:%vreg84
2400B		%vreg81<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg81
2416B		CMP32rm %vreg83, %vreg81, 1, %noreg, 116, %noreg, %EFLAGS<imp-def>; mem:LD4[%numZ] GR32:%vreg83 GR64:%vreg81
2432B		JGE_1 <BB#25>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#25 BB#24

2448B	BB#24: derived from LLVM BB %if.then.44
	    Predecessors according to CFG: BB#21 BB#22 BB#23
2464B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 2; mem:ST4[%retval]
2480B		JMP_1 <BB#38>
	    Successors according to CFG: BB#38

2496B	BB#25: derived from LLVM BB %if.end.45
	    Predecessors according to CFG: BB#23
2512B		%vreg86<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg86
2528B		MOV32mi %vreg86, 1, %noreg, 8, %noreg, 2; mem:ST4[%mode46] GR64:%vreg86
2544B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 1; mem:ST4[%retval]
2560B		JMP_1 <BB#38>
	    Successors according to CFG: BB#38

2576B	BB#26: derived from LLVM BB %sw.bb.47
	    Predecessors according to CFG: BB#8
2592B		CMP32mi8 <fi#2>, 1, %noreg, 0, %noreg, 2, %EFLAGS<imp-def>; mem:LD4[%action.addr]
2608B		JE_1 <BB#28>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#28 BB#27

2624B	BB#27: derived from LLVM BB %if.then.50
	    Predecessors according to CFG: BB#26
2640B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -1; mem:ST4[%retval]
2656B		JMP_1 <BB#38>
	    Successors according to CFG: BB#38

2672B	BB#28: derived from LLVM BB %if.end.51
	    Predecessors according to CFG: BB#26
2688B		%vreg35<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg35
2704B		%vreg34<def> = MOV32rm %vreg35, 1, %noreg, 16, %noreg; mem:LD4[%avail_in_expect52] GR32:%vreg34 GR64:%vreg35
2720B		%vreg32<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg32
2736B		%vreg31<def> = MOV64rm %vreg32, 1, %noreg, 0, %noreg; mem:LD8[%strm53] GR64:%vreg31,%vreg32
2752B		CMP32rm %vreg34, %vreg31, 1, %noreg, 8, %noreg, %EFLAGS<imp-def>; mem:LD4[%avail_in54] GR32:%vreg34 GR64:%vreg31
2768B		JE_1 <BB#30>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#30 BB#29

2784B	BB#29: derived from LLVM BB %if.then.57
	    Predecessors according to CFG: BB#28
2800B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -1; mem:ST4[%retval]
2816B		JMP_1 <BB#38>
	    Successors according to CFG: BB#38

2832B	BB#30: derived from LLVM BB %if.end.58
	    Predecessors according to CFG: BB#28
2848B		%vreg40<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg40
2864B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2880B		%RDI<def> = COPY %vreg40; GR64:%vreg40
2896B		CALL64pcrel32 <ga:@handle_compress>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %AL<imp-def>
2912B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2928B		%vreg39<def> = COPY %AL<kill>; GR8:%vreg39
2944B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2960B		STACKMAP 4, 0, 0, <fi#3>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack3](align=1) LD8[FixedStack0](align=4) LD8[FixedStack4]
2976B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2992B		MOV8mr <fi#3>, 1, %noreg, 0, %noreg, %vreg39; mem:ST1[%progress] GR8:%vreg39
3008B		CMP8mi <fi#3>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD1[%progress]
3024B		JNE_1 <BB#32>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#32 BB#31

3040B	BB#31: derived from LLVM BB %if.then.61
	    Predecessors according to CFG: BB#30
3056B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -1; mem:ST4[%retval]
3072B		JMP_1 <BB#38>
	    Successors according to CFG: BB#38

3088B	BB#32: derived from LLVM BB %if.end.62
	    Predecessors according to CFG: BB#30
3104B		%vreg43<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg43
3120B		CMP32mi8 %vreg43, 1, %noreg, 16, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_in_expect63] GR64:%vreg43
3136B		JA_1 <BB#35>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#35 BB#33

3152B	BB#33: derived from LLVM BB %lor.lhs.false.66
	    Predecessors according to CFG: BB#32
3168B		%vreg47<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg47
3184B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3200B		%RDI<def> = COPY %vreg47; GR64:%vreg47
3216B		CALL64pcrel32 <ga:@isempty_RL>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %AL<imp-def>
3232B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3248B		%vreg46<def> = COPY %AL<kill>; GR8:%vreg46
3264B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3280B		STACKMAP 5, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack4]
3296B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3312B		CMP8ri %vreg46, 0, %EFLAGS<imp-def>; GR8:%vreg46
3328B		JE_1 <BB#35>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#35 BB#34

3344B	BB#34: derived from LLVM BB %lor.lhs.false.69
	    Predecessors according to CFG: BB#33
3360B		%vreg54<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg54
3376B		%vreg53<def> = MOV32rm %vreg54, 1, %noreg, 120, %noreg; mem:LD4[%state_out_pos70] GR32:%vreg53 GR64:%vreg54
3392B		%vreg51<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg51
3408B		CMP32rm %vreg53, %vreg51, 1, %noreg, 116, %noreg, %EFLAGS<imp-def>; mem:LD4[%numZ71] GR32:%vreg53 GR64:%vreg51
3424B		JGE_1 <BB#36>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#36 BB#35

3440B	BB#35: derived from LLVM BB %if.then.74
	    Predecessors according to CFG: BB#32 BB#33 BB#34
3456B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 3; mem:ST4[%retval]
3472B		JMP_1 <BB#38>
	    Successors according to CFG: BB#38

3488B	BB#36: derived from LLVM BB %if.end.75
	    Predecessors according to CFG: BB#34
3504B		%vreg56<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg56
3520B		MOV32mi %vreg56, 1, %noreg, 8, %noreg, 1; mem:ST4[%mode76] GR64:%vreg56
3536B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 4; mem:ST4[%retval]
3552B		JMP_1 <BB#38>
	    Successors according to CFG: BB#38

3568B	BB#37: derived from LLVM BB %sw.epilog
	    Predecessors according to CFG: BB#7
3584B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
	    Successors according to CFG: BB#38

3600B	BB#38: derived from LLVM BB %return
	    Predecessors according to CFG: BB#31 BB#36 BB#35 BB#29 BB#27 BB#25 BB#24 BB#20 BB#18 BB#16 BB#11 BB#9 BB#37 BB#5 BB#3 BB#1
3616B		%vreg120<def> = MOV64ri <ga:@BZ2_bzCompress>; GR64:%vreg120
3648B		%vreg121<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg121
3664B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3680B		%RDI<def> = COPY %vreg120; GR64:%vreg120
3696B		%RSI<def> = COPY %vreg121; GR64:%vreg121
3712B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
3728B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3744B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3760B		STACKMAP 6, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
3776B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3792B		%vreg118<def> = MOV32rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD4[%retval] GR32:%vreg118
3808B		%EAX<def> = COPY %vreg118; GR32:%vreg118
3824B		RETQ %EAX<imp-use,kill>

# End machine code for function BZ2_bzCompress.


selectOrSplit GR32:%vreg3 [16r,272r:0)  0@16r w=4.618902e-03
hints: %ESI
missed hint %ESI
assigning %vreg3 to %EBX: BH [16r,272r:0)  0@16r BL [16r,272r:0)  0@16r

selectOrSplit GR64:%vreg1 [32r,256r:0)  0@32r w=4.855769e-03
hints: %RDI
missed hint %RDI
%R14 is available at cost 1
Only trying the first 10 regs.
should evict: %vreg3 [16r,272r:0)  0@16r w= 4.618902e-03
hints: %ESI
can reassign: %vreg3 [16r,272r:0)  0@16r from %RBX to %ESI
should evict: %vreg3 [16r,272r:0)  0@16r w= 4.618902e-03
hints: %ESI
can reassign: %vreg3 [16r,272r:0)  0@16r from %RBX to %ESI
evicting %RBX interference: Cascade 1
unassigning %vreg3 from %EBX: BH BL
assigning %vreg1 to %RBX: BH [32r,256r:0)  0@32r BL [32r,256r:0)  0@32r
queuing new interval: %vreg3 [16r,272r:0)  0@16r

selectOrSplit GR32:%vreg3 [16r,272r:0)  0@16r w=4.618902e-03
hints: %ESI
missed hint %ESI
%R14D is available at cost 1
Only trying the first 10 regs.
assigning %vreg3 to %R14D: R14B [16r,272r:0)  0@16r

selectOrSplit GR64:%vreg6 [80r,144r:0)  0@80r w=2.176724e-03
hints: %RDI
assigning %vreg6 to %RDI: DIL [80r,144r:0)  0@80r

selectOrSplit GR64:%vreg7 [112r,160r:0)  0@112r w=4.508928e-03
hints: %RSI
assigning %vreg7 to %RSI: SIL [112r,160r:0)  0@112r

selectOrSplit GR64:%vreg116 [992r,1024r:0)  0@992r w=3.817877e-05
hints: %RDI
assigning %vreg116 to %RDI: DIL [992r,1024r:0)  0@992r

selectOrSplit GR8:%vreg115 [1072r,1168r:0)  0@1072r w=3.325248e-05
AllocationOrder(GR8) = [ %AL %CL %DL %SIL %DIL %R8B %R9B %R10B %R11B %BL %R14B %R15B %R12B %R13B ]
hints: %AL
assigning %vreg115 to %AL: AL [1072r,1168r:0)  0@1072r

selectOrSplit GR64:%vreg73 [1952r,1984r:0)  0@1952r w=1.901452e-05
hints: %RDI
assigning %vreg73 to %RDI: DIL [1952r,1984r:0)  0@1952r

selectOrSplit GR8:%vreg72 [2032r,2096r:0)  0@2032r w=1.770318e-05
hints: %AL
assigning %vreg72 to %AL: AL [2032r,2096r:0)  0@2032r

selectOrSplit GR64:%vreg77 [2176r,2208r:0)  0@2176r w=9.432400e-06
hints: %RDI
assigning %vreg77 to %RDI: DIL [2176r,2208r:0)  0@2176r

selectOrSplit GR8:%vreg76 [2256r,2320r:0)  0@2256r w=8.781890e-06
hints: %AL
assigning %vreg76 to %AL: AL [2256r,2320r:0)  0@2256r

selectOrSplit GR64:%vreg40 [2848r,2880r:0)  0@2848r w=1.901452e-05
hints: %RDI
assigning %vreg40 to %RDI: DIL [2848r,2880r:0)  0@2848r

selectOrSplit GR8:%vreg39 [2928r,2992r:0)  0@2928r w=1.770318e-05
hints: %AL
assigning %vreg39 to %AL: AL [2928r,2992r:0)  0@2928r

selectOrSplit GR64:%vreg47 [3168r,3200r:0)  0@3168r w=4.791061e-06
hints: %RDI
assigning %vreg47 to %RDI: DIL [3168r,3200r:0)  0@3168r

selectOrSplit GR8:%vreg46 [3248r,3312r:0)  0@3248r w=4.460643e-06
hints: %AL
assigning %vreg46 to %AL: AL [3248r,3312r:0)  0@3248r

selectOrSplit GR64:%vreg120 [3616r,3680r:0)  0@3616r w=2.176724e-03
hints: %RDI
assigning %vreg120 to %RDI: DIL [3616r,3680r:0)  0@3616r

selectOrSplit GR64:%vreg121 [3648r,3696r:0)  0@3648r w=4.508928e-03
hints: %RSI
assigning %vreg121 to %RSI: SIL [3648r,3696r:0)  0@3648r

selectOrSplit GR32:%vreg118 [3792r,3808r:0)  0@3792r w=inf
hints: %EAX
assigning %vreg118 to %EAX: AH [3792r,3808r:0)  0@3792r AL [3792r,3808r:0)  0@3792r

selectOrSplit GR64_NOSP:%vreg20 [720r,752r:0)[752r,848r:1)  0@720r 1@752r w=2.607464e-03
assigning %vreg20 to %RAX: AH [720r,752r:0)[752r,848r:1)  0@720r 1@752r AL [720r,752r:0)[752r,848r:1)  0@720r 1@752r

selectOrSplit GR64:%vreg14 [384r,400r:0)  0@384r w=inf
assigning %vreg14 to %RAX: AH [384r,400r:0)  0@384r AL [384r,400r:0)  0@384r

selectOrSplit GR64:%vreg11 [400r,432r:0)  0@400r w=inf
assigning %vreg11 to %RAX: AH [400r,432r:0)  0@400r AL [400r,432r:0)  0@400r

selectOrSplit GR64:%vreg19 [544r,560r:0)  0@544r w=inf
assigning %vreg19 to %RAX: AH [544r,560r:0)  0@544r AL [544r,560r:0)  0@544r

selectOrSplit GR64:%vreg18 [560r,576r:0)  0@560r w=inf
assigning %vreg18 to %RAX: AH [560r,576r:0)  0@560r AL [560r,576r:0)  0@560r

selectOrSplit GR64:%vreg21 [704r,720r:0)  0@704r w=inf
assigning %vreg21 to %RAX: AH [704r,720r:0)  0@704r AL [704r,720r:0)  0@704r

selectOrSplit GR32:%vreg24 [784r,800r:0)[800r,800d:1)  0@784r 1@800r w=inf
assigning %vreg24 to %ECX: CH [784r,800r:0)[800r,800d:1)  0@784r 1@800r CL [784r,800r:0)[800r,800d:1)  0@784r 1@800r

selectOrSplit GR64:%vreg25 [848r,864r:0)  0@848r w=inf
assigning %vreg25 to %RAX: AH [848r,864r:0)  0@848r AL [848r,864r:0)  0@848r

selectOrSplit GR32:%vreg110 [1088r,1232r:0)[1232r,1248r:1)  0@1088r 1@1232r w=5.832117e-05
assigning %vreg110 to %ECX: CH [1088r,1232r:0)[1232r,1248r:1)  0@1088r 1@1232r CL [1088r,1232r:0)[1232r,1248r:1)  0@1088r 1@1232r

selectOrSplit GR32:%vreg109 [1104r,1232r:0)  0@1104r w=1.546395e-05
assigning %vreg109 to %EDX: DH [1104r,1232r:0)  0@1104r DL [1104r,1232r:0)  0@1104r

selectOrSplit GR32:%vreg112 [1184r,1200r:0)  0@1184r w=inf
assigning %vreg112 to %EAX: AH [1184r,1200r:0)  0@1184r AL [1184r,1200r:0)  0@1184r

selectOrSplit GR64:%vreg105 [1344r,1360r:0)  0@1344r w=inf
assigning %vreg105 to %RAX: AH [1344r,1360r:0)  0@1344r AL [1344r,1360r:0)  0@1344r

selectOrSplit GR32:%vreg104 [1360r,1392r:0)  0@1360r w=1.882626e-05
assigning %vreg104 to %EAX: AH [1360r,1392r:0)  0@1360r AL [1360r,1392r:0)  0@1360r

selectOrSplit GR64:%vreg102 [1376r,1392r:0)  0@1376r w=inf
assigning %vreg102 to %RCX: CH [1376r,1392r:0)  0@1376r CL [1376r,1392r:0)  0@1376r

selectOrSplit GR64:%vreg99 [1408r,1424r:0)  0@1408r w=inf
assigning %vreg99 to %RAX: AH [1408r,1424r:0)  0@1408r AL [1408r,1424r:0)  0@1408r

selectOrSplit GR64:%vreg97 [1520r,1536r:0)  0@1520r w=inf
assigning %vreg97 to %RAX: AH [1520r,1536r:0)  0@1520r AL [1520r,1536r:0)  0@1520r

selectOrSplit GR32:%vreg96 [1536r,1568r:0)  0@1536r w=9.339011e-06
assigning %vreg96 to %EAX: AH [1536r,1568r:0)  0@1536r AL [1536r,1568r:0)  0@1536r

selectOrSplit GR64:%vreg94 [1552r,1568r:0)  0@1552r w=inf
assigning %vreg94 to %RCX: CH [1552r,1568r:0)  0@1552r CL [1552r,1568r:0)  0@1552r

selectOrSplit GR64:%vreg91 [1584r,1600r:0)  0@1584r w=inf
assigning %vreg91 to %RAX: AH [1584r,1600r:0)  0@1584r AL [1584r,1600r:0)  0@1584r

selectOrSplit GR64:%vreg66 [1792r,1808r:0)  0@1792r w=inf
assigning %vreg66 to %RAX: AH [1792r,1808r:0)  0@1792r AL [1792r,1808r:0)  0@1792r

selectOrSplit GR32:%vreg65 [1808r,1856r:0)  0@1808r w=3.645073e-05
assigning %vreg65 to %EAX: AH [1808r,1856r:0)  0@1808r AL [1808r,1856r:0)  0@1808r

selectOrSplit GR64:%vreg63 [1824r,1840r:0)  0@1824r w=inf
assigning %vreg63 to %RCX: CH [1824r,1840r:0)  0@1824r CL [1824r,1840r:0)  0@1824r

selectOrSplit GR64:%vreg62 [1840r,1856r:0)  0@1840r w=inf
assigning %vreg62 to %RCX: CH [1840r,1856r:0)  0@1840r CL [1840r,1856r:0)  0@1840r

selectOrSplit GR64:%vreg69 [2112r,2128r:0)  0@2112r w=inf
assigning %vreg69 to %RAX: AH [2112r,2128r:0)  0@2112r AL [2112r,2128r:0)  0@2112r

selectOrSplit GR64:%vreg84 [2368r,2384r:0)  0@2368r w=inf
assigning %vreg84 to %RAX: AH [2368r,2384r:0)  0@2368r AL [2368r,2384r:0)  0@2368r

selectOrSplit GR32:%vreg83 [2384r,2416r:0)  0@2384r w=4.743625e-06
assigning %vreg83 to %EAX: AH [2384r,2416r:0)  0@2384r AL [2384r,2416r:0)  0@2384r

selectOrSplit GR64:%vreg81 [2400r,2416r:0)  0@2400r w=inf
assigning %vreg81 to %RCX: CH [2400r,2416r:0)  0@2400r CL [2400r,2416r:0)  0@2400r

selectOrSplit GR64:%vreg86 [2512r,2528r:0)  0@2512r w=inf
assigning %vreg86 to %RAX: AH [2512r,2528r:0)  0@2512r AL [2512r,2528r:0)  0@2512r

selectOrSplit GR64:%vreg35 [2688r,2704r:0)  0@2688r w=inf
assigning %vreg35 to %RAX: AH [2688r,2704r:0)  0@2688r AL [2688r,2704r:0)  0@2688r

selectOrSplit GR32:%vreg34 [2704r,2752r:0)  0@2704r w=3.645073e-05
assigning %vreg34 to %EAX: AH [2704r,2752r:0)  0@2704r AL [2704r,2752r:0)  0@2704r

selectOrSplit GR64:%vreg32 [2720r,2736r:0)  0@2720r w=inf
assigning %vreg32 to %RCX: CH [2720r,2736r:0)  0@2720r CL [2720r,2736r:0)  0@2720r

selectOrSplit GR64:%vreg31 [2736r,2752r:0)  0@2736r w=inf
assigning %vreg31 to %RCX: CH [2736r,2752r:0)  0@2736r CL [2736r,2752r:0)  0@2736r

selectOrSplit GR64:%vreg43 [3104r,3120r:0)  0@3104r w=inf
assigning %vreg43 to %RAX: AH [3104r,3120r:0)  0@3104r AL [3104r,3120r:0)  0@3104r

selectOrSplit GR64:%vreg54 [3360r,3376r:0)  0@3360r w=inf
assigning %vreg54 to %RAX: AH [3360r,3376r:0)  0@3360r AL [3360r,3376r:0)  0@3360r

selectOrSplit GR32:%vreg53 [3376r,3408r:0)  0@3376r w=2.371812e-06
assigning %vreg53 to %EAX: AH [3376r,3408r:0)  0@3376r AL [3376r,3408r:0)  0@3376r

selectOrSplit GR64:%vreg51 [3392r,3408r:0)  0@3392r w=inf
assigning %vreg51 to %RCX: CH [3392r,3408r:0)  0@3392r CL [3392r,3408r:0)  0@3392r

selectOrSplit GR64:%vreg56 [3504r,3520r:0)  0@3504r w=inf
assigning %vreg56 to %RAX: AH [3504r,3520r:0)  0@3504r AL [3504r,3520r:0)  0@3504r

********** STACK TRANSFORMATION METADATA **********
********** Function: BZ2_bzCompress
********** REGISTER MAP **********
[%vreg1 -> %RBX] GR64
[%vreg3 -> %R14D] GR32
[%vreg6 -> %RDI] GR64
[%vreg7 -> %RSI] GR64
[%vreg11 -> %RAX] GR64
[%vreg14 -> %RAX] GR64
[%vreg18 -> %RAX] GR64
[%vreg19 -> %RAX] GR64
[%vreg20 -> %RAX] GR64_NOSP
[%vreg21 -> %RAX] GR64
[%vreg24 -> %ECX] GR32
[%vreg25 -> %RAX] GR64
[%vreg31 -> %RCX] GR64
[%vreg32 -> %RCX] GR64
[%vreg34 -> %EAX] GR32
[%vreg35 -> %RAX] GR64
[%vreg39 -> %AL] GR8
[%vreg40 -> %RDI] GR64
[%vreg43 -> %RAX] GR64
[%vreg46 -> %AL] GR8
[%vreg47 -> %RDI] GR64
[%vreg51 -> %RCX] GR64
[%vreg53 -> %EAX] GR32
[%vreg54 -> %RAX] GR64
[%vreg56 -> %RAX] GR64
[%vreg62 -> %RCX] GR64
[%vreg63 -> %RCX] GR64
[%vreg65 -> %EAX] GR32
[%vreg66 -> %RAX] GR64
[%vreg69 -> %RAX] GR64
[%vreg72 -> %AL] GR8
[%vreg73 -> %RDI] GR64
[%vreg76 -> %AL] GR8
[%vreg77 -> %RDI] GR64
[%vreg81 -> %RCX] GR64
[%vreg83 -> %EAX] GR32
[%vreg84 -> %RAX] GR64
[%vreg86 -> %RAX] GR64
[%vreg91 -> %RAX] GR64
[%vreg94 -> %RCX] GR64
[%vreg96 -> %EAX] GR32
[%vreg97 -> %RAX] GR64
[%vreg99 -> %RAX] GR64
[%vreg102 -> %RCX] GR64
[%vreg104 -> %EAX] GR32
[%vreg105 -> %RAX] GR64
[%vreg109 -> %EDX] GR32
[%vreg110 -> %ECX] GR32
[%vreg112 -> %EAX] GR32
[%vreg115 -> %AL] GR8
[%vreg116 -> %RDI] GR64
[%vreg118 -> %EAX] GR32
[%vreg120 -> %RDI] GR64
[%vreg121 -> %RSI] GR64


Stackmap 0:
  STACKMAP 0, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#3>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, %vreg1, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack3](align=1) LD8[FixedStack0](align=4) LD8[FixedStack4] LD8[FixedStack1] GR32:%vreg3 GR64:%vreg1

i32 %action: in register %R14D (vreg 3)
i32* %action.addr: in stack slot 2 (size: 4)
i8* %progress: in stack slot 3 (size: 1)
i32* %retval: in stack slot 0 (size: 4)
%struct.EState** %s: in stack slot 4 (size: 8)
%struct.bz_stream* %strm: in register %RBX (vreg 1)
%struct.bz_stream** %strm.addr: in stack slot 1 (size: 8)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, 0, <fi#3>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack3](align=1) LD8[FixedStack0](align=4)

i8* %progress: in stack slot 3 (size: 1)
i32* %retval: in stack slot 0 (size: 4)

Duplicate operand locations:


Stackmap 2:
  STACKMAP 2, 0, 0, <fi#3>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack3](align=1) LD8[FixedStack0](align=4) LD8[FixedStack4]

i8* %progress: in stack slot 3 (size: 1)
i32* %retval: in stack slot 0 (size: 4)
%struct.EState** %s: in stack slot 4 (size: 8)

Duplicate operand locations:


Stackmap 3:
  STACKMAP 3, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack4]

i32* %retval: in stack slot 0 (size: 4)
%struct.EState** %s: in stack slot 4 (size: 8)

Duplicate operand locations:


Stackmap 4:
  STACKMAP 4, 0, 0, <fi#3>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack3](align=1) LD8[FixedStack0](align=4) LD8[FixedStack4]

i8* %progress: in stack slot 3 (size: 1)
i32* %retval: in stack slot 0 (size: 4)
%struct.EState** %s: in stack slot 4 (size: 8)

Duplicate operand locations:


Stackmap 5:
  STACKMAP 5, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack4]

i32* %retval: in stack slot 0 (size: 4)
%struct.EState** %s: in stack slot 4 (size: 8)

Duplicate operand locations:


Stackmap 6:
  STACKMAP 6, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)

i32* %retval: in stack slot 0 (size: 4)

Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#3>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, %vreg1, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack3](align=1) LD8[FixedStack0](align=4) LD8[FixedStack4] LD8[FixedStack1] GR32:%vreg3 GR64:%vreg1
  -> Call instruction SlotIndex 176B, searching vregs 0 -> 122 and stack slots -1 -> 5

  STACKMAP 1, 0, 0, <fi#3>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack3](align=1) LD8[FixedStack0](align=4)
  -> Call instruction SlotIndex 1040B, searching vregs 0 -> 122 and stack slots -1 -> 5

  STACKMAP 2, 0, 0, <fi#3>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack3](align=1) LD8[FixedStack0](align=4) LD8[FixedStack4]
  -> Call instruction SlotIndex 2000B, searching vregs 0 -> 122 and stack slots -1 -> 5

  STACKMAP 3, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack4]
  -> Call instruction SlotIndex 2224B, searching vregs 0 -> 122 and stack slots -1 -> 5

  STACKMAP 4, 0, 0, <fi#3>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack3](align=1) LD8[FixedStack0](align=4) LD8[FixedStack4]
  -> Call instruction SlotIndex 2896B, searching vregs 0 -> 122 and stack slots -1 -> 5

  STACKMAP 5, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack4]
  -> Call instruction SlotIndex 3216B, searching vregs 0 -> 122 and stack slots -1 -> 5

  STACKMAP 6, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
  -> Call instruction SlotIndex 3712B, searching vregs 0 -> 122 and stack slots -1 -> 5

********** REWRITE VIRTUAL REGISTERS **********
********** Function: BZ2_bzCompress
********** REGISTER MAP **********
[%vreg1 -> %RBX] GR64
[%vreg3 -> %R14D] GR32
[%vreg6 -> %RDI] GR64
[%vreg7 -> %RSI] GR64
[%vreg11 -> %RAX] GR64
[%vreg14 -> %RAX] GR64
[%vreg18 -> %RAX] GR64
[%vreg19 -> %RAX] GR64
[%vreg20 -> %RAX] GR64_NOSP
[%vreg21 -> %RAX] GR64
[%vreg24 -> %ECX] GR32
[%vreg25 -> %RAX] GR64
[%vreg31 -> %RCX] GR64
[%vreg32 -> %RCX] GR64
[%vreg34 -> %EAX] GR32
[%vreg35 -> %RAX] GR64
[%vreg39 -> %AL] GR8
[%vreg40 -> %RDI] GR64
[%vreg43 -> %RAX] GR64
[%vreg46 -> %AL] GR8
[%vreg47 -> %RDI] GR64
[%vreg51 -> %RCX] GR64
[%vreg53 -> %EAX] GR32
[%vreg54 -> %RAX] GR64
[%vreg56 -> %RAX] GR64
[%vreg62 -> %RCX] GR64
[%vreg63 -> %RCX] GR64
[%vreg65 -> %EAX] GR32
[%vreg66 -> %RAX] GR64
[%vreg69 -> %RAX] GR64
[%vreg72 -> %AL] GR8
[%vreg73 -> %RDI] GR64
[%vreg76 -> %AL] GR8
[%vreg77 -> %RDI] GR64
[%vreg81 -> %RCX] GR64
[%vreg83 -> %EAX] GR32
[%vreg84 -> %RAX] GR64
[%vreg86 -> %RAX] GR64
[%vreg91 -> %RAX] GR64
[%vreg94 -> %RCX] GR64
[%vreg96 -> %EAX] GR32
[%vreg97 -> %RAX] GR64
[%vreg99 -> %RAX] GR64
[%vreg102 -> %RCX] GR64
[%vreg104 -> %EAX] GR32
[%vreg105 -> %RAX] GR64
[%vreg109 -> %EDX] GR32
[%vreg110 -> %ECX] GR32
[%vreg112 -> %EAX] GR32
[%vreg115 -> %AL] GR8
[%vreg116 -> %RDI] GR64
[%vreg118 -> %EAX] GR32
[%vreg120 -> %RDI] GR64
[%vreg121 -> %RSI] GR64

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %ESI %RDI
16B		%vreg3<def> = COPY %ESI; GR32:%vreg3
32B		%vreg1<def> = COPY %RDI; GR64:%vreg1
80B		%vreg6<def> = MOV64ri <ga:@BZ2_bzCompress>; GR64:%vreg6
112B		%vreg7<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg7
128B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
144B		%RDI<def> = COPY %vreg6<kill>; GR64:%vreg6
160B		%RSI<def> = COPY %vreg7<kill>; GR64:%vreg7
176B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
192B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
208B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		STACKMAP 0, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#3>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, %vreg1, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack3](align=1) LD8[FixedStack0](align=4) LD8[FixedStack4] LD8[FixedStack1] GR32:%vreg3 GR64:%vreg1
240B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
256B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg1<kill>; mem:ST8[%strm.addr] GR64:%vreg1
272B		MOV32mr <fi#2>, 1, %noreg, 0, %noreg, %vreg3<kill>; mem:ST4[%action.addr] GR32:%vreg3
288B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%strm.addr]
304B		JNE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1
> %R14D<def> = COPY %ESI
> %RBX<def> = COPY %RDI
> %RDI<def> = MOV64ri <ga:@BZ2_bzCompress>
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 0, 0, %R14D, 0, <fi#2>, 0, 0, <fi#3>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, %RBX, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack3](align=1) LD8[FixedStack0](align=4) LD8[FixedStack4] LD8[FixedStack1]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %RBX<kill>; mem:ST8[%strm.addr]
> MOV32mr <fi#2>, 1, %noreg, 0, %noreg, %R14D<kill>; mem:ST4[%action.addr]
> CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%strm.addr]
> JNE_1 <BB#2>, %EFLAGS<imp-use,kill>
320B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
336B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
352B		JMP_1 <BB#38>
	    Successors according to CFG: BB#38
> MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
> JMP_1 <BB#38>
368B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0
384B		%vreg14<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg14
400B		%vreg11<def> = MOV64rm %vreg14<kill>, 1, %noreg, 48, %noreg; mem:LD8[%state] GR64:%vreg11,%vreg14
432B		MOV64mr <fi#4>, 1, %noreg, 0, %noreg, %vreg11<kill>; mem:ST8[%s] GR64:%vreg11
448B		CMP64mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%s]
464B		JNE_1 <BB#4>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#4 BB#3
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 48, %noreg; mem:LD8[%state]
> MOV64mr <fi#4>, 1, %noreg, 0, %noreg, %RAX<kill>; mem:ST8[%s]
> CMP64mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%s]
> JNE_1 <BB#4>, %EFLAGS<imp-use,kill>
480B	BB#3: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#2
496B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
512B		JMP_1 <BB#38>
	    Successors according to CFG: BB#38
> MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
> JMP_1 <BB#38>
528B	BB#4: derived from LLVM BB %if.end.3
	    Predecessors according to CFG: BB#2
544B		%vreg19<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg19
560B		%vreg18<def> = MOV64rm %vreg19<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm4] GR64:%vreg18,%vreg19
576B		CMP64rm %vreg18<kill>, <fi#1>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD8[%strm.addr] GR64:%vreg18
592B		JE_1 <BB#6>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#6 BB#5
> %RAX<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm4]
> CMP64rm %RAX<kill>, <fi#1>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD8[%strm.addr]
> JE_1 <BB#6>, %EFLAGS<imp-use,kill>
608B	BB#5: derived from LLVM BB %if.then.6
	    Predecessors according to CFG: BB#4
624B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
640B		JMP_1 <BB#38>
	    Successors according to CFG: BB#38
> MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
> JMP_1 <BB#38>
656B	BB#6: derived from LLVM BB %if.end.7
	    Predecessors according to CFG: BB#4
672B		JMP_1 <BB#7>
	    Successors according to CFG: BB#7
> JMP_1 <BB#7>
688B	BB#7: derived from LLVM BB %preswitch
	    Predecessors according to CFG: BB#6 BB#15 BB#13
704B		%vreg21<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg21
720B		%vreg20:sub_32bit<def,read-undef> = MOV32rm %vreg21<kill>, 1, %noreg, 8, %noreg; mem:LD4[%mode] GR64_NOSP:%vreg20 GR64:%vreg21
752B		%vreg20:sub_32bit<def,tied1> = DEC32r %vreg20:sub_32bit<kill,tied0>, %EFLAGS<imp-def,dead>; GR64_NOSP:%vreg20
784B		%vreg24<def> = COPY %vreg20:sub_32bit; GR32:%vreg24 GR64_NOSP:%vreg20
800B		%vreg24<def,dead,tied1> = SUB32ri8 %vreg24<kill,tied0>, 3, %EFLAGS<imp-def>; GR32:%vreg24
816B		JA_1 <BB#37>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#37 BB#8
> %RAX<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 8, %noreg, %RAX<imp-def>; mem:LD4[%mode]
> %EAX<def,tied1> = DEC32r %EAX<tied0>, %EFLAGS<imp-def,dead>, %RAX<imp-use,kill>, %RAX<imp-def>
> %ECX<def> = COPY %EAX
> %ECX<def,dead,tied1> = SUB32ri8 %ECX<kill,tied0>, 3, %EFLAGS<imp-def>
> JA_1 <BB#37>, %EFLAGS<imp-use,kill>
832B	BB#8: derived from LLVM BB %preswitch
	    Live Ins: %RAX
	    Predecessors according to CFG: BB#7
848B		%vreg25<def> = MOV64rm %noreg, 8, %vreg20<kill>, <jt#0>, %noreg; mem:LD8[JumpTable] GR64:%vreg25 GR64_NOSP:%vreg20
864B		JMP64r %vreg25<kill>; GR64:%vreg25
	    Successors according to CFG: BB#9 BB#10 BB#17 BB#26
> %RAX<def> = MOV64rm %noreg, 8, %RAX<kill>, <jt#0>, %noreg; mem:LD8[JumpTable]
> JMP64r %RAX<kill>
880B	BB#9: derived from LLVM BB %sw.bb
	    Predecessors according to CFG: BB#8
896B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -1; mem:ST4[%retval]
912B		JMP_1 <BB#38>
	    Successors according to CFG: BB#38
> MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -1; mem:ST4[%retval]
> JMP_1 <BB#38>
928B	BB#10: derived from LLVM BB %sw.bb.8
	    Predecessors according to CFG: BB#8
944B		CMP32mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%action.addr]
960B		JNE_1 <BB#12>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#12 BB#11
> CMP32mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%action.addr]
> JNE_1 <BB#12>, %EFLAGS<imp-use,kill>
976B	BB#11: derived from LLVM BB %if.then.10
	    Predecessors according to CFG: BB#10
992B		%vreg116<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg116
1008B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1024B		%RDI<def> = COPY %vreg116<kill>; GR64:%vreg116
1040B		CALL64pcrel32 <ga:@handle_compress>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %AL<imp-def>
1056B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1072B		%vreg115<def> = COPY %AL; GR8:%vreg115
1088B		%vreg110<def> = MOV32ri 4294967294; GR32:%vreg110
1104B		%vreg109<def> = MOV32ri 1; GR32:%vreg109
1120B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1136B		STACKMAP 1, 0, 0, <fi#3>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack3](align=1) LD8[FixedStack0](align=4)
1152B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1168B		MOV8mr <fi#3>, 1, %noreg, 0, %noreg, %vreg115<kill>; mem:ST1[%progress] GR8:%vreg115
1184B		%vreg112<def> = MOVZX32rm8 <fi#3>, 1, %noreg, 0, %noreg; mem:LD1[%progress] GR32:%vreg112
1200B		CMP32ri8 %vreg112<kill>, 0, %EFLAGS<imp-def>; GR32:%vreg112
1232B		%vreg110<def,tied1> = CMOVNE32rr %vreg110<kill,tied0>, %vreg109<kill>, %EFLAGS<imp-use,kill>; GR32:%vreg110,%vreg109
1248B		MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %vreg110<kill>; mem:ST4[%retval] GR32:%vreg110
1264B		JMP_1 <BB#38>
	    Successors according to CFG: BB#38
> %RDI<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@handle_compress>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %AL<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %AL<def> = COPY %AL
Deleting identity copy.
> %ECX<def> = MOV32ri 4294967294
> %EDX<def> = MOV32ri 1
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 1, 0, 0, <fi#3>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack3](align=1) LD8[FixedStack0](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV8mr <fi#3>, 1, %noreg, 0, %noreg, %AL<kill>; mem:ST1[%progress]
> %EAX<def> = MOVZX32rm8 <fi#3>, 1, %noreg, 0, %noreg; mem:LD1[%progress]
> CMP32ri8 %EAX<kill>, 0, %EFLAGS<imp-def>
> %ECX<def,tied1> = CMOVNE32rr %ECX<kill,tied0>, %EDX<kill>, %EFLAGS<imp-use,kill>
> MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %ECX<kill>; mem:ST4[%retval]
> JMP_1 <BB#38>
1280B	BB#12: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#10
1296B		CMP32mi8 <fi#2>, 1, %noreg, 0, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%action.addr]
1312B		JNE_1 <BB#14>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#14 BB#13
> CMP32mi8 <fi#2>, 1, %noreg, 0, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%action.addr]
> JNE_1 <BB#14>, %EFLAGS<imp-use,kill>
1328B	BB#13: derived from LLVM BB %if.then.13
	    Predecessors according to CFG: BB#12
1344B		%vreg105<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg105
1360B		%vreg104<def> = MOV32rm %vreg105<kill>, 1, %noreg, 8, %noreg; mem:LD4[%avail_in] GR32:%vreg104 GR64:%vreg105
1376B		%vreg102<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg102
1392B		MOV32mr %vreg102<kill>, 1, %noreg, 16, %noreg, %vreg104<kill>; mem:ST4[%avail_in_expect] GR64:%vreg102 GR32:%vreg104
1408B		%vreg99<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg99
1424B		MOV32mi %vreg99<kill>, 1, %noreg, 8, %noreg, 3; mem:ST4[%mode14] GR64:%vreg99
1440B		JMP_1 <BB#7>
	    Successors according to CFG: BB#7
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 8, %noreg; mem:LD4[%avail_in]
> %RCX<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> MOV32mr %RCX<kill>, 1, %noreg, 16, %noreg, %EAX<kill>; mem:ST4[%avail_in_expect]
> %RAX<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> MOV32mi %RAX<kill>, 1, %noreg, 8, %noreg, 3; mem:ST4[%mode14]
> JMP_1 <BB#7>
1456B	BB#14: derived from LLVM BB %if.else.15
	    Predecessors according to CFG: BB#12
1472B		CMP32mi8 <fi#2>, 1, %noreg, 0, %noreg, 2, %EFLAGS<imp-def>; mem:LD4[%action.addr]
1488B		JNE_1 <BB#16>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#16 BB#15
> CMP32mi8 <fi#2>, 1, %noreg, 0, %noreg, 2, %EFLAGS<imp-def>; mem:LD4[%action.addr]
> JNE_1 <BB#16>, %EFLAGS<imp-use,kill>
1504B	BB#15: derived from LLVM BB %if.then.18
	    Predecessors according to CFG: BB#14
1520B		%vreg97<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg97
1536B		%vreg96<def> = MOV32rm %vreg97<kill>, 1, %noreg, 8, %noreg; mem:LD4[%avail_in19] GR32:%vreg96 GR64:%vreg97
1552B		%vreg94<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg94
1568B		MOV32mr %vreg94<kill>, 1, %noreg, 16, %noreg, %vreg96<kill>; mem:ST4[%avail_in_expect20] GR64:%vreg94 GR32:%vreg96
1584B		%vreg91<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg91
1600B		MOV32mi %vreg91<kill>, 1, %noreg, 8, %noreg, 4; mem:ST4[%mode21] GR64:%vreg91
1616B		JMP_1 <BB#7>
	    Successors according to CFG: BB#7
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 8, %noreg; mem:LD4[%avail_in19]
> %RCX<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> MOV32mr %RCX<kill>, 1, %noreg, 16, %noreg, %EAX<kill>; mem:ST4[%avail_in_expect20]
> %RAX<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> MOV32mi %RAX<kill>, 1, %noreg, 8, %noreg, 4; mem:ST4[%mode21]
> JMP_1 <BB#7>
1632B	BB#16: derived from LLVM BB %if.else.22
	    Predecessors according to CFG: BB#14
1648B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
1664B		JMP_1 <BB#38>
	    Successors according to CFG: BB#38
> MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
> JMP_1 <BB#38>
1680B	BB#17: derived from LLVM BB %sw.bb.23
	    Predecessors according to CFG: BB#8
1696B		CMP32mi8 <fi#2>, 1, %noreg, 0, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%action.addr]
1712B		JE_1 <BB#19>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#19 BB#18
> CMP32mi8 <fi#2>, 1, %noreg, 0, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%action.addr]
> JE_1 <BB#19>, %EFLAGS<imp-use,kill>
1728B	BB#18: derived from LLVM BB %if.then.26
	    Predecessors according to CFG: BB#17
1744B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -1; mem:ST4[%retval]
1760B		JMP_1 <BB#38>
	    Successors according to CFG: BB#38
> MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -1; mem:ST4[%retval]
> JMP_1 <BB#38>
1776B	BB#19: derived from LLVM BB %if.end.27
	    Predecessors according to CFG: BB#17
1792B		%vreg66<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg66
1808B		%vreg65<def> = MOV32rm %vreg66<kill>, 1, %noreg, 16, %noreg; mem:LD4[%avail_in_expect28] GR32:%vreg65 GR64:%vreg66
1824B		%vreg63<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg63
1840B		%vreg62<def> = MOV64rm %vreg63<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm29] GR64:%vreg62,%vreg63
1856B		CMP32rm %vreg65<kill>, %vreg62<kill>, 1, %noreg, 8, %noreg, %EFLAGS<imp-def>; mem:LD4[%avail_in30] GR32:%vreg65 GR64:%vreg62
1872B		JE_1 <BB#21>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#21 BB#20
> %RAX<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 16, %noreg; mem:LD4[%avail_in_expect28]
> %RCX<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> %RCX<def> = MOV64rm %RCX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm29]
> CMP32rm %EAX<kill>, %RCX<kill>, 1, %noreg, 8, %noreg, %EFLAGS<imp-def>; mem:LD4[%avail_in30]
> JE_1 <BB#21>, %EFLAGS<imp-use,kill>
1888B	BB#20: derived from LLVM BB %if.then.33
	    Predecessors according to CFG: BB#19
1904B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -1; mem:ST4[%retval]
1920B		JMP_1 <BB#38>
	    Successors according to CFG: BB#38
> MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -1; mem:ST4[%retval]
> JMP_1 <BB#38>
1936B	BB#21: derived from LLVM BB %if.end.34
	    Predecessors according to CFG: BB#19
1952B		%vreg73<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg73
1968B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1984B		%RDI<def> = COPY %vreg73<kill>; GR64:%vreg73
2000B		CALL64pcrel32 <ga:@handle_compress>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %AL<imp-def>
2016B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2032B		%vreg72<def> = COPY %AL; GR8:%vreg72
2048B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2064B		STACKMAP 2, 0, 0, <fi#3>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack3](align=1) LD8[FixedStack0](align=4) LD8[FixedStack4]
2080B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2096B		MOV8mr <fi#3>, 1, %noreg, 0, %noreg, %vreg72<kill>; mem:ST1[%progress] GR8:%vreg72
2112B		%vreg69<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg69
2128B		CMP32mi8 %vreg69<kill>, 1, %noreg, 16, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_in_expect36] GR64:%vreg69
2144B		JA_1 <BB#24>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#24 BB#22
> %RDI<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@handle_compress>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %AL<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %AL<def> = COPY %AL
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 2, 0, 0, <fi#3>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack3](align=1) LD8[FixedStack0](align=4) LD8[FixedStack4]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV8mr <fi#3>, 1, %noreg, 0, %noreg, %AL<kill>; mem:ST1[%progress]
> %RAX<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> CMP32mi8 %RAX<kill>, 1, %noreg, 16, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_in_expect36]
> JA_1 <BB#24>, %EFLAGS<imp-use,kill>
2160B	BB#22: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#21
2176B		%vreg77<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg77
2192B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2208B		%RDI<def> = COPY %vreg77<kill>; GR64:%vreg77
2224B		CALL64pcrel32 <ga:@isempty_RL>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %AL<imp-def>
2240B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2256B		%vreg76<def> = COPY %AL; GR8:%vreg76
2272B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2288B		STACKMAP 3, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack4]
2304B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2320B		CMP8ri %vreg76<kill>, 0, %EFLAGS<imp-def>; GR8:%vreg76
2336B		JE_1 <BB#24>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#24 BB#23
> %RDI<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@isempty_RL>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %AL<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %AL<def> = COPY %AL
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 3, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack4]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> CMP8ri %AL<kill>, 0, %EFLAGS<imp-def>
> JE_1 <BB#24>, %EFLAGS<imp-use,kill>
2352B	BB#23: derived from LLVM BB %lor.lhs.false.41
	    Predecessors according to CFG: BB#22
2368B		%vreg84<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg84
2384B		%vreg83<def> = MOV32rm %vreg84<kill>, 1, %noreg, 120, %noreg; mem:LD4[%state_out_pos] GR32:%vreg83 GR64:%vreg84
2400B		%vreg81<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg81
2416B		CMP32rm %vreg83<kill>, %vreg81<kill>, 1, %noreg, 116, %noreg, %EFLAGS<imp-def>; mem:LD4[%numZ] GR32:%vreg83 GR64:%vreg81
2432B		JGE_1 <BB#25>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#25 BB#24
> %RAX<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 120, %noreg; mem:LD4[%state_out_pos]
> %RCX<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> CMP32rm %EAX<kill>, %RCX<kill>, 1, %noreg, 116, %noreg, %EFLAGS<imp-def>; mem:LD4[%numZ]
> JGE_1 <BB#25>, %EFLAGS<imp-use,kill>
2448B	BB#24: derived from LLVM BB %if.then.44
	    Predecessors according to CFG: BB#21 BB#22 BB#23
2464B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 2; mem:ST4[%retval]
2480B		JMP_1 <BB#38>
	    Successors according to CFG: BB#38
> MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 2; mem:ST4[%retval]
> JMP_1 <BB#38>
2496B	BB#25: derived from LLVM BB %if.end.45
	    Predecessors according to CFG: BB#23
2512B		%vreg86<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg86
2528B		MOV32mi %vreg86<kill>, 1, %noreg, 8, %noreg, 2; mem:ST4[%mode46] GR64:%vreg86
2544B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 1; mem:ST4[%retval]
2560B		JMP_1 <BB#38>
	    Successors according to CFG: BB#38
> %RAX<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> MOV32mi %RAX<kill>, 1, %noreg, 8, %noreg, 2; mem:ST4[%mode46]
> MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 1; mem:ST4[%retval]
> JMP_1 <BB#38>
2576B	BB#26: derived from LLVM BB %sw.bb.47
	    Predecessors according to CFG: BB#8
2592B		CMP32mi8 <fi#2>, 1, %noreg, 0, %noreg, 2, %EFLAGS<imp-def>; mem:LD4[%action.addr]
2608B		JE_1 <BB#28>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#28 BB#27
> CMP32mi8 <fi#2>, 1, %noreg, 0, %noreg, 2, %EFLAGS<imp-def>; mem:LD4[%action.addr]
> JE_1 <BB#28>, %EFLAGS<imp-use,kill>
2624B	BB#27: derived from LLVM BB %if.then.50
	    Predecessors according to CFG: BB#26
2640B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -1; mem:ST4[%retval]
2656B		JMP_1 <BB#38>
	    Successors according to CFG: BB#38
> MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -1; mem:ST4[%retval]
> JMP_1 <BB#38>
2672B	BB#28: derived from LLVM BB %if.end.51
	    Predecessors according to CFG: BB#26
2688B		%vreg35<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg35
2704B		%vreg34<def> = MOV32rm %vreg35<kill>, 1, %noreg, 16, %noreg; mem:LD4[%avail_in_expect52] GR32:%vreg34 GR64:%vreg35
2720B		%vreg32<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg32
2736B		%vreg31<def> = MOV64rm %vreg32<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm53] GR64:%vreg31,%vreg32
2752B		CMP32rm %vreg34<kill>, %vreg31<kill>, 1, %noreg, 8, %noreg, %EFLAGS<imp-def>; mem:LD4[%avail_in54] GR32:%vreg34 GR64:%vreg31
2768B		JE_1 <BB#30>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#30 BB#29
> %RAX<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 16, %noreg; mem:LD4[%avail_in_expect52]
> %RCX<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> %RCX<def> = MOV64rm %RCX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm53]
> CMP32rm %EAX<kill>, %RCX<kill>, 1, %noreg, 8, %noreg, %EFLAGS<imp-def>; mem:LD4[%avail_in54]
> JE_1 <BB#30>, %EFLAGS<imp-use,kill>
2784B	BB#29: derived from LLVM BB %if.then.57
	    Predecessors according to CFG: BB#28
2800B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -1; mem:ST4[%retval]
2816B		JMP_1 <BB#38>
	    Successors according to CFG: BB#38
> MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -1; mem:ST4[%retval]
> JMP_1 <BB#38>
2832B	BB#30: derived from LLVM BB %if.end.58
	    Predecessors according to CFG: BB#28
2848B		%vreg40<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg40
2864B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2880B		%RDI<def> = COPY %vreg40<kill>; GR64:%vreg40
2896B		CALL64pcrel32 <ga:@handle_compress>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %AL<imp-def>
2912B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2928B		%vreg39<def> = COPY %AL; GR8:%vreg39
2944B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2960B		STACKMAP 4, 0, 0, <fi#3>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack3](align=1) LD8[FixedStack0](align=4) LD8[FixedStack4]
2976B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2992B		MOV8mr <fi#3>, 1, %noreg, 0, %noreg, %vreg39<kill>; mem:ST1[%progress] GR8:%vreg39
3008B		CMP8mi <fi#3>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD1[%progress]
3024B		JNE_1 <BB#32>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#32 BB#31
> %RDI<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@handle_compress>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %AL<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %AL<def> = COPY %AL
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 4, 0, 0, <fi#3>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack3](align=1) LD8[FixedStack0](align=4) LD8[FixedStack4]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV8mr <fi#3>, 1, %noreg, 0, %noreg, %AL<kill>; mem:ST1[%progress]
> CMP8mi <fi#3>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD1[%progress]
> JNE_1 <BB#32>, %EFLAGS<imp-use,kill>
3040B	BB#31: derived from LLVM BB %if.then.61
	    Predecessors according to CFG: BB#30
3056B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -1; mem:ST4[%retval]
3072B		JMP_1 <BB#38>
	    Successors according to CFG: BB#38
> MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -1; mem:ST4[%retval]
> JMP_1 <BB#38>
3088B	BB#32: derived from LLVM BB %if.end.62
	    Predecessors according to CFG: BB#30
3104B		%vreg43<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg43
3120B		CMP32mi8 %vreg43<kill>, 1, %noreg, 16, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_in_expect63] GR64:%vreg43
3136B		JA_1 <BB#35>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#35 BB#33
> %RAX<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> CMP32mi8 %RAX<kill>, 1, %noreg, 16, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_in_expect63]
> JA_1 <BB#35>, %EFLAGS<imp-use,kill>
3152B	BB#33: derived from LLVM BB %lor.lhs.false.66
	    Predecessors according to CFG: BB#32
3168B		%vreg47<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg47
3184B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3200B		%RDI<def> = COPY %vreg47<kill>; GR64:%vreg47
3216B		CALL64pcrel32 <ga:@isempty_RL>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %AL<imp-def>
3232B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3248B		%vreg46<def> = COPY %AL; GR8:%vreg46
3264B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3280B		STACKMAP 5, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack4]
3296B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3312B		CMP8ri %vreg46<kill>, 0, %EFLAGS<imp-def>; GR8:%vreg46
3328B		JE_1 <BB#35>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#35 BB#34
> %RDI<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@isempty_RL>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %AL<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %AL<def> = COPY %AL
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 5, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack4]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> CMP8ri %AL<kill>, 0, %EFLAGS<imp-def>
> JE_1 <BB#35>, %EFLAGS<imp-use,kill>
3344B	BB#34: derived from LLVM BB %lor.lhs.false.69
	    Predecessors according to CFG: BB#33
3360B		%vreg54<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg54
3376B		%vreg53<def> = MOV32rm %vreg54<kill>, 1, %noreg, 120, %noreg; mem:LD4[%state_out_pos70] GR32:%vreg53 GR64:%vreg54
3392B		%vreg51<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg51
3408B		CMP32rm %vreg53<kill>, %vreg51<kill>, 1, %noreg, 116, %noreg, %EFLAGS<imp-def>; mem:LD4[%numZ71] GR32:%vreg53 GR64:%vreg51
3424B		JGE_1 <BB#36>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#36 BB#35
> %RAX<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 120, %noreg; mem:LD4[%state_out_pos70]
> %RCX<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> CMP32rm %EAX<kill>, %RCX<kill>, 1, %noreg, 116, %noreg, %EFLAGS<imp-def>; mem:LD4[%numZ71]
> JGE_1 <BB#36>, %EFLAGS<imp-use,kill>
3440B	BB#35: derived from LLVM BB %if.then.74
	    Predecessors according to CFG: BB#32 BB#33 BB#34
3456B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 3; mem:ST4[%retval]
3472B		JMP_1 <BB#38>
	    Successors according to CFG: BB#38
> MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 3; mem:ST4[%retval]
> JMP_1 <BB#38>
3488B	BB#36: derived from LLVM BB %if.end.75
	    Predecessors according to CFG: BB#34
3504B		%vreg56<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg56
3520B		MOV32mi %vreg56<kill>, 1, %noreg, 8, %noreg, 1; mem:ST4[%mode76] GR64:%vreg56
3536B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 4; mem:ST4[%retval]
3552B		JMP_1 <BB#38>
	    Successors according to CFG: BB#38
> %RAX<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> MOV32mi %RAX<kill>, 1, %noreg, 8, %noreg, 1; mem:ST4[%mode76]
> MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 4; mem:ST4[%retval]
> JMP_1 <BB#38>
3568B	BB#37: derived from LLVM BB %sw.epilog
	    Predecessors according to CFG: BB#7
3584B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
	    Successors according to CFG: BB#38
> MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
3600B	BB#38: derived from LLVM BB %return
	    Predecessors according to CFG: BB#31 BB#36 BB#35 BB#29 BB#27 BB#25 BB#24 BB#20 BB#18 BB#16 BB#11 BB#9 BB#37 BB#5 BB#3 BB#1
3616B		%vreg120<def> = MOV64ri <ga:@BZ2_bzCompress>; GR64:%vreg120
3648B		%vreg121<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg121
3664B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3680B		%RDI<def> = COPY %vreg120<kill>; GR64:%vreg120
3696B		%RSI<def> = COPY %vreg121<kill>; GR64:%vreg121
3712B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
3728B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3744B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3760B		STACKMAP 6, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
3776B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3792B		%vreg118<def> = MOV32rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD4[%retval] GR32:%vreg118
3808B		%EAX<def> = COPY %vreg118<kill>; GR32:%vreg118
3824B		RETQ %EAX<imp-use>
> %RDI<def> = MOV64ri <ga:@BZ2_bzCompress>
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 6, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def> = MOV32rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD4[%retval]
> %EAX<def> = COPY %EAX<kill>
Deleting identity copy.
> RETQ %EAX<imp-use>
Computing live-in reg-units in ABI blocks.
0B	BB#0 DIL#0
Created 1 new intervals.
********** INTERVALS **********
DIL [0B,16r:0)[112r,144r:10)[448r,464r:9)[944r,960r:8)[1184r,1200r:7)[1472r,1488r:6)[1808r,1824r:5)[2176r,2192r:2)[2416r,2464r:3)[2752r,2784r:4)[3488r,3520r:1)  0@0B-phi 1@3488r 2@2176r 3@2416r 4@2752r 5@1808r 6@1472r 7@1184r 8@944r 9@448r 10@112r
%vreg1 [3344r,3392r:0)  0@3344r
%vreg2 [16r,32r:0)  0@16r
%vreg3 [32r,224r:0)  0@32r
%vreg6 [304r,320r:0)  0@304r
%vreg8 [288r,304r:0)  0@288r
%vreg9 [272r,288r:0)  0@272r
%vreg10 [48r,64r:0)  0@48r
%vreg11 [64r,112r:0)  0@64r
%vreg12 [80r,128r:0)  0@80r
%vreg15 [352r,368r:0)  0@352r
%vreg19 [688r,704r:0)  0@688r
%vreg21 [672r,704r:0)  0@672r
%vreg22 [656r,672r:0)  0@656r
%vreg25 [624r,640r:0)  0@624r
%vreg28 [592r,608r:0)[608r,624r:1)  0@592r 1@608r
%vreg30 [576r,592r:0)  0@576r
%vreg32 [560r,608r:0)  0@560r
%vreg34 [496r,560r:0)  0@496r
%vreg35 [416r,448r:0)  0@416r
%vreg38 [784r,800r:0)  0@784r
%vreg41 [848r,864r:0)  0@848r
%vreg44 [1056r,1072r:0)  0@1056r
%vreg46 [992r,1056r:0)  0@992r
%vreg47 [912r,944r:0)  0@912r
%vreg50 [1312r,1328r:0)  0@1312r
%vreg52 [1280r,1296r:0)  0@1280r
%vreg54 [1152r,1184r:0)  0@1152r
%vreg57 [1376r,1392r:0)  0@1376r
%vreg60 [1584r,1600r:0)  0@1584r
%vreg62 [1520r,1584r:0)  0@1520r
%vreg63 [1440r,1472r:0)  0@1440r
%vreg66 [1712r,1728r:0)  0@1712r
%vreg69 [2016r,2032r:0)  0@2016r
%vreg72 [1984r,2000r:0)  0@1984r
%vreg75 [1952r,1968r:0)[1968r,1984r:1)  0@1952r 1@1968r
%vreg77 [1936r,1952r:0)  0@1936r
%vreg79 [1920r,1968r:0)  0@1920r
%vreg81 [1856r,1920r:0)  0@1856r
%vreg82 [1776r,1808r:0)  0@1776r
%vreg85 [2080r,2096r:0)  0@2080r
%vreg89 [2640r,2656r:0)  0@2640r
%vreg91 [2624r,2656r:0)  0@2624r
%vreg92 [2608r,2624r:0)  0@2608r
%vreg96 [2944r,2960r:0)  0@2944r
%vreg97 [2928r,2944r:0)  0@2928r
%vreg99 [2864r,2880r:0)  0@2864r
%vreg101 [2704r,2768r:0)  0@2704r
%vreg102 [2720r,2752r:0)  0@2720r
%vreg104 [2544r,2560r:0)  0@2544r
%vreg107 [2432r,2448r:0)  0@2432r
%vreg109 [2384r,2432r:0)  0@2384r
%vreg111 [2336r,2352r:0)[2352r,2368r:1)  0@2336r 1@2352r
%vreg112 [2368r,2384r:0)  0@2368r
%vreg113 [2320r,2336r:0)  0@2320r
%vreg116 [2288r,2304r:0)  0@2288r
%vreg117 [2272r,2416r:0)  0@2272r
%vreg119 [2144r,2176r:0)  0@2144r
%vreg120 [3168r,3216r:0)  0@3168r
%vreg123 [3184r,3200r:0)  0@3184r
%vreg124 [3296r,3312r:0)  0@3296r
%vreg127 [3264r,3280r:0)  0@3264r
%vreg129 [3360r,3376r:0)  0@3360r
%vreg130 [3376r,3488r:0)  0@3376r
%vreg131 [3456r,3504r:0)  0@3456r
%vreg133 [3440r,3600r:0)  0@3440r
%vreg134 [3392r,3408r:0)[3408r,3424r:1)  0@3392r 1@3408r
%vreg135 [3424r,3440r:0)  0@3424r
%vreg136 [3216r,3248B:0)[3312r,3328B:1)[3328B,3344r:2)  0@3216r 1@3312r 2@3328B-phi
RegMasks: 144r 464r 960r 1200r 1488r 1824r 2192r 2464r 2784r 3520r
********** MACHINEINSTRS **********
# Machine code for function handle_compress: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=8, align=8, at location [SP+8]
  fi#1: size=1, align=1, at location [SP+8]
  fi#2: size=1, align=1, at location [SP+8]
  fi#3: size=8, align=8, at location [SP+8]
Function Live Ins: %RDI in %vreg2

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI
16B		%vreg2<def> = COPY %RDI; GR64:%vreg2
32B		%vreg3<def> = COPY %vreg2; GR64:%vreg3,%vreg2
48B		%vreg10<def> = MOV64ri <ga:@handle_compress>; GR64:%vreg10
64B		%vreg11<def> = COPY %vreg10; GR64:%vreg11,%vreg10
80B		%vreg12<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg12
96B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
112B		%RDI<def> = COPY %vreg11; GR64:%vreg11
128B		%RSI<def> = COPY %vreg12; GR64:%vreg12
144B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
160B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
192B		STACKMAP 0, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, %vreg3, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3] LD8[FixedStack0] GR64:%vreg3
208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg3; mem:ST8[%strm.addr] GR64:%vreg3
240B		MOV8mi <fi#1>, 1, %noreg, 0, %noreg, 0; mem:ST1[%progress_in]
256B		MOV8mi <fi#2>, 1, %noreg, 0, %noreg, 0; mem:ST1[%progress_out]
272B		%vreg9<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg9
288B		%vreg8<def> = MOV64rm %vreg9, 1, %noreg, 48, %noreg; mem:LD8[%state] GR64:%vreg8,%vreg9
304B		%vreg6<def> = COPY %vreg8; GR64:%vreg6,%vreg8
320B		MOV64mr <fi#3>, 1, %noreg, 0, %noreg, %vreg6; mem:ST8[%s] GR64:%vreg6
	    Successors according to CFG: BB#1

336B	BB#1: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#0 BB#24
352B		%vreg15<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg15
368B		CMP32mi8 %vreg15, 1, %noreg, 12, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%state1] GR64:%vreg15
384B		JNE_1 <BB#13>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#13 BB#2

400B	BB#2: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#1
416B		%vreg35<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg35
432B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
448B		%RDI<def> = COPY %vreg35; GR64:%vreg35
464B		CALL64pcrel32 <ga:@copy_output_until_stop>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %AL<imp-def>
480B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
496B		%vreg34<def> = COPY %AL<kill>; GR8:%vreg34
512B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
528B		STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
544B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
560B		%vreg32<def> = MOVZX32rr8 %vreg34; GR32:%vreg32 GR8:%vreg34
576B		%vreg30<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%progress_out] GR32:%vreg30
592B		%vreg28<def> = COPY %vreg30; GR32:%vreg28,%vreg30
608B		%vreg28<def,tied1> = OR32rr %vreg28<tied0>, %vreg32, %EFLAGS<imp-def,dead>; GR32:%vreg28,%vreg32
624B		%vreg25<def> = COPY %vreg28:sub_8bit; GR8:%vreg25 GR32:%vreg28
640B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg25; mem:ST1[%progress_out] GR8:%vreg25
656B		%vreg22<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg22
672B		%vreg21<def> = MOV32rm %vreg22, 1, %noreg, 120, %noreg; mem:LD4[%state_out_pos] GR32:%vreg21 GR64:%vreg22
688B		%vreg19<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg19
704B		CMP32rm %vreg21, %vreg19, 1, %noreg, 116, %noreg, %EFLAGS<imp-def>; mem:LD4[%numZ] GR32:%vreg21 GR64:%vreg19
720B		JGE_1 <BB#4>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#4 BB#3

736B	BB#3: derived from LLVM BB %if.then.6
	    Predecessors according to CFG: BB#2
752B		JMP_1 <BB#25>
	    Successors according to CFG: BB#25

768B	BB#4: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#2
784B		%vreg38<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg38
800B		CMP32mi8 %vreg38, 1, %noreg, 8, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%mode] GR64:%vreg38
816B		JNE_1 <BB#8>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#8 BB#5

832B	BB#5: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#4
848B		%vreg41<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg41
864B		CMP32mi8 %vreg41, 1, %noreg, 16, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_in_expect] GR64:%vreg41
880B		JNE_1 <BB#8>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#8 BB#6

896B	BB#6: derived from LLVM BB %land.lhs.true.11
	    Predecessors according to CFG: BB#5
912B		%vreg47<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg47
928B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
944B		%RDI<def> = COPY %vreg47; GR64:%vreg47
960B		CALL64pcrel32 <ga:@isempty_RL>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %AL<imp-def>
976B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
992B		%vreg46<def> = COPY %AL<kill>; GR8:%vreg46
1008B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1024B		STACKMAP 2, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
1040B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1056B		%vreg44<def> = MOVZX32rr8 %vreg46; GR32:%vreg44 GR8:%vreg46
1072B		CMP32ri8 %vreg44, 0, %EFLAGS<imp-def>; GR32:%vreg44
1088B		JE_1 <BB#8>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#8 BB#7

1104B	BB#7: derived from LLVM BB %if.then.14
	    Predecessors according to CFG: BB#6
1120B		JMP_1 <BB#25>
	    Successors according to CFG: BB#25

1136B	BB#8: derived from LLVM BB %if.end.15
	    Predecessors according to CFG: BB#4 BB#5 BB#6
1152B		%vreg54<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg54
1168B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1184B		%RDI<def> = COPY %vreg54; GR64:%vreg54
1200B		CALL64pcrel32 <ga:@prepare_new_block>, <regmask>, %RSP<imp-use>, %RDI<imp-use>
1216B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1232B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1248B		STACKMAP 3, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
1264B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1280B		%vreg52<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg52
1296B		MOV32mi %vreg52, 1, %noreg, 12, %noreg, 2; mem:ST4[%state16] GR64:%vreg52
1312B		%vreg50<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg50
1328B		CMP32mi8 %vreg50, 1, %noreg, 8, %noreg, 3, %EFLAGS<imp-def>; mem:LD4[%mode17] GR64:%vreg50
1344B		JNE_1 <BB#12>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#12 BB#9

1360B	BB#9: derived from LLVM BB %land.lhs.true.20
	    Predecessors according to CFG: BB#8
1376B		%vreg57<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg57
1392B		CMP32mi8 %vreg57, 1, %noreg, 16, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_in_expect21] GR64:%vreg57
1408B		JNE_1 <BB#12>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#12 BB#10

1424B	BB#10: derived from LLVM BB %land.lhs.true.24
	    Predecessors according to CFG: BB#9
1440B		%vreg63<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg63
1456B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1472B		%RDI<def> = COPY %vreg63; GR64:%vreg63
1488B		CALL64pcrel32 <ga:@isempty_RL>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %AL<imp-def>
1504B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1520B		%vreg62<def> = COPY %AL<kill>; GR8:%vreg62
1536B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1552B		STACKMAP 4, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
1568B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1584B		%vreg60<def> = MOVZX32rr8 %vreg62; GR32:%vreg60 GR8:%vreg62
1600B		CMP32ri8 %vreg60, 0, %EFLAGS<imp-def>; GR32:%vreg60
1616B		JE_1 <BB#12>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#12 BB#11

1632B	BB#11: derived from LLVM BB %if.then.28
	    Predecessors according to CFG: BB#10
1648B		JMP_1 <BB#25>
	    Successors according to CFG: BB#25

1664B	BB#12: derived from LLVM BB %if.end.29
	    Predecessors according to CFG: BB#8 BB#9 BB#10
1680B		JMP_1 <BB#13>
	    Successors according to CFG: BB#13

1696B	BB#13: derived from LLVM BB %if.end.30
	    Predecessors according to CFG: BB#1 BB#12
1712B		%vreg66<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg66
1728B		CMP32mi8 %vreg66, 1, %noreg, 12, %noreg, 2, %EFLAGS<imp-def>; mem:LD4[%state31] GR64:%vreg66
1744B		JNE_1 <BB#24>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#24 BB#14

1760B	BB#14: derived from LLVM BB %if.then.34
	    Predecessors according to CFG: BB#13
1776B		%vreg82<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg82
1792B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1808B		%RDI<def> = COPY %vreg82; GR64:%vreg82
1824B		CALL64pcrel32 <ga:@copy_input_until_stop>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %AL<imp-def>
1840B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1856B		%vreg81<def> = COPY %AL<kill>; GR8:%vreg81
1872B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1888B		STACKMAP 5, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
1904B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1920B		%vreg79<def> = MOVZX32rr8 %vreg81; GR32:%vreg79 GR8:%vreg81
1936B		%vreg77<def> = MOVZX32rm8 <fi#1>, 1, %noreg, 0, %noreg; mem:LD1[%progress_in] GR32:%vreg77
1952B		%vreg75<def> = COPY %vreg77; GR32:%vreg75,%vreg77
1968B		%vreg75<def,tied1> = OR32rr %vreg75<tied0>, %vreg79, %EFLAGS<imp-def,dead>; GR32:%vreg75,%vreg79
1984B		%vreg72<def> = COPY %vreg75:sub_8bit; GR8:%vreg72 GR32:%vreg75
2000B		MOV8mr <fi#1>, 1, %noreg, 0, %noreg, %vreg72; mem:ST1[%progress_in] GR8:%vreg72
2016B		%vreg69<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg69
2032B		CMP32mi8 %vreg69, 1, %noreg, 8, %noreg, 2, %EFLAGS<imp-def>; mem:LD4[%mode40] GR64:%vreg69
2048B		JE_1 <BB#17>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#17 BB#15

2064B	BB#15: derived from LLVM BB %land.lhs.true.43
	    Predecessors according to CFG: BB#14
2080B		%vreg85<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg85
2096B		CMP32mi8 %vreg85, 1, %noreg, 16, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_in_expect44] GR64:%vreg85
2112B		JNE_1 <BB#17>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#17 BB#16

2128B	BB#16: derived from LLVM BB %if.then.47
	    Predecessors according to CFG: BB#15
2144B		%vreg119<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg119
2160B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2176B		%RDI<def> = COPY %vreg119; GR64:%vreg119
2192B		CALL64pcrel32 <ga:@flush_RL>, <regmask>, %RSP<imp-use>, %RDI<imp-use>
2208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2224B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2240B		STACKMAP 6, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
2256B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2272B		%vreg117<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg117
2288B		%vreg116<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg116
2304B		CMP32mi8 %vreg116, 1, %noreg, 8, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%mode48] GR64:%vreg116
2320B		%vreg113<def> = SETEr %EFLAGS<imp-use,kill>; GR8:%vreg113
2336B		%vreg111<def> = COPY %vreg113; GR8:%vreg111,%vreg113
2352B		%vreg111<def,tied1> = AND8ri %vreg111<tied0>, 1, %EFLAGS<imp-def,dead>; GR8:%vreg111
2368B		%vreg112<def> = MOVZX32rr8 %vreg111; GR32:%vreg112 GR8:%vreg111
2384B		%vreg109<def> = COPY %vreg112:sub_8bit; GR8:%vreg109 GR32:%vreg112
2400B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2416B		%RDI<def> = COPY %vreg117; GR64:%vreg117
2432B		%vreg107<def> = MOVZX32rr8 %vreg109; GR32:%vreg107 GR8:%vreg109
2448B		%ESI<def> = COPY %vreg107; GR32:%vreg107
2464B		CALL64pcrel32 <ga:@BZ2_compressBlock>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use,kill>
2480B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2496B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2512B		STACKMAP 7, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
2528B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2544B		%vreg104<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg104
2560B		MOV32mi %vreg104, 1, %noreg, 12, %noreg, 1; mem:ST4[%state52] GR64:%vreg104
2576B		JMP_1 <BB#23>
	    Successors according to CFG: BB#23

2592B	BB#17: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#14 BB#15
2608B		%vreg92<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg92
2624B		%vreg91<def> = MOV32rm %vreg92, 1, %noreg, 108, %noreg; mem:LD4[%nblock] GR32:%vreg91 GR64:%vreg92
2640B		%vreg89<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg89
2656B		CMP32rm %vreg91, %vreg89, 1, %noreg, 112, %noreg, %EFLAGS<imp-def>; mem:LD4[%nblockMAX] GR32:%vreg91 GR64:%vreg89
2672B		JL_1 <BB#19>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#19 BB#18

2688B	BB#18: derived from LLVM BB %if.then.55
	    Predecessors according to CFG: BB#17
2704B		%vreg101<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg101
2720B		%vreg102<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg102
2736B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2752B		%RDI<def> = COPY %vreg102; GR64:%vreg102
2768B		%ESI<def> = COPY %vreg101; GR32:%vreg101
2784B		CALL64pcrel32 <ga:@BZ2_compressBlock>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use,kill>
2800B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2816B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2832B		STACKMAP 8, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
2848B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2864B		%vreg99<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg99
2880B		MOV32mi %vreg99, 1, %noreg, 12, %noreg, 1; mem:ST4[%state56] GR64:%vreg99
2896B		JMP_1 <BB#22>
	    Successors according to CFG: BB#22

2912B	BB#19: derived from LLVM BB %if.else.57
	    Predecessors according to CFG: BB#17
2928B		%vreg97<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg97
2944B		%vreg96<def> = MOV64rm %vreg97, 1, %noreg, 0, %noreg; mem:LD8[%strm58] GR64:%vreg96,%vreg97
2960B		CMP32mi8 %vreg96, 1, %noreg, 8, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_in] GR64:%vreg96
2976B		JNE_1 <BB#21>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#21 BB#20

2992B	BB#20: derived from LLVM BB %if.then.61
	    Predecessors according to CFG: BB#19
3008B		JMP_1 <BB#25>
	    Successors according to CFG: BB#25

3024B	BB#21: derived from LLVM BB %if.end.62
	    Predecessors according to CFG: BB#19
3040B		JMP_1 <BB#22>
	    Successors according to CFG: BB#22

3056B	BB#22: derived from LLVM BB %if.end.63
	    Predecessors according to CFG: BB#21 BB#18
3072B		JMP_1 <BB#23>
	    Successors according to CFG: BB#23

3088B	BB#23: derived from LLVM BB %if.end.64
	    Predecessors according to CFG: BB#22 BB#16
3104B		JMP_1 <BB#24>
	    Successors according to CFG: BB#24

3120B	BB#24: derived from LLVM BB %if.end.65
	    Predecessors according to CFG: BB#13 BB#23
3136B		JMP_1 <BB#1>
	    Successors according to CFG: BB#1

3152B	BB#25: derived from LLVM BB %while.end
	    Predecessors according to CFG: BB#20 BB#11 BB#7 BB#3
3168B		%vreg120<def> = MOV8ri 1; GR8:%vreg120
3184B		%vreg123<def> = MOVZX32rm8 <fi#1>, 1, %noreg, 0, %noreg; mem:LD1[%progress_in] GR32:%vreg123
3200B		CMP32ri8 %vreg123, 0, %EFLAGS<imp-def>; GR32:%vreg123
3216B		%vreg136<def> = COPY %vreg120; GR8:%vreg136,%vreg120
3232B		JNE_1 <BB#27>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#27 BB#26

3248B	BB#26: derived from LLVM BB %lor.rhs
	    Predecessors according to CFG: BB#25
3264B		%vreg127<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%progress_out] GR32:%vreg127
3280B		CMP32ri8 %vreg127, 0, %EFLAGS<imp-def>; GR32:%vreg127
3296B		%vreg124<def> = SETNEr %EFLAGS<imp-use,kill>; GR8:%vreg124
3312B		%vreg136<def> = COPY %vreg124; GR8:%vreg136,%vreg124
	    Successors according to CFG: BB#27

3328B	BB#27: derived from LLVM BB %lor.end
	    Predecessors according to CFG: BB#25 BB#26
3344B		%vreg1<def> = COPY %vreg136; GR8:%vreg1,%vreg136
3360B		%vreg129<def> = MOV64ri <ga:@handle_compress>; GR64:%vreg129
3376B		%vreg130<def> = COPY %vreg129; GR64:%vreg130,%vreg129
3392B		%vreg134<def> = COPY %vreg1; GR8:%vreg134,%vreg1
3408B		%vreg134<def,tied1> = AND8ri %vreg134<tied0>, 1, %EFLAGS<imp-def,dead>; GR8:%vreg134
3424B		%vreg135<def> = MOVZX32rr8 %vreg134; GR32:%vreg135 GR8:%vreg134
3440B		%vreg133<def> = COPY %vreg135:sub_8bit; GR8:%vreg133 GR32:%vreg135
3456B		%vreg131<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg131
3472B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3488B		%RDI<def> = COPY %vreg130; GR64:%vreg130
3504B		%RSI<def> = COPY %vreg131; GR64:%vreg131
3520B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
3536B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3552B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3568B		STACKMAP 9, 0, %vreg133, ...; GR8:%vreg133
3584B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3600B		%AL<def> = COPY %vreg133; GR8:%vreg133
3616B		RETQ %AL<imp-use,kill>

# End machine code for function handle_compress.

********** SIMPLE REGISTER COALESCING **********
********** Function: handle_compress
********** JOINING INTERVALS ***********
if.end.15:
1184B	%RDI<def> = COPY %vreg54; GR64:%vreg54
	Considering merging %vreg54 with %RDI
	Can only merge into reserved registers.
while.body:
if.end.29:
if.end.30:
if.else:
if.then:
448B	%RDI<def> = COPY %vreg35; GR64:%vreg35
	Considering merging %vreg35 with %RDI
	Can only merge into reserved registers.
496B	%vreg34<def> = COPY %AL<kill>; GR8:%vreg34
	Considering merging %vreg34 with %AL
	Can only merge into reserved registers.
if.end:
land.lhs.true:
land.lhs.true.11:
944B	%RDI<def> = COPY %vreg47; GR64:%vreg47
	Considering merging %vreg47 with %RDI
	Can only merge into reserved registers.
992B	%vreg46<def> = COPY %AL<kill>; GR8:%vreg46
	Considering merging %vreg46 with %AL
	Can only merge into reserved registers.
land.lhs.true.20:
land.lhs.true.24:
1472B	%RDI<def> = COPY %vreg63; GR64:%vreg63
	Considering merging %vreg63 with %RDI
	Can only merge into reserved registers.
1520B	%vreg62<def> = COPY %AL<kill>; GR8:%vreg62
	Considering merging %vreg62 with %AL
	Can only merge into reserved registers.
if.then.34:
1808B	%RDI<def> = COPY %vreg82; GR64:%vreg82
	Considering merging %vreg82 with %RDI
	Can only merge into reserved registers.
1856B	%vreg81<def> = COPY %AL<kill>; GR8:%vreg81
	Considering merging %vreg81 with %AL
	Can only merge into reserved registers.
land.lhs.true.43:
if.else.57:
if.end.63:
if.end.64:
if.end.65:
if.then.47:
2176B	%RDI<def> = COPY %vreg119; GR64:%vreg119
	Considering merging %vreg119 with %RDI
	Can only merge into reserved registers.
2416B	%RDI<def> = COPY %vreg117; GR64:%vreg117
	Considering merging %vreg117 with %RDI
	Can only merge into reserved registers.
2448B	%ESI<def> = COPY %vreg107; GR32:%vreg107
	Considering merging %vreg107 with %ESI
	Can only merge into reserved registers.
if.then.55:
2752B	%RDI<def> = COPY %vreg102; GR64:%vreg102
	Considering merging %vreg102 with %RDI
	Can only merge into reserved registers.
2768B	%ESI<def> = COPY %vreg101; GR32:%vreg101
	Considering merging %vreg101 with %ESI
	Can only merge into reserved registers.
Remat: %ESI<def> = MOV32r0 %EFLAGS<imp-def,dead>
Shrink: %vreg101 [2704r,2768r:0)  0@2704r
All defs dead: 2704r	%vreg101<def,dead> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg101
Shrunk: %vreg101 [2704r,2704d:0)  0@2704r
Deleting dead def 2704r	%vreg101<def,dead> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg101
if.end.62:
592B	%vreg28<def> = COPY %vreg30; GR32:%vreg28,%vreg30
	Considering merging to GR32 with %vreg30 in %vreg28
		RHS = %vreg30 [576r,592r:0)  0@576r
		LHS = %vreg28 [592r,608r:0)[608r,624r:1)  0@592r 1@608r
		merge %vreg28:0@592r into %vreg30:0@576r --> @576r
		erased:	592r	%vreg28<def> = COPY %vreg30; GR32:%vreg28,%vreg30
		updated: 576B	%vreg28<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%progress_out] GR32:%vreg28
	Success: %vreg30 -> %vreg28
	Result = %vreg28 [576r,608r:0)[608r,624r:1)  0@576r 1@608r
624B	%vreg25<def> = COPY %vreg28:sub_8bit; GR8:%vreg25 GR32:%vreg28
	Considering merging to GR32 with %vreg25 in %vreg28:sub_8bit
		RHS = %vreg25 [624r,640r:0)  0@624r
		LHS = %vreg28 [576r,608r:0)[608r,624r:1)  0@576r 1@608r
		merge %vreg25:0@624r into %vreg28:1@608r --> @608r
		erased:	624r	%vreg25<def> = COPY %vreg28:sub_8bit; GR8:%vreg25 GR32:%vreg28
		updated: 640B	MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg28:sub_8bit; mem:ST1[%progress_out] GR32:%vreg28
	Success: %vreg25:sub_8bit -> %vreg28
	Result = %vreg28 [576r,608r:0)[608r,640r:1)  0@576r 1@608r
1952B	%vreg75<def> = COPY %vreg77; GR32:%vreg75,%vreg77
	Considering merging to GR32 with %vreg77 in %vreg75
		RHS = %vreg77 [1936r,1952r:0)  0@1936r
		LHS = %vreg75 [1952r,1968r:0)[1968r,1984r:1)  0@1952r 1@1968r
		merge %vreg75:0@1952r into %vreg77:0@1936r --> @1936r
		erased:	1952r	%vreg75<def> = COPY %vreg77; GR32:%vreg75,%vreg77
		updated: 1936B	%vreg75<def> = MOVZX32rm8 <fi#1>, 1, %noreg, 0, %noreg; mem:LD1[%progress_in] GR32:%vreg75
	Success: %vreg77 -> %vreg75
	Result = %vreg75 [1936r,1968r:0)[1968r,1984r:1)  0@1936r 1@1968r
1984B	%vreg72<def> = COPY %vreg75:sub_8bit; GR8:%vreg72 GR32:%vreg75
	Considering merging to GR32 with %vreg72 in %vreg75:sub_8bit
		RHS = %vreg72 [1984r,2000r:0)  0@1984r
		LHS = %vreg75 [1936r,1968r:0)[1968r,1984r:1)  0@1936r 1@1968r
		merge %vreg72:0@1984r into %vreg75:1@1968r --> @1968r
		erased:	1984r	%vreg72<def> = COPY %vreg75:sub_8bit; GR8:%vreg72 GR32:%vreg75
		updated: 2000B	MOV8mr <fi#1>, 1, %noreg, 0, %noreg, %vreg75:sub_8bit; mem:ST1[%progress_in] GR32:%vreg75
	Success: %vreg72:sub_8bit -> %vreg75
	Result = %vreg75 [1936r,1968r:0)[1968r,2000r:1)  0@1936r 1@1968r
2336B	%vreg111<def> = COPY %vreg113; GR8:%vreg111,%vreg113
	Considering merging to GR8 with %vreg113 in %vreg111
		RHS = %vreg113 [2320r,2336r:0)  0@2320r
		LHS = %vreg111 [2336r,2352r:0)[2352r,2368r:1)  0@2336r 1@2352r
		merge %vreg111:0@2336r into %vreg113:0@2320r --> @2320r
		erased:	2336r	%vreg111<def> = COPY %vreg113; GR8:%vreg111,%vreg113
AllocationOrder(GR8) = [ %AL %CL %DL %SIL %DIL %R8B %R9B %R10B %R11B %BL %R14B %R15B %R12B %R13B ]
		updated: 2320B	%vreg111<def> = SETEr %EFLAGS<imp-use,kill>; GR8:%vreg111
	Success: %vreg113 -> %vreg111
	Result = %vreg111 [2320r,2352r:0)[2352r,2368r:1)  0@2320r 1@2352r
2384B	%vreg109<def> = COPY %vreg112:sub_8bit; GR8:%vreg109 GR32:%vreg112
	Considering merging to GR32 with %vreg109 in %vreg112:sub_8bit
		RHS = %vreg109 [2384r,2432r:0)  0@2384r
		LHS = %vreg112 [2368r,2384r:0)  0@2368r
		merge %vreg109:0@2384r into %vreg112:0@2368r --> @2368r
		erased:	2384r	%vreg109<def> = COPY %vreg112:sub_8bit; GR8:%vreg109 GR32:%vreg112
		updated: 2432B	%vreg107<def> = MOVZX32rr8 %vreg112:sub_8bit; GR32:%vreg107,%vreg112
	Success: %vreg109:sub_8bit -> %vreg112
	Result = %vreg112 [2368r,2432r:0)  0@2368r
while.end:
if.then.6:
if.then.14:
if.then.28:
if.then.61:
lor.rhs:
lor.end:
3488B	%RDI<def> = COPY %vreg130; GR64:%vreg130
	Considering merging %vreg130 with %RDI
	Can only merge into reserved registers.
3504B	%RSI<def> = COPY %vreg131; GR64:%vreg131
	Considering merging %vreg131 with %RSI
	Can only merge into reserved registers.
3600B	%AL<def> = COPY %vreg133; GR8:%vreg133
	Considering merging %vreg133 with %AL
	Can only merge into reserved registers.
entry:
16B	%vreg2<def> = COPY %RDI; GR64:%vreg2
	Considering merging %vreg2 with %RDI
	Can only merge into reserved registers.
112B	%RDI<def> = COPY %vreg11; GR64:%vreg11
	Considering merging %vreg11 with %RDI
	Can only merge into reserved registers.
128B	%RSI<def> = COPY %vreg12; GR64:%vreg12
	Considering merging %vreg12 with %RSI
	Can only merge into reserved registers.
3216B	%vreg136<def> = COPY %vreg120; GR8:%vreg136,%vreg120
	Considering merging to GR8 with %vreg120 in %vreg136
		RHS = %vreg120 [3168r,3216r:0)  0@3168r
		LHS = %vreg136 [3216r,3248B:0)[3312r,3328B:1)[3328B,3344r:2)  0@3216r 1@3312r 2@3328B-phi
		merge %vreg136:0@3216r into %vreg120:0@3168r --> @3168r
		erased:	3216r	%vreg136<def> = COPY %vreg120; GR8:%vreg136,%vreg120
		updated: 3168B	%vreg136<def> = MOV8ri 1; GR8:%vreg136
	Success: %vreg120 -> %vreg136
	Result = %vreg136 [3168r,3248B:0)[3312r,3328B:1)[3328B,3344r:2)  0@3168r 1@3312r 2@3328B-phi
3312B	%vreg136<def> = COPY %vreg124; GR8:%vreg136,%vreg124
	Considering merging to GR8 with %vreg124 in %vreg136
		RHS = %vreg124 [3296r,3312r:0)  0@3296r
		LHS = %vreg136 [3168r,3248B:0)[3312r,3328B:1)[3328B,3344r:2)  0@3168r 1@3312r 2@3328B-phi
		merge %vreg136:1@3312r into %vreg124:0@3296r --> @3296r
		erased:	3312r	%vreg136<def> = COPY %vreg124; GR8:%vreg136,%vreg124
		updated: 3296B	%vreg136<def> = SETNEr %EFLAGS<imp-use,kill>; GR8:%vreg136
	Success: %vreg124 -> %vreg136
	Result = %vreg136 [3168r,3248B:0)[3296r,3328B:1)[3328B,3344r:2)  0@3168r 1@3296r 2@3328B-phi
3344B	%vreg1<def> = COPY %vreg136; GR8:%vreg1,%vreg136
	Considering merging to GR8 with %vreg1 in %vreg136
		RHS = %vreg1 [3344r,3392r:0)  0@3344r
		LHS = %vreg136 [3168r,3248B:0)[3296r,3328B:1)[3328B,3344r:2)  0@3168r 1@3296r 2@3328B-phi
		merge %vreg1:0@3344r into %vreg136:2@3328B --> @3328B
		erased:	3344r	%vreg1<def> = COPY %vreg136; GR8:%vreg1,%vreg136
		updated: 3392B	%vreg134<def> = COPY %vreg136; GR8:%vreg134,%vreg136
	Success: %vreg1 -> %vreg136
	Result = %vreg136 [3168r,3248B:0)[3296r,3328B:1)[3328B,3392r:2)  0@3168r 1@3296r 2@3328B-phi
3376B	%vreg130<def> = COPY %vreg129; GR64:%vreg130,%vreg129
	Considering merging to GR64 with %vreg129 in %vreg130
		RHS = %vreg129 [3360r,3376r:0)  0@3360r
		LHS = %vreg130 [3376r,3488r:0)  0@3376r
		merge %vreg130:0@3376r into %vreg129:0@3360r --> @3360r
		erased:	3376r	%vreg130<def> = COPY %vreg129; GR64:%vreg130,%vreg129
		updated: 3360B	%vreg130<def> = MOV64ri <ga:@handle_compress>; GR64:%vreg130
	Success: %vreg129 -> %vreg130
	Result = %vreg130 [3360r,3488r:0)  0@3360r
3392B	%vreg134<def> = COPY %vreg136; GR8:%vreg134,%vreg136
	Considering merging to GR8 with %vreg134 in %vreg136
		RHS = %vreg134 [3392r,3408r:0)[3408r,3424r:1)  0@3392r 1@3408r
		LHS = %vreg136 [3168r,3248B:0)[3296r,3328B:1)[3328B,3392r:2)  0@3168r 1@3296r 2@3328B-phi
		merge %vreg134:0@3392r into %vreg136:2@3328B --> @3328B
		erased:	3392r	%vreg134<def> = COPY %vreg136; GR8:%vreg134,%vreg136
		updated: 3408B	%vreg136<def,tied1> = AND8ri %vreg136<tied0>, 1, %EFLAGS<imp-def,dead>; GR8:%vreg136
		updated: 3424B	%vreg135<def> = MOVZX32rr8 %vreg136; GR32:%vreg135 GR8:%vreg136
	Success: %vreg134 -> %vreg136
	Result = %vreg136 [3168r,3248B:0)[3296r,3328B:1)[3328B,3408r:2)[3408r,3424r:3)  0@3168r 1@3296r 2@3328B-phi 3@3408r
3440B	%vreg133<def> = COPY %vreg135:sub_8bit; GR8:%vreg133 GR32:%vreg135
	Considering merging to GR32 with %vreg133 in %vreg135:sub_8bit
		RHS = %vreg133 [3440r,3600r:0)  0@3440r
		LHS = %vreg135 [3424r,3440r:0)  0@3424r
		merge %vreg133:0@3440r into %vreg135:0@3424r --> @3424r
		erased:	3440r	%vreg133<def> = COPY %vreg135:sub_8bit; GR8:%vreg133 GR32:%vreg135
		updated: 3600B	%AL<def> = COPY %vreg135:sub_8bit; GR32:%vreg135
		updated: 3568B	STACKMAP 9, 0, %vreg135:sub_8bit, ...; GR32:%vreg135
	Success: %vreg133:sub_8bit -> %vreg135
	Result = %vreg135 [3424r,3600r:0)  0@3424r
32B	%vreg3<def> = COPY %vreg2; GR64:%vreg3,%vreg2
	Considering merging to GR64 with %vreg2 in %vreg3
		RHS = %vreg2 [16r,32r:0)  0@16r
		LHS = %vreg3 [32r,224r:0)  0@32r
		merge %vreg3:0@32r into %vreg2:0@16r --> @16r
		erased:	32r	%vreg3<def> = COPY %vreg2; GR64:%vreg3,%vreg2
		updated: 16B	%vreg3<def> = COPY %RDI; GR64:%vreg3
	Success: %vreg2 -> %vreg3
	Result = %vreg3 [16r,224r:0)  0@16r
64B	%vreg11<def> = COPY %vreg10; GR64:%vreg11,%vreg10
	Considering merging to GR64 with %vreg10 in %vreg11
		RHS = %vreg10 [48r,64r:0)  0@48r
		LHS = %vreg11 [64r,112r:0)  0@64r
		merge %vreg11:0@64r into %vreg10:0@48r --> @48r
		erased:	64r	%vreg11<def> = COPY %vreg10; GR64:%vreg11,%vreg10
		updated: 48B	%vreg11<def> = MOV64ri <ga:@handle_compress>; GR64:%vreg11
	Success: %vreg10 -> %vreg11
	Result = %vreg11 [48r,112r:0)  0@48r
304B	%vreg6<def> = COPY %vreg8; GR64:%vreg6,%vreg8
	Considering merging to GR64 with %vreg8 in %vreg6
		RHS = %vreg8 [288r,304r:0)  0@288r
		LHS = %vreg6 [304r,320r:0)  0@304r
		merge %vreg6:0@304r into %vreg8:0@288r --> @288r
		erased:	304r	%vreg6<def> = COPY %vreg8; GR64:%vreg6,%vreg8
		updated: 288B	%vreg6<def> = MOV64rm %vreg9, 1, %noreg, 48, %noreg; mem:LD8[%state] GR64:%vreg6,%vreg9
	Success: %vreg8 -> %vreg6
	Result = %vreg6 [288r,320r:0)  0@288r
3488B	%RDI<def> = COPY %vreg130; GR64:%vreg130
	Considering merging %vreg130 with %RDI
	Can only merge into reserved registers.
3600B	%AL<def> = COPY %vreg135:sub_8bit; GR32:%vreg135
	Considering merging %vreg135 with %EAX
	Can only merge into reserved registers.
112B	%RDI<def> = COPY %vreg11; GR64:%vreg11
	Considering merging %vreg11 with %RDI
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
DIL [0B,16r:0)[112r,144r:10)[448r,464r:9)[944r,960r:8)[1184r,1200r:7)[1472r,1488r:6)[1808r,1824r:5)[2176r,2192r:2)[2416r,2464r:3)[2752r,2784r:4)[3488r,3520r:1)  0@0B-phi 1@3488r 2@2176r 3@2416r 4@2752r 5@1808r 6@1472r 7@1184r 8@944r 9@448r 10@112r
%vreg3 [16r,224r:0)  0@16r
%vreg6 [288r,320r:0)  0@288r
%vreg9 [272r,288r:0)  0@272r
%vreg11 [48r,112r:0)  0@48r
%vreg12 [80r,128r:0)  0@80r
%vreg15 [352r,368r:0)  0@352r
%vreg19 [688r,704r:0)  0@688r
%vreg21 [672r,704r:0)  0@672r
%vreg22 [656r,672r:0)  0@656r
%vreg28 [576r,608r:0)[608r,640r:1)  0@576r 1@608r
%vreg32 [560r,608r:0)  0@560r
%vreg34 [496r,560r:0)  0@496r
%vreg35 [416r,448r:0)  0@416r
%vreg38 [784r,800r:0)  0@784r
%vreg41 [848r,864r:0)  0@848r
%vreg44 [1056r,1072r:0)  0@1056r
%vreg46 [992r,1056r:0)  0@992r
%vreg47 [912r,944r:0)  0@912r
%vreg50 [1312r,1328r:0)  0@1312r
%vreg52 [1280r,1296r:0)  0@1280r
%vreg54 [1152r,1184r:0)  0@1152r
%vreg57 [1376r,1392r:0)  0@1376r
%vreg60 [1584r,1600r:0)  0@1584r
%vreg62 [1520r,1584r:0)  0@1520r
%vreg63 [1440r,1472r:0)  0@1440r
%vreg66 [1712r,1728r:0)  0@1712r
%vreg69 [2016r,2032r:0)  0@2016r
%vreg75 [1936r,1968r:0)[1968r,2000r:1)  0@1936r 1@1968r
%vreg79 [1920r,1968r:0)  0@1920r
%vreg81 [1856r,1920r:0)  0@1856r
%vreg82 [1776r,1808r:0)  0@1776r
%vreg85 [2080r,2096r:0)  0@2080r
%vreg89 [2640r,2656r:0)  0@2640r
%vreg91 [2624r,2656r:0)  0@2624r
%vreg92 [2608r,2624r:0)  0@2608r
%vreg96 [2944r,2960r:0)  0@2944r
%vreg97 [2928r,2944r:0)  0@2928r
%vreg99 [2864r,2880r:0)  0@2864r
%vreg102 [2720r,2752r:0)  0@2720r
%vreg104 [2544r,2560r:0)  0@2544r
%vreg107 [2432r,2448r:0)  0@2432r
%vreg111 [2320r,2352r:0)[2352r,2368r:1)  0@2320r 1@2352r
%vreg112 [2368r,2432r:0)  0@2368r
%vreg116 [2288r,2304r:0)  0@2288r
%vreg117 [2272r,2416r:0)  0@2272r
%vreg119 [2144r,2176r:0)  0@2144r
%vreg123 [3184r,3200r:0)  0@3184r
%vreg127 [3264r,3280r:0)  0@3264r
%vreg130 [3360r,3488r:0)  0@3360r
%vreg131 [3456r,3504r:0)  0@3456r
%vreg135 [3424r,3600r:0)  0@3424r
%vreg136 [3168r,3248B:0)[3296r,3328B:1)[3328B,3408r:2)[3408r,3424r:3)  0@3168r 1@3296r 2@3328B-phi 3@3408r
RegMasks: 144r 464r 960r 1200r 1488r 1824r 2192r 2464r 2784r 3520r
********** MACHINEINSTRS **********
# Machine code for function handle_compress: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=8, align=8, at location [SP+8]
  fi#1: size=1, align=1, at location [SP+8]
  fi#2: size=1, align=1, at location [SP+8]
  fi#3: size=8, align=8, at location [SP+8]
Function Live Ins: %RDI in %vreg2

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI
16B		%vreg3<def> = COPY %RDI; GR64:%vreg3
48B		%vreg11<def> = MOV64ri <ga:@handle_compress>; GR64:%vreg11
80B		%vreg12<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg12
96B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
112B		%RDI<def> = COPY %vreg11; GR64:%vreg11
128B		%RSI<def> = COPY %vreg12; GR64:%vreg12
144B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
160B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
192B		STACKMAP 0, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, %vreg3, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3] LD8[FixedStack0] GR64:%vreg3
208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg3; mem:ST8[%strm.addr] GR64:%vreg3
240B		MOV8mi <fi#1>, 1, %noreg, 0, %noreg, 0; mem:ST1[%progress_in]
256B		MOV8mi <fi#2>, 1, %noreg, 0, %noreg, 0; mem:ST1[%progress_out]
272B		%vreg9<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg9
288B		%vreg6<def> = MOV64rm %vreg9, 1, %noreg, 48, %noreg; mem:LD8[%state] GR64:%vreg6,%vreg9
320B		MOV64mr <fi#3>, 1, %noreg, 0, %noreg, %vreg6; mem:ST8[%s] GR64:%vreg6
	    Successors according to CFG: BB#1

336B	BB#1: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#0 BB#24
352B		%vreg15<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg15
368B		CMP32mi8 %vreg15, 1, %noreg, 12, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%state1] GR64:%vreg15
384B		JNE_1 <BB#13>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#13 BB#2

400B	BB#2: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#1
416B		%vreg35<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg35
432B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
448B		%RDI<def> = COPY %vreg35; GR64:%vreg35
464B		CALL64pcrel32 <ga:@copy_output_until_stop>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %AL<imp-def>
480B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
496B		%vreg34<def> = COPY %AL<kill>; GR8:%vreg34
512B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
528B		STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
544B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
560B		%vreg32<def> = MOVZX32rr8 %vreg34; GR32:%vreg32 GR8:%vreg34
576B		%vreg28<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%progress_out] GR32:%vreg28
608B		%vreg28<def,tied1> = OR32rr %vreg28<tied0>, %vreg32, %EFLAGS<imp-def,dead>; GR32:%vreg28,%vreg32
640B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg28:sub_8bit; mem:ST1[%progress_out] GR32:%vreg28
656B		%vreg22<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg22
672B		%vreg21<def> = MOV32rm %vreg22, 1, %noreg, 120, %noreg; mem:LD4[%state_out_pos] GR32:%vreg21 GR64:%vreg22
688B		%vreg19<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg19
704B		CMP32rm %vreg21, %vreg19, 1, %noreg, 116, %noreg, %EFLAGS<imp-def>; mem:LD4[%numZ] GR32:%vreg21 GR64:%vreg19
720B		JGE_1 <BB#4>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#4 BB#3

736B	BB#3: derived from LLVM BB %if.then.6
	    Predecessors according to CFG: BB#2
752B		JMP_1 <BB#25>
	    Successors according to CFG: BB#25

768B	BB#4: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#2
784B		%vreg38<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg38
800B		CMP32mi8 %vreg38, 1, %noreg, 8, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%mode] GR64:%vreg38
816B		JNE_1 <BB#8>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#8 BB#5

832B	BB#5: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#4
848B		%vreg41<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg41
864B		CMP32mi8 %vreg41, 1, %noreg, 16, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_in_expect] GR64:%vreg41
880B		JNE_1 <BB#8>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#8 BB#6

896B	BB#6: derived from LLVM BB %land.lhs.true.11
	    Predecessors according to CFG: BB#5
912B		%vreg47<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg47
928B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
944B		%RDI<def> = COPY %vreg47; GR64:%vreg47
960B		CALL64pcrel32 <ga:@isempty_RL>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %AL<imp-def>
976B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
992B		%vreg46<def> = COPY %AL<kill>; GR8:%vreg46
1008B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1024B		STACKMAP 2, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
1040B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1056B		%vreg44<def> = MOVZX32rr8 %vreg46; GR32:%vreg44 GR8:%vreg46
1072B		CMP32ri8 %vreg44, 0, %EFLAGS<imp-def>; GR32:%vreg44
1088B		JE_1 <BB#8>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#8 BB#7

1104B	BB#7: derived from LLVM BB %if.then.14
	    Predecessors according to CFG: BB#6
1120B		JMP_1 <BB#25>
	    Successors according to CFG: BB#25

1136B	BB#8: derived from LLVM BB %if.end.15
	    Predecessors according to CFG: BB#4 BB#5 BB#6
1152B		%vreg54<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg54
1168B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1184B		%RDI<def> = COPY %vreg54; GR64:%vreg54
1200B		CALL64pcrel32 <ga:@prepare_new_block>, <regmask>, %RSP<imp-use>, %RDI<imp-use>
1216B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1232B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1248B		STACKMAP 3, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
1264B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1280B		%vreg52<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg52
1296B		MOV32mi %vreg52, 1, %noreg, 12, %noreg, 2; mem:ST4[%state16] GR64:%vreg52
1312B		%vreg50<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg50
1328B		CMP32mi8 %vreg50, 1, %noreg, 8, %noreg, 3, %EFLAGS<imp-def>; mem:LD4[%mode17] GR64:%vreg50
1344B		JNE_1 <BB#12>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#12 BB#9

1360B	BB#9: derived from LLVM BB %land.lhs.true.20
	    Predecessors according to CFG: BB#8
1376B		%vreg57<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg57
1392B		CMP32mi8 %vreg57, 1, %noreg, 16, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_in_expect21] GR64:%vreg57
1408B		JNE_1 <BB#12>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#12 BB#10

1424B	BB#10: derived from LLVM BB %land.lhs.true.24
	    Predecessors according to CFG: BB#9
1440B		%vreg63<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg63
1456B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1472B		%RDI<def> = COPY %vreg63; GR64:%vreg63
1488B		CALL64pcrel32 <ga:@isempty_RL>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %AL<imp-def>
1504B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1520B		%vreg62<def> = COPY %AL<kill>; GR8:%vreg62
1536B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1552B		STACKMAP 4, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
1568B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1584B		%vreg60<def> = MOVZX32rr8 %vreg62; GR32:%vreg60 GR8:%vreg62
1600B		CMP32ri8 %vreg60, 0, %EFLAGS<imp-def>; GR32:%vreg60
1616B		JE_1 <BB#12>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#12 BB#11

1632B	BB#11: derived from LLVM BB %if.then.28
	    Predecessors according to CFG: BB#10
1648B		JMP_1 <BB#25>
	    Successors according to CFG: BB#25

1664B	BB#12: derived from LLVM BB %if.end.29
	    Predecessors according to CFG: BB#8 BB#9 BB#10
1680B		JMP_1 <BB#13>
	    Successors according to CFG: BB#13

1696B	BB#13: derived from LLVM BB %if.end.30
	    Predecessors according to CFG: BB#1 BB#12
1712B		%vreg66<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg66
1728B		CMP32mi8 %vreg66, 1, %noreg, 12, %noreg, 2, %EFLAGS<imp-def>; mem:LD4[%state31] GR64:%vreg66
1744B		JNE_1 <BB#24>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#24 BB#14

1760B	BB#14: derived from LLVM BB %if.then.34
	    Predecessors according to CFG: BB#13
1776B		%vreg82<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg82
1792B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1808B		%RDI<def> = COPY %vreg82; GR64:%vreg82
1824B		CALL64pcrel32 <ga:@copy_input_until_stop>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %AL<imp-def>
1840B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1856B		%vreg81<def> = COPY %AL<kill>; GR8:%vreg81
1872B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1888B		STACKMAP 5, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
1904B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1920B		%vreg79<def> = MOVZX32rr8 %vreg81; GR32:%vreg79 GR8:%vreg81
1936B		%vreg75<def> = MOVZX32rm8 <fi#1>, 1, %noreg, 0, %noreg; mem:LD1[%progress_in] GR32:%vreg75
1968B		%vreg75<def,tied1> = OR32rr %vreg75<tied0>, %vreg79, %EFLAGS<imp-def,dead>; GR32:%vreg75,%vreg79
2000B		MOV8mr <fi#1>, 1, %noreg, 0, %noreg, %vreg75:sub_8bit; mem:ST1[%progress_in] GR32:%vreg75
2016B		%vreg69<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg69
2032B		CMP32mi8 %vreg69, 1, %noreg, 8, %noreg, 2, %EFLAGS<imp-def>; mem:LD4[%mode40] GR64:%vreg69
2048B		JE_1 <BB#17>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#17 BB#15

2064B	BB#15: derived from LLVM BB %land.lhs.true.43
	    Predecessors according to CFG: BB#14
2080B		%vreg85<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg85
2096B		CMP32mi8 %vreg85, 1, %noreg, 16, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_in_expect44] GR64:%vreg85
2112B		JNE_1 <BB#17>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#17 BB#16

2128B	BB#16: derived from LLVM BB %if.then.47
	    Predecessors according to CFG: BB#15
2144B		%vreg119<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg119
2160B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2176B		%RDI<def> = COPY %vreg119; GR64:%vreg119
2192B		CALL64pcrel32 <ga:@flush_RL>, <regmask>, %RSP<imp-use>, %RDI<imp-use>
2208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2224B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2240B		STACKMAP 6, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
2256B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2272B		%vreg117<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg117
2288B		%vreg116<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg116
2304B		CMP32mi8 %vreg116, 1, %noreg, 8, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%mode48] GR64:%vreg116
2320B		%vreg111<def> = SETEr %EFLAGS<imp-use,kill>; GR8:%vreg111
2352B		%vreg111<def,tied1> = AND8ri %vreg111<tied0>, 1, %EFLAGS<imp-def,dead>; GR8:%vreg111
2368B		%vreg112<def> = MOVZX32rr8 %vreg111; GR32:%vreg112 GR8:%vreg111
2400B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2416B		%RDI<def> = COPY %vreg117; GR64:%vreg117
2432B		%vreg107<def> = MOVZX32rr8 %vreg112:sub_8bit; GR32:%vreg107,%vreg112
2448B		%ESI<def> = COPY %vreg107; GR32:%vreg107
2464B		CALL64pcrel32 <ga:@BZ2_compressBlock>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use,kill>
2480B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2496B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2512B		STACKMAP 7, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
2528B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2544B		%vreg104<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg104
2560B		MOV32mi %vreg104, 1, %noreg, 12, %noreg, 1; mem:ST4[%state52] GR64:%vreg104
2576B		JMP_1 <BB#23>
	    Successors according to CFG: BB#23

2592B	BB#17: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#14 BB#15
2608B		%vreg92<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg92
2624B		%vreg91<def> = MOV32rm %vreg92, 1, %noreg, 108, %noreg; mem:LD4[%nblock] GR32:%vreg91 GR64:%vreg92
2640B		%vreg89<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg89
2656B		CMP32rm %vreg91, %vreg89, 1, %noreg, 112, %noreg, %EFLAGS<imp-def>; mem:LD4[%nblockMAX] GR32:%vreg91 GR64:%vreg89
2672B		JL_1 <BB#19>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#19 BB#18

2688B	BB#18: derived from LLVM BB %if.then.55
	    Predecessors according to CFG: BB#17
2720B		%vreg102<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg102
2736B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2752B		%RDI<def> = COPY %vreg102; GR64:%vreg102
2768B		%ESI<def> = MOV32r0 %EFLAGS<imp-def,dead>
2784B		CALL64pcrel32 <ga:@BZ2_compressBlock>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use,kill>
2800B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2816B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2832B		STACKMAP 8, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
2848B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2864B		%vreg99<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg99
2880B		MOV32mi %vreg99, 1, %noreg, 12, %noreg, 1; mem:ST4[%state56] GR64:%vreg99
2896B		JMP_1 <BB#22>
	    Successors according to CFG: BB#22

2912B	BB#19: derived from LLVM BB %if.else.57
	    Predecessors according to CFG: BB#17
2928B		%vreg97<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg97
2944B		%vreg96<def> = MOV64rm %vreg97, 1, %noreg, 0, %noreg; mem:LD8[%strm58] GR64:%vreg96,%vreg97
2960B		CMP32mi8 %vreg96, 1, %noreg, 8, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_in] GR64:%vreg96
2976B		JNE_1 <BB#21>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#21 BB#20

2992B	BB#20: derived from LLVM BB %if.then.61
	    Predecessors according to CFG: BB#19
3008B		JMP_1 <BB#25>
	    Successors according to CFG: BB#25

3024B	BB#21: derived from LLVM BB %if.end.62
	    Predecessors according to CFG: BB#19
3040B		JMP_1 <BB#22>
	    Successors according to CFG: BB#22

3056B	BB#22: derived from LLVM BB %if.end.63
	    Predecessors according to CFG: BB#21 BB#18
3072B		JMP_1 <BB#23>
	    Successors according to CFG: BB#23

3088B	BB#23: derived from LLVM BB %if.end.64
	    Predecessors according to CFG: BB#22 BB#16
3104B		JMP_1 <BB#24>
	    Successors according to CFG: BB#24

3120B	BB#24: derived from LLVM BB %if.end.65
	    Predecessors according to CFG: BB#13 BB#23
3136B		JMP_1 <BB#1>
	    Successors according to CFG: BB#1

3152B	BB#25: derived from LLVM BB %while.end
	    Predecessors according to CFG: BB#20 BB#11 BB#7 BB#3
3168B		%vreg136<def> = MOV8ri 1; GR8:%vreg136
3184B		%vreg123<def> = MOVZX32rm8 <fi#1>, 1, %noreg, 0, %noreg; mem:LD1[%progress_in] GR32:%vreg123
3200B		CMP32ri8 %vreg123, 0, %EFLAGS<imp-def>; GR32:%vreg123
3232B		JNE_1 <BB#27>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#27 BB#26

3248B	BB#26: derived from LLVM BB %lor.rhs
	    Predecessors according to CFG: BB#25
3264B		%vreg127<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%progress_out] GR32:%vreg127
3280B		CMP32ri8 %vreg127, 0, %EFLAGS<imp-def>; GR32:%vreg127
3296B		%vreg136<def> = SETNEr %EFLAGS<imp-use,kill>; GR8:%vreg136
	    Successors according to CFG: BB#27

3328B	BB#27: derived from LLVM BB %lor.end
	    Predecessors according to CFG: BB#25 BB#26
3360B		%vreg130<def> = MOV64ri <ga:@handle_compress>; GR64:%vreg130
3408B		%vreg136<def,tied1> = AND8ri %vreg136<tied0>, 1, %EFLAGS<imp-def,dead>; GR8:%vreg136
3424B		%vreg135<def> = MOVZX32rr8 %vreg136; GR32:%vreg135 GR8:%vreg136
3456B		%vreg131<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg131
3472B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3488B		%RDI<def> = COPY %vreg130; GR64:%vreg130
3504B		%RSI<def> = COPY %vreg131; GR64:%vreg131
3520B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
3536B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3552B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3568B		STACKMAP 9, 0, %vreg135:sub_8bit, ...; GR32:%vreg135
3584B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3600B		%AL<def> = COPY %vreg135:sub_8bit; GR32:%vreg135
3616B		RETQ %AL<imp-use,kill>

# End machine code for function handle_compress.

AllocationOrder(SEGMENT_REG) = [ ]
handleMove 2416B -> 2440B: %RDI<def> = COPY %vreg117; GR64:%vreg117
     DIL:	[0B,16r:0)[112r,144r:10)[448r,464r:9)[944r,960r:8)[1184r,1200r:7)[1472r,1488r:6)[1808r,1824r:5)[2176r,2192r:2)[2416r,2464r:3)[2752r,2784r:4)[3488r,3520r:1)  0@0B-phi 1@3488r 2@2176r 3@2416r 4@2752r 5@1808r 6@1472r 7@1184r 8@944r 9@448r 10@112r
        -->	[0B,16r:0)[112r,144r:10)[448r,464r:9)[944r,960r:8)[1184r,1200r:7)[1472r,1488r:6)[1808r,1824r:5)[2176r,2192r:2)[2440r,2464r:3)[2752r,2784r:4)[3488r,3520r:1)  0@0B-phi 1@3488r 2@2176r 3@2440r 4@2752r 5@1808r 6@1472r 7@1184r 8@944r 9@448r 10@112r
     %vreg117:	[2272r,2416r:0)  0@2272r
        -->	[2272r,2440r:0)  0@2272r
handleMove 2272B -> 2312B: %vreg117<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg117
     %vreg117:	[2272r,2440r:0)  0@2272r
        -->	[2312r,2440r:0)  0@2312r
handleMove 2752B -> 2776B: %RDI<def> = COPY %vreg102; GR64:%vreg102
     DIL:	[0B,16r:0)[112r,144r:10)[448r,464r:9)[944r,960r:8)[1184r,1200r:7)[1472r,1488r:6)[1808r,1824r:5)[2176r,2192r:2)[2440r,2464r:3)[2752r,2784r:4)[3488r,3520r:1)  0@0B-phi 1@3488r 2@2176r 3@2440r 4@2752r 5@1808r 6@1472r 7@1184r 8@944r 9@448r 10@112r
        -->	[0B,16r:0)[112r,144r:10)[448r,464r:9)[944r,960r:8)[1184r,1200r:7)[1472r,1488r:6)[1808r,1824r:5)[2176r,2192r:2)[2440r,2464r:3)[2776r,2784r:4)[3488r,3520r:1)  0@0B-phi 1@3488r 2@2176r 3@2440r 4@2776r 5@1808r 6@1472r 7@1184r 8@944r 9@448r 10@112r
     %vreg102:	[2720r,2752r:0)  0@2720r
        -->	[2720r,2776r:0)  0@2720r
********** GREEDY REGISTER ALLOCATION **********
********** Function: handle_compress
********** INTERVALS **********
DIL [0B,16r:0)[112r,144r:10)[448r,464r:9)[944r,960r:8)[1184r,1200r:7)[1472r,1488r:6)[1808r,1824r:5)[2176r,2192r:2)[2440r,2464r:3)[2776r,2784r:4)[3488r,3520r:1)  0@0B-phi 1@3488r 2@2176r 3@2440r 4@2776r 5@1808r 6@1472r 7@1184r 8@944r 9@448r 10@112r
%vreg3 [16r,224r:0)  0@16r
%vreg6 [288r,320r:0)  0@288r
%vreg9 [272r,288r:0)  0@272r
%vreg11 [48r,112r:0)  0@48r
%vreg12 [80r,128r:0)  0@80r
%vreg15 [352r,368r:0)  0@352r
%vreg19 [688r,704r:0)  0@688r
%vreg21 [672r,704r:0)  0@672r
%vreg22 [656r,672r:0)  0@656r
%vreg28 [576r,608r:0)[608r,640r:1)  0@576r 1@608r
%vreg32 [560r,608r:0)  0@560r
%vreg34 [496r,560r:0)  0@496r
%vreg35 [416r,448r:0)  0@416r
%vreg38 [784r,800r:0)  0@784r
%vreg41 [848r,864r:0)  0@848r
%vreg44 [1056r,1072r:0)  0@1056r
%vreg46 [992r,1056r:0)  0@992r
%vreg47 [912r,944r:0)  0@912r
%vreg50 [1312r,1328r:0)  0@1312r
%vreg52 [1280r,1296r:0)  0@1280r
%vreg54 [1152r,1184r:0)  0@1152r
%vreg57 [1376r,1392r:0)  0@1376r
%vreg60 [1584r,1600r:0)  0@1584r
%vreg62 [1520r,1584r:0)  0@1520r
%vreg63 [1440r,1472r:0)  0@1440r
%vreg66 [1712r,1728r:0)  0@1712r
%vreg69 [2016r,2032r:0)  0@2016r
%vreg75 [1936r,1968r:0)[1968r,2000r:1)  0@1936r 1@1968r
%vreg79 [1920r,1968r:0)  0@1920r
%vreg81 [1856r,1920r:0)  0@1856r
%vreg82 [1776r,1808r:0)  0@1776r
%vreg85 [2080r,2096r:0)  0@2080r
%vreg89 [2640r,2656r:0)  0@2640r
%vreg91 [2624r,2656r:0)  0@2624r
%vreg92 [2608r,2624r:0)  0@2608r
%vreg96 [2944r,2960r:0)  0@2944r
%vreg97 [2928r,2944r:0)  0@2928r
%vreg99 [2864r,2880r:0)  0@2864r
%vreg102 [2720r,2776r:0)  0@2720r
%vreg104 [2544r,2560r:0)  0@2544r
%vreg107 [2432r,2448r:0)  0@2432r
%vreg111 [2320r,2352r:0)[2352r,2368r:1)  0@2320r 1@2352r
%vreg112 [2368r,2432r:0)  0@2368r
%vreg116 [2288r,2304r:0)  0@2288r
%vreg117 [2312r,2440r:0)  0@2312r
%vreg119 [2144r,2176r:0)  0@2144r
%vreg123 [3184r,3200r:0)  0@3184r
%vreg127 [3264r,3280r:0)  0@3264r
%vreg130 [3360r,3488r:0)  0@3360r
%vreg131 [3456r,3504r:0)  0@3456r
%vreg135 [3424r,3600r:0)  0@3424r
%vreg136 [3168r,3248B:0)[3296r,3328B:1)[3328B,3408r:2)[3408r,3424r:3)  0@3168r 1@3296r 2@3328B-phi 3@3408r
RegMasks: 144r 464r 960r 1200r 1488r 1824r 2192r 2464r 2784r 3520r
********** MACHINEINSTRS **********
# Machine code for function handle_compress: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=8, align=8, at location [SP+8]
  fi#1: size=1, align=1, at location [SP+8]
  fi#2: size=1, align=1, at location [SP+8]
  fi#3: size=8, align=8, at location [SP+8]
Function Live Ins: %RDI in %vreg2

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI
16B		%vreg3<def> = COPY %RDI; GR64:%vreg3
48B		%vreg11<def> = MOV64ri <ga:@handle_compress>; GR64:%vreg11
80B		%vreg12<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg12
96B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
112B		%RDI<def> = COPY %vreg11; GR64:%vreg11
128B		%RSI<def> = COPY %vreg12; GR64:%vreg12
144B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
160B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
192B		STACKMAP 0, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, %vreg3, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3] LD8[FixedStack0] GR64:%vreg3
208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg3; mem:ST8[%strm.addr] GR64:%vreg3
240B		MOV8mi <fi#1>, 1, %noreg, 0, %noreg, 0; mem:ST1[%progress_in]
256B		MOV8mi <fi#2>, 1, %noreg, 0, %noreg, 0; mem:ST1[%progress_out]
272B		%vreg9<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg9
288B		%vreg6<def> = MOV64rm %vreg9, 1, %noreg, 48, %noreg; mem:LD8[%state] GR64:%vreg6,%vreg9
320B		MOV64mr <fi#3>, 1, %noreg, 0, %noreg, %vreg6; mem:ST8[%s] GR64:%vreg6
	    Successors according to CFG: BB#1

336B	BB#1: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#0 BB#24
352B		%vreg15<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg15
368B		CMP32mi8 %vreg15, 1, %noreg, 12, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%state1] GR64:%vreg15
384B		JNE_1 <BB#13>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#13 BB#2

400B	BB#2: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#1
416B		%vreg35<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg35
432B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
448B		%RDI<def> = COPY %vreg35; GR64:%vreg35
464B		CALL64pcrel32 <ga:@copy_output_until_stop>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %AL<imp-def>
480B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
496B		%vreg34<def> = COPY %AL<kill>; GR8:%vreg34
512B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
528B		STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
544B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
560B		%vreg32<def> = MOVZX32rr8 %vreg34; GR32:%vreg32 GR8:%vreg34
576B		%vreg28<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%progress_out] GR32:%vreg28
608B		%vreg28<def,tied1> = OR32rr %vreg28<tied0>, %vreg32, %EFLAGS<imp-def,dead>; GR32:%vreg28,%vreg32
640B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg28:sub_8bit; mem:ST1[%progress_out] GR32:%vreg28
656B		%vreg22<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg22
672B		%vreg21<def> = MOV32rm %vreg22, 1, %noreg, 120, %noreg; mem:LD4[%state_out_pos] GR32:%vreg21 GR64:%vreg22
688B		%vreg19<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg19
704B		CMP32rm %vreg21, %vreg19, 1, %noreg, 116, %noreg, %EFLAGS<imp-def>; mem:LD4[%numZ] GR32:%vreg21 GR64:%vreg19
720B		JGE_1 <BB#4>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#4 BB#3

736B	BB#3: derived from LLVM BB %if.then.6
	    Predecessors according to CFG: BB#2
752B		JMP_1 <BB#25>
	    Successors according to CFG: BB#25

768B	BB#4: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#2
784B		%vreg38<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg38
800B		CMP32mi8 %vreg38, 1, %noreg, 8, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%mode] GR64:%vreg38
816B		JNE_1 <BB#8>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#8 BB#5

832B	BB#5: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#4
848B		%vreg41<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg41
864B		CMP32mi8 %vreg41, 1, %noreg, 16, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_in_expect] GR64:%vreg41
880B		JNE_1 <BB#8>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#8 BB#6

896B	BB#6: derived from LLVM BB %land.lhs.true.11
	    Predecessors according to CFG: BB#5
912B		%vreg47<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg47
928B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
944B		%RDI<def> = COPY %vreg47; GR64:%vreg47
960B		CALL64pcrel32 <ga:@isempty_RL>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %AL<imp-def>
976B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
992B		%vreg46<def> = COPY %AL<kill>; GR8:%vreg46
1008B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1024B		STACKMAP 2, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
1040B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1056B		%vreg44<def> = MOVZX32rr8 %vreg46; GR32:%vreg44 GR8:%vreg46
1072B		CMP32ri8 %vreg44, 0, %EFLAGS<imp-def>; GR32:%vreg44
1088B		JE_1 <BB#8>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#8 BB#7

1104B	BB#7: derived from LLVM BB %if.then.14
	    Predecessors according to CFG: BB#6
1120B		JMP_1 <BB#25>
	    Successors according to CFG: BB#25

1136B	BB#8: derived from LLVM BB %if.end.15
	    Predecessors according to CFG: BB#4 BB#5 BB#6
1152B		%vreg54<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg54
1168B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1184B		%RDI<def> = COPY %vreg54; GR64:%vreg54
1200B		CALL64pcrel32 <ga:@prepare_new_block>, <regmask>, %RSP<imp-use>, %RDI<imp-use>
1216B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1232B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1248B		STACKMAP 3, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
1264B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1280B		%vreg52<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg52
1296B		MOV32mi %vreg52, 1, %noreg, 12, %noreg, 2; mem:ST4[%state16] GR64:%vreg52
1312B		%vreg50<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg50
1328B		CMP32mi8 %vreg50, 1, %noreg, 8, %noreg, 3, %EFLAGS<imp-def>; mem:LD4[%mode17] GR64:%vreg50
1344B		JNE_1 <BB#12>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#12 BB#9

1360B	BB#9: derived from LLVM BB %land.lhs.true.20
	    Predecessors according to CFG: BB#8
1376B		%vreg57<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg57
1392B		CMP32mi8 %vreg57, 1, %noreg, 16, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_in_expect21] GR64:%vreg57
1408B		JNE_1 <BB#12>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#12 BB#10

1424B	BB#10: derived from LLVM BB %land.lhs.true.24
	    Predecessors according to CFG: BB#9
1440B		%vreg63<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg63
1456B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1472B		%RDI<def> = COPY %vreg63; GR64:%vreg63
1488B		CALL64pcrel32 <ga:@isempty_RL>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %AL<imp-def>
1504B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1520B		%vreg62<def> = COPY %AL<kill>; GR8:%vreg62
1536B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1552B		STACKMAP 4, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
1568B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1584B		%vreg60<def> = MOVZX32rr8 %vreg62; GR32:%vreg60 GR8:%vreg62
1600B		CMP32ri8 %vreg60, 0, %EFLAGS<imp-def>; GR32:%vreg60
1616B		JE_1 <BB#12>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#12 BB#11

1632B	BB#11: derived from LLVM BB %if.then.28
	    Predecessors according to CFG: BB#10
1648B		JMP_1 <BB#25>
	    Successors according to CFG: BB#25

1664B	BB#12: derived from LLVM BB %if.end.29
	    Predecessors according to CFG: BB#8 BB#9 BB#10
1680B		JMP_1 <BB#13>
	    Successors according to CFG: BB#13

1696B	BB#13: derived from LLVM BB %if.end.30
	    Predecessors according to CFG: BB#1 BB#12
1712B		%vreg66<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg66
1728B		CMP32mi8 %vreg66, 1, %noreg, 12, %noreg, 2, %EFLAGS<imp-def>; mem:LD4[%state31] GR64:%vreg66
1744B		JNE_1 <BB#24>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#24 BB#14

1760B	BB#14: derived from LLVM BB %if.then.34
	    Predecessors according to CFG: BB#13
1776B		%vreg82<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg82
1792B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1808B		%RDI<def> = COPY %vreg82; GR64:%vreg82
1824B		CALL64pcrel32 <ga:@copy_input_until_stop>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %AL<imp-def>
1840B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1856B		%vreg81<def> = COPY %AL<kill>; GR8:%vreg81
1872B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1888B		STACKMAP 5, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
1904B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1920B		%vreg79<def> = MOVZX32rr8 %vreg81; GR32:%vreg79 GR8:%vreg81
1936B		%vreg75<def> = MOVZX32rm8 <fi#1>, 1, %noreg, 0, %noreg; mem:LD1[%progress_in] GR32:%vreg75
1968B		%vreg75<def,tied1> = OR32rr %vreg75<tied0>, %vreg79, %EFLAGS<imp-def,dead>; GR32:%vreg75,%vreg79
2000B		MOV8mr <fi#1>, 1, %noreg, 0, %noreg, %vreg75:sub_8bit; mem:ST1[%progress_in] GR32:%vreg75
2016B		%vreg69<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg69
2032B		CMP32mi8 %vreg69, 1, %noreg, 8, %noreg, 2, %EFLAGS<imp-def>; mem:LD4[%mode40] GR64:%vreg69
2048B		JE_1 <BB#17>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#17 BB#15

2064B	BB#15: derived from LLVM BB %land.lhs.true.43
	    Predecessors according to CFG: BB#14
2080B		%vreg85<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg85
2096B		CMP32mi8 %vreg85, 1, %noreg, 16, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_in_expect44] GR64:%vreg85
2112B		JNE_1 <BB#17>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#17 BB#16

2128B	BB#16: derived from LLVM BB %if.then.47
	    Predecessors according to CFG: BB#15
2144B		%vreg119<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg119
2160B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2176B		%RDI<def> = COPY %vreg119; GR64:%vreg119
2192B		CALL64pcrel32 <ga:@flush_RL>, <regmask>, %RSP<imp-use>, %RDI<imp-use>
2208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2224B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2240B		STACKMAP 6, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
2256B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2288B		%vreg116<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg116
2304B		CMP32mi8 %vreg116, 1, %noreg, 8, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%mode48] GR64:%vreg116
2312B		%vreg117<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg117
2320B		%vreg111<def> = SETEr %EFLAGS<imp-use,kill>; GR8:%vreg111
2352B		%vreg111<def,tied1> = AND8ri %vreg111<tied0>, 1, %EFLAGS<imp-def,dead>; GR8:%vreg111
2368B		%vreg112<def> = MOVZX32rr8 %vreg111; GR32:%vreg112 GR8:%vreg111
2400B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2432B		%vreg107<def> = MOVZX32rr8 %vreg112:sub_8bit; GR32:%vreg107,%vreg112
2440B		%RDI<def> = COPY %vreg117; GR64:%vreg117
2448B		%ESI<def> = COPY %vreg107; GR32:%vreg107
2464B		CALL64pcrel32 <ga:@BZ2_compressBlock>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use,kill>
2480B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2496B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2512B		STACKMAP 7, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
2528B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2544B		%vreg104<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg104
2560B		MOV32mi %vreg104, 1, %noreg, 12, %noreg, 1; mem:ST4[%state52] GR64:%vreg104
2576B		JMP_1 <BB#23>
	    Successors according to CFG: BB#23

2592B	BB#17: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#14 BB#15
2608B		%vreg92<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg92
2624B		%vreg91<def> = MOV32rm %vreg92, 1, %noreg, 108, %noreg; mem:LD4[%nblock] GR32:%vreg91 GR64:%vreg92
2640B		%vreg89<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg89
2656B		CMP32rm %vreg91, %vreg89, 1, %noreg, 112, %noreg, %EFLAGS<imp-def>; mem:LD4[%nblockMAX] GR32:%vreg91 GR64:%vreg89
2672B		JL_1 <BB#19>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#19 BB#18

2688B	BB#18: derived from LLVM BB %if.then.55
	    Predecessors according to CFG: BB#17
2720B		%vreg102<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg102
2736B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2768B		%ESI<def> = MOV32r0 %EFLAGS<imp-def,dead>
2776B		%RDI<def> = COPY %vreg102; GR64:%vreg102
2784B		CALL64pcrel32 <ga:@BZ2_compressBlock>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use,kill>
2800B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2816B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2832B		STACKMAP 8, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
2848B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2864B		%vreg99<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg99
2880B		MOV32mi %vreg99, 1, %noreg, 12, %noreg, 1; mem:ST4[%state56] GR64:%vreg99
2896B		JMP_1 <BB#22>
	    Successors according to CFG: BB#22

2912B	BB#19: derived from LLVM BB %if.else.57
	    Predecessors according to CFG: BB#17
2928B		%vreg97<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg97
2944B		%vreg96<def> = MOV64rm %vreg97, 1, %noreg, 0, %noreg; mem:LD8[%strm58] GR64:%vreg96,%vreg97
2960B		CMP32mi8 %vreg96, 1, %noreg, 8, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_in] GR64:%vreg96
2976B		JNE_1 <BB#21>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#21 BB#20

2992B	BB#20: derived from LLVM BB %if.then.61
	    Predecessors according to CFG: BB#19
3008B		JMP_1 <BB#25>
	    Successors according to CFG: BB#25

3024B	BB#21: derived from LLVM BB %if.end.62
	    Predecessors according to CFG: BB#19
3040B		JMP_1 <BB#22>
	    Successors according to CFG: BB#22

3056B	BB#22: derived from LLVM BB %if.end.63
	    Predecessors according to CFG: BB#21 BB#18
3072B		JMP_1 <BB#23>
	    Successors according to CFG: BB#23

3088B	BB#23: derived from LLVM BB %if.end.64
	    Predecessors according to CFG: BB#22 BB#16
3104B		JMP_1 <BB#24>
	    Successors according to CFG: BB#24

3120B	BB#24: derived from LLVM BB %if.end.65
	    Predecessors according to CFG: BB#13 BB#23
3136B		JMP_1 <BB#1>
	    Successors according to CFG: BB#1

3152B	BB#25: derived from LLVM BB %while.end
	    Predecessors according to CFG: BB#20 BB#11 BB#7 BB#3
3168B		%vreg136<def> = MOV8ri 1; GR8:%vreg136
3184B		%vreg123<def> = MOVZX32rm8 <fi#1>, 1, %noreg, 0, %noreg; mem:LD1[%progress_in] GR32:%vreg123
3200B		CMP32ri8 %vreg123, 0, %EFLAGS<imp-def>; GR32:%vreg123
3232B		JNE_1 <BB#27>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#27 BB#26

3248B	BB#26: derived from LLVM BB %lor.rhs
	    Predecessors according to CFG: BB#25
3264B		%vreg127<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%progress_out] GR32:%vreg127
3280B		CMP32ri8 %vreg127, 0, %EFLAGS<imp-def>; GR32:%vreg127
3296B		%vreg136<def> = SETNEr %EFLAGS<imp-use,kill>; GR8:%vreg136
	    Successors according to CFG: BB#27

3328B	BB#27: derived from LLVM BB %lor.end
	    Predecessors according to CFG: BB#25 BB#26
3360B		%vreg130<def> = MOV64ri <ga:@handle_compress>; GR64:%vreg130
3408B		%vreg136<def,tied1> = AND8ri %vreg136<tied0>, 1, %EFLAGS<imp-def,dead>; GR8:%vreg136
3424B		%vreg135<def> = MOVZX32rr8 %vreg136; GR32:%vreg135 GR8:%vreg136
3456B		%vreg131<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg131
3472B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3488B		%RDI<def> = COPY %vreg130; GR64:%vreg130
3504B		%RSI<def> = COPY %vreg131; GR64:%vreg131
3520B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
3536B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3552B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3568B		STACKMAP 9, 0, %vreg135:sub_8bit, ...; GR32:%vreg135
3584B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3600B		%AL<def> = COPY %vreg135:sub_8bit; GR32:%vreg135
3616B		RETQ %AL<imp-use,kill>

# End machine code for function handle_compress.


selectOrSplit GR64:%vreg3 [16r,224r:0)  0@16r w=4.983552e-03
hints: %RDI
missed hint %RDI
assigning %vreg3 to %RBX: BH [16r,224r:0)  0@16r BL [16r,224r:0)  0@16r

selectOrSplit GR64:%vreg11 [48r,112r:0)  0@48r w=2.176724e-03
hints: %RDI
assigning %vreg11 to %RDI: DIL [48r,112r:0)  0@48r

selectOrSplit GR64:%vreg12 [80r,128r:0)  0@80r w=4.508928e-03
hints: %RSI
assigning %vreg12 to %RSI: SIL [80r,128r:0)  0@80r

selectOrSplit GR64:%vreg35 [416r,448r:0)  0@416r w=6.263167e-03
hints: %RDI
assigning %vreg35 to %RDI: DIL [416r,448r:0)  0@416r

selectOrSplit GR8:%vreg34 [496r,560r:0)  0@496r w=5.831224e-03
hints: %AL
assigning %vreg34 to %AL: AL [496r,560r:0)  0@496r

selectOrSplit GR64:%vreg47 [912r,944r:0)  0@912r w=7.721712e-04
hints: %RDI
assigning %vreg47 to %RDI: DIL [912r,944r:0)  0@912r

selectOrSplit GR8:%vreg46 [992r,1056r:0)  0@992r w=7.189180e-04
hints: %AL
assigning %vreg46 to %AL: AL [992r,1056r:0)  0@992r

selectOrSplit GR64:%vreg54 [1152r,1184r:0)  0@1152r w=2.702599e-03
hints: %RDI
assigning %vreg54 to %RDI: DIL [1152r,1184r:0)  0@1152r

selectOrSplit GR64:%vreg63 [1440r,1472r:0)  0@1440r w=6.863744e-04
hints: %RDI
assigning %vreg63 to %RDI: DIL [1440r,1472r:0)  0@1440r

selectOrSplit GR8:%vreg62 [1520r,1584r:0)  0@1520r w=6.390382e-04
hints: %AL
assigning %vreg62 to %AL: AL [1520r,1584r:0)  0@1520r

selectOrSplit GR64:%vreg82 [1776r,1808r:0)  0@1776r w=4.332738e-03
hints: %RDI
assigning %vreg82 to %RDI: DIL [1776r,1808r:0)  0@1776r

selectOrSplit GR8:%vreg81 [1856r,1920r:0)  0@1856r w=4.033929e-03
hints: %AL
assigning %vreg81 to %AL: AL [1856r,1920r:0)  0@1856r

selectOrSplit GR64:%vreg119 [2144r,2176r:0)  0@2144r w=1.072460e-03
hints: %RDI
assigning %vreg119 to %RDI: DIL [2144r,2176r:0)  0@2144r

selectOrSplit GR64:%vreg117 [2312r,2440r:0)  0@2312r w=8.774673e-04
hints: %RDI
assigning %vreg117 to %RDI: DIL [2312r,2440r:0)  0@2312r

selectOrSplit GR32:%vreg107 [2432r,2448r:0)  0@2432r w=1.113708e-03
hints: %ESI
assigning %vreg107 to %ESI: SIL [2432r,2448r:0)  0@2432r

selectOrSplit GR64:%vreg102 [2720r,2776r:0)  0@2720r w=1.503702e-03
hints: %RDI
assigning %vreg102 to %RDI: DIL [2720r,2776r:0)  0@2720r

selectOrSplit GR64:%vreg130 [3360r,3488r:0)  0@3360r w=1.912879e-03
hints: %RDI
assigning %vreg130 to %RDI: DIL [3360r,3488r:0)  0@3360r

selectOrSplit GR32:%vreg135 [3424r,3600r:0)  0@3424r w=5.260416e-03
hints: %EAX
missed hint %EAX
assigning %vreg135 to %EBX: BH [3424r,3600r:0)  0@3424r BL [3424r,3600r:0)  0@3424r

selectOrSplit GR64:%vreg131 [3456r,3504r:0)  0@3456r w=4.508928e-03
hints: %RSI
assigning %vreg131 to %RSI: SIL [3456r,3504r:0)  0@3456r

selectOrSplit GR8:%vreg136 [3168r,3248B:0)[3296r,3328B:1)[3328B,3408r:2)[3408r,3424r:3)  0@3168r 1@3296r 2@3328B-phi 3@3408r w=7.418173e-03
assigning %vreg136 to %AL: AL [3168r,3248B:0)[3296r,3328B:1)[3328B,3408r:2)[3408r,3424r:3)  0@3168r 1@3296r 2@3328B-phi 3@3408r

selectOrSplit GR64:%vreg9 [272r,288r:0)  0@272r w=inf
assigning %vreg9 to %RAX: AH [272r,288r:0)  0@272r AL [272r,288r:0)  0@272r

selectOrSplit GR64:%vreg6 [288r,320r:0)  0@288r w=inf
assigning %vreg6 to %RAX: AH [288r,320r:0)  0@288r AL [288r,320r:0)  0@288r

selectOrSplit GR64:%vreg15 [352r,368r:0)  0@352r w=inf
assigning %vreg15 to %RAX: AH [352r,368r:0)  0@352r AL [352r,368r:0)  0@352r

selectOrSplit GR32:%vreg32 [560r,608r:0)  0@560r w=5.979686e-03
assigning %vreg32 to %EAX: AH [560r,608r:0)  0@560r AL [560r,608r:0)  0@560r

selectOrSplit GR32:%vreg28 [576r,608r:0)[608r,640r:1)  0@576r 1@608r w=inf
assigning %vreg28 to %ECX: CH [576r,608r:0)[608r,640r:1)  0@576r 1@608r CL [576r,608r:0)[608r,640r:1)  0@576r 1@608r

selectOrSplit GR64:%vreg22 [656r,672r:0)  0@656r w=inf
assigning %vreg22 to %RAX: AH [656r,672r:0)  0@656r AL [656r,672r:0)  0@656r

selectOrSplit GR32:%vreg21 [672r,704r:0)  0@672r w=6.201155e-03
assigning %vreg21 to %EAX: AH [672r,704r:0)  0@672r AL [672r,704r:0)  0@672r

selectOrSplit GR64:%vreg19 [688r,704r:0)  0@688r w=inf
assigning %vreg19 to %RCX: CH [688r,704r:0)  0@688r CL [688r,704r:0)  0@688r

selectOrSplit GR64:%vreg38 [784r,800r:0)  0@784r w=inf
assigning %vreg38 to %RAX: AH [784r,800r:0)  0@784r AL [784r,800r:0)  0@784r

selectOrSplit GR64:%vreg41 [848r,864r:0)  0@848r w=inf
assigning %vreg41 to %RAX: AH [848r,864r:0)  0@848r AL [848r,864r:0)  0@848r

selectOrSplit GR32:%vreg44 [1056r,1072r:0)  0@1056r w=inf
assigning %vreg44 to %EAX: AH [1056r,1072r:0)  0@1056r AL [1056r,1072r:0)  0@1056r

selectOrSplit GR64:%vreg52 [1280r,1296r:0)  0@1280r w=inf
assigning %vreg52 to %RAX: AH [1280r,1296r:0)  0@1280r AL [1280r,1296r:0)  0@1280r

selectOrSplit GR64:%vreg50 [1312r,1328r:0)  0@1312r w=inf
assigning %vreg50 to %RAX: AH [1312r,1328r:0)  0@1312r AL [1312r,1328r:0)  0@1312r

selectOrSplit GR64:%vreg57 [1376r,1392r:0)  0@1376r w=inf
assigning %vreg57 to %RAX: AH [1376r,1392r:0)  0@1376r AL [1376r,1392r:0)  0@1376r

selectOrSplit GR32:%vreg60 [1584r,1600r:0)  0@1584r w=inf
assigning %vreg60 to %EAX: AH [1584r,1600r:0)  0@1584r AL [1584r,1600r:0)  0@1584r

selectOrSplit GR64:%vreg66 [1712r,1728r:0)  0@1712r w=inf
assigning %vreg66 to %RAX: AH [1712r,1728r:0)  0@1712r AL [1712r,1728r:0)  0@1712r

selectOrSplit GR32:%vreg79 [1920r,1968r:0)  0@1920r w=4.136632e-03
assigning %vreg79 to %EAX: AH [1920r,1968r:0)  0@1920r AL [1920r,1968r:0)  0@1920r

selectOrSplit GR32:%vreg75 [1936r,1968r:0)[1968r,2000r:1)  0@1936r 1@1968r w=inf
assigning %vreg75 to %ECX: CH [1936r,1968r:0)[1968r,2000r:1)  0@1936r 1@1968r CL [1936r,1968r:0)[1968r,2000r:1)  0@1936r 1@1968r

selectOrSplit GR64:%vreg69 [2016r,2032r:0)  0@2016r w=inf
assigning %vreg69 to %RAX: AH [2016r,2032r:0)  0@2016r AL [2016r,2032r:0)  0@2016r

selectOrSplit GR64:%vreg85 [2080r,2096r:0)  0@2080r w=inf
assigning %vreg85 to %RAX: AH [2080r,2096r:0)  0@2080r AL [2080r,2096r:0)  0@2080r

selectOrSplit GR64:%vreg116 [2288r,2304r:0)  0@2288r w=inf
assigning %vreg116 to %RAX: AH [2288r,2304r:0)  0@2288r AL [2288r,2304r:0)  0@2288r

selectOrSplit GR8:%vreg111 [2320r,2352r:0)[2352r,2368r:1)  0@2320r 1@2352r w=inf
assigning %vreg111 to %AL: AL [2320r,2352r:0)[2352r,2368r:1)  0@2320r 1@2352r

selectOrSplit GR32:%vreg112 [2368r,2432r:0)  0@2368r w=9.886111e-04
assigning %vreg112 to %EAX: AH [2368r,2432r:0)  0@2368r AL [2368r,2432r:0)  0@2368r

selectOrSplit GR64:%vreg104 [2544r,2560r:0)  0@2544r w=inf
assigning %vreg104 to %RAX: AH [2544r,2560r:0)  0@2544r AL [2544r,2560r:0)  0@2544r

selectOrSplit GR64:%vreg92 [2608r,2624r:0)  0@2608r w=inf
assigning %vreg92 to %RAX: AH [2608r,2624r:0)  0@2608r AL [2608r,2624r:0)  0@2608r

selectOrSplit GR32:%vreg91 [2624r,2656r:0)  0@2624r w=3.185525e-03
assigning %vreg91 to %EAX: AH [2624r,2656r:0)  0@2624r AL [2624r,2656r:0)  0@2624r

selectOrSplit GR64:%vreg89 [2640r,2656r:0)  0@2640r w=inf
assigning %vreg89 to %RCX: CH [2640r,2656r:0)  0@2640r CL [2640r,2656r:0)  0@2640r

selectOrSplit GR64:%vreg99 [2864r,2880r:0)  0@2864r w=inf
assigning %vreg99 to %RAX: AH [2864r,2880r:0)  0@2864r AL [2864r,2880r:0)  0@2864r

selectOrSplit GR64:%vreg97 [2928r,2944r:0)  0@2928r w=inf
assigning %vreg97 to %RAX: AH [2928r,2944r:0)  0@2928r AL [2928r,2944r:0)  0@2928r

selectOrSplit GR64:%vreg96 [2944r,2960r:0)  0@2944r w=inf
assigning %vreg96 to %RAX: AH [2944r,2960r:0)  0@2944r AL [2944r,2960r:0)  0@2944r

selectOrSplit GR32:%vreg123 [3184r,3200r:0)  0@3184r w=inf
assigning %vreg123 to %ECX: CH [3184r,3200r:0)  0@3184r CL [3184r,3200r:0)  0@3184r

selectOrSplit GR32:%vreg127 [3264r,3280r:0)  0@3264r w=inf
assigning %vreg127 to %EAX: AH [3264r,3280r:0)  0@3264r AL [3264r,3280r:0)  0@3264r

********** STACK TRANSFORMATION METADATA **********
********** Function: handle_compress
********** REGISTER MAP **********
[%vreg3 -> %RBX] GR64
[%vreg6 -> %RAX] GR64
[%vreg9 -> %RAX] GR64
[%vreg11 -> %RDI] GR64
[%vreg12 -> %RSI] GR64
[%vreg15 -> %RAX] GR64
[%vreg19 -> %RCX] GR64
[%vreg21 -> %EAX] GR32
[%vreg22 -> %RAX] GR64
[%vreg28 -> %ECX] GR32
[%vreg32 -> %EAX] GR32
[%vreg34 -> %AL] GR8
[%vreg35 -> %RDI] GR64
[%vreg38 -> %RAX] GR64
[%vreg41 -> %RAX] GR64
[%vreg44 -> %EAX] GR32
[%vreg46 -> %AL] GR8
[%vreg47 -> %RDI] GR64
[%vreg50 -> %RAX] GR64
[%vreg52 -> %RAX] GR64
[%vreg54 -> %RDI] GR64
[%vreg57 -> %RAX] GR64
[%vreg60 -> %EAX] GR32
[%vreg62 -> %AL] GR8
[%vreg63 -> %RDI] GR64
[%vreg66 -> %RAX] GR64
[%vreg69 -> %RAX] GR64
[%vreg75 -> %ECX] GR32
[%vreg79 -> %EAX] GR32
[%vreg81 -> %AL] GR8
[%vreg82 -> %RDI] GR64
[%vreg85 -> %RAX] GR64
[%vreg89 -> %RCX] GR64
[%vreg91 -> %EAX] GR32
[%vreg92 -> %RAX] GR64
[%vreg96 -> %RAX] GR64
[%vreg97 -> %RAX] GR64
[%vreg99 -> %RAX] GR64
[%vreg102 -> %RDI] GR64
[%vreg104 -> %RAX] GR64
[%vreg107 -> %ESI] GR32
[%vreg111 -> %AL] GR8
[%vreg112 -> %EAX] GR32
[%vreg116 -> %RAX] GR64
[%vreg117 -> %RDI] GR64
[%vreg119 -> %RDI] GR64
[%vreg123 -> %ECX] GR32
[%vreg127 -> %EAX] GR32
[%vreg130 -> %RDI] GR64
[%vreg131 -> %RSI] GR64
[%vreg135 -> %EBX] GR32
[%vreg136 -> %AL] GR8


Stackmap 0:
  STACKMAP 0, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, %vreg3, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3] LD8[FixedStack0] GR64:%vreg3

i8* %progress_in: in stack slot 1 (size: 1)
i8* %progress_out: in stack slot 2 (size: 1)
%struct.EState** %s: in stack slot 3 (size: 8)
%struct.bz_stream* %strm: in register %RBX (vreg 3)
%struct.bz_stream** %strm.addr: in stack slot 0 (size: 8)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]

i8* %progress_in: in stack slot 1 (size: 1)
i8* %progress_out: in stack slot 2 (size: 1)
%struct.EState** %s: in stack slot 3 (size: 8)

Duplicate operand locations:


Stackmap 2:
  STACKMAP 2, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]

i8* %progress_in: in stack slot 1 (size: 1)
i8* %progress_out: in stack slot 2 (size: 1)
%struct.EState** %s: in stack slot 3 (size: 8)

Duplicate operand locations:


Stackmap 3:
  STACKMAP 3, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]

i8* %progress_in: in stack slot 1 (size: 1)
i8* %progress_out: in stack slot 2 (size: 1)
%struct.EState** %s: in stack slot 3 (size: 8)

Duplicate operand locations:


Stackmap 4:
  STACKMAP 4, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]

i8* %progress_in: in stack slot 1 (size: 1)
i8* %progress_out: in stack slot 2 (size: 1)
%struct.EState** %s: in stack slot 3 (size: 8)

Duplicate operand locations:


Stackmap 5:
  STACKMAP 5, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]

i8* %progress_in: in stack slot 1 (size: 1)
i8* %progress_out: in stack slot 2 (size: 1)
%struct.EState** %s: in stack slot 3 (size: 8)

Duplicate operand locations:


Stackmap 6:
  STACKMAP 6, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]

i8* %progress_in: in stack slot 1 (size: 1)
i8* %progress_out: in stack slot 2 (size: 1)
%struct.EState** %s: in stack slot 3 (size: 8)

Duplicate operand locations:


Stackmap 7:
  STACKMAP 7, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]

i8* %progress_in: in stack slot 1 (size: 1)
i8* %progress_out: in stack slot 2 (size: 1)
%struct.EState** %s: in stack slot 3 (size: 8)

Duplicate operand locations:


Stackmap 8:
  STACKMAP 8, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]

i8* %progress_in: in stack slot 1 (size: 1)
i8* %progress_out: in stack slot 2 (size: 1)
%struct.EState** %s: in stack slot 3 (size: 8)

Duplicate operand locations:


Stackmap 9:
  STACKMAP 9, 0, %vreg135:sub_8bit, ...; GR32:%vreg135

i8 %conv70: in register %EBX (vreg 135)

Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, %vreg3, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3] LD8[FixedStack0] GR64:%vreg3
  -> Call instruction SlotIndex 144B, searching vregs 0 -> 137 and stack slots -1 -> 4

  STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
  -> Call instruction SlotIndex 464B, searching vregs 0 -> 137 and stack slots -1 -> 4

  STACKMAP 2, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
  -> Call instruction SlotIndex 960B, searching vregs 0 -> 137 and stack slots -1 -> 4

  STACKMAP 3, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
  -> Call instruction SlotIndex 1200B, searching vregs 0 -> 137 and stack slots -1 -> 4

  STACKMAP 4, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
  -> Call instruction SlotIndex 1488B, searching vregs 0 -> 137 and stack slots -1 -> 4

  STACKMAP 5, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
  -> Call instruction SlotIndex 1824B, searching vregs 0 -> 137 and stack slots -1 -> 4

  STACKMAP 6, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
  -> Call instruction SlotIndex 2192B, searching vregs 0 -> 137 and stack slots -1 -> 4

  STACKMAP 7, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
  -> Call instruction SlotIndex 2464B, searching vregs 0 -> 137 and stack slots -1 -> 4

  STACKMAP 8, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
  -> Call instruction SlotIndex 2784B, searching vregs 0 -> 137 and stack slots -1 -> 4

  STACKMAP 9, 0, %vreg135:sub_8bit, ...; GR32:%vreg135
  -> Call instruction SlotIndex 3520B, searching vregs 0 -> 137 and stack slots -1 -> 4

********** REWRITE VIRTUAL REGISTERS **********
********** Function: handle_compress
********** REGISTER MAP **********
[%vreg3 -> %RBX] GR64
[%vreg6 -> %RAX] GR64
[%vreg9 -> %RAX] GR64
[%vreg11 -> %RDI] GR64
[%vreg12 -> %RSI] GR64
[%vreg15 -> %RAX] GR64
[%vreg19 -> %RCX] GR64
[%vreg21 -> %EAX] GR32
[%vreg22 -> %RAX] GR64
[%vreg28 -> %ECX] GR32
[%vreg32 -> %EAX] GR32
[%vreg34 -> %AL] GR8
[%vreg35 -> %RDI] GR64
[%vreg38 -> %RAX] GR64
[%vreg41 -> %RAX] GR64
[%vreg44 -> %EAX] GR32
[%vreg46 -> %AL] GR8
[%vreg47 -> %RDI] GR64
[%vreg50 -> %RAX] GR64
[%vreg52 -> %RAX] GR64
[%vreg54 -> %RDI] GR64
[%vreg57 -> %RAX] GR64
[%vreg60 -> %EAX] GR32
[%vreg62 -> %AL] GR8
[%vreg63 -> %RDI] GR64
[%vreg66 -> %RAX] GR64
[%vreg69 -> %RAX] GR64
[%vreg75 -> %ECX] GR32
[%vreg79 -> %EAX] GR32
[%vreg81 -> %AL] GR8
[%vreg82 -> %RDI] GR64
[%vreg85 -> %RAX] GR64
[%vreg89 -> %RCX] GR64
[%vreg91 -> %EAX] GR32
[%vreg92 -> %RAX] GR64
[%vreg96 -> %RAX] GR64
[%vreg97 -> %RAX] GR64
[%vreg99 -> %RAX] GR64
[%vreg102 -> %RDI] GR64
[%vreg104 -> %RAX] GR64
[%vreg107 -> %ESI] GR32
[%vreg111 -> %AL] GR8
[%vreg112 -> %EAX] GR32
[%vreg116 -> %RAX] GR64
[%vreg117 -> %RDI] GR64
[%vreg119 -> %RDI] GR64
[%vreg123 -> %ECX] GR32
[%vreg127 -> %EAX] GR32
[%vreg130 -> %RDI] GR64
[%vreg131 -> %RSI] GR64
[%vreg135 -> %EBX] GR32
[%vreg136 -> %AL] GR8

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI
16B		%vreg3<def> = COPY %RDI; GR64:%vreg3
48B		%vreg11<def> = MOV64ri <ga:@handle_compress>; GR64:%vreg11
80B		%vreg12<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg12
96B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
112B		%RDI<def> = COPY %vreg11<kill>; GR64:%vreg11
128B		%RSI<def> = COPY %vreg12<kill>; GR64:%vreg12
144B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
160B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
192B		STACKMAP 0, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, %vreg3, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3] LD8[FixedStack0] GR64:%vreg3
208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg3<kill>; mem:ST8[%strm.addr] GR64:%vreg3
240B		MOV8mi <fi#1>, 1, %noreg, 0, %noreg, 0; mem:ST1[%progress_in]
256B		MOV8mi <fi#2>, 1, %noreg, 0, %noreg, 0; mem:ST1[%progress_out]
272B		%vreg9<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg9
288B		%vreg6<def> = MOV64rm %vreg9<kill>, 1, %noreg, 48, %noreg; mem:LD8[%state] GR64:%vreg6,%vreg9
320B		MOV64mr <fi#3>, 1, %noreg, 0, %noreg, %vreg6<kill>; mem:ST8[%s] GR64:%vreg6
	    Successors according to CFG: BB#1
> %RBX<def> = COPY %RDI
> %RDI<def> = MOV64ri <ga:@handle_compress>
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 0, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, %RBX, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3] LD8[FixedStack0]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %RBX<kill>; mem:ST8[%strm.addr]
> MOV8mi <fi#1>, 1, %noreg, 0, %noreg, 0; mem:ST1[%progress_in]
> MOV8mi <fi#2>, 1, %noreg, 0, %noreg, 0; mem:ST1[%progress_out]
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 48, %noreg; mem:LD8[%state]
> MOV64mr <fi#3>, 1, %noreg, 0, %noreg, %RAX<kill>; mem:ST8[%s]
336B	BB#1: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#0 BB#24
352B		%vreg15<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg15
368B		CMP32mi8 %vreg15<kill>, 1, %noreg, 12, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%state1] GR64:%vreg15
384B		JNE_1 <BB#13>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#13 BB#2
> %RAX<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> CMP32mi8 %RAX<kill>, 1, %noreg, 12, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%state1]
> JNE_1 <BB#13>, %EFLAGS<imp-use,kill>
400B	BB#2: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#1
416B		%vreg35<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg35
432B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
448B		%RDI<def> = COPY %vreg35<kill>; GR64:%vreg35
464B		CALL64pcrel32 <ga:@copy_output_until_stop>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %AL<imp-def>
480B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
496B		%vreg34<def> = COPY %AL; GR8:%vreg34
512B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
528B		STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
544B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
560B		%vreg32<def> = MOVZX32rr8 %vreg34<kill>; GR32:%vreg32 GR8:%vreg34
576B		%vreg28<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%progress_out] GR32:%vreg28
608B		%vreg28<def,tied1> = OR32rr %vreg28<kill,tied0>, %vreg32<kill>, %EFLAGS<imp-def,dead>; GR32:%vreg28,%vreg32
640B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg28:sub_8bit<kill>; mem:ST1[%progress_out] GR32:%vreg28
656B		%vreg22<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg22
672B		%vreg21<def> = MOV32rm %vreg22<kill>, 1, %noreg, 120, %noreg; mem:LD4[%state_out_pos] GR32:%vreg21 GR64:%vreg22
688B		%vreg19<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg19
704B		CMP32rm %vreg21<kill>, %vreg19<kill>, 1, %noreg, 116, %noreg, %EFLAGS<imp-def>; mem:LD4[%numZ] GR32:%vreg21 GR64:%vreg19
720B		JGE_1 <BB#4>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#4 BB#3
> %RDI<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@copy_output_until_stop>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %AL<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %AL<def> = COPY %AL
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def> = MOVZX32rr8 %AL<kill>
> %ECX<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%progress_out]
> %ECX<def,tied1> = OR32rr %ECX<kill,tied0>, %EAX<kill>, %EFLAGS<imp-def,dead>
> MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %CL, %ECX<imp-use,kill>; mem:ST1[%progress_out]
> %RAX<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 120, %noreg; mem:LD4[%state_out_pos]
> %RCX<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> CMP32rm %EAX<kill>, %RCX<kill>, 1, %noreg, 116, %noreg, %EFLAGS<imp-def>; mem:LD4[%numZ]
> JGE_1 <BB#4>, %EFLAGS<imp-use,kill>
736B	BB#3: derived from LLVM BB %if.then.6
	    Predecessors according to CFG: BB#2
752B		JMP_1 <BB#25>
	    Successors according to CFG: BB#25
> JMP_1 <BB#25>
768B	BB#4: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#2
784B		%vreg38<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg38
800B		CMP32mi8 %vreg38<kill>, 1, %noreg, 8, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%mode] GR64:%vreg38
816B		JNE_1 <BB#8>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#8 BB#5
> %RAX<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> CMP32mi8 %RAX<kill>, 1, %noreg, 8, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%mode]
> JNE_1 <BB#8>, %EFLAGS<imp-use,kill>
832B	BB#5: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#4
848B		%vreg41<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg41
864B		CMP32mi8 %vreg41<kill>, 1, %noreg, 16, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_in_expect] GR64:%vreg41
880B		JNE_1 <BB#8>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#8 BB#6
> %RAX<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> CMP32mi8 %RAX<kill>, 1, %noreg, 16, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_in_expect]
> JNE_1 <BB#8>, %EFLAGS<imp-use,kill>
896B	BB#6: derived from LLVM BB %land.lhs.true.11
	    Predecessors according to CFG: BB#5
912B		%vreg47<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg47
928B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
944B		%RDI<def> = COPY %vreg47<kill>; GR64:%vreg47
960B		CALL64pcrel32 <ga:@isempty_RL>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %AL<imp-def>
976B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
992B		%vreg46<def> = COPY %AL; GR8:%vreg46
1008B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1024B		STACKMAP 2, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
1040B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1056B		%vreg44<def> = MOVZX32rr8 %vreg46<kill>; GR32:%vreg44 GR8:%vreg46
1072B		CMP32ri8 %vreg44<kill>, 0, %EFLAGS<imp-def>; GR32:%vreg44
1088B		JE_1 <BB#8>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#8 BB#7
> %RDI<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@isempty_RL>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %AL<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %AL<def> = COPY %AL
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 2, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def> = MOVZX32rr8 %AL<kill>
> CMP32ri8 %EAX<kill>, 0, %EFLAGS<imp-def>
> JE_1 <BB#8>, %EFLAGS<imp-use,kill>
1104B	BB#7: derived from LLVM BB %if.then.14
	    Predecessors according to CFG: BB#6
1120B		JMP_1 <BB#25>
	    Successors according to CFG: BB#25
> JMP_1 <BB#25>
1136B	BB#8: derived from LLVM BB %if.end.15
	    Predecessors according to CFG: BB#4 BB#5 BB#6
1152B		%vreg54<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg54
1168B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1184B		%RDI<def> = COPY %vreg54<kill>; GR64:%vreg54
1200B		CALL64pcrel32 <ga:@prepare_new_block>, <regmask>, %RSP<imp-use>, %RDI<imp-use>
1216B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1232B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1248B		STACKMAP 3, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
1264B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1280B		%vreg52<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg52
1296B		MOV32mi %vreg52<kill>, 1, %noreg, 12, %noreg, 2; mem:ST4[%state16] GR64:%vreg52
1312B		%vreg50<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg50
1328B		CMP32mi8 %vreg50<kill>, 1, %noreg, 8, %noreg, 3, %EFLAGS<imp-def>; mem:LD4[%mode17] GR64:%vreg50
1344B		JNE_1 <BB#12>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#12 BB#9
> %RDI<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@prepare_new_block>, <regmask>, %RSP<imp-use>, %RDI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 3, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RAX<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> MOV32mi %RAX<kill>, 1, %noreg, 12, %noreg, 2; mem:ST4[%state16]
> %RAX<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> CMP32mi8 %RAX<kill>, 1, %noreg, 8, %noreg, 3, %EFLAGS<imp-def>; mem:LD4[%mode17]
> JNE_1 <BB#12>, %EFLAGS<imp-use,kill>
1360B	BB#9: derived from LLVM BB %land.lhs.true.20
	    Predecessors according to CFG: BB#8
1376B		%vreg57<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg57
1392B		CMP32mi8 %vreg57<kill>, 1, %noreg, 16, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_in_expect21] GR64:%vreg57
1408B		JNE_1 <BB#12>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#12 BB#10
> %RAX<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> CMP32mi8 %RAX<kill>, 1, %noreg, 16, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_in_expect21]
> JNE_1 <BB#12>, %EFLAGS<imp-use,kill>
1424B	BB#10: derived from LLVM BB %land.lhs.true.24
	    Predecessors according to CFG: BB#9
1440B		%vreg63<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg63
1456B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1472B		%RDI<def> = COPY %vreg63<kill>; GR64:%vreg63
1488B		CALL64pcrel32 <ga:@isempty_RL>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %AL<imp-def>
1504B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1520B		%vreg62<def> = COPY %AL; GR8:%vreg62
1536B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1552B		STACKMAP 4, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
1568B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1584B		%vreg60<def> = MOVZX32rr8 %vreg62<kill>; GR32:%vreg60 GR8:%vreg62
1600B		CMP32ri8 %vreg60<kill>, 0, %EFLAGS<imp-def>; GR32:%vreg60
1616B		JE_1 <BB#12>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#12 BB#11
> %RDI<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@isempty_RL>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %AL<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %AL<def> = COPY %AL
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 4, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def> = MOVZX32rr8 %AL<kill>
> CMP32ri8 %EAX<kill>, 0, %EFLAGS<imp-def>
> JE_1 <BB#12>, %EFLAGS<imp-use,kill>
1632B	BB#11: derived from LLVM BB %if.then.28
	    Predecessors according to CFG: BB#10
1648B		JMP_1 <BB#25>
	    Successors according to CFG: BB#25
> JMP_1 <BB#25>
1664B	BB#12: derived from LLVM BB %if.end.29
	    Predecessors according to CFG: BB#8 BB#9 BB#10
1680B		JMP_1 <BB#13>
	    Successors according to CFG: BB#13
> JMP_1 <BB#13>
1696B	BB#13: derived from LLVM BB %if.end.30
	    Predecessors according to CFG: BB#1 BB#12
1712B		%vreg66<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg66
1728B		CMP32mi8 %vreg66<kill>, 1, %noreg, 12, %noreg, 2, %EFLAGS<imp-def>; mem:LD4[%state31] GR64:%vreg66
1744B		JNE_1 <BB#24>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#24 BB#14
> %RAX<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> CMP32mi8 %RAX<kill>, 1, %noreg, 12, %noreg, 2, %EFLAGS<imp-def>; mem:LD4[%state31]
> JNE_1 <BB#24>, %EFLAGS<imp-use,kill>
1760B	BB#14: derived from LLVM BB %if.then.34
	    Predecessors according to CFG: BB#13
1776B		%vreg82<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg82
1792B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1808B		%RDI<def> = COPY %vreg82<kill>; GR64:%vreg82
1824B		CALL64pcrel32 <ga:@copy_input_until_stop>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %AL<imp-def>
1840B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1856B		%vreg81<def> = COPY %AL; GR8:%vreg81
1872B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1888B		STACKMAP 5, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
1904B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1920B		%vreg79<def> = MOVZX32rr8 %vreg81<kill>; GR32:%vreg79 GR8:%vreg81
1936B		%vreg75<def> = MOVZX32rm8 <fi#1>, 1, %noreg, 0, %noreg; mem:LD1[%progress_in] GR32:%vreg75
1968B		%vreg75<def,tied1> = OR32rr %vreg75<kill,tied0>, %vreg79<kill>, %EFLAGS<imp-def,dead>; GR32:%vreg75,%vreg79
2000B		MOV8mr <fi#1>, 1, %noreg, 0, %noreg, %vreg75:sub_8bit<kill>; mem:ST1[%progress_in] GR32:%vreg75
2016B		%vreg69<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg69
2032B		CMP32mi8 %vreg69<kill>, 1, %noreg, 8, %noreg, 2, %EFLAGS<imp-def>; mem:LD4[%mode40] GR64:%vreg69
2048B		JE_1 <BB#17>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#17 BB#15
> %RDI<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@copy_input_until_stop>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %AL<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %AL<def> = COPY %AL
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 5, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def> = MOVZX32rr8 %AL<kill>
> %ECX<def> = MOVZX32rm8 <fi#1>, 1, %noreg, 0, %noreg; mem:LD1[%progress_in]
> %ECX<def,tied1> = OR32rr %ECX<kill,tied0>, %EAX<kill>, %EFLAGS<imp-def,dead>
> MOV8mr <fi#1>, 1, %noreg, 0, %noreg, %CL, %ECX<imp-use,kill>; mem:ST1[%progress_in]
> %RAX<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> CMP32mi8 %RAX<kill>, 1, %noreg, 8, %noreg, 2, %EFLAGS<imp-def>; mem:LD4[%mode40]
> JE_1 <BB#17>, %EFLAGS<imp-use,kill>
2064B	BB#15: derived from LLVM BB %land.lhs.true.43
	    Predecessors according to CFG: BB#14
2080B		%vreg85<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg85
2096B		CMP32mi8 %vreg85<kill>, 1, %noreg, 16, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_in_expect44] GR64:%vreg85
2112B		JNE_1 <BB#17>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#17 BB#16
> %RAX<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> CMP32mi8 %RAX<kill>, 1, %noreg, 16, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_in_expect44]
> JNE_1 <BB#17>, %EFLAGS<imp-use,kill>
2128B	BB#16: derived from LLVM BB %if.then.47
	    Predecessors according to CFG: BB#15
2144B		%vreg119<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg119
2160B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2176B		%RDI<def> = COPY %vreg119<kill>; GR64:%vreg119
2192B		CALL64pcrel32 <ga:@flush_RL>, <regmask>, %RSP<imp-use>, %RDI<imp-use>
2208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2224B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2240B		STACKMAP 6, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
2256B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2288B		%vreg116<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg116
2304B		CMP32mi8 %vreg116<kill>, 1, %noreg, 8, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%mode48] GR64:%vreg116
2312B		%vreg117<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg117
2320B		%vreg111<def> = SETEr %EFLAGS<imp-use,kill>; GR8:%vreg111
2352B		%vreg111<def,tied1> = AND8ri %vreg111<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR8:%vreg111
2368B		%vreg112<def> = MOVZX32rr8 %vreg111<kill>; GR32:%vreg112 GR8:%vreg111
2400B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2432B		%vreg107<def> = MOVZX32rr8 %vreg112:sub_8bit<kill>; GR32:%vreg107,%vreg112
2440B		%RDI<def> = COPY %vreg117<kill>; GR64:%vreg117
2448B		%ESI<def> = COPY %vreg107<kill>; GR32:%vreg107
2464B		CALL64pcrel32 <ga:@BZ2_compressBlock>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>
2480B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2496B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2512B		STACKMAP 7, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
2528B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2544B		%vreg104<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg104
2560B		MOV32mi %vreg104<kill>, 1, %noreg, 12, %noreg, 1; mem:ST4[%state52] GR64:%vreg104
2576B		JMP_1 <BB#23>
	    Successors according to CFG: BB#23
> %RDI<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@flush_RL>, <regmask>, %RSP<imp-use>, %RDI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 6, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RAX<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> CMP32mi8 %RAX<kill>, 1, %noreg, 8, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%mode48]
> %RDI<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> %AL<def> = SETEr %EFLAGS<imp-use,kill>
> %AL<def,tied1> = AND8ri %AL<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> %EAX<def> = MOVZX32rr8 %AL<kill>
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %ESI<def> = MOVZX32rr8 %AL, %EAX<imp-use,kill>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %ESI<def> = COPY %ESI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@BZ2_compressBlock>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 7, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RAX<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> MOV32mi %RAX<kill>, 1, %noreg, 12, %noreg, 1; mem:ST4[%state52]
> JMP_1 <BB#23>
2592B	BB#17: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#14 BB#15
2608B		%vreg92<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg92
2624B		%vreg91<def> = MOV32rm %vreg92<kill>, 1, %noreg, 108, %noreg; mem:LD4[%nblock] GR32:%vreg91 GR64:%vreg92
2640B		%vreg89<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg89
2656B		CMP32rm %vreg91<kill>, %vreg89<kill>, 1, %noreg, 112, %noreg, %EFLAGS<imp-def>; mem:LD4[%nblockMAX] GR32:%vreg91 GR64:%vreg89
2672B		JL_1 <BB#19>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#19 BB#18
> %RAX<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 108, %noreg; mem:LD4[%nblock]
> %RCX<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> CMP32rm %EAX<kill>, %RCX<kill>, 1, %noreg, 112, %noreg, %EFLAGS<imp-def>; mem:LD4[%nblockMAX]
> JL_1 <BB#19>, %EFLAGS<imp-use,kill>
2688B	BB#18: derived from LLVM BB %if.then.55
	    Predecessors according to CFG: BB#17
2720B		%vreg102<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg102
2736B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2768B		%ESI<def> = MOV32r0 %EFLAGS<imp-def,dead>
2776B		%RDI<def> = COPY %vreg102<kill>; GR64:%vreg102
2784B		CALL64pcrel32 <ga:@BZ2_compressBlock>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>
2800B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2816B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2832B		STACKMAP 8, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
2848B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2864B		%vreg99<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg99
2880B		MOV32mi %vreg99<kill>, 1, %noreg, 12, %noreg, 1; mem:ST4[%state56] GR64:%vreg99
2896B		JMP_1 <BB#22>
	    Successors according to CFG: BB#22
> %RDI<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %ESI<def> = MOV32r0 %EFLAGS<imp-def,dead>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@BZ2_compressBlock>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 8, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack2](align=1) LD8[FixedStack3]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RAX<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> MOV32mi %RAX<kill>, 1, %noreg, 12, %noreg, 1; mem:ST4[%state56]
> JMP_1 <BB#22>
2912B	BB#19: derived from LLVM BB %if.else.57
	    Predecessors according to CFG: BB#17
2928B		%vreg97<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg97
2944B		%vreg96<def> = MOV64rm %vreg97<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm58] GR64:%vreg96,%vreg97
2960B		CMP32mi8 %vreg96<kill>, 1, %noreg, 8, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_in] GR64:%vreg96
2976B		JNE_1 <BB#21>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#21 BB#20
> %RAX<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm58]
> CMP32mi8 %RAX<kill>, 1, %noreg, 8, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_in]
> JNE_1 <BB#21>, %EFLAGS<imp-use,kill>
2992B	BB#20: derived from LLVM BB %if.then.61
	    Predecessors according to CFG: BB#19
3008B		JMP_1 <BB#25>
	    Successors according to CFG: BB#25
> JMP_1 <BB#25>
3024B	BB#21: derived from LLVM BB %if.end.62
	    Predecessors according to CFG: BB#19
3040B		JMP_1 <BB#22>
	    Successors according to CFG: BB#22
> JMP_1 <BB#22>
3056B	BB#22: derived from LLVM BB %if.end.63
	    Predecessors according to CFG: BB#21 BB#18
3072B		JMP_1 <BB#23>
	    Successors according to CFG: BB#23
> JMP_1 <BB#23>
3088B	BB#23: derived from LLVM BB %if.end.64
	    Predecessors according to CFG: BB#22 BB#16
3104B		JMP_1 <BB#24>
	    Successors according to CFG: BB#24
> JMP_1 <BB#24>
3120B	BB#24: derived from LLVM BB %if.end.65
	    Predecessors according to CFG: BB#13 BB#23
3136B		JMP_1 <BB#1>
	    Successors according to CFG: BB#1
> JMP_1 <BB#1>
3152B	BB#25: derived from LLVM BB %while.end
	    Predecessors according to CFG: BB#20 BB#11 BB#7 BB#3
3168B		%vreg136<def> = MOV8ri 1; GR8:%vreg136
3184B		%vreg123<def> = MOVZX32rm8 <fi#1>, 1, %noreg, 0, %noreg; mem:LD1[%progress_in] GR32:%vreg123
3200B		CMP32ri8 %vreg123<kill>, 0, %EFLAGS<imp-def>; GR32:%vreg123
3232B		JNE_1 <BB#27>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#27 BB#26
> %AL<def> = MOV8ri 1
> %ECX<def> = MOVZX32rm8 <fi#1>, 1, %noreg, 0, %noreg; mem:LD1[%progress_in]
> CMP32ri8 %ECX<kill>, 0, %EFLAGS<imp-def>
> JNE_1 <BB#27>, %EFLAGS<imp-use,kill>
3248B	BB#26: derived from LLVM BB %lor.rhs
	    Predecessors according to CFG: BB#25
3264B		%vreg127<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%progress_out] GR32:%vreg127
3280B		CMP32ri8 %vreg127<kill>, 0, %EFLAGS<imp-def>; GR32:%vreg127
3296B		%vreg136<def> = SETNEr %EFLAGS<imp-use,kill>; GR8:%vreg136
	    Successors according to CFG: BB#27
> %EAX<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%progress_out]
> CMP32ri8 %EAX<kill>, 0, %EFLAGS<imp-def>
> %AL<def> = SETNEr %EFLAGS<imp-use,kill>
3328B	BB#27: derived from LLVM BB %lor.end
	    Live Ins: %AL
	    Predecessors according to CFG: BB#25 BB#26
3360B		%vreg130<def> = MOV64ri <ga:@handle_compress>; GR64:%vreg130
3408B		%vreg136<def,tied1> = AND8ri %vreg136<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR8:%vreg136
3424B		%vreg135<def> = MOVZX32rr8 %vreg136<kill>; GR32:%vreg135 GR8:%vreg136
3456B		%vreg131<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg131
3472B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3488B		%RDI<def> = COPY %vreg130<kill>; GR64:%vreg130
3504B		%RSI<def> = COPY %vreg131<kill>; GR64:%vreg131
3520B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
3536B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3552B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3568B		STACKMAP 9, 0, %vreg135:sub_8bit, ...; GR32:%vreg135
3584B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3600B		%AL<def> = COPY %vreg135:sub_8bit<kill>; GR32:%vreg135
3616B		RETQ %AL<imp-use>
> %RDI<def> = MOV64ri <ga:@handle_compress>
> %AL<def,tied1> = AND8ri %AL<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> %EBX<def> = MOVZX32rr8 %AL<kill>
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 9, 0, %BL, ...
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %AL<def> = COPY %BL, %EBX<imp-use,kill>
> RETQ %AL<imp-use>
Computing live-in reg-units in ABI blocks.
0B	BB#0 DIL#0
Created 1 new intervals.
********** INTERVALS **********
DIL [0B,16r:0)[112r,144r:2)[512r,544r:1)  0@0B-phi 1@512r 2@112r
%vreg0 [16r,32r:0)  0@16r
%vreg1 [32r,224r:0)  0@32r
%vreg4 [240r,256r:0)  0@240r
%vreg5 [48r,64r:0)  0@48r
%vreg6 [64r,112r:0)  0@64r
%vreg7 [80r,128r:0)  0@80r
%vreg10 [304r,320r:0)  0@304r
%vreg12 [624r,640r:0)  0@624r
%vreg13 [448r,464r:0)  0@448r
%vreg14 [464r,512r:0)  0@464r
%vreg15 [480r,528r:0)  0@480r
RegMasks: 144r 544r
********** MACHINEINSTRS **********
# Machine code for function isempty_RL: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=1, align=1, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
Function Live Ins: %RDI in %vreg0

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI
16B		%vreg0<def> = COPY %RDI; GR64:%vreg0
32B		%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
48B		%vreg5<def> = MOV64ri <ga:@isempty_RL>; GR64:%vreg5
64B		%vreg6<def> = COPY %vreg5; GR64:%vreg6,%vreg5
80B		%vreg7<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg7
96B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
112B		%RDI<def> = COPY %vreg6; GR64:%vreg6
128B		%RSI<def> = COPY %vreg7; GR64:%vreg7
144B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
160B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
192B		STACKMAP 0, 0, 0, <fi#0>, 0, %vreg1, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=1) LD8[FixedStack1] GR64:%vreg1
208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%s.addr] GR64:%vreg1
240B		%vreg4<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg4
256B		CMP32mi %vreg4, 1, %noreg, 92, %noreg, 256, %EFLAGS<imp-def>; mem:LD4[%state_in_ch] GR64:%vreg4
272B		JAE_1 <BB#3>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#3 BB#1

288B	BB#1: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#0
304B		%vreg10<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg10
320B		CMP32mi8 %vreg10, 1, %noreg, 96, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%state_in_len] GR64:%vreg10
336B		JLE_1 <BB#3>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#3 BB#2

352B	BB#2: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#1
368B		MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST1[%retval]
384B		JMP_1 <BB#4>
	    Successors according to CFG: BB#4

400B	BB#3: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#0 BB#1
416B		MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 1; mem:ST1[%retval]
	    Successors according to CFG: BB#4

432B	BB#4: derived from LLVM BB %return
	    Predecessors according to CFG: BB#3 BB#2
448B		%vreg13<def> = MOV64ri <ga:@isempty_RL>; GR64:%vreg13
464B		%vreg14<def> = COPY %vreg13; GR64:%vreg14,%vreg13
480B		%vreg15<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg15
496B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
512B		%RDI<def> = COPY %vreg14; GR64:%vreg14
528B		%RSI<def> = COPY %vreg15; GR64:%vreg15
544B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
560B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
576B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
592B		STACKMAP 1, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=1)
608B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
624B		%vreg12<def> = MOV8rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD1[%retval] GR8:%vreg12
640B		%AL<def> = COPY %vreg12; GR8:%vreg12
656B		RETQ %AL<imp-use,kill>

# End machine code for function isempty_RL.

********** SIMPLE REGISTER COALESCING **********
********** Function: isempty_RL
********** JOINING INTERVALS ***********
land.lhs.true:
if.else:
entry:
16B	%vreg0<def> = COPY %RDI; GR64:%vreg0
	Considering merging %vreg0 with %RDI
	Can only merge into reserved registers.
112B	%RDI<def> = COPY %vreg6; GR64:%vreg6
	Considering merging %vreg6 with %RDI
	Can only merge into reserved registers.
128B	%RSI<def> = COPY %vreg7; GR64:%vreg7
	Considering merging %vreg7 with %RSI
	Can only merge into reserved registers.
if.then:
return:
512B	%RDI<def> = COPY %vreg14; GR64:%vreg14
	Considering merging %vreg14 with %RDI
	Can only merge into reserved registers.
528B	%RSI<def> = COPY %vreg15; GR64:%vreg15
	Considering merging %vreg15 with %RSI
	Can only merge into reserved registers.
640B	%AL<def> = COPY %vreg12; GR8:%vreg12
	Considering merging %vreg12 with %AL
	Can only merge into reserved registers.
32B	%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
	Considering merging to GR64 with %vreg0 in %vreg1
		RHS = %vreg0 [16r,32r:0)  0@16r
		LHS = %vreg1 [32r,224r:0)  0@32r
		merge %vreg1:0@32r into %vreg0:0@16r --> @16r
		erased:	32r	%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
		updated: 16B	%vreg1<def> = COPY %RDI; GR64:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [16r,224r:0)  0@16r
64B	%vreg6<def> = COPY %vreg5; GR64:%vreg6,%vreg5
	Considering merging to GR64 with %vreg5 in %vreg6
		RHS = %vreg5 [48r,64r:0)  0@48r
		LHS = %vreg6 [64r,112r:0)  0@64r
		merge %vreg6:0@64r into %vreg5:0@48r --> @48r
		erased:	64r	%vreg6<def> = COPY %vreg5; GR64:%vreg6,%vreg5
		updated: 48B	%vreg6<def> = MOV64ri <ga:@isempty_RL>; GR64:%vreg6
	Success: %vreg5 -> %vreg6
	Result = %vreg6 [48r,112r:0)  0@48r
464B	%vreg14<def> = COPY %vreg13; GR64:%vreg14,%vreg13
	Considering merging to GR64 with %vreg13 in %vreg14
		RHS = %vreg13 [448r,464r:0)  0@448r
		LHS = %vreg14 [464r,512r:0)  0@464r
		merge %vreg14:0@464r into %vreg13:0@448r --> @448r
		erased:	464r	%vreg14<def> = COPY %vreg13; GR64:%vreg14,%vreg13
		updated: 448B	%vreg14<def> = MOV64ri <ga:@isempty_RL>; GR64:%vreg14
	Success: %vreg13 -> %vreg14
	Result = %vreg14 [448r,512r:0)  0@448r
112B	%RDI<def> = COPY %vreg6; GR64:%vreg6
	Considering merging %vreg6 with %RDI
	Can only merge into reserved registers.
512B	%RDI<def> = COPY %vreg14; GR64:%vreg14
	Considering merging %vreg14 with %RDI
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
DIL [0B,16r:0)[112r,144r:2)[512r,544r:1)  0@0B-phi 1@512r 2@112r
%vreg1 [16r,224r:0)  0@16r
%vreg4 [240r,256r:0)  0@240r
%vreg6 [48r,112r:0)  0@48r
%vreg7 [80r,128r:0)  0@80r
%vreg10 [304r,320r:0)  0@304r
%vreg12 [624r,640r:0)  0@624r
%vreg14 [448r,512r:0)  0@448r
%vreg15 [480r,528r:0)  0@480r
RegMasks: 144r 544r
********** MACHINEINSTRS **********
# Machine code for function isempty_RL: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=1, align=1, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
Function Live Ins: %RDI in %vreg0

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI
16B		%vreg1<def> = COPY %RDI; GR64:%vreg1
48B		%vreg6<def> = MOV64ri <ga:@isempty_RL>; GR64:%vreg6
80B		%vreg7<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg7
96B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
112B		%RDI<def> = COPY %vreg6; GR64:%vreg6
128B		%RSI<def> = COPY %vreg7; GR64:%vreg7
144B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
160B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
192B		STACKMAP 0, 0, 0, <fi#0>, 0, %vreg1, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=1) LD8[FixedStack1] GR64:%vreg1
208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%s.addr] GR64:%vreg1
240B		%vreg4<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg4
256B		CMP32mi %vreg4, 1, %noreg, 92, %noreg, 256, %EFLAGS<imp-def>; mem:LD4[%state_in_ch] GR64:%vreg4
272B		JAE_1 <BB#3>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#3 BB#1

288B	BB#1: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#0
304B		%vreg10<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg10
320B		CMP32mi8 %vreg10, 1, %noreg, 96, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%state_in_len] GR64:%vreg10
336B		JLE_1 <BB#3>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#3 BB#2

352B	BB#2: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#1
368B		MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST1[%retval]
384B		JMP_1 <BB#4>
	    Successors according to CFG: BB#4

400B	BB#3: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#0 BB#1
416B		MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 1; mem:ST1[%retval]
	    Successors according to CFG: BB#4

432B	BB#4: derived from LLVM BB %return
	    Predecessors according to CFG: BB#3 BB#2
448B		%vreg14<def> = MOV64ri <ga:@isempty_RL>; GR64:%vreg14
480B		%vreg15<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg15
496B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
512B		%RDI<def> = COPY %vreg14; GR64:%vreg14
528B		%RSI<def> = COPY %vreg15; GR64:%vreg15
544B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
560B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
576B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
592B		STACKMAP 1, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=1)
608B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
624B		%vreg12<def> = MOV8rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD1[%retval] GR8:%vreg12
640B		%AL<def> = COPY %vreg12; GR8:%vreg12
656B		RETQ %AL<imp-use,kill>

# End machine code for function isempty_RL.

********** GREEDY REGISTER ALLOCATION **********
********** Function: isempty_RL
********** INTERVALS **********
DIL [0B,16r:0)[112r,144r:2)[512r,544r:1)  0@0B-phi 1@512r 2@112r
%vreg1 [16r,224r:0)  0@16r
%vreg4 [240r,256r:0)  0@240r
%vreg6 [48r,112r:0)  0@48r
%vreg7 [80r,128r:0)  0@80r
%vreg10 [304r,320r:0)  0@304r
%vreg12 [624r,640r:0)  0@624r
%vreg14 [448r,512r:0)  0@448r
%vreg15 [480r,528r:0)  0@480r
RegMasks: 144r 544r
********** MACHINEINSTRS **********
# Machine code for function isempty_RL: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=1, align=1, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
Function Live Ins: %RDI in %vreg0

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI
16B		%vreg1<def> = COPY %RDI; GR64:%vreg1
48B		%vreg6<def> = MOV64ri <ga:@isempty_RL>; GR64:%vreg6
80B		%vreg7<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg7
96B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
112B		%RDI<def> = COPY %vreg6; GR64:%vreg6
128B		%RSI<def> = COPY %vreg7; GR64:%vreg7
144B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
160B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
192B		STACKMAP 0, 0, 0, <fi#0>, 0, %vreg1, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=1) LD8[FixedStack1] GR64:%vreg1
208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%s.addr] GR64:%vreg1
240B		%vreg4<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg4
256B		CMP32mi %vreg4, 1, %noreg, 92, %noreg, 256, %EFLAGS<imp-def>; mem:LD4[%state_in_ch] GR64:%vreg4
272B		JAE_1 <BB#3>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#3 BB#1

288B	BB#1: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#0
304B		%vreg10<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg10
320B		CMP32mi8 %vreg10, 1, %noreg, 96, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%state_in_len] GR64:%vreg10
336B		JLE_1 <BB#3>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#3 BB#2

352B	BB#2: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#1
368B		MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST1[%retval]
384B		JMP_1 <BB#4>
	    Successors according to CFG: BB#4

400B	BB#3: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#0 BB#1
416B		MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 1; mem:ST1[%retval]
	    Successors according to CFG: BB#4

432B	BB#4: derived from LLVM BB %return
	    Predecessors according to CFG: BB#3 BB#2
448B		%vreg14<def> = MOV64ri <ga:@isempty_RL>; GR64:%vreg14
480B		%vreg15<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg15
496B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
512B		%RDI<def> = COPY %vreg14; GR64:%vreg14
528B		%RSI<def> = COPY %vreg15; GR64:%vreg15
544B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
560B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
576B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
592B		STACKMAP 1, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=1)
608B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
624B		%vreg12<def> = MOV8rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD1[%retval] GR8:%vreg12
640B		%AL<def> = COPY %vreg12; GR8:%vreg12
656B		RETQ %AL<imp-use,kill>

# End machine code for function isempty_RL.


selectOrSplit GR64:%vreg1 [16r,224r:0)  0@16r w=4.983553e-03
hints: %RDI
missed hint %RDI
assigning %vreg1 to %RBX: BH [16r,224r:0)  0@16r BL [16r,224r:0)  0@16r

selectOrSplit GR64:%vreg6 [48r,112r:0)  0@48r w=2.176724e-03
hints: %RDI
assigning %vreg6 to %RDI: DIL [48r,112r:0)  0@48r

selectOrSplit GR64:%vreg7 [80r,128r:0)  0@80r w=4.508928e-03
hints: %RSI
assigning %vreg7 to %RSI: SIL [80r,128r:0)  0@80r

selectOrSplit GR64:%vreg14 [448r,512r:0)  0@448r w=2.176724e-03
hints: %RDI
assigning %vreg14 to %RDI: DIL [448r,512r:0)  0@448r

selectOrSplit GR64:%vreg15 [480r,528r:0)  0@480r w=4.508928e-03
hints: %RSI
assigning %vreg15 to %RSI: SIL [480r,528r:0)  0@480r

selectOrSplit GR8:%vreg12 [624r,640r:0)  0@624r w=inf
hints: %AL
assigning %vreg12 to %AL: AL [624r,640r:0)  0@624r

selectOrSplit GR64:%vreg4 [240r,256r:0)  0@240r w=inf
assigning %vreg4 to %RAX: AH [240r,256r:0)  0@240r AL [240r,256r:0)  0@240r

selectOrSplit GR64:%vreg10 [304r,320r:0)  0@304r w=inf
assigning %vreg10 to %RAX: AH [304r,320r:0)  0@304r AL [304r,320r:0)  0@304r

********** STACK TRANSFORMATION METADATA **********
********** Function: isempty_RL
********** REGISTER MAP **********
[%vreg1 -> %RBX] GR64
[%vreg4 -> %RAX] GR64
[%vreg6 -> %RDI] GR64
[%vreg7 -> %RSI] GR64
[%vreg10 -> %RAX] GR64
[%vreg12 -> %AL] GR8
[%vreg14 -> %RDI] GR64
[%vreg15 -> %RSI] GR64


Stackmap 0:
  STACKMAP 0, 0, 0, <fi#0>, 0, %vreg1, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=1) LD8[FixedStack1] GR64:%vreg1

i8* %retval: in stack slot 0 (size: 1)
%struct.EState* %s: in register %RBX (vreg 1)
%struct.EState** %s.addr: in stack slot 1 (size: 8)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=1)

i8* %retval: in stack slot 0 (size: 1)

Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, 0, <fi#0>, 0, %vreg1, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=1) LD8[FixedStack1] GR64:%vreg1
  -> Call instruction SlotIndex 144B, searching vregs 0 -> 16 and stack slots -1 -> 2

  STACKMAP 1, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=1)
  -> Call instruction SlotIndex 544B, searching vregs 0 -> 16 and stack slots -1 -> 2

********** REWRITE VIRTUAL REGISTERS **********
********** Function: isempty_RL
********** REGISTER MAP **********
[%vreg1 -> %RBX] GR64
[%vreg4 -> %RAX] GR64
[%vreg6 -> %RDI] GR64
[%vreg7 -> %RSI] GR64
[%vreg10 -> %RAX] GR64
[%vreg12 -> %AL] GR8
[%vreg14 -> %RDI] GR64
[%vreg15 -> %RSI] GR64

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI
16B		%vreg1<def> = COPY %RDI; GR64:%vreg1
48B		%vreg6<def> = MOV64ri <ga:@isempty_RL>; GR64:%vreg6
80B		%vreg7<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg7
96B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
112B		%RDI<def> = COPY %vreg6<kill>; GR64:%vreg6
128B		%RSI<def> = COPY %vreg7<kill>; GR64:%vreg7
144B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
160B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
192B		STACKMAP 0, 0, 0, <fi#0>, 0, %vreg1, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=1) LD8[FixedStack1] GR64:%vreg1
208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg1<kill>; mem:ST8[%s.addr] GR64:%vreg1
240B		%vreg4<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg4
256B		CMP32mi %vreg4<kill>, 1, %noreg, 92, %noreg, 256, %EFLAGS<imp-def>; mem:LD4[%state_in_ch] GR64:%vreg4
272B		JAE_1 <BB#3>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#3 BB#1
> %RBX<def> = COPY %RDI
> %RDI<def> = MOV64ri <ga:@isempty_RL>
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 0, 0, 0, <fi#0>, 0, %RBX, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=1) LD8[FixedStack1]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %RBX<kill>; mem:ST8[%s.addr]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> CMP32mi %RAX<kill>, 1, %noreg, 92, %noreg, 256, %EFLAGS<imp-def>; mem:LD4[%state_in_ch]
> JAE_1 <BB#3>, %EFLAGS<imp-use,kill>
288B	BB#1: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#0
304B		%vreg10<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg10
320B		CMP32mi8 %vreg10<kill>, 1, %noreg, 96, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%state_in_len] GR64:%vreg10
336B		JLE_1 <BB#3>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#3 BB#2
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> CMP32mi8 %RAX<kill>, 1, %noreg, 96, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%state_in_len]
> JLE_1 <BB#3>, %EFLAGS<imp-use,kill>
352B	BB#2: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#1
368B		MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST1[%retval]
384B		JMP_1 <BB#4>
	    Successors according to CFG: BB#4
> MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST1[%retval]
> JMP_1 <BB#4>
400B	BB#3: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#0 BB#1
416B		MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 1; mem:ST1[%retval]
	    Successors according to CFG: BB#4
> MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 1; mem:ST1[%retval]
432B	BB#4: derived from LLVM BB %return
	    Predecessors according to CFG: BB#3 BB#2
448B		%vreg14<def> = MOV64ri <ga:@isempty_RL>; GR64:%vreg14
480B		%vreg15<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg15
496B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
512B		%RDI<def> = COPY %vreg14<kill>; GR64:%vreg14
528B		%RSI<def> = COPY %vreg15<kill>; GR64:%vreg15
544B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
560B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
576B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
592B		STACKMAP 1, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=1)
608B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
624B		%vreg12<def> = MOV8rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD1[%retval] GR8:%vreg12
640B		%AL<def> = COPY %vreg12<kill>; GR8:%vreg12
656B		RETQ %AL<imp-use>
> %RDI<def> = MOV64ri <ga:@isempty_RL>
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 1, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=1)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %AL<def> = MOV8rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD1[%retval]
> %AL<def> = COPY %AL<kill>
Deleting identity copy.
> RETQ %AL<imp-use>
Computing live-in reg-units in ABI blocks.
0B	BB#0 DIL#0
Created 1 new intervals.
********** INTERVALS **********
DIL [0B,16r:0)[112r,144r:6)[816r,848r:5)[1136r,1168r:4)[1456r,1488r:3)[1696r,1728r:2)[1936r,1968r:1)  0@0B-phi 1@1936r 2@1696r 3@1456r 4@1136r 5@816r 6@112r
%vreg0 [16r,32r:0)  0@16r
%vreg1 [32r,224r:0)  0@32r
%vreg3 [48r,64r:0)  0@48r
%vreg4 [64r,112r:0)  0@64r
%vreg5 [80r,128r:0)  0@80r
%vreg9 [368r,384r:0)  0@368r
%vreg11 [352r,368r:0)  0@352r
%vreg12 [336r,352r:0)  0@336r
%vreg16 [512r,528r:0)  0@512r
%vreg17 [496r,512r:0)  0@496r
%vreg20 [624r,640r:0)  0@624r
%vreg25 [784r,832r:0)  0@784r
%vreg27 [768r,784r:0)  0@768r
%vreg28 [752r,768r:0)  0@752r
%vreg30 [736r,816r:0)  0@736r
%vreg31 [720r,736r:0)  0@720r
%vreg33 [704r,848r:0)  0@704r
%vreg34 [688r,704r:0)  0@688r
%vreg37 [944r,960r:0)  0@944r
%vreg42 [1104r,1152r:0)  0@1104r
%vreg44 [1088r,1104r:0)  0@1088r
%vreg45 [1072r,1088r:0)  0@1072r
%vreg47 [1056r,1136r:0)  0@1056r
%vreg48 [1040r,1056r:0)  0@1040r
%vreg50 [1024r,1168r:0)  0@1024r
%vreg51 [1008r,1024r:0)  0@1008r
%vreg54 [1264r,1280r:0)  0@1264r
%vreg59 [1424r,1472r:0)  0@1424r
%vreg61 [1408r,1424r:0)  0@1408r
%vreg62 [1392r,1408r:0)  0@1392r
%vreg64 [1376r,1456r:0)  0@1376r
%vreg65 [1360r,1376r:0)  0@1360r
%vreg67 [1344r,1488r:0)  0@1344r
%vreg68 [1328r,1344r:0)  0@1328r
%vreg70 [1808r,1824r:0)  0@1808r
%vreg75 [1664r,1712r:0)  0@1664r
%vreg76 [1648r,1664r:0)  0@1648r
%vreg78 [1632r,1696r:0)  0@1632r
%vreg79 [1616r,1632r:0)  0@1616r
%vreg81 [1600r,1728r:0)  0@1600r
%vreg82 [1584r,1600r:0)  0@1584r
%vreg84 [2048r,2064r:0)  0@2048r
%vreg85 [1872r,1888r:0)  0@1872r
%vreg86 [1888r,1936r:0)  0@1888r
%vreg87 [1904r,1952r:0)  0@1904r
RegMasks: 144r 848r 1168r 1488r 1728r 1968r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzCompressEnd: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=4, align=4, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=8, align=8, at location [SP+8]
Function Live Ins: %RDI in %vreg0

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI
16B		%vreg0<def> = COPY %RDI; GR64:%vreg0
32B		%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
48B		%vreg3<def> = MOV64ri <ga:@BZ2_bzCompressEnd>; GR64:%vreg3
64B		%vreg4<def> = COPY %vreg3; GR64:%vreg4,%vreg3
80B		%vreg5<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg5
96B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
112B		%RDI<def> = COPY %vreg4; GR64:%vreg4
128B		%RSI<def> = COPY %vreg5; GR64:%vreg5
144B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
160B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
192B		STACKMAP 0, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, %vreg1, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1] GR64:%vreg1
208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%strm.addr] GR64:%vreg1
240B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%strm.addr]
256B		JNE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

272B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
288B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
304B		JMP_1 <BB#13>
	    Successors according to CFG: BB#13

320B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0
336B		%vreg12<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg12
352B		%vreg11<def> = MOV64rm %vreg12, 1, %noreg, 48, %noreg; mem:LD8[%state] GR64:%vreg11,%vreg12
368B		%vreg9<def> = COPY %vreg11; GR64:%vreg9,%vreg11
384B		MOV64mr <fi#2>, 1, %noreg, 0, %noreg, %vreg9; mem:ST8[%s] GR64:%vreg9
400B		CMP64mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%s]
416B		JNE_1 <BB#4>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#4 BB#3

432B	BB#3: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#2
448B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
464B		JMP_1 <BB#13>
	    Successors according to CFG: BB#13

480B	BB#4: derived from LLVM BB %if.end.3
	    Predecessors according to CFG: BB#2
496B		%vreg17<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg17
512B		%vreg16<def> = MOV64rm %vreg17, 1, %noreg, 0, %noreg; mem:LD8[%strm4] GR64:%vreg16,%vreg17
528B		CMP64rm %vreg16, <fi#1>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD8[%strm.addr] GR64:%vreg16
544B		JE_1 <BB#6>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#6 BB#5

560B	BB#5: derived from LLVM BB %if.then.6
	    Predecessors according to CFG: BB#4
576B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
592B		JMP_1 <BB#13>
	    Successors according to CFG: BB#13

608B	BB#6: derived from LLVM BB %if.end.7
	    Predecessors according to CFG: BB#4
624B		%vreg20<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg20
640B		CMP64mi8 %vreg20, 1, %noreg, 24, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%arr1] GR64:%vreg20
656B		JE_1 <BB#8>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#8 BB#7

672B	BB#7: derived from LLVM BB %if.then.9
	    Predecessors according to CFG: BB#6
688B		%vreg34<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg34
704B		%vreg33<def> = MOV64rm %vreg34, 1, %noreg, 64, %noreg; mem:LD8[%bzfree] GR64:%vreg33,%vreg34
720B		%vreg31<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg31
736B		%vreg30<def> = MOV64rm %vreg31, 1, %noreg, 72, %noreg; mem:LD8[%opaque] GR64:%vreg30,%vreg31
752B		%vreg28<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg28
768B		%vreg27<def> = MOV64rm %vreg28, 1, %noreg, 24, %noreg; mem:LD8[%arr110] GR64:%vreg27,%vreg28
784B		%vreg25<def> = COPY %vreg27; GR64:%vreg25,%vreg27
800B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
816B		%RDI<def> = COPY %vreg30; GR64:%vreg30
832B		%RSI<def> = COPY %vreg25; GR64:%vreg25
848B		CALL64r %vreg33, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>; GR64:%vreg33
864B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
880B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
896B		STACKMAP 1, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1]
912B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#8

928B	BB#8: derived from LLVM BB %if.end.11
	    Predecessors according to CFG: BB#6 BB#7
944B		%vreg37<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg37
960B		CMP64mi8 %vreg37, 1, %noreg, 32, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%arr2] GR64:%vreg37
976B		JE_1 <BB#10>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#10 BB#9

992B	BB#9: derived from LLVM BB %if.then.13
	    Predecessors according to CFG: BB#8
1008B		%vreg51<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg51
1024B		%vreg50<def> = MOV64rm %vreg51, 1, %noreg, 64, %noreg; mem:LD8[%bzfree14] GR64:%vreg50,%vreg51
1040B		%vreg48<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg48
1056B		%vreg47<def> = MOV64rm %vreg48, 1, %noreg, 72, %noreg; mem:LD8[%opaque15] GR64:%vreg47,%vreg48
1072B		%vreg45<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg45
1088B		%vreg44<def> = MOV64rm %vreg45, 1, %noreg, 32, %noreg; mem:LD8[%arr216] GR64:%vreg44,%vreg45
1104B		%vreg42<def> = COPY %vreg44; GR64:%vreg42,%vreg44
1120B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1136B		%RDI<def> = COPY %vreg47; GR64:%vreg47
1152B		%RSI<def> = COPY %vreg42; GR64:%vreg42
1168B		CALL64r %vreg50, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>; GR64:%vreg50
1184B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1200B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1216B		STACKMAP 2, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1]
1232B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#10

1248B	BB#10: derived from LLVM BB %if.end.17
	    Predecessors according to CFG: BB#8 BB#9
1264B		%vreg54<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg54
1280B		CMP64mi8 %vreg54, 1, %noreg, 40, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%ftab] GR64:%vreg54
1296B		JE_1 <BB#12>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#12 BB#11

1312B	BB#11: derived from LLVM BB %if.then.19
	    Predecessors according to CFG: BB#10
1328B		%vreg68<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg68
1344B		%vreg67<def> = MOV64rm %vreg68, 1, %noreg, 64, %noreg; mem:LD8[%bzfree20] GR64:%vreg67,%vreg68
1360B		%vreg65<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg65
1376B		%vreg64<def> = MOV64rm %vreg65, 1, %noreg, 72, %noreg; mem:LD8[%opaque21] GR64:%vreg64,%vreg65
1392B		%vreg62<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg62
1408B		%vreg61<def> = MOV64rm %vreg62, 1, %noreg, 40, %noreg; mem:LD8[%ftab22] GR64:%vreg61,%vreg62
1424B		%vreg59<def> = COPY %vreg61; GR64:%vreg59,%vreg61
1440B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1456B		%RDI<def> = COPY %vreg64; GR64:%vreg64
1472B		%RSI<def> = COPY %vreg59; GR64:%vreg59
1488B		CALL64r %vreg67, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>; GR64:%vreg67
1504B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1520B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1536B		STACKMAP 3, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack1]
1552B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#12

1568B	BB#12: derived from LLVM BB %if.end.23
	    Predecessors according to CFG: BB#10 BB#11
1584B		%vreg82<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg82
1600B		%vreg81<def> = MOV64rm %vreg82, 1, %noreg, 64, %noreg; mem:LD8[%bzfree24] GR64:%vreg81,%vreg82
1616B		%vreg79<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg79
1632B		%vreg78<def> = MOV64rm %vreg79, 1, %noreg, 72, %noreg; mem:LD8[%opaque25] GR64:%vreg78,%vreg79
1648B		%vreg76<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg76
1664B		%vreg75<def> = MOV64rm %vreg76, 1, %noreg, 48, %noreg; mem:LD8[%state26] GR64:%vreg75,%vreg76
1680B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1696B		%RDI<def> = COPY %vreg78; GR64:%vreg78
1712B		%RSI<def> = COPY %vreg75; GR64:%vreg75
1728B		CALL64r %vreg81, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>; GR64:%vreg81
1744B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1760B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1776B		STACKMAP 4, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack1]
1792B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1808B		%vreg70<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg70
1824B		MOV64mi32 %vreg70, 1, %noreg, 48, %noreg, 0; mem:ST8[%state27] GR64:%vreg70
1840B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
	    Successors according to CFG: BB#13

1856B	BB#13: derived from LLVM BB %return
	    Predecessors according to CFG: BB#12 BB#5 BB#3 BB#1
1872B		%vreg85<def> = MOV64ri <ga:@BZ2_bzCompressEnd>; GR64:%vreg85
1888B		%vreg86<def> = COPY %vreg85; GR64:%vreg86,%vreg85
1904B		%vreg87<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg87
1920B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1936B		%RDI<def> = COPY %vreg86; GR64:%vreg86
1952B		%RSI<def> = COPY %vreg87; GR64:%vreg87
1968B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
1984B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2000B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2016B		STACKMAP 5, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
2032B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2048B		%vreg84<def> = MOV32rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD4[%retval] GR32:%vreg84
2064B		%EAX<def> = COPY %vreg84; GR32:%vreg84
2080B		RETQ %EAX<imp-use,kill>

# End machine code for function BZ2_bzCompressEnd.

********** SIMPLE REGISTER COALESCING **********
********** Function: BZ2_bzCompressEnd
********** JOINING INTERVALS ***********
if.end.11:
if.end.17:
return:
1936B	%RDI<def> = COPY %vreg86; GR64:%vreg86
	Considering merging %vreg86 with %RDI
	Can only merge into reserved registers.
1952B	%RSI<def> = COPY %vreg87; GR64:%vreg87
	Considering merging %vreg87 with %RSI
	Can only merge into reserved registers.
2064B	%EAX<def> = COPY %vreg84; GR32:%vreg84
	Considering merging %vreg84 with %EAX
	Can only merge into reserved registers.
if.end:
if.end.3:
if.end.7:
if.end.23:
1696B	%RDI<def> = COPY %vreg78; GR64:%vreg78
	Considering merging %vreg78 with %RDI
	Can only merge into reserved registers.
1712B	%RSI<def> = COPY %vreg75; GR64:%vreg75
	Considering merging %vreg75 with %RSI
	Can only merge into reserved registers.
entry:
16B	%vreg0<def> = COPY %RDI; GR64:%vreg0
	Considering merging %vreg0 with %RDI
	Can only merge into reserved registers.
112B	%RDI<def> = COPY %vreg4; GR64:%vreg4
	Considering merging %vreg4 with %RDI
	Can only merge into reserved registers.
128B	%RSI<def> = COPY %vreg5; GR64:%vreg5
	Considering merging %vreg5 with %RSI
	Can only merge into reserved registers.
if.then:
if.then.2:
if.then.6:
if.then.9:
816B	%RDI<def> = COPY %vreg30; GR64:%vreg30
	Considering merging %vreg30 with %RDI
	Can only merge into reserved registers.
832B	%RSI<def> = COPY %vreg25; GR64:%vreg25
	Considering merging %vreg25 with %RSI
	Can only merge into reserved registers.
if.then.13:
1136B	%RDI<def> = COPY %vreg47; GR64:%vreg47
	Considering merging %vreg47 with %RDI
	Can only merge into reserved registers.
1152B	%RSI<def> = COPY %vreg42; GR64:%vreg42
	Considering merging %vreg42 with %RSI
	Can only merge into reserved registers.
if.then.19:
1456B	%RDI<def> = COPY %vreg64; GR64:%vreg64
	Considering merging %vreg64 with %RDI
	Can only merge into reserved registers.
1472B	%RSI<def> = COPY %vreg59; GR64:%vreg59
	Considering merging %vreg59 with %RSI
	Can only merge into reserved registers.
1888B	%vreg86<def> = COPY %vreg85; GR64:%vreg86,%vreg85
	Considering merging to GR64 with %vreg85 in %vreg86
		RHS = %vreg85 [1872r,1888r:0)  0@1872r
		LHS = %vreg86 [1888r,1936r:0)  0@1888r
		merge %vreg86:0@1888r into %vreg85:0@1872r --> @1872r
		erased:	1888r	%vreg86<def> = COPY %vreg85; GR64:%vreg86,%vreg85
		updated: 1872B	%vreg86<def> = MOV64ri <ga:@BZ2_bzCompressEnd>; GR64:%vreg86
	Success: %vreg85 -> %vreg86
	Result = %vreg86 [1872r,1936r:0)  0@1872r
368B	%vreg9<def> = COPY %vreg11; GR64:%vreg9,%vreg11
	Considering merging to GR64 with %vreg11 in %vreg9
		RHS = %vreg11 [352r,368r:0)  0@352r
		LHS = %vreg9 [368r,384r:0)  0@368r
		merge %vreg9:0@368r into %vreg11:0@352r --> @352r
		erased:	368r	%vreg9<def> = COPY %vreg11; GR64:%vreg9,%vreg11
		updated: 352B	%vreg9<def> = MOV64rm %vreg12, 1, %noreg, 48, %noreg; mem:LD8[%state] GR64:%vreg9,%vreg12
	Success: %vreg11 -> %vreg9
	Result = %vreg9 [352r,384r:0)  0@352r
32B	%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
	Considering merging to GR64 with %vreg0 in %vreg1
		RHS = %vreg0 [16r,32r:0)  0@16r
		LHS = %vreg1 [32r,224r:0)  0@32r
		merge %vreg1:0@32r into %vreg0:0@16r --> @16r
		erased:	32r	%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
		updated: 16B	%vreg1<def> = COPY %RDI; GR64:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [16r,224r:0)  0@16r
64B	%vreg4<def> = COPY %vreg3; GR64:%vreg4,%vreg3
	Considering merging to GR64 with %vreg3 in %vreg4
		RHS = %vreg3 [48r,64r:0)  0@48r
		LHS = %vreg4 [64r,112r:0)  0@64r
		merge %vreg4:0@64r into %vreg3:0@48r --> @48r
		erased:	64r	%vreg4<def> = COPY %vreg3; GR64:%vreg4,%vreg3
		updated: 48B	%vreg4<def> = MOV64ri <ga:@BZ2_bzCompressEnd>; GR64:%vreg4
	Success: %vreg3 -> %vreg4
	Result = %vreg4 [48r,112r:0)  0@48r
784B	%vreg25<def> = COPY %vreg27; GR64:%vreg25,%vreg27
	Considering merging to GR64 with %vreg27 in %vreg25
		RHS = %vreg27 [768r,784r:0)  0@768r
		LHS = %vreg25 [784r,832r:0)  0@784r
		merge %vreg25:0@784r into %vreg27:0@768r --> @768r
		erased:	784r	%vreg25<def> = COPY %vreg27; GR64:%vreg25,%vreg27
		updated: 768B	%vreg25<def> = MOV64rm %vreg28, 1, %noreg, 24, %noreg; mem:LD8[%arr110] GR64:%vreg25,%vreg28
	Success: %vreg27 -> %vreg25
	Result = %vreg25 [768r,832r:0)  0@768r
1104B	%vreg42<def> = COPY %vreg44; GR64:%vreg42,%vreg44
	Considering merging to GR64 with %vreg44 in %vreg42
		RHS = %vreg44 [1088r,1104r:0)  0@1088r
		LHS = %vreg42 [1104r,1152r:0)  0@1104r
		merge %vreg42:0@1104r into %vreg44:0@1088r --> @1088r
		erased:	1104r	%vreg42<def> = COPY %vreg44; GR64:%vreg42,%vreg44
		updated: 1088B	%vreg42<def> = MOV64rm %vreg45, 1, %noreg, 32, %noreg; mem:LD8[%arr216] GR64:%vreg42,%vreg45
	Success: %vreg44 -> %vreg42
	Result = %vreg42 [1088r,1152r:0)  0@1088r
1424B	%vreg59<def> = COPY %vreg61; GR64:%vreg59,%vreg61
	Considering merging to GR64 with %vreg61 in %vreg59
		RHS = %vreg61 [1408r,1424r:0)  0@1408r
		LHS = %vreg59 [1424r,1472r:0)  0@1424r
		merge %vreg59:0@1424r into %vreg61:0@1408r --> @1408r
		erased:	1424r	%vreg59<def> = COPY %vreg61; GR64:%vreg59,%vreg61
		updated: 1408B	%vreg59<def> = MOV64rm %vreg62, 1, %noreg, 40, %noreg; mem:LD8[%ftab22] GR64:%vreg59,%vreg62
	Success: %vreg61 -> %vreg59
	Result = %vreg59 [1408r,1472r:0)  0@1408r
1936B	%RDI<def> = COPY %vreg86; GR64:%vreg86
	Considering merging %vreg86 with %RDI
	Can only merge into reserved registers.
112B	%RDI<def> = COPY %vreg4; GR64:%vreg4
	Considering merging %vreg4 with %RDI
	Can only merge into reserved registers.
832B	%RSI<def> = COPY %vreg25; GR64:%vreg25
	Considering merging %vreg25 with %RSI
	Can only merge into reserved registers.
1152B	%RSI<def> = COPY %vreg42; GR64:%vreg42
	Considering merging %vreg42 with %RSI
	Can only merge into reserved registers.
1472B	%RSI<def> = COPY %vreg59; GR64:%vreg59
	Considering merging %vreg59 with %RSI
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
DIL [0B,16r:0)[112r,144r:6)[816r,848r:5)[1136r,1168r:4)[1456r,1488r:3)[1696r,1728r:2)[1936r,1968r:1)  0@0B-phi 1@1936r 2@1696r 3@1456r 4@1136r 5@816r 6@112r
%vreg1 [16r,224r:0)  0@16r
%vreg4 [48r,112r:0)  0@48r
%vreg5 [80r,128r:0)  0@80r
%vreg9 [352r,384r:0)  0@352r
%vreg12 [336r,352r:0)  0@336r
%vreg16 [512r,528r:0)  0@512r
%vreg17 [496r,512r:0)  0@496r
%vreg20 [624r,640r:0)  0@624r
%vreg25 [768r,832r:0)  0@768r
%vreg28 [752r,768r:0)  0@752r
%vreg30 [736r,816r:0)  0@736r
%vreg31 [720r,736r:0)  0@720r
%vreg33 [704r,848r:0)  0@704r
%vreg34 [688r,704r:0)  0@688r
%vreg37 [944r,960r:0)  0@944r
%vreg42 [1088r,1152r:0)  0@1088r
%vreg45 [1072r,1088r:0)  0@1072r
%vreg47 [1056r,1136r:0)  0@1056r
%vreg48 [1040r,1056r:0)  0@1040r
%vreg50 [1024r,1168r:0)  0@1024r
%vreg51 [1008r,1024r:0)  0@1008r
%vreg54 [1264r,1280r:0)  0@1264r
%vreg59 [1408r,1472r:0)  0@1408r
%vreg62 [1392r,1408r:0)  0@1392r
%vreg64 [1376r,1456r:0)  0@1376r
%vreg65 [1360r,1376r:0)  0@1360r
%vreg67 [1344r,1488r:0)  0@1344r
%vreg68 [1328r,1344r:0)  0@1328r
%vreg70 [1808r,1824r:0)  0@1808r
%vreg75 [1664r,1712r:0)  0@1664r
%vreg76 [1648r,1664r:0)  0@1648r
%vreg78 [1632r,1696r:0)  0@1632r
%vreg79 [1616r,1632r:0)  0@1616r
%vreg81 [1600r,1728r:0)  0@1600r
%vreg82 [1584r,1600r:0)  0@1584r
%vreg84 [2048r,2064r:0)  0@2048r
%vreg86 [1872r,1936r:0)  0@1872r
%vreg87 [1904r,1952r:0)  0@1904r
RegMasks: 144r 848r 1168r 1488r 1728r 1968r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzCompressEnd: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=4, align=4, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=8, align=8, at location [SP+8]
Function Live Ins: %RDI in %vreg0

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI
16B		%vreg1<def> = COPY %RDI; GR64:%vreg1
48B		%vreg4<def> = MOV64ri <ga:@BZ2_bzCompressEnd>; GR64:%vreg4
80B		%vreg5<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg5
96B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
112B		%RDI<def> = COPY %vreg4; GR64:%vreg4
128B		%RSI<def> = COPY %vreg5; GR64:%vreg5
144B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
160B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
192B		STACKMAP 0, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, %vreg1, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1] GR64:%vreg1
208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%strm.addr] GR64:%vreg1
240B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%strm.addr]
256B		JNE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

272B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
288B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
304B		JMP_1 <BB#13>
	    Successors according to CFG: BB#13

320B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0
336B		%vreg12<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg12
352B		%vreg9<def> = MOV64rm %vreg12, 1, %noreg, 48, %noreg; mem:LD8[%state] GR64:%vreg9,%vreg12
384B		MOV64mr <fi#2>, 1, %noreg, 0, %noreg, %vreg9; mem:ST8[%s] GR64:%vreg9
400B		CMP64mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%s]
416B		JNE_1 <BB#4>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#4 BB#3

432B	BB#3: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#2
448B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
464B		JMP_1 <BB#13>
	    Successors according to CFG: BB#13

480B	BB#4: derived from LLVM BB %if.end.3
	    Predecessors according to CFG: BB#2
496B		%vreg17<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg17
512B		%vreg16<def> = MOV64rm %vreg17, 1, %noreg, 0, %noreg; mem:LD8[%strm4] GR64:%vreg16,%vreg17
528B		CMP64rm %vreg16, <fi#1>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD8[%strm.addr] GR64:%vreg16
544B		JE_1 <BB#6>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#6 BB#5

560B	BB#5: derived from LLVM BB %if.then.6
	    Predecessors according to CFG: BB#4
576B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
592B		JMP_1 <BB#13>
	    Successors according to CFG: BB#13

608B	BB#6: derived from LLVM BB %if.end.7
	    Predecessors according to CFG: BB#4
624B		%vreg20<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg20
640B		CMP64mi8 %vreg20, 1, %noreg, 24, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%arr1] GR64:%vreg20
656B		JE_1 <BB#8>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#8 BB#7

672B	BB#7: derived from LLVM BB %if.then.9
	    Predecessors according to CFG: BB#6
688B		%vreg34<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg34
704B		%vreg33<def> = MOV64rm %vreg34, 1, %noreg, 64, %noreg; mem:LD8[%bzfree] GR64:%vreg33,%vreg34
720B		%vreg31<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg31
736B		%vreg30<def> = MOV64rm %vreg31, 1, %noreg, 72, %noreg; mem:LD8[%opaque] GR64:%vreg30,%vreg31
752B		%vreg28<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg28
768B		%vreg25<def> = MOV64rm %vreg28, 1, %noreg, 24, %noreg; mem:LD8[%arr110] GR64:%vreg25,%vreg28
800B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
816B		%RDI<def> = COPY %vreg30; GR64:%vreg30
832B		%RSI<def> = COPY %vreg25; GR64:%vreg25
848B		CALL64r %vreg33, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>; GR64:%vreg33
864B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
880B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
896B		STACKMAP 1, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1]
912B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#8

928B	BB#8: derived from LLVM BB %if.end.11
	    Predecessors according to CFG: BB#6 BB#7
944B		%vreg37<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg37
960B		CMP64mi8 %vreg37, 1, %noreg, 32, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%arr2] GR64:%vreg37
976B		JE_1 <BB#10>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#10 BB#9

992B	BB#9: derived from LLVM BB %if.then.13
	    Predecessors according to CFG: BB#8
1008B		%vreg51<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg51
1024B		%vreg50<def> = MOV64rm %vreg51, 1, %noreg, 64, %noreg; mem:LD8[%bzfree14] GR64:%vreg50,%vreg51
1040B		%vreg48<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg48
1056B		%vreg47<def> = MOV64rm %vreg48, 1, %noreg, 72, %noreg; mem:LD8[%opaque15] GR64:%vreg47,%vreg48
1072B		%vreg45<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg45
1088B		%vreg42<def> = MOV64rm %vreg45, 1, %noreg, 32, %noreg; mem:LD8[%arr216] GR64:%vreg42,%vreg45
1120B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1136B		%RDI<def> = COPY %vreg47; GR64:%vreg47
1152B		%RSI<def> = COPY %vreg42; GR64:%vreg42
1168B		CALL64r %vreg50, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>; GR64:%vreg50
1184B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1200B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1216B		STACKMAP 2, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1]
1232B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#10

1248B	BB#10: derived from LLVM BB %if.end.17
	    Predecessors according to CFG: BB#8 BB#9
1264B		%vreg54<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg54
1280B		CMP64mi8 %vreg54, 1, %noreg, 40, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%ftab] GR64:%vreg54
1296B		JE_1 <BB#12>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#12 BB#11

1312B	BB#11: derived from LLVM BB %if.then.19
	    Predecessors according to CFG: BB#10
1328B		%vreg68<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg68
1344B		%vreg67<def> = MOV64rm %vreg68, 1, %noreg, 64, %noreg; mem:LD8[%bzfree20] GR64:%vreg67,%vreg68
1360B		%vreg65<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg65
1376B		%vreg64<def> = MOV64rm %vreg65, 1, %noreg, 72, %noreg; mem:LD8[%opaque21] GR64:%vreg64,%vreg65
1392B		%vreg62<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg62
1408B		%vreg59<def> = MOV64rm %vreg62, 1, %noreg, 40, %noreg; mem:LD8[%ftab22] GR64:%vreg59,%vreg62
1440B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1456B		%RDI<def> = COPY %vreg64; GR64:%vreg64
1472B		%RSI<def> = COPY %vreg59; GR64:%vreg59
1488B		CALL64r %vreg67, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>; GR64:%vreg67
1504B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1520B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1536B		STACKMAP 3, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack1]
1552B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#12

1568B	BB#12: derived from LLVM BB %if.end.23
	    Predecessors according to CFG: BB#10 BB#11
1584B		%vreg82<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg82
1600B		%vreg81<def> = MOV64rm %vreg82, 1, %noreg, 64, %noreg; mem:LD8[%bzfree24] GR64:%vreg81,%vreg82
1616B		%vreg79<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg79
1632B		%vreg78<def> = MOV64rm %vreg79, 1, %noreg, 72, %noreg; mem:LD8[%opaque25] GR64:%vreg78,%vreg79
1648B		%vreg76<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg76
1664B		%vreg75<def> = MOV64rm %vreg76, 1, %noreg, 48, %noreg; mem:LD8[%state26] GR64:%vreg75,%vreg76
1680B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1696B		%RDI<def> = COPY %vreg78; GR64:%vreg78
1712B		%RSI<def> = COPY %vreg75; GR64:%vreg75
1728B		CALL64r %vreg81, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>; GR64:%vreg81
1744B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1760B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1776B		STACKMAP 4, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack1]
1792B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1808B		%vreg70<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg70
1824B		MOV64mi32 %vreg70, 1, %noreg, 48, %noreg, 0; mem:ST8[%state27] GR64:%vreg70
1840B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
	    Successors according to CFG: BB#13

1856B	BB#13: derived from LLVM BB %return
	    Predecessors according to CFG: BB#12 BB#5 BB#3 BB#1
1872B		%vreg86<def> = MOV64ri <ga:@BZ2_bzCompressEnd>; GR64:%vreg86
1904B		%vreg87<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg87
1920B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1936B		%RDI<def> = COPY %vreg86; GR64:%vreg86
1952B		%RSI<def> = COPY %vreg87; GR64:%vreg87
1968B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
1984B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2000B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2016B		STACKMAP 5, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
2032B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2048B		%vreg84<def> = MOV32rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD4[%retval] GR32:%vreg84
2064B		%EAX<def> = COPY %vreg84; GR32:%vreg84
2080B		RETQ %EAX<imp-use,kill>

# End machine code for function BZ2_bzCompressEnd.

********** GREEDY REGISTER ALLOCATION **********
********** Function: BZ2_bzCompressEnd
********** INTERVALS **********
DIL [0B,16r:0)[112r,144r:6)[816r,848r:5)[1136r,1168r:4)[1456r,1488r:3)[1696r,1728r:2)[1936r,1968r:1)  0@0B-phi 1@1936r 2@1696r 3@1456r 4@1136r 5@816r 6@112r
%vreg1 [16r,224r:0)  0@16r
%vreg4 [48r,112r:0)  0@48r
%vreg5 [80r,128r:0)  0@80r
%vreg9 [352r,384r:0)  0@352r
%vreg12 [336r,352r:0)  0@336r
%vreg16 [512r,528r:0)  0@512r
%vreg17 [496r,512r:0)  0@496r
%vreg20 [624r,640r:0)  0@624r
%vreg25 [768r,832r:0)  0@768r
%vreg28 [752r,768r:0)  0@752r
%vreg30 [736r,816r:0)  0@736r
%vreg31 [720r,736r:0)  0@720r
%vreg33 [704r,848r:0)  0@704r
%vreg34 [688r,704r:0)  0@688r
%vreg37 [944r,960r:0)  0@944r
%vreg42 [1088r,1152r:0)  0@1088r
%vreg45 [1072r,1088r:0)  0@1072r
%vreg47 [1056r,1136r:0)  0@1056r
%vreg48 [1040r,1056r:0)  0@1040r
%vreg50 [1024r,1168r:0)  0@1024r
%vreg51 [1008r,1024r:0)  0@1008r
%vreg54 [1264r,1280r:0)  0@1264r
%vreg59 [1408r,1472r:0)  0@1408r
%vreg62 [1392r,1408r:0)  0@1392r
%vreg64 [1376r,1456r:0)  0@1376r
%vreg65 [1360r,1376r:0)  0@1360r
%vreg67 [1344r,1488r:0)  0@1344r
%vreg68 [1328r,1344r:0)  0@1328r
%vreg70 [1808r,1824r:0)  0@1808r
%vreg75 [1664r,1712r:0)  0@1664r
%vreg76 [1648r,1664r:0)  0@1648r
%vreg78 [1632r,1696r:0)  0@1632r
%vreg79 [1616r,1632r:0)  0@1616r
%vreg81 [1600r,1728r:0)  0@1600r
%vreg82 [1584r,1600r:0)  0@1584r
%vreg84 [2048r,2064r:0)  0@2048r
%vreg86 [1872r,1936r:0)  0@1872r
%vreg87 [1904r,1952r:0)  0@1904r
RegMasks: 144r 848r 1168r 1488r 1728r 1968r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzCompressEnd: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=4, align=4, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=8, align=8, at location [SP+8]
Function Live Ins: %RDI in %vreg0

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI
16B		%vreg1<def> = COPY %RDI; GR64:%vreg1
48B		%vreg4<def> = MOV64ri <ga:@BZ2_bzCompressEnd>; GR64:%vreg4
80B		%vreg5<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg5
96B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
112B		%RDI<def> = COPY %vreg4; GR64:%vreg4
128B		%RSI<def> = COPY %vreg5; GR64:%vreg5
144B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
160B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
192B		STACKMAP 0, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, %vreg1, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1] GR64:%vreg1
208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%strm.addr] GR64:%vreg1
240B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%strm.addr]
256B		JNE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

272B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
288B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
304B		JMP_1 <BB#13>
	    Successors according to CFG: BB#13

320B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0
336B		%vreg12<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg12
352B		%vreg9<def> = MOV64rm %vreg12, 1, %noreg, 48, %noreg; mem:LD8[%state] GR64:%vreg9,%vreg12
384B		MOV64mr <fi#2>, 1, %noreg, 0, %noreg, %vreg9; mem:ST8[%s] GR64:%vreg9
400B		CMP64mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%s]
416B		JNE_1 <BB#4>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#4 BB#3

432B	BB#3: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#2
448B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
464B		JMP_1 <BB#13>
	    Successors according to CFG: BB#13

480B	BB#4: derived from LLVM BB %if.end.3
	    Predecessors according to CFG: BB#2
496B		%vreg17<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg17
512B		%vreg16<def> = MOV64rm %vreg17, 1, %noreg, 0, %noreg; mem:LD8[%strm4] GR64:%vreg16,%vreg17
528B		CMP64rm %vreg16, <fi#1>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD8[%strm.addr] GR64:%vreg16
544B		JE_1 <BB#6>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#6 BB#5

560B	BB#5: derived from LLVM BB %if.then.6
	    Predecessors according to CFG: BB#4
576B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
592B		JMP_1 <BB#13>
	    Successors according to CFG: BB#13

608B	BB#6: derived from LLVM BB %if.end.7
	    Predecessors according to CFG: BB#4
624B		%vreg20<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg20
640B		CMP64mi8 %vreg20, 1, %noreg, 24, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%arr1] GR64:%vreg20
656B		JE_1 <BB#8>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#8 BB#7

672B	BB#7: derived from LLVM BB %if.then.9
	    Predecessors according to CFG: BB#6
688B		%vreg34<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg34
704B		%vreg33<def> = MOV64rm %vreg34, 1, %noreg, 64, %noreg; mem:LD8[%bzfree] GR64:%vreg33,%vreg34
720B		%vreg31<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg31
736B		%vreg30<def> = MOV64rm %vreg31, 1, %noreg, 72, %noreg; mem:LD8[%opaque] GR64:%vreg30,%vreg31
752B		%vreg28<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg28
768B		%vreg25<def> = MOV64rm %vreg28, 1, %noreg, 24, %noreg; mem:LD8[%arr110] GR64:%vreg25,%vreg28
800B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
816B		%RDI<def> = COPY %vreg30; GR64:%vreg30
832B		%RSI<def> = COPY %vreg25; GR64:%vreg25
848B		CALL64r %vreg33, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>; GR64:%vreg33
864B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
880B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
896B		STACKMAP 1, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1]
912B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#8

928B	BB#8: derived from LLVM BB %if.end.11
	    Predecessors according to CFG: BB#6 BB#7
944B		%vreg37<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg37
960B		CMP64mi8 %vreg37, 1, %noreg, 32, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%arr2] GR64:%vreg37
976B		JE_1 <BB#10>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#10 BB#9

992B	BB#9: derived from LLVM BB %if.then.13
	    Predecessors according to CFG: BB#8
1008B		%vreg51<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg51
1024B		%vreg50<def> = MOV64rm %vreg51, 1, %noreg, 64, %noreg; mem:LD8[%bzfree14] GR64:%vreg50,%vreg51
1040B		%vreg48<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg48
1056B		%vreg47<def> = MOV64rm %vreg48, 1, %noreg, 72, %noreg; mem:LD8[%opaque15] GR64:%vreg47,%vreg48
1072B		%vreg45<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg45
1088B		%vreg42<def> = MOV64rm %vreg45, 1, %noreg, 32, %noreg; mem:LD8[%arr216] GR64:%vreg42,%vreg45
1120B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1136B		%RDI<def> = COPY %vreg47; GR64:%vreg47
1152B		%RSI<def> = COPY %vreg42; GR64:%vreg42
1168B		CALL64r %vreg50, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>; GR64:%vreg50
1184B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1200B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1216B		STACKMAP 2, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1]
1232B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#10

1248B	BB#10: derived from LLVM BB %if.end.17
	    Predecessors according to CFG: BB#8 BB#9
1264B		%vreg54<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg54
1280B		CMP64mi8 %vreg54, 1, %noreg, 40, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%ftab] GR64:%vreg54
1296B		JE_1 <BB#12>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#12 BB#11

1312B	BB#11: derived from LLVM BB %if.then.19
	    Predecessors according to CFG: BB#10
1328B		%vreg68<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg68
1344B		%vreg67<def> = MOV64rm %vreg68, 1, %noreg, 64, %noreg; mem:LD8[%bzfree20] GR64:%vreg67,%vreg68
1360B		%vreg65<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg65
1376B		%vreg64<def> = MOV64rm %vreg65, 1, %noreg, 72, %noreg; mem:LD8[%opaque21] GR64:%vreg64,%vreg65
1392B		%vreg62<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg62
1408B		%vreg59<def> = MOV64rm %vreg62, 1, %noreg, 40, %noreg; mem:LD8[%ftab22] GR64:%vreg59,%vreg62
1440B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1456B		%RDI<def> = COPY %vreg64; GR64:%vreg64
1472B		%RSI<def> = COPY %vreg59; GR64:%vreg59
1488B		CALL64r %vreg67, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>; GR64:%vreg67
1504B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1520B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1536B		STACKMAP 3, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack1]
1552B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#12

1568B	BB#12: derived from LLVM BB %if.end.23
	    Predecessors according to CFG: BB#10 BB#11
1584B		%vreg82<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg82
1600B		%vreg81<def> = MOV64rm %vreg82, 1, %noreg, 64, %noreg; mem:LD8[%bzfree24] GR64:%vreg81,%vreg82
1616B		%vreg79<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg79
1632B		%vreg78<def> = MOV64rm %vreg79, 1, %noreg, 72, %noreg; mem:LD8[%opaque25] GR64:%vreg78,%vreg79
1648B		%vreg76<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg76
1664B		%vreg75<def> = MOV64rm %vreg76, 1, %noreg, 48, %noreg; mem:LD8[%state26] GR64:%vreg75,%vreg76
1680B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1696B		%RDI<def> = COPY %vreg78; GR64:%vreg78
1712B		%RSI<def> = COPY %vreg75; GR64:%vreg75
1728B		CALL64r %vreg81, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>; GR64:%vreg81
1744B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1760B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1776B		STACKMAP 4, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack1]
1792B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1808B		%vreg70<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg70
1824B		MOV64mi32 %vreg70, 1, %noreg, 48, %noreg, 0; mem:ST8[%state27] GR64:%vreg70
1840B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
	    Successors according to CFG: BB#13

1856B	BB#13: derived from LLVM BB %return
	    Predecessors according to CFG: BB#12 BB#5 BB#3 BB#1
1872B		%vreg86<def> = MOV64ri <ga:@BZ2_bzCompressEnd>; GR64:%vreg86
1904B		%vreg87<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg87
1920B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1936B		%RDI<def> = COPY %vreg86; GR64:%vreg86
1952B		%RSI<def> = COPY %vreg87; GR64:%vreg87
1968B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
1984B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2000B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2016B		STACKMAP 5, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
2032B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2048B		%vreg84<def> = MOV32rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD4[%retval] GR32:%vreg84
2064B		%EAX<def> = COPY %vreg84; GR32:%vreg84
2080B		RETQ %EAX<imp-use,kill>

# End machine code for function BZ2_bzCompressEnd.


selectOrSplit GR64:%vreg1 [16r,224r:0)  0@16r w=4.983553e-03
hints: %RDI
missed hint %RDI
assigning %vreg1 to %RBX: BH [16r,224r:0)  0@16r BL [16r,224r:0)  0@16r

selectOrSplit GR64:%vreg4 [48r,112r:0)  0@48r w=2.176724e-03
hints: %RDI
assigning %vreg4 to %RDI: DIL [48r,112r:0)  0@48r

selectOrSplit GR64:%vreg5 [80r,128r:0)  0@80r w=4.508928e-03
hints: %RSI
assigning %vreg5 to %RSI: SIL [80r,128r:0)  0@80r

selectOrSplit GR64:%vreg30 [736r,816r:0)  0@736r w=2.650919e-04
hints: %RDI
assigning %vreg30 to %RDI: DIL [736r,816r:0)  0@736r

selectOrSplit GR64:%vreg25 [768r,832r:0)  0@768r w=2.742330e-04
hints: %RSI
assigning %vreg25 to %RSI: SIL [768r,832r:0)  0@768r

selectOrSplit GR64:%vreg47 [1056r,1136r:0)  0@1056r w=2.650919e-04
hints: %RDI
assigning %vreg47 to %RDI: DIL [1056r,1136r:0)  0@1056r

selectOrSplit GR64:%vreg42 [1088r,1152r:0)  0@1088r w=2.742330e-04
hints: %RSI
assigning %vreg42 to %RSI: SIL [1088r,1152r:0)  0@1088r

selectOrSplit GR64:%vreg64 [1376r,1456r:0)  0@1376r w=2.650919e-04
hints: %RDI
assigning %vreg64 to %RDI: DIL [1376r,1456r:0)  0@1376r

selectOrSplit GR64:%vreg59 [1408r,1472r:0)  0@1408r w=2.742330e-04
hints: %RSI
assigning %vreg59 to %RSI: SIL [1408r,1472r:0)  0@1408r

selectOrSplit GR64:%vreg78 [1632r,1696r:0)  0@1632r w=5.141868e-04
hints: %RDI
assigning %vreg78 to %RDI: DIL [1632r,1696r:0)  0@1632r

selectOrSplit GR64:%vreg75 [1664r,1712r:0)  0@1664r w=5.325506e-04
hints: %RSI
assigning %vreg75 to %RSI: SIL [1664r,1712r:0)  0@1664r

selectOrSplit GR64:%vreg86 [1872r,1936r:0)  0@1872r w=2.176724e-03
hints: %RDI
assigning %vreg86 to %RDI: DIL [1872r,1936r:0)  0@1872r

selectOrSplit GR64:%vreg87 [1904r,1952r:0)  0@1904r w=4.508928e-03
hints: %RSI
assigning %vreg87 to %RSI: SIL [1904r,1952r:0)  0@1904r

selectOrSplit GR32:%vreg84 [2048r,2064r:0)  0@2048r w=inf
hints: %EAX
assigning %vreg84 to %EAX: AH [2048r,2064r:0)  0@2048r AL [2048r,2064r:0)  0@2048r

selectOrSplit GR64:%vreg12 [336r,352r:0)  0@336r w=inf
assigning %vreg12 to %RAX: AH [336r,352r:0)  0@336r AL [336r,352r:0)  0@336r

selectOrSplit GR64:%vreg9 [352r,384r:0)  0@352r w=inf
assigning %vreg9 to %RAX: AH [352r,384r:0)  0@352r AL [352r,384r:0)  0@352r

selectOrSplit GR64:%vreg17 [496r,512r:0)  0@496r w=inf
assigning %vreg17 to %RAX: AH [496r,512r:0)  0@496r AL [496r,512r:0)  0@496r

selectOrSplit GR64:%vreg16 [512r,528r:0)  0@512r w=inf
assigning %vreg16 to %RAX: AH [512r,528r:0)  0@512r AL [512r,528r:0)  0@512r

selectOrSplit GR64:%vreg20 [624r,640r:0)  0@624r w=inf
assigning %vreg20 to %RAX: AH [624r,640r:0)  0@624r AL [624r,640r:0)  0@624r

selectOrSplit GR64:%vreg34 [688r,704r:0)  0@688r w=inf
assigning %vreg34 to %RAX: AH [688r,704r:0)  0@688r AL [688r,704r:0)  0@688r

selectOrSplit GR64:%vreg33 [704r,848r:0)  0@704r w=2.315887e-04
assigning %vreg33 to %RAX: AH [704r,848r:0)  0@704r AL [704r,848r:0)  0@704r

selectOrSplit GR64:%vreg31 [720r,736r:0)  0@720r w=inf
assigning %vreg31 to %RCX: CH [720r,736r:0)  0@720r CL [720r,736r:0)  0@720r

selectOrSplit GR64:%vreg28 [752r,768r:0)  0@752r w=inf
assigning %vreg28 to %RCX: CH [752r,768r:0)  0@752r CL [752r,768r:0)  0@752r

selectOrSplit GR64:%vreg37 [944r,960r:0)  0@944r w=inf
assigning %vreg37 to %RAX: AH [944r,960r:0)  0@944r AL [944r,960r:0)  0@944r

selectOrSplit GR64:%vreg51 [1008r,1024r:0)  0@1008r w=inf
assigning %vreg51 to %RAX: AH [1008r,1024r:0)  0@1008r AL [1008r,1024r:0)  0@1008r

selectOrSplit GR64:%vreg50 [1024r,1168r:0)  0@1024r w=2.315887e-04
assigning %vreg50 to %RAX: AH [1024r,1168r:0)  0@1024r AL [1024r,1168r:0)  0@1024r

selectOrSplit GR64:%vreg48 [1040r,1056r:0)  0@1040r w=inf
assigning %vreg48 to %RCX: CH [1040r,1056r:0)  0@1040r CL [1040r,1056r:0)  0@1040r

selectOrSplit GR64:%vreg45 [1072r,1088r:0)  0@1072r w=inf
assigning %vreg45 to %RCX: CH [1072r,1088r:0)  0@1072r CL [1072r,1088r:0)  0@1072r

selectOrSplit GR64:%vreg54 [1264r,1280r:0)  0@1264r w=inf
assigning %vreg54 to %RAX: AH [1264r,1280r:0)  0@1264r AL [1264r,1280r:0)  0@1264r

selectOrSplit GR64:%vreg68 [1328r,1344r:0)  0@1328r w=inf
assigning %vreg68 to %RAX: AH [1328r,1344r:0)  0@1328r AL [1328r,1344r:0)  0@1328r

selectOrSplit GR64:%vreg67 [1344r,1488r:0)  0@1344r w=2.315887e-04
assigning %vreg67 to %RAX: AH [1344r,1488r:0)  0@1344r AL [1344r,1488r:0)  0@1344r

selectOrSplit GR64:%vreg65 [1360r,1376r:0)  0@1360r w=inf
assigning %vreg65 to %RCX: CH [1360r,1376r:0)  0@1360r CL [1360r,1376r:0)  0@1360r

selectOrSplit GR64:%vreg62 [1392r,1408r:0)  0@1392r w=inf
assigning %vreg62 to %RCX: CH [1392r,1408r:0)  0@1392r CL [1392r,1408r:0)  0@1392r

selectOrSplit GR64:%vreg82 [1584r,1600r:0)  0@1584r w=inf
assigning %vreg82 to %RAX: AH [1584r,1600r:0)  0@1584r AL [1584r,1600r:0)  0@1584r

selectOrSplit GR64:%vreg81 [1600r,1728r:0)  0@1600r w=4.473873e-04
assigning %vreg81 to %RAX: AH [1600r,1728r:0)  0@1600r AL [1600r,1728r:0)  0@1600r

selectOrSplit GR64:%vreg79 [1616r,1632r:0)  0@1616r w=inf
assigning %vreg79 to %RCX: CH [1616r,1632r:0)  0@1616r CL [1616r,1632r:0)  0@1616r

selectOrSplit GR64:%vreg76 [1648r,1664r:0)  0@1648r w=inf
assigning %vreg76 to %RCX: CH [1648r,1664r:0)  0@1648r CL [1648r,1664r:0)  0@1648r

selectOrSplit GR64:%vreg70 [1808r,1824r:0)  0@1808r w=inf
assigning %vreg70 to %RAX: AH [1808r,1824r:0)  0@1808r AL [1808r,1824r:0)  0@1808r

********** STACK TRANSFORMATION METADATA **********
********** Function: BZ2_bzCompressEnd
********** REGISTER MAP **********
[%vreg1 -> %RBX] GR64
[%vreg4 -> %RDI] GR64
[%vreg5 -> %RSI] GR64
[%vreg9 -> %RAX] GR64
[%vreg12 -> %RAX] GR64
[%vreg16 -> %RAX] GR64
[%vreg17 -> %RAX] GR64
[%vreg20 -> %RAX] GR64
[%vreg25 -> %RSI] GR64
[%vreg28 -> %RCX] GR64
[%vreg30 -> %RDI] GR64
[%vreg31 -> %RCX] GR64
[%vreg33 -> %RAX] GR64
[%vreg34 -> %RAX] GR64
[%vreg37 -> %RAX] GR64
[%vreg42 -> %RSI] GR64
[%vreg45 -> %RCX] GR64
[%vreg47 -> %RDI] GR64
[%vreg48 -> %RCX] GR64
[%vreg50 -> %RAX] GR64
[%vreg51 -> %RAX] GR64
[%vreg54 -> %RAX] GR64
[%vreg59 -> %RSI] GR64
[%vreg62 -> %RCX] GR64
[%vreg64 -> %RDI] GR64
[%vreg65 -> %RCX] GR64
[%vreg67 -> %RAX] GR64
[%vreg68 -> %RAX] GR64
[%vreg70 -> %RAX] GR64
[%vreg75 -> %RSI] GR64
[%vreg76 -> %RCX] GR64
[%vreg78 -> %RDI] GR64
[%vreg79 -> %RCX] GR64
[%vreg81 -> %RAX] GR64
[%vreg82 -> %RAX] GR64
[%vreg84 -> %EAX] GR32
[%vreg86 -> %RDI] GR64
[%vreg87 -> %RSI] GR64


Stackmap 0:
  STACKMAP 0, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, %vreg1, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1] GR64:%vreg1

i32* %retval: in stack slot 0 (size: 4)
%struct.EState** %s: in stack slot 2 (size: 8)
%struct.bz_stream* %strm: in register %RBX (vreg 1)
%struct.bz_stream** %strm.addr: in stack slot 1 (size: 8)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1]

i32* %retval: in stack slot 0 (size: 4)
%struct.EState** %s: in stack slot 2 (size: 8)
%struct.bz_stream** %strm.addr: in stack slot 1 (size: 8)

Duplicate operand locations:


Stackmap 2:
  STACKMAP 2, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1]

i32* %retval: in stack slot 0 (size: 4)
%struct.EState** %s: in stack slot 2 (size: 8)
%struct.bz_stream** %strm.addr: in stack slot 1 (size: 8)

Duplicate operand locations:


Stackmap 3:
  STACKMAP 3, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack1]

i32* %retval: in stack slot 0 (size: 4)
%struct.bz_stream** %strm.addr: in stack slot 1 (size: 8)

Duplicate operand locations:


Stackmap 4:
  STACKMAP 4, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack1]

i32* %retval: in stack slot 0 (size: 4)
%struct.bz_stream** %strm.addr: in stack slot 1 (size: 8)

Duplicate operand locations:


Stackmap 5:
  STACKMAP 5, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)

i32* %retval: in stack slot 0 (size: 4)

Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, %vreg1, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1] GR64:%vreg1
  -> Call instruction SlotIndex 144B, searching vregs 0 -> 88 and stack slots -1 -> 3

  STACKMAP 1, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1]
  -> Call instruction SlotIndex 848B, searching vregs 0 -> 88 and stack slots -1 -> 3

  STACKMAP 2, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1]
  -> Call instruction SlotIndex 1168B, searching vregs 0 -> 88 and stack slots -1 -> 3

  STACKMAP 3, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack1]
  -> Call instruction SlotIndex 1488B, searching vregs 0 -> 88 and stack slots -1 -> 3

  STACKMAP 4, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack1]
  -> Call instruction SlotIndex 1728B, searching vregs 0 -> 88 and stack slots -1 -> 3

  STACKMAP 5, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
  -> Call instruction SlotIndex 1968B, searching vregs 0 -> 88 and stack slots -1 -> 3

********** REWRITE VIRTUAL REGISTERS **********
********** Function: BZ2_bzCompressEnd
********** REGISTER MAP **********
[%vreg1 -> %RBX] GR64
[%vreg4 -> %RDI] GR64
[%vreg5 -> %RSI] GR64
[%vreg9 -> %RAX] GR64
[%vreg12 -> %RAX] GR64
[%vreg16 -> %RAX] GR64
[%vreg17 -> %RAX] GR64
[%vreg20 -> %RAX] GR64
[%vreg25 -> %RSI] GR64
[%vreg28 -> %RCX] GR64
[%vreg30 -> %RDI] GR64
[%vreg31 -> %RCX] GR64
[%vreg33 -> %RAX] GR64
[%vreg34 -> %RAX] GR64
[%vreg37 -> %RAX] GR64
[%vreg42 -> %RSI] GR64
[%vreg45 -> %RCX] GR64
[%vreg47 -> %RDI] GR64
[%vreg48 -> %RCX] GR64
[%vreg50 -> %RAX] GR64
[%vreg51 -> %RAX] GR64
[%vreg54 -> %RAX] GR64
[%vreg59 -> %RSI] GR64
[%vreg62 -> %RCX] GR64
[%vreg64 -> %RDI] GR64
[%vreg65 -> %RCX] GR64
[%vreg67 -> %RAX] GR64
[%vreg68 -> %RAX] GR64
[%vreg70 -> %RAX] GR64
[%vreg75 -> %RSI] GR64
[%vreg76 -> %RCX] GR64
[%vreg78 -> %RDI] GR64
[%vreg79 -> %RCX] GR64
[%vreg81 -> %RAX] GR64
[%vreg82 -> %RAX] GR64
[%vreg84 -> %EAX] GR32
[%vreg86 -> %RDI] GR64
[%vreg87 -> %RSI] GR64

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI
16B		%vreg1<def> = COPY %RDI; GR64:%vreg1
48B		%vreg4<def> = MOV64ri <ga:@BZ2_bzCompressEnd>; GR64:%vreg4
80B		%vreg5<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg5
96B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
112B		%RDI<def> = COPY %vreg4<kill>; GR64:%vreg4
128B		%RSI<def> = COPY %vreg5<kill>; GR64:%vreg5
144B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
160B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
192B		STACKMAP 0, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, %vreg1, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1] GR64:%vreg1
208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg1<kill>; mem:ST8[%strm.addr] GR64:%vreg1
240B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%strm.addr]
256B		JNE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1
> %RBX<def> = COPY %RDI
> %RDI<def> = MOV64ri <ga:@BZ2_bzCompressEnd>
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 0, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, %RBX, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %RBX<kill>; mem:ST8[%strm.addr]
> CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%strm.addr]
> JNE_1 <BB#2>, %EFLAGS<imp-use,kill>
272B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
288B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
304B		JMP_1 <BB#13>
	    Successors according to CFG: BB#13
> MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
> JMP_1 <BB#13>
320B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0
336B		%vreg12<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg12
352B		%vreg9<def> = MOV64rm %vreg12<kill>, 1, %noreg, 48, %noreg; mem:LD8[%state] GR64:%vreg9,%vreg12
384B		MOV64mr <fi#2>, 1, %noreg, 0, %noreg, %vreg9<kill>; mem:ST8[%s] GR64:%vreg9
400B		CMP64mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%s]
416B		JNE_1 <BB#4>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#4 BB#3
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 48, %noreg; mem:LD8[%state]
> MOV64mr <fi#2>, 1, %noreg, 0, %noreg, %RAX<kill>; mem:ST8[%s]
> CMP64mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%s]
> JNE_1 <BB#4>, %EFLAGS<imp-use,kill>
432B	BB#3: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#2
448B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
464B		JMP_1 <BB#13>
	    Successors according to CFG: BB#13
> MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
> JMP_1 <BB#13>
480B	BB#4: derived from LLVM BB %if.end.3
	    Predecessors according to CFG: BB#2
496B		%vreg17<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg17
512B		%vreg16<def> = MOV64rm %vreg17<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm4] GR64:%vreg16,%vreg17
528B		CMP64rm %vreg16<kill>, <fi#1>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD8[%strm.addr] GR64:%vreg16
544B		JE_1 <BB#6>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#6 BB#5
> %RAX<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm4]
> CMP64rm %RAX<kill>, <fi#1>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD8[%strm.addr]
> JE_1 <BB#6>, %EFLAGS<imp-use,kill>
560B	BB#5: derived from LLVM BB %if.then.6
	    Predecessors according to CFG: BB#4
576B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
592B		JMP_1 <BB#13>
	    Successors according to CFG: BB#13
> MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
> JMP_1 <BB#13>
608B	BB#6: derived from LLVM BB %if.end.7
	    Predecessors according to CFG: BB#4
624B		%vreg20<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg20
640B		CMP64mi8 %vreg20<kill>, 1, %noreg, 24, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%arr1] GR64:%vreg20
656B		JE_1 <BB#8>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#8 BB#7
> %RAX<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> CMP64mi8 %RAX<kill>, 1, %noreg, 24, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%arr1]
> JE_1 <BB#8>, %EFLAGS<imp-use,kill>
672B	BB#7: derived from LLVM BB %if.then.9
	    Predecessors according to CFG: BB#6
688B		%vreg34<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg34
704B		%vreg33<def> = MOV64rm %vreg34<kill>, 1, %noreg, 64, %noreg; mem:LD8[%bzfree] GR64:%vreg33,%vreg34
720B		%vreg31<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg31
736B		%vreg30<def> = MOV64rm %vreg31<kill>, 1, %noreg, 72, %noreg; mem:LD8[%opaque] GR64:%vreg30,%vreg31
752B		%vreg28<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg28
768B		%vreg25<def> = MOV64rm %vreg28<kill>, 1, %noreg, 24, %noreg; mem:LD8[%arr110] GR64:%vreg25,%vreg28
800B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
816B		%RDI<def> = COPY %vreg30<kill>; GR64:%vreg30
832B		%RSI<def> = COPY %vreg25<kill>; GR64:%vreg25
848B		CALL64r %vreg33<kill>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>; GR64:%vreg33
864B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
880B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
896B		STACKMAP 1, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1]
912B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#8
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 64, %noreg; mem:LD8[%bzfree]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr]
> %RDI<def> = MOV64rm %RCX<kill>, 1, %noreg, 72, %noreg; mem:LD8[%opaque]
> %RCX<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> %RSI<def> = MOV64rm %RCX<kill>, 1, %noreg, 24, %noreg; mem:LD8[%arr110]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64r %RAX<kill>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 1, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
928B	BB#8: derived from LLVM BB %if.end.11
	    Predecessors according to CFG: BB#6 BB#7
944B		%vreg37<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg37
960B		CMP64mi8 %vreg37<kill>, 1, %noreg, 32, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%arr2] GR64:%vreg37
976B		JE_1 <BB#10>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#10 BB#9
> %RAX<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> CMP64mi8 %RAX<kill>, 1, %noreg, 32, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%arr2]
> JE_1 <BB#10>, %EFLAGS<imp-use,kill>
992B	BB#9: derived from LLVM BB %if.then.13
	    Predecessors according to CFG: BB#8
1008B		%vreg51<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg51
1024B		%vreg50<def> = MOV64rm %vreg51<kill>, 1, %noreg, 64, %noreg; mem:LD8[%bzfree14] GR64:%vreg50,%vreg51
1040B		%vreg48<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg48
1056B		%vreg47<def> = MOV64rm %vreg48<kill>, 1, %noreg, 72, %noreg; mem:LD8[%opaque15] GR64:%vreg47,%vreg48
1072B		%vreg45<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg45
1088B		%vreg42<def> = MOV64rm %vreg45<kill>, 1, %noreg, 32, %noreg; mem:LD8[%arr216] GR64:%vreg42,%vreg45
1120B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1136B		%RDI<def> = COPY %vreg47<kill>; GR64:%vreg47
1152B		%RSI<def> = COPY %vreg42<kill>; GR64:%vreg42
1168B		CALL64r %vreg50<kill>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>; GR64:%vreg50
1184B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1200B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1216B		STACKMAP 2, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1]
1232B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#10
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 64, %noreg; mem:LD8[%bzfree14]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr]
> %RDI<def> = MOV64rm %RCX<kill>, 1, %noreg, 72, %noreg; mem:LD8[%opaque15]
> %RCX<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> %RSI<def> = MOV64rm %RCX<kill>, 1, %noreg, 32, %noreg; mem:LD8[%arr216]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64r %RAX<kill>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 2, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1248B	BB#10: derived from LLVM BB %if.end.17
	    Predecessors according to CFG: BB#8 BB#9
1264B		%vreg54<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg54
1280B		CMP64mi8 %vreg54<kill>, 1, %noreg, 40, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%ftab] GR64:%vreg54
1296B		JE_1 <BB#12>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#12 BB#11
> %RAX<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> CMP64mi8 %RAX<kill>, 1, %noreg, 40, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%ftab]
> JE_1 <BB#12>, %EFLAGS<imp-use,kill>
1312B	BB#11: derived from LLVM BB %if.then.19
	    Predecessors according to CFG: BB#10
1328B		%vreg68<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg68
1344B		%vreg67<def> = MOV64rm %vreg68<kill>, 1, %noreg, 64, %noreg; mem:LD8[%bzfree20] GR64:%vreg67,%vreg68
1360B		%vreg65<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg65
1376B		%vreg64<def> = MOV64rm %vreg65<kill>, 1, %noreg, 72, %noreg; mem:LD8[%opaque21] GR64:%vreg64,%vreg65
1392B		%vreg62<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg62
1408B		%vreg59<def> = MOV64rm %vreg62<kill>, 1, %noreg, 40, %noreg; mem:LD8[%ftab22] GR64:%vreg59,%vreg62
1440B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1456B		%RDI<def> = COPY %vreg64<kill>; GR64:%vreg64
1472B		%RSI<def> = COPY %vreg59<kill>; GR64:%vreg59
1488B		CALL64r %vreg67<kill>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>; GR64:%vreg67
1504B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1520B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1536B		STACKMAP 3, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack1]
1552B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#12
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 64, %noreg; mem:LD8[%bzfree20]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr]
> %RDI<def> = MOV64rm %RCX<kill>, 1, %noreg, 72, %noreg; mem:LD8[%opaque21]
> %RCX<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> %RSI<def> = MOV64rm %RCX<kill>, 1, %noreg, 40, %noreg; mem:LD8[%ftab22]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64r %RAX<kill>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 3, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack1]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1568B	BB#12: derived from LLVM BB %if.end.23
	    Predecessors according to CFG: BB#10 BB#11
1584B		%vreg82<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg82
1600B		%vreg81<def> = MOV64rm %vreg82<kill>, 1, %noreg, 64, %noreg; mem:LD8[%bzfree24] GR64:%vreg81,%vreg82
1616B		%vreg79<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg79
1632B		%vreg78<def> = MOV64rm %vreg79<kill>, 1, %noreg, 72, %noreg; mem:LD8[%opaque25] GR64:%vreg78,%vreg79
1648B		%vreg76<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg76
1664B		%vreg75<def> = MOV64rm %vreg76<kill>, 1, %noreg, 48, %noreg; mem:LD8[%state26] GR64:%vreg75,%vreg76
1680B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1696B		%RDI<def> = COPY %vreg78<kill>; GR64:%vreg78
1712B		%RSI<def> = COPY %vreg75<kill>; GR64:%vreg75
1728B		CALL64r %vreg81<kill>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>; GR64:%vreg81
1744B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1760B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1776B		STACKMAP 4, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack1]
1792B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1808B		%vreg70<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg70
1824B		MOV64mi32 %vreg70<kill>, 1, %noreg, 48, %noreg, 0; mem:ST8[%state27] GR64:%vreg70
1840B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
	    Successors according to CFG: BB#13
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 64, %noreg; mem:LD8[%bzfree24]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr]
> %RDI<def> = MOV64rm %RCX<kill>, 1, %noreg, 72, %noreg; mem:LD8[%opaque25]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr]
> %RSI<def> = MOV64rm %RCX<kill>, 1, %noreg, 48, %noreg; mem:LD8[%state26]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64r %RAX<kill>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 4, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack1]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr]
> MOV64mi32 %RAX<kill>, 1, %noreg, 48, %noreg, 0; mem:ST8[%state27]
> MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
1856B	BB#13: derived from LLVM BB %return
	    Predecessors according to CFG: BB#12 BB#5 BB#3 BB#1
1872B		%vreg86<def> = MOV64ri <ga:@BZ2_bzCompressEnd>; GR64:%vreg86
1904B		%vreg87<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg87
1920B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1936B		%RDI<def> = COPY %vreg86<kill>; GR64:%vreg86
1952B		%RSI<def> = COPY %vreg87<kill>; GR64:%vreg87
1968B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
1984B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2000B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2016B		STACKMAP 5, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
2032B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2048B		%vreg84<def> = MOV32rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD4[%retval] GR32:%vreg84
2064B		%EAX<def> = COPY %vreg84<kill>; GR32:%vreg84
2080B		RETQ %EAX<imp-use>
> %RDI<def> = MOV64ri <ga:@BZ2_bzCompressEnd>
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 5, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def> = MOV32rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD4[%retval]
> %EAX<def> = COPY %EAX<kill>
Deleting identity copy.
> RETQ %EAX<imp-use>
Computing live-in reg-units in ABI blocks.
0B	BB#0 DIL#0 SIL#0 DH#0 DL#0
Created 4 new intervals.
********** INTERVALS **********
DH [0B,16r:0)[1328r,1344r:1)  0@0B-phi 1@1328r
DIL [0B,48r:0)[176r,208r:3)[1296r,1344r:2)[2272r,2304r:1)  0@0B-phi 1@2272r 2@1296r 3@176r
DL [0B,16r:0)[1328r,1344r:1)  0@0B-phi 1@1328r
SIL [0B,32r:0)[192r,208r:3)[1312r,1344r:1)[2288r,2304r:2)  0@0B-phi 1@1312r 2@2288r 3@192r
%vreg0 [48r,64r:0)  0@48r
%vreg1 [64r,288r:0)  0@64r
%vreg2 [32r,80r:0)  0@32r
%vreg3 [80r,304r:0)  0@80r
%vreg4 [16r,96r:0)  0@16r
%vreg5 [96r,320r:0)  0@96r
%vreg7 [384r,448r:0)  0@384r
%vreg8 [112r,128r:0)  0@112r
%vreg9 [128r,176r:0)  0@128r
%vreg10 [144r,192r:0)  0@144r
%vreg18 [928r,944r:0)  0@928r
%vreg20 [992r,1024r:0)  0@992r
%vreg21 [1008r,1024r:0)  0@1008r
%vreg24 [1056r,1072r:0)  0@1056r
%vreg26 [1120r,1152r:0)  0@1120r
%vreg27 [1136r,1152r:0)  0@1136r
%vreg31 [1440r,1456r:0)  0@1440r
%vreg33 [1184r,1312r:0)  0@1184r
%vreg34 [1200r,1328r:0)  0@1200r
%vreg36 [1376r,1440r:0)  0@1376r
%vreg38 [1264r,1296r:0)  0@1264r
%vreg39 [1248r,1264r:0)  0@1248r
%vreg41 [1232r,1344r:0)  0@1232r
%vreg42 [1216r,1232r:0)  0@1216r
%vreg45 [2144r,2160r:0)  0@2144r
%vreg46 [2128r,2160r:0)  0@2128r
%vreg48 [2096r,2112r:0)  0@2096r
%vreg50 [2064r,2080r:0)  0@2064r
%vreg52 [2032r,2048r:0)  0@2032r
%vreg54 [2000r,2016r:0)  0@2000r
%vreg57 [1968r,1984r:0)  0@1968r
%vreg59 [1952r,1984r:0)  0@1952r
%vreg60 [1936r,1952r:0)  0@1936r
%vreg62 [1904r,1920r:0)  0@1904r
%vreg64 [1872r,1888r:0)  0@1872r
%vreg66 [1840r,1856r:0)  0@1840r
%vreg68 [1808r,1824r:0)  0@1808r
%vreg70 [1776r,1792r:0)  0@1776r
%vreg72 [1744r,1760r:0)  0@1744r
%vreg74 [1712r,1728r:0)  0@1712r
%vreg76 [1680r,1696r:0)  0@1680r
%vreg79 [1648r,1664r:0)  0@1648r
%vreg81 [1632r,1664r:0)  0@1632r
%vreg82 [1616r,1632r:0)  0@1616r
%vreg85 [1584r,1600r:0)  0@1584r
%vreg86 [1568r,1600r:0)  0@1568r
%vreg88 [2384r,2400r:0)  0@2384r
%vreg89 [2208r,2224r:0)  0@2208r
%vreg90 [2224r,2272r:0)  0@2224r
%vreg91 [2240r,2288r:0)  0@2240r
RegMasks: 208r 352r 1344r 2304r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzDecompressInit: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=4, align=4, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=4, align=4, at location [SP+8]
  fi#3: size=4, align=4, at location [SP+8]
  fi#4: size=8, align=8, at location [SP+8]
Function Live Ins: %RDI in %vreg0, %ESI in %vreg2, %EDX in %vreg4

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI %ESI %EDX
16B		%vreg4<def> = COPY %EDX; GR32:%vreg4
32B		%vreg2<def> = COPY %ESI; GR32:%vreg2
48B		%vreg0<def> = COPY %RDI; GR64:%vreg0
64B		%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
80B		%vreg3<def> = COPY %vreg2; GR32:%vreg3,%vreg2
96B		%vreg5<def> = COPY %vreg4; GR32:%vreg5,%vreg4
112B		%vreg8<def> = MOV64ri <ga:@BZ2_bzDecompressInit>; GR64:%vreg8
128B		%vreg9<def> = COPY %vreg8; GR64:%vreg9,%vreg8
144B		%vreg10<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg10
160B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		%RDI<def> = COPY %vreg9; GR64:%vreg9
192B		%RSI<def> = COPY %vreg10; GR64:%vreg10
208B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
224B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
240B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
256B		STACKMAP 0, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, %vreg5, 0, <fi#3>, 0, %vreg1, 0, <fi#1>, 0, %vreg3, 0, <fi#2>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack4] LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack2](align=4) GR32:%vreg5,%vreg3 GR64:%vreg1
272B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
288B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%strm.addr] GR64:%vreg1
304B		MOV32mr <fi#2>, 1, %noreg, 0, %noreg, %vreg3; mem:ST4[%verbosity.addr] GR32:%vreg3
320B		MOV32mr <fi#3>, 1, %noreg, 0, %noreg, %vreg5; mem:ST4[%small.addr] GR32:%vreg5
336B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
352B		CALL64pcrel32 <ga:@bz_config_ok>, <regmask>, %RSP<imp-use>, %EAX<imp-def>
368B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
384B		%vreg7<def> = COPY %EAX<kill>; GR32:%vreg7
400B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
416B		STACKMAP 1, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack4] LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack2](align=4)
432B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
448B		CMP32ri8 %vreg7, 0, %EFLAGS<imp-def>; GR32:%vreg7
464B		JNE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

480B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
496B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -9; mem:ST4[%retval]
512B		JMP_1 <BB#17>
	    Successors according to CFG: BB#17

528B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0
544B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%strm.addr]
560B		JNE_1 <BB#4>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#4 BB#3

576B	BB#3: derived from LLVM BB %if.then.1
	    Predecessors according to CFG: BB#2
592B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
608B		JMP_1 <BB#17>
	    Successors according to CFG: BB#17

624B	BB#4: derived from LLVM BB %if.end.2
	    Predecessors according to CFG: BB#2
640B		CMP32mi8 <fi#3>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%small.addr]
656B		JE_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#5

672B	BB#5: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#4
688B		CMP32mi8 <fi#3>, 1, %noreg, 0, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%small.addr]
704B		JE_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#6

720B	BB#6: derived from LLVM BB %if.then.5
	    Predecessors according to CFG: BB#5
736B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
752B		JMP_1 <BB#17>
	    Successors according to CFG: BB#17

768B	BB#7: derived from LLVM BB %if.end.6
	    Predecessors according to CFG: BB#4 BB#5
784B		CMP32mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%verbosity.addr]
800B		JL_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#8

816B	BB#8: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#7
832B		CMP32mi8 <fi#2>, 1, %noreg, 0, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%verbosity.addr]
848B		JLE_1 <BB#10>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#10 BB#9

864B	BB#9: derived from LLVM BB %if.then.9
	    Predecessors according to CFG: BB#7 BB#8
880B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
896B		JMP_1 <BB#17>
	    Successors according to CFG: BB#17

912B	BB#10: derived from LLVM BB %if.end.10
	    Predecessors according to CFG: BB#8
928B		%vreg18<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg18
944B		CMP64mi8 %vreg18, 1, %noreg, 56, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzalloc] GR64:%vreg18
960B		JNE_1 <BB#12>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#12 BB#11

976B	BB#11: derived from LLVM BB %if.then.12
	    Predecessors according to CFG: BB#10
992B		%vreg20<def> = MOV64ri <ga:@default_bzalloc>; GR64:%vreg20
1008B		%vreg21<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg21
1024B		MOV64mr %vreg21, 1, %noreg, 56, %noreg, %vreg20; mem:ST8[%bzalloc13] GR64:%vreg21,%vreg20
	    Successors according to CFG: BB#12

1040B	BB#12: derived from LLVM BB %if.end.14
	    Predecessors according to CFG: BB#10 BB#11
1056B		%vreg24<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg24
1072B		CMP64mi8 %vreg24, 1, %noreg, 64, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzfree] GR64:%vreg24
1088B		JNE_1 <BB#14>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#14 BB#13

1104B	BB#13: derived from LLVM BB %if.then.16
	    Predecessors according to CFG: BB#12
1120B		%vreg26<def> = MOV64ri <ga:@default_bzfree>; GR64:%vreg26
1136B		%vreg27<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg27
1152B		MOV64mr %vreg27, 1, %noreg, 64, %noreg, %vreg26; mem:ST8[%bzfree17] GR64:%vreg27,%vreg26
	    Successors according to CFG: BB#14

1168B	BB#14: derived from LLVM BB %if.end.18
	    Predecessors according to CFG: BB#12 BB#13
1184B		%vreg33<def> = MOV32ri 64144; GR32:%vreg33
1200B		%vreg34<def> = MOV32ri 1; GR32:%vreg34
1216B		%vreg42<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg42
1232B		%vreg41<def> = MOV64rm %vreg42, 1, %noreg, 56, %noreg; mem:LD8[%bzalloc19] GR64:%vreg41,%vreg42
1248B		%vreg39<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg39
1264B		%vreg38<def> = MOV64rm %vreg39, 1, %noreg, 72, %noreg; mem:LD8[%opaque] GR64:%vreg38,%vreg39
1280B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1296B		%RDI<def> = COPY %vreg38; GR64:%vreg38
1312B		%ESI<def> = COPY %vreg33; GR32:%vreg33
1328B		%EDX<def> = COPY %vreg34; GR32:%vreg34
1344B		CALL64r %vreg41, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %EDX<imp-use>, %RAX<imp-def>; GR64:%vreg41
1360B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1376B		%vreg36<def> = COPY %RAX<kill>; GR64:%vreg36
1392B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1408B		STACKMAP 2, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack4] LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack2](align=4)
1424B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1440B		%vreg31<def> = COPY %vreg36; GR64:%vreg31,%vreg36
1456B		MOV64mr <fi#4>, 1, %noreg, 0, %noreg, %vreg31; mem:ST8[%s] GR64:%vreg31
1472B		CMP64mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%s]
1488B		JNE_1 <BB#16>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#16 BB#15

1504B	BB#15: derived from LLVM BB %if.then.22
	    Predecessors according to CFG: BB#14
1520B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -3; mem:ST4[%retval]
1536B		JMP_1 <BB#17>
	    Successors according to CFG: BB#17

1552B	BB#16: derived from LLVM BB %if.end.23
	    Predecessors according to CFG: BB#14
1568B		%vreg86<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg86
1584B		%vreg85<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg85
1600B		MOV64mr %vreg85, 1, %noreg, 0, %noreg, %vreg86; mem:ST8[%strm24] GR64:%vreg85,%vreg86
1616B		%vreg82<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg82
1632B		%vreg81<def> = COPY %vreg82; GR64:%vreg81,%vreg82
1648B		%vreg79<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg79
1664B		MOV64mr %vreg79, 1, %noreg, 48, %noreg, %vreg81; mem:ST8[%state] GR64:%vreg79,%vreg81
1680B		%vreg76<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg76
1696B		MOV32mi %vreg76, 1, %noreg, 8, %noreg, 10; mem:ST4[%state25] GR64:%vreg76
1712B		%vreg74<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg74
1728B		MOV32mi %vreg74, 1, %noreg, 36, %noreg, 0; mem:ST4[%bsLive] GR64:%vreg74
1744B		%vreg72<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg72
1760B		MOV32mi %vreg72, 1, %noreg, 32, %noreg, 0; mem:ST4[%bsBuff] GR64:%vreg72
1776B		%vreg70<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg70
1792B		MOV32mi %vreg70, 1, %noreg, 3188, %noreg, 0; mem:ST4[%calculatedCombinedCRC] GR64:%vreg70
1808B		%vreg68<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg68
1824B		MOV32mi %vreg68, 1, %noreg, 12, %noreg, 0; mem:ST4[%total_in_lo32] GR64:%vreg68
1840B		%vreg66<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg66
1856B		MOV32mi %vreg66, 1, %noreg, 16, %noreg, 0; mem:ST4[%total_in_hi32] GR64:%vreg66
1872B		%vreg64<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg64
1888B		MOV32mi %vreg64, 1, %noreg, 36, %noreg, 0; mem:ST4[%total_out_lo32] GR64:%vreg64
1904B		%vreg62<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg62
1920B		MOV32mi %vreg62, 1, %noreg, 40, %noreg, 0; mem:ST4[%total_out_hi32] GR64:%vreg62
1936B		%vreg60<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%small.addr] GR32:%vreg60
1952B		%vreg59<def> = COPY %vreg60:sub_8bit; GR8:%vreg59 GR32:%vreg60
1968B		%vreg57<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg57
1984B		MOV8mr %vreg57, 1, %noreg, 44, %noreg, %vreg59; mem:ST1[%smallDecompress] GR64:%vreg57 GR8:%vreg59
2000B		%vreg54<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg54
2016B		MOV64mi32 %vreg54, 1, %noreg, 3168, %noreg, 0; mem:ST8[%ll4] GR64:%vreg54
2032B		%vreg52<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg52
2048B		MOV64mi32 %vreg52, 1, %noreg, 3160, %noreg, 0; mem:ST8[%ll16] GR64:%vreg52
2064B		%vreg50<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg50
2080B		MOV64mi32 %vreg50, 1, %noreg, 3152, %noreg, 0; mem:ST8[%tt] GR64:%vreg50
2096B		%vreg48<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg48
2112B		MOV32mi %vreg48, 1, %noreg, 48, %noreg, 0; mem:ST4[%currBlockNo] GR64:%vreg48
2128B		%vreg46<def> = MOV32rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD4[%verbosity.addr] GR32:%vreg46
2144B		%vreg45<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg45
2160B		MOV32mr %vreg45, 1, %noreg, 52, %noreg, %vreg46; mem:ST4[%verbosity26] GR64:%vreg45 GR32:%vreg46
2176B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
	    Successors according to CFG: BB#17

2192B	BB#17: derived from LLVM BB %return
	    Predecessors according to CFG: BB#1 BB#16 BB#15 BB#9 BB#6 BB#3
2208B		%vreg89<def> = MOV64ri <ga:@BZ2_bzDecompressInit>; GR64:%vreg89
2224B		%vreg90<def> = COPY %vreg89; GR64:%vreg90,%vreg89
2240B		%vreg91<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg91
2256B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2272B		%RDI<def> = COPY %vreg90; GR64:%vreg90
2288B		%RSI<def> = COPY %vreg91; GR64:%vreg91
2304B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
2320B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2336B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2352B		STACKMAP 3, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
2368B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2384B		%vreg88<def> = MOV32rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD4[%retval] GR32:%vreg88
2400B		%EAX<def> = COPY %vreg88; GR32:%vreg88
2416B		RETQ %EAX<imp-use,kill>

# End machine code for function BZ2_bzDecompressInit.

********** SIMPLE REGISTER COALESCING **********
********** Function: BZ2_bzDecompressInit
********** JOINING INTERVALS ***********
return:
2272B	%RDI<def> = COPY %vreg90; GR64:%vreg90
	Considering merging %vreg90 with %RDI
	Can only merge into reserved registers.
2288B	%RSI<def> = COPY %vreg91; GR64:%vreg91
	Considering merging %vreg91 with %RSI
	Can only merge into reserved registers.
2400B	%EAX<def> = COPY %vreg88; GR32:%vreg88
	Considering merging %vreg88 with %EAX
	Can only merge into reserved registers.
if.end.6:
if.end.14:
if.end.18:
1296B	%RDI<def> = COPY %vreg38; GR64:%vreg38
	Considering merging %vreg38 with %RDI
	Can only merge into reserved registers.
1312B	%ESI<def> = COPY %vreg33; GR32:%vreg33
	Considering merging %vreg33 with %ESI
	Can only merge into reserved registers.
Remat: %ESI<def> = MOV32ri 64144
Shrink: %vreg33 [1184r,1312r:0)  0@1184r
All defs dead: 1184r	%vreg33<def,dead> = MOV32ri 64144; GR32:%vreg33
Shrunk: %vreg33 [1184r,1184d:0)  0@1184r
Deleting dead def 1184r	%vreg33<def,dead> = MOV32ri 64144; GR32:%vreg33
1328B	%EDX<def> = COPY %vreg34; GR32:%vreg34
	Considering merging %vreg34 with %EDX
	Can only merge into reserved registers.
Remat: %EDX<def> = MOV32ri 1
Shrink: %vreg34 [1200r,1328r:0)  0@1200r
All defs dead: 1200r	%vreg34<def,dead> = MOV32ri 1; GR32:%vreg34
Shrunk: %vreg34 [1200r,1200d:0)  0@1200r
Deleting dead def 1200r	%vreg34<def,dead> = MOV32ri 1; GR32:%vreg34
1376B	%vreg36<def> = COPY %RAX<kill>; GR64:%vreg36
	Considering merging %vreg36 with %RAX
	Can only merge into reserved registers.
if.end:
if.end.2:
land.lhs.true:
lor.lhs.false:
if.then.9:
if.end.10:
entry:
16B	%vreg4<def> = COPY %EDX; GR32:%vreg4
	Considering merging %vreg4 with %EDX
	Can only merge into reserved registers.
32B	%vreg2<def> = COPY %ESI; GR32:%vreg2
	Considering merging %vreg2 with %ESI
	Can only merge into reserved registers.
48B	%vreg0<def> = COPY %RDI; GR64:%vreg0
	Considering merging %vreg0 with %RDI
	Can only merge into reserved registers.
176B	%RDI<def> = COPY %vreg9; GR64:%vreg9
	Considering merging %vreg9 with %RDI
	Can only merge into reserved registers.
192B	%RSI<def> = COPY %vreg10; GR64:%vreg10
	Considering merging %vreg10 with %RSI
	Can only merge into reserved registers.
384B	%vreg7<def> = COPY %EAX<kill>; GR32:%vreg7
	Considering merging %vreg7 with %EAX
	Can only merge into reserved registers.
if.then:
if.then.1:
if.then.5:
if.then.12:
if.then.16:
if.then.22:
if.end.23:
2224B	%vreg90<def> = COPY %vreg89; GR64:%vreg90,%vreg89
	Considering merging to GR64 with %vreg89 in %vreg90
		RHS = %vreg89 [2208r,2224r:0)  0@2208r
		LHS = %vreg90 [2224r,2272r:0)  0@2224r
		merge %vreg90:0@2224r into %vreg89:0@2208r --> @2208r
		erased:	2224r	%vreg90<def> = COPY %vreg89; GR64:%vreg90,%vreg89
		updated: 2208B	%vreg90<def> = MOV64ri <ga:@BZ2_bzDecompressInit>; GR64:%vreg90
	Success: %vreg89 -> %vreg90
	Result = %vreg90 [2208r,2272r:0)  0@2208r
1440B	%vreg31<def> = COPY %vreg36; GR64:%vreg31,%vreg36
	Considering merging to GR64 with %vreg36 in %vreg31
		RHS = %vreg36 [1376r,1440r:0)  0@1376r
		LHS = %vreg31 [1440r,1456r:0)  0@1440r
		merge %vreg31:0@1440r into %vreg36:0@1376r --> @1376r
		erased:	1440r	%vreg31<def> = COPY %vreg36; GR64:%vreg31,%vreg36
		updated: 1376B	%vreg31<def> = COPY %RAX<kill>; GR64:%vreg31
	Success: %vreg36 -> %vreg31
	Result = %vreg31 [1376r,1456r:0)  0@1376r
64B	%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
	Considering merging to GR64 with %vreg0 in %vreg1
		RHS = %vreg0 [48r,64r:0)  0@48r
		LHS = %vreg1 [64r,288r:0)  0@64r
		merge %vreg1:0@64r into %vreg0:0@48r --> @48r
		erased:	64r	%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
		updated: 48B	%vreg1<def> = COPY %RDI; GR64:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [48r,288r:0)  0@48r
80B	%vreg3<def> = COPY %vreg2; GR32:%vreg3,%vreg2
	Considering merging to GR32 with %vreg2 in %vreg3
		RHS = %vreg2 [32r,80r:0)  0@32r
		LHS = %vreg3 [80r,304r:0)  0@80r
		merge %vreg3:0@80r into %vreg2:0@32r --> @32r
		erased:	80r	%vreg3<def> = COPY %vreg2; GR32:%vreg3,%vreg2
		updated: 32B	%vreg3<def> = COPY %ESI; GR32:%vreg3
	Success: %vreg2 -> %vreg3
	Result = %vreg3 [32r,304r:0)  0@32r
96B	%vreg5<def> = COPY %vreg4; GR32:%vreg5,%vreg4
	Considering merging to GR32 with %vreg4 in %vreg5
		RHS = %vreg4 [16r,96r:0)  0@16r
		LHS = %vreg5 [96r,320r:0)  0@96r
		merge %vreg5:0@96r into %vreg4:0@16r --> @16r
		erased:	96r	%vreg5<def> = COPY %vreg4; GR32:%vreg5,%vreg4
		updated: 16B	%vreg5<def> = COPY %EDX; GR32:%vreg5
	Success: %vreg4 -> %vreg5
	Result = %vreg5 [16r,320r:0)  0@16r
128B	%vreg9<def> = COPY %vreg8; GR64:%vreg9,%vreg8
	Considering merging to GR64 with %vreg8 in %vreg9
		RHS = %vreg8 [112r,128r:0)  0@112r
		LHS = %vreg9 [128r,176r:0)  0@128r
		merge %vreg9:0@128r into %vreg8:0@112r --> @112r
		erased:	128r	%vreg9<def> = COPY %vreg8; GR64:%vreg9,%vreg8
		updated: 112B	%vreg9<def> = MOV64ri <ga:@BZ2_bzDecompressInit>; GR64:%vreg9
	Success: %vreg8 -> %vreg9
	Result = %vreg9 [112r,176r:0)  0@112r
1632B	%vreg81<def> = COPY %vreg82; GR64:%vreg81,%vreg82
	Considering merging to GR64 with %vreg82 in %vreg81
		RHS = %vreg82 [1616r,1632r:0)  0@1616r
		LHS = %vreg81 [1632r,1664r:0)  0@1632r
		merge %vreg81:0@1632r into %vreg82:0@1616r --> @1616r
		erased:	1632r	%vreg81<def> = COPY %vreg82; GR64:%vreg81,%vreg82
		updated: 1616B	%vreg81<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg81
	Success: %vreg82 -> %vreg81
	Result = %vreg81 [1616r,1664r:0)  0@1616r
1952B	%vreg59<def> = COPY %vreg60:sub_8bit; GR8:%vreg59 GR32:%vreg60
	Considering merging to GR32 with %vreg59 in %vreg60:sub_8bit
		RHS = %vreg59 [1952r,1984r:0)  0@1952r
		LHS = %vreg60 [1936r,1952r:0)  0@1936r
		merge %vreg59:0@1952r into %vreg60:0@1936r --> @1936r
		erased:	1952r	%vreg59<def> = COPY %vreg60:sub_8bit; GR8:%vreg59 GR32:%vreg60
		updated: 1984B	MOV8mr %vreg57, 1, %noreg, 44, %noreg, %vreg60:sub_8bit; mem:ST1[%smallDecompress] GR64:%vreg57 GR32:%vreg60
	Success: %vreg59:sub_8bit -> %vreg60
	Result = %vreg60 [1936r,1984r:0)  0@1936r
2272B	%RDI<def> = COPY %vreg90; GR64:%vreg90
	Considering merging %vreg90 with %RDI
	Can only merge into reserved registers.
176B	%RDI<def> = COPY %vreg9; GR64:%vreg9
	Considering merging %vreg9 with %RDI
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
DH [0B,16r:0)[1328r,1344r:1)  0@0B-phi 1@1328r
DIL [0B,48r:0)[176r,208r:3)[1296r,1344r:2)[2272r,2304r:1)  0@0B-phi 1@2272r 2@1296r 3@176r
DL [0B,16r:0)[1328r,1344r:1)  0@0B-phi 1@1328r
SIL [0B,32r:0)[192r,208r:3)[1312r,1344r:1)[2288r,2304r:2)  0@0B-phi 1@1312r 2@2288r 3@192r
%vreg1 [48r,288r:0)  0@48r
%vreg3 [32r,304r:0)  0@32r
%vreg5 [16r,320r:0)  0@16r
%vreg7 [384r,448r:0)  0@384r
%vreg9 [112r,176r:0)  0@112r
%vreg10 [144r,192r:0)  0@144r
%vreg18 [928r,944r:0)  0@928r
%vreg20 [992r,1024r:0)  0@992r
%vreg21 [1008r,1024r:0)  0@1008r
%vreg24 [1056r,1072r:0)  0@1056r
%vreg26 [1120r,1152r:0)  0@1120r
%vreg27 [1136r,1152r:0)  0@1136r
%vreg31 [1376r,1456r:0)  0@1376r
%vreg38 [1264r,1296r:0)  0@1264r
%vreg39 [1248r,1264r:0)  0@1248r
%vreg41 [1232r,1344r:0)  0@1232r
%vreg42 [1216r,1232r:0)  0@1216r
%vreg45 [2144r,2160r:0)  0@2144r
%vreg46 [2128r,2160r:0)  0@2128r
%vreg48 [2096r,2112r:0)  0@2096r
%vreg50 [2064r,2080r:0)  0@2064r
%vreg52 [2032r,2048r:0)  0@2032r
%vreg54 [2000r,2016r:0)  0@2000r
%vreg57 [1968r,1984r:0)  0@1968r
%vreg60 [1936r,1984r:0)  0@1936r
%vreg62 [1904r,1920r:0)  0@1904r
%vreg64 [1872r,1888r:0)  0@1872r
%vreg66 [1840r,1856r:0)  0@1840r
%vreg68 [1808r,1824r:0)  0@1808r
%vreg70 [1776r,1792r:0)  0@1776r
%vreg72 [1744r,1760r:0)  0@1744r
%vreg74 [1712r,1728r:0)  0@1712r
%vreg76 [1680r,1696r:0)  0@1680r
%vreg79 [1648r,1664r:0)  0@1648r
%vreg81 [1616r,1664r:0)  0@1616r
%vreg85 [1584r,1600r:0)  0@1584r
%vreg86 [1568r,1600r:0)  0@1568r
%vreg88 [2384r,2400r:0)  0@2384r
%vreg90 [2208r,2272r:0)  0@2208r
%vreg91 [2240r,2288r:0)  0@2240r
RegMasks: 208r 352r 1344r 2304r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzDecompressInit: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=4, align=4, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=4, align=4, at location [SP+8]
  fi#3: size=4, align=4, at location [SP+8]
  fi#4: size=8, align=8, at location [SP+8]
Function Live Ins: %RDI in %vreg0, %ESI in %vreg2, %EDX in %vreg4

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI %ESI %EDX
16B		%vreg5<def> = COPY %EDX; GR32:%vreg5
32B		%vreg3<def> = COPY %ESI; GR32:%vreg3
48B		%vreg1<def> = COPY %RDI; GR64:%vreg1
112B		%vreg9<def> = MOV64ri <ga:@BZ2_bzDecompressInit>; GR64:%vreg9
144B		%vreg10<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg10
160B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		%RDI<def> = COPY %vreg9; GR64:%vreg9
192B		%RSI<def> = COPY %vreg10; GR64:%vreg10
208B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
224B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
240B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
256B		STACKMAP 0, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, %vreg5, 0, <fi#3>, 0, %vreg1, 0, <fi#1>, 0, %vreg3, 0, <fi#2>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack4] LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack2](align=4) GR32:%vreg5,%vreg3 GR64:%vreg1
272B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
288B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%strm.addr] GR64:%vreg1
304B		MOV32mr <fi#2>, 1, %noreg, 0, %noreg, %vreg3; mem:ST4[%verbosity.addr] GR32:%vreg3
320B		MOV32mr <fi#3>, 1, %noreg, 0, %noreg, %vreg5; mem:ST4[%small.addr] GR32:%vreg5
336B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
352B		CALL64pcrel32 <ga:@bz_config_ok>, <regmask>, %RSP<imp-use>, %EAX<imp-def>
368B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
384B		%vreg7<def> = COPY %EAX<kill>; GR32:%vreg7
400B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
416B		STACKMAP 1, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack4] LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack2](align=4)
432B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
448B		CMP32ri8 %vreg7, 0, %EFLAGS<imp-def>; GR32:%vreg7
464B		JNE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

480B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
496B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -9; mem:ST4[%retval]
512B		JMP_1 <BB#17>
	    Successors according to CFG: BB#17

528B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0
544B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%strm.addr]
560B		JNE_1 <BB#4>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#4 BB#3

576B	BB#3: derived from LLVM BB %if.then.1
	    Predecessors according to CFG: BB#2
592B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
608B		JMP_1 <BB#17>
	    Successors according to CFG: BB#17

624B	BB#4: derived from LLVM BB %if.end.2
	    Predecessors according to CFG: BB#2
640B		CMP32mi8 <fi#3>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%small.addr]
656B		JE_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#5

672B	BB#5: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#4
688B		CMP32mi8 <fi#3>, 1, %noreg, 0, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%small.addr]
704B		JE_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#6

720B	BB#6: derived from LLVM BB %if.then.5
	    Predecessors according to CFG: BB#5
736B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
752B		JMP_1 <BB#17>
	    Successors according to CFG: BB#17

768B	BB#7: derived from LLVM BB %if.end.6
	    Predecessors according to CFG: BB#4 BB#5
784B		CMP32mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%verbosity.addr]
800B		JL_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#8

816B	BB#8: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#7
832B		CMP32mi8 <fi#2>, 1, %noreg, 0, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%verbosity.addr]
848B		JLE_1 <BB#10>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#10 BB#9

864B	BB#9: derived from LLVM BB %if.then.9
	    Predecessors according to CFG: BB#7 BB#8
880B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
896B		JMP_1 <BB#17>
	    Successors according to CFG: BB#17

912B	BB#10: derived from LLVM BB %if.end.10
	    Predecessors according to CFG: BB#8
928B		%vreg18<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg18
944B		CMP64mi8 %vreg18, 1, %noreg, 56, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzalloc] GR64:%vreg18
960B		JNE_1 <BB#12>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#12 BB#11

976B	BB#11: derived from LLVM BB %if.then.12
	    Predecessors according to CFG: BB#10
992B		%vreg20<def> = MOV64ri <ga:@default_bzalloc>; GR64:%vreg20
1008B		%vreg21<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg21
1024B		MOV64mr %vreg21, 1, %noreg, 56, %noreg, %vreg20; mem:ST8[%bzalloc13] GR64:%vreg21,%vreg20
	    Successors according to CFG: BB#12

1040B	BB#12: derived from LLVM BB %if.end.14
	    Predecessors according to CFG: BB#10 BB#11
1056B		%vreg24<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg24
1072B		CMP64mi8 %vreg24, 1, %noreg, 64, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzfree] GR64:%vreg24
1088B		JNE_1 <BB#14>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#14 BB#13

1104B	BB#13: derived from LLVM BB %if.then.16
	    Predecessors according to CFG: BB#12
1120B		%vreg26<def> = MOV64ri <ga:@default_bzfree>; GR64:%vreg26
1136B		%vreg27<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg27
1152B		MOV64mr %vreg27, 1, %noreg, 64, %noreg, %vreg26; mem:ST8[%bzfree17] GR64:%vreg27,%vreg26
	    Successors according to CFG: BB#14

1168B	BB#14: derived from LLVM BB %if.end.18
	    Predecessors according to CFG: BB#12 BB#13
1216B		%vreg42<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg42
1232B		%vreg41<def> = MOV64rm %vreg42, 1, %noreg, 56, %noreg; mem:LD8[%bzalloc19] GR64:%vreg41,%vreg42
1248B		%vreg39<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg39
1264B		%vreg38<def> = MOV64rm %vreg39, 1, %noreg, 72, %noreg; mem:LD8[%opaque] GR64:%vreg38,%vreg39
1280B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1296B		%RDI<def> = COPY %vreg38; GR64:%vreg38
1312B		%ESI<def> = MOV32ri 64144
1328B		%EDX<def> = MOV32ri 1
1344B		CALL64r %vreg41, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %EDX<imp-use>, %RAX<imp-def>; GR64:%vreg41
1360B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1376B		%vreg31<def> = COPY %RAX<kill>; GR64:%vreg31
1392B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1408B		STACKMAP 2, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack4] LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack2](align=4)
1424B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1456B		MOV64mr <fi#4>, 1, %noreg, 0, %noreg, %vreg31; mem:ST8[%s] GR64:%vreg31
1472B		CMP64mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%s]
1488B		JNE_1 <BB#16>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#16 BB#15

1504B	BB#15: derived from LLVM BB %if.then.22
	    Predecessors according to CFG: BB#14
1520B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -3; mem:ST4[%retval]
1536B		JMP_1 <BB#17>
	    Successors according to CFG: BB#17

1552B	BB#16: derived from LLVM BB %if.end.23
	    Predecessors according to CFG: BB#14
1568B		%vreg86<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg86
1584B		%vreg85<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg85
1600B		MOV64mr %vreg85, 1, %noreg, 0, %noreg, %vreg86; mem:ST8[%strm24] GR64:%vreg85,%vreg86
1616B		%vreg81<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg81
1648B		%vreg79<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg79
1664B		MOV64mr %vreg79, 1, %noreg, 48, %noreg, %vreg81; mem:ST8[%state] GR64:%vreg79,%vreg81
1680B		%vreg76<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg76
1696B		MOV32mi %vreg76, 1, %noreg, 8, %noreg, 10; mem:ST4[%state25] GR64:%vreg76
1712B		%vreg74<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg74
1728B		MOV32mi %vreg74, 1, %noreg, 36, %noreg, 0; mem:ST4[%bsLive] GR64:%vreg74
1744B		%vreg72<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg72
1760B		MOV32mi %vreg72, 1, %noreg, 32, %noreg, 0; mem:ST4[%bsBuff] GR64:%vreg72
1776B		%vreg70<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg70
1792B		MOV32mi %vreg70, 1, %noreg, 3188, %noreg, 0; mem:ST4[%calculatedCombinedCRC] GR64:%vreg70
1808B		%vreg68<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg68
1824B		MOV32mi %vreg68, 1, %noreg, 12, %noreg, 0; mem:ST4[%total_in_lo32] GR64:%vreg68
1840B		%vreg66<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg66
1856B		MOV32mi %vreg66, 1, %noreg, 16, %noreg, 0; mem:ST4[%total_in_hi32] GR64:%vreg66
1872B		%vreg64<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg64
1888B		MOV32mi %vreg64, 1, %noreg, 36, %noreg, 0; mem:ST4[%total_out_lo32] GR64:%vreg64
1904B		%vreg62<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg62
1920B		MOV32mi %vreg62, 1, %noreg, 40, %noreg, 0; mem:ST4[%total_out_hi32] GR64:%vreg62
1936B		%vreg60<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%small.addr] GR32:%vreg60
1968B		%vreg57<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg57
1984B		MOV8mr %vreg57, 1, %noreg, 44, %noreg, %vreg60:sub_8bit; mem:ST1[%smallDecompress] GR64:%vreg57 GR32:%vreg60
2000B		%vreg54<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg54
2016B		MOV64mi32 %vreg54, 1, %noreg, 3168, %noreg, 0; mem:ST8[%ll4] GR64:%vreg54
2032B		%vreg52<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg52
2048B		MOV64mi32 %vreg52, 1, %noreg, 3160, %noreg, 0; mem:ST8[%ll16] GR64:%vreg52
2064B		%vreg50<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg50
2080B		MOV64mi32 %vreg50, 1, %noreg, 3152, %noreg, 0; mem:ST8[%tt] GR64:%vreg50
2096B		%vreg48<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg48
2112B		MOV32mi %vreg48, 1, %noreg, 48, %noreg, 0; mem:ST4[%currBlockNo] GR64:%vreg48
2128B		%vreg46<def> = MOV32rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD4[%verbosity.addr] GR32:%vreg46
2144B		%vreg45<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg45
2160B		MOV32mr %vreg45, 1, %noreg, 52, %noreg, %vreg46; mem:ST4[%verbosity26] GR64:%vreg45 GR32:%vreg46
2176B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
	    Successors according to CFG: BB#17

2192B	BB#17: derived from LLVM BB %return
	    Predecessors according to CFG: BB#1 BB#16 BB#15 BB#9 BB#6 BB#3
2208B		%vreg90<def> = MOV64ri <ga:@BZ2_bzDecompressInit>; GR64:%vreg90
2240B		%vreg91<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg91
2256B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2272B		%RDI<def> = COPY %vreg90; GR64:%vreg90
2288B		%RSI<def> = COPY %vreg91; GR64:%vreg91
2304B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
2320B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2336B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2352B		STACKMAP 3, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
2368B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2384B		%vreg88<def> = MOV32rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD4[%retval] GR32:%vreg88
2400B		%EAX<def> = COPY %vreg88; GR32:%vreg88
2416B		RETQ %EAX<imp-use,kill>

# End machine code for function BZ2_bzDecompressInit.

handleMove 1296B -> 1336B: %RDI<def> = COPY %vreg38; GR64:%vreg38
     DIL:	[0B,48r:0)[176r,208r:3)[1296r,1344r:2)[2272r,2304r:1)  0@0B-phi 1@2272r 2@1296r 3@176r
        -->	[0B,48r:0)[176r,208r:3)[1336r,1344r:2)[2272r,2304r:1)  0@0B-phi 1@2272r 2@1336r 3@176r
     %vreg38:	[1264r,1296r:0)  0@1264r
        -->	[1264r,1336r:0)  0@1264r
AllocationOrder(SEGMENT_REG) = [ ]
********** GREEDY REGISTER ALLOCATION **********
********** Function: BZ2_bzDecompressInit
********** INTERVALS **********
DH [0B,16r:0)[1328r,1344r:1)  0@0B-phi 1@1328r
DIL [0B,48r:0)[176r,208r:3)[1336r,1344r:2)[2272r,2304r:1)  0@0B-phi 1@2272r 2@1336r 3@176r
DL [0B,16r:0)[1328r,1344r:1)  0@0B-phi 1@1328r
SIL [0B,32r:0)[192r,208r:3)[1312r,1344r:1)[2288r,2304r:2)  0@0B-phi 1@1312r 2@2288r 3@192r
%vreg1 [48r,288r:0)  0@48r
%vreg3 [32r,304r:0)  0@32r
%vreg5 [16r,320r:0)  0@16r
%vreg7 [384r,448r:0)  0@384r
%vreg9 [112r,176r:0)  0@112r
%vreg10 [144r,192r:0)  0@144r
%vreg18 [928r,944r:0)  0@928r
%vreg20 [992r,1024r:0)  0@992r
%vreg21 [1008r,1024r:0)  0@1008r
%vreg24 [1056r,1072r:0)  0@1056r
%vreg26 [1120r,1152r:0)  0@1120r
%vreg27 [1136r,1152r:0)  0@1136r
%vreg31 [1376r,1456r:0)  0@1376r
%vreg38 [1264r,1336r:0)  0@1264r
%vreg39 [1248r,1264r:0)  0@1248r
%vreg41 [1232r,1344r:0)  0@1232r
%vreg42 [1216r,1232r:0)  0@1216r
%vreg45 [2144r,2160r:0)  0@2144r
%vreg46 [2128r,2160r:0)  0@2128r
%vreg48 [2096r,2112r:0)  0@2096r
%vreg50 [2064r,2080r:0)  0@2064r
%vreg52 [2032r,2048r:0)  0@2032r
%vreg54 [2000r,2016r:0)  0@2000r
%vreg57 [1968r,1984r:0)  0@1968r
%vreg60 [1936r,1984r:0)  0@1936r
%vreg62 [1904r,1920r:0)  0@1904r
%vreg64 [1872r,1888r:0)  0@1872r
%vreg66 [1840r,1856r:0)  0@1840r
%vreg68 [1808r,1824r:0)  0@1808r
%vreg70 [1776r,1792r:0)  0@1776r
%vreg72 [1744r,1760r:0)  0@1744r
%vreg74 [1712r,1728r:0)  0@1712r
%vreg76 [1680r,1696r:0)  0@1680r
%vreg79 [1648r,1664r:0)  0@1648r
%vreg81 [1616r,1664r:0)  0@1616r
%vreg85 [1584r,1600r:0)  0@1584r
%vreg86 [1568r,1600r:0)  0@1568r
%vreg88 [2384r,2400r:0)  0@2384r
%vreg90 [2208r,2272r:0)  0@2208r
%vreg91 [2240r,2288r:0)  0@2240r
RegMasks: 208r 352r 1344r 2304r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzDecompressInit: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=4, align=4, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=4, align=4, at location [SP+8]
  fi#3: size=4, align=4, at location [SP+8]
  fi#4: size=8, align=8, at location [SP+8]
Function Live Ins: %RDI in %vreg0, %ESI in %vreg2, %EDX in %vreg4

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI %ESI %EDX
16B		%vreg5<def> = COPY %EDX; GR32:%vreg5
32B		%vreg3<def> = COPY %ESI; GR32:%vreg3
48B		%vreg1<def> = COPY %RDI; GR64:%vreg1
112B		%vreg9<def> = MOV64ri <ga:@BZ2_bzDecompressInit>; GR64:%vreg9
144B		%vreg10<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg10
160B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		%RDI<def> = COPY %vreg9; GR64:%vreg9
192B		%RSI<def> = COPY %vreg10; GR64:%vreg10
208B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
224B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
240B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
256B		STACKMAP 0, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, %vreg5, 0, <fi#3>, 0, %vreg1, 0, <fi#1>, 0, %vreg3, 0, <fi#2>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack4] LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack2](align=4) GR32:%vreg5,%vreg3 GR64:%vreg1
272B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
288B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%strm.addr] GR64:%vreg1
304B		MOV32mr <fi#2>, 1, %noreg, 0, %noreg, %vreg3; mem:ST4[%verbosity.addr] GR32:%vreg3
320B		MOV32mr <fi#3>, 1, %noreg, 0, %noreg, %vreg5; mem:ST4[%small.addr] GR32:%vreg5
336B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
352B		CALL64pcrel32 <ga:@bz_config_ok>, <regmask>, %RSP<imp-use>, %EAX<imp-def>
368B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
384B		%vreg7<def> = COPY %EAX<kill>; GR32:%vreg7
400B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
416B		STACKMAP 1, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack4] LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack2](align=4)
432B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
448B		CMP32ri8 %vreg7, 0, %EFLAGS<imp-def>; GR32:%vreg7
464B		JNE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

480B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
496B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -9; mem:ST4[%retval]
512B		JMP_1 <BB#17>
	    Successors according to CFG: BB#17

528B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0
544B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%strm.addr]
560B		JNE_1 <BB#4>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#4 BB#3

576B	BB#3: derived from LLVM BB %if.then.1
	    Predecessors according to CFG: BB#2
592B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
608B		JMP_1 <BB#17>
	    Successors according to CFG: BB#17

624B	BB#4: derived from LLVM BB %if.end.2
	    Predecessors according to CFG: BB#2
640B		CMP32mi8 <fi#3>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%small.addr]
656B		JE_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#5

672B	BB#5: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#4
688B		CMP32mi8 <fi#3>, 1, %noreg, 0, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%small.addr]
704B		JE_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#6

720B	BB#6: derived from LLVM BB %if.then.5
	    Predecessors according to CFG: BB#5
736B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
752B		JMP_1 <BB#17>
	    Successors according to CFG: BB#17

768B	BB#7: derived from LLVM BB %if.end.6
	    Predecessors according to CFG: BB#4 BB#5
784B		CMP32mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%verbosity.addr]
800B		JL_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#8

816B	BB#8: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#7
832B		CMP32mi8 <fi#2>, 1, %noreg, 0, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%verbosity.addr]
848B		JLE_1 <BB#10>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#10 BB#9

864B	BB#9: derived from LLVM BB %if.then.9
	    Predecessors according to CFG: BB#7 BB#8
880B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
896B		JMP_1 <BB#17>
	    Successors according to CFG: BB#17

912B	BB#10: derived from LLVM BB %if.end.10
	    Predecessors according to CFG: BB#8
928B		%vreg18<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg18
944B		CMP64mi8 %vreg18, 1, %noreg, 56, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzalloc] GR64:%vreg18
960B		JNE_1 <BB#12>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#12 BB#11

976B	BB#11: derived from LLVM BB %if.then.12
	    Predecessors according to CFG: BB#10
992B		%vreg20<def> = MOV64ri <ga:@default_bzalloc>; GR64:%vreg20
1008B		%vreg21<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg21
1024B		MOV64mr %vreg21, 1, %noreg, 56, %noreg, %vreg20; mem:ST8[%bzalloc13] GR64:%vreg21,%vreg20
	    Successors according to CFG: BB#12

1040B	BB#12: derived from LLVM BB %if.end.14
	    Predecessors according to CFG: BB#10 BB#11
1056B		%vreg24<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg24
1072B		CMP64mi8 %vreg24, 1, %noreg, 64, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzfree] GR64:%vreg24
1088B		JNE_1 <BB#14>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#14 BB#13

1104B	BB#13: derived from LLVM BB %if.then.16
	    Predecessors according to CFG: BB#12
1120B		%vreg26<def> = MOV64ri <ga:@default_bzfree>; GR64:%vreg26
1136B		%vreg27<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg27
1152B		MOV64mr %vreg27, 1, %noreg, 64, %noreg, %vreg26; mem:ST8[%bzfree17] GR64:%vreg27,%vreg26
	    Successors according to CFG: BB#14

1168B	BB#14: derived from LLVM BB %if.end.18
	    Predecessors according to CFG: BB#12 BB#13
1216B		%vreg42<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg42
1232B		%vreg41<def> = MOV64rm %vreg42, 1, %noreg, 56, %noreg; mem:LD8[%bzalloc19] GR64:%vreg41,%vreg42
1248B		%vreg39<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg39
1264B		%vreg38<def> = MOV64rm %vreg39, 1, %noreg, 72, %noreg; mem:LD8[%opaque] GR64:%vreg38,%vreg39
1280B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1312B		%ESI<def> = MOV32ri 64144
1328B		%EDX<def> = MOV32ri 1
1336B		%RDI<def> = COPY %vreg38; GR64:%vreg38
1344B		CALL64r %vreg41, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %EDX<imp-use>, %RAX<imp-def>; GR64:%vreg41
1360B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1376B		%vreg31<def> = COPY %RAX<kill>; GR64:%vreg31
1392B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1408B		STACKMAP 2, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack4] LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack2](align=4)
1424B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1456B		MOV64mr <fi#4>, 1, %noreg, 0, %noreg, %vreg31; mem:ST8[%s] GR64:%vreg31
1472B		CMP64mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%s]
1488B		JNE_1 <BB#16>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#16 BB#15

1504B	BB#15: derived from LLVM BB %if.then.22
	    Predecessors according to CFG: BB#14
1520B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -3; mem:ST4[%retval]
1536B		JMP_1 <BB#17>
	    Successors according to CFG: BB#17

1552B	BB#16: derived from LLVM BB %if.end.23
	    Predecessors according to CFG: BB#14
1568B		%vreg86<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg86
1584B		%vreg85<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg85
1600B		MOV64mr %vreg85, 1, %noreg, 0, %noreg, %vreg86; mem:ST8[%strm24] GR64:%vreg85,%vreg86
1616B		%vreg81<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg81
1648B		%vreg79<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg79
1664B		MOV64mr %vreg79, 1, %noreg, 48, %noreg, %vreg81; mem:ST8[%state] GR64:%vreg79,%vreg81
1680B		%vreg76<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg76
1696B		MOV32mi %vreg76, 1, %noreg, 8, %noreg, 10; mem:ST4[%state25] GR64:%vreg76
1712B		%vreg74<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg74
1728B		MOV32mi %vreg74, 1, %noreg, 36, %noreg, 0; mem:ST4[%bsLive] GR64:%vreg74
1744B		%vreg72<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg72
1760B		MOV32mi %vreg72, 1, %noreg, 32, %noreg, 0; mem:ST4[%bsBuff] GR64:%vreg72
1776B		%vreg70<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg70
1792B		MOV32mi %vreg70, 1, %noreg, 3188, %noreg, 0; mem:ST4[%calculatedCombinedCRC] GR64:%vreg70
1808B		%vreg68<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg68
1824B		MOV32mi %vreg68, 1, %noreg, 12, %noreg, 0; mem:ST4[%total_in_lo32] GR64:%vreg68
1840B		%vreg66<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg66
1856B		MOV32mi %vreg66, 1, %noreg, 16, %noreg, 0; mem:ST4[%total_in_hi32] GR64:%vreg66
1872B		%vreg64<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg64
1888B		MOV32mi %vreg64, 1, %noreg, 36, %noreg, 0; mem:ST4[%total_out_lo32] GR64:%vreg64
1904B		%vreg62<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg62
1920B		MOV32mi %vreg62, 1, %noreg, 40, %noreg, 0; mem:ST4[%total_out_hi32] GR64:%vreg62
1936B		%vreg60<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%small.addr] GR32:%vreg60
1968B		%vreg57<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg57
1984B		MOV8mr %vreg57, 1, %noreg, 44, %noreg, %vreg60:sub_8bit; mem:ST1[%smallDecompress] GR64:%vreg57 GR32:%vreg60
2000B		%vreg54<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg54
2016B		MOV64mi32 %vreg54, 1, %noreg, 3168, %noreg, 0; mem:ST8[%ll4] GR64:%vreg54
2032B		%vreg52<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg52
2048B		MOV64mi32 %vreg52, 1, %noreg, 3160, %noreg, 0; mem:ST8[%ll16] GR64:%vreg52
2064B		%vreg50<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg50
2080B		MOV64mi32 %vreg50, 1, %noreg, 3152, %noreg, 0; mem:ST8[%tt] GR64:%vreg50
2096B		%vreg48<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg48
2112B		MOV32mi %vreg48, 1, %noreg, 48, %noreg, 0; mem:ST4[%currBlockNo] GR64:%vreg48
2128B		%vreg46<def> = MOV32rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD4[%verbosity.addr] GR32:%vreg46
2144B		%vreg45<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg45
2160B		MOV32mr %vreg45, 1, %noreg, 52, %noreg, %vreg46; mem:ST4[%verbosity26] GR64:%vreg45 GR32:%vreg46
2176B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
	    Successors according to CFG: BB#17

2192B	BB#17: derived from LLVM BB %return
	    Predecessors according to CFG: BB#1 BB#16 BB#15 BB#9 BB#6 BB#3
2208B		%vreg90<def> = MOV64ri <ga:@BZ2_bzDecompressInit>; GR64:%vreg90
2240B		%vreg91<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg91
2256B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2272B		%RDI<def> = COPY %vreg90; GR64:%vreg90
2288B		%RSI<def> = COPY %vreg91; GR64:%vreg91
2304B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
2320B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2336B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2352B		STACKMAP 3, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
2368B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2384B		%vreg88<def> = MOV32rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD4[%retval] GR32:%vreg88
2400B		%EAX<def> = COPY %vreg88; GR32:%vreg88
2416B		RETQ %EAX<imp-use,kill>

# End machine code for function BZ2_bzDecompressInit.


selectOrSplit GR32:%vreg5 [16r,320r:0)  0@16r w=4.303977e-03
hints: %EDX
missed hint %EDX
assigning %vreg5 to %EBX: BH [16r,320r:0)  0@16r BL [16r,320r:0)  0@16r

selectOrSplit GR32:%vreg3 [32r,304r:0)  0@32r w=4.508928e-03
hints: %ESI
missed hint %ESI
%R14D is available at cost 1
Only trying the first 10 regs.
should evict: %vreg5 [16r,320r:0)  0@16r w= 4.303977e-03
hints: %EDX
can reassign: %vreg5 [16r,320r:0)  0@16r from %EBX to %EDX
should evict: %vreg5 [16r,320r:0)  0@16r w= 4.303977e-03
hints: %EDX
can reassign: %vreg5 [16r,320r:0)  0@16r from %EBX to %EDX
evicting %EBX interference: Cascade 1
unassigning %vreg5 from %EBX: BH BL
assigning %vreg3 to %EBX: BH [32r,304r:0)  0@32r BL [32r,304r:0)  0@32r
queuing new interval: %vreg5 [16r,320r:0)  0@16r

selectOrSplit GR32:%vreg5 [16r,320r:0)  0@16r w=4.303977e-03
hints: %EDX
missed hint %EDX
%R14D is available at cost 1
Only trying the first 10 regs.
assigning %vreg5 to %R14D: R14B [16r,320r:0)  0@16r

selectOrSplit GR64:%vreg1 [48r,288r:0)  0@48r w=4.734375e-03
hints: %RDI
missed hint %RDI
%R15 is available at cost 1
Only trying the first 10 regs.
should evict: %vreg3 [32r,304r:0)  0@32r w= 4.508928e-03
hints: %ESI
can reassign: %vreg3 [32r,304r:0)  0@32r from %RBX to %ESI
should evict: %vreg3 [32r,304r:0)  0@32r w= 4.508928e-03
hints: %ESI
can reassign: %vreg3 [32r,304r:0)  0@32r from %RBX to %ESI
evicting %RBX interference: Cascade 2
unassigning %vreg3 from %EBX: BH BL
assigning %vreg1 to %RBX: BH [48r,288r:0)  0@48r BL [48r,288r:0)  0@48r
queuing new interval: %vreg3 [32r,304r:0)  0@32r

selectOrSplit GR32:%vreg3 [32r,304r:0)  0@32r w=4.508928e-03
hints: %ESI
missed hint %ESI
%R15D is available at cost 1
Only trying the first 10 regs.
assigning %vreg3 to %R15D: R15B [32r,304r:0)  0@32r

selectOrSplit GR64:%vreg9 [112r,176r:0)  0@112r w=2.176724e-03
hints: %RDI
assigning %vreg9 to %RDI: DIL [112r,176r:0)  0@112r

selectOrSplit GR64:%vreg10 [144r,192r:0)  0@144r w=4.508928e-03
hints: %RSI
assigning %vreg10 to %RSI: SIL [144r,192r:0)  0@144r

selectOrSplit GR32:%vreg7 [384r,448r:0)  0@384r w=4.353448e-03
hints: %EAX
assigning %vreg7 to %EAX: AH [384r,448r:0)  0@384r AL [384r,448r:0)  0@384r

selectOrSplit GR64:%vreg38 [1264r,1336r:0)  0@1264r w=1.882549e-04
hints: %RDI
assigning %vreg38 to %RDI: DIL [1264r,1336r:0)  0@1264r

selectOrSplit GR64:%vreg31 [1376r,1456r:0)  0@1376r w=1.851173e-04
hints: %RAX
assigning %vreg31 to %RAX: AH [1376r,1456r:0)  0@1376r AL [1376r,1456r:0)  0@1376r

selectOrSplit GR64:%vreg90 [2208r,2272r:0)  0@2208r w=2.176724e-03
hints: %RDI
assigning %vreg90 to %RDI: DIL [2208r,2272r:0)  0@2208r

selectOrSplit GR64:%vreg91 [2240r,2288r:0)  0@2240r w=4.508928e-03
hints: %RSI
assigning %vreg91 to %RSI: SIL [2240r,2288r:0)  0@2240r

selectOrSplit GR32:%vreg88 [2384r,2400r:0)  0@2384r w=inf
hints: %EAX
assigning %vreg88 to %EAX: AH [2384r,2400r:0)  0@2384r AL [2384r,2400r:0)  0@2384r

selectOrSplit GR64:%vreg18 [928r,944r:0)  0@928r w=inf
assigning %vreg18 to %RAX: AH [928r,944r:0)  0@928r AL [928r,944r:0)  0@928r

selectOrSplit GR64:%vreg20 [992r,1024r:0)  0@992r w=5.430651e-05
assigning %vreg20 to %RAX: AH [992r,1024r:0)  0@992r AL [992r,1024r:0)  0@992r

selectOrSplit GR64:%vreg21 [1008r,1024r:0)  0@1008r w=inf
assigning %vreg21 to %RCX: CH [1008r,1024r:0)  0@1008r CL [1008r,1024r:0)  0@1008r

selectOrSplit GR64:%vreg24 [1056r,1072r:0)  0@1056r w=inf
assigning %vreg24 to %RAX: AH [1056r,1072r:0)  0@1056r AL [1056r,1072r:0)  0@1056r

selectOrSplit GR64:%vreg26 [1120r,1152r:0)  0@1120r w=5.430651e-05
assigning %vreg26 to %RAX: AH [1120r,1152r:0)  0@1120r AL [1120r,1152r:0)  0@1120r

selectOrSplit GR64:%vreg27 [1136r,1152r:0)  0@1136r w=inf
assigning %vreg27 to %RCX: CH [1136r,1152r:0)  0@1136r CL [1136r,1152r:0)  0@1136r

selectOrSplit GR64:%vreg42 [1216r,1232r:0)  0@1216r w=inf
assigning %vreg42 to %RAX: AH [1216r,1232r:0)  0@1216r AL [1216r,1232r:0)  0@1216r

selectOrSplit GR64:%vreg41 [1232r,1344r:0)  0@1232r w=1.718292e-04
assigning %vreg41 to %RAX: AH [1232r,1344r:0)  0@1232r AL [1232r,1344r:0)  0@1232r

selectOrSplit GR64:%vreg39 [1248r,1264r:0)  0@1248r w=inf
assigning %vreg39 to %RCX: CH [1248r,1264r:0)  0@1248r CL [1248r,1264r:0)  0@1248r

selectOrSplit GR64:%vreg86 [1568r,1600r:0)  0@1568r w=1.086130e-04
assigning %vreg86 to %RAX: AH [1568r,1600r:0)  0@1568r AL [1568r,1600r:0)  0@1568r

selectOrSplit GR64:%vreg85 [1584r,1600r:0)  0@1584r w=inf
assigning %vreg85 to %RCX: CH [1584r,1600r:0)  0@1584r CL [1584r,1600r:0)  0@1584r

selectOrSplit GR64:%vreg81 [1616r,1664r:0)  0@1616r w=1.047340e-04
assigning %vreg81 to %RAX: AH [1616r,1664r:0)  0@1616r AL [1616r,1664r:0)  0@1616r

selectOrSplit GR64:%vreg79 [1648r,1664r:0)  0@1648r w=inf
assigning %vreg79 to %RCX: CH [1648r,1664r:0)  0@1648r CL [1648r,1664r:0)  0@1648r

selectOrSplit GR64:%vreg76 [1680r,1696r:0)  0@1680r w=inf
assigning %vreg76 to %RAX: AH [1680r,1696r:0)  0@1680r AL [1680r,1696r:0)  0@1680r

selectOrSplit GR64:%vreg74 [1712r,1728r:0)  0@1712r w=inf
assigning %vreg74 to %RAX: AH [1712r,1728r:0)  0@1712r AL [1712r,1728r:0)  0@1712r

selectOrSplit GR64:%vreg72 [1744r,1760r:0)  0@1744r w=inf
assigning %vreg72 to %RAX: AH [1744r,1760r:0)  0@1744r AL [1744r,1760r:0)  0@1744r

selectOrSplit GR64:%vreg70 [1776r,1792r:0)  0@1776r w=inf
assigning %vreg70 to %RAX: AH [1776r,1792r:0)  0@1776r AL [1776r,1792r:0)  0@1776r

selectOrSplit GR64:%vreg68 [1808r,1824r:0)  0@1808r w=inf
assigning %vreg68 to %RAX: AH [1808r,1824r:0)  0@1808r AL [1808r,1824r:0)  0@1808r

selectOrSplit GR64:%vreg66 [1840r,1856r:0)  0@1840r w=inf
assigning %vreg66 to %RAX: AH [1840r,1856r:0)  0@1840r AL [1840r,1856r:0)  0@1840r

selectOrSplit GR64:%vreg64 [1872r,1888r:0)  0@1872r w=inf
assigning %vreg64 to %RAX: AH [1872r,1888r:0)  0@1872r AL [1872r,1888r:0)  0@1872r

selectOrSplit GR64:%vreg62 [1904r,1920r:0)  0@1904r w=inf
assigning %vreg62 to %RAX: AH [1904r,1920r:0)  0@1904r AL [1904r,1920r:0)  0@1904r

selectOrSplit GR32:%vreg60 [1936r,1984r:0)  0@1936r w=1.047340e-04
assigning %vreg60 to %EAX: AH [1936r,1984r:0)  0@1936r AL [1936r,1984r:0)  0@1936r

selectOrSplit GR64:%vreg57 [1968r,1984r:0)  0@1968r w=inf
assigning %vreg57 to %RCX: CH [1968r,1984r:0)  0@1968r CL [1968r,1984r:0)  0@1968r

selectOrSplit GR64:%vreg54 [2000r,2016r:0)  0@2000r w=inf
assigning %vreg54 to %RAX: AH [2000r,2016r:0)  0@2000r AL [2000r,2016r:0)  0@2000r

selectOrSplit GR64:%vreg52 [2032r,2048r:0)  0@2032r w=inf
assigning %vreg52 to %RAX: AH [2032r,2048r:0)  0@2032r AL [2032r,2048r:0)  0@2032r

selectOrSplit GR64:%vreg50 [2064r,2080r:0)  0@2064r w=inf
assigning %vreg50 to %RAX: AH [2064r,2080r:0)  0@2064r AL [2064r,2080r:0)  0@2064r

selectOrSplit GR64:%vreg48 [2096r,2112r:0)  0@2096r w=inf
assigning %vreg48 to %RAX: AH [2096r,2112r:0)  0@2096r AL [2096r,2112r:0)  0@2096r

selectOrSplit GR32:%vreg46 [2128r,2160r:0)  0@2128r w=1.086130e-04
assigning %vreg46 to %EAX: AH [2128r,2160r:0)  0@2128r AL [2128r,2160r:0)  0@2128r

selectOrSplit GR64:%vreg45 [2144r,2160r:0)  0@2144r w=inf
assigning %vreg45 to %RCX: CH [2144r,2160r:0)  0@2144r CL [2144r,2160r:0)  0@2144r

********** STACK TRANSFORMATION METADATA **********
********** Function: BZ2_bzDecompressInit
********** REGISTER MAP **********
[%vreg1 -> %RBX] GR64
[%vreg3 -> %R15D] GR32
[%vreg5 -> %R14D] GR32
[%vreg7 -> %EAX] GR32
[%vreg9 -> %RDI] GR64
[%vreg10 -> %RSI] GR64
[%vreg18 -> %RAX] GR64
[%vreg20 -> %RAX] GR64
[%vreg21 -> %RCX] GR64
[%vreg24 -> %RAX] GR64
[%vreg26 -> %RAX] GR64
[%vreg27 -> %RCX] GR64
[%vreg31 -> %RAX] GR64
[%vreg38 -> %RDI] GR64
[%vreg39 -> %RCX] GR64
[%vreg41 -> %RAX] GR64
[%vreg42 -> %RAX] GR64
[%vreg45 -> %RCX] GR64
[%vreg46 -> %EAX] GR32
[%vreg48 -> %RAX] GR64
[%vreg50 -> %RAX] GR64
[%vreg52 -> %RAX] GR64
[%vreg54 -> %RAX] GR64
[%vreg57 -> %RCX] GR64
[%vreg60 -> %EAX] GR32
[%vreg62 -> %RAX] GR64
[%vreg64 -> %RAX] GR64
[%vreg66 -> %RAX] GR64
[%vreg68 -> %RAX] GR64
[%vreg70 -> %RAX] GR64
[%vreg72 -> %RAX] GR64
[%vreg74 -> %RAX] GR64
[%vreg76 -> %RAX] GR64
[%vreg79 -> %RCX] GR64
[%vreg81 -> %RAX] GR64
[%vreg85 -> %RCX] GR64
[%vreg86 -> %RAX] GR64
[%vreg88 -> %EAX] GR32
[%vreg90 -> %RDI] GR64
[%vreg91 -> %RSI] GR64


Stackmap 0:
  STACKMAP 0, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, %vreg5, 0, <fi#3>, 0, %vreg1, 0, <fi#1>, 0, %vreg3, 0, <fi#2>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack4] LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack2](align=4) GR32:%vreg5,%vreg3 GR64:%vreg1

i32* %retval: in stack slot 0 (size: 4)
%struct.DState** %s: in stack slot 4 (size: 8)
i32 %small: in register %R14D (vreg 5)
i32* %small.addr: in stack slot 3 (size: 4)
%struct.bz_stream* %strm: in register %RBX (vreg 1)
%struct.bz_stream** %strm.addr: in stack slot 1 (size: 8)
i32 %verbosity: in register %R15D (vreg 3)
i32* %verbosity.addr: in stack slot 2 (size: 4)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack4] LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack2](align=4)

i32* %retval: in stack slot 0 (size: 4)
%struct.DState** %s: in stack slot 4 (size: 8)
i32* %small.addr: in stack slot 3 (size: 4)
%struct.bz_stream** %strm.addr: in stack slot 1 (size: 8)
i32* %verbosity.addr: in stack slot 2 (size: 4)

Duplicate operand locations:


Stackmap 2:
  STACKMAP 2, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack4] LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack2](align=4)

i32* %retval: in stack slot 0 (size: 4)
%struct.DState** %s: in stack slot 4 (size: 8)
i32* %small.addr: in stack slot 3 (size: 4)
%struct.bz_stream** %strm.addr: in stack slot 1 (size: 8)
i32* %verbosity.addr: in stack slot 2 (size: 4)

Duplicate operand locations:


Stackmap 3:
  STACKMAP 3, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)

i32* %retval: in stack slot 0 (size: 4)

Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, %vreg5, 0, <fi#3>, 0, %vreg1, 0, <fi#1>, 0, %vreg3, 0, <fi#2>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack4] LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack2](align=4) GR32:%vreg5,%vreg3 GR64:%vreg1
  -> Call instruction SlotIndex 208B, searching vregs 0 -> 92 and stack slots -1 -> 5

  STACKMAP 1, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack4] LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack2](align=4)
  -> Call instruction SlotIndex 352B, searching vregs 0 -> 92 and stack slots -1 -> 5

  STACKMAP 2, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack4] LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack2](align=4)
  -> Call instruction SlotIndex 1344B, searching vregs 0 -> 92 and stack slots -1 -> 5

  STACKMAP 3, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
  -> Call instruction SlotIndex 2304B, searching vregs 0 -> 92 and stack slots -1 -> 5

********** REWRITE VIRTUAL REGISTERS **********
********** Function: BZ2_bzDecompressInit
********** REGISTER MAP **********
[%vreg1 -> %RBX] GR64
[%vreg3 -> %R15D] GR32
[%vreg5 -> %R14D] GR32
[%vreg7 -> %EAX] GR32
[%vreg9 -> %RDI] GR64
[%vreg10 -> %RSI] GR64
[%vreg18 -> %RAX] GR64
[%vreg20 -> %RAX] GR64
[%vreg21 -> %RCX] GR64
[%vreg24 -> %RAX] GR64
[%vreg26 -> %RAX] GR64
[%vreg27 -> %RCX] GR64
[%vreg31 -> %RAX] GR64
[%vreg38 -> %RDI] GR64
[%vreg39 -> %RCX] GR64
[%vreg41 -> %RAX] GR64
[%vreg42 -> %RAX] GR64
[%vreg45 -> %RCX] GR64
[%vreg46 -> %EAX] GR32
[%vreg48 -> %RAX] GR64
[%vreg50 -> %RAX] GR64
[%vreg52 -> %RAX] GR64
[%vreg54 -> %RAX] GR64
[%vreg57 -> %RCX] GR64
[%vreg60 -> %EAX] GR32
[%vreg62 -> %RAX] GR64
[%vreg64 -> %RAX] GR64
[%vreg66 -> %RAX] GR64
[%vreg68 -> %RAX] GR64
[%vreg70 -> %RAX] GR64
[%vreg72 -> %RAX] GR64
[%vreg74 -> %RAX] GR64
[%vreg76 -> %RAX] GR64
[%vreg79 -> %RCX] GR64
[%vreg81 -> %RAX] GR64
[%vreg85 -> %RCX] GR64
[%vreg86 -> %RAX] GR64
[%vreg88 -> %EAX] GR32
[%vreg90 -> %RDI] GR64
[%vreg91 -> %RSI] GR64

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %EDX %ESI %RDI
16B		%vreg5<def> = COPY %EDX; GR32:%vreg5
32B		%vreg3<def> = COPY %ESI; GR32:%vreg3
48B		%vreg1<def> = COPY %RDI; GR64:%vreg1
112B		%vreg9<def> = MOV64ri <ga:@BZ2_bzDecompressInit>; GR64:%vreg9
144B		%vreg10<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg10
160B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		%RDI<def> = COPY %vreg9<kill>; GR64:%vreg9
192B		%RSI<def> = COPY %vreg10<kill>; GR64:%vreg10
208B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
224B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
240B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
256B		STACKMAP 0, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, %vreg5, 0, <fi#3>, 0, %vreg1, 0, <fi#1>, 0, %vreg3, 0, <fi#2>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack4] LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack2](align=4) GR32:%vreg5,%vreg3 GR64:%vreg1
272B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
288B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg1<kill>; mem:ST8[%strm.addr] GR64:%vreg1
304B		MOV32mr <fi#2>, 1, %noreg, 0, %noreg, %vreg3<kill>; mem:ST4[%verbosity.addr] GR32:%vreg3
320B		MOV32mr <fi#3>, 1, %noreg, 0, %noreg, %vreg5<kill>; mem:ST4[%small.addr] GR32:%vreg5
336B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
352B		CALL64pcrel32 <ga:@bz_config_ok>, <regmask>, %RSP<imp-use>, %EAX<imp-def>
368B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
384B		%vreg7<def> = COPY %EAX; GR32:%vreg7
400B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
416B		STACKMAP 1, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack4] LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack2](align=4)
432B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
448B		CMP32ri8 %vreg7<kill>, 0, %EFLAGS<imp-def>; GR32:%vreg7
464B		JNE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1
> %R14D<def> = COPY %EDX
> %R15D<def> = COPY %ESI
> %RBX<def> = COPY %RDI
> %RDI<def> = MOV64ri <ga:@BZ2_bzDecompressInit>
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 0, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, %R14D, 0, <fi#3>, 0, %RBX, 0, <fi#1>, 0, %R15D, 0, <fi#2>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack4] LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack2](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %RBX<kill>; mem:ST8[%strm.addr]
> MOV32mr <fi#2>, 1, %noreg, 0, %noreg, %R15D<kill>; mem:ST4[%verbosity.addr]
> MOV32mr <fi#3>, 1, %noreg, 0, %noreg, %R14D<kill>; mem:ST4[%small.addr]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> CALL64pcrel32 <ga:@bz_config_ok>, <regmask>, %RSP<imp-use>, %EAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def> = COPY %EAX
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 1, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack4] LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack2](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> CMP32ri8 %EAX<kill>, 0, %EFLAGS<imp-def>
> JNE_1 <BB#2>, %EFLAGS<imp-use,kill>
480B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
496B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -9; mem:ST4[%retval]
512B		JMP_1 <BB#17>
	    Successors according to CFG: BB#17
> MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -9; mem:ST4[%retval]
> JMP_1 <BB#17>
528B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0
544B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%strm.addr]
560B		JNE_1 <BB#4>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#4 BB#3
> CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%strm.addr]
> JNE_1 <BB#4>, %EFLAGS<imp-use,kill>
576B	BB#3: derived from LLVM BB %if.then.1
	    Predecessors according to CFG: BB#2
592B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
608B		JMP_1 <BB#17>
	    Successors according to CFG: BB#17
> MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
> JMP_1 <BB#17>
624B	BB#4: derived from LLVM BB %if.end.2
	    Predecessors according to CFG: BB#2
640B		CMP32mi8 <fi#3>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%small.addr]
656B		JE_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#5
> CMP32mi8 <fi#3>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%small.addr]
> JE_1 <BB#7>, %EFLAGS<imp-use,kill>
672B	BB#5: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#4
688B		CMP32mi8 <fi#3>, 1, %noreg, 0, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%small.addr]
704B		JE_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#6
> CMP32mi8 <fi#3>, 1, %noreg, 0, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%small.addr]
> JE_1 <BB#7>, %EFLAGS<imp-use,kill>
720B	BB#6: derived from LLVM BB %if.then.5
	    Predecessors according to CFG: BB#5
736B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
752B		JMP_1 <BB#17>
	    Successors according to CFG: BB#17
> MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
> JMP_1 <BB#17>
768B	BB#7: derived from LLVM BB %if.end.6
	    Predecessors according to CFG: BB#4 BB#5
784B		CMP32mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%verbosity.addr]
800B		JL_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#8
> CMP32mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%verbosity.addr]
> JL_1 <BB#9>, %EFLAGS<imp-use,kill>
816B	BB#8: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#7
832B		CMP32mi8 <fi#2>, 1, %noreg, 0, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%verbosity.addr]
848B		JLE_1 <BB#10>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#10 BB#9
> CMP32mi8 <fi#2>, 1, %noreg, 0, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%verbosity.addr]
> JLE_1 <BB#10>, %EFLAGS<imp-use,kill>
864B	BB#9: derived from LLVM BB %if.then.9
	    Predecessors according to CFG: BB#7 BB#8
880B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
896B		JMP_1 <BB#17>
	    Successors according to CFG: BB#17
> MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
> JMP_1 <BB#17>
912B	BB#10: derived from LLVM BB %if.end.10
	    Predecessors according to CFG: BB#8
928B		%vreg18<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg18
944B		CMP64mi8 %vreg18<kill>, 1, %noreg, 56, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzalloc] GR64:%vreg18
960B		JNE_1 <BB#12>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#12 BB#11
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr]
> CMP64mi8 %RAX<kill>, 1, %noreg, 56, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzalloc]
> JNE_1 <BB#12>, %EFLAGS<imp-use,kill>
976B	BB#11: derived from LLVM BB %if.then.12
	    Predecessors according to CFG: BB#10
992B		%vreg20<def> = MOV64ri <ga:@default_bzalloc>; GR64:%vreg20
1008B		%vreg21<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg21
1024B		MOV64mr %vreg21<kill>, 1, %noreg, 56, %noreg, %vreg20<kill>; mem:ST8[%bzalloc13] GR64:%vreg21,%vreg20
	    Successors according to CFG: BB#12
> %RAX<def> = MOV64ri <ga:@default_bzalloc>
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr]
> MOV64mr %RCX<kill>, 1, %noreg, 56, %noreg, %RAX<kill>; mem:ST8[%bzalloc13]
1040B	BB#12: derived from LLVM BB %if.end.14
	    Predecessors according to CFG: BB#10 BB#11
1056B		%vreg24<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg24
1072B		CMP64mi8 %vreg24<kill>, 1, %noreg, 64, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzfree] GR64:%vreg24
1088B		JNE_1 <BB#14>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#14 BB#13
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr]
> CMP64mi8 %RAX<kill>, 1, %noreg, 64, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzfree]
> JNE_1 <BB#14>, %EFLAGS<imp-use,kill>
1104B	BB#13: derived from LLVM BB %if.then.16
	    Predecessors according to CFG: BB#12
1120B		%vreg26<def> = MOV64ri <ga:@default_bzfree>; GR64:%vreg26
1136B		%vreg27<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg27
1152B		MOV64mr %vreg27<kill>, 1, %noreg, 64, %noreg, %vreg26<kill>; mem:ST8[%bzfree17] GR64:%vreg27,%vreg26
	    Successors according to CFG: BB#14
> %RAX<def> = MOV64ri <ga:@default_bzfree>
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr]
> MOV64mr %RCX<kill>, 1, %noreg, 64, %noreg, %RAX<kill>; mem:ST8[%bzfree17]
1168B	BB#14: derived from LLVM BB %if.end.18
	    Predecessors according to CFG: BB#12 BB#13
1216B		%vreg42<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg42
1232B		%vreg41<def> = MOV64rm %vreg42<kill>, 1, %noreg, 56, %noreg; mem:LD8[%bzalloc19] GR64:%vreg41,%vreg42
1248B		%vreg39<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg39
1264B		%vreg38<def> = MOV64rm %vreg39<kill>, 1, %noreg, 72, %noreg; mem:LD8[%opaque] GR64:%vreg38,%vreg39
1280B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1312B		%ESI<def> = MOV32ri 64144
1328B		%EDX<def> = MOV32ri 1
1336B		%RDI<def> = COPY %vreg38<kill>; GR64:%vreg38
1344B		CALL64r %vreg41<kill>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %EDX<imp-use>, %RAX<imp-def>; GR64:%vreg41
1360B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1376B		%vreg31<def> = COPY %RAX; GR64:%vreg31
1392B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1408B		STACKMAP 2, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack4] LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack2](align=4)
1424B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1456B		MOV64mr <fi#4>, 1, %noreg, 0, %noreg, %vreg31<kill>; mem:ST8[%s] GR64:%vreg31
1472B		CMP64mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%s]
1488B		JNE_1 <BB#16>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#16 BB#15
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 56, %noreg; mem:LD8[%bzalloc19]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr]
> %RDI<def> = MOV64rm %RCX<kill>, 1, %noreg, 72, %noreg; mem:LD8[%opaque]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %ESI<def> = MOV32ri 64144
> %EDX<def> = MOV32ri 1
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> CALL64r %RAX<kill>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %EDX<imp-use>, %RAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RAX<def> = COPY %RAX
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 2, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack4] LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack2](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV64mr <fi#4>, 1, %noreg, 0, %noreg, %RAX<kill>; mem:ST8[%s]
> CMP64mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%s]
> JNE_1 <BB#16>, %EFLAGS<imp-use,kill>
1504B	BB#15: derived from LLVM BB %if.then.22
	    Predecessors according to CFG: BB#14
1520B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -3; mem:ST4[%retval]
1536B		JMP_1 <BB#17>
	    Successors according to CFG: BB#17
> MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -3; mem:ST4[%retval]
> JMP_1 <BB#17>
1552B	BB#16: derived from LLVM BB %if.end.23
	    Predecessors according to CFG: BB#14
1568B		%vreg86<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg86
1584B		%vreg85<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg85
1600B		MOV64mr %vreg85<kill>, 1, %noreg, 0, %noreg, %vreg86<kill>; mem:ST8[%strm24] GR64:%vreg85,%vreg86
1616B		%vreg81<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg81
1648B		%vreg79<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg79
1664B		MOV64mr %vreg79<kill>, 1, %noreg, 48, %noreg, %vreg81<kill>; mem:ST8[%state] GR64:%vreg79,%vreg81
1680B		%vreg76<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg76
1696B		MOV32mi %vreg76<kill>, 1, %noreg, 8, %noreg, 10; mem:ST4[%state25] GR64:%vreg76
1712B		%vreg74<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg74
1728B		MOV32mi %vreg74<kill>, 1, %noreg, 36, %noreg, 0; mem:ST4[%bsLive] GR64:%vreg74
1744B		%vreg72<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg72
1760B		MOV32mi %vreg72<kill>, 1, %noreg, 32, %noreg, 0; mem:ST4[%bsBuff] GR64:%vreg72
1776B		%vreg70<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg70
1792B		MOV32mi %vreg70<kill>, 1, %noreg, 3188, %noreg, 0; mem:ST4[%calculatedCombinedCRC] GR64:%vreg70
1808B		%vreg68<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg68
1824B		MOV32mi %vreg68<kill>, 1, %noreg, 12, %noreg, 0; mem:ST4[%total_in_lo32] GR64:%vreg68
1840B		%vreg66<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg66
1856B		MOV32mi %vreg66<kill>, 1, %noreg, 16, %noreg, 0; mem:ST4[%total_in_hi32] GR64:%vreg66
1872B		%vreg64<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg64
1888B		MOV32mi %vreg64<kill>, 1, %noreg, 36, %noreg, 0; mem:ST4[%total_out_lo32] GR64:%vreg64
1904B		%vreg62<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg62
1920B		MOV32mi %vreg62<kill>, 1, %noreg, 40, %noreg, 0; mem:ST4[%total_out_hi32] GR64:%vreg62
1936B		%vreg60<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%small.addr] GR32:%vreg60
1968B		%vreg57<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg57
1984B		MOV8mr %vreg57<kill>, 1, %noreg, 44, %noreg, %vreg60:sub_8bit<kill>; mem:ST1[%smallDecompress] GR64:%vreg57 GR32:%vreg60
2000B		%vreg54<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg54
2016B		MOV64mi32 %vreg54<kill>, 1, %noreg, 3168, %noreg, 0; mem:ST8[%ll4] GR64:%vreg54
2032B		%vreg52<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg52
2048B		MOV64mi32 %vreg52<kill>, 1, %noreg, 3160, %noreg, 0; mem:ST8[%ll16] GR64:%vreg52
2064B		%vreg50<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg50
2080B		MOV64mi32 %vreg50<kill>, 1, %noreg, 3152, %noreg, 0; mem:ST8[%tt] GR64:%vreg50
2096B		%vreg48<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg48
2112B		MOV32mi %vreg48<kill>, 1, %noreg, 48, %noreg, 0; mem:ST4[%currBlockNo] GR64:%vreg48
2128B		%vreg46<def> = MOV32rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD4[%verbosity.addr] GR32:%vreg46
2144B		%vreg45<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg45
2160B		MOV32mr %vreg45<kill>, 1, %noreg, 52, %noreg, %vreg46<kill>; mem:ST4[%verbosity26] GR64:%vreg45 GR32:%vreg46
2176B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
	    Successors according to CFG: BB#17
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr]
> %RCX<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> MOV64mr %RCX<kill>, 1, %noreg, 0, %noreg, %RAX<kill>; mem:ST8[%strm24]
> %RAX<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr]
> MOV64mr %RCX<kill>, 1, %noreg, 48, %noreg, %RAX<kill>; mem:ST8[%state]
> %RAX<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> MOV32mi %RAX<kill>, 1, %noreg, 8, %noreg, 10; mem:ST4[%state25]
> %RAX<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> MOV32mi %RAX<kill>, 1, %noreg, 36, %noreg, 0; mem:ST4[%bsLive]
> %RAX<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> MOV32mi %RAX<kill>, 1, %noreg, 32, %noreg, 0; mem:ST4[%bsBuff]
> %RAX<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> MOV32mi %RAX<kill>, 1, %noreg, 3188, %noreg, 0; mem:ST4[%calculatedCombinedCRC]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 12, %noreg, 0; mem:ST4[%total_in_lo32]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 16, %noreg, 0; mem:ST4[%total_in_hi32]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 36, %noreg, 0; mem:ST4[%total_out_lo32]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 40, %noreg, 0; mem:ST4[%total_out_hi32]
> %EAX<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%small.addr]
> %RCX<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> MOV8mr %RCX<kill>, 1, %noreg, 44, %noreg, %AL, %EAX<imp-use,kill>; mem:ST1[%smallDecompress]
> %RAX<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> MOV64mi32 %RAX<kill>, 1, %noreg, 3168, %noreg, 0; mem:ST8[%ll4]
> %RAX<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> MOV64mi32 %RAX<kill>, 1, %noreg, 3160, %noreg, 0; mem:ST8[%ll16]
> %RAX<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> MOV64mi32 %RAX<kill>, 1, %noreg, 3152, %noreg, 0; mem:ST8[%tt]
> %RAX<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> MOV32mi %RAX<kill>, 1, %noreg, 48, %noreg, 0; mem:ST4[%currBlockNo]
> %EAX<def> = MOV32rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD4[%verbosity.addr]
> %RCX<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> MOV32mr %RCX<kill>, 1, %noreg, 52, %noreg, %EAX<kill>; mem:ST4[%verbosity26]
> MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
2192B	BB#17: derived from LLVM BB %return
	    Predecessors according to CFG: BB#1 BB#16 BB#15 BB#9 BB#6 BB#3
2208B		%vreg90<def> = MOV64ri <ga:@BZ2_bzDecompressInit>; GR64:%vreg90
2240B		%vreg91<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg91
2256B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2272B		%RDI<def> = COPY %vreg90<kill>; GR64:%vreg90
2288B		%RSI<def> = COPY %vreg91<kill>; GR64:%vreg91
2304B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
2320B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2336B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2352B		STACKMAP 3, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
2368B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2384B		%vreg88<def> = MOV32rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD4[%retval] GR32:%vreg88
2400B		%EAX<def> = COPY %vreg88<kill>; GR32:%vreg88
2416B		RETQ %EAX<imp-use>
> %RDI<def> = MOV64ri <ga:@BZ2_bzDecompressInit>
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 3, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def> = MOV32rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD4[%retval]
> %EAX<def> = COPY %EAX<kill>
Deleting identity copy.
> RETQ %EAX<imp-use>
Computing live-in reg-units in ABI blocks.
0B	BB#0 DIL#0 SIL#0
Created 2 new intervals.
********** INTERVALS **********
DIL [0B,32r:0)[144r,176r:2)[848r,880r:1)  0@0B-phi 1@848r 2@144r
SIL [0B,16r:0)[160r,176r:2)[864r,880r:1)  0@0B-phi 1@864r 2@160r
%vreg0 [32r,48r:0)  0@32r
%vreg1 [48r,256r:0)  0@48r
%vreg2 [16r,64r:0)  0@16r
%vreg3 [64r,272r:0)  0@64r
%vreg4 [80r,96r:0)  0@80r
%vreg5 [96r,144r:0)  0@96r
%vreg6 [112r,160r:0)  0@112r
%vreg11 [464r,480r:0)  0@464r
%vreg13 [448r,480r:0)  0@448r
%vreg14 [432r,480r:0)  0@432r
%vreg17 [384r,400r:0)[400r,416r:1)  0@384r 1@400r
%vreg20 [352r,368r:0)[368r,384r:1)  0@352r 1@368r
%vreg21 [336r,352r:0)  0@336r
%vreg23 [592r,608r:0)  0@592r
%vreg25 [528r,544r:0)  0@528r
%vreg29 [688r,704r:0)[704r,720r:1)  0@688r 1@704r
%vreg30 [672r,688r:0)  0@672r
%vreg32 [768r,784r:0)  0@768r
%vreg33 [784r,848r:0)  0@784r
%vreg34 [816r,864r:0)  0@816r
%vreg35 [800r,960r:0)  0@800r
RegMasks: 176r 880r
********** MACHINEINSTRS **********
# Machine code for function BZ2_indexIntoF: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=4, align=4, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=4, align=4, at location [SP+8]
  fi#3: size=4, align=4, at location [SP+8]
  fi#4: size=4, align=4, at location [SP+8]
Function Live Ins: %EDI in %vreg0, %RSI in %vreg2

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %EDI %RSI
16B		%vreg2<def> = COPY %RSI; GR64:%vreg2
32B		%vreg0<def> = COPY %EDI; GR32:%vreg0
48B		%vreg1<def> = COPY %vreg0; GR32:%vreg1,%vreg0
64B		%vreg3<def> = COPY %vreg2; GR64:%vreg3,%vreg2
80B		%vreg4<def> = MOV64ri <ga:@BZ2_indexIntoF>; GR64:%vreg4
96B		%vreg5<def> = COPY %vreg4; GR64:%vreg5,%vreg4
112B		%vreg6<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg6
128B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
144B		%RDI<def> = COPY %vreg5; GR64:%vreg5
160B		%RSI<def> = COPY %vreg6; GR64:%vreg6
176B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
192B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
208B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#2>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack0](align=4) LD8[FixedStack4](align=4) LD8[FixedStack3](align=4) LD8[FixedStack2](align=4) GR64:%vreg3 GR32:%vreg1
240B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
256B		MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1; mem:ST4[%indx.addr] GR32:%vreg1
272B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg3; mem:ST8[%cftab.addr] GR64:%vreg3
288B		MOV32mi <fi#2>, 1, %noreg, 0, %noreg, 0; mem:ST4[%nb]
304B		MOV32mi <fi#3>, 1, %noreg, 0, %noreg, 256; mem:ST4[%na]
	    Successors according to CFG: BB#1

320B	BB#1: derived from LLVM BB %do.body
	    Predecessors according to CFG: BB#0 BB#5
336B		%vreg21<def> = MOV32rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD4[%nb] GR32:%vreg21
352B		%vreg20<def> = COPY %vreg21; GR32:%vreg20,%vreg21
368B		%vreg20<def,tied1> = ADD32rm %vreg20<tied0>, <fi#3>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%na] GR32:%vreg20
384B		%vreg17<def> = COPY %vreg20; GR32:%vreg17,%vreg20
400B		%vreg17<def,tied1> = SAR32ri %vreg17<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg17
416B		MOV32mr <fi#4>, 1, %noreg, 0, %noreg, %vreg17; mem:ST4[%mid] GR32:%vreg17
432B		%vreg14<def> = MOV32rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD4[%indx.addr] GR32:%vreg14
448B		%vreg13<def> = MOVSX64rm32 <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%mid] GR64_NOSP:%vreg13
464B		%vreg11<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%cftab.addr] GR64:%vreg11
480B		CMP32rm %vreg14, %vreg11, 4, %vreg13, 0, %noreg, %EFLAGS<imp-def>; mem:LD4[%arrayidx] GR32:%vreg14 GR64:%vreg11 GR64_NOSP:%vreg13
496B		JL_1 <BB#3>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#3 BB#2

512B	BB#2: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#1
528B		%vreg25<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%mid] GR32:%vreg25
544B		MOV32mr <fi#2>, 1, %noreg, 0, %noreg, %vreg25; mem:ST4[%nb] GR32:%vreg25
560B		JMP_1 <BB#4>
	    Successors according to CFG: BB#4

576B	BB#3: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#1
592B		%vreg23<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%mid] GR32:%vreg23
608B		MOV32mr <fi#3>, 1, %noreg, 0, %noreg, %vreg23; mem:ST4[%na] GR32:%vreg23
	    Successors according to CFG: BB#4

624B	BB#4: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#3 BB#2
640B		JMP_1 <BB#5>
	    Successors according to CFG: BB#5

656B	BB#5: derived from LLVM BB %do.cond
	    Predecessors according to CFG: BB#4
672B		%vreg30<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%na] GR32:%vreg30
688B		%vreg29<def> = COPY %vreg30; GR32:%vreg29,%vreg30
704B		%vreg29<def,tied1> = SUB32rm %vreg29<tied0>, <fi#2>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%nb] GR32:%vreg29
720B		CMP32ri8 %vreg29, 1, %EFLAGS<imp-def>; GR32:%vreg29
736B		JNE_1 <BB#1>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#1 BB#6

752B	BB#6: derived from LLVM BB %do.end
	    Predecessors according to CFG: BB#5
768B		%vreg32<def> = MOV64ri <ga:@BZ2_indexIntoF>; GR64:%vreg32
784B		%vreg33<def> = COPY %vreg32; GR64:%vreg33,%vreg32
800B		%vreg35<def> = MOV32rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD4[%nb] GR32:%vreg35
816B		%vreg34<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg34
832B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
848B		%RDI<def> = COPY %vreg33; GR64:%vreg33
864B		%RSI<def> = COPY %vreg34; GR64:%vreg34
880B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
896B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
912B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
928B		STACKMAP 1, 0, %vreg35, ...; GR32:%vreg35
944B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
960B		%EAX<def> = COPY %vreg35; GR32:%vreg35
976B		RETQ %EAX<imp-use,kill>

# End machine code for function BZ2_indexIntoF.

********** SIMPLE REGISTER COALESCING **********
********** Function: BZ2_indexIntoF
********** JOINING INTERVALS ***********
do.body:
if.end:
do.cond:
if.then:
if.else:
352B	%vreg20<def> = COPY %vreg21; GR32:%vreg20,%vreg21
	Considering merging to GR32 with %vreg21 in %vreg20
		RHS = %vreg21 [336r,352r:0)  0@336r
		LHS = %vreg20 [352r,368r:0)[368r,384r:1)  0@352r 1@368r
		merge %vreg20:0@352r into %vreg21:0@336r --> @336r
		erased:	352r	%vreg20<def> = COPY %vreg21; GR32:%vreg20,%vreg21
		updated: 336B	%vreg20<def> = MOV32rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD4[%nb] GR32:%vreg20
	Success: %vreg21 -> %vreg20
	Result = %vreg20 [336r,368r:0)[368r,384r:1)  0@336r 1@368r
384B	%vreg17<def> = COPY %vreg20; GR32:%vreg17,%vreg20
	Considering merging to GR32 with %vreg20 in %vreg17
		RHS = %vreg20 [336r,368r:0)[368r,384r:1)  0@336r 1@368r
		LHS = %vreg17 [384r,400r:0)[400r,416r:1)  0@384r 1@400r
		merge %vreg17:0@384r into %vreg20:1@368r --> @368r
		erased:	384r	%vreg17<def> = COPY %vreg20; GR32:%vreg17,%vreg20
		updated: 336B	%vreg17<def> = MOV32rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD4[%nb] GR32:%vreg17
		updated: 368B	%vreg17<def,tied1> = ADD32rm %vreg17<tied0>, <fi#3>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%na] GR32:%vreg17
	Success: %vreg20 -> %vreg17
	Result = %vreg17 [336r,368r:2)[368r,400r:0)[400r,416r:1)  0@368r 1@400r 2@336r
688B	%vreg29<def> = COPY %vreg30; GR32:%vreg29,%vreg30
	Considering merging to GR32 with %vreg30 in %vreg29
		RHS = %vreg30 [672r,688r:0)  0@672r
		LHS = %vreg29 [688r,704r:0)[704r,720r:1)  0@688r 1@704r
		merge %vreg29:0@688r into %vreg30:0@672r --> @672r
		erased:	688r	%vreg29<def> = COPY %vreg30; GR32:%vreg29,%vreg30
		updated: 672B	%vreg29<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%na] GR32:%vreg29
	Success: %vreg30 -> %vreg29
	Result = %vreg29 [672r,704r:0)[704r,720r:1)  0@672r 1@704r
entry:
16B	%vreg2<def> = COPY %RSI; GR64:%vreg2
	Considering merging %vreg2 with %RSI
	Can only merge into reserved registers.
32B	%vreg0<def> = COPY %EDI; GR32:%vreg0
	Considering merging %vreg0 with %EDI
	Can only merge into reserved registers.
144B	%RDI<def> = COPY %vreg5; GR64:%vreg5
	Considering merging %vreg5 with %RDI
	Can only merge into reserved registers.
160B	%RSI<def> = COPY %vreg6; GR64:%vreg6
	Considering merging %vreg6 with %RSI
	Can only merge into reserved registers.
do.end:
848B	%RDI<def> = COPY %vreg33; GR64:%vreg33
	Considering merging %vreg33 with %RDI
	Can only merge into reserved registers.
864B	%RSI<def> = COPY %vreg34; GR64:%vreg34
	Considering merging %vreg34 with %RSI
	Can only merge into reserved registers.
960B	%EAX<def> = COPY %vreg35; GR32:%vreg35
	Considering merging %vreg35 with %EAX
	Can only merge into reserved registers.
48B	%vreg1<def> = COPY %vreg0; GR32:%vreg1,%vreg0
	Considering merging to GR32 with %vreg0 in %vreg1
		RHS = %vreg0 [32r,48r:0)  0@32r
		LHS = %vreg1 [48r,256r:0)  0@48r
		merge %vreg1:0@48r into %vreg0:0@32r --> @32r
		erased:	48r	%vreg1<def> = COPY %vreg0; GR32:%vreg1,%vreg0
		updated: 32B	%vreg1<def> = COPY %EDI; GR32:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [32r,256r:0)  0@32r
64B	%vreg3<def> = COPY %vreg2; GR64:%vreg3,%vreg2
	Considering merging to GR64 with %vreg2 in %vreg3
		RHS = %vreg2 [16r,64r:0)  0@16r
		LHS = %vreg3 [64r,272r:0)  0@64r
		merge %vreg3:0@64r into %vreg2:0@16r --> @16r
		erased:	64r	%vreg3<def> = COPY %vreg2; GR64:%vreg3,%vreg2
		updated: 16B	%vreg3<def> = COPY %RSI; GR64:%vreg3
	Success: %vreg2 -> %vreg3
	Result = %vreg3 [16r,272r:0)  0@16r
96B	%vreg5<def> = COPY %vreg4; GR64:%vreg5,%vreg4
	Considering merging to GR64 with %vreg4 in %vreg5
		RHS = %vreg4 [80r,96r:0)  0@80r
		LHS = %vreg5 [96r,144r:0)  0@96r
		merge %vreg5:0@96r into %vreg4:0@80r --> @80r
		erased:	96r	%vreg5<def> = COPY %vreg4; GR64:%vreg5,%vreg4
		updated: 80B	%vreg5<def> = MOV64ri <ga:@BZ2_indexIntoF>; GR64:%vreg5
	Success: %vreg4 -> %vreg5
	Result = %vreg5 [80r,144r:0)  0@80r
784B	%vreg33<def> = COPY %vreg32; GR64:%vreg33,%vreg32
	Considering merging to GR64 with %vreg32 in %vreg33
		RHS = %vreg32 [768r,784r:0)  0@768r
		LHS = %vreg33 [784r,848r:0)  0@784r
		merge %vreg33:0@784r into %vreg32:0@768r --> @768r
		erased:	784r	%vreg33<def> = COPY %vreg32; GR64:%vreg33,%vreg32
		updated: 768B	%vreg33<def> = MOV64ri <ga:@BZ2_indexIntoF>; GR64:%vreg33
	Success: %vreg32 -> %vreg33
	Result = %vreg33 [768r,848r:0)  0@768r
144B	%RDI<def> = COPY %vreg5; GR64:%vreg5
	Considering merging %vreg5 with %RDI
	Can only merge into reserved registers.
848B	%RDI<def> = COPY %vreg33; GR64:%vreg33
	Considering merging %vreg33 with %RDI
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
DIL [0B,32r:0)[144r,176r:2)[848r,880r:1)  0@0B-phi 1@848r 2@144r
SIL [0B,16r:0)[160r,176r:2)[864r,880r:1)  0@0B-phi 1@864r 2@160r
%vreg1 [32r,256r:0)  0@32r
%vreg3 [16r,272r:0)  0@16r
%vreg5 [80r,144r:0)  0@80r
%vreg6 [112r,160r:0)  0@112r
%vreg11 [464r,480r:0)  0@464r
%vreg13 [448r,480r:0)  0@448r
%vreg14 [432r,480r:0)  0@432r
%vreg17 [336r,368r:2)[368r,400r:0)[400r,416r:1)  0@368r 1@400r 2@336r
%vreg23 [592r,608r:0)  0@592r
%vreg25 [528r,544r:0)  0@528r
%vreg29 [672r,704r:0)[704r,720r:1)  0@672r 1@704r
%vreg33 [768r,848r:0)  0@768r
%vreg34 [816r,864r:0)  0@816r
%vreg35 [800r,960r:0)  0@800r
RegMasks: 176r 880r
********** MACHINEINSTRS **********
# Machine code for function BZ2_indexIntoF: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=4, align=4, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=4, align=4, at location [SP+8]
  fi#3: size=4, align=4, at location [SP+8]
  fi#4: size=4, align=4, at location [SP+8]
Function Live Ins: %EDI in %vreg0, %RSI in %vreg2

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %EDI %RSI
16B		%vreg3<def> = COPY %RSI; GR64:%vreg3
32B		%vreg1<def> = COPY %EDI; GR32:%vreg1
80B		%vreg5<def> = MOV64ri <ga:@BZ2_indexIntoF>; GR64:%vreg5
112B		%vreg6<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg6
128B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
144B		%RDI<def> = COPY %vreg5; GR64:%vreg5
160B		%RSI<def> = COPY %vreg6; GR64:%vreg6
176B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
192B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
208B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#2>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack0](align=4) LD8[FixedStack4](align=4) LD8[FixedStack3](align=4) LD8[FixedStack2](align=4) GR64:%vreg3 GR32:%vreg1
240B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
256B		MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1; mem:ST4[%indx.addr] GR32:%vreg1
272B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg3; mem:ST8[%cftab.addr] GR64:%vreg3
288B		MOV32mi <fi#2>, 1, %noreg, 0, %noreg, 0; mem:ST4[%nb]
304B		MOV32mi <fi#3>, 1, %noreg, 0, %noreg, 256; mem:ST4[%na]
	    Successors according to CFG: BB#1

320B	BB#1: derived from LLVM BB %do.body
	    Predecessors according to CFG: BB#0 BB#5
336B		%vreg17<def> = MOV32rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD4[%nb] GR32:%vreg17
368B		%vreg17<def,tied1> = ADD32rm %vreg17<tied0>, <fi#3>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%na] GR32:%vreg17
400B		%vreg17<def,tied1> = SAR32ri %vreg17<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg17
416B		MOV32mr <fi#4>, 1, %noreg, 0, %noreg, %vreg17; mem:ST4[%mid] GR32:%vreg17
432B		%vreg14<def> = MOV32rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD4[%indx.addr] GR32:%vreg14
448B		%vreg13<def> = MOVSX64rm32 <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%mid] GR64_NOSP:%vreg13
464B		%vreg11<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%cftab.addr] GR64:%vreg11
480B		CMP32rm %vreg14, %vreg11, 4, %vreg13, 0, %noreg, %EFLAGS<imp-def>; mem:LD4[%arrayidx] GR32:%vreg14 GR64:%vreg11 GR64_NOSP:%vreg13
496B		JL_1 <BB#3>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#3 BB#2

512B	BB#2: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#1
528B		%vreg25<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%mid] GR32:%vreg25
544B		MOV32mr <fi#2>, 1, %noreg, 0, %noreg, %vreg25; mem:ST4[%nb] GR32:%vreg25
560B		JMP_1 <BB#4>
	    Successors according to CFG: BB#4

576B	BB#3: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#1
592B		%vreg23<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%mid] GR32:%vreg23
608B		MOV32mr <fi#3>, 1, %noreg, 0, %noreg, %vreg23; mem:ST4[%na] GR32:%vreg23
	    Successors according to CFG: BB#4

624B	BB#4: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#3 BB#2
640B		JMP_1 <BB#5>
	    Successors according to CFG: BB#5

656B	BB#5: derived from LLVM BB %do.cond
	    Predecessors according to CFG: BB#4
672B		%vreg29<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%na] GR32:%vreg29
704B		%vreg29<def,tied1> = SUB32rm %vreg29<tied0>, <fi#2>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%nb] GR32:%vreg29
720B		CMP32ri8 %vreg29, 1, %EFLAGS<imp-def>; GR32:%vreg29
736B		JNE_1 <BB#1>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#1 BB#6

752B	BB#6: derived from LLVM BB %do.end
	    Predecessors according to CFG: BB#5
768B		%vreg33<def> = MOV64ri <ga:@BZ2_indexIntoF>; GR64:%vreg33
800B		%vreg35<def> = MOV32rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD4[%nb] GR32:%vreg35
816B		%vreg34<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg34
832B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
848B		%RDI<def> = COPY %vreg33; GR64:%vreg33
864B		%RSI<def> = COPY %vreg34; GR64:%vreg34
880B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
896B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
912B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
928B		STACKMAP 1, 0, %vreg35, ...; GR32:%vreg35
944B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
960B		%EAX<def> = COPY %vreg35; GR32:%vreg35
976B		RETQ %EAX<imp-use,kill>

# End machine code for function BZ2_indexIntoF.

AllocationOrder(SEGMENT_REG) = [ ]
********** GREEDY REGISTER ALLOCATION **********
********** Function: BZ2_indexIntoF
********** INTERVALS **********
DIL [0B,32r:0)[144r,176r:2)[848r,880r:1)  0@0B-phi 1@848r 2@144r
SIL [0B,16r:0)[160r,176r:2)[864r,880r:1)  0@0B-phi 1@864r 2@160r
%vreg1 [32r,256r:0)  0@32r
%vreg3 [16r,272r:0)  0@16r
%vreg5 [80r,144r:0)  0@80r
%vreg6 [112r,160r:0)  0@112r
%vreg11 [464r,480r:0)  0@464r
%vreg13 [448r,480r:0)  0@448r
%vreg14 [432r,480r:0)  0@432r
%vreg17 [336r,368r:2)[368r,400r:0)[400r,416r:1)  0@368r 1@400r 2@336r
%vreg23 [592r,608r:0)  0@592r
%vreg25 [528r,544r:0)  0@528r
%vreg29 [672r,704r:0)[704r,720r:1)  0@672r 1@704r
%vreg33 [768r,848r:0)  0@768r
%vreg34 [816r,864r:0)  0@816r
%vreg35 [800r,960r:0)  0@800r
RegMasks: 176r 880r
********** MACHINEINSTRS **********
# Machine code for function BZ2_indexIntoF: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=4, align=4, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=4, align=4, at location [SP+8]
  fi#3: size=4, align=4, at location [SP+8]
  fi#4: size=4, align=4, at location [SP+8]
Function Live Ins: %EDI in %vreg0, %RSI in %vreg2

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %EDI %RSI
16B		%vreg3<def> = COPY %RSI; GR64:%vreg3
32B		%vreg1<def> = COPY %EDI; GR32:%vreg1
80B		%vreg5<def> = MOV64ri <ga:@BZ2_indexIntoF>; GR64:%vreg5
112B		%vreg6<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg6
128B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
144B		%RDI<def> = COPY %vreg5; GR64:%vreg5
160B		%RSI<def> = COPY %vreg6; GR64:%vreg6
176B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
192B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
208B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#2>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack0](align=4) LD8[FixedStack4](align=4) LD8[FixedStack3](align=4) LD8[FixedStack2](align=4) GR64:%vreg3 GR32:%vreg1
240B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
256B		MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1; mem:ST4[%indx.addr] GR32:%vreg1
272B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg3; mem:ST8[%cftab.addr] GR64:%vreg3
288B		MOV32mi <fi#2>, 1, %noreg, 0, %noreg, 0; mem:ST4[%nb]
304B		MOV32mi <fi#3>, 1, %noreg, 0, %noreg, 256; mem:ST4[%na]
	    Successors according to CFG: BB#1

320B	BB#1: derived from LLVM BB %do.body
	    Predecessors according to CFG: BB#0 BB#5
336B		%vreg17<def> = MOV32rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD4[%nb] GR32:%vreg17
368B		%vreg17<def,tied1> = ADD32rm %vreg17<tied0>, <fi#3>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%na] GR32:%vreg17
400B		%vreg17<def,tied1> = SAR32ri %vreg17<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg17
416B		MOV32mr <fi#4>, 1, %noreg, 0, %noreg, %vreg17; mem:ST4[%mid] GR32:%vreg17
432B		%vreg14<def> = MOV32rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD4[%indx.addr] GR32:%vreg14
448B		%vreg13<def> = MOVSX64rm32 <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%mid] GR64_NOSP:%vreg13
464B		%vreg11<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%cftab.addr] GR64:%vreg11
480B		CMP32rm %vreg14, %vreg11, 4, %vreg13, 0, %noreg, %EFLAGS<imp-def>; mem:LD4[%arrayidx] GR32:%vreg14 GR64:%vreg11 GR64_NOSP:%vreg13
496B		JL_1 <BB#3>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#3 BB#2

512B	BB#2: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#1
528B		%vreg25<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%mid] GR32:%vreg25
544B		MOV32mr <fi#2>, 1, %noreg, 0, %noreg, %vreg25; mem:ST4[%nb] GR32:%vreg25
560B		JMP_1 <BB#4>
	    Successors according to CFG: BB#4

576B	BB#3: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#1
592B		%vreg23<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%mid] GR32:%vreg23
608B		MOV32mr <fi#3>, 1, %noreg, 0, %noreg, %vreg23; mem:ST4[%na] GR32:%vreg23
	    Successors according to CFG: BB#4

624B	BB#4: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#3 BB#2
640B		JMP_1 <BB#5>
	    Successors according to CFG: BB#5

656B	BB#5: derived from LLVM BB %do.cond
	    Predecessors according to CFG: BB#4
672B		%vreg29<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%na] GR32:%vreg29
704B		%vreg29<def,tied1> = SUB32rm %vreg29<tied0>, <fi#2>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%nb] GR32:%vreg29
720B		CMP32ri8 %vreg29, 1, %EFLAGS<imp-def>; GR32:%vreg29
736B		JNE_1 <BB#1>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#1 BB#6

752B	BB#6: derived from LLVM BB %do.end
	    Predecessors according to CFG: BB#5
768B		%vreg33<def> = MOV64ri <ga:@BZ2_indexIntoF>; GR64:%vreg33
800B		%vreg35<def> = MOV32rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD4[%nb] GR32:%vreg35
816B		%vreg34<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg34
832B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
848B		%RDI<def> = COPY %vreg33; GR64:%vreg33
864B		%RSI<def> = COPY %vreg34; GR64:%vreg34
880B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
896B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
912B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
928B		STACKMAP 1, 0, %vreg35, ...; GR32:%vreg35
944B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
960B		%EAX<def> = COPY %vreg35; GR32:%vreg35
976B		RETQ %EAX<imp-use,kill>

# End machine code for function BZ2_indexIntoF.


selectOrSplit GR64:%vreg3 [16r,272r:0)  0@16r w=4.618902e-03
hints: %RSI
missed hint %RSI
assigning %vreg3 to %RBX: BH [16r,272r:0)  0@16r BL [16r,272r:0)  0@16r

selectOrSplit GR32:%vreg1 [32r,256r:0)  0@32r w=4.855769e-03
hints: %EDI
missed hint %EDI
%R14D is available at cost 1
Only trying the first 10 regs.
should evict: %vreg3 [16r,272r:0)  0@16r w= 4.618902e-03
hints: %RSI
can reassign: %vreg3 [16r,272r:0)  0@16r from %EBX to %RSI
should evict: %vreg3 [16r,272r:0)  0@16r w= 4.618902e-03
hints: %RSI
can reassign: %vreg3 [16r,272r:0)  0@16r from %EBX to %RSI
evicting %EBX interference: Cascade 1
unassigning %vreg3 from %RBX: BH BL
assigning %vreg1 to %EBX: BH [32r,256r:0)  0@32r BL [32r,256r:0)  0@32r
queuing new interval: %vreg3 [16r,272r:0)  0@16r

selectOrSplit GR64:%vreg3 [16r,272r:0)  0@16r w=4.618902e-03
hints: %RSI
missed hint %RSI
%R14 is available at cost 1
Only trying the first 10 regs.
assigning %vreg3 to %R14: R14B [16r,272r:0)  0@16r

selectOrSplit GR64:%vreg5 [80r,144r:0)  0@80r w=2.176724e-03
hints: %RDI
assigning %vreg5 to %RDI: DIL [80r,144r:0)  0@80r

selectOrSplit GR64:%vreg6 [112r,160r:0)  0@112r w=4.508928e-03
hints: %RSI
assigning %vreg6 to %RSI: SIL [112r,160r:0)  0@112r

selectOrSplit GR64:%vreg33 [768r,848r:0)  0@768r w=2.104167e-03
hints: %RDI
assigning %vreg33 to %RDI: DIL [768r,848r:0)  0@768r

selectOrSplit GR32:%vreg35 [800r,960r:0)  0@800r w=5.410714e-03
hints: %EAX
missed hint %EAX
assigning %vreg35 to %EBX: BH [800r,960r:0)  0@800r BL [800r,960r:0)  0@800r

selectOrSplit GR64:%vreg34 [816r,864r:0)  0@816r w=4.508928e-03
hints: %RSI
assigning %vreg34 to %RSI: SIL [816r,864r:0)  0@816r

selectOrSplit GR32:%vreg17 [336r,368r:2)[368r,400r:0)[400r,416r:1)  0@368r 1@400r 2@336r w=inf
assigning %vreg17 to %EAX: AH [336r,368r:2)[368r,400r:0)[400r,416r:1)  0@368r 1@400r 2@336r AL [336r,368r:2)[368r,400r:0)[400r,416r:1)  0@368r 1@400r 2@336r

selectOrSplit GR32:%vreg14 [432r,480r:0)  0@432r w=8.928572e-03
assigning %vreg14 to %EAX: AH [432r,480r:0)  0@432r AL [432r,480r:0)  0@432r

selectOrSplit GR64_NOSP:%vreg13 [448r,480r:0)  0@448r w=9.259259e-03
assigning %vreg13 to %RCX: CH [448r,480r:0)  0@448r CL [448r,480r:0)  0@448r

selectOrSplit GR64:%vreg11 [464r,480r:0)  0@464r w=inf
assigning %vreg11 to %RDX: DH [464r,480r:0)  0@464r DL [464r,480r:0)  0@464r

selectOrSplit GR32:%vreg25 [528r,544r:0)  0@528r w=inf
assigning %vreg25 to %EAX: AH [528r,544r:0)  0@528r AL [528r,544r:0)  0@528r

selectOrSplit GR32:%vreg23 [592r,608r:0)  0@592r w=inf
assigning %vreg23 to %EAX: AH [592r,608r:0)  0@592r AL [592r,608r:0)  0@592r

selectOrSplit GR32:%vreg29 [672r,704r:0)[704r,720r:1)  0@672r 1@704r w=inf
assigning %vreg29 to %EAX: AH [672r,704r:0)[704r,720r:1)  0@672r 1@704r AL [672r,704r:0)[704r,720r:1)  0@672r 1@704r

********** STACK TRANSFORMATION METADATA **********
********** Function: BZ2_indexIntoF
********** REGISTER MAP **********
[%vreg1 -> %EBX] GR32
[%vreg3 -> %R14] GR64
[%vreg5 -> %RDI] GR64
[%vreg6 -> %RSI] GR64
[%vreg11 -> %RDX] GR64
[%vreg13 -> %RCX] GR64_NOSP
[%vreg14 -> %EAX] GR32
[%vreg17 -> %EAX] GR32
[%vreg23 -> %EAX] GR32
[%vreg25 -> %EAX] GR32
[%vreg29 -> %EAX] GR32
[%vreg33 -> %RDI] GR64
[%vreg34 -> %RSI] GR64
[%vreg35 -> %EBX] GR32


Stackmap 0:
  STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#2>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack0](align=4) LD8[FixedStack4](align=4) LD8[FixedStack3](align=4) LD8[FixedStack2](align=4) GR64:%vreg3 GR32:%vreg1

i32* %cftab: in register %R14 (vreg 3)
i32** %cftab.addr: in stack slot 1 (size: 8)
i32 %indx: in register %EBX (vreg 1)
i32* %indx.addr: in stack slot 0 (size: 4)
i32* %mid: in stack slot 4 (size: 4)
i32* %na: in stack slot 3 (size: 4)
i32* %nb: in stack slot 2 (size: 4)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, %vreg35, ...; GR32:%vreg35

i32 %10: in register %EBX (vreg 35)

Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#2>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack0](align=4) LD8[FixedStack4](align=4) LD8[FixedStack3](align=4) LD8[FixedStack2](align=4) GR64:%vreg3 GR32:%vreg1
  -> Call instruction SlotIndex 176B, searching vregs 0 -> 36 and stack slots -1 -> 5

  STACKMAP 1, 0, %vreg35, ...; GR32:%vreg35
  -> Call instruction SlotIndex 880B, searching vregs 0 -> 36 and stack slots -1 -> 5

********** REWRITE VIRTUAL REGISTERS **********
********** Function: BZ2_indexIntoF
********** REGISTER MAP **********
[%vreg1 -> %EBX] GR32
[%vreg3 -> %R14] GR64
[%vreg5 -> %RDI] GR64
[%vreg6 -> %RSI] GR64
[%vreg11 -> %RDX] GR64
[%vreg13 -> %RCX] GR64_NOSP
[%vreg14 -> %EAX] GR32
[%vreg17 -> %EAX] GR32
[%vreg23 -> %EAX] GR32
[%vreg25 -> %EAX] GR32
[%vreg29 -> %EAX] GR32
[%vreg33 -> %RDI] GR64
[%vreg34 -> %RSI] GR64
[%vreg35 -> %EBX] GR32

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %EDI %RSI
16B		%vreg3<def> = COPY %RSI; GR64:%vreg3
32B		%vreg1<def> = COPY %EDI; GR32:%vreg1
80B		%vreg5<def> = MOV64ri <ga:@BZ2_indexIntoF>; GR64:%vreg5
112B		%vreg6<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg6
128B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
144B		%RDI<def> = COPY %vreg5<kill>; GR64:%vreg5
160B		%RSI<def> = COPY %vreg6<kill>; GR64:%vreg6
176B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
192B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
208B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#2>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack0](align=4) LD8[FixedStack4](align=4) LD8[FixedStack3](align=4) LD8[FixedStack2](align=4) GR64:%vreg3 GR32:%vreg1
240B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
256B		MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1<kill>; mem:ST4[%indx.addr] GR32:%vreg1
272B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg3<kill>; mem:ST8[%cftab.addr] GR64:%vreg3
288B		MOV32mi <fi#2>, 1, %noreg, 0, %noreg, 0; mem:ST4[%nb]
304B		MOV32mi <fi#3>, 1, %noreg, 0, %noreg, 256; mem:ST4[%na]
	    Successors according to CFG: BB#1
> %R14<def> = COPY %RSI
> %EBX<def> = COPY %EDI
> %RDI<def> = MOV64ri <ga:@BZ2_indexIntoF>
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 0, 0, %R14, 0, <fi#1>, 0, %EBX, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#2>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack0](align=4) LD8[FixedStack4](align=4) LD8[FixedStack3](align=4) LD8[FixedStack2](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %EBX<kill>; mem:ST4[%indx.addr]
> MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %R14<kill>; mem:ST8[%cftab.addr]
> MOV32mi <fi#2>, 1, %noreg, 0, %noreg, 0; mem:ST4[%nb]
> MOV32mi <fi#3>, 1, %noreg, 0, %noreg, 256; mem:ST4[%na]
320B	BB#1: derived from LLVM BB %do.body
	    Predecessors according to CFG: BB#0 BB#5
336B		%vreg17<def> = MOV32rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD4[%nb] GR32:%vreg17
368B		%vreg17<def,tied1> = ADD32rm %vreg17<kill,tied0>, <fi#3>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%na] GR32:%vreg17
400B		%vreg17<def,tied1> = SAR32ri %vreg17<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg17
416B		MOV32mr <fi#4>, 1, %noreg, 0, %noreg, %vreg17<kill>; mem:ST4[%mid] GR32:%vreg17
432B		%vreg14<def> = MOV32rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD4[%indx.addr] GR32:%vreg14
448B		%vreg13<def> = MOVSX64rm32 <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%mid] GR64_NOSP:%vreg13
464B		%vreg11<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%cftab.addr] GR64:%vreg11
480B		CMP32rm %vreg14<kill>, %vreg11<kill>, 4, %vreg13<kill>, 0, %noreg, %EFLAGS<imp-def>; mem:LD4[%arrayidx] GR32:%vreg14 GR64:%vreg11 GR64_NOSP:%vreg13
496B		JL_1 <BB#3>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#3 BB#2
> %EAX<def> = MOV32rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD4[%nb]
> %EAX<def,tied1> = ADD32rm %EAX<kill,tied0>, <fi#3>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%na]
> %EAX<def,tied1> = SAR32ri %EAX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV32mr <fi#4>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%mid]
> %EAX<def> = MOV32rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD4[%indx.addr]
> %RCX<def> = MOVSX64rm32 <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%mid]
> %RDX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%cftab.addr]
> CMP32rm %EAX<kill>, %RDX<kill>, 4, %RCX<kill>, 0, %noreg, %EFLAGS<imp-def>; mem:LD4[%arrayidx]
> JL_1 <BB#3>, %EFLAGS<imp-use,kill>
512B	BB#2: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#1
528B		%vreg25<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%mid] GR32:%vreg25
544B		MOV32mr <fi#2>, 1, %noreg, 0, %noreg, %vreg25<kill>; mem:ST4[%nb] GR32:%vreg25
560B		JMP_1 <BB#4>
	    Successors according to CFG: BB#4
> %EAX<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%mid]
> MOV32mr <fi#2>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%nb]
> JMP_1 <BB#4>
576B	BB#3: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#1
592B		%vreg23<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%mid] GR32:%vreg23
608B		MOV32mr <fi#3>, 1, %noreg, 0, %noreg, %vreg23<kill>; mem:ST4[%na] GR32:%vreg23
	    Successors according to CFG: BB#4
> %EAX<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%mid]
> MOV32mr <fi#3>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%na]
624B	BB#4: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#3 BB#2
640B		JMP_1 <BB#5>
	    Successors according to CFG: BB#5
> JMP_1 <BB#5>
656B	BB#5: derived from LLVM BB %do.cond
	    Predecessors according to CFG: BB#4
672B		%vreg29<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%na] GR32:%vreg29
704B		%vreg29<def,tied1> = SUB32rm %vreg29<kill,tied0>, <fi#2>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%nb] GR32:%vreg29
720B		CMP32ri8 %vreg29<kill>, 1, %EFLAGS<imp-def>; GR32:%vreg29
736B		JNE_1 <BB#1>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#1 BB#6
> %EAX<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%na]
> %EAX<def,tied1> = SUB32rm %EAX<kill,tied0>, <fi#2>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%nb]
> CMP32ri8 %EAX<kill>, 1, %EFLAGS<imp-def>
> JNE_1 <BB#1>, %EFLAGS<imp-use,kill>
752B	BB#6: derived from LLVM BB %do.end
	    Predecessors according to CFG: BB#5
768B		%vreg33<def> = MOV64ri <ga:@BZ2_indexIntoF>; GR64:%vreg33
800B		%vreg35<def> = MOV32rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD4[%nb] GR32:%vreg35
816B		%vreg34<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg34
832B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
848B		%RDI<def> = COPY %vreg33<kill>; GR64:%vreg33
864B		%RSI<def> = COPY %vreg34<kill>; GR64:%vreg34
880B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
896B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
912B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
928B		STACKMAP 1, 0, %vreg35, ...; GR32:%vreg35
944B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
960B		%EAX<def> = COPY %vreg35<kill>; GR32:%vreg35
976B		RETQ %EAX<imp-use>
> %RDI<def> = MOV64ri <ga:@BZ2_indexIntoF>
> %EBX<def> = MOV32rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD4[%nb]
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 1, 0, %EBX, ...
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def> = COPY %EBX<kill>
> RETQ %EAX<imp-use>
Computing live-in reg-units in ABI blocks.
0B	BB#0 DIL#0
Created 1 new intervals.
********** INTERVALS **********
DIL [0B,16r:0)[112r,144r:8)[928r,944r:6)[1120r,1136r:7)[1840r,1920r:5)[2144r,2192r:4)[2976r,2992r:3)[3328r,3408r:2)[3984r,4016r:1)  0@0B-phi 1@3984r 2@3328r 3@2976r 4@2144r 5@1840r 6@928r 7@1120r 8@112r
%vreg0 [16r,32r:0)  0@16r
%vreg1 [32r,224r:0)  0@32r
%vreg3 [48r,64r:0)  0@48r
%vreg4 [64r,112r:0)  0@64r
%vreg5 [80r,128r:0)  0@80r
%vreg9 [368r,384r:0)  0@368r
%vreg11 [352r,368r:0)  0@352r
%vreg12 [336r,352r:0)  0@336r
%vreg16 [512r,528r:0)  0@512r
%vreg17 [496r,512r:0)  0@496r
%vreg20 [656r,672r:0)  0@656r
%vreg23 [768r,784r:0)  0@768r
%vreg26 [832r,848r:0)  0@832r
%vreg29 [1168r,1232r:0)  0@1168r
%vreg30 [1088r,1120r:0)  0@1088r
%vreg33 [976r,1040r:0)  0@976r
%vreg34 [896r,928r:0)  0@896r
%vreg39 [1424r,1440r:0)[1440r,1456r:1)  0@1424r 1@1440r
%vreg41 [1408r,1424r:0)  0@1408r
%vreg42 [1392r,1408r:0)  0@1392r
%vreg44 [1376r,1456r:0)  0@1376r
%vreg45 [1360r,1376r:0)  0@1360r
%vreg48 [1504r,1520r:0)  0@1504r
%vreg51 [1664r,1680r:0)  0@1664r
%vreg54 [1632r,1648r:0)  0@1632r
%vreg56 [1600r,1616r:0)[1616r,1648r:1)  0@1600r 1@1616r
%vreg58 [1584r,1600r:0)  0@1584r
%vreg59 [1568r,1584r:0)  0@1568r
%vreg61 [1728r,1856r:0)  0@1728r
%vreg64 [1952r,1952d:0)  0@1952r
%vreg66 [1808r,1888r:0)  0@1808r
%vreg67 [1792r,1808r:0)  0@1792r
%vreg69 [1776r,1872r:0)  0@1776r
%vreg70 [1760r,1776r:0)  0@1760r
%vreg71 [1744r,1840r:0)  0@1744r
%vreg74 [2032r,2048r:0)  0@2032r
%vreg76 [2096r,2160r:0)  0@2096r
%vreg77 [2224r,2224d:0)  0@2224r
%vreg78 [2112r,2144r:0)  0@2112r
%vreg82 [2336r,2352r:0)  0@2336r
%vreg84 [2320r,2352r:0)  0@2320r
%vreg85 [2304r,2320r:0)  0@2304r
%vreg87 [2736r,2752r:0)  0@2736r
%vreg92 [2688r,2704r:0)[2704r,2720r:1)  0@2688r 1@2704r
%vreg93 [2672r,2720r:0)  0@2672r
%vreg95 [2656r,2688r:0)  0@2656r
%vreg96 [2640r,2656r:0)  0@2640r
%vreg99 [2608r,2624r:0)  0@2608r
%vreg102 [2576r,2592r:0)[2592r,2624r:1)  0@2576r 1@2592r
%vreg104 [2544r,2560r:0)[2560r,2592r:1)  0@2544r 1@2560r
%vreg106 [2528r,2544r:0)  0@2528r
%vreg107 [2512r,2528r:0)  0@2512r
%vreg109 [2480r,2496r:0)[2496r,2576r:1)  0@2480r 1@2496r
%vreg111 [2464r,2480r:0)  0@2464r
%vreg112 [2448r,2464r:0)  0@2448r
%vreg115 [2880r,2896r:0)  0@2880r
%vreg119 [3024r,3088r:0)  0@3024r
%vreg120 [2944r,2976r:0)  0@2944r
%vreg123 [3728r,3744r:0)  0@3728r
%vreg125 [3792r,3808r:0)  0@3792r
%vreg128 [3152r,3168r:0)  0@3152r
%vreg130 [3216r,3344r:0)  0@3216r
%vreg133 [3440r,3440d:0)  0@3440r
%vreg135 [3296r,3376r:0)  0@3296r
%vreg136 [3280r,3296r:0)  0@3280r
%vreg138 [3264r,3360r:0)  0@3264r
%vreg139 [3248r,3264r:0)  0@3248r
%vreg140 [3232r,3328r:0)  0@3232r
%vreg144 [3552r,3568r:0)  0@3552r
%vreg146 [3536r,3568r:0)  0@3536r
%vreg147 [3520r,3536r:0)  0@3520r
%vreg149 [3664r,3680r:0)  0@3664r
%vreg151 [4096r,4112r:0)  0@4096r
%vreg152 [3920r,3936r:0)  0@3920r
%vreg153 [3936r,3984r:0)  0@3936r
%vreg154 [3952r,4000r:0)  0@3952r
RegMasks: 144r 944r 1136r 1920r 2192r 2992r 3408r 4016r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzDecompress: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=4, align=4, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=1, align=1, at location [SP+8]
  fi#3: size=8, align=8, at location [SP+8]
  fi#4: size=4, align=4, at location [SP+8]
Function Live Ins: %RDI in %vreg0

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI
16B		%vreg0<def> = COPY %RDI; GR64:%vreg0
32B		%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
48B		%vreg3<def> = MOV64ri <ga:@BZ2_bzDecompress>; GR64:%vreg3
64B		%vreg4<def> = COPY %vreg3; GR64:%vreg4,%vreg3
80B		%vreg5<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg5
96B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
112B		%RDI<def> = COPY %vreg4; GR64:%vreg4
128B		%RSI<def> = COPY %vreg5; GR64:%vreg5
144B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
160B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
192B		STACKMAP 0, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, %vreg1, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3] LD8[FixedStack1] GR64:%vreg1
208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%strm.addr] GR64:%vreg1
240B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%strm.addr]
256B		JNE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

272B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
288B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
304B		JMP_1 <BB#37>
	    Successors according to CFG: BB#37

320B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0
336B		%vreg12<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg12
352B		%vreg11<def> = MOV64rm %vreg12, 1, %noreg, 48, %noreg; mem:LD8[%state] GR64:%vreg11,%vreg12
368B		%vreg9<def> = COPY %vreg11; GR64:%vreg9,%vreg11
384B		MOV64mr <fi#3>, 1, %noreg, 0, %noreg, %vreg9; mem:ST8[%s] GR64:%vreg9
400B		CMP64mi8 <fi#3>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%s]
416B		JNE_1 <BB#4>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#4 BB#3

432B	BB#3: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#2
448B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
464B		JMP_1 <BB#37>
	    Successors according to CFG: BB#37

480B	BB#4: derived from LLVM BB %if.end.3
	    Predecessors according to CFG: BB#2
496B		%vreg17<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg17
512B		%vreg16<def> = MOV64rm %vreg17, 1, %noreg, 0, %noreg; mem:LD8[%strm4] GR64:%vreg16,%vreg17
528B		CMP64rm %vreg16, <fi#1>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD8[%strm.addr] GR64:%vreg16
544B		JE_1 <BB#6>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#6 BB#5

560B	BB#5: derived from LLVM BB %if.then.6
	    Predecessors according to CFG: BB#4
576B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
592B		JMP_1 <BB#37>
	    Successors according to CFG: BB#37

608B	BB#6: derived from LLVM BB %if.end.7
	    Predecessors according to CFG: BB#4
624B		JMP_1 <BB#7>
	    Successors according to CFG: BB#7

640B	BB#7: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#6 BB#36
656B		%vreg20<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg20
672B		CMP32mi8 %vreg20, 1, %noreg, 8, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%state8] GR64:%vreg20
688B		JNE_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#8

704B	BB#8: derived from LLVM BB %if.then.10
	    Predecessors according to CFG: BB#7
720B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -1; mem:ST4[%retval]
736B		JMP_1 <BB#37>
	    Successors according to CFG: BB#37

752B	BB#9: derived from LLVM BB %if.end.11
	    Predecessors according to CFG: BB#7
768B		%vreg23<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg23
784B		CMP32mi8 %vreg23, 1, %noreg, 8, %noreg, 2, %EFLAGS<imp-def>; mem:LD4[%state12] GR64:%vreg23
800B		JNE_1 <BB#26>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#26 BB#10

816B	BB#10: derived from LLVM BB %if.then.14
	    Predecessors according to CFG: BB#9
832B		%vreg26<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg26
848B		CMP8mi %vreg26, 1, %noreg, 44, %noreg, 0, %EFLAGS<imp-def>; mem:LD1[%smallDecompress] GR64:%vreg26
864B		JE_1 <BB#12>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#12 BB#11

880B	BB#11: derived from LLVM BB %if.then.15
	    Predecessors according to CFG: BB#10
896B		%vreg34<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg34
912B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
928B		%RDI<def> = COPY %vreg34; GR64:%vreg34
944B		CALL64pcrel32 <ga:@unRLE_obuf_to_output_SMALL>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %AL<imp-def>
960B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
976B		%vreg33<def> = COPY %AL<kill>; GR8:%vreg33
992B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1008B		STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
1024B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1040B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg33; mem:ST1[%corrupt] GR8:%vreg33
1056B		JMP_1 <BB#13>
	    Successors according to CFG: BB#13

1072B	BB#12: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#10
1088B		%vreg30<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg30
1104B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1120B		%RDI<def> = COPY %vreg30; GR64:%vreg30
1136B		CALL64pcrel32 <ga:@unRLE_obuf_to_output_FAST>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %AL<imp-def>
1152B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1168B		%vreg29<def> = COPY %AL<kill>; GR8:%vreg29
1184B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1200B		STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
1216B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1232B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg29; mem:ST1[%corrupt] GR8:%vreg29
	    Successors according to CFG: BB#13

1248B	BB#13: derived from LLVM BB %if.end.17
	    Predecessors according to CFG: BB#12 BB#11
1264B		CMP8mi <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD1[%corrupt]
1280B		JE_1 <BB#15>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#15 BB#14

1296B	BB#14: derived from LLVM BB %if.then.19
	    Predecessors according to CFG: BB#13
1312B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -4; mem:ST4[%retval]
1328B		JMP_1 <BB#37>
	    Successors according to CFG: BB#37

1344B	BB#15: derived from LLVM BB %if.end.20
	    Predecessors according to CFG: BB#13
1360B		%vreg45<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg45
1376B		%vreg44<def> = MOV32rm %vreg45, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used] GR32:%vreg44 GR64:%vreg45
1392B		%vreg42<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg42
1408B		%vreg41<def> = MOV32rm %vreg42, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock] GR32:%vreg41 GR64:%vreg42
1424B		%vreg39<def> = COPY %vreg41; GR32:%vreg39,%vreg41
1440B		%vreg39<def,tied1> = ADD32ri8 %vreg39<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg39
1456B		CMP32rr %vreg44, %vreg39, %EFLAGS<imp-def>; GR32:%vreg44,%vreg39
1472B		JNE_1 <BB#24>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#24 BB#16

1488B	BB#16: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#15
1504B		%vreg48<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg48
1520B		CMP32mi8 %vreg48, 1, %noreg, 16, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%state_out_len] GR64:%vreg48
1536B		JNE_1 <BB#24>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#24 BB#17

1552B	BB#17: derived from LLVM BB %if.then.23
	    Predecessors according to CFG: BB#16
1568B		%vreg59<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg59
1584B		%vreg58<def> = MOV32rm %vreg59, 1, %noreg, 3184, %noreg; mem:LD4[%calculatedBlockCRC] GR32:%vreg58 GR64:%vreg59
1600B		%vreg56<def> = COPY %vreg58; GR32:%vreg56,%vreg58
1616B		%vreg56<def,tied1> = XOR32ri8 %vreg56<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg56
1632B		%vreg54<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg54
1648B		MOV32mr %vreg54, 1, %noreg, 3184, %noreg, %vreg56; mem:ST4[%calculatedBlockCRC24] GR64:%vreg54 GR32:%vreg56
1664B		%vreg51<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg51
1680B		CMP32mi8 %vreg51, 1, %noreg, 52, %noreg, 3, %EFLAGS<imp-def>; mem:LD4[%verbosity] GR64:%vreg51
1696B		JL_1 <BB#19>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#19 BB#18

1712B	BB#18: derived from LLVM BB %if.then.26
	    Predecessors according to CFG: BB#17
1728B		%vreg61<def> = MOV64ri <ga:@bzlib__str_2___0x_08x__>; GR64:%vreg61
1744B		%vreg71<def> = MOV64rm %noreg, 1, %noreg, <ga:@stderr>, %noreg; mem:LD8[@stderr] GR64:%vreg71
1760B		%vreg70<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg70
1776B		%vreg69<def> = MOV32rm %vreg70, 1, %noreg, 3176, %noreg; mem:LD4[%storedBlockCRC] GR32:%vreg69 GR64:%vreg70
1792B		%vreg67<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg67
1808B		%vreg66<def> = MOV32rm %vreg67, 1, %noreg, 3184, %noreg; mem:LD4[%calculatedBlockCRC27] GR32:%vreg66 GR64:%vreg67
1824B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1840B		%RDI<def> = COPY %vreg71; GR64:%vreg71
1856B		%RSI<def> = COPY %vreg61; GR64:%vreg61
1872B		%EDX<def> = COPY %vreg69; GR32:%vreg69
1888B		%ECX<def> = COPY %vreg66; GR32:%vreg66
1904B		%AL<def> = MOV8ri 0
1920B		CALL64pcrel32 <ga:@fprintf>, <regmask>, %RSP<imp-use>, %AL<imp-use,kill>, %RDI<imp-use>, %RSI<imp-use,kill>, %EDX<imp-use,kill>, %ECX<imp-use,kill>, %EAX<imp-def>
1936B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1952B		%vreg64<def,dead> = COPY %EAX<kill>; GR32:%vreg64
1968B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1984B		STACKMAP 3, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
2000B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#19

2016B	BB#19: derived from LLVM BB %if.end.29
	    Predecessors according to CFG: BB#17 BB#18
2032B		%vreg74<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg74
2048B		CMP32mi8 %vreg74, 1, %noreg, 52, %noreg, 2, %EFLAGS<imp-def>; mem:LD4[%verbosity30] GR64:%vreg74
2064B		JL_1 <BB#21>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#21 BB#20

2080B	BB#20: derived from LLVM BB %if.then.32
	    Predecessors according to CFG: BB#19
2096B		%vreg76<def> = MOV64ri <ga:@bzlib__str_3___>; GR64:%vreg76
2112B		%vreg78<def> = MOV64rm %noreg, 1, %noreg, <ga:@stderr>, %noreg; mem:LD8[@stderr] GR64:%vreg78
2128B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2144B		%RDI<def> = COPY %vreg78; GR64:%vreg78
2160B		%RSI<def> = COPY %vreg76; GR64:%vreg76
2176B		%AL<def> = MOV8ri 0
2192B		CALL64pcrel32 <ga:@fprintf>, <regmask>, %RSP<imp-use>, %AL<imp-use,kill>, %RDI<imp-use>, %RSI<imp-use,kill>, %EAX<imp-def>
2208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2224B		%vreg77<def,dead> = COPY %EAX<kill>; GR32:%vreg77
2240B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2256B		STACKMAP 4, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
2272B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#21

2288B	BB#21: derived from LLVM BB %if.end.34
	    Predecessors according to CFG: BB#19 BB#20
2304B		%vreg85<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg85
2320B		%vreg84<def> = MOV32rm %vreg85, 1, %noreg, 3184, %noreg; mem:LD4[%calculatedBlockCRC35] GR32:%vreg84 GR64:%vreg85
2336B		%vreg82<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg82
2352B		CMP32rm %vreg84, %vreg82, 1, %noreg, 3176, %noreg, %EFLAGS<imp-def>; mem:LD4[%storedBlockCRC36] GR32:%vreg84 GR64:%vreg82
2368B		JE_1 <BB#23>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#23 BB#22

2384B	BB#22: derived from LLVM BB %if.then.38
	    Predecessors according to CFG: BB#21
2400B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -4; mem:ST4[%retval]
2416B		JMP_1 <BB#37>
	    Successors according to CFG: BB#37

2432B	BB#23: derived from LLVM BB %if.end.39
	    Predecessors according to CFG: BB#21
2448B		%vreg112<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg112
2464B		%vreg111<def> = MOV32rm %vreg112, 1, %noreg, 3188, %noreg; mem:LD4[%calculatedCombinedCRC] GR32:%vreg111 GR64:%vreg112
2480B		%vreg109<def> = COPY %vreg111; GR32:%vreg109,%vreg111
2496B		%vreg109<def,tied1> = SHL32ri %vreg109<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg109
2512B		%vreg107<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg107
2528B		%vreg106<def> = MOV32rm %vreg107, 1, %noreg, 3188, %noreg; mem:LD4[%calculatedCombinedCRC40] GR32:%vreg106 GR64:%vreg107
2544B		%vreg104<def> = COPY %vreg106; GR32:%vreg104,%vreg106
2560B		%vreg104<def,tied1> = SHR32ri %vreg104<tied0>, 31, %EFLAGS<imp-def,dead>; GR32:%vreg104
2576B		%vreg102<def> = COPY %vreg109; GR32:%vreg102,%vreg109
2592B		%vreg102<def,tied1> = OR32rr %vreg102<tied0>, %vreg104, %EFLAGS<imp-def,dead>; GR32:%vreg102,%vreg104
2608B		%vreg99<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg99
2624B		MOV32mr %vreg99, 1, %noreg, 3188, %noreg, %vreg102; mem:ST4[%calculatedCombinedCRC41] GR64:%vreg99 GR32:%vreg102
2640B		%vreg96<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg96
2656B		%vreg95<def> = MOV32rm %vreg96, 1, %noreg, 3184, %noreg; mem:LD4[%calculatedBlockCRC42] GR32:%vreg95 GR64:%vreg96
2672B		%vreg93<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg93
2688B		%vreg92<def> = COPY %vreg95; GR32:%vreg92,%vreg95
2704B		%vreg92<def,tied1> = XOR32rm %vreg92<tied0>, %vreg93, 1, %noreg, 3188, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%calculatedCombinedCRC43] GR32:%vreg92 GR64:%vreg93
2720B		MOV32mr %vreg93, 1, %noreg, 3188, %noreg, %vreg92; mem:ST4[%calculatedCombinedCRC43] GR64:%vreg93 GR32:%vreg92
2736B		%vreg87<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg87
2752B		MOV32mi %vreg87, 1, %noreg, 8, %noreg, 14; mem:ST4[%state44] GR64:%vreg87
2768B		JMP_1 <BB#25>
	    Successors according to CFG: BB#25

2784B	BB#24: derived from LLVM BB %if.else.45
	    Predecessors according to CFG: BB#15 BB#16
2800B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
2816B		JMP_1 <BB#37>
	    Successors according to CFG: BB#37

2832B	BB#25: derived from LLVM BB %if.end.46
	    Predecessors according to CFG: BB#23
2848B		JMP_1 <BB#26>
	    Successors according to CFG: BB#26

2864B	BB#26: derived from LLVM BB %if.end.47
	    Predecessors according to CFG: BB#9 BB#25
2880B		%vreg115<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg115
2896B		CMP32mi8 %vreg115, 1, %noreg, 8, %noreg, 10, %EFLAGS<imp-def>; mem:LD4[%state48] GR64:%vreg115
2912B		JL_1 <BB#36>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#36 BB#27

2928B	BB#27: derived from LLVM BB %if.then.50
	    Predecessors according to CFG: BB#26
2944B		%vreg120<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg120
2960B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2976B		%RDI<def> = COPY %vreg120; GR64:%vreg120
2992B		CALL64pcrel32 <ga:@BZ2_decompress>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
3008B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3024B		%vreg119<def> = COPY %EAX<kill>; GR32:%vreg119
3040B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3056B		STACKMAP 5, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
3072B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3088B		MOV32mr <fi#4>, 1, %noreg, 0, %noreg, %vreg119; mem:ST4[%r] GR32:%vreg119
3104B		CMP32mi8 <fi#4>, 1, %noreg, 0, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%r]
3120B		JNE_1 <BB#33>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#33 BB#28

3136B	BB#28: derived from LLVM BB %if.then.53
	    Predecessors according to CFG: BB#27
3152B		%vreg128<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg128
3168B		CMP32mi8 %vreg128, 1, %noreg, 52, %noreg, 3, %EFLAGS<imp-def>; mem:LD4[%verbosity54] GR64:%vreg128
3184B		JL_1 <BB#30>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#30 BB#29

3200B	BB#29: derived from LLVM BB %if.then.56
	    Predecessors according to CFG: BB#28
3216B		%vreg130<def> = MOV64ri <ga:@bzlib__str_4______combi>; GR64:%vreg130
3232B		%vreg140<def> = MOV64rm %noreg, 1, %noreg, <ga:@stderr>, %noreg; mem:LD8[@stderr] GR64:%vreg140
3248B		%vreg139<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg139
3264B		%vreg138<def> = MOV32rm %vreg139, 1, %noreg, 3180, %noreg; mem:LD4[%storedCombinedCRC] GR32:%vreg138 GR64:%vreg139
3280B		%vreg136<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg136
3296B		%vreg135<def> = MOV32rm %vreg136, 1, %noreg, 3188, %noreg; mem:LD4[%calculatedCombinedCRC57] GR32:%vreg135 GR64:%vreg136
3312B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3328B		%RDI<def> = COPY %vreg140; GR64:%vreg140
3344B		%RSI<def> = COPY %vreg130; GR64:%vreg130
3360B		%EDX<def> = COPY %vreg138; GR32:%vreg138
3376B		%ECX<def> = COPY %vreg135; GR32:%vreg135
3392B		%AL<def> = MOV8ri 0
3408B		CALL64pcrel32 <ga:@fprintf>, <regmask>, %RSP<imp-use>, %AL<imp-use,kill>, %RDI<imp-use>, %RSI<imp-use,kill>, %EDX<imp-use,kill>, %ECX<imp-use,kill>, %EAX<imp-def>
3424B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3440B		%vreg133<def,dead> = COPY %EAX<kill>; GR32:%vreg133
3456B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3472B		STACKMAP 6, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
3488B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#30

3504B	BB#30: derived from LLVM BB %if.end.59
	    Predecessors according to CFG: BB#28 BB#29
3520B		%vreg147<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg147
3536B		%vreg146<def> = MOV32rm %vreg147, 1, %noreg, 3188, %noreg; mem:LD4[%calculatedCombinedCRC60] GR32:%vreg146 GR64:%vreg147
3552B		%vreg144<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg144
3568B		CMP32rm %vreg146, %vreg144, 1, %noreg, 3180, %noreg, %EFLAGS<imp-def>; mem:LD4[%storedCombinedCRC61] GR32:%vreg146 GR64:%vreg144
3584B		JE_1 <BB#32>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#32 BB#31

3600B	BB#31: derived from LLVM BB %if.then.63
	    Predecessors according to CFG: BB#30
3616B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -4; mem:ST4[%retval]
3632B		JMP_1 <BB#37>
	    Successors according to CFG: BB#37

3648B	BB#32: derived from LLVM BB %if.end.64
	    Predecessors according to CFG: BB#30
3664B		%vreg149<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%r] GR32:%vreg149
3680B		MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %vreg149; mem:ST4[%retval] GR32:%vreg149
3696B		JMP_1 <BB#37>
	    Successors according to CFG: BB#37

3712B	BB#33: derived from LLVM BB %if.end.65
	    Predecessors according to CFG: BB#27
3728B		%vreg123<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg123
3744B		CMP32mi8 %vreg123, 1, %noreg, 8, %noreg, 2, %EFLAGS<imp-def>; mem:LD4[%state66] GR64:%vreg123
3760B		JE_1 <BB#35>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#35 BB#34

3776B	BB#34: derived from LLVM BB %if.then.68
	    Predecessors according to CFG: BB#33
3792B		%vreg125<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%r] GR32:%vreg125
3808B		MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %vreg125; mem:ST4[%retval] GR32:%vreg125
3824B		JMP_1 <BB#37>
	    Successors according to CFG: BB#37

3840B	BB#35: derived from LLVM BB %if.end.69
	    Predecessors according to CFG: BB#33
3856B		JMP_1 <BB#36>
	    Successors according to CFG: BB#36

3872B	BB#36: derived from LLVM BB %if.end.70
	    Predecessors according to CFG: BB#26 BB#35
3888B		JMP_1 <BB#7>
	    Successors according to CFG: BB#7

3904B	BB#37: derived from LLVM BB %return
	    Predecessors according to CFG: BB#24 BB#34 BB#32 BB#31 BB#22 BB#14 BB#8 BB#5 BB#3 BB#1
3920B		%vreg152<def> = MOV64ri <ga:@BZ2_bzDecompress>; GR64:%vreg152
3936B		%vreg153<def> = COPY %vreg152; GR64:%vreg153,%vreg152
3952B		%vreg154<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg154
3968B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3984B		%RDI<def> = COPY %vreg153; GR64:%vreg153
4000B		%RSI<def> = COPY %vreg154; GR64:%vreg154
4016B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
4032B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4048B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4064B		STACKMAP 7, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
4080B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4096B		%vreg151<def> = MOV32rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD4[%retval] GR32:%vreg151
4112B		%EAX<def> = COPY %vreg151; GR32:%vreg151
4128B		RETQ %EAX<imp-use,kill>

# End machine code for function BZ2_bzDecompress.

********** SIMPLE REGISTER COALESCING **********
********** Function: BZ2_bzDecompress
********** JOINING INTERVALS ***********
while.body:
if.end.17:
if.end.29:
if.end.34:
if.end.47:
if.end.11:
if.then.14:
if.end.20:
land.lhs.true:
if.then.23:
if.then.50:
2976B	%RDI<def> = COPY %vreg120; GR64:%vreg120
	Considering merging %vreg120 with %RDI
	Can only merge into reserved registers.
3024B	%vreg119<def> = COPY %EAX<kill>; GR32:%vreg119
	Considering merging %vreg119 with %EAX
	Can only merge into reserved registers.
if.end.65:
if.end.70:
if.then.15:
928B	%RDI<def> = COPY %vreg34; GR64:%vreg34
	Considering merging %vreg34 with %RDI
	Can only merge into reserved registers.
976B	%vreg33<def> = COPY %AL<kill>; GR8:%vreg33
	Considering merging %vreg33 with %AL
	Can only merge into reserved registers.
if.else:
1120B	%RDI<def> = COPY %vreg30; GR64:%vreg30
	Considering merging %vreg30 with %RDI
	Can only merge into reserved registers.
1168B	%vreg29<def> = COPY %AL<kill>; GR8:%vreg29
	Considering merging %vreg29 with %AL
	Can only merge into reserved registers.
if.then.26:
1840B	%RDI<def> = COPY %vreg71; GR64:%vreg71
	Considering merging %vreg71 with %RDI
	Can only merge into reserved registers.
1856B	%RSI<def> = COPY %vreg61; GR64:%vreg61
	Considering merging %vreg61 with %RSI
	Can only merge into reserved registers.
1872B	%EDX<def> = COPY %vreg69; GR32:%vreg69
	Considering merging %vreg69 with %EDX
	Can only merge into reserved registers.
1888B	%ECX<def> = COPY %vreg66; GR32:%vreg66
	Considering merging %vreg66 with %ECX
	Can only merge into reserved registers.
1952B	%vreg64<def,dead> = COPY %EAX<kill>; GR32:%vreg64
	Considering merging %vreg64 with %EAX
	Can only merge into reserved registers.
if.then.32:
2144B	%RDI<def> = COPY %vreg78; GR64:%vreg78
	Considering merging %vreg78 with %RDI
	Can only merge into reserved registers.
2160B	%RSI<def> = COPY %vreg76; GR64:%vreg76
	Considering merging %vreg76 with %RSI
	Can only merge into reserved registers.
2224B	%vreg77<def,dead> = COPY %EAX<kill>; GR32:%vreg77
	Considering merging %vreg77 with %EAX
	Can only merge into reserved registers.
if.end.39:
if.end.46:
if.end.69:
1424B	%vreg39<def> = COPY %vreg41; GR32:%vreg39,%vreg41
	Considering merging to GR32 with %vreg41 in %vreg39
		RHS = %vreg41 [1408r,1424r:0)  0@1408r
		LHS = %vreg39 [1424r,1440r:0)[1440r,1456r:1)  0@1424r 1@1440r
		merge %vreg39:0@1424r into %vreg41:0@1408r --> @1408r
		erased:	1424r	%vreg39<def> = COPY %vreg41; GR32:%vreg39,%vreg41
		updated: 1408B	%vreg39<def> = MOV32rm %vreg42, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock] GR32:%vreg39 GR64:%vreg42
	Success: %vreg41 -> %vreg39
	Result = %vreg39 [1408r,1440r:0)[1440r,1456r:1)  0@1408r 1@1440r
1600B	%vreg56<def> = COPY %vreg58; GR32:%vreg56,%vreg58
	Considering merging to GR32 with %vreg58 in %vreg56
		RHS = %vreg58 [1584r,1600r:0)  0@1584r
		LHS = %vreg56 [1600r,1616r:0)[1616r,1648r:1)  0@1600r 1@1616r
		merge %vreg56:0@1600r into %vreg58:0@1584r --> @1584r
		erased:	1600r	%vreg56<def> = COPY %vreg58; GR32:%vreg56,%vreg58
		updated: 1584B	%vreg56<def> = MOV32rm %vreg59, 1, %noreg, 3184, %noreg; mem:LD4[%calculatedBlockCRC] GR32:%vreg56 GR64:%vreg59
	Success: %vreg58 -> %vreg56
	Result = %vreg56 [1584r,1616r:0)[1616r,1648r:1)  0@1584r 1@1616r
2480B	%vreg109<def> = COPY %vreg111; GR32:%vreg109,%vreg111
	Considering merging to GR32 with %vreg111 in %vreg109
		RHS = %vreg111 [2464r,2480r:0)  0@2464r
		LHS = %vreg109 [2480r,2496r:0)[2496r,2576r:1)  0@2480r 1@2496r
		merge %vreg109:0@2480r into %vreg111:0@2464r --> @2464r
		erased:	2480r	%vreg109<def> = COPY %vreg111; GR32:%vreg109,%vreg111
		updated: 2464B	%vreg109<def> = MOV32rm %vreg112, 1, %noreg, 3188, %noreg; mem:LD4[%calculatedCombinedCRC] GR32:%vreg109 GR64:%vreg112
	Success: %vreg111 -> %vreg109
	Result = %vreg109 [2464r,2496r:0)[2496r,2576r:1)  0@2464r 1@2496r
2544B	%vreg104<def> = COPY %vreg106; GR32:%vreg104,%vreg106
	Considering merging to GR32 with %vreg106 in %vreg104
		RHS = %vreg106 [2528r,2544r:0)  0@2528r
		LHS = %vreg104 [2544r,2560r:0)[2560r,2592r:1)  0@2544r 1@2560r
		merge %vreg104:0@2544r into %vreg106:0@2528r --> @2528r
		erased:	2544r	%vreg104<def> = COPY %vreg106; GR32:%vreg104,%vreg106
		updated: 2528B	%vreg104<def> = MOV32rm %vreg107, 1, %noreg, 3188, %noreg; mem:LD4[%calculatedCombinedCRC40] GR32:%vreg104 GR64:%vreg107
	Success: %vreg106 -> %vreg104
	Result = %vreg104 [2528r,2560r:0)[2560r,2592r:1)  0@2528r 1@2560r
2576B	%vreg102<def> = COPY %vreg109; GR32:%vreg102,%vreg109
	Considering merging to GR32 with %vreg109 in %vreg102
		RHS = %vreg109 [2464r,2496r:0)[2496r,2576r:1)  0@2464r 1@2496r
		LHS = %vreg102 [2576r,2592r:0)[2592r,2624r:1)  0@2576r 1@2592r
		merge %vreg102:0@2576r into %vreg109:1@2496r --> @2496r
		erased:	2576r	%vreg102<def> = COPY %vreg109; GR32:%vreg102,%vreg109
		updated: 2464B	%vreg102<def> = MOV32rm %vreg112, 1, %noreg, 3188, %noreg; mem:LD4[%calculatedCombinedCRC] GR32:%vreg102 GR64:%vreg112
		updated: 2496B	%vreg102<def,tied1> = SHL32ri %vreg102<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg102
	Success: %vreg109 -> %vreg102
	Result = %vreg102 [2464r,2496r:2)[2496r,2592r:0)[2592r,2624r:1)  0@2496r 1@2592r 2@2464r
2688B	%vreg92<def> = COPY %vreg95; GR32:%vreg92,%vreg95
	Considering merging to GR32 with %vreg95 in %vreg92
		RHS = %vreg95 [2656r,2688r:0)  0@2656r
		LHS = %vreg92 [2688r,2704r:0)[2704r,2720r:1)  0@2688r 1@2704r
		merge %vreg92:0@2688r into %vreg95:0@2656r --> @2656r
		erased:	2688r	%vreg92<def> = COPY %vreg95; GR32:%vreg92,%vreg95
		updated: 2656B	%vreg92<def> = MOV32rm %vreg96, 1, %noreg, 3184, %noreg; mem:LD4[%calculatedBlockCRC42] GR32:%vreg92 GR64:%vreg96
	Success: %vreg95 -> %vreg92
	Result = %vreg92 [2656r,2704r:0)[2704r,2720r:1)  0@2656r 1@2704r
return:
3984B	%RDI<def> = COPY %vreg153; GR64:%vreg153
	Considering merging %vreg153 with %RDI
	Can only merge into reserved registers.
4000B	%RSI<def> = COPY %vreg154; GR64:%vreg154
	Considering merging %vreg154 with %RSI
	Can only merge into reserved registers.
4112B	%EAX<def> = COPY %vreg151; GR32:%vreg151
	Considering merging %vreg151 with %EAX
	Can only merge into reserved registers.
if.end.59:
if.end:
if.end.3:
if.else.45:
if.then.53:
entry:
16B	%vreg0<def> = COPY %RDI; GR64:%vreg0
	Considering merging %vreg0 with %RDI
	Can only merge into reserved registers.
112B	%RDI<def> = COPY %vreg4; GR64:%vreg4
	Considering merging %vreg4 with %RDI
	Can only merge into reserved registers.
128B	%RSI<def> = COPY %vreg5; GR64:%vreg5
	Considering merging %vreg5 with %RSI
	Can only merge into reserved registers.
if.then:
if.then.2:
if.then.6:
if.end.7:
if.then.10:
if.then.19:
if.then.38:
if.then.56:
3328B	%RDI<def> = COPY %vreg140; GR64:%vreg140
	Considering merging %vreg140 with %RDI
	Can only merge into reserved registers.
3344B	%RSI<def> = COPY %vreg130; GR64:%vreg130
	Considering merging %vreg130 with %RSI
	Can only merge into reserved registers.
3360B	%EDX<def> = COPY %vreg138; GR32:%vreg138
	Considering merging %vreg138 with %EDX
	Can only merge into reserved registers.
3376B	%ECX<def> = COPY %vreg135; GR32:%vreg135
	Considering merging %vreg135 with %ECX
	Can only merge into reserved registers.
3440B	%vreg133<def,dead> = COPY %EAX<kill>; GR32:%vreg133
	Considering merging %vreg133 with %EAX
	Can only merge into reserved registers.
if.then.63:
if.end.64:
if.then.68:
3936B	%vreg153<def> = COPY %vreg152; GR64:%vreg153,%vreg152
	Considering merging to GR64 with %vreg152 in %vreg153
		RHS = %vreg152 [3920r,3936r:0)  0@3920r
		LHS = %vreg153 [3936r,3984r:0)  0@3936r
		merge %vreg153:0@3936r into %vreg152:0@3920r --> @3920r
		erased:	3936r	%vreg153<def> = COPY %vreg152; GR64:%vreg153,%vreg152
		updated: 3920B	%vreg153<def> = MOV64ri <ga:@BZ2_bzDecompress>; GR64:%vreg153
	Success: %vreg152 -> %vreg153
	Result = %vreg153 [3920r,3984r:0)  0@3920r
368B	%vreg9<def> = COPY %vreg11; GR64:%vreg9,%vreg11
	Considering merging to GR64 with %vreg11 in %vreg9
		RHS = %vreg11 [352r,368r:0)  0@352r
		LHS = %vreg9 [368r,384r:0)  0@368r
		merge %vreg9:0@368r into %vreg11:0@352r --> @352r
		erased:	368r	%vreg9<def> = COPY %vreg11; GR64:%vreg9,%vreg11
		updated: 352B	%vreg9<def> = MOV64rm %vreg12, 1, %noreg, 48, %noreg; mem:LD8[%state] GR64:%vreg9,%vreg12
	Success: %vreg11 -> %vreg9
	Result = %vreg9 [352r,384r:0)  0@352r
32B	%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
	Considering merging to GR64 with %vreg0 in %vreg1
		RHS = %vreg0 [16r,32r:0)  0@16r
		LHS = %vreg1 [32r,224r:0)  0@32r
		merge %vreg1:0@32r into %vreg0:0@16r --> @16r
		erased:	32r	%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
		updated: 16B	%vreg1<def> = COPY %RDI; GR64:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [16r,224r:0)  0@16r
64B	%vreg4<def> = COPY %vreg3; GR64:%vreg4,%vreg3
	Considering merging to GR64 with %vreg3 in %vreg4
		RHS = %vreg3 [48r,64r:0)  0@48r
		LHS = %vreg4 [64r,112r:0)  0@64r
		merge %vreg4:0@64r into %vreg3:0@48r --> @48r
		erased:	64r	%vreg4<def> = COPY %vreg3; GR64:%vreg4,%vreg3
		updated: 48B	%vreg4<def> = MOV64ri <ga:@BZ2_bzDecompress>; GR64:%vreg4
	Success: %vreg3 -> %vreg4
	Result = %vreg4 [48r,112r:0)  0@48r
3984B	%RDI<def> = COPY %vreg153; GR64:%vreg153
	Considering merging %vreg153 with %RDI
	Can only merge into reserved registers.
112B	%RDI<def> = COPY %vreg4; GR64:%vreg4
	Considering merging %vreg4 with %RDI
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
DIL [0B,16r:0)[112r,144r:8)[928r,944r:6)[1120r,1136r:7)[1840r,1920r:5)[2144r,2192r:4)[2976r,2992r:3)[3328r,3408r:2)[3984r,4016r:1)  0@0B-phi 1@3984r 2@3328r 3@2976r 4@2144r 5@1840r 6@928r 7@1120r 8@112r
%vreg1 [16r,224r:0)  0@16r
%vreg4 [48r,112r:0)  0@48r
%vreg5 [80r,128r:0)  0@80r
%vreg9 [352r,384r:0)  0@352r
%vreg12 [336r,352r:0)  0@336r
%vreg16 [512r,528r:0)  0@512r
%vreg17 [496r,512r:0)  0@496r
%vreg20 [656r,672r:0)  0@656r
%vreg23 [768r,784r:0)  0@768r
%vreg26 [832r,848r:0)  0@832r
%vreg29 [1168r,1232r:0)  0@1168r
%vreg30 [1088r,1120r:0)  0@1088r
%vreg33 [976r,1040r:0)  0@976r
%vreg34 [896r,928r:0)  0@896r
%vreg39 [1408r,1440r:0)[1440r,1456r:1)  0@1408r 1@1440r
%vreg42 [1392r,1408r:0)  0@1392r
%vreg44 [1376r,1456r:0)  0@1376r
%vreg45 [1360r,1376r:0)  0@1360r
%vreg48 [1504r,1520r:0)  0@1504r
%vreg51 [1664r,1680r:0)  0@1664r
%vreg54 [1632r,1648r:0)  0@1632r
%vreg56 [1584r,1616r:0)[1616r,1648r:1)  0@1584r 1@1616r
%vreg59 [1568r,1584r:0)  0@1568r
%vreg61 [1728r,1856r:0)  0@1728r
%vreg64 [1952r,1952d:0)  0@1952r
%vreg66 [1808r,1888r:0)  0@1808r
%vreg67 [1792r,1808r:0)  0@1792r
%vreg69 [1776r,1872r:0)  0@1776r
%vreg70 [1760r,1776r:0)  0@1760r
%vreg71 [1744r,1840r:0)  0@1744r
%vreg74 [2032r,2048r:0)  0@2032r
%vreg76 [2096r,2160r:0)  0@2096r
%vreg77 [2224r,2224d:0)  0@2224r
%vreg78 [2112r,2144r:0)  0@2112r
%vreg82 [2336r,2352r:0)  0@2336r
%vreg84 [2320r,2352r:0)  0@2320r
%vreg85 [2304r,2320r:0)  0@2304r
%vreg87 [2736r,2752r:0)  0@2736r
%vreg92 [2656r,2704r:0)[2704r,2720r:1)  0@2656r 1@2704r
%vreg93 [2672r,2720r:0)  0@2672r
%vreg96 [2640r,2656r:0)  0@2640r
%vreg99 [2608r,2624r:0)  0@2608r
%vreg102 [2464r,2496r:2)[2496r,2592r:0)[2592r,2624r:1)  0@2496r 1@2592r 2@2464r
%vreg104 [2528r,2560r:0)[2560r,2592r:1)  0@2528r 1@2560r
%vreg107 [2512r,2528r:0)  0@2512r
%vreg112 [2448r,2464r:0)  0@2448r
%vreg115 [2880r,2896r:0)  0@2880r
%vreg119 [3024r,3088r:0)  0@3024r
%vreg120 [2944r,2976r:0)  0@2944r
%vreg123 [3728r,3744r:0)  0@3728r
%vreg125 [3792r,3808r:0)  0@3792r
%vreg128 [3152r,3168r:0)  0@3152r
%vreg130 [3216r,3344r:0)  0@3216r
%vreg133 [3440r,3440d:0)  0@3440r
%vreg135 [3296r,3376r:0)  0@3296r
%vreg136 [3280r,3296r:0)  0@3280r
%vreg138 [3264r,3360r:0)  0@3264r
%vreg139 [3248r,3264r:0)  0@3248r
%vreg140 [3232r,3328r:0)  0@3232r
%vreg144 [3552r,3568r:0)  0@3552r
%vreg146 [3536r,3568r:0)  0@3536r
%vreg147 [3520r,3536r:0)  0@3520r
%vreg149 [3664r,3680r:0)  0@3664r
%vreg151 [4096r,4112r:0)  0@4096r
%vreg153 [3920r,3984r:0)  0@3920r
%vreg154 [3952r,4000r:0)  0@3952r
RegMasks: 144r 944r 1136r 1920r 2192r 2992r 3408r 4016r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzDecompress: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=4, align=4, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=1, align=1, at location [SP+8]
  fi#3: size=8, align=8, at location [SP+8]
  fi#4: size=4, align=4, at location [SP+8]
Function Live Ins: %RDI in %vreg0

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI
16B		%vreg1<def> = COPY %RDI; GR64:%vreg1
48B		%vreg4<def> = MOV64ri <ga:@BZ2_bzDecompress>; GR64:%vreg4
80B		%vreg5<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg5
96B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
112B		%RDI<def> = COPY %vreg4; GR64:%vreg4
128B		%RSI<def> = COPY %vreg5; GR64:%vreg5
144B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
160B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
192B		STACKMAP 0, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, %vreg1, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3] LD8[FixedStack1] GR64:%vreg1
208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%strm.addr] GR64:%vreg1
240B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%strm.addr]
256B		JNE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

272B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
288B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
304B		JMP_1 <BB#37>
	    Successors according to CFG: BB#37

320B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0
336B		%vreg12<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg12
352B		%vreg9<def> = MOV64rm %vreg12, 1, %noreg, 48, %noreg; mem:LD8[%state] GR64:%vreg9,%vreg12
384B		MOV64mr <fi#3>, 1, %noreg, 0, %noreg, %vreg9; mem:ST8[%s] GR64:%vreg9
400B		CMP64mi8 <fi#3>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%s]
416B		JNE_1 <BB#4>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#4 BB#3

432B	BB#3: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#2
448B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
464B		JMP_1 <BB#37>
	    Successors according to CFG: BB#37

480B	BB#4: derived from LLVM BB %if.end.3
	    Predecessors according to CFG: BB#2
496B		%vreg17<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg17
512B		%vreg16<def> = MOV64rm %vreg17, 1, %noreg, 0, %noreg; mem:LD8[%strm4] GR64:%vreg16,%vreg17
528B		CMP64rm %vreg16, <fi#1>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD8[%strm.addr] GR64:%vreg16
544B		JE_1 <BB#6>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#6 BB#5

560B	BB#5: derived from LLVM BB %if.then.6
	    Predecessors according to CFG: BB#4
576B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
592B		JMP_1 <BB#37>
	    Successors according to CFG: BB#37

608B	BB#6: derived from LLVM BB %if.end.7
	    Predecessors according to CFG: BB#4
624B		JMP_1 <BB#7>
	    Successors according to CFG: BB#7

640B	BB#7: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#6 BB#36
656B		%vreg20<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg20
672B		CMP32mi8 %vreg20, 1, %noreg, 8, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%state8] GR64:%vreg20
688B		JNE_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#8

704B	BB#8: derived from LLVM BB %if.then.10
	    Predecessors according to CFG: BB#7
720B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -1; mem:ST4[%retval]
736B		JMP_1 <BB#37>
	    Successors according to CFG: BB#37

752B	BB#9: derived from LLVM BB %if.end.11
	    Predecessors according to CFG: BB#7
768B		%vreg23<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg23
784B		CMP32mi8 %vreg23, 1, %noreg, 8, %noreg, 2, %EFLAGS<imp-def>; mem:LD4[%state12] GR64:%vreg23
800B		JNE_1 <BB#26>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#26 BB#10

816B	BB#10: derived from LLVM BB %if.then.14
	    Predecessors according to CFG: BB#9
832B		%vreg26<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg26
848B		CMP8mi %vreg26, 1, %noreg, 44, %noreg, 0, %EFLAGS<imp-def>; mem:LD1[%smallDecompress] GR64:%vreg26
864B		JE_1 <BB#12>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#12 BB#11

880B	BB#11: derived from LLVM BB %if.then.15
	    Predecessors according to CFG: BB#10
896B		%vreg34<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg34
912B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
928B		%RDI<def> = COPY %vreg34; GR64:%vreg34
944B		CALL64pcrel32 <ga:@unRLE_obuf_to_output_SMALL>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %AL<imp-def>
960B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
976B		%vreg33<def> = COPY %AL<kill>; GR8:%vreg33
992B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1008B		STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
1024B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1040B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg33; mem:ST1[%corrupt] GR8:%vreg33
1056B		JMP_1 <BB#13>
	    Successors according to CFG: BB#13

1072B	BB#12: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#10
1088B		%vreg30<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg30
1104B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1120B		%RDI<def> = COPY %vreg30; GR64:%vreg30
1136B		CALL64pcrel32 <ga:@unRLE_obuf_to_output_FAST>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %AL<imp-def>
1152B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1168B		%vreg29<def> = COPY %AL<kill>; GR8:%vreg29
1184B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1200B		STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
1216B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1232B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg29; mem:ST1[%corrupt] GR8:%vreg29
	    Successors according to CFG: BB#13

1248B	BB#13: derived from LLVM BB %if.end.17
	    Predecessors according to CFG: BB#12 BB#11
1264B		CMP8mi <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD1[%corrupt]
1280B		JE_1 <BB#15>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#15 BB#14

1296B	BB#14: derived from LLVM BB %if.then.19
	    Predecessors according to CFG: BB#13
1312B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -4; mem:ST4[%retval]
1328B		JMP_1 <BB#37>
	    Successors according to CFG: BB#37

1344B	BB#15: derived from LLVM BB %if.end.20
	    Predecessors according to CFG: BB#13
1360B		%vreg45<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg45
1376B		%vreg44<def> = MOV32rm %vreg45, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used] GR32:%vreg44 GR64:%vreg45
1392B		%vreg42<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg42
1408B		%vreg39<def> = MOV32rm %vreg42, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock] GR32:%vreg39 GR64:%vreg42
1440B		%vreg39<def,tied1> = ADD32ri8 %vreg39<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg39
1456B		CMP32rr %vreg44, %vreg39, %EFLAGS<imp-def>; GR32:%vreg44,%vreg39
1472B		JNE_1 <BB#24>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#24 BB#16

1488B	BB#16: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#15
1504B		%vreg48<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg48
1520B		CMP32mi8 %vreg48, 1, %noreg, 16, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%state_out_len] GR64:%vreg48
1536B		JNE_1 <BB#24>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#24 BB#17

1552B	BB#17: derived from LLVM BB %if.then.23
	    Predecessors according to CFG: BB#16
1568B		%vreg59<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg59
1584B		%vreg56<def> = MOV32rm %vreg59, 1, %noreg, 3184, %noreg; mem:LD4[%calculatedBlockCRC] GR32:%vreg56 GR64:%vreg59
1616B		%vreg56<def,tied1> = XOR32ri8 %vreg56<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg56
1632B		%vreg54<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg54
1648B		MOV32mr %vreg54, 1, %noreg, 3184, %noreg, %vreg56; mem:ST4[%calculatedBlockCRC24] GR64:%vreg54 GR32:%vreg56
1664B		%vreg51<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg51
1680B		CMP32mi8 %vreg51, 1, %noreg, 52, %noreg, 3, %EFLAGS<imp-def>; mem:LD4[%verbosity] GR64:%vreg51
1696B		JL_1 <BB#19>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#19 BB#18

1712B	BB#18: derived from LLVM BB %if.then.26
	    Predecessors according to CFG: BB#17
1728B		%vreg61<def> = MOV64ri <ga:@bzlib__str_2___0x_08x__>; GR64:%vreg61
1744B		%vreg71<def> = MOV64rm %noreg, 1, %noreg, <ga:@stderr>, %noreg; mem:LD8[@stderr] GR64:%vreg71
1760B		%vreg70<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg70
1776B		%vreg69<def> = MOV32rm %vreg70, 1, %noreg, 3176, %noreg; mem:LD4[%storedBlockCRC] GR32:%vreg69 GR64:%vreg70
1792B		%vreg67<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg67
1808B		%vreg66<def> = MOV32rm %vreg67, 1, %noreg, 3184, %noreg; mem:LD4[%calculatedBlockCRC27] GR32:%vreg66 GR64:%vreg67
1824B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1840B		%RDI<def> = COPY %vreg71; GR64:%vreg71
1856B		%RSI<def> = COPY %vreg61; GR64:%vreg61
1872B		%EDX<def> = COPY %vreg69; GR32:%vreg69
1888B		%ECX<def> = COPY %vreg66; GR32:%vreg66
1904B		%AL<def> = MOV8ri 0
1920B		CALL64pcrel32 <ga:@fprintf>, <regmask>, %RSP<imp-use>, %AL<imp-use,kill>, %RDI<imp-use>, %RSI<imp-use,kill>, %EDX<imp-use,kill>, %ECX<imp-use,kill>, %EAX<imp-def>
1936B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1952B		%vreg64<def,dead> = COPY %EAX<kill>; GR32:%vreg64
1968B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1984B		STACKMAP 3, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
2000B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#19

2016B	BB#19: derived from LLVM BB %if.end.29
	    Predecessors according to CFG: BB#17 BB#18
2032B		%vreg74<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg74
2048B		CMP32mi8 %vreg74, 1, %noreg, 52, %noreg, 2, %EFLAGS<imp-def>; mem:LD4[%verbosity30] GR64:%vreg74
2064B		JL_1 <BB#21>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#21 BB#20

2080B	BB#20: derived from LLVM BB %if.then.32
	    Predecessors according to CFG: BB#19
2096B		%vreg76<def> = MOV64ri <ga:@bzlib__str_3___>; GR64:%vreg76
2112B		%vreg78<def> = MOV64rm %noreg, 1, %noreg, <ga:@stderr>, %noreg; mem:LD8[@stderr] GR64:%vreg78
2128B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2144B		%RDI<def> = COPY %vreg78; GR64:%vreg78
2160B		%RSI<def> = COPY %vreg76; GR64:%vreg76
2176B		%AL<def> = MOV8ri 0
2192B		CALL64pcrel32 <ga:@fprintf>, <regmask>, %RSP<imp-use>, %AL<imp-use,kill>, %RDI<imp-use>, %RSI<imp-use,kill>, %EAX<imp-def>
2208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2224B		%vreg77<def,dead> = COPY %EAX<kill>; GR32:%vreg77
2240B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2256B		STACKMAP 4, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
2272B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#21

2288B	BB#21: derived from LLVM BB %if.end.34
	    Predecessors according to CFG: BB#19 BB#20
2304B		%vreg85<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg85
2320B		%vreg84<def> = MOV32rm %vreg85, 1, %noreg, 3184, %noreg; mem:LD4[%calculatedBlockCRC35] GR32:%vreg84 GR64:%vreg85
2336B		%vreg82<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg82
2352B		CMP32rm %vreg84, %vreg82, 1, %noreg, 3176, %noreg, %EFLAGS<imp-def>; mem:LD4[%storedBlockCRC36] GR32:%vreg84 GR64:%vreg82
2368B		JE_1 <BB#23>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#23 BB#22

2384B	BB#22: derived from LLVM BB %if.then.38
	    Predecessors according to CFG: BB#21
2400B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -4; mem:ST4[%retval]
2416B		JMP_1 <BB#37>
	    Successors according to CFG: BB#37

2432B	BB#23: derived from LLVM BB %if.end.39
	    Predecessors according to CFG: BB#21
2448B		%vreg112<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg112
2464B		%vreg102<def> = MOV32rm %vreg112, 1, %noreg, 3188, %noreg; mem:LD4[%calculatedCombinedCRC] GR32:%vreg102 GR64:%vreg112
2496B		%vreg102<def,tied1> = SHL32ri %vreg102<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg102
2512B		%vreg107<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg107
2528B		%vreg104<def> = MOV32rm %vreg107, 1, %noreg, 3188, %noreg; mem:LD4[%calculatedCombinedCRC40] GR32:%vreg104 GR64:%vreg107
2560B		%vreg104<def,tied1> = SHR32ri %vreg104<tied0>, 31, %EFLAGS<imp-def,dead>; GR32:%vreg104
2592B		%vreg102<def,tied1> = OR32rr %vreg102<tied0>, %vreg104, %EFLAGS<imp-def,dead>; GR32:%vreg102,%vreg104
2608B		%vreg99<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg99
2624B		MOV32mr %vreg99, 1, %noreg, 3188, %noreg, %vreg102; mem:ST4[%calculatedCombinedCRC41] GR64:%vreg99 GR32:%vreg102
2640B		%vreg96<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg96
2656B		%vreg92<def> = MOV32rm %vreg96, 1, %noreg, 3184, %noreg; mem:LD4[%calculatedBlockCRC42] GR32:%vreg92 GR64:%vreg96
2672B		%vreg93<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg93
2704B		%vreg92<def,tied1> = XOR32rm %vreg92<tied0>, %vreg93, 1, %noreg, 3188, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%calculatedCombinedCRC43] GR32:%vreg92 GR64:%vreg93
2720B		MOV32mr %vreg93, 1, %noreg, 3188, %noreg, %vreg92; mem:ST4[%calculatedCombinedCRC43] GR64:%vreg93 GR32:%vreg92
2736B		%vreg87<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg87
2752B		MOV32mi %vreg87, 1, %noreg, 8, %noreg, 14; mem:ST4[%state44] GR64:%vreg87
2768B		JMP_1 <BB#25>
	    Successors according to CFG: BB#25

2784B	BB#24: derived from LLVM BB %if.else.45
	    Predecessors according to CFG: BB#15 BB#16
2800B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
2816B		JMP_1 <BB#37>
	    Successors according to CFG: BB#37

2832B	BB#25: derived from LLVM BB %if.end.46
	    Predecessors according to CFG: BB#23
2848B		JMP_1 <BB#26>
	    Successors according to CFG: BB#26

2864B	BB#26: derived from LLVM BB %if.end.47
	    Predecessors according to CFG: BB#9 BB#25
2880B		%vreg115<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg115
2896B		CMP32mi8 %vreg115, 1, %noreg, 8, %noreg, 10, %EFLAGS<imp-def>; mem:LD4[%state48] GR64:%vreg115
2912B		JL_1 <BB#36>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#36 BB#27

2928B	BB#27: derived from LLVM BB %if.then.50
	    Predecessors according to CFG: BB#26
2944B		%vreg120<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg120
2960B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2976B		%RDI<def> = COPY %vreg120; GR64:%vreg120
2992B		CALL64pcrel32 <ga:@BZ2_decompress>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
3008B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3024B		%vreg119<def> = COPY %EAX<kill>; GR32:%vreg119
3040B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3056B		STACKMAP 5, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
3072B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3088B		MOV32mr <fi#4>, 1, %noreg, 0, %noreg, %vreg119; mem:ST4[%r] GR32:%vreg119
3104B		CMP32mi8 <fi#4>, 1, %noreg, 0, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%r]
3120B		JNE_1 <BB#33>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#33 BB#28

3136B	BB#28: derived from LLVM BB %if.then.53
	    Predecessors according to CFG: BB#27
3152B		%vreg128<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg128
3168B		CMP32mi8 %vreg128, 1, %noreg, 52, %noreg, 3, %EFLAGS<imp-def>; mem:LD4[%verbosity54] GR64:%vreg128
3184B		JL_1 <BB#30>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#30 BB#29

3200B	BB#29: derived from LLVM BB %if.then.56
	    Predecessors according to CFG: BB#28
3216B		%vreg130<def> = MOV64ri <ga:@bzlib__str_4______combi>; GR64:%vreg130
3232B		%vreg140<def> = MOV64rm %noreg, 1, %noreg, <ga:@stderr>, %noreg; mem:LD8[@stderr] GR64:%vreg140
3248B		%vreg139<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg139
3264B		%vreg138<def> = MOV32rm %vreg139, 1, %noreg, 3180, %noreg; mem:LD4[%storedCombinedCRC] GR32:%vreg138 GR64:%vreg139
3280B		%vreg136<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg136
3296B		%vreg135<def> = MOV32rm %vreg136, 1, %noreg, 3188, %noreg; mem:LD4[%calculatedCombinedCRC57] GR32:%vreg135 GR64:%vreg136
3312B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3328B		%RDI<def> = COPY %vreg140; GR64:%vreg140
3344B		%RSI<def> = COPY %vreg130; GR64:%vreg130
3360B		%EDX<def> = COPY %vreg138; GR32:%vreg138
3376B		%ECX<def> = COPY %vreg135; GR32:%vreg135
3392B		%AL<def> = MOV8ri 0
3408B		CALL64pcrel32 <ga:@fprintf>, <regmask>, %RSP<imp-use>, %AL<imp-use,kill>, %RDI<imp-use>, %RSI<imp-use,kill>, %EDX<imp-use,kill>, %ECX<imp-use,kill>, %EAX<imp-def>
3424B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3440B		%vreg133<def,dead> = COPY %EAX<kill>; GR32:%vreg133
3456B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3472B		STACKMAP 6, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
3488B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#30

3504B	BB#30: derived from LLVM BB %if.end.59
	    Predecessors according to CFG: BB#28 BB#29
3520B		%vreg147<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg147
3536B		%vreg146<def> = MOV32rm %vreg147, 1, %noreg, 3188, %noreg; mem:LD4[%calculatedCombinedCRC60] GR32:%vreg146 GR64:%vreg147
3552B		%vreg144<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg144
3568B		CMP32rm %vreg146, %vreg144, 1, %noreg, 3180, %noreg, %EFLAGS<imp-def>; mem:LD4[%storedCombinedCRC61] GR32:%vreg146 GR64:%vreg144
3584B		JE_1 <BB#32>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#32 BB#31

3600B	BB#31: derived from LLVM BB %if.then.63
	    Predecessors according to CFG: BB#30
3616B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -4; mem:ST4[%retval]
3632B		JMP_1 <BB#37>
	    Successors according to CFG: BB#37

3648B	BB#32: derived from LLVM BB %if.end.64
	    Predecessors according to CFG: BB#30
3664B		%vreg149<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%r] GR32:%vreg149
3680B		MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %vreg149; mem:ST4[%retval] GR32:%vreg149
3696B		JMP_1 <BB#37>
	    Successors according to CFG: BB#37

3712B	BB#33: derived from LLVM BB %if.end.65
	    Predecessors according to CFG: BB#27
3728B		%vreg123<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg123
3744B		CMP32mi8 %vreg123, 1, %noreg, 8, %noreg, 2, %EFLAGS<imp-def>; mem:LD4[%state66] GR64:%vreg123
3760B		JE_1 <BB#35>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#35 BB#34

3776B	BB#34: derived from LLVM BB %if.then.68
	    Predecessors according to CFG: BB#33
3792B		%vreg125<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%r] GR32:%vreg125
3808B		MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %vreg125; mem:ST4[%retval] GR32:%vreg125
3824B		JMP_1 <BB#37>
	    Successors according to CFG: BB#37

3840B	BB#35: derived from LLVM BB %if.end.69
	    Predecessors according to CFG: BB#33
3856B		JMP_1 <BB#36>
	    Successors according to CFG: BB#36

3872B	BB#36: derived from LLVM BB %if.end.70
	    Predecessors according to CFG: BB#26 BB#35
3888B		JMP_1 <BB#7>
	    Successors according to CFG: BB#7

3904B	BB#37: derived from LLVM BB %return
	    Predecessors according to CFG: BB#24 BB#34 BB#32 BB#31 BB#22 BB#14 BB#8 BB#5 BB#3 BB#1
3920B		%vreg153<def> = MOV64ri <ga:@BZ2_bzDecompress>; GR64:%vreg153
3952B		%vreg154<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg154
3968B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3984B		%RDI<def> = COPY %vreg153; GR64:%vreg153
4000B		%RSI<def> = COPY %vreg154; GR64:%vreg154
4016B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
4032B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4048B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4064B		STACKMAP 7, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
4080B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4096B		%vreg151<def> = MOV32rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD4[%retval] GR32:%vreg151
4112B		%EAX<def> = COPY %vreg151; GR32:%vreg151
4128B		RETQ %EAX<imp-use,kill>

# End machine code for function BZ2_bzDecompress.

handleMove 1888B -> 1912B: %ECX<def> = COPY %vreg66; GR32:%vreg66
     CH:	[1912r,1920r:1)[3376r,3408r:0)  0@3376r 1@1912r
        -->	[1912r,1920r:1)[3376r,3408r:0)  0@3376r 1@1912r
     CL:	[1912r,1920r:1)[3376r,3408r:0)  0@3376r 1@1912r
        -->	[1912r,1920r:1)[3376r,3408r:0)  0@3376r 1@1912r
     %vreg66:	[1808r,1888r:0)  0@1808r
        -->	[1808r,1912r:0)  0@1808r
handleMove 1872B -> 1908B: %EDX<def> = COPY %vreg69; GR32:%vreg69
     DH:	[1908r,1920r:1)[3360r,3408r:0)  0@3360r 1@1908r
        -->	[1908r,1920r:1)[3360r,3408r:0)  0@3360r 1@1908r
     DL:	[1908r,1920r:1)[3360r,3408r:0)  0@3360r 1@1908r
        -->	[1908r,1920r:1)[3360r,3408r:0)  0@3360r 1@1908r
     %vreg69:	[1776r,1872r:0)  0@1776r
        -->	[1776r,1908r:0)  0@1776r
handleMove 1856B -> 1912B: %RSI<def> = COPY %vreg61; GR64:%vreg61
     SIL:	[128r,144r:4)[1912r,1936r:3)[2160r,2192r:2)[3344r,3408r:1)[4000r,4016r:0)  0@4000r 1@3344r 2@2160r 3@1912r 4@128r
        -->	[128r,144r:4)[1912r,1936r:3)[2160r,2192r:2)[3344r,3408r:1)[4000r,4016r:0)  0@4000r 1@3344r 2@2160r 3@1912r 4@128r
     %vreg61:	[1728r,1856r:0)  0@1728r
        -->	[1728r,1912r:0)  0@1728r
handleMove 1840B -> 1908B: %RDI<def> = COPY %vreg71; GR64:%vreg71
     DIL:	[0B,16r:0)[112r,144r:8)[928r,944r:6)[1120r,1136r:7)[1840r,1936r:5)[2144r,2192r:4)[2976r,2992r:3)[3328r,3408r:2)[3984r,4016r:1)  0@0B-phi 1@3984r 2@3328r 3@2976r 4@2144r 5@1840r 6@928r 7@1120r 8@112r
        -->	[0B,16r:0)[112r,144r:8)[928r,944r:6)[1120r,1136r:7)[1908r,1936r:5)[2144r,2192r:4)[2976r,2992r:3)[3328r,3408r:2)[3984r,4016r:1)  0@0B-phi 1@3984r 2@3328r 3@2976r 4@2144r 5@1908r 6@928r 7@1120r 8@112r
     %vreg71:	[1744r,1840r:0)  0@1744r
        -->	[1744r,1908r:0)  0@1744r
handleMove 2160B -> 2184B: %RSI<def> = COPY %vreg76; GR64:%vreg76
     SIL:	[128r,144r:4)[1912r,1936r:3)[2160r,2192r:2)[3344r,3408r:1)[4000r,4016r:0)  0@4000r 1@3344r 2@2160r 3@1912r 4@128r
        -->	[128r,144r:4)[1912r,1936r:3)[2184r,2192r:2)[3344r,3408r:1)[4000r,4016r:0)  0@4000r 1@3344r 2@2184r 3@1912r 4@128r
     %vreg76:	[2096r,2160r:0)  0@2096r
        -->	[2096r,2184r:0)  0@2096r
handleMove 2144B -> 2180B: %RDI<def> = COPY %vreg78; GR64:%vreg78
     DIL:	[0B,16r:0)[112r,144r:8)[928r,944r:6)[1120r,1136r:7)[1908r,1936r:5)[2144r,2192r:4)[2976r,2992r:3)[3328r,3408r:2)[3984r,4016r:1)  0@0B-phi 1@3984r 2@3328r 3@2976r 4@2144r 5@1908r 6@928r 7@1120r 8@112r
        -->	[0B,16r:0)[112r,144r:8)[928r,944r:6)[1120r,1136r:7)[1908r,1936r:5)[2180r,2192r:4)[2976r,2992r:3)[3328r,3408r:2)[3984r,4016r:1)  0@0B-phi 1@3984r 2@3328r 3@2976r 4@2180r 5@1908r 6@928r 7@1120r 8@112r
     %vreg78:	[2112r,2144r:0)  0@2112r
        -->	[2112r,2180r:0)  0@2112r
AllocationOrder(SEGMENT_REG) = [ ]
handleMove 3376B -> 3400B: %ECX<def> = COPY %vreg135; GR32:%vreg135
     CH:	[1928r,1936r:1)[3376r,3408r:0)  0@3376r 1@1928r
        -->	[1928r,1936r:1)[3400r,3408r:0)  0@3400r 1@1928r
     CL:	[1928r,1936r:1)[3376r,3408r:0)  0@3376r 1@1928r
        -->	[1928r,1936r:1)[3400r,3408r:0)  0@3400r 1@1928r
     %vreg135:	[3296r,3376r:0)  0@3296r
        -->	[3296r,3400r:0)  0@3296r
handleMove 3360B -> 3396B: %EDX<def> = COPY %vreg138; GR32:%vreg138
     DH:	[1920r,1936r:1)[3360r,3408r:0)  0@3360r 1@1920r
        -->	[1920r,1936r:1)[3396r,3408r:0)  0@3396r 1@1920r
     DL:	[1920r,1936r:1)[3360r,3408r:0)  0@3360r 1@1920r
        -->	[1920r,1936r:1)[3396r,3408r:0)  0@3396r 1@1920r
     %vreg138:	[3264r,3360r:0)  0@3264r
        -->	[3264r,3396r:0)  0@3264r
handleMove 3344B -> 3400B: %RSI<def> = COPY %vreg130; GR64:%vreg130
     SIL:	[128r,144r:4)[1912r,1936r:3)[2184r,2192r:2)[3344r,3424r:1)[4000r,4016r:0)  0@4000r 1@3344r 2@2184r 3@1912r 4@128r
        -->	[128r,144r:4)[1912r,1936r:3)[2184r,2192r:2)[3400r,3424r:1)[4000r,4016r:0)  0@4000r 1@3400r 2@2184r 3@1912r 4@128r
     %vreg130:	[3216r,3344r:0)  0@3216r
        -->	[3216r,3400r:0)  0@3216r
handleMove 3328B -> 3396B: %RDI<def> = COPY %vreg140; GR64:%vreg140
     DIL:	[0B,16r:0)[112r,144r:8)[928r,944r:6)[1120r,1136r:7)[1908r,1936r:5)[2180r,2192r:4)[2976r,2992r:3)[3328r,3424r:2)[3984r,4016r:1)  0@0B-phi 1@3984r 2@3328r 3@2976r 4@2180r 5@1908r 6@928r 7@1120r 8@112r
        -->	[0B,16r:0)[112r,144r:8)[928r,944r:6)[1120r,1136r:7)[1908r,1936r:5)[2180r,2192r:4)[2976r,2992r:3)[3396r,3424r:2)[3984r,4016r:1)  0@0B-phi 1@3984r 2@3396r 3@2976r 4@2180r 5@1908r 6@928r 7@1120r 8@112r
     %vreg140:	[3232r,3328r:0)  0@3232r
        -->	[3232r,3396r:0)  0@3232r
********** GREEDY REGISTER ALLOCATION **********
********** Function: BZ2_bzDecompress
********** INTERVALS **********
CH [1928r,1936r:1)[3416r,3424r:0)  0@3416r 1@1928r
CL [1928r,1936r:1)[3416r,3424r:0)  0@3416r 1@1928r
DH [1920r,1936r:1)[3408r,3424r:0)  0@3408r 1@1920r
DIL [0B,16r:0)[112r,144r:8)[928r,944r:6)[1120r,1136r:7)[1908r,1936r:5)[2180r,2192r:4)[2976r,2992r:3)[3396r,3424r:2)[3984r,4016r:1)  0@0B-phi 1@3984r 2@3396r 3@2976r 4@2180r 5@1908r 6@928r 7@1120r 8@112r
DL [1920r,1936r:1)[3408r,3424r:0)  0@3408r 1@1920r
SIL [128r,144r:4)[1912r,1936r:3)[2184r,2192r:2)[3400r,3424r:1)[4000r,4016r:0)  0@4000r 1@3400r 2@2184r 3@1912r 4@128r
%vreg1 [16r,224r:0)  0@16r
%vreg4 [48r,112r:0)  0@48r
%vreg5 [80r,128r:0)  0@80r
%vreg9 [352r,384r:0)  0@352r
%vreg12 [336r,352r:0)  0@336r
%vreg16 [512r,528r:0)  0@512r
%vreg17 [496r,512r:0)  0@496r
%vreg20 [656r,672r:0)  0@656r
%vreg23 [768r,784r:0)  0@768r
%vreg26 [832r,848r:0)  0@832r
%vreg29 [1168r,1232r:0)  0@1168r
%vreg30 [1088r,1120r:0)  0@1088r
%vreg33 [976r,1040r:0)  0@976r
%vreg34 [896r,928r:0)  0@896r
%vreg39 [1408r,1440r:0)[1440r,1456r:1)  0@1408r 1@1440r
%vreg42 [1392r,1408r:0)  0@1392r
%vreg44 [1376r,1456r:0)  0@1376r
%vreg45 [1360r,1376r:0)  0@1360r
%vreg48 [1504r,1520r:0)  0@1504r
%vreg51 [1664r,1680r:0)  0@1664r
%vreg54 [1632r,1648r:0)  0@1632r
%vreg56 [1584r,1616r:0)[1616r,1648r:1)  0@1584r 1@1616r
%vreg59 [1568r,1584r:0)  0@1568r
%vreg61 [1728r,1912r:0)  0@1728r
%vreg64 [1952r,1952d:0)  0@1952r
%vreg66 [1808r,1928r:0)  0@1808r
%vreg67 [1792r,1808r:0)  0@1792r
%vreg69 [1776r,1920r:0)  0@1776r
%vreg70 [1760r,1776r:0)  0@1760r
%vreg71 [1744r,1908r:0)  0@1744r
%vreg74 [2032r,2048r:0)  0@2032r
%vreg76 [2096r,2184r:0)  0@2096r
%vreg77 [2224r,2224d:0)  0@2224r
%vreg78 [2112r,2180r:0)  0@2112r
%vreg82 [2336r,2352r:0)  0@2336r
%vreg84 [2320r,2352r:0)  0@2320r
%vreg85 [2304r,2320r:0)  0@2304r
%vreg87 [2736r,2752r:0)  0@2736r
%vreg92 [2656r,2704r:0)[2704r,2720r:1)  0@2656r 1@2704r
%vreg93 [2672r,2720r:0)  0@2672r
%vreg96 [2640r,2656r:0)  0@2640r
%vreg99 [2608r,2624r:0)  0@2608r
%vreg102 [2464r,2496r:2)[2496r,2592r:0)[2592r,2624r:1)  0@2496r 1@2592r 2@2464r
%vreg104 [2528r,2560r:0)[2560r,2592r:1)  0@2528r 1@2560r
%vreg107 [2512r,2528r:0)  0@2512r
%vreg112 [2448r,2464r:0)  0@2448r
%vreg115 [2880r,2896r:0)  0@2880r
%vreg119 [3024r,3088r:0)  0@3024r
%vreg120 [2944r,2976r:0)  0@2944r
%vreg123 [3728r,3744r:0)  0@3728r
%vreg125 [3792r,3808r:0)  0@3792r
%vreg128 [3152r,3168r:0)  0@3152r
%vreg130 [3216r,3400r:0)  0@3216r
%vreg133 [3440r,3440d:0)  0@3440r
%vreg135 [3296r,3416r:0)  0@3296r
%vreg136 [3280r,3296r:0)  0@3280r
%vreg138 [3264r,3408r:0)  0@3264r
%vreg139 [3248r,3264r:0)  0@3248r
%vreg140 [3232r,3396r:0)  0@3232r
%vreg144 [3552r,3568r:0)  0@3552r
%vreg146 [3536r,3568r:0)  0@3536r
%vreg147 [3520r,3536r:0)  0@3520r
%vreg149 [3664r,3680r:0)  0@3664r
%vreg151 [4096r,4112r:0)  0@4096r
%vreg153 [3920r,3984r:0)  0@3920r
%vreg154 [3952r,4000r:0)  0@3952r
RegMasks: 144r 944r 1136r 1936r 2192r 2992r 3424r 4016r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzDecompress: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=4, align=4, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=1, align=1, at location [SP+8]
  fi#3: size=8, align=8, at location [SP+8]
  fi#4: size=4, align=4, at location [SP+8]
Function Live Ins: %RDI in %vreg0

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI
16B		%vreg1<def> = COPY %RDI; GR64:%vreg1
48B		%vreg4<def> = MOV64ri <ga:@BZ2_bzDecompress>; GR64:%vreg4
80B		%vreg5<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg5
96B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
112B		%RDI<def> = COPY %vreg4; GR64:%vreg4
128B		%RSI<def> = COPY %vreg5; GR64:%vreg5
144B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
160B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
192B		STACKMAP 0, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, %vreg1, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3] LD8[FixedStack1] GR64:%vreg1
208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%strm.addr] GR64:%vreg1
240B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%strm.addr]
256B		JNE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

272B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
288B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
304B		JMP_1 <BB#37>
	    Successors according to CFG: BB#37

320B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0
336B		%vreg12<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg12
352B		%vreg9<def> = MOV64rm %vreg12, 1, %noreg, 48, %noreg; mem:LD8[%state] GR64:%vreg9,%vreg12
384B		MOV64mr <fi#3>, 1, %noreg, 0, %noreg, %vreg9; mem:ST8[%s] GR64:%vreg9
400B		CMP64mi8 <fi#3>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%s]
416B		JNE_1 <BB#4>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#4 BB#3

432B	BB#3: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#2
448B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
464B		JMP_1 <BB#37>
	    Successors according to CFG: BB#37

480B	BB#4: derived from LLVM BB %if.end.3
	    Predecessors according to CFG: BB#2
496B		%vreg17<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg17
512B		%vreg16<def> = MOV64rm %vreg17, 1, %noreg, 0, %noreg; mem:LD8[%strm4] GR64:%vreg16,%vreg17
528B		CMP64rm %vreg16, <fi#1>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD8[%strm.addr] GR64:%vreg16
544B		JE_1 <BB#6>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#6 BB#5

560B	BB#5: derived from LLVM BB %if.then.6
	    Predecessors according to CFG: BB#4
576B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
592B		JMP_1 <BB#37>
	    Successors according to CFG: BB#37

608B	BB#6: derived from LLVM BB %if.end.7
	    Predecessors according to CFG: BB#4
624B		JMP_1 <BB#7>
	    Successors according to CFG: BB#7

640B	BB#7: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#6 BB#36
656B		%vreg20<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg20
672B		CMP32mi8 %vreg20, 1, %noreg, 8, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%state8] GR64:%vreg20
688B		JNE_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#8

704B	BB#8: derived from LLVM BB %if.then.10
	    Predecessors according to CFG: BB#7
720B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -1; mem:ST4[%retval]
736B		JMP_1 <BB#37>
	    Successors according to CFG: BB#37

752B	BB#9: derived from LLVM BB %if.end.11
	    Predecessors according to CFG: BB#7
768B		%vreg23<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg23
784B		CMP32mi8 %vreg23, 1, %noreg, 8, %noreg, 2, %EFLAGS<imp-def>; mem:LD4[%state12] GR64:%vreg23
800B		JNE_1 <BB#26>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#26 BB#10

816B	BB#10: derived from LLVM BB %if.then.14
	    Predecessors according to CFG: BB#9
832B		%vreg26<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg26
848B		CMP8mi %vreg26, 1, %noreg, 44, %noreg, 0, %EFLAGS<imp-def>; mem:LD1[%smallDecompress] GR64:%vreg26
864B		JE_1 <BB#12>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#12 BB#11

880B	BB#11: derived from LLVM BB %if.then.15
	    Predecessors according to CFG: BB#10
896B		%vreg34<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg34
912B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
928B		%RDI<def> = COPY %vreg34; GR64:%vreg34
944B		CALL64pcrel32 <ga:@unRLE_obuf_to_output_SMALL>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %AL<imp-def>
960B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
976B		%vreg33<def> = COPY %AL<kill>; GR8:%vreg33
992B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1008B		STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
1024B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1040B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg33; mem:ST1[%corrupt] GR8:%vreg33
1056B		JMP_1 <BB#13>
	    Successors according to CFG: BB#13

1072B	BB#12: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#10
1088B		%vreg30<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg30
1104B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1120B		%RDI<def> = COPY %vreg30; GR64:%vreg30
1136B		CALL64pcrel32 <ga:@unRLE_obuf_to_output_FAST>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %AL<imp-def>
1152B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1168B		%vreg29<def> = COPY %AL<kill>; GR8:%vreg29
1184B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1200B		STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
1216B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1232B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg29; mem:ST1[%corrupt] GR8:%vreg29
	    Successors according to CFG: BB#13

1248B	BB#13: derived from LLVM BB %if.end.17
	    Predecessors according to CFG: BB#12 BB#11
1264B		CMP8mi <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD1[%corrupt]
1280B		JE_1 <BB#15>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#15 BB#14

1296B	BB#14: derived from LLVM BB %if.then.19
	    Predecessors according to CFG: BB#13
1312B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -4; mem:ST4[%retval]
1328B		JMP_1 <BB#37>
	    Successors according to CFG: BB#37

1344B	BB#15: derived from LLVM BB %if.end.20
	    Predecessors according to CFG: BB#13
1360B		%vreg45<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg45
1376B		%vreg44<def> = MOV32rm %vreg45, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used] GR32:%vreg44 GR64:%vreg45
1392B		%vreg42<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg42
1408B		%vreg39<def> = MOV32rm %vreg42, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock] GR32:%vreg39 GR64:%vreg42
1440B		%vreg39<def,tied1> = ADD32ri8 %vreg39<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg39
1456B		CMP32rr %vreg44, %vreg39, %EFLAGS<imp-def>; GR32:%vreg44,%vreg39
1472B		JNE_1 <BB#24>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#24 BB#16

1488B	BB#16: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#15
1504B		%vreg48<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg48
1520B		CMP32mi8 %vreg48, 1, %noreg, 16, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%state_out_len] GR64:%vreg48
1536B		JNE_1 <BB#24>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#24 BB#17

1552B	BB#17: derived from LLVM BB %if.then.23
	    Predecessors according to CFG: BB#16
1568B		%vreg59<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg59
1584B		%vreg56<def> = MOV32rm %vreg59, 1, %noreg, 3184, %noreg; mem:LD4[%calculatedBlockCRC] GR32:%vreg56 GR64:%vreg59
1616B		%vreg56<def,tied1> = XOR32ri8 %vreg56<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg56
1632B		%vreg54<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg54
1648B		MOV32mr %vreg54, 1, %noreg, 3184, %noreg, %vreg56; mem:ST4[%calculatedBlockCRC24] GR64:%vreg54 GR32:%vreg56
1664B		%vreg51<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg51
1680B		CMP32mi8 %vreg51, 1, %noreg, 52, %noreg, 3, %EFLAGS<imp-def>; mem:LD4[%verbosity] GR64:%vreg51
1696B		JL_1 <BB#19>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#19 BB#18

1712B	BB#18: derived from LLVM BB %if.then.26
	    Predecessors according to CFG: BB#17
1728B		%vreg61<def> = MOV64ri <ga:@bzlib__str_2___0x_08x__>; GR64:%vreg61
1744B		%vreg71<def> = MOV64rm %noreg, 1, %noreg, <ga:@stderr>, %noreg; mem:LD8[@stderr] GR64:%vreg71
1760B		%vreg70<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg70
1776B		%vreg69<def> = MOV32rm %vreg70, 1, %noreg, 3176, %noreg; mem:LD4[%storedBlockCRC] GR32:%vreg69 GR64:%vreg70
1792B		%vreg67<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg67
1808B		%vreg66<def> = MOV32rm %vreg67, 1, %noreg, 3184, %noreg; mem:LD4[%calculatedBlockCRC27] GR32:%vreg66 GR64:%vreg67
1824B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1904B		%AL<def> = MOV8ri 0
1908B		%RDI<def> = COPY %vreg71; GR64:%vreg71
1912B		%RSI<def> = COPY %vreg61; GR64:%vreg61
1920B		%EDX<def> = COPY %vreg69; GR32:%vreg69
1928B		%ECX<def> = COPY %vreg66; GR32:%vreg66
1936B		CALL64pcrel32 <ga:@fprintf>, <regmask>, %RSP<imp-use>, %AL<imp-use,kill>, %RDI<imp-use>, %RSI<imp-use>, %EDX<imp-use>, %ECX<imp-use>, %EAX<imp-def>
1944B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1952B		%vreg64<def,dead> = COPY %EAX<kill>; GR32:%vreg64
1968B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1984B		STACKMAP 3, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
2000B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#19

2016B	BB#19: derived from LLVM BB %if.end.29
	    Predecessors according to CFG: BB#17 BB#18
2032B		%vreg74<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg74
2048B		CMP32mi8 %vreg74, 1, %noreg, 52, %noreg, 2, %EFLAGS<imp-def>; mem:LD4[%verbosity30] GR64:%vreg74
2064B		JL_1 <BB#21>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#21 BB#20

2080B	BB#20: derived from LLVM BB %if.then.32
	    Predecessors according to CFG: BB#19
2096B		%vreg76<def> = MOV64ri <ga:@bzlib__str_3___>; GR64:%vreg76
2112B		%vreg78<def> = MOV64rm %noreg, 1, %noreg, <ga:@stderr>, %noreg; mem:LD8[@stderr] GR64:%vreg78
2128B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2176B		%AL<def> = MOV8ri 0
2180B		%RDI<def> = COPY %vreg78; GR64:%vreg78
2184B		%RSI<def> = COPY %vreg76; GR64:%vreg76
2192B		CALL64pcrel32 <ga:@fprintf>, <regmask>, %RSP<imp-use>, %AL<imp-use,kill>, %RDI<imp-use>, %RSI<imp-use>, %EAX<imp-def>
2208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2224B		%vreg77<def,dead> = COPY %EAX<kill>; GR32:%vreg77
2240B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2256B		STACKMAP 4, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
2272B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#21

2288B	BB#21: derived from LLVM BB %if.end.34
	    Predecessors according to CFG: BB#19 BB#20
2304B		%vreg85<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg85
2320B		%vreg84<def> = MOV32rm %vreg85, 1, %noreg, 3184, %noreg; mem:LD4[%calculatedBlockCRC35] GR32:%vreg84 GR64:%vreg85
2336B		%vreg82<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg82
2352B		CMP32rm %vreg84, %vreg82, 1, %noreg, 3176, %noreg, %EFLAGS<imp-def>; mem:LD4[%storedBlockCRC36] GR32:%vreg84 GR64:%vreg82
2368B		JE_1 <BB#23>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#23 BB#22

2384B	BB#22: derived from LLVM BB %if.then.38
	    Predecessors according to CFG: BB#21
2400B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -4; mem:ST4[%retval]
2416B		JMP_1 <BB#37>
	    Successors according to CFG: BB#37

2432B	BB#23: derived from LLVM BB %if.end.39
	    Predecessors according to CFG: BB#21
2448B		%vreg112<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg112
2464B		%vreg102<def> = MOV32rm %vreg112, 1, %noreg, 3188, %noreg; mem:LD4[%calculatedCombinedCRC] GR32:%vreg102 GR64:%vreg112
2496B		%vreg102<def,tied1> = SHL32ri %vreg102<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg102
2512B		%vreg107<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg107
2528B		%vreg104<def> = MOV32rm %vreg107, 1, %noreg, 3188, %noreg; mem:LD4[%calculatedCombinedCRC40] GR32:%vreg104 GR64:%vreg107
2560B		%vreg104<def,tied1> = SHR32ri %vreg104<tied0>, 31, %EFLAGS<imp-def,dead>; GR32:%vreg104
2592B		%vreg102<def,tied1> = OR32rr %vreg102<tied0>, %vreg104, %EFLAGS<imp-def,dead>; GR32:%vreg102,%vreg104
2608B		%vreg99<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg99
2624B		MOV32mr %vreg99, 1, %noreg, 3188, %noreg, %vreg102; mem:ST4[%calculatedCombinedCRC41] GR64:%vreg99 GR32:%vreg102
2640B		%vreg96<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg96
2656B		%vreg92<def> = MOV32rm %vreg96, 1, %noreg, 3184, %noreg; mem:LD4[%calculatedBlockCRC42] GR32:%vreg92 GR64:%vreg96
2672B		%vreg93<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg93
2704B		%vreg92<def,tied1> = XOR32rm %vreg92<tied0>, %vreg93, 1, %noreg, 3188, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%calculatedCombinedCRC43] GR32:%vreg92 GR64:%vreg93
2720B		MOV32mr %vreg93, 1, %noreg, 3188, %noreg, %vreg92; mem:ST4[%calculatedCombinedCRC43] GR64:%vreg93 GR32:%vreg92
2736B		%vreg87<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg87
2752B		MOV32mi %vreg87, 1, %noreg, 8, %noreg, 14; mem:ST4[%state44] GR64:%vreg87
2768B		JMP_1 <BB#25>
	    Successors according to CFG: BB#25

2784B	BB#24: derived from LLVM BB %if.else.45
	    Predecessors according to CFG: BB#15 BB#16
2800B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
2816B		JMP_1 <BB#37>
	    Successors according to CFG: BB#37

2832B	BB#25: derived from LLVM BB %if.end.46
	    Predecessors according to CFG: BB#23
2848B		JMP_1 <BB#26>
	    Successors according to CFG: BB#26

2864B	BB#26: derived from LLVM BB %if.end.47
	    Predecessors according to CFG: BB#9 BB#25
2880B		%vreg115<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg115
2896B		CMP32mi8 %vreg115, 1, %noreg, 8, %noreg, 10, %EFLAGS<imp-def>; mem:LD4[%state48] GR64:%vreg115
2912B		JL_1 <BB#36>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#36 BB#27

2928B	BB#27: derived from LLVM BB %if.then.50
	    Predecessors according to CFG: BB#26
2944B		%vreg120<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg120
2960B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2976B		%RDI<def> = COPY %vreg120; GR64:%vreg120
2992B		CALL64pcrel32 <ga:@BZ2_decompress>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
3008B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3024B		%vreg119<def> = COPY %EAX<kill>; GR32:%vreg119
3040B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3056B		STACKMAP 5, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
3072B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3088B		MOV32mr <fi#4>, 1, %noreg, 0, %noreg, %vreg119; mem:ST4[%r] GR32:%vreg119
3104B		CMP32mi8 <fi#4>, 1, %noreg, 0, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%r]
3120B		JNE_1 <BB#33>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#33 BB#28

3136B	BB#28: derived from LLVM BB %if.then.53
	    Predecessors according to CFG: BB#27
3152B		%vreg128<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg128
3168B		CMP32mi8 %vreg128, 1, %noreg, 52, %noreg, 3, %EFLAGS<imp-def>; mem:LD4[%verbosity54] GR64:%vreg128
3184B		JL_1 <BB#30>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#30 BB#29

3200B	BB#29: derived from LLVM BB %if.then.56
	    Predecessors according to CFG: BB#28
3216B		%vreg130<def> = MOV64ri <ga:@bzlib__str_4______combi>; GR64:%vreg130
3232B		%vreg140<def> = MOV64rm %noreg, 1, %noreg, <ga:@stderr>, %noreg; mem:LD8[@stderr] GR64:%vreg140
3248B		%vreg139<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg139
3264B		%vreg138<def> = MOV32rm %vreg139, 1, %noreg, 3180, %noreg; mem:LD4[%storedCombinedCRC] GR32:%vreg138 GR64:%vreg139
3280B		%vreg136<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg136
3296B		%vreg135<def> = MOV32rm %vreg136, 1, %noreg, 3188, %noreg; mem:LD4[%calculatedCombinedCRC57] GR32:%vreg135 GR64:%vreg136
3312B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3392B		%AL<def> = MOV8ri 0
3396B		%RDI<def> = COPY %vreg140; GR64:%vreg140
3400B		%RSI<def> = COPY %vreg130; GR64:%vreg130
3408B		%EDX<def> = COPY %vreg138; GR32:%vreg138
3416B		%ECX<def> = COPY %vreg135; GR32:%vreg135
3424B		CALL64pcrel32 <ga:@fprintf>, <regmask>, %RSP<imp-use>, %AL<imp-use,kill>, %RDI<imp-use>, %RSI<imp-use>, %EDX<imp-use>, %ECX<imp-use>, %EAX<imp-def>
3432B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3440B		%vreg133<def,dead> = COPY %EAX<kill>; GR32:%vreg133
3456B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3472B		STACKMAP 6, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
3488B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#30

3504B	BB#30: derived from LLVM BB %if.end.59
	    Predecessors according to CFG: BB#28 BB#29
3520B		%vreg147<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg147
3536B		%vreg146<def> = MOV32rm %vreg147, 1, %noreg, 3188, %noreg; mem:LD4[%calculatedCombinedCRC60] GR32:%vreg146 GR64:%vreg147
3552B		%vreg144<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg144
3568B		CMP32rm %vreg146, %vreg144, 1, %noreg, 3180, %noreg, %EFLAGS<imp-def>; mem:LD4[%storedCombinedCRC61] GR32:%vreg146 GR64:%vreg144
3584B		JE_1 <BB#32>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#32 BB#31

3600B	BB#31: derived from LLVM BB %if.then.63
	    Predecessors according to CFG: BB#30
3616B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -4; mem:ST4[%retval]
3632B		JMP_1 <BB#37>
	    Successors according to CFG: BB#37

3648B	BB#32: derived from LLVM BB %if.end.64
	    Predecessors according to CFG: BB#30
3664B		%vreg149<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%r] GR32:%vreg149
3680B		MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %vreg149; mem:ST4[%retval] GR32:%vreg149
3696B		JMP_1 <BB#37>
	    Successors according to CFG: BB#37

3712B	BB#33: derived from LLVM BB %if.end.65
	    Predecessors according to CFG: BB#27
3728B		%vreg123<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg123
3744B		CMP32mi8 %vreg123, 1, %noreg, 8, %noreg, 2, %EFLAGS<imp-def>; mem:LD4[%state66] GR64:%vreg123
3760B		JE_1 <BB#35>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#35 BB#34

3776B	BB#34: derived from LLVM BB %if.then.68
	    Predecessors according to CFG: BB#33
3792B		%vreg125<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%r] GR32:%vreg125
3808B		MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %vreg125; mem:ST4[%retval] GR32:%vreg125
3824B		JMP_1 <BB#37>
	    Successors according to CFG: BB#37

3840B	BB#35: derived from LLVM BB %if.end.69
	    Predecessors according to CFG: BB#33
3856B		JMP_1 <BB#36>
	    Successors according to CFG: BB#36

3872B	BB#36: derived from LLVM BB %if.end.70
	    Predecessors according to CFG: BB#26 BB#35
3888B		JMP_1 <BB#7>
	    Successors according to CFG: BB#7

3904B	BB#37: derived from LLVM BB %return
	    Predecessors according to CFG: BB#24 BB#34 BB#32 BB#31 BB#22 BB#14 BB#8 BB#5 BB#3 BB#1
3920B		%vreg153<def> = MOV64ri <ga:@BZ2_bzDecompress>; GR64:%vreg153
3952B		%vreg154<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg154
3968B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3984B		%RDI<def> = COPY %vreg153; GR64:%vreg153
4000B		%RSI<def> = COPY %vreg154; GR64:%vreg154
4016B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
4032B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4048B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4064B		STACKMAP 7, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
4080B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4096B		%vreg151<def> = MOV32rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD4[%retval] GR32:%vreg151
4112B		%EAX<def> = COPY %vreg151; GR32:%vreg151
4128B		RETQ %EAX<imp-use,kill>

# End machine code for function BZ2_bzDecompress.


selectOrSplit GR64:%vreg1 [16r,224r:0)  0@16r w=4.983553e-03
hints: %RDI
missed hint %RDI
assigning %vreg1 to %RBX: BH [16r,224r:0)  0@16r BL [16r,224r:0)  0@16r

selectOrSplit GR64:%vreg4 [48r,112r:0)  0@48r w=2.176724e-03
hints: %RDI
assigning %vreg4 to %RDI: DIL [48r,112r:0)  0@48r

selectOrSplit GR64:%vreg5 [80r,128r:0)  0@80r w=4.508928e-03
hints: %RSI
assigning %vreg5 to %RSI: SIL [80r,128r:0)  0@80r

selectOrSplit GR64:%vreg34 [896r,928r:0)  0@896r w=8.626159e-05
hints: %RDI
assigning %vreg34 to %RDI: DIL [896r,928r:0)  0@896r

selectOrSplit GR8:%vreg33 [976r,1040r:0)  0@976r w=8.031251e-05
hints: %AL
assigning %vreg33 to %AL: AL [976r,1040r:0)  0@976r

selectOrSplit GR64:%vreg30 [1088r,1120r:0)  0@1088r w=8.626159e-05
hints: %RDI
assigning %vreg30 to %RDI: DIL [1088r,1120r:0)  0@1088r

selectOrSplit GR8:%vreg29 [1168r,1232r:0)  0@1168r w=8.031251e-05
hints: %AL
assigning %vreg29 to %AL: AL [1168r,1232r:0)  0@1168r

selectOrSplit GR64:%vreg61 [1728r,1912r:0)  0@1728r w=4.051425e-06
hints: %RSI
assigning %vreg61 to %RSI: SIL [1728r,1912r:0)  0@1728r

selectOrSplit GR64:%vreg71 [1744r,1908r:0)  0@1744r w=4.195093e-06
hints: %RDI
assigning %vreg71 to %RDI: DIL [1744r,1908r:0)  0@1744r

selectOrSplit GR32:%vreg69 [1776r,1920r:0)  0@1776r w=8.698647e-06
hints: %EDX
assigning %vreg69 to %EDX: DH [1776r,1920r:0)  0@1776r DL [1776r,1920r:0)  0@1776r

selectOrSplit GR32:%vreg66 [1808r,1928r:0)  0@1808r w=9.100124e-06
hints: %ECX
assigning %vreg66 to %ECX: CH [1808r,1928r:0)  0@1808r CL [1808r,1928r:0)  0@1808r

selectOrSplit GR32:%vreg64 [1952r,1952d:0)  0@1952r w=inf
hints: %EAX
assigning %vreg64 to %EAX: AH [1952r,1952d:0)  0@1952r AL [1952r,1952d:0)  0@1952r

selectOrSplit GR64:%vreg76 [2096r,2184r:0)  0@2096r w=4.848427e-06
hints: %RSI
assigning %vreg76 to %RSI: SIL [2096r,2184r:0)  0@2096r

selectOrSplit GR64:%vreg78 [2112r,2180r:0)  0@2112r w=5.055625e-06
hints: %RDI
assigning %vreg78 to %RDI: DIL [2112r,2180r:0)  0@2112r

selectOrSplit GR32:%vreg77 [2224r,2224d:0)  0@2224r w=inf
hints: %EAX
assigning %vreg77 to %EAX: AH [2224r,2224d:0)  0@2224r AL [2224r,2224d:0)  0@2224r

selectOrSplit GR64:%vreg120 [2944r,2976r:0)  0@2944r w=9.173852e-05
hints: %RDI
assigning %vreg120 to %RDI: DIL [2944r,2976r:0)  0@2944r

selectOrSplit GR32:%vreg119 [3024r,3088r:0)  0@3024r w=8.541172e-05
hints: %EAX
assigning %vreg119 to %EAX: AH [3024r,3088r:0)  0@3024r AL [3024r,3088r:0)  0@3024r

selectOrSplit GR64:%vreg130 [3216r,3400r:0)  0@3216r w=8.609279e-06
hints: %RSI
assigning %vreg130 to %RSI: SIL [3216r,3400r:0)  0@3216r

selectOrSplit GR64:%vreg140 [3232r,3396r:0)  0@3232r w=8.914571e-06
hints: %RDI
assigning %vreg140 to %RDI: DIL [3232r,3396r:0)  0@3232r

selectOrSplit GR32:%vreg138 [3264r,3408r:0)  0@3264r w=1.848463e-05
hints: %EDX
assigning %vreg138 to %EDX: DH [3264r,3408r:0)  0@3264r DL [3264r,3408r:0)  0@3264r

selectOrSplit GR32:%vreg135 [3296r,3416r:0)  0@3296r w=1.933776e-05
hints: %ECX
assigning %vreg135 to %ECX: CH [3296r,3416r:0)  0@3296r CL [3296r,3416r:0)  0@3296r

selectOrSplit GR32:%vreg133 [3440r,3440d:0)  0@3440r w=inf
hints: %EAX
assigning %vreg133 to %EAX: AH [3440r,3440d:0)  0@3440r AL [3440r,3440d:0)  0@3440r

selectOrSplit GR64:%vreg153 [3920r,3984r:0)  0@3920r w=2.176724e-03
hints: %RDI
assigning %vreg153 to %RDI: DIL [3920r,3984r:0)  0@3920r

selectOrSplit GR64:%vreg154 [3952r,4000r:0)  0@3952r w=4.508928e-03
hints: %RSI
assigning %vreg154 to %RSI: SIL [3952r,4000r:0)  0@3952r

selectOrSplit GR32:%vreg151 [4096r,4112r:0)  0@4096r w=inf
hints: %EAX
assigning %vreg151 to %EAX: AH [4096r,4112r:0)  0@4096r AL [4096r,4112r:0)  0@4096r

selectOrSplit GR64:%vreg12 [336r,352r:0)  0@336r w=inf
assigning %vreg12 to %RAX: AH [336r,352r:0)  0@336r AL [336r,352r:0)  0@336r

selectOrSplit GR64:%vreg9 [352r,384r:0)  0@352r w=inf
assigning %vreg9 to %RAX: AH [352r,384r:0)  0@352r AL [352r,384r:0)  0@352r

selectOrSplit GR64:%vreg17 [496r,512r:0)  0@496r w=inf
assigning %vreg17 to %RAX: AH [496r,512r:0)  0@496r AL [496r,512r:0)  0@496r

selectOrSplit GR64:%vreg16 [512r,528r:0)  0@512r w=inf
assigning %vreg16 to %RAX: AH [512r,528r:0)  0@512r AL [512r,528r:0)  0@512r

selectOrSplit GR64:%vreg20 [656r,672r:0)  0@656r w=inf
assigning %vreg20 to %RAX: AH [656r,672r:0)  0@656r AL [656r,672r:0)  0@656r

selectOrSplit GR64:%vreg23 [768r,784r:0)  0@768r w=inf
assigning %vreg23 to %RAX: AH [768r,784r:0)  0@768r AL [768r,784r:0)  0@768r

selectOrSplit GR64:%vreg26 [832r,848r:0)  0@832r w=inf
assigning %vreg26 to %RAX: AH [832r,848r:0)  0@832r AL [832r,848r:0)  0@832r

selectOrSplit GR64:%vreg45 [1360r,1376r:0)  0@1360r w=inf
assigning %vreg45 to %RAX: AH [1360r,1376r:0)  0@1360r AL [1360r,1376r:0)  0@1360r

selectOrSplit GR32:%vreg44 [1376r,1456r:0)  0@1376r w=7.686676e-05
assigning %vreg44 to %EAX: AH [1376r,1456r:0)  0@1376r AL [1376r,1456r:0)  0@1376r

selectOrSplit GR64:%vreg42 [1392r,1408r:0)  0@1392r w=inf
assigning %vreg42 to %RCX: CH [1392r,1408r:0)  0@1392r CL [1392r,1408r:0)  0@1392r

selectOrSplit GR32:%vreg39 [1408r,1440r:0)[1440r,1456r:1)  0@1408r 1@1440r w=inf
assigning %vreg39 to %ECX: CH [1408r,1440r:0)[1440r,1456r:1)  0@1408r 1@1440r CL [1408r,1440r:0)[1440r,1456r:1)  0@1408r 1@1440r

selectOrSplit GR64:%vreg48 [1504r,1520r:0)  0@1504r w=inf
assigning %vreg48 to %RAX: AH [1504r,1520r:0)  0@1504r AL [1504r,1520r:0)  0@1504r

selectOrSplit GR64:%vreg59 [1568r,1584r:0)  0@1568r w=inf
assigning %vreg59 to %RAX: AH [1568r,1584r:0)  0@1568r AL [1568r,1584r:0)  0@1568r

selectOrSplit GR32:%vreg56 [1584r,1616r:0)[1616r,1648r:1)  0@1584r 1@1616r w=3.786540e-05
assigning %vreg56 to %EAX: AH [1584r,1616r:0)[1616r,1648r:1)  0@1584r 1@1616r AL [1584r,1616r:0)[1616r,1648r:1)  0@1584r 1@1616r

selectOrSplit GR64:%vreg54 [1632r,1648r:0)  0@1632r w=inf
assigning %vreg54 to %RCX: CH [1632r,1648r:0)  0@1632r CL [1632r,1648r:0)  0@1632r

selectOrSplit GR64:%vreg51 [1664r,1680r:0)  0@1664r w=inf
assigning %vreg51 to %RAX: AH [1664r,1680r:0)  0@1664r AL [1664r,1680r:0)  0@1664r

selectOrSplit GR64:%vreg70 [1760r,1776r:0)  0@1760r w=inf
assigning %vreg70 to %RAX: AH [1760r,1776r:0)  0@1760r AL [1760r,1776r:0)  0@1760r

selectOrSplit GR64:%vreg67 [1792r,1808r:0)  0@1792r w=inf
assigning %vreg67 to %RAX: AH [1792r,1808r:0)  0@1792r AL [1792r,1808r:0)  0@1792r

selectOrSplit GR64:%vreg74 [2032r,2048r:0)  0@2032r w=inf
assigning %vreg74 to %RAX: AH [2032r,2048r:0)  0@2032r AL [2032r,2048r:0)  0@2032r

selectOrSplit GR64:%vreg85 [2304r,2320r:0)  0@2304r w=inf
assigning %vreg85 to %RAX: AH [2304r,2320r:0)  0@2304r AL [2304r,2320r:0)  0@2304r

selectOrSplit GR32:%vreg84 [2320r,2352r:0)  0@2320r w=2.033512e-05
assigning %vreg84 to %EAX: AH [2320r,2352r:0)  0@2320r AL [2320r,2352r:0)  0@2320r

selectOrSplit GR64:%vreg82 [2336r,2352r:0)  0@2336r w=inf
assigning %vreg82 to %RCX: CH [2336r,2352r:0)  0@2336r CL [2336r,2352r:0)  0@2336r

selectOrSplit GR64:%vreg112 [2448r,2464r:0)  0@2448r w=inf
assigning %vreg112 to %RAX: AH [2448r,2464r:0)  0@2448r AL [2448r,2464r:0)  0@2448r

selectOrSplit GR32:%vreg102 [2464r,2496r:2)[2496r,2592r:0)[2592r,2624r:1)  0@2496r 1@2592r 2@2464r w=2.509935e-05
assigning %vreg102 to %EAX: AH [2464r,2496r:2)[2496r,2592r:0)[2592r,2624r:1)  0@2496r 1@2592r 2@2464r AL [2464r,2496r:2)[2496r,2592r:0)[2592r,2624r:1)  0@2496r 1@2592r 2@2464r

selectOrSplit GR64:%vreg107 [2512r,2528r:0)  0@2512r w=inf
assigning %vreg107 to %RCX: CH [2512r,2528r:0)  0@2512r CL [2512r,2528r:0)  0@2512r

selectOrSplit GR32:%vreg104 [2528r,2560r:0)[2560r,2592r:1)  0@2528r 1@2560r w=inf
assigning %vreg104 to %ECX: CH [2528r,2560r:0)[2560r,2592r:1)  0@2528r 1@2560r CL [2528r,2560r:0)[2560r,2592r:1)  0@2528r 1@2560r

selectOrSplit GR64:%vreg99 [2608r,2624r:0)  0@2608r w=inf
assigning %vreg99 to %RCX: CH [2608r,2624r:0)  0@2608r CL [2608r,2624r:0)  0@2608r

selectOrSplit GR64:%vreg96 [2640r,2656r:0)  0@2640r w=inf
assigning %vreg96 to %RAX: AH [2640r,2656r:0)  0@2640r AL [2640r,2656r:0)  0@2640r

selectOrSplit GR32:%vreg92 [2656r,2704r:0)[2704r,2720r:1)  0@2656r 1@2704r w=2.019488e-05
assigning %vreg92 to %EAX: AH [2656r,2704r:0)[2704r,2720r:1)  0@2656r 1@2704r AL [2656r,2704r:0)[2704r,2720r:1)  0@2656r 1@2704r

selectOrSplit GR64:%vreg93 [2672r,2720r:0)  0@2672r w=1.568710e-05
assigning %vreg93 to %RCX: CH [2672r,2720r:0)  0@2672r CL [2672r,2720r:0)  0@2672r

selectOrSplit GR64:%vreg87 [2736r,2752r:0)  0@2736r w=inf
assigning %vreg87 to %RAX: AH [2736r,2752r:0)  0@2736r AL [2736r,2752r:0)  0@2736r

selectOrSplit GR64:%vreg115 [2880r,2896r:0)  0@2880r w=inf
assigning %vreg115 to %RAX: AH [2880r,2896r:0)  0@2880r AL [2880r,2896r:0)  0@2880r

selectOrSplit GR64:%vreg128 [3152r,3168r:0)  0@3152r w=inf
assigning %vreg128 to %RAX: AH [3152r,3168r:0)  0@3152r AL [3152r,3168r:0)  0@3152r

selectOrSplit GR64:%vreg139 [3248r,3264r:0)  0@3248r w=inf
assigning %vreg139 to %RAX: AH [3248r,3264r:0)  0@3248r AL [3248r,3264r:0)  0@3248r

selectOrSplit GR64:%vreg136 [3280r,3296r:0)  0@3280r w=inf
assigning %vreg136 to %RAX: AH [3280r,3296r:0)  0@3280r AL [3280r,3296r:0)  0@3280r

selectOrSplit GR64:%vreg147 [3520r,3536r:0)  0@3520r w=inf
assigning %vreg147 to %RAX: AH [3520r,3536r:0)  0@3520r AL [3520r,3536r:0)  0@3520r

selectOrSplit GR32:%vreg146 [3536r,3568r:0)  0@3536r w=4.609295e-05
assigning %vreg146 to %EAX: AH [3536r,3568r:0)  0@3536r AL [3536r,3568r:0)  0@3536r

selectOrSplit GR64:%vreg144 [3552r,3568r:0)  0@3552r w=inf
assigning %vreg144 to %RCX: CH [3552r,3568r:0)  0@3552r CL [3552r,3568r:0)  0@3552r

selectOrSplit GR32:%vreg149 [3664r,3680r:0)  0@3664r w=inf
assigning %vreg149 to %EAX: AH [3664r,3680r:0)  0@3664r AL [3664r,3680r:0)  0@3664r

selectOrSplit GR64:%vreg123 [3728r,3744r:0)  0@3728r w=inf
assigning %vreg123 to %RAX: AH [3728r,3744r:0)  0@3728r AL [3728r,3744r:0)  0@3728r

selectOrSplit GR32:%vreg125 [3792r,3808r:0)  0@3792r w=inf
assigning %vreg125 to %EAX: AH [3792r,3808r:0)  0@3792r AL [3792r,3808r:0)  0@3792r

********** STACK TRANSFORMATION METADATA **********
********** Function: BZ2_bzDecompress
********** REGISTER MAP **********
[%vreg1 -> %RBX] GR64
[%vreg4 -> %RDI] GR64
[%vreg5 -> %RSI] GR64
[%vreg9 -> %RAX] GR64
[%vreg12 -> %RAX] GR64
[%vreg16 -> %RAX] GR64
[%vreg17 -> %RAX] GR64
[%vreg20 -> %RAX] GR64
[%vreg23 -> %RAX] GR64
[%vreg26 -> %RAX] GR64
[%vreg29 -> %AL] GR8
[%vreg30 -> %RDI] GR64
[%vreg33 -> %AL] GR8
[%vreg34 -> %RDI] GR64
[%vreg39 -> %ECX] GR32
[%vreg42 -> %RCX] GR64
[%vreg44 -> %EAX] GR32
[%vreg45 -> %RAX] GR64
[%vreg48 -> %RAX] GR64
[%vreg51 -> %RAX] GR64
[%vreg54 -> %RCX] GR64
[%vreg56 -> %EAX] GR32
[%vreg59 -> %RAX] GR64
[%vreg61 -> %RSI] GR64
[%vreg64 -> %EAX] GR32
[%vreg66 -> %ECX] GR32
[%vreg67 -> %RAX] GR64
[%vreg69 -> %EDX] GR32
[%vreg70 -> %RAX] GR64
[%vreg71 -> %RDI] GR64
[%vreg74 -> %RAX] GR64
[%vreg76 -> %RSI] GR64
[%vreg77 -> %EAX] GR32
[%vreg78 -> %RDI] GR64
[%vreg82 -> %RCX] GR64
[%vreg84 -> %EAX] GR32
[%vreg85 -> %RAX] GR64
[%vreg87 -> %RAX] GR64
[%vreg92 -> %EAX] GR32
[%vreg93 -> %RCX] GR64
[%vreg96 -> %RAX] GR64
[%vreg99 -> %RCX] GR64
[%vreg102 -> %EAX] GR32
[%vreg104 -> %ECX] GR32
[%vreg107 -> %RCX] GR64
[%vreg112 -> %RAX] GR64
[%vreg115 -> %RAX] GR64
[%vreg119 -> %EAX] GR32
[%vreg120 -> %RDI] GR64
[%vreg123 -> %RAX] GR64
[%vreg125 -> %EAX] GR32
[%vreg128 -> %RAX] GR64
[%vreg130 -> %RSI] GR64
[%vreg133 -> %EAX] GR32
[%vreg135 -> %ECX] GR32
[%vreg136 -> %RAX] GR64
[%vreg138 -> %EDX] GR32
[%vreg139 -> %RAX] GR64
[%vreg140 -> %RDI] GR64
[%vreg144 -> %RCX] GR64
[%vreg146 -> %EAX] GR32
[%vreg147 -> %RAX] GR64
[%vreg149 -> %EAX] GR32
[%vreg151 -> %EAX] GR32
[%vreg153 -> %RDI] GR64
[%vreg154 -> %RSI] GR64


Stackmap 0:
  STACKMAP 0, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, %vreg1, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3] LD8[FixedStack1] GR64:%vreg1

i8* %corrupt: in stack slot 2 (size: 1)
i32* %r: in stack slot 4 (size: 4)
i32* %retval: in stack slot 0 (size: 4)
%struct.DState** %s: in stack slot 3 (size: 8)
%struct.bz_stream* %strm: in register %RBX (vreg 1)
%struct.bz_stream** %strm.addr: in stack slot 1 (size: 8)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]

i8* %corrupt: in stack slot 2 (size: 1)
i32* %r: in stack slot 4 (size: 4)
i32* %retval: in stack slot 0 (size: 4)
%struct.DState** %s: in stack slot 3 (size: 8)

Duplicate operand locations:


Stackmap 2:
  STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]

i8* %corrupt: in stack slot 2 (size: 1)
i32* %r: in stack slot 4 (size: 4)
i32* %retval: in stack slot 0 (size: 4)
%struct.DState** %s: in stack slot 3 (size: 8)

Duplicate operand locations:


Stackmap 3:
  STACKMAP 3, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]

i8* %corrupt: in stack slot 2 (size: 1)
i32* %r: in stack slot 4 (size: 4)
i32* %retval: in stack slot 0 (size: 4)
%struct.DState** %s: in stack slot 3 (size: 8)

Duplicate operand locations:


Stackmap 4:
  STACKMAP 4, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]

i8* %corrupt: in stack slot 2 (size: 1)
i32* %r: in stack slot 4 (size: 4)
i32* %retval: in stack slot 0 (size: 4)
%struct.DState** %s: in stack slot 3 (size: 8)

Duplicate operand locations:


Stackmap 5:
  STACKMAP 5, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]

i8* %corrupt: in stack slot 2 (size: 1)
i32* %r: in stack slot 4 (size: 4)
i32* %retval: in stack slot 0 (size: 4)
%struct.DState** %s: in stack slot 3 (size: 8)

Duplicate operand locations:


Stackmap 6:
  STACKMAP 6, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]

i32* %r: in stack slot 4 (size: 4)
i32* %retval: in stack slot 0 (size: 4)
%struct.DState** %s: in stack slot 3 (size: 8)

Duplicate operand locations:


Stackmap 7:
  STACKMAP 7, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)

i32* %retval: in stack slot 0 (size: 4)

Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, %vreg1, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3] LD8[FixedStack1] GR64:%vreg1
  -> Call instruction SlotIndex 144B, searching vregs 0 -> 155 and stack slots -1 -> 5

  STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
  -> Call instruction SlotIndex 944B, searching vregs 0 -> 155 and stack slots -1 -> 5

  STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
  -> Call instruction SlotIndex 1136B, searching vregs 0 -> 155 and stack slots -1 -> 5

  STACKMAP 3, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
  -> Call instruction SlotIndex 1936B, searching vregs 0 -> 155 and stack slots -1 -> 5

  STACKMAP 4, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
  -> Call instruction SlotIndex 2192B, searching vregs 0 -> 155 and stack slots -1 -> 5

  STACKMAP 5, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
  -> Call instruction SlotIndex 2992B, searching vregs 0 -> 155 and stack slots -1 -> 5

  STACKMAP 6, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
  -> Call instruction SlotIndex 3424B, searching vregs 0 -> 155 and stack slots -1 -> 5

  STACKMAP 7, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
  -> Call instruction SlotIndex 4016B, searching vregs 0 -> 155 and stack slots -1 -> 5

********** REWRITE VIRTUAL REGISTERS **********
********** Function: BZ2_bzDecompress
********** REGISTER MAP **********
[%vreg1 -> %RBX] GR64
[%vreg4 -> %RDI] GR64
[%vreg5 -> %RSI] GR64
[%vreg9 -> %RAX] GR64
[%vreg12 -> %RAX] GR64
[%vreg16 -> %RAX] GR64
[%vreg17 -> %RAX] GR64
[%vreg20 -> %RAX] GR64
[%vreg23 -> %RAX] GR64
[%vreg26 -> %RAX] GR64
[%vreg29 -> %AL] GR8
[%vreg30 -> %RDI] GR64
[%vreg33 -> %AL] GR8
[%vreg34 -> %RDI] GR64
[%vreg39 -> %ECX] GR32
[%vreg42 -> %RCX] GR64
[%vreg44 -> %EAX] GR32
[%vreg45 -> %RAX] GR64
[%vreg48 -> %RAX] GR64
[%vreg51 -> %RAX] GR64
[%vreg54 -> %RCX] GR64
[%vreg56 -> %EAX] GR32
[%vreg59 -> %RAX] GR64
[%vreg61 -> %RSI] GR64
[%vreg64 -> %EAX] GR32
[%vreg66 -> %ECX] GR32
[%vreg67 -> %RAX] GR64
[%vreg69 -> %EDX] GR32
[%vreg70 -> %RAX] GR64
[%vreg71 -> %RDI] GR64
[%vreg74 -> %RAX] GR64
[%vreg76 -> %RSI] GR64
[%vreg77 -> %EAX] GR32
[%vreg78 -> %RDI] GR64
[%vreg82 -> %RCX] GR64
[%vreg84 -> %EAX] GR32
[%vreg85 -> %RAX] GR64
[%vreg87 -> %RAX] GR64
[%vreg92 -> %EAX] GR32
[%vreg93 -> %RCX] GR64
[%vreg96 -> %RAX] GR64
[%vreg99 -> %RCX] GR64
[%vreg102 -> %EAX] GR32
[%vreg104 -> %ECX] GR32
[%vreg107 -> %RCX] GR64
[%vreg112 -> %RAX] GR64
[%vreg115 -> %RAX] GR64
[%vreg119 -> %EAX] GR32
[%vreg120 -> %RDI] GR64
[%vreg123 -> %RAX] GR64
[%vreg125 -> %EAX] GR32
[%vreg128 -> %RAX] GR64
[%vreg130 -> %RSI] GR64
[%vreg133 -> %EAX] GR32
[%vreg135 -> %ECX] GR32
[%vreg136 -> %RAX] GR64
[%vreg138 -> %EDX] GR32
[%vreg139 -> %RAX] GR64
[%vreg140 -> %RDI] GR64
[%vreg144 -> %RCX] GR64
[%vreg146 -> %EAX] GR32
[%vreg147 -> %RAX] GR64
[%vreg149 -> %EAX] GR32
[%vreg151 -> %EAX] GR32
[%vreg153 -> %RDI] GR64
[%vreg154 -> %RSI] GR64

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI
16B		%vreg1<def> = COPY %RDI; GR64:%vreg1
48B		%vreg4<def> = MOV64ri <ga:@BZ2_bzDecompress>; GR64:%vreg4
80B		%vreg5<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg5
96B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
112B		%RDI<def> = COPY %vreg4<kill>; GR64:%vreg4
128B		%RSI<def> = COPY %vreg5<kill>; GR64:%vreg5
144B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
160B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
192B		STACKMAP 0, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, %vreg1, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3] LD8[FixedStack1] GR64:%vreg1
208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg1<kill>; mem:ST8[%strm.addr] GR64:%vreg1
240B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%strm.addr]
256B		JNE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1
> %RBX<def> = COPY %RDI
> %RDI<def> = MOV64ri <ga:@BZ2_bzDecompress>
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 0, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, %RBX, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3] LD8[FixedStack1]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %RBX<kill>; mem:ST8[%strm.addr]
> CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%strm.addr]
> JNE_1 <BB#2>, %EFLAGS<imp-use,kill>
272B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
288B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
304B		JMP_1 <BB#37>
	    Successors according to CFG: BB#37
> MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
> JMP_1 <BB#37>
320B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0
336B		%vreg12<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg12
352B		%vreg9<def> = MOV64rm %vreg12<kill>, 1, %noreg, 48, %noreg; mem:LD8[%state] GR64:%vreg9,%vreg12
384B		MOV64mr <fi#3>, 1, %noreg, 0, %noreg, %vreg9<kill>; mem:ST8[%s] GR64:%vreg9
400B		CMP64mi8 <fi#3>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%s]
416B		JNE_1 <BB#4>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#4 BB#3
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 48, %noreg; mem:LD8[%state]
> MOV64mr <fi#3>, 1, %noreg, 0, %noreg, %RAX<kill>; mem:ST8[%s]
> CMP64mi8 <fi#3>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%s]
> JNE_1 <BB#4>, %EFLAGS<imp-use,kill>
432B	BB#3: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#2
448B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
464B		JMP_1 <BB#37>
	    Successors according to CFG: BB#37
> MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
> JMP_1 <BB#37>
480B	BB#4: derived from LLVM BB %if.end.3
	    Predecessors according to CFG: BB#2
496B		%vreg17<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg17
512B		%vreg16<def> = MOV64rm %vreg17<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm4] GR64:%vreg16,%vreg17
528B		CMP64rm %vreg16<kill>, <fi#1>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD8[%strm.addr] GR64:%vreg16
544B		JE_1 <BB#6>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#6 BB#5
> %RAX<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm4]
> CMP64rm %RAX<kill>, <fi#1>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD8[%strm.addr]
> JE_1 <BB#6>, %EFLAGS<imp-use,kill>
560B	BB#5: derived from LLVM BB %if.then.6
	    Predecessors according to CFG: BB#4
576B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
592B		JMP_1 <BB#37>
	    Successors according to CFG: BB#37
> MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
> JMP_1 <BB#37>
608B	BB#6: derived from LLVM BB %if.end.7
	    Predecessors according to CFG: BB#4
624B		JMP_1 <BB#7>
	    Successors according to CFG: BB#7
> JMP_1 <BB#7>
640B	BB#7: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#6 BB#36
656B		%vreg20<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg20
672B		CMP32mi8 %vreg20<kill>, 1, %noreg, 8, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%state8] GR64:%vreg20
688B		JNE_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#8
> %RAX<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> CMP32mi8 %RAX<kill>, 1, %noreg, 8, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%state8]
> JNE_1 <BB#9>, %EFLAGS<imp-use,kill>
704B	BB#8: derived from LLVM BB %if.then.10
	    Predecessors according to CFG: BB#7
720B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -1; mem:ST4[%retval]
736B		JMP_1 <BB#37>
	    Successors according to CFG: BB#37
> MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -1; mem:ST4[%retval]
> JMP_1 <BB#37>
752B	BB#9: derived from LLVM BB %if.end.11
	    Predecessors according to CFG: BB#7
768B		%vreg23<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg23
784B		CMP32mi8 %vreg23<kill>, 1, %noreg, 8, %noreg, 2, %EFLAGS<imp-def>; mem:LD4[%state12] GR64:%vreg23
800B		JNE_1 <BB#26>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#26 BB#10
> %RAX<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> CMP32mi8 %RAX<kill>, 1, %noreg, 8, %noreg, 2, %EFLAGS<imp-def>; mem:LD4[%state12]
> JNE_1 <BB#26>, %EFLAGS<imp-use,kill>
816B	BB#10: derived from LLVM BB %if.then.14
	    Predecessors according to CFG: BB#9
832B		%vreg26<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg26
848B		CMP8mi %vreg26<kill>, 1, %noreg, 44, %noreg, 0, %EFLAGS<imp-def>; mem:LD1[%smallDecompress] GR64:%vreg26
864B		JE_1 <BB#12>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#12 BB#11
> %RAX<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> CMP8mi %RAX<kill>, 1, %noreg, 44, %noreg, 0, %EFLAGS<imp-def>; mem:LD1[%smallDecompress]
> JE_1 <BB#12>, %EFLAGS<imp-use,kill>
880B	BB#11: derived from LLVM BB %if.then.15
	    Predecessors according to CFG: BB#10
896B		%vreg34<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg34
912B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
928B		%RDI<def> = COPY %vreg34<kill>; GR64:%vreg34
944B		CALL64pcrel32 <ga:@unRLE_obuf_to_output_SMALL>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %AL<imp-def>
960B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
976B		%vreg33<def> = COPY %AL; GR8:%vreg33
992B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1008B		STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
1024B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1040B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg33<kill>; mem:ST1[%corrupt] GR8:%vreg33
1056B		JMP_1 <BB#13>
	    Successors according to CFG: BB#13
> %RDI<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@unRLE_obuf_to_output_SMALL>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %AL<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %AL<def> = COPY %AL
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %AL<kill>; mem:ST1[%corrupt]
> JMP_1 <BB#13>
1072B	BB#12: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#10
1088B		%vreg30<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg30
1104B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1120B		%RDI<def> = COPY %vreg30<kill>; GR64:%vreg30
1136B		CALL64pcrel32 <ga:@unRLE_obuf_to_output_FAST>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %AL<imp-def>
1152B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1168B		%vreg29<def> = COPY %AL; GR8:%vreg29
1184B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1200B		STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
1216B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1232B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg29<kill>; mem:ST1[%corrupt] GR8:%vreg29
	    Successors according to CFG: BB#13
> %RDI<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@unRLE_obuf_to_output_FAST>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %AL<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %AL<def> = COPY %AL
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %AL<kill>; mem:ST1[%corrupt]
1248B	BB#13: derived from LLVM BB %if.end.17
	    Predecessors according to CFG: BB#12 BB#11
1264B		CMP8mi <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD1[%corrupt]
1280B		JE_1 <BB#15>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#15 BB#14
> CMP8mi <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD1[%corrupt]
> JE_1 <BB#15>, %EFLAGS<imp-use,kill>
1296B	BB#14: derived from LLVM BB %if.then.19
	    Predecessors according to CFG: BB#13
1312B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -4; mem:ST4[%retval]
1328B		JMP_1 <BB#37>
	    Successors according to CFG: BB#37
> MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -4; mem:ST4[%retval]
> JMP_1 <BB#37>
1344B	BB#15: derived from LLVM BB %if.end.20
	    Predecessors according to CFG: BB#13
1360B		%vreg45<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg45
1376B		%vreg44<def> = MOV32rm %vreg45<kill>, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used] GR32:%vreg44 GR64:%vreg45
1392B		%vreg42<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg42
1408B		%vreg39<def> = MOV32rm %vreg42<kill>, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock] GR32:%vreg39 GR64:%vreg42
1440B		%vreg39<def,tied1> = ADD32ri8 %vreg39<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg39
1456B		CMP32rr %vreg44<kill>, %vreg39<kill>, %EFLAGS<imp-def>; GR32:%vreg44,%vreg39
1472B		JNE_1 <BB#24>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#24 BB#16
> %RAX<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used]
> %RCX<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> %ECX<def> = MOV32rm %RCX<kill>, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> CMP32rr %EAX<kill>, %ECX<kill>, %EFLAGS<imp-def>
> JNE_1 <BB#24>, %EFLAGS<imp-use,kill>
1488B	BB#16: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#15
1504B		%vreg48<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg48
1520B		CMP32mi8 %vreg48<kill>, 1, %noreg, 16, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%state_out_len] GR64:%vreg48
1536B		JNE_1 <BB#24>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#24 BB#17
> %RAX<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> CMP32mi8 %RAX<kill>, 1, %noreg, 16, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%state_out_len]
> JNE_1 <BB#24>, %EFLAGS<imp-use,kill>
1552B	BB#17: derived from LLVM BB %if.then.23
	    Predecessors according to CFG: BB#16
1568B		%vreg59<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg59
1584B		%vreg56<def> = MOV32rm %vreg59<kill>, 1, %noreg, 3184, %noreg; mem:LD4[%calculatedBlockCRC] GR32:%vreg56 GR64:%vreg59
1616B		%vreg56<def,tied1> = XOR32ri8 %vreg56<kill,tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg56
1632B		%vreg54<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg54
1648B		MOV32mr %vreg54<kill>, 1, %noreg, 3184, %noreg, %vreg56<kill>; mem:ST4[%calculatedBlockCRC24] GR64:%vreg54 GR32:%vreg56
1664B		%vreg51<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg51
1680B		CMP32mi8 %vreg51<kill>, 1, %noreg, 52, %noreg, 3, %EFLAGS<imp-def>; mem:LD4[%verbosity] GR64:%vreg51
1696B		JL_1 <BB#19>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#19 BB#18
> %RAX<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 3184, %noreg; mem:LD4[%calculatedBlockCRC]
> %EAX<def,tied1> = XOR32ri8 %EAX<kill,tied0>, -1, %EFLAGS<imp-def,dead>
> %RCX<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> MOV32mr %RCX<kill>, 1, %noreg, 3184, %noreg, %EAX<kill>; mem:ST4[%calculatedBlockCRC24]
> %RAX<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> CMP32mi8 %RAX<kill>, 1, %noreg, 52, %noreg, 3, %EFLAGS<imp-def>; mem:LD4[%verbosity]
> JL_1 <BB#19>, %EFLAGS<imp-use,kill>
1712B	BB#18: derived from LLVM BB %if.then.26
	    Predecessors according to CFG: BB#17
1728B		%vreg61<def> = MOV64ri <ga:@bzlib__str_2___0x_08x__>; GR64:%vreg61
1744B		%vreg71<def> = MOV64rm %noreg, 1, %noreg, <ga:@stderr>, %noreg; mem:LD8[@stderr] GR64:%vreg71
1760B		%vreg70<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg70
1776B		%vreg69<def> = MOV32rm %vreg70<kill>, 1, %noreg, 3176, %noreg; mem:LD4[%storedBlockCRC] GR32:%vreg69 GR64:%vreg70
1792B		%vreg67<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg67
1808B		%vreg66<def> = MOV32rm %vreg67<kill>, 1, %noreg, 3184, %noreg; mem:LD4[%calculatedBlockCRC27] GR32:%vreg66 GR64:%vreg67
1824B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1904B		%AL<def> = MOV8ri 0
1908B		%RDI<def> = COPY %vreg71<kill>; GR64:%vreg71
1912B		%RSI<def> = COPY %vreg61<kill>; GR64:%vreg61
1920B		%EDX<def> = COPY %vreg69<kill>; GR32:%vreg69
1928B		%ECX<def> = COPY %vreg66<kill>; GR32:%vreg66
1936B		CALL64pcrel32 <ga:@fprintf>, <regmask>, %RSP<imp-use>, %AL<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %EDX<imp-use>, %ECX<imp-use>, %EAX<imp-def>
1944B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1952B		%vreg64<def,dead> = COPY %EAX; GR32:%vreg64
1968B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1984B		STACKMAP 3, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
2000B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#19
> %RSI<def> = MOV64ri <ga:@bzlib__str_2___0x_08x__>
> %RDI<def> = MOV64rm %noreg, 1, %noreg, <ga:@stderr>, %noreg; mem:LD8[@stderr]
> %RAX<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> %EDX<def> = MOV32rm %RAX<kill>, 1, %noreg, 3176, %noreg; mem:LD4[%storedBlockCRC]
> %RAX<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> %ECX<def> = MOV32rm %RAX<kill>, 1, %noreg, 3184, %noreg; mem:LD4[%calculatedBlockCRC27]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %AL<def> = MOV8ri 0
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> %EDX<def> = COPY %EDX<kill>
Deleting identity copy.
> %ECX<def> = COPY %ECX<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@fprintf>, <regmask>, %RSP<imp-use>, %AL<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %EDX<imp-use>, %ECX<imp-use>, %EAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def,dead> = COPY %EAX
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 3, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2016B	BB#19: derived from LLVM BB %if.end.29
	    Predecessors according to CFG: BB#17 BB#18
2032B		%vreg74<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg74
2048B		CMP32mi8 %vreg74<kill>, 1, %noreg, 52, %noreg, 2, %EFLAGS<imp-def>; mem:LD4[%verbosity30] GR64:%vreg74
2064B		JL_1 <BB#21>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#21 BB#20
> %RAX<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> CMP32mi8 %RAX<kill>, 1, %noreg, 52, %noreg, 2, %EFLAGS<imp-def>; mem:LD4[%verbosity30]
> JL_1 <BB#21>, %EFLAGS<imp-use,kill>
2080B	BB#20: derived from LLVM BB %if.then.32
	    Predecessors according to CFG: BB#19
2096B		%vreg76<def> = MOV64ri <ga:@bzlib__str_3___>; GR64:%vreg76
2112B		%vreg78<def> = MOV64rm %noreg, 1, %noreg, <ga:@stderr>, %noreg; mem:LD8[@stderr] GR64:%vreg78
2128B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2176B		%AL<def> = MOV8ri 0
2180B		%RDI<def> = COPY %vreg78<kill>; GR64:%vreg78
2184B		%RSI<def> = COPY %vreg76<kill>; GR64:%vreg76
2192B		CALL64pcrel32 <ga:@fprintf>, <regmask>, %RSP<imp-use>, %AL<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %EAX<imp-def>
2208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2224B		%vreg77<def,dead> = COPY %EAX; GR32:%vreg77
2240B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2256B		STACKMAP 4, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
2272B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#21
> %RSI<def> = MOV64ri <ga:@bzlib__str_3___>
> %RDI<def> = MOV64rm %noreg, 1, %noreg, <ga:@stderr>, %noreg; mem:LD8[@stderr]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %AL<def> = MOV8ri 0
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@fprintf>, <regmask>, %RSP<imp-use>, %AL<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %EAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def,dead> = COPY %EAX
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 4, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2288B	BB#21: derived from LLVM BB %if.end.34
	    Predecessors according to CFG: BB#19 BB#20
2304B		%vreg85<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg85
2320B		%vreg84<def> = MOV32rm %vreg85<kill>, 1, %noreg, 3184, %noreg; mem:LD4[%calculatedBlockCRC35] GR32:%vreg84 GR64:%vreg85
2336B		%vreg82<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg82
2352B		CMP32rm %vreg84<kill>, %vreg82<kill>, 1, %noreg, 3176, %noreg, %EFLAGS<imp-def>; mem:LD4[%storedBlockCRC36] GR32:%vreg84 GR64:%vreg82
2368B		JE_1 <BB#23>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#23 BB#22
> %RAX<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 3184, %noreg; mem:LD4[%calculatedBlockCRC35]
> %RCX<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> CMP32rm %EAX<kill>, %RCX<kill>, 1, %noreg, 3176, %noreg, %EFLAGS<imp-def>; mem:LD4[%storedBlockCRC36]
> JE_1 <BB#23>, %EFLAGS<imp-use,kill>
2384B	BB#22: derived from LLVM BB %if.then.38
	    Predecessors according to CFG: BB#21
2400B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -4; mem:ST4[%retval]
2416B		JMP_1 <BB#37>
	    Successors according to CFG: BB#37
> MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -4; mem:ST4[%retval]
> JMP_1 <BB#37>
2432B	BB#23: derived from LLVM BB %if.end.39
	    Predecessors according to CFG: BB#21
2448B		%vreg112<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg112
2464B		%vreg102<def> = MOV32rm %vreg112<kill>, 1, %noreg, 3188, %noreg; mem:LD4[%calculatedCombinedCRC] GR32:%vreg102 GR64:%vreg112
2496B		%vreg102<def,tied1> = SHL32ri %vreg102<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg102
2512B		%vreg107<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg107
2528B		%vreg104<def> = MOV32rm %vreg107<kill>, 1, %noreg, 3188, %noreg; mem:LD4[%calculatedCombinedCRC40] GR32:%vreg104 GR64:%vreg107
2560B		%vreg104<def,tied1> = SHR32ri %vreg104<kill,tied0>, 31, %EFLAGS<imp-def,dead>; GR32:%vreg104
2592B		%vreg102<def,tied1> = OR32rr %vreg102<kill,tied0>, %vreg104<kill>, %EFLAGS<imp-def,dead>; GR32:%vreg102,%vreg104
2608B		%vreg99<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg99
2624B		MOV32mr %vreg99<kill>, 1, %noreg, 3188, %noreg, %vreg102<kill>; mem:ST4[%calculatedCombinedCRC41] GR64:%vreg99 GR32:%vreg102
2640B		%vreg96<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg96
2656B		%vreg92<def> = MOV32rm %vreg96<kill>, 1, %noreg, 3184, %noreg; mem:LD4[%calculatedBlockCRC42] GR32:%vreg92 GR64:%vreg96
2672B		%vreg93<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg93
2704B		%vreg92<def,tied1> = XOR32rm %vreg92<kill,tied0>, %vreg93, 1, %noreg, 3188, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%calculatedCombinedCRC43] GR32:%vreg92 GR64:%vreg93
2720B		MOV32mr %vreg93<kill>, 1, %noreg, 3188, %noreg, %vreg92<kill>; mem:ST4[%calculatedCombinedCRC43] GR64:%vreg93 GR32:%vreg92
2736B		%vreg87<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg87
2752B		MOV32mi %vreg87<kill>, 1, %noreg, 8, %noreg, 14; mem:ST4[%state44] GR64:%vreg87
2768B		JMP_1 <BB#25>
	    Successors according to CFG: BB#25
> %RAX<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 3188, %noreg; mem:LD4[%calculatedCombinedCRC]
> %EAX<def,tied1> = SHL32ri %EAX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> %RCX<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> %ECX<def> = MOV32rm %RCX<kill>, 1, %noreg, 3188, %noreg; mem:LD4[%calculatedCombinedCRC40]
> %ECX<def,tied1> = SHR32ri %ECX<kill,tied0>, 31, %EFLAGS<imp-def,dead>
> %EAX<def,tied1> = OR32rr %EAX<kill,tied0>, %ECX<kill>, %EFLAGS<imp-def,dead>
> %RCX<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> MOV32mr %RCX<kill>, 1, %noreg, 3188, %noreg, %EAX<kill>; mem:ST4[%calculatedCombinedCRC41]
> %RAX<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 3184, %noreg; mem:LD4[%calculatedBlockCRC42]
> %RCX<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> %EAX<def,tied1> = XOR32rm %EAX<kill,tied0>, %RCX, 1, %noreg, 3188, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%calculatedCombinedCRC43]
> MOV32mr %RCX<kill>, 1, %noreg, 3188, %noreg, %EAX<kill>; mem:ST4[%calculatedCombinedCRC43]
> %RAX<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> MOV32mi %RAX<kill>, 1, %noreg, 8, %noreg, 14; mem:ST4[%state44]
> JMP_1 <BB#25>
2784B	BB#24: derived from LLVM BB %if.else.45
	    Predecessors according to CFG: BB#15 BB#16
2800B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
2816B		JMP_1 <BB#37>
	    Successors according to CFG: BB#37
> MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
> JMP_1 <BB#37>
2832B	BB#25: derived from LLVM BB %if.end.46
	    Predecessors according to CFG: BB#23
2848B		JMP_1 <BB#26>
	    Successors according to CFG: BB#26
> JMP_1 <BB#26>
2864B	BB#26: derived from LLVM BB %if.end.47
	    Predecessors according to CFG: BB#9 BB#25
2880B		%vreg115<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg115
2896B		CMP32mi8 %vreg115<kill>, 1, %noreg, 8, %noreg, 10, %EFLAGS<imp-def>; mem:LD4[%state48] GR64:%vreg115
2912B		JL_1 <BB#36>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#36 BB#27
> %RAX<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> CMP32mi8 %RAX<kill>, 1, %noreg, 8, %noreg, 10, %EFLAGS<imp-def>; mem:LD4[%state48]
> JL_1 <BB#36>, %EFLAGS<imp-use,kill>
2928B	BB#27: derived from LLVM BB %if.then.50
	    Predecessors according to CFG: BB#26
2944B		%vreg120<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg120
2960B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2976B		%RDI<def> = COPY %vreg120<kill>; GR64:%vreg120
2992B		CALL64pcrel32 <ga:@BZ2_decompress>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
3008B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3024B		%vreg119<def> = COPY %EAX; GR32:%vreg119
3040B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3056B		STACKMAP 5, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
3072B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3088B		MOV32mr <fi#4>, 1, %noreg, 0, %noreg, %vreg119<kill>; mem:ST4[%r] GR32:%vreg119
3104B		CMP32mi8 <fi#4>, 1, %noreg, 0, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%r]
3120B		JNE_1 <BB#33>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#33 BB#28
> %RDI<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@BZ2_decompress>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def> = COPY %EAX
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 5, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV32mr <fi#4>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%r]
> CMP32mi8 <fi#4>, 1, %noreg, 0, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%r]
> JNE_1 <BB#33>, %EFLAGS<imp-use,kill>
3136B	BB#28: derived from LLVM BB %if.then.53
	    Predecessors according to CFG: BB#27
3152B		%vreg128<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg128
3168B		CMP32mi8 %vreg128<kill>, 1, %noreg, 52, %noreg, 3, %EFLAGS<imp-def>; mem:LD4[%verbosity54] GR64:%vreg128
3184B		JL_1 <BB#30>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#30 BB#29
> %RAX<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> CMP32mi8 %RAX<kill>, 1, %noreg, 52, %noreg, 3, %EFLAGS<imp-def>; mem:LD4[%verbosity54]
> JL_1 <BB#30>, %EFLAGS<imp-use,kill>
3200B	BB#29: derived from LLVM BB %if.then.56
	    Predecessors according to CFG: BB#28
3216B		%vreg130<def> = MOV64ri <ga:@bzlib__str_4______combi>; GR64:%vreg130
3232B		%vreg140<def> = MOV64rm %noreg, 1, %noreg, <ga:@stderr>, %noreg; mem:LD8[@stderr] GR64:%vreg140
3248B		%vreg139<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg139
3264B		%vreg138<def> = MOV32rm %vreg139<kill>, 1, %noreg, 3180, %noreg; mem:LD4[%storedCombinedCRC] GR32:%vreg138 GR64:%vreg139
3280B		%vreg136<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg136
3296B		%vreg135<def> = MOV32rm %vreg136<kill>, 1, %noreg, 3188, %noreg; mem:LD4[%calculatedCombinedCRC57] GR32:%vreg135 GR64:%vreg136
3312B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3392B		%AL<def> = MOV8ri 0
3396B		%RDI<def> = COPY %vreg140<kill>; GR64:%vreg140
3400B		%RSI<def> = COPY %vreg130<kill>; GR64:%vreg130
3408B		%EDX<def> = COPY %vreg138<kill>; GR32:%vreg138
3416B		%ECX<def> = COPY %vreg135<kill>; GR32:%vreg135
3424B		CALL64pcrel32 <ga:@fprintf>, <regmask>, %RSP<imp-use>, %AL<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %EDX<imp-use>, %ECX<imp-use>, %EAX<imp-def>
3432B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3440B		%vreg133<def,dead> = COPY %EAX; GR32:%vreg133
3456B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3472B		STACKMAP 6, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
3488B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#30
> %RSI<def> = MOV64ri <ga:@bzlib__str_4______combi>
> %RDI<def> = MOV64rm %noreg, 1, %noreg, <ga:@stderr>, %noreg; mem:LD8[@stderr]
> %RAX<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> %EDX<def> = MOV32rm %RAX<kill>, 1, %noreg, 3180, %noreg; mem:LD4[%storedCombinedCRC]
> %RAX<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> %ECX<def> = MOV32rm %RAX<kill>, 1, %noreg, 3188, %noreg; mem:LD4[%calculatedCombinedCRC57]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %AL<def> = MOV8ri 0
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> %EDX<def> = COPY %EDX<kill>
Deleting identity copy.
> %ECX<def> = COPY %ECX<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@fprintf>, <regmask>, %RSP<imp-use>, %AL<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %EDX<imp-use>, %ECX<imp-use>, %EAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def,dead> = COPY %EAX
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 6, 0, 0, <fi#4>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack4](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3504B	BB#30: derived from LLVM BB %if.end.59
	    Predecessors according to CFG: BB#28 BB#29
3520B		%vreg147<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg147
3536B		%vreg146<def> = MOV32rm %vreg147<kill>, 1, %noreg, 3188, %noreg; mem:LD4[%calculatedCombinedCRC60] GR32:%vreg146 GR64:%vreg147
3552B		%vreg144<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg144
3568B		CMP32rm %vreg146<kill>, %vreg144<kill>, 1, %noreg, 3180, %noreg, %EFLAGS<imp-def>; mem:LD4[%storedCombinedCRC61] GR32:%vreg146 GR64:%vreg144
3584B		JE_1 <BB#32>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#32 BB#31
> %RAX<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 3188, %noreg; mem:LD4[%calculatedCombinedCRC60]
> %RCX<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> CMP32rm %EAX<kill>, %RCX<kill>, 1, %noreg, 3180, %noreg, %EFLAGS<imp-def>; mem:LD4[%storedCombinedCRC61]
> JE_1 <BB#32>, %EFLAGS<imp-use,kill>
3600B	BB#31: derived from LLVM BB %if.then.63
	    Predecessors according to CFG: BB#30
3616B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -4; mem:ST4[%retval]
3632B		JMP_1 <BB#37>
	    Successors according to CFG: BB#37
> MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -4; mem:ST4[%retval]
> JMP_1 <BB#37>
3648B	BB#32: derived from LLVM BB %if.end.64
	    Predecessors according to CFG: BB#30
3664B		%vreg149<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%r] GR32:%vreg149
3680B		MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %vreg149<kill>; mem:ST4[%retval] GR32:%vreg149
3696B		JMP_1 <BB#37>
	    Successors according to CFG: BB#37
> %EAX<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%r]
> MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%retval]
> JMP_1 <BB#37>
3712B	BB#33: derived from LLVM BB %if.end.65
	    Predecessors according to CFG: BB#27
3728B		%vreg123<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg123
3744B		CMP32mi8 %vreg123<kill>, 1, %noreg, 8, %noreg, 2, %EFLAGS<imp-def>; mem:LD4[%state66] GR64:%vreg123
3760B		JE_1 <BB#35>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#35 BB#34
> %RAX<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> CMP32mi8 %RAX<kill>, 1, %noreg, 8, %noreg, 2, %EFLAGS<imp-def>; mem:LD4[%state66]
> JE_1 <BB#35>, %EFLAGS<imp-use,kill>
3776B	BB#34: derived from LLVM BB %if.then.68
	    Predecessors according to CFG: BB#33
3792B		%vreg125<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%r] GR32:%vreg125
3808B		MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %vreg125<kill>; mem:ST4[%retval] GR32:%vreg125
3824B		JMP_1 <BB#37>
	    Successors according to CFG: BB#37
> %EAX<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%r]
> MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%retval]
> JMP_1 <BB#37>
3840B	BB#35: derived from LLVM BB %if.end.69
	    Predecessors according to CFG: BB#33
3856B		JMP_1 <BB#36>
	    Successors according to CFG: BB#36
> JMP_1 <BB#36>
3872B	BB#36: derived from LLVM BB %if.end.70
	    Predecessors according to CFG: BB#26 BB#35
3888B		JMP_1 <BB#7>
	    Successors according to CFG: BB#7
> JMP_1 <BB#7>
3904B	BB#37: derived from LLVM BB %return
	    Predecessors according to CFG: BB#24 BB#34 BB#32 BB#31 BB#22 BB#14 BB#8 BB#5 BB#3 BB#1
3920B		%vreg153<def> = MOV64ri <ga:@BZ2_bzDecompress>; GR64:%vreg153
3952B		%vreg154<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg154
3968B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3984B		%RDI<def> = COPY %vreg153<kill>; GR64:%vreg153
4000B		%RSI<def> = COPY %vreg154<kill>; GR64:%vreg154
4016B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
4032B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4048B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4064B		STACKMAP 7, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
4080B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4096B		%vreg151<def> = MOV32rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD4[%retval] GR32:%vreg151
4112B		%EAX<def> = COPY %vreg151<kill>; GR32:%vreg151
4128B		RETQ %EAX<imp-use>
> %RDI<def> = MOV64ri <ga:@BZ2_bzDecompress>
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 7, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def> = MOV32rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD4[%retval]
> %EAX<def> = COPY %EAX<kill>
Deleting identity copy.
> RETQ %EAX<imp-use>
Computing live-in reg-units in ABI blocks.
0B	BB#0 DIL#0
Created 1 new intervals.
********** INTERVALS **********
DIL [0B,16r:0)[112r,144r:12)[2160r,2192r:5)[4016r,4048r:4)[5872r,5904r:3)[7696r,7728r:2)[9264r,9296r:1)[12528r,12560r:10)[13760r,13792r:9)[14992r,15024r:8)[16192r,16224r:6)[17136r,17168r:7)[18000r,18032r:11)  0@0B-phi 1@9264r 2@7696r 3@5872r 4@4016r 5@2160r 6@16192r 7@17136r 8@14992r 9@13760r 10@12528r 11@18000r 12@112r
%vreg0 [16r,32r:0)  0@16r
%vreg1 [32r,224r:0)  0@32r
%vreg4 [240r,256r:0)  0@240r
%vreg5 [48r,64r:0)  0@48r
%vreg6 [64r,112r:0)  0@64r
%vreg7 [80r,128r:0)  0@80r
%vreg11 [10752r,10768r:0)  0@10752r
%vreg12 [10736r,10752r:0)  0@10736r
%vreg15 [10864r,10880r:0)  0@10864r
%vreg19 [11728r,11744r:0)  0@11728r
%vreg20 [11712r,11728r:0)  0@11712r
%vreg24 [11664r,11680r:0)[11680r,11696r:1)  0@11664r 1@11680r
%vreg25 [11648r,11664r:0)  0@11648r
%vreg27 [11632r,11696r:0)  0@11632r
%vreg28 [11616r,11632r:0)  0@11616r
%vreg32 [11568r,11584r:0)[11584r,11600r:1)  0@11568r 1@11584r
%vreg33 [11552r,11568r:0)  0@11552r
%vreg35 [11536r,11600r:0)  0@11536r
%vreg36 [11520r,11536r:0)  0@11520r
%vreg40 [11472r,11488r:0)[11488r,11504r:1)  0@11472r 1@11488r
%vreg41 [11456r,11472r:0)  0@11456r
%vreg43 [11440r,11504r:0)  0@11440r
%vreg44 [11424r,11440r:0)  0@11424r
%vreg48 [11376r,11392r:0)[11392r,11408r:1)  0@11376r 1@11392r
%vreg49 [11360r,11376r:0)  0@11360r
%vreg50 [11344r,11408r:0)  0@11344r
%vreg53 [11312r,11328r:0)  0@11312r
%vreg56 [11280r,11296r:0)[11296r,11328r:1)  0@11280r 1@11296r
%vreg59 [11248r,11264r:0)  0@11248r
%vreg60 [11264r,11296r:0)  0@11264r
%vreg63 [11216r,11232r:0)[11232r,11248r:1)  0@11216r 1@11232r
%vreg65 [11200r,11232r:0)  0@11200r
%vreg67 [11184r,11200r:0)  0@11184r
%vreg69 [11152r,11168r:0)[11168r,11216r:1)  0@11152r 1@11168r
%vreg71 [11136r,11152r:0)  0@11136r
%vreg72 [11120r,11136r:0)  0@11120r
%vreg74 [11088r,11104r:0)[11104r,11280r:1)  0@11088r 1@11104r
%vreg76 [11072r,11088r:0)  0@11072r
%vreg77 [11056r,11072r:0)  0@11056r
%vreg81 [11024r,11040r:0)  0@11024r
%vreg83 [11008r,11024r:0)  0@11008r
%vreg84 [10992r,11008r:0)  0@10992r
%vreg86 [10976r,11040r:0)  0@10976r
%vreg87 [10960r,10976r:0)  0@10960r
%vreg91 [11840r,11856r:0)[11856r,11872r:1)  0@11840r 1@11856r
%vreg92 [11824r,11840r:0)  0@11824r
%vreg94 [11808r,11872r:0)  0@11808r
%vreg95 [11792r,11808r:0)  0@11792r
%vreg99 [12000r,12016r:0)[12016r,12032r:1)  0@12000r 1@12016r
%vreg101 [11984r,12000r:0)  0@11984r
%vreg102 [11968r,11984r:0)  0@11968r
%vreg104 [11952r,12032r:0)  0@11952r
%vreg105 [11936r,11952r:0)  0@11936r
%vreg109 [12192r,12208r:0)[12208r,12224r:1)  0@12192r 1@12208r
%vreg111 [12176r,12192r:0)  0@12176r
%vreg112 [12160r,12176r:0)  0@12160r
%vreg114 [12144r,12224r:0)  0@12144r
%vreg115 [12128r,12144r:0)  0@12128r
%vreg119 [13360r,13376r:0)[13376r,13392r:1)  0@13360r 1@13376r
%vreg121 [13344r,13360r:0)  0@13344r
%vreg122 [13328r,13344r:0)  0@13328r
%vreg124 [13312r,13392r:0)  0@13312r
%vreg125 [13296r,13312r:0)  0@13296r
%vreg129 [13248r,13264r:0)[13264r,13280r:1)  0@13248r 1@13264r
%vreg130 [13232r,13248r:0)  0@13232r
%vreg131 [13216r,13280r:0)  0@13216r
%vreg134 [13184r,13200r:0)  0@13184r
%vreg137 [13152r,13168r:0)[13168r,13200r:1)  0@13152r 1@13168r
%vreg139 [13120r,13136r:0)[13136r,13168r:1)  0@13120r 1@13136r
%vreg141 [13088r,13104r:0)[13104r,13120r:1)  0@13088r 1@13104r
%vreg144 [13056r,13072r:0)[13072r,13088r:1)  0@13056r 1@13072r
%vreg146 [12992r,13008r:0)[13008r,13024r:1)  0@12992r 1@13008r
%vreg148 [12960r,12976r:0)[12976r,12992r:1)  0@12960r 1@12976r
%vreg150 [12944r,12960r:0)  0@12944r
%vreg151 [12928r,12944r:0)  0@12928r
%vreg153 [12912r,13056r:0)  0@12912r
%vreg157 [12896r,12912r:0)  0@12896r
%vreg158 [12880r,12896r:0)  0@12880r
%vreg160 [12848r,12864r:0)  0@12848r
%vreg161 [12864r,12912r:0)  0@12864r
%vreg163 [12816r,12832r:0)[12832r,12848r:1)  0@12816r 1@12832r
%vreg165 [12800r,12816r:0)  0@12800r
%vreg166 [12784r,12800r:0)  0@12784r
%vreg168 [12768r,13152r:0)  0@12768r
%vreg172 [12752r,12768r:0)  0@12752r
%vreg173 [12736r,12752r:0)  0@12736r
%vreg175 [12704r,12720r:0)  0@12704r
%vreg176 [12720r,12768r:0)  0@12720r
%vreg178 [12688r,12704r:0)  0@12688r
%vreg181 [12656r,12672r:0)  0@12656r
%vreg184 [12592r,12656r:0)  0@12592r
%vreg187 [12480r,12496r:0)[12496r,12544r:1)  0@12480r 1@12496r
%vreg188 [12464r,12480r:0)  0@12464r
%vreg190 [12448r,12528r:0)  0@12448r
%vreg191 [12432r,12448r:0)  0@12432r
%vreg194 [12400r,12416r:0)  0@12400r
%vreg196 [12384r,12416r:0)  0@12384r
%vreg198 [12368r,12384r:0)  0@12368r
%vreg199 [12352r,12368r:0)  0@12352r
%vreg201 [12320r,12336r:0)  0@12320r
%vreg205 [13488r,13504r:0)  0@13488r
%vreg207 [13472r,13504r:0)  0@13472r
%vreg211 [14592r,14608r:0)[14608r,14624r:1)  0@14592r 1@14608r
%vreg213 [14576r,14592r:0)  0@14576r
%vreg214 [14560r,14576r:0)  0@14560r
%vreg216 [14544r,14624r:0)  0@14544r
%vreg217 [14528r,14544r:0)  0@14528r
%vreg221 [14480r,14496r:0)[14496r,14512r:1)  0@14480r 1@14496r
%vreg222 [14464r,14480r:0)  0@14464r
%vreg223 [14448r,14512r:0)  0@14448r
%vreg226 [14416r,14432r:0)  0@14416r
%vreg229 [14384r,14400r:0)[14400r,14432r:1)  0@14384r 1@14400r
%vreg231 [14352r,14368r:0)[14368r,14400r:1)  0@14352r 1@14368r
%vreg233 [14320r,14336r:0)[14336r,14352r:1)  0@14320r 1@14336r
%vreg236 [14288r,14304r:0)[14304r,14320r:1)  0@14288r 1@14304r
%vreg238 [14224r,14240r:0)[14240r,14256r:1)  0@14224r 1@14240r
%vreg240 [14192r,14208r:0)[14208r,14224r:1)  0@14192r 1@14208r
%vreg242 [14176r,14192r:0)  0@14176r
%vreg243 [14160r,14176r:0)  0@14160r
%vreg245 [14144r,14288r:0)  0@14144r
%vreg249 [14128r,14144r:0)  0@14128r
%vreg250 [14112r,14128r:0)  0@14112r
%vreg252 [14080r,14096r:0)  0@14080r
%vreg253 [14096r,14144r:0)  0@14096r
%vreg255 [14048r,14064r:0)[14064r,14080r:1)  0@14048r 1@14064r
%vreg257 [14032r,14048r:0)  0@14032r
%vreg258 [14016r,14032r:0)  0@14016r
%vreg260 [14000r,14384r:0)  0@14000r
%vreg264 [13984r,14000r:0)  0@13984r
%vreg265 [13968r,13984r:0)  0@13968r
%vreg267 [13936r,13952r:0)  0@13936r
%vreg268 [13952r,14000r:0)  0@13952r
%vreg270 [13920r,13936r:0)  0@13920r
%vreg273 [13888r,13904r:0)  0@13888r
%vreg276 [13824r,13888r:0)  0@13824r
%vreg279 [13712r,13728r:0)[13728r,13776r:1)  0@13712r 1@13728r
%vreg280 [13696r,13712r:0)  0@13696r
%vreg282 [13680r,13760r:0)  0@13680r
%vreg283 [13664r,13680r:0)  0@13664r
%vreg285 [13632r,13648r:0)  0@13632r
%vreg289 [14720r,14736r:0)  0@14720r
%vreg291 [14704r,14736r:0)  0@14704r
%vreg295 [15824r,15840r:0)[15840r,15856r:1)  0@15824r 1@15840r
%vreg297 [15808r,15824r:0)  0@15808r
%vreg298 [15792r,15808r:0)  0@15792r
%vreg300 [15776r,15856r:0)  0@15776r
%vreg301 [15760r,15776r:0)  0@15760r
%vreg305 [15712r,15728r:0)[15728r,15744r:1)  0@15712r 1@15728r
%vreg306 [15696r,15712r:0)  0@15696r
%vreg307 [15680r,15744r:0)  0@15680r
%vreg310 [15648r,15664r:0)  0@15648r
%vreg313 [15616r,15632r:0)[15632r,15664r:1)  0@15616r 1@15632r
%vreg315 [15584r,15600r:0)[15600r,15632r:1)  0@15584r 1@15600r
%vreg317 [15552r,15568r:0)[15568r,15584r:1)  0@15552r 1@15568r
%vreg320 [15520r,15536r:0)[15536r,15552r:1)  0@15520r 1@15536r
%vreg322 [15456r,15472r:0)[15472r,15488r:1)  0@15456r 1@15472r
%vreg324 [15424r,15440r:0)[15440r,15456r:1)  0@15424r 1@15440r
%vreg326 [15408r,15424r:0)  0@15408r
%vreg327 [15392r,15408r:0)  0@15392r
%vreg329 [15376r,15520r:0)  0@15376r
%vreg333 [15360r,15376r:0)  0@15360r
%vreg334 [15344r,15360r:0)  0@15344r
%vreg336 [15312r,15328r:0)  0@15312r
%vreg337 [15328r,15376r:0)  0@15328r
%vreg339 [15280r,15296r:0)[15296r,15312r:1)  0@15280r 1@15296r
%vreg341 [15264r,15280r:0)  0@15264r
%vreg342 [15248r,15264r:0)  0@15248r
%vreg344 [15232r,15616r:0)  0@15232r
%vreg348 [15216r,15232r:0)  0@15216r
%vreg349 [15200r,15216r:0)  0@15200r
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%vreg999 [7200r,7216r:0)  0@7200r
%vreg1000 [7184r,7248r:0)  0@7184r
%vreg1003 [7152r,7168r:0)  0@7152r
%vreg1006 [7120r,7136r:0)[7136r,7152r:1)  0@7120r 1@7136r
%vreg1008 [7104r,7120r:0)  0@7104r
%vreg1010 [6928r,7072r:0)  0@6928r
%vreg1011 [6944r,7088r:0)  0@6944r
%vreg1012 [7072r,7088r:0)[7088r,7136r:1)  0@7072r 1@7088r
%vreg1014 [7040r,7056r:0)  0@7040r
%vreg1018 [6992r,7008r:0)[7008r,7024r:1)  0@6992r 1@7008r
%vreg1019 [6976r,6992r:0)  0@6976r
%vreg1020 [6960r,7024r:0)  0@6960r
%vreg1024 [7456r,7472r:0)  0@7456r
%vreg1026 [7440r,7472r:0)  0@7440r
%vreg1029 [8384r,8400r:0)  0@8384r
%vreg1032 [8352r,8368r:0)  0@8352r
%vreg1035 [8320r,8336r:0)[8336r,8368r:1)  0@8320r 1@8336r
%vreg1037 [8288r,8304r:0)[8304r,8336r:1)  0@8288r 1@8304r
%vreg1039 [8256r,8272r:0)[8272r,8288r:1)  0@8256r 1@8272r
%vreg1042 [8224r,8240r:0)[8240r,8256r:1)  0@8224r 1@8240r
%vreg1044 [8160r,8176r:0)[8176r,8192r:1)  0@8160r 1@8176r
%vreg1046 [8128r,8144r:0)[8144r,8160r:1)  0@8128r 1@8144r
%vreg1048 [8112r,8128r:0)  0@8112r
%vreg1049 [8096r,8112r:0)  0@8096r
%vreg1051 [8080r,8224r:0)  0@8080r
%vreg1055 [8064r,8080r:0)  0@8064r
%vreg1056 [8048r,8064r:0)  0@8048r
%vreg1058 [8016r,8032r:0)  0@8016r
%vreg1059 [8032r,8080r:0)  0@8032r
%vreg1061 [7984r,8000r:0)[8000r,8016r:1)  0@7984r 1@8000r
%vreg1063 [7968r,7984r:0)  0@7968r
%vreg1064 [7952r,7968r:0)  0@7952r
%vreg1066 [7936r,8320r:0)  0@7936r
%vreg1070 [7920r,7936r:0)  0@7920r
%vreg1071 [7904r,7920r:0)  0@7904r
%vreg1073 [7872r,7888r:0)  0@7872r
%vreg1074 [7888r,7936r:0)  0@7888r
%vreg1076 [7856r,7872r:0)  0@7856r
%vreg1079 [7824r,7840r:0)  0@7824r
%vreg1082 [7760r,7824r:0)  0@7760r
%vreg1085 [7648r,7664r:0)[7664r,7712r:1)  0@7648r 1@7664r
%vreg1086 [7632r,7648r:0)  0@7632r
%vreg1088 [7616r,7696r:0)  0@7616r
%vreg1089 [7600r,7616r:0)  0@7600r
%vreg1092 [8608r,8624r:0)  0@8608r
%vreg1096 [8560r,8576r:0)[8576r,8592r:1)  0@8560r 1@8576r
%vreg1097 [8544r,8560r:0)  0@8544r
%vreg1098 [8528r,8592r:0)  0@8528r
%vreg1101 [8496r,8512r:0)  0@8496r
%vreg1103 [8480r,8512r:0)  0@8480r
%vreg1105 [8464r,8480r:0)  0@8464r
%vreg1107 [8448r,8464r:0)  0@8448r
%vreg1109 [8672r,8688r:0)  0@8672r
%vreg1112 [9952r,9968r:0)  0@9952r
%vreg1115 [9920r,9936r:0)  0@9920r
%vreg1118 [9888r,9904r:0)[9904r,9936r:1)  0@9888r 1@9904r
%vreg1120 [9856r,9872r:0)[9872r,9904r:1)  0@9856r 1@9872r
%vreg1122 [9824r,9840r:0)[9840r,9856r:1)  0@9824r 1@9840r
%vreg1125 [9792r,9808r:0)[9808r,9824r:1)  0@9792r 1@9808r
%vreg1127 [9728r,9744r:0)[9744r,9760r:1)  0@9728r 1@9744r
%vreg1129 [9696r,9712r:0)[9712r,9728r:1)  0@9696r 1@9712r
%vreg1131 [9680r,9696r:0)  0@9680r
%vreg1132 [9664r,9680r:0)  0@9664r
%vreg1134 [9648r,9792r:0)  0@9648r
%vreg1138 [9632r,9648r:0)  0@9632r
%vreg1139 [9616r,9632r:0)  0@9616r
%vreg1141 [9584r,9600r:0)  0@9584r
%vreg1142 [9600r,9648r:0)  0@9600r
%vreg1144 [9552r,9568r:0)[9568r,9584r:1)  0@9552r 1@9568r
%vreg1146 [9536r,9552r:0)  0@9536r
%vreg1147 [9520r,9536r:0)  0@9520r
%vreg1149 [9504r,9888r:0)  0@9504r
%vreg1153 [9488r,9504r:0)  0@9488r
%vreg1154 [9472r,9488r:0)  0@9472r
%vreg1156 [9440r,9456r:0)  0@9440r
%vreg1157 [9456r,9504r:0)  0@9456r
%vreg1159 [9424r,9440r:0)  0@9424r
%vreg1162 [9392r,9408r:0)  0@9392r
%vreg1165 [9328r,9408r:0)  0@9328r
%vreg1168 [9216r,9232r:0)[9232r,9280r:1)  0@9216r 1@9232r
%vreg1169 [9200r,9216r:0)  0@9200r
%vreg1171 [9184r,9264r:0)  0@9184r
%vreg1172 [9168r,9184r:0)  0@9168r
%vreg1175 [9136r,9152r:0)  0@9136r
%vreg1177 [9104r,9120r:0)[9120r,9152r:1)  0@9104r 1@9120r
%vreg1179 [9088r,9104r:0)  0@9088r
%vreg1183 [9040r,9056r:0)[9056r,9072r:1)  0@9040r 1@9056r
%vreg1184 [9024r,9040r:0)  0@9024r
%vreg1185 [9008r,9072r:0)  0@9008r
%vreg1188 [8976r,8992r:0)  0@8976r
%vreg1191 [8944r,8960r:0)[8960r,8976r:1)  0@8944r 1@8960r
%vreg1193 [8928r,8944r:0)  0@8928r
%vreg1195 [8752r,8896r:0)  0@8752r
%vreg1196 [8768r,8912r:0)  0@8768r
%vreg1197 [8896r,8912r:0)[8912r,8960r:1)  0@8896r 1@8912r
%vreg1199 [8864r,8880r:0)  0@8864r
%vreg1203 [8816r,8832r:0)[8832r,8848r:1)  0@8816r 1@8832r
%vreg1204 [8800r,8816r:0)  0@8800r
%vreg1205 [8784r,8848r:0)  0@8784r
%vreg1208 [10176r,10192r:0)  0@10176r
%vreg1212 [10128r,10144r:0)[10144r,10160r:1)  0@10128r 1@10144r
%vreg1213 [10112r,10128r:0)  0@10112r
%vreg1214 [10096r,10160r:0)  0@10096r
%vreg1217 [10064r,10080r:0)  0@10064r
%vreg1219 [10048r,10080r:0)  0@10048r
%vreg1221 [10032r,10048r:0)  0@10032r
%vreg1223 [10016r,10032r:0)  0@10016r
%vreg1225 [10240r,10256r:0)  0@10240r
%vreg1229 [10592r,10608r:0)[10608r,10624r:1)  0@10592r 1@10608r
%vreg1230 [10576r,10592r:0)  0@10576r
%vreg1231 [10560r,10624r:0)  0@10560r
%vreg1236 [10512r,10528r:0)[10528r,10544r:1)  0@10512r 1@10528r
%vreg1237 [10496r,10544r:0)  0@10496r
%vreg1239 [10320r,10464r:0)  0@10320r
%vreg1240 [10336r,10480r:0)  0@10336r
%vreg1241 [10464r,10480r:0)[10480r,10512r:1)  0@10464r 1@10480r
%vreg1243 [10432r,10448r:0)  0@10432r
%vreg1247 [10384r,10400r:0)[10400r,10416r:1)  0@10384r 1@10400r
%vreg1248 [10368r,10384r:0)  0@10368r
%vreg1249 [10352r,10416r:0)  0@10352r
%vreg1252 [7536r,7552r:0)  0@7536r
%vreg1254 [7520r,7552r:0)  0@7520r
%vreg1257 [5680r,5696r:0)  0@5680r
%vreg1259 [5664r,5696r:0)  0@5664r
%vreg1262 [3824r,3840r:0)  0@3824r
%vreg1264 [3808r,3840r:0)  0@3808r
%vreg1266 [18112r,18128r:0)  0@18112r
%vreg1267 [17936r,17952r:0)  0@17936r
%vreg1268 [17952r,18000r:0)  0@17952r
%vreg1269 [17968r,18016r:0)  0@17968r
RegMasks: 144r 2192r 4048r 5904r 7728r 9296r 12560r 13792r 15024r 16224r 17168r 18032r
********** MACHINEINSTRS **********
# Machine code for function unRLE_obuf_to_output_SMALL: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=1, align=1, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=1, align=1, at location [SP+8]
Function Live Ins: %RDI in %vreg0

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI
16B		%vreg0<def> = COPY %RDI; GR64:%vreg0
32B		%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
48B		%vreg5<def> = MOV64ri <ga:@unRLE_obuf_to_output_SMALL>; GR64:%vreg5
64B		%vreg6<def> = COPY %vreg5; GR64:%vreg6,%vreg5
80B		%vreg7<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg7
96B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
112B		%RDI<def> = COPY %vreg6; GR64:%vreg6
128B		%RSI<def> = COPY %vreg7; GR64:%vreg7
144B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
160B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
192B		STACKMAP 0, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, %vreg1, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1] GR64:%vreg1
208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%s.addr] GR64:%vreg1
240B		%vreg4<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg4
256B		CMP8mi %vreg4, 1, %noreg, 20, %noreg, 0, %EFLAGS<imp-def>; mem:LD1[%blockRandomised] GR64:%vreg4
272B		JE_1 <BB#47>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#47 BB#1

288B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
304B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2

320B	BB#2: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#1 BB#46 BB#37 BB#35 BB#29 BB#27 BB#21 BB#19
336B		JMP_1 <BB#3>
	    Successors according to CFG: BB#3

352B	BB#3: derived from LLVM BB %while.body.2
	    Predecessors according to CFG: BB#2 BB#9
368B		%vreg534<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg534
384B		%vreg533<def> = MOV64rm %vreg534, 1, %noreg, 0, %noreg; mem:LD8[%strm] GR64:%vreg533,%vreg534
400B		CMP32mi8 %vreg533, 1, %noreg, 32, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_out] GR64:%vreg533
416B		JNE_1 <BB#5>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#5 BB#4

432B	BB#4: derived from LLVM BB %if.then.3
	    Predecessors according to CFG: BB#3
448B		MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST1[%retval]
464B		JMP_1 <BB#73>
	    Successors according to CFG: BB#73

480B	BB#5: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#3
496B		%vreg537<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg537
512B		CMP32mi8 %vreg537, 1, %noreg, 16, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%state_out_len] GR64:%vreg537
528B		JNE_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#6

544B	BB#6: derived from LLVM BB %if.then.5
	    Predecessors according to CFG: BB#5
560B		JMP_1 <BB#10>
	    Successors according to CFG: BB#10

576B	BB#7: derived from LLVM BB %if.end.6
	    Predecessors according to CFG: BB#5
592B		%vreg609<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg609
608B		%vreg608<def> = MOV8rm %vreg609, 1, %noreg, 12, %noreg; mem:LD1[%state_out_ch] GR8:%vreg608 GR64:%vreg609
624B		%vreg606<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg606
640B		%vreg605<def> = MOV64rm %vreg606, 1, %noreg, 0, %noreg; mem:LD8[%strm7] GR64:%vreg605,%vreg606
656B		%vreg603<def> = MOV64rm %vreg605, 1, %noreg, 24, %noreg; mem:LD8[%next_out] GR64:%vreg603,%vreg605
672B		MOV8mr %vreg603, 1, %noreg, 0, %noreg, %vreg608; mem:ST1[%11] GR64:%vreg603 GR8:%vreg608
688B		%vreg599<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg599
704B		%vreg598<def> = MOV32rm %vreg599, 1, %noreg, 3184, %noreg; mem:LD4[%calculatedBlockCRC] GR32:%vreg598 GR64:%vreg599
720B		%vreg596<def> = COPY %vreg598; GR32:%vreg596,%vreg598
736B		%vreg596<def,tied1> = SHL32ri %vreg596<tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg596
752B		%vreg594<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg594
768B		%vreg593<def> = MOV32rm %vreg594, 1, %noreg, 3184, %noreg; mem:LD4[%calculatedBlockCRC8] GR32:%vreg593 GR64:%vreg594
784B		%vreg591<def> = COPY %vreg593; GR32:%vreg591,%vreg593
800B		%vreg591<def,tied1> = SHR32ri %vreg591<tied0>, 24, %EFLAGS<imp-def,dead>; GR32:%vreg591
816B		%vreg589<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg589
832B		%vreg587<def> = MOVZX32rm8 %vreg589, 1, %noreg, 12, %noreg; mem:LD1[%state_out_ch9] GR32:%vreg587 GR64:%vreg589
848B		%vreg585<def> = COPY %vreg591; GR32:%vreg585,%vreg591
864B		%vreg585<def,tied1> = XOR32rr %vreg585<tied0>, %vreg587, %EFLAGS<imp-def,dead>; GR32:%vreg585,%vreg587
880B		%vreg581<def> = MOV32rr %vreg585; GR32:%vreg581,%vreg585
896B		%vreg582<def> = SUBREG_TO_REG 0, %vreg581, 4; GR64_NOSP:%vreg582 GR32:%vreg581
912B		%vreg578<def> = COPY %vreg596; GR32:%vreg578,%vreg596
928B		%vreg578<def,tied1> = XOR32rm %vreg578<tied0>, %noreg, 4, %vreg582, <ga:@BZ2_crc32Table>, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%arrayidx] GR32:%vreg578 GR64_NOSP:%vreg582
944B		%vreg575<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg575
960B		MOV32mr %vreg575, 1, %noreg, 3184, %noreg, %vreg578; mem:ST4[%calculatedBlockCRC11] GR64:%vreg575 GR32:%vreg578
976B		%vreg572<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg572
992B		%vreg571<def> = MOV32rm %vreg572, 1, %noreg, 16, %noreg; mem:LD4[%state_out_len12] GR32:%vreg571 GR64:%vreg572
1008B		%vreg570<def> = COPY %vreg571; GR32:%vreg570,%vreg571
1024B		%vreg570<def,tied1> = ADD32ri8 %vreg570<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg570
1040B		MOV32mr %vreg572, 1, %noreg, 16, %noreg, %vreg570; mem:ST4[%state_out_len12] GR64:%vreg572 GR32:%vreg570
1056B		%vreg566<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg566
1072B		%vreg565<def> = MOV64rm %vreg566, 1, %noreg, 0, %noreg; mem:LD8[%strm13] GR64:%vreg565,%vreg566
1088B		%vreg563<def> = MOV64rm %vreg565, 1, %noreg, 24, %noreg; mem:LD8[%next_out14] GR64:%vreg563,%vreg565
1104B		%vreg562<def> = COPY %vreg563; GR64:%vreg562,%vreg563
1120B		%vreg562<def,tied1> = ADD64ri8 %vreg562<tied0>, 1, %EFLAGS<imp-def,dead>; GR64:%vreg562
1136B		MOV64mr %vreg565, 1, %noreg, 24, %noreg, %vreg562; mem:ST8[%next_out14] GR64:%vreg565,%vreg562
1152B		%vreg558<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg558
1168B		%vreg557<def> = MOV64rm %vreg558, 1, %noreg, 0, %noreg; mem:LD8[%strm15] GR64:%vreg557,%vreg558
1184B		%vreg555<def> = MOV32rm %vreg557, 1, %noreg, 32, %noreg; mem:LD4[%avail_out16] GR32:%vreg555 GR64:%vreg557
1200B		%vreg554<def> = COPY %vreg555; GR32:%vreg554,%vreg555
1216B		%vreg554<def,tied1> = ADD32ri8 %vreg554<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg554
1232B		MOV32mr %vreg557, 1, %noreg, 32, %noreg, %vreg554; mem:ST4[%avail_out16] GR64:%vreg557 GR32:%vreg554
1248B		%vreg550<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg550
1264B		%vreg549<def> = MOV64rm %vreg550, 1, %noreg, 0, %noreg; mem:LD8[%strm18] GR64:%vreg549,%vreg550
1280B		%vreg547<def> = MOV32rm %vreg549, 1, %noreg, 36, %noreg; mem:LD4[%total_out_lo32] GR32:%vreg547 GR64:%vreg549
1296B		%vreg546<def> = COPY %vreg547; GR32:%vreg546,%vreg547
1312B		%vreg546<def,tied1> = ADD32ri8 %vreg546<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg546
1328B		MOV32mr %vreg549, 1, %noreg, 36, %noreg, %vreg546; mem:ST4[%total_out_lo32] GR64:%vreg549 GR32:%vreg546
1344B		%vreg542<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg542
1360B		%vreg541<def> = MOV64rm %vreg542, 1, %noreg, 0, %noreg; mem:LD8[%strm19] GR64:%vreg541,%vreg542
1376B		CMP32mi8 %vreg541, 1, %noreg, 36, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%total_out_lo3220] GR64:%vreg541
1392B		JNE_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#8

1408B	BB#8: derived from LLVM BB %if.then.23
	    Predecessors according to CFG: BB#7
1424B		%vreg617<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg617
1440B		%vreg616<def> = MOV64rm %vreg617, 1, %noreg, 0, %noreg; mem:LD8[%strm24] GR64:%vreg616,%vreg617
1456B		%vreg614<def> = MOV32rm %vreg616, 1, %noreg, 40, %noreg; mem:LD4[%total_out_hi32] GR32:%vreg614 GR64:%vreg616
1472B		%vreg613<def> = COPY %vreg614; GR32:%vreg613,%vreg614
1488B		%vreg613<def,tied1> = ADD32ri8 %vreg613<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg613
1504B		MOV32mr %vreg616, 1, %noreg, 40, %noreg, %vreg613; mem:ST4[%total_out_hi32] GR64:%vreg616 GR32:%vreg613
	    Successors according to CFG: BB#9

1520B	BB#9: derived from LLVM BB %if.end.26
	    Predecessors according to CFG: BB#7 BB#8
1536B		JMP_1 <BB#3>
	    Successors according to CFG: BB#3

1552B	BB#10: derived from LLVM BB %while.end
	    Predecessors according to CFG: BB#6
1568B		%vreg627<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg627
1584B		%vreg626<def> = MOV32rm %vreg627, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used] GR32:%vreg626 GR64:%vreg627
1600B		%vreg624<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg624
1616B		%vreg623<def> = MOV32rm %vreg624, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock] GR32:%vreg623 GR64:%vreg624
1632B		%vreg621<def> = COPY %vreg623; GR32:%vreg621,%vreg623
1648B		%vreg621<def,tied1> = ADD32ri8 %vreg621<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg621
1664B		CMP32rr %vreg626, %vreg621, %EFLAGS<imp-def>; GR32:%vreg626,%vreg621
1680B		JNE_1 <BB#12>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#12 BB#11

1696B	BB#11: derived from LLVM BB %if.then.29
	    Predecessors according to CFG: BB#10
1712B		MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST1[%retval]
1728B		JMP_1 <BB#73>
	    Successors according to CFG: BB#73

1744B	BB#12: derived from LLVM BB %if.end.30
	    Predecessors according to CFG: BB#10
1760B		%vreg637<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg637
1776B		%vreg636<def> = MOV32rm %vreg637, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used31] GR32:%vreg636 GR64:%vreg637
1792B		%vreg634<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg634
1808B		%vreg633<def> = MOV32rm %vreg634, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock32] GR32:%vreg633 GR64:%vreg634
1824B		%vreg631<def> = COPY %vreg633; GR32:%vreg631,%vreg633
1840B		%vreg631<def,tied1> = ADD32ri8 %vreg631<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg631
1856B		CMP32rr %vreg636, %vreg631, %EFLAGS<imp-def>; GR32:%vreg636,%vreg631
1872B		JLE_1 <BB#14>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#14 BB#13

1888B	BB#13: derived from LLVM BB %if.then.36
	    Predecessors according to CFG: BB#12
1904B		MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 1; mem:ST1[%retval]
1920B		JMP_1 <BB#73>
	    Successors according to CFG: BB#73

1936B	BB#14: derived from LLVM BB %if.end.37
	    Predecessors according to CFG: BB#12
1952B		%vreg710<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg710
1968B		MOV32mi %vreg710, 1, %noreg, 16, %noreg, 1; mem:ST4[%state_out_len38] GR64:%vreg710
1984B		%vreg708<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg708
2000B		%vreg707<def> = MOV32rm %vreg708, 1, %noreg, 64, %noreg; mem:LD4[%k0] GR32:%vreg707 GR64:%vreg708
2016B		%vreg705<def> = COPY %vreg707:sub_8bit; GR8:%vreg705 GR32:%vreg707
2032B		%vreg703<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg703
2048B		MOV8mr %vreg703, 1, %noreg, 12, %noreg, %vreg705; mem:ST1[%state_out_ch40] GR64:%vreg703 GR8:%vreg705
2064B		%vreg700<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg700
2080B		%vreg699<def> = MOV32rm %vreg700, 1, %noreg, 60, %noreg; mem:LD4[%tPos] GR32:%vreg699 GR64:%vreg700
2096B		%vreg697<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg697
2112B		%vreg696<def> = COPY %vreg697; GR64:%vreg696,%vreg697
2128B		%vreg696<def,tied1> = ADD64ri32 %vreg696<tied0>, 1096, %EFLAGS<imp-def,dead>; GR64:%vreg696
2144B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2160B		%EDI<def> = COPY %vreg699; GR32:%vreg699
2176B		%RSI<def> = COPY %vreg696; GR64:%vreg696
2192B		CALL64pcrel32 <ga:@BZ2_indexIntoF>, <regmask>, %RSP<imp-use>, %EDI<imp-use>, %RSI<imp-use,kill>, %EAX<imp-def>
2208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2224B		%vreg693<def> = COPY %EAX<kill>; GR32:%vreg693
2240B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2256B		STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
2272B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2288B		%vreg690<def> = COPY %vreg693:sub_8bit; GR8:%vreg690 GR32:%vreg693
2304B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg690; mem:ST1[%k1] GR8:%vreg690
2320B		%vreg687<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg687
2336B		%vreg684<def> = MOV32rm %vreg687, 1, %noreg, 60, %noreg; mem:LD4[%tPos42] GR32:%vreg684 GR64:%vreg687
2352B		%vreg685<def> = SUBREG_TO_REG 0, %vreg684, 4; GR64_NOSP:%vreg685 GR32:%vreg684
2368B		%vreg682<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg682
2384B		%vreg681<def> = MOV64rm %vreg682, 1, %noreg, 3160, %noreg; mem:LD8[%ll16] GR64:%vreg681,%vreg682
2400B		%vreg677<def> = MOVZX32rm16 %vreg681, 2, %vreg685, 0, %noreg; mem:LD2[%arrayidx44] GR32:%vreg677 GR64:%vreg681 GR64_NOSP:%vreg685
2416B		%vreg675<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg675
2432B		%vreg674<def> = MOV32rm %vreg675, 1, %noreg, 60, %noreg; mem:LD4[%tPos46] GR32:%vreg674 GR64:%vreg675
2448B		%vreg672<def> = COPY %vreg674; GR32:%vreg672,%vreg674
2464B		%vreg672<def,tied1> = SHR32ri %vreg672<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg672
2480B		%vreg669<def> = MOV32rr %vreg672; GR32:%vreg669,%vreg672
2496B		%vreg670<def> = SUBREG_TO_REG 0, %vreg669, 4; GR64_NOSP:%vreg670 GR32:%vreg669
2512B		%vreg667<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg667
2528B		%vreg666<def> = MOV64rm %vreg667, 1, %noreg, 3168, %noreg; mem:LD8[%ll4] GR64:%vreg666,%vreg667
2544B		%vreg662<def> = MOVZX32rm8 %vreg666, 1, %vreg670, 0, %noreg; mem:LD1[%arrayidx49] GR32:%vreg662 GR64:%vreg666 GR64_NOSP:%vreg670
2560B		%vreg660<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg660
2576B		%vreg659<def> = MOV32rm %vreg660, 1, %noreg, 60, %noreg; mem:LD4[%tPos51] GR32:%vreg659 GR64:%vreg660
2592B		%vreg657<def> = COPY %vreg659; GR32:%vreg657,%vreg659
2608B		%vreg657<def,tied1> = SHL32ri %vreg657<tied0>, 2, %EFLAGS<imp-def,dead>; GR32:%vreg657
2624B		%vreg655<def> = COPY %vreg657; GR32:%vreg655,%vreg657
2640B		%vreg655<def,tied1> = AND32ri8 %vreg655<tied0>, 4, %EFLAGS<imp-def,dead>; GR32:%vreg655
2656B		%ECX<def> = COPY %vreg655; GR32:%vreg655
2672B		%CL<def> = KILL %ECX<kill>
2688B		%vreg653<def> = COPY %vreg662; GR32:%vreg653,%vreg662
2704B		%vreg653<def,tied1> = SHR32rCL %vreg653<tied0>, %EFLAGS<imp-def,dead>, %CL<imp-use,kill>; GR32:%vreg653
2720B		%vreg650<def> = COPY %vreg653; GR32:%vreg650,%vreg653
2736B		%vreg650<def,tied1> = AND32ri8 %vreg650<tied0>, 15, %EFLAGS<imp-def,dead>; GR32:%vreg650
2752B		%vreg648<def> = COPY %vreg650; GR32:%vreg648,%vreg650
2768B		%vreg648<def,tied1> = SHL32ri %vreg648<tied0>, 16, %EFLAGS<imp-def,dead>; GR32:%vreg648
2784B		%vreg646<def> = COPY %vreg677; GR32:%vreg646,%vreg677
2800B		%vreg646<def,tied1> = OR32rr %vreg646<tied0>, %vreg648, %EFLAGS<imp-def,dead>; GR32:%vreg646,%vreg648
2816B		%vreg643<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg643
2832B		MOV32mr %vreg643, 1, %noreg, 60, %noreg, %vreg646; mem:ST4[%tPos56] GR64:%vreg643 GR32:%vreg646
2848B		%vreg640<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg640
2864B		CMP32mi8 %vreg640, 1, %noreg, 24, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%rNToGo] GR64:%vreg640
2880B		JNE_1 <BB#18>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#18 BB#15

2896B	BB#15: derived from LLVM BB %if.then.59
	    Predecessors according to CFG: BB#14
2912B		%vreg728<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg728
2928B		%vreg726<def> = MOVSX64rm32 %vreg728, 1, %noreg, 28, %noreg; mem:LD4[%rTPos] GR64_NOSP:%vreg726 GR64:%vreg728
2944B		%vreg724<def> = MOV32rm %noreg, 4, %vreg726, <ga:@BZ2_rNums>, %noreg; mem:LD4[%arrayidx61] GR32:%vreg724 GR64_NOSP:%vreg726
2960B		%vreg722<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg722
2976B		MOV32mr %vreg722, 1, %noreg, 24, %noreg, %vreg724; mem:ST4[%rNToGo62] GR64:%vreg722 GR32:%vreg724
2992B		%vreg719<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg719
3008B		%vreg718<def> = MOV32rm %vreg719, 1, %noreg, 28, %noreg; mem:LD4[%rTPos63] GR32:%vreg718 GR64:%vreg719
3024B		%vreg717<def> = COPY %vreg718; GR32:%vreg717,%vreg718
3040B		%vreg717<def,tied1> = ADD32ri8 %vreg717<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg717
3056B		MOV32mr %vreg719, 1, %noreg, 28, %noreg, %vreg717; mem:ST4[%rTPos63] GR64:%vreg719 GR32:%vreg717
3072B		%vreg713<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg713
3088B		CMP32mi %vreg713, 1, %noreg, 28, %noreg, 512, %EFLAGS<imp-def>; mem:LD4[%rTPos65] GR64:%vreg713
3104B		JNE_1 <BB#17>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#17 BB#16

3120B	BB#16: derived from LLVM BB %if.then.68
	    Predecessors according to CFG: BB#15
3136B		%vreg730<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg730
3152B		MOV32mi %vreg730, 1, %noreg, 28, %noreg, 0; mem:ST4[%rTPos69] GR64:%vreg730
	    Successors according to CFG: BB#17

3168B	BB#17: derived from LLVM BB %if.end.70
	    Predecessors according to CFG: BB#15 BB#16
3184B		JMP_1 <BB#18>
	    Successors according to CFG: BB#18

3200B	BB#18: derived from LLVM BB %if.end.71
	    Predecessors according to CFG: BB#14 BB#17
3216B		%vreg756<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg756
3232B		%vreg757<def> = MOV32ri 1; GR32:%vreg757
3248B		%vreg766<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg766
3264B		%vreg765<def> = MOV32rm %vreg766, 1, %noreg, 24, %noreg; mem:LD4[%rNToGo72] GR32:%vreg765 GR64:%vreg766
3280B		%vreg764<def> = COPY %vreg765; GR32:%vreg764,%vreg765
3296B		%vreg764<def,tied1> = ADD32ri8 %vreg764<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg764
3312B		MOV32mr %vreg766, 1, %noreg, 24, %noreg, %vreg764; mem:ST4[%rNToGo72] GR64:%vreg766 GR32:%vreg764
3328B		%vreg760<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg760
3344B		CMP32mi8 %vreg760, 1, %noreg, 24, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%rNToGo74] GR64:%vreg760
3360B		%vreg758<def> = COPY %vreg756; GR32:%vreg758,%vreg756
3376B		%vreg758<def,tied1> = CMOVE32rr %vreg758<tied0>, %vreg757, %EFLAGS<imp-use,kill>; GR32:%vreg758,%vreg757
3392B		%vreg754<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg754
3408B		%vreg752<def> = COPY %vreg754; GR32:%vreg752,%vreg754
3424B		%vreg752<def,tied1> = XOR32rr %vreg752<tied0>, %vreg758, %EFLAGS<imp-def,dead>; GR32:%vreg752,%vreg758
3440B		%vreg749<def> = COPY %vreg752:sub_8bit; GR8:%vreg749 GR32:%vreg752
3456B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg749; mem:ST1[%k1] GR8:%vreg749
3472B		%vreg746<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg746
3488B		%vreg745<def> = MOV32rm %vreg746, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used80] GR32:%vreg745 GR64:%vreg746
3504B		%vreg744<def> = COPY %vreg745; GR32:%vreg744,%vreg745
3520B		%vreg744<def,tied1> = ADD32ri8 %vreg744<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg744
3536B		MOV32mr %vreg746, 1, %noreg, 1092, %noreg, %vreg744; mem:ST4[%nblock_used80] GR64:%vreg746 GR32:%vreg744
3552B		%vreg740<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg740
3568B		%vreg739<def> = MOV32rm %vreg740, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used82] GR32:%vreg739 GR64:%vreg740
3584B		%vreg737<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg737
3600B		%vreg736<def> = MOV32rm %vreg737, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock83] GR32:%vreg736 GR64:%vreg737
3616B		%vreg734<def> = COPY %vreg736; GR32:%vreg734,%vreg736
3632B		%vreg734<def,tied1> = ADD32ri8 %vreg734<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg734
3648B		CMP32rr %vreg739, %vreg734, %EFLAGS<imp-def>; GR32:%vreg739,%vreg734
3664B		JNE_1 <BB#20>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#20 BB#19

3680B	BB#19: derived from LLVM BB %if.then.87
	    Predecessors according to CFG: BB#18
3696B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2

3712B	BB#20: derived from LLVM BB %if.end.88
	    Predecessors according to CFG: BB#18
3728B		%vreg772<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg772
3744B		%vreg770<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg770
3760B		CMP32rm %vreg772, %vreg770, 1, %noreg, 64, %noreg, %EFLAGS<imp-def>; mem:LD4[%k090] GR32:%vreg772 GR64:%vreg770
3776B		JE_1 <BB#22>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#22 BB#21

3792B	BB#21: derived from LLVM BB %if.then.93
	    Predecessors according to CFG: BB#20
3808B		%vreg1264<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg1264
3824B		%vreg1262<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1262
3840B		MOV32mr %vreg1262, 1, %noreg, 64, %noreg, %vreg1264; mem:ST4[%k095] GR64:%vreg1262 GR32:%vreg1264
3856B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2

3872B	BB#22: derived from LLVM BB %if.end.96
	    Predecessors according to CFG: BB#20
3888B		%vreg837<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg837
3904B		MOV32mi %vreg837, 1, %noreg, 16, %noreg, 2; mem:ST4[%state_out_len97] GR64:%vreg837
3920B		%vreg835<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg835
3936B		%vreg834<def> = MOV32rm %vreg835, 1, %noreg, 60, %noreg; mem:LD4[%tPos98] GR32:%vreg834 GR64:%vreg835
3952B		%vreg832<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg832
3968B		%vreg831<def> = COPY %vreg832; GR64:%vreg831,%vreg832
3984B		%vreg831<def,tied1> = ADD64ri32 %vreg831<tied0>, 1096, %EFLAGS<imp-def,dead>; GR64:%vreg831
4000B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4016B		%EDI<def> = COPY %vreg834; GR32:%vreg834
4032B		%RSI<def> = COPY %vreg831; GR64:%vreg831
4048B		CALL64pcrel32 <ga:@BZ2_indexIntoF>, <regmask>, %RSP<imp-use>, %EDI<imp-use>, %RSI<imp-use,kill>, %EAX<imp-def>
4064B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4080B		%vreg828<def> = COPY %EAX<kill>; GR32:%vreg828
4096B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4112B		STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
4128B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4144B		%vreg825<def> = COPY %vreg828:sub_8bit; GR8:%vreg825 GR32:%vreg828
4160B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg825; mem:ST1[%k1] GR8:%vreg825
4176B		%vreg822<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg822
4192B		%vreg819<def> = MOV32rm %vreg822, 1, %noreg, 60, %noreg; mem:LD4[%tPos103] GR32:%vreg819 GR64:%vreg822
4208B		%vreg820<def> = SUBREG_TO_REG 0, %vreg819, 4; GR64_NOSP:%vreg820 GR32:%vreg819
4224B		%vreg817<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg817
4240B		%vreg816<def> = MOV64rm %vreg817, 1, %noreg, 3160, %noreg; mem:LD8[%ll16105] GR64:%vreg816,%vreg817
4256B		%vreg812<def> = MOVZX32rm16 %vreg816, 2, %vreg820, 0, %noreg; mem:LD2[%arrayidx106] GR32:%vreg812 GR64:%vreg816 GR64_NOSP:%vreg820
4272B		%vreg810<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg810
4288B		%vreg809<def> = MOV32rm %vreg810, 1, %noreg, 60, %noreg; mem:LD4[%tPos108] GR32:%vreg809 GR64:%vreg810
4304B		%vreg807<def> = COPY %vreg809; GR32:%vreg807,%vreg809
4320B		%vreg807<def,tied1> = SHR32ri %vreg807<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg807
4336B		%vreg804<def> = MOV32rr %vreg807; GR32:%vreg804,%vreg807
4352B		%vreg805<def> = SUBREG_TO_REG 0, %vreg804, 4; GR64_NOSP:%vreg805 GR32:%vreg804
4368B		%vreg802<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg802
4384B		%vreg801<def> = MOV64rm %vreg802, 1, %noreg, 3168, %noreg; mem:LD8[%ll4111] GR64:%vreg801,%vreg802
4400B		%vreg797<def> = MOVZX32rm8 %vreg801, 1, %vreg805, 0, %noreg; mem:LD1[%arrayidx112] GR32:%vreg797 GR64:%vreg801 GR64_NOSP:%vreg805
4416B		%vreg795<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg795
4432B		%vreg794<def> = MOV32rm %vreg795, 1, %noreg, 60, %noreg; mem:LD4[%tPos114] GR32:%vreg794 GR64:%vreg795
4448B		%vreg792<def> = COPY %vreg794; GR32:%vreg792,%vreg794
4464B		%vreg792<def,tied1> = SHL32ri %vreg792<tied0>, 2, %EFLAGS<imp-def,dead>; GR32:%vreg792
4480B		%vreg790<def> = COPY %vreg792; GR32:%vreg790,%vreg792
4496B		%vreg790<def,tied1> = AND32ri8 %vreg790<tied0>, 4, %EFLAGS<imp-def,dead>; GR32:%vreg790
4512B		%ECX<def> = COPY %vreg790; GR32:%vreg790
4528B		%CL<def> = KILL %ECX<kill>
4544B		%vreg788<def> = COPY %vreg797; GR32:%vreg788,%vreg797
4560B		%vreg788<def,tied1> = SHR32rCL %vreg788<tied0>, %EFLAGS<imp-def,dead>, %CL<imp-use,kill>; GR32:%vreg788
4576B		%vreg785<def> = COPY %vreg788; GR32:%vreg785,%vreg788
4592B		%vreg785<def,tied1> = AND32ri8 %vreg785<tied0>, 15, %EFLAGS<imp-def,dead>; GR32:%vreg785
4608B		%vreg783<def> = COPY %vreg785; GR32:%vreg783,%vreg785
4624B		%vreg783<def,tied1> = SHL32ri %vreg783<tied0>, 16, %EFLAGS<imp-def,dead>; GR32:%vreg783
4640B		%vreg781<def> = COPY %vreg812; GR32:%vreg781,%vreg812
4656B		%vreg781<def,tied1> = OR32rr %vreg781<tied0>, %vreg783, %EFLAGS<imp-def,dead>; GR32:%vreg781,%vreg783
4672B		%vreg778<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg778
4688B		MOV32mr %vreg778, 1, %noreg, 60, %noreg, %vreg781; mem:ST4[%tPos121] GR64:%vreg778 GR32:%vreg781
4704B		%vreg775<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg775
4720B		CMP32mi8 %vreg775, 1, %noreg, 24, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%rNToGo122] GR64:%vreg775
4736B		JNE_1 <BB#26>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#26 BB#23

4752B	BB#23: derived from LLVM BB %if.then.125
	    Predecessors according to CFG: BB#22
4768B		%vreg855<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg855
4784B		%vreg853<def> = MOVSX64rm32 %vreg855, 1, %noreg, 28, %noreg; mem:LD4[%rTPos126] GR64_NOSP:%vreg853 GR64:%vreg855
4800B		%vreg851<def> = MOV32rm %noreg, 4, %vreg853, <ga:@BZ2_rNums>, %noreg; mem:LD4[%arrayidx128] GR32:%vreg851 GR64_NOSP:%vreg853
4816B		%vreg849<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg849
4832B		MOV32mr %vreg849, 1, %noreg, 24, %noreg, %vreg851; mem:ST4[%rNToGo129] GR64:%vreg849 GR32:%vreg851
4848B		%vreg846<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg846
4864B		%vreg845<def> = MOV32rm %vreg846, 1, %noreg, 28, %noreg; mem:LD4[%rTPos130] GR32:%vreg845 GR64:%vreg846
4880B		%vreg844<def> = COPY %vreg845; GR32:%vreg844,%vreg845
4896B		%vreg844<def,tied1> = ADD32ri8 %vreg844<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg844
4912B		MOV32mr %vreg846, 1, %noreg, 28, %noreg, %vreg844; mem:ST4[%rTPos130] GR64:%vreg846 GR32:%vreg844
4928B		%vreg840<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg840
4944B		CMP32mi %vreg840, 1, %noreg, 28, %noreg, 512, %EFLAGS<imp-def>; mem:LD4[%rTPos132] GR64:%vreg840
4960B		JNE_1 <BB#25>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#25 BB#24

4976B	BB#24: derived from LLVM BB %if.then.135
	    Predecessors according to CFG: BB#23
4992B		%vreg857<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg857
5008B		MOV32mi %vreg857, 1, %noreg, 28, %noreg, 0; mem:ST4[%rTPos136] GR64:%vreg857
	    Successors according to CFG: BB#25

5024B	BB#25: derived from LLVM BB %if.end.137
	    Predecessors according to CFG: BB#23 BB#24
5040B		JMP_1 <BB#26>
	    Successors according to CFG: BB#26

5056B	BB#26: derived from LLVM BB %if.end.138
	    Predecessors according to CFG: BB#22 BB#25
5072B		%vreg883<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg883
5088B		%vreg884<def> = MOV32ri 1; GR32:%vreg884
5104B		%vreg893<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg893
5120B		%vreg892<def> = MOV32rm %vreg893, 1, %noreg, 24, %noreg; mem:LD4[%rNToGo139] GR32:%vreg892 GR64:%vreg893
5136B		%vreg891<def> = COPY %vreg892; GR32:%vreg891,%vreg892
5152B		%vreg891<def,tied1> = ADD32ri8 %vreg891<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg891
5168B		MOV32mr %vreg893, 1, %noreg, 24, %noreg, %vreg891; mem:ST4[%rNToGo139] GR64:%vreg893 GR32:%vreg891
5184B		%vreg887<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg887
5200B		CMP32mi8 %vreg887, 1, %noreg, 24, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%rNToGo141] GR64:%vreg887
5216B		%vreg885<def> = COPY %vreg883; GR32:%vreg885,%vreg883
5232B		%vreg885<def,tied1> = CMOVE32rr %vreg885<tied0>, %vreg884, %EFLAGS<imp-use,kill>; GR32:%vreg885,%vreg884
5248B		%vreg881<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg881
5264B		%vreg879<def> = COPY %vreg881; GR32:%vreg879,%vreg881
5280B		%vreg879<def,tied1> = XOR32rr %vreg879<tied0>, %vreg885, %EFLAGS<imp-def,dead>; GR32:%vreg879,%vreg885
5296B		%vreg876<def> = COPY %vreg879:sub_8bit; GR8:%vreg876 GR32:%vreg879
5312B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg876; mem:ST1[%k1] GR8:%vreg876
5328B		%vreg873<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg873
5344B		%vreg872<def> = MOV32rm %vreg873, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used148] GR32:%vreg872 GR64:%vreg873
5360B		%vreg871<def> = COPY %vreg872; GR32:%vreg871,%vreg872
5376B		%vreg871<def,tied1> = ADD32ri8 %vreg871<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg871
5392B		MOV32mr %vreg873, 1, %noreg, 1092, %noreg, %vreg871; mem:ST4[%nblock_used148] GR64:%vreg873 GR32:%vreg871
5408B		%vreg867<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg867
5424B		%vreg866<def> = MOV32rm %vreg867, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used150] GR32:%vreg866 GR64:%vreg867
5440B		%vreg864<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg864
5456B		%vreg863<def> = MOV32rm %vreg864, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock151] GR32:%vreg863 GR64:%vreg864
5472B		%vreg861<def> = COPY %vreg863; GR32:%vreg861,%vreg863
5488B		%vreg861<def,tied1> = ADD32ri8 %vreg861<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg861
5504B		CMP32rr %vreg866, %vreg861, %EFLAGS<imp-def>; GR32:%vreg866,%vreg861
5520B		JNE_1 <BB#28>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#28 BB#27

5536B	BB#27: derived from LLVM BB %if.then.155
	    Predecessors according to CFG: BB#26
5552B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2

5568B	BB#28: derived from LLVM BB %if.end.156
	    Predecessors according to CFG: BB#26
5584B		%vreg899<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg899
5600B		%vreg897<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg897
5616B		CMP32rm %vreg899, %vreg897, 1, %noreg, 64, %noreg, %EFLAGS<imp-def>; mem:LD4[%k0158] GR32:%vreg899 GR64:%vreg897
5632B		JE_1 <BB#30>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#30 BB#29

5648B	BB#29: derived from LLVM BB %if.then.161
	    Predecessors according to CFG: BB#28
5664B		%vreg1259<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg1259
5680B		%vreg1257<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1257
5696B		MOV32mr %vreg1257, 1, %noreg, 64, %noreg, %vreg1259; mem:ST4[%k0163] GR64:%vreg1257 GR32:%vreg1259
5712B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2

5728B	BB#30: derived from LLVM BB %if.end.164
	    Predecessors according to CFG: BB#28
5744B		%vreg964<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg964
5760B		MOV32mi %vreg964, 1, %noreg, 16, %noreg, 3; mem:ST4[%state_out_len165] GR64:%vreg964
5776B		%vreg962<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg962
5792B		%vreg961<def> = MOV32rm %vreg962, 1, %noreg, 60, %noreg; mem:LD4[%tPos166] GR32:%vreg961 GR64:%vreg962
5808B		%vreg959<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg959
5824B		%vreg958<def> = COPY %vreg959; GR64:%vreg958,%vreg959
5840B		%vreg958<def,tied1> = ADD64ri32 %vreg958<tied0>, 1096, %EFLAGS<imp-def,dead>; GR64:%vreg958
5856B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5872B		%EDI<def> = COPY %vreg961; GR32:%vreg961
5888B		%RSI<def> = COPY %vreg958; GR64:%vreg958
5904B		CALL64pcrel32 <ga:@BZ2_indexIntoF>, <regmask>, %RSP<imp-use>, %EDI<imp-use>, %RSI<imp-use,kill>, %EAX<imp-def>
5920B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5936B		%vreg955<def> = COPY %EAX<kill>; GR32:%vreg955
5952B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5968B		STACKMAP 3, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
5984B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
6000B		%vreg952<def> = COPY %vreg955:sub_8bit; GR8:%vreg952 GR32:%vreg955
6016B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg952; mem:ST1[%k1] GR8:%vreg952
6032B		%vreg949<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg949
6048B		%vreg946<def> = MOV32rm %vreg949, 1, %noreg, 60, %noreg; mem:LD4[%tPos171] GR32:%vreg946 GR64:%vreg949
6064B		%vreg947<def> = SUBREG_TO_REG 0, %vreg946, 4; GR64_NOSP:%vreg947 GR32:%vreg946
6080B		%vreg944<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg944
6096B		%vreg943<def> = MOV64rm %vreg944, 1, %noreg, 3160, %noreg; mem:LD8[%ll16173] GR64:%vreg943,%vreg944
6112B		%vreg939<def> = MOVZX32rm16 %vreg943, 2, %vreg947, 0, %noreg; mem:LD2[%arrayidx174] GR32:%vreg939 GR64:%vreg943 GR64_NOSP:%vreg947
6128B		%vreg937<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg937
6144B		%vreg936<def> = MOV32rm %vreg937, 1, %noreg, 60, %noreg; mem:LD4[%tPos176] GR32:%vreg936 GR64:%vreg937
6160B		%vreg934<def> = COPY %vreg936; GR32:%vreg934,%vreg936
6176B		%vreg934<def,tied1> = SHR32ri %vreg934<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg934
6192B		%vreg931<def> = MOV32rr %vreg934; GR32:%vreg931,%vreg934
6208B		%vreg932<def> = SUBREG_TO_REG 0, %vreg931, 4; GR64_NOSP:%vreg932 GR32:%vreg931
6224B		%vreg929<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg929
6240B		%vreg928<def> = MOV64rm %vreg929, 1, %noreg, 3168, %noreg; mem:LD8[%ll4179] GR64:%vreg928,%vreg929
6256B		%vreg924<def> = MOVZX32rm8 %vreg928, 1, %vreg932, 0, %noreg; mem:LD1[%arrayidx180] GR32:%vreg924 GR64:%vreg928 GR64_NOSP:%vreg932
6272B		%vreg922<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg922
6288B		%vreg921<def> = MOV32rm %vreg922, 1, %noreg, 60, %noreg; mem:LD4[%tPos182] GR32:%vreg921 GR64:%vreg922
6304B		%vreg919<def> = COPY %vreg921; GR32:%vreg919,%vreg921
6320B		%vreg919<def,tied1> = SHL32ri %vreg919<tied0>, 2, %EFLAGS<imp-def,dead>; GR32:%vreg919
6336B		%vreg917<def> = COPY %vreg919; GR32:%vreg917,%vreg919
6352B		%vreg917<def,tied1> = AND32ri8 %vreg917<tied0>, 4, %EFLAGS<imp-def,dead>; GR32:%vreg917
6368B		%ECX<def> = COPY %vreg917; GR32:%vreg917
6384B		%CL<def> = KILL %ECX<kill>
6400B		%vreg915<def> = COPY %vreg924; GR32:%vreg915,%vreg924
6416B		%vreg915<def,tied1> = SHR32rCL %vreg915<tied0>, %EFLAGS<imp-def,dead>, %CL<imp-use,kill>; GR32:%vreg915
6432B		%vreg912<def> = COPY %vreg915; GR32:%vreg912,%vreg915
6448B		%vreg912<def,tied1> = AND32ri8 %vreg912<tied0>, 15, %EFLAGS<imp-def,dead>; GR32:%vreg912
6464B		%vreg910<def> = COPY %vreg912; GR32:%vreg910,%vreg912
6480B		%vreg910<def,tied1> = SHL32ri %vreg910<tied0>, 16, %EFLAGS<imp-def,dead>; GR32:%vreg910
6496B		%vreg908<def> = COPY %vreg939; GR32:%vreg908,%vreg939
6512B		%vreg908<def,tied1> = OR32rr %vreg908<tied0>, %vreg910, %EFLAGS<imp-def,dead>; GR32:%vreg908,%vreg910
6528B		%vreg905<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg905
6544B		MOV32mr %vreg905, 1, %noreg, 60, %noreg, %vreg908; mem:ST4[%tPos189] GR64:%vreg905 GR32:%vreg908
6560B		%vreg902<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg902
6576B		CMP32mi8 %vreg902, 1, %noreg, 24, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%rNToGo190] GR64:%vreg902
6592B		JNE_1 <BB#34>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#34 BB#31

6608B	BB#31: derived from LLVM BB %if.then.193
	    Predecessors according to CFG: BB#30
6624B		%vreg982<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg982
6640B		%vreg980<def> = MOVSX64rm32 %vreg982, 1, %noreg, 28, %noreg; mem:LD4[%rTPos194] GR64_NOSP:%vreg980 GR64:%vreg982
6656B		%vreg978<def> = MOV32rm %noreg, 4, %vreg980, <ga:@BZ2_rNums>, %noreg; mem:LD4[%arrayidx196] GR32:%vreg978 GR64_NOSP:%vreg980
6672B		%vreg976<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg976
6688B		MOV32mr %vreg976, 1, %noreg, 24, %noreg, %vreg978; mem:ST4[%rNToGo197] GR64:%vreg976 GR32:%vreg978
6704B		%vreg973<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg973
6720B		%vreg972<def> = MOV32rm %vreg973, 1, %noreg, 28, %noreg; mem:LD4[%rTPos198] GR32:%vreg972 GR64:%vreg973
6736B		%vreg971<def> = COPY %vreg972; GR32:%vreg971,%vreg972
6752B		%vreg971<def,tied1> = ADD32ri8 %vreg971<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg971
6768B		MOV32mr %vreg973, 1, %noreg, 28, %noreg, %vreg971; mem:ST4[%rTPos198] GR64:%vreg973 GR32:%vreg971
6784B		%vreg967<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg967
6800B		CMP32mi %vreg967, 1, %noreg, 28, %noreg, 512, %EFLAGS<imp-def>; mem:LD4[%rTPos200] GR64:%vreg967
6816B		JNE_1 <BB#33>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#33 BB#32

6832B	BB#32: derived from LLVM BB %if.then.203
	    Predecessors according to CFG: BB#31
6848B		%vreg984<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg984
6864B		MOV32mi %vreg984, 1, %noreg, 28, %noreg, 0; mem:ST4[%rTPos204] GR64:%vreg984
	    Successors according to CFG: BB#33

6880B	BB#33: derived from LLVM BB %if.end.205
	    Predecessors according to CFG: BB#31 BB#32
6896B		JMP_1 <BB#34>
	    Successors according to CFG: BB#34

6912B	BB#34: derived from LLVM BB %if.end.206
	    Predecessors according to CFG: BB#30 BB#33
6928B		%vreg1010<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg1010
6944B		%vreg1011<def> = MOV32ri 1; GR32:%vreg1011
6960B		%vreg1020<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1020
6976B		%vreg1019<def> = MOV32rm %vreg1020, 1, %noreg, 24, %noreg; mem:LD4[%rNToGo207] GR32:%vreg1019 GR64:%vreg1020
6992B		%vreg1018<def> = COPY %vreg1019; GR32:%vreg1018,%vreg1019
7008B		%vreg1018<def,tied1> = ADD32ri8 %vreg1018<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg1018
7024B		MOV32mr %vreg1020, 1, %noreg, 24, %noreg, %vreg1018; mem:ST4[%rNToGo207] GR64:%vreg1020 GR32:%vreg1018
7040B		%vreg1014<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1014
7056B		CMP32mi8 %vreg1014, 1, %noreg, 24, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%rNToGo209] GR64:%vreg1014
7072B		%vreg1012<def> = COPY %vreg1010; GR32:%vreg1012,%vreg1010
7088B		%vreg1012<def,tied1> = CMOVE32rr %vreg1012<tied0>, %vreg1011, %EFLAGS<imp-use,kill>; GR32:%vreg1012,%vreg1011
7104B		%vreg1008<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg1008
7120B		%vreg1006<def> = COPY %vreg1008; GR32:%vreg1006,%vreg1008
7136B		%vreg1006<def,tied1> = XOR32rr %vreg1006<tied0>, %vreg1012, %EFLAGS<imp-def,dead>; GR32:%vreg1006,%vreg1012
7152B		%vreg1003<def> = COPY %vreg1006:sub_8bit; GR8:%vreg1003 GR32:%vreg1006
7168B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg1003; mem:ST1[%k1] GR8:%vreg1003
7184B		%vreg1000<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1000
7200B		%vreg999<def> = MOV32rm %vreg1000, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used216] GR32:%vreg999 GR64:%vreg1000
7216B		%vreg998<def> = COPY %vreg999; GR32:%vreg998,%vreg999
7232B		%vreg998<def,tied1> = ADD32ri8 %vreg998<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg998
7248B		MOV32mr %vreg1000, 1, %noreg, 1092, %noreg, %vreg998; mem:ST4[%nblock_used216] GR64:%vreg1000 GR32:%vreg998
7264B		%vreg994<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg994
7280B		%vreg993<def> = MOV32rm %vreg994, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used218] GR32:%vreg993 GR64:%vreg994
7296B		%vreg991<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg991
7312B		%vreg990<def> = MOV32rm %vreg991, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock219] GR32:%vreg990 GR64:%vreg991
7328B		%vreg988<def> = COPY %vreg990; GR32:%vreg988,%vreg990
7344B		%vreg988<def,tied1> = ADD32ri8 %vreg988<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg988
7360B		CMP32rr %vreg993, %vreg988, %EFLAGS<imp-def>; GR32:%vreg993,%vreg988
7376B		JNE_1 <BB#36>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#36 BB#35

7392B	BB#35: derived from LLVM BB %if.then.223
	    Predecessors according to CFG: BB#34
7408B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2

7424B	BB#36: derived from LLVM BB %if.end.224
	    Predecessors according to CFG: BB#34
7440B		%vreg1026<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg1026
7456B		%vreg1024<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1024
7472B		CMP32rm %vreg1026, %vreg1024, 1, %noreg, 64, %noreg, %EFLAGS<imp-def>; mem:LD4[%k0226] GR32:%vreg1026 GR64:%vreg1024
7488B		JE_1 <BB#38>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#38 BB#37

7504B	BB#37: derived from LLVM BB %if.then.229
	    Predecessors according to CFG: BB#36
7520B		%vreg1254<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg1254
7536B		%vreg1252<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1252
7552B		MOV32mr %vreg1252, 1, %noreg, 64, %noreg, %vreg1254; mem:ST4[%k0231] GR64:%vreg1252 GR32:%vreg1254
7568B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2

7584B	BB#38: derived from LLVM BB %if.end.232
	    Predecessors according to CFG: BB#36
7600B		%vreg1089<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1089
7616B		%vreg1088<def> = MOV32rm %vreg1089, 1, %noreg, 60, %noreg; mem:LD4[%tPos233] GR32:%vreg1088 GR64:%vreg1089
7632B		%vreg1086<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1086
7648B		%vreg1085<def> = COPY %vreg1086; GR64:%vreg1085,%vreg1086
7664B		%vreg1085<def,tied1> = ADD64ri32 %vreg1085<tied0>, 1096, %EFLAGS<imp-def,dead>; GR64:%vreg1085
7680B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
7696B		%EDI<def> = COPY %vreg1088; GR32:%vreg1088
7712B		%RSI<def> = COPY %vreg1085; GR64:%vreg1085
7728B		CALL64pcrel32 <ga:@BZ2_indexIntoF>, <regmask>, %RSP<imp-use>, %EDI<imp-use>, %RSI<imp-use,kill>, %EAX<imp-def>
7744B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
7760B		%vreg1082<def> = COPY %EAX<kill>; GR32:%vreg1082
7776B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
7792B		STACKMAP 4, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
7808B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
7824B		%vreg1079<def> = COPY %vreg1082:sub_8bit; GR8:%vreg1079 GR32:%vreg1082
7840B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg1079; mem:ST1[%k1] GR8:%vreg1079
7856B		%vreg1076<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1076
7872B		%vreg1073<def> = MOV32rm %vreg1076, 1, %noreg, 60, %noreg; mem:LD4[%tPos238] GR32:%vreg1073 GR64:%vreg1076
7888B		%vreg1074<def> = SUBREG_TO_REG 0, %vreg1073, 4; GR64_NOSP:%vreg1074 GR32:%vreg1073
7904B		%vreg1071<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1071
7920B		%vreg1070<def> = MOV64rm %vreg1071, 1, %noreg, 3160, %noreg; mem:LD8[%ll16240] GR64:%vreg1070,%vreg1071
7936B		%vreg1066<def> = MOVZX32rm16 %vreg1070, 2, %vreg1074, 0, %noreg; mem:LD2[%arrayidx241] GR32:%vreg1066 GR64:%vreg1070 GR64_NOSP:%vreg1074
7952B		%vreg1064<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1064
7968B		%vreg1063<def> = MOV32rm %vreg1064, 1, %noreg, 60, %noreg; mem:LD4[%tPos243] GR32:%vreg1063 GR64:%vreg1064
7984B		%vreg1061<def> = COPY %vreg1063; GR32:%vreg1061,%vreg1063
8000B		%vreg1061<def,tied1> = SHR32ri %vreg1061<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg1061
8016B		%vreg1058<def> = MOV32rr %vreg1061; GR32:%vreg1058,%vreg1061
8032B		%vreg1059<def> = SUBREG_TO_REG 0, %vreg1058, 4; GR64_NOSP:%vreg1059 GR32:%vreg1058
8048B		%vreg1056<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1056
8064B		%vreg1055<def> = MOV64rm %vreg1056, 1, %noreg, 3168, %noreg; mem:LD8[%ll4246] GR64:%vreg1055,%vreg1056
8080B		%vreg1051<def> = MOVZX32rm8 %vreg1055, 1, %vreg1059, 0, %noreg; mem:LD1[%arrayidx247] GR32:%vreg1051 GR64:%vreg1055 GR64_NOSP:%vreg1059
8096B		%vreg1049<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1049
8112B		%vreg1048<def> = MOV32rm %vreg1049, 1, %noreg, 60, %noreg; mem:LD4[%tPos249] GR32:%vreg1048 GR64:%vreg1049
8128B		%vreg1046<def> = COPY %vreg1048; GR32:%vreg1046,%vreg1048
8144B		%vreg1046<def,tied1> = SHL32ri %vreg1046<tied0>, 2, %EFLAGS<imp-def,dead>; GR32:%vreg1046
8160B		%vreg1044<def> = COPY %vreg1046; GR32:%vreg1044,%vreg1046
8176B		%vreg1044<def,tied1> = AND32ri8 %vreg1044<tied0>, 4, %EFLAGS<imp-def,dead>; GR32:%vreg1044
8192B		%ECX<def> = COPY %vreg1044; GR32:%vreg1044
8208B		%CL<def> = KILL %ECX<kill>
8224B		%vreg1042<def> = COPY %vreg1051; GR32:%vreg1042,%vreg1051
8240B		%vreg1042<def,tied1> = SHR32rCL %vreg1042<tied0>, %EFLAGS<imp-def,dead>, %CL<imp-use,kill>; GR32:%vreg1042
8256B		%vreg1039<def> = COPY %vreg1042; GR32:%vreg1039,%vreg1042
8272B		%vreg1039<def,tied1> = AND32ri8 %vreg1039<tied0>, 15, %EFLAGS<imp-def,dead>; GR32:%vreg1039
8288B		%vreg1037<def> = COPY %vreg1039; GR32:%vreg1037,%vreg1039
8304B		%vreg1037<def,tied1> = SHL32ri %vreg1037<tied0>, 16, %EFLAGS<imp-def,dead>; GR32:%vreg1037
8320B		%vreg1035<def> = COPY %vreg1066; GR32:%vreg1035,%vreg1066
8336B		%vreg1035<def,tied1> = OR32rr %vreg1035<tied0>, %vreg1037, %EFLAGS<imp-def,dead>; GR32:%vreg1035,%vreg1037
8352B		%vreg1032<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1032
8368B		MOV32mr %vreg1032, 1, %noreg, 60, %noreg, %vreg1035; mem:ST4[%tPos256] GR64:%vreg1032 GR32:%vreg1035
8384B		%vreg1029<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1029
8400B		CMP32mi8 %vreg1029, 1, %noreg, 24, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%rNToGo257] GR64:%vreg1029
8416B		JNE_1 <BB#42>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#42 BB#39

8432B	BB#39: derived from LLVM BB %if.then.260
	    Predecessors according to CFG: BB#38
8448B		%vreg1107<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1107
8464B		%vreg1105<def> = MOVSX64rm32 %vreg1107, 1, %noreg, 28, %noreg; mem:LD4[%rTPos261] GR64_NOSP:%vreg1105 GR64:%vreg1107
8480B		%vreg1103<def> = MOV32rm %noreg, 4, %vreg1105, <ga:@BZ2_rNums>, %noreg; mem:LD4[%arrayidx263] GR32:%vreg1103 GR64_NOSP:%vreg1105
8496B		%vreg1101<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1101
8512B		MOV32mr %vreg1101, 1, %noreg, 24, %noreg, %vreg1103; mem:ST4[%rNToGo264] GR64:%vreg1101 GR32:%vreg1103
8528B		%vreg1098<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1098
8544B		%vreg1097<def> = MOV32rm %vreg1098, 1, %noreg, 28, %noreg; mem:LD4[%rTPos265] GR32:%vreg1097 GR64:%vreg1098
8560B		%vreg1096<def> = COPY %vreg1097; GR32:%vreg1096,%vreg1097
8576B		%vreg1096<def,tied1> = ADD32ri8 %vreg1096<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg1096
8592B		MOV32mr %vreg1098, 1, %noreg, 28, %noreg, %vreg1096; mem:ST4[%rTPos265] GR64:%vreg1098 GR32:%vreg1096
8608B		%vreg1092<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1092
8624B		CMP32mi %vreg1092, 1, %noreg, 28, %noreg, 512, %EFLAGS<imp-def>; mem:LD4[%rTPos267] GR64:%vreg1092
8640B		JNE_1 <BB#41>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#41 BB#40

8656B	BB#40: derived from LLVM BB %if.then.270
	    Predecessors according to CFG: BB#39
8672B		%vreg1109<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1109
8688B		MOV32mi %vreg1109, 1, %noreg, 28, %noreg, 0; mem:ST4[%rTPos271] GR64:%vreg1109
	    Successors according to CFG: BB#41

8704B	BB#41: derived from LLVM BB %if.end.272
	    Predecessors according to CFG: BB#39 BB#40
8720B		JMP_1 <BB#42>
	    Successors according to CFG: BB#42

8736B	BB#42: derived from LLVM BB %if.end.273
	    Predecessors according to CFG: BB#38 BB#41
8752B		%vreg1195<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg1195
8768B		%vreg1196<def> = MOV32ri 1; GR32:%vreg1196
8784B		%vreg1205<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1205
8800B		%vreg1204<def> = MOV32rm %vreg1205, 1, %noreg, 24, %noreg; mem:LD4[%rNToGo274] GR32:%vreg1204 GR64:%vreg1205
8816B		%vreg1203<def> = COPY %vreg1204; GR32:%vreg1203,%vreg1204
8832B		%vreg1203<def,tied1> = ADD32ri8 %vreg1203<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg1203
8848B		MOV32mr %vreg1205, 1, %noreg, 24, %noreg, %vreg1203; mem:ST4[%rNToGo274] GR64:%vreg1205 GR32:%vreg1203
8864B		%vreg1199<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1199
8880B		CMP32mi8 %vreg1199, 1, %noreg, 24, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%rNToGo276] GR64:%vreg1199
8896B		%vreg1197<def> = COPY %vreg1195; GR32:%vreg1197,%vreg1195
8912B		%vreg1197<def,tied1> = CMOVE32rr %vreg1197<tied0>, %vreg1196, %EFLAGS<imp-use,kill>; GR32:%vreg1197,%vreg1196
8928B		%vreg1193<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg1193
8944B		%vreg1191<def> = COPY %vreg1193; GR32:%vreg1191,%vreg1193
8960B		%vreg1191<def,tied1> = XOR32rr %vreg1191<tied0>, %vreg1197, %EFLAGS<imp-def,dead>; GR32:%vreg1191,%vreg1197
8976B		%vreg1188<def> = COPY %vreg1191:sub_8bit; GR8:%vreg1188 GR32:%vreg1191
8992B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg1188; mem:ST1[%k1] GR8:%vreg1188
9008B		%vreg1185<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1185
9024B		%vreg1184<def> = MOV32rm %vreg1185, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used283] GR32:%vreg1184 GR64:%vreg1185
9040B		%vreg1183<def> = COPY %vreg1184; GR32:%vreg1183,%vreg1184
9056B		%vreg1183<def,tied1> = ADD32ri8 %vreg1183<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg1183
9072B		MOV32mr %vreg1185, 1, %noreg, 1092, %noreg, %vreg1183; mem:ST4[%nblock_used283] GR64:%vreg1185 GR32:%vreg1183
9088B		%vreg1179<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg1179
9104B		%vreg1177<def> = COPY %vreg1179; GR32:%vreg1177,%vreg1179
9120B		%vreg1177<def,tied1> = ADD32ri8 %vreg1177<tied0>, 4, %EFLAGS<imp-def,dead>; GR32:%vreg1177
9136B		%vreg1175<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1175
9152B		MOV32mr %vreg1175, 1, %noreg, 16, %noreg, %vreg1177; mem:ST4[%state_out_len287] GR64:%vreg1175 GR32:%vreg1177
9168B		%vreg1172<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1172
9184B		%vreg1171<def> = MOV32rm %vreg1172, 1, %noreg, 60, %noreg; mem:LD4[%tPos288] GR32:%vreg1171 GR64:%vreg1172
9200B		%vreg1169<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1169
9216B		%vreg1168<def> = COPY %vreg1169; GR64:%vreg1168,%vreg1169
9232B		%vreg1168<def,tied1> = ADD64ri32 %vreg1168<tied0>, 1096, %EFLAGS<imp-def,dead>; GR64:%vreg1168
9248B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
9264B		%EDI<def> = COPY %vreg1171; GR32:%vreg1171
9280B		%RSI<def> = COPY %vreg1168; GR64:%vreg1168
9296B		CALL64pcrel32 <ga:@BZ2_indexIntoF>, <regmask>, %RSP<imp-use>, %EDI<imp-use>, %RSI<imp-use,kill>, %EAX<imp-def>
9312B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
9328B		%vreg1165<def> = COPY %EAX<kill>; GR32:%vreg1165
9344B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
9360B		STACKMAP 5, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
9376B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
9392B		%vreg1162<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1162
9408B		MOV32mr %vreg1162, 1, %noreg, 64, %noreg, %vreg1165; mem:ST4[%k0292] GR64:%vreg1162 GR32:%vreg1165
9424B		%vreg1159<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1159
9440B		%vreg1156<def> = MOV32rm %vreg1159, 1, %noreg, 60, %noreg; mem:LD4[%tPos293] GR32:%vreg1156 GR64:%vreg1159
9456B		%vreg1157<def> = SUBREG_TO_REG 0, %vreg1156, 4; GR64_NOSP:%vreg1157 GR32:%vreg1156
9472B		%vreg1154<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1154
9488B		%vreg1153<def> = MOV64rm %vreg1154, 1, %noreg, 3160, %noreg; mem:LD8[%ll16295] GR64:%vreg1153,%vreg1154
9504B		%vreg1149<def> = MOVZX32rm16 %vreg1153, 2, %vreg1157, 0, %noreg; mem:LD2[%arrayidx296] GR32:%vreg1149 GR64:%vreg1153 GR64_NOSP:%vreg1157
9520B		%vreg1147<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1147
9536B		%vreg1146<def> = MOV32rm %vreg1147, 1, %noreg, 60, %noreg; mem:LD4[%tPos298] GR32:%vreg1146 GR64:%vreg1147
9552B		%vreg1144<def> = COPY %vreg1146; GR32:%vreg1144,%vreg1146
9568B		%vreg1144<def,tied1> = SHR32ri %vreg1144<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg1144
9584B		%vreg1141<def> = MOV32rr %vreg1144; GR32:%vreg1141,%vreg1144
9600B		%vreg1142<def> = SUBREG_TO_REG 0, %vreg1141, 4; GR64_NOSP:%vreg1142 GR32:%vreg1141
9616B		%vreg1139<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1139
9632B		%vreg1138<def> = MOV64rm %vreg1139, 1, %noreg, 3168, %noreg; mem:LD8[%ll4301] GR64:%vreg1138,%vreg1139
9648B		%vreg1134<def> = MOVZX32rm8 %vreg1138, 1, %vreg1142, 0, %noreg; mem:LD1[%arrayidx302] GR32:%vreg1134 GR64:%vreg1138 GR64_NOSP:%vreg1142
9664B		%vreg1132<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1132
9680B		%vreg1131<def> = MOV32rm %vreg1132, 1, %noreg, 60, %noreg; mem:LD4[%tPos304] GR32:%vreg1131 GR64:%vreg1132
9696B		%vreg1129<def> = COPY %vreg1131; GR32:%vreg1129,%vreg1131
9712B		%vreg1129<def,tied1> = SHL32ri %vreg1129<tied0>, 2, %EFLAGS<imp-def,dead>; GR32:%vreg1129
9728B		%vreg1127<def> = COPY %vreg1129; GR32:%vreg1127,%vreg1129
9744B		%vreg1127<def,tied1> = AND32ri8 %vreg1127<tied0>, 4, %EFLAGS<imp-def,dead>; GR32:%vreg1127
9760B		%ECX<def> = COPY %vreg1127; GR32:%vreg1127
9776B		%CL<def> = KILL %ECX<kill>
9792B		%vreg1125<def> = COPY %vreg1134; GR32:%vreg1125,%vreg1134
9808B		%vreg1125<def,tied1> = SHR32rCL %vreg1125<tied0>, %EFLAGS<imp-def,dead>, %CL<imp-use,kill>; GR32:%vreg1125
9824B		%vreg1122<def> = COPY %vreg1125; GR32:%vreg1122,%vreg1125
9840B		%vreg1122<def,tied1> = AND32ri8 %vreg1122<tied0>, 15, %EFLAGS<imp-def,dead>; GR32:%vreg1122
9856B		%vreg1120<def> = COPY %vreg1122; GR32:%vreg1120,%vreg1122
9872B		%vreg1120<def,tied1> = SHL32ri %vreg1120<tied0>, 16, %EFLAGS<imp-def,dead>; GR32:%vreg1120
9888B		%vreg1118<def> = COPY %vreg1149; GR32:%vreg1118,%vreg1149
9904B		%vreg1118<def,tied1> = OR32rr %vreg1118<tied0>, %vreg1120, %EFLAGS<imp-def,dead>; GR32:%vreg1118,%vreg1120
9920B		%vreg1115<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1115
9936B		MOV32mr %vreg1115, 1, %noreg, 60, %noreg, %vreg1118; mem:ST4[%tPos311] GR64:%vreg1115 GR32:%vreg1118
9952B		%vreg1112<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1112
9968B		CMP32mi8 %vreg1112, 1, %noreg, 24, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%rNToGo312] GR64:%vreg1112
9984B		JNE_1 <BB#46>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#46 BB#43

10000B	BB#43: derived from LLVM BB %if.then.315
	    Predecessors according to CFG: BB#42
10016B		%vreg1223<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1223
10032B		%vreg1221<def> = MOVSX64rm32 %vreg1223, 1, %noreg, 28, %noreg; mem:LD4[%rTPos316] GR64_NOSP:%vreg1221 GR64:%vreg1223
10048B		%vreg1219<def> = MOV32rm %noreg, 4, %vreg1221, <ga:@BZ2_rNums>, %noreg; mem:LD4[%arrayidx318] GR32:%vreg1219 GR64_NOSP:%vreg1221
10064B		%vreg1217<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1217
10080B		MOV32mr %vreg1217, 1, %noreg, 24, %noreg, %vreg1219; mem:ST4[%rNToGo319] GR64:%vreg1217 GR32:%vreg1219
10096B		%vreg1214<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1214
10112B		%vreg1213<def> = MOV32rm %vreg1214, 1, %noreg, 28, %noreg; mem:LD4[%rTPos320] GR32:%vreg1213 GR64:%vreg1214
10128B		%vreg1212<def> = COPY %vreg1213; GR32:%vreg1212,%vreg1213
10144B		%vreg1212<def,tied1> = ADD32ri8 %vreg1212<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg1212
10160B		MOV32mr %vreg1214, 1, %noreg, 28, %noreg, %vreg1212; mem:ST4[%rTPos320] GR64:%vreg1214 GR32:%vreg1212
10176B		%vreg1208<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1208
10192B		CMP32mi %vreg1208, 1, %noreg, 28, %noreg, 512, %EFLAGS<imp-def>; mem:LD4[%rTPos322] GR64:%vreg1208
10208B		JNE_1 <BB#45>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#45 BB#44

10224B	BB#44: derived from LLVM BB %if.then.325
	    Predecessors according to CFG: BB#43
10240B		%vreg1225<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1225
10256B		MOV32mi %vreg1225, 1, %noreg, 28, %noreg, 0; mem:ST4[%rTPos326] GR64:%vreg1225
	    Successors according to CFG: BB#45

10272B	BB#45: derived from LLVM BB %if.end.327
	    Predecessors according to CFG: BB#43 BB#44
10288B		JMP_1 <BB#46>
	    Successors according to CFG: BB#46

10304B	BB#46: derived from LLVM BB %if.end.328
	    Predecessors according to CFG: BB#42 BB#45
10320B		%vreg1239<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg1239
10336B		%vreg1240<def> = MOV32ri 1; GR32:%vreg1240
10352B		%vreg1249<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1249
10368B		%vreg1248<def> = MOV32rm %vreg1249, 1, %noreg, 24, %noreg; mem:LD4[%rNToGo329] GR32:%vreg1248 GR64:%vreg1249
10384B		%vreg1247<def> = COPY %vreg1248; GR32:%vreg1247,%vreg1248
10400B		%vreg1247<def,tied1> = ADD32ri8 %vreg1247<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg1247
10416B		MOV32mr %vreg1249, 1, %noreg, 24, %noreg, %vreg1247; mem:ST4[%rNToGo329] GR64:%vreg1249 GR32:%vreg1247
10432B		%vreg1243<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1243
10448B		CMP32mi8 %vreg1243, 1, %noreg, 24, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%rNToGo331] GR64:%vreg1243
10464B		%vreg1241<def> = COPY %vreg1239; GR32:%vreg1241,%vreg1239
10480B		%vreg1241<def,tied1> = CMOVE32rr %vreg1241<tied0>, %vreg1240, %EFLAGS<imp-use,kill>; GR32:%vreg1241,%vreg1240
10496B		%vreg1237<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1237
10512B		%vreg1236<def> = COPY %vreg1241; GR32:%vreg1236,%vreg1241
10528B		%vreg1236<def,tied1> = XOR32rm %vreg1236<tied0>, %vreg1237, 1, %noreg, 64, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%k0335] GR32:%vreg1236 GR64:%vreg1237
10544B		MOV32mr %vreg1237, 1, %noreg, 64, %noreg, %vreg1236; mem:ST4[%k0335] GR64:%vreg1237 GR32:%vreg1236
10560B		%vreg1231<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1231
10576B		%vreg1230<def> = MOV32rm %vreg1231, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used337] GR32:%vreg1230 GR64:%vreg1231
10592B		%vreg1229<def> = COPY %vreg1230; GR32:%vreg1229,%vreg1230
10608B		%vreg1229<def,tied1> = ADD32ri8 %vreg1229<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg1229
10624B		MOV32mr %vreg1231, 1, %noreg, 1092, %noreg, %vreg1229; mem:ST4[%nblock_used337] GR64:%vreg1231 GR32:%vreg1229
10640B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2

10656B	BB#47: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#0
10672B		JMP_1 <BB#48>
	    Successors according to CFG: BB#48

10688B	BB#48: derived from LLVM BB %while.body.339
	    Predecessors according to CFG: BB#47 BB#72 BB#71 BB#69 BB#67 BB#65 BB#63 BB#61
10704B		JMP_1 <BB#49>
	    Successors according to CFG: BB#49

10720B	BB#49: derived from LLVM BB %while.body.341
	    Predecessors according to CFG: BB#48 BB#55
10736B		%vreg12<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg12
10752B		%vreg11<def> = MOV64rm %vreg12, 1, %noreg, 0, %noreg; mem:LD8[%strm342] GR64:%vreg11,%vreg12
10768B		CMP32mi8 %vreg11, 1, %noreg, 32, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_out343] GR64:%vreg11
10784B		JNE_1 <BB#51>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#51 BB#50

10800B	BB#50: derived from LLVM BB %if.then.346
	    Predecessors according to CFG: BB#49
10816B		MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST1[%retval]
10832B		JMP_1 <BB#73>
	    Successors according to CFG: BB#73

10848B	BB#51: derived from LLVM BB %if.end.347
	    Predecessors according to CFG: BB#49
10864B		%vreg15<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg15
10880B		CMP32mi8 %vreg15, 1, %noreg, 16, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%state_out_len348] GR64:%vreg15
10896B		JNE_1 <BB#53>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#53 BB#52

10912B	BB#52: derived from LLVM BB %if.then.351
	    Predecessors according to CFG: BB#51
10928B		JMP_1 <BB#56>
	    Successors according to CFG: BB#56

10944B	BB#53: derived from LLVM BB %if.end.352
	    Predecessors according to CFG: BB#51
10960B		%vreg87<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg87
10976B		%vreg86<def> = MOV8rm %vreg87, 1, %noreg, 12, %noreg; mem:LD1[%state_out_ch353] GR8:%vreg86 GR64:%vreg87
10992B		%vreg84<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg84
11008B		%vreg83<def> = MOV64rm %vreg84, 1, %noreg, 0, %noreg; mem:LD8[%strm354] GR64:%vreg83,%vreg84
11024B		%vreg81<def> = MOV64rm %vreg83, 1, %noreg, 24, %noreg; mem:LD8[%next_out355] GR64:%vreg81,%vreg83
11040B		MOV8mr %vreg81, 1, %noreg, 0, %noreg, %vreg86; mem:ST1[%261] GR64:%vreg81 GR8:%vreg86
11056B		%vreg77<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg77
11072B		%vreg76<def> = MOV32rm %vreg77, 1, %noreg, 3184, %noreg; mem:LD4[%calculatedBlockCRC356] GR32:%vreg76 GR64:%vreg77
11088B		%vreg74<def> = COPY %vreg76; GR32:%vreg74,%vreg76
11104B		%vreg74<def,tied1> = SHL32ri %vreg74<tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg74
11120B		%vreg72<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg72
11136B		%vreg71<def> = MOV32rm %vreg72, 1, %noreg, 3184, %noreg; mem:LD4[%calculatedBlockCRC358] GR32:%vreg71 GR64:%vreg72
11152B		%vreg69<def> = COPY %vreg71; GR32:%vreg69,%vreg71
11168B		%vreg69<def,tied1> = SHR32ri %vreg69<tied0>, 24, %EFLAGS<imp-def,dead>; GR32:%vreg69
11184B		%vreg67<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg67
11200B		%vreg65<def> = MOVZX32rm8 %vreg67, 1, %noreg, 12, %noreg; mem:LD1[%state_out_ch360] GR32:%vreg65 GR64:%vreg67
11216B		%vreg63<def> = COPY %vreg69; GR32:%vreg63,%vreg69
11232B		%vreg63<def,tied1> = XOR32rr %vreg63<tied0>, %vreg65, %EFLAGS<imp-def,dead>; GR32:%vreg63,%vreg65
11248B		%vreg59<def> = MOV32rr %vreg63; GR32:%vreg59,%vreg63
11264B		%vreg60<def> = SUBREG_TO_REG 0, %vreg59, 4; GR64_NOSP:%vreg60 GR32:%vreg59
11280B		%vreg56<def> = COPY %vreg74; GR32:%vreg56,%vreg74
11296B		%vreg56<def,tied1> = XOR32rm %vreg56<tied0>, %noreg, 4, %vreg60, <ga:@BZ2_crc32Table>, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%arrayidx364] GR32:%vreg56 GR64_NOSP:%vreg60
11312B		%vreg53<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg53
11328B		MOV32mr %vreg53, 1, %noreg, 3184, %noreg, %vreg56; mem:ST4[%calculatedBlockCRC366] GR64:%vreg53 GR32:%vreg56
11344B		%vreg50<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg50
11360B		%vreg49<def> = MOV32rm %vreg50, 1, %noreg, 16, %noreg; mem:LD4[%state_out_len367] GR32:%vreg49 GR64:%vreg50
11376B		%vreg48<def> = COPY %vreg49; GR32:%vreg48,%vreg49
11392B		%vreg48<def,tied1> = ADD32ri8 %vreg48<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg48
11408B		MOV32mr %vreg50, 1, %noreg, 16, %noreg, %vreg48; mem:ST4[%state_out_len367] GR64:%vreg50 GR32:%vreg48
11424B		%vreg44<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg44
11440B		%vreg43<def> = MOV64rm %vreg44, 1, %noreg, 0, %noreg; mem:LD8[%strm369] GR64:%vreg43,%vreg44
11456B		%vreg41<def> = MOV64rm %vreg43, 1, %noreg, 24, %noreg; mem:LD8[%next_out370] GR64:%vreg41,%vreg43
11472B		%vreg40<def> = COPY %vreg41; GR64:%vreg40,%vreg41
11488B		%vreg40<def,tied1> = ADD64ri8 %vreg40<tied0>, 1, %EFLAGS<imp-def,dead>; GR64:%vreg40
11504B		MOV64mr %vreg43, 1, %noreg, 24, %noreg, %vreg40; mem:ST8[%next_out370] GR64:%vreg43,%vreg40
11520B		%vreg36<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg36
11536B		%vreg35<def> = MOV64rm %vreg36, 1, %noreg, 0, %noreg; mem:LD8[%strm372] GR64:%vreg35,%vreg36
11552B		%vreg33<def> = MOV32rm %vreg35, 1, %noreg, 32, %noreg; mem:LD4[%avail_out373] GR32:%vreg33 GR64:%vreg35
11568B		%vreg32<def> = COPY %vreg33; GR32:%vreg32,%vreg33
11584B		%vreg32<def,tied1> = ADD32ri8 %vreg32<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg32
11600B		MOV32mr %vreg35, 1, %noreg, 32, %noreg, %vreg32; mem:ST4[%avail_out373] GR64:%vreg35 GR32:%vreg32
11616B		%vreg28<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg28
11632B		%vreg27<def> = MOV64rm %vreg28, 1, %noreg, 0, %noreg; mem:LD8[%strm375] GR64:%vreg27,%vreg28
11648B		%vreg25<def> = MOV32rm %vreg27, 1, %noreg, 36, %noreg; mem:LD4[%total_out_lo32376] GR32:%vreg25 GR64:%vreg27
11664B		%vreg24<def> = COPY %vreg25; GR32:%vreg24,%vreg25
11680B		%vreg24<def,tied1> = ADD32ri8 %vreg24<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg24
11696B		MOV32mr %vreg27, 1, %noreg, 36, %noreg, %vreg24; mem:ST4[%total_out_lo32376] GR64:%vreg27 GR32:%vreg24
11712B		%vreg20<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg20
11728B		%vreg19<def> = MOV64rm %vreg20, 1, %noreg, 0, %noreg; mem:LD8[%strm378] GR64:%vreg19,%vreg20
11744B		CMP32mi8 %vreg19, 1, %noreg, 36, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%total_out_lo32379] GR64:%vreg19
11760B		JNE_1 <BB#55>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#55 BB#54

11776B	BB#54: derived from LLVM BB %if.then.382
	    Predecessors according to CFG: BB#53
11792B		%vreg95<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg95
11808B		%vreg94<def> = MOV64rm %vreg95, 1, %noreg, 0, %noreg; mem:LD8[%strm383] GR64:%vreg94,%vreg95
11824B		%vreg92<def> = MOV32rm %vreg94, 1, %noreg, 40, %noreg; mem:LD4[%total_out_hi32384] GR32:%vreg92 GR64:%vreg94
11840B		%vreg91<def> = COPY %vreg92; GR32:%vreg91,%vreg92
11856B		%vreg91<def,tied1> = ADD32ri8 %vreg91<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg91
11872B		MOV32mr %vreg94, 1, %noreg, 40, %noreg, %vreg91; mem:ST4[%total_out_hi32384] GR64:%vreg94 GR32:%vreg91
	    Successors according to CFG: BB#55

11888B	BB#55: derived from LLVM BB %if.end.386
	    Predecessors according to CFG: BB#53 BB#54
11904B		JMP_1 <BB#49>
	    Successors according to CFG: BB#49

11920B	BB#56: derived from LLVM BB %while.end.387
	    Predecessors according to CFG: BB#52
11936B		%vreg105<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg105
11952B		%vreg104<def> = MOV32rm %vreg105, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used388] GR32:%vreg104 GR64:%vreg105
11968B		%vreg102<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg102
11984B		%vreg101<def> = MOV32rm %vreg102, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock389] GR32:%vreg101 GR64:%vreg102
12000B		%vreg99<def> = COPY %vreg101; GR32:%vreg99,%vreg101
12016B		%vreg99<def,tied1> = ADD32ri8 %vreg99<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg99
12032B		CMP32rr %vreg104, %vreg99, %EFLAGS<imp-def>; GR32:%vreg104,%vreg99
12048B		JNE_1 <BB#58>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#58 BB#57

12064B	BB#57: derived from LLVM BB %if.then.393
	    Predecessors according to CFG: BB#56
12080B		MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST1[%retval]
12096B		JMP_1 <BB#73>
	    Successors according to CFG: BB#73

12112B	BB#58: derived from LLVM BB %if.end.394
	    Predecessors according to CFG: BB#56
12128B		%vreg115<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg115
12144B		%vreg114<def> = MOV32rm %vreg115, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used395] GR32:%vreg114 GR64:%vreg115
12160B		%vreg112<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg112
12176B		%vreg111<def> = MOV32rm %vreg112, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock396] GR32:%vreg111 GR64:%vreg112
12192B		%vreg109<def> = COPY %vreg111; GR32:%vreg109,%vreg111
12208B		%vreg109<def,tied1> = ADD32ri8 %vreg109<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg109
12224B		CMP32rr %vreg114, %vreg109, %EFLAGS<imp-def>; GR32:%vreg114,%vreg109
12240B		JLE_1 <BB#60>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#60 BB#59

12256B	BB#59: derived from LLVM BB %if.then.400
	    Predecessors according to CFG: BB#58
12272B		MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 1; mem:ST1[%retval]
12288B		JMP_1 <BB#73>
	    Successors according to CFG: BB#73

12304B	BB#60: derived from LLVM BB %if.end.401
	    Predecessors according to CFG: BB#58
12320B		%vreg201<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg201
12336B		MOV32mi %vreg201, 1, %noreg, 16, %noreg, 1; mem:ST4[%state_out_len402] GR64:%vreg201
12352B		%vreg199<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg199
12368B		%vreg198<def> = MOV32rm %vreg199, 1, %noreg, 64, %noreg; mem:LD4[%k0403] GR32:%vreg198 GR64:%vreg199
12384B		%vreg196<def> = COPY %vreg198:sub_8bit; GR8:%vreg196 GR32:%vreg198
12400B		%vreg194<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg194
12416B		MOV8mr %vreg194, 1, %noreg, 12, %noreg, %vreg196; mem:ST1[%state_out_ch405] GR64:%vreg194 GR8:%vreg196
12432B		%vreg191<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg191
12448B		%vreg190<def> = MOV32rm %vreg191, 1, %noreg, 60, %noreg; mem:LD4[%tPos406] GR32:%vreg190 GR64:%vreg191
12464B		%vreg188<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg188
12480B		%vreg187<def> = COPY %vreg188; GR64:%vreg187,%vreg188
12496B		%vreg187<def,tied1> = ADD64ri32 %vreg187<tied0>, 1096, %EFLAGS<imp-def,dead>; GR64:%vreg187
12512B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
12528B		%EDI<def> = COPY %vreg190; GR32:%vreg190
12544B		%RSI<def> = COPY %vreg187; GR64:%vreg187
12560B		CALL64pcrel32 <ga:@BZ2_indexIntoF>, <regmask>, %RSP<imp-use>, %EDI<imp-use>, %RSI<imp-use,kill>, %EAX<imp-def>
12576B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
12592B		%vreg184<def> = COPY %EAX<kill>; GR32:%vreg184
12608B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
12624B		STACKMAP 6, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
12640B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
12656B		%vreg181<def> = COPY %vreg184:sub_8bit; GR8:%vreg181 GR32:%vreg184
12672B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg181; mem:ST1[%k1] GR8:%vreg181
12688B		%vreg178<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg178
12704B		%vreg175<def> = MOV32rm %vreg178, 1, %noreg, 60, %noreg; mem:LD4[%tPos411] GR32:%vreg175 GR64:%vreg178
12720B		%vreg176<def> = SUBREG_TO_REG 0, %vreg175, 4; GR64_NOSP:%vreg176 GR32:%vreg175
12736B		%vreg173<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg173
12752B		%vreg172<def> = MOV64rm %vreg173, 1, %noreg, 3160, %noreg; mem:LD8[%ll16413] GR64:%vreg172,%vreg173
12768B		%vreg168<def> = MOVZX32rm16 %vreg172, 2, %vreg176, 0, %noreg; mem:LD2[%arrayidx414] GR32:%vreg168 GR64:%vreg172 GR64_NOSP:%vreg176
12784B		%vreg166<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg166
12800B		%vreg165<def> = MOV32rm %vreg166, 1, %noreg, 60, %noreg; mem:LD4[%tPos416] GR32:%vreg165 GR64:%vreg166
12816B		%vreg163<def> = COPY %vreg165; GR32:%vreg163,%vreg165
12832B		%vreg163<def,tied1> = SHR32ri %vreg163<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg163
12848B		%vreg160<def> = MOV32rr %vreg163; GR32:%vreg160,%vreg163
12864B		%vreg161<def> = SUBREG_TO_REG 0, %vreg160, 4; GR64_NOSP:%vreg161 GR32:%vreg160
12880B		%vreg158<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg158
12896B		%vreg157<def> = MOV64rm %vreg158, 1, %noreg, 3168, %noreg; mem:LD8[%ll4419] GR64:%vreg157,%vreg158
12912B		%vreg153<def> = MOVZX32rm8 %vreg157, 1, %vreg161, 0, %noreg; mem:LD1[%arrayidx420] GR32:%vreg153 GR64:%vreg157 GR64_NOSP:%vreg161
12928B		%vreg151<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg151
12944B		%vreg150<def> = MOV32rm %vreg151, 1, %noreg, 60, %noreg; mem:LD4[%tPos422] GR32:%vreg150 GR64:%vreg151
12960B		%vreg148<def> = COPY %vreg150; GR32:%vreg148,%vreg150
12976B		%vreg148<def,tied1> = SHL32ri %vreg148<tied0>, 2, %EFLAGS<imp-def,dead>; GR32:%vreg148
12992B		%vreg146<def> = COPY %vreg148; GR32:%vreg146,%vreg148
13008B		%vreg146<def,tied1> = AND32ri8 %vreg146<tied0>, 4, %EFLAGS<imp-def,dead>; GR32:%vreg146
13024B		%ECX<def> = COPY %vreg146; GR32:%vreg146
13040B		%CL<def> = KILL %ECX<kill>
13056B		%vreg144<def> = COPY %vreg153; GR32:%vreg144,%vreg153
13072B		%vreg144<def,tied1> = SHR32rCL %vreg144<tied0>, %EFLAGS<imp-def,dead>, %CL<imp-use,kill>; GR32:%vreg144
13088B		%vreg141<def> = COPY %vreg144; GR32:%vreg141,%vreg144
13104B		%vreg141<def,tied1> = AND32ri8 %vreg141<tied0>, 15, %EFLAGS<imp-def,dead>; GR32:%vreg141
13120B		%vreg139<def> = COPY %vreg141; GR32:%vreg139,%vreg141
13136B		%vreg139<def,tied1> = SHL32ri %vreg139<tied0>, 16, %EFLAGS<imp-def,dead>; GR32:%vreg139
13152B		%vreg137<def> = COPY %vreg168; GR32:%vreg137,%vreg168
13168B		%vreg137<def,tied1> = OR32rr %vreg137<tied0>, %vreg139, %EFLAGS<imp-def,dead>; GR32:%vreg137,%vreg139
13184B		%vreg134<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg134
13200B		MOV32mr %vreg134, 1, %noreg, 60, %noreg, %vreg137; mem:ST4[%tPos429] GR64:%vreg134 GR32:%vreg137
13216B		%vreg131<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg131
13232B		%vreg130<def> = MOV32rm %vreg131, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used430] GR32:%vreg130 GR64:%vreg131
13248B		%vreg129<def> = COPY %vreg130; GR32:%vreg129,%vreg130
13264B		%vreg129<def,tied1> = ADD32ri8 %vreg129<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg129
13280B		MOV32mr %vreg131, 1, %noreg, 1092, %noreg, %vreg129; mem:ST4[%nblock_used430] GR64:%vreg131 GR32:%vreg129
13296B		%vreg125<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg125
13312B		%vreg124<def> = MOV32rm %vreg125, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used432] GR32:%vreg124 GR64:%vreg125
13328B		%vreg122<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg122
13344B		%vreg121<def> = MOV32rm %vreg122, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock433] GR32:%vreg121 GR64:%vreg122
13360B		%vreg119<def> = COPY %vreg121; GR32:%vreg119,%vreg121
13376B		%vreg119<def,tied1> = ADD32ri8 %vreg119<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg119
13392B		CMP32rr %vreg124, %vreg119, %EFLAGS<imp-def>; GR32:%vreg124,%vreg119
13408B		JNE_1 <BB#62>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#62 BB#61

13424B	BB#61: derived from LLVM BB %if.then.437
	    Predecessors according to CFG: BB#60
13440B		JMP_1 <BB#48>
	    Successors according to CFG: BB#48

13456B	BB#62: derived from LLVM BB %if.end.438
	    Predecessors according to CFG: BB#60
13472B		%vreg207<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg207
13488B		%vreg205<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg205
13504B		CMP32rm %vreg207, %vreg205, 1, %noreg, 64, %noreg, %EFLAGS<imp-def>; mem:LD4[%k0440] GR32:%vreg207 GR64:%vreg205
13520B		JE_1 <BB#64>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#64 BB#63

13536B	BB#63: derived from LLVM BB %if.then.443
	    Predecessors according to CFG: BB#62
13552B		%vreg529<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg529
13568B		%vreg527<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg527
13584B		MOV32mr %vreg527, 1, %noreg, 64, %noreg, %vreg529; mem:ST4[%k0445] GR64:%vreg527 GR32:%vreg529
13600B		JMP_1 <BB#48>
	    Successors according to CFG: BB#48

13616B	BB#64: derived from LLVM BB %if.end.446
	    Predecessors according to CFG: BB#62
13632B		%vreg285<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg285
13648B		MOV32mi %vreg285, 1, %noreg, 16, %noreg, 2; mem:ST4[%state_out_len447] GR64:%vreg285
13664B		%vreg283<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg283
13680B		%vreg282<def> = MOV32rm %vreg283, 1, %noreg, 60, %noreg; mem:LD4[%tPos448] GR32:%vreg282 GR64:%vreg283
13696B		%vreg280<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg280
13712B		%vreg279<def> = COPY %vreg280; GR64:%vreg279,%vreg280
13728B		%vreg279<def,tied1> = ADD64ri32 %vreg279<tied0>, 1096, %EFLAGS<imp-def,dead>; GR64:%vreg279
13744B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
13760B		%EDI<def> = COPY %vreg282; GR32:%vreg282
13776B		%RSI<def> = COPY %vreg279; GR64:%vreg279
13792B		CALL64pcrel32 <ga:@BZ2_indexIntoF>, <regmask>, %RSP<imp-use>, %EDI<imp-use>, %RSI<imp-use,kill>, %EAX<imp-def>
13808B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
13824B		%vreg276<def> = COPY %EAX<kill>; GR32:%vreg276
13840B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
13856B		STACKMAP 7, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
13872B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
13888B		%vreg273<def> = COPY %vreg276:sub_8bit; GR8:%vreg273 GR32:%vreg276
13904B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg273; mem:ST1[%k1] GR8:%vreg273
13920B		%vreg270<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg270
13936B		%vreg267<def> = MOV32rm %vreg270, 1, %noreg, 60, %noreg; mem:LD4[%tPos453] GR32:%vreg267 GR64:%vreg270
13952B		%vreg268<def> = SUBREG_TO_REG 0, %vreg267, 4; GR64_NOSP:%vreg268 GR32:%vreg267
13968B		%vreg265<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg265
13984B		%vreg264<def> = MOV64rm %vreg265, 1, %noreg, 3160, %noreg; mem:LD8[%ll16455] GR64:%vreg264,%vreg265
14000B		%vreg260<def> = MOVZX32rm16 %vreg264, 2, %vreg268, 0, %noreg; mem:LD2[%arrayidx456] GR32:%vreg260 GR64:%vreg264 GR64_NOSP:%vreg268
14016B		%vreg258<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg258
14032B		%vreg257<def> = MOV32rm %vreg258, 1, %noreg, 60, %noreg; mem:LD4[%tPos458] GR32:%vreg257 GR64:%vreg258
14048B		%vreg255<def> = COPY %vreg257; GR32:%vreg255,%vreg257
14064B		%vreg255<def,tied1> = SHR32ri %vreg255<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg255
14080B		%vreg252<def> = MOV32rr %vreg255; GR32:%vreg252,%vreg255
14096B		%vreg253<def> = SUBREG_TO_REG 0, %vreg252, 4; GR64_NOSP:%vreg253 GR32:%vreg252
14112B		%vreg250<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg250
14128B		%vreg249<def> = MOV64rm %vreg250, 1, %noreg, 3168, %noreg; mem:LD8[%ll4461] GR64:%vreg249,%vreg250
14144B		%vreg245<def> = MOVZX32rm8 %vreg249, 1, %vreg253, 0, %noreg; mem:LD1[%arrayidx462] GR32:%vreg245 GR64:%vreg249 GR64_NOSP:%vreg253
14160B		%vreg243<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg243
14176B		%vreg242<def> = MOV32rm %vreg243, 1, %noreg, 60, %noreg; mem:LD4[%tPos464] GR32:%vreg242 GR64:%vreg243
14192B		%vreg240<def> = COPY %vreg242; GR32:%vreg240,%vreg242
14208B		%vreg240<def,tied1> = SHL32ri %vreg240<tied0>, 2, %EFLAGS<imp-def,dead>; GR32:%vreg240
14224B		%vreg238<def> = COPY %vreg240; GR32:%vreg238,%vreg240
14240B		%vreg238<def,tied1> = AND32ri8 %vreg238<tied0>, 4, %EFLAGS<imp-def,dead>; GR32:%vreg238
14256B		%ECX<def> = COPY %vreg238; GR32:%vreg238
14272B		%CL<def> = KILL %ECX<kill>
14288B		%vreg236<def> = COPY %vreg245; GR32:%vreg236,%vreg245
14304B		%vreg236<def,tied1> = SHR32rCL %vreg236<tied0>, %EFLAGS<imp-def,dead>, %CL<imp-use,kill>; GR32:%vreg236
14320B		%vreg233<def> = COPY %vreg236; GR32:%vreg233,%vreg236
14336B		%vreg233<def,tied1> = AND32ri8 %vreg233<tied0>, 15, %EFLAGS<imp-def,dead>; GR32:%vreg233
14352B		%vreg231<def> = COPY %vreg233; GR32:%vreg231,%vreg233
14368B		%vreg231<def,tied1> = SHL32ri %vreg231<tied0>, 16, %EFLAGS<imp-def,dead>; GR32:%vreg231
14384B		%vreg229<def> = COPY %vreg260; GR32:%vreg229,%vreg260
14400B		%vreg229<def,tied1> = OR32rr %vreg229<tied0>, %vreg231, %EFLAGS<imp-def,dead>; GR32:%vreg229,%vreg231
14416B		%vreg226<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg226
14432B		MOV32mr %vreg226, 1, %noreg, 60, %noreg, %vreg229; mem:ST4[%tPos471] GR64:%vreg226 GR32:%vreg229
14448B		%vreg223<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg223
14464B		%vreg222<def> = MOV32rm %vreg223, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used472] GR32:%vreg222 GR64:%vreg223
14480B		%vreg221<def> = COPY %vreg222; GR32:%vreg221,%vreg222
14496B		%vreg221<def,tied1> = ADD32ri8 %vreg221<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg221
14512B		MOV32mr %vreg223, 1, %noreg, 1092, %noreg, %vreg221; mem:ST4[%nblock_used472] GR64:%vreg223 GR32:%vreg221
14528B		%vreg217<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg217
14544B		%vreg216<def> = MOV32rm %vreg217, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used474] GR32:%vreg216 GR64:%vreg217
14560B		%vreg214<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg214
14576B		%vreg213<def> = MOV32rm %vreg214, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock475] GR32:%vreg213 GR64:%vreg214
14592B		%vreg211<def> = COPY %vreg213; GR32:%vreg211,%vreg213
14608B		%vreg211<def,tied1> = ADD32ri8 %vreg211<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg211
14624B		CMP32rr %vreg216, %vreg211, %EFLAGS<imp-def>; GR32:%vreg216,%vreg211
14640B		JNE_1 <BB#66>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#66 BB#65

14656B	BB#65: derived from LLVM BB %if.then.479
	    Predecessors according to CFG: BB#64
14672B		JMP_1 <BB#48>
	    Successors according to CFG: BB#48

14688B	BB#66: derived from LLVM BB %if.end.480
	    Predecessors according to CFG: BB#64
14704B		%vreg291<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg291
14720B		%vreg289<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg289
14736B		CMP32rm %vreg291, %vreg289, 1, %noreg, 64, %noreg, %EFLAGS<imp-def>; mem:LD4[%k0482] GR32:%vreg291 GR64:%vreg289
14752B		JE_1 <BB#68>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#68 BB#67

14768B	BB#67: derived from LLVM BB %if.then.485
	    Predecessors according to CFG: BB#66
14784B		%vreg524<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg524
14800B		%vreg522<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg522
14816B		MOV32mr %vreg522, 1, %noreg, 64, %noreg, %vreg524; mem:ST4[%k0487] GR64:%vreg522 GR32:%vreg524
14832B		JMP_1 <BB#48>
	    Successors according to CFG: BB#48

14848B	BB#68: derived from LLVM BB %if.end.488
	    Predecessors according to CFG: BB#66
14864B		%vreg369<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg369
14880B		MOV32mi %vreg369, 1, %noreg, 16, %noreg, 3; mem:ST4[%state_out_len489] GR64:%vreg369
14896B		%vreg367<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg367
14912B		%vreg366<def> = MOV32rm %vreg367, 1, %noreg, 60, %noreg; mem:LD4[%tPos490] GR32:%vreg366 GR64:%vreg367
14928B		%vreg364<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg364
14944B		%vreg363<def> = COPY %vreg364; GR64:%vreg363,%vreg364
14960B		%vreg363<def,tied1> = ADD64ri32 %vreg363<tied0>, 1096, %EFLAGS<imp-def,dead>; GR64:%vreg363
14976B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
14992B		%EDI<def> = COPY %vreg366; GR32:%vreg366
15008B		%RSI<def> = COPY %vreg363; GR64:%vreg363
15024B		CALL64pcrel32 <ga:@BZ2_indexIntoF>, <regmask>, %RSP<imp-use>, %EDI<imp-use>, %RSI<imp-use,kill>, %EAX<imp-def>
15040B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
15056B		%vreg360<def> = COPY %EAX<kill>; GR32:%vreg360
15072B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
15088B		STACKMAP 8, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
15104B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
15120B		%vreg357<def> = COPY %vreg360:sub_8bit; GR8:%vreg357 GR32:%vreg360
15136B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg357; mem:ST1[%k1] GR8:%vreg357
15152B		%vreg354<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg354
15168B		%vreg351<def> = MOV32rm %vreg354, 1, %noreg, 60, %noreg; mem:LD4[%tPos495] GR32:%vreg351 GR64:%vreg354
15184B		%vreg352<def> = SUBREG_TO_REG 0, %vreg351, 4; GR64_NOSP:%vreg352 GR32:%vreg351
15200B		%vreg349<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg349
15216B		%vreg348<def> = MOV64rm %vreg349, 1, %noreg, 3160, %noreg; mem:LD8[%ll16497] GR64:%vreg348,%vreg349
15232B		%vreg344<def> = MOVZX32rm16 %vreg348, 2, %vreg352, 0, %noreg; mem:LD2[%arrayidx498] GR32:%vreg344 GR64:%vreg348 GR64_NOSP:%vreg352
15248B		%vreg342<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg342
15264B		%vreg341<def> = MOV32rm %vreg342, 1, %noreg, 60, %noreg; mem:LD4[%tPos500] GR32:%vreg341 GR64:%vreg342
15280B		%vreg339<def> = COPY %vreg341; GR32:%vreg339,%vreg341
15296B		%vreg339<def,tied1> = SHR32ri %vreg339<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg339
15312B		%vreg336<def> = MOV32rr %vreg339; GR32:%vreg336,%vreg339
15328B		%vreg337<def> = SUBREG_TO_REG 0, %vreg336, 4; GR64_NOSP:%vreg337 GR32:%vreg336
15344B		%vreg334<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg334
15360B		%vreg333<def> = MOV64rm %vreg334, 1, %noreg, 3168, %noreg; mem:LD8[%ll4503] GR64:%vreg333,%vreg334
15376B		%vreg329<def> = MOVZX32rm8 %vreg333, 1, %vreg337, 0, %noreg; mem:LD1[%arrayidx504] GR32:%vreg329 GR64:%vreg333 GR64_NOSP:%vreg337
15392B		%vreg327<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg327
15408B		%vreg326<def> = MOV32rm %vreg327, 1, %noreg, 60, %noreg; mem:LD4[%tPos506] GR32:%vreg326 GR64:%vreg327
15424B		%vreg324<def> = COPY %vreg326; GR32:%vreg324,%vreg326
15440B		%vreg324<def,tied1> = SHL32ri %vreg324<tied0>, 2, %EFLAGS<imp-def,dead>; GR32:%vreg324
15456B		%vreg322<def> = COPY %vreg324; GR32:%vreg322,%vreg324
15472B		%vreg322<def,tied1> = AND32ri8 %vreg322<tied0>, 4, %EFLAGS<imp-def,dead>; GR32:%vreg322
15488B		%ECX<def> = COPY %vreg322; GR32:%vreg322
15504B		%CL<def> = KILL %ECX<kill>
15520B		%vreg320<def> = COPY %vreg329; GR32:%vreg320,%vreg329
15536B		%vreg320<def,tied1> = SHR32rCL %vreg320<tied0>, %EFLAGS<imp-def,dead>, %CL<imp-use,kill>; GR32:%vreg320
15552B		%vreg317<def> = COPY %vreg320; GR32:%vreg317,%vreg320
15568B		%vreg317<def,tied1> = AND32ri8 %vreg317<tied0>, 15, %EFLAGS<imp-def,dead>; GR32:%vreg317
15584B		%vreg315<def> = COPY %vreg317; GR32:%vreg315,%vreg317
15600B		%vreg315<def,tied1> = SHL32ri %vreg315<tied0>, 16, %EFLAGS<imp-def,dead>; GR32:%vreg315
15616B		%vreg313<def> = COPY %vreg344; GR32:%vreg313,%vreg344
15632B		%vreg313<def,tied1> = OR32rr %vreg313<tied0>, %vreg315, %EFLAGS<imp-def,dead>; GR32:%vreg313,%vreg315
15648B		%vreg310<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg310
15664B		MOV32mr %vreg310, 1, %noreg, 60, %noreg, %vreg313; mem:ST4[%tPos513] GR64:%vreg310 GR32:%vreg313
15680B		%vreg307<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg307
15696B		%vreg306<def> = MOV32rm %vreg307, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used514] GR32:%vreg306 GR64:%vreg307
15712B		%vreg305<def> = COPY %vreg306; GR32:%vreg305,%vreg306
15728B		%vreg305<def,tied1> = ADD32ri8 %vreg305<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg305
15744B		MOV32mr %vreg307, 1, %noreg, 1092, %noreg, %vreg305; mem:ST4[%nblock_used514] GR64:%vreg307 GR32:%vreg305
15760B		%vreg301<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg301
15776B		%vreg300<def> = MOV32rm %vreg301, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used516] GR32:%vreg300 GR64:%vreg301
15792B		%vreg298<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg298
15808B		%vreg297<def> = MOV32rm %vreg298, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock517] GR32:%vreg297 GR64:%vreg298
15824B		%vreg295<def> = COPY %vreg297; GR32:%vreg295,%vreg297
15840B		%vreg295<def,tied1> = ADD32ri8 %vreg295<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg295
15856B		CMP32rr %vreg300, %vreg295, %EFLAGS<imp-def>; GR32:%vreg300,%vreg295
15872B		JNE_1 <BB#70>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#70 BB#69

15888B	BB#69: derived from LLVM BB %if.then.521
	    Predecessors according to CFG: BB#68
15904B		JMP_1 <BB#48>
	    Successors according to CFG: BB#48

15920B	BB#70: derived from LLVM BB %if.end.522
	    Predecessors according to CFG: BB#68
15936B		%vreg375<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg375
15952B		%vreg373<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg373
15968B		CMP32rm %vreg375, %vreg373, 1, %noreg, 64, %noreg, %EFLAGS<imp-def>; mem:LD4[%k0524] GR32:%vreg375 GR64:%vreg373
15984B		JE_1 <BB#72>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#72 BB#71

16000B	BB#71: derived from LLVM BB %if.then.527
	    Predecessors according to CFG: BB#70
16016B		%vreg519<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg519
16032B		%vreg517<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg517
16048B		MOV32mr %vreg517, 1, %noreg, 64, %noreg, %vreg519; mem:ST4[%k0529] GR64:%vreg517 GR32:%vreg519
16064B		JMP_1 <BB#48>
	    Successors according to CFG: BB#48

16080B	BB#72: derived from LLVM BB %if.end.530
	    Predecessors according to CFG: BB#70
16096B		%vreg514<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg514
16112B		%vreg513<def> = MOV32rm %vreg514, 1, %noreg, 60, %noreg; mem:LD4[%tPos531] GR32:%vreg513 GR64:%vreg514
16128B		%vreg511<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg511
16144B		%vreg510<def> = COPY %vreg511; GR64:%vreg510,%vreg511
16160B		%vreg510<def,tied1> = ADD64ri32 %vreg510<tied0>, 1096, %EFLAGS<imp-def,dead>; GR64:%vreg510
16176B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
16192B		%EDI<def> = COPY %vreg513; GR32:%vreg513
16208B		%RSI<def> = COPY %vreg510; GR64:%vreg510
16224B		CALL64pcrel32 <ga:@BZ2_indexIntoF>, <regmask>, %RSP<imp-use>, %EDI<imp-use>, %RSI<imp-use,kill>, %EAX<imp-def>
16240B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
16256B		%vreg507<def> = COPY %EAX<kill>; GR32:%vreg507
16272B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
16288B		STACKMAP 9, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
16304B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
16320B		%vreg504<def> = COPY %vreg507:sub_8bit; GR8:%vreg504 GR32:%vreg507
16336B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg504; mem:ST1[%k1] GR8:%vreg504
16352B		%vreg501<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg501
16368B		%vreg498<def> = MOV32rm %vreg501, 1, %noreg, 60, %noreg; mem:LD4[%tPos536] GR32:%vreg498 GR64:%vreg501
16384B		%vreg499<def> = SUBREG_TO_REG 0, %vreg498, 4; GR64_NOSP:%vreg499 GR32:%vreg498
16400B		%vreg496<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg496
16416B		%vreg495<def> = MOV64rm %vreg496, 1, %noreg, 3160, %noreg; mem:LD8[%ll16538] GR64:%vreg495,%vreg496
16432B		%vreg491<def> = MOVZX32rm16 %vreg495, 2, %vreg499, 0, %noreg; mem:LD2[%arrayidx539] GR32:%vreg491 GR64:%vreg495 GR64_NOSP:%vreg499
16448B		%vreg489<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg489
16464B		%vreg488<def> = MOV32rm %vreg489, 1, %noreg, 60, %noreg; mem:LD4[%tPos541] GR32:%vreg488 GR64:%vreg489
16480B		%vreg486<def> = COPY %vreg488; GR32:%vreg486,%vreg488
16496B		%vreg486<def,tied1> = SHR32ri %vreg486<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg486
16512B		%vreg483<def> = MOV32rr %vreg486; GR32:%vreg483,%vreg486
16528B		%vreg484<def> = SUBREG_TO_REG 0, %vreg483, 4; GR64_NOSP:%vreg484 GR32:%vreg483
16544B		%vreg481<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg481
16560B		%vreg480<def> = MOV64rm %vreg481, 1, %noreg, 3168, %noreg; mem:LD8[%ll4544] GR64:%vreg480,%vreg481
16576B		%vreg476<def> = MOVZX32rm8 %vreg480, 1, %vreg484, 0, %noreg; mem:LD1[%arrayidx545] GR32:%vreg476 GR64:%vreg480 GR64_NOSP:%vreg484
16592B		%vreg474<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg474
16608B		%vreg473<def> = MOV32rm %vreg474, 1, %noreg, 60, %noreg; mem:LD4[%tPos547] GR32:%vreg473 GR64:%vreg474
16624B		%vreg471<def> = COPY %vreg473; GR32:%vreg471,%vreg473
16640B		%vreg471<def,tied1> = SHL32ri %vreg471<tied0>, 2, %EFLAGS<imp-def,dead>; GR32:%vreg471
16656B		%vreg469<def> = COPY %vreg471; GR32:%vreg469,%vreg471
16672B		%vreg469<def,tied1> = AND32ri8 %vreg469<tied0>, 4, %EFLAGS<imp-def,dead>; GR32:%vreg469
16688B		%ECX<def> = COPY %vreg469; GR32:%vreg469
16704B		%CL<def> = KILL %ECX<kill>
16720B		%vreg467<def> = COPY %vreg476; GR32:%vreg467,%vreg476
16736B		%vreg467<def,tied1> = SHR32rCL %vreg467<tied0>, %EFLAGS<imp-def,dead>, %CL<imp-use,kill>; GR32:%vreg467
16752B		%vreg464<def> = COPY %vreg467; GR32:%vreg464,%vreg467
16768B		%vreg464<def,tied1> = AND32ri8 %vreg464<tied0>, 15, %EFLAGS<imp-def,dead>; GR32:%vreg464
16784B		%vreg462<def> = COPY %vreg464; GR32:%vreg462,%vreg464
16800B		%vreg462<def,tied1> = SHL32ri %vreg462<tied0>, 16, %EFLAGS<imp-def,dead>; GR32:%vreg462
16816B		%vreg460<def> = COPY %vreg491; GR32:%vreg460,%vreg491
16832B		%vreg460<def,tied1> = OR32rr %vreg460<tied0>, %vreg462, %EFLAGS<imp-def,dead>; GR32:%vreg460,%vreg462
16848B		%vreg457<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg457
16864B		MOV32mr %vreg457, 1, %noreg, 60, %noreg, %vreg460; mem:ST4[%tPos554] GR64:%vreg457 GR32:%vreg460
16880B		%vreg454<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg454
16896B		%vreg453<def> = MOV32rm %vreg454, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used555] GR32:%vreg453 GR64:%vreg454
16912B		%vreg452<def> = COPY %vreg453; GR32:%vreg452,%vreg453
16928B		%vreg452<def,tied1> = ADD32ri8 %vreg452<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg452
16944B		MOV32mr %vreg454, 1, %noreg, 1092, %noreg, %vreg452; mem:ST4[%nblock_used555] GR64:%vreg454 GR32:%vreg452
16960B		%vreg448<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg448
16976B		%vreg446<def> = COPY %vreg448; GR32:%vreg446,%vreg448
16992B		%vreg446<def,tied1> = ADD32ri8 %vreg446<tied0>, 4, %EFLAGS<imp-def,dead>; GR32:%vreg446
17008B		%vreg444<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg444
17024B		MOV32mr %vreg444, 1, %noreg, 16, %noreg, %vreg446; mem:ST4[%state_out_len559] GR64:%vreg444 GR32:%vreg446
17040B		%vreg441<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg441
17056B		%vreg440<def> = MOV32rm %vreg441, 1, %noreg, 60, %noreg; mem:LD4[%tPos560] GR32:%vreg440 GR64:%vreg441
17072B		%vreg438<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg438
17088B		%vreg437<def> = COPY %vreg438; GR64:%vreg437,%vreg438
17104B		%vreg437<def,tied1> = ADD64ri32 %vreg437<tied0>, 1096, %EFLAGS<imp-def,dead>; GR64:%vreg437
17120B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
17136B		%EDI<def> = COPY %vreg440; GR32:%vreg440
17152B		%RSI<def> = COPY %vreg437; GR64:%vreg437
17168B		CALL64pcrel32 <ga:@BZ2_indexIntoF>, <regmask>, %RSP<imp-use>, %EDI<imp-use>, %RSI<imp-use,kill>, %EAX<imp-def>
17184B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
17200B		%vreg434<def> = COPY %EAX<kill>; GR32:%vreg434
17216B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
17232B		STACKMAP 10, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
17248B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
17264B		%vreg431<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg431
17280B		MOV32mr %vreg431, 1, %noreg, 64, %noreg, %vreg434; mem:ST4[%k0564] GR64:%vreg431 GR32:%vreg434
17296B		%vreg428<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg428
17312B		%vreg425<def> = MOV32rm %vreg428, 1, %noreg, 60, %noreg; mem:LD4[%tPos565] GR32:%vreg425 GR64:%vreg428
17328B		%vreg426<def> = SUBREG_TO_REG 0, %vreg425, 4; GR64_NOSP:%vreg426 GR32:%vreg425
17344B		%vreg423<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg423
17360B		%vreg422<def> = MOV64rm %vreg423, 1, %noreg, 3160, %noreg; mem:LD8[%ll16567] GR64:%vreg422,%vreg423
17376B		%vreg418<def> = MOVZX32rm16 %vreg422, 2, %vreg426, 0, %noreg; mem:LD2[%arrayidx568] GR32:%vreg418 GR64:%vreg422 GR64_NOSP:%vreg426
17392B		%vreg416<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg416
17408B		%vreg415<def> = MOV32rm %vreg416, 1, %noreg, 60, %noreg; mem:LD4[%tPos570] GR32:%vreg415 GR64:%vreg416
17424B		%vreg413<def> = COPY %vreg415; GR32:%vreg413,%vreg415
17440B		%vreg413<def,tied1> = SHR32ri %vreg413<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg413
17456B		%vreg410<def> = MOV32rr %vreg413; GR32:%vreg410,%vreg413
17472B		%vreg411<def> = SUBREG_TO_REG 0, %vreg410, 4; GR64_NOSP:%vreg411 GR32:%vreg410
17488B		%vreg408<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg408
17504B		%vreg407<def> = MOV64rm %vreg408, 1, %noreg, 3168, %noreg; mem:LD8[%ll4573] GR64:%vreg407,%vreg408
17520B		%vreg403<def> = MOVZX32rm8 %vreg407, 1, %vreg411, 0, %noreg; mem:LD1[%arrayidx574] GR32:%vreg403 GR64:%vreg407 GR64_NOSP:%vreg411
17536B		%vreg401<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg401
17552B		%vreg400<def> = MOV32rm %vreg401, 1, %noreg, 60, %noreg; mem:LD4[%tPos576] GR32:%vreg400 GR64:%vreg401
17568B		%vreg398<def> = COPY %vreg400; GR32:%vreg398,%vreg400
17584B		%vreg398<def,tied1> = SHL32ri %vreg398<tied0>, 2, %EFLAGS<imp-def,dead>; GR32:%vreg398
17600B		%vreg396<def> = COPY %vreg398; GR32:%vreg396,%vreg398
17616B		%vreg396<def,tied1> = AND32ri8 %vreg396<tied0>, 4, %EFLAGS<imp-def,dead>; GR32:%vreg396
17632B		%ECX<def> = COPY %vreg396; GR32:%vreg396
17648B		%CL<def> = KILL %ECX<kill>
17664B		%vreg394<def> = COPY %vreg403; GR32:%vreg394,%vreg403
17680B		%vreg394<def,tied1> = SHR32rCL %vreg394<tied0>, %EFLAGS<imp-def,dead>, %CL<imp-use,kill>; GR32:%vreg394
17696B		%vreg391<def> = COPY %vreg394; GR32:%vreg391,%vreg394
17712B		%vreg391<def,tied1> = AND32ri8 %vreg391<tied0>, 15, %EFLAGS<imp-def,dead>; GR32:%vreg391
17728B		%vreg389<def> = COPY %vreg391; GR32:%vreg389,%vreg391
17744B		%vreg389<def,tied1> = SHL32ri %vreg389<tied0>, 16, %EFLAGS<imp-def,dead>; GR32:%vreg389
17760B		%vreg387<def> = COPY %vreg418; GR32:%vreg387,%vreg418
17776B		%vreg387<def,tied1> = OR32rr %vreg387<tied0>, %vreg389, %EFLAGS<imp-def,dead>; GR32:%vreg387,%vreg389
17792B		%vreg384<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg384
17808B		MOV32mr %vreg384, 1, %noreg, 60, %noreg, %vreg387; mem:ST4[%tPos583] GR64:%vreg384 GR32:%vreg387
17824B		%vreg381<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg381
17840B		%vreg380<def> = MOV32rm %vreg381, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used584] GR32:%vreg380 GR64:%vreg381
17856B		%vreg379<def> = COPY %vreg380; GR32:%vreg379,%vreg380
17872B		%vreg379<def,tied1> = ADD32ri8 %vreg379<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg379
17888B		MOV32mr %vreg381, 1, %noreg, 1092, %noreg, %vreg379; mem:ST4[%nblock_used584] GR64:%vreg381 GR32:%vreg379
17904B		JMP_1 <BB#48>
	    Successors according to CFG: BB#48

17920B	BB#73: derived from LLVM BB %return
	    Predecessors according to CFG: BB#59 BB#57 BB#50 BB#13 BB#11 BB#4
17936B		%vreg1267<def> = MOV64ri <ga:@unRLE_obuf_to_output_SMALL>; GR64:%vreg1267
17952B		%vreg1268<def> = COPY %vreg1267; GR64:%vreg1268,%vreg1267
17968B		%vreg1269<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg1269
17984B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
18000B		%RDI<def> = COPY %vreg1268; GR64:%vreg1268
18016B		%RSI<def> = COPY %vreg1269; GR64:%vreg1269
18032B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
18048B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
18064B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
18080B		STACKMAP 11, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=1)
18096B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
18112B		%vreg1266<def> = MOV8rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD1[%retval] GR8:%vreg1266
18128B		%AL<def> = COPY %vreg1266; GR8:%vreg1266
18144B		RETQ %AL<imp-use,kill>

# End machine code for function unRLE_obuf_to_output_SMALL.

********** SIMPLE REGISTER COALESCING **********
********** Function: unRLE_obuf_to_output_SMALL
********** JOINING INTERVALS ***********
while.body.2:
while.body.341:
if.end:
if.end.6:
896B	%vreg582<def> = SUBREG_TO_REG 0, %vreg581, 4; GR64_NOSP:%vreg582 GR32:%vreg581
	Considering merging to GR64_NOSP with %vreg581 in %vreg582:sub_32bit
		RHS = %vreg581 [880r,896r:0)  0@880r
		LHS = %vreg582 [896r,928r:0)  0@896r
		merge %vreg582:0@896r into %vreg581:0@880r --> @880r
		erased:	896r	%vreg582<def> = SUBREG_TO_REG 0, %vreg581, 4; GR64_NOSP:%vreg582 GR32:%vreg581
		updated: 880B	%vreg582:sub_32bit<def,read-undef> = MOV32rr %vreg585; GR64_NOSP:%vreg582 GR32:%vreg585
	Success: %vreg581:sub_32bit -> %vreg582
	Result = %vreg582 [880r,928r:0)  0@880r
if.end.26:
if.end.347:
if.end.352:
11264B	%vreg60<def> = SUBREG_TO_REG 0, %vreg59, 4; GR64_NOSP:%vreg60 GR32:%vreg59
	Considering merging to GR64_NOSP with %vreg59 in %vreg60:sub_32bit
		RHS = %vreg59 [11248r,11264r:0)  0@11248r
		LHS = %vreg60 [11264r,11296r:0)  0@11264r
		merge %vreg60:0@11264r into %vreg59:0@11248r --> @11248r
		erased:	11264r	%vreg60<def> = SUBREG_TO_REG 0, %vreg59, 4; GR64_NOSP:%vreg60 GR32:%vreg59
		updated: 11248B	%vreg60:sub_32bit<def,read-undef> = MOV32rr %vreg63; GR64_NOSP:%vreg60 GR32:%vreg63
	Success: %vreg59:sub_32bit -> %vreg60
	Result = %vreg60 [11248r,11296r:0)  0@11248r
if.end.386:
if.then.23:
if.then.382:
720B	%vreg596<def> = COPY %vreg598; GR32:%vreg596,%vreg598
	Considering merging to GR32 with %vreg598 in %vreg596
		RHS = %vreg598 [704r,720r:0)  0@704r
		LHS = %vreg596 [720r,736r:0)[736r,912r:1)  0@720r 1@736r
		merge %vreg596:0@720r into %vreg598:0@704r --> @704r
		erased:	720r	%vreg596<def> = COPY %vreg598; GR32:%vreg596,%vreg598
		updated: 704B	%vreg596<def> = MOV32rm %vreg599, 1, %noreg, 3184, %noreg; mem:LD4[%calculatedBlockCRC] GR32:%vreg596 GR64:%vreg599
	Success: %vreg598 -> %vreg596
	Result = %vreg596 [704r,736r:0)[736r,912r:1)  0@704r 1@736r
784B	%vreg591<def> = COPY %vreg593; GR32:%vreg591,%vreg593
	Considering merging to GR32 with %vreg593 in %vreg591
		RHS = %vreg593 [768r,784r:0)  0@768r
		LHS = %vreg591 [784r,800r:0)[800r,848r:1)  0@784r 1@800r
		merge %vreg591:0@784r into %vreg593:0@768r --> @768r
		erased:	784r	%vreg591<def> = COPY %vreg593; GR32:%vreg591,%vreg593
		updated: 768B	%vreg591<def> = MOV32rm %vreg594, 1, %noreg, 3184, %noreg; mem:LD4[%calculatedBlockCRC8] GR32:%vreg591 GR64:%vreg594
	Success: %vreg593 -> %vreg591
	Result = %vreg591 [768r,800r:0)[800r,848r:1)  0@768r 1@800r
848B	%vreg585<def> = COPY %vreg591; GR32:%vreg585,%vreg591
	Considering merging to GR32 with %vreg591 in %vreg585
		RHS = %vreg591 [768r,800r:0)[800r,848r:1)  0@768r 1@800r
		LHS = %vreg585 [848r,864r:0)[864r,880r:1)  0@848r 1@864r
		merge %vreg585:0@848r into %vreg591:1@800r --> @800r
		erased:	848r	%vreg585<def> = COPY %vreg591; GR32:%vreg585,%vreg591
		updated: 768B	%vreg585<def> = MOV32rm %vreg594, 1, %noreg, 3184, %noreg; mem:LD4[%calculatedBlockCRC8] GR32:%vreg585 GR64:%vreg594
		updated: 800B	%vreg585<def,tied1> = SHR32ri %vreg585<tied0>, 24, %EFLAGS<imp-def,dead>; GR32:%vreg585
	Success: %vreg591 -> %vreg585
	Result = %vreg585 [768r,800r:2)[800r,864r:0)[864r,880r:1)  0@800r 1@864r 2@768r
912B	%vreg578<def> = COPY %vreg596; GR32:%vreg578,%vreg596
	Considering merging to GR32 with %vreg596 in %vreg578
		RHS = %vreg596 [704r,736r:0)[736r,912r:1)  0@704r 1@736r
		LHS = %vreg578 [912r,928r:0)[928r,960r:1)  0@912r 1@928r
		merge %vreg578:0@912r into %vreg596:1@736r --> @736r
		erased:	912r	%vreg578<def> = COPY %vreg596; GR32:%vreg578,%vreg596
		updated: 704B	%vreg578<def> = MOV32rm %vreg599, 1, %noreg, 3184, %noreg; mem:LD4[%calculatedBlockCRC] GR32:%vreg578 GR64:%vreg599
		updated: 736B	%vreg578<def,tied1> = SHL32ri %vreg578<tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg578
	Success: %vreg596 -> %vreg578
	Result = %vreg578 [704r,736r:2)[736r,928r:0)[928r,960r:1)  0@736r 1@928r 2@704r
1008B	%vreg570<def> = COPY %vreg571; GR32:%vreg570,%vreg571
	Considering merging to GR32 with %vreg571 in %vreg570
		RHS = %vreg571 [992r,1008r:0)  0@992r
		LHS = %vreg570 [1008r,1024r:0)[1024r,1040r:1)  0@1008r 1@1024r
		merge %vreg570:0@1008r into %vreg571:0@992r --> @992r
		erased:	1008r	%vreg570<def> = COPY %vreg571; GR32:%vreg570,%vreg571
		updated: 992B	%vreg570<def> = MOV32rm %vreg572, 1, %noreg, 16, %noreg; mem:LD4[%state_out_len12] GR32:%vreg570 GR64:%vreg572
	Success: %vreg571 -> %vreg570
	Result = %vreg570 [992r,1024r:0)[1024r,1040r:1)  0@992r 1@1024r
1104B	%vreg562<def> = COPY %vreg563; GR64:%vreg562,%vreg563
	Considering merging to GR64 with %vreg563 in %vreg562
		RHS = %vreg563 [1088r,1104r:0)  0@1088r
		LHS = %vreg562 [1104r,1120r:0)[1120r,1136r:1)  0@1104r 1@1120r
		merge %vreg562:0@1104r into %vreg563:0@1088r --> @1088r
		erased:	1104r	%vreg562<def> = COPY %vreg563; GR64:%vreg562,%vreg563
		updated: 1088B	%vreg562<def> = MOV64rm %vreg565, 1, %noreg, 24, %noreg; mem:LD8[%next_out14] GR64:%vreg562,%vreg565
	Success: %vreg563 -> %vreg562
	Result = %vreg562 [1088r,1120r:0)[1120r,1136r:1)  0@1088r 1@1120r
1200B	%vreg554<def> = COPY %vreg555; GR32:%vreg554,%vreg555
	Considering merging to GR32 with %vreg555 in %vreg554
		RHS = %vreg555 [1184r,1200r:0)  0@1184r
		LHS = %vreg554 [1200r,1216r:0)[1216r,1232r:1)  0@1200r 1@1216r
		merge %vreg554:0@1200r into %vreg555:0@1184r --> @1184r
		erased:	1200r	%vreg554<def> = COPY %vreg555; GR32:%vreg554,%vreg555
		updated: 1184B	%vreg554<def> = MOV32rm %vreg557, 1, %noreg, 32, %noreg; mem:LD4[%avail_out16] GR32:%vreg554 GR64:%vreg557
	Success: %vreg555 -> %vreg554
	Result = %vreg554 [1184r,1216r:0)[1216r,1232r:1)  0@1184r 1@1216r
1296B	%vreg546<def> = COPY %vreg547; GR32:%vreg546,%vreg547
	Considering merging to GR32 with %vreg547 in %vreg546
		RHS = %vreg547 [1280r,1296r:0)  0@1280r
		LHS = %vreg546 [1296r,1312r:0)[1312r,1328r:1)  0@1296r 1@1312r
		merge %vreg546:0@1296r into %vreg547:0@1280r --> @1280r
		erased:	1296r	%vreg546<def> = COPY %vreg547; GR32:%vreg546,%vreg547
		updated: 1280B	%vreg546<def> = MOV32rm %vreg549, 1, %noreg, 36, %noreg; mem:LD4[%total_out_lo32] GR32:%vreg546 GR64:%vreg549
	Success: %vreg547 -> %vreg546
	Result = %vreg546 [1280r,1312r:0)[1312r,1328r:1)  0@1280r 1@1312r
11088B	%vreg74<def> = COPY %vreg76; GR32:%vreg74,%vreg76
	Considering merging to GR32 with %vreg76 in %vreg74
		RHS = %vreg76 [11072r,11088r:0)  0@11072r
		LHS = %vreg74 [11088r,11104r:0)[11104r,11280r:1)  0@11088r 1@11104r
		merge %vreg74:0@11088r into %vreg76:0@11072r --> @11072r
		erased:	11088r	%vreg74<def> = COPY %vreg76; GR32:%vreg74,%vreg76
		updated: 11072B	%vreg74<def> = MOV32rm %vreg77, 1, %noreg, 3184, %noreg; mem:LD4[%calculatedBlockCRC356] GR32:%vreg74 GR64:%vreg77
	Success: %vreg76 -> %vreg74
	Result = %vreg74 [11072r,11104r:0)[11104r,11280r:1)  0@11072r 1@11104r
11152B	%vreg69<def> = COPY %vreg71; GR32:%vreg69,%vreg71
	Considering merging to GR32 with %vreg71 in %vreg69
		RHS = %vreg71 [11136r,11152r:0)  0@11136r
		LHS = %vreg69 [11152r,11168r:0)[11168r,11216r:1)  0@11152r 1@11168r
		merge %vreg69:0@11152r into %vreg71:0@11136r --> @11136r
		erased:	11152r	%vreg69<def> = COPY %vreg71; GR32:%vreg69,%vreg71
		updated: 11136B	%vreg69<def> = MOV32rm %vreg72, 1, %noreg, 3184, %noreg; mem:LD4[%calculatedBlockCRC358] GR32:%vreg69 GR64:%vreg72
	Success: %vreg71 -> %vreg69
	Result = %vreg69 [11136r,11168r:0)[11168r,11216r:1)  0@11136r 1@11168r
11216B	%vreg63<def> = COPY %vreg69; GR32:%vreg63,%vreg69
	Considering merging to GR32 with %vreg69 in %vreg63
		RHS = %vreg69 [11136r,11168r:0)[11168r,11216r:1)  0@11136r 1@11168r
		LHS = %vreg63 [11216r,11232r:0)[11232r,11248r:1)  0@11216r 1@11232r
		merge %vreg63:0@11216r into %vreg69:1@11168r --> @11168r
		erased:	11216r	%vreg63<def> = COPY %vreg69; GR32:%vreg63,%vreg69
		updated: 11136B	%vreg63<def> = MOV32rm %vreg72, 1, %noreg, 3184, %noreg; mem:LD4[%calculatedBlockCRC358] GR32:%vreg63 GR64:%vreg72
		updated: 11168B	%vreg63<def,tied1> = SHR32ri %vreg63<tied0>, 24, %EFLAGS<imp-def,dead>; GR32:%vreg63
	Success: %vreg69 -> %vreg63
	Result = %vreg63 [11136r,11168r:2)[11168r,11232r:0)[11232r,11248r:1)  0@11168r 1@11232r 2@11136r
11280B	%vreg56<def> = COPY %vreg74; GR32:%vreg56,%vreg74
	Considering merging to GR32 with %vreg74 in %vreg56
		RHS = %vreg74 [11072r,11104r:0)[11104r,11280r:1)  0@11072r 1@11104r
		LHS = %vreg56 [11280r,11296r:0)[11296r,11328r:1)  0@11280r 1@11296r
		merge %vreg56:0@11280r into %vreg74:1@11104r --> @11104r
		erased:	11280r	%vreg56<def> = COPY %vreg74; GR32:%vreg56,%vreg74
		updated: 11072B	%vreg56<def> = MOV32rm %vreg77, 1, %noreg, 3184, %noreg; mem:LD4[%calculatedBlockCRC356] GR32:%vreg56 GR64:%vreg77
		updated: 11104B	%vreg56<def,tied1> = SHL32ri %vreg56<tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg56
	Success: %vreg74 -> %vreg56
	Result = %vreg56 [11072r,11104r:2)[11104r,11296r:0)[11296r,11328r:1)  0@11104r 1@11296r 2@11072r
11376B	%vreg48<def> = COPY %vreg49; GR32:%vreg48,%vreg49
	Considering merging to GR32 with %vreg49 in %vreg48
		RHS = %vreg49 [11360r,11376r:0)  0@11360r
		LHS = %vreg48 [11376r,11392r:0)[11392r,11408r:1)  0@11376r 1@11392r
		merge %vreg48:0@11376r into %vreg49:0@11360r --> @11360r
		erased:	11376r	%vreg48<def> = COPY %vreg49; GR32:%vreg48,%vreg49
		updated: 11360B	%vreg48<def> = MOV32rm %vreg50, 1, %noreg, 16, %noreg; mem:LD4[%state_out_len367] GR32:%vreg48 GR64:%vreg50
	Success: %vreg49 -> %vreg48
	Result = %vreg48 [11360r,11392r:0)[11392r,11408r:1)  0@11360r 1@11392r
11472B	%vreg40<def> = COPY %vreg41; GR64:%vreg40,%vreg41
	Considering merging to GR64 with %vreg41 in %vreg40
		RHS = %vreg41 [11456r,11472r:0)  0@11456r
		LHS = %vreg40 [11472r,11488r:0)[11488r,11504r:1)  0@11472r 1@11488r
		merge %vreg40:0@11472r into %vreg41:0@11456r --> @11456r
		erased:	11472r	%vreg40<def> = COPY %vreg41; GR64:%vreg40,%vreg41
		updated: 11456B	%vreg40<def> = MOV64rm %vreg43, 1, %noreg, 24, %noreg; mem:LD8[%next_out370] GR64:%vreg40,%vreg43
	Success: %vreg41 -> %vreg40
	Result = %vreg40 [11456r,11488r:0)[11488r,11504r:1)  0@11456r 1@11488r
11568B	%vreg32<def> = COPY %vreg33; GR32:%vreg32,%vreg33
	Considering merging to GR32 with %vreg33 in %vreg32
		RHS = %vreg33 [11552r,11568r:0)  0@11552r
		LHS = %vreg32 [11568r,11584r:0)[11584r,11600r:1)  0@11568r 1@11584r
		merge %vreg32:0@11568r into %vreg33:0@11552r --> @11552r
		erased:	11568r	%vreg32<def> = COPY %vreg33; GR32:%vreg32,%vreg33
		updated: 11552B	%vreg32<def> = MOV32rm %vreg35, 1, %noreg, 32, %noreg; mem:LD4[%avail_out373] GR32:%vreg32 GR64:%vreg35
	Success: %vreg33 -> %vreg32
	Result = %vreg32 [11552r,11584r:0)[11584r,11600r:1)  0@11552r 1@11584r
11664B	%vreg24<def> = COPY %vreg25; GR32:%vreg24,%vreg25
	Considering merging to GR32 with %vreg25 in %vreg24
		RHS = %vreg25 [11648r,11664r:0)  0@11648r
		LHS = %vreg24 [11664r,11680r:0)[11680r,11696r:1)  0@11664r 1@11680r
		merge %vreg24:0@11664r into %vreg25:0@11648r --> @11648r
		erased:	11664r	%vreg24<def> = COPY %vreg25; GR32:%vreg24,%vreg25
		updated: 11648B	%vreg24<def> = MOV32rm %vreg27, 1, %noreg, 36, %noreg; mem:LD4[%total_out_lo32376] GR32:%vreg24 GR64:%vreg27
	Success: %vreg25 -> %vreg24
	Result = %vreg24 [11648r,11680r:0)[11680r,11696r:1)  0@11648r 1@11680r
1472B	%vreg613<def> = COPY %vreg614; GR32:%vreg613,%vreg614
	Considering merging to GR32 with %vreg614 in %vreg613
		RHS = %vreg614 [1456r,1472r:0)  0@1456r
		LHS = %vreg613 [1472r,1488r:0)[1488r,1504r:1)  0@1472r 1@1488r
		merge %vreg613:0@1472r into %vreg614:0@1456r --> @1456r
		erased:	1472r	%vreg613<def> = COPY %vreg614; GR32:%vreg613,%vreg614
		updated: 1456B	%vreg613<def> = MOV32rm %vreg616, 1, %noreg, 40, %noreg; mem:LD4[%total_out_hi32] GR32:%vreg613 GR64:%vreg616
	Success: %vreg614 -> %vreg613
	Result = %vreg613 [1456r,1488r:0)[1488r,1504r:1)  0@1456r 1@1488r
11840B	%vreg91<def> = COPY %vreg92; GR32:%vreg91,%vreg92
	Considering merging to GR32 with %vreg92 in %vreg91
		RHS = %vreg92 [11824r,11840r:0)  0@11824r
		LHS = %vreg91 [11840r,11856r:0)[11856r,11872r:1)  0@11840r 1@11856r
		merge %vreg91:0@11840r into %vreg92:0@11824r --> @11824r
		erased:	11840r	%vreg91<def> = COPY %vreg92; GR32:%vreg91,%vreg92
		updated: 11824B	%vreg91<def> = MOV32rm %vreg94, 1, %noreg, 40, %noreg; mem:LD4[%total_out_hi32384] GR32:%vreg91 GR64:%vreg94
	Success: %vreg92 -> %vreg91
	Result = %vreg91 [11824r,11856r:0)[11856r,11872r:1)  0@11824r 1@11856r
while.body:
while.body.339:
if.end.71:
if.end.138:
if.end.206:
if.end.273:
9264B	%EDI<def> = COPY %vreg1171; GR32:%vreg1171
	Considering merging %vreg1171 with %EDI
	Can only merge into reserved registers.
9280B	%RSI<def> = COPY %vreg1168; GR64:%vreg1168
	Considering merging %vreg1168 with %RSI
	Can only merge into reserved registers.
9328B	%vreg1165<def> = COPY %EAX<kill>; GR32:%vreg1165
	Considering merging %vreg1165 with %EAX
	Can only merge into reserved registers.
9456B	%vreg1157<def> = SUBREG_TO_REG 0, %vreg1156, 4; GR64_NOSP:%vreg1157 GR32:%vreg1156
	Considering merging to GR64_NOSP with %vreg1156 in %vreg1157:sub_32bit
		RHS = %vreg1156 [9440r,9456r:0)  0@9440r
		LHS = %vreg1157 [9456r,9504r:0)  0@9456r
		merge %vreg1157:0@9456r into %vreg1156:0@9440r --> @9440r
		erased:	9456r	%vreg1157<def> = SUBREG_TO_REG 0, %vreg1156, 4; GR64_NOSP:%vreg1157 GR32:%vreg1156
		updated: 9440B	%vreg1157:sub_32bit<def,read-undef> = MOV32rm %vreg1159, 1, %noreg, 60, %noreg; mem:LD4[%tPos293] GR64_NOSP:%vreg1157 GR64:%vreg1159
	Success: %vreg1156:sub_32bit -> %vreg1157
	Result = %vreg1157 [9440r,9504r:0)  0@9440r
9600B	%vreg1142<def> = SUBREG_TO_REG 0, %vreg1141, 4; GR64_NOSP:%vreg1142 GR32:%vreg1141
	Considering merging to GR64_NOSP with %vreg1141 in %vreg1142:sub_32bit
		RHS = %vreg1141 [9584r,9600r:0)  0@9584r
		LHS = %vreg1142 [9600r,9648r:0)  0@9600r
		merge %vreg1142:0@9600r into %vreg1141:0@9584r --> @9584r
		erased:	9600r	%vreg1142<def> = SUBREG_TO_REG 0, %vreg1141, 4; GR64_NOSP:%vreg1142 GR32:%vreg1141
		updated: 9584B	%vreg1142:sub_32bit<def,read-undef> = MOV32rr %vreg1144; GR64_NOSP:%vreg1142 GR32:%vreg1144
	Success: %vreg1141:sub_32bit -> %vreg1142
	Result = %vreg1142 [9584r,9648r:0)  0@9584r
9760B	%ECX<def> = COPY %vreg1127; GR32:%vreg1127
	Considering merging %vreg1127 with %ECX
	Can only merge into reserved registers.
while.end:
if.end.30:
if.end.37:
2160B	%EDI<def> = COPY %vreg699; GR32:%vreg699
	Considering merging %vreg699 with %EDI
	Can only merge into reserved registers.
2176B	%RSI<def> = COPY %vreg696; GR64:%vreg696
	Considering merging %vreg696 with %RSI
	Can only merge into reserved registers.
2224B	%vreg693<def> = COPY %EAX<kill>; GR32:%vreg693
	Considering merging %vreg693 with %EAX
	Can only merge into reserved registers.
2352B	%vreg685<def> = SUBREG_TO_REG 0, %vreg684, 4; GR64_NOSP:%vreg685 GR32:%vreg684
	Considering merging to GR64_NOSP with %vreg684 in %vreg685:sub_32bit
		RHS = %vreg684 [2336r,2352r:0)  0@2336r
		LHS = %vreg685 [2352r,2400r:0)  0@2352r
		merge %vreg685:0@2352r into %vreg684:0@2336r --> @2336r
		erased:	2352r	%vreg685<def> = SUBREG_TO_REG 0, %vreg684, 4; GR64_NOSP:%vreg685 GR32:%vreg684
		updated: 2336B	%vreg685:sub_32bit<def,read-undef> = MOV32rm %vreg687, 1, %noreg, 60, %noreg; mem:LD4[%tPos42] GR64_NOSP:%vreg685 GR64:%vreg687
	Success: %vreg684:sub_32bit -> %vreg685
	Result = %vreg685 [2336r,2400r:0)  0@2336r
2496B	%vreg670<def> = SUBREG_TO_REG 0, %vreg669, 4; GR64_NOSP:%vreg670 GR32:%vreg669
	Considering merging to GR64_NOSP with %vreg669 in %vreg670:sub_32bit
		RHS = %vreg669 [2480r,2496r:0)  0@2480r
		LHS = %vreg670 [2496r,2544r:0)  0@2496r
		merge %vreg670:0@2496r into %vreg669:0@2480r --> @2480r
		erased:	2496r	%vreg670<def> = SUBREG_TO_REG 0, %vreg669, 4; GR64_NOSP:%vreg670 GR32:%vreg669
		updated: 2480B	%vreg670:sub_32bit<def,read-undef> = MOV32rr %vreg672; GR64_NOSP:%vreg670 GR32:%vreg672
	Success: %vreg669:sub_32bit -> %vreg670
	Result = %vreg670 [2480r,2544r:0)  0@2480r
2656B	%ECX<def> = COPY %vreg655; GR32:%vreg655
	Considering merging %vreg655 with %ECX
	Can only merge into reserved registers.
if.then.59:
if.end.70:
if.end.88:
if.end.96:
4016B	%EDI<def> = COPY %vreg834; GR32:%vreg834
	Considering merging %vreg834 with %EDI
	Can only merge into reserved registers.
4032B	%RSI<def> = COPY %vreg831; GR64:%vreg831
	Considering merging %vreg831 with %RSI
	Can only merge into reserved registers.
4080B	%vreg828<def> = COPY %EAX<kill>; GR32:%vreg828
	Considering merging %vreg828 with %EAX
	Can only merge into reserved registers.
4208B	%vreg820<def> = SUBREG_TO_REG 0, %vreg819, 4; GR64_NOSP:%vreg820 GR32:%vreg819
	Considering merging to GR64_NOSP with %vreg819 in %vreg820:sub_32bit
		RHS = %vreg819 [4192r,4208r:0)  0@4192r
		LHS = %vreg820 [4208r,4256r:0)  0@4208r
		merge %vreg820:0@4208r into %vreg819:0@4192r --> @4192r
		erased:	4208r	%vreg820<def> = SUBREG_TO_REG 0, %vreg819, 4; GR64_NOSP:%vreg820 GR32:%vreg819
		updated: 4192B	%vreg820:sub_32bit<def,read-undef> = MOV32rm %vreg822, 1, %noreg, 60, %noreg; mem:LD4[%tPos103] GR64_NOSP:%vreg820 GR64:%vreg822
	Success: %vreg819:sub_32bit -> %vreg820
	Result = %vreg820 [4192r,4256r:0)  0@4192r
4352B	%vreg805<def> = SUBREG_TO_REG 0, %vreg804, 4; GR64_NOSP:%vreg805 GR32:%vreg804
	Considering merging to GR64_NOSP with %vreg804 in %vreg805:sub_32bit
		RHS = %vreg804 [4336r,4352r:0)  0@4336r
		LHS = %vreg805 [4352r,4400r:0)  0@4352r
		merge %vreg805:0@4352r into %vreg804:0@4336r --> @4336r
		erased:	4352r	%vreg805<def> = SUBREG_TO_REG 0, %vreg804, 4; GR64_NOSP:%vreg805 GR32:%vreg804
		updated: 4336B	%vreg805:sub_32bit<def,read-undef> = MOV32rr %vreg807; GR64_NOSP:%vreg805 GR32:%vreg807
	Success: %vreg804:sub_32bit -> %vreg805
	Result = %vreg805 [4336r,4400r:0)  0@4336r
4512B	%ECX<def> = COPY %vreg790; GR32:%vreg790
	Considering merging %vreg790 with %ECX
	Can only merge into reserved registers.
if.then.125:
if.end.137:
if.end.156:
if.end.164:
5872B	%EDI<def> = COPY %vreg961; GR32:%vreg961
	Considering merging %vreg961 with %EDI
	Can only merge into reserved registers.
5888B	%RSI<def> = COPY %vreg958; GR64:%vreg958
	Considering merging %vreg958 with %RSI
	Can only merge into reserved registers.
5936B	%vreg955<def> = COPY %EAX<kill>; GR32:%vreg955
	Considering merging %vreg955 with %EAX
	Can only merge into reserved registers.
6064B	%vreg947<def> = SUBREG_TO_REG 0, %vreg946, 4; GR64_NOSP:%vreg947 GR32:%vreg946
	Considering merging to GR64_NOSP with %vreg946 in %vreg947:sub_32bit
		RHS = %vreg946 [6048r,6064r:0)  0@6048r
		LHS = %vreg947 [6064r,6112r:0)  0@6064r
		merge %vreg947:0@6064r into %vreg946:0@6048r --> @6048r
		erased:	6064r	%vreg947<def> = SUBREG_TO_REG 0, %vreg946, 4; GR64_NOSP:%vreg947 GR32:%vreg946
		updated: 6048B	%vreg947:sub_32bit<def,read-undef> = MOV32rm %vreg949, 1, %noreg, 60, %noreg; mem:LD4[%tPos171] GR64_NOSP:%vreg947 GR64:%vreg949
	Success: %vreg946:sub_32bit -> %vreg947
	Result = %vreg947 [6048r,6112r:0)  0@6048r
6208B	%vreg932<def> = SUBREG_TO_REG 0, %vreg931, 4; GR64_NOSP:%vreg932 GR32:%vreg931
	Considering merging to GR64_NOSP with %vreg931 in %vreg932:sub_32bit
		RHS = %vreg931 [6192r,6208r:0)  0@6192r
		LHS = %vreg932 [6208r,6256r:0)  0@6208r
		merge %vreg932:0@6208r into %vreg931:0@6192r --> @6192r
		erased:	6208r	%vreg932<def> = SUBREG_TO_REG 0, %vreg931, 4; GR64_NOSP:%vreg932 GR32:%vreg931
		updated: 6192B	%vreg932:sub_32bit<def,read-undef> = MOV32rr %vreg934; GR64_NOSP:%vreg932 GR32:%vreg934
	Success: %vreg931:sub_32bit -> %vreg932
	Result = %vreg932 [6192r,6256r:0)  0@6192r
6368B	%ECX<def> = COPY %vreg917; GR32:%vreg917
	Considering merging %vreg917 with %ECX
	Can only merge into reserved registers.
if.then.193:
if.end.205:
if.end.224:
if.end.232:
7696B	%EDI<def> = COPY %vreg1088; GR32:%vreg1088
	Considering merging %vreg1088 with %EDI
	Can only merge into reserved registers.
7712B	%RSI<def> = COPY %vreg1085; GR64:%vreg1085
	Considering merging %vreg1085 with %RSI
	Can only merge into reserved registers.
7760B	%vreg1082<def> = COPY %EAX<kill>; GR32:%vreg1082
	Considering merging %vreg1082 with %EAX
	Can only merge into reserved registers.
7888B	%vreg1074<def> = SUBREG_TO_REG 0, %vreg1073, 4; GR64_NOSP:%vreg1074 GR32:%vreg1073
	Considering merging to GR64_NOSP with %vreg1073 in %vreg1074:sub_32bit
		RHS = %vreg1073 [7872r,7888r:0)  0@7872r
		LHS = %vreg1074 [7888r,7936r:0)  0@7888r
		merge %vreg1074:0@7888r into %vreg1073:0@7872r --> @7872r
		erased:	7888r	%vreg1074<def> = SUBREG_TO_REG 0, %vreg1073, 4; GR64_NOSP:%vreg1074 GR32:%vreg1073
		updated: 7872B	%vreg1074:sub_32bit<def,read-undef> = MOV32rm %vreg1076, 1, %noreg, 60, %noreg; mem:LD4[%tPos238] GR64_NOSP:%vreg1074 GR64:%vreg1076
	Success: %vreg1073:sub_32bit -> %vreg1074
	Result = %vreg1074 [7872r,7936r:0)  0@7872r
8032B	%vreg1059<def> = SUBREG_TO_REG 0, %vreg1058, 4; GR64_NOSP:%vreg1059 GR32:%vreg1058
	Considering merging to GR64_NOSP with %vreg1058 in %vreg1059:sub_32bit
		RHS = %vreg1058 [8016r,8032r:0)  0@8016r
		LHS = %vreg1059 [8032r,8080r:0)  0@8032r
		merge %vreg1059:0@8032r into %vreg1058:0@8016r --> @8016r
		erased:	8032r	%vreg1059<def> = SUBREG_TO_REG 0, %vreg1058, 4; GR64_NOSP:%vreg1059 GR32:%vreg1058
		updated: 8016B	%vreg1059:sub_32bit<def,read-undef> = MOV32rr %vreg1061; GR64_NOSP:%vreg1059 GR32:%vreg1061
	Success: %vreg1058:sub_32bit -> %vreg1059
	Result = %vreg1059 [8016r,8080r:0)  0@8016r
8192B	%ECX<def> = COPY %vreg1044; GR32:%vreg1044
	Considering merging %vreg1044 with %ECX
	Can only merge into reserved registers.
if.then.260:
if.end.272:
if.then.315:
if.end.327:
if.end.328:
while.end.387:
if.end.394:
if.end.401:
12528B	%EDI<def> = COPY %vreg190; GR32:%vreg190
	Considering merging %vreg190 with %EDI
	Can only merge into reserved registers.
12544B	%RSI<def> = COPY %vreg187; GR64:%vreg187
	Considering merging %vreg187 with %RSI
	Can only merge into reserved registers.
12592B	%vreg184<def> = COPY %EAX<kill>; GR32:%vreg184
	Considering merging %vreg184 with %EAX
	Can only merge into reserved registers.
12720B	%vreg176<def> = SUBREG_TO_REG 0, %vreg175, 4; GR64_NOSP:%vreg176 GR32:%vreg175
	Considering merging to GR64_NOSP with %vreg175 in %vreg176:sub_32bit
		RHS = %vreg175 [12704r,12720r:0)  0@12704r
		LHS = %vreg176 [12720r,12768r:0)  0@12720r
		merge %vreg176:0@12720r into %vreg175:0@12704r --> @12704r
		erased:	12720r	%vreg176<def> = SUBREG_TO_REG 0, %vreg175, 4; GR64_NOSP:%vreg176 GR32:%vreg175
		updated: 12704B	%vreg176:sub_32bit<def,read-undef> = MOV32rm %vreg178, 1, %noreg, 60, %noreg; mem:LD4[%tPos411] GR64_NOSP:%vreg176 GR64:%vreg178
	Success: %vreg175:sub_32bit -> %vreg176
	Result = %vreg176 [12704r,12768r:0)  0@12704r
12864B	%vreg161<def> = SUBREG_TO_REG 0, %vreg160, 4; GR64_NOSP:%vreg161 GR32:%vreg160
	Considering merging to GR64_NOSP with %vreg160 in %vreg161:sub_32bit
		RHS = %vreg160 [12848r,12864r:0)  0@12848r
		LHS = %vreg161 [12864r,12912r:0)  0@12864r
		merge %vreg161:0@12864r into %vreg160:0@12848r --> @12848r
		erased:	12864r	%vreg161<def> = SUBREG_TO_REG 0, %vreg160, 4; GR64_NOSP:%vreg161 GR32:%vreg160
		updated: 12848B	%vreg161:sub_32bit<def,read-undef> = MOV32rr %vreg163; GR64_NOSP:%vreg161 GR32:%vreg163
	Success: %vreg160:sub_32bit -> %vreg161
	Result = %vreg161 [12848r,12912r:0)  0@12848r
13024B	%ECX<def> = COPY %vreg146; GR32:%vreg146
	Considering merging %vreg146 with %ECX
	Can only merge into reserved registers.
if.end.438:
if.end.446:
13760B	%EDI<def> = COPY %vreg282; GR32:%vreg282
	Considering merging %vreg282 with %EDI
	Can only merge into reserved registers.
13776B	%RSI<def> = COPY %vreg279; GR64:%vreg279
	Considering merging %vreg279 with %RSI
	Can only merge into reserved registers.
13824B	%vreg276<def> = COPY %EAX<kill>; GR32:%vreg276
	Considering merging %vreg276 with %EAX
	Can only merge into reserved registers.
13952B	%vreg268<def> = SUBREG_TO_REG 0, %vreg267, 4; GR64_NOSP:%vreg268 GR32:%vreg267
	Considering merging to GR64_NOSP with %vreg267 in %vreg268:sub_32bit
		RHS = %vreg267 [13936r,13952r:0)  0@13936r
		LHS = %vreg268 [13952r,14000r:0)  0@13952r
		merge %vreg268:0@13952r into %vreg267:0@13936r --> @13936r
		erased:	13952r	%vreg268<def> = SUBREG_TO_REG 0, %vreg267, 4; GR64_NOSP:%vreg268 GR32:%vreg267
		updated: 13936B	%vreg268:sub_32bit<def,read-undef> = MOV32rm %vreg270, 1, %noreg, 60, %noreg; mem:LD4[%tPos453] GR64_NOSP:%vreg268 GR64:%vreg270
	Success: %vreg267:sub_32bit -> %vreg268
	Result = %vreg268 [13936r,14000r:0)  0@13936r
14096B	%vreg253<def> = SUBREG_TO_REG 0, %vreg252, 4; GR64_NOSP:%vreg253 GR32:%vreg252
	Considering merging to GR64_NOSP with %vreg252 in %vreg253:sub_32bit
		RHS = %vreg252 [14080r,14096r:0)  0@14080r
		LHS = %vreg253 [14096r,14144r:0)  0@14096r
		merge %vreg253:0@14096r into %vreg252:0@14080r --> @14080r
		erased:	14096r	%vreg253<def> = SUBREG_TO_REG 0, %vreg252, 4; GR64_NOSP:%vreg253 GR32:%vreg252
		updated: 14080B	%vreg253:sub_32bit<def,read-undef> = MOV32rr %vreg255; GR64_NOSP:%vreg253 GR32:%vreg255
	Success: %vreg252:sub_32bit -> %vreg253
	Result = %vreg253 [14080r,14144r:0)  0@14080r
14256B	%ECX<def> = COPY %vreg238; GR32:%vreg238
	Considering merging %vreg238 with %ECX
	Can only merge into reserved registers.
if.end.480:
if.end.488:
14992B	%EDI<def> = COPY %vreg366; GR32:%vreg366
	Considering merging %vreg366 with %EDI
	Can only merge into reserved registers.
15008B	%RSI<def> = COPY %vreg363; GR64:%vreg363
	Considering merging %vreg363 with %RSI
	Can only merge into reserved registers.
15056B	%vreg360<def> = COPY %EAX<kill>; GR32:%vreg360
	Considering merging %vreg360 with %EAX
	Can only merge into reserved registers.
15184B	%vreg352<def> = SUBREG_TO_REG 0, %vreg351, 4; GR64_NOSP:%vreg352 GR32:%vreg351
	Considering merging to GR64_NOSP with %vreg351 in %vreg352:sub_32bit
		RHS = %vreg351 [15168r,15184r:0)  0@15168r
		LHS = %vreg352 [15184r,15232r:0)  0@15184r
		merge %vreg352:0@15184r into %vreg351:0@15168r --> @15168r
		erased:	15184r	%vreg352<def> = SUBREG_TO_REG 0, %vreg351, 4; GR64_NOSP:%vreg352 GR32:%vreg351
		updated: 15168B	%vreg352:sub_32bit<def,read-undef> = MOV32rm %vreg354, 1, %noreg, 60, %noreg; mem:LD4[%tPos495] GR64_NOSP:%vreg352 GR64:%vreg354
	Success: %vreg351:sub_32bit -> %vreg352
	Result = %vreg352 [15168r,15232r:0)  0@15168r
15328B	%vreg337<def> = SUBREG_TO_REG 0, %vreg336, 4; GR64_NOSP:%vreg337 GR32:%vreg336
	Considering merging to GR64_NOSP with %vreg336 in %vreg337:sub_32bit
		RHS = %vreg336 [15312r,15328r:0)  0@15312r
		LHS = %vreg337 [15328r,15376r:0)  0@15328r
		merge %vreg337:0@15328r into %vreg336:0@15312r --> @15312r
		erased:	15328r	%vreg337<def> = SUBREG_TO_REG 0, %vreg336, 4; GR64_NOSP:%vreg337 GR32:%vreg336
		updated: 15312B	%vreg337:sub_32bit<def,read-undef> = MOV32rr %vreg339; GR64_NOSP:%vreg337 GR32:%vreg339
	Success: %vreg336:sub_32bit -> %vreg337
	Result = %vreg337 [15312r,15376r:0)  0@15312r
15488B	%ECX<def> = COPY %vreg322; GR32:%vreg322
	Considering merging %vreg322 with %ECX
	Can only merge into reserved registers.
if.end.522:
if.then.5:
if.then.68:
if.then.87:
if.then.93:
if.then.135:
if.then.155:
if.then.161:
if.then.203:
if.then.223:
if.then.229:
if.then.270:
if.then.325:
if.then.351:
if.then.437:
if.then.443:
if.then.479:
if.then.485:
if.then.521:
if.then.527:
if.end.530:
16192B	%EDI<def> = COPY %vreg513; GR32:%vreg513
	Considering merging %vreg513 with %EDI
	Can only merge into reserved registers.
16208B	%RSI<def> = COPY %vreg510; GR64:%vreg510
	Considering merging %vreg510 with %RSI
	Can only merge into reserved registers.
16256B	%vreg507<def> = COPY %EAX<kill>; GR32:%vreg507
	Considering merging %vreg507 with %EAX
	Can only merge into reserved registers.
16384B	%vreg499<def> = SUBREG_TO_REG 0, %vreg498, 4; GR64_NOSP:%vreg499 GR32:%vreg498
	Considering merging to GR64_NOSP with %vreg498 in %vreg499:sub_32bit
		RHS = %vreg498 [16368r,16384r:0)  0@16368r
		LHS = %vreg499 [16384r,16432r:0)  0@16384r
		merge %vreg499:0@16384r into %vreg498:0@16368r --> @16368r
		erased:	16384r	%vreg499<def> = SUBREG_TO_REG 0, %vreg498, 4; GR64_NOSP:%vreg499 GR32:%vreg498
		updated: 16368B	%vreg499:sub_32bit<def,read-undef> = MOV32rm %vreg501, 1, %noreg, 60, %noreg; mem:LD4[%tPos536] GR64_NOSP:%vreg499 GR64:%vreg501
	Success: %vreg498:sub_32bit -> %vreg499
	Result = %vreg499 [16368r,16432r:0)  0@16368r
16528B	%vreg484<def> = SUBREG_TO_REG 0, %vreg483, 4; GR64_NOSP:%vreg484 GR32:%vreg483
	Considering merging to GR64_NOSP with %vreg483 in %vreg484:sub_32bit
		RHS = %vreg483 [16512r,16528r:0)  0@16512r
		LHS = %vreg484 [16528r,16576r:0)  0@16528r
		merge %vreg484:0@16528r into %vreg483:0@16512r --> @16512r
		erased:	16528r	%vreg484<def> = SUBREG_TO_REG 0, %vreg483, 4; GR64_NOSP:%vreg484 GR32:%vreg483
		updated: 16512B	%vreg484:sub_32bit<def,read-undef> = MOV32rr %vreg486; GR64_NOSP:%vreg484 GR32:%vreg486
	Success: %vreg483:sub_32bit -> %vreg484
	Result = %vreg484 [16512r,16576r:0)  0@16512r
16688B	%ECX<def> = COPY %vreg469; GR32:%vreg469
	Considering merging %vreg469 with %ECX
	Can only merge into reserved registers.
17136B	%EDI<def> = COPY %vreg440; GR32:%vreg440
	Considering merging %vreg440 with %EDI
	Can only merge into reserved registers.
17152B	%RSI<def> = COPY %vreg437; GR64:%vreg437
	Considering merging %vreg437 with %RSI
	Can only merge into reserved registers.
17200B	%vreg434<def> = COPY %EAX<kill>; GR32:%vreg434
	Considering merging %vreg434 with %EAX
	Can only merge into reserved registers.
17328B	%vreg426<def> = SUBREG_TO_REG 0, %vreg425, 4; GR64_NOSP:%vreg426 GR32:%vreg425
	Considering merging to GR64_NOSP with %vreg425 in %vreg426:sub_32bit
		RHS = %vreg425 [17312r,17328r:0)  0@17312r
		LHS = %vreg426 [17328r,17376r:0)  0@17328r
		merge %vreg426:0@17328r into %vreg425:0@17312r --> @17312r
		erased:	17328r	%vreg426<def> = SUBREG_TO_REG 0, %vreg425, 4; GR64_NOSP:%vreg426 GR32:%vreg425
		updated: 17312B	%vreg426:sub_32bit<def,read-undef> = MOV32rm %vreg428, 1, %noreg, 60, %noreg; mem:LD4[%tPos565] GR64_NOSP:%vreg426 GR64:%vreg428
	Success: %vreg425:sub_32bit -> %vreg426
	Result = %vreg426 [17312r,17376r:0)  0@17312r
17472B	%vreg411<def> = SUBREG_TO_REG 0, %vreg410, 4; GR64_NOSP:%vreg411 GR32:%vreg410
	Considering merging to GR64_NOSP with %vreg410 in %vreg411:sub_32bit
		RHS = %vreg410 [17456r,17472r:0)  0@17456r
		LHS = %vreg411 [17472r,17520r:0)  0@17472r
		merge %vreg411:0@17472r into %vreg410:0@17456r --> @17456r
		erased:	17472r	%vreg411<def> = SUBREG_TO_REG 0, %vreg410, 4; GR64_NOSP:%vreg411 GR32:%vreg410
		updated: 17456B	%vreg411:sub_32bit<def,read-undef> = MOV32rr %vreg413; GR64_NOSP:%vreg411 GR32:%vreg413
	Success: %vreg410:sub_32bit -> %vreg411
	Result = %vreg411 [17456r,17520r:0)  0@17456r
17632B	%ECX<def> = COPY %vreg396; GR32:%vreg396
	Considering merging %vreg396 with %ECX
	Can only merge into reserved registers.
3280B	%vreg764<def> = COPY %vreg765; GR32:%vreg764,%vreg765
	Considering merging to GR32 with %vreg765 in %vreg764
		RHS = %vreg765 [3264r,3280r:0)  0@3264r
		LHS = %vreg764 [3280r,3296r:0)[3296r,3312r:1)  0@3280r 1@3296r
		merge %vreg764:0@3280r into %vreg765:0@3264r --> @3264r
		erased:	3280r	%vreg764<def> = COPY %vreg765; GR32:%vreg764,%vreg765
		updated: 3264B	%vreg764<def> = MOV32rm %vreg766, 1, %noreg, 24, %noreg; mem:LD4[%rNToGo72] GR32:%vreg764 GR64:%vreg766
	Success: %vreg765 -> %vreg764
	Result = %vreg764 [3264r,3296r:0)[3296r,3312r:1)  0@3264r 1@3296r
3360B	%vreg758<def> = COPY %vreg756; GR32:%vreg758,%vreg756
	Considering merging to GR32 with %vreg756 in %vreg758
		RHS = %vreg756 [3216r,3360r:0)  0@3216r
		LHS = %vreg758 [3360r,3376r:0)[3376r,3424r:1)  0@3360r 1@3376r
		merge %vreg758:0@3360r into %vreg756:0@3216r --> @3216r
		erased:	3360r	%vreg758<def> = COPY %vreg756; GR32:%vreg758,%vreg756
		updated: 3216B	%vreg758<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg758
	Success: %vreg756 -> %vreg758
	Result = %vreg758 [3216r,3376r:0)[3376r,3424r:1)  0@3216r 1@3376r
3408B	%vreg752<def> = COPY %vreg754; GR32:%vreg752,%vreg754
	Considering merging to GR32 with %vreg754 in %vreg752
		RHS = %vreg754 [3392r,3408r:0)  0@3392r
		LHS = %vreg752 [3408r,3424r:0)[3424r,3440r:1)  0@3408r 1@3424r
		merge %vreg752:0@3408r into %vreg754:0@3392r --> @3392r
		erased:	3408r	%vreg752<def> = COPY %vreg754; GR32:%vreg752,%vreg754
		updated: 3392B	%vreg752<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg752
	Success: %vreg754 -> %vreg752
	Result = %vreg752 [3392r,3424r:0)[3424r,3440r:1)  0@3392r 1@3424r
3440B	%vreg749<def> = COPY %vreg752:sub_8bit; GR8:%vreg749 GR32:%vreg752
	Considering merging to GR32 with %vreg749 in %vreg752:sub_8bit
		RHS = %vreg749 [3440r,3456r:0)  0@3440r
		LHS = %vreg752 [3392r,3424r:0)[3424r,3440r:1)  0@3392r 1@3424r
		merge %vreg749:0@3440r into %vreg752:1@3424r --> @3424r
		erased:	3440r	%vreg749<def> = COPY %vreg752:sub_8bit; GR8:%vreg749 GR32:%vreg752
		updated: 3456B	MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg752:sub_8bit; mem:ST1[%k1] GR32:%vreg752
	Success: %vreg749:sub_8bit -> %vreg752
	Result = %vreg752 [3392r,3424r:0)[3424r,3456r:1)  0@3392r 1@3424r
3504B	%vreg744<def> = COPY %vreg745; GR32:%vreg744,%vreg745
	Considering merging to GR32 with %vreg745 in %vreg744
		RHS = %vreg745 [3488r,3504r:0)  0@3488r
		LHS = %vreg744 [3504r,3520r:0)[3520r,3536r:1)  0@3504r 1@3520r
		merge %vreg744:0@3504r into %vreg745:0@3488r --> @3488r
		erased:	3504r	%vreg744<def> = COPY %vreg745; GR32:%vreg744,%vreg745
		updated: 3488B	%vreg744<def> = MOV32rm %vreg746, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used80] GR32:%vreg744 GR64:%vreg746
	Success: %vreg745 -> %vreg744
	Result = %vreg744 [3488r,3520r:0)[3520r,3536r:1)  0@3488r 1@3520r
3616B	%vreg734<def> = COPY %vreg736; GR32:%vreg734,%vreg736
	Considering merging to GR32 with %vreg736 in %vreg734
		RHS = %vreg736 [3600r,3616r:0)  0@3600r
		LHS = %vreg734 [3616r,3632r:0)[3632r,3648r:1)  0@3616r 1@3632r
		merge %vreg734:0@3616r into %vreg736:0@3600r --> @3600r
		erased:	3616r	%vreg734<def> = COPY %vreg736; GR32:%vreg734,%vreg736
		updated: 3600B	%vreg734<def> = MOV32rm %vreg737, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock83] GR32:%vreg734 GR64:%vreg737
	Success: %vreg736 -> %vreg734
	Result = %vreg734 [3600r,3632r:0)[3632r,3648r:1)  0@3600r 1@3632r
5136B	%vreg891<def> = COPY %vreg892; GR32:%vreg891,%vreg892
	Considering merging to GR32 with %vreg892 in %vreg891
		RHS = %vreg892 [5120r,5136r:0)  0@5120r
		LHS = %vreg891 [5136r,5152r:0)[5152r,5168r:1)  0@5136r 1@5152r
		merge %vreg891:0@5136r into %vreg892:0@5120r --> @5120r
		erased:	5136r	%vreg891<def> = COPY %vreg892; GR32:%vreg891,%vreg892
		updated: 5120B	%vreg891<def> = MOV32rm %vreg893, 1, %noreg, 24, %noreg; mem:LD4[%rNToGo139] GR32:%vreg891 GR64:%vreg893
	Success: %vreg892 -> %vreg891
	Result = %vreg891 [5120r,5152r:0)[5152r,5168r:1)  0@5120r 1@5152r
5216B	%vreg885<def> = COPY %vreg883; GR32:%vreg885,%vreg883
	Considering merging to GR32 with %vreg883 in %vreg885
		RHS = %vreg883 [5072r,5216r:0)  0@5072r
		LHS = %vreg885 [5216r,5232r:0)[5232r,5280r:1)  0@5216r 1@5232r
		merge %vreg885:0@5216r into %vreg883:0@5072r --> @5072r
		erased:	5216r	%vreg885<def> = COPY %vreg883; GR32:%vreg885,%vreg883
		updated: 5072B	%vreg885<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg885
	Success: %vreg883 -> %vreg885
	Result = %vreg885 [5072r,5232r:0)[5232r,5280r:1)  0@5072r 1@5232r
5264B	%vreg879<def> = COPY %vreg881; GR32:%vreg879,%vreg881
	Considering merging to GR32 with %vreg881 in %vreg879
		RHS = %vreg881 [5248r,5264r:0)  0@5248r
		LHS = %vreg879 [5264r,5280r:0)[5280r,5296r:1)  0@5264r 1@5280r
		merge %vreg879:0@5264r into %vreg881:0@5248r --> @5248r
		erased:	5264r	%vreg879<def> = COPY %vreg881; GR32:%vreg879,%vreg881
		updated: 5248B	%vreg879<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg879
	Success: %vreg881 -> %vreg879
	Result = %vreg879 [5248r,5280r:0)[5280r,5296r:1)  0@5248r 1@5280r
5296B	%vreg876<def> = COPY %vreg879:sub_8bit; GR8:%vreg876 GR32:%vreg879
	Considering merging to GR32 with %vreg876 in %vreg879:sub_8bit
		RHS = %vreg876 [5296r,5312r:0)  0@5296r
		LHS = %vreg879 [5248r,5280r:0)[5280r,5296r:1)  0@5248r 1@5280r
		merge %vreg876:0@5296r into %vreg879:1@5280r --> @5280r
		erased:	5296r	%vreg876<def> = COPY %vreg879:sub_8bit; GR8:%vreg876 GR32:%vreg879
		updated: 5312B	MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg879:sub_8bit; mem:ST1[%k1] GR32:%vreg879
	Success: %vreg876:sub_8bit -> %vreg879
	Result = %vreg879 [5248r,5280r:0)[5280r,5312r:1)  0@5248r 1@5280r
5360B	%vreg871<def> = COPY %vreg872; GR32:%vreg871,%vreg872
	Considering merging to GR32 with %vreg872 in %vreg871
		RHS = %vreg872 [5344r,5360r:0)  0@5344r
		LHS = %vreg871 [5360r,5376r:0)[5376r,5392r:1)  0@5360r 1@5376r
		merge %vreg871:0@5360r into %vreg872:0@5344r --> @5344r
		erased:	5360r	%vreg871<def> = COPY %vreg872; GR32:%vreg871,%vreg872
		updated: 5344B	%vreg871<def> = MOV32rm %vreg873, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used148] GR32:%vreg871 GR64:%vreg873
	Success: %vreg872 -> %vreg871
	Result = %vreg871 [5344r,5376r:0)[5376r,5392r:1)  0@5344r 1@5376r
5472B	%vreg861<def> = COPY %vreg863; GR32:%vreg861,%vreg863
	Considering merging to GR32 with %vreg863 in %vreg861
		RHS = %vreg863 [5456r,5472r:0)  0@5456r
		LHS = %vreg861 [5472r,5488r:0)[5488r,5504r:1)  0@5472r 1@5488r
		merge %vreg861:0@5472r into %vreg863:0@5456r --> @5456r
		erased:	5472r	%vreg861<def> = COPY %vreg863; GR32:%vreg861,%vreg863
		updated: 5456B	%vreg861<def> = MOV32rm %vreg864, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock151] GR32:%vreg861 GR64:%vreg864
	Success: %vreg863 -> %vreg861
	Result = %vreg861 [5456r,5488r:0)[5488r,5504r:1)  0@5456r 1@5488r
6992B	%vreg1018<def> = COPY %vreg1019; GR32:%vreg1018,%vreg1019
	Considering merging to GR32 with %vreg1019 in %vreg1018
		RHS = %vreg1019 [6976r,6992r:0)  0@6976r
		LHS = %vreg1018 [6992r,7008r:0)[7008r,7024r:1)  0@6992r 1@7008r
		merge %vreg1018:0@6992r into %vreg1019:0@6976r --> @6976r
		erased:	6992r	%vreg1018<def> = COPY %vreg1019; GR32:%vreg1018,%vreg1019
		updated: 6976B	%vreg1018<def> = MOV32rm %vreg1020, 1, %noreg, 24, %noreg; mem:LD4[%rNToGo207] GR32:%vreg1018 GR64:%vreg1020
	Success: %vreg1019 -> %vreg1018
	Result = %vreg1018 [6976r,7008r:0)[7008r,7024r:1)  0@6976r 1@7008r
7072B	%vreg1012<def> = COPY %vreg1010; GR32:%vreg1012,%vreg1010
	Considering merging to GR32 with %vreg1010 in %vreg1012
		RHS = %vreg1010 [6928r,7072r:0)  0@6928r
		LHS = %vreg1012 [7072r,7088r:0)[7088r,7136r:1)  0@7072r 1@7088r
		merge %vreg1012:0@7072r into %vreg1010:0@6928r --> @6928r
		erased:	7072r	%vreg1012<def> = COPY %vreg1010; GR32:%vreg1012,%vreg1010
		updated: 6928B	%vreg1012<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg1012
	Success: %vreg1010 -> %vreg1012
	Result = %vreg1012 [6928r,7088r:0)[7088r,7136r:1)  0@6928r 1@7088r
7120B	%vreg1006<def> = COPY %vreg1008; GR32:%vreg1006,%vreg1008
	Considering merging to GR32 with %vreg1008 in %vreg1006
		RHS = %vreg1008 [7104r,7120r:0)  0@7104r
		LHS = %vreg1006 [7120r,7136r:0)[7136r,7152r:1)  0@7120r 1@7136r
		merge %vreg1006:0@7120r into %vreg1008:0@7104r --> @7104r
		erased:	7120r	%vreg1006<def> = COPY %vreg1008; GR32:%vreg1006,%vreg1008
		updated: 7104B	%vreg1006<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg1006
	Success: %vreg1008 -> %vreg1006
	Result = %vreg1006 [7104r,7136r:0)[7136r,7152r:1)  0@7104r 1@7136r
7152B	%vreg1003<def> = COPY %vreg1006:sub_8bit; GR8:%vreg1003 GR32:%vreg1006
	Considering merging to GR32 with %vreg1003 in %vreg1006:sub_8bit
		RHS = %vreg1003 [7152r,7168r:0)  0@7152r
		LHS = %vreg1006 [7104r,7136r:0)[7136r,7152r:1)  0@7104r 1@7136r
		merge %vreg1003:0@7152r into %vreg1006:1@7136r --> @7136r
		erased:	7152r	%vreg1003<def> = COPY %vreg1006:sub_8bit; GR8:%vreg1003 GR32:%vreg1006
		updated: 7168B	MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg1006:sub_8bit; mem:ST1[%k1] GR32:%vreg1006
	Success: %vreg1003:sub_8bit -> %vreg1006
	Result = %vreg1006 [7104r,7136r:0)[7136r,7168r:1)  0@7104r 1@7136r
7216B	%vreg998<def> = COPY %vreg999; GR32:%vreg998,%vreg999
	Considering merging to GR32 with %vreg999 in %vreg998
		RHS = %vreg999 [7200r,7216r:0)  0@7200r
		LHS = %vreg998 [7216r,7232r:0)[7232r,7248r:1)  0@7216r 1@7232r
		merge %vreg998:0@7216r into %vreg999:0@7200r --> @7200r
		erased:	7216r	%vreg998<def> = COPY %vreg999; GR32:%vreg998,%vreg999
		updated: 7200B	%vreg998<def> = MOV32rm %vreg1000, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used216] GR32:%vreg998 GR64:%vreg1000
	Success: %vreg999 -> %vreg998
	Result = %vreg998 [7200r,7232r:0)[7232r,7248r:1)  0@7200r 1@7232r
7328B	%vreg988<def> = COPY %vreg990; GR32:%vreg988,%vreg990
	Considering merging to GR32 with %vreg990 in %vreg988
		RHS = %vreg990 [7312r,7328r:0)  0@7312r
		LHS = %vreg988 [7328r,7344r:0)[7344r,7360r:1)  0@7328r 1@7344r
		merge %vreg988:0@7328r into %vreg990:0@7312r --> @7312r
		erased:	7328r	%vreg988<def> = COPY %vreg990; GR32:%vreg988,%vreg990
		updated: 7312B	%vreg988<def> = MOV32rm %vreg991, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock219] GR32:%vreg988 GR64:%vreg991
	Success: %vreg990 -> %vreg988
	Result = %vreg988 [7312r,7344r:0)[7344r,7360r:1)  0@7312r 1@7344r
8816B	%vreg1203<def> = COPY %vreg1204; GR32:%vreg1203,%vreg1204
	Considering merging to GR32 with %vreg1204 in %vreg1203
		RHS = %vreg1204 [8800r,8816r:0)  0@8800r
		LHS = %vreg1203 [8816r,8832r:0)[8832r,8848r:1)  0@8816r 1@8832r
		merge %vreg1203:0@8816r into %vreg1204:0@8800r --> @8800r
		erased:	8816r	%vreg1203<def> = COPY %vreg1204; GR32:%vreg1203,%vreg1204
		updated: 8800B	%vreg1203<def> = MOV32rm %vreg1205, 1, %noreg, 24, %noreg; mem:LD4[%rNToGo274] GR32:%vreg1203 GR64:%vreg1205
	Success: %vreg1204 -> %vreg1203
	Result = %vreg1203 [8800r,8832r:0)[8832r,8848r:1)  0@8800r 1@8832r
8896B	%vreg1197<def> = COPY %vreg1195; GR32:%vreg1197,%vreg1195
	Considering merging to GR32 with %vreg1195 in %vreg1197
		RHS = %vreg1195 [8752r,8896r:0)  0@8752r
		LHS = %vreg1197 [8896r,8912r:0)[8912r,8960r:1)  0@8896r 1@8912r
		merge %vreg1197:0@8896r into %vreg1195:0@8752r --> @8752r
		erased:	8896r	%vreg1197<def> = COPY %vreg1195; GR32:%vreg1197,%vreg1195
		updated: 8752B	%vreg1197<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg1197
	Success: %vreg1195 -> %vreg1197
	Result = %vreg1197 [8752r,8912r:0)[8912r,8960r:1)  0@8752r 1@8912r
8944B	%vreg1191<def> = COPY %vreg1193; GR32:%vreg1191,%vreg1193
	Considering merging to GR32 with %vreg1193 in %vreg1191
		RHS = %vreg1193 [8928r,8944r:0)  0@8928r
		LHS = %vreg1191 [8944r,8960r:0)[8960r,8976r:1)  0@8944r 1@8960r
		merge %vreg1191:0@8944r into %vreg1193:0@8928r --> @8928r
		erased:	8944r	%vreg1191<def> = COPY %vreg1193; GR32:%vreg1191,%vreg1193
		updated: 8928B	%vreg1191<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg1191
	Success: %vreg1193 -> %vreg1191
	Result = %vreg1191 [8928r,8960r:0)[8960r,8976r:1)  0@8928r 1@8960r
8976B	%vreg1188<def> = COPY %vreg1191:sub_8bit; GR8:%vreg1188 GR32:%vreg1191
	Considering merging to GR32 with %vreg1188 in %vreg1191:sub_8bit
		RHS = %vreg1188 [8976r,8992r:0)  0@8976r
		LHS = %vreg1191 [8928r,8960r:0)[8960r,8976r:1)  0@8928r 1@8960r
		merge %vreg1188:0@8976r into %vreg1191:1@8960r --> @8960r
		erased:	8976r	%vreg1188<def> = COPY %vreg1191:sub_8bit; GR8:%vreg1188 GR32:%vreg1191
		updated: 8992B	MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg1191:sub_8bit; mem:ST1[%k1] GR32:%vreg1191
	Success: %vreg1188:sub_8bit -> %vreg1191
	Result = %vreg1191 [8928r,8960r:0)[8960r,8992r:1)  0@8928r 1@8960r
9040B	%vreg1183<def> = COPY %vreg1184; GR32:%vreg1183,%vreg1184
	Considering merging to GR32 with %vreg1184 in %vreg1183
		RHS = %vreg1184 [9024r,9040r:0)  0@9024r
		LHS = %vreg1183 [9040r,9056r:0)[9056r,9072r:1)  0@9040r 1@9056r
		merge %vreg1183:0@9040r into %vreg1184:0@9024r --> @9024r
		erased:	9040r	%vreg1183<def> = COPY %vreg1184; GR32:%vreg1183,%vreg1184
		updated: 9024B	%vreg1183<def> = MOV32rm %vreg1185, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used283] GR32:%vreg1183 GR64:%vreg1185
	Success: %vreg1184 -> %vreg1183
	Result = %vreg1183 [9024r,9056r:0)[9056r,9072r:1)  0@9024r 1@9056r
9104B	%vreg1177<def> = COPY %vreg1179; GR32:%vreg1177,%vreg1179
	Considering merging to GR32 with %vreg1179 in %vreg1177
		RHS = %vreg1179 [9088r,9104r:0)  0@9088r
		LHS = %vreg1177 [9104r,9120r:0)[9120r,9152r:1)  0@9104r 1@9120r
		merge %vreg1177:0@9104r into %vreg1179:0@9088r --> @9088r
		erased:	9104r	%vreg1177<def> = COPY %vreg1179; GR32:%vreg1177,%vreg1179
		updated: 9088B	%vreg1177<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg1177
	Success: %vreg1179 -> %vreg1177
	Result = %vreg1177 [9088r,9120r:0)[9120r,9152r:1)  0@9088r 1@9120r
9216B	%vreg1168<def> = COPY %vreg1169; GR64:%vreg1168,%vreg1169
	Considering merging to GR64 with %vreg1169 in %vreg1168
		RHS = %vreg1169 [9200r,9216r:0)  0@9200r
		LHS = %vreg1168 [9216r,9232r:0)[9232r,9280r:1)  0@9216r 1@9232r
		merge %vreg1168:0@9216r into %vreg1169:0@9200r --> @9200r
		erased:	9216r	%vreg1168<def> = COPY %vreg1169; GR64:%vreg1168,%vreg1169
		updated: 9200B	%vreg1168<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1168
	Success: %vreg1169 -> %vreg1168
	Result = %vreg1168 [9200r,9232r:0)[9232r,9280r:1)  0@9200r 1@9232r
9552B	%vreg1144<def> = COPY %vreg1146; GR32:%vreg1144,%vreg1146
	Considering merging to GR32 with %vreg1146 in %vreg1144
		RHS = %vreg1146 [9536r,9552r:0)  0@9536r
		LHS = %vreg1144 [9552r,9568r:0)[9568r,9584r:1)  0@9552r 1@9568r
		merge %vreg1144:0@9552r into %vreg1146:0@9536r --> @9536r
		erased:	9552r	%vreg1144<def> = COPY %vreg1146; GR32:%vreg1144,%vreg1146
		updated: 9536B	%vreg1144<def> = MOV32rm %vreg1147, 1, %noreg, 60, %noreg; mem:LD4[%tPos298] GR32:%vreg1144 GR64:%vreg1147
	Success: %vreg1146 -> %vreg1144
	Result = %vreg1144 [9536r,9568r:0)[9568r,9584r:1)  0@9536r 1@9568r
9696B	%vreg1129<def> = COPY %vreg1131; GR32:%vreg1129,%vreg1131
	Considering merging to GR32 with %vreg1131 in %vreg1129
		RHS = %vreg1131 [9680r,9696r:0)  0@9680r
		LHS = %vreg1129 [9696r,9712r:0)[9712r,9728r:1)  0@9696r 1@9712r
		merge %vreg1129:0@9696r into %vreg1131:0@9680r --> @9680r
		erased:	9696r	%vreg1129<def> = COPY %vreg1131; GR32:%vreg1129,%vreg1131
		updated: 9680B	%vreg1129<def> = MOV32rm %vreg1132, 1, %noreg, 60, %noreg; mem:LD4[%tPos304] GR32:%vreg1129 GR64:%vreg1132
	Success: %vreg1131 -> %vreg1129
	Result = %vreg1129 [9680r,9712r:0)[9712r,9728r:1)  0@9680r 1@9712r
9728B	%vreg1127<def> = COPY %vreg1129; GR32:%vreg1127,%vreg1129
	Considering merging to GR32 with %vreg1129 in %vreg1127
		RHS = %vreg1129 [9680r,9712r:0)[9712r,9728r:1)  0@9680r 1@9712r
		LHS = %vreg1127 [9728r,9744r:0)[9744r,9760r:1)  0@9728r 1@9744r
		merge %vreg1127:0@9728r into %vreg1129:1@9712r --> @9712r
		erased:	9728r	%vreg1127<def> = COPY %vreg1129; GR32:%vreg1127,%vreg1129
		updated: 9680B	%vreg1127<def> = MOV32rm %vreg1132, 1, %noreg, 60, %noreg; mem:LD4[%tPos304] GR32:%vreg1127 GR64:%vreg1132
		updated: 9712B	%vreg1127<def,tied1> = SHL32ri %vreg1127<tied0>, 2, %EFLAGS<imp-def,dead>; GR32:%vreg1127
	Success: %vreg1129 -> %vreg1127
	Result = %vreg1127 [9680r,9712r:2)[9712r,9744r:0)[9744r,9760r:1)  0@9712r 1@9744r 2@9680r
9792B	%vreg1125<def> = COPY %vreg1134; GR32:%vreg1125,%vreg1134
	Considering merging to GR32 with %vreg1134 in %vreg1125
		RHS = %vreg1134 [9648r,9792r:0)  0@9648r
		LHS = %vreg1125 [9792r,9808r:0)[9808r,9824r:1)  0@9792r 1@9808r
		merge %vreg1125:0@9792r into %vreg1134:0@9648r --> @9648r
		erased:	9792r	%vreg1125<def> = COPY %vreg1134; GR32:%vreg1125,%vreg1134
		updated: 9648B	%vreg1125<def> = MOVZX32rm8 %vreg1138, 1, %vreg1142, 0, %noreg; mem:LD1[%arrayidx302] GR32:%vreg1125 GR64:%vreg1138 GR64_NOSP:%vreg1142
	Success: %vreg1134 -> %vreg1125
	Result = %vreg1125 [9648r,9808r:0)[9808r,9824r:1)  0@9648r 1@9808r
9824B	%vreg1122<def> = COPY %vreg1125; GR32:%vreg1122,%vreg1125
	Considering merging to GR32 with %vreg1125 in %vreg1122
		RHS = %vreg1125 [9648r,9808r:0)[9808r,9824r:1)  0@9648r 1@9808r
		LHS = %vreg1122 [9824r,9840r:0)[9840r,9856r:1)  0@9824r 1@9840r
		merge %vreg1122:0@9824r into %vreg1125:1@9808r --> @9808r
		erased:	9824r	%vreg1122<def> = COPY %vreg1125; GR32:%vreg1122,%vreg1125
		updated: 9648B	%vreg1122<def> = MOVZX32rm8 %vreg1138, 1, %vreg1142, 0, %noreg; mem:LD1[%arrayidx302] GR32:%vreg1122 GR64:%vreg1138 GR64_NOSP:%vreg1142
		updated: 9808B	%vreg1122<def,tied1> = SHR32rCL %vreg1122<tied0>, %EFLAGS<imp-def,dead>, %CL<imp-use,kill>; GR32:%vreg1122
	Success: %vreg1125 -> %vreg1122
	Result = %vreg1122 [9648r,9808r:2)[9808r,9840r:0)[9840r,9856r:1)  0@9808r 1@9840r 2@9648r
9856B	%vreg1120<def> = COPY %vreg1122; GR32:%vreg1120,%vreg1122
	Considering merging to GR32 with %vreg1120 in %vreg1122
		RHS = %vreg1120 [9856r,9872r:0)[9872r,9904r:1)  0@9856r 1@9872r
		LHS = %vreg1122 [9648r,9808r:2)[9808r,9840r:0)[9840r,9856r:1)  0@9808r 1@9840r 2@9648r
		merge %vreg1120:0@9856r into %vreg1122:1@9840r --> @9840r
		erased:	9856r	%vreg1120<def> = COPY %vreg1122; GR32:%vreg1120,%vreg1122
		updated: 9872B	%vreg1122<def,tied1> = SHL32ri %vreg1122<tied0>, 16, %EFLAGS<imp-def,dead>; GR32:%vreg1122
		updated: 9904B	%vreg1118<def,tied1> = OR32rr %vreg1118<tied0>, %vreg1122, %EFLAGS<imp-def,dead>; GR32:%vreg1118,%vreg1122
	Success: %vreg1120 -> %vreg1122
	Result = %vreg1122 [9648r,9808r:2)[9808r,9840r:0)[9840r,9872r:1)[9872r,9904r:3)  0@9808r 1@9840r 2@9648r 3@9872r
9888B	%vreg1118<def> = COPY %vreg1149; GR32:%vreg1118,%vreg1149
	Considering merging to GR32 with %vreg1149 in %vreg1118
		RHS = %vreg1149 [9504r,9888r:0)  0@9504r
		LHS = %vreg1118 [9888r,9904r:0)[9904r,9936r:1)  0@9888r 1@9904r
		merge %vreg1118:0@9888r into %vreg1149:0@9504r --> @9504r
		erased:	9888r	%vreg1118<def> = COPY %vreg1149; GR32:%vreg1118,%vreg1149
		updated: 9504B	%vreg1118<def> = MOVZX32rm16 %vreg1153, 2, %vreg1157, 0, %noreg; mem:LD2[%arrayidx296] GR32:%vreg1118 GR64:%vreg1153 GR64_NOSP:%vreg1157
	Success: %vreg1149 -> %vreg1118
	Result = %vreg1118 [9504r,9904r:0)[9904r,9936r:1)  0@9504r 1@9904r
1632B	%vreg621<def> = COPY %vreg623; GR32:%vreg621,%vreg623
	Considering merging to GR32 with %vreg623 in %vreg621
		RHS = %vreg623 [1616r,1632r:0)  0@1616r
		LHS = %vreg621 [1632r,1648r:0)[1648r,1664r:1)  0@1632r 1@1648r
		merge %vreg621:0@1632r into %vreg623:0@1616r --> @1616r
		erased:	1632r	%vreg621<def> = COPY %vreg623; GR32:%vreg621,%vreg623
		updated: 1616B	%vreg621<def> = MOV32rm %vreg624, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock] GR32:%vreg621 GR64:%vreg624
	Success: %vreg623 -> %vreg621
	Result = %vreg621 [1616r,1648r:0)[1648r,1664r:1)  0@1616r 1@1648r
1824B	%vreg631<def> = COPY %vreg633; GR32:%vreg631,%vreg633
	Considering merging to GR32 with %vreg633 in %vreg631
		RHS = %vreg633 [1808r,1824r:0)  0@1808r
		LHS = %vreg631 [1824r,1840r:0)[1840r,1856r:1)  0@1824r 1@1840r
		merge %vreg631:0@1824r into %vreg633:0@1808r --> @1808r
		erased:	1824r	%vreg631<def> = COPY %vreg633; GR32:%vreg631,%vreg633
		updated: 1808B	%vreg631<def> = MOV32rm %vreg634, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock32] GR32:%vreg631 GR64:%vreg634
	Success: %vreg633 -> %vreg631
	Result = %vreg631 [1808r,1840r:0)[1840r,1856r:1)  0@1808r 1@1840r
2016B	%vreg705<def> = COPY %vreg707:sub_8bit; GR8:%vreg705 GR32:%vreg707
	Considering merging to GR32 with %vreg705 in %vreg707:sub_8bit
		RHS = %vreg705 [2016r,2048r:0)  0@2016r
		LHS = %vreg707 [2000r,2016r:0)  0@2000r
		merge %vreg705:0@2016r into %vreg707:0@2000r --> @2000r
		erased:	2016r	%vreg705<def> = COPY %vreg707:sub_8bit; GR8:%vreg705 GR32:%vreg707
		updated: 2048B	MOV8mr %vreg703, 1, %noreg, 12, %noreg, %vreg707:sub_8bit; mem:ST1[%state_out_ch40] GR64:%vreg703 GR32:%vreg707
	Success: %vreg705:sub_8bit -> %vreg707
	Result = %vreg707 [2000r,2048r:0)  0@2000r
2112B	%vreg696<def> = COPY %vreg697; GR64:%vreg696,%vreg697
	Considering merging to GR64 with %vreg697 in %vreg696
		RHS = %vreg697 [2096r,2112r:0)  0@2096r
		LHS = %vreg696 [2112r,2128r:0)[2128r,2176r:1)  0@2112r 1@2128r
		merge %vreg696:0@2112r into %vreg697:0@2096r --> @2096r
		erased:	2112r	%vreg696<def> = COPY %vreg697; GR64:%vreg696,%vreg697
		updated: 2096B	%vreg696<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg696
	Success: %vreg697 -> %vreg696
	Result = %vreg696 [2096r,2128r:0)[2128r,2176r:1)  0@2096r 1@2128r
2288B	%vreg690<def> = COPY %vreg693:sub_8bit; GR8:%vreg690 GR32:%vreg693
	Considering merging to GR32 with %vreg690 in %vreg693:sub_8bit
		RHS = %vreg690 [2288r,2304r:0)  0@2288r
		LHS = %vreg693 [2224r,2288r:0)  0@2224r
		merge %vreg690:0@2288r into %vreg693:0@2224r --> @2224r
		erased:	2288r	%vreg690<def> = COPY %vreg693:sub_8bit; GR8:%vreg690 GR32:%vreg693
		updated: 2304B	MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg693:sub_8bit; mem:ST1[%k1] GR32:%vreg693
	Success: %vreg690:sub_8bit -> %vreg693
	Result = %vreg693 [2224r,2304r:0)  0@2224r
2448B	%vreg672<def> = COPY %vreg674; GR32:%vreg672,%vreg674
	Considering merging to GR32 with %vreg674 in %vreg672
		RHS = %vreg674 [2432r,2448r:0)  0@2432r
		LHS = %vreg672 [2448r,2464r:0)[2464r,2480r:1)  0@2448r 1@2464r
		merge %vreg672:0@2448r into %vreg674:0@2432r --> @2432r
		erased:	2448r	%vreg672<def> = COPY %vreg674; GR32:%vreg672,%vreg674
		updated: 2432B	%vreg672<def> = MOV32rm %vreg675, 1, %noreg, 60, %noreg; mem:LD4[%tPos46] GR32:%vreg672 GR64:%vreg675
	Success: %vreg674 -> %vreg672
	Result = %vreg672 [2432r,2464r:0)[2464r,2480r:1)  0@2432r 1@2464r
2592B	%vreg657<def> = COPY %vreg659; GR32:%vreg657,%vreg659
	Considering merging to GR32 with %vreg659 in %vreg657
		RHS = %vreg659 [2576r,2592r:0)  0@2576r
		LHS = %vreg657 [2592r,2608r:0)[2608r,2624r:1)  0@2592r 1@2608r
		merge %vreg657:0@2592r into %vreg659:0@2576r --> @2576r
		erased:	2592r	%vreg657<def> = COPY %vreg659; GR32:%vreg657,%vreg659
		updated: 2576B	%vreg657<def> = MOV32rm %vreg660, 1, %noreg, 60, %noreg; mem:LD4[%tPos51] GR32:%vreg657 GR64:%vreg660
	Success: %vreg659 -> %vreg657
	Result = %vreg657 [2576r,2608r:0)[2608r,2624r:1)  0@2576r 1@2608r
2624B	%vreg655<def> = COPY %vreg657; GR32:%vreg655,%vreg657
	Considering merging to GR32 with %vreg657 in %vreg655
		RHS = %vreg657 [2576r,2608r:0)[2608r,2624r:1)  0@2576r 1@2608r
		LHS = %vreg655 [2624r,2640r:0)[2640r,2656r:1)  0@2624r 1@2640r
		merge %vreg655:0@2624r into %vreg657:1@2608r --> @2608r
		erased:	2624r	%vreg655<def> = COPY %vreg657; GR32:%vreg655,%vreg657
		updated: 2576B	%vreg655<def> = MOV32rm %vreg660, 1, %noreg, 60, %noreg; mem:LD4[%tPos51] GR32:%vreg655 GR64:%vreg660
		updated: 2608B	%vreg655<def,tied1> = SHL32ri %vreg655<tied0>, 2, %EFLAGS<imp-def,dead>; GR32:%vreg655
	Success: %vreg657 -> %vreg655
	Result = %vreg655 [2576r,2608r:2)[2608r,2640r:0)[2640r,2656r:1)  0@2608r 1@2640r 2@2576r
2688B	%vreg653<def> = COPY %vreg662; GR32:%vreg653,%vreg662
	Considering merging to GR32 with %vreg662 in %vreg653
		RHS = %vreg662 [2544r,2688r:0)  0@2544r
		LHS = %vreg653 [2688r,2704r:0)[2704r,2720r:1)  0@2688r 1@2704r
		merge %vreg653:0@2688r into %vreg662:0@2544r --> @2544r
		erased:	2688r	%vreg653<def> = COPY %vreg662; GR32:%vreg653,%vreg662
		updated: 2544B	%vreg653<def> = MOVZX32rm8 %vreg666, 1, %vreg670, 0, %noreg; mem:LD1[%arrayidx49] GR32:%vreg653 GR64:%vreg666 GR64_NOSP:%vreg670
	Success: %vreg662 -> %vreg653
	Result = %vreg653 [2544r,2704r:0)[2704r,2720r:1)  0@2544r 1@2704r
2720B	%vreg650<def> = COPY %vreg653; GR32:%vreg650,%vreg653
	Considering merging to GR32 with %vreg653 in %vreg650
		RHS = %vreg653 [2544r,2704r:0)[2704r,2720r:1)  0@2544r 1@2704r
		LHS = %vreg650 [2720r,2736r:0)[2736r,2752r:1)  0@2720r 1@2736r
		merge %vreg650:0@2720r into %vreg653:1@2704r --> @2704r
		erased:	2720r	%vreg650<def> = COPY %vreg653; GR32:%vreg650,%vreg653
		updated: 2544B	%vreg650<def> = MOVZX32rm8 %vreg666, 1, %vreg670, 0, %noreg; mem:LD1[%arrayidx49] GR32:%vreg650 GR64:%vreg666 GR64_NOSP:%vreg670
		updated: 2704B	%vreg650<def,tied1> = SHR32rCL %vreg650<tied0>, %EFLAGS<imp-def,dead>, %CL<imp-use,kill>; GR32:%vreg650
	Success: %vreg653 -> %vreg650
	Result = %vreg650 [2544r,2704r:2)[2704r,2736r:0)[2736r,2752r:1)  0@2704r 1@2736r 2@2544r
2752B	%vreg648<def> = COPY %vreg650; GR32:%vreg648,%vreg650
	Considering merging to GR32 with %vreg648 in %vreg650
		RHS = %vreg648 [2752r,2768r:0)[2768r,2800r:1)  0@2752r 1@2768r
		LHS = %vreg650 [2544r,2704r:2)[2704r,2736r:0)[2736r,2752r:1)  0@2704r 1@2736r 2@2544r
		merge %vreg648:0@2752r into %vreg650:1@2736r --> @2736r
		erased:	2752r	%vreg648<def> = COPY %vreg650; GR32:%vreg648,%vreg650
		updated: 2768B	%vreg650<def,tied1> = SHL32ri %vreg650<tied0>, 16, %EFLAGS<imp-def,dead>; GR32:%vreg650
		updated: 2800B	%vreg646<def,tied1> = OR32rr %vreg646<tied0>, %vreg650, %EFLAGS<imp-def,dead>; GR32:%vreg646,%vreg650
	Success: %vreg648 -> %vreg650
	Result = %vreg650 [2544r,2704r:2)[2704r,2736r:0)[2736r,2768r:1)[2768r,2800r:3)  0@2704r 1@2736r 2@2544r 3@2768r
2784B	%vreg646<def> = COPY %vreg677; GR32:%vreg646,%vreg677
	Considering merging to GR32 with %vreg677 in %vreg646
		RHS = %vreg677 [2400r,2784r:0)  0@2400r
		LHS = %vreg646 [2784r,2800r:0)[2800r,2832r:1)  0@2784r 1@2800r
		merge %vreg646:0@2784r into %vreg677:0@2400r --> @2400r
		erased:	2784r	%vreg646<def> = COPY %vreg677; GR32:%vreg646,%vreg677
		updated: 2400B	%vreg646<def> = MOVZX32rm16 %vreg681, 2, %vreg685, 0, %noreg; mem:LD2[%arrayidx44] GR32:%vreg646 GR64:%vreg681 GR64_NOSP:%vreg685
	Success: %vreg677 -> %vreg646
	Result = %vreg646 [2400r,2800r:0)[2800r,2832r:1)  0@2400r 1@2800r
3024B	%vreg717<def> = COPY %vreg718; GR32:%vreg717,%vreg718
	Considering merging to GR32 with %vreg718 in %vreg717
		RHS = %vreg718 [3008r,3024r:0)  0@3008r
		LHS = %vreg717 [3024r,3040r:0)[3040r,3056r:1)  0@3024r 1@3040r
		merge %vreg717:0@3024r into %vreg718:0@3008r --> @3008r
		erased:	3024r	%vreg717<def> = COPY %vreg718; GR32:%vreg717,%vreg718
		updated: 3008B	%vreg717<def> = MOV32rm %vreg719, 1, %noreg, 28, %noreg; mem:LD4[%rTPos63] GR32:%vreg717 GR64:%vreg719
	Success: %vreg718 -> %vreg717
	Result = %vreg717 [3008r,3040r:0)[3040r,3056r:1)  0@3008r 1@3040r
3968B	%vreg831<def> = COPY %vreg832; GR64:%vreg831,%vreg832
	Considering merging to GR64 with %vreg832 in %vreg831
		RHS = %vreg832 [3952r,3968r:0)  0@3952r
		LHS = %vreg831 [3968r,3984r:0)[3984r,4032r:1)  0@3968r 1@3984r
		merge %vreg831:0@3968r into %vreg832:0@3952r --> @3952r
		erased:	3968r	%vreg831<def> = COPY %vreg832; GR64:%vreg831,%vreg832
		updated: 3952B	%vreg831<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg831
	Success: %vreg832 -> %vreg831
	Result = %vreg831 [3952r,3984r:0)[3984r,4032r:1)  0@3952r 1@3984r
4144B	%vreg825<def> = COPY %vreg828:sub_8bit; GR8:%vreg825 GR32:%vreg828
	Considering merging to GR32 with %vreg825 in %vreg828:sub_8bit
		RHS = %vreg825 [4144r,4160r:0)  0@4144r
		LHS = %vreg828 [4080r,4144r:0)  0@4080r
		merge %vreg825:0@4144r into %vreg828:0@4080r --> @4080r
		erased:	4144r	%vreg825<def> = COPY %vreg828:sub_8bit; GR8:%vreg825 GR32:%vreg828
		updated: 4160B	MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg828:sub_8bit; mem:ST1[%k1] GR32:%vreg828
	Success: %vreg825:sub_8bit -> %vreg828
	Result = %vreg828 [4080r,4160r:0)  0@4080r
4304B	%vreg807<def> = COPY %vreg809; GR32:%vreg807,%vreg809
	Considering merging to GR32 with %vreg809 in %vreg807
		RHS = %vreg809 [4288r,4304r:0)  0@4288r
		LHS = %vreg807 [4304r,4320r:0)[4320r,4336r:1)  0@4304r 1@4320r
		merge %vreg807:0@4304r into %vreg809:0@4288r --> @4288r
		erased:	4304r	%vreg807<def> = COPY %vreg809; GR32:%vreg807,%vreg809
		updated: 4288B	%vreg807<def> = MOV32rm %vreg810, 1, %noreg, 60, %noreg; mem:LD4[%tPos108] GR32:%vreg807 GR64:%vreg810
	Success: %vreg809 -> %vreg807
	Result = %vreg807 [4288r,4320r:0)[4320r,4336r:1)  0@4288r 1@4320r
4448B	%vreg792<def> = COPY %vreg794; GR32:%vreg792,%vreg794
	Considering merging to GR32 with %vreg794 in %vreg792
		RHS = %vreg794 [4432r,4448r:0)  0@4432r
		LHS = %vreg792 [4448r,4464r:0)[4464r,4480r:1)  0@4448r 1@4464r
		merge %vreg792:0@4448r into %vreg794:0@4432r --> @4432r
		erased:	4448r	%vreg792<def> = COPY %vreg794; GR32:%vreg792,%vreg794
		updated: 4432B	%vreg792<def> = MOV32rm %vreg795, 1, %noreg, 60, %noreg; mem:LD4[%tPos114] GR32:%vreg792 GR64:%vreg795
	Success: %vreg794 -> %vreg792
	Result = %vreg792 [4432r,4464r:0)[4464r,4480r:1)  0@4432r 1@4464r
4480B	%vreg790<def> = COPY %vreg792; GR32:%vreg790,%vreg792
	Considering merging to GR32 with %vreg792 in %vreg790
		RHS = %vreg792 [4432r,4464r:0)[4464r,4480r:1)  0@4432r 1@4464r
		LHS = %vreg790 [4480r,4496r:0)[4496r,4512r:1)  0@4480r 1@4496r
		merge %vreg790:0@4480r into %vreg792:1@4464r --> @4464r
		erased:	4480r	%vreg790<def> = COPY %vreg792; GR32:%vreg790,%vreg792
		updated: 4432B	%vreg790<def> = MOV32rm %vreg795, 1, %noreg, 60, %noreg; mem:LD4[%tPos114] GR32:%vreg790 GR64:%vreg795
		updated: 4464B	%vreg790<def,tied1> = SHL32ri %vreg790<tied0>, 2, %EFLAGS<imp-def,dead>; GR32:%vreg790
	Success: %vreg792 -> %vreg790
	Result = %vreg790 [4432r,4464r:2)[4464r,4496r:0)[4496r,4512r:1)  0@4464r 1@4496r 2@4432r
4544B	%vreg788<def> = COPY %vreg797; GR32:%vreg788,%vreg797
	Considering merging to GR32 with %vreg797 in %vreg788
		RHS = %vreg797 [4400r,4544r:0)  0@4400r
		LHS = %vreg788 [4544r,4560r:0)[4560r,4576r:1)  0@4544r 1@4560r
		merge %vreg788:0@4544r into %vreg797:0@4400r --> @4400r
		erased:	4544r	%vreg788<def> = COPY %vreg797; GR32:%vreg788,%vreg797
		updated: 4400B	%vreg788<def> = MOVZX32rm8 %vreg801, 1, %vreg805, 0, %noreg; mem:LD1[%arrayidx112] GR32:%vreg788 GR64:%vreg801 GR64_NOSP:%vreg805
	Success: %vreg797 -> %vreg788
	Result = %vreg788 [4400r,4560r:0)[4560r,4576r:1)  0@4400r 1@4560r
4576B	%vreg785<def> = COPY %vreg788; GR32:%vreg785,%vreg788
	Considering merging to GR32 with %vreg788 in %vreg785
		RHS = %vreg788 [4400r,4560r:0)[4560r,4576r:1)  0@4400r 1@4560r
		LHS = %vreg785 [4576r,4592r:0)[4592r,4608r:1)  0@4576r 1@4592r
		merge %vreg785:0@4576r into %vreg788:1@4560r --> @4560r
		erased:	4576r	%vreg785<def> = COPY %vreg788; GR32:%vreg785,%vreg788
		updated: 4400B	%vreg785<def> = MOVZX32rm8 %vreg801, 1, %vreg805, 0, %noreg; mem:LD1[%arrayidx112] GR32:%vreg785 GR64:%vreg801 GR64_NOSP:%vreg805
		updated: 4560B	%vreg785<def,tied1> = SHR32rCL %vreg785<tied0>, %EFLAGS<imp-def,dead>, %CL<imp-use,kill>; GR32:%vreg785
	Success: %vreg788 -> %vreg785
	Result = %vreg785 [4400r,4560r:2)[4560r,4592r:0)[4592r,4608r:1)  0@4560r 1@4592r 2@4400r
4608B	%vreg783<def> = COPY %vreg785; GR32:%vreg783,%vreg785
	Considering merging to GR32 with %vreg783 in %vreg785
		RHS = %vreg783 [4608r,4624r:0)[4624r,4656r:1)  0@4608r 1@4624r
		LHS = %vreg785 [4400r,4560r:2)[4560r,4592r:0)[4592r,4608r:1)  0@4560r 1@4592r 2@4400r
		merge %vreg783:0@4608r into %vreg785:1@4592r --> @4592r
		erased:	4608r	%vreg783<def> = COPY %vreg785; GR32:%vreg783,%vreg785
		updated: 4624B	%vreg785<def,tied1> = SHL32ri %vreg785<tied0>, 16, %EFLAGS<imp-def,dead>; GR32:%vreg785
		updated: 4656B	%vreg781<def,tied1> = OR32rr %vreg781<tied0>, %vreg785, %EFLAGS<imp-def,dead>; GR32:%vreg781,%vreg785
	Success: %vreg783 -> %vreg785
	Result = %vreg785 [4400r,4560r:2)[4560r,4592r:0)[4592r,4624r:1)[4624r,4656r:3)  0@4560r 1@4592r 2@4400r 3@4624r
4640B	%vreg781<def> = COPY %vreg812; GR32:%vreg781,%vreg812
	Considering merging to GR32 with %vreg812 in %vreg781
		RHS = %vreg812 [4256r,4640r:0)  0@4256r
		LHS = %vreg781 [4640r,4656r:0)[4656r,4688r:1)  0@4640r 1@4656r
		merge %vreg781:0@4640r into %vreg812:0@4256r --> @4256r
		erased:	4640r	%vreg781<def> = COPY %vreg812; GR32:%vreg781,%vreg812
		updated: 4256B	%vreg781<def> = MOVZX32rm16 %vreg816, 2, %vreg820, 0, %noreg; mem:LD2[%arrayidx106] GR32:%vreg781 GR64:%vreg816 GR64_NOSP:%vreg820
	Success: %vreg812 -> %vreg781
	Result = %vreg781 [4256r,4656r:0)[4656r,4688r:1)  0@4256r 1@4656r
4880B	%vreg844<def> = COPY %vreg845; GR32:%vreg844,%vreg845
	Considering merging to GR32 with %vreg845 in %vreg844
		RHS = %vreg845 [4864r,4880r:0)  0@4864r
		LHS = %vreg844 [4880r,4896r:0)[4896r,4912r:1)  0@4880r 1@4896r
		merge %vreg844:0@4880r into %vreg845:0@4864r --> @4864r
		erased:	4880r	%vreg844<def> = COPY %vreg845; GR32:%vreg844,%vreg845
		updated: 4864B	%vreg844<def> = MOV32rm %vreg846, 1, %noreg, 28, %noreg; mem:LD4[%rTPos130] GR32:%vreg844 GR64:%vreg846
	Success: %vreg845 -> %vreg844
	Result = %vreg844 [4864r,4896r:0)[4896r,4912r:1)  0@4864r 1@4896r
5824B	%vreg958<def> = COPY %vreg959; GR64:%vreg958,%vreg959
	Considering merging to GR64 with %vreg959 in %vreg958
		RHS = %vreg959 [5808r,5824r:0)  0@5808r
		LHS = %vreg958 [5824r,5840r:0)[5840r,5888r:1)  0@5824r 1@5840r
		merge %vreg958:0@5824r into %vreg959:0@5808r --> @5808r
		erased:	5824r	%vreg958<def> = COPY %vreg959; GR64:%vreg958,%vreg959
		updated: 5808B	%vreg958<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg958
	Success: %vreg959 -> %vreg958
	Result = %vreg958 [5808r,5840r:0)[5840r,5888r:1)  0@5808r 1@5840r
6000B	%vreg952<def> = COPY %vreg955:sub_8bit; GR8:%vreg952 GR32:%vreg955
	Considering merging to GR32 with %vreg952 in %vreg955:sub_8bit
		RHS = %vreg952 [6000r,6016r:0)  0@6000r
		LHS = %vreg955 [5936r,6000r:0)  0@5936r
		merge %vreg952:0@6000r into %vreg955:0@5936r --> @5936r
		erased:	6000r	%vreg952<def> = COPY %vreg955:sub_8bit; GR8:%vreg952 GR32:%vreg955
		updated: 6016B	MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg955:sub_8bit; mem:ST1[%k1] GR32:%vreg955
	Success: %vreg952:sub_8bit -> %vreg955
	Result = %vreg955 [5936r,6016r:0)  0@5936r
6160B	%vreg934<def> = COPY %vreg936; GR32:%vreg934,%vreg936
	Considering merging to GR32 with %vreg936 in %vreg934
		RHS = %vreg936 [6144r,6160r:0)  0@6144r
		LHS = %vreg934 [6160r,6176r:0)[6176r,6192r:1)  0@6160r 1@6176r
		merge %vreg934:0@6160r into %vreg936:0@6144r --> @6144r
		erased:	6160r	%vreg934<def> = COPY %vreg936; GR32:%vreg934,%vreg936
		updated: 6144B	%vreg934<def> = MOV32rm %vreg937, 1, %noreg, 60, %noreg; mem:LD4[%tPos176] GR32:%vreg934 GR64:%vreg937
	Success: %vreg936 -> %vreg934
	Result = %vreg934 [6144r,6176r:0)[6176r,6192r:1)  0@6144r 1@6176r
6304B	%vreg919<def> = COPY %vreg921; GR32:%vreg919,%vreg921
	Considering merging to GR32 with %vreg921 in %vreg919
		RHS = %vreg921 [6288r,6304r:0)  0@6288r
		LHS = %vreg919 [6304r,6320r:0)[6320r,6336r:1)  0@6304r 1@6320r
		merge %vreg919:0@6304r into %vreg921:0@6288r --> @6288r
		erased:	6304r	%vreg919<def> = COPY %vreg921; GR32:%vreg919,%vreg921
		updated: 6288B	%vreg919<def> = MOV32rm %vreg922, 1, %noreg, 60, %noreg; mem:LD4[%tPos182] GR32:%vreg919 GR64:%vreg922
	Success: %vreg921 -> %vreg919
	Result = %vreg919 [6288r,6320r:0)[6320r,6336r:1)  0@6288r 1@6320r
6336B	%vreg917<def> = COPY %vreg919; GR32:%vreg917,%vreg919
	Considering merging to GR32 with %vreg919 in %vreg917
		RHS = %vreg919 [6288r,6320r:0)[6320r,6336r:1)  0@6288r 1@6320r
		LHS = %vreg917 [6336r,6352r:0)[6352r,6368r:1)  0@6336r 1@6352r
		merge %vreg917:0@6336r into %vreg919:1@6320r --> @6320r
		erased:	6336r	%vreg917<def> = COPY %vreg919; GR32:%vreg917,%vreg919
		updated: 6288B	%vreg917<def> = MOV32rm %vreg922, 1, %noreg, 60, %noreg; mem:LD4[%tPos182] GR32:%vreg917 GR64:%vreg922
		updated: 6320B	%vreg917<def,tied1> = SHL32ri %vreg917<tied0>, 2, %EFLAGS<imp-def,dead>; GR32:%vreg917
	Success: %vreg919 -> %vreg917
	Result = %vreg917 [6288r,6320r:2)[6320r,6352r:0)[6352r,6368r:1)  0@6320r 1@6352r 2@6288r
6400B	%vreg915<def> = COPY %vreg924; GR32:%vreg915,%vreg924
	Considering merging to GR32 with %vreg924 in %vreg915
		RHS = %vreg924 [6256r,6400r:0)  0@6256r
		LHS = %vreg915 [6400r,6416r:0)[6416r,6432r:1)  0@6400r 1@6416r
		merge %vreg915:0@6400r into %vreg924:0@6256r --> @6256r
		erased:	6400r	%vreg915<def> = COPY %vreg924; GR32:%vreg915,%vreg924
		updated: 6256B	%vreg915<def> = MOVZX32rm8 %vreg928, 1, %vreg932, 0, %noreg; mem:LD1[%arrayidx180] GR32:%vreg915 GR64:%vreg928 GR64_NOSP:%vreg932
	Success: %vreg924 -> %vreg915
	Result = %vreg915 [6256r,6416r:0)[6416r,6432r:1)  0@6256r 1@6416r
6432B	%vreg912<def> = COPY %vreg915; GR32:%vreg912,%vreg915
	Considering merging to GR32 with %vreg915 in %vreg912
		RHS = %vreg915 [6256r,6416r:0)[6416r,6432r:1)  0@6256r 1@6416r
		LHS = %vreg912 [6432r,6448r:0)[6448r,6464r:1)  0@6432r 1@6448r
		merge %vreg912:0@6432r into %vreg915:1@6416r --> @6416r
		erased:	6432r	%vreg912<def> = COPY %vreg915; GR32:%vreg912,%vreg915
		updated: 6256B	%vreg912<def> = MOVZX32rm8 %vreg928, 1, %vreg932, 0, %noreg; mem:LD1[%arrayidx180] GR32:%vreg912 GR64:%vreg928 GR64_NOSP:%vreg932
		updated: 6416B	%vreg912<def,tied1> = SHR32rCL %vreg912<tied0>, %EFLAGS<imp-def,dead>, %CL<imp-use,kill>; GR32:%vreg912
	Success: %vreg915 -> %vreg912
	Result = %vreg912 [6256r,6416r:2)[6416r,6448r:0)[6448r,6464r:1)  0@6416r 1@6448r 2@6256r
6464B	%vreg910<def> = COPY %vreg912; GR32:%vreg910,%vreg912
	Considering merging to GR32 with %vreg910 in %vreg912
		RHS = %vreg910 [6464r,6480r:0)[6480r,6512r:1)  0@6464r 1@6480r
		LHS = %vreg912 [6256r,6416r:2)[6416r,6448r:0)[6448r,6464r:1)  0@6416r 1@6448r 2@6256r
		merge %vreg910:0@6464r into %vreg912:1@6448r --> @6448r
		erased:	6464r	%vreg910<def> = COPY %vreg912; GR32:%vreg910,%vreg912
		updated: 6480B	%vreg912<def,tied1> = SHL32ri %vreg912<tied0>, 16, %EFLAGS<imp-def,dead>; GR32:%vreg912
		updated: 6512B	%vreg908<def,tied1> = OR32rr %vreg908<tied0>, %vreg912, %EFLAGS<imp-def,dead>; GR32:%vreg908,%vreg912
	Success: %vreg910 -> %vreg912
	Result = %vreg912 [6256r,6416r:2)[6416r,6448r:0)[6448r,6480r:1)[6480r,6512r:3)  0@6416r 1@6448r 2@6256r 3@6480r
6496B	%vreg908<def> = COPY %vreg939; GR32:%vreg908,%vreg939
	Considering merging to GR32 with %vreg939 in %vreg908
		RHS = %vreg939 [6112r,6496r:0)  0@6112r
		LHS = %vreg908 [6496r,6512r:0)[6512r,6544r:1)  0@6496r 1@6512r
		merge %vreg908:0@6496r into %vreg939:0@6112r --> @6112r
		erased:	6496r	%vreg908<def> = COPY %vreg939; GR32:%vreg908,%vreg939
		updated: 6112B	%vreg908<def> = MOVZX32rm16 %vreg943, 2, %vreg947, 0, %noreg; mem:LD2[%arrayidx174] GR32:%vreg908 GR64:%vreg943 GR64_NOSP:%vreg947
	Success: %vreg939 -> %vreg908
	Result = %vreg908 [6112r,6512r:0)[6512r,6544r:1)  0@6112r 1@6512r
6736B	%vreg971<def> = COPY %vreg972; GR32:%vreg971,%vreg972
	Considering merging to GR32 with %vreg972 in %vreg971
		RHS = %vreg972 [6720r,6736r:0)  0@6720r
		LHS = %vreg971 [6736r,6752r:0)[6752r,6768r:1)  0@6736r 1@6752r
		merge %vreg971:0@6736r into %vreg972:0@6720r --> @6720r
		erased:	6736r	%vreg971<def> = COPY %vreg972; GR32:%vreg971,%vreg972
		updated: 6720B	%vreg971<def> = MOV32rm %vreg973, 1, %noreg, 28, %noreg; mem:LD4[%rTPos198] GR32:%vreg971 GR64:%vreg973
	Success: %vreg972 -> %vreg971
	Result = %vreg971 [6720r,6752r:0)[6752r,6768r:1)  0@6720r 1@6752r
7648B	%vreg1085<def> = COPY %vreg1086; GR64:%vreg1085,%vreg1086
	Considering merging to GR64 with %vreg1086 in %vreg1085
		RHS = %vreg1086 [7632r,7648r:0)  0@7632r
		LHS = %vreg1085 [7648r,7664r:0)[7664r,7712r:1)  0@7648r 1@7664r
		merge %vreg1085:0@7648r into %vreg1086:0@7632r --> @7632r
		erased:	7648r	%vreg1085<def> = COPY %vreg1086; GR64:%vreg1085,%vreg1086
		updated: 7632B	%vreg1085<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1085
	Success: %vreg1086 -> %vreg1085
	Result = %vreg1085 [7632r,7664r:0)[7664r,7712r:1)  0@7632r 1@7664r
7824B	%vreg1079<def> = COPY %vreg1082:sub_8bit; GR8:%vreg1079 GR32:%vreg1082
	Considering merging to GR32 with %vreg1079 in %vreg1082:sub_8bit
		RHS = %vreg1079 [7824r,7840r:0)  0@7824r
		LHS = %vreg1082 [7760r,7824r:0)  0@7760r
		merge %vreg1079:0@7824r into %vreg1082:0@7760r --> @7760r
		erased:	7824r	%vreg1079<def> = COPY %vreg1082:sub_8bit; GR8:%vreg1079 GR32:%vreg1082
		updated: 7840B	MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg1082:sub_8bit; mem:ST1[%k1] GR32:%vreg1082
	Success: %vreg1079:sub_8bit -> %vreg1082
	Result = %vreg1082 [7760r,7840r:0)  0@7760r
7984B	%vreg1061<def> = COPY %vreg1063; GR32:%vreg1061,%vreg1063
	Considering merging to GR32 with %vreg1063 in %vreg1061
		RHS = %vreg1063 [7968r,7984r:0)  0@7968r
		LHS = %vreg1061 [7984r,8000r:0)[8000r,8016r:1)  0@7984r 1@8000r
		merge %vreg1061:0@7984r into %vreg1063:0@7968r --> @7968r
		erased:	7984r	%vreg1061<def> = COPY %vreg1063; GR32:%vreg1061,%vreg1063
		updated: 7968B	%vreg1061<def> = MOV32rm %vreg1064, 1, %noreg, 60, %noreg; mem:LD4[%tPos243] GR32:%vreg1061 GR64:%vreg1064
	Success: %vreg1063 -> %vreg1061
	Result = %vreg1061 [7968r,8000r:0)[8000r,8016r:1)  0@7968r 1@8000r
8128B	%vreg1046<def> = COPY %vreg1048; GR32:%vreg1046,%vreg1048
	Considering merging to GR32 with %vreg1048 in %vreg1046
		RHS = %vreg1048 [8112r,8128r:0)  0@8112r
		LHS = %vreg1046 [8128r,8144r:0)[8144r,8160r:1)  0@8128r 1@8144r
		merge %vreg1046:0@8128r into %vreg1048:0@8112r --> @8112r
		erased:	8128r	%vreg1046<def> = COPY %vreg1048; GR32:%vreg1046,%vreg1048
		updated: 8112B	%vreg1046<def> = MOV32rm %vreg1049, 1, %noreg, 60, %noreg; mem:LD4[%tPos249] GR32:%vreg1046 GR64:%vreg1049
	Success: %vreg1048 -> %vreg1046
	Result = %vreg1046 [8112r,8144r:0)[8144r,8160r:1)  0@8112r 1@8144r
8160B	%vreg1044<def> = COPY %vreg1046; GR32:%vreg1044,%vreg1046
	Considering merging to GR32 with %vreg1046 in %vreg1044
		RHS = %vreg1046 [8112r,8144r:0)[8144r,8160r:1)  0@8112r 1@8144r
		LHS = %vreg1044 [8160r,8176r:0)[8176r,8192r:1)  0@8160r 1@8176r
		merge %vreg1044:0@8160r into %vreg1046:1@8144r --> @8144r
		erased:	8160r	%vreg1044<def> = COPY %vreg1046; GR32:%vreg1044,%vreg1046
		updated: 8112B	%vreg1044<def> = MOV32rm %vreg1049, 1, %noreg, 60, %noreg; mem:LD4[%tPos249] GR32:%vreg1044 GR64:%vreg1049
		updated: 8144B	%vreg1044<def,tied1> = SHL32ri %vreg1044<tied0>, 2, %EFLAGS<imp-def,dead>; GR32:%vreg1044
	Success: %vreg1046 -> %vreg1044
	Result = %vreg1044 [8112r,8144r:2)[8144r,8176r:0)[8176r,8192r:1)  0@8144r 1@8176r 2@8112r
8224B	%vreg1042<def> = COPY %vreg1051; GR32:%vreg1042,%vreg1051
	Considering merging to GR32 with %vreg1051 in %vreg1042
		RHS = %vreg1051 [8080r,8224r:0)  0@8080r
		LHS = %vreg1042 [8224r,8240r:0)[8240r,8256r:1)  0@8224r 1@8240r
		merge %vreg1042:0@8224r into %vreg1051:0@8080r --> @8080r
		erased:	8224r	%vreg1042<def> = COPY %vreg1051; GR32:%vreg1042,%vreg1051
		updated: 8080B	%vreg1042<def> = MOVZX32rm8 %vreg1055, 1, %vreg1059, 0, %noreg; mem:LD1[%arrayidx247] GR32:%vreg1042 GR64:%vreg1055 GR64_NOSP:%vreg1059
	Success: %vreg1051 -> %vreg1042
	Result = %vreg1042 [8080r,8240r:0)[8240r,8256r:1)  0@8080r 1@8240r
8256B	%vreg1039<def> = COPY %vreg1042; GR32:%vreg1039,%vreg1042
	Considering merging to GR32 with %vreg1042 in %vreg1039
		RHS = %vreg1042 [8080r,8240r:0)[8240r,8256r:1)  0@8080r 1@8240r
		LHS = %vreg1039 [8256r,8272r:0)[8272r,8288r:1)  0@8256r 1@8272r
		merge %vreg1039:0@8256r into %vreg1042:1@8240r --> @8240r
		erased:	8256r	%vreg1039<def> = COPY %vreg1042; GR32:%vreg1039,%vreg1042
		updated: 8080B	%vreg1039<def> = MOVZX32rm8 %vreg1055, 1, %vreg1059, 0, %noreg; mem:LD1[%arrayidx247] GR32:%vreg1039 GR64:%vreg1055 GR64_NOSP:%vreg1059
		updated: 8240B	%vreg1039<def,tied1> = SHR32rCL %vreg1039<tied0>, %EFLAGS<imp-def,dead>, %CL<imp-use,kill>; GR32:%vreg1039
	Success: %vreg1042 -> %vreg1039
	Result = %vreg1039 [8080r,8240r:2)[8240r,8272r:0)[8272r,8288r:1)  0@8240r 1@8272r 2@8080r
8288B	%vreg1037<def> = COPY %vreg1039; GR32:%vreg1037,%vreg1039
	Considering merging to GR32 with %vreg1037 in %vreg1039
		RHS = %vreg1037 [8288r,8304r:0)[8304r,8336r:1)  0@8288r 1@8304r
		LHS = %vreg1039 [8080r,8240r:2)[8240r,8272r:0)[8272r,8288r:1)  0@8240r 1@8272r 2@8080r
		merge %vreg1037:0@8288r into %vreg1039:1@8272r --> @8272r
		erased:	8288r	%vreg1037<def> = COPY %vreg1039; GR32:%vreg1037,%vreg1039
		updated: 8304B	%vreg1039<def,tied1> = SHL32ri %vreg1039<tied0>, 16, %EFLAGS<imp-def,dead>; GR32:%vreg1039
		updated: 8336B	%vreg1035<def,tied1> = OR32rr %vreg1035<tied0>, %vreg1039, %EFLAGS<imp-def,dead>; GR32:%vreg1035,%vreg1039
	Success: %vreg1037 -> %vreg1039
	Result = %vreg1039 [8080r,8240r:2)[8240r,8272r:0)[8272r,8304r:1)[8304r,8336r:3)  0@8240r 1@8272r 2@8080r 3@8304r
8320B	%vreg1035<def> = COPY %vreg1066; GR32:%vreg1035,%vreg1066
	Considering merging to GR32 with %vreg1066 in %vreg1035
		RHS = %vreg1066 [7936r,8320r:0)  0@7936r
		LHS = %vreg1035 [8320r,8336r:0)[8336r,8368r:1)  0@8320r 1@8336r
		merge %vreg1035:0@8320r into %vreg1066:0@7936r --> @7936r
		erased:	8320r	%vreg1035<def> = COPY %vreg1066; GR32:%vreg1035,%vreg1066
		updated: 7936B	%vreg1035<def> = MOVZX32rm16 %vreg1070, 2, %vreg1074, 0, %noreg; mem:LD2[%arrayidx241] GR32:%vreg1035 GR64:%vreg1070 GR64_NOSP:%vreg1074
	Success: %vreg1066 -> %vreg1035
	Result = %vreg1035 [7936r,8336r:0)[8336r,8368r:1)  0@7936r 1@8336r
8560B	%vreg1096<def> = COPY %vreg1097; GR32:%vreg1096,%vreg1097
	Considering merging to GR32 with %vreg1097 in %vreg1096
		RHS = %vreg1097 [8544r,8560r:0)  0@8544r
		LHS = %vreg1096 [8560r,8576r:0)[8576r,8592r:1)  0@8560r 1@8576r
		merge %vreg1096:0@8560r into %vreg1097:0@8544r --> @8544r
		erased:	8560r	%vreg1096<def> = COPY %vreg1097; GR32:%vreg1096,%vreg1097
		updated: 8544B	%vreg1096<def> = MOV32rm %vreg1098, 1, %noreg, 28, %noreg; mem:LD4[%rTPos265] GR32:%vreg1096 GR64:%vreg1098
	Success: %vreg1097 -> %vreg1096
	Result = %vreg1096 [8544r,8576r:0)[8576r,8592r:1)  0@8544r 1@8576r
10128B	%vreg1212<def> = COPY %vreg1213; GR32:%vreg1212,%vreg1213
	Considering merging to GR32 with %vreg1213 in %vreg1212
		RHS = %vreg1213 [10112r,10128r:0)  0@10112r
		LHS = %vreg1212 [10128r,10144r:0)[10144r,10160r:1)  0@10128r 1@10144r
		merge %vreg1212:0@10128r into %vreg1213:0@10112r --> @10112r
		erased:	10128r	%vreg1212<def> = COPY %vreg1213; GR32:%vreg1212,%vreg1213
		updated: 10112B	%vreg1212<def> = MOV32rm %vreg1214, 1, %noreg, 28, %noreg; mem:LD4[%rTPos320] GR32:%vreg1212 GR64:%vreg1214
	Success: %vreg1213 -> %vreg1212
	Result = %vreg1212 [10112r,10144r:0)[10144r,10160r:1)  0@10112r 1@10144r
10384B	%vreg1247<def> = COPY %vreg1248; GR32:%vreg1247,%vreg1248
	Considering merging to GR32 with %vreg1248 in %vreg1247
		RHS = %vreg1248 [10368r,10384r:0)  0@10368r
		LHS = %vreg1247 [10384r,10400r:0)[10400r,10416r:1)  0@10384r 1@10400r
		merge %vreg1247:0@10384r into %vreg1248:0@10368r --> @10368r
		erased:	10384r	%vreg1247<def> = COPY %vreg1248; GR32:%vreg1247,%vreg1248
		updated: 10368B	%vreg1247<def> = MOV32rm %vreg1249, 1, %noreg, 24, %noreg; mem:LD4[%rNToGo329] GR32:%vreg1247 GR64:%vreg1249
	Success: %vreg1248 -> %vreg1247
	Result = %vreg1247 [10368r,10400r:0)[10400r,10416r:1)  0@10368r 1@10400r
10464B	%vreg1241<def> = COPY %vreg1239; GR32:%vreg1241,%vreg1239
	Considering merging to GR32 with %vreg1239 in %vreg1241
		RHS = %vreg1239 [10320r,10464r:0)  0@10320r
		LHS = %vreg1241 [10464r,10480r:0)[10480r,10512r:1)  0@10464r 1@10480r
		merge %vreg1241:0@10464r into %vreg1239:0@10320r --> @10320r
		erased:	10464r	%vreg1241<def> = COPY %vreg1239; GR32:%vreg1241,%vreg1239
		updated: 10320B	%vreg1241<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg1241
	Success: %vreg1239 -> %vreg1241
	Result = %vreg1241 [10320r,10480r:0)[10480r,10512r:1)  0@10320r 1@10480r
10512B	%vreg1236<def> = COPY %vreg1241; GR32:%vreg1236,%vreg1241
	Considering merging to GR32 with %vreg1241 in %vreg1236
		RHS = %vreg1241 [10320r,10480r:0)[10480r,10512r:1)  0@10320r 1@10480r
		LHS = %vreg1236 [10512r,10528r:0)[10528r,10544r:1)  0@10512r 1@10528r
		merge %vreg1236:0@10512r into %vreg1241:1@10480r --> @10480r
		erased:	10512r	%vreg1236<def> = COPY %vreg1241; GR32:%vreg1236,%vreg1241
		updated: 10320B	%vreg1236<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg1236
		updated: 10480B	%vreg1236<def,tied1> = CMOVE32rr %vreg1236<tied0>, %vreg1240, %EFLAGS<imp-use,kill>; GR32:%vreg1236,%vreg1240
	Success: %vreg1241 -> %vreg1236
	Result = %vreg1236 [10320r,10480r:2)[10480r,10528r:0)[10528r,10544r:1)  0@10480r 1@10528r 2@10320r
10592B	%vreg1229<def> = COPY %vreg1230; GR32:%vreg1229,%vreg1230
	Considering merging to GR32 with %vreg1230 in %vreg1229
		RHS = %vreg1230 [10576r,10592r:0)  0@10576r
		LHS = %vreg1229 [10592r,10608r:0)[10608r,10624r:1)  0@10592r 1@10608r
		merge %vreg1229:0@10592r into %vreg1230:0@10576r --> @10576r
		erased:	10592r	%vreg1229<def> = COPY %vreg1230; GR32:%vreg1229,%vreg1230
		updated: 10576B	%vreg1229<def> = MOV32rm %vreg1231, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used337] GR32:%vreg1229 GR64:%vreg1231
	Success: %vreg1230 -> %vreg1229
	Result = %vreg1229 [10576r,10608r:0)[10608r,10624r:1)  0@10576r 1@10608r
12000B	%vreg99<def> = COPY %vreg101; GR32:%vreg99,%vreg101
	Considering merging to GR32 with %vreg101 in %vreg99
		RHS = %vreg101 [11984r,12000r:0)  0@11984r
		LHS = %vreg99 [12000r,12016r:0)[12016r,12032r:1)  0@12000r 1@12016r
		merge %vreg99:0@12000r into %vreg101:0@11984r --> @11984r
		erased:	12000r	%vreg99<def> = COPY %vreg101; GR32:%vreg99,%vreg101
		updated: 11984B	%vreg99<def> = MOV32rm %vreg102, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock389] GR32:%vreg99 GR64:%vreg102
	Success: %vreg101 -> %vreg99
	Result = %vreg99 [11984r,12016r:0)[12016r,12032r:1)  0@11984r 1@12016r
12192B	%vreg109<def> = COPY %vreg111; GR32:%vreg109,%vreg111
	Considering merging to GR32 with %vreg111 in %vreg109
		RHS = %vreg111 [12176r,12192r:0)  0@12176r
		LHS = %vreg109 [12192r,12208r:0)[12208r,12224r:1)  0@12192r 1@12208r
		merge %vreg109:0@12192r into %vreg111:0@12176r --> @12176r
		erased:	12192r	%vreg109<def> = COPY %vreg111; GR32:%vreg109,%vreg111
		updated: 12176B	%vreg109<def> = MOV32rm %vreg112, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock396] GR32:%vreg109 GR64:%vreg112
	Success: %vreg111 -> %vreg109
	Result = %vreg109 [12176r,12208r:0)[12208r,12224r:1)  0@12176r 1@12208r
12384B	%vreg196<def> = COPY %vreg198:sub_8bit; GR8:%vreg196 GR32:%vreg198
	Considering merging to GR32 with %vreg196 in %vreg198:sub_8bit
		RHS = %vreg196 [12384r,12416r:0)  0@12384r
		LHS = %vreg198 [12368r,12384r:0)  0@12368r
		merge %vreg196:0@12384r into %vreg198:0@12368r --> @12368r
		erased:	12384r	%vreg196<def> = COPY %vreg198:sub_8bit; GR8:%vreg196 GR32:%vreg198
		updated: 12416B	MOV8mr %vreg194, 1, %noreg, 12, %noreg, %vreg198:sub_8bit; mem:ST1[%state_out_ch405] GR64:%vreg194 GR32:%vreg198
	Success: %vreg196:sub_8bit -> %vreg198
	Result = %vreg198 [12368r,12416r:0)  0@12368r
12480B	%vreg187<def> = COPY %vreg188; GR64:%vreg187,%vreg188
	Considering merging to GR64 with %vreg188 in %vreg187
		RHS = %vreg188 [12464r,12480r:0)  0@12464r
		LHS = %vreg187 [12480r,12496r:0)[12496r,12544r:1)  0@12480r 1@12496r
		merge %vreg187:0@12480r into %vreg188:0@12464r --> @12464r
		erased:	12480r	%vreg187<def> = COPY %vreg188; GR64:%vreg187,%vreg188
		updated: 12464B	%vreg187<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg187
	Success: %vreg188 -> %vreg187
	Result = %vreg187 [12464r,12496r:0)[12496r,12544r:1)  0@12464r 1@12496r
12656B	%vreg181<def> = COPY %vreg184:sub_8bit; GR8:%vreg181 GR32:%vreg184
	Considering merging to GR32 with %vreg181 in %vreg184:sub_8bit
		RHS = %vreg181 [12656r,12672r:0)  0@12656r
		LHS = %vreg184 [12592r,12656r:0)  0@12592r
		merge %vreg181:0@12656r into %vreg184:0@12592r --> @12592r
		erased:	12656r	%vreg181<def> = COPY %vreg184:sub_8bit; GR8:%vreg181 GR32:%vreg184
		updated: 12672B	MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg184:sub_8bit; mem:ST1[%k1] GR32:%vreg184
	Success: %vreg181:sub_8bit -> %vreg184
	Result = %vreg184 [12592r,12672r:0)  0@12592r
12816B	%vreg163<def> = COPY %vreg165; GR32:%vreg163,%vreg165
	Considering merging to GR32 with %vreg165 in %vreg163
		RHS = %vreg165 [12800r,12816r:0)  0@12800r
		LHS = %vreg163 [12816r,12832r:0)[12832r,12848r:1)  0@12816r 1@12832r
		merge %vreg163:0@12816r into %vreg165:0@12800r --> @12800r
		erased:	12816r	%vreg163<def> = COPY %vreg165; GR32:%vreg163,%vreg165
		updated: 12800B	%vreg163<def> = MOV32rm %vreg166, 1, %noreg, 60, %noreg; mem:LD4[%tPos416] GR32:%vreg163 GR64:%vreg166
	Success: %vreg165 -> %vreg163
	Result = %vreg163 [12800r,12832r:0)[12832r,12848r:1)  0@12800r 1@12832r
12960B	%vreg148<def> = COPY %vreg150; GR32:%vreg148,%vreg150
	Considering merging to GR32 with %vreg150 in %vreg148
		RHS = %vreg150 [12944r,12960r:0)  0@12944r
		LHS = %vreg148 [12960r,12976r:0)[12976r,12992r:1)  0@12960r 1@12976r
		merge %vreg148:0@12960r into %vreg150:0@12944r --> @12944r
		erased:	12960r	%vreg148<def> = COPY %vreg150; GR32:%vreg148,%vreg150
		updated: 12944B	%vreg148<def> = MOV32rm %vreg151, 1, %noreg, 60, %noreg; mem:LD4[%tPos422] GR32:%vreg148 GR64:%vreg151
	Success: %vreg150 -> %vreg148
	Result = %vreg148 [12944r,12976r:0)[12976r,12992r:1)  0@12944r 1@12976r
12992B	%vreg146<def> = COPY %vreg148; GR32:%vreg146,%vreg148
	Considering merging to GR32 with %vreg148 in %vreg146
		RHS = %vreg148 [12944r,12976r:0)[12976r,12992r:1)  0@12944r 1@12976r
		LHS = %vreg146 [12992r,13008r:0)[13008r,13024r:1)  0@12992r 1@13008r
		merge %vreg146:0@12992r into %vreg148:1@12976r --> @12976r
		erased:	12992r	%vreg146<def> = COPY %vreg148; GR32:%vreg146,%vreg148
		updated: 12944B	%vreg146<def> = MOV32rm %vreg151, 1, %noreg, 60, %noreg; mem:LD4[%tPos422] GR32:%vreg146 GR64:%vreg151
		updated: 12976B	%vreg146<def,tied1> = SHL32ri %vreg146<tied0>, 2, %EFLAGS<imp-def,dead>; GR32:%vreg146
	Success: %vreg148 -> %vreg146
	Result = %vreg146 [12944r,12976r:2)[12976r,13008r:0)[13008r,13024r:1)  0@12976r 1@13008r 2@12944r
13056B	%vreg144<def> = COPY %vreg153; GR32:%vreg144,%vreg153
	Considering merging to GR32 with %vreg153 in %vreg144
		RHS = %vreg153 [12912r,13056r:0)  0@12912r
		LHS = %vreg144 [13056r,13072r:0)[13072r,13088r:1)  0@13056r 1@13072r
		merge %vreg144:0@13056r into %vreg153:0@12912r --> @12912r
		erased:	13056r	%vreg144<def> = COPY %vreg153; GR32:%vreg144,%vreg153
		updated: 12912B	%vreg144<def> = MOVZX32rm8 %vreg157, 1, %vreg161, 0, %noreg; mem:LD1[%arrayidx420] GR32:%vreg144 GR64:%vreg157 GR64_NOSP:%vreg161
	Success: %vreg153 -> %vreg144
	Result = %vreg144 [12912r,13072r:0)[13072r,13088r:1)  0@12912r 1@13072r
13088B	%vreg141<def> = COPY %vreg144; GR32:%vreg141,%vreg144
	Considering merging to GR32 with %vreg144 in %vreg141
		RHS = %vreg144 [12912r,13072r:0)[13072r,13088r:1)  0@12912r 1@13072r
		LHS = %vreg141 [13088r,13104r:0)[13104r,13120r:1)  0@13088r 1@13104r
		merge %vreg141:0@13088r into %vreg144:1@13072r --> @13072r
		erased:	13088r	%vreg141<def> = COPY %vreg144; GR32:%vreg141,%vreg144
		updated: 12912B	%vreg141<def> = MOVZX32rm8 %vreg157, 1, %vreg161, 0, %noreg; mem:LD1[%arrayidx420] GR32:%vreg141 GR64:%vreg157 GR64_NOSP:%vreg161
		updated: 13072B	%vreg141<def,tied1> = SHR32rCL %vreg141<tied0>, %EFLAGS<imp-def,dead>, %CL<imp-use,kill>; GR32:%vreg141
	Success: %vreg144 -> %vreg141
	Result = %vreg141 [12912r,13072r:2)[13072r,13104r:0)[13104r,13120r:1)  0@13072r 1@13104r 2@12912r
13120B	%vreg139<def> = COPY %vreg141; GR32:%vreg139,%vreg141
	Considering merging to GR32 with %vreg139 in %vreg141
		RHS = %vreg139 [13120r,13136r:0)[13136r,13168r:1)  0@13120r 1@13136r
		LHS = %vreg141 [12912r,13072r:2)[13072r,13104r:0)[13104r,13120r:1)  0@13072r 1@13104r 2@12912r
		merge %vreg139:0@13120r into %vreg141:1@13104r --> @13104r
		erased:	13120r	%vreg139<def> = COPY %vreg141; GR32:%vreg139,%vreg141
		updated: 13136B	%vreg141<def,tied1> = SHL32ri %vreg141<tied0>, 16, %EFLAGS<imp-def,dead>; GR32:%vreg141
		updated: 13168B	%vreg137<def,tied1> = OR32rr %vreg137<tied0>, %vreg141, %EFLAGS<imp-def,dead>; GR32:%vreg137,%vreg141
	Success: %vreg139 -> %vreg141
	Result = %vreg141 [12912r,13072r:2)[13072r,13104r:0)[13104r,13136r:1)[13136r,13168r:3)  0@13072r 1@13104r 2@12912r 3@13136r
13152B	%vreg137<def> = COPY %vreg168; GR32:%vreg137,%vreg168
	Considering merging to GR32 with %vreg168 in %vreg137
		RHS = %vreg168 [12768r,13152r:0)  0@12768r
		LHS = %vreg137 [13152r,13168r:0)[13168r,13200r:1)  0@13152r 1@13168r
		merge %vreg137:0@13152r into %vreg168:0@12768r --> @12768r
		erased:	13152r	%vreg137<def> = COPY %vreg168; GR32:%vreg137,%vreg168
		updated: 12768B	%vreg137<def> = MOVZX32rm16 %vreg172, 2, %vreg176, 0, %noreg; mem:LD2[%arrayidx414] GR32:%vreg137 GR64:%vreg172 GR64_NOSP:%vreg176
	Success: %vreg168 -> %vreg137
	Result = %vreg137 [12768r,13168r:0)[13168r,13200r:1)  0@12768r 1@13168r
13248B	%vreg129<def> = COPY %vreg130; GR32:%vreg129,%vreg130
	Considering merging to GR32 with %vreg130 in %vreg129
		RHS = %vreg130 [13232r,13248r:0)  0@13232r
		LHS = %vreg129 [13248r,13264r:0)[13264r,13280r:1)  0@13248r 1@13264r
		merge %vreg129:0@13248r into %vreg130:0@13232r --> @13232r
		erased:	13248r	%vreg129<def> = COPY %vreg130; GR32:%vreg129,%vreg130
		updated: 13232B	%vreg129<def> = MOV32rm %vreg131, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used430] GR32:%vreg129 GR64:%vreg131
	Success: %vreg130 -> %vreg129
	Result = %vreg129 [13232r,13264r:0)[13264r,13280r:1)  0@13232r 1@13264r
13360B	%vreg119<def> = COPY %vreg121; GR32:%vreg119,%vreg121
	Considering merging to GR32 with %vreg121 in %vreg119
		RHS = %vreg121 [13344r,13360r:0)  0@13344r
		LHS = %vreg119 [13360r,13376r:0)[13376r,13392r:1)  0@13360r 1@13376r
		merge %vreg119:0@13360r into %vreg121:0@13344r --> @13344r
		erased:	13360r	%vreg119<def> = COPY %vreg121; GR32:%vreg119,%vreg121
		updated: 13344B	%vreg119<def> = MOV32rm %vreg122, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock433] GR32:%vreg119 GR64:%vreg122
	Success: %vreg121 -> %vreg119
	Result = %vreg119 [13344r,13376r:0)[13376r,13392r:1)  0@13344r 1@13376r
13712B	%vreg279<def> = COPY %vreg280; GR64:%vreg279,%vreg280
	Considering merging to GR64 with %vreg280 in %vreg279
		RHS = %vreg280 [13696r,13712r:0)  0@13696r
		LHS = %vreg279 [13712r,13728r:0)[13728r,13776r:1)  0@13712r 1@13728r
		merge %vreg279:0@13712r into %vreg280:0@13696r --> @13696r
		erased:	13712r	%vreg279<def> = COPY %vreg280; GR64:%vreg279,%vreg280
		updated: 13696B	%vreg279<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg279
	Success: %vreg280 -> %vreg279
	Result = %vreg279 [13696r,13728r:0)[13728r,13776r:1)  0@13696r 1@13728r
13888B	%vreg273<def> = COPY %vreg276:sub_8bit; GR8:%vreg273 GR32:%vreg276
	Considering merging to GR32 with %vreg273 in %vreg276:sub_8bit
		RHS = %vreg273 [13888r,13904r:0)  0@13888r
		LHS = %vreg276 [13824r,13888r:0)  0@13824r
		merge %vreg273:0@13888r into %vreg276:0@13824r --> @13824r
		erased:	13888r	%vreg273<def> = COPY %vreg276:sub_8bit; GR8:%vreg273 GR32:%vreg276
		updated: 13904B	MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg276:sub_8bit; mem:ST1[%k1] GR32:%vreg276
	Success: %vreg273:sub_8bit -> %vreg276
	Result = %vreg276 [13824r,13904r:0)  0@13824r
14048B	%vreg255<def> = COPY %vreg257; GR32:%vreg255,%vreg257
	Considering merging to GR32 with %vreg257 in %vreg255
		RHS = %vreg257 [14032r,14048r:0)  0@14032r
		LHS = %vreg255 [14048r,14064r:0)[14064r,14080r:1)  0@14048r 1@14064r
		merge %vreg255:0@14048r into %vreg257:0@14032r --> @14032r
		erased:	14048r	%vreg255<def> = COPY %vreg257; GR32:%vreg255,%vreg257
		updated: 14032B	%vreg255<def> = MOV32rm %vreg258, 1, %noreg, 60, %noreg; mem:LD4[%tPos458] GR32:%vreg255 GR64:%vreg258
	Success: %vreg257 -> %vreg255
	Result = %vreg255 [14032r,14064r:0)[14064r,14080r:1)  0@14032r 1@14064r
14192B	%vreg240<def> = COPY %vreg242; GR32:%vreg240,%vreg242
	Considering merging to GR32 with %vreg242 in %vreg240
		RHS = %vreg242 [14176r,14192r:0)  0@14176r
		LHS = %vreg240 [14192r,14208r:0)[14208r,14224r:1)  0@14192r 1@14208r
		merge %vreg240:0@14192r into %vreg242:0@14176r --> @14176r
		erased:	14192r	%vreg240<def> = COPY %vreg242; GR32:%vreg240,%vreg242
		updated: 14176B	%vreg240<def> = MOV32rm %vreg243, 1, %noreg, 60, %noreg; mem:LD4[%tPos464] GR32:%vreg240 GR64:%vreg243
	Success: %vreg242 -> %vreg240
	Result = %vreg240 [14176r,14208r:0)[14208r,14224r:1)  0@14176r 1@14208r
14224B	%vreg238<def> = COPY %vreg240; GR32:%vreg238,%vreg240
	Considering merging to GR32 with %vreg240 in %vreg238
		RHS = %vreg240 [14176r,14208r:0)[14208r,14224r:1)  0@14176r 1@14208r
		LHS = %vreg238 [14224r,14240r:0)[14240r,14256r:1)  0@14224r 1@14240r
		merge %vreg238:0@14224r into %vreg240:1@14208r --> @14208r
		erased:	14224r	%vreg238<def> = COPY %vreg240; GR32:%vreg238,%vreg240
		updated: 14176B	%vreg238<def> = MOV32rm %vreg243, 1, %noreg, 60, %noreg; mem:LD4[%tPos464] GR32:%vreg238 GR64:%vreg243
		updated: 14208B	%vreg238<def,tied1> = SHL32ri %vreg238<tied0>, 2, %EFLAGS<imp-def,dead>; GR32:%vreg238
	Success: %vreg240 -> %vreg238
	Result = %vreg238 [14176r,14208r:2)[14208r,14240r:0)[14240r,14256r:1)  0@14208r 1@14240r 2@14176r
14288B	%vreg236<def> = COPY %vreg245; GR32:%vreg236,%vreg245
	Considering merging to GR32 with %vreg245 in %vreg236
		RHS = %vreg245 [14144r,14288r:0)  0@14144r
		LHS = %vreg236 [14288r,14304r:0)[14304r,14320r:1)  0@14288r 1@14304r
		merge %vreg236:0@14288r into %vreg245:0@14144r --> @14144r
		erased:	14288r	%vreg236<def> = COPY %vreg245; GR32:%vreg236,%vreg245
		updated: 14144B	%vreg236<def> = MOVZX32rm8 %vreg249, 1, %vreg253, 0, %noreg; mem:LD1[%arrayidx462] GR32:%vreg236 GR64:%vreg249 GR64_NOSP:%vreg253
	Success: %vreg245 -> %vreg236
	Result = %vreg236 [14144r,14304r:0)[14304r,14320r:1)  0@14144r 1@14304r
14320B	%vreg233<def> = COPY %vreg236; GR32:%vreg233,%vreg236
	Considering merging to GR32 with %vreg236 in %vreg233
		RHS = %vreg236 [14144r,14304r:0)[14304r,14320r:1)  0@14144r 1@14304r
		LHS = %vreg233 [14320r,14336r:0)[14336r,14352r:1)  0@14320r 1@14336r
		merge %vreg233:0@14320r into %vreg236:1@14304r --> @14304r
		erased:	14320r	%vreg233<def> = COPY %vreg236; GR32:%vreg233,%vreg236
		updated: 14144B	%vreg233<def> = MOVZX32rm8 %vreg249, 1, %vreg253, 0, %noreg; mem:LD1[%arrayidx462] GR32:%vreg233 GR64:%vreg249 GR64_NOSP:%vreg253
		updated: 14304B	%vreg233<def,tied1> = SHR32rCL %vreg233<tied0>, %EFLAGS<imp-def,dead>, %CL<imp-use,kill>; GR32:%vreg233
	Success: %vreg236 -> %vreg233
	Result = %vreg233 [14144r,14304r:2)[14304r,14336r:0)[14336r,14352r:1)  0@14304r 1@14336r 2@14144r
14352B	%vreg231<def> = COPY %vreg233; GR32:%vreg231,%vreg233
	Considering merging to GR32 with %vreg231 in %vreg233
		RHS = %vreg231 [14352r,14368r:0)[14368r,14400r:1)  0@14352r 1@14368r
		LHS = %vreg233 [14144r,14304r:2)[14304r,14336r:0)[14336r,14352r:1)  0@14304r 1@14336r 2@14144r
		merge %vreg231:0@14352r into %vreg233:1@14336r --> @14336r
		erased:	14352r	%vreg231<def> = COPY %vreg233; GR32:%vreg231,%vreg233
		updated: 14368B	%vreg233<def,tied1> = SHL32ri %vreg233<tied0>, 16, %EFLAGS<imp-def,dead>; GR32:%vreg233
		updated: 14400B	%vreg229<def,tied1> = OR32rr %vreg229<tied0>, %vreg233, %EFLAGS<imp-def,dead>; GR32:%vreg229,%vreg233
	Success: %vreg231 -> %vreg233
	Result = %vreg233 [14144r,14304r:2)[14304r,14336r:0)[14336r,14368r:1)[14368r,14400r:3)  0@14304r 1@14336r 2@14144r 3@14368r
14384B	%vreg229<def> = COPY %vreg260; GR32:%vreg229,%vreg260
	Considering merging to GR32 with %vreg260 in %vreg229
		RHS = %vreg260 [14000r,14384r:0)  0@14000r
		LHS = %vreg229 [14384r,14400r:0)[14400r,14432r:1)  0@14384r 1@14400r
		merge %vreg229:0@14384r into %vreg260:0@14000r --> @14000r
		erased:	14384r	%vreg229<def> = COPY %vreg260; GR32:%vreg229,%vreg260
		updated: 14000B	%vreg229<def> = MOVZX32rm16 %vreg264, 2, %vreg268, 0, %noreg; mem:LD2[%arrayidx456] GR32:%vreg229 GR64:%vreg264 GR64_NOSP:%vreg268
	Success: %vreg260 -> %vreg229
	Result = %vreg229 [14000r,14400r:0)[14400r,14432r:1)  0@14000r 1@14400r
14480B	%vreg221<def> = COPY %vreg222; GR32:%vreg221,%vreg222
	Considering merging to GR32 with %vreg222 in %vreg221
		RHS = %vreg222 [14464r,14480r:0)  0@14464r
		LHS = %vreg221 [14480r,14496r:0)[14496r,14512r:1)  0@14480r 1@14496r
		merge %vreg221:0@14480r into %vreg222:0@14464r --> @14464r
		erased:	14480r	%vreg221<def> = COPY %vreg222; GR32:%vreg221,%vreg222
		updated: 14464B	%vreg221<def> = MOV32rm %vreg223, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used472] GR32:%vreg221 GR64:%vreg223
	Success: %vreg222 -> %vreg221
	Result = %vreg221 [14464r,14496r:0)[14496r,14512r:1)  0@14464r 1@14496r
14592B	%vreg211<def> = COPY %vreg213; GR32:%vreg211,%vreg213
	Considering merging to GR32 with %vreg213 in %vreg211
		RHS = %vreg213 [14576r,14592r:0)  0@14576r
		LHS = %vreg211 [14592r,14608r:0)[14608r,14624r:1)  0@14592r 1@14608r
		merge %vreg211:0@14592r into %vreg213:0@14576r --> @14576r
		erased:	14592r	%vreg211<def> = COPY %vreg213; GR32:%vreg211,%vreg213
		updated: 14576B	%vreg211<def> = MOV32rm %vreg214, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock475] GR32:%vreg211 GR64:%vreg214
	Success: %vreg213 -> %vreg211
	Result = %vreg211 [14576r,14608r:0)[14608r,14624r:1)  0@14576r 1@14608r
14944B	%vreg363<def> = COPY %vreg364; GR64:%vreg363,%vreg364
	Considering merging to GR64 with %vreg364 in %vreg363
		RHS = %vreg364 [14928r,14944r:0)  0@14928r
		LHS = %vreg363 [14944r,14960r:0)[14960r,15008r:1)  0@14944r 1@14960r
		merge %vreg363:0@14944r into %vreg364:0@14928r --> @14928r
		erased:	14944r	%vreg363<def> = COPY %vreg364; GR64:%vreg363,%vreg364
		updated: 14928B	%vreg363<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg363
	Success: %vreg364 -> %vreg363
	Result = %vreg363 [14928r,14960r:0)[14960r,15008r:1)  0@14928r 1@14960r
15120B	%vreg357<def> = COPY %vreg360:sub_8bit; GR8:%vreg357 GR32:%vreg360
	Considering merging to GR32 with %vreg357 in %vreg360:sub_8bit
		RHS = %vreg357 [15120r,15136r:0)  0@15120r
		LHS = %vreg360 [15056r,15120r:0)  0@15056r
		merge %vreg357:0@15120r into %vreg360:0@15056r --> @15056r
		erased:	15120r	%vreg357<def> = COPY %vreg360:sub_8bit; GR8:%vreg357 GR32:%vreg360
		updated: 15136B	MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg360:sub_8bit; mem:ST1[%k1] GR32:%vreg360
	Success: %vreg357:sub_8bit -> %vreg360
	Result = %vreg360 [15056r,15136r:0)  0@15056r
15280B	%vreg339<def> = COPY %vreg341; GR32:%vreg339,%vreg341
	Considering merging to GR32 with %vreg341 in %vreg339
		RHS = %vreg341 [15264r,15280r:0)  0@15264r
		LHS = %vreg339 [15280r,15296r:0)[15296r,15312r:1)  0@15280r 1@15296r
		merge %vreg339:0@15280r into %vreg341:0@15264r --> @15264r
		erased:	15280r	%vreg339<def> = COPY %vreg341; GR32:%vreg339,%vreg341
		updated: 15264B	%vreg339<def> = MOV32rm %vreg342, 1, %noreg, 60, %noreg; mem:LD4[%tPos500] GR32:%vreg339 GR64:%vreg342
	Success: %vreg341 -> %vreg339
	Result = %vreg339 [15264r,15296r:0)[15296r,15312r:1)  0@15264r 1@15296r
15424B	%vreg324<def> = COPY %vreg326; GR32:%vreg324,%vreg326
	Considering merging to GR32 with %vreg326 in %vreg324
		RHS = %vreg326 [15408r,15424r:0)  0@15408r
		LHS = %vreg324 [15424r,15440r:0)[15440r,15456r:1)  0@15424r 1@15440r
		merge %vreg324:0@15424r into %vreg326:0@15408r --> @15408r
		erased:	15424r	%vreg324<def> = COPY %vreg326; GR32:%vreg324,%vreg326
		updated: 15408B	%vreg324<def> = MOV32rm %vreg327, 1, %noreg, 60, %noreg; mem:LD4[%tPos506] GR32:%vreg324 GR64:%vreg327
	Success: %vreg326 -> %vreg324
	Result = %vreg324 [15408r,15440r:0)[15440r,15456r:1)  0@15408r 1@15440r
15456B	%vreg322<def> = COPY %vreg324; GR32:%vreg322,%vreg324
	Considering merging to GR32 with %vreg324 in %vreg322
		RHS = %vreg324 [15408r,15440r:0)[15440r,15456r:1)  0@15408r 1@15440r
		LHS = %vreg322 [15456r,15472r:0)[15472r,15488r:1)  0@15456r 1@15472r
		merge %vreg322:0@15456r into %vreg324:1@15440r --> @15440r
		erased:	15456r	%vreg322<def> = COPY %vreg324; GR32:%vreg322,%vreg324
		updated: 15408B	%vreg322<def> = MOV32rm %vreg327, 1, %noreg, 60, %noreg; mem:LD4[%tPos506] GR32:%vreg322 GR64:%vreg327
		updated: 15440B	%vreg322<def,tied1> = SHL32ri %vreg322<tied0>, 2, %EFLAGS<imp-def,dead>; GR32:%vreg322
	Success: %vreg324 -> %vreg322
	Result = %vreg322 [15408r,15440r:2)[15440r,15472r:0)[15472r,15488r:1)  0@15440r 1@15472r 2@15408r
15520B	%vreg320<def> = COPY %vreg329; GR32:%vreg320,%vreg329
	Considering merging to GR32 with %vreg329 in %vreg320
		RHS = %vreg329 [15376r,15520r:0)  0@15376r
		LHS = %vreg320 [15520r,15536r:0)[15536r,15552r:1)  0@15520r 1@15536r
		merge %vreg320:0@15520r into %vreg329:0@15376r --> @15376r
		erased:	15520r	%vreg320<def> = COPY %vreg329; GR32:%vreg320,%vreg329
		updated: 15376B	%vreg320<def> = MOVZX32rm8 %vreg333, 1, %vreg337, 0, %noreg; mem:LD1[%arrayidx504] GR32:%vreg320 GR64:%vreg333 GR64_NOSP:%vreg337
	Success: %vreg329 -> %vreg320
	Result = %vreg320 [15376r,15536r:0)[15536r,15552r:1)  0@15376r 1@15536r
15552B	%vreg317<def> = COPY %vreg320; GR32:%vreg317,%vreg320
	Considering merging to GR32 with %vreg320 in %vreg317
		RHS = %vreg320 [15376r,15536r:0)[15536r,15552r:1)  0@15376r 1@15536r
		LHS = %vreg317 [15552r,15568r:0)[15568r,15584r:1)  0@15552r 1@15568r
		merge %vreg317:0@15552r into %vreg320:1@15536r --> @15536r
		erased:	15552r	%vreg317<def> = COPY %vreg320; GR32:%vreg317,%vreg320
		updated: 15376B	%vreg317<def> = MOVZX32rm8 %vreg333, 1, %vreg337, 0, %noreg; mem:LD1[%arrayidx504] GR32:%vreg317 GR64:%vreg333 GR64_NOSP:%vreg337
		updated: 15536B	%vreg317<def,tied1> = SHR32rCL %vreg317<tied0>, %EFLAGS<imp-def,dead>, %CL<imp-use,kill>; GR32:%vreg317
	Success: %vreg320 -> %vreg317
	Result = %vreg317 [15376r,15536r:2)[15536r,15568r:0)[15568r,15584r:1)  0@15536r 1@15568r 2@15376r
15584B	%vreg315<def> = COPY %vreg317; GR32:%vreg315,%vreg317
	Considering merging to GR32 with %vreg315 in %vreg317
		RHS = %vreg315 [15584r,15600r:0)[15600r,15632r:1)  0@15584r 1@15600r
		LHS = %vreg317 [15376r,15536r:2)[15536r,15568r:0)[15568r,15584r:1)  0@15536r 1@15568r 2@15376r
		merge %vreg315:0@15584r into %vreg317:1@15568r --> @15568r
		erased:	15584r	%vreg315<def> = COPY %vreg317; GR32:%vreg315,%vreg317
		updated: 15600B	%vreg317<def,tied1> = SHL32ri %vreg317<tied0>, 16, %EFLAGS<imp-def,dead>; GR32:%vreg317
		updated: 15632B	%vreg313<def,tied1> = OR32rr %vreg313<tied0>, %vreg317, %EFLAGS<imp-def,dead>; GR32:%vreg313,%vreg317
	Success: %vreg315 -> %vreg317
	Result = %vreg317 [15376r,15536r:2)[15536r,15568r:0)[15568r,15600r:1)[15600r,15632r:3)  0@15536r 1@15568r 2@15376r 3@15600r
15616B	%vreg313<def> = COPY %vreg344; GR32:%vreg313,%vreg344
	Considering merging to GR32 with %vreg344 in %vreg313
		RHS = %vreg344 [15232r,15616r:0)  0@15232r
		LHS = %vreg313 [15616r,15632r:0)[15632r,15664r:1)  0@15616r 1@15632r
		merge %vreg313:0@15616r into %vreg344:0@15232r --> @15232r
		erased:	15616r	%vreg313<def> = COPY %vreg344; GR32:%vreg313,%vreg344
		updated: 15232B	%vreg313<def> = MOVZX32rm16 %vreg348, 2, %vreg352, 0, %noreg; mem:LD2[%arrayidx498] GR32:%vreg313 GR64:%vreg348 GR64_NOSP:%vreg352
	Success: %vreg344 -> %vreg313
	Result = %vreg313 [15232r,15632r:0)[15632r,15664r:1)  0@15232r 1@15632r
15712B	%vreg305<def> = COPY %vreg306; GR32:%vreg305,%vreg306
	Considering merging to GR32 with %vreg306 in %vreg305
		RHS = %vreg306 [15696r,15712r:0)  0@15696r
		LHS = %vreg305 [15712r,15728r:0)[15728r,15744r:1)  0@15712r 1@15728r
		merge %vreg305:0@15712r into %vreg306:0@15696r --> @15696r
		erased:	15712r	%vreg305<def> = COPY %vreg306; GR32:%vreg305,%vreg306
		updated: 15696B	%vreg305<def> = MOV32rm %vreg307, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used514] GR32:%vreg305 GR64:%vreg307
	Success: %vreg306 -> %vreg305
	Result = %vreg305 [15696r,15728r:0)[15728r,15744r:1)  0@15696r 1@15728r
15824B	%vreg295<def> = COPY %vreg297; GR32:%vreg295,%vreg297
	Considering merging to GR32 with %vreg297 in %vreg295
		RHS = %vreg297 [15808r,15824r:0)  0@15808r
		LHS = %vreg295 [15824r,15840r:0)[15840r,15856r:1)  0@15824r 1@15840r
		merge %vreg295:0@15824r into %vreg297:0@15808r --> @15808r
		erased:	15824r	%vreg295<def> = COPY %vreg297; GR32:%vreg295,%vreg297
		updated: 15808B	%vreg295<def> = MOV32rm %vreg298, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock517] GR32:%vreg295 GR64:%vreg298
	Success: %vreg297 -> %vreg295
	Result = %vreg295 [15808r,15840r:0)[15840r,15856r:1)  0@15808r 1@15840r
16144B	%vreg510<def> = COPY %vreg511; GR64:%vreg510,%vreg511
	Considering merging to GR64 with %vreg511 in %vreg510
		RHS = %vreg511 [16128r,16144r:0)  0@16128r
		LHS = %vreg510 [16144r,16160r:0)[16160r,16208r:1)  0@16144r 1@16160r
		merge %vreg510:0@16144r into %vreg511:0@16128r --> @16128r
		erased:	16144r	%vreg510<def> = COPY %vreg511; GR64:%vreg510,%vreg511
		updated: 16128B	%vreg510<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg510
	Success: %vreg511 -> %vreg510
	Result = %vreg510 [16128r,16160r:0)[16160r,16208r:1)  0@16128r 1@16160r
16320B	%vreg504<def> = COPY %vreg507:sub_8bit; GR8:%vreg504 GR32:%vreg507
	Considering merging to GR32 with %vreg504 in %vreg507:sub_8bit
		RHS = %vreg504 [16320r,16336r:0)  0@16320r
		LHS = %vreg507 [16256r,16320r:0)  0@16256r
		merge %vreg504:0@16320r into %vreg507:0@16256r --> @16256r
		erased:	16320r	%vreg504<def> = COPY %vreg507:sub_8bit; GR8:%vreg504 GR32:%vreg507
		updated: 16336B	MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg507:sub_8bit; mem:ST1[%k1] GR32:%vreg507
	Success: %vreg504:sub_8bit -> %vreg507
	Result = %vreg507 [16256r,16336r:0)  0@16256r
16480B	%vreg486<def> = COPY %vreg488; GR32:%vreg486,%vreg488
	Considering merging to GR32 with %vreg488 in %vreg486
		RHS = %vreg488 [16464r,16480r:0)  0@16464r
		LHS = %vreg486 [16480r,16496r:0)[16496r,16512r:1)  0@16480r 1@16496r
		merge %vreg486:0@16480r into %vreg488:0@16464r --> @16464r
		erased:	16480r	%vreg486<def> = COPY %vreg488; GR32:%vreg486,%vreg488
		updated: 16464B	%vreg486<def> = MOV32rm %vreg489, 1, %noreg, 60, %noreg; mem:LD4[%tPos541] GR32:%vreg486 GR64:%vreg489
	Success: %vreg488 -> %vreg486
	Result = %vreg486 [16464r,16496r:0)[16496r,16512r:1)  0@16464r 1@16496r
16624B	%vreg471<def> = COPY %vreg473; GR32:%vreg471,%vreg473
	Considering merging to GR32 with %vreg473 in %vreg471
		RHS = %vreg473 [16608r,16624r:0)  0@16608r
		LHS = %vreg471 [16624r,16640r:0)[16640r,16656r:1)  0@16624r 1@16640r
		merge %vreg471:0@16624r into %vreg473:0@16608r --> @16608r
		erased:	16624r	%vreg471<def> = COPY %vreg473; GR32:%vreg471,%vreg473
		updated: 16608B	%vreg471<def> = MOV32rm %vreg474, 1, %noreg, 60, %noreg; mem:LD4[%tPos547] GR32:%vreg471 GR64:%vreg474
	Success: %vreg473 -> %vreg471
	Result = %vreg471 [16608r,16640r:0)[16640r,16656r:1)  0@16608r 1@16640r
16656B	%vreg469<def> = COPY %vreg471; GR32:%vreg469,%vreg471
	Considering merging to GR32 with %vreg471 in %vreg469
		RHS = %vreg471 [16608r,16640r:0)[16640r,16656r:1)  0@16608r 1@16640r
		LHS = %vreg469 [16656r,16672r:0)[16672r,16688r:1)  0@16656r 1@16672r
		merge %vreg469:0@16656r into %vreg471:1@16640r --> @16640r
		erased:	16656r	%vreg469<def> = COPY %vreg471; GR32:%vreg469,%vreg471
		updated: 16608B	%vreg469<def> = MOV32rm %vreg474, 1, %noreg, 60, %noreg; mem:LD4[%tPos547] GR32:%vreg469 GR64:%vreg474
		updated: 16640B	%vreg469<def,tied1> = SHL32ri %vreg469<tied0>, 2, %EFLAGS<imp-def,dead>; GR32:%vreg469
	Success: %vreg471 -> %vreg469
	Result = %vreg469 [16608r,16640r:2)[16640r,16672r:0)[16672r,16688r:1)  0@16640r 1@16672r 2@16608r
16720B	%vreg467<def> = COPY %vreg476; GR32:%vreg467,%vreg476
	Considering merging to GR32 with %vreg476 in %vreg467
		RHS = %vreg476 [16576r,16720r:0)  0@16576r
		LHS = %vreg467 [16720r,16736r:0)[16736r,16752r:1)  0@16720r 1@16736r
		merge %vreg467:0@16720r into %vreg476:0@16576r --> @16576r
		erased:	16720r	%vreg467<def> = COPY %vreg476; GR32:%vreg467,%vreg476
		updated: 16576B	%vreg467<def> = MOVZX32rm8 %vreg480, 1, %vreg484, 0, %noreg; mem:LD1[%arrayidx545] GR32:%vreg467 GR64:%vreg480 GR64_NOSP:%vreg484
	Success: %vreg476 -> %vreg467
	Result = %vreg467 [16576r,16736r:0)[16736r,16752r:1)  0@16576r 1@16736r
16752B	%vreg464<def> = COPY %vreg467; GR32:%vreg464,%vreg467
	Considering merging to GR32 with %vreg467 in %vreg464
		RHS = %vreg467 [16576r,16736r:0)[16736r,16752r:1)  0@16576r 1@16736r
		LHS = %vreg464 [16752r,16768r:0)[16768r,16784r:1)  0@16752r 1@16768r
		merge %vreg464:0@16752r into %vreg467:1@16736r --> @16736r
		erased:	16752r	%vreg464<def> = COPY %vreg467; GR32:%vreg464,%vreg467
		updated: 16576B	%vreg464<def> = MOVZX32rm8 %vreg480, 1, %vreg484, 0, %noreg; mem:LD1[%arrayidx545] GR32:%vreg464 GR64:%vreg480 GR64_NOSP:%vreg484
		updated: 16736B	%vreg464<def,tied1> = SHR32rCL %vreg464<tied0>, %EFLAGS<imp-def,dead>, %CL<imp-use,kill>; GR32:%vreg464
	Success: %vreg467 -> %vreg464
	Result = %vreg464 [16576r,16736r:2)[16736r,16768r:0)[16768r,16784r:1)  0@16736r 1@16768r 2@16576r
16784B	%vreg462<def> = COPY %vreg464; GR32:%vreg462,%vreg464
	Considering merging to GR32 with %vreg462 in %vreg464
		RHS = %vreg462 [16784r,16800r:0)[16800r,16832r:1)  0@16784r 1@16800r
		LHS = %vreg464 [16576r,16736r:2)[16736r,16768r:0)[16768r,16784r:1)  0@16736r 1@16768r 2@16576r
		merge %vreg462:0@16784r into %vreg464:1@16768r --> @16768r
		erased:	16784r	%vreg462<def> = COPY %vreg464; GR32:%vreg462,%vreg464
		updated: 16800B	%vreg464<def,tied1> = SHL32ri %vreg464<tied0>, 16, %EFLAGS<imp-def,dead>; GR32:%vreg464
		updated: 16832B	%vreg460<def,tied1> = OR32rr %vreg460<tied0>, %vreg464, %EFLAGS<imp-def,dead>; GR32:%vreg460,%vreg464
	Success: %vreg462 -> %vreg464
	Result = %vreg464 [16576r,16736r:2)[16736r,16768r:0)[16768r,16800r:1)[16800r,16832r:3)  0@16736r 1@16768r 2@16576r 3@16800r
16816B	%vreg460<def> = COPY %vreg491; GR32:%vreg460,%vreg491
	Considering merging to GR32 with %vreg491 in %vreg460
		RHS = %vreg491 [16432r,16816r:0)  0@16432r
		LHS = %vreg460 [16816r,16832r:0)[16832r,16864r:1)  0@16816r 1@16832r
		merge %vreg460:0@16816r into %vreg491:0@16432r --> @16432r
		erased:	16816r	%vreg460<def> = COPY %vreg491; GR32:%vreg460,%vreg491
		updated: 16432B	%vreg460<def> = MOVZX32rm16 %vreg495, 2, %vreg499, 0, %noreg; mem:LD2[%arrayidx539] GR32:%vreg460 GR64:%vreg495 GR64_NOSP:%vreg499
	Success: %vreg491 -> %vreg460
	Result = %vreg460 [16432r,16832r:0)[16832r,16864r:1)  0@16432r 1@16832r
16912B	%vreg452<def> = COPY %vreg453; GR32:%vreg452,%vreg453
	Considering merging to GR32 with %vreg453 in %vreg452
		RHS = %vreg453 [16896r,16912r:0)  0@16896r
		LHS = %vreg452 [16912r,16928r:0)[16928r,16944r:1)  0@16912r 1@16928r
		merge %vreg452:0@16912r into %vreg453:0@16896r --> @16896r
		erased:	16912r	%vreg452<def> = COPY %vreg453; GR32:%vreg452,%vreg453
		updated: 16896B	%vreg452<def> = MOV32rm %vreg454, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used555] GR32:%vreg452 GR64:%vreg454
	Success: %vreg453 -> %vreg452
	Result = %vreg452 [16896r,16928r:0)[16928r,16944r:1)  0@16896r 1@16928r
16976B	%vreg446<def> = COPY %vreg448; GR32:%vreg446,%vreg448
	Considering merging to GR32 with %vreg448 in %vreg446
		RHS = %vreg448 [16960r,16976r:0)  0@16960r
		LHS = %vreg446 [16976r,16992r:0)[16992r,17024r:1)  0@16976r 1@16992r
		merge %vreg446:0@16976r into %vreg448:0@16960r --> @16960r
		erased:	16976r	%vreg446<def> = COPY %vreg448; GR32:%vreg446,%vreg448
		updated: 16960B	%vreg446<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg446
	Success: %vreg448 -> %vreg446
	Result = %vreg446 [16960r,16992r:0)[16992r,17024r:1)  0@16960r 1@16992r
17088B	%vreg437<def> = COPY %vreg438; GR64:%vreg437,%vreg438
	Considering merging to GR64 with %vreg438 in %vreg437
		RHS = %vreg438 [17072r,17088r:0)  0@17072r
		LHS = %vreg437 [17088r,17104r:0)[17104r,17152r:1)  0@17088r 1@17104r
		merge %vreg437:0@17088r into %vreg438:0@17072r --> @17072r
		erased:	17088r	%vreg437<def> = COPY %vreg438; GR64:%vreg437,%vreg438
		updated: 17072B	%vreg437<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg437
	Success: %vreg438 -> %vreg437
	Result = %vreg437 [17072r,17104r:0)[17104r,17152r:1)  0@17072r 1@17104r
17424B	%vreg413<def> = COPY %vreg415; GR32:%vreg413,%vreg415
	Considering merging to GR32 with %vreg415 in %vreg413
		RHS = %vreg415 [17408r,17424r:0)  0@17408r
		LHS = %vreg413 [17424r,17440r:0)[17440r,17456r:1)  0@17424r 1@17440r
		merge %vreg413:0@17424r into %vreg415:0@17408r --> @17408r
		erased:	17424r	%vreg413<def> = COPY %vreg415; GR32:%vreg413,%vreg415
		updated: 17408B	%vreg413<def> = MOV32rm %vreg416, 1, %noreg, 60, %noreg; mem:LD4[%tPos570] GR32:%vreg413 GR64:%vreg416
	Success: %vreg415 -> %vreg413
	Result = %vreg413 [17408r,17440r:0)[17440r,17456r:1)  0@17408r 1@17440r
17568B	%vreg398<def> = COPY %vreg400; GR32:%vreg398,%vreg400
	Considering merging to GR32 with %vreg400 in %vreg398
		RHS = %vreg400 [17552r,17568r:0)  0@17552r
		LHS = %vreg398 [17568r,17584r:0)[17584r,17600r:1)  0@17568r 1@17584r
		merge %vreg398:0@17568r into %vreg400:0@17552r --> @17552r
		erased:	17568r	%vreg398<def> = COPY %vreg400; GR32:%vreg398,%vreg400
		updated: 17552B	%vreg398<def> = MOV32rm %vreg401, 1, %noreg, 60, %noreg; mem:LD4[%tPos576] GR32:%vreg398 GR64:%vreg401
	Success: %vreg400 -> %vreg398
	Result = %vreg398 [17552r,17584r:0)[17584r,17600r:1)  0@17552r 1@17584r
17600B	%vreg396<def> = COPY %vreg398; GR32:%vreg396,%vreg398
	Considering merging to GR32 with %vreg398 in %vreg396
		RHS = %vreg398 [17552r,17584r:0)[17584r,17600r:1)  0@17552r 1@17584r
		LHS = %vreg396 [17600r,17616r:0)[17616r,17632r:1)  0@17600r 1@17616r
		merge %vreg396:0@17600r into %vreg398:1@17584r --> @17584r
		erased:	17600r	%vreg396<def> = COPY %vreg398; GR32:%vreg396,%vreg398
		updated: 17552B	%vreg396<def> = MOV32rm %vreg401, 1, %noreg, 60, %noreg; mem:LD4[%tPos576] GR32:%vreg396 GR64:%vreg401
		updated: 17584B	%vreg396<def,tied1> = SHL32ri %vreg396<tied0>, 2, %EFLAGS<imp-def,dead>; GR32:%vreg396
	Success: %vreg398 -> %vreg396
	Result = %vreg396 [17552r,17584r:2)[17584r,17616r:0)[17616r,17632r:1)  0@17584r 1@17616r 2@17552r
17664B	%vreg394<def> = COPY %vreg403; GR32:%vreg394,%vreg403
	Considering merging to GR32 with %vreg403 in %vreg394
		RHS = %vreg403 [17520r,17664r:0)  0@17520r
		LHS = %vreg394 [17664r,17680r:0)[17680r,17696r:1)  0@17664r 1@17680r
		merge %vreg394:0@17664r into %vreg403:0@17520r --> @17520r
		erased:	17664r	%vreg394<def> = COPY %vreg403; GR32:%vreg394,%vreg403
		updated: 17520B	%vreg394<def> = MOVZX32rm8 %vreg407, 1, %vreg411, 0, %noreg; mem:LD1[%arrayidx574] GR32:%vreg394 GR64:%vreg407 GR64_NOSP:%vreg411
	Success: %vreg403 -> %vreg394
	Result = %vreg394 [17520r,17680r:0)[17680r,17696r:1)  0@17520r 1@17680r
17696B	%vreg391<def> = COPY %vreg394; GR32:%vreg391,%vreg394
	Considering merging to GR32 with %vreg394 in %vreg391
		RHS = %vreg394 [17520r,17680r:0)[17680r,17696r:1)  0@17520r 1@17680r
		LHS = %vreg391 [17696r,17712r:0)[17712r,17728r:1)  0@17696r 1@17712r
		merge %vreg391:0@17696r into %vreg394:1@17680r --> @17680r
		erased:	17696r	%vreg391<def> = COPY %vreg394; GR32:%vreg391,%vreg394
		updated: 17520B	%vreg391<def> = MOVZX32rm8 %vreg407, 1, %vreg411, 0, %noreg; mem:LD1[%arrayidx574] GR32:%vreg391 GR64:%vreg407 GR64_NOSP:%vreg411
		updated: 17680B	%vreg391<def,tied1> = SHR32rCL %vreg391<tied0>, %EFLAGS<imp-def,dead>, %CL<imp-use,kill>; GR32:%vreg391
	Success: %vreg394 -> %vreg391
	Result = %vreg391 [17520r,17680r:2)[17680r,17712r:0)[17712r,17728r:1)  0@17680r 1@17712r 2@17520r
17728B	%vreg389<def> = COPY %vreg391; GR32:%vreg389,%vreg391
	Considering merging to GR32 with %vreg389 in %vreg391
		RHS = %vreg389 [17728r,17744r:0)[17744r,17776r:1)  0@17728r 1@17744r
		LHS = %vreg391 [17520r,17680r:2)[17680r,17712r:0)[17712r,17728r:1)  0@17680r 1@17712r 2@17520r
		merge %vreg389:0@17728r into %vreg391:1@17712r --> @17712r
		erased:	17728r	%vreg389<def> = COPY %vreg391; GR32:%vreg389,%vreg391
		updated: 17744B	%vreg391<def,tied1> = SHL32ri %vreg391<tied0>, 16, %EFLAGS<imp-def,dead>; GR32:%vreg391
		updated: 17776B	%vreg387<def,tied1> = OR32rr %vreg387<tied0>, %vreg391, %EFLAGS<imp-def,dead>; GR32:%vreg387,%vreg391
	Success: %vreg389 -> %vreg391
	Result = %vreg391 [17520r,17680r:2)[17680r,17712r:0)[17712r,17744r:1)[17744r,17776r:3)  0@17680r 1@17712r 2@17520r 3@17744r
17760B	%vreg387<def> = COPY %vreg418; GR32:%vreg387,%vreg418
	Considering merging to GR32 with %vreg418 in %vreg387
		RHS = %vreg418 [17376r,17760r:0)  0@17376r
		LHS = %vreg387 [17760r,17776r:0)[17776r,17808r:1)  0@17760r 1@17776r
		merge %vreg387:0@17760r into %vreg418:0@17376r --> @17376r
		erased:	17760r	%vreg387<def> = COPY %vreg418; GR32:%vreg387,%vreg418
		updated: 17376B	%vreg387<def> = MOVZX32rm16 %vreg422, 2, %vreg426, 0, %noreg; mem:LD2[%arrayidx568] GR32:%vreg387 GR64:%vreg422 GR64_NOSP:%vreg426
	Success: %vreg418 -> %vreg387
	Result = %vreg387 [17376r,17776r:0)[17776r,17808r:1)  0@17376r 1@17776r
17856B	%vreg379<def> = COPY %vreg380; GR32:%vreg379,%vreg380
	Considering merging to GR32 with %vreg380 in %vreg379
		RHS = %vreg380 [17840r,17856r:0)  0@17840r
		LHS = %vreg379 [17856r,17872r:0)[17872r,17888r:1)  0@17856r 1@17872r
		merge %vreg379:0@17856r into %vreg380:0@17840r --> @17840r
		erased:	17856r	%vreg379<def> = COPY %vreg380; GR32:%vreg379,%vreg380
		updated: 17840B	%vreg379<def> = MOV32rm %vreg381, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used584] GR32:%vreg379 GR64:%vreg381
	Success: %vreg380 -> %vreg379
	Result = %vreg379 [17840r,17872r:0)[17872r,17888r:1)  0@17840r 1@17872r
return:
18000B	%RDI<def> = COPY %vreg1268; GR64:%vreg1268
	Considering merging %vreg1268 with %RDI
	Can only merge into reserved registers.
18016B	%RSI<def> = COPY %vreg1269; GR64:%vreg1269
	Considering merging %vreg1269 with %RSI
	Can only merge into reserved registers.
18128B	%AL<def> = COPY %vreg1266; GR8:%vreg1266
	Considering merging %vreg1266 with %AL
	Can only merge into reserved registers.
entry:
16B	%vreg0<def> = COPY %RDI; GR64:%vreg0
	Considering merging %vreg0 with %RDI
	Can only merge into reserved registers.
112B	%RDI<def> = COPY %vreg6; GR64:%vreg6
	Considering merging %vreg6 with %RDI
	Can only merge into reserved registers.
128B	%RSI<def> = COPY %vreg7; GR64:%vreg7
	Considering merging %vreg7 with %RSI
	Can only merge into reserved registers.
if.then:
if.then.3:
if.then.29:
if.then.36:
if.else:
if.then.346:
if.then.393:
if.then.400:
17952B	%vreg1268<def> = COPY %vreg1267; GR64:%vreg1268,%vreg1267
	Considering merging to GR64 with %vreg1267 in %vreg1268
		RHS = %vreg1267 [17936r,17952r:0)  0@17936r
		LHS = %vreg1268 [17952r,18000r:0)  0@17952r
		merge %vreg1268:0@17952r into %vreg1267:0@17936r --> @17936r
		erased:	17952r	%vreg1268<def> = COPY %vreg1267; GR64:%vreg1268,%vreg1267
		updated: 17936B	%vreg1268<def> = MOV64ri <ga:@unRLE_obuf_to_output_SMALL>; GR64:%vreg1268
	Success: %vreg1267 -> %vreg1268
	Result = %vreg1268 [17936r,18000r:0)  0@17936r
32B	%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
	Considering merging to GR64 with %vreg0 in %vreg1
		RHS = %vreg0 [16r,32r:0)  0@16r
		LHS = %vreg1 [32r,224r:0)  0@32r
		merge %vreg1:0@32r into %vreg0:0@16r --> @16r
		erased:	32r	%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
		updated: 16B	%vreg1<def> = COPY %RDI; GR64:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [16r,224r:0)  0@16r
64B	%vreg6<def> = COPY %vreg5; GR64:%vreg6,%vreg5
	Considering merging to GR64 with %vreg5 in %vreg6
		RHS = %vreg5 [48r,64r:0)  0@48r
		LHS = %vreg6 [64r,112r:0)  0@64r
		merge %vreg6:0@64r into %vreg5:0@48r --> @48r
		erased:	64r	%vreg6<def> = COPY %vreg5; GR64:%vreg6,%vreg5
		updated: 48B	%vreg6<def> = MOV64ri <ga:@unRLE_obuf_to_output_SMALL>; GR64:%vreg6
	Success: %vreg5 -> %vreg6
	Result = %vreg6 [48r,112r:0)  0@48r
18000B	%RDI<def> = COPY %vreg1268; GR64:%vreg1268
	Considering merging %vreg1268 with %RDI
	Can only merge into reserved registers.
112B	%RDI<def> = COPY %vreg6; GR64:%vreg6
	Considering merging %vreg6 with %RDI
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
DIL [0B,16r:0)[112r,144r:12)[2160r,2192r:5)[4016r,4048r:4)[5872r,5904r:3)[7696r,7728r:2)[9264r,9296r:1)[12528r,12560r:10)[13760r,13792r:9)[14992r,15024r:8)[16192r,16224r:6)[17136r,17168r:7)[18000r,18032r:11)  0@0B-phi 1@9264r 2@7696r 3@5872r 4@4016r 5@2160r 6@16192r 7@17136r 8@14992r 9@13760r 10@12528r 11@18000r 12@112r
%vreg1 [16r,224r:0)  0@16r
%vreg4 [240r,256r:0)  0@240r
%vreg6 [48r,112r:0)  0@48r
%vreg7 [80r,128r:0)  0@80r
%vreg11 [10752r,10768r:0)  0@10752r
%vreg12 [10736r,10752r:0)  0@10736r
%vreg15 [10864r,10880r:0)  0@10864r
%vreg19 [11728r,11744r:0)  0@11728r
%vreg20 [11712r,11728r:0)  0@11712r
%vreg24 [11648r,11680r:0)[11680r,11696r:1)  0@11648r 1@11680r
%vreg27 [11632r,11696r:0)  0@11632r
%vreg28 [11616r,11632r:0)  0@11616r
%vreg32 [11552r,11584r:0)[11584r,11600r:1)  0@11552r 1@11584r
%vreg35 [11536r,11600r:0)  0@11536r
%vreg36 [11520r,11536r:0)  0@11520r
%vreg40 [11456r,11488r:0)[11488r,11504r:1)  0@11456r 1@11488r
%vreg43 [11440r,11504r:0)  0@11440r
%vreg44 [11424r,11440r:0)  0@11424r
%vreg48 [11360r,11392r:0)[11392r,11408r:1)  0@11360r 1@11392r
%vreg50 [11344r,11408r:0)  0@11344r
%vreg53 [11312r,11328r:0)  0@11312r
%vreg56 [11072r,11104r:2)[11104r,11296r:0)[11296r,11328r:1)  0@11104r 1@11296r 2@11072r
%vreg60 [11248r,11296r:0)  0@11248r
%vreg63 [11136r,11168r:2)[11168r,11232r:0)[11232r,11248r:1)  0@11168r 1@11232r 2@11136r
%vreg65 [11200r,11232r:0)  0@11200r
%vreg67 [11184r,11200r:0)  0@11184r
%vreg72 [11120r,11136r:0)  0@11120r
%vreg77 [11056r,11072r:0)  0@11056r
%vreg81 [11024r,11040r:0)  0@11024r
%vreg83 [11008r,11024r:0)  0@11008r
%vreg84 [10992r,11008r:0)  0@10992r
%vreg86 [10976r,11040r:0)  0@10976r
%vreg87 [10960r,10976r:0)  0@10960r
%vreg91 [11824r,11856r:0)[11856r,11872r:1)  0@11824r 1@11856r
%vreg94 [11808r,11872r:0)  0@11808r
%vreg95 [11792r,11808r:0)  0@11792r
%vreg99 [11984r,12016r:0)[12016r,12032r:1)  0@11984r 1@12016r
%vreg102 [11968r,11984r:0)  0@11968r
%vreg104 [11952r,12032r:0)  0@11952r
%vreg105 [11936r,11952r:0)  0@11936r
%vreg109 [12176r,12208r:0)[12208r,12224r:1)  0@12176r 1@12208r
%vreg112 [12160r,12176r:0)  0@12160r
%vreg114 [12144r,12224r:0)  0@12144r
%vreg115 [12128r,12144r:0)  0@12128r
%vreg119 [13344r,13376r:0)[13376r,13392r:1)  0@13344r 1@13376r
%vreg122 [13328r,13344r:0)  0@13328r
%vreg124 [13312r,13392r:0)  0@13312r
%vreg125 [13296r,13312r:0)  0@13296r
%vreg129 [13232r,13264r:0)[13264r,13280r:1)  0@13232r 1@13264r
%vreg131 [13216r,13280r:0)  0@13216r
%vreg134 [13184r,13200r:0)  0@13184r
%vreg137 [12768r,13168r:0)[13168r,13200r:1)  0@12768r 1@13168r
%vreg141 [12912r,13072r:2)[13072r,13104r:0)[13104r,13136r:1)[13136r,13168r:3)  0@13072r 1@13104r 2@12912r 3@13136r
%vreg146 [12944r,12976r:2)[12976r,13008r:0)[13008r,13024r:1)  0@12976r 1@13008r 2@12944r
%vreg151 [12928r,12944r:0)  0@12928r
%vreg157 [12896r,12912r:0)  0@12896r
%vreg158 [12880r,12896r:0)  0@12880r
%vreg161 [12848r,12912r:0)  0@12848r
%vreg163 [12800r,12832r:0)[12832r,12848r:1)  0@12800r 1@12832r
%vreg166 [12784r,12800r:0)  0@12784r
%vreg172 [12752r,12768r:0)  0@12752r
%vreg173 [12736r,12752r:0)  0@12736r
%vreg176 [12704r,12768r:0)  0@12704r
%vreg178 [12688r,12704r:0)  0@12688r
%vreg184 [12592r,12672r:0)  0@12592r
%vreg187 [12464r,12496r:0)[12496r,12544r:1)  0@12464r 1@12496r
%vreg190 [12448r,12528r:0)  0@12448r
%vreg191 [12432r,12448r:0)  0@12432r
%vreg194 [12400r,12416r:0)  0@12400r
%vreg198 [12368r,12416r:0)  0@12368r
%vreg199 [12352r,12368r:0)  0@12352r
%vreg201 [12320r,12336r:0)  0@12320r
%vreg205 [13488r,13504r:0)  0@13488r
%vreg207 [13472r,13504r:0)  0@13472r
%vreg211 [14576r,14608r:0)[14608r,14624r:1)  0@14576r 1@14608r
%vreg214 [14560r,14576r:0)  0@14560r
%vreg216 [14544r,14624r:0)  0@14544r
%vreg217 [14528r,14544r:0)  0@14528r
%vreg221 [14464r,14496r:0)[14496r,14512r:1)  0@14464r 1@14496r
%vreg223 [14448r,14512r:0)  0@14448r
%vreg226 [14416r,14432r:0)  0@14416r
%vreg229 [14000r,14400r:0)[14400r,14432r:1)  0@14000r 1@14400r
%vreg233 [14144r,14304r:2)[14304r,14336r:0)[14336r,14368r:1)[14368r,14400r:3)  0@14304r 1@14336r 2@14144r 3@14368r
%vreg238 [14176r,14208r:2)[14208r,14240r:0)[14240r,14256r:1)  0@14208r 1@14240r 2@14176r
%vreg243 [14160r,14176r:0)  0@14160r
%vreg249 [14128r,14144r:0)  0@14128r
%vreg250 [14112r,14128r:0)  0@14112r
%vreg253 [14080r,14144r:0)  0@14080r
%vreg255 [14032r,14064r:0)[14064r,14080r:1)  0@14032r 1@14064r
%vreg258 [14016r,14032r:0)  0@14016r
%vreg264 [13984r,14000r:0)  0@13984r
%vreg265 [13968r,13984r:0)  0@13968r
%vreg268 [13936r,14000r:0)  0@13936r
%vreg270 [13920r,13936r:0)  0@13920r
%vreg276 [13824r,13904r:0)  0@13824r
%vreg279 [13696r,13728r:0)[13728r,13776r:1)  0@13696r 1@13728r
%vreg282 [13680r,13760r:0)  0@13680r
%vreg283 [13664r,13680r:0)  0@13664r
%vreg285 [13632r,13648r:0)  0@13632r
%vreg289 [14720r,14736r:0)  0@14720r
%vreg291 [14704r,14736r:0)  0@14704r
%vreg295 [15808r,15840r:0)[15840r,15856r:1)  0@15808r 1@15840r
%vreg298 [15792r,15808r:0)  0@15792r
%vreg300 [15776r,15856r:0)  0@15776r
%vreg301 [15760r,15776r:0)  0@15760r
%vreg305 [15696r,15728r:0)[15728r,15744r:1)  0@15696r 1@15728r
%vreg307 [15680r,15744r:0)  0@15680r
%vreg310 [15648r,15664r:0)  0@15648r
%vreg313 [15232r,15632r:0)[15632r,15664r:1)  0@15232r 1@15632r
%vreg317 [15376r,15536r:2)[15536r,15568r:0)[15568r,15600r:1)[15600r,15632r:3)  0@15536r 1@15568r 2@15376r 3@15600r
%vreg322 [15408r,15440r:2)[15440r,15472r:0)[15472r,15488r:1)  0@15440r 1@15472r 2@15408r
%vreg327 [15392r,15408r:0)  0@15392r
%vreg333 [15360r,15376r:0)  0@15360r
%vreg334 [15344r,15360r:0)  0@15344r
%vreg337 [15312r,15376r:0)  0@15312r
%vreg339 [15264r,15296r:0)[15296r,15312r:1)  0@15264r 1@15296r
%vreg342 [15248r,15264r:0)  0@15248r
%vreg348 [15216r,15232r:0)  0@15216r
%vreg349 [15200r,15216r:0)  0@15200r
%vreg352 [15168r,15232r:0)  0@15168r
%vreg354 [15152r,15168r:0)  0@15152r
%vreg360 [15056r,15136r:0)  0@15056r
%vreg363 [14928r,14960r:0)[14960r,15008r:1)  0@14928r 1@14960r
%vreg366 [14912r,14992r:0)  0@14912r
%vreg367 [14896r,14912r:0)  0@14896r
%vreg369 [14864r,14880r:0)  0@14864r
%vreg373 [15952r,15968r:0)  0@15952r
%vreg375 [15936r,15968r:0)  0@15936r
%vreg379 [17840r,17872r:0)[17872r,17888r:1)  0@17840r 1@17872r
%vreg381 [17824r,17888r:0)  0@17824r
%vreg384 [17792r,17808r:0)  0@17792r
%vreg387 [17376r,17776r:0)[17776r,17808r:1)  0@17376r 1@17776r
%vreg391 [17520r,17680r:2)[17680r,17712r:0)[17712r,17744r:1)[17744r,17776r:3)  0@17680r 1@17712r 2@17520r 3@17744r
%vreg396 [17552r,17584r:2)[17584r,17616r:0)[17616r,17632r:1)  0@17584r 1@17616r 2@17552r
%vreg401 [17536r,17552r:0)  0@17536r
%vreg407 [17504r,17520r:0)  0@17504r
%vreg408 [17488r,17504r:0)  0@17488r
%vreg411 [17456r,17520r:0)  0@17456r
%vreg413 [17408r,17440r:0)[17440r,17456r:1)  0@17408r 1@17440r
%vreg416 [17392r,17408r:0)  0@17392r
%vreg422 [17360r,17376r:0)  0@17360r
%vreg423 [17344r,17360r:0)  0@17344r
%vreg426 [17312r,17376r:0)  0@17312r
%vreg428 [17296r,17312r:0)  0@17296r
%vreg431 [17264r,17280r:0)  0@17264r
%vreg434 [17200r,17280r:0)  0@17200r
%vreg437 [17072r,17104r:0)[17104r,17152r:1)  0@17072r 1@17104r
%vreg440 [17056r,17136r:0)  0@17056r
%vreg441 [17040r,17056r:0)  0@17040r
%vreg444 [17008r,17024r:0)  0@17008r
%vreg446 [16960r,16992r:0)[16992r,17024r:1)  0@16960r 1@16992r
%vreg452 [16896r,16928r:0)[16928r,16944r:1)  0@16896r 1@16928r
%vreg454 [16880r,16944r:0)  0@16880r
%vreg457 [16848r,16864r:0)  0@16848r
%vreg460 [16432r,16832r:0)[16832r,16864r:1)  0@16432r 1@16832r
%vreg464 [16576r,16736r:2)[16736r,16768r:0)[16768r,16800r:1)[16800r,16832r:3)  0@16736r 1@16768r 2@16576r 3@16800r
%vreg469 [16608r,16640r:2)[16640r,16672r:0)[16672r,16688r:1)  0@16640r 1@16672r 2@16608r
%vreg474 [16592r,16608r:0)  0@16592r
%vreg480 [16560r,16576r:0)  0@16560r
%vreg481 [16544r,16560r:0)  0@16544r
%vreg484 [16512r,16576r:0)  0@16512r
%vreg486 [16464r,16496r:0)[16496r,16512r:1)  0@16464r 1@16496r
%vreg489 [16448r,16464r:0)  0@16448r
%vreg495 [16416r,16432r:0)  0@16416r
%vreg496 [16400r,16416r:0)  0@16400r
%vreg499 [16368r,16432r:0)  0@16368r
%vreg501 [16352r,16368r:0)  0@16352r
%vreg507 [16256r,16336r:0)  0@16256r
%vreg510 [16128r,16160r:0)[16160r,16208r:1)  0@16128r 1@16160r
%vreg513 [16112r,16192r:0)  0@16112r
%vreg514 [16096r,16112r:0)  0@16096r
%vreg517 [16032r,16048r:0)  0@16032r
%vreg519 [16016r,16048r:0)  0@16016r
%vreg522 [14800r,14816r:0)  0@14800r
%vreg524 [14784r,14816r:0)  0@14784r
%vreg527 [13568r,13584r:0)  0@13568r
%vreg529 [13552r,13584r:0)  0@13552r
%vreg533 [384r,400r:0)  0@384r
%vreg534 [368r,384r:0)  0@368r
%vreg537 [496r,512r:0)  0@496r
%vreg541 [1360r,1376r:0)  0@1360r
%vreg542 [1344r,1360r:0)  0@1344r
%vreg546 [1280r,1312r:0)[1312r,1328r:1)  0@1280r 1@1312r
%vreg549 [1264r,1328r:0)  0@1264r
%vreg550 [1248r,1264r:0)  0@1248r
%vreg554 [1184r,1216r:0)[1216r,1232r:1)  0@1184r 1@1216r
%vreg557 [1168r,1232r:0)  0@1168r
%vreg558 [1152r,1168r:0)  0@1152r
%vreg562 [1088r,1120r:0)[1120r,1136r:1)  0@1088r 1@1120r
%vreg565 [1072r,1136r:0)  0@1072r
%vreg566 [1056r,1072r:0)  0@1056r
%vreg570 [992r,1024r:0)[1024r,1040r:1)  0@992r 1@1024r
%vreg572 [976r,1040r:0)  0@976r
%vreg575 [944r,960r:0)  0@944r
%vreg578 [704r,736r:2)[736r,928r:0)[928r,960r:1)  0@736r 1@928r 2@704r
%vreg582 [880r,928r:0)  0@880r
%vreg585 [768r,800r:2)[800r,864r:0)[864r,880r:1)  0@800r 1@864r 2@768r
%vreg587 [832r,864r:0)  0@832r
%vreg589 [816r,832r:0)  0@816r
%vreg594 [752r,768r:0)  0@752r
%vreg599 [688r,704r:0)  0@688r
%vreg603 [656r,672r:0)  0@656r
%vreg605 [640r,656r:0)  0@640r
%vreg606 [624r,640r:0)  0@624r
%vreg608 [608r,672r:0)  0@608r
%vreg609 [592r,608r:0)  0@592r
%vreg613 [1456r,1488r:0)[1488r,1504r:1)  0@1456r 1@1488r
%vreg616 [1440r,1504r:0)  0@1440r
%vreg617 [1424r,1440r:0)  0@1424r
%vreg621 [1616r,1648r:0)[1648r,1664r:1)  0@1616r 1@1648r
%vreg624 [1600r,1616r:0)  0@1600r
%vreg626 [1584r,1664r:0)  0@1584r
%vreg627 [1568r,1584r:0)  0@1568r
%vreg631 [1808r,1840r:0)[1840r,1856r:1)  0@1808r 1@1840r
%vreg634 [1792r,1808r:0)  0@1792r
%vreg636 [1776r,1856r:0)  0@1776r
%vreg637 [1760r,1776r:0)  0@1760r
%vreg640 [2848r,2864r:0)  0@2848r
%vreg643 [2816r,2832r:0)  0@2816r
%vreg646 [2400r,2800r:0)[2800r,2832r:1)  0@2400r 1@2800r
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%vreg655 [2576r,2608r:2)[2608r,2640r:0)[2640r,2656r:1)  0@2608r 1@2640r 2@2576r
%vreg660 [2560r,2576r:0)  0@2560r
%vreg666 [2528r,2544r:0)  0@2528r
%vreg667 [2512r,2528r:0)  0@2512r
%vreg670 [2480r,2544r:0)  0@2480r
%vreg672 [2432r,2464r:0)[2464r,2480r:1)  0@2432r 1@2464r
%vreg675 [2416r,2432r:0)  0@2416r
%vreg681 [2384r,2400r:0)  0@2384r
%vreg682 [2368r,2384r:0)  0@2368r
%vreg685 [2336r,2400r:0)  0@2336r
%vreg687 [2320r,2336r:0)  0@2320r
%vreg693 [2224r,2304r:0)  0@2224r
%vreg696 [2096r,2128r:0)[2128r,2176r:1)  0@2096r 1@2128r
%vreg699 [2080r,2160r:0)  0@2080r
%vreg700 [2064r,2080r:0)  0@2064r
%vreg703 [2032r,2048r:0)  0@2032r
%vreg707 [2000r,2048r:0)  0@2000r
%vreg708 [1984r,2000r:0)  0@1984r
%vreg710 [1952r,1968r:0)  0@1952r
%vreg713 [3072r,3088r:0)  0@3072r
%vreg717 [3008r,3040r:0)[3040r,3056r:1)  0@3008r 1@3040r
%vreg719 [2992r,3056r:0)  0@2992r
%vreg722 [2960r,2976r:0)  0@2960r
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%vreg726 [2928r,2944r:0)  0@2928r
%vreg728 [2912r,2928r:0)  0@2912r
%vreg730 [3136r,3152r:0)  0@3136r
%vreg734 [3600r,3632r:0)[3632r,3648r:1)  0@3600r 1@3632r
%vreg737 [3584r,3600r:0)  0@3584r
%vreg739 [3568r,3648r:0)  0@3568r
%vreg740 [3552r,3568r:0)  0@3552r
%vreg744 [3488r,3520r:0)[3520r,3536r:1)  0@3488r 1@3520r
%vreg746 [3472r,3536r:0)  0@3472r
%vreg752 [3392r,3424r:0)[3424r,3456r:1)  0@3392r 1@3424r
%vreg757 [3232r,3376r:0)  0@3232r
%vreg758 [3216r,3376r:0)[3376r,3424r:1)  0@3216r 1@3376r
%vreg760 [3328r,3344r:0)  0@3328r
%vreg764 [3264r,3296r:0)[3296r,3312r:1)  0@3264r 1@3296r
%vreg766 [3248r,3312r:0)  0@3248r
%vreg770 [3744r,3760r:0)  0@3744r
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%vreg775 [4704r,4720r:0)  0@4704r
%vreg778 [4672r,4688r:0)  0@4672r
%vreg781 [4256r,4656r:0)[4656r,4688r:1)  0@4256r 1@4656r
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%vreg795 [4416r,4432r:0)  0@4416r
%vreg801 [4384r,4400r:0)  0@4384r
%vreg802 [4368r,4384r:0)  0@4368r
%vreg805 [4336r,4400r:0)  0@4336r
%vreg807 [4288r,4320r:0)[4320r,4336r:1)  0@4288r 1@4320r
%vreg810 [4272r,4288r:0)  0@4272r
%vreg816 [4240r,4256r:0)  0@4240r
%vreg817 [4224r,4240r:0)  0@4224r
%vreg820 [4192r,4256r:0)  0@4192r
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%vreg831 [3952r,3984r:0)[3984r,4032r:1)  0@3952r 1@3984r
%vreg834 [3936r,4016r:0)  0@3936r
%vreg835 [3920r,3936r:0)  0@3920r
%vreg837 [3888r,3904r:0)  0@3888r
%vreg840 [4928r,4944r:0)  0@4928r
%vreg844 [4864r,4896r:0)[4896r,4912r:1)  0@4864r 1@4896r
%vreg846 [4848r,4912r:0)  0@4848r
%vreg849 [4816r,4832r:0)  0@4816r
%vreg851 [4800r,4832r:0)  0@4800r
%vreg853 [4784r,4800r:0)  0@4784r
%vreg855 [4768r,4784r:0)  0@4768r
%vreg857 [4992r,5008r:0)  0@4992r
%vreg861 [5456r,5488r:0)[5488r,5504r:1)  0@5456r 1@5488r
%vreg864 [5440r,5456r:0)  0@5440r
%vreg866 [5424r,5504r:0)  0@5424r
%vreg867 [5408r,5424r:0)  0@5408r
%vreg871 [5344r,5376r:0)[5376r,5392r:1)  0@5344r 1@5376r
%vreg873 [5328r,5392r:0)  0@5328r
%vreg879 [5248r,5280r:0)[5280r,5312r:1)  0@5248r 1@5280r
%vreg884 [5088r,5232r:0)  0@5088r
%vreg885 [5072r,5232r:0)[5232r,5280r:1)  0@5072r 1@5232r
%vreg887 [5184r,5200r:0)  0@5184r
%vreg891 [5120r,5152r:0)[5152r,5168r:1)  0@5120r 1@5152r
%vreg893 [5104r,5168r:0)  0@5104r
%vreg897 [5600r,5616r:0)  0@5600r
%vreg899 [5584r,5616r:0)  0@5584r
%vreg902 [6560r,6576r:0)  0@6560r
%vreg905 [6528r,6544r:0)  0@6528r
%vreg908 [6112r,6512r:0)[6512r,6544r:1)  0@6112r 1@6512r
%vreg912 [6256r,6416r:2)[6416r,6448r:0)[6448r,6480r:1)[6480r,6512r:3)  0@6416r 1@6448r 2@6256r 3@6480r
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%vreg922 [6272r,6288r:0)  0@6272r
%vreg928 [6240r,6256r:0)  0@6240r
%vreg929 [6224r,6240r:0)  0@6224r
%vreg932 [6192r,6256r:0)  0@6192r
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%vreg937 [6128r,6144r:0)  0@6128r
%vreg943 [6096r,6112r:0)  0@6096r
%vreg944 [6080r,6096r:0)  0@6080r
%vreg947 [6048r,6112r:0)  0@6048r
%vreg949 [6032r,6048r:0)  0@6032r
%vreg955 [5936r,6016r:0)  0@5936r
%vreg958 [5808r,5840r:0)[5840r,5888r:1)  0@5808r 1@5840r
%vreg961 [5792r,5872r:0)  0@5792r
%vreg962 [5776r,5792r:0)  0@5776r
%vreg964 [5744r,5760r:0)  0@5744r
%vreg967 [6784r,6800r:0)  0@6784r
%vreg971 [6720r,6752r:0)[6752r,6768r:1)  0@6720r 1@6752r
%vreg973 [6704r,6768r:0)  0@6704r
%vreg976 [6672r,6688r:0)  0@6672r
%vreg978 [6656r,6688r:0)  0@6656r
%vreg980 [6640r,6656r:0)  0@6640r
%vreg982 [6624r,6640r:0)  0@6624r
%vreg984 [6848r,6864r:0)  0@6848r
%vreg988 [7312r,7344r:0)[7344r,7360r:1)  0@7312r 1@7344r
%vreg991 [7296r,7312r:0)  0@7296r
%vreg993 [7280r,7360r:0)  0@7280r
%vreg994 [7264r,7280r:0)  0@7264r
%vreg998 [7200r,7232r:0)[7232r,7248r:1)  0@7200r 1@7232r
%vreg1000 [7184r,7248r:0)  0@7184r
%vreg1006 [7104r,7136r:0)[7136r,7168r:1)  0@7104r 1@7136r
%vreg1011 [6944r,7088r:0)  0@6944r
%vreg1012 [6928r,7088r:0)[7088r,7136r:1)  0@6928r 1@7088r
%vreg1014 [7040r,7056r:0)  0@7040r
%vreg1018 [6976r,7008r:0)[7008r,7024r:1)  0@6976r 1@7008r
%vreg1020 [6960r,7024r:0)  0@6960r
%vreg1024 [7456r,7472r:0)  0@7456r
%vreg1026 [7440r,7472r:0)  0@7440r
%vreg1029 [8384r,8400r:0)  0@8384r
%vreg1032 [8352r,8368r:0)  0@8352r
%vreg1035 [7936r,8336r:0)[8336r,8368r:1)  0@7936r 1@8336r
%vreg1039 [8080r,8240r:2)[8240r,8272r:0)[8272r,8304r:1)[8304r,8336r:3)  0@8240r 1@8272r 2@8080r 3@8304r
%vreg1044 [8112r,8144r:2)[8144r,8176r:0)[8176r,8192r:1)  0@8144r 1@8176r 2@8112r
%vreg1049 [8096r,8112r:0)  0@8096r
%vreg1055 [8064r,8080r:0)  0@8064r
%vreg1056 [8048r,8064r:0)  0@8048r
%vreg1059 [8016r,8080r:0)  0@8016r
%vreg1061 [7968r,8000r:0)[8000r,8016r:1)  0@7968r 1@8000r
%vreg1064 [7952r,7968r:0)  0@7952r
%vreg1070 [7920r,7936r:0)  0@7920r
%vreg1071 [7904r,7920r:0)  0@7904r
%vreg1074 [7872r,7936r:0)  0@7872r
%vreg1076 [7856r,7872r:0)  0@7856r
%vreg1082 [7760r,7840r:0)  0@7760r
%vreg1085 [7632r,7664r:0)[7664r,7712r:1)  0@7632r 1@7664r
%vreg1088 [7616r,7696r:0)  0@7616r
%vreg1089 [7600r,7616r:0)  0@7600r
%vreg1092 [8608r,8624r:0)  0@8608r
%vreg1096 [8544r,8576r:0)[8576r,8592r:1)  0@8544r 1@8576r
%vreg1098 [8528r,8592r:0)  0@8528r
%vreg1101 [8496r,8512r:0)  0@8496r
%vreg1103 [8480r,8512r:0)  0@8480r
%vreg1105 [8464r,8480r:0)  0@8464r
%vreg1107 [8448r,8464r:0)  0@8448r
%vreg1109 [8672r,8688r:0)  0@8672r
%vreg1112 [9952r,9968r:0)  0@9952r
%vreg1115 [9920r,9936r:0)  0@9920r
%vreg1118 [9504r,9904r:0)[9904r,9936r:1)  0@9504r 1@9904r
%vreg1122 [9648r,9808r:2)[9808r,9840r:0)[9840r,9872r:1)[9872r,9904r:3)  0@9808r 1@9840r 2@9648r 3@9872r
%vreg1127 [9680r,9712r:2)[9712r,9744r:0)[9744r,9760r:1)  0@9712r 1@9744r 2@9680r
%vreg1132 [9664r,9680r:0)  0@9664r
%vreg1138 [9632r,9648r:0)  0@9632r
%vreg1139 [9616r,9632r:0)  0@9616r
%vreg1142 [9584r,9648r:0)  0@9584r
%vreg1144 [9536r,9568r:0)[9568r,9584r:1)  0@9536r 1@9568r
%vreg1147 [9520r,9536r:0)  0@9520r
%vreg1153 [9488r,9504r:0)  0@9488r
%vreg1154 [9472r,9488r:0)  0@9472r
%vreg1157 [9440r,9504r:0)  0@9440r
%vreg1159 [9424r,9440r:0)  0@9424r
%vreg1162 [9392r,9408r:0)  0@9392r
%vreg1165 [9328r,9408r:0)  0@9328r
%vreg1168 [9200r,9232r:0)[9232r,9280r:1)  0@9200r 1@9232r
%vreg1171 [9184r,9264r:0)  0@9184r
%vreg1172 [9168r,9184r:0)  0@9168r
%vreg1175 [9136r,9152r:0)  0@9136r
%vreg1177 [9088r,9120r:0)[9120r,9152r:1)  0@9088r 1@9120r
%vreg1183 [9024r,9056r:0)[9056r,9072r:1)  0@9024r 1@9056r
%vreg1185 [9008r,9072r:0)  0@9008r
%vreg1191 [8928r,8960r:0)[8960r,8992r:1)  0@8928r 1@8960r
%vreg1196 [8768r,8912r:0)  0@8768r
%vreg1197 [8752r,8912r:0)[8912r,8960r:1)  0@8752r 1@8912r
%vreg1199 [8864r,8880r:0)  0@8864r
%vreg1203 [8800r,8832r:0)[8832r,8848r:1)  0@8800r 1@8832r
%vreg1205 [8784r,8848r:0)  0@8784r
%vreg1208 [10176r,10192r:0)  0@10176r
%vreg1212 [10112r,10144r:0)[10144r,10160r:1)  0@10112r 1@10144r
%vreg1214 [10096r,10160r:0)  0@10096r
%vreg1217 [10064r,10080r:0)  0@10064r
%vreg1219 [10048r,10080r:0)  0@10048r
%vreg1221 [10032r,10048r:0)  0@10032r
%vreg1223 [10016r,10032r:0)  0@10016r
%vreg1225 [10240r,10256r:0)  0@10240r
%vreg1229 [10576r,10608r:0)[10608r,10624r:1)  0@10576r 1@10608r
%vreg1231 [10560r,10624r:0)  0@10560r
%vreg1236 [10320r,10480r:2)[10480r,10528r:0)[10528r,10544r:1)  0@10480r 1@10528r 2@10320r
%vreg1237 [10496r,10544r:0)  0@10496r
%vreg1240 [10336r,10480r:0)  0@10336r
%vreg1243 [10432r,10448r:0)  0@10432r
%vreg1247 [10368r,10400r:0)[10400r,10416r:1)  0@10368r 1@10400r
%vreg1249 [10352r,10416r:0)  0@10352r
%vreg1252 [7536r,7552r:0)  0@7536r
%vreg1254 [7520r,7552r:0)  0@7520r
%vreg1257 [5680r,5696r:0)  0@5680r
%vreg1259 [5664r,5696r:0)  0@5664r
%vreg1262 [3824r,3840r:0)  0@3824r
%vreg1264 [3808r,3840r:0)  0@3808r
%vreg1266 [18112r,18128r:0)  0@18112r
%vreg1268 [17936r,18000r:0)  0@17936r
%vreg1269 [17968r,18016r:0)  0@17968r
RegMasks: 144r 2192r 4048r 5904r 7728r 9296r 12560r 13792r 15024r 16224r 17168r 18032r
********** MACHINEINSTRS **********
# Machine code for function unRLE_obuf_to_output_SMALL: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=1, align=1, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=1, align=1, at location [SP+8]
Function Live Ins: %RDI in %vreg0

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI
16B		%vreg1<def> = COPY %RDI; GR64:%vreg1
48B		%vreg6<def> = MOV64ri <ga:@unRLE_obuf_to_output_SMALL>; GR64:%vreg6
80B		%vreg7<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg7
96B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
112B		%RDI<def> = COPY %vreg6; GR64:%vreg6
128B		%RSI<def> = COPY %vreg7; GR64:%vreg7
144B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
160B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
192B		STACKMAP 0, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, %vreg1, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1] GR64:%vreg1
208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%s.addr] GR64:%vreg1
240B		%vreg4<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg4
256B		CMP8mi %vreg4, 1, %noreg, 20, %noreg, 0, %EFLAGS<imp-def>; mem:LD1[%blockRandomised] GR64:%vreg4
272B		JE_1 <BB#47>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#47 BB#1

288B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
304B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2

320B	BB#2: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#1 BB#46 BB#37 BB#35 BB#29 BB#27 BB#21 BB#19
336B		JMP_1 <BB#3>
	    Successors according to CFG: BB#3

352B	BB#3: derived from LLVM BB %while.body.2
	    Predecessors according to CFG: BB#2 BB#9
368B		%vreg534<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg534
384B		%vreg533<def> = MOV64rm %vreg534, 1, %noreg, 0, %noreg; mem:LD8[%strm] GR64:%vreg533,%vreg534
400B		CMP32mi8 %vreg533, 1, %noreg, 32, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_out] GR64:%vreg533
416B		JNE_1 <BB#5>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#5 BB#4

432B	BB#4: derived from LLVM BB %if.then.3
	    Predecessors according to CFG: BB#3
448B		MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST1[%retval]
464B		JMP_1 <BB#73>
	    Successors according to CFG: BB#73

480B	BB#5: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#3
496B		%vreg537<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg537
512B		CMP32mi8 %vreg537, 1, %noreg, 16, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%state_out_len] GR64:%vreg537
528B		JNE_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#6

544B	BB#6: derived from LLVM BB %if.then.5
	    Predecessors according to CFG: BB#5
560B		JMP_1 <BB#10>
	    Successors according to CFG: BB#10

576B	BB#7: derived from LLVM BB %if.end.6
	    Predecessors according to CFG: BB#5
592B		%vreg609<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg609
608B		%vreg608<def> = MOV8rm %vreg609, 1, %noreg, 12, %noreg; mem:LD1[%state_out_ch] GR8:%vreg608 GR64:%vreg609
624B		%vreg606<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg606
640B		%vreg605<def> = MOV64rm %vreg606, 1, %noreg, 0, %noreg; mem:LD8[%strm7] GR64:%vreg605,%vreg606
656B		%vreg603<def> = MOV64rm %vreg605, 1, %noreg, 24, %noreg; mem:LD8[%next_out] GR64:%vreg603,%vreg605
672B		MOV8mr %vreg603, 1, %noreg, 0, %noreg, %vreg608; mem:ST1[%11] GR64:%vreg603 GR8:%vreg608
688B		%vreg599<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg599
704B		%vreg578<def> = MOV32rm %vreg599, 1, %noreg, 3184, %noreg; mem:LD4[%calculatedBlockCRC] GR32:%vreg578 GR64:%vreg599
736B		%vreg578<def,tied1> = SHL32ri %vreg578<tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg578
752B		%vreg594<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg594
768B		%vreg585<def> = MOV32rm %vreg594, 1, %noreg, 3184, %noreg; mem:LD4[%calculatedBlockCRC8] GR32:%vreg585 GR64:%vreg594
800B		%vreg585<def,tied1> = SHR32ri %vreg585<tied0>, 24, %EFLAGS<imp-def,dead>; GR32:%vreg585
816B		%vreg589<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg589
832B		%vreg587<def> = MOVZX32rm8 %vreg589, 1, %noreg, 12, %noreg; mem:LD1[%state_out_ch9] GR32:%vreg587 GR64:%vreg589
864B		%vreg585<def,tied1> = XOR32rr %vreg585<tied0>, %vreg587, %EFLAGS<imp-def,dead>; GR32:%vreg585,%vreg587
880B		%vreg582:sub_32bit<def,read-undef> = MOV32rr %vreg585; GR64_NOSP:%vreg582 GR32:%vreg585
928B		%vreg578<def,tied1> = XOR32rm %vreg578<tied0>, %noreg, 4, %vreg582, <ga:@BZ2_crc32Table>, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%arrayidx] GR32:%vreg578 GR64_NOSP:%vreg582
944B		%vreg575<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg575
960B		MOV32mr %vreg575, 1, %noreg, 3184, %noreg, %vreg578; mem:ST4[%calculatedBlockCRC11] GR64:%vreg575 GR32:%vreg578
976B		%vreg572<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg572
992B		%vreg570<def> = MOV32rm %vreg572, 1, %noreg, 16, %noreg; mem:LD4[%state_out_len12] GR32:%vreg570 GR64:%vreg572
1024B		%vreg570<def,tied1> = ADD32ri8 %vreg570<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg570
1040B		MOV32mr %vreg572, 1, %noreg, 16, %noreg, %vreg570; mem:ST4[%state_out_len12] GR64:%vreg572 GR32:%vreg570
1056B		%vreg566<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg566
1072B		%vreg565<def> = MOV64rm %vreg566, 1, %noreg, 0, %noreg; mem:LD8[%strm13] GR64:%vreg565,%vreg566
1088B		%vreg562<def> = MOV64rm %vreg565, 1, %noreg, 24, %noreg; mem:LD8[%next_out14] GR64:%vreg562,%vreg565
1120B		%vreg562<def,tied1> = ADD64ri8 %vreg562<tied0>, 1, %EFLAGS<imp-def,dead>; GR64:%vreg562
1136B		MOV64mr %vreg565, 1, %noreg, 24, %noreg, %vreg562; mem:ST8[%next_out14] GR64:%vreg565,%vreg562
1152B		%vreg558<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg558
1168B		%vreg557<def> = MOV64rm %vreg558, 1, %noreg, 0, %noreg; mem:LD8[%strm15] GR64:%vreg557,%vreg558
1184B		%vreg554<def> = MOV32rm %vreg557, 1, %noreg, 32, %noreg; mem:LD4[%avail_out16] GR32:%vreg554 GR64:%vreg557
1216B		%vreg554<def,tied1> = ADD32ri8 %vreg554<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg554
1232B		MOV32mr %vreg557, 1, %noreg, 32, %noreg, %vreg554; mem:ST4[%avail_out16] GR64:%vreg557 GR32:%vreg554
1248B		%vreg550<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg550
1264B		%vreg549<def> = MOV64rm %vreg550, 1, %noreg, 0, %noreg; mem:LD8[%strm18] GR64:%vreg549,%vreg550
1280B		%vreg546<def> = MOV32rm %vreg549, 1, %noreg, 36, %noreg; mem:LD4[%total_out_lo32] GR32:%vreg546 GR64:%vreg549
1312B		%vreg546<def,tied1> = ADD32ri8 %vreg546<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg546
1328B		MOV32mr %vreg549, 1, %noreg, 36, %noreg, %vreg546; mem:ST4[%total_out_lo32] GR64:%vreg549 GR32:%vreg546
1344B		%vreg542<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg542
1360B		%vreg541<def> = MOV64rm %vreg542, 1, %noreg, 0, %noreg; mem:LD8[%strm19] GR64:%vreg541,%vreg542
1376B		CMP32mi8 %vreg541, 1, %noreg, 36, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%total_out_lo3220] GR64:%vreg541
1392B		JNE_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#8

1408B	BB#8: derived from LLVM BB %if.then.23
	    Predecessors according to CFG: BB#7
1424B		%vreg617<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg617
1440B		%vreg616<def> = MOV64rm %vreg617, 1, %noreg, 0, %noreg; mem:LD8[%strm24] GR64:%vreg616,%vreg617
1456B		%vreg613<def> = MOV32rm %vreg616, 1, %noreg, 40, %noreg; mem:LD4[%total_out_hi32] GR32:%vreg613 GR64:%vreg616
1488B		%vreg613<def,tied1> = ADD32ri8 %vreg613<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg613
1504B		MOV32mr %vreg616, 1, %noreg, 40, %noreg, %vreg613; mem:ST4[%total_out_hi32] GR64:%vreg616 GR32:%vreg613
	    Successors according to CFG: BB#9

1520B	BB#9: derived from LLVM BB %if.end.26
	    Predecessors according to CFG: BB#7 BB#8
1536B		JMP_1 <BB#3>
	    Successors according to CFG: BB#3

1552B	BB#10: derived from LLVM BB %while.end
	    Predecessors according to CFG: BB#6
1568B		%vreg627<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg627
1584B		%vreg626<def> = MOV32rm %vreg627, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used] GR32:%vreg626 GR64:%vreg627
1600B		%vreg624<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg624
1616B		%vreg621<def> = MOV32rm %vreg624, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock] GR32:%vreg621 GR64:%vreg624
1648B		%vreg621<def,tied1> = ADD32ri8 %vreg621<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg621
1664B		CMP32rr %vreg626, %vreg621, %EFLAGS<imp-def>; GR32:%vreg626,%vreg621
1680B		JNE_1 <BB#12>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#12 BB#11

1696B	BB#11: derived from LLVM BB %if.then.29
	    Predecessors according to CFG: BB#10
1712B		MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST1[%retval]
1728B		JMP_1 <BB#73>
	    Successors according to CFG: BB#73

1744B	BB#12: derived from LLVM BB %if.end.30
	    Predecessors according to CFG: BB#10
1760B		%vreg637<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg637
1776B		%vreg636<def> = MOV32rm %vreg637, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used31] GR32:%vreg636 GR64:%vreg637
1792B		%vreg634<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg634
1808B		%vreg631<def> = MOV32rm %vreg634, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock32] GR32:%vreg631 GR64:%vreg634
1840B		%vreg631<def,tied1> = ADD32ri8 %vreg631<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg631
1856B		CMP32rr %vreg636, %vreg631, %EFLAGS<imp-def>; GR32:%vreg636,%vreg631
1872B		JLE_1 <BB#14>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#14 BB#13

1888B	BB#13: derived from LLVM BB %if.then.36
	    Predecessors according to CFG: BB#12
1904B		MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 1; mem:ST1[%retval]
1920B		JMP_1 <BB#73>
	    Successors according to CFG: BB#73

1936B	BB#14: derived from LLVM BB %if.end.37
	    Predecessors according to CFG: BB#12
1952B		%vreg710<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg710
1968B		MOV32mi %vreg710, 1, %noreg, 16, %noreg, 1; mem:ST4[%state_out_len38] GR64:%vreg710
1984B		%vreg708<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg708
2000B		%vreg707<def> = MOV32rm %vreg708, 1, %noreg, 64, %noreg; mem:LD4[%k0] GR32:%vreg707 GR64:%vreg708
2032B		%vreg703<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg703
2048B		MOV8mr %vreg703, 1, %noreg, 12, %noreg, %vreg707:sub_8bit; mem:ST1[%state_out_ch40] GR64:%vreg703 GR32:%vreg707
2064B		%vreg700<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg700
2080B		%vreg699<def> = MOV32rm %vreg700, 1, %noreg, 60, %noreg; mem:LD4[%tPos] GR32:%vreg699 GR64:%vreg700
2096B		%vreg696<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg696
2128B		%vreg696<def,tied1> = ADD64ri32 %vreg696<tied0>, 1096, %EFLAGS<imp-def,dead>; GR64:%vreg696
2144B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2160B		%EDI<def> = COPY %vreg699; GR32:%vreg699
2176B		%RSI<def> = COPY %vreg696; GR64:%vreg696
2192B		CALL64pcrel32 <ga:@BZ2_indexIntoF>, <regmask>, %RSP<imp-use>, %EDI<imp-use>, %RSI<imp-use,kill>, %EAX<imp-def>
2208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2224B		%vreg693<def> = COPY %EAX<kill>; GR32:%vreg693
2240B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2256B		STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
2272B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2304B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg693:sub_8bit; mem:ST1[%k1] GR32:%vreg693
2320B		%vreg687<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg687
2336B		%vreg685:sub_32bit<def,read-undef> = MOV32rm %vreg687, 1, %noreg, 60, %noreg; mem:LD4[%tPos42] GR64_NOSP:%vreg685 GR64:%vreg687
2368B		%vreg682<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg682
2384B		%vreg681<def> = MOV64rm %vreg682, 1, %noreg, 3160, %noreg; mem:LD8[%ll16] GR64:%vreg681,%vreg682
2400B		%vreg646<def> = MOVZX32rm16 %vreg681, 2, %vreg685, 0, %noreg; mem:LD2[%arrayidx44] GR32:%vreg646 GR64:%vreg681 GR64_NOSP:%vreg685
2416B		%vreg675<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg675
2432B		%vreg672<def> = MOV32rm %vreg675, 1, %noreg, 60, %noreg; mem:LD4[%tPos46] GR32:%vreg672 GR64:%vreg675
2464B		%vreg672<def,tied1> = SHR32ri %vreg672<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg672
2480B		%vreg670:sub_32bit<def,read-undef> = MOV32rr %vreg672; GR64_NOSP:%vreg670 GR32:%vreg672
2512B		%vreg667<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg667
2528B		%vreg666<def> = MOV64rm %vreg667, 1, %noreg, 3168, %noreg; mem:LD8[%ll4] GR64:%vreg666,%vreg667
2544B		%vreg650<def> = MOVZX32rm8 %vreg666, 1, %vreg670, 0, %noreg; mem:LD1[%arrayidx49] GR32:%vreg650 GR64:%vreg666 GR64_NOSP:%vreg670
2560B		%vreg660<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg660
2576B		%vreg655<def> = MOV32rm %vreg660, 1, %noreg, 60, %noreg; mem:LD4[%tPos51] GR32:%vreg655 GR64:%vreg660
2608B		%vreg655<def,tied1> = SHL32ri %vreg655<tied0>, 2, %EFLAGS<imp-def,dead>; GR32:%vreg655
2640B		%vreg655<def,tied1> = AND32ri8 %vreg655<tied0>, 4, %EFLAGS<imp-def,dead>; GR32:%vreg655
2656B		%ECX<def> = COPY %vreg655; GR32:%vreg655
2672B		%CL<def> = KILL %ECX<kill>
2704B		%vreg650<def,tied1> = SHR32rCL %vreg650<tied0>, %EFLAGS<imp-def,dead>, %CL<imp-use,kill>; GR32:%vreg650
2736B		%vreg650<def,tied1> = AND32ri8 %vreg650<tied0>, 15, %EFLAGS<imp-def,dead>; GR32:%vreg650
2768B		%vreg650<def,tied1> = SHL32ri %vreg650<tied0>, 16, %EFLAGS<imp-def,dead>; GR32:%vreg650
2800B		%vreg646<def,tied1> = OR32rr %vreg646<tied0>, %vreg650, %EFLAGS<imp-def,dead>; GR32:%vreg646,%vreg650
2816B		%vreg643<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg643
2832B		MOV32mr %vreg643, 1, %noreg, 60, %noreg, %vreg646; mem:ST4[%tPos56] GR64:%vreg643 GR32:%vreg646
2848B		%vreg640<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg640
2864B		CMP32mi8 %vreg640, 1, %noreg, 24, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%rNToGo] GR64:%vreg640
2880B		JNE_1 <BB#18>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#18 BB#15

2896B	BB#15: derived from LLVM BB %if.then.59
	    Predecessors according to CFG: BB#14
2912B		%vreg728<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg728
2928B		%vreg726<def> = MOVSX64rm32 %vreg728, 1, %noreg, 28, %noreg; mem:LD4[%rTPos] GR64_NOSP:%vreg726 GR64:%vreg728
2944B		%vreg724<def> = MOV32rm %noreg, 4, %vreg726, <ga:@BZ2_rNums>, %noreg; mem:LD4[%arrayidx61] GR32:%vreg724 GR64_NOSP:%vreg726
2960B		%vreg722<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg722
2976B		MOV32mr %vreg722, 1, %noreg, 24, %noreg, %vreg724; mem:ST4[%rNToGo62] GR64:%vreg722 GR32:%vreg724
2992B		%vreg719<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg719
3008B		%vreg717<def> = MOV32rm %vreg719, 1, %noreg, 28, %noreg; mem:LD4[%rTPos63] GR32:%vreg717 GR64:%vreg719
3040B		%vreg717<def,tied1> = ADD32ri8 %vreg717<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg717
3056B		MOV32mr %vreg719, 1, %noreg, 28, %noreg, %vreg717; mem:ST4[%rTPos63] GR64:%vreg719 GR32:%vreg717
3072B		%vreg713<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg713
3088B		CMP32mi %vreg713, 1, %noreg, 28, %noreg, 512, %EFLAGS<imp-def>; mem:LD4[%rTPos65] GR64:%vreg713
3104B		JNE_1 <BB#17>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#17 BB#16

3120B	BB#16: derived from LLVM BB %if.then.68
	    Predecessors according to CFG: BB#15
3136B		%vreg730<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg730
3152B		MOV32mi %vreg730, 1, %noreg, 28, %noreg, 0; mem:ST4[%rTPos69] GR64:%vreg730
	    Successors according to CFG: BB#17

3168B	BB#17: derived from LLVM BB %if.end.70
	    Predecessors according to CFG: BB#15 BB#16
3184B		JMP_1 <BB#18>
	    Successors according to CFG: BB#18

3200B	BB#18: derived from LLVM BB %if.end.71
	    Predecessors according to CFG: BB#14 BB#17
3216B		%vreg758<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg758
3232B		%vreg757<def> = MOV32ri 1; GR32:%vreg757
3248B		%vreg766<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg766
3264B		%vreg764<def> = MOV32rm %vreg766, 1, %noreg, 24, %noreg; mem:LD4[%rNToGo72] GR32:%vreg764 GR64:%vreg766
3296B		%vreg764<def,tied1> = ADD32ri8 %vreg764<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg764
3312B		MOV32mr %vreg766, 1, %noreg, 24, %noreg, %vreg764; mem:ST4[%rNToGo72] GR64:%vreg766 GR32:%vreg764
3328B		%vreg760<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg760
3344B		CMP32mi8 %vreg760, 1, %noreg, 24, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%rNToGo74] GR64:%vreg760
3376B		%vreg758<def,tied1> = CMOVE32rr %vreg758<tied0>, %vreg757, %EFLAGS<imp-use,kill>; GR32:%vreg758,%vreg757
3392B		%vreg752<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg752
3424B		%vreg752<def,tied1> = XOR32rr %vreg752<tied0>, %vreg758, %EFLAGS<imp-def,dead>; GR32:%vreg752,%vreg758
3456B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg752:sub_8bit; mem:ST1[%k1] GR32:%vreg752
3472B		%vreg746<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg746
3488B		%vreg744<def> = MOV32rm %vreg746, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used80] GR32:%vreg744 GR64:%vreg746
3520B		%vreg744<def,tied1> = ADD32ri8 %vreg744<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg744
3536B		MOV32mr %vreg746, 1, %noreg, 1092, %noreg, %vreg744; mem:ST4[%nblock_used80] GR64:%vreg746 GR32:%vreg744
3552B		%vreg740<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg740
3568B		%vreg739<def> = MOV32rm %vreg740, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used82] GR32:%vreg739 GR64:%vreg740
3584B		%vreg737<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg737
3600B		%vreg734<def> = MOV32rm %vreg737, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock83] GR32:%vreg734 GR64:%vreg737
3632B		%vreg734<def,tied1> = ADD32ri8 %vreg734<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg734
3648B		CMP32rr %vreg739, %vreg734, %EFLAGS<imp-def>; GR32:%vreg739,%vreg734
3664B		JNE_1 <BB#20>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#20 BB#19

3680B	BB#19: derived from LLVM BB %if.then.87
	    Predecessors according to CFG: BB#18
3696B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2

3712B	BB#20: derived from LLVM BB %if.end.88
	    Predecessors according to CFG: BB#18
3728B		%vreg772<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg772
3744B		%vreg770<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg770
3760B		CMP32rm %vreg772, %vreg770, 1, %noreg, 64, %noreg, %EFLAGS<imp-def>; mem:LD4[%k090] GR32:%vreg772 GR64:%vreg770
3776B		JE_1 <BB#22>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#22 BB#21

3792B	BB#21: derived from LLVM BB %if.then.93
	    Predecessors according to CFG: BB#20
3808B		%vreg1264<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg1264
3824B		%vreg1262<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1262
3840B		MOV32mr %vreg1262, 1, %noreg, 64, %noreg, %vreg1264; mem:ST4[%k095] GR64:%vreg1262 GR32:%vreg1264
3856B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2

3872B	BB#22: derived from LLVM BB %if.end.96
	    Predecessors according to CFG: BB#20
3888B		%vreg837<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg837
3904B		MOV32mi %vreg837, 1, %noreg, 16, %noreg, 2; mem:ST4[%state_out_len97] GR64:%vreg837
3920B		%vreg835<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg835
3936B		%vreg834<def> = MOV32rm %vreg835, 1, %noreg, 60, %noreg; mem:LD4[%tPos98] GR32:%vreg834 GR64:%vreg835
3952B		%vreg831<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg831
3984B		%vreg831<def,tied1> = ADD64ri32 %vreg831<tied0>, 1096, %EFLAGS<imp-def,dead>; GR64:%vreg831
4000B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4016B		%EDI<def> = COPY %vreg834; GR32:%vreg834
4032B		%RSI<def> = COPY %vreg831; GR64:%vreg831
4048B		CALL64pcrel32 <ga:@BZ2_indexIntoF>, <regmask>, %RSP<imp-use>, %EDI<imp-use>, %RSI<imp-use,kill>, %EAX<imp-def>
4064B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4080B		%vreg828<def> = COPY %EAX<kill>; GR32:%vreg828
4096B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4112B		STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
4128B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4160B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg828:sub_8bit; mem:ST1[%k1] GR32:%vreg828
4176B		%vreg822<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg822
4192B		%vreg820:sub_32bit<def,read-undef> = MOV32rm %vreg822, 1, %noreg, 60, %noreg; mem:LD4[%tPos103] GR64_NOSP:%vreg820 GR64:%vreg822
4224B		%vreg817<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg817
4240B		%vreg816<def> = MOV64rm %vreg817, 1, %noreg, 3160, %noreg; mem:LD8[%ll16105] GR64:%vreg816,%vreg817
4256B		%vreg781<def> = MOVZX32rm16 %vreg816, 2, %vreg820, 0, %noreg; mem:LD2[%arrayidx106] GR32:%vreg781 GR64:%vreg816 GR64_NOSP:%vreg820
4272B		%vreg810<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg810
4288B		%vreg807<def> = MOV32rm %vreg810, 1, %noreg, 60, %noreg; mem:LD4[%tPos108] GR32:%vreg807 GR64:%vreg810
4320B		%vreg807<def,tied1> = SHR32ri %vreg807<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg807
4336B		%vreg805:sub_32bit<def,read-undef> = MOV32rr %vreg807; GR64_NOSP:%vreg805 GR32:%vreg807
4368B		%vreg802<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg802
4384B		%vreg801<def> = MOV64rm %vreg802, 1, %noreg, 3168, %noreg; mem:LD8[%ll4111] GR64:%vreg801,%vreg802
4400B		%vreg785<def> = MOVZX32rm8 %vreg801, 1, %vreg805, 0, %noreg; mem:LD1[%arrayidx112] GR32:%vreg785 GR64:%vreg801 GR64_NOSP:%vreg805
4416B		%vreg795<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg795
4432B		%vreg790<def> = MOV32rm %vreg795, 1, %noreg, 60, %noreg; mem:LD4[%tPos114] GR32:%vreg790 GR64:%vreg795
4464B		%vreg790<def,tied1> = SHL32ri %vreg790<tied0>, 2, %EFLAGS<imp-def,dead>; GR32:%vreg790
4496B		%vreg790<def,tied1> = AND32ri8 %vreg790<tied0>, 4, %EFLAGS<imp-def,dead>; GR32:%vreg790
4512B		%ECX<def> = COPY %vreg790; GR32:%vreg790
4528B		%CL<def> = KILL %ECX<kill>
4560B		%vreg785<def,tied1> = SHR32rCL %vreg785<tied0>, %EFLAGS<imp-def,dead>, %CL<imp-use,kill>; GR32:%vreg785
4592B		%vreg785<def,tied1> = AND32ri8 %vreg785<tied0>, 15, %EFLAGS<imp-def,dead>; GR32:%vreg785
4624B		%vreg785<def,tied1> = SHL32ri %vreg785<tied0>, 16, %EFLAGS<imp-def,dead>; GR32:%vreg785
4656B		%vreg781<def,tied1> = OR32rr %vreg781<tied0>, %vreg785, %EFLAGS<imp-def,dead>; GR32:%vreg781,%vreg785
4672B		%vreg778<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg778
4688B		MOV32mr %vreg778, 1, %noreg, 60, %noreg, %vreg781; mem:ST4[%tPos121] GR64:%vreg778 GR32:%vreg781
4704B		%vreg775<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg775
4720B		CMP32mi8 %vreg775, 1, %noreg, 24, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%rNToGo122] GR64:%vreg775
4736B		JNE_1 <BB#26>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#26 BB#23

4752B	BB#23: derived from LLVM BB %if.then.125
	    Predecessors according to CFG: BB#22
4768B		%vreg855<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg855
4784B		%vreg853<def> = MOVSX64rm32 %vreg855, 1, %noreg, 28, %noreg; mem:LD4[%rTPos126] GR64_NOSP:%vreg853 GR64:%vreg855
4800B		%vreg851<def> = MOV32rm %noreg, 4, %vreg853, <ga:@BZ2_rNums>, %noreg; mem:LD4[%arrayidx128] GR32:%vreg851 GR64_NOSP:%vreg853
4816B		%vreg849<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg849
4832B		MOV32mr %vreg849, 1, %noreg, 24, %noreg, %vreg851; mem:ST4[%rNToGo129] GR64:%vreg849 GR32:%vreg851
4848B		%vreg846<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg846
4864B		%vreg844<def> = MOV32rm %vreg846, 1, %noreg, 28, %noreg; mem:LD4[%rTPos130] GR32:%vreg844 GR64:%vreg846
4896B		%vreg844<def,tied1> = ADD32ri8 %vreg844<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg844
4912B		MOV32mr %vreg846, 1, %noreg, 28, %noreg, %vreg844; mem:ST4[%rTPos130] GR64:%vreg846 GR32:%vreg844
4928B		%vreg840<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg840
4944B		CMP32mi %vreg840, 1, %noreg, 28, %noreg, 512, %EFLAGS<imp-def>; mem:LD4[%rTPos132] GR64:%vreg840
4960B		JNE_1 <BB#25>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#25 BB#24

4976B	BB#24: derived from LLVM BB %if.then.135
	    Predecessors according to CFG: BB#23
4992B		%vreg857<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg857
5008B		MOV32mi %vreg857, 1, %noreg, 28, %noreg, 0; mem:ST4[%rTPos136] GR64:%vreg857
	    Successors according to CFG: BB#25

5024B	BB#25: derived from LLVM BB %if.end.137
	    Predecessors according to CFG: BB#23 BB#24
5040B		JMP_1 <BB#26>
	    Successors according to CFG: BB#26

5056B	BB#26: derived from LLVM BB %if.end.138
	    Predecessors according to CFG: BB#22 BB#25
5072B		%vreg885<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg885
5088B		%vreg884<def> = MOV32ri 1; GR32:%vreg884
5104B		%vreg893<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg893
5120B		%vreg891<def> = MOV32rm %vreg893, 1, %noreg, 24, %noreg; mem:LD4[%rNToGo139] GR32:%vreg891 GR64:%vreg893
5152B		%vreg891<def,tied1> = ADD32ri8 %vreg891<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg891
5168B		MOV32mr %vreg893, 1, %noreg, 24, %noreg, %vreg891; mem:ST4[%rNToGo139] GR64:%vreg893 GR32:%vreg891
5184B		%vreg887<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg887
5200B		CMP32mi8 %vreg887, 1, %noreg, 24, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%rNToGo141] GR64:%vreg887
5232B		%vreg885<def,tied1> = CMOVE32rr %vreg885<tied0>, %vreg884, %EFLAGS<imp-use,kill>; GR32:%vreg885,%vreg884
5248B		%vreg879<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg879
5280B		%vreg879<def,tied1> = XOR32rr %vreg879<tied0>, %vreg885, %EFLAGS<imp-def,dead>; GR32:%vreg879,%vreg885
5312B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg879:sub_8bit; mem:ST1[%k1] GR32:%vreg879
5328B		%vreg873<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg873
5344B		%vreg871<def> = MOV32rm %vreg873, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used148] GR32:%vreg871 GR64:%vreg873
5376B		%vreg871<def,tied1> = ADD32ri8 %vreg871<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg871
5392B		MOV32mr %vreg873, 1, %noreg, 1092, %noreg, %vreg871; mem:ST4[%nblock_used148] GR64:%vreg873 GR32:%vreg871
5408B		%vreg867<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg867
5424B		%vreg866<def> = MOV32rm %vreg867, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used150] GR32:%vreg866 GR64:%vreg867
5440B		%vreg864<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg864
5456B		%vreg861<def> = MOV32rm %vreg864, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock151] GR32:%vreg861 GR64:%vreg864
5488B		%vreg861<def,tied1> = ADD32ri8 %vreg861<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg861
5504B		CMP32rr %vreg866, %vreg861, %EFLAGS<imp-def>; GR32:%vreg866,%vreg861
5520B		JNE_1 <BB#28>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#28 BB#27

5536B	BB#27: derived from LLVM BB %if.then.155
	    Predecessors according to CFG: BB#26
5552B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2

5568B	BB#28: derived from LLVM BB %if.end.156
	    Predecessors according to CFG: BB#26
5584B		%vreg899<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg899
5600B		%vreg897<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg897
5616B		CMP32rm %vreg899, %vreg897, 1, %noreg, 64, %noreg, %EFLAGS<imp-def>; mem:LD4[%k0158] GR32:%vreg899 GR64:%vreg897
5632B		JE_1 <BB#30>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#30 BB#29

5648B	BB#29: derived from LLVM BB %if.then.161
	    Predecessors according to CFG: BB#28
5664B		%vreg1259<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg1259
5680B		%vreg1257<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1257
5696B		MOV32mr %vreg1257, 1, %noreg, 64, %noreg, %vreg1259; mem:ST4[%k0163] GR64:%vreg1257 GR32:%vreg1259
5712B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2

5728B	BB#30: derived from LLVM BB %if.end.164
	    Predecessors according to CFG: BB#28
5744B		%vreg964<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg964
5760B		MOV32mi %vreg964, 1, %noreg, 16, %noreg, 3; mem:ST4[%state_out_len165] GR64:%vreg964
5776B		%vreg962<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg962
5792B		%vreg961<def> = MOV32rm %vreg962, 1, %noreg, 60, %noreg; mem:LD4[%tPos166] GR32:%vreg961 GR64:%vreg962
5808B		%vreg958<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg958
5840B		%vreg958<def,tied1> = ADD64ri32 %vreg958<tied0>, 1096, %EFLAGS<imp-def,dead>; GR64:%vreg958
5856B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5872B		%EDI<def> = COPY %vreg961; GR32:%vreg961
5888B		%RSI<def> = COPY %vreg958; GR64:%vreg958
5904B		CALL64pcrel32 <ga:@BZ2_indexIntoF>, <regmask>, %RSP<imp-use>, %EDI<imp-use>, %RSI<imp-use,kill>, %EAX<imp-def>
5920B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5936B		%vreg955<def> = COPY %EAX<kill>; GR32:%vreg955
5952B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5968B		STACKMAP 3, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
5984B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
6016B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg955:sub_8bit; mem:ST1[%k1] GR32:%vreg955
6032B		%vreg949<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg949
6048B		%vreg947:sub_32bit<def,read-undef> = MOV32rm %vreg949, 1, %noreg, 60, %noreg; mem:LD4[%tPos171] GR64_NOSP:%vreg947 GR64:%vreg949
6080B		%vreg944<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg944
6096B		%vreg943<def> = MOV64rm %vreg944, 1, %noreg, 3160, %noreg; mem:LD8[%ll16173] GR64:%vreg943,%vreg944
6112B		%vreg908<def> = MOVZX32rm16 %vreg943, 2, %vreg947, 0, %noreg; mem:LD2[%arrayidx174] GR32:%vreg908 GR64:%vreg943 GR64_NOSP:%vreg947
6128B		%vreg937<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg937
6144B		%vreg934<def> = MOV32rm %vreg937, 1, %noreg, 60, %noreg; mem:LD4[%tPos176] GR32:%vreg934 GR64:%vreg937
6176B		%vreg934<def,tied1> = SHR32ri %vreg934<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg934
6192B		%vreg932:sub_32bit<def,read-undef> = MOV32rr %vreg934; GR64_NOSP:%vreg932 GR32:%vreg934
6224B		%vreg929<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg929
6240B		%vreg928<def> = MOV64rm %vreg929, 1, %noreg, 3168, %noreg; mem:LD8[%ll4179] GR64:%vreg928,%vreg929
6256B		%vreg912<def> = MOVZX32rm8 %vreg928, 1, %vreg932, 0, %noreg; mem:LD1[%arrayidx180] GR32:%vreg912 GR64:%vreg928 GR64_NOSP:%vreg932
6272B		%vreg922<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg922
6288B		%vreg917<def> = MOV32rm %vreg922, 1, %noreg, 60, %noreg; mem:LD4[%tPos182] GR32:%vreg917 GR64:%vreg922
6320B		%vreg917<def,tied1> = SHL32ri %vreg917<tied0>, 2, %EFLAGS<imp-def,dead>; GR32:%vreg917
6352B		%vreg917<def,tied1> = AND32ri8 %vreg917<tied0>, 4, %EFLAGS<imp-def,dead>; GR32:%vreg917
6368B		%ECX<def> = COPY %vreg917; GR32:%vreg917
6384B		%CL<def> = KILL %ECX<kill>
6416B		%vreg912<def,tied1> = SHR32rCL %vreg912<tied0>, %EFLAGS<imp-def,dead>, %CL<imp-use,kill>; GR32:%vreg912
6448B		%vreg912<def,tied1> = AND32ri8 %vreg912<tied0>, 15, %EFLAGS<imp-def,dead>; GR32:%vreg912
6480B		%vreg912<def,tied1> = SHL32ri %vreg912<tied0>, 16, %EFLAGS<imp-def,dead>; GR32:%vreg912
6512B		%vreg908<def,tied1> = OR32rr %vreg908<tied0>, %vreg912, %EFLAGS<imp-def,dead>; GR32:%vreg908,%vreg912
6528B		%vreg905<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg905
6544B		MOV32mr %vreg905, 1, %noreg, 60, %noreg, %vreg908; mem:ST4[%tPos189] GR64:%vreg905 GR32:%vreg908
6560B		%vreg902<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg902
6576B		CMP32mi8 %vreg902, 1, %noreg, 24, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%rNToGo190] GR64:%vreg902
6592B		JNE_1 <BB#34>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#34 BB#31

6608B	BB#31: derived from LLVM BB %if.then.193
	    Predecessors according to CFG: BB#30
6624B		%vreg982<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg982
6640B		%vreg980<def> = MOVSX64rm32 %vreg982, 1, %noreg, 28, %noreg; mem:LD4[%rTPos194] GR64_NOSP:%vreg980 GR64:%vreg982
6656B		%vreg978<def> = MOV32rm %noreg, 4, %vreg980, <ga:@BZ2_rNums>, %noreg; mem:LD4[%arrayidx196] GR32:%vreg978 GR64_NOSP:%vreg980
6672B		%vreg976<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg976
6688B		MOV32mr %vreg976, 1, %noreg, 24, %noreg, %vreg978; mem:ST4[%rNToGo197] GR64:%vreg976 GR32:%vreg978
6704B		%vreg973<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg973
6720B		%vreg971<def> = MOV32rm %vreg973, 1, %noreg, 28, %noreg; mem:LD4[%rTPos198] GR32:%vreg971 GR64:%vreg973
6752B		%vreg971<def,tied1> = ADD32ri8 %vreg971<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg971
6768B		MOV32mr %vreg973, 1, %noreg, 28, %noreg, %vreg971; mem:ST4[%rTPos198] GR64:%vreg973 GR32:%vreg971
6784B		%vreg967<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg967
6800B		CMP32mi %vreg967, 1, %noreg, 28, %noreg, 512, %EFLAGS<imp-def>; mem:LD4[%rTPos200] GR64:%vreg967
6816B		JNE_1 <BB#33>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#33 BB#32

6832B	BB#32: derived from LLVM BB %if.then.203
	    Predecessors according to CFG: BB#31
6848B		%vreg984<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg984
6864B		MOV32mi %vreg984, 1, %noreg, 28, %noreg, 0; mem:ST4[%rTPos204] GR64:%vreg984
	    Successors according to CFG: BB#33

6880B	BB#33: derived from LLVM BB %if.end.205
	    Predecessors according to CFG: BB#31 BB#32
6896B		JMP_1 <BB#34>
	    Successors according to CFG: BB#34

6912B	BB#34: derived from LLVM BB %if.end.206
	    Predecessors according to CFG: BB#30 BB#33
6928B		%vreg1012<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg1012
6944B		%vreg1011<def> = MOV32ri 1; GR32:%vreg1011
6960B		%vreg1020<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1020
6976B		%vreg1018<def> = MOV32rm %vreg1020, 1, %noreg, 24, %noreg; mem:LD4[%rNToGo207] GR32:%vreg1018 GR64:%vreg1020
7008B		%vreg1018<def,tied1> = ADD32ri8 %vreg1018<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg1018
7024B		MOV32mr %vreg1020, 1, %noreg, 24, %noreg, %vreg1018; mem:ST4[%rNToGo207] GR64:%vreg1020 GR32:%vreg1018
7040B		%vreg1014<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1014
7056B		CMP32mi8 %vreg1014, 1, %noreg, 24, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%rNToGo209] GR64:%vreg1014
7088B		%vreg1012<def,tied1> = CMOVE32rr %vreg1012<tied0>, %vreg1011, %EFLAGS<imp-use,kill>; GR32:%vreg1012,%vreg1011
7104B		%vreg1006<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg1006
7136B		%vreg1006<def,tied1> = XOR32rr %vreg1006<tied0>, %vreg1012, %EFLAGS<imp-def,dead>; GR32:%vreg1006,%vreg1012
7168B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg1006:sub_8bit; mem:ST1[%k1] GR32:%vreg1006
7184B		%vreg1000<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1000
7200B		%vreg998<def> = MOV32rm %vreg1000, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used216] GR32:%vreg998 GR64:%vreg1000
7232B		%vreg998<def,tied1> = ADD32ri8 %vreg998<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg998
7248B		MOV32mr %vreg1000, 1, %noreg, 1092, %noreg, %vreg998; mem:ST4[%nblock_used216] GR64:%vreg1000 GR32:%vreg998
7264B		%vreg994<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg994
7280B		%vreg993<def> = MOV32rm %vreg994, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used218] GR32:%vreg993 GR64:%vreg994
7296B		%vreg991<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg991
7312B		%vreg988<def> = MOV32rm %vreg991, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock219] GR32:%vreg988 GR64:%vreg991
7344B		%vreg988<def,tied1> = ADD32ri8 %vreg988<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg988
7360B		CMP32rr %vreg993, %vreg988, %EFLAGS<imp-def>; GR32:%vreg993,%vreg988
7376B		JNE_1 <BB#36>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#36 BB#35

7392B	BB#35: derived from LLVM BB %if.then.223
	    Predecessors according to CFG: BB#34
7408B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2

7424B	BB#36: derived from LLVM BB %if.end.224
	    Predecessors according to CFG: BB#34
7440B		%vreg1026<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg1026
7456B		%vreg1024<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1024
7472B		CMP32rm %vreg1026, %vreg1024, 1, %noreg, 64, %noreg, %EFLAGS<imp-def>; mem:LD4[%k0226] GR32:%vreg1026 GR64:%vreg1024
7488B		JE_1 <BB#38>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#38 BB#37

7504B	BB#37: derived from LLVM BB %if.then.229
	    Predecessors according to CFG: BB#36
7520B		%vreg1254<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg1254
7536B		%vreg1252<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1252
7552B		MOV32mr %vreg1252, 1, %noreg, 64, %noreg, %vreg1254; mem:ST4[%k0231] GR64:%vreg1252 GR32:%vreg1254
7568B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2

7584B	BB#38: derived from LLVM BB %if.end.232
	    Predecessors according to CFG: BB#36
7600B		%vreg1089<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1089
7616B		%vreg1088<def> = MOV32rm %vreg1089, 1, %noreg, 60, %noreg; mem:LD4[%tPos233] GR32:%vreg1088 GR64:%vreg1089
7632B		%vreg1085<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1085
7664B		%vreg1085<def,tied1> = ADD64ri32 %vreg1085<tied0>, 1096, %EFLAGS<imp-def,dead>; GR64:%vreg1085
7680B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
7696B		%EDI<def> = COPY %vreg1088; GR32:%vreg1088
7712B		%RSI<def> = COPY %vreg1085; GR64:%vreg1085
7728B		CALL64pcrel32 <ga:@BZ2_indexIntoF>, <regmask>, %RSP<imp-use>, %EDI<imp-use>, %RSI<imp-use,kill>, %EAX<imp-def>
7744B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
7760B		%vreg1082<def> = COPY %EAX<kill>; GR32:%vreg1082
7776B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
7792B		STACKMAP 4, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
7808B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
7840B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg1082:sub_8bit; mem:ST1[%k1] GR32:%vreg1082
7856B		%vreg1076<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1076
7872B		%vreg1074:sub_32bit<def,read-undef> = MOV32rm %vreg1076, 1, %noreg, 60, %noreg; mem:LD4[%tPos238] GR64_NOSP:%vreg1074 GR64:%vreg1076
7904B		%vreg1071<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1071
7920B		%vreg1070<def> = MOV64rm %vreg1071, 1, %noreg, 3160, %noreg; mem:LD8[%ll16240] GR64:%vreg1070,%vreg1071
7936B		%vreg1035<def> = MOVZX32rm16 %vreg1070, 2, %vreg1074, 0, %noreg; mem:LD2[%arrayidx241] GR32:%vreg1035 GR64:%vreg1070 GR64_NOSP:%vreg1074
7952B		%vreg1064<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1064
7968B		%vreg1061<def> = MOV32rm %vreg1064, 1, %noreg, 60, %noreg; mem:LD4[%tPos243] GR32:%vreg1061 GR64:%vreg1064
8000B		%vreg1061<def,tied1> = SHR32ri %vreg1061<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg1061
8016B		%vreg1059:sub_32bit<def,read-undef> = MOV32rr %vreg1061; GR64_NOSP:%vreg1059 GR32:%vreg1061
8048B		%vreg1056<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1056
8064B		%vreg1055<def> = MOV64rm %vreg1056, 1, %noreg, 3168, %noreg; mem:LD8[%ll4246] GR64:%vreg1055,%vreg1056
8080B		%vreg1039<def> = MOVZX32rm8 %vreg1055, 1, %vreg1059, 0, %noreg; mem:LD1[%arrayidx247] GR32:%vreg1039 GR64:%vreg1055 GR64_NOSP:%vreg1059
8096B		%vreg1049<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1049
8112B		%vreg1044<def> = MOV32rm %vreg1049, 1, %noreg, 60, %noreg; mem:LD4[%tPos249] GR32:%vreg1044 GR64:%vreg1049
8144B		%vreg1044<def,tied1> = SHL32ri %vreg1044<tied0>, 2, %EFLAGS<imp-def,dead>; GR32:%vreg1044
8176B		%vreg1044<def,tied1> = AND32ri8 %vreg1044<tied0>, 4, %EFLAGS<imp-def,dead>; GR32:%vreg1044
8192B		%ECX<def> = COPY %vreg1044; GR32:%vreg1044
8208B		%CL<def> = KILL %ECX<kill>
8240B		%vreg1039<def,tied1> = SHR32rCL %vreg1039<tied0>, %EFLAGS<imp-def,dead>, %CL<imp-use,kill>; GR32:%vreg1039
8272B		%vreg1039<def,tied1> = AND32ri8 %vreg1039<tied0>, 15, %EFLAGS<imp-def,dead>; GR32:%vreg1039
8304B		%vreg1039<def,tied1> = SHL32ri %vreg1039<tied0>, 16, %EFLAGS<imp-def,dead>; GR32:%vreg1039
8336B		%vreg1035<def,tied1> = OR32rr %vreg1035<tied0>, %vreg1039, %EFLAGS<imp-def,dead>; GR32:%vreg1035,%vreg1039
8352B		%vreg1032<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1032
8368B		MOV32mr %vreg1032, 1, %noreg, 60, %noreg, %vreg1035; mem:ST4[%tPos256] GR64:%vreg1032 GR32:%vreg1035
8384B		%vreg1029<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1029
8400B		CMP32mi8 %vreg1029, 1, %noreg, 24, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%rNToGo257] GR64:%vreg1029
8416B		JNE_1 <BB#42>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#42 BB#39

8432B	BB#39: derived from LLVM BB %if.then.260
	    Predecessors according to CFG: BB#38
8448B		%vreg1107<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1107
8464B		%vreg1105<def> = MOVSX64rm32 %vreg1107, 1, %noreg, 28, %noreg; mem:LD4[%rTPos261] GR64_NOSP:%vreg1105 GR64:%vreg1107
8480B		%vreg1103<def> = MOV32rm %noreg, 4, %vreg1105, <ga:@BZ2_rNums>, %noreg; mem:LD4[%arrayidx263] GR32:%vreg1103 GR64_NOSP:%vreg1105
8496B		%vreg1101<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1101
8512B		MOV32mr %vreg1101, 1, %noreg, 24, %noreg, %vreg1103; mem:ST4[%rNToGo264] GR64:%vreg1101 GR32:%vreg1103
8528B		%vreg1098<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1098
8544B		%vreg1096<def> = MOV32rm %vreg1098, 1, %noreg, 28, %noreg; mem:LD4[%rTPos265] GR32:%vreg1096 GR64:%vreg1098
8576B		%vreg1096<def,tied1> = ADD32ri8 %vreg1096<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg1096
8592B		MOV32mr %vreg1098, 1, %noreg, 28, %noreg, %vreg1096; mem:ST4[%rTPos265] GR64:%vreg1098 GR32:%vreg1096
8608B		%vreg1092<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1092
8624B		CMP32mi %vreg1092, 1, %noreg, 28, %noreg, 512, %EFLAGS<imp-def>; mem:LD4[%rTPos267] GR64:%vreg1092
8640B		JNE_1 <BB#41>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#41 BB#40

8656B	BB#40: derived from LLVM BB %if.then.270
	    Predecessors according to CFG: BB#39
8672B		%vreg1109<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1109
8688B		MOV32mi %vreg1109, 1, %noreg, 28, %noreg, 0; mem:ST4[%rTPos271] GR64:%vreg1109
	    Successors according to CFG: BB#41

8704B	BB#41: derived from LLVM BB %if.end.272
	    Predecessors according to CFG: BB#39 BB#40
8720B		JMP_1 <BB#42>
	    Successors according to CFG: BB#42

8736B	BB#42: derived from LLVM BB %if.end.273
	    Predecessors according to CFG: BB#38 BB#41
8752B		%vreg1197<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg1197
8768B		%vreg1196<def> = MOV32ri 1; GR32:%vreg1196
8784B		%vreg1205<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1205
8800B		%vreg1203<def> = MOV32rm %vreg1205, 1, %noreg, 24, %noreg; mem:LD4[%rNToGo274] GR32:%vreg1203 GR64:%vreg1205
8832B		%vreg1203<def,tied1> = ADD32ri8 %vreg1203<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg1203
8848B		MOV32mr %vreg1205, 1, %noreg, 24, %noreg, %vreg1203; mem:ST4[%rNToGo274] GR64:%vreg1205 GR32:%vreg1203
8864B		%vreg1199<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1199
8880B		CMP32mi8 %vreg1199, 1, %noreg, 24, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%rNToGo276] GR64:%vreg1199
8912B		%vreg1197<def,tied1> = CMOVE32rr %vreg1197<tied0>, %vreg1196, %EFLAGS<imp-use,kill>; GR32:%vreg1197,%vreg1196
8928B		%vreg1191<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg1191
8960B		%vreg1191<def,tied1> = XOR32rr %vreg1191<tied0>, %vreg1197, %EFLAGS<imp-def,dead>; GR32:%vreg1191,%vreg1197
8992B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg1191:sub_8bit; mem:ST1[%k1] GR32:%vreg1191
9008B		%vreg1185<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1185
9024B		%vreg1183<def> = MOV32rm %vreg1185, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used283] GR32:%vreg1183 GR64:%vreg1185
9056B		%vreg1183<def,tied1> = ADD32ri8 %vreg1183<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg1183
9072B		MOV32mr %vreg1185, 1, %noreg, 1092, %noreg, %vreg1183; mem:ST4[%nblock_used283] GR64:%vreg1185 GR32:%vreg1183
9088B		%vreg1177<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg1177
9120B		%vreg1177<def,tied1> = ADD32ri8 %vreg1177<tied0>, 4, %EFLAGS<imp-def,dead>; GR32:%vreg1177
9136B		%vreg1175<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1175
9152B		MOV32mr %vreg1175, 1, %noreg, 16, %noreg, %vreg1177; mem:ST4[%state_out_len287] GR64:%vreg1175 GR32:%vreg1177
9168B		%vreg1172<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1172
9184B		%vreg1171<def> = MOV32rm %vreg1172, 1, %noreg, 60, %noreg; mem:LD4[%tPos288] GR32:%vreg1171 GR64:%vreg1172
9200B		%vreg1168<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1168
9232B		%vreg1168<def,tied1> = ADD64ri32 %vreg1168<tied0>, 1096, %EFLAGS<imp-def,dead>; GR64:%vreg1168
9248B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
9264B		%EDI<def> = COPY %vreg1171; GR32:%vreg1171
9280B		%RSI<def> = COPY %vreg1168; GR64:%vreg1168
9296B		CALL64pcrel32 <ga:@BZ2_indexIntoF>, <regmask>, %RSP<imp-use>, %EDI<imp-use>, %RSI<imp-use,kill>, %EAX<imp-def>
9312B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
9328B		%vreg1165<def> = COPY %EAX<kill>; GR32:%vreg1165
9344B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
9360B		STACKMAP 5, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
9376B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
9392B		%vreg1162<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1162
9408B		MOV32mr %vreg1162, 1, %noreg, 64, %noreg, %vreg1165; mem:ST4[%k0292] GR64:%vreg1162 GR32:%vreg1165
9424B		%vreg1159<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1159
9440B		%vreg1157:sub_32bit<def,read-undef> = MOV32rm %vreg1159, 1, %noreg, 60, %noreg; mem:LD4[%tPos293] GR64_NOSP:%vreg1157 GR64:%vreg1159
9472B		%vreg1154<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1154
9488B		%vreg1153<def> = MOV64rm %vreg1154, 1, %noreg, 3160, %noreg; mem:LD8[%ll16295] GR64:%vreg1153,%vreg1154
9504B		%vreg1118<def> = MOVZX32rm16 %vreg1153, 2, %vreg1157, 0, %noreg; mem:LD2[%arrayidx296] GR32:%vreg1118 GR64:%vreg1153 GR64_NOSP:%vreg1157
9520B		%vreg1147<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1147
9536B		%vreg1144<def> = MOV32rm %vreg1147, 1, %noreg, 60, %noreg; mem:LD4[%tPos298] GR32:%vreg1144 GR64:%vreg1147
9568B		%vreg1144<def,tied1> = SHR32ri %vreg1144<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg1144
9584B		%vreg1142:sub_32bit<def,read-undef> = MOV32rr %vreg1144; GR64_NOSP:%vreg1142 GR32:%vreg1144
9616B		%vreg1139<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1139
9632B		%vreg1138<def> = MOV64rm %vreg1139, 1, %noreg, 3168, %noreg; mem:LD8[%ll4301] GR64:%vreg1138,%vreg1139
9648B		%vreg1122<def> = MOVZX32rm8 %vreg1138, 1, %vreg1142, 0, %noreg; mem:LD1[%arrayidx302] GR32:%vreg1122 GR64:%vreg1138 GR64_NOSP:%vreg1142
9664B		%vreg1132<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1132
9680B		%vreg1127<def> = MOV32rm %vreg1132, 1, %noreg, 60, %noreg; mem:LD4[%tPos304] GR32:%vreg1127 GR64:%vreg1132
9712B		%vreg1127<def,tied1> = SHL32ri %vreg1127<tied0>, 2, %EFLAGS<imp-def,dead>; GR32:%vreg1127
9744B		%vreg1127<def,tied1> = AND32ri8 %vreg1127<tied0>, 4, %EFLAGS<imp-def,dead>; GR32:%vreg1127
9760B		%ECX<def> = COPY %vreg1127; GR32:%vreg1127
9776B		%CL<def> = KILL %ECX<kill>
9808B		%vreg1122<def,tied1> = SHR32rCL %vreg1122<tied0>, %EFLAGS<imp-def,dead>, %CL<imp-use,kill>; GR32:%vreg1122
9840B		%vreg1122<def,tied1> = AND32ri8 %vreg1122<tied0>, 15, %EFLAGS<imp-def,dead>; GR32:%vreg1122
9872B		%vreg1122<def,tied1> = SHL32ri %vreg1122<tied0>, 16, %EFLAGS<imp-def,dead>; GR32:%vreg1122
9904B		%vreg1118<def,tied1> = OR32rr %vreg1118<tied0>, %vreg1122, %EFLAGS<imp-def,dead>; GR32:%vreg1118,%vreg1122
9920B		%vreg1115<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1115
9936B		MOV32mr %vreg1115, 1, %noreg, 60, %noreg, %vreg1118; mem:ST4[%tPos311] GR64:%vreg1115 GR32:%vreg1118
9952B		%vreg1112<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1112
9968B		CMP32mi8 %vreg1112, 1, %noreg, 24, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%rNToGo312] GR64:%vreg1112
9984B		JNE_1 <BB#46>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#46 BB#43

10000B	BB#43: derived from LLVM BB %if.then.315
	    Predecessors according to CFG: BB#42
10016B		%vreg1223<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1223
10032B		%vreg1221<def> = MOVSX64rm32 %vreg1223, 1, %noreg, 28, %noreg; mem:LD4[%rTPos316] GR64_NOSP:%vreg1221 GR64:%vreg1223
10048B		%vreg1219<def> = MOV32rm %noreg, 4, %vreg1221, <ga:@BZ2_rNums>, %noreg; mem:LD4[%arrayidx318] GR32:%vreg1219 GR64_NOSP:%vreg1221
10064B		%vreg1217<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1217
10080B		MOV32mr %vreg1217, 1, %noreg, 24, %noreg, %vreg1219; mem:ST4[%rNToGo319] GR64:%vreg1217 GR32:%vreg1219
10096B		%vreg1214<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1214
10112B		%vreg1212<def> = MOV32rm %vreg1214, 1, %noreg, 28, %noreg; mem:LD4[%rTPos320] GR32:%vreg1212 GR64:%vreg1214
10144B		%vreg1212<def,tied1> = ADD32ri8 %vreg1212<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg1212
10160B		MOV32mr %vreg1214, 1, %noreg, 28, %noreg, %vreg1212; mem:ST4[%rTPos320] GR64:%vreg1214 GR32:%vreg1212
10176B		%vreg1208<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1208
10192B		CMP32mi %vreg1208, 1, %noreg, 28, %noreg, 512, %EFLAGS<imp-def>; mem:LD4[%rTPos322] GR64:%vreg1208
10208B		JNE_1 <BB#45>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#45 BB#44

10224B	BB#44: derived from LLVM BB %if.then.325
	    Predecessors according to CFG: BB#43
10240B		%vreg1225<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1225
10256B		MOV32mi %vreg1225, 1, %noreg, 28, %noreg, 0; mem:ST4[%rTPos326] GR64:%vreg1225
	    Successors according to CFG: BB#45

10272B	BB#45: derived from LLVM BB %if.end.327
	    Predecessors according to CFG: BB#43 BB#44
10288B		JMP_1 <BB#46>
	    Successors according to CFG: BB#46

10304B	BB#46: derived from LLVM BB %if.end.328
	    Predecessors according to CFG: BB#42 BB#45
10320B		%vreg1236<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg1236
10336B		%vreg1240<def> = MOV32ri 1; GR32:%vreg1240
10352B		%vreg1249<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1249
10368B		%vreg1247<def> = MOV32rm %vreg1249, 1, %noreg, 24, %noreg; mem:LD4[%rNToGo329] GR32:%vreg1247 GR64:%vreg1249
10400B		%vreg1247<def,tied1> = ADD32ri8 %vreg1247<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg1247
10416B		MOV32mr %vreg1249, 1, %noreg, 24, %noreg, %vreg1247; mem:ST4[%rNToGo329] GR64:%vreg1249 GR32:%vreg1247
10432B		%vreg1243<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1243
10448B		CMP32mi8 %vreg1243, 1, %noreg, 24, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%rNToGo331] GR64:%vreg1243
10480B		%vreg1236<def,tied1> = CMOVE32rr %vreg1236<tied0>, %vreg1240, %EFLAGS<imp-use,kill>; GR32:%vreg1236,%vreg1240
10496B		%vreg1237<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1237
10528B		%vreg1236<def,tied1> = XOR32rm %vreg1236<tied0>, %vreg1237, 1, %noreg, 64, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%k0335] GR32:%vreg1236 GR64:%vreg1237
10544B		MOV32mr %vreg1237, 1, %noreg, 64, %noreg, %vreg1236; mem:ST4[%k0335] GR64:%vreg1237 GR32:%vreg1236
10560B		%vreg1231<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1231
10576B		%vreg1229<def> = MOV32rm %vreg1231, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used337] GR32:%vreg1229 GR64:%vreg1231
10608B		%vreg1229<def,tied1> = ADD32ri8 %vreg1229<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg1229
10624B		MOV32mr %vreg1231, 1, %noreg, 1092, %noreg, %vreg1229; mem:ST4[%nblock_used337] GR64:%vreg1231 GR32:%vreg1229
10640B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2

10656B	BB#47: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#0
10672B		JMP_1 <BB#48>
	    Successors according to CFG: BB#48

10688B	BB#48: derived from LLVM BB %while.body.339
	    Predecessors according to CFG: BB#47 BB#72 BB#71 BB#69 BB#67 BB#65 BB#63 BB#61
10704B		JMP_1 <BB#49>
	    Successors according to CFG: BB#49

10720B	BB#49: derived from LLVM BB %while.body.341
	    Predecessors according to CFG: BB#48 BB#55
10736B		%vreg12<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg12
10752B		%vreg11<def> = MOV64rm %vreg12, 1, %noreg, 0, %noreg; mem:LD8[%strm342] GR64:%vreg11,%vreg12
10768B		CMP32mi8 %vreg11, 1, %noreg, 32, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_out343] GR64:%vreg11
10784B		JNE_1 <BB#51>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#51 BB#50

10800B	BB#50: derived from LLVM BB %if.then.346
	    Predecessors according to CFG: BB#49
10816B		MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST1[%retval]
10832B		JMP_1 <BB#73>
	    Successors according to CFG: BB#73

10848B	BB#51: derived from LLVM BB %if.end.347
	    Predecessors according to CFG: BB#49
10864B		%vreg15<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg15
10880B		CMP32mi8 %vreg15, 1, %noreg, 16, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%state_out_len348] GR64:%vreg15
10896B		JNE_1 <BB#53>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#53 BB#52

10912B	BB#52: derived from LLVM BB %if.then.351
	    Predecessors according to CFG: BB#51
10928B		JMP_1 <BB#56>
	    Successors according to CFG: BB#56

10944B	BB#53: derived from LLVM BB %if.end.352
	    Predecessors according to CFG: BB#51
10960B		%vreg87<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg87
10976B		%vreg86<def> = MOV8rm %vreg87, 1, %noreg, 12, %noreg; mem:LD1[%state_out_ch353] GR8:%vreg86 GR64:%vreg87
10992B		%vreg84<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg84
11008B		%vreg83<def> = MOV64rm %vreg84, 1, %noreg, 0, %noreg; mem:LD8[%strm354] GR64:%vreg83,%vreg84
11024B		%vreg81<def> = MOV64rm %vreg83, 1, %noreg, 24, %noreg; mem:LD8[%next_out355] GR64:%vreg81,%vreg83
11040B		MOV8mr %vreg81, 1, %noreg, 0, %noreg, %vreg86; mem:ST1[%261] GR64:%vreg81 GR8:%vreg86
11056B		%vreg77<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg77
11072B		%vreg56<def> = MOV32rm %vreg77, 1, %noreg, 3184, %noreg; mem:LD4[%calculatedBlockCRC356] GR32:%vreg56 GR64:%vreg77
11104B		%vreg56<def,tied1> = SHL32ri %vreg56<tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg56
11120B		%vreg72<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg72
11136B		%vreg63<def> = MOV32rm %vreg72, 1, %noreg, 3184, %noreg; mem:LD4[%calculatedBlockCRC358] GR32:%vreg63 GR64:%vreg72
11168B		%vreg63<def,tied1> = SHR32ri %vreg63<tied0>, 24, %EFLAGS<imp-def,dead>; GR32:%vreg63
11184B		%vreg67<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg67
11200B		%vreg65<def> = MOVZX32rm8 %vreg67, 1, %noreg, 12, %noreg; mem:LD1[%state_out_ch360] GR32:%vreg65 GR64:%vreg67
11232B		%vreg63<def,tied1> = XOR32rr %vreg63<tied0>, %vreg65, %EFLAGS<imp-def,dead>; GR32:%vreg63,%vreg65
11248B		%vreg60:sub_32bit<def,read-undef> = MOV32rr %vreg63; GR64_NOSP:%vreg60 GR32:%vreg63
11296B		%vreg56<def,tied1> = XOR32rm %vreg56<tied0>, %noreg, 4, %vreg60, <ga:@BZ2_crc32Table>, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%arrayidx364] GR32:%vreg56 GR64_NOSP:%vreg60
11312B		%vreg53<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg53
11328B		MOV32mr %vreg53, 1, %noreg, 3184, %noreg, %vreg56; mem:ST4[%calculatedBlockCRC366] GR64:%vreg53 GR32:%vreg56
11344B		%vreg50<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg50
11360B		%vreg48<def> = MOV32rm %vreg50, 1, %noreg, 16, %noreg; mem:LD4[%state_out_len367] GR32:%vreg48 GR64:%vreg50
11392B		%vreg48<def,tied1> = ADD32ri8 %vreg48<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg48
11408B		MOV32mr %vreg50, 1, %noreg, 16, %noreg, %vreg48; mem:ST4[%state_out_len367] GR64:%vreg50 GR32:%vreg48
11424B		%vreg44<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg44
11440B		%vreg43<def> = MOV64rm %vreg44, 1, %noreg, 0, %noreg; mem:LD8[%strm369] GR64:%vreg43,%vreg44
11456B		%vreg40<def> = MOV64rm %vreg43, 1, %noreg, 24, %noreg; mem:LD8[%next_out370] GR64:%vreg40,%vreg43
11488B		%vreg40<def,tied1> = ADD64ri8 %vreg40<tied0>, 1, %EFLAGS<imp-def,dead>; GR64:%vreg40
11504B		MOV64mr %vreg43, 1, %noreg, 24, %noreg, %vreg40; mem:ST8[%next_out370] GR64:%vreg43,%vreg40
11520B		%vreg36<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg36
11536B		%vreg35<def> = MOV64rm %vreg36, 1, %noreg, 0, %noreg; mem:LD8[%strm372] GR64:%vreg35,%vreg36
11552B		%vreg32<def> = MOV32rm %vreg35, 1, %noreg, 32, %noreg; mem:LD4[%avail_out373] GR32:%vreg32 GR64:%vreg35
11584B		%vreg32<def,tied1> = ADD32ri8 %vreg32<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg32
11600B		MOV32mr %vreg35, 1, %noreg, 32, %noreg, %vreg32; mem:ST4[%avail_out373] GR64:%vreg35 GR32:%vreg32
11616B		%vreg28<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg28
11632B		%vreg27<def> = MOV64rm %vreg28, 1, %noreg, 0, %noreg; mem:LD8[%strm375] GR64:%vreg27,%vreg28
11648B		%vreg24<def> = MOV32rm %vreg27, 1, %noreg, 36, %noreg; mem:LD4[%total_out_lo32376] GR32:%vreg24 GR64:%vreg27
11680B		%vreg24<def,tied1> = ADD32ri8 %vreg24<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg24
11696B		MOV32mr %vreg27, 1, %noreg, 36, %noreg, %vreg24; mem:ST4[%total_out_lo32376] GR64:%vreg27 GR32:%vreg24
11712B		%vreg20<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg20
11728B		%vreg19<def> = MOV64rm %vreg20, 1, %noreg, 0, %noreg; mem:LD8[%strm378] GR64:%vreg19,%vreg20
11744B		CMP32mi8 %vreg19, 1, %noreg, 36, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%total_out_lo32379] GR64:%vreg19
11760B		JNE_1 <BB#55>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#55 BB#54

11776B	BB#54: derived from LLVM BB %if.then.382
	    Predecessors according to CFG: BB#53
11792B		%vreg95<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg95
11808B		%vreg94<def> = MOV64rm %vreg95, 1, %noreg, 0, %noreg; mem:LD8[%strm383] GR64:%vreg94,%vreg95
11824B		%vreg91<def> = MOV32rm %vreg94, 1, %noreg, 40, %noreg; mem:LD4[%total_out_hi32384] GR32:%vreg91 GR64:%vreg94
11856B		%vreg91<def,tied1> = ADD32ri8 %vreg91<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg91
11872B		MOV32mr %vreg94, 1, %noreg, 40, %noreg, %vreg91; mem:ST4[%total_out_hi32384] GR64:%vreg94 GR32:%vreg91
	    Successors according to CFG: BB#55

11888B	BB#55: derived from LLVM BB %if.end.386
	    Predecessors according to CFG: BB#53 BB#54
11904B		JMP_1 <BB#49>
	    Successors according to CFG: BB#49

11920B	BB#56: derived from LLVM BB %while.end.387
	    Predecessors according to CFG: BB#52
11936B		%vreg105<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg105
11952B		%vreg104<def> = MOV32rm %vreg105, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used388] GR32:%vreg104 GR64:%vreg105
11968B		%vreg102<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg102
11984B		%vreg99<def> = MOV32rm %vreg102, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock389] GR32:%vreg99 GR64:%vreg102
12016B		%vreg99<def,tied1> = ADD32ri8 %vreg99<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg99
12032B		CMP32rr %vreg104, %vreg99, %EFLAGS<imp-def>; GR32:%vreg104,%vreg99
12048B		JNE_1 <BB#58>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#58 BB#57

12064B	BB#57: derived from LLVM BB %if.then.393
	    Predecessors according to CFG: BB#56
12080B		MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST1[%retval]
12096B		JMP_1 <BB#73>
	    Successors according to CFG: BB#73

12112B	BB#58: derived from LLVM BB %if.end.394
	    Predecessors according to CFG: BB#56
12128B		%vreg115<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg115
12144B		%vreg114<def> = MOV32rm %vreg115, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used395] GR32:%vreg114 GR64:%vreg115
12160B		%vreg112<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg112
12176B		%vreg109<def> = MOV32rm %vreg112, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock396] GR32:%vreg109 GR64:%vreg112
12208B		%vreg109<def,tied1> = ADD32ri8 %vreg109<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg109
12224B		CMP32rr %vreg114, %vreg109, %EFLAGS<imp-def>; GR32:%vreg114,%vreg109
12240B		JLE_1 <BB#60>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#60 BB#59

12256B	BB#59: derived from LLVM BB %if.then.400
	    Predecessors according to CFG: BB#58
12272B		MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 1; mem:ST1[%retval]
12288B		JMP_1 <BB#73>
	    Successors according to CFG: BB#73

12304B	BB#60: derived from LLVM BB %if.end.401
	    Predecessors according to CFG: BB#58
12320B		%vreg201<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg201
12336B		MOV32mi %vreg201, 1, %noreg, 16, %noreg, 1; mem:ST4[%state_out_len402] GR64:%vreg201
12352B		%vreg199<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg199
12368B		%vreg198<def> = MOV32rm %vreg199, 1, %noreg, 64, %noreg; mem:LD4[%k0403] GR32:%vreg198 GR64:%vreg199
12400B		%vreg194<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg194
12416B		MOV8mr %vreg194, 1, %noreg, 12, %noreg, %vreg198:sub_8bit; mem:ST1[%state_out_ch405] GR64:%vreg194 GR32:%vreg198
12432B		%vreg191<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg191
12448B		%vreg190<def> = MOV32rm %vreg191, 1, %noreg, 60, %noreg; mem:LD4[%tPos406] GR32:%vreg190 GR64:%vreg191
12464B		%vreg187<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg187
12496B		%vreg187<def,tied1> = ADD64ri32 %vreg187<tied0>, 1096, %EFLAGS<imp-def,dead>; GR64:%vreg187
12512B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
12528B		%EDI<def> = COPY %vreg190; GR32:%vreg190
12544B		%RSI<def> = COPY %vreg187; GR64:%vreg187
12560B		CALL64pcrel32 <ga:@BZ2_indexIntoF>, <regmask>, %RSP<imp-use>, %EDI<imp-use>, %RSI<imp-use,kill>, %EAX<imp-def>
12576B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
12592B		%vreg184<def> = COPY %EAX<kill>; GR32:%vreg184
12608B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
12624B		STACKMAP 6, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
12640B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
12672B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg184:sub_8bit; mem:ST1[%k1] GR32:%vreg184
12688B		%vreg178<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg178
12704B		%vreg176:sub_32bit<def,read-undef> = MOV32rm %vreg178, 1, %noreg, 60, %noreg; mem:LD4[%tPos411] GR64_NOSP:%vreg176 GR64:%vreg178
12736B		%vreg173<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg173
12752B		%vreg172<def> = MOV64rm %vreg173, 1, %noreg, 3160, %noreg; mem:LD8[%ll16413] GR64:%vreg172,%vreg173
12768B		%vreg137<def> = MOVZX32rm16 %vreg172, 2, %vreg176, 0, %noreg; mem:LD2[%arrayidx414] GR32:%vreg137 GR64:%vreg172 GR64_NOSP:%vreg176
12784B		%vreg166<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg166
12800B		%vreg163<def> = MOV32rm %vreg166, 1, %noreg, 60, %noreg; mem:LD4[%tPos416] GR32:%vreg163 GR64:%vreg166
12832B		%vreg163<def,tied1> = SHR32ri %vreg163<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg163
12848B		%vreg161:sub_32bit<def,read-undef> = MOV32rr %vreg163; GR64_NOSP:%vreg161 GR32:%vreg163
12880B		%vreg158<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg158
12896B		%vreg157<def> = MOV64rm %vreg158, 1, %noreg, 3168, %noreg; mem:LD8[%ll4419] GR64:%vreg157,%vreg158
12912B		%vreg141<def> = MOVZX32rm8 %vreg157, 1, %vreg161, 0, %noreg; mem:LD1[%arrayidx420] GR32:%vreg141 GR64:%vreg157 GR64_NOSP:%vreg161
12928B		%vreg151<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg151
12944B		%vreg146<def> = MOV32rm %vreg151, 1, %noreg, 60, %noreg; mem:LD4[%tPos422] GR32:%vreg146 GR64:%vreg151
12976B		%vreg146<def,tied1> = SHL32ri %vreg146<tied0>, 2, %EFLAGS<imp-def,dead>; GR32:%vreg146
13008B		%vreg146<def,tied1> = AND32ri8 %vreg146<tied0>, 4, %EFLAGS<imp-def,dead>; GR32:%vreg146
13024B		%ECX<def> = COPY %vreg146; GR32:%vreg146
13040B		%CL<def> = KILL %ECX<kill>
13072B		%vreg141<def,tied1> = SHR32rCL %vreg141<tied0>, %EFLAGS<imp-def,dead>, %CL<imp-use,kill>; GR32:%vreg141
13104B		%vreg141<def,tied1> = AND32ri8 %vreg141<tied0>, 15, %EFLAGS<imp-def,dead>; GR32:%vreg141
13136B		%vreg141<def,tied1> = SHL32ri %vreg141<tied0>, 16, %EFLAGS<imp-def,dead>; GR32:%vreg141
13168B		%vreg137<def,tied1> = OR32rr %vreg137<tied0>, %vreg141, %EFLAGS<imp-def,dead>; GR32:%vreg137,%vreg141
13184B		%vreg134<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg134
13200B		MOV32mr %vreg134, 1, %noreg, 60, %noreg, %vreg137; mem:ST4[%tPos429] GR64:%vreg134 GR32:%vreg137
13216B		%vreg131<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg131
13232B		%vreg129<def> = MOV32rm %vreg131, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used430] GR32:%vreg129 GR64:%vreg131
13264B		%vreg129<def,tied1> = ADD32ri8 %vreg129<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg129
13280B		MOV32mr %vreg131, 1, %noreg, 1092, %noreg, %vreg129; mem:ST4[%nblock_used430] GR64:%vreg131 GR32:%vreg129
13296B		%vreg125<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg125
13312B		%vreg124<def> = MOV32rm %vreg125, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used432] GR32:%vreg124 GR64:%vreg125
13328B		%vreg122<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg122
13344B		%vreg119<def> = MOV32rm %vreg122, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock433] GR32:%vreg119 GR64:%vreg122
13376B		%vreg119<def,tied1> = ADD32ri8 %vreg119<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg119
13392B		CMP32rr %vreg124, %vreg119, %EFLAGS<imp-def>; GR32:%vreg124,%vreg119
13408B		JNE_1 <BB#62>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#62 BB#61

13424B	BB#61: derived from LLVM BB %if.then.437
	    Predecessors according to CFG: BB#60
13440B		JMP_1 <BB#48>
	    Successors according to CFG: BB#48

13456B	BB#62: derived from LLVM BB %if.end.438
	    Predecessors according to CFG: BB#60
13472B		%vreg207<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg207
13488B		%vreg205<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg205
13504B		CMP32rm %vreg207, %vreg205, 1, %noreg, 64, %noreg, %EFLAGS<imp-def>; mem:LD4[%k0440] GR32:%vreg207 GR64:%vreg205
13520B		JE_1 <BB#64>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#64 BB#63

13536B	BB#63: derived from LLVM BB %if.then.443
	    Predecessors according to CFG: BB#62
13552B		%vreg529<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg529
13568B		%vreg527<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg527
13584B		MOV32mr %vreg527, 1, %noreg, 64, %noreg, %vreg529; mem:ST4[%k0445] GR64:%vreg527 GR32:%vreg529
13600B		JMP_1 <BB#48>
	    Successors according to CFG: BB#48

13616B	BB#64: derived from LLVM BB %if.end.446
	    Predecessors according to CFG: BB#62
13632B		%vreg285<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg285
13648B		MOV32mi %vreg285, 1, %noreg, 16, %noreg, 2; mem:ST4[%state_out_len447] GR64:%vreg285
13664B		%vreg283<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg283
13680B		%vreg282<def> = MOV32rm %vreg283, 1, %noreg, 60, %noreg; mem:LD4[%tPos448] GR32:%vreg282 GR64:%vreg283
13696B		%vreg279<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg279
13728B		%vreg279<def,tied1> = ADD64ri32 %vreg279<tied0>, 1096, %EFLAGS<imp-def,dead>; GR64:%vreg279
13744B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
13760B		%EDI<def> = COPY %vreg282; GR32:%vreg282
13776B		%RSI<def> = COPY %vreg279; GR64:%vreg279
13792B		CALL64pcrel32 <ga:@BZ2_indexIntoF>, <regmask>, %RSP<imp-use>, %EDI<imp-use>, %RSI<imp-use,kill>, %EAX<imp-def>
13808B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
13824B		%vreg276<def> = COPY %EAX<kill>; GR32:%vreg276
13840B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
13856B		STACKMAP 7, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
13872B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
13904B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg276:sub_8bit; mem:ST1[%k1] GR32:%vreg276
13920B		%vreg270<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg270
13936B		%vreg268:sub_32bit<def,read-undef> = MOV32rm %vreg270, 1, %noreg, 60, %noreg; mem:LD4[%tPos453] GR64_NOSP:%vreg268 GR64:%vreg270
13968B		%vreg265<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg265
13984B		%vreg264<def> = MOV64rm %vreg265, 1, %noreg, 3160, %noreg; mem:LD8[%ll16455] GR64:%vreg264,%vreg265
14000B		%vreg229<def> = MOVZX32rm16 %vreg264, 2, %vreg268, 0, %noreg; mem:LD2[%arrayidx456] GR32:%vreg229 GR64:%vreg264 GR64_NOSP:%vreg268
14016B		%vreg258<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg258
14032B		%vreg255<def> = MOV32rm %vreg258, 1, %noreg, 60, %noreg; mem:LD4[%tPos458] GR32:%vreg255 GR64:%vreg258
14064B		%vreg255<def,tied1> = SHR32ri %vreg255<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg255
14080B		%vreg253:sub_32bit<def,read-undef> = MOV32rr %vreg255; GR64_NOSP:%vreg253 GR32:%vreg255
14112B		%vreg250<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg250
14128B		%vreg249<def> = MOV64rm %vreg250, 1, %noreg, 3168, %noreg; mem:LD8[%ll4461] GR64:%vreg249,%vreg250
14144B		%vreg233<def> = MOVZX32rm8 %vreg249, 1, %vreg253, 0, %noreg; mem:LD1[%arrayidx462] GR32:%vreg233 GR64:%vreg249 GR64_NOSP:%vreg253
14160B		%vreg243<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg243
14176B		%vreg238<def> = MOV32rm %vreg243, 1, %noreg, 60, %noreg; mem:LD4[%tPos464] GR32:%vreg238 GR64:%vreg243
14208B		%vreg238<def,tied1> = SHL32ri %vreg238<tied0>, 2, %EFLAGS<imp-def,dead>; GR32:%vreg238
14240B		%vreg238<def,tied1> = AND32ri8 %vreg238<tied0>, 4, %EFLAGS<imp-def,dead>; GR32:%vreg238
14256B		%ECX<def> = COPY %vreg238; GR32:%vreg238
14272B		%CL<def> = KILL %ECX<kill>
14304B		%vreg233<def,tied1> = SHR32rCL %vreg233<tied0>, %EFLAGS<imp-def,dead>, %CL<imp-use,kill>; GR32:%vreg233
14336B		%vreg233<def,tied1> = AND32ri8 %vreg233<tied0>, 15, %EFLAGS<imp-def,dead>; GR32:%vreg233
14368B		%vreg233<def,tied1> = SHL32ri %vreg233<tied0>, 16, %EFLAGS<imp-def,dead>; GR32:%vreg233
14400B		%vreg229<def,tied1> = OR32rr %vreg229<tied0>, %vreg233, %EFLAGS<imp-def,dead>; GR32:%vreg229,%vreg233
14416B		%vreg226<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg226
14432B		MOV32mr %vreg226, 1, %noreg, 60, %noreg, %vreg229; mem:ST4[%tPos471] GR64:%vreg226 GR32:%vreg229
14448B		%vreg223<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg223
14464B		%vreg221<def> = MOV32rm %vreg223, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used472] GR32:%vreg221 GR64:%vreg223
14496B		%vreg221<def,tied1> = ADD32ri8 %vreg221<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg221
14512B		MOV32mr %vreg223, 1, %noreg, 1092, %noreg, %vreg221; mem:ST4[%nblock_used472] GR64:%vreg223 GR32:%vreg221
14528B		%vreg217<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg217
14544B		%vreg216<def> = MOV32rm %vreg217, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used474] GR32:%vreg216 GR64:%vreg217
14560B		%vreg214<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg214
14576B		%vreg211<def> = MOV32rm %vreg214, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock475] GR32:%vreg211 GR64:%vreg214
14608B		%vreg211<def,tied1> = ADD32ri8 %vreg211<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg211
14624B		CMP32rr %vreg216, %vreg211, %EFLAGS<imp-def>; GR32:%vreg216,%vreg211
14640B		JNE_1 <BB#66>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#66 BB#65

14656B	BB#65: derived from LLVM BB %if.then.479
	    Predecessors according to CFG: BB#64
14672B		JMP_1 <BB#48>
	    Successors according to CFG: BB#48

14688B	BB#66: derived from LLVM BB %if.end.480
	    Predecessors according to CFG: BB#64
14704B		%vreg291<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg291
14720B		%vreg289<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg289
14736B		CMP32rm %vreg291, %vreg289, 1, %noreg, 64, %noreg, %EFLAGS<imp-def>; mem:LD4[%k0482] GR32:%vreg291 GR64:%vreg289
14752B		JE_1 <BB#68>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#68 BB#67

14768B	BB#67: derived from LLVM BB %if.then.485
	    Predecessors according to CFG: BB#66
14784B		%vreg524<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg524
14800B		%vreg522<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg522
14816B		MOV32mr %vreg522, 1, %noreg, 64, %noreg, %vreg524; mem:ST4[%k0487] GR64:%vreg522 GR32:%vreg524
14832B		JMP_1 <BB#48>
	    Successors according to CFG: BB#48

14848B	BB#68: derived from LLVM BB %if.end.488
	    Predecessors according to CFG: BB#66
14864B		%vreg369<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg369
14880B		MOV32mi %vreg369, 1, %noreg, 16, %noreg, 3; mem:ST4[%state_out_len489] GR64:%vreg369
14896B		%vreg367<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg367
14912B		%vreg366<def> = MOV32rm %vreg367, 1, %noreg, 60, %noreg; mem:LD4[%tPos490] GR32:%vreg366 GR64:%vreg367
14928B		%vreg363<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg363
14960B		%vreg363<def,tied1> = ADD64ri32 %vreg363<tied0>, 1096, %EFLAGS<imp-def,dead>; GR64:%vreg363
14976B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
14992B		%EDI<def> = COPY %vreg366; GR32:%vreg366
15008B		%RSI<def> = COPY %vreg363; GR64:%vreg363
15024B		CALL64pcrel32 <ga:@BZ2_indexIntoF>, <regmask>, %RSP<imp-use>, %EDI<imp-use>, %RSI<imp-use,kill>, %EAX<imp-def>
15040B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
15056B		%vreg360<def> = COPY %EAX<kill>; GR32:%vreg360
15072B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
15088B		STACKMAP 8, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
15104B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
15136B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg360:sub_8bit; mem:ST1[%k1] GR32:%vreg360
15152B		%vreg354<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg354
15168B		%vreg352:sub_32bit<def,read-undef> = MOV32rm %vreg354, 1, %noreg, 60, %noreg; mem:LD4[%tPos495] GR64_NOSP:%vreg352 GR64:%vreg354
15200B		%vreg349<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg349
15216B		%vreg348<def> = MOV64rm %vreg349, 1, %noreg, 3160, %noreg; mem:LD8[%ll16497] GR64:%vreg348,%vreg349
15232B		%vreg313<def> = MOVZX32rm16 %vreg348, 2, %vreg352, 0, %noreg; mem:LD2[%arrayidx498] GR32:%vreg313 GR64:%vreg348 GR64_NOSP:%vreg352
15248B		%vreg342<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg342
15264B		%vreg339<def> = MOV32rm %vreg342, 1, %noreg, 60, %noreg; mem:LD4[%tPos500] GR32:%vreg339 GR64:%vreg342
15296B		%vreg339<def,tied1> = SHR32ri %vreg339<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg339
15312B		%vreg337:sub_32bit<def,read-undef> = MOV32rr %vreg339; GR64_NOSP:%vreg337 GR32:%vreg339
15344B		%vreg334<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg334
15360B		%vreg333<def> = MOV64rm %vreg334, 1, %noreg, 3168, %noreg; mem:LD8[%ll4503] GR64:%vreg333,%vreg334
15376B		%vreg317<def> = MOVZX32rm8 %vreg333, 1, %vreg337, 0, %noreg; mem:LD1[%arrayidx504] GR32:%vreg317 GR64:%vreg333 GR64_NOSP:%vreg337
15392B		%vreg327<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg327
15408B		%vreg322<def> = MOV32rm %vreg327, 1, %noreg, 60, %noreg; mem:LD4[%tPos506] GR32:%vreg322 GR64:%vreg327
15440B		%vreg322<def,tied1> = SHL32ri %vreg322<tied0>, 2, %EFLAGS<imp-def,dead>; GR32:%vreg322
15472B		%vreg322<def,tied1> = AND32ri8 %vreg322<tied0>, 4, %EFLAGS<imp-def,dead>; GR32:%vreg322
15488B		%ECX<def> = COPY %vreg322; GR32:%vreg322
15504B		%CL<def> = KILL %ECX<kill>
15536B		%vreg317<def,tied1> = SHR32rCL %vreg317<tied0>, %EFLAGS<imp-def,dead>, %CL<imp-use,kill>; GR32:%vreg317
15568B		%vreg317<def,tied1> = AND32ri8 %vreg317<tied0>, 15, %EFLAGS<imp-def,dead>; GR32:%vreg317
15600B		%vreg317<def,tied1> = SHL32ri %vreg317<tied0>, 16, %EFLAGS<imp-def,dead>; GR32:%vreg317
15632B		%vreg313<def,tied1> = OR32rr %vreg313<tied0>, %vreg317, %EFLAGS<imp-def,dead>; GR32:%vreg313,%vreg317
15648B		%vreg310<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg310
15664B		MOV32mr %vreg310, 1, %noreg, 60, %noreg, %vreg313; mem:ST4[%tPos513] GR64:%vreg310 GR32:%vreg313
15680B		%vreg307<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg307
15696B		%vreg305<def> = MOV32rm %vreg307, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used514] GR32:%vreg305 GR64:%vreg307
15728B		%vreg305<def,tied1> = ADD32ri8 %vreg305<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg305
15744B		MOV32mr %vreg307, 1, %noreg, 1092, %noreg, %vreg305; mem:ST4[%nblock_used514] GR64:%vreg307 GR32:%vreg305
15760B		%vreg301<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg301
15776B		%vreg300<def> = MOV32rm %vreg301, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used516] GR32:%vreg300 GR64:%vreg301
15792B		%vreg298<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg298
15808B		%vreg295<def> = MOV32rm %vreg298, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock517] GR32:%vreg295 GR64:%vreg298
15840B		%vreg295<def,tied1> = ADD32ri8 %vreg295<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg295
15856B		CMP32rr %vreg300, %vreg295, %EFLAGS<imp-def>; GR32:%vreg300,%vreg295
15872B		JNE_1 <BB#70>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#70 BB#69

15888B	BB#69: derived from LLVM BB %if.then.521
	    Predecessors according to CFG: BB#68
15904B		JMP_1 <BB#48>
	    Successors according to CFG: BB#48

15920B	BB#70: derived from LLVM BB %if.end.522
	    Predecessors according to CFG: BB#68
15936B		%vreg375<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg375
15952B		%vreg373<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg373
15968B		CMP32rm %vreg375, %vreg373, 1, %noreg, 64, %noreg, %EFLAGS<imp-def>; mem:LD4[%k0524] GR32:%vreg375 GR64:%vreg373
15984B		JE_1 <BB#72>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#72 BB#71

16000B	BB#71: derived from LLVM BB %if.then.527
	    Predecessors according to CFG: BB#70
16016B		%vreg519<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg519
16032B		%vreg517<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg517
16048B		MOV32mr %vreg517, 1, %noreg, 64, %noreg, %vreg519; mem:ST4[%k0529] GR64:%vreg517 GR32:%vreg519
16064B		JMP_1 <BB#48>
	    Successors according to CFG: BB#48

16080B	BB#72: derived from LLVM BB %if.end.530
	    Predecessors according to CFG: BB#70
16096B		%vreg514<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg514
16112B		%vreg513<def> = MOV32rm %vreg514, 1, %noreg, 60, %noreg; mem:LD4[%tPos531] GR32:%vreg513 GR64:%vreg514
16128B		%vreg510<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg510
16160B		%vreg510<def,tied1> = ADD64ri32 %vreg510<tied0>, 1096, %EFLAGS<imp-def,dead>; GR64:%vreg510
16176B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
16192B		%EDI<def> = COPY %vreg513; GR32:%vreg513
16208B		%RSI<def> = COPY %vreg510; GR64:%vreg510
16224B		CALL64pcrel32 <ga:@BZ2_indexIntoF>, <regmask>, %RSP<imp-use>, %EDI<imp-use>, %RSI<imp-use,kill>, %EAX<imp-def>
16240B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
16256B		%vreg507<def> = COPY %EAX<kill>; GR32:%vreg507
16272B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
16288B		STACKMAP 9, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
16304B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
16336B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg507:sub_8bit; mem:ST1[%k1] GR32:%vreg507
16352B		%vreg501<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg501
16368B		%vreg499:sub_32bit<def,read-undef> = MOV32rm %vreg501, 1, %noreg, 60, %noreg; mem:LD4[%tPos536] GR64_NOSP:%vreg499 GR64:%vreg501
16400B		%vreg496<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg496
16416B		%vreg495<def> = MOV64rm %vreg496, 1, %noreg, 3160, %noreg; mem:LD8[%ll16538] GR64:%vreg495,%vreg496
16432B		%vreg460<def> = MOVZX32rm16 %vreg495, 2, %vreg499, 0, %noreg; mem:LD2[%arrayidx539] GR32:%vreg460 GR64:%vreg495 GR64_NOSP:%vreg499
16448B		%vreg489<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg489
16464B		%vreg486<def> = MOV32rm %vreg489, 1, %noreg, 60, %noreg; mem:LD4[%tPos541] GR32:%vreg486 GR64:%vreg489
16496B		%vreg486<def,tied1> = SHR32ri %vreg486<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg486
16512B		%vreg484:sub_32bit<def,read-undef> = MOV32rr %vreg486; GR64_NOSP:%vreg484 GR32:%vreg486
16544B		%vreg481<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg481
16560B		%vreg480<def> = MOV64rm %vreg481, 1, %noreg, 3168, %noreg; mem:LD8[%ll4544] GR64:%vreg480,%vreg481
16576B		%vreg464<def> = MOVZX32rm8 %vreg480, 1, %vreg484, 0, %noreg; mem:LD1[%arrayidx545] GR32:%vreg464 GR64:%vreg480 GR64_NOSP:%vreg484
16592B		%vreg474<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg474
16608B		%vreg469<def> = MOV32rm %vreg474, 1, %noreg, 60, %noreg; mem:LD4[%tPos547] GR32:%vreg469 GR64:%vreg474
16640B		%vreg469<def,tied1> = SHL32ri %vreg469<tied0>, 2, %EFLAGS<imp-def,dead>; GR32:%vreg469
16672B		%vreg469<def,tied1> = AND32ri8 %vreg469<tied0>, 4, %EFLAGS<imp-def,dead>; GR32:%vreg469
16688B		%ECX<def> = COPY %vreg469; GR32:%vreg469
16704B		%CL<def> = KILL %ECX<kill>
16736B		%vreg464<def,tied1> = SHR32rCL %vreg464<tied0>, %EFLAGS<imp-def,dead>, %CL<imp-use,kill>; GR32:%vreg464
16768B		%vreg464<def,tied1> = AND32ri8 %vreg464<tied0>, 15, %EFLAGS<imp-def,dead>; GR32:%vreg464
16800B		%vreg464<def,tied1> = SHL32ri %vreg464<tied0>, 16, %EFLAGS<imp-def,dead>; GR32:%vreg464
16832B		%vreg460<def,tied1> = OR32rr %vreg460<tied0>, %vreg464, %EFLAGS<imp-def,dead>; GR32:%vreg460,%vreg464
16848B		%vreg457<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg457
16864B		MOV32mr %vreg457, 1, %noreg, 60, %noreg, %vreg460; mem:ST4[%tPos554] GR64:%vreg457 GR32:%vreg460
16880B		%vreg454<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg454
16896B		%vreg452<def> = MOV32rm %vreg454, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used555] GR32:%vreg452 GR64:%vreg454
16928B		%vreg452<def,tied1> = ADD32ri8 %vreg452<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg452
16944B		MOV32mr %vreg454, 1, %noreg, 1092, %noreg, %vreg452; mem:ST4[%nblock_used555] GR64:%vreg454 GR32:%vreg452
16960B		%vreg446<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg446
16992B		%vreg446<def,tied1> = ADD32ri8 %vreg446<tied0>, 4, %EFLAGS<imp-def,dead>; GR32:%vreg446
17008B		%vreg444<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg444
17024B		MOV32mr %vreg444, 1, %noreg, 16, %noreg, %vreg446; mem:ST4[%state_out_len559] GR64:%vreg444 GR32:%vreg446
17040B		%vreg441<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg441
17056B		%vreg440<def> = MOV32rm %vreg441, 1, %noreg, 60, %noreg; mem:LD4[%tPos560] GR32:%vreg440 GR64:%vreg441
17072B		%vreg437<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg437
17104B		%vreg437<def,tied1> = ADD64ri32 %vreg437<tied0>, 1096, %EFLAGS<imp-def,dead>; GR64:%vreg437
17120B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
17136B		%EDI<def> = COPY %vreg440; GR32:%vreg440
17152B		%RSI<def> = COPY %vreg437; GR64:%vreg437
17168B		CALL64pcrel32 <ga:@BZ2_indexIntoF>, <regmask>, %RSP<imp-use>, %EDI<imp-use>, %RSI<imp-use,kill>, %EAX<imp-def>
17184B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
17200B		%vreg434<def> = COPY %EAX<kill>; GR32:%vreg434
17216B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
17232B		STACKMAP 10, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
17248B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
17264B		%vreg431<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg431
17280B		MOV32mr %vreg431, 1, %noreg, 64, %noreg, %vreg434; mem:ST4[%k0564] GR64:%vreg431 GR32:%vreg434
17296B		%vreg428<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg428
17312B		%vreg426:sub_32bit<def,read-undef> = MOV32rm %vreg428, 1, %noreg, 60, %noreg; mem:LD4[%tPos565] GR64_NOSP:%vreg426 GR64:%vreg428
17344B		%vreg423<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg423
17360B		%vreg422<def> = MOV64rm %vreg423, 1, %noreg, 3160, %noreg; mem:LD8[%ll16567] GR64:%vreg422,%vreg423
17376B		%vreg387<def> = MOVZX32rm16 %vreg422, 2, %vreg426, 0, %noreg; mem:LD2[%arrayidx568] GR32:%vreg387 GR64:%vreg422 GR64_NOSP:%vreg426
17392B		%vreg416<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg416
17408B		%vreg413<def> = MOV32rm %vreg416, 1, %noreg, 60, %noreg; mem:LD4[%tPos570] GR32:%vreg413 GR64:%vreg416
17440B		%vreg413<def,tied1> = SHR32ri %vreg413<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg413
17456B		%vreg411:sub_32bit<def,read-undef> = MOV32rr %vreg413; GR64_NOSP:%vreg411 GR32:%vreg413
17488B		%vreg408<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg408
17504B		%vreg407<def> = MOV64rm %vreg408, 1, %noreg, 3168, %noreg; mem:LD8[%ll4573] GR64:%vreg407,%vreg408
17520B		%vreg391<def> = MOVZX32rm8 %vreg407, 1, %vreg411, 0, %noreg; mem:LD1[%arrayidx574] GR32:%vreg391 GR64:%vreg407 GR64_NOSP:%vreg411
17536B		%vreg401<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg401
17552B		%vreg396<def> = MOV32rm %vreg401, 1, %noreg, 60, %noreg; mem:LD4[%tPos576] GR32:%vreg396 GR64:%vreg401
17584B		%vreg396<def,tied1> = SHL32ri %vreg396<tied0>, 2, %EFLAGS<imp-def,dead>; GR32:%vreg396
17616B		%vreg396<def,tied1> = AND32ri8 %vreg396<tied0>, 4, %EFLAGS<imp-def,dead>; GR32:%vreg396
17632B		%ECX<def> = COPY %vreg396; GR32:%vreg396
17648B		%CL<def> = KILL %ECX<kill>
17680B		%vreg391<def,tied1> = SHR32rCL %vreg391<tied0>, %EFLAGS<imp-def,dead>, %CL<imp-use,kill>; GR32:%vreg391
17712B		%vreg391<def,tied1> = AND32ri8 %vreg391<tied0>, 15, %EFLAGS<imp-def,dead>; GR32:%vreg391
17744B		%vreg391<def,tied1> = SHL32ri %vreg391<tied0>, 16, %EFLAGS<imp-def,dead>; GR32:%vreg391
17776B		%vreg387<def,tied1> = OR32rr %vreg387<tied0>, %vreg391, %EFLAGS<imp-def,dead>; GR32:%vreg387,%vreg391
17792B		%vreg384<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg384
17808B		MOV32mr %vreg384, 1, %noreg, 60, %noreg, %vreg387; mem:ST4[%tPos583] GR64:%vreg384 GR32:%vreg387
17824B		%vreg381<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg381
17840B		%vreg379<def> = MOV32rm %vreg381, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used584] GR32:%vreg379 GR64:%vreg381
17872B		%vreg379<def,tied1> = ADD32ri8 %vreg379<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg379
17888B		MOV32mr %vreg381, 1, %noreg, 1092, %noreg, %vreg379; mem:ST4[%nblock_used584] GR64:%vreg381 GR32:%vreg379
17904B		JMP_1 <BB#48>
	    Successors according to CFG: BB#48

17920B	BB#73: derived from LLVM BB %return
	    Predecessors according to CFG: BB#59 BB#57 BB#50 BB#13 BB#11 BB#4
17936B		%vreg1268<def> = MOV64ri <ga:@unRLE_obuf_to_output_SMALL>; GR64:%vreg1268
17968B		%vreg1269<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg1269
17984B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
18000B		%RDI<def> = COPY %vreg1268; GR64:%vreg1268
18016B		%RSI<def> = COPY %vreg1269; GR64:%vreg1269
18032B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
18048B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
18064B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
18080B		STACKMAP 11, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=1)
18096B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
18112B		%vreg1266<def> = MOV8rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD1[%retval] GR8:%vreg1266
18128B		%AL<def> = COPY %vreg1266; GR8:%vreg1266
18144B		RETQ %AL<imp-use,kill>

# End machine code for function unRLE_obuf_to_output_SMALL.

AllocationOrder(SEGMENT_REG) = [ ]
AllocationOrder(SEGMENT_REG) = [ ]
AllocationOrder(SEGMENT_REG) = [ ]
AllocationOrder(SEGMENT_REG) = [ ]
AllocationOrder(SEGMENT_REG) = [ ]
AllocationOrder(SEGMENT_REG) = [ ]
AllocationOrder(SEGMENT_REG) = [ ]
AllocationOrder(SEGMENT_REG) = [ ]
AllocationOrder(SEGMENT_REG) = [ ]
AllocationOrder(SEGMENT_REG) = [ ]
AllocationOrder(SEGMENT_REG) = [ ]
AllocationOrder(SEGMENT_REG) = [ ]
AllocationOrder(SEGMENT_REG) = [ ]
AllocationOrder(SEGMENT_REG) = [ ]
AllocationOrder(SEGMENT_REG) = [ ]
AllocationOrder(SEGMENT_REG) = [ ]
AllocationOrder(SEGMENT_REG) = [ ]
AllocationOrder(SEGMENT_REG) = [ ]
AllocationOrder(SEGMENT_REG) = [ ]
AllocationOrder(SEGMENT_REG) = [ ]
AllocationOrder(SEGMENT_REG) = [ ]
AllocationOrder(SEGMENT_REG) = [ ]
AllocationOrder(SEGMENT_REG) = [ ]
AllocationOrder(SEGMENT_REG) = [ ]
********** GREEDY REGISTER ALLOCATION **********
********** Function: unRLE_obuf_to_output_SMALL
********** INTERVALS **********
DIL [0B,16r:0)[112r,144r:12)[2160r,2192r:5)[4016r,4048r:4)[5872r,5904r:3)[7696r,7728r:2)[9264r,9296r:1)[12528r,12560r:10)[13760r,13792r:9)[14992r,15024r:8)[16192r,16224r:6)[17136r,17168r:7)[18000r,18032r:11)  0@0B-phi 1@9264r 2@7696r 3@5872r 4@4016r 5@2160r 6@16192r 7@17136r 8@14992r 9@13760r 10@12528r 11@18000r 12@112r
%vreg1 [16r,224r:0)  0@16r
%vreg4 [240r,256r:0)  0@240r
%vreg6 [48r,112r:0)  0@48r
%vreg7 [80r,128r:0)  0@80r
%vreg11 [10752r,10768r:0)  0@10752r
%vreg12 [10736r,10752r:0)  0@10736r
%vreg15 [10864r,10880r:0)  0@10864r
%vreg19 [11728r,11744r:0)  0@11728r
%vreg20 [11712r,11728r:0)  0@11712r
%vreg24 [11648r,11680r:0)[11680r,11696r:1)  0@11648r 1@11680r
%vreg27 [11632r,11696r:0)  0@11632r
%vreg28 [11616r,11632r:0)  0@11616r
%vreg32 [11552r,11584r:0)[11584r,11600r:1)  0@11552r 1@11584r
%vreg35 [11536r,11600r:0)  0@11536r
%vreg36 [11520r,11536r:0)  0@11520r
%vreg40 [11456r,11488r:0)[11488r,11504r:1)  0@11456r 1@11488r
%vreg43 [11440r,11504r:0)  0@11440r
%vreg44 [11424r,11440r:0)  0@11424r
%vreg48 [11360r,11392r:0)[11392r,11408r:1)  0@11360r 1@11392r
%vreg50 [11344r,11408r:0)  0@11344r
%vreg53 [11312r,11328r:0)  0@11312r
%vreg56 [11072r,11104r:2)[11104r,11296r:0)[11296r,11328r:1)  0@11104r 1@11296r 2@11072r
%vreg60 [11248r,11296r:0)  0@11248r
%vreg63 [11136r,11168r:2)[11168r,11232r:0)[11232r,11248r:1)  0@11168r 1@11232r 2@11136r
%vreg65 [11200r,11232r:0)  0@11200r
%vreg67 [11184r,11200r:0)  0@11184r
%vreg72 [11120r,11136r:0)  0@11120r
%vreg77 [11056r,11072r:0)  0@11056r
%vreg81 [11024r,11040r:0)  0@11024r
%vreg83 [11008r,11024r:0)  0@11008r
%vreg84 [10992r,11008r:0)  0@10992r
%vreg86 [10976r,11040r:0)  0@10976r
%vreg87 [10960r,10976r:0)  0@10960r
%vreg91 [11824r,11856r:0)[11856r,11872r:1)  0@11824r 1@11856r
%vreg94 [11808r,11872r:0)  0@11808r
%vreg95 [11792r,11808r:0)  0@11792r
%vreg99 [11984r,12016r:0)[12016r,12032r:1)  0@11984r 1@12016r
%vreg102 [11968r,11984r:0)  0@11968r
%vreg104 [11952r,12032r:0)  0@11952r
%vreg105 [11936r,11952r:0)  0@11936r
%vreg109 [12176r,12208r:0)[12208r,12224r:1)  0@12176r 1@12208r
%vreg112 [12160r,12176r:0)  0@12160r
%vreg114 [12144r,12224r:0)  0@12144r
%vreg115 [12128r,12144r:0)  0@12128r
%vreg119 [13344r,13376r:0)[13376r,13392r:1)  0@13344r 1@13376r
%vreg122 [13328r,13344r:0)  0@13328r
%vreg124 [13312r,13392r:0)  0@13312r
%vreg125 [13296r,13312r:0)  0@13296r
%vreg129 [13232r,13264r:0)[13264r,13280r:1)  0@13232r 1@13264r
%vreg131 [13216r,13280r:0)  0@13216r
%vreg134 [13184r,13200r:0)  0@13184r
%vreg137 [12768r,13168r:0)[13168r,13200r:1)  0@12768r 1@13168r
%vreg141 [12912r,13072r:2)[13072r,13104r:0)[13104r,13136r:1)[13136r,13168r:3)  0@13072r 1@13104r 2@12912r 3@13136r
%vreg146 [12944r,12976r:2)[12976r,13008r:0)[13008r,13024r:1)  0@12976r 1@13008r 2@12944r
%vreg151 [12928r,12944r:0)  0@12928r
%vreg157 [12896r,12912r:0)  0@12896r
%vreg158 [12880r,12896r:0)  0@12880r
%vreg161 [12848r,12912r:0)  0@12848r
%vreg163 [12800r,12832r:0)[12832r,12848r:1)  0@12800r 1@12832r
%vreg166 [12784r,12800r:0)  0@12784r
%vreg172 [12752r,12768r:0)  0@12752r
%vreg173 [12736r,12752r:0)  0@12736r
%vreg176 [12704r,12768r:0)  0@12704r
%vreg178 [12688r,12704r:0)  0@12688r
%vreg184 [12592r,12672r:0)  0@12592r
%vreg187 [12464r,12496r:0)[12496r,12544r:1)  0@12464r 1@12496r
%vreg190 [12448r,12528r:0)  0@12448r
%vreg191 [12432r,12448r:0)  0@12432r
%vreg194 [12400r,12416r:0)  0@12400r
%vreg198 [12368r,12416r:0)  0@12368r
%vreg199 [12352r,12368r:0)  0@12352r
%vreg201 [12320r,12336r:0)  0@12320r
%vreg205 [13488r,13504r:0)  0@13488r
%vreg207 [13472r,13504r:0)  0@13472r
%vreg211 [14576r,14608r:0)[14608r,14624r:1)  0@14576r 1@14608r
%vreg214 [14560r,14576r:0)  0@14560r
%vreg216 [14544r,14624r:0)  0@14544r
%vreg217 [14528r,14544r:0)  0@14528r
%vreg221 [14464r,14496r:0)[14496r,14512r:1)  0@14464r 1@14496r
%vreg223 [14448r,14512r:0)  0@14448r
%vreg226 [14416r,14432r:0)  0@14416r
%vreg229 [14000r,14400r:0)[14400r,14432r:1)  0@14000r 1@14400r
%vreg233 [14144r,14304r:2)[14304r,14336r:0)[14336r,14368r:1)[14368r,14400r:3)  0@14304r 1@14336r 2@14144r 3@14368r
%vreg238 [14176r,14208r:2)[14208r,14240r:0)[14240r,14256r:1)  0@14208r 1@14240r 2@14176r
%vreg243 [14160r,14176r:0)  0@14160r
%vreg249 [14128r,14144r:0)  0@14128r
%vreg250 [14112r,14128r:0)  0@14112r
%vreg253 [14080r,14144r:0)  0@14080r
%vreg255 [14032r,14064r:0)[14064r,14080r:1)  0@14032r 1@14064r
%vreg258 [14016r,14032r:0)  0@14016r
%vreg264 [13984r,14000r:0)  0@13984r
%vreg265 [13968r,13984r:0)  0@13968r
%vreg268 [13936r,14000r:0)  0@13936r
%vreg270 [13920r,13936r:0)  0@13920r
%vreg276 [13824r,13904r:0)  0@13824r
%vreg279 [13696r,13728r:0)[13728r,13776r:1)  0@13696r 1@13728r
%vreg282 [13680r,13760r:0)  0@13680r
%vreg283 [13664r,13680r:0)  0@13664r
%vreg285 [13632r,13648r:0)  0@13632r
%vreg289 [14720r,14736r:0)  0@14720r
%vreg291 [14704r,14736r:0)  0@14704r
%vreg295 [15808r,15840r:0)[15840r,15856r:1)  0@15808r 1@15840r
%vreg298 [15792r,15808r:0)  0@15792r
%vreg300 [15776r,15856r:0)  0@15776r
%vreg301 [15760r,15776r:0)  0@15760r
%vreg305 [15696r,15728r:0)[15728r,15744r:1)  0@15696r 1@15728r
%vreg307 [15680r,15744r:0)  0@15680r
%vreg310 [15648r,15664r:0)  0@15648r
%vreg313 [15232r,15632r:0)[15632r,15664r:1)  0@15232r 1@15632r
%vreg317 [15376r,15536r:2)[15536r,15568r:0)[15568r,15600r:1)[15600r,15632r:3)  0@15536r 1@15568r 2@15376r 3@15600r
%vreg322 [15408r,15440r:2)[15440r,15472r:0)[15472r,15488r:1)  0@15440r 1@15472r 2@15408r
%vreg327 [15392r,15408r:0)  0@15392r
%vreg333 [15360r,15376r:0)  0@15360r
%vreg334 [15344r,15360r:0)  0@15344r
%vreg337 [15312r,15376r:0)  0@15312r
%vreg339 [15264r,15296r:0)[15296r,15312r:1)  0@15264r 1@15296r
%vreg342 [15248r,15264r:0)  0@15248r
%vreg348 [15216r,15232r:0)  0@15216r
%vreg349 [15200r,15216r:0)  0@15200r
%vreg352 [15168r,15232r:0)  0@15168r
%vreg354 [15152r,15168r:0)  0@15152r
%vreg360 [15056r,15136r:0)  0@15056r
%vreg363 [14928r,14960r:0)[14960r,15008r:1)  0@14928r 1@14960r
%vreg366 [14912r,14992r:0)  0@14912r
%vreg367 [14896r,14912r:0)  0@14896r
%vreg369 [14864r,14880r:0)  0@14864r
%vreg373 [15952r,15968r:0)  0@15952r
%vreg375 [15936r,15968r:0)  0@15936r
%vreg379 [17840r,17872r:0)[17872r,17888r:1)  0@17840r 1@17872r
%vreg381 [17824r,17888r:0)  0@17824r
%vreg384 [17792r,17808r:0)  0@17792r
%vreg387 [17376r,17776r:0)[17776r,17808r:1)  0@17376r 1@17776r
%vreg391 [17520r,17680r:2)[17680r,17712r:0)[17712r,17744r:1)[17744r,17776r:3)  0@17680r 1@17712r 2@17520r 3@17744r
%vreg396 [17552r,17584r:2)[17584r,17616r:0)[17616r,17632r:1)  0@17584r 1@17616r 2@17552r
%vreg401 [17536r,17552r:0)  0@17536r
%vreg407 [17504r,17520r:0)  0@17504r
%vreg408 [17488r,17504r:0)  0@17488r
%vreg411 [17456r,17520r:0)  0@17456r
%vreg413 [17408r,17440r:0)[17440r,17456r:1)  0@17408r 1@17440r
%vreg416 [17392r,17408r:0)  0@17392r
%vreg422 [17360r,17376r:0)  0@17360r
%vreg423 [17344r,17360r:0)  0@17344r
%vreg426 [17312r,17376r:0)  0@17312r
%vreg428 [17296r,17312r:0)  0@17296r
%vreg431 [17264r,17280r:0)  0@17264r
%vreg434 [17200r,17280r:0)  0@17200r
%vreg437 [17072r,17104r:0)[17104r,17152r:1)  0@17072r 1@17104r
%vreg440 [17056r,17136r:0)  0@17056r
%vreg441 [17040r,17056r:0)  0@17040r
%vreg444 [17008r,17024r:0)  0@17008r
%vreg446 [16960r,16992r:0)[16992r,17024r:1)  0@16960r 1@16992r
%vreg452 [16896r,16928r:0)[16928r,16944r:1)  0@16896r 1@16928r
%vreg454 [16880r,16944r:0)  0@16880r
%vreg457 [16848r,16864r:0)  0@16848r
%vreg460 [16432r,16832r:0)[16832r,16864r:1)  0@16432r 1@16832r
%vreg464 [16576r,16736r:2)[16736r,16768r:0)[16768r,16800r:1)[16800r,16832r:3)  0@16736r 1@16768r 2@16576r 3@16800r
%vreg469 [16608r,16640r:2)[16640r,16672r:0)[16672r,16688r:1)  0@16640r 1@16672r 2@16608r
%vreg474 [16592r,16608r:0)  0@16592r
%vreg480 [16560r,16576r:0)  0@16560r
%vreg481 [16544r,16560r:0)  0@16544r
%vreg484 [16512r,16576r:0)  0@16512r
%vreg486 [16464r,16496r:0)[16496r,16512r:1)  0@16464r 1@16496r
%vreg489 [16448r,16464r:0)  0@16448r
%vreg495 [16416r,16432r:0)  0@16416r
%vreg496 [16400r,16416r:0)  0@16400r
%vreg499 [16368r,16432r:0)  0@16368r
%vreg501 [16352r,16368r:0)  0@16352r
%vreg507 [16256r,16336r:0)  0@16256r
%vreg510 [16128r,16160r:0)[16160r,16208r:1)  0@16128r 1@16160r
%vreg513 [16112r,16192r:0)  0@16112r
%vreg514 [16096r,16112r:0)  0@16096r
%vreg517 [16032r,16048r:0)  0@16032r
%vreg519 [16016r,16048r:0)  0@16016r
%vreg522 [14800r,14816r:0)  0@14800r
%vreg524 [14784r,14816r:0)  0@14784r
%vreg527 [13568r,13584r:0)  0@13568r
%vreg529 [13552r,13584r:0)  0@13552r
%vreg533 [384r,400r:0)  0@384r
%vreg534 [368r,384r:0)  0@368r
%vreg537 [496r,512r:0)  0@496r
%vreg541 [1360r,1376r:0)  0@1360r
%vreg542 [1344r,1360r:0)  0@1344r
%vreg546 [1280r,1312r:0)[1312r,1328r:1)  0@1280r 1@1312r
%vreg549 [1264r,1328r:0)  0@1264r
%vreg550 [1248r,1264r:0)  0@1248r
%vreg554 [1184r,1216r:0)[1216r,1232r:1)  0@1184r 1@1216r
%vreg557 [1168r,1232r:0)  0@1168r
%vreg558 [1152r,1168r:0)  0@1152r
%vreg562 [1088r,1120r:0)[1120r,1136r:1)  0@1088r 1@1120r
%vreg565 [1072r,1136r:0)  0@1072r
%vreg566 [1056r,1072r:0)  0@1056r
%vreg570 [992r,1024r:0)[1024r,1040r:1)  0@992r 1@1024r
%vreg572 [976r,1040r:0)  0@976r
%vreg575 [944r,960r:0)  0@944r
%vreg578 [704r,736r:2)[736r,928r:0)[928r,960r:1)  0@736r 1@928r 2@704r
%vreg582 [880r,928r:0)  0@880r
%vreg585 [768r,800r:2)[800r,864r:0)[864r,880r:1)  0@800r 1@864r 2@768r
%vreg587 [832r,864r:0)  0@832r
%vreg589 [816r,832r:0)  0@816r
%vreg594 [752r,768r:0)  0@752r
%vreg599 [688r,704r:0)  0@688r
%vreg603 [656r,672r:0)  0@656r
%vreg605 [640r,656r:0)  0@640r
%vreg606 [624r,640r:0)  0@624r
%vreg608 [608r,672r:0)  0@608r
%vreg609 [592r,608r:0)  0@592r
%vreg613 [1456r,1488r:0)[1488r,1504r:1)  0@1456r 1@1488r
%vreg616 [1440r,1504r:0)  0@1440r
%vreg617 [1424r,1440r:0)  0@1424r
%vreg621 [1616r,1648r:0)[1648r,1664r:1)  0@1616r 1@1648r
%vreg624 [1600r,1616r:0)  0@1600r
%vreg626 [1584r,1664r:0)  0@1584r
%vreg627 [1568r,1584r:0)  0@1568r
%vreg631 [1808r,1840r:0)[1840r,1856r:1)  0@1808r 1@1840r
%vreg634 [1792r,1808r:0)  0@1792r
%vreg636 [1776r,1856r:0)  0@1776r
%vreg637 [1760r,1776r:0)  0@1760r
%vreg640 [2848r,2864r:0)  0@2848r
%vreg643 [2816r,2832r:0)  0@2816r
%vreg646 [2400r,2800r:0)[2800r,2832r:1)  0@2400r 1@2800r
%vreg650 [2544r,2704r:2)[2704r,2736r:0)[2736r,2768r:1)[2768r,2800r:3)  0@2704r 1@2736r 2@2544r 3@2768r
%vreg655 [2576r,2608r:2)[2608r,2640r:0)[2640r,2656r:1)  0@2608r 1@2640r 2@2576r
%vreg660 [2560r,2576r:0)  0@2560r
%vreg666 [2528r,2544r:0)  0@2528r
%vreg667 [2512r,2528r:0)  0@2512r
%vreg670 [2480r,2544r:0)  0@2480r
%vreg672 [2432r,2464r:0)[2464r,2480r:1)  0@2432r 1@2464r
%vreg675 [2416r,2432r:0)  0@2416r
%vreg681 [2384r,2400r:0)  0@2384r
%vreg682 [2368r,2384r:0)  0@2368r
%vreg685 [2336r,2400r:0)  0@2336r
%vreg687 [2320r,2336r:0)  0@2320r
%vreg693 [2224r,2304r:0)  0@2224r
%vreg696 [2096r,2128r:0)[2128r,2176r:1)  0@2096r 1@2128r
%vreg699 [2080r,2160r:0)  0@2080r
%vreg700 [2064r,2080r:0)  0@2064r
%vreg703 [2032r,2048r:0)  0@2032r
%vreg707 [2000r,2048r:0)  0@2000r
%vreg708 [1984r,2000r:0)  0@1984r
%vreg710 [1952r,1968r:0)  0@1952r
%vreg713 [3072r,3088r:0)  0@3072r
%vreg717 [3008r,3040r:0)[3040r,3056r:1)  0@3008r 1@3040r
%vreg719 [2992r,3056r:0)  0@2992r
%vreg722 [2960r,2976r:0)  0@2960r
%vreg724 [2944r,2976r:0)  0@2944r
%vreg726 [2928r,2944r:0)  0@2928r
%vreg728 [2912r,2928r:0)  0@2912r
%vreg730 [3136r,3152r:0)  0@3136r
%vreg734 [3600r,3632r:0)[3632r,3648r:1)  0@3600r 1@3632r
%vreg737 [3584r,3600r:0)  0@3584r
%vreg739 [3568r,3648r:0)  0@3568r
%vreg740 [3552r,3568r:0)  0@3552r
%vreg744 [3488r,3520r:0)[3520r,3536r:1)  0@3488r 1@3520r
%vreg746 [3472r,3536r:0)  0@3472r
%vreg752 [3392r,3424r:0)[3424r,3456r:1)  0@3392r 1@3424r
%vreg757 [3232r,3376r:0)  0@3232r
%vreg758 [3216r,3376r:0)[3376r,3424r:1)  0@3216r 1@3376r
%vreg760 [3328r,3344r:0)  0@3328r
%vreg764 [3264r,3296r:0)[3296r,3312r:1)  0@3264r 1@3296r
%vreg766 [3248r,3312r:0)  0@3248r
%vreg770 [3744r,3760r:0)  0@3744r
%vreg772 [3728r,3760r:0)  0@3728r
%vreg775 [4704r,4720r:0)  0@4704r
%vreg778 [4672r,4688r:0)  0@4672r
%vreg781 [4256r,4656r:0)[4656r,4688r:1)  0@4256r 1@4656r
%vreg785 [4400r,4560r:2)[4560r,4592r:0)[4592r,4624r:1)[4624r,4656r:3)  0@4560r 1@4592r 2@4400r 3@4624r
%vreg790 [4432r,4464r:2)[4464r,4496r:0)[4496r,4512r:1)  0@4464r 1@4496r 2@4432r
%vreg795 [4416r,4432r:0)  0@4416r
%vreg801 [4384r,4400r:0)  0@4384r
%vreg802 [4368r,4384r:0)  0@4368r
%vreg805 [4336r,4400r:0)  0@4336r
%vreg807 [4288r,4320r:0)[4320r,4336r:1)  0@4288r 1@4320r
%vreg810 [4272r,4288r:0)  0@4272r
%vreg816 [4240r,4256r:0)  0@4240r
%vreg817 [4224r,4240r:0)  0@4224r
%vreg820 [4192r,4256r:0)  0@4192r
%vreg822 [4176r,4192r:0)  0@4176r
%vreg828 [4080r,4160r:0)  0@4080r
%vreg831 [3952r,3984r:0)[3984r,4032r:1)  0@3952r 1@3984r
%vreg834 [3936r,4016r:0)  0@3936r
%vreg835 [3920r,3936r:0)  0@3920r
%vreg837 [3888r,3904r:0)  0@3888r
%vreg840 [4928r,4944r:0)  0@4928r
%vreg844 [4864r,4896r:0)[4896r,4912r:1)  0@4864r 1@4896r
%vreg846 [4848r,4912r:0)  0@4848r
%vreg849 [4816r,4832r:0)  0@4816r
%vreg851 [4800r,4832r:0)  0@4800r
%vreg853 [4784r,4800r:0)  0@4784r
%vreg855 [4768r,4784r:0)  0@4768r
%vreg857 [4992r,5008r:0)  0@4992r
%vreg861 [5456r,5488r:0)[5488r,5504r:1)  0@5456r 1@5488r
%vreg864 [5440r,5456r:0)  0@5440r
%vreg866 [5424r,5504r:0)  0@5424r
%vreg867 [5408r,5424r:0)  0@5408r
%vreg871 [5344r,5376r:0)[5376r,5392r:1)  0@5344r 1@5376r
%vreg873 [5328r,5392r:0)  0@5328r
%vreg879 [5248r,5280r:0)[5280r,5312r:1)  0@5248r 1@5280r
%vreg884 [5088r,5232r:0)  0@5088r
%vreg885 [5072r,5232r:0)[5232r,5280r:1)  0@5072r 1@5232r
%vreg887 [5184r,5200r:0)  0@5184r
%vreg891 [5120r,5152r:0)[5152r,5168r:1)  0@5120r 1@5152r
%vreg893 [5104r,5168r:0)  0@5104r
%vreg897 [5600r,5616r:0)  0@5600r
%vreg899 [5584r,5616r:0)  0@5584r
%vreg902 [6560r,6576r:0)  0@6560r
%vreg905 [6528r,6544r:0)  0@6528r
%vreg908 [6112r,6512r:0)[6512r,6544r:1)  0@6112r 1@6512r
%vreg912 [6256r,6416r:2)[6416r,6448r:0)[6448r,6480r:1)[6480r,6512r:3)  0@6416r 1@6448r 2@6256r 3@6480r
%vreg917 [6288r,6320r:2)[6320r,6352r:0)[6352r,6368r:1)  0@6320r 1@6352r 2@6288r
%vreg922 [6272r,6288r:0)  0@6272r
%vreg928 [6240r,6256r:0)  0@6240r
%vreg929 [6224r,6240r:0)  0@6224r
%vreg932 [6192r,6256r:0)  0@6192r
%vreg934 [6144r,6176r:0)[6176r,6192r:1)  0@6144r 1@6176r
%vreg937 [6128r,6144r:0)  0@6128r
%vreg943 [6096r,6112r:0)  0@6096r
%vreg944 [6080r,6096r:0)  0@6080r
%vreg947 [6048r,6112r:0)  0@6048r
%vreg949 [6032r,6048r:0)  0@6032r
%vreg955 [5936r,6016r:0)  0@5936r
%vreg958 [5808r,5840r:0)[5840r,5888r:1)  0@5808r 1@5840r
%vreg961 [5792r,5872r:0)  0@5792r
%vreg962 [5776r,5792r:0)  0@5776r
%vreg964 [5744r,5760r:0)  0@5744r
%vreg967 [6784r,6800r:0)  0@6784r
%vreg971 [6720r,6752r:0)[6752r,6768r:1)  0@6720r 1@6752r
%vreg973 [6704r,6768r:0)  0@6704r
%vreg976 [6672r,6688r:0)  0@6672r
%vreg978 [6656r,6688r:0)  0@6656r
%vreg980 [6640r,6656r:0)  0@6640r
%vreg982 [6624r,6640r:0)  0@6624r
%vreg984 [6848r,6864r:0)  0@6848r
%vreg988 [7312r,7344r:0)[7344r,7360r:1)  0@7312r 1@7344r
%vreg991 [7296r,7312r:0)  0@7296r
%vreg993 [7280r,7360r:0)  0@7280r
%vreg994 [7264r,7280r:0)  0@7264r
%vreg998 [7200r,7232r:0)[7232r,7248r:1)  0@7200r 1@7232r
%vreg1000 [7184r,7248r:0)  0@7184r
%vreg1006 [7104r,7136r:0)[7136r,7168r:1)  0@7104r 1@7136r
%vreg1011 [6944r,7088r:0)  0@6944r
%vreg1012 [6928r,7088r:0)[7088r,7136r:1)  0@6928r 1@7088r
%vreg1014 [7040r,7056r:0)  0@7040r
%vreg1018 [6976r,7008r:0)[7008r,7024r:1)  0@6976r 1@7008r
%vreg1020 [6960r,7024r:0)  0@6960r
%vreg1024 [7456r,7472r:0)  0@7456r
%vreg1026 [7440r,7472r:0)  0@7440r
%vreg1029 [8384r,8400r:0)  0@8384r
%vreg1032 [8352r,8368r:0)  0@8352r
%vreg1035 [7936r,8336r:0)[8336r,8368r:1)  0@7936r 1@8336r
%vreg1039 [8080r,8240r:2)[8240r,8272r:0)[8272r,8304r:1)[8304r,8336r:3)  0@8240r 1@8272r 2@8080r 3@8304r
%vreg1044 [8112r,8144r:2)[8144r,8176r:0)[8176r,8192r:1)  0@8144r 1@8176r 2@8112r
%vreg1049 [8096r,8112r:0)  0@8096r
%vreg1055 [8064r,8080r:0)  0@8064r
%vreg1056 [8048r,8064r:0)  0@8048r
%vreg1059 [8016r,8080r:0)  0@8016r
%vreg1061 [7968r,8000r:0)[8000r,8016r:1)  0@7968r 1@8000r
%vreg1064 [7952r,7968r:0)  0@7952r
%vreg1070 [7920r,7936r:0)  0@7920r
%vreg1071 [7904r,7920r:0)  0@7904r
%vreg1074 [7872r,7936r:0)  0@7872r
%vreg1076 [7856r,7872r:0)  0@7856r
%vreg1082 [7760r,7840r:0)  0@7760r
%vreg1085 [7632r,7664r:0)[7664r,7712r:1)  0@7632r 1@7664r
%vreg1088 [7616r,7696r:0)  0@7616r
%vreg1089 [7600r,7616r:0)  0@7600r
%vreg1092 [8608r,8624r:0)  0@8608r
%vreg1096 [8544r,8576r:0)[8576r,8592r:1)  0@8544r 1@8576r
%vreg1098 [8528r,8592r:0)  0@8528r
%vreg1101 [8496r,8512r:0)  0@8496r
%vreg1103 [8480r,8512r:0)  0@8480r
%vreg1105 [8464r,8480r:0)  0@8464r
%vreg1107 [8448r,8464r:0)  0@8448r
%vreg1109 [8672r,8688r:0)  0@8672r
%vreg1112 [9952r,9968r:0)  0@9952r
%vreg1115 [9920r,9936r:0)  0@9920r
%vreg1118 [9504r,9904r:0)[9904r,9936r:1)  0@9504r 1@9904r
%vreg1122 [9648r,9808r:2)[9808r,9840r:0)[9840r,9872r:1)[9872r,9904r:3)  0@9808r 1@9840r 2@9648r 3@9872r
%vreg1127 [9680r,9712r:2)[9712r,9744r:0)[9744r,9760r:1)  0@9712r 1@9744r 2@9680r
%vreg1132 [9664r,9680r:0)  0@9664r
%vreg1138 [9632r,9648r:0)  0@9632r
%vreg1139 [9616r,9632r:0)  0@9616r
%vreg1142 [9584r,9648r:0)  0@9584r
%vreg1144 [9536r,9568r:0)[9568r,9584r:1)  0@9536r 1@9568r
%vreg1147 [9520r,9536r:0)  0@9520r
%vreg1153 [9488r,9504r:0)  0@9488r
%vreg1154 [9472r,9488r:0)  0@9472r
%vreg1157 [9440r,9504r:0)  0@9440r
%vreg1159 [9424r,9440r:0)  0@9424r
%vreg1162 [9392r,9408r:0)  0@9392r
%vreg1165 [9328r,9408r:0)  0@9328r
%vreg1168 [9200r,9232r:0)[9232r,9280r:1)  0@9200r 1@9232r
%vreg1171 [9184r,9264r:0)  0@9184r
%vreg1172 [9168r,9184r:0)  0@9168r
%vreg1175 [9136r,9152r:0)  0@9136r
%vreg1177 [9088r,9120r:0)[9120r,9152r:1)  0@9088r 1@9120r
%vreg1183 [9024r,9056r:0)[9056r,9072r:1)  0@9024r 1@9056r
%vreg1185 [9008r,9072r:0)  0@9008r
%vreg1191 [8928r,8960r:0)[8960r,8992r:1)  0@8928r 1@8960r
%vreg1196 [8768r,8912r:0)  0@8768r
%vreg1197 [8752r,8912r:0)[8912r,8960r:1)  0@8752r 1@8912r
%vreg1199 [8864r,8880r:0)  0@8864r
%vreg1203 [8800r,8832r:0)[8832r,8848r:1)  0@8800r 1@8832r
%vreg1205 [8784r,8848r:0)  0@8784r
%vreg1208 [10176r,10192r:0)  0@10176r
%vreg1212 [10112r,10144r:0)[10144r,10160r:1)  0@10112r 1@10144r
%vreg1214 [10096r,10160r:0)  0@10096r
%vreg1217 [10064r,10080r:0)  0@10064r
%vreg1219 [10048r,10080r:0)  0@10048r
%vreg1221 [10032r,10048r:0)  0@10032r
%vreg1223 [10016r,10032r:0)  0@10016r
%vreg1225 [10240r,10256r:0)  0@10240r
%vreg1229 [10576r,10608r:0)[10608r,10624r:1)  0@10576r 1@10608r
%vreg1231 [10560r,10624r:0)  0@10560r
%vreg1236 [10320r,10480r:2)[10480r,10528r:0)[10528r,10544r:1)  0@10480r 1@10528r 2@10320r
%vreg1237 [10496r,10544r:0)  0@10496r
%vreg1240 [10336r,10480r:0)  0@10336r
%vreg1243 [10432r,10448r:0)  0@10432r
%vreg1247 [10368r,10400r:0)[10400r,10416r:1)  0@10368r 1@10400r
%vreg1249 [10352r,10416r:0)  0@10352r
%vreg1252 [7536r,7552r:0)  0@7536r
%vreg1254 [7520r,7552r:0)  0@7520r
%vreg1257 [5680r,5696r:0)  0@5680r
%vreg1259 [5664r,5696r:0)  0@5664r
%vreg1262 [3824r,3840r:0)  0@3824r
%vreg1264 [3808r,3840r:0)  0@3808r
%vreg1266 [18112r,18128r:0)  0@18112r
%vreg1268 [17936r,18000r:0)  0@17936r
%vreg1269 [17968r,18016r:0)  0@17968r
RegMasks: 144r 2192r 4048r 5904r 7728r 9296r 12560r 13792r 15024r 16224r 17168r 18032r
********** MACHINEINSTRS **********
# Machine code for function unRLE_obuf_to_output_SMALL: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=1, align=1, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=1, align=1, at location [SP+8]
Function Live Ins: %RDI in %vreg0

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI
16B		%vreg1<def> = COPY %RDI; GR64:%vreg1
48B		%vreg6<def> = MOV64ri <ga:@unRLE_obuf_to_output_SMALL>; GR64:%vreg6
80B		%vreg7<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg7
96B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
112B		%RDI<def> = COPY %vreg6; GR64:%vreg6
128B		%RSI<def> = COPY %vreg7; GR64:%vreg7
144B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
160B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
192B		STACKMAP 0, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, %vreg1, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1] GR64:%vreg1
208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%s.addr] GR64:%vreg1
240B		%vreg4<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg4
256B		CMP8mi %vreg4, 1, %noreg, 20, %noreg, 0, %EFLAGS<imp-def>; mem:LD1[%blockRandomised] GR64:%vreg4
272B		JE_1 <BB#47>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#47 BB#1

288B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
304B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2

320B	BB#2: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#1 BB#46 BB#37 BB#35 BB#29 BB#27 BB#21 BB#19
336B		JMP_1 <BB#3>
	    Successors according to CFG: BB#3

352B	BB#3: derived from LLVM BB %while.body.2
	    Predecessors according to CFG: BB#2 BB#9
368B		%vreg534<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg534
384B		%vreg533<def> = MOV64rm %vreg534, 1, %noreg, 0, %noreg; mem:LD8[%strm] GR64:%vreg533,%vreg534
400B		CMP32mi8 %vreg533, 1, %noreg, 32, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_out] GR64:%vreg533
416B		JNE_1 <BB#5>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#5 BB#4

432B	BB#4: derived from LLVM BB %if.then.3
	    Predecessors according to CFG: BB#3
448B		MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST1[%retval]
464B		JMP_1 <BB#73>
	    Successors according to CFG: BB#73

480B	BB#5: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#3
496B		%vreg537<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg537
512B		CMP32mi8 %vreg537, 1, %noreg, 16, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%state_out_len] GR64:%vreg537
528B		JNE_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#6

544B	BB#6: derived from LLVM BB %if.then.5
	    Predecessors according to CFG: BB#5
560B		JMP_1 <BB#10>
	    Successors according to CFG: BB#10

576B	BB#7: derived from LLVM BB %if.end.6
	    Predecessors according to CFG: BB#5
592B		%vreg609<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg609
608B		%vreg608<def> = MOV8rm %vreg609, 1, %noreg, 12, %noreg; mem:LD1[%state_out_ch] GR8:%vreg608 GR64:%vreg609
624B		%vreg606<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg606
640B		%vreg605<def> = MOV64rm %vreg606, 1, %noreg, 0, %noreg; mem:LD8[%strm7] GR64:%vreg605,%vreg606
656B		%vreg603<def> = MOV64rm %vreg605, 1, %noreg, 24, %noreg; mem:LD8[%next_out] GR64:%vreg603,%vreg605
672B		MOV8mr %vreg603, 1, %noreg, 0, %noreg, %vreg608; mem:ST1[%11] GR64:%vreg603 GR8:%vreg608
688B		%vreg599<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg599
704B		%vreg578<def> = MOV32rm %vreg599, 1, %noreg, 3184, %noreg; mem:LD4[%calculatedBlockCRC] GR32:%vreg578 GR64:%vreg599
736B		%vreg578<def,tied1> = SHL32ri %vreg578<tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg578
752B		%vreg594<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg594
768B		%vreg585<def> = MOV32rm %vreg594, 1, %noreg, 3184, %noreg; mem:LD4[%calculatedBlockCRC8] GR32:%vreg585 GR64:%vreg594
800B		%vreg585<def,tied1> = SHR32ri %vreg585<tied0>, 24, %EFLAGS<imp-def,dead>; GR32:%vreg585
816B		%vreg589<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg589
832B		%vreg587<def> = MOVZX32rm8 %vreg589, 1, %noreg, 12, %noreg; mem:LD1[%state_out_ch9] GR32:%vreg587 GR64:%vreg589
864B		%vreg585<def,tied1> = XOR32rr %vreg585<tied0>, %vreg587, %EFLAGS<imp-def,dead>; GR32:%vreg585,%vreg587
880B		%vreg582:sub_32bit<def,read-undef> = MOV32rr %vreg585; GR64_NOSP:%vreg582 GR32:%vreg585
928B		%vreg578<def,tied1> = XOR32rm %vreg578<tied0>, %noreg, 4, %vreg582, <ga:@BZ2_crc32Table>, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%arrayidx] GR32:%vreg578 GR64_NOSP:%vreg582
944B		%vreg575<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg575
960B		MOV32mr %vreg575, 1, %noreg, 3184, %noreg, %vreg578; mem:ST4[%calculatedBlockCRC11] GR64:%vreg575 GR32:%vreg578
976B		%vreg572<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg572
992B		%vreg570<def> = MOV32rm %vreg572, 1, %noreg, 16, %noreg; mem:LD4[%state_out_len12] GR32:%vreg570 GR64:%vreg572
1024B		%vreg570<def,tied1> = ADD32ri8 %vreg570<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg570
1040B		MOV32mr %vreg572, 1, %noreg, 16, %noreg, %vreg570; mem:ST4[%state_out_len12] GR64:%vreg572 GR32:%vreg570
1056B		%vreg566<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg566
1072B		%vreg565<def> = MOV64rm %vreg566, 1, %noreg, 0, %noreg; mem:LD8[%strm13] GR64:%vreg565,%vreg566
1088B		%vreg562<def> = MOV64rm %vreg565, 1, %noreg, 24, %noreg; mem:LD8[%next_out14] GR64:%vreg562,%vreg565
1120B		%vreg562<def,tied1> = ADD64ri8 %vreg562<tied0>, 1, %EFLAGS<imp-def,dead>; GR64:%vreg562
1136B		MOV64mr %vreg565, 1, %noreg, 24, %noreg, %vreg562; mem:ST8[%next_out14] GR64:%vreg565,%vreg562
1152B		%vreg558<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg558
1168B		%vreg557<def> = MOV64rm %vreg558, 1, %noreg, 0, %noreg; mem:LD8[%strm15] GR64:%vreg557,%vreg558
1184B		%vreg554<def> = MOV32rm %vreg557, 1, %noreg, 32, %noreg; mem:LD4[%avail_out16] GR32:%vreg554 GR64:%vreg557
1216B		%vreg554<def,tied1> = ADD32ri8 %vreg554<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg554
1232B		MOV32mr %vreg557, 1, %noreg, 32, %noreg, %vreg554; mem:ST4[%avail_out16] GR64:%vreg557 GR32:%vreg554
1248B		%vreg550<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg550
1264B		%vreg549<def> = MOV64rm %vreg550, 1, %noreg, 0, %noreg; mem:LD8[%strm18] GR64:%vreg549,%vreg550
1280B		%vreg546<def> = MOV32rm %vreg549, 1, %noreg, 36, %noreg; mem:LD4[%total_out_lo32] GR32:%vreg546 GR64:%vreg549
1312B		%vreg546<def,tied1> = ADD32ri8 %vreg546<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg546
1328B		MOV32mr %vreg549, 1, %noreg, 36, %noreg, %vreg546; mem:ST4[%total_out_lo32] GR64:%vreg549 GR32:%vreg546
1344B		%vreg542<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg542
1360B		%vreg541<def> = MOV64rm %vreg542, 1, %noreg, 0, %noreg; mem:LD8[%strm19] GR64:%vreg541,%vreg542
1376B		CMP32mi8 %vreg541, 1, %noreg, 36, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%total_out_lo3220] GR64:%vreg541
1392B		JNE_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#8

1408B	BB#8: derived from LLVM BB %if.then.23
	    Predecessors according to CFG: BB#7
1424B		%vreg617<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg617
1440B		%vreg616<def> = MOV64rm %vreg617, 1, %noreg, 0, %noreg; mem:LD8[%strm24] GR64:%vreg616,%vreg617
1456B		%vreg613<def> = MOV32rm %vreg616, 1, %noreg, 40, %noreg; mem:LD4[%total_out_hi32] GR32:%vreg613 GR64:%vreg616
1488B		%vreg613<def,tied1> = ADD32ri8 %vreg613<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg613
1504B		MOV32mr %vreg616, 1, %noreg, 40, %noreg, %vreg613; mem:ST4[%total_out_hi32] GR64:%vreg616 GR32:%vreg613
	    Successors according to CFG: BB#9

1520B	BB#9: derived from LLVM BB %if.end.26
	    Predecessors according to CFG: BB#7 BB#8
1536B		JMP_1 <BB#3>
	    Successors according to CFG: BB#3

1552B	BB#10: derived from LLVM BB %while.end
	    Predecessors according to CFG: BB#6
1568B		%vreg627<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg627
1584B		%vreg626<def> = MOV32rm %vreg627, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used] GR32:%vreg626 GR64:%vreg627
1600B		%vreg624<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg624
1616B		%vreg621<def> = MOV32rm %vreg624, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock] GR32:%vreg621 GR64:%vreg624
1648B		%vreg621<def,tied1> = ADD32ri8 %vreg621<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg621
1664B		CMP32rr %vreg626, %vreg621, %EFLAGS<imp-def>; GR32:%vreg626,%vreg621
1680B		JNE_1 <BB#12>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#12 BB#11

1696B	BB#11: derived from LLVM BB %if.then.29
	    Predecessors according to CFG: BB#10
1712B		MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST1[%retval]
1728B		JMP_1 <BB#73>
	    Successors according to CFG: BB#73

1744B	BB#12: derived from LLVM BB %if.end.30
	    Predecessors according to CFG: BB#10
1760B		%vreg637<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg637
1776B		%vreg636<def> = MOV32rm %vreg637, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used31] GR32:%vreg636 GR64:%vreg637
1792B		%vreg634<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg634
1808B		%vreg631<def> = MOV32rm %vreg634, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock32] GR32:%vreg631 GR64:%vreg634
1840B		%vreg631<def,tied1> = ADD32ri8 %vreg631<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg631
1856B		CMP32rr %vreg636, %vreg631, %EFLAGS<imp-def>; GR32:%vreg636,%vreg631
1872B		JLE_1 <BB#14>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#14 BB#13

1888B	BB#13: derived from LLVM BB %if.then.36
	    Predecessors according to CFG: BB#12
1904B		MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 1; mem:ST1[%retval]
1920B		JMP_1 <BB#73>
	    Successors according to CFG: BB#73

1936B	BB#14: derived from LLVM BB %if.end.37
	    Predecessors according to CFG: BB#12
1952B		%vreg710<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg710
1968B		MOV32mi %vreg710, 1, %noreg, 16, %noreg, 1; mem:ST4[%state_out_len38] GR64:%vreg710
1984B		%vreg708<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg708
2000B		%vreg707<def> = MOV32rm %vreg708, 1, %noreg, 64, %noreg; mem:LD4[%k0] GR32:%vreg707 GR64:%vreg708
2032B		%vreg703<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg703
2048B		MOV8mr %vreg703, 1, %noreg, 12, %noreg, %vreg707:sub_8bit; mem:ST1[%state_out_ch40] GR64:%vreg703 GR32:%vreg707
2064B		%vreg700<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg700
2080B		%vreg699<def> = MOV32rm %vreg700, 1, %noreg, 60, %noreg; mem:LD4[%tPos] GR32:%vreg699 GR64:%vreg700
2096B		%vreg696<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg696
2128B		%vreg696<def,tied1> = ADD64ri32 %vreg696<tied0>, 1096, %EFLAGS<imp-def,dead>; GR64:%vreg696
2144B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2160B		%EDI<def> = COPY %vreg699; GR32:%vreg699
2176B		%RSI<def> = COPY %vreg696; GR64:%vreg696
2192B		CALL64pcrel32 <ga:@BZ2_indexIntoF>, <regmask>, %RSP<imp-use>, %EDI<imp-use>, %RSI<imp-use,kill>, %EAX<imp-def>
2208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2224B		%vreg693<def> = COPY %EAX<kill>; GR32:%vreg693
2240B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2256B		STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
2272B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2304B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg693:sub_8bit; mem:ST1[%k1] GR32:%vreg693
2320B		%vreg687<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg687
2336B		%vreg685:sub_32bit<def,read-undef> = MOV32rm %vreg687, 1, %noreg, 60, %noreg; mem:LD4[%tPos42] GR64_NOSP:%vreg685 GR64:%vreg687
2368B		%vreg682<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg682
2384B		%vreg681<def> = MOV64rm %vreg682, 1, %noreg, 3160, %noreg; mem:LD8[%ll16] GR64:%vreg681,%vreg682
2400B		%vreg646<def> = MOVZX32rm16 %vreg681, 2, %vreg685, 0, %noreg; mem:LD2[%arrayidx44] GR32:%vreg646 GR64:%vreg681 GR64_NOSP:%vreg685
2416B		%vreg675<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg675
2432B		%vreg672<def> = MOV32rm %vreg675, 1, %noreg, 60, %noreg; mem:LD4[%tPos46] GR32:%vreg672 GR64:%vreg675
2464B		%vreg672<def,tied1> = SHR32ri %vreg672<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg672
2480B		%vreg670:sub_32bit<def,read-undef> = MOV32rr %vreg672; GR64_NOSP:%vreg670 GR32:%vreg672
2512B		%vreg667<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg667
2528B		%vreg666<def> = MOV64rm %vreg667, 1, %noreg, 3168, %noreg; mem:LD8[%ll4] GR64:%vreg666,%vreg667
2544B		%vreg650<def> = MOVZX32rm8 %vreg666, 1, %vreg670, 0, %noreg; mem:LD1[%arrayidx49] GR32:%vreg650 GR64:%vreg666 GR64_NOSP:%vreg670
2560B		%vreg660<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg660
2576B		%vreg655<def> = MOV32rm %vreg660, 1, %noreg, 60, %noreg; mem:LD4[%tPos51] GR32:%vreg655 GR64:%vreg660
2608B		%vreg655<def,tied1> = SHL32ri %vreg655<tied0>, 2, %EFLAGS<imp-def,dead>; GR32:%vreg655
2640B		%vreg655<def,tied1> = AND32ri8 %vreg655<tied0>, 4, %EFLAGS<imp-def,dead>; GR32:%vreg655
2656B		%ECX<def> = COPY %vreg655; GR32:%vreg655
2672B		%CL<def> = KILL %ECX<kill>
2704B		%vreg650<def,tied1> = SHR32rCL %vreg650<tied0>, %EFLAGS<imp-def,dead>, %CL<imp-use,kill>; GR32:%vreg650
2736B		%vreg650<def,tied1> = AND32ri8 %vreg650<tied0>, 15, %EFLAGS<imp-def,dead>; GR32:%vreg650
2768B		%vreg650<def,tied1> = SHL32ri %vreg650<tied0>, 16, %EFLAGS<imp-def,dead>; GR32:%vreg650
2800B		%vreg646<def,tied1> = OR32rr %vreg646<tied0>, %vreg650, %EFLAGS<imp-def,dead>; GR32:%vreg646,%vreg650
2816B		%vreg643<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg643
2832B		MOV32mr %vreg643, 1, %noreg, 60, %noreg, %vreg646; mem:ST4[%tPos56] GR64:%vreg643 GR32:%vreg646
2848B		%vreg640<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg640
2864B		CMP32mi8 %vreg640, 1, %noreg, 24, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%rNToGo] GR64:%vreg640
2880B		JNE_1 <BB#18>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#18 BB#15

2896B	BB#15: derived from LLVM BB %if.then.59
	    Predecessors according to CFG: BB#14
2912B		%vreg728<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg728
2928B		%vreg726<def> = MOVSX64rm32 %vreg728, 1, %noreg, 28, %noreg; mem:LD4[%rTPos] GR64_NOSP:%vreg726 GR64:%vreg728
2944B		%vreg724<def> = MOV32rm %noreg, 4, %vreg726, <ga:@BZ2_rNums>, %noreg; mem:LD4[%arrayidx61] GR32:%vreg724 GR64_NOSP:%vreg726
2960B		%vreg722<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg722
2976B		MOV32mr %vreg722, 1, %noreg, 24, %noreg, %vreg724; mem:ST4[%rNToGo62] GR64:%vreg722 GR32:%vreg724
2992B		%vreg719<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg719
3008B		%vreg717<def> = MOV32rm %vreg719, 1, %noreg, 28, %noreg; mem:LD4[%rTPos63] GR32:%vreg717 GR64:%vreg719
3040B		%vreg717<def,tied1> = ADD32ri8 %vreg717<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg717
3056B		MOV32mr %vreg719, 1, %noreg, 28, %noreg, %vreg717; mem:ST4[%rTPos63] GR64:%vreg719 GR32:%vreg717
3072B		%vreg713<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg713
3088B		CMP32mi %vreg713, 1, %noreg, 28, %noreg, 512, %EFLAGS<imp-def>; mem:LD4[%rTPos65] GR64:%vreg713
3104B		JNE_1 <BB#17>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#17 BB#16

3120B	BB#16: derived from LLVM BB %if.then.68
	    Predecessors according to CFG: BB#15
3136B		%vreg730<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg730
3152B		MOV32mi %vreg730, 1, %noreg, 28, %noreg, 0; mem:ST4[%rTPos69] GR64:%vreg730
	    Successors according to CFG: BB#17

3168B	BB#17: derived from LLVM BB %if.end.70
	    Predecessors according to CFG: BB#15 BB#16
3184B		JMP_1 <BB#18>
	    Successors according to CFG: BB#18

3200B	BB#18: derived from LLVM BB %if.end.71
	    Predecessors according to CFG: BB#14 BB#17
3216B		%vreg758<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg758
3232B		%vreg757<def> = MOV32ri 1; GR32:%vreg757
3248B		%vreg766<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg766
3264B		%vreg764<def> = MOV32rm %vreg766, 1, %noreg, 24, %noreg; mem:LD4[%rNToGo72] GR32:%vreg764 GR64:%vreg766
3296B		%vreg764<def,tied1> = ADD32ri8 %vreg764<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg764
3312B		MOV32mr %vreg766, 1, %noreg, 24, %noreg, %vreg764; mem:ST4[%rNToGo72] GR64:%vreg766 GR32:%vreg764
3328B		%vreg760<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg760
3344B		CMP32mi8 %vreg760, 1, %noreg, 24, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%rNToGo74] GR64:%vreg760
3376B		%vreg758<def,tied1> = CMOVE32rr %vreg758<tied0>, %vreg757, %EFLAGS<imp-use,kill>; GR32:%vreg758,%vreg757
3392B		%vreg752<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg752
3424B		%vreg752<def,tied1> = XOR32rr %vreg752<tied0>, %vreg758, %EFLAGS<imp-def,dead>; GR32:%vreg752,%vreg758
3456B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg752:sub_8bit; mem:ST1[%k1] GR32:%vreg752
3472B		%vreg746<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg746
3488B		%vreg744<def> = MOV32rm %vreg746, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used80] GR32:%vreg744 GR64:%vreg746
3520B		%vreg744<def,tied1> = ADD32ri8 %vreg744<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg744
3536B		MOV32mr %vreg746, 1, %noreg, 1092, %noreg, %vreg744; mem:ST4[%nblock_used80] GR64:%vreg746 GR32:%vreg744
3552B		%vreg740<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg740
3568B		%vreg739<def> = MOV32rm %vreg740, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used82] GR32:%vreg739 GR64:%vreg740
3584B		%vreg737<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg737
3600B		%vreg734<def> = MOV32rm %vreg737, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock83] GR32:%vreg734 GR64:%vreg737
3632B		%vreg734<def,tied1> = ADD32ri8 %vreg734<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg734
3648B		CMP32rr %vreg739, %vreg734, %EFLAGS<imp-def>; GR32:%vreg739,%vreg734
3664B		JNE_1 <BB#20>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#20 BB#19

3680B	BB#19: derived from LLVM BB %if.then.87
	    Predecessors according to CFG: BB#18
3696B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2

3712B	BB#20: derived from LLVM BB %if.end.88
	    Predecessors according to CFG: BB#18
3728B		%vreg772<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg772
3744B		%vreg770<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg770
3760B		CMP32rm %vreg772, %vreg770, 1, %noreg, 64, %noreg, %EFLAGS<imp-def>; mem:LD4[%k090] GR32:%vreg772 GR64:%vreg770
3776B		JE_1 <BB#22>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#22 BB#21

3792B	BB#21: derived from LLVM BB %if.then.93
	    Predecessors according to CFG: BB#20
3808B		%vreg1264<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg1264
3824B		%vreg1262<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1262
3840B		MOV32mr %vreg1262, 1, %noreg, 64, %noreg, %vreg1264; mem:ST4[%k095] GR64:%vreg1262 GR32:%vreg1264
3856B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2

3872B	BB#22: derived from LLVM BB %if.end.96
	    Predecessors according to CFG: BB#20
3888B		%vreg837<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg837
3904B		MOV32mi %vreg837, 1, %noreg, 16, %noreg, 2; mem:ST4[%state_out_len97] GR64:%vreg837
3920B		%vreg835<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg835
3936B		%vreg834<def> = MOV32rm %vreg835, 1, %noreg, 60, %noreg; mem:LD4[%tPos98] GR32:%vreg834 GR64:%vreg835
3952B		%vreg831<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg831
3984B		%vreg831<def,tied1> = ADD64ri32 %vreg831<tied0>, 1096, %EFLAGS<imp-def,dead>; GR64:%vreg831
4000B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4016B		%EDI<def> = COPY %vreg834; GR32:%vreg834
4032B		%RSI<def> = COPY %vreg831; GR64:%vreg831
4048B		CALL64pcrel32 <ga:@BZ2_indexIntoF>, <regmask>, %RSP<imp-use>, %EDI<imp-use>, %RSI<imp-use,kill>, %EAX<imp-def>
4064B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4080B		%vreg828<def> = COPY %EAX<kill>; GR32:%vreg828
4096B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4112B		STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
4128B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4160B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg828:sub_8bit; mem:ST1[%k1] GR32:%vreg828
4176B		%vreg822<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg822
4192B		%vreg820:sub_32bit<def,read-undef> = MOV32rm %vreg822, 1, %noreg, 60, %noreg; mem:LD4[%tPos103] GR64_NOSP:%vreg820 GR64:%vreg822
4224B		%vreg817<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg817
4240B		%vreg816<def> = MOV64rm %vreg817, 1, %noreg, 3160, %noreg; mem:LD8[%ll16105] GR64:%vreg816,%vreg817
4256B		%vreg781<def> = MOVZX32rm16 %vreg816, 2, %vreg820, 0, %noreg; mem:LD2[%arrayidx106] GR32:%vreg781 GR64:%vreg816 GR64_NOSP:%vreg820
4272B		%vreg810<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg810
4288B		%vreg807<def> = MOV32rm %vreg810, 1, %noreg, 60, %noreg; mem:LD4[%tPos108] GR32:%vreg807 GR64:%vreg810
4320B		%vreg807<def,tied1> = SHR32ri %vreg807<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg807
4336B		%vreg805:sub_32bit<def,read-undef> = MOV32rr %vreg807; GR64_NOSP:%vreg805 GR32:%vreg807
4368B		%vreg802<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg802
4384B		%vreg801<def> = MOV64rm %vreg802, 1, %noreg, 3168, %noreg; mem:LD8[%ll4111] GR64:%vreg801,%vreg802
4400B		%vreg785<def> = MOVZX32rm8 %vreg801, 1, %vreg805, 0, %noreg; mem:LD1[%arrayidx112] GR32:%vreg785 GR64:%vreg801 GR64_NOSP:%vreg805
4416B		%vreg795<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg795
4432B		%vreg790<def> = MOV32rm %vreg795, 1, %noreg, 60, %noreg; mem:LD4[%tPos114] GR32:%vreg790 GR64:%vreg795
4464B		%vreg790<def,tied1> = SHL32ri %vreg790<tied0>, 2, %EFLAGS<imp-def,dead>; GR32:%vreg790
4496B		%vreg790<def,tied1> = AND32ri8 %vreg790<tied0>, 4, %EFLAGS<imp-def,dead>; GR32:%vreg790
4512B		%ECX<def> = COPY %vreg790; GR32:%vreg790
4528B		%CL<def> = KILL %ECX<kill>
4560B		%vreg785<def,tied1> = SHR32rCL %vreg785<tied0>, %EFLAGS<imp-def,dead>, %CL<imp-use,kill>; GR32:%vreg785
4592B		%vreg785<def,tied1> = AND32ri8 %vreg785<tied0>, 15, %EFLAGS<imp-def,dead>; GR32:%vreg785
4624B		%vreg785<def,tied1> = SHL32ri %vreg785<tied0>, 16, %EFLAGS<imp-def,dead>; GR32:%vreg785
4656B		%vreg781<def,tied1> = OR32rr %vreg781<tied0>, %vreg785, %EFLAGS<imp-def,dead>; GR32:%vreg781,%vreg785
4672B		%vreg778<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg778
4688B		MOV32mr %vreg778, 1, %noreg, 60, %noreg, %vreg781; mem:ST4[%tPos121] GR64:%vreg778 GR32:%vreg781
4704B		%vreg775<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg775
4720B		CMP32mi8 %vreg775, 1, %noreg, 24, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%rNToGo122] GR64:%vreg775
4736B		JNE_1 <BB#26>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#26 BB#23

4752B	BB#23: derived from LLVM BB %if.then.125
	    Predecessors according to CFG: BB#22
4768B		%vreg855<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg855
4784B		%vreg853<def> = MOVSX64rm32 %vreg855, 1, %noreg, 28, %noreg; mem:LD4[%rTPos126] GR64_NOSP:%vreg853 GR64:%vreg855
4800B		%vreg851<def> = MOV32rm %noreg, 4, %vreg853, <ga:@BZ2_rNums>, %noreg; mem:LD4[%arrayidx128] GR32:%vreg851 GR64_NOSP:%vreg853
4816B		%vreg849<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg849
4832B		MOV32mr %vreg849, 1, %noreg, 24, %noreg, %vreg851; mem:ST4[%rNToGo129] GR64:%vreg849 GR32:%vreg851
4848B		%vreg846<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg846
4864B		%vreg844<def> = MOV32rm %vreg846, 1, %noreg, 28, %noreg; mem:LD4[%rTPos130] GR32:%vreg844 GR64:%vreg846
4896B		%vreg844<def,tied1> = ADD32ri8 %vreg844<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg844
4912B		MOV32mr %vreg846, 1, %noreg, 28, %noreg, %vreg844; mem:ST4[%rTPos130] GR64:%vreg846 GR32:%vreg844
4928B		%vreg840<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg840
4944B		CMP32mi %vreg840, 1, %noreg, 28, %noreg, 512, %EFLAGS<imp-def>; mem:LD4[%rTPos132] GR64:%vreg840
4960B		JNE_1 <BB#25>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#25 BB#24

4976B	BB#24: derived from LLVM BB %if.then.135
	    Predecessors according to CFG: BB#23
4992B		%vreg857<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg857
5008B		MOV32mi %vreg857, 1, %noreg, 28, %noreg, 0; mem:ST4[%rTPos136] GR64:%vreg857
	    Successors according to CFG: BB#25

5024B	BB#25: derived from LLVM BB %if.end.137
	    Predecessors according to CFG: BB#23 BB#24
5040B		JMP_1 <BB#26>
	    Successors according to CFG: BB#26

5056B	BB#26: derived from LLVM BB %if.end.138
	    Predecessors according to CFG: BB#22 BB#25
5072B		%vreg885<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg885
5088B		%vreg884<def> = MOV32ri 1; GR32:%vreg884
5104B		%vreg893<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg893
5120B		%vreg891<def> = MOV32rm %vreg893, 1, %noreg, 24, %noreg; mem:LD4[%rNToGo139] GR32:%vreg891 GR64:%vreg893
5152B		%vreg891<def,tied1> = ADD32ri8 %vreg891<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg891
5168B		MOV32mr %vreg893, 1, %noreg, 24, %noreg, %vreg891; mem:ST4[%rNToGo139] GR64:%vreg893 GR32:%vreg891
5184B		%vreg887<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg887
5200B		CMP32mi8 %vreg887, 1, %noreg, 24, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%rNToGo141] GR64:%vreg887
5232B		%vreg885<def,tied1> = CMOVE32rr %vreg885<tied0>, %vreg884, %EFLAGS<imp-use,kill>; GR32:%vreg885,%vreg884
5248B		%vreg879<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg879
5280B		%vreg879<def,tied1> = XOR32rr %vreg879<tied0>, %vreg885, %EFLAGS<imp-def,dead>; GR32:%vreg879,%vreg885
5312B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg879:sub_8bit; mem:ST1[%k1] GR32:%vreg879
5328B		%vreg873<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg873
5344B		%vreg871<def> = MOV32rm %vreg873, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used148] GR32:%vreg871 GR64:%vreg873
5376B		%vreg871<def,tied1> = ADD32ri8 %vreg871<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg871
5392B		MOV32mr %vreg873, 1, %noreg, 1092, %noreg, %vreg871; mem:ST4[%nblock_used148] GR64:%vreg873 GR32:%vreg871
5408B		%vreg867<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg867
5424B		%vreg866<def> = MOV32rm %vreg867, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used150] GR32:%vreg866 GR64:%vreg867
5440B		%vreg864<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg864
5456B		%vreg861<def> = MOV32rm %vreg864, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock151] GR32:%vreg861 GR64:%vreg864
5488B		%vreg861<def,tied1> = ADD32ri8 %vreg861<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg861
5504B		CMP32rr %vreg866, %vreg861, %EFLAGS<imp-def>; GR32:%vreg866,%vreg861
5520B		JNE_1 <BB#28>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#28 BB#27

5536B	BB#27: derived from LLVM BB %if.then.155
	    Predecessors according to CFG: BB#26
5552B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2

5568B	BB#28: derived from LLVM BB %if.end.156
	    Predecessors according to CFG: BB#26
5584B		%vreg899<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg899
5600B		%vreg897<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg897
5616B		CMP32rm %vreg899, %vreg897, 1, %noreg, 64, %noreg, %EFLAGS<imp-def>; mem:LD4[%k0158] GR32:%vreg899 GR64:%vreg897
5632B		JE_1 <BB#30>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#30 BB#29

5648B	BB#29: derived from LLVM BB %if.then.161
	    Predecessors according to CFG: BB#28
5664B		%vreg1259<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg1259
5680B		%vreg1257<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1257
5696B		MOV32mr %vreg1257, 1, %noreg, 64, %noreg, %vreg1259; mem:ST4[%k0163] GR64:%vreg1257 GR32:%vreg1259
5712B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2

5728B	BB#30: derived from LLVM BB %if.end.164
	    Predecessors according to CFG: BB#28
5744B		%vreg964<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg964
5760B		MOV32mi %vreg964, 1, %noreg, 16, %noreg, 3; mem:ST4[%state_out_len165] GR64:%vreg964
5776B		%vreg962<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg962
5792B		%vreg961<def> = MOV32rm %vreg962, 1, %noreg, 60, %noreg; mem:LD4[%tPos166] GR32:%vreg961 GR64:%vreg962
5808B		%vreg958<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg958
5840B		%vreg958<def,tied1> = ADD64ri32 %vreg958<tied0>, 1096, %EFLAGS<imp-def,dead>; GR64:%vreg958
5856B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5872B		%EDI<def> = COPY %vreg961; GR32:%vreg961
5888B		%RSI<def> = COPY %vreg958; GR64:%vreg958
5904B		CALL64pcrel32 <ga:@BZ2_indexIntoF>, <regmask>, %RSP<imp-use>, %EDI<imp-use>, %RSI<imp-use,kill>, %EAX<imp-def>
5920B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5936B		%vreg955<def> = COPY %EAX<kill>; GR32:%vreg955
5952B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5968B		STACKMAP 3, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
5984B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
6016B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg955:sub_8bit; mem:ST1[%k1] GR32:%vreg955
6032B		%vreg949<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg949
6048B		%vreg947:sub_32bit<def,read-undef> = MOV32rm %vreg949, 1, %noreg, 60, %noreg; mem:LD4[%tPos171] GR64_NOSP:%vreg947 GR64:%vreg949
6080B		%vreg944<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg944
6096B		%vreg943<def> = MOV64rm %vreg944, 1, %noreg, 3160, %noreg; mem:LD8[%ll16173] GR64:%vreg943,%vreg944
6112B		%vreg908<def> = MOVZX32rm16 %vreg943, 2, %vreg947, 0, %noreg; mem:LD2[%arrayidx174] GR32:%vreg908 GR64:%vreg943 GR64_NOSP:%vreg947
6128B		%vreg937<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg937
6144B		%vreg934<def> = MOV32rm %vreg937, 1, %noreg, 60, %noreg; mem:LD4[%tPos176] GR32:%vreg934 GR64:%vreg937
6176B		%vreg934<def,tied1> = SHR32ri %vreg934<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg934
6192B		%vreg932:sub_32bit<def,read-undef> = MOV32rr %vreg934; GR64_NOSP:%vreg932 GR32:%vreg934
6224B		%vreg929<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg929
6240B		%vreg928<def> = MOV64rm %vreg929, 1, %noreg, 3168, %noreg; mem:LD8[%ll4179] GR64:%vreg928,%vreg929
6256B		%vreg912<def> = MOVZX32rm8 %vreg928, 1, %vreg932, 0, %noreg; mem:LD1[%arrayidx180] GR32:%vreg912 GR64:%vreg928 GR64_NOSP:%vreg932
6272B		%vreg922<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg922
6288B		%vreg917<def> = MOV32rm %vreg922, 1, %noreg, 60, %noreg; mem:LD4[%tPos182] GR32:%vreg917 GR64:%vreg922
6320B		%vreg917<def,tied1> = SHL32ri %vreg917<tied0>, 2, %EFLAGS<imp-def,dead>; GR32:%vreg917
6352B		%vreg917<def,tied1> = AND32ri8 %vreg917<tied0>, 4, %EFLAGS<imp-def,dead>; GR32:%vreg917
6368B		%ECX<def> = COPY %vreg917; GR32:%vreg917
6384B		%CL<def> = KILL %ECX<kill>
6416B		%vreg912<def,tied1> = SHR32rCL %vreg912<tied0>, %EFLAGS<imp-def,dead>, %CL<imp-use,kill>; GR32:%vreg912
6448B		%vreg912<def,tied1> = AND32ri8 %vreg912<tied0>, 15, %EFLAGS<imp-def,dead>; GR32:%vreg912
6480B		%vreg912<def,tied1> = SHL32ri %vreg912<tied0>, 16, %EFLAGS<imp-def,dead>; GR32:%vreg912
6512B		%vreg908<def,tied1> = OR32rr %vreg908<tied0>, %vreg912, %EFLAGS<imp-def,dead>; GR32:%vreg908,%vreg912
6528B		%vreg905<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg905
6544B		MOV32mr %vreg905, 1, %noreg, 60, %noreg, %vreg908; mem:ST4[%tPos189] GR64:%vreg905 GR32:%vreg908
6560B		%vreg902<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg902
6576B		CMP32mi8 %vreg902, 1, %noreg, 24, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%rNToGo190] GR64:%vreg902
6592B		JNE_1 <BB#34>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#34 BB#31

6608B	BB#31: derived from LLVM BB %if.then.193
	    Predecessors according to CFG: BB#30
6624B		%vreg982<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg982
6640B		%vreg980<def> = MOVSX64rm32 %vreg982, 1, %noreg, 28, %noreg; mem:LD4[%rTPos194] GR64_NOSP:%vreg980 GR64:%vreg982
6656B		%vreg978<def> = MOV32rm %noreg, 4, %vreg980, <ga:@BZ2_rNums>, %noreg; mem:LD4[%arrayidx196] GR32:%vreg978 GR64_NOSP:%vreg980
6672B		%vreg976<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg976
6688B		MOV32mr %vreg976, 1, %noreg, 24, %noreg, %vreg978; mem:ST4[%rNToGo197] GR64:%vreg976 GR32:%vreg978
6704B		%vreg973<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg973
6720B		%vreg971<def> = MOV32rm %vreg973, 1, %noreg, 28, %noreg; mem:LD4[%rTPos198] GR32:%vreg971 GR64:%vreg973
6752B		%vreg971<def,tied1> = ADD32ri8 %vreg971<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg971
6768B		MOV32mr %vreg973, 1, %noreg, 28, %noreg, %vreg971; mem:ST4[%rTPos198] GR64:%vreg973 GR32:%vreg971
6784B		%vreg967<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg967
6800B		CMP32mi %vreg967, 1, %noreg, 28, %noreg, 512, %EFLAGS<imp-def>; mem:LD4[%rTPos200] GR64:%vreg967
6816B		JNE_1 <BB#33>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#33 BB#32

6832B	BB#32: derived from LLVM BB %if.then.203
	    Predecessors according to CFG: BB#31
6848B		%vreg984<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg984
6864B		MOV32mi %vreg984, 1, %noreg, 28, %noreg, 0; mem:ST4[%rTPos204] GR64:%vreg984
	    Successors according to CFG: BB#33

6880B	BB#33: derived from LLVM BB %if.end.205
	    Predecessors according to CFG: BB#31 BB#32
6896B		JMP_1 <BB#34>
	    Successors according to CFG: BB#34

6912B	BB#34: derived from LLVM BB %if.end.206
	    Predecessors according to CFG: BB#30 BB#33
6928B		%vreg1012<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg1012
6944B		%vreg1011<def> = MOV32ri 1; GR32:%vreg1011
6960B		%vreg1020<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1020
6976B		%vreg1018<def> = MOV32rm %vreg1020, 1, %noreg, 24, %noreg; mem:LD4[%rNToGo207] GR32:%vreg1018 GR64:%vreg1020
7008B		%vreg1018<def,tied1> = ADD32ri8 %vreg1018<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg1018
7024B		MOV32mr %vreg1020, 1, %noreg, 24, %noreg, %vreg1018; mem:ST4[%rNToGo207] GR64:%vreg1020 GR32:%vreg1018
7040B		%vreg1014<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1014
7056B		CMP32mi8 %vreg1014, 1, %noreg, 24, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%rNToGo209] GR64:%vreg1014
7088B		%vreg1012<def,tied1> = CMOVE32rr %vreg1012<tied0>, %vreg1011, %EFLAGS<imp-use,kill>; GR32:%vreg1012,%vreg1011
7104B		%vreg1006<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg1006
7136B		%vreg1006<def,tied1> = XOR32rr %vreg1006<tied0>, %vreg1012, %EFLAGS<imp-def,dead>; GR32:%vreg1006,%vreg1012
7168B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg1006:sub_8bit; mem:ST1[%k1] GR32:%vreg1006
7184B		%vreg1000<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1000
7200B		%vreg998<def> = MOV32rm %vreg1000, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used216] GR32:%vreg998 GR64:%vreg1000
7232B		%vreg998<def,tied1> = ADD32ri8 %vreg998<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg998
7248B		MOV32mr %vreg1000, 1, %noreg, 1092, %noreg, %vreg998; mem:ST4[%nblock_used216] GR64:%vreg1000 GR32:%vreg998
7264B		%vreg994<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg994
7280B		%vreg993<def> = MOV32rm %vreg994, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used218] GR32:%vreg993 GR64:%vreg994
7296B		%vreg991<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg991
7312B		%vreg988<def> = MOV32rm %vreg991, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock219] GR32:%vreg988 GR64:%vreg991
7344B		%vreg988<def,tied1> = ADD32ri8 %vreg988<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg988
7360B		CMP32rr %vreg993, %vreg988, %EFLAGS<imp-def>; GR32:%vreg993,%vreg988
7376B		JNE_1 <BB#36>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#36 BB#35

7392B	BB#35: derived from LLVM BB %if.then.223
	    Predecessors according to CFG: BB#34
7408B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2

7424B	BB#36: derived from LLVM BB %if.end.224
	    Predecessors according to CFG: BB#34
7440B		%vreg1026<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg1026
7456B		%vreg1024<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1024
7472B		CMP32rm %vreg1026, %vreg1024, 1, %noreg, 64, %noreg, %EFLAGS<imp-def>; mem:LD4[%k0226] GR32:%vreg1026 GR64:%vreg1024
7488B		JE_1 <BB#38>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#38 BB#37

7504B	BB#37: derived from LLVM BB %if.then.229
	    Predecessors according to CFG: BB#36
7520B		%vreg1254<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg1254
7536B		%vreg1252<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1252
7552B		MOV32mr %vreg1252, 1, %noreg, 64, %noreg, %vreg1254; mem:ST4[%k0231] GR64:%vreg1252 GR32:%vreg1254
7568B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2

7584B	BB#38: derived from LLVM BB %if.end.232
	    Predecessors according to CFG: BB#36
7600B		%vreg1089<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1089
7616B		%vreg1088<def> = MOV32rm %vreg1089, 1, %noreg, 60, %noreg; mem:LD4[%tPos233] GR32:%vreg1088 GR64:%vreg1089
7632B		%vreg1085<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1085
7664B		%vreg1085<def,tied1> = ADD64ri32 %vreg1085<tied0>, 1096, %EFLAGS<imp-def,dead>; GR64:%vreg1085
7680B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
7696B		%EDI<def> = COPY %vreg1088; GR32:%vreg1088
7712B		%RSI<def> = COPY %vreg1085; GR64:%vreg1085
7728B		CALL64pcrel32 <ga:@BZ2_indexIntoF>, <regmask>, %RSP<imp-use>, %EDI<imp-use>, %RSI<imp-use,kill>, %EAX<imp-def>
7744B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
7760B		%vreg1082<def> = COPY %EAX<kill>; GR32:%vreg1082
7776B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
7792B		STACKMAP 4, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
7808B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
7840B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg1082:sub_8bit; mem:ST1[%k1] GR32:%vreg1082
7856B		%vreg1076<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1076
7872B		%vreg1074:sub_32bit<def,read-undef> = MOV32rm %vreg1076, 1, %noreg, 60, %noreg; mem:LD4[%tPos238] GR64_NOSP:%vreg1074 GR64:%vreg1076
7904B		%vreg1071<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1071
7920B		%vreg1070<def> = MOV64rm %vreg1071, 1, %noreg, 3160, %noreg; mem:LD8[%ll16240] GR64:%vreg1070,%vreg1071
7936B		%vreg1035<def> = MOVZX32rm16 %vreg1070, 2, %vreg1074, 0, %noreg; mem:LD2[%arrayidx241] GR32:%vreg1035 GR64:%vreg1070 GR64_NOSP:%vreg1074
7952B		%vreg1064<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1064
7968B		%vreg1061<def> = MOV32rm %vreg1064, 1, %noreg, 60, %noreg; mem:LD4[%tPos243] GR32:%vreg1061 GR64:%vreg1064
8000B		%vreg1061<def,tied1> = SHR32ri %vreg1061<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg1061
8016B		%vreg1059:sub_32bit<def,read-undef> = MOV32rr %vreg1061; GR64_NOSP:%vreg1059 GR32:%vreg1061
8048B		%vreg1056<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1056
8064B		%vreg1055<def> = MOV64rm %vreg1056, 1, %noreg, 3168, %noreg; mem:LD8[%ll4246] GR64:%vreg1055,%vreg1056
8080B		%vreg1039<def> = MOVZX32rm8 %vreg1055, 1, %vreg1059, 0, %noreg; mem:LD1[%arrayidx247] GR32:%vreg1039 GR64:%vreg1055 GR64_NOSP:%vreg1059
8096B		%vreg1049<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1049
8112B		%vreg1044<def> = MOV32rm %vreg1049, 1, %noreg, 60, %noreg; mem:LD4[%tPos249] GR32:%vreg1044 GR64:%vreg1049
8144B		%vreg1044<def,tied1> = SHL32ri %vreg1044<tied0>, 2, %EFLAGS<imp-def,dead>; GR32:%vreg1044
8176B		%vreg1044<def,tied1> = AND32ri8 %vreg1044<tied0>, 4, %EFLAGS<imp-def,dead>; GR32:%vreg1044
8192B		%ECX<def> = COPY %vreg1044; GR32:%vreg1044
8208B		%CL<def> = KILL %ECX<kill>
8240B		%vreg1039<def,tied1> = SHR32rCL %vreg1039<tied0>, %EFLAGS<imp-def,dead>, %CL<imp-use,kill>; GR32:%vreg1039
8272B		%vreg1039<def,tied1> = AND32ri8 %vreg1039<tied0>, 15, %EFLAGS<imp-def,dead>; GR32:%vreg1039
8304B		%vreg1039<def,tied1> = SHL32ri %vreg1039<tied0>, 16, %EFLAGS<imp-def,dead>; GR32:%vreg1039
8336B		%vreg1035<def,tied1> = OR32rr %vreg1035<tied0>, %vreg1039, %EFLAGS<imp-def,dead>; GR32:%vreg1035,%vreg1039
8352B		%vreg1032<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1032
8368B		MOV32mr %vreg1032, 1, %noreg, 60, %noreg, %vreg1035; mem:ST4[%tPos256] GR64:%vreg1032 GR32:%vreg1035
8384B		%vreg1029<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1029
8400B		CMP32mi8 %vreg1029, 1, %noreg, 24, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%rNToGo257] GR64:%vreg1029
8416B		JNE_1 <BB#42>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#42 BB#39

8432B	BB#39: derived from LLVM BB %if.then.260
	    Predecessors according to CFG: BB#38
8448B		%vreg1107<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1107
8464B		%vreg1105<def> = MOVSX64rm32 %vreg1107, 1, %noreg, 28, %noreg; mem:LD4[%rTPos261] GR64_NOSP:%vreg1105 GR64:%vreg1107
8480B		%vreg1103<def> = MOV32rm %noreg, 4, %vreg1105, <ga:@BZ2_rNums>, %noreg; mem:LD4[%arrayidx263] GR32:%vreg1103 GR64_NOSP:%vreg1105
8496B		%vreg1101<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1101
8512B		MOV32mr %vreg1101, 1, %noreg, 24, %noreg, %vreg1103; mem:ST4[%rNToGo264] GR64:%vreg1101 GR32:%vreg1103
8528B		%vreg1098<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1098
8544B		%vreg1096<def> = MOV32rm %vreg1098, 1, %noreg, 28, %noreg; mem:LD4[%rTPos265] GR32:%vreg1096 GR64:%vreg1098
8576B		%vreg1096<def,tied1> = ADD32ri8 %vreg1096<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg1096
8592B		MOV32mr %vreg1098, 1, %noreg, 28, %noreg, %vreg1096; mem:ST4[%rTPos265] GR64:%vreg1098 GR32:%vreg1096
8608B		%vreg1092<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1092
8624B		CMP32mi %vreg1092, 1, %noreg, 28, %noreg, 512, %EFLAGS<imp-def>; mem:LD4[%rTPos267] GR64:%vreg1092
8640B		JNE_1 <BB#41>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#41 BB#40

8656B	BB#40: derived from LLVM BB %if.then.270
	    Predecessors according to CFG: BB#39
8672B		%vreg1109<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1109
8688B		MOV32mi %vreg1109, 1, %noreg, 28, %noreg, 0; mem:ST4[%rTPos271] GR64:%vreg1109
	    Successors according to CFG: BB#41

8704B	BB#41: derived from LLVM BB %if.end.272
	    Predecessors according to CFG: BB#39 BB#40
8720B		JMP_1 <BB#42>
	    Successors according to CFG: BB#42

8736B	BB#42: derived from LLVM BB %if.end.273
	    Predecessors according to CFG: BB#38 BB#41
8752B		%vreg1197<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg1197
8768B		%vreg1196<def> = MOV32ri 1; GR32:%vreg1196
8784B		%vreg1205<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1205
8800B		%vreg1203<def> = MOV32rm %vreg1205, 1, %noreg, 24, %noreg; mem:LD4[%rNToGo274] GR32:%vreg1203 GR64:%vreg1205
8832B		%vreg1203<def,tied1> = ADD32ri8 %vreg1203<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg1203
8848B		MOV32mr %vreg1205, 1, %noreg, 24, %noreg, %vreg1203; mem:ST4[%rNToGo274] GR64:%vreg1205 GR32:%vreg1203
8864B		%vreg1199<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1199
8880B		CMP32mi8 %vreg1199, 1, %noreg, 24, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%rNToGo276] GR64:%vreg1199
8912B		%vreg1197<def,tied1> = CMOVE32rr %vreg1197<tied0>, %vreg1196, %EFLAGS<imp-use,kill>; GR32:%vreg1197,%vreg1196
8928B		%vreg1191<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg1191
8960B		%vreg1191<def,tied1> = XOR32rr %vreg1191<tied0>, %vreg1197, %EFLAGS<imp-def,dead>; GR32:%vreg1191,%vreg1197
8992B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg1191:sub_8bit; mem:ST1[%k1] GR32:%vreg1191
9008B		%vreg1185<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1185
9024B		%vreg1183<def> = MOV32rm %vreg1185, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used283] GR32:%vreg1183 GR64:%vreg1185
9056B		%vreg1183<def,tied1> = ADD32ri8 %vreg1183<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg1183
9072B		MOV32mr %vreg1185, 1, %noreg, 1092, %noreg, %vreg1183; mem:ST4[%nblock_used283] GR64:%vreg1185 GR32:%vreg1183
9088B		%vreg1177<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg1177
9120B		%vreg1177<def,tied1> = ADD32ri8 %vreg1177<tied0>, 4, %EFLAGS<imp-def,dead>; GR32:%vreg1177
9136B		%vreg1175<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1175
9152B		MOV32mr %vreg1175, 1, %noreg, 16, %noreg, %vreg1177; mem:ST4[%state_out_len287] GR64:%vreg1175 GR32:%vreg1177
9168B		%vreg1172<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1172
9184B		%vreg1171<def> = MOV32rm %vreg1172, 1, %noreg, 60, %noreg; mem:LD4[%tPos288] GR32:%vreg1171 GR64:%vreg1172
9200B		%vreg1168<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1168
9232B		%vreg1168<def,tied1> = ADD64ri32 %vreg1168<tied0>, 1096, %EFLAGS<imp-def,dead>; GR64:%vreg1168
9248B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
9264B		%EDI<def> = COPY %vreg1171; GR32:%vreg1171
9280B		%RSI<def> = COPY %vreg1168; GR64:%vreg1168
9296B		CALL64pcrel32 <ga:@BZ2_indexIntoF>, <regmask>, %RSP<imp-use>, %EDI<imp-use>, %RSI<imp-use,kill>, %EAX<imp-def>
9312B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
9328B		%vreg1165<def> = COPY %EAX<kill>; GR32:%vreg1165
9344B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
9360B		STACKMAP 5, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
9376B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
9392B		%vreg1162<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1162
9408B		MOV32mr %vreg1162, 1, %noreg, 64, %noreg, %vreg1165; mem:ST4[%k0292] GR64:%vreg1162 GR32:%vreg1165
9424B		%vreg1159<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1159
9440B		%vreg1157:sub_32bit<def,read-undef> = MOV32rm %vreg1159, 1, %noreg, 60, %noreg; mem:LD4[%tPos293] GR64_NOSP:%vreg1157 GR64:%vreg1159
9472B		%vreg1154<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1154
9488B		%vreg1153<def> = MOV64rm %vreg1154, 1, %noreg, 3160, %noreg; mem:LD8[%ll16295] GR64:%vreg1153,%vreg1154
9504B		%vreg1118<def> = MOVZX32rm16 %vreg1153, 2, %vreg1157, 0, %noreg; mem:LD2[%arrayidx296] GR32:%vreg1118 GR64:%vreg1153 GR64_NOSP:%vreg1157
9520B		%vreg1147<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1147
9536B		%vreg1144<def> = MOV32rm %vreg1147, 1, %noreg, 60, %noreg; mem:LD4[%tPos298] GR32:%vreg1144 GR64:%vreg1147
9568B		%vreg1144<def,tied1> = SHR32ri %vreg1144<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg1144
9584B		%vreg1142:sub_32bit<def,read-undef> = MOV32rr %vreg1144; GR64_NOSP:%vreg1142 GR32:%vreg1144
9616B		%vreg1139<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1139
9632B		%vreg1138<def> = MOV64rm %vreg1139, 1, %noreg, 3168, %noreg; mem:LD8[%ll4301] GR64:%vreg1138,%vreg1139
9648B		%vreg1122<def> = MOVZX32rm8 %vreg1138, 1, %vreg1142, 0, %noreg; mem:LD1[%arrayidx302] GR32:%vreg1122 GR64:%vreg1138 GR64_NOSP:%vreg1142
9664B		%vreg1132<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1132
9680B		%vreg1127<def> = MOV32rm %vreg1132, 1, %noreg, 60, %noreg; mem:LD4[%tPos304] GR32:%vreg1127 GR64:%vreg1132
9712B		%vreg1127<def,tied1> = SHL32ri %vreg1127<tied0>, 2, %EFLAGS<imp-def,dead>; GR32:%vreg1127
9744B		%vreg1127<def,tied1> = AND32ri8 %vreg1127<tied0>, 4, %EFLAGS<imp-def,dead>; GR32:%vreg1127
9760B		%ECX<def> = COPY %vreg1127; GR32:%vreg1127
9776B		%CL<def> = KILL %ECX<kill>
9808B		%vreg1122<def,tied1> = SHR32rCL %vreg1122<tied0>, %EFLAGS<imp-def,dead>, %CL<imp-use,kill>; GR32:%vreg1122
9840B		%vreg1122<def,tied1> = AND32ri8 %vreg1122<tied0>, 15, %EFLAGS<imp-def,dead>; GR32:%vreg1122
9872B		%vreg1122<def,tied1> = SHL32ri %vreg1122<tied0>, 16, %EFLAGS<imp-def,dead>; GR32:%vreg1122
9904B		%vreg1118<def,tied1> = OR32rr %vreg1118<tied0>, %vreg1122, %EFLAGS<imp-def,dead>; GR32:%vreg1118,%vreg1122
9920B		%vreg1115<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1115
9936B		MOV32mr %vreg1115, 1, %noreg, 60, %noreg, %vreg1118; mem:ST4[%tPos311] GR64:%vreg1115 GR32:%vreg1118
9952B		%vreg1112<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1112
9968B		CMP32mi8 %vreg1112, 1, %noreg, 24, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%rNToGo312] GR64:%vreg1112
9984B		JNE_1 <BB#46>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#46 BB#43

10000B	BB#43: derived from LLVM BB %if.then.315
	    Predecessors according to CFG: BB#42
10016B		%vreg1223<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1223
10032B		%vreg1221<def> = MOVSX64rm32 %vreg1223, 1, %noreg, 28, %noreg; mem:LD4[%rTPos316] GR64_NOSP:%vreg1221 GR64:%vreg1223
10048B		%vreg1219<def> = MOV32rm %noreg, 4, %vreg1221, <ga:@BZ2_rNums>, %noreg; mem:LD4[%arrayidx318] GR32:%vreg1219 GR64_NOSP:%vreg1221
10064B		%vreg1217<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1217
10080B		MOV32mr %vreg1217, 1, %noreg, 24, %noreg, %vreg1219; mem:ST4[%rNToGo319] GR64:%vreg1217 GR32:%vreg1219
10096B		%vreg1214<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1214
10112B		%vreg1212<def> = MOV32rm %vreg1214, 1, %noreg, 28, %noreg; mem:LD4[%rTPos320] GR32:%vreg1212 GR64:%vreg1214
10144B		%vreg1212<def,tied1> = ADD32ri8 %vreg1212<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg1212
10160B		MOV32mr %vreg1214, 1, %noreg, 28, %noreg, %vreg1212; mem:ST4[%rTPos320] GR64:%vreg1214 GR32:%vreg1212
10176B		%vreg1208<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1208
10192B		CMP32mi %vreg1208, 1, %noreg, 28, %noreg, 512, %EFLAGS<imp-def>; mem:LD4[%rTPos322] GR64:%vreg1208
10208B		JNE_1 <BB#45>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#45 BB#44

10224B	BB#44: derived from LLVM BB %if.then.325
	    Predecessors according to CFG: BB#43
10240B		%vreg1225<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1225
10256B		MOV32mi %vreg1225, 1, %noreg, 28, %noreg, 0; mem:ST4[%rTPos326] GR64:%vreg1225
	    Successors according to CFG: BB#45

10272B	BB#45: derived from LLVM BB %if.end.327
	    Predecessors according to CFG: BB#43 BB#44
10288B		JMP_1 <BB#46>
	    Successors according to CFG: BB#46

10304B	BB#46: derived from LLVM BB %if.end.328
	    Predecessors according to CFG: BB#42 BB#45
10320B		%vreg1236<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg1236
10336B		%vreg1240<def> = MOV32ri 1; GR32:%vreg1240
10352B		%vreg1249<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1249
10368B		%vreg1247<def> = MOV32rm %vreg1249, 1, %noreg, 24, %noreg; mem:LD4[%rNToGo329] GR32:%vreg1247 GR64:%vreg1249
10400B		%vreg1247<def,tied1> = ADD32ri8 %vreg1247<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg1247
10416B		MOV32mr %vreg1249, 1, %noreg, 24, %noreg, %vreg1247; mem:ST4[%rNToGo329] GR64:%vreg1249 GR32:%vreg1247
10432B		%vreg1243<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1243
10448B		CMP32mi8 %vreg1243, 1, %noreg, 24, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%rNToGo331] GR64:%vreg1243
10480B		%vreg1236<def,tied1> = CMOVE32rr %vreg1236<tied0>, %vreg1240, %EFLAGS<imp-use,kill>; GR32:%vreg1236,%vreg1240
10496B		%vreg1237<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1237
10528B		%vreg1236<def,tied1> = XOR32rm %vreg1236<tied0>, %vreg1237, 1, %noreg, 64, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%k0335] GR32:%vreg1236 GR64:%vreg1237
10544B		MOV32mr %vreg1237, 1, %noreg, 64, %noreg, %vreg1236; mem:ST4[%k0335] GR64:%vreg1237 GR32:%vreg1236
10560B		%vreg1231<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1231
10576B		%vreg1229<def> = MOV32rm %vreg1231, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used337] GR32:%vreg1229 GR64:%vreg1231
10608B		%vreg1229<def,tied1> = ADD32ri8 %vreg1229<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg1229
10624B		MOV32mr %vreg1231, 1, %noreg, 1092, %noreg, %vreg1229; mem:ST4[%nblock_used337] GR64:%vreg1231 GR32:%vreg1229
10640B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2

10656B	BB#47: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#0
10672B		JMP_1 <BB#48>
	    Successors according to CFG: BB#48

10688B	BB#48: derived from LLVM BB %while.body.339
	    Predecessors according to CFG: BB#47 BB#72 BB#71 BB#69 BB#67 BB#65 BB#63 BB#61
10704B		JMP_1 <BB#49>
	    Successors according to CFG: BB#49

10720B	BB#49: derived from LLVM BB %while.body.341
	    Predecessors according to CFG: BB#48 BB#55
10736B		%vreg12<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg12
10752B		%vreg11<def> = MOV64rm %vreg12, 1, %noreg, 0, %noreg; mem:LD8[%strm342] GR64:%vreg11,%vreg12
10768B		CMP32mi8 %vreg11, 1, %noreg, 32, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_out343] GR64:%vreg11
10784B		JNE_1 <BB#51>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#51 BB#50

10800B	BB#50: derived from LLVM BB %if.then.346
	    Predecessors according to CFG: BB#49
10816B		MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST1[%retval]
10832B		JMP_1 <BB#73>
	    Successors according to CFG: BB#73

10848B	BB#51: derived from LLVM BB %if.end.347
	    Predecessors according to CFG: BB#49
10864B		%vreg15<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg15
10880B		CMP32mi8 %vreg15, 1, %noreg, 16, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%state_out_len348] GR64:%vreg15
10896B		JNE_1 <BB#53>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#53 BB#52

10912B	BB#52: derived from LLVM BB %if.then.351
	    Predecessors according to CFG: BB#51
10928B		JMP_1 <BB#56>
	    Successors according to CFG: BB#56

10944B	BB#53: derived from LLVM BB %if.end.352
	    Predecessors according to CFG: BB#51
10960B		%vreg87<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg87
10976B		%vreg86<def> = MOV8rm %vreg87, 1, %noreg, 12, %noreg; mem:LD1[%state_out_ch353] GR8:%vreg86 GR64:%vreg87
10992B		%vreg84<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg84
11008B		%vreg83<def> = MOV64rm %vreg84, 1, %noreg, 0, %noreg; mem:LD8[%strm354] GR64:%vreg83,%vreg84
11024B		%vreg81<def> = MOV64rm %vreg83, 1, %noreg, 24, %noreg; mem:LD8[%next_out355] GR64:%vreg81,%vreg83
11040B		MOV8mr %vreg81, 1, %noreg, 0, %noreg, %vreg86; mem:ST1[%261] GR64:%vreg81 GR8:%vreg86
11056B		%vreg77<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg77
11072B		%vreg56<def> = MOV32rm %vreg77, 1, %noreg, 3184, %noreg; mem:LD4[%calculatedBlockCRC356] GR32:%vreg56 GR64:%vreg77
11104B		%vreg56<def,tied1> = SHL32ri %vreg56<tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg56
11120B		%vreg72<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg72
11136B		%vreg63<def> = MOV32rm %vreg72, 1, %noreg, 3184, %noreg; mem:LD4[%calculatedBlockCRC358] GR32:%vreg63 GR64:%vreg72
11168B		%vreg63<def,tied1> = SHR32ri %vreg63<tied0>, 24, %EFLAGS<imp-def,dead>; GR32:%vreg63
11184B		%vreg67<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg67
11200B		%vreg65<def> = MOVZX32rm8 %vreg67, 1, %noreg, 12, %noreg; mem:LD1[%state_out_ch360] GR32:%vreg65 GR64:%vreg67
11232B		%vreg63<def,tied1> = XOR32rr %vreg63<tied0>, %vreg65, %EFLAGS<imp-def,dead>; GR32:%vreg63,%vreg65
11248B		%vreg60:sub_32bit<def,read-undef> = MOV32rr %vreg63; GR64_NOSP:%vreg60 GR32:%vreg63
11296B		%vreg56<def,tied1> = XOR32rm %vreg56<tied0>, %noreg, 4, %vreg60, <ga:@BZ2_crc32Table>, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%arrayidx364] GR32:%vreg56 GR64_NOSP:%vreg60
11312B		%vreg53<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg53
11328B		MOV32mr %vreg53, 1, %noreg, 3184, %noreg, %vreg56; mem:ST4[%calculatedBlockCRC366] GR64:%vreg53 GR32:%vreg56
11344B		%vreg50<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg50
11360B		%vreg48<def> = MOV32rm %vreg50, 1, %noreg, 16, %noreg; mem:LD4[%state_out_len367] GR32:%vreg48 GR64:%vreg50
11392B		%vreg48<def,tied1> = ADD32ri8 %vreg48<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg48
11408B		MOV32mr %vreg50, 1, %noreg, 16, %noreg, %vreg48; mem:ST4[%state_out_len367] GR64:%vreg50 GR32:%vreg48
11424B		%vreg44<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg44
11440B		%vreg43<def> = MOV64rm %vreg44, 1, %noreg, 0, %noreg; mem:LD8[%strm369] GR64:%vreg43,%vreg44
11456B		%vreg40<def> = MOV64rm %vreg43, 1, %noreg, 24, %noreg; mem:LD8[%next_out370] GR64:%vreg40,%vreg43
11488B		%vreg40<def,tied1> = ADD64ri8 %vreg40<tied0>, 1, %EFLAGS<imp-def,dead>; GR64:%vreg40
11504B		MOV64mr %vreg43, 1, %noreg, 24, %noreg, %vreg40; mem:ST8[%next_out370] GR64:%vreg43,%vreg40
11520B		%vreg36<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg36
11536B		%vreg35<def> = MOV64rm %vreg36, 1, %noreg, 0, %noreg; mem:LD8[%strm372] GR64:%vreg35,%vreg36
11552B		%vreg32<def> = MOV32rm %vreg35, 1, %noreg, 32, %noreg; mem:LD4[%avail_out373] GR32:%vreg32 GR64:%vreg35
11584B		%vreg32<def,tied1> = ADD32ri8 %vreg32<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg32
11600B		MOV32mr %vreg35, 1, %noreg, 32, %noreg, %vreg32; mem:ST4[%avail_out373] GR64:%vreg35 GR32:%vreg32
11616B		%vreg28<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg28
11632B		%vreg27<def> = MOV64rm %vreg28, 1, %noreg, 0, %noreg; mem:LD8[%strm375] GR64:%vreg27,%vreg28
11648B		%vreg24<def> = MOV32rm %vreg27, 1, %noreg, 36, %noreg; mem:LD4[%total_out_lo32376] GR32:%vreg24 GR64:%vreg27
11680B		%vreg24<def,tied1> = ADD32ri8 %vreg24<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg24
11696B		MOV32mr %vreg27, 1, %noreg, 36, %noreg, %vreg24; mem:ST4[%total_out_lo32376] GR64:%vreg27 GR32:%vreg24
11712B		%vreg20<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg20
11728B		%vreg19<def> = MOV64rm %vreg20, 1, %noreg, 0, %noreg; mem:LD8[%strm378] GR64:%vreg19,%vreg20
11744B		CMP32mi8 %vreg19, 1, %noreg, 36, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%total_out_lo32379] GR64:%vreg19
11760B		JNE_1 <BB#55>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#55 BB#54

11776B	BB#54: derived from LLVM BB %if.then.382
	    Predecessors according to CFG: BB#53
11792B		%vreg95<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg95
11808B		%vreg94<def> = MOV64rm %vreg95, 1, %noreg, 0, %noreg; mem:LD8[%strm383] GR64:%vreg94,%vreg95
11824B		%vreg91<def> = MOV32rm %vreg94, 1, %noreg, 40, %noreg; mem:LD4[%total_out_hi32384] GR32:%vreg91 GR64:%vreg94
11856B		%vreg91<def,tied1> = ADD32ri8 %vreg91<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg91
11872B		MOV32mr %vreg94, 1, %noreg, 40, %noreg, %vreg91; mem:ST4[%total_out_hi32384] GR64:%vreg94 GR32:%vreg91
	    Successors according to CFG: BB#55

11888B	BB#55: derived from LLVM BB %if.end.386
	    Predecessors according to CFG: BB#53 BB#54
11904B		JMP_1 <BB#49>
	    Successors according to CFG: BB#49

11920B	BB#56: derived from LLVM BB %while.end.387
	    Predecessors according to CFG: BB#52
11936B		%vreg105<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg105
11952B		%vreg104<def> = MOV32rm %vreg105, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used388] GR32:%vreg104 GR64:%vreg105
11968B		%vreg102<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg102
11984B		%vreg99<def> = MOV32rm %vreg102, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock389] GR32:%vreg99 GR64:%vreg102
12016B		%vreg99<def,tied1> = ADD32ri8 %vreg99<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg99
12032B		CMP32rr %vreg104, %vreg99, %EFLAGS<imp-def>; GR32:%vreg104,%vreg99
12048B		JNE_1 <BB#58>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#58 BB#57

12064B	BB#57: derived from LLVM BB %if.then.393
	    Predecessors according to CFG: BB#56
12080B		MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST1[%retval]
12096B		JMP_1 <BB#73>
	    Successors according to CFG: BB#73

12112B	BB#58: derived from LLVM BB %if.end.394
	    Predecessors according to CFG: BB#56
12128B		%vreg115<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg115
12144B		%vreg114<def> = MOV32rm %vreg115, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used395] GR32:%vreg114 GR64:%vreg115
12160B		%vreg112<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg112
12176B		%vreg109<def> = MOV32rm %vreg112, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock396] GR32:%vreg109 GR64:%vreg112
12208B		%vreg109<def,tied1> = ADD32ri8 %vreg109<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg109
12224B		CMP32rr %vreg114, %vreg109, %EFLAGS<imp-def>; GR32:%vreg114,%vreg109
12240B		JLE_1 <BB#60>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#60 BB#59

12256B	BB#59: derived from LLVM BB %if.then.400
	    Predecessors according to CFG: BB#58
12272B		MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 1; mem:ST1[%retval]
12288B		JMP_1 <BB#73>
	    Successors according to CFG: BB#73

12304B	BB#60: derived from LLVM BB %if.end.401
	    Predecessors according to CFG: BB#58
12320B		%vreg201<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg201
12336B		MOV32mi %vreg201, 1, %noreg, 16, %noreg, 1; mem:ST4[%state_out_len402] GR64:%vreg201
12352B		%vreg199<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg199
12368B		%vreg198<def> = MOV32rm %vreg199, 1, %noreg, 64, %noreg; mem:LD4[%k0403] GR32:%vreg198 GR64:%vreg199
12400B		%vreg194<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg194
12416B		MOV8mr %vreg194, 1, %noreg, 12, %noreg, %vreg198:sub_8bit; mem:ST1[%state_out_ch405] GR64:%vreg194 GR32:%vreg198
12432B		%vreg191<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg191
12448B		%vreg190<def> = MOV32rm %vreg191, 1, %noreg, 60, %noreg; mem:LD4[%tPos406] GR32:%vreg190 GR64:%vreg191
12464B		%vreg187<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg187
12496B		%vreg187<def,tied1> = ADD64ri32 %vreg187<tied0>, 1096, %EFLAGS<imp-def,dead>; GR64:%vreg187
12512B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
12528B		%EDI<def> = COPY %vreg190; GR32:%vreg190
12544B		%RSI<def> = COPY %vreg187; GR64:%vreg187
12560B		CALL64pcrel32 <ga:@BZ2_indexIntoF>, <regmask>, %RSP<imp-use>, %EDI<imp-use>, %RSI<imp-use,kill>, %EAX<imp-def>
12576B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
12592B		%vreg184<def> = COPY %EAX<kill>; GR32:%vreg184
12608B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
12624B		STACKMAP 6, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
12640B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
12672B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg184:sub_8bit; mem:ST1[%k1] GR32:%vreg184
12688B		%vreg178<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg178
12704B		%vreg176:sub_32bit<def,read-undef> = MOV32rm %vreg178, 1, %noreg, 60, %noreg; mem:LD4[%tPos411] GR64_NOSP:%vreg176 GR64:%vreg178
12736B		%vreg173<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg173
12752B		%vreg172<def> = MOV64rm %vreg173, 1, %noreg, 3160, %noreg; mem:LD8[%ll16413] GR64:%vreg172,%vreg173
12768B		%vreg137<def> = MOVZX32rm16 %vreg172, 2, %vreg176, 0, %noreg; mem:LD2[%arrayidx414] GR32:%vreg137 GR64:%vreg172 GR64_NOSP:%vreg176
12784B		%vreg166<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg166
12800B		%vreg163<def> = MOV32rm %vreg166, 1, %noreg, 60, %noreg; mem:LD4[%tPos416] GR32:%vreg163 GR64:%vreg166
12832B		%vreg163<def,tied1> = SHR32ri %vreg163<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg163
12848B		%vreg161:sub_32bit<def,read-undef> = MOV32rr %vreg163; GR64_NOSP:%vreg161 GR32:%vreg163
12880B		%vreg158<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg158
12896B		%vreg157<def> = MOV64rm %vreg158, 1, %noreg, 3168, %noreg; mem:LD8[%ll4419] GR64:%vreg157,%vreg158
12912B		%vreg141<def> = MOVZX32rm8 %vreg157, 1, %vreg161, 0, %noreg; mem:LD1[%arrayidx420] GR32:%vreg141 GR64:%vreg157 GR64_NOSP:%vreg161
12928B		%vreg151<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg151
12944B		%vreg146<def> = MOV32rm %vreg151, 1, %noreg, 60, %noreg; mem:LD4[%tPos422] GR32:%vreg146 GR64:%vreg151
12976B		%vreg146<def,tied1> = SHL32ri %vreg146<tied0>, 2, %EFLAGS<imp-def,dead>; GR32:%vreg146
13008B		%vreg146<def,tied1> = AND32ri8 %vreg146<tied0>, 4, %EFLAGS<imp-def,dead>; GR32:%vreg146
13024B		%ECX<def> = COPY %vreg146; GR32:%vreg146
13040B		%CL<def> = KILL %ECX<kill>
13072B		%vreg141<def,tied1> = SHR32rCL %vreg141<tied0>, %EFLAGS<imp-def,dead>, %CL<imp-use,kill>; GR32:%vreg141
13104B		%vreg141<def,tied1> = AND32ri8 %vreg141<tied0>, 15, %EFLAGS<imp-def,dead>; GR32:%vreg141
13136B		%vreg141<def,tied1> = SHL32ri %vreg141<tied0>, 16, %EFLAGS<imp-def,dead>; GR32:%vreg141
13168B		%vreg137<def,tied1> = OR32rr %vreg137<tied0>, %vreg141, %EFLAGS<imp-def,dead>; GR32:%vreg137,%vreg141
13184B		%vreg134<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg134
13200B		MOV32mr %vreg134, 1, %noreg, 60, %noreg, %vreg137; mem:ST4[%tPos429] GR64:%vreg134 GR32:%vreg137
13216B		%vreg131<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg131
13232B		%vreg129<def> = MOV32rm %vreg131, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used430] GR32:%vreg129 GR64:%vreg131
13264B		%vreg129<def,tied1> = ADD32ri8 %vreg129<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg129
13280B		MOV32mr %vreg131, 1, %noreg, 1092, %noreg, %vreg129; mem:ST4[%nblock_used430] GR64:%vreg131 GR32:%vreg129
13296B		%vreg125<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg125
13312B		%vreg124<def> = MOV32rm %vreg125, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used432] GR32:%vreg124 GR64:%vreg125
13328B		%vreg122<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg122
13344B		%vreg119<def> = MOV32rm %vreg122, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock433] GR32:%vreg119 GR64:%vreg122
13376B		%vreg119<def,tied1> = ADD32ri8 %vreg119<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg119
13392B		CMP32rr %vreg124, %vreg119, %EFLAGS<imp-def>; GR32:%vreg124,%vreg119
13408B		JNE_1 <BB#62>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#62 BB#61

13424B	BB#61: derived from LLVM BB %if.then.437
	    Predecessors according to CFG: BB#60
13440B		JMP_1 <BB#48>
	    Successors according to CFG: BB#48

13456B	BB#62: derived from LLVM BB %if.end.438
	    Predecessors according to CFG: BB#60
13472B		%vreg207<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg207
13488B		%vreg205<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg205
13504B		CMP32rm %vreg207, %vreg205, 1, %noreg, 64, %noreg, %EFLAGS<imp-def>; mem:LD4[%k0440] GR32:%vreg207 GR64:%vreg205
13520B		JE_1 <BB#64>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#64 BB#63

13536B	BB#63: derived from LLVM BB %if.then.443
	    Predecessors according to CFG: BB#62
13552B		%vreg529<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg529
13568B		%vreg527<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg527
13584B		MOV32mr %vreg527, 1, %noreg, 64, %noreg, %vreg529; mem:ST4[%k0445] GR64:%vreg527 GR32:%vreg529
13600B		JMP_1 <BB#48>
	    Successors according to CFG: BB#48

13616B	BB#64: derived from LLVM BB %if.end.446
	    Predecessors according to CFG: BB#62
13632B		%vreg285<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg285
13648B		MOV32mi %vreg285, 1, %noreg, 16, %noreg, 2; mem:ST4[%state_out_len447] GR64:%vreg285
13664B		%vreg283<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg283
13680B		%vreg282<def> = MOV32rm %vreg283, 1, %noreg, 60, %noreg; mem:LD4[%tPos448] GR32:%vreg282 GR64:%vreg283
13696B		%vreg279<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg279
13728B		%vreg279<def,tied1> = ADD64ri32 %vreg279<tied0>, 1096, %EFLAGS<imp-def,dead>; GR64:%vreg279
13744B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
13760B		%EDI<def> = COPY %vreg282; GR32:%vreg282
13776B		%RSI<def> = COPY %vreg279; GR64:%vreg279
13792B		CALL64pcrel32 <ga:@BZ2_indexIntoF>, <regmask>, %RSP<imp-use>, %EDI<imp-use>, %RSI<imp-use,kill>, %EAX<imp-def>
13808B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
13824B		%vreg276<def> = COPY %EAX<kill>; GR32:%vreg276
13840B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
13856B		STACKMAP 7, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
13872B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
13904B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg276:sub_8bit; mem:ST1[%k1] GR32:%vreg276
13920B		%vreg270<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg270
13936B		%vreg268:sub_32bit<def,read-undef> = MOV32rm %vreg270, 1, %noreg, 60, %noreg; mem:LD4[%tPos453] GR64_NOSP:%vreg268 GR64:%vreg270
13968B		%vreg265<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg265
13984B		%vreg264<def> = MOV64rm %vreg265, 1, %noreg, 3160, %noreg; mem:LD8[%ll16455] GR64:%vreg264,%vreg265
14000B		%vreg229<def> = MOVZX32rm16 %vreg264, 2, %vreg268, 0, %noreg; mem:LD2[%arrayidx456] GR32:%vreg229 GR64:%vreg264 GR64_NOSP:%vreg268
14016B		%vreg258<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg258
14032B		%vreg255<def> = MOV32rm %vreg258, 1, %noreg, 60, %noreg; mem:LD4[%tPos458] GR32:%vreg255 GR64:%vreg258
14064B		%vreg255<def,tied1> = SHR32ri %vreg255<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg255
14080B		%vreg253:sub_32bit<def,read-undef> = MOV32rr %vreg255; GR64_NOSP:%vreg253 GR32:%vreg255
14112B		%vreg250<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg250
14128B		%vreg249<def> = MOV64rm %vreg250, 1, %noreg, 3168, %noreg; mem:LD8[%ll4461] GR64:%vreg249,%vreg250
14144B		%vreg233<def> = MOVZX32rm8 %vreg249, 1, %vreg253, 0, %noreg; mem:LD1[%arrayidx462] GR32:%vreg233 GR64:%vreg249 GR64_NOSP:%vreg253
14160B		%vreg243<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg243
14176B		%vreg238<def> = MOV32rm %vreg243, 1, %noreg, 60, %noreg; mem:LD4[%tPos464] GR32:%vreg238 GR64:%vreg243
14208B		%vreg238<def,tied1> = SHL32ri %vreg238<tied0>, 2, %EFLAGS<imp-def,dead>; GR32:%vreg238
14240B		%vreg238<def,tied1> = AND32ri8 %vreg238<tied0>, 4, %EFLAGS<imp-def,dead>; GR32:%vreg238
14256B		%ECX<def> = COPY %vreg238; GR32:%vreg238
14272B		%CL<def> = KILL %ECX<kill>
14304B		%vreg233<def,tied1> = SHR32rCL %vreg233<tied0>, %EFLAGS<imp-def,dead>, %CL<imp-use,kill>; GR32:%vreg233
14336B		%vreg233<def,tied1> = AND32ri8 %vreg233<tied0>, 15, %EFLAGS<imp-def,dead>; GR32:%vreg233
14368B		%vreg233<def,tied1> = SHL32ri %vreg233<tied0>, 16, %EFLAGS<imp-def,dead>; GR32:%vreg233
14400B		%vreg229<def,tied1> = OR32rr %vreg229<tied0>, %vreg233, %EFLAGS<imp-def,dead>; GR32:%vreg229,%vreg233
14416B		%vreg226<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg226
14432B		MOV32mr %vreg226, 1, %noreg, 60, %noreg, %vreg229; mem:ST4[%tPos471] GR64:%vreg226 GR32:%vreg229
14448B		%vreg223<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg223
14464B		%vreg221<def> = MOV32rm %vreg223, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used472] GR32:%vreg221 GR64:%vreg223
14496B		%vreg221<def,tied1> = ADD32ri8 %vreg221<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg221
14512B		MOV32mr %vreg223, 1, %noreg, 1092, %noreg, %vreg221; mem:ST4[%nblock_used472] GR64:%vreg223 GR32:%vreg221
14528B		%vreg217<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg217
14544B		%vreg216<def> = MOV32rm %vreg217, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used474] GR32:%vreg216 GR64:%vreg217
14560B		%vreg214<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg214
14576B		%vreg211<def> = MOV32rm %vreg214, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock475] GR32:%vreg211 GR64:%vreg214
14608B		%vreg211<def,tied1> = ADD32ri8 %vreg211<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg211
14624B		CMP32rr %vreg216, %vreg211, %EFLAGS<imp-def>; GR32:%vreg216,%vreg211
14640B		JNE_1 <BB#66>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#66 BB#65

14656B	BB#65: derived from LLVM BB %if.then.479
	    Predecessors according to CFG: BB#64
14672B		JMP_1 <BB#48>
	    Successors according to CFG: BB#48

14688B	BB#66: derived from LLVM BB %if.end.480
	    Predecessors according to CFG: BB#64
14704B		%vreg291<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg291
14720B		%vreg289<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg289
14736B		CMP32rm %vreg291, %vreg289, 1, %noreg, 64, %noreg, %EFLAGS<imp-def>; mem:LD4[%k0482] GR32:%vreg291 GR64:%vreg289
14752B		JE_1 <BB#68>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#68 BB#67

14768B	BB#67: derived from LLVM BB %if.then.485
	    Predecessors according to CFG: BB#66
14784B		%vreg524<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg524
14800B		%vreg522<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg522
14816B		MOV32mr %vreg522, 1, %noreg, 64, %noreg, %vreg524; mem:ST4[%k0487] GR64:%vreg522 GR32:%vreg524
14832B		JMP_1 <BB#48>
	    Successors according to CFG: BB#48

14848B	BB#68: derived from LLVM BB %if.end.488
	    Predecessors according to CFG: BB#66
14864B		%vreg369<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg369
14880B		MOV32mi %vreg369, 1, %noreg, 16, %noreg, 3; mem:ST4[%state_out_len489] GR64:%vreg369
14896B		%vreg367<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg367
14912B		%vreg366<def> = MOV32rm %vreg367, 1, %noreg, 60, %noreg; mem:LD4[%tPos490] GR32:%vreg366 GR64:%vreg367
14928B		%vreg363<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg363
14960B		%vreg363<def,tied1> = ADD64ri32 %vreg363<tied0>, 1096, %EFLAGS<imp-def,dead>; GR64:%vreg363
14976B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
14992B		%EDI<def> = COPY %vreg366; GR32:%vreg366
15008B		%RSI<def> = COPY %vreg363; GR64:%vreg363
15024B		CALL64pcrel32 <ga:@BZ2_indexIntoF>, <regmask>, %RSP<imp-use>, %EDI<imp-use>, %RSI<imp-use,kill>, %EAX<imp-def>
15040B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
15056B		%vreg360<def> = COPY %EAX<kill>; GR32:%vreg360
15072B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
15088B		STACKMAP 8, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
15104B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
15136B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg360:sub_8bit; mem:ST1[%k1] GR32:%vreg360
15152B		%vreg354<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg354
15168B		%vreg352:sub_32bit<def,read-undef> = MOV32rm %vreg354, 1, %noreg, 60, %noreg; mem:LD4[%tPos495] GR64_NOSP:%vreg352 GR64:%vreg354
15200B		%vreg349<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg349
15216B		%vreg348<def> = MOV64rm %vreg349, 1, %noreg, 3160, %noreg; mem:LD8[%ll16497] GR64:%vreg348,%vreg349
15232B		%vreg313<def> = MOVZX32rm16 %vreg348, 2, %vreg352, 0, %noreg; mem:LD2[%arrayidx498] GR32:%vreg313 GR64:%vreg348 GR64_NOSP:%vreg352
15248B		%vreg342<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg342
15264B		%vreg339<def> = MOV32rm %vreg342, 1, %noreg, 60, %noreg; mem:LD4[%tPos500] GR32:%vreg339 GR64:%vreg342
15296B		%vreg339<def,tied1> = SHR32ri %vreg339<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg339
15312B		%vreg337:sub_32bit<def,read-undef> = MOV32rr %vreg339; GR64_NOSP:%vreg337 GR32:%vreg339
15344B		%vreg334<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg334
15360B		%vreg333<def> = MOV64rm %vreg334, 1, %noreg, 3168, %noreg; mem:LD8[%ll4503] GR64:%vreg333,%vreg334
15376B		%vreg317<def> = MOVZX32rm8 %vreg333, 1, %vreg337, 0, %noreg; mem:LD1[%arrayidx504] GR32:%vreg317 GR64:%vreg333 GR64_NOSP:%vreg337
15392B		%vreg327<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg327
15408B		%vreg322<def> = MOV32rm %vreg327, 1, %noreg, 60, %noreg; mem:LD4[%tPos506] GR32:%vreg322 GR64:%vreg327
15440B		%vreg322<def,tied1> = SHL32ri %vreg322<tied0>, 2, %EFLAGS<imp-def,dead>; GR32:%vreg322
15472B		%vreg322<def,tied1> = AND32ri8 %vreg322<tied0>, 4, %EFLAGS<imp-def,dead>; GR32:%vreg322
15488B		%ECX<def> = COPY %vreg322; GR32:%vreg322
15504B		%CL<def> = KILL %ECX<kill>
15536B		%vreg317<def,tied1> = SHR32rCL %vreg317<tied0>, %EFLAGS<imp-def,dead>, %CL<imp-use,kill>; GR32:%vreg317
15568B		%vreg317<def,tied1> = AND32ri8 %vreg317<tied0>, 15, %EFLAGS<imp-def,dead>; GR32:%vreg317
15600B		%vreg317<def,tied1> = SHL32ri %vreg317<tied0>, 16, %EFLAGS<imp-def,dead>; GR32:%vreg317
15632B		%vreg313<def,tied1> = OR32rr %vreg313<tied0>, %vreg317, %EFLAGS<imp-def,dead>; GR32:%vreg313,%vreg317
15648B		%vreg310<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg310
15664B		MOV32mr %vreg310, 1, %noreg, 60, %noreg, %vreg313; mem:ST4[%tPos513] GR64:%vreg310 GR32:%vreg313
15680B		%vreg307<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg307
15696B		%vreg305<def> = MOV32rm %vreg307, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used514] GR32:%vreg305 GR64:%vreg307
15728B		%vreg305<def,tied1> = ADD32ri8 %vreg305<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg305
15744B		MOV32mr %vreg307, 1, %noreg, 1092, %noreg, %vreg305; mem:ST4[%nblock_used514] GR64:%vreg307 GR32:%vreg305
15760B		%vreg301<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg301
15776B		%vreg300<def> = MOV32rm %vreg301, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used516] GR32:%vreg300 GR64:%vreg301
15792B		%vreg298<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg298
15808B		%vreg295<def> = MOV32rm %vreg298, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock517] GR32:%vreg295 GR64:%vreg298
15840B		%vreg295<def,tied1> = ADD32ri8 %vreg295<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg295
15856B		CMP32rr %vreg300, %vreg295, %EFLAGS<imp-def>; GR32:%vreg300,%vreg295
15872B		JNE_1 <BB#70>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#70 BB#69

15888B	BB#69: derived from LLVM BB %if.then.521
	    Predecessors according to CFG: BB#68
15904B		JMP_1 <BB#48>
	    Successors according to CFG: BB#48

15920B	BB#70: derived from LLVM BB %if.end.522
	    Predecessors according to CFG: BB#68
15936B		%vreg375<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg375
15952B		%vreg373<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg373
15968B		CMP32rm %vreg375, %vreg373, 1, %noreg, 64, %noreg, %EFLAGS<imp-def>; mem:LD4[%k0524] GR32:%vreg375 GR64:%vreg373
15984B		JE_1 <BB#72>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#72 BB#71

16000B	BB#71: derived from LLVM BB %if.then.527
	    Predecessors according to CFG: BB#70
16016B		%vreg519<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg519
16032B		%vreg517<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg517
16048B		MOV32mr %vreg517, 1, %noreg, 64, %noreg, %vreg519; mem:ST4[%k0529] GR64:%vreg517 GR32:%vreg519
16064B		JMP_1 <BB#48>
	    Successors according to CFG: BB#48

16080B	BB#72: derived from LLVM BB %if.end.530
	    Predecessors according to CFG: BB#70
16096B		%vreg514<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg514
16112B		%vreg513<def> = MOV32rm %vreg514, 1, %noreg, 60, %noreg; mem:LD4[%tPos531] GR32:%vreg513 GR64:%vreg514
16128B		%vreg510<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg510
16160B		%vreg510<def,tied1> = ADD64ri32 %vreg510<tied0>, 1096, %EFLAGS<imp-def,dead>; GR64:%vreg510
16176B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
16192B		%EDI<def> = COPY %vreg513; GR32:%vreg513
16208B		%RSI<def> = COPY %vreg510; GR64:%vreg510
16224B		CALL64pcrel32 <ga:@BZ2_indexIntoF>, <regmask>, %RSP<imp-use>, %EDI<imp-use>, %RSI<imp-use,kill>, %EAX<imp-def>
16240B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
16256B		%vreg507<def> = COPY %EAX<kill>; GR32:%vreg507
16272B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
16288B		STACKMAP 9, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
16304B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
16336B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg507:sub_8bit; mem:ST1[%k1] GR32:%vreg507
16352B		%vreg501<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg501
16368B		%vreg499:sub_32bit<def,read-undef> = MOV32rm %vreg501, 1, %noreg, 60, %noreg; mem:LD4[%tPos536] GR64_NOSP:%vreg499 GR64:%vreg501
16400B		%vreg496<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg496
16416B		%vreg495<def> = MOV64rm %vreg496, 1, %noreg, 3160, %noreg; mem:LD8[%ll16538] GR64:%vreg495,%vreg496
16432B		%vreg460<def> = MOVZX32rm16 %vreg495, 2, %vreg499, 0, %noreg; mem:LD2[%arrayidx539] GR32:%vreg460 GR64:%vreg495 GR64_NOSP:%vreg499
16448B		%vreg489<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg489
16464B		%vreg486<def> = MOV32rm %vreg489, 1, %noreg, 60, %noreg; mem:LD4[%tPos541] GR32:%vreg486 GR64:%vreg489
16496B		%vreg486<def,tied1> = SHR32ri %vreg486<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg486
16512B		%vreg484:sub_32bit<def,read-undef> = MOV32rr %vreg486; GR64_NOSP:%vreg484 GR32:%vreg486
16544B		%vreg481<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg481
16560B		%vreg480<def> = MOV64rm %vreg481, 1, %noreg, 3168, %noreg; mem:LD8[%ll4544] GR64:%vreg480,%vreg481
16576B		%vreg464<def> = MOVZX32rm8 %vreg480, 1, %vreg484, 0, %noreg; mem:LD1[%arrayidx545] GR32:%vreg464 GR64:%vreg480 GR64_NOSP:%vreg484
16592B		%vreg474<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg474
16608B		%vreg469<def> = MOV32rm %vreg474, 1, %noreg, 60, %noreg; mem:LD4[%tPos547] GR32:%vreg469 GR64:%vreg474
16640B		%vreg469<def,tied1> = SHL32ri %vreg469<tied0>, 2, %EFLAGS<imp-def,dead>; GR32:%vreg469
16672B		%vreg469<def,tied1> = AND32ri8 %vreg469<tied0>, 4, %EFLAGS<imp-def,dead>; GR32:%vreg469
16688B		%ECX<def> = COPY %vreg469; GR32:%vreg469
16704B		%CL<def> = KILL %ECX<kill>
16736B		%vreg464<def,tied1> = SHR32rCL %vreg464<tied0>, %EFLAGS<imp-def,dead>, %CL<imp-use,kill>; GR32:%vreg464
16768B		%vreg464<def,tied1> = AND32ri8 %vreg464<tied0>, 15, %EFLAGS<imp-def,dead>; GR32:%vreg464
16800B		%vreg464<def,tied1> = SHL32ri %vreg464<tied0>, 16, %EFLAGS<imp-def,dead>; GR32:%vreg464
16832B		%vreg460<def,tied1> = OR32rr %vreg460<tied0>, %vreg464, %EFLAGS<imp-def,dead>; GR32:%vreg460,%vreg464
16848B		%vreg457<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg457
16864B		MOV32mr %vreg457, 1, %noreg, 60, %noreg, %vreg460; mem:ST4[%tPos554] GR64:%vreg457 GR32:%vreg460
16880B		%vreg454<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg454
16896B		%vreg452<def> = MOV32rm %vreg454, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used555] GR32:%vreg452 GR64:%vreg454
16928B		%vreg452<def,tied1> = ADD32ri8 %vreg452<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg452
16944B		MOV32mr %vreg454, 1, %noreg, 1092, %noreg, %vreg452; mem:ST4[%nblock_used555] GR64:%vreg454 GR32:%vreg452
16960B		%vreg446<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg446
16992B		%vreg446<def,tied1> = ADD32ri8 %vreg446<tied0>, 4, %EFLAGS<imp-def,dead>; GR32:%vreg446
17008B		%vreg444<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg444
17024B		MOV32mr %vreg444, 1, %noreg, 16, %noreg, %vreg446; mem:ST4[%state_out_len559] GR64:%vreg444 GR32:%vreg446
17040B		%vreg441<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg441
17056B		%vreg440<def> = MOV32rm %vreg441, 1, %noreg, 60, %noreg; mem:LD4[%tPos560] GR32:%vreg440 GR64:%vreg441
17072B		%vreg437<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg437
17104B		%vreg437<def,tied1> = ADD64ri32 %vreg437<tied0>, 1096, %EFLAGS<imp-def,dead>; GR64:%vreg437
17120B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
17136B		%EDI<def> = COPY %vreg440; GR32:%vreg440
17152B		%RSI<def> = COPY %vreg437; GR64:%vreg437
17168B		CALL64pcrel32 <ga:@BZ2_indexIntoF>, <regmask>, %RSP<imp-use>, %EDI<imp-use>, %RSI<imp-use,kill>, %EAX<imp-def>
17184B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
17200B		%vreg434<def> = COPY %EAX<kill>; GR32:%vreg434
17216B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
17232B		STACKMAP 10, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
17248B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
17264B		%vreg431<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg431
17280B		MOV32mr %vreg431, 1, %noreg, 64, %noreg, %vreg434; mem:ST4[%k0564] GR64:%vreg431 GR32:%vreg434
17296B		%vreg428<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg428
17312B		%vreg426:sub_32bit<def,read-undef> = MOV32rm %vreg428, 1, %noreg, 60, %noreg; mem:LD4[%tPos565] GR64_NOSP:%vreg426 GR64:%vreg428
17344B		%vreg423<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg423
17360B		%vreg422<def> = MOV64rm %vreg423, 1, %noreg, 3160, %noreg; mem:LD8[%ll16567] GR64:%vreg422,%vreg423
17376B		%vreg387<def> = MOVZX32rm16 %vreg422, 2, %vreg426, 0, %noreg; mem:LD2[%arrayidx568] GR32:%vreg387 GR64:%vreg422 GR64_NOSP:%vreg426
17392B		%vreg416<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg416
17408B		%vreg413<def> = MOV32rm %vreg416, 1, %noreg, 60, %noreg; mem:LD4[%tPos570] GR32:%vreg413 GR64:%vreg416
17440B		%vreg413<def,tied1> = SHR32ri %vreg413<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg413
17456B		%vreg411:sub_32bit<def,read-undef> = MOV32rr %vreg413; GR64_NOSP:%vreg411 GR32:%vreg413
17488B		%vreg408<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg408
17504B		%vreg407<def> = MOV64rm %vreg408, 1, %noreg, 3168, %noreg; mem:LD8[%ll4573] GR64:%vreg407,%vreg408
17520B		%vreg391<def> = MOVZX32rm8 %vreg407, 1, %vreg411, 0, %noreg; mem:LD1[%arrayidx574] GR32:%vreg391 GR64:%vreg407 GR64_NOSP:%vreg411
17536B		%vreg401<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg401
17552B		%vreg396<def> = MOV32rm %vreg401, 1, %noreg, 60, %noreg; mem:LD4[%tPos576] GR32:%vreg396 GR64:%vreg401
17584B		%vreg396<def,tied1> = SHL32ri %vreg396<tied0>, 2, %EFLAGS<imp-def,dead>; GR32:%vreg396
17616B		%vreg396<def,tied1> = AND32ri8 %vreg396<tied0>, 4, %EFLAGS<imp-def,dead>; GR32:%vreg396
17632B		%ECX<def> = COPY %vreg396; GR32:%vreg396
17648B		%CL<def> = KILL %ECX<kill>
17680B		%vreg391<def,tied1> = SHR32rCL %vreg391<tied0>, %EFLAGS<imp-def,dead>, %CL<imp-use,kill>; GR32:%vreg391
17712B		%vreg391<def,tied1> = AND32ri8 %vreg391<tied0>, 15, %EFLAGS<imp-def,dead>; GR32:%vreg391
17744B		%vreg391<def,tied1> = SHL32ri %vreg391<tied0>, 16, %EFLAGS<imp-def,dead>; GR32:%vreg391
17776B		%vreg387<def,tied1> = OR32rr %vreg387<tied0>, %vreg391, %EFLAGS<imp-def,dead>; GR32:%vreg387,%vreg391
17792B		%vreg384<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg384
17808B		MOV32mr %vreg384, 1, %noreg, 60, %noreg, %vreg387; mem:ST4[%tPos583] GR64:%vreg384 GR32:%vreg387
17824B		%vreg381<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg381
17840B		%vreg379<def> = MOV32rm %vreg381, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used584] GR32:%vreg379 GR64:%vreg381
17872B		%vreg379<def,tied1> = ADD32ri8 %vreg379<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg379
17888B		MOV32mr %vreg381, 1, %noreg, 1092, %noreg, %vreg379; mem:ST4[%nblock_used584] GR64:%vreg381 GR32:%vreg379
17904B		JMP_1 <BB#48>
	    Successors according to CFG: BB#48

17920B	BB#73: derived from LLVM BB %return
	    Predecessors according to CFG: BB#59 BB#57 BB#50 BB#13 BB#11 BB#4
17936B		%vreg1268<def> = MOV64ri <ga:@unRLE_obuf_to_output_SMALL>; GR64:%vreg1268
17968B		%vreg1269<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg1269
17984B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
18000B		%RDI<def> = COPY %vreg1268; GR64:%vreg1268
18016B		%RSI<def> = COPY %vreg1269; GR64:%vreg1269
18032B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
18048B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
18064B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
18080B		STACKMAP 11, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=1)
18096B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
18112B		%vreg1266<def> = MOV8rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD1[%retval] GR8:%vreg1266
18128B		%AL<def> = COPY %vreg1266; GR8:%vreg1266
18144B		RETQ %AL<imp-use,kill>

# End machine code for function unRLE_obuf_to_output_SMALL.


selectOrSplit GR64:%vreg1 [16r,224r:0)  0@16r w=4.983552e-03
hints: %RDI
missed hint %RDI
assigning %vreg1 to %RBX: BH [16r,224r:0)  0@16r BL [16r,224r:0)  0@16r

selectOrSplit GR64:%vreg6 [48r,112r:0)  0@48r w=2.176724e-03
hints: %RDI
assigning %vreg6 to %RDI: DIL [48r,112r:0)  0@48r

selectOrSplit GR64:%vreg7 [80r,128r:0)  0@80r w=4.508928e-03
hints: %RSI
assigning %vreg7 to %RSI: SIL [80r,128r:0)  0@80r

selectOrSplit GR32:%vreg699 [2080r,2160r:0)  0@2080r w=1.911987e-04
hints: %EDI
assigning %vreg699 to %EDI: DIL [2080r,2160r:0)  0@2080r

selectOrSplit GR64:%vreg696 [2096r,2128r:0)[2128r,2176r:1)  0@2096r 1@2128r w=3.823974e-04
hints: %RSI
assigning %vreg696 to %RSI: SIL [2096r,2128r:0)[2128r,2176r:1)  0@2096r 1@2128r

selectOrSplit GR32:%vreg693 [2224r,2304r:0)  0@2224r w=1.911987e-04
hints: %EAX
assigning %vreg693 to %EAX: AH [2224r,2304r:0)  0@2224r AL [2224r,2304r:0)  0@2224r

selectOrSplit GR32:%vreg655 [2576r,2608r:2)[2608r,2640r:0)[2640r,2656r:1)  0@2608r 1@2640r 2@2576r w=inf
hints: %ECX
assigning %vreg655 to %ECX: CH [2576r,2608r:2)[2608r,2640r:0)[2640r,2656r:1)  0@2608r 1@2640r 2@2576r CL [2576r,2608r:2)[2608r,2640r:0)[2640r,2656r:1)  0@2608r 1@2640r 2@2576r

selectOrSplit GR32:%vreg834 [3936r,4016r:0)  0@3936r w=4.772962e-05
hints: %EDI
assigning %vreg834 to %EDI: DIL [3936r,4016r:0)  0@3936r

selectOrSplit GR64:%vreg831 [3952r,3984r:0)[3984r,4032r:1)  0@3952r 1@3984r w=9.545925e-05
hints: %RSI
assigning %vreg831 to %RSI: SIL [3952r,3984r:0)[3984r,4032r:1)  0@3952r 1@3984r

selectOrSplit GR32:%vreg828 [4080r,4160r:0)  0@4080r w=4.772962e-05
hints: %EAX
assigning %vreg828 to %EAX: AH [4080r,4160r:0)  0@4080r AL [4080r,4160r:0)  0@4080r

selectOrSplit GR32:%vreg790 [4432r,4464r:2)[4464r,4496r:0)[4496r,4512r:1)  0@4464r 1@4496r 2@4432r w=inf
hints: %ECX
assigning %vreg790 to %ECX: CH [4432r,4464r:2)[4464r,4496r:0)[4496r,4512r:1)  0@4464r 1@4496r 2@4432r CL [4432r,4464r:2)[4464r,4496r:0)[4496r,4512r:1)  0@4464r 1@4496r 2@4432r

selectOrSplit GR32:%vreg961 [5792r,5872r:0)  0@5792r w=1.186235e-05
hints: %EDI
assigning %vreg961 to %EDI: DIL [5792r,5872r:0)  0@5792r

selectOrSplit GR64:%vreg958 [5808r,5840r:0)[5840r,5888r:1)  0@5808r 1@5840r w=2.372471e-05
hints: %RSI
assigning %vreg958 to %RSI: SIL [5808r,5840r:0)[5840r,5888r:1)  0@5808r 1@5840r

selectOrSplit GR32:%vreg955 [5936r,6016r:0)  0@5936r w=1.186235e-05
hints: %EAX
assigning %vreg955 to %EAX: AH [5936r,6016r:0)  0@5936r AL [5936r,6016r:0)  0@5936r

selectOrSplit GR32:%vreg917 [6288r,6320r:2)[6320r,6352r:0)[6352r,6368r:1)  0@6320r 1@6352r 2@6288r w=inf
hints: %ECX
assigning %vreg917 to %ECX: CH [6288r,6320r:2)[6320r,6352r:0)[6352r,6368r:1)  0@6320r 1@6352r 2@6288r CL [6288r,6320r:2)[6320r,6352r:0)[6352r,6368r:1)  0@6320r 1@6352r 2@6288r

selectOrSplit GR32:%vreg1088 [7616r,7696r:0)  0@7616r w=2.895535e-06
hints: %EDI
assigning %vreg1088 to %EDI: DIL [7616r,7696r:0)  0@7616r

selectOrSplit GR64:%vreg1085 [7632r,7664r:0)[7664r,7712r:1)  0@7632r 1@7664r w=5.791070e-06
hints: %RSI
assigning %vreg1085 to %RSI: SIL [7632r,7664r:0)[7664r,7712r:1)  0@7632r 1@7664r

selectOrSplit GR32:%vreg1082 [7760r,7840r:0)  0@7760r w=2.895535e-06
hints: %EAX
assigning %vreg1082 to %EAX: AH [7760r,7840r:0)  0@7760r AL [7760r,7840r:0)  0@7760r

selectOrSplit GR32:%vreg1044 [8112r,8144r:2)[8144r,8176r:0)[8176r,8192r:1)  0@8144r 1@8176r 2@8112r w=inf
hints: %ECX
assigning %vreg1044 to %ECX: CH [8112r,8144r:2)[8144r,8176r:0)[8176r,8192r:1)  0@8144r 1@8176r 2@8112r CL [8112r,8144r:2)[8144r,8176r:0)[8176r,8192r:1)  0@8144r 1@8176r 2@8112r

selectOrSplit GR32:%vreg1171 [9184r,9264r:0)  0@9184r w=2.895535e-06
hints: %EDI
assigning %vreg1171 to %EDI: DIL [9184r,9264r:0)  0@9184r

selectOrSplit GR64:%vreg1168 [9200r,9232r:0)[9232r,9280r:1)  0@9200r 1@9232r w=5.791070e-06
hints: %RSI
assigning %vreg1168 to %RSI: SIL [9200r,9232r:0)[9232r,9280r:1)  0@9200r 1@9232r

selectOrSplit GR32:%vreg1165 [9328r,9408r:0)  0@9328r w=2.895535e-06
hints: %EAX
assigning %vreg1165 to %EAX: AH [9328r,9408r:0)  0@9328r AL [9328r,9408r:0)  0@9328r

selectOrSplit GR32:%vreg1127 [9680r,9712r:2)[9712r,9744r:0)[9744r,9760r:1)  0@9712r 1@9744r 2@9680r w=inf
hints: %ECX
assigning %vreg1127 to %ECX: CH [9680r,9712r:2)[9712r,9744r:0)[9744r,9760r:1)  0@9712r 1@9744r 2@9680r CL [9680r,9712r:2)[9712r,9744r:0)[9744r,9760r:1)  0@9712r 1@9744r 2@9680r

selectOrSplit GR32:%vreg190 [12448r,12528r:0)  0@12448r w=1.911987e-04
hints: %EDI
assigning %vreg190 to %EDI: DIL [12448r,12528r:0)  0@12448r

selectOrSplit GR64:%vreg187 [12464r,12496r:0)[12496r,12544r:1)  0@12464r 1@12496r w=3.823974e-04
hints: %RSI
assigning %vreg187 to %RSI: SIL [12464r,12496r:0)[12496r,12544r:1)  0@12464r 1@12496r

selectOrSplit GR32:%vreg184 [12592r,12672r:0)  0@12592r w=1.911987e-04
hints: %EAX
assigning %vreg184 to %EAX: AH [12592r,12672r:0)  0@12592r AL [12592r,12672r:0)  0@12592r

selectOrSplit GR32:%vreg146 [12944r,12976r:2)[12976r,13008r:0)[13008r,13024r:1)  0@12976r 1@13008r 2@12944r w=inf
hints: %ECX
assigning %vreg146 to %ECX: CH [12944r,12976r:2)[12976r,13008r:0)[13008r,13024r:1)  0@12976r 1@13008r 2@12944r CL [12944r,12976r:2)[12976r,13008r:0)[13008r,13024r:1)  0@12976r 1@13008r 2@12944r

selectOrSplit GR32:%vreg282 [13680r,13760r:0)  0@13680r w=4.772962e-05
hints: %EDI
assigning %vreg282 to %EDI: DIL [13680r,13760r:0)  0@13680r

selectOrSplit GR64:%vreg279 [13696r,13728r:0)[13728r,13776r:1)  0@13696r 1@13728r w=9.545925e-05
hints: %RSI
assigning %vreg279 to %RSI: SIL [13696r,13728r:0)[13728r,13776r:1)  0@13696r 1@13728r

selectOrSplit GR32:%vreg276 [13824r,13904r:0)  0@13824r w=4.772962e-05
hints: %EAX
assigning %vreg276 to %EAX: AH [13824r,13904r:0)  0@13824r AL [13824r,13904r:0)  0@13824r

selectOrSplit GR32:%vreg238 [14176r,14208r:2)[14208r,14240r:0)[14240r,14256r:1)  0@14208r 1@14240r 2@14176r w=inf
hints: %ECX
assigning %vreg238 to %ECX: CH [14176r,14208r:2)[14208r,14240r:0)[14240r,14256r:1)  0@14208r 1@14240r 2@14176r CL [14176r,14208r:2)[14208r,14240r:0)[14240r,14256r:1)  0@14208r 1@14240r 2@14176r

selectOrSplit GR32:%vreg366 [14912r,14992r:0)  0@14912r w=1.186235e-05
hints: %EDI
assigning %vreg366 to %EDI: DIL [14912r,14992r:0)  0@14912r

selectOrSplit GR64:%vreg363 [14928r,14960r:0)[14960r,15008r:1)  0@14928r 1@14960r w=2.372471e-05
hints: %RSI
assigning %vreg363 to %RSI: SIL [14928r,14960r:0)[14960r,15008r:1)  0@14928r 1@14960r

selectOrSplit GR32:%vreg360 [15056r,15136r:0)  0@15056r w=1.186235e-05
hints: %EAX
assigning %vreg360 to %EAX: AH [15056r,15136r:0)  0@15056r AL [15056r,15136r:0)  0@15056r

selectOrSplit GR32:%vreg322 [15408r,15440r:2)[15440r,15472r:0)[15472r,15488r:1)  0@15440r 1@15472r 2@15408r w=inf
hints: %ECX
assigning %vreg322 to %ECX: CH [15408r,15440r:2)[15440r,15472r:0)[15472r,15488r:1)  0@15440r 1@15472r 2@15408r CL [15408r,15440r:2)[15440r,15472r:0)[15472r,15488r:1)  0@15440r 1@15472r 2@15408r

selectOrSplit GR32:%vreg513 [16112r,16192r:0)  0@16112r w=2.895535e-06
hints: %EDI
assigning %vreg513 to %EDI: DIL [16112r,16192r:0)  0@16112r

selectOrSplit GR64:%vreg510 [16128r,16160r:0)[16160r,16208r:1)  0@16128r 1@16160r w=5.791070e-06
hints: %RSI
assigning %vreg510 to %RSI: SIL [16128r,16160r:0)[16160r,16208r:1)  0@16128r 1@16160r

selectOrSplit GR32:%vreg507 [16256r,16336r:0)  0@16256r w=2.895535e-06
hints: %EAX
assigning %vreg507 to %EAX: AH [16256r,16336r:0)  0@16256r AL [16256r,16336r:0)  0@16256r

selectOrSplit GR32:%vreg469 [16608r,16640r:2)[16640r,16672r:0)[16672r,16688r:1)  0@16640r 1@16672r 2@16608r w=inf
hints: %ECX
assigning %vreg469 to %ECX: CH [16608r,16640r:2)[16640r,16672r:0)[16672r,16688r:1)  0@16640r 1@16672r 2@16608r CL [16608r,16640r:2)[16640r,16672r:0)[16672r,16688r:1)  0@16640r 1@16672r 2@16608r

selectOrSplit GR32:%vreg440 [17056r,17136r:0)  0@17056r w=2.895535e-06
hints: %EDI
assigning %vreg440 to %EDI: DIL [17056r,17136r:0)  0@17056r

selectOrSplit GR64:%vreg437 [17072r,17104r:0)[17104r,17152r:1)  0@17072r 1@17104r w=5.791070e-06
hints: %RSI
assigning %vreg437 to %RSI: SIL [17072r,17104r:0)[17104r,17152r:1)  0@17072r 1@17104r

selectOrSplit GR32:%vreg434 [17200r,17280r:0)  0@17200r w=2.895535e-06
hints: %EAX
assigning %vreg434 to %EAX: AH [17200r,17280r:0)  0@17200r AL [17200r,17280r:0)  0@17200r

selectOrSplit GR32:%vreg396 [17552r,17584r:2)[17584r,17616r:0)[17616r,17632r:1)  0@17584r 1@17616r 2@17552r w=inf
hints: %ECX
assigning %vreg396 to %ECX: CH [17552r,17584r:2)[17584r,17616r:0)[17616r,17632r:1)  0@17584r 1@17616r 2@17552r CL [17552r,17584r:2)[17584r,17616r:0)[17616r,17632r:1)  0@17584r 1@17616r 2@17552r

selectOrSplit GR64:%vreg1268 [17936r,18000r:0)  0@17936r w=2.176724e-03
hints: %RDI
assigning %vreg1268 to %RDI: DIL [17936r,18000r:0)  0@17936r

selectOrSplit GR64:%vreg1269 [17968r,18016r:0)  0@17968r w=4.508928e-03
hints: %RSI
assigning %vreg1269 to %RSI: SIL [17968r,18016r:0)  0@17968r

selectOrSplit GR8:%vreg1266 [18112r,18128r:0)  0@18112r w=inf
hints: %AL
assigning %vreg1266 to %AL: AL [18112r,18128r:0)  0@18112r

selectOrSplit GR64:%vreg4 [240r,256r:0)  0@240r w=inf
assigning %vreg4 to %RAX: AH [240r,256r:0)  0@240r AL [240r,256r:0)  0@240r

selectOrSplit GR64:%vreg534 [368r,384r:0)  0@368r w=inf
assigning %vreg534 to %RAX: AH [368r,384r:0)  0@368r AL [368r,384r:0)  0@368r

selectOrSplit GR64:%vreg533 [384r,400r:0)  0@384r w=inf
assigning %vreg533 to %RAX: AH [384r,400r:0)  0@384r AL [384r,400r:0)  0@384r

selectOrSplit GR64:%vreg537 [496r,512r:0)  0@496r w=inf
assigning %vreg537 to %RAX: AH [496r,512r:0)  0@496r AL [496r,512r:0)  0@496r

selectOrSplit GR64:%vreg609 [592r,608r:0)  0@592r w=inf
assigning %vreg609 to %RAX: AH [592r,608r:0)  0@592r AL [592r,608r:0)  0@592r

selectOrSplit GR8:%vreg608 [608r,672r:0)  0@608r w=7.836208e-04
assigning %vreg608 to %AL: AL [608r,672r:0)  0@608r

selectOrSplit GR64:%vreg606 [624r,640r:0)  0@624r w=inf
assigning %vreg606 to %RCX: CH [624r,640r:0)  0@624r CL [624r,640r:0)  0@624r

selectOrSplit GR64:%vreg605 [640r,656r:0)  0@640r w=inf
assigning %vreg605 to %RCX: CH [640r,656r:0)  0@640r CL [640r,656r:0)  0@640r

selectOrSplit GR64:%vreg603 [656r,672r:0)  0@656r w=inf
assigning %vreg603 to %RCX: CH [656r,672r:0)  0@656r CL [656r,672r:0)  0@656r

selectOrSplit GR64:%vreg599 [688r,704r:0)  0@688r w=inf
assigning %vreg599 to %RAX: AH [688r,704r:0)  0@688r AL [688r,704r:0)  0@688r

selectOrSplit GR32:%vreg578 [704r,736r:2)[736r,928r:0)[928r,960r:1)  0@736r 1@928r 2@704r w=1.662805e-03
assigning %vreg578 to %EAX: AH [704r,736r:2)[736r,928r:0)[928r,960r:1)  0@736r 1@928r 2@704r AL [704r,736r:2)[736r,928r:0)[928r,960r:1)  0@736r 1@928r 2@704r

selectOrSplit GR64:%vreg594 [752r,768r:0)  0@752r w=inf
assigning %vreg594 to %RCX: CH [752r,768r:0)  0@752r CL [752r,768r:0)  0@752r

selectOrSplit GR32:%vreg585 [768r,800r:2)[800r,864r:0)[864r,880r:1)  0@800r 1@864r 2@768r w=2.130469e-03
assigning %vreg585 to %ECX: CH [768r,800r:2)[800r,864r:0)[864r,880r:1)  0@800r 1@864r 2@768r CL [768r,800r:2)[800r,864r:0)[864r,880r:1)  0@800r 1@864r 2@768r

selectOrSplit GR64:%vreg589 [816r,832r:0)  0@816r w=inf
assigning %vreg589 to %RDX: DH [816r,832r:0)  0@816r DL [816r,832r:0)  0@816r

selectOrSplit GR32:%vreg587 [832r,864r:0)  0@832r w=inf
assigning %vreg587 to %EDX: DH [832r,864r:0)  0@832r DL [832r,864r:0)  0@832r

selectOrSplit GR64_NOSP:%vreg582 [880r,928r:0)  0@880r w=inf
assigning %vreg582 to %RCX: CH [880r,928r:0)  0@880r CL [880r,928r:0)  0@880r

selectOrSplit GR64:%vreg575 [944r,960r:0)  0@944r w=inf
assigning %vreg575 to %RCX: CH [944r,960r:0)  0@944r CL [944r,960r:0)  0@944r

selectOrSplit GR64:%vreg572 [976r,1040r:0)  0@976r w=1.175431e-03
assigning %vreg572 to %RAX: AH [976r,1040r:0)  0@976r AL [976r,1040r:0)  0@976r

selectOrSplit GR32:%vreg570 [992r,1024r:0)[1024r,1040r:1)  0@992r 1@1024r w=inf
assigning %vreg570 to %ECX: CH [992r,1024r:0)[1024r,1040r:1)  0@992r 1@1024r CL [992r,1024r:0)[1024r,1040r:1)  0@992r 1@1024r

selectOrSplit GR64:%vreg566 [1056r,1072r:0)  0@1056r w=inf
assigning %vreg566 to %RAX: AH [1056r,1072r:0)  0@1056r AL [1056r,1072r:0)  0@1056r

selectOrSplit GR64:%vreg565 [1072r,1136r:0)  0@1072r w=1.175431e-03
assigning %vreg565 to %RAX: AH [1072r,1136r:0)  0@1072r AL [1072r,1136r:0)  0@1072r

selectOrSplit GR64:%vreg562 [1088r,1120r:0)[1120r,1136r:1)  0@1088r 1@1120r w=inf
assigning %vreg562 to %RCX: CH [1088r,1120r:0)[1120r,1136r:1)  0@1088r 1@1120r CL [1088r,1120r:0)[1120r,1136r:1)  0@1088r 1@1120r

selectOrSplit GR64:%vreg558 [1152r,1168r:0)  0@1152r w=inf
assigning %vreg558 to %RAX: AH [1152r,1168r:0)  0@1152r AL [1152r,1168r:0)  0@1152r

selectOrSplit GR64:%vreg557 [1168r,1232r:0)  0@1168r w=1.175431e-03
assigning %vreg557 to %RAX: AH [1168r,1232r:0)  0@1168r AL [1168r,1232r:0)  0@1168r

selectOrSplit GR32:%vreg554 [1184r,1216r:0)[1216r,1232r:1)  0@1184r 1@1216r w=inf
assigning %vreg554 to %ECX: CH [1184r,1216r:0)[1216r,1232r:1)  0@1184r 1@1216r CL [1184r,1216r:0)[1216r,1232r:1)  0@1184r 1@1216r

selectOrSplit GR64:%vreg550 [1248r,1264r:0)  0@1248r w=inf
assigning %vreg550 to %RAX: AH [1248r,1264r:0)  0@1248r AL [1248r,1264r:0)  0@1248r

selectOrSplit GR64:%vreg549 [1264r,1328r:0)  0@1264r w=1.175431e-03
assigning %vreg549 to %RAX: AH [1264r,1328r:0)  0@1264r AL [1264r,1328r:0)  0@1264r

selectOrSplit GR32:%vreg546 [1280r,1312r:0)[1312r,1328r:1)  0@1280r 1@1312r w=inf
assigning %vreg546 to %ECX: CH [1280r,1312r:0)[1312r,1328r:1)  0@1280r 1@1312r CL [1280r,1312r:0)[1312r,1328r:1)  0@1280r 1@1312r

selectOrSplit GR64:%vreg542 [1344r,1360r:0)  0@1344r w=inf
assigning %vreg542 to %RAX: AH [1344r,1360r:0)  0@1344r AL [1344r,1360r:0)  0@1344r

selectOrSplit GR64:%vreg541 [1360r,1376r:0)  0@1360r w=inf
assigning %vreg541 to %RAX: AH [1360r,1376r:0)  0@1360r AL [1360r,1376r:0)  0@1360r

selectOrSplit GR64:%vreg617 [1424r,1440r:0)  0@1424r w=inf
assigning %vreg617 to %RAX: AH [1424r,1440r:0)  0@1424r AL [1424r,1440r:0)  0@1424r

selectOrSplit GR64:%vreg616 [1440r,1504r:0)  0@1440r w=5.876438e-04
assigning %vreg616 to %RAX: AH [1440r,1504r:0)  0@1440r AL [1440r,1504r:0)  0@1440r

selectOrSplit GR32:%vreg613 [1456r,1488r:0)[1488r,1504r:1)  0@1456r 1@1488r w=inf
assigning %vreg613 to %ECX: CH [1456r,1488r:0)[1488r,1504r:1)  0@1456r 1@1488r CL [1456r,1488r:0)[1488r,1504r:1)  0@1456r 1@1488r

selectOrSplit GR64:%vreg627 [1568r,1584r:0)  0@1568r w=inf
assigning %vreg627 to %RAX: AH [1568r,1584r:0)  0@1568r AL [1568r,1584r:0)  0@1568r

selectOrSplit GR32:%vreg626 [1584r,1664r:0)  0@1584r w=7.575001e-04
assigning %vreg626 to %EAX: AH [1584r,1664r:0)  0@1584r AL [1584r,1664r:0)  0@1584r

selectOrSplit GR64:%vreg624 [1600r,1616r:0)  0@1600r w=inf
assigning %vreg624 to %RCX: CH [1600r,1616r:0)  0@1600r CL [1600r,1616r:0)  0@1600r

selectOrSplit GR32:%vreg621 [1616r,1648r:0)[1648r,1664r:1)  0@1616r 1@1648r w=inf
assigning %vreg621 to %ECX: CH [1616r,1648r:0)[1648r,1664r:1)  0@1616r 1@1648r CL [1616r,1648r:0)[1648r,1664r:1)  0@1616r 1@1648r

selectOrSplit GR64:%vreg637 [1760r,1776r:0)  0@1760r w=inf
assigning %vreg637 to %RAX: AH [1760r,1776r:0)  0@1760r AL [1760r,1776r:0)  0@1760r

selectOrSplit GR32:%vreg636 [1776r,1856r:0)  0@1776r w=3.787038e-04
assigning %vreg636 to %EAX: AH [1776r,1856r:0)  0@1776r AL [1776r,1856r:0)  0@1776r

selectOrSplit GR64:%vreg634 [1792r,1808r:0)  0@1792r w=inf
assigning %vreg634 to %RCX: CH [1792r,1808r:0)  0@1792r CL [1792r,1808r:0)  0@1792r

selectOrSplit GR32:%vreg631 [1808r,1840r:0)[1840r,1856r:1)  0@1808r 1@1840r w=inf
assigning %vreg631 to %ECX: CH [1808r,1840r:0)[1840r,1856r:1)  0@1808r 1@1840r CL [1808r,1840r:0)[1840r,1856r:1)  0@1808r 1@1840r

selectOrSplit GR64:%vreg710 [1952r,1968r:0)  0@1952r w=inf
assigning %vreg710 to %RAX: AH [1952r,1968r:0)  0@1952r AL [1952r,1968r:0)  0@1952r

selectOrSplit GR64:%vreg708 [1984r,2000r:0)  0@1984r w=inf
assigning %vreg708 to %RAX: AH [1984r,2000r:0)  0@1984r AL [1984r,2000r:0)  0@1984r

selectOrSplit GR32:%vreg707 [2000r,2048r:0)  0@2000r w=2.028275e-04
assigning %vreg707 to %EAX: AH [2000r,2048r:0)  0@2000r AL [2000r,2048r:0)  0@2000r

selectOrSplit GR64:%vreg703 [2032r,2048r:0)  0@2032r w=inf
assigning %vreg703 to %RCX: CH [2032r,2048r:0)  0@2032r CL [2032r,2048r:0)  0@2032r

selectOrSplit GR64:%vreg700 [2064r,2080r:0)  0@2064r w=inf
assigning %vreg700 to %RAX: AH [2064r,2080r:0)  0@2064r AL [2064r,2080r:0)  0@2064r

selectOrSplit GR64:%vreg687 [2320r,2336r:0)  0@2320r w=inf
assigning %vreg687 to %RAX: AH [2320r,2336r:0)  0@2320r AL [2320r,2336r:0)  0@2320r

selectOrSplit GR64_NOSP:%vreg685 [2336r,2400r:0)  0@2336r w=1.958334e-04
assigning %vreg685 to %RAX: AH [2336r,2400r:0)  0@2336r AL [2336r,2400r:0)  0@2336r

selectOrSplit GR64:%vreg682 [2368r,2384r:0)  0@2368r w=inf
assigning %vreg682 to %RCX: CH [2368r,2384r:0)  0@2368r CL [2368r,2384r:0)  0@2368r

selectOrSplit GR64:%vreg681 [2384r,2400r:0)  0@2384r w=inf
assigning %vreg681 to %RCX: CH [2384r,2400r:0)  0@2384r CL [2384r,2400r:0)  0@2384r

selectOrSplit GR32:%vreg646 [2400r,2800r:0)[2800r,2832r:1)  0@2400r 1@2800r w=2.184296e-04
assigning %vreg646 to %EAX: AH [2400r,2800r:0)[2800r,2832r:1)  0@2400r 1@2800r AL [2400r,2800r:0)[2800r,2832r:1)  0@2400r 1@2800r

selectOrSplit GR64:%vreg675 [2416r,2432r:0)  0@2416r w=inf
assigning %vreg675 to %RCX: CH [2416r,2432r:0)  0@2416r CL [2416r,2432r:0)  0@2416r

selectOrSplit GR32:%vreg672 [2432r,2464r:0)[2464r,2480r:1)  0@2432r 1@2464r w=inf
assigning %vreg672 to %ECX: CH [2432r,2464r:0)[2464r,2480r:1)  0@2432r 1@2464r CL [2432r,2464r:0)[2464r,2480r:1)  0@2432r 1@2464r

selectOrSplit GR64_NOSP:%vreg670 [2480r,2544r:0)  0@2480r w=1.958334e-04
assigning %vreg670 to %RCX: CH [2480r,2544r:0)  0@2480r CL [2480r,2544r:0)  0@2480r

selectOrSplit GR64:%vreg667 [2512r,2528r:0)  0@2512r w=inf
assigning %vreg667 to %RDX: DH [2512r,2528r:0)  0@2512r DL [2512r,2528r:0)  0@2512r

selectOrSplit GR64:%vreg666 [2528r,2544r:0)  0@2528r w=inf
assigning %vreg666 to %RDX: DH [2528r,2544r:0)  0@2528r DL [2528r,2544r:0)  0@2528r

selectOrSplit GR32:%vreg650 [2544r,2704r:2)[2704r,2736r:0)[2736r,2768r:1)[2768r,2800r:3)  0@2704r 1@2736r 2@2544r 3@2768r w=5.540653e-04
assigning %vreg650 to %EDX: DH [2544r,2704r:2)[2704r,2736r:0)[2736r,2768r:1)[2768r,2800r:3)  0@2704r 1@2736r 2@2544r 3@2768r DL [2544r,2704r:2)[2704r,2736r:0)[2736r,2768r:1)[2768r,2800r:3)  0@2704r 1@2736r 2@2544r 3@2768r

selectOrSplit GR64:%vreg660 [2560r,2576r:0)  0@2560r w=inf
assigning %vreg660 to %RCX: CH [2560r,2576r:0)  0@2560r CL [2560r,2576r:0)  0@2560r

selectOrSplit GR64:%vreg643 [2816r,2832r:0)  0@2816r w=inf
assigning %vreg643 to %RCX: CH [2816r,2832r:0)  0@2816r CL [2816r,2832r:0)  0@2816r

selectOrSplit GR64:%vreg640 [2848r,2864r:0)  0@2848r w=inf
assigning %vreg640 to %RAX: AH [2848r,2864r:0)  0@2848r AL [2848r,2864r:0)  0@2848r

selectOrSplit GR64:%vreg728 [2912r,2928r:0)  0@2912r w=inf
assigning %vreg728 to %RAX: AH [2912r,2928r:0)  0@2912r AL [2912r,2928r:0)  0@2912r

selectOrSplit GR64_NOSP:%vreg726 [2928r,2944r:0)  0@2928r w=inf
assigning %vreg726 to %RAX: AH [2928r,2944r:0)  0@2928r AL [2928r,2944r:0)  0@2928r

selectOrSplit GR32:%vreg724 [2944r,2976r:0)  0@2944r w=1.051184e-04
assigning %vreg724 to %EAX: AH [2944r,2976r:0)  0@2944r AL [2944r,2976r:0)  0@2944r

selectOrSplit GR64:%vreg722 [2960r,2976r:0)  0@2960r w=inf
assigning %vreg722 to %RCX: CH [2960r,2976r:0)  0@2960r CL [2960r,2976r:0)  0@2960r

selectOrSplit GR64:%vreg719 [2992r,3056r:0)  0@2992r w=1.468033e-04
assigning %vreg719 to %RAX: AH [2992r,3056r:0)  0@2992r AL [2992r,3056r:0)  0@2992r

selectOrSplit GR32:%vreg717 [3008r,3040r:0)[3040r,3056r:1)  0@3008r 1@3040r w=inf
assigning %vreg717 to %ECX: CH [3008r,3040r:0)[3040r,3056r:1)  0@3008r 1@3040r CL [3008r,3040r:0)[3040r,3056r:1)  0@3008r 1@3040r

selectOrSplit GR64:%vreg713 [3072r,3088r:0)  0@3072r w=inf
assigning %vreg713 to %RAX: AH [3072r,3088r:0)  0@3072r AL [3072r,3088r:0)  0@3072r

selectOrSplit GR64:%vreg730 [3136r,3152r:0)  0@3136r w=inf
assigning %vreg730 to %RAX: AH [3136r,3152r:0)  0@3136r AL [3136r,3152r:0)  0@3136r

selectOrSplit GR32:%vreg758 [3216r,3376r:0)[3376r,3424r:1)  0@3216r 1@3376r w=2.989037e-04
assigning %vreg758 to %EAX: AH [3216r,3376r:0)[3376r,3424r:1)  0@3216r 1@3376r AL [3216r,3376r:0)[3376r,3424r:1)  0@3216r 1@3376r

selectOrSplit GR32:%vreg757 [3232r,3376r:0)  0@3232r w=8.351720e-05
assigning %vreg757 to %ECX: CH [3232r,3376r:0)  0@3232r CL [3232r,3376r:0)  0@3232r

selectOrSplit GR64:%vreg766 [3248r,3312r:0)  0@3248r w=2.937501e-04
assigning %vreg766 to %RDX: DH [3248r,3312r:0)  0@3248r DL [3248r,3312r:0)  0@3248r

selectOrSplit GR32:%vreg764 [3264r,3296r:0)[3296r,3312r:1)  0@3264r 1@3296r w=inf
assigning %vreg764 to %ESI: SIL [3264r,3296r:0)[3296r,3312r:1)  0@3264r 1@3296r

selectOrSplit GR64:%vreg760 [3328r,3344r:0)  0@3328r w=inf
assigning %vreg760 to %RDX: DH [3328r,3344r:0)  0@3328r DL [3328r,3344r:0)  0@3328r

selectOrSplit GR32:%vreg752 [3392r,3424r:0)[3424r,3456r:1)  0@3392r 1@3424r w=inf
assigning %vreg752 to %ECX: CH [3392r,3424r:0)[3424r,3456r:1)  0@3392r 1@3424r CL [3392r,3424r:0)[3424r,3456r:1)  0@3392r 1@3424r

selectOrSplit GR64:%vreg746 [3472r,3536r:0)  0@3472r w=2.937501e-04
assigning %vreg746 to %RAX: AH [3472r,3536r:0)  0@3472r AL [3472r,3536r:0)  0@3472r

selectOrSplit GR32:%vreg744 [3488r,3520r:0)[3520r,3536r:1)  0@3488r 1@3520r w=inf
assigning %vreg744 to %ECX: CH [3488r,3520r:0)[3520r,3536r:1)  0@3488r 1@3520r CL [3488r,3520r:0)[3520r,3536r:1)  0@3488r 1@3520r

selectOrSplit GR64:%vreg740 [3552r,3568r:0)  0@3552r w=inf
assigning %vreg740 to %RAX: AH [3552r,3568r:0)  0@3552r AL [3552r,3568r:0)  0@3552r

selectOrSplit GR32:%vreg739 [3568r,3648r:0)  0@3568r w=1.893057e-04
assigning %vreg739 to %EAX: AH [3568r,3648r:0)  0@3568r AL [3568r,3648r:0)  0@3568r

selectOrSplit GR64:%vreg737 [3584r,3600r:0)  0@3584r w=inf
assigning %vreg737 to %RCX: CH [3584r,3600r:0)  0@3584r CL [3584r,3600r:0)  0@3584r

selectOrSplit GR32:%vreg734 [3600r,3632r:0)[3632r,3648r:1)  0@3600r 1@3632r w=inf
assigning %vreg734 to %ECX: CH [3600r,3632r:0)[3632r,3648r:1)  0@3600r 1@3632r CL [3600r,3632r:0)[3632r,3648r:1)  0@3600r 1@3632r

selectOrSplit GR32:%vreg772 [3728r,3760r:0)  0@3728r w=1.051184e-04
assigning %vreg772 to %EAX: AH [3728r,3760r:0)  0@3728r AL [3728r,3760r:0)  0@3728r

selectOrSplit GR64:%vreg770 [3744r,3760r:0)  0@3744r w=inf
assigning %vreg770 to %RCX: CH [3744r,3760r:0)  0@3744r CL [3744r,3760r:0)  0@3744r

selectOrSplit GR32:%vreg1264 [3808r,3840r:0)  0@3808r w=5.250784e-05
assigning %vreg1264 to %EAX: AH [3808r,3840r:0)  0@3808r AL [3808r,3840r:0)  0@3808r

selectOrSplit GR64:%vreg1262 [3824r,3840r:0)  0@3824r w=inf
assigning %vreg1262 to %RCX: CH [3824r,3840r:0)  0@3824r CL [3824r,3840r:0)  0@3824r

selectOrSplit GR64:%vreg837 [3888r,3904r:0)  0@3888r w=inf
assigning %vreg837 to %RAX: AH [3888r,3904r:0)  0@3888r AL [3888r,3904r:0)  0@3888r

selectOrSplit GR64:%vreg835 [3920r,3936r:0)  0@3920r w=inf
assigning %vreg835 to %RAX: AH [3920r,3936r:0)  0@3920r AL [3920r,3936r:0)  0@3920r

selectOrSplit GR64:%vreg822 [4176r,4192r:0)  0@4176r w=inf
assigning %vreg822 to %RAX: AH [4176r,4192r:0)  0@4176r AL [4176r,4192r:0)  0@4176r

selectOrSplit GR64_NOSP:%vreg820 [4192r,4256r:0)  0@4192r w=4.888661e-05
assigning %vreg820 to %RAX: AH [4192r,4256r:0)  0@4192r AL [4192r,4256r:0)  0@4192r

selectOrSplit GR64:%vreg817 [4224r,4240r:0)  0@4224r w=inf
assigning %vreg817 to %RCX: CH [4224r,4240r:0)  0@4224r CL [4224r,4240r:0)  0@4224r

selectOrSplit GR64:%vreg816 [4240r,4256r:0)  0@4240r w=inf
assigning %vreg816 to %RCX: CH [4240r,4256r:0)  0@4240r CL [4240r,4256r:0)  0@4240r

selectOrSplit GR32:%vreg781 [4256r,4656r:0)[4656r,4688r:1)  0@4256r 1@4656r w=5.452737e-05
assigning %vreg781 to %EAX: AH [4256r,4656r:0)[4656r,4688r:1)  0@4256r 1@4656r AL [4256r,4656r:0)[4656r,4688r:1)  0@4256r 1@4656r

selectOrSplit GR64:%vreg810 [4272r,4288r:0)  0@4272r w=inf
assigning %vreg810 to %RCX: CH [4272r,4288r:0)  0@4272r CL [4272r,4288r:0)  0@4272r

selectOrSplit GR32:%vreg807 [4288r,4320r:0)[4320r,4336r:1)  0@4288r 1@4320r w=inf
assigning %vreg807 to %ECX: CH [4288r,4320r:0)[4320r,4336r:1)  0@4288r 1@4320r CL [4288r,4320r:0)[4320r,4336r:1)  0@4288r 1@4320r

selectOrSplit GR64_NOSP:%vreg805 [4336r,4400r:0)  0@4336r w=4.888661e-05
assigning %vreg805 to %RCX: CH [4336r,4400r:0)  0@4336r CL [4336r,4400r:0)  0@4336r

selectOrSplit GR64:%vreg802 [4368r,4384r:0)  0@4368r w=inf
assigning %vreg802 to %RDX: DH [4368r,4384r:0)  0@4368r DL [4368r,4384r:0)  0@4368r

selectOrSplit GR64:%vreg801 [4384r,4400r:0)  0@4384r w=inf
assigning %vreg801 to %RDX: DH [4384r,4400r:0)  0@4384r DL [4384r,4400r:0)  0@4384r

selectOrSplit GR32:%vreg785 [4400r,4560r:2)[4560r,4592r:0)[4592r,4624r:1)[4624r,4656r:3)  0@4560r 1@4592r 2@4400r 3@4624r w=1.383133e-04
assigning %vreg785 to %EDX: DH [4400r,4560r:2)[4560r,4592r:0)[4592r,4624r:1)[4624r,4656r:3)  0@4560r 1@4592r 2@4400r 3@4624r DL [4400r,4560r:2)[4560r,4592r:0)[4592r,4624r:1)[4624r,4656r:3)  0@4560r 1@4592r 2@4400r 3@4624r

selectOrSplit GR64:%vreg795 [4416r,4432r:0)  0@4416r w=inf
assigning %vreg795 to %RCX: CH [4416r,4432r:0)  0@4416r CL [4416r,4432r:0)  0@4416r

selectOrSplit GR64:%vreg778 [4672r,4688r:0)  0@4672r w=inf
assigning %vreg778 to %RCX: CH [4672r,4688r:0)  0@4672r CL [4672r,4688r:0)  0@4672r

selectOrSplit GR64:%vreg775 [4704r,4720r:0)  0@4704r w=inf
assigning %vreg775 to %RAX: AH [4704r,4720r:0)  0@4704r AL [4704r,4720r:0)  0@4704r

selectOrSplit GR64:%vreg855 [4768r,4784r:0)  0@4768r w=inf
assigning %vreg855 to %RAX: AH [4768r,4784r:0)  0@4768r AL [4768r,4784r:0)  0@4768r

selectOrSplit GR64_NOSP:%vreg853 [4784r,4800r:0)  0@4784r w=inf
assigning %vreg853 to %RAX: AH [4784r,4800r:0)  0@4784r AL [4784r,4800r:0)  0@4784r

selectOrSplit GR32:%vreg851 [4800r,4832r:0)  0@4800r w=2.620254e-05
assigning %vreg851 to %EAX: AH [4800r,4832r:0)  0@4800r AL [4800r,4832r:0)  0@4800r

selectOrSplit GR64:%vreg849 [4816r,4832r:0)  0@4816r w=inf
assigning %vreg849 to %RCX: CH [4816r,4832r:0)  0@4816r CL [4816r,4832r:0)  0@4816r

selectOrSplit GR64:%vreg846 [4848r,4912r:0)  0@4848r w=3.659321e-05
assigning %vreg846 to %RAX: AH [4848r,4912r:0)  0@4848r AL [4848r,4912r:0)  0@4848r

selectOrSplit GR32:%vreg844 [4864r,4896r:0)[4896r,4912r:1)  0@4864r 1@4896r w=inf
assigning %vreg844 to %ECX: CH [4864r,4896r:0)[4896r,4912r:1)  0@4864r 1@4896r CL [4864r,4896r:0)[4896r,4912r:1)  0@4864r 1@4896r

selectOrSplit GR64:%vreg840 [4928r,4944r:0)  0@4928r w=inf
assigning %vreg840 to %RAX: AH [4928r,4944r:0)  0@4928r AL [4928r,4944r:0)  0@4928r

selectOrSplit GR64:%vreg857 [4992r,5008r:0)  0@4992r w=inf
assigning %vreg857 to %RAX: AH [4992r,5008r:0)  0@4992r AL [4992r,5008r:0)  0@4992r

selectOrSplit GR32:%vreg885 [5072r,5232r:0)[5232r,5280r:1)  0@5072r 1@5232r w=7.461640e-05
assigning %vreg885 to %EAX: AH [5072r,5232r:0)[5232r,5280r:1)  0@5072r 1@5232r AL [5072r,5232r:0)[5232r,5280r:1)  0@5072r 1@5232r

selectOrSplit GR32:%vreg884 [5088r,5232r:0)  0@5088r w=2.084870e-05
assigning %vreg884 to %ECX: CH [5088r,5232r:0)  0@5088r CL [5088r,5232r:0)  0@5088r

selectOrSplit GR64:%vreg893 [5104r,5168r:0)  0@5104r w=7.332992e-05
assigning %vreg893 to %RDX: DH [5104r,5168r:0)  0@5104r DL [5104r,5168r:0)  0@5104r

selectOrSplit GR32:%vreg891 [5120r,5152r:0)[5152r,5168r:1)  0@5120r 1@5152r w=inf
assigning %vreg891 to %ESI: SIL [5120r,5152r:0)[5152r,5168r:1)  0@5120r 1@5152r

selectOrSplit GR64:%vreg887 [5184r,5200r:0)  0@5184r w=inf
assigning %vreg887 to %RDX: DH [5184r,5200r:0)  0@5184r DL [5184r,5200r:0)  0@5184r

selectOrSplit GR32:%vreg879 [5248r,5280r:0)[5280r,5312r:1)  0@5248r 1@5280r w=inf
assigning %vreg879 to %ECX: CH [5248r,5280r:0)[5280r,5312r:1)  0@5248r 1@5280r CL [5248r,5280r:0)[5280r,5312r:1)  0@5248r 1@5280r

selectOrSplit GR64:%vreg873 [5328r,5392r:0)  0@5328r w=7.332992e-05
assigning %vreg873 to %RAX: AH [5328r,5392r:0)  0@5328r AL [5328r,5392r:0)  0@5328r

selectOrSplit GR32:%vreg871 [5344r,5376r:0)[5376r,5392r:1)  0@5344r 1@5376r w=inf
assigning %vreg871 to %ECX: CH [5344r,5376r:0)[5376r,5392r:1)  0@5344r 1@5376r CL [5344r,5376r:0)[5376r,5392r:1)  0@5344r 1@5376r

selectOrSplit GR64:%vreg867 [5408r,5424r:0)  0@5408r w=inf
assigning %vreg867 to %RAX: AH [5408r,5424r:0)  0@5408r AL [5408r,5424r:0)  0@5408r

selectOrSplit GR32:%vreg866 [5424r,5504r:0)  0@5424r w=4.725705e-05
assigning %vreg866 to %EAX: AH [5424r,5504r:0)  0@5424r AL [5424r,5504r:0)  0@5424r

selectOrSplit GR64:%vreg864 [5440r,5456r:0)  0@5440r w=inf
assigning %vreg864 to %RCX: CH [5440r,5456r:0)  0@5440r CL [5440r,5456r:0)  0@5440r

selectOrSplit GR32:%vreg861 [5456r,5488r:0)[5488r,5504r:1)  0@5456r 1@5488r w=inf
assigning %vreg861 to %ECX: CH [5456r,5488r:0)[5488r,5504r:1)  0@5456r 1@5488r CL [5456r,5488r:0)[5488r,5504r:1)  0@5456r 1@5488r

selectOrSplit GR32:%vreg899 [5584r,5616r:0)  0@5584r w=2.620254e-05
assigning %vreg899 to %EAX: AH [5584r,5616r:0)  0@5584r AL [5584r,5616r:0)  0@5584r

selectOrSplit GR64:%vreg897 [5600r,5616r:0)  0@5600r w=inf
assigning %vreg897 to %RCX: CH [5600r,5616r:0)  0@5600r CL [5600r,5616r:0)  0@5600r

selectOrSplit GR32:%vreg1259 [5664r,5696r:0)  0@5664r w=1.304989e-05
assigning %vreg1259 to %EAX: AH [5664r,5696r:0)  0@5664r AL [5664r,5696r:0)  0@5664r

selectOrSplit GR64:%vreg1257 [5680r,5696r:0)  0@5680r w=inf
assigning %vreg1257 to %RCX: CH [5680r,5696r:0)  0@5680r CL [5680r,5696r:0)  0@5680r

selectOrSplit GR64:%vreg964 [5744r,5760r:0)  0@5744r w=inf
assigning %vreg964 to %RAX: AH [5744r,5760r:0)  0@5744r AL [5744r,5760r:0)  0@5744r

selectOrSplit GR64:%vreg962 [5776r,5792r:0)  0@5776r w=inf
assigning %vreg962 to %RAX: AH [5776r,5792r:0)  0@5776r AL [5776r,5792r:0)  0@5776r

selectOrSplit GR64:%vreg949 [6032r,6048r:0)  0@6032r w=inf
assigning %vreg949 to %RAX: AH [6032r,6048r:0)  0@6032r AL [6032r,6048r:0)  0@6032r

selectOrSplit GR64_NOSP:%vreg947 [6048r,6112r:0)  0@6048r w=1.214990e-05
assigning %vreg947 to %RAX: AH [6048r,6112r:0)  0@6048r AL [6048r,6112r:0)  0@6048r

selectOrSplit GR64:%vreg944 [6080r,6096r:0)  0@6080r w=inf
assigning %vreg944 to %RCX: CH [6080r,6096r:0)  0@6080r CL [6080r,6096r:0)  0@6080r

selectOrSplit GR64:%vreg943 [6096r,6112r:0)  0@6096r w=inf
assigning %vreg943 to %RCX: CH [6096r,6112r:0)  0@6096r CL [6096r,6112r:0)  0@6096r

selectOrSplit GR32:%vreg908 [6112r,6512r:0)[6512r,6544r:1)  0@6112r 1@6512r w=1.355181e-05
assigning %vreg908 to %EAX: AH [6112r,6512r:0)[6512r,6544r:1)  0@6112r 1@6512r AL [6112r,6512r:0)[6512r,6544r:1)  0@6112r 1@6512r

selectOrSplit GR64:%vreg937 [6128r,6144r:0)  0@6128r w=inf
assigning %vreg937 to %RCX: CH [6128r,6144r:0)  0@6128r CL [6128r,6144r:0)  0@6128r

selectOrSplit GR32:%vreg934 [6144r,6176r:0)[6176r,6192r:1)  0@6144r 1@6176r w=inf
assigning %vreg934 to %ECX: CH [6144r,6176r:0)[6176r,6192r:1)  0@6144r 1@6176r CL [6144r,6176r:0)[6176r,6192r:1)  0@6144r 1@6176r

selectOrSplit GR64_NOSP:%vreg932 [6192r,6256r:0)  0@6192r w=1.214990e-05
assigning %vreg932 to %RCX: CH [6192r,6256r:0)  0@6192r CL [6192r,6256r:0)  0@6192r

selectOrSplit GR64:%vreg929 [6224r,6240r:0)  0@6224r w=inf
assigning %vreg929 to %RDX: DH [6224r,6240r:0)  0@6224r DL [6224r,6240r:0)  0@6224r

selectOrSplit GR64:%vreg928 [6240r,6256r:0)  0@6240r w=inf
assigning %vreg928 to %RDX: DH [6240r,6256r:0)  0@6240r DL [6240r,6256r:0)  0@6240r

selectOrSplit GR32:%vreg912 [6256r,6416r:2)[6416r,6448r:0)[6448r,6480r:1)[6480r,6512r:3)  0@6416r 1@6448r 2@6256r 3@6480r w=3.437533e-05
assigning %vreg912 to %EDX: DH [6256r,6416r:2)[6416r,6448r:0)[6448r,6480r:1)[6480r,6512r:3)  0@6416r 1@6448r 2@6256r 3@6480r DL [6256r,6416r:2)[6416r,6448r:0)[6448r,6480r:1)[6480r,6512r:3)  0@6416r 1@6448r 2@6256r 3@6480r

selectOrSplit GR64:%vreg922 [6272r,6288r:0)  0@6272r w=inf
assigning %vreg922 to %RCX: CH [6272r,6288r:0)  0@6272r CL [6272r,6288r:0)  0@6272r

selectOrSplit GR64:%vreg905 [6528r,6544r:0)  0@6528r w=inf
assigning %vreg905 to %RCX: CH [6528r,6544r:0)  0@6528r CL [6528r,6544r:0)  0@6528r

selectOrSplit GR64:%vreg902 [6560r,6576r:0)  0@6560r w=inf
assigning %vreg902 to %RAX: AH [6560r,6576r:0)  0@6560r AL [6560r,6576r:0)  0@6560r

selectOrSplit GR64:%vreg982 [6624r,6640r:0)  0@6624r w=inf
assigning %vreg982 to %RAX: AH [6624r,6640r:0)  0@6624r AL [6624r,6640r:0)  0@6624r

selectOrSplit GR64_NOSP:%vreg980 [6640r,6656r:0)  0@6640r w=inf
assigning %vreg980 to %RAX: AH [6640r,6656r:0)  0@6640r AL [6640r,6656r:0)  0@6640r

selectOrSplit GR32:%vreg978 [6656r,6688r:0)  0@6656r w=6.473569e-06
assigning %vreg978 to %EAX: AH [6656r,6688r:0)  0@6656r AL [6656r,6688r:0)  0@6656r

selectOrSplit GR64:%vreg976 [6672r,6688r:0)  0@6672r w=inf
assigning %vreg976 to %RCX: CH [6672r,6688r:0)  0@6672r CL [6672r,6688r:0)  0@6672r

selectOrSplit GR64:%vreg973 [6704r,6768r:0)  0@6704r w=9.040675e-06
assigning %vreg973 to %RAX: AH [6704r,6768r:0)  0@6704r AL [6704r,6768r:0)  0@6704r

selectOrSplit GR32:%vreg971 [6720r,6752r:0)[6752r,6768r:1)  0@6720r 1@6752r w=inf
assigning %vreg971 to %ECX: CH [6720r,6752r:0)[6752r,6768r:1)  0@6720r 1@6752r CL [6720r,6752r:0)[6752r,6768r:1)  0@6720r 1@6752r

selectOrSplit GR64:%vreg967 [6784r,6800r:0)  0@6784r w=inf
assigning %vreg967 to %RAX: AH [6784r,6800r:0)  0@6784r AL [6784r,6800r:0)  0@6784r

selectOrSplit GR64:%vreg984 [6848r,6864r:0)  0@6848r w=inf
assigning %vreg984 to %RAX: AH [6848r,6864r:0)  0@6848r AL [6848r,6864r:0)  0@6848r

selectOrSplit GR32:%vreg1012 [6928r,7088r:0)[7088r,7136r:1)  0@6928r 1@7088r w=1.854459e-05
assigning %vreg1012 to %EAX: AH [6928r,7088r:0)[7088r,7136r:1)  0@6928r 1@7088r AL [6928r,7088r:0)[7088r,7136r:1)  0@6928r 1@7088r

selectOrSplit GR32:%vreg1011 [6944r,7088r:0)  0@6944r w=5.181575e-06
assigning %vreg1011 to %ECX: CH [6944r,7088r:0)  0@6944r CL [6944r,7088r:0)  0@6944r

selectOrSplit GR64:%vreg1020 [6960r,7024r:0)  0@6960r w=1.822485e-05
assigning %vreg1020 to %RDX: DH [6960r,7024r:0)  0@6960r DL [6960r,7024r:0)  0@6960r

selectOrSplit GR32:%vreg1018 [6976r,7008r:0)[7008r,7024r:1)  0@6976r 1@7008r w=inf
assigning %vreg1018 to %ESI: SIL [6976r,7008r:0)[7008r,7024r:1)  0@6976r 1@7008r

selectOrSplit GR64:%vreg1014 [7040r,7056r:0)  0@7040r w=inf
assigning %vreg1014 to %RDX: DH [7040r,7056r:0)  0@7040r DL [7040r,7056r:0)  0@7040r

selectOrSplit GR32:%vreg1006 [7104r,7136r:0)[7136r,7168r:1)  0@7104r 1@7136r w=inf
assigning %vreg1006 to %ECX: CH [7104r,7136r:0)[7136r,7168r:1)  0@7104r 1@7136r CL [7104r,7136r:0)[7136r,7168r:1)  0@7104r 1@7136r

selectOrSplit GR64:%vreg1000 [7184r,7248r:0)  0@7184r w=1.822485e-05
assigning %vreg1000 to %RAX: AH [7184r,7248r:0)  0@7184r AL [7184r,7248r:0)  0@7184r

selectOrSplit GR32:%vreg998 [7200r,7232r:0)[7232r,7248r:1)  0@7200r 1@7232r w=inf
assigning %vreg998 to %ECX: CH [7200r,7232r:0)[7232r,7248r:1)  0@7200r 1@7232r CL [7200r,7232r:0)[7232r,7248r:1)  0@7200r 1@7232r

selectOrSplit GR64:%vreg994 [7264r,7280r:0)  0@7264r w=inf
assigning %vreg994 to %RAX: AH [7264r,7280r:0)  0@7264r AL [7264r,7280r:0)  0@7264r

selectOrSplit GR32:%vreg993 [7280r,7360r:0)  0@7280r w=1.174490e-05
assigning %vreg993 to %EAX: AH [7280r,7360r:0)  0@7280r AL [7280r,7360r:0)  0@7280r

selectOrSplit GR64:%vreg991 [7296r,7312r:0)  0@7296r w=inf
assigning %vreg991 to %RCX: CH [7296r,7312r:0)  0@7296r CL [7296r,7312r:0)  0@7296r

selectOrSplit GR32:%vreg988 [7312r,7344r:0)[7344r,7360r:1)  0@7312r 1@7344r w=inf
assigning %vreg988 to %ECX: CH [7312r,7344r:0)[7344r,7360r:1)  0@7312r 1@7344r CL [7312r,7344r:0)[7344r,7360r:1)  0@7312r 1@7344r

selectOrSplit GR32:%vreg1026 [7440r,7472r:0)  0@7440r w=6.473569e-06
assigning %vreg1026 to %EAX: AH [7440r,7472r:0)  0@7440r AL [7440r,7472r:0)  0@7440r

selectOrSplit GR64:%vreg1024 [7456r,7472r:0)  0@7456r w=inf
assigning %vreg1024 to %RCX: CH [7456r,7472r:0)  0@7456r CL [7456r,7472r:0)  0@7456r

selectOrSplit GR32:%vreg1254 [7520r,7552r:0)  0@7520r w=3.185407e-06
assigning %vreg1254 to %EAX: AH [7520r,7552r:0)  0@7520r AL [7520r,7552r:0)  0@7520r

selectOrSplit GR64:%vreg1252 [7536r,7552r:0)  0@7536r w=inf
assigning %vreg1252 to %RCX: CH [7536r,7552r:0)  0@7536r CL [7536r,7552r:0)  0@7536r

selectOrSplit GR64:%vreg1089 [7600r,7616r:0)  0@7600r w=inf
assigning %vreg1089 to %RAX: AH [7600r,7616r:0)  0@7600r AL [7600r,7616r:0)  0@7600r

selectOrSplit GR64:%vreg1076 [7856r,7872r:0)  0@7856r w=inf
assigning %vreg1076 to %RAX: AH [7856r,7872r:0)  0@7856r AL [7856r,7872r:0)  0@7856r

selectOrSplit GR64_NOSP:%vreg1074 [7872r,7936r:0)  0@7872r w=2.965724e-06
assigning %vreg1074 to %RAX: AH [7872r,7936r:0)  0@7872r AL [7872r,7936r:0)  0@7872r

selectOrSplit GR64:%vreg1071 [7904r,7920r:0)  0@7904r w=inf
assigning %vreg1071 to %RCX: CH [7904r,7920r:0)  0@7904r CL [7904r,7920r:0)  0@7904r

selectOrSplit GR64:%vreg1070 [7920r,7936r:0)  0@7920r w=inf
assigning %vreg1070 to %RCX: CH [7920r,7936r:0)  0@7920r CL [7920r,7936r:0)  0@7920r

selectOrSplit GR32:%vreg1035 [7936r,8336r:0)[8336r,8368r:1)  0@7936r 1@8336r w=3.307923e-06
assigning %vreg1035 to %EAX: AH [7936r,8336r:0)[8336r,8368r:1)  0@7936r 1@8336r AL [7936r,8336r:0)[8336r,8368r:1)  0@7936r 1@8336r

selectOrSplit GR64:%vreg1064 [7952r,7968r:0)  0@7952r w=inf
assigning %vreg1064 to %RCX: CH [7952r,7968r:0)  0@7952r CL [7952r,7968r:0)  0@7952r

selectOrSplit GR32:%vreg1061 [7968r,8000r:0)[8000r,8016r:1)  0@7968r 1@8000r w=inf
assigning %vreg1061 to %ECX: CH [7968r,8000r:0)[8000r,8016r:1)  0@7968r 1@8000r CL [7968r,8000r:0)[8000r,8016r:1)  0@7968r 1@8000r

selectOrSplit GR64_NOSP:%vreg1059 [8016r,8080r:0)  0@8016r w=2.965724e-06
assigning %vreg1059 to %RCX: CH [8016r,8080r:0)  0@8016r CL [8016r,8080r:0)  0@8016r

selectOrSplit GR64:%vreg1056 [8048r,8064r:0)  0@8048r w=inf
assigning %vreg1056 to %RDX: DH [8048r,8064r:0)  0@8048r DL [8048r,8064r:0)  0@8048r

selectOrSplit GR64:%vreg1055 [8064r,8080r:0)  0@8064r w=inf
assigning %vreg1055 to %RDX: DH [8064r,8080r:0)  0@8064r DL [8064r,8080r:0)  0@8064r

selectOrSplit GR32:%vreg1039 [8080r,8240r:2)[8240r,8272r:0)[8272r,8304r:1)[8304r,8336r:3)  0@8240r 1@8272r 2@8080r 3@8304r w=8.390828e-06
assigning %vreg1039 to %EDX: DH [8080r,8240r:2)[8240r,8272r:0)[8272r,8304r:1)[8304r,8336r:3)  0@8240r 1@8272r 2@8080r 3@8304r DL [8080r,8240r:2)[8240r,8272r:0)[8272r,8304r:1)[8304r,8336r:3)  0@8240r 1@8272r 2@8080r 3@8304r

selectOrSplit GR64:%vreg1049 [8096r,8112r:0)  0@8096r w=inf
assigning %vreg1049 to %RCX: CH [8096r,8112r:0)  0@8096r CL [8096r,8112r:0)  0@8096r

selectOrSplit GR64:%vreg1032 [8352r,8368r:0)  0@8352r w=inf
assigning %vreg1032 to %RCX: CH [8352r,8368r:0)  0@8352r CL [8352r,8368r:0)  0@8352r

selectOrSplit GR64:%vreg1029 [8384r,8400r:0)  0@8384r w=inf
assigning %vreg1029 to %RAX: AH [8384r,8400r:0)  0@8384r AL [8384r,8400r:0)  0@8384r

selectOrSplit GR64:%vreg1107 [8448r,8464r:0)  0@8448r w=inf
assigning %vreg1107 to %RAX: AH [8448r,8464r:0)  0@8448r AL [8448r,8464r:0)  0@8448r

selectOrSplit GR64_NOSP:%vreg1105 [8464r,8480r:0)  0@8464r w=inf
assigning %vreg1105 to %RAX: AH [8464r,8480r:0)  0@8464r AL [8464r,8480r:0)  0@8464r

selectOrSplit GR32:%vreg1103 [8480r,8512r:0)  0@8480r w=1.644081e-06
assigning %vreg1103 to %EAX: AH [8480r,8512r:0)  0@8480r AL [8480r,8512r:0)  0@8480r

selectOrSplit GR64:%vreg1101 [8496r,8512r:0)  0@8496r w=inf
assigning %vreg1101 to %RCX: CH [8496r,8512r:0)  0@8496r CL [8496r,8512r:0)  0@8496r

selectOrSplit GR64:%vreg1098 [8528r,8592r:0)  0@8528r w=2.296044e-06
assigning %vreg1098 to %RAX: AH [8528r,8592r:0)  0@8528r AL [8528r,8592r:0)  0@8528r

selectOrSplit GR32:%vreg1096 [8544r,8576r:0)[8576r,8592r:1)  0@8544r 1@8576r w=inf
assigning %vreg1096 to %ECX: CH [8544r,8576r:0)[8576r,8592r:1)  0@8544r 1@8576r CL [8544r,8576r:0)[8576r,8592r:1)  0@8544r 1@8576r

selectOrSplit GR64:%vreg1092 [8608r,8624r:0)  0@8608r w=inf
assigning %vreg1092 to %RAX: AH [8608r,8624r:0)  0@8608r AL [8608r,8624r:0)  0@8608r

selectOrSplit GR64:%vreg1109 [8672r,8688r:0)  0@8672r w=inf
assigning %vreg1109 to %RAX: AH [8672r,8688r:0)  0@8672r AL [8672r,8688r:0)  0@8672r

selectOrSplit GR32:%vreg1197 [8752r,8912r:0)[8912r,8960r:1)  0@8752r 1@8912r w=4.526631e-06
assigning %vreg1197 to %EAX: AH [8752r,8912r:0)[8912r,8960r:1)  0@8752r 1@8912r AL [8752r,8912r:0)[8912r,8960r:1)  0@8752r 1@8912r

selectOrSplit GR32:%vreg1196 [8768r,8912r:0)  0@8768r w=1.264794e-06
assigning %vreg1196 to %ECX: CH [8768r,8912r:0)  0@8768r CL [8768r,8912r:0)  0@8768r

selectOrSplit GR64:%vreg1205 [8784r,8848r:0)  0@8784r w=4.448586e-06
assigning %vreg1205 to %RDX: DH [8784r,8848r:0)  0@8784r DL [8784r,8848r:0)  0@8784r

selectOrSplit GR32:%vreg1203 [8800r,8832r:0)[8832r,8848r:1)  0@8800r 1@8832r w=inf
assigning %vreg1203 to %ESI: SIL [8800r,8832r:0)[8832r,8848r:1)  0@8800r 1@8832r

selectOrSplit GR64:%vreg1199 [8864r,8880r:0)  0@8864r w=inf
assigning %vreg1199 to %RDX: DH [8864r,8880r:0)  0@8864r DL [8864r,8880r:0)  0@8864r

selectOrSplit GR32:%vreg1191 [8928r,8960r:0)[8960r,8992r:1)  0@8928r 1@8960r w=inf
assigning %vreg1191 to %ECX: CH [8928r,8960r:0)[8960r,8992r:1)  0@8928r 1@8960r CL [8928r,8960r:0)[8960r,8992r:1)  0@8928r 1@8960r

selectOrSplit GR64:%vreg1185 [9008r,9072r:0)  0@9008r w=4.448586e-06
assigning %vreg1185 to %RAX: AH [9008r,9072r:0)  0@9008r AL [9008r,9072r:0)  0@9008r

selectOrSplit GR32:%vreg1183 [9024r,9056r:0)[9056r,9072r:1)  0@9024r 1@9056r w=inf
assigning %vreg1183 to %ECX: CH [9024r,9056r:0)[9056r,9072r:1)  0@9024r 1@9056r CL [9024r,9056r:0)[9056r,9072r:1)  0@9024r 1@9056r

selectOrSplit GR32:%vreg1177 [9088r,9120r:0)[9120r,9152r:1)  0@9088r 1@9120r w=5.931448e-06
assigning %vreg1177 to %EAX: AH [9088r,9120r:0)[9120r,9152r:1)  0@9088r 1@9120r AL [9088r,9120r:0)[9120r,9152r:1)  0@9088r 1@9120r

selectOrSplit GR64:%vreg1175 [9136r,9152r:0)  0@9136r w=inf
assigning %vreg1175 to %RCX: CH [9136r,9152r:0)  0@9136r CL [9136r,9152r:0)  0@9136r

selectOrSplit GR64:%vreg1172 [9168r,9184r:0)  0@9168r w=inf
assigning %vreg1172 to %RAX: AH [9168r,9184r:0)  0@9168r AL [9168r,9184r:0)  0@9168r

selectOrSplit GR64:%vreg1162 [9392r,9408r:0)  0@9392r w=inf
assigning %vreg1162 to %RCX: CH [9392r,9408r:0)  0@9392r CL [9392r,9408r:0)  0@9392r

selectOrSplit GR64:%vreg1159 [9424r,9440r:0)  0@9424r w=inf
assigning %vreg1159 to %RAX: AH [9424r,9440r:0)  0@9424r AL [9424r,9440r:0)  0@9424r

selectOrSplit GR64_NOSP:%vreg1157 [9440r,9504r:0)  0@9440r w=2.965724e-06
assigning %vreg1157 to %RAX: AH [9440r,9504r:0)  0@9440r AL [9440r,9504r:0)  0@9440r

selectOrSplit GR64:%vreg1154 [9472r,9488r:0)  0@9472r w=inf
assigning %vreg1154 to %RCX: CH [9472r,9488r:0)  0@9472r CL [9472r,9488r:0)  0@9472r

selectOrSplit GR64:%vreg1153 [9488r,9504r:0)  0@9488r w=inf
assigning %vreg1153 to %RCX: CH [9488r,9504r:0)  0@9488r CL [9488r,9504r:0)  0@9488r

selectOrSplit GR32:%vreg1118 [9504r,9904r:0)[9904r,9936r:1)  0@9504r 1@9904r w=3.307923e-06
assigning %vreg1118 to %EAX: AH [9504r,9904r:0)[9904r,9936r:1)  0@9504r 1@9904r AL [9504r,9904r:0)[9904r,9936r:1)  0@9504r 1@9904r

selectOrSplit GR64:%vreg1147 [9520r,9536r:0)  0@9520r w=inf
assigning %vreg1147 to %RCX: CH [9520r,9536r:0)  0@9520r CL [9520r,9536r:0)  0@9520r

selectOrSplit GR32:%vreg1144 [9536r,9568r:0)[9568r,9584r:1)  0@9536r 1@9568r w=inf
assigning %vreg1144 to %ECX: CH [9536r,9568r:0)[9568r,9584r:1)  0@9536r 1@9568r CL [9536r,9568r:0)[9568r,9584r:1)  0@9536r 1@9568r

selectOrSplit GR64_NOSP:%vreg1142 [9584r,9648r:0)  0@9584r w=2.965724e-06
assigning %vreg1142 to %RCX: CH [9584r,9648r:0)  0@9584r CL [9584r,9648r:0)  0@9584r

selectOrSplit GR64:%vreg1139 [9616r,9632r:0)  0@9616r w=inf
assigning %vreg1139 to %RDX: DH [9616r,9632r:0)  0@9616r DL [9616r,9632r:0)  0@9616r

selectOrSplit GR64:%vreg1138 [9632r,9648r:0)  0@9632r w=inf
assigning %vreg1138 to %RDX: DH [9632r,9648r:0)  0@9632r DL [9632r,9648r:0)  0@9632r

selectOrSplit GR32:%vreg1122 [9648r,9808r:2)[9808r,9840r:0)[9840r,9872r:1)[9872r,9904r:3)  0@9808r 1@9840r 2@9648r 3@9872r w=8.390828e-06
assigning %vreg1122 to %EDX: DH [9648r,9808r:2)[9808r,9840r:0)[9840r,9872r:1)[9872r,9904r:3)  0@9808r 1@9840r 2@9648r 3@9872r DL [9648r,9808r:2)[9808r,9840r:0)[9840r,9872r:1)[9872r,9904r:3)  0@9808r 1@9840r 2@9648r 3@9872r

selectOrSplit GR64:%vreg1132 [9664r,9680r:0)  0@9664r w=inf
assigning %vreg1132 to %RCX: CH [9664r,9680r:0)  0@9664r CL [9664r,9680r:0)  0@9664r

selectOrSplit GR64:%vreg1115 [9920r,9936r:0)  0@9920r w=inf
assigning %vreg1115 to %RCX: CH [9920r,9936r:0)  0@9920r CL [9920r,9936r:0)  0@9920r

selectOrSplit GR64:%vreg1112 [9952r,9968r:0)  0@9952r w=inf
assigning %vreg1112 to %RAX: AH [9952r,9968r:0)  0@9952r AL [9952r,9968r:0)  0@9952r

selectOrSplit GR64:%vreg1223 [10016r,10032r:0)  0@10016r w=inf
assigning %vreg1223 to %RAX: AH [10016r,10032r:0)  0@10016r AL [10016r,10032r:0)  0@10016r

selectOrSplit GR64_NOSP:%vreg1221 [10032r,10048r:0)  0@10032r w=inf
assigning %vreg1221 to %RAX: AH [10032r,10048r:0)  0@10032r AL [10032r,10048r:0)  0@10032r

selectOrSplit GR32:%vreg1219 [10048r,10080r:0)  0@10048r w=1.644081e-06
assigning %vreg1219 to %EAX: AH [10048r,10080r:0)  0@10048r AL [10048r,10080r:0)  0@10048r

selectOrSplit GR64:%vreg1217 [10064r,10080r:0)  0@10064r w=inf
assigning %vreg1217 to %RCX: CH [10064r,10080r:0)  0@10064r CL [10064r,10080r:0)  0@10064r

selectOrSplit GR64:%vreg1214 [10096r,10160r:0)  0@10096r w=2.296044e-06
assigning %vreg1214 to %RAX: AH [10096r,10160r:0)  0@10096r AL [10096r,10160r:0)  0@10096r

selectOrSplit GR32:%vreg1212 [10112r,10144r:0)[10144r,10160r:1)  0@10112r 1@10144r w=inf
assigning %vreg1212 to %ECX: CH [10112r,10144r:0)[10144r,10160r:1)  0@10112r 1@10144r CL [10112r,10144r:0)[10144r,10160r:1)  0@10112r 1@10144r

selectOrSplit GR64:%vreg1208 [10176r,10192r:0)  0@10176r w=inf
assigning %vreg1208 to %RAX: AH [10176r,10192r:0)  0@10176r AL [10176r,10192r:0)  0@10176r

selectOrSplit GR64:%vreg1225 [10240r,10256r:0)  0@10240r w=inf
assigning %vreg1225 to %RAX: AH [10240r,10256r:0)  0@10240r AL [10240r,10256r:0)  0@10240r

selectOrSplit GR32:%vreg1236 [10320r,10480r:2)[10480r,10528r:0)[10528r,10544r:1)  0@10480r 1@10528r 2@10320r w=6.615845e-06
assigning %vreg1236 to %EAX: AH [10320r,10480r:2)[10480r,10528r:0)[10528r,10544r:1)  0@10480r 1@10528r 2@10320r AL [10320r,10480r:2)[10480r,10528r:0)[10528r,10544r:1)  0@10480r 1@10528r 2@10320r

selectOrSplit GR32:%vreg1240 [10336r,10480r:0)  0@10336r w=1.264794e-06
assigning %vreg1240 to %ECX: CH [10336r,10480r:0)  0@10336r CL [10336r,10480r:0)  0@10336r

selectOrSplit GR64:%vreg1249 [10352r,10416r:0)  0@10352r w=4.448586e-06
assigning %vreg1249 to %RDX: DH [10352r,10416r:0)  0@10352r DL [10352r,10416r:0)  0@10352r

selectOrSplit GR32:%vreg1247 [10368r,10400r:0)[10400r,10416r:1)  0@10368r 1@10400r w=inf
assigning %vreg1247 to %ESI: SIL [10368r,10400r:0)[10400r,10416r:1)  0@10368r 1@10400r

selectOrSplit GR64:%vreg1243 [10432r,10448r:0)  0@10432r w=inf
assigning %vreg1243 to %RDX: DH [10432r,10448r:0)  0@10432r DL [10432r,10448r:0)  0@10432r

selectOrSplit GR64:%vreg1237 [10496r,10544r:0)  0@10496r w=4.607464e-06
assigning %vreg1237 to %RCX: CH [10496r,10544r:0)  0@10496r CL [10496r,10544r:0)  0@10496r

selectOrSplit GR64:%vreg1231 [10560r,10624r:0)  0@10560r w=4.448586e-06
assigning %vreg1231 to %RAX: AH [10560r,10624r:0)  0@10560r AL [10560r,10624r:0)  0@10560r

selectOrSplit GR32:%vreg1229 [10576r,10608r:0)[10608r,10624r:1)  0@10576r 1@10608r w=inf
assigning %vreg1229 to %ECX: CH [10576r,10608r:0)[10608r,10624r:1)  0@10576r 1@10608r CL [10576r,10608r:0)[10608r,10624r:1)  0@10576r 1@10608r

selectOrSplit GR64:%vreg12 [10736r,10752r:0)  0@10736r w=inf
assigning %vreg12 to %RAX: AH [10736r,10752r:0)  0@10736r AL [10736r,10752r:0)  0@10736r

selectOrSplit GR64:%vreg11 [10752r,10768r:0)  0@10752r w=inf
assigning %vreg11 to %RAX: AH [10752r,10768r:0)  0@10752r AL [10752r,10768r:0)  0@10752r

selectOrSplit GR64:%vreg15 [10864r,10880r:0)  0@10864r w=inf
assigning %vreg15 to %RAX: AH [10864r,10880r:0)  0@10864r AL [10864r,10880r:0)  0@10864r

selectOrSplit GR64:%vreg87 [10960r,10976r:0)  0@10960r w=inf
assigning %vreg87 to %RAX: AH [10960r,10976r:0)  0@10960r AL [10960r,10976r:0)  0@10960r

selectOrSplit GR8:%vreg86 [10976r,11040r:0)  0@10976r w=7.836208e-04
assigning %vreg86 to %AL: AL [10976r,11040r:0)  0@10976r

selectOrSplit GR64:%vreg84 [10992r,11008r:0)  0@10992r w=inf
assigning %vreg84 to %RCX: CH [10992r,11008r:0)  0@10992r CL [10992r,11008r:0)  0@10992r

selectOrSplit GR64:%vreg83 [11008r,11024r:0)  0@11008r w=inf
assigning %vreg83 to %RCX: CH [11008r,11024r:0)  0@11008r CL [11008r,11024r:0)  0@11008r

selectOrSplit GR64:%vreg81 [11024r,11040r:0)  0@11024r w=inf
assigning %vreg81 to %RCX: CH [11024r,11040r:0)  0@11024r CL [11024r,11040r:0)  0@11024r

selectOrSplit GR64:%vreg77 [11056r,11072r:0)  0@11056r w=inf
assigning %vreg77 to %RAX: AH [11056r,11072r:0)  0@11056r AL [11056r,11072r:0)  0@11056r

selectOrSplit GR32:%vreg56 [11072r,11104r:2)[11104r,11296r:0)[11296r,11328r:1)  0@11104r 1@11296r 2@11072r w=1.662805e-03
assigning %vreg56 to %EAX: AH [11072r,11104r:2)[11104r,11296r:0)[11296r,11328r:1)  0@11104r 1@11296r 2@11072r AL [11072r,11104r:2)[11104r,11296r:0)[11296r,11328r:1)  0@11104r 1@11296r 2@11072r

selectOrSplit GR64:%vreg72 [11120r,11136r:0)  0@11120r w=inf
assigning %vreg72 to %RCX: CH [11120r,11136r:0)  0@11120r CL [11120r,11136r:0)  0@11120r

selectOrSplit GR32:%vreg63 [11136r,11168r:2)[11168r,11232r:0)[11232r,11248r:1)  0@11168r 1@11232r 2@11136r w=2.130469e-03
assigning %vreg63 to %ECX: CH [11136r,11168r:2)[11168r,11232r:0)[11232r,11248r:1)  0@11168r 1@11232r 2@11136r CL [11136r,11168r:2)[11168r,11232r:0)[11232r,11248r:1)  0@11168r 1@11232r 2@11136r

selectOrSplit GR64:%vreg67 [11184r,11200r:0)  0@11184r w=inf
assigning %vreg67 to %RDX: DH [11184r,11200r:0)  0@11184r DL [11184r,11200r:0)  0@11184r

selectOrSplit GR32:%vreg65 [11200r,11232r:0)  0@11200r w=inf
assigning %vreg65 to %EDX: DH [11200r,11232r:0)  0@11200r DL [11200r,11232r:0)  0@11200r

selectOrSplit GR64_NOSP:%vreg60 [11248r,11296r:0)  0@11248r w=inf
assigning %vreg60 to %RCX: CH [11248r,11296r:0)  0@11248r CL [11248r,11296r:0)  0@11248r

selectOrSplit GR64:%vreg53 [11312r,11328r:0)  0@11312r w=inf
assigning %vreg53 to %RCX: CH [11312r,11328r:0)  0@11312r CL [11312r,11328r:0)  0@11312r

selectOrSplit GR64:%vreg50 [11344r,11408r:0)  0@11344r w=1.175431e-03
assigning %vreg50 to %RAX: AH [11344r,11408r:0)  0@11344r AL [11344r,11408r:0)  0@11344r

selectOrSplit GR32:%vreg48 [11360r,11392r:0)[11392r,11408r:1)  0@11360r 1@11392r w=inf
assigning %vreg48 to %ECX: CH [11360r,11392r:0)[11392r,11408r:1)  0@11360r 1@11392r CL [11360r,11392r:0)[11392r,11408r:1)  0@11360r 1@11392r

selectOrSplit GR64:%vreg44 [11424r,11440r:0)  0@11424r w=inf
assigning %vreg44 to %RAX: AH [11424r,11440r:0)  0@11424r AL [11424r,11440r:0)  0@11424r

selectOrSplit GR64:%vreg43 [11440r,11504r:0)  0@11440r w=1.175431e-03
assigning %vreg43 to %RAX: AH [11440r,11504r:0)  0@11440r AL [11440r,11504r:0)  0@11440r

selectOrSplit GR64:%vreg40 [11456r,11488r:0)[11488r,11504r:1)  0@11456r 1@11488r w=inf
assigning %vreg40 to %RCX: CH [11456r,11488r:0)[11488r,11504r:1)  0@11456r 1@11488r CL [11456r,11488r:0)[11488r,11504r:1)  0@11456r 1@11488r

selectOrSplit GR64:%vreg36 [11520r,11536r:0)  0@11520r w=inf
assigning %vreg36 to %RAX: AH [11520r,11536r:0)  0@11520r AL [11520r,11536r:0)  0@11520r

selectOrSplit GR64:%vreg35 [11536r,11600r:0)  0@11536r w=1.175431e-03
assigning %vreg35 to %RAX: AH [11536r,11600r:0)  0@11536r AL [11536r,11600r:0)  0@11536r

selectOrSplit GR32:%vreg32 [11552r,11584r:0)[11584r,11600r:1)  0@11552r 1@11584r w=inf
assigning %vreg32 to %ECX: CH [11552r,11584r:0)[11584r,11600r:1)  0@11552r 1@11584r CL [11552r,11584r:0)[11584r,11600r:1)  0@11552r 1@11584r

selectOrSplit GR64:%vreg28 [11616r,11632r:0)  0@11616r w=inf
assigning %vreg28 to %RAX: AH [11616r,11632r:0)  0@11616r AL [11616r,11632r:0)  0@11616r

selectOrSplit GR64:%vreg27 [11632r,11696r:0)  0@11632r w=1.175431e-03
assigning %vreg27 to %RAX: AH [11632r,11696r:0)  0@11632r AL [11632r,11696r:0)  0@11632r

selectOrSplit GR32:%vreg24 [11648r,11680r:0)[11680r,11696r:1)  0@11648r 1@11680r w=inf
assigning %vreg24 to %ECX: CH [11648r,11680r:0)[11680r,11696r:1)  0@11648r 1@11680r CL [11648r,11680r:0)[11680r,11696r:1)  0@11648r 1@11680r

selectOrSplit GR64:%vreg20 [11712r,11728r:0)  0@11712r w=inf
assigning %vreg20 to %RAX: AH [11712r,11728r:0)  0@11712r AL [11712r,11728r:0)  0@11712r

selectOrSplit GR64:%vreg19 [11728r,11744r:0)  0@11728r w=inf
assigning %vreg19 to %RAX: AH [11728r,11744r:0)  0@11728r AL [11728r,11744r:0)  0@11728r

selectOrSplit GR64:%vreg95 [11792r,11808r:0)  0@11792r w=inf
assigning %vreg95 to %RAX: AH [11792r,11808r:0)  0@11792r AL [11792r,11808r:0)  0@11792r

selectOrSplit GR64:%vreg94 [11808r,11872r:0)  0@11808r w=5.876438e-04
assigning %vreg94 to %RAX: AH [11808r,11872r:0)  0@11808r AL [11808r,11872r:0)  0@11808r

selectOrSplit GR32:%vreg91 [11824r,11856r:0)[11856r,11872r:1)  0@11824r 1@11856r w=inf
assigning %vreg91 to %ECX: CH [11824r,11856r:0)[11856r,11872r:1)  0@11824r 1@11856r CL [11824r,11856r:0)[11856r,11872r:1)  0@11824r 1@11856r

selectOrSplit GR64:%vreg105 [11936r,11952r:0)  0@11936r w=inf
assigning %vreg105 to %RAX: AH [11936r,11952r:0)  0@11936r AL [11936r,11952r:0)  0@11936r

selectOrSplit GR32:%vreg104 [11952r,12032r:0)  0@11952r w=7.575001e-04
assigning %vreg104 to %EAX: AH [11952r,12032r:0)  0@11952r AL [11952r,12032r:0)  0@11952r

selectOrSplit GR64:%vreg102 [11968r,11984r:0)  0@11968r w=inf
assigning %vreg102 to %RCX: CH [11968r,11984r:0)  0@11968r CL [11968r,11984r:0)  0@11968r

selectOrSplit GR32:%vreg99 [11984r,12016r:0)[12016r,12032r:1)  0@11984r 1@12016r w=inf
assigning %vreg99 to %ECX: CH [11984r,12016r:0)[12016r,12032r:1)  0@11984r 1@12016r CL [11984r,12016r:0)[12016r,12032r:1)  0@11984r 1@12016r

selectOrSplit GR64:%vreg115 [12128r,12144r:0)  0@12128r w=inf
assigning %vreg115 to %RAX: AH [12128r,12144r:0)  0@12128r AL [12128r,12144r:0)  0@12128r

selectOrSplit GR32:%vreg114 [12144r,12224r:0)  0@12144r w=3.787038e-04
assigning %vreg114 to %EAX: AH [12144r,12224r:0)  0@12144r AL [12144r,12224r:0)  0@12144r

selectOrSplit GR64:%vreg112 [12160r,12176r:0)  0@12160r w=inf
assigning %vreg112 to %RCX: CH [12160r,12176r:0)  0@12160r CL [12160r,12176r:0)  0@12160r

selectOrSplit GR32:%vreg109 [12176r,12208r:0)[12208r,12224r:1)  0@12176r 1@12208r w=inf
assigning %vreg109 to %ECX: CH [12176r,12208r:0)[12208r,12224r:1)  0@12176r 1@12208r CL [12176r,12208r:0)[12208r,12224r:1)  0@12176r 1@12208r

selectOrSplit GR64:%vreg201 [12320r,12336r:0)  0@12320r w=inf
assigning %vreg201 to %RAX: AH [12320r,12336r:0)  0@12320r AL [12320r,12336r:0)  0@12320r

selectOrSplit GR64:%vreg199 [12352r,12368r:0)  0@12352r w=inf
assigning %vreg199 to %RAX: AH [12352r,12368r:0)  0@12352r AL [12352r,12368r:0)  0@12352r

selectOrSplit GR32:%vreg198 [12368r,12416r:0)  0@12368r w=2.028275e-04
assigning %vreg198 to %EAX: AH [12368r,12416r:0)  0@12368r AL [12368r,12416r:0)  0@12368r

selectOrSplit GR64:%vreg194 [12400r,12416r:0)  0@12400r w=inf
assigning %vreg194 to %RCX: CH [12400r,12416r:0)  0@12400r CL [12400r,12416r:0)  0@12400r

selectOrSplit GR64:%vreg191 [12432r,12448r:0)  0@12432r w=inf
assigning %vreg191 to %RAX: AH [12432r,12448r:0)  0@12432r AL [12432r,12448r:0)  0@12432r

selectOrSplit GR64:%vreg178 [12688r,12704r:0)  0@12688r w=inf
assigning %vreg178 to %RAX: AH [12688r,12704r:0)  0@12688r AL [12688r,12704r:0)  0@12688r

selectOrSplit GR64_NOSP:%vreg176 [12704r,12768r:0)  0@12704r w=1.958334e-04
assigning %vreg176 to %RAX: AH [12704r,12768r:0)  0@12704r AL [12704r,12768r:0)  0@12704r

selectOrSplit GR64:%vreg173 [12736r,12752r:0)  0@12736r w=inf
assigning %vreg173 to %RCX: CH [12736r,12752r:0)  0@12736r CL [12736r,12752r:0)  0@12736r

selectOrSplit GR64:%vreg172 [12752r,12768r:0)  0@12752r w=inf
assigning %vreg172 to %RCX: CH [12752r,12768r:0)  0@12752r CL [12752r,12768r:0)  0@12752r

selectOrSplit GR32:%vreg137 [12768r,13168r:0)[13168r,13200r:1)  0@12768r 1@13168r w=2.184296e-04
assigning %vreg137 to %EAX: AH [12768r,13168r:0)[13168r,13200r:1)  0@12768r 1@13168r AL [12768r,13168r:0)[13168r,13200r:1)  0@12768r 1@13168r

selectOrSplit GR64:%vreg166 [12784r,12800r:0)  0@12784r w=inf
assigning %vreg166 to %RCX: CH [12784r,12800r:0)  0@12784r CL [12784r,12800r:0)  0@12784r

selectOrSplit GR32:%vreg163 [12800r,12832r:0)[12832r,12848r:1)  0@12800r 1@12832r w=inf
assigning %vreg163 to %ECX: CH [12800r,12832r:0)[12832r,12848r:1)  0@12800r 1@12832r CL [12800r,12832r:0)[12832r,12848r:1)  0@12800r 1@12832r

selectOrSplit GR64_NOSP:%vreg161 [12848r,12912r:0)  0@12848r w=1.958334e-04
assigning %vreg161 to %RCX: CH [12848r,12912r:0)  0@12848r CL [12848r,12912r:0)  0@12848r

selectOrSplit GR64:%vreg158 [12880r,12896r:0)  0@12880r w=inf
assigning %vreg158 to %RDX: DH [12880r,12896r:0)  0@12880r DL [12880r,12896r:0)  0@12880r

selectOrSplit GR64:%vreg157 [12896r,12912r:0)  0@12896r w=inf
assigning %vreg157 to %RDX: DH [12896r,12912r:0)  0@12896r DL [12896r,12912r:0)  0@12896r

selectOrSplit GR32:%vreg141 [12912r,13072r:2)[13072r,13104r:0)[13104r,13136r:1)[13136r,13168r:3)  0@13072r 1@13104r 2@12912r 3@13136r w=5.540653e-04
assigning %vreg141 to %EDX: DH [12912r,13072r:2)[13072r,13104r:0)[13104r,13136r:1)[13136r,13168r:3)  0@13072r 1@13104r 2@12912r 3@13136r DL [12912r,13072r:2)[13072r,13104r:0)[13104r,13136r:1)[13136r,13168r:3)  0@13072r 1@13104r 2@12912r 3@13136r

selectOrSplit GR64:%vreg151 [12928r,12944r:0)  0@12928r w=inf
assigning %vreg151 to %RCX: CH [12928r,12944r:0)  0@12928r CL [12928r,12944r:0)  0@12928r

selectOrSplit GR64:%vreg134 [13184r,13200r:0)  0@13184r w=inf
assigning %vreg134 to %RCX: CH [13184r,13200r:0)  0@13184r CL [13184r,13200r:0)  0@13184r

selectOrSplit GR64:%vreg131 [13216r,13280r:0)  0@13216r w=2.937501e-04
assigning %vreg131 to %RAX: AH [13216r,13280r:0)  0@13216r AL [13216r,13280r:0)  0@13216r

selectOrSplit GR32:%vreg129 [13232r,13264r:0)[13264r,13280r:1)  0@13232r 1@13264r w=inf
assigning %vreg129 to %ECX: CH [13232r,13264r:0)[13264r,13280r:1)  0@13232r 1@13264r CL [13232r,13264r:0)[13264r,13280r:1)  0@13232r 1@13264r

selectOrSplit GR64:%vreg125 [13296r,13312r:0)  0@13296r w=inf
assigning %vreg125 to %RAX: AH [13296r,13312r:0)  0@13296r AL [13296r,13312r:0)  0@13296r

selectOrSplit GR32:%vreg124 [13312r,13392r:0)  0@13312r w=1.893057e-04
assigning %vreg124 to %EAX: AH [13312r,13392r:0)  0@13312r AL [13312r,13392r:0)  0@13312r

selectOrSplit GR64:%vreg122 [13328r,13344r:0)  0@13328r w=inf
assigning %vreg122 to %RCX: CH [13328r,13344r:0)  0@13328r CL [13328r,13344r:0)  0@13328r

selectOrSplit GR32:%vreg119 [13344r,13376r:0)[13376r,13392r:1)  0@13344r 1@13376r w=inf
assigning %vreg119 to %ECX: CH [13344r,13376r:0)[13376r,13392r:1)  0@13344r 1@13376r CL [13344r,13376r:0)[13376r,13392r:1)  0@13344r 1@13376r

selectOrSplit GR32:%vreg207 [13472r,13504r:0)  0@13472r w=1.051184e-04
assigning %vreg207 to %EAX: AH [13472r,13504r:0)  0@13472r AL [13472r,13504r:0)  0@13472r

selectOrSplit GR64:%vreg205 [13488r,13504r:0)  0@13488r w=inf
assigning %vreg205 to %RCX: CH [13488r,13504r:0)  0@13488r CL [13488r,13504r:0)  0@13488r

selectOrSplit GR32:%vreg529 [13552r,13584r:0)  0@13552r w=5.250784e-05
assigning %vreg529 to %EAX: AH [13552r,13584r:0)  0@13552r AL [13552r,13584r:0)  0@13552r

selectOrSplit GR64:%vreg527 [13568r,13584r:0)  0@13568r w=inf
assigning %vreg527 to %RCX: CH [13568r,13584r:0)  0@13568r CL [13568r,13584r:0)  0@13568r

selectOrSplit GR64:%vreg285 [13632r,13648r:0)  0@13632r w=inf
assigning %vreg285 to %RAX: AH [13632r,13648r:0)  0@13632r AL [13632r,13648r:0)  0@13632r

selectOrSplit GR64:%vreg283 [13664r,13680r:0)  0@13664r w=inf
assigning %vreg283 to %RAX: AH [13664r,13680r:0)  0@13664r AL [13664r,13680r:0)  0@13664r

selectOrSplit GR64:%vreg270 [13920r,13936r:0)  0@13920r w=inf
assigning %vreg270 to %RAX: AH [13920r,13936r:0)  0@13920r AL [13920r,13936r:0)  0@13920r

selectOrSplit GR64_NOSP:%vreg268 [13936r,14000r:0)  0@13936r w=4.888661e-05
assigning %vreg268 to %RAX: AH [13936r,14000r:0)  0@13936r AL [13936r,14000r:0)  0@13936r

selectOrSplit GR64:%vreg265 [13968r,13984r:0)  0@13968r w=inf
assigning %vreg265 to %RCX: CH [13968r,13984r:0)  0@13968r CL [13968r,13984r:0)  0@13968r

selectOrSplit GR64:%vreg264 [13984r,14000r:0)  0@13984r w=inf
assigning %vreg264 to %RCX: CH [13984r,14000r:0)  0@13984r CL [13984r,14000r:0)  0@13984r

selectOrSplit GR32:%vreg229 [14000r,14400r:0)[14400r,14432r:1)  0@14000r 1@14400r w=5.452737e-05
assigning %vreg229 to %EAX: AH [14000r,14400r:0)[14400r,14432r:1)  0@14000r 1@14400r AL [14000r,14400r:0)[14400r,14432r:1)  0@14000r 1@14400r

selectOrSplit GR64:%vreg258 [14016r,14032r:0)  0@14016r w=inf
assigning %vreg258 to %RCX: CH [14016r,14032r:0)  0@14016r CL [14016r,14032r:0)  0@14016r

selectOrSplit GR32:%vreg255 [14032r,14064r:0)[14064r,14080r:1)  0@14032r 1@14064r w=inf
assigning %vreg255 to %ECX: CH [14032r,14064r:0)[14064r,14080r:1)  0@14032r 1@14064r CL [14032r,14064r:0)[14064r,14080r:1)  0@14032r 1@14064r

selectOrSplit GR64_NOSP:%vreg253 [14080r,14144r:0)  0@14080r w=4.888661e-05
assigning %vreg253 to %RCX: CH [14080r,14144r:0)  0@14080r CL [14080r,14144r:0)  0@14080r

selectOrSplit GR64:%vreg250 [14112r,14128r:0)  0@14112r w=inf
assigning %vreg250 to %RDX: DH [14112r,14128r:0)  0@14112r DL [14112r,14128r:0)  0@14112r

selectOrSplit GR64:%vreg249 [14128r,14144r:0)  0@14128r w=inf
assigning %vreg249 to %RDX: DH [14128r,14144r:0)  0@14128r DL [14128r,14144r:0)  0@14128r

selectOrSplit GR32:%vreg233 [14144r,14304r:2)[14304r,14336r:0)[14336r,14368r:1)[14368r,14400r:3)  0@14304r 1@14336r 2@14144r 3@14368r w=1.383133e-04
assigning %vreg233 to %EDX: DH [14144r,14304r:2)[14304r,14336r:0)[14336r,14368r:1)[14368r,14400r:3)  0@14304r 1@14336r 2@14144r 3@14368r DL [14144r,14304r:2)[14304r,14336r:0)[14336r,14368r:1)[14368r,14400r:3)  0@14304r 1@14336r 2@14144r 3@14368r

selectOrSplit GR64:%vreg243 [14160r,14176r:0)  0@14160r w=inf
assigning %vreg243 to %RCX: CH [14160r,14176r:0)  0@14160r CL [14160r,14176r:0)  0@14160r

selectOrSplit GR64:%vreg226 [14416r,14432r:0)  0@14416r w=inf
assigning %vreg226 to %RCX: CH [14416r,14432r:0)  0@14416r CL [14416r,14432r:0)  0@14416r

selectOrSplit GR64:%vreg223 [14448r,14512r:0)  0@14448r w=7.332992e-05
assigning %vreg223 to %RAX: AH [14448r,14512r:0)  0@14448r AL [14448r,14512r:0)  0@14448r

selectOrSplit GR32:%vreg221 [14464r,14496r:0)[14496r,14512r:1)  0@14464r 1@14496r w=inf
assigning %vreg221 to %ECX: CH [14464r,14496r:0)[14496r,14512r:1)  0@14464r 1@14496r CL [14464r,14496r:0)[14496r,14512r:1)  0@14464r 1@14496r

selectOrSplit GR64:%vreg217 [14528r,14544r:0)  0@14528r w=inf
assigning %vreg217 to %RAX: AH [14528r,14544r:0)  0@14528r AL [14528r,14544r:0)  0@14528r

selectOrSplit GR32:%vreg216 [14544r,14624r:0)  0@14544r w=4.725705e-05
assigning %vreg216 to %EAX: AH [14544r,14624r:0)  0@14544r AL [14544r,14624r:0)  0@14544r

selectOrSplit GR64:%vreg214 [14560r,14576r:0)  0@14560r w=inf
assigning %vreg214 to %RCX: CH [14560r,14576r:0)  0@14560r CL [14560r,14576r:0)  0@14560r

selectOrSplit GR32:%vreg211 [14576r,14608r:0)[14608r,14624r:1)  0@14576r 1@14608r w=inf
assigning %vreg211 to %ECX: CH [14576r,14608r:0)[14608r,14624r:1)  0@14576r 1@14608r CL [14576r,14608r:0)[14608r,14624r:1)  0@14576r 1@14608r

selectOrSplit GR32:%vreg291 [14704r,14736r:0)  0@14704r w=2.620254e-05
assigning %vreg291 to %EAX: AH [14704r,14736r:0)  0@14704r AL [14704r,14736r:0)  0@14704r

selectOrSplit GR64:%vreg289 [14720r,14736r:0)  0@14720r w=inf
assigning %vreg289 to %RCX: CH [14720r,14736r:0)  0@14720r CL [14720r,14736r:0)  0@14720r

selectOrSplit GR32:%vreg524 [14784r,14816r:0)  0@14784r w=1.304989e-05
assigning %vreg524 to %EAX: AH [14784r,14816r:0)  0@14784r AL [14784r,14816r:0)  0@14784r

selectOrSplit GR64:%vreg522 [14800r,14816r:0)  0@14800r w=inf
assigning %vreg522 to %RCX: CH [14800r,14816r:0)  0@14800r CL [14800r,14816r:0)  0@14800r

selectOrSplit GR64:%vreg369 [14864r,14880r:0)  0@14864r w=inf
assigning %vreg369 to %RAX: AH [14864r,14880r:0)  0@14864r AL [14864r,14880r:0)  0@14864r

selectOrSplit GR64:%vreg367 [14896r,14912r:0)  0@14896r w=inf
assigning %vreg367 to %RAX: AH [14896r,14912r:0)  0@14896r AL [14896r,14912r:0)  0@14896r

selectOrSplit GR64:%vreg354 [15152r,15168r:0)  0@15152r w=inf
assigning %vreg354 to %RAX: AH [15152r,15168r:0)  0@15152r AL [15152r,15168r:0)  0@15152r

selectOrSplit GR64_NOSP:%vreg352 [15168r,15232r:0)  0@15168r w=1.214990e-05
assigning %vreg352 to %RAX: AH [15168r,15232r:0)  0@15168r AL [15168r,15232r:0)  0@15168r

selectOrSplit GR64:%vreg349 [15200r,15216r:0)  0@15200r w=inf
assigning %vreg349 to %RCX: CH [15200r,15216r:0)  0@15200r CL [15200r,15216r:0)  0@15200r

selectOrSplit GR64:%vreg348 [15216r,15232r:0)  0@15216r w=inf
assigning %vreg348 to %RCX: CH [15216r,15232r:0)  0@15216r CL [15216r,15232r:0)  0@15216r

selectOrSplit GR32:%vreg313 [15232r,15632r:0)[15632r,15664r:1)  0@15232r 1@15632r w=1.355181e-05
assigning %vreg313 to %EAX: AH [15232r,15632r:0)[15632r,15664r:1)  0@15232r 1@15632r AL [15232r,15632r:0)[15632r,15664r:1)  0@15232r 1@15632r

selectOrSplit GR64:%vreg342 [15248r,15264r:0)  0@15248r w=inf
assigning %vreg342 to %RCX: CH [15248r,15264r:0)  0@15248r CL [15248r,15264r:0)  0@15248r

selectOrSplit GR32:%vreg339 [15264r,15296r:0)[15296r,15312r:1)  0@15264r 1@15296r w=inf
assigning %vreg339 to %ECX: CH [15264r,15296r:0)[15296r,15312r:1)  0@15264r 1@15296r CL [15264r,15296r:0)[15296r,15312r:1)  0@15264r 1@15296r

selectOrSplit GR64_NOSP:%vreg337 [15312r,15376r:0)  0@15312r w=1.214990e-05
assigning %vreg337 to %RCX: CH [15312r,15376r:0)  0@15312r CL [15312r,15376r:0)  0@15312r

selectOrSplit GR64:%vreg334 [15344r,15360r:0)  0@15344r w=inf
assigning %vreg334 to %RDX: DH [15344r,15360r:0)  0@15344r DL [15344r,15360r:0)  0@15344r

selectOrSplit GR64:%vreg333 [15360r,15376r:0)  0@15360r w=inf
assigning %vreg333 to %RDX: DH [15360r,15376r:0)  0@15360r DL [15360r,15376r:0)  0@15360r

selectOrSplit GR32:%vreg317 [15376r,15536r:2)[15536r,15568r:0)[15568r,15600r:1)[15600r,15632r:3)  0@15536r 1@15568r 2@15376r 3@15600r w=3.437533e-05
assigning %vreg317 to %EDX: DH [15376r,15536r:2)[15536r,15568r:0)[15568r,15600r:1)[15600r,15632r:3)  0@15536r 1@15568r 2@15376r 3@15600r DL [15376r,15536r:2)[15536r,15568r:0)[15568r,15600r:1)[15600r,15632r:3)  0@15536r 1@15568r 2@15376r 3@15600r

selectOrSplit GR64:%vreg327 [15392r,15408r:0)  0@15392r w=inf
assigning %vreg327 to %RCX: CH [15392r,15408r:0)  0@15392r CL [15392r,15408r:0)  0@15392r

selectOrSplit GR64:%vreg310 [15648r,15664r:0)  0@15648r w=inf
assigning %vreg310 to %RCX: CH [15648r,15664r:0)  0@15648r CL [15648r,15664r:0)  0@15648r

selectOrSplit GR64:%vreg307 [15680r,15744r:0)  0@15680r w=1.822485e-05
assigning %vreg307 to %RAX: AH [15680r,15744r:0)  0@15680r AL [15680r,15744r:0)  0@15680r

selectOrSplit GR32:%vreg305 [15696r,15728r:0)[15728r,15744r:1)  0@15696r 1@15728r w=inf
assigning %vreg305 to %ECX: CH [15696r,15728r:0)[15728r,15744r:1)  0@15696r 1@15728r CL [15696r,15728r:0)[15728r,15744r:1)  0@15696r 1@15728r

selectOrSplit GR64:%vreg301 [15760r,15776r:0)  0@15760r w=inf
assigning %vreg301 to %RAX: AH [15760r,15776r:0)  0@15760r AL [15760r,15776r:0)  0@15760r

selectOrSplit GR32:%vreg300 [15776r,15856r:0)  0@15776r w=1.174490e-05
assigning %vreg300 to %EAX: AH [15776r,15856r:0)  0@15776r AL [15776r,15856r:0)  0@15776r

selectOrSplit GR64:%vreg298 [15792r,15808r:0)  0@15792r w=inf
assigning %vreg298 to %RCX: CH [15792r,15808r:0)  0@15792r CL [15792r,15808r:0)  0@15792r

selectOrSplit GR32:%vreg295 [15808r,15840r:0)[15840r,15856r:1)  0@15808r 1@15840r w=inf
assigning %vreg295 to %ECX: CH [15808r,15840r:0)[15840r,15856r:1)  0@15808r 1@15840r CL [15808r,15840r:0)[15840r,15856r:1)  0@15808r 1@15840r

selectOrSplit GR32:%vreg375 [15936r,15968r:0)  0@15936r w=6.473569e-06
assigning %vreg375 to %EAX: AH [15936r,15968r:0)  0@15936r AL [15936r,15968r:0)  0@15936r

selectOrSplit GR64:%vreg373 [15952r,15968r:0)  0@15952r w=inf
assigning %vreg373 to %RCX: CH [15952r,15968r:0)  0@15952r CL [15952r,15968r:0)  0@15952r

selectOrSplit GR32:%vreg519 [16016r,16048r:0)  0@16016r w=3.185407e-06
assigning %vreg519 to %EAX: AH [16016r,16048r:0)  0@16016r AL [16016r,16048r:0)  0@16016r

selectOrSplit GR64:%vreg517 [16032r,16048r:0)  0@16032r w=inf
assigning %vreg517 to %RCX: CH [16032r,16048r:0)  0@16032r CL [16032r,16048r:0)  0@16032r

selectOrSplit GR64:%vreg514 [16096r,16112r:0)  0@16096r w=inf
assigning %vreg514 to %RAX: AH [16096r,16112r:0)  0@16096r AL [16096r,16112r:0)  0@16096r

selectOrSplit GR64:%vreg501 [16352r,16368r:0)  0@16352r w=inf
assigning %vreg501 to %RAX: AH [16352r,16368r:0)  0@16352r AL [16352r,16368r:0)  0@16352r

selectOrSplit GR64_NOSP:%vreg499 [16368r,16432r:0)  0@16368r w=2.965724e-06
assigning %vreg499 to %RAX: AH [16368r,16432r:0)  0@16368r AL [16368r,16432r:0)  0@16368r

selectOrSplit GR64:%vreg496 [16400r,16416r:0)  0@16400r w=inf
assigning %vreg496 to %RCX: CH [16400r,16416r:0)  0@16400r CL [16400r,16416r:0)  0@16400r

selectOrSplit GR64:%vreg495 [16416r,16432r:0)  0@16416r w=inf
assigning %vreg495 to %RCX: CH [16416r,16432r:0)  0@16416r CL [16416r,16432r:0)  0@16416r

selectOrSplit GR32:%vreg460 [16432r,16832r:0)[16832r,16864r:1)  0@16432r 1@16832r w=3.307923e-06
assigning %vreg460 to %EAX: AH [16432r,16832r:0)[16832r,16864r:1)  0@16432r 1@16832r AL [16432r,16832r:0)[16832r,16864r:1)  0@16432r 1@16832r

selectOrSplit GR64:%vreg489 [16448r,16464r:0)  0@16448r w=inf
assigning %vreg489 to %RCX: CH [16448r,16464r:0)  0@16448r CL [16448r,16464r:0)  0@16448r

selectOrSplit GR32:%vreg486 [16464r,16496r:0)[16496r,16512r:1)  0@16464r 1@16496r w=inf
assigning %vreg486 to %ECX: CH [16464r,16496r:0)[16496r,16512r:1)  0@16464r 1@16496r CL [16464r,16496r:0)[16496r,16512r:1)  0@16464r 1@16496r

selectOrSplit GR64_NOSP:%vreg484 [16512r,16576r:0)  0@16512r w=2.965724e-06
assigning %vreg484 to %RCX: CH [16512r,16576r:0)  0@16512r CL [16512r,16576r:0)  0@16512r

selectOrSplit GR64:%vreg481 [16544r,16560r:0)  0@16544r w=inf
assigning %vreg481 to %RDX: DH [16544r,16560r:0)  0@16544r DL [16544r,16560r:0)  0@16544r

selectOrSplit GR64:%vreg480 [16560r,16576r:0)  0@16560r w=inf
assigning %vreg480 to %RDX: DH [16560r,16576r:0)  0@16560r DL [16560r,16576r:0)  0@16560r

selectOrSplit GR32:%vreg464 [16576r,16736r:2)[16736r,16768r:0)[16768r,16800r:1)[16800r,16832r:3)  0@16736r 1@16768r 2@16576r 3@16800r w=8.390828e-06
assigning %vreg464 to %EDX: DH [16576r,16736r:2)[16736r,16768r:0)[16768r,16800r:1)[16800r,16832r:3)  0@16736r 1@16768r 2@16576r 3@16800r DL [16576r,16736r:2)[16736r,16768r:0)[16768r,16800r:1)[16800r,16832r:3)  0@16736r 1@16768r 2@16576r 3@16800r

selectOrSplit GR64:%vreg474 [16592r,16608r:0)  0@16592r w=inf
assigning %vreg474 to %RCX: CH [16592r,16608r:0)  0@16592r CL [16592r,16608r:0)  0@16592r

selectOrSplit GR64:%vreg457 [16848r,16864r:0)  0@16848r w=inf
assigning %vreg457 to %RCX: CH [16848r,16864r:0)  0@16848r CL [16848r,16864r:0)  0@16848r

selectOrSplit GR64:%vreg454 [16880r,16944r:0)  0@16880r w=4.448586e-06
assigning %vreg454 to %RAX: AH [16880r,16944r:0)  0@16880r AL [16880r,16944r:0)  0@16880r

selectOrSplit GR32:%vreg452 [16896r,16928r:0)[16928r,16944r:1)  0@16896r 1@16928r w=inf
assigning %vreg452 to %ECX: CH [16896r,16928r:0)[16928r,16944r:1)  0@16896r 1@16928r CL [16896r,16928r:0)[16928r,16944r:1)  0@16896r 1@16928r

selectOrSplit GR32:%vreg446 [16960r,16992r:0)[16992r,17024r:1)  0@16960r 1@16992r w=5.931448e-06
assigning %vreg446 to %EAX: AH [16960r,16992r:0)[16992r,17024r:1)  0@16960r 1@16992r AL [16960r,16992r:0)[16992r,17024r:1)  0@16960r 1@16992r

selectOrSplit GR64:%vreg444 [17008r,17024r:0)  0@17008r w=inf
assigning %vreg444 to %RCX: CH [17008r,17024r:0)  0@17008r CL [17008r,17024r:0)  0@17008r

selectOrSplit GR64:%vreg441 [17040r,17056r:0)  0@17040r w=inf
assigning %vreg441 to %RAX: AH [17040r,17056r:0)  0@17040r AL [17040r,17056r:0)  0@17040r

selectOrSplit GR64:%vreg431 [17264r,17280r:0)  0@17264r w=inf
assigning %vreg431 to %RCX: CH [17264r,17280r:0)  0@17264r CL [17264r,17280r:0)  0@17264r

selectOrSplit GR64:%vreg428 [17296r,17312r:0)  0@17296r w=inf
assigning %vreg428 to %RAX: AH [17296r,17312r:0)  0@17296r AL [17296r,17312r:0)  0@17296r

selectOrSplit GR64_NOSP:%vreg426 [17312r,17376r:0)  0@17312r w=2.965724e-06
assigning %vreg426 to %RAX: AH [17312r,17376r:0)  0@17312r AL [17312r,17376r:0)  0@17312r

selectOrSplit GR64:%vreg423 [17344r,17360r:0)  0@17344r w=inf
assigning %vreg423 to %RCX: CH [17344r,17360r:0)  0@17344r CL [17344r,17360r:0)  0@17344r

selectOrSplit GR64:%vreg422 [17360r,17376r:0)  0@17360r w=inf
assigning %vreg422 to %RCX: CH [17360r,17376r:0)  0@17360r CL [17360r,17376r:0)  0@17360r

selectOrSplit GR32:%vreg387 [17376r,17776r:0)[17776r,17808r:1)  0@17376r 1@17776r w=3.307923e-06
assigning %vreg387 to %EAX: AH [17376r,17776r:0)[17776r,17808r:1)  0@17376r 1@17776r AL [17376r,17776r:0)[17776r,17808r:1)  0@17376r 1@17776r

selectOrSplit GR64:%vreg416 [17392r,17408r:0)  0@17392r w=inf
assigning %vreg416 to %RCX: CH [17392r,17408r:0)  0@17392r CL [17392r,17408r:0)  0@17392r

selectOrSplit GR32:%vreg413 [17408r,17440r:0)[17440r,17456r:1)  0@17408r 1@17440r w=inf
assigning %vreg413 to %ECX: CH [17408r,17440r:0)[17440r,17456r:1)  0@17408r 1@17440r CL [17408r,17440r:0)[17440r,17456r:1)  0@17408r 1@17440r

selectOrSplit GR64_NOSP:%vreg411 [17456r,17520r:0)  0@17456r w=2.965724e-06
assigning %vreg411 to %RCX: CH [17456r,17520r:0)  0@17456r CL [17456r,17520r:0)  0@17456r

selectOrSplit GR64:%vreg408 [17488r,17504r:0)  0@17488r w=inf
assigning %vreg408 to %RDX: DH [17488r,17504r:0)  0@17488r DL [17488r,17504r:0)  0@17488r

selectOrSplit GR64:%vreg407 [17504r,17520r:0)  0@17504r w=inf
assigning %vreg407 to %RDX: DH [17504r,17520r:0)  0@17504r DL [17504r,17520r:0)  0@17504r

selectOrSplit GR32:%vreg391 [17520r,17680r:2)[17680r,17712r:0)[17712r,17744r:1)[17744r,17776r:3)  0@17680r 1@17712r 2@17520r 3@17744r w=8.390828e-06
assigning %vreg391 to %EDX: DH [17520r,17680r:2)[17680r,17712r:0)[17712r,17744r:1)[17744r,17776r:3)  0@17680r 1@17712r 2@17520r 3@17744r DL [17520r,17680r:2)[17680r,17712r:0)[17712r,17744r:1)[17744r,17776r:3)  0@17680r 1@17712r 2@17520r 3@17744r

selectOrSplit GR64:%vreg401 [17536r,17552r:0)  0@17536r w=inf
assigning %vreg401 to %RCX: CH [17536r,17552r:0)  0@17536r CL [17536r,17552r:0)  0@17536r

selectOrSplit GR64:%vreg384 [17792r,17808r:0)  0@17792r w=inf
assigning %vreg384 to %RCX: CH [17792r,17808r:0)  0@17792r CL [17792r,17808r:0)  0@17792r

selectOrSplit GR64:%vreg381 [17824r,17888r:0)  0@17824r w=4.448586e-06
assigning %vreg381 to %RAX: AH [17824r,17888r:0)  0@17824r AL [17824r,17888r:0)  0@17824r

selectOrSplit GR32:%vreg379 [17840r,17872r:0)[17872r,17888r:1)  0@17840r 1@17872r w=inf
assigning %vreg379 to %ECX: CH [17840r,17872r:0)[17872r,17888r:1)  0@17840r 1@17872r CL [17840r,17872r:0)[17872r,17888r:1)  0@17840r 1@17872r

********** STACK TRANSFORMATION METADATA **********
********** Function: unRLE_obuf_to_output_SMALL
********** REGISTER MAP **********
[%vreg1 -> %RBX] GR64
[%vreg4 -> %RAX] GR64
[%vreg6 -> %RDI] GR64
[%vreg7 -> %RSI] GR64
[%vreg11 -> %RAX] GR64
[%vreg12 -> %RAX] GR64
[%vreg15 -> %RAX] GR64
[%vreg19 -> %RAX] GR64
[%vreg20 -> %RAX] GR64
[%vreg24 -> %ECX] GR32
[%vreg27 -> %RAX] GR64
[%vreg28 -> %RAX] GR64
[%vreg32 -> %ECX] GR32
[%vreg35 -> %RAX] GR64
[%vreg36 -> %RAX] GR64
[%vreg40 -> %RCX] GR64
[%vreg43 -> %RAX] GR64
[%vreg44 -> %RAX] GR64
[%vreg48 -> %ECX] GR32
[%vreg50 -> %RAX] GR64
[%vreg53 -> %RCX] GR64
[%vreg56 -> %EAX] GR32
[%vreg60 -> %RCX] GR64_NOSP
[%vreg63 -> %ECX] GR32
[%vreg65 -> %EDX] GR32
[%vreg67 -> %RDX] GR64
[%vreg72 -> %RCX] GR64
[%vreg77 -> %RAX] GR64
[%vreg81 -> %RCX] GR64
[%vreg83 -> %RCX] GR64
[%vreg84 -> %RCX] GR64
[%vreg86 -> %AL] GR8
[%vreg87 -> %RAX] GR64
[%vreg91 -> %ECX] GR32
[%vreg94 -> %RAX] GR64
[%vreg95 -> %RAX] GR64
[%vreg99 -> %ECX] GR32
[%vreg102 -> %RCX] GR64
[%vreg104 -> %EAX] GR32
[%vreg105 -> %RAX] GR64
[%vreg109 -> %ECX] GR32
[%vreg112 -> %RCX] GR64
[%vreg114 -> %EAX] GR32
[%vreg115 -> %RAX] GR64
[%vreg119 -> %ECX] GR32
[%vreg122 -> %RCX] GR64
[%vreg124 -> %EAX] GR32
[%vreg125 -> %RAX] GR64
[%vreg129 -> %ECX] GR32
[%vreg131 -> %RAX] GR64
[%vreg134 -> %RCX] GR64
[%vreg137 -> %EAX] GR32
[%vreg141 -> %EDX] GR32
[%vreg146 -> %ECX] GR32
[%vreg151 -> %RCX] GR64
[%vreg157 -> %RDX] GR64
[%vreg158 -> %RDX] GR64
[%vreg161 -> %RCX] GR64_NOSP
[%vreg163 -> %ECX] GR32
[%vreg166 -> %RCX] GR64
[%vreg172 -> %RCX] GR64
[%vreg173 -> %RCX] GR64
[%vreg176 -> %RAX] GR64_NOSP
[%vreg178 -> %RAX] GR64
[%vreg184 -> %EAX] GR32
[%vreg187 -> %RSI] GR64
[%vreg190 -> %EDI] GR32
[%vreg191 -> %RAX] GR64
[%vreg194 -> %RCX] GR64
[%vreg198 -> %EAX] GR32
[%vreg199 -> %RAX] GR64
[%vreg201 -> %RAX] GR64
[%vreg205 -> %RCX] GR64
[%vreg207 -> %EAX] GR32
[%vreg211 -> %ECX] GR32
[%vreg214 -> %RCX] GR64
[%vreg216 -> %EAX] GR32
[%vreg217 -> %RAX] GR64
[%vreg221 -> %ECX] GR32
[%vreg223 -> %RAX] GR64
[%vreg226 -> %RCX] GR64
[%vreg229 -> %EAX] GR32
[%vreg233 -> %EDX] GR32
[%vreg238 -> %ECX] GR32
[%vreg243 -> %RCX] GR64
[%vreg249 -> %RDX] GR64
[%vreg250 -> %RDX] GR64
[%vreg253 -> %RCX] GR64_NOSP
[%vreg255 -> %ECX] GR32
[%vreg258 -> %RCX] GR64
[%vreg264 -> %RCX] GR64
[%vreg265 -> %RCX] GR64
[%vreg268 -> %RAX] GR64_NOSP
[%vreg270 -> %RAX] GR64
[%vreg276 -> %EAX] GR32
[%vreg279 -> %RSI] GR64
[%vreg282 -> %EDI] GR32
[%vreg283 -> %RAX] GR64
[%vreg285 -> %RAX] GR64
[%vreg289 -> %RCX] GR64
[%vreg291 -> %EAX] GR32
[%vreg295 -> %ECX] GR32
[%vreg298 -> %RCX] GR64
[%vreg300 -> %EAX] GR32
[%vreg301 -> %RAX] GR64
[%vreg305 -> %ECX] GR32
[%vreg307 -> %RAX] GR64
[%vreg310 -> %RCX] GR64
[%vreg313 -> %EAX] GR32
[%vreg317 -> %EDX] GR32
[%vreg322 -> %ECX] GR32
[%vreg327 -> %RCX] GR64
[%vreg333 -> %RDX] GR64
[%vreg334 -> %RDX] GR64
[%vreg337 -> %RCX] GR64_NOSP
[%vreg339 -> %ECX] GR32
[%vreg342 -> %RCX] GR64
[%vreg348 -> %RCX] GR64
[%vreg349 -> %RCX] GR64
[%vreg352 -> %RAX] GR64_NOSP
[%vreg354 -> %RAX] GR64
[%vreg360 -> %EAX] GR32
[%vreg363 -> %RSI] GR64
[%vreg366 -> %EDI] GR32
[%vreg367 -> %RAX] GR64
[%vreg369 -> %RAX] GR64
[%vreg373 -> %RCX] GR64
[%vreg375 -> %EAX] GR32
[%vreg379 -> %ECX] GR32
[%vreg381 -> %RAX] GR64
[%vreg384 -> %RCX] GR64
[%vreg387 -> %EAX] GR32
[%vreg391 -> %EDX] GR32
[%vreg396 -> %ECX] GR32
[%vreg401 -> %RCX] GR64
[%vreg407 -> %RDX] GR64
[%vreg408 -> %RDX] GR64
[%vreg411 -> %RCX] GR64_NOSP
[%vreg413 -> %ECX] GR32
[%vreg416 -> %RCX] GR64
[%vreg422 -> %RCX] GR64
[%vreg423 -> %RCX] GR64
[%vreg426 -> %RAX] GR64_NOSP
[%vreg428 -> %RAX] GR64
[%vreg431 -> %RCX] GR64
[%vreg434 -> %EAX] GR32
[%vreg437 -> %RSI] GR64
[%vreg440 -> %EDI] GR32
[%vreg441 -> %RAX] GR64
[%vreg444 -> %RCX] GR64
[%vreg446 -> %EAX] GR32
[%vreg452 -> %ECX] GR32
[%vreg454 -> %RAX] GR64
[%vreg457 -> %RCX] GR64
[%vreg460 -> %EAX] GR32
[%vreg464 -> %EDX] GR32
[%vreg469 -> %ECX] GR32
[%vreg474 -> %RCX] GR64
[%vreg480 -> %RDX] GR64
[%vreg481 -> %RDX] GR64
[%vreg484 -> %RCX] GR64_NOSP
[%vreg486 -> %ECX] GR32
[%vreg489 -> %RCX] GR64
[%vreg495 -> %RCX] GR64
[%vreg496 -> %RCX] GR64
[%vreg499 -> %RAX] GR64_NOSP
[%vreg501 -> %RAX] GR64
[%vreg507 -> %EAX] GR32
[%vreg510 -> %RSI] GR64
[%vreg513 -> %EDI] GR32
[%vreg514 -> %RAX] GR64
[%vreg517 -> %RCX] GR64
[%vreg519 -> %EAX] GR32
[%vreg522 -> %RCX] GR64
[%vreg524 -> %EAX] GR32
[%vreg527 -> %RCX] GR64
[%vreg529 -> %EAX] GR32
[%vreg533 -> %RAX] GR64
[%vreg534 -> %RAX] GR64
[%vreg537 -> %RAX] GR64
[%vreg541 -> %RAX] GR64
[%vreg542 -> %RAX] GR64
[%vreg546 -> %ECX] GR32
[%vreg549 -> %RAX] GR64
[%vreg550 -> %RAX] GR64
[%vreg554 -> %ECX] GR32
[%vreg557 -> %RAX] GR64
[%vreg558 -> %RAX] GR64
[%vreg562 -> %RCX] GR64
[%vreg565 -> %RAX] GR64
[%vreg566 -> %RAX] GR64
[%vreg570 -> %ECX] GR32
[%vreg572 -> %RAX] GR64
[%vreg575 -> %RCX] GR64
[%vreg578 -> %EAX] GR32
[%vreg582 -> %RCX] GR64_NOSP
[%vreg585 -> %ECX] GR32
[%vreg587 -> %EDX] GR32
[%vreg589 -> %RDX] GR64
[%vreg594 -> %RCX] GR64
[%vreg599 -> %RAX] GR64
[%vreg603 -> %RCX] GR64
[%vreg605 -> %RCX] GR64
[%vreg606 -> %RCX] GR64
[%vreg608 -> %AL] GR8
[%vreg609 -> %RAX] GR64
[%vreg613 -> %ECX] GR32
[%vreg616 -> %RAX] GR64
[%vreg617 -> %RAX] GR64
[%vreg621 -> %ECX] GR32
[%vreg624 -> %RCX] GR64
[%vreg626 -> %EAX] GR32
[%vreg627 -> %RAX] GR64
[%vreg631 -> %ECX] GR32
[%vreg634 -> %RCX] GR64
[%vreg636 -> %EAX] GR32
[%vreg637 -> %RAX] GR64
[%vreg640 -> %RAX] GR64
[%vreg643 -> %RCX] GR64
[%vreg646 -> %EAX] GR32
[%vreg650 -> %EDX] GR32
[%vreg655 -> %ECX] GR32
[%vreg660 -> %RCX] GR64
[%vreg666 -> %RDX] GR64
[%vreg667 -> %RDX] GR64
[%vreg670 -> %RCX] GR64_NOSP
[%vreg672 -> %ECX] GR32
[%vreg675 -> %RCX] GR64
[%vreg681 -> %RCX] GR64
[%vreg682 -> %RCX] GR64
[%vreg685 -> %RAX] GR64_NOSP
[%vreg687 -> %RAX] GR64
[%vreg693 -> %EAX] GR32
[%vreg696 -> %RSI] GR64
[%vreg699 -> %EDI] GR32
[%vreg700 -> %RAX] GR64
[%vreg703 -> %RCX] GR64
[%vreg707 -> %EAX] GR32
[%vreg708 -> %RAX] GR64
[%vreg710 -> %RAX] GR64
[%vreg713 -> %RAX] GR64
[%vreg717 -> %ECX] GR32
[%vreg719 -> %RAX] GR64
[%vreg722 -> %RCX] GR64
[%vreg724 -> %EAX] GR32
[%vreg726 -> %RAX] GR64_NOSP
[%vreg728 -> %RAX] GR64
[%vreg730 -> %RAX] GR64
[%vreg734 -> %ECX] GR32
[%vreg737 -> %RCX] GR64
[%vreg739 -> %EAX] GR32
[%vreg740 -> %RAX] GR64
[%vreg744 -> %ECX] GR32
[%vreg746 -> %RAX] GR64
[%vreg752 -> %ECX] GR32
[%vreg757 -> %ECX] GR32
[%vreg758 -> %EAX] GR32
[%vreg760 -> %RDX] GR64
[%vreg764 -> %ESI] GR32
[%vreg766 -> %RDX] GR64
[%vreg770 -> %RCX] GR64
[%vreg772 -> %EAX] GR32
[%vreg775 -> %RAX] GR64
[%vreg778 -> %RCX] GR64
[%vreg781 -> %EAX] GR32
[%vreg785 -> %EDX] GR32
[%vreg790 -> %ECX] GR32
[%vreg795 -> %RCX] GR64
[%vreg801 -> %RDX] GR64
[%vreg802 -> %RDX] GR64
[%vreg805 -> %RCX] GR64_NOSP
[%vreg807 -> %ECX] GR32
[%vreg810 -> %RCX] GR64
[%vreg816 -> %RCX] GR64
[%vreg817 -> %RCX] GR64
[%vreg820 -> %RAX] GR64_NOSP
[%vreg822 -> %RAX] GR64
[%vreg828 -> %EAX] GR32
[%vreg831 -> %RSI] GR64
[%vreg834 -> %EDI] GR32
[%vreg835 -> %RAX] GR64
[%vreg837 -> %RAX] GR64
[%vreg840 -> %RAX] GR64
[%vreg844 -> %ECX] GR32
[%vreg846 -> %RAX] GR64
[%vreg849 -> %RCX] GR64
[%vreg851 -> %EAX] GR32
[%vreg853 -> %RAX] GR64_NOSP
[%vreg855 -> %RAX] GR64
[%vreg857 -> %RAX] GR64
[%vreg861 -> %ECX] GR32
[%vreg864 -> %RCX] GR64
[%vreg866 -> %EAX] GR32
[%vreg867 -> %RAX] GR64
[%vreg871 -> %ECX] GR32
[%vreg873 -> %RAX] GR64
[%vreg879 -> %ECX] GR32
[%vreg884 -> %ECX] GR32
[%vreg885 -> %EAX] GR32
[%vreg887 -> %RDX] GR64
[%vreg891 -> %ESI] GR32
[%vreg893 -> %RDX] GR64
[%vreg897 -> %RCX] GR64
[%vreg899 -> %EAX] GR32
[%vreg902 -> %RAX] GR64
[%vreg905 -> %RCX] GR64
[%vreg908 -> %EAX] GR32
[%vreg912 -> %EDX] GR32
[%vreg917 -> %ECX] GR32
[%vreg922 -> %RCX] GR64
[%vreg928 -> %RDX] GR64
[%vreg929 -> %RDX] GR64
[%vreg932 -> %RCX] GR64_NOSP
[%vreg934 -> %ECX] GR32
[%vreg937 -> %RCX] GR64
[%vreg943 -> %RCX] GR64
[%vreg944 -> %RCX] GR64
[%vreg947 -> %RAX] GR64_NOSP
[%vreg949 -> %RAX] GR64
[%vreg955 -> %EAX] GR32
[%vreg958 -> %RSI] GR64
[%vreg961 -> %EDI] GR32
[%vreg962 -> %RAX] GR64
[%vreg964 -> %RAX] GR64
[%vreg967 -> %RAX] GR64
[%vreg971 -> %ECX] GR32
[%vreg973 -> %RAX] GR64
[%vreg976 -> %RCX] GR64
[%vreg978 -> %EAX] GR32
[%vreg980 -> %RAX] GR64_NOSP
[%vreg982 -> %RAX] GR64
[%vreg984 -> %RAX] GR64
[%vreg988 -> %ECX] GR32
[%vreg991 -> %RCX] GR64
[%vreg993 -> %EAX] GR32
[%vreg994 -> %RAX] GR64
[%vreg998 -> %ECX] GR32
[%vreg1000 -> %RAX] GR64
[%vreg1006 -> %ECX] GR32
[%vreg1011 -> %ECX] GR32
[%vreg1012 -> %EAX] GR32
[%vreg1014 -> %RDX] GR64
[%vreg1018 -> %ESI] GR32
[%vreg1020 -> %RDX] GR64
[%vreg1024 -> %RCX] GR64
[%vreg1026 -> %EAX] GR32
[%vreg1029 -> %RAX] GR64
[%vreg1032 -> %RCX] GR64
[%vreg1035 -> %EAX] GR32
[%vreg1039 -> %EDX] GR32
[%vreg1044 -> %ECX] GR32
[%vreg1049 -> %RCX] GR64
[%vreg1055 -> %RDX] GR64
[%vreg1056 -> %RDX] GR64
[%vreg1059 -> %RCX] GR64_NOSP
[%vreg1061 -> %ECX] GR32
[%vreg1064 -> %RCX] GR64
[%vreg1070 -> %RCX] GR64
[%vreg1071 -> %RCX] GR64
[%vreg1074 -> %RAX] GR64_NOSP
[%vreg1076 -> %RAX] GR64
[%vreg1082 -> %EAX] GR32
[%vreg1085 -> %RSI] GR64
[%vreg1088 -> %EDI] GR32
[%vreg1089 -> %RAX] GR64
[%vreg1092 -> %RAX] GR64
[%vreg1096 -> %ECX] GR32
[%vreg1098 -> %RAX] GR64
[%vreg1101 -> %RCX] GR64
[%vreg1103 -> %EAX] GR32
[%vreg1105 -> %RAX] GR64_NOSP
[%vreg1107 -> %RAX] GR64
[%vreg1109 -> %RAX] GR64
[%vreg1112 -> %RAX] GR64
[%vreg1115 -> %RCX] GR64
[%vreg1118 -> %EAX] GR32
[%vreg1122 -> %EDX] GR32
[%vreg1127 -> %ECX] GR32
[%vreg1132 -> %RCX] GR64
[%vreg1138 -> %RDX] GR64
[%vreg1139 -> %RDX] GR64
[%vreg1142 -> %RCX] GR64_NOSP
[%vreg1144 -> %ECX] GR32
[%vreg1147 -> %RCX] GR64
[%vreg1153 -> %RCX] GR64
[%vreg1154 -> %RCX] GR64
[%vreg1157 -> %RAX] GR64_NOSP
[%vreg1159 -> %RAX] GR64
[%vreg1162 -> %RCX] GR64
[%vreg1165 -> %EAX] GR32
[%vreg1168 -> %RSI] GR64
[%vreg1171 -> %EDI] GR32
[%vreg1172 -> %RAX] GR64
[%vreg1175 -> %RCX] GR64
[%vreg1177 -> %EAX] GR32
[%vreg1183 -> %ECX] GR32
[%vreg1185 -> %RAX] GR64
[%vreg1191 -> %ECX] GR32
[%vreg1196 -> %ECX] GR32
[%vreg1197 -> %EAX] GR32
[%vreg1199 -> %RDX] GR64
[%vreg1203 -> %ESI] GR32
[%vreg1205 -> %RDX] GR64
[%vreg1208 -> %RAX] GR64
[%vreg1212 -> %ECX] GR32
[%vreg1214 -> %RAX] GR64
[%vreg1217 -> %RCX] GR64
[%vreg1219 -> %EAX] GR32
[%vreg1221 -> %RAX] GR64_NOSP
[%vreg1223 -> %RAX] GR64
[%vreg1225 -> %RAX] GR64
[%vreg1229 -> %ECX] GR32
[%vreg1231 -> %RAX] GR64
[%vreg1236 -> %EAX] GR32
[%vreg1237 -> %RCX] GR64
[%vreg1240 -> %ECX] GR32
[%vreg1243 -> %RDX] GR64
[%vreg1247 -> %ESI] GR32
[%vreg1249 -> %RDX] GR64
[%vreg1252 -> %RCX] GR64
[%vreg1254 -> %EAX] GR32
[%vreg1257 -> %RCX] GR64
[%vreg1259 -> %EAX] GR32
[%vreg1262 -> %RCX] GR64
[%vreg1264 -> %EAX] GR32
[%vreg1266 -> %AL] GR8
[%vreg1268 -> %RDI] GR64
[%vreg1269 -> %RSI] GR64


Stackmap 0:
  STACKMAP 0, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, %vreg1, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1] GR64:%vreg1

i8* %k1: in stack slot 2 (size: 1)
i8* %retval: in stack slot 0 (size: 1)
%struct.DState* %s: in register %RBX (vreg 1)
%struct.DState** %s.addr: in stack slot 1 (size: 8)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]

i8* %k1: in stack slot 2 (size: 1)
i8* %retval: in stack slot 0 (size: 1)
%struct.DState** %s.addr: in stack slot 1 (size: 8)

Duplicate operand locations:


Stackmap 2:
  STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]

i8* %k1: in stack slot 2 (size: 1)
i8* %retval: in stack slot 0 (size: 1)
%struct.DState** %s.addr: in stack slot 1 (size: 8)

Duplicate operand locations:


Stackmap 3:
  STACKMAP 3, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]

i8* %k1: in stack slot 2 (size: 1)
i8* %retval: in stack slot 0 (size: 1)
%struct.DState** %s.addr: in stack slot 1 (size: 8)

Duplicate operand locations:


Stackmap 4:
  STACKMAP 4, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]

i8* %k1: in stack slot 2 (size: 1)
i8* %retval: in stack slot 0 (size: 1)
%struct.DState** %s.addr: in stack slot 1 (size: 8)

Duplicate operand locations:


Stackmap 5:
  STACKMAP 5, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]

i8* %k1: in stack slot 2 (size: 1)
i8* %retval: in stack slot 0 (size: 1)
%struct.DState** %s.addr: in stack slot 1 (size: 8)

Duplicate operand locations:


Stackmap 6:
  STACKMAP 6, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]

i8* %k1: in stack slot 2 (size: 1)
i8* %retval: in stack slot 0 (size: 1)
%struct.DState** %s.addr: in stack slot 1 (size: 8)

Duplicate operand locations:


Stackmap 7:
  STACKMAP 7, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]

i8* %k1: in stack slot 2 (size: 1)
i8* %retval: in stack slot 0 (size: 1)
%struct.DState** %s.addr: in stack slot 1 (size: 8)

Duplicate operand locations:


Stackmap 8:
  STACKMAP 8, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]

i8* %k1: in stack slot 2 (size: 1)
i8* %retval: in stack slot 0 (size: 1)
%struct.DState** %s.addr: in stack slot 1 (size: 8)

Duplicate operand locations:


Stackmap 9:
  STACKMAP 9, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]

i8* %k1: in stack slot 2 (size: 1)
i8* %retval: in stack slot 0 (size: 1)
%struct.DState** %s.addr: in stack slot 1 (size: 8)

Duplicate operand locations:


Stackmap 10:
  STACKMAP 10, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]

i8* %k1: in stack slot 2 (size: 1)
i8* %retval: in stack slot 0 (size: 1)
%struct.DState** %s.addr: in stack slot 1 (size: 8)

Duplicate operand locations:


Stackmap 11:
  STACKMAP 11, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=1)

i8* %retval: in stack slot 0 (size: 1)

Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, %vreg1, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1] GR64:%vreg1
  -> Call instruction SlotIndex 144B, searching vregs 0 -> 1270 and stack slots -1 -> 3

  STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
  -> Call instruction SlotIndex 2192B, searching vregs 0 -> 1270 and stack slots -1 -> 3

  STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
  -> Call instruction SlotIndex 4048B, searching vregs 0 -> 1270 and stack slots -1 -> 3

  STACKMAP 3, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
  -> Call instruction SlotIndex 5904B, searching vregs 0 -> 1270 and stack slots -1 -> 3

  STACKMAP 4, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
  -> Call instruction SlotIndex 7728B, searching vregs 0 -> 1270 and stack slots -1 -> 3

  STACKMAP 5, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
  -> Call instruction SlotIndex 9296B, searching vregs 0 -> 1270 and stack slots -1 -> 3

  STACKMAP 6, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
  -> Call instruction SlotIndex 12560B, searching vregs 0 -> 1270 and stack slots -1 -> 3

  STACKMAP 7, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
  -> Call instruction SlotIndex 13792B, searching vregs 0 -> 1270 and stack slots -1 -> 3

  STACKMAP 8, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
  -> Call instruction SlotIndex 15024B, searching vregs 0 -> 1270 and stack slots -1 -> 3

  STACKMAP 9, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
  -> Call instruction SlotIndex 16224B, searching vregs 0 -> 1270 and stack slots -1 -> 3

  STACKMAP 10, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
  -> Call instruction SlotIndex 17168B, searching vregs 0 -> 1270 and stack slots -1 -> 3

  STACKMAP 11, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=1)
  -> Call instruction SlotIndex 18032B, searching vregs 0 -> 1270 and stack slots -1 -> 3

********** REWRITE VIRTUAL REGISTERS **********
********** Function: unRLE_obuf_to_output_SMALL
********** REGISTER MAP **********
[%vreg1 -> %RBX] GR64
[%vreg4 -> %RAX] GR64
[%vreg6 -> %RDI] GR64
[%vreg7 -> %RSI] GR64
[%vreg11 -> %RAX] GR64
[%vreg12 -> %RAX] GR64
[%vreg15 -> %RAX] GR64
[%vreg19 -> %RAX] GR64
[%vreg20 -> %RAX] GR64
[%vreg24 -> %ECX] GR32
[%vreg27 -> %RAX] GR64
[%vreg28 -> %RAX] GR64
[%vreg32 -> %ECX] GR32
[%vreg35 -> %RAX] GR64
[%vreg36 -> %RAX] GR64
[%vreg40 -> %RCX] GR64
[%vreg43 -> %RAX] GR64
[%vreg44 -> %RAX] GR64
[%vreg48 -> %ECX] GR32
[%vreg50 -> %RAX] GR64
[%vreg53 -> %RCX] GR64
[%vreg56 -> %EAX] GR32
[%vreg60 -> %RCX] GR64_NOSP
[%vreg63 -> %ECX] GR32
[%vreg65 -> %EDX] GR32
[%vreg67 -> %RDX] GR64
[%vreg72 -> %RCX] GR64
[%vreg77 -> %RAX] GR64
[%vreg81 -> %RCX] GR64
[%vreg83 -> %RCX] GR64
[%vreg84 -> %RCX] GR64
[%vreg86 -> %AL] GR8
[%vreg87 -> %RAX] GR64
[%vreg91 -> %ECX] GR32
[%vreg94 -> %RAX] GR64
[%vreg95 -> %RAX] GR64
[%vreg99 -> %ECX] GR32
[%vreg102 -> %RCX] GR64
[%vreg104 -> %EAX] GR32
[%vreg105 -> %RAX] GR64
[%vreg109 -> %ECX] GR32
[%vreg112 -> %RCX] GR64
[%vreg114 -> %EAX] GR32
[%vreg115 -> %RAX] GR64
[%vreg119 -> %ECX] GR32
[%vreg122 -> %RCX] GR64
[%vreg124 -> %EAX] GR32
[%vreg125 -> %RAX] GR64
[%vreg129 -> %ECX] GR32
[%vreg131 -> %RAX] GR64
[%vreg134 -> %RCX] GR64
[%vreg137 -> %EAX] GR32
[%vreg141 -> %EDX] GR32
[%vreg146 -> %ECX] GR32
[%vreg151 -> %RCX] GR64
[%vreg157 -> %RDX] GR64
[%vreg158 -> %RDX] GR64
[%vreg161 -> %RCX] GR64_NOSP
[%vreg163 -> %ECX] GR32
[%vreg166 -> %RCX] GR64
[%vreg172 -> %RCX] GR64
[%vreg173 -> %RCX] GR64
[%vreg176 -> %RAX] GR64_NOSP
[%vreg178 -> %RAX] GR64
[%vreg184 -> %EAX] GR32
[%vreg187 -> %RSI] GR64
[%vreg190 -> %EDI] GR32
[%vreg191 -> %RAX] GR64
[%vreg194 -> %RCX] GR64
[%vreg198 -> %EAX] GR32
[%vreg199 -> %RAX] GR64
[%vreg201 -> %RAX] GR64
[%vreg205 -> %RCX] GR64
[%vreg207 -> %EAX] GR32
[%vreg211 -> %ECX] GR32
[%vreg214 -> %RCX] GR64
[%vreg216 -> %EAX] GR32
[%vreg217 -> %RAX] GR64
[%vreg221 -> %ECX] GR32
[%vreg223 -> %RAX] GR64
[%vreg226 -> %RCX] GR64
[%vreg229 -> %EAX] GR32
[%vreg233 -> %EDX] GR32
[%vreg238 -> %ECX] GR32
[%vreg243 -> %RCX] GR64
[%vreg249 -> %RDX] GR64
[%vreg250 -> %RDX] GR64
[%vreg253 -> %RCX] GR64_NOSP
[%vreg255 -> %ECX] GR32
[%vreg258 -> %RCX] GR64
[%vreg264 -> %RCX] GR64
[%vreg265 -> %RCX] GR64
[%vreg268 -> %RAX] GR64_NOSP
[%vreg270 -> %RAX] GR64
[%vreg276 -> %EAX] GR32
[%vreg279 -> %RSI] GR64
[%vreg282 -> %EDI] GR32
[%vreg283 -> %RAX] GR64
[%vreg285 -> %RAX] GR64
[%vreg289 -> %RCX] GR64
[%vreg291 -> %EAX] GR32
[%vreg295 -> %ECX] GR32
[%vreg298 -> %RCX] GR64
[%vreg300 -> %EAX] GR32
[%vreg301 -> %RAX] GR64
[%vreg305 -> %ECX] GR32
[%vreg307 -> %RAX] GR64
[%vreg310 -> %RCX] GR64
[%vreg313 -> %EAX] GR32
[%vreg317 -> %EDX] GR32
[%vreg322 -> %ECX] GR32
[%vreg327 -> %RCX] GR64
[%vreg333 -> %RDX] GR64
[%vreg334 -> %RDX] GR64
[%vreg337 -> %RCX] GR64_NOSP
[%vreg339 -> %ECX] GR32
[%vreg342 -> %RCX] GR64
[%vreg348 -> %RCX] GR64
[%vreg349 -> %RCX] GR64
[%vreg352 -> %RAX] GR64_NOSP
[%vreg354 -> %RAX] GR64
[%vreg360 -> %EAX] GR32
[%vreg363 -> %RSI] GR64
[%vreg366 -> %EDI] GR32
[%vreg367 -> %RAX] GR64
[%vreg369 -> %RAX] GR64
[%vreg373 -> %RCX] GR64
[%vreg375 -> %EAX] GR32
[%vreg379 -> %ECX] GR32
[%vreg381 -> %RAX] GR64
[%vreg384 -> %RCX] GR64
[%vreg387 -> %EAX] GR32
[%vreg391 -> %EDX] GR32
[%vreg396 -> %ECX] GR32
[%vreg401 -> %RCX] GR64
[%vreg407 -> %RDX] GR64
[%vreg408 -> %RDX] GR64
[%vreg411 -> %RCX] GR64_NOSP
[%vreg413 -> %ECX] GR32
[%vreg416 -> %RCX] GR64
[%vreg422 -> %RCX] GR64
[%vreg423 -> %RCX] GR64
[%vreg426 -> %RAX] GR64_NOSP
[%vreg428 -> %RAX] GR64
[%vreg431 -> %RCX] GR64
[%vreg434 -> %EAX] GR32
[%vreg437 -> %RSI] GR64
[%vreg440 -> %EDI] GR32
[%vreg441 -> %RAX] GR64
[%vreg444 -> %RCX] GR64
[%vreg446 -> %EAX] GR32
[%vreg452 -> %ECX] GR32
[%vreg454 -> %RAX] GR64
[%vreg457 -> %RCX] GR64
[%vreg460 -> %EAX] GR32
[%vreg464 -> %EDX] GR32
[%vreg469 -> %ECX] GR32
[%vreg474 -> %RCX] GR64
[%vreg480 -> %RDX] GR64
[%vreg481 -> %RDX] GR64
[%vreg484 -> %RCX] GR64_NOSP
[%vreg486 -> %ECX] GR32
[%vreg489 -> %RCX] GR64
[%vreg495 -> %RCX] GR64
[%vreg496 -> %RCX] GR64
[%vreg499 -> %RAX] GR64_NOSP
[%vreg501 -> %RAX] GR64
[%vreg507 -> %EAX] GR32
[%vreg510 -> %RSI] GR64
[%vreg513 -> %EDI] GR32
[%vreg514 -> %RAX] GR64
[%vreg517 -> %RCX] GR64
[%vreg519 -> %EAX] GR32
[%vreg522 -> %RCX] GR64
[%vreg524 -> %EAX] GR32
[%vreg527 -> %RCX] GR64
[%vreg529 -> %EAX] GR32
[%vreg533 -> %RAX] GR64
[%vreg534 -> %RAX] GR64
[%vreg537 -> %RAX] GR64
[%vreg541 -> %RAX] GR64
[%vreg542 -> %RAX] GR64
[%vreg546 -> %ECX] GR32
[%vreg549 -> %RAX] GR64
[%vreg550 -> %RAX] GR64
[%vreg554 -> %ECX] GR32
[%vreg557 -> %RAX] GR64
[%vreg558 -> %RAX] GR64
[%vreg562 -> %RCX] GR64
[%vreg565 -> %RAX] GR64
[%vreg566 -> %RAX] GR64
[%vreg570 -> %ECX] GR32
[%vreg572 -> %RAX] GR64
[%vreg575 -> %RCX] GR64
[%vreg578 -> %EAX] GR32
[%vreg582 -> %RCX] GR64_NOSP
[%vreg585 -> %ECX] GR32
[%vreg587 -> %EDX] GR32
[%vreg589 -> %RDX] GR64
[%vreg594 -> %RCX] GR64
[%vreg599 -> %RAX] GR64
[%vreg603 -> %RCX] GR64
[%vreg605 -> %RCX] GR64
[%vreg606 -> %RCX] GR64
[%vreg608 -> %AL] GR8
[%vreg609 -> %RAX] GR64
[%vreg613 -> %ECX] GR32
[%vreg616 -> %RAX] GR64
[%vreg617 -> %RAX] GR64
[%vreg621 -> %ECX] GR32
[%vreg624 -> %RCX] GR64
[%vreg626 -> %EAX] GR32
[%vreg627 -> %RAX] GR64
[%vreg631 -> %ECX] GR32
[%vreg634 -> %RCX] GR64
[%vreg636 -> %EAX] GR32
[%vreg637 -> %RAX] GR64
[%vreg640 -> %RAX] GR64
[%vreg643 -> %RCX] GR64
[%vreg646 -> %EAX] GR32
[%vreg650 -> %EDX] GR32
[%vreg655 -> %ECX] GR32
[%vreg660 -> %RCX] GR64
[%vreg666 -> %RDX] GR64
[%vreg667 -> %RDX] GR64
[%vreg670 -> %RCX] GR64_NOSP
[%vreg672 -> %ECX] GR32
[%vreg675 -> %RCX] GR64
[%vreg681 -> %RCX] GR64
[%vreg682 -> %RCX] GR64
[%vreg685 -> %RAX] GR64_NOSP
[%vreg687 -> %RAX] GR64
[%vreg693 -> %EAX] GR32
[%vreg696 -> %RSI] GR64
[%vreg699 -> %EDI] GR32
[%vreg700 -> %RAX] GR64
[%vreg703 -> %RCX] GR64
[%vreg707 -> %EAX] GR32
[%vreg708 -> %RAX] GR64
[%vreg710 -> %RAX] GR64
[%vreg713 -> %RAX] GR64
[%vreg717 -> %ECX] GR32
[%vreg719 -> %RAX] GR64
[%vreg722 -> %RCX] GR64
[%vreg724 -> %EAX] GR32
[%vreg726 -> %RAX] GR64_NOSP
[%vreg728 -> %RAX] GR64
[%vreg730 -> %RAX] GR64
[%vreg734 -> %ECX] GR32
[%vreg737 -> %RCX] GR64
[%vreg739 -> %EAX] GR32
[%vreg740 -> %RAX] GR64
[%vreg744 -> %ECX] GR32
[%vreg746 -> %RAX] GR64
[%vreg752 -> %ECX] GR32
[%vreg757 -> %ECX] GR32
[%vreg758 -> %EAX] GR32
[%vreg760 -> %RDX] GR64
[%vreg764 -> %ESI] GR32
[%vreg766 -> %RDX] GR64
[%vreg770 -> %RCX] GR64
[%vreg772 -> %EAX] GR32
[%vreg775 -> %RAX] GR64
[%vreg778 -> %RCX] GR64
[%vreg781 -> %EAX] GR32
[%vreg785 -> %EDX] GR32
[%vreg790 -> %ECX] GR32
[%vreg795 -> %RCX] GR64
[%vreg801 -> %RDX] GR64
[%vreg802 -> %RDX] GR64
[%vreg805 -> %RCX] GR64_NOSP
[%vreg807 -> %ECX] GR32
[%vreg810 -> %RCX] GR64
[%vreg816 -> %RCX] GR64
[%vreg817 -> %RCX] GR64
[%vreg820 -> %RAX] GR64_NOSP
[%vreg822 -> %RAX] GR64
[%vreg828 -> %EAX] GR32
[%vreg831 -> %RSI] GR64
[%vreg834 -> %EDI] GR32
[%vreg835 -> %RAX] GR64
[%vreg837 -> %RAX] GR64
[%vreg840 -> %RAX] GR64
[%vreg844 -> %ECX] GR32
[%vreg846 -> %RAX] GR64
[%vreg849 -> %RCX] GR64
[%vreg851 -> %EAX] GR32
[%vreg853 -> %RAX] GR64_NOSP
[%vreg855 -> %RAX] GR64
[%vreg857 -> %RAX] GR64
[%vreg861 -> %ECX] GR32
[%vreg864 -> %RCX] GR64
[%vreg866 -> %EAX] GR32
[%vreg867 -> %RAX] GR64
[%vreg871 -> %ECX] GR32
[%vreg873 -> %RAX] GR64
[%vreg879 -> %ECX] GR32
[%vreg884 -> %ECX] GR32
[%vreg885 -> %EAX] GR32
[%vreg887 -> %RDX] GR64
[%vreg891 -> %ESI] GR32
[%vreg893 -> %RDX] GR64
[%vreg897 -> %RCX] GR64
[%vreg899 -> %EAX] GR32
[%vreg902 -> %RAX] GR64
[%vreg905 -> %RCX] GR64
[%vreg908 -> %EAX] GR32
[%vreg912 -> %EDX] GR32
[%vreg917 -> %ECX] GR32
[%vreg922 -> %RCX] GR64
[%vreg928 -> %RDX] GR64
[%vreg929 -> %RDX] GR64
[%vreg932 -> %RCX] GR64_NOSP
[%vreg934 -> %ECX] GR32
[%vreg937 -> %RCX] GR64
[%vreg943 -> %RCX] GR64
[%vreg944 -> %RCX] GR64
[%vreg947 -> %RAX] GR64_NOSP
[%vreg949 -> %RAX] GR64
[%vreg955 -> %EAX] GR32
[%vreg958 -> %RSI] GR64
[%vreg961 -> %EDI] GR32
[%vreg962 -> %RAX] GR64
[%vreg964 -> %RAX] GR64
[%vreg967 -> %RAX] GR64
[%vreg971 -> %ECX] GR32
[%vreg973 -> %RAX] GR64
[%vreg976 -> %RCX] GR64
[%vreg978 -> %EAX] GR32
[%vreg980 -> %RAX] GR64_NOSP
[%vreg982 -> %RAX] GR64
[%vreg984 -> %RAX] GR64
[%vreg988 -> %ECX] GR32
[%vreg991 -> %RCX] GR64
[%vreg993 -> %EAX] GR32
[%vreg994 -> %RAX] GR64
[%vreg998 -> %ECX] GR32
[%vreg1000 -> %RAX] GR64
[%vreg1006 -> %ECX] GR32
[%vreg1011 -> %ECX] GR32
[%vreg1012 -> %EAX] GR32
[%vreg1014 -> %RDX] GR64
[%vreg1018 -> %ESI] GR32
[%vreg1020 -> %RDX] GR64
[%vreg1024 -> %RCX] GR64
[%vreg1026 -> %EAX] GR32
[%vreg1029 -> %RAX] GR64
[%vreg1032 -> %RCX] GR64
[%vreg1035 -> %EAX] GR32
[%vreg1039 -> %EDX] GR32
[%vreg1044 -> %ECX] GR32
[%vreg1049 -> %RCX] GR64
[%vreg1055 -> %RDX] GR64
[%vreg1056 -> %RDX] GR64
[%vreg1059 -> %RCX] GR64_NOSP
[%vreg1061 -> %ECX] GR32
[%vreg1064 -> %RCX] GR64
[%vreg1070 -> %RCX] GR64
[%vreg1071 -> %RCX] GR64
[%vreg1074 -> %RAX] GR64_NOSP
[%vreg1076 -> %RAX] GR64
[%vreg1082 -> %EAX] GR32
[%vreg1085 -> %RSI] GR64
[%vreg1088 -> %EDI] GR32
[%vreg1089 -> %RAX] GR64
[%vreg1092 -> %RAX] GR64
[%vreg1096 -> %ECX] GR32
[%vreg1098 -> %RAX] GR64
[%vreg1101 -> %RCX] GR64
[%vreg1103 -> %EAX] GR32
[%vreg1105 -> %RAX] GR64_NOSP
[%vreg1107 -> %RAX] GR64
[%vreg1109 -> %RAX] GR64
[%vreg1112 -> %RAX] GR64
[%vreg1115 -> %RCX] GR64
[%vreg1118 -> %EAX] GR32
[%vreg1122 -> %EDX] GR32
[%vreg1127 -> %ECX] GR32
[%vreg1132 -> %RCX] GR64
[%vreg1138 -> %RDX] GR64
[%vreg1139 -> %RDX] GR64
[%vreg1142 -> %RCX] GR64_NOSP
[%vreg1144 -> %ECX] GR32
[%vreg1147 -> %RCX] GR64
[%vreg1153 -> %RCX] GR64
[%vreg1154 -> %RCX] GR64
[%vreg1157 -> %RAX] GR64_NOSP
[%vreg1159 -> %RAX] GR64
[%vreg1162 -> %RCX] GR64
[%vreg1165 -> %EAX] GR32
[%vreg1168 -> %RSI] GR64
[%vreg1171 -> %EDI] GR32
[%vreg1172 -> %RAX] GR64
[%vreg1175 -> %RCX] GR64
[%vreg1177 -> %EAX] GR32
[%vreg1183 -> %ECX] GR32
[%vreg1185 -> %RAX] GR64
[%vreg1191 -> %ECX] GR32
[%vreg1196 -> %ECX] GR32
[%vreg1197 -> %EAX] GR32
[%vreg1199 -> %RDX] GR64
[%vreg1203 -> %ESI] GR32
[%vreg1205 -> %RDX] GR64
[%vreg1208 -> %RAX] GR64
[%vreg1212 -> %ECX] GR32
[%vreg1214 -> %RAX] GR64
[%vreg1217 -> %RCX] GR64
[%vreg1219 -> %EAX] GR32
[%vreg1221 -> %RAX] GR64_NOSP
[%vreg1223 -> %RAX] GR64
[%vreg1225 -> %RAX] GR64
[%vreg1229 -> %ECX] GR32
[%vreg1231 -> %RAX] GR64
[%vreg1236 -> %EAX] GR32
[%vreg1237 -> %RCX] GR64
[%vreg1240 -> %ECX] GR32
[%vreg1243 -> %RDX] GR64
[%vreg1247 -> %ESI] GR32
[%vreg1249 -> %RDX] GR64
[%vreg1252 -> %RCX] GR64
[%vreg1254 -> %EAX] GR32
[%vreg1257 -> %RCX] GR64
[%vreg1259 -> %EAX] GR32
[%vreg1262 -> %RCX] GR64
[%vreg1264 -> %EAX] GR32
[%vreg1266 -> %AL] GR8
[%vreg1268 -> %RDI] GR64
[%vreg1269 -> %RSI] GR64

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI
16B		%vreg1<def> = COPY %RDI; GR64:%vreg1
48B		%vreg6<def> = MOV64ri <ga:@unRLE_obuf_to_output_SMALL>; GR64:%vreg6
80B		%vreg7<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg7
96B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
112B		%RDI<def> = COPY %vreg6<kill>; GR64:%vreg6
128B		%RSI<def> = COPY %vreg7<kill>; GR64:%vreg7
144B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
160B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
192B		STACKMAP 0, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, %vreg1, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1] GR64:%vreg1
208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg1<kill>; mem:ST8[%s.addr] GR64:%vreg1
240B		%vreg4<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg4
256B		CMP8mi %vreg4<kill>, 1, %noreg, 20, %noreg, 0, %EFLAGS<imp-def>; mem:LD1[%blockRandomised] GR64:%vreg4
272B		JE_1 <BB#47>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#47 BB#1
> %RBX<def> = COPY %RDI
> %RDI<def> = MOV64ri <ga:@unRLE_obuf_to_output_SMALL>
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 0, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, %RBX, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %RBX<kill>; mem:ST8[%s.addr]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> CMP8mi %RAX<kill>, 1, %noreg, 20, %noreg, 0, %EFLAGS<imp-def>; mem:LD1[%blockRandomised]
> JE_1 <BB#47>, %EFLAGS<imp-use,kill>
288B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
304B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2
> JMP_1 <BB#2>
320B	BB#2: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#1 BB#46 BB#37 BB#35 BB#29 BB#27 BB#21 BB#19
336B		JMP_1 <BB#3>
	    Successors according to CFG: BB#3
> JMP_1 <BB#3>
352B	BB#3: derived from LLVM BB %while.body.2
	    Predecessors according to CFG: BB#2 BB#9
368B		%vreg534<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg534
384B		%vreg533<def> = MOV64rm %vreg534<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm] GR64:%vreg533,%vreg534
400B		CMP32mi8 %vreg533<kill>, 1, %noreg, 32, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_out] GR64:%vreg533
416B		JNE_1 <BB#5>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#5 BB#4
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm]
> CMP32mi8 %RAX<kill>, 1, %noreg, 32, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_out]
> JNE_1 <BB#5>, %EFLAGS<imp-use,kill>
432B	BB#4: derived from LLVM BB %if.then.3
	    Predecessors according to CFG: BB#3
448B		MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST1[%retval]
464B		JMP_1 <BB#73>
	    Successors according to CFG: BB#73
> MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST1[%retval]
> JMP_1 <BB#73>
480B	BB#5: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#3
496B		%vreg537<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg537
512B		CMP32mi8 %vreg537<kill>, 1, %noreg, 16, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%state_out_len] GR64:%vreg537
528B		JNE_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#6
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> CMP32mi8 %RAX<kill>, 1, %noreg, 16, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%state_out_len]
> JNE_1 <BB#7>, %EFLAGS<imp-use,kill>
544B	BB#6: derived from LLVM BB %if.then.5
	    Predecessors according to CFG: BB#5
560B		JMP_1 <BB#10>
	    Successors according to CFG: BB#10
> JMP_1 <BB#10>
576B	BB#7: derived from LLVM BB %if.end.6
	    Predecessors according to CFG: BB#5
592B		%vreg609<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg609
608B		%vreg608<def> = MOV8rm %vreg609<kill>, 1, %noreg, 12, %noreg; mem:LD1[%state_out_ch] GR8:%vreg608 GR64:%vreg609
624B		%vreg606<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg606
640B		%vreg605<def> = MOV64rm %vreg606<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm7] GR64:%vreg605,%vreg606
656B		%vreg603<def> = MOV64rm %vreg605<kill>, 1, %noreg, 24, %noreg; mem:LD8[%next_out] GR64:%vreg603,%vreg605
672B		MOV8mr %vreg603<kill>, 1, %noreg, 0, %noreg, %vreg608<kill>; mem:ST1[%11] GR64:%vreg603 GR8:%vreg608
688B		%vreg599<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg599
704B		%vreg578<def> = MOV32rm %vreg599<kill>, 1, %noreg, 3184, %noreg; mem:LD4[%calculatedBlockCRC] GR32:%vreg578 GR64:%vreg599
736B		%vreg578<def,tied1> = SHL32ri %vreg578<kill,tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg578
752B		%vreg594<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg594
768B		%vreg585<def> = MOV32rm %vreg594<kill>, 1, %noreg, 3184, %noreg; mem:LD4[%calculatedBlockCRC8] GR32:%vreg585 GR64:%vreg594
800B		%vreg585<def,tied1> = SHR32ri %vreg585<kill,tied0>, 24, %EFLAGS<imp-def,dead>; GR32:%vreg585
816B		%vreg589<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg589
832B		%vreg587<def> = MOVZX32rm8 %vreg589<kill>, 1, %noreg, 12, %noreg; mem:LD1[%state_out_ch9] GR32:%vreg587 GR64:%vreg589
864B		%vreg585<def,tied1> = XOR32rr %vreg585<kill,tied0>, %vreg587<kill>, %EFLAGS<imp-def,dead>; GR32:%vreg585,%vreg587
880B		%vreg582:sub_32bit<def,read-undef> = MOV32rr %vreg585<kill>; GR64_NOSP:%vreg582 GR32:%vreg585
928B		%vreg578<def,tied1> = XOR32rm %vreg578<kill,tied0>, %noreg, 4, %vreg582<kill>, <ga:@BZ2_crc32Table>, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%arrayidx] GR32:%vreg578 GR64_NOSP:%vreg582
944B		%vreg575<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg575
960B		MOV32mr %vreg575<kill>, 1, %noreg, 3184, %noreg, %vreg578<kill>; mem:ST4[%calculatedBlockCRC11] GR64:%vreg575 GR32:%vreg578
976B		%vreg572<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg572
992B		%vreg570<def> = MOV32rm %vreg572, 1, %noreg, 16, %noreg; mem:LD4[%state_out_len12] GR32:%vreg570 GR64:%vreg572
1024B		%vreg570<def,tied1> = ADD32ri8 %vreg570<kill,tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg570
1040B		MOV32mr %vreg572<kill>, 1, %noreg, 16, %noreg, %vreg570<kill>; mem:ST4[%state_out_len12] GR64:%vreg572 GR32:%vreg570
1056B		%vreg566<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg566
1072B		%vreg565<def> = MOV64rm %vreg566<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm13] GR64:%vreg565,%vreg566
1088B		%vreg562<def> = MOV64rm %vreg565, 1, %noreg, 24, %noreg; mem:LD8[%next_out14] GR64:%vreg562,%vreg565
1120B		%vreg562<def,tied1> = ADD64ri8 %vreg562<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR64:%vreg562
1136B		MOV64mr %vreg565<kill>, 1, %noreg, 24, %noreg, %vreg562<kill>; mem:ST8[%next_out14] GR64:%vreg565,%vreg562
1152B		%vreg558<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg558
1168B		%vreg557<def> = MOV64rm %vreg558<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm15] GR64:%vreg557,%vreg558
1184B		%vreg554<def> = MOV32rm %vreg557, 1, %noreg, 32, %noreg; mem:LD4[%avail_out16] GR32:%vreg554 GR64:%vreg557
1216B		%vreg554<def,tied1> = ADD32ri8 %vreg554<kill,tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg554
1232B		MOV32mr %vreg557<kill>, 1, %noreg, 32, %noreg, %vreg554<kill>; mem:ST4[%avail_out16] GR64:%vreg557 GR32:%vreg554
1248B		%vreg550<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg550
1264B		%vreg549<def> = MOV64rm %vreg550<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm18] GR64:%vreg549,%vreg550
1280B		%vreg546<def> = MOV32rm %vreg549, 1, %noreg, 36, %noreg; mem:LD4[%total_out_lo32] GR32:%vreg546 GR64:%vreg549
1312B		%vreg546<def,tied1> = ADD32ri8 %vreg546<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg546
1328B		MOV32mr %vreg549<kill>, 1, %noreg, 36, %noreg, %vreg546<kill>; mem:ST4[%total_out_lo32] GR64:%vreg549 GR32:%vreg546
1344B		%vreg542<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg542
1360B		%vreg541<def> = MOV64rm %vreg542<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm19] GR64:%vreg541,%vreg542
1376B		CMP32mi8 %vreg541<kill>, 1, %noreg, 36, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%total_out_lo3220] GR64:%vreg541
1392B		JNE_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#8
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %AL<def> = MOV8rm %RAX<kill>, 1, %noreg, 12, %noreg; mem:LD1[%state_out_ch]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RCX<def> = MOV64rm %RCX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm7]
> %RCX<def> = MOV64rm %RCX<kill>, 1, %noreg, 24, %noreg; mem:LD8[%next_out]
> MOV8mr %RCX<kill>, 1, %noreg, 0, %noreg, %AL<kill>; mem:ST1[%11]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 3184, %noreg; mem:LD4[%calculatedBlockCRC]
> %EAX<def,tied1> = SHL32ri %EAX<kill,tied0>, 8, %EFLAGS<imp-def,dead>
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RCX<kill>, 1, %noreg, 3184, %noreg; mem:LD4[%calculatedBlockCRC8]
> %ECX<def,tied1> = SHR32ri %ECX<kill,tied0>, 24, %EFLAGS<imp-def,dead>
> %RDX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EDX<def> = MOVZX32rm8 %RDX<kill>, 1, %noreg, 12, %noreg; mem:LD1[%state_out_ch9]
> %ECX<def,tied1> = XOR32rr %ECX<kill,tied0>, %EDX<kill>, %EFLAGS<imp-def,dead>
> %ECX<def> = MOV32rr %ECX<kill>, %RCX<imp-def>
> %EAX<def,tied1> = XOR32rm %EAX<kill,tied0>, %noreg, 4, %RCX<kill>, <ga:@BZ2_crc32Table>, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%arrayidx]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mr %RCX<kill>, 1, %noreg, 3184, %noreg, %EAX<kill>; mem:ST4[%calculatedBlockCRC11]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 16, %noreg; mem:LD4[%state_out_len12]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, -1, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 16, %noreg, %ECX<kill>; mem:ST4[%state_out_len12]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm13]
> %RCX<def> = MOV64rm %RAX, 1, %noreg, 24, %noreg; mem:LD8[%next_out14]
> %RCX<def,tied1> = ADD64ri8 %RCX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV64mr %RAX<kill>, 1, %noreg, 24, %noreg, %RCX<kill>; mem:ST8[%next_out14]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm15]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 32, %noreg; mem:LD4[%avail_out16]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, -1, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 32, %noreg, %ECX<kill>; mem:ST4[%avail_out16]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm18]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 36, %noreg; mem:LD4[%total_out_lo32]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 36, %noreg, %ECX<kill>; mem:ST4[%total_out_lo32]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm19]
> CMP32mi8 %RAX<kill>, 1, %noreg, 36, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%total_out_lo3220]
> JNE_1 <BB#9>, %EFLAGS<imp-use,kill>
1408B	BB#8: derived from LLVM BB %if.then.23
	    Predecessors according to CFG: BB#7
1424B		%vreg617<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg617
1440B		%vreg616<def> = MOV64rm %vreg617<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm24] GR64:%vreg616,%vreg617
1456B		%vreg613<def> = MOV32rm %vreg616, 1, %noreg, 40, %noreg; mem:LD4[%total_out_hi32] GR32:%vreg613 GR64:%vreg616
1488B		%vreg613<def,tied1> = ADD32ri8 %vreg613<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg613
1504B		MOV32mr %vreg616<kill>, 1, %noreg, 40, %noreg, %vreg613<kill>; mem:ST4[%total_out_hi32] GR64:%vreg616 GR32:%vreg613
	    Successors according to CFG: BB#9
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm24]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 40, %noreg; mem:LD4[%total_out_hi32]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 40, %noreg, %ECX<kill>; mem:ST4[%total_out_hi32]
1520B	BB#9: derived from LLVM BB %if.end.26
	    Predecessors according to CFG: BB#7 BB#8
1536B		JMP_1 <BB#3>
	    Successors according to CFG: BB#3
> JMP_1 <BB#3>
1552B	BB#10: derived from LLVM BB %while.end
	    Predecessors according to CFG: BB#6
1568B		%vreg627<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg627
1584B		%vreg626<def> = MOV32rm %vreg627<kill>, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used] GR32:%vreg626 GR64:%vreg627
1600B		%vreg624<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg624
1616B		%vreg621<def> = MOV32rm %vreg624<kill>, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock] GR32:%vreg621 GR64:%vreg624
1648B		%vreg621<def,tied1> = ADD32ri8 %vreg621<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg621
1664B		CMP32rr %vreg626<kill>, %vreg621<kill>, %EFLAGS<imp-def>; GR32:%vreg626,%vreg621
1680B		JNE_1 <BB#12>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#12 BB#11
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RCX<kill>, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> CMP32rr %EAX<kill>, %ECX<kill>, %EFLAGS<imp-def>
> JNE_1 <BB#12>, %EFLAGS<imp-use,kill>
1696B	BB#11: derived from LLVM BB %if.then.29
	    Predecessors according to CFG: BB#10
1712B		MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST1[%retval]
1728B		JMP_1 <BB#73>
	    Successors according to CFG: BB#73
> MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST1[%retval]
> JMP_1 <BB#73>
1744B	BB#12: derived from LLVM BB %if.end.30
	    Predecessors according to CFG: BB#10
1760B		%vreg637<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg637
1776B		%vreg636<def> = MOV32rm %vreg637<kill>, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used31] GR32:%vreg636 GR64:%vreg637
1792B		%vreg634<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg634
1808B		%vreg631<def> = MOV32rm %vreg634<kill>, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock32] GR32:%vreg631 GR64:%vreg634
1840B		%vreg631<def,tied1> = ADD32ri8 %vreg631<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg631
1856B		CMP32rr %vreg636<kill>, %vreg631<kill>, %EFLAGS<imp-def>; GR32:%vreg636,%vreg631
1872B		JLE_1 <BB#14>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#14 BB#13
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used31]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RCX<kill>, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock32]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> CMP32rr %EAX<kill>, %ECX<kill>, %EFLAGS<imp-def>
> JLE_1 <BB#14>, %EFLAGS<imp-use,kill>
1888B	BB#13: derived from LLVM BB %if.then.36
	    Predecessors according to CFG: BB#12
1904B		MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 1; mem:ST1[%retval]
1920B		JMP_1 <BB#73>
	    Successors according to CFG: BB#73
> MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 1; mem:ST1[%retval]
> JMP_1 <BB#73>
1936B	BB#14: derived from LLVM BB %if.end.37
	    Predecessors according to CFG: BB#12
1952B		%vreg710<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg710
1968B		MOV32mi %vreg710<kill>, 1, %noreg, 16, %noreg, 1; mem:ST4[%state_out_len38] GR64:%vreg710
1984B		%vreg708<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg708
2000B		%vreg707<def> = MOV32rm %vreg708<kill>, 1, %noreg, 64, %noreg; mem:LD4[%k0] GR32:%vreg707 GR64:%vreg708
2032B		%vreg703<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg703
2048B		MOV8mr %vreg703<kill>, 1, %noreg, 12, %noreg, %vreg707:sub_8bit<kill>; mem:ST1[%state_out_ch40] GR64:%vreg703 GR32:%vreg707
2064B		%vreg700<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg700
2080B		%vreg699<def> = MOV32rm %vreg700<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos] GR32:%vreg699 GR64:%vreg700
2096B		%vreg696<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg696
2128B		%vreg696<def,tied1> = ADD64ri32 %vreg696<kill,tied0>, 1096, %EFLAGS<imp-def,dead>; GR64:%vreg696
2144B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2160B		%EDI<def> = COPY %vreg699<kill>; GR32:%vreg699
2176B		%RSI<def> = COPY %vreg696<kill>; GR64:%vreg696
2192B		CALL64pcrel32 <ga:@BZ2_indexIntoF>, <regmask>, %RSP<imp-use>, %EDI<imp-use>, %RSI<imp-use>, %EAX<imp-def>
2208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2224B		%vreg693<def> = COPY %EAX; GR32:%vreg693
2240B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2256B		STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
2272B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2304B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg693:sub_8bit<kill>; mem:ST1[%k1] GR32:%vreg693
2320B		%vreg687<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg687
2336B		%vreg685:sub_32bit<def,read-undef> = MOV32rm %vreg687<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos42] GR64_NOSP:%vreg685 GR64:%vreg687
2368B		%vreg682<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg682
2384B		%vreg681<def> = MOV64rm %vreg682<kill>, 1, %noreg, 3160, %noreg; mem:LD8[%ll16] GR64:%vreg681,%vreg682
2400B		%vreg646<def> = MOVZX32rm16 %vreg681<kill>, 2, %vreg685<kill>, 0, %noreg; mem:LD2[%arrayidx44] GR32:%vreg646 GR64:%vreg681 GR64_NOSP:%vreg685
2416B		%vreg675<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg675
2432B		%vreg672<def> = MOV32rm %vreg675<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos46] GR32:%vreg672 GR64:%vreg675
2464B		%vreg672<def,tied1> = SHR32ri %vreg672<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg672
2480B		%vreg670:sub_32bit<def,read-undef> = MOV32rr %vreg672<kill>; GR64_NOSP:%vreg670 GR32:%vreg672
2512B		%vreg667<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg667
2528B		%vreg666<def> = MOV64rm %vreg667<kill>, 1, %noreg, 3168, %noreg; mem:LD8[%ll4] GR64:%vreg666,%vreg667
2544B		%vreg650<def> = MOVZX32rm8 %vreg666<kill>, 1, %vreg670<kill>, 0, %noreg; mem:LD1[%arrayidx49] GR32:%vreg650 GR64:%vreg666 GR64_NOSP:%vreg670
2560B		%vreg660<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg660
2576B		%vreg655<def> = MOV32rm %vreg660<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos51] GR32:%vreg655 GR64:%vreg660
2608B		%vreg655<def,tied1> = SHL32ri %vreg655<kill,tied0>, 2, %EFLAGS<imp-def,dead>; GR32:%vreg655
2640B		%vreg655<def,tied1> = AND32ri8 %vreg655<kill,tied0>, 4, %EFLAGS<imp-def,dead>; GR32:%vreg655
2656B		%ECX<def> = COPY %vreg655<kill>; GR32:%vreg655
2672B		%CL<def> = KILL %ECX
2704B		%vreg650<def,tied1> = SHR32rCL %vreg650<kill,tied0>, %EFLAGS<imp-def,dead>, %CL<imp-use>; GR32:%vreg650
2736B		%vreg650<def,tied1> = AND32ri8 %vreg650<kill,tied0>, 15, %EFLAGS<imp-def,dead>; GR32:%vreg650
2768B		%vreg650<def,tied1> = SHL32ri %vreg650<kill,tied0>, 16, %EFLAGS<imp-def,dead>; GR32:%vreg650
2800B		%vreg646<def,tied1> = OR32rr %vreg646<kill,tied0>, %vreg650<kill>, %EFLAGS<imp-def,dead>; GR32:%vreg646,%vreg650
2816B		%vreg643<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg643
2832B		MOV32mr %vreg643<kill>, 1, %noreg, 60, %noreg, %vreg646<kill>; mem:ST4[%tPos56] GR64:%vreg643 GR32:%vreg646
2848B		%vreg640<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg640
2864B		CMP32mi8 %vreg640<kill>, 1, %noreg, 24, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%rNToGo] GR64:%vreg640
2880B		JNE_1 <BB#18>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#18 BB#15
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 16, %noreg, 1; mem:ST4[%state_out_len38]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 64, %noreg; mem:LD4[%k0]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV8mr %RCX<kill>, 1, %noreg, 12, %noreg, %AL, %EAX<imp-use,kill>; mem:ST1[%state_out_ch40]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EDI<def> = MOV32rm %RAX<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos]
> %RSI<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RSI<def,tied1> = ADD64ri32 %RSI<kill,tied0>, 1096, %EFLAGS<imp-def,dead>
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EDI<def> = COPY %EDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@BZ2_indexIntoF>, <regmask>, %RSP<imp-use>, %EDI<imp-use>, %RSI<imp-use>, %EAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def> = COPY %EAX
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %AL, %EAX<imp-use,kill>; mem:ST1[%k1]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 60, %noreg, %RAX<imp-def>; mem:LD4[%tPos42]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RCX<def> = MOV64rm %RCX<kill>, 1, %noreg, 3160, %noreg; mem:LD8[%ll16]
> %EAX<def> = MOVZX32rm16 %RCX<kill>, 2, %RAX<kill>, 0, %noreg; mem:LD2[%arrayidx44]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RCX<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos46]
> %ECX<def,tied1> = SHR32ri %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> %ECX<def> = MOV32rr %ECX<kill>, %RCX<imp-def>
> %RDX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RDX<def> = MOV64rm %RDX<kill>, 1, %noreg, 3168, %noreg; mem:LD8[%ll4]
> %EDX<def> = MOVZX32rm8 %RDX<kill>, 1, %RCX<kill>, 0, %noreg; mem:LD1[%arrayidx49]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RCX<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos51]
> %ECX<def,tied1> = SHL32ri %ECX<kill,tied0>, 2, %EFLAGS<imp-def,dead>
> %ECX<def,tied1> = AND32ri8 %ECX<kill,tied0>, 4, %EFLAGS<imp-def,dead>
> %ECX<def> = COPY %ECX<kill>
Deleting identity copy.
> %CL<def> = KILL %ECX
> %EDX<def,tied1> = SHR32rCL %EDX<kill,tied0>, %EFLAGS<imp-def,dead>, %CL<imp-use>
> %EDX<def,tied1> = AND32ri8 %EDX<kill,tied0>, 15, %EFLAGS<imp-def,dead>
> %EDX<def,tied1> = SHL32ri %EDX<kill,tied0>, 16, %EFLAGS<imp-def,dead>
> %EAX<def,tied1> = OR32rr %EAX<kill,tied0>, %EDX<kill>, %EFLAGS<imp-def,dead>
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mr %RCX<kill>, 1, %noreg, 60, %noreg, %EAX<kill>; mem:ST4[%tPos56]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> CMP32mi8 %RAX<kill>, 1, %noreg, 24, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%rNToGo]
> JNE_1 <BB#18>, %EFLAGS<imp-use,kill>
2896B	BB#15: derived from LLVM BB %if.then.59
	    Predecessors according to CFG: BB#14
2912B		%vreg728<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg728
2928B		%vreg726<def> = MOVSX64rm32 %vreg728<kill>, 1, %noreg, 28, %noreg; mem:LD4[%rTPos] GR64_NOSP:%vreg726 GR64:%vreg728
2944B		%vreg724<def> = MOV32rm %noreg, 4, %vreg726<kill>, <ga:@BZ2_rNums>, %noreg; mem:LD4[%arrayidx61] GR32:%vreg724 GR64_NOSP:%vreg726
2960B		%vreg722<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg722
2976B		MOV32mr %vreg722<kill>, 1, %noreg, 24, %noreg, %vreg724<kill>; mem:ST4[%rNToGo62] GR64:%vreg722 GR32:%vreg724
2992B		%vreg719<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg719
3008B		%vreg717<def> = MOV32rm %vreg719, 1, %noreg, 28, %noreg; mem:LD4[%rTPos63] GR32:%vreg717 GR64:%vreg719
3040B		%vreg717<def,tied1> = ADD32ri8 %vreg717<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg717
3056B		MOV32mr %vreg719<kill>, 1, %noreg, 28, %noreg, %vreg717<kill>; mem:ST4[%rTPos63] GR64:%vreg719 GR32:%vreg717
3072B		%vreg713<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg713
3088B		CMP32mi %vreg713<kill>, 1, %noreg, 28, %noreg, 512, %EFLAGS<imp-def>; mem:LD4[%rTPos65] GR64:%vreg713
3104B		JNE_1 <BB#17>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#17 BB#16
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RAX<def> = MOVSX64rm32 %RAX<kill>, 1, %noreg, 28, %noreg; mem:LD4[%rTPos]
> %EAX<def> = MOV32rm %noreg, 4, %RAX<kill>, <ga:@BZ2_rNums>, %noreg; mem:LD4[%arrayidx61]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mr %RCX<kill>, 1, %noreg, 24, %noreg, %EAX<kill>; mem:ST4[%rNToGo62]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 28, %noreg; mem:LD4[%rTPos63]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 28, %noreg, %ECX<kill>; mem:ST4[%rTPos63]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> CMP32mi %RAX<kill>, 1, %noreg, 28, %noreg, 512, %EFLAGS<imp-def>; mem:LD4[%rTPos65]
> JNE_1 <BB#17>, %EFLAGS<imp-use,kill>
3120B	BB#16: derived from LLVM BB %if.then.68
	    Predecessors according to CFG: BB#15
3136B		%vreg730<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg730
3152B		MOV32mi %vreg730<kill>, 1, %noreg, 28, %noreg, 0; mem:ST4[%rTPos69] GR64:%vreg730
	    Successors according to CFG: BB#17
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 28, %noreg, 0; mem:ST4[%rTPos69]
3168B	BB#17: derived from LLVM BB %if.end.70
	    Predecessors according to CFG: BB#15 BB#16
3184B		JMP_1 <BB#18>
	    Successors according to CFG: BB#18
> JMP_1 <BB#18>
3200B	BB#18: derived from LLVM BB %if.end.71
	    Predecessors according to CFG: BB#14 BB#17
3216B		%vreg758<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg758
3232B		%vreg757<def> = MOV32ri 1; GR32:%vreg757
3248B		%vreg766<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg766
3264B		%vreg764<def> = MOV32rm %vreg766, 1, %noreg, 24, %noreg; mem:LD4[%rNToGo72] GR32:%vreg764 GR64:%vreg766
3296B		%vreg764<def,tied1> = ADD32ri8 %vreg764<kill,tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg764
3312B		MOV32mr %vreg766<kill>, 1, %noreg, 24, %noreg, %vreg764<kill>; mem:ST4[%rNToGo72] GR64:%vreg766 GR32:%vreg764
3328B		%vreg760<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg760
3344B		CMP32mi8 %vreg760<kill>, 1, %noreg, 24, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%rNToGo74] GR64:%vreg760
3376B		%vreg758<def,tied1> = CMOVE32rr %vreg758<kill,tied0>, %vreg757<kill>, %EFLAGS<imp-use,kill>; GR32:%vreg758,%vreg757
3392B		%vreg752<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg752
3424B		%vreg752<def,tied1> = XOR32rr %vreg752<kill,tied0>, %vreg758<kill>, %EFLAGS<imp-def,dead>; GR32:%vreg752,%vreg758
3456B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg752:sub_8bit<kill>; mem:ST1[%k1] GR32:%vreg752
3472B		%vreg746<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg746
3488B		%vreg744<def> = MOV32rm %vreg746, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used80] GR32:%vreg744 GR64:%vreg746
3520B		%vreg744<def,tied1> = ADD32ri8 %vreg744<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg744
3536B		MOV32mr %vreg746<kill>, 1, %noreg, 1092, %noreg, %vreg744<kill>; mem:ST4[%nblock_used80] GR64:%vreg746 GR32:%vreg744
3552B		%vreg740<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg740
3568B		%vreg739<def> = MOV32rm %vreg740<kill>, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used82] GR32:%vreg739 GR64:%vreg740
3584B		%vreg737<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg737
3600B		%vreg734<def> = MOV32rm %vreg737<kill>, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock83] GR32:%vreg734 GR64:%vreg737
3632B		%vreg734<def,tied1> = ADD32ri8 %vreg734<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg734
3648B		CMP32rr %vreg739<kill>, %vreg734<kill>, %EFLAGS<imp-def>; GR32:%vreg739,%vreg734
3664B		JNE_1 <BB#20>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#20 BB#19
> %EAX<def> = MOV32r0 %EFLAGS<imp-def,dead>
> %ECX<def> = MOV32ri 1
> %RDX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ESI<def> = MOV32rm %RDX, 1, %noreg, 24, %noreg; mem:LD4[%rNToGo72]
> %ESI<def,tied1> = ADD32ri8 %ESI<kill,tied0>, -1, %EFLAGS<imp-def,dead>
> MOV32mr %RDX<kill>, 1, %noreg, 24, %noreg, %ESI<kill>; mem:ST4[%rNToGo72]
> %RDX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> CMP32mi8 %RDX<kill>, 1, %noreg, 24, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%rNToGo74]
> %EAX<def,tied1> = CMOVE32rr %EAX<kill,tied0>, %ECX<kill>, %EFLAGS<imp-use,kill>
> %ECX<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1]
> %ECX<def,tied1> = XOR32rr %ECX<kill,tied0>, %EAX<kill>, %EFLAGS<imp-def,dead>
> MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %CL, %ECX<imp-use,kill>; mem:ST1[%k1]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used80]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 1092, %noreg, %ECX<kill>; mem:ST4[%nblock_used80]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used82]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RCX<kill>, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock83]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> CMP32rr %EAX<kill>, %ECX<kill>, %EFLAGS<imp-def>
> JNE_1 <BB#20>, %EFLAGS<imp-use,kill>
3680B	BB#19: derived from LLVM BB %if.then.87
	    Predecessors according to CFG: BB#18
3696B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2
> JMP_1 <BB#2>
3712B	BB#20: derived from LLVM BB %if.end.88
	    Predecessors according to CFG: BB#18
3728B		%vreg772<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg772
3744B		%vreg770<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg770
3760B		CMP32rm %vreg772<kill>, %vreg770<kill>, 1, %noreg, 64, %noreg, %EFLAGS<imp-def>; mem:LD4[%k090] GR32:%vreg772 GR64:%vreg770
3776B		JE_1 <BB#22>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#22 BB#21
> %EAX<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> CMP32rm %EAX<kill>, %RCX<kill>, 1, %noreg, 64, %noreg, %EFLAGS<imp-def>; mem:LD4[%k090]
> JE_1 <BB#22>, %EFLAGS<imp-use,kill>
3792B	BB#21: derived from LLVM BB %if.then.93
	    Predecessors according to CFG: BB#20
3808B		%vreg1264<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg1264
3824B		%vreg1262<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1262
3840B		MOV32mr %vreg1262<kill>, 1, %noreg, 64, %noreg, %vreg1264<kill>; mem:ST4[%k095] GR64:%vreg1262 GR32:%vreg1264
3856B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2
> %EAX<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mr %RCX<kill>, 1, %noreg, 64, %noreg, %EAX<kill>; mem:ST4[%k095]
> JMP_1 <BB#2>
3872B	BB#22: derived from LLVM BB %if.end.96
	    Predecessors according to CFG: BB#20
3888B		%vreg837<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg837
3904B		MOV32mi %vreg837<kill>, 1, %noreg, 16, %noreg, 2; mem:ST4[%state_out_len97] GR64:%vreg837
3920B		%vreg835<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg835
3936B		%vreg834<def> = MOV32rm %vreg835<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos98] GR32:%vreg834 GR64:%vreg835
3952B		%vreg831<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg831
3984B		%vreg831<def,tied1> = ADD64ri32 %vreg831<kill,tied0>, 1096, %EFLAGS<imp-def,dead>; GR64:%vreg831
4000B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4016B		%EDI<def> = COPY %vreg834<kill>; GR32:%vreg834
4032B		%RSI<def> = COPY %vreg831<kill>; GR64:%vreg831
4048B		CALL64pcrel32 <ga:@BZ2_indexIntoF>, <regmask>, %RSP<imp-use>, %EDI<imp-use>, %RSI<imp-use>, %EAX<imp-def>
4064B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4080B		%vreg828<def> = COPY %EAX; GR32:%vreg828
4096B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4112B		STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
4128B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4160B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg828:sub_8bit<kill>; mem:ST1[%k1] GR32:%vreg828
4176B		%vreg822<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg822
4192B		%vreg820:sub_32bit<def,read-undef> = MOV32rm %vreg822<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos103] GR64_NOSP:%vreg820 GR64:%vreg822
4224B		%vreg817<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg817
4240B		%vreg816<def> = MOV64rm %vreg817<kill>, 1, %noreg, 3160, %noreg; mem:LD8[%ll16105] GR64:%vreg816,%vreg817
4256B		%vreg781<def> = MOVZX32rm16 %vreg816<kill>, 2, %vreg820<kill>, 0, %noreg; mem:LD2[%arrayidx106] GR32:%vreg781 GR64:%vreg816 GR64_NOSP:%vreg820
4272B		%vreg810<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg810
4288B		%vreg807<def> = MOV32rm %vreg810<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos108] GR32:%vreg807 GR64:%vreg810
4320B		%vreg807<def,tied1> = SHR32ri %vreg807<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg807
4336B		%vreg805:sub_32bit<def,read-undef> = MOV32rr %vreg807<kill>; GR64_NOSP:%vreg805 GR32:%vreg807
4368B		%vreg802<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg802
4384B		%vreg801<def> = MOV64rm %vreg802<kill>, 1, %noreg, 3168, %noreg; mem:LD8[%ll4111] GR64:%vreg801,%vreg802
4400B		%vreg785<def> = MOVZX32rm8 %vreg801<kill>, 1, %vreg805<kill>, 0, %noreg; mem:LD1[%arrayidx112] GR32:%vreg785 GR64:%vreg801 GR64_NOSP:%vreg805
4416B		%vreg795<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg795
4432B		%vreg790<def> = MOV32rm %vreg795<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos114] GR32:%vreg790 GR64:%vreg795
4464B		%vreg790<def,tied1> = SHL32ri %vreg790<kill,tied0>, 2, %EFLAGS<imp-def,dead>; GR32:%vreg790
4496B		%vreg790<def,tied1> = AND32ri8 %vreg790<kill,tied0>, 4, %EFLAGS<imp-def,dead>; GR32:%vreg790
4512B		%ECX<def> = COPY %vreg790<kill>; GR32:%vreg790
4528B		%CL<def> = KILL %ECX
4560B		%vreg785<def,tied1> = SHR32rCL %vreg785<kill,tied0>, %EFLAGS<imp-def,dead>, %CL<imp-use>; GR32:%vreg785
4592B		%vreg785<def,tied1> = AND32ri8 %vreg785<kill,tied0>, 15, %EFLAGS<imp-def,dead>; GR32:%vreg785
4624B		%vreg785<def,tied1> = SHL32ri %vreg785<kill,tied0>, 16, %EFLAGS<imp-def,dead>; GR32:%vreg785
4656B		%vreg781<def,tied1> = OR32rr %vreg781<kill,tied0>, %vreg785<kill>, %EFLAGS<imp-def,dead>; GR32:%vreg781,%vreg785
4672B		%vreg778<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg778
4688B		MOV32mr %vreg778<kill>, 1, %noreg, 60, %noreg, %vreg781<kill>; mem:ST4[%tPos121] GR64:%vreg778 GR32:%vreg781
4704B		%vreg775<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg775
4720B		CMP32mi8 %vreg775<kill>, 1, %noreg, 24, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%rNToGo122] GR64:%vreg775
4736B		JNE_1 <BB#26>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#26 BB#23
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 16, %noreg, 2; mem:ST4[%state_out_len97]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EDI<def> = MOV32rm %RAX<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos98]
> %RSI<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RSI<def,tied1> = ADD64ri32 %RSI<kill,tied0>, 1096, %EFLAGS<imp-def,dead>
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EDI<def> = COPY %EDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@BZ2_indexIntoF>, <regmask>, %RSP<imp-use>, %EDI<imp-use>, %RSI<imp-use>, %EAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def> = COPY %EAX
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %AL, %EAX<imp-use,kill>; mem:ST1[%k1]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 60, %noreg, %RAX<imp-def>; mem:LD4[%tPos103]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RCX<def> = MOV64rm %RCX<kill>, 1, %noreg, 3160, %noreg; mem:LD8[%ll16105]
> %EAX<def> = MOVZX32rm16 %RCX<kill>, 2, %RAX<kill>, 0, %noreg; mem:LD2[%arrayidx106]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RCX<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos108]
> %ECX<def,tied1> = SHR32ri %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> %ECX<def> = MOV32rr %ECX<kill>, %RCX<imp-def>
> %RDX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RDX<def> = MOV64rm %RDX<kill>, 1, %noreg, 3168, %noreg; mem:LD8[%ll4111]
> %EDX<def> = MOVZX32rm8 %RDX<kill>, 1, %RCX<kill>, 0, %noreg; mem:LD1[%arrayidx112]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RCX<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos114]
> %ECX<def,tied1> = SHL32ri %ECX<kill,tied0>, 2, %EFLAGS<imp-def,dead>
> %ECX<def,tied1> = AND32ri8 %ECX<kill,tied0>, 4, %EFLAGS<imp-def,dead>
> %ECX<def> = COPY %ECX<kill>
Deleting identity copy.
> %CL<def> = KILL %ECX
> %EDX<def,tied1> = SHR32rCL %EDX<kill,tied0>, %EFLAGS<imp-def,dead>, %CL<imp-use>
> %EDX<def,tied1> = AND32ri8 %EDX<kill,tied0>, 15, %EFLAGS<imp-def,dead>
> %EDX<def,tied1> = SHL32ri %EDX<kill,tied0>, 16, %EFLAGS<imp-def,dead>
> %EAX<def,tied1> = OR32rr %EAX<kill,tied0>, %EDX<kill>, %EFLAGS<imp-def,dead>
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mr %RCX<kill>, 1, %noreg, 60, %noreg, %EAX<kill>; mem:ST4[%tPos121]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> CMP32mi8 %RAX<kill>, 1, %noreg, 24, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%rNToGo122]
> JNE_1 <BB#26>, %EFLAGS<imp-use,kill>
4752B	BB#23: derived from LLVM BB %if.then.125
	    Predecessors according to CFG: BB#22
4768B		%vreg855<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg855
4784B		%vreg853<def> = MOVSX64rm32 %vreg855<kill>, 1, %noreg, 28, %noreg; mem:LD4[%rTPos126] GR64_NOSP:%vreg853 GR64:%vreg855
4800B		%vreg851<def> = MOV32rm %noreg, 4, %vreg853<kill>, <ga:@BZ2_rNums>, %noreg; mem:LD4[%arrayidx128] GR32:%vreg851 GR64_NOSP:%vreg853
4816B		%vreg849<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg849
4832B		MOV32mr %vreg849<kill>, 1, %noreg, 24, %noreg, %vreg851<kill>; mem:ST4[%rNToGo129] GR64:%vreg849 GR32:%vreg851
4848B		%vreg846<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg846
4864B		%vreg844<def> = MOV32rm %vreg846, 1, %noreg, 28, %noreg; mem:LD4[%rTPos130] GR32:%vreg844 GR64:%vreg846
4896B		%vreg844<def,tied1> = ADD32ri8 %vreg844<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg844
4912B		MOV32mr %vreg846<kill>, 1, %noreg, 28, %noreg, %vreg844<kill>; mem:ST4[%rTPos130] GR64:%vreg846 GR32:%vreg844
4928B		%vreg840<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg840
4944B		CMP32mi %vreg840<kill>, 1, %noreg, 28, %noreg, 512, %EFLAGS<imp-def>; mem:LD4[%rTPos132] GR64:%vreg840
4960B		JNE_1 <BB#25>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#25 BB#24
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RAX<def> = MOVSX64rm32 %RAX<kill>, 1, %noreg, 28, %noreg; mem:LD4[%rTPos126]
> %EAX<def> = MOV32rm %noreg, 4, %RAX<kill>, <ga:@BZ2_rNums>, %noreg; mem:LD4[%arrayidx128]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mr %RCX<kill>, 1, %noreg, 24, %noreg, %EAX<kill>; mem:ST4[%rNToGo129]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 28, %noreg; mem:LD4[%rTPos130]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 28, %noreg, %ECX<kill>; mem:ST4[%rTPos130]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> CMP32mi %RAX<kill>, 1, %noreg, 28, %noreg, 512, %EFLAGS<imp-def>; mem:LD4[%rTPos132]
> JNE_1 <BB#25>, %EFLAGS<imp-use,kill>
4976B	BB#24: derived from LLVM BB %if.then.135
	    Predecessors according to CFG: BB#23
4992B		%vreg857<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg857
5008B		MOV32mi %vreg857<kill>, 1, %noreg, 28, %noreg, 0; mem:ST4[%rTPos136] GR64:%vreg857
	    Successors according to CFG: BB#25
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 28, %noreg, 0; mem:ST4[%rTPos136]
5024B	BB#25: derived from LLVM BB %if.end.137
	    Predecessors according to CFG: BB#23 BB#24
5040B		JMP_1 <BB#26>
	    Successors according to CFG: BB#26
> JMP_1 <BB#26>
5056B	BB#26: derived from LLVM BB %if.end.138
	    Predecessors according to CFG: BB#22 BB#25
5072B		%vreg885<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg885
5088B		%vreg884<def> = MOV32ri 1; GR32:%vreg884
5104B		%vreg893<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg893
5120B		%vreg891<def> = MOV32rm %vreg893, 1, %noreg, 24, %noreg; mem:LD4[%rNToGo139] GR32:%vreg891 GR64:%vreg893
5152B		%vreg891<def,tied1> = ADD32ri8 %vreg891<kill,tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg891
5168B		MOV32mr %vreg893<kill>, 1, %noreg, 24, %noreg, %vreg891<kill>; mem:ST4[%rNToGo139] GR64:%vreg893 GR32:%vreg891
5184B		%vreg887<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg887
5200B		CMP32mi8 %vreg887<kill>, 1, %noreg, 24, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%rNToGo141] GR64:%vreg887
5232B		%vreg885<def,tied1> = CMOVE32rr %vreg885<kill,tied0>, %vreg884<kill>, %EFLAGS<imp-use,kill>; GR32:%vreg885,%vreg884
5248B		%vreg879<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg879
5280B		%vreg879<def,tied1> = XOR32rr %vreg879<kill,tied0>, %vreg885<kill>, %EFLAGS<imp-def,dead>; GR32:%vreg879,%vreg885
5312B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg879:sub_8bit<kill>; mem:ST1[%k1] GR32:%vreg879
5328B		%vreg873<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg873
5344B		%vreg871<def> = MOV32rm %vreg873, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used148] GR32:%vreg871 GR64:%vreg873
5376B		%vreg871<def,tied1> = ADD32ri8 %vreg871<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg871
5392B		MOV32mr %vreg873<kill>, 1, %noreg, 1092, %noreg, %vreg871<kill>; mem:ST4[%nblock_used148] GR64:%vreg873 GR32:%vreg871
5408B		%vreg867<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg867
5424B		%vreg866<def> = MOV32rm %vreg867<kill>, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used150] GR32:%vreg866 GR64:%vreg867
5440B		%vreg864<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg864
5456B		%vreg861<def> = MOV32rm %vreg864<kill>, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock151] GR32:%vreg861 GR64:%vreg864
5488B		%vreg861<def,tied1> = ADD32ri8 %vreg861<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg861
5504B		CMP32rr %vreg866<kill>, %vreg861<kill>, %EFLAGS<imp-def>; GR32:%vreg866,%vreg861
5520B		JNE_1 <BB#28>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#28 BB#27
> %EAX<def> = MOV32r0 %EFLAGS<imp-def,dead>
> %ECX<def> = MOV32ri 1
> %RDX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ESI<def> = MOV32rm %RDX, 1, %noreg, 24, %noreg; mem:LD4[%rNToGo139]
> %ESI<def,tied1> = ADD32ri8 %ESI<kill,tied0>, -1, %EFLAGS<imp-def,dead>
> MOV32mr %RDX<kill>, 1, %noreg, 24, %noreg, %ESI<kill>; mem:ST4[%rNToGo139]
> %RDX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> CMP32mi8 %RDX<kill>, 1, %noreg, 24, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%rNToGo141]
> %EAX<def,tied1> = CMOVE32rr %EAX<kill,tied0>, %ECX<kill>, %EFLAGS<imp-use,kill>
> %ECX<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1]
> %ECX<def,tied1> = XOR32rr %ECX<kill,tied0>, %EAX<kill>, %EFLAGS<imp-def,dead>
> MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %CL, %ECX<imp-use,kill>; mem:ST1[%k1]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used148]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 1092, %noreg, %ECX<kill>; mem:ST4[%nblock_used148]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used150]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RCX<kill>, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock151]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> CMP32rr %EAX<kill>, %ECX<kill>, %EFLAGS<imp-def>
> JNE_1 <BB#28>, %EFLAGS<imp-use,kill>
5536B	BB#27: derived from LLVM BB %if.then.155
	    Predecessors according to CFG: BB#26
5552B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2
> JMP_1 <BB#2>
5568B	BB#28: derived from LLVM BB %if.end.156
	    Predecessors according to CFG: BB#26
5584B		%vreg899<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg899
5600B		%vreg897<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg897
5616B		CMP32rm %vreg899<kill>, %vreg897<kill>, 1, %noreg, 64, %noreg, %EFLAGS<imp-def>; mem:LD4[%k0158] GR32:%vreg899 GR64:%vreg897
5632B		JE_1 <BB#30>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#30 BB#29
> %EAX<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> CMP32rm %EAX<kill>, %RCX<kill>, 1, %noreg, 64, %noreg, %EFLAGS<imp-def>; mem:LD4[%k0158]
> JE_1 <BB#30>, %EFLAGS<imp-use,kill>
5648B	BB#29: derived from LLVM BB %if.then.161
	    Predecessors according to CFG: BB#28
5664B		%vreg1259<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg1259
5680B		%vreg1257<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1257
5696B		MOV32mr %vreg1257<kill>, 1, %noreg, 64, %noreg, %vreg1259<kill>; mem:ST4[%k0163] GR64:%vreg1257 GR32:%vreg1259
5712B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2
> %EAX<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mr %RCX<kill>, 1, %noreg, 64, %noreg, %EAX<kill>; mem:ST4[%k0163]
> JMP_1 <BB#2>
5728B	BB#30: derived from LLVM BB %if.end.164
	    Predecessors according to CFG: BB#28
5744B		%vreg964<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg964
5760B		MOV32mi %vreg964<kill>, 1, %noreg, 16, %noreg, 3; mem:ST4[%state_out_len165] GR64:%vreg964
5776B		%vreg962<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg962
5792B		%vreg961<def> = MOV32rm %vreg962<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos166] GR32:%vreg961 GR64:%vreg962
5808B		%vreg958<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg958
5840B		%vreg958<def,tied1> = ADD64ri32 %vreg958<kill,tied0>, 1096, %EFLAGS<imp-def,dead>; GR64:%vreg958
5856B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5872B		%EDI<def> = COPY %vreg961<kill>; GR32:%vreg961
5888B		%RSI<def> = COPY %vreg958<kill>; GR64:%vreg958
5904B		CALL64pcrel32 <ga:@BZ2_indexIntoF>, <regmask>, %RSP<imp-use>, %EDI<imp-use>, %RSI<imp-use>, %EAX<imp-def>
5920B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5936B		%vreg955<def> = COPY %EAX; GR32:%vreg955
5952B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5968B		STACKMAP 3, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
5984B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
6016B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg955:sub_8bit<kill>; mem:ST1[%k1] GR32:%vreg955
6032B		%vreg949<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg949
6048B		%vreg947:sub_32bit<def,read-undef> = MOV32rm %vreg949<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos171] GR64_NOSP:%vreg947 GR64:%vreg949
6080B		%vreg944<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg944
6096B		%vreg943<def> = MOV64rm %vreg944<kill>, 1, %noreg, 3160, %noreg; mem:LD8[%ll16173] GR64:%vreg943,%vreg944
6112B		%vreg908<def> = MOVZX32rm16 %vreg943<kill>, 2, %vreg947<kill>, 0, %noreg; mem:LD2[%arrayidx174] GR32:%vreg908 GR64:%vreg943 GR64_NOSP:%vreg947
6128B		%vreg937<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg937
6144B		%vreg934<def> = MOV32rm %vreg937<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos176] GR32:%vreg934 GR64:%vreg937
6176B		%vreg934<def,tied1> = SHR32ri %vreg934<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg934
6192B		%vreg932:sub_32bit<def,read-undef> = MOV32rr %vreg934<kill>; GR64_NOSP:%vreg932 GR32:%vreg934
6224B		%vreg929<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg929
6240B		%vreg928<def> = MOV64rm %vreg929<kill>, 1, %noreg, 3168, %noreg; mem:LD8[%ll4179] GR64:%vreg928,%vreg929
6256B		%vreg912<def> = MOVZX32rm8 %vreg928<kill>, 1, %vreg932<kill>, 0, %noreg; mem:LD1[%arrayidx180] GR32:%vreg912 GR64:%vreg928 GR64_NOSP:%vreg932
6272B		%vreg922<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg922
6288B		%vreg917<def> = MOV32rm %vreg922<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos182] GR32:%vreg917 GR64:%vreg922
6320B		%vreg917<def,tied1> = SHL32ri %vreg917<kill,tied0>, 2, %EFLAGS<imp-def,dead>; GR32:%vreg917
6352B		%vreg917<def,tied1> = AND32ri8 %vreg917<kill,tied0>, 4, %EFLAGS<imp-def,dead>; GR32:%vreg917
6368B		%ECX<def> = COPY %vreg917<kill>; GR32:%vreg917
6384B		%CL<def> = KILL %ECX
6416B		%vreg912<def,tied1> = SHR32rCL %vreg912<kill,tied0>, %EFLAGS<imp-def,dead>, %CL<imp-use>; GR32:%vreg912
6448B		%vreg912<def,tied1> = AND32ri8 %vreg912<kill,tied0>, 15, %EFLAGS<imp-def,dead>; GR32:%vreg912
6480B		%vreg912<def,tied1> = SHL32ri %vreg912<kill,tied0>, 16, %EFLAGS<imp-def,dead>; GR32:%vreg912
6512B		%vreg908<def,tied1> = OR32rr %vreg908<kill,tied0>, %vreg912<kill>, %EFLAGS<imp-def,dead>; GR32:%vreg908,%vreg912
6528B		%vreg905<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg905
6544B		MOV32mr %vreg905<kill>, 1, %noreg, 60, %noreg, %vreg908<kill>; mem:ST4[%tPos189] GR64:%vreg905 GR32:%vreg908
6560B		%vreg902<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg902
6576B		CMP32mi8 %vreg902<kill>, 1, %noreg, 24, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%rNToGo190] GR64:%vreg902
6592B		JNE_1 <BB#34>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#34 BB#31
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 16, %noreg, 3; mem:ST4[%state_out_len165]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EDI<def> = MOV32rm %RAX<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos166]
> %RSI<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RSI<def,tied1> = ADD64ri32 %RSI<kill,tied0>, 1096, %EFLAGS<imp-def,dead>
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EDI<def> = COPY %EDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@BZ2_indexIntoF>, <regmask>, %RSP<imp-use>, %EDI<imp-use>, %RSI<imp-use>, %EAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def> = COPY %EAX
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 3, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %AL, %EAX<imp-use,kill>; mem:ST1[%k1]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 60, %noreg, %RAX<imp-def>; mem:LD4[%tPos171]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RCX<def> = MOV64rm %RCX<kill>, 1, %noreg, 3160, %noreg; mem:LD8[%ll16173]
> %EAX<def> = MOVZX32rm16 %RCX<kill>, 2, %RAX<kill>, 0, %noreg; mem:LD2[%arrayidx174]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RCX<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos176]
> %ECX<def,tied1> = SHR32ri %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> %ECX<def> = MOV32rr %ECX<kill>, %RCX<imp-def>
> %RDX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RDX<def> = MOV64rm %RDX<kill>, 1, %noreg, 3168, %noreg; mem:LD8[%ll4179]
> %EDX<def> = MOVZX32rm8 %RDX<kill>, 1, %RCX<kill>, 0, %noreg; mem:LD1[%arrayidx180]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RCX<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos182]
> %ECX<def,tied1> = SHL32ri %ECX<kill,tied0>, 2, %EFLAGS<imp-def,dead>
> %ECX<def,tied1> = AND32ri8 %ECX<kill,tied0>, 4, %EFLAGS<imp-def,dead>
> %ECX<def> = COPY %ECX<kill>
Deleting identity copy.
> %CL<def> = KILL %ECX
> %EDX<def,tied1> = SHR32rCL %EDX<kill,tied0>, %EFLAGS<imp-def,dead>, %CL<imp-use>
> %EDX<def,tied1> = AND32ri8 %EDX<kill,tied0>, 15, %EFLAGS<imp-def,dead>
> %EDX<def,tied1> = SHL32ri %EDX<kill,tied0>, 16, %EFLAGS<imp-def,dead>
> %EAX<def,tied1> = OR32rr %EAX<kill,tied0>, %EDX<kill>, %EFLAGS<imp-def,dead>
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mr %RCX<kill>, 1, %noreg, 60, %noreg, %EAX<kill>; mem:ST4[%tPos189]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> CMP32mi8 %RAX<kill>, 1, %noreg, 24, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%rNToGo190]
> JNE_1 <BB#34>, %EFLAGS<imp-use,kill>
6608B	BB#31: derived from LLVM BB %if.then.193
	    Predecessors according to CFG: BB#30
6624B		%vreg982<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg982
6640B		%vreg980<def> = MOVSX64rm32 %vreg982<kill>, 1, %noreg, 28, %noreg; mem:LD4[%rTPos194] GR64_NOSP:%vreg980 GR64:%vreg982
6656B		%vreg978<def> = MOV32rm %noreg, 4, %vreg980<kill>, <ga:@BZ2_rNums>, %noreg; mem:LD4[%arrayidx196] GR32:%vreg978 GR64_NOSP:%vreg980
6672B		%vreg976<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg976
6688B		MOV32mr %vreg976<kill>, 1, %noreg, 24, %noreg, %vreg978<kill>; mem:ST4[%rNToGo197] GR64:%vreg976 GR32:%vreg978
6704B		%vreg973<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg973
6720B		%vreg971<def> = MOV32rm %vreg973, 1, %noreg, 28, %noreg; mem:LD4[%rTPos198] GR32:%vreg971 GR64:%vreg973
6752B		%vreg971<def,tied1> = ADD32ri8 %vreg971<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg971
6768B		MOV32mr %vreg973<kill>, 1, %noreg, 28, %noreg, %vreg971<kill>; mem:ST4[%rTPos198] GR64:%vreg973 GR32:%vreg971
6784B		%vreg967<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg967
6800B		CMP32mi %vreg967<kill>, 1, %noreg, 28, %noreg, 512, %EFLAGS<imp-def>; mem:LD4[%rTPos200] GR64:%vreg967
6816B		JNE_1 <BB#33>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#33 BB#32
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RAX<def> = MOVSX64rm32 %RAX<kill>, 1, %noreg, 28, %noreg; mem:LD4[%rTPos194]
> %EAX<def> = MOV32rm %noreg, 4, %RAX<kill>, <ga:@BZ2_rNums>, %noreg; mem:LD4[%arrayidx196]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mr %RCX<kill>, 1, %noreg, 24, %noreg, %EAX<kill>; mem:ST4[%rNToGo197]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 28, %noreg; mem:LD4[%rTPos198]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 28, %noreg, %ECX<kill>; mem:ST4[%rTPos198]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> CMP32mi %RAX<kill>, 1, %noreg, 28, %noreg, 512, %EFLAGS<imp-def>; mem:LD4[%rTPos200]
> JNE_1 <BB#33>, %EFLAGS<imp-use,kill>
6832B	BB#32: derived from LLVM BB %if.then.203
	    Predecessors according to CFG: BB#31
6848B		%vreg984<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg984
6864B		MOV32mi %vreg984<kill>, 1, %noreg, 28, %noreg, 0; mem:ST4[%rTPos204] GR64:%vreg984
	    Successors according to CFG: BB#33
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 28, %noreg, 0; mem:ST4[%rTPos204]
6880B	BB#33: derived from LLVM BB %if.end.205
	    Predecessors according to CFG: BB#31 BB#32
6896B		JMP_1 <BB#34>
	    Successors according to CFG: BB#34
> JMP_1 <BB#34>
6912B	BB#34: derived from LLVM BB %if.end.206
	    Predecessors according to CFG: BB#30 BB#33
6928B		%vreg1012<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg1012
6944B		%vreg1011<def> = MOV32ri 1; GR32:%vreg1011
6960B		%vreg1020<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1020
6976B		%vreg1018<def> = MOV32rm %vreg1020, 1, %noreg, 24, %noreg; mem:LD4[%rNToGo207] GR32:%vreg1018 GR64:%vreg1020
7008B		%vreg1018<def,tied1> = ADD32ri8 %vreg1018<kill,tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg1018
7024B		MOV32mr %vreg1020<kill>, 1, %noreg, 24, %noreg, %vreg1018<kill>; mem:ST4[%rNToGo207] GR64:%vreg1020 GR32:%vreg1018
7040B		%vreg1014<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1014
7056B		CMP32mi8 %vreg1014<kill>, 1, %noreg, 24, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%rNToGo209] GR64:%vreg1014
7088B		%vreg1012<def,tied1> = CMOVE32rr %vreg1012<kill,tied0>, %vreg1011<kill>, %EFLAGS<imp-use,kill>; GR32:%vreg1012,%vreg1011
7104B		%vreg1006<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg1006
7136B		%vreg1006<def,tied1> = XOR32rr %vreg1006<kill,tied0>, %vreg1012<kill>, %EFLAGS<imp-def,dead>; GR32:%vreg1006,%vreg1012
7168B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg1006:sub_8bit<kill>; mem:ST1[%k1] GR32:%vreg1006
7184B		%vreg1000<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1000
7200B		%vreg998<def> = MOV32rm %vreg1000, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used216] GR32:%vreg998 GR64:%vreg1000
7232B		%vreg998<def,tied1> = ADD32ri8 %vreg998<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg998
7248B		MOV32mr %vreg1000<kill>, 1, %noreg, 1092, %noreg, %vreg998<kill>; mem:ST4[%nblock_used216] GR64:%vreg1000 GR32:%vreg998
7264B		%vreg994<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg994
7280B		%vreg993<def> = MOV32rm %vreg994<kill>, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used218] GR32:%vreg993 GR64:%vreg994
7296B		%vreg991<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg991
7312B		%vreg988<def> = MOV32rm %vreg991<kill>, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock219] GR32:%vreg988 GR64:%vreg991
7344B		%vreg988<def,tied1> = ADD32ri8 %vreg988<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg988
7360B		CMP32rr %vreg993<kill>, %vreg988<kill>, %EFLAGS<imp-def>; GR32:%vreg993,%vreg988
7376B		JNE_1 <BB#36>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#36 BB#35
> %EAX<def> = MOV32r0 %EFLAGS<imp-def,dead>
> %ECX<def> = MOV32ri 1
> %RDX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ESI<def> = MOV32rm %RDX, 1, %noreg, 24, %noreg; mem:LD4[%rNToGo207]
> %ESI<def,tied1> = ADD32ri8 %ESI<kill,tied0>, -1, %EFLAGS<imp-def,dead>
> MOV32mr %RDX<kill>, 1, %noreg, 24, %noreg, %ESI<kill>; mem:ST4[%rNToGo207]
> %RDX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> CMP32mi8 %RDX<kill>, 1, %noreg, 24, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%rNToGo209]
> %EAX<def,tied1> = CMOVE32rr %EAX<kill,tied0>, %ECX<kill>, %EFLAGS<imp-use,kill>
> %ECX<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1]
> %ECX<def,tied1> = XOR32rr %ECX<kill,tied0>, %EAX<kill>, %EFLAGS<imp-def,dead>
> MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %CL, %ECX<imp-use,kill>; mem:ST1[%k1]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used216]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 1092, %noreg, %ECX<kill>; mem:ST4[%nblock_used216]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used218]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RCX<kill>, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock219]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> CMP32rr %EAX<kill>, %ECX<kill>, %EFLAGS<imp-def>
> JNE_1 <BB#36>, %EFLAGS<imp-use,kill>
7392B	BB#35: derived from LLVM BB %if.then.223
	    Predecessors according to CFG: BB#34
7408B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2
> JMP_1 <BB#2>
7424B	BB#36: derived from LLVM BB %if.end.224
	    Predecessors according to CFG: BB#34
7440B		%vreg1026<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg1026
7456B		%vreg1024<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1024
7472B		CMP32rm %vreg1026<kill>, %vreg1024<kill>, 1, %noreg, 64, %noreg, %EFLAGS<imp-def>; mem:LD4[%k0226] GR32:%vreg1026 GR64:%vreg1024
7488B		JE_1 <BB#38>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#38 BB#37
> %EAX<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> CMP32rm %EAX<kill>, %RCX<kill>, 1, %noreg, 64, %noreg, %EFLAGS<imp-def>; mem:LD4[%k0226]
> JE_1 <BB#38>, %EFLAGS<imp-use,kill>
7504B	BB#37: derived from LLVM BB %if.then.229
	    Predecessors according to CFG: BB#36
7520B		%vreg1254<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg1254
7536B		%vreg1252<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1252
7552B		MOV32mr %vreg1252<kill>, 1, %noreg, 64, %noreg, %vreg1254<kill>; mem:ST4[%k0231] GR64:%vreg1252 GR32:%vreg1254
7568B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2
> %EAX<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mr %RCX<kill>, 1, %noreg, 64, %noreg, %EAX<kill>; mem:ST4[%k0231]
> JMP_1 <BB#2>
7584B	BB#38: derived from LLVM BB %if.end.232
	    Predecessors according to CFG: BB#36
7600B		%vreg1089<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1089
7616B		%vreg1088<def> = MOV32rm %vreg1089<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos233] GR32:%vreg1088 GR64:%vreg1089
7632B		%vreg1085<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1085
7664B		%vreg1085<def,tied1> = ADD64ri32 %vreg1085<kill,tied0>, 1096, %EFLAGS<imp-def,dead>; GR64:%vreg1085
7680B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
7696B		%EDI<def> = COPY %vreg1088<kill>; GR32:%vreg1088
7712B		%RSI<def> = COPY %vreg1085<kill>; GR64:%vreg1085
7728B		CALL64pcrel32 <ga:@BZ2_indexIntoF>, <regmask>, %RSP<imp-use>, %EDI<imp-use>, %RSI<imp-use>, %EAX<imp-def>
7744B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
7760B		%vreg1082<def> = COPY %EAX; GR32:%vreg1082
7776B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
7792B		STACKMAP 4, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
7808B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
7840B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg1082:sub_8bit<kill>; mem:ST1[%k1] GR32:%vreg1082
7856B		%vreg1076<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1076
7872B		%vreg1074:sub_32bit<def,read-undef> = MOV32rm %vreg1076<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos238] GR64_NOSP:%vreg1074 GR64:%vreg1076
7904B		%vreg1071<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1071
7920B		%vreg1070<def> = MOV64rm %vreg1071<kill>, 1, %noreg, 3160, %noreg; mem:LD8[%ll16240] GR64:%vreg1070,%vreg1071
7936B		%vreg1035<def> = MOVZX32rm16 %vreg1070<kill>, 2, %vreg1074<kill>, 0, %noreg; mem:LD2[%arrayidx241] GR32:%vreg1035 GR64:%vreg1070 GR64_NOSP:%vreg1074
7952B		%vreg1064<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1064
7968B		%vreg1061<def> = MOV32rm %vreg1064<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos243] GR32:%vreg1061 GR64:%vreg1064
8000B		%vreg1061<def,tied1> = SHR32ri %vreg1061<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg1061
8016B		%vreg1059:sub_32bit<def,read-undef> = MOV32rr %vreg1061<kill>; GR64_NOSP:%vreg1059 GR32:%vreg1061
8048B		%vreg1056<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1056
8064B		%vreg1055<def> = MOV64rm %vreg1056<kill>, 1, %noreg, 3168, %noreg; mem:LD8[%ll4246] GR64:%vreg1055,%vreg1056
8080B		%vreg1039<def> = MOVZX32rm8 %vreg1055<kill>, 1, %vreg1059<kill>, 0, %noreg; mem:LD1[%arrayidx247] GR32:%vreg1039 GR64:%vreg1055 GR64_NOSP:%vreg1059
8096B		%vreg1049<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1049
8112B		%vreg1044<def> = MOV32rm %vreg1049<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos249] GR32:%vreg1044 GR64:%vreg1049
8144B		%vreg1044<def,tied1> = SHL32ri %vreg1044<kill,tied0>, 2, %EFLAGS<imp-def,dead>; GR32:%vreg1044
8176B		%vreg1044<def,tied1> = AND32ri8 %vreg1044<kill,tied0>, 4, %EFLAGS<imp-def,dead>; GR32:%vreg1044
8192B		%ECX<def> = COPY %vreg1044<kill>; GR32:%vreg1044
8208B		%CL<def> = KILL %ECX
8240B		%vreg1039<def,tied1> = SHR32rCL %vreg1039<kill,tied0>, %EFLAGS<imp-def,dead>, %CL<imp-use>; GR32:%vreg1039
8272B		%vreg1039<def,tied1> = AND32ri8 %vreg1039<kill,tied0>, 15, %EFLAGS<imp-def,dead>; GR32:%vreg1039
8304B		%vreg1039<def,tied1> = SHL32ri %vreg1039<kill,tied0>, 16, %EFLAGS<imp-def,dead>; GR32:%vreg1039
8336B		%vreg1035<def,tied1> = OR32rr %vreg1035<kill,tied0>, %vreg1039<kill>, %EFLAGS<imp-def,dead>; GR32:%vreg1035,%vreg1039
8352B		%vreg1032<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1032
8368B		MOV32mr %vreg1032<kill>, 1, %noreg, 60, %noreg, %vreg1035<kill>; mem:ST4[%tPos256] GR64:%vreg1032 GR32:%vreg1035
8384B		%vreg1029<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1029
8400B		CMP32mi8 %vreg1029<kill>, 1, %noreg, 24, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%rNToGo257] GR64:%vreg1029
8416B		JNE_1 <BB#42>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#42 BB#39
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EDI<def> = MOV32rm %RAX<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos233]
> %RSI<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RSI<def,tied1> = ADD64ri32 %RSI<kill,tied0>, 1096, %EFLAGS<imp-def,dead>
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EDI<def> = COPY %EDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@BZ2_indexIntoF>, <regmask>, %RSP<imp-use>, %EDI<imp-use>, %RSI<imp-use>, %EAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def> = COPY %EAX
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 4, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %AL, %EAX<imp-use,kill>; mem:ST1[%k1]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 60, %noreg, %RAX<imp-def>; mem:LD4[%tPos238]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RCX<def> = MOV64rm %RCX<kill>, 1, %noreg, 3160, %noreg; mem:LD8[%ll16240]
> %EAX<def> = MOVZX32rm16 %RCX<kill>, 2, %RAX<kill>, 0, %noreg; mem:LD2[%arrayidx241]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RCX<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos243]
> %ECX<def,tied1> = SHR32ri %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> %ECX<def> = MOV32rr %ECX<kill>, %RCX<imp-def>
> %RDX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RDX<def> = MOV64rm %RDX<kill>, 1, %noreg, 3168, %noreg; mem:LD8[%ll4246]
> %EDX<def> = MOVZX32rm8 %RDX<kill>, 1, %RCX<kill>, 0, %noreg; mem:LD1[%arrayidx247]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RCX<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos249]
> %ECX<def,tied1> = SHL32ri %ECX<kill,tied0>, 2, %EFLAGS<imp-def,dead>
> %ECX<def,tied1> = AND32ri8 %ECX<kill,tied0>, 4, %EFLAGS<imp-def,dead>
> %ECX<def> = COPY %ECX<kill>
Deleting identity copy.
> %CL<def> = KILL %ECX
> %EDX<def,tied1> = SHR32rCL %EDX<kill,tied0>, %EFLAGS<imp-def,dead>, %CL<imp-use>
> %EDX<def,tied1> = AND32ri8 %EDX<kill,tied0>, 15, %EFLAGS<imp-def,dead>
> %EDX<def,tied1> = SHL32ri %EDX<kill,tied0>, 16, %EFLAGS<imp-def,dead>
> %EAX<def,tied1> = OR32rr %EAX<kill,tied0>, %EDX<kill>, %EFLAGS<imp-def,dead>
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mr %RCX<kill>, 1, %noreg, 60, %noreg, %EAX<kill>; mem:ST4[%tPos256]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> CMP32mi8 %RAX<kill>, 1, %noreg, 24, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%rNToGo257]
> JNE_1 <BB#42>, %EFLAGS<imp-use,kill>
8432B	BB#39: derived from LLVM BB %if.then.260
	    Predecessors according to CFG: BB#38
8448B		%vreg1107<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1107
8464B		%vreg1105<def> = MOVSX64rm32 %vreg1107<kill>, 1, %noreg, 28, %noreg; mem:LD4[%rTPos261] GR64_NOSP:%vreg1105 GR64:%vreg1107
8480B		%vreg1103<def> = MOV32rm %noreg, 4, %vreg1105<kill>, <ga:@BZ2_rNums>, %noreg; mem:LD4[%arrayidx263] GR32:%vreg1103 GR64_NOSP:%vreg1105
8496B		%vreg1101<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1101
8512B		MOV32mr %vreg1101<kill>, 1, %noreg, 24, %noreg, %vreg1103<kill>; mem:ST4[%rNToGo264] GR64:%vreg1101 GR32:%vreg1103
8528B		%vreg1098<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1098
8544B		%vreg1096<def> = MOV32rm %vreg1098, 1, %noreg, 28, %noreg; mem:LD4[%rTPos265] GR32:%vreg1096 GR64:%vreg1098
8576B		%vreg1096<def,tied1> = ADD32ri8 %vreg1096<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg1096
8592B		MOV32mr %vreg1098<kill>, 1, %noreg, 28, %noreg, %vreg1096<kill>; mem:ST4[%rTPos265] GR64:%vreg1098 GR32:%vreg1096
8608B		%vreg1092<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1092
8624B		CMP32mi %vreg1092<kill>, 1, %noreg, 28, %noreg, 512, %EFLAGS<imp-def>; mem:LD4[%rTPos267] GR64:%vreg1092
8640B		JNE_1 <BB#41>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#41 BB#40
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RAX<def> = MOVSX64rm32 %RAX<kill>, 1, %noreg, 28, %noreg; mem:LD4[%rTPos261]
> %EAX<def> = MOV32rm %noreg, 4, %RAX<kill>, <ga:@BZ2_rNums>, %noreg; mem:LD4[%arrayidx263]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mr %RCX<kill>, 1, %noreg, 24, %noreg, %EAX<kill>; mem:ST4[%rNToGo264]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 28, %noreg; mem:LD4[%rTPos265]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 28, %noreg, %ECX<kill>; mem:ST4[%rTPos265]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> CMP32mi %RAX<kill>, 1, %noreg, 28, %noreg, 512, %EFLAGS<imp-def>; mem:LD4[%rTPos267]
> JNE_1 <BB#41>, %EFLAGS<imp-use,kill>
8656B	BB#40: derived from LLVM BB %if.then.270
	    Predecessors according to CFG: BB#39
8672B		%vreg1109<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1109
8688B		MOV32mi %vreg1109<kill>, 1, %noreg, 28, %noreg, 0; mem:ST4[%rTPos271] GR64:%vreg1109
	    Successors according to CFG: BB#41
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 28, %noreg, 0; mem:ST4[%rTPos271]
8704B	BB#41: derived from LLVM BB %if.end.272
	    Predecessors according to CFG: BB#39 BB#40
8720B		JMP_1 <BB#42>
	    Successors according to CFG: BB#42
> JMP_1 <BB#42>
8736B	BB#42: derived from LLVM BB %if.end.273
	    Predecessors according to CFG: BB#38 BB#41
8752B		%vreg1197<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg1197
8768B		%vreg1196<def> = MOV32ri 1; GR32:%vreg1196
8784B		%vreg1205<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1205
8800B		%vreg1203<def> = MOV32rm %vreg1205, 1, %noreg, 24, %noreg; mem:LD4[%rNToGo274] GR32:%vreg1203 GR64:%vreg1205
8832B		%vreg1203<def,tied1> = ADD32ri8 %vreg1203<kill,tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg1203
8848B		MOV32mr %vreg1205<kill>, 1, %noreg, 24, %noreg, %vreg1203<kill>; mem:ST4[%rNToGo274] GR64:%vreg1205 GR32:%vreg1203
8864B		%vreg1199<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1199
8880B		CMP32mi8 %vreg1199<kill>, 1, %noreg, 24, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%rNToGo276] GR64:%vreg1199
8912B		%vreg1197<def,tied1> = CMOVE32rr %vreg1197<kill,tied0>, %vreg1196<kill>, %EFLAGS<imp-use,kill>; GR32:%vreg1197,%vreg1196
8928B		%vreg1191<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg1191
8960B		%vreg1191<def,tied1> = XOR32rr %vreg1191<kill,tied0>, %vreg1197<kill>, %EFLAGS<imp-def,dead>; GR32:%vreg1191,%vreg1197
8992B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg1191:sub_8bit<kill>; mem:ST1[%k1] GR32:%vreg1191
9008B		%vreg1185<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1185
9024B		%vreg1183<def> = MOV32rm %vreg1185, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used283] GR32:%vreg1183 GR64:%vreg1185
9056B		%vreg1183<def,tied1> = ADD32ri8 %vreg1183<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg1183
9072B		MOV32mr %vreg1185<kill>, 1, %noreg, 1092, %noreg, %vreg1183<kill>; mem:ST4[%nblock_used283] GR64:%vreg1185 GR32:%vreg1183
9088B		%vreg1177<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg1177
9120B		%vreg1177<def,tied1> = ADD32ri8 %vreg1177<kill,tied0>, 4, %EFLAGS<imp-def,dead>; GR32:%vreg1177
9136B		%vreg1175<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1175
9152B		MOV32mr %vreg1175<kill>, 1, %noreg, 16, %noreg, %vreg1177<kill>; mem:ST4[%state_out_len287] GR64:%vreg1175 GR32:%vreg1177
9168B		%vreg1172<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1172
9184B		%vreg1171<def> = MOV32rm %vreg1172<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos288] GR32:%vreg1171 GR64:%vreg1172
9200B		%vreg1168<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1168
9232B		%vreg1168<def,tied1> = ADD64ri32 %vreg1168<kill,tied0>, 1096, %EFLAGS<imp-def,dead>; GR64:%vreg1168
9248B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
9264B		%EDI<def> = COPY %vreg1171<kill>; GR32:%vreg1171
9280B		%RSI<def> = COPY %vreg1168<kill>; GR64:%vreg1168
9296B		CALL64pcrel32 <ga:@BZ2_indexIntoF>, <regmask>, %RSP<imp-use>, %EDI<imp-use>, %RSI<imp-use>, %EAX<imp-def>
9312B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
9328B		%vreg1165<def> = COPY %EAX; GR32:%vreg1165
9344B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
9360B		STACKMAP 5, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
9376B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
9392B		%vreg1162<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1162
9408B		MOV32mr %vreg1162<kill>, 1, %noreg, 64, %noreg, %vreg1165<kill>; mem:ST4[%k0292] GR64:%vreg1162 GR32:%vreg1165
9424B		%vreg1159<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1159
9440B		%vreg1157:sub_32bit<def,read-undef> = MOV32rm %vreg1159<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos293] GR64_NOSP:%vreg1157 GR64:%vreg1159
9472B		%vreg1154<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1154
9488B		%vreg1153<def> = MOV64rm %vreg1154<kill>, 1, %noreg, 3160, %noreg; mem:LD8[%ll16295] GR64:%vreg1153,%vreg1154
9504B		%vreg1118<def> = MOVZX32rm16 %vreg1153<kill>, 2, %vreg1157<kill>, 0, %noreg; mem:LD2[%arrayidx296] GR32:%vreg1118 GR64:%vreg1153 GR64_NOSP:%vreg1157
9520B		%vreg1147<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1147
9536B		%vreg1144<def> = MOV32rm %vreg1147<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos298] GR32:%vreg1144 GR64:%vreg1147
9568B		%vreg1144<def,tied1> = SHR32ri %vreg1144<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg1144
9584B		%vreg1142:sub_32bit<def,read-undef> = MOV32rr %vreg1144<kill>; GR64_NOSP:%vreg1142 GR32:%vreg1144
9616B		%vreg1139<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1139
9632B		%vreg1138<def> = MOV64rm %vreg1139<kill>, 1, %noreg, 3168, %noreg; mem:LD8[%ll4301] GR64:%vreg1138,%vreg1139
9648B		%vreg1122<def> = MOVZX32rm8 %vreg1138<kill>, 1, %vreg1142<kill>, 0, %noreg; mem:LD1[%arrayidx302] GR32:%vreg1122 GR64:%vreg1138 GR64_NOSP:%vreg1142
9664B		%vreg1132<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1132
9680B		%vreg1127<def> = MOV32rm %vreg1132<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos304] GR32:%vreg1127 GR64:%vreg1132
9712B		%vreg1127<def,tied1> = SHL32ri %vreg1127<kill,tied0>, 2, %EFLAGS<imp-def,dead>; GR32:%vreg1127
9744B		%vreg1127<def,tied1> = AND32ri8 %vreg1127<kill,tied0>, 4, %EFLAGS<imp-def,dead>; GR32:%vreg1127
9760B		%ECX<def> = COPY %vreg1127<kill>; GR32:%vreg1127
9776B		%CL<def> = KILL %ECX
9808B		%vreg1122<def,tied1> = SHR32rCL %vreg1122<kill,tied0>, %EFLAGS<imp-def,dead>, %CL<imp-use>; GR32:%vreg1122
9840B		%vreg1122<def,tied1> = AND32ri8 %vreg1122<kill,tied0>, 15, %EFLAGS<imp-def,dead>; GR32:%vreg1122
9872B		%vreg1122<def,tied1> = SHL32ri %vreg1122<kill,tied0>, 16, %EFLAGS<imp-def,dead>; GR32:%vreg1122
9904B		%vreg1118<def,tied1> = OR32rr %vreg1118<kill,tied0>, %vreg1122<kill>, %EFLAGS<imp-def,dead>; GR32:%vreg1118,%vreg1122
9920B		%vreg1115<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1115
9936B		MOV32mr %vreg1115<kill>, 1, %noreg, 60, %noreg, %vreg1118<kill>; mem:ST4[%tPos311] GR64:%vreg1115 GR32:%vreg1118
9952B		%vreg1112<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1112
9968B		CMP32mi8 %vreg1112<kill>, 1, %noreg, 24, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%rNToGo312] GR64:%vreg1112
9984B		JNE_1 <BB#46>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#46 BB#43
> %EAX<def> = MOV32r0 %EFLAGS<imp-def,dead>
> %ECX<def> = MOV32ri 1
> %RDX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ESI<def> = MOV32rm %RDX, 1, %noreg, 24, %noreg; mem:LD4[%rNToGo274]
> %ESI<def,tied1> = ADD32ri8 %ESI<kill,tied0>, -1, %EFLAGS<imp-def,dead>
> MOV32mr %RDX<kill>, 1, %noreg, 24, %noreg, %ESI<kill>; mem:ST4[%rNToGo274]
> %RDX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> CMP32mi8 %RDX<kill>, 1, %noreg, 24, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%rNToGo276]
> %EAX<def,tied1> = CMOVE32rr %EAX<kill,tied0>, %ECX<kill>, %EFLAGS<imp-use,kill>
> %ECX<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1]
> %ECX<def,tied1> = XOR32rr %ECX<kill,tied0>, %EAX<kill>, %EFLAGS<imp-def,dead>
> MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %CL, %ECX<imp-use,kill>; mem:ST1[%k1]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used283]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 1092, %noreg, %ECX<kill>; mem:ST4[%nblock_used283]
> %EAX<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1]
> %EAX<def,tied1> = ADD32ri8 %EAX<kill,tied0>, 4, %EFLAGS<imp-def,dead>
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mr %RCX<kill>, 1, %noreg, 16, %noreg, %EAX<kill>; mem:ST4[%state_out_len287]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EDI<def> = MOV32rm %RAX<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos288]
> %RSI<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RSI<def,tied1> = ADD64ri32 %RSI<kill,tied0>, 1096, %EFLAGS<imp-def,dead>
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EDI<def> = COPY %EDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@BZ2_indexIntoF>, <regmask>, %RSP<imp-use>, %EDI<imp-use>, %RSI<imp-use>, %EAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def> = COPY %EAX
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 5, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mr %RCX<kill>, 1, %noreg, 64, %noreg, %EAX<kill>; mem:ST4[%k0292]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 60, %noreg, %RAX<imp-def>; mem:LD4[%tPos293]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RCX<def> = MOV64rm %RCX<kill>, 1, %noreg, 3160, %noreg; mem:LD8[%ll16295]
> %EAX<def> = MOVZX32rm16 %RCX<kill>, 2, %RAX<kill>, 0, %noreg; mem:LD2[%arrayidx296]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RCX<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos298]
> %ECX<def,tied1> = SHR32ri %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> %ECX<def> = MOV32rr %ECX<kill>, %RCX<imp-def>
> %RDX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RDX<def> = MOV64rm %RDX<kill>, 1, %noreg, 3168, %noreg; mem:LD8[%ll4301]
> %EDX<def> = MOVZX32rm8 %RDX<kill>, 1, %RCX<kill>, 0, %noreg; mem:LD1[%arrayidx302]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RCX<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos304]
> %ECX<def,tied1> = SHL32ri %ECX<kill,tied0>, 2, %EFLAGS<imp-def,dead>
> %ECX<def,tied1> = AND32ri8 %ECX<kill,tied0>, 4, %EFLAGS<imp-def,dead>
> %ECX<def> = COPY %ECX<kill>
Deleting identity copy.
> %CL<def> = KILL %ECX
> %EDX<def,tied1> = SHR32rCL %EDX<kill,tied0>, %EFLAGS<imp-def,dead>, %CL<imp-use>
> %EDX<def,tied1> = AND32ri8 %EDX<kill,tied0>, 15, %EFLAGS<imp-def,dead>
> %EDX<def,tied1> = SHL32ri %EDX<kill,tied0>, 16, %EFLAGS<imp-def,dead>
> %EAX<def,tied1> = OR32rr %EAX<kill,tied0>, %EDX<kill>, %EFLAGS<imp-def,dead>
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mr %RCX<kill>, 1, %noreg, 60, %noreg, %EAX<kill>; mem:ST4[%tPos311]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> CMP32mi8 %RAX<kill>, 1, %noreg, 24, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%rNToGo312]
> JNE_1 <BB#46>, %EFLAGS<imp-use,kill>
10000B	BB#43: derived from LLVM BB %if.then.315
	    Predecessors according to CFG: BB#42
10016B		%vreg1223<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1223
10032B		%vreg1221<def> = MOVSX64rm32 %vreg1223<kill>, 1, %noreg, 28, %noreg; mem:LD4[%rTPos316] GR64_NOSP:%vreg1221 GR64:%vreg1223
10048B		%vreg1219<def> = MOV32rm %noreg, 4, %vreg1221<kill>, <ga:@BZ2_rNums>, %noreg; mem:LD4[%arrayidx318] GR32:%vreg1219 GR64_NOSP:%vreg1221
10064B		%vreg1217<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1217
10080B		MOV32mr %vreg1217<kill>, 1, %noreg, 24, %noreg, %vreg1219<kill>; mem:ST4[%rNToGo319] GR64:%vreg1217 GR32:%vreg1219
10096B		%vreg1214<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1214
10112B		%vreg1212<def> = MOV32rm %vreg1214, 1, %noreg, 28, %noreg; mem:LD4[%rTPos320] GR32:%vreg1212 GR64:%vreg1214
10144B		%vreg1212<def,tied1> = ADD32ri8 %vreg1212<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg1212
10160B		MOV32mr %vreg1214<kill>, 1, %noreg, 28, %noreg, %vreg1212<kill>; mem:ST4[%rTPos320] GR64:%vreg1214 GR32:%vreg1212
10176B		%vreg1208<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1208
10192B		CMP32mi %vreg1208<kill>, 1, %noreg, 28, %noreg, 512, %EFLAGS<imp-def>; mem:LD4[%rTPos322] GR64:%vreg1208
10208B		JNE_1 <BB#45>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#45 BB#44
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RAX<def> = MOVSX64rm32 %RAX<kill>, 1, %noreg, 28, %noreg; mem:LD4[%rTPos316]
> %EAX<def> = MOV32rm %noreg, 4, %RAX<kill>, <ga:@BZ2_rNums>, %noreg; mem:LD4[%arrayidx318]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mr %RCX<kill>, 1, %noreg, 24, %noreg, %EAX<kill>; mem:ST4[%rNToGo319]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 28, %noreg; mem:LD4[%rTPos320]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 28, %noreg, %ECX<kill>; mem:ST4[%rTPos320]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> CMP32mi %RAX<kill>, 1, %noreg, 28, %noreg, 512, %EFLAGS<imp-def>; mem:LD4[%rTPos322]
> JNE_1 <BB#45>, %EFLAGS<imp-use,kill>
10224B	BB#44: derived from LLVM BB %if.then.325
	    Predecessors according to CFG: BB#43
10240B		%vreg1225<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1225
10256B		MOV32mi %vreg1225<kill>, 1, %noreg, 28, %noreg, 0; mem:ST4[%rTPos326] GR64:%vreg1225
	    Successors according to CFG: BB#45
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 28, %noreg, 0; mem:ST4[%rTPos326]
10272B	BB#45: derived from LLVM BB %if.end.327
	    Predecessors according to CFG: BB#43 BB#44
10288B		JMP_1 <BB#46>
	    Successors according to CFG: BB#46
> JMP_1 <BB#46>
10304B	BB#46: derived from LLVM BB %if.end.328
	    Predecessors according to CFG: BB#42 BB#45
10320B		%vreg1236<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg1236
10336B		%vreg1240<def> = MOV32ri 1; GR32:%vreg1240
10352B		%vreg1249<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1249
10368B		%vreg1247<def> = MOV32rm %vreg1249, 1, %noreg, 24, %noreg; mem:LD4[%rNToGo329] GR32:%vreg1247 GR64:%vreg1249
10400B		%vreg1247<def,tied1> = ADD32ri8 %vreg1247<kill,tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg1247
10416B		MOV32mr %vreg1249<kill>, 1, %noreg, 24, %noreg, %vreg1247<kill>; mem:ST4[%rNToGo329] GR64:%vreg1249 GR32:%vreg1247
10432B		%vreg1243<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1243
10448B		CMP32mi8 %vreg1243<kill>, 1, %noreg, 24, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%rNToGo331] GR64:%vreg1243
10480B		%vreg1236<def,tied1> = CMOVE32rr %vreg1236<kill,tied0>, %vreg1240<kill>, %EFLAGS<imp-use,kill>; GR32:%vreg1236,%vreg1240
10496B		%vreg1237<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1237
10528B		%vreg1236<def,tied1> = XOR32rm %vreg1236<kill,tied0>, %vreg1237, 1, %noreg, 64, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%k0335] GR32:%vreg1236 GR64:%vreg1237
10544B		MOV32mr %vreg1237<kill>, 1, %noreg, 64, %noreg, %vreg1236<kill>; mem:ST4[%k0335] GR64:%vreg1237 GR32:%vreg1236
10560B		%vreg1231<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg1231
10576B		%vreg1229<def> = MOV32rm %vreg1231, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used337] GR32:%vreg1229 GR64:%vreg1231
10608B		%vreg1229<def,tied1> = ADD32ri8 %vreg1229<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg1229
10624B		MOV32mr %vreg1231<kill>, 1, %noreg, 1092, %noreg, %vreg1229<kill>; mem:ST4[%nblock_used337] GR64:%vreg1231 GR32:%vreg1229
10640B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2
> %EAX<def> = MOV32r0 %EFLAGS<imp-def,dead>
> %ECX<def> = MOV32ri 1
> %RDX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ESI<def> = MOV32rm %RDX, 1, %noreg, 24, %noreg; mem:LD4[%rNToGo329]
> %ESI<def,tied1> = ADD32ri8 %ESI<kill,tied0>, -1, %EFLAGS<imp-def,dead>
> MOV32mr %RDX<kill>, 1, %noreg, 24, %noreg, %ESI<kill>; mem:ST4[%rNToGo329]
> %RDX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> CMP32mi8 %RDX<kill>, 1, %noreg, 24, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%rNToGo331]
> %EAX<def,tied1> = CMOVE32rr %EAX<kill,tied0>, %ECX<kill>, %EFLAGS<imp-use,kill>
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EAX<def,tied1> = XOR32rm %EAX<kill,tied0>, %RCX, 1, %noreg, 64, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%k0335]
> MOV32mr %RCX<kill>, 1, %noreg, 64, %noreg, %EAX<kill>; mem:ST4[%k0335]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used337]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 1092, %noreg, %ECX<kill>; mem:ST4[%nblock_used337]
> JMP_1 <BB#2>
10656B	BB#47: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#0
10672B		JMP_1 <BB#48>
	    Successors according to CFG: BB#48
> JMP_1 <BB#48>
10688B	BB#48: derived from LLVM BB %while.body.339
	    Predecessors according to CFG: BB#47 BB#72 BB#71 BB#69 BB#67 BB#65 BB#63 BB#61
10704B		JMP_1 <BB#49>
	    Successors according to CFG: BB#49
> JMP_1 <BB#49>
10720B	BB#49: derived from LLVM BB %while.body.341
	    Predecessors according to CFG: BB#48 BB#55
10736B		%vreg12<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg12
10752B		%vreg11<def> = MOV64rm %vreg12<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm342] GR64:%vreg11,%vreg12
10768B		CMP32mi8 %vreg11<kill>, 1, %noreg, 32, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_out343] GR64:%vreg11
10784B		JNE_1 <BB#51>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#51 BB#50
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm342]
> CMP32mi8 %RAX<kill>, 1, %noreg, 32, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_out343]
> JNE_1 <BB#51>, %EFLAGS<imp-use,kill>
10800B	BB#50: derived from LLVM BB %if.then.346
	    Predecessors according to CFG: BB#49
10816B		MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST1[%retval]
10832B		JMP_1 <BB#73>
	    Successors according to CFG: BB#73
> MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST1[%retval]
> JMP_1 <BB#73>
10848B	BB#51: derived from LLVM BB %if.end.347
	    Predecessors according to CFG: BB#49
10864B		%vreg15<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg15
10880B		CMP32mi8 %vreg15<kill>, 1, %noreg, 16, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%state_out_len348] GR64:%vreg15
10896B		JNE_1 <BB#53>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#53 BB#52
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> CMP32mi8 %RAX<kill>, 1, %noreg, 16, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%state_out_len348]
> JNE_1 <BB#53>, %EFLAGS<imp-use,kill>
10912B	BB#52: derived from LLVM BB %if.then.351
	    Predecessors according to CFG: BB#51
10928B		JMP_1 <BB#56>
	    Successors according to CFG: BB#56
> JMP_1 <BB#56>
10944B	BB#53: derived from LLVM BB %if.end.352
	    Predecessors according to CFG: BB#51
10960B		%vreg87<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg87
10976B		%vreg86<def> = MOV8rm %vreg87<kill>, 1, %noreg, 12, %noreg; mem:LD1[%state_out_ch353] GR8:%vreg86 GR64:%vreg87
10992B		%vreg84<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg84
11008B		%vreg83<def> = MOV64rm %vreg84<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm354] GR64:%vreg83,%vreg84
11024B		%vreg81<def> = MOV64rm %vreg83<kill>, 1, %noreg, 24, %noreg; mem:LD8[%next_out355] GR64:%vreg81,%vreg83
11040B		MOV8mr %vreg81<kill>, 1, %noreg, 0, %noreg, %vreg86<kill>; mem:ST1[%261] GR64:%vreg81 GR8:%vreg86
11056B		%vreg77<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg77
11072B		%vreg56<def> = MOV32rm %vreg77<kill>, 1, %noreg, 3184, %noreg; mem:LD4[%calculatedBlockCRC356] GR32:%vreg56 GR64:%vreg77
11104B		%vreg56<def,tied1> = SHL32ri %vreg56<kill,tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg56
11120B		%vreg72<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg72
11136B		%vreg63<def> = MOV32rm %vreg72<kill>, 1, %noreg, 3184, %noreg; mem:LD4[%calculatedBlockCRC358] GR32:%vreg63 GR64:%vreg72
11168B		%vreg63<def,tied1> = SHR32ri %vreg63<kill,tied0>, 24, %EFLAGS<imp-def,dead>; GR32:%vreg63
11184B		%vreg67<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg67
11200B		%vreg65<def> = MOVZX32rm8 %vreg67<kill>, 1, %noreg, 12, %noreg; mem:LD1[%state_out_ch360] GR32:%vreg65 GR64:%vreg67
11232B		%vreg63<def,tied1> = XOR32rr %vreg63<kill,tied0>, %vreg65<kill>, %EFLAGS<imp-def,dead>; GR32:%vreg63,%vreg65
11248B		%vreg60:sub_32bit<def,read-undef> = MOV32rr %vreg63<kill>; GR64_NOSP:%vreg60 GR32:%vreg63
11296B		%vreg56<def,tied1> = XOR32rm %vreg56<kill,tied0>, %noreg, 4, %vreg60<kill>, <ga:@BZ2_crc32Table>, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%arrayidx364] GR32:%vreg56 GR64_NOSP:%vreg60
11312B		%vreg53<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg53
11328B		MOV32mr %vreg53<kill>, 1, %noreg, 3184, %noreg, %vreg56<kill>; mem:ST4[%calculatedBlockCRC366] GR64:%vreg53 GR32:%vreg56
11344B		%vreg50<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg50
11360B		%vreg48<def> = MOV32rm %vreg50, 1, %noreg, 16, %noreg; mem:LD4[%state_out_len367] GR32:%vreg48 GR64:%vreg50
11392B		%vreg48<def,tied1> = ADD32ri8 %vreg48<kill,tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg48
11408B		MOV32mr %vreg50<kill>, 1, %noreg, 16, %noreg, %vreg48<kill>; mem:ST4[%state_out_len367] GR64:%vreg50 GR32:%vreg48
11424B		%vreg44<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg44
11440B		%vreg43<def> = MOV64rm %vreg44<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm369] GR64:%vreg43,%vreg44
11456B		%vreg40<def> = MOV64rm %vreg43, 1, %noreg, 24, %noreg; mem:LD8[%next_out370] GR64:%vreg40,%vreg43
11488B		%vreg40<def,tied1> = ADD64ri8 %vreg40<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR64:%vreg40
11504B		MOV64mr %vreg43<kill>, 1, %noreg, 24, %noreg, %vreg40<kill>; mem:ST8[%next_out370] GR64:%vreg43,%vreg40
11520B		%vreg36<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg36
11536B		%vreg35<def> = MOV64rm %vreg36<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm372] GR64:%vreg35,%vreg36
11552B		%vreg32<def> = MOV32rm %vreg35, 1, %noreg, 32, %noreg; mem:LD4[%avail_out373] GR32:%vreg32 GR64:%vreg35
11584B		%vreg32<def,tied1> = ADD32ri8 %vreg32<kill,tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg32
11600B		MOV32mr %vreg35<kill>, 1, %noreg, 32, %noreg, %vreg32<kill>; mem:ST4[%avail_out373] GR64:%vreg35 GR32:%vreg32
11616B		%vreg28<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg28
11632B		%vreg27<def> = MOV64rm %vreg28<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm375] GR64:%vreg27,%vreg28
11648B		%vreg24<def> = MOV32rm %vreg27, 1, %noreg, 36, %noreg; mem:LD4[%total_out_lo32376] GR32:%vreg24 GR64:%vreg27
11680B		%vreg24<def,tied1> = ADD32ri8 %vreg24<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg24
11696B		MOV32mr %vreg27<kill>, 1, %noreg, 36, %noreg, %vreg24<kill>; mem:ST4[%total_out_lo32376] GR64:%vreg27 GR32:%vreg24
11712B		%vreg20<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg20
11728B		%vreg19<def> = MOV64rm %vreg20<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm378] GR64:%vreg19,%vreg20
11744B		CMP32mi8 %vreg19<kill>, 1, %noreg, 36, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%total_out_lo32379] GR64:%vreg19
11760B		JNE_1 <BB#55>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#55 BB#54
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %AL<def> = MOV8rm %RAX<kill>, 1, %noreg, 12, %noreg; mem:LD1[%state_out_ch353]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RCX<def> = MOV64rm %RCX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm354]
> %RCX<def> = MOV64rm %RCX<kill>, 1, %noreg, 24, %noreg; mem:LD8[%next_out355]
> MOV8mr %RCX<kill>, 1, %noreg, 0, %noreg, %AL<kill>; mem:ST1[%261]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 3184, %noreg; mem:LD4[%calculatedBlockCRC356]
> %EAX<def,tied1> = SHL32ri %EAX<kill,tied0>, 8, %EFLAGS<imp-def,dead>
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RCX<kill>, 1, %noreg, 3184, %noreg; mem:LD4[%calculatedBlockCRC358]
> %ECX<def,tied1> = SHR32ri %ECX<kill,tied0>, 24, %EFLAGS<imp-def,dead>
> %RDX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EDX<def> = MOVZX32rm8 %RDX<kill>, 1, %noreg, 12, %noreg; mem:LD1[%state_out_ch360]
> %ECX<def,tied1> = XOR32rr %ECX<kill,tied0>, %EDX<kill>, %EFLAGS<imp-def,dead>
> %ECX<def> = MOV32rr %ECX<kill>, %RCX<imp-def>
> %EAX<def,tied1> = XOR32rm %EAX<kill,tied0>, %noreg, 4, %RCX<kill>, <ga:@BZ2_crc32Table>, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%arrayidx364]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mr %RCX<kill>, 1, %noreg, 3184, %noreg, %EAX<kill>; mem:ST4[%calculatedBlockCRC366]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 16, %noreg; mem:LD4[%state_out_len367]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, -1, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 16, %noreg, %ECX<kill>; mem:ST4[%state_out_len367]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm369]
> %RCX<def> = MOV64rm %RAX, 1, %noreg, 24, %noreg; mem:LD8[%next_out370]
> %RCX<def,tied1> = ADD64ri8 %RCX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV64mr %RAX<kill>, 1, %noreg, 24, %noreg, %RCX<kill>; mem:ST8[%next_out370]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm372]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 32, %noreg; mem:LD4[%avail_out373]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, -1, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 32, %noreg, %ECX<kill>; mem:ST4[%avail_out373]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm375]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 36, %noreg; mem:LD4[%total_out_lo32376]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 36, %noreg, %ECX<kill>; mem:ST4[%total_out_lo32376]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm378]
> CMP32mi8 %RAX<kill>, 1, %noreg, 36, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%total_out_lo32379]
> JNE_1 <BB#55>, %EFLAGS<imp-use,kill>
11776B	BB#54: derived from LLVM BB %if.then.382
	    Predecessors according to CFG: BB#53
11792B		%vreg95<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg95
11808B		%vreg94<def> = MOV64rm %vreg95<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm383] GR64:%vreg94,%vreg95
11824B		%vreg91<def> = MOV32rm %vreg94, 1, %noreg, 40, %noreg; mem:LD4[%total_out_hi32384] GR32:%vreg91 GR64:%vreg94
11856B		%vreg91<def,tied1> = ADD32ri8 %vreg91<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg91
11872B		MOV32mr %vreg94<kill>, 1, %noreg, 40, %noreg, %vreg91<kill>; mem:ST4[%total_out_hi32384] GR64:%vreg94 GR32:%vreg91
	    Successors according to CFG: BB#55
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm383]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 40, %noreg; mem:LD4[%total_out_hi32384]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 40, %noreg, %ECX<kill>; mem:ST4[%total_out_hi32384]
11888B	BB#55: derived from LLVM BB %if.end.386
	    Predecessors according to CFG: BB#53 BB#54
11904B		JMP_1 <BB#49>
	    Successors according to CFG: BB#49
> JMP_1 <BB#49>
11920B	BB#56: derived from LLVM BB %while.end.387
	    Predecessors according to CFG: BB#52
11936B		%vreg105<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg105
11952B		%vreg104<def> = MOV32rm %vreg105<kill>, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used388] GR32:%vreg104 GR64:%vreg105
11968B		%vreg102<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg102
11984B		%vreg99<def> = MOV32rm %vreg102<kill>, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock389] GR32:%vreg99 GR64:%vreg102
12016B		%vreg99<def,tied1> = ADD32ri8 %vreg99<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg99
12032B		CMP32rr %vreg104<kill>, %vreg99<kill>, %EFLAGS<imp-def>; GR32:%vreg104,%vreg99
12048B		JNE_1 <BB#58>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#58 BB#57
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used388]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RCX<kill>, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock389]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> CMP32rr %EAX<kill>, %ECX<kill>, %EFLAGS<imp-def>
> JNE_1 <BB#58>, %EFLAGS<imp-use,kill>
12064B	BB#57: derived from LLVM BB %if.then.393
	    Predecessors according to CFG: BB#56
12080B		MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST1[%retval]
12096B		JMP_1 <BB#73>
	    Successors according to CFG: BB#73
> MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST1[%retval]
> JMP_1 <BB#73>
12112B	BB#58: derived from LLVM BB %if.end.394
	    Predecessors according to CFG: BB#56
12128B		%vreg115<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg115
12144B		%vreg114<def> = MOV32rm %vreg115<kill>, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used395] GR32:%vreg114 GR64:%vreg115
12160B		%vreg112<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg112
12176B		%vreg109<def> = MOV32rm %vreg112<kill>, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock396] GR32:%vreg109 GR64:%vreg112
12208B		%vreg109<def,tied1> = ADD32ri8 %vreg109<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg109
12224B		CMP32rr %vreg114<kill>, %vreg109<kill>, %EFLAGS<imp-def>; GR32:%vreg114,%vreg109
12240B		JLE_1 <BB#60>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#60 BB#59
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used395]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RCX<kill>, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock396]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> CMP32rr %EAX<kill>, %ECX<kill>, %EFLAGS<imp-def>
> JLE_1 <BB#60>, %EFLAGS<imp-use,kill>
12256B	BB#59: derived from LLVM BB %if.then.400
	    Predecessors according to CFG: BB#58
12272B		MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 1; mem:ST1[%retval]
12288B		JMP_1 <BB#73>
	    Successors according to CFG: BB#73
> MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 1; mem:ST1[%retval]
> JMP_1 <BB#73>
12304B	BB#60: derived from LLVM BB %if.end.401
	    Predecessors according to CFG: BB#58
12320B		%vreg201<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg201
12336B		MOV32mi %vreg201<kill>, 1, %noreg, 16, %noreg, 1; mem:ST4[%state_out_len402] GR64:%vreg201
12352B		%vreg199<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg199
12368B		%vreg198<def> = MOV32rm %vreg199<kill>, 1, %noreg, 64, %noreg; mem:LD4[%k0403] GR32:%vreg198 GR64:%vreg199
12400B		%vreg194<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg194
12416B		MOV8mr %vreg194<kill>, 1, %noreg, 12, %noreg, %vreg198:sub_8bit<kill>; mem:ST1[%state_out_ch405] GR64:%vreg194 GR32:%vreg198
12432B		%vreg191<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg191
12448B		%vreg190<def> = MOV32rm %vreg191<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos406] GR32:%vreg190 GR64:%vreg191
12464B		%vreg187<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg187
12496B		%vreg187<def,tied1> = ADD64ri32 %vreg187<kill,tied0>, 1096, %EFLAGS<imp-def,dead>; GR64:%vreg187
12512B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
12528B		%EDI<def> = COPY %vreg190<kill>; GR32:%vreg190
12544B		%RSI<def> = COPY %vreg187<kill>; GR64:%vreg187
12560B		CALL64pcrel32 <ga:@BZ2_indexIntoF>, <regmask>, %RSP<imp-use>, %EDI<imp-use>, %RSI<imp-use>, %EAX<imp-def>
12576B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
12592B		%vreg184<def> = COPY %EAX; GR32:%vreg184
12608B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
12624B		STACKMAP 6, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
12640B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
12672B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg184:sub_8bit<kill>; mem:ST1[%k1] GR32:%vreg184
12688B		%vreg178<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg178
12704B		%vreg176:sub_32bit<def,read-undef> = MOV32rm %vreg178<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos411] GR64_NOSP:%vreg176 GR64:%vreg178
12736B		%vreg173<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg173
12752B		%vreg172<def> = MOV64rm %vreg173<kill>, 1, %noreg, 3160, %noreg; mem:LD8[%ll16413] GR64:%vreg172,%vreg173
12768B		%vreg137<def> = MOVZX32rm16 %vreg172<kill>, 2, %vreg176<kill>, 0, %noreg; mem:LD2[%arrayidx414] GR32:%vreg137 GR64:%vreg172 GR64_NOSP:%vreg176
12784B		%vreg166<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg166
12800B		%vreg163<def> = MOV32rm %vreg166<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos416] GR32:%vreg163 GR64:%vreg166
12832B		%vreg163<def,tied1> = SHR32ri %vreg163<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg163
12848B		%vreg161:sub_32bit<def,read-undef> = MOV32rr %vreg163<kill>; GR64_NOSP:%vreg161 GR32:%vreg163
12880B		%vreg158<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg158
12896B		%vreg157<def> = MOV64rm %vreg158<kill>, 1, %noreg, 3168, %noreg; mem:LD8[%ll4419] GR64:%vreg157,%vreg158
12912B		%vreg141<def> = MOVZX32rm8 %vreg157<kill>, 1, %vreg161<kill>, 0, %noreg; mem:LD1[%arrayidx420] GR32:%vreg141 GR64:%vreg157 GR64_NOSP:%vreg161
12928B		%vreg151<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg151
12944B		%vreg146<def> = MOV32rm %vreg151<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos422] GR32:%vreg146 GR64:%vreg151
12976B		%vreg146<def,tied1> = SHL32ri %vreg146<kill,tied0>, 2, %EFLAGS<imp-def,dead>; GR32:%vreg146
13008B		%vreg146<def,tied1> = AND32ri8 %vreg146<kill,tied0>, 4, %EFLAGS<imp-def,dead>; GR32:%vreg146
13024B		%ECX<def> = COPY %vreg146<kill>; GR32:%vreg146
13040B		%CL<def> = KILL %ECX
13072B		%vreg141<def,tied1> = SHR32rCL %vreg141<kill,tied0>, %EFLAGS<imp-def,dead>, %CL<imp-use>; GR32:%vreg141
13104B		%vreg141<def,tied1> = AND32ri8 %vreg141<kill,tied0>, 15, %EFLAGS<imp-def,dead>; GR32:%vreg141
13136B		%vreg141<def,tied1> = SHL32ri %vreg141<kill,tied0>, 16, %EFLAGS<imp-def,dead>; GR32:%vreg141
13168B		%vreg137<def,tied1> = OR32rr %vreg137<kill,tied0>, %vreg141<kill>, %EFLAGS<imp-def,dead>; GR32:%vreg137,%vreg141
13184B		%vreg134<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg134
13200B		MOV32mr %vreg134<kill>, 1, %noreg, 60, %noreg, %vreg137<kill>; mem:ST4[%tPos429] GR64:%vreg134 GR32:%vreg137
13216B		%vreg131<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg131
13232B		%vreg129<def> = MOV32rm %vreg131, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used430] GR32:%vreg129 GR64:%vreg131
13264B		%vreg129<def,tied1> = ADD32ri8 %vreg129<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg129
13280B		MOV32mr %vreg131<kill>, 1, %noreg, 1092, %noreg, %vreg129<kill>; mem:ST4[%nblock_used430] GR64:%vreg131 GR32:%vreg129
13296B		%vreg125<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg125
13312B		%vreg124<def> = MOV32rm %vreg125<kill>, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used432] GR32:%vreg124 GR64:%vreg125
13328B		%vreg122<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg122
13344B		%vreg119<def> = MOV32rm %vreg122<kill>, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock433] GR32:%vreg119 GR64:%vreg122
13376B		%vreg119<def,tied1> = ADD32ri8 %vreg119<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg119
13392B		CMP32rr %vreg124<kill>, %vreg119<kill>, %EFLAGS<imp-def>; GR32:%vreg124,%vreg119
13408B		JNE_1 <BB#62>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#62 BB#61
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 16, %noreg, 1; mem:ST4[%state_out_len402]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 64, %noreg; mem:LD4[%k0403]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV8mr %RCX<kill>, 1, %noreg, 12, %noreg, %AL, %EAX<imp-use,kill>; mem:ST1[%state_out_ch405]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EDI<def> = MOV32rm %RAX<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos406]
> %RSI<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RSI<def,tied1> = ADD64ri32 %RSI<kill,tied0>, 1096, %EFLAGS<imp-def,dead>
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EDI<def> = COPY %EDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@BZ2_indexIntoF>, <regmask>, %RSP<imp-use>, %EDI<imp-use>, %RSI<imp-use>, %EAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def> = COPY %EAX
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 6, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %AL, %EAX<imp-use,kill>; mem:ST1[%k1]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 60, %noreg, %RAX<imp-def>; mem:LD4[%tPos411]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RCX<def> = MOV64rm %RCX<kill>, 1, %noreg, 3160, %noreg; mem:LD8[%ll16413]
> %EAX<def> = MOVZX32rm16 %RCX<kill>, 2, %RAX<kill>, 0, %noreg; mem:LD2[%arrayidx414]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RCX<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos416]
> %ECX<def,tied1> = SHR32ri %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> %ECX<def> = MOV32rr %ECX<kill>, %RCX<imp-def>
> %RDX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RDX<def> = MOV64rm %RDX<kill>, 1, %noreg, 3168, %noreg; mem:LD8[%ll4419]
> %EDX<def> = MOVZX32rm8 %RDX<kill>, 1, %RCX<kill>, 0, %noreg; mem:LD1[%arrayidx420]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RCX<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos422]
> %ECX<def,tied1> = SHL32ri %ECX<kill,tied0>, 2, %EFLAGS<imp-def,dead>
> %ECX<def,tied1> = AND32ri8 %ECX<kill,tied0>, 4, %EFLAGS<imp-def,dead>
> %ECX<def> = COPY %ECX<kill>
Deleting identity copy.
> %CL<def> = KILL %ECX
> %EDX<def,tied1> = SHR32rCL %EDX<kill,tied0>, %EFLAGS<imp-def,dead>, %CL<imp-use>
> %EDX<def,tied1> = AND32ri8 %EDX<kill,tied0>, 15, %EFLAGS<imp-def,dead>
> %EDX<def,tied1> = SHL32ri %EDX<kill,tied0>, 16, %EFLAGS<imp-def,dead>
> %EAX<def,tied1> = OR32rr %EAX<kill,tied0>, %EDX<kill>, %EFLAGS<imp-def,dead>
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mr %RCX<kill>, 1, %noreg, 60, %noreg, %EAX<kill>; mem:ST4[%tPos429]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used430]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 1092, %noreg, %ECX<kill>; mem:ST4[%nblock_used430]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used432]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RCX<kill>, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock433]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> CMP32rr %EAX<kill>, %ECX<kill>, %EFLAGS<imp-def>
> JNE_1 <BB#62>, %EFLAGS<imp-use,kill>
13424B	BB#61: derived from LLVM BB %if.then.437
	    Predecessors according to CFG: BB#60
13440B		JMP_1 <BB#48>
	    Successors according to CFG: BB#48
> JMP_1 <BB#48>
13456B	BB#62: derived from LLVM BB %if.end.438
	    Predecessors according to CFG: BB#60
13472B		%vreg207<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg207
13488B		%vreg205<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg205
13504B		CMP32rm %vreg207<kill>, %vreg205<kill>, 1, %noreg, 64, %noreg, %EFLAGS<imp-def>; mem:LD4[%k0440] GR32:%vreg207 GR64:%vreg205
13520B		JE_1 <BB#64>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#64 BB#63
> %EAX<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> CMP32rm %EAX<kill>, %RCX<kill>, 1, %noreg, 64, %noreg, %EFLAGS<imp-def>; mem:LD4[%k0440]
> JE_1 <BB#64>, %EFLAGS<imp-use,kill>
13536B	BB#63: derived from LLVM BB %if.then.443
	    Predecessors according to CFG: BB#62
13552B		%vreg529<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg529
13568B		%vreg527<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg527
13584B		MOV32mr %vreg527<kill>, 1, %noreg, 64, %noreg, %vreg529<kill>; mem:ST4[%k0445] GR64:%vreg527 GR32:%vreg529
13600B		JMP_1 <BB#48>
	    Successors according to CFG: BB#48
> %EAX<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mr %RCX<kill>, 1, %noreg, 64, %noreg, %EAX<kill>; mem:ST4[%k0445]
> JMP_1 <BB#48>
13616B	BB#64: derived from LLVM BB %if.end.446
	    Predecessors according to CFG: BB#62
13632B		%vreg285<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg285
13648B		MOV32mi %vreg285<kill>, 1, %noreg, 16, %noreg, 2; mem:ST4[%state_out_len447] GR64:%vreg285
13664B		%vreg283<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg283
13680B		%vreg282<def> = MOV32rm %vreg283<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos448] GR32:%vreg282 GR64:%vreg283
13696B		%vreg279<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg279
13728B		%vreg279<def,tied1> = ADD64ri32 %vreg279<kill,tied0>, 1096, %EFLAGS<imp-def,dead>; GR64:%vreg279
13744B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
13760B		%EDI<def> = COPY %vreg282<kill>; GR32:%vreg282
13776B		%RSI<def> = COPY %vreg279<kill>; GR64:%vreg279
13792B		CALL64pcrel32 <ga:@BZ2_indexIntoF>, <regmask>, %RSP<imp-use>, %EDI<imp-use>, %RSI<imp-use>, %EAX<imp-def>
13808B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
13824B		%vreg276<def> = COPY %EAX; GR32:%vreg276
13840B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
13856B		STACKMAP 7, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
13872B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
13904B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg276:sub_8bit<kill>; mem:ST1[%k1] GR32:%vreg276
13920B		%vreg270<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg270
13936B		%vreg268:sub_32bit<def,read-undef> = MOV32rm %vreg270<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos453] GR64_NOSP:%vreg268 GR64:%vreg270
13968B		%vreg265<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg265
13984B		%vreg264<def> = MOV64rm %vreg265<kill>, 1, %noreg, 3160, %noreg; mem:LD8[%ll16455] GR64:%vreg264,%vreg265
14000B		%vreg229<def> = MOVZX32rm16 %vreg264<kill>, 2, %vreg268<kill>, 0, %noreg; mem:LD2[%arrayidx456] GR32:%vreg229 GR64:%vreg264 GR64_NOSP:%vreg268
14016B		%vreg258<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg258
14032B		%vreg255<def> = MOV32rm %vreg258<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos458] GR32:%vreg255 GR64:%vreg258
14064B		%vreg255<def,tied1> = SHR32ri %vreg255<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg255
14080B		%vreg253:sub_32bit<def,read-undef> = MOV32rr %vreg255<kill>; GR64_NOSP:%vreg253 GR32:%vreg255
14112B		%vreg250<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg250
14128B		%vreg249<def> = MOV64rm %vreg250<kill>, 1, %noreg, 3168, %noreg; mem:LD8[%ll4461] GR64:%vreg249,%vreg250
14144B		%vreg233<def> = MOVZX32rm8 %vreg249<kill>, 1, %vreg253<kill>, 0, %noreg; mem:LD1[%arrayidx462] GR32:%vreg233 GR64:%vreg249 GR64_NOSP:%vreg253
14160B		%vreg243<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg243
14176B		%vreg238<def> = MOV32rm %vreg243<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos464] GR32:%vreg238 GR64:%vreg243
14208B		%vreg238<def,tied1> = SHL32ri %vreg238<kill,tied0>, 2, %EFLAGS<imp-def,dead>; GR32:%vreg238
14240B		%vreg238<def,tied1> = AND32ri8 %vreg238<kill,tied0>, 4, %EFLAGS<imp-def,dead>; GR32:%vreg238
14256B		%ECX<def> = COPY %vreg238<kill>; GR32:%vreg238
14272B		%CL<def> = KILL %ECX
14304B		%vreg233<def,tied1> = SHR32rCL %vreg233<kill,tied0>, %EFLAGS<imp-def,dead>, %CL<imp-use>; GR32:%vreg233
14336B		%vreg233<def,tied1> = AND32ri8 %vreg233<kill,tied0>, 15, %EFLAGS<imp-def,dead>; GR32:%vreg233
14368B		%vreg233<def,tied1> = SHL32ri %vreg233<kill,tied0>, 16, %EFLAGS<imp-def,dead>; GR32:%vreg233
14400B		%vreg229<def,tied1> = OR32rr %vreg229<kill,tied0>, %vreg233<kill>, %EFLAGS<imp-def,dead>; GR32:%vreg229,%vreg233
14416B		%vreg226<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg226
14432B		MOV32mr %vreg226<kill>, 1, %noreg, 60, %noreg, %vreg229<kill>; mem:ST4[%tPos471] GR64:%vreg226 GR32:%vreg229
14448B		%vreg223<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg223
14464B		%vreg221<def> = MOV32rm %vreg223, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used472] GR32:%vreg221 GR64:%vreg223
14496B		%vreg221<def,tied1> = ADD32ri8 %vreg221<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg221
14512B		MOV32mr %vreg223<kill>, 1, %noreg, 1092, %noreg, %vreg221<kill>; mem:ST4[%nblock_used472] GR64:%vreg223 GR32:%vreg221
14528B		%vreg217<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg217
14544B		%vreg216<def> = MOV32rm %vreg217<kill>, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used474] GR32:%vreg216 GR64:%vreg217
14560B		%vreg214<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg214
14576B		%vreg211<def> = MOV32rm %vreg214<kill>, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock475] GR32:%vreg211 GR64:%vreg214
14608B		%vreg211<def,tied1> = ADD32ri8 %vreg211<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg211
14624B		CMP32rr %vreg216<kill>, %vreg211<kill>, %EFLAGS<imp-def>; GR32:%vreg216,%vreg211
14640B		JNE_1 <BB#66>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#66 BB#65
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 16, %noreg, 2; mem:ST4[%state_out_len447]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EDI<def> = MOV32rm %RAX<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos448]
> %RSI<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RSI<def,tied1> = ADD64ri32 %RSI<kill,tied0>, 1096, %EFLAGS<imp-def,dead>
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EDI<def> = COPY %EDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@BZ2_indexIntoF>, <regmask>, %RSP<imp-use>, %EDI<imp-use>, %RSI<imp-use>, %EAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def> = COPY %EAX
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 7, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %AL, %EAX<imp-use,kill>; mem:ST1[%k1]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 60, %noreg, %RAX<imp-def>; mem:LD4[%tPos453]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RCX<def> = MOV64rm %RCX<kill>, 1, %noreg, 3160, %noreg; mem:LD8[%ll16455]
> %EAX<def> = MOVZX32rm16 %RCX<kill>, 2, %RAX<kill>, 0, %noreg; mem:LD2[%arrayidx456]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RCX<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos458]
> %ECX<def,tied1> = SHR32ri %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> %ECX<def> = MOV32rr %ECX<kill>, %RCX<imp-def>
> %RDX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RDX<def> = MOV64rm %RDX<kill>, 1, %noreg, 3168, %noreg; mem:LD8[%ll4461]
> %EDX<def> = MOVZX32rm8 %RDX<kill>, 1, %RCX<kill>, 0, %noreg; mem:LD1[%arrayidx462]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RCX<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos464]
> %ECX<def,tied1> = SHL32ri %ECX<kill,tied0>, 2, %EFLAGS<imp-def,dead>
> %ECX<def,tied1> = AND32ri8 %ECX<kill,tied0>, 4, %EFLAGS<imp-def,dead>
> %ECX<def> = COPY %ECX<kill>
Deleting identity copy.
> %CL<def> = KILL %ECX
> %EDX<def,tied1> = SHR32rCL %EDX<kill,tied0>, %EFLAGS<imp-def,dead>, %CL<imp-use>
> %EDX<def,tied1> = AND32ri8 %EDX<kill,tied0>, 15, %EFLAGS<imp-def,dead>
> %EDX<def,tied1> = SHL32ri %EDX<kill,tied0>, 16, %EFLAGS<imp-def,dead>
> %EAX<def,tied1> = OR32rr %EAX<kill,tied0>, %EDX<kill>, %EFLAGS<imp-def,dead>
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mr %RCX<kill>, 1, %noreg, 60, %noreg, %EAX<kill>; mem:ST4[%tPos471]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used472]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 1092, %noreg, %ECX<kill>; mem:ST4[%nblock_used472]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used474]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RCX<kill>, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock475]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> CMP32rr %EAX<kill>, %ECX<kill>, %EFLAGS<imp-def>
> JNE_1 <BB#66>, %EFLAGS<imp-use,kill>
14656B	BB#65: derived from LLVM BB %if.then.479
	    Predecessors according to CFG: BB#64
14672B		JMP_1 <BB#48>
	    Successors according to CFG: BB#48
> JMP_1 <BB#48>
14688B	BB#66: derived from LLVM BB %if.end.480
	    Predecessors according to CFG: BB#64
14704B		%vreg291<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg291
14720B		%vreg289<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg289
14736B		CMP32rm %vreg291<kill>, %vreg289<kill>, 1, %noreg, 64, %noreg, %EFLAGS<imp-def>; mem:LD4[%k0482] GR32:%vreg291 GR64:%vreg289
14752B		JE_1 <BB#68>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#68 BB#67
> %EAX<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> CMP32rm %EAX<kill>, %RCX<kill>, 1, %noreg, 64, %noreg, %EFLAGS<imp-def>; mem:LD4[%k0482]
> JE_1 <BB#68>, %EFLAGS<imp-use,kill>
14768B	BB#67: derived from LLVM BB %if.then.485
	    Predecessors according to CFG: BB#66
14784B		%vreg524<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg524
14800B		%vreg522<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg522
14816B		MOV32mr %vreg522<kill>, 1, %noreg, 64, %noreg, %vreg524<kill>; mem:ST4[%k0487] GR64:%vreg522 GR32:%vreg524
14832B		JMP_1 <BB#48>
	    Successors according to CFG: BB#48
> %EAX<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mr %RCX<kill>, 1, %noreg, 64, %noreg, %EAX<kill>; mem:ST4[%k0487]
> JMP_1 <BB#48>
14848B	BB#68: derived from LLVM BB %if.end.488
	    Predecessors according to CFG: BB#66
14864B		%vreg369<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg369
14880B		MOV32mi %vreg369<kill>, 1, %noreg, 16, %noreg, 3; mem:ST4[%state_out_len489] GR64:%vreg369
14896B		%vreg367<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg367
14912B		%vreg366<def> = MOV32rm %vreg367<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos490] GR32:%vreg366 GR64:%vreg367
14928B		%vreg363<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg363
14960B		%vreg363<def,tied1> = ADD64ri32 %vreg363<kill,tied0>, 1096, %EFLAGS<imp-def,dead>; GR64:%vreg363
14976B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
14992B		%EDI<def> = COPY %vreg366<kill>; GR32:%vreg366
15008B		%RSI<def> = COPY %vreg363<kill>; GR64:%vreg363
15024B		CALL64pcrel32 <ga:@BZ2_indexIntoF>, <regmask>, %RSP<imp-use>, %EDI<imp-use>, %RSI<imp-use>, %EAX<imp-def>
15040B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
15056B		%vreg360<def> = COPY %EAX; GR32:%vreg360
15072B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
15088B		STACKMAP 8, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
15104B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
15136B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg360:sub_8bit<kill>; mem:ST1[%k1] GR32:%vreg360
15152B		%vreg354<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg354
15168B		%vreg352:sub_32bit<def,read-undef> = MOV32rm %vreg354<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos495] GR64_NOSP:%vreg352 GR64:%vreg354
15200B		%vreg349<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg349
15216B		%vreg348<def> = MOV64rm %vreg349<kill>, 1, %noreg, 3160, %noreg; mem:LD8[%ll16497] GR64:%vreg348,%vreg349
15232B		%vreg313<def> = MOVZX32rm16 %vreg348<kill>, 2, %vreg352<kill>, 0, %noreg; mem:LD2[%arrayidx498] GR32:%vreg313 GR64:%vreg348 GR64_NOSP:%vreg352
15248B		%vreg342<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg342
15264B		%vreg339<def> = MOV32rm %vreg342<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos500] GR32:%vreg339 GR64:%vreg342
15296B		%vreg339<def,tied1> = SHR32ri %vreg339<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg339
15312B		%vreg337:sub_32bit<def,read-undef> = MOV32rr %vreg339<kill>; GR64_NOSP:%vreg337 GR32:%vreg339
15344B		%vreg334<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg334
15360B		%vreg333<def> = MOV64rm %vreg334<kill>, 1, %noreg, 3168, %noreg; mem:LD8[%ll4503] GR64:%vreg333,%vreg334
15376B		%vreg317<def> = MOVZX32rm8 %vreg333<kill>, 1, %vreg337<kill>, 0, %noreg; mem:LD1[%arrayidx504] GR32:%vreg317 GR64:%vreg333 GR64_NOSP:%vreg337
15392B		%vreg327<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg327
15408B		%vreg322<def> = MOV32rm %vreg327<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos506] GR32:%vreg322 GR64:%vreg327
15440B		%vreg322<def,tied1> = SHL32ri %vreg322<kill,tied0>, 2, %EFLAGS<imp-def,dead>; GR32:%vreg322
15472B		%vreg322<def,tied1> = AND32ri8 %vreg322<kill,tied0>, 4, %EFLAGS<imp-def,dead>; GR32:%vreg322
15488B		%ECX<def> = COPY %vreg322<kill>; GR32:%vreg322
15504B		%CL<def> = KILL %ECX
15536B		%vreg317<def,tied1> = SHR32rCL %vreg317<kill,tied0>, %EFLAGS<imp-def,dead>, %CL<imp-use>; GR32:%vreg317
15568B		%vreg317<def,tied1> = AND32ri8 %vreg317<kill,tied0>, 15, %EFLAGS<imp-def,dead>; GR32:%vreg317
15600B		%vreg317<def,tied1> = SHL32ri %vreg317<kill,tied0>, 16, %EFLAGS<imp-def,dead>; GR32:%vreg317
15632B		%vreg313<def,tied1> = OR32rr %vreg313<kill,tied0>, %vreg317<kill>, %EFLAGS<imp-def,dead>; GR32:%vreg313,%vreg317
15648B		%vreg310<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg310
15664B		MOV32mr %vreg310<kill>, 1, %noreg, 60, %noreg, %vreg313<kill>; mem:ST4[%tPos513] GR64:%vreg310 GR32:%vreg313
15680B		%vreg307<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg307
15696B		%vreg305<def> = MOV32rm %vreg307, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used514] GR32:%vreg305 GR64:%vreg307
15728B		%vreg305<def,tied1> = ADD32ri8 %vreg305<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg305
15744B		MOV32mr %vreg307<kill>, 1, %noreg, 1092, %noreg, %vreg305<kill>; mem:ST4[%nblock_used514] GR64:%vreg307 GR32:%vreg305
15760B		%vreg301<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg301
15776B		%vreg300<def> = MOV32rm %vreg301<kill>, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used516] GR32:%vreg300 GR64:%vreg301
15792B		%vreg298<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg298
15808B		%vreg295<def> = MOV32rm %vreg298<kill>, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock517] GR32:%vreg295 GR64:%vreg298
15840B		%vreg295<def,tied1> = ADD32ri8 %vreg295<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg295
15856B		CMP32rr %vreg300<kill>, %vreg295<kill>, %EFLAGS<imp-def>; GR32:%vreg300,%vreg295
15872B		JNE_1 <BB#70>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#70 BB#69
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 16, %noreg, 3; mem:ST4[%state_out_len489]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EDI<def> = MOV32rm %RAX<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos490]
> %RSI<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RSI<def,tied1> = ADD64ri32 %RSI<kill,tied0>, 1096, %EFLAGS<imp-def,dead>
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EDI<def> = COPY %EDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@BZ2_indexIntoF>, <regmask>, %RSP<imp-use>, %EDI<imp-use>, %RSI<imp-use>, %EAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def> = COPY %EAX
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 8, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %AL, %EAX<imp-use,kill>; mem:ST1[%k1]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 60, %noreg, %RAX<imp-def>; mem:LD4[%tPos495]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RCX<def> = MOV64rm %RCX<kill>, 1, %noreg, 3160, %noreg; mem:LD8[%ll16497]
> %EAX<def> = MOVZX32rm16 %RCX<kill>, 2, %RAX<kill>, 0, %noreg; mem:LD2[%arrayidx498]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RCX<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos500]
> %ECX<def,tied1> = SHR32ri %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> %ECX<def> = MOV32rr %ECX<kill>, %RCX<imp-def>
> %RDX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RDX<def> = MOV64rm %RDX<kill>, 1, %noreg, 3168, %noreg; mem:LD8[%ll4503]
> %EDX<def> = MOVZX32rm8 %RDX<kill>, 1, %RCX<kill>, 0, %noreg; mem:LD1[%arrayidx504]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RCX<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos506]
> %ECX<def,tied1> = SHL32ri %ECX<kill,tied0>, 2, %EFLAGS<imp-def,dead>
> %ECX<def,tied1> = AND32ri8 %ECX<kill,tied0>, 4, %EFLAGS<imp-def,dead>
> %ECX<def> = COPY %ECX<kill>
Deleting identity copy.
> %CL<def> = KILL %ECX
> %EDX<def,tied1> = SHR32rCL %EDX<kill,tied0>, %EFLAGS<imp-def,dead>, %CL<imp-use>
> %EDX<def,tied1> = AND32ri8 %EDX<kill,tied0>, 15, %EFLAGS<imp-def,dead>
> %EDX<def,tied1> = SHL32ri %EDX<kill,tied0>, 16, %EFLAGS<imp-def,dead>
> %EAX<def,tied1> = OR32rr %EAX<kill,tied0>, %EDX<kill>, %EFLAGS<imp-def,dead>
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mr %RCX<kill>, 1, %noreg, 60, %noreg, %EAX<kill>; mem:ST4[%tPos513]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used514]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 1092, %noreg, %ECX<kill>; mem:ST4[%nblock_used514]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used516]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RCX<kill>, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock517]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> CMP32rr %EAX<kill>, %ECX<kill>, %EFLAGS<imp-def>
> JNE_1 <BB#70>, %EFLAGS<imp-use,kill>
15888B	BB#69: derived from LLVM BB %if.then.521
	    Predecessors according to CFG: BB#68
15904B		JMP_1 <BB#48>
	    Successors according to CFG: BB#48
> JMP_1 <BB#48>
15920B	BB#70: derived from LLVM BB %if.end.522
	    Predecessors according to CFG: BB#68
15936B		%vreg375<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg375
15952B		%vreg373<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg373
15968B		CMP32rm %vreg375<kill>, %vreg373<kill>, 1, %noreg, 64, %noreg, %EFLAGS<imp-def>; mem:LD4[%k0524] GR32:%vreg375 GR64:%vreg373
15984B		JE_1 <BB#72>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#72 BB#71
> %EAX<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> CMP32rm %EAX<kill>, %RCX<kill>, 1, %noreg, 64, %noreg, %EFLAGS<imp-def>; mem:LD4[%k0524]
> JE_1 <BB#72>, %EFLAGS<imp-use,kill>
16000B	BB#71: derived from LLVM BB %if.then.527
	    Predecessors according to CFG: BB#70
16016B		%vreg519<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg519
16032B		%vreg517<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg517
16048B		MOV32mr %vreg517<kill>, 1, %noreg, 64, %noreg, %vreg519<kill>; mem:ST4[%k0529] GR64:%vreg517 GR32:%vreg519
16064B		JMP_1 <BB#48>
	    Successors according to CFG: BB#48
> %EAX<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mr %RCX<kill>, 1, %noreg, 64, %noreg, %EAX<kill>; mem:ST4[%k0529]
> JMP_1 <BB#48>
16080B	BB#72: derived from LLVM BB %if.end.530
	    Predecessors according to CFG: BB#70
16096B		%vreg514<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg514
16112B		%vreg513<def> = MOV32rm %vreg514<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos531] GR32:%vreg513 GR64:%vreg514
16128B		%vreg510<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg510
16160B		%vreg510<def,tied1> = ADD64ri32 %vreg510<kill,tied0>, 1096, %EFLAGS<imp-def,dead>; GR64:%vreg510
16176B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
16192B		%EDI<def> = COPY %vreg513<kill>; GR32:%vreg513
16208B		%RSI<def> = COPY %vreg510<kill>; GR64:%vreg510
16224B		CALL64pcrel32 <ga:@BZ2_indexIntoF>, <regmask>, %RSP<imp-use>, %EDI<imp-use>, %RSI<imp-use>, %EAX<imp-def>
16240B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
16256B		%vreg507<def> = COPY %EAX; GR32:%vreg507
16272B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
16288B		STACKMAP 9, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
16304B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
16336B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg507:sub_8bit<kill>; mem:ST1[%k1] GR32:%vreg507
16352B		%vreg501<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg501
16368B		%vreg499:sub_32bit<def,read-undef> = MOV32rm %vreg501<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos536] GR64_NOSP:%vreg499 GR64:%vreg501
16400B		%vreg496<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg496
16416B		%vreg495<def> = MOV64rm %vreg496<kill>, 1, %noreg, 3160, %noreg; mem:LD8[%ll16538] GR64:%vreg495,%vreg496
16432B		%vreg460<def> = MOVZX32rm16 %vreg495<kill>, 2, %vreg499<kill>, 0, %noreg; mem:LD2[%arrayidx539] GR32:%vreg460 GR64:%vreg495 GR64_NOSP:%vreg499
16448B		%vreg489<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg489
16464B		%vreg486<def> = MOV32rm %vreg489<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos541] GR32:%vreg486 GR64:%vreg489
16496B		%vreg486<def,tied1> = SHR32ri %vreg486<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg486
16512B		%vreg484:sub_32bit<def,read-undef> = MOV32rr %vreg486<kill>; GR64_NOSP:%vreg484 GR32:%vreg486
16544B		%vreg481<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg481
16560B		%vreg480<def> = MOV64rm %vreg481<kill>, 1, %noreg, 3168, %noreg; mem:LD8[%ll4544] GR64:%vreg480,%vreg481
16576B		%vreg464<def> = MOVZX32rm8 %vreg480<kill>, 1, %vreg484<kill>, 0, %noreg; mem:LD1[%arrayidx545] GR32:%vreg464 GR64:%vreg480 GR64_NOSP:%vreg484
16592B		%vreg474<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg474
16608B		%vreg469<def> = MOV32rm %vreg474<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos547] GR32:%vreg469 GR64:%vreg474
16640B		%vreg469<def,tied1> = SHL32ri %vreg469<kill,tied0>, 2, %EFLAGS<imp-def,dead>; GR32:%vreg469
16672B		%vreg469<def,tied1> = AND32ri8 %vreg469<kill,tied0>, 4, %EFLAGS<imp-def,dead>; GR32:%vreg469
16688B		%ECX<def> = COPY %vreg469<kill>; GR32:%vreg469
16704B		%CL<def> = KILL %ECX
16736B		%vreg464<def,tied1> = SHR32rCL %vreg464<kill,tied0>, %EFLAGS<imp-def,dead>, %CL<imp-use>; GR32:%vreg464
16768B		%vreg464<def,tied1> = AND32ri8 %vreg464<kill,tied0>, 15, %EFLAGS<imp-def,dead>; GR32:%vreg464
16800B		%vreg464<def,tied1> = SHL32ri %vreg464<kill,tied0>, 16, %EFLAGS<imp-def,dead>; GR32:%vreg464
16832B		%vreg460<def,tied1> = OR32rr %vreg460<kill,tied0>, %vreg464<kill>, %EFLAGS<imp-def,dead>; GR32:%vreg460,%vreg464
16848B		%vreg457<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg457
16864B		MOV32mr %vreg457<kill>, 1, %noreg, 60, %noreg, %vreg460<kill>; mem:ST4[%tPos554] GR64:%vreg457 GR32:%vreg460
16880B		%vreg454<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg454
16896B		%vreg452<def> = MOV32rm %vreg454, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used555] GR32:%vreg452 GR64:%vreg454
16928B		%vreg452<def,tied1> = ADD32ri8 %vreg452<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg452
16944B		MOV32mr %vreg454<kill>, 1, %noreg, 1092, %noreg, %vreg452<kill>; mem:ST4[%nblock_used555] GR64:%vreg454 GR32:%vreg452
16960B		%vreg446<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg446
16992B		%vreg446<def,tied1> = ADD32ri8 %vreg446<kill,tied0>, 4, %EFLAGS<imp-def,dead>; GR32:%vreg446
17008B		%vreg444<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg444
17024B		MOV32mr %vreg444<kill>, 1, %noreg, 16, %noreg, %vreg446<kill>; mem:ST4[%state_out_len559] GR64:%vreg444 GR32:%vreg446
17040B		%vreg441<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg441
17056B		%vreg440<def> = MOV32rm %vreg441<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos560] GR32:%vreg440 GR64:%vreg441
17072B		%vreg437<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg437
17104B		%vreg437<def,tied1> = ADD64ri32 %vreg437<kill,tied0>, 1096, %EFLAGS<imp-def,dead>; GR64:%vreg437
17120B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
17136B		%EDI<def> = COPY %vreg440<kill>; GR32:%vreg440
17152B		%RSI<def> = COPY %vreg437<kill>; GR64:%vreg437
17168B		CALL64pcrel32 <ga:@BZ2_indexIntoF>, <regmask>, %RSP<imp-use>, %EDI<imp-use>, %RSI<imp-use>, %EAX<imp-def>
17184B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
17200B		%vreg434<def> = COPY %EAX; GR32:%vreg434
17216B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
17232B		STACKMAP 10, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
17248B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
17264B		%vreg431<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg431
17280B		MOV32mr %vreg431<kill>, 1, %noreg, 64, %noreg, %vreg434<kill>; mem:ST4[%k0564] GR64:%vreg431 GR32:%vreg434
17296B		%vreg428<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg428
17312B		%vreg426:sub_32bit<def,read-undef> = MOV32rm %vreg428<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos565] GR64_NOSP:%vreg426 GR64:%vreg428
17344B		%vreg423<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg423
17360B		%vreg422<def> = MOV64rm %vreg423<kill>, 1, %noreg, 3160, %noreg; mem:LD8[%ll16567] GR64:%vreg422,%vreg423
17376B		%vreg387<def> = MOVZX32rm16 %vreg422<kill>, 2, %vreg426<kill>, 0, %noreg; mem:LD2[%arrayidx568] GR32:%vreg387 GR64:%vreg422 GR64_NOSP:%vreg426
17392B		%vreg416<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg416
17408B		%vreg413<def> = MOV32rm %vreg416<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos570] GR32:%vreg413 GR64:%vreg416
17440B		%vreg413<def,tied1> = SHR32ri %vreg413<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg413
17456B		%vreg411:sub_32bit<def,read-undef> = MOV32rr %vreg413<kill>; GR64_NOSP:%vreg411 GR32:%vreg413
17488B		%vreg408<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg408
17504B		%vreg407<def> = MOV64rm %vreg408<kill>, 1, %noreg, 3168, %noreg; mem:LD8[%ll4573] GR64:%vreg407,%vreg408
17520B		%vreg391<def> = MOVZX32rm8 %vreg407<kill>, 1, %vreg411<kill>, 0, %noreg; mem:LD1[%arrayidx574] GR32:%vreg391 GR64:%vreg407 GR64_NOSP:%vreg411
17536B		%vreg401<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg401
17552B		%vreg396<def> = MOV32rm %vreg401<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos576] GR32:%vreg396 GR64:%vreg401
17584B		%vreg396<def,tied1> = SHL32ri %vreg396<kill,tied0>, 2, %EFLAGS<imp-def,dead>; GR32:%vreg396
17616B		%vreg396<def,tied1> = AND32ri8 %vreg396<kill,tied0>, 4, %EFLAGS<imp-def,dead>; GR32:%vreg396
17632B		%ECX<def> = COPY %vreg396<kill>; GR32:%vreg396
17648B		%CL<def> = KILL %ECX
17680B		%vreg391<def,tied1> = SHR32rCL %vreg391<kill,tied0>, %EFLAGS<imp-def,dead>, %CL<imp-use>; GR32:%vreg391
17712B		%vreg391<def,tied1> = AND32ri8 %vreg391<kill,tied0>, 15, %EFLAGS<imp-def,dead>; GR32:%vreg391
17744B		%vreg391<def,tied1> = SHL32ri %vreg391<kill,tied0>, 16, %EFLAGS<imp-def,dead>; GR32:%vreg391
17776B		%vreg387<def,tied1> = OR32rr %vreg387<kill,tied0>, %vreg391<kill>, %EFLAGS<imp-def,dead>; GR32:%vreg387,%vreg391
17792B		%vreg384<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg384
17808B		MOV32mr %vreg384<kill>, 1, %noreg, 60, %noreg, %vreg387<kill>; mem:ST4[%tPos583] GR64:%vreg384 GR32:%vreg387
17824B		%vreg381<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg381
17840B		%vreg379<def> = MOV32rm %vreg381, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used584] GR32:%vreg379 GR64:%vreg381
17872B		%vreg379<def,tied1> = ADD32ri8 %vreg379<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg379
17888B		MOV32mr %vreg381<kill>, 1, %noreg, 1092, %noreg, %vreg379<kill>; mem:ST4[%nblock_used584] GR64:%vreg381 GR32:%vreg379
17904B		JMP_1 <BB#48>
	    Successors according to CFG: BB#48
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EDI<def> = MOV32rm %RAX<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos531]
> %RSI<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RSI<def,tied1> = ADD64ri32 %RSI<kill,tied0>, 1096, %EFLAGS<imp-def,dead>
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EDI<def> = COPY %EDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@BZ2_indexIntoF>, <regmask>, %RSP<imp-use>, %EDI<imp-use>, %RSI<imp-use>, %EAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def> = COPY %EAX
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 9, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %AL, %EAX<imp-use,kill>; mem:ST1[%k1]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 60, %noreg, %RAX<imp-def>; mem:LD4[%tPos536]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RCX<def> = MOV64rm %RCX<kill>, 1, %noreg, 3160, %noreg; mem:LD8[%ll16538]
> %EAX<def> = MOVZX32rm16 %RCX<kill>, 2, %RAX<kill>, 0, %noreg; mem:LD2[%arrayidx539]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RCX<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos541]
> %ECX<def,tied1> = SHR32ri %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> %ECX<def> = MOV32rr %ECX<kill>, %RCX<imp-def>
> %RDX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RDX<def> = MOV64rm %RDX<kill>, 1, %noreg, 3168, %noreg; mem:LD8[%ll4544]
> %EDX<def> = MOVZX32rm8 %RDX<kill>, 1, %RCX<kill>, 0, %noreg; mem:LD1[%arrayidx545]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RCX<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos547]
> %ECX<def,tied1> = SHL32ri %ECX<kill,tied0>, 2, %EFLAGS<imp-def,dead>
> %ECX<def,tied1> = AND32ri8 %ECX<kill,tied0>, 4, %EFLAGS<imp-def,dead>
> %ECX<def> = COPY %ECX<kill>
Deleting identity copy.
> %CL<def> = KILL %ECX
> %EDX<def,tied1> = SHR32rCL %EDX<kill,tied0>, %EFLAGS<imp-def,dead>, %CL<imp-use>
> %EDX<def,tied1> = AND32ri8 %EDX<kill,tied0>, 15, %EFLAGS<imp-def,dead>
> %EDX<def,tied1> = SHL32ri %EDX<kill,tied0>, 16, %EFLAGS<imp-def,dead>
> %EAX<def,tied1> = OR32rr %EAX<kill,tied0>, %EDX<kill>, %EFLAGS<imp-def,dead>
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mr %RCX<kill>, 1, %noreg, 60, %noreg, %EAX<kill>; mem:ST4[%tPos554]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used555]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 1092, %noreg, %ECX<kill>; mem:ST4[%nblock_used555]
> %EAX<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1]
> %EAX<def,tied1> = ADD32ri8 %EAX<kill,tied0>, 4, %EFLAGS<imp-def,dead>
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mr %RCX<kill>, 1, %noreg, 16, %noreg, %EAX<kill>; mem:ST4[%state_out_len559]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EDI<def> = MOV32rm %RAX<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos560]
> %RSI<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RSI<def,tied1> = ADD64ri32 %RSI<kill,tied0>, 1096, %EFLAGS<imp-def,dead>
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EDI<def> = COPY %EDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@BZ2_indexIntoF>, <regmask>, %RSP<imp-use>, %EDI<imp-use>, %RSI<imp-use>, %EAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def> = COPY %EAX
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 10, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mr %RCX<kill>, 1, %noreg, 64, %noreg, %EAX<kill>; mem:ST4[%k0564]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 60, %noreg, %RAX<imp-def>; mem:LD4[%tPos565]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RCX<def> = MOV64rm %RCX<kill>, 1, %noreg, 3160, %noreg; mem:LD8[%ll16567]
> %EAX<def> = MOVZX32rm16 %RCX<kill>, 2, %RAX<kill>, 0, %noreg; mem:LD2[%arrayidx568]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RCX<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos570]
> %ECX<def,tied1> = SHR32ri %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> %ECX<def> = MOV32rr %ECX<kill>, %RCX<imp-def>
> %RDX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RDX<def> = MOV64rm %RDX<kill>, 1, %noreg, 3168, %noreg; mem:LD8[%ll4573]
> %EDX<def> = MOVZX32rm8 %RDX<kill>, 1, %RCX<kill>, 0, %noreg; mem:LD1[%arrayidx574]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RCX<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos576]
> %ECX<def,tied1> = SHL32ri %ECX<kill,tied0>, 2, %EFLAGS<imp-def,dead>
> %ECX<def,tied1> = AND32ri8 %ECX<kill,tied0>, 4, %EFLAGS<imp-def,dead>
> %ECX<def> = COPY %ECX<kill>
Deleting identity copy.
> %CL<def> = KILL %ECX
> %EDX<def,tied1> = SHR32rCL %EDX<kill,tied0>, %EFLAGS<imp-def,dead>, %CL<imp-use>
> %EDX<def,tied1> = AND32ri8 %EDX<kill,tied0>, 15, %EFLAGS<imp-def,dead>
> %EDX<def,tied1> = SHL32ri %EDX<kill,tied0>, 16, %EFLAGS<imp-def,dead>
> %EAX<def,tied1> = OR32rr %EAX<kill,tied0>, %EDX<kill>, %EFLAGS<imp-def,dead>
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mr %RCX<kill>, 1, %noreg, 60, %noreg, %EAX<kill>; mem:ST4[%tPos583]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used584]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 1092, %noreg, %ECX<kill>; mem:ST4[%nblock_used584]
> JMP_1 <BB#48>
17920B	BB#73: derived from LLVM BB %return
	    Predecessors according to CFG: BB#59 BB#57 BB#50 BB#13 BB#11 BB#4
17936B		%vreg1268<def> = MOV64ri <ga:@unRLE_obuf_to_output_SMALL>; GR64:%vreg1268
17968B		%vreg1269<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg1269
17984B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
18000B		%RDI<def> = COPY %vreg1268<kill>; GR64:%vreg1268
18016B		%RSI<def> = COPY %vreg1269<kill>; GR64:%vreg1269
18032B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
18048B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
18064B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
18080B		STACKMAP 11, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=1)
18096B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
18112B		%vreg1266<def> = MOV8rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD1[%retval] GR8:%vreg1266
18128B		%AL<def> = COPY %vreg1266<kill>; GR8:%vreg1266
18144B		RETQ %AL<imp-use>
> %RDI<def> = MOV64ri <ga:@unRLE_obuf_to_output_SMALL>
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 11, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=1)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %AL<def> = MOV8rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD1[%retval]
> %AL<def> = COPY %AL<kill>
Deleting identity copy.
> RETQ %AL<imp-use>
Computing live-in reg-units in ABI blocks.
0B	BB#0 DIL#0
Created 1 new intervals.
********** INTERVALS **********
DIL [0B,16r:0)[112r,144r:2)[13680r,13712r:1)  0@0B-phi 1@13680r 2@112r
%vreg0 [16r,32r:0)  0@16r
%vreg1 [32r,224r:0)  0@32r
%vreg4 [240r,256r:0)  0@240r
%vreg5 [48r,64r:0)  0@48r
%vreg6 [64r,112r:0)  0@64r
%vreg7 [80r,128r:0)  0@80r
%vreg10 [8832r,8848r:0)[8848r,8864r:1)  0@8832r 1@8848r
%vreg12 [8816r,8832r:0)  0@8816r
%vreg13 [8800r,8816r:0)  0@8800r
%vreg15 [8768r,8784r:0)  0@8768r
%vreg18 [8736r,8752r:0)  0@8736r
%vreg20 [8720r,8736r:0)  0@8720r
%vreg21 [8704r,8720r:0)  0@8704r
%vreg24 [8672r,8688r:0)  0@8672r
%vreg26 [8656r,8672r:0)  0@8656r
%vreg27 [8640r,8656r:0)  0@8640r
%vreg30 [8608r,8624r:0)  0@8608r
%vreg31 [8592r,8608r:0)  0@8592r
%vreg34 [8560r,8576r:0)  0@8560r
%vreg35 [8544r,8560r:0)  0@8544r
%vreg38 [8512r,8528r:0)  0@8512r
%vreg39 [8496r,8512r:0)  0@8496r
%vreg42 [8464r,8480r:0)  0@8464r
%vreg43 [8448r,8464r:0)  0@8448r
%vreg46 [8416r,8432r:0)  0@8416r
%vreg47 [8400r,8416r:0)  0@8400r
%vreg50 [8368r,8384r:0)  0@8368r
%vreg51 [8352r,8368r:0)  0@8352r
%vreg54 [8320r,8336r:0)  0@8320r
%vreg55 [8304r,8320r:0)  0@8304r
%vreg61 [9552r,9568r:0)[9568r,9584r:1)  0@9552r 1@9568r
%vreg62 [9536r,9552r:0)  0@9536r
%vreg65 [9488r,9504r:0)[9504r,9520r:1)  0@9488r 1@9504r
%vreg66 [9472r,9488r:0)  0@9472r
%vreg69 [9424r,9440r:0)[9440r,9456r:1)  0@9424r 1@9440r
%vreg70 [9408r,9424r:0)  0@9408r
%vreg74 [9360r,9376r:0)[9376r,9392r:1)  0@9360r 1@9376r
%vreg77 [9328r,9344r:0)  0@9328r
%vreg78 [9344r,9376r:0)  0@9344r
%vreg81 [9296r,9312r:0)[9312r,9328r:1)  0@9296r 1@9312r
%vreg83 [9280r,9312r:0)  0@9280r
%vreg85 [9248r,9264r:0)[9264r,9296r:1)  0@9248r 1@9264r
%vreg86 [9232r,9248r:0)  0@9232r
%vreg88 [9200r,9216r:0)[9216r,9360r:1)  0@9200r 1@9216r
%vreg89 [9184r,9200r:0)  0@9184r
%vreg92 [9152r,9168r:0)  0@9152r
%vreg93 [9136r,9168r:0)  0@9136r
%vreg97 [10112r,10128r:0)[10128r,10144r:1)  0@10112r 1@10128r
%vreg98 [10096r,10112r:0)  0@10096r
%vreg101 [10048r,10064r:0)[10064r,10080r:1)  0@10048r 1@10064r
%vreg102 [10032r,10048r:0)  0@10032r
%vreg106 [9984r,10000r:0)[10000r,10016r:1)  0@9984r 1@10000r
%vreg109 [9952r,9968r:0)  0@9952r
%vreg110 [9968r,10000r:0)  0@9968r
%vreg113 [9920r,9936r:0)[9936r,9952r:1)  0@9920r 1@9936r
%vreg115 [9904r,9936r:0)  0@9904r
%vreg117 [9872r,9888r:0)[9888r,9920r:1)  0@9872r 1@9888r
%vreg118 [9856r,9872r:0)  0@9856r
%vreg120 [9824r,9840r:0)[9840r,9984r:1)  0@9824r 1@9840r
%vreg121 [9808r,9824r:0)  0@9808r
%vreg124 [9776r,9792r:0)  0@9776r
%vreg125 [9760r,9792r:0)  0@9760r
%vreg128 [10176r,10192r:0)  0@10176r
%vreg131 [10288r,10304r:0)  0@10288r
%vreg135 [10736r,10752r:0)  0@10736r
%vreg138 [10688r,10704r:0)[10704r,10720r:1)  0@10688r 1@10704r
%vreg139 [10672r,10688r:0)  0@10672r
%vreg142 [10624r,10640r:0)[10640r,10656r:1)  0@10624r 1@10640r
%vreg143 [10608r,10624r:0)  0@10608r
%vreg146 [10576r,10592r:0)  0@10576r
%vreg148 [10544r,10560r:0)[10560r,10576r:1)  0@10544r 1@10560r
%vreg149 [10528r,10544r:0)  0@10528r
%vreg153 [10496r,10512r:0)  0@10496r
%vreg154 [10480r,10496r:0)  0@10480r
%vreg156 [10448r,10464r:0)  0@10448r
%vreg157 [10464r,10496r:0)  0@10464r
%vreg160 [10416r,10432r:0)  0@10416r
%vreg161 [10400r,10416r:0)  0@10400r
%vreg164 [10864r,10880r:0)  0@10864r
%vreg167 [11264r,11280r:0)  0@11264r
%vreg170 [11216r,11232r:0)[11232r,11248r:1)  0@11216r 1@11232r
%vreg171 [11200r,11216r:0)  0@11200r
%vreg174 [11152r,11168r:0)[11168r,11184r:1)  0@11152r 1@11168r
%vreg175 [11136r,11152r:0)  0@11136r
%vreg178 [11104r,11120r:0)  0@11104r
%vreg180 [11072r,11088r:0)[11088r,11104r:1)  0@11072r 1@11088r
%vreg181 [11056r,11072r:0)  0@11056r
%vreg185 [11024r,11040r:0)  0@11024r
%vreg186 [11008r,11024r:0)  0@11008r
%vreg188 [10976r,10992r:0)  0@10976r
%vreg189 [10992r,11024r:0)  0@10992r
%vreg193 [11360r,11376r:0)  0@11360r
%vreg196 [11792r,11808r:0)  0@11792r
%vreg199 [11744r,11760r:0)[11760r,11776r:1)  0@11744r 1@11760r
%vreg200 [11728r,11744r:0)  0@11728r
%vreg203 [11680r,11696r:0)[11696r,11712r:1)  0@11680r 1@11696r
%vreg204 [11664r,11680r:0)  0@11664r
%vreg207 [11632r,11648r:0)  0@11632r
%vreg209 [11600r,11616r:0)[11616r,11632r:1)  0@11600r 1@11616r
%vreg210 [11584r,11600r:0)  0@11584r
%vreg214 [11552r,11568r:0)  0@11552r
%vreg215 [11536r,11552r:0)  0@11536r
%vreg217 [11504r,11520r:0)  0@11504r
%vreg218 [11520r,11552r:0)  0@11520r
%vreg222 [11888r,11904r:0)  0@11888r
%vreg225 [12624r,12640r:0)[12640r,12656r:1)  0@12624r 1@12640r
%vreg226 [12608r,12624r:0)  0@12608r
%vreg229 [12560r,12576r:0)[12576r,12592r:1)  0@12560r 1@12576r
%vreg230 [12544r,12560r:0)  0@12544r
%vreg233 [12512r,12528r:0)  0@12512r
%vreg235 [12496r,12512r:0)  0@12496r
%vreg237 [12464r,12480r:0)[12480r,12496r:1)  0@12464r 1@12480r
%vreg238 [12448r,12464r:0)  0@12448r
%vreg242 [12416r,12432r:0)  0@12416r
%vreg243 [12400r,12416r:0)  0@12400r
%vreg245 [12368r,12384r:0)  0@12368r
%vreg246 [12384r,12416r:0)  0@12384r
%vreg249 [12320r,12336r:0)[12336r,12352r:1)  0@12320r 1@12336r
%vreg251 [12304r,12320r:0)  0@12304r
%vreg254 [12256r,12272r:0)[12272r,12288r:1)  0@12256r 1@12272r
%vreg255 [12240r,12256r:0)  0@12240r
%vreg258 [12192r,12208r:0)[12208r,12224r:1)  0@12192r 1@12208r
%vreg259 [12176r,12192r:0)  0@12176r
%vreg262 [12144r,12160r:0)  0@12144r
%vreg264 [12112r,12128r:0)[12128r,12144r:1)  0@12112r 1@12128r
%vreg265 [12096r,12112r:0)  0@12096r
%vreg269 [12064r,12080r:0)  0@12064r
%vreg270 [12048r,12064r:0)  0@12048r
%vreg272 [12016r,12032r:0)  0@12016r
%vreg273 [12032r,12064r:0)  0@12032r
%vreg276 [11952r,11968r:0)  0@11952r
%vreg279 [11424r,11440r:0)  0@11424r
%vreg282 [10800r,10816r:0)  0@10800r
%vreg286 [12928r,12944r:0)  0@12928r
%vreg288 [12912r,12928r:0)  0@12912r
%vreg289 [12896r,12912r:0)  0@12896r
%vreg294 [12848r,12864r:0)[12864r,12880r:1)  0@12848r 1@12864r
%vreg296 [12832r,12880r:0)  0@12832r
%vreg297 [12816r,12832r:0)  0@12816r
%vreg300 [12784r,12800r:0)[12800r,12848r:1)  0@12784r 1@12800r
%vreg301 [12768r,12784r:0)  0@12768r
%vreg304 [12736r,12752r:0)  0@12736r
%vreg306 [12720r,12736r:0)  0@12720r
%vreg307 [12704r,12720r:0)  0@12704r
%vreg311 [13040r,13056r:0)[13056r,13072r:1)  0@13040r 1@13056r
%vreg312 [13024r,13040r:0)  0@13024r
%vreg314 [13008r,13072r:0)  0@13008r
%vreg315 [12992r,13008r:0)  0@12992r
%vreg319 [13536r,13552r:0)  0@13536r
%vreg320 [13520r,13536r:0)  0@13520r
%vreg321 [13504r,13552r:0)  0@13504r
%vreg325 [13472r,13488r:0)  0@13472r
%vreg326 [13456r,13472r:0)  0@13456r
%vreg327 [13440r,13488r:0)  0@13440r
%vreg330 [13408r,13424r:0)  0@13408r
%vreg331 [13392r,13424r:0)  0@13392r
%vreg334 [13360r,13376r:0)  0@13360r
%vreg335 [13344r,13376r:0)  0@13344r
%vreg338 [13312r,13328r:0)  0@13312r
%vreg339 [13296r,13328r:0)  0@13296r
%vreg342 [13264r,13280r:0)  0@13264r
%vreg343 [13248r,13280r:0)  0@13248r
%vreg346 [13216r,13232r:0)  0@13216r
%vreg347 [13200r,13232r:0)  0@13200r
%vreg350 [13168r,13184r:0)  0@13168r
%vreg351 [13152r,13184r:0)  0@13152r
%vreg354 [13120r,13136r:0)  0@13120r
%vreg355 [13104r,13136r:0)  0@13104r
%vreg359 [384r,400r:0)  0@384r
%vreg360 [368r,384r:0)  0@368r
%vreg363 [496r,512r:0)  0@496r
%vreg367 [1360r,1376r:0)  0@1360r
%vreg368 [1344r,1360r:0)  0@1344r
%vreg372 [1296r,1312r:0)[1312r,1328r:1)  0@1296r 1@1312r
%vreg373 [1280r,1296r:0)  0@1280r
%vreg375 [1264r,1328r:0)  0@1264r
%vreg376 [1248r,1264r:0)  0@1248r
%vreg380 [1200r,1216r:0)[1216r,1232r:1)  0@1200r 1@1216r
%vreg381 [1184r,1200r:0)  0@1184r
%vreg383 [1168r,1232r:0)  0@1168r
%vreg384 [1152r,1168r:0)  0@1152r
%vreg388 [1104r,1120r:0)[1120r,1136r:1)  0@1104r 1@1120r
%vreg389 [1088r,1104r:0)  0@1088r
%vreg391 [1072r,1136r:0)  0@1072r
%vreg392 [1056r,1072r:0)  0@1056r
%vreg396 [1008r,1024r:0)[1024r,1040r:1)  0@1008r 1@1024r
%vreg397 [992r,1008r:0)  0@992r
%vreg398 [976r,1040r:0)  0@976r
%vreg401 [944r,960r:0)  0@944r
%vreg404 [912r,928r:0)[928r,960r:1)  0@912r 1@928r
%vreg407 [880r,896r:0)  0@880r
%vreg408 [896r,928r:0)  0@896r
%vreg411 [848r,864r:0)[864r,880r:1)  0@848r 1@864r
%vreg413 [832r,864r:0)  0@832r
%vreg415 [816r,832r:0)  0@816r
%vreg417 [784r,800r:0)[800r,848r:1)  0@784r 1@800r
%vreg419 [768r,784r:0)  0@768r
%vreg420 [752r,768r:0)  0@752r
%vreg422 [720r,736r:0)[736r,912r:1)  0@720r 1@736r
%vreg424 [704r,720r:0)  0@704r
%vreg425 [688r,704r:0)  0@688r
%vreg429 [656r,672r:0)  0@656r
%vreg431 [640r,656r:0)  0@640r
%vreg432 [624r,640r:0)  0@624r
%vreg434 [608r,672r:0)  0@608r
%vreg435 [592r,608r:0)  0@592r
%vreg439 [1472r,1488r:0)[1488r,1504r:1)  0@1472r 1@1488r
%vreg440 [1456r,1472r:0)  0@1456r
%vreg442 [1440r,1504r:0)  0@1440r
%vreg443 [1424r,1440r:0)  0@1424r
%vreg447 [1632r,1648r:0)[1648r,1664r:1)  0@1632r 1@1648r
%vreg449 [1616r,1632r:0)  0@1616r
%vreg450 [1600r,1616r:0)  0@1600r
%vreg452 [1584r,1664r:0)  0@1584r
%vreg453 [1568r,1584r:0)  0@1568r
%vreg457 [1824r,1840r:0)[1840r,1856r:1)  0@1824r 1@1840r
%vreg459 [1808r,1824r:0)  0@1808r
%vreg460 [1792r,1808r:0)  0@1792r
%vreg462 [1776r,1856r:0)  0@1776r
%vreg463 [1760r,1776r:0)  0@1760r
%vreg466 [2368r,2384r:0)  0@2368r
%vreg470 [2320r,2336r:0)[2336r,2352r:1)  0@2320r 1@2336r
%vreg471 [2304r,2320r:0)  0@2304r
%vreg472 [2288r,2352r:0)  0@2288r
%vreg475 [2256r,2272r:0)  0@2256r
%vreg477 [2224r,2240r:0)[2240r,2256r:1)  0@2224r 1@2240r
%vreg479 [2208r,2224r:0)  0@2208r
%vreg480 [2192r,2208r:0)  0@2192r
%vreg483 [2160r,2176r:0)  0@2160r
%vreg486 [2144r,2176r:0)  0@2144r
%vreg488 [2128r,2144r:0)  0@2128r
%vreg489 [2112r,2128r:0)  0@2112r
%vreg491 [2080r,2096r:0)  0@2080r
%vreg492 [2096r,2144r:0)  0@2096r
%vreg494 [2064r,2080r:0)  0@2064r
%vreg497 [2032r,2048r:0)  0@2032r
%vreg499 [2016r,2048r:0)  0@2016r
%vreg501 [2000r,2016r:0)  0@2000r
%vreg502 [1984r,2000r:0)  0@1984r
%vreg504 [1952r,1968r:0)  0@1952r
%vreg507 [2592r,2608r:0)  0@2592r
%vreg511 [2544r,2560r:0)[2560r,2576r:1)  0@2544r 1@2560r
%vreg512 [2528r,2544r:0)  0@2528r
%vreg513 [2512r,2576r:0)  0@2512r
%vreg516 [2480r,2496r:0)  0@2480r
%vreg518 [2464r,2496r:0)  0@2464r
%vreg520 [2448r,2464r:0)  0@2448r
%vreg522 [2432r,2448r:0)  0@2432r
%vreg524 [2656r,2672r:0)  0@2656r
%vreg528 [3136r,3152r:0)[3152r,3168r:1)  0@3136r 1@3152r
%vreg530 [3120r,3136r:0)  0@3120r
%vreg531 [3104r,3120r:0)  0@3104r
%vreg533 [3088r,3168r:0)  0@3088r
%vreg534 [3072r,3088r:0)  0@3072r
%vreg538 [3024r,3040r:0)[3040r,3056r:1)  0@3024r 1@3040r
%vreg539 [3008r,3024r:0)  0@3008r
%vreg540 [2992r,3056r:0)  0@2992r
%vreg543 [2960r,2976r:0)  0@2960r
%vreg546 [2928r,2944r:0)[2944r,2960r:1)  0@2928r 1@2944r
%vreg548 [2912r,2928r:0)  0@2912r
%vreg550 [2736r,2880r:0)  0@2736r
%vreg551 [2752r,2896r:0)  0@2752r
%vreg552 [2880r,2896r:0)[2896r,2944r:1)  0@2880r 1@2896r
%vreg554 [2848r,2864r:0)  0@2848r
%vreg558 [2800r,2816r:0)[2816r,2832r:1)  0@2800r 1@2816r
%vreg559 [2784r,2800r:0)  0@2784r
%vreg560 [2768r,2832r:0)  0@2768r
%vreg564 [3264r,3280r:0)  0@3264r
%vreg566 [3248r,3280r:0)  0@3248r
%vreg569 [3744r,3760r:0)  0@3744r
%vreg573 [3696r,3712r:0)[3712r,3728r:1)  0@3696r 1@3712r
%vreg574 [3680r,3696r:0)  0@3680r
%vreg575 [3664r,3728r:0)  0@3664r
%vreg578 [3632r,3648r:0)  0@3632r
%vreg580 [3600r,3616r:0)[3616r,3632r:1)  0@3600r 1@3616r
%vreg582 [3584r,3600r:0)  0@3584r
%vreg583 [3568r,3584r:0)  0@3568r
%vreg586 [3536r,3552r:0)  0@3536r
%vreg589 [3520r,3552r:0)  0@3520r
%vreg591 [3504r,3520r:0)  0@3504r
%vreg592 [3488r,3504r:0)  0@3488r
%vreg594 [3456r,3472r:0)  0@3456r
%vreg595 [3472r,3520r:0)  0@3472r
%vreg597 [3440r,3456r:0)  0@3440r
%vreg599 [3408r,3424r:0)  0@3408r
%vreg602 [3968r,3984r:0)  0@3968r
%vreg606 [3920r,3936r:0)[3936r,3952r:1)  0@3920r 1@3936r
%vreg607 [3904r,3920r:0)  0@3904r
%vreg608 [3888r,3952r:0)  0@3888r
%vreg611 [3856r,3872r:0)  0@3856r
%vreg613 [3840r,3872r:0)  0@3840r
%vreg615 [3824r,3840r:0)  0@3824r
%vreg617 [3808r,3824r:0)  0@3808r
%vreg619 [4032r,4048r:0)  0@4032r
%vreg623 [4512r,4528r:0)[4528r,4544r:1)  0@4512r 1@4528r
%vreg625 [4496r,4512r:0)  0@4496r
%vreg626 [4480r,4496r:0)  0@4480r
%vreg628 [4464r,4544r:0)  0@4464r
%vreg629 [4448r,4464r:0)  0@4448r
%vreg633 [4400r,4416r:0)[4416r,4432r:1)  0@4400r 1@4416r
%vreg634 [4384r,4400r:0)  0@4384r
%vreg635 [4368r,4432r:0)  0@4368r
%vreg638 [4336r,4352r:0)  0@4336r
%vreg641 [4304r,4320r:0)[4320r,4336r:1)  0@4304r 1@4320r
%vreg643 [4288r,4304r:0)  0@4288r
%vreg645 [4112r,4256r:0)  0@4112r
%vreg646 [4128r,4272r:0)  0@4128r
%vreg647 [4256r,4272r:0)[4272r,4320r:1)  0@4256r 1@4272r
%vreg649 [4224r,4240r:0)  0@4224r
%vreg653 [4176r,4192r:0)[4192r,4208r:1)  0@4176r 1@4192r
%vreg654 [4160r,4176r:0)  0@4160r
%vreg655 [4144r,4208r:0)  0@4144r
%vreg659 [4640r,4656r:0)  0@4640r
%vreg661 [4624r,4656r:0)  0@4624r
%vreg664 [5120r,5136r:0)  0@5120r
%vreg668 [5072r,5088r:0)[5088r,5104r:1)  0@5072r 1@5088r
%vreg669 [5056r,5072r:0)  0@5056r
%vreg670 [5040r,5104r:0)  0@5040r
%vreg673 [5008r,5024r:0)  0@5008r
%vreg675 [4976r,4992r:0)[4992r,5008r:1)  0@4976r 1@4992r
%vreg677 [4960r,4976r:0)  0@4960r
%vreg678 [4944r,4960r:0)  0@4944r
%vreg681 [4912r,4928r:0)  0@4912r
%vreg684 [4896r,4928r:0)  0@4896r
%vreg686 [4880r,4896r:0)  0@4880r
%vreg687 [4864r,4880r:0)  0@4864r
%vreg689 [4832r,4848r:0)  0@4832r
%vreg690 [4848r,4896r:0)  0@4848r
%vreg692 [4816r,4832r:0)  0@4816r
%vreg694 [4784r,4800r:0)  0@4784r
%vreg697 [5344r,5360r:0)  0@5344r
%vreg701 [5296r,5312r:0)[5312r,5328r:1)  0@5296r 1@5312r
%vreg702 [5280r,5296r:0)  0@5280r
%vreg703 [5264r,5328r:0)  0@5264r
%vreg706 [5232r,5248r:0)  0@5232r
%vreg708 [5216r,5248r:0)  0@5216r
%vreg710 [5200r,5216r:0)  0@5200r
%vreg712 [5184r,5200r:0)  0@5184r
%vreg714 [5408r,5424r:0)  0@5408r
%vreg718 [5888r,5904r:0)[5904r,5920r:1)  0@5888r 1@5904r
%vreg720 [5872r,5888r:0)  0@5872r
%vreg721 [5856r,5872r:0)  0@5856r
%vreg723 [5840r,5920r:0)  0@5840r
%vreg724 [5824r,5840r:0)  0@5824r
%vreg728 [5776r,5792r:0)[5792r,5808r:1)  0@5776r 1@5792r
%vreg729 [5760r,5776r:0)  0@5760r
%vreg730 [5744r,5808r:0)  0@5744r
%vreg733 [5712r,5728r:0)  0@5712r
%vreg736 [5680r,5696r:0)[5696r,5712r:1)  0@5680r 1@5696r
%vreg738 [5664r,5680r:0)  0@5664r
%vreg740 [5488r,5632r:0)  0@5488r
%vreg741 [5504r,5648r:0)  0@5504r
%vreg742 [5632r,5648r:0)[5648r,5696r:1)  0@5632r 1@5648r
%vreg744 [5600r,5616r:0)  0@5600r
%vreg748 [5552r,5568r:0)[5568r,5584r:1)  0@5552r 1@5568r
%vreg749 [5536r,5552r:0)  0@5536r
%vreg750 [5520r,5584r:0)  0@5520r
%vreg754 [6016r,6032r:0)  0@6016r
%vreg756 [6000r,6032r:0)  0@6000r
%vreg759 [6464r,6480r:0)  0@6464r
%vreg763 [6416r,6432r:0)[6432r,6448r:1)  0@6416r 1@6432r
%vreg764 [6400r,6416r:0)  0@6400r
%vreg765 [6384r,6448r:0)  0@6384r
%vreg768 [6352r,6368r:0)  0@6352r
%vreg770 [6320r,6336r:0)[6336r,6352r:1)  0@6320r 1@6336r
%vreg772 [6304r,6320r:0)  0@6304r
%vreg773 [6288r,6304r:0)  0@6288r
%vreg776 [6256r,6272r:0)  0@6256r
%vreg779 [6240r,6272r:0)  0@6240r
%vreg781 [6224r,6240r:0)  0@6224r
%vreg782 [6208r,6224r:0)  0@6208r
%vreg784 [6176r,6192r:0)  0@6176r
%vreg785 [6192r,6240r:0)  0@6192r
%vreg787 [6160r,6176r:0)  0@6160r
%vreg790 [6688r,6704r:0)  0@6688r
%vreg794 [6640r,6656r:0)[6656r,6672r:1)  0@6640r 1@6656r
%vreg795 [6624r,6640r:0)  0@6624r
%vreg796 [6608r,6672r:0)  0@6608r
%vreg799 [6576r,6592r:0)  0@6576r
%vreg801 [6560r,6592r:0)  0@6560r
%vreg803 [6544r,6560r:0)  0@6544r
%vreg805 [6528r,6544r:0)  0@6528r
%vreg807 [6752r,6768r:0)  0@6752r
%vreg810 [7584r,7600r:0)  0@7584r
%vreg814 [7536r,7552r:0)[7552r,7568r:1)  0@7536r 1@7552r
%vreg815 [7520r,7536r:0)  0@7520r
%vreg816 [7504r,7568r:0)  0@7504r
%vreg819 [7472r,7488r:0)  0@7472r
%vreg821 [7456r,7488r:0)  0@7456r
%vreg823 [7440r,7456r:0)  0@7440r
%vreg825 [7408r,7424r:0)[7424r,7440r:1)  0@7408r 1@7424r
%vreg827 [7392r,7408r:0)  0@7392r
%vreg828 [7376r,7392r:0)  0@7376r
%vreg831 [7344r,7360r:0)  0@7344r
%vreg834 [7328r,7360r:0)  0@7328r
%vreg836 [7312r,7328r:0)  0@7312r
%vreg837 [7296r,7312r:0)  0@7296r
%vreg839 [7264r,7280r:0)  0@7264r
%vreg840 [7280r,7328r:0)  0@7280r
%vreg842 [7248r,7264r:0)  0@7248r
%vreg845 [7216r,7232r:0)  0@7216r
%vreg847 [7184r,7200r:0)[7200r,7232r:1)  0@7184r 1@7200r
%vreg849 [7168r,7184r:0)  0@7168r
%vreg853 [7120r,7136r:0)[7136r,7152r:1)  0@7120r 1@7136r
%vreg854 [7104r,7120r:0)  0@7104r
%vreg855 [7088r,7152r:0)  0@7088r
%vreg858 [7056r,7072r:0)  0@7056r
%vreg861 [7024r,7040r:0)[7040r,7056r:1)  0@7024r 1@7040r
%vreg863 [7008r,7024r:0)  0@7008r
%vreg865 [6832r,6976r:0)  0@6832r
%vreg866 [6848r,6992r:0)  0@6848r
%vreg867 [6976r,6992r:0)[6992r,7040r:1)  0@6976r 1@6992r
%vreg869 [6944r,6960r:0)  0@6944r
%vreg873 [6896r,6912r:0)[6912r,6928r:1)  0@6896r 1@6912r
%vreg874 [6880r,6896r:0)  0@6880r
%vreg875 [6864r,6928r:0)  0@6864r
%vreg878 [7808r,7824r:0)  0@7808r
%vreg882 [7760r,7776r:0)[7776r,7792r:1)  0@7760r 1@7776r
%vreg883 [7744r,7760r:0)  0@7744r
%vreg884 [7728r,7792r:0)  0@7728r
%vreg887 [7696r,7712r:0)  0@7696r
%vreg889 [7680r,7712r:0)  0@7680r
%vreg891 [7664r,7680r:0)  0@7664r
%vreg893 [7648r,7664r:0)  0@7648r
%vreg895 [7872r,7888r:0)  0@7872r
%vreg899 [8224r,8240r:0)[8240r,8256r:1)  0@8224r 1@8240r
%vreg900 [8208r,8224r:0)  0@8208r
%vreg901 [8192r,8256r:0)  0@8192r
%vreg906 [8144r,8160r:0)[8160r,8176r:1)  0@8144r 1@8160r
%vreg907 [8128r,8176r:0)  0@8128r
%vreg909 [7952r,8096r:0)  0@7952r
%vreg910 [7968r,8112r:0)  0@7968r
%vreg911 [8096r,8112r:0)[8112r,8144r:1)  0@8096r 1@8112r
%vreg913 [8064r,8080r:0)  0@8064r
%vreg917 [8016r,8032r:0)[8032r,8048r:1)  0@8016r 1@8032r
%vreg918 [8000r,8016r:0)  0@8000r
%vreg919 [7984r,8048r:0)  0@7984r
%vreg922 [6096r,6112r:0)  0@6096r
%vreg924 [6080r,6112r:0)  0@6080r
%vreg927 [4720r,4736r:0)  0@4720r
%vreg929 [4704r,4736r:0)  0@4704r
%vreg932 [3344r,3360r:0)  0@3344r
%vreg934 [3328r,3360r:0)  0@3328r
%vreg936 [13792r,13808r:0)  0@13792r
%vreg937 [13616r,13632r:0)  0@13616r
%vreg938 [13632r,13680r:0)  0@13632r
%vreg939 [13648r,13696r:0)  0@13648r
RegMasks: 144r 13712r
********** MACHINEINSTRS **********
# Machine code for function unRLE_obuf_to_output_FAST: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=1, align=1, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=1, align=1, at location [SP+8]
  fi#3: size=4, align=4, at location [SP+8]
  fi#4: size=1, align=1, at location [SP+8]
  fi#5: size=4, align=4, at location [SP+8]
  fi#6: size=4, align=4, at location [SP+8]
  fi#7: size=4, align=4, at location [SP+8]
  fi#8: size=8, align=8, at location [SP+8]
  fi#9: size=4, align=4, at location [SP+8]
  fi#10: size=8, align=8, at location [SP+8]
  fi#11: size=4, align=4, at location [SP+8]
  fi#12: size=4, align=4, at location [SP+8]
  fi#13: size=4, align=4, at location [SP+8]
  fi#14: size=4, align=4, at location [SP+8]
Function Live Ins: %RDI in %vreg0

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI
16B		%vreg0<def> = COPY %RDI; GR64:%vreg0
32B		%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
48B		%vreg5<def> = MOV64ri <ga:@unRLE_obuf_to_output_FAST>; GR64:%vreg5
64B		%vreg6<def> = COPY %vreg5; GR64:%vreg6,%vreg5
80B		%vreg7<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg7
96B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
112B		%RDI<def> = COPY %vreg6; GR64:%vreg6
128B		%RSI<def> = COPY %vreg7; GR64:%vreg7
144B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
160B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
192B		STACKMAP 0, 0, 0, <fi#12>, 0, 0, <fi#3>, 0, 0, <fi#7>, 0, 0, <fi#6>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#9>, 0, 0, <fi#8>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, %vreg1, 0, <fi#1>, 0, 0, <fi#13>, 0, 0, <fi#14>, 0, ...; mem:LD8[FixedStack12](align=4) LD8[FixedStack3](align=4) LD8[FixedStack7](align=4) LD8[FixedStack6](align=4) LD8[FixedStack4](align=1) LD8[FixedStack5](align=4) LD8[FixedStack9](align=4) LD8[FixedStack8] LD8[FixedStack11](align=4) LD8[FixedStack10] LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1] LD8[FixedStack13](align=4) LD8[FixedStack14](align=4) GR64:%vreg1
208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%s.addr] GR64:%vreg1
240B		%vreg4<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg4
256B		CMP8mi %vreg4, 1, %noreg, 20, %noreg, 0, %EFLAGS<imp-def>; mem:LD1[%blockRandomised] GR64:%vreg4
272B		JE_1 <BB#47>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#47 BB#1

288B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
304B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2

320B	BB#2: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#1 BB#46 BB#37 BB#35 BB#29 BB#27 BB#21 BB#19
336B		JMP_1 <BB#3>
	    Successors according to CFG: BB#3

352B	BB#3: derived from LLVM BB %while.body.2
	    Predecessors according to CFG: BB#2 BB#9
368B		%vreg360<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg360
384B		%vreg359<def> = MOV64rm %vreg360, 1, %noreg, 0, %noreg; mem:LD8[%strm] GR64:%vreg359,%vreg360
400B		CMP32mi8 %vreg359, 1, %noreg, 32, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_out] GR64:%vreg359
416B		JNE_1 <BB#5>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#5 BB#4

432B	BB#4: derived from LLVM BB %if.then.3
	    Predecessors according to CFG: BB#3
448B		MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST1[%retval]
464B		JMP_1 <BB#80>
	    Successors according to CFG: BB#80

480B	BB#5: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#3
496B		%vreg363<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg363
512B		CMP32mi8 %vreg363, 1, %noreg, 16, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%state_out_len] GR64:%vreg363
528B		JNE_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#6

544B	BB#6: derived from LLVM BB %if.then.5
	    Predecessors according to CFG: BB#5
560B		JMP_1 <BB#10>
	    Successors according to CFG: BB#10

576B	BB#7: derived from LLVM BB %if.end.6
	    Predecessors according to CFG: BB#5
592B		%vreg435<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg435
608B		%vreg434<def> = MOV8rm %vreg435, 1, %noreg, 12, %noreg; mem:LD1[%state_out_ch] GR8:%vreg434 GR64:%vreg435
624B		%vreg432<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg432
640B		%vreg431<def> = MOV64rm %vreg432, 1, %noreg, 0, %noreg; mem:LD8[%strm7] GR64:%vreg431,%vreg432
656B		%vreg429<def> = MOV64rm %vreg431, 1, %noreg, 24, %noreg; mem:LD8[%next_out] GR64:%vreg429,%vreg431
672B		MOV8mr %vreg429, 1, %noreg, 0, %noreg, %vreg434; mem:ST1[%11] GR64:%vreg429 GR8:%vreg434
688B		%vreg425<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg425
704B		%vreg424<def> = MOV32rm %vreg425, 1, %noreg, 3184, %noreg; mem:LD4[%calculatedBlockCRC] GR32:%vreg424 GR64:%vreg425
720B		%vreg422<def> = COPY %vreg424; GR32:%vreg422,%vreg424
736B		%vreg422<def,tied1> = SHL32ri %vreg422<tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg422
752B		%vreg420<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg420
768B		%vreg419<def> = MOV32rm %vreg420, 1, %noreg, 3184, %noreg; mem:LD4[%calculatedBlockCRC8] GR32:%vreg419 GR64:%vreg420
784B		%vreg417<def> = COPY %vreg419; GR32:%vreg417,%vreg419
800B		%vreg417<def,tied1> = SHR32ri %vreg417<tied0>, 24, %EFLAGS<imp-def,dead>; GR32:%vreg417
816B		%vreg415<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg415
832B		%vreg413<def> = MOVZX32rm8 %vreg415, 1, %noreg, 12, %noreg; mem:LD1[%state_out_ch9] GR32:%vreg413 GR64:%vreg415
848B		%vreg411<def> = COPY %vreg417; GR32:%vreg411,%vreg417
864B		%vreg411<def,tied1> = XOR32rr %vreg411<tied0>, %vreg413, %EFLAGS<imp-def,dead>; GR32:%vreg411,%vreg413
880B		%vreg407<def> = MOV32rr %vreg411; GR32:%vreg407,%vreg411
896B		%vreg408<def> = SUBREG_TO_REG 0, %vreg407, 4; GR64_NOSP:%vreg408 GR32:%vreg407
912B		%vreg404<def> = COPY %vreg422; GR32:%vreg404,%vreg422
928B		%vreg404<def,tied1> = XOR32rm %vreg404<tied0>, %noreg, 4, %vreg408, <ga:@BZ2_crc32Table>, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%arrayidx] GR32:%vreg404 GR64_NOSP:%vreg408
944B		%vreg401<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg401
960B		MOV32mr %vreg401, 1, %noreg, 3184, %noreg, %vreg404; mem:ST4[%calculatedBlockCRC11] GR64:%vreg401 GR32:%vreg404
976B		%vreg398<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg398
992B		%vreg397<def> = MOV32rm %vreg398, 1, %noreg, 16, %noreg; mem:LD4[%state_out_len12] GR32:%vreg397 GR64:%vreg398
1008B		%vreg396<def> = COPY %vreg397; GR32:%vreg396,%vreg397
1024B		%vreg396<def,tied1> = ADD32ri8 %vreg396<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg396
1040B		MOV32mr %vreg398, 1, %noreg, 16, %noreg, %vreg396; mem:ST4[%state_out_len12] GR64:%vreg398 GR32:%vreg396
1056B		%vreg392<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg392
1072B		%vreg391<def> = MOV64rm %vreg392, 1, %noreg, 0, %noreg; mem:LD8[%strm13] GR64:%vreg391,%vreg392
1088B		%vreg389<def> = MOV64rm %vreg391, 1, %noreg, 24, %noreg; mem:LD8[%next_out14] GR64:%vreg389,%vreg391
1104B		%vreg388<def> = COPY %vreg389; GR64:%vreg388,%vreg389
1120B		%vreg388<def,tied1> = ADD64ri8 %vreg388<tied0>, 1, %EFLAGS<imp-def,dead>; GR64:%vreg388
1136B		MOV64mr %vreg391, 1, %noreg, 24, %noreg, %vreg388; mem:ST8[%next_out14] GR64:%vreg391,%vreg388
1152B		%vreg384<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg384
1168B		%vreg383<def> = MOV64rm %vreg384, 1, %noreg, 0, %noreg; mem:LD8[%strm15] GR64:%vreg383,%vreg384
1184B		%vreg381<def> = MOV32rm %vreg383, 1, %noreg, 32, %noreg; mem:LD4[%avail_out16] GR32:%vreg381 GR64:%vreg383
1200B		%vreg380<def> = COPY %vreg381; GR32:%vreg380,%vreg381
1216B		%vreg380<def,tied1> = ADD32ri8 %vreg380<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg380
1232B		MOV32mr %vreg383, 1, %noreg, 32, %noreg, %vreg380; mem:ST4[%avail_out16] GR64:%vreg383 GR32:%vreg380
1248B		%vreg376<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg376
1264B		%vreg375<def> = MOV64rm %vreg376, 1, %noreg, 0, %noreg; mem:LD8[%strm18] GR64:%vreg375,%vreg376
1280B		%vreg373<def> = MOV32rm %vreg375, 1, %noreg, 36, %noreg; mem:LD4[%total_out_lo32] GR32:%vreg373 GR64:%vreg375
1296B		%vreg372<def> = COPY %vreg373; GR32:%vreg372,%vreg373
1312B		%vreg372<def,tied1> = ADD32ri8 %vreg372<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg372
1328B		MOV32mr %vreg375, 1, %noreg, 36, %noreg, %vreg372; mem:ST4[%total_out_lo32] GR64:%vreg375 GR32:%vreg372
1344B		%vreg368<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg368
1360B		%vreg367<def> = MOV64rm %vreg368, 1, %noreg, 0, %noreg; mem:LD8[%strm19] GR64:%vreg367,%vreg368
1376B		CMP32mi8 %vreg367, 1, %noreg, 36, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%total_out_lo3220] GR64:%vreg367
1392B		JNE_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#8

1408B	BB#8: derived from LLVM BB %if.then.23
	    Predecessors according to CFG: BB#7
1424B		%vreg443<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg443
1440B		%vreg442<def> = MOV64rm %vreg443, 1, %noreg, 0, %noreg; mem:LD8[%strm24] GR64:%vreg442,%vreg443
1456B		%vreg440<def> = MOV32rm %vreg442, 1, %noreg, 40, %noreg; mem:LD4[%total_out_hi32] GR32:%vreg440 GR64:%vreg442
1472B		%vreg439<def> = COPY %vreg440; GR32:%vreg439,%vreg440
1488B		%vreg439<def,tied1> = ADD32ri8 %vreg439<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg439
1504B		MOV32mr %vreg442, 1, %noreg, 40, %noreg, %vreg439; mem:ST4[%total_out_hi32] GR64:%vreg442 GR32:%vreg439
	    Successors according to CFG: BB#9

1520B	BB#9: derived from LLVM BB %if.end.26
	    Predecessors according to CFG: BB#7 BB#8
1536B		JMP_1 <BB#3>
	    Successors according to CFG: BB#3

1552B	BB#10: derived from LLVM BB %while.end
	    Predecessors according to CFG: BB#6
1568B		%vreg453<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg453
1584B		%vreg452<def> = MOV32rm %vreg453, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used] GR32:%vreg452 GR64:%vreg453
1600B		%vreg450<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg450
1616B		%vreg449<def> = MOV32rm %vreg450, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock] GR32:%vreg449 GR64:%vreg450
1632B		%vreg447<def> = COPY %vreg449; GR32:%vreg447,%vreg449
1648B		%vreg447<def,tied1> = ADD32ri8 %vreg447<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg447
1664B		CMP32rr %vreg452, %vreg447, %EFLAGS<imp-def>; GR32:%vreg452,%vreg447
1680B		JNE_1 <BB#12>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#12 BB#11

1696B	BB#11: derived from LLVM BB %if.then.29
	    Predecessors according to CFG: BB#10
1712B		MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST1[%retval]
1728B		JMP_1 <BB#80>
	    Successors according to CFG: BB#80

1744B	BB#12: derived from LLVM BB %if.end.30
	    Predecessors according to CFG: BB#10
1760B		%vreg463<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg463
1776B		%vreg462<def> = MOV32rm %vreg463, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used31] GR32:%vreg462 GR64:%vreg463
1792B		%vreg460<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg460
1808B		%vreg459<def> = MOV32rm %vreg460, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock32] GR32:%vreg459 GR64:%vreg460
1824B		%vreg457<def> = COPY %vreg459; GR32:%vreg457,%vreg459
1840B		%vreg457<def,tied1> = ADD32ri8 %vreg457<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg457
1856B		CMP32rr %vreg462, %vreg457, %EFLAGS<imp-def>; GR32:%vreg462,%vreg457
1872B		JLE_1 <BB#14>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#14 BB#13

1888B	BB#13: derived from LLVM BB %if.then.36
	    Predecessors according to CFG: BB#12
1904B		MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 1; mem:ST1[%retval]
1920B		JMP_1 <BB#80>
	    Successors according to CFG: BB#80

1936B	BB#14: derived from LLVM BB %if.end.37
	    Predecessors according to CFG: BB#12
1952B		%vreg504<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg504
1968B		MOV32mi %vreg504, 1, %noreg, 16, %noreg, 1; mem:ST4[%state_out_len38] GR64:%vreg504
1984B		%vreg502<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg502
2000B		%vreg501<def> = MOV32rm %vreg502, 1, %noreg, 64, %noreg; mem:LD4[%k0] GR32:%vreg501 GR64:%vreg502
2016B		%vreg499<def> = COPY %vreg501:sub_8bit; GR8:%vreg499 GR32:%vreg501
2032B		%vreg497<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg497
2048B		MOV8mr %vreg497, 1, %noreg, 12, %noreg, %vreg499; mem:ST1[%state_out_ch40] GR64:%vreg497 GR8:%vreg499
2064B		%vreg494<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg494
2080B		%vreg491<def> = MOV32rm %vreg494, 1, %noreg, 60, %noreg; mem:LD4[%tPos] GR32:%vreg491 GR64:%vreg494
2096B		%vreg492<def> = SUBREG_TO_REG 0, %vreg491, 4; GR64_NOSP:%vreg492 GR32:%vreg491
2112B		%vreg489<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg489
2128B		%vreg488<def> = MOV64rm %vreg489, 1, %noreg, 3152, %noreg; mem:LD8[%tt] GR64:%vreg488,%vreg489
2144B		%vreg486<def> = MOV32rm %vreg488, 4, %vreg492, 0, %noreg; mem:LD4[%arrayidx42] GR32:%vreg486 GR64:%vreg488 GR64_NOSP:%vreg492
2160B		%vreg483<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg483
2176B		MOV32mr %vreg483, 1, %noreg, 60, %noreg, %vreg486; mem:ST4[%tPos43] GR64:%vreg483 GR32:%vreg486
2192B		%vreg480<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg480
2208B		%vreg479<def> = MOV32rm %vreg480, 1, %noreg, 60, %noreg; mem:LD4[%tPos44] GR32:%vreg479 GR64:%vreg480
2224B		%vreg477<def> = COPY %vreg479; GR32:%vreg477,%vreg479
2240B		%vreg477<def,tied1> = AND32ri %vreg477<tied0>, 255, %EFLAGS<imp-def,dead>; GR32:%vreg477
2256B		%vreg475<def> = COPY %vreg477:sub_8bit; GR8:%vreg475 GR32:%vreg477
2272B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg475; mem:ST1[%k1] GR8:%vreg475
2288B		%vreg472<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg472
2304B		%vreg471<def> = MOV32rm %vreg472, 1, %noreg, 60, %noreg; mem:LD4[%tPos46] GR32:%vreg471 GR64:%vreg472
2320B		%vreg470<def> = COPY %vreg471; GR32:%vreg470,%vreg471
2336B		%vreg470<def,tied1> = SHR32ri %vreg470<tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg470
2352B		MOV32mr %vreg472, 1, %noreg, 60, %noreg, %vreg470; mem:ST4[%tPos46] GR64:%vreg472 GR32:%vreg470
2368B		%vreg466<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg466
2384B		CMP32mi8 %vreg466, 1, %noreg, 24, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%rNToGo] GR64:%vreg466
2400B		JNE_1 <BB#18>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#18 BB#15

2416B	BB#15: derived from LLVM BB %if.then.50
	    Predecessors according to CFG: BB#14
2432B		%vreg522<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg522
2448B		%vreg520<def> = MOVSX64rm32 %vreg522, 1, %noreg, 28, %noreg; mem:LD4[%rTPos] GR64_NOSP:%vreg520 GR64:%vreg522
2464B		%vreg518<def> = MOV32rm %noreg, 4, %vreg520, <ga:@BZ2_rNums>, %noreg; mem:LD4[%arrayidx52] GR32:%vreg518 GR64_NOSP:%vreg520
2480B		%vreg516<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg516
2496B		MOV32mr %vreg516, 1, %noreg, 24, %noreg, %vreg518; mem:ST4[%rNToGo53] GR64:%vreg516 GR32:%vreg518
2512B		%vreg513<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg513
2528B		%vreg512<def> = MOV32rm %vreg513, 1, %noreg, 28, %noreg; mem:LD4[%rTPos54] GR32:%vreg512 GR64:%vreg513
2544B		%vreg511<def> = COPY %vreg512; GR32:%vreg511,%vreg512
2560B		%vreg511<def,tied1> = ADD32ri8 %vreg511<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg511
2576B		MOV32mr %vreg513, 1, %noreg, 28, %noreg, %vreg511; mem:ST4[%rTPos54] GR64:%vreg513 GR32:%vreg511
2592B		%vreg507<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg507
2608B		CMP32mi %vreg507, 1, %noreg, 28, %noreg, 512, %EFLAGS<imp-def>; mem:LD4[%rTPos56] GR64:%vreg507
2624B		JNE_1 <BB#17>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#17 BB#16

2640B	BB#16: derived from LLVM BB %if.then.59
	    Predecessors according to CFG: BB#15
2656B		%vreg524<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg524
2672B		MOV32mi %vreg524, 1, %noreg, 28, %noreg, 0; mem:ST4[%rTPos60] GR64:%vreg524
	    Successors according to CFG: BB#17

2688B	BB#17: derived from LLVM BB %if.end.61
	    Predecessors according to CFG: BB#15 BB#16
2704B		JMP_1 <BB#18>
	    Successors according to CFG: BB#18

2720B	BB#18: derived from LLVM BB %if.end.62
	    Predecessors according to CFG: BB#14 BB#17
2736B		%vreg550<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg550
2752B		%vreg551<def> = MOV32ri 1; GR32:%vreg551
2768B		%vreg560<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg560
2784B		%vreg559<def> = MOV32rm %vreg560, 1, %noreg, 24, %noreg; mem:LD4[%rNToGo63] GR32:%vreg559 GR64:%vreg560
2800B		%vreg558<def> = COPY %vreg559; GR32:%vreg558,%vreg559
2816B		%vreg558<def,tied1> = ADD32ri8 %vreg558<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg558
2832B		MOV32mr %vreg560, 1, %noreg, 24, %noreg, %vreg558; mem:ST4[%rNToGo63] GR64:%vreg560 GR32:%vreg558
2848B		%vreg554<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg554
2864B		CMP32mi8 %vreg554, 1, %noreg, 24, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%rNToGo65] GR64:%vreg554
2880B		%vreg552<def> = COPY %vreg550; GR32:%vreg552,%vreg550
2896B		%vreg552<def,tied1> = CMOVE32rr %vreg552<tied0>, %vreg551, %EFLAGS<imp-use,kill>; GR32:%vreg552,%vreg551
2912B		%vreg548<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg548
2928B		%vreg546<def> = COPY %vreg548; GR32:%vreg546,%vreg548
2944B		%vreg546<def,tied1> = XOR32rr %vreg546<tied0>, %vreg552, %EFLAGS<imp-def,dead>; GR32:%vreg546,%vreg552
2960B		%vreg543<def> = COPY %vreg546:sub_8bit; GR8:%vreg543 GR32:%vreg546
2976B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg543; mem:ST1[%k1] GR8:%vreg543
2992B		%vreg540<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg540
3008B		%vreg539<def> = MOV32rm %vreg540, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used71] GR32:%vreg539 GR64:%vreg540
3024B		%vreg538<def> = COPY %vreg539; GR32:%vreg538,%vreg539
3040B		%vreg538<def,tied1> = ADD32ri8 %vreg538<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg538
3056B		MOV32mr %vreg540, 1, %noreg, 1092, %noreg, %vreg538; mem:ST4[%nblock_used71] GR64:%vreg540 GR32:%vreg538
3072B		%vreg534<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg534
3088B		%vreg533<def> = MOV32rm %vreg534, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used73] GR32:%vreg533 GR64:%vreg534
3104B		%vreg531<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg531
3120B		%vreg530<def> = MOV32rm %vreg531, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock74] GR32:%vreg530 GR64:%vreg531
3136B		%vreg528<def> = COPY %vreg530; GR32:%vreg528,%vreg530
3152B		%vreg528<def,tied1> = ADD32ri8 %vreg528<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg528
3168B		CMP32rr %vreg533, %vreg528, %EFLAGS<imp-def>; GR32:%vreg533,%vreg528
3184B		JNE_1 <BB#20>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#20 BB#19

3200B	BB#19: derived from LLVM BB %if.then.78
	    Predecessors according to CFG: BB#18
3216B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2

3232B	BB#20: derived from LLVM BB %if.end.79
	    Predecessors according to CFG: BB#18
3248B		%vreg566<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg566
3264B		%vreg564<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg564
3280B		CMP32rm %vreg566, %vreg564, 1, %noreg, 64, %noreg, %EFLAGS<imp-def>; mem:LD4[%k081] GR32:%vreg566 GR64:%vreg564
3296B		JE_1 <BB#22>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#22 BB#21

3312B	BB#21: derived from LLVM BB %if.then.84
	    Predecessors according to CFG: BB#20
3328B		%vreg934<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg934
3344B		%vreg932<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg932
3360B		MOV32mr %vreg932, 1, %noreg, 64, %noreg, %vreg934; mem:ST4[%k086] GR64:%vreg932 GR32:%vreg934
3376B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2

3392B	BB#22: derived from LLVM BB %if.end.87
	    Predecessors according to CFG: BB#20
3408B		%vreg599<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg599
3424B		MOV32mi %vreg599, 1, %noreg, 16, %noreg, 2; mem:ST4[%state_out_len88] GR64:%vreg599
3440B		%vreg597<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg597
3456B		%vreg594<def> = MOV32rm %vreg597, 1, %noreg, 60, %noreg; mem:LD4[%tPos89] GR32:%vreg594 GR64:%vreg597
3472B		%vreg595<def> = SUBREG_TO_REG 0, %vreg594, 4; GR64_NOSP:%vreg595 GR32:%vreg594
3488B		%vreg592<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg592
3504B		%vreg591<def> = MOV64rm %vreg592, 1, %noreg, 3152, %noreg; mem:LD8[%tt91] GR64:%vreg591,%vreg592
3520B		%vreg589<def> = MOV32rm %vreg591, 4, %vreg595, 0, %noreg; mem:LD4[%arrayidx92] GR32:%vreg589 GR64:%vreg591 GR64_NOSP:%vreg595
3536B		%vreg586<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg586
3552B		MOV32mr %vreg586, 1, %noreg, 60, %noreg, %vreg589; mem:ST4[%tPos93] GR64:%vreg586 GR32:%vreg589
3568B		%vreg583<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg583
3584B		%vreg582<def> = MOV32rm %vreg583, 1, %noreg, 60, %noreg; mem:LD4[%tPos94] GR32:%vreg582 GR64:%vreg583
3600B		%vreg580<def> = COPY %vreg582; GR32:%vreg580,%vreg582
3616B		%vreg580<def,tied1> = AND32ri %vreg580<tied0>, 255, %EFLAGS<imp-def,dead>; GR32:%vreg580
3632B		%vreg578<def> = COPY %vreg580:sub_8bit; GR8:%vreg578 GR32:%vreg580
3648B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg578; mem:ST1[%k1] GR8:%vreg578
3664B		%vreg575<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg575
3680B		%vreg574<def> = MOV32rm %vreg575, 1, %noreg, 60, %noreg; mem:LD4[%tPos97] GR32:%vreg574 GR64:%vreg575
3696B		%vreg573<def> = COPY %vreg574; GR32:%vreg573,%vreg574
3712B		%vreg573<def,tied1> = SHR32ri %vreg573<tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg573
3728B		MOV32mr %vreg575, 1, %noreg, 60, %noreg, %vreg573; mem:ST4[%tPos97] GR64:%vreg575 GR32:%vreg573
3744B		%vreg569<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg569
3760B		CMP32mi8 %vreg569, 1, %noreg, 24, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%rNToGo99] GR64:%vreg569
3776B		JNE_1 <BB#26>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#26 BB#23

3792B	BB#23: derived from LLVM BB %if.then.102
	    Predecessors according to CFG: BB#22
3808B		%vreg617<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg617
3824B		%vreg615<def> = MOVSX64rm32 %vreg617, 1, %noreg, 28, %noreg; mem:LD4[%rTPos103] GR64_NOSP:%vreg615 GR64:%vreg617
3840B		%vreg613<def> = MOV32rm %noreg, 4, %vreg615, <ga:@BZ2_rNums>, %noreg; mem:LD4[%arrayidx105] GR32:%vreg613 GR64_NOSP:%vreg615
3856B		%vreg611<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg611
3872B		MOV32mr %vreg611, 1, %noreg, 24, %noreg, %vreg613; mem:ST4[%rNToGo106] GR64:%vreg611 GR32:%vreg613
3888B		%vreg608<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg608
3904B		%vreg607<def> = MOV32rm %vreg608, 1, %noreg, 28, %noreg; mem:LD4[%rTPos107] GR32:%vreg607 GR64:%vreg608
3920B		%vreg606<def> = COPY %vreg607; GR32:%vreg606,%vreg607
3936B		%vreg606<def,tied1> = ADD32ri8 %vreg606<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg606
3952B		MOV32mr %vreg608, 1, %noreg, 28, %noreg, %vreg606; mem:ST4[%rTPos107] GR64:%vreg608 GR32:%vreg606
3968B		%vreg602<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg602
3984B		CMP32mi %vreg602, 1, %noreg, 28, %noreg, 512, %EFLAGS<imp-def>; mem:LD4[%rTPos109] GR64:%vreg602
4000B		JNE_1 <BB#25>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#25 BB#24

4016B	BB#24: derived from LLVM BB %if.then.112
	    Predecessors according to CFG: BB#23
4032B		%vreg619<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg619
4048B		MOV32mi %vreg619, 1, %noreg, 28, %noreg, 0; mem:ST4[%rTPos113] GR64:%vreg619
	    Successors according to CFG: BB#25

4064B	BB#25: derived from LLVM BB %if.end.114
	    Predecessors according to CFG: BB#23 BB#24
4080B		JMP_1 <BB#26>
	    Successors according to CFG: BB#26

4096B	BB#26: derived from LLVM BB %if.end.115
	    Predecessors according to CFG: BB#22 BB#25
4112B		%vreg645<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg645
4128B		%vreg646<def> = MOV32ri 1; GR32:%vreg646
4144B		%vreg655<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg655
4160B		%vreg654<def> = MOV32rm %vreg655, 1, %noreg, 24, %noreg; mem:LD4[%rNToGo116] GR32:%vreg654 GR64:%vreg655
4176B		%vreg653<def> = COPY %vreg654; GR32:%vreg653,%vreg654
4192B		%vreg653<def,tied1> = ADD32ri8 %vreg653<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg653
4208B		MOV32mr %vreg655, 1, %noreg, 24, %noreg, %vreg653; mem:ST4[%rNToGo116] GR64:%vreg655 GR32:%vreg653
4224B		%vreg649<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg649
4240B		CMP32mi8 %vreg649, 1, %noreg, 24, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%rNToGo118] GR64:%vreg649
4256B		%vreg647<def> = COPY %vreg645; GR32:%vreg647,%vreg645
4272B		%vreg647<def,tied1> = CMOVE32rr %vreg647<tied0>, %vreg646, %EFLAGS<imp-use,kill>; GR32:%vreg647,%vreg646
4288B		%vreg643<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg643
4304B		%vreg641<def> = COPY %vreg643; GR32:%vreg641,%vreg643
4320B		%vreg641<def,tied1> = XOR32rr %vreg641<tied0>, %vreg647, %EFLAGS<imp-def,dead>; GR32:%vreg641,%vreg647
4336B		%vreg638<def> = COPY %vreg641:sub_8bit; GR8:%vreg638 GR32:%vreg641
4352B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg638; mem:ST1[%k1] GR8:%vreg638
4368B		%vreg635<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg635
4384B		%vreg634<def> = MOV32rm %vreg635, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used125] GR32:%vreg634 GR64:%vreg635
4400B		%vreg633<def> = COPY %vreg634; GR32:%vreg633,%vreg634
4416B		%vreg633<def,tied1> = ADD32ri8 %vreg633<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg633
4432B		MOV32mr %vreg635, 1, %noreg, 1092, %noreg, %vreg633; mem:ST4[%nblock_used125] GR64:%vreg635 GR32:%vreg633
4448B		%vreg629<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg629
4464B		%vreg628<def> = MOV32rm %vreg629, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used127] GR32:%vreg628 GR64:%vreg629
4480B		%vreg626<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg626
4496B		%vreg625<def> = MOV32rm %vreg626, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock128] GR32:%vreg625 GR64:%vreg626
4512B		%vreg623<def> = COPY %vreg625; GR32:%vreg623,%vreg625
4528B		%vreg623<def,tied1> = ADD32ri8 %vreg623<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg623
4544B		CMP32rr %vreg628, %vreg623, %EFLAGS<imp-def>; GR32:%vreg628,%vreg623
4560B		JNE_1 <BB#28>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#28 BB#27

4576B	BB#27: derived from LLVM BB %if.then.132
	    Predecessors according to CFG: BB#26
4592B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2

4608B	BB#28: derived from LLVM BB %if.end.133
	    Predecessors according to CFG: BB#26
4624B		%vreg661<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg661
4640B		%vreg659<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg659
4656B		CMP32rm %vreg661, %vreg659, 1, %noreg, 64, %noreg, %EFLAGS<imp-def>; mem:LD4[%k0135] GR32:%vreg661 GR64:%vreg659
4672B		JE_1 <BB#30>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#30 BB#29

4688B	BB#29: derived from LLVM BB %if.then.138
	    Predecessors according to CFG: BB#28
4704B		%vreg929<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg929
4720B		%vreg927<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg927
4736B		MOV32mr %vreg927, 1, %noreg, 64, %noreg, %vreg929; mem:ST4[%k0140] GR64:%vreg927 GR32:%vreg929
4752B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2

4768B	BB#30: derived from LLVM BB %if.end.141
	    Predecessors according to CFG: BB#28
4784B		%vreg694<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg694
4800B		MOV32mi %vreg694, 1, %noreg, 16, %noreg, 3; mem:ST4[%state_out_len142] GR64:%vreg694
4816B		%vreg692<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg692
4832B		%vreg689<def> = MOV32rm %vreg692, 1, %noreg, 60, %noreg; mem:LD4[%tPos143] GR32:%vreg689 GR64:%vreg692
4848B		%vreg690<def> = SUBREG_TO_REG 0, %vreg689, 4; GR64_NOSP:%vreg690 GR32:%vreg689
4864B		%vreg687<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg687
4880B		%vreg686<def> = MOV64rm %vreg687, 1, %noreg, 3152, %noreg; mem:LD8[%tt145] GR64:%vreg686,%vreg687
4896B		%vreg684<def> = MOV32rm %vreg686, 4, %vreg690, 0, %noreg; mem:LD4[%arrayidx146] GR32:%vreg684 GR64:%vreg686 GR64_NOSP:%vreg690
4912B		%vreg681<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg681
4928B		MOV32mr %vreg681, 1, %noreg, 60, %noreg, %vreg684; mem:ST4[%tPos147] GR64:%vreg681 GR32:%vreg684
4944B		%vreg678<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg678
4960B		%vreg677<def> = MOV32rm %vreg678, 1, %noreg, 60, %noreg; mem:LD4[%tPos148] GR32:%vreg677 GR64:%vreg678
4976B		%vreg675<def> = COPY %vreg677; GR32:%vreg675,%vreg677
4992B		%vreg675<def,tied1> = AND32ri %vreg675<tied0>, 255, %EFLAGS<imp-def,dead>; GR32:%vreg675
5008B		%vreg673<def> = COPY %vreg675:sub_8bit; GR8:%vreg673 GR32:%vreg675
5024B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg673; mem:ST1[%k1] GR8:%vreg673
5040B		%vreg670<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg670
5056B		%vreg669<def> = MOV32rm %vreg670, 1, %noreg, 60, %noreg; mem:LD4[%tPos151] GR32:%vreg669 GR64:%vreg670
5072B		%vreg668<def> = COPY %vreg669; GR32:%vreg668,%vreg669
5088B		%vreg668<def,tied1> = SHR32ri %vreg668<tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg668
5104B		MOV32mr %vreg670, 1, %noreg, 60, %noreg, %vreg668; mem:ST4[%tPos151] GR64:%vreg670 GR32:%vreg668
5120B		%vreg664<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg664
5136B		CMP32mi8 %vreg664, 1, %noreg, 24, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%rNToGo153] GR64:%vreg664
5152B		JNE_1 <BB#34>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#34 BB#31

5168B	BB#31: derived from LLVM BB %if.then.156
	    Predecessors according to CFG: BB#30
5184B		%vreg712<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg712
5200B		%vreg710<def> = MOVSX64rm32 %vreg712, 1, %noreg, 28, %noreg; mem:LD4[%rTPos157] GR64_NOSP:%vreg710 GR64:%vreg712
5216B		%vreg708<def> = MOV32rm %noreg, 4, %vreg710, <ga:@BZ2_rNums>, %noreg; mem:LD4[%arrayidx159] GR32:%vreg708 GR64_NOSP:%vreg710
5232B		%vreg706<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg706
5248B		MOV32mr %vreg706, 1, %noreg, 24, %noreg, %vreg708; mem:ST4[%rNToGo160] GR64:%vreg706 GR32:%vreg708
5264B		%vreg703<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg703
5280B		%vreg702<def> = MOV32rm %vreg703, 1, %noreg, 28, %noreg; mem:LD4[%rTPos161] GR32:%vreg702 GR64:%vreg703
5296B		%vreg701<def> = COPY %vreg702; GR32:%vreg701,%vreg702
5312B		%vreg701<def,tied1> = ADD32ri8 %vreg701<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg701
5328B		MOV32mr %vreg703, 1, %noreg, 28, %noreg, %vreg701; mem:ST4[%rTPos161] GR64:%vreg703 GR32:%vreg701
5344B		%vreg697<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg697
5360B		CMP32mi %vreg697, 1, %noreg, 28, %noreg, 512, %EFLAGS<imp-def>; mem:LD4[%rTPos163] GR64:%vreg697
5376B		JNE_1 <BB#33>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#33 BB#32

5392B	BB#32: derived from LLVM BB %if.then.166
	    Predecessors according to CFG: BB#31
5408B		%vreg714<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg714
5424B		MOV32mi %vreg714, 1, %noreg, 28, %noreg, 0; mem:ST4[%rTPos167] GR64:%vreg714
	    Successors according to CFG: BB#33

5440B	BB#33: derived from LLVM BB %if.end.168
	    Predecessors according to CFG: BB#31 BB#32
5456B		JMP_1 <BB#34>
	    Successors according to CFG: BB#34

5472B	BB#34: derived from LLVM BB %if.end.169
	    Predecessors according to CFG: BB#30 BB#33
5488B		%vreg740<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg740
5504B		%vreg741<def> = MOV32ri 1; GR32:%vreg741
5520B		%vreg750<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg750
5536B		%vreg749<def> = MOV32rm %vreg750, 1, %noreg, 24, %noreg; mem:LD4[%rNToGo170] GR32:%vreg749 GR64:%vreg750
5552B		%vreg748<def> = COPY %vreg749; GR32:%vreg748,%vreg749
5568B		%vreg748<def,tied1> = ADD32ri8 %vreg748<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg748
5584B		MOV32mr %vreg750, 1, %noreg, 24, %noreg, %vreg748; mem:ST4[%rNToGo170] GR64:%vreg750 GR32:%vreg748
5600B		%vreg744<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg744
5616B		CMP32mi8 %vreg744, 1, %noreg, 24, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%rNToGo172] GR64:%vreg744
5632B		%vreg742<def> = COPY %vreg740; GR32:%vreg742,%vreg740
5648B		%vreg742<def,tied1> = CMOVE32rr %vreg742<tied0>, %vreg741, %EFLAGS<imp-use,kill>; GR32:%vreg742,%vreg741
5664B		%vreg738<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg738
5680B		%vreg736<def> = COPY %vreg738; GR32:%vreg736,%vreg738
5696B		%vreg736<def,tied1> = XOR32rr %vreg736<tied0>, %vreg742, %EFLAGS<imp-def,dead>; GR32:%vreg736,%vreg742
5712B		%vreg733<def> = COPY %vreg736:sub_8bit; GR8:%vreg733 GR32:%vreg736
5728B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg733; mem:ST1[%k1] GR8:%vreg733
5744B		%vreg730<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg730
5760B		%vreg729<def> = MOV32rm %vreg730, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used179] GR32:%vreg729 GR64:%vreg730
5776B		%vreg728<def> = COPY %vreg729; GR32:%vreg728,%vreg729
5792B		%vreg728<def,tied1> = ADD32ri8 %vreg728<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg728
5808B		MOV32mr %vreg730, 1, %noreg, 1092, %noreg, %vreg728; mem:ST4[%nblock_used179] GR64:%vreg730 GR32:%vreg728
5824B		%vreg724<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg724
5840B		%vreg723<def> = MOV32rm %vreg724, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used181] GR32:%vreg723 GR64:%vreg724
5856B		%vreg721<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg721
5872B		%vreg720<def> = MOV32rm %vreg721, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock182] GR32:%vreg720 GR64:%vreg721
5888B		%vreg718<def> = COPY %vreg720; GR32:%vreg718,%vreg720
5904B		%vreg718<def,tied1> = ADD32ri8 %vreg718<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg718
5920B		CMP32rr %vreg723, %vreg718, %EFLAGS<imp-def>; GR32:%vreg723,%vreg718
5936B		JNE_1 <BB#36>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#36 BB#35

5952B	BB#35: derived from LLVM BB %if.then.186
	    Predecessors according to CFG: BB#34
5968B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2

5984B	BB#36: derived from LLVM BB %if.end.187
	    Predecessors according to CFG: BB#34
6000B		%vreg756<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg756
6016B		%vreg754<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg754
6032B		CMP32rm %vreg756, %vreg754, 1, %noreg, 64, %noreg, %EFLAGS<imp-def>; mem:LD4[%k0189] GR32:%vreg756 GR64:%vreg754
6048B		JE_1 <BB#38>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#38 BB#37

6064B	BB#37: derived from LLVM BB %if.then.192
	    Predecessors according to CFG: BB#36
6080B		%vreg924<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg924
6096B		%vreg922<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg922
6112B		MOV32mr %vreg922, 1, %noreg, 64, %noreg, %vreg924; mem:ST4[%k0194] GR64:%vreg922 GR32:%vreg924
6128B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2

6144B	BB#38: derived from LLVM BB %if.end.195
	    Predecessors according to CFG: BB#36
6160B		%vreg787<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg787
6176B		%vreg784<def> = MOV32rm %vreg787, 1, %noreg, 60, %noreg; mem:LD4[%tPos196] GR32:%vreg784 GR64:%vreg787
6192B		%vreg785<def> = SUBREG_TO_REG 0, %vreg784, 4; GR64_NOSP:%vreg785 GR32:%vreg784
6208B		%vreg782<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg782
6224B		%vreg781<def> = MOV64rm %vreg782, 1, %noreg, 3152, %noreg; mem:LD8[%tt198] GR64:%vreg781,%vreg782
6240B		%vreg779<def> = MOV32rm %vreg781, 4, %vreg785, 0, %noreg; mem:LD4[%arrayidx199] GR32:%vreg779 GR64:%vreg781 GR64_NOSP:%vreg785
6256B		%vreg776<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg776
6272B		MOV32mr %vreg776, 1, %noreg, 60, %noreg, %vreg779; mem:ST4[%tPos200] GR64:%vreg776 GR32:%vreg779
6288B		%vreg773<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg773
6304B		%vreg772<def> = MOV32rm %vreg773, 1, %noreg, 60, %noreg; mem:LD4[%tPos201] GR32:%vreg772 GR64:%vreg773
6320B		%vreg770<def> = COPY %vreg772; GR32:%vreg770,%vreg772
6336B		%vreg770<def,tied1> = AND32ri %vreg770<tied0>, 255, %EFLAGS<imp-def,dead>; GR32:%vreg770
6352B		%vreg768<def> = COPY %vreg770:sub_8bit; GR8:%vreg768 GR32:%vreg770
6368B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg768; mem:ST1[%k1] GR8:%vreg768
6384B		%vreg765<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg765
6400B		%vreg764<def> = MOV32rm %vreg765, 1, %noreg, 60, %noreg; mem:LD4[%tPos204] GR32:%vreg764 GR64:%vreg765
6416B		%vreg763<def> = COPY %vreg764; GR32:%vreg763,%vreg764
6432B		%vreg763<def,tied1> = SHR32ri %vreg763<tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg763
6448B		MOV32mr %vreg765, 1, %noreg, 60, %noreg, %vreg763; mem:ST4[%tPos204] GR64:%vreg765 GR32:%vreg763
6464B		%vreg759<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg759
6480B		CMP32mi8 %vreg759, 1, %noreg, 24, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%rNToGo206] GR64:%vreg759
6496B		JNE_1 <BB#42>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#42 BB#39

6512B	BB#39: derived from LLVM BB %if.then.209
	    Predecessors according to CFG: BB#38
6528B		%vreg805<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg805
6544B		%vreg803<def> = MOVSX64rm32 %vreg805, 1, %noreg, 28, %noreg; mem:LD4[%rTPos210] GR64_NOSP:%vreg803 GR64:%vreg805
6560B		%vreg801<def> = MOV32rm %noreg, 4, %vreg803, <ga:@BZ2_rNums>, %noreg; mem:LD4[%arrayidx212] GR32:%vreg801 GR64_NOSP:%vreg803
6576B		%vreg799<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg799
6592B		MOV32mr %vreg799, 1, %noreg, 24, %noreg, %vreg801; mem:ST4[%rNToGo213] GR64:%vreg799 GR32:%vreg801
6608B		%vreg796<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg796
6624B		%vreg795<def> = MOV32rm %vreg796, 1, %noreg, 28, %noreg; mem:LD4[%rTPos214] GR32:%vreg795 GR64:%vreg796
6640B		%vreg794<def> = COPY %vreg795; GR32:%vreg794,%vreg795
6656B		%vreg794<def,tied1> = ADD32ri8 %vreg794<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg794
6672B		MOV32mr %vreg796, 1, %noreg, 28, %noreg, %vreg794; mem:ST4[%rTPos214] GR64:%vreg796 GR32:%vreg794
6688B		%vreg790<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg790
6704B		CMP32mi %vreg790, 1, %noreg, 28, %noreg, 512, %EFLAGS<imp-def>; mem:LD4[%rTPos216] GR64:%vreg790
6720B		JNE_1 <BB#41>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#41 BB#40

6736B	BB#40: derived from LLVM BB %if.then.219
	    Predecessors according to CFG: BB#39
6752B		%vreg807<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg807
6768B		MOV32mi %vreg807, 1, %noreg, 28, %noreg, 0; mem:ST4[%rTPos220] GR64:%vreg807
	    Successors according to CFG: BB#41

6784B	BB#41: derived from LLVM BB %if.end.221
	    Predecessors according to CFG: BB#39 BB#40
6800B		JMP_1 <BB#42>
	    Successors according to CFG: BB#42

6816B	BB#42: derived from LLVM BB %if.end.222
	    Predecessors according to CFG: BB#38 BB#41
6832B		%vreg865<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg865
6848B		%vreg866<def> = MOV32ri 1; GR32:%vreg866
6864B		%vreg875<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg875
6880B		%vreg874<def> = MOV32rm %vreg875, 1, %noreg, 24, %noreg; mem:LD4[%rNToGo223] GR32:%vreg874 GR64:%vreg875
6896B		%vreg873<def> = COPY %vreg874; GR32:%vreg873,%vreg874
6912B		%vreg873<def,tied1> = ADD32ri8 %vreg873<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg873
6928B		MOV32mr %vreg875, 1, %noreg, 24, %noreg, %vreg873; mem:ST4[%rNToGo223] GR64:%vreg875 GR32:%vreg873
6944B		%vreg869<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg869
6960B		CMP32mi8 %vreg869, 1, %noreg, 24, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%rNToGo225] GR64:%vreg869
6976B		%vreg867<def> = COPY %vreg865; GR32:%vreg867,%vreg865
6992B		%vreg867<def,tied1> = CMOVE32rr %vreg867<tied0>, %vreg866, %EFLAGS<imp-use,kill>; GR32:%vreg867,%vreg866
7008B		%vreg863<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg863
7024B		%vreg861<def> = COPY %vreg863; GR32:%vreg861,%vreg863
7040B		%vreg861<def,tied1> = XOR32rr %vreg861<tied0>, %vreg867, %EFLAGS<imp-def,dead>; GR32:%vreg861,%vreg867
7056B		%vreg858<def> = COPY %vreg861:sub_8bit; GR8:%vreg858 GR32:%vreg861
7072B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg858; mem:ST1[%k1] GR8:%vreg858
7088B		%vreg855<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg855
7104B		%vreg854<def> = MOV32rm %vreg855, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used232] GR32:%vreg854 GR64:%vreg855
7120B		%vreg853<def> = COPY %vreg854; GR32:%vreg853,%vreg854
7136B		%vreg853<def,tied1> = ADD32ri8 %vreg853<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg853
7152B		MOV32mr %vreg855, 1, %noreg, 1092, %noreg, %vreg853; mem:ST4[%nblock_used232] GR64:%vreg855 GR32:%vreg853
7168B		%vreg849<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg849
7184B		%vreg847<def> = COPY %vreg849; GR32:%vreg847,%vreg849
7200B		%vreg847<def,tied1> = ADD32ri8 %vreg847<tied0>, 4, %EFLAGS<imp-def,dead>; GR32:%vreg847
7216B		%vreg845<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg845
7232B		MOV32mr %vreg845, 1, %noreg, 16, %noreg, %vreg847; mem:ST4[%state_out_len236] GR64:%vreg845 GR32:%vreg847
7248B		%vreg842<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg842
7264B		%vreg839<def> = MOV32rm %vreg842, 1, %noreg, 60, %noreg; mem:LD4[%tPos237] GR32:%vreg839 GR64:%vreg842
7280B		%vreg840<def> = SUBREG_TO_REG 0, %vreg839, 4; GR64_NOSP:%vreg840 GR32:%vreg839
7296B		%vreg837<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg837
7312B		%vreg836<def> = MOV64rm %vreg837, 1, %noreg, 3152, %noreg; mem:LD8[%tt239] GR64:%vreg836,%vreg837
7328B		%vreg834<def> = MOV32rm %vreg836, 4, %vreg840, 0, %noreg; mem:LD4[%arrayidx240] GR32:%vreg834 GR64:%vreg836 GR64_NOSP:%vreg840
7344B		%vreg831<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg831
7360B		MOV32mr %vreg831, 1, %noreg, 60, %noreg, %vreg834; mem:ST4[%tPos241] GR64:%vreg831 GR32:%vreg834
7376B		%vreg828<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg828
7392B		%vreg827<def> = MOV32rm %vreg828, 1, %noreg, 60, %noreg; mem:LD4[%tPos242] GR32:%vreg827 GR64:%vreg828
7408B		%vreg825<def> = COPY %vreg827; GR32:%vreg825,%vreg827
7424B		%vreg825<def,tied1> = AND32ri %vreg825<tied0>, 255, %EFLAGS<imp-def,dead>; GR32:%vreg825
7440B		%vreg823<def> = COPY %vreg825:sub_8bit; GR8:%vreg823 GR32:%vreg825
7456B		%vreg821<def> = MOVZX32rr8 %vreg823; GR32:%vreg821 GR8:%vreg823
7472B		%vreg819<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg819
7488B		MOV32mr %vreg819, 1, %noreg, 64, %noreg, %vreg821; mem:ST4[%k0246] GR64:%vreg819 GR32:%vreg821
7504B		%vreg816<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg816
7520B		%vreg815<def> = MOV32rm %vreg816, 1, %noreg, 60, %noreg; mem:LD4[%tPos247] GR32:%vreg815 GR64:%vreg816
7536B		%vreg814<def> = COPY %vreg815; GR32:%vreg814,%vreg815
7552B		%vreg814<def,tied1> = SHR32ri %vreg814<tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg814
7568B		MOV32mr %vreg816, 1, %noreg, 60, %noreg, %vreg814; mem:ST4[%tPos247] GR64:%vreg816 GR32:%vreg814
7584B		%vreg810<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg810
7600B		CMP32mi8 %vreg810, 1, %noreg, 24, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%rNToGo249] GR64:%vreg810
7616B		JNE_1 <BB#46>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#46 BB#43

7632B	BB#43: derived from LLVM BB %if.then.252
	    Predecessors according to CFG: BB#42
7648B		%vreg893<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg893
7664B		%vreg891<def> = MOVSX64rm32 %vreg893, 1, %noreg, 28, %noreg; mem:LD4[%rTPos253] GR64_NOSP:%vreg891 GR64:%vreg893
7680B		%vreg889<def> = MOV32rm %noreg, 4, %vreg891, <ga:@BZ2_rNums>, %noreg; mem:LD4[%arrayidx255] GR32:%vreg889 GR64_NOSP:%vreg891
7696B		%vreg887<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg887
7712B		MOV32mr %vreg887, 1, %noreg, 24, %noreg, %vreg889; mem:ST4[%rNToGo256] GR64:%vreg887 GR32:%vreg889
7728B		%vreg884<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg884
7744B		%vreg883<def> = MOV32rm %vreg884, 1, %noreg, 28, %noreg; mem:LD4[%rTPos257] GR32:%vreg883 GR64:%vreg884
7760B		%vreg882<def> = COPY %vreg883; GR32:%vreg882,%vreg883
7776B		%vreg882<def,tied1> = ADD32ri8 %vreg882<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg882
7792B		MOV32mr %vreg884, 1, %noreg, 28, %noreg, %vreg882; mem:ST4[%rTPos257] GR64:%vreg884 GR32:%vreg882
7808B		%vreg878<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg878
7824B		CMP32mi %vreg878, 1, %noreg, 28, %noreg, 512, %EFLAGS<imp-def>; mem:LD4[%rTPos259] GR64:%vreg878
7840B		JNE_1 <BB#45>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#45 BB#44

7856B	BB#44: derived from LLVM BB %if.then.262
	    Predecessors according to CFG: BB#43
7872B		%vreg895<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg895
7888B		MOV32mi %vreg895, 1, %noreg, 28, %noreg, 0; mem:ST4[%rTPos263] GR64:%vreg895
	    Successors according to CFG: BB#45

7904B	BB#45: derived from LLVM BB %if.end.264
	    Predecessors according to CFG: BB#43 BB#44
7920B		JMP_1 <BB#46>
	    Successors according to CFG: BB#46

7936B	BB#46: derived from LLVM BB %if.end.265
	    Predecessors according to CFG: BB#42 BB#45
7952B		%vreg909<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg909
7968B		%vreg910<def> = MOV32ri 1; GR32:%vreg910
7984B		%vreg919<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg919
8000B		%vreg918<def> = MOV32rm %vreg919, 1, %noreg, 24, %noreg; mem:LD4[%rNToGo266] GR32:%vreg918 GR64:%vreg919
8016B		%vreg917<def> = COPY %vreg918; GR32:%vreg917,%vreg918
8032B		%vreg917<def,tied1> = ADD32ri8 %vreg917<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg917
8048B		MOV32mr %vreg919, 1, %noreg, 24, %noreg, %vreg917; mem:ST4[%rNToGo266] GR64:%vreg919 GR32:%vreg917
8064B		%vreg913<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg913
8080B		CMP32mi8 %vreg913, 1, %noreg, 24, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%rNToGo268] GR64:%vreg913
8096B		%vreg911<def> = COPY %vreg909; GR32:%vreg911,%vreg909
8112B		%vreg911<def,tied1> = CMOVE32rr %vreg911<tied0>, %vreg910, %EFLAGS<imp-use,kill>; GR32:%vreg911,%vreg910
8128B		%vreg907<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg907
8144B		%vreg906<def> = COPY %vreg911; GR32:%vreg906,%vreg911
8160B		%vreg906<def,tied1> = XOR32rm %vreg906<tied0>, %vreg907, 1, %noreg, 64, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%k0272] GR32:%vreg906 GR64:%vreg907
8176B		MOV32mr %vreg907, 1, %noreg, 64, %noreg, %vreg906; mem:ST4[%k0272] GR64:%vreg907 GR32:%vreg906
8192B		%vreg901<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg901
8208B		%vreg900<def> = MOV32rm %vreg901, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used274] GR32:%vreg900 GR64:%vreg901
8224B		%vreg899<def> = COPY %vreg900; GR32:%vreg899,%vreg900
8240B		%vreg899<def,tied1> = ADD32ri8 %vreg899<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg899
8256B		MOV32mr %vreg901, 1, %noreg, 1092, %noreg, %vreg899; mem:ST4[%nblock_used274] GR64:%vreg901 GR32:%vreg899
8272B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2

8288B	BB#47: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#0
8304B		%vreg55<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg55
8320B		%vreg54<def> = MOV32rm %vreg55, 1, %noreg, 3184, %noreg; mem:LD4[%calculatedBlockCRC276] GR32:%vreg54 GR64:%vreg55
8336B		MOV32mr <fi#3>, 1, %noreg, 0, %noreg, %vreg54; mem:ST4[%c_calculatedBlockCRC] GR32:%vreg54
8352B		%vreg51<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg51
8368B		%vreg50<def> = MOV8rm %vreg51, 1, %noreg, 12, %noreg; mem:LD1[%state_out_ch277] GR8:%vreg50 GR64:%vreg51
8384B		MOV8mr <fi#4>, 1, %noreg, 0, %noreg, %vreg50; mem:ST1[%c_state_out_ch] GR8:%vreg50
8400B		%vreg47<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg47
8416B		%vreg46<def> = MOV32rm %vreg47, 1, %noreg, 16, %noreg; mem:LD4[%state_out_len278] GR32:%vreg46 GR64:%vreg47
8432B		MOV32mr <fi#5>, 1, %noreg, 0, %noreg, %vreg46; mem:ST4[%c_state_out_len] GR32:%vreg46
8448B		%vreg43<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg43
8464B		%vreg42<def> = MOV32rm %vreg43, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used279] GR32:%vreg42 GR64:%vreg43
8480B		MOV32mr <fi#6>, 1, %noreg, 0, %noreg, %vreg42; mem:ST4[%c_nblock_used] GR32:%vreg42
8496B		%vreg39<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg39
8512B		%vreg38<def> = MOV32rm %vreg39, 1, %noreg, 64, %noreg; mem:LD4[%k0280] GR32:%vreg38 GR64:%vreg39
8528B		MOV32mr <fi#7>, 1, %noreg, 0, %noreg, %vreg38; mem:ST4[%c_k0] GR32:%vreg38
8544B		%vreg35<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg35
8560B		%vreg34<def> = MOV64rm %vreg35, 1, %noreg, 3152, %noreg; mem:LD8[%tt281] GR64:%vreg34,%vreg35
8576B		MOV64mr <fi#8>, 1, %noreg, 0, %noreg, %vreg34; mem:ST8[%c_tt] GR64:%vreg34
8592B		%vreg31<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg31
8608B		%vreg30<def> = MOV32rm %vreg31, 1, %noreg, 60, %noreg; mem:LD4[%tPos282] GR32:%vreg30 GR64:%vreg31
8624B		MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %vreg30; mem:ST4[%c_tPos] GR32:%vreg30
8640B		%vreg27<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg27
8656B		%vreg26<def> = MOV64rm %vreg27, 1, %noreg, 0, %noreg; mem:LD8[%strm283] GR64:%vreg26,%vreg27
8672B		%vreg24<def> = MOV64rm %vreg26, 1, %noreg, 24, %noreg; mem:LD8[%next_out284] GR64:%vreg24,%vreg26
8688B		MOV64mr <fi#10>, 1, %noreg, 0, %noreg, %vreg24; mem:ST8[%cs_next_out] GR64:%vreg24
8704B		%vreg21<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg21
8720B		%vreg20<def> = MOV64rm %vreg21, 1, %noreg, 0, %noreg; mem:LD8[%strm285] GR64:%vreg20,%vreg21
8736B		%vreg18<def> = MOV32rm %vreg20, 1, %noreg, 32, %noreg; mem:LD4[%avail_out286] GR32:%vreg18 GR64:%vreg20
8752B		MOV32mr <fi#11>, 1, %noreg, 0, %noreg, %vreg18; mem:ST4[%cs_avail_out] GR32:%vreg18
8768B		%vreg15<def> = MOV32rm <fi#11>, 1, %noreg, 0, %noreg; mem:LD4[%cs_avail_out] GR32:%vreg15
8784B		MOV32mr <fi#12>, 1, %noreg, 0, %noreg, %vreg15; mem:ST4[%avail_out_INIT] GR32:%vreg15
8800B		%vreg13<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg13
8816B		%vreg12<def> = MOV32rm %vreg13, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock287] GR32:%vreg12 GR64:%vreg13
8832B		%vreg10<def> = COPY %vreg12; GR32:%vreg10,%vreg12
8848B		%vreg10<def,tied1> = ADD32ri8 %vreg10<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg10
8864B		MOV32mr <fi#13>, 1, %noreg, 0, %noreg, %vreg10; mem:ST4[%s_save_nblockPP] GR32:%vreg10
	    Successors according to CFG: BB#48

8880B	BB#48: derived from LLVM BB %while.body.289
	    Predecessors according to CFG: BB#47 BB#75 BB#74 BB#72 BB#70 BB#68
8896B		CMP32mi8 <fi#5>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%c_state_out_len]
8912B		JLE_1 <BB#59>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#59 BB#49

8928B	BB#49: derived from LLVM BB %if.then.292
	    Predecessors according to CFG: BB#48
8944B		JMP_1 <BB#50>
	    Successors according to CFG: BB#50

8960B	BB#50: derived from LLVM BB %while.body.294
	    Predecessors according to CFG: BB#49 BB#54
8976B		CMP32mi8 <fi#11>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%cs_avail_out]
8992B		JNE_1 <BB#52>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#52 BB#51

9008B	BB#51: derived from LLVM BB %if.then.297
	    Predecessors according to CFG: BB#50
9024B		JMP_1 <BB#76>
	    Successors according to CFG: BB#76

9040B	BB#52: derived from LLVM BB %if.end.298
	    Predecessors according to CFG: BB#50
9056B		CMP32mi8 <fi#5>, 1, %noreg, 0, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%c_state_out_len]
9072B		JNE_1 <BB#54>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#54 BB#53

9088B	BB#53: derived from LLVM BB %if.then.301
	    Predecessors according to CFG: BB#52
9104B		JMP_1 <BB#55>
	    Successors according to CFG: BB#55

9120B	BB#54: derived from LLVM BB %if.end.302
	    Predecessors according to CFG: BB#52
9136B		%vreg93<def> = MOV8rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD1[%c_state_out_ch] GR8:%vreg93
9152B		%vreg92<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%cs_next_out] GR64:%vreg92
9168B		MOV8mr %vreg92, 1, %noreg, 0, %noreg, %vreg93; mem:ST1[%249] GR64:%vreg92 GR8:%vreg93
9184B		%vreg89<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%c_calculatedBlockCRC] GR32:%vreg89
9200B		%vreg88<def> = COPY %vreg89; GR32:%vreg88,%vreg89
9216B		%vreg88<def,tied1> = SHL32ri %vreg88<tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg88
9232B		%vreg86<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%c_calculatedBlockCRC] GR32:%vreg86
9248B		%vreg85<def> = COPY %vreg86; GR32:%vreg85,%vreg86
9264B		%vreg85<def,tied1> = SHR32ri %vreg85<tied0>, 24, %EFLAGS<imp-def,dead>; GR32:%vreg85
9280B		%vreg83<def> = MOVZX32rm8 <fi#4>, 1, %noreg, 0, %noreg; mem:LD1[%c_state_out_ch] GR32:%vreg83
9296B		%vreg81<def> = COPY %vreg85; GR32:%vreg81,%vreg85
9312B		%vreg81<def,tied1> = XOR32rr %vreg81<tied0>, %vreg83, %EFLAGS<imp-def,dead>; GR32:%vreg81,%vreg83
9328B		%vreg77<def> = MOV32rr %vreg81; GR32:%vreg77,%vreg81
9344B		%vreg78<def> = SUBREG_TO_REG 0, %vreg77, 4; GR64_NOSP:%vreg78 GR32:%vreg77
9360B		%vreg74<def> = COPY %vreg88; GR32:%vreg74,%vreg88
9376B		%vreg74<def,tied1> = XOR32rm %vreg74<tied0>, %noreg, 4, %vreg78, <ga:@BZ2_crc32Table>, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%arrayidx308] GR32:%vreg74 GR64_NOSP:%vreg78
9392B		MOV32mr <fi#3>, 1, %noreg, 0, %noreg, %vreg74; mem:ST4[%c_calculatedBlockCRC] GR32:%vreg74
9408B		%vreg70<def> = MOV32rm <fi#5>, 1, %noreg, 0, %noreg; mem:LD4[%c_state_out_len] GR32:%vreg70
9424B		%vreg69<def> = COPY %vreg70; GR32:%vreg69,%vreg70
9440B		%vreg69<def,tied1> = ADD32ri8 %vreg69<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg69
9456B		MOV32mr <fi#5>, 1, %noreg, 0, %noreg, %vreg69; mem:ST4[%c_state_out_len] GR32:%vreg69
9472B		%vreg66<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%cs_next_out] GR64:%vreg66
9488B		%vreg65<def> = COPY %vreg66; GR64:%vreg65,%vreg66
9504B		%vreg65<def,tied1> = ADD64ri8 %vreg65<tied0>, 1, %EFLAGS<imp-def,dead>; GR64:%vreg65
9520B		MOV64mr <fi#10>, 1, %noreg, 0, %noreg, %vreg65; mem:ST8[%cs_next_out] GR64:%vreg65
9536B		%vreg62<def> = MOV32rm <fi#11>, 1, %noreg, 0, %noreg; mem:LD4[%cs_avail_out] GR32:%vreg62
9552B		%vreg61<def> = COPY %vreg62; GR32:%vreg61,%vreg62
9568B		%vreg61<def,tied1> = ADD32ri8 %vreg61<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg61
9584B		MOV32mr <fi#11>, 1, %noreg, 0, %noreg, %vreg61; mem:ST4[%cs_avail_out] GR32:%vreg61
9600B		JMP_1 <BB#50>
	    Successors according to CFG: BB#50

9616B	BB#55: derived from LLVM BB %while.end.313
	    Predecessors according to CFG: BB#53
9632B		JMP_1 <BB#56>
	    Successors according to CFG: BB#56

9648B	BB#56: derived from LLVM BB %s_state_out_len_eq_one
	    Predecessors according to CFG: BB#55 BB#66 BB#64
9664B		CMP32mi8 <fi#11>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%cs_avail_out]
9680B		JNE_1 <BB#58>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#58 BB#57

9696B	BB#57: derived from LLVM BB %if.then.316
	    Predecessors according to CFG: BB#56
9712B		MOV32mi <fi#5>, 1, %noreg, 0, %noreg, 1; mem:ST4[%c_state_out_len]
9728B		JMP_1 <BB#76>
	    Successors according to CFG: BB#76

9744B	BB#58: derived from LLVM BB %if.end.317
	    Predecessors according to CFG: BB#56
9760B		%vreg125<def> = MOV8rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD1[%c_state_out_ch] GR8:%vreg125
9776B		%vreg124<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%cs_next_out] GR64:%vreg124
9792B		MOV8mr %vreg124, 1, %noreg, 0, %noreg, %vreg125; mem:ST1[%259] GR64:%vreg124 GR8:%vreg125
9808B		%vreg121<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%c_calculatedBlockCRC] GR32:%vreg121
9824B		%vreg120<def> = COPY %vreg121; GR32:%vreg120,%vreg121
9840B		%vreg120<def,tied1> = SHL32ri %vreg120<tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg120
9856B		%vreg118<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%c_calculatedBlockCRC] GR32:%vreg118
9872B		%vreg117<def> = COPY %vreg118; GR32:%vreg117,%vreg118
9888B		%vreg117<def,tied1> = SHR32ri %vreg117<tied0>, 24, %EFLAGS<imp-def,dead>; GR32:%vreg117
9904B		%vreg115<def> = MOVZX32rm8 <fi#4>, 1, %noreg, 0, %noreg; mem:LD1[%c_state_out_ch] GR32:%vreg115
9920B		%vreg113<def> = COPY %vreg117; GR32:%vreg113,%vreg117
9936B		%vreg113<def,tied1> = XOR32rr %vreg113<tied0>, %vreg115, %EFLAGS<imp-def,dead>; GR32:%vreg113,%vreg115
9952B		%vreg109<def> = MOV32rr %vreg113; GR32:%vreg109,%vreg113
9968B		%vreg110<def> = SUBREG_TO_REG 0, %vreg109, 4; GR64_NOSP:%vreg110 GR32:%vreg109
9984B		%vreg106<def> = COPY %vreg120; GR32:%vreg106,%vreg120
10000B		%vreg106<def,tied1> = XOR32rm %vreg106<tied0>, %noreg, 4, %vreg110, <ga:@BZ2_crc32Table>, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%arrayidx323] GR32:%vreg106 GR64_NOSP:%vreg110
10016B		MOV32mr <fi#3>, 1, %noreg, 0, %noreg, %vreg106; mem:ST4[%c_calculatedBlockCRC] GR32:%vreg106
10032B		%vreg102<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%cs_next_out] GR64:%vreg102
10048B		%vreg101<def> = COPY %vreg102; GR64:%vreg101,%vreg102
10064B		%vreg101<def,tied1> = ADD64ri8 %vreg101<tied0>, 1, %EFLAGS<imp-def,dead>; GR64:%vreg101
10080B		MOV64mr <fi#10>, 1, %noreg, 0, %noreg, %vreg101; mem:ST8[%cs_next_out] GR64:%vreg101
10096B		%vreg98<def> = MOV32rm <fi#11>, 1, %noreg, 0, %noreg; mem:LD4[%cs_avail_out] GR32:%vreg98
10112B		%vreg97<def> = COPY %vreg98; GR32:%vreg97,%vreg98
10128B		%vreg97<def,tied1> = ADD32ri8 %vreg97<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg97
10144B		MOV32mr <fi#11>, 1, %noreg, 0, %noreg, %vreg97; mem:ST4[%cs_avail_out] GR32:%vreg97
	    Successors according to CFG: BB#59

10160B	BB#59: derived from LLVM BB %if.end.327
	    Predecessors according to CFG: BB#48 BB#58
10176B		%vreg128<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%c_nblock_used] GR32:%vreg128
10192B		CMP32rm %vreg128, <fi#13>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD4[%s_save_nblockPP] GR32:%vreg128
10208B		JLE_1 <BB#61>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#61 BB#60

10224B	BB#60: derived from LLVM BB %if.then.330
	    Predecessors according to CFG: BB#59
10240B		MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 1; mem:ST1[%retval]
10256B		JMP_1 <BB#80>
	    Successors according to CFG: BB#80

10272B	BB#61: derived from LLVM BB %if.end.331
	    Predecessors according to CFG: BB#59
10288B		%vreg131<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%c_nblock_used] GR32:%vreg131
10304B		CMP32rm %vreg131, <fi#13>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD4[%s_save_nblockPP] GR32:%vreg131
10320B		JNE_1 <BB#63>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#63 BB#62

10336B	BB#62: derived from LLVM BB %if.then.334
	    Predecessors according to CFG: BB#61
10352B		MOV32mi <fi#5>, 1, %noreg, 0, %noreg, 0; mem:ST4[%c_state_out_len]
10368B		JMP_1 <BB#76>
	    Successors according to CFG: BB#76

10384B	BB#63: derived from LLVM BB %if.end.335
	    Predecessors according to CFG: BB#61
10400B		%vreg161<def> = MOV32rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD4[%c_k0] GR32:%vreg161
10416B		%vreg160<def> = COPY %vreg161:sub_8bit; GR8:%vreg160 GR32:%vreg161
10432B		MOV8mr <fi#4>, 1, %noreg, 0, %noreg, %vreg160; mem:ST1[%c_state_out_ch] GR8:%vreg160
10448B		%vreg156<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR32:%vreg156
10464B		%vreg157<def> = SUBREG_TO_REG 0, %vreg156, 4; GR64_NOSP:%vreg157 GR32:%vreg156
10480B		%vreg154<def> = MOV64rm <fi#8>, 1, %noreg, 0, %noreg; mem:LD8[%c_tt] GR64:%vreg154
10496B		%vreg153<def> = MOV32rm %vreg154, 4, %vreg157, 0, %noreg; mem:LD4[%arrayidx338] GR32:%vreg153 GR64:%vreg154 GR64_NOSP:%vreg157
10512B		MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %vreg153; mem:ST4[%c_tPos] GR32:%vreg153
10528B		%vreg149<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR32:%vreg149
10544B		%vreg148<def> = COPY %vreg149; GR32:%vreg148,%vreg149
10560B		%vreg148<def,tied1> = AND32ri %vreg148<tied0>, 255, %EFLAGS<imp-def,dead>; GR32:%vreg148
10576B		%vreg146<def> = COPY %vreg148:sub_8bit; GR8:%vreg146 GR32:%vreg148
10592B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg146; mem:ST1[%k1] GR8:%vreg146
10608B		%vreg143<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR32:%vreg143
10624B		%vreg142<def> = COPY %vreg143; GR32:%vreg142,%vreg143
10640B		%vreg142<def,tied1> = SHR32ri %vreg142<tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg142
10656B		MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %vreg142; mem:ST4[%c_tPos] GR32:%vreg142
10672B		%vreg139<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%c_nblock_used] GR32:%vreg139
10688B		%vreg138<def> = COPY %vreg139; GR32:%vreg138,%vreg139
10704B		%vreg138<def,tied1> = ADD32ri8 %vreg138<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg138
10720B		MOV32mr <fi#6>, 1, %noreg, 0, %noreg, %vreg138; mem:ST4[%c_nblock_used] GR32:%vreg138
10736B		%vreg135<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg135
10752B		CMP32rm %vreg135, <fi#7>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD4[%c_k0] GR32:%vreg135
10768B		JE_1 <BB#65>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#65 BB#64

10784B	BB#64: derived from LLVM BB %if.then.346
	    Predecessors according to CFG: BB#63
10800B		%vreg282<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg282
10816B		MOV32mr <fi#7>, 1, %noreg, 0, %noreg, %vreg282; mem:ST4[%c_k0] GR32:%vreg282
10832B		JMP_1 <BB#56>
	    Successors according to CFG: BB#56

10848B	BB#65: derived from LLVM BB %if.end.348
	    Predecessors according to CFG: BB#63
10864B		%vreg164<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%c_nblock_used] GR32:%vreg164
10880B		CMP32rm %vreg164, <fi#13>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD4[%s_save_nblockPP] GR32:%vreg164
10896B		JNE_1 <BB#67>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#67 BB#66

10912B	BB#66: derived from LLVM BB %if.then.351
	    Predecessors according to CFG: BB#65
10928B		JMP_1 <BB#56>
	    Successors according to CFG: BB#56

10944B	BB#67: derived from LLVM BB %if.end.352
	    Predecessors according to CFG: BB#65
10960B		MOV32mi <fi#5>, 1, %noreg, 0, %noreg, 2; mem:ST4[%c_state_out_len]
10976B		%vreg188<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR32:%vreg188
10992B		%vreg189<def> = SUBREG_TO_REG 0, %vreg188, 4; GR64_NOSP:%vreg189 GR32:%vreg188
11008B		%vreg186<def> = MOV64rm <fi#8>, 1, %noreg, 0, %noreg; mem:LD8[%c_tt] GR64:%vreg186
11024B		%vreg185<def> = MOV32rm %vreg186, 4, %vreg189, 0, %noreg; mem:LD4[%arrayidx354] GR32:%vreg185 GR64:%vreg186 GR64_NOSP:%vreg189
11040B		MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %vreg185; mem:ST4[%c_tPos] GR32:%vreg185
11056B		%vreg181<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR32:%vreg181
11072B		%vreg180<def> = COPY %vreg181; GR32:%vreg180,%vreg181
11088B		%vreg180<def,tied1> = AND32ri %vreg180<tied0>, 255, %EFLAGS<imp-def,dead>; GR32:%vreg180
11104B		%vreg178<def> = COPY %vreg180:sub_8bit; GR8:%vreg178 GR32:%vreg180
11120B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg178; mem:ST1[%k1] GR8:%vreg178
11136B		%vreg175<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR32:%vreg175
11152B		%vreg174<def> = COPY %vreg175; GR32:%vreg174,%vreg175
11168B		%vreg174<def,tied1> = SHR32ri %vreg174<tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg174
11184B		MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %vreg174; mem:ST4[%c_tPos] GR32:%vreg174
11200B		%vreg171<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%c_nblock_used] GR32:%vreg171
11216B		%vreg170<def> = COPY %vreg171; GR32:%vreg170,%vreg171
11232B		%vreg170<def,tied1> = ADD32ri8 %vreg170<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg170
11248B		MOV32mr <fi#6>, 1, %noreg, 0, %noreg, %vreg170; mem:ST4[%c_nblock_used] GR32:%vreg170
11264B		%vreg167<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%c_nblock_used] GR32:%vreg167
11280B		CMP32rm %vreg167, <fi#13>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD4[%s_save_nblockPP] GR32:%vreg167
11296B		JNE_1 <BB#69>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#69 BB#68

11312B	BB#68: derived from LLVM BB %if.then.361
	    Predecessors according to CFG: BB#67
11328B		JMP_1 <BB#48>
	    Successors according to CFG: BB#48

11344B	BB#69: derived from LLVM BB %if.end.362
	    Predecessors according to CFG: BB#67
11360B		%vreg193<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg193
11376B		CMP32rm %vreg193, <fi#7>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD4[%c_k0] GR32:%vreg193
11392B		JE_1 <BB#71>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#71 BB#70

11408B	BB#70: derived from LLVM BB %if.then.366
	    Predecessors according to CFG: BB#69
11424B		%vreg279<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg279
11440B		MOV32mr <fi#7>, 1, %noreg, 0, %noreg, %vreg279; mem:ST4[%c_k0] GR32:%vreg279
11456B		JMP_1 <BB#48>
	    Successors according to CFG: BB#48

11472B	BB#71: derived from LLVM BB %if.end.368
	    Predecessors according to CFG: BB#69
11488B		MOV32mi <fi#5>, 1, %noreg, 0, %noreg, 3; mem:ST4[%c_state_out_len]
11504B		%vreg217<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR32:%vreg217
11520B		%vreg218<def> = SUBREG_TO_REG 0, %vreg217, 4; GR64_NOSP:%vreg218 GR32:%vreg217
11536B		%vreg215<def> = MOV64rm <fi#8>, 1, %noreg, 0, %noreg; mem:LD8[%c_tt] GR64:%vreg215
11552B		%vreg214<def> = MOV32rm %vreg215, 4, %vreg218, 0, %noreg; mem:LD4[%arrayidx370] GR32:%vreg214 GR64:%vreg215 GR64_NOSP:%vreg218
11568B		MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %vreg214; mem:ST4[%c_tPos] GR32:%vreg214
11584B		%vreg210<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR32:%vreg210
11600B		%vreg209<def> = COPY %vreg210; GR32:%vreg209,%vreg210
11616B		%vreg209<def,tied1> = AND32ri %vreg209<tied0>, 255, %EFLAGS<imp-def,dead>; GR32:%vreg209
11632B		%vreg207<def> = COPY %vreg209:sub_8bit; GR8:%vreg207 GR32:%vreg209
11648B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg207; mem:ST1[%k1] GR8:%vreg207
11664B		%vreg204<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR32:%vreg204
11680B		%vreg203<def> = COPY %vreg204; GR32:%vreg203,%vreg204
11696B		%vreg203<def,tied1> = SHR32ri %vreg203<tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg203
11712B		MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %vreg203; mem:ST4[%c_tPos] GR32:%vreg203
11728B		%vreg200<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%c_nblock_used] GR32:%vreg200
11744B		%vreg199<def> = COPY %vreg200; GR32:%vreg199,%vreg200
11760B		%vreg199<def,tied1> = ADD32ri8 %vreg199<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg199
11776B		MOV32mr <fi#6>, 1, %noreg, 0, %noreg, %vreg199; mem:ST4[%c_nblock_used] GR32:%vreg199
11792B		%vreg196<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%c_nblock_used] GR32:%vreg196
11808B		CMP32rm %vreg196, <fi#13>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD4[%s_save_nblockPP] GR32:%vreg196
11824B		JNE_1 <BB#73>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#73 BB#72

11840B	BB#72: derived from LLVM BB %if.then.377
	    Predecessors according to CFG: BB#71
11856B		JMP_1 <BB#48>
	    Successors according to CFG: BB#48

11872B	BB#73: derived from LLVM BB %if.end.378
	    Predecessors according to CFG: BB#71
11888B		%vreg222<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg222
11904B		CMP32rm %vreg222, <fi#7>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD4[%c_k0] GR32:%vreg222
11920B		JE_1 <BB#75>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#75 BB#74

11936B	BB#74: derived from LLVM BB %if.then.382
	    Predecessors according to CFG: BB#73
11952B		%vreg276<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg276
11968B		MOV32mr <fi#7>, 1, %noreg, 0, %noreg, %vreg276; mem:ST4[%c_k0] GR32:%vreg276
11984B		JMP_1 <BB#48>
	    Successors according to CFG: BB#48

12000B	BB#75: derived from LLVM BB %if.end.384
	    Predecessors according to CFG: BB#73
12016B		%vreg272<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR32:%vreg272
12032B		%vreg273<def> = SUBREG_TO_REG 0, %vreg272, 4; GR64_NOSP:%vreg273 GR32:%vreg272
12048B		%vreg270<def> = MOV64rm <fi#8>, 1, %noreg, 0, %noreg; mem:LD8[%c_tt] GR64:%vreg270
12064B		%vreg269<def> = MOV32rm %vreg270, 4, %vreg273, 0, %noreg; mem:LD4[%arrayidx386] GR32:%vreg269 GR64:%vreg270 GR64_NOSP:%vreg273
12080B		MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %vreg269; mem:ST4[%c_tPos] GR32:%vreg269
12096B		%vreg265<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR32:%vreg265
12112B		%vreg264<def> = COPY %vreg265; GR32:%vreg264,%vreg265
12128B		%vreg264<def,tied1> = AND32ri %vreg264<tied0>, 255, %EFLAGS<imp-def,dead>; GR32:%vreg264
12144B		%vreg262<def> = COPY %vreg264:sub_8bit; GR8:%vreg262 GR32:%vreg264
12160B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg262; mem:ST1[%k1] GR8:%vreg262
12176B		%vreg259<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR32:%vreg259
12192B		%vreg258<def> = COPY %vreg259; GR32:%vreg258,%vreg259
12208B		%vreg258<def,tied1> = SHR32ri %vreg258<tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg258
12224B		MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %vreg258; mem:ST4[%c_tPos] GR32:%vreg258
12240B		%vreg255<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%c_nblock_used] GR32:%vreg255
12256B		%vreg254<def> = COPY %vreg255; GR32:%vreg254,%vreg255
12272B		%vreg254<def,tied1> = ADD32ri8 %vreg254<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg254
12288B		MOV32mr <fi#6>, 1, %noreg, 0, %noreg, %vreg254; mem:ST4[%c_nblock_used] GR32:%vreg254
12304B		%vreg251<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg251
12320B		%vreg249<def> = COPY %vreg251; GR32:%vreg249,%vreg251
12336B		%vreg249<def,tied1> = ADD32ri8 %vreg249<tied0>, 4, %EFLAGS<imp-def,dead>; GR32:%vreg249
12352B		MOV32mr <fi#5>, 1, %noreg, 0, %noreg, %vreg249; mem:ST4[%c_state_out_len] GR32:%vreg249
12368B		%vreg245<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR32:%vreg245
12384B		%vreg246<def> = SUBREG_TO_REG 0, %vreg245, 4; GR64_NOSP:%vreg246 GR32:%vreg245
12400B		%vreg243<def> = MOV64rm <fi#8>, 1, %noreg, 0, %noreg; mem:LD8[%c_tt] GR64:%vreg243
12416B		%vreg242<def> = MOV32rm %vreg243, 4, %vreg246, 0, %noreg; mem:LD4[%arrayidx394] GR32:%vreg242 GR64:%vreg243 GR64_NOSP:%vreg246
12432B		MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %vreg242; mem:ST4[%c_tPos] GR32:%vreg242
12448B		%vreg238<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR32:%vreg238
12464B		%vreg237<def> = COPY %vreg238; GR32:%vreg237,%vreg238
12480B		%vreg237<def,tied1> = AND32ri %vreg237<tied0>, 255, %EFLAGS<imp-def,dead>; GR32:%vreg237
12496B		%vreg235<def> = COPY %vreg237:sub_8bit; GR8:%vreg235 GR32:%vreg237
12512B		%vreg233<def> = MOVZX32rr8 %vreg235; GR32:%vreg233 GR8:%vreg235
12528B		MOV32mr <fi#7>, 1, %noreg, 0, %noreg, %vreg233; mem:ST4[%c_k0] GR32:%vreg233
12544B		%vreg230<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR32:%vreg230
12560B		%vreg229<def> = COPY %vreg230; GR32:%vreg229,%vreg230
12576B		%vreg229<def,tied1> = SHR32ri %vreg229<tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg229
12592B		MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %vreg229; mem:ST4[%c_tPos] GR32:%vreg229
12608B		%vreg226<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%c_nblock_used] GR32:%vreg226
12624B		%vreg225<def> = COPY %vreg226; GR32:%vreg225,%vreg226
12640B		%vreg225<def,tied1> = ADD32ri8 %vreg225<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg225
12656B		MOV32mr <fi#6>, 1, %noreg, 0, %noreg, %vreg225; mem:ST4[%c_nblock_used] GR32:%vreg225
12672B		JMP_1 <BB#48>
	    Successors according to CFG: BB#48

12688B	BB#76: derived from LLVM BB %return_notr
	    Predecessors according to CFG: BB#62 BB#57 BB#51
12704B		%vreg307<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg307
12720B		%vreg306<def> = MOV64rm %vreg307, 1, %noreg, 0, %noreg; mem:LD8[%strm400] GR64:%vreg306,%vreg307
12736B		%vreg304<def> = MOV32rm %vreg306, 1, %noreg, 36, %noreg; mem:LD4[%total_out_lo32401] GR32:%vreg304 GR64:%vreg306
12752B		MOV32mr <fi#14>, 1, %noreg, 0, %noreg, %vreg304; mem:ST4[%total_out_lo32_old] GR32:%vreg304
12768B		%vreg301<def> = MOV32rm <fi#12>, 1, %noreg, 0, %noreg; mem:LD4[%avail_out_INIT] GR32:%vreg301
12784B		%vreg300<def> = COPY %vreg301; GR32:%vreg300,%vreg301
12800B		%vreg300<def,tied1> = SUB32rm %vreg300<tied0>, <fi#11>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%cs_avail_out] GR32:%vreg300
12816B		%vreg297<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg297
12832B		%vreg296<def> = MOV64rm %vreg297, 1, %noreg, 0, %noreg; mem:LD8[%strm402] GR64:%vreg296,%vreg297
12848B		%vreg294<def> = COPY %vreg300; GR32:%vreg294,%vreg300
12864B		%vreg294<def,tied1> = ADD32rm %vreg294<tied0>, %vreg296, 1, %noreg, 36, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%total_out_lo32403] GR32:%vreg294 GR64:%vreg296
12880B		MOV32mr %vreg296, 1, %noreg, 36, %noreg, %vreg294; mem:ST4[%total_out_lo32403] GR64:%vreg296 GR32:%vreg294
12896B		%vreg289<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg289
12912B		%vreg288<def> = MOV64rm %vreg289, 1, %noreg, 0, %noreg; mem:LD8[%strm405] GR64:%vreg288,%vreg289
12928B		%vreg286<def> = MOV32rm %vreg288, 1, %noreg, 36, %noreg; mem:LD4[%total_out_lo32406] GR32:%vreg286 GR64:%vreg288
12944B		CMP32rm %vreg286, <fi#14>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD4[%total_out_lo32_old] GR32:%vreg286
12960B		JAE_1 <BB#78>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#78 BB#77

12976B	BB#77: derived from LLVM BB %if.then.409
	    Predecessors according to CFG: BB#76
12992B		%vreg315<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg315
13008B		%vreg314<def> = MOV64rm %vreg315, 1, %noreg, 0, %noreg; mem:LD8[%strm410] GR64:%vreg314,%vreg315
13024B		%vreg312<def> = MOV32rm %vreg314, 1, %noreg, 40, %noreg; mem:LD4[%total_out_hi32411] GR32:%vreg312 GR64:%vreg314
13040B		%vreg311<def> = COPY %vreg312; GR32:%vreg311,%vreg312
13056B		%vreg311<def,tied1> = ADD32ri8 %vreg311<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg311
13072B		MOV32mr %vreg314, 1, %noreg, 40, %noreg, %vreg311; mem:ST4[%total_out_hi32411] GR64:%vreg314 GR32:%vreg311
	    Successors according to CFG: BB#78

13088B	BB#78: derived from LLVM BB %if.end.413
	    Predecessors according to CFG: BB#76 BB#77
13104B		%vreg355<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%c_calculatedBlockCRC] GR32:%vreg355
13120B		%vreg354<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg354
13136B		MOV32mr %vreg354, 1, %noreg, 3184, %noreg, %vreg355; mem:ST4[%calculatedBlockCRC414] GR64:%vreg354 GR32:%vreg355
13152B		%vreg351<def> = MOV8rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD1[%c_state_out_ch] GR8:%vreg351
13168B		%vreg350<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg350
13184B		MOV8mr %vreg350, 1, %noreg, 12, %noreg, %vreg351; mem:ST1[%state_out_ch415] GR64:%vreg350 GR8:%vreg351
13200B		%vreg347<def> = MOV32rm <fi#5>, 1, %noreg, 0, %noreg; mem:LD4[%c_state_out_len] GR32:%vreg347
13216B		%vreg346<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg346
13232B		MOV32mr %vreg346, 1, %noreg, 16, %noreg, %vreg347; mem:ST4[%state_out_len416] GR64:%vreg346 GR32:%vreg347
13248B		%vreg343<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%c_nblock_used] GR32:%vreg343
13264B		%vreg342<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg342
13280B		MOV32mr %vreg342, 1, %noreg, 1092, %noreg, %vreg343; mem:ST4[%nblock_used417] GR64:%vreg342 GR32:%vreg343
13296B		%vreg339<def> = MOV32rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD4[%c_k0] GR32:%vreg339
13312B		%vreg338<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg338
13328B		MOV32mr %vreg338, 1, %noreg, 64, %noreg, %vreg339; mem:ST4[%k0418] GR64:%vreg338 GR32:%vreg339
13344B		%vreg335<def> = MOV64rm <fi#8>, 1, %noreg, 0, %noreg; mem:LD8[%c_tt] GR64:%vreg335
13360B		%vreg334<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg334
13376B		MOV64mr %vreg334, 1, %noreg, 3152, %noreg, %vreg335; mem:ST8[%tt419] GR64:%vreg334,%vreg335
13392B		%vreg331<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR32:%vreg331
13408B		%vreg330<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg330
13424B		MOV32mr %vreg330, 1, %noreg, 60, %noreg, %vreg331; mem:ST4[%tPos420] GR64:%vreg330 GR32:%vreg331
13440B		%vreg327<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%cs_next_out] GR64:%vreg327
13456B		%vreg326<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg326
13472B		%vreg325<def> = MOV64rm %vreg326, 1, %noreg, 0, %noreg; mem:LD8[%strm421] GR64:%vreg325,%vreg326
13488B		MOV64mr %vreg325, 1, %noreg, 24, %noreg, %vreg327; mem:ST8[%next_out422] GR64:%vreg325,%vreg327
13504B		%vreg321<def> = MOV32rm <fi#11>, 1, %noreg, 0, %noreg; mem:LD4[%cs_avail_out] GR32:%vreg321
13520B		%vreg320<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg320
13536B		%vreg319<def> = MOV64rm %vreg320, 1, %noreg, 0, %noreg; mem:LD8[%strm423] GR64:%vreg319,%vreg320
13552B		MOV32mr %vreg319, 1, %noreg, 32, %noreg, %vreg321; mem:ST4[%avail_out424] GR64:%vreg319 GR32:%vreg321
	    Successors according to CFG: BB#79

13568B	BB#79: derived from LLVM BB %if.end.425
	    Predecessors according to CFG: BB#78
13584B		MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST1[%retval]
	    Successors according to CFG: BB#80

13600B	BB#80: derived from LLVM BB %return
	    Predecessors according to CFG: BB#60 BB#79 BB#13 BB#11 BB#4
13616B		%vreg937<def> = MOV64ri <ga:@unRLE_obuf_to_output_FAST>; GR64:%vreg937
13632B		%vreg938<def> = COPY %vreg937; GR64:%vreg938,%vreg937
13648B		%vreg939<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg939
13664B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
13680B		%RDI<def> = COPY %vreg938; GR64:%vreg938
13696B		%RSI<def> = COPY %vreg939; GR64:%vreg939
13712B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
13728B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
13744B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
13760B		STACKMAP 1, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=1)
13776B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
13792B		%vreg936<def> = MOV8rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD1[%retval] GR8:%vreg936
13808B		%AL<def> = COPY %vreg936; GR8:%vreg936
13824B		RETQ %AL<imp-use,kill>

# End machine code for function unRLE_obuf_to_output_FAST.

********** SIMPLE REGISTER COALESCING **********
********** Function: unRLE_obuf_to_output_FAST
********** JOINING INTERVALS ***********
while.body.2:
while.body.294:
if.end:
if.end.6:
896B	%vreg408<def> = SUBREG_TO_REG 0, %vreg407, 4; GR64_NOSP:%vreg408 GR32:%vreg407
	Considering merging to GR64_NOSP with %vreg407 in %vreg408:sub_32bit
		RHS = %vreg407 [880r,896r:0)  0@880r
		LHS = %vreg408 [896r,928r:0)  0@896r
		merge %vreg408:0@896r into %vreg407:0@880r --> @880r
		erased:	896r	%vreg408<def> = SUBREG_TO_REG 0, %vreg407, 4; GR64_NOSP:%vreg408 GR32:%vreg407
		updated: 880B	%vreg408:sub_32bit<def,read-undef> = MOV32rr %vreg411; GR64_NOSP:%vreg408 GR32:%vreg411
	Success: %vreg407:sub_32bit -> %vreg408
	Result = %vreg408 [880r,928r:0)  0@880r
if.end.26:
if.end.298:
if.then.23:
if.end.302:
9344B	%vreg78<def> = SUBREG_TO_REG 0, %vreg77, 4; GR64_NOSP:%vreg78 GR32:%vreg77
	Considering merging to GR64_NOSP with %vreg77 in %vreg78:sub_32bit
		RHS = %vreg77 [9328r,9344r:0)  0@9328r
		LHS = %vreg78 [9344r,9376r:0)  0@9344r
		merge %vreg78:0@9344r into %vreg77:0@9328r --> @9328r
		erased:	9344r	%vreg78<def> = SUBREG_TO_REG 0, %vreg77, 4; GR64_NOSP:%vreg78 GR32:%vreg77
		updated: 9328B	%vreg78:sub_32bit<def,read-undef> = MOV32rr %vreg81; GR64_NOSP:%vreg78 GR32:%vreg81
	Success: %vreg77:sub_32bit -> %vreg78
	Result = %vreg78 [9328r,9376r:0)  0@9328r
720B	%vreg422<def> = COPY %vreg424; GR32:%vreg422,%vreg424
	Considering merging to GR32 with %vreg424 in %vreg422
		RHS = %vreg424 [704r,720r:0)  0@704r
		LHS = %vreg422 [720r,736r:0)[736r,912r:1)  0@720r 1@736r
		merge %vreg422:0@720r into %vreg424:0@704r --> @704r
		erased:	720r	%vreg422<def> = COPY %vreg424; GR32:%vreg422,%vreg424
		updated: 704B	%vreg422<def> = MOV32rm %vreg425, 1, %noreg, 3184, %noreg; mem:LD4[%calculatedBlockCRC] GR32:%vreg422 GR64:%vreg425
	Success: %vreg424 -> %vreg422
	Result = %vreg422 [704r,736r:0)[736r,912r:1)  0@704r 1@736r
784B	%vreg417<def> = COPY %vreg419; GR32:%vreg417,%vreg419
	Considering merging to GR32 with %vreg419 in %vreg417
		RHS = %vreg419 [768r,784r:0)  0@768r
		LHS = %vreg417 [784r,800r:0)[800r,848r:1)  0@784r 1@800r
		merge %vreg417:0@784r into %vreg419:0@768r --> @768r
		erased:	784r	%vreg417<def> = COPY %vreg419; GR32:%vreg417,%vreg419
		updated: 768B	%vreg417<def> = MOV32rm %vreg420, 1, %noreg, 3184, %noreg; mem:LD4[%calculatedBlockCRC8] GR32:%vreg417 GR64:%vreg420
	Success: %vreg419 -> %vreg417
	Result = %vreg417 [768r,800r:0)[800r,848r:1)  0@768r 1@800r
848B	%vreg411<def> = COPY %vreg417; GR32:%vreg411,%vreg417
	Considering merging to GR32 with %vreg417 in %vreg411
		RHS = %vreg417 [768r,800r:0)[800r,848r:1)  0@768r 1@800r
		LHS = %vreg411 [848r,864r:0)[864r,880r:1)  0@848r 1@864r
		merge %vreg411:0@848r into %vreg417:1@800r --> @800r
		erased:	848r	%vreg411<def> = COPY %vreg417; GR32:%vreg411,%vreg417
		updated: 768B	%vreg411<def> = MOV32rm %vreg420, 1, %noreg, 3184, %noreg; mem:LD4[%calculatedBlockCRC8] GR32:%vreg411 GR64:%vreg420
		updated: 800B	%vreg411<def,tied1> = SHR32ri %vreg411<tied0>, 24, %EFLAGS<imp-def,dead>; GR32:%vreg411
	Success: %vreg417 -> %vreg411
	Result = %vreg411 [768r,800r:2)[800r,864r:0)[864r,880r:1)  0@800r 1@864r 2@768r
912B	%vreg404<def> = COPY %vreg422; GR32:%vreg404,%vreg422
	Considering merging to GR32 with %vreg422 in %vreg404
		RHS = %vreg422 [704r,736r:0)[736r,912r:1)  0@704r 1@736r
		LHS = %vreg404 [912r,928r:0)[928r,960r:1)  0@912r 1@928r
		merge %vreg404:0@912r into %vreg422:1@736r --> @736r
		erased:	912r	%vreg404<def> = COPY %vreg422; GR32:%vreg404,%vreg422
		updated: 704B	%vreg404<def> = MOV32rm %vreg425, 1, %noreg, 3184, %noreg; mem:LD4[%calculatedBlockCRC] GR32:%vreg404 GR64:%vreg425
		updated: 736B	%vreg404<def,tied1> = SHL32ri %vreg404<tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg404
	Success: %vreg422 -> %vreg404
	Result = %vreg404 [704r,736r:2)[736r,928r:0)[928r,960r:1)  0@736r 1@928r 2@704r
1008B	%vreg396<def> = COPY %vreg397; GR32:%vreg396,%vreg397
	Considering merging to GR32 with %vreg397 in %vreg396
		RHS = %vreg397 [992r,1008r:0)  0@992r
		LHS = %vreg396 [1008r,1024r:0)[1024r,1040r:1)  0@1008r 1@1024r
		merge %vreg396:0@1008r into %vreg397:0@992r --> @992r
		erased:	1008r	%vreg396<def> = COPY %vreg397; GR32:%vreg396,%vreg397
		updated: 992B	%vreg396<def> = MOV32rm %vreg398, 1, %noreg, 16, %noreg; mem:LD4[%state_out_len12] GR32:%vreg396 GR64:%vreg398
	Success: %vreg397 -> %vreg396
	Result = %vreg396 [992r,1024r:0)[1024r,1040r:1)  0@992r 1@1024r
1104B	%vreg388<def> = COPY %vreg389; GR64:%vreg388,%vreg389
	Considering merging to GR64 with %vreg389 in %vreg388
		RHS = %vreg389 [1088r,1104r:0)  0@1088r
		LHS = %vreg388 [1104r,1120r:0)[1120r,1136r:1)  0@1104r 1@1120r
		merge %vreg388:0@1104r into %vreg389:0@1088r --> @1088r
		erased:	1104r	%vreg388<def> = COPY %vreg389; GR64:%vreg388,%vreg389
		updated: 1088B	%vreg388<def> = MOV64rm %vreg391, 1, %noreg, 24, %noreg; mem:LD8[%next_out14] GR64:%vreg388,%vreg391
	Success: %vreg389 -> %vreg388
	Result = %vreg388 [1088r,1120r:0)[1120r,1136r:1)  0@1088r 1@1120r
1200B	%vreg380<def> = COPY %vreg381; GR32:%vreg380,%vreg381
	Considering merging to GR32 with %vreg381 in %vreg380
		RHS = %vreg381 [1184r,1200r:0)  0@1184r
		LHS = %vreg380 [1200r,1216r:0)[1216r,1232r:1)  0@1200r 1@1216r
		merge %vreg380:0@1200r into %vreg381:0@1184r --> @1184r
		erased:	1200r	%vreg380<def> = COPY %vreg381; GR32:%vreg380,%vreg381
		updated: 1184B	%vreg380<def> = MOV32rm %vreg383, 1, %noreg, 32, %noreg; mem:LD4[%avail_out16] GR32:%vreg380 GR64:%vreg383
	Success: %vreg381 -> %vreg380
	Result = %vreg380 [1184r,1216r:0)[1216r,1232r:1)  0@1184r 1@1216r
1296B	%vreg372<def> = COPY %vreg373; GR32:%vreg372,%vreg373
	Considering merging to GR32 with %vreg373 in %vreg372
		RHS = %vreg373 [1280r,1296r:0)  0@1280r
		LHS = %vreg372 [1296r,1312r:0)[1312r,1328r:1)  0@1296r 1@1312r
		merge %vreg372:0@1296r into %vreg373:0@1280r --> @1280r
		erased:	1296r	%vreg372<def> = COPY %vreg373; GR32:%vreg372,%vreg373
		updated: 1280B	%vreg372<def> = MOV32rm %vreg375, 1, %noreg, 36, %noreg; mem:LD4[%total_out_lo32] GR32:%vreg372 GR64:%vreg375
	Success: %vreg373 -> %vreg372
	Result = %vreg372 [1280r,1312r:0)[1312r,1328r:1)  0@1280r 1@1312r
1472B	%vreg439<def> = COPY %vreg440; GR32:%vreg439,%vreg440
	Considering merging to GR32 with %vreg440 in %vreg439
		RHS = %vreg440 [1456r,1472r:0)  0@1456r
		LHS = %vreg439 [1472r,1488r:0)[1488r,1504r:1)  0@1472r 1@1488r
		merge %vreg439:0@1472r into %vreg440:0@1456r --> @1456r
		erased:	1472r	%vreg439<def> = COPY %vreg440; GR32:%vreg439,%vreg440
		updated: 1456B	%vreg439<def> = MOV32rm %vreg442, 1, %noreg, 40, %noreg; mem:LD4[%total_out_hi32] GR32:%vreg439 GR64:%vreg442
	Success: %vreg440 -> %vreg439
	Result = %vreg439 [1456r,1488r:0)[1488r,1504r:1)  0@1456r 1@1488r
9200B	%vreg88<def> = COPY %vreg89; GR32:%vreg88,%vreg89
	Considering merging to GR32 with %vreg89 in %vreg88
		RHS = %vreg89 [9184r,9200r:0)  0@9184r
		LHS = %vreg88 [9200r,9216r:0)[9216r,9360r:1)  0@9200r 1@9216r
		merge %vreg88:0@9200r into %vreg89:0@9184r --> @9184r
		erased:	9200r	%vreg88<def> = COPY %vreg89; GR32:%vreg88,%vreg89
		updated: 9184B	%vreg88<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%c_calculatedBlockCRC] GR32:%vreg88
	Success: %vreg89 -> %vreg88
	Result = %vreg88 [9184r,9216r:0)[9216r,9360r:1)  0@9184r 1@9216r
9248B	%vreg85<def> = COPY %vreg86; GR32:%vreg85,%vreg86
	Considering merging to GR32 with %vreg86 in %vreg85
		RHS = %vreg86 [9232r,9248r:0)  0@9232r
		LHS = %vreg85 [9248r,9264r:0)[9264r,9296r:1)  0@9248r 1@9264r
		merge %vreg85:0@9248r into %vreg86:0@9232r --> @9232r
		erased:	9248r	%vreg85<def> = COPY %vreg86; GR32:%vreg85,%vreg86
		updated: 9232B	%vreg85<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%c_calculatedBlockCRC] GR32:%vreg85
	Success: %vreg86 -> %vreg85
	Result = %vreg85 [9232r,9264r:0)[9264r,9296r:1)  0@9232r 1@9264r
9296B	%vreg81<def> = COPY %vreg85; GR32:%vreg81,%vreg85
	Considering merging to GR32 with %vreg85 in %vreg81
		RHS = %vreg85 [9232r,9264r:0)[9264r,9296r:1)  0@9232r 1@9264r
		LHS = %vreg81 [9296r,9312r:0)[9312r,9328r:1)  0@9296r 1@9312r
		merge %vreg81:0@9296r into %vreg85:1@9264r --> @9264r
		erased:	9296r	%vreg81<def> = COPY %vreg85; GR32:%vreg81,%vreg85
		updated: 9232B	%vreg81<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%c_calculatedBlockCRC] GR32:%vreg81
		updated: 9264B	%vreg81<def,tied1> = SHR32ri %vreg81<tied0>, 24, %EFLAGS<imp-def,dead>; GR32:%vreg81
	Success: %vreg85 -> %vreg81
	Result = %vreg81 [9232r,9264r:2)[9264r,9312r:0)[9312r,9328r:1)  0@9264r 1@9312r 2@9232r
9360B	%vreg74<def> = COPY %vreg88; GR32:%vreg74,%vreg88
	Considering merging to GR32 with %vreg88 in %vreg74
		RHS = %vreg88 [9184r,9216r:0)[9216r,9360r:1)  0@9184r 1@9216r
		LHS = %vreg74 [9360r,9376r:0)[9376r,9392r:1)  0@9360r 1@9376r
		merge %vreg74:0@9360r into %vreg88:1@9216r --> @9216r
		erased:	9360r	%vreg74<def> = COPY %vreg88; GR32:%vreg74,%vreg88
		updated: 9184B	%vreg74<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%c_calculatedBlockCRC] GR32:%vreg74
		updated: 9216B	%vreg74<def,tied1> = SHL32ri %vreg74<tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg74
	Success: %vreg88 -> %vreg74
	Result = %vreg74 [9184r,9216r:2)[9216r,9376r:0)[9376r,9392r:1)  0@9216r 1@9376r 2@9184r
9424B	%vreg69<def> = COPY %vreg70; GR32:%vreg69,%vreg70
	Considering merging to GR32 with %vreg70 in %vreg69
		RHS = %vreg70 [9408r,9424r:0)  0@9408r
		LHS = %vreg69 [9424r,9440r:0)[9440r,9456r:1)  0@9424r 1@9440r
		merge %vreg69:0@9424r into %vreg70:0@9408r --> @9408r
		erased:	9424r	%vreg69<def> = COPY %vreg70; GR32:%vreg69,%vreg70
		updated: 9408B	%vreg69<def> = MOV32rm <fi#5>, 1, %noreg, 0, %noreg; mem:LD4[%c_state_out_len] GR32:%vreg69
	Success: %vreg70 -> %vreg69
	Result = %vreg69 [9408r,9440r:0)[9440r,9456r:1)  0@9408r 1@9440r
9488B	%vreg65<def> = COPY %vreg66; GR64:%vreg65,%vreg66
	Considering merging to GR64 with %vreg66 in %vreg65
		RHS = %vreg66 [9472r,9488r:0)  0@9472r
		LHS = %vreg65 [9488r,9504r:0)[9504r,9520r:1)  0@9488r 1@9504r
		merge %vreg65:0@9488r into %vreg66:0@9472r --> @9472r
		erased:	9488r	%vreg65<def> = COPY %vreg66; GR64:%vreg65,%vreg66
		updated: 9472B	%vreg65<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%cs_next_out] GR64:%vreg65
	Success: %vreg66 -> %vreg65
	Result = %vreg65 [9472r,9504r:0)[9504r,9520r:1)  0@9472r 1@9504r
9552B	%vreg61<def> = COPY %vreg62; GR32:%vreg61,%vreg62
	Considering merging to GR32 with %vreg62 in %vreg61
		RHS = %vreg62 [9536r,9552r:0)  0@9536r
		LHS = %vreg61 [9552r,9568r:0)[9568r,9584r:1)  0@9552r 1@9568r
		merge %vreg61:0@9552r into %vreg62:0@9536r --> @9536r
		erased:	9552r	%vreg61<def> = COPY %vreg62; GR32:%vreg61,%vreg62
		updated: 9536B	%vreg61<def> = MOV32rm <fi#11>, 1, %noreg, 0, %noreg; mem:LD4[%cs_avail_out] GR32:%vreg61
	Success: %vreg62 -> %vreg61
	Result = %vreg61 [9536r,9568r:0)[9568r,9584r:1)  0@9536r 1@9568r
while.body:
while.body.289:
s_state_out_len_eq_one:
if.end.62:
if.end.115:
if.end.169:
if.end.222:
7280B	%vreg840<def> = SUBREG_TO_REG 0, %vreg839, 4; GR64_NOSP:%vreg840 GR32:%vreg839
	Considering merging to GR64_NOSP with %vreg839 in %vreg840:sub_32bit
		RHS = %vreg839 [7264r,7280r:0)  0@7264r
		LHS = %vreg840 [7280r,7328r:0)  0@7280r
		merge %vreg840:0@7280r into %vreg839:0@7264r --> @7264r
		erased:	7280r	%vreg840<def> = SUBREG_TO_REG 0, %vreg839, 4; GR64_NOSP:%vreg840 GR32:%vreg839
		updated: 7264B	%vreg840:sub_32bit<def,read-undef> = MOV32rm %vreg842, 1, %noreg, 60, %noreg; mem:LD4[%tPos237] GR64_NOSP:%vreg840 GR64:%vreg842
	Success: %vreg839:sub_32bit -> %vreg840
	Result = %vreg840 [7264r,7328r:0)  0@7264r
if.end.327:
while.end:
if.end.30:
if.end.37:
2096B	%vreg492<def> = SUBREG_TO_REG 0, %vreg491, 4; GR64_NOSP:%vreg492 GR32:%vreg491
	Considering merging to GR64_NOSP with %vreg491 in %vreg492:sub_32bit
		RHS = %vreg491 [2080r,2096r:0)  0@2080r
		LHS = %vreg492 [2096r,2144r:0)  0@2096r
		merge %vreg492:0@2096r into %vreg491:0@2080r --> @2080r
		erased:	2096r	%vreg492<def> = SUBREG_TO_REG 0, %vreg491, 4; GR64_NOSP:%vreg492 GR32:%vreg491
		updated: 2080B	%vreg492:sub_32bit<def,read-undef> = MOV32rm %vreg494, 1, %noreg, 60, %noreg; mem:LD4[%tPos] GR64_NOSP:%vreg492 GR64:%vreg494
	Success: %vreg491:sub_32bit -> %vreg492
	Result = %vreg492 [2080r,2144r:0)  0@2080r
if.then.50:
if.end.61:
if.end.79:
if.end.87:
3472B	%vreg595<def> = SUBREG_TO_REG 0, %vreg594, 4; GR64_NOSP:%vreg595 GR32:%vreg594
	Considering merging to GR64_NOSP with %vreg594 in %vreg595:sub_32bit
		RHS = %vreg594 [3456r,3472r:0)  0@3456r
		LHS = %vreg595 [3472r,3520r:0)  0@3472r
		merge %vreg595:0@3472r into %vreg594:0@3456r --> @3456r
		erased:	3472r	%vreg595<def> = SUBREG_TO_REG 0, %vreg594, 4; GR64_NOSP:%vreg595 GR32:%vreg594
		updated: 3456B	%vreg595:sub_32bit<def,read-undef> = MOV32rm %vreg597, 1, %noreg, 60, %noreg; mem:LD4[%tPos89] GR64_NOSP:%vreg595 GR64:%vreg597
	Success: %vreg594:sub_32bit -> %vreg595
	Result = %vreg595 [3456r,3520r:0)  0@3456r
if.then.102:
if.end.114:
if.end.133:
if.end.141:
4848B	%vreg690<def> = SUBREG_TO_REG 0, %vreg689, 4; GR64_NOSP:%vreg690 GR32:%vreg689
	Considering merging to GR64_NOSP with %vreg689 in %vreg690:sub_32bit
		RHS = %vreg689 [4832r,4848r:0)  0@4832r
		LHS = %vreg690 [4848r,4896r:0)  0@4848r
		merge %vreg690:0@4848r into %vreg689:0@4832r --> @4832r
		erased:	4848r	%vreg690<def> = SUBREG_TO_REG 0, %vreg689, 4; GR64_NOSP:%vreg690 GR32:%vreg689
		updated: 4832B	%vreg690:sub_32bit<def,read-undef> = MOV32rm %vreg692, 1, %noreg, 60, %noreg; mem:LD4[%tPos143] GR64_NOSP:%vreg690 GR64:%vreg692
	Success: %vreg689:sub_32bit -> %vreg690
	Result = %vreg690 [4832r,4896r:0)  0@4832r
if.then.156:
if.end.168:
if.end.187:
if.end.195:
6192B	%vreg785<def> = SUBREG_TO_REG 0, %vreg784, 4; GR64_NOSP:%vreg785 GR32:%vreg784
	Considering merging to GR64_NOSP with %vreg784 in %vreg785:sub_32bit
		RHS = %vreg784 [6176r,6192r:0)  0@6176r
		LHS = %vreg785 [6192r,6240r:0)  0@6192r
		merge %vreg785:0@6192r into %vreg784:0@6176r --> @6176r
		erased:	6192r	%vreg785<def> = SUBREG_TO_REG 0, %vreg784, 4; GR64_NOSP:%vreg785 GR32:%vreg784
		updated: 6176B	%vreg785:sub_32bit<def,read-undef> = MOV32rm %vreg787, 1, %noreg, 60, %noreg; mem:LD4[%tPos196] GR64_NOSP:%vreg785 GR64:%vreg787
	Success: %vreg784:sub_32bit -> %vreg785
	Result = %vreg785 [6176r,6240r:0)  0@6176r
if.then.209:
if.end.221:
if.then.252:
if.end.264:
if.end.265:
if.end.331:
if.end.335:
10464B	%vreg157<def> = SUBREG_TO_REG 0, %vreg156, 4; GR64_NOSP:%vreg157 GR32:%vreg156
	Considering merging to GR64_NOSP with %vreg156 in %vreg157:sub_32bit
		RHS = %vreg156 [10448r,10464r:0)  0@10448r
		LHS = %vreg157 [10464r,10496r:0)  0@10464r
		merge %vreg157:0@10464r into %vreg156:0@10448r --> @10448r
		erased:	10464r	%vreg157<def> = SUBREG_TO_REG 0, %vreg156, 4; GR64_NOSP:%vreg157 GR32:%vreg156
		updated: 10448B	%vreg157:sub_32bit<def,read-undef> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR64_NOSP:%vreg157
	Success: %vreg156:sub_32bit -> %vreg157
	Result = %vreg157 [10448r,10496r:0)  0@10448r
if.end.348:
if.end.352:
10992B	%vreg189<def> = SUBREG_TO_REG 0, %vreg188, 4; GR64_NOSP:%vreg189 GR32:%vreg188
	Considering merging to GR64_NOSP with %vreg188 in %vreg189:sub_32bit
		RHS = %vreg188 [10976r,10992r:0)  0@10976r
		LHS = %vreg189 [10992r,11024r:0)  0@10992r
		merge %vreg189:0@10992r into %vreg188:0@10976r --> @10976r
		erased:	10992r	%vreg189<def> = SUBREG_TO_REG 0, %vreg188, 4; GR64_NOSP:%vreg189 GR32:%vreg188
		updated: 10976B	%vreg189:sub_32bit<def,read-undef> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR64_NOSP:%vreg189
	Success: %vreg188:sub_32bit -> %vreg189
	Result = %vreg189 [10976r,11024r:0)  0@10976r
if.end.362:
if.end.368:
11520B	%vreg218<def> = SUBREG_TO_REG 0, %vreg217, 4; GR64_NOSP:%vreg218 GR32:%vreg217
	Considering merging to GR64_NOSP with %vreg217 in %vreg218:sub_32bit
		RHS = %vreg217 [11504r,11520r:0)  0@11504r
		LHS = %vreg218 [11520r,11552r:0)  0@11520r
		merge %vreg218:0@11520r into %vreg217:0@11504r --> @11504r
		erased:	11520r	%vreg218<def> = SUBREG_TO_REG 0, %vreg217, 4; GR64_NOSP:%vreg218 GR32:%vreg217
		updated: 11504B	%vreg218:sub_32bit<def,read-undef> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR64_NOSP:%vreg218
	Success: %vreg217:sub_32bit -> %vreg218
	Result = %vreg218 [11504r,11552r:0)  0@11504r
if.end.378:
if.then.5:
if.then.59:
if.then.78:
if.then.84:
if.then.112:
if.then.132:
if.then.138:
if.then.166:
if.then.186:
if.then.192:
if.then.219:
if.then.262:
if.then.292:
if.then.301:
while.end.313:
if.end.317:
9968B	%vreg110<def> = SUBREG_TO_REG 0, %vreg109, 4; GR64_NOSP:%vreg110 GR32:%vreg109
	Considering merging to GR64_NOSP with %vreg109 in %vreg110:sub_32bit
		RHS = %vreg109 [9952r,9968r:0)  0@9952r
		LHS = %vreg110 [9968r,10000r:0)  0@9968r
		merge %vreg110:0@9968r into %vreg109:0@9952r --> @9952r
		erased:	9968r	%vreg110<def> = SUBREG_TO_REG 0, %vreg109, 4; GR64_NOSP:%vreg110 GR32:%vreg109
		updated: 9952B	%vreg110:sub_32bit<def,read-undef> = MOV32rr %vreg113; GR64_NOSP:%vreg110 GR32:%vreg113
	Success: %vreg109:sub_32bit -> %vreg110
	Result = %vreg110 [9952r,10000r:0)  0@9952r
if.then.346:
if.then.351:
if.then.361:
if.then.366:
if.then.377:
if.then.382:
if.end.384:
12032B	%vreg273<def> = SUBREG_TO_REG 0, %vreg272, 4; GR64_NOSP:%vreg273 GR32:%vreg272
	Considering merging to GR64_NOSP with %vreg272 in %vreg273:sub_32bit
		RHS = %vreg272 [12016r,12032r:0)  0@12016r
		LHS = %vreg273 [12032r,12064r:0)  0@12032r
		merge %vreg273:0@12032r into %vreg272:0@12016r --> @12016r
		erased:	12032r	%vreg273<def> = SUBREG_TO_REG 0, %vreg272, 4; GR64_NOSP:%vreg273 GR32:%vreg272
		updated: 12016B	%vreg273:sub_32bit<def,read-undef> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR64_NOSP:%vreg273
	Success: %vreg272:sub_32bit -> %vreg273
	Result = %vreg273 [12016r,12064r:0)  0@12016r
12384B	%vreg246<def> = SUBREG_TO_REG 0, %vreg245, 4; GR64_NOSP:%vreg246 GR32:%vreg245
	Considering merging to GR64_NOSP with %vreg245 in %vreg246:sub_32bit
		RHS = %vreg245 [12368r,12384r:0)  0@12368r
		LHS = %vreg246 [12384r,12416r:0)  0@12384r
		merge %vreg246:0@12384r into %vreg245:0@12368r --> @12368r
		erased:	12384r	%vreg246<def> = SUBREG_TO_REG 0, %vreg245, 4; GR64_NOSP:%vreg246 GR32:%vreg245
		updated: 12368B	%vreg246:sub_32bit<def,read-undef> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR64_NOSP:%vreg246
	Success: %vreg245:sub_32bit -> %vreg246
	Result = %vreg246 [12368r,12416r:0)  0@12368r
2800B	%vreg558<def> = COPY %vreg559; GR32:%vreg558,%vreg559
	Considering merging to GR32 with %vreg559 in %vreg558
		RHS = %vreg559 [2784r,2800r:0)  0@2784r
		LHS = %vreg558 [2800r,2816r:0)[2816r,2832r:1)  0@2800r 1@2816r
		merge %vreg558:0@2800r into %vreg559:0@2784r --> @2784r
		erased:	2800r	%vreg558<def> = COPY %vreg559; GR32:%vreg558,%vreg559
		updated: 2784B	%vreg558<def> = MOV32rm %vreg560, 1, %noreg, 24, %noreg; mem:LD4[%rNToGo63] GR32:%vreg558 GR64:%vreg560
	Success: %vreg559 -> %vreg558
	Result = %vreg558 [2784r,2816r:0)[2816r,2832r:1)  0@2784r 1@2816r
2880B	%vreg552<def> = COPY %vreg550; GR32:%vreg552,%vreg550
	Considering merging to GR32 with %vreg550 in %vreg552
		RHS = %vreg550 [2736r,2880r:0)  0@2736r
		LHS = %vreg552 [2880r,2896r:0)[2896r,2944r:1)  0@2880r 1@2896r
		merge %vreg552:0@2880r into %vreg550:0@2736r --> @2736r
		erased:	2880r	%vreg552<def> = COPY %vreg550; GR32:%vreg552,%vreg550
		updated: 2736B	%vreg552<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg552
	Success: %vreg550 -> %vreg552
	Result = %vreg552 [2736r,2896r:0)[2896r,2944r:1)  0@2736r 1@2896r
2928B	%vreg546<def> = COPY %vreg548; GR32:%vreg546,%vreg548
	Considering merging to GR32 with %vreg548 in %vreg546
		RHS = %vreg548 [2912r,2928r:0)  0@2912r
		LHS = %vreg546 [2928r,2944r:0)[2944r,2960r:1)  0@2928r 1@2944r
		merge %vreg546:0@2928r into %vreg548:0@2912r --> @2912r
		erased:	2928r	%vreg546<def> = COPY %vreg548; GR32:%vreg546,%vreg548
		updated: 2912B	%vreg546<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg546
	Success: %vreg548 -> %vreg546
	Result = %vreg546 [2912r,2944r:0)[2944r,2960r:1)  0@2912r 1@2944r
2960B	%vreg543<def> = COPY %vreg546:sub_8bit; GR8:%vreg543 GR32:%vreg546
	Considering merging to GR32 with %vreg543 in %vreg546:sub_8bit
		RHS = %vreg543 [2960r,2976r:0)  0@2960r
		LHS = %vreg546 [2912r,2944r:0)[2944r,2960r:1)  0@2912r 1@2944r
		merge %vreg543:0@2960r into %vreg546:1@2944r --> @2944r
		erased:	2960r	%vreg543<def> = COPY %vreg546:sub_8bit; GR8:%vreg543 GR32:%vreg546
		updated: 2976B	MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg546:sub_8bit; mem:ST1[%k1] GR32:%vreg546
	Success: %vreg543:sub_8bit -> %vreg546
	Result = %vreg546 [2912r,2944r:0)[2944r,2976r:1)  0@2912r 1@2944r
3024B	%vreg538<def> = COPY %vreg539; GR32:%vreg538,%vreg539
	Considering merging to GR32 with %vreg539 in %vreg538
		RHS = %vreg539 [3008r,3024r:0)  0@3008r
		LHS = %vreg538 [3024r,3040r:0)[3040r,3056r:1)  0@3024r 1@3040r
		merge %vreg538:0@3024r into %vreg539:0@3008r --> @3008r
		erased:	3024r	%vreg538<def> = COPY %vreg539; GR32:%vreg538,%vreg539
		updated: 3008B	%vreg538<def> = MOV32rm %vreg540, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used71] GR32:%vreg538 GR64:%vreg540
	Success: %vreg539 -> %vreg538
	Result = %vreg538 [3008r,3040r:0)[3040r,3056r:1)  0@3008r 1@3040r
3136B	%vreg528<def> = COPY %vreg530; GR32:%vreg528,%vreg530
	Considering merging to GR32 with %vreg530 in %vreg528
		RHS = %vreg530 [3120r,3136r:0)  0@3120r
		LHS = %vreg528 [3136r,3152r:0)[3152r,3168r:1)  0@3136r 1@3152r
		merge %vreg528:0@3136r into %vreg530:0@3120r --> @3120r
		erased:	3136r	%vreg528<def> = COPY %vreg530; GR32:%vreg528,%vreg530
		updated: 3120B	%vreg528<def> = MOV32rm %vreg531, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock74] GR32:%vreg528 GR64:%vreg531
	Success: %vreg530 -> %vreg528
	Result = %vreg528 [3120r,3152r:0)[3152r,3168r:1)  0@3120r 1@3152r
4176B	%vreg653<def> = COPY %vreg654; GR32:%vreg653,%vreg654
	Considering merging to GR32 with %vreg654 in %vreg653
		RHS = %vreg654 [4160r,4176r:0)  0@4160r
		LHS = %vreg653 [4176r,4192r:0)[4192r,4208r:1)  0@4176r 1@4192r
		merge %vreg653:0@4176r into %vreg654:0@4160r --> @4160r
		erased:	4176r	%vreg653<def> = COPY %vreg654; GR32:%vreg653,%vreg654
		updated: 4160B	%vreg653<def> = MOV32rm %vreg655, 1, %noreg, 24, %noreg; mem:LD4[%rNToGo116] GR32:%vreg653 GR64:%vreg655
	Success: %vreg654 -> %vreg653
	Result = %vreg653 [4160r,4192r:0)[4192r,4208r:1)  0@4160r 1@4192r
4256B	%vreg647<def> = COPY %vreg645; GR32:%vreg647,%vreg645
	Considering merging to GR32 with %vreg645 in %vreg647
		RHS = %vreg645 [4112r,4256r:0)  0@4112r
		LHS = %vreg647 [4256r,4272r:0)[4272r,4320r:1)  0@4256r 1@4272r
		merge %vreg647:0@4256r into %vreg645:0@4112r --> @4112r
		erased:	4256r	%vreg647<def> = COPY %vreg645; GR32:%vreg647,%vreg645
		updated: 4112B	%vreg647<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg647
	Success: %vreg645 -> %vreg647
	Result = %vreg647 [4112r,4272r:0)[4272r,4320r:1)  0@4112r 1@4272r
4304B	%vreg641<def> = COPY %vreg643; GR32:%vreg641,%vreg643
	Considering merging to GR32 with %vreg643 in %vreg641
		RHS = %vreg643 [4288r,4304r:0)  0@4288r
		LHS = %vreg641 [4304r,4320r:0)[4320r,4336r:1)  0@4304r 1@4320r
		merge %vreg641:0@4304r into %vreg643:0@4288r --> @4288r
		erased:	4304r	%vreg641<def> = COPY %vreg643; GR32:%vreg641,%vreg643
		updated: 4288B	%vreg641<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg641
	Success: %vreg643 -> %vreg641
	Result = %vreg641 [4288r,4320r:0)[4320r,4336r:1)  0@4288r 1@4320r
4336B	%vreg638<def> = COPY %vreg641:sub_8bit; GR8:%vreg638 GR32:%vreg641
	Considering merging to GR32 with %vreg638 in %vreg641:sub_8bit
		RHS = %vreg638 [4336r,4352r:0)  0@4336r
		LHS = %vreg641 [4288r,4320r:0)[4320r,4336r:1)  0@4288r 1@4320r
		merge %vreg638:0@4336r into %vreg641:1@4320r --> @4320r
		erased:	4336r	%vreg638<def> = COPY %vreg641:sub_8bit; GR8:%vreg638 GR32:%vreg641
		updated: 4352B	MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg641:sub_8bit; mem:ST1[%k1] GR32:%vreg641
	Success: %vreg638:sub_8bit -> %vreg641
	Result = %vreg641 [4288r,4320r:0)[4320r,4352r:1)  0@4288r 1@4320r
4400B	%vreg633<def> = COPY %vreg634; GR32:%vreg633,%vreg634
	Considering merging to GR32 with %vreg634 in %vreg633
		RHS = %vreg634 [4384r,4400r:0)  0@4384r
		LHS = %vreg633 [4400r,4416r:0)[4416r,4432r:1)  0@4400r 1@4416r
		merge %vreg633:0@4400r into %vreg634:0@4384r --> @4384r
		erased:	4400r	%vreg633<def> = COPY %vreg634; GR32:%vreg633,%vreg634
		updated: 4384B	%vreg633<def> = MOV32rm %vreg635, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used125] GR32:%vreg633 GR64:%vreg635
	Success: %vreg634 -> %vreg633
	Result = %vreg633 [4384r,4416r:0)[4416r,4432r:1)  0@4384r 1@4416r
4512B	%vreg623<def> = COPY %vreg625; GR32:%vreg623,%vreg625
	Considering merging to GR32 with %vreg625 in %vreg623
		RHS = %vreg625 [4496r,4512r:0)  0@4496r
		LHS = %vreg623 [4512r,4528r:0)[4528r,4544r:1)  0@4512r 1@4528r
		merge %vreg623:0@4512r into %vreg625:0@4496r --> @4496r
		erased:	4512r	%vreg623<def> = COPY %vreg625; GR32:%vreg623,%vreg625
		updated: 4496B	%vreg623<def> = MOV32rm %vreg626, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock128] GR32:%vreg623 GR64:%vreg626
	Success: %vreg625 -> %vreg623
	Result = %vreg623 [4496r,4528r:0)[4528r,4544r:1)  0@4496r 1@4528r
5552B	%vreg748<def> = COPY %vreg749; GR32:%vreg748,%vreg749
	Considering merging to GR32 with %vreg749 in %vreg748
		RHS = %vreg749 [5536r,5552r:0)  0@5536r
		LHS = %vreg748 [5552r,5568r:0)[5568r,5584r:1)  0@5552r 1@5568r
		merge %vreg748:0@5552r into %vreg749:0@5536r --> @5536r
		erased:	5552r	%vreg748<def> = COPY %vreg749; GR32:%vreg748,%vreg749
		updated: 5536B	%vreg748<def> = MOV32rm %vreg750, 1, %noreg, 24, %noreg; mem:LD4[%rNToGo170] GR32:%vreg748 GR64:%vreg750
	Success: %vreg749 -> %vreg748
	Result = %vreg748 [5536r,5568r:0)[5568r,5584r:1)  0@5536r 1@5568r
5632B	%vreg742<def> = COPY %vreg740; GR32:%vreg742,%vreg740
	Considering merging to GR32 with %vreg740 in %vreg742
		RHS = %vreg740 [5488r,5632r:0)  0@5488r
		LHS = %vreg742 [5632r,5648r:0)[5648r,5696r:1)  0@5632r 1@5648r
		merge %vreg742:0@5632r into %vreg740:0@5488r --> @5488r
		erased:	5632r	%vreg742<def> = COPY %vreg740; GR32:%vreg742,%vreg740
		updated: 5488B	%vreg742<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg742
	Success: %vreg740 -> %vreg742
	Result = %vreg742 [5488r,5648r:0)[5648r,5696r:1)  0@5488r 1@5648r
5680B	%vreg736<def> = COPY %vreg738; GR32:%vreg736,%vreg738
	Considering merging to GR32 with %vreg738 in %vreg736
		RHS = %vreg738 [5664r,5680r:0)  0@5664r
		LHS = %vreg736 [5680r,5696r:0)[5696r,5712r:1)  0@5680r 1@5696r
		merge %vreg736:0@5680r into %vreg738:0@5664r --> @5664r
		erased:	5680r	%vreg736<def> = COPY %vreg738; GR32:%vreg736,%vreg738
		updated: 5664B	%vreg736<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg736
	Success: %vreg738 -> %vreg736
	Result = %vreg736 [5664r,5696r:0)[5696r,5712r:1)  0@5664r 1@5696r
5712B	%vreg733<def> = COPY %vreg736:sub_8bit; GR8:%vreg733 GR32:%vreg736
	Considering merging to GR32 with %vreg733 in %vreg736:sub_8bit
		RHS = %vreg733 [5712r,5728r:0)  0@5712r
		LHS = %vreg736 [5664r,5696r:0)[5696r,5712r:1)  0@5664r 1@5696r
		merge %vreg733:0@5712r into %vreg736:1@5696r --> @5696r
		erased:	5712r	%vreg733<def> = COPY %vreg736:sub_8bit; GR8:%vreg733 GR32:%vreg736
		updated: 5728B	MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg736:sub_8bit; mem:ST1[%k1] GR32:%vreg736
	Success: %vreg733:sub_8bit -> %vreg736
	Result = %vreg736 [5664r,5696r:0)[5696r,5728r:1)  0@5664r 1@5696r
5776B	%vreg728<def> = COPY %vreg729; GR32:%vreg728,%vreg729
	Considering merging to GR32 with %vreg729 in %vreg728
		RHS = %vreg729 [5760r,5776r:0)  0@5760r
		LHS = %vreg728 [5776r,5792r:0)[5792r,5808r:1)  0@5776r 1@5792r
		merge %vreg728:0@5776r into %vreg729:0@5760r --> @5760r
		erased:	5776r	%vreg728<def> = COPY %vreg729; GR32:%vreg728,%vreg729
		updated: 5760B	%vreg728<def> = MOV32rm %vreg730, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used179] GR32:%vreg728 GR64:%vreg730
	Success: %vreg729 -> %vreg728
	Result = %vreg728 [5760r,5792r:0)[5792r,5808r:1)  0@5760r 1@5792r
5888B	%vreg718<def> = COPY %vreg720; GR32:%vreg718,%vreg720
	Considering merging to GR32 with %vreg720 in %vreg718
		RHS = %vreg720 [5872r,5888r:0)  0@5872r
		LHS = %vreg718 [5888r,5904r:0)[5904r,5920r:1)  0@5888r 1@5904r
		merge %vreg718:0@5888r into %vreg720:0@5872r --> @5872r
		erased:	5888r	%vreg718<def> = COPY %vreg720; GR32:%vreg718,%vreg720
		updated: 5872B	%vreg718<def> = MOV32rm %vreg721, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock182] GR32:%vreg718 GR64:%vreg721
	Success: %vreg720 -> %vreg718
	Result = %vreg718 [5872r,5904r:0)[5904r,5920r:1)  0@5872r 1@5904r
6896B	%vreg873<def> = COPY %vreg874; GR32:%vreg873,%vreg874
	Considering merging to GR32 with %vreg874 in %vreg873
		RHS = %vreg874 [6880r,6896r:0)  0@6880r
		LHS = %vreg873 [6896r,6912r:0)[6912r,6928r:1)  0@6896r 1@6912r
		merge %vreg873:0@6896r into %vreg874:0@6880r --> @6880r
		erased:	6896r	%vreg873<def> = COPY %vreg874; GR32:%vreg873,%vreg874
		updated: 6880B	%vreg873<def> = MOV32rm %vreg875, 1, %noreg, 24, %noreg; mem:LD4[%rNToGo223] GR32:%vreg873 GR64:%vreg875
	Success: %vreg874 -> %vreg873
	Result = %vreg873 [6880r,6912r:0)[6912r,6928r:1)  0@6880r 1@6912r
6976B	%vreg867<def> = COPY %vreg865; GR32:%vreg867,%vreg865
	Considering merging to GR32 with %vreg865 in %vreg867
		RHS = %vreg865 [6832r,6976r:0)  0@6832r
		LHS = %vreg867 [6976r,6992r:0)[6992r,7040r:1)  0@6976r 1@6992r
		merge %vreg867:0@6976r into %vreg865:0@6832r --> @6832r
		erased:	6976r	%vreg867<def> = COPY %vreg865; GR32:%vreg867,%vreg865
		updated: 6832B	%vreg867<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg867
	Success: %vreg865 -> %vreg867
	Result = %vreg867 [6832r,6992r:0)[6992r,7040r:1)  0@6832r 1@6992r
7024B	%vreg861<def> = COPY %vreg863; GR32:%vreg861,%vreg863
	Considering merging to GR32 with %vreg863 in %vreg861
		RHS = %vreg863 [7008r,7024r:0)  0@7008r
		LHS = %vreg861 [7024r,7040r:0)[7040r,7056r:1)  0@7024r 1@7040r
		merge %vreg861:0@7024r into %vreg863:0@7008r --> @7008r
		erased:	7024r	%vreg861<def> = COPY %vreg863; GR32:%vreg861,%vreg863
		updated: 7008B	%vreg861<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg861
	Success: %vreg863 -> %vreg861
	Result = %vreg861 [7008r,7040r:0)[7040r,7056r:1)  0@7008r 1@7040r
7056B	%vreg858<def> = COPY %vreg861:sub_8bit; GR8:%vreg858 GR32:%vreg861
	Considering merging to GR32 with %vreg858 in %vreg861:sub_8bit
		RHS = %vreg858 [7056r,7072r:0)  0@7056r
		LHS = %vreg861 [7008r,7040r:0)[7040r,7056r:1)  0@7008r 1@7040r
		merge %vreg858:0@7056r into %vreg861:1@7040r --> @7040r
		erased:	7056r	%vreg858<def> = COPY %vreg861:sub_8bit; GR8:%vreg858 GR32:%vreg861
		updated: 7072B	MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg861:sub_8bit; mem:ST1[%k1] GR32:%vreg861
	Success: %vreg858:sub_8bit -> %vreg861
	Result = %vreg861 [7008r,7040r:0)[7040r,7072r:1)  0@7008r 1@7040r
7120B	%vreg853<def> = COPY %vreg854; GR32:%vreg853,%vreg854
	Considering merging to GR32 with %vreg854 in %vreg853
		RHS = %vreg854 [7104r,7120r:0)  0@7104r
		LHS = %vreg853 [7120r,7136r:0)[7136r,7152r:1)  0@7120r 1@7136r
		merge %vreg853:0@7120r into %vreg854:0@7104r --> @7104r
		erased:	7120r	%vreg853<def> = COPY %vreg854; GR32:%vreg853,%vreg854
		updated: 7104B	%vreg853<def> = MOV32rm %vreg855, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used232] GR32:%vreg853 GR64:%vreg855
	Success: %vreg854 -> %vreg853
	Result = %vreg853 [7104r,7136r:0)[7136r,7152r:1)  0@7104r 1@7136r
7184B	%vreg847<def> = COPY %vreg849; GR32:%vreg847,%vreg849
	Considering merging to GR32 with %vreg849 in %vreg847
		RHS = %vreg849 [7168r,7184r:0)  0@7168r
		LHS = %vreg847 [7184r,7200r:0)[7200r,7232r:1)  0@7184r 1@7200r
		merge %vreg847:0@7184r into %vreg849:0@7168r --> @7168r
		erased:	7184r	%vreg847<def> = COPY %vreg849; GR32:%vreg847,%vreg849
		updated: 7168B	%vreg847<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg847
	Success: %vreg849 -> %vreg847
	Result = %vreg847 [7168r,7200r:0)[7200r,7232r:1)  0@7168r 1@7200r
7408B	%vreg825<def> = COPY %vreg827; GR32:%vreg825,%vreg827
	Considering merging to GR32 with %vreg827 in %vreg825
		RHS = %vreg827 [7392r,7408r:0)  0@7392r
		LHS = %vreg825 [7408r,7424r:0)[7424r,7440r:1)  0@7408r 1@7424r
		merge %vreg825:0@7408r into %vreg827:0@7392r --> @7392r
		erased:	7408r	%vreg825<def> = COPY %vreg827; GR32:%vreg825,%vreg827
		updated: 7392B	%vreg825<def> = MOV32rm %vreg828, 1, %noreg, 60, %noreg; mem:LD4[%tPos242] GR32:%vreg825 GR64:%vreg828
	Success: %vreg827 -> %vreg825
	Result = %vreg825 [7392r,7424r:0)[7424r,7440r:1)  0@7392r 1@7424r
7440B	%vreg823<def> = COPY %vreg825:sub_8bit; GR8:%vreg823 GR32:%vreg825
	Considering merging to GR32 with %vreg823 in %vreg825:sub_8bit
		RHS = %vreg823 [7440r,7456r:0)  0@7440r
		LHS = %vreg825 [7392r,7424r:0)[7424r,7440r:1)  0@7392r 1@7424r
		merge %vreg823:0@7440r into %vreg825:1@7424r --> @7424r
		erased:	7440r	%vreg823<def> = COPY %vreg825:sub_8bit; GR8:%vreg823 GR32:%vreg825
		updated: 7456B	%vreg821<def> = MOVZX32rr8 %vreg825:sub_8bit; GR32:%vreg821,%vreg825
	Success: %vreg823:sub_8bit -> %vreg825
	Result = %vreg825 [7392r,7424r:0)[7424r,7456r:1)  0@7392r 1@7424r
7536B	%vreg814<def> = COPY %vreg815; GR32:%vreg814,%vreg815
	Considering merging to GR32 with %vreg815 in %vreg814
		RHS = %vreg815 [7520r,7536r:0)  0@7520r
		LHS = %vreg814 [7536r,7552r:0)[7552r,7568r:1)  0@7536r 1@7552r
		merge %vreg814:0@7536r into %vreg815:0@7520r --> @7520r
		erased:	7536r	%vreg814<def> = COPY %vreg815; GR32:%vreg814,%vreg815
		updated: 7520B	%vreg814<def> = MOV32rm %vreg816, 1, %noreg, 60, %noreg; mem:LD4[%tPos247] GR32:%vreg814 GR64:%vreg816
	Success: %vreg815 -> %vreg814
	Result = %vreg814 [7520r,7552r:0)[7552r,7568r:1)  0@7520r 1@7552r
1632B	%vreg447<def> = COPY %vreg449; GR32:%vreg447,%vreg449
	Considering merging to GR32 with %vreg449 in %vreg447
		RHS = %vreg449 [1616r,1632r:0)  0@1616r
		LHS = %vreg447 [1632r,1648r:0)[1648r,1664r:1)  0@1632r 1@1648r
		merge %vreg447:0@1632r into %vreg449:0@1616r --> @1616r
		erased:	1632r	%vreg447<def> = COPY %vreg449; GR32:%vreg447,%vreg449
		updated: 1616B	%vreg447<def> = MOV32rm %vreg450, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock] GR32:%vreg447 GR64:%vreg450
	Success: %vreg449 -> %vreg447
	Result = %vreg447 [1616r,1648r:0)[1648r,1664r:1)  0@1616r 1@1648r
1824B	%vreg457<def> = COPY %vreg459; GR32:%vreg457,%vreg459
	Considering merging to GR32 with %vreg459 in %vreg457
		RHS = %vreg459 [1808r,1824r:0)  0@1808r
		LHS = %vreg457 [1824r,1840r:0)[1840r,1856r:1)  0@1824r 1@1840r
		merge %vreg457:0@1824r into %vreg459:0@1808r --> @1808r
		erased:	1824r	%vreg457<def> = COPY %vreg459; GR32:%vreg457,%vreg459
		updated: 1808B	%vreg457<def> = MOV32rm %vreg460, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock32] GR32:%vreg457 GR64:%vreg460
	Success: %vreg459 -> %vreg457
	Result = %vreg457 [1808r,1840r:0)[1840r,1856r:1)  0@1808r 1@1840r
2016B	%vreg499<def> = COPY %vreg501:sub_8bit; GR8:%vreg499 GR32:%vreg501
	Considering merging to GR32 with %vreg499 in %vreg501:sub_8bit
		RHS = %vreg499 [2016r,2048r:0)  0@2016r
		LHS = %vreg501 [2000r,2016r:0)  0@2000r
		merge %vreg499:0@2016r into %vreg501:0@2000r --> @2000r
		erased:	2016r	%vreg499<def> = COPY %vreg501:sub_8bit; GR8:%vreg499 GR32:%vreg501
		updated: 2048B	MOV8mr %vreg497, 1, %noreg, 12, %noreg, %vreg501:sub_8bit; mem:ST1[%state_out_ch40] GR64:%vreg497 GR32:%vreg501
	Success: %vreg499:sub_8bit -> %vreg501
	Result = %vreg501 [2000r,2048r:0)  0@2000r
2224B	%vreg477<def> = COPY %vreg479; GR32:%vreg477,%vreg479
	Considering merging to GR32 with %vreg479 in %vreg477
		RHS = %vreg479 [2208r,2224r:0)  0@2208r
		LHS = %vreg477 [2224r,2240r:0)[2240r,2256r:1)  0@2224r 1@2240r
		merge %vreg477:0@2224r into %vreg479:0@2208r --> @2208r
		erased:	2224r	%vreg477<def> = COPY %vreg479; GR32:%vreg477,%vreg479
		updated: 2208B	%vreg477<def> = MOV32rm %vreg480, 1, %noreg, 60, %noreg; mem:LD4[%tPos44] GR32:%vreg477 GR64:%vreg480
	Success: %vreg479 -> %vreg477
	Result = %vreg477 [2208r,2240r:0)[2240r,2256r:1)  0@2208r 1@2240r
2256B	%vreg475<def> = COPY %vreg477:sub_8bit; GR8:%vreg475 GR32:%vreg477
	Considering merging to GR32 with %vreg475 in %vreg477:sub_8bit
		RHS = %vreg475 [2256r,2272r:0)  0@2256r
		LHS = %vreg477 [2208r,2240r:0)[2240r,2256r:1)  0@2208r 1@2240r
		merge %vreg475:0@2256r into %vreg477:1@2240r --> @2240r
		erased:	2256r	%vreg475<def> = COPY %vreg477:sub_8bit; GR8:%vreg475 GR32:%vreg477
		updated: 2272B	MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg477:sub_8bit; mem:ST1[%k1] GR32:%vreg477
	Success: %vreg475:sub_8bit -> %vreg477
	Result = %vreg477 [2208r,2240r:0)[2240r,2272r:1)  0@2208r 1@2240r
2320B	%vreg470<def> = COPY %vreg471; GR32:%vreg470,%vreg471
	Considering merging to GR32 with %vreg471 in %vreg470
		RHS = %vreg471 [2304r,2320r:0)  0@2304r
		LHS = %vreg470 [2320r,2336r:0)[2336r,2352r:1)  0@2320r 1@2336r
		merge %vreg470:0@2320r into %vreg471:0@2304r --> @2304r
		erased:	2320r	%vreg470<def> = COPY %vreg471; GR32:%vreg470,%vreg471
		updated: 2304B	%vreg470<def> = MOV32rm %vreg472, 1, %noreg, 60, %noreg; mem:LD4[%tPos46] GR32:%vreg470 GR64:%vreg472
	Success: %vreg471 -> %vreg470
	Result = %vreg470 [2304r,2336r:0)[2336r,2352r:1)  0@2304r 1@2336r
2544B	%vreg511<def> = COPY %vreg512; GR32:%vreg511,%vreg512
	Considering merging to GR32 with %vreg512 in %vreg511
		RHS = %vreg512 [2528r,2544r:0)  0@2528r
		LHS = %vreg511 [2544r,2560r:0)[2560r,2576r:1)  0@2544r 1@2560r
		merge %vreg511:0@2544r into %vreg512:0@2528r --> @2528r
		erased:	2544r	%vreg511<def> = COPY %vreg512; GR32:%vreg511,%vreg512
		updated: 2528B	%vreg511<def> = MOV32rm %vreg513, 1, %noreg, 28, %noreg; mem:LD4[%rTPos54] GR32:%vreg511 GR64:%vreg513
	Success: %vreg512 -> %vreg511
	Result = %vreg511 [2528r,2560r:0)[2560r,2576r:1)  0@2528r 1@2560r
3600B	%vreg580<def> = COPY %vreg582; GR32:%vreg580,%vreg582
	Considering merging to GR32 with %vreg582 in %vreg580
		RHS = %vreg582 [3584r,3600r:0)  0@3584r
		LHS = %vreg580 [3600r,3616r:0)[3616r,3632r:1)  0@3600r 1@3616r
		merge %vreg580:0@3600r into %vreg582:0@3584r --> @3584r
		erased:	3600r	%vreg580<def> = COPY %vreg582; GR32:%vreg580,%vreg582
		updated: 3584B	%vreg580<def> = MOV32rm %vreg583, 1, %noreg, 60, %noreg; mem:LD4[%tPos94] GR32:%vreg580 GR64:%vreg583
	Success: %vreg582 -> %vreg580
	Result = %vreg580 [3584r,3616r:0)[3616r,3632r:1)  0@3584r 1@3616r
3632B	%vreg578<def> = COPY %vreg580:sub_8bit; GR8:%vreg578 GR32:%vreg580
	Considering merging to GR32 with %vreg578 in %vreg580:sub_8bit
		RHS = %vreg578 [3632r,3648r:0)  0@3632r
		LHS = %vreg580 [3584r,3616r:0)[3616r,3632r:1)  0@3584r 1@3616r
		merge %vreg578:0@3632r into %vreg580:1@3616r --> @3616r
		erased:	3632r	%vreg578<def> = COPY %vreg580:sub_8bit; GR8:%vreg578 GR32:%vreg580
		updated: 3648B	MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg580:sub_8bit; mem:ST1[%k1] GR32:%vreg580
	Success: %vreg578:sub_8bit -> %vreg580
	Result = %vreg580 [3584r,3616r:0)[3616r,3648r:1)  0@3584r 1@3616r
3696B	%vreg573<def> = COPY %vreg574; GR32:%vreg573,%vreg574
	Considering merging to GR32 with %vreg574 in %vreg573
		RHS = %vreg574 [3680r,3696r:0)  0@3680r
		LHS = %vreg573 [3696r,3712r:0)[3712r,3728r:1)  0@3696r 1@3712r
		merge %vreg573:0@3696r into %vreg574:0@3680r --> @3680r
		erased:	3696r	%vreg573<def> = COPY %vreg574; GR32:%vreg573,%vreg574
		updated: 3680B	%vreg573<def> = MOV32rm %vreg575, 1, %noreg, 60, %noreg; mem:LD4[%tPos97] GR32:%vreg573 GR64:%vreg575
	Success: %vreg574 -> %vreg573
	Result = %vreg573 [3680r,3712r:0)[3712r,3728r:1)  0@3680r 1@3712r
3920B	%vreg606<def> = COPY %vreg607; GR32:%vreg606,%vreg607
	Considering merging to GR32 with %vreg607 in %vreg606
		RHS = %vreg607 [3904r,3920r:0)  0@3904r
		LHS = %vreg606 [3920r,3936r:0)[3936r,3952r:1)  0@3920r 1@3936r
		merge %vreg606:0@3920r into %vreg607:0@3904r --> @3904r
		erased:	3920r	%vreg606<def> = COPY %vreg607; GR32:%vreg606,%vreg607
		updated: 3904B	%vreg606<def> = MOV32rm %vreg608, 1, %noreg, 28, %noreg; mem:LD4[%rTPos107] GR32:%vreg606 GR64:%vreg608
	Success: %vreg607 -> %vreg606
	Result = %vreg606 [3904r,3936r:0)[3936r,3952r:1)  0@3904r 1@3936r
4976B	%vreg675<def> = COPY %vreg677; GR32:%vreg675,%vreg677
	Considering merging to GR32 with %vreg677 in %vreg675
		RHS = %vreg677 [4960r,4976r:0)  0@4960r
		LHS = %vreg675 [4976r,4992r:0)[4992r,5008r:1)  0@4976r 1@4992r
		merge %vreg675:0@4976r into %vreg677:0@4960r --> @4960r
		erased:	4976r	%vreg675<def> = COPY %vreg677; GR32:%vreg675,%vreg677
		updated: 4960B	%vreg675<def> = MOV32rm %vreg678, 1, %noreg, 60, %noreg; mem:LD4[%tPos148] GR32:%vreg675 GR64:%vreg678
	Success: %vreg677 -> %vreg675
	Result = %vreg675 [4960r,4992r:0)[4992r,5008r:1)  0@4960r 1@4992r
5008B	%vreg673<def> = COPY %vreg675:sub_8bit; GR8:%vreg673 GR32:%vreg675
	Considering merging to GR32 with %vreg673 in %vreg675:sub_8bit
		RHS = %vreg673 [5008r,5024r:0)  0@5008r
		LHS = %vreg675 [4960r,4992r:0)[4992r,5008r:1)  0@4960r 1@4992r
		merge %vreg673:0@5008r into %vreg675:1@4992r --> @4992r
		erased:	5008r	%vreg673<def> = COPY %vreg675:sub_8bit; GR8:%vreg673 GR32:%vreg675
		updated: 5024B	MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg675:sub_8bit; mem:ST1[%k1] GR32:%vreg675
	Success: %vreg673:sub_8bit -> %vreg675
	Result = %vreg675 [4960r,4992r:0)[4992r,5024r:1)  0@4960r 1@4992r
5072B	%vreg668<def> = COPY %vreg669; GR32:%vreg668,%vreg669
	Considering merging to GR32 with %vreg669 in %vreg668
		RHS = %vreg669 [5056r,5072r:0)  0@5056r
		LHS = %vreg668 [5072r,5088r:0)[5088r,5104r:1)  0@5072r 1@5088r
		merge %vreg668:0@5072r into %vreg669:0@5056r --> @5056r
		erased:	5072r	%vreg668<def> = COPY %vreg669; GR32:%vreg668,%vreg669
		updated: 5056B	%vreg668<def> = MOV32rm %vreg670, 1, %noreg, 60, %noreg; mem:LD4[%tPos151] GR32:%vreg668 GR64:%vreg670
	Success: %vreg669 -> %vreg668
	Result = %vreg668 [5056r,5088r:0)[5088r,5104r:1)  0@5056r 1@5088r
5296B	%vreg701<def> = COPY %vreg702; GR32:%vreg701,%vreg702
	Considering merging to GR32 with %vreg702 in %vreg701
		RHS = %vreg702 [5280r,5296r:0)  0@5280r
		LHS = %vreg701 [5296r,5312r:0)[5312r,5328r:1)  0@5296r 1@5312r
		merge %vreg701:0@5296r into %vreg702:0@5280r --> @5280r
		erased:	5296r	%vreg701<def> = COPY %vreg702; GR32:%vreg701,%vreg702
		updated: 5280B	%vreg701<def> = MOV32rm %vreg703, 1, %noreg, 28, %noreg; mem:LD4[%rTPos161] GR32:%vreg701 GR64:%vreg703
	Success: %vreg702 -> %vreg701
	Result = %vreg701 [5280r,5312r:0)[5312r,5328r:1)  0@5280r 1@5312r
6320B	%vreg770<def> = COPY %vreg772; GR32:%vreg770,%vreg772
	Considering merging to GR32 with %vreg772 in %vreg770
		RHS = %vreg772 [6304r,6320r:0)  0@6304r
		LHS = %vreg770 [6320r,6336r:0)[6336r,6352r:1)  0@6320r 1@6336r
		merge %vreg770:0@6320r into %vreg772:0@6304r --> @6304r
		erased:	6320r	%vreg770<def> = COPY %vreg772; GR32:%vreg770,%vreg772
		updated: 6304B	%vreg770<def> = MOV32rm %vreg773, 1, %noreg, 60, %noreg; mem:LD4[%tPos201] GR32:%vreg770 GR64:%vreg773
	Success: %vreg772 -> %vreg770
	Result = %vreg770 [6304r,6336r:0)[6336r,6352r:1)  0@6304r 1@6336r
6352B	%vreg768<def> = COPY %vreg770:sub_8bit; GR8:%vreg768 GR32:%vreg770
	Considering merging to GR32 with %vreg768 in %vreg770:sub_8bit
		RHS = %vreg768 [6352r,6368r:0)  0@6352r
		LHS = %vreg770 [6304r,6336r:0)[6336r,6352r:1)  0@6304r 1@6336r
		merge %vreg768:0@6352r into %vreg770:1@6336r --> @6336r
		erased:	6352r	%vreg768<def> = COPY %vreg770:sub_8bit; GR8:%vreg768 GR32:%vreg770
		updated: 6368B	MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg770:sub_8bit; mem:ST1[%k1] GR32:%vreg770
	Success: %vreg768:sub_8bit -> %vreg770
	Result = %vreg770 [6304r,6336r:0)[6336r,6368r:1)  0@6304r 1@6336r
6416B	%vreg763<def> = COPY %vreg764; GR32:%vreg763,%vreg764
	Considering merging to GR32 with %vreg764 in %vreg763
		RHS = %vreg764 [6400r,6416r:0)  0@6400r
		LHS = %vreg763 [6416r,6432r:0)[6432r,6448r:1)  0@6416r 1@6432r
		merge %vreg763:0@6416r into %vreg764:0@6400r --> @6400r
		erased:	6416r	%vreg763<def> = COPY %vreg764; GR32:%vreg763,%vreg764
		updated: 6400B	%vreg763<def> = MOV32rm %vreg765, 1, %noreg, 60, %noreg; mem:LD4[%tPos204] GR32:%vreg763 GR64:%vreg765
	Success: %vreg764 -> %vreg763
	Result = %vreg763 [6400r,6432r:0)[6432r,6448r:1)  0@6400r 1@6432r
6640B	%vreg794<def> = COPY %vreg795; GR32:%vreg794,%vreg795
	Considering merging to GR32 with %vreg795 in %vreg794
		RHS = %vreg795 [6624r,6640r:0)  0@6624r
		LHS = %vreg794 [6640r,6656r:0)[6656r,6672r:1)  0@6640r 1@6656r
		merge %vreg794:0@6640r into %vreg795:0@6624r --> @6624r
		erased:	6640r	%vreg794<def> = COPY %vreg795; GR32:%vreg794,%vreg795
		updated: 6624B	%vreg794<def> = MOV32rm %vreg796, 1, %noreg, 28, %noreg; mem:LD4[%rTPos214] GR32:%vreg794 GR64:%vreg796
	Success: %vreg795 -> %vreg794
	Result = %vreg794 [6624r,6656r:0)[6656r,6672r:1)  0@6624r 1@6656r
7760B	%vreg882<def> = COPY %vreg883; GR32:%vreg882,%vreg883
	Considering merging to GR32 with %vreg883 in %vreg882
		RHS = %vreg883 [7744r,7760r:0)  0@7744r
		LHS = %vreg882 [7760r,7776r:0)[7776r,7792r:1)  0@7760r 1@7776r
		merge %vreg882:0@7760r into %vreg883:0@7744r --> @7744r
		erased:	7760r	%vreg882<def> = COPY %vreg883; GR32:%vreg882,%vreg883
		updated: 7744B	%vreg882<def> = MOV32rm %vreg884, 1, %noreg, 28, %noreg; mem:LD4[%rTPos257] GR32:%vreg882 GR64:%vreg884
	Success: %vreg883 -> %vreg882
	Result = %vreg882 [7744r,7776r:0)[7776r,7792r:1)  0@7744r 1@7776r
8016B	%vreg917<def> = COPY %vreg918; GR32:%vreg917,%vreg918
	Considering merging to GR32 with %vreg918 in %vreg917
		RHS = %vreg918 [8000r,8016r:0)  0@8000r
		LHS = %vreg917 [8016r,8032r:0)[8032r,8048r:1)  0@8016r 1@8032r
		merge %vreg917:0@8016r into %vreg918:0@8000r --> @8000r
		erased:	8016r	%vreg917<def> = COPY %vreg918; GR32:%vreg917,%vreg918
		updated: 8000B	%vreg917<def> = MOV32rm %vreg919, 1, %noreg, 24, %noreg; mem:LD4[%rNToGo266] GR32:%vreg917 GR64:%vreg919
	Success: %vreg918 -> %vreg917
	Result = %vreg917 [8000r,8032r:0)[8032r,8048r:1)  0@8000r 1@8032r
8096B	%vreg911<def> = COPY %vreg909; GR32:%vreg911,%vreg909
	Considering merging to GR32 with %vreg909 in %vreg911
		RHS = %vreg909 [7952r,8096r:0)  0@7952r
		LHS = %vreg911 [8096r,8112r:0)[8112r,8144r:1)  0@8096r 1@8112r
		merge %vreg911:0@8096r into %vreg909:0@7952r --> @7952r
		erased:	8096r	%vreg911<def> = COPY %vreg909; GR32:%vreg911,%vreg909
		updated: 7952B	%vreg911<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg911
	Success: %vreg909 -> %vreg911
	Result = %vreg911 [7952r,8112r:0)[8112r,8144r:1)  0@7952r 1@8112r
8144B	%vreg906<def> = COPY %vreg911; GR32:%vreg906,%vreg911
	Considering merging to GR32 with %vreg911 in %vreg906
		RHS = %vreg911 [7952r,8112r:0)[8112r,8144r:1)  0@7952r 1@8112r
		LHS = %vreg906 [8144r,8160r:0)[8160r,8176r:1)  0@8144r 1@8160r
		merge %vreg906:0@8144r into %vreg911:1@8112r --> @8112r
		erased:	8144r	%vreg906<def> = COPY %vreg911; GR32:%vreg906,%vreg911
		updated: 7952B	%vreg906<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg906
		updated: 8112B	%vreg906<def,tied1> = CMOVE32rr %vreg906<tied0>, %vreg910, %EFLAGS<imp-use,kill>; GR32:%vreg906,%vreg910
	Success: %vreg911 -> %vreg906
	Result = %vreg906 [7952r,8112r:2)[8112r,8160r:0)[8160r,8176r:1)  0@8112r 1@8160r 2@7952r
8224B	%vreg899<def> = COPY %vreg900; GR32:%vreg899,%vreg900
	Considering merging to GR32 with %vreg900 in %vreg899
		RHS = %vreg900 [8208r,8224r:0)  0@8208r
		LHS = %vreg899 [8224r,8240r:0)[8240r,8256r:1)  0@8224r 1@8240r
		merge %vreg899:0@8224r into %vreg900:0@8208r --> @8208r
		erased:	8224r	%vreg899<def> = COPY %vreg900; GR32:%vreg899,%vreg900
		updated: 8208B	%vreg899<def> = MOV32rm %vreg901, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used274] GR32:%vreg899 GR64:%vreg901
	Success: %vreg900 -> %vreg899
	Result = %vreg899 [8208r,8240r:0)[8240r,8256r:1)  0@8208r 1@8240r
10416B	%vreg160<def> = COPY %vreg161:sub_8bit; GR8:%vreg160 GR32:%vreg161
	Considering merging to GR32 with %vreg160 in %vreg161:sub_8bit
		RHS = %vreg160 [10416r,10432r:0)  0@10416r
		LHS = %vreg161 [10400r,10416r:0)  0@10400r
		merge %vreg160:0@10416r into %vreg161:0@10400r --> @10400r
		erased:	10416r	%vreg160<def> = COPY %vreg161:sub_8bit; GR8:%vreg160 GR32:%vreg161
		updated: 10432B	MOV8mr <fi#4>, 1, %noreg, 0, %noreg, %vreg161:sub_8bit; mem:ST1[%c_state_out_ch] GR32:%vreg161
	Success: %vreg160:sub_8bit -> %vreg161
	Result = %vreg161 [10400r,10432r:0)  0@10400r
10544B	%vreg148<def> = COPY %vreg149; GR32:%vreg148,%vreg149
	Considering merging to GR32 with %vreg149 in %vreg148
		RHS = %vreg149 [10528r,10544r:0)  0@10528r
		LHS = %vreg148 [10544r,10560r:0)[10560r,10576r:1)  0@10544r 1@10560r
		merge %vreg148:0@10544r into %vreg149:0@10528r --> @10528r
		erased:	10544r	%vreg148<def> = COPY %vreg149; GR32:%vreg148,%vreg149
		updated: 10528B	%vreg148<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR32:%vreg148
	Success: %vreg149 -> %vreg148
	Result = %vreg148 [10528r,10560r:0)[10560r,10576r:1)  0@10528r 1@10560r
10576B	%vreg146<def> = COPY %vreg148:sub_8bit; GR8:%vreg146 GR32:%vreg148
	Considering merging to GR32 with %vreg146 in %vreg148:sub_8bit
		RHS = %vreg146 [10576r,10592r:0)  0@10576r
		LHS = %vreg148 [10528r,10560r:0)[10560r,10576r:1)  0@10528r 1@10560r
		merge %vreg146:0@10576r into %vreg148:1@10560r --> @10560r
		erased:	10576r	%vreg146<def> = COPY %vreg148:sub_8bit; GR8:%vreg146 GR32:%vreg148
		updated: 10592B	MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg148:sub_8bit; mem:ST1[%k1] GR32:%vreg148
	Success: %vreg146:sub_8bit -> %vreg148
	Result = %vreg148 [10528r,10560r:0)[10560r,10592r:1)  0@10528r 1@10560r
10624B	%vreg142<def> = COPY %vreg143; GR32:%vreg142,%vreg143
	Considering merging to GR32 with %vreg143 in %vreg142
		RHS = %vreg143 [10608r,10624r:0)  0@10608r
		LHS = %vreg142 [10624r,10640r:0)[10640r,10656r:1)  0@10624r 1@10640r
		merge %vreg142:0@10624r into %vreg143:0@10608r --> @10608r
		erased:	10624r	%vreg142<def> = COPY %vreg143; GR32:%vreg142,%vreg143
		updated: 10608B	%vreg142<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR32:%vreg142
	Success: %vreg143 -> %vreg142
	Result = %vreg142 [10608r,10640r:0)[10640r,10656r:1)  0@10608r 1@10640r
10688B	%vreg138<def> = COPY %vreg139; GR32:%vreg138,%vreg139
	Considering merging to GR32 with %vreg139 in %vreg138
		RHS = %vreg139 [10672r,10688r:0)  0@10672r
		LHS = %vreg138 [10688r,10704r:0)[10704r,10720r:1)  0@10688r 1@10704r
		merge %vreg138:0@10688r into %vreg139:0@10672r --> @10672r
		erased:	10688r	%vreg138<def> = COPY %vreg139; GR32:%vreg138,%vreg139
		updated: 10672B	%vreg138<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%c_nblock_used] GR32:%vreg138
	Success: %vreg139 -> %vreg138
	Result = %vreg138 [10672r,10704r:0)[10704r,10720r:1)  0@10672r 1@10704r
11072B	%vreg180<def> = COPY %vreg181; GR32:%vreg180,%vreg181
	Considering merging to GR32 with %vreg181 in %vreg180
		RHS = %vreg181 [11056r,11072r:0)  0@11056r
		LHS = %vreg180 [11072r,11088r:0)[11088r,11104r:1)  0@11072r 1@11088r
		merge %vreg180:0@11072r into %vreg181:0@11056r --> @11056r
		erased:	11072r	%vreg180<def> = COPY %vreg181; GR32:%vreg180,%vreg181
		updated: 11056B	%vreg180<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR32:%vreg180
	Success: %vreg181 -> %vreg180
	Result = %vreg180 [11056r,11088r:0)[11088r,11104r:1)  0@11056r 1@11088r
11104B	%vreg178<def> = COPY %vreg180:sub_8bit; GR8:%vreg178 GR32:%vreg180
	Considering merging to GR32 with %vreg178 in %vreg180:sub_8bit
		RHS = %vreg178 [11104r,11120r:0)  0@11104r
		LHS = %vreg180 [11056r,11088r:0)[11088r,11104r:1)  0@11056r 1@11088r
		merge %vreg178:0@11104r into %vreg180:1@11088r --> @11088r
		erased:	11104r	%vreg178<def> = COPY %vreg180:sub_8bit; GR8:%vreg178 GR32:%vreg180
		updated: 11120B	MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg180:sub_8bit; mem:ST1[%k1] GR32:%vreg180
	Success: %vreg178:sub_8bit -> %vreg180
	Result = %vreg180 [11056r,11088r:0)[11088r,11120r:1)  0@11056r 1@11088r
11152B	%vreg174<def> = COPY %vreg175; GR32:%vreg174,%vreg175
	Considering merging to GR32 with %vreg175 in %vreg174
		RHS = %vreg175 [11136r,11152r:0)  0@11136r
		LHS = %vreg174 [11152r,11168r:0)[11168r,11184r:1)  0@11152r 1@11168r
		merge %vreg174:0@11152r into %vreg175:0@11136r --> @11136r
		erased:	11152r	%vreg174<def> = COPY %vreg175; GR32:%vreg174,%vreg175
		updated: 11136B	%vreg174<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR32:%vreg174
	Success: %vreg175 -> %vreg174
	Result = %vreg174 [11136r,11168r:0)[11168r,11184r:1)  0@11136r 1@11168r
11216B	%vreg170<def> = COPY %vreg171; GR32:%vreg170,%vreg171
	Considering merging to GR32 with %vreg171 in %vreg170
		RHS = %vreg171 [11200r,11216r:0)  0@11200r
		LHS = %vreg170 [11216r,11232r:0)[11232r,11248r:1)  0@11216r 1@11232r
		merge %vreg170:0@11216r into %vreg171:0@11200r --> @11200r
		erased:	11216r	%vreg170<def> = COPY %vreg171; GR32:%vreg170,%vreg171
		updated: 11200B	%vreg170<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%c_nblock_used] GR32:%vreg170
	Success: %vreg171 -> %vreg170
	Result = %vreg170 [11200r,11232r:0)[11232r,11248r:1)  0@11200r 1@11232r
11600B	%vreg209<def> = COPY %vreg210; GR32:%vreg209,%vreg210
	Considering merging to GR32 with %vreg210 in %vreg209
		RHS = %vreg210 [11584r,11600r:0)  0@11584r
		LHS = %vreg209 [11600r,11616r:0)[11616r,11632r:1)  0@11600r 1@11616r
		merge %vreg209:0@11600r into %vreg210:0@11584r --> @11584r
		erased:	11600r	%vreg209<def> = COPY %vreg210; GR32:%vreg209,%vreg210
		updated: 11584B	%vreg209<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR32:%vreg209
	Success: %vreg210 -> %vreg209
	Result = %vreg209 [11584r,11616r:0)[11616r,11632r:1)  0@11584r 1@11616r
11632B	%vreg207<def> = COPY %vreg209:sub_8bit; GR8:%vreg207 GR32:%vreg209
	Considering merging to GR32 with %vreg207 in %vreg209:sub_8bit
		RHS = %vreg207 [11632r,11648r:0)  0@11632r
		LHS = %vreg209 [11584r,11616r:0)[11616r,11632r:1)  0@11584r 1@11616r
		merge %vreg207:0@11632r into %vreg209:1@11616r --> @11616r
		erased:	11632r	%vreg207<def> = COPY %vreg209:sub_8bit; GR8:%vreg207 GR32:%vreg209
		updated: 11648B	MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg209:sub_8bit; mem:ST1[%k1] GR32:%vreg209
	Success: %vreg207:sub_8bit -> %vreg209
	Result = %vreg209 [11584r,11616r:0)[11616r,11648r:1)  0@11584r 1@11616r
11680B	%vreg203<def> = COPY %vreg204; GR32:%vreg203,%vreg204
	Considering merging to GR32 with %vreg204 in %vreg203
		RHS = %vreg204 [11664r,11680r:0)  0@11664r
		LHS = %vreg203 [11680r,11696r:0)[11696r,11712r:1)  0@11680r 1@11696r
		merge %vreg203:0@11680r into %vreg204:0@11664r --> @11664r
		erased:	11680r	%vreg203<def> = COPY %vreg204; GR32:%vreg203,%vreg204
		updated: 11664B	%vreg203<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR32:%vreg203
	Success: %vreg204 -> %vreg203
	Result = %vreg203 [11664r,11696r:0)[11696r,11712r:1)  0@11664r 1@11696r
11744B	%vreg199<def> = COPY %vreg200; GR32:%vreg199,%vreg200
	Considering merging to GR32 with %vreg200 in %vreg199
		RHS = %vreg200 [11728r,11744r:0)  0@11728r
		LHS = %vreg199 [11744r,11760r:0)[11760r,11776r:1)  0@11744r 1@11760r
		merge %vreg199:0@11744r into %vreg200:0@11728r --> @11728r
		erased:	11744r	%vreg199<def> = COPY %vreg200; GR32:%vreg199,%vreg200
		updated: 11728B	%vreg199<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%c_nblock_used] GR32:%vreg199
	Success: %vreg200 -> %vreg199
	Result = %vreg199 [11728r,11760r:0)[11760r,11776r:1)  0@11728r 1@11760r
9824B	%vreg120<def> = COPY %vreg121; GR32:%vreg120,%vreg121
	Considering merging to GR32 with %vreg121 in %vreg120
		RHS = %vreg121 [9808r,9824r:0)  0@9808r
		LHS = %vreg120 [9824r,9840r:0)[9840r,9984r:1)  0@9824r 1@9840r
		merge %vreg120:0@9824r into %vreg121:0@9808r --> @9808r
		erased:	9824r	%vreg120<def> = COPY %vreg121; GR32:%vreg120,%vreg121
		updated: 9808B	%vreg120<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%c_calculatedBlockCRC] GR32:%vreg120
	Success: %vreg121 -> %vreg120
	Result = %vreg120 [9808r,9840r:0)[9840r,9984r:1)  0@9808r 1@9840r
9872B	%vreg117<def> = COPY %vreg118; GR32:%vreg117,%vreg118
	Considering merging to GR32 with %vreg118 in %vreg117
		RHS = %vreg118 [9856r,9872r:0)  0@9856r
		LHS = %vreg117 [9872r,9888r:0)[9888r,9920r:1)  0@9872r 1@9888r
		merge %vreg117:0@9872r into %vreg118:0@9856r --> @9856r
		erased:	9872r	%vreg117<def> = COPY %vreg118; GR32:%vreg117,%vreg118
		updated: 9856B	%vreg117<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%c_calculatedBlockCRC] GR32:%vreg117
	Success: %vreg118 -> %vreg117
	Result = %vreg117 [9856r,9888r:0)[9888r,9920r:1)  0@9856r 1@9888r
9920B	%vreg113<def> = COPY %vreg117; GR32:%vreg113,%vreg117
	Considering merging to GR32 with %vreg117 in %vreg113
		RHS = %vreg117 [9856r,9888r:0)[9888r,9920r:1)  0@9856r 1@9888r
		LHS = %vreg113 [9920r,9936r:0)[9936r,9952r:1)  0@9920r 1@9936r
		merge %vreg113:0@9920r into %vreg117:1@9888r --> @9888r
		erased:	9920r	%vreg113<def> = COPY %vreg117; GR32:%vreg113,%vreg117
		updated: 9856B	%vreg113<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%c_calculatedBlockCRC] GR32:%vreg113
		updated: 9888B	%vreg113<def,tied1> = SHR32ri %vreg113<tied0>, 24, %EFLAGS<imp-def,dead>; GR32:%vreg113
	Success: %vreg117 -> %vreg113
	Result = %vreg113 [9856r,9888r:2)[9888r,9936r:0)[9936r,9952r:1)  0@9888r 1@9936r 2@9856r
9984B	%vreg106<def> = COPY %vreg120; GR32:%vreg106,%vreg120
	Considering merging to GR32 with %vreg120 in %vreg106
		RHS = %vreg120 [9808r,9840r:0)[9840r,9984r:1)  0@9808r 1@9840r
		LHS = %vreg106 [9984r,10000r:0)[10000r,10016r:1)  0@9984r 1@10000r
		merge %vreg106:0@9984r into %vreg120:1@9840r --> @9840r
		erased:	9984r	%vreg106<def> = COPY %vreg120; GR32:%vreg106,%vreg120
		updated: 9808B	%vreg106<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%c_calculatedBlockCRC] GR32:%vreg106
		updated: 9840B	%vreg106<def,tied1> = SHL32ri %vreg106<tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg106
	Success: %vreg120 -> %vreg106
	Result = %vreg106 [9808r,9840r:2)[9840r,10000r:0)[10000r,10016r:1)  0@9840r 1@10000r 2@9808r
10048B	%vreg101<def> = COPY %vreg102; GR64:%vreg101,%vreg102
	Considering merging to GR64 with %vreg102 in %vreg101
		RHS = %vreg102 [10032r,10048r:0)  0@10032r
		LHS = %vreg101 [10048r,10064r:0)[10064r,10080r:1)  0@10048r 1@10064r
		merge %vreg101:0@10048r into %vreg102:0@10032r --> @10032r
		erased:	10048r	%vreg101<def> = COPY %vreg102; GR64:%vreg101,%vreg102
		updated: 10032B	%vreg101<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%cs_next_out] GR64:%vreg101
	Success: %vreg102 -> %vreg101
	Result = %vreg101 [10032r,10064r:0)[10064r,10080r:1)  0@10032r 1@10064r
10112B	%vreg97<def> = COPY %vreg98; GR32:%vreg97,%vreg98
	Considering merging to GR32 with %vreg98 in %vreg97
		RHS = %vreg98 [10096r,10112r:0)  0@10096r
		LHS = %vreg97 [10112r,10128r:0)[10128r,10144r:1)  0@10112r 1@10128r
		merge %vreg97:0@10112r into %vreg98:0@10096r --> @10096r
		erased:	10112r	%vreg97<def> = COPY %vreg98; GR32:%vreg97,%vreg98
		updated: 10096B	%vreg97<def> = MOV32rm <fi#11>, 1, %noreg, 0, %noreg; mem:LD4[%cs_avail_out] GR32:%vreg97
	Success: %vreg98 -> %vreg97
	Result = %vreg97 [10096r,10128r:0)[10128r,10144r:1)  0@10096r 1@10128r
12112B	%vreg264<def> = COPY %vreg265; GR32:%vreg264,%vreg265
	Considering merging to GR32 with %vreg265 in %vreg264
		RHS = %vreg265 [12096r,12112r:0)  0@12096r
		LHS = %vreg264 [12112r,12128r:0)[12128r,12144r:1)  0@12112r 1@12128r
		merge %vreg264:0@12112r into %vreg265:0@12096r --> @12096r
		erased:	12112r	%vreg264<def> = COPY %vreg265; GR32:%vreg264,%vreg265
		updated: 12096B	%vreg264<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR32:%vreg264
	Success: %vreg265 -> %vreg264
	Result = %vreg264 [12096r,12128r:0)[12128r,12144r:1)  0@12096r 1@12128r
12144B	%vreg262<def> = COPY %vreg264:sub_8bit; GR8:%vreg262 GR32:%vreg264
	Considering merging to GR32 with %vreg262 in %vreg264:sub_8bit
		RHS = %vreg262 [12144r,12160r:0)  0@12144r
		LHS = %vreg264 [12096r,12128r:0)[12128r,12144r:1)  0@12096r 1@12128r
		merge %vreg262:0@12144r into %vreg264:1@12128r --> @12128r
		erased:	12144r	%vreg262<def> = COPY %vreg264:sub_8bit; GR8:%vreg262 GR32:%vreg264
		updated: 12160B	MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg264:sub_8bit; mem:ST1[%k1] GR32:%vreg264
	Success: %vreg262:sub_8bit -> %vreg264
	Result = %vreg264 [12096r,12128r:0)[12128r,12160r:1)  0@12096r 1@12128r
12192B	%vreg258<def> = COPY %vreg259; GR32:%vreg258,%vreg259
	Considering merging to GR32 with %vreg259 in %vreg258
		RHS = %vreg259 [12176r,12192r:0)  0@12176r
		LHS = %vreg258 [12192r,12208r:0)[12208r,12224r:1)  0@12192r 1@12208r
		merge %vreg258:0@12192r into %vreg259:0@12176r --> @12176r
		erased:	12192r	%vreg258<def> = COPY %vreg259; GR32:%vreg258,%vreg259
		updated: 12176B	%vreg258<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR32:%vreg258
	Success: %vreg259 -> %vreg258
	Result = %vreg258 [12176r,12208r:0)[12208r,12224r:1)  0@12176r 1@12208r
12256B	%vreg254<def> = COPY %vreg255; GR32:%vreg254,%vreg255
	Considering merging to GR32 with %vreg255 in %vreg254
		RHS = %vreg255 [12240r,12256r:0)  0@12240r
		LHS = %vreg254 [12256r,12272r:0)[12272r,12288r:1)  0@12256r 1@12272r
		merge %vreg254:0@12256r into %vreg255:0@12240r --> @12240r
		erased:	12256r	%vreg254<def> = COPY %vreg255; GR32:%vreg254,%vreg255
		updated: 12240B	%vreg254<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%c_nblock_used] GR32:%vreg254
	Success: %vreg255 -> %vreg254
	Result = %vreg254 [12240r,12272r:0)[12272r,12288r:1)  0@12240r 1@12272r
12320B	%vreg249<def> = COPY %vreg251; GR32:%vreg249,%vreg251
	Considering merging to GR32 with %vreg251 in %vreg249
		RHS = %vreg251 [12304r,12320r:0)  0@12304r
		LHS = %vreg249 [12320r,12336r:0)[12336r,12352r:1)  0@12320r 1@12336r
		merge %vreg249:0@12320r into %vreg251:0@12304r --> @12304r
		erased:	12320r	%vreg249<def> = COPY %vreg251; GR32:%vreg249,%vreg251
		updated: 12304B	%vreg249<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg249
	Success: %vreg251 -> %vreg249
	Result = %vreg249 [12304r,12336r:0)[12336r,12352r:1)  0@12304r 1@12336r
12464B	%vreg237<def> = COPY %vreg238; GR32:%vreg237,%vreg238
	Considering merging to GR32 with %vreg238 in %vreg237
		RHS = %vreg238 [12448r,12464r:0)  0@12448r
		LHS = %vreg237 [12464r,12480r:0)[12480r,12496r:1)  0@12464r 1@12480r
		merge %vreg237:0@12464r into %vreg238:0@12448r --> @12448r
		erased:	12464r	%vreg237<def> = COPY %vreg238; GR32:%vreg237,%vreg238
		updated: 12448B	%vreg237<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR32:%vreg237
	Success: %vreg238 -> %vreg237
	Result = %vreg237 [12448r,12480r:0)[12480r,12496r:1)  0@12448r 1@12480r
12496B	%vreg235<def> = COPY %vreg237:sub_8bit; GR8:%vreg235 GR32:%vreg237
	Considering merging to GR32 with %vreg235 in %vreg237:sub_8bit
		RHS = %vreg235 [12496r,12512r:0)  0@12496r
		LHS = %vreg237 [12448r,12480r:0)[12480r,12496r:1)  0@12448r 1@12480r
		merge %vreg235:0@12496r into %vreg237:1@12480r --> @12480r
		erased:	12496r	%vreg235<def> = COPY %vreg237:sub_8bit; GR8:%vreg235 GR32:%vreg237
		updated: 12512B	%vreg233<def> = MOVZX32rr8 %vreg237:sub_8bit; GR32:%vreg233,%vreg237
	Success: %vreg235:sub_8bit -> %vreg237
	Result = %vreg237 [12448r,12480r:0)[12480r,12512r:1)  0@12448r 1@12480r
12560B	%vreg229<def> = COPY %vreg230; GR32:%vreg229,%vreg230
	Considering merging to GR32 with %vreg230 in %vreg229
		RHS = %vreg230 [12544r,12560r:0)  0@12544r
		LHS = %vreg229 [12560r,12576r:0)[12576r,12592r:1)  0@12560r 1@12576r
		merge %vreg229:0@12560r into %vreg230:0@12544r --> @12544r
		erased:	12560r	%vreg229<def> = COPY %vreg230; GR32:%vreg229,%vreg230
		updated: 12544B	%vreg229<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR32:%vreg229
	Success: %vreg230 -> %vreg229
	Result = %vreg229 [12544r,12576r:0)[12576r,12592r:1)  0@12544r 1@12576r
12624B	%vreg225<def> = COPY %vreg226; GR32:%vreg225,%vreg226
	Considering merging to GR32 with %vreg226 in %vreg225
		RHS = %vreg226 [12608r,12624r:0)  0@12608r
		LHS = %vreg225 [12624r,12640r:0)[12640r,12656r:1)  0@12624r 1@12640r
		merge %vreg225:0@12624r into %vreg226:0@12608r --> @12608r
		erased:	12624r	%vreg225<def> = COPY %vreg226; GR32:%vreg225,%vreg226
		updated: 12608B	%vreg225<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%c_nblock_used] GR32:%vreg225
	Success: %vreg226 -> %vreg225
	Result = %vreg225 [12608r,12640r:0)[12640r,12656r:1)  0@12608r 1@12640r
return_notr:
return:
13680B	%RDI<def> = COPY %vreg938; GR64:%vreg938
	Considering merging %vreg938 with %RDI
	Can only merge into reserved registers.
13696B	%RSI<def> = COPY %vreg939; GR64:%vreg939
	Considering merging %vreg939 with %RSI
	Can only merge into reserved registers.
13808B	%AL<def> = COPY %vreg936; GR8:%vreg936
	Considering merging %vreg936 with %AL
	Can only merge into reserved registers.
if.end.413:
entry:
16B	%vreg0<def> = COPY %RDI; GR64:%vreg0
	Considering merging %vreg0 with %RDI
	Can only merge into reserved registers.
112B	%RDI<def> = COPY %vreg6; GR64:%vreg6
	Considering merging %vreg6 with %RDI
	Can only merge into reserved registers.
128B	%RSI<def> = COPY %vreg7; GR64:%vreg7
	Considering merging %vreg7 with %RSI
	Can only merge into reserved registers.
if.then:
if.then.3:
if.then.29:
if.then.36:
if.else:
if.then.297:
if.then.316:
if.then.330:
if.then.334:
if.then.409:
if.end.425:
12784B	%vreg300<def> = COPY %vreg301; GR32:%vreg300,%vreg301
	Considering merging to GR32 with %vreg301 in %vreg300
		RHS = %vreg301 [12768r,12784r:0)  0@12768r
		LHS = %vreg300 [12784r,12800r:0)[12800r,12848r:1)  0@12784r 1@12800r
		merge %vreg300:0@12784r into %vreg301:0@12768r --> @12768r
		erased:	12784r	%vreg300<def> = COPY %vreg301; GR32:%vreg300,%vreg301
		updated: 12768B	%vreg300<def> = MOV32rm <fi#12>, 1, %noreg, 0, %noreg; mem:LD4[%avail_out_INIT] GR32:%vreg300
	Success: %vreg301 -> %vreg300
	Result = %vreg300 [12768r,12800r:0)[12800r,12848r:1)  0@12768r 1@12800r
12848B	%vreg294<def> = COPY %vreg300; GR32:%vreg294,%vreg300
	Considering merging to GR32 with %vreg300 in %vreg294
		RHS = %vreg300 [12768r,12800r:0)[12800r,12848r:1)  0@12768r 1@12800r
		LHS = %vreg294 [12848r,12864r:0)[12864r,12880r:1)  0@12848r 1@12864r
		merge %vreg294:0@12848r into %vreg300:1@12800r --> @12800r
		erased:	12848r	%vreg294<def> = COPY %vreg300; GR32:%vreg294,%vreg300
		updated: 12768B	%vreg294<def> = MOV32rm <fi#12>, 1, %noreg, 0, %noreg; mem:LD4[%avail_out_INIT] GR32:%vreg294
		updated: 12800B	%vreg294<def,tied1> = SUB32rm %vreg294<tied0>, <fi#11>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%cs_avail_out] GR32:%vreg294
	Success: %vreg300 -> %vreg294
	Result = %vreg294 [12768r,12800r:2)[12800r,12864r:0)[12864r,12880r:1)  0@12800r 1@12864r 2@12768r
13632B	%vreg938<def> = COPY %vreg937; GR64:%vreg938,%vreg937
	Considering merging to GR64 with %vreg937 in %vreg938
		RHS = %vreg937 [13616r,13632r:0)  0@13616r
		LHS = %vreg938 [13632r,13680r:0)  0@13632r
		merge %vreg938:0@13632r into %vreg937:0@13616r --> @13616r
		erased:	13632r	%vreg938<def> = COPY %vreg937; GR64:%vreg938,%vreg937
		updated: 13616B	%vreg938<def> = MOV64ri <ga:@unRLE_obuf_to_output_FAST>; GR64:%vreg938
	Success: %vreg937 -> %vreg938
	Result = %vreg938 [13616r,13680r:0)  0@13616r
32B	%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
	Considering merging to GR64 with %vreg0 in %vreg1
		RHS = %vreg0 [16r,32r:0)  0@16r
		LHS = %vreg1 [32r,224r:0)  0@32r
		merge %vreg1:0@32r into %vreg0:0@16r --> @16r
		erased:	32r	%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
		updated: 16B	%vreg1<def> = COPY %RDI; GR64:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [16r,224r:0)  0@16r
64B	%vreg6<def> = COPY %vreg5; GR64:%vreg6,%vreg5
	Considering merging to GR64 with %vreg5 in %vreg6
		RHS = %vreg5 [48r,64r:0)  0@48r
		LHS = %vreg6 [64r,112r:0)  0@64r
		merge %vreg6:0@64r into %vreg5:0@48r --> @48r
		erased:	64r	%vreg6<def> = COPY %vreg5; GR64:%vreg6,%vreg5
		updated: 48B	%vreg6<def> = MOV64ri <ga:@unRLE_obuf_to_output_FAST>; GR64:%vreg6
	Success: %vreg5 -> %vreg6
	Result = %vreg6 [48r,112r:0)  0@48r
8832B	%vreg10<def> = COPY %vreg12; GR32:%vreg10,%vreg12
	Considering merging to GR32 with %vreg12 in %vreg10
		RHS = %vreg12 [8816r,8832r:0)  0@8816r
		LHS = %vreg10 [8832r,8848r:0)[8848r,8864r:1)  0@8832r 1@8848r
		merge %vreg10:0@8832r into %vreg12:0@8816r --> @8816r
		erased:	8832r	%vreg10<def> = COPY %vreg12; GR32:%vreg10,%vreg12
		updated: 8816B	%vreg10<def> = MOV32rm %vreg13, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock287] GR32:%vreg10 GR64:%vreg13
	Success: %vreg12 -> %vreg10
	Result = %vreg10 [8816r,8848r:0)[8848r,8864r:1)  0@8816r 1@8848r
13040B	%vreg311<def> = COPY %vreg312; GR32:%vreg311,%vreg312
	Considering merging to GR32 with %vreg312 in %vreg311
		RHS = %vreg312 [13024r,13040r:0)  0@13024r
		LHS = %vreg311 [13040r,13056r:0)[13056r,13072r:1)  0@13040r 1@13056r
		merge %vreg311:0@13040r into %vreg312:0@13024r --> @13024r
		erased:	13040r	%vreg311<def> = COPY %vreg312; GR32:%vreg311,%vreg312
		updated: 13024B	%vreg311<def> = MOV32rm %vreg314, 1, %noreg, 40, %noreg; mem:LD4[%total_out_hi32411] GR32:%vreg311 GR64:%vreg314
	Success: %vreg312 -> %vreg311
	Result = %vreg311 [13024r,13056r:0)[13056r,13072r:1)  0@13024r 1@13056r
13680B	%RDI<def> = COPY %vreg938; GR64:%vreg938
	Considering merging %vreg938 with %RDI
	Can only merge into reserved registers.
112B	%RDI<def> = COPY %vreg6; GR64:%vreg6
	Considering merging %vreg6 with %RDI
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
DIL [0B,16r:0)[112r,144r:2)[13680r,13712r:1)  0@0B-phi 1@13680r 2@112r
%vreg1 [16r,224r:0)  0@16r
%vreg4 [240r,256r:0)  0@240r
%vreg6 [48r,112r:0)  0@48r
%vreg7 [80r,128r:0)  0@80r
%vreg10 [8816r,8848r:0)[8848r,8864r:1)  0@8816r 1@8848r
%vreg13 [8800r,8816r:0)  0@8800r
%vreg15 [8768r,8784r:0)  0@8768r
%vreg18 [8736r,8752r:0)  0@8736r
%vreg20 [8720r,8736r:0)  0@8720r
%vreg21 [8704r,8720r:0)  0@8704r
%vreg24 [8672r,8688r:0)  0@8672r
%vreg26 [8656r,8672r:0)  0@8656r
%vreg27 [8640r,8656r:0)  0@8640r
%vreg30 [8608r,8624r:0)  0@8608r
%vreg31 [8592r,8608r:0)  0@8592r
%vreg34 [8560r,8576r:0)  0@8560r
%vreg35 [8544r,8560r:0)  0@8544r
%vreg38 [8512r,8528r:0)  0@8512r
%vreg39 [8496r,8512r:0)  0@8496r
%vreg42 [8464r,8480r:0)  0@8464r
%vreg43 [8448r,8464r:0)  0@8448r
%vreg46 [8416r,8432r:0)  0@8416r
%vreg47 [8400r,8416r:0)  0@8400r
%vreg50 [8368r,8384r:0)  0@8368r
%vreg51 [8352r,8368r:0)  0@8352r
%vreg54 [8320r,8336r:0)  0@8320r
%vreg55 [8304r,8320r:0)  0@8304r
%vreg61 [9536r,9568r:0)[9568r,9584r:1)  0@9536r 1@9568r
%vreg65 [9472r,9504r:0)[9504r,9520r:1)  0@9472r 1@9504r
%vreg69 [9408r,9440r:0)[9440r,9456r:1)  0@9408r 1@9440r
%vreg74 [9184r,9216r:2)[9216r,9376r:0)[9376r,9392r:1)  0@9216r 1@9376r 2@9184r
%vreg78 [9328r,9376r:0)  0@9328r
%vreg81 [9232r,9264r:2)[9264r,9312r:0)[9312r,9328r:1)  0@9264r 1@9312r 2@9232r
%vreg83 [9280r,9312r:0)  0@9280r
%vreg92 [9152r,9168r:0)  0@9152r
%vreg93 [9136r,9168r:0)  0@9136r
%vreg97 [10096r,10128r:0)[10128r,10144r:1)  0@10096r 1@10128r
%vreg101 [10032r,10064r:0)[10064r,10080r:1)  0@10032r 1@10064r
%vreg106 [9808r,9840r:2)[9840r,10000r:0)[10000r,10016r:1)  0@9840r 1@10000r 2@9808r
%vreg110 [9952r,10000r:0)  0@9952r
%vreg113 [9856r,9888r:2)[9888r,9936r:0)[9936r,9952r:1)  0@9888r 1@9936r 2@9856r
%vreg115 [9904r,9936r:0)  0@9904r
%vreg124 [9776r,9792r:0)  0@9776r
%vreg125 [9760r,9792r:0)  0@9760r
%vreg128 [10176r,10192r:0)  0@10176r
%vreg131 [10288r,10304r:0)  0@10288r
%vreg135 [10736r,10752r:0)  0@10736r
%vreg138 [10672r,10704r:0)[10704r,10720r:1)  0@10672r 1@10704r
%vreg142 [10608r,10640r:0)[10640r,10656r:1)  0@10608r 1@10640r
%vreg148 [10528r,10560r:0)[10560r,10592r:1)  0@10528r 1@10560r
%vreg153 [10496r,10512r:0)  0@10496r
%vreg154 [10480r,10496r:0)  0@10480r
%vreg157 [10448r,10496r:0)  0@10448r
%vreg161 [10400r,10432r:0)  0@10400r
%vreg164 [10864r,10880r:0)  0@10864r
%vreg167 [11264r,11280r:0)  0@11264r
%vreg170 [11200r,11232r:0)[11232r,11248r:1)  0@11200r 1@11232r
%vreg174 [11136r,11168r:0)[11168r,11184r:1)  0@11136r 1@11168r
%vreg180 [11056r,11088r:0)[11088r,11120r:1)  0@11056r 1@11088r
%vreg185 [11024r,11040r:0)  0@11024r
%vreg186 [11008r,11024r:0)  0@11008r
%vreg189 [10976r,11024r:0)  0@10976r
%vreg193 [11360r,11376r:0)  0@11360r
%vreg196 [11792r,11808r:0)  0@11792r
%vreg199 [11728r,11760r:0)[11760r,11776r:1)  0@11728r 1@11760r
%vreg203 [11664r,11696r:0)[11696r,11712r:1)  0@11664r 1@11696r
%vreg209 [11584r,11616r:0)[11616r,11648r:1)  0@11584r 1@11616r
%vreg214 [11552r,11568r:0)  0@11552r
%vreg215 [11536r,11552r:0)  0@11536r
%vreg218 [11504r,11552r:0)  0@11504r
%vreg222 [11888r,11904r:0)  0@11888r
%vreg225 [12608r,12640r:0)[12640r,12656r:1)  0@12608r 1@12640r
%vreg229 [12544r,12576r:0)[12576r,12592r:1)  0@12544r 1@12576r
%vreg233 [12512r,12528r:0)  0@12512r
%vreg237 [12448r,12480r:0)[12480r,12512r:1)  0@12448r 1@12480r
%vreg242 [12416r,12432r:0)  0@12416r
%vreg243 [12400r,12416r:0)  0@12400r
%vreg246 [12368r,12416r:0)  0@12368r
%vreg249 [12304r,12336r:0)[12336r,12352r:1)  0@12304r 1@12336r
%vreg254 [12240r,12272r:0)[12272r,12288r:1)  0@12240r 1@12272r
%vreg258 [12176r,12208r:0)[12208r,12224r:1)  0@12176r 1@12208r
%vreg264 [12096r,12128r:0)[12128r,12160r:1)  0@12096r 1@12128r
%vreg269 [12064r,12080r:0)  0@12064r
%vreg270 [12048r,12064r:0)  0@12048r
%vreg273 [12016r,12064r:0)  0@12016r
%vreg276 [11952r,11968r:0)  0@11952r
%vreg279 [11424r,11440r:0)  0@11424r
%vreg282 [10800r,10816r:0)  0@10800r
%vreg286 [12928r,12944r:0)  0@12928r
%vreg288 [12912r,12928r:0)  0@12912r
%vreg289 [12896r,12912r:0)  0@12896r
%vreg294 [12768r,12800r:2)[12800r,12864r:0)[12864r,12880r:1)  0@12800r 1@12864r 2@12768r
%vreg296 [12832r,12880r:0)  0@12832r
%vreg297 [12816r,12832r:0)  0@12816r
%vreg304 [12736r,12752r:0)  0@12736r
%vreg306 [12720r,12736r:0)  0@12720r
%vreg307 [12704r,12720r:0)  0@12704r
%vreg311 [13024r,13056r:0)[13056r,13072r:1)  0@13024r 1@13056r
%vreg314 [13008r,13072r:0)  0@13008r
%vreg315 [12992r,13008r:0)  0@12992r
%vreg319 [13536r,13552r:0)  0@13536r
%vreg320 [13520r,13536r:0)  0@13520r
%vreg321 [13504r,13552r:0)  0@13504r
%vreg325 [13472r,13488r:0)  0@13472r
%vreg326 [13456r,13472r:0)  0@13456r
%vreg327 [13440r,13488r:0)  0@13440r
%vreg330 [13408r,13424r:0)  0@13408r
%vreg331 [13392r,13424r:0)  0@13392r
%vreg334 [13360r,13376r:0)  0@13360r
%vreg335 [13344r,13376r:0)  0@13344r
%vreg338 [13312r,13328r:0)  0@13312r
%vreg339 [13296r,13328r:0)  0@13296r
%vreg342 [13264r,13280r:0)  0@13264r
%vreg343 [13248r,13280r:0)  0@13248r
%vreg346 [13216r,13232r:0)  0@13216r
%vreg347 [13200r,13232r:0)  0@13200r
%vreg350 [13168r,13184r:0)  0@13168r
%vreg351 [13152r,13184r:0)  0@13152r
%vreg354 [13120r,13136r:0)  0@13120r
%vreg355 [13104r,13136r:0)  0@13104r
%vreg359 [384r,400r:0)  0@384r
%vreg360 [368r,384r:0)  0@368r
%vreg363 [496r,512r:0)  0@496r
%vreg367 [1360r,1376r:0)  0@1360r
%vreg368 [1344r,1360r:0)  0@1344r
%vreg372 [1280r,1312r:0)[1312r,1328r:1)  0@1280r 1@1312r
%vreg375 [1264r,1328r:0)  0@1264r
%vreg376 [1248r,1264r:0)  0@1248r
%vreg380 [1184r,1216r:0)[1216r,1232r:1)  0@1184r 1@1216r
%vreg383 [1168r,1232r:0)  0@1168r
%vreg384 [1152r,1168r:0)  0@1152r
%vreg388 [1088r,1120r:0)[1120r,1136r:1)  0@1088r 1@1120r
%vreg391 [1072r,1136r:0)  0@1072r
%vreg392 [1056r,1072r:0)  0@1056r
%vreg396 [992r,1024r:0)[1024r,1040r:1)  0@992r 1@1024r
%vreg398 [976r,1040r:0)  0@976r
%vreg401 [944r,960r:0)  0@944r
%vreg404 [704r,736r:2)[736r,928r:0)[928r,960r:1)  0@736r 1@928r 2@704r
%vreg408 [880r,928r:0)  0@880r
%vreg411 [768r,800r:2)[800r,864r:0)[864r,880r:1)  0@800r 1@864r 2@768r
%vreg413 [832r,864r:0)  0@832r
%vreg415 [816r,832r:0)  0@816r
%vreg420 [752r,768r:0)  0@752r
%vreg425 [688r,704r:0)  0@688r
%vreg429 [656r,672r:0)  0@656r
%vreg431 [640r,656r:0)  0@640r
%vreg432 [624r,640r:0)  0@624r
%vreg434 [608r,672r:0)  0@608r
%vreg435 [592r,608r:0)  0@592r
%vreg439 [1456r,1488r:0)[1488r,1504r:1)  0@1456r 1@1488r
%vreg442 [1440r,1504r:0)  0@1440r
%vreg443 [1424r,1440r:0)  0@1424r
%vreg447 [1616r,1648r:0)[1648r,1664r:1)  0@1616r 1@1648r
%vreg450 [1600r,1616r:0)  0@1600r
%vreg452 [1584r,1664r:0)  0@1584r
%vreg453 [1568r,1584r:0)  0@1568r
%vreg457 [1808r,1840r:0)[1840r,1856r:1)  0@1808r 1@1840r
%vreg460 [1792r,1808r:0)  0@1792r
%vreg462 [1776r,1856r:0)  0@1776r
%vreg463 [1760r,1776r:0)  0@1760r
%vreg466 [2368r,2384r:0)  0@2368r
%vreg470 [2304r,2336r:0)[2336r,2352r:1)  0@2304r 1@2336r
%vreg472 [2288r,2352r:0)  0@2288r
%vreg477 [2208r,2240r:0)[2240r,2272r:1)  0@2208r 1@2240r
%vreg480 [2192r,2208r:0)  0@2192r
%vreg483 [2160r,2176r:0)  0@2160r
%vreg486 [2144r,2176r:0)  0@2144r
%vreg488 [2128r,2144r:0)  0@2128r
%vreg489 [2112r,2128r:0)  0@2112r
%vreg492 [2080r,2144r:0)  0@2080r
%vreg494 [2064r,2080r:0)  0@2064r
%vreg497 [2032r,2048r:0)  0@2032r
%vreg501 [2000r,2048r:0)  0@2000r
%vreg502 [1984r,2000r:0)  0@1984r
%vreg504 [1952r,1968r:0)  0@1952r
%vreg507 [2592r,2608r:0)  0@2592r
%vreg511 [2528r,2560r:0)[2560r,2576r:1)  0@2528r 1@2560r
%vreg513 [2512r,2576r:0)  0@2512r
%vreg516 [2480r,2496r:0)  0@2480r
%vreg518 [2464r,2496r:0)  0@2464r
%vreg520 [2448r,2464r:0)  0@2448r
%vreg522 [2432r,2448r:0)  0@2432r
%vreg524 [2656r,2672r:0)  0@2656r
%vreg528 [3120r,3152r:0)[3152r,3168r:1)  0@3120r 1@3152r
%vreg531 [3104r,3120r:0)  0@3104r
%vreg533 [3088r,3168r:0)  0@3088r
%vreg534 [3072r,3088r:0)  0@3072r
%vreg538 [3008r,3040r:0)[3040r,3056r:1)  0@3008r 1@3040r
%vreg540 [2992r,3056r:0)  0@2992r
%vreg546 [2912r,2944r:0)[2944r,2976r:1)  0@2912r 1@2944r
%vreg551 [2752r,2896r:0)  0@2752r
%vreg552 [2736r,2896r:0)[2896r,2944r:1)  0@2736r 1@2896r
%vreg554 [2848r,2864r:0)  0@2848r
%vreg558 [2784r,2816r:0)[2816r,2832r:1)  0@2784r 1@2816r
%vreg560 [2768r,2832r:0)  0@2768r
%vreg564 [3264r,3280r:0)  0@3264r
%vreg566 [3248r,3280r:0)  0@3248r
%vreg569 [3744r,3760r:0)  0@3744r
%vreg573 [3680r,3712r:0)[3712r,3728r:1)  0@3680r 1@3712r
%vreg575 [3664r,3728r:0)  0@3664r
%vreg580 [3584r,3616r:0)[3616r,3648r:1)  0@3584r 1@3616r
%vreg583 [3568r,3584r:0)  0@3568r
%vreg586 [3536r,3552r:0)  0@3536r
%vreg589 [3520r,3552r:0)  0@3520r
%vreg591 [3504r,3520r:0)  0@3504r
%vreg592 [3488r,3504r:0)  0@3488r
%vreg595 [3456r,3520r:0)  0@3456r
%vreg597 [3440r,3456r:0)  0@3440r
%vreg599 [3408r,3424r:0)  0@3408r
%vreg602 [3968r,3984r:0)  0@3968r
%vreg606 [3904r,3936r:0)[3936r,3952r:1)  0@3904r 1@3936r
%vreg608 [3888r,3952r:0)  0@3888r
%vreg611 [3856r,3872r:0)  0@3856r
%vreg613 [3840r,3872r:0)  0@3840r
%vreg615 [3824r,3840r:0)  0@3824r
%vreg617 [3808r,3824r:0)  0@3808r
%vreg619 [4032r,4048r:0)  0@4032r
%vreg623 [4496r,4528r:0)[4528r,4544r:1)  0@4496r 1@4528r
%vreg626 [4480r,4496r:0)  0@4480r
%vreg628 [4464r,4544r:0)  0@4464r
%vreg629 [4448r,4464r:0)  0@4448r
%vreg633 [4384r,4416r:0)[4416r,4432r:1)  0@4384r 1@4416r
%vreg635 [4368r,4432r:0)  0@4368r
%vreg641 [4288r,4320r:0)[4320r,4352r:1)  0@4288r 1@4320r
%vreg646 [4128r,4272r:0)  0@4128r
%vreg647 [4112r,4272r:0)[4272r,4320r:1)  0@4112r 1@4272r
%vreg649 [4224r,4240r:0)  0@4224r
%vreg653 [4160r,4192r:0)[4192r,4208r:1)  0@4160r 1@4192r
%vreg655 [4144r,4208r:0)  0@4144r
%vreg659 [4640r,4656r:0)  0@4640r
%vreg661 [4624r,4656r:0)  0@4624r
%vreg664 [5120r,5136r:0)  0@5120r
%vreg668 [5056r,5088r:0)[5088r,5104r:1)  0@5056r 1@5088r
%vreg670 [5040r,5104r:0)  0@5040r
%vreg675 [4960r,4992r:0)[4992r,5024r:1)  0@4960r 1@4992r
%vreg678 [4944r,4960r:0)  0@4944r
%vreg681 [4912r,4928r:0)  0@4912r
%vreg684 [4896r,4928r:0)  0@4896r
%vreg686 [4880r,4896r:0)  0@4880r
%vreg687 [4864r,4880r:0)  0@4864r
%vreg690 [4832r,4896r:0)  0@4832r
%vreg692 [4816r,4832r:0)  0@4816r
%vreg694 [4784r,4800r:0)  0@4784r
%vreg697 [5344r,5360r:0)  0@5344r
%vreg701 [5280r,5312r:0)[5312r,5328r:1)  0@5280r 1@5312r
%vreg703 [5264r,5328r:0)  0@5264r
%vreg706 [5232r,5248r:0)  0@5232r
%vreg708 [5216r,5248r:0)  0@5216r
%vreg710 [5200r,5216r:0)  0@5200r
%vreg712 [5184r,5200r:0)  0@5184r
%vreg714 [5408r,5424r:0)  0@5408r
%vreg718 [5872r,5904r:0)[5904r,5920r:1)  0@5872r 1@5904r
%vreg721 [5856r,5872r:0)  0@5856r
%vreg723 [5840r,5920r:0)  0@5840r
%vreg724 [5824r,5840r:0)  0@5824r
%vreg728 [5760r,5792r:0)[5792r,5808r:1)  0@5760r 1@5792r
%vreg730 [5744r,5808r:0)  0@5744r
%vreg736 [5664r,5696r:0)[5696r,5728r:1)  0@5664r 1@5696r
%vreg741 [5504r,5648r:0)  0@5504r
%vreg742 [5488r,5648r:0)[5648r,5696r:1)  0@5488r 1@5648r
%vreg744 [5600r,5616r:0)  0@5600r
%vreg748 [5536r,5568r:0)[5568r,5584r:1)  0@5536r 1@5568r
%vreg750 [5520r,5584r:0)  0@5520r
%vreg754 [6016r,6032r:0)  0@6016r
%vreg756 [6000r,6032r:0)  0@6000r
%vreg759 [6464r,6480r:0)  0@6464r
%vreg763 [6400r,6432r:0)[6432r,6448r:1)  0@6400r 1@6432r
%vreg765 [6384r,6448r:0)  0@6384r
%vreg770 [6304r,6336r:0)[6336r,6368r:1)  0@6304r 1@6336r
%vreg773 [6288r,6304r:0)  0@6288r
%vreg776 [6256r,6272r:0)  0@6256r
%vreg779 [6240r,6272r:0)  0@6240r
%vreg781 [6224r,6240r:0)  0@6224r
%vreg782 [6208r,6224r:0)  0@6208r
%vreg785 [6176r,6240r:0)  0@6176r
%vreg787 [6160r,6176r:0)  0@6160r
%vreg790 [6688r,6704r:0)  0@6688r
%vreg794 [6624r,6656r:0)[6656r,6672r:1)  0@6624r 1@6656r
%vreg796 [6608r,6672r:0)  0@6608r
%vreg799 [6576r,6592r:0)  0@6576r
%vreg801 [6560r,6592r:0)  0@6560r
%vreg803 [6544r,6560r:0)  0@6544r
%vreg805 [6528r,6544r:0)  0@6528r
%vreg807 [6752r,6768r:0)  0@6752r
%vreg810 [7584r,7600r:0)  0@7584r
%vreg814 [7520r,7552r:0)[7552r,7568r:1)  0@7520r 1@7552r
%vreg816 [7504r,7568r:0)  0@7504r
%vreg819 [7472r,7488r:0)  0@7472r
%vreg821 [7456r,7488r:0)  0@7456r
%vreg825 [7392r,7424r:0)[7424r,7456r:1)  0@7392r 1@7424r
%vreg828 [7376r,7392r:0)  0@7376r
%vreg831 [7344r,7360r:0)  0@7344r
%vreg834 [7328r,7360r:0)  0@7328r
%vreg836 [7312r,7328r:0)  0@7312r
%vreg837 [7296r,7312r:0)  0@7296r
%vreg840 [7264r,7328r:0)  0@7264r
%vreg842 [7248r,7264r:0)  0@7248r
%vreg845 [7216r,7232r:0)  0@7216r
%vreg847 [7168r,7200r:0)[7200r,7232r:1)  0@7168r 1@7200r
%vreg853 [7104r,7136r:0)[7136r,7152r:1)  0@7104r 1@7136r
%vreg855 [7088r,7152r:0)  0@7088r
%vreg861 [7008r,7040r:0)[7040r,7072r:1)  0@7008r 1@7040r
%vreg866 [6848r,6992r:0)  0@6848r
%vreg867 [6832r,6992r:0)[6992r,7040r:1)  0@6832r 1@6992r
%vreg869 [6944r,6960r:0)  0@6944r
%vreg873 [6880r,6912r:0)[6912r,6928r:1)  0@6880r 1@6912r
%vreg875 [6864r,6928r:0)  0@6864r
%vreg878 [7808r,7824r:0)  0@7808r
%vreg882 [7744r,7776r:0)[7776r,7792r:1)  0@7744r 1@7776r
%vreg884 [7728r,7792r:0)  0@7728r
%vreg887 [7696r,7712r:0)  0@7696r
%vreg889 [7680r,7712r:0)  0@7680r
%vreg891 [7664r,7680r:0)  0@7664r
%vreg893 [7648r,7664r:0)  0@7648r
%vreg895 [7872r,7888r:0)  0@7872r
%vreg899 [8208r,8240r:0)[8240r,8256r:1)  0@8208r 1@8240r
%vreg901 [8192r,8256r:0)  0@8192r
%vreg906 [7952r,8112r:2)[8112r,8160r:0)[8160r,8176r:1)  0@8112r 1@8160r 2@7952r
%vreg907 [8128r,8176r:0)  0@8128r
%vreg910 [7968r,8112r:0)  0@7968r
%vreg913 [8064r,8080r:0)  0@8064r
%vreg917 [8000r,8032r:0)[8032r,8048r:1)  0@8000r 1@8032r
%vreg919 [7984r,8048r:0)  0@7984r
%vreg922 [6096r,6112r:0)  0@6096r
%vreg924 [6080r,6112r:0)  0@6080r
%vreg927 [4720r,4736r:0)  0@4720r
%vreg929 [4704r,4736r:0)  0@4704r
%vreg932 [3344r,3360r:0)  0@3344r
%vreg934 [3328r,3360r:0)  0@3328r
%vreg936 [13792r,13808r:0)  0@13792r
%vreg938 [13616r,13680r:0)  0@13616r
%vreg939 [13648r,13696r:0)  0@13648r
RegMasks: 144r 13712r
********** MACHINEINSTRS **********
# Machine code for function unRLE_obuf_to_output_FAST: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=1, align=1, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=1, align=1, at location [SP+8]
  fi#3: size=4, align=4, at location [SP+8]
  fi#4: size=1, align=1, at location [SP+8]
  fi#5: size=4, align=4, at location [SP+8]
  fi#6: size=4, align=4, at location [SP+8]
  fi#7: size=4, align=4, at location [SP+8]
  fi#8: size=8, align=8, at location [SP+8]
  fi#9: size=4, align=4, at location [SP+8]
  fi#10: size=8, align=8, at location [SP+8]
  fi#11: size=4, align=4, at location [SP+8]
  fi#12: size=4, align=4, at location [SP+8]
  fi#13: size=4, align=4, at location [SP+8]
  fi#14: size=4, align=4, at location [SP+8]
Function Live Ins: %RDI in %vreg0

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI
16B		%vreg1<def> = COPY %RDI; GR64:%vreg1
48B		%vreg6<def> = MOV64ri <ga:@unRLE_obuf_to_output_FAST>; GR64:%vreg6
80B		%vreg7<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg7
96B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
112B		%RDI<def> = COPY %vreg6; GR64:%vreg6
128B		%RSI<def> = COPY %vreg7; GR64:%vreg7
144B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
160B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
192B		STACKMAP 0, 0, 0, <fi#12>, 0, 0, <fi#3>, 0, 0, <fi#7>, 0, 0, <fi#6>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#9>, 0, 0, <fi#8>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, %vreg1, 0, <fi#1>, 0, 0, <fi#13>, 0, 0, <fi#14>, 0, ...; mem:LD8[FixedStack12](align=4) LD8[FixedStack3](align=4) LD8[FixedStack7](align=4) LD8[FixedStack6](align=4) LD8[FixedStack4](align=1) LD8[FixedStack5](align=4) LD8[FixedStack9](align=4) LD8[FixedStack8] LD8[FixedStack11](align=4) LD8[FixedStack10] LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1] LD8[FixedStack13](align=4) LD8[FixedStack14](align=4) GR64:%vreg1
208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%s.addr] GR64:%vreg1
240B		%vreg4<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg4
256B		CMP8mi %vreg4, 1, %noreg, 20, %noreg, 0, %EFLAGS<imp-def>; mem:LD1[%blockRandomised] GR64:%vreg4
272B		JE_1 <BB#47>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#47 BB#1

288B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
304B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2

320B	BB#2: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#1 BB#46 BB#37 BB#35 BB#29 BB#27 BB#21 BB#19
336B		JMP_1 <BB#3>
	    Successors according to CFG: BB#3

352B	BB#3: derived from LLVM BB %while.body.2
	    Predecessors according to CFG: BB#2 BB#9
368B		%vreg360<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg360
384B		%vreg359<def> = MOV64rm %vreg360, 1, %noreg, 0, %noreg; mem:LD8[%strm] GR64:%vreg359,%vreg360
400B		CMP32mi8 %vreg359, 1, %noreg, 32, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_out] GR64:%vreg359
416B		JNE_1 <BB#5>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#5 BB#4

432B	BB#4: derived from LLVM BB %if.then.3
	    Predecessors according to CFG: BB#3
448B		MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST1[%retval]
464B		JMP_1 <BB#80>
	    Successors according to CFG: BB#80

480B	BB#5: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#3
496B		%vreg363<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg363
512B		CMP32mi8 %vreg363, 1, %noreg, 16, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%state_out_len] GR64:%vreg363
528B		JNE_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#6

544B	BB#6: derived from LLVM BB %if.then.5
	    Predecessors according to CFG: BB#5
560B		JMP_1 <BB#10>
	    Successors according to CFG: BB#10

576B	BB#7: derived from LLVM BB %if.end.6
	    Predecessors according to CFG: BB#5
592B		%vreg435<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg435
608B		%vreg434<def> = MOV8rm %vreg435, 1, %noreg, 12, %noreg; mem:LD1[%state_out_ch] GR8:%vreg434 GR64:%vreg435
624B		%vreg432<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg432
640B		%vreg431<def> = MOV64rm %vreg432, 1, %noreg, 0, %noreg; mem:LD8[%strm7] GR64:%vreg431,%vreg432
656B		%vreg429<def> = MOV64rm %vreg431, 1, %noreg, 24, %noreg; mem:LD8[%next_out] GR64:%vreg429,%vreg431
672B		MOV8mr %vreg429, 1, %noreg, 0, %noreg, %vreg434; mem:ST1[%11] GR64:%vreg429 GR8:%vreg434
688B		%vreg425<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg425
704B		%vreg404<def> = MOV32rm %vreg425, 1, %noreg, 3184, %noreg; mem:LD4[%calculatedBlockCRC] GR32:%vreg404 GR64:%vreg425
736B		%vreg404<def,tied1> = SHL32ri %vreg404<tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg404
752B		%vreg420<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg420
768B		%vreg411<def> = MOV32rm %vreg420, 1, %noreg, 3184, %noreg; mem:LD4[%calculatedBlockCRC8] GR32:%vreg411 GR64:%vreg420
800B		%vreg411<def,tied1> = SHR32ri %vreg411<tied0>, 24, %EFLAGS<imp-def,dead>; GR32:%vreg411
816B		%vreg415<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg415
832B		%vreg413<def> = MOVZX32rm8 %vreg415, 1, %noreg, 12, %noreg; mem:LD1[%state_out_ch9] GR32:%vreg413 GR64:%vreg415
864B		%vreg411<def,tied1> = XOR32rr %vreg411<tied0>, %vreg413, %EFLAGS<imp-def,dead>; GR32:%vreg411,%vreg413
880B		%vreg408:sub_32bit<def,read-undef> = MOV32rr %vreg411; GR64_NOSP:%vreg408 GR32:%vreg411
928B		%vreg404<def,tied1> = XOR32rm %vreg404<tied0>, %noreg, 4, %vreg408, <ga:@BZ2_crc32Table>, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%arrayidx] GR32:%vreg404 GR64_NOSP:%vreg408
944B		%vreg401<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg401
960B		MOV32mr %vreg401, 1, %noreg, 3184, %noreg, %vreg404; mem:ST4[%calculatedBlockCRC11] GR64:%vreg401 GR32:%vreg404
976B		%vreg398<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg398
992B		%vreg396<def> = MOV32rm %vreg398, 1, %noreg, 16, %noreg; mem:LD4[%state_out_len12] GR32:%vreg396 GR64:%vreg398
1024B		%vreg396<def,tied1> = ADD32ri8 %vreg396<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg396
1040B		MOV32mr %vreg398, 1, %noreg, 16, %noreg, %vreg396; mem:ST4[%state_out_len12] GR64:%vreg398 GR32:%vreg396
1056B		%vreg392<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg392
1072B		%vreg391<def> = MOV64rm %vreg392, 1, %noreg, 0, %noreg; mem:LD8[%strm13] GR64:%vreg391,%vreg392
1088B		%vreg388<def> = MOV64rm %vreg391, 1, %noreg, 24, %noreg; mem:LD8[%next_out14] GR64:%vreg388,%vreg391
1120B		%vreg388<def,tied1> = ADD64ri8 %vreg388<tied0>, 1, %EFLAGS<imp-def,dead>; GR64:%vreg388
1136B		MOV64mr %vreg391, 1, %noreg, 24, %noreg, %vreg388; mem:ST8[%next_out14] GR64:%vreg391,%vreg388
1152B		%vreg384<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg384
1168B		%vreg383<def> = MOV64rm %vreg384, 1, %noreg, 0, %noreg; mem:LD8[%strm15] GR64:%vreg383,%vreg384
1184B		%vreg380<def> = MOV32rm %vreg383, 1, %noreg, 32, %noreg; mem:LD4[%avail_out16] GR32:%vreg380 GR64:%vreg383
1216B		%vreg380<def,tied1> = ADD32ri8 %vreg380<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg380
1232B		MOV32mr %vreg383, 1, %noreg, 32, %noreg, %vreg380; mem:ST4[%avail_out16] GR64:%vreg383 GR32:%vreg380
1248B		%vreg376<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg376
1264B		%vreg375<def> = MOV64rm %vreg376, 1, %noreg, 0, %noreg; mem:LD8[%strm18] GR64:%vreg375,%vreg376
1280B		%vreg372<def> = MOV32rm %vreg375, 1, %noreg, 36, %noreg; mem:LD4[%total_out_lo32] GR32:%vreg372 GR64:%vreg375
1312B		%vreg372<def,tied1> = ADD32ri8 %vreg372<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg372
1328B		MOV32mr %vreg375, 1, %noreg, 36, %noreg, %vreg372; mem:ST4[%total_out_lo32] GR64:%vreg375 GR32:%vreg372
1344B		%vreg368<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg368
1360B		%vreg367<def> = MOV64rm %vreg368, 1, %noreg, 0, %noreg; mem:LD8[%strm19] GR64:%vreg367,%vreg368
1376B		CMP32mi8 %vreg367, 1, %noreg, 36, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%total_out_lo3220] GR64:%vreg367
1392B		JNE_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#8

1408B	BB#8: derived from LLVM BB %if.then.23
	    Predecessors according to CFG: BB#7
1424B		%vreg443<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg443
1440B		%vreg442<def> = MOV64rm %vreg443, 1, %noreg, 0, %noreg; mem:LD8[%strm24] GR64:%vreg442,%vreg443
1456B		%vreg439<def> = MOV32rm %vreg442, 1, %noreg, 40, %noreg; mem:LD4[%total_out_hi32] GR32:%vreg439 GR64:%vreg442
1488B		%vreg439<def,tied1> = ADD32ri8 %vreg439<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg439
1504B		MOV32mr %vreg442, 1, %noreg, 40, %noreg, %vreg439; mem:ST4[%total_out_hi32] GR64:%vreg442 GR32:%vreg439
	    Successors according to CFG: BB#9

1520B	BB#9: derived from LLVM BB %if.end.26
	    Predecessors according to CFG: BB#7 BB#8
1536B		JMP_1 <BB#3>
	    Successors according to CFG: BB#3

1552B	BB#10: derived from LLVM BB %while.end
	    Predecessors according to CFG: BB#6
1568B		%vreg453<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg453
1584B		%vreg452<def> = MOV32rm %vreg453, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used] GR32:%vreg452 GR64:%vreg453
1600B		%vreg450<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg450
1616B		%vreg447<def> = MOV32rm %vreg450, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock] GR32:%vreg447 GR64:%vreg450
1648B		%vreg447<def,tied1> = ADD32ri8 %vreg447<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg447
1664B		CMP32rr %vreg452, %vreg447, %EFLAGS<imp-def>; GR32:%vreg452,%vreg447
1680B		JNE_1 <BB#12>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#12 BB#11

1696B	BB#11: derived from LLVM BB %if.then.29
	    Predecessors according to CFG: BB#10
1712B		MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST1[%retval]
1728B		JMP_1 <BB#80>
	    Successors according to CFG: BB#80

1744B	BB#12: derived from LLVM BB %if.end.30
	    Predecessors according to CFG: BB#10
1760B		%vreg463<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg463
1776B		%vreg462<def> = MOV32rm %vreg463, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used31] GR32:%vreg462 GR64:%vreg463
1792B		%vreg460<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg460
1808B		%vreg457<def> = MOV32rm %vreg460, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock32] GR32:%vreg457 GR64:%vreg460
1840B		%vreg457<def,tied1> = ADD32ri8 %vreg457<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg457
1856B		CMP32rr %vreg462, %vreg457, %EFLAGS<imp-def>; GR32:%vreg462,%vreg457
1872B		JLE_1 <BB#14>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#14 BB#13

1888B	BB#13: derived from LLVM BB %if.then.36
	    Predecessors according to CFG: BB#12
1904B		MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 1; mem:ST1[%retval]
1920B		JMP_1 <BB#80>
	    Successors according to CFG: BB#80

1936B	BB#14: derived from LLVM BB %if.end.37
	    Predecessors according to CFG: BB#12
1952B		%vreg504<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg504
1968B		MOV32mi %vreg504, 1, %noreg, 16, %noreg, 1; mem:ST4[%state_out_len38] GR64:%vreg504
1984B		%vreg502<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg502
2000B		%vreg501<def> = MOV32rm %vreg502, 1, %noreg, 64, %noreg; mem:LD4[%k0] GR32:%vreg501 GR64:%vreg502
2032B		%vreg497<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg497
2048B		MOV8mr %vreg497, 1, %noreg, 12, %noreg, %vreg501:sub_8bit; mem:ST1[%state_out_ch40] GR64:%vreg497 GR32:%vreg501
2064B		%vreg494<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg494
2080B		%vreg492:sub_32bit<def,read-undef> = MOV32rm %vreg494, 1, %noreg, 60, %noreg; mem:LD4[%tPos] GR64_NOSP:%vreg492 GR64:%vreg494
2112B		%vreg489<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg489
2128B		%vreg488<def> = MOV64rm %vreg489, 1, %noreg, 3152, %noreg; mem:LD8[%tt] GR64:%vreg488,%vreg489
2144B		%vreg486<def> = MOV32rm %vreg488, 4, %vreg492, 0, %noreg; mem:LD4[%arrayidx42] GR32:%vreg486 GR64:%vreg488 GR64_NOSP:%vreg492
2160B		%vreg483<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg483
2176B		MOV32mr %vreg483, 1, %noreg, 60, %noreg, %vreg486; mem:ST4[%tPos43] GR64:%vreg483 GR32:%vreg486
2192B		%vreg480<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg480
2208B		%vreg477<def> = MOV32rm %vreg480, 1, %noreg, 60, %noreg; mem:LD4[%tPos44] GR32:%vreg477 GR64:%vreg480
2240B		%vreg477<def,tied1> = AND32ri %vreg477<tied0>, 255, %EFLAGS<imp-def,dead>; GR32:%vreg477
2272B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg477:sub_8bit; mem:ST1[%k1] GR32:%vreg477
2288B		%vreg472<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg472
2304B		%vreg470<def> = MOV32rm %vreg472, 1, %noreg, 60, %noreg; mem:LD4[%tPos46] GR32:%vreg470 GR64:%vreg472
2336B		%vreg470<def,tied1> = SHR32ri %vreg470<tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg470
2352B		MOV32mr %vreg472, 1, %noreg, 60, %noreg, %vreg470; mem:ST4[%tPos46] GR64:%vreg472 GR32:%vreg470
2368B		%vreg466<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg466
2384B		CMP32mi8 %vreg466, 1, %noreg, 24, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%rNToGo] GR64:%vreg466
2400B		JNE_1 <BB#18>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#18 BB#15

2416B	BB#15: derived from LLVM BB %if.then.50
	    Predecessors according to CFG: BB#14
2432B		%vreg522<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg522
2448B		%vreg520<def> = MOVSX64rm32 %vreg522, 1, %noreg, 28, %noreg; mem:LD4[%rTPos] GR64_NOSP:%vreg520 GR64:%vreg522
2464B		%vreg518<def> = MOV32rm %noreg, 4, %vreg520, <ga:@BZ2_rNums>, %noreg; mem:LD4[%arrayidx52] GR32:%vreg518 GR64_NOSP:%vreg520
2480B		%vreg516<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg516
2496B		MOV32mr %vreg516, 1, %noreg, 24, %noreg, %vreg518; mem:ST4[%rNToGo53] GR64:%vreg516 GR32:%vreg518
2512B		%vreg513<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg513
2528B		%vreg511<def> = MOV32rm %vreg513, 1, %noreg, 28, %noreg; mem:LD4[%rTPos54] GR32:%vreg511 GR64:%vreg513
2560B		%vreg511<def,tied1> = ADD32ri8 %vreg511<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg511
2576B		MOV32mr %vreg513, 1, %noreg, 28, %noreg, %vreg511; mem:ST4[%rTPos54] GR64:%vreg513 GR32:%vreg511
2592B		%vreg507<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg507
2608B		CMP32mi %vreg507, 1, %noreg, 28, %noreg, 512, %EFLAGS<imp-def>; mem:LD4[%rTPos56] GR64:%vreg507
2624B		JNE_1 <BB#17>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#17 BB#16

2640B	BB#16: derived from LLVM BB %if.then.59
	    Predecessors according to CFG: BB#15
2656B		%vreg524<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg524
2672B		MOV32mi %vreg524, 1, %noreg, 28, %noreg, 0; mem:ST4[%rTPos60] GR64:%vreg524
	    Successors according to CFG: BB#17

2688B	BB#17: derived from LLVM BB %if.end.61
	    Predecessors according to CFG: BB#15 BB#16
2704B		JMP_1 <BB#18>
	    Successors according to CFG: BB#18

2720B	BB#18: derived from LLVM BB %if.end.62
	    Predecessors according to CFG: BB#14 BB#17
2736B		%vreg552<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg552
2752B		%vreg551<def> = MOV32ri 1; GR32:%vreg551
2768B		%vreg560<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg560
2784B		%vreg558<def> = MOV32rm %vreg560, 1, %noreg, 24, %noreg; mem:LD4[%rNToGo63] GR32:%vreg558 GR64:%vreg560
2816B		%vreg558<def,tied1> = ADD32ri8 %vreg558<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg558
2832B		MOV32mr %vreg560, 1, %noreg, 24, %noreg, %vreg558; mem:ST4[%rNToGo63] GR64:%vreg560 GR32:%vreg558
2848B		%vreg554<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg554
2864B		CMP32mi8 %vreg554, 1, %noreg, 24, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%rNToGo65] GR64:%vreg554
2896B		%vreg552<def,tied1> = CMOVE32rr %vreg552<tied0>, %vreg551, %EFLAGS<imp-use,kill>; GR32:%vreg552,%vreg551
2912B		%vreg546<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg546
2944B		%vreg546<def,tied1> = XOR32rr %vreg546<tied0>, %vreg552, %EFLAGS<imp-def,dead>; GR32:%vreg546,%vreg552
2976B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg546:sub_8bit; mem:ST1[%k1] GR32:%vreg546
2992B		%vreg540<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg540
3008B		%vreg538<def> = MOV32rm %vreg540, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used71] GR32:%vreg538 GR64:%vreg540
3040B		%vreg538<def,tied1> = ADD32ri8 %vreg538<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg538
3056B		MOV32mr %vreg540, 1, %noreg, 1092, %noreg, %vreg538; mem:ST4[%nblock_used71] GR64:%vreg540 GR32:%vreg538
3072B		%vreg534<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg534
3088B		%vreg533<def> = MOV32rm %vreg534, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used73] GR32:%vreg533 GR64:%vreg534
3104B		%vreg531<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg531
3120B		%vreg528<def> = MOV32rm %vreg531, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock74] GR32:%vreg528 GR64:%vreg531
3152B		%vreg528<def,tied1> = ADD32ri8 %vreg528<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg528
3168B		CMP32rr %vreg533, %vreg528, %EFLAGS<imp-def>; GR32:%vreg533,%vreg528
3184B		JNE_1 <BB#20>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#20 BB#19

3200B	BB#19: derived from LLVM BB %if.then.78
	    Predecessors according to CFG: BB#18
3216B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2

3232B	BB#20: derived from LLVM BB %if.end.79
	    Predecessors according to CFG: BB#18
3248B		%vreg566<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg566
3264B		%vreg564<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg564
3280B		CMP32rm %vreg566, %vreg564, 1, %noreg, 64, %noreg, %EFLAGS<imp-def>; mem:LD4[%k081] GR32:%vreg566 GR64:%vreg564
3296B		JE_1 <BB#22>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#22 BB#21

3312B	BB#21: derived from LLVM BB %if.then.84
	    Predecessors according to CFG: BB#20
3328B		%vreg934<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg934
3344B		%vreg932<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg932
3360B		MOV32mr %vreg932, 1, %noreg, 64, %noreg, %vreg934; mem:ST4[%k086] GR64:%vreg932 GR32:%vreg934
3376B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2

3392B	BB#22: derived from LLVM BB %if.end.87
	    Predecessors according to CFG: BB#20
3408B		%vreg599<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg599
3424B		MOV32mi %vreg599, 1, %noreg, 16, %noreg, 2; mem:ST4[%state_out_len88] GR64:%vreg599
3440B		%vreg597<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg597
3456B		%vreg595:sub_32bit<def,read-undef> = MOV32rm %vreg597, 1, %noreg, 60, %noreg; mem:LD4[%tPos89] GR64_NOSP:%vreg595 GR64:%vreg597
3488B		%vreg592<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg592
3504B		%vreg591<def> = MOV64rm %vreg592, 1, %noreg, 3152, %noreg; mem:LD8[%tt91] GR64:%vreg591,%vreg592
3520B		%vreg589<def> = MOV32rm %vreg591, 4, %vreg595, 0, %noreg; mem:LD4[%arrayidx92] GR32:%vreg589 GR64:%vreg591 GR64_NOSP:%vreg595
3536B		%vreg586<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg586
3552B		MOV32mr %vreg586, 1, %noreg, 60, %noreg, %vreg589; mem:ST4[%tPos93] GR64:%vreg586 GR32:%vreg589
3568B		%vreg583<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg583
3584B		%vreg580<def> = MOV32rm %vreg583, 1, %noreg, 60, %noreg; mem:LD4[%tPos94] GR32:%vreg580 GR64:%vreg583
3616B		%vreg580<def,tied1> = AND32ri %vreg580<tied0>, 255, %EFLAGS<imp-def,dead>; GR32:%vreg580
3648B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg580:sub_8bit; mem:ST1[%k1] GR32:%vreg580
3664B		%vreg575<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg575
3680B		%vreg573<def> = MOV32rm %vreg575, 1, %noreg, 60, %noreg; mem:LD4[%tPos97] GR32:%vreg573 GR64:%vreg575
3712B		%vreg573<def,tied1> = SHR32ri %vreg573<tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg573
3728B		MOV32mr %vreg575, 1, %noreg, 60, %noreg, %vreg573; mem:ST4[%tPos97] GR64:%vreg575 GR32:%vreg573
3744B		%vreg569<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg569
3760B		CMP32mi8 %vreg569, 1, %noreg, 24, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%rNToGo99] GR64:%vreg569
3776B		JNE_1 <BB#26>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#26 BB#23

3792B	BB#23: derived from LLVM BB %if.then.102
	    Predecessors according to CFG: BB#22
3808B		%vreg617<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg617
3824B		%vreg615<def> = MOVSX64rm32 %vreg617, 1, %noreg, 28, %noreg; mem:LD4[%rTPos103] GR64_NOSP:%vreg615 GR64:%vreg617
3840B		%vreg613<def> = MOV32rm %noreg, 4, %vreg615, <ga:@BZ2_rNums>, %noreg; mem:LD4[%arrayidx105] GR32:%vreg613 GR64_NOSP:%vreg615
3856B		%vreg611<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg611
3872B		MOV32mr %vreg611, 1, %noreg, 24, %noreg, %vreg613; mem:ST4[%rNToGo106] GR64:%vreg611 GR32:%vreg613
3888B		%vreg608<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg608
3904B		%vreg606<def> = MOV32rm %vreg608, 1, %noreg, 28, %noreg; mem:LD4[%rTPos107] GR32:%vreg606 GR64:%vreg608
3936B		%vreg606<def,tied1> = ADD32ri8 %vreg606<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg606
3952B		MOV32mr %vreg608, 1, %noreg, 28, %noreg, %vreg606; mem:ST4[%rTPos107] GR64:%vreg608 GR32:%vreg606
3968B		%vreg602<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg602
3984B		CMP32mi %vreg602, 1, %noreg, 28, %noreg, 512, %EFLAGS<imp-def>; mem:LD4[%rTPos109] GR64:%vreg602
4000B		JNE_1 <BB#25>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#25 BB#24

4016B	BB#24: derived from LLVM BB %if.then.112
	    Predecessors according to CFG: BB#23
4032B		%vreg619<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg619
4048B		MOV32mi %vreg619, 1, %noreg, 28, %noreg, 0; mem:ST4[%rTPos113] GR64:%vreg619
	    Successors according to CFG: BB#25

4064B	BB#25: derived from LLVM BB %if.end.114
	    Predecessors according to CFG: BB#23 BB#24
4080B		JMP_1 <BB#26>
	    Successors according to CFG: BB#26

4096B	BB#26: derived from LLVM BB %if.end.115
	    Predecessors according to CFG: BB#22 BB#25
4112B		%vreg647<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg647
4128B		%vreg646<def> = MOV32ri 1; GR32:%vreg646
4144B		%vreg655<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg655
4160B		%vreg653<def> = MOV32rm %vreg655, 1, %noreg, 24, %noreg; mem:LD4[%rNToGo116] GR32:%vreg653 GR64:%vreg655
4192B		%vreg653<def,tied1> = ADD32ri8 %vreg653<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg653
4208B		MOV32mr %vreg655, 1, %noreg, 24, %noreg, %vreg653; mem:ST4[%rNToGo116] GR64:%vreg655 GR32:%vreg653
4224B		%vreg649<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg649
4240B		CMP32mi8 %vreg649, 1, %noreg, 24, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%rNToGo118] GR64:%vreg649
4272B		%vreg647<def,tied1> = CMOVE32rr %vreg647<tied0>, %vreg646, %EFLAGS<imp-use,kill>; GR32:%vreg647,%vreg646
4288B		%vreg641<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg641
4320B		%vreg641<def,tied1> = XOR32rr %vreg641<tied0>, %vreg647, %EFLAGS<imp-def,dead>; GR32:%vreg641,%vreg647
4352B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg641:sub_8bit; mem:ST1[%k1] GR32:%vreg641
4368B		%vreg635<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg635
4384B		%vreg633<def> = MOV32rm %vreg635, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used125] GR32:%vreg633 GR64:%vreg635
4416B		%vreg633<def,tied1> = ADD32ri8 %vreg633<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg633
4432B		MOV32mr %vreg635, 1, %noreg, 1092, %noreg, %vreg633; mem:ST4[%nblock_used125] GR64:%vreg635 GR32:%vreg633
4448B		%vreg629<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg629
4464B		%vreg628<def> = MOV32rm %vreg629, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used127] GR32:%vreg628 GR64:%vreg629
4480B		%vreg626<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg626
4496B		%vreg623<def> = MOV32rm %vreg626, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock128] GR32:%vreg623 GR64:%vreg626
4528B		%vreg623<def,tied1> = ADD32ri8 %vreg623<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg623
4544B		CMP32rr %vreg628, %vreg623, %EFLAGS<imp-def>; GR32:%vreg628,%vreg623
4560B		JNE_1 <BB#28>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#28 BB#27

4576B	BB#27: derived from LLVM BB %if.then.132
	    Predecessors according to CFG: BB#26
4592B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2

4608B	BB#28: derived from LLVM BB %if.end.133
	    Predecessors according to CFG: BB#26
4624B		%vreg661<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg661
4640B		%vreg659<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg659
4656B		CMP32rm %vreg661, %vreg659, 1, %noreg, 64, %noreg, %EFLAGS<imp-def>; mem:LD4[%k0135] GR32:%vreg661 GR64:%vreg659
4672B		JE_1 <BB#30>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#30 BB#29

4688B	BB#29: derived from LLVM BB %if.then.138
	    Predecessors according to CFG: BB#28
4704B		%vreg929<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg929
4720B		%vreg927<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg927
4736B		MOV32mr %vreg927, 1, %noreg, 64, %noreg, %vreg929; mem:ST4[%k0140] GR64:%vreg927 GR32:%vreg929
4752B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2

4768B	BB#30: derived from LLVM BB %if.end.141
	    Predecessors according to CFG: BB#28
4784B		%vreg694<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg694
4800B		MOV32mi %vreg694, 1, %noreg, 16, %noreg, 3; mem:ST4[%state_out_len142] GR64:%vreg694
4816B		%vreg692<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg692
4832B		%vreg690:sub_32bit<def,read-undef> = MOV32rm %vreg692, 1, %noreg, 60, %noreg; mem:LD4[%tPos143] GR64_NOSP:%vreg690 GR64:%vreg692
4864B		%vreg687<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg687
4880B		%vreg686<def> = MOV64rm %vreg687, 1, %noreg, 3152, %noreg; mem:LD8[%tt145] GR64:%vreg686,%vreg687
4896B		%vreg684<def> = MOV32rm %vreg686, 4, %vreg690, 0, %noreg; mem:LD4[%arrayidx146] GR32:%vreg684 GR64:%vreg686 GR64_NOSP:%vreg690
4912B		%vreg681<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg681
4928B		MOV32mr %vreg681, 1, %noreg, 60, %noreg, %vreg684; mem:ST4[%tPos147] GR64:%vreg681 GR32:%vreg684
4944B		%vreg678<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg678
4960B		%vreg675<def> = MOV32rm %vreg678, 1, %noreg, 60, %noreg; mem:LD4[%tPos148] GR32:%vreg675 GR64:%vreg678
4992B		%vreg675<def,tied1> = AND32ri %vreg675<tied0>, 255, %EFLAGS<imp-def,dead>; GR32:%vreg675
5024B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg675:sub_8bit; mem:ST1[%k1] GR32:%vreg675
5040B		%vreg670<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg670
5056B		%vreg668<def> = MOV32rm %vreg670, 1, %noreg, 60, %noreg; mem:LD4[%tPos151] GR32:%vreg668 GR64:%vreg670
5088B		%vreg668<def,tied1> = SHR32ri %vreg668<tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg668
5104B		MOV32mr %vreg670, 1, %noreg, 60, %noreg, %vreg668; mem:ST4[%tPos151] GR64:%vreg670 GR32:%vreg668
5120B		%vreg664<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg664
5136B		CMP32mi8 %vreg664, 1, %noreg, 24, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%rNToGo153] GR64:%vreg664
5152B		JNE_1 <BB#34>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#34 BB#31

5168B	BB#31: derived from LLVM BB %if.then.156
	    Predecessors according to CFG: BB#30
5184B		%vreg712<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg712
5200B		%vreg710<def> = MOVSX64rm32 %vreg712, 1, %noreg, 28, %noreg; mem:LD4[%rTPos157] GR64_NOSP:%vreg710 GR64:%vreg712
5216B		%vreg708<def> = MOV32rm %noreg, 4, %vreg710, <ga:@BZ2_rNums>, %noreg; mem:LD4[%arrayidx159] GR32:%vreg708 GR64_NOSP:%vreg710
5232B		%vreg706<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg706
5248B		MOV32mr %vreg706, 1, %noreg, 24, %noreg, %vreg708; mem:ST4[%rNToGo160] GR64:%vreg706 GR32:%vreg708
5264B		%vreg703<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg703
5280B		%vreg701<def> = MOV32rm %vreg703, 1, %noreg, 28, %noreg; mem:LD4[%rTPos161] GR32:%vreg701 GR64:%vreg703
5312B		%vreg701<def,tied1> = ADD32ri8 %vreg701<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg701
5328B		MOV32mr %vreg703, 1, %noreg, 28, %noreg, %vreg701; mem:ST4[%rTPos161] GR64:%vreg703 GR32:%vreg701
5344B		%vreg697<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg697
5360B		CMP32mi %vreg697, 1, %noreg, 28, %noreg, 512, %EFLAGS<imp-def>; mem:LD4[%rTPos163] GR64:%vreg697
5376B		JNE_1 <BB#33>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#33 BB#32

5392B	BB#32: derived from LLVM BB %if.then.166
	    Predecessors according to CFG: BB#31
5408B		%vreg714<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg714
5424B		MOV32mi %vreg714, 1, %noreg, 28, %noreg, 0; mem:ST4[%rTPos167] GR64:%vreg714
	    Successors according to CFG: BB#33

5440B	BB#33: derived from LLVM BB %if.end.168
	    Predecessors according to CFG: BB#31 BB#32
5456B		JMP_1 <BB#34>
	    Successors according to CFG: BB#34

5472B	BB#34: derived from LLVM BB %if.end.169
	    Predecessors according to CFG: BB#30 BB#33
5488B		%vreg742<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg742
5504B		%vreg741<def> = MOV32ri 1; GR32:%vreg741
5520B		%vreg750<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg750
5536B		%vreg748<def> = MOV32rm %vreg750, 1, %noreg, 24, %noreg; mem:LD4[%rNToGo170] GR32:%vreg748 GR64:%vreg750
5568B		%vreg748<def,tied1> = ADD32ri8 %vreg748<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg748
5584B		MOV32mr %vreg750, 1, %noreg, 24, %noreg, %vreg748; mem:ST4[%rNToGo170] GR64:%vreg750 GR32:%vreg748
5600B		%vreg744<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg744
5616B		CMP32mi8 %vreg744, 1, %noreg, 24, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%rNToGo172] GR64:%vreg744
5648B		%vreg742<def,tied1> = CMOVE32rr %vreg742<tied0>, %vreg741, %EFLAGS<imp-use,kill>; GR32:%vreg742,%vreg741
5664B		%vreg736<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg736
5696B		%vreg736<def,tied1> = XOR32rr %vreg736<tied0>, %vreg742, %EFLAGS<imp-def,dead>; GR32:%vreg736,%vreg742
5728B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg736:sub_8bit; mem:ST1[%k1] GR32:%vreg736
5744B		%vreg730<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg730
5760B		%vreg728<def> = MOV32rm %vreg730, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used179] GR32:%vreg728 GR64:%vreg730
5792B		%vreg728<def,tied1> = ADD32ri8 %vreg728<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg728
5808B		MOV32mr %vreg730, 1, %noreg, 1092, %noreg, %vreg728; mem:ST4[%nblock_used179] GR64:%vreg730 GR32:%vreg728
5824B		%vreg724<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg724
5840B		%vreg723<def> = MOV32rm %vreg724, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used181] GR32:%vreg723 GR64:%vreg724
5856B		%vreg721<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg721
5872B		%vreg718<def> = MOV32rm %vreg721, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock182] GR32:%vreg718 GR64:%vreg721
5904B		%vreg718<def,tied1> = ADD32ri8 %vreg718<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg718
5920B		CMP32rr %vreg723, %vreg718, %EFLAGS<imp-def>; GR32:%vreg723,%vreg718
5936B		JNE_1 <BB#36>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#36 BB#35

5952B	BB#35: derived from LLVM BB %if.then.186
	    Predecessors according to CFG: BB#34
5968B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2

5984B	BB#36: derived from LLVM BB %if.end.187
	    Predecessors according to CFG: BB#34
6000B		%vreg756<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg756
6016B		%vreg754<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg754
6032B		CMP32rm %vreg756, %vreg754, 1, %noreg, 64, %noreg, %EFLAGS<imp-def>; mem:LD4[%k0189] GR32:%vreg756 GR64:%vreg754
6048B		JE_1 <BB#38>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#38 BB#37

6064B	BB#37: derived from LLVM BB %if.then.192
	    Predecessors according to CFG: BB#36
6080B		%vreg924<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg924
6096B		%vreg922<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg922
6112B		MOV32mr %vreg922, 1, %noreg, 64, %noreg, %vreg924; mem:ST4[%k0194] GR64:%vreg922 GR32:%vreg924
6128B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2

6144B	BB#38: derived from LLVM BB %if.end.195
	    Predecessors according to CFG: BB#36
6160B		%vreg787<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg787
6176B		%vreg785:sub_32bit<def,read-undef> = MOV32rm %vreg787, 1, %noreg, 60, %noreg; mem:LD4[%tPos196] GR64_NOSP:%vreg785 GR64:%vreg787
6208B		%vreg782<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg782
6224B		%vreg781<def> = MOV64rm %vreg782, 1, %noreg, 3152, %noreg; mem:LD8[%tt198] GR64:%vreg781,%vreg782
6240B		%vreg779<def> = MOV32rm %vreg781, 4, %vreg785, 0, %noreg; mem:LD4[%arrayidx199] GR32:%vreg779 GR64:%vreg781 GR64_NOSP:%vreg785
6256B		%vreg776<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg776
6272B		MOV32mr %vreg776, 1, %noreg, 60, %noreg, %vreg779; mem:ST4[%tPos200] GR64:%vreg776 GR32:%vreg779
6288B		%vreg773<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg773
6304B		%vreg770<def> = MOV32rm %vreg773, 1, %noreg, 60, %noreg; mem:LD4[%tPos201] GR32:%vreg770 GR64:%vreg773
6336B		%vreg770<def,tied1> = AND32ri %vreg770<tied0>, 255, %EFLAGS<imp-def,dead>; GR32:%vreg770
6368B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg770:sub_8bit; mem:ST1[%k1] GR32:%vreg770
6384B		%vreg765<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg765
6400B		%vreg763<def> = MOV32rm %vreg765, 1, %noreg, 60, %noreg; mem:LD4[%tPos204] GR32:%vreg763 GR64:%vreg765
6432B		%vreg763<def,tied1> = SHR32ri %vreg763<tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg763
6448B		MOV32mr %vreg765, 1, %noreg, 60, %noreg, %vreg763; mem:ST4[%tPos204] GR64:%vreg765 GR32:%vreg763
6464B		%vreg759<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg759
6480B		CMP32mi8 %vreg759, 1, %noreg, 24, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%rNToGo206] GR64:%vreg759
6496B		JNE_1 <BB#42>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#42 BB#39

6512B	BB#39: derived from LLVM BB %if.then.209
	    Predecessors according to CFG: BB#38
6528B		%vreg805<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg805
6544B		%vreg803<def> = MOVSX64rm32 %vreg805, 1, %noreg, 28, %noreg; mem:LD4[%rTPos210] GR64_NOSP:%vreg803 GR64:%vreg805
6560B		%vreg801<def> = MOV32rm %noreg, 4, %vreg803, <ga:@BZ2_rNums>, %noreg; mem:LD4[%arrayidx212] GR32:%vreg801 GR64_NOSP:%vreg803
6576B		%vreg799<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg799
6592B		MOV32mr %vreg799, 1, %noreg, 24, %noreg, %vreg801; mem:ST4[%rNToGo213] GR64:%vreg799 GR32:%vreg801
6608B		%vreg796<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg796
6624B		%vreg794<def> = MOV32rm %vreg796, 1, %noreg, 28, %noreg; mem:LD4[%rTPos214] GR32:%vreg794 GR64:%vreg796
6656B		%vreg794<def,tied1> = ADD32ri8 %vreg794<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg794
6672B		MOV32mr %vreg796, 1, %noreg, 28, %noreg, %vreg794; mem:ST4[%rTPos214] GR64:%vreg796 GR32:%vreg794
6688B		%vreg790<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg790
6704B		CMP32mi %vreg790, 1, %noreg, 28, %noreg, 512, %EFLAGS<imp-def>; mem:LD4[%rTPos216] GR64:%vreg790
6720B		JNE_1 <BB#41>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#41 BB#40

6736B	BB#40: derived from LLVM BB %if.then.219
	    Predecessors according to CFG: BB#39
6752B		%vreg807<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg807
6768B		MOV32mi %vreg807, 1, %noreg, 28, %noreg, 0; mem:ST4[%rTPos220] GR64:%vreg807
	    Successors according to CFG: BB#41

6784B	BB#41: derived from LLVM BB %if.end.221
	    Predecessors according to CFG: BB#39 BB#40
6800B		JMP_1 <BB#42>
	    Successors according to CFG: BB#42

6816B	BB#42: derived from LLVM BB %if.end.222
	    Predecessors according to CFG: BB#38 BB#41
6832B		%vreg867<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg867
6848B		%vreg866<def> = MOV32ri 1; GR32:%vreg866
6864B		%vreg875<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg875
6880B		%vreg873<def> = MOV32rm %vreg875, 1, %noreg, 24, %noreg; mem:LD4[%rNToGo223] GR32:%vreg873 GR64:%vreg875
6912B		%vreg873<def,tied1> = ADD32ri8 %vreg873<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg873
6928B		MOV32mr %vreg875, 1, %noreg, 24, %noreg, %vreg873; mem:ST4[%rNToGo223] GR64:%vreg875 GR32:%vreg873
6944B		%vreg869<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg869
6960B		CMP32mi8 %vreg869, 1, %noreg, 24, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%rNToGo225] GR64:%vreg869
6992B		%vreg867<def,tied1> = CMOVE32rr %vreg867<tied0>, %vreg866, %EFLAGS<imp-use,kill>; GR32:%vreg867,%vreg866
7008B		%vreg861<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg861
7040B		%vreg861<def,tied1> = XOR32rr %vreg861<tied0>, %vreg867, %EFLAGS<imp-def,dead>; GR32:%vreg861,%vreg867
7072B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg861:sub_8bit; mem:ST1[%k1] GR32:%vreg861
7088B		%vreg855<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg855
7104B		%vreg853<def> = MOV32rm %vreg855, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used232] GR32:%vreg853 GR64:%vreg855
7136B		%vreg853<def,tied1> = ADD32ri8 %vreg853<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg853
7152B		MOV32mr %vreg855, 1, %noreg, 1092, %noreg, %vreg853; mem:ST4[%nblock_used232] GR64:%vreg855 GR32:%vreg853
7168B		%vreg847<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg847
7200B		%vreg847<def,tied1> = ADD32ri8 %vreg847<tied0>, 4, %EFLAGS<imp-def,dead>; GR32:%vreg847
7216B		%vreg845<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg845
7232B		MOV32mr %vreg845, 1, %noreg, 16, %noreg, %vreg847; mem:ST4[%state_out_len236] GR64:%vreg845 GR32:%vreg847
7248B		%vreg842<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg842
7264B		%vreg840:sub_32bit<def,read-undef> = MOV32rm %vreg842, 1, %noreg, 60, %noreg; mem:LD4[%tPos237] GR64_NOSP:%vreg840 GR64:%vreg842
7296B		%vreg837<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg837
7312B		%vreg836<def> = MOV64rm %vreg837, 1, %noreg, 3152, %noreg; mem:LD8[%tt239] GR64:%vreg836,%vreg837
7328B		%vreg834<def> = MOV32rm %vreg836, 4, %vreg840, 0, %noreg; mem:LD4[%arrayidx240] GR32:%vreg834 GR64:%vreg836 GR64_NOSP:%vreg840
7344B		%vreg831<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg831
7360B		MOV32mr %vreg831, 1, %noreg, 60, %noreg, %vreg834; mem:ST4[%tPos241] GR64:%vreg831 GR32:%vreg834
7376B		%vreg828<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg828
7392B		%vreg825<def> = MOV32rm %vreg828, 1, %noreg, 60, %noreg; mem:LD4[%tPos242] GR32:%vreg825 GR64:%vreg828
7424B		%vreg825<def,tied1> = AND32ri %vreg825<tied0>, 255, %EFLAGS<imp-def,dead>; GR32:%vreg825
7456B		%vreg821<def> = MOVZX32rr8 %vreg825:sub_8bit; GR32:%vreg821,%vreg825
7472B		%vreg819<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg819
7488B		MOV32mr %vreg819, 1, %noreg, 64, %noreg, %vreg821; mem:ST4[%k0246] GR64:%vreg819 GR32:%vreg821
7504B		%vreg816<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg816
7520B		%vreg814<def> = MOV32rm %vreg816, 1, %noreg, 60, %noreg; mem:LD4[%tPos247] GR32:%vreg814 GR64:%vreg816
7552B		%vreg814<def,tied1> = SHR32ri %vreg814<tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg814
7568B		MOV32mr %vreg816, 1, %noreg, 60, %noreg, %vreg814; mem:ST4[%tPos247] GR64:%vreg816 GR32:%vreg814
7584B		%vreg810<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg810
7600B		CMP32mi8 %vreg810, 1, %noreg, 24, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%rNToGo249] GR64:%vreg810
7616B		JNE_1 <BB#46>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#46 BB#43

7632B	BB#43: derived from LLVM BB %if.then.252
	    Predecessors according to CFG: BB#42
7648B		%vreg893<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg893
7664B		%vreg891<def> = MOVSX64rm32 %vreg893, 1, %noreg, 28, %noreg; mem:LD4[%rTPos253] GR64_NOSP:%vreg891 GR64:%vreg893
7680B		%vreg889<def> = MOV32rm %noreg, 4, %vreg891, <ga:@BZ2_rNums>, %noreg; mem:LD4[%arrayidx255] GR32:%vreg889 GR64_NOSP:%vreg891
7696B		%vreg887<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg887
7712B		MOV32mr %vreg887, 1, %noreg, 24, %noreg, %vreg889; mem:ST4[%rNToGo256] GR64:%vreg887 GR32:%vreg889
7728B		%vreg884<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg884
7744B		%vreg882<def> = MOV32rm %vreg884, 1, %noreg, 28, %noreg; mem:LD4[%rTPos257] GR32:%vreg882 GR64:%vreg884
7776B		%vreg882<def,tied1> = ADD32ri8 %vreg882<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg882
7792B		MOV32mr %vreg884, 1, %noreg, 28, %noreg, %vreg882; mem:ST4[%rTPos257] GR64:%vreg884 GR32:%vreg882
7808B		%vreg878<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg878
7824B		CMP32mi %vreg878, 1, %noreg, 28, %noreg, 512, %EFLAGS<imp-def>; mem:LD4[%rTPos259] GR64:%vreg878
7840B		JNE_1 <BB#45>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#45 BB#44

7856B	BB#44: derived from LLVM BB %if.then.262
	    Predecessors according to CFG: BB#43
7872B		%vreg895<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg895
7888B		MOV32mi %vreg895, 1, %noreg, 28, %noreg, 0; mem:ST4[%rTPos263] GR64:%vreg895
	    Successors according to CFG: BB#45

7904B	BB#45: derived from LLVM BB %if.end.264
	    Predecessors according to CFG: BB#43 BB#44
7920B		JMP_1 <BB#46>
	    Successors according to CFG: BB#46

7936B	BB#46: derived from LLVM BB %if.end.265
	    Predecessors according to CFG: BB#42 BB#45
7952B		%vreg906<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg906
7968B		%vreg910<def> = MOV32ri 1; GR32:%vreg910
7984B		%vreg919<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg919
8000B		%vreg917<def> = MOV32rm %vreg919, 1, %noreg, 24, %noreg; mem:LD4[%rNToGo266] GR32:%vreg917 GR64:%vreg919
8032B		%vreg917<def,tied1> = ADD32ri8 %vreg917<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg917
8048B		MOV32mr %vreg919, 1, %noreg, 24, %noreg, %vreg917; mem:ST4[%rNToGo266] GR64:%vreg919 GR32:%vreg917
8064B		%vreg913<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg913
8080B		CMP32mi8 %vreg913, 1, %noreg, 24, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%rNToGo268] GR64:%vreg913
8112B		%vreg906<def,tied1> = CMOVE32rr %vreg906<tied0>, %vreg910, %EFLAGS<imp-use,kill>; GR32:%vreg906,%vreg910
8128B		%vreg907<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg907
8160B		%vreg906<def,tied1> = XOR32rm %vreg906<tied0>, %vreg907, 1, %noreg, 64, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%k0272] GR32:%vreg906 GR64:%vreg907
8176B		MOV32mr %vreg907, 1, %noreg, 64, %noreg, %vreg906; mem:ST4[%k0272] GR64:%vreg907 GR32:%vreg906
8192B		%vreg901<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg901
8208B		%vreg899<def> = MOV32rm %vreg901, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used274] GR32:%vreg899 GR64:%vreg901
8240B		%vreg899<def,tied1> = ADD32ri8 %vreg899<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg899
8256B		MOV32mr %vreg901, 1, %noreg, 1092, %noreg, %vreg899; mem:ST4[%nblock_used274] GR64:%vreg901 GR32:%vreg899
8272B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2

8288B	BB#47: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#0
8304B		%vreg55<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg55
8320B		%vreg54<def> = MOV32rm %vreg55, 1, %noreg, 3184, %noreg; mem:LD4[%calculatedBlockCRC276] GR32:%vreg54 GR64:%vreg55
8336B		MOV32mr <fi#3>, 1, %noreg, 0, %noreg, %vreg54; mem:ST4[%c_calculatedBlockCRC] GR32:%vreg54
8352B		%vreg51<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg51
8368B		%vreg50<def> = MOV8rm %vreg51, 1, %noreg, 12, %noreg; mem:LD1[%state_out_ch277] GR8:%vreg50 GR64:%vreg51
8384B		MOV8mr <fi#4>, 1, %noreg, 0, %noreg, %vreg50; mem:ST1[%c_state_out_ch] GR8:%vreg50
8400B		%vreg47<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg47
8416B		%vreg46<def> = MOV32rm %vreg47, 1, %noreg, 16, %noreg; mem:LD4[%state_out_len278] GR32:%vreg46 GR64:%vreg47
8432B		MOV32mr <fi#5>, 1, %noreg, 0, %noreg, %vreg46; mem:ST4[%c_state_out_len] GR32:%vreg46
8448B		%vreg43<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg43
8464B		%vreg42<def> = MOV32rm %vreg43, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used279] GR32:%vreg42 GR64:%vreg43
8480B		MOV32mr <fi#6>, 1, %noreg, 0, %noreg, %vreg42; mem:ST4[%c_nblock_used] GR32:%vreg42
8496B		%vreg39<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg39
8512B		%vreg38<def> = MOV32rm %vreg39, 1, %noreg, 64, %noreg; mem:LD4[%k0280] GR32:%vreg38 GR64:%vreg39
8528B		MOV32mr <fi#7>, 1, %noreg, 0, %noreg, %vreg38; mem:ST4[%c_k0] GR32:%vreg38
8544B		%vreg35<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg35
8560B		%vreg34<def> = MOV64rm %vreg35, 1, %noreg, 3152, %noreg; mem:LD8[%tt281] GR64:%vreg34,%vreg35
8576B		MOV64mr <fi#8>, 1, %noreg, 0, %noreg, %vreg34; mem:ST8[%c_tt] GR64:%vreg34
8592B		%vreg31<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg31
8608B		%vreg30<def> = MOV32rm %vreg31, 1, %noreg, 60, %noreg; mem:LD4[%tPos282] GR32:%vreg30 GR64:%vreg31
8624B		MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %vreg30; mem:ST4[%c_tPos] GR32:%vreg30
8640B		%vreg27<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg27
8656B		%vreg26<def> = MOV64rm %vreg27, 1, %noreg, 0, %noreg; mem:LD8[%strm283] GR64:%vreg26,%vreg27
8672B		%vreg24<def> = MOV64rm %vreg26, 1, %noreg, 24, %noreg; mem:LD8[%next_out284] GR64:%vreg24,%vreg26
8688B		MOV64mr <fi#10>, 1, %noreg, 0, %noreg, %vreg24; mem:ST8[%cs_next_out] GR64:%vreg24
8704B		%vreg21<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg21
8720B		%vreg20<def> = MOV64rm %vreg21, 1, %noreg, 0, %noreg; mem:LD8[%strm285] GR64:%vreg20,%vreg21
8736B		%vreg18<def> = MOV32rm %vreg20, 1, %noreg, 32, %noreg; mem:LD4[%avail_out286] GR32:%vreg18 GR64:%vreg20
8752B		MOV32mr <fi#11>, 1, %noreg, 0, %noreg, %vreg18; mem:ST4[%cs_avail_out] GR32:%vreg18
8768B		%vreg15<def> = MOV32rm <fi#11>, 1, %noreg, 0, %noreg; mem:LD4[%cs_avail_out] GR32:%vreg15
8784B		MOV32mr <fi#12>, 1, %noreg, 0, %noreg, %vreg15; mem:ST4[%avail_out_INIT] GR32:%vreg15
8800B		%vreg13<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg13
8816B		%vreg10<def> = MOV32rm %vreg13, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock287] GR32:%vreg10 GR64:%vreg13
8848B		%vreg10<def,tied1> = ADD32ri8 %vreg10<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg10
8864B		MOV32mr <fi#13>, 1, %noreg, 0, %noreg, %vreg10; mem:ST4[%s_save_nblockPP] GR32:%vreg10
	    Successors according to CFG: BB#48

8880B	BB#48: derived from LLVM BB %while.body.289
	    Predecessors according to CFG: BB#47 BB#75 BB#74 BB#72 BB#70 BB#68
8896B		CMP32mi8 <fi#5>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%c_state_out_len]
8912B		JLE_1 <BB#59>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#59 BB#49

8928B	BB#49: derived from LLVM BB %if.then.292
	    Predecessors according to CFG: BB#48
8944B		JMP_1 <BB#50>
	    Successors according to CFG: BB#50

8960B	BB#50: derived from LLVM BB %while.body.294
	    Predecessors according to CFG: BB#49 BB#54
8976B		CMP32mi8 <fi#11>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%cs_avail_out]
8992B		JNE_1 <BB#52>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#52 BB#51

9008B	BB#51: derived from LLVM BB %if.then.297
	    Predecessors according to CFG: BB#50
9024B		JMP_1 <BB#76>
	    Successors according to CFG: BB#76

9040B	BB#52: derived from LLVM BB %if.end.298
	    Predecessors according to CFG: BB#50
9056B		CMP32mi8 <fi#5>, 1, %noreg, 0, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%c_state_out_len]
9072B		JNE_1 <BB#54>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#54 BB#53

9088B	BB#53: derived from LLVM BB %if.then.301
	    Predecessors according to CFG: BB#52
9104B		JMP_1 <BB#55>
	    Successors according to CFG: BB#55

9120B	BB#54: derived from LLVM BB %if.end.302
	    Predecessors according to CFG: BB#52
9136B		%vreg93<def> = MOV8rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD1[%c_state_out_ch] GR8:%vreg93
9152B		%vreg92<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%cs_next_out] GR64:%vreg92
9168B		MOV8mr %vreg92, 1, %noreg, 0, %noreg, %vreg93; mem:ST1[%249] GR64:%vreg92 GR8:%vreg93
9184B		%vreg74<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%c_calculatedBlockCRC] GR32:%vreg74
9216B		%vreg74<def,tied1> = SHL32ri %vreg74<tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg74
9232B		%vreg81<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%c_calculatedBlockCRC] GR32:%vreg81
9264B		%vreg81<def,tied1> = SHR32ri %vreg81<tied0>, 24, %EFLAGS<imp-def,dead>; GR32:%vreg81
9280B		%vreg83<def> = MOVZX32rm8 <fi#4>, 1, %noreg, 0, %noreg; mem:LD1[%c_state_out_ch] GR32:%vreg83
9312B		%vreg81<def,tied1> = XOR32rr %vreg81<tied0>, %vreg83, %EFLAGS<imp-def,dead>; GR32:%vreg81,%vreg83
9328B		%vreg78:sub_32bit<def,read-undef> = MOV32rr %vreg81; GR64_NOSP:%vreg78 GR32:%vreg81
9376B		%vreg74<def,tied1> = XOR32rm %vreg74<tied0>, %noreg, 4, %vreg78, <ga:@BZ2_crc32Table>, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%arrayidx308] GR32:%vreg74 GR64_NOSP:%vreg78
9392B		MOV32mr <fi#3>, 1, %noreg, 0, %noreg, %vreg74; mem:ST4[%c_calculatedBlockCRC] GR32:%vreg74
9408B		%vreg69<def> = MOV32rm <fi#5>, 1, %noreg, 0, %noreg; mem:LD4[%c_state_out_len] GR32:%vreg69
9440B		%vreg69<def,tied1> = ADD32ri8 %vreg69<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg69
9456B		MOV32mr <fi#5>, 1, %noreg, 0, %noreg, %vreg69; mem:ST4[%c_state_out_len] GR32:%vreg69
9472B		%vreg65<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%cs_next_out] GR64:%vreg65
9504B		%vreg65<def,tied1> = ADD64ri8 %vreg65<tied0>, 1, %EFLAGS<imp-def,dead>; GR64:%vreg65
9520B		MOV64mr <fi#10>, 1, %noreg, 0, %noreg, %vreg65; mem:ST8[%cs_next_out] GR64:%vreg65
9536B		%vreg61<def> = MOV32rm <fi#11>, 1, %noreg, 0, %noreg; mem:LD4[%cs_avail_out] GR32:%vreg61
9568B		%vreg61<def,tied1> = ADD32ri8 %vreg61<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg61
9584B		MOV32mr <fi#11>, 1, %noreg, 0, %noreg, %vreg61; mem:ST4[%cs_avail_out] GR32:%vreg61
9600B		JMP_1 <BB#50>
	    Successors according to CFG: BB#50

9616B	BB#55: derived from LLVM BB %while.end.313
	    Predecessors according to CFG: BB#53
9632B		JMP_1 <BB#56>
	    Successors according to CFG: BB#56

9648B	BB#56: derived from LLVM BB %s_state_out_len_eq_one
	    Predecessors according to CFG: BB#55 BB#66 BB#64
9664B		CMP32mi8 <fi#11>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%cs_avail_out]
9680B		JNE_1 <BB#58>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#58 BB#57

9696B	BB#57: derived from LLVM BB %if.then.316
	    Predecessors according to CFG: BB#56
9712B		MOV32mi <fi#5>, 1, %noreg, 0, %noreg, 1; mem:ST4[%c_state_out_len]
9728B		JMP_1 <BB#76>
	    Successors according to CFG: BB#76

9744B	BB#58: derived from LLVM BB %if.end.317
	    Predecessors according to CFG: BB#56
9760B		%vreg125<def> = MOV8rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD1[%c_state_out_ch] GR8:%vreg125
9776B		%vreg124<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%cs_next_out] GR64:%vreg124
9792B		MOV8mr %vreg124, 1, %noreg, 0, %noreg, %vreg125; mem:ST1[%259] GR64:%vreg124 GR8:%vreg125
9808B		%vreg106<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%c_calculatedBlockCRC] GR32:%vreg106
9840B		%vreg106<def,tied1> = SHL32ri %vreg106<tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg106
9856B		%vreg113<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%c_calculatedBlockCRC] GR32:%vreg113
9888B		%vreg113<def,tied1> = SHR32ri %vreg113<tied0>, 24, %EFLAGS<imp-def,dead>; GR32:%vreg113
9904B		%vreg115<def> = MOVZX32rm8 <fi#4>, 1, %noreg, 0, %noreg; mem:LD1[%c_state_out_ch] GR32:%vreg115
9936B		%vreg113<def,tied1> = XOR32rr %vreg113<tied0>, %vreg115, %EFLAGS<imp-def,dead>; GR32:%vreg113,%vreg115
9952B		%vreg110:sub_32bit<def,read-undef> = MOV32rr %vreg113; GR64_NOSP:%vreg110 GR32:%vreg113
10000B		%vreg106<def,tied1> = XOR32rm %vreg106<tied0>, %noreg, 4, %vreg110, <ga:@BZ2_crc32Table>, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%arrayidx323] GR32:%vreg106 GR64_NOSP:%vreg110
10016B		MOV32mr <fi#3>, 1, %noreg, 0, %noreg, %vreg106; mem:ST4[%c_calculatedBlockCRC] GR32:%vreg106
10032B		%vreg101<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%cs_next_out] GR64:%vreg101
10064B		%vreg101<def,tied1> = ADD64ri8 %vreg101<tied0>, 1, %EFLAGS<imp-def,dead>; GR64:%vreg101
10080B		MOV64mr <fi#10>, 1, %noreg, 0, %noreg, %vreg101; mem:ST8[%cs_next_out] GR64:%vreg101
10096B		%vreg97<def> = MOV32rm <fi#11>, 1, %noreg, 0, %noreg; mem:LD4[%cs_avail_out] GR32:%vreg97
10128B		%vreg97<def,tied1> = ADD32ri8 %vreg97<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg97
10144B		MOV32mr <fi#11>, 1, %noreg, 0, %noreg, %vreg97; mem:ST4[%cs_avail_out] GR32:%vreg97
	    Successors according to CFG: BB#59

10160B	BB#59: derived from LLVM BB %if.end.327
	    Predecessors according to CFG: BB#48 BB#58
10176B		%vreg128<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%c_nblock_used] GR32:%vreg128
10192B		CMP32rm %vreg128, <fi#13>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD4[%s_save_nblockPP] GR32:%vreg128
10208B		JLE_1 <BB#61>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#61 BB#60

10224B	BB#60: derived from LLVM BB %if.then.330
	    Predecessors according to CFG: BB#59
10240B		MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 1; mem:ST1[%retval]
10256B		JMP_1 <BB#80>
	    Successors according to CFG: BB#80

10272B	BB#61: derived from LLVM BB %if.end.331
	    Predecessors according to CFG: BB#59
10288B		%vreg131<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%c_nblock_used] GR32:%vreg131
10304B		CMP32rm %vreg131, <fi#13>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD4[%s_save_nblockPP] GR32:%vreg131
10320B		JNE_1 <BB#63>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#63 BB#62

10336B	BB#62: derived from LLVM BB %if.then.334
	    Predecessors according to CFG: BB#61
10352B		MOV32mi <fi#5>, 1, %noreg, 0, %noreg, 0; mem:ST4[%c_state_out_len]
10368B		JMP_1 <BB#76>
	    Successors according to CFG: BB#76

10384B	BB#63: derived from LLVM BB %if.end.335
	    Predecessors according to CFG: BB#61
10400B		%vreg161<def> = MOV32rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD4[%c_k0] GR32:%vreg161
10432B		MOV8mr <fi#4>, 1, %noreg, 0, %noreg, %vreg161:sub_8bit; mem:ST1[%c_state_out_ch] GR32:%vreg161
10448B		%vreg157:sub_32bit<def,read-undef> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR64_NOSP:%vreg157
10480B		%vreg154<def> = MOV64rm <fi#8>, 1, %noreg, 0, %noreg; mem:LD8[%c_tt] GR64:%vreg154
10496B		%vreg153<def> = MOV32rm %vreg154, 4, %vreg157, 0, %noreg; mem:LD4[%arrayidx338] GR32:%vreg153 GR64:%vreg154 GR64_NOSP:%vreg157
10512B		MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %vreg153; mem:ST4[%c_tPos] GR32:%vreg153
10528B		%vreg148<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR32:%vreg148
10560B		%vreg148<def,tied1> = AND32ri %vreg148<tied0>, 255, %EFLAGS<imp-def,dead>; GR32:%vreg148
10592B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg148:sub_8bit; mem:ST1[%k1] GR32:%vreg148
10608B		%vreg142<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR32:%vreg142
10640B		%vreg142<def,tied1> = SHR32ri %vreg142<tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg142
10656B		MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %vreg142; mem:ST4[%c_tPos] GR32:%vreg142
10672B		%vreg138<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%c_nblock_used] GR32:%vreg138
10704B		%vreg138<def,tied1> = ADD32ri8 %vreg138<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg138
10720B		MOV32mr <fi#6>, 1, %noreg, 0, %noreg, %vreg138; mem:ST4[%c_nblock_used] GR32:%vreg138
10736B		%vreg135<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg135
10752B		CMP32rm %vreg135, <fi#7>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD4[%c_k0] GR32:%vreg135
10768B		JE_1 <BB#65>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#65 BB#64

10784B	BB#64: derived from LLVM BB %if.then.346
	    Predecessors according to CFG: BB#63
10800B		%vreg282<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg282
10816B		MOV32mr <fi#7>, 1, %noreg, 0, %noreg, %vreg282; mem:ST4[%c_k0] GR32:%vreg282
10832B		JMP_1 <BB#56>
	    Successors according to CFG: BB#56

10848B	BB#65: derived from LLVM BB %if.end.348
	    Predecessors according to CFG: BB#63
10864B		%vreg164<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%c_nblock_used] GR32:%vreg164
10880B		CMP32rm %vreg164, <fi#13>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD4[%s_save_nblockPP] GR32:%vreg164
10896B		JNE_1 <BB#67>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#67 BB#66

10912B	BB#66: derived from LLVM BB %if.then.351
	    Predecessors according to CFG: BB#65
10928B		JMP_1 <BB#56>
	    Successors according to CFG: BB#56

10944B	BB#67: derived from LLVM BB %if.end.352
	    Predecessors according to CFG: BB#65
10960B		MOV32mi <fi#5>, 1, %noreg, 0, %noreg, 2; mem:ST4[%c_state_out_len]
10976B		%vreg189:sub_32bit<def,read-undef> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR64_NOSP:%vreg189
11008B		%vreg186<def> = MOV64rm <fi#8>, 1, %noreg, 0, %noreg; mem:LD8[%c_tt] GR64:%vreg186
11024B		%vreg185<def> = MOV32rm %vreg186, 4, %vreg189, 0, %noreg; mem:LD4[%arrayidx354] GR32:%vreg185 GR64:%vreg186 GR64_NOSP:%vreg189
11040B		MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %vreg185; mem:ST4[%c_tPos] GR32:%vreg185
11056B		%vreg180<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR32:%vreg180
11088B		%vreg180<def,tied1> = AND32ri %vreg180<tied0>, 255, %EFLAGS<imp-def,dead>; GR32:%vreg180
11120B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg180:sub_8bit; mem:ST1[%k1] GR32:%vreg180
11136B		%vreg174<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR32:%vreg174
11168B		%vreg174<def,tied1> = SHR32ri %vreg174<tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg174
11184B		MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %vreg174; mem:ST4[%c_tPos] GR32:%vreg174
11200B		%vreg170<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%c_nblock_used] GR32:%vreg170
11232B		%vreg170<def,tied1> = ADD32ri8 %vreg170<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg170
11248B		MOV32mr <fi#6>, 1, %noreg, 0, %noreg, %vreg170; mem:ST4[%c_nblock_used] GR32:%vreg170
11264B		%vreg167<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%c_nblock_used] GR32:%vreg167
11280B		CMP32rm %vreg167, <fi#13>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD4[%s_save_nblockPP] GR32:%vreg167
11296B		JNE_1 <BB#69>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#69 BB#68

11312B	BB#68: derived from LLVM BB %if.then.361
	    Predecessors according to CFG: BB#67
11328B		JMP_1 <BB#48>
	    Successors according to CFG: BB#48

11344B	BB#69: derived from LLVM BB %if.end.362
	    Predecessors according to CFG: BB#67
11360B		%vreg193<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg193
11376B		CMP32rm %vreg193, <fi#7>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD4[%c_k0] GR32:%vreg193
11392B		JE_1 <BB#71>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#71 BB#70

11408B	BB#70: derived from LLVM BB %if.then.366
	    Predecessors according to CFG: BB#69
11424B		%vreg279<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg279
11440B		MOV32mr <fi#7>, 1, %noreg, 0, %noreg, %vreg279; mem:ST4[%c_k0] GR32:%vreg279
11456B		JMP_1 <BB#48>
	    Successors according to CFG: BB#48

11472B	BB#71: derived from LLVM BB %if.end.368
	    Predecessors according to CFG: BB#69
11488B		MOV32mi <fi#5>, 1, %noreg, 0, %noreg, 3; mem:ST4[%c_state_out_len]
11504B		%vreg218:sub_32bit<def,read-undef> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR64_NOSP:%vreg218
11536B		%vreg215<def> = MOV64rm <fi#8>, 1, %noreg, 0, %noreg; mem:LD8[%c_tt] GR64:%vreg215
11552B		%vreg214<def> = MOV32rm %vreg215, 4, %vreg218, 0, %noreg; mem:LD4[%arrayidx370] GR32:%vreg214 GR64:%vreg215 GR64_NOSP:%vreg218
11568B		MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %vreg214; mem:ST4[%c_tPos] GR32:%vreg214
11584B		%vreg209<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR32:%vreg209
11616B		%vreg209<def,tied1> = AND32ri %vreg209<tied0>, 255, %EFLAGS<imp-def,dead>; GR32:%vreg209
11648B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg209:sub_8bit; mem:ST1[%k1] GR32:%vreg209
11664B		%vreg203<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR32:%vreg203
11696B		%vreg203<def,tied1> = SHR32ri %vreg203<tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg203
11712B		MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %vreg203; mem:ST4[%c_tPos] GR32:%vreg203
11728B		%vreg199<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%c_nblock_used] GR32:%vreg199
11760B		%vreg199<def,tied1> = ADD32ri8 %vreg199<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg199
11776B		MOV32mr <fi#6>, 1, %noreg, 0, %noreg, %vreg199; mem:ST4[%c_nblock_used] GR32:%vreg199
11792B		%vreg196<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%c_nblock_used] GR32:%vreg196
11808B		CMP32rm %vreg196, <fi#13>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD4[%s_save_nblockPP] GR32:%vreg196
11824B		JNE_1 <BB#73>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#73 BB#72

11840B	BB#72: derived from LLVM BB %if.then.377
	    Predecessors according to CFG: BB#71
11856B		JMP_1 <BB#48>
	    Successors according to CFG: BB#48

11872B	BB#73: derived from LLVM BB %if.end.378
	    Predecessors according to CFG: BB#71
11888B		%vreg222<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg222
11904B		CMP32rm %vreg222, <fi#7>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD4[%c_k0] GR32:%vreg222
11920B		JE_1 <BB#75>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#75 BB#74

11936B	BB#74: derived from LLVM BB %if.then.382
	    Predecessors according to CFG: BB#73
11952B		%vreg276<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg276
11968B		MOV32mr <fi#7>, 1, %noreg, 0, %noreg, %vreg276; mem:ST4[%c_k0] GR32:%vreg276
11984B		JMP_1 <BB#48>
	    Successors according to CFG: BB#48

12000B	BB#75: derived from LLVM BB %if.end.384
	    Predecessors according to CFG: BB#73
12016B		%vreg273:sub_32bit<def,read-undef> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR64_NOSP:%vreg273
12048B		%vreg270<def> = MOV64rm <fi#8>, 1, %noreg, 0, %noreg; mem:LD8[%c_tt] GR64:%vreg270
12064B		%vreg269<def> = MOV32rm %vreg270, 4, %vreg273, 0, %noreg; mem:LD4[%arrayidx386] GR32:%vreg269 GR64:%vreg270 GR64_NOSP:%vreg273
12080B		MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %vreg269; mem:ST4[%c_tPos] GR32:%vreg269
12096B		%vreg264<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR32:%vreg264
12128B		%vreg264<def,tied1> = AND32ri %vreg264<tied0>, 255, %EFLAGS<imp-def,dead>; GR32:%vreg264
12160B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg264:sub_8bit; mem:ST1[%k1] GR32:%vreg264
12176B		%vreg258<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR32:%vreg258
12208B		%vreg258<def,tied1> = SHR32ri %vreg258<tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg258
12224B		MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %vreg258; mem:ST4[%c_tPos] GR32:%vreg258
12240B		%vreg254<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%c_nblock_used] GR32:%vreg254
12272B		%vreg254<def,tied1> = ADD32ri8 %vreg254<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg254
12288B		MOV32mr <fi#6>, 1, %noreg, 0, %noreg, %vreg254; mem:ST4[%c_nblock_used] GR32:%vreg254
12304B		%vreg249<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg249
12336B		%vreg249<def,tied1> = ADD32ri8 %vreg249<tied0>, 4, %EFLAGS<imp-def,dead>; GR32:%vreg249
12352B		MOV32mr <fi#5>, 1, %noreg, 0, %noreg, %vreg249; mem:ST4[%c_state_out_len] GR32:%vreg249
12368B		%vreg246:sub_32bit<def,read-undef> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR64_NOSP:%vreg246
12400B		%vreg243<def> = MOV64rm <fi#8>, 1, %noreg, 0, %noreg; mem:LD8[%c_tt] GR64:%vreg243
12416B		%vreg242<def> = MOV32rm %vreg243, 4, %vreg246, 0, %noreg; mem:LD4[%arrayidx394] GR32:%vreg242 GR64:%vreg243 GR64_NOSP:%vreg246
12432B		MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %vreg242; mem:ST4[%c_tPos] GR32:%vreg242
12448B		%vreg237<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR32:%vreg237
12480B		%vreg237<def,tied1> = AND32ri %vreg237<tied0>, 255, %EFLAGS<imp-def,dead>; GR32:%vreg237
12512B		%vreg233<def> = MOVZX32rr8 %vreg237:sub_8bit; GR32:%vreg233,%vreg237
12528B		MOV32mr <fi#7>, 1, %noreg, 0, %noreg, %vreg233; mem:ST4[%c_k0] GR32:%vreg233
12544B		%vreg229<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR32:%vreg229
12576B		%vreg229<def,tied1> = SHR32ri %vreg229<tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg229
12592B		MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %vreg229; mem:ST4[%c_tPos] GR32:%vreg229
12608B		%vreg225<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%c_nblock_used] GR32:%vreg225
12640B		%vreg225<def,tied1> = ADD32ri8 %vreg225<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg225
12656B		MOV32mr <fi#6>, 1, %noreg, 0, %noreg, %vreg225; mem:ST4[%c_nblock_used] GR32:%vreg225
12672B		JMP_1 <BB#48>
	    Successors according to CFG: BB#48

12688B	BB#76: derived from LLVM BB %return_notr
	    Predecessors according to CFG: BB#62 BB#57 BB#51
12704B		%vreg307<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg307
12720B		%vreg306<def> = MOV64rm %vreg307, 1, %noreg, 0, %noreg; mem:LD8[%strm400] GR64:%vreg306,%vreg307
12736B		%vreg304<def> = MOV32rm %vreg306, 1, %noreg, 36, %noreg; mem:LD4[%total_out_lo32401] GR32:%vreg304 GR64:%vreg306
12752B		MOV32mr <fi#14>, 1, %noreg, 0, %noreg, %vreg304; mem:ST4[%total_out_lo32_old] GR32:%vreg304
12768B		%vreg294<def> = MOV32rm <fi#12>, 1, %noreg, 0, %noreg; mem:LD4[%avail_out_INIT] GR32:%vreg294
12800B		%vreg294<def,tied1> = SUB32rm %vreg294<tied0>, <fi#11>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%cs_avail_out] GR32:%vreg294
12816B		%vreg297<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg297
12832B		%vreg296<def> = MOV64rm %vreg297, 1, %noreg, 0, %noreg; mem:LD8[%strm402] GR64:%vreg296,%vreg297
12864B		%vreg294<def,tied1> = ADD32rm %vreg294<tied0>, %vreg296, 1, %noreg, 36, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%total_out_lo32403] GR32:%vreg294 GR64:%vreg296
12880B		MOV32mr %vreg296, 1, %noreg, 36, %noreg, %vreg294; mem:ST4[%total_out_lo32403] GR64:%vreg296 GR32:%vreg294
12896B		%vreg289<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg289
12912B		%vreg288<def> = MOV64rm %vreg289, 1, %noreg, 0, %noreg; mem:LD8[%strm405] GR64:%vreg288,%vreg289
12928B		%vreg286<def> = MOV32rm %vreg288, 1, %noreg, 36, %noreg; mem:LD4[%total_out_lo32406] GR32:%vreg286 GR64:%vreg288
12944B		CMP32rm %vreg286, <fi#14>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD4[%total_out_lo32_old] GR32:%vreg286
12960B		JAE_1 <BB#78>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#78 BB#77

12976B	BB#77: derived from LLVM BB %if.then.409
	    Predecessors according to CFG: BB#76
12992B		%vreg315<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg315
13008B		%vreg314<def> = MOV64rm %vreg315, 1, %noreg, 0, %noreg; mem:LD8[%strm410] GR64:%vreg314,%vreg315
13024B		%vreg311<def> = MOV32rm %vreg314, 1, %noreg, 40, %noreg; mem:LD4[%total_out_hi32411] GR32:%vreg311 GR64:%vreg314
13056B		%vreg311<def,tied1> = ADD32ri8 %vreg311<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg311
13072B		MOV32mr %vreg314, 1, %noreg, 40, %noreg, %vreg311; mem:ST4[%total_out_hi32411] GR64:%vreg314 GR32:%vreg311
	    Successors according to CFG: BB#78

13088B	BB#78: derived from LLVM BB %if.end.413
	    Predecessors according to CFG: BB#76 BB#77
13104B		%vreg355<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%c_calculatedBlockCRC] GR32:%vreg355
13120B		%vreg354<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg354
13136B		MOV32mr %vreg354, 1, %noreg, 3184, %noreg, %vreg355; mem:ST4[%calculatedBlockCRC414] GR64:%vreg354 GR32:%vreg355
13152B		%vreg351<def> = MOV8rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD1[%c_state_out_ch] GR8:%vreg351
13168B		%vreg350<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg350
13184B		MOV8mr %vreg350, 1, %noreg, 12, %noreg, %vreg351; mem:ST1[%state_out_ch415] GR64:%vreg350 GR8:%vreg351
13200B		%vreg347<def> = MOV32rm <fi#5>, 1, %noreg, 0, %noreg; mem:LD4[%c_state_out_len] GR32:%vreg347
13216B		%vreg346<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg346
13232B		MOV32mr %vreg346, 1, %noreg, 16, %noreg, %vreg347; mem:ST4[%state_out_len416] GR64:%vreg346 GR32:%vreg347
13248B		%vreg343<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%c_nblock_used] GR32:%vreg343
13264B		%vreg342<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg342
13280B		MOV32mr %vreg342, 1, %noreg, 1092, %noreg, %vreg343; mem:ST4[%nblock_used417] GR64:%vreg342 GR32:%vreg343
13296B		%vreg339<def> = MOV32rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD4[%c_k0] GR32:%vreg339
13312B		%vreg338<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg338
13328B		MOV32mr %vreg338, 1, %noreg, 64, %noreg, %vreg339; mem:ST4[%k0418] GR64:%vreg338 GR32:%vreg339
13344B		%vreg335<def> = MOV64rm <fi#8>, 1, %noreg, 0, %noreg; mem:LD8[%c_tt] GR64:%vreg335
13360B		%vreg334<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg334
13376B		MOV64mr %vreg334, 1, %noreg, 3152, %noreg, %vreg335; mem:ST8[%tt419] GR64:%vreg334,%vreg335
13392B		%vreg331<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR32:%vreg331
13408B		%vreg330<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg330
13424B		MOV32mr %vreg330, 1, %noreg, 60, %noreg, %vreg331; mem:ST4[%tPos420] GR64:%vreg330 GR32:%vreg331
13440B		%vreg327<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%cs_next_out] GR64:%vreg327
13456B		%vreg326<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg326
13472B		%vreg325<def> = MOV64rm %vreg326, 1, %noreg, 0, %noreg; mem:LD8[%strm421] GR64:%vreg325,%vreg326
13488B		MOV64mr %vreg325, 1, %noreg, 24, %noreg, %vreg327; mem:ST8[%next_out422] GR64:%vreg325,%vreg327
13504B		%vreg321<def> = MOV32rm <fi#11>, 1, %noreg, 0, %noreg; mem:LD4[%cs_avail_out] GR32:%vreg321
13520B		%vreg320<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg320
13536B		%vreg319<def> = MOV64rm %vreg320, 1, %noreg, 0, %noreg; mem:LD8[%strm423] GR64:%vreg319,%vreg320
13552B		MOV32mr %vreg319, 1, %noreg, 32, %noreg, %vreg321; mem:ST4[%avail_out424] GR64:%vreg319 GR32:%vreg321
	    Successors according to CFG: BB#79

13568B	BB#79: derived from LLVM BB %if.end.425
	    Predecessors according to CFG: BB#78
13584B		MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST1[%retval]
	    Successors according to CFG: BB#80

13600B	BB#80: derived from LLVM BB %return
	    Predecessors according to CFG: BB#60 BB#79 BB#13 BB#11 BB#4
13616B		%vreg938<def> = MOV64ri <ga:@unRLE_obuf_to_output_FAST>; GR64:%vreg938
13648B		%vreg939<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg939
13664B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
13680B		%RDI<def> = COPY %vreg938; GR64:%vreg938
13696B		%RSI<def> = COPY %vreg939; GR64:%vreg939
13712B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
13728B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
13744B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
13760B		STACKMAP 1, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=1)
13776B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
13792B		%vreg936<def> = MOV8rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD1[%retval] GR8:%vreg936
13808B		%AL<def> = COPY %vreg936; GR8:%vreg936
13824B		RETQ %AL<imp-use,kill>

# End machine code for function unRLE_obuf_to_output_FAST.

AllocationOrder(SEGMENT_REG) = [ ]
AllocationOrder(SEGMENT_REG) = [ ]
AllocationOrder(SEGMENT_REG) = [ ]
AllocationOrder(SEGMENT_REG) = [ ]
AllocationOrder(SEGMENT_REG) = [ ]
AllocationOrder(SEGMENT_REG) = [ ]
AllocationOrder(SEGMENT_REG) = [ ]
AllocationOrder(SEGMENT_REG) = [ ]
AllocationOrder(SEGMENT_REG) = [ ]
AllocationOrder(SEGMENT_REG) = [ ]
AllocationOrder(SEGMENT_REG) = [ ]
AllocationOrder(SEGMENT_REG) = [ ]
AllocationOrder(SEGMENT_REG) = [ ]
AllocationOrder(SEGMENT_REG) = [ ]
AllocationOrder(SEGMENT_REG) = [ ]
AllocationOrder(SEGMENT_REG) = [ ]
AllocationOrder(SEGMENT_REG) = [ ]
AllocationOrder(SEGMENT_REG) = [ ]
AllocationOrder(SEGMENT_REG) = [ ]
AllocationOrder(SEGMENT_REG) = [ ]
AllocationOrder(SEGMENT_REG) = [ ]
AllocationOrder(SEGMENT_REG) = [ ]
AllocationOrder(SEGMENT_REG) = [ ]
AllocationOrder(SEGMENT_REG) = [ ]
********** GREEDY REGISTER ALLOCATION **********
********** Function: unRLE_obuf_to_output_FAST
********** INTERVALS **********
DIL [0B,16r:0)[112r,144r:2)[13680r,13712r:1)  0@0B-phi 1@13680r 2@112r
%vreg1 [16r,224r:0)  0@16r
%vreg4 [240r,256r:0)  0@240r
%vreg6 [48r,112r:0)  0@48r
%vreg7 [80r,128r:0)  0@80r
%vreg10 [8816r,8848r:0)[8848r,8864r:1)  0@8816r 1@8848r
%vreg13 [8800r,8816r:0)  0@8800r
%vreg15 [8768r,8784r:0)  0@8768r
%vreg18 [8736r,8752r:0)  0@8736r
%vreg20 [8720r,8736r:0)  0@8720r
%vreg21 [8704r,8720r:0)  0@8704r
%vreg24 [8672r,8688r:0)  0@8672r
%vreg26 [8656r,8672r:0)  0@8656r
%vreg27 [8640r,8656r:0)  0@8640r
%vreg30 [8608r,8624r:0)  0@8608r
%vreg31 [8592r,8608r:0)  0@8592r
%vreg34 [8560r,8576r:0)  0@8560r
%vreg35 [8544r,8560r:0)  0@8544r
%vreg38 [8512r,8528r:0)  0@8512r
%vreg39 [8496r,8512r:0)  0@8496r
%vreg42 [8464r,8480r:0)  0@8464r
%vreg43 [8448r,8464r:0)  0@8448r
%vreg46 [8416r,8432r:0)  0@8416r
%vreg47 [8400r,8416r:0)  0@8400r
%vreg50 [8368r,8384r:0)  0@8368r
%vreg51 [8352r,8368r:0)  0@8352r
%vreg54 [8320r,8336r:0)  0@8320r
%vreg55 [8304r,8320r:0)  0@8304r
%vreg61 [9536r,9568r:0)[9568r,9584r:1)  0@9536r 1@9568r
%vreg65 [9472r,9504r:0)[9504r,9520r:1)  0@9472r 1@9504r
%vreg69 [9408r,9440r:0)[9440r,9456r:1)  0@9408r 1@9440r
%vreg74 [9184r,9216r:2)[9216r,9376r:0)[9376r,9392r:1)  0@9216r 1@9376r 2@9184r
%vreg78 [9328r,9376r:0)  0@9328r
%vreg81 [9232r,9264r:2)[9264r,9312r:0)[9312r,9328r:1)  0@9264r 1@9312r 2@9232r
%vreg83 [9280r,9312r:0)  0@9280r
%vreg92 [9152r,9168r:0)  0@9152r
%vreg93 [9136r,9168r:0)  0@9136r
%vreg97 [10096r,10128r:0)[10128r,10144r:1)  0@10096r 1@10128r
%vreg101 [10032r,10064r:0)[10064r,10080r:1)  0@10032r 1@10064r
%vreg106 [9808r,9840r:2)[9840r,10000r:0)[10000r,10016r:1)  0@9840r 1@10000r 2@9808r
%vreg110 [9952r,10000r:0)  0@9952r
%vreg113 [9856r,9888r:2)[9888r,9936r:0)[9936r,9952r:1)  0@9888r 1@9936r 2@9856r
%vreg115 [9904r,9936r:0)  0@9904r
%vreg124 [9776r,9792r:0)  0@9776r
%vreg125 [9760r,9792r:0)  0@9760r
%vreg128 [10176r,10192r:0)  0@10176r
%vreg131 [10288r,10304r:0)  0@10288r
%vreg135 [10736r,10752r:0)  0@10736r
%vreg138 [10672r,10704r:0)[10704r,10720r:1)  0@10672r 1@10704r
%vreg142 [10608r,10640r:0)[10640r,10656r:1)  0@10608r 1@10640r
%vreg148 [10528r,10560r:0)[10560r,10592r:1)  0@10528r 1@10560r
%vreg153 [10496r,10512r:0)  0@10496r
%vreg154 [10480r,10496r:0)  0@10480r
%vreg157 [10448r,10496r:0)  0@10448r
%vreg161 [10400r,10432r:0)  0@10400r
%vreg164 [10864r,10880r:0)  0@10864r
%vreg167 [11264r,11280r:0)  0@11264r
%vreg170 [11200r,11232r:0)[11232r,11248r:1)  0@11200r 1@11232r
%vreg174 [11136r,11168r:0)[11168r,11184r:1)  0@11136r 1@11168r
%vreg180 [11056r,11088r:0)[11088r,11120r:1)  0@11056r 1@11088r
%vreg185 [11024r,11040r:0)  0@11024r
%vreg186 [11008r,11024r:0)  0@11008r
%vreg189 [10976r,11024r:0)  0@10976r
%vreg193 [11360r,11376r:0)  0@11360r
%vreg196 [11792r,11808r:0)  0@11792r
%vreg199 [11728r,11760r:0)[11760r,11776r:1)  0@11728r 1@11760r
%vreg203 [11664r,11696r:0)[11696r,11712r:1)  0@11664r 1@11696r
%vreg209 [11584r,11616r:0)[11616r,11648r:1)  0@11584r 1@11616r
%vreg214 [11552r,11568r:0)  0@11552r
%vreg215 [11536r,11552r:0)  0@11536r
%vreg218 [11504r,11552r:0)  0@11504r
%vreg222 [11888r,11904r:0)  0@11888r
%vreg225 [12608r,12640r:0)[12640r,12656r:1)  0@12608r 1@12640r
%vreg229 [12544r,12576r:0)[12576r,12592r:1)  0@12544r 1@12576r
%vreg233 [12512r,12528r:0)  0@12512r
%vreg237 [12448r,12480r:0)[12480r,12512r:1)  0@12448r 1@12480r
%vreg242 [12416r,12432r:0)  0@12416r
%vreg243 [12400r,12416r:0)  0@12400r
%vreg246 [12368r,12416r:0)  0@12368r
%vreg249 [12304r,12336r:0)[12336r,12352r:1)  0@12304r 1@12336r
%vreg254 [12240r,12272r:0)[12272r,12288r:1)  0@12240r 1@12272r
%vreg258 [12176r,12208r:0)[12208r,12224r:1)  0@12176r 1@12208r
%vreg264 [12096r,12128r:0)[12128r,12160r:1)  0@12096r 1@12128r
%vreg269 [12064r,12080r:0)  0@12064r
%vreg270 [12048r,12064r:0)  0@12048r
%vreg273 [12016r,12064r:0)  0@12016r
%vreg276 [11952r,11968r:0)  0@11952r
%vreg279 [11424r,11440r:0)  0@11424r
%vreg282 [10800r,10816r:0)  0@10800r
%vreg286 [12928r,12944r:0)  0@12928r
%vreg288 [12912r,12928r:0)  0@12912r
%vreg289 [12896r,12912r:0)  0@12896r
%vreg294 [12768r,12800r:2)[12800r,12864r:0)[12864r,12880r:1)  0@12800r 1@12864r 2@12768r
%vreg296 [12832r,12880r:0)  0@12832r
%vreg297 [12816r,12832r:0)  0@12816r
%vreg304 [12736r,12752r:0)  0@12736r
%vreg306 [12720r,12736r:0)  0@12720r
%vreg307 [12704r,12720r:0)  0@12704r
%vreg311 [13024r,13056r:0)[13056r,13072r:1)  0@13024r 1@13056r
%vreg314 [13008r,13072r:0)  0@13008r
%vreg315 [12992r,13008r:0)  0@12992r
%vreg319 [13536r,13552r:0)  0@13536r
%vreg320 [13520r,13536r:0)  0@13520r
%vreg321 [13504r,13552r:0)  0@13504r
%vreg325 [13472r,13488r:0)  0@13472r
%vreg326 [13456r,13472r:0)  0@13456r
%vreg327 [13440r,13488r:0)  0@13440r
%vreg330 [13408r,13424r:0)  0@13408r
%vreg331 [13392r,13424r:0)  0@13392r
%vreg334 [13360r,13376r:0)  0@13360r
%vreg335 [13344r,13376r:0)  0@13344r
%vreg338 [13312r,13328r:0)  0@13312r
%vreg339 [13296r,13328r:0)  0@13296r
%vreg342 [13264r,13280r:0)  0@13264r
%vreg343 [13248r,13280r:0)  0@13248r
%vreg346 [13216r,13232r:0)  0@13216r
%vreg347 [13200r,13232r:0)  0@13200r
%vreg350 [13168r,13184r:0)  0@13168r
%vreg351 [13152r,13184r:0)  0@13152r
%vreg354 [13120r,13136r:0)  0@13120r
%vreg355 [13104r,13136r:0)  0@13104r
%vreg359 [384r,400r:0)  0@384r
%vreg360 [368r,384r:0)  0@368r
%vreg363 [496r,512r:0)  0@496r
%vreg367 [1360r,1376r:0)  0@1360r
%vreg368 [1344r,1360r:0)  0@1344r
%vreg372 [1280r,1312r:0)[1312r,1328r:1)  0@1280r 1@1312r
%vreg375 [1264r,1328r:0)  0@1264r
%vreg376 [1248r,1264r:0)  0@1248r
%vreg380 [1184r,1216r:0)[1216r,1232r:1)  0@1184r 1@1216r
%vreg383 [1168r,1232r:0)  0@1168r
%vreg384 [1152r,1168r:0)  0@1152r
%vreg388 [1088r,1120r:0)[1120r,1136r:1)  0@1088r 1@1120r
%vreg391 [1072r,1136r:0)  0@1072r
%vreg392 [1056r,1072r:0)  0@1056r
%vreg396 [992r,1024r:0)[1024r,1040r:1)  0@992r 1@1024r
%vreg398 [976r,1040r:0)  0@976r
%vreg401 [944r,960r:0)  0@944r
%vreg404 [704r,736r:2)[736r,928r:0)[928r,960r:1)  0@736r 1@928r 2@704r
%vreg408 [880r,928r:0)  0@880r
%vreg411 [768r,800r:2)[800r,864r:0)[864r,880r:1)  0@800r 1@864r 2@768r
%vreg413 [832r,864r:0)  0@832r
%vreg415 [816r,832r:0)  0@816r
%vreg420 [752r,768r:0)  0@752r
%vreg425 [688r,704r:0)  0@688r
%vreg429 [656r,672r:0)  0@656r
%vreg431 [640r,656r:0)  0@640r
%vreg432 [624r,640r:0)  0@624r
%vreg434 [608r,672r:0)  0@608r
%vreg435 [592r,608r:0)  0@592r
%vreg439 [1456r,1488r:0)[1488r,1504r:1)  0@1456r 1@1488r
%vreg442 [1440r,1504r:0)  0@1440r
%vreg443 [1424r,1440r:0)  0@1424r
%vreg447 [1616r,1648r:0)[1648r,1664r:1)  0@1616r 1@1648r
%vreg450 [1600r,1616r:0)  0@1600r
%vreg452 [1584r,1664r:0)  0@1584r
%vreg453 [1568r,1584r:0)  0@1568r
%vreg457 [1808r,1840r:0)[1840r,1856r:1)  0@1808r 1@1840r
%vreg460 [1792r,1808r:0)  0@1792r
%vreg462 [1776r,1856r:0)  0@1776r
%vreg463 [1760r,1776r:0)  0@1760r
%vreg466 [2368r,2384r:0)  0@2368r
%vreg470 [2304r,2336r:0)[2336r,2352r:1)  0@2304r 1@2336r
%vreg472 [2288r,2352r:0)  0@2288r
%vreg477 [2208r,2240r:0)[2240r,2272r:1)  0@2208r 1@2240r
%vreg480 [2192r,2208r:0)  0@2192r
%vreg483 [2160r,2176r:0)  0@2160r
%vreg486 [2144r,2176r:0)  0@2144r
%vreg488 [2128r,2144r:0)  0@2128r
%vreg489 [2112r,2128r:0)  0@2112r
%vreg492 [2080r,2144r:0)  0@2080r
%vreg494 [2064r,2080r:0)  0@2064r
%vreg497 [2032r,2048r:0)  0@2032r
%vreg501 [2000r,2048r:0)  0@2000r
%vreg502 [1984r,2000r:0)  0@1984r
%vreg504 [1952r,1968r:0)  0@1952r
%vreg507 [2592r,2608r:0)  0@2592r
%vreg511 [2528r,2560r:0)[2560r,2576r:1)  0@2528r 1@2560r
%vreg513 [2512r,2576r:0)  0@2512r
%vreg516 [2480r,2496r:0)  0@2480r
%vreg518 [2464r,2496r:0)  0@2464r
%vreg520 [2448r,2464r:0)  0@2448r
%vreg522 [2432r,2448r:0)  0@2432r
%vreg524 [2656r,2672r:0)  0@2656r
%vreg528 [3120r,3152r:0)[3152r,3168r:1)  0@3120r 1@3152r
%vreg531 [3104r,3120r:0)  0@3104r
%vreg533 [3088r,3168r:0)  0@3088r
%vreg534 [3072r,3088r:0)  0@3072r
%vreg538 [3008r,3040r:0)[3040r,3056r:1)  0@3008r 1@3040r
%vreg540 [2992r,3056r:0)  0@2992r
%vreg546 [2912r,2944r:0)[2944r,2976r:1)  0@2912r 1@2944r
%vreg551 [2752r,2896r:0)  0@2752r
%vreg552 [2736r,2896r:0)[2896r,2944r:1)  0@2736r 1@2896r
%vreg554 [2848r,2864r:0)  0@2848r
%vreg558 [2784r,2816r:0)[2816r,2832r:1)  0@2784r 1@2816r
%vreg560 [2768r,2832r:0)  0@2768r
%vreg564 [3264r,3280r:0)  0@3264r
%vreg566 [3248r,3280r:0)  0@3248r
%vreg569 [3744r,3760r:0)  0@3744r
%vreg573 [3680r,3712r:0)[3712r,3728r:1)  0@3680r 1@3712r
%vreg575 [3664r,3728r:0)  0@3664r
%vreg580 [3584r,3616r:0)[3616r,3648r:1)  0@3584r 1@3616r
%vreg583 [3568r,3584r:0)  0@3568r
%vreg586 [3536r,3552r:0)  0@3536r
%vreg589 [3520r,3552r:0)  0@3520r
%vreg591 [3504r,3520r:0)  0@3504r
%vreg592 [3488r,3504r:0)  0@3488r
%vreg595 [3456r,3520r:0)  0@3456r
%vreg597 [3440r,3456r:0)  0@3440r
%vreg599 [3408r,3424r:0)  0@3408r
%vreg602 [3968r,3984r:0)  0@3968r
%vreg606 [3904r,3936r:0)[3936r,3952r:1)  0@3904r 1@3936r
%vreg608 [3888r,3952r:0)  0@3888r
%vreg611 [3856r,3872r:0)  0@3856r
%vreg613 [3840r,3872r:0)  0@3840r
%vreg615 [3824r,3840r:0)  0@3824r
%vreg617 [3808r,3824r:0)  0@3808r
%vreg619 [4032r,4048r:0)  0@4032r
%vreg623 [4496r,4528r:0)[4528r,4544r:1)  0@4496r 1@4528r
%vreg626 [4480r,4496r:0)  0@4480r
%vreg628 [4464r,4544r:0)  0@4464r
%vreg629 [4448r,4464r:0)  0@4448r
%vreg633 [4384r,4416r:0)[4416r,4432r:1)  0@4384r 1@4416r
%vreg635 [4368r,4432r:0)  0@4368r
%vreg641 [4288r,4320r:0)[4320r,4352r:1)  0@4288r 1@4320r
%vreg646 [4128r,4272r:0)  0@4128r
%vreg647 [4112r,4272r:0)[4272r,4320r:1)  0@4112r 1@4272r
%vreg649 [4224r,4240r:0)  0@4224r
%vreg653 [4160r,4192r:0)[4192r,4208r:1)  0@4160r 1@4192r
%vreg655 [4144r,4208r:0)  0@4144r
%vreg659 [4640r,4656r:0)  0@4640r
%vreg661 [4624r,4656r:0)  0@4624r
%vreg664 [5120r,5136r:0)  0@5120r
%vreg668 [5056r,5088r:0)[5088r,5104r:1)  0@5056r 1@5088r
%vreg670 [5040r,5104r:0)  0@5040r
%vreg675 [4960r,4992r:0)[4992r,5024r:1)  0@4960r 1@4992r
%vreg678 [4944r,4960r:0)  0@4944r
%vreg681 [4912r,4928r:0)  0@4912r
%vreg684 [4896r,4928r:0)  0@4896r
%vreg686 [4880r,4896r:0)  0@4880r
%vreg687 [4864r,4880r:0)  0@4864r
%vreg690 [4832r,4896r:0)  0@4832r
%vreg692 [4816r,4832r:0)  0@4816r
%vreg694 [4784r,4800r:0)  0@4784r
%vreg697 [5344r,5360r:0)  0@5344r
%vreg701 [5280r,5312r:0)[5312r,5328r:1)  0@5280r 1@5312r
%vreg703 [5264r,5328r:0)  0@5264r
%vreg706 [5232r,5248r:0)  0@5232r
%vreg708 [5216r,5248r:0)  0@5216r
%vreg710 [5200r,5216r:0)  0@5200r
%vreg712 [5184r,5200r:0)  0@5184r
%vreg714 [5408r,5424r:0)  0@5408r
%vreg718 [5872r,5904r:0)[5904r,5920r:1)  0@5872r 1@5904r
%vreg721 [5856r,5872r:0)  0@5856r
%vreg723 [5840r,5920r:0)  0@5840r
%vreg724 [5824r,5840r:0)  0@5824r
%vreg728 [5760r,5792r:0)[5792r,5808r:1)  0@5760r 1@5792r
%vreg730 [5744r,5808r:0)  0@5744r
%vreg736 [5664r,5696r:0)[5696r,5728r:1)  0@5664r 1@5696r
%vreg741 [5504r,5648r:0)  0@5504r
%vreg742 [5488r,5648r:0)[5648r,5696r:1)  0@5488r 1@5648r
%vreg744 [5600r,5616r:0)  0@5600r
%vreg748 [5536r,5568r:0)[5568r,5584r:1)  0@5536r 1@5568r
%vreg750 [5520r,5584r:0)  0@5520r
%vreg754 [6016r,6032r:0)  0@6016r
%vreg756 [6000r,6032r:0)  0@6000r
%vreg759 [6464r,6480r:0)  0@6464r
%vreg763 [6400r,6432r:0)[6432r,6448r:1)  0@6400r 1@6432r
%vreg765 [6384r,6448r:0)  0@6384r
%vreg770 [6304r,6336r:0)[6336r,6368r:1)  0@6304r 1@6336r
%vreg773 [6288r,6304r:0)  0@6288r
%vreg776 [6256r,6272r:0)  0@6256r
%vreg779 [6240r,6272r:0)  0@6240r
%vreg781 [6224r,6240r:0)  0@6224r
%vreg782 [6208r,6224r:0)  0@6208r
%vreg785 [6176r,6240r:0)  0@6176r
%vreg787 [6160r,6176r:0)  0@6160r
%vreg790 [6688r,6704r:0)  0@6688r
%vreg794 [6624r,6656r:0)[6656r,6672r:1)  0@6624r 1@6656r
%vreg796 [6608r,6672r:0)  0@6608r
%vreg799 [6576r,6592r:0)  0@6576r
%vreg801 [6560r,6592r:0)  0@6560r
%vreg803 [6544r,6560r:0)  0@6544r
%vreg805 [6528r,6544r:0)  0@6528r
%vreg807 [6752r,6768r:0)  0@6752r
%vreg810 [7584r,7600r:0)  0@7584r
%vreg814 [7520r,7552r:0)[7552r,7568r:1)  0@7520r 1@7552r
%vreg816 [7504r,7568r:0)  0@7504r
%vreg819 [7472r,7488r:0)  0@7472r
%vreg821 [7456r,7488r:0)  0@7456r
%vreg825 [7392r,7424r:0)[7424r,7456r:1)  0@7392r 1@7424r
%vreg828 [7376r,7392r:0)  0@7376r
%vreg831 [7344r,7360r:0)  0@7344r
%vreg834 [7328r,7360r:0)  0@7328r
%vreg836 [7312r,7328r:0)  0@7312r
%vreg837 [7296r,7312r:0)  0@7296r
%vreg840 [7264r,7328r:0)  0@7264r
%vreg842 [7248r,7264r:0)  0@7248r
%vreg845 [7216r,7232r:0)  0@7216r
%vreg847 [7168r,7200r:0)[7200r,7232r:1)  0@7168r 1@7200r
%vreg853 [7104r,7136r:0)[7136r,7152r:1)  0@7104r 1@7136r
%vreg855 [7088r,7152r:0)  0@7088r
%vreg861 [7008r,7040r:0)[7040r,7072r:1)  0@7008r 1@7040r
%vreg866 [6848r,6992r:0)  0@6848r
%vreg867 [6832r,6992r:0)[6992r,7040r:1)  0@6832r 1@6992r
%vreg869 [6944r,6960r:0)  0@6944r
%vreg873 [6880r,6912r:0)[6912r,6928r:1)  0@6880r 1@6912r
%vreg875 [6864r,6928r:0)  0@6864r
%vreg878 [7808r,7824r:0)  0@7808r
%vreg882 [7744r,7776r:0)[7776r,7792r:1)  0@7744r 1@7776r
%vreg884 [7728r,7792r:0)  0@7728r
%vreg887 [7696r,7712r:0)  0@7696r
%vreg889 [7680r,7712r:0)  0@7680r
%vreg891 [7664r,7680r:0)  0@7664r
%vreg893 [7648r,7664r:0)  0@7648r
%vreg895 [7872r,7888r:0)  0@7872r
%vreg899 [8208r,8240r:0)[8240r,8256r:1)  0@8208r 1@8240r
%vreg901 [8192r,8256r:0)  0@8192r
%vreg906 [7952r,8112r:2)[8112r,8160r:0)[8160r,8176r:1)  0@8112r 1@8160r 2@7952r
%vreg907 [8128r,8176r:0)  0@8128r
%vreg910 [7968r,8112r:0)  0@7968r
%vreg913 [8064r,8080r:0)  0@8064r
%vreg917 [8000r,8032r:0)[8032r,8048r:1)  0@8000r 1@8032r
%vreg919 [7984r,8048r:0)  0@7984r
%vreg922 [6096r,6112r:0)  0@6096r
%vreg924 [6080r,6112r:0)  0@6080r
%vreg927 [4720r,4736r:0)  0@4720r
%vreg929 [4704r,4736r:0)  0@4704r
%vreg932 [3344r,3360r:0)  0@3344r
%vreg934 [3328r,3360r:0)  0@3328r
%vreg936 [13792r,13808r:0)  0@13792r
%vreg938 [13616r,13680r:0)  0@13616r
%vreg939 [13648r,13696r:0)  0@13648r
RegMasks: 144r 13712r
********** MACHINEINSTRS **********
# Machine code for function unRLE_obuf_to_output_FAST: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=1, align=1, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=1, align=1, at location [SP+8]
  fi#3: size=4, align=4, at location [SP+8]
  fi#4: size=1, align=1, at location [SP+8]
  fi#5: size=4, align=4, at location [SP+8]
  fi#6: size=4, align=4, at location [SP+8]
  fi#7: size=4, align=4, at location [SP+8]
  fi#8: size=8, align=8, at location [SP+8]
  fi#9: size=4, align=4, at location [SP+8]
  fi#10: size=8, align=8, at location [SP+8]
  fi#11: size=4, align=4, at location [SP+8]
  fi#12: size=4, align=4, at location [SP+8]
  fi#13: size=4, align=4, at location [SP+8]
  fi#14: size=4, align=4, at location [SP+8]
Function Live Ins: %RDI in %vreg0

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI
16B		%vreg1<def> = COPY %RDI; GR64:%vreg1
48B		%vreg6<def> = MOV64ri <ga:@unRLE_obuf_to_output_FAST>; GR64:%vreg6
80B		%vreg7<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg7
96B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
112B		%RDI<def> = COPY %vreg6; GR64:%vreg6
128B		%RSI<def> = COPY %vreg7; GR64:%vreg7
144B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
160B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
192B		STACKMAP 0, 0, 0, <fi#12>, 0, 0, <fi#3>, 0, 0, <fi#7>, 0, 0, <fi#6>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#9>, 0, 0, <fi#8>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, %vreg1, 0, <fi#1>, 0, 0, <fi#13>, 0, 0, <fi#14>, 0, ...; mem:LD8[FixedStack12](align=4) LD8[FixedStack3](align=4) LD8[FixedStack7](align=4) LD8[FixedStack6](align=4) LD8[FixedStack4](align=1) LD8[FixedStack5](align=4) LD8[FixedStack9](align=4) LD8[FixedStack8] LD8[FixedStack11](align=4) LD8[FixedStack10] LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1] LD8[FixedStack13](align=4) LD8[FixedStack14](align=4) GR64:%vreg1
208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%s.addr] GR64:%vreg1
240B		%vreg4<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg4
256B		CMP8mi %vreg4, 1, %noreg, 20, %noreg, 0, %EFLAGS<imp-def>; mem:LD1[%blockRandomised] GR64:%vreg4
272B		JE_1 <BB#47>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#47 BB#1

288B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
304B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2

320B	BB#2: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#1 BB#46 BB#37 BB#35 BB#29 BB#27 BB#21 BB#19
336B		JMP_1 <BB#3>
	    Successors according to CFG: BB#3

352B	BB#3: derived from LLVM BB %while.body.2
	    Predecessors according to CFG: BB#2 BB#9
368B		%vreg360<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg360
384B		%vreg359<def> = MOV64rm %vreg360, 1, %noreg, 0, %noreg; mem:LD8[%strm] GR64:%vreg359,%vreg360
400B		CMP32mi8 %vreg359, 1, %noreg, 32, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_out] GR64:%vreg359
416B		JNE_1 <BB#5>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#5 BB#4

432B	BB#4: derived from LLVM BB %if.then.3
	    Predecessors according to CFG: BB#3
448B		MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST1[%retval]
464B		JMP_1 <BB#80>
	    Successors according to CFG: BB#80

480B	BB#5: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#3
496B		%vreg363<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg363
512B		CMP32mi8 %vreg363, 1, %noreg, 16, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%state_out_len] GR64:%vreg363
528B		JNE_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#6

544B	BB#6: derived from LLVM BB %if.then.5
	    Predecessors according to CFG: BB#5
560B		JMP_1 <BB#10>
	    Successors according to CFG: BB#10

576B	BB#7: derived from LLVM BB %if.end.6
	    Predecessors according to CFG: BB#5
592B		%vreg435<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg435
608B		%vreg434<def> = MOV8rm %vreg435, 1, %noreg, 12, %noreg; mem:LD1[%state_out_ch] GR8:%vreg434 GR64:%vreg435
624B		%vreg432<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg432
640B		%vreg431<def> = MOV64rm %vreg432, 1, %noreg, 0, %noreg; mem:LD8[%strm7] GR64:%vreg431,%vreg432
656B		%vreg429<def> = MOV64rm %vreg431, 1, %noreg, 24, %noreg; mem:LD8[%next_out] GR64:%vreg429,%vreg431
672B		MOV8mr %vreg429, 1, %noreg, 0, %noreg, %vreg434; mem:ST1[%11] GR64:%vreg429 GR8:%vreg434
688B		%vreg425<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg425
704B		%vreg404<def> = MOV32rm %vreg425, 1, %noreg, 3184, %noreg; mem:LD4[%calculatedBlockCRC] GR32:%vreg404 GR64:%vreg425
736B		%vreg404<def,tied1> = SHL32ri %vreg404<tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg404
752B		%vreg420<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg420
768B		%vreg411<def> = MOV32rm %vreg420, 1, %noreg, 3184, %noreg; mem:LD4[%calculatedBlockCRC8] GR32:%vreg411 GR64:%vreg420
800B		%vreg411<def,tied1> = SHR32ri %vreg411<tied0>, 24, %EFLAGS<imp-def,dead>; GR32:%vreg411
816B		%vreg415<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg415
832B		%vreg413<def> = MOVZX32rm8 %vreg415, 1, %noreg, 12, %noreg; mem:LD1[%state_out_ch9] GR32:%vreg413 GR64:%vreg415
864B		%vreg411<def,tied1> = XOR32rr %vreg411<tied0>, %vreg413, %EFLAGS<imp-def,dead>; GR32:%vreg411,%vreg413
880B		%vreg408:sub_32bit<def,read-undef> = MOV32rr %vreg411; GR64_NOSP:%vreg408 GR32:%vreg411
928B		%vreg404<def,tied1> = XOR32rm %vreg404<tied0>, %noreg, 4, %vreg408, <ga:@BZ2_crc32Table>, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%arrayidx] GR32:%vreg404 GR64_NOSP:%vreg408
944B		%vreg401<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg401
960B		MOV32mr %vreg401, 1, %noreg, 3184, %noreg, %vreg404; mem:ST4[%calculatedBlockCRC11] GR64:%vreg401 GR32:%vreg404
976B		%vreg398<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg398
992B		%vreg396<def> = MOV32rm %vreg398, 1, %noreg, 16, %noreg; mem:LD4[%state_out_len12] GR32:%vreg396 GR64:%vreg398
1024B		%vreg396<def,tied1> = ADD32ri8 %vreg396<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg396
1040B		MOV32mr %vreg398, 1, %noreg, 16, %noreg, %vreg396; mem:ST4[%state_out_len12] GR64:%vreg398 GR32:%vreg396
1056B		%vreg392<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg392
1072B		%vreg391<def> = MOV64rm %vreg392, 1, %noreg, 0, %noreg; mem:LD8[%strm13] GR64:%vreg391,%vreg392
1088B		%vreg388<def> = MOV64rm %vreg391, 1, %noreg, 24, %noreg; mem:LD8[%next_out14] GR64:%vreg388,%vreg391
1120B		%vreg388<def,tied1> = ADD64ri8 %vreg388<tied0>, 1, %EFLAGS<imp-def,dead>; GR64:%vreg388
1136B		MOV64mr %vreg391, 1, %noreg, 24, %noreg, %vreg388; mem:ST8[%next_out14] GR64:%vreg391,%vreg388
1152B		%vreg384<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg384
1168B		%vreg383<def> = MOV64rm %vreg384, 1, %noreg, 0, %noreg; mem:LD8[%strm15] GR64:%vreg383,%vreg384
1184B		%vreg380<def> = MOV32rm %vreg383, 1, %noreg, 32, %noreg; mem:LD4[%avail_out16] GR32:%vreg380 GR64:%vreg383
1216B		%vreg380<def,tied1> = ADD32ri8 %vreg380<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg380
1232B		MOV32mr %vreg383, 1, %noreg, 32, %noreg, %vreg380; mem:ST4[%avail_out16] GR64:%vreg383 GR32:%vreg380
1248B		%vreg376<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg376
1264B		%vreg375<def> = MOV64rm %vreg376, 1, %noreg, 0, %noreg; mem:LD8[%strm18] GR64:%vreg375,%vreg376
1280B		%vreg372<def> = MOV32rm %vreg375, 1, %noreg, 36, %noreg; mem:LD4[%total_out_lo32] GR32:%vreg372 GR64:%vreg375
1312B		%vreg372<def,tied1> = ADD32ri8 %vreg372<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg372
1328B		MOV32mr %vreg375, 1, %noreg, 36, %noreg, %vreg372; mem:ST4[%total_out_lo32] GR64:%vreg375 GR32:%vreg372
1344B		%vreg368<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg368
1360B		%vreg367<def> = MOV64rm %vreg368, 1, %noreg, 0, %noreg; mem:LD8[%strm19] GR64:%vreg367,%vreg368
1376B		CMP32mi8 %vreg367, 1, %noreg, 36, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%total_out_lo3220] GR64:%vreg367
1392B		JNE_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#8

1408B	BB#8: derived from LLVM BB %if.then.23
	    Predecessors according to CFG: BB#7
1424B		%vreg443<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg443
1440B		%vreg442<def> = MOV64rm %vreg443, 1, %noreg, 0, %noreg; mem:LD8[%strm24] GR64:%vreg442,%vreg443
1456B		%vreg439<def> = MOV32rm %vreg442, 1, %noreg, 40, %noreg; mem:LD4[%total_out_hi32] GR32:%vreg439 GR64:%vreg442
1488B		%vreg439<def,tied1> = ADD32ri8 %vreg439<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg439
1504B		MOV32mr %vreg442, 1, %noreg, 40, %noreg, %vreg439; mem:ST4[%total_out_hi32] GR64:%vreg442 GR32:%vreg439
	    Successors according to CFG: BB#9

1520B	BB#9: derived from LLVM BB %if.end.26
	    Predecessors according to CFG: BB#7 BB#8
1536B		JMP_1 <BB#3>
	    Successors according to CFG: BB#3

1552B	BB#10: derived from LLVM BB %while.end
	    Predecessors according to CFG: BB#6
1568B		%vreg453<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg453
1584B		%vreg452<def> = MOV32rm %vreg453, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used] GR32:%vreg452 GR64:%vreg453
1600B		%vreg450<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg450
1616B		%vreg447<def> = MOV32rm %vreg450, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock] GR32:%vreg447 GR64:%vreg450
1648B		%vreg447<def,tied1> = ADD32ri8 %vreg447<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg447
1664B		CMP32rr %vreg452, %vreg447, %EFLAGS<imp-def>; GR32:%vreg452,%vreg447
1680B		JNE_1 <BB#12>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#12 BB#11

1696B	BB#11: derived from LLVM BB %if.then.29
	    Predecessors according to CFG: BB#10
1712B		MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST1[%retval]
1728B		JMP_1 <BB#80>
	    Successors according to CFG: BB#80

1744B	BB#12: derived from LLVM BB %if.end.30
	    Predecessors according to CFG: BB#10
1760B		%vreg463<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg463
1776B		%vreg462<def> = MOV32rm %vreg463, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used31] GR32:%vreg462 GR64:%vreg463
1792B		%vreg460<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg460
1808B		%vreg457<def> = MOV32rm %vreg460, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock32] GR32:%vreg457 GR64:%vreg460
1840B		%vreg457<def,tied1> = ADD32ri8 %vreg457<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg457
1856B		CMP32rr %vreg462, %vreg457, %EFLAGS<imp-def>; GR32:%vreg462,%vreg457
1872B		JLE_1 <BB#14>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#14 BB#13

1888B	BB#13: derived from LLVM BB %if.then.36
	    Predecessors according to CFG: BB#12
1904B		MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 1; mem:ST1[%retval]
1920B		JMP_1 <BB#80>
	    Successors according to CFG: BB#80

1936B	BB#14: derived from LLVM BB %if.end.37
	    Predecessors according to CFG: BB#12
1952B		%vreg504<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg504
1968B		MOV32mi %vreg504, 1, %noreg, 16, %noreg, 1; mem:ST4[%state_out_len38] GR64:%vreg504
1984B		%vreg502<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg502
2000B		%vreg501<def> = MOV32rm %vreg502, 1, %noreg, 64, %noreg; mem:LD4[%k0] GR32:%vreg501 GR64:%vreg502
2032B		%vreg497<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg497
2048B		MOV8mr %vreg497, 1, %noreg, 12, %noreg, %vreg501:sub_8bit; mem:ST1[%state_out_ch40] GR64:%vreg497 GR32:%vreg501
2064B		%vreg494<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg494
2080B		%vreg492:sub_32bit<def,read-undef> = MOV32rm %vreg494, 1, %noreg, 60, %noreg; mem:LD4[%tPos] GR64_NOSP:%vreg492 GR64:%vreg494
2112B		%vreg489<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg489
2128B		%vreg488<def> = MOV64rm %vreg489, 1, %noreg, 3152, %noreg; mem:LD8[%tt] GR64:%vreg488,%vreg489
2144B		%vreg486<def> = MOV32rm %vreg488, 4, %vreg492, 0, %noreg; mem:LD4[%arrayidx42] GR32:%vreg486 GR64:%vreg488 GR64_NOSP:%vreg492
2160B		%vreg483<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg483
2176B		MOV32mr %vreg483, 1, %noreg, 60, %noreg, %vreg486; mem:ST4[%tPos43] GR64:%vreg483 GR32:%vreg486
2192B		%vreg480<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg480
2208B		%vreg477<def> = MOV32rm %vreg480, 1, %noreg, 60, %noreg; mem:LD4[%tPos44] GR32:%vreg477 GR64:%vreg480
2240B		%vreg477<def,tied1> = AND32ri %vreg477<tied0>, 255, %EFLAGS<imp-def,dead>; GR32:%vreg477
2272B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg477:sub_8bit; mem:ST1[%k1] GR32:%vreg477
2288B		%vreg472<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg472
2304B		%vreg470<def> = MOV32rm %vreg472, 1, %noreg, 60, %noreg; mem:LD4[%tPos46] GR32:%vreg470 GR64:%vreg472
2336B		%vreg470<def,tied1> = SHR32ri %vreg470<tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg470
2352B		MOV32mr %vreg472, 1, %noreg, 60, %noreg, %vreg470; mem:ST4[%tPos46] GR64:%vreg472 GR32:%vreg470
2368B		%vreg466<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg466
2384B		CMP32mi8 %vreg466, 1, %noreg, 24, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%rNToGo] GR64:%vreg466
2400B		JNE_1 <BB#18>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#18 BB#15

2416B	BB#15: derived from LLVM BB %if.then.50
	    Predecessors according to CFG: BB#14
2432B		%vreg522<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg522
2448B		%vreg520<def> = MOVSX64rm32 %vreg522, 1, %noreg, 28, %noreg; mem:LD4[%rTPos] GR64_NOSP:%vreg520 GR64:%vreg522
2464B		%vreg518<def> = MOV32rm %noreg, 4, %vreg520, <ga:@BZ2_rNums>, %noreg; mem:LD4[%arrayidx52] GR32:%vreg518 GR64_NOSP:%vreg520
2480B		%vreg516<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg516
2496B		MOV32mr %vreg516, 1, %noreg, 24, %noreg, %vreg518; mem:ST4[%rNToGo53] GR64:%vreg516 GR32:%vreg518
2512B		%vreg513<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg513
2528B		%vreg511<def> = MOV32rm %vreg513, 1, %noreg, 28, %noreg; mem:LD4[%rTPos54] GR32:%vreg511 GR64:%vreg513
2560B		%vreg511<def,tied1> = ADD32ri8 %vreg511<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg511
2576B		MOV32mr %vreg513, 1, %noreg, 28, %noreg, %vreg511; mem:ST4[%rTPos54] GR64:%vreg513 GR32:%vreg511
2592B		%vreg507<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg507
2608B		CMP32mi %vreg507, 1, %noreg, 28, %noreg, 512, %EFLAGS<imp-def>; mem:LD4[%rTPos56] GR64:%vreg507
2624B		JNE_1 <BB#17>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#17 BB#16

2640B	BB#16: derived from LLVM BB %if.then.59
	    Predecessors according to CFG: BB#15
2656B		%vreg524<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg524
2672B		MOV32mi %vreg524, 1, %noreg, 28, %noreg, 0; mem:ST4[%rTPos60] GR64:%vreg524
	    Successors according to CFG: BB#17

2688B	BB#17: derived from LLVM BB %if.end.61
	    Predecessors according to CFG: BB#15 BB#16
2704B		JMP_1 <BB#18>
	    Successors according to CFG: BB#18

2720B	BB#18: derived from LLVM BB %if.end.62
	    Predecessors according to CFG: BB#14 BB#17
2736B		%vreg552<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg552
2752B		%vreg551<def> = MOV32ri 1; GR32:%vreg551
2768B		%vreg560<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg560
2784B		%vreg558<def> = MOV32rm %vreg560, 1, %noreg, 24, %noreg; mem:LD4[%rNToGo63] GR32:%vreg558 GR64:%vreg560
2816B		%vreg558<def,tied1> = ADD32ri8 %vreg558<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg558
2832B		MOV32mr %vreg560, 1, %noreg, 24, %noreg, %vreg558; mem:ST4[%rNToGo63] GR64:%vreg560 GR32:%vreg558
2848B		%vreg554<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg554
2864B		CMP32mi8 %vreg554, 1, %noreg, 24, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%rNToGo65] GR64:%vreg554
2896B		%vreg552<def,tied1> = CMOVE32rr %vreg552<tied0>, %vreg551, %EFLAGS<imp-use,kill>; GR32:%vreg552,%vreg551
2912B		%vreg546<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg546
2944B		%vreg546<def,tied1> = XOR32rr %vreg546<tied0>, %vreg552, %EFLAGS<imp-def,dead>; GR32:%vreg546,%vreg552
2976B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg546:sub_8bit; mem:ST1[%k1] GR32:%vreg546
2992B		%vreg540<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg540
3008B		%vreg538<def> = MOV32rm %vreg540, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used71] GR32:%vreg538 GR64:%vreg540
3040B		%vreg538<def,tied1> = ADD32ri8 %vreg538<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg538
3056B		MOV32mr %vreg540, 1, %noreg, 1092, %noreg, %vreg538; mem:ST4[%nblock_used71] GR64:%vreg540 GR32:%vreg538
3072B		%vreg534<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg534
3088B		%vreg533<def> = MOV32rm %vreg534, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used73] GR32:%vreg533 GR64:%vreg534
3104B		%vreg531<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg531
3120B		%vreg528<def> = MOV32rm %vreg531, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock74] GR32:%vreg528 GR64:%vreg531
3152B		%vreg528<def,tied1> = ADD32ri8 %vreg528<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg528
3168B		CMP32rr %vreg533, %vreg528, %EFLAGS<imp-def>; GR32:%vreg533,%vreg528
3184B		JNE_1 <BB#20>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#20 BB#19

3200B	BB#19: derived from LLVM BB %if.then.78
	    Predecessors according to CFG: BB#18
3216B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2

3232B	BB#20: derived from LLVM BB %if.end.79
	    Predecessors according to CFG: BB#18
3248B		%vreg566<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg566
3264B		%vreg564<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg564
3280B		CMP32rm %vreg566, %vreg564, 1, %noreg, 64, %noreg, %EFLAGS<imp-def>; mem:LD4[%k081] GR32:%vreg566 GR64:%vreg564
3296B		JE_1 <BB#22>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#22 BB#21

3312B	BB#21: derived from LLVM BB %if.then.84
	    Predecessors according to CFG: BB#20
3328B		%vreg934<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg934
3344B		%vreg932<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg932
3360B		MOV32mr %vreg932, 1, %noreg, 64, %noreg, %vreg934; mem:ST4[%k086] GR64:%vreg932 GR32:%vreg934
3376B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2

3392B	BB#22: derived from LLVM BB %if.end.87
	    Predecessors according to CFG: BB#20
3408B		%vreg599<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg599
3424B		MOV32mi %vreg599, 1, %noreg, 16, %noreg, 2; mem:ST4[%state_out_len88] GR64:%vreg599
3440B		%vreg597<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg597
3456B		%vreg595:sub_32bit<def,read-undef> = MOV32rm %vreg597, 1, %noreg, 60, %noreg; mem:LD4[%tPos89] GR64_NOSP:%vreg595 GR64:%vreg597
3488B		%vreg592<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg592
3504B		%vreg591<def> = MOV64rm %vreg592, 1, %noreg, 3152, %noreg; mem:LD8[%tt91] GR64:%vreg591,%vreg592
3520B		%vreg589<def> = MOV32rm %vreg591, 4, %vreg595, 0, %noreg; mem:LD4[%arrayidx92] GR32:%vreg589 GR64:%vreg591 GR64_NOSP:%vreg595
3536B		%vreg586<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg586
3552B		MOV32mr %vreg586, 1, %noreg, 60, %noreg, %vreg589; mem:ST4[%tPos93] GR64:%vreg586 GR32:%vreg589
3568B		%vreg583<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg583
3584B		%vreg580<def> = MOV32rm %vreg583, 1, %noreg, 60, %noreg; mem:LD4[%tPos94] GR32:%vreg580 GR64:%vreg583
3616B		%vreg580<def,tied1> = AND32ri %vreg580<tied0>, 255, %EFLAGS<imp-def,dead>; GR32:%vreg580
3648B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg580:sub_8bit; mem:ST1[%k1] GR32:%vreg580
3664B		%vreg575<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg575
3680B		%vreg573<def> = MOV32rm %vreg575, 1, %noreg, 60, %noreg; mem:LD4[%tPos97] GR32:%vreg573 GR64:%vreg575
3712B		%vreg573<def,tied1> = SHR32ri %vreg573<tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg573
3728B		MOV32mr %vreg575, 1, %noreg, 60, %noreg, %vreg573; mem:ST4[%tPos97] GR64:%vreg575 GR32:%vreg573
3744B		%vreg569<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg569
3760B		CMP32mi8 %vreg569, 1, %noreg, 24, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%rNToGo99] GR64:%vreg569
3776B		JNE_1 <BB#26>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#26 BB#23

3792B	BB#23: derived from LLVM BB %if.then.102
	    Predecessors according to CFG: BB#22
3808B		%vreg617<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg617
3824B		%vreg615<def> = MOVSX64rm32 %vreg617, 1, %noreg, 28, %noreg; mem:LD4[%rTPos103] GR64_NOSP:%vreg615 GR64:%vreg617
3840B		%vreg613<def> = MOV32rm %noreg, 4, %vreg615, <ga:@BZ2_rNums>, %noreg; mem:LD4[%arrayidx105] GR32:%vreg613 GR64_NOSP:%vreg615
3856B		%vreg611<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg611
3872B		MOV32mr %vreg611, 1, %noreg, 24, %noreg, %vreg613; mem:ST4[%rNToGo106] GR64:%vreg611 GR32:%vreg613
3888B		%vreg608<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg608
3904B		%vreg606<def> = MOV32rm %vreg608, 1, %noreg, 28, %noreg; mem:LD4[%rTPos107] GR32:%vreg606 GR64:%vreg608
3936B		%vreg606<def,tied1> = ADD32ri8 %vreg606<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg606
3952B		MOV32mr %vreg608, 1, %noreg, 28, %noreg, %vreg606; mem:ST4[%rTPos107] GR64:%vreg608 GR32:%vreg606
3968B		%vreg602<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg602
3984B		CMP32mi %vreg602, 1, %noreg, 28, %noreg, 512, %EFLAGS<imp-def>; mem:LD4[%rTPos109] GR64:%vreg602
4000B		JNE_1 <BB#25>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#25 BB#24

4016B	BB#24: derived from LLVM BB %if.then.112
	    Predecessors according to CFG: BB#23
4032B		%vreg619<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg619
4048B		MOV32mi %vreg619, 1, %noreg, 28, %noreg, 0; mem:ST4[%rTPos113] GR64:%vreg619
	    Successors according to CFG: BB#25

4064B	BB#25: derived from LLVM BB %if.end.114
	    Predecessors according to CFG: BB#23 BB#24
4080B		JMP_1 <BB#26>
	    Successors according to CFG: BB#26

4096B	BB#26: derived from LLVM BB %if.end.115
	    Predecessors according to CFG: BB#22 BB#25
4112B		%vreg647<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg647
4128B		%vreg646<def> = MOV32ri 1; GR32:%vreg646
4144B		%vreg655<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg655
4160B		%vreg653<def> = MOV32rm %vreg655, 1, %noreg, 24, %noreg; mem:LD4[%rNToGo116] GR32:%vreg653 GR64:%vreg655
4192B		%vreg653<def,tied1> = ADD32ri8 %vreg653<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg653
4208B		MOV32mr %vreg655, 1, %noreg, 24, %noreg, %vreg653; mem:ST4[%rNToGo116] GR64:%vreg655 GR32:%vreg653
4224B		%vreg649<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg649
4240B		CMP32mi8 %vreg649, 1, %noreg, 24, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%rNToGo118] GR64:%vreg649
4272B		%vreg647<def,tied1> = CMOVE32rr %vreg647<tied0>, %vreg646, %EFLAGS<imp-use,kill>; GR32:%vreg647,%vreg646
4288B		%vreg641<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg641
4320B		%vreg641<def,tied1> = XOR32rr %vreg641<tied0>, %vreg647, %EFLAGS<imp-def,dead>; GR32:%vreg641,%vreg647
4352B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg641:sub_8bit; mem:ST1[%k1] GR32:%vreg641
4368B		%vreg635<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg635
4384B		%vreg633<def> = MOV32rm %vreg635, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used125] GR32:%vreg633 GR64:%vreg635
4416B		%vreg633<def,tied1> = ADD32ri8 %vreg633<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg633
4432B		MOV32mr %vreg635, 1, %noreg, 1092, %noreg, %vreg633; mem:ST4[%nblock_used125] GR64:%vreg635 GR32:%vreg633
4448B		%vreg629<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg629
4464B		%vreg628<def> = MOV32rm %vreg629, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used127] GR32:%vreg628 GR64:%vreg629
4480B		%vreg626<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg626
4496B		%vreg623<def> = MOV32rm %vreg626, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock128] GR32:%vreg623 GR64:%vreg626
4528B		%vreg623<def,tied1> = ADD32ri8 %vreg623<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg623
4544B		CMP32rr %vreg628, %vreg623, %EFLAGS<imp-def>; GR32:%vreg628,%vreg623
4560B		JNE_1 <BB#28>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#28 BB#27

4576B	BB#27: derived from LLVM BB %if.then.132
	    Predecessors according to CFG: BB#26
4592B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2

4608B	BB#28: derived from LLVM BB %if.end.133
	    Predecessors according to CFG: BB#26
4624B		%vreg661<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg661
4640B		%vreg659<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg659
4656B		CMP32rm %vreg661, %vreg659, 1, %noreg, 64, %noreg, %EFLAGS<imp-def>; mem:LD4[%k0135] GR32:%vreg661 GR64:%vreg659
4672B		JE_1 <BB#30>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#30 BB#29

4688B	BB#29: derived from LLVM BB %if.then.138
	    Predecessors according to CFG: BB#28
4704B		%vreg929<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg929
4720B		%vreg927<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg927
4736B		MOV32mr %vreg927, 1, %noreg, 64, %noreg, %vreg929; mem:ST4[%k0140] GR64:%vreg927 GR32:%vreg929
4752B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2

4768B	BB#30: derived from LLVM BB %if.end.141
	    Predecessors according to CFG: BB#28
4784B		%vreg694<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg694
4800B		MOV32mi %vreg694, 1, %noreg, 16, %noreg, 3; mem:ST4[%state_out_len142] GR64:%vreg694
4816B		%vreg692<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg692
4832B		%vreg690:sub_32bit<def,read-undef> = MOV32rm %vreg692, 1, %noreg, 60, %noreg; mem:LD4[%tPos143] GR64_NOSP:%vreg690 GR64:%vreg692
4864B		%vreg687<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg687
4880B		%vreg686<def> = MOV64rm %vreg687, 1, %noreg, 3152, %noreg; mem:LD8[%tt145] GR64:%vreg686,%vreg687
4896B		%vreg684<def> = MOV32rm %vreg686, 4, %vreg690, 0, %noreg; mem:LD4[%arrayidx146] GR32:%vreg684 GR64:%vreg686 GR64_NOSP:%vreg690
4912B		%vreg681<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg681
4928B		MOV32mr %vreg681, 1, %noreg, 60, %noreg, %vreg684; mem:ST4[%tPos147] GR64:%vreg681 GR32:%vreg684
4944B		%vreg678<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg678
4960B		%vreg675<def> = MOV32rm %vreg678, 1, %noreg, 60, %noreg; mem:LD4[%tPos148] GR32:%vreg675 GR64:%vreg678
4992B		%vreg675<def,tied1> = AND32ri %vreg675<tied0>, 255, %EFLAGS<imp-def,dead>; GR32:%vreg675
5024B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg675:sub_8bit; mem:ST1[%k1] GR32:%vreg675
5040B		%vreg670<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg670
5056B		%vreg668<def> = MOV32rm %vreg670, 1, %noreg, 60, %noreg; mem:LD4[%tPos151] GR32:%vreg668 GR64:%vreg670
5088B		%vreg668<def,tied1> = SHR32ri %vreg668<tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg668
5104B		MOV32mr %vreg670, 1, %noreg, 60, %noreg, %vreg668; mem:ST4[%tPos151] GR64:%vreg670 GR32:%vreg668
5120B		%vreg664<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg664
5136B		CMP32mi8 %vreg664, 1, %noreg, 24, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%rNToGo153] GR64:%vreg664
5152B		JNE_1 <BB#34>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#34 BB#31

5168B	BB#31: derived from LLVM BB %if.then.156
	    Predecessors according to CFG: BB#30
5184B		%vreg712<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg712
5200B		%vreg710<def> = MOVSX64rm32 %vreg712, 1, %noreg, 28, %noreg; mem:LD4[%rTPos157] GR64_NOSP:%vreg710 GR64:%vreg712
5216B		%vreg708<def> = MOV32rm %noreg, 4, %vreg710, <ga:@BZ2_rNums>, %noreg; mem:LD4[%arrayidx159] GR32:%vreg708 GR64_NOSP:%vreg710
5232B		%vreg706<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg706
5248B		MOV32mr %vreg706, 1, %noreg, 24, %noreg, %vreg708; mem:ST4[%rNToGo160] GR64:%vreg706 GR32:%vreg708
5264B		%vreg703<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg703
5280B		%vreg701<def> = MOV32rm %vreg703, 1, %noreg, 28, %noreg; mem:LD4[%rTPos161] GR32:%vreg701 GR64:%vreg703
5312B		%vreg701<def,tied1> = ADD32ri8 %vreg701<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg701
5328B		MOV32mr %vreg703, 1, %noreg, 28, %noreg, %vreg701; mem:ST4[%rTPos161] GR64:%vreg703 GR32:%vreg701
5344B		%vreg697<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg697
5360B		CMP32mi %vreg697, 1, %noreg, 28, %noreg, 512, %EFLAGS<imp-def>; mem:LD4[%rTPos163] GR64:%vreg697
5376B		JNE_1 <BB#33>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#33 BB#32

5392B	BB#32: derived from LLVM BB %if.then.166
	    Predecessors according to CFG: BB#31
5408B		%vreg714<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg714
5424B		MOV32mi %vreg714, 1, %noreg, 28, %noreg, 0; mem:ST4[%rTPos167] GR64:%vreg714
	    Successors according to CFG: BB#33

5440B	BB#33: derived from LLVM BB %if.end.168
	    Predecessors according to CFG: BB#31 BB#32
5456B		JMP_1 <BB#34>
	    Successors according to CFG: BB#34

5472B	BB#34: derived from LLVM BB %if.end.169
	    Predecessors according to CFG: BB#30 BB#33
5488B		%vreg742<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg742
5504B		%vreg741<def> = MOV32ri 1; GR32:%vreg741
5520B		%vreg750<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg750
5536B		%vreg748<def> = MOV32rm %vreg750, 1, %noreg, 24, %noreg; mem:LD4[%rNToGo170] GR32:%vreg748 GR64:%vreg750
5568B		%vreg748<def,tied1> = ADD32ri8 %vreg748<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg748
5584B		MOV32mr %vreg750, 1, %noreg, 24, %noreg, %vreg748; mem:ST4[%rNToGo170] GR64:%vreg750 GR32:%vreg748
5600B		%vreg744<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg744
5616B		CMP32mi8 %vreg744, 1, %noreg, 24, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%rNToGo172] GR64:%vreg744
5648B		%vreg742<def,tied1> = CMOVE32rr %vreg742<tied0>, %vreg741, %EFLAGS<imp-use,kill>; GR32:%vreg742,%vreg741
5664B		%vreg736<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg736
5696B		%vreg736<def,tied1> = XOR32rr %vreg736<tied0>, %vreg742, %EFLAGS<imp-def,dead>; GR32:%vreg736,%vreg742
5728B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg736:sub_8bit; mem:ST1[%k1] GR32:%vreg736
5744B		%vreg730<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg730
5760B		%vreg728<def> = MOV32rm %vreg730, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used179] GR32:%vreg728 GR64:%vreg730
5792B		%vreg728<def,tied1> = ADD32ri8 %vreg728<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg728
5808B		MOV32mr %vreg730, 1, %noreg, 1092, %noreg, %vreg728; mem:ST4[%nblock_used179] GR64:%vreg730 GR32:%vreg728
5824B		%vreg724<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg724
5840B		%vreg723<def> = MOV32rm %vreg724, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used181] GR32:%vreg723 GR64:%vreg724
5856B		%vreg721<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg721
5872B		%vreg718<def> = MOV32rm %vreg721, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock182] GR32:%vreg718 GR64:%vreg721
5904B		%vreg718<def,tied1> = ADD32ri8 %vreg718<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg718
5920B		CMP32rr %vreg723, %vreg718, %EFLAGS<imp-def>; GR32:%vreg723,%vreg718
5936B		JNE_1 <BB#36>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#36 BB#35

5952B	BB#35: derived from LLVM BB %if.then.186
	    Predecessors according to CFG: BB#34
5968B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2

5984B	BB#36: derived from LLVM BB %if.end.187
	    Predecessors according to CFG: BB#34
6000B		%vreg756<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg756
6016B		%vreg754<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg754
6032B		CMP32rm %vreg756, %vreg754, 1, %noreg, 64, %noreg, %EFLAGS<imp-def>; mem:LD4[%k0189] GR32:%vreg756 GR64:%vreg754
6048B		JE_1 <BB#38>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#38 BB#37

6064B	BB#37: derived from LLVM BB %if.then.192
	    Predecessors according to CFG: BB#36
6080B		%vreg924<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg924
6096B		%vreg922<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg922
6112B		MOV32mr %vreg922, 1, %noreg, 64, %noreg, %vreg924; mem:ST4[%k0194] GR64:%vreg922 GR32:%vreg924
6128B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2

6144B	BB#38: derived from LLVM BB %if.end.195
	    Predecessors according to CFG: BB#36
6160B		%vreg787<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg787
6176B		%vreg785:sub_32bit<def,read-undef> = MOV32rm %vreg787, 1, %noreg, 60, %noreg; mem:LD4[%tPos196] GR64_NOSP:%vreg785 GR64:%vreg787
6208B		%vreg782<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg782
6224B		%vreg781<def> = MOV64rm %vreg782, 1, %noreg, 3152, %noreg; mem:LD8[%tt198] GR64:%vreg781,%vreg782
6240B		%vreg779<def> = MOV32rm %vreg781, 4, %vreg785, 0, %noreg; mem:LD4[%arrayidx199] GR32:%vreg779 GR64:%vreg781 GR64_NOSP:%vreg785
6256B		%vreg776<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg776
6272B		MOV32mr %vreg776, 1, %noreg, 60, %noreg, %vreg779; mem:ST4[%tPos200] GR64:%vreg776 GR32:%vreg779
6288B		%vreg773<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg773
6304B		%vreg770<def> = MOV32rm %vreg773, 1, %noreg, 60, %noreg; mem:LD4[%tPos201] GR32:%vreg770 GR64:%vreg773
6336B		%vreg770<def,tied1> = AND32ri %vreg770<tied0>, 255, %EFLAGS<imp-def,dead>; GR32:%vreg770
6368B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg770:sub_8bit; mem:ST1[%k1] GR32:%vreg770
6384B		%vreg765<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg765
6400B		%vreg763<def> = MOV32rm %vreg765, 1, %noreg, 60, %noreg; mem:LD4[%tPos204] GR32:%vreg763 GR64:%vreg765
6432B		%vreg763<def,tied1> = SHR32ri %vreg763<tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg763
6448B		MOV32mr %vreg765, 1, %noreg, 60, %noreg, %vreg763; mem:ST4[%tPos204] GR64:%vreg765 GR32:%vreg763
6464B		%vreg759<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg759
6480B		CMP32mi8 %vreg759, 1, %noreg, 24, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%rNToGo206] GR64:%vreg759
6496B		JNE_1 <BB#42>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#42 BB#39

6512B	BB#39: derived from LLVM BB %if.then.209
	    Predecessors according to CFG: BB#38
6528B		%vreg805<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg805
6544B		%vreg803<def> = MOVSX64rm32 %vreg805, 1, %noreg, 28, %noreg; mem:LD4[%rTPos210] GR64_NOSP:%vreg803 GR64:%vreg805
6560B		%vreg801<def> = MOV32rm %noreg, 4, %vreg803, <ga:@BZ2_rNums>, %noreg; mem:LD4[%arrayidx212] GR32:%vreg801 GR64_NOSP:%vreg803
6576B		%vreg799<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg799
6592B		MOV32mr %vreg799, 1, %noreg, 24, %noreg, %vreg801; mem:ST4[%rNToGo213] GR64:%vreg799 GR32:%vreg801
6608B		%vreg796<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg796
6624B		%vreg794<def> = MOV32rm %vreg796, 1, %noreg, 28, %noreg; mem:LD4[%rTPos214] GR32:%vreg794 GR64:%vreg796
6656B		%vreg794<def,tied1> = ADD32ri8 %vreg794<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg794
6672B		MOV32mr %vreg796, 1, %noreg, 28, %noreg, %vreg794; mem:ST4[%rTPos214] GR64:%vreg796 GR32:%vreg794
6688B		%vreg790<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg790
6704B		CMP32mi %vreg790, 1, %noreg, 28, %noreg, 512, %EFLAGS<imp-def>; mem:LD4[%rTPos216] GR64:%vreg790
6720B		JNE_1 <BB#41>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#41 BB#40

6736B	BB#40: derived from LLVM BB %if.then.219
	    Predecessors according to CFG: BB#39
6752B		%vreg807<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg807
6768B		MOV32mi %vreg807, 1, %noreg, 28, %noreg, 0; mem:ST4[%rTPos220] GR64:%vreg807
	    Successors according to CFG: BB#41

6784B	BB#41: derived from LLVM BB %if.end.221
	    Predecessors according to CFG: BB#39 BB#40
6800B		JMP_1 <BB#42>
	    Successors according to CFG: BB#42

6816B	BB#42: derived from LLVM BB %if.end.222
	    Predecessors according to CFG: BB#38 BB#41
6832B		%vreg867<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg867
6848B		%vreg866<def> = MOV32ri 1; GR32:%vreg866
6864B		%vreg875<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg875
6880B		%vreg873<def> = MOV32rm %vreg875, 1, %noreg, 24, %noreg; mem:LD4[%rNToGo223] GR32:%vreg873 GR64:%vreg875
6912B		%vreg873<def,tied1> = ADD32ri8 %vreg873<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg873
6928B		MOV32mr %vreg875, 1, %noreg, 24, %noreg, %vreg873; mem:ST4[%rNToGo223] GR64:%vreg875 GR32:%vreg873
6944B		%vreg869<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg869
6960B		CMP32mi8 %vreg869, 1, %noreg, 24, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%rNToGo225] GR64:%vreg869
6992B		%vreg867<def,tied1> = CMOVE32rr %vreg867<tied0>, %vreg866, %EFLAGS<imp-use,kill>; GR32:%vreg867,%vreg866
7008B		%vreg861<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg861
7040B		%vreg861<def,tied1> = XOR32rr %vreg861<tied0>, %vreg867, %EFLAGS<imp-def,dead>; GR32:%vreg861,%vreg867
7072B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg861:sub_8bit; mem:ST1[%k1] GR32:%vreg861
7088B		%vreg855<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg855
7104B		%vreg853<def> = MOV32rm %vreg855, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used232] GR32:%vreg853 GR64:%vreg855
7136B		%vreg853<def,tied1> = ADD32ri8 %vreg853<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg853
7152B		MOV32mr %vreg855, 1, %noreg, 1092, %noreg, %vreg853; mem:ST4[%nblock_used232] GR64:%vreg855 GR32:%vreg853
7168B		%vreg847<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg847
7200B		%vreg847<def,tied1> = ADD32ri8 %vreg847<tied0>, 4, %EFLAGS<imp-def,dead>; GR32:%vreg847
7216B		%vreg845<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg845
7232B		MOV32mr %vreg845, 1, %noreg, 16, %noreg, %vreg847; mem:ST4[%state_out_len236] GR64:%vreg845 GR32:%vreg847
7248B		%vreg842<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg842
7264B		%vreg840:sub_32bit<def,read-undef> = MOV32rm %vreg842, 1, %noreg, 60, %noreg; mem:LD4[%tPos237] GR64_NOSP:%vreg840 GR64:%vreg842
7296B		%vreg837<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg837
7312B		%vreg836<def> = MOV64rm %vreg837, 1, %noreg, 3152, %noreg; mem:LD8[%tt239] GR64:%vreg836,%vreg837
7328B		%vreg834<def> = MOV32rm %vreg836, 4, %vreg840, 0, %noreg; mem:LD4[%arrayidx240] GR32:%vreg834 GR64:%vreg836 GR64_NOSP:%vreg840
7344B		%vreg831<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg831
7360B		MOV32mr %vreg831, 1, %noreg, 60, %noreg, %vreg834; mem:ST4[%tPos241] GR64:%vreg831 GR32:%vreg834
7376B		%vreg828<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg828
7392B		%vreg825<def> = MOV32rm %vreg828, 1, %noreg, 60, %noreg; mem:LD4[%tPos242] GR32:%vreg825 GR64:%vreg828
7424B		%vreg825<def,tied1> = AND32ri %vreg825<tied0>, 255, %EFLAGS<imp-def,dead>; GR32:%vreg825
7456B		%vreg821<def> = MOVZX32rr8 %vreg825:sub_8bit; GR32:%vreg821,%vreg825
7472B		%vreg819<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg819
7488B		MOV32mr %vreg819, 1, %noreg, 64, %noreg, %vreg821; mem:ST4[%k0246] GR64:%vreg819 GR32:%vreg821
7504B		%vreg816<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg816
7520B		%vreg814<def> = MOV32rm %vreg816, 1, %noreg, 60, %noreg; mem:LD4[%tPos247] GR32:%vreg814 GR64:%vreg816
7552B		%vreg814<def,tied1> = SHR32ri %vreg814<tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg814
7568B		MOV32mr %vreg816, 1, %noreg, 60, %noreg, %vreg814; mem:ST4[%tPos247] GR64:%vreg816 GR32:%vreg814
7584B		%vreg810<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg810
7600B		CMP32mi8 %vreg810, 1, %noreg, 24, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%rNToGo249] GR64:%vreg810
7616B		JNE_1 <BB#46>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#46 BB#43

7632B	BB#43: derived from LLVM BB %if.then.252
	    Predecessors according to CFG: BB#42
7648B		%vreg893<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg893
7664B		%vreg891<def> = MOVSX64rm32 %vreg893, 1, %noreg, 28, %noreg; mem:LD4[%rTPos253] GR64_NOSP:%vreg891 GR64:%vreg893
7680B		%vreg889<def> = MOV32rm %noreg, 4, %vreg891, <ga:@BZ2_rNums>, %noreg; mem:LD4[%arrayidx255] GR32:%vreg889 GR64_NOSP:%vreg891
7696B		%vreg887<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg887
7712B		MOV32mr %vreg887, 1, %noreg, 24, %noreg, %vreg889; mem:ST4[%rNToGo256] GR64:%vreg887 GR32:%vreg889
7728B		%vreg884<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg884
7744B		%vreg882<def> = MOV32rm %vreg884, 1, %noreg, 28, %noreg; mem:LD4[%rTPos257] GR32:%vreg882 GR64:%vreg884
7776B		%vreg882<def,tied1> = ADD32ri8 %vreg882<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg882
7792B		MOV32mr %vreg884, 1, %noreg, 28, %noreg, %vreg882; mem:ST4[%rTPos257] GR64:%vreg884 GR32:%vreg882
7808B		%vreg878<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg878
7824B		CMP32mi %vreg878, 1, %noreg, 28, %noreg, 512, %EFLAGS<imp-def>; mem:LD4[%rTPos259] GR64:%vreg878
7840B		JNE_1 <BB#45>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#45 BB#44

7856B	BB#44: derived from LLVM BB %if.then.262
	    Predecessors according to CFG: BB#43
7872B		%vreg895<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg895
7888B		MOV32mi %vreg895, 1, %noreg, 28, %noreg, 0; mem:ST4[%rTPos263] GR64:%vreg895
	    Successors according to CFG: BB#45

7904B	BB#45: derived from LLVM BB %if.end.264
	    Predecessors according to CFG: BB#43 BB#44
7920B		JMP_1 <BB#46>
	    Successors according to CFG: BB#46

7936B	BB#46: derived from LLVM BB %if.end.265
	    Predecessors according to CFG: BB#42 BB#45
7952B		%vreg906<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg906
7968B		%vreg910<def> = MOV32ri 1; GR32:%vreg910
7984B		%vreg919<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg919
8000B		%vreg917<def> = MOV32rm %vreg919, 1, %noreg, 24, %noreg; mem:LD4[%rNToGo266] GR32:%vreg917 GR64:%vreg919
8032B		%vreg917<def,tied1> = ADD32ri8 %vreg917<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg917
8048B		MOV32mr %vreg919, 1, %noreg, 24, %noreg, %vreg917; mem:ST4[%rNToGo266] GR64:%vreg919 GR32:%vreg917
8064B		%vreg913<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg913
8080B		CMP32mi8 %vreg913, 1, %noreg, 24, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%rNToGo268] GR64:%vreg913
8112B		%vreg906<def,tied1> = CMOVE32rr %vreg906<tied0>, %vreg910, %EFLAGS<imp-use,kill>; GR32:%vreg906,%vreg910
8128B		%vreg907<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg907
8160B		%vreg906<def,tied1> = XOR32rm %vreg906<tied0>, %vreg907, 1, %noreg, 64, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%k0272] GR32:%vreg906 GR64:%vreg907
8176B		MOV32mr %vreg907, 1, %noreg, 64, %noreg, %vreg906; mem:ST4[%k0272] GR64:%vreg907 GR32:%vreg906
8192B		%vreg901<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg901
8208B		%vreg899<def> = MOV32rm %vreg901, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used274] GR32:%vreg899 GR64:%vreg901
8240B		%vreg899<def,tied1> = ADD32ri8 %vreg899<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg899
8256B		MOV32mr %vreg901, 1, %noreg, 1092, %noreg, %vreg899; mem:ST4[%nblock_used274] GR64:%vreg901 GR32:%vreg899
8272B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2

8288B	BB#47: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#0
8304B		%vreg55<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg55
8320B		%vreg54<def> = MOV32rm %vreg55, 1, %noreg, 3184, %noreg; mem:LD4[%calculatedBlockCRC276] GR32:%vreg54 GR64:%vreg55
8336B		MOV32mr <fi#3>, 1, %noreg, 0, %noreg, %vreg54; mem:ST4[%c_calculatedBlockCRC] GR32:%vreg54
8352B		%vreg51<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg51
8368B		%vreg50<def> = MOV8rm %vreg51, 1, %noreg, 12, %noreg; mem:LD1[%state_out_ch277] GR8:%vreg50 GR64:%vreg51
8384B		MOV8mr <fi#4>, 1, %noreg, 0, %noreg, %vreg50; mem:ST1[%c_state_out_ch] GR8:%vreg50
8400B		%vreg47<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg47
8416B		%vreg46<def> = MOV32rm %vreg47, 1, %noreg, 16, %noreg; mem:LD4[%state_out_len278] GR32:%vreg46 GR64:%vreg47
8432B		MOV32mr <fi#5>, 1, %noreg, 0, %noreg, %vreg46; mem:ST4[%c_state_out_len] GR32:%vreg46
8448B		%vreg43<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg43
8464B		%vreg42<def> = MOV32rm %vreg43, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used279] GR32:%vreg42 GR64:%vreg43
8480B		MOV32mr <fi#6>, 1, %noreg, 0, %noreg, %vreg42; mem:ST4[%c_nblock_used] GR32:%vreg42
8496B		%vreg39<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg39
8512B		%vreg38<def> = MOV32rm %vreg39, 1, %noreg, 64, %noreg; mem:LD4[%k0280] GR32:%vreg38 GR64:%vreg39
8528B		MOV32mr <fi#7>, 1, %noreg, 0, %noreg, %vreg38; mem:ST4[%c_k0] GR32:%vreg38
8544B		%vreg35<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg35
8560B		%vreg34<def> = MOV64rm %vreg35, 1, %noreg, 3152, %noreg; mem:LD8[%tt281] GR64:%vreg34,%vreg35
8576B		MOV64mr <fi#8>, 1, %noreg, 0, %noreg, %vreg34; mem:ST8[%c_tt] GR64:%vreg34
8592B		%vreg31<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg31
8608B		%vreg30<def> = MOV32rm %vreg31, 1, %noreg, 60, %noreg; mem:LD4[%tPos282] GR32:%vreg30 GR64:%vreg31
8624B		MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %vreg30; mem:ST4[%c_tPos] GR32:%vreg30
8640B		%vreg27<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg27
8656B		%vreg26<def> = MOV64rm %vreg27, 1, %noreg, 0, %noreg; mem:LD8[%strm283] GR64:%vreg26,%vreg27
8672B		%vreg24<def> = MOV64rm %vreg26, 1, %noreg, 24, %noreg; mem:LD8[%next_out284] GR64:%vreg24,%vreg26
8688B		MOV64mr <fi#10>, 1, %noreg, 0, %noreg, %vreg24; mem:ST8[%cs_next_out] GR64:%vreg24
8704B		%vreg21<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg21
8720B		%vreg20<def> = MOV64rm %vreg21, 1, %noreg, 0, %noreg; mem:LD8[%strm285] GR64:%vreg20,%vreg21
8736B		%vreg18<def> = MOV32rm %vreg20, 1, %noreg, 32, %noreg; mem:LD4[%avail_out286] GR32:%vreg18 GR64:%vreg20
8752B		MOV32mr <fi#11>, 1, %noreg, 0, %noreg, %vreg18; mem:ST4[%cs_avail_out] GR32:%vreg18
8768B		%vreg15<def> = MOV32rm <fi#11>, 1, %noreg, 0, %noreg; mem:LD4[%cs_avail_out] GR32:%vreg15
8784B		MOV32mr <fi#12>, 1, %noreg, 0, %noreg, %vreg15; mem:ST4[%avail_out_INIT] GR32:%vreg15
8800B		%vreg13<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg13
8816B		%vreg10<def> = MOV32rm %vreg13, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock287] GR32:%vreg10 GR64:%vreg13
8848B		%vreg10<def,tied1> = ADD32ri8 %vreg10<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg10
8864B		MOV32mr <fi#13>, 1, %noreg, 0, %noreg, %vreg10; mem:ST4[%s_save_nblockPP] GR32:%vreg10
	    Successors according to CFG: BB#48

8880B	BB#48: derived from LLVM BB %while.body.289
	    Predecessors according to CFG: BB#47 BB#75 BB#74 BB#72 BB#70 BB#68
8896B		CMP32mi8 <fi#5>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%c_state_out_len]
8912B		JLE_1 <BB#59>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#59 BB#49

8928B	BB#49: derived from LLVM BB %if.then.292
	    Predecessors according to CFG: BB#48
8944B		JMP_1 <BB#50>
	    Successors according to CFG: BB#50

8960B	BB#50: derived from LLVM BB %while.body.294
	    Predecessors according to CFG: BB#49 BB#54
8976B		CMP32mi8 <fi#11>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%cs_avail_out]
8992B		JNE_1 <BB#52>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#52 BB#51

9008B	BB#51: derived from LLVM BB %if.then.297
	    Predecessors according to CFG: BB#50
9024B		JMP_1 <BB#76>
	    Successors according to CFG: BB#76

9040B	BB#52: derived from LLVM BB %if.end.298
	    Predecessors according to CFG: BB#50
9056B		CMP32mi8 <fi#5>, 1, %noreg, 0, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%c_state_out_len]
9072B		JNE_1 <BB#54>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#54 BB#53

9088B	BB#53: derived from LLVM BB %if.then.301
	    Predecessors according to CFG: BB#52
9104B		JMP_1 <BB#55>
	    Successors according to CFG: BB#55

9120B	BB#54: derived from LLVM BB %if.end.302
	    Predecessors according to CFG: BB#52
9136B		%vreg93<def> = MOV8rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD1[%c_state_out_ch] GR8:%vreg93
9152B		%vreg92<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%cs_next_out] GR64:%vreg92
9168B		MOV8mr %vreg92, 1, %noreg, 0, %noreg, %vreg93; mem:ST1[%249] GR64:%vreg92 GR8:%vreg93
9184B		%vreg74<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%c_calculatedBlockCRC] GR32:%vreg74
9216B		%vreg74<def,tied1> = SHL32ri %vreg74<tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg74
9232B		%vreg81<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%c_calculatedBlockCRC] GR32:%vreg81
9264B		%vreg81<def,tied1> = SHR32ri %vreg81<tied0>, 24, %EFLAGS<imp-def,dead>; GR32:%vreg81
9280B		%vreg83<def> = MOVZX32rm8 <fi#4>, 1, %noreg, 0, %noreg; mem:LD1[%c_state_out_ch] GR32:%vreg83
9312B		%vreg81<def,tied1> = XOR32rr %vreg81<tied0>, %vreg83, %EFLAGS<imp-def,dead>; GR32:%vreg81,%vreg83
9328B		%vreg78:sub_32bit<def,read-undef> = MOV32rr %vreg81; GR64_NOSP:%vreg78 GR32:%vreg81
9376B		%vreg74<def,tied1> = XOR32rm %vreg74<tied0>, %noreg, 4, %vreg78, <ga:@BZ2_crc32Table>, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%arrayidx308] GR32:%vreg74 GR64_NOSP:%vreg78
9392B		MOV32mr <fi#3>, 1, %noreg, 0, %noreg, %vreg74; mem:ST4[%c_calculatedBlockCRC] GR32:%vreg74
9408B		%vreg69<def> = MOV32rm <fi#5>, 1, %noreg, 0, %noreg; mem:LD4[%c_state_out_len] GR32:%vreg69
9440B		%vreg69<def,tied1> = ADD32ri8 %vreg69<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg69
9456B		MOV32mr <fi#5>, 1, %noreg, 0, %noreg, %vreg69; mem:ST4[%c_state_out_len] GR32:%vreg69
9472B		%vreg65<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%cs_next_out] GR64:%vreg65
9504B		%vreg65<def,tied1> = ADD64ri8 %vreg65<tied0>, 1, %EFLAGS<imp-def,dead>; GR64:%vreg65
9520B		MOV64mr <fi#10>, 1, %noreg, 0, %noreg, %vreg65; mem:ST8[%cs_next_out] GR64:%vreg65
9536B		%vreg61<def> = MOV32rm <fi#11>, 1, %noreg, 0, %noreg; mem:LD4[%cs_avail_out] GR32:%vreg61
9568B		%vreg61<def,tied1> = ADD32ri8 %vreg61<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg61
9584B		MOV32mr <fi#11>, 1, %noreg, 0, %noreg, %vreg61; mem:ST4[%cs_avail_out] GR32:%vreg61
9600B		JMP_1 <BB#50>
	    Successors according to CFG: BB#50

9616B	BB#55: derived from LLVM BB %while.end.313
	    Predecessors according to CFG: BB#53
9632B		JMP_1 <BB#56>
	    Successors according to CFG: BB#56

9648B	BB#56: derived from LLVM BB %s_state_out_len_eq_one
	    Predecessors according to CFG: BB#55 BB#66 BB#64
9664B		CMP32mi8 <fi#11>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%cs_avail_out]
9680B		JNE_1 <BB#58>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#58 BB#57

9696B	BB#57: derived from LLVM BB %if.then.316
	    Predecessors according to CFG: BB#56
9712B		MOV32mi <fi#5>, 1, %noreg, 0, %noreg, 1; mem:ST4[%c_state_out_len]
9728B		JMP_1 <BB#76>
	    Successors according to CFG: BB#76

9744B	BB#58: derived from LLVM BB %if.end.317
	    Predecessors according to CFG: BB#56
9760B		%vreg125<def> = MOV8rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD1[%c_state_out_ch] GR8:%vreg125
9776B		%vreg124<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%cs_next_out] GR64:%vreg124
9792B		MOV8mr %vreg124, 1, %noreg, 0, %noreg, %vreg125; mem:ST1[%259] GR64:%vreg124 GR8:%vreg125
9808B		%vreg106<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%c_calculatedBlockCRC] GR32:%vreg106
9840B		%vreg106<def,tied1> = SHL32ri %vreg106<tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg106
9856B		%vreg113<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%c_calculatedBlockCRC] GR32:%vreg113
9888B		%vreg113<def,tied1> = SHR32ri %vreg113<tied0>, 24, %EFLAGS<imp-def,dead>; GR32:%vreg113
9904B		%vreg115<def> = MOVZX32rm8 <fi#4>, 1, %noreg, 0, %noreg; mem:LD1[%c_state_out_ch] GR32:%vreg115
9936B		%vreg113<def,tied1> = XOR32rr %vreg113<tied0>, %vreg115, %EFLAGS<imp-def,dead>; GR32:%vreg113,%vreg115
9952B		%vreg110:sub_32bit<def,read-undef> = MOV32rr %vreg113; GR64_NOSP:%vreg110 GR32:%vreg113
10000B		%vreg106<def,tied1> = XOR32rm %vreg106<tied0>, %noreg, 4, %vreg110, <ga:@BZ2_crc32Table>, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%arrayidx323] GR32:%vreg106 GR64_NOSP:%vreg110
10016B		MOV32mr <fi#3>, 1, %noreg, 0, %noreg, %vreg106; mem:ST4[%c_calculatedBlockCRC] GR32:%vreg106
10032B		%vreg101<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%cs_next_out] GR64:%vreg101
10064B		%vreg101<def,tied1> = ADD64ri8 %vreg101<tied0>, 1, %EFLAGS<imp-def,dead>; GR64:%vreg101
10080B		MOV64mr <fi#10>, 1, %noreg, 0, %noreg, %vreg101; mem:ST8[%cs_next_out] GR64:%vreg101
10096B		%vreg97<def> = MOV32rm <fi#11>, 1, %noreg, 0, %noreg; mem:LD4[%cs_avail_out] GR32:%vreg97
10128B		%vreg97<def,tied1> = ADD32ri8 %vreg97<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg97
10144B		MOV32mr <fi#11>, 1, %noreg, 0, %noreg, %vreg97; mem:ST4[%cs_avail_out] GR32:%vreg97
	    Successors according to CFG: BB#59

10160B	BB#59: derived from LLVM BB %if.end.327
	    Predecessors according to CFG: BB#48 BB#58
10176B		%vreg128<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%c_nblock_used] GR32:%vreg128
10192B		CMP32rm %vreg128, <fi#13>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD4[%s_save_nblockPP] GR32:%vreg128
10208B		JLE_1 <BB#61>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#61 BB#60

10224B	BB#60: derived from LLVM BB %if.then.330
	    Predecessors according to CFG: BB#59
10240B		MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 1; mem:ST1[%retval]
10256B		JMP_1 <BB#80>
	    Successors according to CFG: BB#80

10272B	BB#61: derived from LLVM BB %if.end.331
	    Predecessors according to CFG: BB#59
10288B		%vreg131<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%c_nblock_used] GR32:%vreg131
10304B		CMP32rm %vreg131, <fi#13>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD4[%s_save_nblockPP] GR32:%vreg131
10320B		JNE_1 <BB#63>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#63 BB#62

10336B	BB#62: derived from LLVM BB %if.then.334
	    Predecessors according to CFG: BB#61
10352B		MOV32mi <fi#5>, 1, %noreg, 0, %noreg, 0; mem:ST4[%c_state_out_len]
10368B		JMP_1 <BB#76>
	    Successors according to CFG: BB#76

10384B	BB#63: derived from LLVM BB %if.end.335
	    Predecessors according to CFG: BB#61
10400B		%vreg161<def> = MOV32rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD4[%c_k0] GR32:%vreg161
10432B		MOV8mr <fi#4>, 1, %noreg, 0, %noreg, %vreg161:sub_8bit; mem:ST1[%c_state_out_ch] GR32:%vreg161
10448B		%vreg157:sub_32bit<def,read-undef> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR64_NOSP:%vreg157
10480B		%vreg154<def> = MOV64rm <fi#8>, 1, %noreg, 0, %noreg; mem:LD8[%c_tt] GR64:%vreg154
10496B		%vreg153<def> = MOV32rm %vreg154, 4, %vreg157, 0, %noreg; mem:LD4[%arrayidx338] GR32:%vreg153 GR64:%vreg154 GR64_NOSP:%vreg157
10512B		MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %vreg153; mem:ST4[%c_tPos] GR32:%vreg153
10528B		%vreg148<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR32:%vreg148
10560B		%vreg148<def,tied1> = AND32ri %vreg148<tied0>, 255, %EFLAGS<imp-def,dead>; GR32:%vreg148
10592B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg148:sub_8bit; mem:ST1[%k1] GR32:%vreg148
10608B		%vreg142<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR32:%vreg142
10640B		%vreg142<def,tied1> = SHR32ri %vreg142<tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg142
10656B		MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %vreg142; mem:ST4[%c_tPos] GR32:%vreg142
10672B		%vreg138<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%c_nblock_used] GR32:%vreg138
10704B		%vreg138<def,tied1> = ADD32ri8 %vreg138<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg138
10720B		MOV32mr <fi#6>, 1, %noreg, 0, %noreg, %vreg138; mem:ST4[%c_nblock_used] GR32:%vreg138
10736B		%vreg135<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg135
10752B		CMP32rm %vreg135, <fi#7>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD4[%c_k0] GR32:%vreg135
10768B		JE_1 <BB#65>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#65 BB#64

10784B	BB#64: derived from LLVM BB %if.then.346
	    Predecessors according to CFG: BB#63
10800B		%vreg282<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg282
10816B		MOV32mr <fi#7>, 1, %noreg, 0, %noreg, %vreg282; mem:ST4[%c_k0] GR32:%vreg282
10832B		JMP_1 <BB#56>
	    Successors according to CFG: BB#56

10848B	BB#65: derived from LLVM BB %if.end.348
	    Predecessors according to CFG: BB#63
10864B		%vreg164<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%c_nblock_used] GR32:%vreg164
10880B		CMP32rm %vreg164, <fi#13>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD4[%s_save_nblockPP] GR32:%vreg164
10896B		JNE_1 <BB#67>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#67 BB#66

10912B	BB#66: derived from LLVM BB %if.then.351
	    Predecessors according to CFG: BB#65
10928B		JMP_1 <BB#56>
	    Successors according to CFG: BB#56

10944B	BB#67: derived from LLVM BB %if.end.352
	    Predecessors according to CFG: BB#65
10960B		MOV32mi <fi#5>, 1, %noreg, 0, %noreg, 2; mem:ST4[%c_state_out_len]
10976B		%vreg189:sub_32bit<def,read-undef> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR64_NOSP:%vreg189
11008B		%vreg186<def> = MOV64rm <fi#8>, 1, %noreg, 0, %noreg; mem:LD8[%c_tt] GR64:%vreg186
11024B		%vreg185<def> = MOV32rm %vreg186, 4, %vreg189, 0, %noreg; mem:LD4[%arrayidx354] GR32:%vreg185 GR64:%vreg186 GR64_NOSP:%vreg189
11040B		MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %vreg185; mem:ST4[%c_tPos] GR32:%vreg185
11056B		%vreg180<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR32:%vreg180
11088B		%vreg180<def,tied1> = AND32ri %vreg180<tied0>, 255, %EFLAGS<imp-def,dead>; GR32:%vreg180
11120B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg180:sub_8bit; mem:ST1[%k1] GR32:%vreg180
11136B		%vreg174<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR32:%vreg174
11168B		%vreg174<def,tied1> = SHR32ri %vreg174<tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg174
11184B		MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %vreg174; mem:ST4[%c_tPos] GR32:%vreg174
11200B		%vreg170<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%c_nblock_used] GR32:%vreg170
11232B		%vreg170<def,tied1> = ADD32ri8 %vreg170<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg170
11248B		MOV32mr <fi#6>, 1, %noreg, 0, %noreg, %vreg170; mem:ST4[%c_nblock_used] GR32:%vreg170
11264B		%vreg167<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%c_nblock_used] GR32:%vreg167
11280B		CMP32rm %vreg167, <fi#13>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD4[%s_save_nblockPP] GR32:%vreg167
11296B		JNE_1 <BB#69>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#69 BB#68

11312B	BB#68: derived from LLVM BB %if.then.361
	    Predecessors according to CFG: BB#67
11328B		JMP_1 <BB#48>
	    Successors according to CFG: BB#48

11344B	BB#69: derived from LLVM BB %if.end.362
	    Predecessors according to CFG: BB#67
11360B		%vreg193<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg193
11376B		CMP32rm %vreg193, <fi#7>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD4[%c_k0] GR32:%vreg193
11392B		JE_1 <BB#71>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#71 BB#70

11408B	BB#70: derived from LLVM BB %if.then.366
	    Predecessors according to CFG: BB#69
11424B		%vreg279<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg279
11440B		MOV32mr <fi#7>, 1, %noreg, 0, %noreg, %vreg279; mem:ST4[%c_k0] GR32:%vreg279
11456B		JMP_1 <BB#48>
	    Successors according to CFG: BB#48

11472B	BB#71: derived from LLVM BB %if.end.368
	    Predecessors according to CFG: BB#69
11488B		MOV32mi <fi#5>, 1, %noreg, 0, %noreg, 3; mem:ST4[%c_state_out_len]
11504B		%vreg218:sub_32bit<def,read-undef> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR64_NOSP:%vreg218
11536B		%vreg215<def> = MOV64rm <fi#8>, 1, %noreg, 0, %noreg; mem:LD8[%c_tt] GR64:%vreg215
11552B		%vreg214<def> = MOV32rm %vreg215, 4, %vreg218, 0, %noreg; mem:LD4[%arrayidx370] GR32:%vreg214 GR64:%vreg215 GR64_NOSP:%vreg218
11568B		MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %vreg214; mem:ST4[%c_tPos] GR32:%vreg214
11584B		%vreg209<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR32:%vreg209
11616B		%vreg209<def,tied1> = AND32ri %vreg209<tied0>, 255, %EFLAGS<imp-def,dead>; GR32:%vreg209
11648B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg209:sub_8bit; mem:ST1[%k1] GR32:%vreg209
11664B		%vreg203<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR32:%vreg203
11696B		%vreg203<def,tied1> = SHR32ri %vreg203<tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg203
11712B		MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %vreg203; mem:ST4[%c_tPos] GR32:%vreg203
11728B		%vreg199<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%c_nblock_used] GR32:%vreg199
11760B		%vreg199<def,tied1> = ADD32ri8 %vreg199<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg199
11776B		MOV32mr <fi#6>, 1, %noreg, 0, %noreg, %vreg199; mem:ST4[%c_nblock_used] GR32:%vreg199
11792B		%vreg196<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%c_nblock_used] GR32:%vreg196
11808B		CMP32rm %vreg196, <fi#13>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD4[%s_save_nblockPP] GR32:%vreg196
11824B		JNE_1 <BB#73>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#73 BB#72

11840B	BB#72: derived from LLVM BB %if.then.377
	    Predecessors according to CFG: BB#71
11856B		JMP_1 <BB#48>
	    Successors according to CFG: BB#48

11872B	BB#73: derived from LLVM BB %if.end.378
	    Predecessors according to CFG: BB#71
11888B		%vreg222<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg222
11904B		CMP32rm %vreg222, <fi#7>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD4[%c_k0] GR32:%vreg222
11920B		JE_1 <BB#75>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#75 BB#74

11936B	BB#74: derived from LLVM BB %if.then.382
	    Predecessors according to CFG: BB#73
11952B		%vreg276<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg276
11968B		MOV32mr <fi#7>, 1, %noreg, 0, %noreg, %vreg276; mem:ST4[%c_k0] GR32:%vreg276
11984B		JMP_1 <BB#48>
	    Successors according to CFG: BB#48

12000B	BB#75: derived from LLVM BB %if.end.384
	    Predecessors according to CFG: BB#73
12016B		%vreg273:sub_32bit<def,read-undef> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR64_NOSP:%vreg273
12048B		%vreg270<def> = MOV64rm <fi#8>, 1, %noreg, 0, %noreg; mem:LD8[%c_tt] GR64:%vreg270
12064B		%vreg269<def> = MOV32rm %vreg270, 4, %vreg273, 0, %noreg; mem:LD4[%arrayidx386] GR32:%vreg269 GR64:%vreg270 GR64_NOSP:%vreg273
12080B		MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %vreg269; mem:ST4[%c_tPos] GR32:%vreg269
12096B		%vreg264<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR32:%vreg264
12128B		%vreg264<def,tied1> = AND32ri %vreg264<tied0>, 255, %EFLAGS<imp-def,dead>; GR32:%vreg264
12160B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg264:sub_8bit; mem:ST1[%k1] GR32:%vreg264
12176B		%vreg258<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR32:%vreg258
12208B		%vreg258<def,tied1> = SHR32ri %vreg258<tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg258
12224B		MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %vreg258; mem:ST4[%c_tPos] GR32:%vreg258
12240B		%vreg254<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%c_nblock_used] GR32:%vreg254
12272B		%vreg254<def,tied1> = ADD32ri8 %vreg254<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg254
12288B		MOV32mr <fi#6>, 1, %noreg, 0, %noreg, %vreg254; mem:ST4[%c_nblock_used] GR32:%vreg254
12304B		%vreg249<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg249
12336B		%vreg249<def,tied1> = ADD32ri8 %vreg249<tied0>, 4, %EFLAGS<imp-def,dead>; GR32:%vreg249
12352B		MOV32mr <fi#5>, 1, %noreg, 0, %noreg, %vreg249; mem:ST4[%c_state_out_len] GR32:%vreg249
12368B		%vreg246:sub_32bit<def,read-undef> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR64_NOSP:%vreg246
12400B		%vreg243<def> = MOV64rm <fi#8>, 1, %noreg, 0, %noreg; mem:LD8[%c_tt] GR64:%vreg243
12416B		%vreg242<def> = MOV32rm %vreg243, 4, %vreg246, 0, %noreg; mem:LD4[%arrayidx394] GR32:%vreg242 GR64:%vreg243 GR64_NOSP:%vreg246
12432B		MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %vreg242; mem:ST4[%c_tPos] GR32:%vreg242
12448B		%vreg237<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR32:%vreg237
12480B		%vreg237<def,tied1> = AND32ri %vreg237<tied0>, 255, %EFLAGS<imp-def,dead>; GR32:%vreg237
12512B		%vreg233<def> = MOVZX32rr8 %vreg237:sub_8bit; GR32:%vreg233,%vreg237
12528B		MOV32mr <fi#7>, 1, %noreg, 0, %noreg, %vreg233; mem:ST4[%c_k0] GR32:%vreg233
12544B		%vreg229<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR32:%vreg229
12576B		%vreg229<def,tied1> = SHR32ri %vreg229<tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg229
12592B		MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %vreg229; mem:ST4[%c_tPos] GR32:%vreg229
12608B		%vreg225<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%c_nblock_used] GR32:%vreg225
12640B		%vreg225<def,tied1> = ADD32ri8 %vreg225<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg225
12656B		MOV32mr <fi#6>, 1, %noreg, 0, %noreg, %vreg225; mem:ST4[%c_nblock_used] GR32:%vreg225
12672B		JMP_1 <BB#48>
	    Successors according to CFG: BB#48

12688B	BB#76: derived from LLVM BB %return_notr
	    Predecessors according to CFG: BB#62 BB#57 BB#51
12704B		%vreg307<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg307
12720B		%vreg306<def> = MOV64rm %vreg307, 1, %noreg, 0, %noreg; mem:LD8[%strm400] GR64:%vreg306,%vreg307
12736B		%vreg304<def> = MOV32rm %vreg306, 1, %noreg, 36, %noreg; mem:LD4[%total_out_lo32401] GR32:%vreg304 GR64:%vreg306
12752B		MOV32mr <fi#14>, 1, %noreg, 0, %noreg, %vreg304; mem:ST4[%total_out_lo32_old] GR32:%vreg304
12768B		%vreg294<def> = MOV32rm <fi#12>, 1, %noreg, 0, %noreg; mem:LD4[%avail_out_INIT] GR32:%vreg294
12800B		%vreg294<def,tied1> = SUB32rm %vreg294<tied0>, <fi#11>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%cs_avail_out] GR32:%vreg294
12816B		%vreg297<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg297
12832B		%vreg296<def> = MOV64rm %vreg297, 1, %noreg, 0, %noreg; mem:LD8[%strm402] GR64:%vreg296,%vreg297
12864B		%vreg294<def,tied1> = ADD32rm %vreg294<tied0>, %vreg296, 1, %noreg, 36, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%total_out_lo32403] GR32:%vreg294 GR64:%vreg296
12880B		MOV32mr %vreg296, 1, %noreg, 36, %noreg, %vreg294; mem:ST4[%total_out_lo32403] GR64:%vreg296 GR32:%vreg294
12896B		%vreg289<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg289
12912B		%vreg288<def> = MOV64rm %vreg289, 1, %noreg, 0, %noreg; mem:LD8[%strm405] GR64:%vreg288,%vreg289
12928B		%vreg286<def> = MOV32rm %vreg288, 1, %noreg, 36, %noreg; mem:LD4[%total_out_lo32406] GR32:%vreg286 GR64:%vreg288
12944B		CMP32rm %vreg286, <fi#14>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD4[%total_out_lo32_old] GR32:%vreg286
12960B		JAE_1 <BB#78>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#78 BB#77

12976B	BB#77: derived from LLVM BB %if.then.409
	    Predecessors according to CFG: BB#76
12992B		%vreg315<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg315
13008B		%vreg314<def> = MOV64rm %vreg315, 1, %noreg, 0, %noreg; mem:LD8[%strm410] GR64:%vreg314,%vreg315
13024B		%vreg311<def> = MOV32rm %vreg314, 1, %noreg, 40, %noreg; mem:LD4[%total_out_hi32411] GR32:%vreg311 GR64:%vreg314
13056B		%vreg311<def,tied1> = ADD32ri8 %vreg311<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg311
13072B		MOV32mr %vreg314, 1, %noreg, 40, %noreg, %vreg311; mem:ST4[%total_out_hi32411] GR64:%vreg314 GR32:%vreg311
	    Successors according to CFG: BB#78

13088B	BB#78: derived from LLVM BB %if.end.413
	    Predecessors according to CFG: BB#76 BB#77
13104B		%vreg355<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%c_calculatedBlockCRC] GR32:%vreg355
13120B		%vreg354<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg354
13136B		MOV32mr %vreg354, 1, %noreg, 3184, %noreg, %vreg355; mem:ST4[%calculatedBlockCRC414] GR64:%vreg354 GR32:%vreg355
13152B		%vreg351<def> = MOV8rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD1[%c_state_out_ch] GR8:%vreg351
13168B		%vreg350<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg350
13184B		MOV8mr %vreg350, 1, %noreg, 12, %noreg, %vreg351; mem:ST1[%state_out_ch415] GR64:%vreg350 GR8:%vreg351
13200B		%vreg347<def> = MOV32rm <fi#5>, 1, %noreg, 0, %noreg; mem:LD4[%c_state_out_len] GR32:%vreg347
13216B		%vreg346<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg346
13232B		MOV32mr %vreg346, 1, %noreg, 16, %noreg, %vreg347; mem:ST4[%state_out_len416] GR64:%vreg346 GR32:%vreg347
13248B		%vreg343<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%c_nblock_used] GR32:%vreg343
13264B		%vreg342<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg342
13280B		MOV32mr %vreg342, 1, %noreg, 1092, %noreg, %vreg343; mem:ST4[%nblock_used417] GR64:%vreg342 GR32:%vreg343
13296B		%vreg339<def> = MOV32rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD4[%c_k0] GR32:%vreg339
13312B		%vreg338<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg338
13328B		MOV32mr %vreg338, 1, %noreg, 64, %noreg, %vreg339; mem:ST4[%k0418] GR64:%vreg338 GR32:%vreg339
13344B		%vreg335<def> = MOV64rm <fi#8>, 1, %noreg, 0, %noreg; mem:LD8[%c_tt] GR64:%vreg335
13360B		%vreg334<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg334
13376B		MOV64mr %vreg334, 1, %noreg, 3152, %noreg, %vreg335; mem:ST8[%tt419] GR64:%vreg334,%vreg335
13392B		%vreg331<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR32:%vreg331
13408B		%vreg330<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg330
13424B		MOV32mr %vreg330, 1, %noreg, 60, %noreg, %vreg331; mem:ST4[%tPos420] GR64:%vreg330 GR32:%vreg331
13440B		%vreg327<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%cs_next_out] GR64:%vreg327
13456B		%vreg326<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg326
13472B		%vreg325<def> = MOV64rm %vreg326, 1, %noreg, 0, %noreg; mem:LD8[%strm421] GR64:%vreg325,%vreg326
13488B		MOV64mr %vreg325, 1, %noreg, 24, %noreg, %vreg327; mem:ST8[%next_out422] GR64:%vreg325,%vreg327
13504B		%vreg321<def> = MOV32rm <fi#11>, 1, %noreg, 0, %noreg; mem:LD4[%cs_avail_out] GR32:%vreg321
13520B		%vreg320<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg320
13536B		%vreg319<def> = MOV64rm %vreg320, 1, %noreg, 0, %noreg; mem:LD8[%strm423] GR64:%vreg319,%vreg320
13552B		MOV32mr %vreg319, 1, %noreg, 32, %noreg, %vreg321; mem:ST4[%avail_out424] GR64:%vreg319 GR32:%vreg321
	    Successors according to CFG: BB#79

13568B	BB#79: derived from LLVM BB %if.end.425
	    Predecessors according to CFG: BB#78
13584B		MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST1[%retval]
	    Successors according to CFG: BB#80

13600B	BB#80: derived from LLVM BB %return
	    Predecessors according to CFG: BB#60 BB#79 BB#13 BB#11 BB#4
13616B		%vreg938<def> = MOV64ri <ga:@unRLE_obuf_to_output_FAST>; GR64:%vreg938
13648B		%vreg939<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg939
13664B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
13680B		%RDI<def> = COPY %vreg938; GR64:%vreg938
13696B		%RSI<def> = COPY %vreg939; GR64:%vreg939
13712B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
13728B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
13744B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
13760B		STACKMAP 1, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=1)
13776B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
13792B		%vreg936<def> = MOV8rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD1[%retval] GR8:%vreg936
13808B		%AL<def> = COPY %vreg936; GR8:%vreg936
13824B		RETQ %AL<imp-use,kill>

# End machine code for function unRLE_obuf_to_output_FAST.


selectOrSplit GR64:%vreg1 [16r,224r:0)  0@16r w=4.983552e-03
hints: %RDI
missed hint %RDI
assigning %vreg1 to %RBX: BH [16r,224r:0)  0@16r BL [16r,224r:0)  0@16r

selectOrSplit GR64:%vreg6 [48r,112r:0)  0@48r w=2.176724e-03
hints: %RDI
assigning %vreg6 to %RDI: DIL [48r,112r:0)  0@48r

selectOrSplit GR64:%vreg7 [80r,128r:0)  0@80r w=4.508928e-03
hints: %RSI
assigning %vreg7 to %RSI: SIL [80r,128r:0)  0@80r

selectOrSplit GR64:%vreg938 [13616r,13680r:0)  0@13616r w=2.176724e-03
hints: %RDI
assigning %vreg938 to %RDI: DIL [13616r,13680r:0)  0@13616r

selectOrSplit GR64:%vreg939 [13648r,13696r:0)  0@13648r w=4.508928e-03
hints: %RSI
assigning %vreg939 to %RSI: SIL [13648r,13696r:0)  0@13648r

selectOrSplit GR8:%vreg936 [13792r,13808r:0)  0@13792r w=inf
hints: %AL
assigning %vreg936 to %AL: AL [13792r,13808r:0)  0@13792r

selectOrSplit GR64:%vreg4 [240r,256r:0)  0@240r w=inf
assigning %vreg4 to %RAX: AH [240r,256r:0)  0@240r AL [240r,256r:0)  0@240r

selectOrSplit GR64:%vreg360 [368r,384r:0)  0@368r w=inf
assigning %vreg360 to %RAX: AH [368r,384r:0)  0@368r AL [368r,384r:0)  0@368r

selectOrSplit GR64:%vreg359 [384r,400r:0)  0@384r w=inf
assigning %vreg359 to %RAX: AH [384r,400r:0)  0@384r AL [384r,400r:0)  0@384r

selectOrSplit GR64:%vreg363 [496r,512r:0)  0@496r w=inf
assigning %vreg363 to %RAX: AH [496r,512r:0)  0@496r AL [496r,512r:0)  0@496r

selectOrSplit GR64:%vreg435 [592r,608r:0)  0@592r w=inf
assigning %vreg435 to %RAX: AH [592r,608r:0)  0@592r AL [592r,608r:0)  0@592r

selectOrSplit GR8:%vreg434 [608r,672r:0)  0@608r w=7.836208e-04
assigning %vreg434 to %AL: AL [608r,672r:0)  0@608r

selectOrSplit GR64:%vreg432 [624r,640r:0)  0@624r w=inf
assigning %vreg432 to %RCX: CH [624r,640r:0)  0@624r CL [624r,640r:0)  0@624r

selectOrSplit GR64:%vreg431 [640r,656r:0)  0@640r w=inf
assigning %vreg431 to %RCX: CH [640r,656r:0)  0@640r CL [640r,656r:0)  0@640r

selectOrSplit GR64:%vreg429 [656r,672r:0)  0@656r w=inf
assigning %vreg429 to %RCX: CH [656r,672r:0)  0@656r CL [656r,672r:0)  0@656r

selectOrSplit GR64:%vreg425 [688r,704r:0)  0@688r w=inf
assigning %vreg425 to %RAX: AH [688r,704r:0)  0@688r AL [688r,704r:0)  0@688r

selectOrSplit GR32:%vreg404 [704r,736r:2)[736r,928r:0)[928r,960r:1)  0@736r 1@928r 2@704r w=1.662805e-03
assigning %vreg404 to %EAX: AH [704r,736r:2)[736r,928r:0)[928r,960r:1)  0@736r 1@928r 2@704r AL [704r,736r:2)[736r,928r:0)[928r,960r:1)  0@736r 1@928r 2@704r

selectOrSplit GR64:%vreg420 [752r,768r:0)  0@752r w=inf
assigning %vreg420 to %RCX: CH [752r,768r:0)  0@752r CL [752r,768r:0)  0@752r

selectOrSplit GR32:%vreg411 [768r,800r:2)[800r,864r:0)[864r,880r:1)  0@800r 1@864r 2@768r w=2.130469e-03
assigning %vreg411 to %ECX: CH [768r,800r:2)[800r,864r:0)[864r,880r:1)  0@800r 1@864r 2@768r CL [768r,800r:2)[800r,864r:0)[864r,880r:1)  0@800r 1@864r 2@768r

selectOrSplit GR64:%vreg415 [816r,832r:0)  0@816r w=inf
assigning %vreg415 to %RDX: DH [816r,832r:0)  0@816r DL [816r,832r:0)  0@816r

selectOrSplit GR32:%vreg413 [832r,864r:0)  0@832r w=inf
assigning %vreg413 to %EDX: DH [832r,864r:0)  0@832r DL [832r,864r:0)  0@832r

selectOrSplit GR64_NOSP:%vreg408 [880r,928r:0)  0@880r w=inf
assigning %vreg408 to %RCX: CH [880r,928r:0)  0@880r CL [880r,928r:0)  0@880r

selectOrSplit GR64:%vreg401 [944r,960r:0)  0@944r w=inf
assigning %vreg401 to %RCX: CH [944r,960r:0)  0@944r CL [944r,960r:0)  0@944r

selectOrSplit GR64:%vreg398 [976r,1040r:0)  0@976r w=1.175431e-03
assigning %vreg398 to %RAX: AH [976r,1040r:0)  0@976r AL [976r,1040r:0)  0@976r

selectOrSplit GR32:%vreg396 [992r,1024r:0)[1024r,1040r:1)  0@992r 1@1024r w=inf
assigning %vreg396 to %ECX: CH [992r,1024r:0)[1024r,1040r:1)  0@992r 1@1024r CL [992r,1024r:0)[1024r,1040r:1)  0@992r 1@1024r

selectOrSplit GR64:%vreg392 [1056r,1072r:0)  0@1056r w=inf
assigning %vreg392 to %RAX: AH [1056r,1072r:0)  0@1056r AL [1056r,1072r:0)  0@1056r

selectOrSplit GR64:%vreg391 [1072r,1136r:0)  0@1072r w=1.175431e-03
assigning %vreg391 to %RAX: AH [1072r,1136r:0)  0@1072r AL [1072r,1136r:0)  0@1072r

selectOrSplit GR64:%vreg388 [1088r,1120r:0)[1120r,1136r:1)  0@1088r 1@1120r w=inf
assigning %vreg388 to %RCX: CH [1088r,1120r:0)[1120r,1136r:1)  0@1088r 1@1120r CL [1088r,1120r:0)[1120r,1136r:1)  0@1088r 1@1120r

selectOrSplit GR64:%vreg384 [1152r,1168r:0)  0@1152r w=inf
assigning %vreg384 to %RAX: AH [1152r,1168r:0)  0@1152r AL [1152r,1168r:0)  0@1152r

selectOrSplit GR64:%vreg383 [1168r,1232r:0)  0@1168r w=1.175431e-03
assigning %vreg383 to %RAX: AH [1168r,1232r:0)  0@1168r AL [1168r,1232r:0)  0@1168r

selectOrSplit GR32:%vreg380 [1184r,1216r:0)[1216r,1232r:1)  0@1184r 1@1216r w=inf
assigning %vreg380 to %ECX: CH [1184r,1216r:0)[1216r,1232r:1)  0@1184r 1@1216r CL [1184r,1216r:0)[1216r,1232r:1)  0@1184r 1@1216r

selectOrSplit GR64:%vreg376 [1248r,1264r:0)  0@1248r w=inf
assigning %vreg376 to %RAX: AH [1248r,1264r:0)  0@1248r AL [1248r,1264r:0)  0@1248r

selectOrSplit GR64:%vreg375 [1264r,1328r:0)  0@1264r w=1.175431e-03
assigning %vreg375 to %RAX: AH [1264r,1328r:0)  0@1264r AL [1264r,1328r:0)  0@1264r

selectOrSplit GR32:%vreg372 [1280r,1312r:0)[1312r,1328r:1)  0@1280r 1@1312r w=inf
assigning %vreg372 to %ECX: CH [1280r,1312r:0)[1312r,1328r:1)  0@1280r 1@1312r CL [1280r,1312r:0)[1312r,1328r:1)  0@1280r 1@1312r

selectOrSplit GR64:%vreg368 [1344r,1360r:0)  0@1344r w=inf
assigning %vreg368 to %RAX: AH [1344r,1360r:0)  0@1344r AL [1344r,1360r:0)  0@1344r

selectOrSplit GR64:%vreg367 [1360r,1376r:0)  0@1360r w=inf
assigning %vreg367 to %RAX: AH [1360r,1376r:0)  0@1360r AL [1360r,1376r:0)  0@1360r

selectOrSplit GR64:%vreg443 [1424r,1440r:0)  0@1424r w=inf
assigning %vreg443 to %RAX: AH [1424r,1440r:0)  0@1424r AL [1424r,1440r:0)  0@1424r

selectOrSplit GR64:%vreg442 [1440r,1504r:0)  0@1440r w=5.876438e-04
assigning %vreg442 to %RAX: AH [1440r,1504r:0)  0@1440r AL [1440r,1504r:0)  0@1440r

selectOrSplit GR32:%vreg439 [1456r,1488r:0)[1488r,1504r:1)  0@1456r 1@1488r w=inf
assigning %vreg439 to %ECX: CH [1456r,1488r:0)[1488r,1504r:1)  0@1456r 1@1488r CL [1456r,1488r:0)[1488r,1504r:1)  0@1456r 1@1488r

selectOrSplit GR64:%vreg453 [1568r,1584r:0)  0@1568r w=inf
assigning %vreg453 to %RAX: AH [1568r,1584r:0)  0@1568r AL [1568r,1584r:0)  0@1568r

selectOrSplit GR32:%vreg452 [1584r,1664r:0)  0@1584r w=7.575001e-04
assigning %vreg452 to %EAX: AH [1584r,1664r:0)  0@1584r AL [1584r,1664r:0)  0@1584r

selectOrSplit GR64:%vreg450 [1600r,1616r:0)  0@1600r w=inf
assigning %vreg450 to %RCX: CH [1600r,1616r:0)  0@1600r CL [1600r,1616r:0)  0@1600r

selectOrSplit GR32:%vreg447 [1616r,1648r:0)[1648r,1664r:1)  0@1616r 1@1648r w=inf
assigning %vreg447 to %ECX: CH [1616r,1648r:0)[1648r,1664r:1)  0@1616r 1@1648r CL [1616r,1648r:0)[1648r,1664r:1)  0@1616r 1@1648r

selectOrSplit GR64:%vreg463 [1760r,1776r:0)  0@1760r w=inf
assigning %vreg463 to %RAX: AH [1760r,1776r:0)  0@1760r AL [1760r,1776r:0)  0@1760r

selectOrSplit GR32:%vreg462 [1776r,1856r:0)  0@1776r w=3.787038e-04
assigning %vreg462 to %EAX: AH [1776r,1856r:0)  0@1776r AL [1776r,1856r:0)  0@1776r

selectOrSplit GR64:%vreg460 [1792r,1808r:0)  0@1792r w=inf
assigning %vreg460 to %RCX: CH [1792r,1808r:0)  0@1792r CL [1792r,1808r:0)  0@1792r

selectOrSplit GR32:%vreg457 [1808r,1840r:0)[1840r,1856r:1)  0@1808r 1@1840r w=inf
assigning %vreg457 to %ECX: CH [1808r,1840r:0)[1840r,1856r:1)  0@1808r 1@1840r CL [1808r,1840r:0)[1840r,1856r:1)  0@1808r 1@1840r

selectOrSplit GR64:%vreg504 [1952r,1968r:0)  0@1952r w=inf
assigning %vreg504 to %RAX: AH [1952r,1968r:0)  0@1952r AL [1952r,1968r:0)  0@1952r

selectOrSplit GR64:%vreg502 [1984r,2000r:0)  0@1984r w=inf
assigning %vreg502 to %RAX: AH [1984r,2000r:0)  0@1984r AL [1984r,2000r:0)  0@1984r

selectOrSplit GR32:%vreg501 [2000r,2048r:0)  0@2000r w=2.028275e-04
assigning %vreg501 to %EAX: AH [2000r,2048r:0)  0@2000r AL [2000r,2048r:0)  0@2000r

selectOrSplit GR64:%vreg497 [2032r,2048r:0)  0@2032r w=inf
assigning %vreg497 to %RCX: CH [2032r,2048r:0)  0@2032r CL [2032r,2048r:0)  0@2032r

selectOrSplit GR64:%vreg494 [2064r,2080r:0)  0@2064r w=inf
assigning %vreg494 to %RAX: AH [2064r,2080r:0)  0@2064r AL [2064r,2080r:0)  0@2064r

selectOrSplit GR64_NOSP:%vreg492 [2080r,2144r:0)  0@2080r w=1.958334e-04
assigning %vreg492 to %RAX: AH [2080r,2144r:0)  0@2080r AL [2080r,2144r:0)  0@2080r

selectOrSplit GR64:%vreg489 [2112r,2128r:0)  0@2112r w=inf
assigning %vreg489 to %RCX: CH [2112r,2128r:0)  0@2112r CL [2112r,2128r:0)  0@2112r

selectOrSplit GR64:%vreg488 [2128r,2144r:0)  0@2128r w=inf
assigning %vreg488 to %RCX: CH [2128r,2144r:0)  0@2128r CL [2128r,2144r:0)  0@2128r

selectOrSplit GR32:%vreg486 [2144r,2176r:0)  0@2144r w=2.103396e-04
assigning %vreg486 to %EAX: AH [2144r,2176r:0)  0@2144r AL [2144r,2176r:0)  0@2144r

selectOrSplit GR64:%vreg483 [2160r,2176r:0)  0@2160r w=inf
assigning %vreg483 to %RCX: CH [2160r,2176r:0)  0@2160r CL [2160r,2176r:0)  0@2160r

selectOrSplit GR64:%vreg480 [2192r,2208r:0)  0@2192r w=inf
assigning %vreg480 to %RAX: AH [2192r,2208r:0)  0@2192r AL [2192r,2208r:0)  0@2192r

selectOrSplit GR32:%vreg477 [2208r,2240r:0)[2240r,2272r:1)  0@2208r 1@2240r w=inf
assigning %vreg477 to %EAX: AH [2208r,2240r:0)[2240r,2272r:1)  0@2208r 1@2240r AL [2208r,2240r:0)[2240r,2272r:1)  0@2208r 1@2240r

selectOrSplit GR64:%vreg472 [2288r,2352r:0)  0@2288r w=2.937501e-04
assigning %vreg472 to %RAX: AH [2288r,2352r:0)  0@2288r AL [2288r,2352r:0)  0@2288r

selectOrSplit GR32:%vreg470 [2304r,2336r:0)[2336r,2352r:1)  0@2304r 1@2336r w=inf
assigning %vreg470 to %ECX: CH [2304r,2336r:0)[2336r,2352r:1)  0@2304r 1@2336r CL [2304r,2336r:0)[2336r,2352r:1)  0@2304r 1@2336r

selectOrSplit GR64:%vreg466 [2368r,2384r:0)  0@2368r w=inf
assigning %vreg466 to %RAX: AH [2368r,2384r:0)  0@2368r AL [2368r,2384r:0)  0@2368r

selectOrSplit GR64:%vreg522 [2432r,2448r:0)  0@2432r w=inf
assigning %vreg522 to %RAX: AH [2432r,2448r:0)  0@2432r AL [2432r,2448r:0)  0@2432r

selectOrSplit GR64_NOSP:%vreg520 [2448r,2464r:0)  0@2448r w=inf
assigning %vreg520 to %RAX: AH [2448r,2464r:0)  0@2448r AL [2448r,2464r:0)  0@2448r

selectOrSplit GR32:%vreg518 [2464r,2496r:0)  0@2464r w=1.051184e-04
assigning %vreg518 to %EAX: AH [2464r,2496r:0)  0@2464r AL [2464r,2496r:0)  0@2464r

selectOrSplit GR64:%vreg516 [2480r,2496r:0)  0@2480r w=inf
assigning %vreg516 to %RCX: CH [2480r,2496r:0)  0@2480r CL [2480r,2496r:0)  0@2480r

selectOrSplit GR64:%vreg513 [2512r,2576r:0)  0@2512r w=1.468033e-04
assigning %vreg513 to %RAX: AH [2512r,2576r:0)  0@2512r AL [2512r,2576r:0)  0@2512r

selectOrSplit GR32:%vreg511 [2528r,2560r:0)[2560r,2576r:1)  0@2528r 1@2560r w=inf
assigning %vreg511 to %ECX: CH [2528r,2560r:0)[2560r,2576r:1)  0@2528r 1@2560r CL [2528r,2560r:0)[2560r,2576r:1)  0@2528r 1@2560r

selectOrSplit GR64:%vreg507 [2592r,2608r:0)  0@2592r w=inf
assigning %vreg507 to %RAX: AH [2592r,2608r:0)  0@2592r AL [2592r,2608r:0)  0@2592r

selectOrSplit GR64:%vreg524 [2656r,2672r:0)  0@2656r w=inf
assigning %vreg524 to %RAX: AH [2656r,2672r:0)  0@2656r AL [2656r,2672r:0)  0@2656r

selectOrSplit GR32:%vreg552 [2736r,2896r:0)[2896r,2944r:1)  0@2736r 1@2896r w=2.989037e-04
assigning %vreg552 to %EAX: AH [2736r,2896r:0)[2896r,2944r:1)  0@2736r 1@2896r AL [2736r,2896r:0)[2896r,2944r:1)  0@2736r 1@2896r

selectOrSplit GR32:%vreg551 [2752r,2896r:0)  0@2752r w=8.351720e-05
assigning %vreg551 to %ECX: CH [2752r,2896r:0)  0@2752r CL [2752r,2896r:0)  0@2752r

selectOrSplit GR64:%vreg560 [2768r,2832r:0)  0@2768r w=2.937501e-04
assigning %vreg560 to %RDX: DH [2768r,2832r:0)  0@2768r DL [2768r,2832r:0)  0@2768r

selectOrSplit GR32:%vreg558 [2784r,2816r:0)[2816r,2832r:1)  0@2784r 1@2816r w=inf
assigning %vreg558 to %ESI: SIL [2784r,2816r:0)[2816r,2832r:1)  0@2784r 1@2816r

selectOrSplit GR64:%vreg554 [2848r,2864r:0)  0@2848r w=inf
assigning %vreg554 to %RDX: DH [2848r,2864r:0)  0@2848r DL [2848r,2864r:0)  0@2848r

selectOrSplit GR32:%vreg546 [2912r,2944r:0)[2944r,2976r:1)  0@2912r 1@2944r w=inf
assigning %vreg546 to %ECX: CH [2912r,2944r:0)[2944r,2976r:1)  0@2912r 1@2944r CL [2912r,2944r:0)[2944r,2976r:1)  0@2912r 1@2944r

selectOrSplit GR64:%vreg540 [2992r,3056r:0)  0@2992r w=2.937501e-04
assigning %vreg540 to %RAX: AH [2992r,3056r:0)  0@2992r AL [2992r,3056r:0)  0@2992r

selectOrSplit GR32:%vreg538 [3008r,3040r:0)[3040r,3056r:1)  0@3008r 1@3040r w=inf
assigning %vreg538 to %ECX: CH [3008r,3040r:0)[3040r,3056r:1)  0@3008r 1@3040r CL [3008r,3040r:0)[3040r,3056r:1)  0@3008r 1@3040r

selectOrSplit GR64:%vreg534 [3072r,3088r:0)  0@3072r w=inf
assigning %vreg534 to %RAX: AH [3072r,3088r:0)  0@3072r AL [3072r,3088r:0)  0@3072r

selectOrSplit GR32:%vreg533 [3088r,3168r:0)  0@3088r w=1.893057e-04
assigning %vreg533 to %EAX: AH [3088r,3168r:0)  0@3088r AL [3088r,3168r:0)  0@3088r

selectOrSplit GR64:%vreg531 [3104r,3120r:0)  0@3104r w=inf
assigning %vreg531 to %RCX: CH [3104r,3120r:0)  0@3104r CL [3104r,3120r:0)  0@3104r

selectOrSplit GR32:%vreg528 [3120r,3152r:0)[3152r,3168r:1)  0@3120r 1@3152r w=inf
assigning %vreg528 to %ECX: CH [3120r,3152r:0)[3152r,3168r:1)  0@3120r 1@3152r CL [3120r,3152r:0)[3152r,3168r:1)  0@3120r 1@3152r

selectOrSplit GR32:%vreg566 [3248r,3280r:0)  0@3248r w=1.051184e-04
assigning %vreg566 to %EAX: AH [3248r,3280r:0)  0@3248r AL [3248r,3280r:0)  0@3248r

selectOrSplit GR64:%vreg564 [3264r,3280r:0)  0@3264r w=inf
assigning %vreg564 to %RCX: CH [3264r,3280r:0)  0@3264r CL [3264r,3280r:0)  0@3264r

selectOrSplit GR32:%vreg934 [3328r,3360r:0)  0@3328r w=5.250784e-05
assigning %vreg934 to %EAX: AH [3328r,3360r:0)  0@3328r AL [3328r,3360r:0)  0@3328r

selectOrSplit GR64:%vreg932 [3344r,3360r:0)  0@3344r w=inf
assigning %vreg932 to %RCX: CH [3344r,3360r:0)  0@3344r CL [3344r,3360r:0)  0@3344r

selectOrSplit GR64:%vreg599 [3408r,3424r:0)  0@3408r w=inf
assigning %vreg599 to %RAX: AH [3408r,3424r:0)  0@3408r AL [3408r,3424r:0)  0@3408r

selectOrSplit GR64:%vreg597 [3440r,3456r:0)  0@3440r w=inf
assigning %vreg597 to %RAX: AH [3440r,3456r:0)  0@3440r AL [3440r,3456r:0)  0@3440r

selectOrSplit GR64_NOSP:%vreg595 [3456r,3520r:0)  0@3456r w=4.888661e-05
assigning %vreg595 to %RAX: AH [3456r,3520r:0)  0@3456r AL [3456r,3520r:0)  0@3456r

selectOrSplit GR64:%vreg592 [3488r,3504r:0)  0@3488r w=inf
assigning %vreg592 to %RCX: CH [3488r,3504r:0)  0@3488r CL [3488r,3504r:0)  0@3488r

selectOrSplit GR64:%vreg591 [3504r,3520r:0)  0@3504r w=inf
assigning %vreg591 to %RCX: CH [3504r,3520r:0)  0@3504r CL [3504r,3520r:0)  0@3504r

selectOrSplit GR32:%vreg589 [3520r,3552r:0)  0@3520r w=5.250784e-05
assigning %vreg589 to %EAX: AH [3520r,3552r:0)  0@3520r AL [3520r,3552r:0)  0@3520r

selectOrSplit GR64:%vreg586 [3536r,3552r:0)  0@3536r w=inf
assigning %vreg586 to %RCX: CH [3536r,3552r:0)  0@3536r CL [3536r,3552r:0)  0@3536r

selectOrSplit GR64:%vreg583 [3568r,3584r:0)  0@3568r w=inf
assigning %vreg583 to %RAX: AH [3568r,3584r:0)  0@3568r AL [3568r,3584r:0)  0@3568r

selectOrSplit GR32:%vreg580 [3584r,3616r:0)[3616r,3648r:1)  0@3584r 1@3616r w=inf
assigning %vreg580 to %EAX: AH [3584r,3616r:0)[3616r,3648r:1)  0@3584r 1@3616r AL [3584r,3616r:0)[3616r,3648r:1)  0@3584r 1@3616r

selectOrSplit GR64:%vreg575 [3664r,3728r:0)  0@3664r w=7.332992e-05
assigning %vreg575 to %RAX: AH [3664r,3728r:0)  0@3664r AL [3664r,3728r:0)  0@3664r

selectOrSplit GR32:%vreg573 [3680r,3712r:0)[3712r,3728r:1)  0@3680r 1@3712r w=inf
assigning %vreg573 to %ECX: CH [3680r,3712r:0)[3712r,3728r:1)  0@3680r 1@3712r CL [3680r,3712r:0)[3712r,3728r:1)  0@3680r 1@3712r

selectOrSplit GR64:%vreg569 [3744r,3760r:0)  0@3744r w=inf
assigning %vreg569 to %RAX: AH [3744r,3760r:0)  0@3744r AL [3744r,3760r:0)  0@3744r

selectOrSplit GR64:%vreg617 [3808r,3824r:0)  0@3808r w=inf
assigning %vreg617 to %RAX: AH [3808r,3824r:0)  0@3808r AL [3808r,3824r:0)  0@3808r

selectOrSplit GR64_NOSP:%vreg615 [3824r,3840r:0)  0@3824r w=inf
assigning %vreg615 to %RAX: AH [3824r,3840r:0)  0@3824r AL [3824r,3840r:0)  0@3824r

selectOrSplit GR32:%vreg613 [3840r,3872r:0)  0@3840r w=2.620254e-05
assigning %vreg613 to %EAX: AH [3840r,3872r:0)  0@3840r AL [3840r,3872r:0)  0@3840r

selectOrSplit GR64:%vreg611 [3856r,3872r:0)  0@3856r w=inf
assigning %vreg611 to %RCX: CH [3856r,3872r:0)  0@3856r CL [3856r,3872r:0)  0@3856r

selectOrSplit GR64:%vreg608 [3888r,3952r:0)  0@3888r w=3.659321e-05
assigning %vreg608 to %RAX: AH [3888r,3952r:0)  0@3888r AL [3888r,3952r:0)  0@3888r

selectOrSplit GR32:%vreg606 [3904r,3936r:0)[3936r,3952r:1)  0@3904r 1@3936r w=inf
assigning %vreg606 to %ECX: CH [3904r,3936r:0)[3936r,3952r:1)  0@3904r 1@3936r CL [3904r,3936r:0)[3936r,3952r:1)  0@3904r 1@3936r

selectOrSplit GR64:%vreg602 [3968r,3984r:0)  0@3968r w=inf
assigning %vreg602 to %RAX: AH [3968r,3984r:0)  0@3968r AL [3968r,3984r:0)  0@3968r

selectOrSplit GR64:%vreg619 [4032r,4048r:0)  0@4032r w=inf
assigning %vreg619 to %RAX: AH [4032r,4048r:0)  0@4032r AL [4032r,4048r:0)  0@4032r

selectOrSplit GR32:%vreg647 [4112r,4272r:0)[4272r,4320r:1)  0@4112r 1@4272r w=7.461640e-05
assigning %vreg647 to %EAX: AH [4112r,4272r:0)[4272r,4320r:1)  0@4112r 1@4272r AL [4112r,4272r:0)[4272r,4320r:1)  0@4112r 1@4272r

selectOrSplit GR32:%vreg646 [4128r,4272r:0)  0@4128r w=2.084870e-05
assigning %vreg646 to %ECX: CH [4128r,4272r:0)  0@4128r CL [4128r,4272r:0)  0@4128r

selectOrSplit GR64:%vreg655 [4144r,4208r:0)  0@4144r w=7.332992e-05
assigning %vreg655 to %RDX: DH [4144r,4208r:0)  0@4144r DL [4144r,4208r:0)  0@4144r

selectOrSplit GR32:%vreg653 [4160r,4192r:0)[4192r,4208r:1)  0@4160r 1@4192r w=inf
assigning %vreg653 to %ESI: SIL [4160r,4192r:0)[4192r,4208r:1)  0@4160r 1@4192r

selectOrSplit GR64:%vreg649 [4224r,4240r:0)  0@4224r w=inf
assigning %vreg649 to %RDX: DH [4224r,4240r:0)  0@4224r DL [4224r,4240r:0)  0@4224r

selectOrSplit GR32:%vreg641 [4288r,4320r:0)[4320r,4352r:1)  0@4288r 1@4320r w=inf
assigning %vreg641 to %ECX: CH [4288r,4320r:0)[4320r,4352r:1)  0@4288r 1@4320r CL [4288r,4320r:0)[4320r,4352r:1)  0@4288r 1@4320r

selectOrSplit GR64:%vreg635 [4368r,4432r:0)  0@4368r w=7.332992e-05
assigning %vreg635 to %RAX: AH [4368r,4432r:0)  0@4368r AL [4368r,4432r:0)  0@4368r

selectOrSplit GR32:%vreg633 [4384r,4416r:0)[4416r,4432r:1)  0@4384r 1@4416r w=inf
assigning %vreg633 to %ECX: CH [4384r,4416r:0)[4416r,4432r:1)  0@4384r 1@4416r CL [4384r,4416r:0)[4416r,4432r:1)  0@4384r 1@4416r

selectOrSplit GR64:%vreg629 [4448r,4464r:0)  0@4448r w=inf
assigning %vreg629 to %RAX: AH [4448r,4464r:0)  0@4448r AL [4448r,4464r:0)  0@4448r

selectOrSplit GR32:%vreg628 [4464r,4544r:0)  0@4464r w=4.725705e-05
assigning %vreg628 to %EAX: AH [4464r,4544r:0)  0@4464r AL [4464r,4544r:0)  0@4464r

selectOrSplit GR64:%vreg626 [4480r,4496r:0)  0@4480r w=inf
assigning %vreg626 to %RCX: CH [4480r,4496r:0)  0@4480r CL [4480r,4496r:0)  0@4480r

selectOrSplit GR32:%vreg623 [4496r,4528r:0)[4528r,4544r:1)  0@4496r 1@4528r w=inf
assigning %vreg623 to %ECX: CH [4496r,4528r:0)[4528r,4544r:1)  0@4496r 1@4528r CL [4496r,4528r:0)[4528r,4544r:1)  0@4496r 1@4528r

selectOrSplit GR32:%vreg661 [4624r,4656r:0)  0@4624r w=2.620254e-05
assigning %vreg661 to %EAX: AH [4624r,4656r:0)  0@4624r AL [4624r,4656r:0)  0@4624r

selectOrSplit GR64:%vreg659 [4640r,4656r:0)  0@4640r w=inf
assigning %vreg659 to %RCX: CH [4640r,4656r:0)  0@4640r CL [4640r,4656r:0)  0@4640r

selectOrSplit GR32:%vreg929 [4704r,4736r:0)  0@4704r w=1.304989e-05
assigning %vreg929 to %EAX: AH [4704r,4736r:0)  0@4704r AL [4704r,4736r:0)  0@4704r

selectOrSplit GR64:%vreg927 [4720r,4736r:0)  0@4720r w=inf
assigning %vreg927 to %RCX: CH [4720r,4736r:0)  0@4720r CL [4720r,4736r:0)  0@4720r

selectOrSplit GR64:%vreg694 [4784r,4800r:0)  0@4784r w=inf
assigning %vreg694 to %RAX: AH [4784r,4800r:0)  0@4784r AL [4784r,4800r:0)  0@4784r

selectOrSplit GR64:%vreg692 [4816r,4832r:0)  0@4816r w=inf
assigning %vreg692 to %RAX: AH [4816r,4832r:0)  0@4816r AL [4816r,4832r:0)  0@4816r

selectOrSplit GR64_NOSP:%vreg690 [4832r,4896r:0)  0@4832r w=1.214990e-05
assigning %vreg690 to %RAX: AH [4832r,4896r:0)  0@4832r AL [4832r,4896r:0)  0@4832r

selectOrSplit GR64:%vreg687 [4864r,4880r:0)  0@4864r w=inf
assigning %vreg687 to %RCX: CH [4864r,4880r:0)  0@4864r CL [4864r,4880r:0)  0@4864r

selectOrSplit GR64:%vreg686 [4880r,4896r:0)  0@4880r w=inf
assigning %vreg686 to %RCX: CH [4880r,4896r:0)  0@4880r CL [4880r,4896r:0)  0@4880r

selectOrSplit GR32:%vreg684 [4896r,4928r:0)  0@4896r w=1.304989e-05
assigning %vreg684 to %EAX: AH [4896r,4928r:0)  0@4896r AL [4896r,4928r:0)  0@4896r

selectOrSplit GR64:%vreg681 [4912r,4928r:0)  0@4912r w=inf
assigning %vreg681 to %RCX: CH [4912r,4928r:0)  0@4912r CL [4912r,4928r:0)  0@4912r

selectOrSplit GR64:%vreg678 [4944r,4960r:0)  0@4944r w=inf
assigning %vreg678 to %RAX: AH [4944r,4960r:0)  0@4944r AL [4944r,4960r:0)  0@4944r

selectOrSplit GR32:%vreg675 [4960r,4992r:0)[4992r,5024r:1)  0@4960r 1@4992r w=inf
assigning %vreg675 to %EAX: AH [4960r,4992r:0)[4992r,5024r:1)  0@4960r 1@4992r AL [4960r,4992r:0)[4992r,5024r:1)  0@4960r 1@4992r

selectOrSplit GR64:%vreg670 [5040r,5104r:0)  0@5040r w=1.822485e-05
assigning %vreg670 to %RAX: AH [5040r,5104r:0)  0@5040r AL [5040r,5104r:0)  0@5040r

selectOrSplit GR32:%vreg668 [5056r,5088r:0)[5088r,5104r:1)  0@5056r 1@5088r w=inf
assigning %vreg668 to %ECX: CH [5056r,5088r:0)[5088r,5104r:1)  0@5056r 1@5088r CL [5056r,5088r:0)[5088r,5104r:1)  0@5056r 1@5088r

selectOrSplit GR64:%vreg664 [5120r,5136r:0)  0@5120r w=inf
assigning %vreg664 to %RAX: AH [5120r,5136r:0)  0@5120r AL [5120r,5136r:0)  0@5120r

selectOrSplit GR64:%vreg712 [5184r,5200r:0)  0@5184r w=inf
assigning %vreg712 to %RAX: AH [5184r,5200r:0)  0@5184r AL [5184r,5200r:0)  0@5184r

selectOrSplit GR64_NOSP:%vreg710 [5200r,5216r:0)  0@5200r w=inf
assigning %vreg710 to %RAX: AH [5200r,5216r:0)  0@5200r AL [5200r,5216r:0)  0@5200r

selectOrSplit GR32:%vreg708 [5216r,5248r:0)  0@5216r w=6.473569e-06
assigning %vreg708 to %EAX: AH [5216r,5248r:0)  0@5216r AL [5216r,5248r:0)  0@5216r

selectOrSplit GR64:%vreg706 [5232r,5248r:0)  0@5232r w=inf
assigning %vreg706 to %RCX: CH [5232r,5248r:0)  0@5232r CL [5232r,5248r:0)  0@5232r

selectOrSplit GR64:%vreg703 [5264r,5328r:0)  0@5264r w=9.040675e-06
assigning %vreg703 to %RAX: AH [5264r,5328r:0)  0@5264r AL [5264r,5328r:0)  0@5264r

selectOrSplit GR32:%vreg701 [5280r,5312r:0)[5312r,5328r:1)  0@5280r 1@5312r w=inf
assigning %vreg701 to %ECX: CH [5280r,5312r:0)[5312r,5328r:1)  0@5280r 1@5312r CL [5280r,5312r:0)[5312r,5328r:1)  0@5280r 1@5312r

selectOrSplit GR64:%vreg697 [5344r,5360r:0)  0@5344r w=inf
assigning %vreg697 to %RAX: AH [5344r,5360r:0)  0@5344r AL [5344r,5360r:0)  0@5344r

selectOrSplit GR64:%vreg714 [5408r,5424r:0)  0@5408r w=inf
assigning %vreg714 to %RAX: AH [5408r,5424r:0)  0@5408r AL [5408r,5424r:0)  0@5408r

selectOrSplit GR32:%vreg742 [5488r,5648r:0)[5648r,5696r:1)  0@5488r 1@5648r w=1.854459e-05
assigning %vreg742 to %EAX: AH [5488r,5648r:0)[5648r,5696r:1)  0@5488r 1@5648r AL [5488r,5648r:0)[5648r,5696r:1)  0@5488r 1@5648r

selectOrSplit GR32:%vreg741 [5504r,5648r:0)  0@5504r w=5.181575e-06
assigning %vreg741 to %ECX: CH [5504r,5648r:0)  0@5504r CL [5504r,5648r:0)  0@5504r

selectOrSplit GR64:%vreg750 [5520r,5584r:0)  0@5520r w=1.822485e-05
assigning %vreg750 to %RDX: DH [5520r,5584r:0)  0@5520r DL [5520r,5584r:0)  0@5520r

selectOrSplit GR32:%vreg748 [5536r,5568r:0)[5568r,5584r:1)  0@5536r 1@5568r w=inf
assigning %vreg748 to %ESI: SIL [5536r,5568r:0)[5568r,5584r:1)  0@5536r 1@5568r

selectOrSplit GR64:%vreg744 [5600r,5616r:0)  0@5600r w=inf
assigning %vreg744 to %RDX: DH [5600r,5616r:0)  0@5600r DL [5600r,5616r:0)  0@5600r

selectOrSplit GR32:%vreg736 [5664r,5696r:0)[5696r,5728r:1)  0@5664r 1@5696r w=inf
assigning %vreg736 to %ECX: CH [5664r,5696r:0)[5696r,5728r:1)  0@5664r 1@5696r CL [5664r,5696r:0)[5696r,5728r:1)  0@5664r 1@5696r

selectOrSplit GR64:%vreg730 [5744r,5808r:0)  0@5744r w=1.822485e-05
assigning %vreg730 to %RAX: AH [5744r,5808r:0)  0@5744r AL [5744r,5808r:0)  0@5744r

selectOrSplit GR32:%vreg728 [5760r,5792r:0)[5792r,5808r:1)  0@5760r 1@5792r w=inf
assigning %vreg728 to %ECX: CH [5760r,5792r:0)[5792r,5808r:1)  0@5760r 1@5792r CL [5760r,5792r:0)[5792r,5808r:1)  0@5760r 1@5792r

selectOrSplit GR64:%vreg724 [5824r,5840r:0)  0@5824r w=inf
assigning %vreg724 to %RAX: AH [5824r,5840r:0)  0@5824r AL [5824r,5840r:0)  0@5824r

selectOrSplit GR32:%vreg723 [5840r,5920r:0)  0@5840r w=1.174490e-05
assigning %vreg723 to %EAX: AH [5840r,5920r:0)  0@5840r AL [5840r,5920r:0)  0@5840r

selectOrSplit GR64:%vreg721 [5856r,5872r:0)  0@5856r w=inf
assigning %vreg721 to %RCX: CH [5856r,5872r:0)  0@5856r CL [5856r,5872r:0)  0@5856r

selectOrSplit GR32:%vreg718 [5872r,5904r:0)[5904r,5920r:1)  0@5872r 1@5904r w=inf
assigning %vreg718 to %ECX: CH [5872r,5904r:0)[5904r,5920r:1)  0@5872r 1@5904r CL [5872r,5904r:0)[5904r,5920r:1)  0@5872r 1@5904r

selectOrSplit GR32:%vreg756 [6000r,6032r:0)  0@6000r w=6.473569e-06
assigning %vreg756 to %EAX: AH [6000r,6032r:0)  0@6000r AL [6000r,6032r:0)  0@6000r

selectOrSplit GR64:%vreg754 [6016r,6032r:0)  0@6016r w=inf
assigning %vreg754 to %RCX: CH [6016r,6032r:0)  0@6016r CL [6016r,6032r:0)  0@6016r

selectOrSplit GR32:%vreg924 [6080r,6112r:0)  0@6080r w=3.185407e-06
assigning %vreg924 to %EAX: AH [6080r,6112r:0)  0@6080r AL [6080r,6112r:0)  0@6080r

selectOrSplit GR64:%vreg922 [6096r,6112r:0)  0@6096r w=inf
assigning %vreg922 to %RCX: CH [6096r,6112r:0)  0@6096r CL [6096r,6112r:0)  0@6096r

selectOrSplit GR64:%vreg787 [6160r,6176r:0)  0@6160r w=inf
assigning %vreg787 to %RAX: AH [6160r,6176r:0)  0@6160r AL [6160r,6176r:0)  0@6160r

selectOrSplit GR64_NOSP:%vreg785 [6176r,6240r:0)  0@6176r w=2.965724e-06
assigning %vreg785 to %RAX: AH [6176r,6240r:0)  0@6176r AL [6176r,6240r:0)  0@6176r

selectOrSplit GR64:%vreg782 [6208r,6224r:0)  0@6208r w=inf
assigning %vreg782 to %RCX: CH [6208r,6224r:0)  0@6208r CL [6208r,6224r:0)  0@6208r

selectOrSplit GR64:%vreg781 [6224r,6240r:0)  0@6224r w=inf
assigning %vreg781 to %RCX: CH [6224r,6240r:0)  0@6224r CL [6224r,6240r:0)  0@6224r

selectOrSplit GR32:%vreg779 [6240r,6272r:0)  0@6240r w=3.185407e-06
assigning %vreg779 to %EAX: AH [6240r,6272r:0)  0@6240r AL [6240r,6272r:0)  0@6240r

selectOrSplit GR64:%vreg776 [6256r,6272r:0)  0@6256r w=inf
assigning %vreg776 to %RCX: CH [6256r,6272r:0)  0@6256r CL [6256r,6272r:0)  0@6256r

selectOrSplit GR64:%vreg773 [6288r,6304r:0)  0@6288r w=inf
assigning %vreg773 to %RAX: AH [6288r,6304r:0)  0@6288r AL [6288r,6304r:0)  0@6288r

selectOrSplit GR32:%vreg770 [6304r,6336r:0)[6336r,6368r:1)  0@6304r 1@6336r w=inf
assigning %vreg770 to %EAX: AH [6304r,6336r:0)[6336r,6368r:1)  0@6304r 1@6336r AL [6304r,6336r:0)[6336r,6368r:1)  0@6304r 1@6336r

selectOrSplit GR64:%vreg765 [6384r,6448r:0)  0@6384r w=4.448586e-06
assigning %vreg765 to %RAX: AH [6384r,6448r:0)  0@6384r AL [6384r,6448r:0)  0@6384r

selectOrSplit GR32:%vreg763 [6400r,6432r:0)[6432r,6448r:1)  0@6400r 1@6432r w=inf
assigning %vreg763 to %ECX: CH [6400r,6432r:0)[6432r,6448r:1)  0@6400r 1@6432r CL [6400r,6432r:0)[6432r,6448r:1)  0@6400r 1@6432r

selectOrSplit GR64:%vreg759 [6464r,6480r:0)  0@6464r w=inf
assigning %vreg759 to %RAX: AH [6464r,6480r:0)  0@6464r AL [6464r,6480r:0)  0@6464r

selectOrSplit GR64:%vreg805 [6528r,6544r:0)  0@6528r w=inf
assigning %vreg805 to %RAX: AH [6528r,6544r:0)  0@6528r AL [6528r,6544r:0)  0@6528r

selectOrSplit GR64_NOSP:%vreg803 [6544r,6560r:0)  0@6544r w=inf
assigning %vreg803 to %RAX: AH [6544r,6560r:0)  0@6544r AL [6544r,6560r:0)  0@6544r

selectOrSplit GR32:%vreg801 [6560r,6592r:0)  0@6560r w=1.644081e-06
assigning %vreg801 to %EAX: AH [6560r,6592r:0)  0@6560r AL [6560r,6592r:0)  0@6560r

selectOrSplit GR64:%vreg799 [6576r,6592r:0)  0@6576r w=inf
assigning %vreg799 to %RCX: CH [6576r,6592r:0)  0@6576r CL [6576r,6592r:0)  0@6576r

selectOrSplit GR64:%vreg796 [6608r,6672r:0)  0@6608r w=2.296044e-06
assigning %vreg796 to %RAX: AH [6608r,6672r:0)  0@6608r AL [6608r,6672r:0)  0@6608r

selectOrSplit GR32:%vreg794 [6624r,6656r:0)[6656r,6672r:1)  0@6624r 1@6656r w=inf
assigning %vreg794 to %ECX: CH [6624r,6656r:0)[6656r,6672r:1)  0@6624r 1@6656r CL [6624r,6656r:0)[6656r,6672r:1)  0@6624r 1@6656r

selectOrSplit GR64:%vreg790 [6688r,6704r:0)  0@6688r w=inf
assigning %vreg790 to %RAX: AH [6688r,6704r:0)  0@6688r AL [6688r,6704r:0)  0@6688r

selectOrSplit GR64:%vreg807 [6752r,6768r:0)  0@6752r w=inf
assigning %vreg807 to %RAX: AH [6752r,6768r:0)  0@6752r AL [6752r,6768r:0)  0@6752r

selectOrSplit GR32:%vreg867 [6832r,6992r:0)[6992r,7040r:1)  0@6832r 1@6992r w=4.526631e-06
assigning %vreg867 to %EAX: AH [6832r,6992r:0)[6992r,7040r:1)  0@6832r 1@6992r AL [6832r,6992r:0)[6992r,7040r:1)  0@6832r 1@6992r

selectOrSplit GR32:%vreg866 [6848r,6992r:0)  0@6848r w=1.264794e-06
assigning %vreg866 to %ECX: CH [6848r,6992r:0)  0@6848r CL [6848r,6992r:0)  0@6848r

selectOrSplit GR64:%vreg875 [6864r,6928r:0)  0@6864r w=4.448586e-06
assigning %vreg875 to %RDX: DH [6864r,6928r:0)  0@6864r DL [6864r,6928r:0)  0@6864r

selectOrSplit GR32:%vreg873 [6880r,6912r:0)[6912r,6928r:1)  0@6880r 1@6912r w=inf
assigning %vreg873 to %ESI: SIL [6880r,6912r:0)[6912r,6928r:1)  0@6880r 1@6912r

selectOrSplit GR64:%vreg869 [6944r,6960r:0)  0@6944r w=inf
assigning %vreg869 to %RDX: DH [6944r,6960r:0)  0@6944r DL [6944r,6960r:0)  0@6944r

selectOrSplit GR32:%vreg861 [7008r,7040r:0)[7040r,7072r:1)  0@7008r 1@7040r w=inf
assigning %vreg861 to %ECX: CH [7008r,7040r:0)[7040r,7072r:1)  0@7008r 1@7040r CL [7008r,7040r:0)[7040r,7072r:1)  0@7008r 1@7040r

selectOrSplit GR64:%vreg855 [7088r,7152r:0)  0@7088r w=4.448586e-06
assigning %vreg855 to %RAX: AH [7088r,7152r:0)  0@7088r AL [7088r,7152r:0)  0@7088r

selectOrSplit GR32:%vreg853 [7104r,7136r:0)[7136r,7152r:1)  0@7104r 1@7136r w=inf
assigning %vreg853 to %ECX: CH [7104r,7136r:0)[7136r,7152r:1)  0@7104r 1@7136r CL [7104r,7136r:0)[7136r,7152r:1)  0@7104r 1@7136r

selectOrSplit GR32:%vreg847 [7168r,7200r:0)[7200r,7232r:1)  0@7168r 1@7200r w=5.931448e-06
assigning %vreg847 to %EAX: AH [7168r,7200r:0)[7200r,7232r:1)  0@7168r 1@7200r AL [7168r,7200r:0)[7200r,7232r:1)  0@7168r 1@7200r

selectOrSplit GR64:%vreg845 [7216r,7232r:0)  0@7216r w=inf
assigning %vreg845 to %RCX: CH [7216r,7232r:0)  0@7216r CL [7216r,7232r:0)  0@7216r

selectOrSplit GR64:%vreg842 [7248r,7264r:0)  0@7248r w=inf
assigning %vreg842 to %RAX: AH [7248r,7264r:0)  0@7248r AL [7248r,7264r:0)  0@7248r

selectOrSplit GR64_NOSP:%vreg840 [7264r,7328r:0)  0@7264r w=2.965724e-06
assigning %vreg840 to %RAX: AH [7264r,7328r:0)  0@7264r AL [7264r,7328r:0)  0@7264r

selectOrSplit GR64:%vreg837 [7296r,7312r:0)  0@7296r w=inf
assigning %vreg837 to %RCX: CH [7296r,7312r:0)  0@7296r CL [7296r,7312r:0)  0@7296r

selectOrSplit GR64:%vreg836 [7312r,7328r:0)  0@7312r w=inf
assigning %vreg836 to %RCX: CH [7312r,7328r:0)  0@7312r CL [7312r,7328r:0)  0@7312r

selectOrSplit GR32:%vreg834 [7328r,7360r:0)  0@7328r w=3.185407e-06
assigning %vreg834 to %EAX: AH [7328r,7360r:0)  0@7328r AL [7328r,7360r:0)  0@7328r

selectOrSplit GR64:%vreg831 [7344r,7360r:0)  0@7344r w=inf
assigning %vreg831 to %RCX: CH [7344r,7360r:0)  0@7344r CL [7344r,7360r:0)  0@7344r

selectOrSplit GR64:%vreg828 [7376r,7392r:0)  0@7376r w=inf
assigning %vreg828 to %RAX: AH [7376r,7392r:0)  0@7376r AL [7376r,7392r:0)  0@7376r

selectOrSplit GR32:%vreg825 [7392r,7424r:0)[7424r,7456r:1)  0@7392r 1@7424r w=inf
assigning %vreg825 to %EAX: AH [7392r,7424r:0)[7424r,7456r:1)  0@7392r 1@7424r AL [7392r,7424r:0)[7424r,7456r:1)  0@7392r 1@7424r

selectOrSplit GR32:%vreg821 [7456r,7488r:0)  0@7456r w=3.185407e-06
assigning %vreg821 to %EAX: AH [7456r,7488r:0)  0@7456r AL [7456r,7488r:0)  0@7456r

selectOrSplit GR64:%vreg819 [7472r,7488r:0)  0@7472r w=inf
assigning %vreg819 to %RCX: CH [7472r,7488r:0)  0@7472r CL [7472r,7488r:0)  0@7472r

selectOrSplit GR64:%vreg816 [7504r,7568r:0)  0@7504r w=4.448586e-06
assigning %vreg816 to %RAX: AH [7504r,7568r:0)  0@7504r AL [7504r,7568r:0)  0@7504r

selectOrSplit GR32:%vreg814 [7520r,7552r:0)[7552r,7568r:1)  0@7520r 1@7552r w=inf
assigning %vreg814 to %ECX: CH [7520r,7552r:0)[7552r,7568r:1)  0@7520r 1@7552r CL [7520r,7552r:0)[7552r,7568r:1)  0@7520r 1@7552r

selectOrSplit GR64:%vreg810 [7584r,7600r:0)  0@7584r w=inf
assigning %vreg810 to %RAX: AH [7584r,7600r:0)  0@7584r AL [7584r,7600r:0)  0@7584r

selectOrSplit GR64:%vreg893 [7648r,7664r:0)  0@7648r w=inf
assigning %vreg893 to %RAX: AH [7648r,7664r:0)  0@7648r AL [7648r,7664r:0)  0@7648r

selectOrSplit GR64_NOSP:%vreg891 [7664r,7680r:0)  0@7664r w=inf
assigning %vreg891 to %RAX: AH [7664r,7680r:0)  0@7664r AL [7664r,7680r:0)  0@7664r

selectOrSplit GR32:%vreg889 [7680r,7712r:0)  0@7680r w=1.644081e-06
assigning %vreg889 to %EAX: AH [7680r,7712r:0)  0@7680r AL [7680r,7712r:0)  0@7680r

selectOrSplit GR64:%vreg887 [7696r,7712r:0)  0@7696r w=inf
assigning %vreg887 to %RCX: CH [7696r,7712r:0)  0@7696r CL [7696r,7712r:0)  0@7696r

selectOrSplit GR64:%vreg884 [7728r,7792r:0)  0@7728r w=2.296044e-06
assigning %vreg884 to %RAX: AH [7728r,7792r:0)  0@7728r AL [7728r,7792r:0)  0@7728r

selectOrSplit GR32:%vreg882 [7744r,7776r:0)[7776r,7792r:1)  0@7744r 1@7776r w=inf
assigning %vreg882 to %ECX: CH [7744r,7776r:0)[7776r,7792r:1)  0@7744r 1@7776r CL [7744r,7776r:0)[7776r,7792r:1)  0@7744r 1@7776r

selectOrSplit GR64:%vreg878 [7808r,7824r:0)  0@7808r w=inf
assigning %vreg878 to %RAX: AH [7808r,7824r:0)  0@7808r AL [7808r,7824r:0)  0@7808r

selectOrSplit GR64:%vreg895 [7872r,7888r:0)  0@7872r w=inf
assigning %vreg895 to %RAX: AH [7872r,7888r:0)  0@7872r AL [7872r,7888r:0)  0@7872r

selectOrSplit GR32:%vreg906 [7952r,8112r:2)[8112r,8160r:0)[8160r,8176r:1)  0@8112r 1@8160r 2@7952r w=6.615845e-06
assigning %vreg906 to %EAX: AH [7952r,8112r:2)[8112r,8160r:0)[8160r,8176r:1)  0@8112r 1@8160r 2@7952r AL [7952r,8112r:2)[8112r,8160r:0)[8160r,8176r:1)  0@8112r 1@8160r 2@7952r

selectOrSplit GR32:%vreg910 [7968r,8112r:0)  0@7968r w=1.264794e-06
assigning %vreg910 to %ECX: CH [7968r,8112r:0)  0@7968r CL [7968r,8112r:0)  0@7968r

selectOrSplit GR64:%vreg919 [7984r,8048r:0)  0@7984r w=4.448586e-06
assigning %vreg919 to %RDX: DH [7984r,8048r:0)  0@7984r DL [7984r,8048r:0)  0@7984r

selectOrSplit GR32:%vreg917 [8000r,8032r:0)[8032r,8048r:1)  0@8000r 1@8032r w=inf
assigning %vreg917 to %ESI: SIL [8000r,8032r:0)[8032r,8048r:1)  0@8000r 1@8032r

selectOrSplit GR64:%vreg913 [8064r,8080r:0)  0@8064r w=inf
assigning %vreg913 to %RDX: DH [8064r,8080r:0)  0@8064r DL [8064r,8080r:0)  0@8064r

selectOrSplit GR64:%vreg907 [8128r,8176r:0)  0@8128r w=4.607464e-06
assigning %vreg907 to %RCX: CH [8128r,8176r:0)  0@8128r CL [8128r,8176r:0)  0@8128r

selectOrSplit GR64:%vreg901 [8192r,8256r:0)  0@8192r w=4.448586e-06
assigning %vreg901 to %RAX: AH [8192r,8256r:0)  0@8192r AL [8192r,8256r:0)  0@8192r

selectOrSplit GR32:%vreg899 [8208r,8240r:0)[8240r,8256r:1)  0@8208r 1@8240r w=inf
assigning %vreg899 to %ECX: CH [8208r,8240r:0)[8240r,8256r:1)  0@8208r 1@8240r CL [8208r,8240r:0)[8240r,8256r:1)  0@8208r 1@8240r

selectOrSplit GR64:%vreg55 [8304r,8320r:0)  0@8304r w=inf
assigning %vreg55 to %RAX: AH [8304r,8320r:0)  0@8304r AL [8304r,8320r:0)  0@8304r

selectOrSplit GR32:%vreg54 [8320r,8336r:0)  0@8320r w=inf
assigning %vreg54 to %EAX: AH [8320r,8336r:0)  0@8320r AL [8320r,8336r:0)  0@8320r

selectOrSplit GR64:%vreg51 [8352r,8368r:0)  0@8352r w=inf
assigning %vreg51 to %RAX: AH [8352r,8368r:0)  0@8352r AL [8352r,8368r:0)  0@8352r

selectOrSplit GR8:%vreg50 [8368r,8384r:0)  0@8368r w=inf
assigning %vreg50 to %AL: AL [8368r,8384r:0)  0@8368r

selectOrSplit GR64:%vreg47 [8400r,8416r:0)  0@8400r w=inf
assigning %vreg47 to %RAX: AH [8400r,8416r:0)  0@8400r AL [8400r,8416r:0)  0@8400r

selectOrSplit GR32:%vreg46 [8416r,8432r:0)  0@8416r w=inf
assigning %vreg46 to %EAX: AH [8416r,8432r:0)  0@8416r AL [8416r,8432r:0)  0@8416r

selectOrSplit GR64:%vreg43 [8448r,8464r:0)  0@8448r w=inf
assigning %vreg43 to %RAX: AH [8448r,8464r:0)  0@8448r AL [8448r,8464r:0)  0@8448r

selectOrSplit GR32:%vreg42 [8464r,8480r:0)  0@8464r w=inf
assigning %vreg42 to %EAX: AH [8464r,8480r:0)  0@8464r AL [8464r,8480r:0)  0@8464r

selectOrSplit GR64:%vreg39 [8496r,8512r:0)  0@8496r w=inf
assigning %vreg39 to %RAX: AH [8496r,8512r:0)  0@8496r AL [8496r,8512r:0)  0@8496r

selectOrSplit GR32:%vreg38 [8512r,8528r:0)  0@8512r w=inf
assigning %vreg38 to %EAX: AH [8512r,8528r:0)  0@8512r AL [8512r,8528r:0)  0@8512r

selectOrSplit GR64:%vreg35 [8544r,8560r:0)  0@8544r w=inf
assigning %vreg35 to %RAX: AH [8544r,8560r:0)  0@8544r AL [8544r,8560r:0)  0@8544r

selectOrSplit GR64:%vreg34 [8560r,8576r:0)  0@8560r w=inf
assigning %vreg34 to %RAX: AH [8560r,8576r:0)  0@8560r AL [8560r,8576r:0)  0@8560r

selectOrSplit GR64:%vreg31 [8592r,8608r:0)  0@8592r w=inf
assigning %vreg31 to %RAX: AH [8592r,8608r:0)  0@8592r AL [8592r,8608r:0)  0@8592r

selectOrSplit GR32:%vreg30 [8608r,8624r:0)  0@8608r w=inf
assigning %vreg30 to %EAX: AH [8608r,8624r:0)  0@8608r AL [8608r,8624r:0)  0@8608r

selectOrSplit GR64:%vreg27 [8640r,8656r:0)  0@8640r w=inf
assigning %vreg27 to %RAX: AH [8640r,8656r:0)  0@8640r AL [8640r,8656r:0)  0@8640r

selectOrSplit GR64:%vreg26 [8656r,8672r:0)  0@8656r w=inf
assigning %vreg26 to %RAX: AH [8656r,8672r:0)  0@8656r AL [8656r,8672r:0)  0@8656r

selectOrSplit GR64:%vreg24 [8672r,8688r:0)  0@8672r w=inf
assigning %vreg24 to %RAX: AH [8672r,8688r:0)  0@8672r AL [8672r,8688r:0)  0@8672r

selectOrSplit GR64:%vreg21 [8704r,8720r:0)  0@8704r w=inf
assigning %vreg21 to %RAX: AH [8704r,8720r:0)  0@8704r AL [8704r,8720r:0)  0@8704r

selectOrSplit GR64:%vreg20 [8720r,8736r:0)  0@8720r w=inf
assigning %vreg20 to %RAX: AH [8720r,8736r:0)  0@8720r AL [8720r,8736r:0)  0@8720r

selectOrSplit GR32:%vreg18 [8736r,8752r:0)  0@8736r w=inf
assigning %vreg18 to %EAX: AH [8736r,8752r:0)  0@8736r AL [8736r,8752r:0)  0@8736r

selectOrSplit GR32:%vreg15 [8768r,8784r:0)  0@8768r w=inf
assigning %vreg15 to %EAX: AH [8768r,8784r:0)  0@8768r AL [8768r,8784r:0)  0@8768r

selectOrSplit GR64:%vreg13 [8800r,8816r:0)  0@8800r w=inf
assigning %vreg13 to %RAX: AH [8800r,8816r:0)  0@8800r AL [8800r,8816r:0)  0@8800r

selectOrSplit GR32:%vreg10 [8816r,8848r:0)[8848r,8864r:1)  0@8816r 1@8848r w=inf
assigning %vreg10 to %EAX: AH [8816r,8848r:0)[8848r,8864r:1)  0@8816r 1@8848r AL [8816r,8848r:0)[8848r,8864r:1)  0@8816r 1@8848r

selectOrSplit GR8:%vreg93 [9136r,9168r:0)  0@9136r w=3.983814e-04
assigning %vreg93 to %AL: AL [9136r,9168r:0)  0@9136r

selectOrSplit GR64:%vreg92 [9152r,9168r:0)  0@9152r w=inf
assigning %vreg92 to %RCX: CH [9152r,9168r:0)  0@9152r CL [9152r,9168r:0)  0@9152r

selectOrSplit GR32:%vreg74 [9184r,9216r:2)[9216r,9376r:0)[9376r,9392r:1)  0@9216r 1@9376r 2@9184r w=8.491813e-04
assigning %vreg74 to %EAX: AH [9184r,9216r:2)[9216r,9376r:0)[9376r,9392r:1)  0@9216r 1@9376r 2@9184r AL [9184r,9216r:2)[9216r,9376r:0)[9376r,9392r:1)  0@9216r 1@9376r 2@9184r

selectOrSplit GR32:%vreg81 [9232r,9264r:2)[9264r,9312r:0)[9312r,9328r:1)  0@9264r 1@9312r 2@9232r w=1.040932e-03
assigning %vreg81 to %ECX: CH [9232r,9264r:2)[9264r,9312r:0)[9312r,9328r:1)  0@9264r 1@9312r 2@9232r CL [9232r,9264r:2)[9264r,9312r:0)[9312r,9328r:1)  0@9264r 1@9312r 2@9232r

selectOrSplit GR32:%vreg83 [9280r,9312r:0)  0@9280r w=inf
assigning %vreg83 to %EDX: DH [9280r,9312r:0)  0@9280r DL [9280r,9312r:0)  0@9280r

selectOrSplit GR64_NOSP:%vreg78 [9328r,9376r:0)  0@9328r w=inf
assigning %vreg78 to %RCX: CH [9328r,9376r:0)  0@9328r CL [9328r,9376r:0)  0@9328r

selectOrSplit GR32:%vreg69 [9408r,9440r:0)[9440r,9456r:1)  0@9408r 1@9440r w=inf
assigning %vreg69 to %EAX: AH [9408r,9440r:0)[9440r,9456r:1)  0@9408r 1@9440r AL [9408r,9440r:0)[9440r,9456r:1)  0@9408r 1@9440r

selectOrSplit GR64:%vreg65 [9472r,9504r:0)[9504r,9520r:1)  0@9472r 1@9504r w=inf
assigning %vreg65 to %RAX: AH [9472r,9504r:0)[9504r,9520r:1)  0@9472r 1@9504r AL [9472r,9504r:0)[9504r,9520r:1)  0@9472r 1@9504r

selectOrSplit GR32:%vreg61 [9536r,9568r:0)[9568r,9584r:1)  0@9536r 1@9568r w=inf
assigning %vreg61 to %EAX: AH [9536r,9568r:0)[9568r,9584r:1)  0@9536r 1@9568r AL [9536r,9568r:0)[9568r,9584r:1)  0@9536r 1@9568r

selectOrSplit GR8:%vreg125 [9760r,9792r:0)  0@9760r w=6.070769e-04
assigning %vreg125 to %AL: AL [9760r,9792r:0)  0@9760r

selectOrSplit GR64:%vreg124 [9776r,9792r:0)  0@9776r w=inf
assigning %vreg124 to %RCX: CH [9776r,9792r:0)  0@9776r CL [9776r,9792r:0)  0@9776r

selectOrSplit GR32:%vreg106 [9808r,9840r:2)[9840r,10000r:0)[10000r,10016r:1)  0@9840r 1@10000r 2@9808r w=1.294032e-03
assigning %vreg106 to %EAX: AH [9808r,9840r:2)[9840r,10000r:0)[10000r,10016r:1)  0@9840r 1@10000r 2@9808r AL [9808r,9840r:2)[9840r,10000r:0)[10000r,10016r:1)  0@9840r 1@10000r 2@9808r

selectOrSplit GR32:%vreg113 [9856r,9888r:2)[9888r,9936r:0)[9936r,9952r:1)  0@9888r 1@9936r 2@9856r w=1.586233e-03
assigning %vreg113 to %ECX: CH [9856r,9888r:2)[9888r,9936r:0)[9936r,9952r:1)  0@9888r 1@9936r 2@9856r CL [9856r,9888r:2)[9888r,9936r:0)[9936r,9952r:1)  0@9888r 1@9936r 2@9856r

selectOrSplit GR32:%vreg115 [9904r,9936r:0)  0@9904r w=inf
assigning %vreg115 to %EDX: DH [9904r,9936r:0)  0@9904r DL [9904r,9936r:0)  0@9904r

selectOrSplit GR64_NOSP:%vreg110 [9952r,10000r:0)  0@9952r w=inf
assigning %vreg110 to %RCX: CH [9952r,10000r:0)  0@9952r CL [9952r,10000r:0)  0@9952r

selectOrSplit GR64:%vreg101 [10032r,10064r:0)[10064r,10080r:1)  0@10032r 1@10064r w=inf
assigning %vreg101 to %RAX: AH [10032r,10064r:0)[10064r,10080r:1)  0@10032r 1@10064r AL [10032r,10064r:0)[10064r,10080r:1)  0@10032r 1@10064r

selectOrSplit GR32:%vreg97 [10096r,10128r:0)[10128r,10144r:1)  0@10096r 1@10128r w=inf
assigning %vreg97 to %EAX: AH [10096r,10128r:0)[10128r,10144r:1)  0@10096r 1@10128r AL [10096r,10128r:0)[10128r,10144r:1)  0@10096r 1@10128r

selectOrSplit GR32:%vreg128 [10176r,10192r:0)  0@10176r w=inf
assigning %vreg128 to %EAX: AH [10176r,10192r:0)  0@10176r AL [10176r,10192r:0)  0@10176r

selectOrSplit GR32:%vreg131 [10288r,10304r:0)  0@10288r w=inf
assigning %vreg131 to %EAX: AH [10288r,10304r:0)  0@10288r AL [10288r,10304r:0)  0@10288r

selectOrSplit GR32:%vreg161 [10400r,10432r:0)  0@10400r w=inf
assigning %vreg161 to %EAX: AH [10400r,10432r:0)  0@10400r AL [10400r,10432r:0)  0@10400r

selectOrSplit GR64_NOSP:%vreg157 [10448r,10496r:0)  0@10448r w=2.926978e-04
assigning %vreg157 to %RAX: AH [10448r,10496r:0)  0@10448r AL [10448r,10496r:0)  0@10448r

selectOrSplit GR64:%vreg154 [10480r,10496r:0)  0@10480r w=inf
assigning %vreg154 to %RCX: CH [10480r,10496r:0)  0@10480r CL [10480r,10496r:0)  0@10480r

selectOrSplit GR32:%vreg153 [10496r,10512r:0)  0@10496r w=inf
assigning %vreg153 to %EAX: AH [10496r,10512r:0)  0@10496r AL [10496r,10512r:0)  0@10496r

selectOrSplit GR32:%vreg148 [10528r,10560r:0)[10560r,10592r:1)  0@10528r 1@10560r w=inf
assigning %vreg148 to %EAX: AH [10528r,10560r:0)[10560r,10592r:1)  0@10528r 1@10560r AL [10528r,10560r:0)[10560r,10592r:1)  0@10528r 1@10560r

selectOrSplit GR32:%vreg142 [10608r,10640r:0)[10640r,10656r:1)  0@10608r 1@10640r w=inf
assigning %vreg142 to %EAX: AH [10608r,10640r:0)[10640r,10656r:1)  0@10608r 1@10640r AL [10608r,10640r:0)[10640r,10656r:1)  0@10608r 1@10640r

selectOrSplit GR32:%vreg138 [10672r,10704r:0)[10704r,10720r:1)  0@10672r 1@10704r w=inf
assigning %vreg138 to %EAX: AH [10672r,10704r:0)[10704r,10720r:1)  0@10672r 1@10704r AL [10672r,10704r:0)[10704r,10720r:1)  0@10672r 1@10704r

selectOrSplit GR32:%vreg135 [10736r,10752r:0)  0@10736r w=inf
assigning %vreg135 to %EAX: AH [10736r,10752r:0)  0@10736r AL [10736r,10752r:0)  0@10736r

selectOrSplit GR32:%vreg282 [10800r,10816r:0)  0@10800r w=inf
assigning %vreg282 to %EAX: AH [10800r,10816r:0)  0@10800r AL [10800r,10816r:0)  0@10800r

selectOrSplit GR32:%vreg164 [10864r,10880r:0)  0@10864r w=inf
assigning %vreg164 to %EAX: AH [10864r,10880r:0)  0@10864r AL [10864r,10880r:0)  0@10864r

selectOrSplit GR64_NOSP:%vreg189 [10976r,11024r:0)  0@10976r w=7.312490e-05
assigning %vreg189 to %RAX: AH [10976r,11024r:0)  0@10976r AL [10976r,11024r:0)  0@10976r

selectOrSplit GR64:%vreg186 [11008r,11024r:0)  0@11008r w=inf
assigning %vreg186 to %RCX: CH [11008r,11024r:0)  0@11008r CL [11008r,11024r:0)  0@11008r

selectOrSplit GR32:%vreg185 [11024r,11040r:0)  0@11024r w=inf
assigning %vreg185 to %EAX: AH [11024r,11040r:0)  0@11024r AL [11024r,11040r:0)  0@11024r

selectOrSplit GR32:%vreg180 [11056r,11088r:0)[11088r,11120r:1)  0@11056r 1@11088r w=inf
assigning %vreg180 to %EAX: AH [11056r,11088r:0)[11088r,11120r:1)  0@11056r 1@11088r AL [11056r,11088r:0)[11088r,11120r:1)  0@11056r 1@11088r

selectOrSplit GR32:%vreg174 [11136r,11168r:0)[11168r,11184r:1)  0@11136r 1@11168r w=inf
assigning %vreg174 to %EAX: AH [11136r,11168r:0)[11168r,11184r:1)  0@11136r 1@11168r AL [11136r,11168r:0)[11168r,11184r:1)  0@11136r 1@11168r

selectOrSplit GR32:%vreg170 [11200r,11232r:0)[11232r,11248r:1)  0@11200r 1@11232r w=inf
assigning %vreg170 to %EAX: AH [11200r,11232r:0)[11232r,11248r:1)  0@11200r 1@11232r AL [11200r,11232r:0)[11232r,11248r:1)  0@11200r 1@11232r

selectOrSplit GR32:%vreg167 [11264r,11280r:0)  0@11264r w=inf
assigning %vreg167 to %EAX: AH [11264r,11280r:0)  0@11264r AL [11264r,11280r:0)  0@11264r

selectOrSplit GR32:%vreg193 [11360r,11376r:0)  0@11360r w=inf
assigning %vreg193 to %EAX: AH [11360r,11376r:0)  0@11360r AL [11360r,11376r:0)  0@11360r

selectOrSplit GR32:%vreg279 [11424r,11440r:0)  0@11424r w=inf
assigning %vreg279 to %EAX: AH [11424r,11440r:0)  0@11424r AL [11424r,11440r:0)  0@11424r

selectOrSplit GR64_NOSP:%vreg218 [11504r,11552r:0)  0@11504r w=1.823169e-05
assigning %vreg218 to %RAX: AH [11504r,11552r:0)  0@11504r AL [11504r,11552r:0)  0@11504r

selectOrSplit GR64:%vreg215 [11536r,11552r:0)  0@11536r w=inf
assigning %vreg215 to %RCX: CH [11536r,11552r:0)  0@11536r CL [11536r,11552r:0)  0@11536r

selectOrSplit GR32:%vreg214 [11552r,11568r:0)  0@11552r w=inf
assigning %vreg214 to %EAX: AH [11552r,11568r:0)  0@11552r AL [11552r,11568r:0)  0@11552r

selectOrSplit GR32:%vreg209 [11584r,11616r:0)[11616r,11648r:1)  0@11584r 1@11616r w=inf
assigning %vreg209 to %EAX: AH [11584r,11616r:0)[11616r,11648r:1)  0@11584r 1@11616r AL [11584r,11616r:0)[11616r,11648r:1)  0@11584r 1@11616r

selectOrSplit GR32:%vreg203 [11664r,11696r:0)[11696r,11712r:1)  0@11664r 1@11696r w=inf
assigning %vreg203 to %EAX: AH [11664r,11696r:0)[11696r,11712r:1)  0@11664r 1@11696r AL [11664r,11696r:0)[11696r,11712r:1)  0@11664r 1@11696r

selectOrSplit GR32:%vreg199 [11728r,11760r:0)[11760r,11776r:1)  0@11728r 1@11760r w=inf
assigning %vreg199 to %EAX: AH [11728r,11760r:0)[11760r,11776r:1)  0@11728r 1@11760r AL [11728r,11760r:0)[11760r,11776r:1)  0@11728r 1@11760r

selectOrSplit GR32:%vreg196 [11792r,11808r:0)  0@11792r w=inf
assigning %vreg196 to %EAX: AH [11792r,11808r:0)  0@11792r AL [11792r,11808r:0)  0@11792r

selectOrSplit GR32:%vreg222 [11888r,11904r:0)  0@11888r w=inf
assigning %vreg222 to %EAX: AH [11888r,11904r:0)  0@11888r AL [11888r,11904r:0)  0@11888r

selectOrSplit GR32:%vreg276 [11952r,11968r:0)  0@11952r w=inf
assigning %vreg276 to %EAX: AH [11952r,11968r:0)  0@11952r AL [11952r,11968r:0)  0@11952r

selectOrSplit GR64_NOSP:%vreg273 [12016r,12064r:0)  0@12016r w=4.557921e-06
assigning %vreg273 to %RAX: AH [12016r,12064r:0)  0@12016r AL [12016r,12064r:0)  0@12016r

selectOrSplit GR64:%vreg270 [12048r,12064r:0)  0@12048r w=inf
assigning %vreg270 to %RCX: CH [12048r,12064r:0)  0@12048r CL [12048r,12064r:0)  0@12048r

selectOrSplit GR32:%vreg269 [12064r,12080r:0)  0@12064r w=inf
assigning %vreg269 to %EAX: AH [12064r,12080r:0)  0@12064r AL [12064r,12080r:0)  0@12064r

selectOrSplit GR32:%vreg264 [12096r,12128r:0)[12128r,12160r:1)  0@12096r 1@12128r w=inf
assigning %vreg264 to %EAX: AH [12096r,12128r:0)[12128r,12160r:1)  0@12096r 1@12128r AL [12096r,12128r:0)[12128r,12160r:1)  0@12096r 1@12128r

selectOrSplit GR32:%vreg258 [12176r,12208r:0)[12208r,12224r:1)  0@12176r 1@12208r w=inf
assigning %vreg258 to %EAX: AH [12176r,12208r:0)[12208r,12224r:1)  0@12176r 1@12208r AL [12176r,12208r:0)[12208r,12224r:1)  0@12176r 1@12208r

selectOrSplit GR32:%vreg254 [12240r,12272r:0)[12272r,12288r:1)  0@12240r 1@12272r w=inf
assigning %vreg254 to %EAX: AH [12240r,12272r:0)[12272r,12288r:1)  0@12240r 1@12272r AL [12240r,12272r:0)[12272r,12288r:1)  0@12240r 1@12272r

selectOrSplit GR32:%vreg249 [12304r,12336r:0)[12336r,12352r:1)  0@12304r 1@12336r w=inf
assigning %vreg249 to %EAX: AH [12304r,12336r:0)[12336r,12352r:1)  0@12304r 1@12336r AL [12304r,12336r:0)[12336r,12352r:1)  0@12304r 1@12336r

selectOrSplit GR64_NOSP:%vreg246 [12368r,12416r:0)  0@12368r w=4.557921e-06
assigning %vreg246 to %RAX: AH [12368r,12416r:0)  0@12368r AL [12368r,12416r:0)  0@12368r

selectOrSplit GR64:%vreg243 [12400r,12416r:0)  0@12400r w=inf
assigning %vreg243 to %RCX: CH [12400r,12416r:0)  0@12400r CL [12400r,12416r:0)  0@12400r

selectOrSplit GR32:%vreg242 [12416r,12432r:0)  0@12416r w=inf
assigning %vreg242 to %EAX: AH [12416r,12432r:0)  0@12416r AL [12416r,12432r:0)  0@12416r

selectOrSplit GR32:%vreg237 [12448r,12480r:0)[12480r,12512r:1)  0@12448r 1@12480r w=inf
assigning %vreg237 to %EAX: AH [12448r,12480r:0)[12480r,12512r:1)  0@12448r 1@12480r AL [12448r,12480r:0)[12480r,12512r:1)  0@12448r 1@12480r

selectOrSplit GR32:%vreg233 [12512r,12528r:0)  0@12512r w=inf
assigning %vreg233 to %EAX: AH [12512r,12528r:0)  0@12512r AL [12512r,12528r:0)  0@12512r

selectOrSplit GR32:%vreg229 [12544r,12576r:0)[12576r,12592r:1)  0@12544r 1@12576r w=inf
assigning %vreg229 to %EAX: AH [12544r,12576r:0)[12576r,12592r:1)  0@12544r 1@12576r AL [12544r,12576r:0)[12576r,12592r:1)  0@12544r 1@12576r

selectOrSplit GR32:%vreg225 [12608r,12640r:0)[12640r,12656r:1)  0@12608r 1@12640r w=inf
assigning %vreg225 to %EAX: AH [12608r,12640r:0)[12640r,12656r:1)  0@12608r 1@12640r AL [12608r,12640r:0)[12640r,12656r:1)  0@12608r 1@12640r

selectOrSplit GR64:%vreg307 [12704r,12720r:0)  0@12704r w=inf
assigning %vreg307 to %RAX: AH [12704r,12720r:0)  0@12704r AL [12704r,12720r:0)  0@12704r

selectOrSplit GR64:%vreg306 [12720r,12736r:0)  0@12720r w=inf
assigning %vreg306 to %RAX: AH [12720r,12736r:0)  0@12720r AL [12720r,12736r:0)  0@12720r

selectOrSplit GR32:%vreg304 [12736r,12752r:0)  0@12736r w=inf
assigning %vreg304 to %EAX: AH [12736r,12752r:0)  0@12736r AL [12736r,12752r:0)  0@12736r

selectOrSplit GR32:%vreg294 [12768r,12800r:2)[12800r,12864r:0)[12864r,12880r:1)  0@12800r 1@12864r 2@12768r w=4.322581e-03
assigning %vreg294 to %EAX: AH [12768r,12800r:2)[12800r,12864r:0)[12864r,12880r:1)  0@12800r 1@12864r 2@12768r AL [12768r,12800r:2)[12800r,12864r:0)[12864r,12880r:1)  0@12800r 1@12864r 2@12768r

selectOrSplit GR64:%vreg297 [12816r,12832r:0)  0@12816r w=inf
assigning %vreg297 to %RCX: CH [12816r,12832r:0)  0@12816r CL [12816r,12832r:0)  0@12816r

selectOrSplit GR64:%vreg296 [12832r,12880r:0)  0@12832r w=2.470047e-03
assigning %vreg296 to %RCX: CH [12832r,12880r:0)  0@12832r CL [12832r,12880r:0)  0@12832r

selectOrSplit GR64:%vreg289 [12896r,12912r:0)  0@12896r w=inf
assigning %vreg289 to %RAX: AH [12896r,12912r:0)  0@12896r AL [12896r,12912r:0)  0@12896r

selectOrSplit GR64:%vreg288 [12912r,12928r:0)  0@12912r w=inf
assigning %vreg288 to %RAX: AH [12912r,12928r:0)  0@12912r AL [12912r,12928r:0)  0@12912r

selectOrSplit GR32:%vreg286 [12928r,12944r:0)  0@12928r w=inf
assigning %vreg286 to %EAX: AH [12928r,12944r:0)  0@12928r AL [12928r,12944r:0)  0@12928r

selectOrSplit GR64:%vreg315 [12992r,13008r:0)  0@12992r w=inf
assigning %vreg315 to %RAX: AH [12992r,13008r:0)  0@12992r AL [12992r,13008r:0)  0@12992r

selectOrSplit GR64:%vreg314 [13008r,13072r:0)  0@13008r w=1.192364e-03
assigning %vreg314 to %RAX: AH [13008r,13072r:0)  0@13008r AL [13008r,13072r:0)  0@13008r

selectOrSplit GR32:%vreg311 [13024r,13056r:0)[13056r,13072r:1)  0@13024r 1@13056r w=inf
assigning %vreg311 to %ECX: CH [13024r,13056r:0)[13056r,13072r:1)  0@13024r 1@13056r CL [13024r,13056r:0)[13056r,13072r:1)  0@13024r 1@13056r

selectOrSplit GR32:%vreg355 [13104r,13136r:0)  0@13104r w=1.707686e-03
assigning %vreg355 to %EAX: AH [13104r,13136r:0)  0@13104r AL [13104r,13136r:0)  0@13104r

selectOrSplit GR64:%vreg354 [13120r,13136r:0)  0@13120r w=inf
assigning %vreg354 to %RCX: CH [13120r,13136r:0)  0@13120r CL [13120r,13136r:0)  0@13120r

selectOrSplit GR8:%vreg351 [13152r,13184r:0)  0@13152r w=1.707686e-03
assigning %vreg351 to %AL: AL [13152r,13184r:0)  0@13152r

selectOrSplit GR64:%vreg350 [13168r,13184r:0)  0@13168r w=inf
assigning %vreg350 to %RCX: CH [13168r,13184r:0)  0@13168r CL [13168r,13184r:0)  0@13168r

selectOrSplit GR32:%vreg347 [13200r,13232r:0)  0@13200r w=1.707686e-03
assigning %vreg347 to %EAX: AH [13200r,13232r:0)  0@13200r AL [13200r,13232r:0)  0@13200r

selectOrSplit GR64:%vreg346 [13216r,13232r:0)  0@13216r w=inf
assigning %vreg346 to %RCX: CH [13216r,13232r:0)  0@13216r CL [13216r,13232r:0)  0@13216r

selectOrSplit GR32:%vreg343 [13248r,13280r:0)  0@13248r w=1.707686e-03
assigning %vreg343 to %EAX: AH [13248r,13280r:0)  0@13248r AL [13248r,13280r:0)  0@13248r

selectOrSplit GR64:%vreg342 [13264r,13280r:0)  0@13264r w=inf
assigning %vreg342 to %RCX: CH [13264r,13280r:0)  0@13264r CL [13264r,13280r:0)  0@13264r

selectOrSplit GR32:%vreg339 [13296r,13328r:0)  0@13296r w=1.707686e-03
assigning %vreg339 to %EAX: AH [13296r,13328r:0)  0@13296r AL [13296r,13328r:0)  0@13296r

selectOrSplit GR64:%vreg338 [13312r,13328r:0)  0@13312r w=inf
assigning %vreg338 to %RCX: CH [13312r,13328r:0)  0@13312r CL [13312r,13328r:0)  0@13312r

selectOrSplit GR64:%vreg335 [13344r,13376r:0)  0@13344r w=1.707686e-03
assigning %vreg335 to %RAX: AH [13344r,13376r:0)  0@13344r AL [13344r,13376r:0)  0@13344r

selectOrSplit GR64:%vreg334 [13360r,13376r:0)  0@13360r w=inf
assigning %vreg334 to %RCX: CH [13360r,13376r:0)  0@13360r CL [13360r,13376r:0)  0@13360r

selectOrSplit GR32:%vreg331 [13392r,13424r:0)  0@13392r w=1.707686e-03
assigning %vreg331 to %EAX: AH [13392r,13424r:0)  0@13392r AL [13392r,13424r:0)  0@13392r

selectOrSplit GR64:%vreg330 [13408r,13424r:0)  0@13408r w=inf
assigning %vreg330 to %RCX: CH [13408r,13424r:0)  0@13408r CL [13408r,13424r:0)  0@13408r

selectOrSplit GR64:%vreg327 [13440r,13488r:0)  0@13440r w=1.646698e-03
assigning %vreg327 to %RAX: AH [13440r,13488r:0)  0@13440r AL [13440r,13488r:0)  0@13440r

selectOrSplit GR64:%vreg326 [13456r,13472r:0)  0@13456r w=inf
assigning %vreg326 to %RCX: CH [13456r,13472r:0)  0@13456r CL [13456r,13472r:0)  0@13456r

selectOrSplit GR64:%vreg325 [13472r,13488r:0)  0@13472r w=inf
assigning %vreg325 to %RCX: CH [13472r,13488r:0)  0@13472r CL [13472r,13488r:0)  0@13472r

selectOrSplit GR32:%vreg321 [13504r,13552r:0)  0@13504r w=1.646698e-03
assigning %vreg321 to %EAX: AH [13504r,13552r:0)  0@13504r AL [13504r,13552r:0)  0@13504r

selectOrSplit GR64:%vreg320 [13520r,13536r:0)  0@13520r w=inf
assigning %vreg320 to %RCX: CH [13520r,13536r:0)  0@13520r CL [13520r,13536r:0)  0@13520r

selectOrSplit GR64:%vreg319 [13536r,13552r:0)  0@13536r w=inf
assigning %vreg319 to %RCX: CH [13536r,13552r:0)  0@13536r CL [13536r,13552r:0)  0@13536r

********** STACK TRANSFORMATION METADATA **********
********** Function: unRLE_obuf_to_output_FAST
********** REGISTER MAP **********
[%vreg1 -> %RBX] GR64
[%vreg4 -> %RAX] GR64
[%vreg6 -> %RDI] GR64
[%vreg7 -> %RSI] GR64
[%vreg10 -> %EAX] GR32
[%vreg13 -> %RAX] GR64
[%vreg15 -> %EAX] GR32
[%vreg18 -> %EAX] GR32
[%vreg20 -> %RAX] GR64
[%vreg21 -> %RAX] GR64
[%vreg24 -> %RAX] GR64
[%vreg26 -> %RAX] GR64
[%vreg27 -> %RAX] GR64
[%vreg30 -> %EAX] GR32
[%vreg31 -> %RAX] GR64
[%vreg34 -> %RAX] GR64
[%vreg35 -> %RAX] GR64
[%vreg38 -> %EAX] GR32
[%vreg39 -> %RAX] GR64
[%vreg42 -> %EAX] GR32
[%vreg43 -> %RAX] GR64
[%vreg46 -> %EAX] GR32
[%vreg47 -> %RAX] GR64
[%vreg50 -> %AL] GR8
[%vreg51 -> %RAX] GR64
[%vreg54 -> %EAX] GR32
[%vreg55 -> %RAX] GR64
[%vreg61 -> %EAX] GR32
[%vreg65 -> %RAX] GR64
[%vreg69 -> %EAX] GR32
[%vreg74 -> %EAX] GR32
[%vreg78 -> %RCX] GR64_NOSP
[%vreg81 -> %ECX] GR32
[%vreg83 -> %EDX] GR32
[%vreg92 -> %RCX] GR64
[%vreg93 -> %AL] GR8
[%vreg97 -> %EAX] GR32
[%vreg101 -> %RAX] GR64
[%vreg106 -> %EAX] GR32
[%vreg110 -> %RCX] GR64_NOSP
[%vreg113 -> %ECX] GR32
[%vreg115 -> %EDX] GR32
[%vreg124 -> %RCX] GR64
[%vreg125 -> %AL] GR8
[%vreg128 -> %EAX] GR32
[%vreg131 -> %EAX] GR32
[%vreg135 -> %EAX] GR32
[%vreg138 -> %EAX] GR32
[%vreg142 -> %EAX] GR32
[%vreg148 -> %EAX] GR32
[%vreg153 -> %EAX] GR32
[%vreg154 -> %RCX] GR64
[%vreg157 -> %RAX] GR64_NOSP
[%vreg161 -> %EAX] GR32
[%vreg164 -> %EAX] GR32
[%vreg167 -> %EAX] GR32
[%vreg170 -> %EAX] GR32
[%vreg174 -> %EAX] GR32
[%vreg180 -> %EAX] GR32
[%vreg185 -> %EAX] GR32
[%vreg186 -> %RCX] GR64
[%vreg189 -> %RAX] GR64_NOSP
[%vreg193 -> %EAX] GR32
[%vreg196 -> %EAX] GR32
[%vreg199 -> %EAX] GR32
[%vreg203 -> %EAX] GR32
[%vreg209 -> %EAX] GR32
[%vreg214 -> %EAX] GR32
[%vreg215 -> %RCX] GR64
[%vreg218 -> %RAX] GR64_NOSP
[%vreg222 -> %EAX] GR32
[%vreg225 -> %EAX] GR32
[%vreg229 -> %EAX] GR32
[%vreg233 -> %EAX] GR32
[%vreg237 -> %EAX] GR32
[%vreg242 -> %EAX] GR32
[%vreg243 -> %RCX] GR64
[%vreg246 -> %RAX] GR64_NOSP
[%vreg249 -> %EAX] GR32
[%vreg254 -> %EAX] GR32
[%vreg258 -> %EAX] GR32
[%vreg264 -> %EAX] GR32
[%vreg269 -> %EAX] GR32
[%vreg270 -> %RCX] GR64
[%vreg273 -> %RAX] GR64_NOSP
[%vreg276 -> %EAX] GR32
[%vreg279 -> %EAX] GR32
[%vreg282 -> %EAX] GR32
[%vreg286 -> %EAX] GR32
[%vreg288 -> %RAX] GR64
[%vreg289 -> %RAX] GR64
[%vreg294 -> %EAX] GR32
[%vreg296 -> %RCX] GR64
[%vreg297 -> %RCX] GR64
[%vreg304 -> %EAX] GR32
[%vreg306 -> %RAX] GR64
[%vreg307 -> %RAX] GR64
[%vreg311 -> %ECX] GR32
[%vreg314 -> %RAX] GR64
[%vreg315 -> %RAX] GR64
[%vreg319 -> %RCX] GR64
[%vreg320 -> %RCX] GR64
[%vreg321 -> %EAX] GR32
[%vreg325 -> %RCX] GR64
[%vreg326 -> %RCX] GR64
[%vreg327 -> %RAX] GR64
[%vreg330 -> %RCX] GR64
[%vreg331 -> %EAX] GR32
[%vreg334 -> %RCX] GR64
[%vreg335 -> %RAX] GR64
[%vreg338 -> %RCX] GR64
[%vreg339 -> %EAX] GR32
[%vreg342 -> %RCX] GR64
[%vreg343 -> %EAX] GR32
[%vreg346 -> %RCX] GR64
[%vreg347 -> %EAX] GR32
[%vreg350 -> %RCX] GR64
[%vreg351 -> %AL] GR8
[%vreg354 -> %RCX] GR64
[%vreg355 -> %EAX] GR32
[%vreg359 -> %RAX] GR64
[%vreg360 -> %RAX] GR64
[%vreg363 -> %RAX] GR64
[%vreg367 -> %RAX] GR64
[%vreg368 -> %RAX] GR64
[%vreg372 -> %ECX] GR32
[%vreg375 -> %RAX] GR64
[%vreg376 -> %RAX] GR64
[%vreg380 -> %ECX] GR32
[%vreg383 -> %RAX] GR64
[%vreg384 -> %RAX] GR64
[%vreg388 -> %RCX] GR64
[%vreg391 -> %RAX] GR64
[%vreg392 -> %RAX] GR64
[%vreg396 -> %ECX] GR32
[%vreg398 -> %RAX] GR64
[%vreg401 -> %RCX] GR64
[%vreg404 -> %EAX] GR32
[%vreg408 -> %RCX] GR64_NOSP
[%vreg411 -> %ECX] GR32
[%vreg413 -> %EDX] GR32
[%vreg415 -> %RDX] GR64
[%vreg420 -> %RCX] GR64
[%vreg425 -> %RAX] GR64
[%vreg429 -> %RCX] GR64
[%vreg431 -> %RCX] GR64
[%vreg432 -> %RCX] GR64
[%vreg434 -> %AL] GR8
[%vreg435 -> %RAX] GR64
[%vreg439 -> %ECX] GR32
[%vreg442 -> %RAX] GR64
[%vreg443 -> %RAX] GR64
[%vreg447 -> %ECX] GR32
[%vreg450 -> %RCX] GR64
[%vreg452 -> %EAX] GR32
[%vreg453 -> %RAX] GR64
[%vreg457 -> %ECX] GR32
[%vreg460 -> %RCX] GR64
[%vreg462 -> %EAX] GR32
[%vreg463 -> %RAX] GR64
[%vreg466 -> %RAX] GR64
[%vreg470 -> %ECX] GR32
[%vreg472 -> %RAX] GR64
[%vreg477 -> %EAX] GR32
[%vreg480 -> %RAX] GR64
[%vreg483 -> %RCX] GR64
[%vreg486 -> %EAX] GR32
[%vreg488 -> %RCX] GR64
[%vreg489 -> %RCX] GR64
[%vreg492 -> %RAX] GR64_NOSP
[%vreg494 -> %RAX] GR64
[%vreg497 -> %RCX] GR64
[%vreg501 -> %EAX] GR32
[%vreg502 -> %RAX] GR64
[%vreg504 -> %RAX] GR64
[%vreg507 -> %RAX] GR64
[%vreg511 -> %ECX] GR32
[%vreg513 -> %RAX] GR64
[%vreg516 -> %RCX] GR64
[%vreg518 -> %EAX] GR32
[%vreg520 -> %RAX] GR64_NOSP
[%vreg522 -> %RAX] GR64
[%vreg524 -> %RAX] GR64
[%vreg528 -> %ECX] GR32
[%vreg531 -> %RCX] GR64
[%vreg533 -> %EAX] GR32
[%vreg534 -> %RAX] GR64
[%vreg538 -> %ECX] GR32
[%vreg540 -> %RAX] GR64
[%vreg546 -> %ECX] GR32
[%vreg551 -> %ECX] GR32
[%vreg552 -> %EAX] GR32
[%vreg554 -> %RDX] GR64
[%vreg558 -> %ESI] GR32
[%vreg560 -> %RDX] GR64
[%vreg564 -> %RCX] GR64
[%vreg566 -> %EAX] GR32
[%vreg569 -> %RAX] GR64
[%vreg573 -> %ECX] GR32
[%vreg575 -> %RAX] GR64
[%vreg580 -> %EAX] GR32
[%vreg583 -> %RAX] GR64
[%vreg586 -> %RCX] GR64
[%vreg589 -> %EAX] GR32
[%vreg591 -> %RCX] GR64
[%vreg592 -> %RCX] GR64
[%vreg595 -> %RAX] GR64_NOSP
[%vreg597 -> %RAX] GR64
[%vreg599 -> %RAX] GR64
[%vreg602 -> %RAX] GR64
[%vreg606 -> %ECX] GR32
[%vreg608 -> %RAX] GR64
[%vreg611 -> %RCX] GR64
[%vreg613 -> %EAX] GR32
[%vreg615 -> %RAX] GR64_NOSP
[%vreg617 -> %RAX] GR64
[%vreg619 -> %RAX] GR64
[%vreg623 -> %ECX] GR32
[%vreg626 -> %RCX] GR64
[%vreg628 -> %EAX] GR32
[%vreg629 -> %RAX] GR64
[%vreg633 -> %ECX] GR32
[%vreg635 -> %RAX] GR64
[%vreg641 -> %ECX] GR32
[%vreg646 -> %ECX] GR32
[%vreg647 -> %EAX] GR32
[%vreg649 -> %RDX] GR64
[%vreg653 -> %ESI] GR32
[%vreg655 -> %RDX] GR64
[%vreg659 -> %RCX] GR64
[%vreg661 -> %EAX] GR32
[%vreg664 -> %RAX] GR64
[%vreg668 -> %ECX] GR32
[%vreg670 -> %RAX] GR64
[%vreg675 -> %EAX] GR32
[%vreg678 -> %RAX] GR64
[%vreg681 -> %RCX] GR64
[%vreg684 -> %EAX] GR32
[%vreg686 -> %RCX] GR64
[%vreg687 -> %RCX] GR64
[%vreg690 -> %RAX] GR64_NOSP
[%vreg692 -> %RAX] GR64
[%vreg694 -> %RAX] GR64
[%vreg697 -> %RAX] GR64
[%vreg701 -> %ECX] GR32
[%vreg703 -> %RAX] GR64
[%vreg706 -> %RCX] GR64
[%vreg708 -> %EAX] GR32
[%vreg710 -> %RAX] GR64_NOSP
[%vreg712 -> %RAX] GR64
[%vreg714 -> %RAX] GR64
[%vreg718 -> %ECX] GR32
[%vreg721 -> %RCX] GR64
[%vreg723 -> %EAX] GR32
[%vreg724 -> %RAX] GR64
[%vreg728 -> %ECX] GR32
[%vreg730 -> %RAX] GR64
[%vreg736 -> %ECX] GR32
[%vreg741 -> %ECX] GR32
[%vreg742 -> %EAX] GR32
[%vreg744 -> %RDX] GR64
[%vreg748 -> %ESI] GR32
[%vreg750 -> %RDX] GR64
[%vreg754 -> %RCX] GR64
[%vreg756 -> %EAX] GR32
[%vreg759 -> %RAX] GR64
[%vreg763 -> %ECX] GR32
[%vreg765 -> %RAX] GR64
[%vreg770 -> %EAX] GR32
[%vreg773 -> %RAX] GR64
[%vreg776 -> %RCX] GR64
[%vreg779 -> %EAX] GR32
[%vreg781 -> %RCX] GR64
[%vreg782 -> %RCX] GR64
[%vreg785 -> %RAX] GR64_NOSP
[%vreg787 -> %RAX] GR64
[%vreg790 -> %RAX] GR64
[%vreg794 -> %ECX] GR32
[%vreg796 -> %RAX] GR64
[%vreg799 -> %RCX] GR64
[%vreg801 -> %EAX] GR32
[%vreg803 -> %RAX] GR64_NOSP
[%vreg805 -> %RAX] GR64
[%vreg807 -> %RAX] GR64
[%vreg810 -> %RAX] GR64
[%vreg814 -> %ECX] GR32
[%vreg816 -> %RAX] GR64
[%vreg819 -> %RCX] GR64
[%vreg821 -> %EAX] GR32
[%vreg825 -> %EAX] GR32
[%vreg828 -> %RAX] GR64
[%vreg831 -> %RCX] GR64
[%vreg834 -> %EAX] GR32
[%vreg836 -> %RCX] GR64
[%vreg837 -> %RCX] GR64
[%vreg840 -> %RAX] GR64_NOSP
[%vreg842 -> %RAX] GR64
[%vreg845 -> %RCX] GR64
[%vreg847 -> %EAX] GR32
[%vreg853 -> %ECX] GR32
[%vreg855 -> %RAX] GR64
[%vreg861 -> %ECX] GR32
[%vreg866 -> %ECX] GR32
[%vreg867 -> %EAX] GR32
[%vreg869 -> %RDX] GR64
[%vreg873 -> %ESI] GR32
[%vreg875 -> %RDX] GR64
[%vreg878 -> %RAX] GR64
[%vreg882 -> %ECX] GR32
[%vreg884 -> %RAX] GR64
[%vreg887 -> %RCX] GR64
[%vreg889 -> %EAX] GR32
[%vreg891 -> %RAX] GR64_NOSP
[%vreg893 -> %RAX] GR64
[%vreg895 -> %RAX] GR64
[%vreg899 -> %ECX] GR32
[%vreg901 -> %RAX] GR64
[%vreg906 -> %EAX] GR32
[%vreg907 -> %RCX] GR64
[%vreg910 -> %ECX] GR32
[%vreg913 -> %RDX] GR64
[%vreg917 -> %ESI] GR32
[%vreg919 -> %RDX] GR64
[%vreg922 -> %RCX] GR64
[%vreg924 -> %EAX] GR32
[%vreg927 -> %RCX] GR64
[%vreg929 -> %EAX] GR32
[%vreg932 -> %RCX] GR64
[%vreg934 -> %EAX] GR32
[%vreg936 -> %AL] GR8
[%vreg938 -> %RDI] GR64
[%vreg939 -> %RSI] GR64


Stackmap 0:
  STACKMAP 0, 0, 0, <fi#12>, 0, 0, <fi#3>, 0, 0, <fi#7>, 0, 0, <fi#6>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#9>, 0, 0, <fi#8>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, %vreg1, 0, <fi#1>, 0, 0, <fi#13>, 0, 0, <fi#14>, 0, ...; mem:LD8[FixedStack12](align=4) LD8[FixedStack3](align=4) LD8[FixedStack7](align=4) LD8[FixedStack6](align=4) LD8[FixedStack4](align=1) LD8[FixedStack5](align=4) LD8[FixedStack9](align=4) LD8[FixedStack8] LD8[FixedStack11](align=4) LD8[FixedStack10] LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1] LD8[FixedStack13](align=4) LD8[FixedStack14](align=4) GR64:%vreg1

i32* %avail_out_INIT: in stack slot 12 (size: 4)
i32* %c_calculatedBlockCRC: in stack slot 3 (size: 4)
i32* %c_k0: in stack slot 7 (size: 4)
i32* %c_nblock_used: in stack slot 6 (size: 4)
i8* %c_state_out_ch: in stack slot 4 (size: 1)
i32* %c_state_out_len: in stack slot 5 (size: 4)
i32* %c_tPos: in stack slot 9 (size: 4)
i32** %c_tt: in stack slot 8 (size: 8)
i32* %cs_avail_out: in stack slot 11 (size: 4)
i8** %cs_next_out: in stack slot 10 (size: 8)
i8* %k1: in stack slot 2 (size: 1)
i8* %retval: in stack slot 0 (size: 1)
%struct.DState* %s: in register %RBX (vreg 1)
%struct.DState** %s.addr: in stack slot 1 (size: 8)
i32* %s_save_nblockPP: in stack slot 13 (size: 4)
i32* %total_out_lo32_old: in stack slot 14 (size: 4)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=1)

i8* %retval: in stack slot 0 (size: 1)

Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, 0, <fi#12>, 0, 0, <fi#3>, 0, 0, <fi#7>, 0, 0, <fi#6>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#9>, 0, 0, <fi#8>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, %vreg1, 0, <fi#1>, 0, 0, <fi#13>, 0, 0, <fi#14>, 0, ...; mem:LD8[FixedStack12](align=4) LD8[FixedStack3](align=4) LD8[FixedStack7](align=4) LD8[FixedStack6](align=4) LD8[FixedStack4](align=1) LD8[FixedStack5](align=4) LD8[FixedStack9](align=4) LD8[FixedStack8] LD8[FixedStack11](align=4) LD8[FixedStack10] LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1] LD8[FixedStack13](align=4) LD8[FixedStack14](align=4) GR64:%vreg1
  -> Call instruction SlotIndex 144B, searching vregs 0 -> 940 and stack slots -1 -> 15

  STACKMAP 1, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=1)
  -> Call instruction SlotIndex 13712B, searching vregs 0 -> 940 and stack slots -1 -> 15

********** REWRITE VIRTUAL REGISTERS **********
********** Function: unRLE_obuf_to_output_FAST
********** REGISTER MAP **********
[%vreg1 -> %RBX] GR64
[%vreg4 -> %RAX] GR64
[%vreg6 -> %RDI] GR64
[%vreg7 -> %RSI] GR64
[%vreg10 -> %EAX] GR32
[%vreg13 -> %RAX] GR64
[%vreg15 -> %EAX] GR32
[%vreg18 -> %EAX] GR32
[%vreg20 -> %RAX] GR64
[%vreg21 -> %RAX] GR64
[%vreg24 -> %RAX] GR64
[%vreg26 -> %RAX] GR64
[%vreg27 -> %RAX] GR64
[%vreg30 -> %EAX] GR32
[%vreg31 -> %RAX] GR64
[%vreg34 -> %RAX] GR64
[%vreg35 -> %RAX] GR64
[%vreg38 -> %EAX] GR32
[%vreg39 -> %RAX] GR64
[%vreg42 -> %EAX] GR32
[%vreg43 -> %RAX] GR64
[%vreg46 -> %EAX] GR32
[%vreg47 -> %RAX] GR64
[%vreg50 -> %AL] GR8
[%vreg51 -> %RAX] GR64
[%vreg54 -> %EAX] GR32
[%vreg55 -> %RAX] GR64
[%vreg61 -> %EAX] GR32
[%vreg65 -> %RAX] GR64
[%vreg69 -> %EAX] GR32
[%vreg74 -> %EAX] GR32
[%vreg78 -> %RCX] GR64_NOSP
[%vreg81 -> %ECX] GR32
[%vreg83 -> %EDX] GR32
[%vreg92 -> %RCX] GR64
[%vreg93 -> %AL] GR8
[%vreg97 -> %EAX] GR32
[%vreg101 -> %RAX] GR64
[%vreg106 -> %EAX] GR32
[%vreg110 -> %RCX] GR64_NOSP
[%vreg113 -> %ECX] GR32
[%vreg115 -> %EDX] GR32
[%vreg124 -> %RCX] GR64
[%vreg125 -> %AL] GR8
[%vreg128 -> %EAX] GR32
[%vreg131 -> %EAX] GR32
[%vreg135 -> %EAX] GR32
[%vreg138 -> %EAX] GR32
[%vreg142 -> %EAX] GR32
[%vreg148 -> %EAX] GR32
[%vreg153 -> %EAX] GR32
[%vreg154 -> %RCX] GR64
[%vreg157 -> %RAX] GR64_NOSP
[%vreg161 -> %EAX] GR32
[%vreg164 -> %EAX] GR32
[%vreg167 -> %EAX] GR32
[%vreg170 -> %EAX] GR32
[%vreg174 -> %EAX] GR32
[%vreg180 -> %EAX] GR32
[%vreg185 -> %EAX] GR32
[%vreg186 -> %RCX] GR64
[%vreg189 -> %RAX] GR64_NOSP
[%vreg193 -> %EAX] GR32
[%vreg196 -> %EAX] GR32
[%vreg199 -> %EAX] GR32
[%vreg203 -> %EAX] GR32
[%vreg209 -> %EAX] GR32
[%vreg214 -> %EAX] GR32
[%vreg215 -> %RCX] GR64
[%vreg218 -> %RAX] GR64_NOSP
[%vreg222 -> %EAX] GR32
[%vreg225 -> %EAX] GR32
[%vreg229 -> %EAX] GR32
[%vreg233 -> %EAX] GR32
[%vreg237 -> %EAX] GR32
[%vreg242 -> %EAX] GR32
[%vreg243 -> %RCX] GR64
[%vreg246 -> %RAX] GR64_NOSP
[%vreg249 -> %EAX] GR32
[%vreg254 -> %EAX] GR32
[%vreg258 -> %EAX] GR32
[%vreg264 -> %EAX] GR32
[%vreg269 -> %EAX] GR32
[%vreg270 -> %RCX] GR64
[%vreg273 -> %RAX] GR64_NOSP
[%vreg276 -> %EAX] GR32
[%vreg279 -> %EAX] GR32
[%vreg282 -> %EAX] GR32
[%vreg286 -> %EAX] GR32
[%vreg288 -> %RAX] GR64
[%vreg289 -> %RAX] GR64
[%vreg294 -> %EAX] GR32
[%vreg296 -> %RCX] GR64
[%vreg297 -> %RCX] GR64
[%vreg304 -> %EAX] GR32
[%vreg306 -> %RAX] GR64
[%vreg307 -> %RAX] GR64
[%vreg311 -> %ECX] GR32
[%vreg314 -> %RAX] GR64
[%vreg315 -> %RAX] GR64
[%vreg319 -> %RCX] GR64
[%vreg320 -> %RCX] GR64
[%vreg321 -> %EAX] GR32
[%vreg325 -> %RCX] GR64
[%vreg326 -> %RCX] GR64
[%vreg327 -> %RAX] GR64
[%vreg330 -> %RCX] GR64
[%vreg331 -> %EAX] GR32
[%vreg334 -> %RCX] GR64
[%vreg335 -> %RAX] GR64
[%vreg338 -> %RCX] GR64
[%vreg339 -> %EAX] GR32
[%vreg342 -> %RCX] GR64
[%vreg343 -> %EAX] GR32
[%vreg346 -> %RCX] GR64
[%vreg347 -> %EAX] GR32
[%vreg350 -> %RCX] GR64
[%vreg351 -> %AL] GR8
[%vreg354 -> %RCX] GR64
[%vreg355 -> %EAX] GR32
[%vreg359 -> %RAX] GR64
[%vreg360 -> %RAX] GR64
[%vreg363 -> %RAX] GR64
[%vreg367 -> %RAX] GR64
[%vreg368 -> %RAX] GR64
[%vreg372 -> %ECX] GR32
[%vreg375 -> %RAX] GR64
[%vreg376 -> %RAX] GR64
[%vreg380 -> %ECX] GR32
[%vreg383 -> %RAX] GR64
[%vreg384 -> %RAX] GR64
[%vreg388 -> %RCX] GR64
[%vreg391 -> %RAX] GR64
[%vreg392 -> %RAX] GR64
[%vreg396 -> %ECX] GR32
[%vreg398 -> %RAX] GR64
[%vreg401 -> %RCX] GR64
[%vreg404 -> %EAX] GR32
[%vreg408 -> %RCX] GR64_NOSP
[%vreg411 -> %ECX] GR32
[%vreg413 -> %EDX] GR32
[%vreg415 -> %RDX] GR64
[%vreg420 -> %RCX] GR64
[%vreg425 -> %RAX] GR64
[%vreg429 -> %RCX] GR64
[%vreg431 -> %RCX] GR64
[%vreg432 -> %RCX] GR64
[%vreg434 -> %AL] GR8
[%vreg435 -> %RAX] GR64
[%vreg439 -> %ECX] GR32
[%vreg442 -> %RAX] GR64
[%vreg443 -> %RAX] GR64
[%vreg447 -> %ECX] GR32
[%vreg450 -> %RCX] GR64
[%vreg452 -> %EAX] GR32
[%vreg453 -> %RAX] GR64
[%vreg457 -> %ECX] GR32
[%vreg460 -> %RCX] GR64
[%vreg462 -> %EAX] GR32
[%vreg463 -> %RAX] GR64
[%vreg466 -> %RAX] GR64
[%vreg470 -> %ECX] GR32
[%vreg472 -> %RAX] GR64
[%vreg477 -> %EAX] GR32
[%vreg480 -> %RAX] GR64
[%vreg483 -> %RCX] GR64
[%vreg486 -> %EAX] GR32
[%vreg488 -> %RCX] GR64
[%vreg489 -> %RCX] GR64
[%vreg492 -> %RAX] GR64_NOSP
[%vreg494 -> %RAX] GR64
[%vreg497 -> %RCX] GR64
[%vreg501 -> %EAX] GR32
[%vreg502 -> %RAX] GR64
[%vreg504 -> %RAX] GR64
[%vreg507 -> %RAX] GR64
[%vreg511 -> %ECX] GR32
[%vreg513 -> %RAX] GR64
[%vreg516 -> %RCX] GR64
[%vreg518 -> %EAX] GR32
[%vreg520 -> %RAX] GR64_NOSP
[%vreg522 -> %RAX] GR64
[%vreg524 -> %RAX] GR64
[%vreg528 -> %ECX] GR32
[%vreg531 -> %RCX] GR64
[%vreg533 -> %EAX] GR32
[%vreg534 -> %RAX] GR64
[%vreg538 -> %ECX] GR32
[%vreg540 -> %RAX] GR64
[%vreg546 -> %ECX] GR32
[%vreg551 -> %ECX] GR32
[%vreg552 -> %EAX] GR32
[%vreg554 -> %RDX] GR64
[%vreg558 -> %ESI] GR32
[%vreg560 -> %RDX] GR64
[%vreg564 -> %RCX] GR64
[%vreg566 -> %EAX] GR32
[%vreg569 -> %RAX] GR64
[%vreg573 -> %ECX] GR32
[%vreg575 -> %RAX] GR64
[%vreg580 -> %EAX] GR32
[%vreg583 -> %RAX] GR64
[%vreg586 -> %RCX] GR64
[%vreg589 -> %EAX] GR32
[%vreg591 -> %RCX] GR64
[%vreg592 -> %RCX] GR64
[%vreg595 -> %RAX] GR64_NOSP
[%vreg597 -> %RAX] GR64
[%vreg599 -> %RAX] GR64
[%vreg602 -> %RAX] GR64
[%vreg606 -> %ECX] GR32
[%vreg608 -> %RAX] GR64
[%vreg611 -> %RCX] GR64
[%vreg613 -> %EAX] GR32
[%vreg615 -> %RAX] GR64_NOSP
[%vreg617 -> %RAX] GR64
[%vreg619 -> %RAX] GR64
[%vreg623 -> %ECX] GR32
[%vreg626 -> %RCX] GR64
[%vreg628 -> %EAX] GR32
[%vreg629 -> %RAX] GR64
[%vreg633 -> %ECX] GR32
[%vreg635 -> %RAX] GR64
[%vreg641 -> %ECX] GR32
[%vreg646 -> %ECX] GR32
[%vreg647 -> %EAX] GR32
[%vreg649 -> %RDX] GR64
[%vreg653 -> %ESI] GR32
[%vreg655 -> %RDX] GR64
[%vreg659 -> %RCX] GR64
[%vreg661 -> %EAX] GR32
[%vreg664 -> %RAX] GR64
[%vreg668 -> %ECX] GR32
[%vreg670 -> %RAX] GR64
[%vreg675 -> %EAX] GR32
[%vreg678 -> %RAX] GR64
[%vreg681 -> %RCX] GR64
[%vreg684 -> %EAX] GR32
[%vreg686 -> %RCX] GR64
[%vreg687 -> %RCX] GR64
[%vreg690 -> %RAX] GR64_NOSP
[%vreg692 -> %RAX] GR64
[%vreg694 -> %RAX] GR64
[%vreg697 -> %RAX] GR64
[%vreg701 -> %ECX] GR32
[%vreg703 -> %RAX] GR64
[%vreg706 -> %RCX] GR64
[%vreg708 -> %EAX] GR32
[%vreg710 -> %RAX] GR64_NOSP
[%vreg712 -> %RAX] GR64
[%vreg714 -> %RAX] GR64
[%vreg718 -> %ECX] GR32
[%vreg721 -> %RCX] GR64
[%vreg723 -> %EAX] GR32
[%vreg724 -> %RAX] GR64
[%vreg728 -> %ECX] GR32
[%vreg730 -> %RAX] GR64
[%vreg736 -> %ECX] GR32
[%vreg741 -> %ECX] GR32
[%vreg742 -> %EAX] GR32
[%vreg744 -> %RDX] GR64
[%vreg748 -> %ESI] GR32
[%vreg750 -> %RDX] GR64
[%vreg754 -> %RCX] GR64
[%vreg756 -> %EAX] GR32
[%vreg759 -> %RAX] GR64
[%vreg763 -> %ECX] GR32
[%vreg765 -> %RAX] GR64
[%vreg770 -> %EAX] GR32
[%vreg773 -> %RAX] GR64
[%vreg776 -> %RCX] GR64
[%vreg779 -> %EAX] GR32
[%vreg781 -> %RCX] GR64
[%vreg782 -> %RCX] GR64
[%vreg785 -> %RAX] GR64_NOSP
[%vreg787 -> %RAX] GR64
[%vreg790 -> %RAX] GR64
[%vreg794 -> %ECX] GR32
[%vreg796 -> %RAX] GR64
[%vreg799 -> %RCX] GR64
[%vreg801 -> %EAX] GR32
[%vreg803 -> %RAX] GR64_NOSP
[%vreg805 -> %RAX] GR64
[%vreg807 -> %RAX] GR64
[%vreg810 -> %RAX] GR64
[%vreg814 -> %ECX] GR32
[%vreg816 -> %RAX] GR64
[%vreg819 -> %RCX] GR64
[%vreg821 -> %EAX] GR32
[%vreg825 -> %EAX] GR32
[%vreg828 -> %RAX] GR64
[%vreg831 -> %RCX] GR64
[%vreg834 -> %EAX] GR32
[%vreg836 -> %RCX] GR64
[%vreg837 -> %RCX] GR64
[%vreg840 -> %RAX] GR64_NOSP
[%vreg842 -> %RAX] GR64
[%vreg845 -> %RCX] GR64
[%vreg847 -> %EAX] GR32
[%vreg853 -> %ECX] GR32
[%vreg855 -> %RAX] GR64
[%vreg861 -> %ECX] GR32
[%vreg866 -> %ECX] GR32
[%vreg867 -> %EAX] GR32
[%vreg869 -> %RDX] GR64
[%vreg873 -> %ESI] GR32
[%vreg875 -> %RDX] GR64
[%vreg878 -> %RAX] GR64
[%vreg882 -> %ECX] GR32
[%vreg884 -> %RAX] GR64
[%vreg887 -> %RCX] GR64
[%vreg889 -> %EAX] GR32
[%vreg891 -> %RAX] GR64_NOSP
[%vreg893 -> %RAX] GR64
[%vreg895 -> %RAX] GR64
[%vreg899 -> %ECX] GR32
[%vreg901 -> %RAX] GR64
[%vreg906 -> %EAX] GR32
[%vreg907 -> %RCX] GR64
[%vreg910 -> %ECX] GR32
[%vreg913 -> %RDX] GR64
[%vreg917 -> %ESI] GR32
[%vreg919 -> %RDX] GR64
[%vreg922 -> %RCX] GR64
[%vreg924 -> %EAX] GR32
[%vreg927 -> %RCX] GR64
[%vreg929 -> %EAX] GR32
[%vreg932 -> %RCX] GR64
[%vreg934 -> %EAX] GR32
[%vreg936 -> %AL] GR8
[%vreg938 -> %RDI] GR64
[%vreg939 -> %RSI] GR64

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI
16B		%vreg1<def> = COPY %RDI; GR64:%vreg1
48B		%vreg6<def> = MOV64ri <ga:@unRLE_obuf_to_output_FAST>; GR64:%vreg6
80B		%vreg7<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg7
96B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
112B		%RDI<def> = COPY %vreg6<kill>; GR64:%vreg6
128B		%RSI<def> = COPY %vreg7<kill>; GR64:%vreg7
144B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
160B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
192B		STACKMAP 0, 0, 0, <fi#12>, 0, 0, <fi#3>, 0, 0, <fi#7>, 0, 0, <fi#6>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#9>, 0, 0, <fi#8>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, %vreg1, 0, <fi#1>, 0, 0, <fi#13>, 0, 0, <fi#14>, 0, ...; mem:LD8[FixedStack12](align=4) LD8[FixedStack3](align=4) LD8[FixedStack7](align=4) LD8[FixedStack6](align=4) LD8[FixedStack4](align=1) LD8[FixedStack5](align=4) LD8[FixedStack9](align=4) LD8[FixedStack8] LD8[FixedStack11](align=4) LD8[FixedStack10] LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1] LD8[FixedStack13](align=4) LD8[FixedStack14](align=4) GR64:%vreg1
208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg1<kill>; mem:ST8[%s.addr] GR64:%vreg1
240B		%vreg4<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg4
256B		CMP8mi %vreg4<kill>, 1, %noreg, 20, %noreg, 0, %EFLAGS<imp-def>; mem:LD1[%blockRandomised] GR64:%vreg4
272B		JE_1 <BB#47>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#47 BB#1
> %RBX<def> = COPY %RDI
> %RDI<def> = MOV64ri <ga:@unRLE_obuf_to_output_FAST>
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 0, 0, 0, <fi#12>, 0, 0, <fi#3>, 0, 0, <fi#7>, 0, 0, <fi#6>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#9>, 0, 0, <fi#8>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, %RBX, 0, <fi#1>, 0, 0, <fi#13>, 0, 0, <fi#14>, 0, ...; mem:LD8[FixedStack12](align=4) LD8[FixedStack3](align=4) LD8[FixedStack7](align=4) LD8[FixedStack6](align=4) LD8[FixedStack4](align=1) LD8[FixedStack5](align=4) LD8[FixedStack9](align=4) LD8[FixedStack8] LD8[FixedStack11](align=4) LD8[FixedStack10] LD8[FixedStack2](align=1) LD8[FixedStack0](align=1) LD8[FixedStack1] LD8[FixedStack13](align=4) LD8[FixedStack14](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %RBX<kill>; mem:ST8[%s.addr]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> CMP8mi %RAX<kill>, 1, %noreg, 20, %noreg, 0, %EFLAGS<imp-def>; mem:LD1[%blockRandomised]
> JE_1 <BB#47>, %EFLAGS<imp-use,kill>
288B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
304B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2
> JMP_1 <BB#2>
320B	BB#2: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#1 BB#46 BB#37 BB#35 BB#29 BB#27 BB#21 BB#19
336B		JMP_1 <BB#3>
	    Successors according to CFG: BB#3
> JMP_1 <BB#3>
352B	BB#3: derived from LLVM BB %while.body.2
	    Predecessors according to CFG: BB#2 BB#9
368B		%vreg360<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg360
384B		%vreg359<def> = MOV64rm %vreg360<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm] GR64:%vreg359,%vreg360
400B		CMP32mi8 %vreg359<kill>, 1, %noreg, 32, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_out] GR64:%vreg359
416B		JNE_1 <BB#5>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#5 BB#4
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm]
> CMP32mi8 %RAX<kill>, 1, %noreg, 32, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_out]
> JNE_1 <BB#5>, %EFLAGS<imp-use,kill>
432B	BB#4: derived from LLVM BB %if.then.3
	    Predecessors according to CFG: BB#3
448B		MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST1[%retval]
464B		JMP_1 <BB#80>
	    Successors according to CFG: BB#80
> MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST1[%retval]
> JMP_1 <BB#80>
480B	BB#5: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#3
496B		%vreg363<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg363
512B		CMP32mi8 %vreg363<kill>, 1, %noreg, 16, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%state_out_len] GR64:%vreg363
528B		JNE_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#6
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> CMP32mi8 %RAX<kill>, 1, %noreg, 16, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%state_out_len]
> JNE_1 <BB#7>, %EFLAGS<imp-use,kill>
544B	BB#6: derived from LLVM BB %if.then.5
	    Predecessors according to CFG: BB#5
560B		JMP_1 <BB#10>
	    Successors according to CFG: BB#10
> JMP_1 <BB#10>
576B	BB#7: derived from LLVM BB %if.end.6
	    Predecessors according to CFG: BB#5
592B		%vreg435<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg435
608B		%vreg434<def> = MOV8rm %vreg435<kill>, 1, %noreg, 12, %noreg; mem:LD1[%state_out_ch] GR8:%vreg434 GR64:%vreg435
624B		%vreg432<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg432
640B		%vreg431<def> = MOV64rm %vreg432<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm7] GR64:%vreg431,%vreg432
656B		%vreg429<def> = MOV64rm %vreg431<kill>, 1, %noreg, 24, %noreg; mem:LD8[%next_out] GR64:%vreg429,%vreg431
672B		MOV8mr %vreg429<kill>, 1, %noreg, 0, %noreg, %vreg434<kill>; mem:ST1[%11] GR64:%vreg429 GR8:%vreg434
688B		%vreg425<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg425
704B		%vreg404<def> = MOV32rm %vreg425<kill>, 1, %noreg, 3184, %noreg; mem:LD4[%calculatedBlockCRC] GR32:%vreg404 GR64:%vreg425
736B		%vreg404<def,tied1> = SHL32ri %vreg404<kill,tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg404
752B		%vreg420<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg420
768B		%vreg411<def> = MOV32rm %vreg420<kill>, 1, %noreg, 3184, %noreg; mem:LD4[%calculatedBlockCRC8] GR32:%vreg411 GR64:%vreg420
800B		%vreg411<def,tied1> = SHR32ri %vreg411<kill,tied0>, 24, %EFLAGS<imp-def,dead>; GR32:%vreg411
816B		%vreg415<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg415
832B		%vreg413<def> = MOVZX32rm8 %vreg415<kill>, 1, %noreg, 12, %noreg; mem:LD1[%state_out_ch9] GR32:%vreg413 GR64:%vreg415
864B		%vreg411<def,tied1> = XOR32rr %vreg411<kill,tied0>, %vreg413<kill>, %EFLAGS<imp-def,dead>; GR32:%vreg411,%vreg413
880B		%vreg408:sub_32bit<def,read-undef> = MOV32rr %vreg411<kill>; GR64_NOSP:%vreg408 GR32:%vreg411
928B		%vreg404<def,tied1> = XOR32rm %vreg404<kill,tied0>, %noreg, 4, %vreg408<kill>, <ga:@BZ2_crc32Table>, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%arrayidx] GR32:%vreg404 GR64_NOSP:%vreg408
944B		%vreg401<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg401
960B		MOV32mr %vreg401<kill>, 1, %noreg, 3184, %noreg, %vreg404<kill>; mem:ST4[%calculatedBlockCRC11] GR64:%vreg401 GR32:%vreg404
976B		%vreg398<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg398
992B		%vreg396<def> = MOV32rm %vreg398, 1, %noreg, 16, %noreg; mem:LD4[%state_out_len12] GR32:%vreg396 GR64:%vreg398
1024B		%vreg396<def,tied1> = ADD32ri8 %vreg396<kill,tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg396
1040B		MOV32mr %vreg398<kill>, 1, %noreg, 16, %noreg, %vreg396<kill>; mem:ST4[%state_out_len12] GR64:%vreg398 GR32:%vreg396
1056B		%vreg392<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg392
1072B		%vreg391<def> = MOV64rm %vreg392<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm13] GR64:%vreg391,%vreg392
1088B		%vreg388<def> = MOV64rm %vreg391, 1, %noreg, 24, %noreg; mem:LD8[%next_out14] GR64:%vreg388,%vreg391
1120B		%vreg388<def,tied1> = ADD64ri8 %vreg388<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR64:%vreg388
1136B		MOV64mr %vreg391<kill>, 1, %noreg, 24, %noreg, %vreg388<kill>; mem:ST8[%next_out14] GR64:%vreg391,%vreg388
1152B		%vreg384<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg384
1168B		%vreg383<def> = MOV64rm %vreg384<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm15] GR64:%vreg383,%vreg384
1184B		%vreg380<def> = MOV32rm %vreg383, 1, %noreg, 32, %noreg; mem:LD4[%avail_out16] GR32:%vreg380 GR64:%vreg383
1216B		%vreg380<def,tied1> = ADD32ri8 %vreg380<kill,tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg380
1232B		MOV32mr %vreg383<kill>, 1, %noreg, 32, %noreg, %vreg380<kill>; mem:ST4[%avail_out16] GR64:%vreg383 GR32:%vreg380
1248B		%vreg376<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg376
1264B		%vreg375<def> = MOV64rm %vreg376<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm18] GR64:%vreg375,%vreg376
1280B		%vreg372<def> = MOV32rm %vreg375, 1, %noreg, 36, %noreg; mem:LD4[%total_out_lo32] GR32:%vreg372 GR64:%vreg375
1312B		%vreg372<def,tied1> = ADD32ri8 %vreg372<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg372
1328B		MOV32mr %vreg375<kill>, 1, %noreg, 36, %noreg, %vreg372<kill>; mem:ST4[%total_out_lo32] GR64:%vreg375 GR32:%vreg372
1344B		%vreg368<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg368
1360B		%vreg367<def> = MOV64rm %vreg368<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm19] GR64:%vreg367,%vreg368
1376B		CMP32mi8 %vreg367<kill>, 1, %noreg, 36, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%total_out_lo3220] GR64:%vreg367
1392B		JNE_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#8
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %AL<def> = MOV8rm %RAX<kill>, 1, %noreg, 12, %noreg; mem:LD1[%state_out_ch]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RCX<def> = MOV64rm %RCX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm7]
> %RCX<def> = MOV64rm %RCX<kill>, 1, %noreg, 24, %noreg; mem:LD8[%next_out]
> MOV8mr %RCX<kill>, 1, %noreg, 0, %noreg, %AL<kill>; mem:ST1[%11]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 3184, %noreg; mem:LD4[%calculatedBlockCRC]
> %EAX<def,tied1> = SHL32ri %EAX<kill,tied0>, 8, %EFLAGS<imp-def,dead>
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RCX<kill>, 1, %noreg, 3184, %noreg; mem:LD4[%calculatedBlockCRC8]
> %ECX<def,tied1> = SHR32ri %ECX<kill,tied0>, 24, %EFLAGS<imp-def,dead>
> %RDX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EDX<def> = MOVZX32rm8 %RDX<kill>, 1, %noreg, 12, %noreg; mem:LD1[%state_out_ch9]
> %ECX<def,tied1> = XOR32rr %ECX<kill,tied0>, %EDX<kill>, %EFLAGS<imp-def,dead>
> %ECX<def> = MOV32rr %ECX<kill>, %RCX<imp-def>
> %EAX<def,tied1> = XOR32rm %EAX<kill,tied0>, %noreg, 4, %RCX<kill>, <ga:@BZ2_crc32Table>, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%arrayidx]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mr %RCX<kill>, 1, %noreg, 3184, %noreg, %EAX<kill>; mem:ST4[%calculatedBlockCRC11]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 16, %noreg; mem:LD4[%state_out_len12]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, -1, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 16, %noreg, %ECX<kill>; mem:ST4[%state_out_len12]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm13]
> %RCX<def> = MOV64rm %RAX, 1, %noreg, 24, %noreg; mem:LD8[%next_out14]
> %RCX<def,tied1> = ADD64ri8 %RCX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV64mr %RAX<kill>, 1, %noreg, 24, %noreg, %RCX<kill>; mem:ST8[%next_out14]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm15]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 32, %noreg; mem:LD4[%avail_out16]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, -1, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 32, %noreg, %ECX<kill>; mem:ST4[%avail_out16]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm18]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 36, %noreg; mem:LD4[%total_out_lo32]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 36, %noreg, %ECX<kill>; mem:ST4[%total_out_lo32]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm19]
> CMP32mi8 %RAX<kill>, 1, %noreg, 36, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%total_out_lo3220]
> JNE_1 <BB#9>, %EFLAGS<imp-use,kill>
1408B	BB#8: derived from LLVM BB %if.then.23
	    Predecessors according to CFG: BB#7
1424B		%vreg443<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg443
1440B		%vreg442<def> = MOV64rm %vreg443<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm24] GR64:%vreg442,%vreg443
1456B		%vreg439<def> = MOV32rm %vreg442, 1, %noreg, 40, %noreg; mem:LD4[%total_out_hi32] GR32:%vreg439 GR64:%vreg442
1488B		%vreg439<def,tied1> = ADD32ri8 %vreg439<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg439
1504B		MOV32mr %vreg442<kill>, 1, %noreg, 40, %noreg, %vreg439<kill>; mem:ST4[%total_out_hi32] GR64:%vreg442 GR32:%vreg439
	    Successors according to CFG: BB#9
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm24]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 40, %noreg; mem:LD4[%total_out_hi32]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 40, %noreg, %ECX<kill>; mem:ST4[%total_out_hi32]
1520B	BB#9: derived from LLVM BB %if.end.26
	    Predecessors according to CFG: BB#7 BB#8
1536B		JMP_1 <BB#3>
	    Successors according to CFG: BB#3
> JMP_1 <BB#3>
1552B	BB#10: derived from LLVM BB %while.end
	    Predecessors according to CFG: BB#6
1568B		%vreg453<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg453
1584B		%vreg452<def> = MOV32rm %vreg453<kill>, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used] GR32:%vreg452 GR64:%vreg453
1600B		%vreg450<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg450
1616B		%vreg447<def> = MOV32rm %vreg450<kill>, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock] GR32:%vreg447 GR64:%vreg450
1648B		%vreg447<def,tied1> = ADD32ri8 %vreg447<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg447
1664B		CMP32rr %vreg452<kill>, %vreg447<kill>, %EFLAGS<imp-def>; GR32:%vreg452,%vreg447
1680B		JNE_1 <BB#12>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#12 BB#11
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RCX<kill>, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> CMP32rr %EAX<kill>, %ECX<kill>, %EFLAGS<imp-def>
> JNE_1 <BB#12>, %EFLAGS<imp-use,kill>
1696B	BB#11: derived from LLVM BB %if.then.29
	    Predecessors according to CFG: BB#10
1712B		MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST1[%retval]
1728B		JMP_1 <BB#80>
	    Successors according to CFG: BB#80
> MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST1[%retval]
> JMP_1 <BB#80>
1744B	BB#12: derived from LLVM BB %if.end.30
	    Predecessors according to CFG: BB#10
1760B		%vreg463<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg463
1776B		%vreg462<def> = MOV32rm %vreg463<kill>, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used31] GR32:%vreg462 GR64:%vreg463
1792B		%vreg460<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg460
1808B		%vreg457<def> = MOV32rm %vreg460<kill>, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock32] GR32:%vreg457 GR64:%vreg460
1840B		%vreg457<def,tied1> = ADD32ri8 %vreg457<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg457
1856B		CMP32rr %vreg462<kill>, %vreg457<kill>, %EFLAGS<imp-def>; GR32:%vreg462,%vreg457
1872B		JLE_1 <BB#14>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#14 BB#13
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used31]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RCX<kill>, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock32]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> CMP32rr %EAX<kill>, %ECX<kill>, %EFLAGS<imp-def>
> JLE_1 <BB#14>, %EFLAGS<imp-use,kill>
1888B	BB#13: derived from LLVM BB %if.then.36
	    Predecessors according to CFG: BB#12
1904B		MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 1; mem:ST1[%retval]
1920B		JMP_1 <BB#80>
	    Successors according to CFG: BB#80
> MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 1; mem:ST1[%retval]
> JMP_1 <BB#80>
1936B	BB#14: derived from LLVM BB %if.end.37
	    Predecessors according to CFG: BB#12
1952B		%vreg504<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg504
1968B		MOV32mi %vreg504<kill>, 1, %noreg, 16, %noreg, 1; mem:ST4[%state_out_len38] GR64:%vreg504
1984B		%vreg502<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg502
2000B		%vreg501<def> = MOV32rm %vreg502<kill>, 1, %noreg, 64, %noreg; mem:LD4[%k0] GR32:%vreg501 GR64:%vreg502
2032B		%vreg497<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg497
2048B		MOV8mr %vreg497<kill>, 1, %noreg, 12, %noreg, %vreg501:sub_8bit<kill>; mem:ST1[%state_out_ch40] GR64:%vreg497 GR32:%vreg501
2064B		%vreg494<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg494
2080B		%vreg492:sub_32bit<def,read-undef> = MOV32rm %vreg494<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos] GR64_NOSP:%vreg492 GR64:%vreg494
2112B		%vreg489<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg489
2128B		%vreg488<def> = MOV64rm %vreg489<kill>, 1, %noreg, 3152, %noreg; mem:LD8[%tt] GR64:%vreg488,%vreg489
2144B		%vreg486<def> = MOV32rm %vreg488<kill>, 4, %vreg492<kill>, 0, %noreg; mem:LD4[%arrayidx42] GR32:%vreg486 GR64:%vreg488 GR64_NOSP:%vreg492
2160B		%vreg483<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg483
2176B		MOV32mr %vreg483<kill>, 1, %noreg, 60, %noreg, %vreg486<kill>; mem:ST4[%tPos43] GR64:%vreg483 GR32:%vreg486
2192B		%vreg480<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg480
2208B		%vreg477<def> = MOV32rm %vreg480<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos44] GR32:%vreg477 GR64:%vreg480
2240B		%vreg477<def,tied1> = AND32ri %vreg477<kill,tied0>, 255, %EFLAGS<imp-def,dead>; GR32:%vreg477
2272B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg477:sub_8bit<kill>; mem:ST1[%k1] GR32:%vreg477
2288B		%vreg472<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg472
2304B		%vreg470<def> = MOV32rm %vreg472, 1, %noreg, 60, %noreg; mem:LD4[%tPos46] GR32:%vreg470 GR64:%vreg472
2336B		%vreg470<def,tied1> = SHR32ri %vreg470<kill,tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg470
2352B		MOV32mr %vreg472<kill>, 1, %noreg, 60, %noreg, %vreg470<kill>; mem:ST4[%tPos46] GR64:%vreg472 GR32:%vreg470
2368B		%vreg466<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg466
2384B		CMP32mi8 %vreg466<kill>, 1, %noreg, 24, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%rNToGo] GR64:%vreg466
2400B		JNE_1 <BB#18>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#18 BB#15
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 16, %noreg, 1; mem:ST4[%state_out_len38]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 64, %noreg; mem:LD4[%k0]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV8mr %RCX<kill>, 1, %noreg, 12, %noreg, %AL, %EAX<imp-use,kill>; mem:ST1[%state_out_ch40]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 60, %noreg, %RAX<imp-def>; mem:LD4[%tPos]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RCX<def> = MOV64rm %RCX<kill>, 1, %noreg, 3152, %noreg; mem:LD8[%tt]
> %EAX<def> = MOV32rm %RCX<kill>, 4, %RAX<kill>, 0, %noreg; mem:LD4[%arrayidx42]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mr %RCX<kill>, 1, %noreg, 60, %noreg, %EAX<kill>; mem:ST4[%tPos43]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos44]
> %EAX<def,tied1> = AND32ri %EAX<kill,tied0>, 255, %EFLAGS<imp-def,dead>
> MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %AL, %EAX<imp-use,kill>; mem:ST1[%k1]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 60, %noreg; mem:LD4[%tPos46]
> %ECX<def,tied1> = SHR32ri %ECX<kill,tied0>, 8, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 60, %noreg, %ECX<kill>; mem:ST4[%tPos46]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> CMP32mi8 %RAX<kill>, 1, %noreg, 24, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%rNToGo]
> JNE_1 <BB#18>, %EFLAGS<imp-use,kill>
2416B	BB#15: derived from LLVM BB %if.then.50
	    Predecessors according to CFG: BB#14
2432B		%vreg522<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg522
2448B		%vreg520<def> = MOVSX64rm32 %vreg522<kill>, 1, %noreg, 28, %noreg; mem:LD4[%rTPos] GR64_NOSP:%vreg520 GR64:%vreg522
2464B		%vreg518<def> = MOV32rm %noreg, 4, %vreg520<kill>, <ga:@BZ2_rNums>, %noreg; mem:LD4[%arrayidx52] GR32:%vreg518 GR64_NOSP:%vreg520
2480B		%vreg516<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg516
2496B		MOV32mr %vreg516<kill>, 1, %noreg, 24, %noreg, %vreg518<kill>; mem:ST4[%rNToGo53] GR64:%vreg516 GR32:%vreg518
2512B		%vreg513<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg513
2528B		%vreg511<def> = MOV32rm %vreg513, 1, %noreg, 28, %noreg; mem:LD4[%rTPos54] GR32:%vreg511 GR64:%vreg513
2560B		%vreg511<def,tied1> = ADD32ri8 %vreg511<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg511
2576B		MOV32mr %vreg513<kill>, 1, %noreg, 28, %noreg, %vreg511<kill>; mem:ST4[%rTPos54] GR64:%vreg513 GR32:%vreg511
2592B		%vreg507<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg507
2608B		CMP32mi %vreg507<kill>, 1, %noreg, 28, %noreg, 512, %EFLAGS<imp-def>; mem:LD4[%rTPos56] GR64:%vreg507
2624B		JNE_1 <BB#17>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#17 BB#16
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RAX<def> = MOVSX64rm32 %RAX<kill>, 1, %noreg, 28, %noreg; mem:LD4[%rTPos]
> %EAX<def> = MOV32rm %noreg, 4, %RAX<kill>, <ga:@BZ2_rNums>, %noreg; mem:LD4[%arrayidx52]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mr %RCX<kill>, 1, %noreg, 24, %noreg, %EAX<kill>; mem:ST4[%rNToGo53]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 28, %noreg; mem:LD4[%rTPos54]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 28, %noreg, %ECX<kill>; mem:ST4[%rTPos54]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> CMP32mi %RAX<kill>, 1, %noreg, 28, %noreg, 512, %EFLAGS<imp-def>; mem:LD4[%rTPos56]
> JNE_1 <BB#17>, %EFLAGS<imp-use,kill>
2640B	BB#16: derived from LLVM BB %if.then.59
	    Predecessors according to CFG: BB#15
2656B		%vreg524<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg524
2672B		MOV32mi %vreg524<kill>, 1, %noreg, 28, %noreg, 0; mem:ST4[%rTPos60] GR64:%vreg524
	    Successors according to CFG: BB#17
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 28, %noreg, 0; mem:ST4[%rTPos60]
2688B	BB#17: derived from LLVM BB %if.end.61
	    Predecessors according to CFG: BB#15 BB#16
2704B		JMP_1 <BB#18>
	    Successors according to CFG: BB#18
> JMP_1 <BB#18>
2720B	BB#18: derived from LLVM BB %if.end.62
	    Predecessors according to CFG: BB#14 BB#17
2736B		%vreg552<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg552
2752B		%vreg551<def> = MOV32ri 1; GR32:%vreg551
2768B		%vreg560<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg560
2784B		%vreg558<def> = MOV32rm %vreg560, 1, %noreg, 24, %noreg; mem:LD4[%rNToGo63] GR32:%vreg558 GR64:%vreg560
2816B		%vreg558<def,tied1> = ADD32ri8 %vreg558<kill,tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg558
2832B		MOV32mr %vreg560<kill>, 1, %noreg, 24, %noreg, %vreg558<kill>; mem:ST4[%rNToGo63] GR64:%vreg560 GR32:%vreg558
2848B		%vreg554<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg554
2864B		CMP32mi8 %vreg554<kill>, 1, %noreg, 24, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%rNToGo65] GR64:%vreg554
2896B		%vreg552<def,tied1> = CMOVE32rr %vreg552<kill,tied0>, %vreg551<kill>, %EFLAGS<imp-use,kill>; GR32:%vreg552,%vreg551
2912B		%vreg546<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg546
2944B		%vreg546<def,tied1> = XOR32rr %vreg546<kill,tied0>, %vreg552<kill>, %EFLAGS<imp-def,dead>; GR32:%vreg546,%vreg552
2976B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg546:sub_8bit<kill>; mem:ST1[%k1] GR32:%vreg546
2992B		%vreg540<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg540
3008B		%vreg538<def> = MOV32rm %vreg540, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used71] GR32:%vreg538 GR64:%vreg540
3040B		%vreg538<def,tied1> = ADD32ri8 %vreg538<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg538
3056B		MOV32mr %vreg540<kill>, 1, %noreg, 1092, %noreg, %vreg538<kill>; mem:ST4[%nblock_used71] GR64:%vreg540 GR32:%vreg538
3072B		%vreg534<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg534
3088B		%vreg533<def> = MOV32rm %vreg534<kill>, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used73] GR32:%vreg533 GR64:%vreg534
3104B		%vreg531<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg531
3120B		%vreg528<def> = MOV32rm %vreg531<kill>, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock74] GR32:%vreg528 GR64:%vreg531
3152B		%vreg528<def,tied1> = ADD32ri8 %vreg528<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg528
3168B		CMP32rr %vreg533<kill>, %vreg528<kill>, %EFLAGS<imp-def>; GR32:%vreg533,%vreg528
3184B		JNE_1 <BB#20>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#20 BB#19
> %EAX<def> = MOV32r0 %EFLAGS<imp-def,dead>
> %ECX<def> = MOV32ri 1
> %RDX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ESI<def> = MOV32rm %RDX, 1, %noreg, 24, %noreg; mem:LD4[%rNToGo63]
> %ESI<def,tied1> = ADD32ri8 %ESI<kill,tied0>, -1, %EFLAGS<imp-def,dead>
> MOV32mr %RDX<kill>, 1, %noreg, 24, %noreg, %ESI<kill>; mem:ST4[%rNToGo63]
> %RDX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> CMP32mi8 %RDX<kill>, 1, %noreg, 24, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%rNToGo65]
> %EAX<def,tied1> = CMOVE32rr %EAX<kill,tied0>, %ECX<kill>, %EFLAGS<imp-use,kill>
> %ECX<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1]
> %ECX<def,tied1> = XOR32rr %ECX<kill,tied0>, %EAX<kill>, %EFLAGS<imp-def,dead>
> MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %CL, %ECX<imp-use,kill>; mem:ST1[%k1]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used71]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 1092, %noreg, %ECX<kill>; mem:ST4[%nblock_used71]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used73]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RCX<kill>, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock74]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> CMP32rr %EAX<kill>, %ECX<kill>, %EFLAGS<imp-def>
> JNE_1 <BB#20>, %EFLAGS<imp-use,kill>
3200B	BB#19: derived from LLVM BB %if.then.78
	    Predecessors according to CFG: BB#18
3216B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2
> JMP_1 <BB#2>
3232B	BB#20: derived from LLVM BB %if.end.79
	    Predecessors according to CFG: BB#18
3248B		%vreg566<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg566
3264B		%vreg564<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg564
3280B		CMP32rm %vreg566<kill>, %vreg564<kill>, 1, %noreg, 64, %noreg, %EFLAGS<imp-def>; mem:LD4[%k081] GR32:%vreg566 GR64:%vreg564
3296B		JE_1 <BB#22>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#22 BB#21
> %EAX<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> CMP32rm %EAX<kill>, %RCX<kill>, 1, %noreg, 64, %noreg, %EFLAGS<imp-def>; mem:LD4[%k081]
> JE_1 <BB#22>, %EFLAGS<imp-use,kill>
3312B	BB#21: derived from LLVM BB %if.then.84
	    Predecessors according to CFG: BB#20
3328B		%vreg934<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg934
3344B		%vreg932<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg932
3360B		MOV32mr %vreg932<kill>, 1, %noreg, 64, %noreg, %vreg934<kill>; mem:ST4[%k086] GR64:%vreg932 GR32:%vreg934
3376B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2
> %EAX<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mr %RCX<kill>, 1, %noreg, 64, %noreg, %EAX<kill>; mem:ST4[%k086]
> JMP_1 <BB#2>
3392B	BB#22: derived from LLVM BB %if.end.87
	    Predecessors according to CFG: BB#20
3408B		%vreg599<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg599
3424B		MOV32mi %vreg599<kill>, 1, %noreg, 16, %noreg, 2; mem:ST4[%state_out_len88] GR64:%vreg599
3440B		%vreg597<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg597
3456B		%vreg595:sub_32bit<def,read-undef> = MOV32rm %vreg597<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos89] GR64_NOSP:%vreg595 GR64:%vreg597
3488B		%vreg592<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg592
3504B		%vreg591<def> = MOV64rm %vreg592<kill>, 1, %noreg, 3152, %noreg; mem:LD8[%tt91] GR64:%vreg591,%vreg592
3520B		%vreg589<def> = MOV32rm %vreg591<kill>, 4, %vreg595<kill>, 0, %noreg; mem:LD4[%arrayidx92] GR32:%vreg589 GR64:%vreg591 GR64_NOSP:%vreg595
3536B		%vreg586<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg586
3552B		MOV32mr %vreg586<kill>, 1, %noreg, 60, %noreg, %vreg589<kill>; mem:ST4[%tPos93] GR64:%vreg586 GR32:%vreg589
3568B		%vreg583<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg583
3584B		%vreg580<def> = MOV32rm %vreg583<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos94] GR32:%vreg580 GR64:%vreg583
3616B		%vreg580<def,tied1> = AND32ri %vreg580<kill,tied0>, 255, %EFLAGS<imp-def,dead>; GR32:%vreg580
3648B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg580:sub_8bit<kill>; mem:ST1[%k1] GR32:%vreg580
3664B		%vreg575<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg575
3680B		%vreg573<def> = MOV32rm %vreg575, 1, %noreg, 60, %noreg; mem:LD4[%tPos97] GR32:%vreg573 GR64:%vreg575
3712B		%vreg573<def,tied1> = SHR32ri %vreg573<kill,tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg573
3728B		MOV32mr %vreg575<kill>, 1, %noreg, 60, %noreg, %vreg573<kill>; mem:ST4[%tPos97] GR64:%vreg575 GR32:%vreg573
3744B		%vreg569<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg569
3760B		CMP32mi8 %vreg569<kill>, 1, %noreg, 24, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%rNToGo99] GR64:%vreg569
3776B		JNE_1 <BB#26>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#26 BB#23
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 16, %noreg, 2; mem:ST4[%state_out_len88]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 60, %noreg, %RAX<imp-def>; mem:LD4[%tPos89]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RCX<def> = MOV64rm %RCX<kill>, 1, %noreg, 3152, %noreg; mem:LD8[%tt91]
> %EAX<def> = MOV32rm %RCX<kill>, 4, %RAX<kill>, 0, %noreg; mem:LD4[%arrayidx92]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mr %RCX<kill>, 1, %noreg, 60, %noreg, %EAX<kill>; mem:ST4[%tPos93]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos94]
> %EAX<def,tied1> = AND32ri %EAX<kill,tied0>, 255, %EFLAGS<imp-def,dead>
> MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %AL, %EAX<imp-use,kill>; mem:ST1[%k1]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 60, %noreg; mem:LD4[%tPos97]
> %ECX<def,tied1> = SHR32ri %ECX<kill,tied0>, 8, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 60, %noreg, %ECX<kill>; mem:ST4[%tPos97]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> CMP32mi8 %RAX<kill>, 1, %noreg, 24, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%rNToGo99]
> JNE_1 <BB#26>, %EFLAGS<imp-use,kill>
3792B	BB#23: derived from LLVM BB %if.then.102
	    Predecessors according to CFG: BB#22
3808B		%vreg617<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg617
3824B		%vreg615<def> = MOVSX64rm32 %vreg617<kill>, 1, %noreg, 28, %noreg; mem:LD4[%rTPos103] GR64_NOSP:%vreg615 GR64:%vreg617
3840B		%vreg613<def> = MOV32rm %noreg, 4, %vreg615<kill>, <ga:@BZ2_rNums>, %noreg; mem:LD4[%arrayidx105] GR32:%vreg613 GR64_NOSP:%vreg615
3856B		%vreg611<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg611
3872B		MOV32mr %vreg611<kill>, 1, %noreg, 24, %noreg, %vreg613<kill>; mem:ST4[%rNToGo106] GR64:%vreg611 GR32:%vreg613
3888B		%vreg608<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg608
3904B		%vreg606<def> = MOV32rm %vreg608, 1, %noreg, 28, %noreg; mem:LD4[%rTPos107] GR32:%vreg606 GR64:%vreg608
3936B		%vreg606<def,tied1> = ADD32ri8 %vreg606<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg606
3952B		MOV32mr %vreg608<kill>, 1, %noreg, 28, %noreg, %vreg606<kill>; mem:ST4[%rTPos107] GR64:%vreg608 GR32:%vreg606
3968B		%vreg602<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg602
3984B		CMP32mi %vreg602<kill>, 1, %noreg, 28, %noreg, 512, %EFLAGS<imp-def>; mem:LD4[%rTPos109] GR64:%vreg602
4000B		JNE_1 <BB#25>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#25 BB#24
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RAX<def> = MOVSX64rm32 %RAX<kill>, 1, %noreg, 28, %noreg; mem:LD4[%rTPos103]
> %EAX<def> = MOV32rm %noreg, 4, %RAX<kill>, <ga:@BZ2_rNums>, %noreg; mem:LD4[%arrayidx105]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mr %RCX<kill>, 1, %noreg, 24, %noreg, %EAX<kill>; mem:ST4[%rNToGo106]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 28, %noreg; mem:LD4[%rTPos107]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 28, %noreg, %ECX<kill>; mem:ST4[%rTPos107]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> CMP32mi %RAX<kill>, 1, %noreg, 28, %noreg, 512, %EFLAGS<imp-def>; mem:LD4[%rTPos109]
> JNE_1 <BB#25>, %EFLAGS<imp-use,kill>
4016B	BB#24: derived from LLVM BB %if.then.112
	    Predecessors according to CFG: BB#23
4032B		%vreg619<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg619
4048B		MOV32mi %vreg619<kill>, 1, %noreg, 28, %noreg, 0; mem:ST4[%rTPos113] GR64:%vreg619
	    Successors according to CFG: BB#25
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 28, %noreg, 0; mem:ST4[%rTPos113]
4064B	BB#25: derived from LLVM BB %if.end.114
	    Predecessors according to CFG: BB#23 BB#24
4080B		JMP_1 <BB#26>
	    Successors according to CFG: BB#26
> JMP_1 <BB#26>
4096B	BB#26: derived from LLVM BB %if.end.115
	    Predecessors according to CFG: BB#22 BB#25
4112B		%vreg647<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg647
4128B		%vreg646<def> = MOV32ri 1; GR32:%vreg646
4144B		%vreg655<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg655
4160B		%vreg653<def> = MOV32rm %vreg655, 1, %noreg, 24, %noreg; mem:LD4[%rNToGo116] GR32:%vreg653 GR64:%vreg655
4192B		%vreg653<def,tied1> = ADD32ri8 %vreg653<kill,tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg653
4208B		MOV32mr %vreg655<kill>, 1, %noreg, 24, %noreg, %vreg653<kill>; mem:ST4[%rNToGo116] GR64:%vreg655 GR32:%vreg653
4224B		%vreg649<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg649
4240B		CMP32mi8 %vreg649<kill>, 1, %noreg, 24, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%rNToGo118] GR64:%vreg649
4272B		%vreg647<def,tied1> = CMOVE32rr %vreg647<kill,tied0>, %vreg646<kill>, %EFLAGS<imp-use,kill>; GR32:%vreg647,%vreg646
4288B		%vreg641<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg641
4320B		%vreg641<def,tied1> = XOR32rr %vreg641<kill,tied0>, %vreg647<kill>, %EFLAGS<imp-def,dead>; GR32:%vreg641,%vreg647
4352B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg641:sub_8bit<kill>; mem:ST1[%k1] GR32:%vreg641
4368B		%vreg635<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg635
4384B		%vreg633<def> = MOV32rm %vreg635, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used125] GR32:%vreg633 GR64:%vreg635
4416B		%vreg633<def,tied1> = ADD32ri8 %vreg633<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg633
4432B		MOV32mr %vreg635<kill>, 1, %noreg, 1092, %noreg, %vreg633<kill>; mem:ST4[%nblock_used125] GR64:%vreg635 GR32:%vreg633
4448B		%vreg629<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg629
4464B		%vreg628<def> = MOV32rm %vreg629<kill>, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used127] GR32:%vreg628 GR64:%vreg629
4480B		%vreg626<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg626
4496B		%vreg623<def> = MOV32rm %vreg626<kill>, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock128] GR32:%vreg623 GR64:%vreg626
4528B		%vreg623<def,tied1> = ADD32ri8 %vreg623<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg623
4544B		CMP32rr %vreg628<kill>, %vreg623<kill>, %EFLAGS<imp-def>; GR32:%vreg628,%vreg623
4560B		JNE_1 <BB#28>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#28 BB#27
> %EAX<def> = MOV32r0 %EFLAGS<imp-def,dead>
> %ECX<def> = MOV32ri 1
> %RDX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ESI<def> = MOV32rm %RDX, 1, %noreg, 24, %noreg; mem:LD4[%rNToGo116]
> %ESI<def,tied1> = ADD32ri8 %ESI<kill,tied0>, -1, %EFLAGS<imp-def,dead>
> MOV32mr %RDX<kill>, 1, %noreg, 24, %noreg, %ESI<kill>; mem:ST4[%rNToGo116]
> %RDX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> CMP32mi8 %RDX<kill>, 1, %noreg, 24, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%rNToGo118]
> %EAX<def,tied1> = CMOVE32rr %EAX<kill,tied0>, %ECX<kill>, %EFLAGS<imp-use,kill>
> %ECX<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1]
> %ECX<def,tied1> = XOR32rr %ECX<kill,tied0>, %EAX<kill>, %EFLAGS<imp-def,dead>
> MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %CL, %ECX<imp-use,kill>; mem:ST1[%k1]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used125]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 1092, %noreg, %ECX<kill>; mem:ST4[%nblock_used125]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used127]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RCX<kill>, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock128]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> CMP32rr %EAX<kill>, %ECX<kill>, %EFLAGS<imp-def>
> JNE_1 <BB#28>, %EFLAGS<imp-use,kill>
4576B	BB#27: derived from LLVM BB %if.then.132
	    Predecessors according to CFG: BB#26
4592B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2
> JMP_1 <BB#2>
4608B	BB#28: derived from LLVM BB %if.end.133
	    Predecessors according to CFG: BB#26
4624B		%vreg661<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg661
4640B		%vreg659<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg659
4656B		CMP32rm %vreg661<kill>, %vreg659<kill>, 1, %noreg, 64, %noreg, %EFLAGS<imp-def>; mem:LD4[%k0135] GR32:%vreg661 GR64:%vreg659
4672B		JE_1 <BB#30>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#30 BB#29
> %EAX<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> CMP32rm %EAX<kill>, %RCX<kill>, 1, %noreg, 64, %noreg, %EFLAGS<imp-def>; mem:LD4[%k0135]
> JE_1 <BB#30>, %EFLAGS<imp-use,kill>
4688B	BB#29: derived from LLVM BB %if.then.138
	    Predecessors according to CFG: BB#28
4704B		%vreg929<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg929
4720B		%vreg927<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg927
4736B		MOV32mr %vreg927<kill>, 1, %noreg, 64, %noreg, %vreg929<kill>; mem:ST4[%k0140] GR64:%vreg927 GR32:%vreg929
4752B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2
> %EAX<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mr %RCX<kill>, 1, %noreg, 64, %noreg, %EAX<kill>; mem:ST4[%k0140]
> JMP_1 <BB#2>
4768B	BB#30: derived from LLVM BB %if.end.141
	    Predecessors according to CFG: BB#28
4784B		%vreg694<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg694
4800B		MOV32mi %vreg694<kill>, 1, %noreg, 16, %noreg, 3; mem:ST4[%state_out_len142] GR64:%vreg694
4816B		%vreg692<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg692
4832B		%vreg690:sub_32bit<def,read-undef> = MOV32rm %vreg692<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos143] GR64_NOSP:%vreg690 GR64:%vreg692
4864B		%vreg687<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg687
4880B		%vreg686<def> = MOV64rm %vreg687<kill>, 1, %noreg, 3152, %noreg; mem:LD8[%tt145] GR64:%vreg686,%vreg687
4896B		%vreg684<def> = MOV32rm %vreg686<kill>, 4, %vreg690<kill>, 0, %noreg; mem:LD4[%arrayidx146] GR32:%vreg684 GR64:%vreg686 GR64_NOSP:%vreg690
4912B		%vreg681<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg681
4928B		MOV32mr %vreg681<kill>, 1, %noreg, 60, %noreg, %vreg684<kill>; mem:ST4[%tPos147] GR64:%vreg681 GR32:%vreg684
4944B		%vreg678<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg678
4960B		%vreg675<def> = MOV32rm %vreg678<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos148] GR32:%vreg675 GR64:%vreg678
4992B		%vreg675<def,tied1> = AND32ri %vreg675<kill,tied0>, 255, %EFLAGS<imp-def,dead>; GR32:%vreg675
5024B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg675:sub_8bit<kill>; mem:ST1[%k1] GR32:%vreg675
5040B		%vreg670<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg670
5056B		%vreg668<def> = MOV32rm %vreg670, 1, %noreg, 60, %noreg; mem:LD4[%tPos151] GR32:%vreg668 GR64:%vreg670
5088B		%vreg668<def,tied1> = SHR32ri %vreg668<kill,tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg668
5104B		MOV32mr %vreg670<kill>, 1, %noreg, 60, %noreg, %vreg668<kill>; mem:ST4[%tPos151] GR64:%vreg670 GR32:%vreg668
5120B		%vreg664<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg664
5136B		CMP32mi8 %vreg664<kill>, 1, %noreg, 24, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%rNToGo153] GR64:%vreg664
5152B		JNE_1 <BB#34>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#34 BB#31
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 16, %noreg, 3; mem:ST4[%state_out_len142]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 60, %noreg, %RAX<imp-def>; mem:LD4[%tPos143]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RCX<def> = MOV64rm %RCX<kill>, 1, %noreg, 3152, %noreg; mem:LD8[%tt145]
> %EAX<def> = MOV32rm %RCX<kill>, 4, %RAX<kill>, 0, %noreg; mem:LD4[%arrayidx146]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mr %RCX<kill>, 1, %noreg, 60, %noreg, %EAX<kill>; mem:ST4[%tPos147]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos148]
> %EAX<def,tied1> = AND32ri %EAX<kill,tied0>, 255, %EFLAGS<imp-def,dead>
> MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %AL, %EAX<imp-use,kill>; mem:ST1[%k1]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 60, %noreg; mem:LD4[%tPos151]
> %ECX<def,tied1> = SHR32ri %ECX<kill,tied0>, 8, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 60, %noreg, %ECX<kill>; mem:ST4[%tPos151]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> CMP32mi8 %RAX<kill>, 1, %noreg, 24, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%rNToGo153]
> JNE_1 <BB#34>, %EFLAGS<imp-use,kill>
5168B	BB#31: derived from LLVM BB %if.then.156
	    Predecessors according to CFG: BB#30
5184B		%vreg712<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg712
5200B		%vreg710<def> = MOVSX64rm32 %vreg712<kill>, 1, %noreg, 28, %noreg; mem:LD4[%rTPos157] GR64_NOSP:%vreg710 GR64:%vreg712
5216B		%vreg708<def> = MOV32rm %noreg, 4, %vreg710<kill>, <ga:@BZ2_rNums>, %noreg; mem:LD4[%arrayidx159] GR32:%vreg708 GR64_NOSP:%vreg710
5232B		%vreg706<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg706
5248B		MOV32mr %vreg706<kill>, 1, %noreg, 24, %noreg, %vreg708<kill>; mem:ST4[%rNToGo160] GR64:%vreg706 GR32:%vreg708
5264B		%vreg703<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg703
5280B		%vreg701<def> = MOV32rm %vreg703, 1, %noreg, 28, %noreg; mem:LD4[%rTPos161] GR32:%vreg701 GR64:%vreg703
5312B		%vreg701<def,tied1> = ADD32ri8 %vreg701<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg701
5328B		MOV32mr %vreg703<kill>, 1, %noreg, 28, %noreg, %vreg701<kill>; mem:ST4[%rTPos161] GR64:%vreg703 GR32:%vreg701
5344B		%vreg697<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg697
5360B		CMP32mi %vreg697<kill>, 1, %noreg, 28, %noreg, 512, %EFLAGS<imp-def>; mem:LD4[%rTPos163] GR64:%vreg697
5376B		JNE_1 <BB#33>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#33 BB#32
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RAX<def> = MOVSX64rm32 %RAX<kill>, 1, %noreg, 28, %noreg; mem:LD4[%rTPos157]
> %EAX<def> = MOV32rm %noreg, 4, %RAX<kill>, <ga:@BZ2_rNums>, %noreg; mem:LD4[%arrayidx159]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mr %RCX<kill>, 1, %noreg, 24, %noreg, %EAX<kill>; mem:ST4[%rNToGo160]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 28, %noreg; mem:LD4[%rTPos161]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 28, %noreg, %ECX<kill>; mem:ST4[%rTPos161]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> CMP32mi %RAX<kill>, 1, %noreg, 28, %noreg, 512, %EFLAGS<imp-def>; mem:LD4[%rTPos163]
> JNE_1 <BB#33>, %EFLAGS<imp-use,kill>
5392B	BB#32: derived from LLVM BB %if.then.166
	    Predecessors according to CFG: BB#31
5408B		%vreg714<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg714
5424B		MOV32mi %vreg714<kill>, 1, %noreg, 28, %noreg, 0; mem:ST4[%rTPos167] GR64:%vreg714
	    Successors according to CFG: BB#33
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 28, %noreg, 0; mem:ST4[%rTPos167]
5440B	BB#33: derived from LLVM BB %if.end.168
	    Predecessors according to CFG: BB#31 BB#32
5456B		JMP_1 <BB#34>
	    Successors according to CFG: BB#34
> JMP_1 <BB#34>
5472B	BB#34: derived from LLVM BB %if.end.169
	    Predecessors according to CFG: BB#30 BB#33
5488B		%vreg742<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg742
5504B		%vreg741<def> = MOV32ri 1; GR32:%vreg741
5520B		%vreg750<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg750
5536B		%vreg748<def> = MOV32rm %vreg750, 1, %noreg, 24, %noreg; mem:LD4[%rNToGo170] GR32:%vreg748 GR64:%vreg750
5568B		%vreg748<def,tied1> = ADD32ri8 %vreg748<kill,tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg748
5584B		MOV32mr %vreg750<kill>, 1, %noreg, 24, %noreg, %vreg748<kill>; mem:ST4[%rNToGo170] GR64:%vreg750 GR32:%vreg748
5600B		%vreg744<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg744
5616B		CMP32mi8 %vreg744<kill>, 1, %noreg, 24, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%rNToGo172] GR64:%vreg744
5648B		%vreg742<def,tied1> = CMOVE32rr %vreg742<kill,tied0>, %vreg741<kill>, %EFLAGS<imp-use,kill>; GR32:%vreg742,%vreg741
5664B		%vreg736<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg736
5696B		%vreg736<def,tied1> = XOR32rr %vreg736<kill,tied0>, %vreg742<kill>, %EFLAGS<imp-def,dead>; GR32:%vreg736,%vreg742
5728B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg736:sub_8bit<kill>; mem:ST1[%k1] GR32:%vreg736
5744B		%vreg730<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg730
5760B		%vreg728<def> = MOV32rm %vreg730, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used179] GR32:%vreg728 GR64:%vreg730
5792B		%vreg728<def,tied1> = ADD32ri8 %vreg728<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg728
5808B		MOV32mr %vreg730<kill>, 1, %noreg, 1092, %noreg, %vreg728<kill>; mem:ST4[%nblock_used179] GR64:%vreg730 GR32:%vreg728
5824B		%vreg724<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg724
5840B		%vreg723<def> = MOV32rm %vreg724<kill>, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used181] GR32:%vreg723 GR64:%vreg724
5856B		%vreg721<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg721
5872B		%vreg718<def> = MOV32rm %vreg721<kill>, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock182] GR32:%vreg718 GR64:%vreg721
5904B		%vreg718<def,tied1> = ADD32ri8 %vreg718<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg718
5920B		CMP32rr %vreg723<kill>, %vreg718<kill>, %EFLAGS<imp-def>; GR32:%vreg723,%vreg718
5936B		JNE_1 <BB#36>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#36 BB#35
> %EAX<def> = MOV32r0 %EFLAGS<imp-def,dead>
> %ECX<def> = MOV32ri 1
> %RDX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ESI<def> = MOV32rm %RDX, 1, %noreg, 24, %noreg; mem:LD4[%rNToGo170]
> %ESI<def,tied1> = ADD32ri8 %ESI<kill,tied0>, -1, %EFLAGS<imp-def,dead>
> MOV32mr %RDX<kill>, 1, %noreg, 24, %noreg, %ESI<kill>; mem:ST4[%rNToGo170]
> %RDX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> CMP32mi8 %RDX<kill>, 1, %noreg, 24, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%rNToGo172]
> %EAX<def,tied1> = CMOVE32rr %EAX<kill,tied0>, %ECX<kill>, %EFLAGS<imp-use,kill>
> %ECX<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1]
> %ECX<def,tied1> = XOR32rr %ECX<kill,tied0>, %EAX<kill>, %EFLAGS<imp-def,dead>
> MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %CL, %ECX<imp-use,kill>; mem:ST1[%k1]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used179]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 1092, %noreg, %ECX<kill>; mem:ST4[%nblock_used179]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used181]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RCX<kill>, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock182]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> CMP32rr %EAX<kill>, %ECX<kill>, %EFLAGS<imp-def>
> JNE_1 <BB#36>, %EFLAGS<imp-use,kill>
5952B	BB#35: derived from LLVM BB %if.then.186
	    Predecessors according to CFG: BB#34
5968B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2
> JMP_1 <BB#2>
5984B	BB#36: derived from LLVM BB %if.end.187
	    Predecessors according to CFG: BB#34
6000B		%vreg756<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg756
6016B		%vreg754<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg754
6032B		CMP32rm %vreg756<kill>, %vreg754<kill>, 1, %noreg, 64, %noreg, %EFLAGS<imp-def>; mem:LD4[%k0189] GR32:%vreg756 GR64:%vreg754
6048B		JE_1 <BB#38>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#38 BB#37
> %EAX<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> CMP32rm %EAX<kill>, %RCX<kill>, 1, %noreg, 64, %noreg, %EFLAGS<imp-def>; mem:LD4[%k0189]
> JE_1 <BB#38>, %EFLAGS<imp-use,kill>
6064B	BB#37: derived from LLVM BB %if.then.192
	    Predecessors according to CFG: BB#36
6080B		%vreg924<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg924
6096B		%vreg922<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg922
6112B		MOV32mr %vreg922<kill>, 1, %noreg, 64, %noreg, %vreg924<kill>; mem:ST4[%k0194] GR64:%vreg922 GR32:%vreg924
6128B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2
> %EAX<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mr %RCX<kill>, 1, %noreg, 64, %noreg, %EAX<kill>; mem:ST4[%k0194]
> JMP_1 <BB#2>
6144B	BB#38: derived from LLVM BB %if.end.195
	    Predecessors according to CFG: BB#36
6160B		%vreg787<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg787
6176B		%vreg785:sub_32bit<def,read-undef> = MOV32rm %vreg787<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos196] GR64_NOSP:%vreg785 GR64:%vreg787
6208B		%vreg782<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg782
6224B		%vreg781<def> = MOV64rm %vreg782<kill>, 1, %noreg, 3152, %noreg; mem:LD8[%tt198] GR64:%vreg781,%vreg782
6240B		%vreg779<def> = MOV32rm %vreg781<kill>, 4, %vreg785<kill>, 0, %noreg; mem:LD4[%arrayidx199] GR32:%vreg779 GR64:%vreg781 GR64_NOSP:%vreg785
6256B		%vreg776<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg776
6272B		MOV32mr %vreg776<kill>, 1, %noreg, 60, %noreg, %vreg779<kill>; mem:ST4[%tPos200] GR64:%vreg776 GR32:%vreg779
6288B		%vreg773<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg773
6304B		%vreg770<def> = MOV32rm %vreg773<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos201] GR32:%vreg770 GR64:%vreg773
6336B		%vreg770<def,tied1> = AND32ri %vreg770<kill,tied0>, 255, %EFLAGS<imp-def,dead>; GR32:%vreg770
6368B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg770:sub_8bit<kill>; mem:ST1[%k1] GR32:%vreg770
6384B		%vreg765<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg765
6400B		%vreg763<def> = MOV32rm %vreg765, 1, %noreg, 60, %noreg; mem:LD4[%tPos204] GR32:%vreg763 GR64:%vreg765
6432B		%vreg763<def,tied1> = SHR32ri %vreg763<kill,tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg763
6448B		MOV32mr %vreg765<kill>, 1, %noreg, 60, %noreg, %vreg763<kill>; mem:ST4[%tPos204] GR64:%vreg765 GR32:%vreg763
6464B		%vreg759<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg759
6480B		CMP32mi8 %vreg759<kill>, 1, %noreg, 24, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%rNToGo206] GR64:%vreg759
6496B		JNE_1 <BB#42>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#42 BB#39
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 60, %noreg, %RAX<imp-def>; mem:LD4[%tPos196]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RCX<def> = MOV64rm %RCX<kill>, 1, %noreg, 3152, %noreg; mem:LD8[%tt198]
> %EAX<def> = MOV32rm %RCX<kill>, 4, %RAX<kill>, 0, %noreg; mem:LD4[%arrayidx199]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mr %RCX<kill>, 1, %noreg, 60, %noreg, %EAX<kill>; mem:ST4[%tPos200]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos201]
> %EAX<def,tied1> = AND32ri %EAX<kill,tied0>, 255, %EFLAGS<imp-def,dead>
> MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %AL, %EAX<imp-use,kill>; mem:ST1[%k1]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 60, %noreg; mem:LD4[%tPos204]
> %ECX<def,tied1> = SHR32ri %ECX<kill,tied0>, 8, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 60, %noreg, %ECX<kill>; mem:ST4[%tPos204]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> CMP32mi8 %RAX<kill>, 1, %noreg, 24, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%rNToGo206]
> JNE_1 <BB#42>, %EFLAGS<imp-use,kill>
6512B	BB#39: derived from LLVM BB %if.then.209
	    Predecessors according to CFG: BB#38
6528B		%vreg805<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg805
6544B		%vreg803<def> = MOVSX64rm32 %vreg805<kill>, 1, %noreg, 28, %noreg; mem:LD4[%rTPos210] GR64_NOSP:%vreg803 GR64:%vreg805
6560B		%vreg801<def> = MOV32rm %noreg, 4, %vreg803<kill>, <ga:@BZ2_rNums>, %noreg; mem:LD4[%arrayidx212] GR32:%vreg801 GR64_NOSP:%vreg803
6576B		%vreg799<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg799
6592B		MOV32mr %vreg799<kill>, 1, %noreg, 24, %noreg, %vreg801<kill>; mem:ST4[%rNToGo213] GR64:%vreg799 GR32:%vreg801
6608B		%vreg796<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg796
6624B		%vreg794<def> = MOV32rm %vreg796, 1, %noreg, 28, %noreg; mem:LD4[%rTPos214] GR32:%vreg794 GR64:%vreg796
6656B		%vreg794<def,tied1> = ADD32ri8 %vreg794<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg794
6672B		MOV32mr %vreg796<kill>, 1, %noreg, 28, %noreg, %vreg794<kill>; mem:ST4[%rTPos214] GR64:%vreg796 GR32:%vreg794
6688B		%vreg790<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg790
6704B		CMP32mi %vreg790<kill>, 1, %noreg, 28, %noreg, 512, %EFLAGS<imp-def>; mem:LD4[%rTPos216] GR64:%vreg790
6720B		JNE_1 <BB#41>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#41 BB#40
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RAX<def> = MOVSX64rm32 %RAX<kill>, 1, %noreg, 28, %noreg; mem:LD4[%rTPos210]
> %EAX<def> = MOV32rm %noreg, 4, %RAX<kill>, <ga:@BZ2_rNums>, %noreg; mem:LD4[%arrayidx212]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mr %RCX<kill>, 1, %noreg, 24, %noreg, %EAX<kill>; mem:ST4[%rNToGo213]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 28, %noreg; mem:LD4[%rTPos214]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 28, %noreg, %ECX<kill>; mem:ST4[%rTPos214]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> CMP32mi %RAX<kill>, 1, %noreg, 28, %noreg, 512, %EFLAGS<imp-def>; mem:LD4[%rTPos216]
> JNE_1 <BB#41>, %EFLAGS<imp-use,kill>
6736B	BB#40: derived from LLVM BB %if.then.219
	    Predecessors according to CFG: BB#39
6752B		%vreg807<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg807
6768B		MOV32mi %vreg807<kill>, 1, %noreg, 28, %noreg, 0; mem:ST4[%rTPos220] GR64:%vreg807
	    Successors according to CFG: BB#41
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 28, %noreg, 0; mem:ST4[%rTPos220]
6784B	BB#41: derived from LLVM BB %if.end.221
	    Predecessors according to CFG: BB#39 BB#40
6800B		JMP_1 <BB#42>
	    Successors according to CFG: BB#42
> JMP_1 <BB#42>
6816B	BB#42: derived from LLVM BB %if.end.222
	    Predecessors according to CFG: BB#38 BB#41
6832B		%vreg867<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg867
6848B		%vreg866<def> = MOV32ri 1; GR32:%vreg866
6864B		%vreg875<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg875
6880B		%vreg873<def> = MOV32rm %vreg875, 1, %noreg, 24, %noreg; mem:LD4[%rNToGo223] GR32:%vreg873 GR64:%vreg875
6912B		%vreg873<def,tied1> = ADD32ri8 %vreg873<kill,tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg873
6928B		MOV32mr %vreg875<kill>, 1, %noreg, 24, %noreg, %vreg873<kill>; mem:ST4[%rNToGo223] GR64:%vreg875 GR32:%vreg873
6944B		%vreg869<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg869
6960B		CMP32mi8 %vreg869<kill>, 1, %noreg, 24, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%rNToGo225] GR64:%vreg869
6992B		%vreg867<def,tied1> = CMOVE32rr %vreg867<kill,tied0>, %vreg866<kill>, %EFLAGS<imp-use,kill>; GR32:%vreg867,%vreg866
7008B		%vreg861<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg861
7040B		%vreg861<def,tied1> = XOR32rr %vreg861<kill,tied0>, %vreg867<kill>, %EFLAGS<imp-def,dead>; GR32:%vreg861,%vreg867
7072B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg861:sub_8bit<kill>; mem:ST1[%k1] GR32:%vreg861
7088B		%vreg855<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg855
7104B		%vreg853<def> = MOV32rm %vreg855, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used232] GR32:%vreg853 GR64:%vreg855
7136B		%vreg853<def,tied1> = ADD32ri8 %vreg853<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg853
7152B		MOV32mr %vreg855<kill>, 1, %noreg, 1092, %noreg, %vreg853<kill>; mem:ST4[%nblock_used232] GR64:%vreg855 GR32:%vreg853
7168B		%vreg847<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg847
7200B		%vreg847<def,tied1> = ADD32ri8 %vreg847<kill,tied0>, 4, %EFLAGS<imp-def,dead>; GR32:%vreg847
7216B		%vreg845<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg845
7232B		MOV32mr %vreg845<kill>, 1, %noreg, 16, %noreg, %vreg847<kill>; mem:ST4[%state_out_len236] GR64:%vreg845 GR32:%vreg847
7248B		%vreg842<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg842
7264B		%vreg840:sub_32bit<def,read-undef> = MOV32rm %vreg842<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos237] GR64_NOSP:%vreg840 GR64:%vreg842
7296B		%vreg837<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg837
7312B		%vreg836<def> = MOV64rm %vreg837<kill>, 1, %noreg, 3152, %noreg; mem:LD8[%tt239] GR64:%vreg836,%vreg837
7328B		%vreg834<def> = MOV32rm %vreg836<kill>, 4, %vreg840<kill>, 0, %noreg; mem:LD4[%arrayidx240] GR32:%vreg834 GR64:%vreg836 GR64_NOSP:%vreg840
7344B		%vreg831<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg831
7360B		MOV32mr %vreg831<kill>, 1, %noreg, 60, %noreg, %vreg834<kill>; mem:ST4[%tPos241] GR64:%vreg831 GR32:%vreg834
7376B		%vreg828<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg828
7392B		%vreg825<def> = MOV32rm %vreg828<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos242] GR32:%vreg825 GR64:%vreg828
7424B		%vreg825<def,tied1> = AND32ri %vreg825<kill,tied0>, 255, %EFLAGS<imp-def,dead>; GR32:%vreg825
7456B		%vreg821<def> = MOVZX32rr8 %vreg825:sub_8bit<kill>; GR32:%vreg821,%vreg825
7472B		%vreg819<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg819
7488B		MOV32mr %vreg819<kill>, 1, %noreg, 64, %noreg, %vreg821<kill>; mem:ST4[%k0246] GR64:%vreg819 GR32:%vreg821
7504B		%vreg816<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg816
7520B		%vreg814<def> = MOV32rm %vreg816, 1, %noreg, 60, %noreg; mem:LD4[%tPos247] GR32:%vreg814 GR64:%vreg816
7552B		%vreg814<def,tied1> = SHR32ri %vreg814<kill,tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg814
7568B		MOV32mr %vreg816<kill>, 1, %noreg, 60, %noreg, %vreg814<kill>; mem:ST4[%tPos247] GR64:%vreg816 GR32:%vreg814
7584B		%vreg810<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg810
7600B		CMP32mi8 %vreg810<kill>, 1, %noreg, 24, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%rNToGo249] GR64:%vreg810
7616B		JNE_1 <BB#46>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#46 BB#43
> %EAX<def> = MOV32r0 %EFLAGS<imp-def,dead>
> %ECX<def> = MOV32ri 1
> %RDX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ESI<def> = MOV32rm %RDX, 1, %noreg, 24, %noreg; mem:LD4[%rNToGo223]
> %ESI<def,tied1> = ADD32ri8 %ESI<kill,tied0>, -1, %EFLAGS<imp-def,dead>
> MOV32mr %RDX<kill>, 1, %noreg, 24, %noreg, %ESI<kill>; mem:ST4[%rNToGo223]
> %RDX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> CMP32mi8 %RDX<kill>, 1, %noreg, 24, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%rNToGo225]
> %EAX<def,tied1> = CMOVE32rr %EAX<kill,tied0>, %ECX<kill>, %EFLAGS<imp-use,kill>
> %ECX<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1]
> %ECX<def,tied1> = XOR32rr %ECX<kill,tied0>, %EAX<kill>, %EFLAGS<imp-def,dead>
> MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %CL, %ECX<imp-use,kill>; mem:ST1[%k1]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used232]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 1092, %noreg, %ECX<kill>; mem:ST4[%nblock_used232]
> %EAX<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1]
> %EAX<def,tied1> = ADD32ri8 %EAX<kill,tied0>, 4, %EFLAGS<imp-def,dead>
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mr %RCX<kill>, 1, %noreg, 16, %noreg, %EAX<kill>; mem:ST4[%state_out_len236]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 60, %noreg, %RAX<imp-def>; mem:LD4[%tPos237]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RCX<def> = MOV64rm %RCX<kill>, 1, %noreg, 3152, %noreg; mem:LD8[%tt239]
> %EAX<def> = MOV32rm %RCX<kill>, 4, %RAX<kill>, 0, %noreg; mem:LD4[%arrayidx240]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mr %RCX<kill>, 1, %noreg, 60, %noreg, %EAX<kill>; mem:ST4[%tPos241]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos242]
> %EAX<def,tied1> = AND32ri %EAX<kill,tied0>, 255, %EFLAGS<imp-def,dead>
> %EAX<def> = MOVZX32rr8 %AL, %EAX<imp-use,kill>
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mr %RCX<kill>, 1, %noreg, 64, %noreg, %EAX<kill>; mem:ST4[%k0246]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 60, %noreg; mem:LD4[%tPos247]
> %ECX<def,tied1> = SHR32ri %ECX<kill,tied0>, 8, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 60, %noreg, %ECX<kill>; mem:ST4[%tPos247]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> CMP32mi8 %RAX<kill>, 1, %noreg, 24, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%rNToGo249]
> JNE_1 <BB#46>, %EFLAGS<imp-use,kill>
7632B	BB#43: derived from LLVM BB %if.then.252
	    Predecessors according to CFG: BB#42
7648B		%vreg893<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg893
7664B		%vreg891<def> = MOVSX64rm32 %vreg893<kill>, 1, %noreg, 28, %noreg; mem:LD4[%rTPos253] GR64_NOSP:%vreg891 GR64:%vreg893
7680B		%vreg889<def> = MOV32rm %noreg, 4, %vreg891<kill>, <ga:@BZ2_rNums>, %noreg; mem:LD4[%arrayidx255] GR32:%vreg889 GR64_NOSP:%vreg891
7696B		%vreg887<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg887
7712B		MOV32mr %vreg887<kill>, 1, %noreg, 24, %noreg, %vreg889<kill>; mem:ST4[%rNToGo256] GR64:%vreg887 GR32:%vreg889
7728B		%vreg884<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg884
7744B		%vreg882<def> = MOV32rm %vreg884, 1, %noreg, 28, %noreg; mem:LD4[%rTPos257] GR32:%vreg882 GR64:%vreg884
7776B		%vreg882<def,tied1> = ADD32ri8 %vreg882<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg882
7792B		MOV32mr %vreg884<kill>, 1, %noreg, 28, %noreg, %vreg882<kill>; mem:ST4[%rTPos257] GR64:%vreg884 GR32:%vreg882
7808B		%vreg878<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg878
7824B		CMP32mi %vreg878<kill>, 1, %noreg, 28, %noreg, 512, %EFLAGS<imp-def>; mem:LD4[%rTPos259] GR64:%vreg878
7840B		JNE_1 <BB#45>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#45 BB#44
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RAX<def> = MOVSX64rm32 %RAX<kill>, 1, %noreg, 28, %noreg; mem:LD4[%rTPos253]
> %EAX<def> = MOV32rm %noreg, 4, %RAX<kill>, <ga:@BZ2_rNums>, %noreg; mem:LD4[%arrayidx255]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mr %RCX<kill>, 1, %noreg, 24, %noreg, %EAX<kill>; mem:ST4[%rNToGo256]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 28, %noreg; mem:LD4[%rTPos257]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 28, %noreg, %ECX<kill>; mem:ST4[%rTPos257]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> CMP32mi %RAX<kill>, 1, %noreg, 28, %noreg, 512, %EFLAGS<imp-def>; mem:LD4[%rTPos259]
> JNE_1 <BB#45>, %EFLAGS<imp-use,kill>
7856B	BB#44: derived from LLVM BB %if.then.262
	    Predecessors according to CFG: BB#43
7872B		%vreg895<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg895
7888B		MOV32mi %vreg895<kill>, 1, %noreg, 28, %noreg, 0; mem:ST4[%rTPos263] GR64:%vreg895
	    Successors according to CFG: BB#45
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 28, %noreg, 0; mem:ST4[%rTPos263]
7904B	BB#45: derived from LLVM BB %if.end.264
	    Predecessors according to CFG: BB#43 BB#44
7920B		JMP_1 <BB#46>
	    Successors according to CFG: BB#46
> JMP_1 <BB#46>
7936B	BB#46: derived from LLVM BB %if.end.265
	    Predecessors according to CFG: BB#42 BB#45
7952B		%vreg906<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg906
7968B		%vreg910<def> = MOV32ri 1; GR32:%vreg910
7984B		%vreg919<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg919
8000B		%vreg917<def> = MOV32rm %vreg919, 1, %noreg, 24, %noreg; mem:LD4[%rNToGo266] GR32:%vreg917 GR64:%vreg919
8032B		%vreg917<def,tied1> = ADD32ri8 %vreg917<kill,tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg917
8048B		MOV32mr %vreg919<kill>, 1, %noreg, 24, %noreg, %vreg917<kill>; mem:ST4[%rNToGo266] GR64:%vreg919 GR32:%vreg917
8064B		%vreg913<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg913
8080B		CMP32mi8 %vreg913<kill>, 1, %noreg, 24, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%rNToGo268] GR64:%vreg913
8112B		%vreg906<def,tied1> = CMOVE32rr %vreg906<kill,tied0>, %vreg910<kill>, %EFLAGS<imp-use,kill>; GR32:%vreg906,%vreg910
8128B		%vreg907<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg907
8160B		%vreg906<def,tied1> = XOR32rm %vreg906<kill,tied0>, %vreg907, 1, %noreg, 64, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%k0272] GR32:%vreg906 GR64:%vreg907
8176B		MOV32mr %vreg907<kill>, 1, %noreg, 64, %noreg, %vreg906<kill>; mem:ST4[%k0272] GR64:%vreg907 GR32:%vreg906
8192B		%vreg901<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg901
8208B		%vreg899<def> = MOV32rm %vreg901, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used274] GR32:%vreg899 GR64:%vreg901
8240B		%vreg899<def,tied1> = ADD32ri8 %vreg899<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg899
8256B		MOV32mr %vreg901<kill>, 1, %noreg, 1092, %noreg, %vreg899<kill>; mem:ST4[%nblock_used274] GR64:%vreg901 GR32:%vreg899
8272B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2
> %EAX<def> = MOV32r0 %EFLAGS<imp-def,dead>
> %ECX<def> = MOV32ri 1
> %RDX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ESI<def> = MOV32rm %RDX, 1, %noreg, 24, %noreg; mem:LD4[%rNToGo266]
> %ESI<def,tied1> = ADD32ri8 %ESI<kill,tied0>, -1, %EFLAGS<imp-def,dead>
> MOV32mr %RDX<kill>, 1, %noreg, 24, %noreg, %ESI<kill>; mem:ST4[%rNToGo266]
> %RDX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> CMP32mi8 %RDX<kill>, 1, %noreg, 24, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%rNToGo268]
> %EAX<def,tied1> = CMOVE32rr %EAX<kill,tied0>, %ECX<kill>, %EFLAGS<imp-use,kill>
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EAX<def,tied1> = XOR32rm %EAX<kill,tied0>, %RCX, 1, %noreg, 64, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%k0272]
> MOV32mr %RCX<kill>, 1, %noreg, 64, %noreg, %EAX<kill>; mem:ST4[%k0272]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used274]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 1092, %noreg, %ECX<kill>; mem:ST4[%nblock_used274]
> JMP_1 <BB#2>
8288B	BB#47: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#0
8304B		%vreg55<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg55
8320B		%vreg54<def> = MOV32rm %vreg55<kill>, 1, %noreg, 3184, %noreg; mem:LD4[%calculatedBlockCRC276] GR32:%vreg54 GR64:%vreg55
8336B		MOV32mr <fi#3>, 1, %noreg, 0, %noreg, %vreg54<kill>; mem:ST4[%c_calculatedBlockCRC] GR32:%vreg54
8352B		%vreg51<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg51
8368B		%vreg50<def> = MOV8rm %vreg51<kill>, 1, %noreg, 12, %noreg; mem:LD1[%state_out_ch277] GR8:%vreg50 GR64:%vreg51
8384B		MOV8mr <fi#4>, 1, %noreg, 0, %noreg, %vreg50<kill>; mem:ST1[%c_state_out_ch] GR8:%vreg50
8400B		%vreg47<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg47
8416B		%vreg46<def> = MOV32rm %vreg47<kill>, 1, %noreg, 16, %noreg; mem:LD4[%state_out_len278] GR32:%vreg46 GR64:%vreg47
8432B		MOV32mr <fi#5>, 1, %noreg, 0, %noreg, %vreg46<kill>; mem:ST4[%c_state_out_len] GR32:%vreg46
8448B		%vreg43<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg43
8464B		%vreg42<def> = MOV32rm %vreg43<kill>, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used279] GR32:%vreg42 GR64:%vreg43
8480B		MOV32mr <fi#6>, 1, %noreg, 0, %noreg, %vreg42<kill>; mem:ST4[%c_nblock_used] GR32:%vreg42
8496B		%vreg39<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg39
8512B		%vreg38<def> = MOV32rm %vreg39<kill>, 1, %noreg, 64, %noreg; mem:LD4[%k0280] GR32:%vreg38 GR64:%vreg39
8528B		MOV32mr <fi#7>, 1, %noreg, 0, %noreg, %vreg38<kill>; mem:ST4[%c_k0] GR32:%vreg38
8544B		%vreg35<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg35
8560B		%vreg34<def> = MOV64rm %vreg35<kill>, 1, %noreg, 3152, %noreg; mem:LD8[%tt281] GR64:%vreg34,%vreg35
8576B		MOV64mr <fi#8>, 1, %noreg, 0, %noreg, %vreg34<kill>; mem:ST8[%c_tt] GR64:%vreg34
8592B		%vreg31<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg31
8608B		%vreg30<def> = MOV32rm %vreg31<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos282] GR32:%vreg30 GR64:%vreg31
8624B		MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %vreg30<kill>; mem:ST4[%c_tPos] GR32:%vreg30
8640B		%vreg27<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg27
8656B		%vreg26<def> = MOV64rm %vreg27<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm283] GR64:%vreg26,%vreg27
8672B		%vreg24<def> = MOV64rm %vreg26<kill>, 1, %noreg, 24, %noreg; mem:LD8[%next_out284] GR64:%vreg24,%vreg26
8688B		MOV64mr <fi#10>, 1, %noreg, 0, %noreg, %vreg24<kill>; mem:ST8[%cs_next_out] GR64:%vreg24
8704B		%vreg21<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg21
8720B		%vreg20<def> = MOV64rm %vreg21<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm285] GR64:%vreg20,%vreg21
8736B		%vreg18<def> = MOV32rm %vreg20<kill>, 1, %noreg, 32, %noreg; mem:LD4[%avail_out286] GR32:%vreg18 GR64:%vreg20
8752B		MOV32mr <fi#11>, 1, %noreg, 0, %noreg, %vreg18<kill>; mem:ST4[%cs_avail_out] GR32:%vreg18
8768B		%vreg15<def> = MOV32rm <fi#11>, 1, %noreg, 0, %noreg; mem:LD4[%cs_avail_out] GR32:%vreg15
8784B		MOV32mr <fi#12>, 1, %noreg, 0, %noreg, %vreg15<kill>; mem:ST4[%avail_out_INIT] GR32:%vreg15
8800B		%vreg13<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg13
8816B		%vreg10<def> = MOV32rm %vreg13<kill>, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock287] GR32:%vreg10 GR64:%vreg13
8848B		%vreg10<def,tied1> = ADD32ri8 %vreg10<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg10
8864B		MOV32mr <fi#13>, 1, %noreg, 0, %noreg, %vreg10<kill>; mem:ST4[%s_save_nblockPP] GR32:%vreg10
	    Successors according to CFG: BB#48
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 3184, %noreg; mem:LD4[%calculatedBlockCRC276]
> MOV32mr <fi#3>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%c_calculatedBlockCRC]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %AL<def> = MOV8rm %RAX<kill>, 1, %noreg, 12, %noreg; mem:LD1[%state_out_ch277]
> MOV8mr <fi#4>, 1, %noreg, 0, %noreg, %AL<kill>; mem:ST1[%c_state_out_ch]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 16, %noreg; mem:LD4[%state_out_len278]
> MOV32mr <fi#5>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%c_state_out_len]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 1092, %noreg; mem:LD4[%nblock_used279]
> MOV32mr <fi#6>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%c_nblock_used]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 64, %noreg; mem:LD4[%k0280]
> MOV32mr <fi#7>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%c_k0]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 3152, %noreg; mem:LD8[%tt281]
> MOV64mr <fi#8>, 1, %noreg, 0, %noreg, %RAX<kill>; mem:ST8[%c_tt]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 60, %noreg; mem:LD4[%tPos282]
> MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%c_tPos]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm283]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 24, %noreg; mem:LD8[%next_out284]
> MOV64mr <fi#10>, 1, %noreg, 0, %noreg, %RAX<kill>; mem:ST8[%cs_next_out]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm285]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 32, %noreg; mem:LD4[%avail_out286]
> MOV32mr <fi#11>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%cs_avail_out]
> %EAX<def> = MOV32rm <fi#11>, 1, %noreg, 0, %noreg; mem:LD4[%cs_avail_out]
> MOV32mr <fi#12>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%avail_out_INIT]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 64080, %noreg; mem:LD4[%save_nblock287]
> %EAX<def,tied1> = ADD32ri8 %EAX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV32mr <fi#13>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%s_save_nblockPP]
8880B	BB#48: derived from LLVM BB %while.body.289
	    Predecessors according to CFG: BB#47 BB#75 BB#74 BB#72 BB#70 BB#68
8896B		CMP32mi8 <fi#5>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%c_state_out_len]
8912B		JLE_1 <BB#59>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#59 BB#49
> CMP32mi8 <fi#5>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%c_state_out_len]
> JLE_1 <BB#59>, %EFLAGS<imp-use,kill>
8928B	BB#49: derived from LLVM BB %if.then.292
	    Predecessors according to CFG: BB#48
8944B		JMP_1 <BB#50>
	    Successors according to CFG: BB#50
> JMP_1 <BB#50>
8960B	BB#50: derived from LLVM BB %while.body.294
	    Predecessors according to CFG: BB#49 BB#54
8976B		CMP32mi8 <fi#11>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%cs_avail_out]
8992B		JNE_1 <BB#52>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#52 BB#51
> CMP32mi8 <fi#11>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%cs_avail_out]
> JNE_1 <BB#52>, %EFLAGS<imp-use,kill>
9008B	BB#51: derived from LLVM BB %if.then.297
	    Predecessors according to CFG: BB#50
9024B		JMP_1 <BB#76>
	    Successors according to CFG: BB#76
> JMP_1 <BB#76>
9040B	BB#52: derived from LLVM BB %if.end.298
	    Predecessors according to CFG: BB#50
9056B		CMP32mi8 <fi#5>, 1, %noreg, 0, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%c_state_out_len]
9072B		JNE_1 <BB#54>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#54 BB#53
> CMP32mi8 <fi#5>, 1, %noreg, 0, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%c_state_out_len]
> JNE_1 <BB#54>, %EFLAGS<imp-use,kill>
9088B	BB#53: derived from LLVM BB %if.then.301
	    Predecessors according to CFG: BB#52
9104B		JMP_1 <BB#55>
	    Successors according to CFG: BB#55
> JMP_1 <BB#55>
9120B	BB#54: derived from LLVM BB %if.end.302
	    Predecessors according to CFG: BB#52
9136B		%vreg93<def> = MOV8rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD1[%c_state_out_ch] GR8:%vreg93
9152B		%vreg92<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%cs_next_out] GR64:%vreg92
9168B		MOV8mr %vreg92<kill>, 1, %noreg, 0, %noreg, %vreg93<kill>; mem:ST1[%249] GR64:%vreg92 GR8:%vreg93
9184B		%vreg74<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%c_calculatedBlockCRC] GR32:%vreg74
9216B		%vreg74<def,tied1> = SHL32ri %vreg74<kill,tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg74
9232B		%vreg81<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%c_calculatedBlockCRC] GR32:%vreg81
9264B		%vreg81<def,tied1> = SHR32ri %vreg81<kill,tied0>, 24, %EFLAGS<imp-def,dead>; GR32:%vreg81
9280B		%vreg83<def> = MOVZX32rm8 <fi#4>, 1, %noreg, 0, %noreg; mem:LD1[%c_state_out_ch] GR32:%vreg83
9312B		%vreg81<def,tied1> = XOR32rr %vreg81<kill,tied0>, %vreg83<kill>, %EFLAGS<imp-def,dead>; GR32:%vreg81,%vreg83
9328B		%vreg78:sub_32bit<def,read-undef> = MOV32rr %vreg81<kill>; GR64_NOSP:%vreg78 GR32:%vreg81
9376B		%vreg74<def,tied1> = XOR32rm %vreg74<kill,tied0>, %noreg, 4, %vreg78<kill>, <ga:@BZ2_crc32Table>, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%arrayidx308] GR32:%vreg74 GR64_NOSP:%vreg78
9392B		MOV32mr <fi#3>, 1, %noreg, 0, %noreg, %vreg74<kill>; mem:ST4[%c_calculatedBlockCRC] GR32:%vreg74
9408B		%vreg69<def> = MOV32rm <fi#5>, 1, %noreg, 0, %noreg; mem:LD4[%c_state_out_len] GR32:%vreg69
9440B		%vreg69<def,tied1> = ADD32ri8 %vreg69<kill,tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg69
9456B		MOV32mr <fi#5>, 1, %noreg, 0, %noreg, %vreg69<kill>; mem:ST4[%c_state_out_len] GR32:%vreg69
9472B		%vreg65<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%cs_next_out] GR64:%vreg65
9504B		%vreg65<def,tied1> = ADD64ri8 %vreg65<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR64:%vreg65
9520B		MOV64mr <fi#10>, 1, %noreg, 0, %noreg, %vreg65<kill>; mem:ST8[%cs_next_out] GR64:%vreg65
9536B		%vreg61<def> = MOV32rm <fi#11>, 1, %noreg, 0, %noreg; mem:LD4[%cs_avail_out] GR32:%vreg61
9568B		%vreg61<def,tied1> = ADD32ri8 %vreg61<kill,tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg61
9584B		MOV32mr <fi#11>, 1, %noreg, 0, %noreg, %vreg61<kill>; mem:ST4[%cs_avail_out] GR32:%vreg61
9600B		JMP_1 <BB#50>
	    Successors according to CFG: BB#50
> %AL<def> = MOV8rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD1[%c_state_out_ch]
> %RCX<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%cs_next_out]
> MOV8mr %RCX<kill>, 1, %noreg, 0, %noreg, %AL<kill>; mem:ST1[%249]
> %EAX<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%c_calculatedBlockCRC]
> %EAX<def,tied1> = SHL32ri %EAX<kill,tied0>, 8, %EFLAGS<imp-def,dead>
> %ECX<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%c_calculatedBlockCRC]
> %ECX<def,tied1> = SHR32ri %ECX<kill,tied0>, 24, %EFLAGS<imp-def,dead>
> %EDX<def> = MOVZX32rm8 <fi#4>, 1, %noreg, 0, %noreg; mem:LD1[%c_state_out_ch]
> %ECX<def,tied1> = XOR32rr %ECX<kill,tied0>, %EDX<kill>, %EFLAGS<imp-def,dead>
> %ECX<def> = MOV32rr %ECX<kill>, %RCX<imp-def>
> %EAX<def,tied1> = XOR32rm %EAX<kill,tied0>, %noreg, 4, %RCX<kill>, <ga:@BZ2_crc32Table>, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%arrayidx308]
> MOV32mr <fi#3>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%c_calculatedBlockCRC]
> %EAX<def> = MOV32rm <fi#5>, 1, %noreg, 0, %noreg; mem:LD4[%c_state_out_len]
> %EAX<def,tied1> = ADD32ri8 %EAX<kill,tied0>, -1, %EFLAGS<imp-def,dead>
> MOV32mr <fi#5>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%c_state_out_len]
> %RAX<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%cs_next_out]
> %RAX<def,tied1> = ADD64ri8 %RAX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV64mr <fi#10>, 1, %noreg, 0, %noreg, %RAX<kill>; mem:ST8[%cs_next_out]
> %EAX<def> = MOV32rm <fi#11>, 1, %noreg, 0, %noreg; mem:LD4[%cs_avail_out]
> %EAX<def,tied1> = ADD32ri8 %EAX<kill,tied0>, -1, %EFLAGS<imp-def,dead>
> MOV32mr <fi#11>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%cs_avail_out]
> JMP_1 <BB#50>
9616B	BB#55: derived from LLVM BB %while.end.313
	    Predecessors according to CFG: BB#53
9632B		JMP_1 <BB#56>
	    Successors according to CFG: BB#56
> JMP_1 <BB#56>
9648B	BB#56: derived from LLVM BB %s_state_out_len_eq_one
	    Predecessors according to CFG: BB#55 BB#66 BB#64
9664B		CMP32mi8 <fi#11>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%cs_avail_out]
9680B		JNE_1 <BB#58>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#58 BB#57
> CMP32mi8 <fi#11>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%cs_avail_out]
> JNE_1 <BB#58>, %EFLAGS<imp-use,kill>
9696B	BB#57: derived from LLVM BB %if.then.316
	    Predecessors according to CFG: BB#56
9712B		MOV32mi <fi#5>, 1, %noreg, 0, %noreg, 1; mem:ST4[%c_state_out_len]
9728B		JMP_1 <BB#76>
	    Successors according to CFG: BB#76
> MOV32mi <fi#5>, 1, %noreg, 0, %noreg, 1; mem:ST4[%c_state_out_len]
> JMP_1 <BB#76>
9744B	BB#58: derived from LLVM BB %if.end.317
	    Predecessors according to CFG: BB#56
9760B		%vreg125<def> = MOV8rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD1[%c_state_out_ch] GR8:%vreg125
9776B		%vreg124<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%cs_next_out] GR64:%vreg124
9792B		MOV8mr %vreg124<kill>, 1, %noreg, 0, %noreg, %vreg125<kill>; mem:ST1[%259] GR64:%vreg124 GR8:%vreg125
9808B		%vreg106<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%c_calculatedBlockCRC] GR32:%vreg106
9840B		%vreg106<def,tied1> = SHL32ri %vreg106<kill,tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg106
9856B		%vreg113<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%c_calculatedBlockCRC] GR32:%vreg113
9888B		%vreg113<def,tied1> = SHR32ri %vreg113<kill,tied0>, 24, %EFLAGS<imp-def,dead>; GR32:%vreg113
9904B		%vreg115<def> = MOVZX32rm8 <fi#4>, 1, %noreg, 0, %noreg; mem:LD1[%c_state_out_ch] GR32:%vreg115
9936B		%vreg113<def,tied1> = XOR32rr %vreg113<kill,tied0>, %vreg115<kill>, %EFLAGS<imp-def,dead>; GR32:%vreg113,%vreg115
9952B		%vreg110:sub_32bit<def,read-undef> = MOV32rr %vreg113<kill>; GR64_NOSP:%vreg110 GR32:%vreg113
10000B		%vreg106<def,tied1> = XOR32rm %vreg106<kill,tied0>, %noreg, 4, %vreg110<kill>, <ga:@BZ2_crc32Table>, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%arrayidx323] GR32:%vreg106 GR64_NOSP:%vreg110
10016B		MOV32mr <fi#3>, 1, %noreg, 0, %noreg, %vreg106<kill>; mem:ST4[%c_calculatedBlockCRC] GR32:%vreg106
10032B		%vreg101<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%cs_next_out] GR64:%vreg101
10064B		%vreg101<def,tied1> = ADD64ri8 %vreg101<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR64:%vreg101
10080B		MOV64mr <fi#10>, 1, %noreg, 0, %noreg, %vreg101<kill>; mem:ST8[%cs_next_out] GR64:%vreg101
10096B		%vreg97<def> = MOV32rm <fi#11>, 1, %noreg, 0, %noreg; mem:LD4[%cs_avail_out] GR32:%vreg97
10128B		%vreg97<def,tied1> = ADD32ri8 %vreg97<kill,tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg97
10144B		MOV32mr <fi#11>, 1, %noreg, 0, %noreg, %vreg97<kill>; mem:ST4[%cs_avail_out] GR32:%vreg97
	    Successors according to CFG: BB#59
> %AL<def> = MOV8rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD1[%c_state_out_ch]
> %RCX<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%cs_next_out]
> MOV8mr %RCX<kill>, 1, %noreg, 0, %noreg, %AL<kill>; mem:ST1[%259]
> %EAX<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%c_calculatedBlockCRC]
> %EAX<def,tied1> = SHL32ri %EAX<kill,tied0>, 8, %EFLAGS<imp-def,dead>
> %ECX<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%c_calculatedBlockCRC]
> %ECX<def,tied1> = SHR32ri %ECX<kill,tied0>, 24, %EFLAGS<imp-def,dead>
> %EDX<def> = MOVZX32rm8 <fi#4>, 1, %noreg, 0, %noreg; mem:LD1[%c_state_out_ch]
> %ECX<def,tied1> = XOR32rr %ECX<kill,tied0>, %EDX<kill>, %EFLAGS<imp-def,dead>
> %ECX<def> = MOV32rr %ECX<kill>, %RCX<imp-def>
> %EAX<def,tied1> = XOR32rm %EAX<kill,tied0>, %noreg, 4, %RCX<kill>, <ga:@BZ2_crc32Table>, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%arrayidx323]
> MOV32mr <fi#3>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%c_calculatedBlockCRC]
> %RAX<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%cs_next_out]
> %RAX<def,tied1> = ADD64ri8 %RAX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV64mr <fi#10>, 1, %noreg, 0, %noreg, %RAX<kill>; mem:ST8[%cs_next_out]
> %EAX<def> = MOV32rm <fi#11>, 1, %noreg, 0, %noreg; mem:LD4[%cs_avail_out]
> %EAX<def,tied1> = ADD32ri8 %EAX<kill,tied0>, -1, %EFLAGS<imp-def,dead>
> MOV32mr <fi#11>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%cs_avail_out]
10160B	BB#59: derived from LLVM BB %if.end.327
	    Predecessors according to CFG: BB#48 BB#58
10176B		%vreg128<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%c_nblock_used] GR32:%vreg128
10192B		CMP32rm %vreg128<kill>, <fi#13>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD4[%s_save_nblockPP] GR32:%vreg128
10208B		JLE_1 <BB#61>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#61 BB#60
> %EAX<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%c_nblock_used]
> CMP32rm %EAX<kill>, <fi#13>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD4[%s_save_nblockPP]
> JLE_1 <BB#61>, %EFLAGS<imp-use,kill>
10224B	BB#60: derived from LLVM BB %if.then.330
	    Predecessors according to CFG: BB#59
10240B		MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 1; mem:ST1[%retval]
10256B		JMP_1 <BB#80>
	    Successors according to CFG: BB#80
> MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 1; mem:ST1[%retval]
> JMP_1 <BB#80>
10272B	BB#61: derived from LLVM BB %if.end.331
	    Predecessors according to CFG: BB#59
10288B		%vreg131<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%c_nblock_used] GR32:%vreg131
10304B		CMP32rm %vreg131<kill>, <fi#13>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD4[%s_save_nblockPP] GR32:%vreg131
10320B		JNE_1 <BB#63>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#63 BB#62
> %EAX<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%c_nblock_used]
> CMP32rm %EAX<kill>, <fi#13>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD4[%s_save_nblockPP]
> JNE_1 <BB#63>, %EFLAGS<imp-use,kill>
10336B	BB#62: derived from LLVM BB %if.then.334
	    Predecessors according to CFG: BB#61
10352B		MOV32mi <fi#5>, 1, %noreg, 0, %noreg, 0; mem:ST4[%c_state_out_len]
10368B		JMP_1 <BB#76>
	    Successors according to CFG: BB#76
> MOV32mi <fi#5>, 1, %noreg, 0, %noreg, 0; mem:ST4[%c_state_out_len]
> JMP_1 <BB#76>
10384B	BB#63: derived from LLVM BB %if.end.335
	    Predecessors according to CFG: BB#61
10400B		%vreg161<def> = MOV32rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD4[%c_k0] GR32:%vreg161
10432B		MOV8mr <fi#4>, 1, %noreg, 0, %noreg, %vreg161:sub_8bit<kill>; mem:ST1[%c_state_out_ch] GR32:%vreg161
10448B		%vreg157:sub_32bit<def,read-undef> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR64_NOSP:%vreg157
10480B		%vreg154<def> = MOV64rm <fi#8>, 1, %noreg, 0, %noreg; mem:LD8[%c_tt] GR64:%vreg154
10496B		%vreg153<def> = MOV32rm %vreg154<kill>, 4, %vreg157<kill>, 0, %noreg; mem:LD4[%arrayidx338] GR32:%vreg153 GR64:%vreg154 GR64_NOSP:%vreg157
10512B		MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %vreg153<kill>; mem:ST4[%c_tPos] GR32:%vreg153
10528B		%vreg148<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR32:%vreg148
10560B		%vreg148<def,tied1> = AND32ri %vreg148<kill,tied0>, 255, %EFLAGS<imp-def,dead>; GR32:%vreg148
10592B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg148:sub_8bit<kill>; mem:ST1[%k1] GR32:%vreg148
10608B		%vreg142<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR32:%vreg142
10640B		%vreg142<def,tied1> = SHR32ri %vreg142<kill,tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg142
10656B		MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %vreg142<kill>; mem:ST4[%c_tPos] GR32:%vreg142
10672B		%vreg138<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%c_nblock_used] GR32:%vreg138
10704B		%vreg138<def,tied1> = ADD32ri8 %vreg138<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg138
10720B		MOV32mr <fi#6>, 1, %noreg, 0, %noreg, %vreg138<kill>; mem:ST4[%c_nblock_used] GR32:%vreg138
10736B		%vreg135<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg135
10752B		CMP32rm %vreg135<kill>, <fi#7>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD4[%c_k0] GR32:%vreg135
10768B		JE_1 <BB#65>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#65 BB#64
> %EAX<def> = MOV32rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD4[%c_k0]
> MOV8mr <fi#4>, 1, %noreg, 0, %noreg, %AL, %EAX<imp-use,kill>; mem:ST1[%c_state_out_ch]
> %EAX<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg, %RAX<imp-def>; mem:LD4[%c_tPos]
> %RCX<def> = MOV64rm <fi#8>, 1, %noreg, 0, %noreg; mem:LD8[%c_tt]
> %EAX<def> = MOV32rm %RCX<kill>, 4, %RAX<kill>, 0, %noreg; mem:LD4[%arrayidx338]
> MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%c_tPos]
> %EAX<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos]
> %EAX<def,tied1> = AND32ri %EAX<kill,tied0>, 255, %EFLAGS<imp-def,dead>
> MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %AL, %EAX<imp-use,kill>; mem:ST1[%k1]
> %EAX<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos]
> %EAX<def,tied1> = SHR32ri %EAX<kill,tied0>, 8, %EFLAGS<imp-def,dead>
> MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%c_tPos]
> %EAX<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%c_nblock_used]
> %EAX<def,tied1> = ADD32ri8 %EAX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV32mr <fi#6>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%c_nblock_used]
> %EAX<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1]
> CMP32rm %EAX<kill>, <fi#7>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD4[%c_k0]
> JE_1 <BB#65>, %EFLAGS<imp-use,kill>
10784B	BB#64: derived from LLVM BB %if.then.346
	    Predecessors according to CFG: BB#63
10800B		%vreg282<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg282
10816B		MOV32mr <fi#7>, 1, %noreg, 0, %noreg, %vreg282<kill>; mem:ST4[%c_k0] GR32:%vreg282
10832B		JMP_1 <BB#56>
	    Successors according to CFG: BB#56
> %EAX<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1]
> MOV32mr <fi#7>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%c_k0]
> JMP_1 <BB#56>
10848B	BB#65: derived from LLVM BB %if.end.348
	    Predecessors according to CFG: BB#63
10864B		%vreg164<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%c_nblock_used] GR32:%vreg164
10880B		CMP32rm %vreg164<kill>, <fi#13>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD4[%s_save_nblockPP] GR32:%vreg164
10896B		JNE_1 <BB#67>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#67 BB#66
> %EAX<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%c_nblock_used]
> CMP32rm %EAX<kill>, <fi#13>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD4[%s_save_nblockPP]
> JNE_1 <BB#67>, %EFLAGS<imp-use,kill>
10912B	BB#66: derived from LLVM BB %if.then.351
	    Predecessors according to CFG: BB#65
10928B		JMP_1 <BB#56>
	    Successors according to CFG: BB#56
> JMP_1 <BB#56>
10944B	BB#67: derived from LLVM BB %if.end.352
	    Predecessors according to CFG: BB#65
10960B		MOV32mi <fi#5>, 1, %noreg, 0, %noreg, 2; mem:ST4[%c_state_out_len]
10976B		%vreg189:sub_32bit<def,read-undef> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR64_NOSP:%vreg189
11008B		%vreg186<def> = MOV64rm <fi#8>, 1, %noreg, 0, %noreg; mem:LD8[%c_tt] GR64:%vreg186
11024B		%vreg185<def> = MOV32rm %vreg186<kill>, 4, %vreg189<kill>, 0, %noreg; mem:LD4[%arrayidx354] GR32:%vreg185 GR64:%vreg186 GR64_NOSP:%vreg189
11040B		MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %vreg185<kill>; mem:ST4[%c_tPos] GR32:%vreg185
11056B		%vreg180<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR32:%vreg180
11088B		%vreg180<def,tied1> = AND32ri %vreg180<kill,tied0>, 255, %EFLAGS<imp-def,dead>; GR32:%vreg180
11120B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg180:sub_8bit<kill>; mem:ST1[%k1] GR32:%vreg180
11136B		%vreg174<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR32:%vreg174
11168B		%vreg174<def,tied1> = SHR32ri %vreg174<kill,tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg174
11184B		MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %vreg174<kill>; mem:ST4[%c_tPos] GR32:%vreg174
11200B		%vreg170<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%c_nblock_used] GR32:%vreg170
11232B		%vreg170<def,tied1> = ADD32ri8 %vreg170<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg170
11248B		MOV32mr <fi#6>, 1, %noreg, 0, %noreg, %vreg170<kill>; mem:ST4[%c_nblock_used] GR32:%vreg170
11264B		%vreg167<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%c_nblock_used] GR32:%vreg167
11280B		CMP32rm %vreg167<kill>, <fi#13>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD4[%s_save_nblockPP] GR32:%vreg167
11296B		JNE_1 <BB#69>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#69 BB#68
> MOV32mi <fi#5>, 1, %noreg, 0, %noreg, 2; mem:ST4[%c_state_out_len]
> %EAX<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg, %RAX<imp-def>; mem:LD4[%c_tPos]
> %RCX<def> = MOV64rm <fi#8>, 1, %noreg, 0, %noreg; mem:LD8[%c_tt]
> %EAX<def> = MOV32rm %RCX<kill>, 4, %RAX<kill>, 0, %noreg; mem:LD4[%arrayidx354]
> MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%c_tPos]
> %EAX<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos]
> %EAX<def,tied1> = AND32ri %EAX<kill,tied0>, 255, %EFLAGS<imp-def,dead>
> MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %AL, %EAX<imp-use,kill>; mem:ST1[%k1]
> %EAX<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos]
> %EAX<def,tied1> = SHR32ri %EAX<kill,tied0>, 8, %EFLAGS<imp-def,dead>
> MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%c_tPos]
> %EAX<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%c_nblock_used]
> %EAX<def,tied1> = ADD32ri8 %EAX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV32mr <fi#6>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%c_nblock_used]
> %EAX<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%c_nblock_used]
> CMP32rm %EAX<kill>, <fi#13>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD4[%s_save_nblockPP]
> JNE_1 <BB#69>, %EFLAGS<imp-use,kill>
11312B	BB#68: derived from LLVM BB %if.then.361
	    Predecessors according to CFG: BB#67
11328B		JMP_1 <BB#48>
	    Successors according to CFG: BB#48
> JMP_1 <BB#48>
11344B	BB#69: derived from LLVM BB %if.end.362
	    Predecessors according to CFG: BB#67
11360B		%vreg193<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg193
11376B		CMP32rm %vreg193<kill>, <fi#7>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD4[%c_k0] GR32:%vreg193
11392B		JE_1 <BB#71>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#71 BB#70
> %EAX<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1]
> CMP32rm %EAX<kill>, <fi#7>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD4[%c_k0]
> JE_1 <BB#71>, %EFLAGS<imp-use,kill>
11408B	BB#70: derived from LLVM BB %if.then.366
	    Predecessors according to CFG: BB#69
11424B		%vreg279<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg279
11440B		MOV32mr <fi#7>, 1, %noreg, 0, %noreg, %vreg279<kill>; mem:ST4[%c_k0] GR32:%vreg279
11456B		JMP_1 <BB#48>
	    Successors according to CFG: BB#48
> %EAX<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1]
> MOV32mr <fi#7>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%c_k0]
> JMP_1 <BB#48>
11472B	BB#71: derived from LLVM BB %if.end.368
	    Predecessors according to CFG: BB#69
11488B		MOV32mi <fi#5>, 1, %noreg, 0, %noreg, 3; mem:ST4[%c_state_out_len]
11504B		%vreg218:sub_32bit<def,read-undef> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR64_NOSP:%vreg218
11536B		%vreg215<def> = MOV64rm <fi#8>, 1, %noreg, 0, %noreg; mem:LD8[%c_tt] GR64:%vreg215
11552B		%vreg214<def> = MOV32rm %vreg215<kill>, 4, %vreg218<kill>, 0, %noreg; mem:LD4[%arrayidx370] GR32:%vreg214 GR64:%vreg215 GR64_NOSP:%vreg218
11568B		MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %vreg214<kill>; mem:ST4[%c_tPos] GR32:%vreg214
11584B		%vreg209<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR32:%vreg209
11616B		%vreg209<def,tied1> = AND32ri %vreg209<kill,tied0>, 255, %EFLAGS<imp-def,dead>; GR32:%vreg209
11648B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg209:sub_8bit<kill>; mem:ST1[%k1] GR32:%vreg209
11664B		%vreg203<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR32:%vreg203
11696B		%vreg203<def,tied1> = SHR32ri %vreg203<kill,tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg203
11712B		MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %vreg203<kill>; mem:ST4[%c_tPos] GR32:%vreg203
11728B		%vreg199<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%c_nblock_used] GR32:%vreg199
11760B		%vreg199<def,tied1> = ADD32ri8 %vreg199<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg199
11776B		MOV32mr <fi#6>, 1, %noreg, 0, %noreg, %vreg199<kill>; mem:ST4[%c_nblock_used] GR32:%vreg199
11792B		%vreg196<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%c_nblock_used] GR32:%vreg196
11808B		CMP32rm %vreg196<kill>, <fi#13>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD4[%s_save_nblockPP] GR32:%vreg196
11824B		JNE_1 <BB#73>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#73 BB#72
> MOV32mi <fi#5>, 1, %noreg, 0, %noreg, 3; mem:ST4[%c_state_out_len]
> %EAX<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg, %RAX<imp-def>; mem:LD4[%c_tPos]
> %RCX<def> = MOV64rm <fi#8>, 1, %noreg, 0, %noreg; mem:LD8[%c_tt]
> %EAX<def> = MOV32rm %RCX<kill>, 4, %RAX<kill>, 0, %noreg; mem:LD4[%arrayidx370]
> MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%c_tPos]
> %EAX<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos]
> %EAX<def,tied1> = AND32ri %EAX<kill,tied0>, 255, %EFLAGS<imp-def,dead>
> MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %AL, %EAX<imp-use,kill>; mem:ST1[%k1]
> %EAX<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos]
> %EAX<def,tied1> = SHR32ri %EAX<kill,tied0>, 8, %EFLAGS<imp-def,dead>
> MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%c_tPos]
> %EAX<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%c_nblock_used]
> %EAX<def,tied1> = ADD32ri8 %EAX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV32mr <fi#6>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%c_nblock_used]
> %EAX<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%c_nblock_used]
> CMP32rm %EAX<kill>, <fi#13>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD4[%s_save_nblockPP]
> JNE_1 <BB#73>, %EFLAGS<imp-use,kill>
11840B	BB#72: derived from LLVM BB %if.then.377
	    Predecessors according to CFG: BB#71
11856B		JMP_1 <BB#48>
	    Successors according to CFG: BB#48
> JMP_1 <BB#48>
11872B	BB#73: derived from LLVM BB %if.end.378
	    Predecessors according to CFG: BB#71
11888B		%vreg222<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg222
11904B		CMP32rm %vreg222<kill>, <fi#7>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD4[%c_k0] GR32:%vreg222
11920B		JE_1 <BB#75>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#75 BB#74
> %EAX<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1]
> CMP32rm %EAX<kill>, <fi#7>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD4[%c_k0]
> JE_1 <BB#75>, %EFLAGS<imp-use,kill>
11936B	BB#74: derived from LLVM BB %if.then.382
	    Predecessors according to CFG: BB#73
11952B		%vreg276<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg276
11968B		MOV32mr <fi#7>, 1, %noreg, 0, %noreg, %vreg276<kill>; mem:ST4[%c_k0] GR32:%vreg276
11984B		JMP_1 <BB#48>
	    Successors according to CFG: BB#48
> %EAX<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1]
> MOV32mr <fi#7>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%c_k0]
> JMP_1 <BB#48>
12000B	BB#75: derived from LLVM BB %if.end.384
	    Predecessors according to CFG: BB#73
12016B		%vreg273:sub_32bit<def,read-undef> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR64_NOSP:%vreg273
12048B		%vreg270<def> = MOV64rm <fi#8>, 1, %noreg, 0, %noreg; mem:LD8[%c_tt] GR64:%vreg270
12064B		%vreg269<def> = MOV32rm %vreg270<kill>, 4, %vreg273<kill>, 0, %noreg; mem:LD4[%arrayidx386] GR32:%vreg269 GR64:%vreg270 GR64_NOSP:%vreg273
12080B		MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %vreg269<kill>; mem:ST4[%c_tPos] GR32:%vreg269
12096B		%vreg264<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR32:%vreg264
12128B		%vreg264<def,tied1> = AND32ri %vreg264<kill,tied0>, 255, %EFLAGS<imp-def,dead>; GR32:%vreg264
12160B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg264:sub_8bit<kill>; mem:ST1[%k1] GR32:%vreg264
12176B		%vreg258<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR32:%vreg258
12208B		%vreg258<def,tied1> = SHR32ri %vreg258<kill,tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg258
12224B		MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %vreg258<kill>; mem:ST4[%c_tPos] GR32:%vreg258
12240B		%vreg254<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%c_nblock_used] GR32:%vreg254
12272B		%vreg254<def,tied1> = ADD32ri8 %vreg254<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg254
12288B		MOV32mr <fi#6>, 1, %noreg, 0, %noreg, %vreg254<kill>; mem:ST4[%c_nblock_used] GR32:%vreg254
12304B		%vreg249<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1] GR32:%vreg249
12336B		%vreg249<def,tied1> = ADD32ri8 %vreg249<kill,tied0>, 4, %EFLAGS<imp-def,dead>; GR32:%vreg249
12352B		MOV32mr <fi#5>, 1, %noreg, 0, %noreg, %vreg249<kill>; mem:ST4[%c_state_out_len] GR32:%vreg249
12368B		%vreg246:sub_32bit<def,read-undef> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR64_NOSP:%vreg246
12400B		%vreg243<def> = MOV64rm <fi#8>, 1, %noreg, 0, %noreg; mem:LD8[%c_tt] GR64:%vreg243
12416B		%vreg242<def> = MOV32rm %vreg243<kill>, 4, %vreg246<kill>, 0, %noreg; mem:LD4[%arrayidx394] GR32:%vreg242 GR64:%vreg243 GR64_NOSP:%vreg246
12432B		MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %vreg242<kill>; mem:ST4[%c_tPos] GR32:%vreg242
12448B		%vreg237<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR32:%vreg237
12480B		%vreg237<def,tied1> = AND32ri %vreg237<kill,tied0>, 255, %EFLAGS<imp-def,dead>; GR32:%vreg237
12512B		%vreg233<def> = MOVZX32rr8 %vreg237:sub_8bit<kill>; GR32:%vreg233,%vreg237
12528B		MOV32mr <fi#7>, 1, %noreg, 0, %noreg, %vreg233<kill>; mem:ST4[%c_k0] GR32:%vreg233
12544B		%vreg229<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR32:%vreg229
12576B		%vreg229<def,tied1> = SHR32ri %vreg229<kill,tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg229
12592B		MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %vreg229<kill>; mem:ST4[%c_tPos] GR32:%vreg229
12608B		%vreg225<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%c_nblock_used] GR32:%vreg225
12640B		%vreg225<def,tied1> = ADD32ri8 %vreg225<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg225
12656B		MOV32mr <fi#6>, 1, %noreg, 0, %noreg, %vreg225<kill>; mem:ST4[%c_nblock_used] GR32:%vreg225
12672B		JMP_1 <BB#48>
	    Successors according to CFG: BB#48
> %EAX<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg, %RAX<imp-def>; mem:LD4[%c_tPos]
> %RCX<def> = MOV64rm <fi#8>, 1, %noreg, 0, %noreg; mem:LD8[%c_tt]
> %EAX<def> = MOV32rm %RCX<kill>, 4, %RAX<kill>, 0, %noreg; mem:LD4[%arrayidx386]
> MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%c_tPos]
> %EAX<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos]
> %EAX<def,tied1> = AND32ri %EAX<kill,tied0>, 255, %EFLAGS<imp-def,dead>
> MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %AL, %EAX<imp-use,kill>; mem:ST1[%k1]
> %EAX<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos]
> %EAX<def,tied1> = SHR32ri %EAX<kill,tied0>, 8, %EFLAGS<imp-def,dead>
> MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%c_tPos]
> %EAX<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%c_nblock_used]
> %EAX<def,tied1> = ADD32ri8 %EAX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV32mr <fi#6>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%c_nblock_used]
> %EAX<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%k1]
> %EAX<def,tied1> = ADD32ri8 %EAX<kill,tied0>, 4, %EFLAGS<imp-def,dead>
> MOV32mr <fi#5>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%c_state_out_len]
> %EAX<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg, %RAX<imp-def>; mem:LD4[%c_tPos]
> %RCX<def> = MOV64rm <fi#8>, 1, %noreg, 0, %noreg; mem:LD8[%c_tt]
> %EAX<def> = MOV32rm %RCX<kill>, 4, %RAX<kill>, 0, %noreg; mem:LD4[%arrayidx394]
> MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%c_tPos]
> %EAX<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos]
> %EAX<def,tied1> = AND32ri %EAX<kill,tied0>, 255, %EFLAGS<imp-def,dead>
> %EAX<def> = MOVZX32rr8 %AL, %EAX<imp-use,kill>
> MOV32mr <fi#7>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%c_k0]
> %EAX<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos]
> %EAX<def,tied1> = SHR32ri %EAX<kill,tied0>, 8, %EFLAGS<imp-def,dead>
> MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%c_tPos]
> %EAX<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%c_nblock_used]
> %EAX<def,tied1> = ADD32ri8 %EAX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV32mr <fi#6>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%c_nblock_used]
> JMP_1 <BB#48>
12688B	BB#76: derived from LLVM BB %return_notr
	    Predecessors according to CFG: BB#62 BB#57 BB#51
12704B		%vreg307<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg307
12720B		%vreg306<def> = MOV64rm %vreg307<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm400] GR64:%vreg306,%vreg307
12736B		%vreg304<def> = MOV32rm %vreg306<kill>, 1, %noreg, 36, %noreg; mem:LD4[%total_out_lo32401] GR32:%vreg304 GR64:%vreg306
12752B		MOV32mr <fi#14>, 1, %noreg, 0, %noreg, %vreg304<kill>; mem:ST4[%total_out_lo32_old] GR32:%vreg304
12768B		%vreg294<def> = MOV32rm <fi#12>, 1, %noreg, 0, %noreg; mem:LD4[%avail_out_INIT] GR32:%vreg294
12800B		%vreg294<def,tied1> = SUB32rm %vreg294<kill,tied0>, <fi#11>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%cs_avail_out] GR32:%vreg294
12816B		%vreg297<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg297
12832B		%vreg296<def> = MOV64rm %vreg297<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm402] GR64:%vreg296,%vreg297
12864B		%vreg294<def,tied1> = ADD32rm %vreg294<kill,tied0>, %vreg296, 1, %noreg, 36, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%total_out_lo32403] GR32:%vreg294 GR64:%vreg296
12880B		MOV32mr %vreg296<kill>, 1, %noreg, 36, %noreg, %vreg294<kill>; mem:ST4[%total_out_lo32403] GR64:%vreg296 GR32:%vreg294
12896B		%vreg289<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg289
12912B		%vreg288<def> = MOV64rm %vreg289<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm405] GR64:%vreg288,%vreg289
12928B		%vreg286<def> = MOV32rm %vreg288<kill>, 1, %noreg, 36, %noreg; mem:LD4[%total_out_lo32406] GR32:%vreg286 GR64:%vreg288
12944B		CMP32rm %vreg286<kill>, <fi#14>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD4[%total_out_lo32_old] GR32:%vreg286
12960B		JAE_1 <BB#78>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#78 BB#77
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm400]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 36, %noreg; mem:LD4[%total_out_lo32401]
> MOV32mr <fi#14>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%total_out_lo32_old]
> %EAX<def> = MOV32rm <fi#12>, 1, %noreg, 0, %noreg; mem:LD4[%avail_out_INIT]
> %EAX<def,tied1> = SUB32rm %EAX<kill,tied0>, <fi#11>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%cs_avail_out]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RCX<def> = MOV64rm %RCX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm402]
> %EAX<def,tied1> = ADD32rm %EAX<kill,tied0>, %RCX, 1, %noreg, 36, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%total_out_lo32403]
> MOV32mr %RCX<kill>, 1, %noreg, 36, %noreg, %EAX<kill>; mem:ST4[%total_out_lo32403]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm405]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 36, %noreg; mem:LD4[%total_out_lo32406]
> CMP32rm %EAX<kill>, <fi#14>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD4[%total_out_lo32_old]
> JAE_1 <BB#78>, %EFLAGS<imp-use,kill>
12976B	BB#77: derived from LLVM BB %if.then.409
	    Predecessors according to CFG: BB#76
12992B		%vreg315<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg315
13008B		%vreg314<def> = MOV64rm %vreg315<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm410] GR64:%vreg314,%vreg315
13024B		%vreg311<def> = MOV32rm %vreg314, 1, %noreg, 40, %noreg; mem:LD4[%total_out_hi32411] GR32:%vreg311 GR64:%vreg314
13056B		%vreg311<def,tied1> = ADD32ri8 %vreg311<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg311
13072B		MOV32mr %vreg314<kill>, 1, %noreg, 40, %noreg, %vreg311<kill>; mem:ST4[%total_out_hi32411] GR64:%vreg314 GR32:%vreg311
	    Successors according to CFG: BB#78
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm410]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 40, %noreg; mem:LD4[%total_out_hi32411]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 40, %noreg, %ECX<kill>; mem:ST4[%total_out_hi32411]
13088B	BB#78: derived from LLVM BB %if.end.413
	    Predecessors according to CFG: BB#76 BB#77
13104B		%vreg355<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%c_calculatedBlockCRC] GR32:%vreg355
13120B		%vreg354<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg354
13136B		MOV32mr %vreg354<kill>, 1, %noreg, 3184, %noreg, %vreg355<kill>; mem:ST4[%calculatedBlockCRC414] GR64:%vreg354 GR32:%vreg355
13152B		%vreg351<def> = MOV8rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD1[%c_state_out_ch] GR8:%vreg351
13168B		%vreg350<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg350
13184B		MOV8mr %vreg350<kill>, 1, %noreg, 12, %noreg, %vreg351<kill>; mem:ST1[%state_out_ch415] GR64:%vreg350 GR8:%vreg351
13200B		%vreg347<def> = MOV32rm <fi#5>, 1, %noreg, 0, %noreg; mem:LD4[%c_state_out_len] GR32:%vreg347
13216B		%vreg346<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg346
13232B		MOV32mr %vreg346<kill>, 1, %noreg, 16, %noreg, %vreg347<kill>; mem:ST4[%state_out_len416] GR64:%vreg346 GR32:%vreg347
13248B		%vreg343<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%c_nblock_used] GR32:%vreg343
13264B		%vreg342<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg342
13280B		MOV32mr %vreg342<kill>, 1, %noreg, 1092, %noreg, %vreg343<kill>; mem:ST4[%nblock_used417] GR64:%vreg342 GR32:%vreg343
13296B		%vreg339<def> = MOV32rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD4[%c_k0] GR32:%vreg339
13312B		%vreg338<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg338
13328B		MOV32mr %vreg338<kill>, 1, %noreg, 64, %noreg, %vreg339<kill>; mem:ST4[%k0418] GR64:%vreg338 GR32:%vreg339
13344B		%vreg335<def> = MOV64rm <fi#8>, 1, %noreg, 0, %noreg; mem:LD8[%c_tt] GR64:%vreg335
13360B		%vreg334<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg334
13376B		MOV64mr %vreg334<kill>, 1, %noreg, 3152, %noreg, %vreg335<kill>; mem:ST8[%tt419] GR64:%vreg334,%vreg335
13392B		%vreg331<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos] GR32:%vreg331
13408B		%vreg330<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg330
13424B		MOV32mr %vreg330<kill>, 1, %noreg, 60, %noreg, %vreg331<kill>; mem:ST4[%tPos420] GR64:%vreg330 GR32:%vreg331
13440B		%vreg327<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%cs_next_out] GR64:%vreg327
13456B		%vreg326<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg326
13472B		%vreg325<def> = MOV64rm %vreg326<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm421] GR64:%vreg325,%vreg326
13488B		MOV64mr %vreg325<kill>, 1, %noreg, 24, %noreg, %vreg327<kill>; mem:ST8[%next_out422] GR64:%vreg325,%vreg327
13504B		%vreg321<def> = MOV32rm <fi#11>, 1, %noreg, 0, %noreg; mem:LD4[%cs_avail_out] GR32:%vreg321
13520B		%vreg320<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg320
13536B		%vreg319<def> = MOV64rm %vreg320<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm423] GR64:%vreg319,%vreg320
13552B		MOV32mr %vreg319<kill>, 1, %noreg, 32, %noreg, %vreg321<kill>; mem:ST4[%avail_out424] GR64:%vreg319 GR32:%vreg321
	    Successors according to CFG: BB#79
> %EAX<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%c_calculatedBlockCRC]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mr %RCX<kill>, 1, %noreg, 3184, %noreg, %EAX<kill>; mem:ST4[%calculatedBlockCRC414]
> %AL<def> = MOV8rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD1[%c_state_out_ch]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV8mr %RCX<kill>, 1, %noreg, 12, %noreg, %AL<kill>; mem:ST1[%state_out_ch415]
> %EAX<def> = MOV32rm <fi#5>, 1, %noreg, 0, %noreg; mem:LD4[%c_state_out_len]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mr %RCX<kill>, 1, %noreg, 16, %noreg, %EAX<kill>; mem:ST4[%state_out_len416]
> %EAX<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%c_nblock_used]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mr %RCX<kill>, 1, %noreg, 1092, %noreg, %EAX<kill>; mem:ST4[%nblock_used417]
> %EAX<def> = MOV32rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD4[%c_k0]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mr %RCX<kill>, 1, %noreg, 64, %noreg, %EAX<kill>; mem:ST4[%k0418]
> %RAX<def> = MOV64rm <fi#8>, 1, %noreg, 0, %noreg; mem:LD8[%c_tt]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV64mr %RCX<kill>, 1, %noreg, 3152, %noreg, %RAX<kill>; mem:ST8[%tt419]
> %EAX<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%c_tPos]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mr %RCX<kill>, 1, %noreg, 60, %noreg, %EAX<kill>; mem:ST4[%tPos420]
> %RAX<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%cs_next_out]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RCX<def> = MOV64rm %RCX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm421]
> MOV64mr %RCX<kill>, 1, %noreg, 24, %noreg, %RAX<kill>; mem:ST8[%next_out422]
> %EAX<def> = MOV32rm <fi#11>, 1, %noreg, 0, %noreg; mem:LD4[%cs_avail_out]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RCX<def> = MOV64rm %RCX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm423]
> MOV32mr %RCX<kill>, 1, %noreg, 32, %noreg, %EAX<kill>; mem:ST4[%avail_out424]
13568B	BB#79: derived from LLVM BB %if.end.425
	    Predecessors according to CFG: BB#78
13584B		MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST1[%retval]
	    Successors according to CFG: BB#80
> MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST1[%retval]
13600B	BB#80: derived from LLVM BB %return
	    Predecessors according to CFG: BB#60 BB#79 BB#13 BB#11 BB#4
13616B		%vreg938<def> = MOV64ri <ga:@unRLE_obuf_to_output_FAST>; GR64:%vreg938
13648B		%vreg939<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg939
13664B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
13680B		%RDI<def> = COPY %vreg938<kill>; GR64:%vreg938
13696B		%RSI<def> = COPY %vreg939<kill>; GR64:%vreg939
13712B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
13728B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
13744B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
13760B		STACKMAP 1, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=1)
13776B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
13792B		%vreg936<def> = MOV8rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD1[%retval] GR8:%vreg936
13808B		%AL<def> = COPY %vreg936<kill>; GR8:%vreg936
13824B		RETQ %AL<imp-use>
> %RDI<def> = MOV64ri <ga:@unRLE_obuf_to_output_FAST>
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 1, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=1)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %AL<def> = MOV8rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD1[%retval]
> %AL<def> = COPY %AL<kill>
Deleting identity copy.
> RETQ %AL<imp-use>
Computing live-in reg-units in ABI blocks.
0B	BB#0 DIL#0
Created 1 new intervals.
********** INTERVALS **********
DIL [0B,16r:0)[112r,144r:6)[816r,848r:5)[1136r,1168r:4)[1440r,1472r:3)[1680r,1712r:2)[1920r,1952r:1)  0@0B-phi 1@1920r 2@1680r 3@1440r 4@1136r 5@816r 6@112r
%vreg0 [16r,32r:0)  0@16r
%vreg1 [32r,224r:0)  0@32r
%vreg3 [48r,64r:0)  0@48r
%vreg4 [64r,112r:0)  0@64r
%vreg5 [80r,128r:0)  0@80r
%vreg9 [368r,384r:0)  0@368r
%vreg11 [352r,368r:0)  0@352r
%vreg12 [336r,352r:0)  0@336r
%vreg16 [512r,528r:0)  0@512r
%vreg17 [496r,512r:0)  0@496r
%vreg20 [624r,640r:0)  0@624r
%vreg25 [784r,832r:0)  0@784r
%vreg27 [768r,784r:0)  0@768r
%vreg28 [752r,768r:0)  0@752r
%vreg30 [736r,816r:0)  0@736r
%vreg31 [720r,736r:0)  0@720r
%vreg33 [704r,848r:0)  0@704r
%vreg34 [688r,704r:0)  0@688r
%vreg37 [944r,960r:0)  0@944r
%vreg42 [1104r,1152r:0)  0@1104r
%vreg44 [1088r,1104r:0)  0@1088r
%vreg45 [1072r,1088r:0)  0@1072r
%vreg47 [1056r,1136r:0)  0@1056r
%vreg48 [1040r,1056r:0)  0@1040r
%vreg50 [1024r,1168r:0)  0@1024r
%vreg51 [1008r,1024r:0)  0@1008r
%vreg54 [1264r,1280r:0)  0@1264r
%vreg59 [1408r,1456r:0)  0@1408r
%vreg60 [1392r,1408r:0)  0@1392r
%vreg62 [1376r,1440r:0)  0@1376r
%vreg63 [1360r,1376r:0)  0@1360r
%vreg65 [1344r,1472r:0)  0@1344r
%vreg66 [1328r,1344r:0)  0@1328r
%vreg68 [1792r,1808r:0)  0@1792r
%vreg73 [1648r,1696r:0)  0@1648r
%vreg74 [1632r,1648r:0)  0@1632r
%vreg76 [1616r,1680r:0)  0@1616r
%vreg77 [1600r,1616r:0)  0@1600r
%vreg79 [1584r,1712r:0)  0@1584r
%vreg80 [1568r,1584r:0)  0@1568r
%vreg82 [2032r,2048r:0)  0@2032r
%vreg83 [1856r,1872r:0)  0@1856r
%vreg84 [1872r,1920r:0)  0@1872r
%vreg85 [1888r,1936r:0)  0@1888r
RegMasks: 144r 848r 1168r 1472r 1712r 1952r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzDecompressEnd: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=4, align=4, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=8, align=8, at location [SP+8]
Function Live Ins: %RDI in %vreg0

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI
16B		%vreg0<def> = COPY %RDI; GR64:%vreg0
32B		%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
48B		%vreg3<def> = MOV64ri <ga:@BZ2_bzDecompressEnd>; GR64:%vreg3
64B		%vreg4<def> = COPY %vreg3; GR64:%vreg4,%vreg3
80B		%vreg5<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg5
96B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
112B		%RDI<def> = COPY %vreg4; GR64:%vreg4
128B		%RSI<def> = COPY %vreg5; GR64:%vreg5
144B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
160B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
192B		STACKMAP 0, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, %vreg1, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1] GR64:%vreg1
208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%strm.addr] GR64:%vreg1
240B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%strm.addr]
256B		JNE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

272B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
288B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
304B		JMP_1 <BB#13>
	    Successors according to CFG: BB#13

320B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0
336B		%vreg12<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg12
352B		%vreg11<def> = MOV64rm %vreg12, 1, %noreg, 48, %noreg; mem:LD8[%state] GR64:%vreg11,%vreg12
368B		%vreg9<def> = COPY %vreg11; GR64:%vreg9,%vreg11
384B		MOV64mr <fi#2>, 1, %noreg, 0, %noreg, %vreg9; mem:ST8[%s] GR64:%vreg9
400B		CMP64mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%s]
416B		JNE_1 <BB#4>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#4 BB#3

432B	BB#3: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#2
448B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
464B		JMP_1 <BB#13>
	    Successors according to CFG: BB#13

480B	BB#4: derived from LLVM BB %if.end.3
	    Predecessors according to CFG: BB#2
496B		%vreg17<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg17
512B		%vreg16<def> = MOV64rm %vreg17, 1, %noreg, 0, %noreg; mem:LD8[%strm4] GR64:%vreg16,%vreg17
528B		CMP64rm %vreg16, <fi#1>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD8[%strm.addr] GR64:%vreg16
544B		JE_1 <BB#6>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#6 BB#5

560B	BB#5: derived from LLVM BB %if.then.6
	    Predecessors according to CFG: BB#4
576B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
592B		JMP_1 <BB#13>
	    Successors according to CFG: BB#13

608B	BB#6: derived from LLVM BB %if.end.7
	    Predecessors according to CFG: BB#4
624B		%vreg20<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg20
640B		CMP64mi8 %vreg20, 1, %noreg, 3152, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%tt] GR64:%vreg20
656B		JE_1 <BB#8>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#8 BB#7

672B	BB#7: derived from LLVM BB %if.then.9
	    Predecessors according to CFG: BB#6
688B		%vreg34<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg34
704B		%vreg33<def> = MOV64rm %vreg34, 1, %noreg, 64, %noreg; mem:LD8[%bzfree] GR64:%vreg33,%vreg34
720B		%vreg31<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg31
736B		%vreg30<def> = MOV64rm %vreg31, 1, %noreg, 72, %noreg; mem:LD8[%opaque] GR64:%vreg30,%vreg31
752B		%vreg28<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg28
768B		%vreg27<def> = MOV64rm %vreg28, 1, %noreg, 3152, %noreg; mem:LD8[%tt10] GR64:%vreg27,%vreg28
784B		%vreg25<def> = COPY %vreg27; GR64:%vreg25,%vreg27
800B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
816B		%RDI<def> = COPY %vreg30; GR64:%vreg30
832B		%RSI<def> = COPY %vreg25; GR64:%vreg25
848B		CALL64r %vreg33, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>; GR64:%vreg33
864B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
880B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
896B		STACKMAP 1, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1]
912B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#8

928B	BB#8: derived from LLVM BB %if.end.11
	    Predecessors according to CFG: BB#6 BB#7
944B		%vreg37<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg37
960B		CMP64mi8 %vreg37, 1, %noreg, 3160, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%ll16] GR64:%vreg37
976B		JE_1 <BB#10>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#10 BB#9

992B	BB#9: derived from LLVM BB %if.then.13
	    Predecessors according to CFG: BB#8
1008B		%vreg51<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg51
1024B		%vreg50<def> = MOV64rm %vreg51, 1, %noreg, 64, %noreg; mem:LD8[%bzfree14] GR64:%vreg50,%vreg51
1040B		%vreg48<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg48
1056B		%vreg47<def> = MOV64rm %vreg48, 1, %noreg, 72, %noreg; mem:LD8[%opaque15] GR64:%vreg47,%vreg48
1072B		%vreg45<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg45
1088B		%vreg44<def> = MOV64rm %vreg45, 1, %noreg, 3160, %noreg; mem:LD8[%ll1616] GR64:%vreg44,%vreg45
1104B		%vreg42<def> = COPY %vreg44; GR64:%vreg42,%vreg44
1120B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1136B		%RDI<def> = COPY %vreg47; GR64:%vreg47
1152B		%RSI<def> = COPY %vreg42; GR64:%vreg42
1168B		CALL64r %vreg50, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>; GR64:%vreg50
1184B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1200B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1216B		STACKMAP 2, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1]
1232B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#10

1248B	BB#10: derived from LLVM BB %if.end.17
	    Predecessors according to CFG: BB#8 BB#9
1264B		%vreg54<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg54
1280B		CMP64mi8 %vreg54, 1, %noreg, 3168, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%ll4] GR64:%vreg54
1296B		JE_1 <BB#12>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#12 BB#11

1312B	BB#11: derived from LLVM BB %if.then.19
	    Predecessors according to CFG: BB#10
1328B		%vreg66<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg66
1344B		%vreg65<def> = MOV64rm %vreg66, 1, %noreg, 64, %noreg; mem:LD8[%bzfree20] GR64:%vreg65,%vreg66
1360B		%vreg63<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg63
1376B		%vreg62<def> = MOV64rm %vreg63, 1, %noreg, 72, %noreg; mem:LD8[%opaque21] GR64:%vreg62,%vreg63
1392B		%vreg60<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg60
1408B		%vreg59<def> = MOV64rm %vreg60, 1, %noreg, 3168, %noreg; mem:LD8[%ll422] GR64:%vreg59,%vreg60
1424B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1440B		%RDI<def> = COPY %vreg62; GR64:%vreg62
1456B		%RSI<def> = COPY %vreg59; GR64:%vreg59
1472B		CALL64r %vreg65, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>; GR64:%vreg65
1488B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1504B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1520B		STACKMAP 3, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack1]
1536B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#12

1552B	BB#12: derived from LLVM BB %if.end.23
	    Predecessors according to CFG: BB#10 BB#11
1568B		%vreg80<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg80
1584B		%vreg79<def> = MOV64rm %vreg80, 1, %noreg, 64, %noreg; mem:LD8[%bzfree24] GR64:%vreg79,%vreg80
1600B		%vreg77<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg77
1616B		%vreg76<def> = MOV64rm %vreg77, 1, %noreg, 72, %noreg; mem:LD8[%opaque25] GR64:%vreg76,%vreg77
1632B		%vreg74<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg74
1648B		%vreg73<def> = MOV64rm %vreg74, 1, %noreg, 48, %noreg; mem:LD8[%state26] GR64:%vreg73,%vreg74
1664B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1680B		%RDI<def> = COPY %vreg76; GR64:%vreg76
1696B		%RSI<def> = COPY %vreg73; GR64:%vreg73
1712B		CALL64r %vreg79, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>; GR64:%vreg79
1728B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1744B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1760B		STACKMAP 4, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack1]
1776B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1792B		%vreg68<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg68
1808B		MOV64mi32 %vreg68, 1, %noreg, 48, %noreg, 0; mem:ST8[%state27] GR64:%vreg68
1824B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
	    Successors according to CFG: BB#13

1840B	BB#13: derived from LLVM BB %return
	    Predecessors according to CFG: BB#12 BB#5 BB#3 BB#1
1856B		%vreg83<def> = MOV64ri <ga:@BZ2_bzDecompressEnd>; GR64:%vreg83
1872B		%vreg84<def> = COPY %vreg83; GR64:%vreg84,%vreg83
1888B		%vreg85<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg85
1904B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1920B		%RDI<def> = COPY %vreg84; GR64:%vreg84
1936B		%RSI<def> = COPY %vreg85; GR64:%vreg85
1952B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
1968B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1984B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2000B		STACKMAP 5, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
2016B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2032B		%vreg82<def> = MOV32rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD4[%retval] GR32:%vreg82
2048B		%EAX<def> = COPY %vreg82; GR32:%vreg82
2064B		RETQ %EAX<imp-use,kill>

# End machine code for function BZ2_bzDecompressEnd.

********** SIMPLE REGISTER COALESCING **********
********** Function: BZ2_bzDecompressEnd
********** JOINING INTERVALS ***********
if.end.11:
if.end.17:
return:
1920B	%RDI<def> = COPY %vreg84; GR64:%vreg84
	Considering merging %vreg84 with %RDI
	Can only merge into reserved registers.
1936B	%RSI<def> = COPY %vreg85; GR64:%vreg85
	Considering merging %vreg85 with %RSI
	Can only merge into reserved registers.
2048B	%EAX<def> = COPY %vreg82; GR32:%vreg82
	Considering merging %vreg82 with %EAX
	Can only merge into reserved registers.
if.end:
if.end.3:
if.end.7:
if.end.23:
1680B	%RDI<def> = COPY %vreg76; GR64:%vreg76
	Considering merging %vreg76 with %RDI
	Can only merge into reserved registers.
1696B	%RSI<def> = COPY %vreg73; GR64:%vreg73
	Considering merging %vreg73 with %RSI
	Can only merge into reserved registers.
entry:
16B	%vreg0<def> = COPY %RDI; GR64:%vreg0
	Considering merging %vreg0 with %RDI
	Can only merge into reserved registers.
112B	%RDI<def> = COPY %vreg4; GR64:%vreg4
	Considering merging %vreg4 with %RDI
	Can only merge into reserved registers.
128B	%RSI<def> = COPY %vreg5; GR64:%vreg5
	Considering merging %vreg5 with %RSI
	Can only merge into reserved registers.
if.then:
if.then.2:
if.then.6:
if.then.9:
816B	%RDI<def> = COPY %vreg30; GR64:%vreg30
	Considering merging %vreg30 with %RDI
	Can only merge into reserved registers.
832B	%RSI<def> = COPY %vreg25; GR64:%vreg25
	Considering merging %vreg25 with %RSI
	Can only merge into reserved registers.
if.then.13:
1136B	%RDI<def> = COPY %vreg47; GR64:%vreg47
	Considering merging %vreg47 with %RDI
	Can only merge into reserved registers.
1152B	%RSI<def> = COPY %vreg42; GR64:%vreg42
	Considering merging %vreg42 with %RSI
	Can only merge into reserved registers.
if.then.19:
1440B	%RDI<def> = COPY %vreg62; GR64:%vreg62
	Considering merging %vreg62 with %RDI
	Can only merge into reserved registers.
1456B	%RSI<def> = COPY %vreg59; GR64:%vreg59
	Considering merging %vreg59 with %RSI
	Can only merge into reserved registers.
1872B	%vreg84<def> = COPY %vreg83; GR64:%vreg84,%vreg83
	Considering merging to GR64 with %vreg83 in %vreg84
		RHS = %vreg83 [1856r,1872r:0)  0@1856r
		LHS = %vreg84 [1872r,1920r:0)  0@1872r
		merge %vreg84:0@1872r into %vreg83:0@1856r --> @1856r
		erased:	1872r	%vreg84<def> = COPY %vreg83; GR64:%vreg84,%vreg83
		updated: 1856B	%vreg84<def> = MOV64ri <ga:@BZ2_bzDecompressEnd>; GR64:%vreg84
	Success: %vreg83 -> %vreg84
	Result = %vreg84 [1856r,1920r:0)  0@1856r
368B	%vreg9<def> = COPY %vreg11; GR64:%vreg9,%vreg11
	Considering merging to GR64 with %vreg11 in %vreg9
		RHS = %vreg11 [352r,368r:0)  0@352r
		LHS = %vreg9 [368r,384r:0)  0@368r
		merge %vreg9:0@368r into %vreg11:0@352r --> @352r
		erased:	368r	%vreg9<def> = COPY %vreg11; GR64:%vreg9,%vreg11
		updated: 352B	%vreg9<def> = MOV64rm %vreg12, 1, %noreg, 48, %noreg; mem:LD8[%state] GR64:%vreg9,%vreg12
	Success: %vreg11 -> %vreg9
	Result = %vreg9 [352r,384r:0)  0@352r
32B	%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
	Considering merging to GR64 with %vreg0 in %vreg1
		RHS = %vreg0 [16r,32r:0)  0@16r
		LHS = %vreg1 [32r,224r:0)  0@32r
		merge %vreg1:0@32r into %vreg0:0@16r --> @16r
		erased:	32r	%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
		updated: 16B	%vreg1<def> = COPY %RDI; GR64:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [16r,224r:0)  0@16r
64B	%vreg4<def> = COPY %vreg3; GR64:%vreg4,%vreg3
	Considering merging to GR64 with %vreg3 in %vreg4
		RHS = %vreg3 [48r,64r:0)  0@48r
		LHS = %vreg4 [64r,112r:0)  0@64r
		merge %vreg4:0@64r into %vreg3:0@48r --> @48r
		erased:	64r	%vreg4<def> = COPY %vreg3; GR64:%vreg4,%vreg3
		updated: 48B	%vreg4<def> = MOV64ri <ga:@BZ2_bzDecompressEnd>; GR64:%vreg4
	Success: %vreg3 -> %vreg4
	Result = %vreg4 [48r,112r:0)  0@48r
784B	%vreg25<def> = COPY %vreg27; GR64:%vreg25,%vreg27
	Considering merging to GR64 with %vreg27 in %vreg25
		RHS = %vreg27 [768r,784r:0)  0@768r
		LHS = %vreg25 [784r,832r:0)  0@784r
		merge %vreg25:0@784r into %vreg27:0@768r --> @768r
		erased:	784r	%vreg25<def> = COPY %vreg27; GR64:%vreg25,%vreg27
		updated: 768B	%vreg25<def> = MOV64rm %vreg28, 1, %noreg, 3152, %noreg; mem:LD8[%tt10] GR64:%vreg25,%vreg28
	Success: %vreg27 -> %vreg25
	Result = %vreg25 [768r,832r:0)  0@768r
1104B	%vreg42<def> = COPY %vreg44; GR64:%vreg42,%vreg44
	Considering merging to GR64 with %vreg44 in %vreg42
		RHS = %vreg44 [1088r,1104r:0)  0@1088r
		LHS = %vreg42 [1104r,1152r:0)  0@1104r
		merge %vreg42:0@1104r into %vreg44:0@1088r --> @1088r
		erased:	1104r	%vreg42<def> = COPY %vreg44; GR64:%vreg42,%vreg44
		updated: 1088B	%vreg42<def> = MOV64rm %vreg45, 1, %noreg, 3160, %noreg; mem:LD8[%ll1616] GR64:%vreg42,%vreg45
	Success: %vreg44 -> %vreg42
	Result = %vreg42 [1088r,1152r:0)  0@1088r
1920B	%RDI<def> = COPY %vreg84; GR64:%vreg84
	Considering merging %vreg84 with %RDI
	Can only merge into reserved registers.
112B	%RDI<def> = COPY %vreg4; GR64:%vreg4
	Considering merging %vreg4 with %RDI
	Can only merge into reserved registers.
832B	%RSI<def> = COPY %vreg25; GR64:%vreg25
	Considering merging %vreg25 with %RSI
	Can only merge into reserved registers.
1152B	%RSI<def> = COPY %vreg42; GR64:%vreg42
	Considering merging %vreg42 with %RSI
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
DIL [0B,16r:0)[112r,144r:6)[816r,848r:5)[1136r,1168r:4)[1440r,1472r:3)[1680r,1712r:2)[1920r,1952r:1)  0@0B-phi 1@1920r 2@1680r 3@1440r 4@1136r 5@816r 6@112r
%vreg1 [16r,224r:0)  0@16r
%vreg4 [48r,112r:0)  0@48r
%vreg5 [80r,128r:0)  0@80r
%vreg9 [352r,384r:0)  0@352r
%vreg12 [336r,352r:0)  0@336r
%vreg16 [512r,528r:0)  0@512r
%vreg17 [496r,512r:0)  0@496r
%vreg20 [624r,640r:0)  0@624r
%vreg25 [768r,832r:0)  0@768r
%vreg28 [752r,768r:0)  0@752r
%vreg30 [736r,816r:0)  0@736r
%vreg31 [720r,736r:0)  0@720r
%vreg33 [704r,848r:0)  0@704r
%vreg34 [688r,704r:0)  0@688r
%vreg37 [944r,960r:0)  0@944r
%vreg42 [1088r,1152r:0)  0@1088r
%vreg45 [1072r,1088r:0)  0@1072r
%vreg47 [1056r,1136r:0)  0@1056r
%vreg48 [1040r,1056r:0)  0@1040r
%vreg50 [1024r,1168r:0)  0@1024r
%vreg51 [1008r,1024r:0)  0@1008r
%vreg54 [1264r,1280r:0)  0@1264r
%vreg59 [1408r,1456r:0)  0@1408r
%vreg60 [1392r,1408r:0)  0@1392r
%vreg62 [1376r,1440r:0)  0@1376r
%vreg63 [1360r,1376r:0)  0@1360r
%vreg65 [1344r,1472r:0)  0@1344r
%vreg66 [1328r,1344r:0)  0@1328r
%vreg68 [1792r,1808r:0)  0@1792r
%vreg73 [1648r,1696r:0)  0@1648r
%vreg74 [1632r,1648r:0)  0@1632r
%vreg76 [1616r,1680r:0)  0@1616r
%vreg77 [1600r,1616r:0)  0@1600r
%vreg79 [1584r,1712r:0)  0@1584r
%vreg80 [1568r,1584r:0)  0@1568r
%vreg82 [2032r,2048r:0)  0@2032r
%vreg84 [1856r,1920r:0)  0@1856r
%vreg85 [1888r,1936r:0)  0@1888r
RegMasks: 144r 848r 1168r 1472r 1712r 1952r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzDecompressEnd: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=4, align=4, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=8, align=8, at location [SP+8]
Function Live Ins: %RDI in %vreg0

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI
16B		%vreg1<def> = COPY %RDI; GR64:%vreg1
48B		%vreg4<def> = MOV64ri <ga:@BZ2_bzDecompressEnd>; GR64:%vreg4
80B		%vreg5<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg5
96B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
112B		%RDI<def> = COPY %vreg4; GR64:%vreg4
128B		%RSI<def> = COPY %vreg5; GR64:%vreg5
144B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
160B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
192B		STACKMAP 0, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, %vreg1, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1] GR64:%vreg1
208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%strm.addr] GR64:%vreg1
240B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%strm.addr]
256B		JNE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

272B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
288B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
304B		JMP_1 <BB#13>
	    Successors according to CFG: BB#13

320B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0
336B		%vreg12<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg12
352B		%vreg9<def> = MOV64rm %vreg12, 1, %noreg, 48, %noreg; mem:LD8[%state] GR64:%vreg9,%vreg12
384B		MOV64mr <fi#2>, 1, %noreg, 0, %noreg, %vreg9; mem:ST8[%s] GR64:%vreg9
400B		CMP64mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%s]
416B		JNE_1 <BB#4>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#4 BB#3

432B	BB#3: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#2
448B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
464B		JMP_1 <BB#13>
	    Successors according to CFG: BB#13

480B	BB#4: derived from LLVM BB %if.end.3
	    Predecessors according to CFG: BB#2
496B		%vreg17<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg17
512B		%vreg16<def> = MOV64rm %vreg17, 1, %noreg, 0, %noreg; mem:LD8[%strm4] GR64:%vreg16,%vreg17
528B		CMP64rm %vreg16, <fi#1>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD8[%strm.addr] GR64:%vreg16
544B		JE_1 <BB#6>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#6 BB#5

560B	BB#5: derived from LLVM BB %if.then.6
	    Predecessors according to CFG: BB#4
576B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
592B		JMP_1 <BB#13>
	    Successors according to CFG: BB#13

608B	BB#6: derived from LLVM BB %if.end.7
	    Predecessors according to CFG: BB#4
624B		%vreg20<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg20
640B		CMP64mi8 %vreg20, 1, %noreg, 3152, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%tt] GR64:%vreg20
656B		JE_1 <BB#8>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#8 BB#7

672B	BB#7: derived from LLVM BB %if.then.9
	    Predecessors according to CFG: BB#6
688B		%vreg34<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg34
704B		%vreg33<def> = MOV64rm %vreg34, 1, %noreg, 64, %noreg; mem:LD8[%bzfree] GR64:%vreg33,%vreg34
720B		%vreg31<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg31
736B		%vreg30<def> = MOV64rm %vreg31, 1, %noreg, 72, %noreg; mem:LD8[%opaque] GR64:%vreg30,%vreg31
752B		%vreg28<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg28
768B		%vreg25<def> = MOV64rm %vreg28, 1, %noreg, 3152, %noreg; mem:LD8[%tt10] GR64:%vreg25,%vreg28
800B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
816B		%RDI<def> = COPY %vreg30; GR64:%vreg30
832B		%RSI<def> = COPY %vreg25; GR64:%vreg25
848B		CALL64r %vreg33, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>; GR64:%vreg33
864B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
880B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
896B		STACKMAP 1, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1]
912B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#8

928B	BB#8: derived from LLVM BB %if.end.11
	    Predecessors according to CFG: BB#6 BB#7
944B		%vreg37<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg37
960B		CMP64mi8 %vreg37, 1, %noreg, 3160, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%ll16] GR64:%vreg37
976B		JE_1 <BB#10>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#10 BB#9

992B	BB#9: derived from LLVM BB %if.then.13
	    Predecessors according to CFG: BB#8
1008B		%vreg51<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg51
1024B		%vreg50<def> = MOV64rm %vreg51, 1, %noreg, 64, %noreg; mem:LD8[%bzfree14] GR64:%vreg50,%vreg51
1040B		%vreg48<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg48
1056B		%vreg47<def> = MOV64rm %vreg48, 1, %noreg, 72, %noreg; mem:LD8[%opaque15] GR64:%vreg47,%vreg48
1072B		%vreg45<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg45
1088B		%vreg42<def> = MOV64rm %vreg45, 1, %noreg, 3160, %noreg; mem:LD8[%ll1616] GR64:%vreg42,%vreg45
1120B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1136B		%RDI<def> = COPY %vreg47; GR64:%vreg47
1152B		%RSI<def> = COPY %vreg42; GR64:%vreg42
1168B		CALL64r %vreg50, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>; GR64:%vreg50
1184B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1200B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1216B		STACKMAP 2, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1]
1232B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#10

1248B	BB#10: derived from LLVM BB %if.end.17
	    Predecessors according to CFG: BB#8 BB#9
1264B		%vreg54<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg54
1280B		CMP64mi8 %vreg54, 1, %noreg, 3168, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%ll4] GR64:%vreg54
1296B		JE_1 <BB#12>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#12 BB#11

1312B	BB#11: derived from LLVM BB %if.then.19
	    Predecessors according to CFG: BB#10
1328B		%vreg66<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg66
1344B		%vreg65<def> = MOV64rm %vreg66, 1, %noreg, 64, %noreg; mem:LD8[%bzfree20] GR64:%vreg65,%vreg66
1360B		%vreg63<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg63
1376B		%vreg62<def> = MOV64rm %vreg63, 1, %noreg, 72, %noreg; mem:LD8[%opaque21] GR64:%vreg62,%vreg63
1392B		%vreg60<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg60
1408B		%vreg59<def> = MOV64rm %vreg60, 1, %noreg, 3168, %noreg; mem:LD8[%ll422] GR64:%vreg59,%vreg60
1424B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1440B		%RDI<def> = COPY %vreg62; GR64:%vreg62
1456B		%RSI<def> = COPY %vreg59; GR64:%vreg59
1472B		CALL64r %vreg65, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>; GR64:%vreg65
1488B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1504B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1520B		STACKMAP 3, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack1]
1536B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#12

1552B	BB#12: derived from LLVM BB %if.end.23
	    Predecessors according to CFG: BB#10 BB#11
1568B		%vreg80<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg80
1584B		%vreg79<def> = MOV64rm %vreg80, 1, %noreg, 64, %noreg; mem:LD8[%bzfree24] GR64:%vreg79,%vreg80
1600B		%vreg77<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg77
1616B		%vreg76<def> = MOV64rm %vreg77, 1, %noreg, 72, %noreg; mem:LD8[%opaque25] GR64:%vreg76,%vreg77
1632B		%vreg74<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg74
1648B		%vreg73<def> = MOV64rm %vreg74, 1, %noreg, 48, %noreg; mem:LD8[%state26] GR64:%vreg73,%vreg74
1664B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1680B		%RDI<def> = COPY %vreg76; GR64:%vreg76
1696B		%RSI<def> = COPY %vreg73; GR64:%vreg73
1712B		CALL64r %vreg79, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>; GR64:%vreg79
1728B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1744B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1760B		STACKMAP 4, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack1]
1776B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1792B		%vreg68<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg68
1808B		MOV64mi32 %vreg68, 1, %noreg, 48, %noreg, 0; mem:ST8[%state27] GR64:%vreg68
1824B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
	    Successors according to CFG: BB#13

1840B	BB#13: derived from LLVM BB %return
	    Predecessors according to CFG: BB#12 BB#5 BB#3 BB#1
1856B		%vreg84<def> = MOV64ri <ga:@BZ2_bzDecompressEnd>; GR64:%vreg84
1888B		%vreg85<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg85
1904B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1920B		%RDI<def> = COPY %vreg84; GR64:%vreg84
1936B		%RSI<def> = COPY %vreg85; GR64:%vreg85
1952B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
1968B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1984B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2000B		STACKMAP 5, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
2016B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2032B		%vreg82<def> = MOV32rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD4[%retval] GR32:%vreg82
2048B		%EAX<def> = COPY %vreg82; GR32:%vreg82
2064B		RETQ %EAX<imp-use,kill>

# End machine code for function BZ2_bzDecompressEnd.

********** GREEDY REGISTER ALLOCATION **********
********** Function: BZ2_bzDecompressEnd
********** INTERVALS **********
DIL [0B,16r:0)[112r,144r:6)[816r,848r:5)[1136r,1168r:4)[1440r,1472r:3)[1680r,1712r:2)[1920r,1952r:1)  0@0B-phi 1@1920r 2@1680r 3@1440r 4@1136r 5@816r 6@112r
%vreg1 [16r,224r:0)  0@16r
%vreg4 [48r,112r:0)  0@48r
%vreg5 [80r,128r:0)  0@80r
%vreg9 [352r,384r:0)  0@352r
%vreg12 [336r,352r:0)  0@336r
%vreg16 [512r,528r:0)  0@512r
%vreg17 [496r,512r:0)  0@496r
%vreg20 [624r,640r:0)  0@624r
%vreg25 [768r,832r:0)  0@768r
%vreg28 [752r,768r:0)  0@752r
%vreg30 [736r,816r:0)  0@736r
%vreg31 [720r,736r:0)  0@720r
%vreg33 [704r,848r:0)  0@704r
%vreg34 [688r,704r:0)  0@688r
%vreg37 [944r,960r:0)  0@944r
%vreg42 [1088r,1152r:0)  0@1088r
%vreg45 [1072r,1088r:0)  0@1072r
%vreg47 [1056r,1136r:0)  0@1056r
%vreg48 [1040r,1056r:0)  0@1040r
%vreg50 [1024r,1168r:0)  0@1024r
%vreg51 [1008r,1024r:0)  0@1008r
%vreg54 [1264r,1280r:0)  0@1264r
%vreg59 [1408r,1456r:0)  0@1408r
%vreg60 [1392r,1408r:0)  0@1392r
%vreg62 [1376r,1440r:0)  0@1376r
%vreg63 [1360r,1376r:0)  0@1360r
%vreg65 [1344r,1472r:0)  0@1344r
%vreg66 [1328r,1344r:0)  0@1328r
%vreg68 [1792r,1808r:0)  0@1792r
%vreg73 [1648r,1696r:0)  0@1648r
%vreg74 [1632r,1648r:0)  0@1632r
%vreg76 [1616r,1680r:0)  0@1616r
%vreg77 [1600r,1616r:0)  0@1600r
%vreg79 [1584r,1712r:0)  0@1584r
%vreg80 [1568r,1584r:0)  0@1568r
%vreg82 [2032r,2048r:0)  0@2032r
%vreg84 [1856r,1920r:0)  0@1856r
%vreg85 [1888r,1936r:0)  0@1888r
RegMasks: 144r 848r 1168r 1472r 1712r 1952r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzDecompressEnd: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=4, align=4, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=8, align=8, at location [SP+8]
Function Live Ins: %RDI in %vreg0

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI
16B		%vreg1<def> = COPY %RDI; GR64:%vreg1
48B		%vreg4<def> = MOV64ri <ga:@BZ2_bzDecompressEnd>; GR64:%vreg4
80B		%vreg5<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg5
96B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
112B		%RDI<def> = COPY %vreg4; GR64:%vreg4
128B		%RSI<def> = COPY %vreg5; GR64:%vreg5
144B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
160B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
192B		STACKMAP 0, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, %vreg1, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1] GR64:%vreg1
208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%strm.addr] GR64:%vreg1
240B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%strm.addr]
256B		JNE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

272B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
288B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
304B		JMP_1 <BB#13>
	    Successors according to CFG: BB#13

320B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0
336B		%vreg12<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg12
352B		%vreg9<def> = MOV64rm %vreg12, 1, %noreg, 48, %noreg; mem:LD8[%state] GR64:%vreg9,%vreg12
384B		MOV64mr <fi#2>, 1, %noreg, 0, %noreg, %vreg9; mem:ST8[%s] GR64:%vreg9
400B		CMP64mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%s]
416B		JNE_1 <BB#4>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#4 BB#3

432B	BB#3: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#2
448B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
464B		JMP_1 <BB#13>
	    Successors according to CFG: BB#13

480B	BB#4: derived from LLVM BB %if.end.3
	    Predecessors according to CFG: BB#2
496B		%vreg17<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg17
512B		%vreg16<def> = MOV64rm %vreg17, 1, %noreg, 0, %noreg; mem:LD8[%strm4] GR64:%vreg16,%vreg17
528B		CMP64rm %vreg16, <fi#1>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD8[%strm.addr] GR64:%vreg16
544B		JE_1 <BB#6>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#6 BB#5

560B	BB#5: derived from LLVM BB %if.then.6
	    Predecessors according to CFG: BB#4
576B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
592B		JMP_1 <BB#13>
	    Successors according to CFG: BB#13

608B	BB#6: derived from LLVM BB %if.end.7
	    Predecessors according to CFG: BB#4
624B		%vreg20<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg20
640B		CMP64mi8 %vreg20, 1, %noreg, 3152, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%tt] GR64:%vreg20
656B		JE_1 <BB#8>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#8 BB#7

672B	BB#7: derived from LLVM BB %if.then.9
	    Predecessors according to CFG: BB#6
688B		%vreg34<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg34
704B		%vreg33<def> = MOV64rm %vreg34, 1, %noreg, 64, %noreg; mem:LD8[%bzfree] GR64:%vreg33,%vreg34
720B		%vreg31<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg31
736B		%vreg30<def> = MOV64rm %vreg31, 1, %noreg, 72, %noreg; mem:LD8[%opaque] GR64:%vreg30,%vreg31
752B		%vreg28<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg28
768B		%vreg25<def> = MOV64rm %vreg28, 1, %noreg, 3152, %noreg; mem:LD8[%tt10] GR64:%vreg25,%vreg28
800B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
816B		%RDI<def> = COPY %vreg30; GR64:%vreg30
832B		%RSI<def> = COPY %vreg25; GR64:%vreg25
848B		CALL64r %vreg33, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>; GR64:%vreg33
864B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
880B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
896B		STACKMAP 1, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1]
912B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#8

928B	BB#8: derived from LLVM BB %if.end.11
	    Predecessors according to CFG: BB#6 BB#7
944B		%vreg37<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg37
960B		CMP64mi8 %vreg37, 1, %noreg, 3160, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%ll16] GR64:%vreg37
976B		JE_1 <BB#10>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#10 BB#9

992B	BB#9: derived from LLVM BB %if.then.13
	    Predecessors according to CFG: BB#8
1008B		%vreg51<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg51
1024B		%vreg50<def> = MOV64rm %vreg51, 1, %noreg, 64, %noreg; mem:LD8[%bzfree14] GR64:%vreg50,%vreg51
1040B		%vreg48<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg48
1056B		%vreg47<def> = MOV64rm %vreg48, 1, %noreg, 72, %noreg; mem:LD8[%opaque15] GR64:%vreg47,%vreg48
1072B		%vreg45<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg45
1088B		%vreg42<def> = MOV64rm %vreg45, 1, %noreg, 3160, %noreg; mem:LD8[%ll1616] GR64:%vreg42,%vreg45
1120B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1136B		%RDI<def> = COPY %vreg47; GR64:%vreg47
1152B		%RSI<def> = COPY %vreg42; GR64:%vreg42
1168B		CALL64r %vreg50, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>; GR64:%vreg50
1184B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1200B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1216B		STACKMAP 2, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1]
1232B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#10

1248B	BB#10: derived from LLVM BB %if.end.17
	    Predecessors according to CFG: BB#8 BB#9
1264B		%vreg54<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg54
1280B		CMP64mi8 %vreg54, 1, %noreg, 3168, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%ll4] GR64:%vreg54
1296B		JE_1 <BB#12>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#12 BB#11

1312B	BB#11: derived from LLVM BB %if.then.19
	    Predecessors according to CFG: BB#10
1328B		%vreg66<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg66
1344B		%vreg65<def> = MOV64rm %vreg66, 1, %noreg, 64, %noreg; mem:LD8[%bzfree20] GR64:%vreg65,%vreg66
1360B		%vreg63<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg63
1376B		%vreg62<def> = MOV64rm %vreg63, 1, %noreg, 72, %noreg; mem:LD8[%opaque21] GR64:%vreg62,%vreg63
1392B		%vreg60<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg60
1408B		%vreg59<def> = MOV64rm %vreg60, 1, %noreg, 3168, %noreg; mem:LD8[%ll422] GR64:%vreg59,%vreg60
1424B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1440B		%RDI<def> = COPY %vreg62; GR64:%vreg62
1456B		%RSI<def> = COPY %vreg59; GR64:%vreg59
1472B		CALL64r %vreg65, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>; GR64:%vreg65
1488B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1504B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1520B		STACKMAP 3, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack1]
1536B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#12

1552B	BB#12: derived from LLVM BB %if.end.23
	    Predecessors according to CFG: BB#10 BB#11
1568B		%vreg80<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg80
1584B		%vreg79<def> = MOV64rm %vreg80, 1, %noreg, 64, %noreg; mem:LD8[%bzfree24] GR64:%vreg79,%vreg80
1600B		%vreg77<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg77
1616B		%vreg76<def> = MOV64rm %vreg77, 1, %noreg, 72, %noreg; mem:LD8[%opaque25] GR64:%vreg76,%vreg77
1632B		%vreg74<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg74
1648B		%vreg73<def> = MOV64rm %vreg74, 1, %noreg, 48, %noreg; mem:LD8[%state26] GR64:%vreg73,%vreg74
1664B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1680B		%RDI<def> = COPY %vreg76; GR64:%vreg76
1696B		%RSI<def> = COPY %vreg73; GR64:%vreg73
1712B		CALL64r %vreg79, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>; GR64:%vreg79
1728B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1744B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1760B		STACKMAP 4, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack1]
1776B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1792B		%vreg68<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg68
1808B		MOV64mi32 %vreg68, 1, %noreg, 48, %noreg, 0; mem:ST8[%state27] GR64:%vreg68
1824B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
	    Successors according to CFG: BB#13

1840B	BB#13: derived from LLVM BB %return
	    Predecessors according to CFG: BB#12 BB#5 BB#3 BB#1
1856B		%vreg84<def> = MOV64ri <ga:@BZ2_bzDecompressEnd>; GR64:%vreg84
1888B		%vreg85<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg85
1904B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1920B		%RDI<def> = COPY %vreg84; GR64:%vreg84
1936B		%RSI<def> = COPY %vreg85; GR64:%vreg85
1952B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
1968B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1984B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2000B		STACKMAP 5, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
2016B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2032B		%vreg82<def> = MOV32rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD4[%retval] GR32:%vreg82
2048B		%EAX<def> = COPY %vreg82; GR32:%vreg82
2064B		RETQ %EAX<imp-use,kill>

# End machine code for function BZ2_bzDecompressEnd.


selectOrSplit GR64:%vreg1 [16r,224r:0)  0@16r w=4.983553e-03
hints: %RDI
missed hint %RDI
assigning %vreg1 to %RBX: BH [16r,224r:0)  0@16r BL [16r,224r:0)  0@16r

selectOrSplit GR64:%vreg4 [48r,112r:0)  0@48r w=2.176724e-03
hints: %RDI
assigning %vreg4 to %RDI: DIL [48r,112r:0)  0@48r

selectOrSplit GR64:%vreg5 [80r,128r:0)  0@80r w=4.508928e-03
hints: %RSI
assigning %vreg5 to %RSI: SIL [80r,128r:0)  0@80r

selectOrSplit GR64:%vreg30 [736r,816r:0)  0@736r w=2.650919e-04
hints: %RDI
assigning %vreg30 to %RDI: DIL [736r,816r:0)  0@736r

selectOrSplit GR64:%vreg25 [768r,832r:0)  0@768r w=2.742330e-04
hints: %RSI
assigning %vreg25 to %RSI: SIL [768r,832r:0)  0@768r

selectOrSplit GR64:%vreg47 [1056r,1136r:0)  0@1056r w=2.650919e-04
hints: %RDI
assigning %vreg47 to %RDI: DIL [1056r,1136r:0)  0@1056r

selectOrSplit GR64:%vreg42 [1088r,1152r:0)  0@1088r w=2.742330e-04
hints: %RSI
assigning %vreg42 to %RSI: SIL [1088r,1152r:0)  0@1088r

selectOrSplit GR64:%vreg62 [1376r,1440r:0)  0@1376r w=2.742330e-04
hints: %RDI
assigning %vreg62 to %RDI: DIL [1376r,1440r:0)  0@1376r

selectOrSplit GR64:%vreg59 [1408r,1456r:0)  0@1408r w=2.840270e-04
hints: %RSI
assigning %vreg59 to %RSI: SIL [1408r,1456r:0)  0@1408r

selectOrSplit GR64:%vreg76 [1616r,1680r:0)  0@1616r w=5.141868e-04
hints: %RDI
assigning %vreg76 to %RDI: DIL [1616r,1680r:0)  0@1616r

selectOrSplit GR64:%vreg73 [1648r,1696r:0)  0@1648r w=5.325506e-04
hints: %RSI
assigning %vreg73 to %RSI: SIL [1648r,1696r:0)  0@1648r

selectOrSplit GR64:%vreg84 [1856r,1920r:0)  0@1856r w=2.176724e-03
hints: %RDI
assigning %vreg84 to %RDI: DIL [1856r,1920r:0)  0@1856r

selectOrSplit GR64:%vreg85 [1888r,1936r:0)  0@1888r w=4.508928e-03
hints: %RSI
assigning %vreg85 to %RSI: SIL [1888r,1936r:0)  0@1888r

selectOrSplit GR32:%vreg82 [2032r,2048r:0)  0@2032r w=inf
hints: %EAX
assigning %vreg82 to %EAX: AH [2032r,2048r:0)  0@2032r AL [2032r,2048r:0)  0@2032r

selectOrSplit GR64:%vreg12 [336r,352r:0)  0@336r w=inf
assigning %vreg12 to %RAX: AH [336r,352r:0)  0@336r AL [336r,352r:0)  0@336r

selectOrSplit GR64:%vreg9 [352r,384r:0)  0@352r w=inf
assigning %vreg9 to %RAX: AH [352r,384r:0)  0@352r AL [352r,384r:0)  0@352r

selectOrSplit GR64:%vreg17 [496r,512r:0)  0@496r w=inf
assigning %vreg17 to %RAX: AH [496r,512r:0)  0@496r AL [496r,512r:0)  0@496r

selectOrSplit GR64:%vreg16 [512r,528r:0)  0@512r w=inf
assigning %vreg16 to %RAX: AH [512r,528r:0)  0@512r AL [512r,528r:0)  0@512r

selectOrSplit GR64:%vreg20 [624r,640r:0)  0@624r w=inf
assigning %vreg20 to %RAX: AH [624r,640r:0)  0@624r AL [624r,640r:0)  0@624r

selectOrSplit GR64:%vreg34 [688r,704r:0)  0@688r w=inf
assigning %vreg34 to %RAX: AH [688r,704r:0)  0@688r AL [688r,704r:0)  0@688r

selectOrSplit GR64:%vreg33 [704r,848r:0)  0@704r w=2.315887e-04
assigning %vreg33 to %RAX: AH [704r,848r:0)  0@704r AL [704r,848r:0)  0@704r

selectOrSplit GR64:%vreg31 [720r,736r:0)  0@720r w=inf
assigning %vreg31 to %RCX: CH [720r,736r:0)  0@720r CL [720r,736r:0)  0@720r

selectOrSplit GR64:%vreg28 [752r,768r:0)  0@752r w=inf
assigning %vreg28 to %RCX: CH [752r,768r:0)  0@752r CL [752r,768r:0)  0@752r

selectOrSplit GR64:%vreg37 [944r,960r:0)  0@944r w=inf
assigning %vreg37 to %RAX: AH [944r,960r:0)  0@944r AL [944r,960r:0)  0@944r

selectOrSplit GR64:%vreg51 [1008r,1024r:0)  0@1008r w=inf
assigning %vreg51 to %RAX: AH [1008r,1024r:0)  0@1008r AL [1008r,1024r:0)  0@1008r

selectOrSplit GR64:%vreg50 [1024r,1168r:0)  0@1024r w=2.315887e-04
assigning %vreg50 to %RAX: AH [1024r,1168r:0)  0@1024r AL [1024r,1168r:0)  0@1024r

selectOrSplit GR64:%vreg48 [1040r,1056r:0)  0@1040r w=inf
assigning %vreg48 to %RCX: CH [1040r,1056r:0)  0@1040r CL [1040r,1056r:0)  0@1040r

selectOrSplit GR64:%vreg45 [1072r,1088r:0)  0@1072r w=inf
assigning %vreg45 to %RCX: CH [1072r,1088r:0)  0@1072r CL [1072r,1088r:0)  0@1072r

selectOrSplit GR64:%vreg54 [1264r,1280r:0)  0@1264r w=inf
assigning %vreg54 to %RAX: AH [1264r,1280r:0)  0@1264r AL [1264r,1280r:0)  0@1264r

selectOrSplit GR64:%vreg66 [1328r,1344r:0)  0@1328r w=inf
assigning %vreg66 to %RAX: AH [1328r,1344r:0)  0@1328r AL [1328r,1344r:0)  0@1328r

selectOrSplit GR64:%vreg65 [1344r,1472r:0)  0@1344r w=2.386065e-04
assigning %vreg65 to %RAX: AH [1344r,1472r:0)  0@1344r AL [1344r,1472r:0)  0@1344r

selectOrSplit GR64:%vreg63 [1360r,1376r:0)  0@1360r w=inf
assigning %vreg63 to %RCX: CH [1360r,1376r:0)  0@1360r CL [1360r,1376r:0)  0@1360r

selectOrSplit GR64:%vreg60 [1392r,1408r:0)  0@1392r w=inf
assigning %vreg60 to %RCX: CH [1392r,1408r:0)  0@1392r CL [1392r,1408r:0)  0@1392r

selectOrSplit GR64:%vreg80 [1568r,1584r:0)  0@1568r w=inf
assigning %vreg80 to %RAX: AH [1568r,1584r:0)  0@1568r AL [1568r,1584r:0)  0@1568r

selectOrSplit GR64:%vreg79 [1584r,1712r:0)  0@1584r w=4.473873e-04
assigning %vreg79 to %RAX: AH [1584r,1712r:0)  0@1584r AL [1584r,1712r:0)  0@1584r

selectOrSplit GR64:%vreg77 [1600r,1616r:0)  0@1600r w=inf
assigning %vreg77 to %RCX: CH [1600r,1616r:0)  0@1600r CL [1600r,1616r:0)  0@1600r

selectOrSplit GR64:%vreg74 [1632r,1648r:0)  0@1632r w=inf
assigning %vreg74 to %RCX: CH [1632r,1648r:0)  0@1632r CL [1632r,1648r:0)  0@1632r

selectOrSplit GR64:%vreg68 [1792r,1808r:0)  0@1792r w=inf
assigning %vreg68 to %RAX: AH [1792r,1808r:0)  0@1792r AL [1792r,1808r:0)  0@1792r

********** STACK TRANSFORMATION METADATA **********
********** Function: BZ2_bzDecompressEnd
********** REGISTER MAP **********
[%vreg1 -> %RBX] GR64
[%vreg4 -> %RDI] GR64
[%vreg5 -> %RSI] GR64
[%vreg9 -> %RAX] GR64
[%vreg12 -> %RAX] GR64
[%vreg16 -> %RAX] GR64
[%vreg17 -> %RAX] GR64
[%vreg20 -> %RAX] GR64
[%vreg25 -> %RSI] GR64
[%vreg28 -> %RCX] GR64
[%vreg30 -> %RDI] GR64
[%vreg31 -> %RCX] GR64
[%vreg33 -> %RAX] GR64
[%vreg34 -> %RAX] GR64
[%vreg37 -> %RAX] GR64
[%vreg42 -> %RSI] GR64
[%vreg45 -> %RCX] GR64
[%vreg47 -> %RDI] GR64
[%vreg48 -> %RCX] GR64
[%vreg50 -> %RAX] GR64
[%vreg51 -> %RAX] GR64
[%vreg54 -> %RAX] GR64
[%vreg59 -> %RSI] GR64
[%vreg60 -> %RCX] GR64
[%vreg62 -> %RDI] GR64
[%vreg63 -> %RCX] GR64
[%vreg65 -> %RAX] GR64
[%vreg66 -> %RAX] GR64
[%vreg68 -> %RAX] GR64
[%vreg73 -> %RSI] GR64
[%vreg74 -> %RCX] GR64
[%vreg76 -> %RDI] GR64
[%vreg77 -> %RCX] GR64
[%vreg79 -> %RAX] GR64
[%vreg80 -> %RAX] GR64
[%vreg82 -> %EAX] GR32
[%vreg84 -> %RDI] GR64
[%vreg85 -> %RSI] GR64


Stackmap 0:
  STACKMAP 0, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, %vreg1, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1] GR64:%vreg1

i32* %retval: in stack slot 0 (size: 4)
%struct.DState** %s: in stack slot 2 (size: 8)
%struct.bz_stream* %strm: in register %RBX (vreg 1)
%struct.bz_stream** %strm.addr: in stack slot 1 (size: 8)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1]

i32* %retval: in stack slot 0 (size: 4)
%struct.DState** %s: in stack slot 2 (size: 8)
%struct.bz_stream** %strm.addr: in stack slot 1 (size: 8)

Duplicate operand locations:


Stackmap 2:
  STACKMAP 2, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1]

i32* %retval: in stack slot 0 (size: 4)
%struct.DState** %s: in stack slot 2 (size: 8)
%struct.bz_stream** %strm.addr: in stack slot 1 (size: 8)

Duplicate operand locations:


Stackmap 3:
  STACKMAP 3, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack1]

i32* %retval: in stack slot 0 (size: 4)
%struct.bz_stream** %strm.addr: in stack slot 1 (size: 8)

Duplicate operand locations:


Stackmap 4:
  STACKMAP 4, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack1]

i32* %retval: in stack slot 0 (size: 4)
%struct.bz_stream** %strm.addr: in stack slot 1 (size: 8)

Duplicate operand locations:


Stackmap 5:
  STACKMAP 5, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)

i32* %retval: in stack slot 0 (size: 4)

Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, %vreg1, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1] GR64:%vreg1
  -> Call instruction SlotIndex 144B, searching vregs 0 -> 86 and stack slots -1 -> 3

  STACKMAP 1, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1]
  -> Call instruction SlotIndex 848B, searching vregs 0 -> 86 and stack slots -1 -> 3

  STACKMAP 2, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1]
  -> Call instruction SlotIndex 1168B, searching vregs 0 -> 86 and stack slots -1 -> 3

  STACKMAP 3, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack1]
  -> Call instruction SlotIndex 1472B, searching vregs 0 -> 86 and stack slots -1 -> 3

  STACKMAP 4, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack1]
  -> Call instruction SlotIndex 1712B, searching vregs 0 -> 86 and stack slots -1 -> 3

  STACKMAP 5, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
  -> Call instruction SlotIndex 1952B, searching vregs 0 -> 86 and stack slots -1 -> 3

********** REWRITE VIRTUAL REGISTERS **********
********** Function: BZ2_bzDecompressEnd
********** REGISTER MAP **********
[%vreg1 -> %RBX] GR64
[%vreg4 -> %RDI] GR64
[%vreg5 -> %RSI] GR64
[%vreg9 -> %RAX] GR64
[%vreg12 -> %RAX] GR64
[%vreg16 -> %RAX] GR64
[%vreg17 -> %RAX] GR64
[%vreg20 -> %RAX] GR64
[%vreg25 -> %RSI] GR64
[%vreg28 -> %RCX] GR64
[%vreg30 -> %RDI] GR64
[%vreg31 -> %RCX] GR64
[%vreg33 -> %RAX] GR64
[%vreg34 -> %RAX] GR64
[%vreg37 -> %RAX] GR64
[%vreg42 -> %RSI] GR64
[%vreg45 -> %RCX] GR64
[%vreg47 -> %RDI] GR64
[%vreg48 -> %RCX] GR64
[%vreg50 -> %RAX] GR64
[%vreg51 -> %RAX] GR64
[%vreg54 -> %RAX] GR64
[%vreg59 -> %RSI] GR64
[%vreg60 -> %RCX] GR64
[%vreg62 -> %RDI] GR64
[%vreg63 -> %RCX] GR64
[%vreg65 -> %RAX] GR64
[%vreg66 -> %RAX] GR64
[%vreg68 -> %RAX] GR64
[%vreg73 -> %RSI] GR64
[%vreg74 -> %RCX] GR64
[%vreg76 -> %RDI] GR64
[%vreg77 -> %RCX] GR64
[%vreg79 -> %RAX] GR64
[%vreg80 -> %RAX] GR64
[%vreg82 -> %EAX] GR32
[%vreg84 -> %RDI] GR64
[%vreg85 -> %RSI] GR64

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI
16B		%vreg1<def> = COPY %RDI; GR64:%vreg1
48B		%vreg4<def> = MOV64ri <ga:@BZ2_bzDecompressEnd>; GR64:%vreg4
80B		%vreg5<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg5
96B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
112B		%RDI<def> = COPY %vreg4<kill>; GR64:%vreg4
128B		%RSI<def> = COPY %vreg5<kill>; GR64:%vreg5
144B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
160B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
192B		STACKMAP 0, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, %vreg1, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1] GR64:%vreg1
208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg1<kill>; mem:ST8[%strm.addr] GR64:%vreg1
240B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%strm.addr]
256B		JNE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1
> %RBX<def> = COPY %RDI
> %RDI<def> = MOV64ri <ga:@BZ2_bzDecompressEnd>
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 0, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, %RBX, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %RBX<kill>; mem:ST8[%strm.addr]
> CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%strm.addr]
> JNE_1 <BB#2>, %EFLAGS<imp-use,kill>
272B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
288B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
304B		JMP_1 <BB#13>
	    Successors according to CFG: BB#13
> MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
> JMP_1 <BB#13>
320B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0
336B		%vreg12<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg12
352B		%vreg9<def> = MOV64rm %vreg12<kill>, 1, %noreg, 48, %noreg; mem:LD8[%state] GR64:%vreg9,%vreg12
384B		MOV64mr <fi#2>, 1, %noreg, 0, %noreg, %vreg9<kill>; mem:ST8[%s] GR64:%vreg9
400B		CMP64mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%s]
416B		JNE_1 <BB#4>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#4 BB#3
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 48, %noreg; mem:LD8[%state]
> MOV64mr <fi#2>, 1, %noreg, 0, %noreg, %RAX<kill>; mem:ST8[%s]
> CMP64mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%s]
> JNE_1 <BB#4>, %EFLAGS<imp-use,kill>
432B	BB#3: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#2
448B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
464B		JMP_1 <BB#13>
	    Successors according to CFG: BB#13
> MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
> JMP_1 <BB#13>
480B	BB#4: derived from LLVM BB %if.end.3
	    Predecessors according to CFG: BB#2
496B		%vreg17<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg17
512B		%vreg16<def> = MOV64rm %vreg17<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm4] GR64:%vreg16,%vreg17
528B		CMP64rm %vreg16<kill>, <fi#1>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD8[%strm.addr] GR64:%vreg16
544B		JE_1 <BB#6>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#6 BB#5
> %RAX<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm4]
> CMP64rm %RAX<kill>, <fi#1>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD8[%strm.addr]
> JE_1 <BB#6>, %EFLAGS<imp-use,kill>
560B	BB#5: derived from LLVM BB %if.then.6
	    Predecessors according to CFG: BB#4
576B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
592B		JMP_1 <BB#13>
	    Successors according to CFG: BB#13
> MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
> JMP_1 <BB#13>
608B	BB#6: derived from LLVM BB %if.end.7
	    Predecessors according to CFG: BB#4
624B		%vreg20<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg20
640B		CMP64mi8 %vreg20<kill>, 1, %noreg, 3152, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%tt] GR64:%vreg20
656B		JE_1 <BB#8>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#8 BB#7
> %RAX<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> CMP64mi8 %RAX<kill>, 1, %noreg, 3152, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%tt]
> JE_1 <BB#8>, %EFLAGS<imp-use,kill>
672B	BB#7: derived from LLVM BB %if.then.9
	    Predecessors according to CFG: BB#6
688B		%vreg34<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg34
704B		%vreg33<def> = MOV64rm %vreg34<kill>, 1, %noreg, 64, %noreg; mem:LD8[%bzfree] GR64:%vreg33,%vreg34
720B		%vreg31<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg31
736B		%vreg30<def> = MOV64rm %vreg31<kill>, 1, %noreg, 72, %noreg; mem:LD8[%opaque] GR64:%vreg30,%vreg31
752B		%vreg28<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg28
768B		%vreg25<def> = MOV64rm %vreg28<kill>, 1, %noreg, 3152, %noreg; mem:LD8[%tt10] GR64:%vreg25,%vreg28
800B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
816B		%RDI<def> = COPY %vreg30<kill>; GR64:%vreg30
832B		%RSI<def> = COPY %vreg25<kill>; GR64:%vreg25
848B		CALL64r %vreg33<kill>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>; GR64:%vreg33
864B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
880B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
896B		STACKMAP 1, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1]
912B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#8
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 64, %noreg; mem:LD8[%bzfree]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr]
> %RDI<def> = MOV64rm %RCX<kill>, 1, %noreg, 72, %noreg; mem:LD8[%opaque]
> %RCX<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> %RSI<def> = MOV64rm %RCX<kill>, 1, %noreg, 3152, %noreg; mem:LD8[%tt10]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64r %RAX<kill>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 1, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
928B	BB#8: derived from LLVM BB %if.end.11
	    Predecessors according to CFG: BB#6 BB#7
944B		%vreg37<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg37
960B		CMP64mi8 %vreg37<kill>, 1, %noreg, 3160, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%ll16] GR64:%vreg37
976B		JE_1 <BB#10>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#10 BB#9
> %RAX<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> CMP64mi8 %RAX<kill>, 1, %noreg, 3160, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%ll16]
> JE_1 <BB#10>, %EFLAGS<imp-use,kill>
992B	BB#9: derived from LLVM BB %if.then.13
	    Predecessors according to CFG: BB#8
1008B		%vreg51<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg51
1024B		%vreg50<def> = MOV64rm %vreg51<kill>, 1, %noreg, 64, %noreg; mem:LD8[%bzfree14] GR64:%vreg50,%vreg51
1040B		%vreg48<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg48
1056B		%vreg47<def> = MOV64rm %vreg48<kill>, 1, %noreg, 72, %noreg; mem:LD8[%opaque15] GR64:%vreg47,%vreg48
1072B		%vreg45<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg45
1088B		%vreg42<def> = MOV64rm %vreg45<kill>, 1, %noreg, 3160, %noreg; mem:LD8[%ll1616] GR64:%vreg42,%vreg45
1120B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1136B		%RDI<def> = COPY %vreg47<kill>; GR64:%vreg47
1152B		%RSI<def> = COPY %vreg42<kill>; GR64:%vreg42
1168B		CALL64r %vreg50<kill>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>; GR64:%vreg50
1184B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1200B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1216B		STACKMAP 2, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1]
1232B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#10
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 64, %noreg; mem:LD8[%bzfree14]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr]
> %RDI<def> = MOV64rm %RCX<kill>, 1, %noreg, 72, %noreg; mem:LD8[%opaque15]
> %RCX<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> %RSI<def> = MOV64rm %RCX<kill>, 1, %noreg, 3160, %noreg; mem:LD8[%ll1616]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64r %RAX<kill>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 2, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack2] LD8[FixedStack1]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1248B	BB#10: derived from LLVM BB %if.end.17
	    Predecessors according to CFG: BB#8 BB#9
1264B		%vreg54<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg54
1280B		CMP64mi8 %vreg54<kill>, 1, %noreg, 3168, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%ll4] GR64:%vreg54
1296B		JE_1 <BB#12>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#12 BB#11
> %RAX<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> CMP64mi8 %RAX<kill>, 1, %noreg, 3168, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%ll4]
> JE_1 <BB#12>, %EFLAGS<imp-use,kill>
1312B	BB#11: derived from LLVM BB %if.then.19
	    Predecessors according to CFG: BB#10
1328B		%vreg66<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg66
1344B		%vreg65<def> = MOV64rm %vreg66<kill>, 1, %noreg, 64, %noreg; mem:LD8[%bzfree20] GR64:%vreg65,%vreg66
1360B		%vreg63<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg63
1376B		%vreg62<def> = MOV64rm %vreg63<kill>, 1, %noreg, 72, %noreg; mem:LD8[%opaque21] GR64:%vreg62,%vreg63
1392B		%vreg60<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%s] GR64:%vreg60
1408B		%vreg59<def> = MOV64rm %vreg60<kill>, 1, %noreg, 3168, %noreg; mem:LD8[%ll422] GR64:%vreg59,%vreg60
1424B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1440B		%RDI<def> = COPY %vreg62<kill>; GR64:%vreg62
1456B		%RSI<def> = COPY %vreg59<kill>; GR64:%vreg59
1472B		CALL64r %vreg65<kill>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>; GR64:%vreg65
1488B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1504B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1520B		STACKMAP 3, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack1]
1536B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#12
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 64, %noreg; mem:LD8[%bzfree20]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr]
> %RDI<def> = MOV64rm %RCX<kill>, 1, %noreg, 72, %noreg; mem:LD8[%opaque21]
> %RCX<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%s]
> %RSI<def> = MOV64rm %RCX<kill>, 1, %noreg, 3168, %noreg; mem:LD8[%ll422]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64r %RAX<kill>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 3, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack1]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1552B	BB#12: derived from LLVM BB %if.end.23
	    Predecessors according to CFG: BB#10 BB#11
1568B		%vreg80<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg80
1584B		%vreg79<def> = MOV64rm %vreg80<kill>, 1, %noreg, 64, %noreg; mem:LD8[%bzfree24] GR64:%vreg79,%vreg80
1600B		%vreg77<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg77
1616B		%vreg76<def> = MOV64rm %vreg77<kill>, 1, %noreg, 72, %noreg; mem:LD8[%opaque25] GR64:%vreg76,%vreg77
1632B		%vreg74<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg74
1648B		%vreg73<def> = MOV64rm %vreg74<kill>, 1, %noreg, 48, %noreg; mem:LD8[%state26] GR64:%vreg73,%vreg74
1664B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1680B		%RDI<def> = COPY %vreg76<kill>; GR64:%vreg76
1696B		%RSI<def> = COPY %vreg73<kill>; GR64:%vreg73
1712B		CALL64r %vreg79<kill>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>; GR64:%vreg79
1728B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1744B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1760B		STACKMAP 4, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack1]
1776B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1792B		%vreg68<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr] GR64:%vreg68
1808B		MOV64mi32 %vreg68<kill>, 1, %noreg, 48, %noreg, 0; mem:ST8[%state27] GR64:%vreg68
1824B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
	    Successors according to CFG: BB#13
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 64, %noreg; mem:LD8[%bzfree24]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr]
> %RDI<def> = MOV64rm %RCX<kill>, 1, %noreg, 72, %noreg; mem:LD8[%opaque25]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr]
> %RSI<def> = MOV64rm %RCX<kill>, 1, %noreg, 48, %noreg; mem:LD8[%state26]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64r %RAX<kill>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 4, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack1]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%strm.addr]
> MOV64mi32 %RAX<kill>, 1, %noreg, 48, %noreg, 0; mem:ST8[%state27]
> MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
1840B	BB#13: derived from LLVM BB %return
	    Predecessors according to CFG: BB#12 BB#5 BB#3 BB#1
1856B		%vreg84<def> = MOV64ri <ga:@BZ2_bzDecompressEnd>; GR64:%vreg84
1888B		%vreg85<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg85
1904B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1920B		%RDI<def> = COPY %vreg84<kill>; GR64:%vreg84
1936B		%RSI<def> = COPY %vreg85<kill>; GR64:%vreg85
1952B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
1968B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1984B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2000B		STACKMAP 5, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
2016B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2032B		%vreg82<def> = MOV32rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD4[%retval] GR32:%vreg82
2048B		%EAX<def> = COPY %vreg82<kill>; GR32:%vreg82
2064B		RETQ %EAX<imp-use>
> %RDI<def> = MOV64ri <ga:@BZ2_bzDecompressEnd>
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 5, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def> = MOV32rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD4[%retval]
> %EAX<def> = COPY %EAX<kill>
Deleting identity copy.
> RETQ %EAX<imp-use>
Computing live-in reg-units in ABI blocks.
0B	BB#0 DIL#0 SIL#0 DH#0 DL#0 CH#0 CL#0 R8B#0
Created 7 new intervals.
********** INTERVALS **********
CH [0B,32r:0)[2800r,2816r:1)  0@0B-phi 1@2800r
CL [0B,32r:0)[2800r,2816r:1)  0@0B-phi 1@2800r
DH [0B,48r:0)[2784r,2816r:1)  0@0B-phi 1@2784r
DIL [0B,80r:0)[240r,272r:6)[1248r,1264r:5)[1696r,1712r:4)[2752r,2816r:3)[3248r,3264r:2)[3584r,3616r:1)  0@0B-phi 1@3584r 2@3248r 3@2752r 4@1696r 5@1248r 6@240r
DL [0B,48r:0)[2784r,2816r:1)  0@0B-phi 1@2784r
SIL [0B,64r:0)[256r,272r:3)[2768r,2816r:1)[3600r,3616r:2)  0@0B-phi 1@2768r 2@3600r 3@256r
R8B [0B,16r:0)  0@0B-phi
%vreg0 [80r,96r:0)  0@80r
%vreg1 [96r,352r:0)  0@96r
%vreg2 [64r,112r:0)  0@64r
%vreg3 [112r,368r:0)  0@112r
%vreg4 [48r,128r:0)  0@48r
%vreg5 [128r,384r:0)  0@128r
%vreg6 [32r,144r:0)  0@32r
%vreg7 [144r,400r:0)  0@144r
%vreg8 [16r,160r:0)  0@16r
%vreg9 [160r,416r:0)  0@160r
%vreg11 [176r,192r:0)  0@176r
%vreg12 [192r,240r:0)  0@192r
%vreg13 [208r,256r:0)  0@208r
%vreg15 [496r,512r:0)  0@496r
%vreg18 [592r,608r:0)  0@592r
%vreg28 [1296r,1360r:0)  0@1296r
%vreg29 [1216r,1248r:0)  0@1216r
%vreg33 [1808r,1824r:0)  0@1808r
%vreg34 [1648r,1664r:0)  0@1648r
%vreg35 [1664r,1696r:0)  0@1664r
%vreg36 [1744r,1808r:0)  0@1744r
%vreg39 [2176r,2192r:0)  0@2176r
%vreg42 [2272r,2288r:0)  0@2272r
%vreg45 [2528r,2544r:0)  0@2528r
%vreg47 [2496r,2512r:0)  0@2496r
%vreg49 [2464r,2480r:0)  0@2464r
%vreg51 [2432r,2448r:0)  0@2432r
%vreg54 [2400r,2416r:0)  0@2400r
%vreg55 [2384r,2416r:0)  0@2384r
%vreg57 [2352r,2368r:0)  0@2352r
%vreg59 [2320r,2336r:0)  0@2320r
%vreg66 [2848r,2912r:0)  0@2848r
%vreg67 [2720r,2800r:0)  0@2720r
%vreg68 [2704r,2784r:0)  0@2704r
%vreg69 [2688r,2768r:0)  0@2688r
%vreg71 [2656r,2672r:0)[2672r,2752r:1)  0@2656r 1@2672r
%vreg72 [2640r,2656r:0)  0@2640r
%vreg75 [3472r,3488r:0)  0@3472r
%vreg76 [3456r,3472r:0)  0@3456r
%vreg78 [3424r,3440r:0)  0@3424r
%vreg80 [3392r,3408r:0)  0@3392r
%vreg84 [3040r,3056r:0)  0@3040r
%vreg85 [3024r,3056r:0)  0@3024r
%vreg89 [3152r,3168r:0)  0@3152r
%vreg90 [3136r,3168r:0)  0@3136r
%vreg93 [3216r,3248r:0)  0@3216r
%vreg94 [3200r,3216r:0)  0@3200r
%vreg97 [1936r,1952r:0)  0@1936r
%vreg100 [2032r,2048r:0)  0@2032r
%vreg103 [1456r,1472r:0)  0@1456r
%vreg106 [1552r,1568r:0)  0@1552r
%vreg109 [1024r,1040r:0)  0@1024r
%vreg112 [1120r,1136r:0)  0@1120r
%vreg114 [3696r,3712r:0)  0@3696r
%vreg115 [3520r,3536r:0)  0@3520r
%vreg116 [3536r,3584r:0)  0@3536r
%vreg117 [3552r,3600r:0)  0@3552r
RegMasks: 272r 1264r 1712r 2816r 3264r 3616r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzWriteOpen: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=8, align=8, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=8, align=8, at location [SP+8]
  fi#3: size=4, align=4, at location [SP+8]
  fi#4: size=4, align=4, at location [SP+8]
  fi#5: size=4, align=4, at location [SP+8]
  fi#6: size=4, align=4, at location [SP+8]
  fi#7: size=8, align=8, at location [SP+8]
Function Live Ins: %RDI in %vreg0, %RSI in %vreg2, %EDX in %vreg4, %ECX in %vreg6, %R8D in %vreg8

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI %RSI %EDX %ECX %R8D
16B		%vreg8<def> = COPY %R8D; GR32:%vreg8
32B		%vreg6<def> = COPY %ECX; GR32:%vreg6
48B		%vreg4<def> = COPY %EDX; GR32:%vreg4
64B		%vreg2<def> = COPY %RSI; GR64:%vreg2
80B		%vreg0<def> = COPY %RDI; GR64:%vreg0
96B		%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
112B		%vreg3<def> = COPY %vreg2; GR64:%vreg3,%vreg2
128B		%vreg5<def> = COPY %vreg4; GR32:%vreg5,%vreg4
144B		%vreg7<def> = COPY %vreg6; GR32:%vreg7,%vreg6
160B		%vreg9<def> = COPY %vreg8; GR32:%vreg9,%vreg8
176B		%vreg11<def> = MOV64ri <ga:@BZ2_bzWriteOpen>; GR64:%vreg11
192B		%vreg12<def> = COPY %vreg11; GR64:%vreg12,%vreg11
208B		%vreg13<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg13
224B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
240B		%RDI<def> = COPY %vreg12; GR64:%vreg12
256B		%RSI<def> = COPY %vreg13; GR64:%vreg13
272B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
288B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
304B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
320B		STACKMAP 0, 0, %vreg5, 0, <fi#3>, 0, %vreg1, 0, <fi#1>, 0, 0, <fi#7>, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, %vreg7, 0, <fi#4>, 0, %vreg9, 0, <fi#5>, 0, ...; mem:LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) GR32:%vreg5,%vreg7,%vreg9 GR64:%vreg1,%vreg3
336B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
352B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%bzerror.addr] GR64:%vreg1
368B		MOV64mr <fi#2>, 1, %noreg, 0, %noreg, %vreg3; mem:ST8[%f.addr] GR64:%vreg3
384B		MOV32mr <fi#3>, 1, %noreg, 0, %noreg, %vreg5; mem:ST4[%blockSize100k.addr] GR32:%vreg5
400B		MOV32mr <fi#4>, 1, %noreg, 0, %noreg, %vreg7; mem:ST4[%verbosity.addr] GR32:%vreg7
416B		MOV32mr <fi#5>, 1, %noreg, 0, %noreg, %vreg9; mem:ST4[%workFactor.addr] GR32:%vreg9
432B		MOV64mi32 <fi#7>, 1, %noreg, 0, %noreg, 0; mem:ST8[%bzf]
448B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
464B		JE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

480B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
496B		%vreg15<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg15
512B		MOV32mi %vreg15, 1, %noreg, 0, %noreg, 0; mem:ST4[%1] GR64:%vreg15
	    Successors according to CFG: BB#2

528B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#1
544B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
560B		JE_1 <BB#4>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#4 BB#3

576B	BB#3: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#2
592B		%vreg18<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg18
608B		MOV32mi %vreg18, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr] GR64:%vreg18
	    Successors according to CFG: BB#4

624B	BB#4: derived from LLVM BB %if.end.3
	    Predecessors according to CFG: BB#2 BB#3
640B		CMP64mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%f.addr]
656B		JE_1 <BB#11>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#11 BB#5

672B	BB#5: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#4
688B		CMP32mi8 <fi#3>, 1, %noreg, 0, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%blockSize100k.addr]
704B		JL_1 <BB#11>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#11 BB#6

720B	BB#6: derived from LLVM BB %lor.lhs.false.6
	    Predecessors according to CFG: BB#5
736B		CMP32mi8 <fi#3>, 1, %noreg, 0, %noreg, 9, %EFLAGS<imp-def>; mem:LD4[%blockSize100k.addr]
752B		JG_1 <BB#11>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#11 BB#7

768B	BB#7: derived from LLVM BB %lor.lhs.false.8
	    Predecessors according to CFG: BB#6
784B		CMP32mi8 <fi#5>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%workFactor.addr]
800B		JL_1 <BB#11>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#11 BB#8

816B	BB#8: derived from LLVM BB %lor.lhs.false.10
	    Predecessors according to CFG: BB#7
832B		CMP32mi <fi#5>, 1, %noreg, 0, %noreg, 250, %EFLAGS<imp-def>; mem:LD4[%workFactor.addr]
848B		JG_1 <BB#11>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#11 BB#9

864B	BB#9: derived from LLVM BB %lor.lhs.false.12
	    Predecessors according to CFG: BB#8
880B		CMP32mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%verbosity.addr]
896B		JL_1 <BB#11>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#11 BB#10

912B	BB#10: derived from LLVM BB %lor.lhs.false.14
	    Predecessors according to CFG: BB#9
928B		CMP32mi8 <fi#4>, 1, %noreg, 0, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%verbosity.addr]
944B		JLE_1 <BB#16>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#16 BB#11

960B	BB#11: derived from LLVM BB %if.then.16
	    Predecessors according to CFG: BB#4 BB#5 BB#6 BB#7 BB#8 BB#9 BB#10
976B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
992B		JE_1 <BB#13>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#13 BB#12

1008B	BB#12: derived from LLVM BB %if.then.18
	    Predecessors according to CFG: BB#11
1024B		%vreg109<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg109
1040B		MOV32mi %vreg109, 1, %noreg, 0, %noreg, -2; mem:ST4[%12] GR64:%vreg109
	    Successors according to CFG: BB#13

1056B	BB#13: derived from LLVM BB %if.end.19
	    Predecessors according to CFG: BB#11 BB#12
1072B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
1088B		JE_1 <BB#15>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#15 BB#14

1104B	BB#14: derived from LLVM BB %if.then.21
	    Predecessors according to CFG: BB#13
1120B		%vreg112<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg112
1136B		MOV32mi %vreg112, 1, %noreg, 5096, %noreg, -2; mem:ST4[%lastErr22] GR64:%vreg112
	    Successors according to CFG: BB#15

1152B	BB#15: derived from LLVM BB %if.end.23
	    Predecessors according to CFG: BB#13 BB#14
1168B		MOV64mi32 <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST8[%retval]
1184B		JMP_1 <BB#41>
	    Successors according to CFG: BB#41

1200B	BB#16: derived from LLVM BB %if.end.24
	    Predecessors according to CFG: BB#10
1216B		%vreg29<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%f.addr] GR64:%vreg29
1232B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1248B		%RDI<def> = COPY %vreg29; GR64:%vreg29
1264B		CALL64pcrel32 <ga:@ferror>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
1280B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1296B		%vreg28<def> = COPY %EAX<kill>; GR32:%vreg28
1312B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1328B		STACKMAP 1, 0, 0, <fi#3>, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#2>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, ...; mem:LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4)
1344B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1360B		CMP32ri8 %vreg28, 0, %EFLAGS<imp-def>; GR32:%vreg28
1376B		JE_1 <BB#22>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#22 BB#17

1392B	BB#17: derived from LLVM BB %if.then.25
	    Predecessors according to CFG: BB#16
1408B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
1424B		JE_1 <BB#19>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#19 BB#18

1440B	BB#18: derived from LLVM BB %if.then.27
	    Predecessors according to CFG: BB#17
1456B		%vreg103<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg103
1472B		MOV32mi %vreg103, 1, %noreg, 0, %noreg, -6; mem:ST4[%17] GR64:%vreg103
	    Successors according to CFG: BB#19

1488B	BB#19: derived from LLVM BB %if.end.28
	    Predecessors according to CFG: BB#17 BB#18
1504B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
1520B		JE_1 <BB#21>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#21 BB#20

1536B	BB#20: derived from LLVM BB %if.then.30
	    Predecessors according to CFG: BB#19
1552B		%vreg106<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg106
1568B		MOV32mi %vreg106, 1, %noreg, 5096, %noreg, -6; mem:ST4[%lastErr31] GR64:%vreg106
	    Successors according to CFG: BB#21

1584B	BB#21: derived from LLVM BB %if.end.32
	    Predecessors according to CFG: BB#19 BB#20
1600B		MOV64mi32 <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST8[%retval]
1616B		JMP_1 <BB#41>
	    Successors according to CFG: BB#41

1632B	BB#22: derived from LLVM BB %if.end.33
	    Predecessors according to CFG: BB#16
1648B		%vreg34<def> = MOV32ri 5104; GR32:%vreg34
1664B		%vreg35<def> = SUBREG_TO_REG 0, %vreg34, 4; GR64:%vreg35 GR32:%vreg34
1680B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1696B		%RDI<def> = COPY %vreg35; GR64:%vreg35
1712B		CALL64pcrel32 <ga:@malloc>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RAX<imp-def>
1728B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1744B		%vreg36<def> = COPY %RAX<kill>; GR64:%vreg36
1760B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1776B		STACKMAP 2, 0, 0, <fi#3>, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#2>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, ...; mem:LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4)
1792B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1808B		%vreg33<def> = COPY %vreg36; GR64:%vreg33,%vreg36
1824B		MOV64mr <fi#7>, 1, %noreg, 0, %noreg, %vreg33; mem:ST8[%bzf] GR64:%vreg33
1840B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
1856B		JNE_1 <BB#28>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#28 BB#23

1872B	BB#23: derived from LLVM BB %if.then.36
	    Predecessors according to CFG: BB#22
1888B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
1904B		JE_1 <BB#25>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#25 BB#24

1920B	BB#24: derived from LLVM BB %if.then.38
	    Predecessors according to CFG: BB#23
1936B		%vreg97<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg97
1952B		MOV32mi %vreg97, 1, %noreg, 0, %noreg, -3; mem:ST4[%23] GR64:%vreg97
	    Successors according to CFG: BB#25

1968B	BB#25: derived from LLVM BB %if.end.39
	    Predecessors according to CFG: BB#23 BB#24
1984B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
2000B		JE_1 <BB#27>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#27 BB#26

2016B	BB#26: derived from LLVM BB %if.then.41
	    Predecessors according to CFG: BB#25
2032B		%vreg100<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg100
2048B		MOV32mi %vreg100, 1, %noreg, 5096, %noreg, -3; mem:ST4[%lastErr42] GR64:%vreg100
	    Successors according to CFG: BB#27

2064B	BB#27: derived from LLVM BB %if.end.43
	    Predecessors according to CFG: BB#25 BB#26
2080B		MOV64mi32 <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST8[%retval]
2096B		JMP_1 <BB#41>
	    Successors according to CFG: BB#41

2112B	BB#28: derived from LLVM BB %if.end.44
	    Predecessors according to CFG: BB#22
2128B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
2144B		JE_1 <BB#30>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#30 BB#29

2160B	BB#29: derived from LLVM BB %if.then.46
	    Predecessors according to CFG: BB#28
2176B		%vreg39<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg39
2192B		MOV32mi %vreg39, 1, %noreg, 0, %noreg, 0; mem:ST4[%27] GR64:%vreg39
	    Successors according to CFG: BB#30

2208B	BB#30: derived from LLVM BB %if.end.47
	    Predecessors according to CFG: BB#28 BB#29
2224B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
2240B		JE_1 <BB#32>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#32 BB#31

2256B	BB#31: derived from LLVM BB %if.then.49
	    Predecessors according to CFG: BB#30
2272B		%vreg42<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg42
2288B		MOV32mi %vreg42, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr50] GR64:%vreg42
	    Successors according to CFG: BB#32

2304B	BB#32: derived from LLVM BB %if.end.51
	    Predecessors according to CFG: BB#30 BB#31
2320B		%vreg59<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg59
2336B		MOV8mi %vreg59, 1, %noreg, 5100, %noreg, 0; mem:ST1[%initialisedOk] GR64:%vreg59
2352B		%vreg57<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg57
2368B		MOV32mi %vreg57, 1, %noreg, 5008, %noreg, 0; mem:ST4[%bufN] GR64:%vreg57
2384B		%vreg55<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%f.addr] GR64:%vreg55
2400B		%vreg54<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg54
2416B		MOV64mr %vreg54, 1, %noreg, 0, %noreg, %vreg55; mem:ST8[%handle] GR64:%vreg54,%vreg55
2432B		%vreg51<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg51
2448B		MOV8mi %vreg51, 1, %noreg, 5012, %noreg, 1; mem:ST1[%writing] GR64:%vreg51
2464B		%vreg49<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg49
2480B		MOV64mi32 %vreg49, 1, %noreg, 5072, %noreg, 0; mem:ST8[%bzalloc] GR64:%vreg49
2496B		%vreg47<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg47
2512B		MOV64mi32 %vreg47, 1, %noreg, 5080, %noreg, 0; mem:ST8[%bzfree] GR64:%vreg47
2528B		%vreg45<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg45
2544B		MOV64mi32 %vreg45, 1, %noreg, 5088, %noreg, 0; mem:ST8[%opaque] GR64:%vreg45
2560B		CMP32mi8 <fi#5>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%workFactor.addr]
2576B		JNE_1 <BB#34>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#34 BB#33

2592B	BB#33: derived from LLVM BB %if.then.55
	    Predecessors according to CFG: BB#32
2608B		MOV32mi <fi#5>, 1, %noreg, 0, %noreg, 30; mem:ST4[%workFactor.addr]
	    Successors according to CFG: BB#34

2624B	BB#34: derived from LLVM BB %if.end.56
	    Predecessors according to CFG: BB#32 BB#33
2640B		%vreg72<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg72
2656B		%vreg71<def> = COPY %vreg72; GR64:%vreg71,%vreg72
2672B		%vreg71<def,tied1> = ADD64ri32 %vreg71<tied0>, 5016, %EFLAGS<imp-def,dead>; GR64:%vreg71
2688B		%vreg69<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%blockSize100k.addr] GR32:%vreg69
2704B		%vreg68<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%verbosity.addr] GR32:%vreg68
2720B		%vreg67<def> = MOV32rm <fi#5>, 1, %noreg, 0, %noreg; mem:LD4[%workFactor.addr] GR32:%vreg67
2736B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2752B		%RDI<def> = COPY %vreg71; GR64:%vreg71
2768B		%ESI<def> = COPY %vreg69; GR32:%vreg69
2784B		%EDX<def> = COPY %vreg68; GR32:%vreg68
2800B		%ECX<def> = COPY %vreg67; GR32:%vreg67
2816B		CALL64pcrel32 <ga:@BZ2_bzCompressInit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %EDX<imp-use>, %ECX<imp-use>, %EAX<imp-def>
2832B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2848B		%vreg66<def> = COPY %EAX<kill>; GR32:%vreg66
2864B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2880B		STACKMAP 3, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack6](align=4) LD8[FixedStack0]
2896B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2912B		MOV32mr <fi#6>, 1, %noreg, 0, %noreg, %vreg66; mem:ST4[%ret] GR32:%vreg66
2928B		CMP32mi8 <fi#6>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%ret]
2944B		JE_1 <BB#40>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#40 BB#35

2960B	BB#35: derived from LLVM BB %if.then.60
	    Predecessors according to CFG: BB#34
2976B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
2992B		JE_1 <BB#37>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#37 BB#36

3008B	BB#36: derived from LLVM BB %if.then.62
	    Predecessors according to CFG: BB#35
3024B		%vreg85<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%ret] GR32:%vreg85
3040B		%vreg84<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg84
3056B		MOV32mr %vreg84, 1, %noreg, 0, %noreg, %vreg85; mem:ST4[%46] GR64:%vreg84 GR32:%vreg85
	    Successors according to CFG: BB#37

3072B	BB#37: derived from LLVM BB %if.end.63
	    Predecessors according to CFG: BB#35 BB#36
3088B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
3104B		JE_1 <BB#39>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#39 BB#38

3120B	BB#38: derived from LLVM BB %if.then.65
	    Predecessors according to CFG: BB#37
3136B		%vreg90<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%ret] GR32:%vreg90
3152B		%vreg89<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg89
3168B		MOV32mr %vreg89, 1, %noreg, 5096, %noreg, %vreg90; mem:ST4[%lastErr66] GR64:%vreg89 GR32:%vreg90
	    Successors according to CFG: BB#39

3184B	BB#39: derived from LLVM BB %if.end.67
	    Predecessors according to CFG: BB#37 BB#38
3200B		%vreg94<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg94
3216B		%vreg93<def> = COPY %vreg94; GR64:%vreg93,%vreg94
3232B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3248B		%RDI<def> = COPY %vreg93; GR64:%vreg93
3264B		CALL64pcrel32 <ga:@free>, <regmask>, %RSP<imp-use>, %RDI<imp-use>
3280B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3296B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3312B		STACKMAP 4, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0]
3328B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3344B		MOV64mi32 <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST8[%retval]
3360B		JMP_1 <BB#41>
	    Successors according to CFG: BB#41

3376B	BB#40: derived from LLVM BB %if.end.68
	    Predecessors according to CFG: BB#34
3392B		%vreg80<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg80
3408B		MOV32mi %vreg80, 1, %noreg, 5024, %noreg, 0; mem:ST4[%avail_in] GR64:%vreg80
3424B		%vreg78<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg78
3440B		MOV8mi %vreg78, 1, %noreg, 5100, %noreg, 1; mem:ST1[%initialisedOk70] GR64:%vreg78
3456B		%vreg76<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg76
3472B		%vreg75<def> = COPY %vreg76; GR64:%vreg75,%vreg76
3488B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg75; mem:ST8[%retval] GR64:%vreg75
	    Successors according to CFG: BB#41

3504B	BB#41: derived from LLVM BB %return
	    Predecessors according to CFG: BB#40 BB#39 BB#27 BB#21 BB#15
3520B		%vreg115<def> = MOV64ri <ga:@BZ2_bzWriteOpen>; GR64:%vreg115
3536B		%vreg116<def> = COPY %vreg115; GR64:%vreg116,%vreg115
3552B		%vreg117<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg117
3568B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3584B		%RDI<def> = COPY %vreg116; GR64:%vreg116
3600B		%RSI<def> = COPY %vreg117; GR64:%vreg117
3616B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
3632B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3648B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3664B		STACKMAP 5, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0]
3680B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3696B		%vreg114<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%retval] GR64:%vreg114
3712B		%RAX<def> = COPY %vreg114; GR64:%vreg114
3728B		RETQ %RAX<imp-use,kill>

# End machine code for function BZ2_bzWriteOpen.

********** SIMPLE REGISTER COALESCING **********
********** Function: BZ2_bzWriteOpen
********** JOINING INTERVALS ***********
if.then.16:
return:
3584B	%RDI<def> = COPY %vreg116; GR64:%vreg116
	Considering merging %vreg116 with %RDI
	Can only merge into reserved registers.
3600B	%RSI<def> = COPY %vreg117; GR64:%vreg117
	Considering merging %vreg117 with %RSI
	Can only merge into reserved registers.
3712B	%RAX<def> = COPY %vreg114; GR64:%vreg114
	Considering merging %vreg114 with %RAX
	Can only merge into reserved registers.
if.end:
if.end.3:
if.end.19:
if.end.28:
if.end.39:
if.end.47:
if.end.51:
if.end.56:
2752B	%RDI<def> = COPY %vreg71; GR64:%vreg71
	Considering merging %vreg71 with %RDI
	Can only merge into reserved registers.
2768B	%ESI<def> = COPY %vreg69; GR32:%vreg69
	Considering merging %vreg69 with %ESI
	Can only merge into reserved registers.
2784B	%EDX<def> = COPY %vreg68; GR32:%vreg68
	Considering merging %vreg68 with %EDX
	Can only merge into reserved registers.
2800B	%ECX<def> = COPY %vreg67; GR32:%vreg67
	Considering merging %vreg67 with %ECX
	Can only merge into reserved registers.
2848B	%vreg66<def> = COPY %EAX<kill>; GR32:%vreg66
	Considering merging %vreg66 with %EAX
	Can only merge into reserved registers.
if.end.63:
lor.lhs.false:
lor.lhs.false.6:
lor.lhs.false.8:
lor.lhs.false.10:
lor.lhs.false.12:
lor.lhs.false.14:
if.end.23:
if.end.24:
1248B	%RDI<def> = COPY %vreg29; GR64:%vreg29
	Considering merging %vreg29 with %RDI
	Can only merge into reserved registers.
1296B	%vreg28<def> = COPY %EAX<kill>; GR32:%vreg28
	Considering merging %vreg28 with %EAX
	Can only merge into reserved registers.
if.then.25:
if.end.32:
if.end.33:
1664B	%vreg35<def> = SUBREG_TO_REG 0, %vreg34, 4; GR64:%vreg35 GR32:%vreg34
	Considering merging to GR64_with_sub_8bit with %vreg34 in %vreg35:sub_32bit
		RHS = %vreg34 [1648r,1664r:0)  0@1648r
		LHS = %vreg35 [1664r,1696r:0)  0@1664r
		merge %vreg35:0@1664r into %vreg34:0@1648r --> @1648r
		erased:	1664r	%vreg35<def> = SUBREG_TO_REG 0, %vreg34, 4; GR64:%vreg35 GR32:%vreg34
		updated: 1648B	%vreg35:sub_32bit<def,read-undef> = MOV32ri 5104; GR64_with_sub_8bit:%vreg35
	Success: %vreg34:sub_32bit -> %vreg35
	Result = %vreg35 [1648r,1696r:0)  0@1648r
1696B	%RDI<def> = COPY %vreg35; GR64_with_sub_8bit:%vreg35
	Considering merging %vreg35 with %RDI
	Can only merge into reserved registers.
Remat: %EDI<def,dead> = MOV32ri 5104, %RDI<imp-def>
Shrink: %vreg35 [1648r,1696r:0)  0@1648r
All defs dead: 1648r	%vreg35:sub_32bit<def,read-undef,dead> = MOV32ri 5104; GR64_with_sub_8bit:%vreg35
Shrunk: %vreg35 [1648r,1648d:0)  0@1648r
Deleting dead def 1648r	%vreg35:sub_32bit<def,read-undef,dead> = MOV32ri 5104; GR64_with_sub_8bit:%vreg35
1744B	%vreg36<def> = COPY %RAX<kill>; GR64:%vreg36
	Considering merging %vreg36 with %RAX
	Can only merge into reserved registers.
if.then.36:
if.end.43:
if.end.44:
if.then.60:
if.end.67:
3248B	%RDI<def> = COPY %vreg93; GR64:%vreg93
	Considering merging %vreg93 with %RDI
	Can only merge into reserved registers.
entry:
16B	%vreg8<def> = COPY %R8D; GR32:%vreg8
	Considering merging %vreg8 with %R8D
	Can only merge into reserved registers.
32B	%vreg6<def> = COPY %ECX; GR32:%vreg6
	Considering merging %vreg6 with %ECX
	Can only merge into reserved registers.
48B	%vreg4<def> = COPY %EDX; GR32:%vreg4
	Considering merging %vreg4 with %EDX
	Can only merge into reserved registers.
64B	%vreg2<def> = COPY %RSI; GR64:%vreg2
	Considering merging %vreg2 with %RSI
	Can only merge into reserved registers.
80B	%vreg0<def> = COPY %RDI; GR64:%vreg0
	Considering merging %vreg0 with %RDI
	Can only merge into reserved registers.
240B	%RDI<def> = COPY %vreg12; GR64:%vreg12
	Considering merging %vreg12 with %RDI
	Can only merge into reserved registers.
256B	%RSI<def> = COPY %vreg13; GR64:%vreg13
	Considering merging %vreg13 with %RSI
	Can only merge into reserved registers.
if.then:
if.then.2:
if.then.18:
if.then.21:
if.then.27:
if.then.30:
if.then.38:
if.then.41:
if.then.46:
if.then.49:
if.then.55:
if.then.62:
if.then.65:
if.end.68:
3536B	%vreg116<def> = COPY %vreg115; GR64:%vreg116,%vreg115
	Considering merging to GR64 with %vreg115 in %vreg116
		RHS = %vreg115 [3520r,3536r:0)  0@3520r
		LHS = %vreg116 [3536r,3584r:0)  0@3536r
		merge %vreg116:0@3536r into %vreg115:0@3520r --> @3520r
		erased:	3536r	%vreg116<def> = COPY %vreg115; GR64:%vreg116,%vreg115
		updated: 3520B	%vreg116<def> = MOV64ri <ga:@BZ2_bzWriteOpen>; GR64:%vreg116
	Success: %vreg115 -> %vreg116
	Result = %vreg116 [3520r,3584r:0)  0@3520r
2656B	%vreg71<def> = COPY %vreg72; GR64:%vreg71,%vreg72
	Considering merging to GR64 with %vreg72 in %vreg71
		RHS = %vreg72 [2640r,2656r:0)  0@2640r
		LHS = %vreg71 [2656r,2672r:0)[2672r,2752r:1)  0@2656r 1@2672r
		merge %vreg71:0@2656r into %vreg72:0@2640r --> @2640r
		erased:	2656r	%vreg71<def> = COPY %vreg72; GR64:%vreg71,%vreg72
		updated: 2640B	%vreg71<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg71
	Success: %vreg72 -> %vreg71
	Result = %vreg71 [2640r,2672r:0)[2672r,2752r:1)  0@2640r 1@2672r
1808B	%vreg33<def> = COPY %vreg36; GR64:%vreg33,%vreg36
	Considering merging to GR64 with %vreg36 in %vreg33
		RHS = %vreg36 [1744r,1808r:0)  0@1744r
		LHS = %vreg33 [1808r,1824r:0)  0@1808r
		merge %vreg33:0@1808r into %vreg36:0@1744r --> @1744r
		erased:	1808r	%vreg33<def> = COPY %vreg36; GR64:%vreg33,%vreg36
		updated: 1744B	%vreg33<def> = COPY %RAX<kill>; GR64:%vreg33
	Success: %vreg36 -> %vreg33
	Result = %vreg33 [1744r,1824r:0)  0@1744r
3216B	%vreg93<def> = COPY %vreg94; GR64:%vreg93,%vreg94
	Considering merging to GR64 with %vreg94 in %vreg93
		RHS = %vreg94 [3200r,3216r:0)  0@3200r
		LHS = %vreg93 [3216r,3248r:0)  0@3216r
		merge %vreg93:0@3216r into %vreg94:0@3200r --> @3200r
		erased:	3216r	%vreg93<def> = COPY %vreg94; GR64:%vreg93,%vreg94
		updated: 3200B	%vreg93<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg93
	Success: %vreg94 -> %vreg93
	Result = %vreg93 [3200r,3248r:0)  0@3200r
96B	%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
	Considering merging to GR64 with %vreg0 in %vreg1
		RHS = %vreg0 [80r,96r:0)  0@80r
		LHS = %vreg1 [96r,352r:0)  0@96r
		merge %vreg1:0@96r into %vreg0:0@80r --> @80r
		erased:	96r	%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
		updated: 80B	%vreg1<def> = COPY %RDI; GR64:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [80r,352r:0)  0@80r
112B	%vreg3<def> = COPY %vreg2; GR64:%vreg3,%vreg2
	Considering merging to GR64 with %vreg2 in %vreg3
		RHS = %vreg2 [64r,112r:0)  0@64r
		LHS = %vreg3 [112r,368r:0)  0@112r
		merge %vreg3:0@112r into %vreg2:0@64r --> @64r
		erased:	112r	%vreg3<def> = COPY %vreg2; GR64:%vreg3,%vreg2
		updated: 64B	%vreg3<def> = COPY %RSI; GR64:%vreg3
	Success: %vreg2 -> %vreg3
	Result = %vreg3 [64r,368r:0)  0@64r
128B	%vreg5<def> = COPY %vreg4; GR32:%vreg5,%vreg4
	Considering merging to GR32 with %vreg4 in %vreg5
		RHS = %vreg4 [48r,128r:0)  0@48r
		LHS = %vreg5 [128r,384r:0)  0@128r
		merge %vreg5:0@128r into %vreg4:0@48r --> @48r
		erased:	128r	%vreg5<def> = COPY %vreg4; GR32:%vreg5,%vreg4
		updated: 48B	%vreg5<def> = COPY %EDX; GR32:%vreg5
	Success: %vreg4 -> %vreg5
	Result = %vreg5 [48r,384r:0)  0@48r
144B	%vreg7<def> = COPY %vreg6; GR32:%vreg7,%vreg6
	Considering merging to GR32 with %vreg6 in %vreg7
		RHS = %vreg6 [32r,144r:0)  0@32r
		LHS = %vreg7 [144r,400r:0)  0@144r
		merge %vreg7:0@144r into %vreg6:0@32r --> @32r
		erased:	144r	%vreg7<def> = COPY %vreg6; GR32:%vreg7,%vreg6
		updated: 32B	%vreg7<def> = COPY %ECX; GR32:%vreg7
	Success: %vreg6 -> %vreg7
	Result = %vreg7 [32r,400r:0)  0@32r
160B	%vreg9<def> = COPY %vreg8; GR32:%vreg9,%vreg8
	Considering merging to GR32 with %vreg8 in %vreg9
		RHS = %vreg8 [16r,160r:0)  0@16r
		LHS = %vreg9 [160r,416r:0)  0@160r
		merge %vreg9:0@160r into %vreg8:0@16r --> @16r
		erased:	160r	%vreg9<def> = COPY %vreg8; GR32:%vreg9,%vreg8
		updated: 16B	%vreg9<def> = COPY %R8D; GR32:%vreg9
	Success: %vreg8 -> %vreg9
	Result = %vreg9 [16r,416r:0)  0@16r
192B	%vreg12<def> = COPY %vreg11; GR64:%vreg12,%vreg11
	Considering merging to GR64 with %vreg11 in %vreg12
		RHS = %vreg11 [176r,192r:0)  0@176r
		LHS = %vreg12 [192r,240r:0)  0@192r
		merge %vreg12:0@192r into %vreg11:0@176r --> @176r
		erased:	192r	%vreg12<def> = COPY %vreg11; GR64:%vreg12,%vreg11
		updated: 176B	%vreg12<def> = MOV64ri <ga:@BZ2_bzWriteOpen>; GR64:%vreg12
	Success: %vreg11 -> %vreg12
	Result = %vreg12 [176r,240r:0)  0@176r
3472B	%vreg75<def> = COPY %vreg76; GR64:%vreg75,%vreg76
	Considering merging to GR64 with %vreg76 in %vreg75
		RHS = %vreg76 [3456r,3472r:0)  0@3456r
		LHS = %vreg75 [3472r,3488r:0)  0@3472r
		merge %vreg75:0@3472r into %vreg76:0@3456r --> @3456r
		erased:	3472r	%vreg75<def> = COPY %vreg76; GR64:%vreg75,%vreg76
		updated: 3456B	%vreg75<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg75
	Success: %vreg76 -> %vreg75
	Result = %vreg75 [3456r,3488r:0)  0@3456r
3584B	%RDI<def> = COPY %vreg116; GR64:%vreg116
	Considering merging %vreg116 with %RDI
	Can only merge into reserved registers.
3248B	%RDI<def> = COPY %vreg93; GR64:%vreg93
	Considering merging %vreg93 with %RDI
	Can only merge into reserved registers.
240B	%RDI<def> = COPY %vreg12; GR64:%vreg12
	Considering merging %vreg12 with %RDI
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
CH [0B,32r:0)[2800r,2816r:1)  0@0B-phi 1@2800r
CL [0B,32r:0)[2800r,2816r:1)  0@0B-phi 1@2800r
DH [0B,48r:0)[2784r,2816r:1)  0@0B-phi 1@2784r
DIL [0B,80r:0)[240r,272r:6)[1248r,1264r:5)[1696r,1712r:4)[2752r,2816r:3)[3248r,3264r:2)[3584r,3616r:1)  0@0B-phi 1@3584r 2@3248r 3@2752r 4@1696r 5@1248r 6@240r
DL [0B,48r:0)[2784r,2816r:1)  0@0B-phi 1@2784r
SIL [0B,64r:0)[256r,272r:3)[2768r,2816r:1)[3600r,3616r:2)  0@0B-phi 1@2768r 2@3600r 3@256r
R8B [0B,16r:0)  0@0B-phi
%vreg1 [80r,352r:0)  0@80r
%vreg3 [64r,368r:0)  0@64r
%vreg5 [48r,384r:0)  0@48r
%vreg7 [32r,400r:0)  0@32r
%vreg9 [16r,416r:0)  0@16r
%vreg12 [176r,240r:0)  0@176r
%vreg13 [208r,256r:0)  0@208r
%vreg15 [496r,512r:0)  0@496r
%vreg18 [592r,608r:0)  0@592r
%vreg28 [1296r,1360r:0)  0@1296r
%vreg29 [1216r,1248r:0)  0@1216r
%vreg33 [1744r,1824r:0)  0@1744r
%vreg39 [2176r,2192r:0)  0@2176r
%vreg42 [2272r,2288r:0)  0@2272r
%vreg45 [2528r,2544r:0)  0@2528r
%vreg47 [2496r,2512r:0)  0@2496r
%vreg49 [2464r,2480r:0)  0@2464r
%vreg51 [2432r,2448r:0)  0@2432r
%vreg54 [2400r,2416r:0)  0@2400r
%vreg55 [2384r,2416r:0)  0@2384r
%vreg57 [2352r,2368r:0)  0@2352r
%vreg59 [2320r,2336r:0)  0@2320r
%vreg66 [2848r,2912r:0)  0@2848r
%vreg67 [2720r,2800r:0)  0@2720r
%vreg68 [2704r,2784r:0)  0@2704r
%vreg69 [2688r,2768r:0)  0@2688r
%vreg71 [2640r,2672r:0)[2672r,2752r:1)  0@2640r 1@2672r
%vreg75 [3456r,3488r:0)  0@3456r
%vreg78 [3424r,3440r:0)  0@3424r
%vreg80 [3392r,3408r:0)  0@3392r
%vreg84 [3040r,3056r:0)  0@3040r
%vreg85 [3024r,3056r:0)  0@3024r
%vreg89 [3152r,3168r:0)  0@3152r
%vreg90 [3136r,3168r:0)  0@3136r
%vreg93 [3200r,3248r:0)  0@3200r
%vreg97 [1936r,1952r:0)  0@1936r
%vreg100 [2032r,2048r:0)  0@2032r
%vreg103 [1456r,1472r:0)  0@1456r
%vreg106 [1552r,1568r:0)  0@1552r
%vreg109 [1024r,1040r:0)  0@1024r
%vreg112 [1120r,1136r:0)  0@1120r
%vreg114 [3696r,3712r:0)  0@3696r
%vreg116 [3520r,3584r:0)  0@3520r
%vreg117 [3552r,3600r:0)  0@3552r
RegMasks: 272r 1264r 1712r 2816r 3264r 3616r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzWriteOpen: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=8, align=8, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=8, align=8, at location [SP+8]
  fi#3: size=4, align=4, at location [SP+8]
  fi#4: size=4, align=4, at location [SP+8]
  fi#5: size=4, align=4, at location [SP+8]
  fi#6: size=4, align=4, at location [SP+8]
  fi#7: size=8, align=8, at location [SP+8]
Function Live Ins: %RDI in %vreg0, %RSI in %vreg2, %EDX in %vreg4, %ECX in %vreg6, %R8D in %vreg8

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI %RSI %EDX %ECX %R8D
16B		%vreg9<def> = COPY %R8D; GR32:%vreg9
32B		%vreg7<def> = COPY %ECX; GR32:%vreg7
48B		%vreg5<def> = COPY %EDX; GR32:%vreg5
64B		%vreg3<def> = COPY %RSI; GR64:%vreg3
80B		%vreg1<def> = COPY %RDI; GR64:%vreg1
176B		%vreg12<def> = MOV64ri <ga:@BZ2_bzWriteOpen>; GR64:%vreg12
208B		%vreg13<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg13
224B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
240B		%RDI<def> = COPY %vreg12; GR64:%vreg12
256B		%RSI<def> = COPY %vreg13; GR64:%vreg13
272B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
288B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
304B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
320B		STACKMAP 0, 0, %vreg5, 0, <fi#3>, 0, %vreg1, 0, <fi#1>, 0, 0, <fi#7>, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, %vreg7, 0, <fi#4>, 0, %vreg9, 0, <fi#5>, 0, ...; mem:LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) GR32:%vreg5,%vreg7,%vreg9 GR64:%vreg1,%vreg3
336B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
352B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%bzerror.addr] GR64:%vreg1
368B		MOV64mr <fi#2>, 1, %noreg, 0, %noreg, %vreg3; mem:ST8[%f.addr] GR64:%vreg3
384B		MOV32mr <fi#3>, 1, %noreg, 0, %noreg, %vreg5; mem:ST4[%blockSize100k.addr] GR32:%vreg5
400B		MOV32mr <fi#4>, 1, %noreg, 0, %noreg, %vreg7; mem:ST4[%verbosity.addr] GR32:%vreg7
416B		MOV32mr <fi#5>, 1, %noreg, 0, %noreg, %vreg9; mem:ST4[%workFactor.addr] GR32:%vreg9
432B		MOV64mi32 <fi#7>, 1, %noreg, 0, %noreg, 0; mem:ST8[%bzf]
448B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
464B		JE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

480B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
496B		%vreg15<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg15
512B		MOV32mi %vreg15, 1, %noreg, 0, %noreg, 0; mem:ST4[%1] GR64:%vreg15
	    Successors according to CFG: BB#2

528B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#1
544B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
560B		JE_1 <BB#4>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#4 BB#3

576B	BB#3: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#2
592B		%vreg18<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg18
608B		MOV32mi %vreg18, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr] GR64:%vreg18
	    Successors according to CFG: BB#4

624B	BB#4: derived from LLVM BB %if.end.3
	    Predecessors according to CFG: BB#2 BB#3
640B		CMP64mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%f.addr]
656B		JE_1 <BB#11>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#11 BB#5

672B	BB#5: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#4
688B		CMP32mi8 <fi#3>, 1, %noreg, 0, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%blockSize100k.addr]
704B		JL_1 <BB#11>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#11 BB#6

720B	BB#6: derived from LLVM BB %lor.lhs.false.6
	    Predecessors according to CFG: BB#5
736B		CMP32mi8 <fi#3>, 1, %noreg, 0, %noreg, 9, %EFLAGS<imp-def>; mem:LD4[%blockSize100k.addr]
752B		JG_1 <BB#11>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#11 BB#7

768B	BB#7: derived from LLVM BB %lor.lhs.false.8
	    Predecessors according to CFG: BB#6
784B		CMP32mi8 <fi#5>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%workFactor.addr]
800B		JL_1 <BB#11>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#11 BB#8

816B	BB#8: derived from LLVM BB %lor.lhs.false.10
	    Predecessors according to CFG: BB#7
832B		CMP32mi <fi#5>, 1, %noreg, 0, %noreg, 250, %EFLAGS<imp-def>; mem:LD4[%workFactor.addr]
848B		JG_1 <BB#11>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#11 BB#9

864B	BB#9: derived from LLVM BB %lor.lhs.false.12
	    Predecessors according to CFG: BB#8
880B		CMP32mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%verbosity.addr]
896B		JL_1 <BB#11>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#11 BB#10

912B	BB#10: derived from LLVM BB %lor.lhs.false.14
	    Predecessors according to CFG: BB#9
928B		CMP32mi8 <fi#4>, 1, %noreg, 0, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%verbosity.addr]
944B		JLE_1 <BB#16>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#16 BB#11

960B	BB#11: derived from LLVM BB %if.then.16
	    Predecessors according to CFG: BB#4 BB#5 BB#6 BB#7 BB#8 BB#9 BB#10
976B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
992B		JE_1 <BB#13>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#13 BB#12

1008B	BB#12: derived from LLVM BB %if.then.18
	    Predecessors according to CFG: BB#11
1024B		%vreg109<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg109
1040B		MOV32mi %vreg109, 1, %noreg, 0, %noreg, -2; mem:ST4[%12] GR64:%vreg109
	    Successors according to CFG: BB#13

1056B	BB#13: derived from LLVM BB %if.end.19
	    Predecessors according to CFG: BB#11 BB#12
1072B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
1088B		JE_1 <BB#15>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#15 BB#14

1104B	BB#14: derived from LLVM BB %if.then.21
	    Predecessors according to CFG: BB#13
1120B		%vreg112<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg112
1136B		MOV32mi %vreg112, 1, %noreg, 5096, %noreg, -2; mem:ST4[%lastErr22] GR64:%vreg112
	    Successors according to CFG: BB#15

1152B	BB#15: derived from LLVM BB %if.end.23
	    Predecessors according to CFG: BB#13 BB#14
1168B		MOV64mi32 <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST8[%retval]
1184B		JMP_1 <BB#41>
	    Successors according to CFG: BB#41

1200B	BB#16: derived from LLVM BB %if.end.24
	    Predecessors according to CFG: BB#10
1216B		%vreg29<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%f.addr] GR64:%vreg29
1232B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1248B		%RDI<def> = COPY %vreg29; GR64:%vreg29
1264B		CALL64pcrel32 <ga:@ferror>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
1280B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1296B		%vreg28<def> = COPY %EAX<kill>; GR32:%vreg28
1312B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1328B		STACKMAP 1, 0, 0, <fi#3>, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#2>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, ...; mem:LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4)
1344B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1360B		CMP32ri8 %vreg28, 0, %EFLAGS<imp-def>; GR32:%vreg28
1376B		JE_1 <BB#22>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#22 BB#17

1392B	BB#17: derived from LLVM BB %if.then.25
	    Predecessors according to CFG: BB#16
1408B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
1424B		JE_1 <BB#19>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#19 BB#18

1440B	BB#18: derived from LLVM BB %if.then.27
	    Predecessors according to CFG: BB#17
1456B		%vreg103<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg103
1472B		MOV32mi %vreg103, 1, %noreg, 0, %noreg, -6; mem:ST4[%17] GR64:%vreg103
	    Successors according to CFG: BB#19

1488B	BB#19: derived from LLVM BB %if.end.28
	    Predecessors according to CFG: BB#17 BB#18
1504B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
1520B		JE_1 <BB#21>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#21 BB#20

1536B	BB#20: derived from LLVM BB %if.then.30
	    Predecessors according to CFG: BB#19
1552B		%vreg106<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg106
1568B		MOV32mi %vreg106, 1, %noreg, 5096, %noreg, -6; mem:ST4[%lastErr31] GR64:%vreg106
	    Successors according to CFG: BB#21

1584B	BB#21: derived from LLVM BB %if.end.32
	    Predecessors according to CFG: BB#19 BB#20
1600B		MOV64mi32 <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST8[%retval]
1616B		JMP_1 <BB#41>
	    Successors according to CFG: BB#41

1632B	BB#22: derived from LLVM BB %if.end.33
	    Predecessors according to CFG: BB#16
1680B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1696B		%EDI<def,dead> = MOV32ri 5104, %RDI<imp-def>
1712B		CALL64pcrel32 <ga:@malloc>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RAX<imp-def>
1728B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1744B		%vreg33<def> = COPY %RAX<kill>; GR64:%vreg33
1760B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1776B		STACKMAP 2, 0, 0, <fi#3>, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#2>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, ...; mem:LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4)
1792B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1824B		MOV64mr <fi#7>, 1, %noreg, 0, %noreg, %vreg33; mem:ST8[%bzf] GR64:%vreg33
1840B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
1856B		JNE_1 <BB#28>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#28 BB#23

1872B	BB#23: derived from LLVM BB %if.then.36
	    Predecessors according to CFG: BB#22
1888B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
1904B		JE_1 <BB#25>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#25 BB#24

1920B	BB#24: derived from LLVM BB %if.then.38
	    Predecessors according to CFG: BB#23
1936B		%vreg97<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg97
1952B		MOV32mi %vreg97, 1, %noreg, 0, %noreg, -3; mem:ST4[%23] GR64:%vreg97
	    Successors according to CFG: BB#25

1968B	BB#25: derived from LLVM BB %if.end.39
	    Predecessors according to CFG: BB#23 BB#24
1984B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
2000B		JE_1 <BB#27>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#27 BB#26

2016B	BB#26: derived from LLVM BB %if.then.41
	    Predecessors according to CFG: BB#25
2032B		%vreg100<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg100
2048B		MOV32mi %vreg100, 1, %noreg, 5096, %noreg, -3; mem:ST4[%lastErr42] GR64:%vreg100
	    Successors according to CFG: BB#27

2064B	BB#27: derived from LLVM BB %if.end.43
	    Predecessors according to CFG: BB#25 BB#26
2080B		MOV64mi32 <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST8[%retval]
2096B		JMP_1 <BB#41>
	    Successors according to CFG: BB#41

2112B	BB#28: derived from LLVM BB %if.end.44
	    Predecessors according to CFG: BB#22
2128B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
2144B		JE_1 <BB#30>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#30 BB#29

2160B	BB#29: derived from LLVM BB %if.then.46
	    Predecessors according to CFG: BB#28
2176B		%vreg39<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg39
2192B		MOV32mi %vreg39, 1, %noreg, 0, %noreg, 0; mem:ST4[%27] GR64:%vreg39
	    Successors according to CFG: BB#30

2208B	BB#30: derived from LLVM BB %if.end.47
	    Predecessors according to CFG: BB#28 BB#29
2224B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
2240B		JE_1 <BB#32>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#32 BB#31

2256B	BB#31: derived from LLVM BB %if.then.49
	    Predecessors according to CFG: BB#30
2272B		%vreg42<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg42
2288B		MOV32mi %vreg42, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr50] GR64:%vreg42
	    Successors according to CFG: BB#32

2304B	BB#32: derived from LLVM BB %if.end.51
	    Predecessors according to CFG: BB#30 BB#31
2320B		%vreg59<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg59
2336B		MOV8mi %vreg59, 1, %noreg, 5100, %noreg, 0; mem:ST1[%initialisedOk] GR64:%vreg59
2352B		%vreg57<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg57
2368B		MOV32mi %vreg57, 1, %noreg, 5008, %noreg, 0; mem:ST4[%bufN] GR64:%vreg57
2384B		%vreg55<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%f.addr] GR64:%vreg55
2400B		%vreg54<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg54
2416B		MOV64mr %vreg54, 1, %noreg, 0, %noreg, %vreg55; mem:ST8[%handle] GR64:%vreg54,%vreg55
2432B		%vreg51<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg51
2448B		MOV8mi %vreg51, 1, %noreg, 5012, %noreg, 1; mem:ST1[%writing] GR64:%vreg51
2464B		%vreg49<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg49
2480B		MOV64mi32 %vreg49, 1, %noreg, 5072, %noreg, 0; mem:ST8[%bzalloc] GR64:%vreg49
2496B		%vreg47<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg47
2512B		MOV64mi32 %vreg47, 1, %noreg, 5080, %noreg, 0; mem:ST8[%bzfree] GR64:%vreg47
2528B		%vreg45<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg45
2544B		MOV64mi32 %vreg45, 1, %noreg, 5088, %noreg, 0; mem:ST8[%opaque] GR64:%vreg45
2560B		CMP32mi8 <fi#5>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%workFactor.addr]
2576B		JNE_1 <BB#34>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#34 BB#33

2592B	BB#33: derived from LLVM BB %if.then.55
	    Predecessors according to CFG: BB#32
2608B		MOV32mi <fi#5>, 1, %noreg, 0, %noreg, 30; mem:ST4[%workFactor.addr]
	    Successors according to CFG: BB#34

2624B	BB#34: derived from LLVM BB %if.end.56
	    Predecessors according to CFG: BB#32 BB#33
2640B		%vreg71<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg71
2672B		%vreg71<def,tied1> = ADD64ri32 %vreg71<tied0>, 5016, %EFLAGS<imp-def,dead>; GR64:%vreg71
2688B		%vreg69<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%blockSize100k.addr] GR32:%vreg69
2704B		%vreg68<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%verbosity.addr] GR32:%vreg68
2720B		%vreg67<def> = MOV32rm <fi#5>, 1, %noreg, 0, %noreg; mem:LD4[%workFactor.addr] GR32:%vreg67
2736B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2752B		%RDI<def> = COPY %vreg71; GR64:%vreg71
2768B		%ESI<def> = COPY %vreg69; GR32:%vreg69
2784B		%EDX<def> = COPY %vreg68; GR32:%vreg68
2800B		%ECX<def> = COPY %vreg67; GR32:%vreg67
2816B		CALL64pcrel32 <ga:@BZ2_bzCompressInit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %EDX<imp-use>, %ECX<imp-use>, %EAX<imp-def>
2832B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2848B		%vreg66<def> = COPY %EAX<kill>; GR32:%vreg66
2864B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2880B		STACKMAP 3, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack6](align=4) LD8[FixedStack0]
2896B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2912B		MOV32mr <fi#6>, 1, %noreg, 0, %noreg, %vreg66; mem:ST4[%ret] GR32:%vreg66
2928B		CMP32mi8 <fi#6>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%ret]
2944B		JE_1 <BB#40>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#40 BB#35

2960B	BB#35: derived from LLVM BB %if.then.60
	    Predecessors according to CFG: BB#34
2976B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
2992B		JE_1 <BB#37>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#37 BB#36

3008B	BB#36: derived from LLVM BB %if.then.62
	    Predecessors according to CFG: BB#35
3024B		%vreg85<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%ret] GR32:%vreg85
3040B		%vreg84<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg84
3056B		MOV32mr %vreg84, 1, %noreg, 0, %noreg, %vreg85; mem:ST4[%46] GR64:%vreg84 GR32:%vreg85
	    Successors according to CFG: BB#37

3072B	BB#37: derived from LLVM BB %if.end.63
	    Predecessors according to CFG: BB#35 BB#36
3088B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
3104B		JE_1 <BB#39>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#39 BB#38

3120B	BB#38: derived from LLVM BB %if.then.65
	    Predecessors according to CFG: BB#37
3136B		%vreg90<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%ret] GR32:%vreg90
3152B		%vreg89<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg89
3168B		MOV32mr %vreg89, 1, %noreg, 5096, %noreg, %vreg90; mem:ST4[%lastErr66] GR64:%vreg89 GR32:%vreg90
	    Successors according to CFG: BB#39

3184B	BB#39: derived from LLVM BB %if.end.67
	    Predecessors according to CFG: BB#37 BB#38
3200B		%vreg93<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg93
3232B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3248B		%RDI<def> = COPY %vreg93; GR64:%vreg93
3264B		CALL64pcrel32 <ga:@free>, <regmask>, %RSP<imp-use>, %RDI<imp-use>
3280B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3296B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3312B		STACKMAP 4, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0]
3328B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3344B		MOV64mi32 <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST8[%retval]
3360B		JMP_1 <BB#41>
	    Successors according to CFG: BB#41

3376B	BB#40: derived from LLVM BB %if.end.68
	    Predecessors according to CFG: BB#34
3392B		%vreg80<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg80
3408B		MOV32mi %vreg80, 1, %noreg, 5024, %noreg, 0; mem:ST4[%avail_in] GR64:%vreg80
3424B		%vreg78<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg78
3440B		MOV8mi %vreg78, 1, %noreg, 5100, %noreg, 1; mem:ST1[%initialisedOk70] GR64:%vreg78
3456B		%vreg75<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg75
3488B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg75; mem:ST8[%retval] GR64:%vreg75
	    Successors according to CFG: BB#41

3504B	BB#41: derived from LLVM BB %return
	    Predecessors according to CFG: BB#40 BB#39 BB#27 BB#21 BB#15
3520B		%vreg116<def> = MOV64ri <ga:@BZ2_bzWriteOpen>; GR64:%vreg116
3552B		%vreg117<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg117
3568B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3584B		%RDI<def> = COPY %vreg116; GR64:%vreg116
3600B		%RSI<def> = COPY %vreg117; GR64:%vreg117
3616B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
3632B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3648B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3664B		STACKMAP 5, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0]
3680B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3696B		%vreg114<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%retval] GR64:%vreg114
3712B		%RAX<def> = COPY %vreg114; GR64:%vreg114
3728B		RETQ %RAX<imp-use,kill>

# End machine code for function BZ2_bzWriteOpen.

AllocationOrder(SEGMENT_REG) = [ ]
********** GREEDY REGISTER ALLOCATION **********
********** Function: BZ2_bzWriteOpen
********** INTERVALS **********
CH [0B,32r:0)[2800r,2816r:1)  0@0B-phi 1@2800r
CL [0B,32r:0)[2800r,2816r:1)  0@0B-phi 1@2800r
DH [0B,48r:0)[2784r,2816r:1)  0@0B-phi 1@2784r
DIL [0B,80r:0)[240r,272r:6)[1248r,1264r:5)[1696r,1712r:4)[2752r,2816r:3)[3248r,3264r:2)[3584r,3616r:1)  0@0B-phi 1@3584r 2@3248r 3@2752r 4@1696r 5@1248r 6@240r
DL [0B,48r:0)[2784r,2816r:1)  0@0B-phi 1@2784r
SIL [0B,64r:0)[256r,272r:3)[2768r,2816r:1)[3600r,3616r:2)  0@0B-phi 1@2768r 2@3600r 3@256r
R8B [0B,16r:0)  0@0B-phi
%vreg1 [80r,352r:0)  0@80r
%vreg3 [64r,368r:0)  0@64r
%vreg5 [48r,384r:0)  0@48r
%vreg7 [32r,400r:0)  0@32r
%vreg9 [16r,416r:0)  0@16r
%vreg12 [176r,240r:0)  0@176r
%vreg13 [208r,256r:0)  0@208r
%vreg15 [496r,512r:0)  0@496r
%vreg18 [592r,608r:0)  0@592r
%vreg28 [1296r,1360r:0)  0@1296r
%vreg29 [1216r,1248r:0)  0@1216r
%vreg33 [1744r,1824r:0)  0@1744r
%vreg39 [2176r,2192r:0)  0@2176r
%vreg42 [2272r,2288r:0)  0@2272r
%vreg45 [2528r,2544r:0)  0@2528r
%vreg47 [2496r,2512r:0)  0@2496r
%vreg49 [2464r,2480r:0)  0@2464r
%vreg51 [2432r,2448r:0)  0@2432r
%vreg54 [2400r,2416r:0)  0@2400r
%vreg55 [2384r,2416r:0)  0@2384r
%vreg57 [2352r,2368r:0)  0@2352r
%vreg59 [2320r,2336r:0)  0@2320r
%vreg66 [2848r,2912r:0)  0@2848r
%vreg67 [2720r,2800r:0)  0@2720r
%vreg68 [2704r,2784r:0)  0@2704r
%vreg69 [2688r,2768r:0)  0@2688r
%vreg71 [2640r,2672r:0)[2672r,2752r:1)  0@2640r 1@2672r
%vreg75 [3456r,3488r:0)  0@3456r
%vreg78 [3424r,3440r:0)  0@3424r
%vreg80 [3392r,3408r:0)  0@3392r
%vreg84 [3040r,3056r:0)  0@3040r
%vreg85 [3024r,3056r:0)  0@3024r
%vreg89 [3152r,3168r:0)  0@3152r
%vreg90 [3136r,3168r:0)  0@3136r
%vreg93 [3200r,3248r:0)  0@3200r
%vreg97 [1936r,1952r:0)  0@1936r
%vreg100 [2032r,2048r:0)  0@2032r
%vreg103 [1456r,1472r:0)  0@1456r
%vreg106 [1552r,1568r:0)  0@1552r
%vreg109 [1024r,1040r:0)  0@1024r
%vreg112 [1120r,1136r:0)  0@1120r
%vreg114 [3696r,3712r:0)  0@3696r
%vreg116 [3520r,3584r:0)  0@3520r
%vreg117 [3552r,3600r:0)  0@3552r
RegMasks: 272r 1264r 1712r 2816r 3264r 3616r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzWriteOpen: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=8, align=8, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=8, align=8, at location [SP+8]
  fi#3: size=4, align=4, at location [SP+8]
  fi#4: size=4, align=4, at location [SP+8]
  fi#5: size=4, align=4, at location [SP+8]
  fi#6: size=4, align=4, at location [SP+8]
  fi#7: size=8, align=8, at location [SP+8]
Function Live Ins: %RDI in %vreg0, %RSI in %vreg2, %EDX in %vreg4, %ECX in %vreg6, %R8D in %vreg8

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI %RSI %EDX %ECX %R8D
16B		%vreg9<def> = COPY %R8D; GR32:%vreg9
32B		%vreg7<def> = COPY %ECX; GR32:%vreg7
48B		%vreg5<def> = COPY %EDX; GR32:%vreg5
64B		%vreg3<def> = COPY %RSI; GR64:%vreg3
80B		%vreg1<def> = COPY %RDI; GR64:%vreg1
176B		%vreg12<def> = MOV64ri <ga:@BZ2_bzWriteOpen>; GR64:%vreg12
208B		%vreg13<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg13
224B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
240B		%RDI<def> = COPY %vreg12; GR64:%vreg12
256B		%RSI<def> = COPY %vreg13; GR64:%vreg13
272B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
288B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
304B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
320B		STACKMAP 0, 0, %vreg5, 0, <fi#3>, 0, %vreg1, 0, <fi#1>, 0, 0, <fi#7>, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, %vreg7, 0, <fi#4>, 0, %vreg9, 0, <fi#5>, 0, ...; mem:LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) GR32:%vreg5,%vreg7,%vreg9 GR64:%vreg1,%vreg3
336B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
352B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%bzerror.addr] GR64:%vreg1
368B		MOV64mr <fi#2>, 1, %noreg, 0, %noreg, %vreg3; mem:ST8[%f.addr] GR64:%vreg3
384B		MOV32mr <fi#3>, 1, %noreg, 0, %noreg, %vreg5; mem:ST4[%blockSize100k.addr] GR32:%vreg5
400B		MOV32mr <fi#4>, 1, %noreg, 0, %noreg, %vreg7; mem:ST4[%verbosity.addr] GR32:%vreg7
416B		MOV32mr <fi#5>, 1, %noreg, 0, %noreg, %vreg9; mem:ST4[%workFactor.addr] GR32:%vreg9
432B		MOV64mi32 <fi#7>, 1, %noreg, 0, %noreg, 0; mem:ST8[%bzf]
448B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
464B		JE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

480B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
496B		%vreg15<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg15
512B		MOV32mi %vreg15, 1, %noreg, 0, %noreg, 0; mem:ST4[%1] GR64:%vreg15
	    Successors according to CFG: BB#2

528B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#1
544B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
560B		JE_1 <BB#4>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#4 BB#3

576B	BB#3: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#2
592B		%vreg18<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg18
608B		MOV32mi %vreg18, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr] GR64:%vreg18
	    Successors according to CFG: BB#4

624B	BB#4: derived from LLVM BB %if.end.3
	    Predecessors according to CFG: BB#2 BB#3
640B		CMP64mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%f.addr]
656B		JE_1 <BB#11>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#11 BB#5

672B	BB#5: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#4
688B		CMP32mi8 <fi#3>, 1, %noreg, 0, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%blockSize100k.addr]
704B		JL_1 <BB#11>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#11 BB#6

720B	BB#6: derived from LLVM BB %lor.lhs.false.6
	    Predecessors according to CFG: BB#5
736B		CMP32mi8 <fi#3>, 1, %noreg, 0, %noreg, 9, %EFLAGS<imp-def>; mem:LD4[%blockSize100k.addr]
752B		JG_1 <BB#11>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#11 BB#7

768B	BB#7: derived from LLVM BB %lor.lhs.false.8
	    Predecessors according to CFG: BB#6
784B		CMP32mi8 <fi#5>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%workFactor.addr]
800B		JL_1 <BB#11>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#11 BB#8

816B	BB#8: derived from LLVM BB %lor.lhs.false.10
	    Predecessors according to CFG: BB#7
832B		CMP32mi <fi#5>, 1, %noreg, 0, %noreg, 250, %EFLAGS<imp-def>; mem:LD4[%workFactor.addr]
848B		JG_1 <BB#11>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#11 BB#9

864B	BB#9: derived from LLVM BB %lor.lhs.false.12
	    Predecessors according to CFG: BB#8
880B		CMP32mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%verbosity.addr]
896B		JL_1 <BB#11>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#11 BB#10

912B	BB#10: derived from LLVM BB %lor.lhs.false.14
	    Predecessors according to CFG: BB#9
928B		CMP32mi8 <fi#4>, 1, %noreg, 0, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%verbosity.addr]
944B		JLE_1 <BB#16>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#16 BB#11

960B	BB#11: derived from LLVM BB %if.then.16
	    Predecessors according to CFG: BB#4 BB#5 BB#6 BB#7 BB#8 BB#9 BB#10
976B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
992B		JE_1 <BB#13>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#13 BB#12

1008B	BB#12: derived from LLVM BB %if.then.18
	    Predecessors according to CFG: BB#11
1024B		%vreg109<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg109
1040B		MOV32mi %vreg109, 1, %noreg, 0, %noreg, -2; mem:ST4[%12] GR64:%vreg109
	    Successors according to CFG: BB#13

1056B	BB#13: derived from LLVM BB %if.end.19
	    Predecessors according to CFG: BB#11 BB#12
1072B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
1088B		JE_1 <BB#15>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#15 BB#14

1104B	BB#14: derived from LLVM BB %if.then.21
	    Predecessors according to CFG: BB#13
1120B		%vreg112<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg112
1136B		MOV32mi %vreg112, 1, %noreg, 5096, %noreg, -2; mem:ST4[%lastErr22] GR64:%vreg112
	    Successors according to CFG: BB#15

1152B	BB#15: derived from LLVM BB %if.end.23
	    Predecessors according to CFG: BB#13 BB#14
1168B		MOV64mi32 <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST8[%retval]
1184B		JMP_1 <BB#41>
	    Successors according to CFG: BB#41

1200B	BB#16: derived from LLVM BB %if.end.24
	    Predecessors according to CFG: BB#10
1216B		%vreg29<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%f.addr] GR64:%vreg29
1232B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1248B		%RDI<def> = COPY %vreg29; GR64:%vreg29
1264B		CALL64pcrel32 <ga:@ferror>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
1280B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1296B		%vreg28<def> = COPY %EAX<kill>; GR32:%vreg28
1312B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1328B		STACKMAP 1, 0, 0, <fi#3>, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#2>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, ...; mem:LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4)
1344B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1360B		CMP32ri8 %vreg28, 0, %EFLAGS<imp-def>; GR32:%vreg28
1376B		JE_1 <BB#22>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#22 BB#17

1392B	BB#17: derived from LLVM BB %if.then.25
	    Predecessors according to CFG: BB#16
1408B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
1424B		JE_1 <BB#19>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#19 BB#18

1440B	BB#18: derived from LLVM BB %if.then.27
	    Predecessors according to CFG: BB#17
1456B		%vreg103<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg103
1472B		MOV32mi %vreg103, 1, %noreg, 0, %noreg, -6; mem:ST4[%17] GR64:%vreg103
	    Successors according to CFG: BB#19

1488B	BB#19: derived from LLVM BB %if.end.28
	    Predecessors according to CFG: BB#17 BB#18
1504B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
1520B		JE_1 <BB#21>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#21 BB#20

1536B	BB#20: derived from LLVM BB %if.then.30
	    Predecessors according to CFG: BB#19
1552B		%vreg106<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg106
1568B		MOV32mi %vreg106, 1, %noreg, 5096, %noreg, -6; mem:ST4[%lastErr31] GR64:%vreg106
	    Successors according to CFG: BB#21

1584B	BB#21: derived from LLVM BB %if.end.32
	    Predecessors according to CFG: BB#19 BB#20
1600B		MOV64mi32 <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST8[%retval]
1616B		JMP_1 <BB#41>
	    Successors according to CFG: BB#41

1632B	BB#22: derived from LLVM BB %if.end.33
	    Predecessors according to CFG: BB#16
1680B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1696B		%EDI<def,dead> = MOV32ri 5104, %RDI<imp-def>
1712B		CALL64pcrel32 <ga:@malloc>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RAX<imp-def>
1728B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1744B		%vreg33<def> = COPY %RAX<kill>; GR64:%vreg33
1760B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1776B		STACKMAP 2, 0, 0, <fi#3>, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#2>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, ...; mem:LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4)
1792B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1824B		MOV64mr <fi#7>, 1, %noreg, 0, %noreg, %vreg33; mem:ST8[%bzf] GR64:%vreg33
1840B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
1856B		JNE_1 <BB#28>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#28 BB#23

1872B	BB#23: derived from LLVM BB %if.then.36
	    Predecessors according to CFG: BB#22
1888B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
1904B		JE_1 <BB#25>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#25 BB#24

1920B	BB#24: derived from LLVM BB %if.then.38
	    Predecessors according to CFG: BB#23
1936B		%vreg97<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg97
1952B		MOV32mi %vreg97, 1, %noreg, 0, %noreg, -3; mem:ST4[%23] GR64:%vreg97
	    Successors according to CFG: BB#25

1968B	BB#25: derived from LLVM BB %if.end.39
	    Predecessors according to CFG: BB#23 BB#24
1984B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
2000B		JE_1 <BB#27>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#27 BB#26

2016B	BB#26: derived from LLVM BB %if.then.41
	    Predecessors according to CFG: BB#25
2032B		%vreg100<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg100
2048B		MOV32mi %vreg100, 1, %noreg, 5096, %noreg, -3; mem:ST4[%lastErr42] GR64:%vreg100
	    Successors according to CFG: BB#27

2064B	BB#27: derived from LLVM BB %if.end.43
	    Predecessors according to CFG: BB#25 BB#26
2080B		MOV64mi32 <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST8[%retval]
2096B		JMP_1 <BB#41>
	    Successors according to CFG: BB#41

2112B	BB#28: derived from LLVM BB %if.end.44
	    Predecessors according to CFG: BB#22
2128B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
2144B		JE_1 <BB#30>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#30 BB#29

2160B	BB#29: derived from LLVM BB %if.then.46
	    Predecessors according to CFG: BB#28
2176B		%vreg39<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg39
2192B		MOV32mi %vreg39, 1, %noreg, 0, %noreg, 0; mem:ST4[%27] GR64:%vreg39
	    Successors according to CFG: BB#30

2208B	BB#30: derived from LLVM BB %if.end.47
	    Predecessors according to CFG: BB#28 BB#29
2224B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
2240B		JE_1 <BB#32>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#32 BB#31

2256B	BB#31: derived from LLVM BB %if.then.49
	    Predecessors according to CFG: BB#30
2272B		%vreg42<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg42
2288B		MOV32mi %vreg42, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr50] GR64:%vreg42
	    Successors according to CFG: BB#32

2304B	BB#32: derived from LLVM BB %if.end.51
	    Predecessors according to CFG: BB#30 BB#31
2320B		%vreg59<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg59
2336B		MOV8mi %vreg59, 1, %noreg, 5100, %noreg, 0; mem:ST1[%initialisedOk] GR64:%vreg59
2352B		%vreg57<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg57
2368B		MOV32mi %vreg57, 1, %noreg, 5008, %noreg, 0; mem:ST4[%bufN] GR64:%vreg57
2384B		%vreg55<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%f.addr] GR64:%vreg55
2400B		%vreg54<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg54
2416B		MOV64mr %vreg54, 1, %noreg, 0, %noreg, %vreg55; mem:ST8[%handle] GR64:%vreg54,%vreg55
2432B		%vreg51<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg51
2448B		MOV8mi %vreg51, 1, %noreg, 5012, %noreg, 1; mem:ST1[%writing] GR64:%vreg51
2464B		%vreg49<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg49
2480B		MOV64mi32 %vreg49, 1, %noreg, 5072, %noreg, 0; mem:ST8[%bzalloc] GR64:%vreg49
2496B		%vreg47<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg47
2512B		MOV64mi32 %vreg47, 1, %noreg, 5080, %noreg, 0; mem:ST8[%bzfree] GR64:%vreg47
2528B		%vreg45<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg45
2544B		MOV64mi32 %vreg45, 1, %noreg, 5088, %noreg, 0; mem:ST8[%opaque] GR64:%vreg45
2560B		CMP32mi8 <fi#5>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%workFactor.addr]
2576B		JNE_1 <BB#34>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#34 BB#33

2592B	BB#33: derived from LLVM BB %if.then.55
	    Predecessors according to CFG: BB#32
2608B		MOV32mi <fi#5>, 1, %noreg, 0, %noreg, 30; mem:ST4[%workFactor.addr]
	    Successors according to CFG: BB#34

2624B	BB#34: derived from LLVM BB %if.end.56
	    Predecessors according to CFG: BB#32 BB#33
2640B		%vreg71<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg71
2672B		%vreg71<def,tied1> = ADD64ri32 %vreg71<tied0>, 5016, %EFLAGS<imp-def,dead>; GR64:%vreg71
2688B		%vreg69<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%blockSize100k.addr] GR32:%vreg69
2704B		%vreg68<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%verbosity.addr] GR32:%vreg68
2720B		%vreg67<def> = MOV32rm <fi#5>, 1, %noreg, 0, %noreg; mem:LD4[%workFactor.addr] GR32:%vreg67
2736B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2752B		%RDI<def> = COPY %vreg71; GR64:%vreg71
2768B		%ESI<def> = COPY %vreg69; GR32:%vreg69
2784B		%EDX<def> = COPY %vreg68; GR32:%vreg68
2800B		%ECX<def> = COPY %vreg67; GR32:%vreg67
2816B		CALL64pcrel32 <ga:@BZ2_bzCompressInit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %EDX<imp-use>, %ECX<imp-use>, %EAX<imp-def>
2832B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2848B		%vreg66<def> = COPY %EAX<kill>; GR32:%vreg66
2864B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2880B		STACKMAP 3, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack6](align=4) LD8[FixedStack0]
2896B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2912B		MOV32mr <fi#6>, 1, %noreg, 0, %noreg, %vreg66; mem:ST4[%ret] GR32:%vreg66
2928B		CMP32mi8 <fi#6>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%ret]
2944B		JE_1 <BB#40>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#40 BB#35

2960B	BB#35: derived from LLVM BB %if.then.60
	    Predecessors according to CFG: BB#34
2976B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
2992B		JE_1 <BB#37>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#37 BB#36

3008B	BB#36: derived from LLVM BB %if.then.62
	    Predecessors according to CFG: BB#35
3024B		%vreg85<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%ret] GR32:%vreg85
3040B		%vreg84<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg84
3056B		MOV32mr %vreg84, 1, %noreg, 0, %noreg, %vreg85; mem:ST4[%46] GR64:%vreg84 GR32:%vreg85
	    Successors according to CFG: BB#37

3072B	BB#37: derived from LLVM BB %if.end.63
	    Predecessors according to CFG: BB#35 BB#36
3088B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
3104B		JE_1 <BB#39>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#39 BB#38

3120B	BB#38: derived from LLVM BB %if.then.65
	    Predecessors according to CFG: BB#37
3136B		%vreg90<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%ret] GR32:%vreg90
3152B		%vreg89<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg89
3168B		MOV32mr %vreg89, 1, %noreg, 5096, %noreg, %vreg90; mem:ST4[%lastErr66] GR64:%vreg89 GR32:%vreg90
	    Successors according to CFG: BB#39

3184B	BB#39: derived from LLVM BB %if.end.67
	    Predecessors according to CFG: BB#37 BB#38
3200B		%vreg93<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg93
3232B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3248B		%RDI<def> = COPY %vreg93; GR64:%vreg93
3264B		CALL64pcrel32 <ga:@free>, <regmask>, %RSP<imp-use>, %RDI<imp-use>
3280B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3296B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3312B		STACKMAP 4, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0]
3328B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3344B		MOV64mi32 <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST8[%retval]
3360B		JMP_1 <BB#41>
	    Successors according to CFG: BB#41

3376B	BB#40: derived from LLVM BB %if.end.68
	    Predecessors according to CFG: BB#34
3392B		%vreg80<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg80
3408B		MOV32mi %vreg80, 1, %noreg, 5024, %noreg, 0; mem:ST4[%avail_in] GR64:%vreg80
3424B		%vreg78<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg78
3440B		MOV8mi %vreg78, 1, %noreg, 5100, %noreg, 1; mem:ST1[%initialisedOk70] GR64:%vreg78
3456B		%vreg75<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg75
3488B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg75; mem:ST8[%retval] GR64:%vreg75
	    Successors according to CFG: BB#41

3504B	BB#41: derived from LLVM BB %return
	    Predecessors according to CFG: BB#40 BB#39 BB#27 BB#21 BB#15
3520B		%vreg116<def> = MOV64ri <ga:@BZ2_bzWriteOpen>; GR64:%vreg116
3552B		%vreg117<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg117
3568B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3584B		%RDI<def> = COPY %vreg116; GR64:%vreg116
3600B		%RSI<def> = COPY %vreg117; GR64:%vreg117
3616B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
3632B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3648B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3664B		STACKMAP 5, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0]
3680B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3696B		%vreg114<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%retval] GR64:%vreg114
3712B		%RAX<def> = COPY %vreg114; GR64:%vreg114
3728B		RETQ %RAX<imp-use,kill>

# End machine code for function BZ2_bzWriteOpen.


selectOrSplit GR32:%vreg9 [16r,416r:0)  0@16r w=3.787500e-03
hints: %R8D
missed hint %R8D
assigning %vreg9 to %EBX: BH [16r,416r:0)  0@16r BL [16r,416r:0)  0@16r

selectOrSplit GR32:%vreg7 [32r,400r:0)  0@32r w=3.945312e-03
hints: %ECX
missed hint %ECX
%R14D is available at cost 1
Only trying the first 10 regs.
should evict: %vreg9 [16r,416r:0)  0@16r w= 3.787500e-03
hints: %R8D
can reassign: %vreg9 [16r,416r:0)  0@16r from %EBX to %R8D
should evict: %vreg9 [16r,416r:0)  0@16r w= 3.787500e-03
hints: %R8D
can reassign: %vreg9 [16r,416r:0)  0@16r from %EBX to %R8D
evicting %EBX interference: Cascade 1
unassigning %vreg9 from %EBX: BH BL
assigning %vreg7 to %EBX: BH [32r,400r:0)  0@32r BL [32r,400r:0)  0@32r
queuing new interval: %vreg9 [16r,416r:0)  0@16r

selectOrSplit GR32:%vreg9 [16r,416r:0)  0@16r w=3.787500e-03
hints: %R8D
missed hint %R8D
%R14D is available at cost 1
Only trying the first 10 regs.
assigning %vreg9 to %R14D: R14B [16r,416r:0)  0@16r

selectOrSplit GR32:%vreg5 [48r,384r:0)  0@48r w=4.116848e-03
hints: %EDX
missed hint %EDX
%R15D is available at cost 1
Only trying the first 10 regs.
should evict: %vreg7 [32r,400r:0)  0@32r w= 3.945312e-03
hints: %ECX
can reassign: %vreg7 [32r,400r:0)  0@32r from %EBX to %ECX
should evict: %vreg7 [32r,400r:0)  0@32r w= 3.945312e-03
hints: %ECX
can reassign: %vreg7 [32r,400r:0)  0@32r from %EBX to %ECX
evicting %EBX interference: Cascade 2
unassigning %vreg7 from %EBX: BH BL
assigning %vreg5 to %EBX: BH [48r,384r:0)  0@48r BL [48r,384r:0)  0@48r
queuing new interval: %vreg7 [32r,400r:0)  0@32r

selectOrSplit GR32:%vreg7 [32r,400r:0)  0@32r w=3.945312e-03
hints: %ECX
missed hint %ECX
%R15D is available at cost 1
Only trying the first 10 regs.
assigning %vreg7 to %R15D: R15B [32r,400r:0)  0@32r

selectOrSplit GR64:%vreg3 [64r,368r:0)  0@64r w=4.303977e-03
hints: %RSI
missed hint %RSI
%R12 is available at cost 1
Only trying the first 10 regs.
should evict: %vreg5 [48r,384r:0)  0@48r w= 4.116848e-03
hints: %EDX
can reassign: %vreg5 [48r,384r:0)  0@48r from %RBX to %EDX
should evict: %vreg5 [48r,384r:0)  0@48r w= 4.116848e-03
hints: %EDX
can reassign: %vreg5 [48r,384r:0)  0@48r from %RBX to %EDX
evicting %RBX interference: Cascade 3
unassigning %vreg5 from %EBX: BH BL
assigning %vreg3 to %RBX: BH [64r,368r:0)  0@64r BL [64r,368r:0)  0@64r
queuing new interval: %vreg5 [48r,384r:0)  0@48r

selectOrSplit GR32:%vreg5 [48r,384r:0)  0@48r w=4.116848e-03
hints: %EDX
missed hint %EDX
%R12D is available at cost 1
Only trying the first 10 regs.
assigning %vreg5 to %R12D: R12B [48r,384r:0)  0@48r

selectOrSplit GR64:%vreg1 [80r,352r:0)  0@80r w=4.508928e-03
hints: %RDI
missed hint %RDI
%R13 is available at cost 1
Only trying the first 10 regs.
should evict: %vreg3 [64r,368r:0)  0@64r w= 4.303977e-03
hints: %RSI
can reassign: %vreg3 [64r,368r:0)  0@64r from %RBX to %RSI
should evict: %vreg3 [64r,368r:0)  0@64r w= 4.303977e-03
hints: %RSI
can reassign: %vreg3 [64r,368r:0)  0@64r from %RBX to %RSI
evicting %RBX interference: Cascade 4
unassigning %vreg3 from %RBX: BH BL
assigning %vreg1 to %RBX: BH [80r,352r:0)  0@80r BL [80r,352r:0)  0@80r
queuing new interval: %vreg3 [64r,368r:0)  0@64r

selectOrSplit GR64:%vreg3 [64r,368r:0)  0@64r w=4.303977e-03
hints: %RSI
missed hint %RSI
%R13 is available at cost 1
Only trying the first 10 regs.
assigning %vreg3 to %R13: R13B [64r,368r:0)  0@64r

selectOrSplit GR64:%vreg12 [176r,240r:0)  0@176r w=2.176724e-03
hints: %RDI
assigning %vreg12 to %RDI: DIL [176r,240r:0)  0@176r

selectOrSplit GR64:%vreg13 [208r,256r:0)  0@208r w=4.508928e-03
hints: %RSI
assigning %vreg13 to %RSI: SIL [208r,256r:0)  0@208r

selectOrSplit GR64:%vreg29 [1216r,1248r:0)  0@1216r w=3.624749e-05
hints: %RDI
assigning %vreg29 to %RDI: DIL [1216r,1248r:0)  0@1216r

selectOrSplit GR32:%vreg28 [1296r,1360r:0)  0@1296r w=3.374766e-05
hints: %EAX
assigning %vreg28 to %EAX: AH [1296r,1360r:0)  0@1296r AL [1296r,1360r:0)  0@1296r

selectOrSplit GR64:%vreg33 [1744r,1824r:0)  0@1744r w=1.618293e-05
hints: %RAX
assigning %vreg33 to %RAX: AH [1744r,1824r:0)  0@1744r AL [1744r,1824r:0)  0@1744r

selectOrSplit GR64:%vreg71 [2640r,2672r:0)[2672r,2752r:1)  0@2640r 1@2672r w=1.493068e-05
hints: %RDI
assigning %vreg71 to %RDI: DIL [2640r,2672r:0)[2672r,2752r:1)  0@2640r 1@2672r

selectOrSplit GR32:%vreg69 [2688r,2768r:0)  0@2688r w=7.963031e-06
hints: %ESI
assigning %vreg69 to %ESI: SIL [2688r,2768r:0)  0@2688r

selectOrSplit GR32:%vreg68 [2704r,2784r:0)  0@2704r w=7.963031e-06
hints: %EDX
assigning %vreg68 to %EDX: DH [2704r,2784r:0)  0@2704r DL [2704r,2784r:0)  0@2704r

selectOrSplit GR32:%vreg67 [2720r,2800r:0)  0@2720r w=7.963031e-06
hints: %ECX
assigning %vreg67 to %ECX: CH [2720r,2800r:0)  0@2720r CL [2720r,2800r:0)  0@2720r

selectOrSplit GR32:%vreg66 [2848r,2912r:0)  0@2848r w=8.237618e-06
hints: %EAX
assigning %vreg66 to %EAX: AH [2848r,2912r:0)  0@2848r AL [2848r,2912r:0)  0@2848r

selectOrSplit GR64:%vreg93 [3200r,3248r:0)  0@3200r w=4.128299e-06
hints: %RDI
assigning %vreg93 to %RDI: DIL [3200r,3248r:0)  0@3200r

selectOrSplit GR64:%vreg116 [3520r,3584r:0)  0@3520r w=2.176724e-03
hints: %RDI
assigning %vreg116 to %RDI: DIL [3520r,3584r:0)  0@3520r

selectOrSplit GR64:%vreg117 [3552r,3600r:0)  0@3552r w=4.508928e-03
hints: %RSI
assigning %vreg117 to %RSI: SIL [3552r,3600r:0)  0@3552r

selectOrSplit GR64:%vreg114 [3696r,3712r:0)  0@3696r w=inf
hints: %RAX
assigning %vreg114 to %RAX: AH [3696r,3712r:0)  0@3696r AL [3696r,3712r:0)  0@3696r

selectOrSplit GR64:%vreg15 [496r,512r:0)  0@496r w=inf
assigning %vreg15 to %RAX: AH [496r,512r:0)  0@496r AL [496r,512r:0)  0@496r

selectOrSplit GR64:%vreg18 [592r,608r:0)  0@592r w=inf
assigning %vreg18 to %RAX: AH [592r,608r:0)  0@592r AL [592r,608r:0)  0@592r

selectOrSplit GR64:%vreg109 [1024r,1040r:0)  0@1024r w=inf
assigning %vreg109 to %RAX: AH [1024r,1040r:0)  0@1024r AL [1024r,1040r:0)  0@1024r

selectOrSplit GR64:%vreg112 [1120r,1136r:0)  0@1120r w=inf
assigning %vreg112 to %RAX: AH [1120r,1136r:0)  0@1120r AL [1120r,1136r:0)  0@1120r

selectOrSplit GR64:%vreg103 [1456r,1472r:0)  0@1456r w=inf
assigning %vreg103 to %RAX: AH [1456r,1472r:0)  0@1456r AL [1456r,1472r:0)  0@1456r

selectOrSplit GR64:%vreg106 [1552r,1568r:0)  0@1552r w=inf
assigning %vreg106 to %RAX: AH [1552r,1568r:0)  0@1552r AL [1552r,1568r:0)  0@1552r

selectOrSplit GR64:%vreg97 [1936r,1952r:0)  0@1936r w=inf
assigning %vreg97 to %RAX: AH [1936r,1952r:0)  0@1936r AL [1936r,1952r:0)  0@1936r

selectOrSplit GR64:%vreg100 [2032r,2048r:0)  0@2032r w=inf
assigning %vreg100 to %RAX: AH [2032r,2048r:0)  0@2032r AL [2032r,2048r:0)  0@2032r

selectOrSplit GR64:%vreg39 [2176r,2192r:0)  0@2176r w=inf
assigning %vreg39 to %RAX: AH [2176r,2192r:0)  0@2176r AL [2176r,2192r:0)  0@2176r

selectOrSplit GR64:%vreg42 [2272r,2288r:0)  0@2272r w=inf
assigning %vreg42 to %RAX: AH [2272r,2288r:0)  0@2272r AL [2272r,2288r:0)  0@2272r

selectOrSplit GR64:%vreg59 [2320r,2336r:0)  0@2320r w=inf
assigning %vreg59 to %RAX: AH [2320r,2336r:0)  0@2320r AL [2320r,2336r:0)  0@2320r

selectOrSplit GR64:%vreg57 [2352r,2368r:0)  0@2352r w=inf
assigning %vreg57 to %RAX: AH [2352r,2368r:0)  0@2352r AL [2352r,2368r:0)  0@2352r

selectOrSplit GR64:%vreg55 [2384r,2416r:0)  0@2384r w=8.760210e-06
assigning %vreg55 to %RAX: AH [2384r,2416r:0)  0@2384r AL [2384r,2416r:0)  0@2384r

selectOrSplit GR64:%vreg54 [2400r,2416r:0)  0@2400r w=inf
assigning %vreg54 to %RCX: CH [2400r,2416r:0)  0@2400r CL [2400r,2416r:0)  0@2400r

selectOrSplit GR64:%vreg51 [2432r,2448r:0)  0@2432r w=inf
assigning %vreg51 to %RAX: AH [2432r,2448r:0)  0@2432r AL [2432r,2448r:0)  0@2432r

selectOrSplit GR64:%vreg49 [2464r,2480r:0)  0@2464r w=inf
assigning %vreg49 to %RAX: AH [2464r,2480r:0)  0@2464r AL [2464r,2480r:0)  0@2464r

selectOrSplit GR64:%vreg47 [2496r,2512r:0)  0@2496r w=inf
assigning %vreg47 to %RAX: AH [2496r,2512r:0)  0@2496r AL [2496r,2512r:0)  0@2496r

selectOrSplit GR64:%vreg45 [2528r,2544r:0)  0@2528r w=inf
assigning %vreg45 to %RAX: AH [2528r,2544r:0)  0@2528r AL [2528r,2544r:0)  0@2528r

selectOrSplit GR32:%vreg85 [3024r,3056r:0)  0@3024r w=2.260699e-06
assigning %vreg85 to %EAX: AH [3024r,3056r:0)  0@3024r AL [3024r,3056r:0)  0@3024r

selectOrSplit GR64:%vreg84 [3040r,3056r:0)  0@3040r w=inf
assigning %vreg84 to %RCX: CH [3040r,3056r:0)  0@3040r CL [3040r,3056r:0)  0@3040r

selectOrSplit GR32:%vreg90 [3136r,3168r:0)  0@3136r w=2.260699e-06
assigning %vreg90 to %EAX: AH [3136r,3168r:0)  0@3136r AL [3136r,3168r:0)  0@3136r

selectOrSplit GR64:%vreg89 [3152r,3168r:0)  0@3152r w=inf
assigning %vreg89 to %RCX: CH [3152r,3168r:0)  0@3152r CL [3152r,3168r:0)  0@3152r

selectOrSplit GR64:%vreg80 [3392r,3408r:0)  0@3392r w=inf
assigning %vreg80 to %RAX: AH [3392r,3408r:0)  0@3392r AL [3392r,3408r:0)  0@3392r

selectOrSplit GR64:%vreg78 [3424r,3440r:0)  0@3424r w=inf
assigning %vreg78 to %RAX: AH [3424r,3440r:0)  0@3424r AL [3424r,3440r:0)  0@3424r

selectOrSplit GR64:%vreg75 [3456r,3488r:0)  0@3456r w=inf
assigning %vreg75 to %RAX: AH [3456r,3488r:0)  0@3456r AL [3456r,3488r:0)  0@3456r

********** STACK TRANSFORMATION METADATA **********
********** Function: BZ2_bzWriteOpen
********** REGISTER MAP **********
[%vreg1 -> %RBX] GR64
[%vreg3 -> %R13] GR64
[%vreg5 -> %R12D] GR32
[%vreg7 -> %R15D] GR32
[%vreg9 -> %R14D] GR32
[%vreg12 -> %RDI] GR64
[%vreg13 -> %RSI] GR64
[%vreg15 -> %RAX] GR64
[%vreg18 -> %RAX] GR64
[%vreg28 -> %EAX] GR32
[%vreg29 -> %RDI] GR64
[%vreg33 -> %RAX] GR64
[%vreg39 -> %RAX] GR64
[%vreg42 -> %RAX] GR64
[%vreg45 -> %RAX] GR64
[%vreg47 -> %RAX] GR64
[%vreg49 -> %RAX] GR64
[%vreg51 -> %RAX] GR64
[%vreg54 -> %RCX] GR64
[%vreg55 -> %RAX] GR64
[%vreg57 -> %RAX] GR64
[%vreg59 -> %RAX] GR64
[%vreg66 -> %EAX] GR32
[%vreg67 -> %ECX] GR32
[%vreg68 -> %EDX] GR32
[%vreg69 -> %ESI] GR32
[%vreg71 -> %RDI] GR64
[%vreg75 -> %RAX] GR64
[%vreg78 -> %RAX] GR64
[%vreg80 -> %RAX] GR64
[%vreg84 -> %RCX] GR64
[%vreg85 -> %EAX] GR32
[%vreg89 -> %RCX] GR64
[%vreg90 -> %EAX] GR32
[%vreg93 -> %RDI] GR64
[%vreg97 -> %RAX] GR64
[%vreg100 -> %RAX] GR64
[%vreg103 -> %RAX] GR64
[%vreg106 -> %RAX] GR64
[%vreg109 -> %RAX] GR64
[%vreg112 -> %RAX] GR64
[%vreg114 -> %RAX] GR64
[%vreg116 -> %RDI] GR64
[%vreg117 -> %RSI] GR64


Stackmap 0:
  STACKMAP 0, 0, %vreg5, 0, <fi#3>, 0, %vreg1, 0, <fi#1>, 0, 0, <fi#7>, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, %vreg7, 0, <fi#4>, 0, %vreg9, 0, <fi#5>, 0, ...; mem:LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) GR32:%vreg5,%vreg7,%vreg9 GR64:%vreg1,%vreg3

i32 %blockSize100k: in register %R12D (vreg 5)
i32* %blockSize100k.addr: in stack slot 3 (size: 4)
i32* %bzerror: in register %RBX (vreg 1)
i32** %bzerror.addr: in stack slot 1 (size: 8)
%struct.bzFile** %bzf: in stack slot 7 (size: 8)
%struct._IO_FILE* %f: in register %R13 (vreg 3)
%struct._IO_FILE** %f.addr: in stack slot 2 (size: 8)
i32* %ret: in stack slot 6 (size: 4)
i8** %retval: in stack slot 0 (size: 8)
i32 %verbosity: in register %R15D (vreg 7)
i32* %verbosity.addr: in stack slot 4 (size: 4)
i32 %workFactor: in register %R14D (vreg 9)
i32* %workFactor.addr: in stack slot 5 (size: 4)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, 0, <fi#3>, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#2>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, ...; mem:LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4)

i32* %blockSize100k.addr: in stack slot 3 (size: 4)
i32** %bzerror.addr: in stack slot 1 (size: 8)
%struct.bzFile** %bzf: in stack slot 7 (size: 8)
%struct._IO_FILE** %f.addr: in stack slot 2 (size: 8)
i32* %ret: in stack slot 6 (size: 4)
i8** %retval: in stack slot 0 (size: 8)
i32* %verbosity.addr: in stack slot 4 (size: 4)
i32* %workFactor.addr: in stack slot 5 (size: 4)

Duplicate operand locations:


Stackmap 2:
  STACKMAP 2, 0, 0, <fi#3>, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#2>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, ...; mem:LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4)

i32* %blockSize100k.addr: in stack slot 3 (size: 4)
i32** %bzerror.addr: in stack slot 1 (size: 8)
%struct.bzFile** %bzf: in stack slot 7 (size: 8)
%struct._IO_FILE** %f.addr: in stack slot 2 (size: 8)
i32* %ret: in stack slot 6 (size: 4)
i8** %retval: in stack slot 0 (size: 8)
i32* %verbosity.addr: in stack slot 4 (size: 4)
i32* %workFactor.addr: in stack slot 5 (size: 4)

Duplicate operand locations:


Stackmap 3:
  STACKMAP 3, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack6](align=4) LD8[FixedStack0]

i32** %bzerror.addr: in stack slot 1 (size: 8)
%struct.bzFile** %bzf: in stack slot 7 (size: 8)
i32* %ret: in stack slot 6 (size: 4)
i8** %retval: in stack slot 0 (size: 8)

Duplicate operand locations:


Stackmap 4:
  STACKMAP 4, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0]

i8** %retval: in stack slot 0 (size: 8)

Duplicate operand locations:


Stackmap 5:
  STACKMAP 5, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0]

i8** %retval: in stack slot 0 (size: 8)

Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, %vreg5, 0, <fi#3>, 0, %vreg1, 0, <fi#1>, 0, 0, <fi#7>, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, %vreg7, 0, <fi#4>, 0, %vreg9, 0, <fi#5>, 0, ...; mem:LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) GR32:%vreg5,%vreg7,%vreg9 GR64:%vreg1,%vreg3
  -> Call instruction SlotIndex 272B, searching vregs 0 -> 118 and stack slots -1 -> 8

  STACKMAP 1, 0, 0, <fi#3>, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#2>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, ...; mem:LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4)
  -> Call instruction SlotIndex 1264B, searching vregs 0 -> 118 and stack slots -1 -> 8

  STACKMAP 2, 0, 0, <fi#3>, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#2>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, ...; mem:LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4)
  -> Call instruction SlotIndex 1712B, searching vregs 0 -> 118 and stack slots -1 -> 8

  STACKMAP 3, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack6](align=4) LD8[FixedStack0]
  -> Call instruction SlotIndex 2816B, searching vregs 0 -> 118 and stack slots -1 -> 8

  STACKMAP 4, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0]
  -> Call instruction SlotIndex 3264B, searching vregs 0 -> 118 and stack slots -1 -> 8

  STACKMAP 5, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0]
  -> Call instruction SlotIndex 3616B, searching vregs 0 -> 118 and stack slots -1 -> 8

********** REWRITE VIRTUAL REGISTERS **********
********** Function: BZ2_bzWriteOpen
********** REGISTER MAP **********
[%vreg1 -> %RBX] GR64
[%vreg3 -> %R13] GR64
[%vreg5 -> %R12D] GR32
[%vreg7 -> %R15D] GR32
[%vreg9 -> %R14D] GR32
[%vreg12 -> %RDI] GR64
[%vreg13 -> %RSI] GR64
[%vreg15 -> %RAX] GR64
[%vreg18 -> %RAX] GR64
[%vreg28 -> %EAX] GR32
[%vreg29 -> %RDI] GR64
[%vreg33 -> %RAX] GR64
[%vreg39 -> %RAX] GR64
[%vreg42 -> %RAX] GR64
[%vreg45 -> %RAX] GR64
[%vreg47 -> %RAX] GR64
[%vreg49 -> %RAX] GR64
[%vreg51 -> %RAX] GR64
[%vreg54 -> %RCX] GR64
[%vreg55 -> %RAX] GR64
[%vreg57 -> %RAX] GR64
[%vreg59 -> %RAX] GR64
[%vreg66 -> %EAX] GR32
[%vreg67 -> %ECX] GR32
[%vreg68 -> %EDX] GR32
[%vreg69 -> %ESI] GR32
[%vreg71 -> %RDI] GR64
[%vreg75 -> %RAX] GR64
[%vreg78 -> %RAX] GR64
[%vreg80 -> %RAX] GR64
[%vreg84 -> %RCX] GR64
[%vreg85 -> %EAX] GR32
[%vreg89 -> %RCX] GR64
[%vreg90 -> %EAX] GR32
[%vreg93 -> %RDI] GR64
[%vreg97 -> %RAX] GR64
[%vreg100 -> %RAX] GR64
[%vreg103 -> %RAX] GR64
[%vreg106 -> %RAX] GR64
[%vreg109 -> %RAX] GR64
[%vreg112 -> %RAX] GR64
[%vreg114 -> %RAX] GR64
[%vreg116 -> %RDI] GR64
[%vreg117 -> %RSI] GR64

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %ECX %EDX %RDI %RSI %R8D
16B		%vreg9<def> = COPY %R8D; GR32:%vreg9
32B		%vreg7<def> = COPY %ECX; GR32:%vreg7
48B		%vreg5<def> = COPY %EDX; GR32:%vreg5
64B		%vreg3<def> = COPY %RSI; GR64:%vreg3
80B		%vreg1<def> = COPY %RDI; GR64:%vreg1
176B		%vreg12<def> = MOV64ri <ga:@BZ2_bzWriteOpen>; GR64:%vreg12
208B		%vreg13<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg13
224B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
240B		%RDI<def> = COPY %vreg12<kill>; GR64:%vreg12
256B		%RSI<def> = COPY %vreg13<kill>; GR64:%vreg13
272B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
288B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
304B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
320B		STACKMAP 0, 0, %vreg5, 0, <fi#3>, 0, %vreg1, 0, <fi#1>, 0, 0, <fi#7>, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, %vreg7, 0, <fi#4>, 0, %vreg9, 0, <fi#5>, 0, ...; mem:LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) GR32:%vreg5,%vreg7,%vreg9 GR64:%vreg1,%vreg3
336B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
352B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg1<kill>; mem:ST8[%bzerror.addr] GR64:%vreg1
368B		MOV64mr <fi#2>, 1, %noreg, 0, %noreg, %vreg3<kill>; mem:ST8[%f.addr] GR64:%vreg3
384B		MOV32mr <fi#3>, 1, %noreg, 0, %noreg, %vreg5<kill>; mem:ST4[%blockSize100k.addr] GR32:%vreg5
400B		MOV32mr <fi#4>, 1, %noreg, 0, %noreg, %vreg7<kill>; mem:ST4[%verbosity.addr] GR32:%vreg7
416B		MOV32mr <fi#5>, 1, %noreg, 0, %noreg, %vreg9<kill>; mem:ST4[%workFactor.addr] GR32:%vreg9
432B		MOV64mi32 <fi#7>, 1, %noreg, 0, %noreg, 0; mem:ST8[%bzf]
448B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
464B		JE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1
> %R14D<def> = COPY %R8D
> %R15D<def> = COPY %ECX
> %R12D<def> = COPY %EDX
> %R13<def> = COPY %RSI
> %RBX<def> = COPY %RDI
> %RDI<def> = MOV64ri <ga:@BZ2_bzWriteOpen>
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 0, 0, %R12D, 0, <fi#3>, 0, %RBX, 0, <fi#1>, 0, 0, <fi#7>, 0, %R13, 0, <fi#2>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, %R15D, 0, <fi#4>, 0, %R14D, 0, <fi#5>, 0, ...; mem:LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %RBX<kill>; mem:ST8[%bzerror.addr]
> MOV64mr <fi#2>, 1, %noreg, 0, %noreg, %R13<kill>; mem:ST8[%f.addr]
> MOV32mr <fi#3>, 1, %noreg, 0, %noreg, %R12D<kill>; mem:ST4[%blockSize100k.addr]
> MOV32mr <fi#4>, 1, %noreg, 0, %noreg, %R15D<kill>; mem:ST4[%verbosity.addr]
> MOV32mr <fi#5>, 1, %noreg, 0, %noreg, %R14D<kill>; mem:ST4[%workFactor.addr]
> MOV64mi32 <fi#7>, 1, %noreg, 0, %noreg, 0; mem:ST8[%bzf]
> CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
> JE_1 <BB#2>, %EFLAGS<imp-use,kill>
480B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
496B		%vreg15<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg15
512B		MOV32mi %vreg15<kill>, 1, %noreg, 0, %noreg, 0; mem:ST4[%1] GR64:%vreg15
	    Successors according to CFG: BB#2
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 0, %noreg, 0; mem:ST4[%1]
528B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#1
544B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
560B		JE_1 <BB#4>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#4 BB#3
> CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
> JE_1 <BB#4>, %EFLAGS<imp-use,kill>
576B	BB#3: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#2
592B		%vreg18<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg18
608B		MOV32mi %vreg18<kill>, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr] GR64:%vreg18
	    Successors according to CFG: BB#4
> %RAX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV32mi %RAX<kill>, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr]
624B	BB#4: derived from LLVM BB %if.end.3
	    Predecessors according to CFG: BB#2 BB#3
640B		CMP64mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%f.addr]
656B		JE_1 <BB#11>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#11 BB#5
> CMP64mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%f.addr]
> JE_1 <BB#11>, %EFLAGS<imp-use,kill>
672B	BB#5: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#4
688B		CMP32mi8 <fi#3>, 1, %noreg, 0, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%blockSize100k.addr]
704B		JL_1 <BB#11>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#11 BB#6
> CMP32mi8 <fi#3>, 1, %noreg, 0, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%blockSize100k.addr]
> JL_1 <BB#11>, %EFLAGS<imp-use,kill>
720B	BB#6: derived from LLVM BB %lor.lhs.false.6
	    Predecessors according to CFG: BB#5
736B		CMP32mi8 <fi#3>, 1, %noreg, 0, %noreg, 9, %EFLAGS<imp-def>; mem:LD4[%blockSize100k.addr]
752B		JG_1 <BB#11>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#11 BB#7
> CMP32mi8 <fi#3>, 1, %noreg, 0, %noreg, 9, %EFLAGS<imp-def>; mem:LD4[%blockSize100k.addr]
> JG_1 <BB#11>, %EFLAGS<imp-use,kill>
768B	BB#7: derived from LLVM BB %lor.lhs.false.8
	    Predecessors according to CFG: BB#6
784B		CMP32mi8 <fi#5>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%workFactor.addr]
800B		JL_1 <BB#11>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#11 BB#8
> CMP32mi8 <fi#5>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%workFactor.addr]
> JL_1 <BB#11>, %EFLAGS<imp-use,kill>
816B	BB#8: derived from LLVM BB %lor.lhs.false.10
	    Predecessors according to CFG: BB#7
832B		CMP32mi <fi#5>, 1, %noreg, 0, %noreg, 250, %EFLAGS<imp-def>; mem:LD4[%workFactor.addr]
848B		JG_1 <BB#11>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#11 BB#9
> CMP32mi <fi#5>, 1, %noreg, 0, %noreg, 250, %EFLAGS<imp-def>; mem:LD4[%workFactor.addr]
> JG_1 <BB#11>, %EFLAGS<imp-use,kill>
864B	BB#9: derived from LLVM BB %lor.lhs.false.12
	    Predecessors according to CFG: BB#8
880B		CMP32mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%verbosity.addr]
896B		JL_1 <BB#11>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#11 BB#10
> CMP32mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%verbosity.addr]
> JL_1 <BB#11>, %EFLAGS<imp-use,kill>
912B	BB#10: derived from LLVM BB %lor.lhs.false.14
	    Predecessors according to CFG: BB#9
928B		CMP32mi8 <fi#4>, 1, %noreg, 0, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%verbosity.addr]
944B		JLE_1 <BB#16>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#16 BB#11
> CMP32mi8 <fi#4>, 1, %noreg, 0, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%verbosity.addr]
> JLE_1 <BB#16>, %EFLAGS<imp-use,kill>
960B	BB#11: derived from LLVM BB %if.then.16
	    Predecessors according to CFG: BB#4 BB#5 BB#6 BB#7 BB#8 BB#9 BB#10
976B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
992B		JE_1 <BB#13>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#13 BB#12
> CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
> JE_1 <BB#13>, %EFLAGS<imp-use,kill>
1008B	BB#12: derived from LLVM BB %if.then.18
	    Predecessors according to CFG: BB#11
1024B		%vreg109<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg109
1040B		MOV32mi %vreg109<kill>, 1, %noreg, 0, %noreg, -2; mem:ST4[%12] GR64:%vreg109
	    Successors according to CFG: BB#13
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 0, %noreg, -2; mem:ST4[%12]
1056B	BB#13: derived from LLVM BB %if.end.19
	    Predecessors according to CFG: BB#11 BB#12
1072B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
1088B		JE_1 <BB#15>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#15 BB#14
> CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
> JE_1 <BB#15>, %EFLAGS<imp-use,kill>
1104B	BB#14: derived from LLVM BB %if.then.21
	    Predecessors according to CFG: BB#13
1120B		%vreg112<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg112
1136B		MOV32mi %vreg112<kill>, 1, %noreg, 5096, %noreg, -2; mem:ST4[%lastErr22] GR64:%vreg112
	    Successors according to CFG: BB#15
> %RAX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV32mi %RAX<kill>, 1, %noreg, 5096, %noreg, -2; mem:ST4[%lastErr22]
1152B	BB#15: derived from LLVM BB %if.end.23
	    Predecessors according to CFG: BB#13 BB#14
1168B		MOV64mi32 <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST8[%retval]
1184B		JMP_1 <BB#41>
	    Successors according to CFG: BB#41
> MOV64mi32 <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST8[%retval]
> JMP_1 <BB#41>
1200B	BB#16: derived from LLVM BB %if.end.24
	    Predecessors according to CFG: BB#10
1216B		%vreg29<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%f.addr] GR64:%vreg29
1232B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1248B		%RDI<def> = COPY %vreg29<kill>; GR64:%vreg29
1264B		CALL64pcrel32 <ga:@ferror>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
1280B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1296B		%vreg28<def> = COPY %EAX; GR32:%vreg28
1312B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1328B		STACKMAP 1, 0, 0, <fi#3>, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#2>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, ...; mem:LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4)
1344B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1360B		CMP32ri8 %vreg28<kill>, 0, %EFLAGS<imp-def>; GR32:%vreg28
1376B		JE_1 <BB#22>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#22 BB#17
> %RDI<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%f.addr]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@ferror>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def> = COPY %EAX
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 1, 0, 0, <fi#3>, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#2>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, ...; mem:LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> CMP32ri8 %EAX<kill>, 0, %EFLAGS<imp-def>
> JE_1 <BB#22>, %EFLAGS<imp-use,kill>
1392B	BB#17: derived from LLVM BB %if.then.25
	    Predecessors according to CFG: BB#16
1408B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
1424B		JE_1 <BB#19>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#19 BB#18
> CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
> JE_1 <BB#19>, %EFLAGS<imp-use,kill>
1440B	BB#18: derived from LLVM BB %if.then.27
	    Predecessors according to CFG: BB#17
1456B		%vreg103<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg103
1472B		MOV32mi %vreg103<kill>, 1, %noreg, 0, %noreg, -6; mem:ST4[%17] GR64:%vreg103
	    Successors according to CFG: BB#19
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 0, %noreg, -6; mem:ST4[%17]
1488B	BB#19: derived from LLVM BB %if.end.28
	    Predecessors according to CFG: BB#17 BB#18
1504B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
1520B		JE_1 <BB#21>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#21 BB#20
> CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
> JE_1 <BB#21>, %EFLAGS<imp-use,kill>
1536B	BB#20: derived from LLVM BB %if.then.30
	    Predecessors according to CFG: BB#19
1552B		%vreg106<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg106
1568B		MOV32mi %vreg106<kill>, 1, %noreg, 5096, %noreg, -6; mem:ST4[%lastErr31] GR64:%vreg106
	    Successors according to CFG: BB#21
> %RAX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV32mi %RAX<kill>, 1, %noreg, 5096, %noreg, -6; mem:ST4[%lastErr31]
1584B	BB#21: derived from LLVM BB %if.end.32
	    Predecessors according to CFG: BB#19 BB#20
1600B		MOV64mi32 <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST8[%retval]
1616B		JMP_1 <BB#41>
	    Successors according to CFG: BB#41
> MOV64mi32 <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST8[%retval]
> JMP_1 <BB#41>
1632B	BB#22: derived from LLVM BB %if.end.33
	    Predecessors according to CFG: BB#16
1680B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1696B		%EDI<def,dead> = MOV32ri 5104, %RDI<imp-def>
1712B		CALL64pcrel32 <ga:@malloc>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RAX<imp-def>
1728B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1744B		%vreg33<def> = COPY %RAX; GR64:%vreg33
1760B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1776B		STACKMAP 2, 0, 0, <fi#3>, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#2>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, ...; mem:LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4)
1792B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1824B		MOV64mr <fi#7>, 1, %noreg, 0, %noreg, %vreg33<kill>; mem:ST8[%bzf] GR64:%vreg33
1840B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
1856B		JNE_1 <BB#28>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#28 BB#23
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EDI<def,dead> = MOV32ri 5104, %RDI<imp-def>
> CALL64pcrel32 <ga:@malloc>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RAX<def> = COPY %RAX
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 2, 0, 0, <fi#3>, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#2>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, ...; mem:LD8[FixedStack3](align=4) LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV64mr <fi#7>, 1, %noreg, 0, %noreg, %RAX<kill>; mem:ST8[%bzf]
> CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
> JNE_1 <BB#28>, %EFLAGS<imp-use,kill>
1872B	BB#23: derived from LLVM BB %if.then.36
	    Predecessors according to CFG: BB#22
1888B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
1904B		JE_1 <BB#25>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#25 BB#24
> CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
> JE_1 <BB#25>, %EFLAGS<imp-use,kill>
1920B	BB#24: derived from LLVM BB %if.then.38
	    Predecessors according to CFG: BB#23
1936B		%vreg97<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg97
1952B		MOV32mi %vreg97<kill>, 1, %noreg, 0, %noreg, -3; mem:ST4[%23] GR64:%vreg97
	    Successors according to CFG: BB#25
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 0, %noreg, -3; mem:ST4[%23]
1968B	BB#25: derived from LLVM BB %if.end.39
	    Predecessors according to CFG: BB#23 BB#24
1984B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
2000B		JE_1 <BB#27>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#27 BB#26
> CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
> JE_1 <BB#27>, %EFLAGS<imp-use,kill>
2016B	BB#26: derived from LLVM BB %if.then.41
	    Predecessors according to CFG: BB#25
2032B		%vreg100<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg100
2048B		MOV32mi %vreg100<kill>, 1, %noreg, 5096, %noreg, -3; mem:ST4[%lastErr42] GR64:%vreg100
	    Successors according to CFG: BB#27
> %RAX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV32mi %RAX<kill>, 1, %noreg, 5096, %noreg, -3; mem:ST4[%lastErr42]
2064B	BB#27: derived from LLVM BB %if.end.43
	    Predecessors according to CFG: BB#25 BB#26
2080B		MOV64mi32 <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST8[%retval]
2096B		JMP_1 <BB#41>
	    Successors according to CFG: BB#41
> MOV64mi32 <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST8[%retval]
> JMP_1 <BB#41>
2112B	BB#28: derived from LLVM BB %if.end.44
	    Predecessors according to CFG: BB#22
2128B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
2144B		JE_1 <BB#30>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#30 BB#29
> CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
> JE_1 <BB#30>, %EFLAGS<imp-use,kill>
2160B	BB#29: derived from LLVM BB %if.then.46
	    Predecessors according to CFG: BB#28
2176B		%vreg39<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg39
2192B		MOV32mi %vreg39<kill>, 1, %noreg, 0, %noreg, 0; mem:ST4[%27] GR64:%vreg39
	    Successors according to CFG: BB#30
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 0, %noreg, 0; mem:ST4[%27]
2208B	BB#30: derived from LLVM BB %if.end.47
	    Predecessors according to CFG: BB#28 BB#29
2224B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
2240B		JE_1 <BB#32>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#32 BB#31
> CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
> JE_1 <BB#32>, %EFLAGS<imp-use,kill>
2256B	BB#31: derived from LLVM BB %if.then.49
	    Predecessors according to CFG: BB#30
2272B		%vreg42<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg42
2288B		MOV32mi %vreg42<kill>, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr50] GR64:%vreg42
	    Successors according to CFG: BB#32
> %RAX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV32mi %RAX<kill>, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr50]
2304B	BB#32: derived from LLVM BB %if.end.51
	    Predecessors according to CFG: BB#30 BB#31
2320B		%vreg59<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg59
2336B		MOV8mi %vreg59<kill>, 1, %noreg, 5100, %noreg, 0; mem:ST1[%initialisedOk] GR64:%vreg59
2352B		%vreg57<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg57
2368B		MOV32mi %vreg57<kill>, 1, %noreg, 5008, %noreg, 0; mem:ST4[%bufN] GR64:%vreg57
2384B		%vreg55<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%f.addr] GR64:%vreg55
2400B		%vreg54<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg54
2416B		MOV64mr %vreg54<kill>, 1, %noreg, 0, %noreg, %vreg55<kill>; mem:ST8[%handle] GR64:%vreg54,%vreg55
2432B		%vreg51<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg51
2448B		MOV8mi %vreg51<kill>, 1, %noreg, 5012, %noreg, 1; mem:ST1[%writing] GR64:%vreg51
2464B		%vreg49<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg49
2480B		MOV64mi32 %vreg49<kill>, 1, %noreg, 5072, %noreg, 0; mem:ST8[%bzalloc] GR64:%vreg49
2496B		%vreg47<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg47
2512B		MOV64mi32 %vreg47<kill>, 1, %noreg, 5080, %noreg, 0; mem:ST8[%bzfree] GR64:%vreg47
2528B		%vreg45<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg45
2544B		MOV64mi32 %vreg45<kill>, 1, %noreg, 5088, %noreg, 0; mem:ST8[%opaque] GR64:%vreg45
2560B		CMP32mi8 <fi#5>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%workFactor.addr]
2576B		JNE_1 <BB#34>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#34 BB#33
> %RAX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV8mi %RAX<kill>, 1, %noreg, 5100, %noreg, 0; mem:ST1[%initialisedOk]
> %RAX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV32mi %RAX<kill>, 1, %noreg, 5008, %noreg, 0; mem:ST4[%bufN]
> %RAX<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%f.addr]
> %RCX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV64mr %RCX<kill>, 1, %noreg, 0, %noreg, %RAX<kill>; mem:ST8[%handle]
> %RAX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV8mi %RAX<kill>, 1, %noreg, 5012, %noreg, 1; mem:ST1[%writing]
> %RAX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV64mi32 %RAX<kill>, 1, %noreg, 5072, %noreg, 0; mem:ST8[%bzalloc]
> %RAX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV64mi32 %RAX<kill>, 1, %noreg, 5080, %noreg, 0; mem:ST8[%bzfree]
> %RAX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV64mi32 %RAX<kill>, 1, %noreg, 5088, %noreg, 0; mem:ST8[%opaque]
> CMP32mi8 <fi#5>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%workFactor.addr]
> JNE_1 <BB#34>, %EFLAGS<imp-use,kill>
2592B	BB#33: derived from LLVM BB %if.then.55
	    Predecessors according to CFG: BB#32
2608B		MOV32mi <fi#5>, 1, %noreg, 0, %noreg, 30; mem:ST4[%workFactor.addr]
	    Successors according to CFG: BB#34
> MOV32mi <fi#5>, 1, %noreg, 0, %noreg, 30; mem:ST4[%workFactor.addr]
2624B	BB#34: derived from LLVM BB %if.end.56
	    Predecessors according to CFG: BB#32 BB#33
2640B		%vreg71<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg71
2672B		%vreg71<def,tied1> = ADD64ri32 %vreg71<kill,tied0>, 5016, %EFLAGS<imp-def,dead>; GR64:%vreg71
2688B		%vreg69<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%blockSize100k.addr] GR32:%vreg69
2704B		%vreg68<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%verbosity.addr] GR32:%vreg68
2720B		%vreg67<def> = MOV32rm <fi#5>, 1, %noreg, 0, %noreg; mem:LD4[%workFactor.addr] GR32:%vreg67
2736B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2752B		%RDI<def> = COPY %vreg71<kill>; GR64:%vreg71
2768B		%ESI<def> = COPY %vreg69<kill>; GR32:%vreg69
2784B		%EDX<def> = COPY %vreg68<kill>; GR32:%vreg68
2800B		%ECX<def> = COPY %vreg67<kill>; GR32:%vreg67
2816B		CALL64pcrel32 <ga:@BZ2_bzCompressInit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %EDX<imp-use>, %ECX<imp-use>, %EAX<imp-def>
2832B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2848B		%vreg66<def> = COPY %EAX; GR32:%vreg66
2864B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2880B		STACKMAP 3, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack6](align=4) LD8[FixedStack0]
2896B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2912B		MOV32mr <fi#6>, 1, %noreg, 0, %noreg, %vreg66<kill>; mem:ST4[%ret] GR32:%vreg66
2928B		CMP32mi8 <fi#6>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%ret]
2944B		JE_1 <BB#40>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#40 BB#35
> %RDI<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> %RDI<def,tied1> = ADD64ri32 %RDI<kill,tied0>, 5016, %EFLAGS<imp-def,dead>
> %ESI<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%blockSize100k.addr]
> %EDX<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%verbosity.addr]
> %ECX<def> = MOV32rm <fi#5>, 1, %noreg, 0, %noreg; mem:LD4[%workFactor.addr]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %ESI<def> = COPY %ESI<kill>
Deleting identity copy.
> %EDX<def> = COPY %EDX<kill>
Deleting identity copy.
> %ECX<def> = COPY %ECX<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@BZ2_bzCompressInit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %EDX<imp-use>, %ECX<imp-use>, %EAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def> = COPY %EAX
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 3, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack6](align=4) LD8[FixedStack0]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV32mr <fi#6>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%ret]
> CMP32mi8 <fi#6>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%ret]
> JE_1 <BB#40>, %EFLAGS<imp-use,kill>
2960B	BB#35: derived from LLVM BB %if.then.60
	    Predecessors according to CFG: BB#34
2976B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
2992B		JE_1 <BB#37>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#37 BB#36
> CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
> JE_1 <BB#37>, %EFLAGS<imp-use,kill>
3008B	BB#36: derived from LLVM BB %if.then.62
	    Predecessors according to CFG: BB#35
3024B		%vreg85<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%ret] GR32:%vreg85
3040B		%vreg84<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg84
3056B		MOV32mr %vreg84<kill>, 1, %noreg, 0, %noreg, %vreg85<kill>; mem:ST4[%46] GR64:%vreg84 GR32:%vreg85
	    Successors according to CFG: BB#37
> %EAX<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%ret]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr]
> MOV32mr %RCX<kill>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%46]
3072B	BB#37: derived from LLVM BB %if.end.63
	    Predecessors according to CFG: BB#35 BB#36
3088B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
3104B		JE_1 <BB#39>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#39 BB#38
> CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
> JE_1 <BB#39>, %EFLAGS<imp-use,kill>
3120B	BB#38: derived from LLVM BB %if.then.65
	    Predecessors according to CFG: BB#37
3136B		%vreg90<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%ret] GR32:%vreg90
3152B		%vreg89<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg89
3168B		MOV32mr %vreg89<kill>, 1, %noreg, 5096, %noreg, %vreg90<kill>; mem:ST4[%lastErr66] GR64:%vreg89 GR32:%vreg90
	    Successors according to CFG: BB#39
> %EAX<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%ret]
> %RCX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV32mr %RCX<kill>, 1, %noreg, 5096, %noreg, %EAX<kill>; mem:ST4[%lastErr66]
3184B	BB#39: derived from LLVM BB %if.end.67
	    Predecessors according to CFG: BB#37 BB#38
3200B		%vreg93<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg93
3232B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3248B		%RDI<def> = COPY %vreg93<kill>; GR64:%vreg93
3264B		CALL64pcrel32 <ga:@free>, <regmask>, %RSP<imp-use>, %RDI<imp-use>
3280B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3296B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3312B		STACKMAP 4, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0]
3328B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3344B		MOV64mi32 <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST8[%retval]
3360B		JMP_1 <BB#41>
	    Successors according to CFG: BB#41
> %RDI<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@free>, <regmask>, %RSP<imp-use>, %RDI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 4, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV64mi32 <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST8[%retval]
> JMP_1 <BB#41>
3376B	BB#40: derived from LLVM BB %if.end.68
	    Predecessors according to CFG: BB#34
3392B		%vreg80<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg80
3408B		MOV32mi %vreg80<kill>, 1, %noreg, 5024, %noreg, 0; mem:ST4[%avail_in] GR64:%vreg80
3424B		%vreg78<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg78
3440B		MOV8mi %vreg78<kill>, 1, %noreg, 5100, %noreg, 1; mem:ST1[%initialisedOk70] GR64:%vreg78
3456B		%vreg75<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg75
3488B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg75<kill>; mem:ST8[%retval] GR64:%vreg75
	    Successors according to CFG: BB#41
> %RAX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV32mi %RAX<kill>, 1, %noreg, 5024, %noreg, 0; mem:ST4[%avail_in]
> %RAX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV8mi %RAX<kill>, 1, %noreg, 5100, %noreg, 1; mem:ST1[%initialisedOk70]
> %RAX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %RAX<kill>; mem:ST8[%retval]
3504B	BB#41: derived from LLVM BB %return
	    Predecessors according to CFG: BB#40 BB#39 BB#27 BB#21 BB#15
3520B		%vreg116<def> = MOV64ri <ga:@BZ2_bzWriteOpen>; GR64:%vreg116
3552B		%vreg117<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg117
3568B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3584B		%RDI<def> = COPY %vreg116<kill>; GR64:%vreg116
3600B		%RSI<def> = COPY %vreg117<kill>; GR64:%vreg117
3616B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
3632B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3648B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3664B		STACKMAP 5, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0]
3680B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3696B		%vreg114<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%retval] GR64:%vreg114
3712B		%RAX<def> = COPY %vreg114<kill>; GR64:%vreg114
3728B		RETQ %RAX<imp-use>
> %RDI<def> = MOV64ri <ga:@BZ2_bzWriteOpen>
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 5, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%retval]
> %RAX<def> = COPY %RAX<kill>
Deleting identity copy.
> RETQ %RAX<imp-use>
Computing live-in reg-units in ABI blocks.
0B	BB#0 DIL#0 SIL#0 DH#0 DL#0 CH#0 CL#0
Created 6 new intervals.
********** INTERVALS **********
CH [0B,16r:0)[3072r,3088r:1)  0@0B-phi 1@3072r
CL [0B,16r:0)[3072r,3088r:1)  0@0B-phi 1@3072r
DH [0B,32r:0)[3056r,3088r:1)  0@0B-phi 1@3056r
DIL [0B,64r:0)[208r,240r:6)[1328r,1344r:5)[2288r,2320r:4)[3024r,3088r:3)[3328r,3344r:2)[4128r,4160r:1)  0@0B-phi 1@4128r 2@3328r 3@3024r 4@2288r 5@1328r 6@208r
DL [0B,32r:0)[3056r,3088r:1)  0@0B-phi 1@3056r
SIL [0B,48r:0)[224r,240r:4)[2304r,2320r:1)[3040r,3088r:3)[4144r,4160r:2)  0@0B-phi 1@2304r 2@4144r 3@3040r 4@224r
%vreg0 [64r,80r:0)  0@64r
%vreg1 [80r,320r:0)  0@80r
%vreg2 [48r,96r:0)  0@48r
%vreg3 [96r,336r:0)  0@96r
%vreg4 [32r,112r:0)  0@32r
%vreg5 [112r,352r:0)  0@112r
%vreg6 [16r,128r:0)  0@16r
%vreg7 [128r,368r:0)  0@128r
%vreg11 [400r,416r:0)  0@400r
%vreg12 [384r,400r:0)  0@384r
%vreg13 [144r,160r:0)  0@144r
%vreg14 [160r,208r:0)  0@160r
%vreg15 [176r,224r:0)  0@176r
%vreg17 [480r,496r:0)  0@480r
%vreg20 [576r,592r:0)  0@576r
%vreg26 [992r,1008r:0)  0@992r
%vreg29 [1104r,1120r:0)  0@1104r
%vreg32 [1200r,1216r:0)  0@1200r
%vreg35 [1376r,1440r:0)  0@1376r
%vreg37 [1296r,1328r:0)  0@1296r
%vreg38 [1280r,1296r:0)  0@1280r
%vreg42 [2048r,2064r:0)  0@2048r
%vreg43 [2032r,2064r:0)  0@2032r
%vreg46 [2000r,2016r:0)  0@2000r
%vreg47 [1984r,2016r:0)  0@1984r
%vreg51 [2096r,2304r:0)  0@2096r
%vreg52 [2352r,2416r:0)  0@2352r
%vreg54 [2240r,2256r:0)[2256r,2288r:1)  0@2240r 1@2256r
%vreg55 [2224r,2240r:0)  0@2224r
%vreg58 [2192r,2208r:0)  0@2192r
%vreg61 [2160r,2176r:0)[2176r,2208r:1)  0@2160r 1@2176r
%vreg62 [2144r,2160r:0)  0@2144r
%vreg64 [2112r,2128r:0)  0@2112r
%vreg67 [2736r,2752r:0)  0@2736r
%vreg70 [3216r,3232r:0)  0@3216r
%vreg73 [3184r,3200r:0)  0@3184r
%vreg75 [2800r,2816r:0)  0@2800r
%vreg76 [2816r,3040r:0)  0@2816r
%vreg79 [3120r,3184r:0)  0@3120r
%vreg81 [2992r,3072r:0)  0@2992r
%vreg82 [2976r,2992r:0)  0@2976r
%vreg84 [2960r,3056r:0)  0@2960r
%vreg87 [2928r,2944r:0)[2944r,3024r:1)  0@2928r 1@2944r
%vreg88 [2912r,2928r:0)  0@2912r
%vreg90 [2832r,2864r:0)  0@2832r
%vreg92 [2864r,2880r:0)[2880r,2896r:1)  0@2864r 1@2880r
%vreg94 [2848r,2880r:0)  0@2848r
%vreg97 [3376r,3440r:0)  0@3376r
%vreg99 [3296r,3328r:0)  0@3296r
%vreg100 [3280r,3296r:0)  0@3280r
%vreg103 [3744r,3760r:0)  0@3744r
%vreg106 [3856r,3872r:0)  0@3856r
%vreg109 [3952r,3968r:0)  0@3952r
%vreg112 [3536r,3552r:0)  0@3536r
%vreg115 [3632r,3648r:0)  0@3632r
%vreg119 [2544r,2560r:0)  0@2544r
%vreg120 [2528r,2560r:0)  0@2528r
%vreg124 [2656r,2672r:0)  0@2656r
%vreg125 [2640r,2672r:0)  0@2640r
%vreg128 [1808r,1824r:0)  0@1808r
%vreg131 [1904r,1920r:0)  0@1904r
%vreg134 [1536r,1552r:0)  0@1536r
%vreg137 [1632r,1648r:0)  0@1632r
%vreg140 [816r,832r:0)  0@816r
%vreg143 [912r,928r:0)  0@912r
%vreg144 [4064r,4080r:0)  0@4064r
%vreg145 [4080r,4128r:0)  0@4080r
%vreg146 [4096r,4144r:0)  0@4096r
RegMasks: 240r 1344r 2320r 3088r 3344r 4160r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzWrite: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=8, align=8, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=8, align=8, at location [SP+8]
  fi#3: size=4, align=4, at location [SP+8]
  fi#4: size=4, align=4, at location [SP+8]
  fi#5: size=4, align=4, at location [SP+8]
  fi#6: size=4, align=4, at location [SP+8]
  fi#7: size=8, align=8, at location [SP+8]
Function Live Ins: %RDI in %vreg0, %RSI in %vreg2, %RDX in %vreg4, %ECX in %vreg6

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI %RSI %RDX %ECX
16B		%vreg6<def> = COPY %ECX; GR32:%vreg6
32B		%vreg4<def> = COPY %RDX; GR64:%vreg4
48B		%vreg2<def> = COPY %RSI; GR64:%vreg2
64B		%vreg0<def> = COPY %RDI; GR64:%vreg0
80B		%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
96B		%vreg3<def> = COPY %vreg2; GR64:%vreg3,%vreg2
112B		%vreg5<def> = COPY %vreg4; GR64:%vreg5,%vreg4
128B		%vreg7<def> = COPY %vreg6; GR32:%vreg7,%vreg6
144B		%vreg13<def> = MOV64ri <ga:@BZ2_bzWrite>; GR64:%vreg13
160B		%vreg14<def> = COPY %vreg13; GR64:%vreg14,%vreg13
176B		%vreg15<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg15
192B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
208B		%RDI<def> = COPY %vreg14; GR64:%vreg14
224B		%RSI<def> = COPY %vreg15; GR64:%vreg15
240B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
256B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
272B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
288B		STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg5, 0, <fi#2>, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#7>, 0, %vreg7, 0, <fi#3>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack0] LD8[FixedStack7] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) GR64:%vreg3,%vreg5,%vreg1 GR32:%vreg7
304B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
320B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%bzerror.addr] GR64:%vreg1
336B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg3; mem:ST8[%b.addr] GR64:%vreg3
352B		MOV64mr <fi#2>, 1, %noreg, 0, %noreg, %vreg5; mem:ST8[%buf.addr] GR64:%vreg5
368B		MOV32mr <fi#3>, 1, %noreg, 0, %noreg, %vreg7; mem:ST4[%len.addr] GR32:%vreg7
384B		%vreg12<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr] GR64:%vreg12
400B		%vreg11<def> = COPY %vreg12; GR64:%vreg11,%vreg12
416B		MOV64mr <fi#7>, 1, %noreg, 0, %noreg, %vreg11; mem:ST8[%bzf] GR64:%vreg11
432B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
448B		JE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

464B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
480B		%vreg17<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg17
496B		MOV32mi %vreg17, 1, %noreg, 0, %noreg, 0; mem:ST4[%3] GR64:%vreg17
	    Successors according to CFG: BB#2

512B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#1
528B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
544B		JE_1 <BB#4>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#4 BB#3

560B	BB#3: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#2
576B		%vreg20<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg20
592B		MOV32mi %vreg20, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr] GR64:%vreg20
	    Successors according to CFG: BB#4

608B	BB#4: derived from LLVM BB %if.end.3
	    Predecessors according to CFG: BB#2 BB#3
624B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
640B		JE_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#5

656B	BB#5: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#4
672B		CMP64mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%buf.addr]
688B		JE_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#6

704B	BB#6: derived from LLVM BB %lor.lhs.false.6
	    Predecessors according to CFG: BB#5
720B		CMP32mi8 <fi#3>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%len.addr]
736B		JGE_1 <BB#12>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#12 BB#7

752B	BB#7: derived from LLVM BB %if.then.8
	    Predecessors according to CFG: BB#4 BB#5 BB#6
768B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
784B		JE_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#8

800B	BB#8: derived from LLVM BB %if.then.10
	    Predecessors according to CFG: BB#7
816B		%vreg140<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg140
832B		MOV32mi %vreg140, 1, %noreg, 0, %noreg, -2; mem:ST4[%10] GR64:%vreg140
	    Successors according to CFG: BB#9

848B	BB#9: derived from LLVM BB %if.end.11
	    Predecessors according to CFG: BB#7 BB#8
864B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
880B		JE_1 <BB#11>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#11 BB#10

896B	BB#10: derived from LLVM BB %if.then.13
	    Predecessors according to CFG: BB#9
912B		%vreg143<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg143
928B		MOV32mi %vreg143, 1, %noreg, 5096, %noreg, -2; mem:ST4[%lastErr14] GR64:%vreg143
	    Successors according to CFG: BB#11

944B	BB#11: derived from LLVM BB %if.end.15
	    Predecessors according to CFG: BB#9 BB#10
960B		JMP_1 <BB#53>
	    Successors according to CFG: BB#53

976B	BB#12: derived from LLVM BB %if.end.16
	    Predecessors according to CFG: BB#6
992B		%vreg26<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg26
1008B		CMP8mi %vreg26, 1, %noreg, 5012, %noreg, 0, %EFLAGS<imp-def>; mem:LD1[%writing] GR64:%vreg26
1024B		JNE_1 <BB#18>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#18 BB#13

1040B	BB#13: derived from LLVM BB %if.then.17
	    Predecessors according to CFG: BB#12
1056B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
1072B		JE_1 <BB#15>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#15 BB#14

1088B	BB#14: derived from LLVM BB %if.then.19
	    Predecessors according to CFG: BB#13
1104B		%vreg29<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg29
1120B		MOV32mi %vreg29, 1, %noreg, 0, %noreg, -1; mem:ST4[%16] GR64:%vreg29
	    Successors according to CFG: BB#15

1136B	BB#15: derived from LLVM BB %if.end.20
	    Predecessors according to CFG: BB#13 BB#14
1152B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
1168B		JE_1 <BB#17>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#17 BB#16

1184B	BB#16: derived from LLVM BB %if.then.22
	    Predecessors according to CFG: BB#15
1200B		%vreg32<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg32
1216B		MOV32mi %vreg32, 1, %noreg, 5096, %noreg, -1; mem:ST4[%lastErr23] GR64:%vreg32
	    Successors according to CFG: BB#17

1232B	BB#17: derived from LLVM BB %if.end.24
	    Predecessors according to CFG: BB#15 BB#16
1248B		JMP_1 <BB#53>
	    Successors according to CFG: BB#53

1264B	BB#18: derived from LLVM BB %if.end.25
	    Predecessors according to CFG: BB#12
1280B		%vreg38<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg38
1296B		%vreg37<def> = MOV64rm %vreg38, 1, %noreg, 0, %noreg; mem:LD8[%handle] GR64:%vreg37,%vreg38
1312B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1328B		%RDI<def> = COPY %vreg37; GR64:%vreg37
1344B		CALL64pcrel32 <ga:@ferror>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
1360B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1376B		%vreg35<def> = COPY %EAX<kill>; GR32:%vreg35
1392B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1408B		STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#7>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, ...; mem:LD8[FixedStack2] LD8[FixedStack0] LD8[FixedStack7] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4)
1424B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1440B		CMP32ri8 %vreg35, 0, %EFLAGS<imp-def>; GR32:%vreg35
1456B		JE_1 <BB#24>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#24 BB#19

1472B	BB#19: derived from LLVM BB %if.then.27
	    Predecessors according to CFG: BB#18
1488B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
1504B		JE_1 <BB#21>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#21 BB#20

1520B	BB#20: derived from LLVM BB %if.then.29
	    Predecessors according to CFG: BB#19
1536B		%vreg134<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg134
1552B		MOV32mi %vreg134, 1, %noreg, 0, %noreg, -6; mem:ST4[%22] GR64:%vreg134
	    Successors according to CFG: BB#21

1568B	BB#21: derived from LLVM BB %if.end.30
	    Predecessors according to CFG: BB#19 BB#20
1584B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
1600B		JE_1 <BB#23>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#23 BB#22

1616B	BB#22: derived from LLVM BB %if.then.32
	    Predecessors according to CFG: BB#21
1632B		%vreg137<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg137
1648B		MOV32mi %vreg137, 1, %noreg, 5096, %noreg, -6; mem:ST4[%lastErr33] GR64:%vreg137
	    Successors according to CFG: BB#23

1664B	BB#23: derived from LLVM BB %if.end.34
	    Predecessors according to CFG: BB#21 BB#22
1680B		JMP_1 <BB#53>
	    Successors according to CFG: BB#53

1696B	BB#24: derived from LLVM BB %if.end.35
	    Predecessors according to CFG: BB#18
1712B		CMP32mi8 <fi#3>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%len.addr]
1728B		JNE_1 <BB#30>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#30 BB#25

1744B	BB#25: derived from LLVM BB %if.then.37
	    Predecessors according to CFG: BB#24
1760B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
1776B		JE_1 <BB#27>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#27 BB#26

1792B	BB#26: derived from LLVM BB %if.then.39
	    Predecessors according to CFG: BB#25
1808B		%vreg128<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg128
1824B		MOV32mi %vreg128, 1, %noreg, 0, %noreg, 0; mem:ST4[%27] GR64:%vreg128
	    Successors according to CFG: BB#27

1840B	BB#27: derived from LLVM BB %if.end.40
	    Predecessors according to CFG: BB#25 BB#26
1856B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
1872B		JE_1 <BB#29>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#29 BB#28

1888B	BB#28: derived from LLVM BB %if.then.42
	    Predecessors according to CFG: BB#27
1904B		%vreg131<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg131
1920B		MOV32mi %vreg131, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr43] GR64:%vreg131
	    Successors according to CFG: BB#29

1936B	BB#29: derived from LLVM BB %if.end.44
	    Predecessors according to CFG: BB#27 BB#28
1952B		JMP_1 <BB#53>
	    Successors according to CFG: BB#53

1968B	BB#30: derived from LLVM BB %if.end.45
	    Predecessors according to CFG: BB#24
1984B		%vreg47<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%len.addr] GR32:%vreg47
2000B		%vreg46<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg46
2016B		MOV32mr %vreg46, 1, %noreg, 5024, %noreg, %vreg47; mem:ST4[%avail_in] GR64:%vreg46 GR32:%vreg47
2032B		%vreg43<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%buf.addr] GR64:%vreg43
2048B		%vreg42<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg42
2064B		MOV64mr %vreg42, 1, %noreg, 5016, %noreg, %vreg43; mem:ST8[%next_in] GR64:%vreg42,%vreg43
	    Successors according to CFG: BB#31

2080B	BB#31: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#30 BB#52
2096B		%vreg51<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg51
2112B		%vreg64<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg64
2128B		MOV32mi %vreg64, 1, %noreg, 5048, %noreg, 5000; mem:ST4[%avail_out] GR64:%vreg64
2144B		%vreg62<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg62
2160B		%vreg61<def> = COPY %vreg62; GR64:%vreg61,%vreg62
2176B		%vreg61<def,tied1> = ADD64ri8 %vreg61<tied0>, 8, %EFLAGS<imp-def,dead>; GR64:%vreg61
2192B		%vreg58<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg58
2208B		MOV64mr %vreg58, 1, %noreg, 5040, %noreg, %vreg61; mem:ST8[%next_out] GR64:%vreg58,%vreg61
2224B		%vreg55<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg55
2240B		%vreg54<def> = COPY %vreg55; GR64:%vreg54,%vreg55
2256B		%vreg54<def,tied1> = ADD64ri32 %vreg54<tied0>, 5016, %EFLAGS<imp-def,dead>; GR64:%vreg54
2272B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2288B		%RDI<def> = COPY %vreg54; GR64:%vreg54
2304B		%ESI<def> = COPY %vreg51; GR32:%vreg51
2320B		CALL64pcrel32 <ga:@BZ2_bzCompress>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %EAX<imp-def>
2336B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2352B		%vreg52<def> = COPY %EAX<kill>; GR32:%vreg52
2368B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2384B		STACKMAP 2, 0, 0, <fi#0>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, ...; mem:LD8[FixedStack0] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4)
2400B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2416B		MOV32mr <fi#6>, 1, %noreg, 0, %noreg, %vreg52; mem:ST4[%ret] GR32:%vreg52
2432B		CMP32mi8 <fi#6>, 1, %noreg, 0, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%ret]
2448B		JE_1 <BB#37>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#37 BB#32

2464B	BB#32: derived from LLVM BB %if.then.53
	    Predecessors according to CFG: BB#31
2480B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
2496B		JE_1 <BB#34>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#34 BB#33

2512B	BB#33: derived from LLVM BB %if.then.55
	    Predecessors according to CFG: BB#32
2528B		%vreg120<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%ret] GR32:%vreg120
2544B		%vreg119<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg119
2560B		MOV32mr %vreg119, 1, %noreg, 0, %noreg, %vreg120; mem:ST4[%41] GR64:%vreg119 GR32:%vreg120
	    Successors according to CFG: BB#34

2576B	BB#34: derived from LLVM BB %if.end.56
	    Predecessors according to CFG: BB#32 BB#33
2592B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
2608B		JE_1 <BB#36>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#36 BB#35

2624B	BB#35: derived from LLVM BB %if.then.58
	    Predecessors according to CFG: BB#34
2640B		%vreg125<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%ret] GR32:%vreg125
2656B		%vreg124<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg124
2672B		MOV32mr %vreg124, 1, %noreg, 5096, %noreg, %vreg125; mem:ST4[%lastErr59] GR64:%vreg124 GR32:%vreg125
	    Successors according to CFG: BB#36

2688B	BB#36: derived from LLVM BB %if.end.60
	    Predecessors according to CFG: BB#34 BB#35
2704B		JMP_1 <BB#53>
	    Successors according to CFG: BB#53

2720B	BB#37: derived from LLVM BB %if.end.61
	    Predecessors according to CFG: BB#31
2736B		%vreg67<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg67
2752B		CMP32mi %vreg67, 1, %noreg, 5048, %noreg, 5000, %EFLAGS<imp-def>; mem:LD4[%avail_out63] GR64:%vreg67
2768B		JAE_1 <BB#46>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#46 BB#38

2784B	BB#38: derived from LLVM BB %if.then.65
	    Predecessors according to CFG: BB#37
2800B		%vreg75<def> = MOV32ri 1; GR32:%vreg75
2816B		%vreg76<def> = SUBREG_TO_REG 0, %vreg75, 4; GR64:%vreg76 GR32:%vreg75
2832B		%vreg90<def> = MOV32ri 5000; GR32:%vreg90
2848B		%vreg94<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg94
2864B		%vreg92<def> = COPY %vreg90; GR32:%vreg92,%vreg90
2880B		%vreg92<def,tied1> = SUB32rm %vreg92<tied0>, %vreg94, 1, %noreg, 5048, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%avail_out67] GR32:%vreg92 GR64:%vreg94
2896B		MOV32mr <fi#4>, 1, %noreg, 0, %noreg, %vreg92; mem:ST4[%n] GR32:%vreg92
2912B		%vreg88<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg88
2928B		%vreg87<def> = COPY %vreg88; GR64:%vreg87,%vreg88
2944B		%vreg87<def,tied1> = ADD64ri8 %vreg87<tied0>, 8, %EFLAGS<imp-def,dead>; GR64:%vreg87
2960B		%vreg84<def> = MOVSX64rm32 <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%n] GR64:%vreg84
2976B		%vreg82<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg82
2992B		%vreg81<def> = MOV64rm %vreg82, 1, %noreg, 0, %noreg; mem:LD8[%handle70] GR64:%vreg81,%vreg82
3008B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3024B		%RDI<def> = COPY %vreg87; GR64:%vreg87
3040B		%RSI<def> = COPY %vreg76; GR64:%vreg76
3056B		%RDX<def> = COPY %vreg84; GR64:%vreg84
3072B		%RCX<def> = COPY %vreg81; GR64:%vreg81
3088B		CALL64pcrel32 <ga:@fwrite>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %RDX<imp-use>, %RCX<imp-use>, %RAX<imp-def>
3104B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3120B		%vreg79<def> = COPY %RAX<kill>; GR64:%vreg79
3136B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3152B		STACKMAP 3, 0, 0, <fi#0>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, ...; mem:LD8[FixedStack0] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4)
3168B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3184B		%vreg73<def> = COPY %vreg79:sub_32bit; GR32:%vreg73 GR64:%vreg79
3200B		MOV32mr <fi#5>, 1, %noreg, 0, %noreg, %vreg73; mem:ST4[%n2] GR32:%vreg73
3216B		%vreg70<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%n] GR32:%vreg70
3232B		CMP32rm %vreg70, <fi#5>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD4[%n2] GR32:%vreg70
3248B		JNE_1 <BB#40>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#40 BB#39

3264B	BB#39: derived from LLVM BB %lor.lhs.false.75
	    Predecessors according to CFG: BB#38
3280B		%vreg100<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg100
3296B		%vreg99<def> = MOV64rm %vreg100, 1, %noreg, 0, %noreg; mem:LD8[%handle76] GR64:%vreg99,%vreg100
3312B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3328B		%RDI<def> = COPY %vreg99; GR64:%vreg99
3344B		CALL64pcrel32 <ga:@ferror>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
3360B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3376B		%vreg97<def> = COPY %EAX<kill>; GR32:%vreg97
3392B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3408B		STACKMAP 4, 0, 0, <fi#0>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, ...; mem:LD8[FixedStack0] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4)
3424B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3440B		CMP32ri8 %vreg97, 0, %EFLAGS<imp-def>; GR32:%vreg97
3456B		JE_1 <BB#45>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#45 BB#40

3472B	BB#40: derived from LLVM BB %if.then.79
	    Predecessors according to CFG: BB#38 BB#39
3488B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
3504B		JE_1 <BB#42>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#42 BB#41

3520B	BB#41: derived from LLVM BB %if.then.82
	    Predecessors according to CFG: BB#40
3536B		%vreg112<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg112
3552B		MOV32mi %vreg112, 1, %noreg, 0, %noreg, -6; mem:ST4[%58] GR64:%vreg112
	    Successors according to CFG: BB#42

3568B	BB#42: derived from LLVM BB %if.end.83
	    Predecessors according to CFG: BB#40 BB#41
3584B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
3600B		JE_1 <BB#44>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#44 BB#43

3616B	BB#43: derived from LLVM BB %if.then.86
	    Predecessors according to CFG: BB#42
3632B		%vreg115<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg115
3648B		MOV32mi %vreg115, 1, %noreg, 5096, %noreg, -6; mem:ST4[%lastErr87] GR64:%vreg115
	    Successors according to CFG: BB#44

3664B	BB#44: derived from LLVM BB %if.end.88
	    Predecessors according to CFG: BB#42 BB#43
3680B		JMP_1 <BB#53>
	    Successors according to CFG: BB#53

3696B	BB#45: derived from LLVM BB %if.end.89
	    Predecessors according to CFG: BB#39
3712B		JMP_1 <BB#46>
	    Successors according to CFG: BB#46

3728B	BB#46: derived from LLVM BB %if.end.90
	    Predecessors according to CFG: BB#37 BB#45
3744B		%vreg103<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg103
3760B		CMP32mi8 %vreg103, 1, %noreg, 5024, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_in92] GR64:%vreg103
3776B		JNE_1 <BB#52>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#52 BB#47

3792B	BB#47: derived from LLVM BB %if.then.95
	    Predecessors according to CFG: BB#46
3808B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
3824B		JE_1 <BB#49>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#49 BB#48

3840B	BB#48: derived from LLVM BB %if.then.98
	    Predecessors according to CFG: BB#47
3856B		%vreg106<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg106
3872B		MOV32mi %vreg106, 1, %noreg, 0, %noreg, 0; mem:ST4[%64] GR64:%vreg106
	    Successors according to CFG: BB#49

3888B	BB#49: derived from LLVM BB %if.end.99
	    Predecessors according to CFG: BB#47 BB#48
3904B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
3920B		JE_1 <BB#51>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#51 BB#50

3936B	BB#50: derived from LLVM BB %if.then.102
	    Predecessors according to CFG: BB#49
3952B		%vreg109<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg109
3968B		MOV32mi %vreg109, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr103] GR64:%vreg109
	    Successors according to CFG: BB#51

3984B	BB#51: derived from LLVM BB %if.end.104
	    Predecessors according to CFG: BB#49 BB#50
4000B		JMP_1 <BB#53>
	    Successors according to CFG: BB#53

4016B	BB#52: derived from LLVM BB %if.end.105
	    Predecessors according to CFG: BB#46
4032B		JMP_1 <BB#31>
	    Successors according to CFG: BB#31

4048B	BB#53: derived from LLVM BB %return
	    Predecessors according to CFG: BB#17 BB#51 BB#44 BB#36 BB#29 BB#23 BB#11
4064B		%vreg144<def> = MOV64ri <ga:@BZ2_bzWrite>; GR64:%vreg144
4080B		%vreg145<def> = COPY %vreg144; GR64:%vreg145,%vreg144
4096B		%vreg146<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg146
4112B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4128B		%RDI<def> = COPY %vreg145; GR64:%vreg145
4144B		%RSI<def> = COPY %vreg146; GR64:%vreg146
4160B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
4176B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4192B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4208B		STACKMAP 5, 0, ...
4224B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4240B		RETQ

# End machine code for function BZ2_bzWrite.

********** SIMPLE REGISTER COALESCING **********
********** Function: BZ2_bzWrite
********** JOINING INTERVALS ***********
while.body:
2288B	%RDI<def> = COPY %vreg54; GR64:%vreg54
	Considering merging %vreg54 with %RDI
	Can only merge into reserved registers.
2304B	%ESI<def> = COPY %vreg51; GR32:%vreg51
	Considering merging %vreg51 with %ESI
	Can only merge into reserved registers.
Remat: %ESI<def> = MOV32r0 %EFLAGS<imp-def,dead>
Shrink: %vreg51 [2096r,2304r:0)  0@2096r
All defs dead: 2096r	%vreg51<def,dead> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg51
Shrunk: %vreg51 [2096r,2096d:0)  0@2096r
Deleting dead def 2096r	%vreg51<def,dead> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg51
2352B	%vreg52<def> = COPY %EAX<kill>; GR32:%vreg52
	Considering merging %vreg52 with %EAX
	Can only merge into reserved registers.
if.end.90:
if.end.61:
if.then.65:
2816B	%vreg76<def> = SUBREG_TO_REG 0, %vreg75, 4; GR64:%vreg76 GR32:%vreg75
	Considering merging to GR64_with_sub_8bit with %vreg75 in %vreg76:sub_32bit
		RHS = %vreg75 [2800r,2816r:0)  0@2800r
		LHS = %vreg76 [2816r,3040r:0)  0@2816r
		merge %vreg76:0@2816r into %vreg75:0@2800r --> @2800r
		erased:	2816r	%vreg76<def> = SUBREG_TO_REG 0, %vreg75, 4; GR64:%vreg76 GR32:%vreg75
		updated: 2800B	%vreg76:sub_32bit<def,read-undef> = MOV32ri 1; GR64_with_sub_8bit:%vreg76
	Success: %vreg75:sub_32bit -> %vreg76
	Result = %vreg76 [2800r,3040r:0)  0@2800r
3024B	%RDI<def> = COPY %vreg87; GR64:%vreg87
	Considering merging %vreg87 with %RDI
	Can only merge into reserved registers.
3040B	%RSI<def> = COPY %vreg76; GR64_with_sub_8bit:%vreg76
	Considering merging %vreg76 with %RSI
	Can only merge into reserved registers.
Remat: %ESI<def,dead> = MOV32ri 1, %RSI<imp-def>
Shrink: %vreg76 [2800r,3040r:0)  0@2800r
All defs dead: 2800r	%vreg76:sub_32bit<def,read-undef,dead> = MOV32ri 1; GR64_with_sub_8bit:%vreg76
Shrunk: %vreg76 [2800r,2800d:0)  0@2800r
Deleting dead def 2800r	%vreg76:sub_32bit<def,read-undef,dead> = MOV32ri 1; GR64_with_sub_8bit:%vreg76
3056B	%RDX<def> = COPY %vreg84; GR64:%vreg84
	Considering merging %vreg84 with %RDX
	Can only merge into reserved registers.
3072B	%RCX<def> = COPY %vreg81; GR64:%vreg81
	Considering merging %vreg81 with %RCX
	Can only merge into reserved registers.
3120B	%vreg79<def> = COPY %RAX<kill>; GR64:%vreg79
	Considering merging %vreg79 with %RAX
	Can only merge into reserved registers.
lor.lhs.false.75:
3328B	%RDI<def> = COPY %vreg99; GR64:%vreg99
	Considering merging %vreg99 with %RDI
	Can only merge into reserved registers.
3376B	%vreg97<def> = COPY %EAX<kill>; GR32:%vreg97
	Considering merging %vreg97 with %EAX
	Can only merge into reserved registers.
if.end.89:
if.end.105:
2160B	%vreg61<def> = COPY %vreg62; GR64:%vreg61,%vreg62
	Considering merging to GR64 with %vreg62 in %vreg61
		RHS = %vreg62 [2144r,2160r:0)  0@2144r
		LHS = %vreg61 [2160r,2176r:0)[2176r,2208r:1)  0@2160r 1@2176r
		merge %vreg61:0@2160r into %vreg62:0@2144r --> @2144r
		erased:	2160r	%vreg61<def> = COPY %vreg62; GR64:%vreg61,%vreg62
		updated: 2144B	%vreg61<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg61
	Success: %vreg62 -> %vreg61
	Result = %vreg61 [2144r,2176r:0)[2176r,2208r:1)  0@2144r 1@2176r
2240B	%vreg54<def> = COPY %vreg55; GR64:%vreg54,%vreg55
	Considering merging to GR64 with %vreg55 in %vreg54
		RHS = %vreg55 [2224r,2240r:0)  0@2224r
		LHS = %vreg54 [2240r,2256r:0)[2256r,2288r:1)  0@2240r 1@2256r
		merge %vreg54:0@2240r into %vreg55:0@2224r --> @2224r
		erased:	2240r	%vreg54<def> = COPY %vreg55; GR64:%vreg54,%vreg55
		updated: 2224B	%vreg54<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg54
	Success: %vreg55 -> %vreg54
	Result = %vreg54 [2224r,2256r:0)[2256r,2288r:1)  0@2224r 1@2256r
2864B	%vreg92<def> = COPY %vreg90; GR32:%vreg92,%vreg90
	Considering merging to GR32 with %vreg90 in %vreg92
		RHS = %vreg90 [2832r,2864r:0)  0@2832r
		LHS = %vreg92 [2864r,2880r:0)[2880r,2896r:1)  0@2864r 1@2880r
		merge %vreg92:0@2864r into %vreg90:0@2832r --> @2832r
		erased:	2864r	%vreg92<def> = COPY %vreg90; GR32:%vreg92,%vreg90
		updated: 2832B	%vreg92<def> = MOV32ri 5000; GR32:%vreg92
	Success: %vreg90 -> %vreg92
	Result = %vreg92 [2832r,2880r:0)[2880r,2896r:1)  0@2832r 1@2880r
2928B	%vreg87<def> = COPY %vreg88; GR64:%vreg87,%vreg88
	Considering merging to GR64 with %vreg88 in %vreg87
		RHS = %vreg88 [2912r,2928r:0)  0@2912r
		LHS = %vreg87 [2928r,2944r:0)[2944r,3024r:1)  0@2928r 1@2944r
		merge %vreg87:0@2928r into %vreg88:0@2912r --> @2912r
		erased:	2928r	%vreg87<def> = COPY %vreg88; GR64:%vreg87,%vreg88
		updated: 2912B	%vreg87<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg87
	Success: %vreg88 -> %vreg87
	Result = %vreg87 [2912r,2944r:0)[2944r,3024r:1)  0@2912r 1@2944r
3184B	%vreg73<def> = COPY %vreg79:sub_32bit; GR32:%vreg73 GR64:%vreg79
	Considering merging to GR64_with_sub_8bit with %vreg73 in %vreg79:sub_32bit
		RHS = %vreg73 [3184r,3200r:0)  0@3184r
		LHS = %vreg79 [3120r,3184r:0)  0@3120r
		merge %vreg73:0@3184r into %vreg79:0@3120r --> @3120r
		erased:	3184r	%vreg73<def> = COPY %vreg79:sub_32bit; GR32:%vreg73 GR64:%vreg79
		updated: 3200B	MOV32mr <fi#5>, 1, %noreg, 0, %noreg, %vreg79:sub_32bit; mem:ST4[%n2] GR64_with_sub_8bit:%vreg79
	Success: %vreg73:sub_32bit -> %vreg79
	Result = %vreg79 [3120r,3200r:0)  0@3120r
return:
4128B	%RDI<def> = COPY %vreg145; GR64:%vreg145
	Considering merging %vreg145 with %RDI
	Can only merge into reserved registers.
4144B	%RSI<def> = COPY %vreg146; GR64:%vreg146
	Considering merging %vreg146 with %RSI
	Can only merge into reserved registers.
if.then.8:
if.end:
if.end.3:
if.end.11:
if.end.20:
if.end.30:
if.end.40:
if.end.56:
if.then.79:
if.end.83:
if.end.99:
lor.lhs.false:
lor.lhs.false.6:
if.end.15:
if.end.16:
if.then.17:
if.end.24:
if.end.25:
1328B	%RDI<def> = COPY %vreg37; GR64:%vreg37
	Considering merging %vreg37 with %RDI
	Can only merge into reserved registers.
1376B	%vreg35<def> = COPY %EAX<kill>; GR32:%vreg35
	Considering merging %vreg35 with %EAX
	Can only merge into reserved registers.
if.then.27:
if.end.34:
if.end.35:
if.then.37:
if.end.44:
if.then.53:
if.end.60:
if.end.88:
if.then.95:
if.end.104:
entry:
16B	%vreg6<def> = COPY %ECX; GR32:%vreg6
	Considering merging %vreg6 with %ECX
	Can only merge into reserved registers.
32B	%vreg4<def> = COPY %RDX; GR64:%vreg4
	Considering merging %vreg4 with %RDX
	Can only merge into reserved registers.
48B	%vreg2<def> = COPY %RSI; GR64:%vreg2
	Considering merging %vreg2 with %RSI
	Can only merge into reserved registers.
64B	%vreg0<def> = COPY %RDI; GR64:%vreg0
	Considering merging %vreg0 with %RDI
	Can only merge into reserved registers.
208B	%RDI<def> = COPY %vreg14; GR64:%vreg14
	Considering merging %vreg14 with %RDI
	Can only merge into reserved registers.
224B	%RSI<def> = COPY %vreg15; GR64:%vreg15
	Considering merging %vreg15 with %RSI
	Can only merge into reserved registers.
if.then:
if.then.2:
if.then.10:
if.then.13:
if.then.19:
if.then.22:
if.then.29:
if.then.32:
if.then.39:
if.then.42:
if.end.45:
if.then.55:
if.then.58:
if.then.82:
if.then.86:
if.then.98:
if.then.102:
4080B	%vreg145<def> = COPY %vreg144; GR64:%vreg145,%vreg144
	Considering merging to GR64 with %vreg144 in %vreg145
		RHS = %vreg144 [4064r,4080r:0)  0@4064r
		LHS = %vreg145 [4080r,4128r:0)  0@4080r
		merge %vreg145:0@4080r into %vreg144:0@4064r --> @4064r
		erased:	4080r	%vreg145<def> = COPY %vreg144; GR64:%vreg145,%vreg144
		updated: 4064B	%vreg145<def> = MOV64ri <ga:@BZ2_bzWrite>; GR64:%vreg145
	Success: %vreg144 -> %vreg145
	Result = %vreg145 [4064r,4128r:0)  0@4064r
80B	%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
	Considering merging to GR64 with %vreg0 in %vreg1
		RHS = %vreg0 [64r,80r:0)  0@64r
		LHS = %vreg1 [80r,320r:0)  0@80r
		merge %vreg1:0@80r into %vreg0:0@64r --> @64r
		erased:	80r	%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
		updated: 64B	%vreg1<def> = COPY %RDI; GR64:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [64r,320r:0)  0@64r
96B	%vreg3<def> = COPY %vreg2; GR64:%vreg3,%vreg2
	Considering merging to GR64 with %vreg2 in %vreg3
		RHS = %vreg2 [48r,96r:0)  0@48r
		LHS = %vreg3 [96r,336r:0)  0@96r
		merge %vreg3:0@96r into %vreg2:0@48r --> @48r
		erased:	96r	%vreg3<def> = COPY %vreg2; GR64:%vreg3,%vreg2
		updated: 48B	%vreg3<def> = COPY %RSI; GR64:%vreg3
	Success: %vreg2 -> %vreg3
	Result = %vreg3 [48r,336r:0)  0@48r
112B	%vreg5<def> = COPY %vreg4; GR64:%vreg5,%vreg4
	Considering merging to GR64 with %vreg4 in %vreg5
		RHS = %vreg4 [32r,112r:0)  0@32r
		LHS = %vreg5 [112r,352r:0)  0@112r
		merge %vreg5:0@112r into %vreg4:0@32r --> @32r
		erased:	112r	%vreg5<def> = COPY %vreg4; GR64:%vreg5,%vreg4
		updated: 32B	%vreg5<def> = COPY %RDX; GR64:%vreg5
	Success: %vreg4 -> %vreg5
	Result = %vreg5 [32r,352r:0)  0@32r
128B	%vreg7<def> = COPY %vreg6; GR32:%vreg7,%vreg6
	Considering merging to GR32 with %vreg6 in %vreg7
		RHS = %vreg6 [16r,128r:0)  0@16r
		LHS = %vreg7 [128r,368r:0)  0@128r
		merge %vreg7:0@128r into %vreg6:0@16r --> @16r
		erased:	128r	%vreg7<def> = COPY %vreg6; GR32:%vreg7,%vreg6
		updated: 16B	%vreg7<def> = COPY %ECX; GR32:%vreg7
	Success: %vreg6 -> %vreg7
	Result = %vreg7 [16r,368r:0)  0@16r
160B	%vreg14<def> = COPY %vreg13; GR64:%vreg14,%vreg13
	Considering merging to GR64 with %vreg13 in %vreg14
		RHS = %vreg13 [144r,160r:0)  0@144r
		LHS = %vreg14 [160r,208r:0)  0@160r
		merge %vreg14:0@160r into %vreg13:0@144r --> @144r
		erased:	160r	%vreg14<def> = COPY %vreg13; GR64:%vreg14,%vreg13
		updated: 144B	%vreg14<def> = MOV64ri <ga:@BZ2_bzWrite>; GR64:%vreg14
	Success: %vreg13 -> %vreg14
	Result = %vreg14 [144r,208r:0)  0@144r
400B	%vreg11<def> = COPY %vreg12; GR64:%vreg11,%vreg12
	Considering merging to GR64 with %vreg12 in %vreg11
		RHS = %vreg12 [384r,400r:0)  0@384r
		LHS = %vreg11 [400r,416r:0)  0@400r
		merge %vreg11:0@400r into %vreg12:0@384r --> @384r
		erased:	400r	%vreg11<def> = COPY %vreg12; GR64:%vreg11,%vreg12
		updated: 384B	%vreg11<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr] GR64:%vreg11
	Success: %vreg12 -> %vreg11
	Result = %vreg11 [384r,416r:0)  0@384r
4128B	%RDI<def> = COPY %vreg145; GR64:%vreg145
	Considering merging %vreg145 with %RDI
	Can only merge into reserved registers.
208B	%RDI<def> = COPY %vreg14; GR64:%vreg14
	Considering merging %vreg14 with %RDI
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
CH [0B,16r:0)[3072r,3088r:1)  0@0B-phi 1@3072r
CL [0B,16r:0)[3072r,3088r:1)  0@0B-phi 1@3072r
DH [0B,32r:0)[3056r,3088r:1)  0@0B-phi 1@3056r
DIL [0B,64r:0)[208r,240r:6)[1328r,1344r:5)[2288r,2320r:4)[3024r,3088r:3)[3328r,3344r:2)[4128r,4160r:1)  0@0B-phi 1@4128r 2@3328r 3@3024r 4@2288r 5@1328r 6@208r
DL [0B,32r:0)[3056r,3088r:1)  0@0B-phi 1@3056r
SIL [0B,48r:0)[224r,240r:4)[2304r,2320r:1)[3040r,3088r:3)[4144r,4160r:2)  0@0B-phi 1@2304r 2@4144r 3@3040r 4@224r
%vreg1 [64r,320r:0)  0@64r
%vreg3 [48r,336r:0)  0@48r
%vreg5 [32r,352r:0)  0@32r
%vreg7 [16r,368r:0)  0@16r
%vreg11 [384r,416r:0)  0@384r
%vreg14 [144r,208r:0)  0@144r
%vreg15 [176r,224r:0)  0@176r
%vreg17 [480r,496r:0)  0@480r
%vreg20 [576r,592r:0)  0@576r
%vreg26 [992r,1008r:0)  0@992r
%vreg29 [1104r,1120r:0)  0@1104r
%vreg32 [1200r,1216r:0)  0@1200r
%vreg35 [1376r,1440r:0)  0@1376r
%vreg37 [1296r,1328r:0)  0@1296r
%vreg38 [1280r,1296r:0)  0@1280r
%vreg42 [2048r,2064r:0)  0@2048r
%vreg43 [2032r,2064r:0)  0@2032r
%vreg46 [2000r,2016r:0)  0@2000r
%vreg47 [1984r,2016r:0)  0@1984r
%vreg52 [2352r,2416r:0)  0@2352r
%vreg54 [2224r,2256r:0)[2256r,2288r:1)  0@2224r 1@2256r
%vreg58 [2192r,2208r:0)  0@2192r
%vreg61 [2144r,2176r:0)[2176r,2208r:1)  0@2144r 1@2176r
%vreg64 [2112r,2128r:0)  0@2112r
%vreg67 [2736r,2752r:0)  0@2736r
%vreg70 [3216r,3232r:0)  0@3216r
%vreg79 [3120r,3200r:0)  0@3120r
%vreg81 [2992r,3072r:0)  0@2992r
%vreg82 [2976r,2992r:0)  0@2976r
%vreg84 [2960r,3056r:0)  0@2960r
%vreg87 [2912r,2944r:0)[2944r,3024r:1)  0@2912r 1@2944r
%vreg92 [2832r,2880r:0)[2880r,2896r:1)  0@2832r 1@2880r
%vreg94 [2848r,2880r:0)  0@2848r
%vreg97 [3376r,3440r:0)  0@3376r
%vreg99 [3296r,3328r:0)  0@3296r
%vreg100 [3280r,3296r:0)  0@3280r
%vreg103 [3744r,3760r:0)  0@3744r
%vreg106 [3856r,3872r:0)  0@3856r
%vreg109 [3952r,3968r:0)  0@3952r
%vreg112 [3536r,3552r:0)  0@3536r
%vreg115 [3632r,3648r:0)  0@3632r
%vreg119 [2544r,2560r:0)  0@2544r
%vreg120 [2528r,2560r:0)  0@2528r
%vreg124 [2656r,2672r:0)  0@2656r
%vreg125 [2640r,2672r:0)  0@2640r
%vreg128 [1808r,1824r:0)  0@1808r
%vreg131 [1904r,1920r:0)  0@1904r
%vreg134 [1536r,1552r:0)  0@1536r
%vreg137 [1632r,1648r:0)  0@1632r
%vreg140 [816r,832r:0)  0@816r
%vreg143 [912r,928r:0)  0@912r
%vreg145 [4064r,4128r:0)  0@4064r
%vreg146 [4096r,4144r:0)  0@4096r
RegMasks: 240r 1344r 2320r 3088r 3344r 4160r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzWrite: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=8, align=8, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=8, align=8, at location [SP+8]
  fi#3: size=4, align=4, at location [SP+8]
  fi#4: size=4, align=4, at location [SP+8]
  fi#5: size=4, align=4, at location [SP+8]
  fi#6: size=4, align=4, at location [SP+8]
  fi#7: size=8, align=8, at location [SP+8]
Function Live Ins: %RDI in %vreg0, %RSI in %vreg2, %RDX in %vreg4, %ECX in %vreg6

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI %RSI %RDX %ECX
16B		%vreg7<def> = COPY %ECX; GR32:%vreg7
32B		%vreg5<def> = COPY %RDX; GR64:%vreg5
48B		%vreg3<def> = COPY %RSI; GR64:%vreg3
64B		%vreg1<def> = COPY %RDI; GR64:%vreg1
144B		%vreg14<def> = MOV64ri <ga:@BZ2_bzWrite>; GR64:%vreg14
176B		%vreg15<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg15
192B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
208B		%RDI<def> = COPY %vreg14; GR64:%vreg14
224B		%RSI<def> = COPY %vreg15; GR64:%vreg15
240B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
256B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
272B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
288B		STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg5, 0, <fi#2>, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#7>, 0, %vreg7, 0, <fi#3>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack0] LD8[FixedStack7] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) GR64:%vreg3,%vreg5,%vreg1 GR32:%vreg7
304B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
320B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%bzerror.addr] GR64:%vreg1
336B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg3; mem:ST8[%b.addr] GR64:%vreg3
352B		MOV64mr <fi#2>, 1, %noreg, 0, %noreg, %vreg5; mem:ST8[%buf.addr] GR64:%vreg5
368B		MOV32mr <fi#3>, 1, %noreg, 0, %noreg, %vreg7; mem:ST4[%len.addr] GR32:%vreg7
384B		%vreg11<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr] GR64:%vreg11
416B		MOV64mr <fi#7>, 1, %noreg, 0, %noreg, %vreg11; mem:ST8[%bzf] GR64:%vreg11
432B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
448B		JE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

464B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
480B		%vreg17<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg17
496B		MOV32mi %vreg17, 1, %noreg, 0, %noreg, 0; mem:ST4[%3] GR64:%vreg17
	    Successors according to CFG: BB#2

512B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#1
528B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
544B		JE_1 <BB#4>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#4 BB#3

560B	BB#3: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#2
576B		%vreg20<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg20
592B		MOV32mi %vreg20, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr] GR64:%vreg20
	    Successors according to CFG: BB#4

608B	BB#4: derived from LLVM BB %if.end.3
	    Predecessors according to CFG: BB#2 BB#3
624B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
640B		JE_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#5

656B	BB#5: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#4
672B		CMP64mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%buf.addr]
688B		JE_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#6

704B	BB#6: derived from LLVM BB %lor.lhs.false.6
	    Predecessors according to CFG: BB#5
720B		CMP32mi8 <fi#3>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%len.addr]
736B		JGE_1 <BB#12>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#12 BB#7

752B	BB#7: derived from LLVM BB %if.then.8
	    Predecessors according to CFG: BB#4 BB#5 BB#6
768B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
784B		JE_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#8

800B	BB#8: derived from LLVM BB %if.then.10
	    Predecessors according to CFG: BB#7
816B		%vreg140<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg140
832B		MOV32mi %vreg140, 1, %noreg, 0, %noreg, -2; mem:ST4[%10] GR64:%vreg140
	    Successors according to CFG: BB#9

848B	BB#9: derived from LLVM BB %if.end.11
	    Predecessors according to CFG: BB#7 BB#8
864B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
880B		JE_1 <BB#11>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#11 BB#10

896B	BB#10: derived from LLVM BB %if.then.13
	    Predecessors according to CFG: BB#9
912B		%vreg143<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg143
928B		MOV32mi %vreg143, 1, %noreg, 5096, %noreg, -2; mem:ST4[%lastErr14] GR64:%vreg143
	    Successors according to CFG: BB#11

944B	BB#11: derived from LLVM BB %if.end.15
	    Predecessors according to CFG: BB#9 BB#10
960B		JMP_1 <BB#53>
	    Successors according to CFG: BB#53

976B	BB#12: derived from LLVM BB %if.end.16
	    Predecessors according to CFG: BB#6
992B		%vreg26<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg26
1008B		CMP8mi %vreg26, 1, %noreg, 5012, %noreg, 0, %EFLAGS<imp-def>; mem:LD1[%writing] GR64:%vreg26
1024B		JNE_1 <BB#18>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#18 BB#13

1040B	BB#13: derived from LLVM BB %if.then.17
	    Predecessors according to CFG: BB#12
1056B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
1072B		JE_1 <BB#15>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#15 BB#14

1088B	BB#14: derived from LLVM BB %if.then.19
	    Predecessors according to CFG: BB#13
1104B		%vreg29<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg29
1120B		MOV32mi %vreg29, 1, %noreg, 0, %noreg, -1; mem:ST4[%16] GR64:%vreg29
	    Successors according to CFG: BB#15

1136B	BB#15: derived from LLVM BB %if.end.20
	    Predecessors according to CFG: BB#13 BB#14
1152B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
1168B		JE_1 <BB#17>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#17 BB#16

1184B	BB#16: derived from LLVM BB %if.then.22
	    Predecessors according to CFG: BB#15
1200B		%vreg32<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg32
1216B		MOV32mi %vreg32, 1, %noreg, 5096, %noreg, -1; mem:ST4[%lastErr23] GR64:%vreg32
	    Successors according to CFG: BB#17

1232B	BB#17: derived from LLVM BB %if.end.24
	    Predecessors according to CFG: BB#15 BB#16
1248B		JMP_1 <BB#53>
	    Successors according to CFG: BB#53

1264B	BB#18: derived from LLVM BB %if.end.25
	    Predecessors according to CFG: BB#12
1280B		%vreg38<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg38
1296B		%vreg37<def> = MOV64rm %vreg38, 1, %noreg, 0, %noreg; mem:LD8[%handle] GR64:%vreg37,%vreg38
1312B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1328B		%RDI<def> = COPY %vreg37; GR64:%vreg37
1344B		CALL64pcrel32 <ga:@ferror>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
1360B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1376B		%vreg35<def> = COPY %EAX<kill>; GR32:%vreg35
1392B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1408B		STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#7>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, ...; mem:LD8[FixedStack2] LD8[FixedStack0] LD8[FixedStack7] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4)
1424B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1440B		CMP32ri8 %vreg35, 0, %EFLAGS<imp-def>; GR32:%vreg35
1456B		JE_1 <BB#24>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#24 BB#19

1472B	BB#19: derived from LLVM BB %if.then.27
	    Predecessors according to CFG: BB#18
1488B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
1504B		JE_1 <BB#21>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#21 BB#20

1520B	BB#20: derived from LLVM BB %if.then.29
	    Predecessors according to CFG: BB#19
1536B		%vreg134<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg134
1552B		MOV32mi %vreg134, 1, %noreg, 0, %noreg, -6; mem:ST4[%22] GR64:%vreg134
	    Successors according to CFG: BB#21

1568B	BB#21: derived from LLVM BB %if.end.30
	    Predecessors according to CFG: BB#19 BB#20
1584B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
1600B		JE_1 <BB#23>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#23 BB#22

1616B	BB#22: derived from LLVM BB %if.then.32
	    Predecessors according to CFG: BB#21
1632B		%vreg137<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg137
1648B		MOV32mi %vreg137, 1, %noreg, 5096, %noreg, -6; mem:ST4[%lastErr33] GR64:%vreg137
	    Successors according to CFG: BB#23

1664B	BB#23: derived from LLVM BB %if.end.34
	    Predecessors according to CFG: BB#21 BB#22
1680B		JMP_1 <BB#53>
	    Successors according to CFG: BB#53

1696B	BB#24: derived from LLVM BB %if.end.35
	    Predecessors according to CFG: BB#18
1712B		CMP32mi8 <fi#3>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%len.addr]
1728B		JNE_1 <BB#30>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#30 BB#25

1744B	BB#25: derived from LLVM BB %if.then.37
	    Predecessors according to CFG: BB#24
1760B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
1776B		JE_1 <BB#27>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#27 BB#26

1792B	BB#26: derived from LLVM BB %if.then.39
	    Predecessors according to CFG: BB#25
1808B		%vreg128<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg128
1824B		MOV32mi %vreg128, 1, %noreg, 0, %noreg, 0; mem:ST4[%27] GR64:%vreg128
	    Successors according to CFG: BB#27

1840B	BB#27: derived from LLVM BB %if.end.40
	    Predecessors according to CFG: BB#25 BB#26
1856B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
1872B		JE_1 <BB#29>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#29 BB#28

1888B	BB#28: derived from LLVM BB %if.then.42
	    Predecessors according to CFG: BB#27
1904B		%vreg131<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg131
1920B		MOV32mi %vreg131, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr43] GR64:%vreg131
	    Successors according to CFG: BB#29

1936B	BB#29: derived from LLVM BB %if.end.44
	    Predecessors according to CFG: BB#27 BB#28
1952B		JMP_1 <BB#53>
	    Successors according to CFG: BB#53

1968B	BB#30: derived from LLVM BB %if.end.45
	    Predecessors according to CFG: BB#24
1984B		%vreg47<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%len.addr] GR32:%vreg47
2000B		%vreg46<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg46
2016B		MOV32mr %vreg46, 1, %noreg, 5024, %noreg, %vreg47; mem:ST4[%avail_in] GR64:%vreg46 GR32:%vreg47
2032B		%vreg43<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%buf.addr] GR64:%vreg43
2048B		%vreg42<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg42
2064B		MOV64mr %vreg42, 1, %noreg, 5016, %noreg, %vreg43; mem:ST8[%next_in] GR64:%vreg42,%vreg43
	    Successors according to CFG: BB#31

2080B	BB#31: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#30 BB#52
2112B		%vreg64<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg64
2128B		MOV32mi %vreg64, 1, %noreg, 5048, %noreg, 5000; mem:ST4[%avail_out] GR64:%vreg64
2144B		%vreg61<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg61
2176B		%vreg61<def,tied1> = ADD64ri8 %vreg61<tied0>, 8, %EFLAGS<imp-def,dead>; GR64:%vreg61
2192B		%vreg58<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg58
2208B		MOV64mr %vreg58, 1, %noreg, 5040, %noreg, %vreg61; mem:ST8[%next_out] GR64:%vreg58,%vreg61
2224B		%vreg54<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg54
2256B		%vreg54<def,tied1> = ADD64ri32 %vreg54<tied0>, 5016, %EFLAGS<imp-def,dead>; GR64:%vreg54
2272B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2288B		%RDI<def> = COPY %vreg54; GR64:%vreg54
2304B		%ESI<def> = MOV32r0 %EFLAGS<imp-def,dead>
2320B		CALL64pcrel32 <ga:@BZ2_bzCompress>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %EAX<imp-def>
2336B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2352B		%vreg52<def> = COPY %EAX<kill>; GR32:%vreg52
2368B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2384B		STACKMAP 2, 0, 0, <fi#0>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, ...; mem:LD8[FixedStack0] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4)
2400B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2416B		MOV32mr <fi#6>, 1, %noreg, 0, %noreg, %vreg52; mem:ST4[%ret] GR32:%vreg52
2432B		CMP32mi8 <fi#6>, 1, %noreg, 0, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%ret]
2448B		JE_1 <BB#37>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#37 BB#32

2464B	BB#32: derived from LLVM BB %if.then.53
	    Predecessors according to CFG: BB#31
2480B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
2496B		JE_1 <BB#34>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#34 BB#33

2512B	BB#33: derived from LLVM BB %if.then.55
	    Predecessors according to CFG: BB#32
2528B		%vreg120<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%ret] GR32:%vreg120
2544B		%vreg119<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg119
2560B		MOV32mr %vreg119, 1, %noreg, 0, %noreg, %vreg120; mem:ST4[%41] GR64:%vreg119 GR32:%vreg120
	    Successors according to CFG: BB#34

2576B	BB#34: derived from LLVM BB %if.end.56
	    Predecessors according to CFG: BB#32 BB#33
2592B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
2608B		JE_1 <BB#36>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#36 BB#35

2624B	BB#35: derived from LLVM BB %if.then.58
	    Predecessors according to CFG: BB#34
2640B		%vreg125<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%ret] GR32:%vreg125
2656B		%vreg124<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg124
2672B		MOV32mr %vreg124, 1, %noreg, 5096, %noreg, %vreg125; mem:ST4[%lastErr59] GR64:%vreg124 GR32:%vreg125
	    Successors according to CFG: BB#36

2688B	BB#36: derived from LLVM BB %if.end.60
	    Predecessors according to CFG: BB#34 BB#35
2704B		JMP_1 <BB#53>
	    Successors according to CFG: BB#53

2720B	BB#37: derived from LLVM BB %if.end.61
	    Predecessors according to CFG: BB#31
2736B		%vreg67<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg67
2752B		CMP32mi %vreg67, 1, %noreg, 5048, %noreg, 5000, %EFLAGS<imp-def>; mem:LD4[%avail_out63] GR64:%vreg67
2768B		JAE_1 <BB#46>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#46 BB#38

2784B	BB#38: derived from LLVM BB %if.then.65
	    Predecessors according to CFG: BB#37
2832B		%vreg92<def> = MOV32ri 5000; GR32:%vreg92
2848B		%vreg94<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg94
2880B		%vreg92<def,tied1> = SUB32rm %vreg92<tied0>, %vreg94, 1, %noreg, 5048, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%avail_out67] GR32:%vreg92 GR64:%vreg94
2896B		MOV32mr <fi#4>, 1, %noreg, 0, %noreg, %vreg92; mem:ST4[%n] GR32:%vreg92
2912B		%vreg87<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg87
2944B		%vreg87<def,tied1> = ADD64ri8 %vreg87<tied0>, 8, %EFLAGS<imp-def,dead>; GR64:%vreg87
2960B		%vreg84<def> = MOVSX64rm32 <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%n] GR64:%vreg84
2976B		%vreg82<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg82
2992B		%vreg81<def> = MOV64rm %vreg82, 1, %noreg, 0, %noreg; mem:LD8[%handle70] GR64:%vreg81,%vreg82
3008B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3024B		%RDI<def> = COPY %vreg87; GR64:%vreg87
3040B		%ESI<def,dead> = MOV32ri 1, %RSI<imp-def>
3056B		%RDX<def> = COPY %vreg84; GR64:%vreg84
3072B		%RCX<def> = COPY %vreg81; GR64:%vreg81
3088B		CALL64pcrel32 <ga:@fwrite>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %RDX<imp-use>, %RCX<imp-use>, %RAX<imp-def>
3104B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3120B		%vreg79<def> = COPY %RAX<kill>; GR64_with_sub_8bit:%vreg79
3136B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3152B		STACKMAP 3, 0, 0, <fi#0>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, ...; mem:LD8[FixedStack0] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4)
3168B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3200B		MOV32mr <fi#5>, 1, %noreg, 0, %noreg, %vreg79:sub_32bit; mem:ST4[%n2] GR64_with_sub_8bit:%vreg79
3216B		%vreg70<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%n] GR32:%vreg70
3232B		CMP32rm %vreg70, <fi#5>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD4[%n2] GR32:%vreg70
3248B		JNE_1 <BB#40>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#40 BB#39

3264B	BB#39: derived from LLVM BB %lor.lhs.false.75
	    Predecessors according to CFG: BB#38
3280B		%vreg100<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg100
3296B		%vreg99<def> = MOV64rm %vreg100, 1, %noreg, 0, %noreg; mem:LD8[%handle76] GR64:%vreg99,%vreg100
3312B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3328B		%RDI<def> = COPY %vreg99; GR64:%vreg99
3344B		CALL64pcrel32 <ga:@ferror>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
3360B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3376B		%vreg97<def> = COPY %EAX<kill>; GR32:%vreg97
3392B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3408B		STACKMAP 4, 0, 0, <fi#0>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, ...; mem:LD8[FixedStack0] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4)
3424B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3440B		CMP32ri8 %vreg97, 0, %EFLAGS<imp-def>; GR32:%vreg97
3456B		JE_1 <BB#45>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#45 BB#40

3472B	BB#40: derived from LLVM BB %if.then.79
	    Predecessors according to CFG: BB#38 BB#39
3488B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
3504B		JE_1 <BB#42>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#42 BB#41

3520B	BB#41: derived from LLVM BB %if.then.82
	    Predecessors according to CFG: BB#40
3536B		%vreg112<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg112
3552B		MOV32mi %vreg112, 1, %noreg, 0, %noreg, -6; mem:ST4[%58] GR64:%vreg112
	    Successors according to CFG: BB#42

3568B	BB#42: derived from LLVM BB %if.end.83
	    Predecessors according to CFG: BB#40 BB#41
3584B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
3600B		JE_1 <BB#44>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#44 BB#43

3616B	BB#43: derived from LLVM BB %if.then.86
	    Predecessors according to CFG: BB#42
3632B		%vreg115<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg115
3648B		MOV32mi %vreg115, 1, %noreg, 5096, %noreg, -6; mem:ST4[%lastErr87] GR64:%vreg115
	    Successors according to CFG: BB#44

3664B	BB#44: derived from LLVM BB %if.end.88
	    Predecessors according to CFG: BB#42 BB#43
3680B		JMP_1 <BB#53>
	    Successors according to CFG: BB#53

3696B	BB#45: derived from LLVM BB %if.end.89
	    Predecessors according to CFG: BB#39
3712B		JMP_1 <BB#46>
	    Successors according to CFG: BB#46

3728B	BB#46: derived from LLVM BB %if.end.90
	    Predecessors according to CFG: BB#37 BB#45
3744B		%vreg103<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg103
3760B		CMP32mi8 %vreg103, 1, %noreg, 5024, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_in92] GR64:%vreg103
3776B		JNE_1 <BB#52>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#52 BB#47

3792B	BB#47: derived from LLVM BB %if.then.95
	    Predecessors according to CFG: BB#46
3808B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
3824B		JE_1 <BB#49>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#49 BB#48

3840B	BB#48: derived from LLVM BB %if.then.98
	    Predecessors according to CFG: BB#47
3856B		%vreg106<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg106
3872B		MOV32mi %vreg106, 1, %noreg, 0, %noreg, 0; mem:ST4[%64] GR64:%vreg106
	    Successors according to CFG: BB#49

3888B	BB#49: derived from LLVM BB %if.end.99
	    Predecessors according to CFG: BB#47 BB#48
3904B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
3920B		JE_1 <BB#51>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#51 BB#50

3936B	BB#50: derived from LLVM BB %if.then.102
	    Predecessors according to CFG: BB#49
3952B		%vreg109<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg109
3968B		MOV32mi %vreg109, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr103] GR64:%vreg109
	    Successors according to CFG: BB#51

3984B	BB#51: derived from LLVM BB %if.end.104
	    Predecessors according to CFG: BB#49 BB#50
4000B		JMP_1 <BB#53>
	    Successors according to CFG: BB#53

4016B	BB#52: derived from LLVM BB %if.end.105
	    Predecessors according to CFG: BB#46
4032B		JMP_1 <BB#31>
	    Successors according to CFG: BB#31

4048B	BB#53: derived from LLVM BB %return
	    Predecessors according to CFG: BB#17 BB#51 BB#44 BB#36 BB#29 BB#23 BB#11
4064B		%vreg145<def> = MOV64ri <ga:@BZ2_bzWrite>; GR64:%vreg145
4096B		%vreg146<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg146
4112B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4128B		%RDI<def> = COPY %vreg145; GR64:%vreg145
4144B		%RSI<def> = COPY %vreg146; GR64:%vreg146
4160B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
4176B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4192B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4208B		STACKMAP 5, 0, ...
4224B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4240B		RETQ

# End machine code for function BZ2_bzWrite.

handleMove 2288B -> 2312B: %RDI<def> = COPY %vreg54; GR64:%vreg54
     DIL:	[0B,64r:0)[208r,240r:6)[1328r,1344r:5)[2288r,2320r:4)[3024r,3088r:3)[3328r,3344r:2)[4128r,4160r:1)  0@0B-phi 1@4128r 2@3328r 3@3024r 4@2288r 5@1328r 6@208r
        -->	[0B,64r:0)[208r,240r:6)[1328r,1344r:5)[2312r,2320r:4)[3024r,3088r:3)[3328r,3344r:2)[4128r,4160r:1)  0@0B-phi 1@4128r 2@3328r 3@3024r 4@2312r 5@1328r 6@208r
     %vreg54:	[2224r,2256r:0)[2256r,2288r:1)  0@2224r 1@2256r
        -->	[2224r,2256r:0)[2256r,2312r:1)  0@2224r 1@2256r
AllocationOrder(SEGMENT_REG) = [ ]
handleMove 3024B -> 3048B: %RDI<def> = COPY %vreg87; GR64:%vreg87
     DIL:	[0B,64r:0)[208r,240r:6)[1328r,1344r:5)[2312r,2320r:4)[3024r,3088r:3)[3328r,3344r:2)[4128r,4160r:1)  0@0B-phi 1@4128r 2@3328r 3@3024r 4@2312r 5@1328r 6@208r
        -->	[0B,64r:0)[208r,240r:6)[1328r,1344r:5)[2312r,2320r:4)[3048r,3088r:3)[3328r,3344r:2)[4128r,4160r:1)  0@0B-phi 1@4128r 2@3328r 3@3048r 4@2312r 5@1328r 6@208r
     %vreg87:	[2912r,2944r:0)[2944r,3024r:1)  0@2912r 1@2944r
        -->	[2912r,2944r:0)[2944r,3048r:1)  0@2912r 1@2944r
AllocationOrder(SEGMENT_REG) = [ ]
********** GREEDY REGISTER ALLOCATION **********
********** Function: BZ2_bzWrite
********** INTERVALS **********
CH [0B,16r:0)[3072r,3088r:1)  0@0B-phi 1@3072r
CL [0B,16r:0)[3072r,3088r:1)  0@0B-phi 1@3072r
DH [0B,32r:0)[3056r,3088r:1)  0@0B-phi 1@3056r
DIL [0B,64r:0)[208r,240r:6)[1328r,1344r:5)[2312r,2320r:4)[3048r,3088r:3)[3328r,3344r:2)[4128r,4160r:1)  0@0B-phi 1@4128r 2@3328r 3@3048r 4@2312r 5@1328r 6@208r
DL [0B,32r:0)[3056r,3088r:1)  0@0B-phi 1@3056r
SIL [0B,48r:0)[224r,240r:4)[2304r,2320r:1)[3040r,3088r:3)[4144r,4160r:2)  0@0B-phi 1@2304r 2@4144r 3@3040r 4@224r
%vreg1 [64r,320r:0)  0@64r
%vreg3 [48r,336r:0)  0@48r
%vreg5 [32r,352r:0)  0@32r
%vreg7 [16r,368r:0)  0@16r
%vreg11 [384r,416r:0)  0@384r
%vreg14 [144r,208r:0)  0@144r
%vreg15 [176r,224r:0)  0@176r
%vreg17 [480r,496r:0)  0@480r
%vreg20 [576r,592r:0)  0@576r
%vreg26 [992r,1008r:0)  0@992r
%vreg29 [1104r,1120r:0)  0@1104r
%vreg32 [1200r,1216r:0)  0@1200r
%vreg35 [1376r,1440r:0)  0@1376r
%vreg37 [1296r,1328r:0)  0@1296r
%vreg38 [1280r,1296r:0)  0@1280r
%vreg42 [2048r,2064r:0)  0@2048r
%vreg43 [2032r,2064r:0)  0@2032r
%vreg46 [2000r,2016r:0)  0@2000r
%vreg47 [1984r,2016r:0)  0@1984r
%vreg52 [2352r,2416r:0)  0@2352r
%vreg54 [2224r,2256r:0)[2256r,2312r:1)  0@2224r 1@2256r
%vreg58 [2192r,2208r:0)  0@2192r
%vreg61 [2144r,2176r:0)[2176r,2208r:1)  0@2144r 1@2176r
%vreg64 [2112r,2128r:0)  0@2112r
%vreg67 [2736r,2752r:0)  0@2736r
%vreg70 [3216r,3232r:0)  0@3216r
%vreg79 [3120r,3200r:0)  0@3120r
%vreg81 [2992r,3072r:0)  0@2992r
%vreg82 [2976r,2992r:0)  0@2976r
%vreg84 [2960r,3056r:0)  0@2960r
%vreg87 [2912r,2944r:0)[2944r,3048r:1)  0@2912r 1@2944r
%vreg92 [2832r,2880r:0)[2880r,2896r:1)  0@2832r 1@2880r
%vreg94 [2848r,2880r:0)  0@2848r
%vreg97 [3376r,3440r:0)  0@3376r
%vreg99 [3296r,3328r:0)  0@3296r
%vreg100 [3280r,3296r:0)  0@3280r
%vreg103 [3744r,3760r:0)  0@3744r
%vreg106 [3856r,3872r:0)  0@3856r
%vreg109 [3952r,3968r:0)  0@3952r
%vreg112 [3536r,3552r:0)  0@3536r
%vreg115 [3632r,3648r:0)  0@3632r
%vreg119 [2544r,2560r:0)  0@2544r
%vreg120 [2528r,2560r:0)  0@2528r
%vreg124 [2656r,2672r:0)  0@2656r
%vreg125 [2640r,2672r:0)  0@2640r
%vreg128 [1808r,1824r:0)  0@1808r
%vreg131 [1904r,1920r:0)  0@1904r
%vreg134 [1536r,1552r:0)  0@1536r
%vreg137 [1632r,1648r:0)  0@1632r
%vreg140 [816r,832r:0)  0@816r
%vreg143 [912r,928r:0)  0@912r
%vreg145 [4064r,4128r:0)  0@4064r
%vreg146 [4096r,4144r:0)  0@4096r
RegMasks: 240r 1344r 2320r 3088r 3344r 4160r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzWrite: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=8, align=8, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=8, align=8, at location [SP+8]
  fi#3: size=4, align=4, at location [SP+8]
  fi#4: size=4, align=4, at location [SP+8]
  fi#5: size=4, align=4, at location [SP+8]
  fi#6: size=4, align=4, at location [SP+8]
  fi#7: size=8, align=8, at location [SP+8]
Function Live Ins: %RDI in %vreg0, %RSI in %vreg2, %RDX in %vreg4, %ECX in %vreg6

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI %RSI %RDX %ECX
16B		%vreg7<def> = COPY %ECX; GR32:%vreg7
32B		%vreg5<def> = COPY %RDX; GR64:%vreg5
48B		%vreg3<def> = COPY %RSI; GR64:%vreg3
64B		%vreg1<def> = COPY %RDI; GR64:%vreg1
144B		%vreg14<def> = MOV64ri <ga:@BZ2_bzWrite>; GR64:%vreg14
176B		%vreg15<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg15
192B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
208B		%RDI<def> = COPY %vreg14; GR64:%vreg14
224B		%RSI<def> = COPY %vreg15; GR64:%vreg15
240B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
256B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
272B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
288B		STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg5, 0, <fi#2>, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#7>, 0, %vreg7, 0, <fi#3>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack0] LD8[FixedStack7] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) GR64:%vreg3,%vreg5,%vreg1 GR32:%vreg7
304B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
320B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%bzerror.addr] GR64:%vreg1
336B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg3; mem:ST8[%b.addr] GR64:%vreg3
352B		MOV64mr <fi#2>, 1, %noreg, 0, %noreg, %vreg5; mem:ST8[%buf.addr] GR64:%vreg5
368B		MOV32mr <fi#3>, 1, %noreg, 0, %noreg, %vreg7; mem:ST4[%len.addr] GR32:%vreg7
384B		%vreg11<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr] GR64:%vreg11
416B		MOV64mr <fi#7>, 1, %noreg, 0, %noreg, %vreg11; mem:ST8[%bzf] GR64:%vreg11
432B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
448B		JE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

464B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
480B		%vreg17<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg17
496B		MOV32mi %vreg17, 1, %noreg, 0, %noreg, 0; mem:ST4[%3] GR64:%vreg17
	    Successors according to CFG: BB#2

512B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#1
528B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
544B		JE_1 <BB#4>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#4 BB#3

560B	BB#3: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#2
576B		%vreg20<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg20
592B		MOV32mi %vreg20, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr] GR64:%vreg20
	    Successors according to CFG: BB#4

608B	BB#4: derived from LLVM BB %if.end.3
	    Predecessors according to CFG: BB#2 BB#3
624B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
640B		JE_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#5

656B	BB#5: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#4
672B		CMP64mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%buf.addr]
688B		JE_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#6

704B	BB#6: derived from LLVM BB %lor.lhs.false.6
	    Predecessors according to CFG: BB#5
720B		CMP32mi8 <fi#3>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%len.addr]
736B		JGE_1 <BB#12>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#12 BB#7

752B	BB#7: derived from LLVM BB %if.then.8
	    Predecessors according to CFG: BB#4 BB#5 BB#6
768B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
784B		JE_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#8

800B	BB#8: derived from LLVM BB %if.then.10
	    Predecessors according to CFG: BB#7
816B		%vreg140<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg140
832B		MOV32mi %vreg140, 1, %noreg, 0, %noreg, -2; mem:ST4[%10] GR64:%vreg140
	    Successors according to CFG: BB#9

848B	BB#9: derived from LLVM BB %if.end.11
	    Predecessors according to CFG: BB#7 BB#8
864B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
880B		JE_1 <BB#11>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#11 BB#10

896B	BB#10: derived from LLVM BB %if.then.13
	    Predecessors according to CFG: BB#9
912B		%vreg143<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg143
928B		MOV32mi %vreg143, 1, %noreg, 5096, %noreg, -2; mem:ST4[%lastErr14] GR64:%vreg143
	    Successors according to CFG: BB#11

944B	BB#11: derived from LLVM BB %if.end.15
	    Predecessors according to CFG: BB#9 BB#10
960B		JMP_1 <BB#53>
	    Successors according to CFG: BB#53

976B	BB#12: derived from LLVM BB %if.end.16
	    Predecessors according to CFG: BB#6
992B		%vreg26<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg26
1008B		CMP8mi %vreg26, 1, %noreg, 5012, %noreg, 0, %EFLAGS<imp-def>; mem:LD1[%writing] GR64:%vreg26
1024B		JNE_1 <BB#18>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#18 BB#13

1040B	BB#13: derived from LLVM BB %if.then.17
	    Predecessors according to CFG: BB#12
1056B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
1072B		JE_1 <BB#15>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#15 BB#14

1088B	BB#14: derived from LLVM BB %if.then.19
	    Predecessors according to CFG: BB#13
1104B		%vreg29<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg29
1120B		MOV32mi %vreg29, 1, %noreg, 0, %noreg, -1; mem:ST4[%16] GR64:%vreg29
	    Successors according to CFG: BB#15

1136B	BB#15: derived from LLVM BB %if.end.20
	    Predecessors according to CFG: BB#13 BB#14
1152B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
1168B		JE_1 <BB#17>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#17 BB#16

1184B	BB#16: derived from LLVM BB %if.then.22
	    Predecessors according to CFG: BB#15
1200B		%vreg32<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg32
1216B		MOV32mi %vreg32, 1, %noreg, 5096, %noreg, -1; mem:ST4[%lastErr23] GR64:%vreg32
	    Successors according to CFG: BB#17

1232B	BB#17: derived from LLVM BB %if.end.24
	    Predecessors according to CFG: BB#15 BB#16
1248B		JMP_1 <BB#53>
	    Successors according to CFG: BB#53

1264B	BB#18: derived from LLVM BB %if.end.25
	    Predecessors according to CFG: BB#12
1280B		%vreg38<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg38
1296B		%vreg37<def> = MOV64rm %vreg38, 1, %noreg, 0, %noreg; mem:LD8[%handle] GR64:%vreg37,%vreg38
1312B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1328B		%RDI<def> = COPY %vreg37; GR64:%vreg37
1344B		CALL64pcrel32 <ga:@ferror>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
1360B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1376B		%vreg35<def> = COPY %EAX<kill>; GR32:%vreg35
1392B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1408B		STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#7>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, ...; mem:LD8[FixedStack2] LD8[FixedStack0] LD8[FixedStack7] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4)
1424B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1440B		CMP32ri8 %vreg35, 0, %EFLAGS<imp-def>; GR32:%vreg35
1456B		JE_1 <BB#24>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#24 BB#19

1472B	BB#19: derived from LLVM BB %if.then.27
	    Predecessors according to CFG: BB#18
1488B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
1504B		JE_1 <BB#21>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#21 BB#20

1520B	BB#20: derived from LLVM BB %if.then.29
	    Predecessors according to CFG: BB#19
1536B		%vreg134<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg134
1552B		MOV32mi %vreg134, 1, %noreg, 0, %noreg, -6; mem:ST4[%22] GR64:%vreg134
	    Successors according to CFG: BB#21

1568B	BB#21: derived from LLVM BB %if.end.30
	    Predecessors according to CFG: BB#19 BB#20
1584B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
1600B		JE_1 <BB#23>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#23 BB#22

1616B	BB#22: derived from LLVM BB %if.then.32
	    Predecessors according to CFG: BB#21
1632B		%vreg137<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg137
1648B		MOV32mi %vreg137, 1, %noreg, 5096, %noreg, -6; mem:ST4[%lastErr33] GR64:%vreg137
	    Successors according to CFG: BB#23

1664B	BB#23: derived from LLVM BB %if.end.34
	    Predecessors according to CFG: BB#21 BB#22
1680B		JMP_1 <BB#53>
	    Successors according to CFG: BB#53

1696B	BB#24: derived from LLVM BB %if.end.35
	    Predecessors according to CFG: BB#18
1712B		CMP32mi8 <fi#3>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%len.addr]
1728B		JNE_1 <BB#30>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#30 BB#25

1744B	BB#25: derived from LLVM BB %if.then.37
	    Predecessors according to CFG: BB#24
1760B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
1776B		JE_1 <BB#27>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#27 BB#26

1792B	BB#26: derived from LLVM BB %if.then.39
	    Predecessors according to CFG: BB#25
1808B		%vreg128<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg128
1824B		MOV32mi %vreg128, 1, %noreg, 0, %noreg, 0; mem:ST4[%27] GR64:%vreg128
	    Successors according to CFG: BB#27

1840B	BB#27: derived from LLVM BB %if.end.40
	    Predecessors according to CFG: BB#25 BB#26
1856B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
1872B		JE_1 <BB#29>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#29 BB#28

1888B	BB#28: derived from LLVM BB %if.then.42
	    Predecessors according to CFG: BB#27
1904B		%vreg131<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg131
1920B		MOV32mi %vreg131, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr43] GR64:%vreg131
	    Successors according to CFG: BB#29

1936B	BB#29: derived from LLVM BB %if.end.44
	    Predecessors according to CFG: BB#27 BB#28
1952B		JMP_1 <BB#53>
	    Successors according to CFG: BB#53

1968B	BB#30: derived from LLVM BB %if.end.45
	    Predecessors according to CFG: BB#24
1984B		%vreg47<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%len.addr] GR32:%vreg47
2000B		%vreg46<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg46
2016B		MOV32mr %vreg46, 1, %noreg, 5024, %noreg, %vreg47; mem:ST4[%avail_in] GR64:%vreg46 GR32:%vreg47
2032B		%vreg43<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%buf.addr] GR64:%vreg43
2048B		%vreg42<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg42
2064B		MOV64mr %vreg42, 1, %noreg, 5016, %noreg, %vreg43; mem:ST8[%next_in] GR64:%vreg42,%vreg43
	    Successors according to CFG: BB#31

2080B	BB#31: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#30 BB#52
2112B		%vreg64<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg64
2128B		MOV32mi %vreg64, 1, %noreg, 5048, %noreg, 5000; mem:ST4[%avail_out] GR64:%vreg64
2144B		%vreg61<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg61
2176B		%vreg61<def,tied1> = ADD64ri8 %vreg61<tied0>, 8, %EFLAGS<imp-def,dead>; GR64:%vreg61
2192B		%vreg58<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg58
2208B		MOV64mr %vreg58, 1, %noreg, 5040, %noreg, %vreg61; mem:ST8[%next_out] GR64:%vreg58,%vreg61
2224B		%vreg54<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg54
2256B		%vreg54<def,tied1> = ADD64ri32 %vreg54<tied0>, 5016, %EFLAGS<imp-def,dead>; GR64:%vreg54
2272B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2304B		%ESI<def> = MOV32r0 %EFLAGS<imp-def,dead>
2312B		%RDI<def> = COPY %vreg54; GR64:%vreg54
2320B		CALL64pcrel32 <ga:@BZ2_bzCompress>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %EAX<imp-def>
2336B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2352B		%vreg52<def> = COPY %EAX<kill>; GR32:%vreg52
2368B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2384B		STACKMAP 2, 0, 0, <fi#0>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, ...; mem:LD8[FixedStack0] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4)
2400B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2416B		MOV32mr <fi#6>, 1, %noreg, 0, %noreg, %vreg52; mem:ST4[%ret] GR32:%vreg52
2432B		CMP32mi8 <fi#6>, 1, %noreg, 0, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%ret]
2448B		JE_1 <BB#37>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#37 BB#32

2464B	BB#32: derived from LLVM BB %if.then.53
	    Predecessors according to CFG: BB#31
2480B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
2496B		JE_1 <BB#34>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#34 BB#33

2512B	BB#33: derived from LLVM BB %if.then.55
	    Predecessors according to CFG: BB#32
2528B		%vreg120<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%ret] GR32:%vreg120
2544B		%vreg119<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg119
2560B		MOV32mr %vreg119, 1, %noreg, 0, %noreg, %vreg120; mem:ST4[%41] GR64:%vreg119 GR32:%vreg120
	    Successors according to CFG: BB#34

2576B	BB#34: derived from LLVM BB %if.end.56
	    Predecessors according to CFG: BB#32 BB#33
2592B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
2608B		JE_1 <BB#36>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#36 BB#35

2624B	BB#35: derived from LLVM BB %if.then.58
	    Predecessors according to CFG: BB#34
2640B		%vreg125<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%ret] GR32:%vreg125
2656B		%vreg124<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg124
2672B		MOV32mr %vreg124, 1, %noreg, 5096, %noreg, %vreg125; mem:ST4[%lastErr59] GR64:%vreg124 GR32:%vreg125
	    Successors according to CFG: BB#36

2688B	BB#36: derived from LLVM BB %if.end.60
	    Predecessors according to CFG: BB#34 BB#35
2704B		JMP_1 <BB#53>
	    Successors according to CFG: BB#53

2720B	BB#37: derived from LLVM BB %if.end.61
	    Predecessors according to CFG: BB#31
2736B		%vreg67<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg67
2752B		CMP32mi %vreg67, 1, %noreg, 5048, %noreg, 5000, %EFLAGS<imp-def>; mem:LD4[%avail_out63] GR64:%vreg67
2768B		JAE_1 <BB#46>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#46 BB#38

2784B	BB#38: derived from LLVM BB %if.then.65
	    Predecessors according to CFG: BB#37
2832B		%vreg92<def> = MOV32ri 5000; GR32:%vreg92
2848B		%vreg94<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg94
2880B		%vreg92<def,tied1> = SUB32rm %vreg92<tied0>, %vreg94, 1, %noreg, 5048, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%avail_out67] GR32:%vreg92 GR64:%vreg94
2896B		MOV32mr <fi#4>, 1, %noreg, 0, %noreg, %vreg92; mem:ST4[%n] GR32:%vreg92
2912B		%vreg87<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg87
2944B		%vreg87<def,tied1> = ADD64ri8 %vreg87<tied0>, 8, %EFLAGS<imp-def,dead>; GR64:%vreg87
2960B		%vreg84<def> = MOVSX64rm32 <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%n] GR64:%vreg84
2976B		%vreg82<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg82
2992B		%vreg81<def> = MOV64rm %vreg82, 1, %noreg, 0, %noreg; mem:LD8[%handle70] GR64:%vreg81,%vreg82
3008B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3040B		%ESI<def,dead> = MOV32ri 1, %RSI<imp-def>
3048B		%RDI<def> = COPY %vreg87; GR64:%vreg87
3056B		%RDX<def> = COPY %vreg84; GR64:%vreg84
3072B		%RCX<def> = COPY %vreg81; GR64:%vreg81
3088B		CALL64pcrel32 <ga:@fwrite>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %RDX<imp-use>, %RCX<imp-use>, %RAX<imp-def>
3104B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3120B		%vreg79<def> = COPY %RAX<kill>; GR64_with_sub_8bit:%vreg79
3136B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3152B		STACKMAP 3, 0, 0, <fi#0>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, ...; mem:LD8[FixedStack0] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4)
3168B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3200B		MOV32mr <fi#5>, 1, %noreg, 0, %noreg, %vreg79:sub_32bit; mem:ST4[%n2] GR64_with_sub_8bit:%vreg79
3216B		%vreg70<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%n] GR32:%vreg70
3232B		CMP32rm %vreg70, <fi#5>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD4[%n2] GR32:%vreg70
3248B		JNE_1 <BB#40>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#40 BB#39

3264B	BB#39: derived from LLVM BB %lor.lhs.false.75
	    Predecessors according to CFG: BB#38
3280B		%vreg100<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg100
3296B		%vreg99<def> = MOV64rm %vreg100, 1, %noreg, 0, %noreg; mem:LD8[%handle76] GR64:%vreg99,%vreg100
3312B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3328B		%RDI<def> = COPY %vreg99; GR64:%vreg99
3344B		CALL64pcrel32 <ga:@ferror>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
3360B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3376B		%vreg97<def> = COPY %EAX<kill>; GR32:%vreg97
3392B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3408B		STACKMAP 4, 0, 0, <fi#0>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, ...; mem:LD8[FixedStack0] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4)
3424B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3440B		CMP32ri8 %vreg97, 0, %EFLAGS<imp-def>; GR32:%vreg97
3456B		JE_1 <BB#45>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#45 BB#40

3472B	BB#40: derived from LLVM BB %if.then.79
	    Predecessors according to CFG: BB#38 BB#39
3488B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
3504B		JE_1 <BB#42>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#42 BB#41

3520B	BB#41: derived from LLVM BB %if.then.82
	    Predecessors according to CFG: BB#40
3536B		%vreg112<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg112
3552B		MOV32mi %vreg112, 1, %noreg, 0, %noreg, -6; mem:ST4[%58] GR64:%vreg112
	    Successors according to CFG: BB#42

3568B	BB#42: derived from LLVM BB %if.end.83
	    Predecessors according to CFG: BB#40 BB#41
3584B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
3600B		JE_1 <BB#44>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#44 BB#43

3616B	BB#43: derived from LLVM BB %if.then.86
	    Predecessors according to CFG: BB#42
3632B		%vreg115<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg115
3648B		MOV32mi %vreg115, 1, %noreg, 5096, %noreg, -6; mem:ST4[%lastErr87] GR64:%vreg115
	    Successors according to CFG: BB#44

3664B	BB#44: derived from LLVM BB %if.end.88
	    Predecessors according to CFG: BB#42 BB#43
3680B		JMP_1 <BB#53>
	    Successors according to CFG: BB#53

3696B	BB#45: derived from LLVM BB %if.end.89
	    Predecessors according to CFG: BB#39
3712B		JMP_1 <BB#46>
	    Successors according to CFG: BB#46

3728B	BB#46: derived from LLVM BB %if.end.90
	    Predecessors according to CFG: BB#37 BB#45
3744B		%vreg103<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg103
3760B		CMP32mi8 %vreg103, 1, %noreg, 5024, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_in92] GR64:%vreg103
3776B		JNE_1 <BB#52>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#52 BB#47

3792B	BB#47: derived from LLVM BB %if.then.95
	    Predecessors according to CFG: BB#46
3808B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
3824B		JE_1 <BB#49>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#49 BB#48

3840B	BB#48: derived from LLVM BB %if.then.98
	    Predecessors according to CFG: BB#47
3856B		%vreg106<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg106
3872B		MOV32mi %vreg106, 1, %noreg, 0, %noreg, 0; mem:ST4[%64] GR64:%vreg106
	    Successors according to CFG: BB#49

3888B	BB#49: derived from LLVM BB %if.end.99
	    Predecessors according to CFG: BB#47 BB#48
3904B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
3920B		JE_1 <BB#51>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#51 BB#50

3936B	BB#50: derived from LLVM BB %if.then.102
	    Predecessors according to CFG: BB#49
3952B		%vreg109<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg109
3968B		MOV32mi %vreg109, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr103] GR64:%vreg109
	    Successors according to CFG: BB#51

3984B	BB#51: derived from LLVM BB %if.end.104
	    Predecessors according to CFG: BB#49 BB#50
4000B		JMP_1 <BB#53>
	    Successors according to CFG: BB#53

4016B	BB#52: derived from LLVM BB %if.end.105
	    Predecessors according to CFG: BB#46
4032B		JMP_1 <BB#31>
	    Successors according to CFG: BB#31

4048B	BB#53: derived from LLVM BB %return
	    Predecessors according to CFG: BB#17 BB#51 BB#44 BB#36 BB#29 BB#23 BB#11
4064B		%vreg145<def> = MOV64ri <ga:@BZ2_bzWrite>; GR64:%vreg145
4096B		%vreg146<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg146
4112B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4128B		%RDI<def> = COPY %vreg145; GR64:%vreg145
4144B		%RSI<def> = COPY %vreg146; GR64:%vreg146
4160B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
4176B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4192B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4208B		STACKMAP 5, 0, ...
4224B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4240B		RETQ

# End machine code for function BZ2_bzWrite.


selectOrSplit GR32:%vreg7 [16r,368r:0)  0@16r w=4.029255e-03
hints: %ECX
missed hint %ECX
assigning %vreg7 to %EBX: BH [16r,368r:0)  0@16r BL [16r,368r:0)  0@16r

selectOrSplit GR64:%vreg5 [32r,352r:0)  0@32r w=4.208333e-03
hints: %RDX
missed hint %RDX
%R14 is available at cost 1
Only trying the first 10 regs.
should evict: %vreg7 [16r,368r:0)  0@16r w= 4.029255e-03
hints: %ECX
can reassign: %vreg7 [16r,368r:0)  0@16r from %RBX to %ECX
should evict: %vreg7 [16r,368r:0)  0@16r w= 4.029255e-03
hints: %ECX
can reassign: %vreg7 [16r,368r:0)  0@16r from %RBX to %ECX
evicting %RBX interference: Cascade 1
unassigning %vreg7 from %EBX: BH BL
assigning %vreg5 to %RBX: BH [32r,352r:0)  0@32r BL [32r,352r:0)  0@32r
queuing new interval: %vreg7 [16r,368r:0)  0@16r

selectOrSplit GR32:%vreg7 [16r,368r:0)  0@16r w=4.029255e-03
hints: %ECX
missed hint %ECX
%R14D is available at cost 1
Only trying the first 10 regs.
assigning %vreg7 to %R14D: R14B [16r,368r:0)  0@16r

selectOrSplit GR64:%vreg3 [48r,336r:0)  0@48r w=4.404070e-03
hints: %RSI
missed hint %RSI
%R15 is available at cost 1
Only trying the first 10 regs.
should evict: %vreg5 [32r,352r:0)  0@32r w= 4.208333e-03
hints: %RDX
can reassign: %vreg5 [32r,352r:0)  0@32r from %RBX to %RDX
should evict: %vreg5 [32r,352r:0)  0@32r w= 4.208333e-03
hints: %RDX
can reassign: %vreg5 [32r,352r:0)  0@32r from %RBX to %RDX
evicting %RBX interference: Cascade 2
unassigning %vreg5 from %RBX: BH BL
assigning %vreg3 to %RBX: BH [48r,336r:0)  0@48r BL [48r,336r:0)  0@48r
queuing new interval: %vreg5 [32r,352r:0)  0@32r

selectOrSplit GR64:%vreg5 [32r,352r:0)  0@32r w=4.208333e-03
hints: %RDX
missed hint %RDX
%R15 is available at cost 1
Only trying the first 10 regs.
assigning %vreg5 to %R15: R15B [32r,352r:0)  0@32r

selectOrSplit GR64:%vreg1 [64r,320r:0)  0@64r w=4.618902e-03
hints: %RDI
missed hint %RDI
%R12 is available at cost 1
Only trying the first 10 regs.
should evict: %vreg3 [48r,336r:0)  0@48r w= 4.404070e-03
hints: %RSI
can reassign: %vreg3 [48r,336r:0)  0@48r from %RBX to %RSI
should evict: %vreg3 [48r,336r:0)  0@48r w= 4.404070e-03
hints: %RSI
can reassign: %vreg3 [48r,336r:0)  0@48r from %RBX to %RSI
evicting %RBX interference: Cascade 3
unassigning %vreg3 from %RBX: BH BL
assigning %vreg1 to %RBX: BH [64r,320r:0)  0@64r BL [64r,320r:0)  0@64r
queuing new interval: %vreg3 [48r,336r:0)  0@48r

selectOrSplit GR64:%vreg3 [48r,336r:0)  0@48r w=4.404070e-03
hints: %RSI
missed hint %RSI
%R12 is available at cost 1
Only trying the first 10 regs.
assigning %vreg3 to %R12: R12B [48r,336r:0)  0@48r

selectOrSplit GR64:%vreg14 [144r,208r:0)  0@144r w=2.176724e-03
hints: %RDI
assigning %vreg14 to %RDI: DIL [144r,208r:0)  0@144r

selectOrSplit GR64:%vreg15 [176r,224r:0)  0@176r w=4.508928e-03
hints: %RSI
assigning %vreg15 to %RSI: SIL [176r,224r:0)  0@176r

selectOrSplit GR64:%vreg37 [1296r,1328r:0)  0@1296r w=2.916111e-04
hints: %RDI
assigning %vreg37 to %RDI: DIL [1296r,1328r:0)  0@1296r

selectOrSplit GR32:%vreg35 [1376r,1440r:0)  0@1376r w=2.715000e-04
hints: %EAX
assigning %vreg35 to %EAX: AH [1376r,1440r:0)  0@1376r AL [1376r,1440r:0)  0@1376r

selectOrSplit GR64:%vreg54 [2224r,2256r:0)[2256r,2312r:1)  0@2224r 1@2256r w=1.521333e-04
hints: %RDI
assigning %vreg54 to %RDI: DIL [2224r,2256r:0)[2256r,2312r:1)  0@2224r 1@2256r

selectOrSplit GR32:%vreg52 [2352r,2416r:0)  0@2352r w=8.000115e-05
hints: %EAX
assigning %vreg52 to %EAX: AH [2352r,2416r:0)  0@2352r AL [2352r,2416r:0)  0@2352r

selectOrSplit GR64:%vreg87 [2912r,2944r:0)[2944r,3048r:1)  0@2912r 1@2944r w=3.380939e-05
hints: %RDI
assigning %vreg87 to %RDI: DIL [2912r,2944r:0)[2944r,3048r:1)  0@2912r 1@2944r

selectOrSplit GR64:%vreg84 [2960r,3056r:0)  0@2960r w=1.826798e-05
hints: %RDX
assigning %vreg84 to %RDX: DH [2960r,3056r:0)  0@2960r DL [2960r,3056r:0)  0@2960r

selectOrSplit GR64:%vreg81 [2992r,3072r:0)  0@2992r w=1.887691e-05
hints: %RCX
assigning %vreg81 to %RCX: CH [2992r,3072r:0)  0@2992r CL [2992r,3072r:0)  0@2992r

selectOrSplit GR64_with_sub_8bit:%vreg79 [3120r,3200r:0)  0@3120r w=1.887691e-05
hints: %RAX
assigning %vreg79 to %RAX: AH [3120r,3200r:0)  0@3120r AL [3120r,3200r:0)  0@3120r

selectOrSplit GR64:%vreg99 [3296r,3328r:0)  0@3296r w=1.014888e-05
hints: %RDI
assigning %vreg99 to %RDI: DIL [3296r,3328r:0)  0@3296r

selectOrSplit GR32:%vreg97 [3376r,3440r:0)  0@3376r w=9.448955e-06
hints: %EAX
assigning %vreg97 to %EAX: AH [3376r,3440r:0)  0@3376r AL [3376r,3440r:0)  0@3376r

selectOrSplit GR64:%vreg145 [4064r,4128r:0)  0@4064r w=2.176724e-03
hints: %RDI
assigning %vreg145 to %RDI: DIL [4064r,4128r:0)  0@4064r

selectOrSplit GR64:%vreg146 [4096r,4144r:0)  0@4096r w=4.508928e-03
hints: %RSI
assigning %vreg146 to %RSI: SIL [4096r,4144r:0)  0@4096r

selectOrSplit GR64:%vreg11 [384r,416r:0)  0@384r w=inf
assigning %vreg11 to %RAX: AH [384r,416r:0)  0@384r AL [384r,416r:0)  0@384r

selectOrSplit GR64:%vreg17 [480r,496r:0)  0@480r w=inf
assigning %vreg17 to %RAX: AH [480r,496r:0)  0@480r AL [480r,496r:0)  0@480r

selectOrSplit GR64:%vreg20 [576r,592r:0)  0@576r w=inf
assigning %vreg20 to %RAX: AH [576r,592r:0)  0@576r AL [576r,592r:0)  0@576r

selectOrSplit GR64:%vreg140 [816r,832r:0)  0@816r w=inf
assigning %vreg140 to %RAX: AH [816r,832r:0)  0@816r AL [816r,832r:0)  0@816r

selectOrSplit GR64:%vreg143 [912r,928r:0)  0@912r w=inf
assigning %vreg143 to %RAX: AH [912r,928r:0)  0@912r AL [912r,928r:0)  0@912r

selectOrSplit GR64:%vreg26 [992r,1008r:0)  0@992r w=inf
assigning %vreg26 to %RAX: AH [992r,1008r:0)  0@992r AL [992r,1008r:0)  0@992r

selectOrSplit GR64:%vreg29 [1104r,1120r:0)  0@1104r w=inf
assigning %vreg29 to %RAX: AH [1104r,1120r:0)  0@1104r AL [1104r,1120r:0)  0@1104r

selectOrSplit GR64:%vreg32 [1200r,1216r:0)  0@1200r w=inf
assigning %vreg32 to %RAX: AH [1200r,1216r:0)  0@1200r AL [1200r,1216r:0)  0@1200r

selectOrSplit GR64:%vreg38 [1280r,1296r:0)  0@1280r w=inf
assigning %vreg38 to %RAX: AH [1280r,1296r:0)  0@1280r AL [1280r,1296r:0)  0@1280r

selectOrSplit GR64:%vreg134 [1536r,1552r:0)  0@1536r w=inf
assigning %vreg134 to %RAX: AH [1536r,1552r:0)  0@1536r AL [1536r,1552r:0)  0@1536r

selectOrSplit GR64:%vreg137 [1632r,1648r:0)  0@1632r w=inf
assigning %vreg137 to %RAX: AH [1632r,1648r:0)  0@1632r AL [1632r,1648r:0)  0@1632r

selectOrSplit GR64:%vreg128 [1808r,1824r:0)  0@1808r w=inf
assigning %vreg128 to %RAX: AH [1808r,1824r:0)  0@1808r AL [1808r,1824r:0)  0@1808r

selectOrSplit GR64:%vreg131 [1904r,1920r:0)  0@1904r w=inf
assigning %vreg131 to %RAX: AH [1904r,1920r:0)  0@1904r AL [1904r,1920r:0)  0@1904r

selectOrSplit GR32:%vreg47 [1984r,2016r:0)  0@1984r w=7.167854e-05
assigning %vreg47 to %EAX: AH [1984r,2016r:0)  0@1984r AL [1984r,2016r:0)  0@1984r

selectOrSplit GR64:%vreg46 [2000r,2016r:0)  0@2000r w=inf
assigning %vreg46 to %RCX: CH [2000r,2016r:0)  0@2000r CL [2000r,2016r:0)  0@2000r

selectOrSplit GR64:%vreg43 [2032r,2064r:0)  0@2032r w=7.167854e-05
assigning %vreg43 to %RAX: AH [2032r,2064r:0)  0@2032r AL [2032r,2064r:0)  0@2032r

selectOrSplit GR64:%vreg42 [2048r,2064r:0)  0@2048r w=inf
assigning %vreg42 to %RCX: CH [2048r,2064r:0)  0@2048r CL [2048r,2064r:0)  0@2048r

selectOrSplit GR64:%vreg64 [2112r,2128r:0)  0@2112r w=inf
assigning %vreg64 to %RAX: AH [2112r,2128r:0)  0@2112r AL [2112r,2128r:0)  0@2112r

selectOrSplit GR64:%vreg61 [2144r,2176r:0)[2176r,2208r:1)  0@2144r 1@2176r w=1.584181e-04
assigning %vreg61 to %RAX: AH [2144r,2176r:0)[2176r,2208r:1)  0@2144r 1@2176r AL [2144r,2176r:0)[2176r,2208r:1)  0@2144r 1@2176r

selectOrSplit GR64:%vreg58 [2192r,2208r:0)  0@2192r w=inf
assigning %vreg58 to %RCX: CH [2192r,2208r:0)  0@2192r CL [2192r,2208r:0)  0@2192r

selectOrSplit GR32:%vreg120 [2528r,2560r:0)  0@2528r w=2.076668e-05
assigning %vreg120 to %EAX: AH [2528r,2560r:0)  0@2528r AL [2528r,2560r:0)  0@2528r

selectOrSplit GR64:%vreg119 [2544r,2560r:0)  0@2544r w=inf
assigning %vreg119 to %RCX: CH [2544r,2560r:0)  0@2544r CL [2544r,2560r:0)  0@2544r

selectOrSplit GR32:%vreg125 [2640r,2672r:0)  0@2640r w=2.076668e-05
assigning %vreg125 to %EAX: AH [2640r,2672r:0)  0@2640r AL [2640r,2672r:0)  0@2640r

selectOrSplit GR64:%vreg124 [2656r,2672r:0)  0@2656r w=inf
assigning %vreg124 to %RCX: CH [2656r,2672r:0)  0@2656r CL [2656r,2672r:0)  0@2656r

selectOrSplit GR64:%vreg67 [2736r,2752r:0)  0@2736r w=inf
assigning %vreg67 to %RAX: AH [2736r,2752r:0)  0@2736r AL [2736r,2752r:0)  0@2736r

selectOrSplit GR32:%vreg92 [2832r,2880r:0)[2880r,2896r:1)  0@2832r 1@2880r w=3.866899e-05
assigning %vreg92 to %EAX: AH [2832r,2880r:0)[2880r,2896r:1)  0@2832r 1@2880r AL [2832r,2880r:0)[2880r,2896r:1)  0@2832r 1@2880r

selectOrSplit GR64:%vreg94 [2848r,2880r:0)  0@2848r w=inf
assigning %vreg94 to %RCX: CH [2848r,2880r:0)  0@2848r CL [2848r,2880r:0)  0@2848r

selectOrSplit GR64:%vreg82 [2976r,2992r:0)  0@2976r w=inf
assigning %vreg82 to %RAX: AH [2976r,2992r:0)  0@2976r AL [2976r,2992r:0)  0@2976r

selectOrSplit GR32:%vreg70 [3216r,3232r:0)  0@3216r w=inf
assigning %vreg70 to %EAX: AH [3216r,3232r:0)  0@3216r AL [3216r,3232r:0)  0@3216r

selectOrSplit GR64:%vreg100 [3280r,3296r:0)  0@3280r w=inf
assigning %vreg100 to %RAX: AH [3280r,3296r:0)  0@3280r AL [3280r,3296r:0)  0@3280r

selectOrSplit GR64:%vreg112 [3536r,3552r:0)  0@3536r w=inf
assigning %vreg112 to %RAX: AH [3536r,3552r:0)  0@3536r AL [3536r,3552r:0)  0@3536r

selectOrSplit GR64:%vreg115 [3632r,3648r:0)  0@3632r w=inf
assigning %vreg115 to %RAX: AH [3632r,3648r:0)  0@3632r AL [3632r,3648r:0)  0@3632r

selectOrSplit GR64:%vreg103 [3744r,3760r:0)  0@3744r w=inf
assigning %vreg103 to %RAX: AH [3744r,3760r:0)  0@3744r AL [3744r,3760r:0)  0@3744r

selectOrSplit GR64:%vreg106 [3856r,3872r:0)  0@3856r w=inf
assigning %vreg106 to %RAX: AH [3856r,3872r:0)  0@3856r AL [3856r,3872r:0)  0@3856r

selectOrSplit GR64:%vreg109 [3952r,3968r:0)  0@3952r w=inf
assigning %vreg109 to %RAX: AH [3952r,3968r:0)  0@3952r AL [3952r,3968r:0)  0@3952r

********** STACK TRANSFORMATION METADATA **********
********** Function: BZ2_bzWrite
********** REGISTER MAP **********
[%vreg1 -> %RBX] GR64
[%vreg3 -> %R12] GR64
[%vreg5 -> %R15] GR64
[%vreg7 -> %R14D] GR32
[%vreg11 -> %RAX] GR64
[%vreg14 -> %RDI] GR64
[%vreg15 -> %RSI] GR64
[%vreg17 -> %RAX] GR64
[%vreg20 -> %RAX] GR64
[%vreg26 -> %RAX] GR64
[%vreg29 -> %RAX] GR64
[%vreg32 -> %RAX] GR64
[%vreg35 -> %EAX] GR32
[%vreg37 -> %RDI] GR64
[%vreg38 -> %RAX] GR64
[%vreg42 -> %RCX] GR64
[%vreg43 -> %RAX] GR64
[%vreg46 -> %RCX] GR64
[%vreg47 -> %EAX] GR32
[%vreg52 -> %EAX] GR32
[%vreg54 -> %RDI] GR64
[%vreg58 -> %RCX] GR64
[%vreg61 -> %RAX] GR64
[%vreg64 -> %RAX] GR64
[%vreg67 -> %RAX] GR64
[%vreg70 -> %EAX] GR32
[%vreg79 -> %RAX] GR64_with_sub_8bit
[%vreg81 -> %RCX] GR64
[%vreg82 -> %RAX] GR64
[%vreg84 -> %RDX] GR64
[%vreg87 -> %RDI] GR64
[%vreg92 -> %EAX] GR32
[%vreg94 -> %RCX] GR64
[%vreg97 -> %EAX] GR32
[%vreg99 -> %RDI] GR64
[%vreg100 -> %RAX] GR64
[%vreg103 -> %RAX] GR64
[%vreg106 -> %RAX] GR64
[%vreg109 -> %RAX] GR64
[%vreg112 -> %RAX] GR64
[%vreg115 -> %RAX] GR64
[%vreg119 -> %RCX] GR64
[%vreg120 -> %EAX] GR32
[%vreg124 -> %RCX] GR64
[%vreg125 -> %EAX] GR32
[%vreg128 -> %RAX] GR64
[%vreg131 -> %RAX] GR64
[%vreg134 -> %RAX] GR64
[%vreg137 -> %RAX] GR64
[%vreg140 -> %RAX] GR64
[%vreg143 -> %RAX] GR64
[%vreg145 -> %RDI] GR64
[%vreg146 -> %RSI] GR64


Stackmap 0:
  STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg5, 0, <fi#2>, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#7>, 0, %vreg7, 0, <fi#3>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack0] LD8[FixedStack7] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) GR64:%vreg3,%vreg5,%vreg1 GR32:%vreg7

i8* %b: in register %R12 (vreg 3)
i8** %b.addr: in stack slot 1 (size: 8)
i8* %buf: in register %R15 (vreg 5)
i8** %buf.addr: in stack slot 2 (size: 8)
i32* %bzerror: in register %RBX (vreg 1)
i32** %bzerror.addr: in stack slot 0 (size: 8)
%struct.bzFile** %bzf: in stack slot 7 (size: 8)
i32 %len: in register %R14D (vreg 7)
i32* %len.addr: in stack slot 3 (size: 4)
i32* %n: in stack slot 4 (size: 4)
i32* %n2: in stack slot 5 (size: 4)
i32* %ret: in stack slot 6 (size: 4)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#7>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, ...; mem:LD8[FixedStack2] LD8[FixedStack0] LD8[FixedStack7] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4)

i8** %buf.addr: in stack slot 2 (size: 8)
i32** %bzerror.addr: in stack slot 0 (size: 8)
%struct.bzFile** %bzf: in stack slot 7 (size: 8)
i32* %len.addr: in stack slot 3 (size: 4)
i32* %n: in stack slot 4 (size: 4)
i32* %n2: in stack slot 5 (size: 4)
i32* %ret: in stack slot 6 (size: 4)

Duplicate operand locations:


Stackmap 2:
  STACKMAP 2, 0, 0, <fi#0>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, ...; mem:LD8[FixedStack0] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4)

i32** %bzerror.addr: in stack slot 0 (size: 8)
%struct.bzFile** %bzf: in stack slot 7 (size: 8)
i32* %n: in stack slot 4 (size: 4)
i32* %n2: in stack slot 5 (size: 4)
i32* %ret: in stack slot 6 (size: 4)

Duplicate operand locations:


Stackmap 3:
  STACKMAP 3, 0, 0, <fi#0>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, ...; mem:LD8[FixedStack0] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4)

i32** %bzerror.addr: in stack slot 0 (size: 8)
%struct.bzFile** %bzf: in stack slot 7 (size: 8)
i32* %n: in stack slot 4 (size: 4)
i32* %n2: in stack slot 5 (size: 4)
i32* %ret: in stack slot 6 (size: 4)

Duplicate operand locations:


Stackmap 4:
  STACKMAP 4, 0, 0, <fi#0>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, ...; mem:LD8[FixedStack0] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4)

i32** %bzerror.addr: in stack slot 0 (size: 8)
%struct.bzFile** %bzf: in stack slot 7 (size: 8)
i32* %n: in stack slot 4 (size: 4)
i32* %n2: in stack slot 5 (size: 4)
i32* %ret: in stack slot 6 (size: 4)

Duplicate operand locations:


Stackmap 5:
  STACKMAP 5, 0, ...


Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg5, 0, <fi#2>, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#7>, 0, %vreg7, 0, <fi#3>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack0] LD8[FixedStack7] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) GR64:%vreg3,%vreg5,%vreg1 GR32:%vreg7
  -> Call instruction SlotIndex 240B, searching vregs 0 -> 147 and stack slots -1 -> 8

  STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#7>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, ...; mem:LD8[FixedStack2] LD8[FixedStack0] LD8[FixedStack7] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4)
  -> Call instruction SlotIndex 1344B, searching vregs 0 -> 147 and stack slots -1 -> 8

  STACKMAP 2, 0, 0, <fi#0>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, ...; mem:LD8[FixedStack0] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4)
  -> Call instruction SlotIndex 2320B, searching vregs 0 -> 147 and stack slots -1 -> 8

  STACKMAP 3, 0, 0, <fi#0>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, ...; mem:LD8[FixedStack0] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4)
  -> Call instruction SlotIndex 3088B, searching vregs 0 -> 147 and stack slots -1 -> 8

  STACKMAP 4, 0, 0, <fi#0>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, ...; mem:LD8[FixedStack0] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4)
  -> Call instruction SlotIndex 3344B, searching vregs 0 -> 147 and stack slots -1 -> 8

  STACKMAP 5, 0, ...
  -> Call instruction SlotIndex 4160B, searching vregs 0 -> 147 and stack slots -1 -> 8

********** REWRITE VIRTUAL REGISTERS **********
********** Function: BZ2_bzWrite
********** REGISTER MAP **********
[%vreg1 -> %RBX] GR64
[%vreg3 -> %R12] GR64
[%vreg5 -> %R15] GR64
[%vreg7 -> %R14D] GR32
[%vreg11 -> %RAX] GR64
[%vreg14 -> %RDI] GR64
[%vreg15 -> %RSI] GR64
[%vreg17 -> %RAX] GR64
[%vreg20 -> %RAX] GR64
[%vreg26 -> %RAX] GR64
[%vreg29 -> %RAX] GR64
[%vreg32 -> %RAX] GR64
[%vreg35 -> %EAX] GR32
[%vreg37 -> %RDI] GR64
[%vreg38 -> %RAX] GR64
[%vreg42 -> %RCX] GR64
[%vreg43 -> %RAX] GR64
[%vreg46 -> %RCX] GR64
[%vreg47 -> %EAX] GR32
[%vreg52 -> %EAX] GR32
[%vreg54 -> %RDI] GR64
[%vreg58 -> %RCX] GR64
[%vreg61 -> %RAX] GR64
[%vreg64 -> %RAX] GR64
[%vreg67 -> %RAX] GR64
[%vreg70 -> %EAX] GR32
[%vreg79 -> %RAX] GR64_with_sub_8bit
[%vreg81 -> %RCX] GR64
[%vreg82 -> %RAX] GR64
[%vreg84 -> %RDX] GR64
[%vreg87 -> %RDI] GR64
[%vreg92 -> %EAX] GR32
[%vreg94 -> %RCX] GR64
[%vreg97 -> %EAX] GR32
[%vreg99 -> %RDI] GR64
[%vreg100 -> %RAX] GR64
[%vreg103 -> %RAX] GR64
[%vreg106 -> %RAX] GR64
[%vreg109 -> %RAX] GR64
[%vreg112 -> %RAX] GR64
[%vreg115 -> %RAX] GR64
[%vreg119 -> %RCX] GR64
[%vreg120 -> %EAX] GR32
[%vreg124 -> %RCX] GR64
[%vreg125 -> %EAX] GR32
[%vreg128 -> %RAX] GR64
[%vreg131 -> %RAX] GR64
[%vreg134 -> %RAX] GR64
[%vreg137 -> %RAX] GR64
[%vreg140 -> %RAX] GR64
[%vreg143 -> %RAX] GR64
[%vreg145 -> %RDI] GR64
[%vreg146 -> %RSI] GR64

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %ECX %RDI %RDX %RSI
16B		%vreg7<def> = COPY %ECX; GR32:%vreg7
32B		%vreg5<def> = COPY %RDX; GR64:%vreg5
48B		%vreg3<def> = COPY %RSI; GR64:%vreg3
64B		%vreg1<def> = COPY %RDI; GR64:%vreg1
144B		%vreg14<def> = MOV64ri <ga:@BZ2_bzWrite>; GR64:%vreg14
176B		%vreg15<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg15
192B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
208B		%RDI<def> = COPY %vreg14<kill>; GR64:%vreg14
224B		%RSI<def> = COPY %vreg15<kill>; GR64:%vreg15
240B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
256B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
272B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
288B		STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg5, 0, <fi#2>, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#7>, 0, %vreg7, 0, <fi#3>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack0] LD8[FixedStack7] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) GR64:%vreg3,%vreg5,%vreg1 GR32:%vreg7
304B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
320B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1<kill>; mem:ST8[%bzerror.addr] GR64:%vreg1
336B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg3<kill>; mem:ST8[%b.addr] GR64:%vreg3
352B		MOV64mr <fi#2>, 1, %noreg, 0, %noreg, %vreg5<kill>; mem:ST8[%buf.addr] GR64:%vreg5
368B		MOV32mr <fi#3>, 1, %noreg, 0, %noreg, %vreg7<kill>; mem:ST4[%len.addr] GR32:%vreg7
384B		%vreg11<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr] GR64:%vreg11
416B		MOV64mr <fi#7>, 1, %noreg, 0, %noreg, %vreg11<kill>; mem:ST8[%bzf] GR64:%vreg11
432B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
448B		JE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1
> %R14D<def> = COPY %ECX
> %R15<def> = COPY %RDX
> %R12<def> = COPY %RSI
> %RBX<def> = COPY %RDI
> %RDI<def> = MOV64ri <ga:@BZ2_bzWrite>
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 0, 0, %R12, 0, <fi#1>, 0, %R15, 0, <fi#2>, 0, %RBX, 0, <fi#0>, 0, 0, <fi#7>, 0, %R14D, 0, <fi#3>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack0] LD8[FixedStack7] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %RBX<kill>; mem:ST8[%bzerror.addr]
> MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %R12<kill>; mem:ST8[%b.addr]
> MOV64mr <fi#2>, 1, %noreg, 0, %noreg, %R15<kill>; mem:ST8[%buf.addr]
> MOV32mr <fi#3>, 1, %noreg, 0, %noreg, %R14D<kill>; mem:ST4[%len.addr]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr]
> MOV64mr <fi#7>, 1, %noreg, 0, %noreg, %RAX<kill>; mem:ST8[%bzf]
> CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
> JE_1 <BB#2>, %EFLAGS<imp-use,kill>
464B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
480B		%vreg17<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg17
496B		MOV32mi %vreg17<kill>, 1, %noreg, 0, %noreg, 0; mem:ST4[%3] GR64:%vreg17
	    Successors according to CFG: BB#2
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 0, %noreg, 0; mem:ST4[%3]
512B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#1
528B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
544B		JE_1 <BB#4>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#4 BB#3
> CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
> JE_1 <BB#4>, %EFLAGS<imp-use,kill>
560B	BB#3: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#2
576B		%vreg20<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg20
592B		MOV32mi %vreg20<kill>, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr] GR64:%vreg20
	    Successors according to CFG: BB#4
> %RAX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV32mi %RAX<kill>, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr]
608B	BB#4: derived from LLVM BB %if.end.3
	    Predecessors according to CFG: BB#2 BB#3
624B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
640B		JE_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#5
> CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
> JE_1 <BB#7>, %EFLAGS<imp-use,kill>
656B	BB#5: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#4
672B		CMP64mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%buf.addr]
688B		JE_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#6
> CMP64mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%buf.addr]
> JE_1 <BB#7>, %EFLAGS<imp-use,kill>
704B	BB#6: derived from LLVM BB %lor.lhs.false.6
	    Predecessors according to CFG: BB#5
720B		CMP32mi8 <fi#3>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%len.addr]
736B		JGE_1 <BB#12>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#12 BB#7
> CMP32mi8 <fi#3>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%len.addr]
> JGE_1 <BB#12>, %EFLAGS<imp-use,kill>
752B	BB#7: derived from LLVM BB %if.then.8
	    Predecessors according to CFG: BB#4 BB#5 BB#6
768B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
784B		JE_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#8
> CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
> JE_1 <BB#9>, %EFLAGS<imp-use,kill>
800B	BB#8: derived from LLVM BB %if.then.10
	    Predecessors according to CFG: BB#7
816B		%vreg140<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg140
832B		MOV32mi %vreg140<kill>, 1, %noreg, 0, %noreg, -2; mem:ST4[%10] GR64:%vreg140
	    Successors according to CFG: BB#9
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 0, %noreg, -2; mem:ST4[%10]
848B	BB#9: derived from LLVM BB %if.end.11
	    Predecessors according to CFG: BB#7 BB#8
864B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
880B		JE_1 <BB#11>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#11 BB#10
> CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
> JE_1 <BB#11>, %EFLAGS<imp-use,kill>
896B	BB#10: derived from LLVM BB %if.then.13
	    Predecessors according to CFG: BB#9
912B		%vreg143<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg143
928B		MOV32mi %vreg143<kill>, 1, %noreg, 5096, %noreg, -2; mem:ST4[%lastErr14] GR64:%vreg143
	    Successors according to CFG: BB#11
> %RAX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV32mi %RAX<kill>, 1, %noreg, 5096, %noreg, -2; mem:ST4[%lastErr14]
944B	BB#11: derived from LLVM BB %if.end.15
	    Predecessors according to CFG: BB#9 BB#10
960B		JMP_1 <BB#53>
	    Successors according to CFG: BB#53
> JMP_1 <BB#53>
976B	BB#12: derived from LLVM BB %if.end.16
	    Predecessors according to CFG: BB#6
992B		%vreg26<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg26
1008B		CMP8mi %vreg26<kill>, 1, %noreg, 5012, %noreg, 0, %EFLAGS<imp-def>; mem:LD1[%writing] GR64:%vreg26
1024B		JNE_1 <BB#18>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#18 BB#13
> %RAX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> CMP8mi %RAX<kill>, 1, %noreg, 5012, %noreg, 0, %EFLAGS<imp-def>; mem:LD1[%writing]
> JNE_1 <BB#18>, %EFLAGS<imp-use,kill>
1040B	BB#13: derived from LLVM BB %if.then.17
	    Predecessors according to CFG: BB#12
1056B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
1072B		JE_1 <BB#15>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#15 BB#14
> CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
> JE_1 <BB#15>, %EFLAGS<imp-use,kill>
1088B	BB#14: derived from LLVM BB %if.then.19
	    Predecessors according to CFG: BB#13
1104B		%vreg29<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg29
1120B		MOV32mi %vreg29<kill>, 1, %noreg, 0, %noreg, -1; mem:ST4[%16] GR64:%vreg29
	    Successors according to CFG: BB#15
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 0, %noreg, -1; mem:ST4[%16]
1136B	BB#15: derived from LLVM BB %if.end.20
	    Predecessors according to CFG: BB#13 BB#14
1152B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
1168B		JE_1 <BB#17>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#17 BB#16
> CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
> JE_1 <BB#17>, %EFLAGS<imp-use,kill>
1184B	BB#16: derived from LLVM BB %if.then.22
	    Predecessors according to CFG: BB#15
1200B		%vreg32<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg32
1216B		MOV32mi %vreg32<kill>, 1, %noreg, 5096, %noreg, -1; mem:ST4[%lastErr23] GR64:%vreg32
	    Successors according to CFG: BB#17
> %RAX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV32mi %RAX<kill>, 1, %noreg, 5096, %noreg, -1; mem:ST4[%lastErr23]
1232B	BB#17: derived from LLVM BB %if.end.24
	    Predecessors according to CFG: BB#15 BB#16
1248B		JMP_1 <BB#53>
	    Successors according to CFG: BB#53
> JMP_1 <BB#53>
1264B	BB#18: derived from LLVM BB %if.end.25
	    Predecessors according to CFG: BB#12
1280B		%vreg38<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg38
1296B		%vreg37<def> = MOV64rm %vreg38<kill>, 1, %noreg, 0, %noreg; mem:LD8[%handle] GR64:%vreg37,%vreg38
1312B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1328B		%RDI<def> = COPY %vreg37<kill>; GR64:%vreg37
1344B		CALL64pcrel32 <ga:@ferror>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
1360B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1376B		%vreg35<def> = COPY %EAX; GR32:%vreg35
1392B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1408B		STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#7>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, ...; mem:LD8[FixedStack2] LD8[FixedStack0] LD8[FixedStack7] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4)
1424B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1440B		CMP32ri8 %vreg35<kill>, 0, %EFLAGS<imp-def>; GR32:%vreg35
1456B		JE_1 <BB#24>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#24 BB#19
> %RAX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> %RDI<def> = MOV64rm %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%handle]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@ferror>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def> = COPY %EAX
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#7>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, ...; mem:LD8[FixedStack2] LD8[FixedStack0] LD8[FixedStack7] LD8[FixedStack3](align=4) LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> CMP32ri8 %EAX<kill>, 0, %EFLAGS<imp-def>
> JE_1 <BB#24>, %EFLAGS<imp-use,kill>
1472B	BB#19: derived from LLVM BB %if.then.27
	    Predecessors according to CFG: BB#18
1488B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
1504B		JE_1 <BB#21>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#21 BB#20
> CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
> JE_1 <BB#21>, %EFLAGS<imp-use,kill>
1520B	BB#20: derived from LLVM BB %if.then.29
	    Predecessors according to CFG: BB#19
1536B		%vreg134<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg134
1552B		MOV32mi %vreg134<kill>, 1, %noreg, 0, %noreg, -6; mem:ST4[%22] GR64:%vreg134
	    Successors according to CFG: BB#21
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 0, %noreg, -6; mem:ST4[%22]
1568B	BB#21: derived from LLVM BB %if.end.30
	    Predecessors according to CFG: BB#19 BB#20
1584B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
1600B		JE_1 <BB#23>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#23 BB#22
> CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
> JE_1 <BB#23>, %EFLAGS<imp-use,kill>
1616B	BB#22: derived from LLVM BB %if.then.32
	    Predecessors according to CFG: BB#21
1632B		%vreg137<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg137
1648B		MOV32mi %vreg137<kill>, 1, %noreg, 5096, %noreg, -6; mem:ST4[%lastErr33] GR64:%vreg137
	    Successors according to CFG: BB#23
> %RAX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV32mi %RAX<kill>, 1, %noreg, 5096, %noreg, -6; mem:ST4[%lastErr33]
1664B	BB#23: derived from LLVM BB %if.end.34
	    Predecessors according to CFG: BB#21 BB#22
1680B		JMP_1 <BB#53>
	    Successors according to CFG: BB#53
> JMP_1 <BB#53>
1696B	BB#24: derived from LLVM BB %if.end.35
	    Predecessors according to CFG: BB#18
1712B		CMP32mi8 <fi#3>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%len.addr]
1728B		JNE_1 <BB#30>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#30 BB#25
> CMP32mi8 <fi#3>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%len.addr]
> JNE_1 <BB#30>, %EFLAGS<imp-use,kill>
1744B	BB#25: derived from LLVM BB %if.then.37
	    Predecessors according to CFG: BB#24
1760B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
1776B		JE_1 <BB#27>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#27 BB#26
> CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
> JE_1 <BB#27>, %EFLAGS<imp-use,kill>
1792B	BB#26: derived from LLVM BB %if.then.39
	    Predecessors according to CFG: BB#25
1808B		%vreg128<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg128
1824B		MOV32mi %vreg128<kill>, 1, %noreg, 0, %noreg, 0; mem:ST4[%27] GR64:%vreg128
	    Successors according to CFG: BB#27
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 0, %noreg, 0; mem:ST4[%27]
1840B	BB#27: derived from LLVM BB %if.end.40
	    Predecessors according to CFG: BB#25 BB#26
1856B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
1872B		JE_1 <BB#29>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#29 BB#28
> CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
> JE_1 <BB#29>, %EFLAGS<imp-use,kill>
1888B	BB#28: derived from LLVM BB %if.then.42
	    Predecessors according to CFG: BB#27
1904B		%vreg131<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg131
1920B		MOV32mi %vreg131<kill>, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr43] GR64:%vreg131
	    Successors according to CFG: BB#29
> %RAX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV32mi %RAX<kill>, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr43]
1936B	BB#29: derived from LLVM BB %if.end.44
	    Predecessors according to CFG: BB#27 BB#28
1952B		JMP_1 <BB#53>
	    Successors according to CFG: BB#53
> JMP_1 <BB#53>
1968B	BB#30: derived from LLVM BB %if.end.45
	    Predecessors according to CFG: BB#24
1984B		%vreg47<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%len.addr] GR32:%vreg47
2000B		%vreg46<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg46
2016B		MOV32mr %vreg46<kill>, 1, %noreg, 5024, %noreg, %vreg47<kill>; mem:ST4[%avail_in] GR64:%vreg46 GR32:%vreg47
2032B		%vreg43<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%buf.addr] GR64:%vreg43
2048B		%vreg42<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg42
2064B		MOV64mr %vreg42<kill>, 1, %noreg, 5016, %noreg, %vreg43<kill>; mem:ST8[%next_in] GR64:%vreg42,%vreg43
	    Successors according to CFG: BB#31
> %EAX<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%len.addr]
> %RCX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV32mr %RCX<kill>, 1, %noreg, 5024, %noreg, %EAX<kill>; mem:ST4[%avail_in]
> %RAX<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%buf.addr]
> %RCX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV64mr %RCX<kill>, 1, %noreg, 5016, %noreg, %RAX<kill>; mem:ST8[%next_in]
2080B	BB#31: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#30 BB#52
2112B		%vreg64<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg64
2128B		MOV32mi %vreg64<kill>, 1, %noreg, 5048, %noreg, 5000; mem:ST4[%avail_out] GR64:%vreg64
2144B		%vreg61<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg61
2176B		%vreg61<def,tied1> = ADD64ri8 %vreg61<kill,tied0>, 8, %EFLAGS<imp-def,dead>; GR64:%vreg61
2192B		%vreg58<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg58
2208B		MOV64mr %vreg58<kill>, 1, %noreg, 5040, %noreg, %vreg61<kill>; mem:ST8[%next_out] GR64:%vreg58,%vreg61
2224B		%vreg54<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg54
2256B		%vreg54<def,tied1> = ADD64ri32 %vreg54<kill,tied0>, 5016, %EFLAGS<imp-def,dead>; GR64:%vreg54
2272B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2304B		%ESI<def> = MOV32r0 %EFLAGS<imp-def,dead>
2312B		%RDI<def> = COPY %vreg54<kill>; GR64:%vreg54
2320B		CALL64pcrel32 <ga:@BZ2_bzCompress>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %EAX<imp-def>
2336B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2352B		%vreg52<def> = COPY %EAX; GR32:%vreg52
2368B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2384B		STACKMAP 2, 0, 0, <fi#0>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, ...; mem:LD8[FixedStack0] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4)
2400B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2416B		MOV32mr <fi#6>, 1, %noreg, 0, %noreg, %vreg52<kill>; mem:ST4[%ret] GR32:%vreg52
2432B		CMP32mi8 <fi#6>, 1, %noreg, 0, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%ret]
2448B		JE_1 <BB#37>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#37 BB#32
> %RAX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV32mi %RAX<kill>, 1, %noreg, 5048, %noreg, 5000; mem:ST4[%avail_out]
> %RAX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> %RAX<def,tied1> = ADD64ri8 %RAX<kill,tied0>, 8, %EFLAGS<imp-def,dead>
> %RCX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV64mr %RCX<kill>, 1, %noreg, 5040, %noreg, %RAX<kill>; mem:ST8[%next_out]
> %RDI<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> %RDI<def,tied1> = ADD64ri32 %RDI<kill,tied0>, 5016, %EFLAGS<imp-def,dead>
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %ESI<def> = MOV32r0 %EFLAGS<imp-def,dead>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@BZ2_bzCompress>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %EAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def> = COPY %EAX
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 2, 0, 0, <fi#0>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, ...; mem:LD8[FixedStack0] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV32mr <fi#6>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%ret]
> CMP32mi8 <fi#6>, 1, %noreg, 0, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%ret]
> JE_1 <BB#37>, %EFLAGS<imp-use,kill>
2464B	BB#32: derived from LLVM BB %if.then.53
	    Predecessors according to CFG: BB#31
2480B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
2496B		JE_1 <BB#34>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#34 BB#33
> CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
> JE_1 <BB#34>, %EFLAGS<imp-use,kill>
2512B	BB#33: derived from LLVM BB %if.then.55
	    Predecessors according to CFG: BB#32
2528B		%vreg120<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%ret] GR32:%vreg120
2544B		%vreg119<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg119
2560B		MOV32mr %vreg119<kill>, 1, %noreg, 0, %noreg, %vreg120<kill>; mem:ST4[%41] GR64:%vreg119 GR32:%vreg120
	    Successors according to CFG: BB#34
> %EAX<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%ret]
> %RCX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr]
> MOV32mr %RCX<kill>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%41]
2576B	BB#34: derived from LLVM BB %if.end.56
	    Predecessors according to CFG: BB#32 BB#33
2592B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
2608B		JE_1 <BB#36>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#36 BB#35
> CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
> JE_1 <BB#36>, %EFLAGS<imp-use,kill>
2624B	BB#35: derived from LLVM BB %if.then.58
	    Predecessors according to CFG: BB#34
2640B		%vreg125<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%ret] GR32:%vreg125
2656B		%vreg124<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg124
2672B		MOV32mr %vreg124<kill>, 1, %noreg, 5096, %noreg, %vreg125<kill>; mem:ST4[%lastErr59] GR64:%vreg124 GR32:%vreg125
	    Successors according to CFG: BB#36
> %EAX<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%ret]
> %RCX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV32mr %RCX<kill>, 1, %noreg, 5096, %noreg, %EAX<kill>; mem:ST4[%lastErr59]
2688B	BB#36: derived from LLVM BB %if.end.60
	    Predecessors according to CFG: BB#34 BB#35
2704B		JMP_1 <BB#53>
	    Successors according to CFG: BB#53
> JMP_1 <BB#53>
2720B	BB#37: derived from LLVM BB %if.end.61
	    Predecessors according to CFG: BB#31
2736B		%vreg67<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg67
2752B		CMP32mi %vreg67<kill>, 1, %noreg, 5048, %noreg, 5000, %EFLAGS<imp-def>; mem:LD4[%avail_out63] GR64:%vreg67
2768B		JAE_1 <BB#46>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#46 BB#38
> %RAX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> CMP32mi %RAX<kill>, 1, %noreg, 5048, %noreg, 5000, %EFLAGS<imp-def>; mem:LD4[%avail_out63]
> JAE_1 <BB#46>, %EFLAGS<imp-use,kill>
2784B	BB#38: derived from LLVM BB %if.then.65
	    Predecessors according to CFG: BB#37
2832B		%vreg92<def> = MOV32ri 5000; GR32:%vreg92
2848B		%vreg94<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg94
2880B		%vreg92<def,tied1> = SUB32rm %vreg92<kill,tied0>, %vreg94<kill>, 1, %noreg, 5048, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%avail_out67] GR32:%vreg92 GR64:%vreg94
2896B		MOV32mr <fi#4>, 1, %noreg, 0, %noreg, %vreg92<kill>; mem:ST4[%n] GR32:%vreg92
2912B		%vreg87<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg87
2944B		%vreg87<def,tied1> = ADD64ri8 %vreg87<kill,tied0>, 8, %EFLAGS<imp-def,dead>; GR64:%vreg87
2960B		%vreg84<def> = MOVSX64rm32 <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%n] GR64:%vreg84
2976B		%vreg82<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg82
2992B		%vreg81<def> = MOV64rm %vreg82<kill>, 1, %noreg, 0, %noreg; mem:LD8[%handle70] GR64:%vreg81,%vreg82
3008B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3040B		%ESI<def,dead> = MOV32ri 1, %RSI<imp-def>
3048B		%RDI<def> = COPY %vreg87<kill>; GR64:%vreg87
3056B		%RDX<def> = COPY %vreg84<kill>; GR64:%vreg84
3072B		%RCX<def> = COPY %vreg81<kill>; GR64:%vreg81
3088B		CALL64pcrel32 <ga:@fwrite>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %RDX<imp-use>, %RCX<imp-use>, %RAX<imp-def>
3104B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3120B		%vreg79<def> = COPY %RAX; GR64_with_sub_8bit:%vreg79
3136B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3152B		STACKMAP 3, 0, 0, <fi#0>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, ...; mem:LD8[FixedStack0] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4)
3168B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3200B		MOV32mr <fi#5>, 1, %noreg, 0, %noreg, %vreg79:sub_32bit<kill>; mem:ST4[%n2] GR64_with_sub_8bit:%vreg79
3216B		%vreg70<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%n] GR32:%vreg70
3232B		CMP32rm %vreg70<kill>, <fi#5>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD4[%n2] GR32:%vreg70
3248B		JNE_1 <BB#40>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#40 BB#39
> %EAX<def> = MOV32ri 5000
> %RCX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> %EAX<def,tied1> = SUB32rm %EAX<kill,tied0>, %RCX<kill>, 1, %noreg, 5048, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%avail_out67]
> MOV32mr <fi#4>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%n]
> %RDI<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> %RDI<def,tied1> = ADD64ri8 %RDI<kill,tied0>, 8, %EFLAGS<imp-def,dead>
> %RDX<def> = MOVSX64rm32 <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%n]
> %RAX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> %RCX<def> = MOV64rm %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%handle70]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %ESI<def,dead> = MOV32ri 1, %RSI<imp-def>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RDX<def> = COPY %RDX<kill>
Deleting identity copy.
> %RCX<def> = COPY %RCX<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@fwrite>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %RDX<imp-use>, %RCX<imp-use>, %RAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RAX<def> = COPY %RAX
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 3, 0, 0, <fi#0>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, ...; mem:LD8[FixedStack0] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV32mr <fi#5>, 1, %noreg, 0, %noreg, %EAX, %RAX<imp-use,kill>; mem:ST4[%n2]
> %EAX<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%n]
> CMP32rm %EAX<kill>, <fi#5>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD4[%n2]
> JNE_1 <BB#40>, %EFLAGS<imp-use,kill>
3264B	BB#39: derived from LLVM BB %lor.lhs.false.75
	    Predecessors according to CFG: BB#38
3280B		%vreg100<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg100
3296B		%vreg99<def> = MOV64rm %vreg100<kill>, 1, %noreg, 0, %noreg; mem:LD8[%handle76] GR64:%vreg99,%vreg100
3312B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3328B		%RDI<def> = COPY %vreg99<kill>; GR64:%vreg99
3344B		CALL64pcrel32 <ga:@ferror>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
3360B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3376B		%vreg97<def> = COPY %EAX; GR32:%vreg97
3392B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3408B		STACKMAP 4, 0, 0, <fi#0>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, ...; mem:LD8[FixedStack0] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4)
3424B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3440B		CMP32ri8 %vreg97<kill>, 0, %EFLAGS<imp-def>; GR32:%vreg97
3456B		JE_1 <BB#45>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#45 BB#40
> %RAX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> %RDI<def> = MOV64rm %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%handle76]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@ferror>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def> = COPY %EAX
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 4, 0, 0, <fi#0>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, ...; mem:LD8[FixedStack0] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> CMP32ri8 %EAX<kill>, 0, %EFLAGS<imp-def>
> JE_1 <BB#45>, %EFLAGS<imp-use,kill>
3472B	BB#40: derived from LLVM BB %if.then.79
	    Predecessors according to CFG: BB#38 BB#39
3488B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
3504B		JE_1 <BB#42>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#42 BB#41
> CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
> JE_1 <BB#42>, %EFLAGS<imp-use,kill>
3520B	BB#41: derived from LLVM BB %if.then.82
	    Predecessors according to CFG: BB#40
3536B		%vreg112<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg112
3552B		MOV32mi %vreg112<kill>, 1, %noreg, 0, %noreg, -6; mem:ST4[%58] GR64:%vreg112
	    Successors according to CFG: BB#42
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 0, %noreg, -6; mem:ST4[%58]
3568B	BB#42: derived from LLVM BB %if.end.83
	    Predecessors according to CFG: BB#40 BB#41
3584B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
3600B		JE_1 <BB#44>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#44 BB#43
> CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
> JE_1 <BB#44>, %EFLAGS<imp-use,kill>
3616B	BB#43: derived from LLVM BB %if.then.86
	    Predecessors according to CFG: BB#42
3632B		%vreg115<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg115
3648B		MOV32mi %vreg115<kill>, 1, %noreg, 5096, %noreg, -6; mem:ST4[%lastErr87] GR64:%vreg115
	    Successors according to CFG: BB#44
> %RAX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV32mi %RAX<kill>, 1, %noreg, 5096, %noreg, -6; mem:ST4[%lastErr87]
3664B	BB#44: derived from LLVM BB %if.end.88
	    Predecessors according to CFG: BB#42 BB#43
3680B		JMP_1 <BB#53>
	    Successors according to CFG: BB#53
> JMP_1 <BB#53>
3696B	BB#45: derived from LLVM BB %if.end.89
	    Predecessors according to CFG: BB#39
3712B		JMP_1 <BB#46>
	    Successors according to CFG: BB#46
> JMP_1 <BB#46>
3728B	BB#46: derived from LLVM BB %if.end.90
	    Predecessors according to CFG: BB#37 BB#45
3744B		%vreg103<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg103
3760B		CMP32mi8 %vreg103<kill>, 1, %noreg, 5024, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_in92] GR64:%vreg103
3776B		JNE_1 <BB#52>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#52 BB#47
> %RAX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> CMP32mi8 %RAX<kill>, 1, %noreg, 5024, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_in92]
> JNE_1 <BB#52>, %EFLAGS<imp-use,kill>
3792B	BB#47: derived from LLVM BB %if.then.95
	    Predecessors according to CFG: BB#46
3808B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
3824B		JE_1 <BB#49>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#49 BB#48
> CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
> JE_1 <BB#49>, %EFLAGS<imp-use,kill>
3840B	BB#48: derived from LLVM BB %if.then.98
	    Predecessors according to CFG: BB#47
3856B		%vreg106<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg106
3872B		MOV32mi %vreg106<kill>, 1, %noreg, 0, %noreg, 0; mem:ST4[%64] GR64:%vreg106
	    Successors according to CFG: BB#49
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 0, %noreg, 0; mem:ST4[%64]
3888B	BB#49: derived from LLVM BB %if.end.99
	    Predecessors according to CFG: BB#47 BB#48
3904B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
3920B		JE_1 <BB#51>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#51 BB#50
> CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
> JE_1 <BB#51>, %EFLAGS<imp-use,kill>
3936B	BB#50: derived from LLVM BB %if.then.102
	    Predecessors according to CFG: BB#49
3952B		%vreg109<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg109
3968B		MOV32mi %vreg109<kill>, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr103] GR64:%vreg109
	    Successors according to CFG: BB#51
> %RAX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV32mi %RAX<kill>, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr103]
3984B	BB#51: derived from LLVM BB %if.end.104
	    Predecessors according to CFG: BB#49 BB#50
4000B		JMP_1 <BB#53>
	    Successors according to CFG: BB#53
> JMP_1 <BB#53>
4016B	BB#52: derived from LLVM BB %if.end.105
	    Predecessors according to CFG: BB#46
4032B		JMP_1 <BB#31>
	    Successors according to CFG: BB#31
> JMP_1 <BB#31>
4048B	BB#53: derived from LLVM BB %return
	    Predecessors according to CFG: BB#17 BB#51 BB#44 BB#36 BB#29 BB#23 BB#11
4064B		%vreg145<def> = MOV64ri <ga:@BZ2_bzWrite>; GR64:%vreg145
4096B		%vreg146<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg146
4112B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4128B		%RDI<def> = COPY %vreg145<kill>; GR64:%vreg145
4144B		%RSI<def> = COPY %vreg146<kill>; GR64:%vreg146
4160B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
4176B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4192B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4208B		STACKMAP 5, 0, ...
4224B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4240B		RETQ
> %RDI<def> = MOV64ri <ga:@BZ2_bzWrite>
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 5, 0, ...
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> RETQ
Computing live-in reg-units in ABI blocks.
0B	BB#0 DIL#0 SIL#0 DH#0 DL#0 CH#0 CL#0 R8B#0
Created 7 new intervals.
********** INTERVALS **********
CH [0B,32r:0)[608r,672r:1)  0@0B-phi 1@608r
CL [0B,32r:0)[608r,672r:1)  0@0B-phi 1@608r
DH [0B,48r:0)[592r,672r:1)  0@0B-phi 1@592r
DIL [0B,80r:0)[240r,272r:1)[560r,672r:2)[816r,848r:3)  0@0B-phi 1@240r 2@560r 3@816r
DL [0B,48r:0)[592r,672r:1)  0@0B-phi 1@592r
SIL [0B,64r:0)[256r,272r:1)[576r,672r:2)[832r,848r:3)  0@0B-phi 1@256r 2@576r 3@832r
R8B [0B,16r:0)[624r,672r:1)  0@0B-phi 1@624r
%vreg0 [80r,96r:0)  0@80r
%vreg1 [96r,384r:0)  0@96r
%vreg2 [64r,112r:0)  0@64r
%vreg3 [112r,400r:0)  0@112r
%vreg4 [48r,128r:0)  0@48r
%vreg5 [128r,416r:0)  0@128r
%vreg6 [32r,144r:0)  0@32r
%vreg7 [144r,432r:0)  0@144r
%vreg8 [16r,160r:0)  0@16r
%vreg9 [160r,448r:0)  0@160r
%vreg10 [704r,720r:0)  0@704r
%vreg11 [720r,816r:0)  0@720r
%vreg12 [784r,832r:0)  0@784r
%vreg17 [304r,320r:0)  0@304r
%vreg18 [320r,624r:0)  0@320r
%vreg20 [528r,640r:0)  0@528r
%vreg21 [512r,608r:0)  0@512r
%vreg22 [496r,592r:0)  0@496r
%vreg23 [480r,576r:0)  0@480r
%vreg24 [464r,560r:0)  0@464r
%vreg25 [176r,192r:0)  0@176r
%vreg26 [192r,240r:0)  0@192r
%vreg27 [208r,256r:0)  0@208r
RegMasks: 272r 672r 848r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzWriteClose: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=8, align=8, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=4, align=4, at location [SP+8]
  fi#3: size=8, align=8, at location [SP+8]
  fi#4: size=8, align=8, at location [SP+8]
Function Live Ins: %RDI in %vreg0, %RSI in %vreg2, %EDX in %vreg4, %RCX in %vreg6, %R8 in %vreg8

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI %RSI %EDX %RCX %R8
16B		%vreg8<def> = COPY %R8; GR64:%vreg8
32B		%vreg6<def> = COPY %RCX; GR64:%vreg6
48B		%vreg4<def> = COPY %EDX; GR32:%vreg4
64B		%vreg2<def> = COPY %RSI; GR64:%vreg2
80B		%vreg0<def> = COPY %RDI; GR64:%vreg0
96B		%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
112B		%vreg3<def> = COPY %vreg2; GR64:%vreg3,%vreg2
128B		%vreg5<def> = COPY %vreg4; GR32:%vreg5,%vreg4
144B		%vreg7<def> = COPY %vreg6; GR64:%vreg7,%vreg6
160B		%vreg9<def> = COPY %vreg8; GR64:%vreg9,%vreg8
176B		%vreg25<def> = MOV64ri <ga:@BZ2_bzWriteClose>; GR64:%vreg25
192B		%vreg26<def> = COPY %vreg25; GR64:%vreg26,%vreg25
208B		%vreg27<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg27
224B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
240B		%RDI<def> = COPY %vreg26; GR64:%vreg26
256B		%RSI<def> = COPY %vreg27; GR64:%vreg27
272B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
288B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
304B		%vreg17<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg17
320B		%vreg18<def> = SUBREG_TO_REG 0, %vreg17, 4; GR64:%vreg18 GR32:%vreg17
336B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
352B		STACKMAP 0, 0, %vreg5, 0, <fi#2>, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, %vreg7, 0, <fi#3>, 0, %vreg9, 0, <fi#4>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack3] LD8[FixedStack4] GR32:%vreg5 GR64:%vreg3,%vreg1,%vreg7,%vreg9
368B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
384B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%bzerror.addr] GR64:%vreg1
400B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg3; mem:ST8[%b.addr] GR64:%vreg3
416B		MOV32mr <fi#2>, 1, %noreg, 0, %noreg, %vreg5; mem:ST4[%abandon.addr] GR32:%vreg5
432B		MOV64mr <fi#3>, 1, %noreg, 0, %noreg, %vreg7; mem:ST8[%nbytes_in.addr] GR64:%vreg7
448B		MOV64mr <fi#4>, 1, %noreg, 0, %noreg, %vreg9; mem:ST8[%nbytes_out.addr] GR64:%vreg9
464B		%vreg24<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg24
480B		%vreg23<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr] GR64:%vreg23
496B		%vreg22<def> = MOV32rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD4[%abandon.addr] GR32:%vreg22
512B		%vreg21<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%nbytes_in.addr] GR64:%vreg21
528B		%vreg20<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%nbytes_out.addr] GR64:%vreg20
544B		ADJCALLSTACKDOWN64 8, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
560B		%RDI<def> = COPY %vreg24; GR64:%vreg24
576B		%RSI<def> = COPY %vreg23; GR64:%vreg23
592B		%EDX<def> = COPY %vreg22; GR32:%vreg22
608B		%RCX<def> = COPY %vreg21; GR64:%vreg21
624B		%R8<def> = COPY %vreg18; GR64:%vreg18
640B		%R9<def> = COPY %vreg20; GR64:%vreg20
656B		MOV64mi32 %RSP, 1, %noreg, 0, %noreg, 0; mem:ST8[Stack]
672B		CALL64pcrel32 <ga:@BZ2_bzWriteClose64>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %EDX<imp-use>, %RCX<imp-use>, %R8<imp-use>, %R9<imp-use,kill>
688B		ADJCALLSTACKUP64 8, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
704B		%vreg10<def> = MOV64ri <ga:@BZ2_bzWriteClose>; GR64:%vreg10
720B		%vreg11<def> = COPY %vreg10; GR64:%vreg11,%vreg10
736B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
752B		STACKMAP 1, 0, ...
768B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
784B		%vreg12<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg12
800B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
816B		%RDI<def> = COPY %vreg11; GR64:%vreg11
832B		%RSI<def> = COPY %vreg12; GR64:%vreg12
848B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
864B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
880B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
896B		STACKMAP 2, 0, ...
912B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
928B		RETQ

# End machine code for function BZ2_bzWriteClose.

********** SIMPLE REGISTER COALESCING **********
********** Function: BZ2_bzWriteClose
********** JOINING INTERVALS ***********
entry:
16B	%vreg8<def> = COPY %R8; GR64:%vreg8
	Considering merging %vreg8 with %R8
	Can only merge into reserved registers.
32B	%vreg6<def> = COPY %RCX; GR64:%vreg6
	Considering merging %vreg6 with %RCX
	Can only merge into reserved registers.
48B	%vreg4<def> = COPY %EDX; GR32:%vreg4
	Considering merging %vreg4 with %EDX
	Can only merge into reserved registers.
64B	%vreg2<def> = COPY %RSI; GR64:%vreg2
	Considering merging %vreg2 with %RSI
	Can only merge into reserved registers.
80B	%vreg0<def> = COPY %RDI; GR64:%vreg0
	Considering merging %vreg0 with %RDI
	Can only merge into reserved registers.
240B	%RDI<def> = COPY %vreg26; GR64:%vreg26
	Considering merging %vreg26 with %RDI
	Can only merge into reserved registers.
256B	%RSI<def> = COPY %vreg27; GR64:%vreg27
	Considering merging %vreg27 with %RSI
	Can only merge into reserved registers.
320B	%vreg18<def> = SUBREG_TO_REG 0, %vreg17, 4; GR64:%vreg18 GR32:%vreg17
	Considering merging to GR64_with_sub_8bit with %vreg17 in %vreg18:sub_32bit
		RHS = %vreg17 [304r,320r:0)  0@304r
		LHS = %vreg18 [320r,624r:0)  0@320r
		merge %vreg18:0@320r into %vreg17:0@304r --> @304r
		erased:	320r	%vreg18<def> = SUBREG_TO_REG 0, %vreg17, 4; GR64:%vreg18 GR32:%vreg17
		updated: 304B	%vreg18:sub_32bit<def,read-undef> = MOV32r0 %EFLAGS<imp-def,dead>; GR64_with_sub_8bit:%vreg18
	Success: %vreg17:sub_32bit -> %vreg18
	Result = %vreg18 [304r,624r:0)  0@304r
560B	%RDI<def> = COPY %vreg24; GR64:%vreg24
	Considering merging %vreg24 with %RDI
	Can only merge into reserved registers.
576B	%RSI<def> = COPY %vreg23; GR64:%vreg23
	Considering merging %vreg23 with %RSI
	Can only merge into reserved registers.
592B	%EDX<def> = COPY %vreg22; GR32:%vreg22
	Considering merging %vreg22 with %EDX
	Can only merge into reserved registers.
608B	%RCX<def> = COPY %vreg21; GR64:%vreg21
	Considering merging %vreg21 with %RCX
	Can only merge into reserved registers.
624B	%R8<def> = COPY %vreg18; GR64_with_sub_8bit:%vreg18
	Considering merging %vreg18 with %R8
	Can only merge into reserved registers.
Remat: %R8D<def,dead> = MOV32r0 %EFLAGS<imp-def,dead>, %R8<imp-def>
Shrink: %vreg18 [304r,624r:0)  0@304r
All defs dead: 304r	%vreg18:sub_32bit<def,read-undef,dead> = MOV32r0 %EFLAGS<imp-def,dead>; GR64_with_sub_8bit:%vreg18
Shrunk: %vreg18 [304r,304d:0)  0@304r
Deleting dead def 304r	%vreg18:sub_32bit<def,read-undef,dead> = MOV32r0 %EFLAGS<imp-def,dead>; GR64_with_sub_8bit:%vreg18
640B	%R9<def> = COPY %vreg20; GR64:%vreg20
	Considering merging %vreg20 with %R9
	Can only merge into reserved registers.
816B	%RDI<def> = COPY %vreg11; GR64:%vreg11
	Considering merging %vreg11 with %RDI
	Can only merge into reserved registers.
832B	%RSI<def> = COPY %vreg12; GR64:%vreg12
	Considering merging %vreg12 with %RSI
	Can only merge into reserved registers.
96B	%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
	Considering merging to GR64 with %vreg0 in %vreg1
		RHS = %vreg0 [80r,96r:0)  0@80r
		LHS = %vreg1 [96r,384r:0)  0@96r
		merge %vreg1:0@96r into %vreg0:0@80r --> @80r
		erased:	96r	%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
		updated: 80B	%vreg1<def> = COPY %RDI; GR64:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [80r,384r:0)  0@80r
112B	%vreg3<def> = COPY %vreg2; GR64:%vreg3,%vreg2
	Considering merging to GR64 with %vreg2 in %vreg3
		RHS = %vreg2 [64r,112r:0)  0@64r
		LHS = %vreg3 [112r,400r:0)  0@112r
		merge %vreg3:0@112r into %vreg2:0@64r --> @64r
		erased:	112r	%vreg3<def> = COPY %vreg2; GR64:%vreg3,%vreg2
		updated: 64B	%vreg3<def> = COPY %RSI; GR64:%vreg3
	Success: %vreg2 -> %vreg3
	Result = %vreg3 [64r,400r:0)  0@64r
128B	%vreg5<def> = COPY %vreg4; GR32:%vreg5,%vreg4
	Considering merging to GR32 with %vreg4 in %vreg5
		RHS = %vreg4 [48r,128r:0)  0@48r
		LHS = %vreg5 [128r,416r:0)  0@128r
		merge %vreg5:0@128r into %vreg4:0@48r --> @48r
		erased:	128r	%vreg5<def> = COPY %vreg4; GR32:%vreg5,%vreg4
		updated: 48B	%vreg5<def> = COPY %EDX; GR32:%vreg5
	Success: %vreg4 -> %vreg5
	Result = %vreg5 [48r,416r:0)  0@48r
144B	%vreg7<def> = COPY %vreg6; GR64:%vreg7,%vreg6
	Considering merging to GR64 with %vreg6 in %vreg7
		RHS = %vreg6 [32r,144r:0)  0@32r
		LHS = %vreg7 [144r,432r:0)  0@144r
		merge %vreg7:0@144r into %vreg6:0@32r --> @32r
		erased:	144r	%vreg7<def> = COPY %vreg6; GR64:%vreg7,%vreg6
		updated: 32B	%vreg7<def> = COPY %RCX; GR64:%vreg7
	Success: %vreg6 -> %vreg7
	Result = %vreg7 [32r,432r:0)  0@32r
160B	%vreg9<def> = COPY %vreg8; GR64:%vreg9,%vreg8
	Considering merging to GR64 with %vreg8 in %vreg9
		RHS = %vreg8 [16r,160r:0)  0@16r
		LHS = %vreg9 [160r,448r:0)  0@160r
		merge %vreg9:0@160r into %vreg8:0@16r --> @16r
		erased:	160r	%vreg9<def> = COPY %vreg8; GR64:%vreg9,%vreg8
		updated: 16B	%vreg9<def> = COPY %R8; GR64:%vreg9
	Success: %vreg8 -> %vreg9
	Result = %vreg9 [16r,448r:0)  0@16r
192B	%vreg26<def> = COPY %vreg25; GR64:%vreg26,%vreg25
	Considering merging to GR64 with %vreg25 in %vreg26
		RHS = %vreg25 [176r,192r:0)  0@176r
		LHS = %vreg26 [192r,240r:0)  0@192r
		merge %vreg26:0@192r into %vreg25:0@176r --> @176r
		erased:	192r	%vreg26<def> = COPY %vreg25; GR64:%vreg26,%vreg25
		updated: 176B	%vreg26<def> = MOV64ri <ga:@BZ2_bzWriteClose>; GR64:%vreg26
	Success: %vreg25 -> %vreg26
	Result = %vreg26 [176r,240r:0)  0@176r
720B	%vreg11<def> = COPY %vreg10; GR64:%vreg11,%vreg10
	Considering merging to GR64 with %vreg10 in %vreg11
		RHS = %vreg10 [704r,720r:0)  0@704r
		LHS = %vreg11 [720r,816r:0)  0@720r
		merge %vreg11:0@720r into %vreg10:0@704r --> @704r
		erased:	720r	%vreg11<def> = COPY %vreg10; GR64:%vreg11,%vreg10
		updated: 704B	%vreg11<def> = MOV64ri <ga:@BZ2_bzWriteClose>; GR64:%vreg11
	Success: %vreg10 -> %vreg11
	Result = %vreg11 [704r,816r:0)  0@704r
240B	%RDI<def> = COPY %vreg26; GR64:%vreg26
	Considering merging %vreg26 with %RDI
	Can only merge into reserved registers.
816B	%RDI<def> = COPY %vreg11; GR64:%vreg11
	Considering merging %vreg11 with %RDI
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
CH [0B,32r:0)[608r,672r:1)  0@0B-phi 1@608r
CL [0B,32r:0)[608r,672r:1)  0@0B-phi 1@608r
DH [0B,48r:0)[592r,672r:1)  0@0B-phi 1@592r
DIL [0B,80r:0)[240r,272r:1)[560r,672r:2)[816r,848r:3)  0@0B-phi 1@240r 2@560r 3@816r
DL [0B,48r:0)[592r,672r:1)  0@0B-phi 1@592r
SIL [0B,64r:0)[256r,272r:1)[576r,672r:2)[832r,848r:3)  0@0B-phi 1@256r 2@576r 3@832r
R8B [0B,16r:0)[624r,672r:1)  0@0B-phi 1@624r
%vreg1 [80r,384r:0)  0@80r
%vreg3 [64r,400r:0)  0@64r
%vreg5 [48r,416r:0)  0@48r
%vreg7 [32r,432r:0)  0@32r
%vreg9 [16r,448r:0)  0@16r
%vreg11 [704r,816r:0)  0@704r
%vreg12 [784r,832r:0)  0@784r
%vreg20 [528r,640r:0)  0@528r
%vreg21 [512r,608r:0)  0@512r
%vreg22 [496r,592r:0)  0@496r
%vreg23 [480r,576r:0)  0@480r
%vreg24 [464r,560r:0)  0@464r
%vreg26 [176r,240r:0)  0@176r
%vreg27 [208r,256r:0)  0@208r
RegMasks: 272r 672r 848r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzWriteClose: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=8, align=8, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=4, align=4, at location [SP+8]
  fi#3: size=8, align=8, at location [SP+8]
  fi#4: size=8, align=8, at location [SP+8]
Function Live Ins: %RDI in %vreg0, %RSI in %vreg2, %EDX in %vreg4, %RCX in %vreg6, %R8 in %vreg8

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI %RSI %EDX %RCX %R8
16B		%vreg9<def> = COPY %R8; GR64:%vreg9
32B		%vreg7<def> = COPY %RCX; GR64:%vreg7
48B		%vreg5<def> = COPY %EDX; GR32:%vreg5
64B		%vreg3<def> = COPY %RSI; GR64:%vreg3
80B		%vreg1<def> = COPY %RDI; GR64:%vreg1
176B		%vreg26<def> = MOV64ri <ga:@BZ2_bzWriteClose>; GR64:%vreg26
208B		%vreg27<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg27
224B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
240B		%RDI<def> = COPY %vreg26; GR64:%vreg26
256B		%RSI<def> = COPY %vreg27; GR64:%vreg27
272B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
288B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
336B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
352B		STACKMAP 0, 0, %vreg5, 0, <fi#2>, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, %vreg7, 0, <fi#3>, 0, %vreg9, 0, <fi#4>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack3] LD8[FixedStack4] GR32:%vreg5 GR64:%vreg3,%vreg1,%vreg7,%vreg9
368B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
384B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%bzerror.addr] GR64:%vreg1
400B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg3; mem:ST8[%b.addr] GR64:%vreg3
416B		MOV32mr <fi#2>, 1, %noreg, 0, %noreg, %vreg5; mem:ST4[%abandon.addr] GR32:%vreg5
432B		MOV64mr <fi#3>, 1, %noreg, 0, %noreg, %vreg7; mem:ST8[%nbytes_in.addr] GR64:%vreg7
448B		MOV64mr <fi#4>, 1, %noreg, 0, %noreg, %vreg9; mem:ST8[%nbytes_out.addr] GR64:%vreg9
464B		%vreg24<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg24
480B		%vreg23<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr] GR64:%vreg23
496B		%vreg22<def> = MOV32rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD4[%abandon.addr] GR32:%vreg22
512B		%vreg21<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%nbytes_in.addr] GR64:%vreg21
528B		%vreg20<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%nbytes_out.addr] GR64:%vreg20
544B		ADJCALLSTACKDOWN64 8, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
560B		%RDI<def> = COPY %vreg24; GR64:%vreg24
576B		%RSI<def> = COPY %vreg23; GR64:%vreg23
592B		%EDX<def> = COPY %vreg22; GR32:%vreg22
608B		%RCX<def> = COPY %vreg21; GR64:%vreg21
624B		%R8D<def,dead> = MOV32r0 %EFLAGS<imp-def,dead>, %R8<imp-def>
640B		%R9<def> = COPY %vreg20; GR64:%vreg20
656B		MOV64mi32 %RSP, 1, %noreg, 0, %noreg, 0; mem:ST8[Stack]
672B		CALL64pcrel32 <ga:@BZ2_bzWriteClose64>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %EDX<imp-use>, %RCX<imp-use>, %R8<imp-use>, %R9<imp-use,kill>
688B		ADJCALLSTACKUP64 8, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
704B		%vreg11<def> = MOV64ri <ga:@BZ2_bzWriteClose>; GR64:%vreg11
736B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
752B		STACKMAP 1, 0, ...
768B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
784B		%vreg12<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg12
800B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
816B		%RDI<def> = COPY %vreg11; GR64:%vreg11
832B		%RSI<def> = COPY %vreg12; GR64:%vreg12
848B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
864B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
880B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
896B		STACKMAP 2, 0, ...
912B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
928B		RETQ

# End machine code for function BZ2_bzWriteClose.

handleMove 640B -> 664B: %R9<def> = COPY %vreg20; GR64:%vreg20
     R9B:	[664r,672r:0)  0@664r
        -->	[664r,672r:0)  0@664r
     %vreg20:	[528r,640r:0)  0@528r
        -->	[528r,664r:0)  0@528r
handleMove 608B -> 660B: %RCX<def> = COPY %vreg21; GR64:%vreg21
     CH:	[0B,32r:0)[608r,672r:1)  0@0B-phi 1@608r
        -->	[0B,32r:0)[660r,672r:1)  0@0B-phi 1@660r
     CL:	[0B,32r:0)[608r,672r:1)  0@0B-phi 1@608r
        -->	[0B,32r:0)[660r,672r:1)  0@0B-phi 1@660r
     %vreg21:	[512r,608r:0)  0@512r
        -->	[512r,660r:0)  0@512r
handleMove 592B -> 664B: %EDX<def> = COPY %vreg22; GR32:%vreg22
     DH:	[0B,48r:0)[592r,688r:1)  0@0B-phi 1@592r
        -->	[0B,48r:0)[664r,688r:1)  0@0B-phi 1@664r
     DL:	[0B,48r:0)[592r,688r:1)  0@0B-phi 1@592r
        -->	[0B,48r:0)[664r,688r:1)  0@0B-phi 1@664r
     %vreg22:	[496r,592r:0)  0@496r
        -->	[496r,664r:0)  0@496r
handleMove 576B -> 660B: %RSI<def> = COPY %vreg23; GR64:%vreg23
     SIL:	[0B,64r:0)[256r,272r:1)[576r,688r:2)[832r,848r:3)  0@0B-phi 1@256r 2@576r 3@832r
        -->	[0B,64r:0)[256r,272r:1)[660r,688r:2)[832r,848r:3)  0@0B-phi 1@256r 2@660r 3@832r
     %vreg23:	[480r,576r:0)  0@480r
        -->	[480r,660r:0)  0@480r
handleMove 560B -> 664B: %RDI<def> = COPY %vreg24; GR64:%vreg24
     DIL:	[0B,80r:0)[240r,272r:1)[560r,704r:2)[816r,848r:3)  0@0B-phi 1@240r 2@560r 3@816r
        -->	[0B,80r:0)[240r,272r:1)[664r,704r:2)[816r,848r:3)  0@0B-phi 1@240r 2@664r 3@816r
     %vreg24:	[464r,560r:0)  0@464r
        -->	[464r,664r:0)  0@464r
AllocationOrder(SEGMENT_REG) = [ ]
********** GREEDY REGISTER ALLOCATION **********
********** Function: BZ2_bzWriteClose
********** INTERVALS **********
CH [0B,32r:0)[688r,704r:1)  0@0B-phi 1@688r
CL [0B,32r:0)[688r,704r:1)  0@0B-phi 1@688r
DH [0B,48r:0)[680r,704r:1)  0@0B-phi 1@680r
DIL [0B,80r:0)[240r,272r:1)[664r,704r:2)[816r,848r:3)  0@0B-phi 1@240r 2@664r 3@816r
DL [0B,48r:0)[680r,704r:1)  0@0B-phi 1@680r
SIL [0B,64r:0)[256r,272r:1)[672r,704r:2)[832r,848r:3)  0@0B-phi 1@256r 2@672r 3@832r
R8B [0B,16r:0)[624r,704r:1)  0@0B-phi 1@624r
R9B [696r,704r:0)  0@696r
%vreg1 [80r,384r:0)  0@80r
%vreg3 [64r,400r:0)  0@64r
%vreg5 [48r,416r:0)  0@48r
%vreg7 [32r,432r:0)  0@32r
%vreg9 [16r,448r:0)  0@16r
%vreg11 [720r,816r:0)  0@720r
%vreg12 [784r,832r:0)  0@784r
%vreg20 [528r,696r:0)  0@528r
%vreg21 [512r,688r:0)  0@512r
%vreg22 [496r,680r:0)  0@496r
%vreg23 [480r,672r:0)  0@480r
%vreg24 [464r,664r:0)  0@464r
%vreg26 [176r,240r:0)  0@176r
%vreg27 [208r,256r:0)  0@208r
RegMasks: 272r 704r 848r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzWriteClose: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=8, align=8, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=4, align=4, at location [SP+8]
  fi#3: size=8, align=8, at location [SP+8]
  fi#4: size=8, align=8, at location [SP+8]
Function Live Ins: %RDI in %vreg0, %RSI in %vreg2, %EDX in %vreg4, %RCX in %vreg6, %R8 in %vreg8

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI %RSI %EDX %RCX %R8
16B		%vreg9<def> = COPY %R8; GR64:%vreg9
32B		%vreg7<def> = COPY %RCX; GR64:%vreg7
48B		%vreg5<def> = COPY %EDX; GR32:%vreg5
64B		%vreg3<def> = COPY %RSI; GR64:%vreg3
80B		%vreg1<def> = COPY %RDI; GR64:%vreg1
176B		%vreg26<def> = MOV64ri <ga:@BZ2_bzWriteClose>; GR64:%vreg26
208B		%vreg27<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg27
224B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
240B		%RDI<def> = COPY %vreg26; GR64:%vreg26
256B		%RSI<def> = COPY %vreg27; GR64:%vreg27
272B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
288B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
336B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
352B		STACKMAP 0, 0, %vreg5, 0, <fi#2>, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, %vreg7, 0, <fi#3>, 0, %vreg9, 0, <fi#4>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack3] LD8[FixedStack4] GR32:%vreg5 GR64:%vreg3,%vreg1,%vreg7,%vreg9
368B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
384B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%bzerror.addr] GR64:%vreg1
400B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg3; mem:ST8[%b.addr] GR64:%vreg3
416B		MOV32mr <fi#2>, 1, %noreg, 0, %noreg, %vreg5; mem:ST4[%abandon.addr] GR32:%vreg5
432B		MOV64mr <fi#3>, 1, %noreg, 0, %noreg, %vreg7; mem:ST8[%nbytes_in.addr] GR64:%vreg7
448B		MOV64mr <fi#4>, 1, %noreg, 0, %noreg, %vreg9; mem:ST8[%nbytes_out.addr] GR64:%vreg9
464B		%vreg24<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg24
480B		%vreg23<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr] GR64:%vreg23
496B		%vreg22<def> = MOV32rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD4[%abandon.addr] GR32:%vreg22
512B		%vreg21<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%nbytes_in.addr] GR64:%vreg21
528B		%vreg20<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%nbytes_out.addr] GR64:%vreg20
544B		ADJCALLSTACKDOWN64 8, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
624B		%R8D<def,dead> = MOV32r0 %EFLAGS<imp-def,dead>, %R8<imp-def>
656B		MOV64mi32 %RSP, 1, %noreg, 0, %noreg, 0; mem:ST8[Stack]
664B		%RDI<def> = COPY %vreg24; GR64:%vreg24
672B		%RSI<def> = COPY %vreg23; GR64:%vreg23
680B		%EDX<def> = COPY %vreg22; GR32:%vreg22
688B		%RCX<def> = COPY %vreg21; GR64:%vreg21
696B		%R9<def> = COPY %vreg20; GR64:%vreg20
704B		CALL64pcrel32 <ga:@BZ2_bzWriteClose64>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %EDX<imp-use>, %RCX<imp-use>, %R8<imp-use>, %R9<imp-use>
712B		ADJCALLSTACKUP64 8, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
720B		%vreg11<def> = MOV64ri <ga:@BZ2_bzWriteClose>; GR64:%vreg11
736B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
752B		STACKMAP 1, 0, ...
768B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
784B		%vreg12<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg12
800B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
816B		%RDI<def> = COPY %vreg11; GR64:%vreg11
832B		%RSI<def> = COPY %vreg12; GR64:%vreg12
848B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
864B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
880B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
896B		STACKMAP 2, 0, ...
912B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
928B		RETQ

# End machine code for function BZ2_bzWriteClose.


selectOrSplit GR64:%vreg9 [16r,448r:0)  0@16r w=3.641827e-03
hints: %R8
missed hint %R8
assigning %vreg9 to %RBX: BH [16r,448r:0)  0@16r BL [16r,448r:0)  0@16r

selectOrSplit GR64:%vreg7 [32r,432r:0)  0@32r w=3.787500e-03
hints: %RCX
missed hint %RCX
%R14 is available at cost 1
Only trying the first 10 regs.
should evict: %vreg9 [16r,448r:0)  0@16r w= 3.641827e-03
hints: %R8
can reassign: %vreg9 [16r,448r:0)  0@16r from %RBX to %R8
should evict: %vreg9 [16r,448r:0)  0@16r w= 3.641827e-03
hints: %R8
can reassign: %vreg9 [16r,448r:0)  0@16r from %RBX to %R8
evicting %RBX interference: Cascade 1
unassigning %vreg9 from %RBX: BH BL
assigning %vreg7 to %RBX: BH [32r,432r:0)  0@32r BL [32r,432r:0)  0@32r
queuing new interval: %vreg9 [16r,448r:0)  0@16r

selectOrSplit GR64:%vreg9 [16r,448r:0)  0@16r w=3.641827e-03
hints: %R8
missed hint %R8
%R14 is available at cost 1
Only trying the first 10 regs.
assigning %vreg9 to %R14: R14B [16r,448r:0)  0@16r

selectOrSplit GR32:%vreg5 [48r,416r:0)  0@48r w=3.945312e-03
hints: %EDX
missed hint %EDX
%R15D is available at cost 1
Only trying the first 10 regs.
should evict: %vreg7 [32r,432r:0)  0@32r w= 3.787500e-03
hints: %RCX
can reassign: %vreg7 [32r,432r:0)  0@32r from %EBX to %RCX
should evict: %vreg7 [32r,432r:0)  0@32r w= 3.787500e-03
hints: %RCX
can reassign: %vreg7 [32r,432r:0)  0@32r from %EBX to %RCX
evicting %EBX interference: Cascade 2
unassigning %vreg7 from %RBX: BH BL
assigning %vreg5 to %EBX: BH [48r,416r:0)  0@48r BL [48r,416r:0)  0@48r
queuing new interval: %vreg7 [32r,432r:0)  0@32r

selectOrSplit GR64:%vreg7 [32r,432r:0)  0@32r w=3.787500e-03
hints: %RCX
missed hint %RCX
%R15 is available at cost 1
Only trying the first 10 regs.
assigning %vreg7 to %R15: R15B [32r,432r:0)  0@32r

selectOrSplit GR64:%vreg3 [64r,400r:0)  0@64r w=4.116848e-03
hints: %RSI
missed hint %RSI
%R12 is available at cost 1
Only trying the first 10 regs.
should evict: %vreg5 [48r,416r:0)  0@48r w= 3.945312e-03
hints: %EDX
can reassign: %vreg5 [48r,416r:0)  0@48r from %RBX to %EDX
should evict: %vreg5 [48r,416r:0)  0@48r w= 3.945312e-03
hints: %EDX
can reassign: %vreg5 [48r,416r:0)  0@48r from %RBX to %EDX
evicting %RBX interference: Cascade 3
unassigning %vreg5 from %EBX: BH BL
assigning %vreg3 to %RBX: BH [64r,400r:0)  0@64r BL [64r,400r:0)  0@64r
queuing new interval: %vreg5 [48r,416r:0)  0@48r

selectOrSplit GR32:%vreg5 [48r,416r:0)  0@48r w=3.945312e-03
hints: %EDX
missed hint %EDX
%R12D is available at cost 1
Only trying the first 10 regs.
assigning %vreg5 to %R12D: R12B [48r,416r:0)  0@48r

selectOrSplit GR64:%vreg1 [80r,384r:0)  0@80r w=4.303977e-03
hints: %RDI
missed hint %RDI
%R13 is available at cost 1
Only trying the first 10 regs.
should evict: %vreg3 [64r,400r:0)  0@64r w= 4.116848e-03
hints: %RSI
can reassign: %vreg3 [64r,400r:0)  0@64r from %RBX to %RSI
should evict: %vreg3 [64r,400r:0)  0@64r w= 4.116848e-03
hints: %RSI
can reassign: %vreg3 [64r,400r:0)  0@64r from %RBX to %RSI
evicting %RBX interference: Cascade 4
unassigning %vreg3 from %RBX: BH BL
assigning %vreg1 to %RBX: BH [80r,384r:0)  0@80r BL [80r,384r:0)  0@80r
queuing new interval: %vreg3 [64r,400r:0)  0@64r

selectOrSplit GR64:%vreg3 [64r,400r:0)  0@64r w=4.116848e-03
hints: %RSI
missed hint %RSI
%R13 is available at cost 1
Only trying the first 10 regs.
assigning %vreg3 to %R13: R13B [64r,400r:0)  0@64r

selectOrSplit GR64:%vreg26 [176r,240r:0)  0@176r w=2.176724e-03
hints: %RDI
assigning %vreg26 to %RDI: DIL [176r,240r:0)  0@176r

selectOrSplit GR64:%vreg27 [208r,256r:0)  0@208r w=4.508928e-03
hints: %RSI
assigning %vreg27 to %RSI: SIL [208r,256r:0)  0@208r

selectOrSplit GR64:%vreg24 [464r,664r:0)  0@464r w=3.366667e-03
hints: %RDI
assigning %vreg24 to %RDI: DIL [464r,664r:0)  0@464r

selectOrSplit GR64:%vreg23 [480r,672r:0)  0@480r w=3.412162e-03
hints: %RSI
assigning %vreg23 to %RSI: SIL [480r,672r:0)  0@480r

selectOrSplit GR32:%vreg22 [496r,680r:0)  0@496r w=3.458904e-03
hints: %EDX
assigning %vreg22 to %EDX: DH [496r,680r:0)  0@496r DL [496r,680r:0)  0@496r

selectOrSplit GR64:%vreg21 [512r,688r:0)  0@512r w=3.506945e-03
hints: %RCX
assigning %vreg21 to %RCX: CH [512r,688r:0)  0@512r CL [512r,688r:0)  0@512r

selectOrSplit GR64:%vreg20 [528r,696r:0)  0@528r w=3.556338e-03
hints: %R9
assigning %vreg20 to %R9: R9B [528r,696r:0)  0@528r

selectOrSplit GR64:%vreg11 [720r,816r:0)  0@720r w=2.036290e-03
hints: %RDI
assigning %vreg11 to %RDI: DIL [720r,816r:0)  0@720r

selectOrSplit GR64:%vreg12 [784r,832r:0)  0@784r w=4.508928e-03
hints: %RSI
assigning %vreg12 to %RSI: SIL [784r,832r:0)  0@784r

********** STACK TRANSFORMATION METADATA **********
********** Function: BZ2_bzWriteClose
********** REGISTER MAP **********
[%vreg1 -> %RBX] GR64
[%vreg3 -> %R13] GR64
[%vreg5 -> %R12D] GR32
[%vreg7 -> %R15] GR64
[%vreg9 -> %R14] GR64
[%vreg11 -> %RDI] GR64
[%vreg12 -> %RSI] GR64
[%vreg20 -> %R9] GR64
[%vreg21 -> %RCX] GR64
[%vreg22 -> %EDX] GR32
[%vreg23 -> %RSI] GR64
[%vreg24 -> %RDI] GR64
[%vreg26 -> %RDI] GR64
[%vreg27 -> %RSI] GR64


Stackmap 0:
  STACKMAP 0, 0, %vreg5, 0, <fi#2>, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, %vreg7, 0, <fi#3>, 0, %vreg9, 0, <fi#4>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack3] LD8[FixedStack4] GR32:%vreg5 GR64:%vreg3,%vreg1,%vreg7,%vreg9

i32 %abandon: in register %R12D (vreg 5)
i32* %abandon.addr: in stack slot 2 (size: 4)
i8* %b: in register %R13 (vreg 3)
i8** %b.addr: in stack slot 1 (size: 8)
i32* %bzerror: in register %RBX (vreg 1)
i32** %bzerror.addr: in stack slot 0 (size: 8)
i32* %nbytes_in: in register %R15 (vreg 7)
i32** %nbytes_in.addr: in stack slot 3 (size: 8)
i32* %nbytes_out: in register %R14 (vreg 9)
i32** %nbytes_out.addr: in stack slot 4 (size: 8)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, ...


Duplicate operand locations:


Stackmap 2:
  STACKMAP 2, 0, ...


Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, %vreg5, 0, <fi#2>, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, %vreg7, 0, <fi#3>, 0, %vreg9, 0, <fi#4>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack3] LD8[FixedStack4] GR32:%vreg5 GR64:%vreg3,%vreg1,%vreg7,%vreg9
  -> Call instruction SlotIndex 272B, searching vregs 0 -> 28 and stack slots -1 -> 5

  STACKMAP 1, 0, ...
  -> Call instruction SlotIndex 704B, searching vregs 0 -> 28 and stack slots -1 -> 5

  STACKMAP 2, 0, ...
  -> Call instruction SlotIndex 848B, searching vregs 0 -> 28 and stack slots -1 -> 5

********** REWRITE VIRTUAL REGISTERS **********
********** Function: BZ2_bzWriteClose
********** REGISTER MAP **********
[%vreg1 -> %RBX] GR64
[%vreg3 -> %R13] GR64
[%vreg5 -> %R12D] GR32
[%vreg7 -> %R15] GR64
[%vreg9 -> %R14] GR64
[%vreg11 -> %RDI] GR64
[%vreg12 -> %RSI] GR64
[%vreg20 -> %R9] GR64
[%vreg21 -> %RCX] GR64
[%vreg22 -> %EDX] GR32
[%vreg23 -> %RSI] GR64
[%vreg24 -> %RDI] GR64
[%vreg26 -> %RDI] GR64
[%vreg27 -> %RSI] GR64

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %EDX %RCX %RDI %RSI %R8
16B		%vreg9<def> = COPY %R8; GR64:%vreg9
32B		%vreg7<def> = COPY %RCX; GR64:%vreg7
48B		%vreg5<def> = COPY %EDX; GR32:%vreg5
64B		%vreg3<def> = COPY %RSI; GR64:%vreg3
80B		%vreg1<def> = COPY %RDI; GR64:%vreg1
176B		%vreg26<def> = MOV64ri <ga:@BZ2_bzWriteClose>; GR64:%vreg26
208B		%vreg27<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg27
224B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
240B		%RDI<def> = COPY %vreg26<kill>; GR64:%vreg26
256B		%RSI<def> = COPY %vreg27<kill>; GR64:%vreg27
272B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
288B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
336B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
352B		STACKMAP 0, 0, %vreg5, 0, <fi#2>, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, %vreg7, 0, <fi#3>, 0, %vreg9, 0, <fi#4>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack3] LD8[FixedStack4] GR32:%vreg5 GR64:%vreg3,%vreg1,%vreg7,%vreg9
368B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
384B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1<kill>; mem:ST8[%bzerror.addr] GR64:%vreg1
400B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg3<kill>; mem:ST8[%b.addr] GR64:%vreg3
416B		MOV32mr <fi#2>, 1, %noreg, 0, %noreg, %vreg5<kill>; mem:ST4[%abandon.addr] GR32:%vreg5
432B		MOV64mr <fi#3>, 1, %noreg, 0, %noreg, %vreg7<kill>; mem:ST8[%nbytes_in.addr] GR64:%vreg7
448B		MOV64mr <fi#4>, 1, %noreg, 0, %noreg, %vreg9<kill>; mem:ST8[%nbytes_out.addr] GR64:%vreg9
464B		%vreg24<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg24
480B		%vreg23<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr] GR64:%vreg23
496B		%vreg22<def> = MOV32rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD4[%abandon.addr] GR32:%vreg22
512B		%vreg21<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%nbytes_in.addr] GR64:%vreg21
528B		%vreg20<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%nbytes_out.addr] GR64:%vreg20
544B		ADJCALLSTACKDOWN64 8, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
624B		%R8D<def,dead> = MOV32r0 %EFLAGS<imp-def,dead>, %R8<imp-def>
656B		MOV64mi32 %RSP, 1, %noreg, 0, %noreg, 0; mem:ST8[Stack]
664B		%RDI<def> = COPY %vreg24<kill>; GR64:%vreg24
672B		%RSI<def> = COPY %vreg23<kill>; GR64:%vreg23
680B		%EDX<def> = COPY %vreg22<kill>; GR32:%vreg22
688B		%RCX<def> = COPY %vreg21<kill>; GR64:%vreg21
696B		%R9<def> = COPY %vreg20<kill>; GR64:%vreg20
704B		CALL64pcrel32 <ga:@BZ2_bzWriteClose64>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %EDX<imp-use>, %RCX<imp-use>, %R8<imp-use>, %R9<imp-use>
712B		ADJCALLSTACKUP64 8, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
720B		%vreg11<def> = MOV64ri <ga:@BZ2_bzWriteClose>; GR64:%vreg11
736B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
752B		STACKMAP 1, 0, ...
768B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
784B		%vreg12<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg12
800B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
816B		%RDI<def> = COPY %vreg11<kill>; GR64:%vreg11
832B		%RSI<def> = COPY %vreg12<kill>; GR64:%vreg12
848B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
864B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
880B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
896B		STACKMAP 2, 0, ...
912B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
928B		RETQ
> %R14<def> = COPY %R8
> %R15<def> = COPY %RCX
> %R12D<def> = COPY %EDX
> %R13<def> = COPY %RSI
> %RBX<def> = COPY %RDI
> %RDI<def> = MOV64ri <ga:@BZ2_bzWriteClose>
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 0, 0, %R12D, 0, <fi#2>, 0, %R13, 0, <fi#1>, 0, %RBX, 0, <fi#0>, 0, %R15, 0, <fi#3>, 0, %R14, 0, <fi#4>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack3] LD8[FixedStack4]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %RBX<kill>; mem:ST8[%bzerror.addr]
> MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %R13<kill>; mem:ST8[%b.addr]
> MOV32mr <fi#2>, 1, %noreg, 0, %noreg, %R12D<kill>; mem:ST4[%abandon.addr]
> MOV64mr <fi#3>, 1, %noreg, 0, %noreg, %R15<kill>; mem:ST8[%nbytes_in.addr]
> MOV64mr <fi#4>, 1, %noreg, 0, %noreg, %R14<kill>; mem:ST8[%nbytes_out.addr]
> %RDI<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr]
> %RSI<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr]
> %EDX<def> = MOV32rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD4[%abandon.addr]
> %RCX<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%nbytes_in.addr]
> %R9<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%nbytes_out.addr]
> ADJCALLSTACKDOWN64 8, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %R8D<def,dead> = MOV32r0 %EFLAGS<imp-def,dead>, %R8<imp-def>
> MOV64mi32 %RSP, 1, %noreg, 0, %noreg, 0; mem:ST8[Stack]
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> %EDX<def> = COPY %EDX<kill>
Deleting identity copy.
> %RCX<def> = COPY %RCX<kill>
Deleting identity copy.
> %R9<def> = COPY %R9<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@BZ2_bzWriteClose64>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %EDX<imp-use>, %RCX<imp-use>, %R8<imp-use>, %R9<imp-use>
> ADJCALLSTACKUP64 8, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = MOV64ri <ga:@BZ2_bzWriteClose>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 1, 0, ...
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 2, 0, ...
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> RETQ
Computing live-in reg-units in ABI blocks.
0B	BB#0 DIL#0 SIL#0 DH#0 DL#0 CH#0 CL#0 R8B#0 R9B#0
Created 8 new intervals.
********** INTERVALS **********
CH [0B,48r:0)[3104r,3120r:1)  0@0B-phi 1@3104r
CL [0B,48r:0)[3104r,3120r:1)  0@0B-phi 1@3104r
DH [0B,64r:0)[3088r,3120r:1)  0@0B-phi 1@3088r
DIL [0B,96r:0)[288r,320r:11)[1168r,1184r:10)[2272r,2304r:9)[3056r,3120r:8)[3360r,3376r:7)[4016r,4032r:6)[4224r,4240r:4)[4384r,4400r:5)[5568r,5584r:2)[5728r,5744r:3)[5904r,5936r:1)  0@0B-phi 1@5904r 2@5568r 3@5728r 4@4224r 5@4384r 6@4016r 7@3360r 8@3056r 9@2272r 10@1168r 11@288r
DL [0B,64r:0)[3088r,3120r:1)  0@0B-phi 1@3088r
SIL [0B,80r:0)[304r,320r:4)[2288r,2304r:1)[3072r,3120r:3)[5920r,5936r:2)  0@0B-phi 1@2288r 2@5920r 3@3072r 4@304r
R8B [0B,32r:0)  0@0B-phi
R9B [0B,16r:0)  0@0B-phi
%vreg0 [96r,208r:0)  0@96r
%vreg1 [80r,192r:0)  0@80r
%vreg2 [64r,176r:0)  0@64r
%vreg3 [48r,160r:0)  0@48r
%vreg4 [32r,144r:0)  0@32r
%vreg5 [16r,128r:0)  0@16r
%vreg6 [208r,400r:0)  0@208r
%vreg7 [192r,416r:0)  0@192r
%vreg8 [176r,432r:0)  0@176r
%vreg9 [160r,448r:0)  0@160r
%vreg10 [144r,464r:0)  0@144r
%vreg11 [128r,480r:0)  0@128r
%vreg12 [112r,496r:0)  0@112r
%vreg16 [528r,544r:0)  0@528r
%vreg17 [512r,528r:0)  0@512r
%vreg18 [224r,240r:0)  0@224r
%vreg19 [240r,288r:0)  0@240r
%vreg20 [256r,304r:0)  0@256r
%vreg23 [832r,848r:0)  0@832r
%vreg26 [944r,960r:0)  0@944r
%vreg29 [1040r,1056r:0)  0@1040r
%vreg32 [1216r,1280r:0)  0@1216r
%vreg34 [1136r,1168r:0)  0@1136r
%vreg35 [1120r,1136r:0)  0@1120r
%vreg38 [1600r,1616r:0)  0@1600r
%vreg41 [1696r,1712r:0)  0@1696r
%vreg44 [1792r,1808r:0)  0@1792r
%vreg47 [1888r,1904r:0)  0@1888r
%vreg51 [1984r,2000r:0)  0@1984r
%vreg55 [2080r,2288r:0)  0@2080r
%vreg56 [2336r,2400r:0)  0@2336r
%vreg58 [2224r,2240r:0)[2240r,2272r:1)  0@2224r 1@2240r
%vreg59 [2208r,2224r:0)  0@2208r
%vreg62 [2176r,2192r:0)  0@2176r
%vreg65 [2144r,2160r:0)[2160r,2192r:1)  0@2144r 1@2160r
%vreg66 [2128r,2144r:0)  0@2128r
%vreg68 [2096r,2112r:0)  0@2096r
%vreg72 [2768r,2784r:0)  0@2768r
%vreg75 [3248r,3264r:0)  0@3248r
%vreg78 [3216r,3232r:0)  0@3216r
%vreg80 [2832r,2848r:0)  0@2832r
%vreg81 [2848r,3072r:0)  0@2848r
%vreg84 [3152r,3216r:0)  0@3152r
%vreg86 [3024r,3104r:0)  0@3024r
%vreg87 [3008r,3024r:0)  0@3008r
%vreg89 [2992r,3088r:0)  0@2992r
%vreg92 [2960r,2976r:0)[2976r,3056r:1)  0@2960r 1@2976r
%vreg93 [2944r,2960r:0)  0@2944r
%vreg95 [2864r,2896r:0)  0@2864r
%vreg97 [2896r,2912r:0)[2912r,2928r:1)  0@2896r 1@2912r
%vreg99 [2880r,2912r:0)  0@2880r
%vreg102 [3408r,3472r:0)  0@3408r
%vreg104 [3328r,3360r:0)  0@3328r
%vreg105 [3312r,3328r:0)  0@3312r
%vreg109 [3568r,3584r:0)  0@3568r
%vreg112 [3664r,3680r:0)  0@3664r
%vreg116 [2576r,2592r:0)  0@2576r
%vreg117 [2560r,2592r:0)  0@2560r
%vreg121 [2688r,2704r:0)  0@2688r
%vreg122 [2672r,2704r:0)  0@2672r
%vreg126 [4064r,4128r:0)  0@4064r
%vreg128 [3984r,4016r:0)  0@3984r
%vreg129 [3968r,3984r:0)  0@3968r
%vreg132 [4432r,4496r:0)  0@4432r
%vreg134 [4352r,4384r:0)  0@4352r
%vreg135 [4336r,4352r:0)  0@4336r
%vreg137 [4272r,4272d:0)  0@4272r
%vreg139 [4192r,4224r:0)  0@4192r
%vreg140 [4176r,4192r:0)  0@4176r
%vreg143 [4592r,4608r:0)  0@4592r
%vreg146 [4688r,4704r:0)  0@4688r
%vreg150 [4880r,4896r:0)  0@4880r
%vreg152 [4864r,4896r:0)  0@4864r
%vreg153 [4848r,4864r:0)  0@4848r
%vreg157 [5008r,5024r:0)  0@5008r
%vreg159 [4992r,5024r:0)  0@4992r
%vreg160 [4976r,4992r:0)  0@4976r
%vreg164 [5136r,5152r:0)  0@5136r
%vreg166 [5120r,5152r:0)  0@5120r
%vreg167 [5104r,5120r:0)  0@5104r
%vreg171 [5264r,5280r:0)  0@5264r
%vreg173 [5248r,5280r:0)  0@5248r
%vreg174 [5232r,5248r:0)  0@5232r
%vreg177 [5360r,5376r:0)  0@5360r
%vreg180 [5456r,5472r:0)  0@5456r
%vreg183 [5696r,5728r:0)  0@5696r
%vreg184 [5680r,5696r:0)  0@5680r
%vreg186 [5616r,5616d:0)  0@5616r
%vreg188 [5520r,5536r:0)[5536r,5568r:1)  0@5520r 1@5536r
%vreg189 [5504r,5520r:0)  0@5504r
%vreg192 [1376r,1392r:0)  0@1376r
%vreg195 [1472r,1488r:0)  0@1472r
%vreg198 [656r,672r:0)  0@656r
%vreg201 [752r,768r:0)  0@752r
%vreg202 [5840r,5856r:0)  0@5840r
%vreg203 [5856r,5904r:0)  0@5856r
%vreg204 [5872r,5920r:0)  0@5872r
RegMasks: 320r 1184r 2304r 3120r 3376r 4032r 4240r 4400r 5584r 5744r 5936r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzWriteClose64: Post SSA
Frame Objects:
  fi#-2: size=8, align=8, fixed, at location [SP]
  fi#-1: size=8, align=16, fixed, at location [SP+8]
  fi#0: size=8, align=8, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=4, align=4, at location [SP+8]
  fi#3: size=8, align=8, at location [SP+8]
  fi#4: size=8, align=8, at location [SP+8]
  fi#5: size=8, align=8, at location [SP+8]
  fi#6: size=8, align=8, at location [SP+8]
  fi#7: size=4, align=4, at location [SP+8]
  fi#8: size=4, align=4, at location [SP+8]
  fi#9: size=4, align=4, at location [SP+8]
  fi#10: size=8, align=8, at location [SP+8]
Function Live Ins: %RDI in %vreg0, %RSI in %vreg1, %EDX in %vreg2, %RCX in %vreg3, %R8 in %vreg4, %R9 in %vreg5

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI %RSI %EDX %RCX %R8 %R9
16B		%vreg5<def> = COPY %R9; GR64:%vreg5
32B		%vreg4<def> = COPY %R8; GR64:%vreg4
48B		%vreg3<def> = COPY %RCX; GR64:%vreg3
64B		%vreg2<def> = COPY %EDX; GR32:%vreg2
80B		%vreg1<def> = COPY %RSI; GR64:%vreg1
96B		%vreg0<def> = COPY %RDI; GR64:%vreg0
112B		%vreg12<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg12
128B		%vreg11<def> = COPY %vreg5; GR64:%vreg11,%vreg5
144B		%vreg10<def> = COPY %vreg4; GR64:%vreg10,%vreg4
160B		%vreg9<def> = COPY %vreg3; GR64:%vreg9,%vreg3
176B		%vreg8<def> = COPY %vreg2; GR32:%vreg8,%vreg2
192B		%vreg7<def> = COPY %vreg1; GR64:%vreg7,%vreg1
208B		%vreg6<def> = COPY %vreg0; GR64:%vreg6,%vreg0
224B		%vreg18<def> = MOV64ri <ga:@BZ2_bzWriteClose64>; GR64:%vreg18
240B		%vreg19<def> = COPY %vreg18; GR64:%vreg19,%vreg18
256B		%vreg20<def> = MOV64rm <fi#-2>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-2] GR64:%vreg20
272B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
288B		%RDI<def> = COPY %vreg19; GR64:%vreg19
304B		%RSI<def> = COPY %vreg20; GR64:%vreg20
320B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
336B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
352B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
368B		STACKMAP 0, 0, %vreg8, 0, <fi#2>, 0, %vreg7, 0, <fi#1>, 0, %vreg6, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, %vreg10, 0, <fi#4>, 0, %vreg9, 0, <fi#3>, 0, %vreg12, 0, <fi#6>, 0, %vreg11, 0, <fi#5>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4) GR32:%vreg8 GR64:%vreg7,%vreg6,%vreg10,%vreg9,%vreg12,%vreg11
384B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
400B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg6; mem:ST8[%bzerror.addr] GR64:%vreg6
416B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg7; mem:ST8[%b.addr] GR64:%vreg7
432B		MOV32mr <fi#2>, 1, %noreg, 0, %noreg, %vreg8; mem:ST4[%abandon.addr] GR32:%vreg8
448B		MOV64mr <fi#3>, 1, %noreg, 0, %noreg, %vreg9; mem:ST8[%nbytes_in_lo32.addr] GR64:%vreg9
464B		MOV64mr <fi#4>, 1, %noreg, 0, %noreg, %vreg10; mem:ST8[%nbytes_in_hi32.addr] GR64:%vreg10
480B		MOV64mr <fi#5>, 1, %noreg, 0, %noreg, %vreg11; mem:ST8[%nbytes_out_lo32.addr] GR64:%vreg11
496B		MOV64mr <fi#6>, 1, %noreg, 0, %noreg, %vreg12; mem:ST8[%nbytes_out_hi32.addr] GR64:%vreg12
512B		%vreg17<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr] GR64:%vreg17
528B		%vreg16<def> = COPY %vreg17; GR64:%vreg16,%vreg17
544B		MOV64mr <fi#10>, 1, %noreg, 0, %noreg, %vreg16; mem:ST8[%bzf] GR64:%vreg16
560B		CMP64mi8 <fi#10>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
576B		JNE_1 <BB#6>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#6 BB#1

592B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
608B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
624B		JE_1 <BB#3>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#3 BB#2

640B	BB#2: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#1
656B		%vreg198<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg198
672B		MOV32mi %vreg198, 1, %noreg, 0, %noreg, 0; mem:ST4[%4] GR64:%vreg198
	    Successors according to CFG: BB#3

688B	BB#3: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#1 BB#2
704B		CMP64mi8 <fi#10>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
720B		JE_1 <BB#5>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#5 BB#4

736B	BB#4: derived from LLVM BB %if.then.4
	    Predecessors according to CFG: BB#3
752B		%vreg201<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg201
768B		MOV32mi %vreg201, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr] GR64:%vreg201
	    Successors according to CFG: BB#5

784B	BB#5: derived from LLVM BB %if.end.5
	    Predecessors according to CFG: BB#3 BB#4
800B		JMP_1 <BB#71>
	    Successors according to CFG: BB#71

816B	BB#6: derived from LLVM BB %if.end.6
	    Predecessors according to CFG: BB#0
832B		%vreg23<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg23
848B		CMP8mi %vreg23, 1, %noreg, 5012, %noreg, 0, %EFLAGS<imp-def>; mem:LD1[%writing] GR64:%vreg23
864B		JNE_1 <BB#12>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#12 BB#7

880B	BB#7: derived from LLVM BB %if.then.7
	    Predecessors according to CFG: BB#6
896B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
912B		JE_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#8

928B	BB#8: derived from LLVM BB %if.then.9
	    Predecessors according to CFG: BB#7
944B		%vreg26<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg26
960B		MOV32mi %vreg26, 1, %noreg, 0, %noreg, -1; mem:ST4[%10] GR64:%vreg26
	    Successors according to CFG: BB#9

976B	BB#9: derived from LLVM BB %if.end.10
	    Predecessors according to CFG: BB#7 BB#8
992B		CMP64mi8 <fi#10>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
1008B		JE_1 <BB#11>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#11 BB#10

1024B	BB#10: derived from LLVM BB %if.then.12
	    Predecessors according to CFG: BB#9
1040B		%vreg29<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg29
1056B		MOV32mi %vreg29, 1, %noreg, 5096, %noreg, -1; mem:ST4[%lastErr13] GR64:%vreg29
	    Successors according to CFG: BB#11

1072B	BB#11: derived from LLVM BB %if.end.14
	    Predecessors according to CFG: BB#9 BB#10
1088B		JMP_1 <BB#71>
	    Successors according to CFG: BB#71

1104B	BB#12: derived from LLVM BB %if.end.15
	    Predecessors according to CFG: BB#6
1120B		%vreg35<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg35
1136B		%vreg34<def> = MOV64rm %vreg35, 1, %noreg, 0, %noreg; mem:LD8[%handle] GR64:%vreg34,%vreg35
1152B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1168B		%RDI<def> = COPY %vreg34; GR64:%vreg34
1184B		CALL64pcrel32 <ga:@ferror>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
1200B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1216B		%vreg32<def> = COPY %EAX<kill>; GR32:%vreg32
1232B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1248B		STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4)
1264B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1280B		CMP32ri8 %vreg32, 0, %EFLAGS<imp-def>; GR32:%vreg32
1296B		JE_1 <BB#18>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#18 BB#13

1312B	BB#13: derived from LLVM BB %if.then.17
	    Predecessors according to CFG: BB#12
1328B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
1344B		JE_1 <BB#15>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#15 BB#14

1360B	BB#14: derived from LLVM BB %if.then.19
	    Predecessors according to CFG: BB#13
1376B		%vreg192<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg192
1392B		MOV32mi %vreg192, 1, %noreg, 0, %noreg, -6; mem:ST4[%16] GR64:%vreg192
	    Successors according to CFG: BB#15

1408B	BB#15: derived from LLVM BB %if.end.20
	    Predecessors according to CFG: BB#13 BB#14
1424B		CMP64mi8 <fi#10>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
1440B		JE_1 <BB#17>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#17 BB#16

1456B	BB#16: derived from LLVM BB %if.then.22
	    Predecessors according to CFG: BB#15
1472B		%vreg195<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg195
1488B		MOV32mi %vreg195, 1, %noreg, 5096, %noreg, -6; mem:ST4[%lastErr23] GR64:%vreg195
	    Successors according to CFG: BB#17

1504B	BB#17: derived from LLVM BB %if.end.24
	    Predecessors according to CFG: BB#15 BB#16
1520B		JMP_1 <BB#71>
	    Successors according to CFG: BB#71

1536B	BB#18: derived from LLVM BB %if.end.25
	    Predecessors according to CFG: BB#12
1552B		CMP64mi8 <fi#3>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%nbytes_in_lo32.addr]
1568B		JE_1 <BB#20>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#20 BB#19

1584B	BB#19: derived from LLVM BB %if.then.27
	    Predecessors according to CFG: BB#18
1600B		%vreg38<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%nbytes_in_lo32.addr] GR64:%vreg38
1616B		MOV32mi %vreg38, 1, %noreg, 0, %noreg, 0; mem:ST4[%20] GR64:%vreg38
	    Successors according to CFG: BB#20

1632B	BB#20: derived from LLVM BB %if.end.28
	    Predecessors according to CFG: BB#18 BB#19
1648B		CMP64mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%nbytes_in_hi32.addr]
1664B		JE_1 <BB#22>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#22 BB#21

1680B	BB#21: derived from LLVM BB %if.then.30
	    Predecessors according to CFG: BB#20
1696B		%vreg41<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%nbytes_in_hi32.addr] GR64:%vreg41
1712B		MOV32mi %vreg41, 1, %noreg, 0, %noreg, 0; mem:ST4[%22] GR64:%vreg41
	    Successors according to CFG: BB#22

1728B	BB#22: derived from LLVM BB %if.end.31
	    Predecessors according to CFG: BB#20 BB#21
1744B		CMP64mi8 <fi#5>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%nbytes_out_lo32.addr]
1760B		JE_1 <BB#24>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#24 BB#23

1776B	BB#23: derived from LLVM BB %if.then.33
	    Predecessors according to CFG: BB#22
1792B		%vreg44<def> = MOV64rm <fi#5>, 1, %noreg, 0, %noreg; mem:LD8[%nbytes_out_lo32.addr] GR64:%vreg44
1808B		MOV32mi %vreg44, 1, %noreg, 0, %noreg, 0; mem:ST4[%24] GR64:%vreg44
	    Successors according to CFG: BB#24

1824B	BB#24: derived from LLVM BB %if.end.34
	    Predecessors according to CFG: BB#22 BB#23
1840B		CMP64mi8 <fi#6>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%nbytes_out_hi32.addr]
1856B		JE_1 <BB#26>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#26 BB#25

1872B	BB#25: derived from LLVM BB %if.then.36
	    Predecessors according to CFG: BB#24
1888B		%vreg47<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%nbytes_out_hi32.addr] GR64:%vreg47
1904B		MOV32mi %vreg47, 1, %noreg, 0, %noreg, 0; mem:ST4[%26] GR64:%vreg47
	    Successors according to CFG: BB#26

1920B	BB#26: derived from LLVM BB %if.end.37
	    Predecessors according to CFG: BB#24 BB#25
1936B		CMP32mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%abandon.addr]
1952B		JNE_1 <BB#49>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#49 BB#27

1968B	BB#27: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#26
1984B		%vreg51<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg51
2000B		CMP32mi8 %vreg51, 1, %noreg, 5096, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%lastErr39] GR64:%vreg51
2016B		JNE_1 <BB#49>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#49 BB#28

2032B	BB#28: derived from LLVM BB %if.then.41
	    Predecessors according to CFG: BB#27
2048B		JMP_1 <BB#29>
	    Successors according to CFG: BB#29

2064B	BB#29: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#28 BB#47
2080B		%vreg55<def> = MOV32ri 2; GR32:%vreg55
2096B		%vreg68<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg68
2112B		MOV32mi %vreg68, 1, %noreg, 5048, %noreg, 5000; mem:ST4[%avail_out] GR64:%vreg68
2128B		%vreg66<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg66
2144B		%vreg65<def> = COPY %vreg66; GR64:%vreg65,%vreg66
2160B		%vreg65<def,tied1> = ADD64ri8 %vreg65<tied0>, 8, %EFLAGS<imp-def,dead>; GR64:%vreg65
2176B		%vreg62<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg62
2192B		MOV64mr %vreg62, 1, %noreg, 5040, %noreg, %vreg65; mem:ST8[%next_out] GR64:%vreg62,%vreg65
2208B		%vreg59<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg59
2224B		%vreg58<def> = COPY %vreg59; GR64:%vreg58,%vreg59
2240B		%vreg58<def,tied1> = ADD64ri32 %vreg58<tied0>, 5016, %EFLAGS<imp-def,dead>; GR64:%vreg58
2256B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2272B		%RDI<def> = COPY %vreg58; GR64:%vreg58
2288B		%ESI<def> = COPY %vreg55; GR32:%vreg55
2304B		CALL64pcrel32 <ga:@BZ2_bzCompress>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %EAX<imp-def>
2320B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2336B		%vreg56<def> = COPY %EAX<kill>; GR32:%vreg56
2352B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2368B		STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4)
2384B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2400B		MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %vreg56; mem:ST4[%ret] GR32:%vreg56
2416B		CMP32mi8 <fi#9>, 1, %noreg, 0, %noreg, 3, %EFLAGS<imp-def>; mem:LD4[%ret]
2432B		JE_1 <BB#36>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#36 BB#30

2448B	BB#30: derived from LLVM BB %land.lhs.true.46
	    Predecessors according to CFG: BB#29
2464B		CMP32mi8 <fi#9>, 1, %noreg, 0, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%ret]
2480B		JE_1 <BB#36>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#36 BB#31

2496B	BB#31: derived from LLVM BB %if.then.48
	    Predecessors according to CFG: BB#30
2512B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
2528B		JE_1 <BB#33>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#33 BB#32

2544B	BB#32: derived from LLVM BB %if.then.50
	    Predecessors according to CFG: BB#31
2560B		%vreg117<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%ret] GR32:%vreg117
2576B		%vreg116<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg116
2592B		MOV32mr %vreg116, 1, %noreg, 0, %noreg, %vreg117; mem:ST4[%38] GR64:%vreg116 GR32:%vreg117
	    Successors according to CFG: BB#33

2608B	BB#33: derived from LLVM BB %if.end.51
	    Predecessors according to CFG: BB#31 BB#32
2624B		CMP64mi8 <fi#10>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
2640B		JE_1 <BB#35>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#35 BB#34

2656B	BB#34: derived from LLVM BB %if.then.53
	    Predecessors according to CFG: BB#33
2672B		%vreg122<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%ret] GR32:%vreg122
2688B		%vreg121<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg121
2704B		MOV32mr %vreg121, 1, %noreg, 5096, %noreg, %vreg122; mem:ST4[%lastErr54] GR64:%vreg121 GR32:%vreg122
	    Successors according to CFG: BB#35

2720B	BB#35: derived from LLVM BB %if.end.55
	    Predecessors according to CFG: BB#33 BB#34
2736B		JMP_1 <BB#71>
	    Successors according to CFG: BB#71

2752B	BB#36: derived from LLVM BB %if.end.56
	    Predecessors according to CFG: BB#29 BB#30
2768B		%vreg72<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg72
2784B		CMP32mi %vreg72, 1, %noreg, 5048, %noreg, 5000, %EFLAGS<imp-def>; mem:LD4[%avail_out58] GR64:%vreg72
2800B		JAE_1 <BB#45>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#45 BB#37

2816B	BB#37: derived from LLVM BB %if.then.60
	    Predecessors according to CFG: BB#36
2832B		%vreg80<def> = MOV32ri 1; GR32:%vreg80
2848B		%vreg81<def> = SUBREG_TO_REG 0, %vreg80, 4; GR64:%vreg81 GR32:%vreg80
2864B		%vreg95<def> = MOV32ri 5000; GR32:%vreg95
2880B		%vreg99<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg99
2896B		%vreg97<def> = COPY %vreg95; GR32:%vreg97,%vreg95
2912B		%vreg97<def,tied1> = SUB32rm %vreg97<tied0>, %vreg99, 1, %noreg, 5048, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%avail_out62] GR32:%vreg97 GR64:%vreg99
2928B		MOV32mr <fi#7>, 1, %noreg, 0, %noreg, %vreg97; mem:ST4[%n] GR32:%vreg97
2944B		%vreg93<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg93
2960B		%vreg92<def> = COPY %vreg93; GR64:%vreg92,%vreg93
2976B		%vreg92<def,tied1> = ADD64ri8 %vreg92<tied0>, 8, %EFLAGS<imp-def,dead>; GR64:%vreg92
2992B		%vreg89<def> = MOVSX64rm32 <fi#7>, 1, %noreg, 0, %noreg; mem:LD4[%n] GR64:%vreg89
3008B		%vreg87<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg87
3024B		%vreg86<def> = MOV64rm %vreg87, 1, %noreg, 0, %noreg; mem:LD8[%handle65] GR64:%vreg86,%vreg87
3040B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3056B		%RDI<def> = COPY %vreg92; GR64:%vreg92
3072B		%RSI<def> = COPY %vreg81; GR64:%vreg81
3088B		%RDX<def> = COPY %vreg89; GR64:%vreg89
3104B		%RCX<def> = COPY %vreg86; GR64:%vreg86
3120B		CALL64pcrel32 <ga:@fwrite>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %RDX<imp-use>, %RCX<imp-use>, %RAX<imp-def>
3136B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3152B		%vreg84<def> = COPY %RAX<kill>; GR64:%vreg84
3168B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3184B		STACKMAP 3, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4)
3200B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3216B		%vreg78<def> = COPY %vreg84:sub_32bit; GR32:%vreg78 GR64:%vreg84
3232B		MOV32mr <fi#8>, 1, %noreg, 0, %noreg, %vreg78; mem:ST4[%n2] GR32:%vreg78
3248B		%vreg75<def> = MOV32rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD4[%n] GR32:%vreg75
3264B		CMP32rm %vreg75, <fi#8>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD4[%n2] GR32:%vreg75
3280B		JNE_1 <BB#39>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#39 BB#38

3296B	BB#38: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#37
3312B		%vreg105<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg105
3328B		%vreg104<def> = MOV64rm %vreg105, 1, %noreg, 0, %noreg; mem:LD8[%handle70] GR64:%vreg104,%vreg105
3344B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3360B		%RDI<def> = COPY %vreg104; GR64:%vreg104
3376B		CALL64pcrel32 <ga:@ferror>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
3392B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3408B		%vreg102<def> = COPY %EAX<kill>; GR32:%vreg102
3424B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3440B		STACKMAP 4, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4)
3456B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3472B		CMP32ri8 %vreg102, 0, %EFLAGS<imp-def>; GR32:%vreg102
3488B		JE_1 <BB#44>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#44 BB#39

3504B	BB#39: derived from LLVM BB %if.then.73
	    Predecessors according to CFG: BB#37 BB#38
3520B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
3536B		JE_1 <BB#41>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#41 BB#40

3552B	BB#40: derived from LLVM BB %if.then.76
	    Predecessors according to CFG: BB#39
3568B		%vreg109<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg109
3584B		MOV32mi %vreg109, 1, %noreg, 0, %noreg, -6; mem:ST4[%55] GR64:%vreg109
	    Successors according to CFG: BB#41

3600B	BB#41: derived from LLVM BB %if.end.77
	    Predecessors according to CFG: BB#39 BB#40
3616B		CMP64mi8 <fi#10>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
3632B		JE_1 <BB#43>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#43 BB#42

3648B	BB#42: derived from LLVM BB %if.then.80
	    Predecessors according to CFG: BB#41
3664B		%vreg112<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg112
3680B		MOV32mi %vreg112, 1, %noreg, 5096, %noreg, -6; mem:ST4[%lastErr81] GR64:%vreg112
	    Successors according to CFG: BB#43

3696B	BB#43: derived from LLVM BB %if.end.82
	    Predecessors according to CFG: BB#41 BB#42
3712B		JMP_1 <BB#71>
	    Successors according to CFG: BB#71

3728B	BB#44: derived from LLVM BB %if.end.83
	    Predecessors according to CFG: BB#38
3744B		JMP_1 <BB#45>
	    Successors according to CFG: BB#45

3760B	BB#45: derived from LLVM BB %if.end.84
	    Predecessors according to CFG: BB#36 BB#44
3776B		CMP32mi8 <fi#9>, 1, %noreg, 0, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%ret]
3792B		JNE_1 <BB#47>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#47 BB#46

3808B	BB#46: derived from LLVM BB %if.then.87
	    Predecessors according to CFG: BB#45
3824B		JMP_1 <BB#48>
	    Successors according to CFG: BB#48

3840B	BB#47: derived from LLVM BB %if.end.88
	    Predecessors according to CFG: BB#45
3856B		JMP_1 <BB#29>
	    Successors according to CFG: BB#29

3872B	BB#48: derived from LLVM BB %while.end
	    Predecessors according to CFG: BB#46
3888B		JMP_1 <BB#49>
	    Successors according to CFG: BB#49

3904B	BB#49: derived from LLVM BB %if.end.89
	    Predecessors according to CFG: BB#26 BB#27 BB#48
3920B		CMP32mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%abandon.addr]
3936B		JNE_1 <BB#58>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#58 BB#50

3952B	BB#50: derived from LLVM BB %land.lhs.true.91
	    Predecessors according to CFG: BB#49
3968B		%vreg129<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg129
3984B		%vreg128<def> = MOV64rm %vreg129, 1, %noreg, 0, %noreg; mem:LD8[%handle92] GR64:%vreg128,%vreg129
4000B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4016B		%RDI<def> = COPY %vreg128; GR64:%vreg128
4032B		CALL64pcrel32 <ga:@ferror>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
4048B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4064B		%vreg126<def> = COPY %EAX<kill>; GR32:%vreg126
4080B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4096B		STACKMAP 5, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, ...; mem:LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5]
4112B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4128B		CMP32ri8 %vreg126, 0, %EFLAGS<imp-def>; GR32:%vreg126
4144B		JNE_1 <BB#58>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#58 BB#51

4160B	BB#51: derived from LLVM BB %if.then.95
	    Predecessors according to CFG: BB#50
4176B		%vreg140<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg140
4192B		%vreg139<def> = MOV64rm %vreg140, 1, %noreg, 0, %noreg; mem:LD8[%handle96] GR64:%vreg139,%vreg140
4208B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4224B		%RDI<def> = COPY %vreg139; GR64:%vreg139
4240B		CALL64pcrel32 <ga:@fflush>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
4256B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4272B		%vreg137<def,dead> = COPY %EAX<kill>; GR32:%vreg137
4288B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4304B		STACKMAP 6, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, ...; mem:LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5]
4320B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4336B		%vreg135<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg135
4352B		%vreg134<def> = MOV64rm %vreg135, 1, %noreg, 0, %noreg; mem:LD8[%handle98] GR64:%vreg134,%vreg135
4368B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4384B		%RDI<def> = COPY %vreg134; GR64:%vreg134
4400B		CALL64pcrel32 <ga:@ferror>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
4416B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4432B		%vreg132<def> = COPY %EAX<kill>; GR32:%vreg132
4448B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4464B		STACKMAP 7, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, ...; mem:LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5]
4480B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4496B		CMP32ri8 %vreg132, 0, %EFLAGS<imp-def>; GR32:%vreg132
4512B		JE_1 <BB#57>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#57 BB#52

4528B	BB#52: derived from LLVM BB %if.then.101
	    Predecessors according to CFG: BB#51
4544B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
4560B		JE_1 <BB#54>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#54 BB#53

4576B	BB#53: derived from LLVM BB %if.then.104
	    Predecessors according to CFG: BB#52
4592B		%vreg143<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg143
4608B		MOV32mi %vreg143, 1, %noreg, 0, %noreg, -6; mem:ST4[%67] GR64:%vreg143
	    Successors according to CFG: BB#54

4624B	BB#54: derived from LLVM BB %if.end.105
	    Predecessors according to CFG: BB#52 BB#53
4640B		CMP64mi8 <fi#10>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
4656B		JE_1 <BB#56>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#56 BB#55

4672B	BB#55: derived from LLVM BB %if.then.108
	    Predecessors according to CFG: BB#54
4688B		%vreg146<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg146
4704B		MOV32mi %vreg146, 1, %noreg, 5096, %noreg, -6; mem:ST4[%lastErr109] GR64:%vreg146
	    Successors according to CFG: BB#56

4720B	BB#56: derived from LLVM BB %if.end.110
	    Predecessors according to CFG: BB#54 BB#55
4736B		JMP_1 <BB#71>
	    Successors according to CFG: BB#71

4752B	BB#57: derived from LLVM BB %if.end.111
	    Predecessors according to CFG: BB#51
4768B		JMP_1 <BB#58>
	    Successors according to CFG: BB#58

4784B	BB#58: derived from LLVM BB %if.end.112
	    Predecessors according to CFG: BB#49 BB#50 BB#57
4800B		CMP64mi8 <fi#3>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%nbytes_in_lo32.addr]
4816B		JE_1 <BB#60>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#60 BB#59

4832B	BB#59: derived from LLVM BB %if.then.115
	    Predecessors according to CFG: BB#58
4848B		%vreg153<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg153
4864B		%vreg152<def> = MOV32rm %vreg153, 1, %noreg, 5028, %noreg; mem:LD4[%total_in_lo32] GR32:%vreg152 GR64:%vreg153
4880B		%vreg150<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%nbytes_in_lo32.addr] GR64:%vreg150
4896B		MOV32mr %vreg150, 1, %noreg, 0, %noreg, %vreg152; mem:ST4[%73] GR64:%vreg150 GR32:%vreg152
	    Successors according to CFG: BB#60

4912B	BB#60: derived from LLVM BB %if.end.117
	    Predecessors according to CFG: BB#58 BB#59
4928B		CMP64mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%nbytes_in_hi32.addr]
4944B		JE_1 <BB#62>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#62 BB#61

4960B	BB#61: derived from LLVM BB %if.then.120
	    Predecessors according to CFG: BB#60
4976B		%vreg160<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg160
4992B		%vreg159<def> = MOV32rm %vreg160, 1, %noreg, 5032, %noreg; mem:LD4[%total_in_hi32] GR32:%vreg159 GR64:%vreg160
5008B		%vreg157<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%nbytes_in_hi32.addr] GR64:%vreg157
5024B		MOV32mr %vreg157, 1, %noreg, 0, %noreg, %vreg159; mem:ST4[%77] GR64:%vreg157 GR32:%vreg159
	    Successors according to CFG: BB#62

5040B	BB#62: derived from LLVM BB %if.end.122
	    Predecessors according to CFG: BB#60 BB#61
5056B		CMP64mi8 <fi#5>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%nbytes_out_lo32.addr]
5072B		JE_1 <BB#64>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#64 BB#63

5088B	BB#63: derived from LLVM BB %if.then.125
	    Predecessors according to CFG: BB#62
5104B		%vreg167<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg167
5120B		%vreg166<def> = MOV32rm %vreg167, 1, %noreg, 5052, %noreg; mem:LD4[%total_out_lo32] GR32:%vreg166 GR64:%vreg167
5136B		%vreg164<def> = MOV64rm <fi#5>, 1, %noreg, 0, %noreg; mem:LD8[%nbytes_out_lo32.addr] GR64:%vreg164
5152B		MOV32mr %vreg164, 1, %noreg, 0, %noreg, %vreg166; mem:ST4[%81] GR64:%vreg164 GR32:%vreg166
	    Successors according to CFG: BB#64

5168B	BB#64: derived from LLVM BB %if.end.127
	    Predecessors according to CFG: BB#62 BB#63
5184B		CMP64mi8 <fi#6>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%nbytes_out_hi32.addr]
5200B		JE_1 <BB#66>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#66 BB#65

5216B	BB#65: derived from LLVM BB %if.then.130
	    Predecessors according to CFG: BB#64
5232B		%vreg174<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg174
5248B		%vreg173<def> = MOV32rm %vreg174, 1, %noreg, 5056, %noreg; mem:LD4[%total_out_hi32] GR32:%vreg173 GR64:%vreg174
5264B		%vreg171<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%nbytes_out_hi32.addr] GR64:%vreg171
5280B		MOV32mr %vreg171, 1, %noreg, 0, %noreg, %vreg173; mem:ST4[%85] GR64:%vreg171 GR32:%vreg173
	    Successors according to CFG: BB#66

5296B	BB#66: derived from LLVM BB %if.end.132
	    Predecessors according to CFG: BB#64 BB#65
5312B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
5328B		JE_1 <BB#68>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#68 BB#67

5344B	BB#67: derived from LLVM BB %if.then.135
	    Predecessors according to CFG: BB#66
5360B		%vreg177<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg177
5376B		MOV32mi %vreg177, 1, %noreg, 0, %noreg, 0; mem:ST4[%87] GR64:%vreg177
	    Successors according to CFG: BB#68

5392B	BB#68: derived from LLVM BB %if.end.136
	    Predecessors according to CFG: BB#66 BB#67
5408B		CMP64mi8 <fi#10>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
5424B		JE_1 <BB#70>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#70 BB#69

5440B	BB#69: derived from LLVM BB %if.then.139
	    Predecessors according to CFG: BB#68
5456B		%vreg180<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg180
5472B		MOV32mi %vreg180, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr140] GR64:%vreg180
	    Successors according to CFG: BB#70

5488B	BB#70: derived from LLVM BB %if.end.141
	    Predecessors according to CFG: BB#68 BB#69
5504B		%vreg189<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg189
5520B		%vreg188<def> = COPY %vreg189; GR64:%vreg188,%vreg189
5536B		%vreg188<def,tied1> = ADD64ri32 %vreg188<tied0>, 5016, %EFLAGS<imp-def,dead>; GR64:%vreg188
5552B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5568B		%RDI<def> = COPY %vreg188; GR64:%vreg188
5584B		CALL64pcrel32 <ga:@BZ2_bzCompressEnd>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
5600B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5616B		%vreg186<def,dead> = COPY %EAX<kill>; GR32:%vreg186
5632B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5648B		STACKMAP 8, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack10]
5664B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5680B		%vreg184<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg184
5696B		%vreg183<def> = COPY %vreg184; GR64:%vreg183,%vreg184
5712B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5728B		%RDI<def> = COPY %vreg183; GR64:%vreg183
5744B		CALL64pcrel32 <ga:@free>, <regmask>, %RSP<imp-use>, %RDI<imp-use>
5760B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5776B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5792B		STACKMAP 9, 0, ...
5808B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#71

5824B	BB#71: derived from LLVM BB %return
	    Predecessors according to CFG: BB#11 BB#43 BB#35 BB#56 BB#70 BB#17 BB#5
5840B		%vreg202<def> = MOV64ri <ga:@BZ2_bzWriteClose64>; GR64:%vreg202
5856B		%vreg203<def> = COPY %vreg202; GR64:%vreg203,%vreg202
5872B		%vreg204<def> = MOV64rm <fi#-2>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-2] GR64:%vreg204
5888B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5904B		%RDI<def> = COPY %vreg203; GR64:%vreg203
5920B		%RSI<def> = COPY %vreg204; GR64:%vreg204
5936B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
5952B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5968B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5984B		STACKMAP 10, 0, ...
6000B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
6016B		RETQ

# End machine code for function BZ2_bzWriteClose64.

********** SIMPLE REGISTER COALESCING **********
********** Function: BZ2_bzWriteClose64
********** JOINING INTERVALS ***********
while.body:
2272B	%RDI<def> = COPY %vreg58; GR64:%vreg58
	Considering merging %vreg58 with %RDI
	Can only merge into reserved registers.
2288B	%ESI<def> = COPY %vreg55; GR32:%vreg55
	Considering merging %vreg55 with %ESI
	Can only merge into reserved registers.
Remat: %ESI<def> = MOV32ri 2
Shrink: %vreg55 [2080r,2288r:0)  0@2080r
All defs dead: 2080r	%vreg55<def,dead> = MOV32ri 2; GR32:%vreg55
Shrunk: %vreg55 [2080r,2080d:0)  0@2080r
Deleting dead def 2080r	%vreg55<def,dead> = MOV32ri 2; GR32:%vreg55
2336B	%vreg56<def> = COPY %EAX<kill>; GR32:%vreg56
	Considering merging %vreg56 with %EAX
	Can only merge into reserved registers.
if.end.56:
if.end.84:
land.lhs.true.46:
if.then.60:
2848B	%vreg81<def> = SUBREG_TO_REG 0, %vreg80, 4; GR64:%vreg81 GR32:%vreg80
	Considering merging to GR64_with_sub_8bit with %vreg80 in %vreg81:sub_32bit
		RHS = %vreg80 [2832r,2848r:0)  0@2832r
		LHS = %vreg81 [2848r,3072r:0)  0@2848r
		merge %vreg81:0@2848r into %vreg80:0@2832r --> @2832r
		erased:	2848r	%vreg81<def> = SUBREG_TO_REG 0, %vreg80, 4; GR64:%vreg81 GR32:%vreg80
		updated: 2832B	%vreg81:sub_32bit<def,read-undef> = MOV32ri 1; GR64_with_sub_8bit:%vreg81
	Success: %vreg80:sub_32bit -> %vreg81
	Result = %vreg81 [2832r,3072r:0)  0@2832r
3056B	%RDI<def> = COPY %vreg92; GR64:%vreg92
	Considering merging %vreg92 with %RDI
	Can only merge into reserved registers.
3072B	%RSI<def> = COPY %vreg81; GR64_with_sub_8bit:%vreg81
	Considering merging %vreg81 with %RSI
	Can only merge into reserved registers.
Remat: %ESI<def,dead> = MOV32ri 1, %RSI<imp-def>
Shrink: %vreg81 [2832r,3072r:0)  0@2832r
All defs dead: 2832r	%vreg81:sub_32bit<def,read-undef,dead> = MOV32ri 1; GR64_with_sub_8bit:%vreg81
Shrunk: %vreg81 [2832r,2832d:0)  0@2832r
Deleting dead def 2832r	%vreg81:sub_32bit<def,read-undef,dead> = MOV32ri 1; GR64_with_sub_8bit:%vreg81
3088B	%RDX<def> = COPY %vreg89; GR64:%vreg89
	Considering merging %vreg89 with %RDX
	Can only merge into reserved registers.
3104B	%RCX<def> = COPY %vreg86; GR64:%vreg86
	Considering merging %vreg86 with %RCX
	Can only merge into reserved registers.
3152B	%vreg84<def> = COPY %RAX<kill>; GR64:%vreg84
	Considering merging %vreg84 with %RAX
	Can only merge into reserved registers.
lor.lhs.false:
3360B	%RDI<def> = COPY %vreg104; GR64:%vreg104
	Considering merging %vreg104 with %RDI
	Can only merge into reserved registers.
3408B	%vreg102<def> = COPY %EAX<kill>; GR32:%vreg102
	Considering merging %vreg102 with %EAX
	Can only merge into reserved registers.
if.end.83:
if.end.88:
2144B	%vreg65<def> = COPY %vreg66; GR64:%vreg65,%vreg66
	Considering merging to GR64 with %vreg66 in %vreg65
		RHS = %vreg66 [2128r,2144r:0)  0@2128r
		LHS = %vreg65 [2144r,2160r:0)[2160r,2192r:1)  0@2144r 1@2160r
		merge %vreg65:0@2144r into %vreg66:0@2128r --> @2128r
		erased:	2144r	%vreg65<def> = COPY %vreg66; GR64:%vreg65,%vreg66
		updated: 2128B	%vreg65<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg65
	Success: %vreg66 -> %vreg65
	Result = %vreg65 [2128r,2160r:0)[2160r,2192r:1)  0@2128r 1@2160r
2224B	%vreg58<def> = COPY %vreg59; GR64:%vreg58,%vreg59
	Considering merging to GR64 with %vreg59 in %vreg58
		RHS = %vreg59 [2208r,2224r:0)  0@2208r
		LHS = %vreg58 [2224r,2240r:0)[2240r,2272r:1)  0@2224r 1@2240r
		merge %vreg58:0@2224r into %vreg59:0@2208r --> @2208r
		erased:	2224r	%vreg58<def> = COPY %vreg59; GR64:%vreg58,%vreg59
		updated: 2208B	%vreg58<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg58
	Success: %vreg59 -> %vreg58
	Result = %vreg58 [2208r,2240r:0)[2240r,2272r:1)  0@2208r 1@2240r
2896B	%vreg97<def> = COPY %vreg95; GR32:%vreg97,%vreg95
	Considering merging to GR32 with %vreg95 in %vreg97
		RHS = %vreg95 [2864r,2896r:0)  0@2864r
		LHS = %vreg97 [2896r,2912r:0)[2912r,2928r:1)  0@2896r 1@2912r
		merge %vreg97:0@2896r into %vreg95:0@2864r --> @2864r
		erased:	2896r	%vreg97<def> = COPY %vreg95; GR32:%vreg97,%vreg95
		updated: 2864B	%vreg97<def> = MOV32ri 5000; GR32:%vreg97
	Success: %vreg95 -> %vreg97
	Result = %vreg97 [2864r,2912r:0)[2912r,2928r:1)  0@2864r 1@2912r
2960B	%vreg92<def> = COPY %vreg93; GR64:%vreg92,%vreg93
	Considering merging to GR64 with %vreg93 in %vreg92
		RHS = %vreg93 [2944r,2960r:0)  0@2944r
		LHS = %vreg92 [2960r,2976r:0)[2976r,3056r:1)  0@2960r 1@2976r
		merge %vreg92:0@2960r into %vreg93:0@2944r --> @2944r
		erased:	2960r	%vreg92<def> = COPY %vreg93; GR64:%vreg92,%vreg93
		updated: 2944B	%vreg92<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg92
	Success: %vreg93 -> %vreg92
	Result = %vreg92 [2944r,2976r:0)[2976r,3056r:1)  0@2944r 1@2976r
3216B	%vreg78<def> = COPY %vreg84:sub_32bit; GR32:%vreg78 GR64:%vreg84
	Considering merging to GR64_with_sub_8bit with %vreg78 in %vreg84:sub_32bit
		RHS = %vreg78 [3216r,3232r:0)  0@3216r
		LHS = %vreg84 [3152r,3216r:0)  0@3152r
		merge %vreg78:0@3216r into %vreg84:0@3152r --> @3152r
		erased:	3216r	%vreg78<def> = COPY %vreg84:sub_32bit; GR32:%vreg78 GR64:%vreg84
		updated: 3232B	MOV32mr <fi#8>, 1, %noreg, 0, %noreg, %vreg84:sub_32bit; mem:ST4[%n2] GR64_with_sub_8bit:%vreg84
	Success: %vreg78:sub_32bit -> %vreg84
	Result = %vreg84 [3152r,3232r:0)  0@3152r
return:
5904B	%RDI<def> = COPY %vreg203; GR64:%vreg203
	Considering merging %vreg203 with %RDI
	Can only merge into reserved registers.
5920B	%RSI<def> = COPY %vreg204; GR64:%vreg204
	Considering merging %vreg204 with %RSI
	Can only merge into reserved registers.
if.end.89:
if.end.112:
if.end:
if.end.10:
if.end.20:
if.end.28:
if.end.31:
if.end.34:
if.end.37:
if.end.51:
if.then.73:
if.end.77:
if.end.105:
if.end.117:
if.end.122:
if.end.127:
if.end.132:
if.end.136:
if.then:
if.end.5:
if.end.6:
if.then.7:
if.end.14:
if.end.15:
1168B	%RDI<def> = COPY %vreg34; GR64:%vreg34
	Considering merging %vreg34 with %RDI
	Can only merge into reserved registers.
1216B	%vreg32<def> = COPY %EAX<kill>; GR32:%vreg32
	Considering merging %vreg32 with %EAX
	Can only merge into reserved registers.
if.then.17:
if.end.24:
if.end.25:
land.lhs.true:
if.then.48:
if.end.55:
if.end.82:
land.lhs.true.91:
4016B	%RDI<def> = COPY %vreg128; GR64:%vreg128
	Considering merging %vreg128 with %RDI
	Can only merge into reserved registers.
4064B	%vreg126<def> = COPY %EAX<kill>; GR32:%vreg126
	Considering merging %vreg126 with %EAX
	Can only merge into reserved registers.
if.then.95:
4224B	%RDI<def> = COPY %vreg139; GR64:%vreg139
	Considering merging %vreg139 with %RDI
	Can only merge into reserved registers.
4272B	%vreg137<def,dead> = COPY %EAX<kill>; GR32:%vreg137
	Considering merging %vreg137 with %EAX
	Can only merge into reserved registers.
4384B	%RDI<def> = COPY %vreg134; GR64:%vreg134
	Considering merging %vreg134 with %RDI
	Can only merge into reserved registers.
4432B	%vreg132<def> = COPY %EAX<kill>; GR32:%vreg132
	Considering merging %vreg132 with %EAX
	Can only merge into reserved registers.
if.then.101:
if.end.110:
if.end.141:
5568B	%RDI<def> = COPY %vreg188; GR64:%vreg188
	Considering merging %vreg188 with %RDI
	Can only merge into reserved registers.
5616B	%vreg186<def,dead> = COPY %EAX<kill>; GR32:%vreg186
	Considering merging %vreg186 with %EAX
	Can only merge into reserved registers.
5728B	%RDI<def> = COPY %vreg183; GR64:%vreg183
	Considering merging %vreg183 with %RDI
	Can only merge into reserved registers.
entry:
16B	%vreg5<def> = COPY %R9; GR64:%vreg5
	Considering merging %vreg5 with %R9
	Can only merge into reserved registers.
32B	%vreg4<def> = COPY %R8; GR64:%vreg4
	Considering merging %vreg4 with %R8
	Can only merge into reserved registers.
48B	%vreg3<def> = COPY %RCX; GR64:%vreg3
	Considering merging %vreg3 with %RCX
	Can only merge into reserved registers.
64B	%vreg2<def> = COPY %EDX; GR32:%vreg2
	Considering merging %vreg2 with %EDX
	Can only merge into reserved registers.
80B	%vreg1<def> = COPY %RSI; GR64:%vreg1
	Considering merging %vreg1 with %RSI
	Can only merge into reserved registers.
96B	%vreg0<def> = COPY %RDI; GR64:%vreg0
	Considering merging %vreg0 with %RDI
	Can only merge into reserved registers.
288B	%RDI<def> = COPY %vreg19; GR64:%vreg19
	Considering merging %vreg19 with %RDI
	Can only merge into reserved registers.
304B	%RSI<def> = COPY %vreg20; GR64:%vreg20
	Considering merging %vreg20 with %RSI
	Can only merge into reserved registers.
if.then.2:
if.then.4:
if.then.9:
if.then.12:
if.then.19:
if.then.22:
if.then.27:
if.then.30:
if.then.33:
if.then.36:
if.then.41:
if.then.50:
if.then.53:
if.then.76:
if.then.80:
if.then.87:
while.end:
if.then.104:
if.then.108:
if.end.111:
if.then.115:
if.then.120:
if.then.125:
if.then.130:
if.then.135:
if.then.139:
5856B	%vreg203<def> = COPY %vreg202; GR64:%vreg203,%vreg202
	Considering merging to GR64 with %vreg202 in %vreg203
		RHS = %vreg202 [5840r,5856r:0)  0@5840r
		LHS = %vreg203 [5856r,5904r:0)  0@5856r
		merge %vreg203:0@5856r into %vreg202:0@5840r --> @5840r
		erased:	5856r	%vreg203<def> = COPY %vreg202; GR64:%vreg203,%vreg202
		updated: 5840B	%vreg203<def> = MOV64ri <ga:@BZ2_bzWriteClose64>; GR64:%vreg203
	Success: %vreg202 -> %vreg203
	Result = %vreg203 [5840r,5904r:0)  0@5840r
5520B	%vreg188<def> = COPY %vreg189; GR64:%vreg188,%vreg189
	Considering merging to GR64 with %vreg189 in %vreg188
		RHS = %vreg189 [5504r,5520r:0)  0@5504r
		LHS = %vreg188 [5520r,5536r:0)[5536r,5568r:1)  0@5520r 1@5536r
		merge %vreg188:0@5520r into %vreg189:0@5504r --> @5504r
		erased:	5520r	%vreg188<def> = COPY %vreg189; GR64:%vreg188,%vreg189
		updated: 5504B	%vreg188<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg188
	Success: %vreg189 -> %vreg188
	Result = %vreg188 [5504r,5536r:0)[5536r,5568r:1)  0@5504r 1@5536r
5696B	%vreg183<def> = COPY %vreg184; GR64:%vreg183,%vreg184
	Considering merging to GR64 with %vreg184 in %vreg183
		RHS = %vreg184 [5680r,5696r:0)  0@5680r
		LHS = %vreg183 [5696r,5728r:0)  0@5696r
		merge %vreg183:0@5696r into %vreg184:0@5680r --> @5680r
		erased:	5696r	%vreg183<def> = COPY %vreg184; GR64:%vreg183,%vreg184
		updated: 5680B	%vreg183<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg183
	Success: %vreg184 -> %vreg183
	Result = %vreg183 [5680r,5728r:0)  0@5680r
128B	%vreg11<def> = COPY %vreg5; GR64:%vreg11,%vreg5
	Considering merging to GR64 with %vreg5 in %vreg11
		RHS = %vreg5 [16r,128r:0)  0@16r
		LHS = %vreg11 [128r,480r:0)  0@128r
		merge %vreg11:0@128r into %vreg5:0@16r --> @16r
		erased:	128r	%vreg11<def> = COPY %vreg5; GR64:%vreg11,%vreg5
		updated: 16B	%vreg11<def> = COPY %R9; GR64:%vreg11
	Success: %vreg5 -> %vreg11
	Result = %vreg11 [16r,480r:0)  0@16r
144B	%vreg10<def> = COPY %vreg4; GR64:%vreg10,%vreg4
	Considering merging to GR64 with %vreg4 in %vreg10
		RHS = %vreg4 [32r,144r:0)  0@32r
		LHS = %vreg10 [144r,464r:0)  0@144r
		merge %vreg10:0@144r into %vreg4:0@32r --> @32r
		erased:	144r	%vreg10<def> = COPY %vreg4; GR64:%vreg10,%vreg4
		updated: 32B	%vreg10<def> = COPY %R8; GR64:%vreg10
	Success: %vreg4 -> %vreg10
	Result = %vreg10 [32r,464r:0)  0@32r
160B	%vreg9<def> = COPY %vreg3; GR64:%vreg9,%vreg3
	Considering merging to GR64 with %vreg3 in %vreg9
		RHS = %vreg3 [48r,160r:0)  0@48r
		LHS = %vreg9 [160r,448r:0)  0@160r
		merge %vreg9:0@160r into %vreg3:0@48r --> @48r
		erased:	160r	%vreg9<def> = COPY %vreg3; GR64:%vreg9,%vreg3
		updated: 48B	%vreg9<def> = COPY %RCX; GR64:%vreg9
	Success: %vreg3 -> %vreg9
	Result = %vreg9 [48r,448r:0)  0@48r
176B	%vreg8<def> = COPY %vreg2; GR32:%vreg8,%vreg2
	Considering merging to GR32 with %vreg2 in %vreg8
		RHS = %vreg2 [64r,176r:0)  0@64r
		LHS = %vreg8 [176r,432r:0)  0@176r
		merge %vreg8:0@176r into %vreg2:0@64r --> @64r
		erased:	176r	%vreg8<def> = COPY %vreg2; GR32:%vreg8,%vreg2
		updated: 64B	%vreg8<def> = COPY %EDX; GR32:%vreg8
	Success: %vreg2 -> %vreg8
	Result = %vreg8 [64r,432r:0)  0@64r
192B	%vreg7<def> = COPY %vreg1; GR64:%vreg7,%vreg1
	Considering merging to GR64 with %vreg1 in %vreg7
		RHS = %vreg1 [80r,192r:0)  0@80r
		LHS = %vreg7 [192r,416r:0)  0@192r
		merge %vreg7:0@192r into %vreg1:0@80r --> @80r
		erased:	192r	%vreg7<def> = COPY %vreg1; GR64:%vreg7,%vreg1
		updated: 80B	%vreg7<def> = COPY %RSI; GR64:%vreg7
	Success: %vreg1 -> %vreg7
	Result = %vreg7 [80r,416r:0)  0@80r
208B	%vreg6<def> = COPY %vreg0; GR64:%vreg6,%vreg0
	Considering merging to GR64 with %vreg0 in %vreg6
		RHS = %vreg0 [96r,208r:0)  0@96r
		LHS = %vreg6 [208r,400r:0)  0@208r
		merge %vreg6:0@208r into %vreg0:0@96r --> @96r
		erased:	208r	%vreg6<def> = COPY %vreg0; GR64:%vreg6,%vreg0
		updated: 96B	%vreg6<def> = COPY %RDI; GR64:%vreg6
	Success: %vreg0 -> %vreg6
	Result = %vreg6 [96r,400r:0)  0@96r
240B	%vreg19<def> = COPY %vreg18; GR64:%vreg19,%vreg18
	Considering merging to GR64 with %vreg18 in %vreg19
		RHS = %vreg18 [224r,240r:0)  0@224r
		LHS = %vreg19 [240r,288r:0)  0@240r
		merge %vreg19:0@240r into %vreg18:0@224r --> @224r
		erased:	240r	%vreg19<def> = COPY %vreg18; GR64:%vreg19,%vreg18
		updated: 224B	%vreg19<def> = MOV64ri <ga:@BZ2_bzWriteClose64>; GR64:%vreg19
	Success: %vreg18 -> %vreg19
	Result = %vreg19 [224r,288r:0)  0@224r
528B	%vreg16<def> = COPY %vreg17; GR64:%vreg16,%vreg17
	Considering merging to GR64 with %vreg17 in %vreg16
		RHS = %vreg17 [512r,528r:0)  0@512r
		LHS = %vreg16 [528r,544r:0)  0@528r
		merge %vreg16:0@528r into %vreg17:0@512r --> @512r
		erased:	528r	%vreg16<def> = COPY %vreg17; GR64:%vreg16,%vreg17
		updated: 512B	%vreg16<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr] GR64:%vreg16
	Success: %vreg17 -> %vreg16
	Result = %vreg16 [512r,544r:0)  0@512r
5904B	%RDI<def> = COPY %vreg203; GR64:%vreg203
	Considering merging %vreg203 with %RDI
	Can only merge into reserved registers.
5728B	%RDI<def> = COPY %vreg183; GR64:%vreg183
	Considering merging %vreg183 with %RDI
	Can only merge into reserved registers.
288B	%RDI<def> = COPY %vreg19; GR64:%vreg19
	Considering merging %vreg19 with %RDI
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
CH [0B,48r:0)[3104r,3120r:1)  0@0B-phi 1@3104r
CL [0B,48r:0)[3104r,3120r:1)  0@0B-phi 1@3104r
DH [0B,64r:0)[3088r,3120r:1)  0@0B-phi 1@3088r
DIL [0B,96r:0)[288r,320r:11)[1168r,1184r:10)[2272r,2304r:9)[3056r,3120r:8)[3360r,3376r:7)[4016r,4032r:6)[4224r,4240r:4)[4384r,4400r:5)[5568r,5584r:2)[5728r,5744r:3)[5904r,5936r:1)  0@0B-phi 1@5904r 2@5568r 3@5728r 4@4224r 5@4384r 6@4016r 7@3360r 8@3056r 9@2272r 10@1168r 11@288r
DL [0B,64r:0)[3088r,3120r:1)  0@0B-phi 1@3088r
SIL [0B,80r:0)[304r,320r:4)[2288r,2304r:1)[3072r,3120r:3)[5920r,5936r:2)  0@0B-phi 1@2288r 2@5920r 3@3072r 4@304r
R8B [0B,32r:0)  0@0B-phi
R9B [0B,16r:0)  0@0B-phi
%vreg6 [96r,400r:0)  0@96r
%vreg7 [80r,416r:0)  0@80r
%vreg8 [64r,432r:0)  0@64r
%vreg9 [48r,448r:0)  0@48r
%vreg10 [32r,464r:0)  0@32r
%vreg11 [16r,480r:0)  0@16r
%vreg12 [112r,496r:0)  0@112r
%vreg16 [512r,544r:0)  0@512r
%vreg19 [224r,288r:0)  0@224r
%vreg20 [256r,304r:0)  0@256r
%vreg23 [832r,848r:0)  0@832r
%vreg26 [944r,960r:0)  0@944r
%vreg29 [1040r,1056r:0)  0@1040r
%vreg32 [1216r,1280r:0)  0@1216r
%vreg34 [1136r,1168r:0)  0@1136r
%vreg35 [1120r,1136r:0)  0@1120r
%vreg38 [1600r,1616r:0)  0@1600r
%vreg41 [1696r,1712r:0)  0@1696r
%vreg44 [1792r,1808r:0)  0@1792r
%vreg47 [1888r,1904r:0)  0@1888r
%vreg51 [1984r,2000r:0)  0@1984r
%vreg56 [2336r,2400r:0)  0@2336r
%vreg58 [2208r,2240r:0)[2240r,2272r:1)  0@2208r 1@2240r
%vreg62 [2176r,2192r:0)  0@2176r
%vreg65 [2128r,2160r:0)[2160r,2192r:1)  0@2128r 1@2160r
%vreg68 [2096r,2112r:0)  0@2096r
%vreg72 [2768r,2784r:0)  0@2768r
%vreg75 [3248r,3264r:0)  0@3248r
%vreg84 [3152r,3232r:0)  0@3152r
%vreg86 [3024r,3104r:0)  0@3024r
%vreg87 [3008r,3024r:0)  0@3008r
%vreg89 [2992r,3088r:0)  0@2992r
%vreg92 [2944r,2976r:0)[2976r,3056r:1)  0@2944r 1@2976r
%vreg97 [2864r,2912r:0)[2912r,2928r:1)  0@2864r 1@2912r
%vreg99 [2880r,2912r:0)  0@2880r
%vreg102 [3408r,3472r:0)  0@3408r
%vreg104 [3328r,3360r:0)  0@3328r
%vreg105 [3312r,3328r:0)  0@3312r
%vreg109 [3568r,3584r:0)  0@3568r
%vreg112 [3664r,3680r:0)  0@3664r
%vreg116 [2576r,2592r:0)  0@2576r
%vreg117 [2560r,2592r:0)  0@2560r
%vreg121 [2688r,2704r:0)  0@2688r
%vreg122 [2672r,2704r:0)  0@2672r
%vreg126 [4064r,4128r:0)  0@4064r
%vreg128 [3984r,4016r:0)  0@3984r
%vreg129 [3968r,3984r:0)  0@3968r
%vreg132 [4432r,4496r:0)  0@4432r
%vreg134 [4352r,4384r:0)  0@4352r
%vreg135 [4336r,4352r:0)  0@4336r
%vreg137 [4272r,4272d:0)  0@4272r
%vreg139 [4192r,4224r:0)  0@4192r
%vreg140 [4176r,4192r:0)  0@4176r
%vreg143 [4592r,4608r:0)  0@4592r
%vreg146 [4688r,4704r:0)  0@4688r
%vreg150 [4880r,4896r:0)  0@4880r
%vreg152 [4864r,4896r:0)  0@4864r
%vreg153 [4848r,4864r:0)  0@4848r
%vreg157 [5008r,5024r:0)  0@5008r
%vreg159 [4992r,5024r:0)  0@4992r
%vreg160 [4976r,4992r:0)  0@4976r
%vreg164 [5136r,5152r:0)  0@5136r
%vreg166 [5120r,5152r:0)  0@5120r
%vreg167 [5104r,5120r:0)  0@5104r
%vreg171 [5264r,5280r:0)  0@5264r
%vreg173 [5248r,5280r:0)  0@5248r
%vreg174 [5232r,5248r:0)  0@5232r
%vreg177 [5360r,5376r:0)  0@5360r
%vreg180 [5456r,5472r:0)  0@5456r
%vreg183 [5680r,5728r:0)  0@5680r
%vreg186 [5616r,5616d:0)  0@5616r
%vreg188 [5504r,5536r:0)[5536r,5568r:1)  0@5504r 1@5536r
%vreg192 [1376r,1392r:0)  0@1376r
%vreg195 [1472r,1488r:0)  0@1472r
%vreg198 [656r,672r:0)  0@656r
%vreg201 [752r,768r:0)  0@752r
%vreg203 [5840r,5904r:0)  0@5840r
%vreg204 [5872r,5920r:0)  0@5872r
RegMasks: 320r 1184r 2304r 3120r 3376r 4032r 4240r 4400r 5584r 5744r 5936r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzWriteClose64: Post SSA
Frame Objects:
  fi#-2: size=8, align=8, fixed, at location [SP]
  fi#-1: size=8, align=16, fixed, at location [SP+8]
  fi#0: size=8, align=8, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=4, align=4, at location [SP+8]
  fi#3: size=8, align=8, at location [SP+8]
  fi#4: size=8, align=8, at location [SP+8]
  fi#5: size=8, align=8, at location [SP+8]
  fi#6: size=8, align=8, at location [SP+8]
  fi#7: size=4, align=4, at location [SP+8]
  fi#8: size=4, align=4, at location [SP+8]
  fi#9: size=4, align=4, at location [SP+8]
  fi#10: size=8, align=8, at location [SP+8]
Function Live Ins: %RDI in %vreg0, %RSI in %vreg1, %EDX in %vreg2, %RCX in %vreg3, %R8 in %vreg4, %R9 in %vreg5

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI %RSI %EDX %RCX %R8 %R9
16B		%vreg11<def> = COPY %R9; GR64:%vreg11
32B		%vreg10<def> = COPY %R8; GR64:%vreg10
48B		%vreg9<def> = COPY %RCX; GR64:%vreg9
64B		%vreg8<def> = COPY %EDX; GR32:%vreg8
80B		%vreg7<def> = COPY %RSI; GR64:%vreg7
96B		%vreg6<def> = COPY %RDI; GR64:%vreg6
112B		%vreg12<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg12
224B		%vreg19<def> = MOV64ri <ga:@BZ2_bzWriteClose64>; GR64:%vreg19
256B		%vreg20<def> = MOV64rm <fi#-2>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-2] GR64:%vreg20
272B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
288B		%RDI<def> = COPY %vreg19; GR64:%vreg19
304B		%RSI<def> = COPY %vreg20; GR64:%vreg20
320B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
336B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
352B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
368B		STACKMAP 0, 0, %vreg8, 0, <fi#2>, 0, %vreg7, 0, <fi#1>, 0, %vreg6, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, %vreg10, 0, <fi#4>, 0, %vreg9, 0, <fi#3>, 0, %vreg12, 0, <fi#6>, 0, %vreg11, 0, <fi#5>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4) GR32:%vreg8 GR64:%vreg7,%vreg6,%vreg10,%vreg9,%vreg12,%vreg11
384B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
400B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg6; mem:ST8[%bzerror.addr] GR64:%vreg6
416B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg7; mem:ST8[%b.addr] GR64:%vreg7
432B		MOV32mr <fi#2>, 1, %noreg, 0, %noreg, %vreg8; mem:ST4[%abandon.addr] GR32:%vreg8
448B		MOV64mr <fi#3>, 1, %noreg, 0, %noreg, %vreg9; mem:ST8[%nbytes_in_lo32.addr] GR64:%vreg9
464B		MOV64mr <fi#4>, 1, %noreg, 0, %noreg, %vreg10; mem:ST8[%nbytes_in_hi32.addr] GR64:%vreg10
480B		MOV64mr <fi#5>, 1, %noreg, 0, %noreg, %vreg11; mem:ST8[%nbytes_out_lo32.addr] GR64:%vreg11
496B		MOV64mr <fi#6>, 1, %noreg, 0, %noreg, %vreg12; mem:ST8[%nbytes_out_hi32.addr] GR64:%vreg12
512B		%vreg16<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr] GR64:%vreg16
544B		MOV64mr <fi#10>, 1, %noreg, 0, %noreg, %vreg16; mem:ST8[%bzf] GR64:%vreg16
560B		CMP64mi8 <fi#10>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
576B		JNE_1 <BB#6>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#6 BB#1

592B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
608B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
624B		JE_1 <BB#3>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#3 BB#2

640B	BB#2: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#1
656B		%vreg198<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg198
672B		MOV32mi %vreg198, 1, %noreg, 0, %noreg, 0; mem:ST4[%4] GR64:%vreg198
	    Successors according to CFG: BB#3

688B	BB#3: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#1 BB#2
704B		CMP64mi8 <fi#10>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
720B		JE_1 <BB#5>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#5 BB#4

736B	BB#4: derived from LLVM BB %if.then.4
	    Predecessors according to CFG: BB#3
752B		%vreg201<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg201
768B		MOV32mi %vreg201, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr] GR64:%vreg201
	    Successors according to CFG: BB#5

784B	BB#5: derived from LLVM BB %if.end.5
	    Predecessors according to CFG: BB#3 BB#4
800B		JMP_1 <BB#71>
	    Successors according to CFG: BB#71

816B	BB#6: derived from LLVM BB %if.end.6
	    Predecessors according to CFG: BB#0
832B		%vreg23<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg23
848B		CMP8mi %vreg23, 1, %noreg, 5012, %noreg, 0, %EFLAGS<imp-def>; mem:LD1[%writing] GR64:%vreg23
864B		JNE_1 <BB#12>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#12 BB#7

880B	BB#7: derived from LLVM BB %if.then.7
	    Predecessors according to CFG: BB#6
896B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
912B		JE_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#8

928B	BB#8: derived from LLVM BB %if.then.9
	    Predecessors according to CFG: BB#7
944B		%vreg26<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg26
960B		MOV32mi %vreg26, 1, %noreg, 0, %noreg, -1; mem:ST4[%10] GR64:%vreg26
	    Successors according to CFG: BB#9

976B	BB#9: derived from LLVM BB %if.end.10
	    Predecessors according to CFG: BB#7 BB#8
992B		CMP64mi8 <fi#10>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
1008B		JE_1 <BB#11>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#11 BB#10

1024B	BB#10: derived from LLVM BB %if.then.12
	    Predecessors according to CFG: BB#9
1040B		%vreg29<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg29
1056B		MOV32mi %vreg29, 1, %noreg, 5096, %noreg, -1; mem:ST4[%lastErr13] GR64:%vreg29
	    Successors according to CFG: BB#11

1072B	BB#11: derived from LLVM BB %if.end.14
	    Predecessors according to CFG: BB#9 BB#10
1088B		JMP_1 <BB#71>
	    Successors according to CFG: BB#71

1104B	BB#12: derived from LLVM BB %if.end.15
	    Predecessors according to CFG: BB#6
1120B		%vreg35<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg35
1136B		%vreg34<def> = MOV64rm %vreg35, 1, %noreg, 0, %noreg; mem:LD8[%handle] GR64:%vreg34,%vreg35
1152B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1168B		%RDI<def> = COPY %vreg34; GR64:%vreg34
1184B		CALL64pcrel32 <ga:@ferror>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
1200B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1216B		%vreg32<def> = COPY %EAX<kill>; GR32:%vreg32
1232B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1248B		STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4)
1264B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1280B		CMP32ri8 %vreg32, 0, %EFLAGS<imp-def>; GR32:%vreg32
1296B		JE_1 <BB#18>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#18 BB#13

1312B	BB#13: derived from LLVM BB %if.then.17
	    Predecessors according to CFG: BB#12
1328B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
1344B		JE_1 <BB#15>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#15 BB#14

1360B	BB#14: derived from LLVM BB %if.then.19
	    Predecessors according to CFG: BB#13
1376B		%vreg192<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg192
1392B		MOV32mi %vreg192, 1, %noreg, 0, %noreg, -6; mem:ST4[%16] GR64:%vreg192
	    Successors according to CFG: BB#15

1408B	BB#15: derived from LLVM BB %if.end.20
	    Predecessors according to CFG: BB#13 BB#14
1424B		CMP64mi8 <fi#10>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
1440B		JE_1 <BB#17>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#17 BB#16

1456B	BB#16: derived from LLVM BB %if.then.22
	    Predecessors according to CFG: BB#15
1472B		%vreg195<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg195
1488B		MOV32mi %vreg195, 1, %noreg, 5096, %noreg, -6; mem:ST4[%lastErr23] GR64:%vreg195
	    Successors according to CFG: BB#17

1504B	BB#17: derived from LLVM BB %if.end.24
	    Predecessors according to CFG: BB#15 BB#16
1520B		JMP_1 <BB#71>
	    Successors according to CFG: BB#71

1536B	BB#18: derived from LLVM BB %if.end.25
	    Predecessors according to CFG: BB#12
1552B		CMP64mi8 <fi#3>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%nbytes_in_lo32.addr]
1568B		JE_1 <BB#20>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#20 BB#19

1584B	BB#19: derived from LLVM BB %if.then.27
	    Predecessors according to CFG: BB#18
1600B		%vreg38<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%nbytes_in_lo32.addr] GR64:%vreg38
1616B		MOV32mi %vreg38, 1, %noreg, 0, %noreg, 0; mem:ST4[%20] GR64:%vreg38
	    Successors according to CFG: BB#20

1632B	BB#20: derived from LLVM BB %if.end.28
	    Predecessors according to CFG: BB#18 BB#19
1648B		CMP64mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%nbytes_in_hi32.addr]
1664B		JE_1 <BB#22>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#22 BB#21

1680B	BB#21: derived from LLVM BB %if.then.30
	    Predecessors according to CFG: BB#20
1696B		%vreg41<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%nbytes_in_hi32.addr] GR64:%vreg41
1712B		MOV32mi %vreg41, 1, %noreg, 0, %noreg, 0; mem:ST4[%22] GR64:%vreg41
	    Successors according to CFG: BB#22

1728B	BB#22: derived from LLVM BB %if.end.31
	    Predecessors according to CFG: BB#20 BB#21
1744B		CMP64mi8 <fi#5>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%nbytes_out_lo32.addr]
1760B		JE_1 <BB#24>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#24 BB#23

1776B	BB#23: derived from LLVM BB %if.then.33
	    Predecessors according to CFG: BB#22
1792B		%vreg44<def> = MOV64rm <fi#5>, 1, %noreg, 0, %noreg; mem:LD8[%nbytes_out_lo32.addr] GR64:%vreg44
1808B		MOV32mi %vreg44, 1, %noreg, 0, %noreg, 0; mem:ST4[%24] GR64:%vreg44
	    Successors according to CFG: BB#24

1824B	BB#24: derived from LLVM BB %if.end.34
	    Predecessors according to CFG: BB#22 BB#23
1840B		CMP64mi8 <fi#6>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%nbytes_out_hi32.addr]
1856B		JE_1 <BB#26>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#26 BB#25

1872B	BB#25: derived from LLVM BB %if.then.36
	    Predecessors according to CFG: BB#24
1888B		%vreg47<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%nbytes_out_hi32.addr] GR64:%vreg47
1904B		MOV32mi %vreg47, 1, %noreg, 0, %noreg, 0; mem:ST4[%26] GR64:%vreg47
	    Successors according to CFG: BB#26

1920B	BB#26: derived from LLVM BB %if.end.37
	    Predecessors according to CFG: BB#24 BB#25
1936B		CMP32mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%abandon.addr]
1952B		JNE_1 <BB#49>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#49 BB#27

1968B	BB#27: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#26
1984B		%vreg51<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg51
2000B		CMP32mi8 %vreg51, 1, %noreg, 5096, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%lastErr39] GR64:%vreg51
2016B		JNE_1 <BB#49>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#49 BB#28

2032B	BB#28: derived from LLVM BB %if.then.41
	    Predecessors according to CFG: BB#27
2048B		JMP_1 <BB#29>
	    Successors according to CFG: BB#29

2064B	BB#29: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#28 BB#47
2096B		%vreg68<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg68
2112B		MOV32mi %vreg68, 1, %noreg, 5048, %noreg, 5000; mem:ST4[%avail_out] GR64:%vreg68
2128B		%vreg65<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg65
2160B		%vreg65<def,tied1> = ADD64ri8 %vreg65<tied0>, 8, %EFLAGS<imp-def,dead>; GR64:%vreg65
2176B		%vreg62<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg62
2192B		MOV64mr %vreg62, 1, %noreg, 5040, %noreg, %vreg65; mem:ST8[%next_out] GR64:%vreg62,%vreg65
2208B		%vreg58<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg58
2240B		%vreg58<def,tied1> = ADD64ri32 %vreg58<tied0>, 5016, %EFLAGS<imp-def,dead>; GR64:%vreg58
2256B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2272B		%RDI<def> = COPY %vreg58; GR64:%vreg58
2288B		%ESI<def> = MOV32ri 2
2304B		CALL64pcrel32 <ga:@BZ2_bzCompress>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %EAX<imp-def>
2320B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2336B		%vreg56<def> = COPY %EAX<kill>; GR32:%vreg56
2352B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2368B		STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4)
2384B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2400B		MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %vreg56; mem:ST4[%ret] GR32:%vreg56
2416B		CMP32mi8 <fi#9>, 1, %noreg, 0, %noreg, 3, %EFLAGS<imp-def>; mem:LD4[%ret]
2432B		JE_1 <BB#36>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#36 BB#30

2448B	BB#30: derived from LLVM BB %land.lhs.true.46
	    Predecessors according to CFG: BB#29
2464B		CMP32mi8 <fi#9>, 1, %noreg, 0, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%ret]
2480B		JE_1 <BB#36>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#36 BB#31

2496B	BB#31: derived from LLVM BB %if.then.48
	    Predecessors according to CFG: BB#30
2512B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
2528B		JE_1 <BB#33>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#33 BB#32

2544B	BB#32: derived from LLVM BB %if.then.50
	    Predecessors according to CFG: BB#31
2560B		%vreg117<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%ret] GR32:%vreg117
2576B		%vreg116<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg116
2592B		MOV32mr %vreg116, 1, %noreg, 0, %noreg, %vreg117; mem:ST4[%38] GR64:%vreg116 GR32:%vreg117
	    Successors according to CFG: BB#33

2608B	BB#33: derived from LLVM BB %if.end.51
	    Predecessors according to CFG: BB#31 BB#32
2624B		CMP64mi8 <fi#10>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
2640B		JE_1 <BB#35>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#35 BB#34

2656B	BB#34: derived from LLVM BB %if.then.53
	    Predecessors according to CFG: BB#33
2672B		%vreg122<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%ret] GR32:%vreg122
2688B		%vreg121<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg121
2704B		MOV32mr %vreg121, 1, %noreg, 5096, %noreg, %vreg122; mem:ST4[%lastErr54] GR64:%vreg121 GR32:%vreg122
	    Successors according to CFG: BB#35

2720B	BB#35: derived from LLVM BB %if.end.55
	    Predecessors according to CFG: BB#33 BB#34
2736B		JMP_1 <BB#71>
	    Successors according to CFG: BB#71

2752B	BB#36: derived from LLVM BB %if.end.56
	    Predecessors according to CFG: BB#29 BB#30
2768B		%vreg72<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg72
2784B		CMP32mi %vreg72, 1, %noreg, 5048, %noreg, 5000, %EFLAGS<imp-def>; mem:LD4[%avail_out58] GR64:%vreg72
2800B		JAE_1 <BB#45>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#45 BB#37

2816B	BB#37: derived from LLVM BB %if.then.60
	    Predecessors according to CFG: BB#36
2864B		%vreg97<def> = MOV32ri 5000; GR32:%vreg97
2880B		%vreg99<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg99
2912B		%vreg97<def,tied1> = SUB32rm %vreg97<tied0>, %vreg99, 1, %noreg, 5048, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%avail_out62] GR32:%vreg97 GR64:%vreg99
2928B		MOV32mr <fi#7>, 1, %noreg, 0, %noreg, %vreg97; mem:ST4[%n] GR32:%vreg97
2944B		%vreg92<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg92
2976B		%vreg92<def,tied1> = ADD64ri8 %vreg92<tied0>, 8, %EFLAGS<imp-def,dead>; GR64:%vreg92
2992B		%vreg89<def> = MOVSX64rm32 <fi#7>, 1, %noreg, 0, %noreg; mem:LD4[%n] GR64:%vreg89
3008B		%vreg87<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg87
3024B		%vreg86<def> = MOV64rm %vreg87, 1, %noreg, 0, %noreg; mem:LD8[%handle65] GR64:%vreg86,%vreg87
3040B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3056B		%RDI<def> = COPY %vreg92; GR64:%vreg92
3072B		%ESI<def,dead> = MOV32ri 1, %RSI<imp-def>
3088B		%RDX<def> = COPY %vreg89; GR64:%vreg89
3104B		%RCX<def> = COPY %vreg86; GR64:%vreg86
3120B		CALL64pcrel32 <ga:@fwrite>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %RDX<imp-use>, %RCX<imp-use>, %RAX<imp-def>
3136B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3152B		%vreg84<def> = COPY %RAX<kill>; GR64_with_sub_8bit:%vreg84
3168B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3184B		STACKMAP 3, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4)
3200B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3232B		MOV32mr <fi#8>, 1, %noreg, 0, %noreg, %vreg84:sub_32bit; mem:ST4[%n2] GR64_with_sub_8bit:%vreg84
3248B		%vreg75<def> = MOV32rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD4[%n] GR32:%vreg75
3264B		CMP32rm %vreg75, <fi#8>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD4[%n2] GR32:%vreg75
3280B		JNE_1 <BB#39>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#39 BB#38

3296B	BB#38: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#37
3312B		%vreg105<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg105
3328B		%vreg104<def> = MOV64rm %vreg105, 1, %noreg, 0, %noreg; mem:LD8[%handle70] GR64:%vreg104,%vreg105
3344B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3360B		%RDI<def> = COPY %vreg104; GR64:%vreg104
3376B		CALL64pcrel32 <ga:@ferror>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
3392B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3408B		%vreg102<def> = COPY %EAX<kill>; GR32:%vreg102
3424B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3440B		STACKMAP 4, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4)
3456B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3472B		CMP32ri8 %vreg102, 0, %EFLAGS<imp-def>; GR32:%vreg102
3488B		JE_1 <BB#44>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#44 BB#39

3504B	BB#39: derived from LLVM BB %if.then.73
	    Predecessors according to CFG: BB#37 BB#38
3520B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
3536B		JE_1 <BB#41>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#41 BB#40

3552B	BB#40: derived from LLVM BB %if.then.76
	    Predecessors according to CFG: BB#39
3568B		%vreg109<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg109
3584B		MOV32mi %vreg109, 1, %noreg, 0, %noreg, -6; mem:ST4[%55] GR64:%vreg109
	    Successors according to CFG: BB#41

3600B	BB#41: derived from LLVM BB %if.end.77
	    Predecessors according to CFG: BB#39 BB#40
3616B		CMP64mi8 <fi#10>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
3632B		JE_1 <BB#43>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#43 BB#42

3648B	BB#42: derived from LLVM BB %if.then.80
	    Predecessors according to CFG: BB#41
3664B		%vreg112<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg112
3680B		MOV32mi %vreg112, 1, %noreg, 5096, %noreg, -6; mem:ST4[%lastErr81] GR64:%vreg112
	    Successors according to CFG: BB#43

3696B	BB#43: derived from LLVM BB %if.end.82
	    Predecessors according to CFG: BB#41 BB#42
3712B		JMP_1 <BB#71>
	    Successors according to CFG: BB#71

3728B	BB#44: derived from LLVM BB %if.end.83
	    Predecessors according to CFG: BB#38
3744B		JMP_1 <BB#45>
	    Successors according to CFG: BB#45

3760B	BB#45: derived from LLVM BB %if.end.84
	    Predecessors according to CFG: BB#36 BB#44
3776B		CMP32mi8 <fi#9>, 1, %noreg, 0, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%ret]
3792B		JNE_1 <BB#47>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#47 BB#46

3808B	BB#46: derived from LLVM BB %if.then.87
	    Predecessors according to CFG: BB#45
3824B		JMP_1 <BB#48>
	    Successors according to CFG: BB#48

3840B	BB#47: derived from LLVM BB %if.end.88
	    Predecessors according to CFG: BB#45
3856B		JMP_1 <BB#29>
	    Successors according to CFG: BB#29

3872B	BB#48: derived from LLVM BB %while.end
	    Predecessors according to CFG: BB#46
3888B		JMP_1 <BB#49>
	    Successors according to CFG: BB#49

3904B	BB#49: derived from LLVM BB %if.end.89
	    Predecessors according to CFG: BB#26 BB#27 BB#48
3920B		CMP32mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%abandon.addr]
3936B		JNE_1 <BB#58>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#58 BB#50

3952B	BB#50: derived from LLVM BB %land.lhs.true.91
	    Predecessors according to CFG: BB#49
3968B		%vreg129<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg129
3984B		%vreg128<def> = MOV64rm %vreg129, 1, %noreg, 0, %noreg; mem:LD8[%handle92] GR64:%vreg128,%vreg129
4000B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4016B		%RDI<def> = COPY %vreg128; GR64:%vreg128
4032B		CALL64pcrel32 <ga:@ferror>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
4048B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4064B		%vreg126<def> = COPY %EAX<kill>; GR32:%vreg126
4080B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4096B		STACKMAP 5, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, ...; mem:LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5]
4112B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4128B		CMP32ri8 %vreg126, 0, %EFLAGS<imp-def>; GR32:%vreg126
4144B		JNE_1 <BB#58>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#58 BB#51

4160B	BB#51: derived from LLVM BB %if.then.95
	    Predecessors according to CFG: BB#50
4176B		%vreg140<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg140
4192B		%vreg139<def> = MOV64rm %vreg140, 1, %noreg, 0, %noreg; mem:LD8[%handle96] GR64:%vreg139,%vreg140
4208B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4224B		%RDI<def> = COPY %vreg139; GR64:%vreg139
4240B		CALL64pcrel32 <ga:@fflush>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
4256B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4272B		%vreg137<def,dead> = COPY %EAX<kill>; GR32:%vreg137
4288B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4304B		STACKMAP 6, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, ...; mem:LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5]
4320B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4336B		%vreg135<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg135
4352B		%vreg134<def> = MOV64rm %vreg135, 1, %noreg, 0, %noreg; mem:LD8[%handle98] GR64:%vreg134,%vreg135
4368B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4384B		%RDI<def> = COPY %vreg134; GR64:%vreg134
4400B		CALL64pcrel32 <ga:@ferror>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
4416B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4432B		%vreg132<def> = COPY %EAX<kill>; GR32:%vreg132
4448B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4464B		STACKMAP 7, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, ...; mem:LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5]
4480B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4496B		CMP32ri8 %vreg132, 0, %EFLAGS<imp-def>; GR32:%vreg132
4512B		JE_1 <BB#57>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#57 BB#52

4528B	BB#52: derived from LLVM BB %if.then.101
	    Predecessors according to CFG: BB#51
4544B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
4560B		JE_1 <BB#54>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#54 BB#53

4576B	BB#53: derived from LLVM BB %if.then.104
	    Predecessors according to CFG: BB#52
4592B		%vreg143<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg143
4608B		MOV32mi %vreg143, 1, %noreg, 0, %noreg, -6; mem:ST4[%67] GR64:%vreg143
	    Successors according to CFG: BB#54

4624B	BB#54: derived from LLVM BB %if.end.105
	    Predecessors according to CFG: BB#52 BB#53
4640B		CMP64mi8 <fi#10>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
4656B		JE_1 <BB#56>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#56 BB#55

4672B	BB#55: derived from LLVM BB %if.then.108
	    Predecessors according to CFG: BB#54
4688B		%vreg146<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg146
4704B		MOV32mi %vreg146, 1, %noreg, 5096, %noreg, -6; mem:ST4[%lastErr109] GR64:%vreg146
	    Successors according to CFG: BB#56

4720B	BB#56: derived from LLVM BB %if.end.110
	    Predecessors according to CFG: BB#54 BB#55
4736B		JMP_1 <BB#71>
	    Successors according to CFG: BB#71

4752B	BB#57: derived from LLVM BB %if.end.111
	    Predecessors according to CFG: BB#51
4768B		JMP_1 <BB#58>
	    Successors according to CFG: BB#58

4784B	BB#58: derived from LLVM BB %if.end.112
	    Predecessors according to CFG: BB#49 BB#50 BB#57
4800B		CMP64mi8 <fi#3>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%nbytes_in_lo32.addr]
4816B		JE_1 <BB#60>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#60 BB#59

4832B	BB#59: derived from LLVM BB %if.then.115
	    Predecessors according to CFG: BB#58
4848B		%vreg153<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg153
4864B		%vreg152<def> = MOV32rm %vreg153, 1, %noreg, 5028, %noreg; mem:LD4[%total_in_lo32] GR32:%vreg152 GR64:%vreg153
4880B		%vreg150<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%nbytes_in_lo32.addr] GR64:%vreg150
4896B		MOV32mr %vreg150, 1, %noreg, 0, %noreg, %vreg152; mem:ST4[%73] GR64:%vreg150 GR32:%vreg152
	    Successors according to CFG: BB#60

4912B	BB#60: derived from LLVM BB %if.end.117
	    Predecessors according to CFG: BB#58 BB#59
4928B		CMP64mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%nbytes_in_hi32.addr]
4944B		JE_1 <BB#62>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#62 BB#61

4960B	BB#61: derived from LLVM BB %if.then.120
	    Predecessors according to CFG: BB#60
4976B		%vreg160<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg160
4992B		%vreg159<def> = MOV32rm %vreg160, 1, %noreg, 5032, %noreg; mem:LD4[%total_in_hi32] GR32:%vreg159 GR64:%vreg160
5008B		%vreg157<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%nbytes_in_hi32.addr] GR64:%vreg157
5024B		MOV32mr %vreg157, 1, %noreg, 0, %noreg, %vreg159; mem:ST4[%77] GR64:%vreg157 GR32:%vreg159
	    Successors according to CFG: BB#62

5040B	BB#62: derived from LLVM BB %if.end.122
	    Predecessors according to CFG: BB#60 BB#61
5056B		CMP64mi8 <fi#5>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%nbytes_out_lo32.addr]
5072B		JE_1 <BB#64>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#64 BB#63

5088B	BB#63: derived from LLVM BB %if.then.125
	    Predecessors according to CFG: BB#62
5104B		%vreg167<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg167
5120B		%vreg166<def> = MOV32rm %vreg167, 1, %noreg, 5052, %noreg; mem:LD4[%total_out_lo32] GR32:%vreg166 GR64:%vreg167
5136B		%vreg164<def> = MOV64rm <fi#5>, 1, %noreg, 0, %noreg; mem:LD8[%nbytes_out_lo32.addr] GR64:%vreg164
5152B		MOV32mr %vreg164, 1, %noreg, 0, %noreg, %vreg166; mem:ST4[%81] GR64:%vreg164 GR32:%vreg166
	    Successors according to CFG: BB#64

5168B	BB#64: derived from LLVM BB %if.end.127
	    Predecessors according to CFG: BB#62 BB#63
5184B		CMP64mi8 <fi#6>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%nbytes_out_hi32.addr]
5200B		JE_1 <BB#66>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#66 BB#65

5216B	BB#65: derived from LLVM BB %if.then.130
	    Predecessors according to CFG: BB#64
5232B		%vreg174<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg174
5248B		%vreg173<def> = MOV32rm %vreg174, 1, %noreg, 5056, %noreg; mem:LD4[%total_out_hi32] GR32:%vreg173 GR64:%vreg174
5264B		%vreg171<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%nbytes_out_hi32.addr] GR64:%vreg171
5280B		MOV32mr %vreg171, 1, %noreg, 0, %noreg, %vreg173; mem:ST4[%85] GR64:%vreg171 GR32:%vreg173
	    Successors according to CFG: BB#66

5296B	BB#66: derived from LLVM BB %if.end.132
	    Predecessors according to CFG: BB#64 BB#65
5312B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
5328B		JE_1 <BB#68>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#68 BB#67

5344B	BB#67: derived from LLVM BB %if.then.135
	    Predecessors according to CFG: BB#66
5360B		%vreg177<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg177
5376B		MOV32mi %vreg177, 1, %noreg, 0, %noreg, 0; mem:ST4[%87] GR64:%vreg177
	    Successors according to CFG: BB#68

5392B	BB#68: derived from LLVM BB %if.end.136
	    Predecessors according to CFG: BB#66 BB#67
5408B		CMP64mi8 <fi#10>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
5424B		JE_1 <BB#70>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#70 BB#69

5440B	BB#69: derived from LLVM BB %if.then.139
	    Predecessors according to CFG: BB#68
5456B		%vreg180<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg180
5472B		MOV32mi %vreg180, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr140] GR64:%vreg180
	    Successors according to CFG: BB#70

5488B	BB#70: derived from LLVM BB %if.end.141
	    Predecessors according to CFG: BB#68 BB#69
5504B		%vreg188<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg188
5536B		%vreg188<def,tied1> = ADD64ri32 %vreg188<tied0>, 5016, %EFLAGS<imp-def,dead>; GR64:%vreg188
5552B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5568B		%RDI<def> = COPY %vreg188; GR64:%vreg188
5584B		CALL64pcrel32 <ga:@BZ2_bzCompressEnd>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
5600B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5616B		%vreg186<def,dead> = COPY %EAX<kill>; GR32:%vreg186
5632B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5648B		STACKMAP 8, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack10]
5664B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5680B		%vreg183<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg183
5712B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5728B		%RDI<def> = COPY %vreg183; GR64:%vreg183
5744B		CALL64pcrel32 <ga:@free>, <regmask>, %RSP<imp-use>, %RDI<imp-use>
5760B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5776B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5792B		STACKMAP 9, 0, ...
5808B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#71

5824B	BB#71: derived from LLVM BB %return
	    Predecessors according to CFG: BB#11 BB#43 BB#35 BB#56 BB#70 BB#17 BB#5
5840B		%vreg203<def> = MOV64ri <ga:@BZ2_bzWriteClose64>; GR64:%vreg203
5872B		%vreg204<def> = MOV64rm <fi#-2>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-2] GR64:%vreg204
5888B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5904B		%RDI<def> = COPY %vreg203; GR64:%vreg203
5920B		%RSI<def> = COPY %vreg204; GR64:%vreg204
5936B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
5952B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5968B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5984B		STACKMAP 10, 0, ...
6000B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
6016B		RETQ

# End machine code for function BZ2_bzWriteClose64.

AllocationOrder(SEGMENT_REG) = [ ]
AllocationOrder(SEGMENT_REG) = [ ]
handleMove 2272B -> 2296B: %RDI<def> = COPY %vreg58; GR64:%vreg58
     DIL:	[0B,96r:0)[288r,320r:11)[1168r,1184r:10)[2272r,2304r:9)[3056r,3120r:8)[3360r,3376r:7)[4016r,4032r:6)[4224r,4240r:4)[4384r,4400r:5)[5568r,5584r:2)[5728r,5744r:3)[5904r,5936r:1)  0@0B-phi 1@5904r 2@5568r 3@5728r 4@4224r 5@4384r 6@4016r 7@3360r 8@3056r 9@2272r 10@1168r 11@288r
        -->	[0B,96r:0)[288r,320r:11)[1168r,1184r:10)[2296r,2304r:9)[3056r,3120r:8)[3360r,3376r:7)[4016r,4032r:6)[4224r,4240r:4)[4384r,4400r:5)[5568r,5584r:2)[5728r,5744r:3)[5904r,5936r:1)  0@0B-phi 1@5904r 2@5568r 3@5728r 4@4224r 5@4384r 6@4016r 7@3360r 8@3056r 9@2296r 10@1168r 11@288r
     %vreg58:	[2208r,2240r:0)[2240r,2272r:1)  0@2208r 1@2240r
        -->	[2208r,2240r:0)[2240r,2296r:1)  0@2208r 1@2240r
AllocationOrder(SEGMENT_REG) = [ ]
handleMove 3056B -> 3080B: %RDI<def> = COPY %vreg92; GR64:%vreg92
     DIL:	[0B,96r:0)[288r,320r:11)[1168r,1184r:10)[2296r,2304r:9)[3056r,3120r:8)[3360r,3376r:7)[4016r,4032r:6)[4224r,4240r:4)[4384r,4400r:5)[5568r,5584r:2)[5728r,5744r:3)[5904r,5936r:1)  0@0B-phi 1@5904r 2@5568r 3@5728r 4@4224r 5@4384r 6@4016r 7@3360r 8@3056r 9@2296r 10@1168r 11@288r
        -->	[0B,96r:0)[288r,320r:11)[1168r,1184r:10)[2296r,2304r:9)[3080r,3120r:8)[3360r,3376r:7)[4016r,4032r:6)[4224r,4240r:4)[4384r,4400r:5)[5568r,5584r:2)[5728r,5744r:3)[5904r,5936r:1)  0@0B-phi 1@5904r 2@5568r 3@5728r 4@4224r 5@4384r 6@4016r 7@3360r 8@3080r 9@2296r 10@1168r 11@288r
     %vreg92:	[2944r,2976r:0)[2976r,3056r:1)  0@2944r 1@2976r
        -->	[2944r,2976r:0)[2976r,3080r:1)  0@2944r 1@2976r
AllocationOrder(SEGMENT_REG) = [ ]
********** GREEDY REGISTER ALLOCATION **********
********** Function: BZ2_bzWriteClose64
********** INTERVALS **********
CH [0B,48r:0)[3104r,3120r:1)  0@0B-phi 1@3104r
CL [0B,48r:0)[3104r,3120r:1)  0@0B-phi 1@3104r
DH [0B,64r:0)[3088r,3120r:1)  0@0B-phi 1@3088r
DIL [0B,96r:0)[288r,320r:11)[1168r,1184r:10)[2296r,2304r:9)[3080r,3120r:8)[3360r,3376r:7)[4016r,4032r:6)[4224r,4240r:4)[4384r,4400r:5)[5568r,5584r:2)[5728r,5744r:3)[5904r,5936r:1)  0@0B-phi 1@5904r 2@5568r 3@5728r 4@4224r 5@4384r 6@4016r 7@3360r 8@3080r 9@2296r 10@1168r 11@288r
DL [0B,64r:0)[3088r,3120r:1)  0@0B-phi 1@3088r
SIL [0B,80r:0)[304r,320r:4)[2288r,2304r:1)[3072r,3120r:3)[5920r,5936r:2)  0@0B-phi 1@2288r 2@5920r 3@3072r 4@304r
R8B [0B,32r:0)  0@0B-phi
R9B [0B,16r:0)  0@0B-phi
%vreg6 [96r,400r:0)  0@96r
%vreg7 [80r,416r:0)  0@80r
%vreg8 [64r,432r:0)  0@64r
%vreg9 [48r,448r:0)  0@48r
%vreg10 [32r,464r:0)  0@32r
%vreg11 [16r,480r:0)  0@16r
%vreg12 [112r,496r:0)  0@112r
%vreg16 [512r,544r:0)  0@512r
%vreg19 [224r,288r:0)  0@224r
%vreg20 [256r,304r:0)  0@256r
%vreg23 [832r,848r:0)  0@832r
%vreg26 [944r,960r:0)  0@944r
%vreg29 [1040r,1056r:0)  0@1040r
%vreg32 [1216r,1280r:0)  0@1216r
%vreg34 [1136r,1168r:0)  0@1136r
%vreg35 [1120r,1136r:0)  0@1120r
%vreg38 [1600r,1616r:0)  0@1600r
%vreg41 [1696r,1712r:0)  0@1696r
%vreg44 [1792r,1808r:0)  0@1792r
%vreg47 [1888r,1904r:0)  0@1888r
%vreg51 [1984r,2000r:0)  0@1984r
%vreg56 [2336r,2400r:0)  0@2336r
%vreg58 [2208r,2240r:0)[2240r,2296r:1)  0@2208r 1@2240r
%vreg62 [2176r,2192r:0)  0@2176r
%vreg65 [2128r,2160r:0)[2160r,2192r:1)  0@2128r 1@2160r
%vreg68 [2096r,2112r:0)  0@2096r
%vreg72 [2768r,2784r:0)  0@2768r
%vreg75 [3248r,3264r:0)  0@3248r
%vreg84 [3152r,3232r:0)  0@3152r
%vreg86 [3024r,3104r:0)  0@3024r
%vreg87 [3008r,3024r:0)  0@3008r
%vreg89 [2992r,3088r:0)  0@2992r
%vreg92 [2944r,2976r:0)[2976r,3080r:1)  0@2944r 1@2976r
%vreg97 [2864r,2912r:0)[2912r,2928r:1)  0@2864r 1@2912r
%vreg99 [2880r,2912r:0)  0@2880r
%vreg102 [3408r,3472r:0)  0@3408r
%vreg104 [3328r,3360r:0)  0@3328r
%vreg105 [3312r,3328r:0)  0@3312r
%vreg109 [3568r,3584r:0)  0@3568r
%vreg112 [3664r,3680r:0)  0@3664r
%vreg116 [2576r,2592r:0)  0@2576r
%vreg117 [2560r,2592r:0)  0@2560r
%vreg121 [2688r,2704r:0)  0@2688r
%vreg122 [2672r,2704r:0)  0@2672r
%vreg126 [4064r,4128r:0)  0@4064r
%vreg128 [3984r,4016r:0)  0@3984r
%vreg129 [3968r,3984r:0)  0@3968r
%vreg132 [4432r,4496r:0)  0@4432r
%vreg134 [4352r,4384r:0)  0@4352r
%vreg135 [4336r,4352r:0)  0@4336r
%vreg137 [4272r,4272d:0)  0@4272r
%vreg139 [4192r,4224r:0)  0@4192r
%vreg140 [4176r,4192r:0)  0@4176r
%vreg143 [4592r,4608r:0)  0@4592r
%vreg146 [4688r,4704r:0)  0@4688r
%vreg150 [4880r,4896r:0)  0@4880r
%vreg152 [4864r,4896r:0)  0@4864r
%vreg153 [4848r,4864r:0)  0@4848r
%vreg157 [5008r,5024r:0)  0@5008r
%vreg159 [4992r,5024r:0)  0@4992r
%vreg160 [4976r,4992r:0)  0@4976r
%vreg164 [5136r,5152r:0)  0@5136r
%vreg166 [5120r,5152r:0)  0@5120r
%vreg167 [5104r,5120r:0)  0@5104r
%vreg171 [5264r,5280r:0)  0@5264r
%vreg173 [5248r,5280r:0)  0@5248r
%vreg174 [5232r,5248r:0)  0@5232r
%vreg177 [5360r,5376r:0)  0@5360r
%vreg180 [5456r,5472r:0)  0@5456r
%vreg183 [5680r,5728r:0)  0@5680r
%vreg186 [5616r,5616d:0)  0@5616r
%vreg188 [5504r,5536r:0)[5536r,5568r:1)  0@5504r 1@5536r
%vreg192 [1376r,1392r:0)  0@1376r
%vreg195 [1472r,1488r:0)  0@1472r
%vreg198 [656r,672r:0)  0@656r
%vreg201 [752r,768r:0)  0@752r
%vreg203 [5840r,5904r:0)  0@5840r
%vreg204 [5872r,5920r:0)  0@5872r
RegMasks: 320r 1184r 2304r 3120r 3376r 4032r 4240r 4400r 5584r 5744r 5936r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzWriteClose64: Post SSA
Frame Objects:
  fi#-2: size=8, align=8, fixed, at location [SP]
  fi#-1: size=8, align=16, fixed, at location [SP+8]
  fi#0: size=8, align=8, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=4, align=4, at location [SP+8]
  fi#3: size=8, align=8, at location [SP+8]
  fi#4: size=8, align=8, at location [SP+8]
  fi#5: size=8, align=8, at location [SP+8]
  fi#6: size=8, align=8, at location [SP+8]
  fi#7: size=4, align=4, at location [SP+8]
  fi#8: size=4, align=4, at location [SP+8]
  fi#9: size=4, align=4, at location [SP+8]
  fi#10: size=8, align=8, at location [SP+8]
Function Live Ins: %RDI in %vreg0, %RSI in %vreg1, %EDX in %vreg2, %RCX in %vreg3, %R8 in %vreg4, %R9 in %vreg5

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI %RSI %EDX %RCX %R8 %R9
16B		%vreg11<def> = COPY %R9; GR64:%vreg11
32B		%vreg10<def> = COPY %R8; GR64:%vreg10
48B		%vreg9<def> = COPY %RCX; GR64:%vreg9
64B		%vreg8<def> = COPY %EDX; GR32:%vreg8
80B		%vreg7<def> = COPY %RSI; GR64:%vreg7
96B		%vreg6<def> = COPY %RDI; GR64:%vreg6
112B		%vreg12<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg12
224B		%vreg19<def> = MOV64ri <ga:@BZ2_bzWriteClose64>; GR64:%vreg19
256B		%vreg20<def> = MOV64rm <fi#-2>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-2] GR64:%vreg20
272B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
288B		%RDI<def> = COPY %vreg19; GR64:%vreg19
304B		%RSI<def> = COPY %vreg20; GR64:%vreg20
320B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
336B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
352B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
368B		STACKMAP 0, 0, %vreg8, 0, <fi#2>, 0, %vreg7, 0, <fi#1>, 0, %vreg6, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, %vreg10, 0, <fi#4>, 0, %vreg9, 0, <fi#3>, 0, %vreg12, 0, <fi#6>, 0, %vreg11, 0, <fi#5>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4) GR32:%vreg8 GR64:%vreg7,%vreg6,%vreg10,%vreg9,%vreg12,%vreg11
384B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
400B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg6; mem:ST8[%bzerror.addr] GR64:%vreg6
416B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg7; mem:ST8[%b.addr] GR64:%vreg7
432B		MOV32mr <fi#2>, 1, %noreg, 0, %noreg, %vreg8; mem:ST4[%abandon.addr] GR32:%vreg8
448B		MOV64mr <fi#3>, 1, %noreg, 0, %noreg, %vreg9; mem:ST8[%nbytes_in_lo32.addr] GR64:%vreg9
464B		MOV64mr <fi#4>, 1, %noreg, 0, %noreg, %vreg10; mem:ST8[%nbytes_in_hi32.addr] GR64:%vreg10
480B		MOV64mr <fi#5>, 1, %noreg, 0, %noreg, %vreg11; mem:ST8[%nbytes_out_lo32.addr] GR64:%vreg11
496B		MOV64mr <fi#6>, 1, %noreg, 0, %noreg, %vreg12; mem:ST8[%nbytes_out_hi32.addr] GR64:%vreg12
512B		%vreg16<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr] GR64:%vreg16
544B		MOV64mr <fi#10>, 1, %noreg, 0, %noreg, %vreg16; mem:ST8[%bzf] GR64:%vreg16
560B		CMP64mi8 <fi#10>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
576B		JNE_1 <BB#6>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#6 BB#1

592B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
608B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
624B		JE_1 <BB#3>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#3 BB#2

640B	BB#2: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#1
656B		%vreg198<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg198
672B		MOV32mi %vreg198, 1, %noreg, 0, %noreg, 0; mem:ST4[%4] GR64:%vreg198
	    Successors according to CFG: BB#3

688B	BB#3: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#1 BB#2
704B		CMP64mi8 <fi#10>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
720B		JE_1 <BB#5>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#5 BB#4

736B	BB#4: derived from LLVM BB %if.then.4
	    Predecessors according to CFG: BB#3
752B		%vreg201<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg201
768B		MOV32mi %vreg201, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr] GR64:%vreg201
	    Successors according to CFG: BB#5

784B	BB#5: derived from LLVM BB %if.end.5
	    Predecessors according to CFG: BB#3 BB#4
800B		JMP_1 <BB#71>
	    Successors according to CFG: BB#71

816B	BB#6: derived from LLVM BB %if.end.6
	    Predecessors according to CFG: BB#0
832B		%vreg23<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg23
848B		CMP8mi %vreg23, 1, %noreg, 5012, %noreg, 0, %EFLAGS<imp-def>; mem:LD1[%writing] GR64:%vreg23
864B		JNE_1 <BB#12>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#12 BB#7

880B	BB#7: derived from LLVM BB %if.then.7
	    Predecessors according to CFG: BB#6
896B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
912B		JE_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#8

928B	BB#8: derived from LLVM BB %if.then.9
	    Predecessors according to CFG: BB#7
944B		%vreg26<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg26
960B		MOV32mi %vreg26, 1, %noreg, 0, %noreg, -1; mem:ST4[%10] GR64:%vreg26
	    Successors according to CFG: BB#9

976B	BB#9: derived from LLVM BB %if.end.10
	    Predecessors according to CFG: BB#7 BB#8
992B		CMP64mi8 <fi#10>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
1008B		JE_1 <BB#11>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#11 BB#10

1024B	BB#10: derived from LLVM BB %if.then.12
	    Predecessors according to CFG: BB#9
1040B		%vreg29<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg29
1056B		MOV32mi %vreg29, 1, %noreg, 5096, %noreg, -1; mem:ST4[%lastErr13] GR64:%vreg29
	    Successors according to CFG: BB#11

1072B	BB#11: derived from LLVM BB %if.end.14
	    Predecessors according to CFG: BB#9 BB#10
1088B		JMP_1 <BB#71>
	    Successors according to CFG: BB#71

1104B	BB#12: derived from LLVM BB %if.end.15
	    Predecessors according to CFG: BB#6
1120B		%vreg35<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg35
1136B		%vreg34<def> = MOV64rm %vreg35, 1, %noreg, 0, %noreg; mem:LD8[%handle] GR64:%vreg34,%vreg35
1152B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1168B		%RDI<def> = COPY %vreg34; GR64:%vreg34
1184B		CALL64pcrel32 <ga:@ferror>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
1200B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1216B		%vreg32<def> = COPY %EAX<kill>; GR32:%vreg32
1232B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1248B		STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4)
1264B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1280B		CMP32ri8 %vreg32, 0, %EFLAGS<imp-def>; GR32:%vreg32
1296B		JE_1 <BB#18>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#18 BB#13

1312B	BB#13: derived from LLVM BB %if.then.17
	    Predecessors according to CFG: BB#12
1328B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
1344B		JE_1 <BB#15>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#15 BB#14

1360B	BB#14: derived from LLVM BB %if.then.19
	    Predecessors according to CFG: BB#13
1376B		%vreg192<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg192
1392B		MOV32mi %vreg192, 1, %noreg, 0, %noreg, -6; mem:ST4[%16] GR64:%vreg192
	    Successors according to CFG: BB#15

1408B	BB#15: derived from LLVM BB %if.end.20
	    Predecessors according to CFG: BB#13 BB#14
1424B		CMP64mi8 <fi#10>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
1440B		JE_1 <BB#17>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#17 BB#16

1456B	BB#16: derived from LLVM BB %if.then.22
	    Predecessors according to CFG: BB#15
1472B		%vreg195<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg195
1488B		MOV32mi %vreg195, 1, %noreg, 5096, %noreg, -6; mem:ST4[%lastErr23] GR64:%vreg195
	    Successors according to CFG: BB#17

1504B	BB#17: derived from LLVM BB %if.end.24
	    Predecessors according to CFG: BB#15 BB#16
1520B		JMP_1 <BB#71>
	    Successors according to CFG: BB#71

1536B	BB#18: derived from LLVM BB %if.end.25
	    Predecessors according to CFG: BB#12
1552B		CMP64mi8 <fi#3>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%nbytes_in_lo32.addr]
1568B		JE_1 <BB#20>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#20 BB#19

1584B	BB#19: derived from LLVM BB %if.then.27
	    Predecessors according to CFG: BB#18
1600B		%vreg38<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%nbytes_in_lo32.addr] GR64:%vreg38
1616B		MOV32mi %vreg38, 1, %noreg, 0, %noreg, 0; mem:ST4[%20] GR64:%vreg38
	    Successors according to CFG: BB#20

1632B	BB#20: derived from LLVM BB %if.end.28
	    Predecessors according to CFG: BB#18 BB#19
1648B		CMP64mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%nbytes_in_hi32.addr]
1664B		JE_1 <BB#22>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#22 BB#21

1680B	BB#21: derived from LLVM BB %if.then.30
	    Predecessors according to CFG: BB#20
1696B		%vreg41<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%nbytes_in_hi32.addr] GR64:%vreg41
1712B		MOV32mi %vreg41, 1, %noreg, 0, %noreg, 0; mem:ST4[%22] GR64:%vreg41
	    Successors according to CFG: BB#22

1728B	BB#22: derived from LLVM BB %if.end.31
	    Predecessors according to CFG: BB#20 BB#21
1744B		CMP64mi8 <fi#5>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%nbytes_out_lo32.addr]
1760B		JE_1 <BB#24>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#24 BB#23

1776B	BB#23: derived from LLVM BB %if.then.33
	    Predecessors according to CFG: BB#22
1792B		%vreg44<def> = MOV64rm <fi#5>, 1, %noreg, 0, %noreg; mem:LD8[%nbytes_out_lo32.addr] GR64:%vreg44
1808B		MOV32mi %vreg44, 1, %noreg, 0, %noreg, 0; mem:ST4[%24] GR64:%vreg44
	    Successors according to CFG: BB#24

1824B	BB#24: derived from LLVM BB %if.end.34
	    Predecessors according to CFG: BB#22 BB#23
1840B		CMP64mi8 <fi#6>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%nbytes_out_hi32.addr]
1856B		JE_1 <BB#26>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#26 BB#25

1872B	BB#25: derived from LLVM BB %if.then.36
	    Predecessors according to CFG: BB#24
1888B		%vreg47<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%nbytes_out_hi32.addr] GR64:%vreg47
1904B		MOV32mi %vreg47, 1, %noreg, 0, %noreg, 0; mem:ST4[%26] GR64:%vreg47
	    Successors according to CFG: BB#26

1920B	BB#26: derived from LLVM BB %if.end.37
	    Predecessors according to CFG: BB#24 BB#25
1936B		CMP32mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%abandon.addr]
1952B		JNE_1 <BB#49>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#49 BB#27

1968B	BB#27: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#26
1984B		%vreg51<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg51
2000B		CMP32mi8 %vreg51, 1, %noreg, 5096, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%lastErr39] GR64:%vreg51
2016B		JNE_1 <BB#49>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#49 BB#28

2032B	BB#28: derived from LLVM BB %if.then.41
	    Predecessors according to CFG: BB#27
2048B		JMP_1 <BB#29>
	    Successors according to CFG: BB#29

2064B	BB#29: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#28 BB#47
2096B		%vreg68<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg68
2112B		MOV32mi %vreg68, 1, %noreg, 5048, %noreg, 5000; mem:ST4[%avail_out] GR64:%vreg68
2128B		%vreg65<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg65
2160B		%vreg65<def,tied1> = ADD64ri8 %vreg65<tied0>, 8, %EFLAGS<imp-def,dead>; GR64:%vreg65
2176B		%vreg62<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg62
2192B		MOV64mr %vreg62, 1, %noreg, 5040, %noreg, %vreg65; mem:ST8[%next_out] GR64:%vreg62,%vreg65
2208B		%vreg58<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg58
2240B		%vreg58<def,tied1> = ADD64ri32 %vreg58<tied0>, 5016, %EFLAGS<imp-def,dead>; GR64:%vreg58
2256B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2288B		%ESI<def> = MOV32ri 2
2296B		%RDI<def> = COPY %vreg58; GR64:%vreg58
2304B		CALL64pcrel32 <ga:@BZ2_bzCompress>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %EAX<imp-def>
2320B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2336B		%vreg56<def> = COPY %EAX<kill>; GR32:%vreg56
2352B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2368B		STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4)
2384B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2400B		MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %vreg56; mem:ST4[%ret] GR32:%vreg56
2416B		CMP32mi8 <fi#9>, 1, %noreg, 0, %noreg, 3, %EFLAGS<imp-def>; mem:LD4[%ret]
2432B		JE_1 <BB#36>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#36 BB#30

2448B	BB#30: derived from LLVM BB %land.lhs.true.46
	    Predecessors according to CFG: BB#29
2464B		CMP32mi8 <fi#9>, 1, %noreg, 0, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%ret]
2480B		JE_1 <BB#36>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#36 BB#31

2496B	BB#31: derived from LLVM BB %if.then.48
	    Predecessors according to CFG: BB#30
2512B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
2528B		JE_1 <BB#33>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#33 BB#32

2544B	BB#32: derived from LLVM BB %if.then.50
	    Predecessors according to CFG: BB#31
2560B		%vreg117<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%ret] GR32:%vreg117
2576B		%vreg116<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg116
2592B		MOV32mr %vreg116, 1, %noreg, 0, %noreg, %vreg117; mem:ST4[%38] GR64:%vreg116 GR32:%vreg117
	    Successors according to CFG: BB#33

2608B	BB#33: derived from LLVM BB %if.end.51
	    Predecessors according to CFG: BB#31 BB#32
2624B		CMP64mi8 <fi#10>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
2640B		JE_1 <BB#35>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#35 BB#34

2656B	BB#34: derived from LLVM BB %if.then.53
	    Predecessors according to CFG: BB#33
2672B		%vreg122<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%ret] GR32:%vreg122
2688B		%vreg121<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg121
2704B		MOV32mr %vreg121, 1, %noreg, 5096, %noreg, %vreg122; mem:ST4[%lastErr54] GR64:%vreg121 GR32:%vreg122
	    Successors according to CFG: BB#35

2720B	BB#35: derived from LLVM BB %if.end.55
	    Predecessors according to CFG: BB#33 BB#34
2736B		JMP_1 <BB#71>
	    Successors according to CFG: BB#71

2752B	BB#36: derived from LLVM BB %if.end.56
	    Predecessors according to CFG: BB#29 BB#30
2768B		%vreg72<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg72
2784B		CMP32mi %vreg72, 1, %noreg, 5048, %noreg, 5000, %EFLAGS<imp-def>; mem:LD4[%avail_out58] GR64:%vreg72
2800B		JAE_1 <BB#45>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#45 BB#37

2816B	BB#37: derived from LLVM BB %if.then.60
	    Predecessors according to CFG: BB#36
2864B		%vreg97<def> = MOV32ri 5000; GR32:%vreg97
2880B		%vreg99<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg99
2912B		%vreg97<def,tied1> = SUB32rm %vreg97<tied0>, %vreg99, 1, %noreg, 5048, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%avail_out62] GR32:%vreg97 GR64:%vreg99
2928B		MOV32mr <fi#7>, 1, %noreg, 0, %noreg, %vreg97; mem:ST4[%n] GR32:%vreg97
2944B		%vreg92<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg92
2976B		%vreg92<def,tied1> = ADD64ri8 %vreg92<tied0>, 8, %EFLAGS<imp-def,dead>; GR64:%vreg92
2992B		%vreg89<def> = MOVSX64rm32 <fi#7>, 1, %noreg, 0, %noreg; mem:LD4[%n] GR64:%vreg89
3008B		%vreg87<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg87
3024B		%vreg86<def> = MOV64rm %vreg87, 1, %noreg, 0, %noreg; mem:LD8[%handle65] GR64:%vreg86,%vreg87
3040B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3072B		%ESI<def,dead> = MOV32ri 1, %RSI<imp-def>
3080B		%RDI<def> = COPY %vreg92; GR64:%vreg92
3088B		%RDX<def> = COPY %vreg89; GR64:%vreg89
3104B		%RCX<def> = COPY %vreg86; GR64:%vreg86
3120B		CALL64pcrel32 <ga:@fwrite>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %RDX<imp-use>, %RCX<imp-use>, %RAX<imp-def>
3136B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3152B		%vreg84<def> = COPY %RAX<kill>; GR64_with_sub_8bit:%vreg84
3168B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3184B		STACKMAP 3, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4)
3200B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3232B		MOV32mr <fi#8>, 1, %noreg, 0, %noreg, %vreg84:sub_32bit; mem:ST4[%n2] GR64_with_sub_8bit:%vreg84
3248B		%vreg75<def> = MOV32rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD4[%n] GR32:%vreg75
3264B		CMP32rm %vreg75, <fi#8>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD4[%n2] GR32:%vreg75
3280B		JNE_1 <BB#39>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#39 BB#38

3296B	BB#38: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#37
3312B		%vreg105<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg105
3328B		%vreg104<def> = MOV64rm %vreg105, 1, %noreg, 0, %noreg; mem:LD8[%handle70] GR64:%vreg104,%vreg105
3344B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3360B		%RDI<def> = COPY %vreg104; GR64:%vreg104
3376B		CALL64pcrel32 <ga:@ferror>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
3392B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3408B		%vreg102<def> = COPY %EAX<kill>; GR32:%vreg102
3424B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3440B		STACKMAP 4, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4)
3456B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3472B		CMP32ri8 %vreg102, 0, %EFLAGS<imp-def>; GR32:%vreg102
3488B		JE_1 <BB#44>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#44 BB#39

3504B	BB#39: derived from LLVM BB %if.then.73
	    Predecessors according to CFG: BB#37 BB#38
3520B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
3536B		JE_1 <BB#41>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#41 BB#40

3552B	BB#40: derived from LLVM BB %if.then.76
	    Predecessors according to CFG: BB#39
3568B		%vreg109<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg109
3584B		MOV32mi %vreg109, 1, %noreg, 0, %noreg, -6; mem:ST4[%55] GR64:%vreg109
	    Successors according to CFG: BB#41

3600B	BB#41: derived from LLVM BB %if.end.77
	    Predecessors according to CFG: BB#39 BB#40
3616B		CMP64mi8 <fi#10>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
3632B		JE_1 <BB#43>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#43 BB#42

3648B	BB#42: derived from LLVM BB %if.then.80
	    Predecessors according to CFG: BB#41
3664B		%vreg112<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg112
3680B		MOV32mi %vreg112, 1, %noreg, 5096, %noreg, -6; mem:ST4[%lastErr81] GR64:%vreg112
	    Successors according to CFG: BB#43

3696B	BB#43: derived from LLVM BB %if.end.82
	    Predecessors according to CFG: BB#41 BB#42
3712B		JMP_1 <BB#71>
	    Successors according to CFG: BB#71

3728B	BB#44: derived from LLVM BB %if.end.83
	    Predecessors according to CFG: BB#38
3744B		JMP_1 <BB#45>
	    Successors according to CFG: BB#45

3760B	BB#45: derived from LLVM BB %if.end.84
	    Predecessors according to CFG: BB#36 BB#44
3776B		CMP32mi8 <fi#9>, 1, %noreg, 0, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%ret]
3792B		JNE_1 <BB#47>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#47 BB#46

3808B	BB#46: derived from LLVM BB %if.then.87
	    Predecessors according to CFG: BB#45
3824B		JMP_1 <BB#48>
	    Successors according to CFG: BB#48

3840B	BB#47: derived from LLVM BB %if.end.88
	    Predecessors according to CFG: BB#45
3856B		JMP_1 <BB#29>
	    Successors according to CFG: BB#29

3872B	BB#48: derived from LLVM BB %while.end
	    Predecessors according to CFG: BB#46
3888B		JMP_1 <BB#49>
	    Successors according to CFG: BB#49

3904B	BB#49: derived from LLVM BB %if.end.89
	    Predecessors according to CFG: BB#26 BB#27 BB#48
3920B		CMP32mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%abandon.addr]
3936B		JNE_1 <BB#58>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#58 BB#50

3952B	BB#50: derived from LLVM BB %land.lhs.true.91
	    Predecessors according to CFG: BB#49
3968B		%vreg129<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg129
3984B		%vreg128<def> = MOV64rm %vreg129, 1, %noreg, 0, %noreg; mem:LD8[%handle92] GR64:%vreg128,%vreg129
4000B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4016B		%RDI<def> = COPY %vreg128; GR64:%vreg128
4032B		CALL64pcrel32 <ga:@ferror>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
4048B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4064B		%vreg126<def> = COPY %EAX<kill>; GR32:%vreg126
4080B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4096B		STACKMAP 5, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, ...; mem:LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5]
4112B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4128B		CMP32ri8 %vreg126, 0, %EFLAGS<imp-def>; GR32:%vreg126
4144B		JNE_1 <BB#58>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#58 BB#51

4160B	BB#51: derived from LLVM BB %if.then.95
	    Predecessors according to CFG: BB#50
4176B		%vreg140<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg140
4192B		%vreg139<def> = MOV64rm %vreg140, 1, %noreg, 0, %noreg; mem:LD8[%handle96] GR64:%vreg139,%vreg140
4208B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4224B		%RDI<def> = COPY %vreg139; GR64:%vreg139
4240B		CALL64pcrel32 <ga:@fflush>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
4256B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4272B		%vreg137<def,dead> = COPY %EAX<kill>; GR32:%vreg137
4288B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4304B		STACKMAP 6, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, ...; mem:LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5]
4320B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4336B		%vreg135<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg135
4352B		%vreg134<def> = MOV64rm %vreg135, 1, %noreg, 0, %noreg; mem:LD8[%handle98] GR64:%vreg134,%vreg135
4368B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4384B		%RDI<def> = COPY %vreg134; GR64:%vreg134
4400B		CALL64pcrel32 <ga:@ferror>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
4416B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4432B		%vreg132<def> = COPY %EAX<kill>; GR32:%vreg132
4448B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4464B		STACKMAP 7, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, ...; mem:LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5]
4480B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4496B		CMP32ri8 %vreg132, 0, %EFLAGS<imp-def>; GR32:%vreg132
4512B		JE_1 <BB#57>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#57 BB#52

4528B	BB#52: derived from LLVM BB %if.then.101
	    Predecessors according to CFG: BB#51
4544B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
4560B		JE_1 <BB#54>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#54 BB#53

4576B	BB#53: derived from LLVM BB %if.then.104
	    Predecessors according to CFG: BB#52
4592B		%vreg143<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg143
4608B		MOV32mi %vreg143, 1, %noreg, 0, %noreg, -6; mem:ST4[%67] GR64:%vreg143
	    Successors according to CFG: BB#54

4624B	BB#54: derived from LLVM BB %if.end.105
	    Predecessors according to CFG: BB#52 BB#53
4640B		CMP64mi8 <fi#10>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
4656B		JE_1 <BB#56>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#56 BB#55

4672B	BB#55: derived from LLVM BB %if.then.108
	    Predecessors according to CFG: BB#54
4688B		%vreg146<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg146
4704B		MOV32mi %vreg146, 1, %noreg, 5096, %noreg, -6; mem:ST4[%lastErr109] GR64:%vreg146
	    Successors according to CFG: BB#56

4720B	BB#56: derived from LLVM BB %if.end.110
	    Predecessors according to CFG: BB#54 BB#55
4736B		JMP_1 <BB#71>
	    Successors according to CFG: BB#71

4752B	BB#57: derived from LLVM BB %if.end.111
	    Predecessors according to CFG: BB#51
4768B		JMP_1 <BB#58>
	    Successors according to CFG: BB#58

4784B	BB#58: derived from LLVM BB %if.end.112
	    Predecessors according to CFG: BB#49 BB#50 BB#57
4800B		CMP64mi8 <fi#3>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%nbytes_in_lo32.addr]
4816B		JE_1 <BB#60>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#60 BB#59

4832B	BB#59: derived from LLVM BB %if.then.115
	    Predecessors according to CFG: BB#58
4848B		%vreg153<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg153
4864B		%vreg152<def> = MOV32rm %vreg153, 1, %noreg, 5028, %noreg; mem:LD4[%total_in_lo32] GR32:%vreg152 GR64:%vreg153
4880B		%vreg150<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%nbytes_in_lo32.addr] GR64:%vreg150
4896B		MOV32mr %vreg150, 1, %noreg, 0, %noreg, %vreg152; mem:ST4[%73] GR64:%vreg150 GR32:%vreg152
	    Successors according to CFG: BB#60

4912B	BB#60: derived from LLVM BB %if.end.117
	    Predecessors according to CFG: BB#58 BB#59
4928B		CMP64mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%nbytes_in_hi32.addr]
4944B		JE_1 <BB#62>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#62 BB#61

4960B	BB#61: derived from LLVM BB %if.then.120
	    Predecessors according to CFG: BB#60
4976B		%vreg160<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg160
4992B		%vreg159<def> = MOV32rm %vreg160, 1, %noreg, 5032, %noreg; mem:LD4[%total_in_hi32] GR32:%vreg159 GR64:%vreg160
5008B		%vreg157<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%nbytes_in_hi32.addr] GR64:%vreg157
5024B		MOV32mr %vreg157, 1, %noreg, 0, %noreg, %vreg159; mem:ST4[%77] GR64:%vreg157 GR32:%vreg159
	    Successors according to CFG: BB#62

5040B	BB#62: derived from LLVM BB %if.end.122
	    Predecessors according to CFG: BB#60 BB#61
5056B		CMP64mi8 <fi#5>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%nbytes_out_lo32.addr]
5072B		JE_1 <BB#64>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#64 BB#63

5088B	BB#63: derived from LLVM BB %if.then.125
	    Predecessors according to CFG: BB#62
5104B		%vreg167<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg167
5120B		%vreg166<def> = MOV32rm %vreg167, 1, %noreg, 5052, %noreg; mem:LD4[%total_out_lo32] GR32:%vreg166 GR64:%vreg167
5136B		%vreg164<def> = MOV64rm <fi#5>, 1, %noreg, 0, %noreg; mem:LD8[%nbytes_out_lo32.addr] GR64:%vreg164
5152B		MOV32mr %vreg164, 1, %noreg, 0, %noreg, %vreg166; mem:ST4[%81] GR64:%vreg164 GR32:%vreg166
	    Successors according to CFG: BB#64

5168B	BB#64: derived from LLVM BB %if.end.127
	    Predecessors according to CFG: BB#62 BB#63
5184B		CMP64mi8 <fi#6>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%nbytes_out_hi32.addr]
5200B		JE_1 <BB#66>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#66 BB#65

5216B	BB#65: derived from LLVM BB %if.then.130
	    Predecessors according to CFG: BB#64
5232B		%vreg174<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg174
5248B		%vreg173<def> = MOV32rm %vreg174, 1, %noreg, 5056, %noreg; mem:LD4[%total_out_hi32] GR32:%vreg173 GR64:%vreg174
5264B		%vreg171<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%nbytes_out_hi32.addr] GR64:%vreg171
5280B		MOV32mr %vreg171, 1, %noreg, 0, %noreg, %vreg173; mem:ST4[%85] GR64:%vreg171 GR32:%vreg173
	    Successors according to CFG: BB#66

5296B	BB#66: derived from LLVM BB %if.end.132
	    Predecessors according to CFG: BB#64 BB#65
5312B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
5328B		JE_1 <BB#68>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#68 BB#67

5344B	BB#67: derived from LLVM BB %if.then.135
	    Predecessors according to CFG: BB#66
5360B		%vreg177<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg177
5376B		MOV32mi %vreg177, 1, %noreg, 0, %noreg, 0; mem:ST4[%87] GR64:%vreg177
	    Successors according to CFG: BB#68

5392B	BB#68: derived from LLVM BB %if.end.136
	    Predecessors according to CFG: BB#66 BB#67
5408B		CMP64mi8 <fi#10>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
5424B		JE_1 <BB#70>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#70 BB#69

5440B	BB#69: derived from LLVM BB %if.then.139
	    Predecessors according to CFG: BB#68
5456B		%vreg180<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg180
5472B		MOV32mi %vreg180, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr140] GR64:%vreg180
	    Successors according to CFG: BB#70

5488B	BB#70: derived from LLVM BB %if.end.141
	    Predecessors according to CFG: BB#68 BB#69
5504B		%vreg188<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg188
5536B		%vreg188<def,tied1> = ADD64ri32 %vreg188<tied0>, 5016, %EFLAGS<imp-def,dead>; GR64:%vreg188
5552B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5568B		%RDI<def> = COPY %vreg188; GR64:%vreg188
5584B		CALL64pcrel32 <ga:@BZ2_bzCompressEnd>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
5600B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5616B		%vreg186<def,dead> = COPY %EAX<kill>; GR32:%vreg186
5632B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5648B		STACKMAP 8, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack10]
5664B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5680B		%vreg183<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg183
5712B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5728B		%RDI<def> = COPY %vreg183; GR64:%vreg183
5744B		CALL64pcrel32 <ga:@free>, <regmask>, %RSP<imp-use>, %RDI<imp-use>
5760B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5776B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5792B		STACKMAP 9, 0, ...
5808B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#71

5824B	BB#71: derived from LLVM BB %return
	    Predecessors according to CFG: BB#11 BB#43 BB#35 BB#56 BB#70 BB#17 BB#5
5840B		%vreg203<def> = MOV64ri <ga:@BZ2_bzWriteClose64>; GR64:%vreg203
5872B		%vreg204<def> = MOV64rm <fi#-2>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-2] GR64:%vreg204
5888B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5904B		%RDI<def> = COPY %vreg203; GR64:%vreg203
5920B		%RSI<def> = COPY %vreg204; GR64:%vreg204
5936B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
5952B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5968B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5984B		STACKMAP 10, 0, ...
6000B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
6016B		RETQ

# End machine code for function BZ2_bzWriteClose64.


selectOrSplit GR64:%vreg11 [16r,480r:0)  0@16r w=3.506945e-03
hints: %R9
missed hint %R9
assigning %vreg11 to %RBX: BH [16r,480r:0)  0@16r BL [16r,480r:0)  0@16r

selectOrSplit GR64:%vreg10 [32r,464r:0)  0@32r w=3.641827e-03
hints: %R8
missed hint %R8
%R14 is available at cost 1
Only trying the first 10 regs.
should evict: %vreg11 [16r,480r:0)  0@16r w= 3.506945e-03
hints: %R9
can reassign: %vreg11 [16r,480r:0)  0@16r from %RBX to %R9
should evict: %vreg11 [16r,480r:0)  0@16r w= 3.506945e-03
hints: %R9
can reassign: %vreg11 [16r,480r:0)  0@16r from %RBX to %R9
evicting %RBX interference: Cascade 1
unassigning %vreg11 from %RBX: BH BL
assigning %vreg10 to %RBX: BH [32r,464r:0)  0@32r BL [32r,464r:0)  0@32r
queuing new interval: %vreg11 [16r,480r:0)  0@16r

selectOrSplit GR64:%vreg11 [16r,480r:0)  0@16r w=3.506945e-03
hints: %R9
missed hint %R9
%R14 is available at cost 1
Only trying the first 10 regs.
assigning %vreg11 to %R14: R14B [16r,480r:0)  0@16r

selectOrSplit GR64:%vreg9 [48r,448r:0)  0@48r w=3.787500e-03
hints: %RCX
missed hint %RCX
%R15 is available at cost 1
Only trying the first 10 regs.
should evict: %vreg10 [32r,464r:0)  0@32r w= 3.641827e-03
hints: %R8
can reassign: %vreg10 [32r,464r:0)  0@32r from %RBX to %R8
should evict: %vreg10 [32r,464r:0)  0@32r w= 3.641827e-03
hints: %R8
can reassign: %vreg10 [32r,464r:0)  0@32r from %RBX to %R8
evicting %RBX interference: Cascade 2
unassigning %vreg10 from %RBX: BH BL
assigning %vreg9 to %RBX: BH [48r,448r:0)  0@48r BL [48r,448r:0)  0@48r
queuing new interval: %vreg10 [32r,464r:0)  0@32r

selectOrSplit GR64:%vreg10 [32r,464r:0)  0@32r w=3.641827e-03
hints: %R8
missed hint %R8
%R15 is available at cost 1
Only trying the first 10 regs.
assigning %vreg10 to %R15: R15B [32r,464r:0)  0@32r

selectOrSplit GR32:%vreg8 [64r,432r:0)  0@64r w=3.945312e-03
hints: %EDX
missed hint %EDX
%R12D is available at cost 1
Only trying the first 10 regs.
should evict: %vreg9 [48r,448r:0)  0@48r w= 3.787500e-03
hints: %RCX
can reassign: %vreg9 [48r,448r:0)  0@48r from %EBX to %RCX
should evict: %vreg9 [48r,448r:0)  0@48r w= 3.787500e-03
hints: %RCX
can reassign: %vreg9 [48r,448r:0)  0@48r from %EBX to %RCX
evicting %EBX interference: Cascade 3
unassigning %vreg9 from %RBX: BH BL
assigning %vreg8 to %EBX: BH [64r,432r:0)  0@64r BL [64r,432r:0)  0@64r
queuing new interval: %vreg9 [48r,448r:0)  0@48r

selectOrSplit GR64:%vreg9 [48r,448r:0)  0@48r w=3.787500e-03
hints: %RCX
missed hint %RCX
%R12 is available at cost 1
Only trying the first 10 regs.
assigning %vreg9 to %R12: R12B [48r,448r:0)  0@48r

selectOrSplit GR64:%vreg7 [80r,416r:0)  0@80r w=4.116848e-03
hints: %RSI
missed hint %RSI
%R13 is available at cost 1
Only trying the first 10 regs.
should evict: %vreg8 [64r,432r:0)  0@64r w= 3.945312e-03
hints: %EDX
can reassign: %vreg8 [64r,432r:0)  0@64r from %RBX to %EDX
should evict: %vreg8 [64r,432r:0)  0@64r w= 3.945312e-03
hints: %EDX
can reassign: %vreg8 [64r,432r:0)  0@64r from %RBX to %EDX
evicting %RBX interference: Cascade 4
unassigning %vreg8 from %EBX: BH BL
assigning %vreg7 to %RBX: BH [80r,416r:0)  0@80r BL [80r,416r:0)  0@80r
queuing new interval: %vreg8 [64r,432r:0)  0@64r

selectOrSplit GR32:%vreg8 [64r,432r:0)  0@64r w=3.945312e-03
hints: %EDX
missed hint %EDX
%R13D is available at cost 1
Only trying the first 10 regs.
assigning %vreg8 to %R13D: R13B [64r,432r:0)  0@64r

selectOrSplit GR64:%vreg6 [96r,400r:0)  0@96r w=4.303977e-03
hints: %RDI
RS_Assign Cascade 0
should evict: %vreg7 [80r,416r:0)  0@80r w= 4.116848e-03
should evict: %vreg7 [80r,416r:0)  0@80r w= 4.116848e-03
should evict: %vreg11 [16r,480r:0)  0@16r w= 3.506945e-03
hints: %R9
can reassign: %vreg11 [16r,480r:0)  0@16r from %R14 to %R9
evicting %R14 interference: Cascade 5
unassigning %vreg11 from %R14: R14B
assigning %vreg6 to %R14: R14B [96r,400r:0)  0@96r
queuing new interval: %vreg11 [16r,480r:0)  0@16r

selectOrSplit GR64:%vreg11 [16r,480r:0)  0@16r w=3.506945e-03
hints: %R9
RS_Assign Cascade 5
wait for second round
queuing new interval: %vreg11 [16r,480r:0)  0@16r

selectOrSplit GR64:%vreg19 [224r,288r:0)  0@224r w=2.176724e-03
hints: %RDI
assigning %vreg19 to %RDI: DIL [224r,288r:0)  0@224r

selectOrSplit GR64:%vreg20 [256r,304r:0)  0@256r w=4.508928e-03
hints: %RSI
assigning %vreg20 to %RSI: SIL [256r,304r:0)  0@256r

selectOrSplit GR64:%vreg34 [1136r,1168r:0)  0@1136r w=1.167863e-03
hints: %RDI
assigning %vreg34 to %RDI: DIL [1136r,1168r:0)  0@1136r

selectOrSplit GR32:%vreg32 [1216r,1280r:0)  0@1216r w=1.087321e-03
hints: %EAX
assigning %vreg32 to %EAX: AH [1216r,1280r:0)  0@1216r AL [1216r,1280r:0)  0@1216r

selectOrSplit GR64:%vreg58 [2208r,2240r:0)[2240r,2296r:1)  0@2208r 1@2240r w=3.366930e-04
hints: %RDI
assigning %vreg58 to %RDI: DIL [2208r,2240r:0)[2240r,2296r:1)  0@2208r 1@2240r

selectOrSplit GR32:%vreg56 [2336r,2400r:0)  0@2336r w=1.770541e-04
hints: %EAX
assigning %vreg56 to %EAX: AH [2336r,2400r:0)  0@2336r AL [2336r,2400r:0)  0@2336r

selectOrSplit GR64:%vreg92 [2944r,2976r:0)[2976r,3080r:1)  0@2944r 1@2976r w=1.117975e-04
hints: %RDI
assigning %vreg92 to %RDI: DIL [2944r,2976r:0)[2976r,3080r:1)  0@2944r 1@2976r

selectOrSplit GR64:%vreg89 [2992r,3088r:0)  0@2992r w=6.040670e-05
hints: %RDX
assigning %vreg89 to %RDX: DH [2992r,3088r:0)  0@2992r DL [2992r,3088r:0)  0@2992r

selectOrSplit GR64:%vreg86 [3024r,3104r:0)  0@3024r w=6.242025e-05
hints: %RCX
assigning %vreg86 to %RCX: CH [3024r,3104r:0)  0@3024r CL [3024r,3104r:0)  0@3024r

selectOrSplit GR64_with_sub_8bit:%vreg84 [3152r,3232r:0)  0@3152r w=6.242025e-05
hints: %RAX
assigning %vreg84 to %RAX: AH [3152r,3232r:0)  0@3152r AL [3152r,3232r:0)  0@3152r

selectOrSplit GR64:%vreg104 [3328r,3360r:0)  0@3328r w=3.355927e-05
hints: %RDI
assigning %vreg104 to %RDI: DIL [3328r,3360r:0)  0@3328r

selectOrSplit GR32:%vreg102 [3408r,3472r:0)  0@3408r w=3.124484e-05
hints: %EAX
assigning %vreg102 to %EAX: AH [3408r,3472r:0)  0@3408r AL [3408r,3472r:0)  0@3408r

selectOrSplit GR64:%vreg128 [3984r,4016r:0)  0@3984r w=2.393895e-04
hints: %RDI
assigning %vreg128 to %RDI: DIL [3984r,4016r:0)  0@3984r

selectOrSplit GR32:%vreg126 [4064r,4128r:0)  0@4064r w=2.228799e-04
hints: %EAX
assigning %vreg126 to %EAX: AH [4064r,4128r:0)  0@4064r AL [4064r,4128r:0)  0@4064r

selectOrSplit GR64:%vreg139 [4192r,4224r:0)  0@4192r w=1.185761e-04
hints: %RDI
assigning %vreg139 to %RDI: DIL [4192r,4224r:0)  0@4192r

selectOrSplit GR32:%vreg137 [4272r,4272d:0)  0@4272r w=inf
hints: %EAX
assigning %vreg137 to %EAX: AH [4272r,4272d:0)  0@4272r AL [4272r,4272d:0)  0@4272r

selectOrSplit GR64:%vreg134 [4352r,4384r:0)  0@4352r w=1.185761e-04
hints: %RDI
assigning %vreg134 to %RDI: DIL [4352r,4384r:0)  0@4352r

selectOrSplit GR32:%vreg132 [4432r,4496r:0)  0@4432r w=1.103984e-04
hints: %EAX
assigning %vreg132 to %EAX: AH [4432r,4496r:0)  0@4432r AL [4432r,4496r:0)  0@4432r

selectOrSplit GR64:%vreg188 [5504r,5536r:0)[5536r,5568r:1)  0@5504r 1@5536r w=7.832040e-04
hints: %RDI
assigning %vreg188 to %RDI: DIL [5504r,5536r:0)[5536r,5568r:1)  0@5504r 1@5536r

selectOrSplit GR32:%vreg186 [5616r,5616d:0)  0@5616r w=inf
hints: %EAX
assigning %vreg186 to %EAX: AH [5616r,5616d:0)  0@5616r AL [5616r,5616d:0)  0@5616r

selectOrSplit GR64:%vreg183 [5680r,5728r:0)  0@5680r w=4.055878e-04
hints: %RDI
assigning %vreg183 to %RDI: DIL [5680r,5728r:0)  0@5680r

selectOrSplit GR64:%vreg203 [5840r,5904r:0)  0@5840r w=2.176724e-03
hints: %RDI
assigning %vreg203 to %RDI: DIL [5840r,5904r:0)  0@5840r

selectOrSplit GR64:%vreg204 [5872r,5920r:0)  0@5872r w=4.508928e-03
hints: %RSI
assigning %vreg204 to %RSI: SIL [5872r,5920r:0)  0@5872r

selectOrSplit GR64:%vreg12 [112r,496r:0)  0@112r w=1.913265e-03
RS_Assign Cascade 0
wait for second round
queuing new interval: %vreg12 [112r,496r:0)  0@112r

selectOrSplit GR64:%vreg16 [512r,544r:0)  0@512r w=inf
assigning %vreg16 to %RAX: AH [512r,544r:0)  0@512r AL [512r,544r:0)  0@512r

selectOrSplit GR64:%vreg198 [656r,672r:0)  0@656r w=inf
assigning %vreg198 to %RAX: AH [656r,672r:0)  0@656r AL [656r,672r:0)  0@656r

selectOrSplit GR64:%vreg201 [752r,768r:0)  0@752r w=inf
assigning %vreg201 to %RAX: AH [752r,768r:0)  0@752r AL [752r,768r:0)  0@752r

selectOrSplit GR64:%vreg23 [832r,848r:0)  0@832r w=inf
assigning %vreg23 to %RAX: AH [832r,848r:0)  0@832r AL [832r,848r:0)  0@832r

selectOrSplit GR64:%vreg26 [944r,960r:0)  0@944r w=inf
assigning %vreg26 to %RAX: AH [944r,960r:0)  0@944r AL [944r,960r:0)  0@944r

selectOrSplit GR64:%vreg29 [1040r,1056r:0)  0@1040r w=inf
assigning %vreg29 to %RAX: AH [1040r,1056r:0)  0@1040r AL [1040r,1056r:0)  0@1040r

selectOrSplit GR64:%vreg35 [1120r,1136r:0)  0@1120r w=inf
assigning %vreg35 to %RAX: AH [1120r,1136r:0)  0@1120r AL [1120r,1136r:0)  0@1120r

selectOrSplit GR64:%vreg192 [1376r,1392r:0)  0@1376r w=inf
assigning %vreg192 to %RAX: AH [1376r,1392r:0)  0@1376r AL [1376r,1392r:0)  0@1376r

selectOrSplit GR64:%vreg195 [1472r,1488r:0)  0@1472r w=inf
assigning %vreg195 to %RAX: AH [1472r,1488r:0)  0@1472r AL [1472r,1488r:0)  0@1472r

selectOrSplit GR64:%vreg38 [1600r,1616r:0)  0@1600r w=inf
assigning %vreg38 to %RAX: AH [1600r,1616r:0)  0@1600r AL [1600r,1616r:0)  0@1600r

selectOrSplit GR64:%vreg41 [1696r,1712r:0)  0@1696r w=inf
assigning %vreg41 to %RAX: AH [1696r,1712r:0)  0@1696r AL [1696r,1712r:0)  0@1696r

selectOrSplit GR64:%vreg44 [1792r,1808r:0)  0@1792r w=inf
assigning %vreg44 to %RAX: AH [1792r,1808r:0)  0@1792r AL [1792r,1808r:0)  0@1792r

selectOrSplit GR64:%vreg47 [1888r,1904r:0)  0@1888r w=inf
assigning %vreg47 to %RAX: AH [1888r,1904r:0)  0@1888r AL [1888r,1904r:0)  0@1888r

selectOrSplit GR64:%vreg51 [1984r,2000r:0)  0@1984r w=inf
assigning %vreg51 to %RAX: AH [1984r,2000r:0)  0@1984r AL [1984r,2000r:0)  0@1984r

selectOrSplit GR64:%vreg68 [2096r,2112r:0)  0@2096r w=inf
assigning %vreg68 to %RAX: AH [2096r,2112r:0)  0@2096r AL [2096r,2112r:0)  0@2096r

selectOrSplit GR64:%vreg65 [2128r,2160r:0)[2160r,2192r:1)  0@2128r 1@2160r w=3.506022e-04
assigning %vreg65 to %RAX: AH [2128r,2160r:0)[2160r,2192r:1)  0@2128r 1@2160r AL [2128r,2160r:0)[2160r,2192r:1)  0@2128r 1@2160r

selectOrSplit GR64:%vreg62 [2176r,2192r:0)  0@2176r w=inf
assigning %vreg62 to %RCX: CH [2176r,2192r:0)  0@2176r CL [2176r,2192r:0)  0@2176r

selectOrSplit GR32:%vreg117 [2560r,2592r:0)  0@2560r w=2.215134e-05
assigning %vreg117 to %EAX: AH [2560r,2592r:0)  0@2560r AL [2560r,2592r:0)  0@2560r

selectOrSplit GR64:%vreg116 [2576r,2592r:0)  0@2576r w=inf
assigning %vreg116 to %RCX: CH [2576r,2592r:0)  0@2576r CL [2576r,2592r:0)  0@2576r

selectOrSplit GR32:%vreg122 [2672r,2704r:0)  0@2672r w=2.215134e-05
assigning %vreg122 to %EAX: AH [2672r,2704r:0)  0@2672r AL [2672r,2704r:0)  0@2672r

selectOrSplit GR64:%vreg121 [2688r,2704r:0)  0@2688r w=inf
assigning %vreg121 to %RCX: CH [2688r,2704r:0)  0@2688r CL [2688r,2704r:0)  0@2688r

selectOrSplit GR64:%vreg72 [2768r,2784r:0)  0@2768r w=inf
assigning %vreg72 to %RAX: AH [2768r,2784r:0)  0@2768r AL [2768r,2784r:0)  0@2768r

selectOrSplit GR32:%vreg97 [2864r,2912r:0)[2912r,2928r:1)  0@2864r 1@2912r w=1.278667e-04
assigning %vreg97 to %EAX: AH [2864r,2912r:0)[2912r,2928r:1)  0@2864r 1@2912r AL [2864r,2912r:0)[2912r,2928r:1)  0@2864r 1@2912r

selectOrSplit GR64:%vreg99 [2880r,2912r:0)  0@2880r w=inf
assigning %vreg99 to %RCX: CH [2880r,2912r:0)  0@2880r CL [2880r,2912r:0)  0@2880r

selectOrSplit GR64:%vreg87 [3008r,3024r:0)  0@3008r w=inf
assigning %vreg87 to %RAX: AH [3008r,3024r:0)  0@3008r AL [3008r,3024r:0)  0@3008r

selectOrSplit GR32:%vreg75 [3248r,3264r:0)  0@3248r w=inf
assigning %vreg75 to %EAX: AH [3248r,3264r:0)  0@3248r AL [3248r,3264r:0)  0@3248r

selectOrSplit GR64:%vreg105 [3312r,3328r:0)  0@3312r w=inf
assigning %vreg105 to %RAX: AH [3312r,3328r:0)  0@3312r AL [3312r,3328r:0)  0@3312r

selectOrSplit GR64:%vreg109 [3568r,3584r:0)  0@3568r w=inf
assigning %vreg109 to %RAX: AH [3568r,3584r:0)  0@3568r AL [3568r,3584r:0)  0@3568r

selectOrSplit GR64:%vreg112 [3664r,3680r:0)  0@3664r w=inf
assigning %vreg112 to %RAX: AH [3664r,3680r:0)  0@3664r AL [3664r,3680r:0)  0@3664r

selectOrSplit GR64:%vreg129 [3968r,3984r:0)  0@3968r w=inf
assigning %vreg129 to %RAX: AH [3968r,3984r:0)  0@3968r AL [3968r,3984r:0)  0@3968r

selectOrSplit GR64:%vreg140 [4176r,4192r:0)  0@4176r w=inf
assigning %vreg140 to %RAX: AH [4176r,4192r:0)  0@4176r AL [4176r,4192r:0)  0@4176r

selectOrSplit GR64:%vreg135 [4336r,4352r:0)  0@4336r w=inf
assigning %vreg135 to %RAX: AH [4336r,4352r:0)  0@4336r AL [4336r,4352r:0)  0@4336r

selectOrSplit GR64:%vreg143 [4592r,4608r:0)  0@4592r w=inf
assigning %vreg143 to %RAX: AH [4592r,4608r:0)  0@4592r AL [4592r,4608r:0)  0@4592r

selectOrSplit GR64:%vreg146 [4688r,4704r:0)  0@4688r w=inf
assigning %vreg146 to %RAX: AH [4688r,4704r:0)  0@4688r AL [4688r,4704r:0)  0@4688r

selectOrSplit GR64:%vreg153 [4848r,4864r:0)  0@4848r w=inf
assigning %vreg153 to %RAX: AH [4848r,4864r:0)  0@4848r AL [4848r,4864r:0)  0@4848r

selectOrSplit GR32:%vreg152 [4864r,4896r:0)  0@4864r w=2.082226e-04
assigning %vreg152 to %EAX: AH [4864r,4896r:0)  0@4864r AL [4864r,4896r:0)  0@4864r

selectOrSplit GR64:%vreg150 [4880r,4896r:0)  0@4880r w=inf
assigning %vreg150 to %RCX: CH [4880r,4896r:0)  0@4880r CL [4880r,4896r:0)  0@4880r

selectOrSplit GR64:%vreg160 [4976r,4992r:0)  0@4976r w=inf
assigning %vreg160 to %RAX: AH [4976r,4992r:0)  0@4976r AL [4976r,4992r:0)  0@4976r

selectOrSplit GR32:%vreg159 [4992r,5024r:0)  0@4992r w=2.082226e-04
assigning %vreg159 to %EAX: AH [4992r,5024r:0)  0@4992r AL [4992r,5024r:0)  0@4992r

selectOrSplit GR64:%vreg157 [5008r,5024r:0)  0@5008r w=inf
assigning %vreg157 to %RCX: CH [5008r,5024r:0)  0@5008r CL [5008r,5024r:0)  0@5008r

selectOrSplit GR64:%vreg167 [5104r,5120r:0)  0@5104r w=inf
assigning %vreg167 to %RAX: AH [5104r,5120r:0)  0@5104r AL [5104r,5120r:0)  0@5104r

selectOrSplit GR32:%vreg166 [5120r,5152r:0)  0@5120r w=2.082226e-04
assigning %vreg166 to %EAX: AH [5120r,5152r:0)  0@5120r AL [5120r,5152r:0)  0@5120r

selectOrSplit GR64:%vreg164 [5136r,5152r:0)  0@5136r w=inf
assigning %vreg164 to %RCX: CH [5136r,5152r:0)  0@5136r CL [5136r,5152r:0)  0@5136r

selectOrSplit GR64:%vreg174 [5232r,5248r:0)  0@5232r w=inf
assigning %vreg174 to %RAX: AH [5232r,5248r:0)  0@5232r AL [5232r,5248r:0)  0@5232r

selectOrSplit GR32:%vreg173 [5248r,5280r:0)  0@5248r w=2.082226e-04
assigning %vreg173 to %EAX: AH [5248r,5280r:0)  0@5248r AL [5248r,5280r:0)  0@5248r

selectOrSplit GR64:%vreg171 [5264r,5280r:0)  0@5264r w=inf
assigning %vreg171 to %RCX: CH [5264r,5280r:0)  0@5264r CL [5264r,5280r:0)  0@5264r

selectOrSplit GR64:%vreg177 [5360r,5376r:0)  0@5360r w=inf
assigning %vreg177 to %RAX: AH [5360r,5376r:0)  0@5360r AL [5360r,5376r:0)  0@5360r

selectOrSplit GR64:%vreg180 [5456r,5472r:0)  0@5456r w=inf
assigning %vreg180 to %RAX: AH [5456r,5472r:0)  0@5456r AL [5456r,5472r:0)  0@5456r

selectOrSplit GR64:%vreg11 [16r,480r:0)  0@16r w=3.506945e-03
hints: %R9
RS_Split Cascade 5
Analyze counted 3 instrs in 1 blocks, through 0 blocks.
tryLocalSplit:  16r 368r 480r
1 regmasks in block: 320r:16r-368r
%R9 16r-368r i=inf extend
%R9 368r-480r i=0.000000e+00 w=5.681818e-03 (best) end
%RAX 16r-368r i=inf extend
%RAX 368r-480r i=0.000000e+00 w=5.681818e-03 (best) end
%RCX 16r-368r i=inf extend
%RCX 368r-480r i=0.000000e+00 w=5.681818e-03 (best) end
%RDX 16r-368r i=inf extend
%RDX 368r-480r i=0.000000e+00 w=5.681818e-03 (best) end
%RSI 16r-368r i=inf extend
%RSI 368r-480r i=0.000000e+00 w=5.681818e-03 (best) end
%RDI 16r-368r i=inf extend
%RDI 368r-480r i=0.000000e+00 w=5.681818e-03 (best) end
%R8 16r-368r i=inf extend
%R8 368r-480r i=0.000000e+00 w=5.681818e-03 (best) end
%R10 16r-368r i=inf extend
%R10 368r-480r i=0.000000e+00 w=5.681818e-03 (best) end
%R11 16r-368r i=inf extend
%R11 368r-480r i=inf end
%RBX 16r-368r i=4.116848e-03 w=3.906250e-03 extend
%RBX 368r-480r i=4.116848e-03 w=5.681818e-03 end
%R14 16r-368r i=4.303977e-03 w=3.906250e-03 extend
%R14 368r-480r i=4.303977e-03 w=5.681818e-03 end
%R15 16r-368r i=3.641827e-03 w=3.906250e-03 extend
%R15 16r-480r i=3.641827e-03 all
%R12 16r-368r i=3.787500e-03 w=3.906250e-03 extend
%R12 16r-480r i=3.787500e-03 all
%R13 16r-368r i=3.945312e-03 w=3.906250e-03 extend
%R13 368r-480r i=3.945312e-03 w=5.681818e-03 end
Best local split range: 368r-480r, 5.568071e-03, 2 instrs
    enterIntvBefore 368r: valno 0
    leaveIntvAfter 480r: not live
    useIntv [360r;496B): [360r;496B):1
  blit [16r,480r:0): [16r;360r)=0:0 [360r;480r)=1:0
  rewr BB#0	16r:0	%vreg205<def> = COPY %R9; GR64:%vreg205
  rewr BB#0	480B:1	MOV64mr <fi#5>, 1, %noreg, 0, %noreg, %vreg206; mem:ST8[%nbytes_out_lo32.addr] GR64:%vreg206
  rewr BB#0	368B:1	STACKMAP 0, 0, %vreg8, 0, <fi#2>, 0, %vreg7, 0, <fi#1>, 0, %vreg6, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, %vreg10, 0, <fi#4>, 0, %vreg9, 0, <fi#3>, 0, %vreg12, 0, <fi#6>, 0, %vreg206, 0, <fi#5>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4) GR32:%vreg8 GR64:%vreg7,%vreg6,%vreg10,%vreg9,%vreg12,%vreg206
  rewr BB#0	360B:0	%vreg206<def> = COPY %vreg205; GR64:%vreg206,%vreg205
Tagging non-progress ranges: %vreg206
queuing new interval: %vreg205 [16r,360r:0)  0@16r
queuing new interval: %vreg206 [360r,480r:0)  0@360r

selectOrSplit GR64:%vreg205 [16r,360r:0)  0@16r w=2.715054e-03
hints: %R9
RS_Assign Cascade 0
wait for second round
queuing new interval: %vreg205 [16r,360r:0)  0@16r

selectOrSplit GR64:%vreg206 [360r,480r:0)  0@360r w=5.826923e-03
assigning %vreg206 to %RAX: AH [360r,480r:0)  0@360r AL [360r,480r:0)  0@360r

selectOrSplit GR64:%vreg12 [112r,496r:0)  0@112r w=1.913265e-03
RS_Split Cascade 0
Analyze counted 3 instrs in 1 blocks, through 0 blocks.
tryLocalSplit:  112r 368r 496r
1 regmasks in block: 320r:112r-368r
%RAX 112r-368r i=inf extend
%RAX 368r-496r i=5.826923e-03 w=5.514706e-03 end
%RCX 112r-368r i=inf extend
%RCX 368r-496r i=0.000000e+00 w=5.514706e-03 (best) end
%RDX 112r-368r i=inf extend
%RDX 368r-496r i=0.000000e+00 w=5.514706e-03 (best) end
%RSI 112r-368r i=inf extend
%RSI 368r-496r i=0.000000e+00 w=5.514706e-03 (best) end
%RDI 112r-368r i=inf extend
%RDI 368r-496r i=0.000000e+00 w=5.514706e-03 (best) end
%R8 112r-368r i=inf extend
%R8 368r-496r i=0.000000e+00 w=5.514706e-03 (best) end
%R9 112r-368r i=inf extend
%R9 368r-496r i=0.000000e+00 w=5.514706e-03 (best) end
%R10 112r-368r i=inf extend
%R10 368r-496r i=0.000000e+00 w=5.514706e-03 (best) end
%R11 112r-368r i=inf extend
%R11 368r-496r i=inf end
%RBX 112r-368r i=4.116848e-03 w=4.464286e-03 extend
%RBX 112r-496r i=4.116848e-03 all
%R14 112r-368r i=4.303977e-03 w=4.464286e-03 extend
%R14 112r-496r i=4.303977e-03 all
%R15 112r-368r i=3.641827e-03 w=4.464286e-03 extend
%R15 112r-496r i=3.641827e-03 all
%R12 112r-368r i=3.787500e-03 w=4.464286e-03 extend
%R12 112r-496r i=3.787500e-03 all
%R13 112r-368r i=3.945312e-03 w=4.464286e-03 extend
%R13 112r-496r i=3.945312e-03 all
Best local split range: 368r-496r, 5.404304e-03, 2 instrs
    enterIntvBefore 368r: valno 0
    leaveIntvAfter 496r: not live
    useIntv [364r;512B): [364r;512B):1
  blit [112r,496r:0): [112r;364r)=0:0 [364r;496r)=1:0
  rewr BB#0	112r:0	%vreg207<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg207
  rewr BB#0	496B:1	MOV64mr <fi#6>, 1, %noreg, 0, %noreg, %vreg208; mem:ST8[%nbytes_out_hi32.addr] GR64:%vreg208
  rewr BB#0	368B:1	STACKMAP 0, 0, %vreg8, 0, <fi#2>, 0, %vreg7, 0, <fi#1>, 0, %vreg6, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, %vreg10, 0, <fi#4>, 0, %vreg9, 0, <fi#3>, 0, %vreg208, 0, <fi#6>, 0, %vreg206, 0, <fi#5>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4) GR32:%vreg8 GR64:%vreg7,%vreg6,%vreg10,%vreg9,%vreg208,%vreg206
  rewr BB#0	364B:0	%vreg208<def> = COPY %vreg207; GR64:%vreg208,%vreg207
Tagging non-progress ranges: %vreg208
queuing new interval: %vreg207 [112r,364r:0)  0@112r
queuing new interval: %vreg208 [364r,496r:0)  0@364r

selectOrSplit GR64:%vreg208 [364r,496r:0)  0@364r w=5.695489e-03
assigning %vreg208 to %RCX: CH [364r,496r:0)  0@364r CL [364r,496r:0)  0@364r

selectOrSplit GR64:%vreg207 [112r,364r:0)  0@112r w=1.549080e-03
hints: %RCX
RS_Assign Cascade 0
wait for second round
queuing new interval: %vreg207 [112r,364r:0)  0@112r

selectOrSplit GR64:%vreg205 [16r,360r:0)  0@16r w=2.715054e-03
hints: %R9
RS_Split Cascade 0
Analyze counted 2 instrs in 1 blocks, through 0 blocks.
Inline spilling GR64:%vreg205 [16r,360r:0)  0@16r
From original %vreg11
Merged spilled regs: SS#11 [16r,360r:0)  0@x
spillAroundUses %vreg205
	folded:   16r	MOV64mr <fi#11>, 1, %noreg, 0, %noreg, %R9; mem:ST8[FixedStack11]
Checking redundant spills for 0@360r in %vreg206 [360r,480r:0)  0@360r
Merged to stack int: SS#11 [16r,480r:0)  0@x
	folded:   360r	%vreg206<def> = MOV64rm <fi#11>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack11] GR64:%vreg206

selectOrSplit GR64:%vreg207 [112r,364r:0)  0@112r w=1.549080e-03
hints: %RCX
RS_Split Cascade 0
Analyze counted 2 instrs in 1 blocks, through 0 blocks.
Inline spilling GR64:%vreg207 [112r,364r:0)  0@112r
From original %vreg12
Value %vreg207:0@112r may remat from %vreg207<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg207
	remat:  368r	%vreg209<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg209
	        376e	%vreg208<def> = COPY %vreg209<kill>; GR64:%vreg208,%vreg209

All defs dead: %vreg207<def,dead> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg207
Remat created 1 dead defs.
Deleting dead def 112r	%vreg207<def,dead> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg207
0 registers to spill after remat.
queuing new interval: %vreg209 [368r,376r:0)  0@368r

selectOrSplit GR64:%vreg209 [368r,376r:0)  0@368r w=inf
hints: %RCX
assigning %vreg209 to %RCX: CH [368r,376r:0)  0@368r CL [368r,376r:0)  0@368r
Trying to reconcile hints for: %vreg6(%R14)
%vreg6(%R14) is recolorable.

********** STACK TRANSFORMATION METADATA **********
********** Function: BZ2_bzWriteClose64
********** REGISTER MAP **********
[%vreg6 -> %R14] GR64
[%vreg7 -> %RBX] GR64
[%vreg8 -> %R13D] GR32
[%vreg9 -> %R12] GR64
[%vreg10 -> %R15] GR64
[%vreg16 -> %RAX] GR64
[%vreg19 -> %RDI] GR64
[%vreg20 -> %RSI] GR64
[%vreg23 -> %RAX] GR64
[%vreg26 -> %RAX] GR64
[%vreg29 -> %RAX] GR64
[%vreg32 -> %EAX] GR32
[%vreg34 -> %RDI] GR64
[%vreg35 -> %RAX] GR64
[%vreg38 -> %RAX] GR64
[%vreg41 -> %RAX] GR64
[%vreg44 -> %RAX] GR64
[%vreg47 -> %RAX] GR64
[%vreg51 -> %RAX] GR64
[%vreg56 -> %EAX] GR32
[%vreg58 -> %RDI] GR64
[%vreg62 -> %RCX] GR64
[%vreg65 -> %RAX] GR64
[%vreg68 -> %RAX] GR64
[%vreg72 -> %RAX] GR64
[%vreg75 -> %EAX] GR32
[%vreg84 -> %RAX] GR64_with_sub_8bit
[%vreg86 -> %RCX] GR64
[%vreg87 -> %RAX] GR64
[%vreg89 -> %RDX] GR64
[%vreg92 -> %RDI] GR64
[%vreg97 -> %EAX] GR32
[%vreg99 -> %RCX] GR64
[%vreg102 -> %EAX] GR32
[%vreg104 -> %RDI] GR64
[%vreg105 -> %RAX] GR64
[%vreg109 -> %RAX] GR64
[%vreg112 -> %RAX] GR64
[%vreg116 -> %RCX] GR64
[%vreg117 -> %EAX] GR32
[%vreg121 -> %RCX] GR64
[%vreg122 -> %EAX] GR32
[%vreg126 -> %EAX] GR32
[%vreg128 -> %RDI] GR64
[%vreg129 -> %RAX] GR64
[%vreg132 -> %EAX] GR32
[%vreg134 -> %RDI] GR64
[%vreg135 -> %RAX] GR64
[%vreg137 -> %EAX] GR32
[%vreg139 -> %RDI] GR64
[%vreg140 -> %RAX] GR64
[%vreg143 -> %RAX] GR64
[%vreg146 -> %RAX] GR64
[%vreg150 -> %RCX] GR64
[%vreg152 -> %EAX] GR32
[%vreg153 -> %RAX] GR64
[%vreg157 -> %RCX] GR64
[%vreg159 -> %EAX] GR32
[%vreg160 -> %RAX] GR64
[%vreg164 -> %RCX] GR64
[%vreg166 -> %EAX] GR32
[%vreg167 -> %RAX] GR64
[%vreg171 -> %RCX] GR64
[%vreg173 -> %EAX] GR32
[%vreg174 -> %RAX] GR64
[%vreg177 -> %RAX] GR64
[%vreg180 -> %RAX] GR64
[%vreg183 -> %RDI] GR64
[%vreg186 -> %EAX] GR32
[%vreg188 -> %RDI] GR64
[%vreg192 -> %RAX] GR64
[%vreg195 -> %RAX] GR64
[%vreg198 -> %RAX] GR64
[%vreg201 -> %RAX] GR64
[%vreg203 -> %RDI] GR64
[%vreg204 -> %RSI] GR64
[%vreg206 -> %RAX] GR64
[%vreg208 -> %RCX] GR64
[%vreg209 -> %RCX] GR64
[%vreg11 -> fi#11] GR64
[%vreg205 -> fi#11] GR64


Stackmap 0:
  STACKMAP 0, 0, %vreg8, 0, <fi#2>, 0, %vreg7, 0, <fi#1>, 0, %vreg6, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, %vreg10, 0, <fi#4>, 0, %vreg9, 0, <fi#3>, 0, %vreg208, 0, <fi#6>, 0, %vreg206, 0, <fi#5>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4) GR32:%vreg8 GR64:%vreg7,%vreg6,%vreg10,%vreg9,%vreg208,%vreg206

i32 %abandon: in register %R13D (vreg 8)
i32* %abandon.addr: in stack slot 2 (size: 4)
i8* %b: in register %RBX (vreg 7)
i8** %b.addr: in stack slot 1 (size: 8)
i32* %bzerror: in register %R14 (vreg 6)
i32** %bzerror.addr: in stack slot 0 (size: 8)
%struct.bzFile** %bzf: in stack slot 10 (size: 8)
i32* %n: in stack slot 7 (size: 4)
i32* %n2: in stack slot 8 (size: 4)
i32* %nbytes_in_hi32: in register %R15 (vreg 10)
i32** %nbytes_in_hi32.addr: in stack slot 4 (size: 8)
i32* %nbytes_in_lo32: in register %R12 (vreg 9)
i32** %nbytes_in_lo32.addr: in stack slot 3 (size: 8)
i32* %nbytes_out_hi32: in register %RCX (vreg 208)
i32** %nbytes_out_hi32.addr: in stack slot 6 (size: 8)
i32* %nbytes_out_lo32: in register %RAX (vreg 206)
i32** %nbytes_out_lo32.addr: in stack slot 5 (size: 8)
i32* %ret: in stack slot 9 (size: 4)

Duplicate operand locations:

i32* %nbytes_out_lo32: in stack slot 11 (size: 8)

Stackmap 1:
  STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4)

i32* %abandon.addr: in stack slot 2 (size: 4)
i32** %bzerror.addr: in stack slot 0 (size: 8)
%struct.bzFile** %bzf: in stack slot 10 (size: 8)
i32* %n: in stack slot 7 (size: 4)
i32* %n2: in stack slot 8 (size: 4)
i32** %nbytes_in_hi32.addr: in stack slot 4 (size: 8)
i32** %nbytes_in_lo32.addr: in stack slot 3 (size: 8)
i32** %nbytes_out_hi32.addr: in stack slot 6 (size: 8)
i32** %nbytes_out_lo32.addr: in stack slot 5 (size: 8)
i32* %ret: in stack slot 9 (size: 4)

Duplicate operand locations:


Stackmap 2:
  STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4)

i32* %abandon.addr: in stack slot 2 (size: 4)
i32** %bzerror.addr: in stack slot 0 (size: 8)
%struct.bzFile** %bzf: in stack slot 10 (size: 8)
i32* %n: in stack slot 7 (size: 4)
i32* %n2: in stack slot 8 (size: 4)
i32** %nbytes_in_hi32.addr: in stack slot 4 (size: 8)
i32** %nbytes_in_lo32.addr: in stack slot 3 (size: 8)
i32** %nbytes_out_hi32.addr: in stack slot 6 (size: 8)
i32** %nbytes_out_lo32.addr: in stack slot 5 (size: 8)
i32* %ret: in stack slot 9 (size: 4)

Duplicate operand locations:


Stackmap 3:
  STACKMAP 3, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4)

i32* %abandon.addr: in stack slot 2 (size: 4)
i32** %bzerror.addr: in stack slot 0 (size: 8)
%struct.bzFile** %bzf: in stack slot 10 (size: 8)
i32* %n: in stack slot 7 (size: 4)
i32* %n2: in stack slot 8 (size: 4)
i32** %nbytes_in_hi32.addr: in stack slot 4 (size: 8)
i32** %nbytes_in_lo32.addr: in stack slot 3 (size: 8)
i32** %nbytes_out_hi32.addr: in stack slot 6 (size: 8)
i32** %nbytes_out_lo32.addr: in stack slot 5 (size: 8)
i32* %ret: in stack slot 9 (size: 4)

Duplicate operand locations:


Stackmap 4:
  STACKMAP 4, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4)

i32* %abandon.addr: in stack slot 2 (size: 4)
i32** %bzerror.addr: in stack slot 0 (size: 8)
%struct.bzFile** %bzf: in stack slot 10 (size: 8)
i32* %n: in stack slot 7 (size: 4)
i32* %n2: in stack slot 8 (size: 4)
i32** %nbytes_in_hi32.addr: in stack slot 4 (size: 8)
i32** %nbytes_in_lo32.addr: in stack slot 3 (size: 8)
i32** %nbytes_out_hi32.addr: in stack slot 6 (size: 8)
i32** %nbytes_out_lo32.addr: in stack slot 5 (size: 8)
i32* %ret: in stack slot 9 (size: 4)

Duplicate operand locations:


Stackmap 5:
  STACKMAP 5, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, ...; mem:LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5]

i32** %bzerror.addr: in stack slot 0 (size: 8)
%struct.bzFile** %bzf: in stack slot 10 (size: 8)
i32** %nbytes_in_hi32.addr: in stack slot 4 (size: 8)
i32** %nbytes_in_lo32.addr: in stack slot 3 (size: 8)
i32** %nbytes_out_hi32.addr: in stack slot 6 (size: 8)
i32** %nbytes_out_lo32.addr: in stack slot 5 (size: 8)

Duplicate operand locations:


Stackmap 6:
  STACKMAP 6, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, ...; mem:LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5]

i32** %bzerror.addr: in stack slot 0 (size: 8)
%struct.bzFile** %bzf: in stack slot 10 (size: 8)
i32** %nbytes_in_hi32.addr: in stack slot 4 (size: 8)
i32** %nbytes_in_lo32.addr: in stack slot 3 (size: 8)
i32** %nbytes_out_hi32.addr: in stack slot 6 (size: 8)
i32** %nbytes_out_lo32.addr: in stack slot 5 (size: 8)

Duplicate operand locations:


Stackmap 7:
  STACKMAP 7, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, ...; mem:LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5]

i32** %bzerror.addr: in stack slot 0 (size: 8)
%struct.bzFile** %bzf: in stack slot 10 (size: 8)
i32** %nbytes_in_hi32.addr: in stack slot 4 (size: 8)
i32** %nbytes_in_lo32.addr: in stack slot 3 (size: 8)
i32** %nbytes_out_hi32.addr: in stack slot 6 (size: 8)
i32** %nbytes_out_lo32.addr: in stack slot 5 (size: 8)

Duplicate operand locations:


Stackmap 8:
  STACKMAP 8, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack10]

%struct.bzFile** %bzf: in stack slot 10 (size: 8)

Duplicate operand locations:


Stackmap 9:
  STACKMAP 9, 0, ...


Duplicate operand locations:


Stackmap 10:
  STACKMAP 10, 0, ...


Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, %vreg8, 0, <fi#2>, 0, %vreg7, 0, <fi#1>, 0, %vreg6, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, %vreg10, 0, <fi#4>, 0, %vreg9, 0, <fi#3>, 0, %vreg208, 0, <fi#6>, 0, %vreg206, 0, <fi#5>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4) GR32:%vreg8 GR64:%vreg7,%vreg6,%vreg10,%vreg9,%vreg208,%vreg206
  -> Call instruction SlotIndex 320B, searching vregs 0 -> 210 and stack slots -2 -> 12

  STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4)
  -> Call instruction SlotIndex 1184B, searching vregs 0 -> 210 and stack slots -2 -> 12

  STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4)
  -> Call instruction SlotIndex 2304B, searching vregs 0 -> 210 and stack slots -2 -> 12

  STACKMAP 3, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4)
  -> Call instruction SlotIndex 3120B, searching vregs 0 -> 210 and stack slots -2 -> 12

  STACKMAP 4, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4)
  -> Call instruction SlotIndex 3376B, searching vregs 0 -> 210 and stack slots -2 -> 12

  STACKMAP 5, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, ...; mem:LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5]
  -> Call instruction SlotIndex 4032B, searching vregs 0 -> 210 and stack slots -2 -> 12

  STACKMAP 6, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, ...; mem:LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5]
  -> Call instruction SlotIndex 4240B, searching vregs 0 -> 210 and stack slots -2 -> 12

  STACKMAP 7, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, ...; mem:LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5]
  -> Call instruction SlotIndex 4400B, searching vregs 0 -> 210 and stack slots -2 -> 12

  STACKMAP 8, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack10]
  -> Call instruction SlotIndex 5584B, searching vregs 0 -> 210 and stack slots -2 -> 12

  STACKMAP 9, 0, ...
  -> Call instruction SlotIndex 5744B, searching vregs 0 -> 210 and stack slots -2 -> 12

  STACKMAP 10, 0, ...
  -> Call instruction SlotIndex 5936B, searching vregs 0 -> 210 and stack slots -2 -> 12

********** REWRITE VIRTUAL REGISTERS **********
********** Function: BZ2_bzWriteClose64
********** REGISTER MAP **********
[%vreg6 -> %R14] GR64
[%vreg7 -> %RBX] GR64
[%vreg8 -> %R13D] GR32
[%vreg9 -> %R12] GR64
[%vreg10 -> %R15] GR64
[%vreg16 -> %RAX] GR64
[%vreg19 -> %RDI] GR64
[%vreg20 -> %RSI] GR64
[%vreg23 -> %RAX] GR64
[%vreg26 -> %RAX] GR64
[%vreg29 -> %RAX] GR64
[%vreg32 -> %EAX] GR32
[%vreg34 -> %RDI] GR64
[%vreg35 -> %RAX] GR64
[%vreg38 -> %RAX] GR64
[%vreg41 -> %RAX] GR64
[%vreg44 -> %RAX] GR64
[%vreg47 -> %RAX] GR64
[%vreg51 -> %RAX] GR64
[%vreg56 -> %EAX] GR32
[%vreg58 -> %RDI] GR64
[%vreg62 -> %RCX] GR64
[%vreg65 -> %RAX] GR64
[%vreg68 -> %RAX] GR64
[%vreg72 -> %RAX] GR64
[%vreg75 -> %EAX] GR32
[%vreg84 -> %RAX] GR64_with_sub_8bit
[%vreg86 -> %RCX] GR64
[%vreg87 -> %RAX] GR64
[%vreg89 -> %RDX] GR64
[%vreg92 -> %RDI] GR64
[%vreg97 -> %EAX] GR32
[%vreg99 -> %RCX] GR64
[%vreg102 -> %EAX] GR32
[%vreg104 -> %RDI] GR64
[%vreg105 -> %RAX] GR64
[%vreg109 -> %RAX] GR64
[%vreg112 -> %RAX] GR64
[%vreg116 -> %RCX] GR64
[%vreg117 -> %EAX] GR32
[%vreg121 -> %RCX] GR64
[%vreg122 -> %EAX] GR32
[%vreg126 -> %EAX] GR32
[%vreg128 -> %RDI] GR64
[%vreg129 -> %RAX] GR64
[%vreg132 -> %EAX] GR32
[%vreg134 -> %RDI] GR64
[%vreg135 -> %RAX] GR64
[%vreg137 -> %EAX] GR32
[%vreg139 -> %RDI] GR64
[%vreg140 -> %RAX] GR64
[%vreg143 -> %RAX] GR64
[%vreg146 -> %RAX] GR64
[%vreg150 -> %RCX] GR64
[%vreg152 -> %EAX] GR32
[%vreg153 -> %RAX] GR64
[%vreg157 -> %RCX] GR64
[%vreg159 -> %EAX] GR32
[%vreg160 -> %RAX] GR64
[%vreg164 -> %RCX] GR64
[%vreg166 -> %EAX] GR32
[%vreg167 -> %RAX] GR64
[%vreg171 -> %RCX] GR64
[%vreg173 -> %EAX] GR32
[%vreg174 -> %RAX] GR64
[%vreg177 -> %RAX] GR64
[%vreg180 -> %RAX] GR64
[%vreg183 -> %RDI] GR64
[%vreg186 -> %EAX] GR32
[%vreg188 -> %RDI] GR64
[%vreg192 -> %RAX] GR64
[%vreg195 -> %RAX] GR64
[%vreg198 -> %RAX] GR64
[%vreg201 -> %RAX] GR64
[%vreg203 -> %RDI] GR64
[%vreg204 -> %RSI] GR64
[%vreg206 -> %RAX] GR64
[%vreg208 -> %RCX] GR64
[%vreg209 -> %RCX] GR64
[%vreg11 -> fi#11] GR64
[%vreg205 -> fi#11] GR64

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %EDX %RCX %RDI %RSI %R8 %R9
16B		MOV64mr <fi#11>, 1, %noreg, 0, %noreg, %R9; mem:ST8[FixedStack11]
32B		%vreg10<def> = COPY %R8; GR64:%vreg10
48B		%vreg9<def> = COPY %RCX; GR64:%vreg9
64B		%vreg8<def> = COPY %EDX; GR32:%vreg8
80B		%vreg7<def> = COPY %RSI; GR64:%vreg7
96B		%vreg6<def> = COPY %RDI; GR64:%vreg6
224B		%vreg19<def> = MOV64ri <ga:@BZ2_bzWriteClose64>; GR64:%vreg19
256B		%vreg20<def> = MOV64rm <fi#-2>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-2] GR64:%vreg20
272B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
288B		%RDI<def> = COPY %vreg19<kill>; GR64:%vreg19
304B		%RSI<def> = COPY %vreg20<kill>; GR64:%vreg20
320B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
336B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
352B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
360B		%vreg206<def> = MOV64rm <fi#11>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack11] GR64:%vreg206
368B		%vreg209<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg209
376B		%vreg208<def> = COPY %vreg209<kill>; GR64:%vreg208,%vreg209
384B		STACKMAP 0, 0, %vreg8, 0, <fi#2>, 0, %vreg7, 0, <fi#1>, 0, %vreg6, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, %vreg10, 0, <fi#4>, 0, %vreg9, 0, <fi#3>, 0, %vreg208, 0, <fi#6>, 0, %vreg206, 0, <fi#5>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4) GR32:%vreg8 GR64:%vreg7,%vreg6,%vreg10,%vreg9,%vreg208,%vreg206
392B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
400B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg6<kill>; mem:ST8[%bzerror.addr] GR64:%vreg6
416B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg7<kill>; mem:ST8[%b.addr] GR64:%vreg7
432B		MOV32mr <fi#2>, 1, %noreg, 0, %noreg, %vreg8<kill>; mem:ST4[%abandon.addr] GR32:%vreg8
448B		MOV64mr <fi#3>, 1, %noreg, 0, %noreg, %vreg9<kill>; mem:ST8[%nbytes_in_lo32.addr] GR64:%vreg9
464B		MOV64mr <fi#4>, 1, %noreg, 0, %noreg, %vreg10<kill>; mem:ST8[%nbytes_in_hi32.addr] GR64:%vreg10
480B		MOV64mr <fi#5>, 1, %noreg, 0, %noreg, %vreg206<kill>; mem:ST8[%nbytes_out_lo32.addr] GR64:%vreg206
496B		MOV64mr <fi#6>, 1, %noreg, 0, %noreg, %vreg208<kill>; mem:ST8[%nbytes_out_hi32.addr] GR64:%vreg208
512B		%vreg16<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr] GR64:%vreg16
544B		MOV64mr <fi#10>, 1, %noreg, 0, %noreg, %vreg16<kill>; mem:ST8[%bzf] GR64:%vreg16
560B		CMP64mi8 <fi#10>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
576B		JNE_1 <BB#6>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#6 BB#1
> MOV64mr <fi#11>, 1, %noreg, 0, %noreg, %R9; mem:ST8[FixedStack11]
> %R15<def> = COPY %R8
> %R12<def> = COPY %RCX
> %R13D<def> = COPY %EDX
> %RBX<def> = COPY %RSI
> %R14<def> = COPY %RDI
> %RDI<def> = MOV64ri <ga:@BZ2_bzWriteClose64>
> %RSI<def> = MOV64rm <fi#-2>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-2]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RAX<def> = MOV64rm <fi#11>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack11]
> %RCX<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> %RCX<def> = COPY %RCX<kill>
Deleting identity copy.
> STACKMAP 0, 0, %R13D, 0, <fi#2>, 0, %RBX, 0, <fi#1>, 0, %R14, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, %R15, 0, <fi#4>, 0, %R12, 0, <fi#3>, 0, %RCX, 0, <fi#6>, 0, %RAX, 0, <fi#5>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %R14<kill>; mem:ST8[%bzerror.addr]
> MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %RBX<kill>; mem:ST8[%b.addr]
> MOV32mr <fi#2>, 1, %noreg, 0, %noreg, %R13D<kill>; mem:ST4[%abandon.addr]
> MOV64mr <fi#3>, 1, %noreg, 0, %noreg, %R12<kill>; mem:ST8[%nbytes_in_lo32.addr]
> MOV64mr <fi#4>, 1, %noreg, 0, %noreg, %R15<kill>; mem:ST8[%nbytes_in_hi32.addr]
> MOV64mr <fi#5>, 1, %noreg, 0, %noreg, %RAX<kill>; mem:ST8[%nbytes_out_lo32.addr]
> MOV64mr <fi#6>, 1, %noreg, 0, %noreg, %RCX<kill>; mem:ST8[%nbytes_out_hi32.addr]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr]
> MOV64mr <fi#10>, 1, %noreg, 0, %noreg, %RAX<kill>; mem:ST8[%bzf]
> CMP64mi8 <fi#10>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
> JNE_1 <BB#6>, %EFLAGS<imp-use,kill>
592B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
608B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
624B		JE_1 <BB#3>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#3 BB#2
> CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
> JE_1 <BB#3>, %EFLAGS<imp-use,kill>
640B	BB#2: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#1
656B		%vreg198<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg198
672B		MOV32mi %vreg198<kill>, 1, %noreg, 0, %noreg, 0; mem:ST4[%4] GR64:%vreg198
	    Successors according to CFG: BB#3
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 0, %noreg, 0; mem:ST4[%4]
688B	BB#3: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#1 BB#2
704B		CMP64mi8 <fi#10>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
720B		JE_1 <BB#5>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#5 BB#4
> CMP64mi8 <fi#10>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
> JE_1 <BB#5>, %EFLAGS<imp-use,kill>
736B	BB#4: derived from LLVM BB %if.then.4
	    Predecessors according to CFG: BB#3
752B		%vreg201<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg201
768B		MOV32mi %vreg201<kill>, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr] GR64:%vreg201
	    Successors according to CFG: BB#5
> %RAX<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV32mi %RAX<kill>, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr]
784B	BB#5: derived from LLVM BB %if.end.5
	    Predecessors according to CFG: BB#3 BB#4
800B		JMP_1 <BB#71>
	    Successors according to CFG: BB#71
> JMP_1 <BB#71>
816B	BB#6: derived from LLVM BB %if.end.6
	    Predecessors according to CFG: BB#0
832B		%vreg23<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg23
848B		CMP8mi %vreg23<kill>, 1, %noreg, 5012, %noreg, 0, %EFLAGS<imp-def>; mem:LD1[%writing] GR64:%vreg23
864B		JNE_1 <BB#12>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#12 BB#7
> %RAX<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> CMP8mi %RAX<kill>, 1, %noreg, 5012, %noreg, 0, %EFLAGS<imp-def>; mem:LD1[%writing]
> JNE_1 <BB#12>, %EFLAGS<imp-use,kill>
880B	BB#7: derived from LLVM BB %if.then.7
	    Predecessors according to CFG: BB#6
896B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
912B		JE_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#8
> CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
> JE_1 <BB#9>, %EFLAGS<imp-use,kill>
928B	BB#8: derived from LLVM BB %if.then.9
	    Predecessors according to CFG: BB#7
944B		%vreg26<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg26
960B		MOV32mi %vreg26<kill>, 1, %noreg, 0, %noreg, -1; mem:ST4[%10] GR64:%vreg26
	    Successors according to CFG: BB#9
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 0, %noreg, -1; mem:ST4[%10]
976B	BB#9: derived from LLVM BB %if.end.10
	    Predecessors according to CFG: BB#7 BB#8
992B		CMP64mi8 <fi#10>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
1008B		JE_1 <BB#11>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#11 BB#10
> CMP64mi8 <fi#10>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
> JE_1 <BB#11>, %EFLAGS<imp-use,kill>
1024B	BB#10: derived from LLVM BB %if.then.12
	    Predecessors according to CFG: BB#9
1040B		%vreg29<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg29
1056B		MOV32mi %vreg29<kill>, 1, %noreg, 5096, %noreg, -1; mem:ST4[%lastErr13] GR64:%vreg29
	    Successors according to CFG: BB#11
> %RAX<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV32mi %RAX<kill>, 1, %noreg, 5096, %noreg, -1; mem:ST4[%lastErr13]
1072B	BB#11: derived from LLVM BB %if.end.14
	    Predecessors according to CFG: BB#9 BB#10
1088B		JMP_1 <BB#71>
	    Successors according to CFG: BB#71
> JMP_1 <BB#71>
1104B	BB#12: derived from LLVM BB %if.end.15
	    Predecessors according to CFG: BB#6
1120B		%vreg35<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg35
1136B		%vreg34<def> = MOV64rm %vreg35<kill>, 1, %noreg, 0, %noreg; mem:LD8[%handle] GR64:%vreg34,%vreg35
1152B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1168B		%RDI<def> = COPY %vreg34<kill>; GR64:%vreg34
1184B		CALL64pcrel32 <ga:@ferror>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
1200B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1216B		%vreg32<def> = COPY %EAX; GR32:%vreg32
1232B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1248B		STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4)
1264B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1280B		CMP32ri8 %vreg32<kill>, 0, %EFLAGS<imp-def>; GR32:%vreg32
1296B		JE_1 <BB#18>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#18 BB#13
> %RAX<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> %RDI<def> = MOV64rm %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%handle]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@ferror>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def> = COPY %EAX
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> CMP32ri8 %EAX<kill>, 0, %EFLAGS<imp-def>
> JE_1 <BB#18>, %EFLAGS<imp-use,kill>
1312B	BB#13: derived from LLVM BB %if.then.17
	    Predecessors according to CFG: BB#12
1328B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
1344B		JE_1 <BB#15>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#15 BB#14
> CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
> JE_1 <BB#15>, %EFLAGS<imp-use,kill>
1360B	BB#14: derived from LLVM BB %if.then.19
	    Predecessors according to CFG: BB#13
1376B		%vreg192<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg192
1392B		MOV32mi %vreg192<kill>, 1, %noreg, 0, %noreg, -6; mem:ST4[%16] GR64:%vreg192
	    Successors according to CFG: BB#15
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 0, %noreg, -6; mem:ST4[%16]
1408B	BB#15: derived from LLVM BB %if.end.20
	    Predecessors according to CFG: BB#13 BB#14
1424B		CMP64mi8 <fi#10>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
1440B		JE_1 <BB#17>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#17 BB#16
> CMP64mi8 <fi#10>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
> JE_1 <BB#17>, %EFLAGS<imp-use,kill>
1456B	BB#16: derived from LLVM BB %if.then.22
	    Predecessors according to CFG: BB#15
1472B		%vreg195<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg195
1488B		MOV32mi %vreg195<kill>, 1, %noreg, 5096, %noreg, -6; mem:ST4[%lastErr23] GR64:%vreg195
	    Successors according to CFG: BB#17
> %RAX<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV32mi %RAX<kill>, 1, %noreg, 5096, %noreg, -6; mem:ST4[%lastErr23]
1504B	BB#17: derived from LLVM BB %if.end.24
	    Predecessors according to CFG: BB#15 BB#16
1520B		JMP_1 <BB#71>
	    Successors according to CFG: BB#71
> JMP_1 <BB#71>
1536B	BB#18: derived from LLVM BB %if.end.25
	    Predecessors according to CFG: BB#12
1552B		CMP64mi8 <fi#3>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%nbytes_in_lo32.addr]
1568B		JE_1 <BB#20>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#20 BB#19
> CMP64mi8 <fi#3>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%nbytes_in_lo32.addr]
> JE_1 <BB#20>, %EFLAGS<imp-use,kill>
1584B	BB#19: derived from LLVM BB %if.then.27
	    Predecessors according to CFG: BB#18
1600B		%vreg38<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%nbytes_in_lo32.addr] GR64:%vreg38
1616B		MOV32mi %vreg38<kill>, 1, %noreg, 0, %noreg, 0; mem:ST4[%20] GR64:%vreg38
	    Successors according to CFG: BB#20
> %RAX<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%nbytes_in_lo32.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 0, %noreg, 0; mem:ST4[%20]
1632B	BB#20: derived from LLVM BB %if.end.28
	    Predecessors according to CFG: BB#18 BB#19
1648B		CMP64mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%nbytes_in_hi32.addr]
1664B		JE_1 <BB#22>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#22 BB#21
> CMP64mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%nbytes_in_hi32.addr]
> JE_1 <BB#22>, %EFLAGS<imp-use,kill>
1680B	BB#21: derived from LLVM BB %if.then.30
	    Predecessors according to CFG: BB#20
1696B		%vreg41<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%nbytes_in_hi32.addr] GR64:%vreg41
1712B		MOV32mi %vreg41<kill>, 1, %noreg, 0, %noreg, 0; mem:ST4[%22] GR64:%vreg41
	    Successors according to CFG: BB#22
> %RAX<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%nbytes_in_hi32.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 0, %noreg, 0; mem:ST4[%22]
1728B	BB#22: derived from LLVM BB %if.end.31
	    Predecessors according to CFG: BB#20 BB#21
1744B		CMP64mi8 <fi#5>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%nbytes_out_lo32.addr]
1760B		JE_1 <BB#24>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#24 BB#23
> CMP64mi8 <fi#5>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%nbytes_out_lo32.addr]
> JE_1 <BB#24>, %EFLAGS<imp-use,kill>
1776B	BB#23: derived from LLVM BB %if.then.33
	    Predecessors according to CFG: BB#22
1792B		%vreg44<def> = MOV64rm <fi#5>, 1, %noreg, 0, %noreg; mem:LD8[%nbytes_out_lo32.addr] GR64:%vreg44
1808B		MOV32mi %vreg44<kill>, 1, %noreg, 0, %noreg, 0; mem:ST4[%24] GR64:%vreg44
	    Successors according to CFG: BB#24
> %RAX<def> = MOV64rm <fi#5>, 1, %noreg, 0, %noreg; mem:LD8[%nbytes_out_lo32.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 0, %noreg, 0; mem:ST4[%24]
1824B	BB#24: derived from LLVM BB %if.end.34
	    Predecessors according to CFG: BB#22 BB#23
1840B		CMP64mi8 <fi#6>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%nbytes_out_hi32.addr]
1856B		JE_1 <BB#26>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#26 BB#25
> CMP64mi8 <fi#6>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%nbytes_out_hi32.addr]
> JE_1 <BB#26>, %EFLAGS<imp-use,kill>
1872B	BB#25: derived from LLVM BB %if.then.36
	    Predecessors according to CFG: BB#24
1888B		%vreg47<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%nbytes_out_hi32.addr] GR64:%vreg47
1904B		MOV32mi %vreg47<kill>, 1, %noreg, 0, %noreg, 0; mem:ST4[%26] GR64:%vreg47
	    Successors according to CFG: BB#26
> %RAX<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%nbytes_out_hi32.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 0, %noreg, 0; mem:ST4[%26]
1920B	BB#26: derived from LLVM BB %if.end.37
	    Predecessors according to CFG: BB#24 BB#25
1936B		CMP32mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%abandon.addr]
1952B		JNE_1 <BB#49>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#49 BB#27
> CMP32mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%abandon.addr]
> JNE_1 <BB#49>, %EFLAGS<imp-use,kill>
1968B	BB#27: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#26
1984B		%vreg51<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg51
2000B		CMP32mi8 %vreg51<kill>, 1, %noreg, 5096, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%lastErr39] GR64:%vreg51
2016B		JNE_1 <BB#49>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#49 BB#28
> %RAX<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> CMP32mi8 %RAX<kill>, 1, %noreg, 5096, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%lastErr39]
> JNE_1 <BB#49>, %EFLAGS<imp-use,kill>
2032B	BB#28: derived from LLVM BB %if.then.41
	    Predecessors according to CFG: BB#27
2048B		JMP_1 <BB#29>
	    Successors according to CFG: BB#29
> JMP_1 <BB#29>
2064B	BB#29: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#28 BB#47
2096B		%vreg68<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg68
2112B		MOV32mi %vreg68<kill>, 1, %noreg, 5048, %noreg, 5000; mem:ST4[%avail_out] GR64:%vreg68
2128B		%vreg65<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg65
2160B		%vreg65<def,tied1> = ADD64ri8 %vreg65<kill,tied0>, 8, %EFLAGS<imp-def,dead>; GR64:%vreg65
2176B		%vreg62<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg62
2192B		MOV64mr %vreg62<kill>, 1, %noreg, 5040, %noreg, %vreg65<kill>; mem:ST8[%next_out] GR64:%vreg62,%vreg65
2208B		%vreg58<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg58
2240B		%vreg58<def,tied1> = ADD64ri32 %vreg58<kill,tied0>, 5016, %EFLAGS<imp-def,dead>; GR64:%vreg58
2256B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2288B		%ESI<def> = MOV32ri 2
2296B		%RDI<def> = COPY %vreg58<kill>; GR64:%vreg58
2304B		CALL64pcrel32 <ga:@BZ2_bzCompress>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %EAX<imp-def>
2320B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2336B		%vreg56<def> = COPY %EAX; GR32:%vreg56
2352B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2368B		STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4)
2384B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2400B		MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %vreg56<kill>; mem:ST4[%ret] GR32:%vreg56
2416B		CMP32mi8 <fi#9>, 1, %noreg, 0, %noreg, 3, %EFLAGS<imp-def>; mem:LD4[%ret]
2432B		JE_1 <BB#36>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#36 BB#30
> %RAX<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV32mi %RAX<kill>, 1, %noreg, 5048, %noreg, 5000; mem:ST4[%avail_out]
> %RAX<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> %RAX<def,tied1> = ADD64ri8 %RAX<kill,tied0>, 8, %EFLAGS<imp-def,dead>
> %RCX<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV64mr %RCX<kill>, 1, %noreg, 5040, %noreg, %RAX<kill>; mem:ST8[%next_out]
> %RDI<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> %RDI<def,tied1> = ADD64ri32 %RDI<kill,tied0>, 5016, %EFLAGS<imp-def,dead>
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %ESI<def> = MOV32ri 2
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@BZ2_bzCompress>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %EAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def> = COPY %EAX
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%ret]
> CMP32mi8 <fi#9>, 1, %noreg, 0, %noreg, 3, %EFLAGS<imp-def>; mem:LD4[%ret]
> JE_1 <BB#36>, %EFLAGS<imp-use,kill>
2448B	BB#30: derived from LLVM BB %land.lhs.true.46
	    Predecessors according to CFG: BB#29
2464B		CMP32mi8 <fi#9>, 1, %noreg, 0, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%ret]
2480B		JE_1 <BB#36>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#36 BB#31
> CMP32mi8 <fi#9>, 1, %noreg, 0, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%ret]
> JE_1 <BB#36>, %EFLAGS<imp-use,kill>
2496B	BB#31: derived from LLVM BB %if.then.48
	    Predecessors according to CFG: BB#30
2512B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
2528B		JE_1 <BB#33>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#33 BB#32
> CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
> JE_1 <BB#33>, %EFLAGS<imp-use,kill>
2544B	BB#32: derived from LLVM BB %if.then.50
	    Predecessors according to CFG: BB#31
2560B		%vreg117<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%ret] GR32:%vreg117
2576B		%vreg116<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg116
2592B		MOV32mr %vreg116<kill>, 1, %noreg, 0, %noreg, %vreg117<kill>; mem:ST4[%38] GR64:%vreg116 GR32:%vreg117
	    Successors according to CFG: BB#33
> %EAX<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%ret]
> %RCX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr]
> MOV32mr %RCX<kill>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%38]
2608B	BB#33: derived from LLVM BB %if.end.51
	    Predecessors according to CFG: BB#31 BB#32
2624B		CMP64mi8 <fi#10>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
2640B		JE_1 <BB#35>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#35 BB#34
> CMP64mi8 <fi#10>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
> JE_1 <BB#35>, %EFLAGS<imp-use,kill>
2656B	BB#34: derived from LLVM BB %if.then.53
	    Predecessors according to CFG: BB#33
2672B		%vreg122<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%ret] GR32:%vreg122
2688B		%vreg121<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg121
2704B		MOV32mr %vreg121<kill>, 1, %noreg, 5096, %noreg, %vreg122<kill>; mem:ST4[%lastErr54] GR64:%vreg121 GR32:%vreg122
	    Successors according to CFG: BB#35
> %EAX<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%ret]
> %RCX<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV32mr %RCX<kill>, 1, %noreg, 5096, %noreg, %EAX<kill>; mem:ST4[%lastErr54]
2720B	BB#35: derived from LLVM BB %if.end.55
	    Predecessors according to CFG: BB#33 BB#34
2736B		JMP_1 <BB#71>
	    Successors according to CFG: BB#71
> JMP_1 <BB#71>
2752B	BB#36: derived from LLVM BB %if.end.56
	    Predecessors according to CFG: BB#29 BB#30
2768B		%vreg72<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg72
2784B		CMP32mi %vreg72<kill>, 1, %noreg, 5048, %noreg, 5000, %EFLAGS<imp-def>; mem:LD4[%avail_out58] GR64:%vreg72
2800B		JAE_1 <BB#45>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#45 BB#37
> %RAX<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> CMP32mi %RAX<kill>, 1, %noreg, 5048, %noreg, 5000, %EFLAGS<imp-def>; mem:LD4[%avail_out58]
> JAE_1 <BB#45>, %EFLAGS<imp-use,kill>
2816B	BB#37: derived from LLVM BB %if.then.60
	    Predecessors according to CFG: BB#36
2864B		%vreg97<def> = MOV32ri 5000; GR32:%vreg97
2880B		%vreg99<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg99
2912B		%vreg97<def,tied1> = SUB32rm %vreg97<kill,tied0>, %vreg99<kill>, 1, %noreg, 5048, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%avail_out62] GR32:%vreg97 GR64:%vreg99
2928B		MOV32mr <fi#7>, 1, %noreg, 0, %noreg, %vreg97<kill>; mem:ST4[%n] GR32:%vreg97
2944B		%vreg92<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg92
2976B		%vreg92<def,tied1> = ADD64ri8 %vreg92<kill,tied0>, 8, %EFLAGS<imp-def,dead>; GR64:%vreg92
2992B		%vreg89<def> = MOVSX64rm32 <fi#7>, 1, %noreg, 0, %noreg; mem:LD4[%n] GR64:%vreg89
3008B		%vreg87<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg87
3024B		%vreg86<def> = MOV64rm %vreg87<kill>, 1, %noreg, 0, %noreg; mem:LD8[%handle65] GR64:%vreg86,%vreg87
3040B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3072B		%ESI<def,dead> = MOV32ri 1, %RSI<imp-def>
3080B		%RDI<def> = COPY %vreg92<kill>; GR64:%vreg92
3088B		%RDX<def> = COPY %vreg89<kill>; GR64:%vreg89
3104B		%RCX<def> = COPY %vreg86<kill>; GR64:%vreg86
3120B		CALL64pcrel32 <ga:@fwrite>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %RDX<imp-use>, %RCX<imp-use>, %RAX<imp-def>
3136B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3152B		%vreg84<def> = COPY %RAX; GR64_with_sub_8bit:%vreg84
3168B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3184B		STACKMAP 3, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4)
3200B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3232B		MOV32mr <fi#8>, 1, %noreg, 0, %noreg, %vreg84:sub_32bit<kill>; mem:ST4[%n2] GR64_with_sub_8bit:%vreg84
3248B		%vreg75<def> = MOV32rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD4[%n] GR32:%vreg75
3264B		CMP32rm %vreg75<kill>, <fi#8>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD4[%n2] GR32:%vreg75
3280B		JNE_1 <BB#39>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#39 BB#38
> %EAX<def> = MOV32ri 5000
> %RCX<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> %EAX<def,tied1> = SUB32rm %EAX<kill,tied0>, %RCX<kill>, 1, %noreg, 5048, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%avail_out62]
> MOV32mr <fi#7>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%n]
> %RDI<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> %RDI<def,tied1> = ADD64ri8 %RDI<kill,tied0>, 8, %EFLAGS<imp-def,dead>
> %RDX<def> = MOVSX64rm32 <fi#7>, 1, %noreg, 0, %noreg; mem:LD4[%n]
> %RAX<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> %RCX<def> = MOV64rm %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%handle65]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %ESI<def,dead> = MOV32ri 1, %RSI<imp-def>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RDX<def> = COPY %RDX<kill>
Deleting identity copy.
> %RCX<def> = COPY %RCX<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@fwrite>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %RDX<imp-use>, %RCX<imp-use>, %RAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RAX<def> = COPY %RAX
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 3, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV32mr <fi#8>, 1, %noreg, 0, %noreg, %EAX, %RAX<imp-use,kill>; mem:ST4[%n2]
> %EAX<def> = MOV32rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD4[%n]
> CMP32rm %EAX<kill>, <fi#8>, 1, %noreg, 0, %noreg, %EFLAGS<imp-def>; mem:LD4[%n2]
> JNE_1 <BB#39>, %EFLAGS<imp-use,kill>
3296B	BB#38: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#37
3312B		%vreg105<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg105
3328B		%vreg104<def> = MOV64rm %vreg105<kill>, 1, %noreg, 0, %noreg; mem:LD8[%handle70] GR64:%vreg104,%vreg105
3344B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3360B		%RDI<def> = COPY %vreg104<kill>; GR64:%vreg104
3376B		CALL64pcrel32 <ga:@ferror>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
3392B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3408B		%vreg102<def> = COPY %EAX; GR32:%vreg102
3424B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3440B		STACKMAP 4, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4)
3456B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3472B		CMP32ri8 %vreg102<kill>, 0, %EFLAGS<imp-def>; GR32:%vreg102
3488B		JE_1 <BB#44>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#44 BB#39
> %RAX<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> %RDI<def> = MOV64rm %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%handle70]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@ferror>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def> = COPY %EAX
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 4, 0, 0, <fi#2>, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, 0, <fi#9>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack7](align=4) LD8[FixedStack8](align=4) LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5] LD8[FixedStack9](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> CMP32ri8 %EAX<kill>, 0, %EFLAGS<imp-def>
> JE_1 <BB#44>, %EFLAGS<imp-use,kill>
3504B	BB#39: derived from LLVM BB %if.then.73
	    Predecessors according to CFG: BB#37 BB#38
3520B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
3536B		JE_1 <BB#41>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#41 BB#40
> CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
> JE_1 <BB#41>, %EFLAGS<imp-use,kill>
3552B	BB#40: derived from LLVM BB %if.then.76
	    Predecessors according to CFG: BB#39
3568B		%vreg109<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg109
3584B		MOV32mi %vreg109<kill>, 1, %noreg, 0, %noreg, -6; mem:ST4[%55] GR64:%vreg109
	    Successors according to CFG: BB#41
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 0, %noreg, -6; mem:ST4[%55]
3600B	BB#41: derived from LLVM BB %if.end.77
	    Predecessors according to CFG: BB#39 BB#40
3616B		CMP64mi8 <fi#10>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
3632B		JE_1 <BB#43>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#43 BB#42
> CMP64mi8 <fi#10>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
> JE_1 <BB#43>, %EFLAGS<imp-use,kill>
3648B	BB#42: derived from LLVM BB %if.then.80
	    Predecessors according to CFG: BB#41
3664B		%vreg112<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg112
3680B		MOV32mi %vreg112<kill>, 1, %noreg, 5096, %noreg, -6; mem:ST4[%lastErr81] GR64:%vreg112
	    Successors according to CFG: BB#43
> %RAX<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV32mi %RAX<kill>, 1, %noreg, 5096, %noreg, -6; mem:ST4[%lastErr81]
3696B	BB#43: derived from LLVM BB %if.end.82
	    Predecessors according to CFG: BB#41 BB#42
3712B		JMP_1 <BB#71>
	    Successors according to CFG: BB#71
> JMP_1 <BB#71>
3728B	BB#44: derived from LLVM BB %if.end.83
	    Predecessors according to CFG: BB#38
3744B		JMP_1 <BB#45>
	    Successors according to CFG: BB#45
> JMP_1 <BB#45>
3760B	BB#45: derived from LLVM BB %if.end.84
	    Predecessors according to CFG: BB#36 BB#44
3776B		CMP32mi8 <fi#9>, 1, %noreg, 0, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%ret]
3792B		JNE_1 <BB#47>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#47 BB#46
> CMP32mi8 <fi#9>, 1, %noreg, 0, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%ret]
> JNE_1 <BB#47>, %EFLAGS<imp-use,kill>
3808B	BB#46: derived from LLVM BB %if.then.87
	    Predecessors according to CFG: BB#45
3824B		JMP_1 <BB#48>
	    Successors according to CFG: BB#48
> JMP_1 <BB#48>
3840B	BB#47: derived from LLVM BB %if.end.88
	    Predecessors according to CFG: BB#45
3856B		JMP_1 <BB#29>
	    Successors according to CFG: BB#29
> JMP_1 <BB#29>
3872B	BB#48: derived from LLVM BB %while.end
	    Predecessors according to CFG: BB#46
3888B		JMP_1 <BB#49>
	    Successors according to CFG: BB#49
> JMP_1 <BB#49>
3904B	BB#49: derived from LLVM BB %if.end.89
	    Predecessors according to CFG: BB#26 BB#27 BB#48
3920B		CMP32mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%abandon.addr]
3936B		JNE_1 <BB#58>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#58 BB#50
> CMP32mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%abandon.addr]
> JNE_1 <BB#58>, %EFLAGS<imp-use,kill>
3952B	BB#50: derived from LLVM BB %land.lhs.true.91
	    Predecessors according to CFG: BB#49
3968B		%vreg129<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg129
3984B		%vreg128<def> = MOV64rm %vreg129<kill>, 1, %noreg, 0, %noreg; mem:LD8[%handle92] GR64:%vreg128,%vreg129
4000B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4016B		%RDI<def> = COPY %vreg128<kill>; GR64:%vreg128
4032B		CALL64pcrel32 <ga:@ferror>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
4048B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4064B		%vreg126<def> = COPY %EAX; GR32:%vreg126
4080B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4096B		STACKMAP 5, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, ...; mem:LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5]
4112B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4128B		CMP32ri8 %vreg126<kill>, 0, %EFLAGS<imp-def>; GR32:%vreg126
4144B		JNE_1 <BB#58>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#58 BB#51
> %RAX<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> %RDI<def> = MOV64rm %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%handle92]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@ferror>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def> = COPY %EAX
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 5, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, ...; mem:LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> CMP32ri8 %EAX<kill>, 0, %EFLAGS<imp-def>
> JNE_1 <BB#58>, %EFLAGS<imp-use,kill>
4160B	BB#51: derived from LLVM BB %if.then.95
	    Predecessors according to CFG: BB#50
4176B		%vreg140<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg140
4192B		%vreg139<def> = MOV64rm %vreg140<kill>, 1, %noreg, 0, %noreg; mem:LD8[%handle96] GR64:%vreg139,%vreg140
4208B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4224B		%RDI<def> = COPY %vreg139<kill>; GR64:%vreg139
4240B		CALL64pcrel32 <ga:@fflush>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
4256B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4272B		%vreg137<def,dead> = COPY %EAX; GR32:%vreg137
4288B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4304B		STACKMAP 6, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, ...; mem:LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5]
4320B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4336B		%vreg135<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg135
4352B		%vreg134<def> = MOV64rm %vreg135<kill>, 1, %noreg, 0, %noreg; mem:LD8[%handle98] GR64:%vreg134,%vreg135
4368B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4384B		%RDI<def> = COPY %vreg134<kill>; GR64:%vreg134
4400B		CALL64pcrel32 <ga:@ferror>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
4416B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4432B		%vreg132<def> = COPY %EAX; GR32:%vreg132
4448B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4464B		STACKMAP 7, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, ...; mem:LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5]
4480B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4496B		CMP32ri8 %vreg132<kill>, 0, %EFLAGS<imp-def>; GR32:%vreg132
4512B		JE_1 <BB#57>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#57 BB#52
> %RAX<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> %RDI<def> = MOV64rm %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%handle96]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@fflush>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def,dead> = COPY %EAX
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 6, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, ...; mem:LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RAX<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> %RDI<def> = MOV64rm %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%handle98]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@ferror>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def> = COPY %EAX
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 7, 0, 0, <fi#0>, 0, 0, <fi#10>, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#6>, 0, 0, <fi#5>, 0, ...; mem:LD8[FixedStack0] LD8[FixedStack10] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack6] LD8[FixedStack5]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> CMP32ri8 %EAX<kill>, 0, %EFLAGS<imp-def>
> JE_1 <BB#57>, %EFLAGS<imp-use,kill>
4528B	BB#52: derived from LLVM BB %if.then.101
	    Predecessors according to CFG: BB#51
4544B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
4560B		JE_1 <BB#54>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#54 BB#53
> CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
> JE_1 <BB#54>, %EFLAGS<imp-use,kill>
4576B	BB#53: derived from LLVM BB %if.then.104
	    Predecessors according to CFG: BB#52
4592B		%vreg143<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg143
4608B		MOV32mi %vreg143<kill>, 1, %noreg, 0, %noreg, -6; mem:ST4[%67] GR64:%vreg143
	    Successors according to CFG: BB#54
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 0, %noreg, -6; mem:ST4[%67]
4624B	BB#54: derived from LLVM BB %if.end.105
	    Predecessors according to CFG: BB#52 BB#53
4640B		CMP64mi8 <fi#10>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
4656B		JE_1 <BB#56>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#56 BB#55
> CMP64mi8 <fi#10>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
> JE_1 <BB#56>, %EFLAGS<imp-use,kill>
4672B	BB#55: derived from LLVM BB %if.then.108
	    Predecessors according to CFG: BB#54
4688B		%vreg146<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg146
4704B		MOV32mi %vreg146<kill>, 1, %noreg, 5096, %noreg, -6; mem:ST4[%lastErr109] GR64:%vreg146
	    Successors according to CFG: BB#56
> %RAX<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV32mi %RAX<kill>, 1, %noreg, 5096, %noreg, -6; mem:ST4[%lastErr109]
4720B	BB#56: derived from LLVM BB %if.end.110
	    Predecessors according to CFG: BB#54 BB#55
4736B		JMP_1 <BB#71>
	    Successors according to CFG: BB#71
> JMP_1 <BB#71>
4752B	BB#57: derived from LLVM BB %if.end.111
	    Predecessors according to CFG: BB#51
4768B		JMP_1 <BB#58>
	    Successors according to CFG: BB#58
> JMP_1 <BB#58>
4784B	BB#58: derived from LLVM BB %if.end.112
	    Predecessors according to CFG: BB#49 BB#50 BB#57
4800B		CMP64mi8 <fi#3>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%nbytes_in_lo32.addr]
4816B		JE_1 <BB#60>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#60 BB#59
> CMP64mi8 <fi#3>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%nbytes_in_lo32.addr]
> JE_1 <BB#60>, %EFLAGS<imp-use,kill>
4832B	BB#59: derived from LLVM BB %if.then.115
	    Predecessors according to CFG: BB#58
4848B		%vreg153<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg153
4864B		%vreg152<def> = MOV32rm %vreg153<kill>, 1, %noreg, 5028, %noreg; mem:LD4[%total_in_lo32] GR32:%vreg152 GR64:%vreg153
4880B		%vreg150<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%nbytes_in_lo32.addr] GR64:%vreg150
4896B		MOV32mr %vreg150<kill>, 1, %noreg, 0, %noreg, %vreg152<kill>; mem:ST4[%73] GR64:%vreg150 GR32:%vreg152
	    Successors according to CFG: BB#60
> %RAX<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 5028, %noreg; mem:LD4[%total_in_lo32]
> %RCX<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%nbytes_in_lo32.addr]
> MOV32mr %RCX<kill>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%73]
4912B	BB#60: derived from LLVM BB %if.end.117
	    Predecessors according to CFG: BB#58 BB#59
4928B		CMP64mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%nbytes_in_hi32.addr]
4944B		JE_1 <BB#62>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#62 BB#61
> CMP64mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%nbytes_in_hi32.addr]
> JE_1 <BB#62>, %EFLAGS<imp-use,kill>
4960B	BB#61: derived from LLVM BB %if.then.120
	    Predecessors according to CFG: BB#60
4976B		%vreg160<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg160
4992B		%vreg159<def> = MOV32rm %vreg160<kill>, 1, %noreg, 5032, %noreg; mem:LD4[%total_in_hi32] GR32:%vreg159 GR64:%vreg160
5008B		%vreg157<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%nbytes_in_hi32.addr] GR64:%vreg157
5024B		MOV32mr %vreg157<kill>, 1, %noreg, 0, %noreg, %vreg159<kill>; mem:ST4[%77] GR64:%vreg157 GR32:%vreg159
	    Successors according to CFG: BB#62
> %RAX<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 5032, %noreg; mem:LD4[%total_in_hi32]
> %RCX<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%nbytes_in_hi32.addr]
> MOV32mr %RCX<kill>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%77]
5040B	BB#62: derived from LLVM BB %if.end.122
	    Predecessors according to CFG: BB#60 BB#61
5056B		CMP64mi8 <fi#5>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%nbytes_out_lo32.addr]
5072B		JE_1 <BB#64>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#64 BB#63
> CMP64mi8 <fi#5>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%nbytes_out_lo32.addr]
> JE_1 <BB#64>, %EFLAGS<imp-use,kill>
5088B	BB#63: derived from LLVM BB %if.then.125
	    Predecessors according to CFG: BB#62
5104B		%vreg167<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg167
5120B		%vreg166<def> = MOV32rm %vreg167<kill>, 1, %noreg, 5052, %noreg; mem:LD4[%total_out_lo32] GR32:%vreg166 GR64:%vreg167
5136B		%vreg164<def> = MOV64rm <fi#5>, 1, %noreg, 0, %noreg; mem:LD8[%nbytes_out_lo32.addr] GR64:%vreg164
5152B		MOV32mr %vreg164<kill>, 1, %noreg, 0, %noreg, %vreg166<kill>; mem:ST4[%81] GR64:%vreg164 GR32:%vreg166
	    Successors according to CFG: BB#64
> %RAX<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 5052, %noreg; mem:LD4[%total_out_lo32]
> %RCX<def> = MOV64rm <fi#5>, 1, %noreg, 0, %noreg; mem:LD8[%nbytes_out_lo32.addr]
> MOV32mr %RCX<kill>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%81]
5168B	BB#64: derived from LLVM BB %if.end.127
	    Predecessors according to CFG: BB#62 BB#63
5184B		CMP64mi8 <fi#6>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%nbytes_out_hi32.addr]
5200B		JE_1 <BB#66>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#66 BB#65
> CMP64mi8 <fi#6>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%nbytes_out_hi32.addr]
> JE_1 <BB#66>, %EFLAGS<imp-use,kill>
5216B	BB#65: derived from LLVM BB %if.then.130
	    Predecessors according to CFG: BB#64
5232B		%vreg174<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg174
5248B		%vreg173<def> = MOV32rm %vreg174<kill>, 1, %noreg, 5056, %noreg; mem:LD4[%total_out_hi32] GR32:%vreg173 GR64:%vreg174
5264B		%vreg171<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%nbytes_out_hi32.addr] GR64:%vreg171
5280B		MOV32mr %vreg171<kill>, 1, %noreg, 0, %noreg, %vreg173<kill>; mem:ST4[%85] GR64:%vreg171 GR32:%vreg173
	    Successors according to CFG: BB#66
> %RAX<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 5056, %noreg; mem:LD4[%total_out_hi32]
> %RCX<def> = MOV64rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD8[%nbytes_out_hi32.addr]
> MOV32mr %RCX<kill>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%85]
5296B	BB#66: derived from LLVM BB %if.end.132
	    Predecessors according to CFG: BB#64 BB#65
5312B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
5328B		JE_1 <BB#68>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#68 BB#67
> CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
> JE_1 <BB#68>, %EFLAGS<imp-use,kill>
5344B	BB#67: derived from LLVM BB %if.then.135
	    Predecessors according to CFG: BB#66
5360B		%vreg177<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg177
5376B		MOV32mi %vreg177<kill>, 1, %noreg, 0, %noreg, 0; mem:ST4[%87] GR64:%vreg177
	    Successors according to CFG: BB#68
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 0, %noreg, 0; mem:ST4[%87]
5392B	BB#68: derived from LLVM BB %if.end.136
	    Predecessors according to CFG: BB#66 BB#67
5408B		CMP64mi8 <fi#10>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
5424B		JE_1 <BB#70>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#70 BB#69
> CMP64mi8 <fi#10>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
> JE_1 <BB#70>, %EFLAGS<imp-use,kill>
5440B	BB#69: derived from LLVM BB %if.then.139
	    Predecessors according to CFG: BB#68
5456B		%vreg180<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg180
5472B		MOV32mi %vreg180<kill>, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr140] GR64:%vreg180
	    Successors according to CFG: BB#70
> %RAX<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV32mi %RAX<kill>, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr140]
5488B	BB#70: derived from LLVM BB %if.end.141
	    Predecessors according to CFG: BB#68 BB#69
5504B		%vreg188<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg188
5536B		%vreg188<def,tied1> = ADD64ri32 %vreg188<kill,tied0>, 5016, %EFLAGS<imp-def,dead>; GR64:%vreg188
5552B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5568B		%RDI<def> = COPY %vreg188<kill>; GR64:%vreg188
5584B		CALL64pcrel32 <ga:@BZ2_bzCompressEnd>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
5600B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5616B		%vreg186<def,dead> = COPY %EAX; GR32:%vreg186
5632B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5648B		STACKMAP 8, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack10]
5664B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5680B		%vreg183<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg183
5712B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5728B		%RDI<def> = COPY %vreg183<kill>; GR64:%vreg183
5744B		CALL64pcrel32 <ga:@free>, <regmask>, %RSP<imp-use>, %RDI<imp-use>
5760B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5776B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5792B		STACKMAP 9, 0, ...
5808B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#71
> %RDI<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> %RDI<def,tied1> = ADD64ri32 %RDI<kill,tied0>, 5016, %EFLAGS<imp-def,dead>
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@BZ2_bzCompressEnd>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def,dead> = COPY %EAX
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 8, 0, 0, <fi#10>, 0, ...; mem:LD8[FixedStack10]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@free>, <regmask>, %RSP<imp-use>, %RDI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 9, 0, ...
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5824B	BB#71: derived from LLVM BB %return
	    Predecessors according to CFG: BB#11 BB#43 BB#35 BB#56 BB#70 BB#17 BB#5
5840B		%vreg203<def> = MOV64ri <ga:@BZ2_bzWriteClose64>; GR64:%vreg203
5872B		%vreg204<def> = MOV64rm <fi#-2>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-2] GR64:%vreg204
5888B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5904B		%RDI<def> = COPY %vreg203<kill>; GR64:%vreg203
5920B		%RSI<def> = COPY %vreg204<kill>; GR64:%vreg204
5936B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
5952B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5968B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5984B		STACKMAP 10, 0, ...
6000B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
6016B		RETQ
> %RDI<def> = MOV64ri <ga:@BZ2_bzWriteClose64>
> %RSI<def> = MOV64rm <fi#-2>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-2]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 10, 0, ...
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> RETQ
Computing live-in reg-units in ABI blocks.
0B	BB#0 DIL#0 SIL#0 DH#0 DL#0 CH#0 CL#0 R8B#0 R9B#0
Created 8 new intervals.
********** INTERVALS **********
CH [0B,48r:0)  0@0B-phi
CL [0B,48r:0)  0@0B-phi
DH [0B,64r:0)[3280r,3296r:1)  0@0B-phi 1@3280r
DIL [0B,96r:0)[272r,304r:6)[1440r,1456r:5)[1888r,1904r:4)[3248r,3296r:3)[3728r,3744r:2)[4176r,4208r:1)  0@0B-phi 1@4176r 2@3728r 3@3248r 4@1888r 5@1440r 6@272r
DL [0B,64r:0)[3280r,3296r:1)  0@0B-phi 1@3280r
SIL [0B,80r:0)[288r,304r:3)[3264r,3296r:1)[4192r,4208r:2)  0@0B-phi 1@3264r 2@4192r 3@288r
R8B [0B,32r:0)  0@0B-phi
R9B [0B,16r:0)  0@0B-phi
%vreg0 [96r,112r:0)  0@96r
%vreg1 [112r,384r:0)  0@112r
%vreg2 [80r,128r:0)  0@80r
%vreg3 [128r,400r:0)  0@128r
%vreg4 [64r,144r:0)  0@64r
%vreg5 [144r,416r:0)  0@144r
%vreg6 [48r,160r:0)  0@48r
%vreg7 [160r,432r:0)  0@160r
%vreg8 [32r,176r:0)  0@32r
%vreg9 [176r,448r:0)  0@176r
%vreg10 [16r,192r:0)  0@16r
%vreg11 [192r,464r:0)  0@192r
%vreg13 [208r,224r:0)  0@208r
%vreg14 [224r,272r:0)  0@224r
%vreg15 [240r,288r:0)  0@240r
%vreg17 [544r,560r:0)  0@544r
%vreg20 [640r,656r:0)  0@640r
%vreg33 [1488r,1552r:0)  0@1488r
%vreg34 [1408r,1440r:0)  0@1408r
%vreg38 [2000r,2016r:0)  0@2000r
%vreg39 [1840r,1856r:0)  0@1840r
%vreg40 [1856r,1888r:0)  0@1856r
%vreg41 [1936r,2000r:0)  0@1936r
%vreg44 [2368r,2384r:0)  0@2368r
%vreg47 [2464r,2480r:0)  0@2464r
%vreg49 [2720r,2736r:0)  0@2720r
%vreg51 [2688r,2704r:0)  0@2688r
%vreg53 [2656r,2672r:0)  0@2656r
%vreg55 [2624r,2640r:0)  0@2624r
%vreg57 [2592r,2608r:0)  0@2592r
%vreg60 [2560r,2576r:0)  0@2560r
%vreg61 [2544r,2576r:0)  0@2544r
%vreg63 [2512r,2528r:0)  0@2512r
%vreg70 [3328r,3392r:0)  0@3328r
%vreg71 [3216r,3280r:0)  0@3216r
%vreg72 [3200r,3264r:0)  0@3200r
%vreg74 [3168r,3184r:0)[3184r,3248r:1)  0@3168r 1@3184r
%vreg75 [3152r,3168r:0)  0@3152r
%vreg78 [4064r,4080r:0)  0@4064r
%vreg79 [4048r,4064r:0)  0@4048r
%vreg81 [4016r,4032r:0)  0@4016r
%vreg84 [3984r,4000r:0)  0@3984r
%vreg87 [3952r,3968r:0)[3968r,4000r:1)  0@3952r 1@3968r
%vreg88 [3936r,3952r:0)  0@3936r
%vreg91 [3904r,3920r:0)  0@3904r
%vreg93 [3888r,3920r:0)  0@3888r
%vreg94 [3872r,3888r:0)  0@3872r
%vreg98 [3520r,3536r:0)  0@3520r
%vreg99 [3504r,3536r:0)  0@3504r
%vreg103 [3632r,3648r:0)  0@3632r
%vreg104 [3616r,3648r:0)  0@3616r
%vreg107 [3696r,3728r:0)  0@3696r
%vreg108 [3680r,3696r:0)  0@3680r
%vreg111 [3072r,3088r:0)[3088r,3104r:1)  0@3072r 1@3088r
%vreg112 [3056r,3072r:0)  0@3056r
%vreg115 [3008r,3024r:0)[3024r,3040r:1)  0@3008r 1@3024r
%vreg116 [2992r,3008r:0)  0@2992r
%vreg120 [2944r,2960r:0)[2960r,2976r:1)  0@2944r 1@2960r
%vreg121 [2928r,2944r:0)  0@2928r
%vreg122 [2912r,2976r:0)  0@2912r
%vreg126 [2880r,2896r:0)  0@2880r
%vreg128 [2864r,2896r:0)  0@2864r
%vreg130 [2848r,2864r:0)  0@2848r
%vreg132 [2832r,2896r:0)  0@2832r
%vreg133 [2816r,2832r:0)  0@2816r
%vreg136 [2128r,2144r:0)  0@2128r
%vreg139 [2224r,2240r:0)  0@2224r
%vreg142 [1648r,1664r:0)  0@1648r
%vreg145 [1744r,1760r:0)  0@1744r
%vreg148 [1216r,1232r:0)  0@1216r
%vreg151 [1312r,1328r:0)  0@1312r
%vreg153 [4288r,4304r:0)  0@4288r
%vreg154 [4112r,4128r:0)  0@4112r
%vreg155 [4128r,4176r:0)  0@4128r
%vreg156 [4144r,4192r:0)  0@4144r
RegMasks: 304r 1456r 1904r 3296r 3744r 4208r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzReadOpen: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=8, align=8, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=8, align=8, at location [SP+8]
  fi#3: size=4, align=4, at location [SP+8]
  fi#4: size=4, align=4, at location [SP+8]
  fi#5: size=8, align=8, at location [SP+8]
  fi#6: size=4, align=4, at location [SP+8]
  fi#7: size=8, align=8, at location [SP+8]
  fi#8: size=4, align=4, at location [SP+8]
Function Live Ins: %RDI in %vreg0, %RSI in %vreg2, %EDX in %vreg4, %ECX in %vreg6, %R8 in %vreg8, %R9D in %vreg10

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI %RSI %EDX %ECX %R8 %R9D
16B		%vreg10<def> = COPY %R9D; GR32:%vreg10
32B		%vreg8<def> = COPY %R8; GR64:%vreg8
48B		%vreg6<def> = COPY %ECX; GR32:%vreg6
64B		%vreg4<def> = COPY %EDX; GR32:%vreg4
80B		%vreg2<def> = COPY %RSI; GR64:%vreg2
96B		%vreg0<def> = COPY %RDI; GR64:%vreg0
112B		%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
128B		%vreg3<def> = COPY %vreg2; GR64:%vreg3,%vreg2
144B		%vreg5<def> = COPY %vreg4; GR32:%vreg5,%vreg4
160B		%vreg7<def> = COPY %vreg6; GR32:%vreg7,%vreg6
176B		%vreg9<def> = COPY %vreg8; GR64:%vreg9,%vreg8
192B		%vreg11<def> = COPY %vreg10; GR32:%vreg11,%vreg10
208B		%vreg13<def> = MOV64ri <ga:@BZ2_bzReadOpen>; GR64:%vreg13
224B		%vreg14<def> = COPY %vreg13; GR64:%vreg14,%vreg13
240B		%vreg15<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg15
256B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
272B		%RDI<def> = COPY %vreg14; GR64:%vreg14
288B		%RSI<def> = COPY %vreg15; GR64:%vreg15
304B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
320B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
336B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
352B		STACKMAP 0, 0, %vreg1, 0, <fi#1>, 0, 0, <fi#7>, 0, %vreg3, 0, <fi#2>, 0, %vreg11, 0, <fi#6>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, %vreg7, 0, <fi#4>, 0, %vreg9, 0, <fi#5>, 0, %vreg5, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack8](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5] LD8[FixedStack3](align=4) GR64:%vreg1,%vreg3,%vreg9 GR32:%vreg11,%vreg7,%vreg5
368B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
384B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%bzerror.addr] GR64:%vreg1
400B		MOV64mr <fi#2>, 1, %noreg, 0, %noreg, %vreg3; mem:ST8[%f.addr] GR64:%vreg3
416B		MOV32mr <fi#3>, 1, %noreg, 0, %noreg, %vreg5; mem:ST4[%verbosity.addr] GR32:%vreg5
432B		MOV32mr <fi#4>, 1, %noreg, 0, %noreg, %vreg7; mem:ST4[%small.addr] GR32:%vreg7
448B		MOV64mr <fi#5>, 1, %noreg, 0, %noreg, %vreg9; mem:ST8[%unused.addr] GR64:%vreg9
464B		MOV32mr <fi#6>, 1, %noreg, 0, %noreg, %vreg11; mem:ST4[%nUnused.addr] GR32:%vreg11
480B		MOV64mi32 <fi#7>, 1, %noreg, 0, %noreg, 0; mem:ST8[%bzf]
496B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
512B		JE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

528B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
544B		%vreg17<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg17
560B		MOV32mi %vreg17, 1, %noreg, 0, %noreg, 0; mem:ST4[%1] GR64:%vreg17
	    Successors according to CFG: BB#2

576B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#1
592B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
608B		JE_1 <BB#4>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#4 BB#3

624B	BB#3: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#2
640B		%vreg20<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg20
656B		MOV32mi %vreg20, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr] GR64:%vreg20
	    Successors according to CFG: BB#4

672B	BB#4: derived from LLVM BB %if.end.3
	    Predecessors according to CFG: BB#2 BB#3
688B		CMP64mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%f.addr]
704B		JE_1 <BB#14>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#14 BB#5

720B	BB#5: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#4
736B		CMP32mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%small.addr]
752B		JE_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#6

768B	BB#6: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#5
784B		CMP32mi8 <fi#4>, 1, %noreg, 0, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%small.addr]
800B		JNE_1 <BB#14>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#14 BB#7

816B	BB#7: derived from LLVM BB %lor.lhs.false.7
	    Predecessors according to CFG: BB#5 BB#6
832B		CMP32mi8 <fi#3>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%verbosity.addr]
848B		JL_1 <BB#14>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#14 BB#8

864B	BB#8: derived from LLVM BB %lor.lhs.false.9
	    Predecessors according to CFG: BB#7
880B		CMP32mi8 <fi#3>, 1, %noreg, 0, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%verbosity.addr]
896B		JG_1 <BB#14>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#14 BB#9

912B	BB#9: derived from LLVM BB %lor.lhs.false.11
	    Predecessors according to CFG: BB#8
928B		CMP64mi8 <fi#5>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%unused.addr]
944B		JNE_1 <BB#11>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#11 BB#10

960B	BB#10: derived from LLVM BB %land.lhs.true.13
	    Predecessors according to CFG: BB#9
976B		CMP32mi8 <fi#6>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%nUnused.addr]
992B		JNE_1 <BB#14>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#14 BB#11

1008B	BB#11: derived from LLVM BB %lor.lhs.false.15
	    Predecessors according to CFG: BB#9 BB#10
1024B		CMP64mi8 <fi#5>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%unused.addr]
1040B		JE_1 <BB#19>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#19 BB#12

1056B	BB#12: derived from LLVM BB %land.lhs.true.17
	    Predecessors according to CFG: BB#11
1072B		CMP32mi8 <fi#6>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%nUnused.addr]
1088B		JL_1 <BB#14>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#14 BB#13

1104B	BB#13: derived from LLVM BB %lor.lhs.false.19
	    Predecessors according to CFG: BB#12
1120B		CMP32mi <fi#6>, 1, %noreg, 0, %noreg, 5000, %EFLAGS<imp-def>; mem:LD4[%nUnused.addr]
1136B		JLE_1 <BB#19>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#19 BB#14

1152B	BB#14: derived from LLVM BB %if.then.21
	    Predecessors according to CFG: BB#4 BB#6 BB#7 BB#8 BB#10 BB#12 BB#13
1168B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
1184B		JE_1 <BB#16>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#16 BB#15

1200B	BB#15: derived from LLVM BB %if.then.23
	    Predecessors according to CFG: BB#14
1216B		%vreg148<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg148
1232B		MOV32mi %vreg148, 1, %noreg, 0, %noreg, -2; mem:ST4[%15] GR64:%vreg148
	    Successors according to CFG: BB#16

1248B	BB#16: derived from LLVM BB %if.end.24
	    Predecessors according to CFG: BB#14 BB#15
1264B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
1280B		JE_1 <BB#18>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#18 BB#17

1296B	BB#17: derived from LLVM BB %if.then.26
	    Predecessors according to CFG: BB#16
1312B		%vreg151<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg151
1328B		MOV32mi %vreg151, 1, %noreg, 5096, %noreg, -2; mem:ST4[%lastErr27] GR64:%vreg151
	    Successors according to CFG: BB#18

1344B	BB#18: derived from LLVM BB %if.end.28
	    Predecessors according to CFG: BB#16 BB#17
1360B		MOV64mi32 <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST8[%retval]
1376B		JMP_1 <BB#45>
	    Successors according to CFG: BB#45

1392B	BB#19: derived from LLVM BB %if.end.29
	    Predecessors according to CFG: BB#11 BB#13
1408B		%vreg34<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%f.addr] GR64:%vreg34
1424B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1440B		%RDI<def> = COPY %vreg34; GR64:%vreg34
1456B		CALL64pcrel32 <ga:@ferror>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
1472B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1488B		%vreg33<def> = COPY %EAX<kill>; GR32:%vreg33
1504B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1520B		STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#2>, 0, 0, <fi#6>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack8](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5] LD8[FixedStack3](align=4)
1536B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1552B		CMP32ri8 %vreg33, 0, %EFLAGS<imp-def>; GR32:%vreg33
1568B		JE_1 <BB#25>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#25 BB#20

1584B	BB#20: derived from LLVM BB %if.then.30
	    Predecessors according to CFG: BB#19
1600B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
1616B		JE_1 <BB#22>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#22 BB#21

1632B	BB#21: derived from LLVM BB %if.then.32
	    Predecessors according to CFG: BB#20
1648B		%vreg142<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg142
1664B		MOV32mi %vreg142, 1, %noreg, 0, %noreg, -6; mem:ST4[%20] GR64:%vreg142
	    Successors according to CFG: BB#22

1680B	BB#22: derived from LLVM BB %if.end.33
	    Predecessors according to CFG: BB#20 BB#21
1696B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
1712B		JE_1 <BB#24>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#24 BB#23

1728B	BB#23: derived from LLVM BB %if.then.35
	    Predecessors according to CFG: BB#22
1744B		%vreg145<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg145
1760B		MOV32mi %vreg145, 1, %noreg, 5096, %noreg, -6; mem:ST4[%lastErr36] GR64:%vreg145
	    Successors according to CFG: BB#24

1776B	BB#24: derived from LLVM BB %if.end.37
	    Predecessors according to CFG: BB#22 BB#23
1792B		MOV64mi32 <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST8[%retval]
1808B		JMP_1 <BB#45>
	    Successors according to CFG: BB#45

1824B	BB#25: derived from LLVM BB %if.end.38
	    Predecessors according to CFG: BB#19
1840B		%vreg39<def> = MOV32ri 5104; GR32:%vreg39
1856B		%vreg40<def> = SUBREG_TO_REG 0, %vreg39, 4; GR64:%vreg40 GR32:%vreg39
1872B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1888B		%RDI<def> = COPY %vreg40; GR64:%vreg40
1904B		CALL64pcrel32 <ga:@malloc>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RAX<imp-def>
1920B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1936B		%vreg41<def> = COPY %RAX<kill>; GR64:%vreg41
1952B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1968B		STACKMAP 2, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#2>, 0, 0, <fi#6>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack8](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5] LD8[FixedStack3](align=4)
1984B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2000B		%vreg38<def> = COPY %vreg41; GR64:%vreg38,%vreg41
2016B		MOV64mr <fi#7>, 1, %noreg, 0, %noreg, %vreg38; mem:ST8[%bzf] GR64:%vreg38
2032B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
2048B		JNE_1 <BB#31>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#31 BB#26

2064B	BB#26: derived from LLVM BB %if.then.41
	    Predecessors according to CFG: BB#25
2080B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
2096B		JE_1 <BB#28>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#28 BB#27

2112B	BB#27: derived from LLVM BB %if.then.43
	    Predecessors according to CFG: BB#26
2128B		%vreg136<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg136
2144B		MOV32mi %vreg136, 1, %noreg, 0, %noreg, -3; mem:ST4[%26] GR64:%vreg136
	    Successors according to CFG: BB#28

2160B	BB#28: derived from LLVM BB %if.end.44
	    Predecessors according to CFG: BB#26 BB#27
2176B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
2192B		JE_1 <BB#30>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#30 BB#29

2208B	BB#29: derived from LLVM BB %if.then.46
	    Predecessors according to CFG: BB#28
2224B		%vreg139<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg139
2240B		MOV32mi %vreg139, 1, %noreg, 5096, %noreg, -3; mem:ST4[%lastErr47] GR64:%vreg139
	    Successors according to CFG: BB#30

2256B	BB#30: derived from LLVM BB %if.end.48
	    Predecessors according to CFG: BB#28 BB#29
2272B		MOV64mi32 <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST8[%retval]
2288B		JMP_1 <BB#45>
	    Successors according to CFG: BB#45

2304B	BB#31: derived from LLVM BB %if.end.49
	    Predecessors according to CFG: BB#25
2320B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
2336B		JE_1 <BB#33>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#33 BB#32

2352B	BB#32: derived from LLVM BB %if.then.51
	    Predecessors according to CFG: BB#31
2368B		%vreg44<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg44
2384B		MOV32mi %vreg44, 1, %noreg, 0, %noreg, 0; mem:ST4[%30] GR64:%vreg44
	    Successors according to CFG: BB#33

2400B	BB#33: derived from LLVM BB %if.end.52
	    Predecessors according to CFG: BB#31 BB#32
2416B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
2432B		JE_1 <BB#35>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#35 BB#34

2448B	BB#34: derived from LLVM BB %if.then.54
	    Predecessors according to CFG: BB#33
2464B		%vreg47<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg47
2480B		MOV32mi %vreg47, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr55] GR64:%vreg47
	    Successors according to CFG: BB#35

2496B	BB#35: derived from LLVM BB %if.end.56
	    Predecessors according to CFG: BB#33 BB#34
2512B		%vreg63<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg63
2528B		MOV8mi %vreg63, 1, %noreg, 5100, %noreg, 0; mem:ST1[%initialisedOk] GR64:%vreg63
2544B		%vreg61<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%f.addr] GR64:%vreg61
2560B		%vreg60<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg60
2576B		MOV64mr %vreg60, 1, %noreg, 0, %noreg, %vreg61; mem:ST8[%handle] GR64:%vreg60,%vreg61
2592B		%vreg57<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg57
2608B		MOV32mi %vreg57, 1, %noreg, 5008, %noreg, 0; mem:ST4[%bufN] GR64:%vreg57
2624B		%vreg55<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg55
2640B		MOV8mi %vreg55, 1, %noreg, 5012, %noreg, 0; mem:ST1[%writing] GR64:%vreg55
2656B		%vreg53<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg53
2672B		MOV64mi32 %vreg53, 1, %noreg, 5072, %noreg, 0; mem:ST8[%bzalloc] GR64:%vreg53
2688B		%vreg51<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg51
2704B		MOV64mi32 %vreg51, 1, %noreg, 5080, %noreg, 0; mem:ST8[%bzfree] GR64:%vreg51
2720B		%vreg49<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg49
2736B		MOV64mi32 %vreg49, 1, %noreg, 5088, %noreg, 0; mem:ST8[%opaque] GR64:%vreg49
	    Successors according to CFG: BB#36

2752B	BB#36: derived from LLVM BB %while.cond
	    Predecessors according to CFG: BB#35 BB#37
2768B		CMP32mi8 <fi#6>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%nUnused.addr]
2784B		JLE_1 <BB#38>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#38 BB#37

2800B	BB#37: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#36
2816B		%vreg133<def> = MOV64rm <fi#5>, 1, %noreg, 0, %noreg; mem:LD8[%unused.addr] GR64:%vreg133
2832B		%vreg132<def> = MOV8rm %vreg133, 1, %noreg, 0, %noreg; mem:LD1[%42] GR8:%vreg132 GR64:%vreg133
2848B		%vreg130<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg130
2864B		%vreg128<def> = MOVSX64rm32 %vreg130, 1, %noreg, 5008, %noreg; mem:LD4[%bufN60] GR64_NOSP:%vreg128 GR64:%vreg130
2880B		%vreg126<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg126
2896B		MOV8mr %vreg126, 1, %vreg128, 8, %noreg, %vreg132; mem:ST1[%arrayidx] GR64:%vreg126 GR64_NOSP:%vreg128 GR8:%vreg132
2912B		%vreg122<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg122
2928B		%vreg121<def> = MOV32rm %vreg122, 1, %noreg, 5008, %noreg; mem:LD4[%bufN61] GR32:%vreg121 GR64:%vreg122
2944B		%vreg120<def> = COPY %vreg121; GR32:%vreg120,%vreg121
2960B		%vreg120<def,tied1> = ADD32ri8 %vreg120<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg120
2976B		MOV32mr %vreg122, 1, %noreg, 5008, %noreg, %vreg120; mem:ST4[%bufN61] GR64:%vreg122 GR32:%vreg120
2992B		%vreg116<def> = MOV64rm <fi#5>, 1, %noreg, 0, %noreg; mem:LD8[%unused.addr] GR64:%vreg116
3008B		%vreg115<def> = COPY %vreg116; GR64:%vreg115,%vreg116
3024B		%vreg115<def,tied1> = ADD64ri8 %vreg115<tied0>, 1, %EFLAGS<imp-def,dead>; GR64:%vreg115
3040B		MOV64mr <fi#5>, 1, %noreg, 0, %noreg, %vreg115; mem:ST8[%unused.addr] GR64:%vreg115
3056B		%vreg112<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%nUnused.addr] GR32:%vreg112
3072B		%vreg111<def> = COPY %vreg112; GR32:%vreg111,%vreg112
3088B		%vreg111<def,tied1> = ADD32ri8 %vreg111<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg111
3104B		MOV32mr <fi#6>, 1, %noreg, 0, %noreg, %vreg111; mem:ST4[%nUnused.addr] GR32:%vreg111
3120B		JMP_1 <BB#36>
	    Successors according to CFG: BB#36

3136B	BB#38: derived from LLVM BB %while.end
	    Predecessors according to CFG: BB#36
3152B		%vreg75<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg75
3168B		%vreg74<def> = COPY %vreg75; GR64:%vreg74,%vreg75
3184B		%vreg74<def,tied1> = ADD64ri32 %vreg74<tied0>, 5016, %EFLAGS<imp-def,dead>; GR64:%vreg74
3200B		%vreg72<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%verbosity.addr] GR32:%vreg72
3216B		%vreg71<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%small.addr] GR32:%vreg71
3232B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3248B		%RDI<def> = COPY %vreg74; GR64:%vreg74
3264B		%ESI<def> = COPY %vreg72; GR32:%vreg72
3280B		%EDX<def> = COPY %vreg71; GR32:%vreg71
3296B		CALL64pcrel32 <ga:@BZ2_bzDecompressInit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %EDX<imp-use>, %EAX<imp-def>
3312B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3328B		%vreg70<def> = COPY %EAX<kill>; GR32:%vreg70
3344B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3360B		STACKMAP 3, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack8](align=4) LD8[FixedStack0]
3376B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3392B		MOV32mr <fi#8>, 1, %noreg, 0, %noreg, %vreg70; mem:ST4[%ret] GR32:%vreg70
3408B		CMP32mi8 <fi#8>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%ret]
3424B		JE_1 <BB#44>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#44 BB#39

3440B	BB#39: derived from LLVM BB %if.then.65
	    Predecessors according to CFG: BB#38
3456B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
3472B		JE_1 <BB#41>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#41 BB#40

3488B	BB#40: derived from LLVM BB %if.then.67
	    Predecessors according to CFG: BB#39
3504B		%vreg99<def> = MOV32rm <fi#8>, 1, %noreg, 0, %noreg; mem:LD4[%ret] GR32:%vreg99
3520B		%vreg98<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg98
3536B		MOV32mr %vreg98, 1, %noreg, 0, %noreg, %vreg99; mem:ST4[%57] GR64:%vreg98 GR32:%vreg99
	    Successors according to CFG: BB#41

3552B	BB#41: derived from LLVM BB %if.end.68
	    Predecessors according to CFG: BB#39 BB#40
3568B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
3584B		JE_1 <BB#43>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#43 BB#42

3600B	BB#42: derived from LLVM BB %if.then.70
	    Predecessors according to CFG: BB#41
3616B		%vreg104<def> = MOV32rm <fi#8>, 1, %noreg, 0, %noreg; mem:LD4[%ret] GR32:%vreg104
3632B		%vreg103<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg103
3648B		MOV32mr %vreg103, 1, %noreg, 5096, %noreg, %vreg104; mem:ST4[%lastErr71] GR64:%vreg103 GR32:%vreg104
	    Successors according to CFG: BB#43

3664B	BB#43: derived from LLVM BB %if.end.72
	    Predecessors according to CFG: BB#41 BB#42
3680B		%vreg108<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg108
3696B		%vreg107<def> = COPY %vreg108; GR64:%vreg107,%vreg108
3712B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3728B		%RDI<def> = COPY %vreg107; GR64:%vreg107
3744B		CALL64pcrel32 <ga:@free>, <regmask>, %RSP<imp-use>, %RDI<imp-use>
3760B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3776B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3792B		STACKMAP 4, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0]
3808B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3824B		MOV64mi32 <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST8[%retval]
3840B		JMP_1 <BB#45>
	    Successors according to CFG: BB#45

3856B	BB#44: derived from LLVM BB %if.end.73
	    Predecessors according to CFG: BB#38
3872B		%vreg94<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg94
3888B		%vreg93<def> = MOV32rm %vreg94, 1, %noreg, 5008, %noreg; mem:LD4[%bufN74] GR32:%vreg93 GR64:%vreg94
3904B		%vreg91<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg91
3920B		MOV32mr %vreg91, 1, %noreg, 5024, %noreg, %vreg93; mem:ST4[%avail_in] GR64:%vreg91 GR32:%vreg93
3936B		%vreg88<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg88
3952B		%vreg87<def> = COPY %vreg88; GR64:%vreg87,%vreg88
3968B		%vreg87<def,tied1> = ADD64ri8 %vreg87<tied0>, 8, %EFLAGS<imp-def,dead>; GR64:%vreg87
3984B		%vreg84<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg84
4000B		MOV64mr %vreg84, 1, %noreg, 5016, %noreg, %vreg87; mem:ST8[%next_in] GR64:%vreg84,%vreg87
4016B		%vreg81<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg81
4032B		MOV8mi %vreg81, 1, %noreg, 5100, %noreg, 1; mem:ST1[%initialisedOk78] GR64:%vreg81
4048B		%vreg79<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg79
4064B		%vreg78<def> = COPY %vreg79; GR64:%vreg78,%vreg79
4080B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg78; mem:ST8[%retval] GR64:%vreg78
	    Successors according to CFG: BB#45

4096B	BB#45: derived from LLVM BB %return
	    Predecessors according to CFG: BB#44 BB#43 BB#30 BB#24 BB#18
4112B		%vreg154<def> = MOV64ri <ga:@BZ2_bzReadOpen>; GR64:%vreg154
4128B		%vreg155<def> = COPY %vreg154; GR64:%vreg155,%vreg154
4144B		%vreg156<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg156
4160B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4176B		%RDI<def> = COPY %vreg155; GR64:%vreg155
4192B		%RSI<def> = COPY %vreg156; GR64:%vreg156
4208B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
4224B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4240B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4256B		STACKMAP 5, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0]
4272B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4288B		%vreg153<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%retval] GR64:%vreg153
4304B		%RAX<def> = COPY %vreg153; GR64:%vreg153
4320B		RETQ %RAX<imp-use,kill>

# End machine code for function BZ2_bzReadOpen.

********** SIMPLE REGISTER COALESCING **********
********** Function: BZ2_bzReadOpen
********** JOINING INTERVALS ***********
while.cond:
while.body:
2944B	%vreg120<def> = COPY %vreg121; GR32:%vreg120,%vreg121
	Considering merging to GR32 with %vreg121 in %vreg120
		RHS = %vreg121 [2928r,2944r:0)  0@2928r
		LHS = %vreg120 [2944r,2960r:0)[2960r,2976r:1)  0@2944r 1@2960r
		merge %vreg120:0@2944r into %vreg121:0@2928r --> @2928r
		erased:	2944r	%vreg120<def> = COPY %vreg121; GR32:%vreg120,%vreg121
		updated: 2928B	%vreg120<def> = MOV32rm %vreg122, 1, %noreg, 5008, %noreg; mem:LD4[%bufN61] GR32:%vreg120 GR64:%vreg122
	Success: %vreg121 -> %vreg120
	Result = %vreg120 [2928r,2960r:0)[2960r,2976r:1)  0@2928r 1@2960r
3008B	%vreg115<def> = COPY %vreg116; GR64:%vreg115,%vreg116
	Considering merging to GR64 with %vreg116 in %vreg115
		RHS = %vreg116 [2992r,3008r:0)  0@2992r
		LHS = %vreg115 [3008r,3024r:0)[3024r,3040r:1)  0@3008r 1@3024r
		merge %vreg115:0@3008r into %vreg116:0@2992r --> @2992r
		erased:	3008r	%vreg115<def> = COPY %vreg116; GR64:%vreg115,%vreg116
		updated: 2992B	%vreg115<def> = MOV64rm <fi#5>, 1, %noreg, 0, %noreg; mem:LD8[%unused.addr] GR64:%vreg115
	Success: %vreg116 -> %vreg115
	Result = %vreg115 [2992r,3024r:0)[3024r,3040r:1)  0@2992r 1@3024r
3072B	%vreg111<def> = COPY %vreg112; GR32:%vreg111,%vreg112
	Considering merging to GR32 with %vreg112 in %vreg111
		RHS = %vreg112 [3056r,3072r:0)  0@3056r
		LHS = %vreg111 [3072r,3088r:0)[3088r,3104r:1)  0@3072r 1@3088r
		merge %vreg111:0@3072r into %vreg112:0@3056r --> @3056r
		erased:	3072r	%vreg111<def> = COPY %vreg112; GR32:%vreg111,%vreg112
		updated: 3056B	%vreg111<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%nUnused.addr] GR32:%vreg111
	Success: %vreg112 -> %vreg111
	Result = %vreg111 [3056r,3088r:0)[3088r,3104r:1)  0@3056r 1@3088r
if.then.21:
return:
4176B	%RDI<def> = COPY %vreg155; GR64:%vreg155
	Considering merging %vreg155 with %RDI
	Can only merge into reserved registers.
4192B	%RSI<def> = COPY %vreg156; GR64:%vreg156
	Considering merging %vreg156 with %RSI
	Can only merge into reserved registers.
4304B	%RAX<def> = COPY %vreg153; GR64:%vreg153
	Considering merging %vreg153 with %RAX
	Can only merge into reserved registers.
if.end:
if.end.3:
lor.lhs.false.7:
lor.lhs.false.15:
if.end.24:
if.end.29:
1440B	%RDI<def> = COPY %vreg34; GR64:%vreg34
	Considering merging %vreg34 with %RDI
	Can only merge into reserved registers.
1488B	%vreg33<def> = COPY %EAX<kill>; GR32:%vreg33
	Considering merging %vreg33 with %EAX
	Can only merge into reserved registers.
if.end.33:
if.end.44:
if.end.52:
if.end.68:
lor.lhs.false:
land.lhs.true:
lor.lhs.false.9:
lor.lhs.false.11:
land.lhs.true.13:
land.lhs.true.17:
lor.lhs.false.19:
if.end.28:
if.then.30:
if.end.37:
if.end.38:
1856B	%vreg40<def> = SUBREG_TO_REG 0, %vreg39, 4; GR64:%vreg40 GR32:%vreg39
	Considering merging to GR64_with_sub_8bit with %vreg39 in %vreg40:sub_32bit
		RHS = %vreg39 [1840r,1856r:0)  0@1840r
		LHS = %vreg40 [1856r,1888r:0)  0@1856r
		merge %vreg40:0@1856r into %vreg39:0@1840r --> @1840r
		erased:	1856r	%vreg40<def> = SUBREG_TO_REG 0, %vreg39, 4; GR64:%vreg40 GR32:%vreg39
		updated: 1840B	%vreg40:sub_32bit<def,read-undef> = MOV32ri 5104; GR64_with_sub_8bit:%vreg40
	Success: %vreg39:sub_32bit -> %vreg40
	Result = %vreg40 [1840r,1888r:0)  0@1840r
1888B	%RDI<def> = COPY %vreg40; GR64_with_sub_8bit:%vreg40
	Considering merging %vreg40 with %RDI
	Can only merge into reserved registers.
Remat: %EDI<def,dead> = MOV32ri 5104, %RDI<imp-def>
Shrink: %vreg40 [1840r,1888r:0)  0@1840r
All defs dead: 1840r	%vreg40:sub_32bit<def,read-undef,dead> = MOV32ri 5104; GR64_with_sub_8bit:%vreg40
Shrunk: %vreg40 [1840r,1840d:0)  0@1840r
Deleting dead def 1840r	%vreg40:sub_32bit<def,read-undef,dead> = MOV32ri 5104; GR64_with_sub_8bit:%vreg40
1936B	%vreg41<def> = COPY %RAX<kill>; GR64:%vreg41
	Considering merging %vreg41 with %RAX
	Can only merge into reserved registers.
if.then.41:
if.end.48:
if.end.49:
if.end.56:
while.end:
3248B	%RDI<def> = COPY %vreg74; GR64:%vreg74
	Considering merging %vreg74 with %RDI
	Can only merge into reserved registers.
3264B	%ESI<def> = COPY %vreg72; GR32:%vreg72
	Considering merging %vreg72 with %ESI
	Can only merge into reserved registers.
3280B	%EDX<def> = COPY %vreg71; GR32:%vreg71
	Considering merging %vreg71 with %EDX
	Can only merge into reserved registers.
3328B	%vreg70<def> = COPY %EAX<kill>; GR32:%vreg70
	Considering merging %vreg70 with %EAX
	Can only merge into reserved registers.
if.then.65:
if.end.72:
3728B	%RDI<def> = COPY %vreg107; GR64:%vreg107
	Considering merging %vreg107 with %RDI
	Can only merge into reserved registers.
entry:
16B	%vreg10<def> = COPY %R9D; GR32:%vreg10
	Considering merging %vreg10 with %R9D
	Can only merge into reserved registers.
32B	%vreg8<def> = COPY %R8; GR64:%vreg8
	Considering merging %vreg8 with %R8
	Can only merge into reserved registers.
48B	%vreg6<def> = COPY %ECX; GR32:%vreg6
	Considering merging %vreg6 with %ECX
	Can only merge into reserved registers.
64B	%vreg4<def> = COPY %EDX; GR32:%vreg4
	Considering merging %vreg4 with %EDX
	Can only merge into reserved registers.
80B	%vreg2<def> = COPY %RSI; GR64:%vreg2
	Considering merging %vreg2 with %RSI
	Can only merge into reserved registers.
96B	%vreg0<def> = COPY %RDI; GR64:%vreg0
	Considering merging %vreg0 with %RDI
	Can only merge into reserved registers.
272B	%RDI<def> = COPY %vreg14; GR64:%vreg14
	Considering merging %vreg14 with %RDI
	Can only merge into reserved registers.
288B	%RSI<def> = COPY %vreg15; GR64:%vreg15
	Considering merging %vreg15 with %RSI
	Can only merge into reserved registers.
if.then:
if.then.2:
if.then.23:
if.then.26:
if.then.32:
if.then.35:
if.then.43:
if.then.46:
if.then.51:
if.then.54:
if.then.67:
if.then.70:
if.end.73:
4128B	%vreg155<def> = COPY %vreg154; GR64:%vreg155,%vreg154
	Considering merging to GR64 with %vreg154 in %vreg155
		RHS = %vreg154 [4112r,4128r:0)  0@4112r
		LHS = %vreg155 [4128r,4176r:0)  0@4128r
		merge %vreg155:0@4128r into %vreg154:0@4112r --> @4112r
		erased:	4128r	%vreg155<def> = COPY %vreg154; GR64:%vreg155,%vreg154
		updated: 4112B	%vreg155<def> = MOV64ri <ga:@BZ2_bzReadOpen>; GR64:%vreg155
	Success: %vreg154 -> %vreg155
	Result = %vreg155 [4112r,4176r:0)  0@4112r
2000B	%vreg38<def> = COPY %vreg41; GR64:%vreg38,%vreg41
	Considering merging to GR64 with %vreg41 in %vreg38
		RHS = %vreg41 [1936r,2000r:0)  0@1936r
		LHS = %vreg38 [2000r,2016r:0)  0@2000r
		merge %vreg38:0@2000r into %vreg41:0@1936r --> @1936r
		erased:	2000r	%vreg38<def> = COPY %vreg41; GR64:%vreg38,%vreg41
		updated: 1936B	%vreg38<def> = COPY %RAX<kill>; GR64:%vreg38
	Success: %vreg41 -> %vreg38
	Result = %vreg38 [1936r,2016r:0)  0@1936r
3168B	%vreg74<def> = COPY %vreg75; GR64:%vreg74,%vreg75
	Considering merging to GR64 with %vreg75 in %vreg74
		RHS = %vreg75 [3152r,3168r:0)  0@3152r
		LHS = %vreg74 [3168r,3184r:0)[3184r,3248r:1)  0@3168r 1@3184r
		merge %vreg74:0@3168r into %vreg75:0@3152r --> @3152r
		erased:	3168r	%vreg74<def> = COPY %vreg75; GR64:%vreg74,%vreg75
		updated: 3152B	%vreg74<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg74
	Success: %vreg75 -> %vreg74
	Result = %vreg74 [3152r,3184r:0)[3184r,3248r:1)  0@3152r 1@3184r
3696B	%vreg107<def> = COPY %vreg108; GR64:%vreg107,%vreg108
	Considering merging to GR64 with %vreg108 in %vreg107
		RHS = %vreg108 [3680r,3696r:0)  0@3680r
		LHS = %vreg107 [3696r,3728r:0)  0@3696r
		merge %vreg107:0@3696r into %vreg108:0@3680r --> @3680r
		erased:	3696r	%vreg107<def> = COPY %vreg108; GR64:%vreg107,%vreg108
		updated: 3680B	%vreg107<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg107
	Success: %vreg108 -> %vreg107
	Result = %vreg107 [3680r,3728r:0)  0@3680r
112B	%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
	Considering merging to GR64 with %vreg0 in %vreg1
		RHS = %vreg0 [96r,112r:0)  0@96r
		LHS = %vreg1 [112r,384r:0)  0@112r
		merge %vreg1:0@112r into %vreg0:0@96r --> @96r
		erased:	112r	%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
		updated: 96B	%vreg1<def> = COPY %RDI; GR64:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [96r,384r:0)  0@96r
128B	%vreg3<def> = COPY %vreg2; GR64:%vreg3,%vreg2
	Considering merging to GR64 with %vreg2 in %vreg3
		RHS = %vreg2 [80r,128r:0)  0@80r
		LHS = %vreg3 [128r,400r:0)  0@128r
		merge %vreg3:0@128r into %vreg2:0@80r --> @80r
		erased:	128r	%vreg3<def> = COPY %vreg2; GR64:%vreg3,%vreg2
		updated: 80B	%vreg3<def> = COPY %RSI; GR64:%vreg3
	Success: %vreg2 -> %vreg3
	Result = %vreg3 [80r,400r:0)  0@80r
144B	%vreg5<def> = COPY %vreg4; GR32:%vreg5,%vreg4
	Considering merging to GR32 with %vreg4 in %vreg5
		RHS = %vreg4 [64r,144r:0)  0@64r
		LHS = %vreg5 [144r,416r:0)  0@144r
		merge %vreg5:0@144r into %vreg4:0@64r --> @64r
		erased:	144r	%vreg5<def> = COPY %vreg4; GR32:%vreg5,%vreg4
		updated: 64B	%vreg5<def> = COPY %EDX; GR32:%vreg5
	Success: %vreg4 -> %vreg5
	Result = %vreg5 [64r,416r:0)  0@64r
160B	%vreg7<def> = COPY %vreg6; GR32:%vreg7,%vreg6
	Considering merging to GR32 with %vreg6 in %vreg7
		RHS = %vreg6 [48r,160r:0)  0@48r
		LHS = %vreg7 [160r,432r:0)  0@160r
		merge %vreg7:0@160r into %vreg6:0@48r --> @48r
		erased:	160r	%vreg7<def> = COPY %vreg6; GR32:%vreg7,%vreg6
		updated: 48B	%vreg7<def> = COPY %ECX; GR32:%vreg7
	Success: %vreg6 -> %vreg7
	Result = %vreg7 [48r,432r:0)  0@48r
176B	%vreg9<def> = COPY %vreg8; GR64:%vreg9,%vreg8
	Considering merging to GR64 with %vreg8 in %vreg9
		RHS = %vreg8 [32r,176r:0)  0@32r
		LHS = %vreg9 [176r,448r:0)  0@176r
		merge %vreg9:0@176r into %vreg8:0@32r --> @32r
		erased:	176r	%vreg9<def> = COPY %vreg8; GR64:%vreg9,%vreg8
		updated: 32B	%vreg9<def> = COPY %R8; GR64:%vreg9
	Success: %vreg8 -> %vreg9
	Result = %vreg9 [32r,448r:0)  0@32r
192B	%vreg11<def> = COPY %vreg10; GR32:%vreg11,%vreg10
	Considering merging to GR32 with %vreg10 in %vreg11
		RHS = %vreg10 [16r,192r:0)  0@16r
		LHS = %vreg11 [192r,464r:0)  0@192r
		merge %vreg11:0@192r into %vreg10:0@16r --> @16r
		erased:	192r	%vreg11<def> = COPY %vreg10; GR32:%vreg11,%vreg10
		updated: 16B	%vreg11<def> = COPY %R9D; GR32:%vreg11
	Success: %vreg10 -> %vreg11
	Result = %vreg11 [16r,464r:0)  0@16r
224B	%vreg14<def> = COPY %vreg13; GR64:%vreg14,%vreg13
	Considering merging to GR64 with %vreg13 in %vreg14
		RHS = %vreg13 [208r,224r:0)  0@208r
		LHS = %vreg14 [224r,272r:0)  0@224r
		merge %vreg14:0@224r into %vreg13:0@208r --> @208r
		erased:	224r	%vreg14<def> = COPY %vreg13; GR64:%vreg14,%vreg13
		updated: 208B	%vreg14<def> = MOV64ri <ga:@BZ2_bzReadOpen>; GR64:%vreg14
	Success: %vreg13 -> %vreg14
	Result = %vreg14 [208r,272r:0)  0@208r
3952B	%vreg87<def> = COPY %vreg88; GR64:%vreg87,%vreg88
	Considering merging to GR64 with %vreg88 in %vreg87
		RHS = %vreg88 [3936r,3952r:0)  0@3936r
		LHS = %vreg87 [3952r,3968r:0)[3968r,4000r:1)  0@3952r 1@3968r
		merge %vreg87:0@3952r into %vreg88:0@3936r --> @3936r
		erased:	3952r	%vreg87<def> = COPY %vreg88; GR64:%vreg87,%vreg88
		updated: 3936B	%vreg87<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg87
	Success: %vreg88 -> %vreg87
	Result = %vreg87 [3936r,3968r:0)[3968r,4000r:1)  0@3936r 1@3968r
4064B	%vreg78<def> = COPY %vreg79; GR64:%vreg78,%vreg79
	Considering merging to GR64 with %vreg79 in %vreg78
		RHS = %vreg79 [4048r,4064r:0)  0@4048r
		LHS = %vreg78 [4064r,4080r:0)  0@4064r
		merge %vreg78:0@4064r into %vreg79:0@4048r --> @4048r
		erased:	4064r	%vreg78<def> = COPY %vreg79; GR64:%vreg78,%vreg79
		updated: 4048B	%vreg78<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg78
	Success: %vreg79 -> %vreg78
	Result = %vreg78 [4048r,4080r:0)  0@4048r
4176B	%RDI<def> = COPY %vreg155; GR64:%vreg155
	Considering merging %vreg155 with %RDI
	Can only merge into reserved registers.
3728B	%RDI<def> = COPY %vreg107; GR64:%vreg107
	Considering merging %vreg107 with %RDI
	Can only merge into reserved registers.
272B	%RDI<def> = COPY %vreg14; GR64:%vreg14
	Considering merging %vreg14 with %RDI
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
CH [0B,48r:0)  0@0B-phi
CL [0B,48r:0)  0@0B-phi
DH [0B,64r:0)[3280r,3296r:1)  0@0B-phi 1@3280r
DIL [0B,96r:0)[272r,304r:6)[1440r,1456r:5)[1888r,1904r:4)[3248r,3296r:3)[3728r,3744r:2)[4176r,4208r:1)  0@0B-phi 1@4176r 2@3728r 3@3248r 4@1888r 5@1440r 6@272r
DL [0B,64r:0)[3280r,3296r:1)  0@0B-phi 1@3280r
SIL [0B,80r:0)[288r,304r:3)[3264r,3296r:1)[4192r,4208r:2)  0@0B-phi 1@3264r 2@4192r 3@288r
R8B [0B,32r:0)  0@0B-phi
R9B [0B,16r:0)  0@0B-phi
%vreg1 [96r,384r:0)  0@96r
%vreg3 [80r,400r:0)  0@80r
%vreg5 [64r,416r:0)  0@64r
%vreg7 [48r,432r:0)  0@48r
%vreg9 [32r,448r:0)  0@32r
%vreg11 [16r,464r:0)  0@16r
%vreg14 [208r,272r:0)  0@208r
%vreg15 [240r,288r:0)  0@240r
%vreg17 [544r,560r:0)  0@544r
%vreg20 [640r,656r:0)  0@640r
%vreg33 [1488r,1552r:0)  0@1488r
%vreg34 [1408r,1440r:0)  0@1408r
%vreg38 [1936r,2016r:0)  0@1936r
%vreg44 [2368r,2384r:0)  0@2368r
%vreg47 [2464r,2480r:0)  0@2464r
%vreg49 [2720r,2736r:0)  0@2720r
%vreg51 [2688r,2704r:0)  0@2688r
%vreg53 [2656r,2672r:0)  0@2656r
%vreg55 [2624r,2640r:0)  0@2624r
%vreg57 [2592r,2608r:0)  0@2592r
%vreg60 [2560r,2576r:0)  0@2560r
%vreg61 [2544r,2576r:0)  0@2544r
%vreg63 [2512r,2528r:0)  0@2512r
%vreg70 [3328r,3392r:0)  0@3328r
%vreg71 [3216r,3280r:0)  0@3216r
%vreg72 [3200r,3264r:0)  0@3200r
%vreg74 [3152r,3184r:0)[3184r,3248r:1)  0@3152r 1@3184r
%vreg78 [4048r,4080r:0)  0@4048r
%vreg81 [4016r,4032r:0)  0@4016r
%vreg84 [3984r,4000r:0)  0@3984r
%vreg87 [3936r,3968r:0)[3968r,4000r:1)  0@3936r 1@3968r
%vreg91 [3904r,3920r:0)  0@3904r
%vreg93 [3888r,3920r:0)  0@3888r
%vreg94 [3872r,3888r:0)  0@3872r
%vreg98 [3520r,3536r:0)  0@3520r
%vreg99 [3504r,3536r:0)  0@3504r
%vreg103 [3632r,3648r:0)  0@3632r
%vreg104 [3616r,3648r:0)  0@3616r
%vreg107 [3680r,3728r:0)  0@3680r
%vreg111 [3056r,3088r:0)[3088r,3104r:1)  0@3056r 1@3088r
%vreg115 [2992r,3024r:0)[3024r,3040r:1)  0@2992r 1@3024r
%vreg120 [2928r,2960r:0)[2960r,2976r:1)  0@2928r 1@2960r
%vreg122 [2912r,2976r:0)  0@2912r
%vreg126 [2880r,2896r:0)  0@2880r
%vreg128 [2864r,2896r:0)  0@2864r
%vreg130 [2848r,2864r:0)  0@2848r
%vreg132 [2832r,2896r:0)  0@2832r
%vreg133 [2816r,2832r:0)  0@2816r
%vreg136 [2128r,2144r:0)  0@2128r
%vreg139 [2224r,2240r:0)  0@2224r
%vreg142 [1648r,1664r:0)  0@1648r
%vreg145 [1744r,1760r:0)  0@1744r
%vreg148 [1216r,1232r:0)  0@1216r
%vreg151 [1312r,1328r:0)  0@1312r
%vreg153 [4288r,4304r:0)  0@4288r
%vreg155 [4112r,4176r:0)  0@4112r
%vreg156 [4144r,4192r:0)  0@4144r
RegMasks: 304r 1456r 1904r 3296r 3744r 4208r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzReadOpen: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=8, align=8, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=8, align=8, at location [SP+8]
  fi#3: size=4, align=4, at location [SP+8]
  fi#4: size=4, align=4, at location [SP+8]
  fi#5: size=8, align=8, at location [SP+8]
  fi#6: size=4, align=4, at location [SP+8]
  fi#7: size=8, align=8, at location [SP+8]
  fi#8: size=4, align=4, at location [SP+8]
Function Live Ins: %RDI in %vreg0, %RSI in %vreg2, %EDX in %vreg4, %ECX in %vreg6, %R8 in %vreg8, %R9D in %vreg10

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI %RSI %EDX %ECX %R8 %R9D
16B		%vreg11<def> = COPY %R9D; GR32:%vreg11
32B		%vreg9<def> = COPY %R8; GR64:%vreg9
48B		%vreg7<def> = COPY %ECX; GR32:%vreg7
64B		%vreg5<def> = COPY %EDX; GR32:%vreg5
80B		%vreg3<def> = COPY %RSI; GR64:%vreg3
96B		%vreg1<def> = COPY %RDI; GR64:%vreg1
208B		%vreg14<def> = MOV64ri <ga:@BZ2_bzReadOpen>; GR64:%vreg14
240B		%vreg15<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg15
256B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
272B		%RDI<def> = COPY %vreg14; GR64:%vreg14
288B		%RSI<def> = COPY %vreg15; GR64:%vreg15
304B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
320B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
336B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
352B		STACKMAP 0, 0, %vreg1, 0, <fi#1>, 0, 0, <fi#7>, 0, %vreg3, 0, <fi#2>, 0, %vreg11, 0, <fi#6>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, %vreg7, 0, <fi#4>, 0, %vreg9, 0, <fi#5>, 0, %vreg5, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack8](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5] LD8[FixedStack3](align=4) GR64:%vreg1,%vreg3,%vreg9 GR32:%vreg11,%vreg7,%vreg5
368B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
384B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%bzerror.addr] GR64:%vreg1
400B		MOV64mr <fi#2>, 1, %noreg, 0, %noreg, %vreg3; mem:ST8[%f.addr] GR64:%vreg3
416B		MOV32mr <fi#3>, 1, %noreg, 0, %noreg, %vreg5; mem:ST4[%verbosity.addr] GR32:%vreg5
432B		MOV32mr <fi#4>, 1, %noreg, 0, %noreg, %vreg7; mem:ST4[%small.addr] GR32:%vreg7
448B		MOV64mr <fi#5>, 1, %noreg, 0, %noreg, %vreg9; mem:ST8[%unused.addr] GR64:%vreg9
464B		MOV32mr <fi#6>, 1, %noreg, 0, %noreg, %vreg11; mem:ST4[%nUnused.addr] GR32:%vreg11
480B		MOV64mi32 <fi#7>, 1, %noreg, 0, %noreg, 0; mem:ST8[%bzf]
496B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
512B		JE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

528B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
544B		%vreg17<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg17
560B		MOV32mi %vreg17, 1, %noreg, 0, %noreg, 0; mem:ST4[%1] GR64:%vreg17
	    Successors according to CFG: BB#2

576B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#1
592B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
608B		JE_1 <BB#4>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#4 BB#3

624B	BB#3: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#2
640B		%vreg20<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg20
656B		MOV32mi %vreg20, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr] GR64:%vreg20
	    Successors according to CFG: BB#4

672B	BB#4: derived from LLVM BB %if.end.3
	    Predecessors according to CFG: BB#2 BB#3
688B		CMP64mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%f.addr]
704B		JE_1 <BB#14>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#14 BB#5

720B	BB#5: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#4
736B		CMP32mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%small.addr]
752B		JE_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#6

768B	BB#6: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#5
784B		CMP32mi8 <fi#4>, 1, %noreg, 0, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%small.addr]
800B		JNE_1 <BB#14>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#14 BB#7

816B	BB#7: derived from LLVM BB %lor.lhs.false.7
	    Predecessors according to CFG: BB#5 BB#6
832B		CMP32mi8 <fi#3>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%verbosity.addr]
848B		JL_1 <BB#14>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#14 BB#8

864B	BB#8: derived from LLVM BB %lor.lhs.false.9
	    Predecessors according to CFG: BB#7
880B		CMP32mi8 <fi#3>, 1, %noreg, 0, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%verbosity.addr]
896B		JG_1 <BB#14>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#14 BB#9

912B	BB#9: derived from LLVM BB %lor.lhs.false.11
	    Predecessors according to CFG: BB#8
928B		CMP64mi8 <fi#5>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%unused.addr]
944B		JNE_1 <BB#11>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#11 BB#10

960B	BB#10: derived from LLVM BB %land.lhs.true.13
	    Predecessors according to CFG: BB#9
976B		CMP32mi8 <fi#6>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%nUnused.addr]
992B		JNE_1 <BB#14>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#14 BB#11

1008B	BB#11: derived from LLVM BB %lor.lhs.false.15
	    Predecessors according to CFG: BB#9 BB#10
1024B		CMP64mi8 <fi#5>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%unused.addr]
1040B		JE_1 <BB#19>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#19 BB#12

1056B	BB#12: derived from LLVM BB %land.lhs.true.17
	    Predecessors according to CFG: BB#11
1072B		CMP32mi8 <fi#6>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%nUnused.addr]
1088B		JL_1 <BB#14>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#14 BB#13

1104B	BB#13: derived from LLVM BB %lor.lhs.false.19
	    Predecessors according to CFG: BB#12
1120B		CMP32mi <fi#6>, 1, %noreg, 0, %noreg, 5000, %EFLAGS<imp-def>; mem:LD4[%nUnused.addr]
1136B		JLE_1 <BB#19>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#19 BB#14

1152B	BB#14: derived from LLVM BB %if.then.21
	    Predecessors according to CFG: BB#4 BB#6 BB#7 BB#8 BB#10 BB#12 BB#13
1168B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
1184B		JE_1 <BB#16>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#16 BB#15

1200B	BB#15: derived from LLVM BB %if.then.23
	    Predecessors according to CFG: BB#14
1216B		%vreg148<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg148
1232B		MOV32mi %vreg148, 1, %noreg, 0, %noreg, -2; mem:ST4[%15] GR64:%vreg148
	    Successors according to CFG: BB#16

1248B	BB#16: derived from LLVM BB %if.end.24
	    Predecessors according to CFG: BB#14 BB#15
1264B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
1280B		JE_1 <BB#18>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#18 BB#17

1296B	BB#17: derived from LLVM BB %if.then.26
	    Predecessors according to CFG: BB#16
1312B		%vreg151<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg151
1328B		MOV32mi %vreg151, 1, %noreg, 5096, %noreg, -2; mem:ST4[%lastErr27] GR64:%vreg151
	    Successors according to CFG: BB#18

1344B	BB#18: derived from LLVM BB %if.end.28
	    Predecessors according to CFG: BB#16 BB#17
1360B		MOV64mi32 <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST8[%retval]
1376B		JMP_1 <BB#45>
	    Successors according to CFG: BB#45

1392B	BB#19: derived from LLVM BB %if.end.29
	    Predecessors according to CFG: BB#11 BB#13
1408B		%vreg34<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%f.addr] GR64:%vreg34
1424B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1440B		%RDI<def> = COPY %vreg34; GR64:%vreg34
1456B		CALL64pcrel32 <ga:@ferror>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
1472B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1488B		%vreg33<def> = COPY %EAX<kill>; GR32:%vreg33
1504B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1520B		STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#2>, 0, 0, <fi#6>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack8](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5] LD8[FixedStack3](align=4)
1536B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1552B		CMP32ri8 %vreg33, 0, %EFLAGS<imp-def>; GR32:%vreg33
1568B		JE_1 <BB#25>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#25 BB#20

1584B	BB#20: derived from LLVM BB %if.then.30
	    Predecessors according to CFG: BB#19
1600B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
1616B		JE_1 <BB#22>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#22 BB#21

1632B	BB#21: derived from LLVM BB %if.then.32
	    Predecessors according to CFG: BB#20
1648B		%vreg142<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg142
1664B		MOV32mi %vreg142, 1, %noreg, 0, %noreg, -6; mem:ST4[%20] GR64:%vreg142
	    Successors according to CFG: BB#22

1680B	BB#22: derived from LLVM BB %if.end.33
	    Predecessors according to CFG: BB#20 BB#21
1696B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
1712B		JE_1 <BB#24>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#24 BB#23

1728B	BB#23: derived from LLVM BB %if.then.35
	    Predecessors according to CFG: BB#22
1744B		%vreg145<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg145
1760B		MOV32mi %vreg145, 1, %noreg, 5096, %noreg, -6; mem:ST4[%lastErr36] GR64:%vreg145
	    Successors according to CFG: BB#24

1776B	BB#24: derived from LLVM BB %if.end.37
	    Predecessors according to CFG: BB#22 BB#23
1792B		MOV64mi32 <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST8[%retval]
1808B		JMP_1 <BB#45>
	    Successors according to CFG: BB#45

1824B	BB#25: derived from LLVM BB %if.end.38
	    Predecessors according to CFG: BB#19
1872B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1888B		%EDI<def,dead> = MOV32ri 5104, %RDI<imp-def>
1904B		CALL64pcrel32 <ga:@malloc>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RAX<imp-def>
1920B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1936B		%vreg38<def> = COPY %RAX<kill>; GR64:%vreg38
1952B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1968B		STACKMAP 2, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#2>, 0, 0, <fi#6>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack8](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5] LD8[FixedStack3](align=4)
1984B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2016B		MOV64mr <fi#7>, 1, %noreg, 0, %noreg, %vreg38; mem:ST8[%bzf] GR64:%vreg38
2032B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
2048B		JNE_1 <BB#31>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#31 BB#26

2064B	BB#26: derived from LLVM BB %if.then.41
	    Predecessors according to CFG: BB#25
2080B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
2096B		JE_1 <BB#28>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#28 BB#27

2112B	BB#27: derived from LLVM BB %if.then.43
	    Predecessors according to CFG: BB#26
2128B		%vreg136<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg136
2144B		MOV32mi %vreg136, 1, %noreg, 0, %noreg, -3; mem:ST4[%26] GR64:%vreg136
	    Successors according to CFG: BB#28

2160B	BB#28: derived from LLVM BB %if.end.44
	    Predecessors according to CFG: BB#26 BB#27
2176B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
2192B		JE_1 <BB#30>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#30 BB#29

2208B	BB#29: derived from LLVM BB %if.then.46
	    Predecessors according to CFG: BB#28
2224B		%vreg139<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg139
2240B		MOV32mi %vreg139, 1, %noreg, 5096, %noreg, -3; mem:ST4[%lastErr47] GR64:%vreg139
	    Successors according to CFG: BB#30

2256B	BB#30: derived from LLVM BB %if.end.48
	    Predecessors according to CFG: BB#28 BB#29
2272B		MOV64mi32 <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST8[%retval]
2288B		JMP_1 <BB#45>
	    Successors according to CFG: BB#45

2304B	BB#31: derived from LLVM BB %if.end.49
	    Predecessors according to CFG: BB#25
2320B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
2336B		JE_1 <BB#33>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#33 BB#32

2352B	BB#32: derived from LLVM BB %if.then.51
	    Predecessors according to CFG: BB#31
2368B		%vreg44<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg44
2384B		MOV32mi %vreg44, 1, %noreg, 0, %noreg, 0; mem:ST4[%30] GR64:%vreg44
	    Successors according to CFG: BB#33

2400B	BB#33: derived from LLVM BB %if.end.52
	    Predecessors according to CFG: BB#31 BB#32
2416B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
2432B		JE_1 <BB#35>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#35 BB#34

2448B	BB#34: derived from LLVM BB %if.then.54
	    Predecessors according to CFG: BB#33
2464B		%vreg47<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg47
2480B		MOV32mi %vreg47, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr55] GR64:%vreg47
	    Successors according to CFG: BB#35

2496B	BB#35: derived from LLVM BB %if.end.56
	    Predecessors according to CFG: BB#33 BB#34
2512B		%vreg63<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg63
2528B		MOV8mi %vreg63, 1, %noreg, 5100, %noreg, 0; mem:ST1[%initialisedOk] GR64:%vreg63
2544B		%vreg61<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%f.addr] GR64:%vreg61
2560B		%vreg60<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg60
2576B		MOV64mr %vreg60, 1, %noreg, 0, %noreg, %vreg61; mem:ST8[%handle] GR64:%vreg60,%vreg61
2592B		%vreg57<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg57
2608B		MOV32mi %vreg57, 1, %noreg, 5008, %noreg, 0; mem:ST4[%bufN] GR64:%vreg57
2624B		%vreg55<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg55
2640B		MOV8mi %vreg55, 1, %noreg, 5012, %noreg, 0; mem:ST1[%writing] GR64:%vreg55
2656B		%vreg53<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg53
2672B		MOV64mi32 %vreg53, 1, %noreg, 5072, %noreg, 0; mem:ST8[%bzalloc] GR64:%vreg53
2688B		%vreg51<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg51
2704B		MOV64mi32 %vreg51, 1, %noreg, 5080, %noreg, 0; mem:ST8[%bzfree] GR64:%vreg51
2720B		%vreg49<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg49
2736B		MOV64mi32 %vreg49, 1, %noreg, 5088, %noreg, 0; mem:ST8[%opaque] GR64:%vreg49
	    Successors according to CFG: BB#36

2752B	BB#36: derived from LLVM BB %while.cond
	    Predecessors according to CFG: BB#35 BB#37
2768B		CMP32mi8 <fi#6>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%nUnused.addr]
2784B		JLE_1 <BB#38>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#38 BB#37

2800B	BB#37: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#36
2816B		%vreg133<def> = MOV64rm <fi#5>, 1, %noreg, 0, %noreg; mem:LD8[%unused.addr] GR64:%vreg133
2832B		%vreg132<def> = MOV8rm %vreg133, 1, %noreg, 0, %noreg; mem:LD1[%42] GR8:%vreg132 GR64:%vreg133
2848B		%vreg130<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg130
2864B		%vreg128<def> = MOVSX64rm32 %vreg130, 1, %noreg, 5008, %noreg; mem:LD4[%bufN60] GR64_NOSP:%vreg128 GR64:%vreg130
2880B		%vreg126<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg126
2896B		MOV8mr %vreg126, 1, %vreg128, 8, %noreg, %vreg132; mem:ST1[%arrayidx] GR64:%vreg126 GR64_NOSP:%vreg128 GR8:%vreg132
2912B		%vreg122<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg122
2928B		%vreg120<def> = MOV32rm %vreg122, 1, %noreg, 5008, %noreg; mem:LD4[%bufN61] GR32:%vreg120 GR64:%vreg122
2960B		%vreg120<def,tied1> = ADD32ri8 %vreg120<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg120
2976B		MOV32mr %vreg122, 1, %noreg, 5008, %noreg, %vreg120; mem:ST4[%bufN61] GR64:%vreg122 GR32:%vreg120
2992B		%vreg115<def> = MOV64rm <fi#5>, 1, %noreg, 0, %noreg; mem:LD8[%unused.addr] GR64:%vreg115
3024B		%vreg115<def,tied1> = ADD64ri8 %vreg115<tied0>, 1, %EFLAGS<imp-def,dead>; GR64:%vreg115
3040B		MOV64mr <fi#5>, 1, %noreg, 0, %noreg, %vreg115; mem:ST8[%unused.addr] GR64:%vreg115
3056B		%vreg111<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%nUnused.addr] GR32:%vreg111
3088B		%vreg111<def,tied1> = ADD32ri8 %vreg111<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg111
3104B		MOV32mr <fi#6>, 1, %noreg, 0, %noreg, %vreg111; mem:ST4[%nUnused.addr] GR32:%vreg111
3120B		JMP_1 <BB#36>
	    Successors according to CFG: BB#36

3136B	BB#38: derived from LLVM BB %while.end
	    Predecessors according to CFG: BB#36
3152B		%vreg74<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg74
3184B		%vreg74<def,tied1> = ADD64ri32 %vreg74<tied0>, 5016, %EFLAGS<imp-def,dead>; GR64:%vreg74
3200B		%vreg72<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%verbosity.addr] GR32:%vreg72
3216B		%vreg71<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%small.addr] GR32:%vreg71
3232B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3248B		%RDI<def> = COPY %vreg74; GR64:%vreg74
3264B		%ESI<def> = COPY %vreg72; GR32:%vreg72
3280B		%EDX<def> = COPY %vreg71; GR32:%vreg71
3296B		CALL64pcrel32 <ga:@BZ2_bzDecompressInit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %EDX<imp-use>, %EAX<imp-def>
3312B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3328B		%vreg70<def> = COPY %EAX<kill>; GR32:%vreg70
3344B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3360B		STACKMAP 3, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack8](align=4) LD8[FixedStack0]
3376B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3392B		MOV32mr <fi#8>, 1, %noreg, 0, %noreg, %vreg70; mem:ST4[%ret] GR32:%vreg70
3408B		CMP32mi8 <fi#8>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%ret]
3424B		JE_1 <BB#44>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#44 BB#39

3440B	BB#39: derived from LLVM BB %if.then.65
	    Predecessors according to CFG: BB#38
3456B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
3472B		JE_1 <BB#41>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#41 BB#40

3488B	BB#40: derived from LLVM BB %if.then.67
	    Predecessors according to CFG: BB#39
3504B		%vreg99<def> = MOV32rm <fi#8>, 1, %noreg, 0, %noreg; mem:LD4[%ret] GR32:%vreg99
3520B		%vreg98<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg98
3536B		MOV32mr %vreg98, 1, %noreg, 0, %noreg, %vreg99; mem:ST4[%57] GR64:%vreg98 GR32:%vreg99
	    Successors according to CFG: BB#41

3552B	BB#41: derived from LLVM BB %if.end.68
	    Predecessors according to CFG: BB#39 BB#40
3568B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
3584B		JE_1 <BB#43>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#43 BB#42

3600B	BB#42: derived from LLVM BB %if.then.70
	    Predecessors according to CFG: BB#41
3616B		%vreg104<def> = MOV32rm <fi#8>, 1, %noreg, 0, %noreg; mem:LD4[%ret] GR32:%vreg104
3632B		%vreg103<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg103
3648B		MOV32mr %vreg103, 1, %noreg, 5096, %noreg, %vreg104; mem:ST4[%lastErr71] GR64:%vreg103 GR32:%vreg104
	    Successors according to CFG: BB#43

3664B	BB#43: derived from LLVM BB %if.end.72
	    Predecessors according to CFG: BB#41 BB#42
3680B		%vreg107<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg107
3712B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3728B		%RDI<def> = COPY %vreg107; GR64:%vreg107
3744B		CALL64pcrel32 <ga:@free>, <regmask>, %RSP<imp-use>, %RDI<imp-use>
3760B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3776B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3792B		STACKMAP 4, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0]
3808B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3824B		MOV64mi32 <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST8[%retval]
3840B		JMP_1 <BB#45>
	    Successors according to CFG: BB#45

3856B	BB#44: derived from LLVM BB %if.end.73
	    Predecessors according to CFG: BB#38
3872B		%vreg94<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg94
3888B		%vreg93<def> = MOV32rm %vreg94, 1, %noreg, 5008, %noreg; mem:LD4[%bufN74] GR32:%vreg93 GR64:%vreg94
3904B		%vreg91<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg91
3920B		MOV32mr %vreg91, 1, %noreg, 5024, %noreg, %vreg93; mem:ST4[%avail_in] GR64:%vreg91 GR32:%vreg93
3936B		%vreg87<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg87
3968B		%vreg87<def,tied1> = ADD64ri8 %vreg87<tied0>, 8, %EFLAGS<imp-def,dead>; GR64:%vreg87
3984B		%vreg84<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg84
4000B		MOV64mr %vreg84, 1, %noreg, 5016, %noreg, %vreg87; mem:ST8[%next_in] GR64:%vreg84,%vreg87
4016B		%vreg81<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg81
4032B		MOV8mi %vreg81, 1, %noreg, 5100, %noreg, 1; mem:ST1[%initialisedOk78] GR64:%vreg81
4048B		%vreg78<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg78
4080B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg78; mem:ST8[%retval] GR64:%vreg78
	    Successors according to CFG: BB#45

4096B	BB#45: derived from LLVM BB %return
	    Predecessors according to CFG: BB#44 BB#43 BB#30 BB#24 BB#18
4112B		%vreg155<def> = MOV64ri <ga:@BZ2_bzReadOpen>; GR64:%vreg155
4144B		%vreg156<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg156
4160B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4176B		%RDI<def> = COPY %vreg155; GR64:%vreg155
4192B		%RSI<def> = COPY %vreg156; GR64:%vreg156
4208B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
4224B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4240B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4256B		STACKMAP 5, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0]
4272B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4288B		%vreg153<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%retval] GR64:%vreg153
4304B		%RAX<def> = COPY %vreg153; GR64:%vreg153
4320B		RETQ %RAX<imp-use,kill>

# End machine code for function BZ2_bzReadOpen.

AllocationOrder(SEGMENT_REG) = [ ]
AllocationOrder(SEGMENT_REG) = [ ]
AllocationOrder(SEGMENT_REG) = [ ]
AllocationOrder(SEGMENT_REG) = [ ]
AllocationOrder(SEGMENT_REG) = [ ]
********** GREEDY REGISTER ALLOCATION **********
********** Function: BZ2_bzReadOpen
********** INTERVALS **********
CH [0B,48r:0)  0@0B-phi
CL [0B,48r:0)  0@0B-phi
DH [0B,64r:0)[3280r,3296r:1)  0@0B-phi 1@3280r
DIL [0B,96r:0)[272r,304r:6)[1440r,1456r:5)[1888r,1904r:4)[3248r,3296r:3)[3728r,3744r:2)[4176r,4208r:1)  0@0B-phi 1@4176r 2@3728r 3@3248r 4@1888r 5@1440r 6@272r
DL [0B,64r:0)[3280r,3296r:1)  0@0B-phi 1@3280r
SIL [0B,80r:0)[288r,304r:3)[3264r,3296r:1)[4192r,4208r:2)  0@0B-phi 1@3264r 2@4192r 3@288r
R8B [0B,32r:0)  0@0B-phi
R9B [0B,16r:0)  0@0B-phi
%vreg1 [96r,384r:0)  0@96r
%vreg3 [80r,400r:0)  0@80r
%vreg5 [64r,416r:0)  0@64r
%vreg7 [48r,432r:0)  0@48r
%vreg9 [32r,448r:0)  0@32r
%vreg11 [16r,464r:0)  0@16r
%vreg14 [208r,272r:0)  0@208r
%vreg15 [240r,288r:0)  0@240r
%vreg17 [544r,560r:0)  0@544r
%vreg20 [640r,656r:0)  0@640r
%vreg33 [1488r,1552r:0)  0@1488r
%vreg34 [1408r,1440r:0)  0@1408r
%vreg38 [1936r,2016r:0)  0@1936r
%vreg44 [2368r,2384r:0)  0@2368r
%vreg47 [2464r,2480r:0)  0@2464r
%vreg49 [2720r,2736r:0)  0@2720r
%vreg51 [2688r,2704r:0)  0@2688r
%vreg53 [2656r,2672r:0)  0@2656r
%vreg55 [2624r,2640r:0)  0@2624r
%vreg57 [2592r,2608r:0)  0@2592r
%vreg60 [2560r,2576r:0)  0@2560r
%vreg61 [2544r,2576r:0)  0@2544r
%vreg63 [2512r,2528r:0)  0@2512r
%vreg70 [3328r,3392r:0)  0@3328r
%vreg71 [3216r,3280r:0)  0@3216r
%vreg72 [3200r,3264r:0)  0@3200r
%vreg74 [3152r,3184r:0)[3184r,3248r:1)  0@3152r 1@3184r
%vreg78 [4048r,4080r:0)  0@4048r
%vreg81 [4016r,4032r:0)  0@4016r
%vreg84 [3984r,4000r:0)  0@3984r
%vreg87 [3936r,3968r:0)[3968r,4000r:1)  0@3936r 1@3968r
%vreg91 [3904r,3920r:0)  0@3904r
%vreg93 [3888r,3920r:0)  0@3888r
%vreg94 [3872r,3888r:0)  0@3872r
%vreg98 [3520r,3536r:0)  0@3520r
%vreg99 [3504r,3536r:0)  0@3504r
%vreg103 [3632r,3648r:0)  0@3632r
%vreg104 [3616r,3648r:0)  0@3616r
%vreg107 [3680r,3728r:0)  0@3680r
%vreg111 [3056r,3088r:0)[3088r,3104r:1)  0@3056r 1@3088r
%vreg115 [2992r,3024r:0)[3024r,3040r:1)  0@2992r 1@3024r
%vreg120 [2928r,2960r:0)[2960r,2976r:1)  0@2928r 1@2960r
%vreg122 [2912r,2976r:0)  0@2912r
%vreg126 [2880r,2896r:0)  0@2880r
%vreg128 [2864r,2896r:0)  0@2864r
%vreg130 [2848r,2864r:0)  0@2848r
%vreg132 [2832r,2896r:0)  0@2832r
%vreg133 [2816r,2832r:0)  0@2816r
%vreg136 [2128r,2144r:0)  0@2128r
%vreg139 [2224r,2240r:0)  0@2224r
%vreg142 [1648r,1664r:0)  0@1648r
%vreg145 [1744r,1760r:0)  0@1744r
%vreg148 [1216r,1232r:0)  0@1216r
%vreg151 [1312r,1328r:0)  0@1312r
%vreg153 [4288r,4304r:0)  0@4288r
%vreg155 [4112r,4176r:0)  0@4112r
%vreg156 [4144r,4192r:0)  0@4144r
RegMasks: 304r 1456r 1904r 3296r 3744r 4208r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzReadOpen: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=8, align=8, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=8, align=8, at location [SP+8]
  fi#3: size=4, align=4, at location [SP+8]
  fi#4: size=4, align=4, at location [SP+8]
  fi#5: size=8, align=8, at location [SP+8]
  fi#6: size=4, align=4, at location [SP+8]
  fi#7: size=8, align=8, at location [SP+8]
  fi#8: size=4, align=4, at location [SP+8]
Function Live Ins: %RDI in %vreg0, %RSI in %vreg2, %EDX in %vreg4, %ECX in %vreg6, %R8 in %vreg8, %R9D in %vreg10

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI %RSI %EDX %ECX %R8 %R9D
16B		%vreg11<def> = COPY %R9D; GR32:%vreg11
32B		%vreg9<def> = COPY %R8; GR64:%vreg9
48B		%vreg7<def> = COPY %ECX; GR32:%vreg7
64B		%vreg5<def> = COPY %EDX; GR32:%vreg5
80B		%vreg3<def> = COPY %RSI; GR64:%vreg3
96B		%vreg1<def> = COPY %RDI; GR64:%vreg1
208B		%vreg14<def> = MOV64ri <ga:@BZ2_bzReadOpen>; GR64:%vreg14
240B		%vreg15<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg15
256B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
272B		%RDI<def> = COPY %vreg14; GR64:%vreg14
288B		%RSI<def> = COPY %vreg15; GR64:%vreg15
304B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
320B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
336B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
352B		STACKMAP 0, 0, %vreg1, 0, <fi#1>, 0, 0, <fi#7>, 0, %vreg3, 0, <fi#2>, 0, %vreg11, 0, <fi#6>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, %vreg7, 0, <fi#4>, 0, %vreg9, 0, <fi#5>, 0, %vreg5, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack8](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5] LD8[FixedStack3](align=4) GR64:%vreg1,%vreg3,%vreg9 GR32:%vreg11,%vreg7,%vreg5
368B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
384B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%bzerror.addr] GR64:%vreg1
400B		MOV64mr <fi#2>, 1, %noreg, 0, %noreg, %vreg3; mem:ST8[%f.addr] GR64:%vreg3
416B		MOV32mr <fi#3>, 1, %noreg, 0, %noreg, %vreg5; mem:ST4[%verbosity.addr] GR32:%vreg5
432B		MOV32mr <fi#4>, 1, %noreg, 0, %noreg, %vreg7; mem:ST4[%small.addr] GR32:%vreg7
448B		MOV64mr <fi#5>, 1, %noreg, 0, %noreg, %vreg9; mem:ST8[%unused.addr] GR64:%vreg9
464B		MOV32mr <fi#6>, 1, %noreg, 0, %noreg, %vreg11; mem:ST4[%nUnused.addr] GR32:%vreg11
480B		MOV64mi32 <fi#7>, 1, %noreg, 0, %noreg, 0; mem:ST8[%bzf]
496B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
512B		JE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

528B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
544B		%vreg17<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg17
560B		MOV32mi %vreg17, 1, %noreg, 0, %noreg, 0; mem:ST4[%1] GR64:%vreg17
	    Successors according to CFG: BB#2

576B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#1
592B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
608B		JE_1 <BB#4>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#4 BB#3

624B	BB#3: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#2
640B		%vreg20<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg20
656B		MOV32mi %vreg20, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr] GR64:%vreg20
	    Successors according to CFG: BB#4

672B	BB#4: derived from LLVM BB %if.end.3
	    Predecessors according to CFG: BB#2 BB#3
688B		CMP64mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%f.addr]
704B		JE_1 <BB#14>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#14 BB#5

720B	BB#5: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#4
736B		CMP32mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%small.addr]
752B		JE_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#6

768B	BB#6: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#5
784B		CMP32mi8 <fi#4>, 1, %noreg, 0, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%small.addr]
800B		JNE_1 <BB#14>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#14 BB#7

816B	BB#7: derived from LLVM BB %lor.lhs.false.7
	    Predecessors according to CFG: BB#5 BB#6
832B		CMP32mi8 <fi#3>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%verbosity.addr]
848B		JL_1 <BB#14>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#14 BB#8

864B	BB#8: derived from LLVM BB %lor.lhs.false.9
	    Predecessors according to CFG: BB#7
880B		CMP32mi8 <fi#3>, 1, %noreg, 0, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%verbosity.addr]
896B		JG_1 <BB#14>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#14 BB#9

912B	BB#9: derived from LLVM BB %lor.lhs.false.11
	    Predecessors according to CFG: BB#8
928B		CMP64mi8 <fi#5>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%unused.addr]
944B		JNE_1 <BB#11>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#11 BB#10

960B	BB#10: derived from LLVM BB %land.lhs.true.13
	    Predecessors according to CFG: BB#9
976B		CMP32mi8 <fi#6>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%nUnused.addr]
992B		JNE_1 <BB#14>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#14 BB#11

1008B	BB#11: derived from LLVM BB %lor.lhs.false.15
	    Predecessors according to CFG: BB#9 BB#10
1024B		CMP64mi8 <fi#5>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%unused.addr]
1040B		JE_1 <BB#19>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#19 BB#12

1056B	BB#12: derived from LLVM BB %land.lhs.true.17
	    Predecessors according to CFG: BB#11
1072B		CMP32mi8 <fi#6>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%nUnused.addr]
1088B		JL_1 <BB#14>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#14 BB#13

1104B	BB#13: derived from LLVM BB %lor.lhs.false.19
	    Predecessors according to CFG: BB#12
1120B		CMP32mi <fi#6>, 1, %noreg, 0, %noreg, 5000, %EFLAGS<imp-def>; mem:LD4[%nUnused.addr]
1136B		JLE_1 <BB#19>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#19 BB#14

1152B	BB#14: derived from LLVM BB %if.then.21
	    Predecessors according to CFG: BB#4 BB#6 BB#7 BB#8 BB#10 BB#12 BB#13
1168B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
1184B		JE_1 <BB#16>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#16 BB#15

1200B	BB#15: derived from LLVM BB %if.then.23
	    Predecessors according to CFG: BB#14
1216B		%vreg148<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg148
1232B		MOV32mi %vreg148, 1, %noreg, 0, %noreg, -2; mem:ST4[%15] GR64:%vreg148
	    Successors according to CFG: BB#16

1248B	BB#16: derived from LLVM BB %if.end.24
	    Predecessors according to CFG: BB#14 BB#15
1264B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
1280B		JE_1 <BB#18>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#18 BB#17

1296B	BB#17: derived from LLVM BB %if.then.26
	    Predecessors according to CFG: BB#16
1312B		%vreg151<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg151
1328B		MOV32mi %vreg151, 1, %noreg, 5096, %noreg, -2; mem:ST4[%lastErr27] GR64:%vreg151
	    Successors according to CFG: BB#18

1344B	BB#18: derived from LLVM BB %if.end.28
	    Predecessors according to CFG: BB#16 BB#17
1360B		MOV64mi32 <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST8[%retval]
1376B		JMP_1 <BB#45>
	    Successors according to CFG: BB#45

1392B	BB#19: derived from LLVM BB %if.end.29
	    Predecessors according to CFG: BB#11 BB#13
1408B		%vreg34<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%f.addr] GR64:%vreg34
1424B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1440B		%RDI<def> = COPY %vreg34; GR64:%vreg34
1456B		CALL64pcrel32 <ga:@ferror>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
1472B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1488B		%vreg33<def> = COPY %EAX<kill>; GR32:%vreg33
1504B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1520B		STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#2>, 0, 0, <fi#6>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack8](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5] LD8[FixedStack3](align=4)
1536B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1552B		CMP32ri8 %vreg33, 0, %EFLAGS<imp-def>; GR32:%vreg33
1568B		JE_1 <BB#25>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#25 BB#20

1584B	BB#20: derived from LLVM BB %if.then.30
	    Predecessors according to CFG: BB#19
1600B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
1616B		JE_1 <BB#22>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#22 BB#21

1632B	BB#21: derived from LLVM BB %if.then.32
	    Predecessors according to CFG: BB#20
1648B		%vreg142<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg142
1664B		MOV32mi %vreg142, 1, %noreg, 0, %noreg, -6; mem:ST4[%20] GR64:%vreg142
	    Successors according to CFG: BB#22

1680B	BB#22: derived from LLVM BB %if.end.33
	    Predecessors according to CFG: BB#20 BB#21
1696B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
1712B		JE_1 <BB#24>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#24 BB#23

1728B	BB#23: derived from LLVM BB %if.then.35
	    Predecessors according to CFG: BB#22
1744B		%vreg145<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg145
1760B		MOV32mi %vreg145, 1, %noreg, 5096, %noreg, -6; mem:ST4[%lastErr36] GR64:%vreg145
	    Successors according to CFG: BB#24

1776B	BB#24: derived from LLVM BB %if.end.37
	    Predecessors according to CFG: BB#22 BB#23
1792B		MOV64mi32 <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST8[%retval]
1808B		JMP_1 <BB#45>
	    Successors according to CFG: BB#45

1824B	BB#25: derived from LLVM BB %if.end.38
	    Predecessors according to CFG: BB#19
1872B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1888B		%EDI<def,dead> = MOV32ri 5104, %RDI<imp-def>
1904B		CALL64pcrel32 <ga:@malloc>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RAX<imp-def>
1920B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1936B		%vreg38<def> = COPY %RAX<kill>; GR64:%vreg38
1952B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1968B		STACKMAP 2, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#2>, 0, 0, <fi#6>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack8](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5] LD8[FixedStack3](align=4)
1984B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2016B		MOV64mr <fi#7>, 1, %noreg, 0, %noreg, %vreg38; mem:ST8[%bzf] GR64:%vreg38
2032B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
2048B		JNE_1 <BB#31>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#31 BB#26

2064B	BB#26: derived from LLVM BB %if.then.41
	    Predecessors according to CFG: BB#25
2080B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
2096B		JE_1 <BB#28>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#28 BB#27

2112B	BB#27: derived from LLVM BB %if.then.43
	    Predecessors according to CFG: BB#26
2128B		%vreg136<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg136
2144B		MOV32mi %vreg136, 1, %noreg, 0, %noreg, -3; mem:ST4[%26] GR64:%vreg136
	    Successors according to CFG: BB#28

2160B	BB#28: derived from LLVM BB %if.end.44
	    Predecessors according to CFG: BB#26 BB#27
2176B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
2192B		JE_1 <BB#30>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#30 BB#29

2208B	BB#29: derived from LLVM BB %if.then.46
	    Predecessors according to CFG: BB#28
2224B		%vreg139<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg139
2240B		MOV32mi %vreg139, 1, %noreg, 5096, %noreg, -3; mem:ST4[%lastErr47] GR64:%vreg139
	    Successors according to CFG: BB#30

2256B	BB#30: derived from LLVM BB %if.end.48
	    Predecessors according to CFG: BB#28 BB#29
2272B		MOV64mi32 <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST8[%retval]
2288B		JMP_1 <BB#45>
	    Successors according to CFG: BB#45

2304B	BB#31: derived from LLVM BB %if.end.49
	    Predecessors according to CFG: BB#25
2320B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
2336B		JE_1 <BB#33>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#33 BB#32

2352B	BB#32: derived from LLVM BB %if.then.51
	    Predecessors according to CFG: BB#31
2368B		%vreg44<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg44
2384B		MOV32mi %vreg44, 1, %noreg, 0, %noreg, 0; mem:ST4[%30] GR64:%vreg44
	    Successors according to CFG: BB#33

2400B	BB#33: derived from LLVM BB %if.end.52
	    Predecessors according to CFG: BB#31 BB#32
2416B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
2432B		JE_1 <BB#35>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#35 BB#34

2448B	BB#34: derived from LLVM BB %if.then.54
	    Predecessors according to CFG: BB#33
2464B		%vreg47<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg47
2480B		MOV32mi %vreg47, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr55] GR64:%vreg47
	    Successors according to CFG: BB#35

2496B	BB#35: derived from LLVM BB %if.end.56
	    Predecessors according to CFG: BB#33 BB#34
2512B		%vreg63<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg63
2528B		MOV8mi %vreg63, 1, %noreg, 5100, %noreg, 0; mem:ST1[%initialisedOk] GR64:%vreg63
2544B		%vreg61<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%f.addr] GR64:%vreg61
2560B		%vreg60<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg60
2576B		MOV64mr %vreg60, 1, %noreg, 0, %noreg, %vreg61; mem:ST8[%handle] GR64:%vreg60,%vreg61
2592B		%vreg57<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg57
2608B		MOV32mi %vreg57, 1, %noreg, 5008, %noreg, 0; mem:ST4[%bufN] GR64:%vreg57
2624B		%vreg55<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg55
2640B		MOV8mi %vreg55, 1, %noreg, 5012, %noreg, 0; mem:ST1[%writing] GR64:%vreg55
2656B		%vreg53<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg53
2672B		MOV64mi32 %vreg53, 1, %noreg, 5072, %noreg, 0; mem:ST8[%bzalloc] GR64:%vreg53
2688B		%vreg51<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg51
2704B		MOV64mi32 %vreg51, 1, %noreg, 5080, %noreg, 0; mem:ST8[%bzfree] GR64:%vreg51
2720B		%vreg49<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg49
2736B		MOV64mi32 %vreg49, 1, %noreg, 5088, %noreg, 0; mem:ST8[%opaque] GR64:%vreg49
	    Successors according to CFG: BB#36

2752B	BB#36: derived from LLVM BB %while.cond
	    Predecessors according to CFG: BB#35 BB#37
2768B		CMP32mi8 <fi#6>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%nUnused.addr]
2784B		JLE_1 <BB#38>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#38 BB#37

2800B	BB#37: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#36
2816B		%vreg133<def> = MOV64rm <fi#5>, 1, %noreg, 0, %noreg; mem:LD8[%unused.addr] GR64:%vreg133
2832B		%vreg132<def> = MOV8rm %vreg133, 1, %noreg, 0, %noreg; mem:LD1[%42] GR8:%vreg132 GR64:%vreg133
2848B		%vreg130<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg130
2864B		%vreg128<def> = MOVSX64rm32 %vreg130, 1, %noreg, 5008, %noreg; mem:LD4[%bufN60] GR64_NOSP:%vreg128 GR64:%vreg130
2880B		%vreg126<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg126
2896B		MOV8mr %vreg126, 1, %vreg128, 8, %noreg, %vreg132; mem:ST1[%arrayidx] GR64:%vreg126 GR64_NOSP:%vreg128 GR8:%vreg132
2912B		%vreg122<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg122
2928B		%vreg120<def> = MOV32rm %vreg122, 1, %noreg, 5008, %noreg; mem:LD4[%bufN61] GR32:%vreg120 GR64:%vreg122
2960B		%vreg120<def,tied1> = ADD32ri8 %vreg120<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg120
2976B		MOV32mr %vreg122, 1, %noreg, 5008, %noreg, %vreg120; mem:ST4[%bufN61] GR64:%vreg122 GR32:%vreg120
2992B		%vreg115<def> = MOV64rm <fi#5>, 1, %noreg, 0, %noreg; mem:LD8[%unused.addr] GR64:%vreg115
3024B		%vreg115<def,tied1> = ADD64ri8 %vreg115<tied0>, 1, %EFLAGS<imp-def,dead>; GR64:%vreg115
3040B		MOV64mr <fi#5>, 1, %noreg, 0, %noreg, %vreg115; mem:ST8[%unused.addr] GR64:%vreg115
3056B		%vreg111<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%nUnused.addr] GR32:%vreg111
3088B		%vreg111<def,tied1> = ADD32ri8 %vreg111<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg111
3104B		MOV32mr <fi#6>, 1, %noreg, 0, %noreg, %vreg111; mem:ST4[%nUnused.addr] GR32:%vreg111
3120B		JMP_1 <BB#36>
	    Successors according to CFG: BB#36

3136B	BB#38: derived from LLVM BB %while.end
	    Predecessors according to CFG: BB#36
3152B		%vreg74<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg74
3184B		%vreg74<def,tied1> = ADD64ri32 %vreg74<tied0>, 5016, %EFLAGS<imp-def,dead>; GR64:%vreg74
3200B		%vreg72<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%verbosity.addr] GR32:%vreg72
3216B		%vreg71<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%small.addr] GR32:%vreg71
3232B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3248B		%RDI<def> = COPY %vreg74; GR64:%vreg74
3264B		%ESI<def> = COPY %vreg72; GR32:%vreg72
3280B		%EDX<def> = COPY %vreg71; GR32:%vreg71
3296B		CALL64pcrel32 <ga:@BZ2_bzDecompressInit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %EDX<imp-use>, %EAX<imp-def>
3312B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3328B		%vreg70<def> = COPY %EAX<kill>; GR32:%vreg70
3344B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3360B		STACKMAP 3, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack8](align=4) LD8[FixedStack0]
3376B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3392B		MOV32mr <fi#8>, 1, %noreg, 0, %noreg, %vreg70; mem:ST4[%ret] GR32:%vreg70
3408B		CMP32mi8 <fi#8>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%ret]
3424B		JE_1 <BB#44>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#44 BB#39

3440B	BB#39: derived from LLVM BB %if.then.65
	    Predecessors according to CFG: BB#38
3456B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
3472B		JE_1 <BB#41>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#41 BB#40

3488B	BB#40: derived from LLVM BB %if.then.67
	    Predecessors according to CFG: BB#39
3504B		%vreg99<def> = MOV32rm <fi#8>, 1, %noreg, 0, %noreg; mem:LD4[%ret] GR32:%vreg99
3520B		%vreg98<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg98
3536B		MOV32mr %vreg98, 1, %noreg, 0, %noreg, %vreg99; mem:ST4[%57] GR64:%vreg98 GR32:%vreg99
	    Successors according to CFG: BB#41

3552B	BB#41: derived from LLVM BB %if.end.68
	    Predecessors according to CFG: BB#39 BB#40
3568B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
3584B		JE_1 <BB#43>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#43 BB#42

3600B	BB#42: derived from LLVM BB %if.then.70
	    Predecessors according to CFG: BB#41
3616B		%vreg104<def> = MOV32rm <fi#8>, 1, %noreg, 0, %noreg; mem:LD4[%ret] GR32:%vreg104
3632B		%vreg103<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg103
3648B		MOV32mr %vreg103, 1, %noreg, 5096, %noreg, %vreg104; mem:ST4[%lastErr71] GR64:%vreg103 GR32:%vreg104
	    Successors according to CFG: BB#43

3664B	BB#43: derived from LLVM BB %if.end.72
	    Predecessors according to CFG: BB#41 BB#42
3680B		%vreg107<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg107
3712B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3728B		%RDI<def> = COPY %vreg107; GR64:%vreg107
3744B		CALL64pcrel32 <ga:@free>, <regmask>, %RSP<imp-use>, %RDI<imp-use>
3760B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3776B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3792B		STACKMAP 4, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0]
3808B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3824B		MOV64mi32 <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST8[%retval]
3840B		JMP_1 <BB#45>
	    Successors according to CFG: BB#45

3856B	BB#44: derived from LLVM BB %if.end.73
	    Predecessors according to CFG: BB#38
3872B		%vreg94<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg94
3888B		%vreg93<def> = MOV32rm %vreg94, 1, %noreg, 5008, %noreg; mem:LD4[%bufN74] GR32:%vreg93 GR64:%vreg94
3904B		%vreg91<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg91
3920B		MOV32mr %vreg91, 1, %noreg, 5024, %noreg, %vreg93; mem:ST4[%avail_in] GR64:%vreg91 GR32:%vreg93
3936B		%vreg87<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg87
3968B		%vreg87<def,tied1> = ADD64ri8 %vreg87<tied0>, 8, %EFLAGS<imp-def,dead>; GR64:%vreg87
3984B		%vreg84<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg84
4000B		MOV64mr %vreg84, 1, %noreg, 5016, %noreg, %vreg87; mem:ST8[%next_in] GR64:%vreg84,%vreg87
4016B		%vreg81<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg81
4032B		MOV8mi %vreg81, 1, %noreg, 5100, %noreg, 1; mem:ST1[%initialisedOk78] GR64:%vreg81
4048B		%vreg78<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg78
4080B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg78; mem:ST8[%retval] GR64:%vreg78
	    Successors according to CFG: BB#45

4096B	BB#45: derived from LLVM BB %return
	    Predecessors according to CFG: BB#44 BB#43 BB#30 BB#24 BB#18
4112B		%vreg155<def> = MOV64ri <ga:@BZ2_bzReadOpen>; GR64:%vreg155
4144B		%vreg156<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg156
4160B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4176B		%RDI<def> = COPY %vreg155; GR64:%vreg155
4192B		%RSI<def> = COPY %vreg156; GR64:%vreg156
4208B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
4224B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4240B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4256B		STACKMAP 5, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0]
4272B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4288B		%vreg153<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%retval] GR64:%vreg153
4304B		%RAX<def> = COPY %vreg153; GR64:%vreg153
4320B		RETQ %RAX<imp-use,kill>

# End machine code for function BZ2_bzReadOpen.


selectOrSplit GR32:%vreg11 [16r,464r:0)  0@16r w=3.573113e-03
hints: %R9D
missed hint %R9D
assigning %vreg11 to %EBX: BH [16r,464r:0)  0@16r BL [16r,464r:0)  0@16r

selectOrSplit GR64:%vreg9 [32r,448r:0)  0@32r w=3.713235e-03
hints: %R8
missed hint %R8
%R14 is available at cost 1
Only trying the first 10 regs.
should evict: %vreg11 [16r,464r:0)  0@16r w= 3.573113e-03
hints: %R9D
can reassign: %vreg11 [16r,464r:0)  0@16r from %RBX to %R9D
should evict: %vreg11 [16r,464r:0)  0@16r w= 3.573113e-03
hints: %R9D
can reassign: %vreg11 [16r,464r:0)  0@16r from %RBX to %R9D
evicting %RBX interference: Cascade 1
unassigning %vreg11 from %EBX: BH BL
assigning %vreg9 to %RBX: BH [32r,448r:0)  0@32r BL [32r,448r:0)  0@32r
queuing new interval: %vreg11 [16r,464r:0)  0@16r

selectOrSplit GR32:%vreg11 [16r,464r:0)  0@16r w=3.573113e-03
hints: %R9D
missed hint %R9D
%R14D is available at cost 1
Only trying the first 10 regs.
assigning %vreg11 to %R14D: R14B [16r,464r:0)  0@16r

selectOrSplit GR32:%vreg7 [48r,432r:0)  0@48r w=3.864796e-03
hints: %ECX
missed hint %ECX
%R15D is available at cost 1
Only trying the first 10 regs.
should evict: %vreg9 [32r,448r:0)  0@32r w= 3.713235e-03
hints: %R8
can reassign: %vreg9 [32r,448r:0)  0@32r from %EBX to %R8
should evict: %vreg9 [32r,448r:0)  0@32r w= 3.713235e-03
hints: %R8
can reassign: %vreg9 [32r,448r:0)  0@32r from %EBX to %R8
evicting %EBX interference: Cascade 2
unassigning %vreg9 from %RBX: BH BL
assigning %vreg7 to %EBX: BH [48r,432r:0)  0@48r BL [48r,432r:0)  0@48r
queuing new interval: %vreg9 [32r,448r:0)  0@32r

selectOrSplit GR64:%vreg9 [32r,448r:0)  0@32r w=3.713235e-03
hints: %R8
missed hint %R8
%R15 is available at cost 1
Only trying the first 10 regs.
assigning %vreg9 to %R15: R15B [32r,448r:0)  0@32r

selectOrSplit GR32:%vreg5 [64r,416r:0)  0@64r w=4.029255e-03
hints: %EDX
missed hint %EDX
%R12D is available at cost 1
Only trying the first 10 regs.
should evict: %vreg7 [48r,432r:0)  0@48r w= 3.864796e-03
hints: %ECX
can reassign: %vreg7 [48r,432r:0)  0@48r from %EBX to %ECX
should evict: %vreg7 [48r,432r:0)  0@48r w= 3.864796e-03
hints: %ECX
can reassign: %vreg7 [48r,432r:0)  0@48r from %EBX to %ECX
evicting %EBX interference: Cascade 3
unassigning %vreg7 from %EBX: BH BL
assigning %vreg5 to %EBX: BH [64r,416r:0)  0@64r BL [64r,416r:0)  0@64r
queuing new interval: %vreg7 [48r,432r:0)  0@48r

selectOrSplit GR32:%vreg7 [48r,432r:0)  0@48r w=3.864796e-03
hints: %ECX
missed hint %ECX
%R12D is available at cost 1
Only trying the first 10 regs.
assigning %vreg7 to %R12D: R12B [48r,432r:0)  0@48r

selectOrSplit GR64:%vreg3 [80r,400r:0)  0@80r w=4.208333e-03
hints: %RSI
missed hint %RSI
%R13 is available at cost 1
Only trying the first 10 regs.
should evict: %vreg5 [64r,416r:0)  0@64r w= 4.029255e-03
hints: %EDX
can reassign: %vreg5 [64r,416r:0)  0@64r from %RBX to %EDX
should evict: %vreg5 [64r,416r:0)  0@64r w= 4.029255e-03
hints: %EDX
can reassign: %vreg5 [64r,416r:0)  0@64r from %RBX to %EDX
evicting %RBX interference: Cascade 4
unassigning %vreg5 from %EBX: BH BL
assigning %vreg3 to %RBX: BH [80r,400r:0)  0@80r BL [80r,400r:0)  0@80r
queuing new interval: %vreg5 [64r,416r:0)  0@64r

selectOrSplit GR32:%vreg5 [64r,416r:0)  0@64r w=4.029255e-03
hints: %EDX
missed hint %EDX
%R13D is available at cost 1
Only trying the first 10 regs.
assigning %vreg5 to %R13D: R13B [64r,416r:0)  0@64r

selectOrSplit GR64:%vreg1 [96r,384r:0)  0@96r w=4.404070e-03
hints: %RDI
RS_Assign Cascade 0
should evict: %vreg3 [80r,400r:0)  0@80r w= 4.208333e-03
should evict: %vreg3 [80r,400r:0)  0@80r w= 4.208333e-03
should evict: %vreg11 [16r,464r:0)  0@16r w= 3.573113e-03
hints: %R9D
can reassign: %vreg11 [16r,464r:0)  0@16r from %R14 to %R9D
evicting %R14 interference: Cascade 5
unassigning %vreg11 from %R14D: R14B
assigning %vreg1 to %R14: R14B [96r,384r:0)  0@96r
queuing new interval: %vreg11 [16r,464r:0)  0@16r

selectOrSplit GR32:%vreg11 [16r,464r:0)  0@16r w=3.573113e-03
hints: %R9D
RS_Assign Cascade 5
wait for second round
queuing new interval: %vreg11 [16r,464r:0)  0@16r

selectOrSplit GR64:%vreg14 [208r,272r:0)  0@208r w=2.176724e-03
hints: %RDI
assigning %vreg14 to %RDI: DIL [208r,272r:0)  0@208r

selectOrSplit GR64:%vreg15 [240r,288r:0)  0@240r w=4.508928e-03
hints: %RSI
assigning %vreg15 to %RSI: SIL [240r,288r:0)  0@240r

selectOrSplit GR64:%vreg34 [1408r,1440r:0)  0@1408r w=2.039295e-04
hints: %RDI
assigning %vreg34 to %RDI: DIL [1408r,1440r:0)  0@1408r

selectOrSplit GR32:%vreg33 [1488r,1552r:0)  0@1488r w=1.898654e-04
hints: %EAX
assigning %vreg33 to %EAX: AH [1488r,1552r:0)  0@1488r AL [1488r,1552r:0)  0@1488r

selectOrSplit GR64:%vreg38 [1936r,2016r:0)  0@1936r w=9.104567e-05
hints: %RAX
assigning %vreg38 to %RAX: AH [1936r,2016r:0)  0@1936r AL [1936r,2016r:0)  0@1936r

selectOrSplit GR64:%vreg74 [3152r,3184r:0)[3184r,3248r:1)  0@3152r 1@3184r w=8.671016e-05
hints: %RDI
assigning %vreg74 to %RDI: DIL [3152r,3184r:0)[3184r,3248r:1)  0@3152r 1@3184r

selectOrSplit GR32:%vreg72 [3200r,3264r:0)  0@3200r w=4.634509e-05
hints: %ESI
assigning %vreg72 to %ESI: SIL [3200r,3264r:0)  0@3200r

selectOrSplit GR32:%vreg71 [3216r,3280r:0)  0@3216r w=4.634509e-05
hints: %EDX
assigning %vreg71 to %EDX: DH [3216r,3280r:0)  0@3216r DL [3216r,3280r:0)  0@3216r

selectOrSplit GR32:%vreg70 [3328r,3392r:0)  0@3328r w=4.634509e-05
hints: %EAX
assigning %vreg70 to %EAX: AH [3328r,3392r:0)  0@3328r AL [3328r,3392r:0)  0@3328r

selectOrSplit GR64:%vreg107 [3680r,3728r:0)  0@3680r w=2.322594e-05
hints: %RDI
assigning %vreg107 to %RDI: DIL [3680r,3728r:0)  0@3680r

selectOrSplit GR64:%vreg155 [4112r,4176r:0)  0@4112r w=2.176724e-03
hints: %RDI
assigning %vreg155 to %RDI: DIL [4112r,4176r:0)  0@4112r

selectOrSplit GR64:%vreg156 [4144r,4192r:0)  0@4144r w=4.508928e-03
hints: %RSI
assigning %vreg156 to %RSI: SIL [4144r,4192r:0)  0@4144r

selectOrSplit GR64:%vreg153 [4288r,4304r:0)  0@4288r w=inf
hints: %RAX
assigning %vreg153 to %RAX: AH [4288r,4304r:0)  0@4288r AL [4288r,4304r:0)  0@4288r

selectOrSplit GR64:%vreg17 [544r,560r:0)  0@544r w=inf
assigning %vreg17 to %RAX: AH [544r,560r:0)  0@544r AL [544r,560r:0)  0@544r

selectOrSplit GR64:%vreg20 [640r,656r:0)  0@640r w=inf
assigning %vreg20 to %RAX: AH [640r,656r:0)  0@640r AL [640r,656r:0)  0@640r

selectOrSplit GR64:%vreg148 [1216r,1232r:0)  0@1216r w=inf
assigning %vreg148 to %RAX: AH [1216r,1232r:0)  0@1216r AL [1216r,1232r:0)  0@1216r

selectOrSplit GR64:%vreg151 [1312r,1328r:0)  0@1312r w=inf
assigning %vreg151 to %RAX: AH [1312r,1328r:0)  0@1312r AL [1312r,1328r:0)  0@1312r

selectOrSplit GR64:%vreg142 [1648r,1664r:0)  0@1648r w=inf
assigning %vreg142 to %RAX: AH [1648r,1664r:0)  0@1648r AL [1648r,1664r:0)  0@1648r

selectOrSplit GR64:%vreg145 [1744r,1760r:0)  0@1744r w=inf
assigning %vreg145 to %RAX: AH [1744r,1760r:0)  0@1744r AL [1744r,1760r:0)  0@1744r

selectOrSplit GR64:%vreg136 [2128r,2144r:0)  0@2128r w=inf
assigning %vreg136 to %RAX: AH [2128r,2144r:0)  0@2128r AL [2128r,2144r:0)  0@2128r

selectOrSplit GR64:%vreg139 [2224r,2240r:0)  0@2224r w=inf
assigning %vreg139 to %RAX: AH [2224r,2240r:0)  0@2224r AL [2224r,2240r:0)  0@2224r

selectOrSplit GR64:%vreg44 [2368r,2384r:0)  0@2368r w=inf
assigning %vreg44 to %RAX: AH [2368r,2384r:0)  0@2368r AL [2368r,2384r:0)  0@2368r

selectOrSplit GR64:%vreg47 [2464r,2480r:0)  0@2464r w=inf
assigning %vreg47 to %RAX: AH [2464r,2480r:0)  0@2464r AL [2464r,2480r:0)  0@2464r

selectOrSplit GR64:%vreg63 [2512r,2528r:0)  0@2512r w=inf
assigning %vreg63 to %RAX: AH [2512r,2528r:0)  0@2512r AL [2512r,2528r:0)  0@2512r

selectOrSplit GR64:%vreg61 [2544r,2576r:0)  0@2544r w=4.928521e-05
assigning %vreg61 to %RAX: AH [2544r,2576r:0)  0@2544r AL [2544r,2576r:0)  0@2544r

selectOrSplit GR64:%vreg60 [2560r,2576r:0)  0@2560r w=inf
assigning %vreg60 to %RCX: CH [2560r,2576r:0)  0@2560r CL [2560r,2576r:0)  0@2560r

selectOrSplit GR64:%vreg57 [2592r,2608r:0)  0@2592r w=inf
assigning %vreg57 to %RAX: AH [2592r,2608r:0)  0@2592r AL [2592r,2608r:0)  0@2592r

selectOrSplit GR64:%vreg55 [2624r,2640r:0)  0@2624r w=inf
assigning %vreg55 to %RAX: AH [2624r,2640r:0)  0@2624r AL [2624r,2640r:0)  0@2624r

selectOrSplit GR64:%vreg53 [2656r,2672r:0)  0@2656r w=inf
assigning %vreg53 to %RAX: AH [2656r,2672r:0)  0@2656r AL [2656r,2672r:0)  0@2656r

selectOrSplit GR64:%vreg51 [2688r,2704r:0)  0@2688r w=inf
assigning %vreg51 to %RAX: AH [2688r,2704r:0)  0@2688r AL [2688r,2704r:0)  0@2688r

selectOrSplit GR64:%vreg49 [2720r,2736r:0)  0@2720r w=inf
assigning %vreg49 to %RAX: AH [2720r,2736r:0)  0@2720r AL [2720r,2736r:0)  0@2720r

selectOrSplit GR64:%vreg133 [2816r,2832r:0)  0@2816r w=inf
assigning %vreg133 to %RAX: AH [2816r,2832r:0)  0@2816r AL [2816r,2832r:0)  0@2816r

selectOrSplit GR8:%vreg132 [2832r,2896r:0)  0@2832r w=4.588623e-05
assigning %vreg132 to %AL: AL [2832r,2896r:0)  0@2832r

selectOrSplit GR64:%vreg130 [2848r,2864r:0)  0@2848r w=inf
assigning %vreg130 to %RCX: CH [2848r,2864r:0)  0@2848r CL [2848r,2864r:0)  0@2848r

selectOrSplit GR64_NOSP:%vreg128 [2864r,2896r:0)  0@2864r w=4.928521e-05
assigning %vreg128 to %RCX: CH [2864r,2896r:0)  0@2864r CL [2864r,2896r:0)  0@2864r

selectOrSplit GR64:%vreg126 [2880r,2896r:0)  0@2880r w=inf
assigning %vreg126 to %RDX: DH [2880r,2896r:0)  0@2880r DL [2880r,2896r:0)  0@2880r

selectOrSplit GR64:%vreg122 [2912r,2976r:0)  0@2912r w=6.882934e-05
assigning %vreg122 to %RAX: AH [2912r,2976r:0)  0@2912r AL [2912r,2976r:0)  0@2912r

selectOrSplit GR32:%vreg120 [2928r,2960r:0)[2960r,2976r:1)  0@2928r 1@2960r w=inf
assigning %vreg120 to %ECX: CH [2928r,2960r:0)[2960r,2976r:1)  0@2928r 1@2960r CL [2928r,2960r:0)[2960r,2976r:1)  0@2928r 1@2960r

selectOrSplit GR64:%vreg115 [2992r,3024r:0)[3024r,3040r:1)  0@2992r 1@3024r w=inf
assigning %vreg115 to %RAX: AH [2992r,3024r:0)[3024r,3040r:1)  0@2992r 1@3024r AL [2992r,3024r:0)[3024r,3040r:1)  0@2992r 1@3024r

selectOrSplit GR32:%vreg111 [3056r,3088r:0)[3088r,3104r:1)  0@3056r 1@3088r w=inf
assigning %vreg111 to %EAX: AH [3056r,3088r:0)[3088r,3104r:1)  0@3056r 1@3088r AL [3056r,3088r:0)[3088r,3104r:1)  0@3056r 1@3088r

selectOrSplit GR32:%vreg99 [3504r,3536r:0)  0@3504r w=1.112892e-05
assigning %vreg99 to %EAX: AH [3504r,3536r:0)  0@3504r AL [3504r,3536r:0)  0@3504r

selectOrSplit GR64:%vreg98 [3520r,3536r:0)  0@3520r w=inf
assigning %vreg98 to %RCX: CH [3520r,3536r:0)  0@3520r CL [3520r,3536r:0)  0@3520r

selectOrSplit GR32:%vreg104 [3616r,3648r:0)  0@3616r w=1.112892e-05
assigning %vreg104 to %EAX: AH [3616r,3648r:0)  0@3616r AL [3616r,3648r:0)  0@3616r

selectOrSplit GR64:%vreg103 [3632r,3648r:0)  0@3632r w=inf
assigning %vreg103 to %RCX: CH [3632r,3648r:0)  0@3632r CL [3632r,3648r:0)  0@3632r

selectOrSplit GR64:%vreg94 [3872r,3888r:0)  0@3872r w=inf
assigning %vreg94 to %RAX: AH [3872r,3888r:0)  0@3872r AL [3872r,3888r:0)  0@3872r

selectOrSplit GR32:%vreg93 [3888r,3920r:0)  0@3888r w=2.384768e-05
assigning %vreg93 to %EAX: AH [3888r,3920r:0)  0@3888r AL [3888r,3920r:0)  0@3888r

selectOrSplit GR64:%vreg91 [3904r,3920r:0)  0@3904r w=inf
assigning %vreg91 to %RCX: CH [3904r,3920r:0)  0@3904r CL [3904r,3920r:0)  0@3904r

selectOrSplit GR64:%vreg87 [3936r,3968r:0)[3968r,4000r:1)  0@3936r 1@3968r w=4.440603e-05
assigning %vreg87 to %RAX: AH [3936r,3968r:0)[3968r,4000r:1)  0@3936r 1@3968r AL [3936r,3968r:0)[3968r,4000r:1)  0@3936r 1@3968r

selectOrSplit GR64:%vreg84 [3984r,4000r:0)  0@3984r w=inf
assigning %vreg84 to %RCX: CH [3984r,4000r:0)  0@3984r CL [3984r,4000r:0)  0@3984r

selectOrSplit GR64:%vreg81 [4016r,4032r:0)  0@4016r w=inf
assigning %vreg81 to %RAX: AH [4016r,4032r:0)  0@4016r AL [4016r,4032r:0)  0@4016r

selectOrSplit GR64:%vreg78 [4048r,4080r:0)  0@4048r w=inf
assigning %vreg78 to %RAX: AH [4048r,4080r:0)  0@4048r AL [4048r,4080r:0)  0@4048r

selectOrSplit GR32:%vreg11 [16r,464r:0)  0@16r w=3.573113e-03
hints: %R9D
RS_Split Cascade 5
Analyze counted 3 instrs in 1 blocks, through 0 blocks.
tryLocalSplit:  16r 352r 464r
1 regmasks in block: 304r:16r-352r
%R9D 16r-352r i=inf extend
%R9D 352r-464r i=0.000000e+00 w=5.681818e-03 (best) end
%EAX 16r-352r i=inf extend
%EAX 352r-464r i=0.000000e+00 w=5.681818e-03 (best) end
%ECX 16r-352r i=inf extend
%ECX 352r-464r i=0.000000e+00 w=5.681818e-03 (best) end
%EDX 16r-352r i=inf extend
%EDX 352r-464r i=0.000000e+00 w=5.681818e-03 (best) end
%ESI 16r-352r i=inf extend
%ESI 352r-464r i=0.000000e+00 w=5.681818e-03 (best) end
%EDI 16r-352r i=inf extend
%EDI 352r-464r i=0.000000e+00 w=5.681818e-03 (best) end
%R8D 16r-352r i=inf extend
%R8D 352r-464r i=0.000000e+00 w=5.681818e-03 (best) end
%R10D 16r-352r i=inf extend
%R10D 352r-464r i=0.000000e+00 w=5.681818e-03 (best) end
%R11D 16r-352r i=inf extend
%R11D 352r-464r i=inf end
%EBX 16r-352r i=4.208333e-03 w=3.989362e-03 extend
%EBX 352r-464r i=4.208333e-03 w=5.681818e-03 end
%R14D 16r-352r i=4.404070e-03 w=3.989362e-03 extend
%R14D 352r-464r i=4.404070e-03 w=5.681818e-03 end
%R15D 16r-352r i=3.713235e-03 w=3.989362e-03 extend
%R15D 16r-464r i=3.713235e-03 all
%R12D 16r-352r i=3.864796e-03 w=3.989362e-03 extend
%R12D 16r-464r i=3.864796e-03 all
%R13D 16r-352r i=4.029255e-03 w=3.989362e-03 extend
%R13D 352r-464r i=4.029255e-03 w=5.681818e-03 end
Best local split range: 352r-464r, 5.568071e-03, 2 instrs
    enterIntvBefore 352r: valno 0
    leaveIntvAfter 464r: not live
    useIntv [344r;480B): [344r;480B):1
  blit [16r,464r:0): [16r;344r)=0:0 [344r;464r)=1:0
  rewr BB#0	16r:0	%vreg157<def> = COPY %R9D; GR32:%vreg157
  rewr BB#0	464B:1	MOV32mr <fi#6>, 1, %noreg, 0, %noreg, %vreg158; mem:ST4[%nUnused.addr] GR32:%vreg158
  rewr BB#0	352B:1	STACKMAP 0, 0, %vreg1, 0, <fi#1>, 0, 0, <fi#7>, 0, %vreg3, 0, <fi#2>, 0, %vreg158, 0, <fi#6>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, %vreg7, 0, <fi#4>, 0, %vreg9, 0, <fi#5>, 0, %vreg5, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack8](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5] LD8[FixedStack3](align=4) GR64:%vreg1,%vreg3,%vreg9 GR32:%vreg158,%vreg7,%vreg5
  rewr BB#0	344B:0	%vreg158<def> = COPY %vreg157; GR32:%vreg158,%vreg157
Tagging non-progress ranges: %vreg158
queuing new interval: %vreg157 [16r,344r:0)  0@16r
queuing new interval: %vreg158 [344r,464r:0)  0@344r

selectOrSplit GR32:%vreg157 [16r,344r:0)  0@16r w=2.774725e-03
hints: %R9D
RS_Assign Cascade 0
wait for second round
queuing new interval: %vreg157 [16r,344r:0)  0@16r

selectOrSplit GR32:%vreg158 [344r,464r:0)  0@344r w=5.826923e-03
assigning %vreg158 to %EAX: AH [344r,464r:0)  0@344r AL [344r,464r:0)  0@344r

selectOrSplit GR32:%vreg157 [16r,344r:0)  0@16r w=2.774725e-03
hints: %R9D
RS_Split Cascade 0
Analyze counted 2 instrs in 1 blocks, through 0 blocks.
Inline spilling GR32:%vreg157 [16r,344r:0)  0@16r
From original %vreg11
Merged spilled regs: SS#9 [16r,344r:0)  0@x
spillAroundUses %vreg157
	folded:   16r	MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %R9D; mem:ST4[FixedStack9]
Checking redundant spills for 0@344r in %vreg158 [344r,464r:0)  0@344r
Merged to stack int: SS#9 [16r,464r:0)  0@x
	folded:   344r	%vreg158<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[FixedStack9] GR32:%vreg158
Trying to reconcile hints for: %vreg1(%R14)
%vreg1(%R14) is recolorable.

********** STACK TRANSFORMATION METADATA **********
********** Function: BZ2_bzReadOpen
********** REGISTER MAP **********
[%vreg1 -> %R14] GR64
[%vreg3 -> %RBX] GR64
[%vreg5 -> %R13D] GR32
[%vreg7 -> %R12D] GR32
[%vreg9 -> %R15] GR64
[%vreg14 -> %RDI] GR64
[%vreg15 -> %RSI] GR64
[%vreg17 -> %RAX] GR64
[%vreg20 -> %RAX] GR64
[%vreg33 -> %EAX] GR32
[%vreg34 -> %RDI] GR64
[%vreg38 -> %RAX] GR64
[%vreg44 -> %RAX] GR64
[%vreg47 -> %RAX] GR64
[%vreg49 -> %RAX] GR64
[%vreg51 -> %RAX] GR64
[%vreg53 -> %RAX] GR64
[%vreg55 -> %RAX] GR64
[%vreg57 -> %RAX] GR64
[%vreg60 -> %RCX] GR64
[%vreg61 -> %RAX] GR64
[%vreg63 -> %RAX] GR64
[%vreg70 -> %EAX] GR32
[%vreg71 -> %EDX] GR32
[%vreg72 -> %ESI] GR32
[%vreg74 -> %RDI] GR64
[%vreg78 -> %RAX] GR64
[%vreg81 -> %RAX] GR64
[%vreg84 -> %RCX] GR64
[%vreg87 -> %RAX] GR64
[%vreg91 -> %RCX] GR64
[%vreg93 -> %EAX] GR32
[%vreg94 -> %RAX] GR64
[%vreg98 -> %RCX] GR64
[%vreg99 -> %EAX] GR32
[%vreg103 -> %RCX] GR64
[%vreg104 -> %EAX] GR32
[%vreg107 -> %RDI] GR64
[%vreg111 -> %EAX] GR32
[%vreg115 -> %RAX] GR64
[%vreg120 -> %ECX] GR32
[%vreg122 -> %RAX] GR64
[%vreg126 -> %RDX] GR64
[%vreg128 -> %RCX] GR64_NOSP
[%vreg130 -> %RCX] GR64
[%vreg132 -> %AL] GR8
[%vreg133 -> %RAX] GR64
[%vreg136 -> %RAX] GR64
[%vreg139 -> %RAX] GR64
[%vreg142 -> %RAX] GR64
[%vreg145 -> %RAX] GR64
[%vreg148 -> %RAX] GR64
[%vreg151 -> %RAX] GR64
[%vreg153 -> %RAX] GR64
[%vreg155 -> %RDI] GR64
[%vreg156 -> %RSI] GR64
[%vreg158 -> %EAX] GR32
[%vreg11 -> fi#9] GR32
[%vreg157 -> fi#9] GR32


Stackmap 0:
  STACKMAP 0, 0, %vreg1, 0, <fi#1>, 0, 0, <fi#7>, 0, %vreg3, 0, <fi#2>, 0, %vreg158, 0, <fi#6>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, %vreg7, 0, <fi#4>, 0, %vreg9, 0, <fi#5>, 0, %vreg5, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack8](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5] LD8[FixedStack3](align=4) GR64:%vreg1,%vreg3,%vreg9 GR32:%vreg158,%vreg7,%vreg5

i32* %bzerror: in register %R14 (vreg 1)
i32** %bzerror.addr: in stack slot 1 (size: 8)
%struct.bzFile** %bzf: in stack slot 7 (size: 8)
%struct._IO_FILE* %f: in register %RBX (vreg 3)
%struct._IO_FILE** %f.addr: in stack slot 2 (size: 8)
i32 %nUnused: in register %EAX (vreg 158)
i32* %nUnused.addr: in stack slot 6 (size: 4)
i32* %ret: in stack slot 8 (size: 4)
i8** %retval: in stack slot 0 (size: 8)
i32 %small: in register %R12D (vreg 7)
i32* %small.addr: in stack slot 4 (size: 4)
i8* %unused: in register %R15 (vreg 9)
i8** %unused.addr: in stack slot 5 (size: 8)
i32 %verbosity: in register %R13D (vreg 5)
i32* %verbosity.addr: in stack slot 3 (size: 4)

Duplicate operand locations:

i32 %nUnused: in stack slot 9 (size: 4)

Stackmap 1:
  STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#2>, 0, 0, <fi#6>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack8](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5] LD8[FixedStack3](align=4)

i32** %bzerror.addr: in stack slot 1 (size: 8)
%struct.bzFile** %bzf: in stack slot 7 (size: 8)
%struct._IO_FILE** %f.addr: in stack slot 2 (size: 8)
i32* %nUnused.addr: in stack slot 6 (size: 4)
i32* %ret: in stack slot 8 (size: 4)
i8** %retval: in stack slot 0 (size: 8)
i32* %small.addr: in stack slot 4 (size: 4)
i8** %unused.addr: in stack slot 5 (size: 8)
i32* %verbosity.addr: in stack slot 3 (size: 4)

Duplicate operand locations:


Stackmap 2:
  STACKMAP 2, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#2>, 0, 0, <fi#6>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack8](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5] LD8[FixedStack3](align=4)

i32** %bzerror.addr: in stack slot 1 (size: 8)
%struct.bzFile** %bzf: in stack slot 7 (size: 8)
%struct._IO_FILE** %f.addr: in stack slot 2 (size: 8)
i32* %nUnused.addr: in stack slot 6 (size: 4)
i32* %ret: in stack slot 8 (size: 4)
i8** %retval: in stack slot 0 (size: 8)
i32* %small.addr: in stack slot 4 (size: 4)
i8** %unused.addr: in stack slot 5 (size: 8)
i32* %verbosity.addr: in stack slot 3 (size: 4)

Duplicate operand locations:


Stackmap 3:
  STACKMAP 3, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack8](align=4) LD8[FixedStack0]

i32** %bzerror.addr: in stack slot 1 (size: 8)
%struct.bzFile** %bzf: in stack slot 7 (size: 8)
i32* %ret: in stack slot 8 (size: 4)
i8** %retval: in stack slot 0 (size: 8)

Duplicate operand locations:


Stackmap 4:
  STACKMAP 4, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0]

i8** %retval: in stack slot 0 (size: 8)

Duplicate operand locations:


Stackmap 5:
  STACKMAP 5, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0]

i8** %retval: in stack slot 0 (size: 8)

Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, %vreg1, 0, <fi#1>, 0, 0, <fi#7>, 0, %vreg3, 0, <fi#2>, 0, %vreg158, 0, <fi#6>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, %vreg7, 0, <fi#4>, 0, %vreg9, 0, <fi#5>, 0, %vreg5, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack8](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5] LD8[FixedStack3](align=4) GR64:%vreg1,%vreg3,%vreg9 GR32:%vreg158,%vreg7,%vreg5
  -> Call instruction SlotIndex 304B, searching vregs 0 -> 159 and stack slots -1 -> 10

  STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#2>, 0, 0, <fi#6>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack8](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5] LD8[FixedStack3](align=4)
  -> Call instruction SlotIndex 1456B, searching vregs 0 -> 159 and stack slots -1 -> 10

  STACKMAP 2, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#2>, 0, 0, <fi#6>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack8](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5] LD8[FixedStack3](align=4)
  -> Call instruction SlotIndex 1904B, searching vregs 0 -> 159 and stack slots -1 -> 10

  STACKMAP 3, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack8](align=4) LD8[FixedStack0]
  -> Call instruction SlotIndex 3296B, searching vregs 0 -> 159 and stack slots -1 -> 10

  STACKMAP 4, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0]
  -> Call instruction SlotIndex 3744B, searching vregs 0 -> 159 and stack slots -1 -> 10

  STACKMAP 5, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0]
  -> Call instruction SlotIndex 4208B, searching vregs 0 -> 159 and stack slots -1 -> 10

********** REWRITE VIRTUAL REGISTERS **********
********** Function: BZ2_bzReadOpen
********** REGISTER MAP **********
[%vreg1 -> %R14] GR64
[%vreg3 -> %RBX] GR64
[%vreg5 -> %R13D] GR32
[%vreg7 -> %R12D] GR32
[%vreg9 -> %R15] GR64
[%vreg14 -> %RDI] GR64
[%vreg15 -> %RSI] GR64
[%vreg17 -> %RAX] GR64
[%vreg20 -> %RAX] GR64
[%vreg33 -> %EAX] GR32
[%vreg34 -> %RDI] GR64
[%vreg38 -> %RAX] GR64
[%vreg44 -> %RAX] GR64
[%vreg47 -> %RAX] GR64
[%vreg49 -> %RAX] GR64
[%vreg51 -> %RAX] GR64
[%vreg53 -> %RAX] GR64
[%vreg55 -> %RAX] GR64
[%vreg57 -> %RAX] GR64
[%vreg60 -> %RCX] GR64
[%vreg61 -> %RAX] GR64
[%vreg63 -> %RAX] GR64
[%vreg70 -> %EAX] GR32
[%vreg71 -> %EDX] GR32
[%vreg72 -> %ESI] GR32
[%vreg74 -> %RDI] GR64
[%vreg78 -> %RAX] GR64
[%vreg81 -> %RAX] GR64
[%vreg84 -> %RCX] GR64
[%vreg87 -> %RAX] GR64
[%vreg91 -> %RCX] GR64
[%vreg93 -> %EAX] GR32
[%vreg94 -> %RAX] GR64
[%vreg98 -> %RCX] GR64
[%vreg99 -> %EAX] GR32
[%vreg103 -> %RCX] GR64
[%vreg104 -> %EAX] GR32
[%vreg107 -> %RDI] GR64
[%vreg111 -> %EAX] GR32
[%vreg115 -> %RAX] GR64
[%vreg120 -> %ECX] GR32
[%vreg122 -> %RAX] GR64
[%vreg126 -> %RDX] GR64
[%vreg128 -> %RCX] GR64_NOSP
[%vreg130 -> %RCX] GR64
[%vreg132 -> %AL] GR8
[%vreg133 -> %RAX] GR64
[%vreg136 -> %RAX] GR64
[%vreg139 -> %RAX] GR64
[%vreg142 -> %RAX] GR64
[%vreg145 -> %RAX] GR64
[%vreg148 -> %RAX] GR64
[%vreg151 -> %RAX] GR64
[%vreg153 -> %RAX] GR64
[%vreg155 -> %RDI] GR64
[%vreg156 -> %RSI] GR64
[%vreg158 -> %EAX] GR32
[%vreg11 -> fi#9] GR32
[%vreg157 -> fi#9] GR32

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %ECX %EDX %RDI %RSI %R8 %R9D
16B		MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %R9D; mem:ST4[FixedStack9]
32B		%vreg9<def> = COPY %R8; GR64:%vreg9
48B		%vreg7<def> = COPY %ECX; GR32:%vreg7
64B		%vreg5<def> = COPY %EDX; GR32:%vreg5
80B		%vreg3<def> = COPY %RSI; GR64:%vreg3
96B		%vreg1<def> = COPY %RDI; GR64:%vreg1
208B		%vreg14<def> = MOV64ri <ga:@BZ2_bzReadOpen>; GR64:%vreg14
240B		%vreg15<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg15
256B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
272B		%RDI<def> = COPY %vreg14<kill>; GR64:%vreg14
288B		%RSI<def> = COPY %vreg15<kill>; GR64:%vreg15
304B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
320B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
336B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
344B		%vreg158<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[FixedStack9] GR32:%vreg158
352B		STACKMAP 0, 0, %vreg1, 0, <fi#1>, 0, 0, <fi#7>, 0, %vreg3, 0, <fi#2>, 0, %vreg158, 0, <fi#6>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, %vreg7, 0, <fi#4>, 0, %vreg9, 0, <fi#5>, 0, %vreg5, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack8](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5] LD8[FixedStack3](align=4) GR64:%vreg1,%vreg3,%vreg9 GR32:%vreg158,%vreg7,%vreg5
368B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
384B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg1<kill>; mem:ST8[%bzerror.addr] GR64:%vreg1
400B		MOV64mr <fi#2>, 1, %noreg, 0, %noreg, %vreg3<kill>; mem:ST8[%f.addr] GR64:%vreg3
416B		MOV32mr <fi#3>, 1, %noreg, 0, %noreg, %vreg5<kill>; mem:ST4[%verbosity.addr] GR32:%vreg5
432B		MOV32mr <fi#4>, 1, %noreg, 0, %noreg, %vreg7<kill>; mem:ST4[%small.addr] GR32:%vreg7
448B		MOV64mr <fi#5>, 1, %noreg, 0, %noreg, %vreg9<kill>; mem:ST8[%unused.addr] GR64:%vreg9
464B		MOV32mr <fi#6>, 1, %noreg, 0, %noreg, %vreg158<kill>; mem:ST4[%nUnused.addr] GR32:%vreg158
480B		MOV64mi32 <fi#7>, 1, %noreg, 0, %noreg, 0; mem:ST8[%bzf]
496B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
512B		JE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1
> MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %R9D; mem:ST4[FixedStack9]
> %R15<def> = COPY %R8
> %R12D<def> = COPY %ECX
> %R13D<def> = COPY %EDX
> %RBX<def> = COPY %RSI
> %R14<def> = COPY %RDI
> %RDI<def> = MOV64ri <ga:@BZ2_bzReadOpen>
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[FixedStack9]
> STACKMAP 0, 0, %R14, 0, <fi#1>, 0, 0, <fi#7>, 0, %RBX, 0, <fi#2>, 0, %EAX, 0, <fi#6>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, %R12D, 0, <fi#4>, 0, %R15, 0, <fi#5>, 0, %R13D, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack8](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5] LD8[FixedStack3](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %R14<kill>; mem:ST8[%bzerror.addr]
> MOV64mr <fi#2>, 1, %noreg, 0, %noreg, %RBX<kill>; mem:ST8[%f.addr]
> MOV32mr <fi#3>, 1, %noreg, 0, %noreg, %R13D<kill>; mem:ST4[%verbosity.addr]
> MOV32mr <fi#4>, 1, %noreg, 0, %noreg, %R12D<kill>; mem:ST4[%small.addr]
> MOV64mr <fi#5>, 1, %noreg, 0, %noreg, %R15<kill>; mem:ST8[%unused.addr]
> MOV32mr <fi#6>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%nUnused.addr]
> MOV64mi32 <fi#7>, 1, %noreg, 0, %noreg, 0; mem:ST8[%bzf]
> CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
> JE_1 <BB#2>, %EFLAGS<imp-use,kill>
528B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
544B		%vreg17<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg17
560B		MOV32mi %vreg17<kill>, 1, %noreg, 0, %noreg, 0; mem:ST4[%1] GR64:%vreg17
	    Successors according to CFG: BB#2
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 0, %noreg, 0; mem:ST4[%1]
576B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#1
592B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
608B		JE_1 <BB#4>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#4 BB#3
> CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
> JE_1 <BB#4>, %EFLAGS<imp-use,kill>
624B	BB#3: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#2
640B		%vreg20<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg20
656B		MOV32mi %vreg20<kill>, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr] GR64:%vreg20
	    Successors according to CFG: BB#4
> %RAX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV32mi %RAX<kill>, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr]
672B	BB#4: derived from LLVM BB %if.end.3
	    Predecessors according to CFG: BB#2 BB#3
688B		CMP64mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%f.addr]
704B		JE_1 <BB#14>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#14 BB#5
> CMP64mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%f.addr]
> JE_1 <BB#14>, %EFLAGS<imp-use,kill>
720B	BB#5: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#4
736B		CMP32mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%small.addr]
752B		JE_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#6
> CMP32mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%small.addr]
> JE_1 <BB#7>, %EFLAGS<imp-use,kill>
768B	BB#6: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#5
784B		CMP32mi8 <fi#4>, 1, %noreg, 0, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%small.addr]
800B		JNE_1 <BB#14>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#14 BB#7
> CMP32mi8 <fi#4>, 1, %noreg, 0, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%small.addr]
> JNE_1 <BB#14>, %EFLAGS<imp-use,kill>
816B	BB#7: derived from LLVM BB %lor.lhs.false.7
	    Predecessors according to CFG: BB#5 BB#6
832B		CMP32mi8 <fi#3>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%verbosity.addr]
848B		JL_1 <BB#14>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#14 BB#8
> CMP32mi8 <fi#3>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%verbosity.addr]
> JL_1 <BB#14>, %EFLAGS<imp-use,kill>
864B	BB#8: derived from LLVM BB %lor.lhs.false.9
	    Predecessors according to CFG: BB#7
880B		CMP32mi8 <fi#3>, 1, %noreg, 0, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%verbosity.addr]
896B		JG_1 <BB#14>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#14 BB#9
> CMP32mi8 <fi#3>, 1, %noreg, 0, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%verbosity.addr]
> JG_1 <BB#14>, %EFLAGS<imp-use,kill>
912B	BB#9: derived from LLVM BB %lor.lhs.false.11
	    Predecessors according to CFG: BB#8
928B		CMP64mi8 <fi#5>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%unused.addr]
944B		JNE_1 <BB#11>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#11 BB#10
> CMP64mi8 <fi#5>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%unused.addr]
> JNE_1 <BB#11>, %EFLAGS<imp-use,kill>
960B	BB#10: derived from LLVM BB %land.lhs.true.13
	    Predecessors according to CFG: BB#9
976B		CMP32mi8 <fi#6>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%nUnused.addr]
992B		JNE_1 <BB#14>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#14 BB#11
> CMP32mi8 <fi#6>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%nUnused.addr]
> JNE_1 <BB#14>, %EFLAGS<imp-use,kill>
1008B	BB#11: derived from LLVM BB %lor.lhs.false.15
	    Predecessors according to CFG: BB#9 BB#10
1024B		CMP64mi8 <fi#5>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%unused.addr]
1040B		JE_1 <BB#19>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#19 BB#12
> CMP64mi8 <fi#5>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%unused.addr]
> JE_1 <BB#19>, %EFLAGS<imp-use,kill>
1056B	BB#12: derived from LLVM BB %land.lhs.true.17
	    Predecessors according to CFG: BB#11
1072B		CMP32mi8 <fi#6>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%nUnused.addr]
1088B		JL_1 <BB#14>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#14 BB#13
> CMP32mi8 <fi#6>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%nUnused.addr]
> JL_1 <BB#14>, %EFLAGS<imp-use,kill>
1104B	BB#13: derived from LLVM BB %lor.lhs.false.19
	    Predecessors according to CFG: BB#12
1120B		CMP32mi <fi#6>, 1, %noreg, 0, %noreg, 5000, %EFLAGS<imp-def>; mem:LD4[%nUnused.addr]
1136B		JLE_1 <BB#19>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#19 BB#14
> CMP32mi <fi#6>, 1, %noreg, 0, %noreg, 5000, %EFLAGS<imp-def>; mem:LD4[%nUnused.addr]
> JLE_1 <BB#19>, %EFLAGS<imp-use,kill>
1152B	BB#14: derived from LLVM BB %if.then.21
	    Predecessors according to CFG: BB#4 BB#6 BB#7 BB#8 BB#10 BB#12 BB#13
1168B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
1184B		JE_1 <BB#16>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#16 BB#15
> CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
> JE_1 <BB#16>, %EFLAGS<imp-use,kill>
1200B	BB#15: derived from LLVM BB %if.then.23
	    Predecessors according to CFG: BB#14
1216B		%vreg148<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg148
1232B		MOV32mi %vreg148<kill>, 1, %noreg, 0, %noreg, -2; mem:ST4[%15] GR64:%vreg148
	    Successors according to CFG: BB#16
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 0, %noreg, -2; mem:ST4[%15]
1248B	BB#16: derived from LLVM BB %if.end.24
	    Predecessors according to CFG: BB#14 BB#15
1264B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
1280B		JE_1 <BB#18>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#18 BB#17
> CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
> JE_1 <BB#18>, %EFLAGS<imp-use,kill>
1296B	BB#17: derived from LLVM BB %if.then.26
	    Predecessors according to CFG: BB#16
1312B		%vreg151<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg151
1328B		MOV32mi %vreg151<kill>, 1, %noreg, 5096, %noreg, -2; mem:ST4[%lastErr27] GR64:%vreg151
	    Successors according to CFG: BB#18
> %RAX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV32mi %RAX<kill>, 1, %noreg, 5096, %noreg, -2; mem:ST4[%lastErr27]
1344B	BB#18: derived from LLVM BB %if.end.28
	    Predecessors according to CFG: BB#16 BB#17
1360B		MOV64mi32 <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST8[%retval]
1376B		JMP_1 <BB#45>
	    Successors according to CFG: BB#45
> MOV64mi32 <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST8[%retval]
> JMP_1 <BB#45>
1392B	BB#19: derived from LLVM BB %if.end.29
	    Predecessors according to CFG: BB#11 BB#13
1408B		%vreg34<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%f.addr] GR64:%vreg34
1424B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1440B		%RDI<def> = COPY %vreg34<kill>; GR64:%vreg34
1456B		CALL64pcrel32 <ga:@ferror>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
1472B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1488B		%vreg33<def> = COPY %EAX; GR32:%vreg33
1504B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1520B		STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#2>, 0, 0, <fi#6>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack8](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5] LD8[FixedStack3](align=4)
1536B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1552B		CMP32ri8 %vreg33<kill>, 0, %EFLAGS<imp-def>; GR32:%vreg33
1568B		JE_1 <BB#25>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#25 BB#20
> %RDI<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%f.addr]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@ferror>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def> = COPY %EAX
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#2>, 0, 0, <fi#6>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack8](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5] LD8[FixedStack3](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> CMP32ri8 %EAX<kill>, 0, %EFLAGS<imp-def>
> JE_1 <BB#25>, %EFLAGS<imp-use,kill>
1584B	BB#20: derived from LLVM BB %if.then.30
	    Predecessors according to CFG: BB#19
1600B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
1616B		JE_1 <BB#22>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#22 BB#21
> CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
> JE_1 <BB#22>, %EFLAGS<imp-use,kill>
1632B	BB#21: derived from LLVM BB %if.then.32
	    Predecessors according to CFG: BB#20
1648B		%vreg142<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg142
1664B		MOV32mi %vreg142<kill>, 1, %noreg, 0, %noreg, -6; mem:ST4[%20] GR64:%vreg142
	    Successors according to CFG: BB#22
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 0, %noreg, -6; mem:ST4[%20]
1680B	BB#22: derived from LLVM BB %if.end.33
	    Predecessors according to CFG: BB#20 BB#21
1696B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
1712B		JE_1 <BB#24>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#24 BB#23
> CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
> JE_1 <BB#24>, %EFLAGS<imp-use,kill>
1728B	BB#23: derived from LLVM BB %if.then.35
	    Predecessors according to CFG: BB#22
1744B		%vreg145<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg145
1760B		MOV32mi %vreg145<kill>, 1, %noreg, 5096, %noreg, -6; mem:ST4[%lastErr36] GR64:%vreg145
	    Successors according to CFG: BB#24
> %RAX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV32mi %RAX<kill>, 1, %noreg, 5096, %noreg, -6; mem:ST4[%lastErr36]
1776B	BB#24: derived from LLVM BB %if.end.37
	    Predecessors according to CFG: BB#22 BB#23
1792B		MOV64mi32 <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST8[%retval]
1808B		JMP_1 <BB#45>
	    Successors according to CFG: BB#45
> MOV64mi32 <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST8[%retval]
> JMP_1 <BB#45>
1824B	BB#25: derived from LLVM BB %if.end.38
	    Predecessors according to CFG: BB#19
1872B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1888B		%EDI<def,dead> = MOV32ri 5104, %RDI<imp-def>
1904B		CALL64pcrel32 <ga:@malloc>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RAX<imp-def>
1920B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1936B		%vreg38<def> = COPY %RAX; GR64:%vreg38
1952B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1968B		STACKMAP 2, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#2>, 0, 0, <fi#6>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack8](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5] LD8[FixedStack3](align=4)
1984B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2016B		MOV64mr <fi#7>, 1, %noreg, 0, %noreg, %vreg38<kill>; mem:ST8[%bzf] GR64:%vreg38
2032B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
2048B		JNE_1 <BB#31>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#31 BB#26
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EDI<def,dead> = MOV32ri 5104, %RDI<imp-def>
> CALL64pcrel32 <ga:@malloc>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RAX<def> = COPY %RAX
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 2, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#2>, 0, 0, <fi#6>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#3>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack2] LD8[FixedStack6](align=4) LD8[FixedStack8](align=4) LD8[FixedStack0] LD8[FixedStack4](align=4) LD8[FixedStack5] LD8[FixedStack3](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV64mr <fi#7>, 1, %noreg, 0, %noreg, %RAX<kill>; mem:ST8[%bzf]
> CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
> JNE_1 <BB#31>, %EFLAGS<imp-use,kill>
2064B	BB#26: derived from LLVM BB %if.then.41
	    Predecessors according to CFG: BB#25
2080B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
2096B		JE_1 <BB#28>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#28 BB#27
> CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
> JE_1 <BB#28>, %EFLAGS<imp-use,kill>
2112B	BB#27: derived from LLVM BB %if.then.43
	    Predecessors according to CFG: BB#26
2128B		%vreg136<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg136
2144B		MOV32mi %vreg136<kill>, 1, %noreg, 0, %noreg, -3; mem:ST4[%26] GR64:%vreg136
	    Successors according to CFG: BB#28
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 0, %noreg, -3; mem:ST4[%26]
2160B	BB#28: derived from LLVM BB %if.end.44
	    Predecessors according to CFG: BB#26 BB#27
2176B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
2192B		JE_1 <BB#30>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#30 BB#29
> CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
> JE_1 <BB#30>, %EFLAGS<imp-use,kill>
2208B	BB#29: derived from LLVM BB %if.then.46
	    Predecessors according to CFG: BB#28
2224B		%vreg139<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg139
2240B		MOV32mi %vreg139<kill>, 1, %noreg, 5096, %noreg, -3; mem:ST4[%lastErr47] GR64:%vreg139
	    Successors according to CFG: BB#30
> %RAX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV32mi %RAX<kill>, 1, %noreg, 5096, %noreg, -3; mem:ST4[%lastErr47]
2256B	BB#30: derived from LLVM BB %if.end.48
	    Predecessors according to CFG: BB#28 BB#29
2272B		MOV64mi32 <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST8[%retval]
2288B		JMP_1 <BB#45>
	    Successors according to CFG: BB#45
> MOV64mi32 <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST8[%retval]
> JMP_1 <BB#45>
2304B	BB#31: derived from LLVM BB %if.end.49
	    Predecessors according to CFG: BB#25
2320B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
2336B		JE_1 <BB#33>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#33 BB#32
> CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
> JE_1 <BB#33>, %EFLAGS<imp-use,kill>
2352B	BB#32: derived from LLVM BB %if.then.51
	    Predecessors according to CFG: BB#31
2368B		%vreg44<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg44
2384B		MOV32mi %vreg44<kill>, 1, %noreg, 0, %noreg, 0; mem:ST4[%30] GR64:%vreg44
	    Successors according to CFG: BB#33
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 0, %noreg, 0; mem:ST4[%30]
2400B	BB#33: derived from LLVM BB %if.end.52
	    Predecessors according to CFG: BB#31 BB#32
2416B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
2432B		JE_1 <BB#35>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#35 BB#34
> CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
> JE_1 <BB#35>, %EFLAGS<imp-use,kill>
2448B	BB#34: derived from LLVM BB %if.then.54
	    Predecessors according to CFG: BB#33
2464B		%vreg47<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg47
2480B		MOV32mi %vreg47<kill>, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr55] GR64:%vreg47
	    Successors according to CFG: BB#35
> %RAX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV32mi %RAX<kill>, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr55]
2496B	BB#35: derived from LLVM BB %if.end.56
	    Predecessors according to CFG: BB#33 BB#34
2512B		%vreg63<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg63
2528B		MOV8mi %vreg63<kill>, 1, %noreg, 5100, %noreg, 0; mem:ST1[%initialisedOk] GR64:%vreg63
2544B		%vreg61<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%f.addr] GR64:%vreg61
2560B		%vreg60<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg60
2576B		MOV64mr %vreg60<kill>, 1, %noreg, 0, %noreg, %vreg61<kill>; mem:ST8[%handle] GR64:%vreg60,%vreg61
2592B		%vreg57<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg57
2608B		MOV32mi %vreg57<kill>, 1, %noreg, 5008, %noreg, 0; mem:ST4[%bufN] GR64:%vreg57
2624B		%vreg55<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg55
2640B		MOV8mi %vreg55<kill>, 1, %noreg, 5012, %noreg, 0; mem:ST1[%writing] GR64:%vreg55
2656B		%vreg53<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg53
2672B		MOV64mi32 %vreg53<kill>, 1, %noreg, 5072, %noreg, 0; mem:ST8[%bzalloc] GR64:%vreg53
2688B		%vreg51<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg51
2704B		MOV64mi32 %vreg51<kill>, 1, %noreg, 5080, %noreg, 0; mem:ST8[%bzfree] GR64:%vreg51
2720B		%vreg49<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg49
2736B		MOV64mi32 %vreg49<kill>, 1, %noreg, 5088, %noreg, 0; mem:ST8[%opaque] GR64:%vreg49
	    Successors according to CFG: BB#36
> %RAX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV8mi %RAX<kill>, 1, %noreg, 5100, %noreg, 0; mem:ST1[%initialisedOk]
> %RAX<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%f.addr]
> %RCX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV64mr %RCX<kill>, 1, %noreg, 0, %noreg, %RAX<kill>; mem:ST8[%handle]
> %RAX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV32mi %RAX<kill>, 1, %noreg, 5008, %noreg, 0; mem:ST4[%bufN]
> %RAX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV8mi %RAX<kill>, 1, %noreg, 5012, %noreg, 0; mem:ST1[%writing]
> %RAX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV64mi32 %RAX<kill>, 1, %noreg, 5072, %noreg, 0; mem:ST8[%bzalloc]
> %RAX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV64mi32 %RAX<kill>, 1, %noreg, 5080, %noreg, 0; mem:ST8[%bzfree]
> %RAX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV64mi32 %RAX<kill>, 1, %noreg, 5088, %noreg, 0; mem:ST8[%opaque]
2752B	BB#36: derived from LLVM BB %while.cond
	    Predecessors according to CFG: BB#35 BB#37
2768B		CMP32mi8 <fi#6>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%nUnused.addr]
2784B		JLE_1 <BB#38>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#38 BB#37
> CMP32mi8 <fi#6>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%nUnused.addr]
> JLE_1 <BB#38>, %EFLAGS<imp-use,kill>
2800B	BB#37: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#36
2816B		%vreg133<def> = MOV64rm <fi#5>, 1, %noreg, 0, %noreg; mem:LD8[%unused.addr] GR64:%vreg133
2832B		%vreg132<def> = MOV8rm %vreg133<kill>, 1, %noreg, 0, %noreg; mem:LD1[%42] GR8:%vreg132 GR64:%vreg133
2848B		%vreg130<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg130
2864B		%vreg128<def> = MOVSX64rm32 %vreg130<kill>, 1, %noreg, 5008, %noreg; mem:LD4[%bufN60] GR64_NOSP:%vreg128 GR64:%vreg130
2880B		%vreg126<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg126
2896B		MOV8mr %vreg126<kill>, 1, %vreg128<kill>, 8, %noreg, %vreg132<kill>; mem:ST1[%arrayidx] GR64:%vreg126 GR64_NOSP:%vreg128 GR8:%vreg132
2912B		%vreg122<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg122
2928B		%vreg120<def> = MOV32rm %vreg122, 1, %noreg, 5008, %noreg; mem:LD4[%bufN61] GR32:%vreg120 GR64:%vreg122
2960B		%vreg120<def,tied1> = ADD32ri8 %vreg120<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg120
2976B		MOV32mr %vreg122<kill>, 1, %noreg, 5008, %noreg, %vreg120<kill>; mem:ST4[%bufN61] GR64:%vreg122 GR32:%vreg120
2992B		%vreg115<def> = MOV64rm <fi#5>, 1, %noreg, 0, %noreg; mem:LD8[%unused.addr] GR64:%vreg115
3024B		%vreg115<def,tied1> = ADD64ri8 %vreg115<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR64:%vreg115
3040B		MOV64mr <fi#5>, 1, %noreg, 0, %noreg, %vreg115<kill>; mem:ST8[%unused.addr] GR64:%vreg115
3056B		%vreg111<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%nUnused.addr] GR32:%vreg111
3088B		%vreg111<def,tied1> = ADD32ri8 %vreg111<kill,tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg111
3104B		MOV32mr <fi#6>, 1, %noreg, 0, %noreg, %vreg111<kill>; mem:ST4[%nUnused.addr] GR32:%vreg111
3120B		JMP_1 <BB#36>
	    Successors according to CFG: BB#36
> %RAX<def> = MOV64rm <fi#5>, 1, %noreg, 0, %noreg; mem:LD8[%unused.addr]
> %AL<def> = MOV8rm %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD1[%42]
> %RCX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> %RCX<def> = MOVSX64rm32 %RCX<kill>, 1, %noreg, 5008, %noreg; mem:LD4[%bufN60]
> %RDX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV8mr %RDX<kill>, 1, %RCX<kill>, 8, %noreg, %AL<kill>; mem:ST1[%arrayidx]
> %RAX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 5008, %noreg; mem:LD4[%bufN61]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 5008, %noreg, %ECX<kill>; mem:ST4[%bufN61]
> %RAX<def> = MOV64rm <fi#5>, 1, %noreg, 0, %noreg; mem:LD8[%unused.addr]
> %RAX<def,tied1> = ADD64ri8 %RAX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV64mr <fi#5>, 1, %noreg, 0, %noreg, %RAX<kill>; mem:ST8[%unused.addr]
> %EAX<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%nUnused.addr]
> %EAX<def,tied1> = ADD32ri8 %EAX<kill,tied0>, -1, %EFLAGS<imp-def,dead>
> MOV32mr <fi#6>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%nUnused.addr]
> JMP_1 <BB#36>
3136B	BB#38: derived from LLVM BB %while.end
	    Predecessors according to CFG: BB#36
3152B		%vreg74<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg74
3184B		%vreg74<def,tied1> = ADD64ri32 %vreg74<kill,tied0>, 5016, %EFLAGS<imp-def,dead>; GR64:%vreg74
3200B		%vreg72<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%verbosity.addr] GR32:%vreg72
3216B		%vreg71<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%small.addr] GR32:%vreg71
3232B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3248B		%RDI<def> = COPY %vreg74<kill>; GR64:%vreg74
3264B		%ESI<def> = COPY %vreg72<kill>; GR32:%vreg72
3280B		%EDX<def> = COPY %vreg71<kill>; GR32:%vreg71
3296B		CALL64pcrel32 <ga:@BZ2_bzDecompressInit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %EDX<imp-use>, %EAX<imp-def>
3312B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3328B		%vreg70<def> = COPY %EAX; GR32:%vreg70
3344B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3360B		STACKMAP 3, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack8](align=4) LD8[FixedStack0]
3376B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3392B		MOV32mr <fi#8>, 1, %noreg, 0, %noreg, %vreg70<kill>; mem:ST4[%ret] GR32:%vreg70
3408B		CMP32mi8 <fi#8>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%ret]
3424B		JE_1 <BB#44>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#44 BB#39
> %RDI<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> %RDI<def,tied1> = ADD64ri32 %RDI<kill,tied0>, 5016, %EFLAGS<imp-def,dead>
> %ESI<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%verbosity.addr]
> %EDX<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%small.addr]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %ESI<def> = COPY %ESI<kill>
Deleting identity copy.
> %EDX<def> = COPY %EDX<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@BZ2_bzDecompressInit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %EDX<imp-use>, %EAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def> = COPY %EAX
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 3, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack8](align=4) LD8[FixedStack0]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV32mr <fi#8>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%ret]
> CMP32mi8 <fi#8>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%ret]
> JE_1 <BB#44>, %EFLAGS<imp-use,kill>
3440B	BB#39: derived from LLVM BB %if.then.65
	    Predecessors according to CFG: BB#38
3456B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
3472B		JE_1 <BB#41>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#41 BB#40
> CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
> JE_1 <BB#41>, %EFLAGS<imp-use,kill>
3488B	BB#40: derived from LLVM BB %if.then.67
	    Predecessors according to CFG: BB#39
3504B		%vreg99<def> = MOV32rm <fi#8>, 1, %noreg, 0, %noreg; mem:LD4[%ret] GR32:%vreg99
3520B		%vreg98<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg98
3536B		MOV32mr %vreg98<kill>, 1, %noreg, 0, %noreg, %vreg99<kill>; mem:ST4[%57] GR64:%vreg98 GR32:%vreg99
	    Successors according to CFG: BB#41
> %EAX<def> = MOV32rm <fi#8>, 1, %noreg, 0, %noreg; mem:LD4[%ret]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr]
> MOV32mr %RCX<kill>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%57]
3552B	BB#41: derived from LLVM BB %if.end.68
	    Predecessors according to CFG: BB#39 BB#40
3568B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
3584B		JE_1 <BB#43>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#43 BB#42
> CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
> JE_1 <BB#43>, %EFLAGS<imp-use,kill>
3600B	BB#42: derived from LLVM BB %if.then.70
	    Predecessors according to CFG: BB#41
3616B		%vreg104<def> = MOV32rm <fi#8>, 1, %noreg, 0, %noreg; mem:LD4[%ret] GR32:%vreg104
3632B		%vreg103<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg103
3648B		MOV32mr %vreg103<kill>, 1, %noreg, 5096, %noreg, %vreg104<kill>; mem:ST4[%lastErr71] GR64:%vreg103 GR32:%vreg104
	    Successors according to CFG: BB#43
> %EAX<def> = MOV32rm <fi#8>, 1, %noreg, 0, %noreg; mem:LD4[%ret]
> %RCX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV32mr %RCX<kill>, 1, %noreg, 5096, %noreg, %EAX<kill>; mem:ST4[%lastErr71]
3664B	BB#43: derived from LLVM BB %if.end.72
	    Predecessors according to CFG: BB#41 BB#42
3680B		%vreg107<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg107
3712B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3728B		%RDI<def> = COPY %vreg107<kill>; GR64:%vreg107
3744B		CALL64pcrel32 <ga:@free>, <regmask>, %RSP<imp-use>, %RDI<imp-use>
3760B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3776B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3792B		STACKMAP 4, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0]
3808B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3824B		MOV64mi32 <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST8[%retval]
3840B		JMP_1 <BB#45>
	    Successors according to CFG: BB#45
> %RDI<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@free>, <regmask>, %RSP<imp-use>, %RDI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 4, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV64mi32 <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST8[%retval]
> JMP_1 <BB#45>
3856B	BB#44: derived from LLVM BB %if.end.73
	    Predecessors according to CFG: BB#38
3872B		%vreg94<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg94
3888B		%vreg93<def> = MOV32rm %vreg94<kill>, 1, %noreg, 5008, %noreg; mem:LD4[%bufN74] GR32:%vreg93 GR64:%vreg94
3904B		%vreg91<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg91
3920B		MOV32mr %vreg91<kill>, 1, %noreg, 5024, %noreg, %vreg93<kill>; mem:ST4[%avail_in] GR64:%vreg91 GR32:%vreg93
3936B		%vreg87<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg87
3968B		%vreg87<def,tied1> = ADD64ri8 %vreg87<kill,tied0>, 8, %EFLAGS<imp-def,dead>; GR64:%vreg87
3984B		%vreg84<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg84
4000B		MOV64mr %vreg84<kill>, 1, %noreg, 5016, %noreg, %vreg87<kill>; mem:ST8[%next_in] GR64:%vreg84,%vreg87
4016B		%vreg81<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg81
4032B		MOV8mi %vreg81<kill>, 1, %noreg, 5100, %noreg, 1; mem:ST1[%initialisedOk78] GR64:%vreg81
4048B		%vreg78<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg78
4080B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg78<kill>; mem:ST8[%retval] GR64:%vreg78
	    Successors according to CFG: BB#45
> %RAX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 5008, %noreg; mem:LD4[%bufN74]
> %RCX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV32mr %RCX<kill>, 1, %noreg, 5024, %noreg, %EAX<kill>; mem:ST4[%avail_in]
> %RAX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> %RAX<def,tied1> = ADD64ri8 %RAX<kill,tied0>, 8, %EFLAGS<imp-def,dead>
> %RCX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV64mr %RCX<kill>, 1, %noreg, 5016, %noreg, %RAX<kill>; mem:ST8[%next_in]
> %RAX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV8mi %RAX<kill>, 1, %noreg, 5100, %noreg, 1; mem:ST1[%initialisedOk78]
> %RAX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %RAX<kill>; mem:ST8[%retval]
4096B	BB#45: derived from LLVM BB %return
	    Predecessors according to CFG: BB#44 BB#43 BB#30 BB#24 BB#18
4112B		%vreg155<def> = MOV64ri <ga:@BZ2_bzReadOpen>; GR64:%vreg155
4144B		%vreg156<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg156
4160B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4176B		%RDI<def> = COPY %vreg155<kill>; GR64:%vreg155
4192B		%RSI<def> = COPY %vreg156<kill>; GR64:%vreg156
4208B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
4224B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4240B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4256B		STACKMAP 5, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0]
4272B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4288B		%vreg153<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%retval] GR64:%vreg153
4304B		%RAX<def> = COPY %vreg153<kill>; GR64:%vreg153
4320B		RETQ %RAX<imp-use>
> %RDI<def> = MOV64ri <ga:@BZ2_bzReadOpen>
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 5, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%retval]
> %RAX<def> = COPY %RAX<kill>
Deleting identity copy.
> RETQ %RAX<imp-use>
Computing live-in reg-units in ABI blocks.
0B	BB#0 DIL#0 SIL#0
Created 2 new intervals.
********** INTERVALS **********
DIL [0B,32r:0)[144r,176r:4)[1216r,1232r:3)[1392r,1408r:2)[1568r,1600r:1)  0@0B-phi 1@1568r 2@1392r 3@1216r 4@144r
SIL [0B,16r:0)[160r,176r:2)[1584r,1600r:1)  0@0B-phi 1@1584r 2@160r
%vreg0 [32r,48r:0)  0@32r
%vreg1 [48r,256r:0)  0@48r
%vreg2 [16r,64r:0)  0@16r
%vreg3 [64r,272r:0)  0@64r
%vreg7 [304r,320r:0)  0@304r
%vreg8 [288r,304r:0)  0@288r
%vreg9 [80r,96r:0)  0@80r
%vreg10 [96r,144r:0)  0@96r
%vreg11 [112r,160r:0)  0@112r
%vreg13 [384r,400r:0)  0@384r
%vreg16 [480r,496r:0)  0@480r
%vreg20 [800r,816r:0)  0@800r
%vreg23 [1088r,1104r:0)  0@1088r
%vreg25 [1264r,1264d:0)  0@1264r
%vreg27 [1168r,1184r:0)[1184r,1216r:1)  0@1168r 1@1184r
%vreg28 [1152r,1168r:0)  0@1152r
%vreg31 [1360r,1392r:0)  0@1360r
%vreg32 [1344r,1360r:0)  0@1344r
%vreg35 [912r,928r:0)  0@912r
%vreg38 [1008r,1024r:0)  0@1008r
%vreg41 [624r,640r:0)  0@624r
%vreg44 [720r,736r:0)  0@720r
%vreg45 [1504r,1520r:0)  0@1504r
%vreg46 [1520r,1568r:0)  0@1520r
%vreg47 [1536r,1584r:0)  0@1536r
RegMasks: 176r 1232r 1408r 1600r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzReadClose: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=8, align=8, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=8, align=8, at location [SP+8]
Function Live Ins: %RDI in %vreg0, %RSI in %vreg2

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI %RSI
16B		%vreg2<def> = COPY %RSI; GR64:%vreg2
32B		%vreg0<def> = COPY %RDI; GR64:%vreg0
48B		%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
64B		%vreg3<def> = COPY %vreg2; GR64:%vreg3,%vreg2
80B		%vreg9<def> = MOV64ri <ga:@BZ2_bzReadClose>; GR64:%vreg9
96B		%vreg10<def> = COPY %vreg9; GR64:%vreg10,%vreg9
112B		%vreg11<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg11
128B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
144B		%RDI<def> = COPY %vreg10; GR64:%vreg10
160B		%RSI<def> = COPY %vreg11; GR64:%vreg11
176B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
192B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
208B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#2>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack2] GR64:%vreg3,%vreg1
240B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
256B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%bzerror.addr] GR64:%vreg1
272B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg3; mem:ST8[%b.addr] GR64:%vreg3
288B		%vreg8<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr] GR64:%vreg8
304B		%vreg7<def> = COPY %vreg8; GR64:%vreg7,%vreg8
320B		MOV64mr <fi#2>, 1, %noreg, 0, %noreg, %vreg7; mem:ST8[%bzf] GR64:%vreg7
336B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
352B		JE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

368B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
384B		%vreg13<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg13
400B		MOV32mi %vreg13, 1, %noreg, 0, %noreg, 0; mem:ST4[%3] GR64:%vreg13
	    Successors according to CFG: BB#2

416B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#1
432B		CMP64mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
448B		JE_1 <BB#4>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#4 BB#3

464B	BB#3: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#2
480B		%vreg16<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg16
496B		MOV32mi %vreg16, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr] GR64:%vreg16
	    Successors according to CFG: BB#4

512B	BB#4: derived from LLVM BB %if.end.3
	    Predecessors according to CFG: BB#2 BB#3
528B		CMP64mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
544B		JNE_1 <BB#10>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#10 BB#5

560B	BB#5: derived from LLVM BB %if.then.5
	    Predecessors according to CFG: BB#4
576B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
592B		JE_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#6

608B	BB#6: derived from LLVM BB %if.then.7
	    Predecessors according to CFG: BB#5
624B		%vreg41<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg41
640B		MOV32mi %vreg41, 1, %noreg, 0, %noreg, 0; mem:ST4[%8] GR64:%vreg41
	    Successors according to CFG: BB#7

656B	BB#7: derived from LLVM BB %if.end.8
	    Predecessors according to CFG: BB#5 BB#6
672B		CMP64mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
688B		JE_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#8

704B	BB#8: derived from LLVM BB %if.then.10
	    Predecessors according to CFG: BB#7
720B		%vreg44<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg44
736B		MOV32mi %vreg44, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr11] GR64:%vreg44
	    Successors according to CFG: BB#9

752B	BB#9: derived from LLVM BB %if.end.12
	    Predecessors according to CFG: BB#7 BB#8
768B		JMP_1 <BB#19>
	    Successors according to CFG: BB#19

784B	BB#10: derived from LLVM BB %if.end.13
	    Predecessors according to CFG: BB#4
800B		%vreg20<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg20
816B		CMP8mi %vreg20, 1, %noreg, 5012, %noreg, 0, %EFLAGS<imp-def>; mem:LD1[%writing] GR64:%vreg20
832B		JE_1 <BB#16>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#16 BB#11

848B	BB#11: derived from LLVM BB %if.then.14
	    Predecessors according to CFG: BB#10
864B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
880B		JE_1 <BB#13>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#13 BB#12

896B	BB#12: derived from LLVM BB %if.then.16
	    Predecessors according to CFG: BB#11
912B		%vreg35<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg35
928B		MOV32mi %vreg35, 1, %noreg, 0, %noreg, -1; mem:ST4[%14] GR64:%vreg35
	    Successors according to CFG: BB#13

944B	BB#13: derived from LLVM BB %if.end.17
	    Predecessors according to CFG: BB#11 BB#12
960B		CMP64mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
976B		JE_1 <BB#15>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#15 BB#14

992B	BB#14: derived from LLVM BB %if.then.19
	    Predecessors according to CFG: BB#13
1008B		%vreg38<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg38
1024B		MOV32mi %vreg38, 1, %noreg, 5096, %noreg, -1; mem:ST4[%lastErr20] GR64:%vreg38
	    Successors according to CFG: BB#15

1040B	BB#15: derived from LLVM BB %if.end.21
	    Predecessors according to CFG: BB#13 BB#14
1056B		JMP_1 <BB#19>
	    Successors according to CFG: BB#19

1072B	BB#16: derived from LLVM BB %if.end.22
	    Predecessors according to CFG: BB#10
1088B		%vreg23<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg23
1104B		CMP8mi %vreg23, 1, %noreg, 5100, %noreg, 0, %EFLAGS<imp-def>; mem:LD1[%initialisedOk] GR64:%vreg23
1120B		JE_1 <BB#18>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#18 BB#17

1136B	BB#17: derived from LLVM BB %if.then.24
	    Predecessors according to CFG: BB#16
1152B		%vreg28<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg28
1168B		%vreg27<def> = COPY %vreg28; GR64:%vreg27,%vreg28
1184B		%vreg27<def,tied1> = ADD64ri32 %vreg27<tied0>, 5016, %EFLAGS<imp-def,dead>; GR64:%vreg27
1200B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1216B		%RDI<def> = COPY %vreg27; GR64:%vreg27
1232B		CALL64pcrel32 <ga:@BZ2_bzDecompressEnd>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
1248B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1264B		%vreg25<def,dead> = COPY %EAX<kill>; GR32:%vreg25
1280B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1296B		STACKMAP 1, 0, 0, <fi#2>, 0, ...; mem:LD8[FixedStack2]
1312B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#18

1328B	BB#18: derived from LLVM BB %if.end.25
	    Predecessors according to CFG: BB#16 BB#17
1344B		%vreg32<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg32
1360B		%vreg31<def> = COPY %vreg32; GR64:%vreg31,%vreg32
1376B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1392B		%RDI<def> = COPY %vreg31; GR64:%vreg31
1408B		CALL64pcrel32 <ga:@free>, <regmask>, %RSP<imp-use>, %RDI<imp-use>
1424B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1440B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1456B		STACKMAP 2, 0, ...
1472B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#19

1488B	BB#19: derived from LLVM BB %return
	    Predecessors according to CFG: BB#18 BB#15 BB#9
1504B		%vreg45<def> = MOV64ri <ga:@BZ2_bzReadClose>; GR64:%vreg45
1520B		%vreg46<def> = COPY %vreg45; GR64:%vreg46,%vreg45
1536B		%vreg47<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg47
1552B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1568B		%RDI<def> = COPY %vreg46; GR64:%vreg46
1584B		%RSI<def> = COPY %vreg47; GR64:%vreg47
1600B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
1616B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1632B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1648B		STACKMAP 3, 0, ...
1664B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1680B		RETQ

# End machine code for function BZ2_bzReadClose.

********** SIMPLE REGISTER COALESCING **********
********** Function: BZ2_bzReadClose
********** JOINING INTERVALS ***********
if.end:
if.end.3:
if.end.8:
if.end.17:
if.then.5:
if.end.12:
if.end.13:
if.then.14:
if.end.21:
if.end.22:
if.end.25:
1392B	%RDI<def> = COPY %vreg31; GR64:%vreg31
	Considering merging %vreg31 with %RDI
	Can only merge into reserved registers.
return:
1568B	%RDI<def> = COPY %vreg46; GR64:%vreg46
	Considering merging %vreg46 with %RDI
	Can only merge into reserved registers.
1584B	%RSI<def> = COPY %vreg47; GR64:%vreg47
	Considering merging %vreg47 with %RSI
	Can only merge into reserved registers.
entry:
16B	%vreg2<def> = COPY %RSI; GR64:%vreg2
	Considering merging %vreg2 with %RSI
	Can only merge into reserved registers.
32B	%vreg0<def> = COPY %RDI; GR64:%vreg0
	Considering merging %vreg0 with %RDI
	Can only merge into reserved registers.
144B	%RDI<def> = COPY %vreg10; GR64:%vreg10
	Considering merging %vreg10 with %RDI
	Can only merge into reserved registers.
160B	%RSI<def> = COPY %vreg11; GR64:%vreg11
	Considering merging %vreg11 with %RSI
	Can only merge into reserved registers.
if.then:
if.then.2:
if.then.7:
if.then.10:
if.then.16:
if.then.19:
if.then.24:
1216B	%RDI<def> = COPY %vreg27; GR64:%vreg27
	Considering merging %vreg27 with %RDI
	Can only merge into reserved registers.
1264B	%vreg25<def,dead> = COPY %EAX<kill>; GR32:%vreg25
	Considering merging %vreg25 with %EAX
	Can only merge into reserved registers.
1360B	%vreg31<def> = COPY %vreg32; GR64:%vreg31,%vreg32
	Considering merging to GR64 with %vreg32 in %vreg31
		RHS = %vreg32 [1344r,1360r:0)  0@1344r
		LHS = %vreg31 [1360r,1392r:0)  0@1360r
		merge %vreg31:0@1360r into %vreg32:0@1344r --> @1344r
		erased:	1360r	%vreg31<def> = COPY %vreg32; GR64:%vreg31,%vreg32
		updated: 1344B	%vreg31<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg31
	Success: %vreg32 -> %vreg31
	Result = %vreg31 [1344r,1392r:0)  0@1344r
1520B	%vreg46<def> = COPY %vreg45; GR64:%vreg46,%vreg45
	Considering merging to GR64 with %vreg45 in %vreg46
		RHS = %vreg45 [1504r,1520r:0)  0@1504r
		LHS = %vreg46 [1520r,1568r:0)  0@1520r
		merge %vreg46:0@1520r into %vreg45:0@1504r --> @1504r
		erased:	1520r	%vreg46<def> = COPY %vreg45; GR64:%vreg46,%vreg45
		updated: 1504B	%vreg46<def> = MOV64ri <ga:@BZ2_bzReadClose>; GR64:%vreg46
	Success: %vreg45 -> %vreg46
	Result = %vreg46 [1504r,1568r:0)  0@1504r
48B	%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
	Considering merging to GR64 with %vreg0 in %vreg1
		RHS = %vreg0 [32r,48r:0)  0@32r
		LHS = %vreg1 [48r,256r:0)  0@48r
		merge %vreg1:0@48r into %vreg0:0@32r --> @32r
		erased:	48r	%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
		updated: 32B	%vreg1<def> = COPY %RDI; GR64:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [32r,256r:0)  0@32r
64B	%vreg3<def> = COPY %vreg2; GR64:%vreg3,%vreg2
	Considering merging to GR64 with %vreg2 in %vreg3
		RHS = %vreg2 [16r,64r:0)  0@16r
		LHS = %vreg3 [64r,272r:0)  0@64r
		merge %vreg3:0@64r into %vreg2:0@16r --> @16r
		erased:	64r	%vreg3<def> = COPY %vreg2; GR64:%vreg3,%vreg2
		updated: 16B	%vreg3<def> = COPY %RSI; GR64:%vreg3
	Success: %vreg2 -> %vreg3
	Result = %vreg3 [16r,272r:0)  0@16r
96B	%vreg10<def> = COPY %vreg9; GR64:%vreg10,%vreg9
	Considering merging to GR64 with %vreg9 in %vreg10
		RHS = %vreg9 [80r,96r:0)  0@80r
		LHS = %vreg10 [96r,144r:0)  0@96r
		merge %vreg10:0@96r into %vreg9:0@80r --> @80r
		erased:	96r	%vreg10<def> = COPY %vreg9; GR64:%vreg10,%vreg9
		updated: 80B	%vreg10<def> = MOV64ri <ga:@BZ2_bzReadClose>; GR64:%vreg10
	Success: %vreg9 -> %vreg10
	Result = %vreg10 [80r,144r:0)  0@80r
304B	%vreg7<def> = COPY %vreg8; GR64:%vreg7,%vreg8
	Considering merging to GR64 with %vreg8 in %vreg7
		RHS = %vreg8 [288r,304r:0)  0@288r
		LHS = %vreg7 [304r,320r:0)  0@304r
		merge %vreg7:0@304r into %vreg8:0@288r --> @288r
		erased:	304r	%vreg7<def> = COPY %vreg8; GR64:%vreg7,%vreg8
		updated: 288B	%vreg7<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr] GR64:%vreg7
	Success: %vreg8 -> %vreg7
	Result = %vreg7 [288r,320r:0)  0@288r
1168B	%vreg27<def> = COPY %vreg28; GR64:%vreg27,%vreg28
	Considering merging to GR64 with %vreg28 in %vreg27
		RHS = %vreg28 [1152r,1168r:0)  0@1152r
		LHS = %vreg27 [1168r,1184r:0)[1184r,1216r:1)  0@1168r 1@1184r
		merge %vreg27:0@1168r into %vreg28:0@1152r --> @1152r
		erased:	1168r	%vreg27<def> = COPY %vreg28; GR64:%vreg27,%vreg28
		updated: 1152B	%vreg27<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg27
	Success: %vreg28 -> %vreg27
	Result = %vreg27 [1152r,1184r:0)[1184r,1216r:1)  0@1152r 1@1184r
1392B	%RDI<def> = COPY %vreg31; GR64:%vreg31
	Considering merging %vreg31 with %RDI
	Can only merge into reserved registers.
1568B	%RDI<def> = COPY %vreg46; GR64:%vreg46
	Considering merging %vreg46 with %RDI
	Can only merge into reserved registers.
144B	%RDI<def> = COPY %vreg10; GR64:%vreg10
	Considering merging %vreg10 with %RDI
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
DIL [0B,32r:0)[144r,176r:4)[1216r,1232r:3)[1392r,1408r:2)[1568r,1600r:1)  0@0B-phi 1@1568r 2@1392r 3@1216r 4@144r
SIL [0B,16r:0)[160r,176r:2)[1584r,1600r:1)  0@0B-phi 1@1584r 2@160r
%vreg1 [32r,256r:0)  0@32r
%vreg3 [16r,272r:0)  0@16r
%vreg7 [288r,320r:0)  0@288r
%vreg10 [80r,144r:0)  0@80r
%vreg11 [112r,160r:0)  0@112r
%vreg13 [384r,400r:0)  0@384r
%vreg16 [480r,496r:0)  0@480r
%vreg20 [800r,816r:0)  0@800r
%vreg23 [1088r,1104r:0)  0@1088r
%vreg25 [1264r,1264d:0)  0@1264r
%vreg27 [1152r,1184r:0)[1184r,1216r:1)  0@1152r 1@1184r
%vreg31 [1344r,1392r:0)  0@1344r
%vreg35 [912r,928r:0)  0@912r
%vreg38 [1008r,1024r:0)  0@1008r
%vreg41 [624r,640r:0)  0@624r
%vreg44 [720r,736r:0)  0@720r
%vreg46 [1504r,1568r:0)  0@1504r
%vreg47 [1536r,1584r:0)  0@1536r
RegMasks: 176r 1232r 1408r 1600r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzReadClose: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=8, align=8, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=8, align=8, at location [SP+8]
Function Live Ins: %RDI in %vreg0, %RSI in %vreg2

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI %RSI
16B		%vreg3<def> = COPY %RSI; GR64:%vreg3
32B		%vreg1<def> = COPY %RDI; GR64:%vreg1
80B		%vreg10<def> = MOV64ri <ga:@BZ2_bzReadClose>; GR64:%vreg10
112B		%vreg11<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg11
128B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
144B		%RDI<def> = COPY %vreg10; GR64:%vreg10
160B		%RSI<def> = COPY %vreg11; GR64:%vreg11
176B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
192B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
208B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#2>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack2] GR64:%vreg3,%vreg1
240B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
256B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%bzerror.addr] GR64:%vreg1
272B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg3; mem:ST8[%b.addr] GR64:%vreg3
288B		%vreg7<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr] GR64:%vreg7
320B		MOV64mr <fi#2>, 1, %noreg, 0, %noreg, %vreg7; mem:ST8[%bzf] GR64:%vreg7
336B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
352B		JE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

368B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
384B		%vreg13<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg13
400B		MOV32mi %vreg13, 1, %noreg, 0, %noreg, 0; mem:ST4[%3] GR64:%vreg13
	    Successors according to CFG: BB#2

416B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#1
432B		CMP64mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
448B		JE_1 <BB#4>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#4 BB#3

464B	BB#3: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#2
480B		%vreg16<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg16
496B		MOV32mi %vreg16, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr] GR64:%vreg16
	    Successors according to CFG: BB#4

512B	BB#4: derived from LLVM BB %if.end.3
	    Predecessors according to CFG: BB#2 BB#3
528B		CMP64mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
544B		JNE_1 <BB#10>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#10 BB#5

560B	BB#5: derived from LLVM BB %if.then.5
	    Predecessors according to CFG: BB#4
576B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
592B		JE_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#6

608B	BB#6: derived from LLVM BB %if.then.7
	    Predecessors according to CFG: BB#5
624B		%vreg41<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg41
640B		MOV32mi %vreg41, 1, %noreg, 0, %noreg, 0; mem:ST4[%8] GR64:%vreg41
	    Successors according to CFG: BB#7

656B	BB#7: derived from LLVM BB %if.end.8
	    Predecessors according to CFG: BB#5 BB#6
672B		CMP64mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
688B		JE_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#8

704B	BB#8: derived from LLVM BB %if.then.10
	    Predecessors according to CFG: BB#7
720B		%vreg44<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg44
736B		MOV32mi %vreg44, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr11] GR64:%vreg44
	    Successors according to CFG: BB#9

752B	BB#9: derived from LLVM BB %if.end.12
	    Predecessors according to CFG: BB#7 BB#8
768B		JMP_1 <BB#19>
	    Successors according to CFG: BB#19

784B	BB#10: derived from LLVM BB %if.end.13
	    Predecessors according to CFG: BB#4
800B		%vreg20<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg20
816B		CMP8mi %vreg20, 1, %noreg, 5012, %noreg, 0, %EFLAGS<imp-def>; mem:LD1[%writing] GR64:%vreg20
832B		JE_1 <BB#16>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#16 BB#11

848B	BB#11: derived from LLVM BB %if.then.14
	    Predecessors according to CFG: BB#10
864B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
880B		JE_1 <BB#13>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#13 BB#12

896B	BB#12: derived from LLVM BB %if.then.16
	    Predecessors according to CFG: BB#11
912B		%vreg35<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg35
928B		MOV32mi %vreg35, 1, %noreg, 0, %noreg, -1; mem:ST4[%14] GR64:%vreg35
	    Successors according to CFG: BB#13

944B	BB#13: derived from LLVM BB %if.end.17
	    Predecessors according to CFG: BB#11 BB#12
960B		CMP64mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
976B		JE_1 <BB#15>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#15 BB#14

992B	BB#14: derived from LLVM BB %if.then.19
	    Predecessors according to CFG: BB#13
1008B		%vreg38<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg38
1024B		MOV32mi %vreg38, 1, %noreg, 5096, %noreg, -1; mem:ST4[%lastErr20] GR64:%vreg38
	    Successors according to CFG: BB#15

1040B	BB#15: derived from LLVM BB %if.end.21
	    Predecessors according to CFG: BB#13 BB#14
1056B		JMP_1 <BB#19>
	    Successors according to CFG: BB#19

1072B	BB#16: derived from LLVM BB %if.end.22
	    Predecessors according to CFG: BB#10
1088B		%vreg23<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg23
1104B		CMP8mi %vreg23, 1, %noreg, 5100, %noreg, 0, %EFLAGS<imp-def>; mem:LD1[%initialisedOk] GR64:%vreg23
1120B		JE_1 <BB#18>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#18 BB#17

1136B	BB#17: derived from LLVM BB %if.then.24
	    Predecessors according to CFG: BB#16
1152B		%vreg27<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg27
1184B		%vreg27<def,tied1> = ADD64ri32 %vreg27<tied0>, 5016, %EFLAGS<imp-def,dead>; GR64:%vreg27
1200B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1216B		%RDI<def> = COPY %vreg27; GR64:%vreg27
1232B		CALL64pcrel32 <ga:@BZ2_bzDecompressEnd>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
1248B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1264B		%vreg25<def,dead> = COPY %EAX<kill>; GR32:%vreg25
1280B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1296B		STACKMAP 1, 0, 0, <fi#2>, 0, ...; mem:LD8[FixedStack2]
1312B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#18

1328B	BB#18: derived from LLVM BB %if.end.25
	    Predecessors according to CFG: BB#16 BB#17
1344B		%vreg31<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg31
1376B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1392B		%RDI<def> = COPY %vreg31; GR64:%vreg31
1408B		CALL64pcrel32 <ga:@free>, <regmask>, %RSP<imp-use>, %RDI<imp-use>
1424B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1440B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1456B		STACKMAP 2, 0, ...
1472B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#19

1488B	BB#19: derived from LLVM BB %return
	    Predecessors according to CFG: BB#18 BB#15 BB#9
1504B		%vreg46<def> = MOV64ri <ga:@BZ2_bzReadClose>; GR64:%vreg46
1536B		%vreg47<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg47
1552B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1568B		%RDI<def> = COPY %vreg46; GR64:%vreg46
1584B		%RSI<def> = COPY %vreg47; GR64:%vreg47
1600B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
1616B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1632B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1648B		STACKMAP 3, 0, ...
1664B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1680B		RETQ

# End machine code for function BZ2_bzReadClose.

********** GREEDY REGISTER ALLOCATION **********
********** Function: BZ2_bzReadClose
********** INTERVALS **********
DIL [0B,32r:0)[144r,176r:4)[1216r,1232r:3)[1392r,1408r:2)[1568r,1600r:1)  0@0B-phi 1@1568r 2@1392r 3@1216r 4@144r
SIL [0B,16r:0)[160r,176r:2)[1584r,1600r:1)  0@0B-phi 1@1584r 2@160r
%vreg1 [32r,256r:0)  0@32r
%vreg3 [16r,272r:0)  0@16r
%vreg7 [288r,320r:0)  0@288r
%vreg10 [80r,144r:0)  0@80r
%vreg11 [112r,160r:0)  0@112r
%vreg13 [384r,400r:0)  0@384r
%vreg16 [480r,496r:0)  0@480r
%vreg20 [800r,816r:0)  0@800r
%vreg23 [1088r,1104r:0)  0@1088r
%vreg25 [1264r,1264d:0)  0@1264r
%vreg27 [1152r,1184r:0)[1184r,1216r:1)  0@1152r 1@1184r
%vreg31 [1344r,1392r:0)  0@1344r
%vreg35 [912r,928r:0)  0@912r
%vreg38 [1008r,1024r:0)  0@1008r
%vreg41 [624r,640r:0)  0@624r
%vreg44 [720r,736r:0)  0@720r
%vreg46 [1504r,1568r:0)  0@1504r
%vreg47 [1536r,1584r:0)  0@1536r
RegMasks: 176r 1232r 1408r 1600r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzReadClose: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=8, align=8, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=8, align=8, at location [SP+8]
Function Live Ins: %RDI in %vreg0, %RSI in %vreg2

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI %RSI
16B		%vreg3<def> = COPY %RSI; GR64:%vreg3
32B		%vreg1<def> = COPY %RDI; GR64:%vreg1
80B		%vreg10<def> = MOV64ri <ga:@BZ2_bzReadClose>; GR64:%vreg10
112B		%vreg11<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg11
128B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
144B		%RDI<def> = COPY %vreg10; GR64:%vreg10
160B		%RSI<def> = COPY %vreg11; GR64:%vreg11
176B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
192B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
208B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#2>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack2] GR64:%vreg3,%vreg1
240B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
256B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%bzerror.addr] GR64:%vreg1
272B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg3; mem:ST8[%b.addr] GR64:%vreg3
288B		%vreg7<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr] GR64:%vreg7
320B		MOV64mr <fi#2>, 1, %noreg, 0, %noreg, %vreg7; mem:ST8[%bzf] GR64:%vreg7
336B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
352B		JE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

368B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
384B		%vreg13<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg13
400B		MOV32mi %vreg13, 1, %noreg, 0, %noreg, 0; mem:ST4[%3] GR64:%vreg13
	    Successors according to CFG: BB#2

416B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#1
432B		CMP64mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
448B		JE_1 <BB#4>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#4 BB#3

464B	BB#3: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#2
480B		%vreg16<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg16
496B		MOV32mi %vreg16, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr] GR64:%vreg16
	    Successors according to CFG: BB#4

512B	BB#4: derived from LLVM BB %if.end.3
	    Predecessors according to CFG: BB#2 BB#3
528B		CMP64mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
544B		JNE_1 <BB#10>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#10 BB#5

560B	BB#5: derived from LLVM BB %if.then.5
	    Predecessors according to CFG: BB#4
576B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
592B		JE_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#6

608B	BB#6: derived from LLVM BB %if.then.7
	    Predecessors according to CFG: BB#5
624B		%vreg41<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg41
640B		MOV32mi %vreg41, 1, %noreg, 0, %noreg, 0; mem:ST4[%8] GR64:%vreg41
	    Successors according to CFG: BB#7

656B	BB#7: derived from LLVM BB %if.end.8
	    Predecessors according to CFG: BB#5 BB#6
672B		CMP64mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
688B		JE_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#8

704B	BB#8: derived from LLVM BB %if.then.10
	    Predecessors according to CFG: BB#7
720B		%vreg44<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg44
736B		MOV32mi %vreg44, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr11] GR64:%vreg44
	    Successors according to CFG: BB#9

752B	BB#9: derived from LLVM BB %if.end.12
	    Predecessors according to CFG: BB#7 BB#8
768B		JMP_1 <BB#19>
	    Successors according to CFG: BB#19

784B	BB#10: derived from LLVM BB %if.end.13
	    Predecessors according to CFG: BB#4
800B		%vreg20<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg20
816B		CMP8mi %vreg20, 1, %noreg, 5012, %noreg, 0, %EFLAGS<imp-def>; mem:LD1[%writing] GR64:%vreg20
832B		JE_1 <BB#16>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#16 BB#11

848B	BB#11: derived from LLVM BB %if.then.14
	    Predecessors according to CFG: BB#10
864B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
880B		JE_1 <BB#13>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#13 BB#12

896B	BB#12: derived from LLVM BB %if.then.16
	    Predecessors according to CFG: BB#11
912B		%vreg35<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg35
928B		MOV32mi %vreg35, 1, %noreg, 0, %noreg, -1; mem:ST4[%14] GR64:%vreg35
	    Successors according to CFG: BB#13

944B	BB#13: derived from LLVM BB %if.end.17
	    Predecessors according to CFG: BB#11 BB#12
960B		CMP64mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
976B		JE_1 <BB#15>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#15 BB#14

992B	BB#14: derived from LLVM BB %if.then.19
	    Predecessors according to CFG: BB#13
1008B		%vreg38<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg38
1024B		MOV32mi %vreg38, 1, %noreg, 5096, %noreg, -1; mem:ST4[%lastErr20] GR64:%vreg38
	    Successors according to CFG: BB#15

1040B	BB#15: derived from LLVM BB %if.end.21
	    Predecessors according to CFG: BB#13 BB#14
1056B		JMP_1 <BB#19>
	    Successors according to CFG: BB#19

1072B	BB#16: derived from LLVM BB %if.end.22
	    Predecessors according to CFG: BB#10
1088B		%vreg23<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg23
1104B		CMP8mi %vreg23, 1, %noreg, 5100, %noreg, 0, %EFLAGS<imp-def>; mem:LD1[%initialisedOk] GR64:%vreg23
1120B		JE_1 <BB#18>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#18 BB#17

1136B	BB#17: derived from LLVM BB %if.then.24
	    Predecessors according to CFG: BB#16
1152B		%vreg27<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg27
1184B		%vreg27<def,tied1> = ADD64ri32 %vreg27<tied0>, 5016, %EFLAGS<imp-def,dead>; GR64:%vreg27
1200B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1216B		%RDI<def> = COPY %vreg27; GR64:%vreg27
1232B		CALL64pcrel32 <ga:@BZ2_bzDecompressEnd>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
1248B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1264B		%vreg25<def,dead> = COPY %EAX<kill>; GR32:%vreg25
1280B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1296B		STACKMAP 1, 0, 0, <fi#2>, 0, ...; mem:LD8[FixedStack2]
1312B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#18

1328B	BB#18: derived from LLVM BB %if.end.25
	    Predecessors according to CFG: BB#16 BB#17
1344B		%vreg31<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg31
1376B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1392B		%RDI<def> = COPY %vreg31; GR64:%vreg31
1408B		CALL64pcrel32 <ga:@free>, <regmask>, %RSP<imp-use>, %RDI<imp-use>
1424B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1440B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1456B		STACKMAP 2, 0, ...
1472B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#19

1488B	BB#19: derived from LLVM BB %return
	    Predecessors according to CFG: BB#18 BB#15 BB#9
1504B		%vreg46<def> = MOV64ri <ga:@BZ2_bzReadClose>; GR64:%vreg46
1536B		%vreg47<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg47
1552B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1568B		%RDI<def> = COPY %vreg46; GR64:%vreg46
1584B		%RSI<def> = COPY %vreg47; GR64:%vreg47
1600B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
1616B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1632B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1648B		STACKMAP 3, 0, ...
1664B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1680B		RETQ

# End machine code for function BZ2_bzReadClose.


selectOrSplit GR64:%vreg3 [16r,272r:0)  0@16r w=4.618902e-03
hints: %RSI
missed hint %RSI
assigning %vreg3 to %RBX: BH [16r,272r:0)  0@16r BL [16r,272r:0)  0@16r

selectOrSplit GR64:%vreg1 [32r,256r:0)  0@32r w=4.855769e-03
hints: %RDI
missed hint %RDI
%R14 is available at cost 1
Only trying the first 10 regs.
should evict: %vreg3 [16r,272r:0)  0@16r w= 4.618902e-03
hints: %RSI
can reassign: %vreg3 [16r,272r:0)  0@16r from %RBX to %RSI
should evict: %vreg3 [16r,272r:0)  0@16r w= 4.618902e-03
hints: %RSI
can reassign: %vreg3 [16r,272r:0)  0@16r from %RBX to %RSI
evicting %RBX interference: Cascade 1
unassigning %vreg3 from %RBX: BH BL
assigning %vreg1 to %RBX: BH [32r,256r:0)  0@32r BL [32r,256r:0)  0@32r
queuing new interval: %vreg3 [16r,272r:0)  0@16r

selectOrSplit GR64:%vreg3 [16r,272r:0)  0@16r w=4.618902e-03
hints: %RSI
missed hint %RSI
%R14 is available at cost 1
Only trying the first 10 regs.
assigning %vreg3 to %R14: R14B [16r,272r:0)  0@16r

selectOrSplit GR64:%vreg10 [80r,144r:0)  0@80r w=2.176724e-03
hints: %RDI
assigning %vreg10 to %RDI: DIL [80r,144r:0)  0@80r

selectOrSplit GR64:%vreg11 [112r,160r:0)  0@112r w=4.508928e-03
hints: %RSI
assigning %vreg11 to %RSI: SIL [112r,160r:0)  0@112r

selectOrSplit GR64:%vreg27 [1152r,1184r:0)[1184r,1216r:1)  0@1152r 1@1184r w=1.105638e-03
hints: %RDI
assigning %vreg27 to %RDI: DIL [1152r,1184r:0)[1184r,1216r:1)  0@1152r 1@1184r

selectOrSplit GR32:%vreg25 [1264r,1264d:0)  0@1264r w=inf
hints: %EAX
assigning %vreg25 to %EAX: AH [1264r,1264d:0)  0@1264r AL [1264r,1264d:0)  0@1264r

selectOrSplit GR64:%vreg31 [1344r,1392r:0)  0@1344r w=1.073555e-03
hints: %RDI
assigning %vreg31 to %RDI: DIL [1344r,1392r:0)  0@1344r

selectOrSplit GR64:%vreg46 [1504r,1568r:0)  0@1504r w=2.176724e-03
hints: %RDI
assigning %vreg46 to %RDI: DIL [1504r,1568r:0)  0@1504r

selectOrSplit GR64:%vreg47 [1536r,1584r:0)  0@1536r w=4.508928e-03
hints: %RSI
assigning %vreg47 to %RSI: SIL [1536r,1584r:0)  0@1536r

selectOrSplit GR64:%vreg7 [288r,320r:0)  0@288r w=inf
assigning %vreg7 to %RAX: AH [288r,320r:0)  0@288r AL [288r,320r:0)  0@288r

selectOrSplit GR64:%vreg13 [384r,400r:0)  0@384r w=inf
assigning %vreg13 to %RAX: AH [384r,400r:0)  0@384r AL [384r,400r:0)  0@384r

selectOrSplit GR64:%vreg16 [480r,496r:0)  0@480r w=inf
assigning %vreg16 to %RAX: AH [480r,496r:0)  0@480r AL [480r,496r:0)  0@480r

selectOrSplit GR64:%vreg41 [624r,640r:0)  0@624r w=inf
assigning %vreg41 to %RAX: AH [624r,640r:0)  0@624r AL [624r,640r:0)  0@624r

selectOrSplit GR64:%vreg44 [720r,736r:0)  0@720r w=inf
assigning %vreg44 to %RAX: AH [720r,736r:0)  0@720r AL [720r,736r:0)  0@720r

selectOrSplit GR64:%vreg20 [800r,816r:0)  0@800r w=inf
assigning %vreg20 to %RAX: AH [800r,816r:0)  0@800r AL [800r,816r:0)  0@800r

selectOrSplit GR64:%vreg35 [912r,928r:0)  0@912r w=inf
assigning %vreg35 to %RAX: AH [912r,928r:0)  0@912r AL [912r,928r:0)  0@912r

selectOrSplit GR64:%vreg38 [1008r,1024r:0)  0@1008r w=inf
assigning %vreg38 to %RAX: AH [1008r,1024r:0)  0@1008r AL [1008r,1024r:0)  0@1008r

selectOrSplit GR64:%vreg23 [1088r,1104r:0)  0@1088r w=inf
assigning %vreg23 to %RAX: AH [1088r,1104r:0)  0@1088r AL [1088r,1104r:0)  0@1088r

********** STACK TRANSFORMATION METADATA **********
********** Function: BZ2_bzReadClose
********** REGISTER MAP **********
[%vreg1 -> %RBX] GR64
[%vreg3 -> %R14] GR64
[%vreg7 -> %RAX] GR64
[%vreg10 -> %RDI] GR64
[%vreg11 -> %RSI] GR64
[%vreg13 -> %RAX] GR64
[%vreg16 -> %RAX] GR64
[%vreg20 -> %RAX] GR64
[%vreg23 -> %RAX] GR64
[%vreg25 -> %EAX] GR32
[%vreg27 -> %RDI] GR64
[%vreg31 -> %RDI] GR64
[%vreg35 -> %RAX] GR64
[%vreg38 -> %RAX] GR64
[%vreg41 -> %RAX] GR64
[%vreg44 -> %RAX] GR64
[%vreg46 -> %RDI] GR64
[%vreg47 -> %RSI] GR64


Stackmap 0:
  STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#2>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack2] GR64:%vreg3,%vreg1

i8* %b: in register %R14 (vreg 3)
i8** %b.addr: in stack slot 1 (size: 8)
i32* %bzerror: in register %RBX (vreg 1)
i32** %bzerror.addr: in stack slot 0 (size: 8)
%struct.bzFile** %bzf: in stack slot 2 (size: 8)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, 0, <fi#2>, 0, ...; mem:LD8[FixedStack2]

%struct.bzFile** %bzf: in stack slot 2 (size: 8)

Duplicate operand locations:


Stackmap 2:
  STACKMAP 2, 0, ...


Duplicate operand locations:


Stackmap 3:
  STACKMAP 3, 0, ...


Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#2>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack2] GR64:%vreg3,%vreg1
  -> Call instruction SlotIndex 176B, searching vregs 0 -> 48 and stack slots -1 -> 3

  STACKMAP 1, 0, 0, <fi#2>, 0, ...; mem:LD8[FixedStack2]
  -> Call instruction SlotIndex 1232B, searching vregs 0 -> 48 and stack slots -1 -> 3

  STACKMAP 2, 0, ...
  -> Call instruction SlotIndex 1408B, searching vregs 0 -> 48 and stack slots -1 -> 3

  STACKMAP 3, 0, ...
  -> Call instruction SlotIndex 1600B, searching vregs 0 -> 48 and stack slots -1 -> 3

********** REWRITE VIRTUAL REGISTERS **********
********** Function: BZ2_bzReadClose
********** REGISTER MAP **********
[%vreg1 -> %RBX] GR64
[%vreg3 -> %R14] GR64
[%vreg7 -> %RAX] GR64
[%vreg10 -> %RDI] GR64
[%vreg11 -> %RSI] GR64
[%vreg13 -> %RAX] GR64
[%vreg16 -> %RAX] GR64
[%vreg20 -> %RAX] GR64
[%vreg23 -> %RAX] GR64
[%vreg25 -> %EAX] GR32
[%vreg27 -> %RDI] GR64
[%vreg31 -> %RDI] GR64
[%vreg35 -> %RAX] GR64
[%vreg38 -> %RAX] GR64
[%vreg41 -> %RAX] GR64
[%vreg44 -> %RAX] GR64
[%vreg46 -> %RDI] GR64
[%vreg47 -> %RSI] GR64

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI %RSI
16B		%vreg3<def> = COPY %RSI; GR64:%vreg3
32B		%vreg1<def> = COPY %RDI; GR64:%vreg1
80B		%vreg10<def> = MOV64ri <ga:@BZ2_bzReadClose>; GR64:%vreg10
112B		%vreg11<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg11
128B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
144B		%RDI<def> = COPY %vreg10<kill>; GR64:%vreg10
160B		%RSI<def> = COPY %vreg11<kill>; GR64:%vreg11
176B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
192B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
208B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#2>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack2] GR64:%vreg3,%vreg1
240B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
256B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1<kill>; mem:ST8[%bzerror.addr] GR64:%vreg1
272B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg3<kill>; mem:ST8[%b.addr] GR64:%vreg3
288B		%vreg7<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr] GR64:%vreg7
320B		MOV64mr <fi#2>, 1, %noreg, 0, %noreg, %vreg7<kill>; mem:ST8[%bzf] GR64:%vreg7
336B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
352B		JE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1
> %R14<def> = COPY %RSI
> %RBX<def> = COPY %RDI
> %RDI<def> = MOV64ri <ga:@BZ2_bzReadClose>
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 0, 0, %R14, 0, <fi#1>, 0, %RBX, 0, <fi#0>, 0, 0, <fi#2>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack2]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %RBX<kill>; mem:ST8[%bzerror.addr]
> MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %R14<kill>; mem:ST8[%b.addr]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr]
> MOV64mr <fi#2>, 1, %noreg, 0, %noreg, %RAX<kill>; mem:ST8[%bzf]
> CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
> JE_1 <BB#2>, %EFLAGS<imp-use,kill>
368B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
384B		%vreg13<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg13
400B		MOV32mi %vreg13<kill>, 1, %noreg, 0, %noreg, 0; mem:ST4[%3] GR64:%vreg13
	    Successors according to CFG: BB#2
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 0, %noreg, 0; mem:ST4[%3]
416B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#1
432B		CMP64mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
448B		JE_1 <BB#4>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#4 BB#3
> CMP64mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
> JE_1 <BB#4>, %EFLAGS<imp-use,kill>
464B	BB#3: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#2
480B		%vreg16<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg16
496B		MOV32mi %vreg16<kill>, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr] GR64:%vreg16
	    Successors according to CFG: BB#4
> %RAX<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV32mi %RAX<kill>, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr]
512B	BB#4: derived from LLVM BB %if.end.3
	    Predecessors according to CFG: BB#2 BB#3
528B		CMP64mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
544B		JNE_1 <BB#10>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#10 BB#5
> CMP64mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
> JNE_1 <BB#10>, %EFLAGS<imp-use,kill>
560B	BB#5: derived from LLVM BB %if.then.5
	    Predecessors according to CFG: BB#4
576B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
592B		JE_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#6
> CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
> JE_1 <BB#7>, %EFLAGS<imp-use,kill>
608B	BB#6: derived from LLVM BB %if.then.7
	    Predecessors according to CFG: BB#5
624B		%vreg41<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg41
640B		MOV32mi %vreg41<kill>, 1, %noreg, 0, %noreg, 0; mem:ST4[%8] GR64:%vreg41
	    Successors according to CFG: BB#7
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 0, %noreg, 0; mem:ST4[%8]
656B	BB#7: derived from LLVM BB %if.end.8
	    Predecessors according to CFG: BB#5 BB#6
672B		CMP64mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
688B		JE_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#8
> CMP64mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
> JE_1 <BB#9>, %EFLAGS<imp-use,kill>
704B	BB#8: derived from LLVM BB %if.then.10
	    Predecessors according to CFG: BB#7
720B		%vreg44<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg44
736B		MOV32mi %vreg44<kill>, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr11] GR64:%vreg44
	    Successors according to CFG: BB#9
> %RAX<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV32mi %RAX<kill>, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr11]
752B	BB#9: derived from LLVM BB %if.end.12
	    Predecessors according to CFG: BB#7 BB#8
768B		JMP_1 <BB#19>
	    Successors according to CFG: BB#19
> JMP_1 <BB#19>
784B	BB#10: derived from LLVM BB %if.end.13
	    Predecessors according to CFG: BB#4
800B		%vreg20<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg20
816B		CMP8mi %vreg20<kill>, 1, %noreg, 5012, %noreg, 0, %EFLAGS<imp-def>; mem:LD1[%writing] GR64:%vreg20
832B		JE_1 <BB#16>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#16 BB#11
> %RAX<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> CMP8mi %RAX<kill>, 1, %noreg, 5012, %noreg, 0, %EFLAGS<imp-def>; mem:LD1[%writing]
> JE_1 <BB#16>, %EFLAGS<imp-use,kill>
848B	BB#11: derived from LLVM BB %if.then.14
	    Predecessors according to CFG: BB#10
864B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
880B		JE_1 <BB#13>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#13 BB#12
> CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
> JE_1 <BB#13>, %EFLAGS<imp-use,kill>
896B	BB#12: derived from LLVM BB %if.then.16
	    Predecessors according to CFG: BB#11
912B		%vreg35<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg35
928B		MOV32mi %vreg35<kill>, 1, %noreg, 0, %noreg, -1; mem:ST4[%14] GR64:%vreg35
	    Successors according to CFG: BB#13
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 0, %noreg, -1; mem:ST4[%14]
944B	BB#13: derived from LLVM BB %if.end.17
	    Predecessors according to CFG: BB#11 BB#12
960B		CMP64mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
976B		JE_1 <BB#15>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#15 BB#14
> CMP64mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
> JE_1 <BB#15>, %EFLAGS<imp-use,kill>
992B	BB#14: derived from LLVM BB %if.then.19
	    Predecessors according to CFG: BB#13
1008B		%vreg38<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg38
1024B		MOV32mi %vreg38<kill>, 1, %noreg, 5096, %noreg, -1; mem:ST4[%lastErr20] GR64:%vreg38
	    Successors according to CFG: BB#15
> %RAX<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV32mi %RAX<kill>, 1, %noreg, 5096, %noreg, -1; mem:ST4[%lastErr20]
1040B	BB#15: derived from LLVM BB %if.end.21
	    Predecessors according to CFG: BB#13 BB#14
1056B		JMP_1 <BB#19>
	    Successors according to CFG: BB#19
> JMP_1 <BB#19>
1072B	BB#16: derived from LLVM BB %if.end.22
	    Predecessors according to CFG: BB#10
1088B		%vreg23<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg23
1104B		CMP8mi %vreg23<kill>, 1, %noreg, 5100, %noreg, 0, %EFLAGS<imp-def>; mem:LD1[%initialisedOk] GR64:%vreg23
1120B		JE_1 <BB#18>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#18 BB#17
> %RAX<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> CMP8mi %RAX<kill>, 1, %noreg, 5100, %noreg, 0, %EFLAGS<imp-def>; mem:LD1[%initialisedOk]
> JE_1 <BB#18>, %EFLAGS<imp-use,kill>
1136B	BB#17: derived from LLVM BB %if.then.24
	    Predecessors according to CFG: BB#16
1152B		%vreg27<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg27
1184B		%vreg27<def,tied1> = ADD64ri32 %vreg27<kill,tied0>, 5016, %EFLAGS<imp-def,dead>; GR64:%vreg27
1200B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1216B		%RDI<def> = COPY %vreg27<kill>; GR64:%vreg27
1232B		CALL64pcrel32 <ga:@BZ2_bzDecompressEnd>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
1248B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1264B		%vreg25<def,dead> = COPY %EAX; GR32:%vreg25
1280B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1296B		STACKMAP 1, 0, 0, <fi#2>, 0, ...; mem:LD8[FixedStack2]
1312B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#18
> %RDI<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> %RDI<def,tied1> = ADD64ri32 %RDI<kill,tied0>, 5016, %EFLAGS<imp-def,dead>
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@BZ2_bzDecompressEnd>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def,dead> = COPY %EAX
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 1, 0, 0, <fi#2>, 0, ...; mem:LD8[FixedStack2]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1328B	BB#18: derived from LLVM BB %if.end.25
	    Predecessors according to CFG: BB#16 BB#17
1344B		%vreg31<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg31
1376B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1392B		%RDI<def> = COPY %vreg31<kill>; GR64:%vreg31
1408B		CALL64pcrel32 <ga:@free>, <regmask>, %RSP<imp-use>, %RDI<imp-use>
1424B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1440B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1456B		STACKMAP 2, 0, ...
1472B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#19
> %RDI<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@free>, <regmask>, %RSP<imp-use>, %RDI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 2, 0, ...
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1488B	BB#19: derived from LLVM BB %return
	    Predecessors according to CFG: BB#18 BB#15 BB#9
1504B		%vreg46<def> = MOV64ri <ga:@BZ2_bzReadClose>; GR64:%vreg46
1536B		%vreg47<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg47
1552B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1568B		%RDI<def> = COPY %vreg46<kill>; GR64:%vreg46
1584B		%RSI<def> = COPY %vreg47<kill>; GR64:%vreg47
1600B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
1616B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1632B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1648B		STACKMAP 3, 0, ...
1664B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1680B		RETQ
> %RDI<def> = MOV64ri <ga:@BZ2_bzReadClose>
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 3, 0, ...
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> RETQ
Computing live-in reg-units in ABI blocks.
0B	BB#0 DIL#0 SIL#0 DH#0 DL#0 CH#0 CL#0
Created 6 new intervals.
********** INTERVALS **********
CH [0B,16r:0)[2640r,2656r:1)  0@0B-phi 1@2640r
CL [0B,16r:0)[2640r,2656r:1)  0@0B-phi 1@2640r
DH [0B,32r:0)[2624r,2656r:1)  0@0B-phi 1@2624r
DIL [0B,64r:0)[208r,240r:8)[1760r,1776r:7)[2272r,2288r:6)[2592r,2656r:4)[2832r,2848r:5)[3504r,3520r:3)[4096r,4112r:2)[5408r,5440r:1)  0@0B-phi 1@5408r 2@4096r 3@3504r 4@2592r 5@2832r 6@2272r 7@1760r 8@208r
DL [0B,32r:0)[2624r,2656r:1)  0@0B-phi 1@2624r
SIL [0B,48r:0)[224r,240r:3)[2608r,2656r:2)[5424r,5440r:1)  0@0B-phi 1@5424r 2@2608r 3@224r
%vreg0 [64r,80r:0)  0@64r
%vreg1 [80r,320r:0)  0@80r
%vreg2 [48r,96r:0)  0@48r
%vreg3 [96r,336r:0)  0@96r
%vreg4 [32r,112r:0)  0@32r
%vreg5 [112r,352r:0)  0@112r
%vreg6 [16r,128r:0)  0@16r
%vreg7 [128r,368r:0)  0@128r
%vreg11 [400r,416r:0)  0@400r
%vreg12 [384r,400r:0)  0@384r
%vreg13 [144r,160r:0)  0@144r
%vreg14 [160r,208r:0)  0@160r
%vreg15 [176r,224r:0)  0@176r
%vreg17 [480r,496r:0)  0@480r
%vreg20 [576r,592r:0)  0@576r
%vreg26 [1008r,1024r:0)  0@1008r
%vreg30 [1664r,1680r:0)  0@1664r
%vreg31 [1648r,1680r:0)  0@1648r
%vreg34 [1616r,1632r:0)  0@1616r
%vreg35 [1600r,1632r:0)  0@1600r
%vreg38 [1808r,1872r:0)  0@1808r
%vreg40 [1728r,1760r:0)  0@1728r
%vreg41 [1712r,1728r:0)  0@1712r
%vreg44 [2160r,2176r:0)  0@2160r
%vreg47 [2320r,2384r:0)  0@2320r
%vreg49 [2240r,2272r:0)  0@2240r
%vreg50 [2224r,2240r:0)  0@2224r
%vreg53 [2880r,2944r:0)  0@2880r
%vreg55 [2800r,2832r:0)  0@2800r
%vreg56 [2784r,2800r:0)  0@2784r
%vreg59 [2752r,2768r:0)  0@2752r
%vreg61 [2432r,2448r:0)  0@2432r
%vreg62 [2448r,2608r:0)  0@2448r
%vreg63 [2464r,2480r:0)  0@2464r
%vreg64 [2480r,2624r:0)  0@2480r
%vreg66 [2688r,2752r:0)  0@2688r
%vreg68 [2560r,2640r:0)  0@2560r
%vreg69 [2544r,2560r:0)  0@2544r
%vreg72 [2512r,2528r:0)[2528r,2592r:1)  0@2512r 1@2528r
%vreg73 [2496r,2512r:0)  0@2496r
%vreg76 [3392r,3408r:0)  0@3392r
%vreg79 [3360r,3376r:0)[3376r,3408r:1)  0@3360r 1@3376r
%vreg80 [3344r,3360r:0)  0@3344r
%vreg83 [3312r,3328r:0)  0@3312r
%vreg85 [3296r,3328r:0)  0@3296r
%vreg86 [3280r,3296r:0)  0@3280r
%vreg89 [3248r,3264r:0)  0@3248r
%vreg90 [3232r,3264r:0)  0@3232r
%vreg93 [3040r,3056r:0)  0@3040r
%vreg96 [3136r,3152r:0)  0@3136r
%vreg100 [3552r,3616r:0)  0@3552r
%vreg102 [3456r,3472r:0)[3472r,3504r:1)  0@3456r 1@3472r
%vreg103 [3440r,3456r:0)  0@3440r
%vreg108 [4208r,4224r:0)  0@4208r
%vreg110 [4144r,4208r:0)  0@4144r
%vreg112 [4064r,4096r:0)  0@4064r
%vreg113 [4048r,4064r:0)  0@4048r
%vreg116 [4272r,4288r:0)  0@4272r
%vreg119 [4336r,4352r:0)  0@4336r
%vreg123 [4992r,5008r:0)  0@4992r
%vreg126 [5104r,5120r:0)  0@5104r
%vreg129 [5200r,5216r:0)  0@5200r
%vreg131 [5248r,5264r:0)  0@5248r
%vreg134 [4736r,4752r:0)  0@4736r
%vreg137 [4832r,4848r:0)  0@4832r
%vreg141 [4912r,4928r:0)[4928r,4944r:1)  0@4912r 1@4928r
%vreg143 [4896r,4928r:0)  0@4896r
%vreg144 [4880r,4912r:0)  0@4880r
%vreg147 [4448r,4464r:0)  0@4448r
%vreg150 [4544r,4560r:0)  0@4544r
%vreg154 [3792r,3808r:0)  0@3792r
%vreg155 [3776r,3808r:0)  0@3776r
%vreg159 [3904r,3920r:0)  0@3904r
%vreg160 [3888r,3920r:0)  0@3888r
%vreg163 [1968r,1984r:0)  0@1968r
%vreg166 [2064r,2080r:0)  0@2064r
%vreg169 [1408r,1424r:0)  0@1408r
%vreg172 [1504r,1520r:0)  0@1504r
%vreg175 [1120r,1136r:0)  0@1120r
%vreg178 [1216r,1232r:0)  0@1216r
%vreg181 [816r,832r:0)  0@816r
%vreg184 [912r,928r:0)  0@912r
%vreg186 [5520r,5536r:0)  0@5520r
%vreg187 [5344r,5360r:0)  0@5344r
%vreg188 [5360r,5408r:0)  0@5360r
%vreg189 [5376r,5424r:0)  0@5376r
RegMasks: 240r 1776r 2288r 2656r 2848r 3520r 4112r 5440r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzRead: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=4, align=4, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=8, align=8, at location [SP+8]
  fi#3: size=8, align=8, at location [SP+8]
  fi#4: size=4, align=4, at location [SP+8]
  fi#5: size=4, align=4, at location [SP+8]
  fi#6: size=4, align=4, at location [SP+8]
  fi#7: size=8, align=8, at location [SP+8]
Function Live Ins: %RDI in %vreg0, %RSI in %vreg2, %RDX in %vreg4, %ECX in %vreg6

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI %RSI %RDX %ECX
16B		%vreg6<def> = COPY %ECX; GR32:%vreg6
32B		%vreg4<def> = COPY %RDX; GR64:%vreg4
48B		%vreg2<def> = COPY %RSI; GR64:%vreg2
64B		%vreg0<def> = COPY %RDI; GR64:%vreg0
80B		%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
96B		%vreg3<def> = COPY %vreg2; GR64:%vreg3,%vreg2
112B		%vreg5<def> = COPY %vreg4; GR64:%vreg5,%vreg4
128B		%vreg7<def> = COPY %vreg6; GR32:%vreg7,%vreg6
144B		%vreg13<def> = MOV64ri <ga:@BZ2_bzRead>; GR64:%vreg13
160B		%vreg14<def> = COPY %vreg13; GR64:%vreg14,%vreg13
176B		%vreg15<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg15
192B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
208B		%RDI<def> = COPY %vreg14; GR64:%vreg14
224B		%RSI<def> = COPY %vreg15; GR64:%vreg15
240B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
256B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
272B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
288B		STACKMAP 0, 0, %vreg3, 0, <fi#2>, 0, %vreg5, 0, <fi#3>, 0, %vreg1, 0, <fi#1>, 0, 0, <fi#7>, 0, %vreg7, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack2] LD8[FixedStack3] LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4) GR64:%vreg3,%vreg5,%vreg1 GR32:%vreg7
304B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
320B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%bzerror.addr] GR64:%vreg1
336B		MOV64mr <fi#2>, 1, %noreg, 0, %noreg, %vreg3; mem:ST8[%b.addr] GR64:%vreg3
352B		MOV64mr <fi#3>, 1, %noreg, 0, %noreg, %vreg5; mem:ST8[%buf.addr] GR64:%vreg5
368B		MOV32mr <fi#4>, 1, %noreg, 0, %noreg, %vreg7; mem:ST4[%len.addr] GR32:%vreg7
384B		%vreg12<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr] GR64:%vreg12
400B		%vreg11<def> = COPY %vreg12; GR64:%vreg11,%vreg12
416B		MOV64mr <fi#7>, 1, %noreg, 0, %noreg, %vreg11; mem:ST8[%bzf] GR64:%vreg11
432B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
448B		JE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

464B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
480B		%vreg17<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg17
496B		MOV32mi %vreg17, 1, %noreg, 0, %noreg, 0; mem:ST4[%3] GR64:%vreg17
	    Successors according to CFG: BB#2

512B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#1
528B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
544B		JE_1 <BB#4>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#4 BB#3

560B	BB#3: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#2
576B		%vreg20<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg20
592B		MOV32mi %vreg20, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr] GR64:%vreg20
	    Successors according to CFG: BB#4

608B	BB#4: derived from LLVM BB %if.end.3
	    Predecessors according to CFG: BB#2 BB#3
624B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
640B		JE_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#5

656B	BB#5: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#4
672B		CMP64mi8 <fi#3>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%buf.addr]
688B		JE_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#6

704B	BB#6: derived from LLVM BB %lor.lhs.false.6
	    Predecessors according to CFG: BB#5
720B		CMP32mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%len.addr]
736B		JGE_1 <BB#12>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#12 BB#7

752B	BB#7: derived from LLVM BB %if.then.8
	    Predecessors according to CFG: BB#4 BB#5 BB#6
768B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
784B		JE_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#8

800B	BB#8: derived from LLVM BB %if.then.10
	    Predecessors according to CFG: BB#7
816B		%vreg181<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg181
832B		MOV32mi %vreg181, 1, %noreg, 0, %noreg, -2; mem:ST4[%10] GR64:%vreg181
	    Successors according to CFG: BB#9

848B	BB#9: derived from LLVM BB %if.end.11
	    Predecessors according to CFG: BB#7 BB#8
864B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
880B		JE_1 <BB#11>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#11 BB#10

896B	BB#10: derived from LLVM BB %if.then.13
	    Predecessors according to CFG: BB#9
912B		%vreg184<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg184
928B		MOV32mi %vreg184, 1, %noreg, 5096, %noreg, -2; mem:ST4[%lastErr14] GR64:%vreg184
	    Successors according to CFG: BB#11

944B	BB#11: derived from LLVM BB %if.end.15
	    Predecessors according to CFG: BB#9 BB#10
960B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
976B		JMP_1 <BB#69>
	    Successors according to CFG: BB#69

992B	BB#12: derived from LLVM BB %if.end.16
	    Predecessors according to CFG: BB#6
1008B		%vreg26<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg26
1024B		CMP8mi %vreg26, 1, %noreg, 5012, %noreg, 0, %EFLAGS<imp-def>; mem:LD1[%writing] GR64:%vreg26
1040B		JE_1 <BB#18>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#18 BB#13

1056B	BB#13: derived from LLVM BB %if.then.17
	    Predecessors according to CFG: BB#12
1072B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
1088B		JE_1 <BB#15>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#15 BB#14

1104B	BB#14: derived from LLVM BB %if.then.19
	    Predecessors according to CFG: BB#13
1120B		%vreg175<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg175
1136B		MOV32mi %vreg175, 1, %noreg, 0, %noreg, -1; mem:ST4[%16] GR64:%vreg175
	    Successors according to CFG: BB#15

1152B	BB#15: derived from LLVM BB %if.end.20
	    Predecessors according to CFG: BB#13 BB#14
1168B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
1184B		JE_1 <BB#17>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#17 BB#16

1200B	BB#16: derived from LLVM BB %if.then.22
	    Predecessors according to CFG: BB#15
1216B		%vreg178<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg178
1232B		MOV32mi %vreg178, 1, %noreg, 5096, %noreg, -1; mem:ST4[%lastErr23] GR64:%vreg178
	    Successors according to CFG: BB#17

1248B	BB#17: derived from LLVM BB %if.end.24
	    Predecessors according to CFG: BB#15 BB#16
1264B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
1280B		JMP_1 <BB#69>
	    Successors according to CFG: BB#69

1296B	BB#18: derived from LLVM BB %if.end.25
	    Predecessors according to CFG: BB#12
1312B		CMP32mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%len.addr]
1328B		JNE_1 <BB#24>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#24 BB#19

1344B	BB#19: derived from LLVM BB %if.then.27
	    Predecessors according to CFG: BB#18
1360B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
1376B		JE_1 <BB#21>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#21 BB#20

1392B	BB#20: derived from LLVM BB %if.then.29
	    Predecessors according to CFG: BB#19
1408B		%vreg169<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg169
1424B		MOV32mi %vreg169, 1, %noreg, 0, %noreg, 0; mem:ST4[%21] GR64:%vreg169
	    Successors according to CFG: BB#21

1440B	BB#21: derived from LLVM BB %if.end.30
	    Predecessors according to CFG: BB#19 BB#20
1456B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
1472B		JE_1 <BB#23>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#23 BB#22

1488B	BB#22: derived from LLVM BB %if.then.32
	    Predecessors according to CFG: BB#21
1504B		%vreg172<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg172
1520B		MOV32mi %vreg172, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr33] GR64:%vreg172
	    Successors according to CFG: BB#23

1536B	BB#23: derived from LLVM BB %if.end.34
	    Predecessors according to CFG: BB#21 BB#22
1552B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
1568B		JMP_1 <BB#69>
	    Successors according to CFG: BB#69

1584B	BB#24: derived from LLVM BB %if.end.35
	    Predecessors according to CFG: BB#18
1600B		%vreg35<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%len.addr] GR32:%vreg35
1616B		%vreg34<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg34
1632B		MOV32mr %vreg34, 1, %noreg, 5048, %noreg, %vreg35; mem:ST4[%avail_out] GR64:%vreg34 GR32:%vreg35
1648B		%vreg31<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%buf.addr] GR64:%vreg31
1664B		%vreg30<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg30
1680B		MOV64mr %vreg30, 1, %noreg, 5040, %noreg, %vreg31; mem:ST8[%next_out] GR64:%vreg30,%vreg31
	    Successors according to CFG: BB#25

1696B	BB#25: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#24 BB#68
1712B		%vreg41<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg41
1728B		%vreg40<def> = MOV64rm %vreg41, 1, %noreg, 0, %noreg; mem:LD8[%handle] GR64:%vreg40,%vreg41
1744B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1760B		%RDI<def> = COPY %vreg40; GR64:%vreg40
1776B		CALL64pcrel32 <ga:@ferror>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
1792B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1808B		%vreg38<def> = COPY %EAX<kill>; GR32:%vreg38
1824B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1840B		STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
1856B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1872B		CMP32ri8 %vreg38, 0, %EFLAGS<imp-def>; GR32:%vreg38
1888B		JE_1 <BB#31>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#31 BB#26

1904B	BB#26: derived from LLVM BB %if.then.38
	    Predecessors according to CFG: BB#25
1920B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
1936B		JE_1 <BB#28>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#28 BB#27

1952B	BB#27: derived from LLVM BB %if.then.40
	    Predecessors according to CFG: BB#26
1968B		%vreg163<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg163
1984B		MOV32mi %vreg163, 1, %noreg, 0, %noreg, -6; mem:ST4[%31] GR64:%vreg163
	    Successors according to CFG: BB#28

2000B	BB#28: derived from LLVM BB %if.end.41
	    Predecessors according to CFG: BB#26 BB#27
2016B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
2032B		JE_1 <BB#30>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#30 BB#29

2048B	BB#29: derived from LLVM BB %if.then.43
	    Predecessors according to CFG: BB#28
2064B		%vreg166<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg166
2080B		MOV32mi %vreg166, 1, %noreg, 5096, %noreg, -6; mem:ST4[%lastErr44] GR64:%vreg166
	    Successors according to CFG: BB#30

2096B	BB#30: derived from LLVM BB %if.end.45
	    Predecessors according to CFG: BB#28 BB#29
2112B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
2128B		JMP_1 <BB#69>
	    Successors according to CFG: BB#69

2144B	BB#31: derived from LLVM BB %if.end.46
	    Predecessors according to CFG: BB#25
2160B		%vreg44<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg44
2176B		CMP32mi8 %vreg44, 1, %noreg, 5024, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_in] GR64:%vreg44
2192B		JNE_1 <BB#40>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#40 BB#32

2208B	BB#32: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#31
2224B		%vreg50<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg50
2240B		%vreg49<def> = MOV64rm %vreg50, 1, %noreg, 0, %noreg; mem:LD8[%handle49] GR64:%vreg49,%vreg50
2256B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2272B		%RDI<def> = COPY %vreg49; GR64:%vreg49
2288B		CALL64pcrel32 <ga:@myfeof>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %AL<imp-def>
2304B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2320B		%vreg47<def> = COPY %AL<kill>; GR8:%vreg47
2336B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2352B		STACKMAP 2, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
2368B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2384B		CMP8ri %vreg47, 0, %EFLAGS<imp-def>; GR8:%vreg47
2400B		JNE_1 <BB#40>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#40 BB#33

2416B	BB#33: derived from LLVM BB %if.then.52
	    Predecessors according to CFG: BB#32
2432B		%vreg61<def> = MOV32ri 1; GR32:%vreg61
2448B		%vreg62<def> = SUBREG_TO_REG 0, %vreg61, 4; GR64:%vreg62 GR32:%vreg61
2464B		%vreg63<def> = MOV32ri 5000; GR32:%vreg63
2480B		%vreg64<def> = SUBREG_TO_REG 0, %vreg63, 4; GR64:%vreg64 GR32:%vreg63
2496B		%vreg73<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg73
2512B		%vreg72<def> = COPY %vreg73; GR64:%vreg72,%vreg73
2528B		%vreg72<def,tied1> = ADD64ri8 %vreg72<tied0>, 8, %EFLAGS<imp-def,dead>; GR64:%vreg72
2544B		%vreg69<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg69
2560B		%vreg68<def> = MOV64rm %vreg69, 1, %noreg, 0, %noreg; mem:LD8[%handle54] GR64:%vreg68,%vreg69
2576B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2592B		%RDI<def> = COPY %vreg72; GR64:%vreg72
2608B		%RSI<def> = COPY %vreg62; GR64:%vreg62
2624B		%RDX<def> = COPY %vreg64; GR64:%vreg64
2640B		%RCX<def> = COPY %vreg68; GR64:%vreg68
2656B		CALL64pcrel32 <ga:@fread>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %RDX<imp-use>, %RCX<imp-use>, %RAX<imp-def>
2672B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2688B		%vreg66<def> = COPY %RAX<kill>; GR64:%vreg66
2704B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2720B		STACKMAP 3, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
2736B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2752B		%vreg59<def> = COPY %vreg66:sub_32bit; GR32:%vreg59 GR64:%vreg66
2768B		MOV32mr <fi#5>, 1, %noreg, 0, %noreg, %vreg59; mem:ST4[%n] GR32:%vreg59
2784B		%vreg56<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg56
2800B		%vreg55<def> = MOV64rm %vreg56, 1, %noreg, 0, %noreg; mem:LD8[%handle56] GR64:%vreg55,%vreg56
2816B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2832B		%RDI<def> = COPY %vreg55; GR64:%vreg55
2848B		CALL64pcrel32 <ga:@ferror>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
2864B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2880B		%vreg53<def> = COPY %EAX<kill>; GR32:%vreg53
2896B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2912B		STACKMAP 4, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
2928B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2944B		CMP32ri8 %vreg53, 0, %EFLAGS<imp-def>; GR32:%vreg53
2960B		JE_1 <BB#39>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#39 BB#34

2976B	BB#34: derived from LLVM BB %if.then.59
	    Predecessors according to CFG: BB#33
2992B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
3008B		JE_1 <BB#36>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#36 BB#35

3024B	BB#35: derived from LLVM BB %if.then.62
	    Predecessors according to CFG: BB#34
3040B		%vreg93<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg93
3056B		MOV32mi %vreg93, 1, %noreg, 0, %noreg, -6; mem:ST4[%44] GR64:%vreg93
	    Successors according to CFG: BB#36

3072B	BB#36: derived from LLVM BB %if.end.63
	    Predecessors according to CFG: BB#34 BB#35
3088B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
3104B		JE_1 <BB#38>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#38 BB#37

3120B	BB#37: derived from LLVM BB %if.then.66
	    Predecessors according to CFG: BB#36
3136B		%vreg96<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg96
3152B		MOV32mi %vreg96, 1, %noreg, 5096, %noreg, -6; mem:ST4[%lastErr67] GR64:%vreg96
	    Successors according to CFG: BB#38

3168B	BB#38: derived from LLVM BB %if.end.68
	    Predecessors according to CFG: BB#36 BB#37
3184B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
3200B		JMP_1 <BB#69>
	    Successors according to CFG: BB#69

3216B	BB#39: derived from LLVM BB %if.end.69
	    Predecessors according to CFG: BB#33
3232B		%vreg90<def> = MOV32rm <fi#5>, 1, %noreg, 0, %noreg; mem:LD4[%n] GR32:%vreg90
3248B		%vreg89<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg89
3264B		MOV32mr %vreg89, 1, %noreg, 5008, %noreg, %vreg90; mem:ST4[%bufN] GR64:%vreg89 GR32:%vreg90
3280B		%vreg86<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg86
3296B		%vreg85<def> = MOV32rm %vreg86, 1, %noreg, 5008, %noreg; mem:LD4[%bufN70] GR32:%vreg85 GR64:%vreg86
3312B		%vreg83<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg83
3328B		MOV32mr %vreg83, 1, %noreg, 5024, %noreg, %vreg85; mem:ST4[%avail_in72] GR64:%vreg83 GR32:%vreg85
3344B		%vreg80<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg80
3360B		%vreg79<def> = COPY %vreg80; GR64:%vreg79,%vreg80
3376B		%vreg79<def,tied1> = ADD64ri8 %vreg79<tied0>, 8, %EFLAGS<imp-def,dead>; GR64:%vreg79
3392B		%vreg76<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg76
3408B		MOV64mr %vreg76, 1, %noreg, 5016, %noreg, %vreg79; mem:ST8[%next_in] GR64:%vreg76,%vreg79
	    Successors according to CFG: BB#40

3424B	BB#40: derived from LLVM BB %if.end.76
	    Predecessors according to CFG: BB#31 BB#32 BB#39
3440B		%vreg103<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg103
3456B		%vreg102<def> = COPY %vreg103; GR64:%vreg102,%vreg103
3472B		%vreg102<def,tied1> = ADD64ri32 %vreg102<tied0>, 5016, %EFLAGS<imp-def,dead>; GR64:%vreg102
3488B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3504B		%RDI<def> = COPY %vreg102; GR64:%vreg102
3520B		CALL64pcrel32 <ga:@BZ2_bzDecompress>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
3536B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3552B		%vreg100<def> = COPY %EAX<kill>; GR32:%vreg100
3568B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3584B		STACKMAP 5, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
3600B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3616B		MOV32mr <fi#6>, 1, %noreg, 0, %noreg, %vreg100; mem:ST4[%ret] GR32:%vreg100
3632B		CMP32mi8 <fi#6>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%ret]
3648B		JE_1 <BB#47>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#47 BB#41

3664B	BB#41: derived from LLVM BB %land.lhs.true.81
	    Predecessors according to CFG: BB#40
3680B		CMP32mi8 <fi#6>, 1, %noreg, 0, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%ret]
3696B		JE_1 <BB#47>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#47 BB#42

3712B	BB#42: derived from LLVM BB %if.then.84
	    Predecessors according to CFG: BB#41
3728B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
3744B		JE_1 <BB#44>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#44 BB#43

3760B	BB#43: derived from LLVM BB %if.then.87
	    Predecessors according to CFG: BB#42
3776B		%vreg155<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%ret] GR32:%vreg155
3792B		%vreg154<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg154
3808B		MOV32mr %vreg154, 1, %noreg, 0, %noreg, %vreg155; mem:ST4[%59] GR64:%vreg154 GR32:%vreg155
	    Successors according to CFG: BB#44

3824B	BB#44: derived from LLVM BB %if.end.88
	    Predecessors according to CFG: BB#42 BB#43
3840B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
3856B		JE_1 <BB#46>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#46 BB#45

3872B	BB#45: derived from LLVM BB %if.then.91
	    Predecessors according to CFG: BB#44
3888B		%vreg160<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%ret] GR32:%vreg160
3904B		%vreg159<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg159
3920B		MOV32mr %vreg159, 1, %noreg, 5096, %noreg, %vreg160; mem:ST4[%lastErr92] GR64:%vreg159 GR32:%vreg160
	    Successors according to CFG: BB#46

3936B	BB#46: derived from LLVM BB %if.end.93
	    Predecessors according to CFG: BB#44 BB#45
3952B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
3968B		JMP_1 <BB#69>
	    Successors according to CFG: BB#69

3984B	BB#47: derived from LLVM BB %if.end.94
	    Predecessors according to CFG: BB#40 BB#41
4000B		CMP32mi8 <fi#6>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%ret]
4016B		JNE_1 <BB#56>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#56 BB#48

4032B	BB#48: derived from LLVM BB %land.lhs.true.97
	    Predecessors according to CFG: BB#47
4048B		%vreg113<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg113
4064B		%vreg112<def> = MOV64rm %vreg113, 1, %noreg, 0, %noreg; mem:LD8[%handle98] GR64:%vreg112,%vreg113
4080B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4096B		%RDI<def> = COPY %vreg112; GR64:%vreg112
4112B		CALL64pcrel32 <ga:@myfeof>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %AL<imp-def>
4128B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4144B		%vreg110<def> = COPY %AL<kill>; GR8:%vreg110
4160B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4176B		STACKMAP 6, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
4192B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4208B		%vreg108<def> = MOVZX32rr8 %vreg110; GR32:%vreg108 GR8:%vreg110
4224B		CMP32ri8 %vreg108, 0, %EFLAGS<imp-def>; GR32:%vreg108
4240B		JE_1 <BB#56>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#56 BB#49

4256B	BB#49: derived from LLVM BB %land.lhs.true.102
	    Predecessors according to CFG: BB#48
4272B		%vreg116<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg116
4288B		CMP32mi8 %vreg116, 1, %noreg, 5024, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_in104] GR64:%vreg116
4304B		JNE_1 <BB#56>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#56 BB#50

4320B	BB#50: derived from LLVM BB %land.lhs.true.107
	    Predecessors according to CFG: BB#49
4336B		%vreg119<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg119
4352B		CMP32mi8 %vreg119, 1, %noreg, 5048, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_out109] GR64:%vreg119
4368B		JBE_1 <BB#56>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#56 BB#51

4384B	BB#51: derived from LLVM BB %if.then.112
	    Predecessors according to CFG: BB#50
4400B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
4416B		JE_1 <BB#53>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#53 BB#52

4432B	BB#52: derived from LLVM BB %if.then.115
	    Predecessors according to CFG: BB#51
4448B		%vreg147<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg147
4464B		MOV32mi %vreg147, 1, %noreg, 0, %noreg, -7; mem:ST4[%71] GR64:%vreg147
	    Successors according to CFG: BB#53

4480B	BB#53: derived from LLVM BB %if.end.116
	    Predecessors according to CFG: BB#51 BB#52
4496B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
4512B		JE_1 <BB#55>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#55 BB#54

4528B	BB#54: derived from LLVM BB %if.then.119
	    Predecessors according to CFG: BB#53
4544B		%vreg150<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg150
4560B		MOV32mi %vreg150, 1, %noreg, 5096, %noreg, -7; mem:ST4[%lastErr120] GR64:%vreg150
	    Successors according to CFG: BB#55

4576B	BB#55: derived from LLVM BB %if.end.121
	    Predecessors according to CFG: BB#53 BB#54
4592B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
4608B		JMP_1 <BB#69>
	    Successors according to CFG: BB#69

4624B	BB#56: derived from LLVM BB %if.end.122
	    Predecessors according to CFG: BB#47 BB#48 BB#49 BB#50
4640B		CMP32mi8 <fi#6>, 1, %noreg, 0, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%ret]
4656B		JNE_1 <BB#62>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#62 BB#57

4672B	BB#57: derived from LLVM BB %if.then.125
	    Predecessors according to CFG: BB#56
4688B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
4704B		JE_1 <BB#59>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#59 BB#58

4720B	BB#58: derived from LLVM BB %if.then.128
	    Predecessors according to CFG: BB#57
4736B		%vreg134<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg134
4752B		MOV32mi %vreg134, 1, %noreg, 0, %noreg, 4; mem:ST4[%76] GR64:%vreg134
	    Successors according to CFG: BB#59

4768B	BB#59: derived from LLVM BB %if.end.129
	    Predecessors according to CFG: BB#57 BB#58
4784B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
4800B		JE_1 <BB#61>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#61 BB#60

4816B	BB#60: derived from LLVM BB %if.then.132
	    Predecessors according to CFG: BB#59
4832B		%vreg137<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg137
4848B		MOV32mi %vreg137, 1, %noreg, 5096, %noreg, 4; mem:ST4[%lastErr133] GR64:%vreg137
	    Successors according to CFG: BB#61

4864B	BB#61: derived from LLVM BB %if.end.134
	    Predecessors according to CFG: BB#59 BB#60
4880B		%vreg144<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%len.addr] GR32:%vreg144
4896B		%vreg143<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg143
4912B		%vreg141<def> = COPY %vreg144; GR32:%vreg141,%vreg144
4928B		%vreg141<def,tied1> = SUB32rm %vreg141<tied0>, %vreg143, 1, %noreg, 5048, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%avail_out136] GR32:%vreg141 GR64:%vreg143
4944B		MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %vreg141; mem:ST4[%retval] GR32:%vreg141
4960B		JMP_1 <BB#69>
	    Successors according to CFG: BB#69

4976B	BB#62: derived from LLVM BB %if.end.137
	    Predecessors according to CFG: BB#56
4992B		%vreg123<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg123
5008B		CMP32mi8 %vreg123, 1, %noreg, 5048, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_out139] GR64:%vreg123
5024B		JNE_1 <BB#68>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#68 BB#63

5040B	BB#63: derived from LLVM BB %if.then.142
	    Predecessors according to CFG: BB#62
5056B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
5072B		JE_1 <BB#65>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#65 BB#64

5088B	BB#64: derived from LLVM BB %if.then.145
	    Predecessors according to CFG: BB#63
5104B		%vreg126<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg126
5120B		MOV32mi %vreg126, 1, %noreg, 0, %noreg, 0; mem:ST4[%85] GR64:%vreg126
	    Successors according to CFG: BB#65

5136B	BB#65: derived from LLVM BB %if.end.146
	    Predecessors according to CFG: BB#63 BB#64
5152B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
5168B		JE_1 <BB#67>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#67 BB#66

5184B	BB#66: derived from LLVM BB %if.then.149
	    Predecessors according to CFG: BB#65
5200B		%vreg129<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg129
5216B		MOV32mi %vreg129, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr150] GR64:%vreg129
	    Successors according to CFG: BB#67

5232B	BB#67: derived from LLVM BB %if.end.151
	    Predecessors according to CFG: BB#65 BB#66
5248B		%vreg131<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%len.addr] GR32:%vreg131
5264B		MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %vreg131; mem:ST4[%retval] GR32:%vreg131
5280B		JMP_1 <BB#69>
	    Successors according to CFG: BB#69

5296B	BB#68: derived from LLVM BB %if.end.152
	    Predecessors according to CFG: BB#62
5312B		JMP_1 <BB#25>
	    Successors according to CFG: BB#25

5328B	BB#69: derived from LLVM BB %return
	    Predecessors according to CFG: BB#38 BB#67 BB#61 BB#55 BB#46 BB#30 BB#23 BB#17 BB#11
5344B		%vreg187<def> = MOV64ri <ga:@BZ2_bzRead>; GR64:%vreg187
5360B		%vreg188<def> = COPY %vreg187; GR64:%vreg188,%vreg187
5376B		%vreg189<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg189
5392B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5408B		%RDI<def> = COPY %vreg188; GR64:%vreg188
5424B		%RSI<def> = COPY %vreg189; GR64:%vreg189
5440B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
5456B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5472B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5488B		STACKMAP 7, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
5504B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5520B		%vreg186<def> = MOV32rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD4[%retval] GR32:%vreg186
5536B		%EAX<def> = COPY %vreg186; GR32:%vreg186
5552B		RETQ %EAX<imp-use,kill>

# End machine code for function BZ2_bzRead.

********** SIMPLE REGISTER COALESCING **********
********** Function: BZ2_bzRead
********** JOINING INTERVALS ***********
if.end.122:
if.end.76:
3504B	%RDI<def> = COPY %vreg102; GR64:%vreg102
	Considering merging %vreg102 with %RDI
	Can only merge into reserved registers.
3552B	%vreg100<def> = COPY %EAX<kill>; GR32:%vreg100
	Considering merging %vreg100 with %EAX
	Can only merge into reserved registers.
while.body:
1760B	%RDI<def> = COPY %vreg40; GR64:%vreg40
	Considering merging %vreg40 with %RDI
	Can only merge into reserved registers.
1808B	%vreg38<def> = COPY %EAX<kill>; GR32:%vreg38
	Considering merging %vreg38 with %EAX
	Can only merge into reserved registers.
if.end.94:
if.end.46:
land.lhs.true:
2272B	%RDI<def> = COPY %vreg49; GR64:%vreg49
	Considering merging %vreg49 with %RDI
	Can only merge into reserved registers.
2320B	%vreg47<def> = COPY %AL<kill>; GR8:%vreg47
	Considering merging %vreg47 with %AL
	Can only merge into reserved registers.
if.then.52:
2448B	%vreg62<def> = SUBREG_TO_REG 0, %vreg61, 4; GR64:%vreg62 GR32:%vreg61
	Considering merging to GR64_with_sub_8bit with %vreg61 in %vreg62:sub_32bit
		RHS = %vreg61 [2432r,2448r:0)  0@2432r
		LHS = %vreg62 [2448r,2608r:0)  0@2448r
		merge %vreg62:0@2448r into %vreg61:0@2432r --> @2432r
		erased:	2448r	%vreg62<def> = SUBREG_TO_REG 0, %vreg61, 4; GR64:%vreg62 GR32:%vreg61
		updated: 2432B	%vreg62:sub_32bit<def,read-undef> = MOV32ri 1; GR64_with_sub_8bit:%vreg62
	Success: %vreg61:sub_32bit -> %vreg62
	Result = %vreg62 [2432r,2608r:0)  0@2432r
2480B	%vreg64<def> = SUBREG_TO_REG 0, %vreg63, 4; GR64:%vreg64 GR32:%vreg63
	Considering merging to GR64_with_sub_8bit with %vreg63 in %vreg64:sub_32bit
		RHS = %vreg63 [2464r,2480r:0)  0@2464r
		LHS = %vreg64 [2480r,2624r:0)  0@2480r
		merge %vreg64:0@2480r into %vreg63:0@2464r --> @2464r
		erased:	2480r	%vreg64<def> = SUBREG_TO_REG 0, %vreg63, 4; GR64:%vreg64 GR32:%vreg63
		updated: 2464B	%vreg64:sub_32bit<def,read-undef> = MOV32ri 5000; GR64_with_sub_8bit:%vreg64
	Success: %vreg63:sub_32bit -> %vreg64
	Result = %vreg64 [2464r,2624r:0)  0@2464r
2592B	%RDI<def> = COPY %vreg72; GR64:%vreg72
	Considering merging %vreg72 with %RDI
	Can only merge into reserved registers.
2608B	%RSI<def> = COPY %vreg62; GR64_with_sub_8bit:%vreg62
	Considering merging %vreg62 with %RSI
	Can only merge into reserved registers.
Remat: %ESI<def,dead> = MOV32ri 1, %RSI<imp-def>
Shrink: %vreg62 [2432r,2608r:0)  0@2432r
All defs dead: 2432r	%vreg62:sub_32bit<def,read-undef,dead> = MOV32ri 1; GR64_with_sub_8bit:%vreg62
Shrunk: %vreg62 [2432r,2432d:0)  0@2432r
Deleting dead def 2432r	%vreg62:sub_32bit<def,read-undef,dead> = MOV32ri 1; GR64_with_sub_8bit:%vreg62
2624B	%RDX<def> = COPY %vreg64; GR64_with_sub_8bit:%vreg64
	Considering merging %vreg64 with %RDX
	Can only merge into reserved registers.
Remat: %EDX<def,dead> = MOV32ri 5000, %RDX<imp-def>
Shrink: %vreg64 [2464r,2624r:0)  0@2464r
All defs dead: 2464r	%vreg64:sub_32bit<def,read-undef,dead> = MOV32ri 5000; GR64_with_sub_8bit:%vreg64
Shrunk: %vreg64 [2464r,2464d:0)  0@2464r
Deleting dead def 2464r	%vreg64:sub_32bit<def,read-undef,dead> = MOV32ri 5000; GR64_with_sub_8bit:%vreg64
2640B	%RCX<def> = COPY %vreg68; GR64:%vreg68
	Considering merging %vreg68 with %RCX
	Can only merge into reserved registers.
2688B	%vreg66<def> = COPY %RAX<kill>; GR64:%vreg66
	Considering merging %vreg66 with %RAX
	Can only merge into reserved registers.
2832B	%RDI<def> = COPY %vreg55; GR64:%vreg55
	Considering merging %vreg55 with %RDI
	Can only merge into reserved registers.
2880B	%vreg53<def> = COPY %EAX<kill>; GR32:%vreg53
	Considering merging %vreg53 with %EAX
	Can only merge into reserved registers.
land.lhs.true.81:
land.lhs.true.97:
4096B	%RDI<def> = COPY %vreg112; GR64:%vreg112
	Considering merging %vreg112 with %RDI
	Can only merge into reserved registers.
4144B	%vreg110<def> = COPY %AL<kill>; GR8:%vreg110
	Considering merging %vreg110 with %AL
	Can only merge into reserved registers.
land.lhs.true.102:
land.lhs.true.107:
if.end.137:
if.end.69:
if.end.152:
3456B	%vreg102<def> = COPY %vreg103; GR64:%vreg102,%vreg103
	Considering merging to GR64 with %vreg103 in %vreg102
		RHS = %vreg103 [3440r,3456r:0)  0@3440r
		LHS = %vreg102 [3456r,3472r:0)[3472r,3504r:1)  0@3456r 1@3472r
		merge %vreg102:0@3456r into %vreg103:0@3440r --> @3440r
		erased:	3456r	%vreg102<def> = COPY %vreg103; GR64:%vreg102,%vreg103
		updated: 3440B	%vreg102<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg102
	Success: %vreg103 -> %vreg102
	Result = %vreg102 [3440r,3472r:0)[3472r,3504r:1)  0@3440r 1@3472r
2512B	%vreg72<def> = COPY %vreg73; GR64:%vreg72,%vreg73
	Considering merging to GR64 with %vreg73 in %vreg72
		RHS = %vreg73 [2496r,2512r:0)  0@2496r
		LHS = %vreg72 [2512r,2528r:0)[2528r,2592r:1)  0@2512r 1@2528r
		merge %vreg72:0@2512r into %vreg73:0@2496r --> @2496r
		erased:	2512r	%vreg72<def> = COPY %vreg73; GR64:%vreg72,%vreg73
		updated: 2496B	%vreg72<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg72
	Success: %vreg73 -> %vreg72
	Result = %vreg72 [2496r,2528r:0)[2528r,2592r:1)  0@2496r 1@2528r
2752B	%vreg59<def> = COPY %vreg66:sub_32bit; GR32:%vreg59 GR64:%vreg66
	Considering merging to GR64_with_sub_8bit with %vreg59 in %vreg66:sub_32bit
		RHS = %vreg59 [2752r,2768r:0)  0@2752r
		LHS = %vreg66 [2688r,2752r:0)  0@2688r
		merge %vreg59:0@2752r into %vreg66:0@2688r --> @2688r
		erased:	2752r	%vreg59<def> = COPY %vreg66:sub_32bit; GR32:%vreg59 GR64:%vreg66
		updated: 2768B	MOV32mr <fi#5>, 1, %noreg, 0, %noreg, %vreg66:sub_32bit; mem:ST4[%n] GR64_with_sub_8bit:%vreg66
	Success: %vreg59:sub_32bit -> %vreg66
	Result = %vreg66 [2688r,2768r:0)  0@2688r
3360B	%vreg79<def> = COPY %vreg80; GR64:%vreg79,%vreg80
	Considering merging to GR64 with %vreg80 in %vreg79
		RHS = %vreg80 [3344r,3360r:0)  0@3344r
		LHS = %vreg79 [3360r,3376r:0)[3376r,3408r:1)  0@3360r 1@3376r
		merge %vreg79:0@3360r into %vreg80:0@3344r --> @3344r
		erased:	3360r	%vreg79<def> = COPY %vreg80; GR64:%vreg79,%vreg80
		updated: 3344B	%vreg79<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg79
	Success: %vreg80 -> %vreg79
	Result = %vreg79 [3344r,3376r:0)[3376r,3408r:1)  0@3344r 1@3376r
return:
5408B	%RDI<def> = COPY %vreg188; GR64:%vreg188
	Considering merging %vreg188 with %RDI
	Can only merge into reserved registers.
5424B	%RSI<def> = COPY %vreg189; GR64:%vreg189
	Considering merging %vreg189 with %RSI
	Can only merge into reserved registers.
5536B	%EAX<def> = COPY %vreg186; GR32:%vreg186
	Considering merging %vreg186 with %EAX
	Can only merge into reserved registers.
if.then.8:
if.end:
if.end.3:
if.end.11:
if.end.20:
if.end.30:
if.end.41:
if.end.63:
if.end.88:
if.end.116:
if.end.129:
if.end.146:
lor.lhs.false:
lor.lhs.false.6:
if.end.15:
if.end.16:
if.then.17:
if.end.24:
if.end.25:
if.then.27:
if.end.34:
if.then.38:
if.end.45:
if.then.59:
if.end.68:
if.then.84:
if.end.93:
if.then.112:
if.end.121:
if.then.125:
if.end.134:
if.then.142:
if.end.151:
entry:
16B	%vreg6<def> = COPY %ECX; GR32:%vreg6
	Considering merging %vreg6 with %ECX
	Can only merge into reserved registers.
32B	%vreg4<def> = COPY %RDX; GR64:%vreg4
	Considering merging %vreg4 with %RDX
	Can only merge into reserved registers.
48B	%vreg2<def> = COPY %RSI; GR64:%vreg2
	Considering merging %vreg2 with %RSI
	Can only merge into reserved registers.
64B	%vreg0<def> = COPY %RDI; GR64:%vreg0
	Considering merging %vreg0 with %RDI
	Can only merge into reserved registers.
208B	%RDI<def> = COPY %vreg14; GR64:%vreg14
	Considering merging %vreg14 with %RDI
	Can only merge into reserved registers.
224B	%RSI<def> = COPY %vreg15; GR64:%vreg15
	Considering merging %vreg15 with %RSI
	Can only merge into reserved registers.
if.then:
if.then.2:
if.then.10:
if.then.13:
if.then.19:
if.then.22:
if.then.29:
if.then.32:
if.end.35:
if.then.40:
if.then.43:
if.then.62:
if.then.66:
if.then.87:
if.then.91:
if.then.115:
if.then.119:
if.then.128:
if.then.132:
if.then.145:
if.then.149:
5360B	%vreg188<def> = COPY %vreg187; GR64:%vreg188,%vreg187
	Considering merging to GR64 with %vreg187 in %vreg188
		RHS = %vreg187 [5344r,5360r:0)  0@5344r
		LHS = %vreg188 [5360r,5408r:0)  0@5360r
		merge %vreg188:0@5360r into %vreg187:0@5344r --> @5344r
		erased:	5360r	%vreg188<def> = COPY %vreg187; GR64:%vreg188,%vreg187
		updated: 5344B	%vreg188<def> = MOV64ri <ga:@BZ2_bzRead>; GR64:%vreg188
	Success: %vreg187 -> %vreg188
	Result = %vreg188 [5344r,5408r:0)  0@5344r
4912B	%vreg141<def> = COPY %vreg144; GR32:%vreg141,%vreg144
	Considering merging to GR32 with %vreg144 in %vreg141
		RHS = %vreg144 [4880r,4912r:0)  0@4880r
		LHS = %vreg141 [4912r,4928r:0)[4928r,4944r:1)  0@4912r 1@4928r
		merge %vreg141:0@4912r into %vreg144:0@4880r --> @4880r
		erased:	4912r	%vreg141<def> = COPY %vreg144; GR32:%vreg141,%vreg144
		updated: 4880B	%vreg141<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%len.addr] GR32:%vreg141
	Success: %vreg144 -> %vreg141
	Result = %vreg141 [4880r,4928r:0)[4928r,4944r:1)  0@4880r 1@4928r
80B	%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
	Considering merging to GR64 with %vreg0 in %vreg1
		RHS = %vreg0 [64r,80r:0)  0@64r
		LHS = %vreg1 [80r,320r:0)  0@80r
		merge %vreg1:0@80r into %vreg0:0@64r --> @64r
		erased:	80r	%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
		updated: 64B	%vreg1<def> = COPY %RDI; GR64:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [64r,320r:0)  0@64r
96B	%vreg3<def> = COPY %vreg2; GR64:%vreg3,%vreg2
	Considering merging to GR64 with %vreg2 in %vreg3
		RHS = %vreg2 [48r,96r:0)  0@48r
		LHS = %vreg3 [96r,336r:0)  0@96r
		merge %vreg3:0@96r into %vreg2:0@48r --> @48r
		erased:	96r	%vreg3<def> = COPY %vreg2; GR64:%vreg3,%vreg2
		updated: 48B	%vreg3<def> = COPY %RSI; GR64:%vreg3
	Success: %vreg2 -> %vreg3
	Result = %vreg3 [48r,336r:0)  0@48r
112B	%vreg5<def> = COPY %vreg4; GR64:%vreg5,%vreg4
	Considering merging to GR64 with %vreg4 in %vreg5
		RHS = %vreg4 [32r,112r:0)  0@32r
		LHS = %vreg5 [112r,352r:0)  0@112r
		merge %vreg5:0@112r into %vreg4:0@32r --> @32r
		erased:	112r	%vreg5<def> = COPY %vreg4; GR64:%vreg5,%vreg4
		updated: 32B	%vreg5<def> = COPY %RDX; GR64:%vreg5
	Success: %vreg4 -> %vreg5
	Result = %vreg5 [32r,352r:0)  0@32r
128B	%vreg7<def> = COPY %vreg6; GR32:%vreg7,%vreg6
	Considering merging to GR32 with %vreg6 in %vreg7
		RHS = %vreg6 [16r,128r:0)  0@16r
		LHS = %vreg7 [128r,368r:0)  0@128r
		merge %vreg7:0@128r into %vreg6:0@16r --> @16r
		erased:	128r	%vreg7<def> = COPY %vreg6; GR32:%vreg7,%vreg6
		updated: 16B	%vreg7<def> = COPY %ECX; GR32:%vreg7
	Success: %vreg6 -> %vreg7
	Result = %vreg7 [16r,368r:0)  0@16r
160B	%vreg14<def> = COPY %vreg13; GR64:%vreg14,%vreg13
	Considering merging to GR64 with %vreg13 in %vreg14
		RHS = %vreg13 [144r,160r:0)  0@144r
		LHS = %vreg14 [160r,208r:0)  0@160r
		merge %vreg14:0@160r into %vreg13:0@144r --> @144r
		erased:	160r	%vreg14<def> = COPY %vreg13; GR64:%vreg14,%vreg13
		updated: 144B	%vreg14<def> = MOV64ri <ga:@BZ2_bzRead>; GR64:%vreg14
	Success: %vreg13 -> %vreg14
	Result = %vreg14 [144r,208r:0)  0@144r
400B	%vreg11<def> = COPY %vreg12; GR64:%vreg11,%vreg12
	Considering merging to GR64 with %vreg12 in %vreg11
		RHS = %vreg12 [384r,400r:0)  0@384r
		LHS = %vreg11 [400r,416r:0)  0@400r
		merge %vreg11:0@400r into %vreg12:0@384r --> @384r
		erased:	400r	%vreg11<def> = COPY %vreg12; GR64:%vreg11,%vreg12
		updated: 384B	%vreg11<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr] GR64:%vreg11
	Success: %vreg12 -> %vreg11
	Result = %vreg11 [384r,416r:0)  0@384r
5408B	%RDI<def> = COPY %vreg188; GR64:%vreg188
	Considering merging %vreg188 with %RDI
	Can only merge into reserved registers.
208B	%RDI<def> = COPY %vreg14; GR64:%vreg14
	Considering merging %vreg14 with %RDI
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
CH [0B,16r:0)[2640r,2656r:1)  0@0B-phi 1@2640r
CL [0B,16r:0)[2640r,2656r:1)  0@0B-phi 1@2640r
DH [0B,32r:0)[2624r,2656r:1)  0@0B-phi 1@2624r
DIL [0B,64r:0)[208r,240r:8)[1760r,1776r:7)[2272r,2288r:6)[2592r,2656r:4)[2832r,2848r:5)[3504r,3520r:3)[4096r,4112r:2)[5408r,5440r:1)  0@0B-phi 1@5408r 2@4096r 3@3504r 4@2592r 5@2832r 6@2272r 7@1760r 8@208r
DL [0B,32r:0)[2624r,2656r:1)  0@0B-phi 1@2624r
SIL [0B,48r:0)[224r,240r:3)[2608r,2656r:2)[5424r,5440r:1)  0@0B-phi 1@5424r 2@2608r 3@224r
%vreg1 [64r,320r:0)  0@64r
%vreg3 [48r,336r:0)  0@48r
%vreg5 [32r,352r:0)  0@32r
%vreg7 [16r,368r:0)  0@16r
%vreg11 [384r,416r:0)  0@384r
%vreg14 [144r,208r:0)  0@144r
%vreg15 [176r,224r:0)  0@176r
%vreg17 [480r,496r:0)  0@480r
%vreg20 [576r,592r:0)  0@576r
%vreg26 [1008r,1024r:0)  0@1008r
%vreg30 [1664r,1680r:0)  0@1664r
%vreg31 [1648r,1680r:0)  0@1648r
%vreg34 [1616r,1632r:0)  0@1616r
%vreg35 [1600r,1632r:0)  0@1600r
%vreg38 [1808r,1872r:0)  0@1808r
%vreg40 [1728r,1760r:0)  0@1728r
%vreg41 [1712r,1728r:0)  0@1712r
%vreg44 [2160r,2176r:0)  0@2160r
%vreg47 [2320r,2384r:0)  0@2320r
%vreg49 [2240r,2272r:0)  0@2240r
%vreg50 [2224r,2240r:0)  0@2224r
%vreg53 [2880r,2944r:0)  0@2880r
%vreg55 [2800r,2832r:0)  0@2800r
%vreg56 [2784r,2800r:0)  0@2784r
%vreg66 [2688r,2768r:0)  0@2688r
%vreg68 [2560r,2640r:0)  0@2560r
%vreg69 [2544r,2560r:0)  0@2544r
%vreg72 [2496r,2528r:0)[2528r,2592r:1)  0@2496r 1@2528r
%vreg76 [3392r,3408r:0)  0@3392r
%vreg79 [3344r,3376r:0)[3376r,3408r:1)  0@3344r 1@3376r
%vreg83 [3312r,3328r:0)  0@3312r
%vreg85 [3296r,3328r:0)  0@3296r
%vreg86 [3280r,3296r:0)  0@3280r
%vreg89 [3248r,3264r:0)  0@3248r
%vreg90 [3232r,3264r:0)  0@3232r
%vreg93 [3040r,3056r:0)  0@3040r
%vreg96 [3136r,3152r:0)  0@3136r
%vreg100 [3552r,3616r:0)  0@3552r
%vreg102 [3440r,3472r:0)[3472r,3504r:1)  0@3440r 1@3472r
%vreg108 [4208r,4224r:0)  0@4208r
%vreg110 [4144r,4208r:0)  0@4144r
%vreg112 [4064r,4096r:0)  0@4064r
%vreg113 [4048r,4064r:0)  0@4048r
%vreg116 [4272r,4288r:0)  0@4272r
%vreg119 [4336r,4352r:0)  0@4336r
%vreg123 [4992r,5008r:0)  0@4992r
%vreg126 [5104r,5120r:0)  0@5104r
%vreg129 [5200r,5216r:0)  0@5200r
%vreg131 [5248r,5264r:0)  0@5248r
%vreg134 [4736r,4752r:0)  0@4736r
%vreg137 [4832r,4848r:0)  0@4832r
%vreg141 [4880r,4928r:0)[4928r,4944r:1)  0@4880r 1@4928r
%vreg143 [4896r,4928r:0)  0@4896r
%vreg147 [4448r,4464r:0)  0@4448r
%vreg150 [4544r,4560r:0)  0@4544r
%vreg154 [3792r,3808r:0)  0@3792r
%vreg155 [3776r,3808r:0)  0@3776r
%vreg159 [3904r,3920r:0)  0@3904r
%vreg160 [3888r,3920r:0)  0@3888r
%vreg163 [1968r,1984r:0)  0@1968r
%vreg166 [2064r,2080r:0)  0@2064r
%vreg169 [1408r,1424r:0)  0@1408r
%vreg172 [1504r,1520r:0)  0@1504r
%vreg175 [1120r,1136r:0)  0@1120r
%vreg178 [1216r,1232r:0)  0@1216r
%vreg181 [816r,832r:0)  0@816r
%vreg184 [912r,928r:0)  0@912r
%vreg186 [5520r,5536r:0)  0@5520r
%vreg188 [5344r,5408r:0)  0@5344r
%vreg189 [5376r,5424r:0)  0@5376r
RegMasks: 240r 1776r 2288r 2656r 2848r 3520r 4112r 5440r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzRead: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=4, align=4, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=8, align=8, at location [SP+8]
  fi#3: size=8, align=8, at location [SP+8]
  fi#4: size=4, align=4, at location [SP+8]
  fi#5: size=4, align=4, at location [SP+8]
  fi#6: size=4, align=4, at location [SP+8]
  fi#7: size=8, align=8, at location [SP+8]
Function Live Ins: %RDI in %vreg0, %RSI in %vreg2, %RDX in %vreg4, %ECX in %vreg6

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI %RSI %RDX %ECX
16B		%vreg7<def> = COPY %ECX; GR32:%vreg7
32B		%vreg5<def> = COPY %RDX; GR64:%vreg5
48B		%vreg3<def> = COPY %RSI; GR64:%vreg3
64B		%vreg1<def> = COPY %RDI; GR64:%vreg1
144B		%vreg14<def> = MOV64ri <ga:@BZ2_bzRead>; GR64:%vreg14
176B		%vreg15<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg15
192B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
208B		%RDI<def> = COPY %vreg14; GR64:%vreg14
224B		%RSI<def> = COPY %vreg15; GR64:%vreg15
240B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
256B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
272B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
288B		STACKMAP 0, 0, %vreg3, 0, <fi#2>, 0, %vreg5, 0, <fi#3>, 0, %vreg1, 0, <fi#1>, 0, 0, <fi#7>, 0, %vreg7, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack2] LD8[FixedStack3] LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4) GR64:%vreg3,%vreg5,%vreg1 GR32:%vreg7
304B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
320B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%bzerror.addr] GR64:%vreg1
336B		MOV64mr <fi#2>, 1, %noreg, 0, %noreg, %vreg3; mem:ST8[%b.addr] GR64:%vreg3
352B		MOV64mr <fi#3>, 1, %noreg, 0, %noreg, %vreg5; mem:ST8[%buf.addr] GR64:%vreg5
368B		MOV32mr <fi#4>, 1, %noreg, 0, %noreg, %vreg7; mem:ST4[%len.addr] GR32:%vreg7
384B		%vreg11<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr] GR64:%vreg11
416B		MOV64mr <fi#7>, 1, %noreg, 0, %noreg, %vreg11; mem:ST8[%bzf] GR64:%vreg11
432B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
448B		JE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

464B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
480B		%vreg17<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg17
496B		MOV32mi %vreg17, 1, %noreg, 0, %noreg, 0; mem:ST4[%3] GR64:%vreg17
	    Successors according to CFG: BB#2

512B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#1
528B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
544B		JE_1 <BB#4>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#4 BB#3

560B	BB#3: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#2
576B		%vreg20<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg20
592B		MOV32mi %vreg20, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr] GR64:%vreg20
	    Successors according to CFG: BB#4

608B	BB#4: derived from LLVM BB %if.end.3
	    Predecessors according to CFG: BB#2 BB#3
624B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
640B		JE_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#5

656B	BB#5: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#4
672B		CMP64mi8 <fi#3>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%buf.addr]
688B		JE_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#6

704B	BB#6: derived from LLVM BB %lor.lhs.false.6
	    Predecessors according to CFG: BB#5
720B		CMP32mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%len.addr]
736B		JGE_1 <BB#12>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#12 BB#7

752B	BB#7: derived from LLVM BB %if.then.8
	    Predecessors according to CFG: BB#4 BB#5 BB#6
768B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
784B		JE_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#8

800B	BB#8: derived from LLVM BB %if.then.10
	    Predecessors according to CFG: BB#7
816B		%vreg181<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg181
832B		MOV32mi %vreg181, 1, %noreg, 0, %noreg, -2; mem:ST4[%10] GR64:%vreg181
	    Successors according to CFG: BB#9

848B	BB#9: derived from LLVM BB %if.end.11
	    Predecessors according to CFG: BB#7 BB#8
864B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
880B		JE_1 <BB#11>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#11 BB#10

896B	BB#10: derived from LLVM BB %if.then.13
	    Predecessors according to CFG: BB#9
912B		%vreg184<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg184
928B		MOV32mi %vreg184, 1, %noreg, 5096, %noreg, -2; mem:ST4[%lastErr14] GR64:%vreg184
	    Successors according to CFG: BB#11

944B	BB#11: derived from LLVM BB %if.end.15
	    Predecessors according to CFG: BB#9 BB#10
960B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
976B		JMP_1 <BB#69>
	    Successors according to CFG: BB#69

992B	BB#12: derived from LLVM BB %if.end.16
	    Predecessors according to CFG: BB#6
1008B		%vreg26<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg26
1024B		CMP8mi %vreg26, 1, %noreg, 5012, %noreg, 0, %EFLAGS<imp-def>; mem:LD1[%writing] GR64:%vreg26
1040B		JE_1 <BB#18>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#18 BB#13

1056B	BB#13: derived from LLVM BB %if.then.17
	    Predecessors according to CFG: BB#12
1072B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
1088B		JE_1 <BB#15>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#15 BB#14

1104B	BB#14: derived from LLVM BB %if.then.19
	    Predecessors according to CFG: BB#13
1120B		%vreg175<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg175
1136B		MOV32mi %vreg175, 1, %noreg, 0, %noreg, -1; mem:ST4[%16] GR64:%vreg175
	    Successors according to CFG: BB#15

1152B	BB#15: derived from LLVM BB %if.end.20
	    Predecessors according to CFG: BB#13 BB#14
1168B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
1184B		JE_1 <BB#17>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#17 BB#16

1200B	BB#16: derived from LLVM BB %if.then.22
	    Predecessors according to CFG: BB#15
1216B		%vreg178<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg178
1232B		MOV32mi %vreg178, 1, %noreg, 5096, %noreg, -1; mem:ST4[%lastErr23] GR64:%vreg178
	    Successors according to CFG: BB#17

1248B	BB#17: derived from LLVM BB %if.end.24
	    Predecessors according to CFG: BB#15 BB#16
1264B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
1280B		JMP_1 <BB#69>
	    Successors according to CFG: BB#69

1296B	BB#18: derived from LLVM BB %if.end.25
	    Predecessors according to CFG: BB#12
1312B		CMP32mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%len.addr]
1328B		JNE_1 <BB#24>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#24 BB#19

1344B	BB#19: derived from LLVM BB %if.then.27
	    Predecessors according to CFG: BB#18
1360B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
1376B		JE_1 <BB#21>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#21 BB#20

1392B	BB#20: derived from LLVM BB %if.then.29
	    Predecessors according to CFG: BB#19
1408B		%vreg169<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg169
1424B		MOV32mi %vreg169, 1, %noreg, 0, %noreg, 0; mem:ST4[%21] GR64:%vreg169
	    Successors according to CFG: BB#21

1440B	BB#21: derived from LLVM BB %if.end.30
	    Predecessors according to CFG: BB#19 BB#20
1456B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
1472B		JE_1 <BB#23>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#23 BB#22

1488B	BB#22: derived from LLVM BB %if.then.32
	    Predecessors according to CFG: BB#21
1504B		%vreg172<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg172
1520B		MOV32mi %vreg172, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr33] GR64:%vreg172
	    Successors according to CFG: BB#23

1536B	BB#23: derived from LLVM BB %if.end.34
	    Predecessors according to CFG: BB#21 BB#22
1552B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
1568B		JMP_1 <BB#69>
	    Successors according to CFG: BB#69

1584B	BB#24: derived from LLVM BB %if.end.35
	    Predecessors according to CFG: BB#18
1600B		%vreg35<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%len.addr] GR32:%vreg35
1616B		%vreg34<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg34
1632B		MOV32mr %vreg34, 1, %noreg, 5048, %noreg, %vreg35; mem:ST4[%avail_out] GR64:%vreg34 GR32:%vreg35
1648B		%vreg31<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%buf.addr] GR64:%vreg31
1664B		%vreg30<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg30
1680B		MOV64mr %vreg30, 1, %noreg, 5040, %noreg, %vreg31; mem:ST8[%next_out] GR64:%vreg30,%vreg31
	    Successors according to CFG: BB#25

1696B	BB#25: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#24 BB#68
1712B		%vreg41<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg41
1728B		%vreg40<def> = MOV64rm %vreg41, 1, %noreg, 0, %noreg; mem:LD8[%handle] GR64:%vreg40,%vreg41
1744B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1760B		%RDI<def> = COPY %vreg40; GR64:%vreg40
1776B		CALL64pcrel32 <ga:@ferror>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
1792B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1808B		%vreg38<def> = COPY %EAX<kill>; GR32:%vreg38
1824B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1840B		STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
1856B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1872B		CMP32ri8 %vreg38, 0, %EFLAGS<imp-def>; GR32:%vreg38
1888B		JE_1 <BB#31>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#31 BB#26

1904B	BB#26: derived from LLVM BB %if.then.38
	    Predecessors according to CFG: BB#25
1920B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
1936B		JE_1 <BB#28>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#28 BB#27

1952B	BB#27: derived from LLVM BB %if.then.40
	    Predecessors according to CFG: BB#26
1968B		%vreg163<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg163
1984B		MOV32mi %vreg163, 1, %noreg, 0, %noreg, -6; mem:ST4[%31] GR64:%vreg163
	    Successors according to CFG: BB#28

2000B	BB#28: derived from LLVM BB %if.end.41
	    Predecessors according to CFG: BB#26 BB#27
2016B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
2032B		JE_1 <BB#30>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#30 BB#29

2048B	BB#29: derived from LLVM BB %if.then.43
	    Predecessors according to CFG: BB#28
2064B		%vreg166<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg166
2080B		MOV32mi %vreg166, 1, %noreg, 5096, %noreg, -6; mem:ST4[%lastErr44] GR64:%vreg166
	    Successors according to CFG: BB#30

2096B	BB#30: derived from LLVM BB %if.end.45
	    Predecessors according to CFG: BB#28 BB#29
2112B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
2128B		JMP_1 <BB#69>
	    Successors according to CFG: BB#69

2144B	BB#31: derived from LLVM BB %if.end.46
	    Predecessors according to CFG: BB#25
2160B		%vreg44<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg44
2176B		CMP32mi8 %vreg44, 1, %noreg, 5024, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_in] GR64:%vreg44
2192B		JNE_1 <BB#40>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#40 BB#32

2208B	BB#32: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#31
2224B		%vreg50<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg50
2240B		%vreg49<def> = MOV64rm %vreg50, 1, %noreg, 0, %noreg; mem:LD8[%handle49] GR64:%vreg49,%vreg50
2256B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2272B		%RDI<def> = COPY %vreg49; GR64:%vreg49
2288B		CALL64pcrel32 <ga:@myfeof>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %AL<imp-def>
2304B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2320B		%vreg47<def> = COPY %AL<kill>; GR8:%vreg47
2336B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2352B		STACKMAP 2, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
2368B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2384B		CMP8ri %vreg47, 0, %EFLAGS<imp-def>; GR8:%vreg47
2400B		JNE_1 <BB#40>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#40 BB#33

2416B	BB#33: derived from LLVM BB %if.then.52
	    Predecessors according to CFG: BB#32
2496B		%vreg72<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg72
2528B		%vreg72<def,tied1> = ADD64ri8 %vreg72<tied0>, 8, %EFLAGS<imp-def,dead>; GR64:%vreg72
2544B		%vreg69<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg69
2560B		%vreg68<def> = MOV64rm %vreg69, 1, %noreg, 0, %noreg; mem:LD8[%handle54] GR64:%vreg68,%vreg69
2576B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2592B		%RDI<def> = COPY %vreg72; GR64:%vreg72
2608B		%ESI<def,dead> = MOV32ri 1, %RSI<imp-def>
2624B		%EDX<def,dead> = MOV32ri 5000, %RDX<imp-def>
2640B		%RCX<def> = COPY %vreg68; GR64:%vreg68
2656B		CALL64pcrel32 <ga:@fread>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %RDX<imp-use>, %RCX<imp-use>, %RAX<imp-def>
2672B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2688B		%vreg66<def> = COPY %RAX<kill>; GR64_with_sub_8bit:%vreg66
2704B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2720B		STACKMAP 3, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
2736B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2768B		MOV32mr <fi#5>, 1, %noreg, 0, %noreg, %vreg66:sub_32bit; mem:ST4[%n] GR64_with_sub_8bit:%vreg66
2784B		%vreg56<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg56
2800B		%vreg55<def> = MOV64rm %vreg56, 1, %noreg, 0, %noreg; mem:LD8[%handle56] GR64:%vreg55,%vreg56
2816B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2832B		%RDI<def> = COPY %vreg55; GR64:%vreg55
2848B		CALL64pcrel32 <ga:@ferror>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
2864B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2880B		%vreg53<def> = COPY %EAX<kill>; GR32:%vreg53
2896B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2912B		STACKMAP 4, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
2928B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2944B		CMP32ri8 %vreg53, 0, %EFLAGS<imp-def>; GR32:%vreg53
2960B		JE_1 <BB#39>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#39 BB#34

2976B	BB#34: derived from LLVM BB %if.then.59
	    Predecessors according to CFG: BB#33
2992B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
3008B		JE_1 <BB#36>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#36 BB#35

3024B	BB#35: derived from LLVM BB %if.then.62
	    Predecessors according to CFG: BB#34
3040B		%vreg93<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg93
3056B		MOV32mi %vreg93, 1, %noreg, 0, %noreg, -6; mem:ST4[%44] GR64:%vreg93
	    Successors according to CFG: BB#36

3072B	BB#36: derived from LLVM BB %if.end.63
	    Predecessors according to CFG: BB#34 BB#35
3088B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
3104B		JE_1 <BB#38>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#38 BB#37

3120B	BB#37: derived from LLVM BB %if.then.66
	    Predecessors according to CFG: BB#36
3136B		%vreg96<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg96
3152B		MOV32mi %vreg96, 1, %noreg, 5096, %noreg, -6; mem:ST4[%lastErr67] GR64:%vreg96
	    Successors according to CFG: BB#38

3168B	BB#38: derived from LLVM BB %if.end.68
	    Predecessors according to CFG: BB#36 BB#37
3184B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
3200B		JMP_1 <BB#69>
	    Successors according to CFG: BB#69

3216B	BB#39: derived from LLVM BB %if.end.69
	    Predecessors according to CFG: BB#33
3232B		%vreg90<def> = MOV32rm <fi#5>, 1, %noreg, 0, %noreg; mem:LD4[%n] GR32:%vreg90
3248B		%vreg89<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg89
3264B		MOV32mr %vreg89, 1, %noreg, 5008, %noreg, %vreg90; mem:ST4[%bufN] GR64:%vreg89 GR32:%vreg90
3280B		%vreg86<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg86
3296B		%vreg85<def> = MOV32rm %vreg86, 1, %noreg, 5008, %noreg; mem:LD4[%bufN70] GR32:%vreg85 GR64:%vreg86
3312B		%vreg83<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg83
3328B		MOV32mr %vreg83, 1, %noreg, 5024, %noreg, %vreg85; mem:ST4[%avail_in72] GR64:%vreg83 GR32:%vreg85
3344B		%vreg79<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg79
3376B		%vreg79<def,tied1> = ADD64ri8 %vreg79<tied0>, 8, %EFLAGS<imp-def,dead>; GR64:%vreg79
3392B		%vreg76<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg76
3408B		MOV64mr %vreg76, 1, %noreg, 5016, %noreg, %vreg79; mem:ST8[%next_in] GR64:%vreg76,%vreg79
	    Successors according to CFG: BB#40

3424B	BB#40: derived from LLVM BB %if.end.76
	    Predecessors according to CFG: BB#31 BB#32 BB#39
3440B		%vreg102<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg102
3472B		%vreg102<def,tied1> = ADD64ri32 %vreg102<tied0>, 5016, %EFLAGS<imp-def,dead>; GR64:%vreg102
3488B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3504B		%RDI<def> = COPY %vreg102; GR64:%vreg102
3520B		CALL64pcrel32 <ga:@BZ2_bzDecompress>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
3536B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3552B		%vreg100<def> = COPY %EAX<kill>; GR32:%vreg100
3568B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3584B		STACKMAP 5, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
3600B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3616B		MOV32mr <fi#6>, 1, %noreg, 0, %noreg, %vreg100; mem:ST4[%ret] GR32:%vreg100
3632B		CMP32mi8 <fi#6>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%ret]
3648B		JE_1 <BB#47>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#47 BB#41

3664B	BB#41: derived from LLVM BB %land.lhs.true.81
	    Predecessors according to CFG: BB#40
3680B		CMP32mi8 <fi#6>, 1, %noreg, 0, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%ret]
3696B		JE_1 <BB#47>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#47 BB#42

3712B	BB#42: derived from LLVM BB %if.then.84
	    Predecessors according to CFG: BB#41
3728B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
3744B		JE_1 <BB#44>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#44 BB#43

3760B	BB#43: derived from LLVM BB %if.then.87
	    Predecessors according to CFG: BB#42
3776B		%vreg155<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%ret] GR32:%vreg155
3792B		%vreg154<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg154
3808B		MOV32mr %vreg154, 1, %noreg, 0, %noreg, %vreg155; mem:ST4[%59] GR64:%vreg154 GR32:%vreg155
	    Successors according to CFG: BB#44

3824B	BB#44: derived from LLVM BB %if.end.88
	    Predecessors according to CFG: BB#42 BB#43
3840B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
3856B		JE_1 <BB#46>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#46 BB#45

3872B	BB#45: derived from LLVM BB %if.then.91
	    Predecessors according to CFG: BB#44
3888B		%vreg160<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%ret] GR32:%vreg160
3904B		%vreg159<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg159
3920B		MOV32mr %vreg159, 1, %noreg, 5096, %noreg, %vreg160; mem:ST4[%lastErr92] GR64:%vreg159 GR32:%vreg160
	    Successors according to CFG: BB#46

3936B	BB#46: derived from LLVM BB %if.end.93
	    Predecessors according to CFG: BB#44 BB#45
3952B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
3968B		JMP_1 <BB#69>
	    Successors according to CFG: BB#69

3984B	BB#47: derived from LLVM BB %if.end.94
	    Predecessors according to CFG: BB#40 BB#41
4000B		CMP32mi8 <fi#6>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%ret]
4016B		JNE_1 <BB#56>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#56 BB#48

4032B	BB#48: derived from LLVM BB %land.lhs.true.97
	    Predecessors according to CFG: BB#47
4048B		%vreg113<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg113
4064B		%vreg112<def> = MOV64rm %vreg113, 1, %noreg, 0, %noreg; mem:LD8[%handle98] GR64:%vreg112,%vreg113
4080B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4096B		%RDI<def> = COPY %vreg112; GR64:%vreg112
4112B		CALL64pcrel32 <ga:@myfeof>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %AL<imp-def>
4128B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4144B		%vreg110<def> = COPY %AL<kill>; GR8:%vreg110
4160B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4176B		STACKMAP 6, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
4192B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4208B		%vreg108<def> = MOVZX32rr8 %vreg110; GR32:%vreg108 GR8:%vreg110
4224B		CMP32ri8 %vreg108, 0, %EFLAGS<imp-def>; GR32:%vreg108
4240B		JE_1 <BB#56>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#56 BB#49

4256B	BB#49: derived from LLVM BB %land.lhs.true.102
	    Predecessors according to CFG: BB#48
4272B		%vreg116<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg116
4288B		CMP32mi8 %vreg116, 1, %noreg, 5024, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_in104] GR64:%vreg116
4304B		JNE_1 <BB#56>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#56 BB#50

4320B	BB#50: derived from LLVM BB %land.lhs.true.107
	    Predecessors according to CFG: BB#49
4336B		%vreg119<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg119
4352B		CMP32mi8 %vreg119, 1, %noreg, 5048, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_out109] GR64:%vreg119
4368B		JBE_1 <BB#56>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#56 BB#51

4384B	BB#51: derived from LLVM BB %if.then.112
	    Predecessors according to CFG: BB#50
4400B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
4416B		JE_1 <BB#53>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#53 BB#52

4432B	BB#52: derived from LLVM BB %if.then.115
	    Predecessors according to CFG: BB#51
4448B		%vreg147<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg147
4464B		MOV32mi %vreg147, 1, %noreg, 0, %noreg, -7; mem:ST4[%71] GR64:%vreg147
	    Successors according to CFG: BB#53

4480B	BB#53: derived from LLVM BB %if.end.116
	    Predecessors according to CFG: BB#51 BB#52
4496B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
4512B		JE_1 <BB#55>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#55 BB#54

4528B	BB#54: derived from LLVM BB %if.then.119
	    Predecessors according to CFG: BB#53
4544B		%vreg150<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg150
4560B		MOV32mi %vreg150, 1, %noreg, 5096, %noreg, -7; mem:ST4[%lastErr120] GR64:%vreg150
	    Successors according to CFG: BB#55

4576B	BB#55: derived from LLVM BB %if.end.121
	    Predecessors according to CFG: BB#53 BB#54
4592B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
4608B		JMP_1 <BB#69>
	    Successors according to CFG: BB#69

4624B	BB#56: derived from LLVM BB %if.end.122
	    Predecessors according to CFG: BB#47 BB#48 BB#49 BB#50
4640B		CMP32mi8 <fi#6>, 1, %noreg, 0, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%ret]
4656B		JNE_1 <BB#62>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#62 BB#57

4672B	BB#57: derived from LLVM BB %if.then.125
	    Predecessors according to CFG: BB#56
4688B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
4704B		JE_1 <BB#59>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#59 BB#58

4720B	BB#58: derived from LLVM BB %if.then.128
	    Predecessors according to CFG: BB#57
4736B		%vreg134<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg134
4752B		MOV32mi %vreg134, 1, %noreg, 0, %noreg, 4; mem:ST4[%76] GR64:%vreg134
	    Successors according to CFG: BB#59

4768B	BB#59: derived from LLVM BB %if.end.129
	    Predecessors according to CFG: BB#57 BB#58
4784B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
4800B		JE_1 <BB#61>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#61 BB#60

4816B	BB#60: derived from LLVM BB %if.then.132
	    Predecessors according to CFG: BB#59
4832B		%vreg137<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg137
4848B		MOV32mi %vreg137, 1, %noreg, 5096, %noreg, 4; mem:ST4[%lastErr133] GR64:%vreg137
	    Successors according to CFG: BB#61

4864B	BB#61: derived from LLVM BB %if.end.134
	    Predecessors according to CFG: BB#59 BB#60
4880B		%vreg141<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%len.addr] GR32:%vreg141
4896B		%vreg143<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg143
4928B		%vreg141<def,tied1> = SUB32rm %vreg141<tied0>, %vreg143, 1, %noreg, 5048, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%avail_out136] GR32:%vreg141 GR64:%vreg143
4944B		MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %vreg141; mem:ST4[%retval] GR32:%vreg141
4960B		JMP_1 <BB#69>
	    Successors according to CFG: BB#69

4976B	BB#62: derived from LLVM BB %if.end.137
	    Predecessors according to CFG: BB#56
4992B		%vreg123<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg123
5008B		CMP32mi8 %vreg123, 1, %noreg, 5048, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_out139] GR64:%vreg123
5024B		JNE_1 <BB#68>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#68 BB#63

5040B	BB#63: derived from LLVM BB %if.then.142
	    Predecessors according to CFG: BB#62
5056B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
5072B		JE_1 <BB#65>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#65 BB#64

5088B	BB#64: derived from LLVM BB %if.then.145
	    Predecessors according to CFG: BB#63
5104B		%vreg126<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg126
5120B		MOV32mi %vreg126, 1, %noreg, 0, %noreg, 0; mem:ST4[%85] GR64:%vreg126
	    Successors according to CFG: BB#65

5136B	BB#65: derived from LLVM BB %if.end.146
	    Predecessors according to CFG: BB#63 BB#64
5152B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
5168B		JE_1 <BB#67>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#67 BB#66

5184B	BB#66: derived from LLVM BB %if.then.149
	    Predecessors according to CFG: BB#65
5200B		%vreg129<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg129
5216B		MOV32mi %vreg129, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr150] GR64:%vreg129
	    Successors according to CFG: BB#67

5232B	BB#67: derived from LLVM BB %if.end.151
	    Predecessors according to CFG: BB#65 BB#66
5248B		%vreg131<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%len.addr] GR32:%vreg131
5264B		MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %vreg131; mem:ST4[%retval] GR32:%vreg131
5280B		JMP_1 <BB#69>
	    Successors according to CFG: BB#69

5296B	BB#68: derived from LLVM BB %if.end.152
	    Predecessors according to CFG: BB#62
5312B		JMP_1 <BB#25>
	    Successors according to CFG: BB#25

5328B	BB#69: derived from LLVM BB %return
	    Predecessors according to CFG: BB#38 BB#67 BB#61 BB#55 BB#46 BB#30 BB#23 BB#17 BB#11
5344B		%vreg188<def> = MOV64ri <ga:@BZ2_bzRead>; GR64:%vreg188
5376B		%vreg189<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg189
5392B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5408B		%RDI<def> = COPY %vreg188; GR64:%vreg188
5424B		%RSI<def> = COPY %vreg189; GR64:%vreg189
5440B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
5456B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5472B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5488B		STACKMAP 7, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
5504B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5520B		%vreg186<def> = MOV32rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD4[%retval] GR32:%vreg186
5536B		%EAX<def> = COPY %vreg186; GR32:%vreg186
5552B		RETQ %EAX<imp-use,kill>

# End machine code for function BZ2_bzRead.

handleMove 2592B -> 2632B: %RDI<def> = COPY %vreg72; GR64:%vreg72
     DIL:	[0B,64r:0)[208r,240r:8)[1760r,1776r:7)[2272r,2288r:6)[2592r,2656r:4)[2832r,2848r:5)[3504r,3520r:3)[4096r,4112r:2)[5408r,5440r:1)  0@0B-phi 1@5408r 2@4096r 3@3504r 4@2592r 5@2832r 6@2272r 7@1760r 8@208r
        -->	[0B,64r:0)[208r,240r:8)[1760r,1776r:7)[2272r,2288r:6)[2632r,2656r:4)[2832r,2848r:5)[3504r,3520r:3)[4096r,4112r:2)[5408r,5440r:1)  0@0B-phi 1@5408r 2@4096r 3@3504r 4@2632r 5@2832r 6@2272r 7@1760r 8@208r
     %vreg72:	[2496r,2528r:0)[2528r,2592r:1)  0@2496r 1@2528r
        -->	[2496r,2528r:0)[2528r,2632r:1)  0@2496r 1@2528r
AllocationOrder(SEGMENT_REG) = [ ]
********** GREEDY REGISTER ALLOCATION **********
********** Function: BZ2_bzRead
********** INTERVALS **********
CH [0B,16r:0)[2640r,2656r:1)  0@0B-phi 1@2640r
CL [0B,16r:0)[2640r,2656r:1)  0@0B-phi 1@2640r
DH [0B,32r:0)[2624r,2656r:1)  0@0B-phi 1@2624r
DIL [0B,64r:0)[208r,240r:8)[1760r,1776r:7)[2272r,2288r:6)[2632r,2656r:4)[2832r,2848r:5)[3504r,3520r:3)[4096r,4112r:2)[5408r,5440r:1)  0@0B-phi 1@5408r 2@4096r 3@3504r 4@2632r 5@2832r 6@2272r 7@1760r 8@208r
DL [0B,32r:0)[2624r,2656r:1)  0@0B-phi 1@2624r
SIL [0B,48r:0)[224r,240r:3)[2608r,2656r:2)[5424r,5440r:1)  0@0B-phi 1@5424r 2@2608r 3@224r
%vreg1 [64r,320r:0)  0@64r
%vreg3 [48r,336r:0)  0@48r
%vreg5 [32r,352r:0)  0@32r
%vreg7 [16r,368r:0)  0@16r
%vreg11 [384r,416r:0)  0@384r
%vreg14 [144r,208r:0)  0@144r
%vreg15 [176r,224r:0)  0@176r
%vreg17 [480r,496r:0)  0@480r
%vreg20 [576r,592r:0)  0@576r
%vreg26 [1008r,1024r:0)  0@1008r
%vreg30 [1664r,1680r:0)  0@1664r
%vreg31 [1648r,1680r:0)  0@1648r
%vreg34 [1616r,1632r:0)  0@1616r
%vreg35 [1600r,1632r:0)  0@1600r
%vreg38 [1808r,1872r:0)  0@1808r
%vreg40 [1728r,1760r:0)  0@1728r
%vreg41 [1712r,1728r:0)  0@1712r
%vreg44 [2160r,2176r:0)  0@2160r
%vreg47 [2320r,2384r:0)  0@2320r
%vreg49 [2240r,2272r:0)  0@2240r
%vreg50 [2224r,2240r:0)  0@2224r
%vreg53 [2880r,2944r:0)  0@2880r
%vreg55 [2800r,2832r:0)  0@2800r
%vreg56 [2784r,2800r:0)  0@2784r
%vreg66 [2688r,2768r:0)  0@2688r
%vreg68 [2560r,2640r:0)  0@2560r
%vreg69 [2544r,2560r:0)  0@2544r
%vreg72 [2496r,2528r:0)[2528r,2632r:1)  0@2496r 1@2528r
%vreg76 [3392r,3408r:0)  0@3392r
%vreg79 [3344r,3376r:0)[3376r,3408r:1)  0@3344r 1@3376r
%vreg83 [3312r,3328r:0)  0@3312r
%vreg85 [3296r,3328r:0)  0@3296r
%vreg86 [3280r,3296r:0)  0@3280r
%vreg89 [3248r,3264r:0)  0@3248r
%vreg90 [3232r,3264r:0)  0@3232r
%vreg93 [3040r,3056r:0)  0@3040r
%vreg96 [3136r,3152r:0)  0@3136r
%vreg100 [3552r,3616r:0)  0@3552r
%vreg102 [3440r,3472r:0)[3472r,3504r:1)  0@3440r 1@3472r
%vreg108 [4208r,4224r:0)  0@4208r
%vreg110 [4144r,4208r:0)  0@4144r
%vreg112 [4064r,4096r:0)  0@4064r
%vreg113 [4048r,4064r:0)  0@4048r
%vreg116 [4272r,4288r:0)  0@4272r
%vreg119 [4336r,4352r:0)  0@4336r
%vreg123 [4992r,5008r:0)  0@4992r
%vreg126 [5104r,5120r:0)  0@5104r
%vreg129 [5200r,5216r:0)  0@5200r
%vreg131 [5248r,5264r:0)  0@5248r
%vreg134 [4736r,4752r:0)  0@4736r
%vreg137 [4832r,4848r:0)  0@4832r
%vreg141 [4880r,4928r:0)[4928r,4944r:1)  0@4880r 1@4928r
%vreg143 [4896r,4928r:0)  0@4896r
%vreg147 [4448r,4464r:0)  0@4448r
%vreg150 [4544r,4560r:0)  0@4544r
%vreg154 [3792r,3808r:0)  0@3792r
%vreg155 [3776r,3808r:0)  0@3776r
%vreg159 [3904r,3920r:0)  0@3904r
%vreg160 [3888r,3920r:0)  0@3888r
%vreg163 [1968r,1984r:0)  0@1968r
%vreg166 [2064r,2080r:0)  0@2064r
%vreg169 [1408r,1424r:0)  0@1408r
%vreg172 [1504r,1520r:0)  0@1504r
%vreg175 [1120r,1136r:0)  0@1120r
%vreg178 [1216r,1232r:0)  0@1216r
%vreg181 [816r,832r:0)  0@816r
%vreg184 [912r,928r:0)  0@912r
%vreg186 [5520r,5536r:0)  0@5520r
%vreg188 [5344r,5408r:0)  0@5344r
%vreg189 [5376r,5424r:0)  0@5376r
RegMasks: 240r 1776r 2288r 2656r 2848r 3520r 4112r 5440r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzRead: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=4, align=4, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=8, align=8, at location [SP+8]
  fi#3: size=8, align=8, at location [SP+8]
  fi#4: size=4, align=4, at location [SP+8]
  fi#5: size=4, align=4, at location [SP+8]
  fi#6: size=4, align=4, at location [SP+8]
  fi#7: size=8, align=8, at location [SP+8]
Function Live Ins: %RDI in %vreg0, %RSI in %vreg2, %RDX in %vreg4, %ECX in %vreg6

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI %RSI %RDX %ECX
16B		%vreg7<def> = COPY %ECX; GR32:%vreg7
32B		%vreg5<def> = COPY %RDX; GR64:%vreg5
48B		%vreg3<def> = COPY %RSI; GR64:%vreg3
64B		%vreg1<def> = COPY %RDI; GR64:%vreg1
144B		%vreg14<def> = MOV64ri <ga:@BZ2_bzRead>; GR64:%vreg14
176B		%vreg15<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg15
192B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
208B		%RDI<def> = COPY %vreg14; GR64:%vreg14
224B		%RSI<def> = COPY %vreg15; GR64:%vreg15
240B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
256B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
272B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
288B		STACKMAP 0, 0, %vreg3, 0, <fi#2>, 0, %vreg5, 0, <fi#3>, 0, %vreg1, 0, <fi#1>, 0, 0, <fi#7>, 0, %vreg7, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack2] LD8[FixedStack3] LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4) GR64:%vreg3,%vreg5,%vreg1 GR32:%vreg7
304B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
320B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%bzerror.addr] GR64:%vreg1
336B		MOV64mr <fi#2>, 1, %noreg, 0, %noreg, %vreg3; mem:ST8[%b.addr] GR64:%vreg3
352B		MOV64mr <fi#3>, 1, %noreg, 0, %noreg, %vreg5; mem:ST8[%buf.addr] GR64:%vreg5
368B		MOV32mr <fi#4>, 1, %noreg, 0, %noreg, %vreg7; mem:ST4[%len.addr] GR32:%vreg7
384B		%vreg11<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr] GR64:%vreg11
416B		MOV64mr <fi#7>, 1, %noreg, 0, %noreg, %vreg11; mem:ST8[%bzf] GR64:%vreg11
432B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
448B		JE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

464B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
480B		%vreg17<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg17
496B		MOV32mi %vreg17, 1, %noreg, 0, %noreg, 0; mem:ST4[%3] GR64:%vreg17
	    Successors according to CFG: BB#2

512B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#1
528B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
544B		JE_1 <BB#4>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#4 BB#3

560B	BB#3: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#2
576B		%vreg20<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg20
592B		MOV32mi %vreg20, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr] GR64:%vreg20
	    Successors according to CFG: BB#4

608B	BB#4: derived from LLVM BB %if.end.3
	    Predecessors according to CFG: BB#2 BB#3
624B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
640B		JE_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#5

656B	BB#5: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#4
672B		CMP64mi8 <fi#3>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%buf.addr]
688B		JE_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#6

704B	BB#6: derived from LLVM BB %lor.lhs.false.6
	    Predecessors according to CFG: BB#5
720B		CMP32mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%len.addr]
736B		JGE_1 <BB#12>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#12 BB#7

752B	BB#7: derived from LLVM BB %if.then.8
	    Predecessors according to CFG: BB#4 BB#5 BB#6
768B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
784B		JE_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#8

800B	BB#8: derived from LLVM BB %if.then.10
	    Predecessors according to CFG: BB#7
816B		%vreg181<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg181
832B		MOV32mi %vreg181, 1, %noreg, 0, %noreg, -2; mem:ST4[%10] GR64:%vreg181
	    Successors according to CFG: BB#9

848B	BB#9: derived from LLVM BB %if.end.11
	    Predecessors according to CFG: BB#7 BB#8
864B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
880B		JE_1 <BB#11>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#11 BB#10

896B	BB#10: derived from LLVM BB %if.then.13
	    Predecessors according to CFG: BB#9
912B		%vreg184<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg184
928B		MOV32mi %vreg184, 1, %noreg, 5096, %noreg, -2; mem:ST4[%lastErr14] GR64:%vreg184
	    Successors according to CFG: BB#11

944B	BB#11: derived from LLVM BB %if.end.15
	    Predecessors according to CFG: BB#9 BB#10
960B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
976B		JMP_1 <BB#69>
	    Successors according to CFG: BB#69

992B	BB#12: derived from LLVM BB %if.end.16
	    Predecessors according to CFG: BB#6
1008B		%vreg26<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg26
1024B		CMP8mi %vreg26, 1, %noreg, 5012, %noreg, 0, %EFLAGS<imp-def>; mem:LD1[%writing] GR64:%vreg26
1040B		JE_1 <BB#18>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#18 BB#13

1056B	BB#13: derived from LLVM BB %if.then.17
	    Predecessors according to CFG: BB#12
1072B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
1088B		JE_1 <BB#15>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#15 BB#14

1104B	BB#14: derived from LLVM BB %if.then.19
	    Predecessors according to CFG: BB#13
1120B		%vreg175<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg175
1136B		MOV32mi %vreg175, 1, %noreg, 0, %noreg, -1; mem:ST4[%16] GR64:%vreg175
	    Successors according to CFG: BB#15

1152B	BB#15: derived from LLVM BB %if.end.20
	    Predecessors according to CFG: BB#13 BB#14
1168B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
1184B		JE_1 <BB#17>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#17 BB#16

1200B	BB#16: derived from LLVM BB %if.then.22
	    Predecessors according to CFG: BB#15
1216B		%vreg178<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg178
1232B		MOV32mi %vreg178, 1, %noreg, 5096, %noreg, -1; mem:ST4[%lastErr23] GR64:%vreg178
	    Successors according to CFG: BB#17

1248B	BB#17: derived from LLVM BB %if.end.24
	    Predecessors according to CFG: BB#15 BB#16
1264B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
1280B		JMP_1 <BB#69>
	    Successors according to CFG: BB#69

1296B	BB#18: derived from LLVM BB %if.end.25
	    Predecessors according to CFG: BB#12
1312B		CMP32mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%len.addr]
1328B		JNE_1 <BB#24>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#24 BB#19

1344B	BB#19: derived from LLVM BB %if.then.27
	    Predecessors according to CFG: BB#18
1360B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
1376B		JE_1 <BB#21>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#21 BB#20

1392B	BB#20: derived from LLVM BB %if.then.29
	    Predecessors according to CFG: BB#19
1408B		%vreg169<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg169
1424B		MOV32mi %vreg169, 1, %noreg, 0, %noreg, 0; mem:ST4[%21] GR64:%vreg169
	    Successors according to CFG: BB#21

1440B	BB#21: derived from LLVM BB %if.end.30
	    Predecessors according to CFG: BB#19 BB#20
1456B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
1472B		JE_1 <BB#23>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#23 BB#22

1488B	BB#22: derived from LLVM BB %if.then.32
	    Predecessors according to CFG: BB#21
1504B		%vreg172<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg172
1520B		MOV32mi %vreg172, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr33] GR64:%vreg172
	    Successors according to CFG: BB#23

1536B	BB#23: derived from LLVM BB %if.end.34
	    Predecessors according to CFG: BB#21 BB#22
1552B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
1568B		JMP_1 <BB#69>
	    Successors according to CFG: BB#69

1584B	BB#24: derived from LLVM BB %if.end.35
	    Predecessors according to CFG: BB#18
1600B		%vreg35<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%len.addr] GR32:%vreg35
1616B		%vreg34<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg34
1632B		MOV32mr %vreg34, 1, %noreg, 5048, %noreg, %vreg35; mem:ST4[%avail_out] GR64:%vreg34 GR32:%vreg35
1648B		%vreg31<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%buf.addr] GR64:%vreg31
1664B		%vreg30<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg30
1680B		MOV64mr %vreg30, 1, %noreg, 5040, %noreg, %vreg31; mem:ST8[%next_out] GR64:%vreg30,%vreg31
	    Successors according to CFG: BB#25

1696B	BB#25: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#24 BB#68
1712B		%vreg41<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg41
1728B		%vreg40<def> = MOV64rm %vreg41, 1, %noreg, 0, %noreg; mem:LD8[%handle] GR64:%vreg40,%vreg41
1744B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1760B		%RDI<def> = COPY %vreg40; GR64:%vreg40
1776B		CALL64pcrel32 <ga:@ferror>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
1792B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1808B		%vreg38<def> = COPY %EAX<kill>; GR32:%vreg38
1824B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1840B		STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
1856B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1872B		CMP32ri8 %vreg38, 0, %EFLAGS<imp-def>; GR32:%vreg38
1888B		JE_1 <BB#31>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#31 BB#26

1904B	BB#26: derived from LLVM BB %if.then.38
	    Predecessors according to CFG: BB#25
1920B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
1936B		JE_1 <BB#28>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#28 BB#27

1952B	BB#27: derived from LLVM BB %if.then.40
	    Predecessors according to CFG: BB#26
1968B		%vreg163<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg163
1984B		MOV32mi %vreg163, 1, %noreg, 0, %noreg, -6; mem:ST4[%31] GR64:%vreg163
	    Successors according to CFG: BB#28

2000B	BB#28: derived from LLVM BB %if.end.41
	    Predecessors according to CFG: BB#26 BB#27
2016B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
2032B		JE_1 <BB#30>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#30 BB#29

2048B	BB#29: derived from LLVM BB %if.then.43
	    Predecessors according to CFG: BB#28
2064B		%vreg166<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg166
2080B		MOV32mi %vreg166, 1, %noreg, 5096, %noreg, -6; mem:ST4[%lastErr44] GR64:%vreg166
	    Successors according to CFG: BB#30

2096B	BB#30: derived from LLVM BB %if.end.45
	    Predecessors according to CFG: BB#28 BB#29
2112B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
2128B		JMP_1 <BB#69>
	    Successors according to CFG: BB#69

2144B	BB#31: derived from LLVM BB %if.end.46
	    Predecessors according to CFG: BB#25
2160B		%vreg44<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg44
2176B		CMP32mi8 %vreg44, 1, %noreg, 5024, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_in] GR64:%vreg44
2192B		JNE_1 <BB#40>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#40 BB#32

2208B	BB#32: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#31
2224B		%vreg50<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg50
2240B		%vreg49<def> = MOV64rm %vreg50, 1, %noreg, 0, %noreg; mem:LD8[%handle49] GR64:%vreg49,%vreg50
2256B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2272B		%RDI<def> = COPY %vreg49; GR64:%vreg49
2288B		CALL64pcrel32 <ga:@myfeof>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %AL<imp-def>
2304B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2320B		%vreg47<def> = COPY %AL<kill>; GR8:%vreg47
2336B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2352B		STACKMAP 2, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
2368B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2384B		CMP8ri %vreg47, 0, %EFLAGS<imp-def>; GR8:%vreg47
2400B		JNE_1 <BB#40>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#40 BB#33

2416B	BB#33: derived from LLVM BB %if.then.52
	    Predecessors according to CFG: BB#32
2496B		%vreg72<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg72
2528B		%vreg72<def,tied1> = ADD64ri8 %vreg72<tied0>, 8, %EFLAGS<imp-def,dead>; GR64:%vreg72
2544B		%vreg69<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg69
2560B		%vreg68<def> = MOV64rm %vreg69, 1, %noreg, 0, %noreg; mem:LD8[%handle54] GR64:%vreg68,%vreg69
2576B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2608B		%ESI<def,dead> = MOV32ri 1, %RSI<imp-def>
2624B		%EDX<def,dead> = MOV32ri 5000, %RDX<imp-def>
2632B		%RDI<def> = COPY %vreg72; GR64:%vreg72
2640B		%RCX<def> = COPY %vreg68; GR64:%vreg68
2656B		CALL64pcrel32 <ga:@fread>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %RDX<imp-use>, %RCX<imp-use>, %RAX<imp-def>
2672B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2688B		%vreg66<def> = COPY %RAX<kill>; GR64_with_sub_8bit:%vreg66
2704B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2720B		STACKMAP 3, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
2736B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2768B		MOV32mr <fi#5>, 1, %noreg, 0, %noreg, %vreg66:sub_32bit; mem:ST4[%n] GR64_with_sub_8bit:%vreg66
2784B		%vreg56<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg56
2800B		%vreg55<def> = MOV64rm %vreg56, 1, %noreg, 0, %noreg; mem:LD8[%handle56] GR64:%vreg55,%vreg56
2816B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2832B		%RDI<def> = COPY %vreg55; GR64:%vreg55
2848B		CALL64pcrel32 <ga:@ferror>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
2864B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2880B		%vreg53<def> = COPY %EAX<kill>; GR32:%vreg53
2896B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2912B		STACKMAP 4, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
2928B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2944B		CMP32ri8 %vreg53, 0, %EFLAGS<imp-def>; GR32:%vreg53
2960B		JE_1 <BB#39>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#39 BB#34

2976B	BB#34: derived from LLVM BB %if.then.59
	    Predecessors according to CFG: BB#33
2992B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
3008B		JE_1 <BB#36>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#36 BB#35

3024B	BB#35: derived from LLVM BB %if.then.62
	    Predecessors according to CFG: BB#34
3040B		%vreg93<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg93
3056B		MOV32mi %vreg93, 1, %noreg, 0, %noreg, -6; mem:ST4[%44] GR64:%vreg93
	    Successors according to CFG: BB#36

3072B	BB#36: derived from LLVM BB %if.end.63
	    Predecessors according to CFG: BB#34 BB#35
3088B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
3104B		JE_1 <BB#38>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#38 BB#37

3120B	BB#37: derived from LLVM BB %if.then.66
	    Predecessors according to CFG: BB#36
3136B		%vreg96<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg96
3152B		MOV32mi %vreg96, 1, %noreg, 5096, %noreg, -6; mem:ST4[%lastErr67] GR64:%vreg96
	    Successors according to CFG: BB#38

3168B	BB#38: derived from LLVM BB %if.end.68
	    Predecessors according to CFG: BB#36 BB#37
3184B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
3200B		JMP_1 <BB#69>
	    Successors according to CFG: BB#69

3216B	BB#39: derived from LLVM BB %if.end.69
	    Predecessors according to CFG: BB#33
3232B		%vreg90<def> = MOV32rm <fi#5>, 1, %noreg, 0, %noreg; mem:LD4[%n] GR32:%vreg90
3248B		%vreg89<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg89
3264B		MOV32mr %vreg89, 1, %noreg, 5008, %noreg, %vreg90; mem:ST4[%bufN] GR64:%vreg89 GR32:%vreg90
3280B		%vreg86<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg86
3296B		%vreg85<def> = MOV32rm %vreg86, 1, %noreg, 5008, %noreg; mem:LD4[%bufN70] GR32:%vreg85 GR64:%vreg86
3312B		%vreg83<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg83
3328B		MOV32mr %vreg83, 1, %noreg, 5024, %noreg, %vreg85; mem:ST4[%avail_in72] GR64:%vreg83 GR32:%vreg85
3344B		%vreg79<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg79
3376B		%vreg79<def,tied1> = ADD64ri8 %vreg79<tied0>, 8, %EFLAGS<imp-def,dead>; GR64:%vreg79
3392B		%vreg76<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg76
3408B		MOV64mr %vreg76, 1, %noreg, 5016, %noreg, %vreg79; mem:ST8[%next_in] GR64:%vreg76,%vreg79
	    Successors according to CFG: BB#40

3424B	BB#40: derived from LLVM BB %if.end.76
	    Predecessors according to CFG: BB#31 BB#32 BB#39
3440B		%vreg102<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg102
3472B		%vreg102<def,tied1> = ADD64ri32 %vreg102<tied0>, 5016, %EFLAGS<imp-def,dead>; GR64:%vreg102
3488B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3504B		%RDI<def> = COPY %vreg102; GR64:%vreg102
3520B		CALL64pcrel32 <ga:@BZ2_bzDecompress>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
3536B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3552B		%vreg100<def> = COPY %EAX<kill>; GR32:%vreg100
3568B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3584B		STACKMAP 5, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
3600B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3616B		MOV32mr <fi#6>, 1, %noreg, 0, %noreg, %vreg100; mem:ST4[%ret] GR32:%vreg100
3632B		CMP32mi8 <fi#6>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%ret]
3648B		JE_1 <BB#47>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#47 BB#41

3664B	BB#41: derived from LLVM BB %land.lhs.true.81
	    Predecessors according to CFG: BB#40
3680B		CMP32mi8 <fi#6>, 1, %noreg, 0, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%ret]
3696B		JE_1 <BB#47>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#47 BB#42

3712B	BB#42: derived from LLVM BB %if.then.84
	    Predecessors according to CFG: BB#41
3728B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
3744B		JE_1 <BB#44>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#44 BB#43

3760B	BB#43: derived from LLVM BB %if.then.87
	    Predecessors according to CFG: BB#42
3776B		%vreg155<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%ret] GR32:%vreg155
3792B		%vreg154<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg154
3808B		MOV32mr %vreg154, 1, %noreg, 0, %noreg, %vreg155; mem:ST4[%59] GR64:%vreg154 GR32:%vreg155
	    Successors according to CFG: BB#44

3824B	BB#44: derived from LLVM BB %if.end.88
	    Predecessors according to CFG: BB#42 BB#43
3840B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
3856B		JE_1 <BB#46>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#46 BB#45

3872B	BB#45: derived from LLVM BB %if.then.91
	    Predecessors according to CFG: BB#44
3888B		%vreg160<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%ret] GR32:%vreg160
3904B		%vreg159<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg159
3920B		MOV32mr %vreg159, 1, %noreg, 5096, %noreg, %vreg160; mem:ST4[%lastErr92] GR64:%vreg159 GR32:%vreg160
	    Successors according to CFG: BB#46

3936B	BB#46: derived from LLVM BB %if.end.93
	    Predecessors according to CFG: BB#44 BB#45
3952B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
3968B		JMP_1 <BB#69>
	    Successors according to CFG: BB#69

3984B	BB#47: derived from LLVM BB %if.end.94
	    Predecessors according to CFG: BB#40 BB#41
4000B		CMP32mi8 <fi#6>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%ret]
4016B		JNE_1 <BB#56>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#56 BB#48

4032B	BB#48: derived from LLVM BB %land.lhs.true.97
	    Predecessors according to CFG: BB#47
4048B		%vreg113<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg113
4064B		%vreg112<def> = MOV64rm %vreg113, 1, %noreg, 0, %noreg; mem:LD8[%handle98] GR64:%vreg112,%vreg113
4080B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4096B		%RDI<def> = COPY %vreg112; GR64:%vreg112
4112B		CALL64pcrel32 <ga:@myfeof>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %AL<imp-def>
4128B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4144B		%vreg110<def> = COPY %AL<kill>; GR8:%vreg110
4160B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4176B		STACKMAP 6, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
4192B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4208B		%vreg108<def> = MOVZX32rr8 %vreg110; GR32:%vreg108 GR8:%vreg110
4224B		CMP32ri8 %vreg108, 0, %EFLAGS<imp-def>; GR32:%vreg108
4240B		JE_1 <BB#56>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#56 BB#49

4256B	BB#49: derived from LLVM BB %land.lhs.true.102
	    Predecessors according to CFG: BB#48
4272B		%vreg116<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg116
4288B		CMP32mi8 %vreg116, 1, %noreg, 5024, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_in104] GR64:%vreg116
4304B		JNE_1 <BB#56>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#56 BB#50

4320B	BB#50: derived from LLVM BB %land.lhs.true.107
	    Predecessors according to CFG: BB#49
4336B		%vreg119<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg119
4352B		CMP32mi8 %vreg119, 1, %noreg, 5048, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_out109] GR64:%vreg119
4368B		JBE_1 <BB#56>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#56 BB#51

4384B	BB#51: derived from LLVM BB %if.then.112
	    Predecessors according to CFG: BB#50
4400B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
4416B		JE_1 <BB#53>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#53 BB#52

4432B	BB#52: derived from LLVM BB %if.then.115
	    Predecessors according to CFG: BB#51
4448B		%vreg147<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg147
4464B		MOV32mi %vreg147, 1, %noreg, 0, %noreg, -7; mem:ST4[%71] GR64:%vreg147
	    Successors according to CFG: BB#53

4480B	BB#53: derived from LLVM BB %if.end.116
	    Predecessors according to CFG: BB#51 BB#52
4496B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
4512B		JE_1 <BB#55>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#55 BB#54

4528B	BB#54: derived from LLVM BB %if.then.119
	    Predecessors according to CFG: BB#53
4544B		%vreg150<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg150
4560B		MOV32mi %vreg150, 1, %noreg, 5096, %noreg, -7; mem:ST4[%lastErr120] GR64:%vreg150
	    Successors according to CFG: BB#55

4576B	BB#55: derived from LLVM BB %if.end.121
	    Predecessors according to CFG: BB#53 BB#54
4592B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
4608B		JMP_1 <BB#69>
	    Successors according to CFG: BB#69

4624B	BB#56: derived from LLVM BB %if.end.122
	    Predecessors according to CFG: BB#47 BB#48 BB#49 BB#50
4640B		CMP32mi8 <fi#6>, 1, %noreg, 0, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%ret]
4656B		JNE_1 <BB#62>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#62 BB#57

4672B	BB#57: derived from LLVM BB %if.then.125
	    Predecessors according to CFG: BB#56
4688B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
4704B		JE_1 <BB#59>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#59 BB#58

4720B	BB#58: derived from LLVM BB %if.then.128
	    Predecessors according to CFG: BB#57
4736B		%vreg134<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg134
4752B		MOV32mi %vreg134, 1, %noreg, 0, %noreg, 4; mem:ST4[%76] GR64:%vreg134
	    Successors according to CFG: BB#59

4768B	BB#59: derived from LLVM BB %if.end.129
	    Predecessors according to CFG: BB#57 BB#58
4784B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
4800B		JE_1 <BB#61>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#61 BB#60

4816B	BB#60: derived from LLVM BB %if.then.132
	    Predecessors according to CFG: BB#59
4832B		%vreg137<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg137
4848B		MOV32mi %vreg137, 1, %noreg, 5096, %noreg, 4; mem:ST4[%lastErr133] GR64:%vreg137
	    Successors according to CFG: BB#61

4864B	BB#61: derived from LLVM BB %if.end.134
	    Predecessors according to CFG: BB#59 BB#60
4880B		%vreg141<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%len.addr] GR32:%vreg141
4896B		%vreg143<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg143
4928B		%vreg141<def,tied1> = SUB32rm %vreg141<tied0>, %vreg143, 1, %noreg, 5048, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%avail_out136] GR32:%vreg141 GR64:%vreg143
4944B		MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %vreg141; mem:ST4[%retval] GR32:%vreg141
4960B		JMP_1 <BB#69>
	    Successors according to CFG: BB#69

4976B	BB#62: derived from LLVM BB %if.end.137
	    Predecessors according to CFG: BB#56
4992B		%vreg123<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg123
5008B		CMP32mi8 %vreg123, 1, %noreg, 5048, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_out139] GR64:%vreg123
5024B		JNE_1 <BB#68>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#68 BB#63

5040B	BB#63: derived from LLVM BB %if.then.142
	    Predecessors according to CFG: BB#62
5056B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
5072B		JE_1 <BB#65>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#65 BB#64

5088B	BB#64: derived from LLVM BB %if.then.145
	    Predecessors according to CFG: BB#63
5104B		%vreg126<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg126
5120B		MOV32mi %vreg126, 1, %noreg, 0, %noreg, 0; mem:ST4[%85] GR64:%vreg126
	    Successors according to CFG: BB#65

5136B	BB#65: derived from LLVM BB %if.end.146
	    Predecessors according to CFG: BB#63 BB#64
5152B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
5168B		JE_1 <BB#67>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#67 BB#66

5184B	BB#66: derived from LLVM BB %if.then.149
	    Predecessors according to CFG: BB#65
5200B		%vreg129<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg129
5216B		MOV32mi %vreg129, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr150] GR64:%vreg129
	    Successors according to CFG: BB#67

5232B	BB#67: derived from LLVM BB %if.end.151
	    Predecessors according to CFG: BB#65 BB#66
5248B		%vreg131<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%len.addr] GR32:%vreg131
5264B		MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %vreg131; mem:ST4[%retval] GR32:%vreg131
5280B		JMP_1 <BB#69>
	    Successors according to CFG: BB#69

5296B	BB#68: derived from LLVM BB %if.end.152
	    Predecessors according to CFG: BB#62
5312B		JMP_1 <BB#25>
	    Successors according to CFG: BB#25

5328B	BB#69: derived from LLVM BB %return
	    Predecessors according to CFG: BB#38 BB#67 BB#61 BB#55 BB#46 BB#30 BB#23 BB#17 BB#11
5344B		%vreg188<def> = MOV64ri <ga:@BZ2_bzRead>; GR64:%vreg188
5376B		%vreg189<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg189
5392B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5408B		%RDI<def> = COPY %vreg188; GR64:%vreg188
5424B		%RSI<def> = COPY %vreg189; GR64:%vreg189
5440B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
5456B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5472B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5488B		STACKMAP 7, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
5504B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5520B		%vreg186<def> = MOV32rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD4[%retval] GR32:%vreg186
5536B		%EAX<def> = COPY %vreg186; GR32:%vreg186
5552B		RETQ %EAX<imp-use,kill>

# End machine code for function BZ2_bzRead.


selectOrSplit GR32:%vreg7 [16r,368r:0)  0@16r w=4.029255e-03
hints: %ECX
missed hint %ECX
assigning %vreg7 to %EBX: BH [16r,368r:0)  0@16r BL [16r,368r:0)  0@16r

selectOrSplit GR64:%vreg5 [32r,352r:0)  0@32r w=4.208333e-03
hints: %RDX
missed hint %RDX
%R14 is available at cost 1
Only trying the first 10 regs.
should evict: %vreg7 [16r,368r:0)  0@16r w= 4.029255e-03
hints: %ECX
can reassign: %vreg7 [16r,368r:0)  0@16r from %RBX to %ECX
should evict: %vreg7 [16r,368r:0)  0@16r w= 4.029255e-03
hints: %ECX
can reassign: %vreg7 [16r,368r:0)  0@16r from %RBX to %ECX
evicting %RBX interference: Cascade 1
unassigning %vreg7 from %EBX: BH BL
assigning %vreg5 to %RBX: BH [32r,352r:0)  0@32r BL [32r,352r:0)  0@32r
queuing new interval: %vreg7 [16r,368r:0)  0@16r

selectOrSplit GR32:%vreg7 [16r,368r:0)  0@16r w=4.029255e-03
hints: %ECX
missed hint %ECX
%R14D is available at cost 1
Only trying the first 10 regs.
assigning %vreg7 to %R14D: R14B [16r,368r:0)  0@16r

selectOrSplit GR64:%vreg3 [48r,336r:0)  0@48r w=4.404070e-03
hints: %RSI
missed hint %RSI
%R15 is available at cost 1
Only trying the first 10 regs.
should evict: %vreg5 [32r,352r:0)  0@32r w= 4.208333e-03
hints: %RDX
can reassign: %vreg5 [32r,352r:0)  0@32r from %RBX to %RDX
should evict: %vreg5 [32r,352r:0)  0@32r w= 4.208333e-03
hints: %RDX
can reassign: %vreg5 [32r,352r:0)  0@32r from %RBX to %RDX
evicting %RBX interference: Cascade 2
unassigning %vreg5 from %RBX: BH BL
assigning %vreg3 to %RBX: BH [48r,336r:0)  0@48r BL [48r,336r:0)  0@48r
queuing new interval: %vreg5 [32r,352r:0)  0@32r

selectOrSplit GR64:%vreg5 [32r,352r:0)  0@32r w=4.208333e-03
hints: %RDX
missed hint %RDX
%R15 is available at cost 1
Only trying the first 10 regs.
assigning %vreg5 to %R15: R15B [32r,352r:0)  0@32r

selectOrSplit GR64:%vreg1 [64r,320r:0)  0@64r w=4.618902e-03
hints: %RDI
missed hint %RDI
%R12 is available at cost 1
Only trying the first 10 regs.
should evict: %vreg3 [48r,336r:0)  0@48r w= 4.404070e-03
hints: %RSI
can reassign: %vreg3 [48r,336r:0)  0@48r from %RBX to %RSI
should evict: %vreg3 [48r,336r:0)  0@48r w= 4.404070e-03
hints: %RSI
can reassign: %vreg3 [48r,336r:0)  0@48r from %RBX to %RSI
evicting %RBX interference: Cascade 3
unassigning %vreg3 from %RBX: BH BL
assigning %vreg1 to %RBX: BH [64r,320r:0)  0@64r BL [64r,320r:0)  0@64r
queuing new interval: %vreg3 [48r,336r:0)  0@48r

selectOrSplit GR64:%vreg3 [48r,336r:0)  0@48r w=4.404070e-03
hints: %RSI
missed hint %RSI
%R12 is available at cost 1
Only trying the first 10 regs.
assigning %vreg3 to %R12: R12B [48r,336r:0)  0@48r

selectOrSplit GR64:%vreg14 [144r,208r:0)  0@144r w=2.176724e-03
hints: %RDI
assigning %vreg14 to %RDI: DIL [144r,208r:0)  0@144r

selectOrSplit GR64:%vreg15 [176r,224r:0)  0@176r w=4.508928e-03
hints: %RSI
assigning %vreg15 to %RSI: SIL [176r,224r:0)  0@176r

selectOrSplit GR64:%vreg40 [1728r,1760r:0)  0@1728r w=1.582584e-04
hints: %RDI
assigning %vreg40 to %RDI: DIL [1728r,1760r:0)  0@1728r

selectOrSplit GR32:%vreg38 [1808r,1872r:0)  0@1808r w=1.473440e-04
hints: %EAX
assigning %vreg38 to %EAX: AH [1808r,1872r:0)  0@1808r AL [1808r,1872r:0)  0@1808r

selectOrSplit GR64:%vreg49 [2240r,2272r:0)  0@2240r w=3.956459e-05
hints: %RDI
assigning %vreg49 to %RDI: DIL [2240r,2272r:0)  0@2240r

selectOrSplit GR8:%vreg47 [2320r,2384r:0)  0@2320r w=3.683600e-05
hints: %AL
assigning %vreg47 to %AL: AL [2320r,2384r:0)  0@2320r

selectOrSplit GR64:%vreg72 [2496r,2528r:0)[2528r,2632r:1)  0@2496r 1@2528r w=3.172435e-05
hints: %RDI
assigning %vreg72 to %RDI: DIL [2496r,2528r:0)[2528r,2632r:1)  0@2496r 1@2528r

selectOrSplit GR64:%vreg68 [2560r,2640r:0)  0@2560r w=1.771276e-05
hints: %RCX
assigning %vreg68 to %RCX: CH [2560r,2640r:0)  0@2560r CL [2560r,2640r:0)  0@2560r

selectOrSplit GR64_with_sub_8bit:%vreg66 [2688r,2768r:0)  0@2688r w=1.771276e-05
hints: %RAX
assigning %vreg66 to %RAX: AH [2688r,2768r:0)  0@2688r AL [2688r,2768r:0)  0@2688r

selectOrSplit GR64:%vreg55 [2800r,2832r:0)  0@2800r w=1.968085e-05
hints: %RDI
assigning %vreg55 to %RDI: DIL [2800r,2832r:0)  0@2800r

selectOrSplit GR32:%vreg53 [2880r,2944r:0)  0@2880r w=1.832355e-05
hints: %EAX
assigning %vreg53 to %EAX: AH [2880r,2944r:0)  0@2880r AL [2880r,2944r:0)  0@2880r

selectOrSplit GR64:%vreg102 [3440r,3472r:0)[3472r,3504r:1)  0@3440r 1@3472r w=1.288315e-04
hints: %RDI
assigning %vreg102 to %RDI: DIL [3440r,3472r:0)[3472r,3504r:1)  0@3440r 1@3472r

selectOrSplit GR32:%vreg100 [3552r,3616r:0)  0@3552r w=6.441577e-05
hints: %EAX
assigning %vreg100 to %EAX: AH [3552r,3616r:0)  0@3552r AL [3552r,3616r:0)  0@3552r

selectOrSplit GR64:%vreg112 [4064r,4096r:0)  0@4064r w=2.576771e-05
hints: %RDI
assigning %vreg112 to %RDI: DIL [4064r,4096r:0)  0@4064r

selectOrSplit GR8:%vreg110 [4144r,4208r:0)  0@4144r w=2.399063e-05
hints: %AL
assigning %vreg110 to %AL: AL [4144r,4208r:0)  0@4144r

selectOrSplit GR64:%vreg188 [5344r,5408r:0)  0@5344r w=2.176724e-03
hints: %RDI
assigning %vreg188 to %RDI: DIL [5344r,5408r:0)  0@5344r

selectOrSplit GR64:%vreg189 [5376r,5424r:0)  0@5376r w=4.508928e-03
hints: %RSI
assigning %vreg189 to %RSI: SIL [5376r,5424r:0)  0@5376r

selectOrSplit GR32:%vreg186 [5520r,5536r:0)  0@5520r w=inf
hints: %EAX
assigning %vreg186 to %EAX: AH [5520r,5536r:0)  0@5520r AL [5520r,5536r:0)  0@5520r

selectOrSplit GR64:%vreg11 [384r,416r:0)  0@384r w=inf
assigning %vreg11 to %RAX: AH [384r,416r:0)  0@384r AL [384r,416r:0)  0@384r

selectOrSplit GR64:%vreg17 [480r,496r:0)  0@480r w=inf
assigning %vreg17 to %RAX: AH [480r,496r:0)  0@480r AL [480r,496r:0)  0@480r

selectOrSplit GR64:%vreg20 [576r,592r:0)  0@576r w=inf
assigning %vreg20 to %RAX: AH [576r,592r:0)  0@576r AL [576r,592r:0)  0@576r

selectOrSplit GR64:%vreg181 [816r,832r:0)  0@816r w=inf
assigning %vreg181 to %RAX: AH [816r,832r:0)  0@816r AL [816r,832r:0)  0@816r

selectOrSplit GR64:%vreg184 [912r,928r:0)  0@912r w=inf
assigning %vreg184 to %RAX: AH [912r,928r:0)  0@912r AL [912r,928r:0)  0@912r

selectOrSplit GR64:%vreg26 [1008r,1024r:0)  0@1008r w=inf
assigning %vreg26 to %RAX: AH [1008r,1024r:0)  0@1008r AL [1008r,1024r:0)  0@1008r

selectOrSplit GR64:%vreg175 [1120r,1136r:0)  0@1120r w=inf
assigning %vreg175 to %RAX: AH [1120r,1136r:0)  0@1120r AL [1120r,1136r:0)  0@1120r

selectOrSplit GR64:%vreg178 [1216r,1232r:0)  0@1216r w=inf
assigning %vreg178 to %RAX: AH [1216r,1232r:0)  0@1216r AL [1216r,1232r:0)  0@1216r

selectOrSplit GR64:%vreg169 [1408r,1424r:0)  0@1408r w=inf
assigning %vreg169 to %RAX: AH [1408r,1424r:0)  0@1408r AL [1408r,1424r:0)  0@1408r

selectOrSplit GR64:%vreg172 [1504r,1520r:0)  0@1504r w=inf
assigning %vreg172 to %RAX: AH [1504r,1520r:0)  0@1504r AL [1504r,1520r:0)  0@1504r

selectOrSplit GR32:%vreg35 [1600r,1632r:0)  0@1600r w=1.446383e-04
assigning %vreg35 to %EAX: AH [1600r,1632r:0)  0@1600r AL [1600r,1632r:0)  0@1600r

selectOrSplit GR64:%vreg34 [1616r,1632r:0)  0@1616r w=inf
assigning %vreg34 to %RCX: CH [1616r,1632r:0)  0@1616r CL [1616r,1632r:0)  0@1616r

selectOrSplit GR64:%vreg31 [1648r,1680r:0)  0@1648r w=1.446383e-04
assigning %vreg31 to %RAX: AH [1648r,1680r:0)  0@1648r AL [1648r,1680r:0)  0@1648r

selectOrSplit GR64:%vreg30 [1664r,1680r:0)  0@1664r w=inf
assigning %vreg30 to %RCX: CH [1664r,1680r:0)  0@1664r CL [1664r,1680r:0)  0@1664r

selectOrSplit GR64:%vreg41 [1712r,1728r:0)  0@1712r w=inf
assigning %vreg41 to %RAX: AH [1712r,1728r:0)  0@1712r AL [1712r,1728r:0)  0@1712r

selectOrSplit GR64:%vreg163 [1968r,1984r:0)  0@1968r w=inf
assigning %vreg163 to %RAX: AH [1968r,1984r:0)  0@1968r AL [1968r,1984r:0)  0@1968r

selectOrSplit GR64:%vreg166 [2064r,2080r:0)  0@2064r w=inf
assigning %vreg166 to %RAX: AH [2064r,2080r:0)  0@2064r AL [2064r,2080r:0)  0@2064r

selectOrSplit GR64:%vreg44 [2160r,2176r:0)  0@2160r w=inf
assigning %vreg44 to %RAX: AH [2160r,2176r:0)  0@2160r AL [2160r,2176r:0)  0@2160r

selectOrSplit GR64:%vreg50 [2224r,2240r:0)  0@2224r w=inf
assigning %vreg50 to %RAX: AH [2224r,2240r:0)  0@2224r AL [2224r,2240r:0)  0@2224r

selectOrSplit GR64:%vreg69 [2544r,2560r:0)  0@2544r w=inf
assigning %vreg69 to %RAX: AH [2544r,2560r:0)  0@2544r AL [2544r,2560r:0)  0@2544r

selectOrSplit GR64:%vreg56 [2784r,2800r:0)  0@2784r w=inf
assigning %vreg56 to %RAX: AH [2784r,2800r:0)  0@2784r AL [2784r,2800r:0)  0@2784r

selectOrSplit GR64:%vreg93 [3040r,3056r:0)  0@3040r w=inf
assigning %vreg93 to %RAX: AH [3040r,3056r:0)  0@3040r AL [3040r,3056r:0)  0@3040r

selectOrSplit GR64:%vreg96 [3136r,3152r:0)  0@3136r w=inf
assigning %vreg96 to %RAX: AH [3136r,3152r:0)  0@3136r AL [3136r,3152r:0)  0@3136r

selectOrSplit GR32:%vreg90 [3232r,3264r:0)  0@3232r w=9.642551e-06
assigning %vreg90 to %EAX: AH [3232r,3264r:0)  0@3232r AL [3232r,3264r:0)  0@3232r

selectOrSplit GR64:%vreg89 [3248r,3264r:0)  0@3248r w=inf
assigning %vreg89 to %RCX: CH [3248r,3264r:0)  0@3248r CL [3248r,3264r:0)  0@3248r

selectOrSplit GR64:%vreg86 [3280r,3296r:0)  0@3280r w=inf
assigning %vreg86 to %RAX: AH [3280r,3296r:0)  0@3280r AL [3280r,3296r:0)  0@3280r

selectOrSplit GR32:%vreg85 [3296r,3328r:0)  0@3296r w=9.642551e-06
assigning %vreg85 to %EAX: AH [3296r,3328r:0)  0@3296r AL [3296r,3328r:0)  0@3296r

selectOrSplit GR64:%vreg83 [3312r,3328r:0)  0@3312r w=inf
assigning %vreg83 to %RCX: CH [3312r,3328r:0)  0@3312r CL [3312r,3328r:0)  0@3312r

selectOrSplit GR64:%vreg79 [3344r,3376r:0)[3376r,3408r:1)  0@3344r 1@3376r w=1.795510e-05
assigning %vreg79 to %RAX: AH [3344r,3376r:0)[3376r,3408r:1)  0@3344r 1@3376r AL [3344r,3376r:0)[3376r,3408r:1)  0@3344r 1@3376r

selectOrSplit GR64:%vreg76 [3392r,3408r:0)  0@3392r w=inf
assigning %vreg76 to %RCX: CH [3392r,3408r:0)  0@3392r CL [3392r,3408r:0)  0@3392r

selectOrSplit GR32:%vreg155 [3776r,3808r:0)  0@3776r w=8.437232e-06
assigning %vreg155 to %EAX: AH [3776r,3808r:0)  0@3776r AL [3776r,3808r:0)  0@3776r

selectOrSplit GR64:%vreg154 [3792r,3808r:0)  0@3792r w=inf
assigning %vreg154 to %RCX: CH [3792r,3808r:0)  0@3792r CL [3792r,3808r:0)  0@3792r

selectOrSplit GR32:%vreg160 [3888r,3920r:0)  0@3888r w=8.437232e-06
assigning %vreg160 to %EAX: AH [3888r,3920r:0)  0@3888r AL [3888r,3920r:0)  0@3888r

selectOrSplit GR64:%vreg159 [3904r,3920r:0)  0@3904r w=inf
assigning %vreg159 to %RCX: CH [3904r,3920r:0)  0@3904r CL [3904r,3920r:0)  0@3904r

selectOrSplit GR64:%vreg113 [4048r,4064r:0)  0@4048r w=inf
assigning %vreg113 to %RAX: AH [4048r,4064r:0)  0@4048r AL [4048r,4064r:0)  0@4048r

selectOrSplit GR32:%vreg108 [4208r,4224r:0)  0@4208r w=inf
assigning %vreg108 to %EAX: AH [4208r,4224r:0)  0@4208r AL [4208r,4224r:0)  0@4208r

selectOrSplit GR64:%vreg116 [4272r,4288r:0)  0@4272r w=inf
assigning %vreg116 to %RAX: AH [4272r,4288r:0)  0@4272r AL [4272r,4288r:0)  0@4272r

selectOrSplit GR64:%vreg119 [4336r,4352r:0)  0@4336r w=inf
assigning %vreg119 to %RAX: AH [4336r,4352r:0)  0@4336r AL [4336r,4352r:0)  0@4336r

selectOrSplit GR64:%vreg147 [4448r,4464r:0)  0@4448r w=inf
assigning %vreg147 to %RAX: AH [4448r,4464r:0)  0@4448r AL [4448r,4464r:0)  0@4448r

selectOrSplit GR64:%vreg150 [4544r,4560r:0)  0@4544r w=inf
assigning %vreg150 to %RAX: AH [4544r,4560r:0)  0@4544r AL [4544r,4560r:0)  0@4544r

selectOrSplit GR64:%vreg134 [4736r,4752r:0)  0@4736r w=inf
assigning %vreg134 to %RAX: AH [4736r,4752r:0)  0@4736r AL [4736r,4752r:0)  0@4736r

selectOrSplit GR64:%vreg137 [4832r,4848r:0)  0@4832r w=inf
assigning %vreg137 to %RAX: AH [4832r,4848r:0)  0@4832r AL [4832r,4848r:0)  0@4832r

selectOrSplit GR32:%vreg141 [4880r,4928r:0)[4928r,4944r:1)  0@4880r 1@4928r w=4.451368e-05
assigning %vreg141 to %EAX: AH [4880r,4928r:0)[4928r,4944r:1)  0@4880r 1@4928r AL [4880r,4928r:0)[4928r,4944r:1)  0@4880r 1@4928r

selectOrSplit GR64:%vreg143 [4896r,4928r:0)  0@4896r w=inf
assigning %vreg143 to %RCX: CH [4896r,4928r:0)  0@4896r CL [4896r,4928r:0)  0@4896r

selectOrSplit GR64:%vreg123 [4992r,5008r:0)  0@4992r w=inf
assigning %vreg123 to %RAX: AH [4992r,5008r:0)  0@4992r AL [4992r,5008r:0)  0@4992r

selectOrSplit GR64:%vreg126 [5104r,5120r:0)  0@5104r w=inf
assigning %vreg126 to %RAX: AH [5104r,5120r:0)  0@5104r AL [5104r,5120r:0)  0@5104r

selectOrSplit GR64:%vreg129 [5200r,5216r:0)  0@5200r w=inf
assigning %vreg129 to %RAX: AH [5200r,5216r:0)  0@5200r AL [5200r,5216r:0)  0@5200r

selectOrSplit GR32:%vreg131 [5248r,5264r:0)  0@5248r w=inf
assigning %vreg131 to %EAX: AH [5248r,5264r:0)  0@5248r AL [5248r,5264r:0)  0@5248r

********** STACK TRANSFORMATION METADATA **********
********** Function: BZ2_bzRead
********** REGISTER MAP **********
[%vreg1 -> %RBX] GR64
[%vreg3 -> %R12] GR64
[%vreg5 -> %R15] GR64
[%vreg7 -> %R14D] GR32
[%vreg11 -> %RAX] GR64
[%vreg14 -> %RDI] GR64
[%vreg15 -> %RSI] GR64
[%vreg17 -> %RAX] GR64
[%vreg20 -> %RAX] GR64
[%vreg26 -> %RAX] GR64
[%vreg30 -> %RCX] GR64
[%vreg31 -> %RAX] GR64
[%vreg34 -> %RCX] GR64
[%vreg35 -> %EAX] GR32
[%vreg38 -> %EAX] GR32
[%vreg40 -> %RDI] GR64
[%vreg41 -> %RAX] GR64
[%vreg44 -> %RAX] GR64
[%vreg47 -> %AL] GR8
[%vreg49 -> %RDI] GR64
[%vreg50 -> %RAX] GR64
[%vreg53 -> %EAX] GR32
[%vreg55 -> %RDI] GR64
[%vreg56 -> %RAX] GR64
[%vreg66 -> %RAX] GR64_with_sub_8bit
[%vreg68 -> %RCX] GR64
[%vreg69 -> %RAX] GR64
[%vreg72 -> %RDI] GR64
[%vreg76 -> %RCX] GR64
[%vreg79 -> %RAX] GR64
[%vreg83 -> %RCX] GR64
[%vreg85 -> %EAX] GR32
[%vreg86 -> %RAX] GR64
[%vreg89 -> %RCX] GR64
[%vreg90 -> %EAX] GR32
[%vreg93 -> %RAX] GR64
[%vreg96 -> %RAX] GR64
[%vreg100 -> %EAX] GR32
[%vreg102 -> %RDI] GR64
[%vreg108 -> %EAX] GR32
[%vreg110 -> %AL] GR8
[%vreg112 -> %RDI] GR64
[%vreg113 -> %RAX] GR64
[%vreg116 -> %RAX] GR64
[%vreg119 -> %RAX] GR64
[%vreg123 -> %RAX] GR64
[%vreg126 -> %RAX] GR64
[%vreg129 -> %RAX] GR64
[%vreg131 -> %EAX] GR32
[%vreg134 -> %RAX] GR64
[%vreg137 -> %RAX] GR64
[%vreg141 -> %EAX] GR32
[%vreg143 -> %RCX] GR64
[%vreg147 -> %RAX] GR64
[%vreg150 -> %RAX] GR64
[%vreg154 -> %RCX] GR64
[%vreg155 -> %EAX] GR32
[%vreg159 -> %RCX] GR64
[%vreg160 -> %EAX] GR32
[%vreg163 -> %RAX] GR64
[%vreg166 -> %RAX] GR64
[%vreg169 -> %RAX] GR64
[%vreg172 -> %RAX] GR64
[%vreg175 -> %RAX] GR64
[%vreg178 -> %RAX] GR64
[%vreg181 -> %RAX] GR64
[%vreg184 -> %RAX] GR64
[%vreg186 -> %EAX] GR32
[%vreg188 -> %RDI] GR64
[%vreg189 -> %RSI] GR64


Stackmap 0:
  STACKMAP 0, 0, %vreg3, 0, <fi#2>, 0, %vreg5, 0, <fi#3>, 0, %vreg1, 0, <fi#1>, 0, 0, <fi#7>, 0, %vreg7, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack2] LD8[FixedStack3] LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4) GR64:%vreg3,%vreg5,%vreg1 GR32:%vreg7

i8* %b: in register %R12 (vreg 3)
i8** %b.addr: in stack slot 2 (size: 8)
i8* %buf: in register %R15 (vreg 5)
i8** %buf.addr: in stack slot 3 (size: 8)
i32* %bzerror: in register %RBX (vreg 1)
i32** %bzerror.addr: in stack slot 1 (size: 8)
%struct.bzFile** %bzf: in stack slot 7 (size: 8)
i32 %len: in register %R14D (vreg 7)
i32* %len.addr: in stack slot 4 (size: 4)
i32* %n: in stack slot 5 (size: 4)
i32* %ret: in stack slot 6 (size: 4)
i32* %retval: in stack slot 0 (size: 4)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)

i32** %bzerror.addr: in stack slot 1 (size: 8)
%struct.bzFile** %bzf: in stack slot 7 (size: 8)
i32* %len.addr: in stack slot 4 (size: 4)
i32* %n: in stack slot 5 (size: 4)
i32* %ret: in stack slot 6 (size: 4)
i32* %retval: in stack slot 0 (size: 4)

Duplicate operand locations:


Stackmap 2:
  STACKMAP 2, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)

i32** %bzerror.addr: in stack slot 1 (size: 8)
%struct.bzFile** %bzf: in stack slot 7 (size: 8)
i32* %len.addr: in stack slot 4 (size: 4)
i32* %n: in stack slot 5 (size: 4)
i32* %ret: in stack slot 6 (size: 4)
i32* %retval: in stack slot 0 (size: 4)

Duplicate operand locations:


Stackmap 3:
  STACKMAP 3, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)

i32** %bzerror.addr: in stack slot 1 (size: 8)
%struct.bzFile** %bzf: in stack slot 7 (size: 8)
i32* %len.addr: in stack slot 4 (size: 4)
i32* %n: in stack slot 5 (size: 4)
i32* %ret: in stack slot 6 (size: 4)
i32* %retval: in stack slot 0 (size: 4)

Duplicate operand locations:


Stackmap 4:
  STACKMAP 4, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)

i32** %bzerror.addr: in stack slot 1 (size: 8)
%struct.bzFile** %bzf: in stack slot 7 (size: 8)
i32* %len.addr: in stack slot 4 (size: 4)
i32* %n: in stack slot 5 (size: 4)
i32* %ret: in stack slot 6 (size: 4)
i32* %retval: in stack slot 0 (size: 4)

Duplicate operand locations:


Stackmap 5:
  STACKMAP 5, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)

i32** %bzerror.addr: in stack slot 1 (size: 8)
%struct.bzFile** %bzf: in stack slot 7 (size: 8)
i32* %len.addr: in stack slot 4 (size: 4)
i32* %n: in stack slot 5 (size: 4)
i32* %ret: in stack slot 6 (size: 4)
i32* %retval: in stack slot 0 (size: 4)

Duplicate operand locations:


Stackmap 6:
  STACKMAP 6, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)

i32** %bzerror.addr: in stack slot 1 (size: 8)
%struct.bzFile** %bzf: in stack slot 7 (size: 8)
i32* %len.addr: in stack slot 4 (size: 4)
i32* %n: in stack slot 5 (size: 4)
i32* %ret: in stack slot 6 (size: 4)
i32* %retval: in stack slot 0 (size: 4)

Duplicate operand locations:


Stackmap 7:
  STACKMAP 7, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)

i32* %retval: in stack slot 0 (size: 4)

Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, %vreg3, 0, <fi#2>, 0, %vreg5, 0, <fi#3>, 0, %vreg1, 0, <fi#1>, 0, 0, <fi#7>, 0, %vreg7, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack2] LD8[FixedStack3] LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4) GR64:%vreg3,%vreg5,%vreg1 GR32:%vreg7
  -> Call instruction SlotIndex 240B, searching vregs 0 -> 190 and stack slots -1 -> 8

  STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
  -> Call instruction SlotIndex 1776B, searching vregs 0 -> 190 and stack slots -1 -> 8

  STACKMAP 2, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
  -> Call instruction SlotIndex 2288B, searching vregs 0 -> 190 and stack slots -1 -> 8

  STACKMAP 3, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
  -> Call instruction SlotIndex 2656B, searching vregs 0 -> 190 and stack slots -1 -> 8

  STACKMAP 4, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
  -> Call instruction SlotIndex 2848B, searching vregs 0 -> 190 and stack slots -1 -> 8

  STACKMAP 5, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
  -> Call instruction SlotIndex 3520B, searching vregs 0 -> 190 and stack slots -1 -> 8

  STACKMAP 6, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
  -> Call instruction SlotIndex 4112B, searching vregs 0 -> 190 and stack slots -1 -> 8

  STACKMAP 7, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
  -> Call instruction SlotIndex 5440B, searching vregs 0 -> 190 and stack slots -1 -> 8

********** REWRITE VIRTUAL REGISTERS **********
********** Function: BZ2_bzRead
********** REGISTER MAP **********
[%vreg1 -> %RBX] GR64
[%vreg3 -> %R12] GR64
[%vreg5 -> %R15] GR64
[%vreg7 -> %R14D] GR32
[%vreg11 -> %RAX] GR64
[%vreg14 -> %RDI] GR64
[%vreg15 -> %RSI] GR64
[%vreg17 -> %RAX] GR64
[%vreg20 -> %RAX] GR64
[%vreg26 -> %RAX] GR64
[%vreg30 -> %RCX] GR64
[%vreg31 -> %RAX] GR64
[%vreg34 -> %RCX] GR64
[%vreg35 -> %EAX] GR32
[%vreg38 -> %EAX] GR32
[%vreg40 -> %RDI] GR64
[%vreg41 -> %RAX] GR64
[%vreg44 -> %RAX] GR64
[%vreg47 -> %AL] GR8
[%vreg49 -> %RDI] GR64
[%vreg50 -> %RAX] GR64
[%vreg53 -> %EAX] GR32
[%vreg55 -> %RDI] GR64
[%vreg56 -> %RAX] GR64
[%vreg66 -> %RAX] GR64_with_sub_8bit
[%vreg68 -> %RCX] GR64
[%vreg69 -> %RAX] GR64
[%vreg72 -> %RDI] GR64
[%vreg76 -> %RCX] GR64
[%vreg79 -> %RAX] GR64
[%vreg83 -> %RCX] GR64
[%vreg85 -> %EAX] GR32
[%vreg86 -> %RAX] GR64
[%vreg89 -> %RCX] GR64
[%vreg90 -> %EAX] GR32
[%vreg93 -> %RAX] GR64
[%vreg96 -> %RAX] GR64
[%vreg100 -> %EAX] GR32
[%vreg102 -> %RDI] GR64
[%vreg108 -> %EAX] GR32
[%vreg110 -> %AL] GR8
[%vreg112 -> %RDI] GR64
[%vreg113 -> %RAX] GR64
[%vreg116 -> %RAX] GR64
[%vreg119 -> %RAX] GR64
[%vreg123 -> %RAX] GR64
[%vreg126 -> %RAX] GR64
[%vreg129 -> %RAX] GR64
[%vreg131 -> %EAX] GR32
[%vreg134 -> %RAX] GR64
[%vreg137 -> %RAX] GR64
[%vreg141 -> %EAX] GR32
[%vreg143 -> %RCX] GR64
[%vreg147 -> %RAX] GR64
[%vreg150 -> %RAX] GR64
[%vreg154 -> %RCX] GR64
[%vreg155 -> %EAX] GR32
[%vreg159 -> %RCX] GR64
[%vreg160 -> %EAX] GR32
[%vreg163 -> %RAX] GR64
[%vreg166 -> %RAX] GR64
[%vreg169 -> %RAX] GR64
[%vreg172 -> %RAX] GR64
[%vreg175 -> %RAX] GR64
[%vreg178 -> %RAX] GR64
[%vreg181 -> %RAX] GR64
[%vreg184 -> %RAX] GR64
[%vreg186 -> %EAX] GR32
[%vreg188 -> %RDI] GR64
[%vreg189 -> %RSI] GR64

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %ECX %RDI %RDX %RSI
16B		%vreg7<def> = COPY %ECX; GR32:%vreg7
32B		%vreg5<def> = COPY %RDX; GR64:%vreg5
48B		%vreg3<def> = COPY %RSI; GR64:%vreg3
64B		%vreg1<def> = COPY %RDI; GR64:%vreg1
144B		%vreg14<def> = MOV64ri <ga:@BZ2_bzRead>; GR64:%vreg14
176B		%vreg15<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg15
192B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
208B		%RDI<def> = COPY %vreg14<kill>; GR64:%vreg14
224B		%RSI<def> = COPY %vreg15<kill>; GR64:%vreg15
240B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
256B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
272B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
288B		STACKMAP 0, 0, %vreg3, 0, <fi#2>, 0, %vreg5, 0, <fi#3>, 0, %vreg1, 0, <fi#1>, 0, 0, <fi#7>, 0, %vreg7, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack2] LD8[FixedStack3] LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4) GR64:%vreg3,%vreg5,%vreg1 GR32:%vreg7
304B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
320B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg1<kill>; mem:ST8[%bzerror.addr] GR64:%vreg1
336B		MOV64mr <fi#2>, 1, %noreg, 0, %noreg, %vreg3<kill>; mem:ST8[%b.addr] GR64:%vreg3
352B		MOV64mr <fi#3>, 1, %noreg, 0, %noreg, %vreg5<kill>; mem:ST8[%buf.addr] GR64:%vreg5
368B		MOV32mr <fi#4>, 1, %noreg, 0, %noreg, %vreg7<kill>; mem:ST4[%len.addr] GR32:%vreg7
384B		%vreg11<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr] GR64:%vreg11
416B		MOV64mr <fi#7>, 1, %noreg, 0, %noreg, %vreg11<kill>; mem:ST8[%bzf] GR64:%vreg11
432B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
448B		JE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1
> %R14D<def> = COPY %ECX
> %R15<def> = COPY %RDX
> %R12<def> = COPY %RSI
> %RBX<def> = COPY %RDI
> %RDI<def> = MOV64ri <ga:@BZ2_bzRead>
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 0, 0, %R12, 0, <fi#2>, 0, %R15, 0, <fi#3>, 0, %RBX, 0, <fi#1>, 0, 0, <fi#7>, 0, %R14D, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack2] LD8[FixedStack3] LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %RBX<kill>; mem:ST8[%bzerror.addr]
> MOV64mr <fi#2>, 1, %noreg, 0, %noreg, %R12<kill>; mem:ST8[%b.addr]
> MOV64mr <fi#3>, 1, %noreg, 0, %noreg, %R15<kill>; mem:ST8[%buf.addr]
> MOV32mr <fi#4>, 1, %noreg, 0, %noreg, %R14D<kill>; mem:ST4[%len.addr]
> %RAX<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr]
> MOV64mr <fi#7>, 1, %noreg, 0, %noreg, %RAX<kill>; mem:ST8[%bzf]
> CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
> JE_1 <BB#2>, %EFLAGS<imp-use,kill>
464B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
480B		%vreg17<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg17
496B		MOV32mi %vreg17<kill>, 1, %noreg, 0, %noreg, 0; mem:ST4[%3] GR64:%vreg17
	    Successors according to CFG: BB#2
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 0, %noreg, 0; mem:ST4[%3]
512B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#1
528B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
544B		JE_1 <BB#4>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#4 BB#3
> CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
> JE_1 <BB#4>, %EFLAGS<imp-use,kill>
560B	BB#3: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#2
576B		%vreg20<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg20
592B		MOV32mi %vreg20<kill>, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr] GR64:%vreg20
	    Successors according to CFG: BB#4
> %RAX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV32mi %RAX<kill>, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr]
608B	BB#4: derived from LLVM BB %if.end.3
	    Predecessors according to CFG: BB#2 BB#3
624B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
640B		JE_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#5
> CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
> JE_1 <BB#7>, %EFLAGS<imp-use,kill>
656B	BB#5: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#4
672B		CMP64mi8 <fi#3>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%buf.addr]
688B		JE_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#6
> CMP64mi8 <fi#3>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%buf.addr]
> JE_1 <BB#7>, %EFLAGS<imp-use,kill>
704B	BB#6: derived from LLVM BB %lor.lhs.false.6
	    Predecessors according to CFG: BB#5
720B		CMP32mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%len.addr]
736B		JGE_1 <BB#12>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#12 BB#7
> CMP32mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%len.addr]
> JGE_1 <BB#12>, %EFLAGS<imp-use,kill>
752B	BB#7: derived from LLVM BB %if.then.8
	    Predecessors according to CFG: BB#4 BB#5 BB#6
768B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
784B		JE_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#8
> CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
> JE_1 <BB#9>, %EFLAGS<imp-use,kill>
800B	BB#8: derived from LLVM BB %if.then.10
	    Predecessors according to CFG: BB#7
816B		%vreg181<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg181
832B		MOV32mi %vreg181<kill>, 1, %noreg, 0, %noreg, -2; mem:ST4[%10] GR64:%vreg181
	    Successors according to CFG: BB#9
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 0, %noreg, -2; mem:ST4[%10]
848B	BB#9: derived from LLVM BB %if.end.11
	    Predecessors according to CFG: BB#7 BB#8
864B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
880B		JE_1 <BB#11>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#11 BB#10
> CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
> JE_1 <BB#11>, %EFLAGS<imp-use,kill>
896B	BB#10: derived from LLVM BB %if.then.13
	    Predecessors according to CFG: BB#9
912B		%vreg184<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg184
928B		MOV32mi %vreg184<kill>, 1, %noreg, 5096, %noreg, -2; mem:ST4[%lastErr14] GR64:%vreg184
	    Successors according to CFG: BB#11
> %RAX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV32mi %RAX<kill>, 1, %noreg, 5096, %noreg, -2; mem:ST4[%lastErr14]
944B	BB#11: derived from LLVM BB %if.end.15
	    Predecessors according to CFG: BB#9 BB#10
960B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
976B		JMP_1 <BB#69>
	    Successors according to CFG: BB#69
> MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
> JMP_1 <BB#69>
992B	BB#12: derived from LLVM BB %if.end.16
	    Predecessors according to CFG: BB#6
1008B		%vreg26<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg26
1024B		CMP8mi %vreg26<kill>, 1, %noreg, 5012, %noreg, 0, %EFLAGS<imp-def>; mem:LD1[%writing] GR64:%vreg26
1040B		JE_1 <BB#18>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#18 BB#13
> %RAX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> CMP8mi %RAX<kill>, 1, %noreg, 5012, %noreg, 0, %EFLAGS<imp-def>; mem:LD1[%writing]
> JE_1 <BB#18>, %EFLAGS<imp-use,kill>
1056B	BB#13: derived from LLVM BB %if.then.17
	    Predecessors according to CFG: BB#12
1072B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
1088B		JE_1 <BB#15>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#15 BB#14
> CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
> JE_1 <BB#15>, %EFLAGS<imp-use,kill>
1104B	BB#14: derived from LLVM BB %if.then.19
	    Predecessors according to CFG: BB#13
1120B		%vreg175<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg175
1136B		MOV32mi %vreg175<kill>, 1, %noreg, 0, %noreg, -1; mem:ST4[%16] GR64:%vreg175
	    Successors according to CFG: BB#15
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 0, %noreg, -1; mem:ST4[%16]
1152B	BB#15: derived from LLVM BB %if.end.20
	    Predecessors according to CFG: BB#13 BB#14
1168B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
1184B		JE_1 <BB#17>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#17 BB#16
> CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
> JE_1 <BB#17>, %EFLAGS<imp-use,kill>
1200B	BB#16: derived from LLVM BB %if.then.22
	    Predecessors according to CFG: BB#15
1216B		%vreg178<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg178
1232B		MOV32mi %vreg178<kill>, 1, %noreg, 5096, %noreg, -1; mem:ST4[%lastErr23] GR64:%vreg178
	    Successors according to CFG: BB#17
> %RAX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV32mi %RAX<kill>, 1, %noreg, 5096, %noreg, -1; mem:ST4[%lastErr23]
1248B	BB#17: derived from LLVM BB %if.end.24
	    Predecessors according to CFG: BB#15 BB#16
1264B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
1280B		JMP_1 <BB#69>
	    Successors according to CFG: BB#69
> MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
> JMP_1 <BB#69>
1296B	BB#18: derived from LLVM BB %if.end.25
	    Predecessors according to CFG: BB#12
1312B		CMP32mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%len.addr]
1328B		JNE_1 <BB#24>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#24 BB#19
> CMP32mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%len.addr]
> JNE_1 <BB#24>, %EFLAGS<imp-use,kill>
1344B	BB#19: derived from LLVM BB %if.then.27
	    Predecessors according to CFG: BB#18
1360B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
1376B		JE_1 <BB#21>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#21 BB#20
> CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
> JE_1 <BB#21>, %EFLAGS<imp-use,kill>
1392B	BB#20: derived from LLVM BB %if.then.29
	    Predecessors according to CFG: BB#19
1408B		%vreg169<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg169
1424B		MOV32mi %vreg169<kill>, 1, %noreg, 0, %noreg, 0; mem:ST4[%21] GR64:%vreg169
	    Successors according to CFG: BB#21
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 0, %noreg, 0; mem:ST4[%21]
1440B	BB#21: derived from LLVM BB %if.end.30
	    Predecessors according to CFG: BB#19 BB#20
1456B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
1472B		JE_1 <BB#23>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#23 BB#22
> CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
> JE_1 <BB#23>, %EFLAGS<imp-use,kill>
1488B	BB#22: derived from LLVM BB %if.then.32
	    Predecessors according to CFG: BB#21
1504B		%vreg172<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg172
1520B		MOV32mi %vreg172<kill>, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr33] GR64:%vreg172
	    Successors according to CFG: BB#23
> %RAX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV32mi %RAX<kill>, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr33]
1536B	BB#23: derived from LLVM BB %if.end.34
	    Predecessors according to CFG: BB#21 BB#22
1552B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
1568B		JMP_1 <BB#69>
	    Successors according to CFG: BB#69
> MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
> JMP_1 <BB#69>
1584B	BB#24: derived from LLVM BB %if.end.35
	    Predecessors according to CFG: BB#18
1600B		%vreg35<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%len.addr] GR32:%vreg35
1616B		%vreg34<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg34
1632B		MOV32mr %vreg34<kill>, 1, %noreg, 5048, %noreg, %vreg35<kill>; mem:ST4[%avail_out] GR64:%vreg34 GR32:%vreg35
1648B		%vreg31<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%buf.addr] GR64:%vreg31
1664B		%vreg30<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg30
1680B		MOV64mr %vreg30<kill>, 1, %noreg, 5040, %noreg, %vreg31<kill>; mem:ST8[%next_out] GR64:%vreg30,%vreg31
	    Successors according to CFG: BB#25
> %EAX<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%len.addr]
> %RCX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV32mr %RCX<kill>, 1, %noreg, 5048, %noreg, %EAX<kill>; mem:ST4[%avail_out]
> %RAX<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%buf.addr]
> %RCX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV64mr %RCX<kill>, 1, %noreg, 5040, %noreg, %RAX<kill>; mem:ST8[%next_out]
1696B	BB#25: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#24 BB#68
1712B		%vreg41<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg41
1728B		%vreg40<def> = MOV64rm %vreg41<kill>, 1, %noreg, 0, %noreg; mem:LD8[%handle] GR64:%vreg40,%vreg41
1744B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1760B		%RDI<def> = COPY %vreg40<kill>; GR64:%vreg40
1776B		CALL64pcrel32 <ga:@ferror>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
1792B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1808B		%vreg38<def> = COPY %EAX; GR32:%vreg38
1824B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1840B		STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
1856B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1872B		CMP32ri8 %vreg38<kill>, 0, %EFLAGS<imp-def>; GR32:%vreg38
1888B		JE_1 <BB#31>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#31 BB#26
> %RAX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> %RDI<def> = MOV64rm %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%handle]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@ferror>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def> = COPY %EAX
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> CMP32ri8 %EAX<kill>, 0, %EFLAGS<imp-def>
> JE_1 <BB#31>, %EFLAGS<imp-use,kill>
1904B	BB#26: derived from LLVM BB %if.then.38
	    Predecessors according to CFG: BB#25
1920B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
1936B		JE_1 <BB#28>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#28 BB#27
> CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
> JE_1 <BB#28>, %EFLAGS<imp-use,kill>
1952B	BB#27: derived from LLVM BB %if.then.40
	    Predecessors according to CFG: BB#26
1968B		%vreg163<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg163
1984B		MOV32mi %vreg163<kill>, 1, %noreg, 0, %noreg, -6; mem:ST4[%31] GR64:%vreg163
	    Successors according to CFG: BB#28
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 0, %noreg, -6; mem:ST4[%31]
2000B	BB#28: derived from LLVM BB %if.end.41
	    Predecessors according to CFG: BB#26 BB#27
2016B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
2032B		JE_1 <BB#30>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#30 BB#29
> CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
> JE_1 <BB#30>, %EFLAGS<imp-use,kill>
2048B	BB#29: derived from LLVM BB %if.then.43
	    Predecessors according to CFG: BB#28
2064B		%vreg166<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg166
2080B		MOV32mi %vreg166<kill>, 1, %noreg, 5096, %noreg, -6; mem:ST4[%lastErr44] GR64:%vreg166
	    Successors according to CFG: BB#30
> %RAX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV32mi %RAX<kill>, 1, %noreg, 5096, %noreg, -6; mem:ST4[%lastErr44]
2096B	BB#30: derived from LLVM BB %if.end.45
	    Predecessors according to CFG: BB#28 BB#29
2112B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
2128B		JMP_1 <BB#69>
	    Successors according to CFG: BB#69
> MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
> JMP_1 <BB#69>
2144B	BB#31: derived from LLVM BB %if.end.46
	    Predecessors according to CFG: BB#25
2160B		%vreg44<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg44
2176B		CMP32mi8 %vreg44<kill>, 1, %noreg, 5024, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_in] GR64:%vreg44
2192B		JNE_1 <BB#40>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#40 BB#32
> %RAX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> CMP32mi8 %RAX<kill>, 1, %noreg, 5024, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_in]
> JNE_1 <BB#40>, %EFLAGS<imp-use,kill>
2208B	BB#32: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#31
2224B		%vreg50<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg50
2240B		%vreg49<def> = MOV64rm %vreg50<kill>, 1, %noreg, 0, %noreg; mem:LD8[%handle49] GR64:%vreg49,%vreg50
2256B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2272B		%RDI<def> = COPY %vreg49<kill>; GR64:%vreg49
2288B		CALL64pcrel32 <ga:@myfeof>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %AL<imp-def>
2304B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2320B		%vreg47<def> = COPY %AL; GR8:%vreg47
2336B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2352B		STACKMAP 2, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
2368B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2384B		CMP8ri %vreg47<kill>, 0, %EFLAGS<imp-def>; GR8:%vreg47
2400B		JNE_1 <BB#40>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#40 BB#33
> %RAX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> %RDI<def> = MOV64rm %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%handle49]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@myfeof>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %AL<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %AL<def> = COPY %AL
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 2, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> CMP8ri %AL<kill>, 0, %EFLAGS<imp-def>
> JNE_1 <BB#40>, %EFLAGS<imp-use,kill>
2416B	BB#33: derived from LLVM BB %if.then.52
	    Predecessors according to CFG: BB#32
2496B		%vreg72<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg72
2528B		%vreg72<def,tied1> = ADD64ri8 %vreg72<kill,tied0>, 8, %EFLAGS<imp-def,dead>; GR64:%vreg72
2544B		%vreg69<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg69
2560B		%vreg68<def> = MOV64rm %vreg69<kill>, 1, %noreg, 0, %noreg; mem:LD8[%handle54] GR64:%vreg68,%vreg69
2576B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2608B		%ESI<def,dead> = MOV32ri 1, %RSI<imp-def>
2624B		%EDX<def,dead> = MOV32ri 5000, %RDX<imp-def>
2632B		%RDI<def> = COPY %vreg72<kill>; GR64:%vreg72
2640B		%RCX<def> = COPY %vreg68<kill>; GR64:%vreg68
2656B		CALL64pcrel32 <ga:@fread>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %RDX<imp-use>, %RCX<imp-use>, %RAX<imp-def>
2672B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2688B		%vreg66<def> = COPY %RAX; GR64_with_sub_8bit:%vreg66
2704B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2720B		STACKMAP 3, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
2736B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2768B		MOV32mr <fi#5>, 1, %noreg, 0, %noreg, %vreg66:sub_32bit<kill>; mem:ST4[%n] GR64_with_sub_8bit:%vreg66
2784B		%vreg56<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg56
2800B		%vreg55<def> = MOV64rm %vreg56<kill>, 1, %noreg, 0, %noreg; mem:LD8[%handle56] GR64:%vreg55,%vreg56
2816B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2832B		%RDI<def> = COPY %vreg55<kill>; GR64:%vreg55
2848B		CALL64pcrel32 <ga:@ferror>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
2864B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2880B		%vreg53<def> = COPY %EAX; GR32:%vreg53
2896B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2912B		STACKMAP 4, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
2928B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2944B		CMP32ri8 %vreg53<kill>, 0, %EFLAGS<imp-def>; GR32:%vreg53
2960B		JE_1 <BB#39>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#39 BB#34
> %RDI<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> %RDI<def,tied1> = ADD64ri8 %RDI<kill,tied0>, 8, %EFLAGS<imp-def,dead>
> %RAX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> %RCX<def> = MOV64rm %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%handle54]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %ESI<def,dead> = MOV32ri 1, %RSI<imp-def>
> %EDX<def,dead> = MOV32ri 5000, %RDX<imp-def>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RCX<def> = COPY %RCX<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@fread>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %RDX<imp-use>, %RCX<imp-use>, %RAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RAX<def> = COPY %RAX
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 3, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV32mr <fi#5>, 1, %noreg, 0, %noreg, %EAX, %RAX<imp-use,kill>; mem:ST4[%n]
> %RAX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> %RDI<def> = MOV64rm %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%handle56]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@ferror>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def> = COPY %EAX
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 4, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> CMP32ri8 %EAX<kill>, 0, %EFLAGS<imp-def>
> JE_1 <BB#39>, %EFLAGS<imp-use,kill>
2976B	BB#34: derived from LLVM BB %if.then.59
	    Predecessors according to CFG: BB#33
2992B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
3008B		JE_1 <BB#36>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#36 BB#35
> CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
> JE_1 <BB#36>, %EFLAGS<imp-use,kill>
3024B	BB#35: derived from LLVM BB %if.then.62
	    Predecessors according to CFG: BB#34
3040B		%vreg93<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg93
3056B		MOV32mi %vreg93<kill>, 1, %noreg, 0, %noreg, -6; mem:ST4[%44] GR64:%vreg93
	    Successors according to CFG: BB#36
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 0, %noreg, -6; mem:ST4[%44]
3072B	BB#36: derived from LLVM BB %if.end.63
	    Predecessors according to CFG: BB#34 BB#35
3088B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
3104B		JE_1 <BB#38>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#38 BB#37
> CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
> JE_1 <BB#38>, %EFLAGS<imp-use,kill>
3120B	BB#37: derived from LLVM BB %if.then.66
	    Predecessors according to CFG: BB#36
3136B		%vreg96<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg96
3152B		MOV32mi %vreg96<kill>, 1, %noreg, 5096, %noreg, -6; mem:ST4[%lastErr67] GR64:%vreg96
	    Successors according to CFG: BB#38
> %RAX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV32mi %RAX<kill>, 1, %noreg, 5096, %noreg, -6; mem:ST4[%lastErr67]
3168B	BB#38: derived from LLVM BB %if.end.68
	    Predecessors according to CFG: BB#36 BB#37
3184B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
3200B		JMP_1 <BB#69>
	    Successors according to CFG: BB#69
> MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
> JMP_1 <BB#69>
3216B	BB#39: derived from LLVM BB %if.end.69
	    Predecessors according to CFG: BB#33
3232B		%vreg90<def> = MOV32rm <fi#5>, 1, %noreg, 0, %noreg; mem:LD4[%n] GR32:%vreg90
3248B		%vreg89<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg89
3264B		MOV32mr %vreg89<kill>, 1, %noreg, 5008, %noreg, %vreg90<kill>; mem:ST4[%bufN] GR64:%vreg89 GR32:%vreg90
3280B		%vreg86<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg86
3296B		%vreg85<def> = MOV32rm %vreg86<kill>, 1, %noreg, 5008, %noreg; mem:LD4[%bufN70] GR32:%vreg85 GR64:%vreg86
3312B		%vreg83<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg83
3328B		MOV32mr %vreg83<kill>, 1, %noreg, 5024, %noreg, %vreg85<kill>; mem:ST4[%avail_in72] GR64:%vreg83 GR32:%vreg85
3344B		%vreg79<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg79
3376B		%vreg79<def,tied1> = ADD64ri8 %vreg79<kill,tied0>, 8, %EFLAGS<imp-def,dead>; GR64:%vreg79
3392B		%vreg76<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg76
3408B		MOV64mr %vreg76<kill>, 1, %noreg, 5016, %noreg, %vreg79<kill>; mem:ST8[%next_in] GR64:%vreg76,%vreg79
	    Successors according to CFG: BB#40
> %EAX<def> = MOV32rm <fi#5>, 1, %noreg, 0, %noreg; mem:LD4[%n]
> %RCX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV32mr %RCX<kill>, 1, %noreg, 5008, %noreg, %EAX<kill>; mem:ST4[%bufN]
> %RAX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 5008, %noreg; mem:LD4[%bufN70]
> %RCX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV32mr %RCX<kill>, 1, %noreg, 5024, %noreg, %EAX<kill>; mem:ST4[%avail_in72]
> %RAX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> %RAX<def,tied1> = ADD64ri8 %RAX<kill,tied0>, 8, %EFLAGS<imp-def,dead>
> %RCX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV64mr %RCX<kill>, 1, %noreg, 5016, %noreg, %RAX<kill>; mem:ST8[%next_in]
3424B	BB#40: derived from LLVM BB %if.end.76
	    Predecessors according to CFG: BB#31 BB#32 BB#39
3440B		%vreg102<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg102
3472B		%vreg102<def,tied1> = ADD64ri32 %vreg102<kill,tied0>, 5016, %EFLAGS<imp-def,dead>; GR64:%vreg102
3488B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3504B		%RDI<def> = COPY %vreg102<kill>; GR64:%vreg102
3520B		CALL64pcrel32 <ga:@BZ2_bzDecompress>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
3536B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3552B		%vreg100<def> = COPY %EAX; GR32:%vreg100
3568B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3584B		STACKMAP 5, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
3600B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3616B		MOV32mr <fi#6>, 1, %noreg, 0, %noreg, %vreg100<kill>; mem:ST4[%ret] GR32:%vreg100
3632B		CMP32mi8 <fi#6>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%ret]
3648B		JE_1 <BB#47>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#47 BB#41
> %RDI<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> %RDI<def,tied1> = ADD64ri32 %RDI<kill,tied0>, 5016, %EFLAGS<imp-def,dead>
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@BZ2_bzDecompress>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def> = COPY %EAX
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 5, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV32mr <fi#6>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%ret]
> CMP32mi8 <fi#6>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%ret]
> JE_1 <BB#47>, %EFLAGS<imp-use,kill>
3664B	BB#41: derived from LLVM BB %land.lhs.true.81
	    Predecessors according to CFG: BB#40
3680B		CMP32mi8 <fi#6>, 1, %noreg, 0, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%ret]
3696B		JE_1 <BB#47>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#47 BB#42
> CMP32mi8 <fi#6>, 1, %noreg, 0, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%ret]
> JE_1 <BB#47>, %EFLAGS<imp-use,kill>
3712B	BB#42: derived from LLVM BB %if.then.84
	    Predecessors according to CFG: BB#41
3728B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
3744B		JE_1 <BB#44>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#44 BB#43
> CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
> JE_1 <BB#44>, %EFLAGS<imp-use,kill>
3760B	BB#43: derived from LLVM BB %if.then.87
	    Predecessors according to CFG: BB#42
3776B		%vreg155<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%ret] GR32:%vreg155
3792B		%vreg154<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg154
3808B		MOV32mr %vreg154<kill>, 1, %noreg, 0, %noreg, %vreg155<kill>; mem:ST4[%59] GR64:%vreg154 GR32:%vreg155
	    Successors according to CFG: BB#44
> %EAX<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%ret]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr]
> MOV32mr %RCX<kill>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%59]
3824B	BB#44: derived from LLVM BB %if.end.88
	    Predecessors according to CFG: BB#42 BB#43
3840B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
3856B		JE_1 <BB#46>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#46 BB#45
> CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
> JE_1 <BB#46>, %EFLAGS<imp-use,kill>
3872B	BB#45: derived from LLVM BB %if.then.91
	    Predecessors according to CFG: BB#44
3888B		%vreg160<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%ret] GR32:%vreg160
3904B		%vreg159<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg159
3920B		MOV32mr %vreg159<kill>, 1, %noreg, 5096, %noreg, %vreg160<kill>; mem:ST4[%lastErr92] GR64:%vreg159 GR32:%vreg160
	    Successors according to CFG: BB#46
> %EAX<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%ret]
> %RCX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV32mr %RCX<kill>, 1, %noreg, 5096, %noreg, %EAX<kill>; mem:ST4[%lastErr92]
3936B	BB#46: derived from LLVM BB %if.end.93
	    Predecessors according to CFG: BB#44 BB#45
3952B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
3968B		JMP_1 <BB#69>
	    Successors according to CFG: BB#69
> MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
> JMP_1 <BB#69>
3984B	BB#47: derived from LLVM BB %if.end.94
	    Predecessors according to CFG: BB#40 BB#41
4000B		CMP32mi8 <fi#6>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%ret]
4016B		JNE_1 <BB#56>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#56 BB#48
> CMP32mi8 <fi#6>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%ret]
> JNE_1 <BB#56>, %EFLAGS<imp-use,kill>
4032B	BB#48: derived from LLVM BB %land.lhs.true.97
	    Predecessors according to CFG: BB#47
4048B		%vreg113<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg113
4064B		%vreg112<def> = MOV64rm %vreg113<kill>, 1, %noreg, 0, %noreg; mem:LD8[%handle98] GR64:%vreg112,%vreg113
4080B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4096B		%RDI<def> = COPY %vreg112<kill>; GR64:%vreg112
4112B		CALL64pcrel32 <ga:@myfeof>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %AL<imp-def>
4128B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4144B		%vreg110<def> = COPY %AL; GR8:%vreg110
4160B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4176B		STACKMAP 6, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
4192B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4208B		%vreg108<def> = MOVZX32rr8 %vreg110<kill>; GR32:%vreg108 GR8:%vreg110
4224B		CMP32ri8 %vreg108<kill>, 0, %EFLAGS<imp-def>; GR32:%vreg108
4240B		JE_1 <BB#56>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#56 BB#49
> %RAX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> %RDI<def> = MOV64rm %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%handle98]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@myfeof>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %AL<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %AL<def> = COPY %AL
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 6, 0, 0, <fi#1>, 0, 0, <fi#7>, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#6>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack7] LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack6](align=4) LD8[FixedStack0](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def> = MOVZX32rr8 %AL<kill>
> CMP32ri8 %EAX<kill>, 0, %EFLAGS<imp-def>
> JE_1 <BB#56>, %EFLAGS<imp-use,kill>
4256B	BB#49: derived from LLVM BB %land.lhs.true.102
	    Predecessors according to CFG: BB#48
4272B		%vreg116<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg116
4288B		CMP32mi8 %vreg116<kill>, 1, %noreg, 5024, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_in104] GR64:%vreg116
4304B		JNE_1 <BB#56>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#56 BB#50
> %RAX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> CMP32mi8 %RAX<kill>, 1, %noreg, 5024, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_in104]
> JNE_1 <BB#56>, %EFLAGS<imp-use,kill>
4320B	BB#50: derived from LLVM BB %land.lhs.true.107
	    Predecessors according to CFG: BB#49
4336B		%vreg119<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg119
4352B		CMP32mi8 %vreg119<kill>, 1, %noreg, 5048, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_out109] GR64:%vreg119
4368B		JBE_1 <BB#56>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#56 BB#51
> %RAX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> CMP32mi8 %RAX<kill>, 1, %noreg, 5048, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_out109]
> JBE_1 <BB#56>, %EFLAGS<imp-use,kill>
4384B	BB#51: derived from LLVM BB %if.then.112
	    Predecessors according to CFG: BB#50
4400B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
4416B		JE_1 <BB#53>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#53 BB#52
> CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
> JE_1 <BB#53>, %EFLAGS<imp-use,kill>
4432B	BB#52: derived from LLVM BB %if.then.115
	    Predecessors according to CFG: BB#51
4448B		%vreg147<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg147
4464B		MOV32mi %vreg147<kill>, 1, %noreg, 0, %noreg, -7; mem:ST4[%71] GR64:%vreg147
	    Successors according to CFG: BB#53
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 0, %noreg, -7; mem:ST4[%71]
4480B	BB#53: derived from LLVM BB %if.end.116
	    Predecessors according to CFG: BB#51 BB#52
4496B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
4512B		JE_1 <BB#55>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#55 BB#54
> CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
> JE_1 <BB#55>, %EFLAGS<imp-use,kill>
4528B	BB#54: derived from LLVM BB %if.then.119
	    Predecessors according to CFG: BB#53
4544B		%vreg150<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg150
4560B		MOV32mi %vreg150<kill>, 1, %noreg, 5096, %noreg, -7; mem:ST4[%lastErr120] GR64:%vreg150
	    Successors according to CFG: BB#55
> %RAX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV32mi %RAX<kill>, 1, %noreg, 5096, %noreg, -7; mem:ST4[%lastErr120]
4576B	BB#55: derived from LLVM BB %if.end.121
	    Predecessors according to CFG: BB#53 BB#54
4592B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
4608B		JMP_1 <BB#69>
	    Successors according to CFG: BB#69
> MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
> JMP_1 <BB#69>
4624B	BB#56: derived from LLVM BB %if.end.122
	    Predecessors according to CFG: BB#47 BB#48 BB#49 BB#50
4640B		CMP32mi8 <fi#6>, 1, %noreg, 0, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%ret]
4656B		JNE_1 <BB#62>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#62 BB#57
> CMP32mi8 <fi#6>, 1, %noreg, 0, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%ret]
> JNE_1 <BB#62>, %EFLAGS<imp-use,kill>
4672B	BB#57: derived from LLVM BB %if.then.125
	    Predecessors according to CFG: BB#56
4688B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
4704B		JE_1 <BB#59>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#59 BB#58
> CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
> JE_1 <BB#59>, %EFLAGS<imp-use,kill>
4720B	BB#58: derived from LLVM BB %if.then.128
	    Predecessors according to CFG: BB#57
4736B		%vreg134<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg134
4752B		MOV32mi %vreg134<kill>, 1, %noreg, 0, %noreg, 4; mem:ST4[%76] GR64:%vreg134
	    Successors according to CFG: BB#59
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 0, %noreg, 4; mem:ST4[%76]
4768B	BB#59: derived from LLVM BB %if.end.129
	    Predecessors according to CFG: BB#57 BB#58
4784B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
4800B		JE_1 <BB#61>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#61 BB#60
> CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
> JE_1 <BB#61>, %EFLAGS<imp-use,kill>
4816B	BB#60: derived from LLVM BB %if.then.132
	    Predecessors according to CFG: BB#59
4832B		%vreg137<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg137
4848B		MOV32mi %vreg137<kill>, 1, %noreg, 5096, %noreg, 4; mem:ST4[%lastErr133] GR64:%vreg137
	    Successors according to CFG: BB#61
> %RAX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV32mi %RAX<kill>, 1, %noreg, 5096, %noreg, 4; mem:ST4[%lastErr133]
4864B	BB#61: derived from LLVM BB %if.end.134
	    Predecessors according to CFG: BB#59 BB#60
4880B		%vreg141<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%len.addr] GR32:%vreg141
4896B		%vreg143<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg143
4928B		%vreg141<def,tied1> = SUB32rm %vreg141<kill,tied0>, %vreg143<kill>, 1, %noreg, 5048, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%avail_out136] GR32:%vreg141 GR64:%vreg143
4944B		MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %vreg141<kill>; mem:ST4[%retval] GR32:%vreg141
4960B		JMP_1 <BB#69>
	    Successors according to CFG: BB#69
> %EAX<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%len.addr]
> %RCX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> %EAX<def,tied1> = SUB32rm %EAX<kill,tied0>, %RCX<kill>, 1, %noreg, 5048, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%avail_out136]
> MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%retval]
> JMP_1 <BB#69>
4976B	BB#62: derived from LLVM BB %if.end.137
	    Predecessors according to CFG: BB#56
4992B		%vreg123<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg123
5008B		CMP32mi8 %vreg123<kill>, 1, %noreg, 5048, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_out139] GR64:%vreg123
5024B		JNE_1 <BB#68>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#68 BB#63
> %RAX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> CMP32mi8 %RAX<kill>, 1, %noreg, 5048, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_out139]
> JNE_1 <BB#68>, %EFLAGS<imp-use,kill>
5040B	BB#63: derived from LLVM BB %if.then.142
	    Predecessors according to CFG: BB#62
5056B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
5072B		JE_1 <BB#65>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#65 BB#64
> CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
> JE_1 <BB#65>, %EFLAGS<imp-use,kill>
5088B	BB#64: derived from LLVM BB %if.then.145
	    Predecessors according to CFG: BB#63
5104B		%vreg126<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg126
5120B		MOV32mi %vreg126<kill>, 1, %noreg, 0, %noreg, 0; mem:ST4[%85] GR64:%vreg126
	    Successors according to CFG: BB#65
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 0, %noreg, 0; mem:ST4[%85]
5136B	BB#65: derived from LLVM BB %if.end.146
	    Predecessors according to CFG: BB#63 BB#64
5152B		CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
5168B		JE_1 <BB#67>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#67 BB#66
> CMP64mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
> JE_1 <BB#67>, %EFLAGS<imp-use,kill>
5184B	BB#66: derived from LLVM BB %if.then.149
	    Predecessors according to CFG: BB#65
5200B		%vreg129<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg129
5216B		MOV32mi %vreg129<kill>, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr150] GR64:%vreg129
	    Successors according to CFG: BB#67
> %RAX<def> = MOV64rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV32mi %RAX<kill>, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr150]
5232B	BB#67: derived from LLVM BB %if.end.151
	    Predecessors according to CFG: BB#65 BB#66
5248B		%vreg131<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%len.addr] GR32:%vreg131
5264B		MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %vreg131<kill>; mem:ST4[%retval] GR32:%vreg131
5280B		JMP_1 <BB#69>
	    Successors according to CFG: BB#69
> %EAX<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%len.addr]
> MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%retval]
> JMP_1 <BB#69>
5296B	BB#68: derived from LLVM BB %if.end.152
	    Predecessors according to CFG: BB#62
5312B		JMP_1 <BB#25>
	    Successors according to CFG: BB#25
> JMP_1 <BB#25>
5328B	BB#69: derived from LLVM BB %return
	    Predecessors according to CFG: BB#38 BB#67 BB#61 BB#55 BB#46 BB#30 BB#23 BB#17 BB#11
5344B		%vreg188<def> = MOV64ri <ga:@BZ2_bzRead>; GR64:%vreg188
5376B		%vreg189<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg189
5392B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5408B		%RDI<def> = COPY %vreg188<kill>; GR64:%vreg188
5424B		%RSI<def> = COPY %vreg189<kill>; GR64:%vreg189
5440B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
5456B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5472B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5488B		STACKMAP 7, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
5504B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5520B		%vreg186<def> = MOV32rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD4[%retval] GR32:%vreg186
5536B		%EAX<def> = COPY %vreg186<kill>; GR32:%vreg186
5552B		RETQ %EAX<imp-use>
> %RDI<def> = MOV64ri <ga:@BZ2_bzRead>
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 7, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def> = MOV32rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD4[%retval]
> %EAX<def> = COPY %EAX<kill>
Deleting identity copy.
> RETQ %EAX<imp-use>
Computing live-in reg-units in ABI blocks.
0B	BB#0 DIL#0
Created 1 new intervals.
********** INTERVALS **********
DIL [0B,16r:0)[112r,144r:3)[272r,288r:4)[544r,576r:1)[768r,800r:2)  0@0B-phi 1@544r 2@768r 3@112r 4@272r
%vreg0 [16r,32r:0)  0@16r
%vreg1 [32r,224r:0)  0@32r
%vreg5 [320r,384r:0)  0@320r
%vreg6 [240r,272r:0)  0@240r
%vreg7 [48r,64r:0)  0@48r
%vreg8 [64r,112r:0)  0@64r
%vreg9 [80r,128r:0)  0@80r
%vreg12 [608r,608d:0)  0@608r
%vreg13 [512r,560r:0)  0@512r
%vreg14 [496r,544r:0)  0@496r
%vreg16 [880r,896r:0)  0@880r
%vreg17 [704r,720r:0)  0@704r
%vreg18 [720r,768r:0)  0@720r
%vreg19 [736r,784r:0)  0@736r
RegMasks: 144r 288r 576r 800r
********** MACHINEINSTRS **********
# Machine code for function myfeof: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=1, align=1, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=4, align=4, at location [SP+8]
Function Live Ins: %RDI in %vreg0

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI
16B		%vreg0<def> = COPY %RDI; GR64:%vreg0
32B		%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
48B		%vreg7<def> = MOV64ri <ga:@myfeof>; GR64:%vreg7
64B		%vreg8<def> = COPY %vreg7; GR64:%vreg8,%vreg7
80B		%vreg9<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg9
96B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
112B		%RDI<def> = COPY %vreg8; GR64:%vreg8
128B		%RSI<def> = COPY %vreg9; GR64:%vreg9
144B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
160B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
192B		STACKMAP 0, 0, 0, <fi#2>, 0, %vreg1, 0, <fi#1>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack1] LD8[FixedStack0](align=1) GR64:%vreg1
208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%f.addr] GR64:%vreg1
240B		%vreg6<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%f.addr] GR64:%vreg6
256B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
272B		%RDI<def> = COPY %vreg6; GR64:%vreg6
288B		CALL64pcrel32 <ga:@fgetc>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
304B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
320B		%vreg5<def> = COPY %EAX<kill>; GR32:%vreg5
336B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
352B		STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack1] LD8[FixedStack0](align=1)
368B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
384B		MOV32mr <fi#2>, 1, %noreg, 0, %noreg, %vreg5; mem:ST4[%c] GR32:%vreg5
400B		CMP32mi8 <fi#2>, 1, %noreg, 0, %noreg, -1, %EFLAGS<imp-def>; mem:LD4[%c]
416B		JNE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

432B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
448B		MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 1; mem:ST1[%retval]
464B		JMP_1 <BB#3>
	    Successors according to CFG: BB#3

480B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0
496B		%vreg14<def> = MOV32rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD4[%c] GR32:%vreg14
512B		%vreg13<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%f.addr] GR64:%vreg13
528B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
544B		%EDI<def> = COPY %vreg14; GR32:%vreg14
560B		%RSI<def> = COPY %vreg13; GR64:%vreg13
576B		CALL64pcrel32 <ga:@ungetc>, <regmask>, %RSP<imp-use>, %EDI<imp-use>, %RSI<imp-use,kill>, %EAX<imp-def>
592B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
608B		%vreg12<def,dead> = COPY %EAX<kill>; GR32:%vreg12
624B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
640B		STACKMAP 2, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=1)
656B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
672B		MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST1[%retval]
	    Successors according to CFG: BB#3

688B	BB#3: derived from LLVM BB %return
	    Predecessors according to CFG: BB#2 BB#1
704B		%vreg17<def> = MOV64ri <ga:@myfeof>; GR64:%vreg17
720B		%vreg18<def> = COPY %vreg17; GR64:%vreg18,%vreg17
736B		%vreg19<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg19
752B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
768B		%RDI<def> = COPY %vreg18; GR64:%vreg18
784B		%RSI<def> = COPY %vreg19; GR64:%vreg19
800B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
816B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
832B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
848B		STACKMAP 3, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=1)
864B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
880B		%vreg16<def> = MOV8rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD1[%retval] GR8:%vreg16
896B		%AL<def> = COPY %vreg16; GR8:%vreg16
912B		RETQ %AL<imp-use,kill>

# End machine code for function myfeof.

********** SIMPLE REGISTER COALESCING **********
********** Function: myfeof
********** JOINING INTERVALS ***********
entry:
16B	%vreg0<def> = COPY %RDI; GR64:%vreg0
	Considering merging %vreg0 with %RDI
	Can only merge into reserved registers.
112B	%RDI<def> = COPY %vreg8; GR64:%vreg8
	Considering merging %vreg8 with %RDI
	Can only merge into reserved registers.
128B	%RSI<def> = COPY %vreg9; GR64:%vreg9
	Considering merging %vreg9 with %RSI
	Can only merge into reserved registers.
272B	%RDI<def> = COPY %vreg6; GR64:%vreg6
	Considering merging %vreg6 with %RDI
	Can only merge into reserved registers.
320B	%vreg5<def> = COPY %EAX<kill>; GR32:%vreg5
	Considering merging %vreg5 with %EAX
	Can only merge into reserved registers.
if.then:
if.end:
544B	%EDI<def> = COPY %vreg14; GR32:%vreg14
	Considering merging %vreg14 with %EDI
	Can only merge into reserved registers.
560B	%RSI<def> = COPY %vreg13; GR64:%vreg13
	Considering merging %vreg13 with %RSI
	Can only merge into reserved registers.
608B	%vreg12<def,dead> = COPY %EAX<kill>; GR32:%vreg12
	Considering merging %vreg12 with %EAX
	Can only merge into reserved registers.
return:
768B	%RDI<def> = COPY %vreg18; GR64:%vreg18
	Considering merging %vreg18 with %RDI
	Can only merge into reserved registers.
784B	%RSI<def> = COPY %vreg19; GR64:%vreg19
	Considering merging %vreg19 with %RSI
	Can only merge into reserved registers.
896B	%AL<def> = COPY %vreg16; GR8:%vreg16
	Considering merging %vreg16 with %AL
	Can only merge into reserved registers.
32B	%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
	Considering merging to GR64 with %vreg0 in %vreg1
		RHS = %vreg0 [16r,32r:0)  0@16r
		LHS = %vreg1 [32r,224r:0)  0@32r
		merge %vreg1:0@32r into %vreg0:0@16r --> @16r
		erased:	32r	%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
		updated: 16B	%vreg1<def> = COPY %RDI; GR64:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [16r,224r:0)  0@16r
64B	%vreg8<def> = COPY %vreg7; GR64:%vreg8,%vreg7
	Considering merging to GR64 with %vreg7 in %vreg8
		RHS = %vreg7 [48r,64r:0)  0@48r
		LHS = %vreg8 [64r,112r:0)  0@64r
		merge %vreg8:0@64r into %vreg7:0@48r --> @48r
		erased:	64r	%vreg8<def> = COPY %vreg7; GR64:%vreg8,%vreg7
		updated: 48B	%vreg8<def> = MOV64ri <ga:@myfeof>; GR64:%vreg8
	Success: %vreg7 -> %vreg8
	Result = %vreg8 [48r,112r:0)  0@48r
720B	%vreg18<def> = COPY %vreg17; GR64:%vreg18,%vreg17
	Considering merging to GR64 with %vreg17 in %vreg18
		RHS = %vreg17 [704r,720r:0)  0@704r
		LHS = %vreg18 [720r,768r:0)  0@720r
		merge %vreg18:0@720r into %vreg17:0@704r --> @704r
		erased:	720r	%vreg18<def> = COPY %vreg17; GR64:%vreg18,%vreg17
		updated: 704B	%vreg18<def> = MOV64ri <ga:@myfeof>; GR64:%vreg18
	Success: %vreg17 -> %vreg18
	Result = %vreg18 [704r,768r:0)  0@704r
112B	%RDI<def> = COPY %vreg8; GR64:%vreg8
	Considering merging %vreg8 with %RDI
	Can only merge into reserved registers.
768B	%RDI<def> = COPY %vreg18; GR64:%vreg18
	Considering merging %vreg18 with %RDI
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
DIL [0B,16r:0)[112r,144r:3)[272r,288r:4)[544r,576r:1)[768r,800r:2)  0@0B-phi 1@544r 2@768r 3@112r 4@272r
%vreg1 [16r,224r:0)  0@16r
%vreg5 [320r,384r:0)  0@320r
%vreg6 [240r,272r:0)  0@240r
%vreg8 [48r,112r:0)  0@48r
%vreg9 [80r,128r:0)  0@80r
%vreg12 [608r,608d:0)  0@608r
%vreg13 [512r,560r:0)  0@512r
%vreg14 [496r,544r:0)  0@496r
%vreg16 [880r,896r:0)  0@880r
%vreg18 [704r,768r:0)  0@704r
%vreg19 [736r,784r:0)  0@736r
RegMasks: 144r 288r 576r 800r
********** MACHINEINSTRS **********
# Machine code for function myfeof: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=1, align=1, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=4, align=4, at location [SP+8]
Function Live Ins: %RDI in %vreg0

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI
16B		%vreg1<def> = COPY %RDI; GR64:%vreg1
48B		%vreg8<def> = MOV64ri <ga:@myfeof>; GR64:%vreg8
80B		%vreg9<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg9
96B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
112B		%RDI<def> = COPY %vreg8; GR64:%vreg8
128B		%RSI<def> = COPY %vreg9; GR64:%vreg9
144B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
160B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
192B		STACKMAP 0, 0, 0, <fi#2>, 0, %vreg1, 0, <fi#1>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack1] LD8[FixedStack0](align=1) GR64:%vreg1
208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%f.addr] GR64:%vreg1
240B		%vreg6<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%f.addr] GR64:%vreg6
256B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
272B		%RDI<def> = COPY %vreg6; GR64:%vreg6
288B		CALL64pcrel32 <ga:@fgetc>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
304B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
320B		%vreg5<def> = COPY %EAX<kill>; GR32:%vreg5
336B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
352B		STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack1] LD8[FixedStack0](align=1)
368B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
384B		MOV32mr <fi#2>, 1, %noreg, 0, %noreg, %vreg5; mem:ST4[%c] GR32:%vreg5
400B		CMP32mi8 <fi#2>, 1, %noreg, 0, %noreg, -1, %EFLAGS<imp-def>; mem:LD4[%c]
416B		JNE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

432B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
448B		MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 1; mem:ST1[%retval]
464B		JMP_1 <BB#3>
	    Successors according to CFG: BB#3

480B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0
496B		%vreg14<def> = MOV32rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD4[%c] GR32:%vreg14
512B		%vreg13<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%f.addr] GR64:%vreg13
528B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
544B		%EDI<def> = COPY %vreg14; GR32:%vreg14
560B		%RSI<def> = COPY %vreg13; GR64:%vreg13
576B		CALL64pcrel32 <ga:@ungetc>, <regmask>, %RSP<imp-use>, %EDI<imp-use>, %RSI<imp-use,kill>, %EAX<imp-def>
592B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
608B		%vreg12<def,dead> = COPY %EAX<kill>; GR32:%vreg12
624B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
640B		STACKMAP 2, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=1)
656B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
672B		MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST1[%retval]
	    Successors according to CFG: BB#3

688B	BB#3: derived from LLVM BB %return
	    Predecessors according to CFG: BB#2 BB#1
704B		%vreg18<def> = MOV64ri <ga:@myfeof>; GR64:%vreg18
736B		%vreg19<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg19
752B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
768B		%RDI<def> = COPY %vreg18; GR64:%vreg18
784B		%RSI<def> = COPY %vreg19; GR64:%vreg19
800B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
816B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
832B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
848B		STACKMAP 3, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=1)
864B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
880B		%vreg16<def> = MOV8rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD1[%retval] GR8:%vreg16
896B		%AL<def> = COPY %vreg16; GR8:%vreg16
912B		RETQ %AL<imp-use,kill>

# End machine code for function myfeof.

********** GREEDY REGISTER ALLOCATION **********
********** Function: myfeof
********** INTERVALS **********
DIL [0B,16r:0)[112r,144r:3)[272r,288r:4)[544r,576r:1)[768r,800r:2)  0@0B-phi 1@544r 2@768r 3@112r 4@272r
%vreg1 [16r,224r:0)  0@16r
%vreg5 [320r,384r:0)  0@320r
%vreg6 [240r,272r:0)  0@240r
%vreg8 [48r,112r:0)  0@48r
%vreg9 [80r,128r:0)  0@80r
%vreg12 [608r,608d:0)  0@608r
%vreg13 [512r,560r:0)  0@512r
%vreg14 [496r,544r:0)  0@496r
%vreg16 [880r,896r:0)  0@880r
%vreg18 [704r,768r:0)  0@704r
%vreg19 [736r,784r:0)  0@736r
RegMasks: 144r 288r 576r 800r
********** MACHINEINSTRS **********
# Machine code for function myfeof: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=1, align=1, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=4, align=4, at location [SP+8]
Function Live Ins: %RDI in %vreg0

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI
16B		%vreg1<def> = COPY %RDI; GR64:%vreg1
48B		%vreg8<def> = MOV64ri <ga:@myfeof>; GR64:%vreg8
80B		%vreg9<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg9
96B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
112B		%RDI<def> = COPY %vreg8; GR64:%vreg8
128B		%RSI<def> = COPY %vreg9; GR64:%vreg9
144B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
160B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
192B		STACKMAP 0, 0, 0, <fi#2>, 0, %vreg1, 0, <fi#1>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack1] LD8[FixedStack0](align=1) GR64:%vreg1
208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%f.addr] GR64:%vreg1
240B		%vreg6<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%f.addr] GR64:%vreg6
256B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
272B		%RDI<def> = COPY %vreg6; GR64:%vreg6
288B		CALL64pcrel32 <ga:@fgetc>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
304B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
320B		%vreg5<def> = COPY %EAX<kill>; GR32:%vreg5
336B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
352B		STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack1] LD8[FixedStack0](align=1)
368B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
384B		MOV32mr <fi#2>, 1, %noreg, 0, %noreg, %vreg5; mem:ST4[%c] GR32:%vreg5
400B		CMP32mi8 <fi#2>, 1, %noreg, 0, %noreg, -1, %EFLAGS<imp-def>; mem:LD4[%c]
416B		JNE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

432B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
448B		MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 1; mem:ST1[%retval]
464B		JMP_1 <BB#3>
	    Successors according to CFG: BB#3

480B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0
496B		%vreg14<def> = MOV32rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD4[%c] GR32:%vreg14
512B		%vreg13<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%f.addr] GR64:%vreg13
528B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
544B		%EDI<def> = COPY %vreg14; GR32:%vreg14
560B		%RSI<def> = COPY %vreg13; GR64:%vreg13
576B		CALL64pcrel32 <ga:@ungetc>, <regmask>, %RSP<imp-use>, %EDI<imp-use>, %RSI<imp-use,kill>, %EAX<imp-def>
592B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
608B		%vreg12<def,dead> = COPY %EAX<kill>; GR32:%vreg12
624B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
640B		STACKMAP 2, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=1)
656B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
672B		MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST1[%retval]
	    Successors according to CFG: BB#3

688B	BB#3: derived from LLVM BB %return
	    Predecessors according to CFG: BB#2 BB#1
704B		%vreg18<def> = MOV64ri <ga:@myfeof>; GR64:%vreg18
736B		%vreg19<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg19
752B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
768B		%RDI<def> = COPY %vreg18; GR64:%vreg18
784B		%RSI<def> = COPY %vreg19; GR64:%vreg19
800B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
816B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
832B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
848B		STACKMAP 3, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=1)
864B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
880B		%vreg16<def> = MOV8rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD1[%retval] GR8:%vreg16
896B		%AL<def> = COPY %vreg16; GR8:%vreg16
912B		RETQ %AL<imp-use,kill>

# End machine code for function myfeof.


selectOrSplit GR64:%vreg1 [16r,224r:0)  0@16r w=4.983553e-03
hints: %RDI
missed hint %RDI
assigning %vreg1 to %RBX: BH [16r,224r:0)  0@16r BL [16r,224r:0)  0@16r

selectOrSplit GR64:%vreg8 [48r,112r:0)  0@48r w=2.176724e-03
hints: %RDI
assigning %vreg8 to %RDI: DIL [48r,112r:0)  0@48r

selectOrSplit GR64:%vreg9 [80r,128r:0)  0@80r w=4.508928e-03
hints: %RSI
assigning %vreg9 to %RSI: SIL [80r,128r:0)  0@80r

selectOrSplit GR64:%vreg6 [240r,272r:0)  0@240r w=4.675926e-03
hints: %RDI
assigning %vreg6 to %RDI: DIL [240r,272r:0)  0@240r

selectOrSplit GR32:%vreg5 [320r,384r:0)  0@320r w=4.353448e-03
hints: %EAX
assigning %vreg5 to %EAX: AH [320r,384r:0)  0@320r AL [320r,384r:0)  0@320r

selectOrSplit GR32:%vreg14 [496r,544r:0)  0@496r w=2.254464e-03
hints: %EDI
assigning %vreg14 to %EDI: DIL [496r,544r:0)  0@496r

selectOrSplit GR64:%vreg13 [512r,560r:0)  0@512r w=2.254464e-03
hints: %RSI
assigning %vreg13 to %RSI: SIL [512r,560r:0)  0@512r

selectOrSplit GR32:%vreg12 [608r,608d:0)  0@608r w=inf
hints: %EAX
assigning %vreg12 to %EAX: AH [608r,608d:0)  0@608r AL [608r,608d:0)  0@608r

selectOrSplit GR64:%vreg18 [704r,768r:0)  0@704r w=2.176724e-03
hints: %RDI
assigning %vreg18 to %RDI: DIL [704r,768r:0)  0@704r

selectOrSplit GR64:%vreg19 [736r,784r:0)  0@736r w=4.508928e-03
hints: %RSI
assigning %vreg19 to %RSI: SIL [736r,784r:0)  0@736r

selectOrSplit GR8:%vreg16 [880r,896r:0)  0@880r w=inf
hints: %AL
assigning %vreg16 to %AL: AL [880r,896r:0)  0@880r

********** STACK TRANSFORMATION METADATA **********
********** Function: myfeof
********** REGISTER MAP **********
[%vreg1 -> %RBX] GR64
[%vreg5 -> %EAX] GR32
[%vreg6 -> %RDI] GR64
[%vreg8 -> %RDI] GR64
[%vreg9 -> %RSI] GR64
[%vreg12 -> %EAX] GR32
[%vreg13 -> %RSI] GR64
[%vreg14 -> %EDI] GR32
[%vreg16 -> %AL] GR8
[%vreg18 -> %RDI] GR64
[%vreg19 -> %RSI] GR64


Stackmap 0:
  STACKMAP 0, 0, 0, <fi#2>, 0, %vreg1, 0, <fi#1>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack1] LD8[FixedStack0](align=1) GR64:%vreg1

i32* %c: in stack slot 2 (size: 4)
%struct._IO_FILE* %f: in register %RBX (vreg 1)
%struct._IO_FILE** %f.addr: in stack slot 1 (size: 8)
i8* %retval: in stack slot 0 (size: 1)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack1] LD8[FixedStack0](align=1)

i32* %c: in stack slot 2 (size: 4)
%struct._IO_FILE** %f.addr: in stack slot 1 (size: 8)
i8* %retval: in stack slot 0 (size: 1)

Duplicate operand locations:


Stackmap 2:
  STACKMAP 2, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=1)

i8* %retval: in stack slot 0 (size: 1)

Duplicate operand locations:


Stackmap 3:
  STACKMAP 3, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=1)

i8* %retval: in stack slot 0 (size: 1)

Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, 0, <fi#2>, 0, %vreg1, 0, <fi#1>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack1] LD8[FixedStack0](align=1) GR64:%vreg1
  -> Call instruction SlotIndex 144B, searching vregs 0 -> 20 and stack slots -1 -> 3

  STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack1] LD8[FixedStack0](align=1)
  -> Call instruction SlotIndex 288B, searching vregs 0 -> 20 and stack slots -1 -> 3

  STACKMAP 2, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=1)
  -> Call instruction SlotIndex 576B, searching vregs 0 -> 20 and stack slots -1 -> 3

  STACKMAP 3, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=1)
  -> Call instruction SlotIndex 800B, searching vregs 0 -> 20 and stack slots -1 -> 3

********** REWRITE VIRTUAL REGISTERS **********
********** Function: myfeof
********** REGISTER MAP **********
[%vreg1 -> %RBX] GR64
[%vreg5 -> %EAX] GR32
[%vreg6 -> %RDI] GR64
[%vreg8 -> %RDI] GR64
[%vreg9 -> %RSI] GR64
[%vreg12 -> %EAX] GR32
[%vreg13 -> %RSI] GR64
[%vreg14 -> %EDI] GR32
[%vreg16 -> %AL] GR8
[%vreg18 -> %RDI] GR64
[%vreg19 -> %RSI] GR64

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI
16B		%vreg1<def> = COPY %RDI; GR64:%vreg1
48B		%vreg8<def> = MOV64ri <ga:@myfeof>; GR64:%vreg8
80B		%vreg9<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg9
96B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
112B		%RDI<def> = COPY %vreg8<kill>; GR64:%vreg8
128B		%RSI<def> = COPY %vreg9<kill>; GR64:%vreg9
144B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
160B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
192B		STACKMAP 0, 0, 0, <fi#2>, 0, %vreg1, 0, <fi#1>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack1] LD8[FixedStack0](align=1) GR64:%vreg1
208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg1<kill>; mem:ST8[%f.addr] GR64:%vreg1
240B		%vreg6<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%f.addr] GR64:%vreg6
256B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
272B		%RDI<def> = COPY %vreg6<kill>; GR64:%vreg6
288B		CALL64pcrel32 <ga:@fgetc>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
304B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
320B		%vreg5<def> = COPY %EAX; GR32:%vreg5
336B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
352B		STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack1] LD8[FixedStack0](align=1)
368B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
384B		MOV32mr <fi#2>, 1, %noreg, 0, %noreg, %vreg5<kill>; mem:ST4[%c] GR32:%vreg5
400B		CMP32mi8 <fi#2>, 1, %noreg, 0, %noreg, -1, %EFLAGS<imp-def>; mem:LD4[%c]
416B		JNE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1
> %RBX<def> = COPY %RDI
> %RDI<def> = MOV64ri <ga:@myfeof>
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 0, 0, 0, <fi#2>, 0, %RBX, 0, <fi#1>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack1] LD8[FixedStack0](align=1)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %RBX<kill>; mem:ST8[%f.addr]
> %RDI<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%f.addr]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@fgetc>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def> = COPY %EAX
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 1, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack2](align=4) LD8[FixedStack1] LD8[FixedStack0](align=1)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV32mr <fi#2>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%c]
> CMP32mi8 <fi#2>, 1, %noreg, 0, %noreg, -1, %EFLAGS<imp-def>; mem:LD4[%c]
> JNE_1 <BB#2>, %EFLAGS<imp-use,kill>
432B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
448B		MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 1; mem:ST1[%retval]
464B		JMP_1 <BB#3>
	    Successors according to CFG: BB#3
> MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 1; mem:ST1[%retval]
> JMP_1 <BB#3>
480B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0
496B		%vreg14<def> = MOV32rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD4[%c] GR32:%vreg14
512B		%vreg13<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%f.addr] GR64:%vreg13
528B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
544B		%EDI<def> = COPY %vreg14<kill>; GR32:%vreg14
560B		%RSI<def> = COPY %vreg13<kill>; GR64:%vreg13
576B		CALL64pcrel32 <ga:@ungetc>, <regmask>, %RSP<imp-use>, %EDI<imp-use>, %RSI<imp-use>, %EAX<imp-def>
592B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
608B		%vreg12<def,dead> = COPY %EAX; GR32:%vreg12
624B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
640B		STACKMAP 2, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=1)
656B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
672B		MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST1[%retval]
	    Successors according to CFG: BB#3
> %EDI<def> = MOV32rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD4[%c]
> %RSI<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%f.addr]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EDI<def> = COPY %EDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@ungetc>, <regmask>, %RSP<imp-use>, %EDI<imp-use>, %RSI<imp-use>, %EAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def,dead> = COPY %EAX
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 2, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=1)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV8mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST1[%retval]
688B	BB#3: derived from LLVM BB %return
	    Predecessors according to CFG: BB#2 BB#1
704B		%vreg18<def> = MOV64ri <ga:@myfeof>; GR64:%vreg18
736B		%vreg19<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg19
752B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
768B		%RDI<def> = COPY %vreg18<kill>; GR64:%vreg18
784B		%RSI<def> = COPY %vreg19<kill>; GR64:%vreg19
800B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
816B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
832B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
848B		STACKMAP 3, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=1)
864B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
880B		%vreg16<def> = MOV8rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD1[%retval] GR8:%vreg16
896B		%AL<def> = COPY %vreg16<kill>; GR8:%vreg16
912B		RETQ %AL<imp-use>
> %RDI<def> = MOV64ri <ga:@myfeof>
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 3, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=1)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %AL<def> = MOV8rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD1[%retval]
> %AL<def> = COPY %AL<kill>
Deleting identity copy.
> RETQ %AL<imp-use>
Computing live-in reg-units in ABI blocks.
0B	BB#0 DIL#0 SIL#0 DH#0 DL#0 CH#0 CL#0
Created 6 new intervals.
********** INTERVALS **********
CH [0B,16r:0)  0@0B-phi
CL [0B,16r:0)  0@0B-phi
DH [0B,32r:0)  0@0B-phi
DIL [0B,64r:0)[208r,240r:2)[1712r,1744r:1)  0@0B-phi 1@1712r 2@208r
DL [0B,32r:0)  0@0B-phi
SIL [0B,48r:0)[224r,240r:2)[1728r,1744r:1)  0@0B-phi 1@1728r 2@224r
%vreg0 [64r,80r:0)  0@64r
%vreg1 [80r,320r:0)  0@80r
%vreg2 [48r,96r:0)  0@48r
%vreg3 [96r,336r:0)  0@96r
%vreg4 [32r,112r:0)  0@32r
%vreg5 [112r,352r:0)  0@112r
%vreg6 [16r,128r:0)  0@16r
%vreg7 [128r,368r:0)  0@128r
%vreg11 [400r,416r:0)  0@400r
%vreg12 [384r,400r:0)  0@384r
%vreg13 [144r,160r:0)  0@144r
%vreg14 [160r,208r:0)  0@160r
%vreg15 [176r,224r:0)  0@176r
%vreg18 [704r,720r:0)  0@704r
%vreg23 [1360r,1376r:0)  0@1360r
%vreg26 [1456r,1472r:0)  0@1456r
%vreg29 [1600r,1616r:0)  0@1600r
%vreg31 [1584r,1616r:0)  0@1584r
%vreg32 [1568r,1584r:0)  0@1568r
%vreg35 [1536r,1552r:0)  0@1536r
%vreg37 [1520r,1552r:0)  0@1520r
%vreg38 [1504r,1520r:0)  0@1504r
%vreg41 [1136r,1152r:0)  0@1136r
%vreg44 [1232r,1248r:0)  0@1232r
%vreg47 [816r,832r:0)  0@816r
%vreg50 [912r,928r:0)  0@912r
%vreg53 [528r,544r:0)  0@528r
%vreg56 [624r,640r:0)  0@624r
%vreg57 [1648r,1664r:0)  0@1648r
%vreg58 [1664r,1712r:0)  0@1664r
%vreg59 [1680r,1728r:0)  0@1680r
RegMasks: 240r 1744r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzReadGetUnused: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=8, align=8, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=8, align=8, at location [SP+8]
  fi#3: size=8, align=8, at location [SP+8]
  fi#4: size=8, align=8, at location [SP+8]
Function Live Ins: %RDI in %vreg0, %RSI in %vreg2, %RDX in %vreg4, %RCX in %vreg6

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI %RSI %RDX %RCX
16B		%vreg6<def> = COPY %RCX; GR64:%vreg6
32B		%vreg4<def> = COPY %RDX; GR64:%vreg4
48B		%vreg2<def> = COPY %RSI; GR64:%vreg2
64B		%vreg0<def> = COPY %RDI; GR64:%vreg0
80B		%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
96B		%vreg3<def> = COPY %vreg2; GR64:%vreg3,%vreg2
112B		%vreg5<def> = COPY %vreg4; GR64:%vreg5,%vreg4
128B		%vreg7<def> = COPY %vreg6; GR64:%vreg7,%vreg6
144B		%vreg13<def> = MOV64ri <ga:@BZ2_bzReadGetUnused>; GR64:%vreg13
160B		%vreg14<def> = COPY %vreg13; GR64:%vreg14,%vreg13
176B		%vreg15<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg15
192B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
208B		%RDI<def> = COPY %vreg14; GR64:%vreg14
224B		%RSI<def> = COPY %vreg15; GR64:%vreg15
240B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
256B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
272B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
288B		STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#4>, 0, %vreg7, 0, <fi#3>, 0, %vreg5, 0, <fi#2>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack2] GR64:%vreg3,%vreg1,%vreg7,%vreg5
304B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
320B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%bzerror.addr] GR64:%vreg1
336B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg3; mem:ST8[%b.addr] GR64:%vreg3
352B		MOV64mr <fi#2>, 1, %noreg, 0, %noreg, %vreg5; mem:ST8[%unused.addr] GR64:%vreg5
368B		MOV64mr <fi#3>, 1, %noreg, 0, %noreg, %vreg7; mem:ST8[%nUnused.addr] GR64:%vreg7
384B		%vreg12<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr] GR64:%vreg12
400B		%vreg11<def> = COPY %vreg12; GR64:%vreg11,%vreg12
416B		MOV64mr <fi#4>, 1, %noreg, 0, %noreg, %vreg11; mem:ST8[%bzf] GR64:%vreg11
432B		CMP64mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
448B		JNE_1 <BB#6>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#6 BB#1

464B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
480B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
496B		JE_1 <BB#3>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#3 BB#2

512B	BB#2: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#1
528B		%vreg53<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg53
544B		MOV32mi %vreg53, 1, %noreg, 0, %noreg, -2; mem:ST4[%4] GR64:%vreg53
	    Successors according to CFG: BB#3

560B	BB#3: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#1 BB#2
576B		CMP64mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
592B		JE_1 <BB#5>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#5 BB#4

608B	BB#4: derived from LLVM BB %if.then.4
	    Predecessors according to CFG: BB#3
624B		%vreg56<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg56
640B		MOV32mi %vreg56, 1, %noreg, 5096, %noreg, -2; mem:ST4[%lastErr] GR64:%vreg56
	    Successors according to CFG: BB#5

656B	BB#5: derived from LLVM BB %if.end.5
	    Predecessors according to CFG: BB#3 BB#4
672B		JMP_1 <BB#24>
	    Successors according to CFG: BB#24

688B	BB#6: derived from LLVM BB %if.end.6
	    Predecessors according to CFG: BB#0
704B		%vreg18<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg18
720B		CMP32mi8 %vreg18, 1, %noreg, 5096, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%lastErr7] GR64:%vreg18
736B		JE_1 <BB#12>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#12 BB#7

752B	BB#7: derived from LLVM BB %if.then.9
	    Predecessors according to CFG: BB#6
768B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
784B		JE_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#8

800B	BB#8: derived from LLVM BB %if.then.11
	    Predecessors according to CFG: BB#7
816B		%vreg47<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg47
832B		MOV32mi %vreg47, 1, %noreg, 0, %noreg, -1; mem:ST4[%10] GR64:%vreg47
	    Successors according to CFG: BB#9

848B	BB#9: derived from LLVM BB %if.end.12
	    Predecessors according to CFG: BB#7 BB#8
864B		CMP64mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
880B		JE_1 <BB#11>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#11 BB#10

896B	BB#10: derived from LLVM BB %if.then.14
	    Predecessors according to CFG: BB#9
912B		%vreg50<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg50
928B		MOV32mi %vreg50, 1, %noreg, 5096, %noreg, -1; mem:ST4[%lastErr15] GR64:%vreg50
	    Successors according to CFG: BB#11

944B	BB#11: derived from LLVM BB %if.end.16
	    Predecessors according to CFG: BB#9 BB#10
960B		JMP_1 <BB#24>
	    Successors according to CFG: BB#24

976B	BB#12: derived from LLVM BB %if.end.17
	    Predecessors according to CFG: BB#6
992B		CMP64mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%unused.addr]
1008B		JE_1 <BB#14>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#14 BB#13

1024B	BB#13: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#12
1040B		CMP64mi8 <fi#3>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%nUnused.addr]
1056B		JNE_1 <BB#19>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#19 BB#14

1072B	BB#14: derived from LLVM BB %if.then.20
	    Predecessors according to CFG: BB#12 BB#13
1088B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
1104B		JE_1 <BB#16>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#16 BB#15

1120B	BB#15: derived from LLVM BB %if.then.22
	    Predecessors according to CFG: BB#14
1136B		%vreg41<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg41
1152B		MOV32mi %vreg41, 1, %noreg, 0, %noreg, -2; mem:ST4[%16] GR64:%vreg41
	    Successors according to CFG: BB#16

1168B	BB#16: derived from LLVM BB %if.end.23
	    Predecessors according to CFG: BB#14 BB#15
1184B		CMP64mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
1200B		JE_1 <BB#18>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#18 BB#17

1216B	BB#17: derived from LLVM BB %if.then.25
	    Predecessors according to CFG: BB#16
1232B		%vreg44<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg44
1248B		MOV32mi %vreg44, 1, %noreg, 5096, %noreg, -2; mem:ST4[%lastErr26] GR64:%vreg44
	    Successors according to CFG: BB#18

1264B	BB#18: derived from LLVM BB %if.end.27
	    Predecessors according to CFG: BB#16 BB#17
1280B		JMP_1 <BB#24>
	    Successors according to CFG: BB#24

1296B	BB#19: derived from LLVM BB %if.end.28
	    Predecessors according to CFG: BB#13
1312B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
1328B		JE_1 <BB#21>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#21 BB#20

1344B	BB#20: derived from LLVM BB %if.then.30
	    Predecessors according to CFG: BB#19
1360B		%vreg23<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg23
1376B		MOV32mi %vreg23, 1, %noreg, 0, %noreg, 0; mem:ST4[%20] GR64:%vreg23
	    Successors according to CFG: BB#21

1392B	BB#21: derived from LLVM BB %if.end.31
	    Predecessors according to CFG: BB#19 BB#20
1408B		CMP64mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
1424B		JE_1 <BB#23>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#23 BB#22

1440B	BB#22: derived from LLVM BB %if.then.33
	    Predecessors according to CFG: BB#21
1456B		%vreg26<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg26
1472B		MOV32mi %vreg26, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr34] GR64:%vreg26
	    Successors according to CFG: BB#23

1488B	BB#23: derived from LLVM BB %if.end.35
	    Predecessors according to CFG: BB#21 BB#22
1504B		%vreg38<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg38
1520B		%vreg37<def> = MOV32rm %vreg38, 1, %noreg, 5024, %noreg; mem:LD4[%avail_in] GR32:%vreg37 GR64:%vreg38
1536B		%vreg35<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%nUnused.addr] GR64:%vreg35
1552B		MOV32mr %vreg35, 1, %noreg, 0, %noreg, %vreg37; mem:ST4[%25] GR64:%vreg35 GR32:%vreg37
1568B		%vreg32<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg32
1584B		%vreg31<def> = MOV64rm %vreg32, 1, %noreg, 5016, %noreg; mem:LD8[%next_in] GR64:%vreg31,%vreg32
1600B		%vreg29<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%unused.addr] GR64:%vreg29
1616B		MOV64mr %vreg29, 1, %noreg, 0, %noreg, %vreg31; mem:ST8[%28] GR64:%vreg29,%vreg31
	    Successors according to CFG: BB#24

1632B	BB#24: derived from LLVM BB %return
	    Predecessors according to CFG: BB#23 BB#18 BB#11 BB#5
1648B		%vreg57<def> = MOV64ri <ga:@BZ2_bzReadGetUnused>; GR64:%vreg57
1664B		%vreg58<def> = COPY %vreg57; GR64:%vreg58,%vreg57
1680B		%vreg59<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg59
1696B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1712B		%RDI<def> = COPY %vreg58; GR64:%vreg58
1728B		%RSI<def> = COPY %vreg59; GR64:%vreg59
1744B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
1760B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1776B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1792B		STACKMAP 1, 0, ...
1808B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1824B		RETQ

# End machine code for function BZ2_bzReadGetUnused.

********** SIMPLE REGISTER COALESCING **********
********** Function: BZ2_bzReadGetUnused
********** JOINING INTERVALS ***********
if.end:
if.end.12:
if.then.20:
if.end.23:
if.end.31:
return:
1712B	%RDI<def> = COPY %vreg58; GR64:%vreg58
	Considering merging %vreg58 with %RDI
	Can only merge into reserved registers.
1728B	%RSI<def> = COPY %vreg59; GR64:%vreg59
	Considering merging %vreg59 with %RSI
	Can only merge into reserved registers.
if.then:
if.end.5:
if.end.6:
if.then.9:
if.end.16:
if.end.17:
lor.lhs.false:
if.end.27:
if.end.28:
if.end.35:
entry:
16B	%vreg6<def> = COPY %RCX; GR64:%vreg6
	Considering merging %vreg6 with %RCX
	Can only merge into reserved registers.
32B	%vreg4<def> = COPY %RDX; GR64:%vreg4
	Considering merging %vreg4 with %RDX
	Can only merge into reserved registers.
48B	%vreg2<def> = COPY %RSI; GR64:%vreg2
	Considering merging %vreg2 with %RSI
	Can only merge into reserved registers.
64B	%vreg0<def> = COPY %RDI; GR64:%vreg0
	Considering merging %vreg0 with %RDI
	Can only merge into reserved registers.
208B	%RDI<def> = COPY %vreg14; GR64:%vreg14
	Considering merging %vreg14 with %RDI
	Can only merge into reserved registers.
224B	%RSI<def> = COPY %vreg15; GR64:%vreg15
	Considering merging %vreg15 with %RSI
	Can only merge into reserved registers.
if.then.2:
if.then.4:
if.then.11:
if.then.14:
if.then.22:
if.then.25:
if.then.30:
if.then.33:
1664B	%vreg58<def> = COPY %vreg57; GR64:%vreg58,%vreg57
	Considering merging to GR64 with %vreg57 in %vreg58
		RHS = %vreg57 [1648r,1664r:0)  0@1648r
		LHS = %vreg58 [1664r,1712r:0)  0@1664r
		merge %vreg58:0@1664r into %vreg57:0@1648r --> @1648r
		erased:	1664r	%vreg58<def> = COPY %vreg57; GR64:%vreg58,%vreg57
		updated: 1648B	%vreg58<def> = MOV64ri <ga:@BZ2_bzReadGetUnused>; GR64:%vreg58
	Success: %vreg57 -> %vreg58
	Result = %vreg58 [1648r,1712r:0)  0@1648r
80B	%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
	Considering merging to GR64 with %vreg0 in %vreg1
		RHS = %vreg0 [64r,80r:0)  0@64r
		LHS = %vreg1 [80r,320r:0)  0@80r
		merge %vreg1:0@80r into %vreg0:0@64r --> @64r
		erased:	80r	%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
		updated: 64B	%vreg1<def> = COPY %RDI; GR64:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [64r,320r:0)  0@64r
96B	%vreg3<def> = COPY %vreg2; GR64:%vreg3,%vreg2
	Considering merging to GR64 with %vreg2 in %vreg3
		RHS = %vreg2 [48r,96r:0)  0@48r
		LHS = %vreg3 [96r,336r:0)  0@96r
		merge %vreg3:0@96r into %vreg2:0@48r --> @48r
		erased:	96r	%vreg3<def> = COPY %vreg2; GR64:%vreg3,%vreg2
		updated: 48B	%vreg3<def> = COPY %RSI; GR64:%vreg3
	Success: %vreg2 -> %vreg3
	Result = %vreg3 [48r,336r:0)  0@48r
112B	%vreg5<def> = COPY %vreg4; GR64:%vreg5,%vreg4
	Considering merging to GR64 with %vreg4 in %vreg5
		RHS = %vreg4 [32r,112r:0)  0@32r
		LHS = %vreg5 [112r,352r:0)  0@112r
		merge %vreg5:0@112r into %vreg4:0@32r --> @32r
		erased:	112r	%vreg5<def> = COPY %vreg4; GR64:%vreg5,%vreg4
		updated: 32B	%vreg5<def> = COPY %RDX; GR64:%vreg5
	Success: %vreg4 -> %vreg5
	Result = %vreg5 [32r,352r:0)  0@32r
128B	%vreg7<def> = COPY %vreg6; GR64:%vreg7,%vreg6
	Considering merging to GR64 with %vreg6 in %vreg7
		RHS = %vreg6 [16r,128r:0)  0@16r
		LHS = %vreg7 [128r,368r:0)  0@128r
		merge %vreg7:0@128r into %vreg6:0@16r --> @16r
		erased:	128r	%vreg7<def> = COPY %vreg6; GR64:%vreg7,%vreg6
		updated: 16B	%vreg7<def> = COPY %RCX; GR64:%vreg7
	Success: %vreg6 -> %vreg7
	Result = %vreg7 [16r,368r:0)  0@16r
160B	%vreg14<def> = COPY %vreg13; GR64:%vreg14,%vreg13
	Considering merging to GR64 with %vreg13 in %vreg14
		RHS = %vreg13 [144r,160r:0)  0@144r
		LHS = %vreg14 [160r,208r:0)  0@160r
		merge %vreg14:0@160r into %vreg13:0@144r --> @144r
		erased:	160r	%vreg14<def> = COPY %vreg13; GR64:%vreg14,%vreg13
		updated: 144B	%vreg14<def> = MOV64ri <ga:@BZ2_bzReadGetUnused>; GR64:%vreg14
	Success: %vreg13 -> %vreg14
	Result = %vreg14 [144r,208r:0)  0@144r
400B	%vreg11<def> = COPY %vreg12; GR64:%vreg11,%vreg12
	Considering merging to GR64 with %vreg12 in %vreg11
		RHS = %vreg12 [384r,400r:0)  0@384r
		LHS = %vreg11 [400r,416r:0)  0@400r
		merge %vreg11:0@400r into %vreg12:0@384r --> @384r
		erased:	400r	%vreg11<def> = COPY %vreg12; GR64:%vreg11,%vreg12
		updated: 384B	%vreg11<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr] GR64:%vreg11
	Success: %vreg12 -> %vreg11
	Result = %vreg11 [384r,416r:0)  0@384r
1712B	%RDI<def> = COPY %vreg58; GR64:%vreg58
	Considering merging %vreg58 with %RDI
	Can only merge into reserved registers.
208B	%RDI<def> = COPY %vreg14; GR64:%vreg14
	Considering merging %vreg14 with %RDI
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
CH [0B,16r:0)  0@0B-phi
CL [0B,16r:0)  0@0B-phi
DH [0B,32r:0)  0@0B-phi
DIL [0B,64r:0)[208r,240r:2)[1712r,1744r:1)  0@0B-phi 1@1712r 2@208r
DL [0B,32r:0)  0@0B-phi
SIL [0B,48r:0)[224r,240r:2)[1728r,1744r:1)  0@0B-phi 1@1728r 2@224r
%vreg1 [64r,320r:0)  0@64r
%vreg3 [48r,336r:0)  0@48r
%vreg5 [32r,352r:0)  0@32r
%vreg7 [16r,368r:0)  0@16r
%vreg11 [384r,416r:0)  0@384r
%vreg14 [144r,208r:0)  0@144r
%vreg15 [176r,224r:0)  0@176r
%vreg18 [704r,720r:0)  0@704r
%vreg23 [1360r,1376r:0)  0@1360r
%vreg26 [1456r,1472r:0)  0@1456r
%vreg29 [1600r,1616r:0)  0@1600r
%vreg31 [1584r,1616r:0)  0@1584r
%vreg32 [1568r,1584r:0)  0@1568r
%vreg35 [1536r,1552r:0)  0@1536r
%vreg37 [1520r,1552r:0)  0@1520r
%vreg38 [1504r,1520r:0)  0@1504r
%vreg41 [1136r,1152r:0)  0@1136r
%vreg44 [1232r,1248r:0)  0@1232r
%vreg47 [816r,832r:0)  0@816r
%vreg50 [912r,928r:0)  0@912r
%vreg53 [528r,544r:0)  0@528r
%vreg56 [624r,640r:0)  0@624r
%vreg58 [1648r,1712r:0)  0@1648r
%vreg59 [1680r,1728r:0)  0@1680r
RegMasks: 240r 1744r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzReadGetUnused: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=8, align=8, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=8, align=8, at location [SP+8]
  fi#3: size=8, align=8, at location [SP+8]
  fi#4: size=8, align=8, at location [SP+8]
Function Live Ins: %RDI in %vreg0, %RSI in %vreg2, %RDX in %vreg4, %RCX in %vreg6

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI %RSI %RDX %RCX
16B		%vreg7<def> = COPY %RCX; GR64:%vreg7
32B		%vreg5<def> = COPY %RDX; GR64:%vreg5
48B		%vreg3<def> = COPY %RSI; GR64:%vreg3
64B		%vreg1<def> = COPY %RDI; GR64:%vreg1
144B		%vreg14<def> = MOV64ri <ga:@BZ2_bzReadGetUnused>; GR64:%vreg14
176B		%vreg15<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg15
192B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
208B		%RDI<def> = COPY %vreg14; GR64:%vreg14
224B		%RSI<def> = COPY %vreg15; GR64:%vreg15
240B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
256B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
272B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
288B		STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#4>, 0, %vreg7, 0, <fi#3>, 0, %vreg5, 0, <fi#2>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack2] GR64:%vreg3,%vreg1,%vreg7,%vreg5
304B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
320B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%bzerror.addr] GR64:%vreg1
336B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg3; mem:ST8[%b.addr] GR64:%vreg3
352B		MOV64mr <fi#2>, 1, %noreg, 0, %noreg, %vreg5; mem:ST8[%unused.addr] GR64:%vreg5
368B		MOV64mr <fi#3>, 1, %noreg, 0, %noreg, %vreg7; mem:ST8[%nUnused.addr] GR64:%vreg7
384B		%vreg11<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr] GR64:%vreg11
416B		MOV64mr <fi#4>, 1, %noreg, 0, %noreg, %vreg11; mem:ST8[%bzf] GR64:%vreg11
432B		CMP64mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
448B		JNE_1 <BB#6>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#6 BB#1

464B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
480B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
496B		JE_1 <BB#3>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#3 BB#2

512B	BB#2: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#1
528B		%vreg53<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg53
544B		MOV32mi %vreg53, 1, %noreg, 0, %noreg, -2; mem:ST4[%4] GR64:%vreg53
	    Successors according to CFG: BB#3

560B	BB#3: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#1 BB#2
576B		CMP64mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
592B		JE_1 <BB#5>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#5 BB#4

608B	BB#4: derived from LLVM BB %if.then.4
	    Predecessors according to CFG: BB#3
624B		%vreg56<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg56
640B		MOV32mi %vreg56, 1, %noreg, 5096, %noreg, -2; mem:ST4[%lastErr] GR64:%vreg56
	    Successors according to CFG: BB#5

656B	BB#5: derived from LLVM BB %if.end.5
	    Predecessors according to CFG: BB#3 BB#4
672B		JMP_1 <BB#24>
	    Successors according to CFG: BB#24

688B	BB#6: derived from LLVM BB %if.end.6
	    Predecessors according to CFG: BB#0
704B		%vreg18<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg18
720B		CMP32mi8 %vreg18, 1, %noreg, 5096, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%lastErr7] GR64:%vreg18
736B		JE_1 <BB#12>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#12 BB#7

752B	BB#7: derived from LLVM BB %if.then.9
	    Predecessors according to CFG: BB#6
768B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
784B		JE_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#8

800B	BB#8: derived from LLVM BB %if.then.11
	    Predecessors according to CFG: BB#7
816B		%vreg47<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg47
832B		MOV32mi %vreg47, 1, %noreg, 0, %noreg, -1; mem:ST4[%10] GR64:%vreg47
	    Successors according to CFG: BB#9

848B	BB#9: derived from LLVM BB %if.end.12
	    Predecessors according to CFG: BB#7 BB#8
864B		CMP64mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
880B		JE_1 <BB#11>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#11 BB#10

896B	BB#10: derived from LLVM BB %if.then.14
	    Predecessors according to CFG: BB#9
912B		%vreg50<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg50
928B		MOV32mi %vreg50, 1, %noreg, 5096, %noreg, -1; mem:ST4[%lastErr15] GR64:%vreg50
	    Successors according to CFG: BB#11

944B	BB#11: derived from LLVM BB %if.end.16
	    Predecessors according to CFG: BB#9 BB#10
960B		JMP_1 <BB#24>
	    Successors according to CFG: BB#24

976B	BB#12: derived from LLVM BB %if.end.17
	    Predecessors according to CFG: BB#6
992B		CMP64mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%unused.addr]
1008B		JE_1 <BB#14>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#14 BB#13

1024B	BB#13: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#12
1040B		CMP64mi8 <fi#3>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%nUnused.addr]
1056B		JNE_1 <BB#19>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#19 BB#14

1072B	BB#14: derived from LLVM BB %if.then.20
	    Predecessors according to CFG: BB#12 BB#13
1088B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
1104B		JE_1 <BB#16>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#16 BB#15

1120B	BB#15: derived from LLVM BB %if.then.22
	    Predecessors according to CFG: BB#14
1136B		%vreg41<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg41
1152B		MOV32mi %vreg41, 1, %noreg, 0, %noreg, -2; mem:ST4[%16] GR64:%vreg41
	    Successors according to CFG: BB#16

1168B	BB#16: derived from LLVM BB %if.end.23
	    Predecessors according to CFG: BB#14 BB#15
1184B		CMP64mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
1200B		JE_1 <BB#18>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#18 BB#17

1216B	BB#17: derived from LLVM BB %if.then.25
	    Predecessors according to CFG: BB#16
1232B		%vreg44<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg44
1248B		MOV32mi %vreg44, 1, %noreg, 5096, %noreg, -2; mem:ST4[%lastErr26] GR64:%vreg44
	    Successors according to CFG: BB#18

1264B	BB#18: derived from LLVM BB %if.end.27
	    Predecessors according to CFG: BB#16 BB#17
1280B		JMP_1 <BB#24>
	    Successors according to CFG: BB#24

1296B	BB#19: derived from LLVM BB %if.end.28
	    Predecessors according to CFG: BB#13
1312B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
1328B		JE_1 <BB#21>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#21 BB#20

1344B	BB#20: derived from LLVM BB %if.then.30
	    Predecessors according to CFG: BB#19
1360B		%vreg23<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg23
1376B		MOV32mi %vreg23, 1, %noreg, 0, %noreg, 0; mem:ST4[%20] GR64:%vreg23
	    Successors according to CFG: BB#21

1392B	BB#21: derived from LLVM BB %if.end.31
	    Predecessors according to CFG: BB#19 BB#20
1408B		CMP64mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
1424B		JE_1 <BB#23>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#23 BB#22

1440B	BB#22: derived from LLVM BB %if.then.33
	    Predecessors according to CFG: BB#21
1456B		%vreg26<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg26
1472B		MOV32mi %vreg26, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr34] GR64:%vreg26
	    Successors according to CFG: BB#23

1488B	BB#23: derived from LLVM BB %if.end.35
	    Predecessors according to CFG: BB#21 BB#22
1504B		%vreg38<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg38
1520B		%vreg37<def> = MOV32rm %vreg38, 1, %noreg, 5024, %noreg; mem:LD4[%avail_in] GR32:%vreg37 GR64:%vreg38
1536B		%vreg35<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%nUnused.addr] GR64:%vreg35
1552B		MOV32mr %vreg35, 1, %noreg, 0, %noreg, %vreg37; mem:ST4[%25] GR64:%vreg35 GR32:%vreg37
1568B		%vreg32<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg32
1584B		%vreg31<def> = MOV64rm %vreg32, 1, %noreg, 5016, %noreg; mem:LD8[%next_in] GR64:%vreg31,%vreg32
1600B		%vreg29<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%unused.addr] GR64:%vreg29
1616B		MOV64mr %vreg29, 1, %noreg, 0, %noreg, %vreg31; mem:ST8[%28] GR64:%vreg29,%vreg31
	    Successors according to CFG: BB#24

1632B	BB#24: derived from LLVM BB %return
	    Predecessors according to CFG: BB#23 BB#18 BB#11 BB#5
1648B		%vreg58<def> = MOV64ri <ga:@BZ2_bzReadGetUnused>; GR64:%vreg58
1680B		%vreg59<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg59
1696B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1712B		%RDI<def> = COPY %vreg58; GR64:%vreg58
1728B		%RSI<def> = COPY %vreg59; GR64:%vreg59
1744B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
1760B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1776B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1792B		STACKMAP 1, 0, ...
1808B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1824B		RETQ

# End machine code for function BZ2_bzReadGetUnused.

AllocationOrder(SEGMENT_REG) = [ ]
********** GREEDY REGISTER ALLOCATION **********
********** Function: BZ2_bzReadGetUnused
********** INTERVALS **********
CH [0B,16r:0)  0@0B-phi
CL [0B,16r:0)  0@0B-phi
DH [0B,32r:0)  0@0B-phi
DIL [0B,64r:0)[208r,240r:2)[1712r,1744r:1)  0@0B-phi 1@1712r 2@208r
DL [0B,32r:0)  0@0B-phi
SIL [0B,48r:0)[224r,240r:2)[1728r,1744r:1)  0@0B-phi 1@1728r 2@224r
%vreg1 [64r,320r:0)  0@64r
%vreg3 [48r,336r:0)  0@48r
%vreg5 [32r,352r:0)  0@32r
%vreg7 [16r,368r:0)  0@16r
%vreg11 [384r,416r:0)  0@384r
%vreg14 [144r,208r:0)  0@144r
%vreg15 [176r,224r:0)  0@176r
%vreg18 [704r,720r:0)  0@704r
%vreg23 [1360r,1376r:0)  0@1360r
%vreg26 [1456r,1472r:0)  0@1456r
%vreg29 [1600r,1616r:0)  0@1600r
%vreg31 [1584r,1616r:0)  0@1584r
%vreg32 [1568r,1584r:0)  0@1568r
%vreg35 [1536r,1552r:0)  0@1536r
%vreg37 [1520r,1552r:0)  0@1520r
%vreg38 [1504r,1520r:0)  0@1504r
%vreg41 [1136r,1152r:0)  0@1136r
%vreg44 [1232r,1248r:0)  0@1232r
%vreg47 [816r,832r:0)  0@816r
%vreg50 [912r,928r:0)  0@912r
%vreg53 [528r,544r:0)  0@528r
%vreg56 [624r,640r:0)  0@624r
%vreg58 [1648r,1712r:0)  0@1648r
%vreg59 [1680r,1728r:0)  0@1680r
RegMasks: 240r 1744r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzReadGetUnused: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=8, align=8, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=8, align=8, at location [SP+8]
  fi#3: size=8, align=8, at location [SP+8]
  fi#4: size=8, align=8, at location [SP+8]
Function Live Ins: %RDI in %vreg0, %RSI in %vreg2, %RDX in %vreg4, %RCX in %vreg6

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI %RSI %RDX %RCX
16B		%vreg7<def> = COPY %RCX; GR64:%vreg7
32B		%vreg5<def> = COPY %RDX; GR64:%vreg5
48B		%vreg3<def> = COPY %RSI; GR64:%vreg3
64B		%vreg1<def> = COPY %RDI; GR64:%vreg1
144B		%vreg14<def> = MOV64ri <ga:@BZ2_bzReadGetUnused>; GR64:%vreg14
176B		%vreg15<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg15
192B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
208B		%RDI<def> = COPY %vreg14; GR64:%vreg14
224B		%RSI<def> = COPY %vreg15; GR64:%vreg15
240B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
256B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
272B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
288B		STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#4>, 0, %vreg7, 0, <fi#3>, 0, %vreg5, 0, <fi#2>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack2] GR64:%vreg3,%vreg1,%vreg7,%vreg5
304B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
320B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%bzerror.addr] GR64:%vreg1
336B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg3; mem:ST8[%b.addr] GR64:%vreg3
352B		MOV64mr <fi#2>, 1, %noreg, 0, %noreg, %vreg5; mem:ST8[%unused.addr] GR64:%vreg5
368B		MOV64mr <fi#3>, 1, %noreg, 0, %noreg, %vreg7; mem:ST8[%nUnused.addr] GR64:%vreg7
384B		%vreg11<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr] GR64:%vreg11
416B		MOV64mr <fi#4>, 1, %noreg, 0, %noreg, %vreg11; mem:ST8[%bzf] GR64:%vreg11
432B		CMP64mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
448B		JNE_1 <BB#6>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#6 BB#1

464B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
480B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
496B		JE_1 <BB#3>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#3 BB#2

512B	BB#2: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#1
528B		%vreg53<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg53
544B		MOV32mi %vreg53, 1, %noreg, 0, %noreg, -2; mem:ST4[%4] GR64:%vreg53
	    Successors according to CFG: BB#3

560B	BB#3: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#1 BB#2
576B		CMP64mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
592B		JE_1 <BB#5>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#5 BB#4

608B	BB#4: derived from LLVM BB %if.then.4
	    Predecessors according to CFG: BB#3
624B		%vreg56<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg56
640B		MOV32mi %vreg56, 1, %noreg, 5096, %noreg, -2; mem:ST4[%lastErr] GR64:%vreg56
	    Successors according to CFG: BB#5

656B	BB#5: derived from LLVM BB %if.end.5
	    Predecessors according to CFG: BB#3 BB#4
672B		JMP_1 <BB#24>
	    Successors according to CFG: BB#24

688B	BB#6: derived from LLVM BB %if.end.6
	    Predecessors according to CFG: BB#0
704B		%vreg18<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg18
720B		CMP32mi8 %vreg18, 1, %noreg, 5096, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%lastErr7] GR64:%vreg18
736B		JE_1 <BB#12>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#12 BB#7

752B	BB#7: derived from LLVM BB %if.then.9
	    Predecessors according to CFG: BB#6
768B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
784B		JE_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#8

800B	BB#8: derived from LLVM BB %if.then.11
	    Predecessors according to CFG: BB#7
816B		%vreg47<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg47
832B		MOV32mi %vreg47, 1, %noreg, 0, %noreg, -1; mem:ST4[%10] GR64:%vreg47
	    Successors according to CFG: BB#9

848B	BB#9: derived from LLVM BB %if.end.12
	    Predecessors according to CFG: BB#7 BB#8
864B		CMP64mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
880B		JE_1 <BB#11>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#11 BB#10

896B	BB#10: derived from LLVM BB %if.then.14
	    Predecessors according to CFG: BB#9
912B		%vreg50<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg50
928B		MOV32mi %vreg50, 1, %noreg, 5096, %noreg, -1; mem:ST4[%lastErr15] GR64:%vreg50
	    Successors according to CFG: BB#11

944B	BB#11: derived from LLVM BB %if.end.16
	    Predecessors according to CFG: BB#9 BB#10
960B		JMP_1 <BB#24>
	    Successors according to CFG: BB#24

976B	BB#12: derived from LLVM BB %if.end.17
	    Predecessors according to CFG: BB#6
992B		CMP64mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%unused.addr]
1008B		JE_1 <BB#14>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#14 BB#13

1024B	BB#13: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#12
1040B		CMP64mi8 <fi#3>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%nUnused.addr]
1056B		JNE_1 <BB#19>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#19 BB#14

1072B	BB#14: derived from LLVM BB %if.then.20
	    Predecessors according to CFG: BB#12 BB#13
1088B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
1104B		JE_1 <BB#16>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#16 BB#15

1120B	BB#15: derived from LLVM BB %if.then.22
	    Predecessors according to CFG: BB#14
1136B		%vreg41<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg41
1152B		MOV32mi %vreg41, 1, %noreg, 0, %noreg, -2; mem:ST4[%16] GR64:%vreg41
	    Successors according to CFG: BB#16

1168B	BB#16: derived from LLVM BB %if.end.23
	    Predecessors according to CFG: BB#14 BB#15
1184B		CMP64mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
1200B		JE_1 <BB#18>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#18 BB#17

1216B	BB#17: derived from LLVM BB %if.then.25
	    Predecessors according to CFG: BB#16
1232B		%vreg44<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg44
1248B		MOV32mi %vreg44, 1, %noreg, 5096, %noreg, -2; mem:ST4[%lastErr26] GR64:%vreg44
	    Successors according to CFG: BB#18

1264B	BB#18: derived from LLVM BB %if.end.27
	    Predecessors according to CFG: BB#16 BB#17
1280B		JMP_1 <BB#24>
	    Successors according to CFG: BB#24

1296B	BB#19: derived from LLVM BB %if.end.28
	    Predecessors according to CFG: BB#13
1312B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
1328B		JE_1 <BB#21>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#21 BB#20

1344B	BB#20: derived from LLVM BB %if.then.30
	    Predecessors according to CFG: BB#19
1360B		%vreg23<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg23
1376B		MOV32mi %vreg23, 1, %noreg, 0, %noreg, 0; mem:ST4[%20] GR64:%vreg23
	    Successors according to CFG: BB#21

1392B	BB#21: derived from LLVM BB %if.end.31
	    Predecessors according to CFG: BB#19 BB#20
1408B		CMP64mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
1424B		JE_1 <BB#23>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#23 BB#22

1440B	BB#22: derived from LLVM BB %if.then.33
	    Predecessors according to CFG: BB#21
1456B		%vreg26<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg26
1472B		MOV32mi %vreg26, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr34] GR64:%vreg26
	    Successors according to CFG: BB#23

1488B	BB#23: derived from LLVM BB %if.end.35
	    Predecessors according to CFG: BB#21 BB#22
1504B		%vreg38<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg38
1520B		%vreg37<def> = MOV32rm %vreg38, 1, %noreg, 5024, %noreg; mem:LD4[%avail_in] GR32:%vreg37 GR64:%vreg38
1536B		%vreg35<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%nUnused.addr] GR64:%vreg35
1552B		MOV32mr %vreg35, 1, %noreg, 0, %noreg, %vreg37; mem:ST4[%25] GR64:%vreg35 GR32:%vreg37
1568B		%vreg32<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg32
1584B		%vreg31<def> = MOV64rm %vreg32, 1, %noreg, 5016, %noreg; mem:LD8[%next_in] GR64:%vreg31,%vreg32
1600B		%vreg29<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%unused.addr] GR64:%vreg29
1616B		MOV64mr %vreg29, 1, %noreg, 0, %noreg, %vreg31; mem:ST8[%28] GR64:%vreg29,%vreg31
	    Successors according to CFG: BB#24

1632B	BB#24: derived from LLVM BB %return
	    Predecessors according to CFG: BB#23 BB#18 BB#11 BB#5
1648B		%vreg58<def> = MOV64ri <ga:@BZ2_bzReadGetUnused>; GR64:%vreg58
1680B		%vreg59<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg59
1696B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1712B		%RDI<def> = COPY %vreg58; GR64:%vreg58
1728B		%RSI<def> = COPY %vreg59; GR64:%vreg59
1744B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
1760B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1776B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1792B		STACKMAP 1, 0, ...
1808B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1824B		RETQ

# End machine code for function BZ2_bzReadGetUnused.


selectOrSplit GR64:%vreg7 [16r,368r:0)  0@16r w=4.029255e-03
hints: %RCX
missed hint %RCX
assigning %vreg7 to %RBX: BH [16r,368r:0)  0@16r BL [16r,368r:0)  0@16r

selectOrSplit GR64:%vreg5 [32r,352r:0)  0@32r w=4.208333e-03
hints: %RDX
missed hint %RDX
%R14 is available at cost 1
Only trying the first 10 regs.
should evict: %vreg7 [16r,368r:0)  0@16r w= 4.029255e-03
hints: %RCX
can reassign: %vreg7 [16r,368r:0)  0@16r from %RBX to %RCX
should evict: %vreg7 [16r,368r:0)  0@16r w= 4.029255e-03
hints: %RCX
can reassign: %vreg7 [16r,368r:0)  0@16r from %RBX to %RCX
evicting %RBX interference: Cascade 1
unassigning %vreg7 from %RBX: BH BL
assigning %vreg5 to %RBX: BH [32r,352r:0)  0@32r BL [32r,352r:0)  0@32r
queuing new interval: %vreg7 [16r,368r:0)  0@16r

selectOrSplit GR64:%vreg7 [16r,368r:0)  0@16r w=4.029255e-03
hints: %RCX
missed hint %RCX
%R14 is available at cost 1
Only trying the first 10 regs.
assigning %vreg7 to %R14: R14B [16r,368r:0)  0@16r

selectOrSplit GR64:%vreg3 [48r,336r:0)  0@48r w=4.404070e-03
hints: %RSI
missed hint %RSI
%R15 is available at cost 1
Only trying the first 10 regs.
should evict: %vreg5 [32r,352r:0)  0@32r w= 4.208333e-03
hints: %RDX
can reassign: %vreg5 [32r,352r:0)  0@32r from %RBX to %RDX
should evict: %vreg5 [32r,352r:0)  0@32r w= 4.208333e-03
hints: %RDX
can reassign: %vreg5 [32r,352r:0)  0@32r from %RBX to %RDX
evicting %RBX interference: Cascade 2
unassigning %vreg5 from %RBX: BH BL
assigning %vreg3 to %RBX: BH [48r,336r:0)  0@48r BL [48r,336r:0)  0@48r
queuing new interval: %vreg5 [32r,352r:0)  0@32r

selectOrSplit GR64:%vreg5 [32r,352r:0)  0@32r w=4.208333e-03
hints: %RDX
missed hint %RDX
%R15 is available at cost 1
Only trying the first 10 regs.
assigning %vreg5 to %R15: R15B [32r,352r:0)  0@32r

selectOrSplit GR64:%vreg1 [64r,320r:0)  0@64r w=4.618902e-03
hints: %RDI
missed hint %RDI
%R12 is available at cost 1
Only trying the first 10 regs.
should evict: %vreg3 [48r,336r:0)  0@48r w= 4.404070e-03
hints: %RSI
can reassign: %vreg3 [48r,336r:0)  0@48r from %RBX to %RSI
should evict: %vreg3 [48r,336r:0)  0@48r w= 4.404070e-03
hints: %RSI
can reassign: %vreg3 [48r,336r:0)  0@48r from %RBX to %RSI
evicting %RBX interference: Cascade 3
unassigning %vreg3 from %RBX: BH BL
assigning %vreg1 to %RBX: BH [64r,320r:0)  0@64r BL [64r,320r:0)  0@64r
queuing new interval: %vreg3 [48r,336r:0)  0@48r

selectOrSplit GR64:%vreg3 [48r,336r:0)  0@48r w=4.404070e-03
hints: %RSI
missed hint %RSI
%R12 is available at cost 1
Only trying the first 10 regs.
assigning %vreg3 to %R12: R12B [48r,336r:0)  0@48r

selectOrSplit GR64:%vreg14 [144r,208r:0)  0@144r w=2.176724e-03
hints: %RDI
assigning %vreg14 to %RDI: DIL [144r,208r:0)  0@144r

selectOrSplit GR64:%vreg15 [176r,224r:0)  0@176r w=4.508928e-03
hints: %RSI
assigning %vreg15 to %RSI: SIL [176r,224r:0)  0@176r

selectOrSplit GR64:%vreg58 [1648r,1712r:0)  0@1648r w=2.176724e-03
hints: %RDI
assigning %vreg58 to %RDI: DIL [1648r,1712r:0)  0@1648r

selectOrSplit GR64:%vreg59 [1680r,1728r:0)  0@1680r w=4.508928e-03
hints: %RSI
assigning %vreg59 to %RSI: SIL [1680r,1728r:0)  0@1680r

selectOrSplit GR64:%vreg11 [384r,416r:0)  0@384r w=inf
assigning %vreg11 to %RAX: AH [384r,416r:0)  0@384r AL [384r,416r:0)  0@384r

selectOrSplit GR64:%vreg53 [528r,544r:0)  0@528r w=inf
assigning %vreg53 to %RAX: AH [528r,544r:0)  0@528r AL [528r,544r:0)  0@528r

selectOrSplit GR64:%vreg56 [624r,640r:0)  0@624r w=inf
assigning %vreg56 to %RAX: AH [624r,640r:0)  0@624r AL [624r,640r:0)  0@624r

selectOrSplit GR64:%vreg18 [704r,720r:0)  0@704r w=inf
assigning %vreg18 to %RAX: AH [704r,720r:0)  0@704r AL [704r,720r:0)  0@704r

selectOrSplit GR64:%vreg47 [816r,832r:0)  0@816r w=inf
assigning %vreg47 to %RAX: AH [816r,832r:0)  0@816r AL [816r,832r:0)  0@816r

selectOrSplit GR64:%vreg50 [912r,928r:0)  0@912r w=inf
assigning %vreg50 to %RAX: AH [912r,928r:0)  0@912r AL [912r,928r:0)  0@912r

selectOrSplit GR64:%vreg41 [1136r,1152r:0)  0@1136r w=inf
assigning %vreg41 to %RAX: AH [1136r,1152r:0)  0@1136r AL [1136r,1152r:0)  0@1136r

selectOrSplit GR64:%vreg44 [1232r,1248r:0)  0@1232r w=inf
assigning %vreg44 to %RAX: AH [1232r,1248r:0)  0@1232r AL [1232r,1248r:0)  0@1232r

selectOrSplit GR64:%vreg23 [1360r,1376r:0)  0@1360r w=inf
assigning %vreg23 to %RAX: AH [1360r,1376r:0)  0@1360r AL [1360r,1376r:0)  0@1360r

selectOrSplit GR64:%vreg26 [1456r,1472r:0)  0@1456r w=inf
assigning %vreg26 to %RAX: AH [1456r,1472r:0)  0@1456r AL [1456r,1472r:0)  0@1456r

selectOrSplit GR64:%vreg38 [1504r,1520r:0)  0@1504r w=inf
assigning %vreg38 to %RAX: AH [1504r,1520r:0)  0@1504r AL [1504r,1520r:0)  0@1504r

selectOrSplit GR32:%vreg37 [1520r,1552r:0)  0@1520r w=2.723312e-04
assigning %vreg37 to %EAX: AH [1520r,1552r:0)  0@1520r AL [1520r,1552r:0)  0@1520r

selectOrSplit GR64:%vreg35 [1536r,1552r:0)  0@1536r w=inf
assigning %vreg35 to %RCX: CH [1536r,1552r:0)  0@1536r CL [1536r,1552r:0)  0@1536r

selectOrSplit GR64:%vreg32 [1568r,1584r:0)  0@1568r w=inf
assigning %vreg32 to %RAX: AH [1568r,1584r:0)  0@1568r AL [1568r,1584r:0)  0@1568r

selectOrSplit GR64:%vreg31 [1584r,1616r:0)  0@1584r w=2.723312e-04
assigning %vreg31 to %RAX: AH [1584r,1616r:0)  0@1584r AL [1584r,1616r:0)  0@1584r

selectOrSplit GR64:%vreg29 [1600r,1616r:0)  0@1600r w=inf
assigning %vreg29 to %RCX: CH [1600r,1616r:0)  0@1600r CL [1600r,1616r:0)  0@1600r

********** STACK TRANSFORMATION METADATA **********
********** Function: BZ2_bzReadGetUnused
********** REGISTER MAP **********
[%vreg1 -> %RBX] GR64
[%vreg3 -> %R12] GR64
[%vreg5 -> %R15] GR64
[%vreg7 -> %R14] GR64
[%vreg11 -> %RAX] GR64
[%vreg14 -> %RDI] GR64
[%vreg15 -> %RSI] GR64
[%vreg18 -> %RAX] GR64
[%vreg23 -> %RAX] GR64
[%vreg26 -> %RAX] GR64
[%vreg29 -> %RCX] GR64
[%vreg31 -> %RAX] GR64
[%vreg32 -> %RAX] GR64
[%vreg35 -> %RCX] GR64
[%vreg37 -> %EAX] GR32
[%vreg38 -> %RAX] GR64
[%vreg41 -> %RAX] GR64
[%vreg44 -> %RAX] GR64
[%vreg47 -> %RAX] GR64
[%vreg50 -> %RAX] GR64
[%vreg53 -> %RAX] GR64
[%vreg56 -> %RAX] GR64
[%vreg58 -> %RDI] GR64
[%vreg59 -> %RSI] GR64


Stackmap 0:
  STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#4>, 0, %vreg7, 0, <fi#3>, 0, %vreg5, 0, <fi#2>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack2] GR64:%vreg3,%vreg1,%vreg7,%vreg5

i8* %b: in register %R12 (vreg 3)
i8** %b.addr: in stack slot 1 (size: 8)
i32* %bzerror: in register %RBX (vreg 1)
i32** %bzerror.addr: in stack slot 0 (size: 8)
%struct.bzFile** %bzf: in stack slot 4 (size: 8)
i32* %nUnused: in register %R14 (vreg 7)
i32** %nUnused.addr: in stack slot 3 (size: 8)
i8** %unused: in register %R15 (vreg 5)
i8*** %unused.addr: in stack slot 2 (size: 8)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, ...


Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#4>, 0, %vreg7, 0, <fi#3>, 0, %vreg5, 0, <fi#2>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack2] GR64:%vreg3,%vreg1,%vreg7,%vreg5
  -> Call instruction SlotIndex 240B, searching vregs 0 -> 60 and stack slots -1 -> 5

  STACKMAP 1, 0, ...
  -> Call instruction SlotIndex 1744B, searching vregs 0 -> 60 and stack slots -1 -> 5

********** REWRITE VIRTUAL REGISTERS **********
********** Function: BZ2_bzReadGetUnused
********** REGISTER MAP **********
[%vreg1 -> %RBX] GR64
[%vreg3 -> %R12] GR64
[%vreg5 -> %R15] GR64
[%vreg7 -> %R14] GR64
[%vreg11 -> %RAX] GR64
[%vreg14 -> %RDI] GR64
[%vreg15 -> %RSI] GR64
[%vreg18 -> %RAX] GR64
[%vreg23 -> %RAX] GR64
[%vreg26 -> %RAX] GR64
[%vreg29 -> %RCX] GR64
[%vreg31 -> %RAX] GR64
[%vreg32 -> %RAX] GR64
[%vreg35 -> %RCX] GR64
[%vreg37 -> %EAX] GR32
[%vreg38 -> %RAX] GR64
[%vreg41 -> %RAX] GR64
[%vreg44 -> %RAX] GR64
[%vreg47 -> %RAX] GR64
[%vreg50 -> %RAX] GR64
[%vreg53 -> %RAX] GR64
[%vreg56 -> %RAX] GR64
[%vreg58 -> %RDI] GR64
[%vreg59 -> %RSI] GR64

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RCX %RDI %RDX %RSI
16B		%vreg7<def> = COPY %RCX; GR64:%vreg7
32B		%vreg5<def> = COPY %RDX; GR64:%vreg5
48B		%vreg3<def> = COPY %RSI; GR64:%vreg3
64B		%vreg1<def> = COPY %RDI; GR64:%vreg1
144B		%vreg14<def> = MOV64ri <ga:@BZ2_bzReadGetUnused>; GR64:%vreg14
176B		%vreg15<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg15
192B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
208B		%RDI<def> = COPY %vreg14<kill>; GR64:%vreg14
224B		%RSI<def> = COPY %vreg15<kill>; GR64:%vreg15
240B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
256B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
272B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
288B		STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#4>, 0, %vreg7, 0, <fi#3>, 0, %vreg5, 0, <fi#2>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack2] GR64:%vreg3,%vreg1,%vreg7,%vreg5
304B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
320B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1<kill>; mem:ST8[%bzerror.addr] GR64:%vreg1
336B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg3<kill>; mem:ST8[%b.addr] GR64:%vreg3
352B		MOV64mr <fi#2>, 1, %noreg, 0, %noreg, %vreg5<kill>; mem:ST8[%unused.addr] GR64:%vreg5
368B		MOV64mr <fi#3>, 1, %noreg, 0, %noreg, %vreg7<kill>; mem:ST8[%nUnused.addr] GR64:%vreg7
384B		%vreg11<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr] GR64:%vreg11
416B		MOV64mr <fi#4>, 1, %noreg, 0, %noreg, %vreg11<kill>; mem:ST8[%bzf] GR64:%vreg11
432B		CMP64mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
448B		JNE_1 <BB#6>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#6 BB#1
> %R14<def> = COPY %RCX
> %R15<def> = COPY %RDX
> %R12<def> = COPY %RSI
> %RBX<def> = COPY %RDI
> %RDI<def> = MOV64ri <ga:@BZ2_bzReadGetUnused>
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 0, 0, %R12, 0, <fi#1>, 0, %RBX, 0, <fi#0>, 0, 0, <fi#4>, 0, %R14, 0, <fi#3>, 0, %R15, 0, <fi#2>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack4] LD8[FixedStack3] LD8[FixedStack2]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %RBX<kill>; mem:ST8[%bzerror.addr]
> MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %R12<kill>; mem:ST8[%b.addr]
> MOV64mr <fi#2>, 1, %noreg, 0, %noreg, %R15<kill>; mem:ST8[%unused.addr]
> MOV64mr <fi#3>, 1, %noreg, 0, %noreg, %R14<kill>; mem:ST8[%nUnused.addr]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr]
> MOV64mr <fi#4>, 1, %noreg, 0, %noreg, %RAX<kill>; mem:ST8[%bzf]
> CMP64mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
> JNE_1 <BB#6>, %EFLAGS<imp-use,kill>
464B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
480B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
496B		JE_1 <BB#3>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#3 BB#2
> CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
> JE_1 <BB#3>, %EFLAGS<imp-use,kill>
512B	BB#2: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#1
528B		%vreg53<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg53
544B		MOV32mi %vreg53<kill>, 1, %noreg, 0, %noreg, -2; mem:ST4[%4] GR64:%vreg53
	    Successors according to CFG: BB#3
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 0, %noreg, -2; mem:ST4[%4]
560B	BB#3: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#1 BB#2
576B		CMP64mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
592B		JE_1 <BB#5>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#5 BB#4
> CMP64mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
> JE_1 <BB#5>, %EFLAGS<imp-use,kill>
608B	BB#4: derived from LLVM BB %if.then.4
	    Predecessors according to CFG: BB#3
624B		%vreg56<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg56
640B		MOV32mi %vreg56<kill>, 1, %noreg, 5096, %noreg, -2; mem:ST4[%lastErr] GR64:%vreg56
	    Successors according to CFG: BB#5
> %RAX<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV32mi %RAX<kill>, 1, %noreg, 5096, %noreg, -2; mem:ST4[%lastErr]
656B	BB#5: derived from LLVM BB %if.end.5
	    Predecessors according to CFG: BB#3 BB#4
672B		JMP_1 <BB#24>
	    Successors according to CFG: BB#24
> JMP_1 <BB#24>
688B	BB#6: derived from LLVM BB %if.end.6
	    Predecessors according to CFG: BB#0
704B		%vreg18<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg18
720B		CMP32mi8 %vreg18<kill>, 1, %noreg, 5096, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%lastErr7] GR64:%vreg18
736B		JE_1 <BB#12>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#12 BB#7
> %RAX<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> CMP32mi8 %RAX<kill>, 1, %noreg, 5096, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%lastErr7]
> JE_1 <BB#12>, %EFLAGS<imp-use,kill>
752B	BB#7: derived from LLVM BB %if.then.9
	    Predecessors according to CFG: BB#6
768B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
784B		JE_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#8
> CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
> JE_1 <BB#9>, %EFLAGS<imp-use,kill>
800B	BB#8: derived from LLVM BB %if.then.11
	    Predecessors according to CFG: BB#7
816B		%vreg47<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg47
832B		MOV32mi %vreg47<kill>, 1, %noreg, 0, %noreg, -1; mem:ST4[%10] GR64:%vreg47
	    Successors according to CFG: BB#9
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 0, %noreg, -1; mem:ST4[%10]
848B	BB#9: derived from LLVM BB %if.end.12
	    Predecessors according to CFG: BB#7 BB#8
864B		CMP64mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
880B		JE_1 <BB#11>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#11 BB#10
> CMP64mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
> JE_1 <BB#11>, %EFLAGS<imp-use,kill>
896B	BB#10: derived from LLVM BB %if.then.14
	    Predecessors according to CFG: BB#9
912B		%vreg50<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg50
928B		MOV32mi %vreg50<kill>, 1, %noreg, 5096, %noreg, -1; mem:ST4[%lastErr15] GR64:%vreg50
	    Successors according to CFG: BB#11
> %RAX<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV32mi %RAX<kill>, 1, %noreg, 5096, %noreg, -1; mem:ST4[%lastErr15]
944B	BB#11: derived from LLVM BB %if.end.16
	    Predecessors according to CFG: BB#9 BB#10
960B		JMP_1 <BB#24>
	    Successors according to CFG: BB#24
> JMP_1 <BB#24>
976B	BB#12: derived from LLVM BB %if.end.17
	    Predecessors according to CFG: BB#6
992B		CMP64mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%unused.addr]
1008B		JE_1 <BB#14>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#14 BB#13
> CMP64mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%unused.addr]
> JE_1 <BB#14>, %EFLAGS<imp-use,kill>
1024B	BB#13: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#12
1040B		CMP64mi8 <fi#3>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%nUnused.addr]
1056B		JNE_1 <BB#19>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#19 BB#14
> CMP64mi8 <fi#3>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%nUnused.addr]
> JNE_1 <BB#19>, %EFLAGS<imp-use,kill>
1072B	BB#14: derived from LLVM BB %if.then.20
	    Predecessors according to CFG: BB#12 BB#13
1088B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
1104B		JE_1 <BB#16>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#16 BB#15
> CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
> JE_1 <BB#16>, %EFLAGS<imp-use,kill>
1120B	BB#15: derived from LLVM BB %if.then.22
	    Predecessors according to CFG: BB#14
1136B		%vreg41<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg41
1152B		MOV32mi %vreg41<kill>, 1, %noreg, 0, %noreg, -2; mem:ST4[%16] GR64:%vreg41
	    Successors according to CFG: BB#16
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 0, %noreg, -2; mem:ST4[%16]
1168B	BB#16: derived from LLVM BB %if.end.23
	    Predecessors according to CFG: BB#14 BB#15
1184B		CMP64mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
1200B		JE_1 <BB#18>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#18 BB#17
> CMP64mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
> JE_1 <BB#18>, %EFLAGS<imp-use,kill>
1216B	BB#17: derived from LLVM BB %if.then.25
	    Predecessors according to CFG: BB#16
1232B		%vreg44<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg44
1248B		MOV32mi %vreg44<kill>, 1, %noreg, 5096, %noreg, -2; mem:ST4[%lastErr26] GR64:%vreg44
	    Successors according to CFG: BB#18
> %RAX<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV32mi %RAX<kill>, 1, %noreg, 5096, %noreg, -2; mem:ST4[%lastErr26]
1264B	BB#18: derived from LLVM BB %if.end.27
	    Predecessors according to CFG: BB#16 BB#17
1280B		JMP_1 <BB#24>
	    Successors according to CFG: BB#24
> JMP_1 <BB#24>
1296B	BB#19: derived from LLVM BB %if.end.28
	    Predecessors according to CFG: BB#13
1312B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
1328B		JE_1 <BB#21>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#21 BB#20
> CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzerror.addr]
> JE_1 <BB#21>, %EFLAGS<imp-use,kill>
1344B	BB#20: derived from LLVM BB %if.then.30
	    Predecessors according to CFG: BB#19
1360B		%vreg23<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr] GR64:%vreg23
1376B		MOV32mi %vreg23<kill>, 1, %noreg, 0, %noreg, 0; mem:ST4[%20] GR64:%vreg23
	    Successors according to CFG: BB#21
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%bzerror.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 0, %noreg, 0; mem:ST4[%20]
1392B	BB#21: derived from LLVM BB %if.end.31
	    Predecessors according to CFG: BB#19 BB#20
1408B		CMP64mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
1424B		JE_1 <BB#23>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#23 BB#22
> CMP64mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzf]
> JE_1 <BB#23>, %EFLAGS<imp-use,kill>
1440B	BB#22: derived from LLVM BB %if.then.33
	    Predecessors according to CFG: BB#21
1456B		%vreg26<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg26
1472B		MOV32mi %vreg26<kill>, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr34] GR64:%vreg26
	    Successors according to CFG: BB#23
> %RAX<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> MOV32mi %RAX<kill>, 1, %noreg, 5096, %noreg, 0; mem:ST4[%lastErr34]
1488B	BB#23: derived from LLVM BB %if.end.35
	    Predecessors according to CFG: BB#21 BB#22
1504B		%vreg38<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg38
1520B		%vreg37<def> = MOV32rm %vreg38<kill>, 1, %noreg, 5024, %noreg; mem:LD4[%avail_in] GR32:%vreg37 GR64:%vreg38
1536B		%vreg35<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%nUnused.addr] GR64:%vreg35
1552B		MOV32mr %vreg35<kill>, 1, %noreg, 0, %noreg, %vreg37<kill>; mem:ST4[%25] GR64:%vreg35 GR32:%vreg37
1568B		%vreg32<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%bzf] GR64:%vreg32
1584B		%vreg31<def> = MOV64rm %vreg32<kill>, 1, %noreg, 5016, %noreg; mem:LD8[%next_in] GR64:%vreg31,%vreg32
1600B		%vreg29<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%unused.addr] GR64:%vreg29
1616B		MOV64mr %vreg29<kill>, 1, %noreg, 0, %noreg, %vreg31<kill>; mem:ST8[%28] GR64:%vreg29,%vreg31
	    Successors according to CFG: BB#24
> %RAX<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 5024, %noreg; mem:LD4[%avail_in]
> %RCX<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%nUnused.addr]
> MOV32mr %RCX<kill>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%25]
> %RAX<def> = MOV64rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD8[%bzf]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 5016, %noreg; mem:LD8[%next_in]
> %RCX<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%unused.addr]
> MOV64mr %RCX<kill>, 1, %noreg, 0, %noreg, %RAX<kill>; mem:ST8[%28]
1632B	BB#24: derived from LLVM BB %return
	    Predecessors according to CFG: BB#23 BB#18 BB#11 BB#5
1648B		%vreg58<def> = MOV64ri <ga:@BZ2_bzReadGetUnused>; GR64:%vreg58
1680B		%vreg59<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg59
1696B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1712B		%RDI<def> = COPY %vreg58<kill>; GR64:%vreg58
1728B		%RSI<def> = COPY %vreg59<kill>; GR64:%vreg59
1744B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
1760B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1776B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1792B		STACKMAP 1, 0, ...
1808B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1824B		RETQ
> %RDI<def> = MOV64ri <ga:@BZ2_bzReadGetUnused>
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 1, 0, ...
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> RETQ
Computing live-in reg-units in ABI blocks.
0B	BB#0 DIL#0 SIL#0 DH#0 DL#0 CH#0 CL#0 R8B#0 R9B#0
Created 8 new intervals.
********** INTERVALS **********
CH [0B,48r:0)[1248r,1264r:1)  0@0B-phi 1@1248r
CL [0B,48r:0)[1248r,1264r:1)  0@0B-phi 1@1248r
DH [0B,64r:0)[1232r,1264r:1)  0@0B-phi 1@1232r
DIL [0B,96r:0)[288r,320r:7)[1200r,1264r:6)[1680r,1712r:5)[2112r,2128r:4)[2304r,2320r:2)[2496r,2512r:3)[2720r,2752r:1)  0@0B-phi 1@2720r 2@2304r 3@2496r 4@2112r 5@1680r 6@1200r 7@288r
DL [0B,64r:0)[1232r,1264r:1)  0@0B-phi 1@1232r
SIL [0B,80r:0)[304r,320r:4)[1216r,1264r:2)[1696r,1712r:1)[2736r,2752r:3)  0@0B-phi 1@1696r 2@1216r 3@2736r 4@304r
R8B [0B,32r:0)  0@0B-phi
R9B [0B,16r:0)  0@0B-phi
%vreg0 [96r,208r:0)  0@96r
%vreg1 [80r,192r:0)  0@80r
%vreg2 [64r,176r:0)  0@64r
%vreg3 [48r,160r:0)  0@48r
%vreg4 [32r,144r:0)  0@32r
%vreg5 [16r,128r:0)  0@16r
%vreg6 [208r,400r:0)  0@208r
%vreg7 [192r,416r:0)  0@192r
%vreg8 [176r,432r:0)  0@176r
%vreg9 [160r,448r:0)  0@160r
%vreg10 [144r,464r:0)  0@144r
%vreg11 [128r,480r:0)  0@128r
%vreg12 [112r,496r:0)  0@112r
%vreg14 [224r,240r:0)  0@224r
%vreg15 [240r,288r:0)  0@240r
%vreg16 [256r,304r:0)  0@256r
%vreg28 [1072r,1200r:0)  0@1072r
%vreg32 [1296r,1360r:0)  0@1296r
%vreg33 [1168r,1248r:0)  0@1168r
%vreg34 [1152r,1232r:0)  0@1152r
%vreg35 [1136r,1216r:0)  0@1136r
%vreg38 [1488r,1680r:0)  0@1488r
%vreg39 [1504r,1696r:0)  0@1504r
%vreg40 [1744r,1808r:0)  0@1744r
%vreg43 [1632r,1648r:0)  0@1632r
%vreg44 [1616r,1632r:0)  0@1616r
%vreg46 [1584r,1600r:0)  0@1584r
%vreg48 [1552r,1568r:0)  0@1552r
%vreg50 [1520r,1536r:0)  0@1520r
%vreg52 [1984r,2112r:0)  0@1984r
%vreg53 [2160r,2160d:0)  0@2160r
%vreg58 [2048r,2064r:0)[2064r,2080r:1)  0@2048r 1@2064r
%vreg59 [2032r,2048r:0)  0@2032r
%vreg60 [2016r,2080r:0)  0@2016r
%vreg61 [2000r,2064r:0)  0@2000r
%vreg63 [2608r,2624r:0)  0@2608r
%vreg64 [2464r,2496r:0)  0@2464r
%vreg65 [2544r,2544d:0)  0@2544r
%vreg66 [2272r,2304r:0)  0@2272r
%vreg67 [2352r,2352d:0)  0@2352r
%vreg69 [1424r,1440r:0)  0@1424r
%vreg71 [2832r,2848r:0)  0@2832r
%vreg72 [2656r,2672r:0)  0@2656r
%vreg73 [2672r,2720r:0)  0@2672r
%vreg74 [2688r,2736r:0)  0@2688r
RegMasks: 320r 1264r 1712r 2128r 2320r 2512r 2752r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzBuffToBuffCompress: Post SSA
Frame Objects:
  fi#-2: size=8, align=8, fixed, at location [SP]
  fi#-1: size=4, align=16, fixed, at location [SP+8]
  fi#0: size=4, align=4, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=8, align=8, at location [SP+8]
  fi#3: size=8, align=8, at location [SP+8]
  fi#4: size=4, align=4, at location [SP+8]
  fi#5: size=4, align=4, at location [SP+8]
  fi#6: size=4, align=4, at location [SP+8]
  fi#7: size=4, align=4, at location [SP+8]
  fi#8: size=80, align=8, at location [SP+8]
  fi#9: size=4, align=4, at location [SP+8]
Function Live Ins: %RDI in %vreg0, %RSI in %vreg1, %RDX in %vreg2, %ECX in %vreg3, %R8D in %vreg4, %R9D in %vreg5

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI %RSI %RDX %ECX %R8D %R9D
16B		%vreg5<def> = COPY %R9D; GR32:%vreg5
32B		%vreg4<def> = COPY %R8D; GR32:%vreg4
48B		%vreg3<def> = COPY %ECX; GR32:%vreg3
64B		%vreg2<def> = COPY %RDX; GR64:%vreg2
80B		%vreg1<def> = COPY %RSI; GR64:%vreg1
96B		%vreg0<def> = COPY %RDI; GR64:%vreg0
112B		%vreg12<def> = MOV32rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD4[FixedStack-1] GR32:%vreg12
128B		%vreg11<def> = COPY %vreg5; GR32:%vreg11,%vreg5
144B		%vreg10<def> = COPY %vreg4; GR32:%vreg10,%vreg4
160B		%vreg9<def> = COPY %vreg3; GR32:%vreg9,%vreg3
176B		%vreg8<def> = COPY %vreg2; GR64:%vreg8,%vreg2
192B		%vreg7<def> = COPY %vreg1; GR64:%vreg7,%vreg1
208B		%vreg6<def> = COPY %vreg0; GR64:%vreg6,%vreg0
224B		%vreg14<def> = MOV64ri <ga:@BZ2_bzBuffToBuffCompress>; GR64:%vreg14
240B		%vreg15<def> = COPY %vreg14; GR64:%vreg15,%vreg14
256B		%vreg16<def> = MOV64rm <fi#-2>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-2] GR64:%vreg16
272B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
288B		%RDI<def> = COPY %vreg15; GR64:%vreg15
304B		%RSI<def> = COPY %vreg16; GR64:%vreg16
320B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
336B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
352B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
368B		STACKMAP 0, 0, %vreg10, 0, <fi#5>, 0, %vreg6, 0, <fi#1>, 0, %vreg7, 0, <fi#2>, 0, 0, <fi#9>, 0, 0, <fi#0>, 0, %vreg8, 0, <fi#3>, 0, %vreg9, 0, <fi#4>, 0, 0, <fi#8>, 0, %vreg11, 0, <fi#6>, 0, %vreg12, 0, <fi#7>, 0, ...; mem:LD8[FixedStack5](align=4) LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack9](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3] LD8[FixedStack4](align=4) LD8[FixedStack8] LD8[FixedStack6](align=4) LD8[FixedStack7](align=4) GR32:%vreg10,%vreg9,%vreg11,%vreg12 GR64:%vreg6,%vreg7,%vreg8
384B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
400B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg6; mem:ST8[%dest.addr] GR64:%vreg6
416B		MOV64mr <fi#2>, 1, %noreg, 0, %noreg, %vreg7; mem:ST8[%destLen.addr] GR64:%vreg7
432B		MOV64mr <fi#3>, 1, %noreg, 0, %noreg, %vreg8; mem:ST8[%source.addr] GR64:%vreg8
448B		MOV32mr <fi#4>, 1, %noreg, 0, %noreg, %vreg9; mem:ST4[%sourceLen.addr] GR32:%vreg9
464B		MOV32mr <fi#5>, 1, %noreg, 0, %noreg, %vreg10; mem:ST4[%blockSize100k.addr] GR32:%vreg10
480B		MOV32mr <fi#6>, 1, %noreg, 0, %noreg, %vreg11; mem:ST4[%verbosity.addr] GR32:%vreg11
496B		MOV32mr <fi#7>, 1, %noreg, 0, %noreg, %vreg12; mem:ST4[%workFactor.addr] GR32:%vreg12
512B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%dest.addr]
528B		JE_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#1

544B	BB#1: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#0
560B		CMP64mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%destLen.addr]
576B		JE_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#2

592B	BB#2: derived from LLVM BB %lor.lhs.false.2
	    Predecessors according to CFG: BB#1
608B		CMP64mi8 <fi#3>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%source.addr]
624B		JE_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#3

640B	BB#3: derived from LLVM BB %lor.lhs.false.4
	    Predecessors according to CFG: BB#2
656B		CMP32mi8 <fi#5>, 1, %noreg, 0, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%blockSize100k.addr]
672B		JL_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#4

688B	BB#4: derived from LLVM BB %lor.lhs.false.6
	    Predecessors according to CFG: BB#3
704B		CMP32mi8 <fi#5>, 1, %noreg, 0, %noreg, 9, %EFLAGS<imp-def>; mem:LD4[%blockSize100k.addr]
720B		JG_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#5

736B	BB#5: derived from LLVM BB %lor.lhs.false.8
	    Predecessors according to CFG: BB#4
752B		CMP32mi8 <fi#6>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%verbosity.addr]
768B		JL_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#6

784B	BB#6: derived from LLVM BB %lor.lhs.false.10
	    Predecessors according to CFG: BB#5
800B		CMP32mi8 <fi#6>, 1, %noreg, 0, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%verbosity.addr]
816B		JG_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#7

832B	BB#7: derived from LLVM BB %lor.lhs.false.12
	    Predecessors according to CFG: BB#6
848B		CMP32mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%workFactor.addr]
864B		JL_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#8

880B	BB#8: derived from LLVM BB %lor.lhs.false.14
	    Predecessors according to CFG: BB#7
896B		CMP32mi <fi#7>, 1, %noreg, 0, %noreg, 250, %EFLAGS<imp-def>; mem:LD4[%workFactor.addr]
912B		JLE_1 <BB#10>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#10 BB#9

928B	BB#9: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0 BB#1 BB#2 BB#3 BB#4 BB#5 BB#6 BB#7 BB#8
944B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
960B		JMP_1 <BB#21>
	    Successors according to CFG: BB#21

976B	BB#10: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#8
992B		CMP32mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%workFactor.addr]
1008B		JNE_1 <BB#12>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#12 BB#11

1024B	BB#11: derived from LLVM BB %if.then.17
	    Predecessors according to CFG: BB#10
1040B		MOV32mi <fi#7>, 1, %noreg, 0, %noreg, 30; mem:ST4[%workFactor.addr]
	    Successors according to CFG: BB#12

1056B	BB#12: derived from LLVM BB %if.end.18
	    Predecessors according to CFG: BB#10 BB#11
1072B		%vreg28<def> = LEA64r <fi#8>, 1, %noreg, 0, %noreg; GR64:%vreg28
1088B		MOV64mi32 <fi#8>, 1, %noreg, 56, %noreg, 0; mem:ST8[%bzalloc]
1104B		MOV64mi32 <fi#8>, 1, %noreg, 64, %noreg, 0; mem:ST8[%bzfree]
1120B		MOV64mi32 <fi#8>, 1, %noreg, 72, %noreg, 0; mem:ST8[%opaque]
1136B		%vreg35<def> = MOV32rm <fi#5>, 1, %noreg, 0, %noreg; mem:LD4[%blockSize100k.addr] GR32:%vreg35
1152B		%vreg34<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%verbosity.addr] GR32:%vreg34
1168B		%vreg33<def> = MOV32rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD4[%workFactor.addr] GR32:%vreg33
1184B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1200B		%RDI<def> = COPY %vreg28; GR64:%vreg28
1216B		%ESI<def> = COPY %vreg35; GR32:%vreg35
1232B		%EDX<def> = COPY %vreg34; GR32:%vreg34
1248B		%ECX<def> = COPY %vreg33; GR32:%vreg33
1264B		CALL64pcrel32 <ga:@BZ2_bzCompressInit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %EDX<imp-use>, %ECX<imp-use>, %EAX<imp-def>
1280B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1296B		%vreg32<def> = COPY %EAX<kill>; GR32:%vreg32
1312B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1328B		STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#9>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, 0, <fi#8>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack9](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3] LD8[FixedStack4](align=4) LD8[FixedStack8]
1344B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1360B		MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %vreg32; mem:ST4[%ret] GR32:%vreg32
1376B		CMP32mi8 <fi#9>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%ret]
1392B		JE_1 <BB#14>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#14 BB#13

1408B	BB#13: derived from LLVM BB %if.then.20
	    Predecessors according to CFG: BB#12
1424B		%vreg69<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%ret] GR32:%vreg69
1440B		MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %vreg69; mem:ST4[%retval] GR32:%vreg69
1456B		JMP_1 <BB#21>
	    Successors according to CFG: BB#21

1472B	BB#14: derived from LLVM BB %if.end.21
	    Predecessors according to CFG: BB#12
1488B		%vreg38<def> = LEA64r <fi#8>, 1, %noreg, 0, %noreg; GR64:%vreg38
1504B		%vreg39<def> = MOV32ri 2; GR32:%vreg39
1520B		%vreg50<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%source.addr] GR64:%vreg50
1536B		MOV64mr <fi#8>, 1, %noreg, 0, %noreg, %vreg50; mem:ST8[%next_in] GR64:%vreg50
1552B		%vreg48<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%dest.addr] GR64:%vreg48
1568B		MOV64mr <fi#8>, 1, %noreg, 24, %noreg, %vreg48; mem:ST8[%next_out] GR64:%vreg48
1584B		%vreg46<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%sourceLen.addr] GR32:%vreg46
1600B		MOV32mr <fi#8>, 1, %noreg, 8, %noreg, %vreg46; mem:ST4[%avail_in] GR32:%vreg46
1616B		%vreg44<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%destLen.addr] GR64:%vreg44
1632B		%vreg43<def> = MOV32rm %vreg44, 1, %noreg, 0, %noreg; mem:LD4[%18] GR32:%vreg43 GR64:%vreg44
1648B		MOV32mr <fi#8>, 1, %noreg, 32, %noreg, %vreg43; mem:ST4[%avail_out] GR32:%vreg43
1664B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1680B		%RDI<def> = COPY %vreg38; GR64:%vreg38
1696B		%ESI<def> = COPY %vreg39; GR32:%vreg39
1712B		CALL64pcrel32 <ga:@BZ2_bzCompress>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %EAX<imp-def>
1728B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1744B		%vreg40<def> = COPY %EAX<kill>; GR32:%vreg40
1760B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1776B		STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#9>, 0, 0, <fi#0>, 0, 0, <fi#8>, 0, ...; mem:LD8[FixedStack2] LD8[FixedStack9](align=4) LD8[FixedStack0](align=4) LD8[FixedStack8]
1792B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1808B		MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %vreg40; mem:ST4[%ret] GR32:%vreg40
1824B		CMP32mi8 <fi#9>, 1, %noreg, 0, %noreg, 3, %EFLAGS<imp-def>; mem:LD4[%ret]
1840B		JNE_1 <BB#16>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#16 BB#15

1856B	BB#15: derived from LLVM BB %if.then.24
	    Predecessors according to CFG: BB#14
1872B		JMP_1 <BB#19>
	    Successors according to CFG: BB#19

1888B	BB#16: derived from LLVM BB %if.end.25
	    Predecessors according to CFG: BB#14
1904B		CMP32mi8 <fi#9>, 1, %noreg, 0, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%ret]
1920B		JE_1 <BB#18>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#18 BB#17

1936B	BB#17: derived from LLVM BB %if.then.27
	    Predecessors according to CFG: BB#16
1952B		JMP_1 <BB#20>
	    Successors according to CFG: BB#20

1968B	BB#18: derived from LLVM BB %if.end.28
	    Predecessors according to CFG: BB#16
1984B		%vreg52<def> = LEA64r <fi#8>, 1, %noreg, 0, %noreg; GR64:%vreg52
2000B		%vreg61<def> = MOV32rm <fi#8>, 1, %noreg, 32, %noreg; mem:LD4[%avail_out29] GR32:%vreg61
2016B		%vreg60<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%destLen.addr] GR64:%vreg60
2032B		%vreg59<def> = MOV32rm %vreg60, 1, %noreg, 0, %noreg; mem:LD4[%23] GR32:%vreg59 GR64:%vreg60
2048B		%vreg58<def> = COPY %vreg59; GR32:%vreg58,%vreg59
2064B		%vreg58<def,tied1> = SUB32rr %vreg58<tied0>, %vreg61, %EFLAGS<imp-def,dead>; GR32:%vreg58,%vreg61
2080B		MOV32mr %vreg60, 1, %noreg, 0, %noreg, %vreg58; mem:ST4[%23] GR64:%vreg60 GR32:%vreg58
2096B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2112B		%RDI<def> = COPY %vreg52; GR64:%vreg52
2128B		CALL64pcrel32 <ga:@BZ2_bzCompressEnd>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
2144B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2160B		%vreg53<def,dead> = COPY %EAX<kill>; GR32:%vreg53
2176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2192B		STACKMAP 3, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
2208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2224B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
2240B		JMP_1 <BB#21>
	    Successors according to CFG: BB#21

2256B	BB#19: derived from LLVM BB %output_overflow
	    Predecessors according to CFG: BB#15
2272B		%vreg66<def> = LEA64r <fi#8>, 1, %noreg, 0, %noreg; GR64:%vreg66
2288B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2304B		%RDI<def> = COPY %vreg66; GR64:%vreg66
2320B		CALL64pcrel32 <ga:@BZ2_bzCompressEnd>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
2336B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2352B		%vreg67<def,dead> = COPY %EAX<kill>; GR32:%vreg67
2368B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2384B		STACKMAP 4, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
2400B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2416B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -8; mem:ST4[%retval]
2432B		JMP_1 <BB#21>
	    Successors according to CFG: BB#21

2448B	BB#20: derived from LLVM BB %errhandler
	    Predecessors according to CFG: BB#17
2464B		%vreg64<def> = LEA64r <fi#8>, 1, %noreg, 0, %noreg; GR64:%vreg64
2480B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2496B		%RDI<def> = COPY %vreg64; GR64:%vreg64
2512B		CALL64pcrel32 <ga:@BZ2_bzCompressEnd>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
2528B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2544B		%vreg65<def,dead> = COPY %EAX<kill>; GR32:%vreg65
2560B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2576B		STACKMAP 5, 0, 0, <fi#9>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack9](align=4) LD8[FixedStack0](align=4)
2592B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2608B		%vreg63<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%ret] GR32:%vreg63
2624B		MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %vreg63; mem:ST4[%retval] GR32:%vreg63
	    Successors according to CFG: BB#21

2640B	BB#21: derived from LLVM BB %return
	    Predecessors according to CFG: BB#18 BB#20 BB#19 BB#13 BB#9
2656B		%vreg72<def> = MOV64ri <ga:@BZ2_bzBuffToBuffCompress>; GR64:%vreg72
2672B		%vreg73<def> = COPY %vreg72; GR64:%vreg73,%vreg72
2688B		%vreg74<def> = MOV64rm <fi#-2>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-2] GR64:%vreg74
2704B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2720B		%RDI<def> = COPY %vreg73; GR64:%vreg73
2736B		%RSI<def> = COPY %vreg74; GR64:%vreg74
2752B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
2768B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2784B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2800B		STACKMAP 6, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
2816B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2832B		%vreg71<def> = MOV32rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD4[%retval] GR32:%vreg71
2848B		%EAX<def> = COPY %vreg71; GR32:%vreg71
2864B		RETQ %EAX<imp-use,kill>

# End machine code for function BZ2_bzBuffToBuffCompress.

********** SIMPLE REGISTER COALESCING **********
********** Function: BZ2_bzBuffToBuffCompress
********** JOINING INTERVALS ***********
if.then:
return:
2720B	%RDI<def> = COPY %vreg73; GR64:%vreg73
	Considering merging %vreg73 with %RDI
	Can only merge into reserved registers.
2736B	%RSI<def> = COPY %vreg74; GR64:%vreg74
	Considering merging %vreg74 with %RSI
	Can only merge into reserved registers.
2848B	%EAX<def> = COPY %vreg71; GR32:%vreg71
	Considering merging %vreg71 with %EAX
	Can only merge into reserved registers.
if.end.18:
1200B	%RDI<def> = COPY %vreg28; GR64:%vreg28
	Considering merging %vreg28 with %RDI
	Can only merge into reserved registers.
1216B	%ESI<def> = COPY %vreg35; GR32:%vreg35
	Considering merging %vreg35 with %ESI
	Can only merge into reserved registers.
1232B	%EDX<def> = COPY %vreg34; GR32:%vreg34
	Considering merging %vreg34 with %EDX
	Can only merge into reserved registers.
1248B	%ECX<def> = COPY %vreg33; GR32:%vreg33
	Considering merging %vreg33 with %ECX
	Can only merge into reserved registers.
1296B	%vreg32<def> = COPY %EAX<kill>; GR32:%vreg32
	Considering merging %vreg32 with %EAX
	Can only merge into reserved registers.
lor.lhs.false:
lor.lhs.false.2:
lor.lhs.false.4:
lor.lhs.false.6:
lor.lhs.false.8:
lor.lhs.false.10:
lor.lhs.false.12:
lor.lhs.false.14:
if.end:
if.end.21:
1680B	%RDI<def> = COPY %vreg38; GR64:%vreg38
	Considering merging %vreg38 with %RDI
	Can only merge into reserved registers.
1696B	%ESI<def> = COPY %vreg39; GR32:%vreg39
	Considering merging %vreg39 with %ESI
	Can only merge into reserved registers.
Remat: %ESI<def> = MOV32ri 2
Shrink: %vreg39 [1504r,1696r:0)  0@1504r
All defs dead: 1504r	%vreg39<def,dead> = MOV32ri 2; GR32:%vreg39
Shrunk: %vreg39 [1504r,1504d:0)  0@1504r
Deleting dead def 1504r	%vreg39<def,dead> = MOV32ri 2; GR32:%vreg39
1744B	%vreg40<def> = COPY %EAX<kill>; GR32:%vreg40
	Considering merging %vreg40 with %EAX
	Can only merge into reserved registers.
if.end.25:
entry:
16B	%vreg5<def> = COPY %R9D; GR32:%vreg5
	Considering merging %vreg5 with %R9D
	Can only merge into reserved registers.
32B	%vreg4<def> = COPY %R8D; GR32:%vreg4
	Considering merging %vreg4 with %R8D
	Can only merge into reserved registers.
48B	%vreg3<def> = COPY %ECX; GR32:%vreg3
	Considering merging %vreg3 with %ECX
	Can only merge into reserved registers.
64B	%vreg2<def> = COPY %RDX; GR64:%vreg2
	Considering merging %vreg2 with %RDX
	Can only merge into reserved registers.
80B	%vreg1<def> = COPY %RSI; GR64:%vreg1
	Considering merging %vreg1 with %RSI
	Can only merge into reserved registers.
96B	%vreg0<def> = COPY %RDI; GR64:%vreg0
	Considering merging %vreg0 with %RDI
	Can only merge into reserved registers.
288B	%RDI<def> = COPY %vreg15; GR64:%vreg15
	Considering merging %vreg15 with %RDI
	Can only merge into reserved registers.
304B	%RSI<def> = COPY %vreg16; GR64:%vreg16
	Considering merging %vreg16 with %RSI
	Can only merge into reserved registers.
if.then.17:
if.then.20:
if.then.24:
if.then.27:
if.end.28:
2112B	%RDI<def> = COPY %vreg52; GR64:%vreg52
	Considering merging %vreg52 with %RDI
	Can only merge into reserved registers.
2160B	%vreg53<def,dead> = COPY %EAX<kill>; GR32:%vreg53
	Considering merging %vreg53 with %EAX
	Can only merge into reserved registers.
output_overflow:
2304B	%RDI<def> = COPY %vreg66; GR64:%vreg66
	Considering merging %vreg66 with %RDI
	Can only merge into reserved registers.
2352B	%vreg67<def,dead> = COPY %EAX<kill>; GR32:%vreg67
	Considering merging %vreg67 with %EAX
	Can only merge into reserved registers.
errhandler:
2496B	%RDI<def> = COPY %vreg64; GR64:%vreg64
	Considering merging %vreg64 with %RDI
	Can only merge into reserved registers.
2544B	%vreg65<def,dead> = COPY %EAX<kill>; GR32:%vreg65
	Considering merging %vreg65 with %EAX
	Can only merge into reserved registers.
2672B	%vreg73<def> = COPY %vreg72; GR64:%vreg73,%vreg72
	Considering merging to GR64 with %vreg72 in %vreg73
		RHS = %vreg72 [2656r,2672r:0)  0@2656r
		LHS = %vreg73 [2672r,2720r:0)  0@2672r
		merge %vreg73:0@2672r into %vreg72:0@2656r --> @2656r
		erased:	2672r	%vreg73<def> = COPY %vreg72; GR64:%vreg73,%vreg72
		updated: 2656B	%vreg73<def> = MOV64ri <ga:@BZ2_bzBuffToBuffCompress>; GR64:%vreg73
	Success: %vreg72 -> %vreg73
	Result = %vreg73 [2656r,2720r:0)  0@2656r
128B	%vreg11<def> = COPY %vreg5; GR32:%vreg11,%vreg5
	Considering merging to GR32 with %vreg5 in %vreg11
		RHS = %vreg5 [16r,128r:0)  0@16r
		LHS = %vreg11 [128r,480r:0)  0@128r
		merge %vreg11:0@128r into %vreg5:0@16r --> @16r
		erased:	128r	%vreg11<def> = COPY %vreg5; GR32:%vreg11,%vreg5
		updated: 16B	%vreg11<def> = COPY %R9D; GR32:%vreg11
	Success: %vreg5 -> %vreg11
	Result = %vreg11 [16r,480r:0)  0@16r
144B	%vreg10<def> = COPY %vreg4; GR32:%vreg10,%vreg4
	Considering merging to GR32 with %vreg4 in %vreg10
		RHS = %vreg4 [32r,144r:0)  0@32r
		LHS = %vreg10 [144r,464r:0)  0@144r
		merge %vreg10:0@144r into %vreg4:0@32r --> @32r
		erased:	144r	%vreg10<def> = COPY %vreg4; GR32:%vreg10,%vreg4
		updated: 32B	%vreg10<def> = COPY %R8D; GR32:%vreg10
	Success: %vreg4 -> %vreg10
	Result = %vreg10 [32r,464r:0)  0@32r
160B	%vreg9<def> = COPY %vreg3; GR32:%vreg9,%vreg3
	Considering merging to GR32 with %vreg3 in %vreg9
		RHS = %vreg3 [48r,160r:0)  0@48r
		LHS = %vreg9 [160r,448r:0)  0@160r
		merge %vreg9:0@160r into %vreg3:0@48r --> @48r
		erased:	160r	%vreg9<def> = COPY %vreg3; GR32:%vreg9,%vreg3
		updated: 48B	%vreg9<def> = COPY %ECX; GR32:%vreg9
	Success: %vreg3 -> %vreg9
	Result = %vreg9 [48r,448r:0)  0@48r
176B	%vreg8<def> = COPY %vreg2; GR64:%vreg8,%vreg2
	Considering merging to GR64 with %vreg2 in %vreg8
		RHS = %vreg2 [64r,176r:0)  0@64r
		LHS = %vreg8 [176r,432r:0)  0@176r
		merge %vreg8:0@176r into %vreg2:0@64r --> @64r
		erased:	176r	%vreg8<def> = COPY %vreg2; GR64:%vreg8,%vreg2
		updated: 64B	%vreg8<def> = COPY %RDX; GR64:%vreg8
	Success: %vreg2 -> %vreg8
	Result = %vreg8 [64r,432r:0)  0@64r
192B	%vreg7<def> = COPY %vreg1; GR64:%vreg7,%vreg1
	Considering merging to GR64 with %vreg1 in %vreg7
		RHS = %vreg1 [80r,192r:0)  0@80r
		LHS = %vreg7 [192r,416r:0)  0@192r
		merge %vreg7:0@192r into %vreg1:0@80r --> @80r
		erased:	192r	%vreg7<def> = COPY %vreg1; GR64:%vreg7,%vreg1
		updated: 80B	%vreg7<def> = COPY %RSI; GR64:%vreg7
	Success: %vreg1 -> %vreg7
	Result = %vreg7 [80r,416r:0)  0@80r
208B	%vreg6<def> = COPY %vreg0; GR64:%vreg6,%vreg0
	Considering merging to GR64 with %vreg0 in %vreg6
		RHS = %vreg0 [96r,208r:0)  0@96r
		LHS = %vreg6 [208r,400r:0)  0@208r
		merge %vreg6:0@208r into %vreg0:0@96r --> @96r
		erased:	208r	%vreg6<def> = COPY %vreg0; GR64:%vreg6,%vreg0
		updated: 96B	%vreg6<def> = COPY %RDI; GR64:%vreg6
	Success: %vreg0 -> %vreg6
	Result = %vreg6 [96r,400r:0)  0@96r
240B	%vreg15<def> = COPY %vreg14; GR64:%vreg15,%vreg14
	Considering merging to GR64 with %vreg14 in %vreg15
		RHS = %vreg14 [224r,240r:0)  0@224r
		LHS = %vreg15 [240r,288r:0)  0@240r
		merge %vreg15:0@240r into %vreg14:0@224r --> @224r
		erased:	240r	%vreg15<def> = COPY %vreg14; GR64:%vreg15,%vreg14
		updated: 224B	%vreg15<def> = MOV64ri <ga:@BZ2_bzBuffToBuffCompress>; GR64:%vreg15
	Success: %vreg14 -> %vreg15
	Result = %vreg15 [224r,288r:0)  0@224r
2048B	%vreg58<def> = COPY %vreg59; GR32:%vreg58,%vreg59
	Considering merging to GR32 with %vreg59 in %vreg58
		RHS = %vreg59 [2032r,2048r:0)  0@2032r
		LHS = %vreg58 [2048r,2064r:0)[2064r,2080r:1)  0@2048r 1@2064r
		merge %vreg58:0@2048r into %vreg59:0@2032r --> @2032r
		erased:	2048r	%vreg58<def> = COPY %vreg59; GR32:%vreg58,%vreg59
		updated: 2032B	%vreg58<def> = MOV32rm %vreg60, 1, %noreg, 0, %noreg; mem:LD4[%23] GR32:%vreg58 GR64:%vreg60
	Success: %vreg59 -> %vreg58
	Result = %vreg58 [2032r,2064r:0)[2064r,2080r:1)  0@2032r 1@2064r
2720B	%RDI<def> = COPY %vreg73; GR64:%vreg73
	Considering merging %vreg73 with %RDI
	Can only merge into reserved registers.
288B	%RDI<def> = COPY %vreg15; GR64:%vreg15
	Considering merging %vreg15 with %RDI
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
CH [0B,48r:0)[1248r,1264r:1)  0@0B-phi 1@1248r
CL [0B,48r:0)[1248r,1264r:1)  0@0B-phi 1@1248r
DH [0B,64r:0)[1232r,1264r:1)  0@0B-phi 1@1232r
DIL [0B,96r:0)[288r,320r:7)[1200r,1264r:6)[1680r,1712r:5)[2112r,2128r:4)[2304r,2320r:2)[2496r,2512r:3)[2720r,2752r:1)  0@0B-phi 1@2720r 2@2304r 3@2496r 4@2112r 5@1680r 6@1200r 7@288r
DL [0B,64r:0)[1232r,1264r:1)  0@0B-phi 1@1232r
SIL [0B,80r:0)[304r,320r:4)[1216r,1264r:2)[1696r,1712r:1)[2736r,2752r:3)  0@0B-phi 1@1696r 2@1216r 3@2736r 4@304r
R8B [0B,32r:0)  0@0B-phi
R9B [0B,16r:0)  0@0B-phi
%vreg6 [96r,400r:0)  0@96r
%vreg7 [80r,416r:0)  0@80r
%vreg8 [64r,432r:0)  0@64r
%vreg9 [48r,448r:0)  0@48r
%vreg10 [32r,464r:0)  0@32r
%vreg11 [16r,480r:0)  0@16r
%vreg12 [112r,496r:0)  0@112r
%vreg15 [224r,288r:0)  0@224r
%vreg16 [256r,304r:0)  0@256r
%vreg28 [1072r,1200r:0)  0@1072r
%vreg32 [1296r,1360r:0)  0@1296r
%vreg33 [1168r,1248r:0)  0@1168r
%vreg34 [1152r,1232r:0)  0@1152r
%vreg35 [1136r,1216r:0)  0@1136r
%vreg38 [1488r,1680r:0)  0@1488r
%vreg40 [1744r,1808r:0)  0@1744r
%vreg43 [1632r,1648r:0)  0@1632r
%vreg44 [1616r,1632r:0)  0@1616r
%vreg46 [1584r,1600r:0)  0@1584r
%vreg48 [1552r,1568r:0)  0@1552r
%vreg50 [1520r,1536r:0)  0@1520r
%vreg52 [1984r,2112r:0)  0@1984r
%vreg53 [2160r,2160d:0)  0@2160r
%vreg58 [2032r,2064r:0)[2064r,2080r:1)  0@2032r 1@2064r
%vreg60 [2016r,2080r:0)  0@2016r
%vreg61 [2000r,2064r:0)  0@2000r
%vreg63 [2608r,2624r:0)  0@2608r
%vreg64 [2464r,2496r:0)  0@2464r
%vreg65 [2544r,2544d:0)  0@2544r
%vreg66 [2272r,2304r:0)  0@2272r
%vreg67 [2352r,2352d:0)  0@2352r
%vreg69 [1424r,1440r:0)  0@1424r
%vreg71 [2832r,2848r:0)  0@2832r
%vreg73 [2656r,2720r:0)  0@2656r
%vreg74 [2688r,2736r:0)  0@2688r
RegMasks: 320r 1264r 1712r 2128r 2320r 2512r 2752r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzBuffToBuffCompress: Post SSA
Frame Objects:
  fi#-2: size=8, align=8, fixed, at location [SP]
  fi#-1: size=4, align=16, fixed, at location [SP+8]
  fi#0: size=4, align=4, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=8, align=8, at location [SP+8]
  fi#3: size=8, align=8, at location [SP+8]
  fi#4: size=4, align=4, at location [SP+8]
  fi#5: size=4, align=4, at location [SP+8]
  fi#6: size=4, align=4, at location [SP+8]
  fi#7: size=4, align=4, at location [SP+8]
  fi#8: size=80, align=8, at location [SP+8]
  fi#9: size=4, align=4, at location [SP+8]
Function Live Ins: %RDI in %vreg0, %RSI in %vreg1, %RDX in %vreg2, %ECX in %vreg3, %R8D in %vreg4, %R9D in %vreg5

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI %RSI %RDX %ECX %R8D %R9D
16B		%vreg11<def> = COPY %R9D; GR32:%vreg11
32B		%vreg10<def> = COPY %R8D; GR32:%vreg10
48B		%vreg9<def> = COPY %ECX; GR32:%vreg9
64B		%vreg8<def> = COPY %RDX; GR64:%vreg8
80B		%vreg7<def> = COPY %RSI; GR64:%vreg7
96B		%vreg6<def> = COPY %RDI; GR64:%vreg6
112B		%vreg12<def> = MOV32rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD4[FixedStack-1] GR32:%vreg12
224B		%vreg15<def> = MOV64ri <ga:@BZ2_bzBuffToBuffCompress>; GR64:%vreg15
256B		%vreg16<def> = MOV64rm <fi#-2>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-2] GR64:%vreg16
272B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
288B		%RDI<def> = COPY %vreg15; GR64:%vreg15
304B		%RSI<def> = COPY %vreg16; GR64:%vreg16
320B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
336B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
352B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
368B		STACKMAP 0, 0, %vreg10, 0, <fi#5>, 0, %vreg6, 0, <fi#1>, 0, %vreg7, 0, <fi#2>, 0, 0, <fi#9>, 0, 0, <fi#0>, 0, %vreg8, 0, <fi#3>, 0, %vreg9, 0, <fi#4>, 0, 0, <fi#8>, 0, %vreg11, 0, <fi#6>, 0, %vreg12, 0, <fi#7>, 0, ...; mem:LD8[FixedStack5](align=4) LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack9](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3] LD8[FixedStack4](align=4) LD8[FixedStack8] LD8[FixedStack6](align=4) LD8[FixedStack7](align=4) GR32:%vreg10,%vreg9,%vreg11,%vreg12 GR64:%vreg6,%vreg7,%vreg8
384B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
400B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg6; mem:ST8[%dest.addr] GR64:%vreg6
416B		MOV64mr <fi#2>, 1, %noreg, 0, %noreg, %vreg7; mem:ST8[%destLen.addr] GR64:%vreg7
432B		MOV64mr <fi#3>, 1, %noreg, 0, %noreg, %vreg8; mem:ST8[%source.addr] GR64:%vreg8
448B		MOV32mr <fi#4>, 1, %noreg, 0, %noreg, %vreg9; mem:ST4[%sourceLen.addr] GR32:%vreg9
464B		MOV32mr <fi#5>, 1, %noreg, 0, %noreg, %vreg10; mem:ST4[%blockSize100k.addr] GR32:%vreg10
480B		MOV32mr <fi#6>, 1, %noreg, 0, %noreg, %vreg11; mem:ST4[%verbosity.addr] GR32:%vreg11
496B		MOV32mr <fi#7>, 1, %noreg, 0, %noreg, %vreg12; mem:ST4[%workFactor.addr] GR32:%vreg12
512B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%dest.addr]
528B		JE_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#1

544B	BB#1: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#0
560B		CMP64mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%destLen.addr]
576B		JE_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#2

592B	BB#2: derived from LLVM BB %lor.lhs.false.2
	    Predecessors according to CFG: BB#1
608B		CMP64mi8 <fi#3>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%source.addr]
624B		JE_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#3

640B	BB#3: derived from LLVM BB %lor.lhs.false.4
	    Predecessors according to CFG: BB#2
656B		CMP32mi8 <fi#5>, 1, %noreg, 0, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%blockSize100k.addr]
672B		JL_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#4

688B	BB#4: derived from LLVM BB %lor.lhs.false.6
	    Predecessors according to CFG: BB#3
704B		CMP32mi8 <fi#5>, 1, %noreg, 0, %noreg, 9, %EFLAGS<imp-def>; mem:LD4[%blockSize100k.addr]
720B		JG_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#5

736B	BB#5: derived from LLVM BB %lor.lhs.false.8
	    Predecessors according to CFG: BB#4
752B		CMP32mi8 <fi#6>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%verbosity.addr]
768B		JL_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#6

784B	BB#6: derived from LLVM BB %lor.lhs.false.10
	    Predecessors according to CFG: BB#5
800B		CMP32mi8 <fi#6>, 1, %noreg, 0, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%verbosity.addr]
816B		JG_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#7

832B	BB#7: derived from LLVM BB %lor.lhs.false.12
	    Predecessors according to CFG: BB#6
848B		CMP32mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%workFactor.addr]
864B		JL_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#8

880B	BB#8: derived from LLVM BB %lor.lhs.false.14
	    Predecessors according to CFG: BB#7
896B		CMP32mi <fi#7>, 1, %noreg, 0, %noreg, 250, %EFLAGS<imp-def>; mem:LD4[%workFactor.addr]
912B		JLE_1 <BB#10>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#10 BB#9

928B	BB#9: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0 BB#1 BB#2 BB#3 BB#4 BB#5 BB#6 BB#7 BB#8
944B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
960B		JMP_1 <BB#21>
	    Successors according to CFG: BB#21

976B	BB#10: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#8
992B		CMP32mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%workFactor.addr]
1008B		JNE_1 <BB#12>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#12 BB#11

1024B	BB#11: derived from LLVM BB %if.then.17
	    Predecessors according to CFG: BB#10
1040B		MOV32mi <fi#7>, 1, %noreg, 0, %noreg, 30; mem:ST4[%workFactor.addr]
	    Successors according to CFG: BB#12

1056B	BB#12: derived from LLVM BB %if.end.18
	    Predecessors according to CFG: BB#10 BB#11
1072B		%vreg28<def> = LEA64r <fi#8>, 1, %noreg, 0, %noreg; GR64:%vreg28
1088B		MOV64mi32 <fi#8>, 1, %noreg, 56, %noreg, 0; mem:ST8[%bzalloc]
1104B		MOV64mi32 <fi#8>, 1, %noreg, 64, %noreg, 0; mem:ST8[%bzfree]
1120B		MOV64mi32 <fi#8>, 1, %noreg, 72, %noreg, 0; mem:ST8[%opaque]
1136B		%vreg35<def> = MOV32rm <fi#5>, 1, %noreg, 0, %noreg; mem:LD4[%blockSize100k.addr] GR32:%vreg35
1152B		%vreg34<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%verbosity.addr] GR32:%vreg34
1168B		%vreg33<def> = MOV32rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD4[%workFactor.addr] GR32:%vreg33
1184B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1200B		%RDI<def> = COPY %vreg28; GR64:%vreg28
1216B		%ESI<def> = COPY %vreg35; GR32:%vreg35
1232B		%EDX<def> = COPY %vreg34; GR32:%vreg34
1248B		%ECX<def> = COPY %vreg33; GR32:%vreg33
1264B		CALL64pcrel32 <ga:@BZ2_bzCompressInit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %EDX<imp-use>, %ECX<imp-use>, %EAX<imp-def>
1280B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1296B		%vreg32<def> = COPY %EAX<kill>; GR32:%vreg32
1312B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1328B		STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#9>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, 0, <fi#8>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack9](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3] LD8[FixedStack4](align=4) LD8[FixedStack8]
1344B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1360B		MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %vreg32; mem:ST4[%ret] GR32:%vreg32
1376B		CMP32mi8 <fi#9>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%ret]
1392B		JE_1 <BB#14>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#14 BB#13

1408B	BB#13: derived from LLVM BB %if.then.20
	    Predecessors according to CFG: BB#12
1424B		%vreg69<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%ret] GR32:%vreg69
1440B		MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %vreg69; mem:ST4[%retval] GR32:%vreg69
1456B		JMP_1 <BB#21>
	    Successors according to CFG: BB#21

1472B	BB#14: derived from LLVM BB %if.end.21
	    Predecessors according to CFG: BB#12
1488B		%vreg38<def> = LEA64r <fi#8>, 1, %noreg, 0, %noreg; GR64:%vreg38
1520B		%vreg50<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%source.addr] GR64:%vreg50
1536B		MOV64mr <fi#8>, 1, %noreg, 0, %noreg, %vreg50; mem:ST8[%next_in] GR64:%vreg50
1552B		%vreg48<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%dest.addr] GR64:%vreg48
1568B		MOV64mr <fi#8>, 1, %noreg, 24, %noreg, %vreg48; mem:ST8[%next_out] GR64:%vreg48
1584B		%vreg46<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%sourceLen.addr] GR32:%vreg46
1600B		MOV32mr <fi#8>, 1, %noreg, 8, %noreg, %vreg46; mem:ST4[%avail_in] GR32:%vreg46
1616B		%vreg44<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%destLen.addr] GR64:%vreg44
1632B		%vreg43<def> = MOV32rm %vreg44, 1, %noreg, 0, %noreg; mem:LD4[%18] GR32:%vreg43 GR64:%vreg44
1648B		MOV32mr <fi#8>, 1, %noreg, 32, %noreg, %vreg43; mem:ST4[%avail_out] GR32:%vreg43
1664B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1680B		%RDI<def> = COPY %vreg38; GR64:%vreg38
1696B		%ESI<def> = MOV32ri 2
1712B		CALL64pcrel32 <ga:@BZ2_bzCompress>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %EAX<imp-def>
1728B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1744B		%vreg40<def> = COPY %EAX<kill>; GR32:%vreg40
1760B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1776B		STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#9>, 0, 0, <fi#0>, 0, 0, <fi#8>, 0, ...; mem:LD8[FixedStack2] LD8[FixedStack9](align=4) LD8[FixedStack0](align=4) LD8[FixedStack8]
1792B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1808B		MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %vreg40; mem:ST4[%ret] GR32:%vreg40
1824B		CMP32mi8 <fi#9>, 1, %noreg, 0, %noreg, 3, %EFLAGS<imp-def>; mem:LD4[%ret]
1840B		JNE_1 <BB#16>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#16 BB#15

1856B	BB#15: derived from LLVM BB %if.then.24
	    Predecessors according to CFG: BB#14
1872B		JMP_1 <BB#19>
	    Successors according to CFG: BB#19

1888B	BB#16: derived from LLVM BB %if.end.25
	    Predecessors according to CFG: BB#14
1904B		CMP32mi8 <fi#9>, 1, %noreg, 0, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%ret]
1920B		JE_1 <BB#18>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#18 BB#17

1936B	BB#17: derived from LLVM BB %if.then.27
	    Predecessors according to CFG: BB#16
1952B		JMP_1 <BB#20>
	    Successors according to CFG: BB#20

1968B	BB#18: derived from LLVM BB %if.end.28
	    Predecessors according to CFG: BB#16
1984B		%vreg52<def> = LEA64r <fi#8>, 1, %noreg, 0, %noreg; GR64:%vreg52
2000B		%vreg61<def> = MOV32rm <fi#8>, 1, %noreg, 32, %noreg; mem:LD4[%avail_out29] GR32:%vreg61
2016B		%vreg60<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%destLen.addr] GR64:%vreg60
2032B		%vreg58<def> = MOV32rm %vreg60, 1, %noreg, 0, %noreg; mem:LD4[%23] GR32:%vreg58 GR64:%vreg60
2064B		%vreg58<def,tied1> = SUB32rr %vreg58<tied0>, %vreg61, %EFLAGS<imp-def,dead>; GR32:%vreg58,%vreg61
2080B		MOV32mr %vreg60, 1, %noreg, 0, %noreg, %vreg58; mem:ST4[%23] GR64:%vreg60 GR32:%vreg58
2096B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2112B		%RDI<def> = COPY %vreg52; GR64:%vreg52
2128B		CALL64pcrel32 <ga:@BZ2_bzCompressEnd>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
2144B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2160B		%vreg53<def,dead> = COPY %EAX<kill>; GR32:%vreg53
2176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2192B		STACKMAP 3, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
2208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2224B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
2240B		JMP_1 <BB#21>
	    Successors according to CFG: BB#21

2256B	BB#19: derived from LLVM BB %output_overflow
	    Predecessors according to CFG: BB#15
2272B		%vreg66<def> = LEA64r <fi#8>, 1, %noreg, 0, %noreg; GR64:%vreg66
2288B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2304B		%RDI<def> = COPY %vreg66; GR64:%vreg66
2320B		CALL64pcrel32 <ga:@BZ2_bzCompressEnd>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
2336B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2352B		%vreg67<def,dead> = COPY %EAX<kill>; GR32:%vreg67
2368B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2384B		STACKMAP 4, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
2400B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2416B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -8; mem:ST4[%retval]
2432B		JMP_1 <BB#21>
	    Successors according to CFG: BB#21

2448B	BB#20: derived from LLVM BB %errhandler
	    Predecessors according to CFG: BB#17
2464B		%vreg64<def> = LEA64r <fi#8>, 1, %noreg, 0, %noreg; GR64:%vreg64
2480B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2496B		%RDI<def> = COPY %vreg64; GR64:%vreg64
2512B		CALL64pcrel32 <ga:@BZ2_bzCompressEnd>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
2528B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2544B		%vreg65<def,dead> = COPY %EAX<kill>; GR32:%vreg65
2560B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2576B		STACKMAP 5, 0, 0, <fi#9>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack9](align=4) LD8[FixedStack0](align=4)
2592B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2608B		%vreg63<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%ret] GR32:%vreg63
2624B		MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %vreg63; mem:ST4[%retval] GR32:%vreg63
	    Successors according to CFG: BB#21

2640B	BB#21: derived from LLVM BB %return
	    Predecessors according to CFG: BB#18 BB#20 BB#19 BB#13 BB#9
2656B		%vreg73<def> = MOV64ri <ga:@BZ2_bzBuffToBuffCompress>; GR64:%vreg73
2688B		%vreg74<def> = MOV64rm <fi#-2>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-2] GR64:%vreg74
2704B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2720B		%RDI<def> = COPY %vreg73; GR64:%vreg73
2736B		%RSI<def> = COPY %vreg74; GR64:%vreg74
2752B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
2768B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2784B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2800B		STACKMAP 6, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
2816B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2832B		%vreg71<def> = MOV32rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD4[%retval] GR32:%vreg71
2848B		%EAX<def> = COPY %vreg71; GR32:%vreg71
2864B		RETQ %EAX<imp-use,kill>

# End machine code for function BZ2_bzBuffToBuffCompress.

AllocationOrder(SEGMENT_REG) = [ ]
AllocationOrder(SEGMENT_REG) = [ ]
handleMove 1680B -> 1704B: %RDI<def> = COPY %vreg38; GR64:%vreg38
     DIL:	[0B,96r:0)[288r,320r:7)[1200r,1264r:6)[1680r,1712r:5)[2112r,2128r:4)[2304r,2320r:2)[2496r,2512r:3)[2720r,2752r:1)  0@0B-phi 1@2720r 2@2304r 3@2496r 4@2112r 5@1680r 6@1200r 7@288r
        -->	[0B,96r:0)[288r,320r:7)[1200r,1264r:6)[1704r,1712r:5)[2112r,2128r:4)[2304r,2320r:2)[2496r,2512r:3)[2720r,2752r:1)  0@0B-phi 1@2720r 2@2304r 3@2496r 4@2112r 5@1704r 6@1200r 7@288r
     %vreg38:	[1488r,1680r:0)  0@1488r
        -->	[1488r,1704r:0)  0@1488r
AllocationOrder(SEGMENT_REG) = [ ]
********** GREEDY REGISTER ALLOCATION **********
********** Function: BZ2_bzBuffToBuffCompress
********** INTERVALS **********
CH [0B,48r:0)[1248r,1264r:1)  0@0B-phi 1@1248r
CL [0B,48r:0)[1248r,1264r:1)  0@0B-phi 1@1248r
DH [0B,64r:0)[1232r,1264r:1)  0@0B-phi 1@1232r
DIL [0B,96r:0)[288r,320r:7)[1200r,1264r:6)[1704r,1712r:5)[2112r,2128r:4)[2304r,2320r:2)[2496r,2512r:3)[2720r,2752r:1)  0@0B-phi 1@2720r 2@2304r 3@2496r 4@2112r 5@1704r 6@1200r 7@288r
DL [0B,64r:0)[1232r,1264r:1)  0@0B-phi 1@1232r
SIL [0B,80r:0)[304r,320r:4)[1216r,1264r:2)[1696r,1712r:1)[2736r,2752r:3)  0@0B-phi 1@1696r 2@1216r 3@2736r 4@304r
R8B [0B,32r:0)  0@0B-phi
R9B [0B,16r:0)  0@0B-phi
%vreg6 [96r,400r:0)  0@96r
%vreg7 [80r,416r:0)  0@80r
%vreg8 [64r,432r:0)  0@64r
%vreg9 [48r,448r:0)  0@48r
%vreg10 [32r,464r:0)  0@32r
%vreg11 [16r,480r:0)  0@16r
%vreg12 [112r,496r:0)  0@112r
%vreg15 [224r,288r:0)  0@224r
%vreg16 [256r,304r:0)  0@256r
%vreg28 [1072r,1200r:0)  0@1072r
%vreg32 [1296r,1360r:0)  0@1296r
%vreg33 [1168r,1248r:0)  0@1168r
%vreg34 [1152r,1232r:0)  0@1152r
%vreg35 [1136r,1216r:0)  0@1136r
%vreg38 [1488r,1704r:0)  0@1488r
%vreg40 [1744r,1808r:0)  0@1744r
%vreg43 [1632r,1648r:0)  0@1632r
%vreg44 [1616r,1632r:0)  0@1616r
%vreg46 [1584r,1600r:0)  0@1584r
%vreg48 [1552r,1568r:0)  0@1552r
%vreg50 [1520r,1536r:0)  0@1520r
%vreg52 [1984r,2112r:0)  0@1984r
%vreg53 [2160r,2160d:0)  0@2160r
%vreg58 [2032r,2064r:0)[2064r,2080r:1)  0@2032r 1@2064r
%vreg60 [2016r,2080r:0)  0@2016r
%vreg61 [2000r,2064r:0)  0@2000r
%vreg63 [2608r,2624r:0)  0@2608r
%vreg64 [2464r,2496r:0)  0@2464r
%vreg65 [2544r,2544d:0)  0@2544r
%vreg66 [2272r,2304r:0)  0@2272r
%vreg67 [2352r,2352d:0)  0@2352r
%vreg69 [1424r,1440r:0)  0@1424r
%vreg71 [2832r,2848r:0)  0@2832r
%vreg73 [2656r,2720r:0)  0@2656r
%vreg74 [2688r,2736r:0)  0@2688r
RegMasks: 320r 1264r 1712r 2128r 2320r 2512r 2752r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzBuffToBuffCompress: Post SSA
Frame Objects:
  fi#-2: size=8, align=8, fixed, at location [SP]
  fi#-1: size=4, align=16, fixed, at location [SP+8]
  fi#0: size=4, align=4, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=8, align=8, at location [SP+8]
  fi#3: size=8, align=8, at location [SP+8]
  fi#4: size=4, align=4, at location [SP+8]
  fi#5: size=4, align=4, at location [SP+8]
  fi#6: size=4, align=4, at location [SP+8]
  fi#7: size=4, align=4, at location [SP+8]
  fi#8: size=80, align=8, at location [SP+8]
  fi#9: size=4, align=4, at location [SP+8]
Function Live Ins: %RDI in %vreg0, %RSI in %vreg1, %RDX in %vreg2, %ECX in %vreg3, %R8D in %vreg4, %R9D in %vreg5

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI %RSI %RDX %ECX %R8D %R9D
16B		%vreg11<def> = COPY %R9D; GR32:%vreg11
32B		%vreg10<def> = COPY %R8D; GR32:%vreg10
48B		%vreg9<def> = COPY %ECX; GR32:%vreg9
64B		%vreg8<def> = COPY %RDX; GR64:%vreg8
80B		%vreg7<def> = COPY %RSI; GR64:%vreg7
96B		%vreg6<def> = COPY %RDI; GR64:%vreg6
112B		%vreg12<def> = MOV32rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD4[FixedStack-1] GR32:%vreg12
224B		%vreg15<def> = MOV64ri <ga:@BZ2_bzBuffToBuffCompress>; GR64:%vreg15
256B		%vreg16<def> = MOV64rm <fi#-2>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-2] GR64:%vreg16
272B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
288B		%RDI<def> = COPY %vreg15; GR64:%vreg15
304B		%RSI<def> = COPY %vreg16; GR64:%vreg16
320B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
336B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
352B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
368B		STACKMAP 0, 0, %vreg10, 0, <fi#5>, 0, %vreg6, 0, <fi#1>, 0, %vreg7, 0, <fi#2>, 0, 0, <fi#9>, 0, 0, <fi#0>, 0, %vreg8, 0, <fi#3>, 0, %vreg9, 0, <fi#4>, 0, 0, <fi#8>, 0, %vreg11, 0, <fi#6>, 0, %vreg12, 0, <fi#7>, 0, ...; mem:LD8[FixedStack5](align=4) LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack9](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3] LD8[FixedStack4](align=4) LD8[FixedStack8] LD8[FixedStack6](align=4) LD8[FixedStack7](align=4) GR32:%vreg10,%vreg9,%vreg11,%vreg12 GR64:%vreg6,%vreg7,%vreg8
384B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
400B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg6; mem:ST8[%dest.addr] GR64:%vreg6
416B		MOV64mr <fi#2>, 1, %noreg, 0, %noreg, %vreg7; mem:ST8[%destLen.addr] GR64:%vreg7
432B		MOV64mr <fi#3>, 1, %noreg, 0, %noreg, %vreg8; mem:ST8[%source.addr] GR64:%vreg8
448B		MOV32mr <fi#4>, 1, %noreg, 0, %noreg, %vreg9; mem:ST4[%sourceLen.addr] GR32:%vreg9
464B		MOV32mr <fi#5>, 1, %noreg, 0, %noreg, %vreg10; mem:ST4[%blockSize100k.addr] GR32:%vreg10
480B		MOV32mr <fi#6>, 1, %noreg, 0, %noreg, %vreg11; mem:ST4[%verbosity.addr] GR32:%vreg11
496B		MOV32mr <fi#7>, 1, %noreg, 0, %noreg, %vreg12; mem:ST4[%workFactor.addr] GR32:%vreg12
512B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%dest.addr]
528B		JE_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#1

544B	BB#1: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#0
560B		CMP64mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%destLen.addr]
576B		JE_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#2

592B	BB#2: derived from LLVM BB %lor.lhs.false.2
	    Predecessors according to CFG: BB#1
608B		CMP64mi8 <fi#3>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%source.addr]
624B		JE_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#3

640B	BB#3: derived from LLVM BB %lor.lhs.false.4
	    Predecessors according to CFG: BB#2
656B		CMP32mi8 <fi#5>, 1, %noreg, 0, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%blockSize100k.addr]
672B		JL_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#4

688B	BB#4: derived from LLVM BB %lor.lhs.false.6
	    Predecessors according to CFG: BB#3
704B		CMP32mi8 <fi#5>, 1, %noreg, 0, %noreg, 9, %EFLAGS<imp-def>; mem:LD4[%blockSize100k.addr]
720B		JG_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#5

736B	BB#5: derived from LLVM BB %lor.lhs.false.8
	    Predecessors according to CFG: BB#4
752B		CMP32mi8 <fi#6>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%verbosity.addr]
768B		JL_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#6

784B	BB#6: derived from LLVM BB %lor.lhs.false.10
	    Predecessors according to CFG: BB#5
800B		CMP32mi8 <fi#6>, 1, %noreg, 0, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%verbosity.addr]
816B		JG_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#7

832B	BB#7: derived from LLVM BB %lor.lhs.false.12
	    Predecessors according to CFG: BB#6
848B		CMP32mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%workFactor.addr]
864B		JL_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#8

880B	BB#8: derived from LLVM BB %lor.lhs.false.14
	    Predecessors according to CFG: BB#7
896B		CMP32mi <fi#7>, 1, %noreg, 0, %noreg, 250, %EFLAGS<imp-def>; mem:LD4[%workFactor.addr]
912B		JLE_1 <BB#10>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#10 BB#9

928B	BB#9: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0 BB#1 BB#2 BB#3 BB#4 BB#5 BB#6 BB#7 BB#8
944B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
960B		JMP_1 <BB#21>
	    Successors according to CFG: BB#21

976B	BB#10: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#8
992B		CMP32mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%workFactor.addr]
1008B		JNE_1 <BB#12>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#12 BB#11

1024B	BB#11: derived from LLVM BB %if.then.17
	    Predecessors according to CFG: BB#10
1040B		MOV32mi <fi#7>, 1, %noreg, 0, %noreg, 30; mem:ST4[%workFactor.addr]
	    Successors according to CFG: BB#12

1056B	BB#12: derived from LLVM BB %if.end.18
	    Predecessors according to CFG: BB#10 BB#11
1072B		%vreg28<def> = LEA64r <fi#8>, 1, %noreg, 0, %noreg; GR64:%vreg28
1088B		MOV64mi32 <fi#8>, 1, %noreg, 56, %noreg, 0; mem:ST8[%bzalloc]
1104B		MOV64mi32 <fi#8>, 1, %noreg, 64, %noreg, 0; mem:ST8[%bzfree]
1120B		MOV64mi32 <fi#8>, 1, %noreg, 72, %noreg, 0; mem:ST8[%opaque]
1136B		%vreg35<def> = MOV32rm <fi#5>, 1, %noreg, 0, %noreg; mem:LD4[%blockSize100k.addr] GR32:%vreg35
1152B		%vreg34<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%verbosity.addr] GR32:%vreg34
1168B		%vreg33<def> = MOV32rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD4[%workFactor.addr] GR32:%vreg33
1184B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1200B		%RDI<def> = COPY %vreg28; GR64:%vreg28
1216B		%ESI<def> = COPY %vreg35; GR32:%vreg35
1232B		%EDX<def> = COPY %vreg34; GR32:%vreg34
1248B		%ECX<def> = COPY %vreg33; GR32:%vreg33
1264B		CALL64pcrel32 <ga:@BZ2_bzCompressInit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %EDX<imp-use>, %ECX<imp-use>, %EAX<imp-def>
1280B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1296B		%vreg32<def> = COPY %EAX<kill>; GR32:%vreg32
1312B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1328B		STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#9>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, 0, <fi#8>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack9](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3] LD8[FixedStack4](align=4) LD8[FixedStack8]
1344B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1360B		MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %vreg32; mem:ST4[%ret] GR32:%vreg32
1376B		CMP32mi8 <fi#9>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%ret]
1392B		JE_1 <BB#14>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#14 BB#13

1408B	BB#13: derived from LLVM BB %if.then.20
	    Predecessors according to CFG: BB#12
1424B		%vreg69<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%ret] GR32:%vreg69
1440B		MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %vreg69; mem:ST4[%retval] GR32:%vreg69
1456B		JMP_1 <BB#21>
	    Successors according to CFG: BB#21

1472B	BB#14: derived from LLVM BB %if.end.21
	    Predecessors according to CFG: BB#12
1488B		%vreg38<def> = LEA64r <fi#8>, 1, %noreg, 0, %noreg; GR64:%vreg38
1520B		%vreg50<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%source.addr] GR64:%vreg50
1536B		MOV64mr <fi#8>, 1, %noreg, 0, %noreg, %vreg50; mem:ST8[%next_in] GR64:%vreg50
1552B		%vreg48<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%dest.addr] GR64:%vreg48
1568B		MOV64mr <fi#8>, 1, %noreg, 24, %noreg, %vreg48; mem:ST8[%next_out] GR64:%vreg48
1584B		%vreg46<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%sourceLen.addr] GR32:%vreg46
1600B		MOV32mr <fi#8>, 1, %noreg, 8, %noreg, %vreg46; mem:ST4[%avail_in] GR32:%vreg46
1616B		%vreg44<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%destLen.addr] GR64:%vreg44
1632B		%vreg43<def> = MOV32rm %vreg44, 1, %noreg, 0, %noreg; mem:LD4[%18] GR32:%vreg43 GR64:%vreg44
1648B		MOV32mr <fi#8>, 1, %noreg, 32, %noreg, %vreg43; mem:ST4[%avail_out] GR32:%vreg43
1664B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1696B		%ESI<def> = MOV32ri 2
1704B		%RDI<def> = COPY %vreg38; GR64:%vreg38
1712B		CALL64pcrel32 <ga:@BZ2_bzCompress>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %EAX<imp-def>
1728B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1744B		%vreg40<def> = COPY %EAX<kill>; GR32:%vreg40
1760B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1776B		STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#9>, 0, 0, <fi#0>, 0, 0, <fi#8>, 0, ...; mem:LD8[FixedStack2] LD8[FixedStack9](align=4) LD8[FixedStack0](align=4) LD8[FixedStack8]
1792B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1808B		MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %vreg40; mem:ST4[%ret] GR32:%vreg40
1824B		CMP32mi8 <fi#9>, 1, %noreg, 0, %noreg, 3, %EFLAGS<imp-def>; mem:LD4[%ret]
1840B		JNE_1 <BB#16>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#16 BB#15

1856B	BB#15: derived from LLVM BB %if.then.24
	    Predecessors according to CFG: BB#14
1872B		JMP_1 <BB#19>
	    Successors according to CFG: BB#19

1888B	BB#16: derived from LLVM BB %if.end.25
	    Predecessors according to CFG: BB#14
1904B		CMP32mi8 <fi#9>, 1, %noreg, 0, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%ret]
1920B		JE_1 <BB#18>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#18 BB#17

1936B	BB#17: derived from LLVM BB %if.then.27
	    Predecessors according to CFG: BB#16
1952B		JMP_1 <BB#20>
	    Successors according to CFG: BB#20

1968B	BB#18: derived from LLVM BB %if.end.28
	    Predecessors according to CFG: BB#16
1984B		%vreg52<def> = LEA64r <fi#8>, 1, %noreg, 0, %noreg; GR64:%vreg52
2000B		%vreg61<def> = MOV32rm <fi#8>, 1, %noreg, 32, %noreg; mem:LD4[%avail_out29] GR32:%vreg61
2016B		%vreg60<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%destLen.addr] GR64:%vreg60
2032B		%vreg58<def> = MOV32rm %vreg60, 1, %noreg, 0, %noreg; mem:LD4[%23] GR32:%vreg58 GR64:%vreg60
2064B		%vreg58<def,tied1> = SUB32rr %vreg58<tied0>, %vreg61, %EFLAGS<imp-def,dead>; GR32:%vreg58,%vreg61
2080B		MOV32mr %vreg60, 1, %noreg, 0, %noreg, %vreg58; mem:ST4[%23] GR64:%vreg60 GR32:%vreg58
2096B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2112B		%RDI<def> = COPY %vreg52; GR64:%vreg52
2128B		CALL64pcrel32 <ga:@BZ2_bzCompressEnd>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
2144B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2160B		%vreg53<def,dead> = COPY %EAX<kill>; GR32:%vreg53
2176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2192B		STACKMAP 3, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
2208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2224B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
2240B		JMP_1 <BB#21>
	    Successors according to CFG: BB#21

2256B	BB#19: derived from LLVM BB %output_overflow
	    Predecessors according to CFG: BB#15
2272B		%vreg66<def> = LEA64r <fi#8>, 1, %noreg, 0, %noreg; GR64:%vreg66
2288B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2304B		%RDI<def> = COPY %vreg66; GR64:%vreg66
2320B		CALL64pcrel32 <ga:@BZ2_bzCompressEnd>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
2336B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2352B		%vreg67<def,dead> = COPY %EAX<kill>; GR32:%vreg67
2368B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2384B		STACKMAP 4, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
2400B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2416B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -8; mem:ST4[%retval]
2432B		JMP_1 <BB#21>
	    Successors according to CFG: BB#21

2448B	BB#20: derived from LLVM BB %errhandler
	    Predecessors according to CFG: BB#17
2464B		%vreg64<def> = LEA64r <fi#8>, 1, %noreg, 0, %noreg; GR64:%vreg64
2480B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2496B		%RDI<def> = COPY %vreg64; GR64:%vreg64
2512B		CALL64pcrel32 <ga:@BZ2_bzCompressEnd>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
2528B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2544B		%vreg65<def,dead> = COPY %EAX<kill>; GR32:%vreg65
2560B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2576B		STACKMAP 5, 0, 0, <fi#9>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack9](align=4) LD8[FixedStack0](align=4)
2592B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2608B		%vreg63<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%ret] GR32:%vreg63
2624B		MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %vreg63; mem:ST4[%retval] GR32:%vreg63
	    Successors according to CFG: BB#21

2640B	BB#21: derived from LLVM BB %return
	    Predecessors according to CFG: BB#18 BB#20 BB#19 BB#13 BB#9
2656B		%vreg73<def> = MOV64ri <ga:@BZ2_bzBuffToBuffCompress>; GR64:%vreg73
2688B		%vreg74<def> = MOV64rm <fi#-2>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-2] GR64:%vreg74
2704B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2720B		%RDI<def> = COPY %vreg73; GR64:%vreg73
2736B		%RSI<def> = COPY %vreg74; GR64:%vreg74
2752B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
2768B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2784B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2800B		STACKMAP 6, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
2816B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2832B		%vreg71<def> = MOV32rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD4[%retval] GR32:%vreg71
2848B		%EAX<def> = COPY %vreg71; GR32:%vreg71
2864B		RETQ %EAX<imp-use,kill>

# End machine code for function BZ2_bzBuffToBuffCompress.


selectOrSplit GR32:%vreg11 [16r,480r:0)  0@16r w=3.506945e-03
hints: %R9D
missed hint %R9D
assigning %vreg11 to %EBX: BH [16r,480r:0)  0@16r BL [16r,480r:0)  0@16r

selectOrSplit GR32:%vreg10 [32r,464r:0)  0@32r w=3.641827e-03
hints: %R8D
missed hint %R8D
%R14D is available at cost 1
Only trying the first 10 regs.
should evict: %vreg11 [16r,480r:0)  0@16r w= 3.506945e-03
hints: %R9D
can reassign: %vreg11 [16r,480r:0)  0@16r from %EBX to %R9D
should evict: %vreg11 [16r,480r:0)  0@16r w= 3.506945e-03
hints: %R9D
can reassign: %vreg11 [16r,480r:0)  0@16r from %EBX to %R9D
evicting %EBX interference: Cascade 1
unassigning %vreg11 from %EBX: BH BL
assigning %vreg10 to %EBX: BH [32r,464r:0)  0@32r BL [32r,464r:0)  0@32r
queuing new interval: %vreg11 [16r,480r:0)  0@16r

selectOrSplit GR32:%vreg11 [16r,480r:0)  0@16r w=3.506945e-03
hints: %R9D
missed hint %R9D
%R14D is available at cost 1
Only trying the first 10 regs.
assigning %vreg11 to %R14D: R14B [16r,480r:0)  0@16r

selectOrSplit GR32:%vreg9 [48r,448r:0)  0@48r w=3.787500e-03
hints: %ECX
missed hint %ECX
%R15D is available at cost 1
Only trying the first 10 regs.
should evict: %vreg10 [32r,464r:0)  0@32r w= 3.641827e-03
hints: %R8D
can reassign: %vreg10 [32r,464r:0)  0@32r from %EBX to %R8D
should evict: %vreg10 [32r,464r:0)  0@32r w= 3.641827e-03
hints: %R8D
can reassign: %vreg10 [32r,464r:0)  0@32r from %EBX to %R8D
evicting %EBX interference: Cascade 2
unassigning %vreg10 from %EBX: BH BL
assigning %vreg9 to %EBX: BH [48r,448r:0)  0@48r BL [48r,448r:0)  0@48r
queuing new interval: %vreg10 [32r,464r:0)  0@32r

selectOrSplit GR32:%vreg10 [32r,464r:0)  0@32r w=3.641827e-03
hints: %R8D
missed hint %R8D
%R15D is available at cost 1
Only trying the first 10 regs.
assigning %vreg10 to %R15D: R15B [32r,464r:0)  0@32r

selectOrSplit GR64:%vreg8 [64r,432r:0)  0@64r w=3.945312e-03
hints: %RDX
missed hint %RDX
%R12 is available at cost 1
Only trying the first 10 regs.
should evict: %vreg9 [48r,448r:0)  0@48r w= 3.787500e-03
hints: %ECX
can reassign: %vreg9 [48r,448r:0)  0@48r from %RBX to %ECX
should evict: %vreg9 [48r,448r:0)  0@48r w= 3.787500e-03
hints: %ECX
can reassign: %vreg9 [48r,448r:0)  0@48r from %RBX to %ECX
evicting %RBX interference: Cascade 3
unassigning %vreg9 from %EBX: BH BL
assigning %vreg8 to %RBX: BH [64r,432r:0)  0@64r BL [64r,432r:0)  0@64r
queuing new interval: %vreg9 [48r,448r:0)  0@48r

selectOrSplit GR32:%vreg9 [48r,448r:0)  0@48r w=3.787500e-03
hints: %ECX
missed hint %ECX
%R12D is available at cost 1
Only trying the first 10 regs.
assigning %vreg9 to %R12D: R12B [48r,448r:0)  0@48r

selectOrSplit GR64:%vreg7 [80r,416r:0)  0@80r w=4.116848e-03
hints: %RSI
missed hint %RSI
%R13 is available at cost 1
Only trying the first 10 regs.
should evict: %vreg8 [64r,432r:0)  0@64r w= 3.945312e-03
hints: %RDX
can reassign: %vreg8 [64r,432r:0)  0@64r from %RBX to %RDX
should evict: %vreg8 [64r,432r:0)  0@64r w= 3.945312e-03
hints: %RDX
can reassign: %vreg8 [64r,432r:0)  0@64r from %RBX to %RDX
evicting %RBX interference: Cascade 4
unassigning %vreg8 from %RBX: BH BL
assigning %vreg7 to %RBX: BH [80r,416r:0)  0@80r BL [80r,416r:0)  0@80r
queuing new interval: %vreg8 [64r,432r:0)  0@64r

selectOrSplit GR64:%vreg8 [64r,432r:0)  0@64r w=3.945312e-03
hints: %RDX
missed hint %RDX
%R13 is available at cost 1
Only trying the first 10 regs.
assigning %vreg8 to %R13: R13B [64r,432r:0)  0@64r

selectOrSplit GR64:%vreg6 [96r,400r:0)  0@96r w=4.303977e-03
hints: %RDI
RS_Assign Cascade 0
should evict: %vreg7 [80r,416r:0)  0@80r w= 4.116848e-03
should evict: %vreg7 [80r,416r:0)  0@80r w= 4.116848e-03
should evict: %vreg11 [16r,480r:0)  0@16r w= 3.506945e-03
hints: %R9D
can reassign: %vreg11 [16r,480r:0)  0@16r from %R14 to %R9D
evicting %R14 interference: Cascade 5
unassigning %vreg11 from %R14D: R14B
assigning %vreg6 to %R14: R14B [96r,400r:0)  0@96r
queuing new interval: %vreg11 [16r,480r:0)  0@16r

selectOrSplit GR32:%vreg11 [16r,480r:0)  0@16r w=3.506945e-03
hints: %R9D
RS_Assign Cascade 5
wait for second round
queuing new interval: %vreg11 [16r,480r:0)  0@16r

selectOrSplit GR64:%vreg15 [224r,288r:0)  0@224r w=2.176724e-03
hints: %RDI
assigning %vreg15 to %RDI: DIL [224r,288r:0)  0@224r

selectOrSplit GR64:%vreg16 [256r,304r:0)  0@256r w=4.508928e-03
hints: %RSI
assigning %vreg16 to %RSI: SIL [256r,304r:0)  0@256r

selectOrSplit GR64:%vreg28 [1072r,1200r:0)  0@1072r w=3.677827e-06
hints: %RDI
assigning %vreg28 to %RDI: DIL [1072r,1200r:0)  0@1072r

selectOrSplit GR32:%vreg35 [1136r,1216r:0)  0@1136r w=8.091220e-06
hints: %ESI
assigning %vreg35 to %ESI: SIL [1136r,1216r:0)  0@1136r

selectOrSplit GR32:%vreg34 [1152r,1232r:0)  0@1152r w=8.091220e-06
hints: %EDX
assigning %vreg34 to %EDX: DH [1152r,1232r:0)  0@1152r DL [1152r,1232r:0)  0@1152r

selectOrSplit GR32:%vreg33 [1168r,1248r:0)  0@1168r w=8.091220e-06
hints: %ECX
assigning %vreg33 to %ECX: CH [1168r,1248r:0)  0@1168r CL [1168r,1248r:0)  0@1168r

selectOrSplit GR32:%vreg32 [1296r,1360r:0)  0@1296r w=8.370227e-06
hints: %EAX
assigning %vreg32 to %EAX: AH [1296r,1360r:0)  0@1296r AL [1296r,1360r:0)  0@1296r

selectOrSplit GR64:%vreg38 [1488r,1704r:0)  0@1488r w=1.551192e-06
hints: %RDI
assigning %vreg38 to %RDI: DIL [1488r,1704r:0)  0@1488r

selectOrSplit GR32:%vreg40 [1744r,1808r:0)  0@1744r w=4.118683e-06
hints: %EAX
assigning %vreg40 to %EAX: AH [1744r,1808r:0)  0@1744r AL [1744r,1808r:0)  0@1744r

selectOrSplit GR64:%vreg52 [1984r,2112r:0)  0@1984r w=4.670257e-07
hints: %RDI
assigning %vreg52 to %RDI: DIL [1984r,2112r:0)  0@1984r

selectOrSplit GR32:%vreg53 [2160r,2160d:0)  0@2160r w=inf
hints: %EAX
assigning %vreg53 to %EAX: AH [2160r,2160d:0)  0@2160r AL [2160r,2160d:0)  0@2160r

selectOrSplit GR64:%vreg66 [2272r,2304r:0)  0@2272r w=1.070267e-06
hints: %RDI
assigning %vreg66 to %RDI: DIL [2272r,2304r:0)  0@2272r

selectOrSplit GR32:%vreg67 [2352r,2352d:0)  0@2352r w=inf
hints: %EAX
assigning %vreg67 to %EAX: AH [2352r,2352d:0)  0@2352r AL [2352r,2352d:0)  0@2352r

selectOrSplit GR64:%vreg64 [2464r,2496r:0)  0@2464r w=5.708092e-07
hints: %RDI
assigning %vreg64 to %RDI: DIL [2464r,2496r:0)  0@2464r

selectOrSplit GR32:%vreg65 [2544r,2544d:0)  0@2544r w=inf
hints: %EAX
assigning %vreg65 to %EAX: AH [2544r,2544d:0)  0@2544r AL [2544r,2544d:0)  0@2544r

selectOrSplit GR64:%vreg73 [2656r,2720r:0)  0@2656r w=2.176724e-03
hints: %RDI
assigning %vreg73 to %RDI: DIL [2656r,2720r:0)  0@2656r

selectOrSplit GR64:%vreg74 [2688r,2736r:0)  0@2688r w=4.508928e-03
hints: %RSI
assigning %vreg74 to %RSI: SIL [2688r,2736r:0)  0@2688r

selectOrSplit GR32:%vreg71 [2832r,2848r:0)  0@2832r w=inf
hints: %EAX
assigning %vreg71 to %EAX: AH [2832r,2848r:0)  0@2832r AL [2832r,2848r:0)  0@2832r

selectOrSplit GR32:%vreg12 [112r,496r:0)  0@112r w=1.913265e-03
RS_Assign Cascade 0
wait for second round
queuing new interval: %vreg12 [112r,496r:0)  0@112r

selectOrSplit GR32:%vreg69 [1424r,1440r:0)  0@1424r w=inf
assigning %vreg69 to %EAX: AH [1424r,1440r:0)  0@1424r AL [1424r,1440r:0)  0@1424r

selectOrSplit GR64:%vreg50 [1520r,1536r:0)  0@1520r w=inf
assigning %vreg50 to %RAX: AH [1520r,1536r:0)  0@1520r AL [1520r,1536r:0)  0@1520r

selectOrSplit GR64:%vreg48 [1552r,1568r:0)  0@1552r w=inf
assigning %vreg48 to %RAX: AH [1552r,1568r:0)  0@1552r AL [1552r,1568r:0)  0@1552r

selectOrSplit GR32:%vreg46 [1584r,1600r:0)  0@1584r w=inf
assigning %vreg46 to %EAX: AH [1584r,1600r:0)  0@1584r AL [1584r,1600r:0)  0@1584r

selectOrSplit GR64:%vreg44 [1616r,1632r:0)  0@1616r w=inf
assigning %vreg44 to %RAX: AH [1616r,1632r:0)  0@1616r AL [1616r,1632r:0)  0@1616r

selectOrSplit GR32:%vreg43 [1632r,1648r:0)  0@1632r w=inf
assigning %vreg43 to %EAX: AH [1632r,1648r:0)  0@1632r AL [1632r,1648r:0)  0@1632r

selectOrSplit GR32:%vreg61 [2000r,2064r:0)  0@2000r w=1.052362e-06
assigning %vreg61 to %EAX: AH [2000r,2064r:0)  0@2000r AL [2000r,2064r:0)  0@2000r

selectOrSplit GR64:%vreg60 [2016r,2080r:0)  0@2016r w=1.578544e-06
assigning %vreg60 to %RCX: CH [2016r,2080r:0)  0@2016r CL [2016r,2080r:0)  0@2016r

selectOrSplit GR32:%vreg58 [2032r,2064r:0)[2064r,2080r:1)  0@2032r 1@2064r w=inf
assigning %vreg58 to %EDX: DH [2032r,2064r:0)[2064r,2080r:1)  0@2032r 1@2064r DL [2032r,2064r:0)[2064r,2080r:1)  0@2032r 1@2064r

selectOrSplit GR32:%vreg63 [2608r,2624r:0)  0@2608r w=inf
assigning %vreg63 to %EAX: AH [2608r,2624r:0)  0@2608r AL [2608r,2624r:0)  0@2608r

selectOrSplit GR32:%vreg11 [16r,480r:0)  0@16r w=3.506945e-03
hints: %R9D
RS_Split Cascade 5
Analyze counted 3 instrs in 1 blocks, through 0 blocks.
tryLocalSplit:  16r 368r 480r
1 regmasks in block: 320r:16r-368r
%R9D 16r-368r i=inf extend
%R9D 368r-480r i=0.000000e+00 w=5.681818e-03 (best) end
%EAX 16r-368r i=inf extend
%EAX 368r-480r i=0.000000e+00 w=5.681818e-03 (best) end
%ECX 16r-368r i=inf extend
%ECX 368r-480r i=0.000000e+00 w=5.681818e-03 (best) end
%EDX 16r-368r i=inf extend
%EDX 368r-480r i=0.000000e+00 w=5.681818e-03 (best) end
%ESI 16r-368r i=inf extend
%ESI 368r-480r i=0.000000e+00 w=5.681818e-03 (best) end
%EDI 16r-368r i=inf extend
%EDI 368r-480r i=0.000000e+00 w=5.681818e-03 (best) end
%R8D 16r-368r i=inf extend
%R8D 368r-480r i=0.000000e+00 w=5.681818e-03 (best) end
%R10D 16r-368r i=inf extend
%R10D 368r-480r i=0.000000e+00 w=5.681818e-03 (best) end
%R11D 16r-368r i=inf extend
%R11D 368r-480r i=inf end
%EBX 16r-368r i=4.116848e-03 w=3.906250e-03 extend
%EBX 368r-480r i=4.116848e-03 w=5.681818e-03 end
%R14D 16r-368r i=4.303977e-03 w=3.906250e-03 extend
%R14D 368r-480r i=4.303977e-03 w=5.681818e-03 end
%R15D 16r-368r i=3.641827e-03 w=3.906250e-03 extend
%R15D 16r-480r i=3.641827e-03 all
%R12D 16r-368r i=3.787500e-03 w=3.906250e-03 extend
%R12D 16r-480r i=3.787500e-03 all
%R13D 16r-368r i=3.945312e-03 w=3.906250e-03 extend
%R13D 368r-480r i=3.945312e-03 w=5.681818e-03 end
Best local split range: 368r-480r, 5.568071e-03, 2 instrs
    enterIntvBefore 368r: valno 0
    leaveIntvAfter 480r: not live
    useIntv [360r;496B): [360r;496B):1
  blit [16r,480r:0): [16r;360r)=0:0 [360r;480r)=1:0
  rewr BB#0	16r:0	%vreg75<def> = COPY %R9D; GR32:%vreg75
  rewr BB#0	480B:1	MOV32mr <fi#6>, 1, %noreg, 0, %noreg, %vreg76; mem:ST4[%verbosity.addr] GR32:%vreg76
  rewr BB#0	368B:1	STACKMAP 0, 0, %vreg10, 0, <fi#5>, 0, %vreg6, 0, <fi#1>, 0, %vreg7, 0, <fi#2>, 0, 0, <fi#9>, 0, 0, <fi#0>, 0, %vreg8, 0, <fi#3>, 0, %vreg9, 0, <fi#4>, 0, 0, <fi#8>, 0, %vreg76, 0, <fi#6>, 0, %vreg12, 0, <fi#7>, 0, ...; mem:LD8[FixedStack5](align=4) LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack9](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3] LD8[FixedStack4](align=4) LD8[FixedStack8] LD8[FixedStack6](align=4) LD8[FixedStack7](align=4) GR32:%vreg10,%vreg9,%vreg76,%vreg12 GR64:%vreg6,%vreg7,%vreg8
  rewr BB#0	360B:0	%vreg76<def> = COPY %vreg75; GR32:%vreg76,%vreg75
Tagging non-progress ranges: %vreg76
queuing new interval: %vreg75 [16r,360r:0)  0@16r
queuing new interval: %vreg76 [360r,480r:0)  0@360r

selectOrSplit GR32:%vreg75 [16r,360r:0)  0@16r w=2.715054e-03
hints: %R9D
RS_Assign Cascade 0
wait for second round
queuing new interval: %vreg75 [16r,360r:0)  0@16r

selectOrSplit GR32:%vreg76 [360r,480r:0)  0@360r w=5.826923e-03
assigning %vreg76 to %EAX: AH [360r,480r:0)  0@360r AL [360r,480r:0)  0@360r

selectOrSplit GR32:%vreg12 [112r,496r:0)  0@112r w=1.913265e-03
RS_Split Cascade 0
Analyze counted 3 instrs in 1 blocks, through 0 blocks.
tryLocalSplit:  112r 368r 496r
1 regmasks in block: 320r:112r-368r
%EAX 112r-368r i=inf extend
%EAX 368r-496r i=5.826923e-03 w=5.514706e-03 end
%ECX 112r-368r i=inf extend
%ECX 368r-496r i=0.000000e+00 w=5.514706e-03 (best) end
%EDX 112r-368r i=inf extend
%EDX 368r-496r i=0.000000e+00 w=5.514706e-03 (best) end
%ESI 112r-368r i=inf extend
%ESI 368r-496r i=0.000000e+00 w=5.514706e-03 (best) end
%EDI 112r-368r i=inf extend
%EDI 368r-496r i=0.000000e+00 w=5.514706e-03 (best) end
%R8D 112r-368r i=inf extend
%R8D 368r-496r i=0.000000e+00 w=5.514706e-03 (best) end
%R9D 112r-368r i=inf extend
%R9D 368r-496r i=0.000000e+00 w=5.514706e-03 (best) end
%R10D 112r-368r i=inf extend
%R10D 368r-496r i=0.000000e+00 w=5.514706e-03 (best) end
%R11D 112r-368r i=inf extend
%R11D 368r-496r i=inf end
%EBX 112r-368r i=4.116848e-03 w=4.464286e-03 extend
%EBX 112r-496r i=4.116848e-03 all
%R14D 112r-368r i=4.303977e-03 w=4.464286e-03 extend
%R14D 112r-496r i=4.303977e-03 all
%R15D 112r-368r i=3.641827e-03 w=4.464286e-03 extend
%R15D 112r-496r i=3.641827e-03 all
%R12D 112r-368r i=3.787500e-03 w=4.464286e-03 extend
%R12D 112r-496r i=3.787500e-03 all
%R13D 112r-368r i=3.945312e-03 w=4.464286e-03 extend
%R13D 112r-496r i=3.945312e-03 all
Best local split range: 368r-496r, 5.404304e-03, 2 instrs
    enterIntvBefore 368r: valno 0
    leaveIntvAfter 496r: not live
    useIntv [364r;512B): [364r;512B):1
  blit [112r,496r:0): [112r;364r)=0:0 [364r;496r)=1:0
  rewr BB#0	112r:0	%vreg77<def> = MOV32rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD4[FixedStack-1] GR32:%vreg77
  rewr BB#0	496B:1	MOV32mr <fi#7>, 1, %noreg, 0, %noreg, %vreg78; mem:ST4[%workFactor.addr] GR32:%vreg78
  rewr BB#0	368B:1	STACKMAP 0, 0, %vreg10, 0, <fi#5>, 0, %vreg6, 0, <fi#1>, 0, %vreg7, 0, <fi#2>, 0, 0, <fi#9>, 0, 0, <fi#0>, 0, %vreg8, 0, <fi#3>, 0, %vreg9, 0, <fi#4>, 0, 0, <fi#8>, 0, %vreg76, 0, <fi#6>, 0, %vreg78, 0, <fi#7>, 0, ...; mem:LD8[FixedStack5](align=4) LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack9](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3] LD8[FixedStack4](align=4) LD8[FixedStack8] LD8[FixedStack6](align=4) LD8[FixedStack7](align=4) GR32:%vreg10,%vreg9,%vreg76,%vreg78 GR64:%vreg6,%vreg7,%vreg8
  rewr BB#0	364B:0	%vreg78<def> = COPY %vreg77; GR32:%vreg78,%vreg77
Tagging non-progress ranges: %vreg78
queuing new interval: %vreg77 [112r,364r:0)  0@112r
queuing new interval: %vreg78 [364r,496r:0)  0@364r

selectOrSplit GR32:%vreg78 [364r,496r:0)  0@364r w=5.695489e-03
assigning %vreg78 to %ECX: CH [364r,496r:0)  0@364r CL [364r,496r:0)  0@364r

selectOrSplit GR32:%vreg77 [112r,364r:0)  0@112r w=1.549080e-03
hints: %ECX
RS_Assign Cascade 0
wait for second round
queuing new interval: %vreg77 [112r,364r:0)  0@112r

selectOrSplit GR32:%vreg75 [16r,360r:0)  0@16r w=2.715054e-03
hints: %R9D
RS_Split Cascade 0
Analyze counted 2 instrs in 1 blocks, through 0 blocks.
Inline spilling GR32:%vreg75 [16r,360r:0)  0@16r
From original %vreg11
Merged spilled regs: SS#10 [16r,360r:0)  0@x
spillAroundUses %vreg75
	folded:   16r	MOV32mr <fi#10>, 1, %noreg, 0, %noreg, %R9D; mem:ST4[FixedStack10]
Checking redundant spills for 0@360r in %vreg76 [360r,480r:0)  0@360r
Merged to stack int: SS#10 [16r,480r:0)  0@x
	folded:   360r	%vreg76<def> = MOV32rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD4[FixedStack10] GR32:%vreg76

selectOrSplit GR32:%vreg77 [112r,364r:0)  0@112r w=1.549080e-03
hints: %ECX
RS_Split Cascade 0
Analyze counted 2 instrs in 1 blocks, through 0 blocks.
Inline spilling GR32:%vreg77 [112r,364r:0)  0@112r
From original %vreg12
Value %vreg77:0@112r may remat from %vreg77<def> = MOV32rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD4[FixedStack-1] GR32:%vreg77
	remat:  368r	%vreg79<def> = MOV32rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD4[FixedStack-1] GR32:%vreg79
	        376e	%vreg78<def> = COPY %vreg79<kill>; GR32:%vreg78,%vreg79

All defs dead: %vreg77<def,dead> = MOV32rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD4[FixedStack-1] GR32:%vreg77
Remat created 1 dead defs.
Deleting dead def 112r	%vreg77<def,dead> = MOV32rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD4[FixedStack-1] GR32:%vreg77
0 registers to spill after remat.
queuing new interval: %vreg79 [368r,376r:0)  0@368r

selectOrSplit GR32:%vreg79 [368r,376r:0)  0@368r w=inf
hints: %ECX
assigning %vreg79 to %ECX: CH [368r,376r:0)  0@368r CL [368r,376r:0)  0@368r
Trying to reconcile hints for: %vreg6(%R14)
%vreg6(%R14) is recolorable.

********** STACK TRANSFORMATION METADATA **********
********** Function: BZ2_bzBuffToBuffCompress
********** REGISTER MAP **********
[%vreg6 -> %R14] GR64
[%vreg7 -> %RBX] GR64
[%vreg8 -> %R13] GR64
[%vreg9 -> %R12D] GR32
[%vreg10 -> %R15D] GR32
[%vreg15 -> %RDI] GR64
[%vreg16 -> %RSI] GR64
[%vreg28 -> %RDI] GR64
[%vreg32 -> %EAX] GR32
[%vreg33 -> %ECX] GR32
[%vreg34 -> %EDX] GR32
[%vreg35 -> %ESI] GR32
[%vreg38 -> %RDI] GR64
[%vreg40 -> %EAX] GR32
[%vreg43 -> %EAX] GR32
[%vreg44 -> %RAX] GR64
[%vreg46 -> %EAX] GR32
[%vreg48 -> %RAX] GR64
[%vreg50 -> %RAX] GR64
[%vreg52 -> %RDI] GR64
[%vreg53 -> %EAX] GR32
[%vreg58 -> %EDX] GR32
[%vreg60 -> %RCX] GR64
[%vreg61 -> %EAX] GR32
[%vreg63 -> %EAX] GR32
[%vreg64 -> %RDI] GR64
[%vreg65 -> %EAX] GR32
[%vreg66 -> %RDI] GR64
[%vreg67 -> %EAX] GR32
[%vreg69 -> %EAX] GR32
[%vreg71 -> %EAX] GR32
[%vreg73 -> %RDI] GR64
[%vreg74 -> %RSI] GR64
[%vreg76 -> %EAX] GR32
[%vreg78 -> %ECX] GR32
[%vreg79 -> %ECX] GR32
[%vreg11 -> fi#10] GR32
[%vreg75 -> fi#10] GR32


Stackmap 0:
  STACKMAP 0, 0, %vreg10, 0, <fi#5>, 0, %vreg6, 0, <fi#1>, 0, %vreg7, 0, <fi#2>, 0, 0, <fi#9>, 0, 0, <fi#0>, 0, %vreg8, 0, <fi#3>, 0, %vreg9, 0, <fi#4>, 0, 0, <fi#8>, 0, %vreg76, 0, <fi#6>, 0, %vreg78, 0, <fi#7>, 0, ...; mem:LD8[FixedStack5](align=4) LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack9](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3] LD8[FixedStack4](align=4) LD8[FixedStack8] LD8[FixedStack6](align=4) LD8[FixedStack7](align=4) GR32:%vreg10,%vreg9,%vreg76,%vreg78 GR64:%vreg6,%vreg7,%vreg8

i32 %blockSize100k: in register %R15D (vreg 10)
i32* %blockSize100k.addr: in stack slot 5 (size: 4)
i8* %dest: in register %R14 (vreg 6)
i8** %dest.addr: in stack slot 1 (size: 8)
i32* %destLen: in register %RBX (vreg 7)
i32** %destLen.addr: in stack slot 2 (size: 8)
i32* %ret: in stack slot 9 (size: 4)
i32* %retval: in stack slot 0 (size: 4)
i8* %source: in register %R13 (vreg 8)
i8** %source.addr: in stack slot 3 (size: 8)
i32 %sourceLen: in register %R12D (vreg 9)
i32* %sourceLen.addr: in stack slot 4 (size: 4)
%struct.bz_stream* %strm: in stack slot 8 (size: 80)
i32 %verbosity: in register %EAX (vreg 76)
i32* %verbosity.addr: in stack slot 6 (size: 4)
i32 %workFactor: in register %ECX (vreg 78)
i32* %workFactor.addr: in stack slot 7 (size: 4)

Duplicate operand locations:

i32 %verbosity: in stack slot 10 (size: 4)

Stackmap 1:
  STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#9>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, 0, <fi#8>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack9](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3] LD8[FixedStack4](align=4) LD8[FixedStack8]

i8** %dest.addr: in stack slot 1 (size: 8)
i32** %destLen.addr: in stack slot 2 (size: 8)
i32* %ret: in stack slot 9 (size: 4)
i32* %retval: in stack slot 0 (size: 4)
i8** %source.addr: in stack slot 3 (size: 8)
i32* %sourceLen.addr: in stack slot 4 (size: 4)
%struct.bz_stream* %strm: in stack slot 8 (size: 80)

Duplicate operand locations:


Stackmap 2:
  STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#9>, 0, 0, <fi#0>, 0, 0, <fi#8>, 0, ...; mem:LD8[FixedStack2] LD8[FixedStack9](align=4) LD8[FixedStack0](align=4) LD8[FixedStack8]

i32** %destLen.addr: in stack slot 2 (size: 8)
i32* %ret: in stack slot 9 (size: 4)
i32* %retval: in stack slot 0 (size: 4)
%struct.bz_stream* %strm: in stack slot 8 (size: 80)

Duplicate operand locations:


Stackmap 3:
  STACKMAP 3, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)

i32* %retval: in stack slot 0 (size: 4)

Duplicate operand locations:


Stackmap 4:
  STACKMAP 4, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)

i32* %retval: in stack slot 0 (size: 4)

Duplicate operand locations:


Stackmap 5:
  STACKMAP 5, 0, 0, <fi#9>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack9](align=4) LD8[FixedStack0](align=4)

i32* %ret: in stack slot 9 (size: 4)
i32* %retval: in stack slot 0 (size: 4)

Duplicate operand locations:


Stackmap 6:
  STACKMAP 6, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)

i32* %retval: in stack slot 0 (size: 4)

Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, %vreg10, 0, <fi#5>, 0, %vreg6, 0, <fi#1>, 0, %vreg7, 0, <fi#2>, 0, 0, <fi#9>, 0, 0, <fi#0>, 0, %vreg8, 0, <fi#3>, 0, %vreg9, 0, <fi#4>, 0, 0, <fi#8>, 0, %vreg76, 0, <fi#6>, 0, %vreg78, 0, <fi#7>, 0, ...; mem:LD8[FixedStack5](align=4) LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack9](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3] LD8[FixedStack4](align=4) LD8[FixedStack8] LD8[FixedStack6](align=4) LD8[FixedStack7](align=4) GR32:%vreg10,%vreg9,%vreg76,%vreg78 GR64:%vreg6,%vreg7,%vreg8
  -> Call instruction SlotIndex 320B, searching vregs 0 -> 80 and stack slots -2 -> 11

  STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#9>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, 0, <fi#8>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack9](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3] LD8[FixedStack4](align=4) LD8[FixedStack8]
  -> Call instruction SlotIndex 1264B, searching vregs 0 -> 80 and stack slots -2 -> 11

  STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#9>, 0, 0, <fi#0>, 0, 0, <fi#8>, 0, ...; mem:LD8[FixedStack2] LD8[FixedStack9](align=4) LD8[FixedStack0](align=4) LD8[FixedStack8]
  -> Call instruction SlotIndex 1712B, searching vregs 0 -> 80 and stack slots -2 -> 11

  STACKMAP 3, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
  -> Call instruction SlotIndex 2128B, searching vregs 0 -> 80 and stack slots -2 -> 11

  STACKMAP 4, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
  -> Call instruction SlotIndex 2320B, searching vregs 0 -> 80 and stack slots -2 -> 11

  STACKMAP 5, 0, 0, <fi#9>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack9](align=4) LD8[FixedStack0](align=4)
  -> Call instruction SlotIndex 2512B, searching vregs 0 -> 80 and stack slots -2 -> 11

  STACKMAP 6, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
  -> Call instruction SlotIndex 2752B, searching vregs 0 -> 80 and stack slots -2 -> 11

********** REWRITE VIRTUAL REGISTERS **********
********** Function: BZ2_bzBuffToBuffCompress
********** REGISTER MAP **********
[%vreg6 -> %R14] GR64
[%vreg7 -> %RBX] GR64
[%vreg8 -> %R13] GR64
[%vreg9 -> %R12D] GR32
[%vreg10 -> %R15D] GR32
[%vreg15 -> %RDI] GR64
[%vreg16 -> %RSI] GR64
[%vreg28 -> %RDI] GR64
[%vreg32 -> %EAX] GR32
[%vreg33 -> %ECX] GR32
[%vreg34 -> %EDX] GR32
[%vreg35 -> %ESI] GR32
[%vreg38 -> %RDI] GR64
[%vreg40 -> %EAX] GR32
[%vreg43 -> %EAX] GR32
[%vreg44 -> %RAX] GR64
[%vreg46 -> %EAX] GR32
[%vreg48 -> %RAX] GR64
[%vreg50 -> %RAX] GR64
[%vreg52 -> %RDI] GR64
[%vreg53 -> %EAX] GR32
[%vreg58 -> %EDX] GR32
[%vreg60 -> %RCX] GR64
[%vreg61 -> %EAX] GR32
[%vreg63 -> %EAX] GR32
[%vreg64 -> %RDI] GR64
[%vreg65 -> %EAX] GR32
[%vreg66 -> %RDI] GR64
[%vreg67 -> %EAX] GR32
[%vreg69 -> %EAX] GR32
[%vreg71 -> %EAX] GR32
[%vreg73 -> %RDI] GR64
[%vreg74 -> %RSI] GR64
[%vreg76 -> %EAX] GR32
[%vreg78 -> %ECX] GR32
[%vreg79 -> %ECX] GR32
[%vreg11 -> fi#10] GR32
[%vreg75 -> fi#10] GR32

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %ECX %RDI %RDX %RSI %R8D %R9D
16B		MOV32mr <fi#10>, 1, %noreg, 0, %noreg, %R9D; mem:ST4[FixedStack10]
32B		%vreg10<def> = COPY %R8D; GR32:%vreg10
48B		%vreg9<def> = COPY %ECX; GR32:%vreg9
64B		%vreg8<def> = COPY %RDX; GR64:%vreg8
80B		%vreg7<def> = COPY %RSI; GR64:%vreg7
96B		%vreg6<def> = COPY %RDI; GR64:%vreg6
224B		%vreg15<def> = MOV64ri <ga:@BZ2_bzBuffToBuffCompress>; GR64:%vreg15
256B		%vreg16<def> = MOV64rm <fi#-2>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-2] GR64:%vreg16
272B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
288B		%RDI<def> = COPY %vreg15<kill>; GR64:%vreg15
304B		%RSI<def> = COPY %vreg16<kill>; GR64:%vreg16
320B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
336B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
352B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
360B		%vreg76<def> = MOV32rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD4[FixedStack10] GR32:%vreg76
368B		%vreg79<def> = MOV32rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD4[FixedStack-1] GR32:%vreg79
376B		%vreg78<def> = COPY %vreg79<kill>; GR32:%vreg78,%vreg79
384B		STACKMAP 0, 0, %vreg10, 0, <fi#5>, 0, %vreg6, 0, <fi#1>, 0, %vreg7, 0, <fi#2>, 0, 0, <fi#9>, 0, 0, <fi#0>, 0, %vreg8, 0, <fi#3>, 0, %vreg9, 0, <fi#4>, 0, 0, <fi#8>, 0, %vreg76, 0, <fi#6>, 0, %vreg78, 0, <fi#7>, 0, ...; mem:LD8[FixedStack5](align=4) LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack9](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3] LD8[FixedStack4](align=4) LD8[FixedStack8] LD8[FixedStack6](align=4) LD8[FixedStack7](align=4) GR32:%vreg10,%vreg9,%vreg76,%vreg78 GR64:%vreg6,%vreg7,%vreg8
392B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
400B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg6<kill>; mem:ST8[%dest.addr] GR64:%vreg6
416B		MOV64mr <fi#2>, 1, %noreg, 0, %noreg, %vreg7<kill>; mem:ST8[%destLen.addr] GR64:%vreg7
432B		MOV64mr <fi#3>, 1, %noreg, 0, %noreg, %vreg8<kill>; mem:ST8[%source.addr] GR64:%vreg8
448B		MOV32mr <fi#4>, 1, %noreg, 0, %noreg, %vreg9<kill>; mem:ST4[%sourceLen.addr] GR32:%vreg9
464B		MOV32mr <fi#5>, 1, %noreg, 0, %noreg, %vreg10<kill>; mem:ST4[%blockSize100k.addr] GR32:%vreg10
480B		MOV32mr <fi#6>, 1, %noreg, 0, %noreg, %vreg76<kill>; mem:ST4[%verbosity.addr] GR32:%vreg76
496B		MOV32mr <fi#7>, 1, %noreg, 0, %noreg, %vreg78<kill>; mem:ST4[%workFactor.addr] GR32:%vreg78
512B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%dest.addr]
528B		JE_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#1
> MOV32mr <fi#10>, 1, %noreg, 0, %noreg, %R9D; mem:ST4[FixedStack10]
> %R15D<def> = COPY %R8D
> %R12D<def> = COPY %ECX
> %R13<def> = COPY %RDX
> %RBX<def> = COPY %RSI
> %R14<def> = COPY %RDI
> %RDI<def> = MOV64ri <ga:@BZ2_bzBuffToBuffCompress>
> %RSI<def> = MOV64rm <fi#-2>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-2]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def> = MOV32rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD4[FixedStack10]
> %ECX<def> = MOV32rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD4[FixedStack-1]
> %ECX<def> = COPY %ECX<kill>
Deleting identity copy.
> STACKMAP 0, 0, %R15D, 0, <fi#5>, 0, %R14, 0, <fi#1>, 0, %RBX, 0, <fi#2>, 0, 0, <fi#9>, 0, 0, <fi#0>, 0, %R13, 0, <fi#3>, 0, %R12D, 0, <fi#4>, 0, 0, <fi#8>, 0, %EAX, 0, <fi#6>, 0, %ECX, 0, <fi#7>, 0, ...; mem:LD8[FixedStack5](align=4) LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack9](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3] LD8[FixedStack4](align=4) LD8[FixedStack8] LD8[FixedStack6](align=4) LD8[FixedStack7](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %R14<kill>; mem:ST8[%dest.addr]
> MOV64mr <fi#2>, 1, %noreg, 0, %noreg, %RBX<kill>; mem:ST8[%destLen.addr]
> MOV64mr <fi#3>, 1, %noreg, 0, %noreg, %R13<kill>; mem:ST8[%source.addr]
> MOV32mr <fi#4>, 1, %noreg, 0, %noreg, %R12D<kill>; mem:ST4[%sourceLen.addr]
> MOV32mr <fi#5>, 1, %noreg, 0, %noreg, %R15D<kill>; mem:ST4[%blockSize100k.addr]
> MOV32mr <fi#6>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%verbosity.addr]
> MOV32mr <fi#7>, 1, %noreg, 0, %noreg, %ECX<kill>; mem:ST4[%workFactor.addr]
> CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%dest.addr]
> JE_1 <BB#9>, %EFLAGS<imp-use,kill>
544B	BB#1: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#0
560B		CMP64mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%destLen.addr]
576B		JE_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#2
> CMP64mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%destLen.addr]
> JE_1 <BB#9>, %EFLAGS<imp-use,kill>
592B	BB#2: derived from LLVM BB %lor.lhs.false.2
	    Predecessors according to CFG: BB#1
608B		CMP64mi8 <fi#3>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%source.addr]
624B		JE_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#3
> CMP64mi8 <fi#3>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%source.addr]
> JE_1 <BB#9>, %EFLAGS<imp-use,kill>
640B	BB#3: derived from LLVM BB %lor.lhs.false.4
	    Predecessors according to CFG: BB#2
656B		CMP32mi8 <fi#5>, 1, %noreg, 0, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%blockSize100k.addr]
672B		JL_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#4
> CMP32mi8 <fi#5>, 1, %noreg, 0, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%blockSize100k.addr]
> JL_1 <BB#9>, %EFLAGS<imp-use,kill>
688B	BB#4: derived from LLVM BB %lor.lhs.false.6
	    Predecessors according to CFG: BB#3
704B		CMP32mi8 <fi#5>, 1, %noreg, 0, %noreg, 9, %EFLAGS<imp-def>; mem:LD4[%blockSize100k.addr]
720B		JG_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#5
> CMP32mi8 <fi#5>, 1, %noreg, 0, %noreg, 9, %EFLAGS<imp-def>; mem:LD4[%blockSize100k.addr]
> JG_1 <BB#9>, %EFLAGS<imp-use,kill>
736B	BB#5: derived from LLVM BB %lor.lhs.false.8
	    Predecessors according to CFG: BB#4
752B		CMP32mi8 <fi#6>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%verbosity.addr]
768B		JL_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#6
> CMP32mi8 <fi#6>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%verbosity.addr]
> JL_1 <BB#9>, %EFLAGS<imp-use,kill>
784B	BB#6: derived from LLVM BB %lor.lhs.false.10
	    Predecessors according to CFG: BB#5
800B		CMP32mi8 <fi#6>, 1, %noreg, 0, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%verbosity.addr]
816B		JG_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#7
> CMP32mi8 <fi#6>, 1, %noreg, 0, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%verbosity.addr]
> JG_1 <BB#9>, %EFLAGS<imp-use,kill>
832B	BB#7: derived from LLVM BB %lor.lhs.false.12
	    Predecessors according to CFG: BB#6
848B		CMP32mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%workFactor.addr]
864B		JL_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#8
> CMP32mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%workFactor.addr]
> JL_1 <BB#9>, %EFLAGS<imp-use,kill>
880B	BB#8: derived from LLVM BB %lor.lhs.false.14
	    Predecessors according to CFG: BB#7
896B		CMP32mi <fi#7>, 1, %noreg, 0, %noreg, 250, %EFLAGS<imp-def>; mem:LD4[%workFactor.addr]
912B		JLE_1 <BB#10>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#10 BB#9
> CMP32mi <fi#7>, 1, %noreg, 0, %noreg, 250, %EFLAGS<imp-def>; mem:LD4[%workFactor.addr]
> JLE_1 <BB#10>, %EFLAGS<imp-use,kill>
928B	BB#9: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0 BB#1 BB#2 BB#3 BB#4 BB#5 BB#6 BB#7 BB#8
944B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
960B		JMP_1 <BB#21>
	    Successors according to CFG: BB#21
> MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
> JMP_1 <BB#21>
976B	BB#10: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#8
992B		CMP32mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%workFactor.addr]
1008B		JNE_1 <BB#12>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#12 BB#11
> CMP32mi8 <fi#7>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%workFactor.addr]
> JNE_1 <BB#12>, %EFLAGS<imp-use,kill>
1024B	BB#11: derived from LLVM BB %if.then.17
	    Predecessors according to CFG: BB#10
1040B		MOV32mi <fi#7>, 1, %noreg, 0, %noreg, 30; mem:ST4[%workFactor.addr]
	    Successors according to CFG: BB#12
> MOV32mi <fi#7>, 1, %noreg, 0, %noreg, 30; mem:ST4[%workFactor.addr]
1056B	BB#12: derived from LLVM BB %if.end.18
	    Predecessors according to CFG: BB#10 BB#11
1072B		%vreg28<def> = LEA64r <fi#8>, 1, %noreg, 0, %noreg; GR64:%vreg28
1088B		MOV64mi32 <fi#8>, 1, %noreg, 56, %noreg, 0; mem:ST8[%bzalloc]
1104B		MOV64mi32 <fi#8>, 1, %noreg, 64, %noreg, 0; mem:ST8[%bzfree]
1120B		MOV64mi32 <fi#8>, 1, %noreg, 72, %noreg, 0; mem:ST8[%opaque]
1136B		%vreg35<def> = MOV32rm <fi#5>, 1, %noreg, 0, %noreg; mem:LD4[%blockSize100k.addr] GR32:%vreg35
1152B		%vreg34<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%verbosity.addr] GR32:%vreg34
1168B		%vreg33<def> = MOV32rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD4[%workFactor.addr] GR32:%vreg33
1184B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1200B		%RDI<def> = COPY %vreg28<kill>; GR64:%vreg28
1216B		%ESI<def> = COPY %vreg35<kill>; GR32:%vreg35
1232B		%EDX<def> = COPY %vreg34<kill>; GR32:%vreg34
1248B		%ECX<def> = COPY %vreg33<kill>; GR32:%vreg33
1264B		CALL64pcrel32 <ga:@BZ2_bzCompressInit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %EDX<imp-use>, %ECX<imp-use>, %EAX<imp-def>
1280B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1296B		%vreg32<def> = COPY %EAX; GR32:%vreg32
1312B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1328B		STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#9>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, 0, <fi#8>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack9](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3] LD8[FixedStack4](align=4) LD8[FixedStack8]
1344B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1360B		MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %vreg32<kill>; mem:ST4[%ret] GR32:%vreg32
1376B		CMP32mi8 <fi#9>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%ret]
1392B		JE_1 <BB#14>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#14 BB#13
> %RDI<def> = LEA64r <fi#8>, 1, %noreg, 0, %noreg
> MOV64mi32 <fi#8>, 1, %noreg, 56, %noreg, 0; mem:ST8[%bzalloc]
> MOV64mi32 <fi#8>, 1, %noreg, 64, %noreg, 0; mem:ST8[%bzfree]
> MOV64mi32 <fi#8>, 1, %noreg, 72, %noreg, 0; mem:ST8[%opaque]
> %ESI<def> = MOV32rm <fi#5>, 1, %noreg, 0, %noreg; mem:LD4[%blockSize100k.addr]
> %EDX<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%verbosity.addr]
> %ECX<def> = MOV32rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD4[%workFactor.addr]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %ESI<def> = COPY %ESI<kill>
Deleting identity copy.
> %EDX<def> = COPY %EDX<kill>
Deleting identity copy.
> %ECX<def> = COPY %ECX<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@BZ2_bzCompressInit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %EDX<imp-use>, %ECX<imp-use>, %EAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def> = COPY %EAX
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#9>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, 0, <fi#8>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack9](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3] LD8[FixedStack4](align=4) LD8[FixedStack8]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%ret]
> CMP32mi8 <fi#9>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%ret]
> JE_1 <BB#14>, %EFLAGS<imp-use,kill>
1408B	BB#13: derived from LLVM BB %if.then.20
	    Predecessors according to CFG: BB#12
1424B		%vreg69<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%ret] GR32:%vreg69
1440B		MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %vreg69<kill>; mem:ST4[%retval] GR32:%vreg69
1456B		JMP_1 <BB#21>
	    Successors according to CFG: BB#21
> %EAX<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%ret]
> MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%retval]
> JMP_1 <BB#21>
1472B	BB#14: derived from LLVM BB %if.end.21
	    Predecessors according to CFG: BB#12
1488B		%vreg38<def> = LEA64r <fi#8>, 1, %noreg, 0, %noreg; GR64:%vreg38
1520B		%vreg50<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%source.addr] GR64:%vreg50
1536B		MOV64mr <fi#8>, 1, %noreg, 0, %noreg, %vreg50<kill>; mem:ST8[%next_in] GR64:%vreg50
1552B		%vreg48<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%dest.addr] GR64:%vreg48
1568B		MOV64mr <fi#8>, 1, %noreg, 24, %noreg, %vreg48<kill>; mem:ST8[%next_out] GR64:%vreg48
1584B		%vreg46<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%sourceLen.addr] GR32:%vreg46
1600B		MOV32mr <fi#8>, 1, %noreg, 8, %noreg, %vreg46<kill>; mem:ST4[%avail_in] GR32:%vreg46
1616B		%vreg44<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%destLen.addr] GR64:%vreg44
1632B		%vreg43<def> = MOV32rm %vreg44<kill>, 1, %noreg, 0, %noreg; mem:LD4[%18] GR32:%vreg43 GR64:%vreg44
1648B		MOV32mr <fi#8>, 1, %noreg, 32, %noreg, %vreg43<kill>; mem:ST4[%avail_out] GR32:%vreg43
1664B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1696B		%ESI<def> = MOV32ri 2
1704B		%RDI<def> = COPY %vreg38<kill>; GR64:%vreg38
1712B		CALL64pcrel32 <ga:@BZ2_bzCompress>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %EAX<imp-def>
1728B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1744B		%vreg40<def> = COPY %EAX; GR32:%vreg40
1760B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1776B		STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#9>, 0, 0, <fi#0>, 0, 0, <fi#8>, 0, ...; mem:LD8[FixedStack2] LD8[FixedStack9](align=4) LD8[FixedStack0](align=4) LD8[FixedStack8]
1792B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1808B		MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %vreg40<kill>; mem:ST4[%ret] GR32:%vreg40
1824B		CMP32mi8 <fi#9>, 1, %noreg, 0, %noreg, 3, %EFLAGS<imp-def>; mem:LD4[%ret]
1840B		JNE_1 <BB#16>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#16 BB#15
> %RDI<def> = LEA64r <fi#8>, 1, %noreg, 0, %noreg
> %RAX<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%source.addr]
> MOV64mr <fi#8>, 1, %noreg, 0, %noreg, %RAX<kill>; mem:ST8[%next_in]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%dest.addr]
> MOV64mr <fi#8>, 1, %noreg, 24, %noreg, %RAX<kill>; mem:ST8[%next_out]
> %EAX<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%sourceLen.addr]
> MOV32mr <fi#8>, 1, %noreg, 8, %noreg, %EAX<kill>; mem:ST4[%avail_in]
> %RAX<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%destLen.addr]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD4[%18]
> MOV32mr <fi#8>, 1, %noreg, 32, %noreg, %EAX<kill>; mem:ST4[%avail_out]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %ESI<def> = MOV32ri 2
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@BZ2_bzCompress>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %EAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def> = COPY %EAX
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#9>, 0, 0, <fi#0>, 0, 0, <fi#8>, 0, ...; mem:LD8[FixedStack2] LD8[FixedStack9](align=4) LD8[FixedStack0](align=4) LD8[FixedStack8]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%ret]
> CMP32mi8 <fi#9>, 1, %noreg, 0, %noreg, 3, %EFLAGS<imp-def>; mem:LD4[%ret]
> JNE_1 <BB#16>, %EFLAGS<imp-use,kill>
1856B	BB#15: derived from LLVM BB %if.then.24
	    Predecessors according to CFG: BB#14
1872B		JMP_1 <BB#19>
	    Successors according to CFG: BB#19
> JMP_1 <BB#19>
1888B	BB#16: derived from LLVM BB %if.end.25
	    Predecessors according to CFG: BB#14
1904B		CMP32mi8 <fi#9>, 1, %noreg, 0, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%ret]
1920B		JE_1 <BB#18>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#18 BB#17
> CMP32mi8 <fi#9>, 1, %noreg, 0, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%ret]
> JE_1 <BB#18>, %EFLAGS<imp-use,kill>
1936B	BB#17: derived from LLVM BB %if.then.27
	    Predecessors according to CFG: BB#16
1952B		JMP_1 <BB#20>
	    Successors according to CFG: BB#20
> JMP_1 <BB#20>
1968B	BB#18: derived from LLVM BB %if.end.28
	    Predecessors according to CFG: BB#16
1984B		%vreg52<def> = LEA64r <fi#8>, 1, %noreg, 0, %noreg; GR64:%vreg52
2000B		%vreg61<def> = MOV32rm <fi#8>, 1, %noreg, 32, %noreg; mem:LD4[%avail_out29] GR32:%vreg61
2016B		%vreg60<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%destLen.addr] GR64:%vreg60
2032B		%vreg58<def> = MOV32rm %vreg60, 1, %noreg, 0, %noreg; mem:LD4[%23] GR32:%vreg58 GR64:%vreg60
2064B		%vreg58<def,tied1> = SUB32rr %vreg58<kill,tied0>, %vreg61<kill>, %EFLAGS<imp-def,dead>; GR32:%vreg58,%vreg61
2080B		MOV32mr %vreg60<kill>, 1, %noreg, 0, %noreg, %vreg58<kill>; mem:ST4[%23] GR64:%vreg60 GR32:%vreg58
2096B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2112B		%RDI<def> = COPY %vreg52<kill>; GR64:%vreg52
2128B		CALL64pcrel32 <ga:@BZ2_bzCompressEnd>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
2144B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2160B		%vreg53<def,dead> = COPY %EAX; GR32:%vreg53
2176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2192B		STACKMAP 3, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
2208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2224B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
2240B		JMP_1 <BB#21>
	    Successors according to CFG: BB#21
> %RDI<def> = LEA64r <fi#8>, 1, %noreg, 0, %noreg
> %EAX<def> = MOV32rm <fi#8>, 1, %noreg, 32, %noreg; mem:LD4[%avail_out29]
> %RCX<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%destLen.addr]
> %EDX<def> = MOV32rm %RCX, 1, %noreg, 0, %noreg; mem:LD4[%23]
> %EDX<def,tied1> = SUB32rr %EDX<kill,tied0>, %EAX<kill>, %EFLAGS<imp-def,dead>
> MOV32mr %RCX<kill>, 1, %noreg, 0, %noreg, %EDX<kill>; mem:ST4[%23]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@BZ2_bzCompressEnd>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def,dead> = COPY %EAX
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 3, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
> JMP_1 <BB#21>
2256B	BB#19: derived from LLVM BB %output_overflow
	    Predecessors according to CFG: BB#15
2272B		%vreg66<def> = LEA64r <fi#8>, 1, %noreg, 0, %noreg; GR64:%vreg66
2288B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2304B		%RDI<def> = COPY %vreg66<kill>; GR64:%vreg66
2320B		CALL64pcrel32 <ga:@BZ2_bzCompressEnd>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
2336B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2352B		%vreg67<def,dead> = COPY %EAX; GR32:%vreg67
2368B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2384B		STACKMAP 4, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
2400B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2416B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -8; mem:ST4[%retval]
2432B		JMP_1 <BB#21>
	    Successors according to CFG: BB#21
> %RDI<def> = LEA64r <fi#8>, 1, %noreg, 0, %noreg
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@BZ2_bzCompressEnd>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def,dead> = COPY %EAX
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 4, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -8; mem:ST4[%retval]
> JMP_1 <BB#21>
2448B	BB#20: derived from LLVM BB %errhandler
	    Predecessors according to CFG: BB#17
2464B		%vreg64<def> = LEA64r <fi#8>, 1, %noreg, 0, %noreg; GR64:%vreg64
2480B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2496B		%RDI<def> = COPY %vreg64<kill>; GR64:%vreg64
2512B		CALL64pcrel32 <ga:@BZ2_bzCompressEnd>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
2528B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2544B		%vreg65<def,dead> = COPY %EAX; GR32:%vreg65
2560B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2576B		STACKMAP 5, 0, 0, <fi#9>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack9](align=4) LD8[FixedStack0](align=4)
2592B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2608B		%vreg63<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%ret] GR32:%vreg63
2624B		MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %vreg63<kill>; mem:ST4[%retval] GR32:%vreg63
	    Successors according to CFG: BB#21
> %RDI<def> = LEA64r <fi#8>, 1, %noreg, 0, %noreg
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@BZ2_bzCompressEnd>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def,dead> = COPY %EAX
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 5, 0, 0, <fi#9>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack9](align=4) LD8[FixedStack0](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[%ret]
> MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%retval]
2640B	BB#21: derived from LLVM BB %return
	    Predecessors according to CFG: BB#18 BB#20 BB#19 BB#13 BB#9
2656B		%vreg73<def> = MOV64ri <ga:@BZ2_bzBuffToBuffCompress>; GR64:%vreg73
2688B		%vreg74<def> = MOV64rm <fi#-2>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-2] GR64:%vreg74
2704B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2720B		%RDI<def> = COPY %vreg73<kill>; GR64:%vreg73
2736B		%RSI<def> = COPY %vreg74<kill>; GR64:%vreg74
2752B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
2768B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2784B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2800B		STACKMAP 6, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
2816B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2832B		%vreg71<def> = MOV32rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD4[%retval] GR32:%vreg71
2848B		%EAX<def> = COPY %vreg71<kill>; GR32:%vreg71
2864B		RETQ %EAX<imp-use>
> %RDI<def> = MOV64ri <ga:@BZ2_bzBuffToBuffCompress>
> %RSI<def> = MOV64rm <fi#-2>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-2]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 6, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def> = MOV32rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD4[%retval]
> %EAX<def> = COPY %EAX<kill>
Deleting identity copy.
> RETQ %EAX<imp-use>
Computing live-in reg-units in ABI blocks.
0B	BB#0 DIL#0 SIL#0 DH#0 DL#0 CH#0 CL#0 R8B#0 R9B#0
Created 8 new intervals.
********** INTERVALS **********
CH [0B,48r:0)  0@0B-phi
CL [0B,48r:0)  0@0B-phi
DH [0B,64r:0)[1008r,1024r:1)  0@0B-phi 1@1008r
DIL [0B,96r:0)[272r,304r:8)[976r,1024r:7)[1424r,1440r:6)[1840r,1856r:5)[2080r,2096r:2)[2272r,2288r:3)[2464r,2480r:4)[2688r,2720r:1)  0@0B-phi 1@2688r 2@2080r 3@2272r 4@2464r 5@1840r 6@1424r 7@976r 8@272r
DL [0B,64r:0)[1008r,1024r:1)  0@0B-phi 1@1008r
SIL [0B,80r:0)[288r,304r:3)[992r,1024r:1)[2704r,2720r:2)  0@0B-phi 1@992r 2@2704r 3@288r
R8B [0B,32r:0)  0@0B-phi
R9B [0B,16r:0)  0@0B-phi
%vreg0 [96r,112r:0)  0@96r
%vreg1 [112r,384r:0)  0@112r
%vreg2 [80r,128r:0)  0@80r
%vreg3 [128r,400r:0)  0@128r
%vreg4 [64r,144r:0)  0@64r
%vreg5 [144r,416r:0)  0@144r
%vreg6 [48r,160r:0)  0@48r
%vreg7 [160r,432r:0)  0@160r
%vreg8 [32r,176r:0)  0@32r
%vreg9 [176r,448r:0)  0@176r
%vreg10 [16r,192r:0)  0@16r
%vreg11 [192r,464r:0)  0@192r
%vreg13 [208r,224r:0)  0@208r
%vreg14 [224r,272r:0)  0@224r
%vreg15 [240r,288r:0)  0@240r
%vreg24 [864r,976r:0)  0@864r
%vreg27 [1056r,1120r:0)  0@1056r
%vreg28 [944r,1008r:0)  0@944r
%vreg29 [928r,992r:0)  0@928r
%vreg32 [1248r,1424r:0)  0@1248r
%vreg33 [1472r,1536r:0)  0@1472r
%vreg36 [1376r,1392r:0)  0@1376r
%vreg37 [1360r,1376r:0)  0@1360r
%vreg39 [1328r,1344r:0)  0@1328r
%vreg41 [1296r,1312r:0)  0@1296r
%vreg43 [1264r,1280r:0)  0@1264r
%vreg45 [1712r,1840r:0)  0@1712r
%vreg46 [1888r,1888d:0)  0@1888r
%vreg51 [1776r,1792r:0)[1792r,1808r:1)  0@1776r 1@1792r
%vreg52 [1760r,1776r:0)  0@1760r
%vreg53 [1744r,1808r:0)  0@1744r
%vreg54 [1728r,1792r:0)  0@1728r
%vreg56 [2576r,2592r:0)  0@2576r
%vreg57 [2432r,2464r:0)  0@2432r
%vreg58 [2512r,2512d:0)  0@2512r
%vreg60 [2240r,2272r:0)  0@2240r
%vreg61 [2320r,2320d:0)  0@2320r
%vreg62 [2048r,2080r:0)  0@2048r
%vreg63 [2128r,2128d:0)  0@2128r
%vreg65 [1184r,1200r:0)  0@1184r
%vreg67 [2800r,2816r:0)  0@2800r
%vreg68 [2624r,2640r:0)  0@2624r
%vreg69 [2640r,2688r:0)  0@2640r
%vreg70 [2656r,2704r:0)  0@2656r
RegMasks: 304r 1024r 1440r 1856r 2096r 2288r 2480r 2720r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzBuffToBuffDecompress: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=4, align=4, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=8, align=8, at location [SP+8]
  fi#3: size=8, align=8, at location [SP+8]
  fi#4: size=4, align=4, at location [SP+8]
  fi#5: size=4, align=4, at location [SP+8]
  fi#6: size=4, align=4, at location [SP+8]
  fi#7: size=80, align=8, at location [SP+8]
  fi#8: size=4, align=4, at location [SP+8]
Function Live Ins: %RDI in %vreg0, %RSI in %vreg2, %RDX in %vreg4, %ECX in %vreg6, %R8D in %vreg8, %R9D in %vreg10

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI %RSI %RDX %ECX %R8D %R9D
16B		%vreg10<def> = COPY %R9D; GR32:%vreg10
32B		%vreg8<def> = COPY %R8D; GR32:%vreg8
48B		%vreg6<def> = COPY %ECX; GR32:%vreg6
64B		%vreg4<def> = COPY %RDX; GR64:%vreg4
80B		%vreg2<def> = COPY %RSI; GR64:%vreg2
96B		%vreg0<def> = COPY %RDI; GR64:%vreg0
112B		%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
128B		%vreg3<def> = COPY %vreg2; GR64:%vreg3,%vreg2
144B		%vreg5<def> = COPY %vreg4; GR64:%vreg5,%vreg4
160B		%vreg7<def> = COPY %vreg6; GR32:%vreg7,%vreg6
176B		%vreg9<def> = COPY %vreg8; GR32:%vreg9,%vreg8
192B		%vreg11<def> = COPY %vreg10; GR32:%vreg11,%vreg10
208B		%vreg13<def> = MOV64ri <ga:@BZ2_bzBuffToBuffDecompress>; GR64:%vreg13
224B		%vreg14<def> = COPY %vreg13; GR64:%vreg14,%vreg13
240B		%vreg15<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg15
256B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
272B		%RDI<def> = COPY %vreg14; GR64:%vreg14
288B		%RSI<def> = COPY %vreg15; GR64:%vreg15
304B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
320B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
336B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
352B		STACKMAP 0, 0, %vreg1, 0, <fi#1>, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, %vreg9, 0, <fi#5>, 0, %vreg5, 0, <fi#3>, 0, %vreg7, 0, <fi#4>, 0, 0, <fi#7>, 0, %vreg11, 0, <fi#6>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack8](align=4) LD8[FixedStack0](align=4) LD8[FixedStack5](align=4) LD8[FixedStack3] LD8[FixedStack4](align=4) LD8[FixedStack7] LD8[FixedStack6](align=4) GR64:%vreg1,%vreg3,%vreg5 GR32:%vreg9,%vreg7,%vreg11
368B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
384B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%dest.addr] GR64:%vreg1
400B		MOV64mr <fi#2>, 1, %noreg, 0, %noreg, %vreg3; mem:ST8[%destLen.addr] GR64:%vreg3
416B		MOV64mr <fi#3>, 1, %noreg, 0, %noreg, %vreg5; mem:ST8[%source.addr] GR64:%vreg5
432B		MOV32mr <fi#4>, 1, %noreg, 0, %noreg, %vreg7; mem:ST4[%sourceLen.addr] GR32:%vreg7
448B		MOV32mr <fi#5>, 1, %noreg, 0, %noreg, %vreg9; mem:ST4[%small.addr] GR32:%vreg9
464B		MOV32mr <fi#6>, 1, %noreg, 0, %noreg, %vreg11; mem:ST4[%verbosity.addr] GR32:%vreg11
480B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%dest.addr]
496B		JE_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#1

512B	BB#1: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#0
528B		CMP64mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%destLen.addr]
544B		JE_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#2

560B	BB#2: derived from LLVM BB %lor.lhs.false.2
	    Predecessors according to CFG: BB#1
576B		CMP64mi8 <fi#3>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%source.addr]
592B		JE_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#3

608B	BB#3: derived from LLVM BB %lor.lhs.false.4
	    Predecessors according to CFG: BB#2
624B		CMP32mi8 <fi#5>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%small.addr]
640B		JE_1 <BB#5>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#5 BB#4

656B	BB#4: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#3
672B		CMP32mi8 <fi#5>, 1, %noreg, 0, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%small.addr]
688B		JNE_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#5

704B	BB#5: derived from LLVM BB %lor.lhs.false.7
	    Predecessors according to CFG: BB#3 BB#4
720B		CMP32mi8 <fi#6>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%verbosity.addr]
736B		JL_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#6

752B	BB#6: derived from LLVM BB %lor.lhs.false.9
	    Predecessors according to CFG: BB#5
768B		CMP32mi8 <fi#6>, 1, %noreg, 0, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%verbosity.addr]
784B		JLE_1 <BB#8>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#8 BB#7

800B	BB#7: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0 BB#1 BB#2 BB#4 BB#5 BB#6
816B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
832B		JMP_1 <BB#19>
	    Successors according to CFG: BB#19

848B	BB#8: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#6
864B		%vreg24<def> = LEA64r <fi#7>, 1, %noreg, 0, %noreg; GR64:%vreg24
880B		MOV64mi32 <fi#7>, 1, %noreg, 56, %noreg, 0; mem:ST8[%bzalloc]
896B		MOV64mi32 <fi#7>, 1, %noreg, 64, %noreg, 0; mem:ST8[%bzfree]
912B		MOV64mi32 <fi#7>, 1, %noreg, 72, %noreg, 0; mem:ST8[%opaque]
928B		%vreg29<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%verbosity.addr] GR32:%vreg29
944B		%vreg28<def> = MOV32rm <fi#5>, 1, %noreg, 0, %noreg; mem:LD4[%small.addr] GR32:%vreg28
960B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
976B		%RDI<def> = COPY %vreg24; GR64:%vreg24
992B		%ESI<def> = COPY %vreg29; GR32:%vreg29
1008B		%EDX<def> = COPY %vreg28; GR32:%vreg28
1024B		CALL64pcrel32 <ga:@BZ2_bzDecompressInit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %EDX<imp-use>, %EAX<imp-def>
1040B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1056B		%vreg27<def> = COPY %EAX<kill>; GR32:%vreg27
1072B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1088B		STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, 0, <fi#7>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack8](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3] LD8[FixedStack4](align=4) LD8[FixedStack7]
1104B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1120B		MOV32mr <fi#8>, 1, %noreg, 0, %noreg, %vreg27; mem:ST4[%ret] GR32:%vreg27
1136B		CMP32mi8 <fi#8>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%ret]
1152B		JE_1 <BB#10>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#10 BB#9

1168B	BB#9: derived from LLVM BB %if.then.12
	    Predecessors according to CFG: BB#8
1184B		%vreg65<def> = MOV32rm <fi#8>, 1, %noreg, 0, %noreg; mem:LD4[%ret] GR32:%vreg65
1200B		MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %vreg65; mem:ST4[%retval] GR32:%vreg65
1216B		JMP_1 <BB#19>
	    Successors according to CFG: BB#19

1232B	BB#10: derived from LLVM BB %if.end.13
	    Predecessors according to CFG: BB#8
1248B		%vreg32<def> = LEA64r <fi#7>, 1, %noreg, 0, %noreg; GR64:%vreg32
1264B		%vreg43<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%source.addr] GR64:%vreg43
1280B		MOV64mr <fi#7>, 1, %noreg, 0, %noreg, %vreg43; mem:ST8[%next_in] GR64:%vreg43
1296B		%vreg41<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%dest.addr] GR64:%vreg41
1312B		MOV64mr <fi#7>, 1, %noreg, 24, %noreg, %vreg41; mem:ST8[%next_out] GR64:%vreg41
1328B		%vreg39<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%sourceLen.addr] GR32:%vreg39
1344B		MOV32mr <fi#7>, 1, %noreg, 8, %noreg, %vreg39; mem:ST4[%avail_in] GR32:%vreg39
1360B		%vreg37<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%destLen.addr] GR64:%vreg37
1376B		%vreg36<def> = MOV32rm %vreg37, 1, %noreg, 0, %noreg; mem:LD4[%14] GR32:%vreg36 GR64:%vreg37
1392B		MOV32mr <fi#7>, 1, %noreg, 32, %noreg, %vreg36; mem:ST4[%avail_out] GR32:%vreg36
1408B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1424B		%RDI<def> = COPY %vreg32; GR64:%vreg32
1440B		CALL64pcrel32 <ga:@BZ2_bzDecompress>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
1456B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1472B		%vreg33<def> = COPY %EAX<kill>; GR32:%vreg33
1488B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1504B		STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, 0, <fi#7>, 0, ...; mem:LD8[FixedStack2] LD8[FixedStack8](align=4) LD8[FixedStack0](align=4) LD8[FixedStack7]
1520B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1536B		MOV32mr <fi#8>, 1, %noreg, 0, %noreg, %vreg33; mem:ST4[%ret] GR32:%vreg33
1552B		CMP32mi8 <fi#8>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%ret]
1568B		JNE_1 <BB#12>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#12 BB#11

1584B	BB#11: derived from LLVM BB %if.then.16
	    Predecessors according to CFG: BB#10
1600B		JMP_1 <BB#15>
	    Successors according to CFG: BB#15

1616B	BB#12: derived from LLVM BB %if.end.17
	    Predecessors according to CFG: BB#10
1632B		CMP32mi8 <fi#8>, 1, %noreg, 0, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%ret]
1648B		JE_1 <BB#14>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#14 BB#13

1664B	BB#13: derived from LLVM BB %if.then.19
	    Predecessors according to CFG: BB#12
1680B		JMP_1 <BB#18>
	    Successors according to CFG: BB#18

1696B	BB#14: derived from LLVM BB %if.end.20
	    Predecessors according to CFG: BB#12
1712B		%vreg45<def> = LEA64r <fi#7>, 1, %noreg, 0, %noreg; GR64:%vreg45
1728B		%vreg54<def> = MOV32rm <fi#7>, 1, %noreg, 32, %noreg; mem:LD4[%avail_out21] GR32:%vreg54
1744B		%vreg53<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%destLen.addr] GR64:%vreg53
1760B		%vreg52<def> = MOV32rm %vreg53, 1, %noreg, 0, %noreg; mem:LD4[%19] GR32:%vreg52 GR64:%vreg53
1776B		%vreg51<def> = COPY %vreg52; GR32:%vreg51,%vreg52
1792B		%vreg51<def,tied1> = SUB32rr %vreg51<tied0>, %vreg54, %EFLAGS<imp-def,dead>; GR32:%vreg51,%vreg54
1808B		MOV32mr %vreg53, 1, %noreg, 0, %noreg, %vreg51; mem:ST4[%19] GR64:%vreg53 GR32:%vreg51
1824B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1840B		%RDI<def> = COPY %vreg45; GR64:%vreg45
1856B		CALL64pcrel32 <ga:@BZ2_bzDecompressEnd>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
1872B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1888B		%vreg46<def,dead> = COPY %EAX<kill>; GR32:%vreg46
1904B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1920B		STACKMAP 3, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
1936B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1952B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
1968B		JMP_1 <BB#19>
	    Successors according to CFG: BB#19

1984B	BB#15: derived from LLVM BB %output_overflow_or_eof
	    Predecessors according to CFG: BB#11
2000B		CMP32mi8 <fi#7>, 1, %noreg, 32, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_out23]
2016B		JBE_1 <BB#17>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#17 BB#16

2032B	BB#16: derived from LLVM BB %if.then.25
	    Predecessors according to CFG: BB#15
2048B		%vreg62<def> = LEA64r <fi#7>, 1, %noreg, 0, %noreg; GR64:%vreg62
2064B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2080B		%RDI<def> = COPY %vreg62; GR64:%vreg62
2096B		CALL64pcrel32 <ga:@BZ2_bzDecompressEnd>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
2112B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2128B		%vreg63<def,dead> = COPY %EAX<kill>; GR32:%vreg63
2144B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2160B		STACKMAP 4, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
2176B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2192B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -7; mem:ST4[%retval]
2208B		JMP_1 <BB#19>
	    Successors according to CFG: BB#19

2224B	BB#17: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#15
2240B		%vreg60<def> = LEA64r <fi#7>, 1, %noreg, 0, %noreg; GR64:%vreg60
2256B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2272B		%RDI<def> = COPY %vreg60; GR64:%vreg60
2288B		CALL64pcrel32 <ga:@BZ2_bzDecompressEnd>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
2304B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2320B		%vreg61<def,dead> = COPY %EAX<kill>; GR32:%vreg61
2336B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2352B		STACKMAP 5, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
2368B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2384B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -8; mem:ST4[%retval]
2400B		JMP_1 <BB#19>
	    Successors according to CFG: BB#19

2416B	BB#18: derived from LLVM BB %errhandler
	    Predecessors according to CFG: BB#13
2432B		%vreg57<def> = LEA64r <fi#7>, 1, %noreg, 0, %noreg; GR64:%vreg57
2448B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2464B		%RDI<def> = COPY %vreg57; GR64:%vreg57
2480B		CALL64pcrel32 <ga:@BZ2_bzDecompressEnd>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
2496B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2512B		%vreg58<def,dead> = COPY %EAX<kill>; GR32:%vreg58
2528B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2544B		STACKMAP 6, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack8](align=4) LD8[FixedStack0](align=4)
2560B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2576B		%vreg56<def> = MOV32rm <fi#8>, 1, %noreg, 0, %noreg; mem:LD4[%ret] GR32:%vreg56
2592B		MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %vreg56; mem:ST4[%retval] GR32:%vreg56
	    Successors according to CFG: BB#19

2608B	BB#19: derived from LLVM BB %return
	    Predecessors according to CFG: BB#14 BB#18 BB#17 BB#16 BB#9 BB#7
2624B		%vreg68<def> = MOV64ri <ga:@BZ2_bzBuffToBuffDecompress>; GR64:%vreg68
2640B		%vreg69<def> = COPY %vreg68; GR64:%vreg69,%vreg68
2656B		%vreg70<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg70
2672B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2688B		%RDI<def> = COPY %vreg69; GR64:%vreg69
2704B		%RSI<def> = COPY %vreg70; GR64:%vreg70
2720B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
2736B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2752B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2768B		STACKMAP 7, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
2784B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2800B		%vreg67<def> = MOV32rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD4[%retval] GR32:%vreg67
2816B		%EAX<def> = COPY %vreg67; GR32:%vreg67
2832B		RETQ %EAX<imp-use,kill>

# End machine code for function BZ2_bzBuffToBuffDecompress.

********** SIMPLE REGISTER COALESCING **********
********** Function: BZ2_bzBuffToBuffDecompress
********** JOINING INTERVALS ***********
if.then:
return:
2688B	%RDI<def> = COPY %vreg69; GR64:%vreg69
	Considering merging %vreg69 with %RDI
	Can only merge into reserved registers.
2704B	%RSI<def> = COPY %vreg70; GR64:%vreg70
	Considering merging %vreg70 with %RSI
	Can only merge into reserved registers.
2816B	%EAX<def> = COPY %vreg67; GR32:%vreg67
	Considering merging %vreg67 with %EAX
	Can only merge into reserved registers.
lor.lhs.false.7:
lor.lhs.false:
lor.lhs.false.2:
lor.lhs.false.4:
land.lhs.true:
lor.lhs.false.9:
if.end:
976B	%RDI<def> = COPY %vreg24; GR64:%vreg24
	Considering merging %vreg24 with %RDI
	Can only merge into reserved registers.
992B	%ESI<def> = COPY %vreg29; GR32:%vreg29
	Considering merging %vreg29 with %ESI
	Can only merge into reserved registers.
1008B	%EDX<def> = COPY %vreg28; GR32:%vreg28
	Considering merging %vreg28 with %EDX
	Can only merge into reserved registers.
1056B	%vreg27<def> = COPY %EAX<kill>; GR32:%vreg27
	Considering merging %vreg27 with %EAX
	Can only merge into reserved registers.
if.end.13:
1424B	%RDI<def> = COPY %vreg32; GR64:%vreg32
	Considering merging %vreg32 with %RDI
	Can only merge into reserved registers.
1472B	%vreg33<def> = COPY %EAX<kill>; GR32:%vreg33
	Considering merging %vreg33 with %EAX
	Can only merge into reserved registers.
if.end.17:
output_overflow_or_eof:
entry:
16B	%vreg10<def> = COPY %R9D; GR32:%vreg10
	Considering merging %vreg10 with %R9D
	Can only merge into reserved registers.
32B	%vreg8<def> = COPY %R8D; GR32:%vreg8
	Considering merging %vreg8 with %R8D
	Can only merge into reserved registers.
48B	%vreg6<def> = COPY %ECX; GR32:%vreg6
	Considering merging %vreg6 with %ECX
	Can only merge into reserved registers.
64B	%vreg4<def> = COPY %RDX; GR64:%vreg4
	Considering merging %vreg4 with %RDX
	Can only merge into reserved registers.
80B	%vreg2<def> = COPY %RSI; GR64:%vreg2
	Considering merging %vreg2 with %RSI
	Can only merge into reserved registers.
96B	%vreg0<def> = COPY %RDI; GR64:%vreg0
	Considering merging %vreg0 with %RDI
	Can only merge into reserved registers.
272B	%RDI<def> = COPY %vreg14; GR64:%vreg14
	Considering merging %vreg14 with %RDI
	Can only merge into reserved registers.
288B	%RSI<def> = COPY %vreg15; GR64:%vreg15
	Considering merging %vreg15 with %RSI
	Can only merge into reserved registers.
if.then.12:
if.then.16:
if.then.19:
if.end.20:
1840B	%RDI<def> = COPY %vreg45; GR64:%vreg45
	Considering merging %vreg45 with %RDI
	Can only merge into reserved registers.
1888B	%vreg46<def,dead> = COPY %EAX<kill>; GR32:%vreg46
	Considering merging %vreg46 with %EAX
	Can only merge into reserved registers.
if.then.25:
2080B	%RDI<def> = COPY %vreg62; GR64:%vreg62
	Considering merging %vreg62 with %RDI
	Can only merge into reserved registers.
2128B	%vreg63<def,dead> = COPY %EAX<kill>; GR32:%vreg63
	Considering merging %vreg63 with %EAX
	Can only merge into reserved registers.
if.else:
2272B	%RDI<def> = COPY %vreg60; GR64:%vreg60
	Considering merging %vreg60 with %RDI
	Can only merge into reserved registers.
2320B	%vreg61<def,dead> = COPY %EAX<kill>; GR32:%vreg61
	Considering merging %vreg61 with %EAX
	Can only merge into reserved registers.
errhandler:
2464B	%RDI<def> = COPY %vreg57; GR64:%vreg57
	Considering merging %vreg57 with %RDI
	Can only merge into reserved registers.
2512B	%vreg58<def,dead> = COPY %EAX<kill>; GR32:%vreg58
	Considering merging %vreg58 with %EAX
	Can only merge into reserved registers.
2640B	%vreg69<def> = COPY %vreg68; GR64:%vreg69,%vreg68
	Considering merging to GR64 with %vreg68 in %vreg69
		RHS = %vreg68 [2624r,2640r:0)  0@2624r
		LHS = %vreg69 [2640r,2688r:0)  0@2640r
		merge %vreg69:0@2640r into %vreg68:0@2624r --> @2624r
		erased:	2640r	%vreg69<def> = COPY %vreg68; GR64:%vreg69,%vreg68
		updated: 2624B	%vreg69<def> = MOV64ri <ga:@BZ2_bzBuffToBuffDecompress>; GR64:%vreg69
	Success: %vreg68 -> %vreg69
	Result = %vreg69 [2624r,2688r:0)  0@2624r
112B	%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
	Considering merging to GR64 with %vreg0 in %vreg1
		RHS = %vreg0 [96r,112r:0)  0@96r
		LHS = %vreg1 [112r,384r:0)  0@112r
		merge %vreg1:0@112r into %vreg0:0@96r --> @96r
		erased:	112r	%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
		updated: 96B	%vreg1<def> = COPY %RDI; GR64:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [96r,384r:0)  0@96r
128B	%vreg3<def> = COPY %vreg2; GR64:%vreg3,%vreg2
	Considering merging to GR64 with %vreg2 in %vreg3
		RHS = %vreg2 [80r,128r:0)  0@80r
		LHS = %vreg3 [128r,400r:0)  0@128r
		merge %vreg3:0@128r into %vreg2:0@80r --> @80r
		erased:	128r	%vreg3<def> = COPY %vreg2; GR64:%vreg3,%vreg2
		updated: 80B	%vreg3<def> = COPY %RSI; GR64:%vreg3
	Success: %vreg2 -> %vreg3
	Result = %vreg3 [80r,400r:0)  0@80r
144B	%vreg5<def> = COPY %vreg4; GR64:%vreg5,%vreg4
	Considering merging to GR64 with %vreg4 in %vreg5
		RHS = %vreg4 [64r,144r:0)  0@64r
		LHS = %vreg5 [144r,416r:0)  0@144r
		merge %vreg5:0@144r into %vreg4:0@64r --> @64r
		erased:	144r	%vreg5<def> = COPY %vreg4; GR64:%vreg5,%vreg4
		updated: 64B	%vreg5<def> = COPY %RDX; GR64:%vreg5
	Success: %vreg4 -> %vreg5
	Result = %vreg5 [64r,416r:0)  0@64r
160B	%vreg7<def> = COPY %vreg6; GR32:%vreg7,%vreg6
	Considering merging to GR32 with %vreg6 in %vreg7
		RHS = %vreg6 [48r,160r:0)  0@48r
		LHS = %vreg7 [160r,432r:0)  0@160r
		merge %vreg7:0@160r into %vreg6:0@48r --> @48r
		erased:	160r	%vreg7<def> = COPY %vreg6; GR32:%vreg7,%vreg6
		updated: 48B	%vreg7<def> = COPY %ECX; GR32:%vreg7
	Success: %vreg6 -> %vreg7
	Result = %vreg7 [48r,432r:0)  0@48r
176B	%vreg9<def> = COPY %vreg8; GR32:%vreg9,%vreg8
	Considering merging to GR32 with %vreg8 in %vreg9
		RHS = %vreg8 [32r,176r:0)  0@32r
		LHS = %vreg9 [176r,448r:0)  0@176r
		merge %vreg9:0@176r into %vreg8:0@32r --> @32r
		erased:	176r	%vreg9<def> = COPY %vreg8; GR32:%vreg9,%vreg8
		updated: 32B	%vreg9<def> = COPY %R8D; GR32:%vreg9
	Success: %vreg8 -> %vreg9
	Result = %vreg9 [32r,448r:0)  0@32r
192B	%vreg11<def> = COPY %vreg10; GR32:%vreg11,%vreg10
	Considering merging to GR32 with %vreg10 in %vreg11
		RHS = %vreg10 [16r,192r:0)  0@16r
		LHS = %vreg11 [192r,464r:0)  0@192r
		merge %vreg11:0@192r into %vreg10:0@16r --> @16r
		erased:	192r	%vreg11<def> = COPY %vreg10; GR32:%vreg11,%vreg10
		updated: 16B	%vreg11<def> = COPY %R9D; GR32:%vreg11
	Success: %vreg10 -> %vreg11
	Result = %vreg11 [16r,464r:0)  0@16r
224B	%vreg14<def> = COPY %vreg13; GR64:%vreg14,%vreg13
	Considering merging to GR64 with %vreg13 in %vreg14
		RHS = %vreg13 [208r,224r:0)  0@208r
		LHS = %vreg14 [224r,272r:0)  0@224r
		merge %vreg14:0@224r into %vreg13:0@208r --> @208r
		erased:	224r	%vreg14<def> = COPY %vreg13; GR64:%vreg14,%vreg13
		updated: 208B	%vreg14<def> = MOV64ri <ga:@BZ2_bzBuffToBuffDecompress>; GR64:%vreg14
	Success: %vreg13 -> %vreg14
	Result = %vreg14 [208r,272r:0)  0@208r
1776B	%vreg51<def> = COPY %vreg52; GR32:%vreg51,%vreg52
	Considering merging to GR32 with %vreg52 in %vreg51
		RHS = %vreg52 [1760r,1776r:0)  0@1760r
		LHS = %vreg51 [1776r,1792r:0)[1792r,1808r:1)  0@1776r 1@1792r
		merge %vreg51:0@1776r into %vreg52:0@1760r --> @1760r
		erased:	1776r	%vreg51<def> = COPY %vreg52; GR32:%vreg51,%vreg52
		updated: 1760B	%vreg51<def> = MOV32rm %vreg53, 1, %noreg, 0, %noreg; mem:LD4[%19] GR32:%vreg51 GR64:%vreg53
	Success: %vreg52 -> %vreg51
	Result = %vreg51 [1760r,1792r:0)[1792r,1808r:1)  0@1760r 1@1792r
2688B	%RDI<def> = COPY %vreg69; GR64:%vreg69
	Considering merging %vreg69 with %RDI
	Can only merge into reserved registers.
272B	%RDI<def> = COPY %vreg14; GR64:%vreg14
	Considering merging %vreg14 with %RDI
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
CH [0B,48r:0)  0@0B-phi
CL [0B,48r:0)  0@0B-phi
DH [0B,64r:0)[1008r,1024r:1)  0@0B-phi 1@1008r
DIL [0B,96r:0)[272r,304r:8)[976r,1024r:7)[1424r,1440r:6)[1840r,1856r:5)[2080r,2096r:2)[2272r,2288r:3)[2464r,2480r:4)[2688r,2720r:1)  0@0B-phi 1@2688r 2@2080r 3@2272r 4@2464r 5@1840r 6@1424r 7@976r 8@272r
DL [0B,64r:0)[1008r,1024r:1)  0@0B-phi 1@1008r
SIL [0B,80r:0)[288r,304r:3)[992r,1024r:1)[2704r,2720r:2)  0@0B-phi 1@992r 2@2704r 3@288r
R8B [0B,32r:0)  0@0B-phi
R9B [0B,16r:0)  0@0B-phi
%vreg1 [96r,384r:0)  0@96r
%vreg3 [80r,400r:0)  0@80r
%vreg5 [64r,416r:0)  0@64r
%vreg7 [48r,432r:0)  0@48r
%vreg9 [32r,448r:0)  0@32r
%vreg11 [16r,464r:0)  0@16r
%vreg14 [208r,272r:0)  0@208r
%vreg15 [240r,288r:0)  0@240r
%vreg24 [864r,976r:0)  0@864r
%vreg27 [1056r,1120r:0)  0@1056r
%vreg28 [944r,1008r:0)  0@944r
%vreg29 [928r,992r:0)  0@928r
%vreg32 [1248r,1424r:0)  0@1248r
%vreg33 [1472r,1536r:0)  0@1472r
%vreg36 [1376r,1392r:0)  0@1376r
%vreg37 [1360r,1376r:0)  0@1360r
%vreg39 [1328r,1344r:0)  0@1328r
%vreg41 [1296r,1312r:0)  0@1296r
%vreg43 [1264r,1280r:0)  0@1264r
%vreg45 [1712r,1840r:0)  0@1712r
%vreg46 [1888r,1888d:0)  0@1888r
%vreg51 [1760r,1792r:0)[1792r,1808r:1)  0@1760r 1@1792r
%vreg53 [1744r,1808r:0)  0@1744r
%vreg54 [1728r,1792r:0)  0@1728r
%vreg56 [2576r,2592r:0)  0@2576r
%vreg57 [2432r,2464r:0)  0@2432r
%vreg58 [2512r,2512d:0)  0@2512r
%vreg60 [2240r,2272r:0)  0@2240r
%vreg61 [2320r,2320d:0)  0@2320r
%vreg62 [2048r,2080r:0)  0@2048r
%vreg63 [2128r,2128d:0)  0@2128r
%vreg65 [1184r,1200r:0)  0@1184r
%vreg67 [2800r,2816r:0)  0@2800r
%vreg69 [2624r,2688r:0)  0@2624r
%vreg70 [2656r,2704r:0)  0@2656r
RegMasks: 304r 1024r 1440r 1856r 2096r 2288r 2480r 2720r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzBuffToBuffDecompress: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=4, align=4, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=8, align=8, at location [SP+8]
  fi#3: size=8, align=8, at location [SP+8]
  fi#4: size=4, align=4, at location [SP+8]
  fi#5: size=4, align=4, at location [SP+8]
  fi#6: size=4, align=4, at location [SP+8]
  fi#7: size=80, align=8, at location [SP+8]
  fi#8: size=4, align=4, at location [SP+8]
Function Live Ins: %RDI in %vreg0, %RSI in %vreg2, %RDX in %vreg4, %ECX in %vreg6, %R8D in %vreg8, %R9D in %vreg10

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI %RSI %RDX %ECX %R8D %R9D
16B		%vreg11<def> = COPY %R9D; GR32:%vreg11
32B		%vreg9<def> = COPY %R8D; GR32:%vreg9
48B		%vreg7<def> = COPY %ECX; GR32:%vreg7
64B		%vreg5<def> = COPY %RDX; GR64:%vreg5
80B		%vreg3<def> = COPY %RSI; GR64:%vreg3
96B		%vreg1<def> = COPY %RDI; GR64:%vreg1
208B		%vreg14<def> = MOV64ri <ga:@BZ2_bzBuffToBuffDecompress>; GR64:%vreg14
240B		%vreg15<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg15
256B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
272B		%RDI<def> = COPY %vreg14; GR64:%vreg14
288B		%RSI<def> = COPY %vreg15; GR64:%vreg15
304B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
320B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
336B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
352B		STACKMAP 0, 0, %vreg1, 0, <fi#1>, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, %vreg9, 0, <fi#5>, 0, %vreg5, 0, <fi#3>, 0, %vreg7, 0, <fi#4>, 0, 0, <fi#7>, 0, %vreg11, 0, <fi#6>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack8](align=4) LD8[FixedStack0](align=4) LD8[FixedStack5](align=4) LD8[FixedStack3] LD8[FixedStack4](align=4) LD8[FixedStack7] LD8[FixedStack6](align=4) GR64:%vreg1,%vreg3,%vreg5 GR32:%vreg9,%vreg7,%vreg11
368B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
384B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%dest.addr] GR64:%vreg1
400B		MOV64mr <fi#2>, 1, %noreg, 0, %noreg, %vreg3; mem:ST8[%destLen.addr] GR64:%vreg3
416B		MOV64mr <fi#3>, 1, %noreg, 0, %noreg, %vreg5; mem:ST8[%source.addr] GR64:%vreg5
432B		MOV32mr <fi#4>, 1, %noreg, 0, %noreg, %vreg7; mem:ST4[%sourceLen.addr] GR32:%vreg7
448B		MOV32mr <fi#5>, 1, %noreg, 0, %noreg, %vreg9; mem:ST4[%small.addr] GR32:%vreg9
464B		MOV32mr <fi#6>, 1, %noreg, 0, %noreg, %vreg11; mem:ST4[%verbosity.addr] GR32:%vreg11
480B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%dest.addr]
496B		JE_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#1

512B	BB#1: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#0
528B		CMP64mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%destLen.addr]
544B		JE_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#2

560B	BB#2: derived from LLVM BB %lor.lhs.false.2
	    Predecessors according to CFG: BB#1
576B		CMP64mi8 <fi#3>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%source.addr]
592B		JE_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#3

608B	BB#3: derived from LLVM BB %lor.lhs.false.4
	    Predecessors according to CFG: BB#2
624B		CMP32mi8 <fi#5>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%small.addr]
640B		JE_1 <BB#5>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#5 BB#4

656B	BB#4: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#3
672B		CMP32mi8 <fi#5>, 1, %noreg, 0, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%small.addr]
688B		JNE_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#5

704B	BB#5: derived from LLVM BB %lor.lhs.false.7
	    Predecessors according to CFG: BB#3 BB#4
720B		CMP32mi8 <fi#6>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%verbosity.addr]
736B		JL_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#6

752B	BB#6: derived from LLVM BB %lor.lhs.false.9
	    Predecessors according to CFG: BB#5
768B		CMP32mi8 <fi#6>, 1, %noreg, 0, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%verbosity.addr]
784B		JLE_1 <BB#8>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#8 BB#7

800B	BB#7: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0 BB#1 BB#2 BB#4 BB#5 BB#6
816B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
832B		JMP_1 <BB#19>
	    Successors according to CFG: BB#19

848B	BB#8: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#6
864B		%vreg24<def> = LEA64r <fi#7>, 1, %noreg, 0, %noreg; GR64:%vreg24
880B		MOV64mi32 <fi#7>, 1, %noreg, 56, %noreg, 0; mem:ST8[%bzalloc]
896B		MOV64mi32 <fi#7>, 1, %noreg, 64, %noreg, 0; mem:ST8[%bzfree]
912B		MOV64mi32 <fi#7>, 1, %noreg, 72, %noreg, 0; mem:ST8[%opaque]
928B		%vreg29<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%verbosity.addr] GR32:%vreg29
944B		%vreg28<def> = MOV32rm <fi#5>, 1, %noreg, 0, %noreg; mem:LD4[%small.addr] GR32:%vreg28
960B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
976B		%RDI<def> = COPY %vreg24; GR64:%vreg24
992B		%ESI<def> = COPY %vreg29; GR32:%vreg29
1008B		%EDX<def> = COPY %vreg28; GR32:%vreg28
1024B		CALL64pcrel32 <ga:@BZ2_bzDecompressInit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %EDX<imp-use>, %EAX<imp-def>
1040B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1056B		%vreg27<def> = COPY %EAX<kill>; GR32:%vreg27
1072B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1088B		STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, 0, <fi#7>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack8](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3] LD8[FixedStack4](align=4) LD8[FixedStack7]
1104B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1120B		MOV32mr <fi#8>, 1, %noreg, 0, %noreg, %vreg27; mem:ST4[%ret] GR32:%vreg27
1136B		CMP32mi8 <fi#8>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%ret]
1152B		JE_1 <BB#10>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#10 BB#9

1168B	BB#9: derived from LLVM BB %if.then.12
	    Predecessors according to CFG: BB#8
1184B		%vreg65<def> = MOV32rm <fi#8>, 1, %noreg, 0, %noreg; mem:LD4[%ret] GR32:%vreg65
1200B		MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %vreg65; mem:ST4[%retval] GR32:%vreg65
1216B		JMP_1 <BB#19>
	    Successors according to CFG: BB#19

1232B	BB#10: derived from LLVM BB %if.end.13
	    Predecessors according to CFG: BB#8
1248B		%vreg32<def> = LEA64r <fi#7>, 1, %noreg, 0, %noreg; GR64:%vreg32
1264B		%vreg43<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%source.addr] GR64:%vreg43
1280B		MOV64mr <fi#7>, 1, %noreg, 0, %noreg, %vreg43; mem:ST8[%next_in] GR64:%vreg43
1296B		%vreg41<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%dest.addr] GR64:%vreg41
1312B		MOV64mr <fi#7>, 1, %noreg, 24, %noreg, %vreg41; mem:ST8[%next_out] GR64:%vreg41
1328B		%vreg39<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%sourceLen.addr] GR32:%vreg39
1344B		MOV32mr <fi#7>, 1, %noreg, 8, %noreg, %vreg39; mem:ST4[%avail_in] GR32:%vreg39
1360B		%vreg37<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%destLen.addr] GR64:%vreg37
1376B		%vreg36<def> = MOV32rm %vreg37, 1, %noreg, 0, %noreg; mem:LD4[%14] GR32:%vreg36 GR64:%vreg37
1392B		MOV32mr <fi#7>, 1, %noreg, 32, %noreg, %vreg36; mem:ST4[%avail_out] GR32:%vreg36
1408B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1424B		%RDI<def> = COPY %vreg32; GR64:%vreg32
1440B		CALL64pcrel32 <ga:@BZ2_bzDecompress>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
1456B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1472B		%vreg33<def> = COPY %EAX<kill>; GR32:%vreg33
1488B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1504B		STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, 0, <fi#7>, 0, ...; mem:LD8[FixedStack2] LD8[FixedStack8](align=4) LD8[FixedStack0](align=4) LD8[FixedStack7]
1520B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1536B		MOV32mr <fi#8>, 1, %noreg, 0, %noreg, %vreg33; mem:ST4[%ret] GR32:%vreg33
1552B		CMP32mi8 <fi#8>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%ret]
1568B		JNE_1 <BB#12>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#12 BB#11

1584B	BB#11: derived from LLVM BB %if.then.16
	    Predecessors according to CFG: BB#10
1600B		JMP_1 <BB#15>
	    Successors according to CFG: BB#15

1616B	BB#12: derived from LLVM BB %if.end.17
	    Predecessors according to CFG: BB#10
1632B		CMP32mi8 <fi#8>, 1, %noreg, 0, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%ret]
1648B		JE_1 <BB#14>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#14 BB#13

1664B	BB#13: derived from LLVM BB %if.then.19
	    Predecessors according to CFG: BB#12
1680B		JMP_1 <BB#18>
	    Successors according to CFG: BB#18

1696B	BB#14: derived from LLVM BB %if.end.20
	    Predecessors according to CFG: BB#12
1712B		%vreg45<def> = LEA64r <fi#7>, 1, %noreg, 0, %noreg; GR64:%vreg45
1728B		%vreg54<def> = MOV32rm <fi#7>, 1, %noreg, 32, %noreg; mem:LD4[%avail_out21] GR32:%vreg54
1744B		%vreg53<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%destLen.addr] GR64:%vreg53
1760B		%vreg51<def> = MOV32rm %vreg53, 1, %noreg, 0, %noreg; mem:LD4[%19] GR32:%vreg51 GR64:%vreg53
1792B		%vreg51<def,tied1> = SUB32rr %vreg51<tied0>, %vreg54, %EFLAGS<imp-def,dead>; GR32:%vreg51,%vreg54
1808B		MOV32mr %vreg53, 1, %noreg, 0, %noreg, %vreg51; mem:ST4[%19] GR64:%vreg53 GR32:%vreg51
1824B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1840B		%RDI<def> = COPY %vreg45; GR64:%vreg45
1856B		CALL64pcrel32 <ga:@BZ2_bzDecompressEnd>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
1872B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1888B		%vreg46<def,dead> = COPY %EAX<kill>; GR32:%vreg46
1904B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1920B		STACKMAP 3, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
1936B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1952B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
1968B		JMP_1 <BB#19>
	    Successors according to CFG: BB#19

1984B	BB#15: derived from LLVM BB %output_overflow_or_eof
	    Predecessors according to CFG: BB#11
2000B		CMP32mi8 <fi#7>, 1, %noreg, 32, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_out23]
2016B		JBE_1 <BB#17>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#17 BB#16

2032B	BB#16: derived from LLVM BB %if.then.25
	    Predecessors according to CFG: BB#15
2048B		%vreg62<def> = LEA64r <fi#7>, 1, %noreg, 0, %noreg; GR64:%vreg62
2064B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2080B		%RDI<def> = COPY %vreg62; GR64:%vreg62
2096B		CALL64pcrel32 <ga:@BZ2_bzDecompressEnd>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
2112B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2128B		%vreg63<def,dead> = COPY %EAX<kill>; GR32:%vreg63
2144B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2160B		STACKMAP 4, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
2176B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2192B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -7; mem:ST4[%retval]
2208B		JMP_1 <BB#19>
	    Successors according to CFG: BB#19

2224B	BB#17: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#15
2240B		%vreg60<def> = LEA64r <fi#7>, 1, %noreg, 0, %noreg; GR64:%vreg60
2256B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2272B		%RDI<def> = COPY %vreg60; GR64:%vreg60
2288B		CALL64pcrel32 <ga:@BZ2_bzDecompressEnd>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
2304B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2320B		%vreg61<def,dead> = COPY %EAX<kill>; GR32:%vreg61
2336B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2352B		STACKMAP 5, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
2368B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2384B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -8; mem:ST4[%retval]
2400B		JMP_1 <BB#19>
	    Successors according to CFG: BB#19

2416B	BB#18: derived from LLVM BB %errhandler
	    Predecessors according to CFG: BB#13
2432B		%vreg57<def> = LEA64r <fi#7>, 1, %noreg, 0, %noreg; GR64:%vreg57
2448B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2464B		%RDI<def> = COPY %vreg57; GR64:%vreg57
2480B		CALL64pcrel32 <ga:@BZ2_bzDecompressEnd>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
2496B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2512B		%vreg58<def,dead> = COPY %EAX<kill>; GR32:%vreg58
2528B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2544B		STACKMAP 6, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack8](align=4) LD8[FixedStack0](align=4)
2560B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2576B		%vreg56<def> = MOV32rm <fi#8>, 1, %noreg, 0, %noreg; mem:LD4[%ret] GR32:%vreg56
2592B		MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %vreg56; mem:ST4[%retval] GR32:%vreg56
	    Successors according to CFG: BB#19

2608B	BB#19: derived from LLVM BB %return
	    Predecessors according to CFG: BB#14 BB#18 BB#17 BB#16 BB#9 BB#7
2624B		%vreg69<def> = MOV64ri <ga:@BZ2_bzBuffToBuffDecompress>; GR64:%vreg69
2656B		%vreg70<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg70
2672B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2688B		%RDI<def> = COPY %vreg69; GR64:%vreg69
2704B		%RSI<def> = COPY %vreg70; GR64:%vreg70
2720B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
2736B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2752B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2768B		STACKMAP 7, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
2784B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2800B		%vreg67<def> = MOV32rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD4[%retval] GR32:%vreg67
2816B		%EAX<def> = COPY %vreg67; GR32:%vreg67
2832B		RETQ %EAX<imp-use,kill>

# End machine code for function BZ2_bzBuffToBuffDecompress.

AllocationOrder(SEGMENT_REG) = [ ]
AllocationOrder(SEGMENT_REG) = [ ]
********** GREEDY REGISTER ALLOCATION **********
********** Function: BZ2_bzBuffToBuffDecompress
********** INTERVALS **********
CH [0B,48r:0)  0@0B-phi
CL [0B,48r:0)  0@0B-phi
DH [0B,64r:0)[1008r,1024r:1)  0@0B-phi 1@1008r
DIL [0B,96r:0)[272r,304r:8)[976r,1024r:7)[1424r,1440r:6)[1840r,1856r:5)[2080r,2096r:2)[2272r,2288r:3)[2464r,2480r:4)[2688r,2720r:1)  0@0B-phi 1@2688r 2@2080r 3@2272r 4@2464r 5@1840r 6@1424r 7@976r 8@272r
DL [0B,64r:0)[1008r,1024r:1)  0@0B-phi 1@1008r
SIL [0B,80r:0)[288r,304r:3)[992r,1024r:1)[2704r,2720r:2)  0@0B-phi 1@992r 2@2704r 3@288r
R8B [0B,32r:0)  0@0B-phi
R9B [0B,16r:0)  0@0B-phi
%vreg1 [96r,384r:0)  0@96r
%vreg3 [80r,400r:0)  0@80r
%vreg5 [64r,416r:0)  0@64r
%vreg7 [48r,432r:0)  0@48r
%vreg9 [32r,448r:0)  0@32r
%vreg11 [16r,464r:0)  0@16r
%vreg14 [208r,272r:0)  0@208r
%vreg15 [240r,288r:0)  0@240r
%vreg24 [864r,976r:0)  0@864r
%vreg27 [1056r,1120r:0)  0@1056r
%vreg28 [944r,1008r:0)  0@944r
%vreg29 [928r,992r:0)  0@928r
%vreg32 [1248r,1424r:0)  0@1248r
%vreg33 [1472r,1536r:0)  0@1472r
%vreg36 [1376r,1392r:0)  0@1376r
%vreg37 [1360r,1376r:0)  0@1360r
%vreg39 [1328r,1344r:0)  0@1328r
%vreg41 [1296r,1312r:0)  0@1296r
%vreg43 [1264r,1280r:0)  0@1264r
%vreg45 [1712r,1840r:0)  0@1712r
%vreg46 [1888r,1888d:0)  0@1888r
%vreg51 [1760r,1792r:0)[1792r,1808r:1)  0@1760r 1@1792r
%vreg53 [1744r,1808r:0)  0@1744r
%vreg54 [1728r,1792r:0)  0@1728r
%vreg56 [2576r,2592r:0)  0@2576r
%vreg57 [2432r,2464r:0)  0@2432r
%vreg58 [2512r,2512d:0)  0@2512r
%vreg60 [2240r,2272r:0)  0@2240r
%vreg61 [2320r,2320d:0)  0@2320r
%vreg62 [2048r,2080r:0)  0@2048r
%vreg63 [2128r,2128d:0)  0@2128r
%vreg65 [1184r,1200r:0)  0@1184r
%vreg67 [2800r,2816r:0)  0@2800r
%vreg69 [2624r,2688r:0)  0@2624r
%vreg70 [2656r,2704r:0)  0@2656r
RegMasks: 304r 1024r 1440r 1856r 2096r 2288r 2480r 2720r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzBuffToBuffDecompress: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=4, align=4, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=8, align=8, at location [SP+8]
  fi#3: size=8, align=8, at location [SP+8]
  fi#4: size=4, align=4, at location [SP+8]
  fi#5: size=4, align=4, at location [SP+8]
  fi#6: size=4, align=4, at location [SP+8]
  fi#7: size=80, align=8, at location [SP+8]
  fi#8: size=4, align=4, at location [SP+8]
Function Live Ins: %RDI in %vreg0, %RSI in %vreg2, %RDX in %vreg4, %ECX in %vreg6, %R8D in %vreg8, %R9D in %vreg10

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI %RSI %RDX %ECX %R8D %R9D
16B		%vreg11<def> = COPY %R9D; GR32:%vreg11
32B		%vreg9<def> = COPY %R8D; GR32:%vreg9
48B		%vreg7<def> = COPY %ECX; GR32:%vreg7
64B		%vreg5<def> = COPY %RDX; GR64:%vreg5
80B		%vreg3<def> = COPY %RSI; GR64:%vreg3
96B		%vreg1<def> = COPY %RDI; GR64:%vreg1
208B		%vreg14<def> = MOV64ri <ga:@BZ2_bzBuffToBuffDecompress>; GR64:%vreg14
240B		%vreg15<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg15
256B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
272B		%RDI<def> = COPY %vreg14; GR64:%vreg14
288B		%RSI<def> = COPY %vreg15; GR64:%vreg15
304B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
320B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
336B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
352B		STACKMAP 0, 0, %vreg1, 0, <fi#1>, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, %vreg9, 0, <fi#5>, 0, %vreg5, 0, <fi#3>, 0, %vreg7, 0, <fi#4>, 0, 0, <fi#7>, 0, %vreg11, 0, <fi#6>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack8](align=4) LD8[FixedStack0](align=4) LD8[FixedStack5](align=4) LD8[FixedStack3] LD8[FixedStack4](align=4) LD8[FixedStack7] LD8[FixedStack6](align=4) GR64:%vreg1,%vreg3,%vreg5 GR32:%vreg9,%vreg7,%vreg11
368B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
384B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%dest.addr] GR64:%vreg1
400B		MOV64mr <fi#2>, 1, %noreg, 0, %noreg, %vreg3; mem:ST8[%destLen.addr] GR64:%vreg3
416B		MOV64mr <fi#3>, 1, %noreg, 0, %noreg, %vreg5; mem:ST8[%source.addr] GR64:%vreg5
432B		MOV32mr <fi#4>, 1, %noreg, 0, %noreg, %vreg7; mem:ST4[%sourceLen.addr] GR32:%vreg7
448B		MOV32mr <fi#5>, 1, %noreg, 0, %noreg, %vreg9; mem:ST4[%small.addr] GR32:%vreg9
464B		MOV32mr <fi#6>, 1, %noreg, 0, %noreg, %vreg11; mem:ST4[%verbosity.addr] GR32:%vreg11
480B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%dest.addr]
496B		JE_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#1

512B	BB#1: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#0
528B		CMP64mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%destLen.addr]
544B		JE_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#2

560B	BB#2: derived from LLVM BB %lor.lhs.false.2
	    Predecessors according to CFG: BB#1
576B		CMP64mi8 <fi#3>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%source.addr]
592B		JE_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#3

608B	BB#3: derived from LLVM BB %lor.lhs.false.4
	    Predecessors according to CFG: BB#2
624B		CMP32mi8 <fi#5>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%small.addr]
640B		JE_1 <BB#5>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#5 BB#4

656B	BB#4: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#3
672B		CMP32mi8 <fi#5>, 1, %noreg, 0, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%small.addr]
688B		JNE_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#5

704B	BB#5: derived from LLVM BB %lor.lhs.false.7
	    Predecessors according to CFG: BB#3 BB#4
720B		CMP32mi8 <fi#6>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%verbosity.addr]
736B		JL_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#6

752B	BB#6: derived from LLVM BB %lor.lhs.false.9
	    Predecessors according to CFG: BB#5
768B		CMP32mi8 <fi#6>, 1, %noreg, 0, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%verbosity.addr]
784B		JLE_1 <BB#8>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#8 BB#7

800B	BB#7: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0 BB#1 BB#2 BB#4 BB#5 BB#6
816B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
832B		JMP_1 <BB#19>
	    Successors according to CFG: BB#19

848B	BB#8: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#6
864B		%vreg24<def> = LEA64r <fi#7>, 1, %noreg, 0, %noreg; GR64:%vreg24
880B		MOV64mi32 <fi#7>, 1, %noreg, 56, %noreg, 0; mem:ST8[%bzalloc]
896B		MOV64mi32 <fi#7>, 1, %noreg, 64, %noreg, 0; mem:ST8[%bzfree]
912B		MOV64mi32 <fi#7>, 1, %noreg, 72, %noreg, 0; mem:ST8[%opaque]
928B		%vreg29<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%verbosity.addr] GR32:%vreg29
944B		%vreg28<def> = MOV32rm <fi#5>, 1, %noreg, 0, %noreg; mem:LD4[%small.addr] GR32:%vreg28
960B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
976B		%RDI<def> = COPY %vreg24; GR64:%vreg24
992B		%ESI<def> = COPY %vreg29; GR32:%vreg29
1008B		%EDX<def> = COPY %vreg28; GR32:%vreg28
1024B		CALL64pcrel32 <ga:@BZ2_bzDecompressInit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %EDX<imp-use>, %EAX<imp-def>
1040B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1056B		%vreg27<def> = COPY %EAX<kill>; GR32:%vreg27
1072B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1088B		STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, 0, <fi#7>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack8](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3] LD8[FixedStack4](align=4) LD8[FixedStack7]
1104B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1120B		MOV32mr <fi#8>, 1, %noreg, 0, %noreg, %vreg27; mem:ST4[%ret] GR32:%vreg27
1136B		CMP32mi8 <fi#8>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%ret]
1152B		JE_1 <BB#10>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#10 BB#9

1168B	BB#9: derived from LLVM BB %if.then.12
	    Predecessors according to CFG: BB#8
1184B		%vreg65<def> = MOV32rm <fi#8>, 1, %noreg, 0, %noreg; mem:LD4[%ret] GR32:%vreg65
1200B		MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %vreg65; mem:ST4[%retval] GR32:%vreg65
1216B		JMP_1 <BB#19>
	    Successors according to CFG: BB#19

1232B	BB#10: derived from LLVM BB %if.end.13
	    Predecessors according to CFG: BB#8
1248B		%vreg32<def> = LEA64r <fi#7>, 1, %noreg, 0, %noreg; GR64:%vreg32
1264B		%vreg43<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%source.addr] GR64:%vreg43
1280B		MOV64mr <fi#7>, 1, %noreg, 0, %noreg, %vreg43; mem:ST8[%next_in] GR64:%vreg43
1296B		%vreg41<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%dest.addr] GR64:%vreg41
1312B		MOV64mr <fi#7>, 1, %noreg, 24, %noreg, %vreg41; mem:ST8[%next_out] GR64:%vreg41
1328B		%vreg39<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%sourceLen.addr] GR32:%vreg39
1344B		MOV32mr <fi#7>, 1, %noreg, 8, %noreg, %vreg39; mem:ST4[%avail_in] GR32:%vreg39
1360B		%vreg37<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%destLen.addr] GR64:%vreg37
1376B		%vreg36<def> = MOV32rm %vreg37, 1, %noreg, 0, %noreg; mem:LD4[%14] GR32:%vreg36 GR64:%vreg37
1392B		MOV32mr <fi#7>, 1, %noreg, 32, %noreg, %vreg36; mem:ST4[%avail_out] GR32:%vreg36
1408B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1424B		%RDI<def> = COPY %vreg32; GR64:%vreg32
1440B		CALL64pcrel32 <ga:@BZ2_bzDecompress>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
1456B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1472B		%vreg33<def> = COPY %EAX<kill>; GR32:%vreg33
1488B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1504B		STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, 0, <fi#7>, 0, ...; mem:LD8[FixedStack2] LD8[FixedStack8](align=4) LD8[FixedStack0](align=4) LD8[FixedStack7]
1520B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1536B		MOV32mr <fi#8>, 1, %noreg, 0, %noreg, %vreg33; mem:ST4[%ret] GR32:%vreg33
1552B		CMP32mi8 <fi#8>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%ret]
1568B		JNE_1 <BB#12>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#12 BB#11

1584B	BB#11: derived from LLVM BB %if.then.16
	    Predecessors according to CFG: BB#10
1600B		JMP_1 <BB#15>
	    Successors according to CFG: BB#15

1616B	BB#12: derived from LLVM BB %if.end.17
	    Predecessors according to CFG: BB#10
1632B		CMP32mi8 <fi#8>, 1, %noreg, 0, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%ret]
1648B		JE_1 <BB#14>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#14 BB#13

1664B	BB#13: derived from LLVM BB %if.then.19
	    Predecessors according to CFG: BB#12
1680B		JMP_1 <BB#18>
	    Successors according to CFG: BB#18

1696B	BB#14: derived from LLVM BB %if.end.20
	    Predecessors according to CFG: BB#12
1712B		%vreg45<def> = LEA64r <fi#7>, 1, %noreg, 0, %noreg; GR64:%vreg45
1728B		%vreg54<def> = MOV32rm <fi#7>, 1, %noreg, 32, %noreg; mem:LD4[%avail_out21] GR32:%vreg54
1744B		%vreg53<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%destLen.addr] GR64:%vreg53
1760B		%vreg51<def> = MOV32rm %vreg53, 1, %noreg, 0, %noreg; mem:LD4[%19] GR32:%vreg51 GR64:%vreg53
1792B		%vreg51<def,tied1> = SUB32rr %vreg51<tied0>, %vreg54, %EFLAGS<imp-def,dead>; GR32:%vreg51,%vreg54
1808B		MOV32mr %vreg53, 1, %noreg, 0, %noreg, %vreg51; mem:ST4[%19] GR64:%vreg53 GR32:%vreg51
1824B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1840B		%RDI<def> = COPY %vreg45; GR64:%vreg45
1856B		CALL64pcrel32 <ga:@BZ2_bzDecompressEnd>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
1872B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1888B		%vreg46<def,dead> = COPY %EAX<kill>; GR32:%vreg46
1904B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1920B		STACKMAP 3, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
1936B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1952B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
1968B		JMP_1 <BB#19>
	    Successors according to CFG: BB#19

1984B	BB#15: derived from LLVM BB %output_overflow_or_eof
	    Predecessors according to CFG: BB#11
2000B		CMP32mi8 <fi#7>, 1, %noreg, 32, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_out23]
2016B		JBE_1 <BB#17>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#17 BB#16

2032B	BB#16: derived from LLVM BB %if.then.25
	    Predecessors according to CFG: BB#15
2048B		%vreg62<def> = LEA64r <fi#7>, 1, %noreg, 0, %noreg; GR64:%vreg62
2064B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2080B		%RDI<def> = COPY %vreg62; GR64:%vreg62
2096B		CALL64pcrel32 <ga:@BZ2_bzDecompressEnd>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
2112B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2128B		%vreg63<def,dead> = COPY %EAX<kill>; GR32:%vreg63
2144B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2160B		STACKMAP 4, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
2176B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2192B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -7; mem:ST4[%retval]
2208B		JMP_1 <BB#19>
	    Successors according to CFG: BB#19

2224B	BB#17: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#15
2240B		%vreg60<def> = LEA64r <fi#7>, 1, %noreg, 0, %noreg; GR64:%vreg60
2256B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2272B		%RDI<def> = COPY %vreg60; GR64:%vreg60
2288B		CALL64pcrel32 <ga:@BZ2_bzDecompressEnd>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
2304B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2320B		%vreg61<def,dead> = COPY %EAX<kill>; GR32:%vreg61
2336B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2352B		STACKMAP 5, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
2368B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2384B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -8; mem:ST4[%retval]
2400B		JMP_1 <BB#19>
	    Successors according to CFG: BB#19

2416B	BB#18: derived from LLVM BB %errhandler
	    Predecessors according to CFG: BB#13
2432B		%vreg57<def> = LEA64r <fi#7>, 1, %noreg, 0, %noreg; GR64:%vreg57
2448B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2464B		%RDI<def> = COPY %vreg57; GR64:%vreg57
2480B		CALL64pcrel32 <ga:@BZ2_bzDecompressEnd>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
2496B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2512B		%vreg58<def,dead> = COPY %EAX<kill>; GR32:%vreg58
2528B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2544B		STACKMAP 6, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack8](align=4) LD8[FixedStack0](align=4)
2560B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2576B		%vreg56<def> = MOV32rm <fi#8>, 1, %noreg, 0, %noreg; mem:LD4[%ret] GR32:%vreg56
2592B		MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %vreg56; mem:ST4[%retval] GR32:%vreg56
	    Successors according to CFG: BB#19

2608B	BB#19: derived from LLVM BB %return
	    Predecessors according to CFG: BB#14 BB#18 BB#17 BB#16 BB#9 BB#7
2624B		%vreg69<def> = MOV64ri <ga:@BZ2_bzBuffToBuffDecompress>; GR64:%vreg69
2656B		%vreg70<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg70
2672B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2688B		%RDI<def> = COPY %vreg69; GR64:%vreg69
2704B		%RSI<def> = COPY %vreg70; GR64:%vreg70
2720B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
2736B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2752B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2768B		STACKMAP 7, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
2784B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2800B		%vreg67<def> = MOV32rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD4[%retval] GR32:%vreg67
2816B		%EAX<def> = COPY %vreg67; GR32:%vreg67
2832B		RETQ %EAX<imp-use,kill>

# End machine code for function BZ2_bzBuffToBuffDecompress.


selectOrSplit GR32:%vreg11 [16r,464r:0)  0@16r w=3.573113e-03
hints: %R9D
missed hint %R9D
assigning %vreg11 to %EBX: BH [16r,464r:0)  0@16r BL [16r,464r:0)  0@16r

selectOrSplit GR32:%vreg9 [32r,448r:0)  0@32r w=3.713235e-03
hints: %R8D
missed hint %R8D
%R14D is available at cost 1
Only trying the first 10 regs.
should evict: %vreg11 [16r,464r:0)  0@16r w= 3.573113e-03
hints: %R9D
can reassign: %vreg11 [16r,464r:0)  0@16r from %EBX to %R9D
should evict: %vreg11 [16r,464r:0)  0@16r w= 3.573113e-03
hints: %R9D
can reassign: %vreg11 [16r,464r:0)  0@16r from %EBX to %R9D
evicting %EBX interference: Cascade 1
unassigning %vreg11 from %EBX: BH BL
assigning %vreg9 to %EBX: BH [32r,448r:0)  0@32r BL [32r,448r:0)  0@32r
queuing new interval: %vreg11 [16r,464r:0)  0@16r

selectOrSplit GR32:%vreg11 [16r,464r:0)  0@16r w=3.573113e-03
hints: %R9D
missed hint %R9D
%R14D is available at cost 1
Only trying the first 10 regs.
assigning %vreg11 to %R14D: R14B [16r,464r:0)  0@16r

selectOrSplit GR32:%vreg7 [48r,432r:0)  0@48r w=3.864796e-03
hints: %ECX
missed hint %ECX
%R15D is available at cost 1
Only trying the first 10 regs.
should evict: %vreg9 [32r,448r:0)  0@32r w= 3.713235e-03
hints: %R8D
can reassign: %vreg9 [32r,448r:0)  0@32r from %EBX to %R8D
should evict: %vreg9 [32r,448r:0)  0@32r w= 3.713235e-03
hints: %R8D
can reassign: %vreg9 [32r,448r:0)  0@32r from %EBX to %R8D
evicting %EBX interference: Cascade 2
unassigning %vreg9 from %EBX: BH BL
assigning %vreg7 to %EBX: BH [48r,432r:0)  0@48r BL [48r,432r:0)  0@48r
queuing new interval: %vreg9 [32r,448r:0)  0@32r

selectOrSplit GR32:%vreg9 [32r,448r:0)  0@32r w=3.713235e-03
hints: %R8D
missed hint %R8D
%R15D is available at cost 1
Only trying the first 10 regs.
assigning %vreg9 to %R15D: R15B [32r,448r:0)  0@32r

selectOrSplit GR64:%vreg5 [64r,416r:0)  0@64r w=4.029255e-03
hints: %RDX
missed hint %RDX
%R12 is available at cost 1
Only trying the first 10 regs.
should evict: %vreg7 [48r,432r:0)  0@48r w= 3.864796e-03
hints: %ECX
can reassign: %vreg7 [48r,432r:0)  0@48r from %RBX to %ECX
should evict: %vreg7 [48r,432r:0)  0@48r w= 3.864796e-03
hints: %ECX
can reassign: %vreg7 [48r,432r:0)  0@48r from %RBX to %ECX
evicting %RBX interference: Cascade 3
unassigning %vreg7 from %EBX: BH BL
assigning %vreg5 to %RBX: BH [64r,416r:0)  0@64r BL [64r,416r:0)  0@64r
queuing new interval: %vreg7 [48r,432r:0)  0@48r

selectOrSplit GR32:%vreg7 [48r,432r:0)  0@48r w=3.864796e-03
hints: %ECX
missed hint %ECX
%R12D is available at cost 1
Only trying the first 10 regs.
assigning %vreg7 to %R12D: R12B [48r,432r:0)  0@48r

selectOrSplit GR64:%vreg3 [80r,400r:0)  0@80r w=4.208333e-03
hints: %RSI
missed hint %RSI
%R13 is available at cost 1
Only trying the first 10 regs.
should evict: %vreg5 [64r,416r:0)  0@64r w= 4.029255e-03
hints: %RDX
can reassign: %vreg5 [64r,416r:0)  0@64r from %RBX to %RDX
should evict: %vreg5 [64r,416r:0)  0@64r w= 4.029255e-03
hints: %RDX
can reassign: %vreg5 [64r,416r:0)  0@64r from %RBX to %RDX
evicting %RBX interference: Cascade 4
unassigning %vreg5 from %RBX: BH BL
assigning %vreg3 to %RBX: BH [80r,400r:0)  0@80r BL [80r,400r:0)  0@80r
queuing new interval: %vreg5 [64r,416r:0)  0@64r

selectOrSplit GR64:%vreg5 [64r,416r:0)  0@64r w=4.029255e-03
hints: %RDX
missed hint %RDX
%R13 is available at cost 1
Only trying the first 10 regs.
assigning %vreg5 to %R13: R13B [64r,416r:0)  0@64r

selectOrSplit GR64:%vreg1 [96r,384r:0)  0@96r w=4.404070e-03
hints: %RDI
RS_Assign Cascade 0
should evict: %vreg3 [80r,400r:0)  0@80r w= 4.208333e-03
should evict: %vreg3 [80r,400r:0)  0@80r w= 4.208333e-03
should evict: %vreg11 [16r,464r:0)  0@16r w= 3.573113e-03
hints: %R9D
can reassign: %vreg11 [16r,464r:0)  0@16r from %R14 to %R9D
evicting %R14 interference: Cascade 5
unassigning %vreg11 from %R14D: R14B
assigning %vreg1 to %R14: R14B [96r,384r:0)  0@96r
queuing new interval: %vreg11 [16r,464r:0)  0@16r

selectOrSplit GR32:%vreg11 [16r,464r:0)  0@16r w=3.573113e-03
hints: %R9D
RS_Assign Cascade 5
wait for second round
queuing new interval: %vreg11 [16r,464r:0)  0@16r

selectOrSplit GR64:%vreg14 [208r,272r:0)  0@208r w=2.176724e-03
hints: %RDI
assigning %vreg14 to %RDI: DIL [208r,272r:0)  0@208r

selectOrSplit GR64:%vreg15 [240r,288r:0)  0@240r w=4.508928e-03
hints: %RSI
assigning %vreg15 to %RSI: SIL [240r,288r:0)  0@240r

selectOrSplit GR64:%vreg24 [864r,976r:0)  0@864r w=4.552284e-05
hints: %RDI
assigning %vreg24 to %RDI: DIL [864r,976r:0)  0@864r

selectOrSplit GR32:%vreg29 [928r,992r:0)  0@928r w=1.004642e-04
hints: %ESI
assigning %vreg29 to %ESI: SIL [928r,992r:0)  0@928r

selectOrSplit GR32:%vreg28 [944r,1008r:0)  0@944r w=1.004642e-04
hints: %EDX
assigning %vreg28 to %EDX: DH [944r,1008r:0)  0@944r DL [944r,1008r:0)  0@944r

selectOrSplit GR32:%vreg27 [1056r,1120r:0)  0@1056r w=1.004642e-04
hints: %EAX
assigning %vreg27 to %EAX: AH [1056r,1120r:0)  0@1056r AL [1056r,1120r:0)  0@1056r

selectOrSplit GR64:%vreg32 [1248r,1424r:0)  0@1248r w=1.991122e-05
hints: %RDI
assigning %vreg32 to %RDI: DIL [1248r,1424r:0)  0@1248r

selectOrSplit GR32:%vreg33 [1472r,1536r:0)  0@1472r w=4.943476e-05
hints: %EAX
assigning %vreg33 to %EAX: AH [1472r,1536r:0)  0@1472r AL [1472r,1536r:0)  0@1472r

selectOrSplit GR64:%vreg45 [1712r,1840r:0)  0@1712r w=5.605506e-06
hints: %RDI
assigning %vreg45 to %RDI: DIL [1712r,1840r:0)  0@1712r

selectOrSplit GR32:%vreg46 [1888r,1888d:0)  0@1888r w=inf
hints: %EAX
assigning %vreg46 to %EAX: AH [1888r,1888d:0)  0@1888r AL [1888r,1888d:0)  0@1888r

selectOrSplit GR64:%vreg62 [2048r,2080r:0)  0@2048r w=6.851174e-06
hints: %RDI
assigning %vreg62 to %RDI: DIL [2048r,2080r:0)  0@2048r

selectOrSplit GR32:%vreg63 [2128r,2128d:0)  0@2128r w=inf
hints: %EAX
assigning %vreg63 to %EAX: AH [2128r,2128d:0)  0@2128r AL [2128r,2128d:0)  0@2128r

selectOrSplit GR64:%vreg60 [2240r,2272r:0)  0@2240r w=6.851174e-06
hints: %RDI
assigning %vreg60 to %RDI: DIL [2240r,2272r:0)  0@2240r

selectOrSplit GR32:%vreg61 [2320r,2320d:0)  0@2320r w=inf
hints: %EAX
assigning %vreg61 to %EAX: AH [2320r,2320d:0)  0@2320r AL [2320r,2320d:0)  0@2320r

selectOrSplit GR64:%vreg57 [2432r,2464r:0)  0@2432r w=6.851174e-06
hints: %RDI
assigning %vreg57 to %RDI: DIL [2432r,2464r:0)  0@2432r

selectOrSplit GR32:%vreg58 [2512r,2512d:0)  0@2512r w=inf
hints: %EAX
assigning %vreg58 to %EAX: AH [2512r,2512d:0)  0@2512r AL [2512r,2512d:0)  0@2512r

selectOrSplit GR64:%vreg69 [2624r,2688r:0)  0@2624r w=2.176724e-03
hints: %RDI
assigning %vreg69 to %RDI: DIL [2624r,2688r:0)  0@2624r

selectOrSplit GR64:%vreg70 [2656r,2704r:0)  0@2656r w=4.508928e-03
hints: %RSI
assigning %vreg70 to %RSI: SIL [2656r,2704r:0)  0@2656r

selectOrSplit GR32:%vreg67 [2800r,2816r:0)  0@2800r w=inf
hints: %EAX
assigning %vreg67 to %EAX: AH [2800r,2816r:0)  0@2800r AL [2800r,2816r:0)  0@2800r

selectOrSplit GR32:%vreg65 [1184r,1200r:0)  0@1184r w=inf
assigning %vreg65 to %EAX: AH [1184r,1200r:0)  0@1184r AL [1184r,1200r:0)  0@1184r

selectOrSplit GR64:%vreg43 [1264r,1280r:0)  0@1264r w=inf
assigning %vreg43 to %RAX: AH [1264r,1280r:0)  0@1264r AL [1264r,1280r:0)  0@1264r

selectOrSplit GR64:%vreg41 [1296r,1312r:0)  0@1296r w=inf
assigning %vreg41 to %RAX: AH [1296r,1312r:0)  0@1296r AL [1296r,1312r:0)  0@1296r

selectOrSplit GR32:%vreg39 [1328r,1344r:0)  0@1328r w=inf
assigning %vreg39 to %EAX: AH [1328r,1344r:0)  0@1328r AL [1328r,1344r:0)  0@1328r

selectOrSplit GR64:%vreg37 [1360r,1376r:0)  0@1360r w=inf
assigning %vreg37 to %RAX: AH [1360r,1376r:0)  0@1360r AL [1360r,1376r:0)  0@1360r

selectOrSplit GR32:%vreg36 [1376r,1392r:0)  0@1376r w=inf
assigning %vreg36 to %EAX: AH [1376r,1392r:0)  0@1376r AL [1376r,1392r:0)  0@1376r

selectOrSplit GR32:%vreg54 [1728r,1792r:0)  0@1728r w=1.263105e-05
assigning %vreg54 to %EAX: AH [1728r,1792r:0)  0@1728r AL [1728r,1792r:0)  0@1728r

selectOrSplit GR64:%vreg53 [1744r,1808r:0)  0@1744r w=1.894657e-05
assigning %vreg53 to %RCX: CH [1744r,1808r:0)  0@1744r CL [1744r,1808r:0)  0@1744r

selectOrSplit GR32:%vreg51 [1760r,1792r:0)[1792r,1808r:1)  0@1760r 1@1792r w=inf
assigning %vreg51 to %EDX: DH [1760r,1792r:0)[1792r,1808r:1)  0@1760r 1@1792r DL [1760r,1792r:0)[1792r,1808r:1)  0@1760r 1@1792r

selectOrSplit GR32:%vreg56 [2576r,2592r:0)  0@2576r w=inf
assigning %vreg56 to %EAX: AH [2576r,2592r:0)  0@2576r AL [2576r,2592r:0)  0@2576r

selectOrSplit GR32:%vreg11 [16r,464r:0)  0@16r w=3.573113e-03
hints: %R9D
RS_Split Cascade 5
Analyze counted 3 instrs in 1 blocks, through 0 blocks.
tryLocalSplit:  16r 352r 464r
1 regmasks in block: 304r:16r-352r
%R9D 16r-352r i=inf extend
%R9D 352r-464r i=0.000000e+00 w=5.681818e-03 (best) end
%EAX 16r-352r i=inf extend
%EAX 352r-464r i=0.000000e+00 w=5.681818e-03 (best) end
%ECX 16r-352r i=inf extend
%ECX 352r-464r i=0.000000e+00 w=5.681818e-03 (best) end
%EDX 16r-352r i=inf extend
%EDX 352r-464r i=0.000000e+00 w=5.681818e-03 (best) end
%ESI 16r-352r i=inf extend
%ESI 352r-464r i=0.000000e+00 w=5.681818e-03 (best) end
%EDI 16r-352r i=inf extend
%EDI 352r-464r i=0.000000e+00 w=5.681818e-03 (best) end
%R8D 16r-352r i=inf extend
%R8D 352r-464r i=0.000000e+00 w=5.681818e-03 (best) end
%R10D 16r-352r i=inf extend
%R10D 352r-464r i=0.000000e+00 w=5.681818e-03 (best) end
%R11D 16r-352r i=inf extend
%R11D 352r-464r i=inf end
%EBX 16r-352r i=4.208333e-03 w=3.989362e-03 extend
%EBX 352r-464r i=4.208333e-03 w=5.681818e-03 end
%R14D 16r-352r i=4.404070e-03 w=3.989362e-03 extend
%R14D 352r-464r i=4.404070e-03 w=5.681818e-03 end
%R15D 16r-352r i=3.713235e-03 w=3.989362e-03 extend
%R15D 16r-464r i=3.713235e-03 all
%R12D 16r-352r i=3.864796e-03 w=3.989362e-03 extend
%R12D 16r-464r i=3.864796e-03 all
%R13D 16r-352r i=4.029255e-03 w=3.989362e-03 extend
%R13D 352r-464r i=4.029255e-03 w=5.681818e-03 end
Best local split range: 352r-464r, 5.568071e-03, 2 instrs
    enterIntvBefore 352r: valno 0
    leaveIntvAfter 464r: not live
    useIntv [344r;480B): [344r;480B):1
  blit [16r,464r:0): [16r;344r)=0:0 [344r;464r)=1:0
  rewr BB#0	16r:0	%vreg71<def> = COPY %R9D; GR32:%vreg71
  rewr BB#0	464B:1	MOV32mr <fi#6>, 1, %noreg, 0, %noreg, %vreg72; mem:ST4[%verbosity.addr] GR32:%vreg72
  rewr BB#0	352B:1	STACKMAP 0, 0, %vreg1, 0, <fi#1>, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, %vreg9, 0, <fi#5>, 0, %vreg5, 0, <fi#3>, 0, %vreg7, 0, <fi#4>, 0, 0, <fi#7>, 0, %vreg72, 0, <fi#6>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack8](align=4) LD8[FixedStack0](align=4) LD8[FixedStack5](align=4) LD8[FixedStack3] LD8[FixedStack4](align=4) LD8[FixedStack7] LD8[FixedStack6](align=4) GR64:%vreg1,%vreg3,%vreg5 GR32:%vreg9,%vreg7,%vreg72
  rewr BB#0	344B:0	%vreg72<def> = COPY %vreg71; GR32:%vreg72,%vreg71
Tagging non-progress ranges: %vreg72
queuing new interval: %vreg71 [16r,344r:0)  0@16r
queuing new interval: %vreg72 [344r,464r:0)  0@344r

selectOrSplit GR32:%vreg71 [16r,344r:0)  0@16r w=2.774725e-03
hints: %R9D
RS_Assign Cascade 0
wait for second round
queuing new interval: %vreg71 [16r,344r:0)  0@16r

selectOrSplit GR32:%vreg72 [344r,464r:0)  0@344r w=5.826923e-03
assigning %vreg72 to %EAX: AH [344r,464r:0)  0@344r AL [344r,464r:0)  0@344r

selectOrSplit GR32:%vreg71 [16r,344r:0)  0@16r w=2.774725e-03
hints: %R9D
RS_Split Cascade 0
Analyze counted 2 instrs in 1 blocks, through 0 blocks.
Inline spilling GR32:%vreg71 [16r,344r:0)  0@16r
From original %vreg11
Merged spilled regs: SS#9 [16r,344r:0)  0@x
spillAroundUses %vreg71
	folded:   16r	MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %R9D; mem:ST4[FixedStack9]
Checking redundant spills for 0@344r in %vreg72 [344r,464r:0)  0@344r
Merged to stack int: SS#9 [16r,464r:0)  0@x
	folded:   344r	%vreg72<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[FixedStack9] GR32:%vreg72
Trying to reconcile hints for: %vreg1(%R14)
%vreg1(%R14) is recolorable.

********** STACK TRANSFORMATION METADATA **********
********** Function: BZ2_bzBuffToBuffDecompress
********** REGISTER MAP **********
[%vreg1 -> %R14] GR64
[%vreg3 -> %RBX] GR64
[%vreg5 -> %R13] GR64
[%vreg7 -> %R12D] GR32
[%vreg9 -> %R15D] GR32
[%vreg14 -> %RDI] GR64
[%vreg15 -> %RSI] GR64
[%vreg24 -> %RDI] GR64
[%vreg27 -> %EAX] GR32
[%vreg28 -> %EDX] GR32
[%vreg29 -> %ESI] GR32
[%vreg32 -> %RDI] GR64
[%vreg33 -> %EAX] GR32
[%vreg36 -> %EAX] GR32
[%vreg37 -> %RAX] GR64
[%vreg39 -> %EAX] GR32
[%vreg41 -> %RAX] GR64
[%vreg43 -> %RAX] GR64
[%vreg45 -> %RDI] GR64
[%vreg46 -> %EAX] GR32
[%vreg51 -> %EDX] GR32
[%vreg53 -> %RCX] GR64
[%vreg54 -> %EAX] GR32
[%vreg56 -> %EAX] GR32
[%vreg57 -> %RDI] GR64
[%vreg58 -> %EAX] GR32
[%vreg60 -> %RDI] GR64
[%vreg61 -> %EAX] GR32
[%vreg62 -> %RDI] GR64
[%vreg63 -> %EAX] GR32
[%vreg65 -> %EAX] GR32
[%vreg67 -> %EAX] GR32
[%vreg69 -> %RDI] GR64
[%vreg70 -> %RSI] GR64
[%vreg72 -> %EAX] GR32
[%vreg11 -> fi#9] GR32
[%vreg71 -> fi#9] GR32


Stackmap 0:
  STACKMAP 0, 0, %vreg1, 0, <fi#1>, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, %vreg9, 0, <fi#5>, 0, %vreg5, 0, <fi#3>, 0, %vreg7, 0, <fi#4>, 0, 0, <fi#7>, 0, %vreg72, 0, <fi#6>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack8](align=4) LD8[FixedStack0](align=4) LD8[FixedStack5](align=4) LD8[FixedStack3] LD8[FixedStack4](align=4) LD8[FixedStack7] LD8[FixedStack6](align=4) GR64:%vreg1,%vreg3,%vreg5 GR32:%vreg9,%vreg7,%vreg72

i8* %dest: in register %R14 (vreg 1)
i8** %dest.addr: in stack slot 1 (size: 8)
i32* %destLen: in register %RBX (vreg 3)
i32** %destLen.addr: in stack slot 2 (size: 8)
i32* %ret: in stack slot 8 (size: 4)
i32* %retval: in stack slot 0 (size: 4)
i32 %small: in register %R15D (vreg 9)
i32* %small.addr: in stack slot 5 (size: 4)
i8* %source: in register %R13 (vreg 5)
i8** %source.addr: in stack slot 3 (size: 8)
i32 %sourceLen: in register %R12D (vreg 7)
i32* %sourceLen.addr: in stack slot 4 (size: 4)
%struct.bz_stream* %strm: in stack slot 7 (size: 80)
i32 %verbosity: in register %EAX (vreg 72)
i32* %verbosity.addr: in stack slot 6 (size: 4)

Duplicate operand locations:

i32 %verbosity: in stack slot 9 (size: 4)

Stackmap 1:
  STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, 0, <fi#7>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack8](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3] LD8[FixedStack4](align=4) LD8[FixedStack7]

i8** %dest.addr: in stack slot 1 (size: 8)
i32** %destLen.addr: in stack slot 2 (size: 8)
i32* %ret: in stack slot 8 (size: 4)
i32* %retval: in stack slot 0 (size: 4)
i8** %source.addr: in stack slot 3 (size: 8)
i32* %sourceLen.addr: in stack slot 4 (size: 4)
%struct.bz_stream* %strm: in stack slot 7 (size: 80)

Duplicate operand locations:


Stackmap 2:
  STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, 0, <fi#7>, 0, ...; mem:LD8[FixedStack2] LD8[FixedStack8](align=4) LD8[FixedStack0](align=4) LD8[FixedStack7]

i32** %destLen.addr: in stack slot 2 (size: 8)
i32* %ret: in stack slot 8 (size: 4)
i32* %retval: in stack slot 0 (size: 4)
%struct.bz_stream* %strm: in stack slot 7 (size: 80)

Duplicate operand locations:


Stackmap 3:
  STACKMAP 3, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)

i32* %retval: in stack slot 0 (size: 4)

Duplicate operand locations:


Stackmap 4:
  STACKMAP 4, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)

i32* %retval: in stack slot 0 (size: 4)

Duplicate operand locations:


Stackmap 5:
  STACKMAP 5, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)

i32* %retval: in stack slot 0 (size: 4)

Duplicate operand locations:


Stackmap 6:
  STACKMAP 6, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack8](align=4) LD8[FixedStack0](align=4)

i32* %ret: in stack slot 8 (size: 4)
i32* %retval: in stack slot 0 (size: 4)

Duplicate operand locations:


Stackmap 7:
  STACKMAP 7, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)

i32* %retval: in stack slot 0 (size: 4)

Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, %vreg1, 0, <fi#1>, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, %vreg9, 0, <fi#5>, 0, %vreg5, 0, <fi#3>, 0, %vreg7, 0, <fi#4>, 0, 0, <fi#7>, 0, %vreg72, 0, <fi#6>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack8](align=4) LD8[FixedStack0](align=4) LD8[FixedStack5](align=4) LD8[FixedStack3] LD8[FixedStack4](align=4) LD8[FixedStack7] LD8[FixedStack6](align=4) GR64:%vreg1,%vreg3,%vreg5 GR32:%vreg9,%vreg7,%vreg72
  -> Call instruction SlotIndex 304B, searching vregs 0 -> 73 and stack slots -1 -> 10

  STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, 0, <fi#7>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack8](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3] LD8[FixedStack4](align=4) LD8[FixedStack7]
  -> Call instruction SlotIndex 1024B, searching vregs 0 -> 73 and stack slots -1 -> 10

  STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, 0, <fi#7>, 0, ...; mem:LD8[FixedStack2] LD8[FixedStack8](align=4) LD8[FixedStack0](align=4) LD8[FixedStack7]
  -> Call instruction SlotIndex 1440B, searching vregs 0 -> 73 and stack slots -1 -> 10

  STACKMAP 3, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
  -> Call instruction SlotIndex 1856B, searching vregs 0 -> 73 and stack slots -1 -> 10

  STACKMAP 4, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
  -> Call instruction SlotIndex 2096B, searching vregs 0 -> 73 and stack slots -1 -> 10

  STACKMAP 5, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
  -> Call instruction SlotIndex 2288B, searching vregs 0 -> 73 and stack slots -1 -> 10

  STACKMAP 6, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack8](align=4) LD8[FixedStack0](align=4)
  -> Call instruction SlotIndex 2480B, searching vregs 0 -> 73 and stack slots -1 -> 10

  STACKMAP 7, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
  -> Call instruction SlotIndex 2720B, searching vregs 0 -> 73 and stack slots -1 -> 10

********** REWRITE VIRTUAL REGISTERS **********
********** Function: BZ2_bzBuffToBuffDecompress
********** REGISTER MAP **********
[%vreg1 -> %R14] GR64
[%vreg3 -> %RBX] GR64
[%vreg5 -> %R13] GR64
[%vreg7 -> %R12D] GR32
[%vreg9 -> %R15D] GR32
[%vreg14 -> %RDI] GR64
[%vreg15 -> %RSI] GR64
[%vreg24 -> %RDI] GR64
[%vreg27 -> %EAX] GR32
[%vreg28 -> %EDX] GR32
[%vreg29 -> %ESI] GR32
[%vreg32 -> %RDI] GR64
[%vreg33 -> %EAX] GR32
[%vreg36 -> %EAX] GR32
[%vreg37 -> %RAX] GR64
[%vreg39 -> %EAX] GR32
[%vreg41 -> %RAX] GR64
[%vreg43 -> %RAX] GR64
[%vreg45 -> %RDI] GR64
[%vreg46 -> %EAX] GR32
[%vreg51 -> %EDX] GR32
[%vreg53 -> %RCX] GR64
[%vreg54 -> %EAX] GR32
[%vreg56 -> %EAX] GR32
[%vreg57 -> %RDI] GR64
[%vreg58 -> %EAX] GR32
[%vreg60 -> %RDI] GR64
[%vreg61 -> %EAX] GR32
[%vreg62 -> %RDI] GR64
[%vreg63 -> %EAX] GR32
[%vreg65 -> %EAX] GR32
[%vreg67 -> %EAX] GR32
[%vreg69 -> %RDI] GR64
[%vreg70 -> %RSI] GR64
[%vreg72 -> %EAX] GR32
[%vreg11 -> fi#9] GR32
[%vreg71 -> fi#9] GR32

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %ECX %RDI %RDX %RSI %R8D %R9D
16B		MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %R9D; mem:ST4[FixedStack9]
32B		%vreg9<def> = COPY %R8D; GR32:%vreg9
48B		%vreg7<def> = COPY %ECX; GR32:%vreg7
64B		%vreg5<def> = COPY %RDX; GR64:%vreg5
80B		%vreg3<def> = COPY %RSI; GR64:%vreg3
96B		%vreg1<def> = COPY %RDI; GR64:%vreg1
208B		%vreg14<def> = MOV64ri <ga:@BZ2_bzBuffToBuffDecompress>; GR64:%vreg14
240B		%vreg15<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg15
256B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
272B		%RDI<def> = COPY %vreg14<kill>; GR64:%vreg14
288B		%RSI<def> = COPY %vreg15<kill>; GR64:%vreg15
304B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
320B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
336B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
344B		%vreg72<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[FixedStack9] GR32:%vreg72
352B		STACKMAP 0, 0, %vreg1, 0, <fi#1>, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, %vreg9, 0, <fi#5>, 0, %vreg5, 0, <fi#3>, 0, %vreg7, 0, <fi#4>, 0, 0, <fi#7>, 0, %vreg72, 0, <fi#6>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack8](align=4) LD8[FixedStack0](align=4) LD8[FixedStack5](align=4) LD8[FixedStack3] LD8[FixedStack4](align=4) LD8[FixedStack7] LD8[FixedStack6](align=4) GR64:%vreg1,%vreg3,%vreg5 GR32:%vreg9,%vreg7,%vreg72
368B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
384B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg1<kill>; mem:ST8[%dest.addr] GR64:%vreg1
400B		MOV64mr <fi#2>, 1, %noreg, 0, %noreg, %vreg3<kill>; mem:ST8[%destLen.addr] GR64:%vreg3
416B		MOV64mr <fi#3>, 1, %noreg, 0, %noreg, %vreg5<kill>; mem:ST8[%source.addr] GR64:%vreg5
432B		MOV32mr <fi#4>, 1, %noreg, 0, %noreg, %vreg7<kill>; mem:ST4[%sourceLen.addr] GR32:%vreg7
448B		MOV32mr <fi#5>, 1, %noreg, 0, %noreg, %vreg9<kill>; mem:ST4[%small.addr] GR32:%vreg9
464B		MOV32mr <fi#6>, 1, %noreg, 0, %noreg, %vreg72<kill>; mem:ST4[%verbosity.addr] GR32:%vreg72
480B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%dest.addr]
496B		JE_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#1
> MOV32mr <fi#9>, 1, %noreg, 0, %noreg, %R9D; mem:ST4[FixedStack9]
> %R15D<def> = COPY %R8D
> %R12D<def> = COPY %ECX
> %R13<def> = COPY %RDX
> %RBX<def> = COPY %RSI
> %R14<def> = COPY %RDI
> %RDI<def> = MOV64ri <ga:@BZ2_bzBuffToBuffDecompress>
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def> = MOV32rm <fi#9>, 1, %noreg, 0, %noreg; mem:LD4[FixedStack9]
> STACKMAP 0, 0, %R14, 0, <fi#1>, 0, %RBX, 0, <fi#2>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, %R15D, 0, <fi#5>, 0, %R13, 0, <fi#3>, 0, %R12D, 0, <fi#4>, 0, 0, <fi#7>, 0, %EAX, 0, <fi#6>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack8](align=4) LD8[FixedStack0](align=4) LD8[FixedStack5](align=4) LD8[FixedStack3] LD8[FixedStack4](align=4) LD8[FixedStack7] LD8[FixedStack6](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %R14<kill>; mem:ST8[%dest.addr]
> MOV64mr <fi#2>, 1, %noreg, 0, %noreg, %RBX<kill>; mem:ST8[%destLen.addr]
> MOV64mr <fi#3>, 1, %noreg, 0, %noreg, %R13<kill>; mem:ST8[%source.addr]
> MOV32mr <fi#4>, 1, %noreg, 0, %noreg, %R12D<kill>; mem:ST4[%sourceLen.addr]
> MOV32mr <fi#5>, 1, %noreg, 0, %noreg, %R15D<kill>; mem:ST4[%small.addr]
> MOV32mr <fi#6>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%verbosity.addr]
> CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%dest.addr]
> JE_1 <BB#7>, %EFLAGS<imp-use,kill>
512B	BB#1: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#0
528B		CMP64mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%destLen.addr]
544B		JE_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#2
> CMP64mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%destLen.addr]
> JE_1 <BB#7>, %EFLAGS<imp-use,kill>
560B	BB#2: derived from LLVM BB %lor.lhs.false.2
	    Predecessors according to CFG: BB#1
576B		CMP64mi8 <fi#3>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%source.addr]
592B		JE_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#3
> CMP64mi8 <fi#3>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%source.addr]
> JE_1 <BB#7>, %EFLAGS<imp-use,kill>
608B	BB#3: derived from LLVM BB %lor.lhs.false.4
	    Predecessors according to CFG: BB#2
624B		CMP32mi8 <fi#5>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%small.addr]
640B		JE_1 <BB#5>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#5 BB#4
> CMP32mi8 <fi#5>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%small.addr]
> JE_1 <BB#5>, %EFLAGS<imp-use,kill>
656B	BB#4: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#3
672B		CMP32mi8 <fi#5>, 1, %noreg, 0, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%small.addr]
688B		JNE_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#5
> CMP32mi8 <fi#5>, 1, %noreg, 0, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%small.addr]
> JNE_1 <BB#7>, %EFLAGS<imp-use,kill>
704B	BB#5: derived from LLVM BB %lor.lhs.false.7
	    Predecessors according to CFG: BB#3 BB#4
720B		CMP32mi8 <fi#6>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%verbosity.addr]
736B		JL_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#6
> CMP32mi8 <fi#6>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%verbosity.addr]
> JL_1 <BB#7>, %EFLAGS<imp-use,kill>
752B	BB#6: derived from LLVM BB %lor.lhs.false.9
	    Predecessors according to CFG: BB#5
768B		CMP32mi8 <fi#6>, 1, %noreg, 0, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%verbosity.addr]
784B		JLE_1 <BB#8>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#8 BB#7
> CMP32mi8 <fi#6>, 1, %noreg, 0, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%verbosity.addr]
> JLE_1 <BB#8>, %EFLAGS<imp-use,kill>
800B	BB#7: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0 BB#1 BB#2 BB#4 BB#5 BB#6
816B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
832B		JMP_1 <BB#19>
	    Successors according to CFG: BB#19
> MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -2; mem:ST4[%retval]
> JMP_1 <BB#19>
848B	BB#8: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#6
864B		%vreg24<def> = LEA64r <fi#7>, 1, %noreg, 0, %noreg; GR64:%vreg24
880B		MOV64mi32 <fi#7>, 1, %noreg, 56, %noreg, 0; mem:ST8[%bzalloc]
896B		MOV64mi32 <fi#7>, 1, %noreg, 64, %noreg, 0; mem:ST8[%bzfree]
912B		MOV64mi32 <fi#7>, 1, %noreg, 72, %noreg, 0; mem:ST8[%opaque]
928B		%vreg29<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%verbosity.addr] GR32:%vreg29
944B		%vreg28<def> = MOV32rm <fi#5>, 1, %noreg, 0, %noreg; mem:LD4[%small.addr] GR32:%vreg28
960B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
976B		%RDI<def> = COPY %vreg24<kill>; GR64:%vreg24
992B		%ESI<def> = COPY %vreg29<kill>; GR32:%vreg29
1008B		%EDX<def> = COPY %vreg28<kill>; GR32:%vreg28
1024B		CALL64pcrel32 <ga:@BZ2_bzDecompressInit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %EDX<imp-use>, %EAX<imp-def>
1040B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1056B		%vreg27<def> = COPY %EAX; GR32:%vreg27
1072B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1088B		STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, 0, <fi#7>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack8](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3] LD8[FixedStack4](align=4) LD8[FixedStack7]
1104B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1120B		MOV32mr <fi#8>, 1, %noreg, 0, %noreg, %vreg27<kill>; mem:ST4[%ret] GR32:%vreg27
1136B		CMP32mi8 <fi#8>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%ret]
1152B		JE_1 <BB#10>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#10 BB#9
> %RDI<def> = LEA64r <fi#7>, 1, %noreg, 0, %noreg
> MOV64mi32 <fi#7>, 1, %noreg, 56, %noreg, 0; mem:ST8[%bzalloc]
> MOV64mi32 <fi#7>, 1, %noreg, 64, %noreg, 0; mem:ST8[%bzfree]
> MOV64mi32 <fi#7>, 1, %noreg, 72, %noreg, 0; mem:ST8[%opaque]
> %ESI<def> = MOV32rm <fi#6>, 1, %noreg, 0, %noreg; mem:LD4[%verbosity.addr]
> %EDX<def> = MOV32rm <fi#5>, 1, %noreg, 0, %noreg; mem:LD4[%small.addr]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %ESI<def> = COPY %ESI<kill>
Deleting identity copy.
> %EDX<def> = COPY %EDX<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@BZ2_bzDecompressInit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %EDX<imp-use>, %EAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def> = COPY %EAX
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 1, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, 0, <fi#3>, 0, 0, <fi#4>, 0, 0, <fi#7>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack8](align=4) LD8[FixedStack0](align=4) LD8[FixedStack3] LD8[FixedStack4](align=4) LD8[FixedStack7]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV32mr <fi#8>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%ret]
> CMP32mi8 <fi#8>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%ret]
> JE_1 <BB#10>, %EFLAGS<imp-use,kill>
1168B	BB#9: derived from LLVM BB %if.then.12
	    Predecessors according to CFG: BB#8
1184B		%vreg65<def> = MOV32rm <fi#8>, 1, %noreg, 0, %noreg; mem:LD4[%ret] GR32:%vreg65
1200B		MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %vreg65<kill>; mem:ST4[%retval] GR32:%vreg65
1216B		JMP_1 <BB#19>
	    Successors according to CFG: BB#19
> %EAX<def> = MOV32rm <fi#8>, 1, %noreg, 0, %noreg; mem:LD4[%ret]
> MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%retval]
> JMP_1 <BB#19>
1232B	BB#10: derived from LLVM BB %if.end.13
	    Predecessors according to CFG: BB#8
1248B		%vreg32<def> = LEA64r <fi#7>, 1, %noreg, 0, %noreg; GR64:%vreg32
1264B		%vreg43<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%source.addr] GR64:%vreg43
1280B		MOV64mr <fi#7>, 1, %noreg, 0, %noreg, %vreg43<kill>; mem:ST8[%next_in] GR64:%vreg43
1296B		%vreg41<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%dest.addr] GR64:%vreg41
1312B		MOV64mr <fi#7>, 1, %noreg, 24, %noreg, %vreg41<kill>; mem:ST8[%next_out] GR64:%vreg41
1328B		%vreg39<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%sourceLen.addr] GR32:%vreg39
1344B		MOV32mr <fi#7>, 1, %noreg, 8, %noreg, %vreg39<kill>; mem:ST4[%avail_in] GR32:%vreg39
1360B		%vreg37<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%destLen.addr] GR64:%vreg37
1376B		%vreg36<def> = MOV32rm %vreg37<kill>, 1, %noreg, 0, %noreg; mem:LD4[%14] GR32:%vreg36 GR64:%vreg37
1392B		MOV32mr <fi#7>, 1, %noreg, 32, %noreg, %vreg36<kill>; mem:ST4[%avail_out] GR32:%vreg36
1408B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1424B		%RDI<def> = COPY %vreg32<kill>; GR64:%vreg32
1440B		CALL64pcrel32 <ga:@BZ2_bzDecompress>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
1456B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1472B		%vreg33<def> = COPY %EAX; GR32:%vreg33
1488B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1504B		STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, 0, <fi#7>, 0, ...; mem:LD8[FixedStack2] LD8[FixedStack8](align=4) LD8[FixedStack0](align=4) LD8[FixedStack7]
1520B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1536B		MOV32mr <fi#8>, 1, %noreg, 0, %noreg, %vreg33<kill>; mem:ST4[%ret] GR32:%vreg33
1552B		CMP32mi8 <fi#8>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%ret]
1568B		JNE_1 <BB#12>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#12 BB#11
> %RDI<def> = LEA64r <fi#7>, 1, %noreg, 0, %noreg
> %RAX<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%source.addr]
> MOV64mr <fi#7>, 1, %noreg, 0, %noreg, %RAX<kill>; mem:ST8[%next_in]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%dest.addr]
> MOV64mr <fi#7>, 1, %noreg, 24, %noreg, %RAX<kill>; mem:ST8[%next_out]
> %EAX<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%sourceLen.addr]
> MOV32mr <fi#7>, 1, %noreg, 8, %noreg, %EAX<kill>; mem:ST4[%avail_in]
> %RAX<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%destLen.addr]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD4[%14]
> MOV32mr <fi#7>, 1, %noreg, 32, %noreg, %EAX<kill>; mem:ST4[%avail_out]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@BZ2_bzDecompress>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def> = COPY %EAX
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 2, 0, 0, <fi#2>, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, 0, <fi#7>, 0, ...; mem:LD8[FixedStack2] LD8[FixedStack8](align=4) LD8[FixedStack0](align=4) LD8[FixedStack7]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV32mr <fi#8>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%ret]
> CMP32mi8 <fi#8>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%ret]
> JNE_1 <BB#12>, %EFLAGS<imp-use,kill>
1584B	BB#11: derived from LLVM BB %if.then.16
	    Predecessors according to CFG: BB#10
1600B		JMP_1 <BB#15>
	    Successors according to CFG: BB#15
> JMP_1 <BB#15>
1616B	BB#12: derived from LLVM BB %if.end.17
	    Predecessors according to CFG: BB#10
1632B		CMP32mi8 <fi#8>, 1, %noreg, 0, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%ret]
1648B		JE_1 <BB#14>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#14 BB#13
> CMP32mi8 <fi#8>, 1, %noreg, 0, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%ret]
> JE_1 <BB#14>, %EFLAGS<imp-use,kill>
1664B	BB#13: derived from LLVM BB %if.then.19
	    Predecessors according to CFG: BB#12
1680B		JMP_1 <BB#18>
	    Successors according to CFG: BB#18
> JMP_1 <BB#18>
1696B	BB#14: derived from LLVM BB %if.end.20
	    Predecessors according to CFG: BB#12
1712B		%vreg45<def> = LEA64r <fi#7>, 1, %noreg, 0, %noreg; GR64:%vreg45
1728B		%vreg54<def> = MOV32rm <fi#7>, 1, %noreg, 32, %noreg; mem:LD4[%avail_out21] GR32:%vreg54
1744B		%vreg53<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%destLen.addr] GR64:%vreg53
1760B		%vreg51<def> = MOV32rm %vreg53, 1, %noreg, 0, %noreg; mem:LD4[%19] GR32:%vreg51 GR64:%vreg53
1792B		%vreg51<def,tied1> = SUB32rr %vreg51<kill,tied0>, %vreg54<kill>, %EFLAGS<imp-def,dead>; GR32:%vreg51,%vreg54
1808B		MOV32mr %vreg53<kill>, 1, %noreg, 0, %noreg, %vreg51<kill>; mem:ST4[%19] GR64:%vreg53 GR32:%vreg51
1824B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1840B		%RDI<def> = COPY %vreg45<kill>; GR64:%vreg45
1856B		CALL64pcrel32 <ga:@BZ2_bzDecompressEnd>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
1872B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1888B		%vreg46<def,dead> = COPY %EAX; GR32:%vreg46
1904B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1920B		STACKMAP 3, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
1936B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1952B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
1968B		JMP_1 <BB#19>
	    Successors according to CFG: BB#19
> %RDI<def> = LEA64r <fi#7>, 1, %noreg, 0, %noreg
> %EAX<def> = MOV32rm <fi#7>, 1, %noreg, 32, %noreg; mem:LD4[%avail_out21]
> %RCX<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%destLen.addr]
> %EDX<def> = MOV32rm %RCX, 1, %noreg, 0, %noreg; mem:LD4[%19]
> %EDX<def,tied1> = SUB32rr %EDX<kill,tied0>, %EAX<kill>, %EFLAGS<imp-def,dead>
> MOV32mr %RCX<kill>, 1, %noreg, 0, %noreg, %EDX<kill>; mem:ST4[%19]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@BZ2_bzDecompressEnd>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def,dead> = COPY %EAX
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 3, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
> JMP_1 <BB#19>
1984B	BB#15: derived from LLVM BB %output_overflow_or_eof
	    Predecessors according to CFG: BB#11
2000B		CMP32mi8 <fi#7>, 1, %noreg, 32, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_out23]
2016B		JBE_1 <BB#17>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#17 BB#16
> CMP32mi8 <fi#7>, 1, %noreg, 32, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_out23]
> JBE_1 <BB#17>, %EFLAGS<imp-use,kill>
2032B	BB#16: derived from LLVM BB %if.then.25
	    Predecessors according to CFG: BB#15
2048B		%vreg62<def> = LEA64r <fi#7>, 1, %noreg, 0, %noreg; GR64:%vreg62
2064B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2080B		%RDI<def> = COPY %vreg62<kill>; GR64:%vreg62
2096B		CALL64pcrel32 <ga:@BZ2_bzDecompressEnd>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
2112B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2128B		%vreg63<def,dead> = COPY %EAX; GR32:%vreg63
2144B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2160B		STACKMAP 4, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
2176B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2192B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -7; mem:ST4[%retval]
2208B		JMP_1 <BB#19>
	    Successors according to CFG: BB#19
> %RDI<def> = LEA64r <fi#7>, 1, %noreg, 0, %noreg
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@BZ2_bzDecompressEnd>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def,dead> = COPY %EAX
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 4, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -7; mem:ST4[%retval]
> JMP_1 <BB#19>
2224B	BB#17: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#15
2240B		%vreg60<def> = LEA64r <fi#7>, 1, %noreg, 0, %noreg; GR64:%vreg60
2256B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2272B		%RDI<def> = COPY %vreg60<kill>; GR64:%vreg60
2288B		CALL64pcrel32 <ga:@BZ2_bzDecompressEnd>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
2304B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2320B		%vreg61<def,dead> = COPY %EAX; GR32:%vreg61
2336B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2352B		STACKMAP 5, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
2368B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2384B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -8; mem:ST4[%retval]
2400B		JMP_1 <BB#19>
	    Successors according to CFG: BB#19
> %RDI<def> = LEA64r <fi#7>, 1, %noreg, 0, %noreg
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@BZ2_bzDecompressEnd>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def,dead> = COPY %EAX
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 5, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -8; mem:ST4[%retval]
> JMP_1 <BB#19>
2416B	BB#18: derived from LLVM BB %errhandler
	    Predecessors according to CFG: BB#13
2432B		%vreg57<def> = LEA64r <fi#7>, 1, %noreg, 0, %noreg; GR64:%vreg57
2448B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2464B		%RDI<def> = COPY %vreg57<kill>; GR64:%vreg57
2480B		CALL64pcrel32 <ga:@BZ2_bzDecompressEnd>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
2496B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2512B		%vreg58<def,dead> = COPY %EAX; GR32:%vreg58
2528B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2544B		STACKMAP 6, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack8](align=4) LD8[FixedStack0](align=4)
2560B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2576B		%vreg56<def> = MOV32rm <fi#8>, 1, %noreg, 0, %noreg; mem:LD4[%ret] GR32:%vreg56
2592B		MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %vreg56<kill>; mem:ST4[%retval] GR32:%vreg56
	    Successors according to CFG: BB#19
> %RDI<def> = LEA64r <fi#7>, 1, %noreg, 0, %noreg
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@BZ2_bzDecompressEnd>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def,dead> = COPY %EAX
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 6, 0, 0, <fi#8>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack8](align=4) LD8[FixedStack0](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def> = MOV32rm <fi#8>, 1, %noreg, 0, %noreg; mem:LD4[%ret]
> MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%retval]
2608B	BB#19: derived from LLVM BB %return
	    Predecessors according to CFG: BB#14 BB#18 BB#17 BB#16 BB#9 BB#7
2624B		%vreg69<def> = MOV64ri <ga:@BZ2_bzBuffToBuffDecompress>; GR64:%vreg69
2656B		%vreg70<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg70
2672B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2688B		%RDI<def> = COPY %vreg69<kill>; GR64:%vreg69
2704B		%RSI<def> = COPY %vreg70<kill>; GR64:%vreg70
2720B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
2736B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2752B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2768B		STACKMAP 7, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
2784B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2800B		%vreg67<def> = MOV32rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD4[%retval] GR32:%vreg67
2816B		%EAX<def> = COPY %vreg67<kill>; GR32:%vreg67
2832B		RETQ %EAX<imp-use>
> %RDI<def> = MOV64ri <ga:@BZ2_bzBuffToBuffDecompress>
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 7, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def> = MOV32rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD4[%retval]
> %EAX<def> = COPY %EAX<kill>
Deleting identity copy.
> RETQ %EAX<imp-use>
Computing live-in reg-units in ABI blocks.
0B	BB#0 DIL#0 SIL#0
Created 2 new intervals.
********** INTERVALS **********
DIL [0B,32r:0)[144r,176r:1)[368r,432r:2)[592r,624r:3)  0@0B-phi 1@144r 2@368r 3@592r
SIL [0B,16r:0)[160r,176r:2)[384r,432r:1)[608r,624r:3)  0@0B-phi 1@384r 2@160r 3@608r
%vreg0 [32r,48r:0)  0@32r
%vreg1 [48r,288r:0)  0@48r
%vreg2 [16r,64r:0)  0@16r
%vreg3 [64r,304r:0)  0@64r
%vreg5 [480r,496r:0)  0@480r
%vreg6 [496r,592r:0)  0@496r
%vreg7 [560r,608r:0)  0@560r
%vreg9 [208r,384r:0)  0@208r
%vreg11 [224r,416r:0)  0@224r
%vreg12 [464r,704r:0)  0@464r
%vreg13 [336r,400r:0)  0@336r
%vreg14 [320r,368r:0)  0@320r
%vreg15 [80r,96r:0)  0@80r
%vreg16 [96r,144r:0)  0@96r
%vreg17 [112r,160r:0)  0@112r
RegMasks: 176r 432r 624r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzopen: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=8, align=8, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
Function Live Ins: %RDI in %vreg0, %RSI in %vreg2

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI %RSI
16B		%vreg2<def> = COPY %RSI; GR64:%vreg2
32B		%vreg0<def> = COPY %RDI; GR64:%vreg0
48B		%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
64B		%vreg3<def> = COPY %vreg2; GR64:%vreg3,%vreg2
80B		%vreg15<def> = MOV64ri <ga:@BZ2_bzopen>; GR64:%vreg15
96B		%vreg16<def> = COPY %vreg15; GR64:%vreg16,%vreg15
112B		%vreg17<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg17
128B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
144B		%RDI<def> = COPY %vreg16; GR64:%vreg16
160B		%RSI<def> = COPY %vreg17; GR64:%vreg17
176B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
192B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
208B		%vreg9<def> = MOV32ri 4294967295; GR32:%vreg9
224B		%vreg11<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg11
240B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
256B		STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack0] GR64:%vreg3,%vreg1
272B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
288B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%path.addr] GR64:%vreg1
304B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg3; mem:ST8[%mode.addr] GR64:%vreg3
320B		%vreg14<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%path.addr] GR64:%vreg14
336B		%vreg13<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%mode.addr] GR64:%vreg13
352B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
368B		%RDI<def> = COPY %vreg14; GR64:%vreg14
384B		%ESI<def> = COPY %vreg9; GR32:%vreg9
400B		%RDX<def> = COPY %vreg13; GR64:%vreg13
416B		%ECX<def> = COPY %vreg11; GR32:%vreg11
432B		CALL64pcrel32 <ga:@bzopen_or_bzdopen>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %RDX<imp-use,kill>, %ECX<imp-use,kill>, %RAX<imp-def>
448B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
464B		%vreg12<def> = COPY %RAX<kill>; GR64:%vreg12
480B		%vreg5<def> = MOV64ri <ga:@BZ2_bzopen>; GR64:%vreg5
496B		%vreg6<def> = COPY %vreg5; GR64:%vreg6,%vreg5
512B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
528B		STACKMAP 1, 0, ...
544B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
560B		%vreg7<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg7
576B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
592B		%RDI<def> = COPY %vreg6; GR64:%vreg6
608B		%RSI<def> = COPY %vreg7; GR64:%vreg7
624B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
640B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
656B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
672B		STACKMAP 2, 0, %vreg12, ...; GR64:%vreg12
688B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
704B		%RAX<def> = COPY %vreg12; GR64:%vreg12
720B		RETQ %RAX<imp-use,kill>

# End machine code for function BZ2_bzopen.

********** SIMPLE REGISTER COALESCING **********
********** Function: BZ2_bzopen
********** JOINING INTERVALS ***********
entry:
16B	%vreg2<def> = COPY %RSI; GR64:%vreg2
	Considering merging %vreg2 with %RSI
	Can only merge into reserved registers.
32B	%vreg0<def> = COPY %RDI; GR64:%vreg0
	Considering merging %vreg0 with %RDI
	Can only merge into reserved registers.
144B	%RDI<def> = COPY %vreg16; GR64:%vreg16
	Considering merging %vreg16 with %RDI
	Can only merge into reserved registers.
160B	%RSI<def> = COPY %vreg17; GR64:%vreg17
	Considering merging %vreg17 with %RSI
	Can only merge into reserved registers.
368B	%RDI<def> = COPY %vreg14; GR64:%vreg14
	Considering merging %vreg14 with %RDI
	Can only merge into reserved registers.
384B	%ESI<def> = COPY %vreg9; GR32:%vreg9
	Considering merging %vreg9 with %ESI
	Can only merge into reserved registers.
Remat: %ESI<def> = MOV32ri 4294967295
Shrink: %vreg9 [208r,384r:0)  0@208r
All defs dead: 208r	%vreg9<def,dead> = MOV32ri 4294967295; GR32:%vreg9
Shrunk: %vreg9 [208r,208d:0)  0@208r
Deleting dead def 208r	%vreg9<def,dead> = MOV32ri 4294967295; GR32:%vreg9
400B	%RDX<def> = COPY %vreg13; GR64:%vreg13
	Considering merging %vreg13 with %RDX
	Can only merge into reserved registers.
416B	%ECX<def> = COPY %vreg11; GR32:%vreg11
	Considering merging %vreg11 with %ECX
	Can only merge into reserved registers.
Remat: %ECX<def> = MOV32r0 %EFLAGS<imp-def,dead>
Shrink: %vreg11 [224r,416r:0)  0@224r
All defs dead: 224r	%vreg11<def,dead> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg11
Shrunk: %vreg11 [224r,224d:0)  0@224r
Deleting dead def 224r	%vreg11<def,dead> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg11
464B	%vreg12<def> = COPY %RAX<kill>; GR64:%vreg12
	Considering merging %vreg12 with %RAX
	Can only merge into reserved registers.
592B	%RDI<def> = COPY %vreg6; GR64:%vreg6
	Considering merging %vreg6 with %RDI
	Can only merge into reserved registers.
608B	%RSI<def> = COPY %vreg7; GR64:%vreg7
	Considering merging %vreg7 with %RSI
	Can only merge into reserved registers.
704B	%RAX<def> = COPY %vreg12; GR64:%vreg12
	Considering merging %vreg12 with %RAX
	Can only merge into reserved registers.
48B	%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
	Considering merging to GR64 with %vreg0 in %vreg1
		RHS = %vreg0 [32r,48r:0)  0@32r
		LHS = %vreg1 [48r,288r:0)  0@48r
		merge %vreg1:0@48r into %vreg0:0@32r --> @32r
		erased:	48r	%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
		updated: 32B	%vreg1<def> = COPY %RDI; GR64:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [32r,288r:0)  0@32r
64B	%vreg3<def> = COPY %vreg2; GR64:%vreg3,%vreg2
	Considering merging to GR64 with %vreg2 in %vreg3
		RHS = %vreg2 [16r,64r:0)  0@16r
		LHS = %vreg3 [64r,304r:0)  0@64r
		merge %vreg3:0@64r into %vreg2:0@16r --> @16r
		erased:	64r	%vreg3<def> = COPY %vreg2; GR64:%vreg3,%vreg2
		updated: 16B	%vreg3<def> = COPY %RSI; GR64:%vreg3
	Success: %vreg2 -> %vreg3
	Result = %vreg3 [16r,304r:0)  0@16r
96B	%vreg16<def> = COPY %vreg15; GR64:%vreg16,%vreg15
	Considering merging to GR64 with %vreg15 in %vreg16
		RHS = %vreg15 [80r,96r:0)  0@80r
		LHS = %vreg16 [96r,144r:0)  0@96r
		merge %vreg16:0@96r into %vreg15:0@80r --> @80r
		erased:	96r	%vreg16<def> = COPY %vreg15; GR64:%vreg16,%vreg15
		updated: 80B	%vreg16<def> = MOV64ri <ga:@BZ2_bzopen>; GR64:%vreg16
	Success: %vreg15 -> %vreg16
	Result = %vreg16 [80r,144r:0)  0@80r
496B	%vreg6<def> = COPY %vreg5; GR64:%vreg6,%vreg5
	Considering merging to GR64 with %vreg5 in %vreg6
		RHS = %vreg5 [480r,496r:0)  0@480r
		LHS = %vreg6 [496r,592r:0)  0@496r
		merge %vreg6:0@496r into %vreg5:0@480r --> @480r
		erased:	496r	%vreg6<def> = COPY %vreg5; GR64:%vreg6,%vreg5
		updated: 480B	%vreg6<def> = MOV64ri <ga:@BZ2_bzopen>; GR64:%vreg6
	Success: %vreg5 -> %vreg6
	Result = %vreg6 [480r,592r:0)  0@480r
144B	%RDI<def> = COPY %vreg16; GR64:%vreg16
	Considering merging %vreg16 with %RDI
	Can only merge into reserved registers.
592B	%RDI<def> = COPY %vreg6; GR64:%vreg6
	Considering merging %vreg6 with %RDI
	Can only merge into reserved registers.
704B	%RAX<def> = COPY %vreg12; GR64:%vreg12
	Considering merging %vreg12 with %RAX
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
DIL [0B,32r:0)[144r,176r:1)[368r,432r:2)[592r,624r:3)  0@0B-phi 1@144r 2@368r 3@592r
SIL [0B,16r:0)[160r,176r:2)[384r,432r:1)[608r,624r:3)  0@0B-phi 1@384r 2@160r 3@608r
%vreg1 [32r,288r:0)  0@32r
%vreg3 [16r,304r:0)  0@16r
%vreg6 [480r,592r:0)  0@480r
%vreg7 [560r,608r:0)  0@560r
%vreg12 [464r,704r:0)  0@464r
%vreg13 [336r,400r:0)  0@336r
%vreg14 [320r,368r:0)  0@320r
%vreg16 [80r,144r:0)  0@80r
%vreg17 [112r,160r:0)  0@112r
RegMasks: 176r 432r 624r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzopen: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=8, align=8, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
Function Live Ins: %RDI in %vreg0, %RSI in %vreg2

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI %RSI
16B		%vreg3<def> = COPY %RSI; GR64:%vreg3
32B		%vreg1<def> = COPY %RDI; GR64:%vreg1
80B		%vreg16<def> = MOV64ri <ga:@BZ2_bzopen>; GR64:%vreg16
112B		%vreg17<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg17
128B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
144B		%RDI<def> = COPY %vreg16; GR64:%vreg16
160B		%RSI<def> = COPY %vreg17; GR64:%vreg17
176B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
192B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
240B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
256B		STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack0] GR64:%vreg3,%vreg1
272B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
288B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%path.addr] GR64:%vreg1
304B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg3; mem:ST8[%mode.addr] GR64:%vreg3
320B		%vreg14<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%path.addr] GR64:%vreg14
336B		%vreg13<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%mode.addr] GR64:%vreg13
352B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
368B		%RDI<def> = COPY %vreg14; GR64:%vreg14
384B		%ESI<def> = MOV32ri 4294967295
400B		%RDX<def> = COPY %vreg13; GR64:%vreg13
416B		%ECX<def> = MOV32r0 %EFLAGS<imp-def,dead>
432B		CALL64pcrel32 <ga:@bzopen_or_bzdopen>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %RDX<imp-use,kill>, %ECX<imp-use,kill>, %RAX<imp-def>
448B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
464B		%vreg12<def> = COPY %RAX<kill>; GR64:%vreg12
480B		%vreg6<def> = MOV64ri <ga:@BZ2_bzopen>; GR64:%vreg6
512B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
528B		STACKMAP 1, 0, ...
544B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
560B		%vreg7<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg7
576B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
592B		%RDI<def> = COPY %vreg6; GR64:%vreg6
608B		%RSI<def> = COPY %vreg7; GR64:%vreg7
624B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
640B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
656B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
672B		STACKMAP 2, 0, %vreg12, ...; GR64:%vreg12
688B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
704B		%RAX<def> = COPY %vreg12; GR64:%vreg12
720B		RETQ %RAX<imp-use,kill>

# End machine code for function BZ2_bzopen.

handleMove 400B -> 424B: %RDX<def> = COPY %vreg13; GR64:%vreg13
     DH:	[424r,432r:0)  0@424r
        -->	[424r,432r:0)  0@424r
     DL:	[424r,432r:0)  0@424r
        -->	[424r,432r:0)  0@424r
     %vreg13:	[336r,400r:0)  0@336r
        -->	[336r,424r:0)  0@336r
handleMove 368B -> 420B: %RDI<def> = COPY %vreg14; GR64:%vreg14
     DIL:	[0B,32r:0)[144r,176r:1)[368r,432r:2)[592r,624r:3)  0@0B-phi 1@144r 2@368r 3@592r
        -->	[0B,32r:0)[144r,176r:1)[420r,432r:2)[592r,624r:3)  0@0B-phi 1@144r 2@420r 3@592r
     %vreg14:	[320r,368r:0)  0@320r
        -->	[320r,420r:0)  0@320r
********** GREEDY REGISTER ALLOCATION **********
********** Function: BZ2_bzopen
********** INTERVALS **********
DH [424r,432r:0)  0@424r
DIL [0B,32r:0)[144r,176r:1)[420r,432r:2)[592r,624r:3)  0@0B-phi 1@144r 2@420r 3@592r
DL [424r,432r:0)  0@424r
SIL [0B,16r:0)[160r,176r:2)[384r,432r:1)[608r,624r:3)  0@0B-phi 1@384r 2@160r 3@608r
%vreg1 [32r,288r:0)  0@32r
%vreg3 [16r,304r:0)  0@16r
%vreg6 [480r,592r:0)  0@480r
%vreg7 [560r,608r:0)  0@560r
%vreg12 [464r,704r:0)  0@464r
%vreg13 [336r,424r:0)  0@336r
%vreg14 [320r,420r:0)  0@320r
%vreg16 [80r,144r:0)  0@80r
%vreg17 [112r,160r:0)  0@112r
RegMasks: 176r 432r 624r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzopen: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=8, align=8, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
Function Live Ins: %RDI in %vreg0, %RSI in %vreg2

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI %RSI
16B		%vreg3<def> = COPY %RSI; GR64:%vreg3
32B		%vreg1<def> = COPY %RDI; GR64:%vreg1
80B		%vreg16<def> = MOV64ri <ga:@BZ2_bzopen>; GR64:%vreg16
112B		%vreg17<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg17
128B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
144B		%RDI<def> = COPY %vreg16; GR64:%vreg16
160B		%RSI<def> = COPY %vreg17; GR64:%vreg17
176B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
192B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
240B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
256B		STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack0] GR64:%vreg3,%vreg1
272B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
288B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%path.addr] GR64:%vreg1
304B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg3; mem:ST8[%mode.addr] GR64:%vreg3
320B		%vreg14<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%path.addr] GR64:%vreg14
336B		%vreg13<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%mode.addr] GR64:%vreg13
352B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
384B		%ESI<def> = MOV32ri 4294967295
416B		%ECX<def> = MOV32r0 %EFLAGS<imp-def,dead>
420B		%RDI<def> = COPY %vreg14; GR64:%vreg14
424B		%RDX<def> = COPY %vreg13; GR64:%vreg13
432B		CALL64pcrel32 <ga:@bzopen_or_bzdopen>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %RDX<imp-use>, %ECX<imp-use,kill>, %RAX<imp-def>
448B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
464B		%vreg12<def> = COPY %RAX<kill>; GR64:%vreg12
480B		%vreg6<def> = MOV64ri <ga:@BZ2_bzopen>; GR64:%vreg6
512B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
528B		STACKMAP 1, 0, ...
544B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
560B		%vreg7<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg7
576B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
592B		%RDI<def> = COPY %vreg6; GR64:%vreg6
608B		%RSI<def> = COPY %vreg7; GR64:%vreg7
624B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
640B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
656B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
672B		STACKMAP 2, 0, %vreg12, ...; GR64:%vreg12
688B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
704B		%RAX<def> = COPY %vreg12; GR64:%vreg12
720B		RETQ %RAX<imp-use,kill>

# End machine code for function BZ2_bzopen.


selectOrSplit GR64:%vreg3 [16r,304r:0)  0@16r w=4.404070e-03
hints: %RSI
missed hint %RSI
assigning %vreg3 to %RBX: BH [16r,304r:0)  0@16r BL [16r,304r:0)  0@16r

selectOrSplit GR64:%vreg1 [32r,288r:0)  0@32r w=4.618902e-03
hints: %RDI
missed hint %RDI
%R14 is available at cost 1
Only trying the first 10 regs.
should evict: %vreg3 [16r,304r:0)  0@16r w= 4.404070e-03
hints: %RSI
can reassign: %vreg3 [16r,304r:0)  0@16r from %RBX to %RSI
should evict: %vreg3 [16r,304r:0)  0@16r w= 4.404070e-03
hints: %RSI
can reassign: %vreg3 [16r,304r:0)  0@16r from %RBX to %RSI
evicting %RBX interference: Cascade 1
unassigning %vreg3 from %RBX: BH BL
assigning %vreg1 to %RBX: BH [32r,288r:0)  0@32r BL [32r,288r:0)  0@32r
queuing new interval: %vreg3 [16r,304r:0)  0@16r

selectOrSplit GR64:%vreg3 [16r,304r:0)  0@16r w=4.404070e-03
hints: %RSI
missed hint %RSI
%R14 is available at cost 1
Only trying the first 10 regs.
assigning %vreg3 to %R14: R14B [16r,304r:0)  0@16r

selectOrSplit GR64:%vreg16 [80r,144r:0)  0@80r w=2.176724e-03
hints: %RDI
assigning %vreg16 to %RDI: DIL [80r,144r:0)  0@80r

selectOrSplit GR64:%vreg17 [112r,160r:0)  0@112r w=4.508928e-03
hints: %RSI
assigning %vreg17 to %RSI: SIL [112r,160r:0)  0@112r

selectOrSplit GR64:%vreg14 [320r,420r:0)  0@320r w=4.040000e-03
hints: %RDI
assigning %vreg14 to %RDI: DIL [320r,420r:0)  0@320r

selectOrSplit GR64:%vreg13 [336r,424r:0)  0@336r w=4.139344e-03
hints: %RDX
assigning %vreg13 to %RDX: DH [336r,424r:0)  0@336r DL [336r,424r:0)  0@336r

selectOrSplit GR64:%vreg12 [464r,704r:0)  0@464r w=4.734375e-03
hints: %RAX
missed hint %RAX
assigning %vreg12 to %RBX: BH [464r,704r:0)  0@464r BL [464r,704r:0)  0@464r

selectOrSplit GR64:%vreg6 [480r,592r:0)  0@480r w=1.972656e-03
hints: %RDI
assigning %vreg6 to %RDI: DIL [480r,592r:0)  0@480r

selectOrSplit GR64:%vreg7 [560r,608r:0)  0@560r w=4.508928e-03
hints: %RSI
assigning %vreg7 to %RSI: SIL [560r,608r:0)  0@560r

********** STACK TRANSFORMATION METADATA **********
********** Function: BZ2_bzopen
********** REGISTER MAP **********
[%vreg1 -> %RBX] GR64
[%vreg3 -> %R14] GR64
[%vreg6 -> %RDI] GR64
[%vreg7 -> %RSI] GR64
[%vreg12 -> %RBX] GR64
[%vreg13 -> %RDX] GR64
[%vreg14 -> %RDI] GR64
[%vreg16 -> %RDI] GR64
[%vreg17 -> %RSI] GR64


Stackmap 0:
  STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack0] GR64:%vreg3,%vreg1

i8* %mode: in register %R14 (vreg 3)
i8** %mode.addr: in stack slot 1 (size: 8)
i8* %path: in register %RBX (vreg 1)
i8** %path.addr: in stack slot 0 (size: 8)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, ...


Duplicate operand locations:


Stackmap 2:
  STACKMAP 2, 0, %vreg12, ...; GR64:%vreg12

i8* %call: in register %RBX (vreg 12)

Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack0] GR64:%vreg3,%vreg1
  -> Call instruction SlotIndex 176B, searching vregs 0 -> 18 and stack slots -1 -> 2

  STACKMAP 1, 0, ...
  -> Call instruction SlotIndex 432B, searching vregs 0 -> 18 and stack slots -1 -> 2

  STACKMAP 2, 0, %vreg12, ...; GR64:%vreg12
  -> Call instruction SlotIndex 624B, searching vregs 0 -> 18 and stack slots -1 -> 2

********** REWRITE VIRTUAL REGISTERS **********
********** Function: BZ2_bzopen
********** REGISTER MAP **********
[%vreg1 -> %RBX] GR64
[%vreg3 -> %R14] GR64
[%vreg6 -> %RDI] GR64
[%vreg7 -> %RSI] GR64
[%vreg12 -> %RBX] GR64
[%vreg13 -> %RDX] GR64
[%vreg14 -> %RDI] GR64
[%vreg16 -> %RDI] GR64
[%vreg17 -> %RSI] GR64

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI %RSI
16B		%vreg3<def> = COPY %RSI; GR64:%vreg3
32B		%vreg1<def> = COPY %RDI; GR64:%vreg1
80B		%vreg16<def> = MOV64ri <ga:@BZ2_bzopen>; GR64:%vreg16
112B		%vreg17<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg17
128B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
144B		%RDI<def> = COPY %vreg16<kill>; GR64:%vreg16
160B		%RSI<def> = COPY %vreg17<kill>; GR64:%vreg17
176B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
192B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
240B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
256B		STACKMAP 0, 0, %vreg3, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack0] GR64:%vreg3,%vreg1
272B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
288B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1<kill>; mem:ST8[%path.addr] GR64:%vreg1
304B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg3<kill>; mem:ST8[%mode.addr] GR64:%vreg3
320B		%vreg14<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%path.addr] GR64:%vreg14
336B		%vreg13<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%mode.addr] GR64:%vreg13
352B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
384B		%ESI<def> = MOV32ri 4294967295
416B		%ECX<def> = MOV32r0 %EFLAGS<imp-def,dead>
420B		%RDI<def> = COPY %vreg14<kill>; GR64:%vreg14
424B		%RDX<def> = COPY %vreg13<kill>; GR64:%vreg13
432B		CALL64pcrel32 <ga:@bzopen_or_bzdopen>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %RDX<imp-use>, %ECX<imp-use,kill>, %RAX<imp-def>
448B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
464B		%vreg12<def> = COPY %RAX<kill>; GR64:%vreg12
480B		%vreg6<def> = MOV64ri <ga:@BZ2_bzopen>; GR64:%vreg6
512B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
528B		STACKMAP 1, 0, ...
544B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
560B		%vreg7<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg7
576B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
592B		%RDI<def> = COPY %vreg6<kill>; GR64:%vreg6
608B		%RSI<def> = COPY %vreg7<kill>; GR64:%vreg7
624B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
640B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
656B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
672B		STACKMAP 2, 0, %vreg12, ...; GR64:%vreg12
688B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
704B		%RAX<def> = COPY %vreg12<kill>; GR64:%vreg12
720B		RETQ %RAX<imp-use,kill>
> %R14<def> = COPY %RSI
> %RBX<def> = COPY %RDI
> %RDI<def> = MOV64ri <ga:@BZ2_bzopen>
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 0, 0, %R14, 0, <fi#1>, 0, %RBX, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack0]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %RBX<kill>; mem:ST8[%path.addr]
> MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %R14<kill>; mem:ST8[%mode.addr]
> %RDI<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%path.addr]
> %RDX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%mode.addr]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %ESI<def> = MOV32ri 4294967295
> %ECX<def> = MOV32r0 %EFLAGS<imp-def,dead>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RDX<def> = COPY %RDX<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@bzopen_or_bzdopen>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %RDX<imp-use>, %ECX<imp-use,kill>, %RAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RBX<def> = COPY %RAX<kill>
> %RDI<def> = MOV64ri <ga:@BZ2_bzopen>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 1, 0, ...
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 2, 0, %RBX, ...
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RAX<def> = COPY %RBX<kill>
> RETQ %RAX<imp-use,kill>
Computing live-in reg-units in ABI blocks.
0B	BB#0 DIL#0 SIL#0 DH#0 DL#0 CH#0 CL#0
Created 6 new intervals.
********** INTERVALS **********
CH [0B,16r:0)[3840r,3872r:1)[4176r,4224r:2)  0@0B-phi 1@3840r 2@4176r
CL [0B,16r:0)[3840r,3872r:1)[4176r,4224r:2)  0@0B-phi 1@3840r 2@4176r
DH [0B,32r:0)[544r,560r:3)[3824r,3872r:1)[4160r,4224r:2)  0@0B-phi 1@3824r 2@4160r 3@544r
DIL [0B,64r:0)[208r,240r:11)[512r,560r:12)[1440r,1456r:1)[2064r,2096r:9)[2240r,2272r:10)[2528r,2560r:8)[2992r,3024r:7)[3232r,3264r:2)[3792r,3872r:5)[4128r,4224r:6)[4560r,4576r:4)[4848r,4880r:3)  0@0B-phi 1@1440r 2@3232r 3@4848r 4@4560r 5@3792r 6@4128r 7@2992r 8@2528r 9@2064r 10@2240r 11@208r 12@512r
DL [0B,32r:0)[544r,560r:3)[3824r,3872r:1)[4160r,4224r:2)  0@0B-phi 1@3824r 2@4160r 3@544r
SIL [0B,48r:0)[224r,240r:10)[528r,560r:1)[2080r,2096r:8)[2256r,2272r:9)[2544r,2560r:6)[3008r,3024r:5)[3248r,3264r:7)[3808r,3872r:3)[4144r,4224r:4)[4864r,4880r:2)  0@0B-phi 1@528r 2@4864r 3@3808r 4@4144r 5@3008r 6@2544r 7@3248r 8@2080r 9@2256r 10@224r
%vreg2 [2880r,2896r:0)  0@2880r
%vreg3 [64r,80r:0)  0@64r
%vreg4 [80r,384r:0)  0@80r
%vreg5 [48r,96r:0)  0@48r
%vreg6 [96r,400r:0)  0@96r
%vreg7 [32r,112r:0)  0@32r
%vreg8 [112r,416r:0)  0@112r
%vreg9 [16r,128r:0)  0@16r
%vreg10 [128r,432r:0)  0@128r
%vreg13 [272r,528r:0)  0@272r
%vreg14 [288r,304r:0)  0@288r
%vreg15 [304r,544r:0)  0@304r
%vreg16 [320r,480r:0)  0@320r
%vreg17 [480r,512r:0)  0@480r
%vreg18 [144r,160r:0)  0@144r
%vreg19 [160r,208r:0)  0@160r
%vreg20 [176r,224r:0)  0@176r
%vreg23 [816r,832r:0)  0@816r
%vreg26 [2144r,2256r:0)  0@2144r
%vreg27 [2304r,2304d:0)  0@2304r
%vreg28 [2160r,2240r:0)  0@2160r
%vreg31 [2128r,2128d:0)  0@2128r
%vreg33 [1952r,2016r:0)  0@1952r
%vreg34 [1968r,2032r:0)  0@1968r
%vreg35 [2016r,2032r:0)[2032r,2080r:1)  0@2016r 1@2032r
%vreg36 [1984r,2064r:0)  0@1984r
%vreg40 [3296r,3360r:0)  0@3296r
%vreg41 [3184r,3248r:0)  0@3184r
%vreg42 [3200r,3232r:0)  0@3200r
%vreg44 [2608r,2672r:0)  0@2608r
%vreg46 [2496r,2512r:0)  0@2496r
%vreg47 [2512r,2544r:0)  0@2512r
%vreg48 [2592r,2608r:0)  0@2592r
%vreg49 [2464r,2528r:0)  0@2464r
%vreg53 [3056r,3120r:0)  0@3056r
%vreg54 [2944r,3008r:0)  0@2944r
%vreg55 [2960r,2992r:0)  0@2960r
%vreg57 [2832r,2848r:0)  0@2832r
%vreg58 [2768r,2784r:0)  0@2768r
%vreg62 [4016r,4128r:0)  0@4016r
%vreg68 [4256r,4320r:0)  0@4256r
%vreg69 [4096r,4208r:0)  0@4096r
%vreg70 [4032r,4192r:0)  0@4032r
%vreg71 [4080r,4176r:0)  0@4080r
%vreg72 [4064r,4160r:0)  0@4064r
%vreg73 [4048r,4144r:0)  0@4048r
%vreg77 [3696r,3792r:0)  0@3696r
%vreg82 [3904r,3968r:0)  0@3904r
%vreg83 [3760r,3856r:0)  0@3760r
%vreg84 [3744r,3840r:0)  0@3744r
%vreg85 [3728r,3824r:0)  0@3728r
%vreg86 [3712r,3808r:0)  0@3712r
%vreg89 [4736r,4752r:0)  0@4736r
%vreg92 [4400r,4416r:0)  0@4400r
%vreg95 [4464r,4480r:0)  0@4464r
%vreg97 [4608r,4608d:0)  0@4608r
%vreg98 [4528r,4560r:0)  0@4528r
%vreg99 [896r,1072r:0)  0@896r
%vreg100 [880r,896r:0)  0@880r
%vreg101 [912r,928r:0)[928r,928d:1)  0@912r 1@928r
%vreg102 [992r,1008r:0)[1008r,1008d:1)  0@992r 1@1008r
%vreg103 [1072r,1088r:0)[1088r,1088d:1)  0@1072r 1@1088r
%vreg104 [1296r,1312r:0)  0@1296r
%vreg105 [1312r,1328r:0)  0@1312r
%vreg108 [1648r,1664r:0)[1664r,1680r:1)  0@1648r 1@1664r
%vreg110 [1632r,1648r:0)  0@1632r
%vreg112 [1616r,1632r:0)  0@1616r
%vreg115 [1488r,1552r:0)  0@1488r
%vreg117 [1408r,1440r:0)  0@1408r
%vreg119 [1392r,1408r:0)  0@1392r
%vreg122 [1760r,1776r:0)[1776r,1792r:1)  0@1760r 1@1776r
%vreg124 [1744r,1760r:0)  0@1744r
%vreg126 [1728r,1744r:0)  0@1728r
%vreg129 [1872r,1888r:0)[1888r,1904r:1)  0@1872r 1@1888r
%vreg130 [1856r,1872r:0)  0@1856r
%vreg132 [4960r,4976r:0)  0@4960r
%vreg133 [4784r,4800r:0)  0@4784r
%vreg134 [4800r,4848r:0)  0@4800r
%vreg135 [4816r,4864r:0)  0@4816r
%vreg136 [2784r,2816B:1)[2848r,2864B:0)[2864B,2880r:2)  0@2848r 1@2784r 2@2864B-phi
RegMasks: 240r 560r 1456r 2096r 2272r 2560r 3024r 3264r 3872r 4224r 4576r 4880r
********** MACHINEINSTRS **********
# Machine code for function bzopen_or_bzdopen: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=8, align=8, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=4, align=4, at location [SP+8]
  fi#3: size=8, align=8, at location [SP+8]
  fi#4: size=4, align=4, at location [SP+8]
  fi#5: size=4, align=4, at location [SP+8]
  fi#6: size=5000, align=16, at location [SP+8]
  fi#7: size=4, align=4, at location [SP+8]
  fi#8: size=4, align=4, at location [SP+8]
  fi#9: size=10, align=1, at location [SP+8]
  fi#10: size=8, align=8, at location [SP+8]
  fi#11: size=8, align=8, at location [SP+8]
  fi#12: size=4, align=4, at location [SP+8]
  fi#13: size=4, align=4, at location [SP+8]
  fi#14: size=4, align=4, at location [SP+8]
  fi#15: size=4, align=4, at location [SP+8]
Function Live Ins: %RDI in %vreg3, %ESI in %vreg5, %RDX in %vreg7, %ECX in %vreg9

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI %ESI %RDX %ECX
16B		%vreg9<def> = COPY %ECX; GR32:%vreg9
32B		%vreg7<def> = COPY %RDX; GR64:%vreg7
48B		%vreg5<def> = COPY %ESI; GR32:%vreg5
64B		%vreg3<def> = COPY %RDI; GR64:%vreg3
80B		%vreg4<def> = COPY %vreg3; GR64:%vreg4,%vreg3
96B		%vreg6<def> = COPY %vreg5; GR32:%vreg6,%vreg5
112B		%vreg8<def> = COPY %vreg7; GR64:%vreg8,%vreg7
128B		%vreg10<def> = COPY %vreg9; GR32:%vreg10,%vreg9
144B		%vreg18<def> = MOV64ri <ga:@bzopen_or_bzdopen>; GR64:%vreg18
160B		%vreg19<def> = COPY %vreg18; GR64:%vreg19,%vreg18
176B		%vreg20<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg20
192B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
208B		%RDI<def> = COPY %vreg19; GR64:%vreg19
224B		%RSI<def> = COPY %vreg20; GR64:%vreg20
240B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
256B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
272B		%vreg13<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg13
288B		%vreg14<def> = MOV32ri 10; GR32:%vreg14
304B		%vreg15<def> = SUBREG_TO_REG 0, %vreg14, 4; GR64:%vreg15 GR32:%vreg14
320B		%vreg16<def> = LEA64r <fi#9>, 1, %noreg, 0, %noreg; GR64:%vreg16
336B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
352B		STACKMAP 0, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, %vreg6, 0, <fi#2>, 0, 0, <fi#10>, 0, %vreg8, 0, <fi#3>, 0, 0, <fi#9>, 0, 0, <fi#15>, 0, %vreg10, 0, <fi#4>, 0, %vreg4, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack2](align=4) LD8[FixedStack10] LD8[FixedStack3] LD8[FixedStack9](align=1) LD8[FixedStack15](align=4) LD8[FixedStack4](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4) GR32:%vreg6,%vreg10 GR64:%vreg8,%vreg4
368B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
384B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg4; mem:ST8[%path.addr] GR64:%vreg4
400B		MOV32mr <fi#2>, 1, %noreg, 0, %noreg, %vreg6; mem:ST4[%fd.addr] GR32:%vreg6
416B		MOV64mr <fi#3>, 1, %noreg, 0, %noreg, %vreg8; mem:ST8[%mode.addr] GR64:%vreg8
432B		MOV32mr <fi#4>, 1, %noreg, 0, %noreg, %vreg10; mem:ST4[%open_mode.addr] GR32:%vreg10
448B		MOV32mi <fi#7>, 1, %noreg, 0, %noreg, 9; mem:ST4[%blockSize100k]
464B		MOV32mi <fi#8>, 1, %noreg, 0, %noreg, 0; mem:ST4[%writing]
480B		%vreg17<def> = COPY %vreg16; GR64:%vreg17,%vreg16
496B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
512B		%RDI<def> = COPY %vreg17; GR64:%vreg17
528B		%ESI<def> = COPY %vreg13; GR32:%vreg13
544B		%RDX<def> = COPY %vreg15; GR64:%vreg15
560B		CALL64pcrel32 <MCSym=memset>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %RDX<imp-use>
576B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
592B		MOV64mi32 <fi#10>, 1, %noreg, 0, %noreg, 0; mem:ST8[%fp]
608B		MOV64mi32 <fi#11>, 1, %noreg, 0, %noreg, 0; mem:ST8[%bzfp]
624B		MOV32mi <fi#12>, 1, %noreg, 0, %noreg, 0; mem:ST4[%verbosity]
640B		MOV32mi <fi#13>, 1, %noreg, 0, %noreg, 30; mem:ST4[%workFactor]
656B		MOV32mi <fi#14>, 1, %noreg, 0, %noreg, 0; mem:ST4[%smallMode]
672B		MOV32mi <fi#15>, 1, %noreg, 0, %noreg, 0; mem:ST4[%nUnused]
688B		CMP64mi8 <fi#3>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%mode.addr]
704B		JNE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

720B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
736B		MOV64mi32 <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST8[%retval]
752B		JMP_1 <BB#41>
	    Successors according to CFG: BB#41

768B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0
784B		JMP_1 <BB#3>
	    Successors according to CFG: BB#3

800B	BB#3: derived from LLVM BB %while.cond
	    Predecessors according to CFG: BB#2 BB#15
816B		%vreg23<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%mode.addr] GR64:%vreg23
832B		CMP8mi %vreg23, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD1[%2] GR64:%vreg23
848B		JE_1 <BB#16>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#16 BB#4

864B	BB#4: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#3
880B		%vreg100<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%mode.addr] GR64:%vreg100
896B		%vreg99<def> = MOVSX32rm8 %vreg100, 1, %noreg, 0, %noreg; mem:LD1[%4] GR32:%vreg99 GR64:%vreg100
912B		%vreg101<def> = COPY %vreg99; GR32:%vreg101,%vreg99
928B		%vreg101<def,dead,tied1> = SUB32ri8 %vreg101<tied0>, 114, %EFLAGS<imp-def>; GR32:%vreg101
944B		JE_1 <BB#7>, %EFLAGS<imp-use,kill>
960B		JMP_1 <BB#5>
	    Successors according to CFG: BB#7 BB#5

976B	BB#5: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#4
992B		%vreg102<def> = COPY %vreg99; GR32:%vreg102,%vreg99
1008B		%vreg102<def,dead,tied1> = SUB32ri8 %vreg102<tied0>, 115, %EFLAGS<imp-def>; GR32:%vreg102
1024B		JE_1 <BB#9>, %EFLAGS<imp-use,kill>
1040B		JMP_1 <BB#6>
	    Successors according to CFG: BB#9 BB#6

1056B	BB#6: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#5
1072B		%vreg103<def> = COPY %vreg99; GR32:%vreg103,%vreg99
1088B		%vreg103<def,dead,tied1> = SUB32ri8 %vreg103<tied0>, 119, %EFLAGS<imp-def>; GR32:%vreg103
1104B		JE_1 <BB#8>, %EFLAGS<imp-use,kill>
1120B		JMP_1 <BB#10>
	    Successors according to CFG: BB#8 BB#10

1136B	BB#7: derived from LLVM BB %sw.bb
	    Predecessors according to CFG: BB#4
1152B		MOV32mi <fi#8>, 1, %noreg, 0, %noreg, 0; mem:ST4[%writing]
1168B		JMP_1 <BB#15>
	    Successors according to CFG: BB#15

1184B	BB#8: derived from LLVM BB %sw.bb.1
	    Predecessors according to CFG: BB#6
1200B		MOV32mi <fi#8>, 1, %noreg, 0, %noreg, 1; mem:ST4[%writing]
1216B		JMP_1 <BB#15>
	    Successors according to CFG: BB#15

1232B	BB#9: derived from LLVM BB %sw.bb.2
	    Predecessors according to CFG: BB#5
1248B		MOV32mi <fi#14>, 1, %noreg, 0, %noreg, 1; mem:ST4[%smallMode]
1264B		JMP_1 <BB#15>
	    Successors according to CFG: BB#15

1280B	BB#10: derived from LLVM BB %sw.default
	    Predecessors according to CFG: BB#6
1296B		%vreg104<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg104
1312B		%vreg105<def> = COPY %vreg104:sub_8bit; GR8:%vreg105 GR32:%vreg104
1328B		TEST8ri %vreg105, 1, %EFLAGS<imp-def>; GR8:%vreg105
1344B		JNE_1 <BB#11>, %EFLAGS<imp-use,kill>
1360B		JMP_1 <BB#12>
	    Successors according to CFG: BB#12 BB#11

1376B	BB#11: derived from LLVM BB %cond.true
	    Predecessors according to CFG: BB#10
1392B		%vreg119<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%mode.addr] GR64:%vreg119
1408B		%vreg117<def> = MOVSX32rm8 %vreg119, 1, %noreg, 0, %noreg; mem:LD1[%6] GR32:%vreg117 GR64:%vreg119
1424B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1440B		%EDI<def> = COPY %vreg117; GR32:%vreg117
1456B		CALL64pcrel32 <ga:@isdigit>, <regmask>, %RSP<imp-use>, %EDI<imp-use>, %EAX<imp-def>
1472B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1488B		%vreg115<def> = COPY %EAX<kill>; GR32:%vreg115
1504B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1520B		STACKMAP 1, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#2>, 0, 0, <fi#10>, 0, 0, <fi#3>, 0, 0, <fi#9>, 0, 0, <fi#15>, 0, 0, <fi#4>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack2](align=4) LD8[FixedStack10] LD8[FixedStack3] LD8[FixedStack9](align=1) LD8[FixedStack15](align=4) LD8[FixedStack4](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)
1536B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1552B		CMP32ri8 %vreg115, 0, %EFLAGS<imp-def>; GR32:%vreg115
1568B		JNE_1 <BB#13>, %EFLAGS<imp-use,kill>
1584B		JMP_1 <BB#14>
	    Successors according to CFG: BB#13 BB#14

1600B	BB#12: derived from LLVM BB %cond.false
	    Predecessors according to CFG: BB#10
1616B		%vreg112<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%mode.addr] GR64:%vreg112
1632B		%vreg110<def> = MOVSX32rm8 %vreg112, 1, %noreg, 0, %noreg; mem:LD1[%8] GR32:%vreg110 GR64:%vreg112
1648B		%vreg108<def> = COPY %vreg110; GR32:%vreg108,%vreg110
1664B		%vreg108<def,tied1> = SUB32ri8 %vreg108<tied0>, 48, %EFLAGS<imp-def,dead>; GR32:%vreg108
1680B		CMP32ri8 %vreg108, 10, %EFLAGS<imp-def>; GR32:%vreg108
1696B		JAE_1 <BB#14>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#14 BB#13

1712B	BB#13: derived from LLVM BB %if.then.8
	    Predecessors according to CFG: BB#12 BB#11
1728B		%vreg126<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%mode.addr] GR64:%vreg126
1744B		%vreg124<def> = MOVSX32rm8 %vreg126, 1, %noreg, 0, %noreg; mem:LD1[%10] GR32:%vreg124 GR64:%vreg126
1760B		%vreg122<def> = COPY %vreg124; GR32:%vreg122,%vreg124
1776B		%vreg122<def,tied1> = SUB32ri8 %vreg122<tied0>, 48, %EFLAGS<imp-def,dead>; GR32:%vreg122
1792B		MOV32mr <fi#7>, 1, %noreg, 0, %noreg, %vreg122; mem:ST4[%blockSize100k] GR32:%vreg122
	    Successors according to CFG: BB#14

1808B	BB#14: derived from LLVM BB %if.end.11
	    Predecessors according to CFG: BB#12 BB#11 BB#13
1824B		JMP_1 <BB#15>
	    Successors according to CFG: BB#15

1840B	BB#15: derived from LLVM BB %sw.epilog
	    Predecessors according to CFG: BB#9 BB#8 BB#7 BB#14
1856B		%vreg130<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%mode.addr] GR64:%vreg130
1872B		%vreg129<def> = COPY %vreg130; GR64:%vreg129,%vreg130
1888B		%vreg129<def,tied1> = ADD64ri8 %vreg129<tied0>, 1, %EFLAGS<imp-def,dead>; GR64:%vreg129
1904B		MOV64mr <fi#3>, 1, %noreg, 0, %noreg, %vreg129; mem:ST8[%mode.addr] GR64:%vreg129
1920B		JMP_1 <BB#3>
	    Successors according to CFG: BB#3

1936B	BB#16: derived from LLVM BB %while.end
	    Predecessors according to CFG: BB#3
1952B		%vreg33<def> = MOV64ri <ga:@bzlib__str_7_r_>; GR64:%vreg33
1968B		%vreg34<def> = MOV64ri <ga:@bzlib__str_6_w_>; GR64:%vreg34
1984B		%vreg36<def> = LEA64r <fi#9>, 1, %noreg, 0, %noreg; GR64:%vreg36
2000B		CMP32mi8 <fi#8>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%writing]
2016B		%vreg35<def> = COPY %vreg33; GR64:%vreg35,%vreg33
2032B		%vreg35<def,tied1> = CMOVNE64rr %vreg35<tied0>, %vreg34, %EFLAGS<imp-use,kill>; GR64:%vreg35,%vreg34
2048B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2064B		%RDI<def> = COPY %vreg36; GR64:%vreg36
2080B		%RSI<def> = COPY %vreg35; GR64:%vreg35
2096B		CALL64pcrel32 <ga:@strcat>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %RAX<imp-def>
2112B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2128B		%vreg31<def,dead> = COPY %RAX<kill>; GR64:%vreg31
2144B		%vreg26<def> = MOV64ri <ga:@bzlib__str_8_b_>; GR64:%vreg26
2160B		%vreg28<def> = LEA64r <fi#9>, 1, %noreg, 0, %noreg; GR64:%vreg28
2176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2192B		STACKMAP 2, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#2>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, 0, <fi#15>, 0, 0, <fi#4>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack2](align=4) LD8[FixedStack10] LD8[FixedStack9](align=1) LD8[FixedStack15](align=4) LD8[FixedStack4](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)
2208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2224B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2240B		%RDI<def> = COPY %vreg28; GR64:%vreg28
2256B		%RSI<def> = COPY %vreg26; GR64:%vreg26
2272B		CALL64pcrel32 <ga:@strcat>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %RAX<imp-def>
2288B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2304B		%vreg27<def,dead> = COPY %RAX<kill>; GR64:%vreg27
2320B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2336B		STACKMAP 3, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#2>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, 0, <fi#15>, 0, 0, <fi#4>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack2](align=4) LD8[FixedStack10] LD8[FixedStack9](align=1) LD8[FixedStack15](align=4) LD8[FixedStack4](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)
2352B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2368B		CMP32mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%open_mode.addr]
2384B		JNE_1 <BB#25>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#25 BB#17

2400B	BB#17: derived from LLVM BB %if.then.18
	    Predecessors according to CFG: BB#16
2416B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%path.addr]
2432B		JE_1 <BB#19>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#19 BB#18

2448B	BB#18: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#17
2464B		%vreg49<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%path.addr] GR64:%vreg49
2480B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2496B		%vreg46<def> = MOV32ri64 <ga:@bzlib__str_9_>; GR32:%vreg46
2512B		%vreg47<def> = SUBREG_TO_REG 0, %vreg46, 4; GR64:%vreg47 GR32:%vreg46
2528B		%RDI<def> = COPY %vreg49; GR64:%vreg49
2544B		%RSI<def> = COPY %vreg47; GR64:%vreg47
2560B		CALL64pcrel32 <ga:@strcmp>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %RSP<imp-def>, %EAX<imp-def>
2576B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2592B		%vreg48<def> = COPY %EAX<kill>; GR32:%vreg48
2608B		%vreg44<def> = COPY %vreg48; GR32:%vreg44,%vreg48
2624B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2640B		STACKMAP 4, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, 0, <fi#15>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack9](align=1) LD8[FixedStack15](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)
2656B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2672B		CMP32ri8 %vreg44, 0, %EFLAGS<imp-def>; GR32:%vreg44
2688B		JNE_1 <BB#23>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#23 BB#19

2704B	BB#19: derived from LLVM BB %if.then.24
	    Predecessors according to CFG: BB#17 BB#18
2720B		CMP32mi8 <fi#8>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%writing]
2736B		JE_1 <BB#21>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#21 BB#20

2752B	BB#20: derived from LLVM BB %cond.true.26
	    Predecessors according to CFG: BB#19
2768B		%vreg58<def> = MOV64rm %noreg, 1, %noreg, <ga:@stdout>, %noreg; mem:LD8[@stdout] GR64:%vreg58
2784B		%vreg136<def> = COPY %vreg58; GR64:%vreg136,%vreg58
2800B		JMP_1 <BB#22>
	    Successors according to CFG: BB#22

2816B	BB#21: derived from LLVM BB %cond.false.27
	    Predecessors according to CFG: BB#19
2832B		%vreg57<def> = MOV64rm %noreg, 1, %noreg, <ga:@stdin>, %noreg; mem:LD8[@stdin] GR64:%vreg57
2848B		%vreg136<def> = COPY %vreg57; GR64:%vreg136,%vreg57
	    Successors according to CFG: BB#22

2864B	BB#22: derived from LLVM BB %cond.end
	    Predecessors according to CFG: BB#21 BB#20
2880B		%vreg2<def> = COPY %vreg136; GR64:%vreg2,%vreg136
2896B		MOV64mr <fi#10>, 1, %noreg, 0, %noreg, %vreg2; mem:ST8[%fp] GR64:%vreg2
2912B		JMP_1 <BB#24>
	    Successors according to CFG: BB#24

2928B	BB#23: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#18
2944B		%vreg54<def> = LEA64r <fi#9>, 1, %noreg, 0, %noreg; GR64:%vreg54
2960B		%vreg55<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%path.addr] GR64:%vreg55
2976B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2992B		%RDI<def> = COPY %vreg55; GR64:%vreg55
3008B		%RSI<def> = COPY %vreg54; GR64:%vreg54
3024B		CALL64pcrel32 <ga:@fopen>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %RAX<imp-def>
3040B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3056B		%vreg53<def> = COPY %RAX<kill>; GR64:%vreg53
3072B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3088B		STACKMAP 5, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#15>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack15](align=4) LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)
3104B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3120B		MOV64mr <fi#10>, 1, %noreg, 0, %noreg, %vreg53; mem:ST8[%fp] GR64:%vreg53
	    Successors according to CFG: BB#24

3136B	BB#24: derived from LLVM BB %if.end.31
	    Predecessors according to CFG: BB#23 BB#22
3152B		JMP_1 <BB#26>
	    Successors according to CFG: BB#26

3168B	BB#25: derived from LLVM BB %if.else.32
	    Predecessors according to CFG: BB#16
3184B		%vreg41<def> = LEA64r <fi#9>, 1, %noreg, 0, %noreg; GR64:%vreg41
3200B		%vreg42<def> = MOV32rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD4[%fd.addr] GR32:%vreg42
3216B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3232B		%EDI<def> = COPY %vreg42; GR32:%vreg42
3248B		%RSI<def> = COPY %vreg41; GR64:%vreg41
3264B		CALL64pcrel32 <ga:@fdopen>, <regmask>, %RSP<imp-use>, %EDI<imp-use>, %RSI<imp-use>, %RAX<imp-def>
3280B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3296B		%vreg40<def> = COPY %RAX<kill>; GR64:%vreg40
3312B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3328B		STACKMAP 6, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#15>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack15](align=4) LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)
3344B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3360B		MOV64mr <fi#10>, 1, %noreg, 0, %noreg, %vreg40; mem:ST8[%fp] GR64:%vreg40
	    Successors according to CFG: BB#26

3376B	BB#26: derived from LLVM BB %if.end.35
	    Predecessors according to CFG: BB#25 BB#24
3392B		CMP64mi8 <fi#10>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%fp]
3408B		JNE_1 <BB#28>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#28 BB#27

3424B	BB#27: derived from LLVM BB %if.then.38
	    Predecessors according to CFG: BB#26
3440B		MOV64mi32 <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST8[%retval]
3456B		JMP_1 <BB#41>
	    Successors according to CFG: BB#41

3472B	BB#28: derived from LLVM BB %if.end.39
	    Predecessors according to CFG: BB#26
3488B		CMP32mi8 <fi#8>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%writing]
3504B		JE_1 <BB#34>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#34 BB#29

3520B	BB#29: derived from LLVM BB %if.then.41
	    Predecessors according to CFG: BB#28
3536B		CMP32mi8 <fi#7>, 1, %noreg, 0, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%blockSize100k]
3552B		JGE_1 <BB#31>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#31 BB#30

3568B	BB#30: derived from LLVM BB %if.then.44
	    Predecessors according to CFG: BB#29
3584B		MOV32mi <fi#7>, 1, %noreg, 0, %noreg, 1; mem:ST4[%blockSize100k]
	    Successors according to CFG: BB#31

3600B	BB#31: derived from LLVM BB %if.end.45
	    Predecessors according to CFG: BB#29 BB#30
3616B		CMP32mi8 <fi#7>, 1, %noreg, 0, %noreg, 9, %EFLAGS<imp-def>; mem:LD4[%blockSize100k]
3632B		JLE_1 <BB#33>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#33 BB#32

3648B	BB#32: derived from LLVM BB %if.then.48
	    Predecessors according to CFG: BB#31
3664B		MOV32mi <fi#7>, 1, %noreg, 0, %noreg, 9; mem:ST4[%blockSize100k]
	    Successors according to CFG: BB#33

3680B	BB#33: derived from LLVM BB %if.end.49
	    Predecessors according to CFG: BB#31 BB#32
3696B		%vreg77<def> = LEA64r <fi#5>, 1, %noreg, 0, %noreg; GR64:%vreg77
3712B		%vreg86<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%fp] GR64:%vreg86
3728B		%vreg85<def> = MOV32rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD4[%blockSize100k] GR32:%vreg85
3744B		%vreg84<def> = MOV32rm <fi#12>, 1, %noreg, 0, %noreg; mem:LD4[%verbosity] GR32:%vreg84
3760B		%vreg83<def> = MOV32rm <fi#13>, 1, %noreg, 0, %noreg; mem:LD4[%workFactor] GR32:%vreg83
3776B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3792B		%RDI<def> = COPY %vreg77; GR64:%vreg77
3808B		%RSI<def> = COPY %vreg86; GR64:%vreg86
3824B		%EDX<def> = COPY %vreg85; GR32:%vreg85
3840B		%ECX<def> = COPY %vreg84; GR32:%vreg84
3856B		%R8D<def> = COPY %vreg83; GR32:%vreg83
3872B		CALL64pcrel32 <ga:@BZ2_bzWriteOpen>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %EDX<imp-use>, %ECX<imp-use>, %R8D<imp-use,kill>, %RAX<imp-def>
3888B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3904B		%vreg82<def> = COPY %RAX<kill>; GR64:%vreg82
3920B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3936B		STACKMAP 7, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack0]
3952B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3968B		MOV64mr <fi#11>, 1, %noreg, 0, %noreg, %vreg82; mem:ST8[%bzfp] GR64:%vreg82
3984B		JMP_1 <BB#35>
	    Successors according to CFG: BB#35

4000B	BB#34: derived from LLVM BB %if.else.51
	    Predecessors according to CFG: BB#28
4016B		%vreg62<def> = LEA64r <fi#5>, 1, %noreg, 0, %noreg; GR64:%vreg62
4032B		%vreg70<def> = LEA64r <fi#6>, 1, %noreg, 0, %noreg; GR64:%vreg70
4048B		%vreg73<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%fp] GR64:%vreg73
4064B		%vreg72<def> = MOV32rm <fi#12>, 1, %noreg, 0, %noreg; mem:LD4[%verbosity] GR32:%vreg72
4080B		%vreg71<def> = MOV32rm <fi#14>, 1, %noreg, 0, %noreg; mem:LD4[%smallMode] GR32:%vreg71
4096B		%vreg69<def> = MOV32rm <fi#15>, 1, %noreg, 0, %noreg; mem:LD4[%nUnused] GR32:%vreg69
4112B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4128B		%RDI<def> = COPY %vreg62; GR64:%vreg62
4144B		%RSI<def> = COPY %vreg73; GR64:%vreg73
4160B		%EDX<def> = COPY %vreg72; GR32:%vreg72
4176B		%ECX<def> = COPY %vreg71; GR32:%vreg71
4192B		%R8<def> = COPY %vreg70; GR64:%vreg70
4208B		%R9D<def> = COPY %vreg69; GR32:%vreg69
4224B		CALL64pcrel32 <ga:@BZ2_bzReadOpen>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %EDX<imp-use>, %ECX<imp-use>, %R8<imp-use,kill>, %R9D<imp-use,kill>, %RAX<imp-def>
4240B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4256B		%vreg68<def> = COPY %RAX<kill>; GR64:%vreg68
4272B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4288B		STACKMAP 8, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack0]
4304B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4320B		MOV64mr <fi#11>, 1, %noreg, 0, %noreg, %vreg68; mem:ST8[%bzfp] GR64:%vreg68
	    Successors according to CFG: BB#35

4336B	BB#35: derived from LLVM BB %if.end.54
	    Predecessors according to CFG: BB#34 BB#33
4352B		CMP64mi8 <fi#11>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzfp]
4368B		JNE_1 <BB#40>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#40 BB#36

4384B	BB#36: derived from LLVM BB %if.then.57
	    Predecessors according to CFG: BB#35
4400B		%vreg92<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%fp] GR64:%vreg92
4416B		CMP64rm %vreg92, %noreg, 1, %noreg, <ga:@stdin>, %noreg, %EFLAGS<imp-def>; mem:LD8[@stdin] GR64:%vreg92
4432B		JE_1 <BB#39>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#39 BB#37

4448B	BB#37: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#36
4464B		%vreg95<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%fp] GR64:%vreg95
4480B		CMP64rm %vreg95, %noreg, 1, %noreg, <ga:@stdout>, %noreg, %EFLAGS<imp-def>; mem:LD8[@stdout] GR64:%vreg95
4496B		JE_1 <BB#39>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#39 BB#38

4512B	BB#38: derived from LLVM BB %if.then.62
	    Predecessors according to CFG: BB#37
4528B		%vreg98<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%fp] GR64:%vreg98
4544B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4560B		%RDI<def> = COPY %vreg98; GR64:%vreg98
4576B		CALL64pcrel32 <ga:@fclose>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
4592B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4608B		%vreg97<def,dead> = COPY %EAX<kill>; GR32:%vreg97
4624B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4640B		STACKMAP 9, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0]
4656B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#39

4672B	BB#39: derived from LLVM BB %if.end.64
	    Predecessors according to CFG: BB#36 BB#37 BB#38
4688B		MOV64mi32 <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST8[%retval]
4704B		JMP_1 <BB#41>
	    Successors according to CFG: BB#41

4720B	BB#40: derived from LLVM BB %if.end.65
	    Predecessors according to CFG: BB#35
4736B		%vreg89<def> = MOV64rm <fi#11>, 1, %noreg, 0, %noreg; mem:LD8[%bzfp] GR64:%vreg89
4752B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg89; mem:ST8[%retval] GR64:%vreg89
	    Successors according to CFG: BB#41

4768B	BB#41: derived from LLVM BB %return
	    Predecessors according to CFG: BB#40 BB#39 BB#27 BB#1
4784B		%vreg133<def> = MOV64ri <ga:@bzopen_or_bzdopen>; GR64:%vreg133
4800B		%vreg134<def> = COPY %vreg133; GR64:%vreg134,%vreg133
4816B		%vreg135<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg135
4832B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4848B		%RDI<def> = COPY %vreg134; GR64:%vreg134
4864B		%RSI<def> = COPY %vreg135; GR64:%vreg135
4880B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
4896B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4912B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4928B		STACKMAP 10, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0]
4944B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4960B		%vreg132<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%retval] GR64:%vreg132
4976B		%RAX<def> = COPY %vreg132; GR64:%vreg132
4992B		RETQ %RAX<imp-use,kill>

# End machine code for function bzopen_or_bzdopen.

********** SIMPLE REGISTER COALESCING **********
********** Function: bzopen_or_bzdopen
********** JOINING INTERVALS ***********
sw.epilog:
while.cond:
if.end.11:
while.body:
while.body:
while.body:
sw.default:
cond.true:
1440B	%EDI<def> = COPY %vreg117; GR32:%vreg117
	Considering merging %vreg117 with %EDI
	Can only merge into reserved registers.
1488B	%vreg115<def> = COPY %EAX<kill>; GR32:%vreg115
	Considering merging %vreg115 with %EAX
	Can only merge into reserved registers.
cond.false:
if.then.8:
sw.bb:
sw.bb.1:
sw.bb.2:
1872B	%vreg129<def> = COPY %vreg130; GR64:%vreg129,%vreg130
	Considering merging to GR64 with %vreg130 in %vreg129
		RHS = %vreg130 [1856r,1872r:0)  0@1856r
		LHS = %vreg129 [1872r,1888r:0)[1888r,1904r:1)  0@1872r 1@1888r
		merge %vreg129:0@1872r into %vreg130:0@1856r --> @1856r
		erased:	1872r	%vreg129<def> = COPY %vreg130; GR64:%vreg129,%vreg130
		updated: 1856B	%vreg129<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%mode.addr] GR64:%vreg129
	Success: %vreg130 -> %vreg129
	Result = %vreg129 [1856r,1888r:0)[1888r,1904r:1)  0@1856r 1@1888r
912B	%vreg101<def> = COPY %vreg99; GR32:%vreg101,%vreg99
	Considering merging to GR32 with %vreg99 in %vreg101
		RHS = %vreg99 [896r,1072r:0)  0@896r
		LHS = %vreg101 [912r,928r:0)[928r,928d:1)  0@912r 1@928r
		merge %vreg101:0@912r into %vreg99:0@896r --> @896r
		interference at %vreg101:1@928r
	Interference!
992B	%vreg102<def> = COPY %vreg99; GR32:%vreg102,%vreg99
	Considering merging to GR32 with %vreg99 in %vreg102
		RHS = %vreg99 [896r,1072r:0)  0@896r
		LHS = %vreg102 [992r,1008r:0)[1008r,1008d:1)  0@992r 1@1008r
		merge %vreg102:0@992r into %vreg99:0@896r --> @896r
		interference at %vreg102:1@1008r
	Interference!
1072B	%vreg103<def> = COPY %vreg99; GR32:%vreg103,%vreg99
	Considering merging to GR32 with %vreg99 in %vreg103
		RHS = %vreg99 [896r,1072r:0)  0@896r
		LHS = %vreg103 [1072r,1088r:0)[1088r,1088d:1)  0@1072r 1@1088r
		merge %vreg103:0@1072r into %vreg99:0@896r --> @896r
		erased:	1072r	%vreg103<def> = COPY %vreg99; GR32:%vreg103,%vreg99
		updated: 896B	%vreg103<def> = MOVSX32rm8 %vreg100, 1, %noreg, 0, %noreg; mem:LD1[%4] GR32:%vreg103 GR64:%vreg100
		updated: 912B	%vreg101<def> = COPY %vreg103; GR32:%vreg101,%vreg103
		updated: 992B	%vreg102<def> = COPY %vreg103; GR32:%vreg102,%vreg103
	Success: %vreg99 -> %vreg103
	Result = %vreg103 [896r,1088r:0)[1088r,1088d:1)  0@896r 1@1088r
1312B	%vreg105<def> = COPY %vreg104:sub_8bit; GR8:%vreg105 GR32:%vreg104
	Considering merging to GR32 with %vreg105 in %vreg104:sub_8bit
		RHS = %vreg105 [1312r,1328r:0)  0@1312r
		LHS = %vreg104 [1296r,1312r:0)  0@1296r
		merge %vreg105:0@1312r into %vreg104:0@1296r --> @1296r
		erased:	1312r	%vreg105<def> = COPY %vreg104:sub_8bit; GR8:%vreg105 GR32:%vreg104
		updated: 1328B	TEST8ri %vreg104:sub_8bit, 1, %EFLAGS<imp-def>; GR32:%vreg104
	Success: %vreg105:sub_8bit -> %vreg104
	Result = %vreg104 [1296r,1328r:0)  0@1296r
1648B	%vreg108<def> = COPY %vreg110; GR32:%vreg108,%vreg110
	Considering merging to GR32 with %vreg110 in %vreg108
		RHS = %vreg110 [1632r,1648r:0)  0@1632r
		LHS = %vreg108 [1648r,1664r:0)[1664r,1680r:1)  0@1648r 1@1664r
		merge %vreg108:0@1648r into %vreg110:0@1632r --> @1632r
		erased:	1648r	%vreg108<def> = COPY %vreg110; GR32:%vreg108,%vreg110
		updated: 1632B	%vreg108<def> = MOVSX32rm8 %vreg112, 1, %noreg, 0, %noreg; mem:LD1[%8] GR32:%vreg108 GR64:%vreg112
	Success: %vreg110 -> %vreg108
	Result = %vreg108 [1632r,1664r:0)[1664r,1680r:1)  0@1632r 1@1664r
1760B	%vreg122<def> = COPY %vreg124; GR32:%vreg122,%vreg124
	Considering merging to GR32 with %vreg124 in %vreg122
		RHS = %vreg124 [1744r,1760r:0)  0@1744r
		LHS = %vreg122 [1760r,1776r:0)[1776r,1792r:1)  0@1760r 1@1776r
		merge %vreg122:0@1760r into %vreg124:0@1744r --> @1744r
		erased:	1760r	%vreg122<def> = COPY %vreg124; GR32:%vreg122,%vreg124
		updated: 1744B	%vreg122<def> = MOVSX32rm8 %vreg126, 1, %noreg, 0, %noreg; mem:LD1[%10] GR32:%vreg122 GR64:%vreg126
	Success: %vreg124 -> %vreg122
	Result = %vreg122 [1744r,1776r:0)[1776r,1792r:1)  0@1744r 1@1776r
if.then.24:
if.end.35:
if.end.45:
if.end.54:
if.end.64:
return:
4848B	%RDI<def> = COPY %vreg134; GR64:%vreg134
	Considering merging %vreg134 with %RDI
	Can only merge into reserved registers.
4864B	%RSI<def> = COPY %vreg135; GR64:%vreg135
	Considering merging %vreg135 with %RSI
	Can only merge into reserved registers.
4976B	%RAX<def> = COPY %vreg132; GR64:%vreg132
	Considering merging %vreg132 with %RAX
	Can only merge into reserved registers.
while.end:
2064B	%RDI<def> = COPY %vreg36; GR64:%vreg36
	Considering merging %vreg36 with %RDI
	Can only merge into reserved registers.
2080B	%RSI<def> = COPY %vreg35; GR64:%vreg35
	Considering merging %vreg35 with %RSI
	Can only merge into reserved registers.
2128B	%vreg31<def,dead> = COPY %RAX<kill>; GR64:%vreg31
	Considering merging %vreg31 with %RAX
	Can only merge into reserved registers.
2240B	%RDI<def> = COPY %vreg28; GR64:%vreg28
	Considering merging %vreg28 with %RDI
	Can only merge into reserved registers.
2256B	%RSI<def> = COPY %vreg26; GR64:%vreg26
	Considering merging %vreg26 with %RSI
	Can only merge into reserved registers.
2304B	%vreg27<def,dead> = COPY %RAX<kill>; GR64:%vreg27
	Considering merging %vreg27 with %RAX
	Can only merge into reserved registers.
if.then.18:
lor.lhs.false:
2512B	%vreg47<def> = SUBREG_TO_REG 0, %vreg46, 4; GR64:%vreg47 GR32:%vreg46
	Considering merging to GR64_with_sub_8bit with %vreg46 in %vreg47:sub_32bit
		RHS = %vreg46 [2496r,2512r:0)  0@2496r
		LHS = %vreg47 [2512r,2544r:0)  0@2512r
		merge %vreg47:0@2512r into %vreg46:0@2496r --> @2496r
		erased:	2512r	%vreg47<def> = SUBREG_TO_REG 0, %vreg46, 4; GR64:%vreg47 GR32:%vreg46
		updated: 2496B	%vreg47:sub_32bit<def,read-undef> = MOV32ri64 <ga:@bzlib__str_9_>; GR64_with_sub_8bit:%vreg47
	Success: %vreg46:sub_32bit -> %vreg47
	Result = %vreg47 [2496r,2544r:0)  0@2496r
2528B	%RDI<def> = COPY %vreg49; GR64:%vreg49
	Considering merging %vreg49 with %RDI
	Can only merge into reserved registers.
2544B	%RSI<def> = COPY %vreg47; GR64_with_sub_8bit:%vreg47
	Considering merging %vreg47 with %RSI
	Can only merge into reserved registers.
Remat: %ESI<def,dead> = MOV32ri64 <ga:@bzlib__str_9_>, %RSI<imp-def>
Shrink: %vreg47 [2496r,2544r:0)  0@2496r
All defs dead: 2496r	%vreg47:sub_32bit<def,read-undef,dead> = MOV32ri64 <ga:@bzlib__str_9_>; GR64_with_sub_8bit:%vreg47
Shrunk: %vreg47 [2496r,2496d:0)  0@2496r
Deleting dead def 2496r	%vreg47:sub_32bit<def,read-undef,dead> = MOV32ri64 <ga:@bzlib__str_9_>; GR64_with_sub_8bit:%vreg47
2592B	%vreg48<def> = COPY %EAX<kill>; GR32:%vreg48
	Considering merging %vreg48 with %EAX
	Can only merge into reserved registers.
cond.end:
if.end.31:
if.end.39:
if.then.41:
if.end.49:
3792B	%RDI<def> = COPY %vreg77; GR64:%vreg77
	Considering merging %vreg77 with %RDI
	Can only merge into reserved registers.
3808B	%RSI<def> = COPY %vreg86; GR64:%vreg86
	Considering merging %vreg86 with %RSI
	Can only merge into reserved registers.
3824B	%EDX<def> = COPY %vreg85; GR32:%vreg85
	Considering merging %vreg85 with %EDX
	Can only merge into reserved registers.
3840B	%ECX<def> = COPY %vreg84; GR32:%vreg84
	Considering merging %vreg84 with %ECX
	Can only merge into reserved registers.
3856B	%R8D<def> = COPY %vreg83; GR32:%vreg83
	Considering merging %vreg83 with %R8D
	Can only merge into reserved registers.
3904B	%vreg82<def> = COPY %RAX<kill>; GR64:%vreg82
	Considering merging %vreg82 with %RAX
	Can only merge into reserved registers.
if.then.57:
land.lhs.true:
entry:
16B	%vreg9<def> = COPY %ECX; GR32:%vreg9
	Considering merging %vreg9 with %ECX
	Can only merge into reserved registers.
32B	%vreg7<def> = COPY %RDX; GR64:%vreg7
	Considering merging %vreg7 with %RDX
	Can only merge into reserved registers.
48B	%vreg5<def> = COPY %ESI; GR32:%vreg5
	Considering merging %vreg5 with %ESI
	Can only merge into reserved registers.
64B	%vreg3<def> = COPY %RDI; GR64:%vreg3
	Considering merging %vreg3 with %RDI
	Can only merge into reserved registers.
208B	%RDI<def> = COPY %vreg19; GR64:%vreg19
	Considering merging %vreg19 with %RDI
	Can only merge into reserved registers.
224B	%RSI<def> = COPY %vreg20; GR64:%vreg20
	Considering merging %vreg20 with %RSI
	Can only merge into reserved registers.
304B	%vreg15<def> = SUBREG_TO_REG 0, %vreg14, 4; GR64:%vreg15 GR32:%vreg14
	Considering merging to GR64_with_sub_8bit with %vreg14 in %vreg15:sub_32bit
		RHS = %vreg14 [288r,304r:0)  0@288r
		LHS = %vreg15 [304r,544r:0)  0@304r
		merge %vreg15:0@304r into %vreg14:0@288r --> @288r
		erased:	304r	%vreg15<def> = SUBREG_TO_REG 0, %vreg14, 4; GR64:%vreg15 GR32:%vreg14
		updated: 288B	%vreg15:sub_32bit<def,read-undef> = MOV32ri 10; GR64_with_sub_8bit:%vreg15
	Success: %vreg14:sub_32bit -> %vreg15
	Result = %vreg15 [288r,544r:0)  0@288r
512B	%RDI<def> = COPY %vreg17; GR64:%vreg17
	Considering merging %vreg17 with %RDI
	Can only merge into reserved registers.
528B	%ESI<def> = COPY %vreg13; GR32:%vreg13
	Considering merging %vreg13 with %ESI
	Can only merge into reserved registers.
Remat: %ESI<def> = MOV32r0 %EFLAGS<imp-def,dead>
Shrink: %vreg13 [272r,528r:0)  0@272r
All defs dead: 272r	%vreg13<def,dead> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg13
Shrunk: %vreg13 [272r,272d:0)  0@272r
Deleting dead def 272r	%vreg13<def,dead> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg13
544B	%RDX<def> = COPY %vreg15; GR64_with_sub_8bit:%vreg15
	Considering merging %vreg15 with %RDX
	Can only merge into reserved registers.
Remat: %EDX<def,dead> = MOV32ri 10, %RDX<imp-def>
Shrink: %vreg15 [288r,544r:0)  0@288r
All defs dead: 288r	%vreg15:sub_32bit<def,read-undef,dead> = MOV32ri 10; GR64_with_sub_8bit:%vreg15
Shrunk: %vreg15 [288r,288d:0)  0@288r
Deleting dead def 288r	%vreg15:sub_32bit<def,read-undef,dead> = MOV32ri 10; GR64_with_sub_8bit:%vreg15
if.then:
if.end:
cond.true.26:
cond.false.27:
if.else:
2992B	%RDI<def> = COPY %vreg55; GR64:%vreg55
	Considering merging %vreg55 with %RDI
	Can only merge into reserved registers.
3008B	%RSI<def> = COPY %vreg54; GR64:%vreg54
	Considering merging %vreg54 with %RSI
	Can only merge into reserved registers.
3056B	%vreg53<def> = COPY %RAX<kill>; GR64:%vreg53
	Considering merging %vreg53 with %RAX
	Can only merge into reserved registers.
if.else.32:
3232B	%EDI<def> = COPY %vreg42; GR32:%vreg42
	Considering merging %vreg42 with %EDI
	Can only merge into reserved registers.
3248B	%RSI<def> = COPY %vreg41; GR64:%vreg41
	Considering merging %vreg41 with %RSI
	Can only merge into reserved registers.
3296B	%vreg40<def> = COPY %RAX<kill>; GR64:%vreg40
	Considering merging %vreg40 with %RAX
	Can only merge into reserved registers.
if.then.38:
if.then.44:
if.then.48:
if.else.51:
4128B	%RDI<def> = COPY %vreg62; GR64:%vreg62
	Considering merging %vreg62 with %RDI
	Can only merge into reserved registers.
4144B	%RSI<def> = COPY %vreg73; GR64:%vreg73
	Considering merging %vreg73 with %RSI
	Can only merge into reserved registers.
4160B	%EDX<def> = COPY %vreg72; GR32:%vreg72
	Considering merging %vreg72 with %EDX
	Can only merge into reserved registers.
4176B	%ECX<def> = COPY %vreg71; GR32:%vreg71
	Considering merging %vreg71 with %ECX
	Can only merge into reserved registers.
4192B	%R8<def> = COPY %vreg70; GR64:%vreg70
	Considering merging %vreg70 with %R8
	Can only merge into reserved registers.
4208B	%R9D<def> = COPY %vreg69; GR32:%vreg69
	Considering merging %vreg69 with %R9D
	Can only merge into reserved registers.
4256B	%vreg68<def> = COPY %RAX<kill>; GR64:%vreg68
	Considering merging %vreg68 with %RAX
	Can only merge into reserved registers.
if.then.62:
4560B	%RDI<def> = COPY %vreg98; GR64:%vreg98
	Considering merging %vreg98 with %RDI
	Can only merge into reserved registers.
4608B	%vreg97<def,dead> = COPY %EAX<kill>; GR32:%vreg97
	Considering merging %vreg97 with %EAX
	Can only merge into reserved registers.
if.end.65:
4800B	%vreg134<def> = COPY %vreg133; GR64:%vreg134,%vreg133
	Considering merging to GR64 with %vreg133 in %vreg134
		RHS = %vreg133 [4784r,4800r:0)  0@4784r
		LHS = %vreg134 [4800r,4848r:0)  0@4800r
		merge %vreg134:0@4800r into %vreg133:0@4784r --> @4784r
		erased:	4800r	%vreg134<def> = COPY %vreg133; GR64:%vreg134,%vreg133
		updated: 4784B	%vreg134<def> = MOV64ri <ga:@bzopen_or_bzdopen>; GR64:%vreg134
	Success: %vreg133 -> %vreg134
	Result = %vreg134 [4784r,4848r:0)  0@4784r
2016B	%vreg35<def> = COPY %vreg33; GR64:%vreg35,%vreg33
	Considering merging to GR64 with %vreg33 in %vreg35
		RHS = %vreg33 [1952r,2016r:0)  0@1952r
		LHS = %vreg35 [2016r,2032r:0)[2032r,2080r:1)  0@2016r 1@2032r
		merge %vreg35:0@2016r into %vreg33:0@1952r --> @1952r
		erased:	2016r	%vreg35<def> = COPY %vreg33; GR64:%vreg35,%vreg33
		updated: 1952B	%vreg35<def> = MOV64ri <ga:@bzlib__str_7_r_>; GR64:%vreg35
	Success: %vreg33 -> %vreg35
	Result = %vreg35 [1952r,2032r:0)[2032r,2080r:1)  0@1952r 1@2032r
2608B	%vreg44<def> = COPY %vreg48; GR32:%vreg44,%vreg48
	Considering merging to GR32 with %vreg48 in %vreg44
		RHS = %vreg48 [2592r,2608r:0)  0@2592r
		LHS = %vreg44 [2608r,2672r:0)  0@2608r
		merge %vreg44:0@2608r into %vreg48:0@2592r --> @2592r
		erased:	2608r	%vreg44<def> = COPY %vreg48; GR32:%vreg44,%vreg48
		updated: 2592B	%vreg44<def> = COPY %EAX<kill>; GR32:%vreg44
	Success: %vreg48 -> %vreg44
	Result = %vreg44 [2592r,2672r:0)  0@2592r
2880B	%vreg2<def> = COPY %vreg136; GR64:%vreg2,%vreg136
	Considering merging to GR64 with %vreg2 in %vreg136
		RHS = %vreg2 [2880r,2896r:0)  0@2880r
		LHS = %vreg136 [2784r,2816B:1)[2848r,2864B:0)[2864B,2880r:2)  0@2848r 1@2784r 2@2864B-phi
		merge %vreg2:0@2880r into %vreg136:2@2864B --> @2864B
		erased:	2880r	%vreg2<def> = COPY %vreg136; GR64:%vreg2,%vreg136
		updated: 2896B	MOV64mr <fi#10>, 1, %noreg, 0, %noreg, %vreg136; mem:ST8[%fp] GR64:%vreg136
	Success: %vreg2 -> %vreg136
	Result = %vreg136 [2784r,2816B:1)[2848r,2864B:0)[2864B,2896r:2)  0@2848r 1@2784r 2@2864B-phi
80B	%vreg4<def> = COPY %vreg3; GR64:%vreg4,%vreg3
	Considering merging to GR64 with %vreg3 in %vreg4
		RHS = %vreg3 [64r,80r:0)  0@64r
		LHS = %vreg4 [80r,384r:0)  0@80r
		merge %vreg4:0@80r into %vreg3:0@64r --> @64r
		erased:	80r	%vreg4<def> = COPY %vreg3; GR64:%vreg4,%vreg3
		updated: 64B	%vreg4<def> = COPY %RDI; GR64:%vreg4
	Success: %vreg3 -> %vreg4
	Result = %vreg4 [64r,384r:0)  0@64r
96B	%vreg6<def> = COPY %vreg5; GR32:%vreg6,%vreg5
	Considering merging to GR32 with %vreg5 in %vreg6
		RHS = %vreg5 [48r,96r:0)  0@48r
		LHS = %vreg6 [96r,400r:0)  0@96r
		merge %vreg6:0@96r into %vreg5:0@48r --> @48r
		erased:	96r	%vreg6<def> = COPY %vreg5; GR32:%vreg6,%vreg5
		updated: 48B	%vreg6<def> = COPY %ESI; GR32:%vreg6
	Success: %vreg5 -> %vreg6
	Result = %vreg6 [48r,400r:0)  0@48r
112B	%vreg8<def> = COPY %vreg7; GR64:%vreg8,%vreg7
	Considering merging to GR64 with %vreg7 in %vreg8
		RHS = %vreg7 [32r,112r:0)  0@32r
		LHS = %vreg8 [112r,416r:0)  0@112r
		merge %vreg8:0@112r into %vreg7:0@32r --> @32r
		erased:	112r	%vreg8<def> = COPY %vreg7; GR64:%vreg8,%vreg7
		updated: 32B	%vreg8<def> = COPY %RDX; GR64:%vreg8
	Success: %vreg7 -> %vreg8
	Result = %vreg8 [32r,416r:0)  0@32r
128B	%vreg10<def> = COPY %vreg9; GR32:%vreg10,%vreg9
	Considering merging to GR32 with %vreg9 in %vreg10
		RHS = %vreg9 [16r,128r:0)  0@16r
		LHS = %vreg10 [128r,432r:0)  0@128r
		merge %vreg10:0@128r into %vreg9:0@16r --> @16r
		erased:	128r	%vreg10<def> = COPY %vreg9; GR32:%vreg10,%vreg9
		updated: 16B	%vreg10<def> = COPY %ECX; GR32:%vreg10
	Success: %vreg9 -> %vreg10
	Result = %vreg10 [16r,432r:0)  0@16r
160B	%vreg19<def> = COPY %vreg18; GR64:%vreg19,%vreg18
	Considering merging to GR64 with %vreg18 in %vreg19
		RHS = %vreg18 [144r,160r:0)  0@144r
		LHS = %vreg19 [160r,208r:0)  0@160r
		merge %vreg19:0@160r into %vreg18:0@144r --> @144r
		erased:	160r	%vreg19<def> = COPY %vreg18; GR64:%vreg19,%vreg18
		updated: 144B	%vreg19<def> = MOV64ri <ga:@bzopen_or_bzdopen>; GR64:%vreg19
	Success: %vreg18 -> %vreg19
	Result = %vreg19 [144r,208r:0)  0@144r
480B	%vreg17<def> = COPY %vreg16; GR64:%vreg17,%vreg16
	Considering merging to GR64 with %vreg16 in %vreg17
		RHS = %vreg16 [320r,480r:0)  0@320r
		LHS = %vreg17 [480r,512r:0)  0@480r
		merge %vreg17:0@480r into %vreg16:0@320r --> @320r
		erased:	480r	%vreg17<def> = COPY %vreg16; GR64:%vreg17,%vreg16
		updated: 320B	%vreg17<def> = LEA64r <fi#9>, 1, %noreg, 0, %noreg; GR64:%vreg17
	Success: %vreg16 -> %vreg17
	Result = %vreg17 [320r,512r:0)  0@320r
2784B	%vreg136<def> = COPY %vreg58; GR64:%vreg136,%vreg58
	Considering merging to GR64 with %vreg58 in %vreg136
		RHS = %vreg58 [2768r,2784r:0)  0@2768r
		LHS = %vreg136 [2784r,2816B:1)[2848r,2864B:0)[2864B,2896r:2)  0@2848r 1@2784r 2@2864B-phi
		merge %vreg136:1@2784r into %vreg58:0@2768r --> @2768r
		erased:	2784r	%vreg136<def> = COPY %vreg58; GR64:%vreg136,%vreg58
		updated: 2768B	%vreg136<def> = MOV64rm %noreg, 1, %noreg, <ga:@stdout>, %noreg; mem:LD8[@stdout] GR64:%vreg136
	Success: %vreg58 -> %vreg136
	Result = %vreg136 [2768r,2816B:1)[2848r,2864B:0)[2864B,2896r:2)  0@2848r 1@2768r 2@2864B-phi
2848B	%vreg136<def> = COPY %vreg57; GR64:%vreg136,%vreg57
	Considering merging to GR64 with %vreg57 in %vreg136
		RHS = %vreg57 [2832r,2848r:0)  0@2832r
		LHS = %vreg136 [2768r,2816B:1)[2848r,2864B:0)[2864B,2896r:2)  0@2848r 1@2768r 2@2864B-phi
		merge %vreg136:0@2848r into %vreg57:0@2832r --> @2832r
		erased:	2848r	%vreg136<def> = COPY %vreg57; GR64:%vreg136,%vreg57
		updated: 2832B	%vreg136<def> = MOV64rm %noreg, 1, %noreg, <ga:@stdin>, %noreg; mem:LD8[@stdin] GR64:%vreg136
	Success: %vreg57 -> %vreg136
	Result = %vreg136 [2768r,2816B:1)[2832r,2864B:0)[2864B,2896r:2)  0@2832r 1@2768r 2@2864B-phi
912B	%vreg101<def> = COPY %vreg103; GR32:%vreg101,%vreg103
	Considering merging to GR32 with %vreg103 in %vreg101
		RHS = %vreg103 [896r,1088r:0)[1088r,1088d:1)  0@896r 1@1088r
		LHS = %vreg101 [912r,928r:0)[928r,928d:1)  0@912r 1@928r
		merge %vreg101:0@912r into %vreg103:0@896r --> @896r
		interference at %vreg101:1@928r
	Interference!
992B	%vreg102<def> = COPY %vreg103; GR32:%vreg102,%vreg103
	Considering merging to GR32 with %vreg103 in %vreg102
		RHS = %vreg103 [896r,1088r:0)[1088r,1088d:1)  0@896r 1@1088r
		LHS = %vreg102 [992r,1008r:0)[1008r,1008d:1)  0@992r 1@1008r
		merge %vreg102:0@992r into %vreg103:0@896r --> @896r
		interference at %vreg102:1@1008r
	Interference!
4848B	%RDI<def> = COPY %vreg134; GR64:%vreg134
	Considering merging %vreg134 with %RDI
	Can only merge into reserved registers.
208B	%RDI<def> = COPY %vreg19; GR64:%vreg19
	Considering merging %vreg19 with %RDI
	Can only merge into reserved registers.
512B	%RDI<def> = COPY %vreg17; GR64:%vreg17
	Considering merging %vreg17 with %RDI
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
CH [0B,16r:0)[3840r,3872r:1)[4176r,4224r:2)  0@0B-phi 1@3840r 2@4176r
CL [0B,16r:0)[3840r,3872r:1)[4176r,4224r:2)  0@0B-phi 1@3840r 2@4176r
DH [0B,32r:0)[544r,560r:3)[3824r,3872r:1)[4160r,4224r:2)  0@0B-phi 1@3824r 2@4160r 3@544r
DIL [0B,64r:0)[208r,240r:11)[512r,560r:12)[1440r,1456r:1)[2064r,2096r:9)[2240r,2272r:10)[2528r,2560r:8)[2992r,3024r:7)[3232r,3264r:2)[3792r,3872r:5)[4128r,4224r:6)[4560r,4576r:4)[4848r,4880r:3)  0@0B-phi 1@1440r 2@3232r 3@4848r 4@4560r 5@3792r 6@4128r 7@2992r 8@2528r 9@2064r 10@2240r 11@208r 12@512r
DL [0B,32r:0)[544r,560r:3)[3824r,3872r:1)[4160r,4224r:2)  0@0B-phi 1@3824r 2@4160r 3@544r
SIL [0B,48r:0)[224r,240r:10)[528r,560r:1)[2080r,2096r:8)[2256r,2272r:9)[2544r,2560r:6)[3008r,3024r:5)[3248r,3264r:7)[3808r,3872r:3)[4144r,4224r:4)[4864r,4880r:2)  0@0B-phi 1@528r 2@4864r 3@3808r 4@4144r 5@3008r 6@2544r 7@3248r 8@2080r 9@2256r 10@224r
%vreg4 [64r,384r:0)  0@64r
%vreg6 [48r,400r:0)  0@48r
%vreg8 [32r,416r:0)  0@32r
%vreg10 [16r,432r:0)  0@16r
%vreg17 [320r,512r:0)  0@320r
%vreg19 [144r,208r:0)  0@144r
%vreg20 [176r,224r:0)  0@176r
%vreg23 [816r,832r:0)  0@816r
%vreg26 [2144r,2256r:0)  0@2144r
%vreg27 [2304r,2304d:0)  0@2304r
%vreg28 [2160r,2240r:0)  0@2160r
%vreg31 [2128r,2128d:0)  0@2128r
%vreg34 [1968r,2032r:0)  0@1968r
%vreg35 [1952r,2032r:0)[2032r,2080r:1)  0@1952r 1@2032r
%vreg36 [1984r,2064r:0)  0@1984r
%vreg40 [3296r,3360r:0)  0@3296r
%vreg41 [3184r,3248r:0)  0@3184r
%vreg42 [3200r,3232r:0)  0@3200r
%vreg44 [2592r,2672r:0)  0@2592r
%vreg49 [2464r,2528r:0)  0@2464r
%vreg53 [3056r,3120r:0)  0@3056r
%vreg54 [2944r,3008r:0)  0@2944r
%vreg55 [2960r,2992r:0)  0@2960r
%vreg62 [4016r,4128r:0)  0@4016r
%vreg68 [4256r,4320r:0)  0@4256r
%vreg69 [4096r,4208r:0)  0@4096r
%vreg70 [4032r,4192r:0)  0@4032r
%vreg71 [4080r,4176r:0)  0@4080r
%vreg72 [4064r,4160r:0)  0@4064r
%vreg73 [4048r,4144r:0)  0@4048r
%vreg77 [3696r,3792r:0)  0@3696r
%vreg82 [3904r,3968r:0)  0@3904r
%vreg83 [3760r,3856r:0)  0@3760r
%vreg84 [3744r,3840r:0)  0@3744r
%vreg85 [3728r,3824r:0)  0@3728r
%vreg86 [3712r,3808r:0)  0@3712r
%vreg89 [4736r,4752r:0)  0@4736r
%vreg92 [4400r,4416r:0)  0@4400r
%vreg95 [4464r,4480r:0)  0@4464r
%vreg97 [4608r,4608d:0)  0@4608r
%vreg98 [4528r,4560r:0)  0@4528r
%vreg100 [880r,896r:0)  0@880r
%vreg101 [912r,928r:0)[928r,928d:1)  0@912r 1@928r
%vreg102 [992r,1008r:0)[1008r,1008d:1)  0@992r 1@1008r
%vreg103 [896r,1088r:0)[1088r,1088d:1)  0@896r 1@1088r
%vreg104 [1296r,1328r:0)  0@1296r
%vreg108 [1632r,1664r:0)[1664r,1680r:1)  0@1632r 1@1664r
%vreg112 [1616r,1632r:0)  0@1616r
%vreg115 [1488r,1552r:0)  0@1488r
%vreg117 [1408r,1440r:0)  0@1408r
%vreg119 [1392r,1408r:0)  0@1392r
%vreg122 [1744r,1776r:0)[1776r,1792r:1)  0@1744r 1@1776r
%vreg126 [1728r,1744r:0)  0@1728r
%vreg129 [1856r,1888r:0)[1888r,1904r:1)  0@1856r 1@1888r
%vreg132 [4960r,4976r:0)  0@4960r
%vreg134 [4784r,4848r:0)  0@4784r
%vreg135 [4816r,4864r:0)  0@4816r
%vreg136 [2768r,2816B:1)[2832r,2864B:0)[2864B,2896r:2)  0@2832r 1@2768r 2@2864B-phi
RegMasks: 240r 560r 1456r 2096r 2272r 2560r 3024r 3264r 3872r 4224r 4576r 4880r
********** MACHINEINSTRS **********
# Machine code for function bzopen_or_bzdopen: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=8, align=8, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=4, align=4, at location [SP+8]
  fi#3: size=8, align=8, at location [SP+8]
  fi#4: size=4, align=4, at location [SP+8]
  fi#5: size=4, align=4, at location [SP+8]
  fi#6: size=5000, align=16, at location [SP+8]
  fi#7: size=4, align=4, at location [SP+8]
  fi#8: size=4, align=4, at location [SP+8]
  fi#9: size=10, align=1, at location [SP+8]
  fi#10: size=8, align=8, at location [SP+8]
  fi#11: size=8, align=8, at location [SP+8]
  fi#12: size=4, align=4, at location [SP+8]
  fi#13: size=4, align=4, at location [SP+8]
  fi#14: size=4, align=4, at location [SP+8]
  fi#15: size=4, align=4, at location [SP+8]
Function Live Ins: %RDI in %vreg3, %ESI in %vreg5, %RDX in %vreg7, %ECX in %vreg9

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI %ESI %RDX %ECX
16B		%vreg10<def> = COPY %ECX; GR32:%vreg10
32B		%vreg8<def> = COPY %RDX; GR64:%vreg8
48B		%vreg6<def> = COPY %ESI; GR32:%vreg6
64B		%vreg4<def> = COPY %RDI; GR64:%vreg4
144B		%vreg19<def> = MOV64ri <ga:@bzopen_or_bzdopen>; GR64:%vreg19
176B		%vreg20<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg20
192B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
208B		%RDI<def> = COPY %vreg19; GR64:%vreg19
224B		%RSI<def> = COPY %vreg20; GR64:%vreg20
240B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
256B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
320B		%vreg17<def> = LEA64r <fi#9>, 1, %noreg, 0, %noreg; GR64:%vreg17
336B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
352B		STACKMAP 0, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, %vreg6, 0, <fi#2>, 0, 0, <fi#10>, 0, %vreg8, 0, <fi#3>, 0, 0, <fi#9>, 0, 0, <fi#15>, 0, %vreg10, 0, <fi#4>, 0, %vreg4, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack2](align=4) LD8[FixedStack10] LD8[FixedStack3] LD8[FixedStack9](align=1) LD8[FixedStack15](align=4) LD8[FixedStack4](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4) GR32:%vreg6,%vreg10 GR64:%vreg8,%vreg4
368B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
384B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg4; mem:ST8[%path.addr] GR64:%vreg4
400B		MOV32mr <fi#2>, 1, %noreg, 0, %noreg, %vreg6; mem:ST4[%fd.addr] GR32:%vreg6
416B		MOV64mr <fi#3>, 1, %noreg, 0, %noreg, %vreg8; mem:ST8[%mode.addr] GR64:%vreg8
432B		MOV32mr <fi#4>, 1, %noreg, 0, %noreg, %vreg10; mem:ST4[%open_mode.addr] GR32:%vreg10
448B		MOV32mi <fi#7>, 1, %noreg, 0, %noreg, 9; mem:ST4[%blockSize100k]
464B		MOV32mi <fi#8>, 1, %noreg, 0, %noreg, 0; mem:ST4[%writing]
496B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
512B		%RDI<def> = COPY %vreg17; GR64:%vreg17
528B		%ESI<def> = MOV32r0 %EFLAGS<imp-def,dead>
544B		%EDX<def,dead> = MOV32ri 10, %RDX<imp-def>
560B		CALL64pcrel32 <MCSym=memset>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %RDX<imp-use>
576B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
592B		MOV64mi32 <fi#10>, 1, %noreg, 0, %noreg, 0; mem:ST8[%fp]
608B		MOV64mi32 <fi#11>, 1, %noreg, 0, %noreg, 0; mem:ST8[%bzfp]
624B		MOV32mi <fi#12>, 1, %noreg, 0, %noreg, 0; mem:ST4[%verbosity]
640B		MOV32mi <fi#13>, 1, %noreg, 0, %noreg, 30; mem:ST4[%workFactor]
656B		MOV32mi <fi#14>, 1, %noreg, 0, %noreg, 0; mem:ST4[%smallMode]
672B		MOV32mi <fi#15>, 1, %noreg, 0, %noreg, 0; mem:ST4[%nUnused]
688B		CMP64mi8 <fi#3>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%mode.addr]
704B		JNE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

720B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
736B		MOV64mi32 <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST8[%retval]
752B		JMP_1 <BB#41>
	    Successors according to CFG: BB#41

768B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0
784B		JMP_1 <BB#3>
	    Successors according to CFG: BB#3

800B	BB#3: derived from LLVM BB %while.cond
	    Predecessors according to CFG: BB#2 BB#15
816B		%vreg23<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%mode.addr] GR64:%vreg23
832B		CMP8mi %vreg23, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD1[%2] GR64:%vreg23
848B		JE_1 <BB#16>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#16 BB#4

864B	BB#4: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#3
880B		%vreg100<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%mode.addr] GR64:%vreg100
896B		%vreg103<def> = MOVSX32rm8 %vreg100, 1, %noreg, 0, %noreg; mem:LD1[%4] GR32:%vreg103 GR64:%vreg100
912B		%vreg101<def> = COPY %vreg103; GR32:%vreg101,%vreg103
928B		%vreg101<def,dead,tied1> = SUB32ri8 %vreg101<tied0>, 114, %EFLAGS<imp-def>; GR32:%vreg101
944B		JE_1 <BB#7>, %EFLAGS<imp-use,kill>
960B		JMP_1 <BB#5>
	    Successors according to CFG: BB#7 BB#5

976B	BB#5: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#4
992B		%vreg102<def> = COPY %vreg103; GR32:%vreg102,%vreg103
1008B		%vreg102<def,dead,tied1> = SUB32ri8 %vreg102<tied0>, 115, %EFLAGS<imp-def>; GR32:%vreg102
1024B		JE_1 <BB#9>, %EFLAGS<imp-use,kill>
1040B		JMP_1 <BB#6>
	    Successors according to CFG: BB#9 BB#6

1056B	BB#6: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#5
1088B		%vreg103<def,dead,tied1> = SUB32ri8 %vreg103<tied0>, 119, %EFLAGS<imp-def>; GR32:%vreg103
1104B		JE_1 <BB#8>, %EFLAGS<imp-use,kill>
1120B		JMP_1 <BB#10>
	    Successors according to CFG: BB#8 BB#10

1136B	BB#7: derived from LLVM BB %sw.bb
	    Predecessors according to CFG: BB#4
1152B		MOV32mi <fi#8>, 1, %noreg, 0, %noreg, 0; mem:ST4[%writing]
1168B		JMP_1 <BB#15>
	    Successors according to CFG: BB#15

1184B	BB#8: derived from LLVM BB %sw.bb.1
	    Predecessors according to CFG: BB#6
1200B		MOV32mi <fi#8>, 1, %noreg, 0, %noreg, 1; mem:ST4[%writing]
1216B		JMP_1 <BB#15>
	    Successors according to CFG: BB#15

1232B	BB#9: derived from LLVM BB %sw.bb.2
	    Predecessors according to CFG: BB#5
1248B		MOV32mi <fi#14>, 1, %noreg, 0, %noreg, 1; mem:ST4[%smallMode]
1264B		JMP_1 <BB#15>
	    Successors according to CFG: BB#15

1280B	BB#10: derived from LLVM BB %sw.default
	    Predecessors according to CFG: BB#6
1296B		%vreg104<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg104
1328B		TEST8ri %vreg104:sub_8bit, 1, %EFLAGS<imp-def>; GR32:%vreg104
1344B		JNE_1 <BB#11>, %EFLAGS<imp-use,kill>
1360B		JMP_1 <BB#12>
	    Successors according to CFG: BB#12 BB#11

1376B	BB#11: derived from LLVM BB %cond.true
	    Predecessors according to CFG: BB#10
1392B		%vreg119<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%mode.addr] GR64:%vreg119
1408B		%vreg117<def> = MOVSX32rm8 %vreg119, 1, %noreg, 0, %noreg; mem:LD1[%6] GR32:%vreg117 GR64:%vreg119
1424B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1440B		%EDI<def> = COPY %vreg117; GR32:%vreg117
1456B		CALL64pcrel32 <ga:@isdigit>, <regmask>, %RSP<imp-use>, %EDI<imp-use>, %EAX<imp-def>
1472B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1488B		%vreg115<def> = COPY %EAX<kill>; GR32:%vreg115
1504B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1520B		STACKMAP 1, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#2>, 0, 0, <fi#10>, 0, 0, <fi#3>, 0, 0, <fi#9>, 0, 0, <fi#15>, 0, 0, <fi#4>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack2](align=4) LD8[FixedStack10] LD8[FixedStack3] LD8[FixedStack9](align=1) LD8[FixedStack15](align=4) LD8[FixedStack4](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)
1536B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1552B		CMP32ri8 %vreg115, 0, %EFLAGS<imp-def>; GR32:%vreg115
1568B		JNE_1 <BB#13>, %EFLAGS<imp-use,kill>
1584B		JMP_1 <BB#14>
	    Successors according to CFG: BB#13 BB#14

1600B	BB#12: derived from LLVM BB %cond.false
	    Predecessors according to CFG: BB#10
1616B		%vreg112<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%mode.addr] GR64:%vreg112
1632B		%vreg108<def> = MOVSX32rm8 %vreg112, 1, %noreg, 0, %noreg; mem:LD1[%8] GR32:%vreg108 GR64:%vreg112
1664B		%vreg108<def,tied1> = SUB32ri8 %vreg108<tied0>, 48, %EFLAGS<imp-def,dead>; GR32:%vreg108
1680B		CMP32ri8 %vreg108, 10, %EFLAGS<imp-def>; GR32:%vreg108
1696B		JAE_1 <BB#14>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#14 BB#13

1712B	BB#13: derived from LLVM BB %if.then.8
	    Predecessors according to CFG: BB#12 BB#11
1728B		%vreg126<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%mode.addr] GR64:%vreg126
1744B		%vreg122<def> = MOVSX32rm8 %vreg126, 1, %noreg, 0, %noreg; mem:LD1[%10] GR32:%vreg122 GR64:%vreg126
1776B		%vreg122<def,tied1> = SUB32ri8 %vreg122<tied0>, 48, %EFLAGS<imp-def,dead>; GR32:%vreg122
1792B		MOV32mr <fi#7>, 1, %noreg, 0, %noreg, %vreg122; mem:ST4[%blockSize100k] GR32:%vreg122
	    Successors according to CFG: BB#14

1808B	BB#14: derived from LLVM BB %if.end.11
	    Predecessors according to CFG: BB#12 BB#11 BB#13
1824B		JMP_1 <BB#15>
	    Successors according to CFG: BB#15

1840B	BB#15: derived from LLVM BB %sw.epilog
	    Predecessors according to CFG: BB#9 BB#8 BB#7 BB#14
1856B		%vreg129<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%mode.addr] GR64:%vreg129
1888B		%vreg129<def,tied1> = ADD64ri8 %vreg129<tied0>, 1, %EFLAGS<imp-def,dead>; GR64:%vreg129
1904B		MOV64mr <fi#3>, 1, %noreg, 0, %noreg, %vreg129; mem:ST8[%mode.addr] GR64:%vreg129
1920B		JMP_1 <BB#3>
	    Successors according to CFG: BB#3

1936B	BB#16: derived from LLVM BB %while.end
	    Predecessors according to CFG: BB#3
1952B		%vreg35<def> = MOV64ri <ga:@bzlib__str_7_r_>; GR64:%vreg35
1968B		%vreg34<def> = MOV64ri <ga:@bzlib__str_6_w_>; GR64:%vreg34
1984B		%vreg36<def> = LEA64r <fi#9>, 1, %noreg, 0, %noreg; GR64:%vreg36
2000B		CMP32mi8 <fi#8>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%writing]
2032B		%vreg35<def,tied1> = CMOVNE64rr %vreg35<tied0>, %vreg34, %EFLAGS<imp-use,kill>; GR64:%vreg35,%vreg34
2048B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2064B		%RDI<def> = COPY %vreg36; GR64:%vreg36
2080B		%RSI<def> = COPY %vreg35; GR64:%vreg35
2096B		CALL64pcrel32 <ga:@strcat>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %RAX<imp-def>
2112B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2128B		%vreg31<def,dead> = COPY %RAX<kill>; GR64:%vreg31
2144B		%vreg26<def> = MOV64ri <ga:@bzlib__str_8_b_>; GR64:%vreg26
2160B		%vreg28<def> = LEA64r <fi#9>, 1, %noreg, 0, %noreg; GR64:%vreg28
2176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2192B		STACKMAP 2, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#2>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, 0, <fi#15>, 0, 0, <fi#4>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack2](align=4) LD8[FixedStack10] LD8[FixedStack9](align=1) LD8[FixedStack15](align=4) LD8[FixedStack4](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)
2208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2224B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2240B		%RDI<def> = COPY %vreg28; GR64:%vreg28
2256B		%RSI<def> = COPY %vreg26; GR64:%vreg26
2272B		CALL64pcrel32 <ga:@strcat>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %RAX<imp-def>
2288B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2304B		%vreg27<def,dead> = COPY %RAX<kill>; GR64:%vreg27
2320B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2336B		STACKMAP 3, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#2>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, 0, <fi#15>, 0, 0, <fi#4>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack2](align=4) LD8[FixedStack10] LD8[FixedStack9](align=1) LD8[FixedStack15](align=4) LD8[FixedStack4](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)
2352B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2368B		CMP32mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%open_mode.addr]
2384B		JNE_1 <BB#25>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#25 BB#17

2400B	BB#17: derived from LLVM BB %if.then.18
	    Predecessors according to CFG: BB#16
2416B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%path.addr]
2432B		JE_1 <BB#19>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#19 BB#18

2448B	BB#18: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#17
2464B		%vreg49<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%path.addr] GR64:%vreg49
2480B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2528B		%RDI<def> = COPY %vreg49; GR64:%vreg49
2544B		%ESI<def,dead> = MOV32ri64 <ga:@bzlib__str_9_>, %RSI<imp-def>
2560B		CALL64pcrel32 <ga:@strcmp>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %RSP<imp-def>, %EAX<imp-def>
2576B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2592B		%vreg44<def> = COPY %EAX<kill>; GR32:%vreg44
2624B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2640B		STACKMAP 4, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, 0, <fi#15>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack9](align=1) LD8[FixedStack15](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)
2656B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2672B		CMP32ri8 %vreg44, 0, %EFLAGS<imp-def>; GR32:%vreg44
2688B		JNE_1 <BB#23>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#23 BB#19

2704B	BB#19: derived from LLVM BB %if.then.24
	    Predecessors according to CFG: BB#17 BB#18
2720B		CMP32mi8 <fi#8>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%writing]
2736B		JE_1 <BB#21>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#21 BB#20

2752B	BB#20: derived from LLVM BB %cond.true.26
	    Predecessors according to CFG: BB#19
2768B		%vreg136<def> = MOV64rm %noreg, 1, %noreg, <ga:@stdout>, %noreg; mem:LD8[@stdout] GR64:%vreg136
2800B		JMP_1 <BB#22>
	    Successors according to CFG: BB#22

2816B	BB#21: derived from LLVM BB %cond.false.27
	    Predecessors according to CFG: BB#19
2832B		%vreg136<def> = MOV64rm %noreg, 1, %noreg, <ga:@stdin>, %noreg; mem:LD8[@stdin] GR64:%vreg136
	    Successors according to CFG: BB#22

2864B	BB#22: derived from LLVM BB %cond.end
	    Predecessors according to CFG: BB#21 BB#20
2896B		MOV64mr <fi#10>, 1, %noreg, 0, %noreg, %vreg136; mem:ST8[%fp] GR64:%vreg136
2912B		JMP_1 <BB#24>
	    Successors according to CFG: BB#24

2928B	BB#23: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#18
2944B		%vreg54<def> = LEA64r <fi#9>, 1, %noreg, 0, %noreg; GR64:%vreg54
2960B		%vreg55<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%path.addr] GR64:%vreg55
2976B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2992B		%RDI<def> = COPY %vreg55; GR64:%vreg55
3008B		%RSI<def> = COPY %vreg54; GR64:%vreg54
3024B		CALL64pcrel32 <ga:@fopen>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %RAX<imp-def>
3040B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3056B		%vreg53<def> = COPY %RAX<kill>; GR64:%vreg53
3072B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3088B		STACKMAP 5, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#15>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack15](align=4) LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)
3104B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3120B		MOV64mr <fi#10>, 1, %noreg, 0, %noreg, %vreg53; mem:ST8[%fp] GR64:%vreg53
	    Successors according to CFG: BB#24

3136B	BB#24: derived from LLVM BB %if.end.31
	    Predecessors according to CFG: BB#23 BB#22
3152B		JMP_1 <BB#26>
	    Successors according to CFG: BB#26

3168B	BB#25: derived from LLVM BB %if.else.32
	    Predecessors according to CFG: BB#16
3184B		%vreg41<def> = LEA64r <fi#9>, 1, %noreg, 0, %noreg; GR64:%vreg41
3200B		%vreg42<def> = MOV32rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD4[%fd.addr] GR32:%vreg42
3216B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3232B		%EDI<def> = COPY %vreg42; GR32:%vreg42
3248B		%RSI<def> = COPY %vreg41; GR64:%vreg41
3264B		CALL64pcrel32 <ga:@fdopen>, <regmask>, %RSP<imp-use>, %EDI<imp-use>, %RSI<imp-use>, %RAX<imp-def>
3280B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3296B		%vreg40<def> = COPY %RAX<kill>; GR64:%vreg40
3312B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3328B		STACKMAP 6, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#15>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack15](align=4) LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)
3344B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3360B		MOV64mr <fi#10>, 1, %noreg, 0, %noreg, %vreg40; mem:ST8[%fp] GR64:%vreg40
	    Successors according to CFG: BB#26

3376B	BB#26: derived from LLVM BB %if.end.35
	    Predecessors according to CFG: BB#25 BB#24
3392B		CMP64mi8 <fi#10>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%fp]
3408B		JNE_1 <BB#28>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#28 BB#27

3424B	BB#27: derived from LLVM BB %if.then.38
	    Predecessors according to CFG: BB#26
3440B		MOV64mi32 <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST8[%retval]
3456B		JMP_1 <BB#41>
	    Successors according to CFG: BB#41

3472B	BB#28: derived from LLVM BB %if.end.39
	    Predecessors according to CFG: BB#26
3488B		CMP32mi8 <fi#8>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%writing]
3504B		JE_1 <BB#34>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#34 BB#29

3520B	BB#29: derived from LLVM BB %if.then.41
	    Predecessors according to CFG: BB#28
3536B		CMP32mi8 <fi#7>, 1, %noreg, 0, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%blockSize100k]
3552B		JGE_1 <BB#31>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#31 BB#30

3568B	BB#30: derived from LLVM BB %if.then.44
	    Predecessors according to CFG: BB#29
3584B		MOV32mi <fi#7>, 1, %noreg, 0, %noreg, 1; mem:ST4[%blockSize100k]
	    Successors according to CFG: BB#31

3600B	BB#31: derived from LLVM BB %if.end.45
	    Predecessors according to CFG: BB#29 BB#30
3616B		CMP32mi8 <fi#7>, 1, %noreg, 0, %noreg, 9, %EFLAGS<imp-def>; mem:LD4[%blockSize100k]
3632B		JLE_1 <BB#33>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#33 BB#32

3648B	BB#32: derived from LLVM BB %if.then.48
	    Predecessors according to CFG: BB#31
3664B		MOV32mi <fi#7>, 1, %noreg, 0, %noreg, 9; mem:ST4[%blockSize100k]
	    Successors according to CFG: BB#33

3680B	BB#33: derived from LLVM BB %if.end.49
	    Predecessors according to CFG: BB#31 BB#32
3696B		%vreg77<def> = LEA64r <fi#5>, 1, %noreg, 0, %noreg; GR64:%vreg77
3712B		%vreg86<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%fp] GR64:%vreg86
3728B		%vreg85<def> = MOV32rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD4[%blockSize100k] GR32:%vreg85
3744B		%vreg84<def> = MOV32rm <fi#12>, 1, %noreg, 0, %noreg; mem:LD4[%verbosity] GR32:%vreg84
3760B		%vreg83<def> = MOV32rm <fi#13>, 1, %noreg, 0, %noreg; mem:LD4[%workFactor] GR32:%vreg83
3776B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3792B		%RDI<def> = COPY %vreg77; GR64:%vreg77
3808B		%RSI<def> = COPY %vreg86; GR64:%vreg86
3824B		%EDX<def> = COPY %vreg85; GR32:%vreg85
3840B		%ECX<def> = COPY %vreg84; GR32:%vreg84
3856B		%R8D<def> = COPY %vreg83; GR32:%vreg83
3872B		CALL64pcrel32 <ga:@BZ2_bzWriteOpen>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %EDX<imp-use>, %ECX<imp-use>, %R8D<imp-use,kill>, %RAX<imp-def>
3888B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3904B		%vreg82<def> = COPY %RAX<kill>; GR64:%vreg82
3920B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3936B		STACKMAP 7, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack0]
3952B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3968B		MOV64mr <fi#11>, 1, %noreg, 0, %noreg, %vreg82; mem:ST8[%bzfp] GR64:%vreg82
3984B		JMP_1 <BB#35>
	    Successors according to CFG: BB#35

4000B	BB#34: derived from LLVM BB %if.else.51
	    Predecessors according to CFG: BB#28
4016B		%vreg62<def> = LEA64r <fi#5>, 1, %noreg, 0, %noreg; GR64:%vreg62
4032B		%vreg70<def> = LEA64r <fi#6>, 1, %noreg, 0, %noreg; GR64:%vreg70
4048B		%vreg73<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%fp] GR64:%vreg73
4064B		%vreg72<def> = MOV32rm <fi#12>, 1, %noreg, 0, %noreg; mem:LD4[%verbosity] GR32:%vreg72
4080B		%vreg71<def> = MOV32rm <fi#14>, 1, %noreg, 0, %noreg; mem:LD4[%smallMode] GR32:%vreg71
4096B		%vreg69<def> = MOV32rm <fi#15>, 1, %noreg, 0, %noreg; mem:LD4[%nUnused] GR32:%vreg69
4112B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4128B		%RDI<def> = COPY %vreg62; GR64:%vreg62
4144B		%RSI<def> = COPY %vreg73; GR64:%vreg73
4160B		%EDX<def> = COPY %vreg72; GR32:%vreg72
4176B		%ECX<def> = COPY %vreg71; GR32:%vreg71
4192B		%R8<def> = COPY %vreg70; GR64:%vreg70
4208B		%R9D<def> = COPY %vreg69; GR32:%vreg69
4224B		CALL64pcrel32 <ga:@BZ2_bzReadOpen>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %EDX<imp-use>, %ECX<imp-use>, %R8<imp-use,kill>, %R9D<imp-use,kill>, %RAX<imp-def>
4240B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4256B		%vreg68<def> = COPY %RAX<kill>; GR64:%vreg68
4272B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4288B		STACKMAP 8, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack0]
4304B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4320B		MOV64mr <fi#11>, 1, %noreg, 0, %noreg, %vreg68; mem:ST8[%bzfp] GR64:%vreg68
	    Successors according to CFG: BB#35

4336B	BB#35: derived from LLVM BB %if.end.54
	    Predecessors according to CFG: BB#34 BB#33
4352B		CMP64mi8 <fi#11>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzfp]
4368B		JNE_1 <BB#40>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#40 BB#36

4384B	BB#36: derived from LLVM BB %if.then.57
	    Predecessors according to CFG: BB#35
4400B		%vreg92<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%fp] GR64:%vreg92
4416B		CMP64rm %vreg92, %noreg, 1, %noreg, <ga:@stdin>, %noreg, %EFLAGS<imp-def>; mem:LD8[@stdin] GR64:%vreg92
4432B		JE_1 <BB#39>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#39 BB#37

4448B	BB#37: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#36
4464B		%vreg95<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%fp] GR64:%vreg95
4480B		CMP64rm %vreg95, %noreg, 1, %noreg, <ga:@stdout>, %noreg, %EFLAGS<imp-def>; mem:LD8[@stdout] GR64:%vreg95
4496B		JE_1 <BB#39>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#39 BB#38

4512B	BB#38: derived from LLVM BB %if.then.62
	    Predecessors according to CFG: BB#37
4528B		%vreg98<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%fp] GR64:%vreg98
4544B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4560B		%RDI<def> = COPY %vreg98; GR64:%vreg98
4576B		CALL64pcrel32 <ga:@fclose>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
4592B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4608B		%vreg97<def,dead> = COPY %EAX<kill>; GR32:%vreg97
4624B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4640B		STACKMAP 9, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0]
4656B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#39

4672B	BB#39: derived from LLVM BB %if.end.64
	    Predecessors according to CFG: BB#36 BB#37 BB#38
4688B		MOV64mi32 <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST8[%retval]
4704B		JMP_1 <BB#41>
	    Successors according to CFG: BB#41

4720B	BB#40: derived from LLVM BB %if.end.65
	    Predecessors according to CFG: BB#35
4736B		%vreg89<def> = MOV64rm <fi#11>, 1, %noreg, 0, %noreg; mem:LD8[%bzfp] GR64:%vreg89
4752B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg89; mem:ST8[%retval] GR64:%vreg89
	    Successors according to CFG: BB#41

4768B	BB#41: derived from LLVM BB %return
	    Predecessors according to CFG: BB#40 BB#39 BB#27 BB#1
4784B		%vreg134<def> = MOV64ri <ga:@bzopen_or_bzdopen>; GR64:%vreg134
4816B		%vreg135<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg135
4832B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4848B		%RDI<def> = COPY %vreg134; GR64:%vreg134
4864B		%RSI<def> = COPY %vreg135; GR64:%vreg135
4880B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
4896B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4912B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4928B		STACKMAP 10, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0]
4944B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4960B		%vreg132<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%retval] GR64:%vreg132
4976B		%RAX<def> = COPY %vreg132; GR64:%vreg132
4992B		RETQ %RAX<imp-use,kill>

# End machine code for function bzopen_or_bzdopen.

handleMove 512B -> 552B: %RDI<def> = COPY %vreg17; GR64:%vreg17
     DIL:	[0B,64r:0)[208r,240r:11)[512r,560r:12)[1440r,1456r:1)[2064r,2096r:9)[2240r,2272r:10)[2528r,2560r:8)[2992r,3024r:7)[3232r,3264r:2)[3792r,3872r:5)[4128r,4224r:6)[4560r,4576r:4)[4848r,4880r:3)  0@0B-phi 1@1440r 2@3232r 3@4848r 4@4560r 5@3792r 6@4128r 7@2992r 8@2528r 9@2064r 10@2240r 11@208r 12@512r
        -->	[0B,64r:0)[208r,240r:11)[552r,560r:12)[1440r,1456r:1)[2064r,2096r:9)[2240r,2272r:10)[2528r,2560r:8)[2992r,3024r:7)[3232r,3264r:2)[3792r,3872r:5)[4128r,4224r:6)[4560r,4576r:4)[4848r,4880r:3)  0@0B-phi 1@1440r 2@3232r 3@4848r 4@4560r 5@3792r 6@4128r 7@2992r 8@2528r 9@2064r 10@2240r 11@208r 12@552r
     %vreg17:	[320r,512r:0)  0@320r
        -->	[320r,552r:0)  0@320r
handleMove 2528B -> 2552B: %RDI<def> = COPY %vreg49; GR64:%vreg49
     DIL:	[0B,64r:0)[208r,240r:11)[552r,560r:12)[1440r,1456r:1)[2064r,2096r:9)[2240r,2272r:10)[2528r,2560r:8)[2992r,3024r:7)[3232r,3264r:2)[3792r,3872r:5)[4128r,4224r:6)[4560r,4576r:4)[4848r,4880r:3)  0@0B-phi 1@1440r 2@3232r 3@4848r 4@4560r 5@3792r 6@4128r 7@2992r 8@2528r 9@2064r 10@2240r 11@208r 12@552r
        -->	[0B,64r:0)[208r,240r:11)[552r,560r:12)[1440r,1456r:1)[2064r,2096r:9)[2240r,2272r:10)[2552r,2560r:8)[2992r,3024r:7)[3232r,3264r:2)[3792r,3872r:5)[4128r,4224r:6)[4560r,4576r:4)[4848r,4880r:3)  0@0B-phi 1@1440r 2@3232r 3@4848r 4@4560r 5@3792r 6@4128r 7@2992r 8@2552r 9@2064r 10@2240r 11@208r 12@552r
     %vreg49:	[2464r,2528r:0)  0@2464r
        -->	[2464r,2552r:0)  0@2464r
********** GREEDY REGISTER ALLOCATION **********
********** Function: bzopen_or_bzdopen
********** INTERVALS **********
CH [0B,16r:0)[3840r,3872r:1)[4176r,4224r:2)  0@0B-phi 1@3840r 2@4176r
CL [0B,16r:0)[3840r,3872r:1)[4176r,4224r:2)  0@0B-phi 1@3840r 2@4176r
DH [0B,32r:0)[544r,560r:3)[3824r,3872r:1)[4160r,4224r:2)  0@0B-phi 1@3824r 2@4160r 3@544r
DIL [0B,64r:0)[208r,240r:11)[552r,560r:12)[1440r,1456r:1)[2064r,2096r:9)[2240r,2272r:10)[2552r,2560r:8)[2992r,3024r:7)[3232r,3264r:2)[3792r,3872r:5)[4128r,4224r:6)[4560r,4576r:4)[4848r,4880r:3)  0@0B-phi 1@1440r 2@3232r 3@4848r 4@4560r 5@3792r 6@4128r 7@2992r 8@2552r 9@2064r 10@2240r 11@208r 12@552r
DL [0B,32r:0)[544r,560r:3)[3824r,3872r:1)[4160r,4224r:2)  0@0B-phi 1@3824r 2@4160r 3@544r
SIL [0B,48r:0)[224r,240r:10)[528r,560r:1)[2080r,2096r:8)[2256r,2272r:9)[2544r,2560r:6)[3008r,3024r:5)[3248r,3264r:7)[3808r,3872r:3)[4144r,4224r:4)[4864r,4880r:2)  0@0B-phi 1@528r 2@4864r 3@3808r 4@4144r 5@3008r 6@2544r 7@3248r 8@2080r 9@2256r 10@224r
%vreg4 [64r,384r:0)  0@64r
%vreg6 [48r,400r:0)  0@48r
%vreg8 [32r,416r:0)  0@32r
%vreg10 [16r,432r:0)  0@16r
%vreg17 [320r,552r:0)  0@320r
%vreg19 [144r,208r:0)  0@144r
%vreg20 [176r,224r:0)  0@176r
%vreg23 [816r,832r:0)  0@816r
%vreg26 [2144r,2256r:0)  0@2144r
%vreg27 [2304r,2304d:0)  0@2304r
%vreg28 [2160r,2240r:0)  0@2160r
%vreg31 [2128r,2128d:0)  0@2128r
%vreg34 [1968r,2032r:0)  0@1968r
%vreg35 [1952r,2032r:0)[2032r,2080r:1)  0@1952r 1@2032r
%vreg36 [1984r,2064r:0)  0@1984r
%vreg40 [3296r,3360r:0)  0@3296r
%vreg41 [3184r,3248r:0)  0@3184r
%vreg42 [3200r,3232r:0)  0@3200r
%vreg44 [2592r,2672r:0)  0@2592r
%vreg49 [2464r,2552r:0)  0@2464r
%vreg53 [3056r,3120r:0)  0@3056r
%vreg54 [2944r,3008r:0)  0@2944r
%vreg55 [2960r,2992r:0)  0@2960r
%vreg62 [4016r,4128r:0)  0@4016r
%vreg68 [4256r,4320r:0)  0@4256r
%vreg69 [4096r,4208r:0)  0@4096r
%vreg70 [4032r,4192r:0)  0@4032r
%vreg71 [4080r,4176r:0)  0@4080r
%vreg72 [4064r,4160r:0)  0@4064r
%vreg73 [4048r,4144r:0)  0@4048r
%vreg77 [3696r,3792r:0)  0@3696r
%vreg82 [3904r,3968r:0)  0@3904r
%vreg83 [3760r,3856r:0)  0@3760r
%vreg84 [3744r,3840r:0)  0@3744r
%vreg85 [3728r,3824r:0)  0@3728r
%vreg86 [3712r,3808r:0)  0@3712r
%vreg89 [4736r,4752r:0)  0@4736r
%vreg92 [4400r,4416r:0)  0@4400r
%vreg95 [4464r,4480r:0)  0@4464r
%vreg97 [4608r,4608d:0)  0@4608r
%vreg98 [4528r,4560r:0)  0@4528r
%vreg100 [880r,896r:0)  0@880r
%vreg101 [912r,928r:0)[928r,928d:1)  0@912r 1@928r
%vreg102 [992r,1008r:0)[1008r,1008d:1)  0@992r 1@1008r
%vreg103 [896r,1088r:0)[1088r,1088d:1)  0@896r 1@1088r
%vreg104 [1296r,1328r:0)  0@1296r
%vreg108 [1632r,1664r:0)[1664r,1680r:1)  0@1632r 1@1664r
%vreg112 [1616r,1632r:0)  0@1616r
%vreg115 [1488r,1552r:0)  0@1488r
%vreg117 [1408r,1440r:0)  0@1408r
%vreg119 [1392r,1408r:0)  0@1392r
%vreg122 [1744r,1776r:0)[1776r,1792r:1)  0@1744r 1@1776r
%vreg126 [1728r,1744r:0)  0@1728r
%vreg129 [1856r,1888r:0)[1888r,1904r:1)  0@1856r 1@1888r
%vreg132 [4960r,4976r:0)  0@4960r
%vreg134 [4784r,4848r:0)  0@4784r
%vreg135 [4816r,4864r:0)  0@4816r
%vreg136 [2768r,2816B:1)[2832r,2864B:0)[2864B,2896r:2)  0@2832r 1@2768r 2@2864B-phi
RegMasks: 240r 560r 1456r 2096r 2272r 2560r 3024r 3264r 3872r 4224r 4576r 4880r
********** MACHINEINSTRS **********
# Machine code for function bzopen_or_bzdopen: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=8, align=8, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=4, align=4, at location [SP+8]
  fi#3: size=8, align=8, at location [SP+8]
  fi#4: size=4, align=4, at location [SP+8]
  fi#5: size=4, align=4, at location [SP+8]
  fi#6: size=5000, align=16, at location [SP+8]
  fi#7: size=4, align=4, at location [SP+8]
  fi#8: size=4, align=4, at location [SP+8]
  fi#9: size=10, align=1, at location [SP+8]
  fi#10: size=8, align=8, at location [SP+8]
  fi#11: size=8, align=8, at location [SP+8]
  fi#12: size=4, align=4, at location [SP+8]
  fi#13: size=4, align=4, at location [SP+8]
  fi#14: size=4, align=4, at location [SP+8]
  fi#15: size=4, align=4, at location [SP+8]
Function Live Ins: %RDI in %vreg3, %ESI in %vreg5, %RDX in %vreg7, %ECX in %vreg9

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI %ESI %RDX %ECX
16B		%vreg10<def> = COPY %ECX; GR32:%vreg10
32B		%vreg8<def> = COPY %RDX; GR64:%vreg8
48B		%vreg6<def> = COPY %ESI; GR32:%vreg6
64B		%vreg4<def> = COPY %RDI; GR64:%vreg4
144B		%vreg19<def> = MOV64ri <ga:@bzopen_or_bzdopen>; GR64:%vreg19
176B		%vreg20<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg20
192B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
208B		%RDI<def> = COPY %vreg19; GR64:%vreg19
224B		%RSI<def> = COPY %vreg20; GR64:%vreg20
240B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
256B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
320B		%vreg17<def> = LEA64r <fi#9>, 1, %noreg, 0, %noreg; GR64:%vreg17
336B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
352B		STACKMAP 0, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, %vreg6, 0, <fi#2>, 0, 0, <fi#10>, 0, %vreg8, 0, <fi#3>, 0, 0, <fi#9>, 0, 0, <fi#15>, 0, %vreg10, 0, <fi#4>, 0, %vreg4, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack2](align=4) LD8[FixedStack10] LD8[FixedStack3] LD8[FixedStack9](align=1) LD8[FixedStack15](align=4) LD8[FixedStack4](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4) GR32:%vreg6,%vreg10 GR64:%vreg8,%vreg4
368B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
384B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg4; mem:ST8[%path.addr] GR64:%vreg4
400B		MOV32mr <fi#2>, 1, %noreg, 0, %noreg, %vreg6; mem:ST4[%fd.addr] GR32:%vreg6
416B		MOV64mr <fi#3>, 1, %noreg, 0, %noreg, %vreg8; mem:ST8[%mode.addr] GR64:%vreg8
432B		MOV32mr <fi#4>, 1, %noreg, 0, %noreg, %vreg10; mem:ST4[%open_mode.addr] GR32:%vreg10
448B		MOV32mi <fi#7>, 1, %noreg, 0, %noreg, 9; mem:ST4[%blockSize100k]
464B		MOV32mi <fi#8>, 1, %noreg, 0, %noreg, 0; mem:ST4[%writing]
496B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
528B		%ESI<def> = MOV32r0 %EFLAGS<imp-def,dead>
544B		%EDX<def,dead> = MOV32ri 10, %RDX<imp-def>
552B		%RDI<def> = COPY %vreg17; GR64:%vreg17
560B		CALL64pcrel32 <MCSym=memset>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %RDX<imp-use>
576B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
592B		MOV64mi32 <fi#10>, 1, %noreg, 0, %noreg, 0; mem:ST8[%fp]
608B		MOV64mi32 <fi#11>, 1, %noreg, 0, %noreg, 0; mem:ST8[%bzfp]
624B		MOV32mi <fi#12>, 1, %noreg, 0, %noreg, 0; mem:ST4[%verbosity]
640B		MOV32mi <fi#13>, 1, %noreg, 0, %noreg, 30; mem:ST4[%workFactor]
656B		MOV32mi <fi#14>, 1, %noreg, 0, %noreg, 0; mem:ST4[%smallMode]
672B		MOV32mi <fi#15>, 1, %noreg, 0, %noreg, 0; mem:ST4[%nUnused]
688B		CMP64mi8 <fi#3>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%mode.addr]
704B		JNE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

720B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
736B		MOV64mi32 <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST8[%retval]
752B		JMP_1 <BB#41>
	    Successors according to CFG: BB#41

768B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0
784B		JMP_1 <BB#3>
	    Successors according to CFG: BB#3

800B	BB#3: derived from LLVM BB %while.cond
	    Predecessors according to CFG: BB#2 BB#15
816B		%vreg23<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%mode.addr] GR64:%vreg23
832B		CMP8mi %vreg23, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD1[%2] GR64:%vreg23
848B		JE_1 <BB#16>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#16 BB#4

864B	BB#4: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#3
880B		%vreg100<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%mode.addr] GR64:%vreg100
896B		%vreg103<def> = MOVSX32rm8 %vreg100, 1, %noreg, 0, %noreg; mem:LD1[%4] GR32:%vreg103 GR64:%vreg100
912B		%vreg101<def> = COPY %vreg103; GR32:%vreg101,%vreg103
928B		%vreg101<def,dead,tied1> = SUB32ri8 %vreg101<tied0>, 114, %EFLAGS<imp-def>; GR32:%vreg101
944B		JE_1 <BB#7>, %EFLAGS<imp-use,kill>
960B		JMP_1 <BB#5>
	    Successors according to CFG: BB#7 BB#5

976B	BB#5: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#4
992B		%vreg102<def> = COPY %vreg103; GR32:%vreg102,%vreg103
1008B		%vreg102<def,dead,tied1> = SUB32ri8 %vreg102<tied0>, 115, %EFLAGS<imp-def>; GR32:%vreg102
1024B		JE_1 <BB#9>, %EFLAGS<imp-use,kill>
1040B		JMP_1 <BB#6>
	    Successors according to CFG: BB#9 BB#6

1056B	BB#6: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#5
1088B		%vreg103<def,dead,tied1> = SUB32ri8 %vreg103<tied0>, 119, %EFLAGS<imp-def>; GR32:%vreg103
1104B		JE_1 <BB#8>, %EFLAGS<imp-use,kill>
1120B		JMP_1 <BB#10>
	    Successors according to CFG: BB#8 BB#10

1136B	BB#7: derived from LLVM BB %sw.bb
	    Predecessors according to CFG: BB#4
1152B		MOV32mi <fi#8>, 1, %noreg, 0, %noreg, 0; mem:ST4[%writing]
1168B		JMP_1 <BB#15>
	    Successors according to CFG: BB#15

1184B	BB#8: derived from LLVM BB %sw.bb.1
	    Predecessors according to CFG: BB#6
1200B		MOV32mi <fi#8>, 1, %noreg, 0, %noreg, 1; mem:ST4[%writing]
1216B		JMP_1 <BB#15>
	    Successors according to CFG: BB#15

1232B	BB#9: derived from LLVM BB %sw.bb.2
	    Predecessors according to CFG: BB#5
1248B		MOV32mi <fi#14>, 1, %noreg, 0, %noreg, 1; mem:ST4[%smallMode]
1264B		JMP_1 <BB#15>
	    Successors according to CFG: BB#15

1280B	BB#10: derived from LLVM BB %sw.default
	    Predecessors according to CFG: BB#6
1296B		%vreg104<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg104
1328B		TEST8ri %vreg104:sub_8bit, 1, %EFLAGS<imp-def>; GR32:%vreg104
1344B		JNE_1 <BB#11>, %EFLAGS<imp-use,kill>
1360B		JMP_1 <BB#12>
	    Successors according to CFG: BB#12 BB#11

1376B	BB#11: derived from LLVM BB %cond.true
	    Predecessors according to CFG: BB#10
1392B		%vreg119<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%mode.addr] GR64:%vreg119
1408B		%vreg117<def> = MOVSX32rm8 %vreg119, 1, %noreg, 0, %noreg; mem:LD1[%6] GR32:%vreg117 GR64:%vreg119
1424B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1440B		%EDI<def> = COPY %vreg117; GR32:%vreg117
1456B		CALL64pcrel32 <ga:@isdigit>, <regmask>, %RSP<imp-use>, %EDI<imp-use>, %EAX<imp-def>
1472B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1488B		%vreg115<def> = COPY %EAX<kill>; GR32:%vreg115
1504B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1520B		STACKMAP 1, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#2>, 0, 0, <fi#10>, 0, 0, <fi#3>, 0, 0, <fi#9>, 0, 0, <fi#15>, 0, 0, <fi#4>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack2](align=4) LD8[FixedStack10] LD8[FixedStack3] LD8[FixedStack9](align=1) LD8[FixedStack15](align=4) LD8[FixedStack4](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)
1536B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1552B		CMP32ri8 %vreg115, 0, %EFLAGS<imp-def>; GR32:%vreg115
1568B		JNE_1 <BB#13>, %EFLAGS<imp-use,kill>
1584B		JMP_1 <BB#14>
	    Successors according to CFG: BB#13 BB#14

1600B	BB#12: derived from LLVM BB %cond.false
	    Predecessors according to CFG: BB#10
1616B		%vreg112<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%mode.addr] GR64:%vreg112
1632B		%vreg108<def> = MOVSX32rm8 %vreg112, 1, %noreg, 0, %noreg; mem:LD1[%8] GR32:%vreg108 GR64:%vreg112
1664B		%vreg108<def,tied1> = SUB32ri8 %vreg108<tied0>, 48, %EFLAGS<imp-def,dead>; GR32:%vreg108
1680B		CMP32ri8 %vreg108, 10, %EFLAGS<imp-def>; GR32:%vreg108
1696B		JAE_1 <BB#14>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#14 BB#13

1712B	BB#13: derived from LLVM BB %if.then.8
	    Predecessors according to CFG: BB#12 BB#11
1728B		%vreg126<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%mode.addr] GR64:%vreg126
1744B		%vreg122<def> = MOVSX32rm8 %vreg126, 1, %noreg, 0, %noreg; mem:LD1[%10] GR32:%vreg122 GR64:%vreg126
1776B		%vreg122<def,tied1> = SUB32ri8 %vreg122<tied0>, 48, %EFLAGS<imp-def,dead>; GR32:%vreg122
1792B		MOV32mr <fi#7>, 1, %noreg, 0, %noreg, %vreg122; mem:ST4[%blockSize100k] GR32:%vreg122
	    Successors according to CFG: BB#14

1808B	BB#14: derived from LLVM BB %if.end.11
	    Predecessors according to CFG: BB#12 BB#11 BB#13
1824B		JMP_1 <BB#15>
	    Successors according to CFG: BB#15

1840B	BB#15: derived from LLVM BB %sw.epilog
	    Predecessors according to CFG: BB#9 BB#8 BB#7 BB#14
1856B		%vreg129<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%mode.addr] GR64:%vreg129
1888B		%vreg129<def,tied1> = ADD64ri8 %vreg129<tied0>, 1, %EFLAGS<imp-def,dead>; GR64:%vreg129
1904B		MOV64mr <fi#3>, 1, %noreg, 0, %noreg, %vreg129; mem:ST8[%mode.addr] GR64:%vreg129
1920B		JMP_1 <BB#3>
	    Successors according to CFG: BB#3

1936B	BB#16: derived from LLVM BB %while.end
	    Predecessors according to CFG: BB#3
1952B		%vreg35<def> = MOV64ri <ga:@bzlib__str_7_r_>; GR64:%vreg35
1968B		%vreg34<def> = MOV64ri <ga:@bzlib__str_6_w_>; GR64:%vreg34
1984B		%vreg36<def> = LEA64r <fi#9>, 1, %noreg, 0, %noreg; GR64:%vreg36
2000B		CMP32mi8 <fi#8>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%writing]
2032B		%vreg35<def,tied1> = CMOVNE64rr %vreg35<tied0>, %vreg34, %EFLAGS<imp-use,kill>; GR64:%vreg35,%vreg34
2048B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2064B		%RDI<def> = COPY %vreg36; GR64:%vreg36
2080B		%RSI<def> = COPY %vreg35; GR64:%vreg35
2096B		CALL64pcrel32 <ga:@strcat>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %RAX<imp-def>
2112B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2128B		%vreg31<def,dead> = COPY %RAX<kill>; GR64:%vreg31
2144B		%vreg26<def> = MOV64ri <ga:@bzlib__str_8_b_>; GR64:%vreg26
2160B		%vreg28<def> = LEA64r <fi#9>, 1, %noreg, 0, %noreg; GR64:%vreg28
2176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2192B		STACKMAP 2, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#2>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, 0, <fi#15>, 0, 0, <fi#4>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack2](align=4) LD8[FixedStack10] LD8[FixedStack9](align=1) LD8[FixedStack15](align=4) LD8[FixedStack4](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)
2208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2224B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2240B		%RDI<def> = COPY %vreg28; GR64:%vreg28
2256B		%RSI<def> = COPY %vreg26; GR64:%vreg26
2272B		CALL64pcrel32 <ga:@strcat>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %RAX<imp-def>
2288B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2304B		%vreg27<def,dead> = COPY %RAX<kill>; GR64:%vreg27
2320B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2336B		STACKMAP 3, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#2>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, 0, <fi#15>, 0, 0, <fi#4>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack2](align=4) LD8[FixedStack10] LD8[FixedStack9](align=1) LD8[FixedStack15](align=4) LD8[FixedStack4](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)
2352B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2368B		CMP32mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%open_mode.addr]
2384B		JNE_1 <BB#25>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#25 BB#17

2400B	BB#17: derived from LLVM BB %if.then.18
	    Predecessors according to CFG: BB#16
2416B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%path.addr]
2432B		JE_1 <BB#19>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#19 BB#18

2448B	BB#18: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#17
2464B		%vreg49<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%path.addr] GR64:%vreg49
2480B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2544B		%ESI<def,dead> = MOV32ri64 <ga:@bzlib__str_9_>, %RSI<imp-def>
2552B		%RDI<def> = COPY %vreg49; GR64:%vreg49
2560B		CALL64pcrel32 <ga:@strcmp>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %RSP<imp-def>, %EAX<imp-def>
2576B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2592B		%vreg44<def> = COPY %EAX<kill>; GR32:%vreg44
2624B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2640B		STACKMAP 4, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, 0, <fi#15>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack9](align=1) LD8[FixedStack15](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)
2656B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2672B		CMP32ri8 %vreg44, 0, %EFLAGS<imp-def>; GR32:%vreg44
2688B		JNE_1 <BB#23>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#23 BB#19

2704B	BB#19: derived from LLVM BB %if.then.24
	    Predecessors according to CFG: BB#17 BB#18
2720B		CMP32mi8 <fi#8>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%writing]
2736B		JE_1 <BB#21>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#21 BB#20

2752B	BB#20: derived from LLVM BB %cond.true.26
	    Predecessors according to CFG: BB#19
2768B		%vreg136<def> = MOV64rm %noreg, 1, %noreg, <ga:@stdout>, %noreg; mem:LD8[@stdout] GR64:%vreg136
2800B		JMP_1 <BB#22>
	    Successors according to CFG: BB#22

2816B	BB#21: derived from LLVM BB %cond.false.27
	    Predecessors according to CFG: BB#19
2832B		%vreg136<def> = MOV64rm %noreg, 1, %noreg, <ga:@stdin>, %noreg; mem:LD8[@stdin] GR64:%vreg136
	    Successors according to CFG: BB#22

2864B	BB#22: derived from LLVM BB %cond.end
	    Predecessors according to CFG: BB#21 BB#20
2896B		MOV64mr <fi#10>, 1, %noreg, 0, %noreg, %vreg136; mem:ST8[%fp] GR64:%vreg136
2912B		JMP_1 <BB#24>
	    Successors according to CFG: BB#24

2928B	BB#23: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#18
2944B		%vreg54<def> = LEA64r <fi#9>, 1, %noreg, 0, %noreg; GR64:%vreg54
2960B		%vreg55<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%path.addr] GR64:%vreg55
2976B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2992B		%RDI<def> = COPY %vreg55; GR64:%vreg55
3008B		%RSI<def> = COPY %vreg54; GR64:%vreg54
3024B		CALL64pcrel32 <ga:@fopen>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %RAX<imp-def>
3040B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3056B		%vreg53<def> = COPY %RAX<kill>; GR64:%vreg53
3072B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3088B		STACKMAP 5, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#15>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack15](align=4) LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)
3104B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3120B		MOV64mr <fi#10>, 1, %noreg, 0, %noreg, %vreg53; mem:ST8[%fp] GR64:%vreg53
	    Successors according to CFG: BB#24

3136B	BB#24: derived from LLVM BB %if.end.31
	    Predecessors according to CFG: BB#23 BB#22
3152B		JMP_1 <BB#26>
	    Successors according to CFG: BB#26

3168B	BB#25: derived from LLVM BB %if.else.32
	    Predecessors according to CFG: BB#16
3184B		%vreg41<def> = LEA64r <fi#9>, 1, %noreg, 0, %noreg; GR64:%vreg41
3200B		%vreg42<def> = MOV32rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD4[%fd.addr] GR32:%vreg42
3216B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3232B		%EDI<def> = COPY %vreg42; GR32:%vreg42
3248B		%RSI<def> = COPY %vreg41; GR64:%vreg41
3264B		CALL64pcrel32 <ga:@fdopen>, <regmask>, %RSP<imp-use>, %EDI<imp-use>, %RSI<imp-use>, %RAX<imp-def>
3280B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3296B		%vreg40<def> = COPY %RAX<kill>; GR64:%vreg40
3312B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3328B		STACKMAP 6, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#15>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack15](align=4) LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)
3344B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3360B		MOV64mr <fi#10>, 1, %noreg, 0, %noreg, %vreg40; mem:ST8[%fp] GR64:%vreg40
	    Successors according to CFG: BB#26

3376B	BB#26: derived from LLVM BB %if.end.35
	    Predecessors according to CFG: BB#25 BB#24
3392B		CMP64mi8 <fi#10>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%fp]
3408B		JNE_1 <BB#28>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#28 BB#27

3424B	BB#27: derived from LLVM BB %if.then.38
	    Predecessors according to CFG: BB#26
3440B		MOV64mi32 <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST8[%retval]
3456B		JMP_1 <BB#41>
	    Successors according to CFG: BB#41

3472B	BB#28: derived from LLVM BB %if.end.39
	    Predecessors according to CFG: BB#26
3488B		CMP32mi8 <fi#8>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%writing]
3504B		JE_1 <BB#34>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#34 BB#29

3520B	BB#29: derived from LLVM BB %if.then.41
	    Predecessors according to CFG: BB#28
3536B		CMP32mi8 <fi#7>, 1, %noreg, 0, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%blockSize100k]
3552B		JGE_1 <BB#31>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#31 BB#30

3568B	BB#30: derived from LLVM BB %if.then.44
	    Predecessors according to CFG: BB#29
3584B		MOV32mi <fi#7>, 1, %noreg, 0, %noreg, 1; mem:ST4[%blockSize100k]
	    Successors according to CFG: BB#31

3600B	BB#31: derived from LLVM BB %if.end.45
	    Predecessors according to CFG: BB#29 BB#30
3616B		CMP32mi8 <fi#7>, 1, %noreg, 0, %noreg, 9, %EFLAGS<imp-def>; mem:LD4[%blockSize100k]
3632B		JLE_1 <BB#33>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#33 BB#32

3648B	BB#32: derived from LLVM BB %if.then.48
	    Predecessors according to CFG: BB#31
3664B		MOV32mi <fi#7>, 1, %noreg, 0, %noreg, 9; mem:ST4[%blockSize100k]
	    Successors according to CFG: BB#33

3680B	BB#33: derived from LLVM BB %if.end.49
	    Predecessors according to CFG: BB#31 BB#32
3696B		%vreg77<def> = LEA64r <fi#5>, 1, %noreg, 0, %noreg; GR64:%vreg77
3712B		%vreg86<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%fp] GR64:%vreg86
3728B		%vreg85<def> = MOV32rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD4[%blockSize100k] GR32:%vreg85
3744B		%vreg84<def> = MOV32rm <fi#12>, 1, %noreg, 0, %noreg; mem:LD4[%verbosity] GR32:%vreg84
3760B		%vreg83<def> = MOV32rm <fi#13>, 1, %noreg, 0, %noreg; mem:LD4[%workFactor] GR32:%vreg83
3776B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3792B		%RDI<def> = COPY %vreg77; GR64:%vreg77
3808B		%RSI<def> = COPY %vreg86; GR64:%vreg86
3824B		%EDX<def> = COPY %vreg85; GR32:%vreg85
3840B		%ECX<def> = COPY %vreg84; GR32:%vreg84
3856B		%R8D<def> = COPY %vreg83; GR32:%vreg83
3872B		CALL64pcrel32 <ga:@BZ2_bzWriteOpen>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %EDX<imp-use>, %ECX<imp-use>, %R8D<imp-use,kill>, %RAX<imp-def>
3888B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3904B		%vreg82<def> = COPY %RAX<kill>; GR64:%vreg82
3920B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3936B		STACKMAP 7, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack0]
3952B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3968B		MOV64mr <fi#11>, 1, %noreg, 0, %noreg, %vreg82; mem:ST8[%bzfp] GR64:%vreg82
3984B		JMP_1 <BB#35>
	    Successors according to CFG: BB#35

4000B	BB#34: derived from LLVM BB %if.else.51
	    Predecessors according to CFG: BB#28
4016B		%vreg62<def> = LEA64r <fi#5>, 1, %noreg, 0, %noreg; GR64:%vreg62
4032B		%vreg70<def> = LEA64r <fi#6>, 1, %noreg, 0, %noreg; GR64:%vreg70
4048B		%vreg73<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%fp] GR64:%vreg73
4064B		%vreg72<def> = MOV32rm <fi#12>, 1, %noreg, 0, %noreg; mem:LD4[%verbosity] GR32:%vreg72
4080B		%vreg71<def> = MOV32rm <fi#14>, 1, %noreg, 0, %noreg; mem:LD4[%smallMode] GR32:%vreg71
4096B		%vreg69<def> = MOV32rm <fi#15>, 1, %noreg, 0, %noreg; mem:LD4[%nUnused] GR32:%vreg69
4112B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4128B		%RDI<def> = COPY %vreg62; GR64:%vreg62
4144B		%RSI<def> = COPY %vreg73; GR64:%vreg73
4160B		%EDX<def> = COPY %vreg72; GR32:%vreg72
4176B		%ECX<def> = COPY %vreg71; GR32:%vreg71
4192B		%R8<def> = COPY %vreg70; GR64:%vreg70
4208B		%R9D<def> = COPY %vreg69; GR32:%vreg69
4224B		CALL64pcrel32 <ga:@BZ2_bzReadOpen>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %EDX<imp-use>, %ECX<imp-use>, %R8<imp-use,kill>, %R9D<imp-use,kill>, %RAX<imp-def>
4240B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4256B		%vreg68<def> = COPY %RAX<kill>; GR64:%vreg68
4272B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4288B		STACKMAP 8, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack0]
4304B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4320B		MOV64mr <fi#11>, 1, %noreg, 0, %noreg, %vreg68; mem:ST8[%bzfp] GR64:%vreg68
	    Successors according to CFG: BB#35

4336B	BB#35: derived from LLVM BB %if.end.54
	    Predecessors according to CFG: BB#34 BB#33
4352B		CMP64mi8 <fi#11>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzfp]
4368B		JNE_1 <BB#40>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#40 BB#36

4384B	BB#36: derived from LLVM BB %if.then.57
	    Predecessors according to CFG: BB#35
4400B		%vreg92<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%fp] GR64:%vreg92
4416B		CMP64rm %vreg92, %noreg, 1, %noreg, <ga:@stdin>, %noreg, %EFLAGS<imp-def>; mem:LD8[@stdin] GR64:%vreg92
4432B		JE_1 <BB#39>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#39 BB#37

4448B	BB#37: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#36
4464B		%vreg95<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%fp] GR64:%vreg95
4480B		CMP64rm %vreg95, %noreg, 1, %noreg, <ga:@stdout>, %noreg, %EFLAGS<imp-def>; mem:LD8[@stdout] GR64:%vreg95
4496B		JE_1 <BB#39>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#39 BB#38

4512B	BB#38: derived from LLVM BB %if.then.62
	    Predecessors according to CFG: BB#37
4528B		%vreg98<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%fp] GR64:%vreg98
4544B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4560B		%RDI<def> = COPY %vreg98; GR64:%vreg98
4576B		CALL64pcrel32 <ga:@fclose>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
4592B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4608B		%vreg97<def,dead> = COPY %EAX<kill>; GR32:%vreg97
4624B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4640B		STACKMAP 9, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0]
4656B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#39

4672B	BB#39: derived from LLVM BB %if.end.64
	    Predecessors according to CFG: BB#36 BB#37 BB#38
4688B		MOV64mi32 <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST8[%retval]
4704B		JMP_1 <BB#41>
	    Successors according to CFG: BB#41

4720B	BB#40: derived from LLVM BB %if.end.65
	    Predecessors according to CFG: BB#35
4736B		%vreg89<def> = MOV64rm <fi#11>, 1, %noreg, 0, %noreg; mem:LD8[%bzfp] GR64:%vreg89
4752B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg89; mem:ST8[%retval] GR64:%vreg89
	    Successors according to CFG: BB#41

4768B	BB#41: derived from LLVM BB %return
	    Predecessors according to CFG: BB#40 BB#39 BB#27 BB#1
4784B		%vreg134<def> = MOV64ri <ga:@bzopen_or_bzdopen>; GR64:%vreg134
4816B		%vreg135<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg135
4832B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4848B		%RDI<def> = COPY %vreg134; GR64:%vreg134
4864B		%RSI<def> = COPY %vreg135; GR64:%vreg135
4880B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
4896B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4912B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4928B		STACKMAP 10, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0]
4944B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4960B		%vreg132<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%retval] GR64:%vreg132
4976B		%RAX<def> = COPY %vreg132; GR64:%vreg132
4992B		RETQ %RAX<imp-use,kill>

# End machine code for function bzopen_or_bzdopen.


selectOrSplit GR32:%vreg10 [16r,432r:0)  0@16r w=3.713235e-03
hints: %ECX
missed hint %ECX
assigning %vreg10 to %EBX: BH [16r,432r:0)  0@16r BL [16r,432r:0)  0@16r

selectOrSplit GR64:%vreg8 [32r,416r:0)  0@32r w=3.864796e-03
hints: %RDX
missed hint %RDX
%R14 is available at cost 1
Only trying the first 10 regs.
should evict: %vreg10 [16r,432r:0)  0@16r w= 3.713235e-03
hints: %ECX
can reassign: %vreg10 [16r,432r:0)  0@16r from %RBX to %ECX
should evict: %vreg10 [16r,432r:0)  0@16r w= 3.713235e-03
hints: %ECX
can reassign: %vreg10 [16r,432r:0)  0@16r from %RBX to %ECX
evicting %RBX interference: Cascade 1
unassigning %vreg10 from %EBX: BH BL
assigning %vreg8 to %RBX: BH [32r,416r:0)  0@32r BL [32r,416r:0)  0@32r
queuing new interval: %vreg10 [16r,432r:0)  0@16r

selectOrSplit GR32:%vreg10 [16r,432r:0)  0@16r w=3.713235e-03
hints: %ECX
missed hint %ECX
%R14D is available at cost 1
Only trying the first 10 regs.
assigning %vreg10 to %R14D: R14B [16r,432r:0)  0@16r

selectOrSplit GR32:%vreg6 [48r,400r:0)  0@48r w=4.029255e-03
hints: %ESI
missed hint %ESI
%R15D is available at cost 1
Only trying the first 10 regs.
should evict: %vreg8 [32r,416r:0)  0@32r w= 3.864796e-03
hints: %RDX
can reassign: %vreg8 [32r,416r:0)  0@32r from %EBX to %RDX
should evict: %vreg8 [32r,416r:0)  0@32r w= 3.864796e-03
hints: %RDX
can reassign: %vreg8 [32r,416r:0)  0@32r from %EBX to %RDX
evicting %EBX interference: Cascade 2
unassigning %vreg8 from %RBX: BH BL
assigning %vreg6 to %EBX: BH [48r,400r:0)  0@48r BL [48r,400r:0)  0@48r
queuing new interval: %vreg8 [32r,416r:0)  0@32r

selectOrSplit GR64:%vreg8 [32r,416r:0)  0@32r w=3.864796e-03
hints: %RDX
missed hint %RDX
%R15 is available at cost 1
Only trying the first 10 regs.
assigning %vreg8 to %R15: R15B [32r,416r:0)  0@32r

selectOrSplit GR64:%vreg4 [64r,384r:0)  0@64r w=4.208333e-03
hints: %RDI
missed hint %RDI
%R12 is available at cost 1
Only trying the first 10 regs.
should evict: %vreg6 [48r,400r:0)  0@48r w= 4.029255e-03
hints: %ESI
can reassign: %vreg6 [48r,400r:0)  0@48r from %RBX to %ESI
should evict: %vreg6 [48r,400r:0)  0@48r w= 4.029255e-03
hints: %ESI
can reassign: %vreg6 [48r,400r:0)  0@48r from %RBX to %ESI
evicting %RBX interference: Cascade 3
unassigning %vreg6 from %EBX: BH BL
assigning %vreg4 to %RBX: BH [64r,384r:0)  0@64r BL [64r,384r:0)  0@64r
queuing new interval: %vreg6 [48r,400r:0)  0@48r

selectOrSplit GR32:%vreg6 [48r,400r:0)  0@48r w=4.029255e-03
hints: %ESI
missed hint %ESI
%R12D is available at cost 1
Only trying the first 10 regs.
assigning %vreg6 to %R12D: R12B [48r,400r:0)  0@48r

selectOrSplit GR64:%vreg19 [144r,208r:0)  0@144r w=2.176724e-03
hints: %RDI
assigning %vreg19 to %RDI: DIL [144r,208r:0)  0@144r

selectOrSplit GR64:%vreg20 [176r,224r:0)  0@176r w=4.508928e-03
hints: %RSI
assigning %vreg20 to %RSI: SIL [176r,224r:0)  0@176r

selectOrSplit GR64:%vreg17 [320r,552r:0)  0@320r w=1.598101e-03
hints: %RDI
assigning %vreg17 to %RDI: DIL [320r,552r:0)  0@320r

selectOrSplit GR32:%vreg117 [1408r,1440r:0)  0@1408r w=1.461227e-04
hints: %EDI
assigning %vreg117 to %EDI: DIL [1408r,1440r:0)  0@1408r

selectOrSplit GR32:%vreg115 [1488r,1552r:0)  0@1488r w=1.360453e-04
hints: %EAX
assigning %vreg115 to %EAX: AH [1488r,1552r:0)  0@1488r AL [1488r,1552r:0)  0@1488r

selectOrSplit GR64:%vreg35 [1952r,2032r:0)[2032r,2080r:1)  0@1952r 1@2032r w=3.825758e-03
hints: %RSI
assigning %vreg35 to %RSI: SIL [1952r,2032r:0)[2032r,2080r:1)  0@1952r 1@2032r

selectOrSplit GR64:%vreg36 [1984r,2064r:0)  0@1984r w=1.052083e-03
hints: %RDI
assigning %vreg36 to %RDI: DIL [1984r,2064r:0)  0@1984r

selectOrSplit GR64:%vreg31 [2128r,2128d:0)  0@2128r w=inf
hints: %RAX
assigning %vreg31 to %RAX: AH [2128r,2128d:0)  0@2128r AL [2128r,2128d:0)  0@2128r

selectOrSplit GR64:%vreg26 [2144r,2256r:0)  0@2144r w=9.863281e-04
hints: %RSI
assigning %vreg26 to %RSI: SIL [2144r,2256r:0)  0@2144r

selectOrSplit GR64:%vreg28 [2160r,2240r:0)  0@2160r w=1.052083e-03
hints: %RDI
assigning %vreg28 to %RDI: DIL [2160r,2240r:0)  0@2160r

selectOrSplit GR64:%vreg27 [2304r,2304d:0)  0@2304r w=inf
hints: %RAX
assigning %vreg27 to %RAX: AH [2304r,2304d:0)  0@2304r AL [2304r,2304d:0)  0@2304r

selectOrSplit GR64:%vreg49 [2464r,2552r:0)  0@2464r w=5.174180e-04
hints: %RDI
assigning %vreg49 to %RDI: DIL [2464r,2552r:0)  0@2464r

selectOrSplit GR32:%vreg44 [2592r,2672r:0)  0@2592r w=5.260417e-04
hints: %EAX
assigning %vreg44 to %EAX: AH [2592r,2672r:0)  0@2592r AL [2592r,2672r:0)  0@2592r

selectOrSplit GR64:%vreg54 [2944r,3008r:0)  0@2944r w=1.360453e-04
hints: %RSI
assigning %vreg54 to %RSI: SIL [2944r,3008r:0)  0@2944r

selectOrSplit GR64:%vreg55 [2960r,2992r:0)  0@2960r w=2.922454e-04
hints: %RDI
assigning %vreg55 to %RDI: DIL [2960r,2992r:0)  0@2960r

selectOrSplit GR64:%vreg53 [3056r,3120r:0)  0@3056r w=2.720905e-04
hints: %RAX
assigning %vreg53 to %RAX: AH [3056r,3120r:0)  0@3056r AL [3056r,3120r:0)  0@3056r

selectOrSplit GR64:%vreg41 [3184r,3248r:0)  0@3184r w=5.441810e-04
hints: %RSI
assigning %vreg41 to %RSI: SIL [3184r,3248r:0)  0@3184r

selectOrSplit GR32:%vreg42 [3200r,3232r:0)  0@3200r w=1.168981e-03
hints: %EDI
assigning %vreg42 to %EDI: DIL [3200r,3232r:0)  0@3200r

selectOrSplit GR64:%vreg40 [3296r,3360r:0)  0@3296r w=1.088362e-03
hints: %RAX
assigning %vreg40 to %RAX: AH [3296r,3360r:0)  0@3296r AL [3296r,3360r:0)  0@3296r

selectOrSplit GR64:%vreg77 [3696r,3792r:0)  0@3696r w=2.545363e-04
hints: %RDI
assigning %vreg77 to %RDI: DIL [3696r,3792r:0)  0@3696r

selectOrSplit GR64:%vreg86 [3712r,3808r:0)  0@3712r w=5.090726e-04
hints: %RSI
assigning %vreg86 to %RSI: SIL [3712r,3808r:0)  0@3712r

selectOrSplit GR32:%vreg85 [3728r,3824r:0)  0@3728r w=5.090726e-04
hints: %EDX
assigning %vreg85 to %EDX: DH [3728r,3824r:0)  0@3728r DL [3728r,3824r:0)  0@3728r

selectOrSplit GR32:%vreg84 [3744r,3840r:0)  0@3744r w=5.090726e-04
hints: %ECX
assigning %vreg84 to %ECX: CH [3744r,3840r:0)  0@3744r CL [3744r,3840r:0)  0@3744r

selectOrSplit GR32:%vreg83 [3760r,3856r:0)  0@3760r w=5.090726e-04
hints: %R8D
assigning %vreg83 to %R8D: R8B [3760r,3856r:0)  0@3760r

selectOrSplit GR64:%vreg82 [3904r,3968r:0)  0@3904r w=5.441810e-04
hints: %RAX
assigning %vreg82 to %RAX: AH [3904r,3968r:0)  0@3904r AL [3904r,3968r:0)  0@3904r

selectOrSplit GR64:%vreg62 [4016r,4128r:0)  0@4016r w=2.465820e-04
hints: %RDI
assigning %vreg62 to %RDI: DIL [4016r,4128r:0)  0@4016r

selectOrSplit GR64:%vreg70 [4032r,4192r:0)  0@4032r w=2.254464e-04
hints: %R8
assigning %vreg70 to %R8: R8B [4032r,4192r:0)  0@4032r

selectOrSplit GR64:%vreg73 [4048r,4144r:0)  0@4048r w=5.090726e-04
hints: %RSI
assigning %vreg73 to %RSI: SIL [4048r,4144r:0)  0@4048r

selectOrSplit GR32:%vreg72 [4064r,4160r:0)  0@4064r w=5.090726e-04
hints: %EDX
assigning %vreg72 to %EDX: DH [4064r,4160r:0)  0@4064r DL [4064r,4160r:0)  0@4064r

selectOrSplit GR32:%vreg71 [4080r,4176r:0)  0@4080r w=5.090726e-04
hints: %ECX
assigning %vreg71 to %ECX: CH [4080r,4176r:0)  0@4080r CL [4080r,4176r:0)  0@4080r

selectOrSplit GR32:%vreg69 [4096r,4208r:0)  0@4096r w=4.931641e-04
hints: %R9D
assigning %vreg69 to %R9D: R9B [4096r,4208r:0)  0@4096r

selectOrSplit GR64:%vreg68 [4256r,4320r:0)  0@4256r w=5.441810e-04
hints: %RAX
assigning %vreg68 to %RAX: AH [4256r,4320r:0)  0@4256r AL [4256r,4320r:0)  0@4256r

selectOrSplit GR64:%vreg98 [4528r,4560r:0)  0@4528r w=1.461227e-04
hints: %RDI
assigning %vreg98 to %RDI: DIL [4528r,4560r:0)  0@4528r

selectOrSplit GR32:%vreg97 [4608r,4608d:0)  0@4608r w=inf
hints: %EAX
assigning %vreg97 to %EAX: AH [4608r,4608d:0)  0@4608r AL [4608r,4608d:0)  0@4608r

selectOrSplit GR64:%vreg134 [4784r,4848r:0)  0@4784r w=2.176724e-03
hints: %RDI
assigning %vreg134 to %RDI: DIL [4784r,4848r:0)  0@4784r

selectOrSplit GR64:%vreg135 [4816r,4864r:0)  0@4816r w=4.508928e-03
hints: %RSI
assigning %vreg135 to %RSI: SIL [4816r,4864r:0)  0@4816r

selectOrSplit GR64:%vreg132 [4960r,4976r:0)  0@4960r w=inf
hints: %RAX
assigning %vreg132 to %RAX: AH [4960r,4976r:0)  0@4960r AL [4960r,4976r:0)  0@4960r

selectOrSplit GR32:%vreg103 [896r,1088r:0)[1088r,1088d:1)  0@896r 1@1088r w=2.554806e-03
assigning %vreg103 to %EAX: AH [896r,1088r:0)[1088r,1088d:1)  0@896r 1@1088r AL [896r,1088r:0)[1088r,1088d:1)  0@896r 1@1088r

selectOrSplit GR64:%vreg136 [2768r,2816B:1)[2832r,2864B:0)[2864B,2896r:2)  0@2832r 1@2768r 2@2864B-phi w=7.352941e-04
assigning %vreg136 to %RAX: AH [2768r,2816B:1)[2832r,2864B:0)[2864B,2896r:2)  0@2832r 1@2768r 2@2864B-phi AL [2768r,2816B:1)[2832r,2864B:0)[2864B,2896r:2)  0@2832r 1@2768r 2@2864B-phi

selectOrSplit GR64:%vreg23 [816r,832r:0)  0@816r w=inf
assigning %vreg23 to %RAX: AH [816r,832r:0)  0@816r AL [816r,832r:0)  0@816r

selectOrSplit GR64:%vreg100 [880r,896r:0)  0@880r w=inf
assigning %vreg100 to %RAX: AH [880r,896r:0)  0@880r AL [880r,896r:0)  0@880r

selectOrSplit GR32:%vreg101 [912r,928r:0)[928r,928d:1)  0@912r 1@928r w=inf
hints: %EAX
assigning %vreg101 to %ECX: CH [912r,928r:0)[928r,928d:1)  0@912r 1@928r CL [912r,928r:0)[928r,928d:1)  0@912r 1@928r

selectOrSplit GR32:%vreg102 [992r,1008r:0)[1008r,1008d:1)  0@992r 1@1008r w=inf
hints: %EAX
assigning %vreg102 to %ECX: CH [992r,1008r:0)[1008r,1008d:1)  0@992r 1@1008r CL [992r,1008r:0)[1008r,1008d:1)  0@992r 1@1008r

selectOrSplit GR32:%vreg104 [1296r,1328r:0)  0@1296r w=inf
assigning %vreg104 to %EAX: AH [1296r,1328r:0)  0@1296r AL [1296r,1328r:0)  0@1296r

selectOrSplit GR64:%vreg119 [1392r,1408r:0)  0@1392r w=inf
assigning %vreg119 to %RAX: AH [1392r,1408r:0)  0@1392r AL [1392r,1408r:0)  0@1392r

selectOrSplit GR64:%vreg112 [1616r,1632r:0)  0@1616r w=inf
assigning %vreg112 to %RAX: AH [1616r,1632r:0)  0@1616r AL [1616r,1632r:0)  0@1616r

selectOrSplit GR32:%vreg108 [1632r,1664r:0)[1664r,1680r:1)  0@1632r 1@1664r w=inf
assigning %vreg108 to %EAX: AH [1632r,1664r:0)[1664r,1680r:1)  0@1632r 1@1664r AL [1632r,1664r:0)[1664r,1680r:1)  0@1632r 1@1664r

selectOrSplit GR64:%vreg126 [1728r,1744r:0)  0@1728r w=inf
assigning %vreg126 to %RAX: AH [1728r,1744r:0)  0@1728r AL [1728r,1744r:0)  0@1728r

selectOrSplit GR32:%vreg122 [1744r,1776r:0)[1776r,1792r:1)  0@1744r 1@1776r w=inf
assigning %vreg122 to %EAX: AH [1744r,1776r:0)[1776r,1792r:1)  0@1744r 1@1776r AL [1744r,1776r:0)[1776r,1792r:1)  0@1744r 1@1776r

selectOrSplit GR64:%vreg129 [1856r,1888r:0)[1888r,1904r:1)  0@1856r 1@1888r w=inf
assigning %vreg129 to %RAX: AH [1856r,1888r:0)[1888r,1904r:1)  0@1856r 1@1888r AL [1856r,1888r:0)[1888r,1904r:1)  0@1856r 1@1888r

selectOrSplit GR64:%vreg34 [1968r,2032r:0)  0@1968r w=1.077586e-03
assigning %vreg34 to %RAX: AH [1968r,2032r:0)  0@1968r AL [1968r,2032r:0)  0@1968r

selectOrSplit GR64:%vreg92 [4400r,4416r:0)  0@4400r w=inf
assigning %vreg92 to %RAX: AH [4400r,4416r:0)  0@4400r AL [4400r,4416r:0)  0@4400r

selectOrSplit GR64:%vreg95 [4464r,4480r:0)  0@4464r w=inf
assigning %vreg95 to %RAX: AH [4464r,4480r:0)  0@4464r AL [4464r,4480r:0)  0@4464r

selectOrSplit GR64:%vreg89 [4736r,4752r:0)  0@4736r w=inf
assigning %vreg89 to %RAX: AH [4736r,4752r:0)  0@4736r AL [4736r,4752r:0)  0@4736r

********** STACK TRANSFORMATION METADATA **********
********** Function: bzopen_or_bzdopen
********** REGISTER MAP **********
[%vreg4 -> %RBX] GR64
[%vreg6 -> %R12D] GR32
[%vreg8 -> %R15] GR64
[%vreg10 -> %R14D] GR32
[%vreg17 -> %RDI] GR64
[%vreg19 -> %RDI] GR64
[%vreg20 -> %RSI] GR64
[%vreg23 -> %RAX] GR64
[%vreg26 -> %RSI] GR64
[%vreg27 -> %RAX] GR64
[%vreg28 -> %RDI] GR64
[%vreg31 -> %RAX] GR64
[%vreg34 -> %RAX] GR64
[%vreg35 -> %RSI] GR64
[%vreg36 -> %RDI] GR64
[%vreg40 -> %RAX] GR64
[%vreg41 -> %RSI] GR64
[%vreg42 -> %EDI] GR32
[%vreg44 -> %EAX] GR32
[%vreg49 -> %RDI] GR64
[%vreg53 -> %RAX] GR64
[%vreg54 -> %RSI] GR64
[%vreg55 -> %RDI] GR64
[%vreg62 -> %RDI] GR64
[%vreg68 -> %RAX] GR64
[%vreg69 -> %R9D] GR32
[%vreg70 -> %R8] GR64
[%vreg71 -> %ECX] GR32
[%vreg72 -> %EDX] GR32
[%vreg73 -> %RSI] GR64
[%vreg77 -> %RDI] GR64
[%vreg82 -> %RAX] GR64
[%vreg83 -> %R8D] GR32
[%vreg84 -> %ECX] GR32
[%vreg85 -> %EDX] GR32
[%vreg86 -> %RSI] GR64
[%vreg89 -> %RAX] GR64
[%vreg92 -> %RAX] GR64
[%vreg95 -> %RAX] GR64
[%vreg97 -> %EAX] GR32
[%vreg98 -> %RDI] GR64
[%vreg100 -> %RAX] GR64
[%vreg101 -> %ECX] GR32
[%vreg102 -> %ECX] GR32
[%vreg103 -> %EAX] GR32
[%vreg104 -> %EAX] GR32
[%vreg108 -> %EAX] GR32
[%vreg112 -> %RAX] GR64
[%vreg115 -> %EAX] GR32
[%vreg117 -> %EDI] GR32
[%vreg119 -> %RAX] GR64
[%vreg122 -> %EAX] GR32
[%vreg126 -> %RAX] GR64
[%vreg129 -> %RAX] GR64
[%vreg132 -> %RAX] GR64
[%vreg134 -> %RDI] GR64
[%vreg135 -> %RSI] GR64
[%vreg136 -> %RAX] GR64


Stackmap 0:
  STACKMAP 0, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, %vreg6, 0, <fi#2>, 0, 0, <fi#10>, 0, %vreg8, 0, <fi#3>, 0, 0, <fi#9>, 0, 0, <fi#15>, 0, %vreg10, 0, <fi#4>, 0, %vreg4, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack2](align=4) LD8[FixedStack10] LD8[FixedStack3] LD8[FixedStack9](align=1) LD8[FixedStack15](align=4) LD8[FixedStack4](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4) GR32:%vreg6,%vreg10 GR64:%vreg8,%vreg4

i32* %blockSize100k: in stack slot 7 (size: 4)
i32* %bzerr: in stack slot 5 (size: 4)
i8** %bzfp: in stack slot 11 (size: 8)
i32 %fd: in register %R12D (vreg 6)
i32* %fd.addr: in stack slot 2 (size: 4)
%struct._IO_FILE** %fp: in stack slot 10 (size: 8)
i8* %mode: in register %R15 (vreg 8)
i8** %mode.addr: in stack slot 3 (size: 8)
[10 x i8]* %mode2: in stack slot 9 (size: 10)
i32* %nUnused: in stack slot 15 (size: 4)
i32 %open_mode: in register %R14D (vreg 10)
i32* %open_mode.addr: in stack slot 4 (size: 4)
i8* %path: in register %RBX (vreg 4)
i8** %path.addr: in stack slot 1 (size: 8)
i8** %retval: in stack slot 0 (size: 8)
i32* %smallMode: in stack slot 14 (size: 4)
[5000 x i8]* %unused: in stack slot 6 (size: 5000)
i32* %verbosity: in stack slot 12 (size: 4)
i32* %workFactor: in stack slot 13 (size: 4)
i32* %writing: in stack slot 8 (size: 4)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#2>, 0, 0, <fi#10>, 0, 0, <fi#3>, 0, 0, <fi#9>, 0, 0, <fi#15>, 0, 0, <fi#4>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack2](align=4) LD8[FixedStack10] LD8[FixedStack3] LD8[FixedStack9](align=1) LD8[FixedStack15](align=4) LD8[FixedStack4](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)

i32* %blockSize100k: in stack slot 7 (size: 4)
i32* %bzerr: in stack slot 5 (size: 4)
i8** %bzfp: in stack slot 11 (size: 8)
i32* %fd.addr: in stack slot 2 (size: 4)
%struct._IO_FILE** %fp: in stack slot 10 (size: 8)
i8** %mode.addr: in stack slot 3 (size: 8)
[10 x i8]* %mode2: in stack slot 9 (size: 10)
i32* %nUnused: in stack slot 15 (size: 4)
i32* %open_mode.addr: in stack slot 4 (size: 4)
i8** %path.addr: in stack slot 1 (size: 8)
i8** %retval: in stack slot 0 (size: 8)
i32* %smallMode: in stack slot 14 (size: 4)
[5000 x i8]* %unused: in stack slot 6 (size: 5000)
i32* %verbosity: in stack slot 12 (size: 4)
i32* %workFactor: in stack slot 13 (size: 4)
i32* %writing: in stack slot 8 (size: 4)

Duplicate operand locations:


Stackmap 2:
  STACKMAP 2, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#2>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, 0, <fi#15>, 0, 0, <fi#4>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack2](align=4) LD8[FixedStack10] LD8[FixedStack9](align=1) LD8[FixedStack15](align=4) LD8[FixedStack4](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)

i32* %blockSize100k: in stack slot 7 (size: 4)
i32* %bzerr: in stack slot 5 (size: 4)
i8** %bzfp: in stack slot 11 (size: 8)
i32* %fd.addr: in stack slot 2 (size: 4)
%struct._IO_FILE** %fp: in stack slot 10 (size: 8)
[10 x i8]* %mode2: in stack slot 9 (size: 10)
i32* %nUnused: in stack slot 15 (size: 4)
i32* %open_mode.addr: in stack slot 4 (size: 4)
i8** %path.addr: in stack slot 1 (size: 8)
i8** %retval: in stack slot 0 (size: 8)
i32* %smallMode: in stack slot 14 (size: 4)
[5000 x i8]* %unused: in stack slot 6 (size: 5000)
i32* %verbosity: in stack slot 12 (size: 4)
i32* %workFactor: in stack slot 13 (size: 4)
i32* %writing: in stack slot 8 (size: 4)

Duplicate operand locations:


Stackmap 3:
  STACKMAP 3, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#2>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, 0, <fi#15>, 0, 0, <fi#4>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack2](align=4) LD8[FixedStack10] LD8[FixedStack9](align=1) LD8[FixedStack15](align=4) LD8[FixedStack4](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)

i32* %blockSize100k: in stack slot 7 (size: 4)
i32* %bzerr: in stack slot 5 (size: 4)
i8** %bzfp: in stack slot 11 (size: 8)
i32* %fd.addr: in stack slot 2 (size: 4)
%struct._IO_FILE** %fp: in stack slot 10 (size: 8)
[10 x i8]* %mode2: in stack slot 9 (size: 10)
i32* %nUnused: in stack slot 15 (size: 4)
i32* %open_mode.addr: in stack slot 4 (size: 4)
i8** %path.addr: in stack slot 1 (size: 8)
i8** %retval: in stack slot 0 (size: 8)
i32* %smallMode: in stack slot 14 (size: 4)
[5000 x i8]* %unused: in stack slot 6 (size: 5000)
i32* %verbosity: in stack slot 12 (size: 4)
i32* %workFactor: in stack slot 13 (size: 4)
i32* %writing: in stack slot 8 (size: 4)

Duplicate operand locations:


Stackmap 4:
  STACKMAP 4, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, 0, <fi#15>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack9](align=1) LD8[FixedStack15](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)

i32* %blockSize100k: in stack slot 7 (size: 4)
i32* %bzerr: in stack slot 5 (size: 4)
i8** %bzfp: in stack slot 11 (size: 8)
%struct._IO_FILE** %fp: in stack slot 10 (size: 8)
[10 x i8]* %mode2: in stack slot 9 (size: 10)
i32* %nUnused: in stack slot 15 (size: 4)
i8** %path.addr: in stack slot 1 (size: 8)
i8** %retval: in stack slot 0 (size: 8)
i32* %smallMode: in stack slot 14 (size: 4)
[5000 x i8]* %unused: in stack slot 6 (size: 5000)
i32* %verbosity: in stack slot 12 (size: 4)
i32* %workFactor: in stack slot 13 (size: 4)
i32* %writing: in stack slot 8 (size: 4)

Duplicate operand locations:


Stackmap 5:
  STACKMAP 5, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#15>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack15](align=4) LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)

i32* %blockSize100k: in stack slot 7 (size: 4)
i32* %bzerr: in stack slot 5 (size: 4)
i8** %bzfp: in stack slot 11 (size: 8)
%struct._IO_FILE** %fp: in stack slot 10 (size: 8)
i32* %nUnused: in stack slot 15 (size: 4)
i8** %retval: in stack slot 0 (size: 8)
i32* %smallMode: in stack slot 14 (size: 4)
[5000 x i8]* %unused: in stack slot 6 (size: 5000)
i32* %verbosity: in stack slot 12 (size: 4)
i32* %workFactor: in stack slot 13 (size: 4)
i32* %writing: in stack slot 8 (size: 4)

Duplicate operand locations:


Stackmap 6:
  STACKMAP 6, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#15>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack15](align=4) LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)

i32* %blockSize100k: in stack slot 7 (size: 4)
i32* %bzerr: in stack slot 5 (size: 4)
i8** %bzfp: in stack slot 11 (size: 8)
%struct._IO_FILE** %fp: in stack slot 10 (size: 8)
i32* %nUnused: in stack slot 15 (size: 4)
i8** %retval: in stack slot 0 (size: 8)
i32* %smallMode: in stack slot 14 (size: 4)
[5000 x i8]* %unused: in stack slot 6 (size: 5000)
i32* %verbosity: in stack slot 12 (size: 4)
i32* %workFactor: in stack slot 13 (size: 4)
i32* %writing: in stack slot 8 (size: 4)

Duplicate operand locations:


Stackmap 7:
  STACKMAP 7, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack0]

i8** %bzfp: in stack slot 11 (size: 8)
%struct._IO_FILE** %fp: in stack slot 10 (size: 8)
i8** %retval: in stack slot 0 (size: 8)

Duplicate operand locations:


Stackmap 8:
  STACKMAP 8, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack0]

i8** %bzfp: in stack slot 11 (size: 8)
%struct._IO_FILE** %fp: in stack slot 10 (size: 8)
i8** %retval: in stack slot 0 (size: 8)

Duplicate operand locations:


Stackmap 9:
  STACKMAP 9, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0]

i8** %retval: in stack slot 0 (size: 8)

Duplicate operand locations:


Stackmap 10:
  STACKMAP 10, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0]

i8** %retval: in stack slot 0 (size: 8)

Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, %vreg6, 0, <fi#2>, 0, 0, <fi#10>, 0, %vreg8, 0, <fi#3>, 0, 0, <fi#9>, 0, 0, <fi#15>, 0, %vreg10, 0, <fi#4>, 0, %vreg4, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack2](align=4) LD8[FixedStack10] LD8[FixedStack3] LD8[FixedStack9](align=1) LD8[FixedStack15](align=4) LD8[FixedStack4](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4) GR32:%vreg6,%vreg10 GR64:%vreg8,%vreg4
  -> Call instruction SlotIndex 240B, searching vregs 0 -> 137 and stack slots -1 -> 16

  STACKMAP 1, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#2>, 0, 0, <fi#10>, 0, 0, <fi#3>, 0, 0, <fi#9>, 0, 0, <fi#15>, 0, 0, <fi#4>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack2](align=4) LD8[FixedStack10] LD8[FixedStack3] LD8[FixedStack9](align=1) LD8[FixedStack15](align=4) LD8[FixedStack4](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)
  -> Call instruction SlotIndex 1456B, searching vregs 0 -> 137 and stack slots -1 -> 16

  STACKMAP 2, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#2>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, 0, <fi#15>, 0, 0, <fi#4>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack2](align=4) LD8[FixedStack10] LD8[FixedStack9](align=1) LD8[FixedStack15](align=4) LD8[FixedStack4](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)
  -> Call instruction SlotIndex 2096B, searching vregs 0 -> 137 and stack slots -1 -> 16

  STACKMAP 3, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#2>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, 0, <fi#15>, 0, 0, <fi#4>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack2](align=4) LD8[FixedStack10] LD8[FixedStack9](align=1) LD8[FixedStack15](align=4) LD8[FixedStack4](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)
  -> Call instruction SlotIndex 2272B, searching vregs 0 -> 137 and stack slots -1 -> 16

  STACKMAP 4, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, 0, <fi#15>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack9](align=1) LD8[FixedStack15](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)
  -> Call instruction SlotIndex 2560B, searching vregs 0 -> 137 and stack slots -1 -> 16

  STACKMAP 5, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#15>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack15](align=4) LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)
  -> Call instruction SlotIndex 3024B, searching vregs 0 -> 137 and stack slots -1 -> 16

  STACKMAP 6, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#15>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack15](align=4) LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)
  -> Call instruction SlotIndex 3264B, searching vregs 0 -> 137 and stack slots -1 -> 16

  STACKMAP 7, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack0]
  -> Call instruction SlotIndex 3872B, searching vregs 0 -> 137 and stack slots -1 -> 16

  STACKMAP 8, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack0]
  -> Call instruction SlotIndex 4224B, searching vregs 0 -> 137 and stack slots -1 -> 16

  STACKMAP 9, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0]
  -> Call instruction SlotIndex 4576B, searching vregs 0 -> 137 and stack slots -1 -> 16

  STACKMAP 10, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0]
  -> Call instruction SlotIndex 4880B, searching vregs 0 -> 137 and stack slots -1 -> 16

********** REWRITE VIRTUAL REGISTERS **********
********** Function: bzopen_or_bzdopen
********** REGISTER MAP **********
[%vreg4 -> %RBX] GR64
[%vreg6 -> %R12D] GR32
[%vreg8 -> %R15] GR64
[%vreg10 -> %R14D] GR32
[%vreg17 -> %RDI] GR64
[%vreg19 -> %RDI] GR64
[%vreg20 -> %RSI] GR64
[%vreg23 -> %RAX] GR64
[%vreg26 -> %RSI] GR64
[%vreg27 -> %RAX] GR64
[%vreg28 -> %RDI] GR64
[%vreg31 -> %RAX] GR64
[%vreg34 -> %RAX] GR64
[%vreg35 -> %RSI] GR64
[%vreg36 -> %RDI] GR64
[%vreg40 -> %RAX] GR64
[%vreg41 -> %RSI] GR64
[%vreg42 -> %EDI] GR32
[%vreg44 -> %EAX] GR32
[%vreg49 -> %RDI] GR64
[%vreg53 -> %RAX] GR64
[%vreg54 -> %RSI] GR64
[%vreg55 -> %RDI] GR64
[%vreg62 -> %RDI] GR64
[%vreg68 -> %RAX] GR64
[%vreg69 -> %R9D] GR32
[%vreg70 -> %R8] GR64
[%vreg71 -> %ECX] GR32
[%vreg72 -> %EDX] GR32
[%vreg73 -> %RSI] GR64
[%vreg77 -> %RDI] GR64
[%vreg82 -> %RAX] GR64
[%vreg83 -> %R8D] GR32
[%vreg84 -> %ECX] GR32
[%vreg85 -> %EDX] GR32
[%vreg86 -> %RSI] GR64
[%vreg89 -> %RAX] GR64
[%vreg92 -> %RAX] GR64
[%vreg95 -> %RAX] GR64
[%vreg97 -> %EAX] GR32
[%vreg98 -> %RDI] GR64
[%vreg100 -> %RAX] GR64
[%vreg101 -> %ECX] GR32
[%vreg102 -> %ECX] GR32
[%vreg103 -> %EAX] GR32
[%vreg104 -> %EAX] GR32
[%vreg108 -> %EAX] GR32
[%vreg112 -> %RAX] GR64
[%vreg115 -> %EAX] GR32
[%vreg117 -> %EDI] GR32
[%vreg119 -> %RAX] GR64
[%vreg122 -> %EAX] GR32
[%vreg126 -> %RAX] GR64
[%vreg129 -> %RAX] GR64
[%vreg132 -> %RAX] GR64
[%vreg134 -> %RDI] GR64
[%vreg135 -> %RSI] GR64
[%vreg136 -> %RAX] GR64

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %ECX %ESI %RDI %RDX
16B		%vreg10<def> = COPY %ECX; GR32:%vreg10
32B		%vreg8<def> = COPY %RDX; GR64:%vreg8
48B		%vreg6<def> = COPY %ESI; GR32:%vreg6
64B		%vreg4<def> = COPY %RDI; GR64:%vreg4
144B		%vreg19<def> = MOV64ri <ga:@bzopen_or_bzdopen>; GR64:%vreg19
176B		%vreg20<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg20
192B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
208B		%RDI<def> = COPY %vreg19<kill>; GR64:%vreg19
224B		%RSI<def> = COPY %vreg20<kill>; GR64:%vreg20
240B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
256B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
320B		%vreg17<def> = LEA64r <fi#9>, 1, %noreg, 0, %noreg; GR64:%vreg17
336B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
352B		STACKMAP 0, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, %vreg6, 0, <fi#2>, 0, 0, <fi#10>, 0, %vreg8, 0, <fi#3>, 0, 0, <fi#9>, 0, 0, <fi#15>, 0, %vreg10, 0, <fi#4>, 0, %vreg4, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack2](align=4) LD8[FixedStack10] LD8[FixedStack3] LD8[FixedStack9](align=1) LD8[FixedStack15](align=4) LD8[FixedStack4](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4) GR32:%vreg6,%vreg10 GR64:%vreg8,%vreg4
368B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
384B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg4<kill>; mem:ST8[%path.addr] GR64:%vreg4
400B		MOV32mr <fi#2>, 1, %noreg, 0, %noreg, %vreg6<kill>; mem:ST4[%fd.addr] GR32:%vreg6
416B		MOV64mr <fi#3>, 1, %noreg, 0, %noreg, %vreg8<kill>; mem:ST8[%mode.addr] GR64:%vreg8
432B		MOV32mr <fi#4>, 1, %noreg, 0, %noreg, %vreg10<kill>; mem:ST4[%open_mode.addr] GR32:%vreg10
448B		MOV32mi <fi#7>, 1, %noreg, 0, %noreg, 9; mem:ST4[%blockSize100k]
464B		MOV32mi <fi#8>, 1, %noreg, 0, %noreg, 0; mem:ST4[%writing]
496B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
528B		%ESI<def> = MOV32r0 %EFLAGS<imp-def,dead>
544B		%EDX<def,dead> = MOV32ri 10, %RDX<imp-def>
552B		%RDI<def> = COPY %vreg17<kill>; GR64:%vreg17
560B		CALL64pcrel32 <MCSym=memset>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %RDX<imp-use>
576B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
592B		MOV64mi32 <fi#10>, 1, %noreg, 0, %noreg, 0; mem:ST8[%fp]
608B		MOV64mi32 <fi#11>, 1, %noreg, 0, %noreg, 0; mem:ST8[%bzfp]
624B		MOV32mi <fi#12>, 1, %noreg, 0, %noreg, 0; mem:ST4[%verbosity]
640B		MOV32mi <fi#13>, 1, %noreg, 0, %noreg, 30; mem:ST4[%workFactor]
656B		MOV32mi <fi#14>, 1, %noreg, 0, %noreg, 0; mem:ST4[%smallMode]
672B		MOV32mi <fi#15>, 1, %noreg, 0, %noreg, 0; mem:ST4[%nUnused]
688B		CMP64mi8 <fi#3>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%mode.addr]
704B		JNE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1
> %R14D<def> = COPY %ECX
> %R15<def> = COPY %RDX
> %R12D<def> = COPY %ESI
> %RBX<def> = COPY %RDI
> %RDI<def> = MOV64ri <ga:@bzopen_or_bzdopen>
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = LEA64r <fi#9>, 1, %noreg, 0, %noreg
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 0, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, %R12D, 0, <fi#2>, 0, 0, <fi#10>, 0, %R15, 0, <fi#3>, 0, 0, <fi#9>, 0, 0, <fi#15>, 0, %R14D, 0, <fi#4>, 0, %RBX, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack2](align=4) LD8[FixedStack10] LD8[FixedStack3] LD8[FixedStack9](align=1) LD8[FixedStack15](align=4) LD8[FixedStack4](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %RBX<kill>; mem:ST8[%path.addr]
> MOV32mr <fi#2>, 1, %noreg, 0, %noreg, %R12D<kill>; mem:ST4[%fd.addr]
> MOV64mr <fi#3>, 1, %noreg, 0, %noreg, %R15<kill>; mem:ST8[%mode.addr]
> MOV32mr <fi#4>, 1, %noreg, 0, %noreg, %R14D<kill>; mem:ST4[%open_mode.addr]
> MOV32mi <fi#7>, 1, %noreg, 0, %noreg, 9; mem:ST4[%blockSize100k]
> MOV32mi <fi#8>, 1, %noreg, 0, %noreg, 0; mem:ST4[%writing]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %ESI<def> = MOV32r0 %EFLAGS<imp-def,dead>
> %EDX<def,dead> = MOV32ri 10, %RDX<imp-def>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> CALL64pcrel32 <MCSym=memset>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %RDX<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV64mi32 <fi#10>, 1, %noreg, 0, %noreg, 0; mem:ST8[%fp]
> MOV64mi32 <fi#11>, 1, %noreg, 0, %noreg, 0; mem:ST8[%bzfp]
> MOV32mi <fi#12>, 1, %noreg, 0, %noreg, 0; mem:ST4[%verbosity]
> MOV32mi <fi#13>, 1, %noreg, 0, %noreg, 30; mem:ST4[%workFactor]
> MOV32mi <fi#14>, 1, %noreg, 0, %noreg, 0; mem:ST4[%smallMode]
> MOV32mi <fi#15>, 1, %noreg, 0, %noreg, 0; mem:ST4[%nUnused]
> CMP64mi8 <fi#3>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%mode.addr]
> JNE_1 <BB#2>, %EFLAGS<imp-use,kill>
720B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
736B		MOV64mi32 <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST8[%retval]
752B		JMP_1 <BB#41>
	    Successors according to CFG: BB#41
> MOV64mi32 <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST8[%retval]
> JMP_1 <BB#41>
768B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0
784B		JMP_1 <BB#3>
	    Successors according to CFG: BB#3
> JMP_1 <BB#3>
800B	BB#3: derived from LLVM BB %while.cond
	    Predecessors according to CFG: BB#2 BB#15
816B		%vreg23<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%mode.addr] GR64:%vreg23
832B		CMP8mi %vreg23<kill>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD1[%2] GR64:%vreg23
848B		JE_1 <BB#16>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#16 BB#4
> %RAX<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%mode.addr]
> CMP8mi %RAX<kill>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD1[%2]
> JE_1 <BB#16>, %EFLAGS<imp-use,kill>
864B	BB#4: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#3
880B		%vreg100<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%mode.addr] GR64:%vreg100
896B		%vreg103<def> = MOVSX32rm8 %vreg100<kill>, 1, %noreg, 0, %noreg; mem:LD1[%4] GR32:%vreg103 GR64:%vreg100
912B		%vreg101<def> = COPY %vreg103; GR32:%vreg101,%vreg103
928B		%vreg101<def,dead,tied1> = SUB32ri8 %vreg101<kill,tied0>, 114, %EFLAGS<imp-def>; GR32:%vreg101
944B		JE_1 <BB#7>, %EFLAGS<imp-use,kill>
960B		JMP_1 <BB#5>
	    Successors according to CFG: BB#7 BB#5
> %RAX<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%mode.addr]
> %EAX<def> = MOVSX32rm8 %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD1[%4]
> %ECX<def> = COPY %EAX
> %ECX<def,dead,tied1> = SUB32ri8 %ECX<kill,tied0>, 114, %EFLAGS<imp-def>
> JE_1 <BB#7>, %EFLAGS<imp-use,kill>
> JMP_1 <BB#5>
976B	BB#5: derived from LLVM BB %while.body
	    Live Ins: %EAX
	    Predecessors according to CFG: BB#4
992B		%vreg102<def> = COPY %vreg103; GR32:%vreg102,%vreg103
1008B		%vreg102<def,dead,tied1> = SUB32ri8 %vreg102<kill,tied0>, 115, %EFLAGS<imp-def>; GR32:%vreg102
1024B		JE_1 <BB#9>, %EFLAGS<imp-use,kill>
1040B		JMP_1 <BB#6>
	    Successors according to CFG: BB#9 BB#6
> %ECX<def> = COPY %EAX
> %ECX<def,dead,tied1> = SUB32ri8 %ECX<kill,tied0>, 115, %EFLAGS<imp-def>
> JE_1 <BB#9>, %EFLAGS<imp-use,kill>
> JMP_1 <BB#6>
1056B	BB#6: derived from LLVM BB %while.body
	    Live Ins: %EAX
	    Predecessors according to CFG: BB#5
1088B		%vreg103<def,dead,tied1> = SUB32ri8 %vreg103<kill,tied0>, 119, %EFLAGS<imp-def>; GR32:%vreg103
1104B		JE_1 <BB#8>, %EFLAGS<imp-use,kill>
1120B		JMP_1 <BB#10>
	    Successors according to CFG: BB#8 BB#10
> %EAX<def,dead,tied1> = SUB32ri8 %EAX<kill,tied0>, 119, %EFLAGS<imp-def>
> JE_1 <BB#8>, %EFLAGS<imp-use,kill>
> JMP_1 <BB#10>
1136B	BB#7: derived from LLVM BB %sw.bb
	    Predecessors according to CFG: BB#4
1152B		MOV32mi <fi#8>, 1, %noreg, 0, %noreg, 0; mem:ST4[%writing]
1168B		JMP_1 <BB#15>
	    Successors according to CFG: BB#15
> MOV32mi <fi#8>, 1, %noreg, 0, %noreg, 0; mem:ST4[%writing]
> JMP_1 <BB#15>
1184B	BB#8: derived from LLVM BB %sw.bb.1
	    Predecessors according to CFG: BB#6
1200B		MOV32mi <fi#8>, 1, %noreg, 0, %noreg, 1; mem:ST4[%writing]
1216B		JMP_1 <BB#15>
	    Successors according to CFG: BB#15
> MOV32mi <fi#8>, 1, %noreg, 0, %noreg, 1; mem:ST4[%writing]
> JMP_1 <BB#15>
1232B	BB#9: derived from LLVM BB %sw.bb.2
	    Predecessors according to CFG: BB#5
1248B		MOV32mi <fi#14>, 1, %noreg, 0, %noreg, 1; mem:ST4[%smallMode]
1264B		JMP_1 <BB#15>
	    Successors according to CFG: BB#15
> MOV32mi <fi#14>, 1, %noreg, 0, %noreg, 1; mem:ST4[%smallMode]
> JMP_1 <BB#15>
1280B	BB#10: derived from LLVM BB %sw.default
	    Predecessors according to CFG: BB#6
1296B		%vreg104<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg104
1328B		TEST8ri %vreg104:sub_8bit<kill>, 1, %EFLAGS<imp-def>; GR32:%vreg104
1344B		JNE_1 <BB#11>, %EFLAGS<imp-use,kill>
1360B		JMP_1 <BB#12>
	    Successors according to CFG: BB#12 BB#11
> %EAX<def> = MOV32r0 %EFLAGS<imp-def,dead>
> TEST8ri %AL, 1, %EFLAGS<imp-def>, %EAX<imp-use,kill>
> JNE_1 <BB#11>, %EFLAGS<imp-use,kill>
> JMP_1 <BB#12>
1376B	BB#11: derived from LLVM BB %cond.true
	    Predecessors according to CFG: BB#10
1392B		%vreg119<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%mode.addr] GR64:%vreg119
1408B		%vreg117<def> = MOVSX32rm8 %vreg119<kill>, 1, %noreg, 0, %noreg; mem:LD1[%6] GR32:%vreg117 GR64:%vreg119
1424B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1440B		%EDI<def> = COPY %vreg117<kill>; GR32:%vreg117
1456B		CALL64pcrel32 <ga:@isdigit>, <regmask>, %RSP<imp-use>, %EDI<imp-use>, %EAX<imp-def>
1472B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1488B		%vreg115<def> = COPY %EAX; GR32:%vreg115
1504B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1520B		STACKMAP 1, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#2>, 0, 0, <fi#10>, 0, 0, <fi#3>, 0, 0, <fi#9>, 0, 0, <fi#15>, 0, 0, <fi#4>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack2](align=4) LD8[FixedStack10] LD8[FixedStack3] LD8[FixedStack9](align=1) LD8[FixedStack15](align=4) LD8[FixedStack4](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)
1536B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1552B		CMP32ri8 %vreg115<kill>, 0, %EFLAGS<imp-def>; GR32:%vreg115
1568B		JNE_1 <BB#13>, %EFLAGS<imp-use,kill>
1584B		JMP_1 <BB#14>
	    Successors according to CFG: BB#13 BB#14
> %RAX<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%mode.addr]
> %EDI<def> = MOVSX32rm8 %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD1[%6]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EDI<def> = COPY %EDI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@isdigit>, <regmask>, %RSP<imp-use>, %EDI<imp-use>, %EAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def> = COPY %EAX
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 1, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#2>, 0, 0, <fi#10>, 0, 0, <fi#3>, 0, 0, <fi#9>, 0, 0, <fi#15>, 0, 0, <fi#4>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack2](align=4) LD8[FixedStack10] LD8[FixedStack3] LD8[FixedStack9](align=1) LD8[FixedStack15](align=4) LD8[FixedStack4](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> CMP32ri8 %EAX<kill>, 0, %EFLAGS<imp-def>
> JNE_1 <BB#13>, %EFLAGS<imp-use,kill>
> JMP_1 <BB#14>
1600B	BB#12: derived from LLVM BB %cond.false
	    Predecessors according to CFG: BB#10
1616B		%vreg112<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%mode.addr] GR64:%vreg112
1632B		%vreg108<def> = MOVSX32rm8 %vreg112<kill>, 1, %noreg, 0, %noreg; mem:LD1[%8] GR32:%vreg108 GR64:%vreg112
1664B		%vreg108<def,tied1> = SUB32ri8 %vreg108<kill,tied0>, 48, %EFLAGS<imp-def,dead>; GR32:%vreg108
1680B		CMP32ri8 %vreg108<kill>, 10, %EFLAGS<imp-def>; GR32:%vreg108
1696B		JAE_1 <BB#14>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#14 BB#13
> %RAX<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%mode.addr]
> %EAX<def> = MOVSX32rm8 %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD1[%8]
> %EAX<def,tied1> = SUB32ri8 %EAX<kill,tied0>, 48, %EFLAGS<imp-def,dead>
> CMP32ri8 %EAX<kill>, 10, %EFLAGS<imp-def>
> JAE_1 <BB#14>, %EFLAGS<imp-use,kill>
1712B	BB#13: derived from LLVM BB %if.then.8
	    Predecessors according to CFG: BB#12 BB#11
1728B		%vreg126<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%mode.addr] GR64:%vreg126
1744B		%vreg122<def> = MOVSX32rm8 %vreg126<kill>, 1, %noreg, 0, %noreg; mem:LD1[%10] GR32:%vreg122 GR64:%vreg126
1776B		%vreg122<def,tied1> = SUB32ri8 %vreg122<kill,tied0>, 48, %EFLAGS<imp-def,dead>; GR32:%vreg122
1792B		MOV32mr <fi#7>, 1, %noreg, 0, %noreg, %vreg122<kill>; mem:ST4[%blockSize100k] GR32:%vreg122
	    Successors according to CFG: BB#14
> %RAX<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%mode.addr]
> %EAX<def> = MOVSX32rm8 %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD1[%10]
> %EAX<def,tied1> = SUB32ri8 %EAX<kill,tied0>, 48, %EFLAGS<imp-def,dead>
> MOV32mr <fi#7>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%blockSize100k]
1808B	BB#14: derived from LLVM BB %if.end.11
	    Predecessors according to CFG: BB#12 BB#11 BB#13
1824B		JMP_1 <BB#15>
	    Successors according to CFG: BB#15
> JMP_1 <BB#15>
1840B	BB#15: derived from LLVM BB %sw.epilog
	    Predecessors according to CFG: BB#9 BB#8 BB#7 BB#14
1856B		%vreg129<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%mode.addr] GR64:%vreg129
1888B		%vreg129<def,tied1> = ADD64ri8 %vreg129<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR64:%vreg129
1904B		MOV64mr <fi#3>, 1, %noreg, 0, %noreg, %vreg129<kill>; mem:ST8[%mode.addr] GR64:%vreg129
1920B		JMP_1 <BB#3>
	    Successors according to CFG: BB#3
> %RAX<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%mode.addr]
> %RAX<def,tied1> = ADD64ri8 %RAX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV64mr <fi#3>, 1, %noreg, 0, %noreg, %RAX<kill>; mem:ST8[%mode.addr]
> JMP_1 <BB#3>
1936B	BB#16: derived from LLVM BB %while.end
	    Predecessors according to CFG: BB#3
1952B		%vreg35<def> = MOV64ri <ga:@bzlib__str_7_r_>; GR64:%vreg35
1968B		%vreg34<def> = MOV64ri <ga:@bzlib__str_6_w_>; GR64:%vreg34
1984B		%vreg36<def> = LEA64r <fi#9>, 1, %noreg, 0, %noreg; GR64:%vreg36
2000B		CMP32mi8 <fi#8>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%writing]
2032B		%vreg35<def,tied1> = CMOVNE64rr %vreg35<kill,tied0>, %vreg34<kill>, %EFLAGS<imp-use,kill>; GR64:%vreg35,%vreg34
2048B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2064B		%RDI<def> = COPY %vreg36<kill>; GR64:%vreg36
2080B		%RSI<def> = COPY %vreg35<kill>; GR64:%vreg35
2096B		CALL64pcrel32 <ga:@strcat>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %RAX<imp-def>
2112B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2128B		%vreg31<def,dead> = COPY %RAX; GR64:%vreg31
2144B		%vreg26<def> = MOV64ri <ga:@bzlib__str_8_b_>; GR64:%vreg26
2160B		%vreg28<def> = LEA64r <fi#9>, 1, %noreg, 0, %noreg; GR64:%vreg28
2176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2192B		STACKMAP 2, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#2>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, 0, <fi#15>, 0, 0, <fi#4>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack2](align=4) LD8[FixedStack10] LD8[FixedStack9](align=1) LD8[FixedStack15](align=4) LD8[FixedStack4](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)
2208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2224B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2240B		%RDI<def> = COPY %vreg28<kill>; GR64:%vreg28
2256B		%RSI<def> = COPY %vreg26<kill>; GR64:%vreg26
2272B		CALL64pcrel32 <ga:@strcat>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %RAX<imp-def>
2288B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2304B		%vreg27<def,dead> = COPY %RAX; GR64:%vreg27
2320B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2336B		STACKMAP 3, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#2>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, 0, <fi#15>, 0, 0, <fi#4>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack2](align=4) LD8[FixedStack10] LD8[FixedStack9](align=1) LD8[FixedStack15](align=4) LD8[FixedStack4](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)
2352B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2368B		CMP32mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%open_mode.addr]
2384B		JNE_1 <BB#25>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#25 BB#17
> %RSI<def> = MOV64ri <ga:@bzlib__str_7_r_>
> %RAX<def> = MOV64ri <ga:@bzlib__str_6_w_>
> %RDI<def> = LEA64r <fi#9>, 1, %noreg, 0, %noreg
> CMP32mi8 <fi#8>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%writing]
> %RSI<def,tied1> = CMOVNE64rr %RSI<kill,tied0>, %RAX<kill>, %EFLAGS<imp-use,kill>
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@strcat>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %RAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RAX<def,dead> = COPY %RAX
Deleting identity copy.
> %RSI<def> = MOV64ri <ga:@bzlib__str_8_b_>
> %RDI<def> = LEA64r <fi#9>, 1, %noreg, 0, %noreg
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 2, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#2>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, 0, <fi#15>, 0, 0, <fi#4>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack2](align=4) LD8[FixedStack10] LD8[FixedStack9](align=1) LD8[FixedStack15](align=4) LD8[FixedStack4](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@strcat>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %RAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RAX<def,dead> = COPY %RAX
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 3, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#2>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, 0, <fi#15>, 0, 0, <fi#4>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack2](align=4) LD8[FixedStack10] LD8[FixedStack9](align=1) LD8[FixedStack15](align=4) LD8[FixedStack4](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> CMP32mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%open_mode.addr]
> JNE_1 <BB#25>, %EFLAGS<imp-use,kill>
2400B	BB#17: derived from LLVM BB %if.then.18
	    Predecessors according to CFG: BB#16
2416B		CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%path.addr]
2432B		JE_1 <BB#19>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#19 BB#18
> CMP64mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%path.addr]
> JE_1 <BB#19>, %EFLAGS<imp-use,kill>
2448B	BB#18: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#17
2464B		%vreg49<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%path.addr] GR64:%vreg49
2480B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2544B		%ESI<def,dead> = MOV32ri64 <ga:@bzlib__str_9_>, %RSI<imp-def>
2552B		%RDI<def> = COPY %vreg49<kill>; GR64:%vreg49
2560B		CALL64pcrel32 <ga:@strcmp>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %RSP<imp-def>, %EAX<imp-def>
2576B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2592B		%vreg44<def> = COPY %EAX; GR32:%vreg44
2624B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2640B		STACKMAP 4, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, 0, <fi#15>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack9](align=1) LD8[FixedStack15](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)
2656B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2672B		CMP32ri8 %vreg44<kill>, 0, %EFLAGS<imp-def>; GR32:%vreg44
2688B		JNE_1 <BB#23>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#23 BB#19
> %RDI<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%path.addr]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %ESI<def,dead> = MOV32ri64 <ga:@bzlib__str_9_>, %RSI<imp-def>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@strcmp>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %RSP<imp-def>, %EAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def> = COPY %EAX
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 4, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#9>, 0, 0, <fi#15>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack9](align=1) LD8[FixedStack15](align=4) LD8[FixedStack1] LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> CMP32ri8 %EAX<kill>, 0, %EFLAGS<imp-def>
> JNE_1 <BB#23>, %EFLAGS<imp-use,kill>
2704B	BB#19: derived from LLVM BB %if.then.24
	    Predecessors according to CFG: BB#17 BB#18
2720B		CMP32mi8 <fi#8>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%writing]
2736B		JE_1 <BB#21>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#21 BB#20
> CMP32mi8 <fi#8>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%writing]
> JE_1 <BB#21>, %EFLAGS<imp-use,kill>
2752B	BB#20: derived from LLVM BB %cond.true.26
	    Predecessors according to CFG: BB#19
2768B		%vreg136<def> = MOV64rm %noreg, 1, %noreg, <ga:@stdout>, %noreg; mem:LD8[@stdout] GR64:%vreg136
2800B		JMP_1 <BB#22>
	    Successors according to CFG: BB#22
> %RAX<def> = MOV64rm %noreg, 1, %noreg, <ga:@stdout>, %noreg; mem:LD8[@stdout]
> JMP_1 <BB#22>
2816B	BB#21: derived from LLVM BB %cond.false.27
	    Predecessors according to CFG: BB#19
2832B		%vreg136<def> = MOV64rm %noreg, 1, %noreg, <ga:@stdin>, %noreg; mem:LD8[@stdin] GR64:%vreg136
	    Successors according to CFG: BB#22
> %RAX<def> = MOV64rm %noreg, 1, %noreg, <ga:@stdin>, %noreg; mem:LD8[@stdin]
2864B	BB#22: derived from LLVM BB %cond.end
	    Live Ins: %RAX
	    Predecessors according to CFG: BB#21 BB#20
2896B		MOV64mr <fi#10>, 1, %noreg, 0, %noreg, %vreg136<kill>; mem:ST8[%fp] GR64:%vreg136
2912B		JMP_1 <BB#24>
	    Successors according to CFG: BB#24
> MOV64mr <fi#10>, 1, %noreg, 0, %noreg, %RAX<kill>; mem:ST8[%fp]
> JMP_1 <BB#24>
2928B	BB#23: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#18
2944B		%vreg54<def> = LEA64r <fi#9>, 1, %noreg, 0, %noreg; GR64:%vreg54
2960B		%vreg55<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%path.addr] GR64:%vreg55
2976B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
2992B		%RDI<def> = COPY %vreg55<kill>; GR64:%vreg55
3008B		%RSI<def> = COPY %vreg54<kill>; GR64:%vreg54
3024B		CALL64pcrel32 <ga:@fopen>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %RAX<imp-def>
3040B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3056B		%vreg53<def> = COPY %RAX; GR64:%vreg53
3072B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3088B		STACKMAP 5, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#15>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack15](align=4) LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)
3104B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3120B		MOV64mr <fi#10>, 1, %noreg, 0, %noreg, %vreg53<kill>; mem:ST8[%fp] GR64:%vreg53
	    Successors according to CFG: BB#24
> %RSI<def> = LEA64r <fi#9>, 1, %noreg, 0, %noreg
> %RDI<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%path.addr]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@fopen>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %RAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RAX<def> = COPY %RAX
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 5, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#15>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack15](align=4) LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV64mr <fi#10>, 1, %noreg, 0, %noreg, %RAX<kill>; mem:ST8[%fp]
3136B	BB#24: derived from LLVM BB %if.end.31
	    Predecessors according to CFG: BB#23 BB#22
3152B		JMP_1 <BB#26>
	    Successors according to CFG: BB#26
> JMP_1 <BB#26>
3168B	BB#25: derived from LLVM BB %if.else.32
	    Predecessors according to CFG: BB#16
3184B		%vreg41<def> = LEA64r <fi#9>, 1, %noreg, 0, %noreg; GR64:%vreg41
3200B		%vreg42<def> = MOV32rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD4[%fd.addr] GR32:%vreg42
3216B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3232B		%EDI<def> = COPY %vreg42<kill>; GR32:%vreg42
3248B		%RSI<def> = COPY %vreg41<kill>; GR64:%vreg41
3264B		CALL64pcrel32 <ga:@fdopen>, <regmask>, %RSP<imp-use>, %EDI<imp-use>, %RSI<imp-use>, %RAX<imp-def>
3280B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3296B		%vreg40<def> = COPY %RAX; GR64:%vreg40
3312B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3328B		STACKMAP 6, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#15>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack15](align=4) LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)
3344B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3360B		MOV64mr <fi#10>, 1, %noreg, 0, %noreg, %vreg40<kill>; mem:ST8[%fp] GR64:%vreg40
	    Successors according to CFG: BB#26
> %RSI<def> = LEA64r <fi#9>, 1, %noreg, 0, %noreg
> %EDI<def> = MOV32rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD4[%fd.addr]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EDI<def> = COPY %EDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@fdopen>, <regmask>, %RSP<imp-use>, %EDI<imp-use>, %RSI<imp-use>, %RAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RAX<def> = COPY %RAX
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 6, 0, 0, <fi#7>, 0, 0, <fi#5>, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#15>, 0, 0, <fi#0>, 0, 0, <fi#14>, 0, 0, <fi#6>, 0, 0, <fi#12>, 0, 0, <fi#13>, 0, 0, <fi#8>, 0, ...; mem:LD8[FixedStack7](align=4) LD8[FixedStack5](align=4) LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack15](align=4) LD8[FixedStack0] LD8[FixedStack14](align=4) LD8[FixedStack6](align=16) LD8[FixedStack12](align=4) LD8[FixedStack13](align=4) LD8[FixedStack8](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV64mr <fi#10>, 1, %noreg, 0, %noreg, %RAX<kill>; mem:ST8[%fp]
3376B	BB#26: derived from LLVM BB %if.end.35
	    Predecessors according to CFG: BB#25 BB#24
3392B		CMP64mi8 <fi#10>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%fp]
3408B		JNE_1 <BB#28>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#28 BB#27
> CMP64mi8 <fi#10>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%fp]
> JNE_1 <BB#28>, %EFLAGS<imp-use,kill>
3424B	BB#27: derived from LLVM BB %if.then.38
	    Predecessors according to CFG: BB#26
3440B		MOV64mi32 <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST8[%retval]
3456B		JMP_1 <BB#41>
	    Successors according to CFG: BB#41
> MOV64mi32 <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST8[%retval]
> JMP_1 <BB#41>
3472B	BB#28: derived from LLVM BB %if.end.39
	    Predecessors according to CFG: BB#26
3488B		CMP32mi8 <fi#8>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%writing]
3504B		JE_1 <BB#34>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#34 BB#29
> CMP32mi8 <fi#8>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%writing]
> JE_1 <BB#34>, %EFLAGS<imp-use,kill>
3520B	BB#29: derived from LLVM BB %if.then.41
	    Predecessors according to CFG: BB#28
3536B		CMP32mi8 <fi#7>, 1, %noreg, 0, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%blockSize100k]
3552B		JGE_1 <BB#31>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#31 BB#30
> CMP32mi8 <fi#7>, 1, %noreg, 0, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%blockSize100k]
> JGE_1 <BB#31>, %EFLAGS<imp-use,kill>
3568B	BB#30: derived from LLVM BB %if.then.44
	    Predecessors according to CFG: BB#29
3584B		MOV32mi <fi#7>, 1, %noreg, 0, %noreg, 1; mem:ST4[%blockSize100k]
	    Successors according to CFG: BB#31
> MOV32mi <fi#7>, 1, %noreg, 0, %noreg, 1; mem:ST4[%blockSize100k]
3600B	BB#31: derived from LLVM BB %if.end.45
	    Predecessors according to CFG: BB#29 BB#30
3616B		CMP32mi8 <fi#7>, 1, %noreg, 0, %noreg, 9, %EFLAGS<imp-def>; mem:LD4[%blockSize100k]
3632B		JLE_1 <BB#33>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#33 BB#32
> CMP32mi8 <fi#7>, 1, %noreg, 0, %noreg, 9, %EFLAGS<imp-def>; mem:LD4[%blockSize100k]
> JLE_1 <BB#33>, %EFLAGS<imp-use,kill>
3648B	BB#32: derived from LLVM BB %if.then.48
	    Predecessors according to CFG: BB#31
3664B		MOV32mi <fi#7>, 1, %noreg, 0, %noreg, 9; mem:ST4[%blockSize100k]
	    Successors according to CFG: BB#33
> MOV32mi <fi#7>, 1, %noreg, 0, %noreg, 9; mem:ST4[%blockSize100k]
3680B	BB#33: derived from LLVM BB %if.end.49
	    Predecessors according to CFG: BB#31 BB#32
3696B		%vreg77<def> = LEA64r <fi#5>, 1, %noreg, 0, %noreg; GR64:%vreg77
3712B		%vreg86<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%fp] GR64:%vreg86
3728B		%vreg85<def> = MOV32rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD4[%blockSize100k] GR32:%vreg85
3744B		%vreg84<def> = MOV32rm <fi#12>, 1, %noreg, 0, %noreg; mem:LD4[%verbosity] GR32:%vreg84
3760B		%vreg83<def> = MOV32rm <fi#13>, 1, %noreg, 0, %noreg; mem:LD4[%workFactor] GR32:%vreg83
3776B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3792B		%RDI<def> = COPY %vreg77<kill>; GR64:%vreg77
3808B		%RSI<def> = COPY %vreg86<kill>; GR64:%vreg86
3824B		%EDX<def> = COPY %vreg85<kill>; GR32:%vreg85
3840B		%ECX<def> = COPY %vreg84<kill>; GR32:%vreg84
3856B		%R8D<def> = COPY %vreg83<kill>; GR32:%vreg83
3872B		CALL64pcrel32 <ga:@BZ2_bzWriteOpen>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %EDX<imp-use>, %ECX<imp-use>, %R8D<imp-use>, %RAX<imp-def>
3888B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3904B		%vreg82<def> = COPY %RAX; GR64:%vreg82
3920B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3936B		STACKMAP 7, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack0]
3952B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3968B		MOV64mr <fi#11>, 1, %noreg, 0, %noreg, %vreg82<kill>; mem:ST8[%bzfp] GR64:%vreg82
3984B		JMP_1 <BB#35>
	    Successors according to CFG: BB#35
> %RDI<def> = LEA64r <fi#5>, 1, %noreg, 0, %noreg
> %RSI<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%fp]
> %EDX<def> = MOV32rm <fi#7>, 1, %noreg, 0, %noreg; mem:LD4[%blockSize100k]
> %ECX<def> = MOV32rm <fi#12>, 1, %noreg, 0, %noreg; mem:LD4[%verbosity]
> %R8D<def> = MOV32rm <fi#13>, 1, %noreg, 0, %noreg; mem:LD4[%workFactor]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> %EDX<def> = COPY %EDX<kill>
Deleting identity copy.
> %ECX<def> = COPY %ECX<kill>
Deleting identity copy.
> %R8D<def> = COPY %R8D<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@BZ2_bzWriteOpen>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %EDX<imp-use>, %ECX<imp-use>, %R8D<imp-use>, %RAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RAX<def> = COPY %RAX
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 7, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack0]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV64mr <fi#11>, 1, %noreg, 0, %noreg, %RAX<kill>; mem:ST8[%bzfp]
> JMP_1 <BB#35>
4000B	BB#34: derived from LLVM BB %if.else.51
	    Predecessors according to CFG: BB#28
4016B		%vreg62<def> = LEA64r <fi#5>, 1, %noreg, 0, %noreg; GR64:%vreg62
4032B		%vreg70<def> = LEA64r <fi#6>, 1, %noreg, 0, %noreg; GR64:%vreg70
4048B		%vreg73<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%fp] GR64:%vreg73
4064B		%vreg72<def> = MOV32rm <fi#12>, 1, %noreg, 0, %noreg; mem:LD4[%verbosity] GR32:%vreg72
4080B		%vreg71<def> = MOV32rm <fi#14>, 1, %noreg, 0, %noreg; mem:LD4[%smallMode] GR32:%vreg71
4096B		%vreg69<def> = MOV32rm <fi#15>, 1, %noreg, 0, %noreg; mem:LD4[%nUnused] GR32:%vreg69
4112B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4128B		%RDI<def> = COPY %vreg62<kill>; GR64:%vreg62
4144B		%RSI<def> = COPY %vreg73<kill>; GR64:%vreg73
4160B		%EDX<def> = COPY %vreg72<kill>; GR32:%vreg72
4176B		%ECX<def> = COPY %vreg71<kill>; GR32:%vreg71
4192B		%R8<def> = COPY %vreg70<kill>; GR64:%vreg70
4208B		%R9D<def> = COPY %vreg69<kill>; GR32:%vreg69
4224B		CALL64pcrel32 <ga:@BZ2_bzReadOpen>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %EDX<imp-use>, %ECX<imp-use>, %R8<imp-use>, %R9D<imp-use>, %RAX<imp-def>
4240B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4256B		%vreg68<def> = COPY %RAX; GR64:%vreg68
4272B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4288B		STACKMAP 8, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack0]
4304B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4320B		MOV64mr <fi#11>, 1, %noreg, 0, %noreg, %vreg68<kill>; mem:ST8[%bzfp] GR64:%vreg68
	    Successors according to CFG: BB#35
> %RDI<def> = LEA64r <fi#5>, 1, %noreg, 0, %noreg
> %R8<def> = LEA64r <fi#6>, 1, %noreg, 0, %noreg
> %RSI<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%fp]
> %EDX<def> = MOV32rm <fi#12>, 1, %noreg, 0, %noreg; mem:LD4[%verbosity]
> %ECX<def> = MOV32rm <fi#14>, 1, %noreg, 0, %noreg; mem:LD4[%smallMode]
> %R9D<def> = MOV32rm <fi#15>, 1, %noreg, 0, %noreg; mem:LD4[%nUnused]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> %EDX<def> = COPY %EDX<kill>
Deleting identity copy.
> %ECX<def> = COPY %ECX<kill>
Deleting identity copy.
> %R8<def> = COPY %R8<kill>
Deleting identity copy.
> %R9D<def> = COPY %R9D<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@BZ2_bzReadOpen>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %EDX<imp-use>, %ECX<imp-use>, %R8<imp-use>, %R9D<imp-use>, %RAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RAX<def> = COPY %RAX
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 8, 0, 0, <fi#11>, 0, 0, <fi#10>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack11] LD8[FixedStack10] LD8[FixedStack0]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV64mr <fi#11>, 1, %noreg, 0, %noreg, %RAX<kill>; mem:ST8[%bzfp]
4336B	BB#35: derived from LLVM BB %if.end.54
	    Predecessors according to CFG: BB#34 BB#33
4352B		CMP64mi8 <fi#11>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzfp]
4368B		JNE_1 <BB#40>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#40 BB#36
> CMP64mi8 <fi#11>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%bzfp]
> JNE_1 <BB#40>, %EFLAGS<imp-use,kill>
4384B	BB#36: derived from LLVM BB %if.then.57
	    Predecessors according to CFG: BB#35
4400B		%vreg92<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%fp] GR64:%vreg92
4416B		CMP64rm %vreg92<kill>, %noreg, 1, %noreg, <ga:@stdin>, %noreg, %EFLAGS<imp-def>; mem:LD8[@stdin] GR64:%vreg92
4432B		JE_1 <BB#39>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#39 BB#37
> %RAX<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%fp]
> CMP64rm %RAX<kill>, %noreg, 1, %noreg, <ga:@stdin>, %noreg, %EFLAGS<imp-def>; mem:LD8[@stdin]
> JE_1 <BB#39>, %EFLAGS<imp-use,kill>
4448B	BB#37: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#36
4464B		%vreg95<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%fp] GR64:%vreg95
4480B		CMP64rm %vreg95<kill>, %noreg, 1, %noreg, <ga:@stdout>, %noreg, %EFLAGS<imp-def>; mem:LD8[@stdout] GR64:%vreg95
4496B		JE_1 <BB#39>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#39 BB#38
> %RAX<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%fp]
> CMP64rm %RAX<kill>, %noreg, 1, %noreg, <ga:@stdout>, %noreg, %EFLAGS<imp-def>; mem:LD8[@stdout]
> JE_1 <BB#39>, %EFLAGS<imp-use,kill>
4512B	BB#38: derived from LLVM BB %if.then.62
	    Predecessors according to CFG: BB#37
4528B		%vreg98<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%fp] GR64:%vreg98
4544B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4560B		%RDI<def> = COPY %vreg98<kill>; GR64:%vreg98
4576B		CALL64pcrel32 <ga:@fclose>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
4592B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4608B		%vreg97<def,dead> = COPY %EAX; GR32:%vreg97
4624B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4640B		STACKMAP 9, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0]
4656B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#39
> %RDI<def> = MOV64rm <fi#10>, 1, %noreg, 0, %noreg; mem:LD8[%fp]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@fclose>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def,dead> = COPY %EAX
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 9, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4672B	BB#39: derived from LLVM BB %if.end.64
	    Predecessors according to CFG: BB#36 BB#37 BB#38
4688B		MOV64mi32 <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST8[%retval]
4704B		JMP_1 <BB#41>
	    Successors according to CFG: BB#41
> MOV64mi32 <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST8[%retval]
> JMP_1 <BB#41>
4720B	BB#40: derived from LLVM BB %if.end.65
	    Predecessors according to CFG: BB#35
4736B		%vreg89<def> = MOV64rm <fi#11>, 1, %noreg, 0, %noreg; mem:LD8[%bzfp] GR64:%vreg89
4752B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg89<kill>; mem:ST8[%retval] GR64:%vreg89
	    Successors according to CFG: BB#41
> %RAX<def> = MOV64rm <fi#11>, 1, %noreg, 0, %noreg; mem:LD8[%bzfp]
> MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %RAX<kill>; mem:ST8[%retval]
4768B	BB#41: derived from LLVM BB %return
	    Predecessors according to CFG: BB#40 BB#39 BB#27 BB#1
4784B		%vreg134<def> = MOV64ri <ga:@bzopen_or_bzdopen>; GR64:%vreg134
4816B		%vreg135<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg135
4832B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4848B		%RDI<def> = COPY %vreg134<kill>; GR64:%vreg134
4864B		%RSI<def> = COPY %vreg135<kill>; GR64:%vreg135
4880B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
4896B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4912B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4928B		STACKMAP 10, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0]
4944B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4960B		%vreg132<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%retval] GR64:%vreg132
4976B		%RAX<def> = COPY %vreg132<kill>; GR64:%vreg132
4992B		RETQ %RAX<imp-use>
> %RDI<def> = MOV64ri <ga:@bzopen_or_bzdopen>
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 10, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%retval]
> %RAX<def> = COPY %RAX<kill>
Deleting identity copy.
> RETQ %RAX<imp-use>
Computing live-in reg-units in ABI blocks.
0B	BB#0 DIL#0 SIL#0
Created 2 new intervals.
********** INTERVALS **********
DIL [0B,32r:0)[144r,176r:1)[384r,448r:2)[608r,640r:3)  0@0B-phi 1@144r 2@384r 3@608r
SIL [0B,16r:0)[160r,176r:2)[400r,448r:1)[624r,640r:3)  0@0B-phi 1@400r 2@160r 3@624r
%vreg0 [32r,48r:0)  0@32r
%vreg1 [48r,304r:0)  0@48r
%vreg2 [16r,64r:0)  0@16r
%vreg3 [64r,320r:0)  0@64r
%vreg5 [496r,512r:0)  0@496r
%vreg6 [512r,608r:0)  0@512r
%vreg7 [576r,624r:0)  0@576r
%vreg8 [208r,224r:0)  0@208r
%vreg9 [224r,384r:0)  0@224r
%vreg12 [240r,432r:0)  0@240r
%vreg13 [480r,720r:0)  0@480r
%vreg14 [352r,416r:0)  0@352r
%vreg15 [336r,400r:0)  0@336r
%vreg16 [80r,96r:0)  0@80r
%vreg17 [96r,144r:0)  0@96r
%vreg18 [112r,160r:0)  0@112r
RegMasks: 176r 448r 640r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzdopen: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=4, align=4, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
Function Live Ins: %EDI in %vreg0, %RSI in %vreg2

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %EDI %RSI
16B		%vreg2<def> = COPY %RSI; GR64:%vreg2
32B		%vreg0<def> = COPY %EDI; GR32:%vreg0
48B		%vreg1<def> = COPY %vreg0; GR32:%vreg1,%vreg0
64B		%vreg3<def> = COPY %vreg2; GR64:%vreg3,%vreg2
80B		%vreg16<def> = MOV64ri <ga:@BZ2_bzdopen>; GR64:%vreg16
96B		%vreg17<def> = COPY %vreg16; GR64:%vreg17,%vreg16
112B		%vreg18<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg18
128B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
144B		%RDI<def> = COPY %vreg17; GR64:%vreg17
160B		%RSI<def> = COPY %vreg18; GR64:%vreg18
176B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
192B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
208B		%vreg8<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg8
224B		%vreg9<def> = SUBREG_TO_REG 0, %vreg8, 4; GR64:%vreg9 GR32:%vreg8
240B		%vreg12<def> = MOV32ri 1; GR32:%vreg12
256B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
272B		STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, %vreg3, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack1] GR32:%vreg1 GR64:%vreg3
288B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
304B		MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1; mem:ST4[%fd.addr] GR32:%vreg1
320B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg3; mem:ST8[%mode.addr] GR64:%vreg3
336B		%vreg15<def> = MOV32rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD4[%fd.addr] GR32:%vreg15
352B		%vreg14<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%mode.addr] GR64:%vreg14
368B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
384B		%RDI<def> = COPY %vreg9; GR64:%vreg9
400B		%ESI<def> = COPY %vreg15; GR32:%vreg15
416B		%RDX<def> = COPY %vreg14; GR64:%vreg14
432B		%ECX<def> = COPY %vreg12; GR32:%vreg12
448B		CALL64pcrel32 <ga:@bzopen_or_bzdopen>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %RDX<imp-use,kill>, %ECX<imp-use,kill>, %RAX<imp-def>
464B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
480B		%vreg13<def> = COPY %RAX<kill>; GR64:%vreg13
496B		%vreg5<def> = MOV64ri <ga:@BZ2_bzdopen>; GR64:%vreg5
512B		%vreg6<def> = COPY %vreg5; GR64:%vreg6,%vreg5
528B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
544B		STACKMAP 1, 0, ...
560B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
576B		%vreg7<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg7
592B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
608B		%RDI<def> = COPY %vreg6; GR64:%vreg6
624B		%RSI<def> = COPY %vreg7; GR64:%vreg7
640B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
656B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
672B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
688B		STACKMAP 2, 0, %vreg13, ...; GR64:%vreg13
704B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
720B		%RAX<def> = COPY %vreg13; GR64:%vreg13
736B		RETQ %RAX<imp-use,kill>

# End machine code for function BZ2_bzdopen.

********** SIMPLE REGISTER COALESCING **********
********** Function: BZ2_bzdopen
********** JOINING INTERVALS ***********
entry:
16B	%vreg2<def> = COPY %RSI; GR64:%vreg2
	Considering merging %vreg2 with %RSI
	Can only merge into reserved registers.
32B	%vreg0<def> = COPY %EDI; GR32:%vreg0
	Considering merging %vreg0 with %EDI
	Can only merge into reserved registers.
144B	%RDI<def> = COPY %vreg17; GR64:%vreg17
	Considering merging %vreg17 with %RDI
	Can only merge into reserved registers.
160B	%RSI<def> = COPY %vreg18; GR64:%vreg18
	Considering merging %vreg18 with %RSI
	Can only merge into reserved registers.
224B	%vreg9<def> = SUBREG_TO_REG 0, %vreg8, 4; GR64:%vreg9 GR32:%vreg8
	Considering merging to GR64_with_sub_8bit with %vreg8 in %vreg9:sub_32bit
		RHS = %vreg8 [208r,224r:0)  0@208r
		LHS = %vreg9 [224r,384r:0)  0@224r
		merge %vreg9:0@224r into %vreg8:0@208r --> @208r
		erased:	224r	%vreg9<def> = SUBREG_TO_REG 0, %vreg8, 4; GR64:%vreg9 GR32:%vreg8
		updated: 208B	%vreg9:sub_32bit<def,read-undef> = MOV32r0 %EFLAGS<imp-def,dead>; GR64_with_sub_8bit:%vreg9
	Success: %vreg8:sub_32bit -> %vreg9
	Result = %vreg9 [208r,384r:0)  0@208r
384B	%RDI<def> = COPY %vreg9; GR64_with_sub_8bit:%vreg9
	Considering merging %vreg9 with %RDI
	Can only merge into reserved registers.
Remat: %EDI<def,dead> = MOV32r0 %EFLAGS<imp-def,dead>, %RDI<imp-def>
Shrink: %vreg9 [208r,384r:0)  0@208r
All defs dead: 208r	%vreg9:sub_32bit<def,read-undef,dead> = MOV32r0 %EFLAGS<imp-def,dead>; GR64_with_sub_8bit:%vreg9
Shrunk: %vreg9 [208r,208d:0)  0@208r
Deleting dead def 208r	%vreg9:sub_32bit<def,read-undef,dead> = MOV32r0 %EFLAGS<imp-def,dead>; GR64_with_sub_8bit:%vreg9
400B	%ESI<def> = COPY %vreg15; GR32:%vreg15
	Considering merging %vreg15 with %ESI
	Can only merge into reserved registers.
416B	%RDX<def> = COPY %vreg14; GR64:%vreg14
	Considering merging %vreg14 with %RDX
	Can only merge into reserved registers.
432B	%ECX<def> = COPY %vreg12; GR32:%vreg12
	Considering merging %vreg12 with %ECX
	Can only merge into reserved registers.
Remat: %ECX<def> = MOV32ri 1
Shrink: %vreg12 [240r,432r:0)  0@240r
All defs dead: 240r	%vreg12<def,dead> = MOV32ri 1; GR32:%vreg12
Shrunk: %vreg12 [240r,240d:0)  0@240r
Deleting dead def 240r	%vreg12<def,dead> = MOV32ri 1; GR32:%vreg12
480B	%vreg13<def> = COPY %RAX<kill>; GR64:%vreg13
	Considering merging %vreg13 with %RAX
	Can only merge into reserved registers.
608B	%RDI<def> = COPY %vreg6; GR64:%vreg6
	Considering merging %vreg6 with %RDI
	Can only merge into reserved registers.
624B	%RSI<def> = COPY %vreg7; GR64:%vreg7
	Considering merging %vreg7 with %RSI
	Can only merge into reserved registers.
720B	%RAX<def> = COPY %vreg13; GR64:%vreg13
	Considering merging %vreg13 with %RAX
	Can only merge into reserved registers.
48B	%vreg1<def> = COPY %vreg0; GR32:%vreg1,%vreg0
	Considering merging to GR32 with %vreg0 in %vreg1
		RHS = %vreg0 [32r,48r:0)  0@32r
		LHS = %vreg1 [48r,304r:0)  0@48r
		merge %vreg1:0@48r into %vreg0:0@32r --> @32r
		erased:	48r	%vreg1<def> = COPY %vreg0; GR32:%vreg1,%vreg0
		updated: 32B	%vreg1<def> = COPY %EDI; GR32:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [32r,304r:0)  0@32r
64B	%vreg3<def> = COPY %vreg2; GR64:%vreg3,%vreg2
	Considering merging to GR64 with %vreg2 in %vreg3
		RHS = %vreg2 [16r,64r:0)  0@16r
		LHS = %vreg3 [64r,320r:0)  0@64r
		merge %vreg3:0@64r into %vreg2:0@16r --> @16r
		erased:	64r	%vreg3<def> = COPY %vreg2; GR64:%vreg3,%vreg2
		updated: 16B	%vreg3<def> = COPY %RSI; GR64:%vreg3
	Success: %vreg2 -> %vreg3
	Result = %vreg3 [16r,320r:0)  0@16r
96B	%vreg17<def> = COPY %vreg16; GR64:%vreg17,%vreg16
	Considering merging to GR64 with %vreg16 in %vreg17
		RHS = %vreg16 [80r,96r:0)  0@80r
		LHS = %vreg17 [96r,144r:0)  0@96r
		merge %vreg17:0@96r into %vreg16:0@80r --> @80r
		erased:	96r	%vreg17<def> = COPY %vreg16; GR64:%vreg17,%vreg16
		updated: 80B	%vreg17<def> = MOV64ri <ga:@BZ2_bzdopen>; GR64:%vreg17
	Success: %vreg16 -> %vreg17
	Result = %vreg17 [80r,144r:0)  0@80r
512B	%vreg6<def> = COPY %vreg5; GR64:%vreg6,%vreg5
	Considering merging to GR64 with %vreg5 in %vreg6
		RHS = %vreg5 [496r,512r:0)  0@496r
		LHS = %vreg6 [512r,608r:0)  0@512r
		merge %vreg6:0@512r into %vreg5:0@496r --> @496r
		erased:	512r	%vreg6<def> = COPY %vreg5; GR64:%vreg6,%vreg5
		updated: 496B	%vreg6<def> = MOV64ri <ga:@BZ2_bzdopen>; GR64:%vreg6
	Success: %vreg5 -> %vreg6
	Result = %vreg6 [496r,608r:0)  0@496r
144B	%RDI<def> = COPY %vreg17; GR64:%vreg17
	Considering merging %vreg17 with %RDI
	Can only merge into reserved registers.
608B	%RDI<def> = COPY %vreg6; GR64:%vreg6
	Considering merging %vreg6 with %RDI
	Can only merge into reserved registers.
720B	%RAX<def> = COPY %vreg13; GR64:%vreg13
	Considering merging %vreg13 with %RAX
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
DIL [0B,32r:0)[144r,176r:1)[384r,448r:2)[608r,640r:3)  0@0B-phi 1@144r 2@384r 3@608r
SIL [0B,16r:0)[160r,176r:2)[400r,448r:1)[624r,640r:3)  0@0B-phi 1@400r 2@160r 3@624r
%vreg1 [32r,304r:0)  0@32r
%vreg3 [16r,320r:0)  0@16r
%vreg6 [496r,608r:0)  0@496r
%vreg7 [576r,624r:0)  0@576r
%vreg13 [480r,720r:0)  0@480r
%vreg14 [352r,416r:0)  0@352r
%vreg15 [336r,400r:0)  0@336r
%vreg17 [80r,144r:0)  0@80r
%vreg18 [112r,160r:0)  0@112r
RegMasks: 176r 448r 640r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzdopen: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=4, align=4, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
Function Live Ins: %EDI in %vreg0, %RSI in %vreg2

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %EDI %RSI
16B		%vreg3<def> = COPY %RSI; GR64:%vreg3
32B		%vreg1<def> = COPY %EDI; GR32:%vreg1
80B		%vreg17<def> = MOV64ri <ga:@BZ2_bzdopen>; GR64:%vreg17
112B		%vreg18<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg18
128B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
144B		%RDI<def> = COPY %vreg17; GR64:%vreg17
160B		%RSI<def> = COPY %vreg18; GR64:%vreg18
176B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
192B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
256B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
272B		STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, %vreg3, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack1] GR32:%vreg1 GR64:%vreg3
288B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
304B		MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1; mem:ST4[%fd.addr] GR32:%vreg1
320B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg3; mem:ST8[%mode.addr] GR64:%vreg3
336B		%vreg15<def> = MOV32rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD4[%fd.addr] GR32:%vreg15
352B		%vreg14<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%mode.addr] GR64:%vreg14
368B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
384B		%EDI<def,dead> = MOV32r0 %EFLAGS<imp-def,dead>, %RDI<imp-def>
400B		%ESI<def> = COPY %vreg15; GR32:%vreg15
416B		%RDX<def> = COPY %vreg14; GR64:%vreg14
432B		%ECX<def> = MOV32ri 1
448B		CALL64pcrel32 <ga:@bzopen_or_bzdopen>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %RDX<imp-use,kill>, %ECX<imp-use,kill>, %RAX<imp-def>
464B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
480B		%vreg13<def> = COPY %RAX<kill>; GR64:%vreg13
496B		%vreg6<def> = MOV64ri <ga:@BZ2_bzdopen>; GR64:%vreg6
528B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
544B		STACKMAP 1, 0, ...
560B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
576B		%vreg7<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg7
592B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
608B		%RDI<def> = COPY %vreg6; GR64:%vreg6
624B		%RSI<def> = COPY %vreg7; GR64:%vreg7
640B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
656B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
672B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
688B		STACKMAP 2, 0, %vreg13, ...; GR64:%vreg13
704B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
720B		%RAX<def> = COPY %vreg13; GR64:%vreg13
736B		RETQ %RAX<imp-use,kill>

# End machine code for function BZ2_bzdopen.

handleMove 416B -> 440B: %RDX<def> = COPY %vreg14; GR64:%vreg14
     DH:	[440r,448r:0)  0@440r
        -->	[440r,448r:0)  0@440r
     DL:	[440r,448r:0)  0@440r
        -->	[440r,448r:0)  0@440r
     %vreg14:	[352r,416r:0)  0@352r
        -->	[352r,440r:0)  0@352r
handleMove 400B -> 436B: %ESI<def> = COPY %vreg15; GR32:%vreg15
     SIL:	[0B,16r:0)[160r,176r:2)[400r,448r:1)[624r,640r:3)  0@0B-phi 1@400r 2@160r 3@624r
        -->	[0B,16r:0)[160r,176r:2)[436r,448r:1)[624r,640r:3)  0@0B-phi 1@436r 2@160r 3@624r
     %vreg15:	[336r,400r:0)  0@336r
        -->	[336r,436r:0)  0@336r
********** GREEDY REGISTER ALLOCATION **********
********** Function: BZ2_bzdopen
********** INTERVALS **********
DH [440r,448r:0)  0@440r
DIL [0B,32r:0)[144r,176r:1)[384r,448r:2)[608r,640r:3)  0@0B-phi 1@144r 2@384r 3@608r
DL [440r,448r:0)  0@440r
SIL [0B,16r:0)[160r,176r:2)[436r,448r:1)[624r,640r:3)  0@0B-phi 1@436r 2@160r 3@624r
%vreg1 [32r,304r:0)  0@32r
%vreg3 [16r,320r:0)  0@16r
%vreg6 [496r,608r:0)  0@496r
%vreg7 [576r,624r:0)  0@576r
%vreg13 [480r,720r:0)  0@480r
%vreg14 [352r,440r:0)  0@352r
%vreg15 [336r,436r:0)  0@336r
%vreg17 [80r,144r:0)  0@80r
%vreg18 [112r,160r:0)  0@112r
RegMasks: 176r 448r 640r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzdopen: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=4, align=4, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
Function Live Ins: %EDI in %vreg0, %RSI in %vreg2

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %EDI %RSI
16B		%vreg3<def> = COPY %RSI; GR64:%vreg3
32B		%vreg1<def> = COPY %EDI; GR32:%vreg1
80B		%vreg17<def> = MOV64ri <ga:@BZ2_bzdopen>; GR64:%vreg17
112B		%vreg18<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg18
128B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
144B		%RDI<def> = COPY %vreg17; GR64:%vreg17
160B		%RSI<def> = COPY %vreg18; GR64:%vreg18
176B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
192B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
256B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
272B		STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, %vreg3, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack1] GR32:%vreg1 GR64:%vreg3
288B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
304B		MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1; mem:ST4[%fd.addr] GR32:%vreg1
320B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg3; mem:ST8[%mode.addr] GR64:%vreg3
336B		%vreg15<def> = MOV32rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD4[%fd.addr] GR32:%vreg15
352B		%vreg14<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%mode.addr] GR64:%vreg14
368B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
384B		%EDI<def,dead> = MOV32r0 %EFLAGS<imp-def,dead>, %RDI<imp-def>
432B		%ECX<def> = MOV32ri 1
436B		%ESI<def> = COPY %vreg15; GR32:%vreg15
440B		%RDX<def> = COPY %vreg14; GR64:%vreg14
448B		CALL64pcrel32 <ga:@bzopen_or_bzdopen>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %RDX<imp-use>, %ECX<imp-use,kill>, %RAX<imp-def>
464B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
480B		%vreg13<def> = COPY %RAX<kill>; GR64:%vreg13
496B		%vreg6<def> = MOV64ri <ga:@BZ2_bzdopen>; GR64:%vreg6
528B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
544B		STACKMAP 1, 0, ...
560B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
576B		%vreg7<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg7
592B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
608B		%RDI<def> = COPY %vreg6; GR64:%vreg6
624B		%RSI<def> = COPY %vreg7; GR64:%vreg7
640B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
656B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
672B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
688B		STACKMAP 2, 0, %vreg13, ...; GR64:%vreg13
704B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
720B		%RAX<def> = COPY %vreg13; GR64:%vreg13
736B		RETQ %RAX<imp-use,kill>

# End machine code for function BZ2_bzdopen.


selectOrSplit GR64:%vreg3 [16r,320r:0)  0@16r w=4.303977e-03
hints: %RSI
missed hint %RSI
assigning %vreg3 to %RBX: BH [16r,320r:0)  0@16r BL [16r,320r:0)  0@16r

selectOrSplit GR32:%vreg1 [32r,304r:0)  0@32r w=4.508928e-03
hints: %EDI
missed hint %EDI
%R14D is available at cost 1
Only trying the first 10 regs.
should evict: %vreg3 [16r,320r:0)  0@16r w= 4.303977e-03
hints: %RSI
can reassign: %vreg3 [16r,320r:0)  0@16r from %EBX to %RSI
should evict: %vreg3 [16r,320r:0)  0@16r w= 4.303977e-03
hints: %RSI
can reassign: %vreg3 [16r,320r:0)  0@16r from %EBX to %RSI
evicting %EBX interference: Cascade 1
unassigning %vreg3 from %RBX: BH BL
assigning %vreg1 to %EBX: BH [32r,304r:0)  0@32r BL [32r,304r:0)  0@32r
queuing new interval: %vreg3 [16r,320r:0)  0@16r

selectOrSplit GR64:%vreg3 [16r,320r:0)  0@16r w=4.303977e-03
hints: %RSI
missed hint %RSI
%R14 is available at cost 1
Only trying the first 10 regs.
assigning %vreg3 to %R14: R14B [16r,320r:0)  0@16r

selectOrSplit GR64:%vreg17 [80r,144r:0)  0@80r w=2.176724e-03
hints: %RDI
assigning %vreg17 to %RDI: DIL [80r,144r:0)  0@80r

selectOrSplit GR64:%vreg18 [112r,160r:0)  0@112r w=4.508928e-03
hints: %RSI
assigning %vreg18 to %RSI: SIL [112r,160r:0)  0@112r

selectOrSplit GR32:%vreg15 [336r,436r:0)  0@336r w=4.040000e-03
hints: %ESI
assigning %vreg15 to %ESI: SIL [336r,436r:0)  0@336r

selectOrSplit GR64:%vreg14 [352r,440r:0)  0@352r w=4.139344e-03
hints: %RDX
assigning %vreg14 to %RDX: DH [352r,440r:0)  0@352r DL [352r,440r:0)  0@352r

selectOrSplit GR64:%vreg13 [480r,720r:0)  0@480r w=4.734375e-03
hints: %RAX
missed hint %RAX
assigning %vreg13 to %RBX: BH [480r,720r:0)  0@480r BL [480r,720r:0)  0@480r

selectOrSplit GR64:%vreg6 [496r,608r:0)  0@496r w=1.972656e-03
hints: %RDI
assigning %vreg6 to %RDI: DIL [496r,608r:0)  0@496r

selectOrSplit GR64:%vreg7 [576r,624r:0)  0@576r w=4.508928e-03
hints: %RSI
assigning %vreg7 to %RSI: SIL [576r,624r:0)  0@576r

********** STACK TRANSFORMATION METADATA **********
********** Function: BZ2_bzdopen
********** REGISTER MAP **********
[%vreg1 -> %EBX] GR32
[%vreg3 -> %R14] GR64
[%vreg6 -> %RDI] GR64
[%vreg7 -> %RSI] GR64
[%vreg13 -> %RBX] GR64
[%vreg14 -> %RDX] GR64
[%vreg15 -> %ESI] GR32
[%vreg17 -> %RDI] GR64
[%vreg18 -> %RSI] GR64


Stackmap 0:
  STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, %vreg3, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack1] GR32:%vreg1 GR64:%vreg3

i32 %fd: in register %EBX (vreg 1)
i32* %fd.addr: in stack slot 0 (size: 4)
i8* %mode: in register %R14 (vreg 3)
i8** %mode.addr: in stack slot 1 (size: 8)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, ...


Duplicate operand locations:


Stackmap 2:
  STACKMAP 2, 0, %vreg13, ...; GR64:%vreg13

i8* %call: in register %RBX (vreg 13)

Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, %vreg3, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack1] GR32:%vreg1 GR64:%vreg3
  -> Call instruction SlotIndex 176B, searching vregs 0 -> 19 and stack slots -1 -> 2

  STACKMAP 1, 0, ...
  -> Call instruction SlotIndex 448B, searching vregs 0 -> 19 and stack slots -1 -> 2

  STACKMAP 2, 0, %vreg13, ...; GR64:%vreg13
  -> Call instruction SlotIndex 640B, searching vregs 0 -> 19 and stack slots -1 -> 2

********** REWRITE VIRTUAL REGISTERS **********
********** Function: BZ2_bzdopen
********** REGISTER MAP **********
[%vreg1 -> %EBX] GR32
[%vreg3 -> %R14] GR64
[%vreg6 -> %RDI] GR64
[%vreg7 -> %RSI] GR64
[%vreg13 -> %RBX] GR64
[%vreg14 -> %RDX] GR64
[%vreg15 -> %ESI] GR32
[%vreg17 -> %RDI] GR64
[%vreg18 -> %RSI] GR64

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %EDI %RSI
16B		%vreg3<def> = COPY %RSI; GR64:%vreg3
32B		%vreg1<def> = COPY %EDI; GR32:%vreg1
80B		%vreg17<def> = MOV64ri <ga:@BZ2_bzdopen>; GR64:%vreg17
112B		%vreg18<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg18
128B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
144B		%RDI<def> = COPY %vreg17<kill>; GR64:%vreg17
160B		%RSI<def> = COPY %vreg18<kill>; GR64:%vreg18
176B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
192B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
256B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
272B		STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, %vreg3, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack1] GR32:%vreg1 GR64:%vreg3
288B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
304B		MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1<kill>; mem:ST4[%fd.addr] GR32:%vreg1
320B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg3<kill>; mem:ST8[%mode.addr] GR64:%vreg3
336B		%vreg15<def> = MOV32rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD4[%fd.addr] GR32:%vreg15
352B		%vreg14<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%mode.addr] GR64:%vreg14
368B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
384B		%EDI<def,dead> = MOV32r0 %EFLAGS<imp-def,dead>, %RDI<imp-def>
432B		%ECX<def> = MOV32ri 1
436B		%ESI<def> = COPY %vreg15<kill>; GR32:%vreg15
440B		%RDX<def> = COPY %vreg14<kill>; GR64:%vreg14
448B		CALL64pcrel32 <ga:@bzopen_or_bzdopen>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %RDX<imp-use>, %ECX<imp-use,kill>, %RAX<imp-def>
464B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
480B		%vreg13<def> = COPY %RAX<kill>; GR64:%vreg13
496B		%vreg6<def> = MOV64ri <ga:@BZ2_bzdopen>; GR64:%vreg6
528B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
544B		STACKMAP 1, 0, ...
560B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
576B		%vreg7<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg7
592B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
608B		%RDI<def> = COPY %vreg6<kill>; GR64:%vreg6
624B		%RSI<def> = COPY %vreg7<kill>; GR64:%vreg7
640B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
656B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
672B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
688B		STACKMAP 2, 0, %vreg13, ...; GR64:%vreg13
704B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
720B		%RAX<def> = COPY %vreg13<kill>; GR64:%vreg13
736B		RETQ %RAX<imp-use,kill>
> %R14<def> = COPY %RSI
> %EBX<def> = COPY %EDI
> %RDI<def> = MOV64ri <ga:@BZ2_bzdopen>
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 0, 0, %EBX, 0, <fi#0>, 0, %R14, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0](align=4) LD8[FixedStack1]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %EBX<kill>; mem:ST4[%fd.addr]
> MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %R14<kill>; mem:ST8[%mode.addr]
> %ESI<def> = MOV32rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD4[%fd.addr]
> %RDX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%mode.addr]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EDI<def,dead> = MOV32r0 %EFLAGS<imp-def,dead>, %RDI<imp-def>
> %ECX<def> = MOV32ri 1
> %ESI<def> = COPY %ESI<kill>
Deleting identity copy.
> %RDX<def> = COPY %RDX<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@bzopen_or_bzdopen>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %ESI<imp-use>, %RDX<imp-use>, %ECX<imp-use,kill>, %RAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RBX<def> = COPY %RAX<kill>
> %RDI<def> = MOV64ri <ga:@BZ2_bzdopen>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 1, 0, ...
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 2, 0, %RBX, ...
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RAX<def> = COPY %RBX<kill>
> RETQ %RAX<imp-use,kill>
Computing live-in reg-units in ABI blocks.
0B	BB#0 DIL#0 SIL#0 DH#0 DL#0
Created 4 new intervals.
********** INTERVALS **********
DH [0B,16r:0)[560r,592r:1)  0@0B-phi 1@560r
DIL [0B,48r:0)[176r,208r:3)[528r,592r:2)[960r,992r:1)  0@0B-phi 1@960r 2@528r 3@176r
DL [0B,16r:0)[560r,592r:1)  0@0B-phi 1@560r
SIL [0B,32r:0)[192r,208r:3)[544r,592r:2)[976r,992r:1)  0@0B-phi 1@976r 2@544r 3@192r
%vreg0 [48r,64r:0)  0@48r
%vreg1 [64r,288r:0)  0@64r
%vreg2 [32r,80r:0)  0@32r
%vreg3 [80r,304r:0)  0@80r
%vreg4 [16r,96r:0)  0@16r
%vreg5 [96r,320r:0)  0@96r
%vreg8 [336r,352r:0)  0@336r
%vreg9 [112r,128r:0)  0@112r
%vreg10 [128r,176r:0)  0@128r
%vreg11 [144r,192r:0)  0@144r
%vreg14 [448r,528r:0)  0@448r
%vreg18 [624r,688r:0)  0@624r
%vreg19 [496r,576r:0)  0@496r
%vreg20 [480r,560r:0)  0@480r
%vreg21 [464r,544r:0)  0@464r
%vreg24 [800r,816r:0)  0@800r
%vreg26 [1072r,1088r:0)  0@1072r
%vreg27 [896r,912r:0)  0@896r
%vreg28 [912r,960r:0)  0@912r
%vreg29 [928r,976r:0)  0@928r
RegMasks: 208r 592r 992r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzread: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=4, align=4, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=8, align=8, at location [SP+8]
  fi#3: size=4, align=4, at location [SP+8]
  fi#4: size=4, align=4, at location [SP+8]
  fi#5: size=4, align=4, at location [SP+8]
Function Live Ins: %RDI in %vreg0, %RSI in %vreg2, %EDX in %vreg4

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI %RSI %EDX
16B		%vreg4<def> = COPY %EDX; GR32:%vreg4
32B		%vreg2<def> = COPY %RSI; GR64:%vreg2
48B		%vreg0<def> = COPY %RDI; GR64:%vreg0
64B		%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
80B		%vreg3<def> = COPY %vreg2; GR64:%vreg3,%vreg2
96B		%vreg5<def> = COPY %vreg4; GR32:%vreg5,%vreg4
112B		%vreg9<def> = MOV64ri <ga:@BZ2_bzread>; GR64:%vreg9
128B		%vreg10<def> = COPY %vreg9; GR64:%vreg10,%vreg9
144B		%vreg11<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg11
160B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		%RDI<def> = COPY %vreg10; GR64:%vreg10
192B		%RSI<def> = COPY %vreg11; GR64:%vreg11
208B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
224B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
240B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
256B		STACKMAP 0, 0, %vreg1, 0, <fi#1>, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#4>, 0, %vreg5, 0, <fi#3>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack4](align=4) LD8[FixedStack3](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4) GR64:%vreg1,%vreg3 GR32:%vreg5
272B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
288B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%b.addr] GR64:%vreg1
304B		MOV64mr <fi#2>, 1, %noreg, 0, %noreg, %vreg3; mem:ST8[%buf.addr] GR64:%vreg3
320B		MOV32mr <fi#3>, 1, %noreg, 0, %noreg, %vreg5; mem:ST4[%len.addr] GR32:%vreg5
336B		%vreg8<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr] GR64:%vreg8
352B		CMP32mi8 %vreg8, 1, %noreg, 5096, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%lastErr] GR64:%vreg8
368B		JNE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

384B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
400B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
416B		JMP_1 <BB#6>
	    Successors according to CFG: BB#6

432B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0
448B		%vreg14<def> = LEA64r <fi#4>, 1, %noreg, 0, %noreg; GR64:%vreg14
464B		%vreg21<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr] GR64:%vreg21
480B		%vreg20<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%buf.addr] GR64:%vreg20
496B		%vreg19<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%len.addr] GR32:%vreg19
512B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
528B		%RDI<def> = COPY %vreg14; GR64:%vreg14
544B		%RSI<def> = COPY %vreg21; GR64:%vreg21
560B		%RDX<def> = COPY %vreg20; GR64:%vreg20
576B		%ECX<def> = COPY %vreg19; GR32:%vreg19
592B		CALL64pcrel32 <ga:@BZ2_bzRead>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %RDX<imp-use>, %ECX<imp-use,kill>, %EAX<imp-def>
608B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
624B		%vreg18<def> = COPY %EAX<kill>; GR32:%vreg18
640B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
656B		STACKMAP 1, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4)
672B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
688B		MOV32mr <fi#5>, 1, %noreg, 0, %noreg, %vreg18; mem:ST4[%nread] GR32:%vreg18
704B		CMP32mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%bzerr]
720B		JE_1 <BB#4>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#4 BB#3

736B	BB#3: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#2
752B		CMP32mi8 <fi#4>, 1, %noreg, 0, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%bzerr]
768B		JNE_1 <BB#5>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#5 BB#4

784B	BB#4: derived from LLVM BB %if.then.3
	    Predecessors according to CFG: BB#2 BB#3
800B		%vreg24<def> = MOV32rm <fi#5>, 1, %noreg, 0, %noreg; mem:LD4[%nread] GR32:%vreg24
816B		MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %vreg24; mem:ST4[%retval] GR32:%vreg24
832B		JMP_1 <BB#6>
	    Successors according to CFG: BB#6

848B	BB#5: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#3
864B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -1; mem:ST4[%retval]
	    Successors according to CFG: BB#6

880B	BB#6: derived from LLVM BB %return
	    Predecessors according to CFG: BB#5 BB#4 BB#1
896B		%vreg27<def> = MOV64ri <ga:@BZ2_bzread>; GR64:%vreg27
912B		%vreg28<def> = COPY %vreg27; GR64:%vreg28,%vreg27
928B		%vreg29<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg29
944B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
960B		%RDI<def> = COPY %vreg28; GR64:%vreg28
976B		%RSI<def> = COPY %vreg29; GR64:%vreg29
992B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
1008B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1024B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1040B		STACKMAP 2, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
1056B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1072B		%vreg26<def> = MOV32rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD4[%retval] GR32:%vreg26
1088B		%EAX<def> = COPY %vreg26; GR32:%vreg26
1104B		RETQ %EAX<imp-use,kill>

# End machine code for function BZ2_bzread.

********** SIMPLE REGISTER COALESCING **********
********** Function: BZ2_bzread
********** JOINING INTERVALS ***********
if.end:
528B	%RDI<def> = COPY %vreg14; GR64:%vreg14
	Considering merging %vreg14 with %RDI
	Can only merge into reserved registers.
544B	%RSI<def> = COPY %vreg21; GR64:%vreg21
	Considering merging %vreg21 with %RSI
	Can only merge into reserved registers.
560B	%RDX<def> = COPY %vreg20; GR64:%vreg20
	Considering merging %vreg20 with %RDX
	Can only merge into reserved registers.
576B	%ECX<def> = COPY %vreg19; GR32:%vreg19
	Considering merging %vreg19 with %ECX
	Can only merge into reserved registers.
624B	%vreg18<def> = COPY %EAX<kill>; GR32:%vreg18
	Considering merging %vreg18 with %EAX
	Can only merge into reserved registers.
lor.lhs.false:
if.then.3:
return:
960B	%RDI<def> = COPY %vreg28; GR64:%vreg28
	Considering merging %vreg28 with %RDI
	Can only merge into reserved registers.
976B	%RSI<def> = COPY %vreg29; GR64:%vreg29
	Considering merging %vreg29 with %RSI
	Can only merge into reserved registers.
1088B	%EAX<def> = COPY %vreg26; GR32:%vreg26
	Considering merging %vreg26 with %EAX
	Can only merge into reserved registers.
entry:
16B	%vreg4<def> = COPY %EDX; GR32:%vreg4
	Considering merging %vreg4 with %EDX
	Can only merge into reserved registers.
32B	%vreg2<def> = COPY %RSI; GR64:%vreg2
	Considering merging %vreg2 with %RSI
	Can only merge into reserved registers.
48B	%vreg0<def> = COPY %RDI; GR64:%vreg0
	Considering merging %vreg0 with %RDI
	Can only merge into reserved registers.
176B	%RDI<def> = COPY %vreg10; GR64:%vreg10
	Considering merging %vreg10 with %RDI
	Can only merge into reserved registers.
192B	%RSI<def> = COPY %vreg11; GR64:%vreg11
	Considering merging %vreg11 with %RSI
	Can only merge into reserved registers.
if.then:
if.else:
912B	%vreg28<def> = COPY %vreg27; GR64:%vreg28,%vreg27
	Considering merging to GR64 with %vreg27 in %vreg28
		RHS = %vreg27 [896r,912r:0)  0@896r
		LHS = %vreg28 [912r,960r:0)  0@912r
		merge %vreg28:0@912r into %vreg27:0@896r --> @896r
		erased:	912r	%vreg28<def> = COPY %vreg27; GR64:%vreg28,%vreg27
		updated: 896B	%vreg28<def> = MOV64ri <ga:@BZ2_bzread>; GR64:%vreg28
	Success: %vreg27 -> %vreg28
	Result = %vreg28 [896r,960r:0)  0@896r
64B	%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
	Considering merging to GR64 with %vreg0 in %vreg1
		RHS = %vreg0 [48r,64r:0)  0@48r
		LHS = %vreg1 [64r,288r:0)  0@64r
		merge %vreg1:0@64r into %vreg0:0@48r --> @48r
		erased:	64r	%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
		updated: 48B	%vreg1<def> = COPY %RDI; GR64:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [48r,288r:0)  0@48r
80B	%vreg3<def> = COPY %vreg2; GR64:%vreg3,%vreg2
	Considering merging to GR64 with %vreg2 in %vreg3
		RHS = %vreg2 [32r,80r:0)  0@32r
		LHS = %vreg3 [80r,304r:0)  0@80r
		merge %vreg3:0@80r into %vreg2:0@32r --> @32r
		erased:	80r	%vreg3<def> = COPY %vreg2; GR64:%vreg3,%vreg2
		updated: 32B	%vreg3<def> = COPY %RSI; GR64:%vreg3
	Success: %vreg2 -> %vreg3
	Result = %vreg3 [32r,304r:0)  0@32r
96B	%vreg5<def> = COPY %vreg4; GR32:%vreg5,%vreg4
	Considering merging to GR32 with %vreg4 in %vreg5
		RHS = %vreg4 [16r,96r:0)  0@16r
		LHS = %vreg5 [96r,320r:0)  0@96r
		merge %vreg5:0@96r into %vreg4:0@16r --> @16r
		erased:	96r	%vreg5<def> = COPY %vreg4; GR32:%vreg5,%vreg4
		updated: 16B	%vreg5<def> = COPY %EDX; GR32:%vreg5
	Success: %vreg4 -> %vreg5
	Result = %vreg5 [16r,320r:0)  0@16r
128B	%vreg10<def> = COPY %vreg9; GR64:%vreg10,%vreg9
	Considering merging to GR64 with %vreg9 in %vreg10
		RHS = %vreg9 [112r,128r:0)  0@112r
		LHS = %vreg10 [128r,176r:0)  0@128r
		merge %vreg10:0@128r into %vreg9:0@112r --> @112r
		erased:	128r	%vreg10<def> = COPY %vreg9; GR64:%vreg10,%vreg9
		updated: 112B	%vreg10<def> = MOV64ri <ga:@BZ2_bzread>; GR64:%vreg10
	Success: %vreg9 -> %vreg10
	Result = %vreg10 [112r,176r:0)  0@112r
960B	%RDI<def> = COPY %vreg28; GR64:%vreg28
	Considering merging %vreg28 with %RDI
	Can only merge into reserved registers.
176B	%RDI<def> = COPY %vreg10; GR64:%vreg10
	Considering merging %vreg10 with %RDI
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
DH [0B,16r:0)[560r,592r:1)  0@0B-phi 1@560r
DIL [0B,48r:0)[176r,208r:3)[528r,592r:2)[960r,992r:1)  0@0B-phi 1@960r 2@528r 3@176r
DL [0B,16r:0)[560r,592r:1)  0@0B-phi 1@560r
SIL [0B,32r:0)[192r,208r:3)[544r,592r:2)[976r,992r:1)  0@0B-phi 1@976r 2@544r 3@192r
%vreg1 [48r,288r:0)  0@48r
%vreg3 [32r,304r:0)  0@32r
%vreg5 [16r,320r:0)  0@16r
%vreg8 [336r,352r:0)  0@336r
%vreg10 [112r,176r:0)  0@112r
%vreg11 [144r,192r:0)  0@144r
%vreg14 [448r,528r:0)  0@448r
%vreg18 [624r,688r:0)  0@624r
%vreg19 [496r,576r:0)  0@496r
%vreg20 [480r,560r:0)  0@480r
%vreg21 [464r,544r:0)  0@464r
%vreg24 [800r,816r:0)  0@800r
%vreg26 [1072r,1088r:0)  0@1072r
%vreg28 [896r,960r:0)  0@896r
%vreg29 [928r,976r:0)  0@928r
RegMasks: 208r 592r 992r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzread: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=4, align=4, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=8, align=8, at location [SP+8]
  fi#3: size=4, align=4, at location [SP+8]
  fi#4: size=4, align=4, at location [SP+8]
  fi#5: size=4, align=4, at location [SP+8]
Function Live Ins: %RDI in %vreg0, %RSI in %vreg2, %EDX in %vreg4

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI %RSI %EDX
16B		%vreg5<def> = COPY %EDX; GR32:%vreg5
32B		%vreg3<def> = COPY %RSI; GR64:%vreg3
48B		%vreg1<def> = COPY %RDI; GR64:%vreg1
112B		%vreg10<def> = MOV64ri <ga:@BZ2_bzread>; GR64:%vreg10
144B		%vreg11<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg11
160B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		%RDI<def> = COPY %vreg10; GR64:%vreg10
192B		%RSI<def> = COPY %vreg11; GR64:%vreg11
208B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
224B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
240B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
256B		STACKMAP 0, 0, %vreg1, 0, <fi#1>, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#4>, 0, %vreg5, 0, <fi#3>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack4](align=4) LD8[FixedStack3](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4) GR64:%vreg1,%vreg3 GR32:%vreg5
272B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
288B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%b.addr] GR64:%vreg1
304B		MOV64mr <fi#2>, 1, %noreg, 0, %noreg, %vreg3; mem:ST8[%buf.addr] GR64:%vreg3
320B		MOV32mr <fi#3>, 1, %noreg, 0, %noreg, %vreg5; mem:ST4[%len.addr] GR32:%vreg5
336B		%vreg8<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr] GR64:%vreg8
352B		CMP32mi8 %vreg8, 1, %noreg, 5096, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%lastErr] GR64:%vreg8
368B		JNE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

384B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
400B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
416B		JMP_1 <BB#6>
	    Successors according to CFG: BB#6

432B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0
448B		%vreg14<def> = LEA64r <fi#4>, 1, %noreg, 0, %noreg; GR64:%vreg14
464B		%vreg21<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr] GR64:%vreg21
480B		%vreg20<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%buf.addr] GR64:%vreg20
496B		%vreg19<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%len.addr] GR32:%vreg19
512B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
528B		%RDI<def> = COPY %vreg14; GR64:%vreg14
544B		%RSI<def> = COPY %vreg21; GR64:%vreg21
560B		%RDX<def> = COPY %vreg20; GR64:%vreg20
576B		%ECX<def> = COPY %vreg19; GR32:%vreg19
592B		CALL64pcrel32 <ga:@BZ2_bzRead>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %RDX<imp-use>, %ECX<imp-use,kill>, %EAX<imp-def>
608B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
624B		%vreg18<def> = COPY %EAX<kill>; GR32:%vreg18
640B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
656B		STACKMAP 1, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4)
672B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
688B		MOV32mr <fi#5>, 1, %noreg, 0, %noreg, %vreg18; mem:ST4[%nread] GR32:%vreg18
704B		CMP32mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%bzerr]
720B		JE_1 <BB#4>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#4 BB#3

736B	BB#3: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#2
752B		CMP32mi8 <fi#4>, 1, %noreg, 0, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%bzerr]
768B		JNE_1 <BB#5>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#5 BB#4

784B	BB#4: derived from LLVM BB %if.then.3
	    Predecessors according to CFG: BB#2 BB#3
800B		%vreg24<def> = MOV32rm <fi#5>, 1, %noreg, 0, %noreg; mem:LD4[%nread] GR32:%vreg24
816B		MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %vreg24; mem:ST4[%retval] GR32:%vreg24
832B		JMP_1 <BB#6>
	    Successors according to CFG: BB#6

848B	BB#5: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#3
864B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -1; mem:ST4[%retval]
	    Successors according to CFG: BB#6

880B	BB#6: derived from LLVM BB %return
	    Predecessors according to CFG: BB#5 BB#4 BB#1
896B		%vreg28<def> = MOV64ri <ga:@BZ2_bzread>; GR64:%vreg28
928B		%vreg29<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg29
944B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
960B		%RDI<def> = COPY %vreg28; GR64:%vreg28
976B		%RSI<def> = COPY %vreg29; GR64:%vreg29
992B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
1008B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1024B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1040B		STACKMAP 2, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
1056B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1072B		%vreg26<def> = MOV32rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD4[%retval] GR32:%vreg26
1088B		%EAX<def> = COPY %vreg26; GR32:%vreg26
1104B		RETQ %EAX<imp-use,kill>

# End machine code for function BZ2_bzread.

********** GREEDY REGISTER ALLOCATION **********
********** Function: BZ2_bzread
********** INTERVALS **********
DH [0B,16r:0)[560r,592r:1)  0@0B-phi 1@560r
DIL [0B,48r:0)[176r,208r:3)[528r,592r:2)[960r,992r:1)  0@0B-phi 1@960r 2@528r 3@176r
DL [0B,16r:0)[560r,592r:1)  0@0B-phi 1@560r
SIL [0B,32r:0)[192r,208r:3)[544r,592r:2)[976r,992r:1)  0@0B-phi 1@976r 2@544r 3@192r
%vreg1 [48r,288r:0)  0@48r
%vreg3 [32r,304r:0)  0@32r
%vreg5 [16r,320r:0)  0@16r
%vreg8 [336r,352r:0)  0@336r
%vreg10 [112r,176r:0)  0@112r
%vreg11 [144r,192r:0)  0@144r
%vreg14 [448r,528r:0)  0@448r
%vreg18 [624r,688r:0)  0@624r
%vreg19 [496r,576r:0)  0@496r
%vreg20 [480r,560r:0)  0@480r
%vreg21 [464r,544r:0)  0@464r
%vreg24 [800r,816r:0)  0@800r
%vreg26 [1072r,1088r:0)  0@1072r
%vreg28 [896r,960r:0)  0@896r
%vreg29 [928r,976r:0)  0@928r
RegMasks: 208r 592r 992r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzread: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=4, align=4, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=8, align=8, at location [SP+8]
  fi#3: size=4, align=4, at location [SP+8]
  fi#4: size=4, align=4, at location [SP+8]
  fi#5: size=4, align=4, at location [SP+8]
Function Live Ins: %RDI in %vreg0, %RSI in %vreg2, %EDX in %vreg4

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI %RSI %EDX
16B		%vreg5<def> = COPY %EDX; GR32:%vreg5
32B		%vreg3<def> = COPY %RSI; GR64:%vreg3
48B		%vreg1<def> = COPY %RDI; GR64:%vreg1
112B		%vreg10<def> = MOV64ri <ga:@BZ2_bzread>; GR64:%vreg10
144B		%vreg11<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg11
160B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		%RDI<def> = COPY %vreg10; GR64:%vreg10
192B		%RSI<def> = COPY %vreg11; GR64:%vreg11
208B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
224B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
240B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
256B		STACKMAP 0, 0, %vreg1, 0, <fi#1>, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#4>, 0, %vreg5, 0, <fi#3>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack4](align=4) LD8[FixedStack3](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4) GR64:%vreg1,%vreg3 GR32:%vreg5
272B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
288B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%b.addr] GR64:%vreg1
304B		MOV64mr <fi#2>, 1, %noreg, 0, %noreg, %vreg3; mem:ST8[%buf.addr] GR64:%vreg3
320B		MOV32mr <fi#3>, 1, %noreg, 0, %noreg, %vreg5; mem:ST4[%len.addr] GR32:%vreg5
336B		%vreg8<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr] GR64:%vreg8
352B		CMP32mi8 %vreg8, 1, %noreg, 5096, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%lastErr] GR64:%vreg8
368B		JNE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

384B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
400B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
416B		JMP_1 <BB#6>
	    Successors according to CFG: BB#6

432B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0
448B		%vreg14<def> = LEA64r <fi#4>, 1, %noreg, 0, %noreg; GR64:%vreg14
464B		%vreg21<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr] GR64:%vreg21
480B		%vreg20<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%buf.addr] GR64:%vreg20
496B		%vreg19<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%len.addr] GR32:%vreg19
512B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
528B		%RDI<def> = COPY %vreg14; GR64:%vreg14
544B		%RSI<def> = COPY %vreg21; GR64:%vreg21
560B		%RDX<def> = COPY %vreg20; GR64:%vreg20
576B		%ECX<def> = COPY %vreg19; GR32:%vreg19
592B		CALL64pcrel32 <ga:@BZ2_bzRead>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %RDX<imp-use>, %ECX<imp-use,kill>, %EAX<imp-def>
608B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
624B		%vreg18<def> = COPY %EAX<kill>; GR32:%vreg18
640B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
656B		STACKMAP 1, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4)
672B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
688B		MOV32mr <fi#5>, 1, %noreg, 0, %noreg, %vreg18; mem:ST4[%nread] GR32:%vreg18
704B		CMP32mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%bzerr]
720B		JE_1 <BB#4>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#4 BB#3

736B	BB#3: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#2
752B		CMP32mi8 <fi#4>, 1, %noreg, 0, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%bzerr]
768B		JNE_1 <BB#5>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#5 BB#4

784B	BB#4: derived from LLVM BB %if.then.3
	    Predecessors according to CFG: BB#2 BB#3
800B		%vreg24<def> = MOV32rm <fi#5>, 1, %noreg, 0, %noreg; mem:LD4[%nread] GR32:%vreg24
816B		MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %vreg24; mem:ST4[%retval] GR32:%vreg24
832B		JMP_1 <BB#6>
	    Successors according to CFG: BB#6

848B	BB#5: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#3
864B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -1; mem:ST4[%retval]
	    Successors according to CFG: BB#6

880B	BB#6: derived from LLVM BB %return
	    Predecessors according to CFG: BB#5 BB#4 BB#1
896B		%vreg28<def> = MOV64ri <ga:@BZ2_bzread>; GR64:%vreg28
928B		%vreg29<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg29
944B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
960B		%RDI<def> = COPY %vreg28; GR64:%vreg28
976B		%RSI<def> = COPY %vreg29; GR64:%vreg29
992B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
1008B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1024B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1040B		STACKMAP 2, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
1056B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1072B		%vreg26<def> = MOV32rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD4[%retval] GR32:%vreg26
1088B		%EAX<def> = COPY %vreg26; GR32:%vreg26
1104B		RETQ %EAX<imp-use,kill>

# End machine code for function BZ2_bzread.


selectOrSplit GR32:%vreg5 [16r,320r:0)  0@16r w=4.303977e-03
hints: %EDX
missed hint %EDX
assigning %vreg5 to %EBX: BH [16r,320r:0)  0@16r BL [16r,320r:0)  0@16r

selectOrSplit GR64:%vreg3 [32r,304r:0)  0@32r w=4.508928e-03
hints: %RSI
missed hint %RSI
%R14 is available at cost 1
Only trying the first 10 regs.
should evict: %vreg5 [16r,320r:0)  0@16r w= 4.303977e-03
hints: %EDX
can reassign: %vreg5 [16r,320r:0)  0@16r from %RBX to %EDX
should evict: %vreg5 [16r,320r:0)  0@16r w= 4.303977e-03
hints: %EDX
can reassign: %vreg5 [16r,320r:0)  0@16r from %RBX to %EDX
evicting %RBX interference: Cascade 1
unassigning %vreg5 from %EBX: BH BL
assigning %vreg3 to %RBX: BH [32r,304r:0)  0@32r BL [32r,304r:0)  0@32r
queuing new interval: %vreg5 [16r,320r:0)  0@16r

selectOrSplit GR32:%vreg5 [16r,320r:0)  0@16r w=4.303977e-03
hints: %EDX
missed hint %EDX
%R14D is available at cost 1
Only trying the first 10 regs.
assigning %vreg5 to %R14D: R14B [16r,320r:0)  0@16r

selectOrSplit GR64:%vreg1 [48r,288r:0)  0@48r w=4.734375e-03
hints: %RDI
missed hint %RDI
%R15 is available at cost 1
Only trying the first 10 regs.
should evict: %vreg3 [32r,304r:0)  0@32r w= 4.508928e-03
hints: %RSI
can reassign: %vreg3 [32r,304r:0)  0@32r from %RBX to %RSI
should evict: %vreg3 [32r,304r:0)  0@32r w= 4.508928e-03
hints: %RSI
can reassign: %vreg3 [32r,304r:0)  0@32r from %RBX to %RSI
evicting %RBX interference: Cascade 2
unassigning %vreg3 from %RBX: BH BL
assigning %vreg1 to %RBX: BH [48r,288r:0)  0@48r BL [48r,288r:0)  0@48r
queuing new interval: %vreg3 [32r,304r:0)  0@32r

selectOrSplit GR64:%vreg3 [32r,304r:0)  0@32r w=4.508928e-03
hints: %RSI
missed hint %RSI
%R15 is available at cost 1
Only trying the first 10 regs.
assigning %vreg3 to %R15: R15B [32r,304r:0)  0@32r

selectOrSplit GR64:%vreg10 [112r,176r:0)  0@112r w=2.176724e-03
hints: %RDI
assigning %vreg10 to %RDI: DIL [112r,176r:0)  0@112r

selectOrSplit GR64:%vreg11 [144r,192r:0)  0@144r w=4.508928e-03
hints: %RSI
assigning %vreg11 to %RSI: SIL [144r,192r:0)  0@144r

selectOrSplit GR64:%vreg14 [448r,528r:0)  0@448r w=1.035384e-03
hints: %RDI
assigning %vreg14 to %RDI: DIL [448r,528r:0)  0@448r

selectOrSplit GR64:%vreg21 [464r,544r:0)  0@464r w=2.070767e-03
hints: %RSI
assigning %vreg21 to %RSI: SIL [464r,544r:0)  0@464r

selectOrSplit GR64:%vreg20 [480r,560r:0)  0@480r w=2.070767e-03
hints: %RDX
assigning %vreg20 to %RDX: DH [480r,560r:0)  0@480r DL [480r,560r:0)  0@480r

selectOrSplit GR32:%vreg19 [496r,576r:0)  0@496r w=2.070767e-03
hints: %ECX
assigning %vreg19 to %ECX: CH [496r,576r:0)  0@496r CL [496r,576r:0)  0@496r

selectOrSplit GR32:%vreg18 [624r,688r:0)  0@624r w=2.142173e-03
hints: %EAX
assigning %vreg18 to %EAX: AH [624r,688r:0)  0@624r AL [624r,688r:0)  0@624r

selectOrSplit GR64:%vreg28 [896r,960r:0)  0@896r w=2.176724e-03
hints: %RDI
assigning %vreg28 to %RDI: DIL [896r,960r:0)  0@896r

selectOrSplit GR64:%vreg29 [928r,976r:0)  0@928r w=4.508928e-03
hints: %RSI
assigning %vreg29 to %RSI: SIL [928r,976r:0)  0@928r

selectOrSplit GR32:%vreg26 [1072r,1088r:0)  0@1072r w=inf
hints: %EAX
assigning %vreg26 to %EAX: AH [1072r,1088r:0)  0@1072r AL [1072r,1088r:0)  0@1072r

selectOrSplit GR64:%vreg8 [336r,352r:0)  0@336r w=inf
assigning %vreg8 to %RAX: AH [336r,352r:0)  0@336r AL [336r,352r:0)  0@336r

selectOrSplit GR32:%vreg24 [800r,816r:0)  0@800r w=inf
assigning %vreg24 to %EAX: AH [800r,816r:0)  0@800r AL [800r,816r:0)  0@800r

********** STACK TRANSFORMATION METADATA **********
********** Function: BZ2_bzread
********** REGISTER MAP **********
[%vreg1 -> %RBX] GR64
[%vreg3 -> %R15] GR64
[%vreg5 -> %R14D] GR32
[%vreg8 -> %RAX] GR64
[%vreg10 -> %RDI] GR64
[%vreg11 -> %RSI] GR64
[%vreg14 -> %RDI] GR64
[%vreg18 -> %EAX] GR32
[%vreg19 -> %ECX] GR32
[%vreg20 -> %RDX] GR64
[%vreg21 -> %RSI] GR64
[%vreg24 -> %EAX] GR32
[%vreg26 -> %EAX] GR32
[%vreg28 -> %RDI] GR64
[%vreg29 -> %RSI] GR64


Stackmap 0:
  STACKMAP 0, 0, %vreg1, 0, <fi#1>, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#4>, 0, %vreg5, 0, <fi#3>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack4](align=4) LD8[FixedStack3](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4) GR64:%vreg1,%vreg3 GR32:%vreg5

i8* %b: in register %RBX (vreg 1)
i8** %b.addr: in stack slot 1 (size: 8)
i8* %buf: in register %R15 (vreg 3)
i8** %buf.addr: in stack slot 2 (size: 8)
i32* %bzerr: in stack slot 4 (size: 4)
i32 %len: in register %R14D (vreg 5)
i32* %len.addr: in stack slot 3 (size: 4)
i32* %nread: in stack slot 5 (size: 4)
i32* %retval: in stack slot 0 (size: 4)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4)

i32* %bzerr: in stack slot 4 (size: 4)
i32* %nread: in stack slot 5 (size: 4)
i32* %retval: in stack slot 0 (size: 4)

Duplicate operand locations:


Stackmap 2:
  STACKMAP 2, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)

i32* %retval: in stack slot 0 (size: 4)

Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, %vreg1, 0, <fi#1>, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#4>, 0, %vreg5, 0, <fi#3>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack4](align=4) LD8[FixedStack3](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4) GR64:%vreg1,%vreg3 GR32:%vreg5
  -> Call instruction SlotIndex 208B, searching vregs 0 -> 30 and stack slots -1 -> 6

  STACKMAP 1, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4)
  -> Call instruction SlotIndex 592B, searching vregs 0 -> 30 and stack slots -1 -> 6

  STACKMAP 2, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
  -> Call instruction SlotIndex 992B, searching vregs 0 -> 30 and stack slots -1 -> 6

********** REWRITE VIRTUAL REGISTERS **********
********** Function: BZ2_bzread
********** REGISTER MAP **********
[%vreg1 -> %RBX] GR64
[%vreg3 -> %R15] GR64
[%vreg5 -> %R14D] GR32
[%vreg8 -> %RAX] GR64
[%vreg10 -> %RDI] GR64
[%vreg11 -> %RSI] GR64
[%vreg14 -> %RDI] GR64
[%vreg18 -> %EAX] GR32
[%vreg19 -> %ECX] GR32
[%vreg20 -> %RDX] GR64
[%vreg21 -> %RSI] GR64
[%vreg24 -> %EAX] GR32
[%vreg26 -> %EAX] GR32
[%vreg28 -> %RDI] GR64
[%vreg29 -> %RSI] GR64

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %EDX %RDI %RSI
16B		%vreg5<def> = COPY %EDX; GR32:%vreg5
32B		%vreg3<def> = COPY %RSI; GR64:%vreg3
48B		%vreg1<def> = COPY %RDI; GR64:%vreg1
112B		%vreg10<def> = MOV64ri <ga:@BZ2_bzread>; GR64:%vreg10
144B		%vreg11<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg11
160B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		%RDI<def> = COPY %vreg10<kill>; GR64:%vreg10
192B		%RSI<def> = COPY %vreg11<kill>; GR64:%vreg11
208B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
224B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
240B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
256B		STACKMAP 0, 0, %vreg1, 0, <fi#1>, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#4>, 0, %vreg5, 0, <fi#3>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack4](align=4) LD8[FixedStack3](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4) GR64:%vreg1,%vreg3 GR32:%vreg5
272B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
288B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg1<kill>; mem:ST8[%b.addr] GR64:%vreg1
304B		MOV64mr <fi#2>, 1, %noreg, 0, %noreg, %vreg3<kill>; mem:ST8[%buf.addr] GR64:%vreg3
320B		MOV32mr <fi#3>, 1, %noreg, 0, %noreg, %vreg5<kill>; mem:ST4[%len.addr] GR32:%vreg5
336B		%vreg8<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr] GR64:%vreg8
352B		CMP32mi8 %vreg8<kill>, 1, %noreg, 5096, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%lastErr] GR64:%vreg8
368B		JNE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1
> %R14D<def> = COPY %EDX
> %R15<def> = COPY %RSI
> %RBX<def> = COPY %RDI
> %RDI<def> = MOV64ri <ga:@BZ2_bzread>
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 0, 0, %RBX, 0, <fi#1>, 0, %R15, 0, <fi#2>, 0, 0, <fi#4>, 0, %R14D, 0, <fi#3>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack4](align=4) LD8[FixedStack3](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %RBX<kill>; mem:ST8[%b.addr]
> MOV64mr <fi#2>, 1, %noreg, 0, %noreg, %R15<kill>; mem:ST8[%buf.addr]
> MOV32mr <fi#3>, 1, %noreg, 0, %noreg, %R14D<kill>; mem:ST4[%len.addr]
> %RAX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr]
> CMP32mi8 %RAX<kill>, 1, %noreg, 5096, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%lastErr]
> JNE_1 <BB#2>, %EFLAGS<imp-use,kill>
384B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
400B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
416B		JMP_1 <BB#6>
	    Successors according to CFG: BB#6
> MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval]
> JMP_1 <BB#6>
432B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0
448B		%vreg14<def> = LEA64r <fi#4>, 1, %noreg, 0, %noreg; GR64:%vreg14
464B		%vreg21<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr] GR64:%vreg21
480B		%vreg20<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%buf.addr] GR64:%vreg20
496B		%vreg19<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%len.addr] GR32:%vreg19
512B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
528B		%RDI<def> = COPY %vreg14<kill>; GR64:%vreg14
544B		%RSI<def> = COPY %vreg21<kill>; GR64:%vreg21
560B		%RDX<def> = COPY %vreg20<kill>; GR64:%vreg20
576B		%ECX<def> = COPY %vreg19<kill>; GR32:%vreg19
592B		CALL64pcrel32 <ga:@BZ2_bzRead>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %RDX<imp-use>, %ECX<imp-use>, %EAX<imp-def>
608B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
624B		%vreg18<def> = COPY %EAX; GR32:%vreg18
640B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
656B		STACKMAP 1, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4)
672B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
688B		MOV32mr <fi#5>, 1, %noreg, 0, %noreg, %vreg18<kill>; mem:ST4[%nread] GR32:%vreg18
704B		CMP32mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%bzerr]
720B		JE_1 <BB#4>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#4 BB#3
> %RDI<def> = LEA64r <fi#4>, 1, %noreg, 0, %noreg
> %RSI<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr]
> %RDX<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%buf.addr]
> %ECX<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%len.addr]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> %RDX<def> = COPY %RDX<kill>
Deleting identity copy.
> %ECX<def> = COPY %ECX<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@BZ2_bzRead>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %RDX<imp-use>, %ECX<imp-use>, %EAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def> = COPY %EAX
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 1, 0, 0, <fi#4>, 0, 0, <fi#5>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack4](align=4) LD8[FixedStack5](align=4) LD8[FixedStack0](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV32mr <fi#5>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%nread]
> CMP32mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%bzerr]
> JE_1 <BB#4>, %EFLAGS<imp-use,kill>
736B	BB#3: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#2
752B		CMP32mi8 <fi#4>, 1, %noreg, 0, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%bzerr]
768B		JNE_1 <BB#5>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#5 BB#4
> CMP32mi8 <fi#4>, 1, %noreg, 0, %noreg, 4, %EFLAGS<imp-def>; mem:LD4[%bzerr]
> JNE_1 <BB#5>, %EFLAGS<imp-use,kill>
784B	BB#4: derived from LLVM BB %if.then.3
	    Predecessors according to CFG: BB#2 BB#3
800B		%vreg24<def> = MOV32rm <fi#5>, 1, %noreg, 0, %noreg; mem:LD4[%nread] GR32:%vreg24
816B		MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %vreg24<kill>; mem:ST4[%retval] GR32:%vreg24
832B		JMP_1 <BB#6>
	    Successors according to CFG: BB#6
> %EAX<def> = MOV32rm <fi#5>, 1, %noreg, 0, %noreg; mem:LD4[%nread]
> MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%retval]
> JMP_1 <BB#6>
848B	BB#5: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#3
864B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -1; mem:ST4[%retval]
	    Successors according to CFG: BB#6
> MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -1; mem:ST4[%retval]
880B	BB#6: derived from LLVM BB %return
	    Predecessors according to CFG: BB#5 BB#4 BB#1
896B		%vreg28<def> = MOV64ri <ga:@BZ2_bzread>; GR64:%vreg28
928B		%vreg29<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg29
944B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
960B		%RDI<def> = COPY %vreg28<kill>; GR64:%vreg28
976B		%RSI<def> = COPY %vreg29<kill>; GR64:%vreg29
992B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
1008B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1024B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1040B		STACKMAP 2, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
1056B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1072B		%vreg26<def> = MOV32rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD4[%retval] GR32:%vreg26
1088B		%EAX<def> = COPY %vreg26<kill>; GR32:%vreg26
1104B		RETQ %EAX<imp-use>
> %RDI<def> = MOV64ri <ga:@BZ2_bzread>
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 2, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def> = MOV32rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD4[%retval]
> %EAX<def> = COPY %EAX<kill>
Deleting identity copy.
> RETQ %EAX<imp-use>
Computing live-in reg-units in ABI blocks.
0B	BB#0 DIL#0 SIL#0 DH#0 DL#0
Created 4 new intervals.
********** INTERVALS **********
DH [0B,16r:0)[448r,480r:1)  0@0B-phi 1@448r
DIL [0B,48r:0)[176r,208r:2)[416r,480r:3)[768r,800r:1)  0@0B-phi 1@768r 2@176r 3@416r
DL [0B,16r:0)[448r,480r:1)  0@0B-phi 1@448r
SIL [0B,32r:0)[192r,208r:2)[432r,480r:3)[784r,800r:1)  0@0B-phi 1@784r 2@192r 3@432r
%vreg0 [48r,64r:0)  0@48r
%vreg1 [64r,304r:0)  0@64r
%vreg2 [32r,80r:0)  0@32r
%vreg3 [80r,320r:0)  0@80r
%vreg4 [16r,96r:0)  0@16r
%vreg5 [96r,336r:0)  0@96r
%vreg7 [240r,416r:0)  0@240r
%vreg11 [384r,464r:0)  0@384r
%vreg12 [368r,448r:0)  0@368r
%vreg13 [352r,432r:0)  0@352r
%vreg14 [112r,128r:0)  0@112r
%vreg15 [128r,176r:0)  0@128r
%vreg16 [144r,192r:0)  0@144r
%vreg18 [608r,624r:0)  0@608r
%vreg20 [880r,896r:0)  0@880r
%vreg21 [704r,720r:0)  0@704r
%vreg22 [720r,768r:0)  0@720r
%vreg23 [736r,784r:0)  0@736r
RegMasks: 208r 480r 800r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzwrite: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=4, align=4, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=8, align=8, at location [SP+8]
  fi#3: size=4, align=4, at location [SP+8]
  fi#4: size=4, align=4, at location [SP+8]
Function Live Ins: %RDI in %vreg0, %RSI in %vreg2, %EDX in %vreg4

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI %RSI %EDX
16B		%vreg4<def> = COPY %EDX; GR32:%vreg4
32B		%vreg2<def> = COPY %RSI; GR64:%vreg2
48B		%vreg0<def> = COPY %RDI; GR64:%vreg0
64B		%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
80B		%vreg3<def> = COPY %vreg2; GR64:%vreg3,%vreg2
96B		%vreg5<def> = COPY %vreg4; GR32:%vreg5,%vreg4
112B		%vreg14<def> = MOV64ri <ga:@BZ2_bzwrite>; GR64:%vreg14
128B		%vreg15<def> = COPY %vreg14; GR64:%vreg15,%vreg14
144B		%vreg16<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg16
160B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		%RDI<def> = COPY %vreg15; GR64:%vreg15
192B		%RSI<def> = COPY %vreg16; GR64:%vreg16
208B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
224B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
240B		%vreg7<def> = LEA64r <fi#4>, 1, %noreg, 0, %noreg; GR64:%vreg7
256B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
272B		STACKMAP 0, 0, %vreg1, 0, <fi#1>, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#4>, 0, %vreg5, 0, <fi#3>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack4](align=4) LD8[FixedStack3](align=4) LD8[FixedStack0](align=4) GR64:%vreg1,%vreg3 GR32:%vreg5
288B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
304B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%b.addr] GR64:%vreg1
320B		MOV64mr <fi#2>, 1, %noreg, 0, %noreg, %vreg3; mem:ST8[%buf.addr] GR64:%vreg3
336B		MOV32mr <fi#3>, 1, %noreg, 0, %noreg, %vreg5; mem:ST4[%len.addr] GR32:%vreg5
352B		%vreg13<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr] GR64:%vreg13
368B		%vreg12<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%buf.addr] GR64:%vreg12
384B		%vreg11<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%len.addr] GR32:%vreg11
400B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
416B		%RDI<def> = COPY %vreg7; GR64:%vreg7
432B		%RSI<def> = COPY %vreg13; GR64:%vreg13
448B		%RDX<def> = COPY %vreg12; GR64:%vreg12
464B		%ECX<def> = COPY %vreg11; GR32:%vreg11
480B		CALL64pcrel32 <ga:@BZ2_bzWrite>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %RDX<imp-use>, %ECX<imp-use,kill>
496B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
512B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
528B		STACKMAP 1, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack4](align=4) LD8[FixedStack3](align=4) LD8[FixedStack0](align=4)
544B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
560B		CMP32mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%bzerr]
576B		JNE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

592B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
608B		%vreg18<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%len.addr] GR32:%vreg18
624B		MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %vreg18; mem:ST4[%retval] GR32:%vreg18
640B		JMP_1 <BB#3>
	    Successors according to CFG: BB#3

656B	BB#2: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#0
672B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -1; mem:ST4[%retval]
	    Successors according to CFG: BB#3

688B	BB#3: derived from LLVM BB %return
	    Predecessors according to CFG: BB#2 BB#1
704B		%vreg21<def> = MOV64ri <ga:@BZ2_bzwrite>; GR64:%vreg21
720B		%vreg22<def> = COPY %vreg21; GR64:%vreg22,%vreg21
736B		%vreg23<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg23
752B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
768B		%RDI<def> = COPY %vreg22; GR64:%vreg22
784B		%RSI<def> = COPY %vreg23; GR64:%vreg23
800B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
816B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
832B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
848B		STACKMAP 2, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
864B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
880B		%vreg20<def> = MOV32rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD4[%retval] GR32:%vreg20
896B		%EAX<def> = COPY %vreg20; GR32:%vreg20
912B		RETQ %EAX<imp-use,kill>

# End machine code for function BZ2_bzwrite.

********** SIMPLE REGISTER COALESCING **********
********** Function: BZ2_bzwrite
********** JOINING INTERVALS ***********
entry:
16B	%vreg4<def> = COPY %EDX; GR32:%vreg4
	Considering merging %vreg4 with %EDX
	Can only merge into reserved registers.
32B	%vreg2<def> = COPY %RSI; GR64:%vreg2
	Considering merging %vreg2 with %RSI
	Can only merge into reserved registers.
48B	%vreg0<def> = COPY %RDI; GR64:%vreg0
	Considering merging %vreg0 with %RDI
	Can only merge into reserved registers.
176B	%RDI<def> = COPY %vreg15; GR64:%vreg15
	Considering merging %vreg15 with %RDI
	Can only merge into reserved registers.
192B	%RSI<def> = COPY %vreg16; GR64:%vreg16
	Considering merging %vreg16 with %RSI
	Can only merge into reserved registers.
416B	%RDI<def> = COPY %vreg7; GR64:%vreg7
	Considering merging %vreg7 with %RDI
	Can only merge into reserved registers.
432B	%RSI<def> = COPY %vreg13; GR64:%vreg13
	Considering merging %vreg13 with %RSI
	Can only merge into reserved registers.
448B	%RDX<def> = COPY %vreg12; GR64:%vreg12
	Considering merging %vreg12 with %RDX
	Can only merge into reserved registers.
464B	%ECX<def> = COPY %vreg11; GR32:%vreg11
	Considering merging %vreg11 with %ECX
	Can only merge into reserved registers.
if.then:
if.else:
return:
768B	%RDI<def> = COPY %vreg22; GR64:%vreg22
	Considering merging %vreg22 with %RDI
	Can only merge into reserved registers.
784B	%RSI<def> = COPY %vreg23; GR64:%vreg23
	Considering merging %vreg23 with %RSI
	Can only merge into reserved registers.
896B	%EAX<def> = COPY %vreg20; GR32:%vreg20
	Considering merging %vreg20 with %EAX
	Can only merge into reserved registers.
64B	%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
	Considering merging to GR64 with %vreg0 in %vreg1
		RHS = %vreg0 [48r,64r:0)  0@48r
		LHS = %vreg1 [64r,304r:0)  0@64r
		merge %vreg1:0@64r into %vreg0:0@48r --> @48r
		erased:	64r	%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
		updated: 48B	%vreg1<def> = COPY %RDI; GR64:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [48r,304r:0)  0@48r
80B	%vreg3<def> = COPY %vreg2; GR64:%vreg3,%vreg2
	Considering merging to GR64 with %vreg2 in %vreg3
		RHS = %vreg2 [32r,80r:0)  0@32r
		LHS = %vreg3 [80r,320r:0)  0@80r
		merge %vreg3:0@80r into %vreg2:0@32r --> @32r
		erased:	80r	%vreg3<def> = COPY %vreg2; GR64:%vreg3,%vreg2
		updated: 32B	%vreg3<def> = COPY %RSI; GR64:%vreg3
	Success: %vreg2 -> %vreg3
	Result = %vreg3 [32r,320r:0)  0@32r
96B	%vreg5<def> = COPY %vreg4; GR32:%vreg5,%vreg4
	Considering merging to GR32 with %vreg4 in %vreg5
		RHS = %vreg4 [16r,96r:0)  0@16r
		LHS = %vreg5 [96r,336r:0)  0@96r
		merge %vreg5:0@96r into %vreg4:0@16r --> @16r
		erased:	96r	%vreg5<def> = COPY %vreg4; GR32:%vreg5,%vreg4
		updated: 16B	%vreg5<def> = COPY %EDX; GR32:%vreg5
	Success: %vreg4 -> %vreg5
	Result = %vreg5 [16r,336r:0)  0@16r
128B	%vreg15<def> = COPY %vreg14; GR64:%vreg15,%vreg14
	Considering merging to GR64 with %vreg14 in %vreg15
		RHS = %vreg14 [112r,128r:0)  0@112r
		LHS = %vreg15 [128r,176r:0)  0@128r
		merge %vreg15:0@128r into %vreg14:0@112r --> @112r
		erased:	128r	%vreg15<def> = COPY %vreg14; GR64:%vreg15,%vreg14
		updated: 112B	%vreg15<def> = MOV64ri <ga:@BZ2_bzwrite>; GR64:%vreg15
	Success: %vreg14 -> %vreg15
	Result = %vreg15 [112r,176r:0)  0@112r
720B	%vreg22<def> = COPY %vreg21; GR64:%vreg22,%vreg21
	Considering merging to GR64 with %vreg21 in %vreg22
		RHS = %vreg21 [704r,720r:0)  0@704r
		LHS = %vreg22 [720r,768r:0)  0@720r
		merge %vreg22:0@720r into %vreg21:0@704r --> @704r
		erased:	720r	%vreg22<def> = COPY %vreg21; GR64:%vreg22,%vreg21
		updated: 704B	%vreg22<def> = MOV64ri <ga:@BZ2_bzwrite>; GR64:%vreg22
	Success: %vreg21 -> %vreg22
	Result = %vreg22 [704r,768r:0)  0@704r
176B	%RDI<def> = COPY %vreg15; GR64:%vreg15
	Considering merging %vreg15 with %RDI
	Can only merge into reserved registers.
768B	%RDI<def> = COPY %vreg22; GR64:%vreg22
	Considering merging %vreg22 with %RDI
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
DH [0B,16r:0)[448r,480r:1)  0@0B-phi 1@448r
DIL [0B,48r:0)[176r,208r:2)[416r,480r:3)[768r,800r:1)  0@0B-phi 1@768r 2@176r 3@416r
DL [0B,16r:0)[448r,480r:1)  0@0B-phi 1@448r
SIL [0B,32r:0)[192r,208r:2)[432r,480r:3)[784r,800r:1)  0@0B-phi 1@784r 2@192r 3@432r
%vreg1 [48r,304r:0)  0@48r
%vreg3 [32r,320r:0)  0@32r
%vreg5 [16r,336r:0)  0@16r
%vreg7 [240r,416r:0)  0@240r
%vreg11 [384r,464r:0)  0@384r
%vreg12 [368r,448r:0)  0@368r
%vreg13 [352r,432r:0)  0@352r
%vreg15 [112r,176r:0)  0@112r
%vreg16 [144r,192r:0)  0@144r
%vreg18 [608r,624r:0)  0@608r
%vreg20 [880r,896r:0)  0@880r
%vreg22 [704r,768r:0)  0@704r
%vreg23 [736r,784r:0)  0@736r
RegMasks: 208r 480r 800r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzwrite: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=4, align=4, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=8, align=8, at location [SP+8]
  fi#3: size=4, align=4, at location [SP+8]
  fi#4: size=4, align=4, at location [SP+8]
Function Live Ins: %RDI in %vreg0, %RSI in %vreg2, %EDX in %vreg4

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI %RSI %EDX
16B		%vreg5<def> = COPY %EDX; GR32:%vreg5
32B		%vreg3<def> = COPY %RSI; GR64:%vreg3
48B		%vreg1<def> = COPY %RDI; GR64:%vreg1
112B		%vreg15<def> = MOV64ri <ga:@BZ2_bzwrite>; GR64:%vreg15
144B		%vreg16<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg16
160B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		%RDI<def> = COPY %vreg15; GR64:%vreg15
192B		%RSI<def> = COPY %vreg16; GR64:%vreg16
208B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
224B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
240B		%vreg7<def> = LEA64r <fi#4>, 1, %noreg, 0, %noreg; GR64:%vreg7
256B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
272B		STACKMAP 0, 0, %vreg1, 0, <fi#1>, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#4>, 0, %vreg5, 0, <fi#3>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack4](align=4) LD8[FixedStack3](align=4) LD8[FixedStack0](align=4) GR64:%vreg1,%vreg3 GR32:%vreg5
288B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
304B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%b.addr] GR64:%vreg1
320B		MOV64mr <fi#2>, 1, %noreg, 0, %noreg, %vreg3; mem:ST8[%buf.addr] GR64:%vreg3
336B		MOV32mr <fi#3>, 1, %noreg, 0, %noreg, %vreg5; mem:ST4[%len.addr] GR32:%vreg5
352B		%vreg13<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr] GR64:%vreg13
368B		%vreg12<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%buf.addr] GR64:%vreg12
384B		%vreg11<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%len.addr] GR32:%vreg11
400B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
416B		%RDI<def> = COPY %vreg7; GR64:%vreg7
432B		%RSI<def> = COPY %vreg13; GR64:%vreg13
448B		%RDX<def> = COPY %vreg12; GR64:%vreg12
464B		%ECX<def> = COPY %vreg11; GR32:%vreg11
480B		CALL64pcrel32 <ga:@BZ2_bzWrite>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %RDX<imp-use>, %ECX<imp-use,kill>
496B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
512B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
528B		STACKMAP 1, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack4](align=4) LD8[FixedStack3](align=4) LD8[FixedStack0](align=4)
544B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
560B		CMP32mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%bzerr]
576B		JNE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

592B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
608B		%vreg18<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%len.addr] GR32:%vreg18
624B		MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %vreg18; mem:ST4[%retval] GR32:%vreg18
640B		JMP_1 <BB#3>
	    Successors according to CFG: BB#3

656B	BB#2: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#0
672B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -1; mem:ST4[%retval]
	    Successors according to CFG: BB#3

688B	BB#3: derived from LLVM BB %return
	    Predecessors according to CFG: BB#2 BB#1
704B		%vreg22<def> = MOV64ri <ga:@BZ2_bzwrite>; GR64:%vreg22
736B		%vreg23<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg23
752B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
768B		%RDI<def> = COPY %vreg22; GR64:%vreg22
784B		%RSI<def> = COPY %vreg23; GR64:%vreg23
800B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
816B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
832B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
848B		STACKMAP 2, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
864B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
880B		%vreg20<def> = MOV32rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD4[%retval] GR32:%vreg20
896B		%EAX<def> = COPY %vreg20; GR32:%vreg20
912B		RETQ %EAX<imp-use,kill>

# End machine code for function BZ2_bzwrite.

********** GREEDY REGISTER ALLOCATION **********
********** Function: BZ2_bzwrite
********** INTERVALS **********
DH [0B,16r:0)[448r,480r:1)  0@0B-phi 1@448r
DIL [0B,48r:0)[176r,208r:2)[416r,480r:3)[768r,800r:1)  0@0B-phi 1@768r 2@176r 3@416r
DL [0B,16r:0)[448r,480r:1)  0@0B-phi 1@448r
SIL [0B,32r:0)[192r,208r:2)[432r,480r:3)[784r,800r:1)  0@0B-phi 1@784r 2@192r 3@432r
%vreg1 [48r,304r:0)  0@48r
%vreg3 [32r,320r:0)  0@32r
%vreg5 [16r,336r:0)  0@16r
%vreg7 [240r,416r:0)  0@240r
%vreg11 [384r,464r:0)  0@384r
%vreg12 [368r,448r:0)  0@368r
%vreg13 [352r,432r:0)  0@352r
%vreg15 [112r,176r:0)  0@112r
%vreg16 [144r,192r:0)  0@144r
%vreg18 [608r,624r:0)  0@608r
%vreg20 [880r,896r:0)  0@880r
%vreg22 [704r,768r:0)  0@704r
%vreg23 [736r,784r:0)  0@736r
RegMasks: 208r 480r 800r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzwrite: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=4, align=4, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=8, align=8, at location [SP+8]
  fi#3: size=4, align=4, at location [SP+8]
  fi#4: size=4, align=4, at location [SP+8]
Function Live Ins: %RDI in %vreg0, %RSI in %vreg2, %EDX in %vreg4

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI %RSI %EDX
16B		%vreg5<def> = COPY %EDX; GR32:%vreg5
32B		%vreg3<def> = COPY %RSI; GR64:%vreg3
48B		%vreg1<def> = COPY %RDI; GR64:%vreg1
112B		%vreg15<def> = MOV64ri <ga:@BZ2_bzwrite>; GR64:%vreg15
144B		%vreg16<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg16
160B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		%RDI<def> = COPY %vreg15; GR64:%vreg15
192B		%RSI<def> = COPY %vreg16; GR64:%vreg16
208B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
224B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
240B		%vreg7<def> = LEA64r <fi#4>, 1, %noreg, 0, %noreg; GR64:%vreg7
256B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
272B		STACKMAP 0, 0, %vreg1, 0, <fi#1>, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#4>, 0, %vreg5, 0, <fi#3>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack4](align=4) LD8[FixedStack3](align=4) LD8[FixedStack0](align=4) GR64:%vreg1,%vreg3 GR32:%vreg5
288B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
304B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%b.addr] GR64:%vreg1
320B		MOV64mr <fi#2>, 1, %noreg, 0, %noreg, %vreg3; mem:ST8[%buf.addr] GR64:%vreg3
336B		MOV32mr <fi#3>, 1, %noreg, 0, %noreg, %vreg5; mem:ST4[%len.addr] GR32:%vreg5
352B		%vreg13<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr] GR64:%vreg13
368B		%vreg12<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%buf.addr] GR64:%vreg12
384B		%vreg11<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%len.addr] GR32:%vreg11
400B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
416B		%RDI<def> = COPY %vreg7; GR64:%vreg7
432B		%RSI<def> = COPY %vreg13; GR64:%vreg13
448B		%RDX<def> = COPY %vreg12; GR64:%vreg12
464B		%ECX<def> = COPY %vreg11; GR32:%vreg11
480B		CALL64pcrel32 <ga:@BZ2_bzWrite>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %RDX<imp-use>, %ECX<imp-use,kill>
496B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
512B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
528B		STACKMAP 1, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack4](align=4) LD8[FixedStack3](align=4) LD8[FixedStack0](align=4)
544B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
560B		CMP32mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%bzerr]
576B		JNE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

592B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
608B		%vreg18<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%len.addr] GR32:%vreg18
624B		MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %vreg18; mem:ST4[%retval] GR32:%vreg18
640B		JMP_1 <BB#3>
	    Successors according to CFG: BB#3

656B	BB#2: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#0
672B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -1; mem:ST4[%retval]
	    Successors according to CFG: BB#3

688B	BB#3: derived from LLVM BB %return
	    Predecessors according to CFG: BB#2 BB#1
704B		%vreg22<def> = MOV64ri <ga:@BZ2_bzwrite>; GR64:%vreg22
736B		%vreg23<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg23
752B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
768B		%RDI<def> = COPY %vreg22; GR64:%vreg22
784B		%RSI<def> = COPY %vreg23; GR64:%vreg23
800B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
816B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
832B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
848B		STACKMAP 2, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
864B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
880B		%vreg20<def> = MOV32rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD4[%retval] GR32:%vreg20
896B		%EAX<def> = COPY %vreg20; GR32:%vreg20
912B		RETQ %EAX<imp-use,kill>

# End machine code for function BZ2_bzwrite.


selectOrSplit GR32:%vreg5 [16r,336r:0)  0@16r w=4.208333e-03
hints: %EDX
missed hint %EDX
assigning %vreg5 to %EBX: BH [16r,336r:0)  0@16r BL [16r,336r:0)  0@16r

selectOrSplit GR64:%vreg3 [32r,320r:0)  0@32r w=4.404070e-03
hints: %RSI
missed hint %RSI
%R14 is available at cost 1
Only trying the first 10 regs.
should evict: %vreg5 [16r,336r:0)  0@16r w= 4.208333e-03
hints: %EDX
can reassign: %vreg5 [16r,336r:0)  0@16r from %RBX to %EDX
should evict: %vreg5 [16r,336r:0)  0@16r w= 4.208333e-03
hints: %EDX
can reassign: %vreg5 [16r,336r:0)  0@16r from %RBX to %EDX
evicting %RBX interference: Cascade 1
unassigning %vreg5 from %EBX: BH BL
assigning %vreg3 to %RBX: BH [32r,320r:0)  0@32r BL [32r,320r:0)  0@32r
queuing new interval: %vreg5 [16r,336r:0)  0@16r

selectOrSplit GR32:%vreg5 [16r,336r:0)  0@16r w=4.208333e-03
hints: %EDX
missed hint %EDX
%R14D is available at cost 1
Only trying the first 10 regs.
assigning %vreg5 to %R14D: R14B [16r,336r:0)  0@16r

selectOrSplit GR64:%vreg1 [48r,304r:0)  0@48r w=4.618902e-03
hints: %RDI
missed hint %RDI
%R15 is available at cost 1
Only trying the first 10 regs.
should evict: %vreg3 [32r,320r:0)  0@32r w= 4.404070e-03
hints: %RSI
can reassign: %vreg3 [32r,320r:0)  0@32r from %RBX to %RSI
should evict: %vreg3 [32r,320r:0)  0@32r w= 4.404070e-03
hints: %RSI
can reassign: %vreg3 [32r,320r:0)  0@32r from %RBX to %RSI
evicting %RBX interference: Cascade 2
unassigning %vreg3 from %RBX: BH BL
assigning %vreg1 to %RBX: BH [48r,304r:0)  0@48r BL [48r,304r:0)  0@48r
queuing new interval: %vreg3 [32r,320r:0)  0@32r

selectOrSplit GR64:%vreg3 [32r,320r:0)  0@32r w=4.404070e-03
hints: %RSI
missed hint %RSI
%R15 is available at cost 1
Only trying the first 10 regs.
assigning %vreg3 to %R15: R15B [32r,320r:0)  0@32r

selectOrSplit GR64:%vreg15 [112r,176r:0)  0@112r w=2.176724e-03
hints: %RDI
assigning %vreg15 to %RDI: DIL [112r,176r:0)  0@112r

selectOrSplit GR64:%vreg16 [144r,192r:0)  0@144r w=4.508928e-03
hints: %RSI
assigning %vreg16 to %RSI: SIL [144r,192r:0)  0@144r

selectOrSplit GR64:%vreg7 [240r,416r:0)  0@240r w=1.753472e-03
hints: %RDI
assigning %vreg7 to %RDI: DIL [240r,416r:0)  0@240r

selectOrSplit GR64:%vreg13 [352r,432r:0)  0@352r w=4.208333e-03
hints: %RSI
assigning %vreg13 to %RSI: SIL [352r,432r:0)  0@352r

selectOrSplit GR64:%vreg12 [368r,448r:0)  0@368r w=4.208333e-03
hints: %RDX
assigning %vreg12 to %RDX: DH [368r,448r:0)  0@368r DL [368r,448r:0)  0@368r

selectOrSplit GR32:%vreg11 [384r,464r:0)  0@384r w=4.208333e-03
hints: %ECX
assigning %vreg11 to %ECX: CH [384r,464r:0)  0@384r CL [384r,464r:0)  0@384r

selectOrSplit GR64:%vreg22 [704r,768r:0)  0@704r w=2.176724e-03
hints: %RDI
assigning %vreg22 to %RDI: DIL [704r,768r:0)  0@704r

selectOrSplit GR64:%vreg23 [736r,784r:0)  0@736r w=4.508928e-03
hints: %RSI
assigning %vreg23 to %RSI: SIL [736r,784r:0)  0@736r

selectOrSplit GR32:%vreg20 [880r,896r:0)  0@880r w=inf
hints: %EAX
assigning %vreg20 to %EAX: AH [880r,896r:0)  0@880r AL [880r,896r:0)  0@880r

selectOrSplit GR32:%vreg18 [608r,624r:0)  0@608r w=inf
assigning %vreg18 to %EAX: AH [608r,624r:0)  0@608r AL [608r,624r:0)  0@608r

********** STACK TRANSFORMATION METADATA **********
********** Function: BZ2_bzwrite
********** REGISTER MAP **********
[%vreg1 -> %RBX] GR64
[%vreg3 -> %R15] GR64
[%vreg5 -> %R14D] GR32
[%vreg7 -> %RDI] GR64
[%vreg11 -> %ECX] GR32
[%vreg12 -> %RDX] GR64
[%vreg13 -> %RSI] GR64
[%vreg15 -> %RDI] GR64
[%vreg16 -> %RSI] GR64
[%vreg18 -> %EAX] GR32
[%vreg20 -> %EAX] GR32
[%vreg22 -> %RDI] GR64
[%vreg23 -> %RSI] GR64


Stackmap 0:
  STACKMAP 0, 0, %vreg1, 0, <fi#1>, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#4>, 0, %vreg5, 0, <fi#3>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack4](align=4) LD8[FixedStack3](align=4) LD8[FixedStack0](align=4) GR64:%vreg1,%vreg3 GR32:%vreg5

i8* %b: in register %RBX (vreg 1)
i8** %b.addr: in stack slot 1 (size: 8)
i8* %buf: in register %R15 (vreg 3)
i8** %buf.addr: in stack slot 2 (size: 8)
i32* %bzerr: in stack slot 4 (size: 4)
i32 %len: in register %R14D (vreg 5)
i32* %len.addr: in stack slot 3 (size: 4)
i32* %retval: in stack slot 0 (size: 4)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack4](align=4) LD8[FixedStack3](align=4) LD8[FixedStack0](align=4)

i32* %bzerr: in stack slot 4 (size: 4)
i32* %len.addr: in stack slot 3 (size: 4)
i32* %retval: in stack slot 0 (size: 4)

Duplicate operand locations:


Stackmap 2:
  STACKMAP 2, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)

i32* %retval: in stack slot 0 (size: 4)

Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, %vreg1, 0, <fi#1>, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#4>, 0, %vreg5, 0, <fi#3>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack4](align=4) LD8[FixedStack3](align=4) LD8[FixedStack0](align=4) GR64:%vreg1,%vreg3 GR32:%vreg5
  -> Call instruction SlotIndex 208B, searching vregs 0 -> 24 and stack slots -1 -> 5

  STACKMAP 1, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack4](align=4) LD8[FixedStack3](align=4) LD8[FixedStack0](align=4)
  -> Call instruction SlotIndex 480B, searching vregs 0 -> 24 and stack slots -1 -> 5

  STACKMAP 2, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
  -> Call instruction SlotIndex 800B, searching vregs 0 -> 24 and stack slots -1 -> 5

********** REWRITE VIRTUAL REGISTERS **********
********** Function: BZ2_bzwrite
********** REGISTER MAP **********
[%vreg1 -> %RBX] GR64
[%vreg3 -> %R15] GR64
[%vreg5 -> %R14D] GR32
[%vreg7 -> %RDI] GR64
[%vreg11 -> %ECX] GR32
[%vreg12 -> %RDX] GR64
[%vreg13 -> %RSI] GR64
[%vreg15 -> %RDI] GR64
[%vreg16 -> %RSI] GR64
[%vreg18 -> %EAX] GR32
[%vreg20 -> %EAX] GR32
[%vreg22 -> %RDI] GR64
[%vreg23 -> %RSI] GR64

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %EDX %RDI %RSI
16B		%vreg5<def> = COPY %EDX; GR32:%vreg5
32B		%vreg3<def> = COPY %RSI; GR64:%vreg3
48B		%vreg1<def> = COPY %RDI; GR64:%vreg1
112B		%vreg15<def> = MOV64ri <ga:@BZ2_bzwrite>; GR64:%vreg15
144B		%vreg16<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg16
160B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		%RDI<def> = COPY %vreg15<kill>; GR64:%vreg15
192B		%RSI<def> = COPY %vreg16<kill>; GR64:%vreg16
208B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
224B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
240B		%vreg7<def> = LEA64r <fi#4>, 1, %noreg, 0, %noreg; GR64:%vreg7
256B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
272B		STACKMAP 0, 0, %vreg1, 0, <fi#1>, 0, %vreg3, 0, <fi#2>, 0, 0, <fi#4>, 0, %vreg5, 0, <fi#3>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack4](align=4) LD8[FixedStack3](align=4) LD8[FixedStack0](align=4) GR64:%vreg1,%vreg3 GR32:%vreg5
288B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
304B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg1<kill>; mem:ST8[%b.addr] GR64:%vreg1
320B		MOV64mr <fi#2>, 1, %noreg, 0, %noreg, %vreg3<kill>; mem:ST8[%buf.addr] GR64:%vreg3
336B		MOV32mr <fi#3>, 1, %noreg, 0, %noreg, %vreg5<kill>; mem:ST4[%len.addr] GR32:%vreg5
352B		%vreg13<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr] GR64:%vreg13
368B		%vreg12<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%buf.addr] GR64:%vreg12
384B		%vreg11<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%len.addr] GR32:%vreg11
400B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
416B		%RDI<def> = COPY %vreg7<kill>; GR64:%vreg7
432B		%RSI<def> = COPY %vreg13<kill>; GR64:%vreg13
448B		%RDX<def> = COPY %vreg12<kill>; GR64:%vreg12
464B		%ECX<def> = COPY %vreg11<kill>; GR32:%vreg11
480B		CALL64pcrel32 <ga:@BZ2_bzWrite>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %RDX<imp-use>, %ECX<imp-use>
496B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
512B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
528B		STACKMAP 1, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack4](align=4) LD8[FixedStack3](align=4) LD8[FixedStack0](align=4)
544B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
560B		CMP32mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%bzerr]
576B		JNE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1
> %R14D<def> = COPY %EDX
> %R15<def> = COPY %RSI
> %RBX<def> = COPY %RDI
> %RDI<def> = MOV64ri <ga:@BZ2_bzwrite>
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = LEA64r <fi#4>, 1, %noreg, 0, %noreg
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 0, 0, %RBX, 0, <fi#1>, 0, %R15, 0, <fi#2>, 0, 0, <fi#4>, 0, %R14D, 0, <fi#3>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1] LD8[FixedStack2] LD8[FixedStack4](align=4) LD8[FixedStack3](align=4) LD8[FixedStack0](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %RBX<kill>; mem:ST8[%b.addr]
> MOV64mr <fi#2>, 1, %noreg, 0, %noreg, %R15<kill>; mem:ST8[%buf.addr]
> MOV32mr <fi#3>, 1, %noreg, 0, %noreg, %R14D<kill>; mem:ST4[%len.addr]
> %RSI<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr]
> %RDX<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%buf.addr]
> %ECX<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%len.addr]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> %RDX<def> = COPY %RDX<kill>
Deleting identity copy.
> %ECX<def> = COPY %ECX<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@BZ2_bzWrite>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %RDX<imp-use>, %ECX<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 1, 0, 0, <fi#4>, 0, 0, <fi#3>, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack4](align=4) LD8[FixedStack3](align=4) LD8[FixedStack0](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> CMP32mi8 <fi#4>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%bzerr]
> JNE_1 <BB#2>, %EFLAGS<imp-use,kill>
592B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
608B		%vreg18<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%len.addr] GR32:%vreg18
624B		MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %vreg18<kill>; mem:ST4[%retval] GR32:%vreg18
640B		JMP_1 <BB#3>
	    Successors according to CFG: BB#3
> %EAX<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD4[%len.addr]
> MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%retval]
> JMP_1 <BB#3>
656B	BB#2: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#0
672B		MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -1; mem:ST4[%retval]
	    Successors according to CFG: BB#3
> MOV32mi <fi#0>, 1, %noreg, 0, %noreg, -1; mem:ST4[%retval]
688B	BB#3: derived from LLVM BB %return
	    Predecessors according to CFG: BB#2 BB#1
704B		%vreg22<def> = MOV64ri <ga:@BZ2_bzwrite>; GR64:%vreg22
736B		%vreg23<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg23
752B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
768B		%RDI<def> = COPY %vreg22<kill>; GR64:%vreg22
784B		%RSI<def> = COPY %vreg23<kill>; GR64:%vreg23
800B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
816B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
832B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
848B		STACKMAP 2, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
864B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
880B		%vreg20<def> = MOV32rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD4[%retval] GR32:%vreg20
896B		%EAX<def> = COPY %vreg20<kill>; GR32:%vreg20
912B		RETQ %EAX<imp-use>
> %RDI<def> = MOV64ri <ga:@BZ2_bzwrite>
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 2, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def> = MOV32rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD4[%retval]
> %EAX<def> = COPY %EAX<kill>
Deleting identity copy.
> RETQ %EAX<imp-use>
Computing live-in reg-units in ABI blocks.
0B	BB#0 DIL#0
Created 1 new intervals.
********** INTERVALS **********
DIL [0B,16r:0)[112r,144r:1)[304r,336r:2)  0@0B-phi 1@112r 2@304r
%vreg0 [16r,32r:0)  0@16r
%vreg1 [32r,256r:0)  0@32r
%vreg2 [368r,432r:0)  0@368r
%vreg3 [176r,192r:0)  0@176r
%vreg4 [192r,304r:0)  0@192r
%vreg5 [272r,320r:0)  0@272r
%vreg6 [48r,64r:0)  0@48r
%vreg7 [64r,112r:0)  0@64r
%vreg8 [80r,128r:0)  0@80r
RegMasks: 144r 336r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzflush: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=8, align=8, at location [SP+8]
Function Live Ins: %RDI in %vreg0

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI
16B		%vreg0<def> = COPY %RDI; GR64:%vreg0
32B		%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
48B		%vreg6<def> = MOV64ri <ga:@BZ2_bzflush>; GR64:%vreg6
64B		%vreg7<def> = COPY %vreg6; GR64:%vreg7,%vreg6
80B		%vreg8<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg8
96B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
112B		%RDI<def> = COPY %vreg7; GR64:%vreg7
128B		%RSI<def> = COPY %vreg8; GR64:%vreg8
144B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
160B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		%vreg3<def> = MOV64ri <ga:@BZ2_bzflush>; GR64:%vreg3
192B		%vreg4<def> = COPY %vreg3; GR64:%vreg4,%vreg3
208B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0] GR64:%vreg1
240B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
256B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%b.addr] GR64:%vreg1
272B		%vreg5<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg5
288B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
304B		%RDI<def> = COPY %vreg4; GR64:%vreg4
320B		%RSI<def> = COPY %vreg5; GR64:%vreg5
336B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
352B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
368B		%vreg2<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg2
384B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
400B		STACKMAP 1, 0, ...
416B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
432B		%EAX<def> = COPY %vreg2; GR32:%vreg2
448B		RETQ %EAX<imp-use,kill>

# End machine code for function BZ2_bzflush.

********** SIMPLE REGISTER COALESCING **********
********** Function: BZ2_bzflush
********** JOINING INTERVALS ***********
entry:
16B	%vreg0<def> = COPY %RDI; GR64:%vreg0
	Considering merging %vreg0 with %RDI
	Can only merge into reserved registers.
112B	%RDI<def> = COPY %vreg7; GR64:%vreg7
	Considering merging %vreg7 with %RDI
	Can only merge into reserved registers.
128B	%RSI<def> = COPY %vreg8; GR64:%vreg8
	Considering merging %vreg8 with %RSI
	Can only merge into reserved registers.
304B	%RDI<def> = COPY %vreg4; GR64:%vreg4
	Considering merging %vreg4 with %RDI
	Can only merge into reserved registers.
320B	%RSI<def> = COPY %vreg5; GR64:%vreg5
	Considering merging %vreg5 with %RSI
	Can only merge into reserved registers.
432B	%EAX<def> = COPY %vreg2; GR32:%vreg2
	Considering merging %vreg2 with %EAX
	Can only merge into reserved registers.
Remat: %EAX<def> = MOV32r0 %EFLAGS<imp-def,dead>
Shrink: %vreg2 [368r,432r:0)  0@368r
All defs dead: 368r	%vreg2<def,dead> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg2
Shrunk: %vreg2 [368r,368d:0)  0@368r
Deleting dead def 368r	%vreg2<def,dead> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg2
32B	%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
	Considering merging to GR64 with %vreg0 in %vreg1
		RHS = %vreg0 [16r,32r:0)  0@16r
		LHS = %vreg1 [32r,256r:0)  0@32r
		merge %vreg1:0@32r into %vreg0:0@16r --> @16r
		erased:	32r	%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
		updated: 16B	%vreg1<def> = COPY %RDI; GR64:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [16r,256r:0)  0@16r
64B	%vreg7<def> = COPY %vreg6; GR64:%vreg7,%vreg6
	Considering merging to GR64 with %vreg6 in %vreg7
		RHS = %vreg6 [48r,64r:0)  0@48r
		LHS = %vreg7 [64r,112r:0)  0@64r
		merge %vreg7:0@64r into %vreg6:0@48r --> @48r
		erased:	64r	%vreg7<def> = COPY %vreg6; GR64:%vreg7,%vreg6
		updated: 48B	%vreg7<def> = MOV64ri <ga:@BZ2_bzflush>; GR64:%vreg7
	Success: %vreg6 -> %vreg7
	Result = %vreg7 [48r,112r:0)  0@48r
192B	%vreg4<def> = COPY %vreg3; GR64:%vreg4,%vreg3
	Considering merging to GR64 with %vreg3 in %vreg4
		RHS = %vreg3 [176r,192r:0)  0@176r
		LHS = %vreg4 [192r,304r:0)  0@192r
		merge %vreg4:0@192r into %vreg3:0@176r --> @176r
		erased:	192r	%vreg4<def> = COPY %vreg3; GR64:%vreg4,%vreg3
		updated: 176B	%vreg4<def> = MOV64ri <ga:@BZ2_bzflush>; GR64:%vreg4
	Success: %vreg3 -> %vreg4
	Result = %vreg4 [176r,304r:0)  0@176r
112B	%RDI<def> = COPY %vreg7; GR64:%vreg7
	Considering merging %vreg7 with %RDI
	Can only merge into reserved registers.
304B	%RDI<def> = COPY %vreg4; GR64:%vreg4
	Considering merging %vreg4 with %RDI
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
DIL [0B,16r:0)[112r,144r:1)[304r,336r:2)  0@0B-phi 1@112r 2@304r
%vreg1 [16r,256r:0)  0@16r
%vreg4 [176r,304r:0)  0@176r
%vreg5 [272r,320r:0)  0@272r
%vreg7 [48r,112r:0)  0@48r
%vreg8 [80r,128r:0)  0@80r
RegMasks: 144r 336r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzflush: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=8, align=8, at location [SP+8]
Function Live Ins: %RDI in %vreg0

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI
16B		%vreg1<def> = COPY %RDI; GR64:%vreg1
48B		%vreg7<def> = MOV64ri <ga:@BZ2_bzflush>; GR64:%vreg7
80B		%vreg8<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg8
96B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
112B		%RDI<def> = COPY %vreg7; GR64:%vreg7
128B		%RSI<def> = COPY %vreg8; GR64:%vreg8
144B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
160B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		%vreg4<def> = MOV64ri <ga:@BZ2_bzflush>; GR64:%vreg4
208B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0] GR64:%vreg1
240B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
256B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%b.addr] GR64:%vreg1
272B		%vreg5<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg5
288B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
304B		%RDI<def> = COPY %vreg4; GR64:%vreg4
320B		%RSI<def> = COPY %vreg5; GR64:%vreg5
336B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
352B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
384B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
400B		STACKMAP 1, 0, ...
416B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
432B		%EAX<def> = MOV32r0 %EFLAGS<imp-def,dead>
448B		RETQ %EAX<imp-use,kill>

# End machine code for function BZ2_bzflush.

********** GREEDY REGISTER ALLOCATION **********
********** Function: BZ2_bzflush
********** INTERVALS **********
DIL [0B,16r:0)[112r,144r:1)[304r,336r:2)  0@0B-phi 1@112r 2@304r
%vreg1 [16r,256r:0)  0@16r
%vreg4 [176r,304r:0)  0@176r
%vreg5 [272r,320r:0)  0@272r
%vreg7 [48r,112r:0)  0@48r
%vreg8 [80r,128r:0)  0@80r
RegMasks: 144r 336r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzflush: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=8, align=8, at location [SP+8]
Function Live Ins: %RDI in %vreg0

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI
16B		%vreg1<def> = COPY %RDI; GR64:%vreg1
48B		%vreg7<def> = MOV64ri <ga:@BZ2_bzflush>; GR64:%vreg7
80B		%vreg8<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg8
96B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
112B		%RDI<def> = COPY %vreg7; GR64:%vreg7
128B		%RSI<def> = COPY %vreg8; GR64:%vreg8
144B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
160B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		%vreg4<def> = MOV64ri <ga:@BZ2_bzflush>; GR64:%vreg4
208B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0] GR64:%vreg1
240B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
256B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%b.addr] GR64:%vreg1
272B		%vreg5<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg5
288B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
304B		%RDI<def> = COPY %vreg4; GR64:%vreg4
320B		%RSI<def> = COPY %vreg5; GR64:%vreg5
336B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
352B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
384B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
400B		STACKMAP 1, 0, ...
416B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
432B		%EAX<def> = MOV32r0 %EFLAGS<imp-def,dead>
448B		RETQ %EAX<imp-use,kill>

# End machine code for function BZ2_bzflush.


selectOrSplit GR64:%vreg1 [16r,256r:0)  0@16r w=4.734375e-03
hints: %RDI
missed hint %RDI
assigning %vreg1 to %RBX: BH [16r,256r:0)  0@16r BL [16r,256r:0)  0@16r

selectOrSplit GR64:%vreg7 [48r,112r:0)  0@48r w=2.176724e-03
hints: %RDI
assigning %vreg7 to %RDI: DIL [48r,112r:0)  0@48r

selectOrSplit GR64:%vreg8 [80r,128r:0)  0@80r w=4.508928e-03
hints: %RSI
assigning %vreg8 to %RSI: SIL [80r,128r:0)  0@80r

selectOrSplit GR64:%vreg4 [176r,304r:0)  0@176r w=1.912879e-03
hints: %RDI
assigning %vreg4 to %RDI: DIL [176r,304r:0)  0@176r

selectOrSplit GR64:%vreg5 [272r,320r:0)  0@272r w=4.508928e-03
hints: %RSI
assigning %vreg5 to %RSI: SIL [272r,320r:0)  0@272r

********** STACK TRANSFORMATION METADATA **********
********** Function: BZ2_bzflush
********** REGISTER MAP **********
[%vreg1 -> %RBX] GR64
[%vreg4 -> %RDI] GR64
[%vreg5 -> %RSI] GR64
[%vreg7 -> %RDI] GR64
[%vreg8 -> %RSI] GR64


Stackmap 0:
  STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0] GR64:%vreg1

i8* %b: in register %RBX (vreg 1)
i8** %b.addr: in stack slot 0 (size: 8)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, ...


Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0] GR64:%vreg1
  -> Call instruction SlotIndex 144B, searching vregs 0 -> 9 and stack slots -1 -> 1

  STACKMAP 1, 0, ...
  -> Call instruction SlotIndex 336B, searching vregs 0 -> 9 and stack slots -1 -> 1

********** REWRITE VIRTUAL REGISTERS **********
********** Function: BZ2_bzflush
********** REGISTER MAP **********
[%vreg1 -> %RBX] GR64
[%vreg4 -> %RDI] GR64
[%vreg5 -> %RSI] GR64
[%vreg7 -> %RDI] GR64
[%vreg8 -> %RSI] GR64

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI
16B		%vreg1<def> = COPY %RDI; GR64:%vreg1
48B		%vreg7<def> = MOV64ri <ga:@BZ2_bzflush>; GR64:%vreg7
80B		%vreg8<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg8
96B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
112B		%RDI<def> = COPY %vreg7<kill>; GR64:%vreg7
128B		%RSI<def> = COPY %vreg8<kill>; GR64:%vreg8
144B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
160B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		%vreg4<def> = MOV64ri <ga:@BZ2_bzflush>; GR64:%vreg4
208B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0] GR64:%vreg1
240B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
256B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1<kill>; mem:ST8[%b.addr] GR64:%vreg1
272B		%vreg5<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg5
288B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
304B		%RDI<def> = COPY %vreg4<kill>; GR64:%vreg4
320B		%RSI<def> = COPY %vreg5<kill>; GR64:%vreg5
336B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
352B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
384B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
400B		STACKMAP 1, 0, ...
416B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
432B		%EAX<def> = MOV32r0 %EFLAGS<imp-def,dead>
448B		RETQ %EAX<imp-use,kill>
> %RBX<def> = COPY %RDI
> %RDI<def> = MOV64ri <ga:@BZ2_bzflush>
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = MOV64ri <ga:@BZ2_bzflush>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 0, 0, %RBX, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %RBX<kill>; mem:ST8[%b.addr]
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 1, 0, ...
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def> = MOV32r0 %EFLAGS<imp-def,dead>
> RETQ %EAX<imp-use,kill>
Computing live-in reg-units in ABI blocks.
0B	BB#0 DIL#0
Created 1 new intervals.
********** INTERVALS **********
DIL [0B,16r:0)[112r,144r:6)[528r,608r:4)[816r,896r:3)[1072r,1104r:5)[1360r,1376r:2)[1552r,1584r:1)  0@0B-phi 1@1552r 2@1360r 3@816r 4@528r 5@1072r 6@112r
%vreg0 [16r,32r:0)  0@16r
%vreg1 [32r,224r:0)  0@32r
%vreg5 [256r,272r:0)  0@256r
%vreg6 [240r,256r:0)  0@240r
%vreg7 [48r,64r:0)  0@48r
%vreg8 [64r,112r:0)  0@64r
%vreg9 [80r,128r:0)  0@80r
%vreg12 [368r,384r:0)  0@368r
%vreg13 [1024r,1072r:0)  0@1024r
%vreg15 [1040r,1088r:0)  0@1040r
%vreg17 [432r,528r:0)  0@432r
%vreg19 [448r,560r:0)  0@448r
%vreg20 [464r,480r:0)  0@464r
%vreg21 [480r,592r:0)  0@480r
%vreg22 [496r,544r:0)  0@496r
%vreg23 [736r,752r:0)  0@736r
%vreg24 [752r,880r:0)  0@752r
%vreg26 [768r,848r:0)  0@768r
%vreg27 [784r,832r:0)  0@784r
%vreg30 [1200r,1216r:0)  0@1200r
%vreg33 [1264r,1280r:0)  0@1264r
%vreg35 [1408r,1408d:0)  0@1408r
%vreg36 [1328r,1360r:0)  0@1328r
%vreg37 [1488r,1504r:0)  0@1488r
%vreg38 [1504r,1552r:0)  0@1504r
%vreg39 [1520r,1568r:0)  0@1520r
RegMasks: 144r 608r 896r 1104r 1376r 1584r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzclose: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=8, align=8, at location [SP+8]
  fi#1: size=4, align=4, at location [SP+8]
  fi#2: size=8, align=8, at location [SP+8]
Function Live Ins: %RDI in %vreg0

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI
16B		%vreg0<def> = COPY %RDI; GR64:%vreg0
32B		%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
48B		%vreg7<def> = MOV64ri <ga:@BZ2_bzclose>; GR64:%vreg7
64B		%vreg8<def> = COPY %vreg7; GR64:%vreg8,%vreg7
80B		%vreg9<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg9
96B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
112B		%RDI<def> = COPY %vreg8; GR64:%vreg8
128B		%RSI<def> = COPY %vreg9; GR64:%vreg9
144B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
160B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
192B		STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, ...; mem:LD8[FixedStack0] LD8[FixedStack1](align=4) LD8[FixedStack2] GR64:%vreg1
208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%b.addr] GR64:%vreg1
240B		%vreg6<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr] GR64:%vreg6
256B		%vreg5<def> = MOV64rm %vreg6, 1, %noreg, 0, %noreg; mem:LD8[%handle] GR64:%vreg5,%vreg6
272B		MOV64mr <fi#2>, 1, %noreg, 0, %noreg, %vreg5; mem:ST8[%fp] GR64:%vreg5
288B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%b.addr]
304B		JNE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

320B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
336B		JMP_1 <BB#10>
	    Successors according to CFG: BB#10

352B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0
368B		%vreg12<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr] GR64:%vreg12
384B		CMP8mi %vreg12, 1, %noreg, 5012, %noreg, 0, %EFLAGS<imp-def>; mem:LD1[%writing] GR64:%vreg12
400B		JE_1 <BB#6>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#6 BB#3

416B	BB#3: derived from LLVM BB %if.then.1
	    Predecessors according to CFG: BB#2
432B		%vreg17<def> = LEA64r <fi#1>, 1, %noreg, 0, %noreg; GR64:%vreg17
448B		%vreg19<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg19
464B		%vreg20<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg20
480B		%vreg21<def> = SUBREG_TO_REG 0, %vreg20, 4; GR64:%vreg21 GR32:%vreg20
496B		%vreg22<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr] GR64:%vreg22
512B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
528B		%RDI<def> = COPY %vreg17; GR64:%vreg17
544B		%RSI<def> = COPY %vreg22; GR64:%vreg22
560B		%EDX<def> = COPY %vreg19; GR32:%vreg19
576B		%RCX<def> = COPY %vreg21; GR64:%vreg21
592B		%R8<def> = COPY %vreg21; GR64:%vreg21
608B		CALL64pcrel32 <ga:@BZ2_bzWriteClose>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>, %EDX<imp-use,kill>, %RCX<imp-use,kill>, %R8<imp-use,kill>
624B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
640B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
656B		STACKMAP 1, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, ...; mem:LD8[FixedStack0] LD8[FixedStack1](align=4) LD8[FixedStack2]
672B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
688B		CMP32mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%bzerr]
704B		JE_1 <BB#5>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#5 BB#4

720B	BB#4: derived from LLVM BB %if.then.3
	    Predecessors according to CFG: BB#3
736B		%vreg23<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg23
752B		%vreg24<def> = SUBREG_TO_REG 0, %vreg23, 4; GR64:%vreg24 GR32:%vreg23
768B		%vreg26<def> = MOV32ri 1; GR32:%vreg26
784B		%vreg27<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr] GR64:%vreg27
800B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
816B		%RDI<def> = COPY %vreg24; GR64:%vreg24
832B		%RSI<def> = COPY %vreg27; GR64:%vreg27
848B		%EDX<def> = COPY %vreg26; GR32:%vreg26
864B		%RCX<def> = COPY %vreg24; GR64:%vreg24
880B		%R8<def> = COPY %vreg24; GR64:%vreg24
896B		CALL64pcrel32 <ga:@BZ2_bzWriteClose>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>, %EDX<imp-use,kill>, %RCX<imp-use,kill>, %R8<imp-use,kill>
912B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
928B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
944B		STACKMAP 2, 0, 0, <fi#2>, 0, ...; mem:LD8[FixedStack2]
960B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#5

976B	BB#5: derived from LLVM BB %if.end.4
	    Predecessors according to CFG: BB#3 BB#4
992B		JMP_1 <BB#7>
	    Successors according to CFG: BB#7

1008B	BB#6: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#2
1024B		%vreg13<def> = LEA64r <fi#1>, 1, %noreg, 0, %noreg; GR64:%vreg13
1040B		%vreg15<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr] GR64:%vreg15
1056B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1072B		%RDI<def> = COPY %vreg13; GR64:%vreg13
1088B		%RSI<def> = COPY %vreg15; GR64:%vreg15
1104B		CALL64pcrel32 <ga:@BZ2_bzReadClose>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
1120B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1136B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1152B		STACKMAP 3, 0, 0, <fi#2>, 0, ...; mem:LD8[FixedStack2]
1168B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#7

1184B	BB#7: derived from LLVM BB %if.end.5
	    Predecessors according to CFG: BB#6 BB#5
1200B		%vreg30<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%fp] GR64:%vreg30
1216B		CMP64rm %vreg30, %noreg, 1, %noreg, <ga:@stdin>, %noreg, %EFLAGS<imp-def>; mem:LD8[@stdin] GR64:%vreg30
1232B		JE_1 <BB#10>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#10 BB#8

1248B	BB#8: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#7
1264B		%vreg33<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%fp] GR64:%vreg33
1280B		CMP64rm %vreg33, %noreg, 1, %noreg, <ga:@stdout>, %noreg, %EFLAGS<imp-def>; mem:LD8[@stdout] GR64:%vreg33
1296B		JE_1 <BB#10>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#10 BB#9

1312B	BB#9: derived from LLVM BB %if.then.8
	    Predecessors according to CFG: BB#8
1328B		%vreg36<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%fp] GR64:%vreg36
1344B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1360B		%RDI<def> = COPY %vreg36; GR64:%vreg36
1376B		CALL64pcrel32 <ga:@fclose>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
1392B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1408B		%vreg35<def,dead> = COPY %EAX<kill>; GR32:%vreg35
1424B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1440B		STACKMAP 4, 0, ...
1456B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#10

1472B	BB#10: derived from LLVM BB %if.end.9
	    Predecessors according to CFG: BB#7 BB#8 BB#9 BB#1
1488B		%vreg37<def> = MOV64ri <ga:@BZ2_bzclose>; GR64:%vreg37
1504B		%vreg38<def> = COPY %vreg37; GR64:%vreg38,%vreg37
1520B		%vreg39<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg39
1536B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1552B		%RDI<def> = COPY %vreg38; GR64:%vreg38
1568B		%RSI<def> = COPY %vreg39; GR64:%vreg39
1584B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
1600B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1616B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1632B		STACKMAP 5, 0, ...
1648B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1664B		RETQ

# End machine code for function BZ2_bzclose.

********** SIMPLE REGISTER COALESCING **********
********** Function: BZ2_bzclose
********** JOINING INTERVALS ***********
if.end.5:
if.end.9:
1552B	%RDI<def> = COPY %vreg38; GR64:%vreg38
	Considering merging %vreg38 with %RDI
	Can only merge into reserved registers.
1568B	%RSI<def> = COPY %vreg39; GR64:%vreg39
	Considering merging %vreg39 with %RSI
	Can only merge into reserved registers.
if.end:
if.then.1:
480B	%vreg21<def> = SUBREG_TO_REG 0, %vreg20, 4; GR64:%vreg21 GR32:%vreg20
	Considering merging to GR64_with_sub_8bit with %vreg20 in %vreg21:sub_32bit
		RHS = %vreg20 [464r,480r:0)  0@464r
		LHS = %vreg21 [480r,592r:0)  0@480r
		merge %vreg21:0@480r into %vreg20:0@464r --> @464r
		erased:	480r	%vreg21<def> = SUBREG_TO_REG 0, %vreg20, 4; GR64:%vreg21 GR32:%vreg20
		updated: 464B	%vreg21:sub_32bit<def,read-undef> = MOV32r0 %EFLAGS<imp-def,dead>; GR64_with_sub_8bit:%vreg21
	Success: %vreg20:sub_32bit -> %vreg21
	Result = %vreg21 [464r,592r:0)  0@464r
528B	%RDI<def> = COPY %vreg17; GR64:%vreg17
	Considering merging %vreg17 with %RDI
	Can only merge into reserved registers.
544B	%RSI<def> = COPY %vreg22; GR64:%vreg22
	Considering merging %vreg22 with %RSI
	Can only merge into reserved registers.
560B	%EDX<def> = COPY %vreg19; GR32:%vreg19
	Considering merging %vreg19 with %EDX
	Can only merge into reserved registers.
Remat: %EDX<def> = MOV32r0 %EFLAGS<imp-def,dead>
Shrink: %vreg19 [448r,560r:0)  0@448r
All defs dead: 448r	%vreg19<def,dead> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg19
Shrunk: %vreg19 [448r,448d:0)  0@448r
Deleting dead def 448r	%vreg19<def,dead> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg19
576B	%RCX<def> = COPY %vreg21; GR64_with_sub_8bit:%vreg21
	Considering merging %vreg21 with %RCX
	Can only merge into reserved registers.
Remat: %ECX<def,dead> = MOV32r0 %EFLAGS<imp-def,dead>, %RCX<imp-def>
Shrink: %vreg21 [464r,592r:0)  0@464r
Shrunk: %vreg21 [464r,592r:0)  0@464r
592B	%R8<def> = COPY %vreg21; GR64_with_sub_8bit:%vreg21
	Considering merging %vreg21 with %R8
	Can only merge into reserved registers.
Remat: %R8D<def,dead> = MOV32r0 %EFLAGS<imp-def,dead>, %R8<imp-def>
Shrink: %vreg21 [464r,592r:0)  0@464r
All defs dead: 464r	%vreg21:sub_32bit<def,read-undef,dead> = MOV32r0 %EFLAGS<imp-def,dead>; GR64_with_sub_8bit:%vreg21
Shrunk: %vreg21 [464r,464d:0)  0@464r
Deleting dead def 464r	%vreg21:sub_32bit<def,read-undef,dead> = MOV32r0 %EFLAGS<imp-def,dead>; GR64_with_sub_8bit:%vreg21
if.end.4:
land.lhs.true:
entry:
16B	%vreg0<def> = COPY %RDI; GR64:%vreg0
	Considering merging %vreg0 with %RDI
	Can only merge into reserved registers.
112B	%RDI<def> = COPY %vreg8; GR64:%vreg8
	Considering merging %vreg8 with %RDI
	Can only merge into reserved registers.
128B	%RSI<def> = COPY %vreg9; GR64:%vreg9
	Considering merging %vreg9 with %RSI
	Can only merge into reserved registers.
if.then:
if.then.3:
752B	%vreg24<def> = SUBREG_TO_REG 0, %vreg23, 4; GR64:%vreg24 GR32:%vreg23
	Considering merging to GR64_with_sub_8bit with %vreg23 in %vreg24:sub_32bit
		RHS = %vreg23 [736r,752r:0)  0@736r
		LHS = %vreg24 [752r,880r:0)  0@752r
		merge %vreg24:0@752r into %vreg23:0@736r --> @736r
		erased:	752r	%vreg24<def> = SUBREG_TO_REG 0, %vreg23, 4; GR64:%vreg24 GR32:%vreg23
		updated: 736B	%vreg24:sub_32bit<def,read-undef> = MOV32r0 %EFLAGS<imp-def,dead>; GR64_with_sub_8bit:%vreg24
	Success: %vreg23:sub_32bit -> %vreg24
	Result = %vreg24 [736r,880r:0)  0@736r
816B	%RDI<def> = COPY %vreg24; GR64_with_sub_8bit:%vreg24
	Considering merging %vreg24 with %RDI
	Can only merge into reserved registers.
Remat: %EDI<def,dead> = MOV32r0 %EFLAGS<imp-def,dead>, %RDI<imp-def>
Shrink: %vreg24 [736r,880r:0)  0@736r
Shrunk: %vreg24 [736r,880r:0)  0@736r
832B	%RSI<def> = COPY %vreg27; GR64:%vreg27
	Considering merging %vreg27 with %RSI
	Can only merge into reserved registers.
848B	%EDX<def> = COPY %vreg26; GR32:%vreg26
	Considering merging %vreg26 with %EDX
	Can only merge into reserved registers.
Remat: %EDX<def> = MOV32ri 1
Shrink: %vreg26 [768r,848r:0)  0@768r
All defs dead: 768r	%vreg26<def,dead> = MOV32ri 1; GR32:%vreg26
Shrunk: %vreg26 [768r,768d:0)  0@768r
Deleting dead def 768r	%vreg26<def,dead> = MOV32ri 1; GR32:%vreg26
864B	%RCX<def> = COPY %vreg24; GR64_with_sub_8bit:%vreg24
	Considering merging %vreg24 with %RCX
	Can only merge into reserved registers.
Remat: %ECX<def,dead> = MOV32r0 %EFLAGS<imp-def,dead>, %RCX<imp-def>
Shrink: %vreg24 [736r,880r:0)  0@736r
Shrunk: %vreg24 [736r,880r:0)  0@736r
880B	%R8<def> = COPY %vreg24; GR64_with_sub_8bit:%vreg24
	Considering merging %vreg24 with %R8
	Can only merge into reserved registers.
Remat: %R8D<def,dead> = MOV32r0 %EFLAGS<imp-def,dead>, %R8<imp-def>
Shrink: %vreg24 [736r,880r:0)  0@736r
All defs dead: 736r	%vreg24:sub_32bit<def,read-undef,dead> = MOV32r0 %EFLAGS<imp-def,dead>; GR64_with_sub_8bit:%vreg24
Shrunk: %vreg24 [736r,736d:0)  0@736r
Deleting dead def 736r	%vreg24:sub_32bit<def,read-undef,dead> = MOV32r0 %EFLAGS<imp-def,dead>; GR64_with_sub_8bit:%vreg24
if.else:
1072B	%RDI<def> = COPY %vreg13; GR64:%vreg13
	Considering merging %vreg13 with %RDI
	Can only merge into reserved registers.
1088B	%RSI<def> = COPY %vreg15; GR64:%vreg15
	Considering merging %vreg15 with %RSI
	Can only merge into reserved registers.
if.then.8:
1360B	%RDI<def> = COPY %vreg36; GR64:%vreg36
	Considering merging %vreg36 with %RDI
	Can only merge into reserved registers.
1408B	%vreg35<def,dead> = COPY %EAX<kill>; GR32:%vreg35
	Considering merging %vreg35 with %EAX
	Can only merge into reserved registers.
1504B	%vreg38<def> = COPY %vreg37; GR64:%vreg38,%vreg37
	Considering merging to GR64 with %vreg37 in %vreg38
		RHS = %vreg37 [1488r,1504r:0)  0@1488r
		LHS = %vreg38 [1504r,1552r:0)  0@1504r
		merge %vreg38:0@1504r into %vreg37:0@1488r --> @1488r
		erased:	1504r	%vreg38<def> = COPY %vreg37; GR64:%vreg38,%vreg37
		updated: 1488B	%vreg38<def> = MOV64ri <ga:@BZ2_bzclose>; GR64:%vreg38
	Success: %vreg37 -> %vreg38
	Result = %vreg38 [1488r,1552r:0)  0@1488r
32B	%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
	Considering merging to GR64 with %vreg0 in %vreg1
		RHS = %vreg0 [16r,32r:0)  0@16r
		LHS = %vreg1 [32r,224r:0)  0@32r
		merge %vreg1:0@32r into %vreg0:0@16r --> @16r
		erased:	32r	%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
		updated: 16B	%vreg1<def> = COPY %RDI; GR64:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [16r,224r:0)  0@16r
64B	%vreg8<def> = COPY %vreg7; GR64:%vreg8,%vreg7
	Considering merging to GR64 with %vreg7 in %vreg8
		RHS = %vreg7 [48r,64r:0)  0@48r
		LHS = %vreg8 [64r,112r:0)  0@64r
		merge %vreg8:0@64r into %vreg7:0@48r --> @48r
		erased:	64r	%vreg8<def> = COPY %vreg7; GR64:%vreg8,%vreg7
		updated: 48B	%vreg8<def> = MOV64ri <ga:@BZ2_bzclose>; GR64:%vreg8
	Success: %vreg7 -> %vreg8
	Result = %vreg8 [48r,112r:0)  0@48r
1552B	%RDI<def> = COPY %vreg38; GR64:%vreg38
	Considering merging %vreg38 with %RDI
	Can only merge into reserved registers.
112B	%RDI<def> = COPY %vreg8; GR64:%vreg8
	Considering merging %vreg8 with %RDI
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
DIL [0B,16r:0)[112r,144r:6)[528r,608r:4)[816r,896r:3)[1072r,1104r:5)[1360r,1376r:2)[1552r,1584r:1)  0@0B-phi 1@1552r 2@1360r 3@816r 4@528r 5@1072r 6@112r
%vreg1 [16r,224r:0)  0@16r
%vreg5 [256r,272r:0)  0@256r
%vreg6 [240r,256r:0)  0@240r
%vreg8 [48r,112r:0)  0@48r
%vreg9 [80r,128r:0)  0@80r
%vreg12 [368r,384r:0)  0@368r
%vreg13 [1024r,1072r:0)  0@1024r
%vreg15 [1040r,1088r:0)  0@1040r
%vreg17 [432r,528r:0)  0@432r
%vreg22 [496r,544r:0)  0@496r
%vreg27 [784r,832r:0)  0@784r
%vreg30 [1200r,1216r:0)  0@1200r
%vreg33 [1264r,1280r:0)  0@1264r
%vreg35 [1408r,1408d:0)  0@1408r
%vreg36 [1328r,1360r:0)  0@1328r
%vreg38 [1488r,1552r:0)  0@1488r
%vreg39 [1520r,1568r:0)  0@1520r
RegMasks: 144r 608r 896r 1104r 1376r 1584r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzclose: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=8, align=8, at location [SP+8]
  fi#1: size=4, align=4, at location [SP+8]
  fi#2: size=8, align=8, at location [SP+8]
Function Live Ins: %RDI in %vreg0

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI
16B		%vreg1<def> = COPY %RDI; GR64:%vreg1
48B		%vreg8<def> = MOV64ri <ga:@BZ2_bzclose>; GR64:%vreg8
80B		%vreg9<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg9
96B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
112B		%RDI<def> = COPY %vreg8; GR64:%vreg8
128B		%RSI<def> = COPY %vreg9; GR64:%vreg9
144B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
160B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
192B		STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, ...; mem:LD8[FixedStack0] LD8[FixedStack1](align=4) LD8[FixedStack2] GR64:%vreg1
208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%b.addr] GR64:%vreg1
240B		%vreg6<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr] GR64:%vreg6
256B		%vreg5<def> = MOV64rm %vreg6, 1, %noreg, 0, %noreg; mem:LD8[%handle] GR64:%vreg5,%vreg6
272B		MOV64mr <fi#2>, 1, %noreg, 0, %noreg, %vreg5; mem:ST8[%fp] GR64:%vreg5
288B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%b.addr]
304B		JNE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

320B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
336B		JMP_1 <BB#10>
	    Successors according to CFG: BB#10

352B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0
368B		%vreg12<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr] GR64:%vreg12
384B		CMP8mi %vreg12, 1, %noreg, 5012, %noreg, 0, %EFLAGS<imp-def>; mem:LD1[%writing] GR64:%vreg12
400B		JE_1 <BB#6>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#6 BB#3

416B	BB#3: derived from LLVM BB %if.then.1
	    Predecessors according to CFG: BB#2
432B		%vreg17<def> = LEA64r <fi#1>, 1, %noreg, 0, %noreg; GR64:%vreg17
496B		%vreg22<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr] GR64:%vreg22
512B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
528B		%RDI<def> = COPY %vreg17; GR64:%vreg17
544B		%RSI<def> = COPY %vreg22; GR64:%vreg22
560B		%EDX<def> = MOV32r0 %EFLAGS<imp-def,dead>
576B		%ECX<def,dead> = MOV32r0 %EFLAGS<imp-def,dead>, %RCX<imp-def>
592B		%R8D<def,dead> = MOV32r0 %EFLAGS<imp-def,dead>, %R8<imp-def>
608B		CALL64pcrel32 <ga:@BZ2_bzWriteClose>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>, %EDX<imp-use,kill>, %RCX<imp-use,kill>, %R8<imp-use,kill>
624B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
640B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
656B		STACKMAP 1, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, ...; mem:LD8[FixedStack0] LD8[FixedStack1](align=4) LD8[FixedStack2]
672B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
688B		CMP32mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%bzerr]
704B		JE_1 <BB#5>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#5 BB#4

720B	BB#4: derived from LLVM BB %if.then.3
	    Predecessors according to CFG: BB#3
784B		%vreg27<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr] GR64:%vreg27
800B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
816B		%EDI<def,dead> = MOV32r0 %EFLAGS<imp-def,dead>, %RDI<imp-def>
832B		%RSI<def> = COPY %vreg27; GR64:%vreg27
848B		%EDX<def> = MOV32ri 1
864B		%ECX<def,dead> = MOV32r0 %EFLAGS<imp-def,dead>, %RCX<imp-def>
880B		%R8D<def,dead> = MOV32r0 %EFLAGS<imp-def,dead>, %R8<imp-def>
896B		CALL64pcrel32 <ga:@BZ2_bzWriteClose>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>, %EDX<imp-use,kill>, %RCX<imp-use,kill>, %R8<imp-use,kill>
912B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
928B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
944B		STACKMAP 2, 0, 0, <fi#2>, 0, ...; mem:LD8[FixedStack2]
960B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#5

976B	BB#5: derived from LLVM BB %if.end.4
	    Predecessors according to CFG: BB#3 BB#4
992B		JMP_1 <BB#7>
	    Successors according to CFG: BB#7

1008B	BB#6: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#2
1024B		%vreg13<def> = LEA64r <fi#1>, 1, %noreg, 0, %noreg; GR64:%vreg13
1040B		%vreg15<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr] GR64:%vreg15
1056B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1072B		%RDI<def> = COPY %vreg13; GR64:%vreg13
1088B		%RSI<def> = COPY %vreg15; GR64:%vreg15
1104B		CALL64pcrel32 <ga:@BZ2_bzReadClose>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
1120B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1136B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1152B		STACKMAP 3, 0, 0, <fi#2>, 0, ...; mem:LD8[FixedStack2]
1168B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#7

1184B	BB#7: derived from LLVM BB %if.end.5
	    Predecessors according to CFG: BB#6 BB#5
1200B		%vreg30<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%fp] GR64:%vreg30
1216B		CMP64rm %vreg30, %noreg, 1, %noreg, <ga:@stdin>, %noreg, %EFLAGS<imp-def>; mem:LD8[@stdin] GR64:%vreg30
1232B		JE_1 <BB#10>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#10 BB#8

1248B	BB#8: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#7
1264B		%vreg33<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%fp] GR64:%vreg33
1280B		CMP64rm %vreg33, %noreg, 1, %noreg, <ga:@stdout>, %noreg, %EFLAGS<imp-def>; mem:LD8[@stdout] GR64:%vreg33
1296B		JE_1 <BB#10>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#10 BB#9

1312B	BB#9: derived from LLVM BB %if.then.8
	    Predecessors according to CFG: BB#8
1328B		%vreg36<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%fp] GR64:%vreg36
1344B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1360B		%RDI<def> = COPY %vreg36; GR64:%vreg36
1376B		CALL64pcrel32 <ga:@fclose>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
1392B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1408B		%vreg35<def,dead> = COPY %EAX<kill>; GR32:%vreg35
1424B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1440B		STACKMAP 4, 0, ...
1456B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#10

1472B	BB#10: derived from LLVM BB %if.end.9
	    Predecessors according to CFG: BB#7 BB#8 BB#9 BB#1
1488B		%vreg38<def> = MOV64ri <ga:@BZ2_bzclose>; GR64:%vreg38
1520B		%vreg39<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg39
1536B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1552B		%RDI<def> = COPY %vreg38; GR64:%vreg38
1568B		%RSI<def> = COPY %vreg39; GR64:%vreg39
1584B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
1600B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1616B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1632B		STACKMAP 5, 0, ...
1648B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1664B		RETQ

# End machine code for function BZ2_bzclose.

handleMove 544B -> 600B: %RSI<def> = COPY %vreg22; GR64:%vreg22
     SIL:	[128r,144r:4)[600r,608r:2)[832r,896r:1)[1088r,1104r:3)[1568r,1584r:0)  0@1568r 1@832r 2@600r 3@1088r 4@128r
        -->	[128r,144r:4)[600r,608r:2)[832r,896r:1)[1088r,1104r:3)[1568r,1584r:0)  0@1568r 1@832r 2@600r 3@1088r 4@128r
     %vreg22:	[496r,544r:0)  0@496r
        -->	[496r,600r:0)  0@496r
handleMove 528B -> 596B: %RDI<def> = COPY %vreg17; GR64:%vreg17
     DIL:	[0B,16r:0)[112r,144r:6)[528r,608r:4)[816r,896r:3)[1072r,1104r:5)[1360r,1376r:2)[1552r,1584r:1)  0@0B-phi 1@1552r 2@1360r 3@816r 4@528r 5@1072r 6@112r
        -->	[0B,16r:0)[112r,144r:6)[596r,608r:4)[816r,896r:3)[1072r,1104r:5)[1360r,1376r:2)[1552r,1584r:1)  0@0B-phi 1@1552r 2@1360r 3@816r 4@596r 5@1072r 6@112r
     %vreg17:	[432r,528r:0)  0@432r
        -->	[432r,596r:0)  0@432r
handleMove 832B -> 888B: %RSI<def> = COPY %vreg27; GR64:%vreg27
     SIL:	[128r,144r:4)[600r,608r:2)[832r,896r:1)[1088r,1104r:3)[1568r,1584r:0)  0@1568r 1@832r 2@600r 3@1088r 4@128r
        -->	[128r,144r:4)[600r,608r:2)[888r,896r:1)[1088r,1104r:3)[1568r,1584r:0)  0@1568r 1@888r 2@600r 3@1088r 4@128r
     %vreg27:	[784r,832r:0)  0@784r
        -->	[784r,888r:0)  0@784r
********** GREEDY REGISTER ALLOCATION **********
********** Function: BZ2_bzclose
********** INTERVALS **********
DIL [0B,16r:0)[112r,144r:6)[596r,608r:4)[816r,896r:3)[1072r,1104r:5)[1360r,1376r:2)[1552r,1584r:1)  0@0B-phi 1@1552r 2@1360r 3@816r 4@596r 5@1072r 6@112r
SIL [128r,144r:4)[600r,608r:2)[888r,896r:1)[1088r,1104r:3)[1568r,1584r:0)  0@1568r 1@888r 2@600r 3@1088r 4@128r
%vreg1 [16r,224r:0)  0@16r
%vreg5 [256r,272r:0)  0@256r
%vreg6 [240r,256r:0)  0@240r
%vreg8 [48r,112r:0)  0@48r
%vreg9 [80r,128r:0)  0@80r
%vreg12 [368r,384r:0)  0@368r
%vreg13 [1024r,1072r:0)  0@1024r
%vreg15 [1040r,1088r:0)  0@1040r
%vreg17 [432r,596r:0)  0@432r
%vreg22 [496r,600r:0)  0@496r
%vreg27 [784r,888r:0)  0@784r
%vreg30 [1200r,1216r:0)  0@1200r
%vreg33 [1264r,1280r:0)  0@1264r
%vreg35 [1408r,1408d:0)  0@1408r
%vreg36 [1328r,1360r:0)  0@1328r
%vreg38 [1488r,1552r:0)  0@1488r
%vreg39 [1520r,1568r:0)  0@1520r
RegMasks: 144r 608r 896r 1104r 1376r 1584r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzclose: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=8, align=8, at location [SP+8]
  fi#1: size=4, align=4, at location [SP+8]
  fi#2: size=8, align=8, at location [SP+8]
Function Live Ins: %RDI in %vreg0

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI
16B		%vreg1<def> = COPY %RDI; GR64:%vreg1
48B		%vreg8<def> = MOV64ri <ga:@BZ2_bzclose>; GR64:%vreg8
80B		%vreg9<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg9
96B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
112B		%RDI<def> = COPY %vreg8; GR64:%vreg8
128B		%RSI<def> = COPY %vreg9; GR64:%vreg9
144B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
160B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
192B		STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, ...; mem:LD8[FixedStack0] LD8[FixedStack1](align=4) LD8[FixedStack2] GR64:%vreg1
208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%b.addr] GR64:%vreg1
240B		%vreg6<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr] GR64:%vreg6
256B		%vreg5<def> = MOV64rm %vreg6, 1, %noreg, 0, %noreg; mem:LD8[%handle] GR64:%vreg5,%vreg6
272B		MOV64mr <fi#2>, 1, %noreg, 0, %noreg, %vreg5; mem:ST8[%fp] GR64:%vreg5
288B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%b.addr]
304B		JNE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

320B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
336B		JMP_1 <BB#10>
	    Successors according to CFG: BB#10

352B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0
368B		%vreg12<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr] GR64:%vreg12
384B		CMP8mi %vreg12, 1, %noreg, 5012, %noreg, 0, %EFLAGS<imp-def>; mem:LD1[%writing] GR64:%vreg12
400B		JE_1 <BB#6>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#6 BB#3

416B	BB#3: derived from LLVM BB %if.then.1
	    Predecessors according to CFG: BB#2
432B		%vreg17<def> = LEA64r <fi#1>, 1, %noreg, 0, %noreg; GR64:%vreg17
496B		%vreg22<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr] GR64:%vreg22
512B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
560B		%EDX<def> = MOV32r0 %EFLAGS<imp-def,dead>
576B		%ECX<def,dead> = MOV32r0 %EFLAGS<imp-def,dead>, %RCX<imp-def>
592B		%R8D<def,dead> = MOV32r0 %EFLAGS<imp-def,dead>, %R8<imp-def>
596B		%RDI<def> = COPY %vreg17; GR64:%vreg17
600B		%RSI<def> = COPY %vreg22; GR64:%vreg22
608B		CALL64pcrel32 <ga:@BZ2_bzWriteClose>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %EDX<imp-use,kill>, %RCX<imp-use,kill>, %R8<imp-use,kill>
624B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
640B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
656B		STACKMAP 1, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, ...; mem:LD8[FixedStack0] LD8[FixedStack1](align=4) LD8[FixedStack2]
672B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
688B		CMP32mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%bzerr]
704B		JE_1 <BB#5>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#5 BB#4

720B	BB#4: derived from LLVM BB %if.then.3
	    Predecessors according to CFG: BB#3
784B		%vreg27<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr] GR64:%vreg27
800B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
816B		%EDI<def,dead> = MOV32r0 %EFLAGS<imp-def,dead>, %RDI<imp-def>
848B		%EDX<def> = MOV32ri 1
864B		%ECX<def,dead> = MOV32r0 %EFLAGS<imp-def,dead>, %RCX<imp-def>
880B		%R8D<def,dead> = MOV32r0 %EFLAGS<imp-def,dead>, %R8<imp-def>
888B		%RSI<def> = COPY %vreg27; GR64:%vreg27
896B		CALL64pcrel32 <ga:@BZ2_bzWriteClose>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %EDX<imp-use,kill>, %RCX<imp-use,kill>, %R8<imp-use,kill>
912B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
928B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
944B		STACKMAP 2, 0, 0, <fi#2>, 0, ...; mem:LD8[FixedStack2]
960B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#5

976B	BB#5: derived from LLVM BB %if.end.4
	    Predecessors according to CFG: BB#3 BB#4
992B		JMP_1 <BB#7>
	    Successors according to CFG: BB#7

1008B	BB#6: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#2
1024B		%vreg13<def> = LEA64r <fi#1>, 1, %noreg, 0, %noreg; GR64:%vreg13
1040B		%vreg15<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr] GR64:%vreg15
1056B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1072B		%RDI<def> = COPY %vreg13; GR64:%vreg13
1088B		%RSI<def> = COPY %vreg15; GR64:%vreg15
1104B		CALL64pcrel32 <ga:@BZ2_bzReadClose>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
1120B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1136B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1152B		STACKMAP 3, 0, 0, <fi#2>, 0, ...; mem:LD8[FixedStack2]
1168B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#7

1184B	BB#7: derived from LLVM BB %if.end.5
	    Predecessors according to CFG: BB#6 BB#5
1200B		%vreg30<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%fp] GR64:%vreg30
1216B		CMP64rm %vreg30, %noreg, 1, %noreg, <ga:@stdin>, %noreg, %EFLAGS<imp-def>; mem:LD8[@stdin] GR64:%vreg30
1232B		JE_1 <BB#10>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#10 BB#8

1248B	BB#8: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#7
1264B		%vreg33<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%fp] GR64:%vreg33
1280B		CMP64rm %vreg33, %noreg, 1, %noreg, <ga:@stdout>, %noreg, %EFLAGS<imp-def>; mem:LD8[@stdout] GR64:%vreg33
1296B		JE_1 <BB#10>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#10 BB#9

1312B	BB#9: derived from LLVM BB %if.then.8
	    Predecessors according to CFG: BB#8
1328B		%vreg36<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%fp] GR64:%vreg36
1344B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1360B		%RDI<def> = COPY %vreg36; GR64:%vreg36
1376B		CALL64pcrel32 <ga:@fclose>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
1392B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1408B		%vreg35<def,dead> = COPY %EAX<kill>; GR32:%vreg35
1424B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1440B		STACKMAP 4, 0, ...
1456B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#10

1472B	BB#10: derived from LLVM BB %if.end.9
	    Predecessors according to CFG: BB#7 BB#8 BB#9 BB#1
1488B		%vreg38<def> = MOV64ri <ga:@BZ2_bzclose>; GR64:%vreg38
1520B		%vreg39<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg39
1536B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1552B		%RDI<def> = COPY %vreg38; GR64:%vreg38
1568B		%RSI<def> = COPY %vreg39; GR64:%vreg39
1584B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
1600B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1616B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1632B		STACKMAP 5, 0, ...
1648B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1664B		RETQ

# End machine code for function BZ2_bzclose.


selectOrSplit GR64:%vreg1 [16r,224r:0)  0@16r w=4.983553e-03
hints: %RDI
missed hint %RDI
assigning %vreg1 to %RBX: BH [16r,224r:0)  0@16r BL [16r,224r:0)  0@16r

selectOrSplit GR64:%vreg8 [48r,112r:0)  0@48r w=2.176724e-03
hints: %RDI
assigning %vreg8 to %RDI: DIL [48r,112r:0)  0@48r

selectOrSplit GR64:%vreg9 [80r,128r:0)  0@80r w=4.508928e-03
hints: %RSI
assigning %vreg9 to %RSI: SIL [80r,128r:0)  0@80r

selectOrSplit GR64:%vreg17 [432r,596r:0)  0@432r w=4.263762e-04
hints: %RDI
assigning %vreg17 to %RDI: DIL [432r,596r:0)  0@432r

selectOrSplit GR64:%vreg22 [496r,600r:0)  0@496r w=9.542707e-04
hints: %RSI
assigning %vreg22 to %RSI: SIL [496r,600r:0)  0@496r

selectOrSplit GR64:%vreg27 [784r,888r:0)  0@784r w=5.089444e-04
hints: %RSI
assigning %vreg27 to %RSI: SIL [784r,888r:0)  0@784r

selectOrSplit GR64:%vreg13 [1024r,1072r:0)  0@1024r w=5.367773e-04
hints: %RDI
assigning %vreg13 to %RDI: DIL [1024r,1072r:0)  0@1024r

selectOrSplit GR64:%vreg15 [1040r,1088r:0)  0@1040r w=1.073555e-03
hints: %RSI
assigning %vreg15 to %RSI: SIL [1040r,1088r:0)  0@1040r

selectOrSplit GR64:%vreg36 [1328r,1360r:0)  0@1328r w=5.937684e-04
hints: %RDI
assigning %vreg36 to %RDI: DIL [1328r,1360r:0)  0@1328r

selectOrSplit GR32:%vreg35 [1408r,1408d:0)  0@1408r w=inf
hints: %EAX
assigning %vreg35 to %EAX: AH [1408r,1408d:0)  0@1408r AL [1408r,1408d:0)  0@1408r

selectOrSplit GR64:%vreg38 [1488r,1552r:0)  0@1488r w=2.176724e-03
hints: %RDI
assigning %vreg38 to %RDI: DIL [1488r,1552r:0)  0@1488r

selectOrSplit GR64:%vreg39 [1520r,1568r:0)  0@1520r w=4.508928e-03
hints: %RSI
assigning %vreg39 to %RSI: SIL [1520r,1568r:0)  0@1520r

selectOrSplit GR64:%vreg6 [240r,256r:0)  0@240r w=inf
assigning %vreg6 to %RAX: AH [240r,256r:0)  0@240r AL [240r,256r:0)  0@240r

selectOrSplit GR64:%vreg5 [256r,272r:0)  0@256r w=inf
assigning %vreg5 to %RAX: AH [256r,272r:0)  0@256r AL [256r,272r:0)  0@256r

selectOrSplit GR64:%vreg12 [368r,384r:0)  0@368r w=inf
assigning %vreg12 to %RAX: AH [368r,384r:0)  0@368r AL [368r,384r:0)  0@368r

selectOrSplit GR64:%vreg30 [1200r,1216r:0)  0@1200r w=inf
assigning %vreg30 to %RAX: AH [1200r,1216r:0)  0@1200r AL [1200r,1216r:0)  0@1200r

selectOrSplit GR64:%vreg33 [1264r,1280r:0)  0@1264r w=inf
assigning %vreg33 to %RAX: AH [1264r,1280r:0)  0@1264r AL [1264r,1280r:0)  0@1264r

********** STACK TRANSFORMATION METADATA **********
********** Function: BZ2_bzclose
********** REGISTER MAP **********
[%vreg1 -> %RBX] GR64
[%vreg5 -> %RAX] GR64
[%vreg6 -> %RAX] GR64
[%vreg8 -> %RDI] GR64
[%vreg9 -> %RSI] GR64
[%vreg12 -> %RAX] GR64
[%vreg13 -> %RDI] GR64
[%vreg15 -> %RSI] GR64
[%vreg17 -> %RDI] GR64
[%vreg22 -> %RSI] GR64
[%vreg27 -> %RSI] GR64
[%vreg30 -> %RAX] GR64
[%vreg33 -> %RAX] GR64
[%vreg35 -> %EAX] GR32
[%vreg36 -> %RDI] GR64
[%vreg38 -> %RDI] GR64
[%vreg39 -> %RSI] GR64


Stackmap 0:
  STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, ...; mem:LD8[FixedStack0] LD8[FixedStack1](align=4) LD8[FixedStack2] GR64:%vreg1

i8* %b: in register %RBX (vreg 1)
i8** %b.addr: in stack slot 0 (size: 8)
i32* %bzerr: in stack slot 1 (size: 4)
%struct._IO_FILE** %fp: in stack slot 2 (size: 8)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, ...; mem:LD8[FixedStack0] LD8[FixedStack1](align=4) LD8[FixedStack2]

i8** %b.addr: in stack slot 0 (size: 8)
i32* %bzerr: in stack slot 1 (size: 4)
%struct._IO_FILE** %fp: in stack slot 2 (size: 8)

Duplicate operand locations:


Stackmap 2:
  STACKMAP 2, 0, 0, <fi#2>, 0, ...; mem:LD8[FixedStack2]

%struct._IO_FILE** %fp: in stack slot 2 (size: 8)

Duplicate operand locations:


Stackmap 3:
  STACKMAP 3, 0, 0, <fi#2>, 0, ...; mem:LD8[FixedStack2]

%struct._IO_FILE** %fp: in stack slot 2 (size: 8)

Duplicate operand locations:


Stackmap 4:
  STACKMAP 4, 0, ...


Duplicate operand locations:


Stackmap 5:
  STACKMAP 5, 0, ...


Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, ...; mem:LD8[FixedStack0] LD8[FixedStack1](align=4) LD8[FixedStack2] GR64:%vreg1
  -> Call instruction SlotIndex 144B, searching vregs 0 -> 40 and stack slots -1 -> 3

  STACKMAP 1, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, ...; mem:LD8[FixedStack0] LD8[FixedStack1](align=4) LD8[FixedStack2]
  -> Call instruction SlotIndex 608B, searching vregs 0 -> 40 and stack slots -1 -> 3

  STACKMAP 2, 0, 0, <fi#2>, 0, ...; mem:LD8[FixedStack2]
  -> Call instruction SlotIndex 896B, searching vregs 0 -> 40 and stack slots -1 -> 3

  STACKMAP 3, 0, 0, <fi#2>, 0, ...; mem:LD8[FixedStack2]
  -> Call instruction SlotIndex 1104B, searching vregs 0 -> 40 and stack slots -1 -> 3

  STACKMAP 4, 0, ...
  -> Call instruction SlotIndex 1376B, searching vregs 0 -> 40 and stack slots -1 -> 3

  STACKMAP 5, 0, ...
  -> Call instruction SlotIndex 1584B, searching vregs 0 -> 40 and stack slots -1 -> 3

********** REWRITE VIRTUAL REGISTERS **********
********** Function: BZ2_bzclose
********** REGISTER MAP **********
[%vreg1 -> %RBX] GR64
[%vreg5 -> %RAX] GR64
[%vreg6 -> %RAX] GR64
[%vreg8 -> %RDI] GR64
[%vreg9 -> %RSI] GR64
[%vreg12 -> %RAX] GR64
[%vreg13 -> %RDI] GR64
[%vreg15 -> %RSI] GR64
[%vreg17 -> %RDI] GR64
[%vreg22 -> %RSI] GR64
[%vreg27 -> %RSI] GR64
[%vreg30 -> %RAX] GR64
[%vreg33 -> %RAX] GR64
[%vreg35 -> %EAX] GR32
[%vreg36 -> %RDI] GR64
[%vreg38 -> %RDI] GR64
[%vreg39 -> %RSI] GR64

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI
16B		%vreg1<def> = COPY %RDI; GR64:%vreg1
48B		%vreg8<def> = MOV64ri <ga:@BZ2_bzclose>; GR64:%vreg8
80B		%vreg9<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg9
96B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
112B		%RDI<def> = COPY %vreg8<kill>; GR64:%vreg8
128B		%RSI<def> = COPY %vreg9<kill>; GR64:%vreg9
144B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
160B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
192B		STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, ...; mem:LD8[FixedStack0] LD8[FixedStack1](align=4) LD8[FixedStack2] GR64:%vreg1
208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1<kill>; mem:ST8[%b.addr] GR64:%vreg1
240B		%vreg6<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr] GR64:%vreg6
256B		%vreg5<def> = MOV64rm %vreg6<kill>, 1, %noreg, 0, %noreg; mem:LD8[%handle] GR64:%vreg5,%vreg6
272B		MOV64mr <fi#2>, 1, %noreg, 0, %noreg, %vreg5<kill>; mem:ST8[%fp] GR64:%vreg5
288B		CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%b.addr]
304B		JNE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1
> %RBX<def> = COPY %RDI
> %RDI<def> = MOV64ri <ga:@BZ2_bzclose>
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 0, 0, %RBX, 0, <fi#0>, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, ...; mem:LD8[FixedStack0] LD8[FixedStack1](align=4) LD8[FixedStack2]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %RBX<kill>; mem:ST8[%b.addr]
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%handle]
> MOV64mr <fi#2>, 1, %noreg, 0, %noreg, %RAX<kill>; mem:ST8[%fp]
> CMP64mi8 <fi#0>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD8[%b.addr]
> JNE_1 <BB#2>, %EFLAGS<imp-use,kill>
320B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
336B		JMP_1 <BB#10>
	    Successors according to CFG: BB#10
> JMP_1 <BB#10>
352B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0
368B		%vreg12<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr] GR64:%vreg12
384B		CMP8mi %vreg12<kill>, 1, %noreg, 5012, %noreg, 0, %EFLAGS<imp-def>; mem:LD1[%writing] GR64:%vreg12
400B		JE_1 <BB#6>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#6 BB#3
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr]
> CMP8mi %RAX<kill>, 1, %noreg, 5012, %noreg, 0, %EFLAGS<imp-def>; mem:LD1[%writing]
> JE_1 <BB#6>, %EFLAGS<imp-use,kill>
416B	BB#3: derived from LLVM BB %if.then.1
	    Predecessors according to CFG: BB#2
432B		%vreg17<def> = LEA64r <fi#1>, 1, %noreg, 0, %noreg; GR64:%vreg17
496B		%vreg22<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr] GR64:%vreg22
512B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
560B		%EDX<def> = MOV32r0 %EFLAGS<imp-def,dead>
576B		%ECX<def,dead> = MOV32r0 %EFLAGS<imp-def,dead>, %RCX<imp-def>
592B		%R8D<def,dead> = MOV32r0 %EFLAGS<imp-def,dead>, %R8<imp-def>
596B		%RDI<def> = COPY %vreg17<kill>; GR64:%vreg17
600B		%RSI<def> = COPY %vreg22<kill>; GR64:%vreg22
608B		CALL64pcrel32 <ga:@BZ2_bzWriteClose>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %EDX<imp-use,kill>, %RCX<imp-use,kill>, %R8<imp-use,kill>
624B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
640B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
656B		STACKMAP 1, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, ...; mem:LD8[FixedStack0] LD8[FixedStack1](align=4) LD8[FixedStack2]
672B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
688B		CMP32mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%bzerr]
704B		JE_1 <BB#5>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#5 BB#4
> %RDI<def> = LEA64r <fi#1>, 1, %noreg, 0, %noreg
> %RSI<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EDX<def> = MOV32r0 %EFLAGS<imp-def,dead>
> %ECX<def,dead> = MOV32r0 %EFLAGS<imp-def,dead>, %RCX<imp-def>
> %R8D<def,dead> = MOV32r0 %EFLAGS<imp-def,dead>, %R8<imp-def>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@BZ2_bzWriteClose>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %EDX<imp-use,kill>, %RCX<imp-use,kill>, %R8<imp-use,kill>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 1, 0, 0, <fi#0>, 0, 0, <fi#1>, 0, 0, <fi#2>, 0, ...; mem:LD8[FixedStack0] LD8[FixedStack1](align=4) LD8[FixedStack2]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> CMP32mi8 <fi#1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%bzerr]
> JE_1 <BB#5>, %EFLAGS<imp-use,kill>
720B	BB#4: derived from LLVM BB %if.then.3
	    Predecessors according to CFG: BB#3
784B		%vreg27<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr] GR64:%vreg27
800B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
816B		%EDI<def,dead> = MOV32r0 %EFLAGS<imp-def,dead>, %RDI<imp-def>
848B		%EDX<def> = MOV32ri 1
864B		%ECX<def,dead> = MOV32r0 %EFLAGS<imp-def,dead>, %RCX<imp-def>
880B		%R8D<def,dead> = MOV32r0 %EFLAGS<imp-def,dead>, %R8<imp-def>
888B		%RSI<def> = COPY %vreg27<kill>; GR64:%vreg27
896B		CALL64pcrel32 <ga:@BZ2_bzWriteClose>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %EDX<imp-use,kill>, %RCX<imp-use,kill>, %R8<imp-use,kill>
912B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
928B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
944B		STACKMAP 2, 0, 0, <fi#2>, 0, ...; mem:LD8[FixedStack2]
960B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#5
> %RSI<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EDI<def,dead> = MOV32r0 %EFLAGS<imp-def,dead>, %RDI<imp-def>
> %EDX<def> = MOV32ri 1
> %ECX<def,dead> = MOV32r0 %EFLAGS<imp-def,dead>, %RCX<imp-def>
> %R8D<def,dead> = MOV32r0 %EFLAGS<imp-def,dead>, %R8<imp-def>
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@BZ2_bzWriteClose>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>, %EDX<imp-use,kill>, %RCX<imp-use,kill>, %R8<imp-use,kill>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 2, 0, 0, <fi#2>, 0, ...; mem:LD8[FixedStack2]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
976B	BB#5: derived from LLVM BB %if.end.4
	    Predecessors according to CFG: BB#3 BB#4
992B		JMP_1 <BB#7>
	    Successors according to CFG: BB#7
> JMP_1 <BB#7>
1008B	BB#6: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#2
1024B		%vreg13<def> = LEA64r <fi#1>, 1, %noreg, 0, %noreg; GR64:%vreg13
1040B		%vreg15<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr] GR64:%vreg15
1056B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1072B		%RDI<def> = COPY %vreg13<kill>; GR64:%vreg13
1088B		%RSI<def> = COPY %vreg15<kill>; GR64:%vreg15
1104B		CALL64pcrel32 <ga:@BZ2_bzReadClose>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
1120B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1136B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1152B		STACKMAP 3, 0, 0, <fi#2>, 0, ...; mem:LD8[FixedStack2]
1168B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#7
> %RDI<def> = LEA64r <fi#1>, 1, %noreg, 0, %noreg
> %RSI<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@BZ2_bzReadClose>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 3, 0, 0, <fi#2>, 0, ...; mem:LD8[FixedStack2]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1184B	BB#7: derived from LLVM BB %if.end.5
	    Predecessors according to CFG: BB#6 BB#5
1200B		%vreg30<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%fp] GR64:%vreg30
1216B		CMP64rm %vreg30<kill>, %noreg, 1, %noreg, <ga:@stdin>, %noreg, %EFLAGS<imp-def>; mem:LD8[@stdin] GR64:%vreg30
1232B		JE_1 <BB#10>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#10 BB#8
> %RAX<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%fp]
> CMP64rm %RAX<kill>, %noreg, 1, %noreg, <ga:@stdin>, %noreg, %EFLAGS<imp-def>; mem:LD8[@stdin]
> JE_1 <BB#10>, %EFLAGS<imp-use,kill>
1248B	BB#8: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#7
1264B		%vreg33<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%fp] GR64:%vreg33
1280B		CMP64rm %vreg33<kill>, %noreg, 1, %noreg, <ga:@stdout>, %noreg, %EFLAGS<imp-def>; mem:LD8[@stdout] GR64:%vreg33
1296B		JE_1 <BB#10>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#10 BB#9
> %RAX<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%fp]
> CMP64rm %RAX<kill>, %noreg, 1, %noreg, <ga:@stdout>, %noreg, %EFLAGS<imp-def>; mem:LD8[@stdout]
> JE_1 <BB#10>, %EFLAGS<imp-use,kill>
1312B	BB#9: derived from LLVM BB %if.then.8
	    Predecessors according to CFG: BB#8
1328B		%vreg36<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%fp] GR64:%vreg36
1344B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1360B		%RDI<def> = COPY %vreg36<kill>; GR64:%vreg36
1376B		CALL64pcrel32 <ga:@fclose>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
1392B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1408B		%vreg35<def,dead> = COPY %EAX; GR32:%vreg35
1424B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1440B		STACKMAP 4, 0, ...
1456B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#10
> %RDI<def> = MOV64rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD8[%fp]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@fclose>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %EAX<imp-def>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %EAX<def,dead> = COPY %EAX
Deleting identity copy.
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 4, 0, ...
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1472B	BB#10: derived from LLVM BB %if.end.9
	    Predecessors according to CFG: BB#7 BB#8 BB#9 BB#1
1488B		%vreg38<def> = MOV64ri <ga:@BZ2_bzclose>; GR64:%vreg38
1520B		%vreg39<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg39
1536B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1552B		%RDI<def> = COPY %vreg38<kill>; GR64:%vreg38
1568B		%RSI<def> = COPY %vreg39<kill>; GR64:%vreg39
1584B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
1600B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1616B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1632B		STACKMAP 5, 0, ...
1648B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1664B		RETQ
> %RDI<def> = MOV64ri <ga:@BZ2_bzclose>
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 5, 0, ...
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> RETQ
Computing live-in reg-units in ABI blocks.
0B	BB#0 DIL#0 SIL#0
Created 2 new intervals.
********** INTERVALS **********
DIL [0B,32r:0)[144r,176r:2)[576r,608r:1)  0@0B-phi 1@576r 2@144r
SIL [0B,16r:0)[160r,176r:2)[592r,608r:1)  0@0B-phi 1@592r 2@160r
%vreg0 [32r,48r:0)  0@32r
%vreg1 [48r,256r:0)  0@48r
%vreg2 [16r,64r:0)  0@16r
%vreg3 [64r,272r:0)  0@64r
%vreg7 [304r,320r:0)  0@304r
%vreg8 [288r,304r:0)  0@288r
%vreg9 [80r,96r:0)  0@80r
%vreg10 [96r,144r:0)  0@96r
%vreg11 [112r,160r:0)  0@112r
%vreg13 [416r,432r:0)  0@416r
%vreg14 [432r,576r:0)  0@432r
%vreg15 [544r,592r:0)  0@544r
%vreg17 [528r,688r:0)  0@528r
%vreg19 [512r,528r:0)  0@512r
%vreg21 [496r,512r:0)  0@496r
%vreg24 [464r,480r:0)  0@464r
%vreg25 [448r,480r:0)  0@448r
RegMasks: 176r 608r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzerror: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=8, align=8, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=4, align=4, at location [SP+8]
Function Live Ins: %RDI in %vreg0, %RSI in %vreg2

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI %RSI
16B		%vreg2<def> = COPY %RSI; GR64:%vreg2
32B		%vreg0<def> = COPY %RDI; GR64:%vreg0
48B		%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
64B		%vreg3<def> = COPY %vreg2; GR64:%vreg3,%vreg2
80B		%vreg9<def> = MOV64ri <ga:@BZ2_bzerror>; GR64:%vreg9
96B		%vreg10<def> = COPY %vreg9; GR64:%vreg10,%vreg9
112B		%vreg11<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg11
128B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
144B		%RDI<def> = COPY %vreg10; GR64:%vreg10
160B		%RSI<def> = COPY %vreg11; GR64:%vreg11
176B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
192B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
208B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#2>, 0, %vreg3, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0] LD8[FixedStack2](align=4) LD8[FixedStack1] GR64:%vreg1,%vreg3
240B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
256B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%b.addr] GR64:%vreg1
272B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg3; mem:ST8[%errnum.addr] GR64:%vreg3
288B		%vreg8<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr] GR64:%vreg8
304B		%vreg7<def> = MOV32rm %vreg8, 1, %noreg, 5096, %noreg; mem:LD4[%lastErr] GR32:%vreg7 GR64:%vreg8
320B		MOV32mr <fi#2>, 1, %noreg, 0, %noreg, %vreg7; mem:ST4[%err] GR32:%vreg7
336B		CMP32mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%err]
352B		JLE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

368B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
384B		MOV32mi <fi#2>, 1, %noreg, 0, %noreg, 0; mem:ST4[%err]
	    Successors according to CFG: BB#2

400B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#1
416B		%vreg13<def> = MOV64ri <ga:@BZ2_bzerror>; GR64:%vreg13
432B		%vreg14<def> = COPY %vreg13; GR64:%vreg14,%vreg13
448B		%vreg25<def> = MOV32rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD4[%err] GR32:%vreg25
464B		%vreg24<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%errnum.addr] GR64:%vreg24
480B		MOV32mr %vreg24, 1, %noreg, 0, %noreg, %vreg25; mem:ST4[%5] GR64:%vreg24 GR32:%vreg25
496B		%vreg21<def> = IMUL32rmi8 <fi#2>, 1, %noreg, 0, %noreg, -1, %EFLAGS<imp-def,dead>; mem:LD4[%err] GR32:%vreg21
512B		%vreg19<def> = MOVSX64rr32 %vreg21; GR64_NOSP:%vreg19 GR32:%vreg21
528B		%vreg17<def> = MOV64rm %noreg, 8, %vreg19, <ga:@bzerrorstrings>, %noreg; mem:LD8[%arrayidx] GR64:%vreg17 GR64_NOSP:%vreg19
544B		%vreg15<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg15
560B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
576B		%RDI<def> = COPY %vreg14; GR64:%vreg14
592B		%RSI<def> = COPY %vreg15; GR64:%vreg15
608B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
624B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
640B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
656B		STACKMAP 1, 0, %vreg17, ...; GR64:%vreg17
672B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
688B		%RAX<def> = COPY %vreg17; GR64:%vreg17
704B		RETQ %RAX<imp-use,kill>

# End machine code for function BZ2_bzerror.

********** SIMPLE REGISTER COALESCING **********
********** Function: BZ2_bzerror
********** JOINING INTERVALS ***********
entry:
16B	%vreg2<def> = COPY %RSI; GR64:%vreg2
	Considering merging %vreg2 with %RSI
	Can only merge into reserved registers.
32B	%vreg0<def> = COPY %RDI; GR64:%vreg0
	Considering merging %vreg0 with %RDI
	Can only merge into reserved registers.
144B	%RDI<def> = COPY %vreg10; GR64:%vreg10
	Considering merging %vreg10 with %RDI
	Can only merge into reserved registers.
160B	%RSI<def> = COPY %vreg11; GR64:%vreg11
	Considering merging %vreg11 with %RSI
	Can only merge into reserved registers.
if.then:
if.end:
576B	%RDI<def> = COPY %vreg14; GR64:%vreg14
	Considering merging %vreg14 with %RDI
	Can only merge into reserved registers.
592B	%RSI<def> = COPY %vreg15; GR64:%vreg15
	Considering merging %vreg15 with %RSI
	Can only merge into reserved registers.
688B	%RAX<def> = COPY %vreg17; GR64:%vreg17
	Considering merging %vreg17 with %RAX
	Can only merge into reserved registers.
48B	%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
	Considering merging to GR64 with %vreg0 in %vreg1
		RHS = %vreg0 [32r,48r:0)  0@32r
		LHS = %vreg1 [48r,256r:0)  0@48r
		merge %vreg1:0@48r into %vreg0:0@32r --> @32r
		erased:	48r	%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
		updated: 32B	%vreg1<def> = COPY %RDI; GR64:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [32r,256r:0)  0@32r
64B	%vreg3<def> = COPY %vreg2; GR64:%vreg3,%vreg2
	Considering merging to GR64 with %vreg2 in %vreg3
		RHS = %vreg2 [16r,64r:0)  0@16r
		LHS = %vreg3 [64r,272r:0)  0@64r
		merge %vreg3:0@64r into %vreg2:0@16r --> @16r
		erased:	64r	%vreg3<def> = COPY %vreg2; GR64:%vreg3,%vreg2
		updated: 16B	%vreg3<def> = COPY %RSI; GR64:%vreg3
	Success: %vreg2 -> %vreg3
	Result = %vreg3 [16r,272r:0)  0@16r
96B	%vreg10<def> = COPY %vreg9; GR64:%vreg10,%vreg9
	Considering merging to GR64 with %vreg9 in %vreg10
		RHS = %vreg9 [80r,96r:0)  0@80r
		LHS = %vreg10 [96r,144r:0)  0@96r
		merge %vreg10:0@96r into %vreg9:0@80r --> @80r
		erased:	96r	%vreg10<def> = COPY %vreg9; GR64:%vreg10,%vreg9
		updated: 80B	%vreg10<def> = MOV64ri <ga:@BZ2_bzerror>; GR64:%vreg10
	Success: %vreg9 -> %vreg10
	Result = %vreg10 [80r,144r:0)  0@80r
432B	%vreg14<def> = COPY %vreg13; GR64:%vreg14,%vreg13
	Considering merging to GR64 with %vreg13 in %vreg14
		RHS = %vreg13 [416r,432r:0)  0@416r
		LHS = %vreg14 [432r,576r:0)  0@432r
		merge %vreg14:0@432r into %vreg13:0@416r --> @416r
		erased:	432r	%vreg14<def> = COPY %vreg13; GR64:%vreg14,%vreg13
		updated: 416B	%vreg14<def> = MOV64ri <ga:@BZ2_bzerror>; GR64:%vreg14
	Success: %vreg13 -> %vreg14
	Result = %vreg14 [416r,576r:0)  0@416r
144B	%RDI<def> = COPY %vreg10; GR64:%vreg10
	Considering merging %vreg10 with %RDI
	Can only merge into reserved registers.
576B	%RDI<def> = COPY %vreg14; GR64:%vreg14
	Considering merging %vreg14 with %RDI
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
DIL [0B,32r:0)[144r,176r:2)[576r,608r:1)  0@0B-phi 1@576r 2@144r
SIL [0B,16r:0)[160r,176r:2)[592r,608r:1)  0@0B-phi 1@592r 2@160r
%vreg1 [32r,256r:0)  0@32r
%vreg3 [16r,272r:0)  0@16r
%vreg7 [304r,320r:0)  0@304r
%vreg8 [288r,304r:0)  0@288r
%vreg10 [80r,144r:0)  0@80r
%vreg11 [112r,160r:0)  0@112r
%vreg14 [416r,576r:0)  0@416r
%vreg15 [544r,592r:0)  0@544r
%vreg17 [528r,688r:0)  0@528r
%vreg19 [512r,528r:0)  0@512r
%vreg21 [496r,512r:0)  0@496r
%vreg24 [464r,480r:0)  0@464r
%vreg25 [448r,480r:0)  0@448r
RegMasks: 176r 608r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzerror: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=8, align=8, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=4, align=4, at location [SP+8]
Function Live Ins: %RDI in %vreg0, %RSI in %vreg2

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI %RSI
16B		%vreg3<def> = COPY %RSI; GR64:%vreg3
32B		%vreg1<def> = COPY %RDI; GR64:%vreg1
80B		%vreg10<def> = MOV64ri <ga:@BZ2_bzerror>; GR64:%vreg10
112B		%vreg11<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg11
128B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
144B		%RDI<def> = COPY %vreg10; GR64:%vreg10
160B		%RSI<def> = COPY %vreg11; GR64:%vreg11
176B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
192B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
208B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#2>, 0, %vreg3, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0] LD8[FixedStack2](align=4) LD8[FixedStack1] GR64:%vreg1,%vreg3
240B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
256B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%b.addr] GR64:%vreg1
272B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg3; mem:ST8[%errnum.addr] GR64:%vreg3
288B		%vreg8<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr] GR64:%vreg8
304B		%vreg7<def> = MOV32rm %vreg8, 1, %noreg, 5096, %noreg; mem:LD4[%lastErr] GR32:%vreg7 GR64:%vreg8
320B		MOV32mr <fi#2>, 1, %noreg, 0, %noreg, %vreg7; mem:ST4[%err] GR32:%vreg7
336B		CMP32mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%err]
352B		JLE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

368B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
384B		MOV32mi <fi#2>, 1, %noreg, 0, %noreg, 0; mem:ST4[%err]
	    Successors according to CFG: BB#2

400B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#1
416B		%vreg14<def> = MOV64ri <ga:@BZ2_bzerror>; GR64:%vreg14
448B		%vreg25<def> = MOV32rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD4[%err] GR32:%vreg25
464B		%vreg24<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%errnum.addr] GR64:%vreg24
480B		MOV32mr %vreg24, 1, %noreg, 0, %noreg, %vreg25; mem:ST4[%5] GR64:%vreg24 GR32:%vreg25
496B		%vreg21<def> = IMUL32rmi8 <fi#2>, 1, %noreg, 0, %noreg, -1, %EFLAGS<imp-def,dead>; mem:LD4[%err] GR32:%vreg21
512B		%vreg19<def> = MOVSX64rr32 %vreg21; GR64_NOSP:%vreg19 GR32:%vreg21
528B		%vreg17<def> = MOV64rm %noreg, 8, %vreg19, <ga:@bzerrorstrings>, %noreg; mem:LD8[%arrayidx] GR64:%vreg17 GR64_NOSP:%vreg19
544B		%vreg15<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg15
560B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
576B		%RDI<def> = COPY %vreg14; GR64:%vreg14
592B		%RSI<def> = COPY %vreg15; GR64:%vreg15
608B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
624B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
640B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
656B		STACKMAP 1, 0, %vreg17, ...; GR64:%vreg17
672B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
688B		%RAX<def> = COPY %vreg17; GR64:%vreg17
704B		RETQ %RAX<imp-use,kill>

# End machine code for function BZ2_bzerror.

AllocationOrder(SEGMENT_REG) = [ ]
********** GREEDY REGISTER ALLOCATION **********
********** Function: BZ2_bzerror
********** INTERVALS **********
DIL [0B,32r:0)[144r,176r:2)[576r,608r:1)  0@0B-phi 1@576r 2@144r
SIL [0B,16r:0)[160r,176r:2)[592r,608r:1)  0@0B-phi 1@592r 2@160r
%vreg1 [32r,256r:0)  0@32r
%vreg3 [16r,272r:0)  0@16r
%vreg7 [304r,320r:0)  0@304r
%vreg8 [288r,304r:0)  0@288r
%vreg10 [80r,144r:0)  0@80r
%vreg11 [112r,160r:0)  0@112r
%vreg14 [416r,576r:0)  0@416r
%vreg15 [544r,592r:0)  0@544r
%vreg17 [528r,688r:0)  0@528r
%vreg19 [512r,528r:0)  0@512r
%vreg21 [496r,512r:0)  0@496r
%vreg24 [464r,480r:0)  0@464r
%vreg25 [448r,480r:0)  0@448r
RegMasks: 176r 608r
********** MACHINEINSTRS **********
# Machine code for function BZ2_bzerror: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=8, align=8, at location [SP+8]
  fi#1: size=8, align=8, at location [SP+8]
  fi#2: size=4, align=4, at location [SP+8]
Function Live Ins: %RDI in %vreg0, %RSI in %vreg2

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI %RSI
16B		%vreg3<def> = COPY %RSI; GR64:%vreg3
32B		%vreg1<def> = COPY %RDI; GR64:%vreg1
80B		%vreg10<def> = MOV64ri <ga:@BZ2_bzerror>; GR64:%vreg10
112B		%vreg11<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg11
128B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
144B		%RDI<def> = COPY %vreg10; GR64:%vreg10
160B		%RSI<def> = COPY %vreg11; GR64:%vreg11
176B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
192B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
208B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#2>, 0, %vreg3, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0] LD8[FixedStack2](align=4) LD8[FixedStack1] GR64:%vreg1,%vreg3
240B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
256B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%b.addr] GR64:%vreg1
272B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg3; mem:ST8[%errnum.addr] GR64:%vreg3
288B		%vreg8<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr] GR64:%vreg8
304B		%vreg7<def> = MOV32rm %vreg8, 1, %noreg, 5096, %noreg; mem:LD4[%lastErr] GR32:%vreg7 GR64:%vreg8
320B		MOV32mr <fi#2>, 1, %noreg, 0, %noreg, %vreg7; mem:ST4[%err] GR32:%vreg7
336B		CMP32mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%err]
352B		JLE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

368B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
384B		MOV32mi <fi#2>, 1, %noreg, 0, %noreg, 0; mem:ST4[%err]
	    Successors according to CFG: BB#2

400B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#1
416B		%vreg14<def> = MOV64ri <ga:@BZ2_bzerror>; GR64:%vreg14
448B		%vreg25<def> = MOV32rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD4[%err] GR32:%vreg25
464B		%vreg24<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%errnum.addr] GR64:%vreg24
480B		MOV32mr %vreg24, 1, %noreg, 0, %noreg, %vreg25; mem:ST4[%5] GR64:%vreg24 GR32:%vreg25
496B		%vreg21<def> = IMUL32rmi8 <fi#2>, 1, %noreg, 0, %noreg, -1, %EFLAGS<imp-def,dead>; mem:LD4[%err] GR32:%vreg21
512B		%vreg19<def> = MOVSX64rr32 %vreg21; GR64_NOSP:%vreg19 GR32:%vreg21
528B		%vreg17<def> = MOV64rm %noreg, 8, %vreg19, <ga:@bzerrorstrings>, %noreg; mem:LD8[%arrayidx] GR64:%vreg17 GR64_NOSP:%vreg19
544B		%vreg15<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg15
560B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
576B		%RDI<def> = COPY %vreg14; GR64:%vreg14
592B		%RSI<def> = COPY %vreg15; GR64:%vreg15
608B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
624B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
640B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
656B		STACKMAP 1, 0, %vreg17, ...; GR64:%vreg17
672B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
688B		%RAX<def> = COPY %vreg17; GR64:%vreg17
704B		RETQ %RAX<imp-use,kill>

# End machine code for function BZ2_bzerror.


selectOrSplit GR64:%vreg3 [16r,272r:0)  0@16r w=4.618902e-03
hints: %RSI
missed hint %RSI
assigning %vreg3 to %RBX: BH [16r,272r:0)  0@16r BL [16r,272r:0)  0@16r

selectOrSplit GR64:%vreg1 [32r,256r:0)  0@32r w=4.855769e-03
hints: %RDI
missed hint %RDI
%R14 is available at cost 1
Only trying the first 10 regs.
should evict: %vreg3 [16r,272r:0)  0@16r w= 4.618902e-03
hints: %RSI
can reassign: %vreg3 [16r,272r:0)  0@16r from %RBX to %RSI
should evict: %vreg3 [16r,272r:0)  0@16r w= 4.618902e-03
hints: %RSI
can reassign: %vreg3 [16r,272r:0)  0@16r from %RBX to %RSI
evicting %RBX interference: Cascade 1
unassigning %vreg3 from %RBX: BH BL
assigning %vreg1 to %RBX: BH [32r,256r:0)  0@32r BL [32r,256r:0)  0@32r
queuing new interval: %vreg3 [16r,272r:0)  0@16r

selectOrSplit GR64:%vreg3 [16r,272r:0)  0@16r w=4.618902e-03
hints: %RSI
missed hint %RSI
%R14 is available at cost 1
Only trying the first 10 regs.
assigning %vreg3 to %R14: R14B [16r,272r:0)  0@16r

selectOrSplit GR64:%vreg10 [80r,144r:0)  0@80r w=2.176724e-03
hints: %RDI
assigning %vreg10 to %RDI: DIL [80r,144r:0)  0@80r

selectOrSplit GR64:%vreg11 [112r,160r:0)  0@112r w=4.508928e-03
hints: %RSI
assigning %vreg11 to %RSI: SIL [112r,160r:0)  0@112r

selectOrSplit GR64:%vreg14 [416r,576r:0)  0@416r w=1.803571e-03
hints: %RDI
assigning %vreg14 to %RDI: DIL [416r,576r:0)  0@416r

selectOrSplit GR64:%vreg17 [528r,688r:0)  0@528r w=5.410714e-03
hints: %RAX
missed hint %RAX
assigning %vreg17 to %RBX: BH [528r,688r:0)  0@528r BL [528r,688r:0)  0@528r

selectOrSplit GR64:%vreg15 [544r,592r:0)  0@544r w=4.508928e-03
hints: %RSI
assigning %vreg15 to %RSI: SIL [544r,592r:0)  0@544r

selectOrSplit GR64:%vreg8 [288r,304r:0)  0@288r w=inf
assigning %vreg8 to %RAX: AH [288r,304r:0)  0@288r AL [288r,304r:0)  0@288r

selectOrSplit GR32:%vreg7 [304r,320r:0)  0@304r w=inf
assigning %vreg7 to %EAX: AH [304r,320r:0)  0@304r AL [304r,320r:0)  0@304r

selectOrSplit GR32:%vreg25 [448r,480r:0)  0@448r w=4.629630e-03
assigning %vreg25 to %EAX: AH [448r,480r:0)  0@448r AL [448r,480r:0)  0@448r

selectOrSplit GR64:%vreg24 [464r,480r:0)  0@464r w=inf
assigning %vreg24 to %RCX: CH [464r,480r:0)  0@464r CL [464r,480r:0)  0@464r

selectOrSplit GR32:%vreg21 [496r,512r:0)  0@496r w=inf
assigning %vreg21 to %EAX: AH [496r,512r:0)  0@496r AL [496r,512r:0)  0@496r

selectOrSplit GR64_NOSP:%vreg19 [512r,528r:0)  0@512r w=inf
assigning %vreg19 to %RAX: AH [512r,528r:0)  0@512r AL [512r,528r:0)  0@512r

********** STACK TRANSFORMATION METADATA **********
********** Function: BZ2_bzerror
********** REGISTER MAP **********
[%vreg1 -> %RBX] GR64
[%vreg3 -> %R14] GR64
[%vreg7 -> %EAX] GR32
[%vreg8 -> %RAX] GR64
[%vreg10 -> %RDI] GR64
[%vreg11 -> %RSI] GR64
[%vreg14 -> %RDI] GR64
[%vreg15 -> %RSI] GR64
[%vreg17 -> %RBX] GR64
[%vreg19 -> %RAX] GR64_NOSP
[%vreg21 -> %EAX] GR32
[%vreg24 -> %RCX] GR64
[%vreg25 -> %EAX] GR32


Stackmap 0:
  STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#2>, 0, %vreg3, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0] LD8[FixedStack2](align=4) LD8[FixedStack1] GR64:%vreg1,%vreg3

i8* %b: in register %RBX (vreg 1)
i8** %b.addr: in stack slot 0 (size: 8)
i32* %err: in stack slot 2 (size: 4)
i32* %errnum: in register %R14 (vreg 3)
i32** %errnum.addr: in stack slot 1 (size: 8)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, %vreg17, ...; GR64:%vreg17

i8* %7: in register %RBX (vreg 17)

Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#2>, 0, %vreg3, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0] LD8[FixedStack2](align=4) LD8[FixedStack1] GR64:%vreg1,%vreg3
  -> Call instruction SlotIndex 176B, searching vregs 0 -> 26 and stack slots -1 -> 3

  STACKMAP 1, 0, %vreg17, ...; GR64:%vreg17
  -> Call instruction SlotIndex 608B, searching vregs 0 -> 26 and stack slots -1 -> 3

********** REWRITE VIRTUAL REGISTERS **********
********** Function: BZ2_bzerror
********** REGISTER MAP **********
[%vreg1 -> %RBX] GR64
[%vreg3 -> %R14] GR64
[%vreg7 -> %EAX] GR32
[%vreg8 -> %RAX] GR64
[%vreg10 -> %RDI] GR64
[%vreg11 -> %RSI] GR64
[%vreg14 -> %RDI] GR64
[%vreg15 -> %RSI] GR64
[%vreg17 -> %RBX] GR64
[%vreg19 -> %RAX] GR64_NOSP
[%vreg21 -> %EAX] GR32
[%vreg24 -> %RCX] GR64
[%vreg25 -> %EAX] GR32

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI %RSI
16B		%vreg3<def> = COPY %RSI; GR64:%vreg3
32B		%vreg1<def> = COPY %RDI; GR64:%vreg1
80B		%vreg10<def> = MOV64ri <ga:@BZ2_bzerror>; GR64:%vreg10
112B		%vreg11<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg11
128B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
144B		%RDI<def> = COPY %vreg10<kill>; GR64:%vreg10
160B		%RSI<def> = COPY %vreg11<kill>; GR64:%vreg11
176B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
192B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
208B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#2>, 0, %vreg3, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0] LD8[FixedStack2](align=4) LD8[FixedStack1] GR64:%vreg1,%vreg3
240B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
256B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1<kill>; mem:ST8[%b.addr] GR64:%vreg1
272B		MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %vreg3<kill>; mem:ST8[%errnum.addr] GR64:%vreg3
288B		%vreg8<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr] GR64:%vreg8
304B		%vreg7<def> = MOV32rm %vreg8<kill>, 1, %noreg, 5096, %noreg; mem:LD4[%lastErr] GR32:%vreg7 GR64:%vreg8
320B		MOV32mr <fi#2>, 1, %noreg, 0, %noreg, %vreg7<kill>; mem:ST4[%err] GR32:%vreg7
336B		CMP32mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%err]
352B		JLE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1
> %R14<def> = COPY %RSI
> %RBX<def> = COPY %RDI
> %RDI<def> = MOV64ri <ga:@BZ2_bzerror>
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 0, 0, %RBX, 0, <fi#0>, 0, 0, <fi#2>, 0, %R14, 0, <fi#1>, 0, ...; mem:LD8[FixedStack0] LD8[FixedStack2](align=4) LD8[FixedStack1]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %RBX<kill>; mem:ST8[%b.addr]
> MOV64mr <fi#1>, 1, %noreg, 0, %noreg, %R14<kill>; mem:ST8[%errnum.addr]
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%b.addr]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 5096, %noreg; mem:LD4[%lastErr]
> MOV32mr <fi#2>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%err]
> CMP32mi8 <fi#2>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%err]
> JLE_1 <BB#2>, %EFLAGS<imp-use,kill>
368B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
384B		MOV32mi <fi#2>, 1, %noreg, 0, %noreg, 0; mem:ST4[%err]
	    Successors according to CFG: BB#2
> MOV32mi <fi#2>, 1, %noreg, 0, %noreg, 0; mem:ST4[%err]
400B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#1
416B		%vreg14<def> = MOV64ri <ga:@BZ2_bzerror>; GR64:%vreg14
448B		%vreg25<def> = MOV32rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD4[%err] GR32:%vreg25
464B		%vreg24<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%errnum.addr] GR64:%vreg24
480B		MOV32mr %vreg24<kill>, 1, %noreg, 0, %noreg, %vreg25<kill>; mem:ST4[%5] GR64:%vreg24 GR32:%vreg25
496B		%vreg21<def> = IMUL32rmi8 <fi#2>, 1, %noreg, 0, %noreg, -1, %EFLAGS<imp-def,dead>; mem:LD4[%err] GR32:%vreg21
512B		%vreg19<def> = MOVSX64rr32 %vreg21<kill>; GR64_NOSP:%vreg19 GR32:%vreg21
528B		%vreg17<def> = MOV64rm %noreg, 8, %vreg19<kill>, <ga:@bzerrorstrings>, %noreg; mem:LD8[%arrayidx] GR64:%vreg17 GR64_NOSP:%vreg19
544B		%vreg15<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg15
560B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
576B		%RDI<def> = COPY %vreg14<kill>; GR64:%vreg14
592B		%RSI<def> = COPY %vreg15<kill>; GR64:%vreg15
608B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
624B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
640B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
656B		STACKMAP 1, 0, %vreg17, ...; GR64:%vreg17
672B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
688B		%RAX<def> = COPY %vreg17<kill>; GR64:%vreg17
704B		RETQ %RAX<imp-use>
> %RDI<def> = MOV64ri <ga:@BZ2_bzerror>
> %EAX<def> = MOV32rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD4[%err]
> %RCX<def> = MOV64rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD8[%errnum.addr]
> MOV32mr %RCX<kill>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%5]
> %EAX<def> = IMUL32rmi8 <fi#2>, 1, %noreg, 0, %noreg, -1, %EFLAGS<imp-def,dead>; mem:LD4[%err]
> %RAX<def> = MOVSX64rr32 %EAX<kill>
> %RBX<def> = MOV64rm %noreg, 8, %RAX<kill>, <ga:@bzerrorstrings>, %noreg; mem:LD8[%arrayidx]
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 1, 0, %RBX, ...
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RAX<def> = COPY %RBX<kill>
> RETQ %RAX<imp-use>
Computing live-in reg-units in ABI blocks.
0B	BB#0 DIL#0
Created 1 new intervals.
********** INTERVALS **********
DIL [0B,16r:0)[112r,144r:2)[1344r,1376r:1)  0@0B-phi 1@1344r 2@112r
%vreg0 [16r,32r:0)  0@16r
%vreg1 [32r,224r:0)  0@32r
%vreg2 [48r,64r:0)  0@48r
%vreg3 [64r,112r:0)  0@64r
%vreg4 [80r,128r:0)  0@80r
%vreg8 [288r,304r:0)  0@288r
%vreg9 [272r,288r:0)  0@272r
%vreg13 [416r,432r:0)  0@416r
%vreg15 [400r,432r:0)  0@400r
%vreg16 [384r,400r:0)  0@384r
%vreg20 [1056r,1072r:0)  0@1056r
%vreg21 [1040r,1056r:0)  0@1040r
%vreg25 [992r,1008r:0)[1008r,1024r:1)  0@992r 1@1008r
%vreg26 [976r,992r:0)  0@976r
%vreg28 [960r,1024r:0)  0@960r
%vreg29 [944r,960r:0)  0@944r
%vreg33 [896r,912r:0)[912r,928r:1)  0@896r 1@912r
%vreg34 [880r,896r:0)  0@880r
%vreg36 [864r,928r:0)  0@864r
%vreg37 [848r,864r:0)  0@848r
%vreg41 [800r,816r:0)[816r,832r:1)  0@800r 1@816r
%vreg42 [784r,800r:0)  0@784r
%vreg44 [768r,832r:0)  0@768r
%vreg45 [752r,768r:0)  0@752r
%vreg49 [704r,720r:0)[720r,736r:1)  0@704r 1@720r
%vreg50 [688r,704r:0)  0@688r
%vreg51 [672r,736r:0)  0@672r
%vreg55 [640r,656r:0)  0@640r
%vreg57 [624r,640r:0)  0@624r
%vreg58 [608r,624r:0)  0@608r
%vreg61 [592r,656r:0)  0@592r
%vreg63 [576r,592r:0)  0@576r
%vreg64 [560r,576r:0)  0@560r
%vreg66 [544r,592r:0)  0@544r
%vreg68 [528r,544r:0)  0@528r
%vreg72 [1168r,1184r:0)[1184r,1200r:1)  0@1168r 1@1184r
%vreg73 [1152r,1168r:0)  0@1152r
%vreg75 [1136r,1200r:0)  0@1136r
%vreg76 [1120r,1136r:0)  0@1120r
%vreg78 [1264r,1280r:0)  0@1264r
%vreg79 [1280r,1344r:0)  0@1280r
%vreg80 [1312r,1360r:0)  0@1312r
%vreg81 [1296r,1456r:0)  0@1296r
RegMasks: 144r 1376r
********** MACHINEINSTRS **********
# Machine code for function copy_output_until_stop: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=8, align=8, at location [SP+8]
  fi#1: size=1, align=1, at location [SP+8]
Function Live Ins: %RDI in %vreg0

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI
16B		%vreg0<def> = COPY %RDI; GR64:%vreg0
32B		%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
48B		%vreg2<def> = MOV64ri <ga:@copy_output_until_stop>; GR64:%vreg2
64B		%vreg3<def> = COPY %vreg2; GR64:%vreg3,%vreg2
80B		%vreg4<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg4
96B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
112B		%RDI<def> = COPY %vreg3; GR64:%vreg3
128B		%RSI<def> = COPY %vreg4; GR64:%vreg4
144B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
160B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
192B		STACKMAP 0, 0, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack0] GR64:%vreg1
208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%s.addr] GR64:%vreg1
240B		MOV8mi <fi#1>, 1, %noreg, 0, %noreg, 0; mem:ST1[%progress_out]
	    Successors according to CFG: BB#1

256B	BB#1: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#0 BB#7
272B		%vreg9<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg9
288B		%vreg8<def> = MOV64rm %vreg9, 1, %noreg, 0, %noreg; mem:LD8[%strm] GR64:%vreg8,%vreg9
304B		CMP32mi8 %vreg8, 1, %noreg, 32, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_out] GR64:%vreg8
320B		JNE_1 <BB#3>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#3 BB#2

336B	BB#2: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#1
352B		JMP_1 <BB#8>
	    Successors according to CFG: BB#8

368B	BB#3: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#1
384B		%vreg16<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg16
400B		%vreg15<def> = MOV32rm %vreg16, 1, %noreg, 120, %noreg; mem:LD4[%state_out_pos] GR32:%vreg15 GR64:%vreg16
416B		%vreg13<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg13
432B		CMP32rm %vreg15, %vreg13, 1, %noreg, 116, %noreg, %EFLAGS<imp-def>; mem:LD4[%numZ] GR32:%vreg15 GR64:%vreg13
448B		JL_1 <BB#5>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#5 BB#4

464B	BB#4: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#3
480B		JMP_1 <BB#8>
	    Successors according to CFG: BB#8

496B	BB#5: derived from LLVM BB %if.end.3
	    Predecessors according to CFG: BB#3
512B		MOV8mi <fi#1>, 1, %noreg, 0, %noreg, 1; mem:ST1[%progress_out]
528B		%vreg68<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg68
544B		%vreg66<def> = MOVSX64rm32 %vreg68, 1, %noreg, 120, %noreg; mem:LD4[%state_out_pos4] GR64_NOSP:%vreg66 GR64:%vreg68
560B		%vreg64<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg64
576B		%vreg63<def> = MOV64rm %vreg64, 1, %noreg, 80, %noreg; mem:LD8[%zbits] GR64:%vreg63,%vreg64
592B		%vreg61<def> = MOV8rm %vreg63, 1, %vreg66, 0, %noreg; mem:LD1[%arrayidx] GR8:%vreg61 GR64:%vreg63 GR64_NOSP:%vreg66
608B		%vreg58<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg58
624B		%vreg57<def> = MOV64rm %vreg58, 1, %noreg, 0, %noreg; mem:LD8[%strm5] GR64:%vreg57,%vreg58
640B		%vreg55<def> = MOV64rm %vreg57, 1, %noreg, 24, %noreg; mem:LD8[%next_out] GR64:%vreg55,%vreg57
656B		MOV8mr %vreg55, 1, %noreg, 0, %noreg, %vreg61; mem:ST1[%14] GR64:%vreg55 GR8:%vreg61
672B		%vreg51<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg51
688B		%vreg50<def> = MOV32rm %vreg51, 1, %noreg, 120, %noreg; mem:LD4[%state_out_pos6] GR32:%vreg50 GR64:%vreg51
704B		%vreg49<def> = COPY %vreg50; GR32:%vreg49,%vreg50
720B		%vreg49<def,tied1> = ADD32ri8 %vreg49<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg49
736B		MOV32mr %vreg51, 1, %noreg, 120, %noreg, %vreg49; mem:ST4[%state_out_pos6] GR64:%vreg51 GR32:%vreg49
752B		%vreg45<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg45
768B		%vreg44<def> = MOV64rm %vreg45, 1, %noreg, 0, %noreg; mem:LD8[%strm7] GR64:%vreg44,%vreg45
784B		%vreg42<def> = MOV32rm %vreg44, 1, %noreg, 32, %noreg; mem:LD4[%avail_out8] GR32:%vreg42 GR64:%vreg44
800B		%vreg41<def> = COPY %vreg42; GR32:%vreg41,%vreg42
816B		%vreg41<def,tied1> = ADD32ri8 %vreg41<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg41
832B		MOV32mr %vreg44, 1, %noreg, 32, %noreg, %vreg41; mem:ST4[%avail_out8] GR64:%vreg44 GR32:%vreg41
848B		%vreg37<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg37
864B		%vreg36<def> = MOV64rm %vreg37, 1, %noreg, 0, %noreg; mem:LD8[%strm9] GR64:%vreg36,%vreg37
880B		%vreg34<def> = MOV64rm %vreg36, 1, %noreg, 24, %noreg; mem:LD8[%next_out10] GR64:%vreg34,%vreg36
896B		%vreg33<def> = COPY %vreg34; GR64:%vreg33,%vreg34
912B		%vreg33<def,tied1> = ADD64ri8 %vreg33<tied0>, 1, %EFLAGS<imp-def,dead>; GR64:%vreg33
928B		MOV64mr %vreg36, 1, %noreg, 24, %noreg, %vreg33; mem:ST8[%next_out10] GR64:%vreg36,%vreg33
944B		%vreg29<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg29
960B		%vreg28<def> = MOV64rm %vreg29, 1, %noreg, 0, %noreg; mem:LD8[%strm11] GR64:%vreg28,%vreg29
976B		%vreg26<def> = MOV32rm %vreg28, 1, %noreg, 36, %noreg; mem:LD4[%total_out_lo32] GR32:%vreg26 GR64:%vreg28
992B		%vreg25<def> = COPY %vreg26; GR32:%vreg25,%vreg26
1008B		%vreg25<def,tied1> = ADD32ri8 %vreg25<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg25
1024B		MOV32mr %vreg28, 1, %noreg, 36, %noreg, %vreg25; mem:ST4[%total_out_lo32] GR64:%vreg28 GR32:%vreg25
1040B		%vreg21<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg21
1056B		%vreg20<def> = MOV64rm %vreg21, 1, %noreg, 0, %noreg; mem:LD8[%strm13] GR64:%vreg20,%vreg21
1072B		CMP32mi8 %vreg20, 1, %noreg, 36, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%total_out_lo3214] GR64:%vreg20
1088B		JNE_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#6

1104B	BB#6: derived from LLVM BB %if.then.16
	    Predecessors according to CFG: BB#5
1120B		%vreg76<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg76
1136B		%vreg75<def> = MOV64rm %vreg76, 1, %noreg, 0, %noreg; mem:LD8[%strm17] GR64:%vreg75,%vreg76
1152B		%vreg73<def> = MOV32rm %vreg75, 1, %noreg, 40, %noreg; mem:LD4[%total_out_hi32] GR32:%vreg73 GR64:%vreg75
1168B		%vreg72<def> = COPY %vreg73; GR32:%vreg72,%vreg73
1184B		%vreg72<def,tied1> = ADD32ri8 %vreg72<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg72
1200B		MOV32mr %vreg75, 1, %noreg, 40, %noreg, %vreg72; mem:ST4[%total_out_hi32] GR64:%vreg75 GR32:%vreg72
	    Successors according to CFG: BB#7

1216B	BB#7: derived from LLVM BB %if.end.19
	    Predecessors according to CFG: BB#5 BB#6
1232B		JMP_1 <BB#1>
	    Successors according to CFG: BB#1

1248B	BB#8: derived from LLVM BB %while.end
	    Predecessors according to CFG: BB#4 BB#2
1264B		%vreg78<def> = MOV64ri <ga:@copy_output_until_stop>; GR64:%vreg78
1280B		%vreg79<def> = COPY %vreg78; GR64:%vreg79,%vreg78
1296B		%vreg81<def> = MOV8rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD1[%progress_out] GR8:%vreg81
1312B		%vreg80<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg80
1328B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1344B		%RDI<def> = COPY %vreg79; GR64:%vreg79
1360B		%RSI<def> = COPY %vreg80; GR64:%vreg80
1376B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
1392B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1408B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1424B		STACKMAP 1, 0, %vreg81, ...; GR8:%vreg81
1440B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1456B		%AL<def> = COPY %vreg81; GR8:%vreg81
1472B		RETQ %AL<imp-use,kill>

# End machine code for function copy_output_until_stop.

********** SIMPLE REGISTER COALESCING **********
********** Function: copy_output_until_stop
********** JOINING INTERVALS ***********
while.body:
if.end:
if.end.3:
if.end.19:
if.then.16:
704B	%vreg49<def> = COPY %vreg50; GR32:%vreg49,%vreg50
	Considering merging to GR32 with %vreg50 in %vreg49
		RHS = %vreg50 [688r,704r:0)  0@688r
		LHS = %vreg49 [704r,720r:0)[720r,736r:1)  0@704r 1@720r
		merge %vreg49:0@704r into %vreg50:0@688r --> @688r
		erased:	704r	%vreg49<def> = COPY %vreg50; GR32:%vreg49,%vreg50
		updated: 688B	%vreg49<def> = MOV32rm %vreg51, 1, %noreg, 120, %noreg; mem:LD4[%state_out_pos6] GR32:%vreg49 GR64:%vreg51
	Success: %vreg50 -> %vreg49
	Result = %vreg49 [688r,720r:0)[720r,736r:1)  0@688r 1@720r
800B	%vreg41<def> = COPY %vreg42; GR32:%vreg41,%vreg42
	Considering merging to GR32 with %vreg42 in %vreg41
		RHS = %vreg42 [784r,800r:0)  0@784r
		LHS = %vreg41 [800r,816r:0)[816r,832r:1)  0@800r 1@816r
		merge %vreg41:0@800r into %vreg42:0@784r --> @784r
		erased:	800r	%vreg41<def> = COPY %vreg42; GR32:%vreg41,%vreg42
		updated: 784B	%vreg41<def> = MOV32rm %vreg44, 1, %noreg, 32, %noreg; mem:LD4[%avail_out8] GR32:%vreg41 GR64:%vreg44
	Success: %vreg42 -> %vreg41
	Result = %vreg41 [784r,816r:0)[816r,832r:1)  0@784r 1@816r
896B	%vreg33<def> = COPY %vreg34; GR64:%vreg33,%vreg34
	Considering merging to GR64 with %vreg34 in %vreg33
		RHS = %vreg34 [880r,896r:0)  0@880r
		LHS = %vreg33 [896r,912r:0)[912r,928r:1)  0@896r 1@912r
		merge %vreg33:0@896r into %vreg34:0@880r --> @880r
		erased:	896r	%vreg33<def> = COPY %vreg34; GR64:%vreg33,%vreg34
		updated: 880B	%vreg33<def> = MOV64rm %vreg36, 1, %noreg, 24, %noreg; mem:LD8[%next_out10] GR64:%vreg33,%vreg36
	Success: %vreg34 -> %vreg33
	Result = %vreg33 [880r,912r:0)[912r,928r:1)  0@880r 1@912r
992B	%vreg25<def> = COPY %vreg26; GR32:%vreg25,%vreg26
	Considering merging to GR32 with %vreg26 in %vreg25
		RHS = %vreg26 [976r,992r:0)  0@976r
		LHS = %vreg25 [992r,1008r:0)[1008r,1024r:1)  0@992r 1@1008r
		merge %vreg25:0@992r into %vreg26:0@976r --> @976r
		erased:	992r	%vreg25<def> = COPY %vreg26; GR32:%vreg25,%vreg26
		updated: 976B	%vreg25<def> = MOV32rm %vreg28, 1, %noreg, 36, %noreg; mem:LD4[%total_out_lo32] GR32:%vreg25 GR64:%vreg28
	Success: %vreg26 -> %vreg25
	Result = %vreg25 [976r,1008r:0)[1008r,1024r:1)  0@976r 1@1008r
1168B	%vreg72<def> = COPY %vreg73; GR32:%vreg72,%vreg73
	Considering merging to GR32 with %vreg73 in %vreg72
		RHS = %vreg73 [1152r,1168r:0)  0@1152r
		LHS = %vreg72 [1168r,1184r:0)[1184r,1200r:1)  0@1168r 1@1184r
		merge %vreg72:0@1168r into %vreg73:0@1152r --> @1152r
		erased:	1168r	%vreg72<def> = COPY %vreg73; GR32:%vreg72,%vreg73
		updated: 1152B	%vreg72<def> = MOV32rm %vreg75, 1, %noreg, 40, %noreg; mem:LD4[%total_out_hi32] GR32:%vreg72 GR64:%vreg75
	Success: %vreg73 -> %vreg72
	Result = %vreg72 [1152r,1184r:0)[1184r,1200r:1)  0@1152r 1@1184r
if.then:
if.then.2:
while.end:
1344B	%RDI<def> = COPY %vreg79; GR64:%vreg79
	Considering merging %vreg79 with %RDI
	Can only merge into reserved registers.
1360B	%RSI<def> = COPY %vreg80; GR64:%vreg80
	Considering merging %vreg80 with %RSI
	Can only merge into reserved registers.
1456B	%AL<def> = COPY %vreg81; GR8:%vreg81
	Considering merging %vreg81 with %AL
	Can only merge into reserved registers.
entry:
16B	%vreg0<def> = COPY %RDI; GR64:%vreg0
	Considering merging %vreg0 with %RDI
	Can only merge into reserved registers.
112B	%RDI<def> = COPY %vreg3; GR64:%vreg3
	Considering merging %vreg3 with %RDI
	Can only merge into reserved registers.
128B	%RSI<def> = COPY %vreg4; GR64:%vreg4
	Considering merging %vreg4 with %RSI
	Can only merge into reserved registers.
1280B	%vreg79<def> = COPY %vreg78; GR64:%vreg79,%vreg78
	Considering merging to GR64 with %vreg78 in %vreg79
		RHS = %vreg78 [1264r,1280r:0)  0@1264r
		LHS = %vreg79 [1280r,1344r:0)  0@1280r
		merge %vreg79:0@1280r into %vreg78:0@1264r --> @1264r
		erased:	1280r	%vreg79<def> = COPY %vreg78; GR64:%vreg79,%vreg78
		updated: 1264B	%vreg79<def> = MOV64ri <ga:@copy_output_until_stop>; GR64:%vreg79
	Success: %vreg78 -> %vreg79
	Result = %vreg79 [1264r,1344r:0)  0@1264r
32B	%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
	Considering merging to GR64 with %vreg0 in %vreg1
		RHS = %vreg0 [16r,32r:0)  0@16r
		LHS = %vreg1 [32r,224r:0)  0@32r
		merge %vreg1:0@32r into %vreg0:0@16r --> @16r
		erased:	32r	%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
		updated: 16B	%vreg1<def> = COPY %RDI; GR64:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [16r,224r:0)  0@16r
64B	%vreg3<def> = COPY %vreg2; GR64:%vreg3,%vreg2
	Considering merging to GR64 with %vreg2 in %vreg3
		RHS = %vreg2 [48r,64r:0)  0@48r
		LHS = %vreg3 [64r,112r:0)  0@64r
		merge %vreg3:0@64r into %vreg2:0@48r --> @48r
		erased:	64r	%vreg3<def> = COPY %vreg2; GR64:%vreg3,%vreg2
		updated: 48B	%vreg3<def> = MOV64ri <ga:@copy_output_until_stop>; GR64:%vreg3
	Success: %vreg2 -> %vreg3
	Result = %vreg3 [48r,112r:0)  0@48r
1344B	%RDI<def> = COPY %vreg79; GR64:%vreg79
	Considering merging %vreg79 with %RDI
	Can only merge into reserved registers.
112B	%RDI<def> = COPY %vreg3; GR64:%vreg3
	Considering merging %vreg3 with %RDI
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
DIL [0B,16r:0)[112r,144r:2)[1344r,1376r:1)  0@0B-phi 1@1344r 2@112r
%vreg1 [16r,224r:0)  0@16r
%vreg3 [48r,112r:0)  0@48r
%vreg4 [80r,128r:0)  0@80r
%vreg8 [288r,304r:0)  0@288r
%vreg9 [272r,288r:0)  0@272r
%vreg13 [416r,432r:0)  0@416r
%vreg15 [400r,432r:0)  0@400r
%vreg16 [384r,400r:0)  0@384r
%vreg20 [1056r,1072r:0)  0@1056r
%vreg21 [1040r,1056r:0)  0@1040r
%vreg25 [976r,1008r:0)[1008r,1024r:1)  0@976r 1@1008r
%vreg28 [960r,1024r:0)  0@960r
%vreg29 [944r,960r:0)  0@944r
%vreg33 [880r,912r:0)[912r,928r:1)  0@880r 1@912r
%vreg36 [864r,928r:0)  0@864r
%vreg37 [848r,864r:0)  0@848r
%vreg41 [784r,816r:0)[816r,832r:1)  0@784r 1@816r
%vreg44 [768r,832r:0)  0@768r
%vreg45 [752r,768r:0)  0@752r
%vreg49 [688r,720r:0)[720r,736r:1)  0@688r 1@720r
%vreg51 [672r,736r:0)  0@672r
%vreg55 [640r,656r:0)  0@640r
%vreg57 [624r,640r:0)  0@624r
%vreg58 [608r,624r:0)  0@608r
%vreg61 [592r,656r:0)  0@592r
%vreg63 [576r,592r:0)  0@576r
%vreg64 [560r,576r:0)  0@560r
%vreg66 [544r,592r:0)  0@544r
%vreg68 [528r,544r:0)  0@528r
%vreg72 [1152r,1184r:0)[1184r,1200r:1)  0@1152r 1@1184r
%vreg75 [1136r,1200r:0)  0@1136r
%vreg76 [1120r,1136r:0)  0@1120r
%vreg79 [1264r,1344r:0)  0@1264r
%vreg80 [1312r,1360r:0)  0@1312r
%vreg81 [1296r,1456r:0)  0@1296r
RegMasks: 144r 1376r
********** MACHINEINSTRS **********
# Machine code for function copy_output_until_stop: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=8, align=8, at location [SP+8]
  fi#1: size=1, align=1, at location [SP+8]
Function Live Ins: %RDI in %vreg0

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI
16B		%vreg1<def> = COPY %RDI; GR64:%vreg1
48B		%vreg3<def> = MOV64ri <ga:@copy_output_until_stop>; GR64:%vreg3
80B		%vreg4<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg4
96B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
112B		%RDI<def> = COPY %vreg3; GR64:%vreg3
128B		%RSI<def> = COPY %vreg4; GR64:%vreg4
144B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
160B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
192B		STACKMAP 0, 0, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack0] GR64:%vreg1
208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%s.addr] GR64:%vreg1
240B		MOV8mi <fi#1>, 1, %noreg, 0, %noreg, 0; mem:ST1[%progress_out]
	    Successors according to CFG: BB#1

256B	BB#1: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#0 BB#7
272B		%vreg9<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg9
288B		%vreg8<def> = MOV64rm %vreg9, 1, %noreg, 0, %noreg; mem:LD8[%strm] GR64:%vreg8,%vreg9
304B		CMP32mi8 %vreg8, 1, %noreg, 32, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_out] GR64:%vreg8
320B		JNE_1 <BB#3>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#3 BB#2

336B	BB#2: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#1
352B		JMP_1 <BB#8>
	    Successors according to CFG: BB#8

368B	BB#3: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#1
384B		%vreg16<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg16
400B		%vreg15<def> = MOV32rm %vreg16, 1, %noreg, 120, %noreg; mem:LD4[%state_out_pos] GR32:%vreg15 GR64:%vreg16
416B		%vreg13<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg13
432B		CMP32rm %vreg15, %vreg13, 1, %noreg, 116, %noreg, %EFLAGS<imp-def>; mem:LD4[%numZ] GR32:%vreg15 GR64:%vreg13
448B		JL_1 <BB#5>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#5 BB#4

464B	BB#4: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#3
480B		JMP_1 <BB#8>
	    Successors according to CFG: BB#8

496B	BB#5: derived from LLVM BB %if.end.3
	    Predecessors according to CFG: BB#3
512B		MOV8mi <fi#1>, 1, %noreg, 0, %noreg, 1; mem:ST1[%progress_out]
528B		%vreg68<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg68
544B		%vreg66<def> = MOVSX64rm32 %vreg68, 1, %noreg, 120, %noreg; mem:LD4[%state_out_pos4] GR64_NOSP:%vreg66 GR64:%vreg68
560B		%vreg64<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg64
576B		%vreg63<def> = MOV64rm %vreg64, 1, %noreg, 80, %noreg; mem:LD8[%zbits] GR64:%vreg63,%vreg64
592B		%vreg61<def> = MOV8rm %vreg63, 1, %vreg66, 0, %noreg; mem:LD1[%arrayidx] GR8:%vreg61 GR64:%vreg63 GR64_NOSP:%vreg66
608B		%vreg58<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg58
624B		%vreg57<def> = MOV64rm %vreg58, 1, %noreg, 0, %noreg; mem:LD8[%strm5] GR64:%vreg57,%vreg58
640B		%vreg55<def> = MOV64rm %vreg57, 1, %noreg, 24, %noreg; mem:LD8[%next_out] GR64:%vreg55,%vreg57
656B		MOV8mr %vreg55, 1, %noreg, 0, %noreg, %vreg61; mem:ST1[%14] GR64:%vreg55 GR8:%vreg61
672B		%vreg51<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg51
688B		%vreg49<def> = MOV32rm %vreg51, 1, %noreg, 120, %noreg; mem:LD4[%state_out_pos6] GR32:%vreg49 GR64:%vreg51
720B		%vreg49<def,tied1> = ADD32ri8 %vreg49<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg49
736B		MOV32mr %vreg51, 1, %noreg, 120, %noreg, %vreg49; mem:ST4[%state_out_pos6] GR64:%vreg51 GR32:%vreg49
752B		%vreg45<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg45
768B		%vreg44<def> = MOV64rm %vreg45, 1, %noreg, 0, %noreg; mem:LD8[%strm7] GR64:%vreg44,%vreg45
784B		%vreg41<def> = MOV32rm %vreg44, 1, %noreg, 32, %noreg; mem:LD4[%avail_out8] GR32:%vreg41 GR64:%vreg44
816B		%vreg41<def,tied1> = ADD32ri8 %vreg41<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg41
832B		MOV32mr %vreg44, 1, %noreg, 32, %noreg, %vreg41; mem:ST4[%avail_out8] GR64:%vreg44 GR32:%vreg41
848B		%vreg37<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg37
864B		%vreg36<def> = MOV64rm %vreg37, 1, %noreg, 0, %noreg; mem:LD8[%strm9] GR64:%vreg36,%vreg37
880B		%vreg33<def> = MOV64rm %vreg36, 1, %noreg, 24, %noreg; mem:LD8[%next_out10] GR64:%vreg33,%vreg36
912B		%vreg33<def,tied1> = ADD64ri8 %vreg33<tied0>, 1, %EFLAGS<imp-def,dead>; GR64:%vreg33
928B		MOV64mr %vreg36, 1, %noreg, 24, %noreg, %vreg33; mem:ST8[%next_out10] GR64:%vreg36,%vreg33
944B		%vreg29<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg29
960B		%vreg28<def> = MOV64rm %vreg29, 1, %noreg, 0, %noreg; mem:LD8[%strm11] GR64:%vreg28,%vreg29
976B		%vreg25<def> = MOV32rm %vreg28, 1, %noreg, 36, %noreg; mem:LD4[%total_out_lo32] GR32:%vreg25 GR64:%vreg28
1008B		%vreg25<def,tied1> = ADD32ri8 %vreg25<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg25
1024B		MOV32mr %vreg28, 1, %noreg, 36, %noreg, %vreg25; mem:ST4[%total_out_lo32] GR64:%vreg28 GR32:%vreg25
1040B		%vreg21<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg21
1056B		%vreg20<def> = MOV64rm %vreg21, 1, %noreg, 0, %noreg; mem:LD8[%strm13] GR64:%vreg20,%vreg21
1072B		CMP32mi8 %vreg20, 1, %noreg, 36, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%total_out_lo3214] GR64:%vreg20
1088B		JNE_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#6

1104B	BB#6: derived from LLVM BB %if.then.16
	    Predecessors according to CFG: BB#5
1120B		%vreg76<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg76
1136B		%vreg75<def> = MOV64rm %vreg76, 1, %noreg, 0, %noreg; mem:LD8[%strm17] GR64:%vreg75,%vreg76
1152B		%vreg72<def> = MOV32rm %vreg75, 1, %noreg, 40, %noreg; mem:LD4[%total_out_hi32] GR32:%vreg72 GR64:%vreg75
1184B		%vreg72<def,tied1> = ADD32ri8 %vreg72<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg72
1200B		MOV32mr %vreg75, 1, %noreg, 40, %noreg, %vreg72; mem:ST4[%total_out_hi32] GR64:%vreg75 GR32:%vreg72
	    Successors according to CFG: BB#7

1216B	BB#7: derived from LLVM BB %if.end.19
	    Predecessors according to CFG: BB#5 BB#6
1232B		JMP_1 <BB#1>
	    Successors according to CFG: BB#1

1248B	BB#8: derived from LLVM BB %while.end
	    Predecessors according to CFG: BB#4 BB#2
1264B		%vreg79<def> = MOV64ri <ga:@copy_output_until_stop>; GR64:%vreg79
1296B		%vreg81<def> = MOV8rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD1[%progress_out] GR8:%vreg81
1312B		%vreg80<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg80
1328B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1344B		%RDI<def> = COPY %vreg79; GR64:%vreg79
1360B		%RSI<def> = COPY %vreg80; GR64:%vreg80
1376B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
1392B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1408B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1424B		STACKMAP 1, 0, %vreg81, ...; GR8:%vreg81
1440B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1456B		%AL<def> = COPY %vreg81; GR8:%vreg81
1472B		RETQ %AL<imp-use,kill>

# End machine code for function copy_output_until_stop.

AllocationOrder(SEGMENT_REG) = [ ]
********** GREEDY REGISTER ALLOCATION **********
********** Function: copy_output_until_stop
********** INTERVALS **********
DIL [0B,16r:0)[112r,144r:2)[1344r,1376r:1)  0@0B-phi 1@1344r 2@112r
%vreg1 [16r,224r:0)  0@16r
%vreg3 [48r,112r:0)  0@48r
%vreg4 [80r,128r:0)  0@80r
%vreg8 [288r,304r:0)  0@288r
%vreg9 [272r,288r:0)  0@272r
%vreg13 [416r,432r:0)  0@416r
%vreg15 [400r,432r:0)  0@400r
%vreg16 [384r,400r:0)  0@384r
%vreg20 [1056r,1072r:0)  0@1056r
%vreg21 [1040r,1056r:0)  0@1040r
%vreg25 [976r,1008r:0)[1008r,1024r:1)  0@976r 1@1008r
%vreg28 [960r,1024r:0)  0@960r
%vreg29 [944r,960r:0)  0@944r
%vreg33 [880r,912r:0)[912r,928r:1)  0@880r 1@912r
%vreg36 [864r,928r:0)  0@864r
%vreg37 [848r,864r:0)  0@848r
%vreg41 [784r,816r:0)[816r,832r:1)  0@784r 1@816r
%vreg44 [768r,832r:0)  0@768r
%vreg45 [752r,768r:0)  0@752r
%vreg49 [688r,720r:0)[720r,736r:1)  0@688r 1@720r
%vreg51 [672r,736r:0)  0@672r
%vreg55 [640r,656r:0)  0@640r
%vreg57 [624r,640r:0)  0@624r
%vreg58 [608r,624r:0)  0@608r
%vreg61 [592r,656r:0)  0@592r
%vreg63 [576r,592r:0)  0@576r
%vreg64 [560r,576r:0)  0@560r
%vreg66 [544r,592r:0)  0@544r
%vreg68 [528r,544r:0)  0@528r
%vreg72 [1152r,1184r:0)[1184r,1200r:1)  0@1152r 1@1184r
%vreg75 [1136r,1200r:0)  0@1136r
%vreg76 [1120r,1136r:0)  0@1120r
%vreg79 [1264r,1344r:0)  0@1264r
%vreg80 [1312r,1360r:0)  0@1312r
%vreg81 [1296r,1456r:0)  0@1296r
RegMasks: 144r 1376r
********** MACHINEINSTRS **********
# Machine code for function copy_output_until_stop: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=8, align=8, at location [SP+8]
  fi#1: size=1, align=1, at location [SP+8]
Function Live Ins: %RDI in %vreg0

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI
16B		%vreg1<def> = COPY %RDI; GR64:%vreg1
48B		%vreg3<def> = MOV64ri <ga:@copy_output_until_stop>; GR64:%vreg3
80B		%vreg4<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg4
96B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
112B		%RDI<def> = COPY %vreg3; GR64:%vreg3
128B		%RSI<def> = COPY %vreg4; GR64:%vreg4
144B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
160B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
192B		STACKMAP 0, 0, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack0] GR64:%vreg1
208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%s.addr] GR64:%vreg1
240B		MOV8mi <fi#1>, 1, %noreg, 0, %noreg, 0; mem:ST1[%progress_out]
	    Successors according to CFG: BB#1

256B	BB#1: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#0 BB#7
272B		%vreg9<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg9
288B		%vreg8<def> = MOV64rm %vreg9, 1, %noreg, 0, %noreg; mem:LD8[%strm] GR64:%vreg8,%vreg9
304B		CMP32mi8 %vreg8, 1, %noreg, 32, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_out] GR64:%vreg8
320B		JNE_1 <BB#3>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#3 BB#2

336B	BB#2: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#1
352B		JMP_1 <BB#8>
	    Successors according to CFG: BB#8

368B	BB#3: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#1
384B		%vreg16<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg16
400B		%vreg15<def> = MOV32rm %vreg16, 1, %noreg, 120, %noreg; mem:LD4[%state_out_pos] GR32:%vreg15 GR64:%vreg16
416B		%vreg13<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg13
432B		CMP32rm %vreg15, %vreg13, 1, %noreg, 116, %noreg, %EFLAGS<imp-def>; mem:LD4[%numZ] GR32:%vreg15 GR64:%vreg13
448B		JL_1 <BB#5>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#5 BB#4

464B	BB#4: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#3
480B		JMP_1 <BB#8>
	    Successors according to CFG: BB#8

496B	BB#5: derived from LLVM BB %if.end.3
	    Predecessors according to CFG: BB#3
512B		MOV8mi <fi#1>, 1, %noreg, 0, %noreg, 1; mem:ST1[%progress_out]
528B		%vreg68<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg68
544B		%vreg66<def> = MOVSX64rm32 %vreg68, 1, %noreg, 120, %noreg; mem:LD4[%state_out_pos4] GR64_NOSP:%vreg66 GR64:%vreg68
560B		%vreg64<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg64
576B		%vreg63<def> = MOV64rm %vreg64, 1, %noreg, 80, %noreg; mem:LD8[%zbits] GR64:%vreg63,%vreg64
592B		%vreg61<def> = MOV8rm %vreg63, 1, %vreg66, 0, %noreg; mem:LD1[%arrayidx] GR8:%vreg61 GR64:%vreg63 GR64_NOSP:%vreg66
608B		%vreg58<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg58
624B		%vreg57<def> = MOV64rm %vreg58, 1, %noreg, 0, %noreg; mem:LD8[%strm5] GR64:%vreg57,%vreg58
640B		%vreg55<def> = MOV64rm %vreg57, 1, %noreg, 24, %noreg; mem:LD8[%next_out] GR64:%vreg55,%vreg57
656B		MOV8mr %vreg55, 1, %noreg, 0, %noreg, %vreg61; mem:ST1[%14] GR64:%vreg55 GR8:%vreg61
672B		%vreg51<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg51
688B		%vreg49<def> = MOV32rm %vreg51, 1, %noreg, 120, %noreg; mem:LD4[%state_out_pos6] GR32:%vreg49 GR64:%vreg51
720B		%vreg49<def,tied1> = ADD32ri8 %vreg49<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg49
736B		MOV32mr %vreg51, 1, %noreg, 120, %noreg, %vreg49; mem:ST4[%state_out_pos6] GR64:%vreg51 GR32:%vreg49
752B		%vreg45<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg45
768B		%vreg44<def> = MOV64rm %vreg45, 1, %noreg, 0, %noreg; mem:LD8[%strm7] GR64:%vreg44,%vreg45
784B		%vreg41<def> = MOV32rm %vreg44, 1, %noreg, 32, %noreg; mem:LD4[%avail_out8] GR32:%vreg41 GR64:%vreg44
816B		%vreg41<def,tied1> = ADD32ri8 %vreg41<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg41
832B		MOV32mr %vreg44, 1, %noreg, 32, %noreg, %vreg41; mem:ST4[%avail_out8] GR64:%vreg44 GR32:%vreg41
848B		%vreg37<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg37
864B		%vreg36<def> = MOV64rm %vreg37, 1, %noreg, 0, %noreg; mem:LD8[%strm9] GR64:%vreg36,%vreg37
880B		%vreg33<def> = MOV64rm %vreg36, 1, %noreg, 24, %noreg; mem:LD8[%next_out10] GR64:%vreg33,%vreg36
912B		%vreg33<def,tied1> = ADD64ri8 %vreg33<tied0>, 1, %EFLAGS<imp-def,dead>; GR64:%vreg33
928B		MOV64mr %vreg36, 1, %noreg, 24, %noreg, %vreg33; mem:ST8[%next_out10] GR64:%vreg36,%vreg33
944B		%vreg29<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg29
960B		%vreg28<def> = MOV64rm %vreg29, 1, %noreg, 0, %noreg; mem:LD8[%strm11] GR64:%vreg28,%vreg29
976B		%vreg25<def> = MOV32rm %vreg28, 1, %noreg, 36, %noreg; mem:LD4[%total_out_lo32] GR32:%vreg25 GR64:%vreg28
1008B		%vreg25<def,tied1> = ADD32ri8 %vreg25<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg25
1024B		MOV32mr %vreg28, 1, %noreg, 36, %noreg, %vreg25; mem:ST4[%total_out_lo32] GR64:%vreg28 GR32:%vreg25
1040B		%vreg21<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg21
1056B		%vreg20<def> = MOV64rm %vreg21, 1, %noreg, 0, %noreg; mem:LD8[%strm13] GR64:%vreg20,%vreg21
1072B		CMP32mi8 %vreg20, 1, %noreg, 36, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%total_out_lo3214] GR64:%vreg20
1088B		JNE_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#6

1104B	BB#6: derived from LLVM BB %if.then.16
	    Predecessors according to CFG: BB#5
1120B		%vreg76<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg76
1136B		%vreg75<def> = MOV64rm %vreg76, 1, %noreg, 0, %noreg; mem:LD8[%strm17] GR64:%vreg75,%vreg76
1152B		%vreg72<def> = MOV32rm %vreg75, 1, %noreg, 40, %noreg; mem:LD4[%total_out_hi32] GR32:%vreg72 GR64:%vreg75
1184B		%vreg72<def,tied1> = ADD32ri8 %vreg72<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg72
1200B		MOV32mr %vreg75, 1, %noreg, 40, %noreg, %vreg72; mem:ST4[%total_out_hi32] GR64:%vreg75 GR32:%vreg72
	    Successors according to CFG: BB#7

1216B	BB#7: derived from LLVM BB %if.end.19
	    Predecessors according to CFG: BB#5 BB#6
1232B		JMP_1 <BB#1>
	    Successors according to CFG: BB#1

1248B	BB#8: derived from LLVM BB %while.end
	    Predecessors according to CFG: BB#4 BB#2
1264B		%vreg79<def> = MOV64ri <ga:@copy_output_until_stop>; GR64:%vreg79
1296B		%vreg81<def> = MOV8rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD1[%progress_out] GR8:%vreg81
1312B		%vreg80<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg80
1328B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1344B		%RDI<def> = COPY %vreg79; GR64:%vreg79
1360B		%RSI<def> = COPY %vreg80; GR64:%vreg80
1376B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
1392B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1408B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1424B		STACKMAP 1, 0, %vreg81, ...; GR8:%vreg81
1440B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1456B		%AL<def> = COPY %vreg81; GR8:%vreg81
1472B		RETQ %AL<imp-use,kill>

# End machine code for function copy_output_until_stop.


selectOrSplit GR64:%vreg1 [16r,224r:0)  0@16r w=4.983552e-03
hints: %RDI
missed hint %RDI
assigning %vreg1 to %RBX: BH [16r,224r:0)  0@16r BL [16r,224r:0)  0@16r

selectOrSplit GR64:%vreg3 [48r,112r:0)  0@48r w=2.176724e-03
hints: %RDI
assigning %vreg3 to %RDI: DIL [48r,112r:0)  0@48r

selectOrSplit GR64:%vreg4 [80r,128r:0)  0@80r w=4.508928e-03
hints: %RSI
assigning %vreg4 to %RSI: SIL [80r,128r:0)  0@80r

selectOrSplit GR64:%vreg79 [1264r,1344r:0)  0@1264r w=2.104166e-03
hints: %RDI
assigning %vreg79 to %RDI: DIL [1264r,1344r:0)  0@1264r

selectOrSplit GR8:%vreg81 [1296r,1456r:0)  0@1296r w=5.410714e-03
hints: %AL
missed hint %AL
assigning %vreg81 to %BL: BL [1296r,1456r:0)  0@1296r

selectOrSplit GR64:%vreg80 [1312r,1360r:0)  0@1312r w=4.508928e-03
hints: %RSI
assigning %vreg80 to %RSI: SIL [1312r,1360r:0)  0@1312r

selectOrSplit GR64:%vreg9 [272r,288r:0)  0@272r w=inf
assigning %vreg9 to %RAX: AH [272r,288r:0)  0@272r AL [272r,288r:0)  0@272r

selectOrSplit GR64:%vreg8 [288r,304r:0)  0@288r w=inf
assigning %vreg8 to %RAX: AH [288r,304r:0)  0@288r AL [288r,304r:0)  0@288r

selectOrSplit GR64:%vreg16 [384r,400r:0)  0@384r w=inf
assigning %vreg16 to %RAX: AH [384r,400r:0)  0@384r AL [384r,400r:0)  0@384r

selectOrSplit GR32:%vreg15 [400r,432r:0)  0@400r w=3.053585e-03
assigning %vreg15 to %EAX: AH [400r,432r:0)  0@400r AL [400r,432r:0)  0@400r

selectOrSplit GR64:%vreg13 [416r,432r:0)  0@416r w=inf
assigning %vreg13 to %RCX: CH [416r,432r:0)  0@416r CL [416r,432r:0)  0@416r

selectOrSplit GR64:%vreg68 [528r,544r:0)  0@528r w=inf
assigning %vreg68 to %RAX: AH [528r,544r:0)  0@528r AL [528r,544r:0)  0@528r

selectOrSplit GR64_NOSP:%vreg66 [544r,592r:0)  0@544r w=1.424772e-03
assigning %vreg66 to %RAX: AH [544r,592r:0)  0@544r AL [544r,592r:0)  0@544r

selectOrSplit GR64:%vreg64 [560r,576r:0)  0@560r w=inf
assigning %vreg64 to %RCX: CH [560r,576r:0)  0@560r CL [560r,576r:0)  0@560r

selectOrSplit GR64:%vreg63 [576r,592r:0)  0@576r w=inf
assigning %vreg63 to %RCX: CH [576r,592r:0)  0@576r CL [576r,592r:0)  0@576r

selectOrSplit GR8:%vreg61 [592r,656r:0)  0@592r w=1.375642e-03
assigning %vreg61 to %AL: AL [592r,656r:0)  0@592r

selectOrSplit GR64:%vreg58 [608r,624r:0)  0@608r w=inf
assigning %vreg58 to %RCX: CH [608r,624r:0)  0@608r CL [608r,624r:0)  0@608r

selectOrSplit GR64:%vreg57 [624r,640r:0)  0@624r w=inf
assigning %vreg57 to %RCX: CH [624r,640r:0)  0@624r CL [624r,640r:0)  0@624r

selectOrSplit GR64:%vreg55 [640r,656r:0)  0@640r w=inf
assigning %vreg55 to %RCX: CH [640r,656r:0)  0@640r CL [640r,656r:0)  0@640r

selectOrSplit GR64:%vreg51 [672r,736r:0)  0@672r w=2.063463e-03
assigning %vreg51 to %RAX: AH [672r,736r:0)  0@672r AL [672r,736r:0)  0@672r

selectOrSplit GR32:%vreg49 [688r,720r:0)[720r,736r:1)  0@688r 1@720r w=inf
assigning %vreg49 to %ECX: CH [688r,720r:0)[720r,736r:1)  0@688r 1@720r CL [688r,720r:0)[720r,736r:1)  0@688r 1@720r

selectOrSplit GR64:%vreg45 [752r,768r:0)  0@752r w=inf
assigning %vreg45 to %RAX: AH [752r,768r:0)  0@752r AL [752r,768r:0)  0@752r

selectOrSplit GR64:%vreg44 [768r,832r:0)  0@768r w=2.063463e-03
assigning %vreg44 to %RAX: AH [768r,832r:0)  0@768r AL [768r,832r:0)  0@768r

selectOrSplit GR32:%vreg41 [784r,816r:0)[816r,832r:1)  0@784r 1@816r w=inf
assigning %vreg41 to %ECX: CH [784r,816r:0)[816r,832r:1)  0@784r 1@816r CL [784r,816r:0)[816r,832r:1)  0@784r 1@816r

selectOrSplit GR64:%vreg37 [848r,864r:0)  0@848r w=inf
assigning %vreg37 to %RAX: AH [848r,864r:0)  0@848r AL [848r,864r:0)  0@848r

selectOrSplit GR64:%vreg36 [864r,928r:0)  0@864r w=2.063463e-03
assigning %vreg36 to %RAX: AH [864r,928r:0)  0@864r AL [864r,928r:0)  0@864r

selectOrSplit GR64:%vreg33 [880r,912r:0)[912r,928r:1)  0@880r 1@912r w=inf
assigning %vreg33 to %RCX: CH [880r,912r:0)[912r,928r:1)  0@880r 1@912r CL [880r,912r:0)[912r,928r:1)  0@880r 1@912r

selectOrSplit GR64:%vreg29 [944r,960r:0)  0@944r w=inf
assigning %vreg29 to %RAX: AH [944r,960r:0)  0@944r AL [944r,960r:0)  0@944r

selectOrSplit GR64:%vreg28 [960r,1024r:0)  0@960r w=2.063463e-03
assigning %vreg28 to %RAX: AH [960r,1024r:0)  0@960r AL [960r,1024r:0)  0@960r

selectOrSplit GR32:%vreg25 [976r,1008r:0)[1008r,1024r:1)  0@976r 1@1008r w=inf
assigning %vreg25 to %ECX: CH [976r,1008r:0)[1008r,1024r:1)  0@976r 1@1008r CL [976r,1008r:0)[1008r,1024r:1)  0@976r 1@1008r

selectOrSplit GR64:%vreg21 [1040r,1056r:0)  0@1040r w=inf
assigning %vreg21 to %RAX: AH [1040r,1056r:0)  0@1040r AL [1040r,1056r:0)  0@1040r

selectOrSplit GR64:%vreg20 [1056r,1072r:0)  0@1056r w=inf
assigning %vreg20 to %RAX: AH [1056r,1072r:0)  0@1056r AL [1056r,1072r:0)  0@1056r

selectOrSplit GR64:%vreg76 [1120r,1136r:0)  0@1120r w=inf
assigning %vreg76 to %RAX: AH [1120r,1136r:0)  0@1120r AL [1120r,1136r:0)  0@1120r

selectOrSplit GR64:%vreg75 [1136r,1200r:0)  0@1136r w=1.100514e-03
assigning %vreg75 to %RAX: AH [1136r,1200r:0)  0@1136r AL [1136r,1200r:0)  0@1136r

selectOrSplit GR32:%vreg72 [1152r,1184r:0)[1184r,1200r:1)  0@1152r 1@1184r w=inf
assigning %vreg72 to %ECX: CH [1152r,1184r:0)[1184r,1200r:1)  0@1152r 1@1184r CL [1152r,1184r:0)[1184r,1200r:1)  0@1152r 1@1184r

********** STACK TRANSFORMATION METADATA **********
********** Function: copy_output_until_stop
********** REGISTER MAP **********
[%vreg1 -> %RBX] GR64
[%vreg3 -> %RDI] GR64
[%vreg4 -> %RSI] GR64
[%vreg8 -> %RAX] GR64
[%vreg9 -> %RAX] GR64
[%vreg13 -> %RCX] GR64
[%vreg15 -> %EAX] GR32
[%vreg16 -> %RAX] GR64
[%vreg20 -> %RAX] GR64
[%vreg21 -> %RAX] GR64
[%vreg25 -> %ECX] GR32
[%vreg28 -> %RAX] GR64
[%vreg29 -> %RAX] GR64
[%vreg33 -> %RCX] GR64
[%vreg36 -> %RAX] GR64
[%vreg37 -> %RAX] GR64
[%vreg41 -> %ECX] GR32
[%vreg44 -> %RAX] GR64
[%vreg45 -> %RAX] GR64
[%vreg49 -> %ECX] GR32
[%vreg51 -> %RAX] GR64
[%vreg55 -> %RCX] GR64
[%vreg57 -> %RCX] GR64
[%vreg58 -> %RCX] GR64
[%vreg61 -> %AL] GR8
[%vreg63 -> %RCX] GR64
[%vreg64 -> %RCX] GR64
[%vreg66 -> %RAX] GR64_NOSP
[%vreg68 -> %RAX] GR64
[%vreg72 -> %ECX] GR32
[%vreg75 -> %RAX] GR64
[%vreg76 -> %RAX] GR64
[%vreg79 -> %RDI] GR64
[%vreg80 -> %RSI] GR64
[%vreg81 -> %BL] GR8


Stackmap 0:
  STACKMAP 0, 0, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack0] GR64:%vreg1

i8* %progress_out: in stack slot 1 (size: 1)
%struct.EState* %s: in register %RBX (vreg 1)
%struct.EState** %s.addr: in stack slot 0 (size: 8)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, %vreg81, ...; GR8:%vreg81

i8 %32: in register %BL (vreg 81)

Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack0] GR64:%vreg1
  -> Call instruction SlotIndex 144B, searching vregs 0 -> 82 and stack slots -1 -> 2

  STACKMAP 1, 0, %vreg81, ...; GR8:%vreg81
  -> Call instruction SlotIndex 1376B, searching vregs 0 -> 82 and stack slots -1 -> 2

********** REWRITE VIRTUAL REGISTERS **********
********** Function: copy_output_until_stop
********** REGISTER MAP **********
[%vreg1 -> %RBX] GR64
[%vreg3 -> %RDI] GR64
[%vreg4 -> %RSI] GR64
[%vreg8 -> %RAX] GR64
[%vreg9 -> %RAX] GR64
[%vreg13 -> %RCX] GR64
[%vreg15 -> %EAX] GR32
[%vreg16 -> %RAX] GR64
[%vreg20 -> %RAX] GR64
[%vreg21 -> %RAX] GR64
[%vreg25 -> %ECX] GR32
[%vreg28 -> %RAX] GR64
[%vreg29 -> %RAX] GR64
[%vreg33 -> %RCX] GR64
[%vreg36 -> %RAX] GR64
[%vreg37 -> %RAX] GR64
[%vreg41 -> %ECX] GR32
[%vreg44 -> %RAX] GR64
[%vreg45 -> %RAX] GR64
[%vreg49 -> %ECX] GR32
[%vreg51 -> %RAX] GR64
[%vreg55 -> %RCX] GR64
[%vreg57 -> %RCX] GR64
[%vreg58 -> %RCX] GR64
[%vreg61 -> %AL] GR8
[%vreg63 -> %RCX] GR64
[%vreg64 -> %RCX] GR64
[%vreg66 -> %RAX] GR64_NOSP
[%vreg68 -> %RAX] GR64
[%vreg72 -> %ECX] GR32
[%vreg75 -> %RAX] GR64
[%vreg76 -> %RAX] GR64
[%vreg79 -> %RDI] GR64
[%vreg80 -> %RSI] GR64
[%vreg81 -> %BL] GR8

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI
16B		%vreg1<def> = COPY %RDI; GR64:%vreg1
48B		%vreg3<def> = MOV64ri <ga:@copy_output_until_stop>; GR64:%vreg3
80B		%vreg4<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg4
96B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
112B		%RDI<def> = COPY %vreg3<kill>; GR64:%vreg3
128B		%RSI<def> = COPY %vreg4<kill>; GR64:%vreg4
144B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
160B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
192B		STACKMAP 0, 0, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack0] GR64:%vreg1
208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1<kill>; mem:ST8[%s.addr] GR64:%vreg1
240B		MOV8mi <fi#1>, 1, %noreg, 0, %noreg, 0; mem:ST1[%progress_out]
	    Successors according to CFG: BB#1
> %RBX<def> = COPY %RDI
> %RDI<def> = MOV64ri <ga:@copy_output_until_stop>
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 0, 0, 0, <fi#1>, 0, %RBX, 0, <fi#0>, 0, ...; mem:LD8[FixedStack1](align=1) LD8[FixedStack0]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %RBX<kill>; mem:ST8[%s.addr]
> MOV8mi <fi#1>, 1, %noreg, 0, %noreg, 0; mem:ST1[%progress_out]
256B	BB#1: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#0 BB#7
272B		%vreg9<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg9
288B		%vreg8<def> = MOV64rm %vreg9<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm] GR64:%vreg8,%vreg9
304B		CMP32mi8 %vreg8<kill>, 1, %noreg, 32, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_out] GR64:%vreg8
320B		JNE_1 <BB#3>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#3 BB#2
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm]
> CMP32mi8 %RAX<kill>, 1, %noreg, 32, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_out]
> JNE_1 <BB#3>, %EFLAGS<imp-use,kill>
336B	BB#2: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#1
352B		JMP_1 <BB#8>
	    Successors according to CFG: BB#8
> JMP_1 <BB#8>
368B	BB#3: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#1
384B		%vreg16<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg16
400B		%vreg15<def> = MOV32rm %vreg16<kill>, 1, %noreg, 120, %noreg; mem:LD4[%state_out_pos] GR32:%vreg15 GR64:%vreg16
416B		%vreg13<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg13
432B		CMP32rm %vreg15<kill>, %vreg13<kill>, 1, %noreg, 116, %noreg, %EFLAGS<imp-def>; mem:LD4[%numZ] GR32:%vreg15 GR64:%vreg13
448B		JL_1 <BB#5>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#5 BB#4
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 120, %noreg; mem:LD4[%state_out_pos]
> %RCX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> CMP32rm %EAX<kill>, %RCX<kill>, 1, %noreg, 116, %noreg, %EFLAGS<imp-def>; mem:LD4[%numZ]
> JL_1 <BB#5>, %EFLAGS<imp-use,kill>
464B	BB#4: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#3
480B		JMP_1 <BB#8>
	    Successors according to CFG: BB#8
> JMP_1 <BB#8>
496B	BB#5: derived from LLVM BB %if.end.3
	    Predecessors according to CFG: BB#3
512B		MOV8mi <fi#1>, 1, %noreg, 0, %noreg, 1; mem:ST1[%progress_out]
528B		%vreg68<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg68
544B		%vreg66<def> = MOVSX64rm32 %vreg68<kill>, 1, %noreg, 120, %noreg; mem:LD4[%state_out_pos4] GR64_NOSP:%vreg66 GR64:%vreg68
560B		%vreg64<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg64
576B		%vreg63<def> = MOV64rm %vreg64<kill>, 1, %noreg, 80, %noreg; mem:LD8[%zbits] GR64:%vreg63,%vreg64
592B		%vreg61<def> = MOV8rm %vreg63<kill>, 1, %vreg66<kill>, 0, %noreg; mem:LD1[%arrayidx] GR8:%vreg61 GR64:%vreg63 GR64_NOSP:%vreg66
608B		%vreg58<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg58
624B		%vreg57<def> = MOV64rm %vreg58<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm5] GR64:%vreg57,%vreg58
640B		%vreg55<def> = MOV64rm %vreg57<kill>, 1, %noreg, 24, %noreg; mem:LD8[%next_out] GR64:%vreg55,%vreg57
656B		MOV8mr %vreg55<kill>, 1, %noreg, 0, %noreg, %vreg61<kill>; mem:ST1[%14] GR64:%vreg55 GR8:%vreg61
672B		%vreg51<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg51
688B		%vreg49<def> = MOV32rm %vreg51, 1, %noreg, 120, %noreg; mem:LD4[%state_out_pos6] GR32:%vreg49 GR64:%vreg51
720B		%vreg49<def,tied1> = ADD32ri8 %vreg49<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg49
736B		MOV32mr %vreg51<kill>, 1, %noreg, 120, %noreg, %vreg49<kill>; mem:ST4[%state_out_pos6] GR64:%vreg51 GR32:%vreg49
752B		%vreg45<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg45
768B		%vreg44<def> = MOV64rm %vreg45<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm7] GR64:%vreg44,%vreg45
784B		%vreg41<def> = MOV32rm %vreg44, 1, %noreg, 32, %noreg; mem:LD4[%avail_out8] GR32:%vreg41 GR64:%vreg44
816B		%vreg41<def,tied1> = ADD32ri8 %vreg41<kill,tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg41
832B		MOV32mr %vreg44<kill>, 1, %noreg, 32, %noreg, %vreg41<kill>; mem:ST4[%avail_out8] GR64:%vreg44 GR32:%vreg41
848B		%vreg37<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg37
864B		%vreg36<def> = MOV64rm %vreg37<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm9] GR64:%vreg36,%vreg37
880B		%vreg33<def> = MOV64rm %vreg36, 1, %noreg, 24, %noreg; mem:LD8[%next_out10] GR64:%vreg33,%vreg36
912B		%vreg33<def,tied1> = ADD64ri8 %vreg33<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR64:%vreg33
928B		MOV64mr %vreg36<kill>, 1, %noreg, 24, %noreg, %vreg33<kill>; mem:ST8[%next_out10] GR64:%vreg36,%vreg33
944B		%vreg29<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg29
960B		%vreg28<def> = MOV64rm %vreg29<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm11] GR64:%vreg28,%vreg29
976B		%vreg25<def> = MOV32rm %vreg28, 1, %noreg, 36, %noreg; mem:LD4[%total_out_lo32] GR32:%vreg25 GR64:%vreg28
1008B		%vreg25<def,tied1> = ADD32ri8 %vreg25<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg25
1024B		MOV32mr %vreg28<kill>, 1, %noreg, 36, %noreg, %vreg25<kill>; mem:ST4[%total_out_lo32] GR64:%vreg28 GR32:%vreg25
1040B		%vreg21<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg21
1056B		%vreg20<def> = MOV64rm %vreg21<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm13] GR64:%vreg20,%vreg21
1072B		CMP32mi8 %vreg20<kill>, 1, %noreg, 36, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%total_out_lo3214] GR64:%vreg20
1088B		JNE_1 <BB#7>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#7 BB#6
> MOV8mi <fi#1>, 1, %noreg, 0, %noreg, 1; mem:ST1[%progress_out]
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RAX<def> = MOVSX64rm32 %RAX<kill>, 1, %noreg, 120, %noreg; mem:LD4[%state_out_pos4]
> %RCX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RCX<def> = MOV64rm %RCX<kill>, 1, %noreg, 80, %noreg; mem:LD8[%zbits]
> %AL<def> = MOV8rm %RCX<kill>, 1, %RAX<kill>, 0, %noreg; mem:LD1[%arrayidx]
> %RCX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RCX<def> = MOV64rm %RCX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm5]
> %RCX<def> = MOV64rm %RCX<kill>, 1, %noreg, 24, %noreg; mem:LD8[%next_out]
> MOV8mr %RCX<kill>, 1, %noreg, 0, %noreg, %AL<kill>; mem:ST1[%14]
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 120, %noreg; mem:LD4[%state_out_pos6]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 120, %noreg, %ECX<kill>; mem:ST4[%state_out_pos6]
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm7]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 32, %noreg; mem:LD4[%avail_out8]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, -1, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 32, %noreg, %ECX<kill>; mem:ST4[%avail_out8]
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm9]
> %RCX<def> = MOV64rm %RAX, 1, %noreg, 24, %noreg; mem:LD8[%next_out10]
> %RCX<def,tied1> = ADD64ri8 %RCX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV64mr %RAX<kill>, 1, %noreg, 24, %noreg, %RCX<kill>; mem:ST8[%next_out10]
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm11]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 36, %noreg; mem:LD4[%total_out_lo32]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 36, %noreg, %ECX<kill>; mem:ST4[%total_out_lo32]
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm13]
> CMP32mi8 %RAX<kill>, 1, %noreg, 36, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%total_out_lo3214]
> JNE_1 <BB#7>, %EFLAGS<imp-use,kill>
1104B	BB#6: derived from LLVM BB %if.then.16
	    Predecessors according to CFG: BB#5
1120B		%vreg76<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg76
1136B		%vreg75<def> = MOV64rm %vreg76<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm17] GR64:%vreg75,%vreg76
1152B		%vreg72<def> = MOV32rm %vreg75, 1, %noreg, 40, %noreg; mem:LD4[%total_out_hi32] GR32:%vreg72 GR64:%vreg75
1184B		%vreg72<def,tied1> = ADD32ri8 %vreg72<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg72
1200B		MOV32mr %vreg75<kill>, 1, %noreg, 40, %noreg, %vreg72<kill>; mem:ST4[%total_out_hi32] GR64:%vreg75 GR32:%vreg72
	    Successors according to CFG: BB#7
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm17]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 40, %noreg; mem:LD4[%total_out_hi32]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 40, %noreg, %ECX<kill>; mem:ST4[%total_out_hi32]
1216B	BB#7: derived from LLVM BB %if.end.19
	    Predecessors according to CFG: BB#5 BB#6
1232B		JMP_1 <BB#1>
	    Successors according to CFG: BB#1
> JMP_1 <BB#1>
1248B	BB#8: derived from LLVM BB %while.end
	    Predecessors according to CFG: BB#4 BB#2
1264B		%vreg79<def> = MOV64ri <ga:@copy_output_until_stop>; GR64:%vreg79
1296B		%vreg81<def> = MOV8rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD1[%progress_out] GR8:%vreg81
1312B		%vreg80<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg80
1328B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1344B		%RDI<def> = COPY %vreg79<kill>; GR64:%vreg79
1360B		%RSI<def> = COPY %vreg80<kill>; GR64:%vreg80
1376B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
1392B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1408B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1424B		STACKMAP 1, 0, %vreg81, ...; GR8:%vreg81
1440B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1456B		%AL<def> = COPY %vreg81<kill>; GR8:%vreg81
1472B		RETQ %AL<imp-use>
> %RDI<def> = MOV64ri <ga:@copy_output_until_stop>
> %BL<def> = MOV8rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD1[%progress_out]
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 1, 0, %BL, ...
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %AL<def> = COPY %BL<kill>
> RETQ %AL<imp-use>
Computing live-in reg-units in ABI blocks.
0B	BB#0 DIL#0
Created 1 new intervals.
********** INTERVALS **********
DIL [0B,16r:0)[112r,144r:4)[1744r,1760r:2)[4160r,4176r:3)[5216r,5248r:1)  0@0B-phi 1@5216r 2@1744r 3@4160r 4@112r
%vreg0 [16r,32r:0)  0@16r
%vreg1 [32r,224r:0)  0@32r
%vreg4 [256r,272r:0)  0@256r
%vreg5 [48r,64r:0)  0@48r
%vreg6 [64r,112r:0)  0@64r
%vreg7 [80r,128r:0)  0@80r
%vreg11 [2704r,2720r:0)  0@2704r
%vreg13 [2688r,2720r:0)  0@2688r
%vreg14 [2672r,2688r:0)  0@2672r
%vreg18 [2816r,2832r:0)  0@2816r
%vreg19 [2800r,2816r:0)  0@2800r
%vreg22 [2912r,2928r:0)  0@2912r
%vreg26 [3120r,3136r:0)  0@3120r
%vreg27 [3104r,3136r:0)  0@3104r
%vreg30 [3072r,3088r:0)  0@3072r
%vreg33 [3056r,3072r:0)  0@3056r
%vreg35 [3040r,3056r:0)  0@3040r
%vreg36 [3024r,3040r:0)  0@3024r
%vreg39 [3184r,3200r:0)  0@3184r
%vreg43 [3936r,3952r:0)  0@3936r
%vreg44 [3920r,3952r:0)  0@3920r
%vreg47 [4000r,4016r:0)  0@4000r
%vreg51 [4416r,4432r:0)[4432r,4448r:1)  0@4416r 1@4432r
%vreg52 [4400r,4416r:0)  0@4400r
%vreg53 [4384r,4448r:0)  0@4384r
%vreg56 [4064r,4080r:0)  0@4064r
%vreg58 [4128r,4160r:0)  0@4128r
%vreg60 [4320r,4336r:0)  0@4320r
%vreg63 [4288r,4304r:0)  0@4288r
%vreg64 [4272r,4304r:0)  0@4272r
%vreg67 [3856r,3872r:0)  0@3856r
%vreg68 [3840r,3872r:0)  0@3840r
%vreg72 [3792r,3808r:0)[3808r,3824r:1)  0@3792r 1@3808r
%vreg73 [3776r,3792r:0)  0@3776r
%vreg74 [3760r,3824r:0)  0@3760r
%vreg79 [3728r,3744r:0)  0@3728r
%vreg80 [3712r,3728r:0)  0@3712r
%vreg82 [3696r,3744r:0)  0@3696r
%vreg84 [3680r,3696r:0)  0@3680r
%vreg85 [3664r,3744r:0)  0@3664r
%vreg88 [3632r,3648r:0)  0@3632r
%vreg90 [3600r,3616r:0)  0@3600r
%vreg91 [3616r,3648r:0)  0@3616r
%vreg93 [3584r,3600r:0)  0@3584r
%vreg96 [3552r,3568r:0)  0@3552r
%vreg99 [3520r,3536r:0)[3536r,3568r:1)  0@3520r 1@3536r
%vreg102 [3488r,3504r:0)  0@3488r
%vreg103 [3504r,3536r:0)  0@3504r
%vreg106 [3456r,3472r:0)[3472r,3488r:1)  0@3456r 1@3472r
%vreg108 [3440r,3472r:0)  0@3440r
%vreg110 [3408r,3424r:0)[3424r,3456r:1)  0@3408r 1@3424r
%vreg112 [3392r,3408r:0)  0@3392r
%vreg113 [3376r,3392r:0)  0@3376r
%vreg115 [3344r,3360r:0)[3360r,3520r:1)  0@3344r 1@3360r
%vreg117 [3328r,3344r:0)  0@3328r
%vreg118 [3312r,3328r:0)  0@3312r
%vreg121 [3280r,3296r:0)  0@3280r
%vreg123 [3264r,3280r:0)  0@3264r
%vreg124 [3248r,3264r:0)  0@3248r
%vreg128 [4816r,4832r:0)  0@4816r
%vreg129 [4800r,4816r:0)  0@4800r
%vreg133 [4752r,4768r:0)[4768r,4784r:1)  0@4752r 1@4768r
%vreg134 [4736r,4752r:0)  0@4736r
%vreg136 [4720r,4784r:0)  0@4720r
%vreg137 [4704r,4720r:0)  0@4704r
%vreg141 [4656r,4672r:0)[4672r,4688r:1)  0@4656r 1@4672r
%vreg142 [4640r,4656r:0)  0@4640r
%vreg144 [4624r,4688r:0)  0@4624r
%vreg145 [4608r,4624r:0)  0@4608r
%vreg149 [4560r,4576r:0)[4576r,4592r:1)  0@4560r 1@4576r
%vreg150 [4544r,4560r:0)  0@4544r
%vreg152 [4528r,4592r:0)  0@4528r
%vreg153 [4512r,4528r:0)  0@4512r
%vreg157 [4928r,4944r:0)[4944r,4960r:1)  0@4928r 1@4944r
%vreg158 [4912r,4928r:0)  0@4912r
%vreg160 [4896r,4960r:0)  0@4896r
%vreg161 [4880r,4896r:0)  0@4880r
%vreg165 [5024r,5040r:0)[5040r,5056r:1)  0@5024r 1@5040r
%vreg166 [5008r,5024r:0)  0@5008r
%vreg167 [4992r,5056r:0)  0@4992r
%vreg171 [384r,400r:0)  0@384r
%vreg173 [368r,400r:0)  0@368r
%vreg174 [352r,368r:0)  0@352r
%vreg178 [496r,512r:0)  0@496r
%vreg179 [480r,496r:0)  0@480r
%vreg183 [704r,720r:0)  0@704r
%vreg184 [688r,720r:0)  0@688r
%vreg187 [656r,672r:0)  0@656r
%vreg190 [640r,656r:0)  0@640r
%vreg192 [624r,640r:0)  0@624r
%vreg193 [608r,624r:0)  0@608r
%vreg196 [768r,784r:0)  0@768r
%vreg200 [1520r,1536r:0)  0@1520r
%vreg201 [1504r,1536r:0)  0@1504r
%vreg204 [1584r,1600r:0)  0@1584r
%vreg208 [2000r,2016r:0)[2016r,2032r:1)  0@2000r 1@2016r
%vreg209 [1984r,2000r:0)  0@1984r
%vreg210 [1968r,2032r:0)  0@1968r
%vreg213 [1648r,1664r:0)  0@1648r
%vreg215 [1712r,1744r:0)  0@1712r
%vreg217 [1904r,1920r:0)  0@1904r
%vreg220 [1872r,1888r:0)  0@1872r
%vreg221 [1856r,1888r:0)  0@1856r
%vreg224 [1440r,1456r:0)  0@1440r
%vreg225 [1424r,1456r:0)  0@1424r
%vreg229 [1376r,1392r:0)[1392r,1408r:1)  0@1376r 1@1392r
%vreg230 [1360r,1376r:0)  0@1360r
%vreg231 [1344r,1408r:0)  0@1344r
%vreg236 [1312r,1328r:0)  0@1312r
%vreg237 [1296r,1312r:0)  0@1296r
%vreg239 [1280r,1328r:0)  0@1280r
%vreg241 [1264r,1280r:0)  0@1264r
%vreg242 [1248r,1328r:0)  0@1248r
%vreg245 [1216r,1232r:0)  0@1216r
%vreg247 [1184r,1200r:0)  0@1184r
%vreg248 [1200r,1232r:0)  0@1200r
%vreg250 [1168r,1184r:0)  0@1168r
%vreg253 [1136r,1152r:0)  0@1136r
%vreg256 [1104r,1120r:0)[1120r,1152r:1)  0@1104r 1@1120r
%vreg259 [1072r,1088r:0)  0@1072r
%vreg260 [1088r,1120r:0)  0@1088r
%vreg263 [1040r,1056r:0)[1056r,1072r:1)  0@1040r 1@1056r
%vreg265 [1024r,1056r:0)  0@1024r
%vreg267 [992r,1008r:0)[1008r,1040r:1)  0@992r 1@1008r
%vreg269 [976r,992r:0)  0@976r
%vreg270 [960r,976r:0)  0@960r
%vreg272 [928r,944r:0)[944r,1104r:1)  0@928r 1@944r
%vreg274 [912r,928r:0)  0@912r
%vreg275 [896r,912r:0)  0@896r
%vreg278 [864r,880r:0)  0@864r
%vreg280 [848r,864r:0)  0@848r
%vreg281 [832r,848r:0)  0@832r
%vreg285 [2400r,2416r:0)  0@2400r
%vreg286 [2384r,2400r:0)  0@2384r
%vreg290 [2336r,2352r:0)[2352r,2368r:1)  0@2336r 1@2352r
%vreg291 [2320r,2336r:0)  0@2320r
%vreg293 [2304r,2368r:0)  0@2304r
%vreg294 [2288r,2304r:0)  0@2288r
%vreg298 [2240r,2256r:0)[2256r,2272r:1)  0@2240r 1@2256r
%vreg299 [2224r,2240r:0)  0@2224r
%vreg301 [2208r,2272r:0)  0@2208r
%vreg302 [2192r,2208r:0)  0@2192r
%vreg306 [2144r,2160r:0)[2160r,2176r:1)  0@2144r 1@2160r
%vreg307 [2128r,2144r:0)  0@2128r
%vreg309 [2112r,2176r:0)  0@2112r
%vreg310 [2096r,2112r:0)  0@2096r
%vreg314 [2512r,2528r:0)[2528r,2544r:1)  0@2512r 1@2528r
%vreg315 [2496r,2512r:0)  0@2496r
%vreg317 [2480r,2544r:0)  0@2480r
%vreg318 [2464r,2480r:0)  0@2464r
%vreg320 [5136r,5152r:0)  0@5136r
%vreg321 [5152r,5216r:0)  0@5152r
%vreg322 [5184r,5232r:0)  0@5184r
%vreg323 [5168r,5328r:0)  0@5168r
RegMasks: 144r 1760r 4176r 5248r
********** MACHINEINSTRS **********
# Machine code for function copy_input_until_stop: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=8, align=8, at location [SP+8]
  fi#1: size=1, align=1, at location [SP+8]
  fi#2: size=4, align=4, at location [SP+8]
  fi#3: size=1, align=1, at location [SP+8]
  fi#4: size=4, align=4, at location [SP+8]
  fi#5: size=1, align=1, at location [SP+8]
Function Live Ins: %RDI in %vreg0

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI
16B		%vreg0<def> = COPY %RDI; GR64:%vreg0
32B		%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
48B		%vreg5<def> = MOV64ri <ga:@copy_input_until_stop>; GR64:%vreg5
64B		%vreg6<def> = COPY %vreg5; GR64:%vreg6,%vreg5
80B		%vreg7<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg7
96B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
112B		%RDI<def> = COPY %vreg6; GR64:%vreg6
128B		%RSI<def> = COPY %vreg7; GR64:%vreg7
144B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
160B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
192B		STACKMAP 0, 0, 0, <fi#3>, 0, 0, <fi#5>, 0, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack3](align=1) LD8[FixedStack5](align=1) LD8[FixedStack1](align=1) LD8[FixedStack0] LD8[FixedStack2](align=4) LD8[FixedStack4](align=4) GR64:%vreg1
208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%s.addr] GR64:%vreg1
240B		MOV8mi <fi#1>, 1, %noreg, 0, %noreg, 0; mem:ST1[%progress_in]
256B		%vreg4<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg4
272B		CMP32mi8 %vreg4, 1, %noreg, 8, %noreg, 2, %EFLAGS<imp-def>; mem:LD4[%mode] GR64:%vreg4
288B		JNE_1 <BB#20>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#20 BB#1

304B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
320B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2

336B	BB#2: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#1 BB#18
352B		%vreg174<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg174
368B		%vreg173<def> = MOV32rm %vreg174, 1, %noreg, 108, %noreg; mem:LD4[%nblock] GR32:%vreg173 GR64:%vreg174
384B		%vreg171<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg171
400B		CMP32rm %vreg173, %vreg171, 1, %noreg, 112, %noreg, %EFLAGS<imp-def>; mem:LD4[%nblockMAX] GR32:%vreg173 GR64:%vreg171
416B		JL_1 <BB#4>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#4 BB#3

432B	BB#3: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#2
448B		JMP_1 <BB#19>
	    Successors according to CFG: BB#19

464B	BB#4: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#2
480B		%vreg179<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg179
496B		%vreg178<def> = MOV64rm %vreg179, 1, %noreg, 0, %noreg; mem:LD8[%strm] GR64:%vreg178,%vreg179
512B		CMP32mi8 %vreg178, 1, %noreg, 8, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_in] GR64:%vreg178
528B		JNE_1 <BB#6>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#6 BB#5

544B	BB#5: derived from LLVM BB %if.then.4
	    Predecessors according to CFG: BB#4
560B		JMP_1 <BB#19>
	    Successors according to CFG: BB#19

576B	BB#6: derived from LLVM BB %if.end.5
	    Predecessors according to CFG: BB#4
592B		MOV8mi <fi#1>, 1, %noreg, 0, %noreg, 1; mem:ST1[%progress_in]
608B		%vreg193<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg193
624B		%vreg192<def> = MOV64rm %vreg193, 1, %noreg, 0, %noreg; mem:LD8[%strm6] GR64:%vreg192,%vreg193
640B		%vreg190<def> = MOV64rm %vreg192, 1, %noreg, 0, %noreg; mem:LD8[%next_in] GR64:%vreg190,%vreg192
656B		%vreg187<def> = MOVZX32rm8 %vreg190, 1, %noreg, 0, %noreg; mem:LD1[%11] GR32:%vreg187 GR64:%vreg190
672B		MOV32mr <fi#2>, 1, %noreg, 0, %noreg, %vreg187; mem:ST4[%zchh] GR32:%vreg187
688B		%vreg184<def> = MOV32rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD4[%zchh] GR32:%vreg184
704B		%vreg183<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg183
720B		CMP32rm %vreg184, %vreg183, 1, %noreg, 92, %noreg, %EFLAGS<imp-def>; mem:LD4[%state_in_ch] GR32:%vreg184 GR64:%vreg183
736B		JE_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#7

752B	BB#7: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#6
768B		%vreg196<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg196
784B		CMP32mi8 %vreg196, 1, %noreg, 96, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%state_in_len] GR64:%vreg196
800B		JNE_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#8

816B	BB#8: derived from LLVM BB %if.then.11
	    Predecessors according to CFG: BB#7
832B		%vreg281<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg281
848B		%vreg280<def> = MOV32rm %vreg281, 1, %noreg, 92, %noreg; mem:LD4[%state_in_ch12] GR32:%vreg280 GR64:%vreg281
864B		%vreg278<def> = COPY %vreg280:sub_8bit; GR8:%vreg278 GR32:%vreg280
880B		MOV8mr <fi#3>, 1, %noreg, 0, %noreg, %vreg278; mem:ST1[%ch] GR8:%vreg278
896B		%vreg275<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg275
912B		%vreg274<def> = MOV32rm %vreg275, 1, %noreg, 648, %noreg; mem:LD4[%blockCRC] GR32:%vreg274 GR64:%vreg275
928B		%vreg272<def> = COPY %vreg274; GR32:%vreg272,%vreg274
944B		%vreg272<def,tied1> = SHL32ri %vreg272<tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg272
960B		%vreg270<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg270
976B		%vreg269<def> = MOV32rm %vreg270, 1, %noreg, 648, %noreg; mem:LD4[%blockCRC14] GR32:%vreg269 GR64:%vreg270
992B		%vreg267<def> = COPY %vreg269; GR32:%vreg267,%vreg269
1008B		%vreg267<def,tied1> = SHR32ri %vreg267<tied0>, 24, %EFLAGS<imp-def,dead>; GR32:%vreg267
1024B		%vreg265<def> = MOVZX32rm8 <fi#3>, 1, %noreg, 0, %noreg; mem:LD1[%ch] GR32:%vreg265
1040B		%vreg263<def> = COPY %vreg267; GR32:%vreg263,%vreg267
1056B		%vreg263<def,tied1> = XOR32rr %vreg263<tied0>, %vreg265, %EFLAGS<imp-def,dead>; GR32:%vreg263,%vreg265
1072B		%vreg259<def> = MOV32rr %vreg263; GR32:%vreg259,%vreg263
1088B		%vreg260<def> = SUBREG_TO_REG 0, %vreg259, 4; GR64_NOSP:%vreg260 GR32:%vreg259
1104B		%vreg256<def> = COPY %vreg272; GR32:%vreg256,%vreg272
1120B		%vreg256<def,tied1> = XOR32rm %vreg256<tied0>, %noreg, 4, %vreg260, <ga:@BZ2_crc32Table>, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%arrayidx] GR32:%vreg256 GR64_NOSP:%vreg260
1136B		%vreg253<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg253
1152B		MOV32mr %vreg253, 1, %noreg, 648, %noreg, %vreg256; mem:ST4[%blockCRC17] GR64:%vreg253 GR32:%vreg256
1168B		%vreg250<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg250
1184B		%vreg247<def> = MOV32rm %vreg250, 1, %noreg, 92, %noreg; mem:LD4[%state_in_ch18] GR32:%vreg247 GR64:%vreg250
1200B		%vreg248<def> = SUBREG_TO_REG 0, %vreg247, 4; GR64_NOSP:%vreg248 GR32:%vreg247
1216B		%vreg245<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg245
1232B		MOV8mi %vreg245, 1, %vreg248, 128, %noreg, 1; mem:ST1[%arrayidx20] GR64:%vreg245 GR64_NOSP:%vreg248
1248B		%vreg242<def> = MOV8rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD1[%ch] GR8:%vreg242
1264B		%vreg241<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg241
1280B		%vreg239<def> = MOVSX64rm32 %vreg241, 1, %noreg, 108, %noreg; mem:LD4[%nblock21] GR64_NOSP:%vreg239 GR64:%vreg241
1296B		%vreg237<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg237
1312B		%vreg236<def> = MOV64rm %vreg237, 1, %noreg, 64, %noreg; mem:LD8[%block] GR64:%vreg236,%vreg237
1328B		MOV8mr %vreg236, 1, %vreg239, 0, %noreg, %vreg242; mem:ST1[%arrayidx23] GR64:%vreg236 GR64_NOSP:%vreg239 GR8:%vreg242
1344B		%vreg231<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg231
1360B		%vreg230<def> = MOV32rm %vreg231, 1, %noreg, 108, %noreg; mem:LD4[%nblock24] GR32:%vreg230 GR64:%vreg231
1376B		%vreg229<def> = COPY %vreg230; GR32:%vreg229,%vreg230
1392B		%vreg229<def,tied1> = ADD32ri8 %vreg229<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg229
1408B		MOV32mr %vreg231, 1, %noreg, 108, %noreg, %vreg229; mem:ST4[%nblock24] GR64:%vreg231 GR32:%vreg229
1424B		%vreg225<def> = MOV32rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD4[%zchh] GR32:%vreg225
1440B		%vreg224<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg224
1456B		MOV32mr %vreg224, 1, %noreg, 92, %noreg, %vreg225; mem:ST4[%state_in_ch25] GR64:%vreg224 GR32:%vreg225
1472B		JMP_1 <BB#16>
	    Successors according to CFG: BB#16

1488B	BB#9: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#6 BB#7
1504B		%vreg201<def> = MOV32rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD4[%zchh] GR32:%vreg201
1520B		%vreg200<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg200
1536B		CMP32rm %vreg201, %vreg200, 1, %noreg, 92, %noreg, %EFLAGS<imp-def>; mem:LD4[%state_in_ch26] GR32:%vreg201 GR64:%vreg200
1552B		JNE_1 <BB#11>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#11 BB#10

1568B	BB#10: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#9
1584B		%vreg204<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg204
1600B		CMP32mi %vreg204, 1, %noreg, 96, %noreg, 255, %EFLAGS<imp-def>; mem:LD4[%state_in_len29] GR64:%vreg204
1616B		JNE_1 <BB#14>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#14 BB#11

1632B	BB#11: derived from LLVM BB %if.then.32
	    Predecessors according to CFG: BB#9 BB#10
1648B		%vreg213<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg213
1664B		CMP32mi %vreg213, 1, %noreg, 92, %noreg, 256, %EFLAGS<imp-def>; mem:LD4[%state_in_ch33] GR64:%vreg213
1680B		JAE_1 <BB#13>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#13 BB#12

1696B	BB#12: derived from LLVM BB %if.then.36
	    Predecessors according to CFG: BB#11
1712B		%vreg215<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg215
1728B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1744B		%RDI<def> = COPY %vreg215; GR64:%vreg215
1760B		CALL64pcrel32 <ga:@add_pair_to_block>, <regmask>, %RSP<imp-use>, %RDI<imp-use>
1776B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1792B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1808B		STACKMAP 1, 0, 0, <fi#3>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, ...; mem:LD8[FixedStack3](align=1) LD8[FixedStack1](align=1) LD8[FixedStack0] LD8[FixedStack2](align=4)
1824B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#13

1840B	BB#13: derived from LLVM BB %if.end.37
	    Predecessors according to CFG: BB#11 BB#12
1856B		%vreg221<def> = MOV32rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD4[%zchh] GR32:%vreg221
1872B		%vreg220<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg220
1888B		MOV32mr %vreg220, 1, %noreg, 92, %noreg, %vreg221; mem:ST4[%state_in_ch38] GR64:%vreg220 GR32:%vreg221
1904B		%vreg217<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg217
1920B		MOV32mi %vreg217, 1, %noreg, 96, %noreg, 1; mem:ST4[%state_in_len39] GR64:%vreg217
1936B		JMP_1 <BB#15>
	    Successors according to CFG: BB#15

1952B	BB#14: derived from LLVM BB %if.else.40
	    Predecessors according to CFG: BB#10
1968B		%vreg210<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg210
1984B		%vreg209<def> = MOV32rm %vreg210, 1, %noreg, 96, %noreg; mem:LD4[%state_in_len41] GR32:%vreg209 GR64:%vreg210
2000B		%vreg208<def> = COPY %vreg209; GR32:%vreg208,%vreg209
2016B		%vreg208<def,tied1> = ADD32ri8 %vreg208<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg208
2032B		MOV32mr %vreg210, 1, %noreg, 96, %noreg, %vreg208; mem:ST4[%state_in_len41] GR64:%vreg210 GR32:%vreg208
	    Successors according to CFG: BB#15

2048B	BB#15: derived from LLVM BB %if.end.43
	    Predecessors according to CFG: BB#14 BB#13
2064B		JMP_1 <BB#16>
	    Successors according to CFG: BB#16

2080B	BB#16: derived from LLVM BB %if.end.44
	    Predecessors according to CFG: BB#15 BB#8
2096B		%vreg310<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg310
2112B		%vreg309<def> = MOV64rm %vreg310, 1, %noreg, 0, %noreg; mem:LD8[%strm45] GR64:%vreg309,%vreg310
2128B		%vreg307<def> = MOV64rm %vreg309, 1, %noreg, 0, %noreg; mem:LD8[%next_in46] GR64:%vreg307,%vreg309
2144B		%vreg306<def> = COPY %vreg307; GR64:%vreg306,%vreg307
2160B		%vreg306<def,tied1> = ADD64ri8 %vreg306<tied0>, 1, %EFLAGS<imp-def,dead>; GR64:%vreg306
2176B		MOV64mr %vreg309, 1, %noreg, 0, %noreg, %vreg306; mem:ST8[%next_in46] GR64:%vreg309,%vreg306
2192B		%vreg302<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg302
2208B		%vreg301<def> = MOV64rm %vreg302, 1, %noreg, 0, %noreg; mem:LD8[%strm47] GR64:%vreg301,%vreg302
2224B		%vreg299<def> = MOV32rm %vreg301, 1, %noreg, 8, %noreg; mem:LD4[%avail_in48] GR32:%vreg299 GR64:%vreg301
2240B		%vreg298<def> = COPY %vreg299; GR32:%vreg298,%vreg299
2256B		%vreg298<def,tied1> = ADD32ri8 %vreg298<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg298
2272B		MOV32mr %vreg301, 1, %noreg, 8, %noreg, %vreg298; mem:ST4[%avail_in48] GR64:%vreg301 GR32:%vreg298
2288B		%vreg294<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg294
2304B		%vreg293<def> = MOV64rm %vreg294, 1, %noreg, 0, %noreg; mem:LD8[%strm49] GR64:%vreg293,%vreg294
2320B		%vreg291<def> = MOV32rm %vreg293, 1, %noreg, 12, %noreg; mem:LD4[%total_in_lo32] GR32:%vreg291 GR64:%vreg293
2336B		%vreg290<def> = COPY %vreg291; GR32:%vreg290,%vreg291
2352B		%vreg290<def,tied1> = ADD32ri8 %vreg290<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg290
2368B		MOV32mr %vreg293, 1, %noreg, 12, %noreg, %vreg290; mem:ST4[%total_in_lo32] GR64:%vreg293 GR32:%vreg290
2384B		%vreg286<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg286
2400B		%vreg285<def> = MOV64rm %vreg286, 1, %noreg, 0, %noreg; mem:LD8[%strm51] GR64:%vreg285,%vreg286
2416B		CMP32mi8 %vreg285, 1, %noreg, 12, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%total_in_lo3252] GR64:%vreg285
2432B		JNE_1 <BB#18>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#18 BB#17

2448B	BB#17: derived from LLVM BB %if.then.55
	    Predecessors according to CFG: BB#16
2464B		%vreg318<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg318
2480B		%vreg317<def> = MOV64rm %vreg318, 1, %noreg, 0, %noreg; mem:LD8[%strm56] GR64:%vreg317,%vreg318
2496B		%vreg315<def> = MOV32rm %vreg317, 1, %noreg, 16, %noreg; mem:LD4[%total_in_hi32] GR32:%vreg315 GR64:%vreg317
2512B		%vreg314<def> = COPY %vreg315; GR32:%vreg314,%vreg315
2528B		%vreg314<def,tied1> = ADD32ri8 %vreg314<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg314
2544B		MOV32mr %vreg317, 1, %noreg, 16, %noreg, %vreg314; mem:ST4[%total_in_hi32] GR64:%vreg317 GR32:%vreg314
	    Successors according to CFG: BB#18

2560B	BB#18: derived from LLVM BB %if.end.58
	    Predecessors according to CFG: BB#16 BB#17
2576B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2

2592B	BB#19: derived from LLVM BB %while.end
	    Predecessors according to CFG: BB#5 BB#3
2608B		JMP_1 <BB#41>
	    Successors according to CFG: BB#41

2624B	BB#20: derived from LLVM BB %if.else.59
	    Predecessors according to CFG: BB#0
2640B		JMP_1 <BB#21>
	    Successors according to CFG: BB#21

2656B	BB#21: derived from LLVM BB %while.body.60
	    Predecessors according to CFG: BB#20 BB#39
2672B		%vreg14<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg14
2688B		%vreg13<def> = MOV32rm %vreg14, 1, %noreg, 108, %noreg; mem:LD4[%nblock61] GR32:%vreg13 GR64:%vreg14
2704B		%vreg11<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg11
2720B		CMP32rm %vreg13, %vreg11, 1, %noreg, 112, %noreg, %EFLAGS<imp-def>; mem:LD4[%nblockMAX62] GR32:%vreg13 GR64:%vreg11
2736B		JL_1 <BB#23>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#23 BB#22

2752B	BB#22: derived from LLVM BB %if.then.65
	    Predecessors according to CFG: BB#21
2768B		JMP_1 <BB#40>
	    Successors according to CFG: BB#40

2784B	BB#23: derived from LLVM BB %if.end.66
	    Predecessors according to CFG: BB#21
2800B		%vreg19<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg19
2816B		%vreg18<def> = MOV64rm %vreg19, 1, %noreg, 0, %noreg; mem:LD8[%strm67] GR64:%vreg18,%vreg19
2832B		CMP32mi8 %vreg18, 1, %noreg, 8, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_in68] GR64:%vreg18
2848B		JNE_1 <BB#25>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#25 BB#24

2864B	BB#24: derived from LLVM BB %if.then.71
	    Predecessors according to CFG: BB#23
2880B		JMP_1 <BB#40>
	    Successors according to CFG: BB#40

2896B	BB#25: derived from LLVM BB %if.end.72
	    Predecessors according to CFG: BB#23
2912B		%vreg22<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg22
2928B		CMP32mi8 %vreg22, 1, %noreg, 16, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_in_expect] GR64:%vreg22
2944B		JNE_1 <BB#27>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#27 BB#26

2960B	BB#26: derived from LLVM BB %if.then.75
	    Predecessors according to CFG: BB#25
2976B		JMP_1 <BB#40>
	    Successors according to CFG: BB#40

2992B	BB#27: derived from LLVM BB %if.end.76
	    Predecessors according to CFG: BB#25
3008B		MOV8mi <fi#1>, 1, %noreg, 0, %noreg, 1; mem:ST1[%progress_in]
3024B		%vreg36<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg36
3040B		%vreg35<def> = MOV64rm %vreg36, 1, %noreg, 0, %noreg; mem:LD8[%strm78] GR64:%vreg35,%vreg36
3056B		%vreg33<def> = MOV64rm %vreg35, 1, %noreg, 0, %noreg; mem:LD8[%next_in79] GR64:%vreg33,%vreg35
3072B		%vreg30<def> = MOVZX32rm8 %vreg33, 1, %noreg, 0, %noreg; mem:LD1[%78] GR32:%vreg30 GR64:%vreg33
3088B		MOV32mr <fi#4>, 1, %noreg, 0, %noreg, %vreg30; mem:ST4[%zchh77] GR32:%vreg30
3104B		%vreg27<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%zchh77] GR32:%vreg27
3120B		%vreg26<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg26
3136B		CMP32rm %vreg27, %vreg26, 1, %noreg, 92, %noreg, %EFLAGS<imp-def>; mem:LD4[%state_in_ch81] GR32:%vreg27 GR64:%vreg26
3152B		JE_1 <BB#30>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#30 BB#28

3168B	BB#28: derived from LLVM BB %land.lhs.true.84
	    Predecessors according to CFG: BB#27
3184B		%vreg39<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg39
3200B		CMP32mi8 %vreg39, 1, %noreg, 96, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%state_in_len85] GR64:%vreg39
3216B		JNE_1 <BB#30>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#30 BB#29

3232B	BB#29: derived from LLVM BB %if.then.88
	    Predecessors according to CFG: BB#28
3248B		%vreg124<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg124
3264B		%vreg123<def> = MOV32rm %vreg124, 1, %noreg, 92, %noreg; mem:LD4[%state_in_ch90] GR32:%vreg123 GR64:%vreg124
3280B		%vreg121<def> = COPY %vreg123:sub_8bit; GR8:%vreg121 GR32:%vreg123
3296B		MOV8mr <fi#5>, 1, %noreg, 0, %noreg, %vreg121; mem:ST1[%ch89] GR8:%vreg121
3312B		%vreg118<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg118
3328B		%vreg117<def> = MOV32rm %vreg118, 1, %noreg, 648, %noreg; mem:LD4[%blockCRC92] GR32:%vreg117 GR64:%vreg118
3344B		%vreg115<def> = COPY %vreg117; GR32:%vreg115,%vreg117
3360B		%vreg115<def,tied1> = SHL32ri %vreg115<tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg115
3376B		%vreg113<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg113
3392B		%vreg112<def> = MOV32rm %vreg113, 1, %noreg, 648, %noreg; mem:LD4[%blockCRC94] GR32:%vreg112 GR64:%vreg113
3408B		%vreg110<def> = COPY %vreg112; GR32:%vreg110,%vreg112
3424B		%vreg110<def,tied1> = SHR32ri %vreg110<tied0>, 24, %EFLAGS<imp-def,dead>; GR32:%vreg110
3440B		%vreg108<def> = MOVZX32rm8 <fi#5>, 1, %noreg, 0, %noreg; mem:LD1[%ch89] GR32:%vreg108
3456B		%vreg106<def> = COPY %vreg110; GR32:%vreg106,%vreg110
3472B		%vreg106<def,tied1> = XOR32rr %vreg106<tied0>, %vreg108, %EFLAGS<imp-def,dead>; GR32:%vreg106,%vreg108
3488B		%vreg102<def> = MOV32rr %vreg106; GR32:%vreg102,%vreg106
3504B		%vreg103<def> = SUBREG_TO_REG 0, %vreg102, 4; GR64_NOSP:%vreg103 GR32:%vreg102
3520B		%vreg99<def> = COPY %vreg115; GR32:%vreg99,%vreg115
3536B		%vreg99<def,tied1> = XOR32rm %vreg99<tied0>, %noreg, 4, %vreg103, <ga:@BZ2_crc32Table>, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%arrayidx99] GR32:%vreg99 GR64_NOSP:%vreg103
3552B		%vreg96<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg96
3568B		MOV32mr %vreg96, 1, %noreg, 648, %noreg, %vreg99; mem:ST4[%blockCRC101] GR64:%vreg96 GR32:%vreg99
3584B		%vreg93<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg93
3600B		%vreg90<def> = MOV32rm %vreg93, 1, %noreg, 92, %noreg; mem:LD4[%state_in_ch102] GR32:%vreg90 GR64:%vreg93
3616B		%vreg91<def> = SUBREG_TO_REG 0, %vreg90, 4; GR64_NOSP:%vreg91 GR32:%vreg90
3632B		%vreg88<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg88
3648B		MOV8mi %vreg88, 1, %vreg91, 128, %noreg, 1; mem:ST1[%arrayidx105] GR64:%vreg88 GR64_NOSP:%vreg91
3664B		%vreg85<def> = MOV8rm <fi#5>, 1, %noreg, 0, %noreg; mem:LD1[%ch89] GR8:%vreg85
3680B		%vreg84<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg84
3696B		%vreg82<def> = MOVSX64rm32 %vreg84, 1, %noreg, 108, %noreg; mem:LD4[%nblock106] GR64_NOSP:%vreg82 GR64:%vreg84
3712B		%vreg80<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg80
3728B		%vreg79<def> = MOV64rm %vreg80, 1, %noreg, 64, %noreg; mem:LD8[%block108] GR64:%vreg79,%vreg80
3744B		MOV8mr %vreg79, 1, %vreg82, 0, %noreg, %vreg85; mem:ST1[%arrayidx109] GR64:%vreg79 GR64_NOSP:%vreg82 GR8:%vreg85
3760B		%vreg74<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg74
3776B		%vreg73<def> = MOV32rm %vreg74, 1, %noreg, 108, %noreg; mem:LD4[%nblock110] GR32:%vreg73 GR64:%vreg74
3792B		%vreg72<def> = COPY %vreg73; GR32:%vreg72,%vreg73
3808B		%vreg72<def,tied1> = ADD32ri8 %vreg72<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg72
3824B		MOV32mr %vreg74, 1, %noreg, 108, %noreg, %vreg72; mem:ST4[%nblock110] GR64:%vreg74 GR32:%vreg72
3840B		%vreg68<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%zchh77] GR32:%vreg68
3856B		%vreg67<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg67
3872B		MOV32mr %vreg67, 1, %noreg, 92, %noreg, %vreg68; mem:ST4[%state_in_ch112] GR64:%vreg67 GR32:%vreg68
3888B		JMP_1 <BB#37>
	    Successors according to CFG: BB#37

3904B	BB#30: derived from LLVM BB %if.else.113
	    Predecessors according to CFG: BB#27 BB#28
3920B		%vreg44<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%zchh77] GR32:%vreg44
3936B		%vreg43<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg43
3952B		CMP32rm %vreg44, %vreg43, 1, %noreg, 92, %noreg, %EFLAGS<imp-def>; mem:LD4[%state_in_ch114] GR32:%vreg44 GR64:%vreg43
3968B		JNE_1 <BB#32>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#32 BB#31

3984B	BB#31: derived from LLVM BB %lor.lhs.false.117
	    Predecessors according to CFG: BB#30
4000B		%vreg47<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg47
4016B		CMP32mi %vreg47, 1, %noreg, 96, %noreg, 255, %EFLAGS<imp-def>; mem:LD4[%state_in_len118] GR64:%vreg47
4032B		JNE_1 <BB#35>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#35 BB#32

4048B	BB#32: derived from LLVM BB %if.then.121
	    Predecessors according to CFG: BB#30 BB#31
4064B		%vreg56<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg56
4080B		CMP32mi %vreg56, 1, %noreg, 92, %noreg, 256, %EFLAGS<imp-def>; mem:LD4[%state_in_ch122] GR64:%vreg56
4096B		JAE_1 <BB#34>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#34 BB#33

4112B	BB#33: derived from LLVM BB %if.then.125
	    Predecessors according to CFG: BB#32
4128B		%vreg58<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg58
4144B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4160B		%RDI<def> = COPY %vreg58; GR64:%vreg58
4176B		CALL64pcrel32 <ga:@add_pair_to_block>, <regmask>, %RSP<imp-use>, %RDI<imp-use>
4192B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4208B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4224B		STACKMAP 2, 0, 0, <fi#5>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack5](align=1) LD8[FixedStack1](align=1) LD8[FixedStack0] LD8[FixedStack4](align=4)
4240B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#34

4256B	BB#34: derived from LLVM BB %if.end.126
	    Predecessors according to CFG: BB#32 BB#33
4272B		%vreg64<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%zchh77] GR32:%vreg64
4288B		%vreg63<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg63
4304B		MOV32mr %vreg63, 1, %noreg, 92, %noreg, %vreg64; mem:ST4[%state_in_ch127] GR64:%vreg63 GR32:%vreg64
4320B		%vreg60<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg60
4336B		MOV32mi %vreg60, 1, %noreg, 96, %noreg, 1; mem:ST4[%state_in_len128] GR64:%vreg60
4352B		JMP_1 <BB#36>
	    Successors according to CFG: BB#36

4368B	BB#35: derived from LLVM BB %if.else.129
	    Predecessors according to CFG: BB#31
4384B		%vreg53<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg53
4400B		%vreg52<def> = MOV32rm %vreg53, 1, %noreg, 96, %noreg; mem:LD4[%state_in_len130] GR32:%vreg52 GR64:%vreg53
4416B		%vreg51<def> = COPY %vreg52; GR32:%vreg51,%vreg52
4432B		%vreg51<def,tied1> = ADD32ri8 %vreg51<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg51
4448B		MOV32mr %vreg53, 1, %noreg, 96, %noreg, %vreg51; mem:ST4[%state_in_len130] GR64:%vreg53 GR32:%vreg51
	    Successors according to CFG: BB#36

4464B	BB#36: derived from LLVM BB %if.end.132
	    Predecessors according to CFG: BB#35 BB#34
4480B		JMP_1 <BB#37>
	    Successors according to CFG: BB#37

4496B	BB#37: derived from LLVM BB %if.end.133
	    Predecessors according to CFG: BB#36 BB#29
4512B		%vreg153<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg153
4528B		%vreg152<def> = MOV64rm %vreg153, 1, %noreg, 0, %noreg; mem:LD8[%strm134] GR64:%vreg152,%vreg153
4544B		%vreg150<def> = MOV64rm %vreg152, 1, %noreg, 0, %noreg; mem:LD8[%next_in135] GR64:%vreg150,%vreg152
4560B		%vreg149<def> = COPY %vreg150; GR64:%vreg149,%vreg150
4576B		%vreg149<def,tied1> = ADD64ri8 %vreg149<tied0>, 1, %EFLAGS<imp-def,dead>; GR64:%vreg149
4592B		MOV64mr %vreg152, 1, %noreg, 0, %noreg, %vreg149; mem:ST8[%next_in135] GR64:%vreg152,%vreg149
4608B		%vreg145<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg145
4624B		%vreg144<def> = MOV64rm %vreg145, 1, %noreg, 0, %noreg; mem:LD8[%strm137] GR64:%vreg144,%vreg145
4640B		%vreg142<def> = MOV32rm %vreg144, 1, %noreg, 8, %noreg; mem:LD4[%avail_in138] GR32:%vreg142 GR64:%vreg144
4656B		%vreg141<def> = COPY %vreg142; GR32:%vreg141,%vreg142
4672B		%vreg141<def,tied1> = ADD32ri8 %vreg141<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg141
4688B		MOV32mr %vreg144, 1, %noreg, 8, %noreg, %vreg141; mem:ST4[%avail_in138] GR64:%vreg144 GR32:%vreg141
4704B		%vreg137<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg137
4720B		%vreg136<def> = MOV64rm %vreg137, 1, %noreg, 0, %noreg; mem:LD8[%strm140] GR64:%vreg136,%vreg137
4736B		%vreg134<def> = MOV32rm %vreg136, 1, %noreg, 12, %noreg; mem:LD4[%total_in_lo32141] GR32:%vreg134 GR64:%vreg136
4752B		%vreg133<def> = COPY %vreg134; GR32:%vreg133,%vreg134
4768B		%vreg133<def,tied1> = ADD32ri8 %vreg133<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg133
4784B		MOV32mr %vreg136, 1, %noreg, 12, %noreg, %vreg133; mem:ST4[%total_in_lo32141] GR64:%vreg136 GR32:%vreg133
4800B		%vreg129<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg129
4816B		%vreg128<def> = MOV64rm %vreg129, 1, %noreg, 0, %noreg; mem:LD8[%strm143] GR64:%vreg128,%vreg129
4832B		CMP32mi8 %vreg128, 1, %noreg, 12, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%total_in_lo32144] GR64:%vreg128
4848B		JNE_1 <BB#39>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#39 BB#38

4864B	BB#38: derived from LLVM BB %if.then.147
	    Predecessors according to CFG: BB#37
4880B		%vreg161<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg161
4896B		%vreg160<def> = MOV64rm %vreg161, 1, %noreg, 0, %noreg; mem:LD8[%strm148] GR64:%vreg160,%vreg161
4912B		%vreg158<def> = MOV32rm %vreg160, 1, %noreg, 16, %noreg; mem:LD4[%total_in_hi32149] GR32:%vreg158 GR64:%vreg160
4928B		%vreg157<def> = COPY %vreg158; GR32:%vreg157,%vreg158
4944B		%vreg157<def,tied1> = ADD32ri8 %vreg157<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg157
4960B		MOV32mr %vreg160, 1, %noreg, 16, %noreg, %vreg157; mem:ST4[%total_in_hi32149] GR64:%vreg160 GR32:%vreg157
	    Successors according to CFG: BB#39

4976B	BB#39: derived from LLVM BB %if.end.151
	    Predecessors according to CFG: BB#37 BB#38
4992B		%vreg167<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg167
5008B		%vreg166<def> = MOV32rm %vreg167, 1, %noreg, 16, %noreg; mem:LD4[%avail_in_expect152] GR32:%vreg166 GR64:%vreg167
5024B		%vreg165<def> = COPY %vreg166; GR32:%vreg165,%vreg166
5040B		%vreg165<def,tied1> = ADD32ri8 %vreg165<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg165
5056B		MOV32mr %vreg167, 1, %noreg, 16, %noreg, %vreg165; mem:ST4[%avail_in_expect152] GR64:%vreg167 GR32:%vreg165
5072B		JMP_1 <BB#21>
	    Successors according to CFG: BB#21

5088B	BB#40: derived from LLVM BB %while.end.154
	    Predecessors according to CFG: BB#26 BB#24 BB#22
5104B		JMP_1 <BB#41>
	    Successors according to CFG: BB#41

5120B	BB#41: derived from LLVM BB %if.end.155
	    Predecessors according to CFG: BB#40 BB#19
5136B		%vreg320<def> = MOV64ri <ga:@copy_input_until_stop>; GR64:%vreg320
5152B		%vreg321<def> = COPY %vreg320; GR64:%vreg321,%vreg320
5168B		%vreg323<def> = MOV8rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD1[%progress_in] GR8:%vreg323
5184B		%vreg322<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg322
5200B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5216B		%RDI<def> = COPY %vreg321; GR64:%vreg321
5232B		%RSI<def> = COPY %vreg322; GR64:%vreg322
5248B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
5264B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5280B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5296B		STACKMAP 3, 0, %vreg323, ...; GR8:%vreg323
5312B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5328B		%AL<def> = COPY %vreg323; GR8:%vreg323
5344B		RETQ %AL<imp-use,kill>

# End machine code for function copy_input_until_stop.

********** SIMPLE REGISTER COALESCING **********
********** Function: copy_input_until_stop
********** JOINING INTERVALS ***********
while.body:
if.else:
if.then.32:
if.end.44:
while.body.60:
if.else.113:
if.then.121:
if.end.133:
if.end:
if.end.5:
land.lhs.true:
lor.lhs.false:
if.end.37:
if.end.43:
if.end.58:
if.end.66:
if.end.72:
if.end.76:
land.lhs.true.84:
lor.lhs.false.117:
if.end.126:
if.end.132:
if.end.151:
if.then.11:
1088B	%vreg260<def> = SUBREG_TO_REG 0, %vreg259, 4; GR64_NOSP:%vreg260 GR32:%vreg259
	Considering merging to GR64_NOSP with %vreg259 in %vreg260:sub_32bit
		RHS = %vreg259 [1072r,1088r:0)  0@1072r
		LHS = %vreg260 [1088r,1120r:0)  0@1088r
		merge %vreg260:0@1088r into %vreg259:0@1072r --> @1072r
		erased:	1088r	%vreg260<def> = SUBREG_TO_REG 0, %vreg259, 4; GR64_NOSP:%vreg260 GR32:%vreg259
		updated: 1072B	%vreg260:sub_32bit<def,read-undef> = MOV32rr %vreg263; GR64_NOSP:%vreg260 GR32:%vreg263
	Success: %vreg259:sub_32bit -> %vreg260
	Result = %vreg260 [1072r,1120r:0)  0@1072r
1200B	%vreg248<def> = SUBREG_TO_REG 0, %vreg247, 4; GR64_NOSP:%vreg248 GR32:%vreg247
	Considering merging to GR64_NOSP with %vreg247 in %vreg248:sub_32bit
		RHS = %vreg247 [1184r,1200r:0)  0@1184r
		LHS = %vreg248 [1200r,1232r:0)  0@1200r
		merge %vreg248:0@1200r into %vreg247:0@1184r --> @1184r
		erased:	1200r	%vreg248<def> = SUBREG_TO_REG 0, %vreg247, 4; GR64_NOSP:%vreg248 GR32:%vreg247
		updated: 1184B	%vreg248:sub_32bit<def,read-undef> = MOV32rm %vreg250, 1, %noreg, 92, %noreg; mem:LD4[%state_in_ch18] GR64_NOSP:%vreg248 GR64:%vreg250
	Success: %vreg247:sub_32bit -> %vreg248
	Result = %vreg248 [1184r,1232r:0)  0@1184r
if.then.36:
1744B	%RDI<def> = COPY %vreg215; GR64:%vreg215
	Considering merging %vreg215 with %RDI
	Can only merge into reserved registers.
if.else.40:
if.then.55:
if.then.88:
3504B	%vreg103<def> = SUBREG_TO_REG 0, %vreg102, 4; GR64_NOSP:%vreg103 GR32:%vreg102
	Considering merging to GR64_NOSP with %vreg102 in %vreg103:sub_32bit
		RHS = %vreg102 [3488r,3504r:0)  0@3488r
		LHS = %vreg103 [3504r,3536r:0)  0@3504r
		merge %vreg103:0@3504r into %vreg102:0@3488r --> @3488r
		erased:	3504r	%vreg103<def> = SUBREG_TO_REG 0, %vreg102, 4; GR64_NOSP:%vreg103 GR32:%vreg102
		updated: 3488B	%vreg103:sub_32bit<def,read-undef> = MOV32rr %vreg106; GR64_NOSP:%vreg103 GR32:%vreg106
	Success: %vreg102:sub_32bit -> %vreg103
	Result = %vreg103 [3488r,3536r:0)  0@3488r
3616B	%vreg91<def> = SUBREG_TO_REG 0, %vreg90, 4; GR64_NOSP:%vreg91 GR32:%vreg90
	Considering merging to GR64_NOSP with %vreg90 in %vreg91:sub_32bit
		RHS = %vreg90 [3600r,3616r:0)  0@3600r
		LHS = %vreg91 [3616r,3648r:0)  0@3616r
		merge %vreg91:0@3616r into %vreg90:0@3600r --> @3600r
		erased:	3616r	%vreg91<def> = SUBREG_TO_REG 0, %vreg90, 4; GR64_NOSP:%vreg91 GR32:%vreg90
		updated: 3600B	%vreg91:sub_32bit<def,read-undef> = MOV32rm %vreg93, 1, %noreg, 92, %noreg; mem:LD4[%state_in_ch102] GR64_NOSP:%vreg91 GR64:%vreg93
	Success: %vreg90:sub_32bit -> %vreg91
	Result = %vreg91 [3600r,3648r:0)  0@3600r
if.then.125:
4160B	%RDI<def> = COPY %vreg58; GR64:%vreg58
	Considering merging %vreg58 with %RDI
	Can only merge into reserved registers.
if.else.129:
if.then.147:
2144B	%vreg306<def> = COPY %vreg307; GR64:%vreg306,%vreg307
	Considering merging to GR64 with %vreg307 in %vreg306
		RHS = %vreg307 [2128r,2144r:0)  0@2128r
		LHS = %vreg306 [2144r,2160r:0)[2160r,2176r:1)  0@2144r 1@2160r
		merge %vreg306:0@2144r into %vreg307:0@2128r --> @2128r
		erased:	2144r	%vreg306<def> = COPY %vreg307; GR64:%vreg306,%vreg307
		updated: 2128B	%vreg306<def> = MOV64rm %vreg309, 1, %noreg, 0, %noreg; mem:LD8[%next_in46] GR64:%vreg306,%vreg309
	Success: %vreg307 -> %vreg306
	Result = %vreg306 [2128r,2160r:0)[2160r,2176r:1)  0@2128r 1@2160r
2240B	%vreg298<def> = COPY %vreg299; GR32:%vreg298,%vreg299
	Considering merging to GR32 with %vreg299 in %vreg298
		RHS = %vreg299 [2224r,2240r:0)  0@2224r
		LHS = %vreg298 [2240r,2256r:0)[2256r,2272r:1)  0@2240r 1@2256r
		merge %vreg298:0@2240r into %vreg299:0@2224r --> @2224r
		erased:	2240r	%vreg298<def> = COPY %vreg299; GR32:%vreg298,%vreg299
		updated: 2224B	%vreg298<def> = MOV32rm %vreg301, 1, %noreg, 8, %noreg; mem:LD4[%avail_in48] GR32:%vreg298 GR64:%vreg301
	Success: %vreg299 -> %vreg298
	Result = %vreg298 [2224r,2256r:0)[2256r,2272r:1)  0@2224r 1@2256r
2336B	%vreg290<def> = COPY %vreg291; GR32:%vreg290,%vreg291
	Considering merging to GR32 with %vreg291 in %vreg290
		RHS = %vreg291 [2320r,2336r:0)  0@2320r
		LHS = %vreg290 [2336r,2352r:0)[2352r,2368r:1)  0@2336r 1@2352r
		merge %vreg290:0@2336r into %vreg291:0@2320r --> @2320r
		erased:	2336r	%vreg290<def> = COPY %vreg291; GR32:%vreg290,%vreg291
		updated: 2320B	%vreg290<def> = MOV32rm %vreg293, 1, %noreg, 12, %noreg; mem:LD4[%total_in_lo32] GR32:%vreg290 GR64:%vreg293
	Success: %vreg291 -> %vreg290
	Result = %vreg290 [2320r,2352r:0)[2352r,2368r:1)  0@2320r 1@2352r
4560B	%vreg149<def> = COPY %vreg150; GR64:%vreg149,%vreg150
	Considering merging to GR64 with %vreg150 in %vreg149
		RHS = %vreg150 [4544r,4560r:0)  0@4544r
		LHS = %vreg149 [4560r,4576r:0)[4576r,4592r:1)  0@4560r 1@4576r
		merge %vreg149:0@4560r into %vreg150:0@4544r --> @4544r
		erased:	4560r	%vreg149<def> = COPY %vreg150; GR64:%vreg149,%vreg150
		updated: 4544B	%vreg149<def> = MOV64rm %vreg152, 1, %noreg, 0, %noreg; mem:LD8[%next_in135] GR64:%vreg149,%vreg152
	Success: %vreg150 -> %vreg149
	Result = %vreg149 [4544r,4576r:0)[4576r,4592r:1)  0@4544r 1@4576r
4656B	%vreg141<def> = COPY %vreg142; GR32:%vreg141,%vreg142
	Considering merging to GR32 with %vreg142 in %vreg141
		RHS = %vreg142 [4640r,4656r:0)  0@4640r
		LHS = %vreg141 [4656r,4672r:0)[4672r,4688r:1)  0@4656r 1@4672r
		merge %vreg141:0@4656r into %vreg142:0@4640r --> @4640r
		erased:	4656r	%vreg141<def> = COPY %vreg142; GR32:%vreg141,%vreg142
		updated: 4640B	%vreg141<def> = MOV32rm %vreg144, 1, %noreg, 8, %noreg; mem:LD4[%avail_in138] GR32:%vreg141 GR64:%vreg144
	Success: %vreg142 -> %vreg141
	Result = %vreg141 [4640r,4672r:0)[4672r,4688r:1)  0@4640r 1@4672r
4752B	%vreg133<def> = COPY %vreg134; GR32:%vreg133,%vreg134
	Considering merging to GR32 with %vreg134 in %vreg133
		RHS = %vreg134 [4736r,4752r:0)  0@4736r
		LHS = %vreg133 [4752r,4768r:0)[4768r,4784r:1)  0@4752r 1@4768r
		merge %vreg133:0@4752r into %vreg134:0@4736r --> @4736r
		erased:	4752r	%vreg133<def> = COPY %vreg134; GR32:%vreg133,%vreg134
		updated: 4736B	%vreg133<def> = MOV32rm %vreg136, 1, %noreg, 12, %noreg; mem:LD4[%total_in_lo32141] GR32:%vreg133 GR64:%vreg136
	Success: %vreg134 -> %vreg133
	Result = %vreg133 [4736r,4768r:0)[4768r,4784r:1)  0@4736r 1@4768r
5024B	%vreg165<def> = COPY %vreg166; GR32:%vreg165,%vreg166
	Considering merging to GR32 with %vreg166 in %vreg165
		RHS = %vreg166 [5008r,5024r:0)  0@5008r
		LHS = %vreg165 [5024r,5040r:0)[5040r,5056r:1)  0@5024r 1@5040r
		merge %vreg165:0@5024r into %vreg166:0@5008r --> @5008r
		erased:	5024r	%vreg165<def> = COPY %vreg166; GR32:%vreg165,%vreg166
		updated: 5008B	%vreg165<def> = MOV32rm %vreg167, 1, %noreg, 16, %noreg; mem:LD4[%avail_in_expect152] GR32:%vreg165 GR64:%vreg167
	Success: %vreg166 -> %vreg165
	Result = %vreg165 [5008r,5040r:0)[5040r,5056r:1)  0@5008r 1@5040r
864B	%vreg278<def> = COPY %vreg280:sub_8bit; GR8:%vreg278 GR32:%vreg280
	Considering merging to GR32 with %vreg278 in %vreg280:sub_8bit
		RHS = %vreg278 [864r,880r:0)  0@864r
		LHS = %vreg280 [848r,864r:0)  0@848r
		merge %vreg278:0@864r into %vreg280:0@848r --> @848r
		erased:	864r	%vreg278<def> = COPY %vreg280:sub_8bit; GR8:%vreg278 GR32:%vreg280
		updated: 880B	MOV8mr <fi#3>, 1, %noreg, 0, %noreg, %vreg280:sub_8bit; mem:ST1[%ch] GR32:%vreg280
	Success: %vreg278:sub_8bit -> %vreg280
	Result = %vreg280 [848r,880r:0)  0@848r
928B	%vreg272<def> = COPY %vreg274; GR32:%vreg272,%vreg274
	Considering merging to GR32 with %vreg274 in %vreg272
		RHS = %vreg274 [912r,928r:0)  0@912r
		LHS = %vreg272 [928r,944r:0)[944r,1104r:1)  0@928r 1@944r
		merge %vreg272:0@928r into %vreg274:0@912r --> @912r
		erased:	928r	%vreg272<def> = COPY %vreg274; GR32:%vreg272,%vreg274
		updated: 912B	%vreg272<def> = MOV32rm %vreg275, 1, %noreg, 648, %noreg; mem:LD4[%blockCRC] GR32:%vreg272 GR64:%vreg275
	Success: %vreg274 -> %vreg272
	Result = %vreg272 [912r,944r:0)[944r,1104r:1)  0@912r 1@944r
992B	%vreg267<def> = COPY %vreg269; GR32:%vreg267,%vreg269
	Considering merging to GR32 with %vreg269 in %vreg267
		RHS = %vreg269 [976r,992r:0)  0@976r
		LHS = %vreg267 [992r,1008r:0)[1008r,1040r:1)  0@992r 1@1008r
		merge %vreg267:0@992r into %vreg269:0@976r --> @976r
		erased:	992r	%vreg267<def> = COPY %vreg269; GR32:%vreg267,%vreg269
		updated: 976B	%vreg267<def> = MOV32rm %vreg270, 1, %noreg, 648, %noreg; mem:LD4[%blockCRC14] GR32:%vreg267 GR64:%vreg270
	Success: %vreg269 -> %vreg267
	Result = %vreg267 [976r,1008r:0)[1008r,1040r:1)  0@976r 1@1008r
1040B	%vreg263<def> = COPY %vreg267; GR32:%vreg263,%vreg267
	Considering merging to GR32 with %vreg267 in %vreg263
		RHS = %vreg267 [976r,1008r:0)[1008r,1040r:1)  0@976r 1@1008r
		LHS = %vreg263 [1040r,1056r:0)[1056r,1072r:1)  0@1040r 1@1056r
		merge %vreg263:0@1040r into %vreg267:1@1008r --> @1008r
		erased:	1040r	%vreg263<def> = COPY %vreg267; GR32:%vreg263,%vreg267
		updated: 976B	%vreg263<def> = MOV32rm %vreg270, 1, %noreg, 648, %noreg; mem:LD4[%blockCRC14] GR32:%vreg263 GR64:%vreg270
		updated: 1008B	%vreg263<def,tied1> = SHR32ri %vreg263<tied0>, 24, %EFLAGS<imp-def,dead>; GR32:%vreg263
	Success: %vreg267 -> %vreg263
	Result = %vreg263 [976r,1008r:2)[1008r,1056r:0)[1056r,1072r:1)  0@1008r 1@1056r 2@976r
1104B	%vreg256<def> = COPY %vreg272; GR32:%vreg256,%vreg272
	Considering merging to GR32 with %vreg272 in %vreg256
		RHS = %vreg272 [912r,944r:0)[944r,1104r:1)  0@912r 1@944r
		LHS = %vreg256 [1104r,1120r:0)[1120r,1152r:1)  0@1104r 1@1120r
		merge %vreg256:0@1104r into %vreg272:1@944r --> @944r
		erased:	1104r	%vreg256<def> = COPY %vreg272; GR32:%vreg256,%vreg272
		updated: 912B	%vreg256<def> = MOV32rm %vreg275, 1, %noreg, 648, %noreg; mem:LD4[%blockCRC] GR32:%vreg256 GR64:%vreg275
		updated: 944B	%vreg256<def,tied1> = SHL32ri %vreg256<tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg256
	Success: %vreg272 -> %vreg256
	Result = %vreg256 [912r,944r:2)[944r,1120r:0)[1120r,1152r:1)  0@944r 1@1120r 2@912r
1376B	%vreg229<def> = COPY %vreg230; GR32:%vreg229,%vreg230
	Considering merging to GR32 with %vreg230 in %vreg229
		RHS = %vreg230 [1360r,1376r:0)  0@1360r
		LHS = %vreg229 [1376r,1392r:0)[1392r,1408r:1)  0@1376r 1@1392r
		merge %vreg229:0@1376r into %vreg230:0@1360r --> @1360r
		erased:	1376r	%vreg229<def> = COPY %vreg230; GR32:%vreg229,%vreg230
		updated: 1360B	%vreg229<def> = MOV32rm %vreg231, 1, %noreg, 108, %noreg; mem:LD4[%nblock24] GR32:%vreg229 GR64:%vreg231
	Success: %vreg230 -> %vreg229
	Result = %vreg229 [1360r,1392r:0)[1392r,1408r:1)  0@1360r 1@1392r
2000B	%vreg208<def> = COPY %vreg209; GR32:%vreg208,%vreg209
	Considering merging to GR32 with %vreg209 in %vreg208
		RHS = %vreg209 [1984r,2000r:0)  0@1984r
		LHS = %vreg208 [2000r,2016r:0)[2016r,2032r:1)  0@2000r 1@2016r
		merge %vreg208:0@2000r into %vreg209:0@1984r --> @1984r
		erased:	2000r	%vreg208<def> = COPY %vreg209; GR32:%vreg208,%vreg209
		updated: 1984B	%vreg208<def> = MOV32rm %vreg210, 1, %noreg, 96, %noreg; mem:LD4[%state_in_len41] GR32:%vreg208 GR64:%vreg210
	Success: %vreg209 -> %vreg208
	Result = %vreg208 [1984r,2016r:0)[2016r,2032r:1)  0@1984r 1@2016r
2512B	%vreg314<def> = COPY %vreg315; GR32:%vreg314,%vreg315
	Considering merging to GR32 with %vreg315 in %vreg314
		RHS = %vreg315 [2496r,2512r:0)  0@2496r
		LHS = %vreg314 [2512r,2528r:0)[2528r,2544r:1)  0@2512r 1@2528r
		merge %vreg314:0@2512r into %vreg315:0@2496r --> @2496r
		erased:	2512r	%vreg314<def> = COPY %vreg315; GR32:%vreg314,%vreg315
		updated: 2496B	%vreg314<def> = MOV32rm %vreg317, 1, %noreg, 16, %noreg; mem:LD4[%total_in_hi32] GR32:%vreg314 GR64:%vreg317
	Success: %vreg315 -> %vreg314
	Result = %vreg314 [2496r,2528r:0)[2528r,2544r:1)  0@2496r 1@2528r
3280B	%vreg121<def> = COPY %vreg123:sub_8bit; GR8:%vreg121 GR32:%vreg123
	Considering merging to GR32 with %vreg121 in %vreg123:sub_8bit
		RHS = %vreg121 [3280r,3296r:0)  0@3280r
		LHS = %vreg123 [3264r,3280r:0)  0@3264r
		merge %vreg121:0@3280r into %vreg123:0@3264r --> @3264r
		erased:	3280r	%vreg121<def> = COPY %vreg123:sub_8bit; GR8:%vreg121 GR32:%vreg123
		updated: 3296B	MOV8mr <fi#5>, 1, %noreg, 0, %noreg, %vreg123:sub_8bit; mem:ST1[%ch89] GR32:%vreg123
	Success: %vreg121:sub_8bit -> %vreg123
	Result = %vreg123 [3264r,3296r:0)  0@3264r
3344B	%vreg115<def> = COPY %vreg117; GR32:%vreg115,%vreg117
	Considering merging to GR32 with %vreg117 in %vreg115
		RHS = %vreg117 [3328r,3344r:0)  0@3328r
		LHS = %vreg115 [3344r,3360r:0)[3360r,3520r:1)  0@3344r 1@3360r
		merge %vreg115:0@3344r into %vreg117:0@3328r --> @3328r
		erased:	3344r	%vreg115<def> = COPY %vreg117; GR32:%vreg115,%vreg117
		updated: 3328B	%vreg115<def> = MOV32rm %vreg118, 1, %noreg, 648, %noreg; mem:LD4[%blockCRC92] GR32:%vreg115 GR64:%vreg118
	Success: %vreg117 -> %vreg115
	Result = %vreg115 [3328r,3360r:0)[3360r,3520r:1)  0@3328r 1@3360r
3408B	%vreg110<def> = COPY %vreg112; GR32:%vreg110,%vreg112
	Considering merging to GR32 with %vreg112 in %vreg110
		RHS = %vreg112 [3392r,3408r:0)  0@3392r
		LHS = %vreg110 [3408r,3424r:0)[3424r,3456r:1)  0@3408r 1@3424r
		merge %vreg110:0@3408r into %vreg112:0@3392r --> @3392r
		erased:	3408r	%vreg110<def> = COPY %vreg112; GR32:%vreg110,%vreg112
		updated: 3392B	%vreg110<def> = MOV32rm %vreg113, 1, %noreg, 648, %noreg; mem:LD4[%blockCRC94] GR32:%vreg110 GR64:%vreg113
	Success: %vreg112 -> %vreg110
	Result = %vreg110 [3392r,3424r:0)[3424r,3456r:1)  0@3392r 1@3424r
3456B	%vreg106<def> = COPY %vreg110; GR32:%vreg106,%vreg110
	Considering merging to GR32 with %vreg110 in %vreg106
		RHS = %vreg110 [3392r,3424r:0)[3424r,3456r:1)  0@3392r 1@3424r
		LHS = %vreg106 [3456r,3472r:0)[3472r,3488r:1)  0@3456r 1@3472r
		merge %vreg106:0@3456r into %vreg110:1@3424r --> @3424r
		erased:	3456r	%vreg106<def> = COPY %vreg110; GR32:%vreg106,%vreg110
		updated: 3392B	%vreg106<def> = MOV32rm %vreg113, 1, %noreg, 648, %noreg; mem:LD4[%blockCRC94] GR32:%vreg106 GR64:%vreg113
		updated: 3424B	%vreg106<def,tied1> = SHR32ri %vreg106<tied0>, 24, %EFLAGS<imp-def,dead>; GR32:%vreg106
	Success: %vreg110 -> %vreg106
	Result = %vreg106 [3392r,3424r:2)[3424r,3472r:0)[3472r,3488r:1)  0@3424r 1@3472r 2@3392r
3520B	%vreg99<def> = COPY %vreg115; GR32:%vreg99,%vreg115
	Considering merging to GR32 with %vreg115 in %vreg99
		RHS = %vreg115 [3328r,3360r:0)[3360r,3520r:1)  0@3328r 1@3360r
		LHS = %vreg99 [3520r,3536r:0)[3536r,3568r:1)  0@3520r 1@3536r
		merge %vreg99:0@3520r into %vreg115:1@3360r --> @3360r
		erased:	3520r	%vreg99<def> = COPY %vreg115; GR32:%vreg99,%vreg115
		updated: 3328B	%vreg99<def> = MOV32rm %vreg118, 1, %noreg, 648, %noreg; mem:LD4[%blockCRC92] GR32:%vreg99 GR64:%vreg118
		updated: 3360B	%vreg99<def,tied1> = SHL32ri %vreg99<tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg99
	Success: %vreg115 -> %vreg99
	Result = %vreg99 [3328r,3360r:2)[3360r,3536r:0)[3536r,3568r:1)  0@3360r 1@3536r 2@3328r
3792B	%vreg72<def> = COPY %vreg73; GR32:%vreg72,%vreg73
	Considering merging to GR32 with %vreg73 in %vreg72
		RHS = %vreg73 [3776r,3792r:0)  0@3776r
		LHS = %vreg72 [3792r,3808r:0)[3808r,3824r:1)  0@3792r 1@3808r
		merge %vreg72:0@3792r into %vreg73:0@3776r --> @3776r
		erased:	3792r	%vreg72<def> = COPY %vreg73; GR32:%vreg72,%vreg73
		updated: 3776B	%vreg72<def> = MOV32rm %vreg74, 1, %noreg, 108, %noreg; mem:LD4[%nblock110] GR32:%vreg72 GR64:%vreg74
	Success: %vreg73 -> %vreg72
	Result = %vreg72 [3776r,3808r:0)[3808r,3824r:1)  0@3776r 1@3808r
4416B	%vreg51<def> = COPY %vreg52; GR32:%vreg51,%vreg52
	Considering merging to GR32 with %vreg52 in %vreg51
		RHS = %vreg52 [4400r,4416r:0)  0@4400r
		LHS = %vreg51 [4416r,4432r:0)[4432r,4448r:1)  0@4416r 1@4432r
		merge %vreg51:0@4416r into %vreg52:0@4400r --> @4400r
		erased:	4416r	%vreg51<def> = COPY %vreg52; GR32:%vreg51,%vreg52
		updated: 4400B	%vreg51<def> = MOV32rm %vreg53, 1, %noreg, 96, %noreg; mem:LD4[%state_in_len130] GR32:%vreg51 GR64:%vreg53
	Success: %vreg52 -> %vreg51
	Result = %vreg51 [4400r,4432r:0)[4432r,4448r:1)  0@4400r 1@4432r
4928B	%vreg157<def> = COPY %vreg158; GR32:%vreg157,%vreg158
	Considering merging to GR32 with %vreg158 in %vreg157
		RHS = %vreg158 [4912r,4928r:0)  0@4912r
		LHS = %vreg157 [4928r,4944r:0)[4944r,4960r:1)  0@4928r 1@4944r
		merge %vreg157:0@4928r into %vreg158:0@4912r --> @4912r
		erased:	4928r	%vreg157<def> = COPY %vreg158; GR32:%vreg157,%vreg158
		updated: 4912B	%vreg157<def> = MOV32rm %vreg160, 1, %noreg, 16, %noreg; mem:LD4[%total_in_hi32149] GR32:%vreg157 GR64:%vreg160
	Success: %vreg158 -> %vreg157
	Result = %vreg157 [4912r,4944r:0)[4944r,4960r:1)  0@4912r 1@4944r
while.end.154:
while.end:
entry:
16B	%vreg0<def> = COPY %RDI; GR64:%vreg0
	Considering merging %vreg0 with %RDI
	Can only merge into reserved registers.
112B	%RDI<def> = COPY %vreg6; GR64:%vreg6
	Considering merging %vreg6 with %RDI
	Can only merge into reserved registers.
128B	%RSI<def> = COPY %vreg7; GR64:%vreg7
	Considering merging %vreg7 with %RSI
	Can only merge into reserved registers.
if.then:
if.then.2:
if.then.4:
if.else.59:
if.then.65:
if.then.71:
if.then.75:
if.end.155:
5216B	%RDI<def> = COPY %vreg321; GR64:%vreg321
	Considering merging %vreg321 with %RDI
	Can only merge into reserved registers.
5232B	%RSI<def> = COPY %vreg322; GR64:%vreg322
	Considering merging %vreg322 with %RSI
	Can only merge into reserved registers.
5328B	%AL<def> = COPY %vreg323; GR8:%vreg323
	Considering merging %vreg323 with %AL
	Can only merge into reserved registers.
32B	%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
	Considering merging to GR64 with %vreg0 in %vreg1
		RHS = %vreg0 [16r,32r:0)  0@16r
		LHS = %vreg1 [32r,224r:0)  0@32r
		merge %vreg1:0@32r into %vreg0:0@16r --> @16r
		erased:	32r	%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
		updated: 16B	%vreg1<def> = COPY %RDI; GR64:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [16r,224r:0)  0@16r
64B	%vreg6<def> = COPY %vreg5; GR64:%vreg6,%vreg5
	Considering merging to GR64 with %vreg5 in %vreg6
		RHS = %vreg5 [48r,64r:0)  0@48r
		LHS = %vreg6 [64r,112r:0)  0@64r
		merge %vreg6:0@64r into %vreg5:0@48r --> @48r
		erased:	64r	%vreg6<def> = COPY %vreg5; GR64:%vreg6,%vreg5
		updated: 48B	%vreg6<def> = MOV64ri <ga:@copy_input_until_stop>; GR64:%vreg6
	Success: %vreg5 -> %vreg6
	Result = %vreg6 [48r,112r:0)  0@48r
5152B	%vreg321<def> = COPY %vreg320; GR64:%vreg321,%vreg320
	Considering merging to GR64 with %vreg320 in %vreg321
		RHS = %vreg320 [5136r,5152r:0)  0@5136r
		LHS = %vreg321 [5152r,5216r:0)  0@5152r
		merge %vreg321:0@5152r into %vreg320:0@5136r --> @5136r
		erased:	5152r	%vreg321<def> = COPY %vreg320; GR64:%vreg321,%vreg320
		updated: 5136B	%vreg321<def> = MOV64ri <ga:@copy_input_until_stop>; GR64:%vreg321
	Success: %vreg320 -> %vreg321
	Result = %vreg321 [5136r,5216r:0)  0@5136r
112B	%RDI<def> = COPY %vreg6; GR64:%vreg6
	Considering merging %vreg6 with %RDI
	Can only merge into reserved registers.
5216B	%RDI<def> = COPY %vreg321; GR64:%vreg321
	Considering merging %vreg321 with %RDI
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
DIL [0B,16r:0)[112r,144r:4)[1744r,1760r:2)[4160r,4176r:3)[5216r,5248r:1)  0@0B-phi 1@5216r 2@1744r 3@4160r 4@112r
%vreg1 [16r,224r:0)  0@16r
%vreg4 [256r,272r:0)  0@256r
%vreg6 [48r,112r:0)  0@48r
%vreg7 [80r,128r:0)  0@80r
%vreg11 [2704r,2720r:0)  0@2704r
%vreg13 [2688r,2720r:0)  0@2688r
%vreg14 [2672r,2688r:0)  0@2672r
%vreg18 [2816r,2832r:0)  0@2816r
%vreg19 [2800r,2816r:0)  0@2800r
%vreg22 [2912r,2928r:0)  0@2912r
%vreg26 [3120r,3136r:0)  0@3120r
%vreg27 [3104r,3136r:0)  0@3104r
%vreg30 [3072r,3088r:0)  0@3072r
%vreg33 [3056r,3072r:0)  0@3056r
%vreg35 [3040r,3056r:0)  0@3040r
%vreg36 [3024r,3040r:0)  0@3024r
%vreg39 [3184r,3200r:0)  0@3184r
%vreg43 [3936r,3952r:0)  0@3936r
%vreg44 [3920r,3952r:0)  0@3920r
%vreg47 [4000r,4016r:0)  0@4000r
%vreg51 [4400r,4432r:0)[4432r,4448r:1)  0@4400r 1@4432r
%vreg53 [4384r,4448r:0)  0@4384r
%vreg56 [4064r,4080r:0)  0@4064r
%vreg58 [4128r,4160r:0)  0@4128r
%vreg60 [4320r,4336r:0)  0@4320r
%vreg63 [4288r,4304r:0)  0@4288r
%vreg64 [4272r,4304r:0)  0@4272r
%vreg67 [3856r,3872r:0)  0@3856r
%vreg68 [3840r,3872r:0)  0@3840r
%vreg72 [3776r,3808r:0)[3808r,3824r:1)  0@3776r 1@3808r
%vreg74 [3760r,3824r:0)  0@3760r
%vreg79 [3728r,3744r:0)  0@3728r
%vreg80 [3712r,3728r:0)  0@3712r
%vreg82 [3696r,3744r:0)  0@3696r
%vreg84 [3680r,3696r:0)  0@3680r
%vreg85 [3664r,3744r:0)  0@3664r
%vreg88 [3632r,3648r:0)  0@3632r
%vreg91 [3600r,3648r:0)  0@3600r
%vreg93 [3584r,3600r:0)  0@3584r
%vreg96 [3552r,3568r:0)  0@3552r
%vreg99 [3328r,3360r:2)[3360r,3536r:0)[3536r,3568r:1)  0@3360r 1@3536r 2@3328r
%vreg103 [3488r,3536r:0)  0@3488r
%vreg106 [3392r,3424r:2)[3424r,3472r:0)[3472r,3488r:1)  0@3424r 1@3472r 2@3392r
%vreg108 [3440r,3472r:0)  0@3440r
%vreg113 [3376r,3392r:0)  0@3376r
%vreg118 [3312r,3328r:0)  0@3312r
%vreg123 [3264r,3296r:0)  0@3264r
%vreg124 [3248r,3264r:0)  0@3248r
%vreg128 [4816r,4832r:0)  0@4816r
%vreg129 [4800r,4816r:0)  0@4800r
%vreg133 [4736r,4768r:0)[4768r,4784r:1)  0@4736r 1@4768r
%vreg136 [4720r,4784r:0)  0@4720r
%vreg137 [4704r,4720r:0)  0@4704r
%vreg141 [4640r,4672r:0)[4672r,4688r:1)  0@4640r 1@4672r
%vreg144 [4624r,4688r:0)  0@4624r
%vreg145 [4608r,4624r:0)  0@4608r
%vreg149 [4544r,4576r:0)[4576r,4592r:1)  0@4544r 1@4576r
%vreg152 [4528r,4592r:0)  0@4528r
%vreg153 [4512r,4528r:0)  0@4512r
%vreg157 [4912r,4944r:0)[4944r,4960r:1)  0@4912r 1@4944r
%vreg160 [4896r,4960r:0)  0@4896r
%vreg161 [4880r,4896r:0)  0@4880r
%vreg165 [5008r,5040r:0)[5040r,5056r:1)  0@5008r 1@5040r
%vreg167 [4992r,5056r:0)  0@4992r
%vreg171 [384r,400r:0)  0@384r
%vreg173 [368r,400r:0)  0@368r
%vreg174 [352r,368r:0)  0@352r
%vreg178 [496r,512r:0)  0@496r
%vreg179 [480r,496r:0)  0@480r
%vreg183 [704r,720r:0)  0@704r
%vreg184 [688r,720r:0)  0@688r
%vreg187 [656r,672r:0)  0@656r
%vreg190 [640r,656r:0)  0@640r
%vreg192 [624r,640r:0)  0@624r
%vreg193 [608r,624r:0)  0@608r
%vreg196 [768r,784r:0)  0@768r
%vreg200 [1520r,1536r:0)  0@1520r
%vreg201 [1504r,1536r:0)  0@1504r
%vreg204 [1584r,1600r:0)  0@1584r
%vreg208 [1984r,2016r:0)[2016r,2032r:1)  0@1984r 1@2016r
%vreg210 [1968r,2032r:0)  0@1968r
%vreg213 [1648r,1664r:0)  0@1648r
%vreg215 [1712r,1744r:0)  0@1712r
%vreg217 [1904r,1920r:0)  0@1904r
%vreg220 [1872r,1888r:0)  0@1872r
%vreg221 [1856r,1888r:0)  0@1856r
%vreg224 [1440r,1456r:0)  0@1440r
%vreg225 [1424r,1456r:0)  0@1424r
%vreg229 [1360r,1392r:0)[1392r,1408r:1)  0@1360r 1@1392r
%vreg231 [1344r,1408r:0)  0@1344r
%vreg236 [1312r,1328r:0)  0@1312r
%vreg237 [1296r,1312r:0)  0@1296r
%vreg239 [1280r,1328r:0)  0@1280r
%vreg241 [1264r,1280r:0)  0@1264r
%vreg242 [1248r,1328r:0)  0@1248r
%vreg245 [1216r,1232r:0)  0@1216r
%vreg248 [1184r,1232r:0)  0@1184r
%vreg250 [1168r,1184r:0)  0@1168r
%vreg253 [1136r,1152r:0)  0@1136r
%vreg256 [912r,944r:2)[944r,1120r:0)[1120r,1152r:1)  0@944r 1@1120r 2@912r
%vreg260 [1072r,1120r:0)  0@1072r
%vreg263 [976r,1008r:2)[1008r,1056r:0)[1056r,1072r:1)  0@1008r 1@1056r 2@976r
%vreg265 [1024r,1056r:0)  0@1024r
%vreg270 [960r,976r:0)  0@960r
%vreg275 [896r,912r:0)  0@896r
%vreg280 [848r,880r:0)  0@848r
%vreg281 [832r,848r:0)  0@832r
%vreg285 [2400r,2416r:0)  0@2400r
%vreg286 [2384r,2400r:0)  0@2384r
%vreg290 [2320r,2352r:0)[2352r,2368r:1)  0@2320r 1@2352r
%vreg293 [2304r,2368r:0)  0@2304r
%vreg294 [2288r,2304r:0)  0@2288r
%vreg298 [2224r,2256r:0)[2256r,2272r:1)  0@2224r 1@2256r
%vreg301 [2208r,2272r:0)  0@2208r
%vreg302 [2192r,2208r:0)  0@2192r
%vreg306 [2128r,2160r:0)[2160r,2176r:1)  0@2128r 1@2160r
%vreg309 [2112r,2176r:0)  0@2112r
%vreg310 [2096r,2112r:0)  0@2096r
%vreg314 [2496r,2528r:0)[2528r,2544r:1)  0@2496r 1@2528r
%vreg317 [2480r,2544r:0)  0@2480r
%vreg318 [2464r,2480r:0)  0@2464r
%vreg321 [5136r,5216r:0)  0@5136r
%vreg322 [5184r,5232r:0)  0@5184r
%vreg323 [5168r,5328r:0)  0@5168r
RegMasks: 144r 1760r 4176r 5248r
********** MACHINEINSTRS **********
# Machine code for function copy_input_until_stop: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=8, align=8, at location [SP+8]
  fi#1: size=1, align=1, at location [SP+8]
  fi#2: size=4, align=4, at location [SP+8]
  fi#3: size=1, align=1, at location [SP+8]
  fi#4: size=4, align=4, at location [SP+8]
  fi#5: size=1, align=1, at location [SP+8]
Function Live Ins: %RDI in %vreg0

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI
16B		%vreg1<def> = COPY %RDI; GR64:%vreg1
48B		%vreg6<def> = MOV64ri <ga:@copy_input_until_stop>; GR64:%vreg6
80B		%vreg7<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg7
96B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
112B		%RDI<def> = COPY %vreg6; GR64:%vreg6
128B		%RSI<def> = COPY %vreg7; GR64:%vreg7
144B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
160B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
192B		STACKMAP 0, 0, 0, <fi#3>, 0, 0, <fi#5>, 0, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack3](align=1) LD8[FixedStack5](align=1) LD8[FixedStack1](align=1) LD8[FixedStack0] LD8[FixedStack2](align=4) LD8[FixedStack4](align=4) GR64:%vreg1
208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%s.addr] GR64:%vreg1
240B		MOV8mi <fi#1>, 1, %noreg, 0, %noreg, 0; mem:ST1[%progress_in]
256B		%vreg4<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg4
272B		CMP32mi8 %vreg4, 1, %noreg, 8, %noreg, 2, %EFLAGS<imp-def>; mem:LD4[%mode] GR64:%vreg4
288B		JNE_1 <BB#20>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#20 BB#1

304B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
320B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2

336B	BB#2: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#1 BB#18
352B		%vreg174<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg174
368B		%vreg173<def> = MOV32rm %vreg174, 1, %noreg, 108, %noreg; mem:LD4[%nblock] GR32:%vreg173 GR64:%vreg174
384B		%vreg171<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg171
400B		CMP32rm %vreg173, %vreg171, 1, %noreg, 112, %noreg, %EFLAGS<imp-def>; mem:LD4[%nblockMAX] GR32:%vreg173 GR64:%vreg171
416B		JL_1 <BB#4>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#4 BB#3

432B	BB#3: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#2
448B		JMP_1 <BB#19>
	    Successors according to CFG: BB#19

464B	BB#4: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#2
480B		%vreg179<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg179
496B		%vreg178<def> = MOV64rm %vreg179, 1, %noreg, 0, %noreg; mem:LD8[%strm] GR64:%vreg178,%vreg179
512B		CMP32mi8 %vreg178, 1, %noreg, 8, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_in] GR64:%vreg178
528B		JNE_1 <BB#6>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#6 BB#5

544B	BB#5: derived from LLVM BB %if.then.4
	    Predecessors according to CFG: BB#4
560B		JMP_1 <BB#19>
	    Successors according to CFG: BB#19

576B	BB#6: derived from LLVM BB %if.end.5
	    Predecessors according to CFG: BB#4
592B		MOV8mi <fi#1>, 1, %noreg, 0, %noreg, 1; mem:ST1[%progress_in]
608B		%vreg193<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg193
624B		%vreg192<def> = MOV64rm %vreg193, 1, %noreg, 0, %noreg; mem:LD8[%strm6] GR64:%vreg192,%vreg193
640B		%vreg190<def> = MOV64rm %vreg192, 1, %noreg, 0, %noreg; mem:LD8[%next_in] GR64:%vreg190,%vreg192
656B		%vreg187<def> = MOVZX32rm8 %vreg190, 1, %noreg, 0, %noreg; mem:LD1[%11] GR32:%vreg187 GR64:%vreg190
672B		MOV32mr <fi#2>, 1, %noreg, 0, %noreg, %vreg187; mem:ST4[%zchh] GR32:%vreg187
688B		%vreg184<def> = MOV32rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD4[%zchh] GR32:%vreg184
704B		%vreg183<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg183
720B		CMP32rm %vreg184, %vreg183, 1, %noreg, 92, %noreg, %EFLAGS<imp-def>; mem:LD4[%state_in_ch] GR32:%vreg184 GR64:%vreg183
736B		JE_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#7

752B	BB#7: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#6
768B		%vreg196<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg196
784B		CMP32mi8 %vreg196, 1, %noreg, 96, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%state_in_len] GR64:%vreg196
800B		JNE_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#8

816B	BB#8: derived from LLVM BB %if.then.11
	    Predecessors according to CFG: BB#7
832B		%vreg281<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg281
848B		%vreg280<def> = MOV32rm %vreg281, 1, %noreg, 92, %noreg; mem:LD4[%state_in_ch12] GR32:%vreg280 GR64:%vreg281
880B		MOV8mr <fi#3>, 1, %noreg, 0, %noreg, %vreg280:sub_8bit; mem:ST1[%ch] GR32:%vreg280
896B		%vreg275<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg275
912B		%vreg256<def> = MOV32rm %vreg275, 1, %noreg, 648, %noreg; mem:LD4[%blockCRC] GR32:%vreg256 GR64:%vreg275
944B		%vreg256<def,tied1> = SHL32ri %vreg256<tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg256
960B		%vreg270<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg270
976B		%vreg263<def> = MOV32rm %vreg270, 1, %noreg, 648, %noreg; mem:LD4[%blockCRC14] GR32:%vreg263 GR64:%vreg270
1008B		%vreg263<def,tied1> = SHR32ri %vreg263<tied0>, 24, %EFLAGS<imp-def,dead>; GR32:%vreg263
1024B		%vreg265<def> = MOVZX32rm8 <fi#3>, 1, %noreg, 0, %noreg; mem:LD1[%ch] GR32:%vreg265
1056B		%vreg263<def,tied1> = XOR32rr %vreg263<tied0>, %vreg265, %EFLAGS<imp-def,dead>; GR32:%vreg263,%vreg265
1072B		%vreg260:sub_32bit<def,read-undef> = MOV32rr %vreg263; GR64_NOSP:%vreg260 GR32:%vreg263
1120B		%vreg256<def,tied1> = XOR32rm %vreg256<tied0>, %noreg, 4, %vreg260, <ga:@BZ2_crc32Table>, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%arrayidx] GR32:%vreg256 GR64_NOSP:%vreg260
1136B		%vreg253<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg253
1152B		MOV32mr %vreg253, 1, %noreg, 648, %noreg, %vreg256; mem:ST4[%blockCRC17] GR64:%vreg253 GR32:%vreg256
1168B		%vreg250<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg250
1184B		%vreg248:sub_32bit<def,read-undef> = MOV32rm %vreg250, 1, %noreg, 92, %noreg; mem:LD4[%state_in_ch18] GR64_NOSP:%vreg248 GR64:%vreg250
1216B		%vreg245<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg245
1232B		MOV8mi %vreg245, 1, %vreg248, 128, %noreg, 1; mem:ST1[%arrayidx20] GR64:%vreg245 GR64_NOSP:%vreg248
1248B		%vreg242<def> = MOV8rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD1[%ch] GR8:%vreg242
1264B		%vreg241<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg241
1280B		%vreg239<def> = MOVSX64rm32 %vreg241, 1, %noreg, 108, %noreg; mem:LD4[%nblock21] GR64_NOSP:%vreg239 GR64:%vreg241
1296B		%vreg237<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg237
1312B		%vreg236<def> = MOV64rm %vreg237, 1, %noreg, 64, %noreg; mem:LD8[%block] GR64:%vreg236,%vreg237
1328B		MOV8mr %vreg236, 1, %vreg239, 0, %noreg, %vreg242; mem:ST1[%arrayidx23] GR64:%vreg236 GR64_NOSP:%vreg239 GR8:%vreg242
1344B		%vreg231<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg231
1360B		%vreg229<def> = MOV32rm %vreg231, 1, %noreg, 108, %noreg; mem:LD4[%nblock24] GR32:%vreg229 GR64:%vreg231
1392B		%vreg229<def,tied1> = ADD32ri8 %vreg229<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg229
1408B		MOV32mr %vreg231, 1, %noreg, 108, %noreg, %vreg229; mem:ST4[%nblock24] GR64:%vreg231 GR32:%vreg229
1424B		%vreg225<def> = MOV32rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD4[%zchh] GR32:%vreg225
1440B		%vreg224<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg224
1456B		MOV32mr %vreg224, 1, %noreg, 92, %noreg, %vreg225; mem:ST4[%state_in_ch25] GR64:%vreg224 GR32:%vreg225
1472B		JMP_1 <BB#16>
	    Successors according to CFG: BB#16

1488B	BB#9: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#6 BB#7
1504B		%vreg201<def> = MOV32rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD4[%zchh] GR32:%vreg201
1520B		%vreg200<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg200
1536B		CMP32rm %vreg201, %vreg200, 1, %noreg, 92, %noreg, %EFLAGS<imp-def>; mem:LD4[%state_in_ch26] GR32:%vreg201 GR64:%vreg200
1552B		JNE_1 <BB#11>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#11 BB#10

1568B	BB#10: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#9
1584B		%vreg204<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg204
1600B		CMP32mi %vreg204, 1, %noreg, 96, %noreg, 255, %EFLAGS<imp-def>; mem:LD4[%state_in_len29] GR64:%vreg204
1616B		JNE_1 <BB#14>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#14 BB#11

1632B	BB#11: derived from LLVM BB %if.then.32
	    Predecessors according to CFG: BB#9 BB#10
1648B		%vreg213<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg213
1664B		CMP32mi %vreg213, 1, %noreg, 92, %noreg, 256, %EFLAGS<imp-def>; mem:LD4[%state_in_ch33] GR64:%vreg213
1680B		JAE_1 <BB#13>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#13 BB#12

1696B	BB#12: derived from LLVM BB %if.then.36
	    Predecessors according to CFG: BB#11
1712B		%vreg215<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg215
1728B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1744B		%RDI<def> = COPY %vreg215; GR64:%vreg215
1760B		CALL64pcrel32 <ga:@add_pair_to_block>, <regmask>, %RSP<imp-use>, %RDI<imp-use>
1776B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1792B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1808B		STACKMAP 1, 0, 0, <fi#3>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, ...; mem:LD8[FixedStack3](align=1) LD8[FixedStack1](align=1) LD8[FixedStack0] LD8[FixedStack2](align=4)
1824B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#13

1840B	BB#13: derived from LLVM BB %if.end.37
	    Predecessors according to CFG: BB#11 BB#12
1856B		%vreg221<def> = MOV32rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD4[%zchh] GR32:%vreg221
1872B		%vreg220<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg220
1888B		MOV32mr %vreg220, 1, %noreg, 92, %noreg, %vreg221; mem:ST4[%state_in_ch38] GR64:%vreg220 GR32:%vreg221
1904B		%vreg217<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg217
1920B		MOV32mi %vreg217, 1, %noreg, 96, %noreg, 1; mem:ST4[%state_in_len39] GR64:%vreg217
1936B		JMP_1 <BB#15>
	    Successors according to CFG: BB#15

1952B	BB#14: derived from LLVM BB %if.else.40
	    Predecessors according to CFG: BB#10
1968B		%vreg210<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg210
1984B		%vreg208<def> = MOV32rm %vreg210, 1, %noreg, 96, %noreg; mem:LD4[%state_in_len41] GR32:%vreg208 GR64:%vreg210
2016B		%vreg208<def,tied1> = ADD32ri8 %vreg208<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg208
2032B		MOV32mr %vreg210, 1, %noreg, 96, %noreg, %vreg208; mem:ST4[%state_in_len41] GR64:%vreg210 GR32:%vreg208
	    Successors according to CFG: BB#15

2048B	BB#15: derived from LLVM BB %if.end.43
	    Predecessors according to CFG: BB#14 BB#13
2064B		JMP_1 <BB#16>
	    Successors according to CFG: BB#16

2080B	BB#16: derived from LLVM BB %if.end.44
	    Predecessors according to CFG: BB#15 BB#8
2096B		%vreg310<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg310
2112B		%vreg309<def> = MOV64rm %vreg310, 1, %noreg, 0, %noreg; mem:LD8[%strm45] GR64:%vreg309,%vreg310
2128B		%vreg306<def> = MOV64rm %vreg309, 1, %noreg, 0, %noreg; mem:LD8[%next_in46] GR64:%vreg306,%vreg309
2160B		%vreg306<def,tied1> = ADD64ri8 %vreg306<tied0>, 1, %EFLAGS<imp-def,dead>; GR64:%vreg306
2176B		MOV64mr %vreg309, 1, %noreg, 0, %noreg, %vreg306; mem:ST8[%next_in46] GR64:%vreg309,%vreg306
2192B		%vreg302<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg302
2208B		%vreg301<def> = MOV64rm %vreg302, 1, %noreg, 0, %noreg; mem:LD8[%strm47] GR64:%vreg301,%vreg302
2224B		%vreg298<def> = MOV32rm %vreg301, 1, %noreg, 8, %noreg; mem:LD4[%avail_in48] GR32:%vreg298 GR64:%vreg301
2256B		%vreg298<def,tied1> = ADD32ri8 %vreg298<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg298
2272B		MOV32mr %vreg301, 1, %noreg, 8, %noreg, %vreg298; mem:ST4[%avail_in48] GR64:%vreg301 GR32:%vreg298
2288B		%vreg294<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg294
2304B		%vreg293<def> = MOV64rm %vreg294, 1, %noreg, 0, %noreg; mem:LD8[%strm49] GR64:%vreg293,%vreg294
2320B		%vreg290<def> = MOV32rm %vreg293, 1, %noreg, 12, %noreg; mem:LD4[%total_in_lo32] GR32:%vreg290 GR64:%vreg293
2352B		%vreg290<def,tied1> = ADD32ri8 %vreg290<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg290
2368B		MOV32mr %vreg293, 1, %noreg, 12, %noreg, %vreg290; mem:ST4[%total_in_lo32] GR64:%vreg293 GR32:%vreg290
2384B		%vreg286<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg286
2400B		%vreg285<def> = MOV64rm %vreg286, 1, %noreg, 0, %noreg; mem:LD8[%strm51] GR64:%vreg285,%vreg286
2416B		CMP32mi8 %vreg285, 1, %noreg, 12, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%total_in_lo3252] GR64:%vreg285
2432B		JNE_1 <BB#18>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#18 BB#17

2448B	BB#17: derived from LLVM BB %if.then.55
	    Predecessors according to CFG: BB#16
2464B		%vreg318<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg318
2480B		%vreg317<def> = MOV64rm %vreg318, 1, %noreg, 0, %noreg; mem:LD8[%strm56] GR64:%vreg317,%vreg318
2496B		%vreg314<def> = MOV32rm %vreg317, 1, %noreg, 16, %noreg; mem:LD4[%total_in_hi32] GR32:%vreg314 GR64:%vreg317
2528B		%vreg314<def,tied1> = ADD32ri8 %vreg314<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg314
2544B		MOV32mr %vreg317, 1, %noreg, 16, %noreg, %vreg314; mem:ST4[%total_in_hi32] GR64:%vreg317 GR32:%vreg314
	    Successors according to CFG: BB#18

2560B	BB#18: derived from LLVM BB %if.end.58
	    Predecessors according to CFG: BB#16 BB#17
2576B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2

2592B	BB#19: derived from LLVM BB %while.end
	    Predecessors according to CFG: BB#5 BB#3
2608B		JMP_1 <BB#41>
	    Successors according to CFG: BB#41

2624B	BB#20: derived from LLVM BB %if.else.59
	    Predecessors according to CFG: BB#0
2640B		JMP_1 <BB#21>
	    Successors according to CFG: BB#21

2656B	BB#21: derived from LLVM BB %while.body.60
	    Predecessors according to CFG: BB#20 BB#39
2672B		%vreg14<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg14
2688B		%vreg13<def> = MOV32rm %vreg14, 1, %noreg, 108, %noreg; mem:LD4[%nblock61] GR32:%vreg13 GR64:%vreg14
2704B		%vreg11<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg11
2720B		CMP32rm %vreg13, %vreg11, 1, %noreg, 112, %noreg, %EFLAGS<imp-def>; mem:LD4[%nblockMAX62] GR32:%vreg13 GR64:%vreg11
2736B		JL_1 <BB#23>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#23 BB#22

2752B	BB#22: derived from LLVM BB %if.then.65
	    Predecessors according to CFG: BB#21
2768B		JMP_1 <BB#40>
	    Successors according to CFG: BB#40

2784B	BB#23: derived from LLVM BB %if.end.66
	    Predecessors according to CFG: BB#21
2800B		%vreg19<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg19
2816B		%vreg18<def> = MOV64rm %vreg19, 1, %noreg, 0, %noreg; mem:LD8[%strm67] GR64:%vreg18,%vreg19
2832B		CMP32mi8 %vreg18, 1, %noreg, 8, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_in68] GR64:%vreg18
2848B		JNE_1 <BB#25>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#25 BB#24

2864B	BB#24: derived from LLVM BB %if.then.71
	    Predecessors according to CFG: BB#23
2880B		JMP_1 <BB#40>
	    Successors according to CFG: BB#40

2896B	BB#25: derived from LLVM BB %if.end.72
	    Predecessors according to CFG: BB#23
2912B		%vreg22<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg22
2928B		CMP32mi8 %vreg22, 1, %noreg, 16, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_in_expect] GR64:%vreg22
2944B		JNE_1 <BB#27>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#27 BB#26

2960B	BB#26: derived from LLVM BB %if.then.75
	    Predecessors according to CFG: BB#25
2976B		JMP_1 <BB#40>
	    Successors according to CFG: BB#40

2992B	BB#27: derived from LLVM BB %if.end.76
	    Predecessors according to CFG: BB#25
3008B		MOV8mi <fi#1>, 1, %noreg, 0, %noreg, 1; mem:ST1[%progress_in]
3024B		%vreg36<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg36
3040B		%vreg35<def> = MOV64rm %vreg36, 1, %noreg, 0, %noreg; mem:LD8[%strm78] GR64:%vreg35,%vreg36
3056B		%vreg33<def> = MOV64rm %vreg35, 1, %noreg, 0, %noreg; mem:LD8[%next_in79] GR64:%vreg33,%vreg35
3072B		%vreg30<def> = MOVZX32rm8 %vreg33, 1, %noreg, 0, %noreg; mem:LD1[%78] GR32:%vreg30 GR64:%vreg33
3088B		MOV32mr <fi#4>, 1, %noreg, 0, %noreg, %vreg30; mem:ST4[%zchh77] GR32:%vreg30
3104B		%vreg27<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%zchh77] GR32:%vreg27
3120B		%vreg26<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg26
3136B		CMP32rm %vreg27, %vreg26, 1, %noreg, 92, %noreg, %EFLAGS<imp-def>; mem:LD4[%state_in_ch81] GR32:%vreg27 GR64:%vreg26
3152B		JE_1 <BB#30>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#30 BB#28

3168B	BB#28: derived from LLVM BB %land.lhs.true.84
	    Predecessors according to CFG: BB#27
3184B		%vreg39<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg39
3200B		CMP32mi8 %vreg39, 1, %noreg, 96, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%state_in_len85] GR64:%vreg39
3216B		JNE_1 <BB#30>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#30 BB#29

3232B	BB#29: derived from LLVM BB %if.then.88
	    Predecessors according to CFG: BB#28
3248B		%vreg124<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg124
3264B		%vreg123<def> = MOV32rm %vreg124, 1, %noreg, 92, %noreg; mem:LD4[%state_in_ch90] GR32:%vreg123 GR64:%vreg124
3296B		MOV8mr <fi#5>, 1, %noreg, 0, %noreg, %vreg123:sub_8bit; mem:ST1[%ch89] GR32:%vreg123
3312B		%vreg118<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg118
3328B		%vreg99<def> = MOV32rm %vreg118, 1, %noreg, 648, %noreg; mem:LD4[%blockCRC92] GR32:%vreg99 GR64:%vreg118
3360B		%vreg99<def,tied1> = SHL32ri %vreg99<tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg99
3376B		%vreg113<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg113
3392B		%vreg106<def> = MOV32rm %vreg113, 1, %noreg, 648, %noreg; mem:LD4[%blockCRC94] GR32:%vreg106 GR64:%vreg113
3424B		%vreg106<def,tied1> = SHR32ri %vreg106<tied0>, 24, %EFLAGS<imp-def,dead>; GR32:%vreg106
3440B		%vreg108<def> = MOVZX32rm8 <fi#5>, 1, %noreg, 0, %noreg; mem:LD1[%ch89] GR32:%vreg108
3472B		%vreg106<def,tied1> = XOR32rr %vreg106<tied0>, %vreg108, %EFLAGS<imp-def,dead>; GR32:%vreg106,%vreg108
3488B		%vreg103:sub_32bit<def,read-undef> = MOV32rr %vreg106; GR64_NOSP:%vreg103 GR32:%vreg106
3536B		%vreg99<def,tied1> = XOR32rm %vreg99<tied0>, %noreg, 4, %vreg103, <ga:@BZ2_crc32Table>, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%arrayidx99] GR32:%vreg99 GR64_NOSP:%vreg103
3552B		%vreg96<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg96
3568B		MOV32mr %vreg96, 1, %noreg, 648, %noreg, %vreg99; mem:ST4[%blockCRC101] GR64:%vreg96 GR32:%vreg99
3584B		%vreg93<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg93
3600B		%vreg91:sub_32bit<def,read-undef> = MOV32rm %vreg93, 1, %noreg, 92, %noreg; mem:LD4[%state_in_ch102] GR64_NOSP:%vreg91 GR64:%vreg93
3632B		%vreg88<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg88
3648B		MOV8mi %vreg88, 1, %vreg91, 128, %noreg, 1; mem:ST1[%arrayidx105] GR64:%vreg88 GR64_NOSP:%vreg91
3664B		%vreg85<def> = MOV8rm <fi#5>, 1, %noreg, 0, %noreg; mem:LD1[%ch89] GR8:%vreg85
3680B		%vreg84<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg84
3696B		%vreg82<def> = MOVSX64rm32 %vreg84, 1, %noreg, 108, %noreg; mem:LD4[%nblock106] GR64_NOSP:%vreg82 GR64:%vreg84
3712B		%vreg80<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg80
3728B		%vreg79<def> = MOV64rm %vreg80, 1, %noreg, 64, %noreg; mem:LD8[%block108] GR64:%vreg79,%vreg80
3744B		MOV8mr %vreg79, 1, %vreg82, 0, %noreg, %vreg85; mem:ST1[%arrayidx109] GR64:%vreg79 GR64_NOSP:%vreg82 GR8:%vreg85
3760B		%vreg74<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg74
3776B		%vreg72<def> = MOV32rm %vreg74, 1, %noreg, 108, %noreg; mem:LD4[%nblock110] GR32:%vreg72 GR64:%vreg74
3808B		%vreg72<def,tied1> = ADD32ri8 %vreg72<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg72
3824B		MOV32mr %vreg74, 1, %noreg, 108, %noreg, %vreg72; mem:ST4[%nblock110] GR64:%vreg74 GR32:%vreg72
3840B		%vreg68<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%zchh77] GR32:%vreg68
3856B		%vreg67<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg67
3872B		MOV32mr %vreg67, 1, %noreg, 92, %noreg, %vreg68; mem:ST4[%state_in_ch112] GR64:%vreg67 GR32:%vreg68
3888B		JMP_1 <BB#37>
	    Successors according to CFG: BB#37

3904B	BB#30: derived from LLVM BB %if.else.113
	    Predecessors according to CFG: BB#27 BB#28
3920B		%vreg44<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%zchh77] GR32:%vreg44
3936B		%vreg43<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg43
3952B		CMP32rm %vreg44, %vreg43, 1, %noreg, 92, %noreg, %EFLAGS<imp-def>; mem:LD4[%state_in_ch114] GR32:%vreg44 GR64:%vreg43
3968B		JNE_1 <BB#32>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#32 BB#31

3984B	BB#31: derived from LLVM BB %lor.lhs.false.117
	    Predecessors according to CFG: BB#30
4000B		%vreg47<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg47
4016B		CMP32mi %vreg47, 1, %noreg, 96, %noreg, 255, %EFLAGS<imp-def>; mem:LD4[%state_in_len118] GR64:%vreg47
4032B		JNE_1 <BB#35>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#35 BB#32

4048B	BB#32: derived from LLVM BB %if.then.121
	    Predecessors according to CFG: BB#30 BB#31
4064B		%vreg56<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg56
4080B		CMP32mi %vreg56, 1, %noreg, 92, %noreg, 256, %EFLAGS<imp-def>; mem:LD4[%state_in_ch122] GR64:%vreg56
4096B		JAE_1 <BB#34>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#34 BB#33

4112B	BB#33: derived from LLVM BB %if.then.125
	    Predecessors according to CFG: BB#32
4128B		%vreg58<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg58
4144B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4160B		%RDI<def> = COPY %vreg58; GR64:%vreg58
4176B		CALL64pcrel32 <ga:@add_pair_to_block>, <regmask>, %RSP<imp-use>, %RDI<imp-use>
4192B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4208B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4224B		STACKMAP 2, 0, 0, <fi#5>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack5](align=1) LD8[FixedStack1](align=1) LD8[FixedStack0] LD8[FixedStack4](align=4)
4240B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#34

4256B	BB#34: derived from LLVM BB %if.end.126
	    Predecessors according to CFG: BB#32 BB#33
4272B		%vreg64<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%zchh77] GR32:%vreg64
4288B		%vreg63<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg63
4304B		MOV32mr %vreg63, 1, %noreg, 92, %noreg, %vreg64; mem:ST4[%state_in_ch127] GR64:%vreg63 GR32:%vreg64
4320B		%vreg60<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg60
4336B		MOV32mi %vreg60, 1, %noreg, 96, %noreg, 1; mem:ST4[%state_in_len128] GR64:%vreg60
4352B		JMP_1 <BB#36>
	    Successors according to CFG: BB#36

4368B	BB#35: derived from LLVM BB %if.else.129
	    Predecessors according to CFG: BB#31
4384B		%vreg53<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg53
4400B		%vreg51<def> = MOV32rm %vreg53, 1, %noreg, 96, %noreg; mem:LD4[%state_in_len130] GR32:%vreg51 GR64:%vreg53
4432B		%vreg51<def,tied1> = ADD32ri8 %vreg51<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg51
4448B		MOV32mr %vreg53, 1, %noreg, 96, %noreg, %vreg51; mem:ST4[%state_in_len130] GR64:%vreg53 GR32:%vreg51
	    Successors according to CFG: BB#36

4464B	BB#36: derived from LLVM BB %if.end.132
	    Predecessors according to CFG: BB#35 BB#34
4480B		JMP_1 <BB#37>
	    Successors according to CFG: BB#37

4496B	BB#37: derived from LLVM BB %if.end.133
	    Predecessors according to CFG: BB#36 BB#29
4512B		%vreg153<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg153
4528B		%vreg152<def> = MOV64rm %vreg153, 1, %noreg, 0, %noreg; mem:LD8[%strm134] GR64:%vreg152,%vreg153
4544B		%vreg149<def> = MOV64rm %vreg152, 1, %noreg, 0, %noreg; mem:LD8[%next_in135] GR64:%vreg149,%vreg152
4576B		%vreg149<def,tied1> = ADD64ri8 %vreg149<tied0>, 1, %EFLAGS<imp-def,dead>; GR64:%vreg149
4592B		MOV64mr %vreg152, 1, %noreg, 0, %noreg, %vreg149; mem:ST8[%next_in135] GR64:%vreg152,%vreg149
4608B		%vreg145<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg145
4624B		%vreg144<def> = MOV64rm %vreg145, 1, %noreg, 0, %noreg; mem:LD8[%strm137] GR64:%vreg144,%vreg145
4640B		%vreg141<def> = MOV32rm %vreg144, 1, %noreg, 8, %noreg; mem:LD4[%avail_in138] GR32:%vreg141 GR64:%vreg144
4672B		%vreg141<def,tied1> = ADD32ri8 %vreg141<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg141
4688B		MOV32mr %vreg144, 1, %noreg, 8, %noreg, %vreg141; mem:ST4[%avail_in138] GR64:%vreg144 GR32:%vreg141
4704B		%vreg137<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg137
4720B		%vreg136<def> = MOV64rm %vreg137, 1, %noreg, 0, %noreg; mem:LD8[%strm140] GR64:%vreg136,%vreg137
4736B		%vreg133<def> = MOV32rm %vreg136, 1, %noreg, 12, %noreg; mem:LD4[%total_in_lo32141] GR32:%vreg133 GR64:%vreg136
4768B		%vreg133<def,tied1> = ADD32ri8 %vreg133<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg133
4784B		MOV32mr %vreg136, 1, %noreg, 12, %noreg, %vreg133; mem:ST4[%total_in_lo32141] GR64:%vreg136 GR32:%vreg133
4800B		%vreg129<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg129
4816B		%vreg128<def> = MOV64rm %vreg129, 1, %noreg, 0, %noreg; mem:LD8[%strm143] GR64:%vreg128,%vreg129
4832B		CMP32mi8 %vreg128, 1, %noreg, 12, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%total_in_lo32144] GR64:%vreg128
4848B		JNE_1 <BB#39>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#39 BB#38

4864B	BB#38: derived from LLVM BB %if.then.147
	    Predecessors according to CFG: BB#37
4880B		%vreg161<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg161
4896B		%vreg160<def> = MOV64rm %vreg161, 1, %noreg, 0, %noreg; mem:LD8[%strm148] GR64:%vreg160,%vreg161
4912B		%vreg157<def> = MOV32rm %vreg160, 1, %noreg, 16, %noreg; mem:LD4[%total_in_hi32149] GR32:%vreg157 GR64:%vreg160
4944B		%vreg157<def,tied1> = ADD32ri8 %vreg157<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg157
4960B		MOV32mr %vreg160, 1, %noreg, 16, %noreg, %vreg157; mem:ST4[%total_in_hi32149] GR64:%vreg160 GR32:%vreg157
	    Successors according to CFG: BB#39

4976B	BB#39: derived from LLVM BB %if.end.151
	    Predecessors according to CFG: BB#37 BB#38
4992B		%vreg167<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg167
5008B		%vreg165<def> = MOV32rm %vreg167, 1, %noreg, 16, %noreg; mem:LD4[%avail_in_expect152] GR32:%vreg165 GR64:%vreg167
5040B		%vreg165<def,tied1> = ADD32ri8 %vreg165<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg165
5056B		MOV32mr %vreg167, 1, %noreg, 16, %noreg, %vreg165; mem:ST4[%avail_in_expect152] GR64:%vreg167 GR32:%vreg165
5072B		JMP_1 <BB#21>
	    Successors according to CFG: BB#21

5088B	BB#40: derived from LLVM BB %while.end.154
	    Predecessors according to CFG: BB#26 BB#24 BB#22
5104B		JMP_1 <BB#41>
	    Successors according to CFG: BB#41

5120B	BB#41: derived from LLVM BB %if.end.155
	    Predecessors according to CFG: BB#40 BB#19
5136B		%vreg321<def> = MOV64ri <ga:@copy_input_until_stop>; GR64:%vreg321
5168B		%vreg323<def> = MOV8rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD1[%progress_in] GR8:%vreg323
5184B		%vreg322<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg322
5200B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5216B		%RDI<def> = COPY %vreg321; GR64:%vreg321
5232B		%RSI<def> = COPY %vreg322; GR64:%vreg322
5248B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
5264B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5280B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5296B		STACKMAP 3, 0, %vreg323, ...; GR8:%vreg323
5312B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5328B		%AL<def> = COPY %vreg323; GR8:%vreg323
5344B		RETQ %AL<imp-use,kill>

# End machine code for function copy_input_until_stop.

AllocationOrder(SEGMENT_REG) = [ ]
AllocationOrder(SEGMENT_REG) = [ ]
AllocationOrder(SEGMENT_REG) = [ ]
AllocationOrder(SEGMENT_REG) = [ ]
AllocationOrder(SEGMENT_REG) = [ ]
AllocationOrder(SEGMENT_REG) = [ ]
********** GREEDY REGISTER ALLOCATION **********
********** Function: copy_input_until_stop
********** INTERVALS **********
DIL [0B,16r:0)[112r,144r:4)[1744r,1760r:2)[4160r,4176r:3)[5216r,5248r:1)  0@0B-phi 1@5216r 2@1744r 3@4160r 4@112r
%vreg1 [16r,224r:0)  0@16r
%vreg4 [256r,272r:0)  0@256r
%vreg6 [48r,112r:0)  0@48r
%vreg7 [80r,128r:0)  0@80r
%vreg11 [2704r,2720r:0)  0@2704r
%vreg13 [2688r,2720r:0)  0@2688r
%vreg14 [2672r,2688r:0)  0@2672r
%vreg18 [2816r,2832r:0)  0@2816r
%vreg19 [2800r,2816r:0)  0@2800r
%vreg22 [2912r,2928r:0)  0@2912r
%vreg26 [3120r,3136r:0)  0@3120r
%vreg27 [3104r,3136r:0)  0@3104r
%vreg30 [3072r,3088r:0)  0@3072r
%vreg33 [3056r,3072r:0)  0@3056r
%vreg35 [3040r,3056r:0)  0@3040r
%vreg36 [3024r,3040r:0)  0@3024r
%vreg39 [3184r,3200r:0)  0@3184r
%vreg43 [3936r,3952r:0)  0@3936r
%vreg44 [3920r,3952r:0)  0@3920r
%vreg47 [4000r,4016r:0)  0@4000r
%vreg51 [4400r,4432r:0)[4432r,4448r:1)  0@4400r 1@4432r
%vreg53 [4384r,4448r:0)  0@4384r
%vreg56 [4064r,4080r:0)  0@4064r
%vreg58 [4128r,4160r:0)  0@4128r
%vreg60 [4320r,4336r:0)  0@4320r
%vreg63 [4288r,4304r:0)  0@4288r
%vreg64 [4272r,4304r:0)  0@4272r
%vreg67 [3856r,3872r:0)  0@3856r
%vreg68 [3840r,3872r:0)  0@3840r
%vreg72 [3776r,3808r:0)[3808r,3824r:1)  0@3776r 1@3808r
%vreg74 [3760r,3824r:0)  0@3760r
%vreg79 [3728r,3744r:0)  0@3728r
%vreg80 [3712r,3728r:0)  0@3712r
%vreg82 [3696r,3744r:0)  0@3696r
%vreg84 [3680r,3696r:0)  0@3680r
%vreg85 [3664r,3744r:0)  0@3664r
%vreg88 [3632r,3648r:0)  0@3632r
%vreg91 [3600r,3648r:0)  0@3600r
%vreg93 [3584r,3600r:0)  0@3584r
%vreg96 [3552r,3568r:0)  0@3552r
%vreg99 [3328r,3360r:2)[3360r,3536r:0)[3536r,3568r:1)  0@3360r 1@3536r 2@3328r
%vreg103 [3488r,3536r:0)  0@3488r
%vreg106 [3392r,3424r:2)[3424r,3472r:0)[3472r,3488r:1)  0@3424r 1@3472r 2@3392r
%vreg108 [3440r,3472r:0)  0@3440r
%vreg113 [3376r,3392r:0)  0@3376r
%vreg118 [3312r,3328r:0)  0@3312r
%vreg123 [3264r,3296r:0)  0@3264r
%vreg124 [3248r,3264r:0)  0@3248r
%vreg128 [4816r,4832r:0)  0@4816r
%vreg129 [4800r,4816r:0)  0@4800r
%vreg133 [4736r,4768r:0)[4768r,4784r:1)  0@4736r 1@4768r
%vreg136 [4720r,4784r:0)  0@4720r
%vreg137 [4704r,4720r:0)  0@4704r
%vreg141 [4640r,4672r:0)[4672r,4688r:1)  0@4640r 1@4672r
%vreg144 [4624r,4688r:0)  0@4624r
%vreg145 [4608r,4624r:0)  0@4608r
%vreg149 [4544r,4576r:0)[4576r,4592r:1)  0@4544r 1@4576r
%vreg152 [4528r,4592r:0)  0@4528r
%vreg153 [4512r,4528r:0)  0@4512r
%vreg157 [4912r,4944r:0)[4944r,4960r:1)  0@4912r 1@4944r
%vreg160 [4896r,4960r:0)  0@4896r
%vreg161 [4880r,4896r:0)  0@4880r
%vreg165 [5008r,5040r:0)[5040r,5056r:1)  0@5008r 1@5040r
%vreg167 [4992r,5056r:0)  0@4992r
%vreg171 [384r,400r:0)  0@384r
%vreg173 [368r,400r:0)  0@368r
%vreg174 [352r,368r:0)  0@352r
%vreg178 [496r,512r:0)  0@496r
%vreg179 [480r,496r:0)  0@480r
%vreg183 [704r,720r:0)  0@704r
%vreg184 [688r,720r:0)  0@688r
%vreg187 [656r,672r:0)  0@656r
%vreg190 [640r,656r:0)  0@640r
%vreg192 [624r,640r:0)  0@624r
%vreg193 [608r,624r:0)  0@608r
%vreg196 [768r,784r:0)  0@768r
%vreg200 [1520r,1536r:0)  0@1520r
%vreg201 [1504r,1536r:0)  0@1504r
%vreg204 [1584r,1600r:0)  0@1584r
%vreg208 [1984r,2016r:0)[2016r,2032r:1)  0@1984r 1@2016r
%vreg210 [1968r,2032r:0)  0@1968r
%vreg213 [1648r,1664r:0)  0@1648r
%vreg215 [1712r,1744r:0)  0@1712r
%vreg217 [1904r,1920r:0)  0@1904r
%vreg220 [1872r,1888r:0)  0@1872r
%vreg221 [1856r,1888r:0)  0@1856r
%vreg224 [1440r,1456r:0)  0@1440r
%vreg225 [1424r,1456r:0)  0@1424r
%vreg229 [1360r,1392r:0)[1392r,1408r:1)  0@1360r 1@1392r
%vreg231 [1344r,1408r:0)  0@1344r
%vreg236 [1312r,1328r:0)  0@1312r
%vreg237 [1296r,1312r:0)  0@1296r
%vreg239 [1280r,1328r:0)  0@1280r
%vreg241 [1264r,1280r:0)  0@1264r
%vreg242 [1248r,1328r:0)  0@1248r
%vreg245 [1216r,1232r:0)  0@1216r
%vreg248 [1184r,1232r:0)  0@1184r
%vreg250 [1168r,1184r:0)  0@1168r
%vreg253 [1136r,1152r:0)  0@1136r
%vreg256 [912r,944r:2)[944r,1120r:0)[1120r,1152r:1)  0@944r 1@1120r 2@912r
%vreg260 [1072r,1120r:0)  0@1072r
%vreg263 [976r,1008r:2)[1008r,1056r:0)[1056r,1072r:1)  0@1008r 1@1056r 2@976r
%vreg265 [1024r,1056r:0)  0@1024r
%vreg270 [960r,976r:0)  0@960r
%vreg275 [896r,912r:0)  0@896r
%vreg280 [848r,880r:0)  0@848r
%vreg281 [832r,848r:0)  0@832r
%vreg285 [2400r,2416r:0)  0@2400r
%vreg286 [2384r,2400r:0)  0@2384r
%vreg290 [2320r,2352r:0)[2352r,2368r:1)  0@2320r 1@2352r
%vreg293 [2304r,2368r:0)  0@2304r
%vreg294 [2288r,2304r:0)  0@2288r
%vreg298 [2224r,2256r:0)[2256r,2272r:1)  0@2224r 1@2256r
%vreg301 [2208r,2272r:0)  0@2208r
%vreg302 [2192r,2208r:0)  0@2192r
%vreg306 [2128r,2160r:0)[2160r,2176r:1)  0@2128r 1@2160r
%vreg309 [2112r,2176r:0)  0@2112r
%vreg310 [2096r,2112r:0)  0@2096r
%vreg314 [2496r,2528r:0)[2528r,2544r:1)  0@2496r 1@2528r
%vreg317 [2480r,2544r:0)  0@2480r
%vreg318 [2464r,2480r:0)  0@2464r
%vreg321 [5136r,5216r:0)  0@5136r
%vreg322 [5184r,5232r:0)  0@5184r
%vreg323 [5168r,5328r:0)  0@5168r
RegMasks: 144r 1760r 4176r 5248r
********** MACHINEINSTRS **********
# Machine code for function copy_input_until_stop: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=8, align=8, at location [SP+8]
  fi#1: size=1, align=1, at location [SP+8]
  fi#2: size=4, align=4, at location [SP+8]
  fi#3: size=1, align=1, at location [SP+8]
  fi#4: size=4, align=4, at location [SP+8]
  fi#5: size=1, align=1, at location [SP+8]
Function Live Ins: %RDI in %vreg0

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI
16B		%vreg1<def> = COPY %RDI; GR64:%vreg1
48B		%vreg6<def> = MOV64ri <ga:@copy_input_until_stop>; GR64:%vreg6
80B		%vreg7<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg7
96B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
112B		%RDI<def> = COPY %vreg6; GR64:%vreg6
128B		%RSI<def> = COPY %vreg7; GR64:%vreg7
144B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
160B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
192B		STACKMAP 0, 0, 0, <fi#3>, 0, 0, <fi#5>, 0, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack3](align=1) LD8[FixedStack5](align=1) LD8[FixedStack1](align=1) LD8[FixedStack0] LD8[FixedStack2](align=4) LD8[FixedStack4](align=4) GR64:%vreg1
208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%s.addr] GR64:%vreg1
240B		MOV8mi <fi#1>, 1, %noreg, 0, %noreg, 0; mem:ST1[%progress_in]
256B		%vreg4<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg4
272B		CMP32mi8 %vreg4, 1, %noreg, 8, %noreg, 2, %EFLAGS<imp-def>; mem:LD4[%mode] GR64:%vreg4
288B		JNE_1 <BB#20>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#20 BB#1

304B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
320B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2

336B	BB#2: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#1 BB#18
352B		%vreg174<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg174
368B		%vreg173<def> = MOV32rm %vreg174, 1, %noreg, 108, %noreg; mem:LD4[%nblock] GR32:%vreg173 GR64:%vreg174
384B		%vreg171<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg171
400B		CMP32rm %vreg173, %vreg171, 1, %noreg, 112, %noreg, %EFLAGS<imp-def>; mem:LD4[%nblockMAX] GR32:%vreg173 GR64:%vreg171
416B		JL_1 <BB#4>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#4 BB#3

432B	BB#3: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#2
448B		JMP_1 <BB#19>
	    Successors according to CFG: BB#19

464B	BB#4: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#2
480B		%vreg179<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg179
496B		%vreg178<def> = MOV64rm %vreg179, 1, %noreg, 0, %noreg; mem:LD8[%strm] GR64:%vreg178,%vreg179
512B		CMP32mi8 %vreg178, 1, %noreg, 8, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_in] GR64:%vreg178
528B		JNE_1 <BB#6>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#6 BB#5

544B	BB#5: derived from LLVM BB %if.then.4
	    Predecessors according to CFG: BB#4
560B		JMP_1 <BB#19>
	    Successors according to CFG: BB#19

576B	BB#6: derived from LLVM BB %if.end.5
	    Predecessors according to CFG: BB#4
592B		MOV8mi <fi#1>, 1, %noreg, 0, %noreg, 1; mem:ST1[%progress_in]
608B		%vreg193<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg193
624B		%vreg192<def> = MOV64rm %vreg193, 1, %noreg, 0, %noreg; mem:LD8[%strm6] GR64:%vreg192,%vreg193
640B		%vreg190<def> = MOV64rm %vreg192, 1, %noreg, 0, %noreg; mem:LD8[%next_in] GR64:%vreg190,%vreg192
656B		%vreg187<def> = MOVZX32rm8 %vreg190, 1, %noreg, 0, %noreg; mem:LD1[%11] GR32:%vreg187 GR64:%vreg190
672B		MOV32mr <fi#2>, 1, %noreg, 0, %noreg, %vreg187; mem:ST4[%zchh] GR32:%vreg187
688B		%vreg184<def> = MOV32rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD4[%zchh] GR32:%vreg184
704B		%vreg183<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg183
720B		CMP32rm %vreg184, %vreg183, 1, %noreg, 92, %noreg, %EFLAGS<imp-def>; mem:LD4[%state_in_ch] GR32:%vreg184 GR64:%vreg183
736B		JE_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#7

752B	BB#7: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#6
768B		%vreg196<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg196
784B		CMP32mi8 %vreg196, 1, %noreg, 96, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%state_in_len] GR64:%vreg196
800B		JNE_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#8

816B	BB#8: derived from LLVM BB %if.then.11
	    Predecessors according to CFG: BB#7
832B		%vreg281<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg281
848B		%vreg280<def> = MOV32rm %vreg281, 1, %noreg, 92, %noreg; mem:LD4[%state_in_ch12] GR32:%vreg280 GR64:%vreg281
880B		MOV8mr <fi#3>, 1, %noreg, 0, %noreg, %vreg280:sub_8bit; mem:ST1[%ch] GR32:%vreg280
896B		%vreg275<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg275
912B		%vreg256<def> = MOV32rm %vreg275, 1, %noreg, 648, %noreg; mem:LD4[%blockCRC] GR32:%vreg256 GR64:%vreg275
944B		%vreg256<def,tied1> = SHL32ri %vreg256<tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg256
960B		%vreg270<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg270
976B		%vreg263<def> = MOV32rm %vreg270, 1, %noreg, 648, %noreg; mem:LD4[%blockCRC14] GR32:%vreg263 GR64:%vreg270
1008B		%vreg263<def,tied1> = SHR32ri %vreg263<tied0>, 24, %EFLAGS<imp-def,dead>; GR32:%vreg263
1024B		%vreg265<def> = MOVZX32rm8 <fi#3>, 1, %noreg, 0, %noreg; mem:LD1[%ch] GR32:%vreg265
1056B		%vreg263<def,tied1> = XOR32rr %vreg263<tied0>, %vreg265, %EFLAGS<imp-def,dead>; GR32:%vreg263,%vreg265
1072B		%vreg260:sub_32bit<def,read-undef> = MOV32rr %vreg263; GR64_NOSP:%vreg260 GR32:%vreg263
1120B		%vreg256<def,tied1> = XOR32rm %vreg256<tied0>, %noreg, 4, %vreg260, <ga:@BZ2_crc32Table>, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%arrayidx] GR32:%vreg256 GR64_NOSP:%vreg260
1136B		%vreg253<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg253
1152B		MOV32mr %vreg253, 1, %noreg, 648, %noreg, %vreg256; mem:ST4[%blockCRC17] GR64:%vreg253 GR32:%vreg256
1168B		%vreg250<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg250
1184B		%vreg248:sub_32bit<def,read-undef> = MOV32rm %vreg250, 1, %noreg, 92, %noreg; mem:LD4[%state_in_ch18] GR64_NOSP:%vreg248 GR64:%vreg250
1216B		%vreg245<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg245
1232B		MOV8mi %vreg245, 1, %vreg248, 128, %noreg, 1; mem:ST1[%arrayidx20] GR64:%vreg245 GR64_NOSP:%vreg248
1248B		%vreg242<def> = MOV8rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD1[%ch] GR8:%vreg242
1264B		%vreg241<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg241
1280B		%vreg239<def> = MOVSX64rm32 %vreg241, 1, %noreg, 108, %noreg; mem:LD4[%nblock21] GR64_NOSP:%vreg239 GR64:%vreg241
1296B		%vreg237<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg237
1312B		%vreg236<def> = MOV64rm %vreg237, 1, %noreg, 64, %noreg; mem:LD8[%block] GR64:%vreg236,%vreg237
1328B		MOV8mr %vreg236, 1, %vreg239, 0, %noreg, %vreg242; mem:ST1[%arrayidx23] GR64:%vreg236 GR64_NOSP:%vreg239 GR8:%vreg242
1344B		%vreg231<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg231
1360B		%vreg229<def> = MOV32rm %vreg231, 1, %noreg, 108, %noreg; mem:LD4[%nblock24] GR32:%vreg229 GR64:%vreg231
1392B		%vreg229<def,tied1> = ADD32ri8 %vreg229<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg229
1408B		MOV32mr %vreg231, 1, %noreg, 108, %noreg, %vreg229; mem:ST4[%nblock24] GR64:%vreg231 GR32:%vreg229
1424B		%vreg225<def> = MOV32rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD4[%zchh] GR32:%vreg225
1440B		%vreg224<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg224
1456B		MOV32mr %vreg224, 1, %noreg, 92, %noreg, %vreg225; mem:ST4[%state_in_ch25] GR64:%vreg224 GR32:%vreg225
1472B		JMP_1 <BB#16>
	    Successors according to CFG: BB#16

1488B	BB#9: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#6 BB#7
1504B		%vreg201<def> = MOV32rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD4[%zchh] GR32:%vreg201
1520B		%vreg200<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg200
1536B		CMP32rm %vreg201, %vreg200, 1, %noreg, 92, %noreg, %EFLAGS<imp-def>; mem:LD4[%state_in_ch26] GR32:%vreg201 GR64:%vreg200
1552B		JNE_1 <BB#11>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#11 BB#10

1568B	BB#10: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#9
1584B		%vreg204<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg204
1600B		CMP32mi %vreg204, 1, %noreg, 96, %noreg, 255, %EFLAGS<imp-def>; mem:LD4[%state_in_len29] GR64:%vreg204
1616B		JNE_1 <BB#14>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#14 BB#11

1632B	BB#11: derived from LLVM BB %if.then.32
	    Predecessors according to CFG: BB#9 BB#10
1648B		%vreg213<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg213
1664B		CMP32mi %vreg213, 1, %noreg, 92, %noreg, 256, %EFLAGS<imp-def>; mem:LD4[%state_in_ch33] GR64:%vreg213
1680B		JAE_1 <BB#13>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#13 BB#12

1696B	BB#12: derived from LLVM BB %if.then.36
	    Predecessors according to CFG: BB#11
1712B		%vreg215<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg215
1728B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1744B		%RDI<def> = COPY %vreg215; GR64:%vreg215
1760B		CALL64pcrel32 <ga:@add_pair_to_block>, <regmask>, %RSP<imp-use>, %RDI<imp-use>
1776B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1792B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1808B		STACKMAP 1, 0, 0, <fi#3>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, ...; mem:LD8[FixedStack3](align=1) LD8[FixedStack1](align=1) LD8[FixedStack0] LD8[FixedStack2](align=4)
1824B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#13

1840B	BB#13: derived from LLVM BB %if.end.37
	    Predecessors according to CFG: BB#11 BB#12
1856B		%vreg221<def> = MOV32rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD4[%zchh] GR32:%vreg221
1872B		%vreg220<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg220
1888B		MOV32mr %vreg220, 1, %noreg, 92, %noreg, %vreg221; mem:ST4[%state_in_ch38] GR64:%vreg220 GR32:%vreg221
1904B		%vreg217<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg217
1920B		MOV32mi %vreg217, 1, %noreg, 96, %noreg, 1; mem:ST4[%state_in_len39] GR64:%vreg217
1936B		JMP_1 <BB#15>
	    Successors according to CFG: BB#15

1952B	BB#14: derived from LLVM BB %if.else.40
	    Predecessors according to CFG: BB#10
1968B		%vreg210<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg210
1984B		%vreg208<def> = MOV32rm %vreg210, 1, %noreg, 96, %noreg; mem:LD4[%state_in_len41] GR32:%vreg208 GR64:%vreg210
2016B		%vreg208<def,tied1> = ADD32ri8 %vreg208<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg208
2032B		MOV32mr %vreg210, 1, %noreg, 96, %noreg, %vreg208; mem:ST4[%state_in_len41] GR64:%vreg210 GR32:%vreg208
	    Successors according to CFG: BB#15

2048B	BB#15: derived from LLVM BB %if.end.43
	    Predecessors according to CFG: BB#14 BB#13
2064B		JMP_1 <BB#16>
	    Successors according to CFG: BB#16

2080B	BB#16: derived from LLVM BB %if.end.44
	    Predecessors according to CFG: BB#15 BB#8
2096B		%vreg310<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg310
2112B		%vreg309<def> = MOV64rm %vreg310, 1, %noreg, 0, %noreg; mem:LD8[%strm45] GR64:%vreg309,%vreg310
2128B		%vreg306<def> = MOV64rm %vreg309, 1, %noreg, 0, %noreg; mem:LD8[%next_in46] GR64:%vreg306,%vreg309
2160B		%vreg306<def,tied1> = ADD64ri8 %vreg306<tied0>, 1, %EFLAGS<imp-def,dead>; GR64:%vreg306
2176B		MOV64mr %vreg309, 1, %noreg, 0, %noreg, %vreg306; mem:ST8[%next_in46] GR64:%vreg309,%vreg306
2192B		%vreg302<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg302
2208B		%vreg301<def> = MOV64rm %vreg302, 1, %noreg, 0, %noreg; mem:LD8[%strm47] GR64:%vreg301,%vreg302
2224B		%vreg298<def> = MOV32rm %vreg301, 1, %noreg, 8, %noreg; mem:LD4[%avail_in48] GR32:%vreg298 GR64:%vreg301
2256B		%vreg298<def,tied1> = ADD32ri8 %vreg298<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg298
2272B		MOV32mr %vreg301, 1, %noreg, 8, %noreg, %vreg298; mem:ST4[%avail_in48] GR64:%vreg301 GR32:%vreg298
2288B		%vreg294<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg294
2304B		%vreg293<def> = MOV64rm %vreg294, 1, %noreg, 0, %noreg; mem:LD8[%strm49] GR64:%vreg293,%vreg294
2320B		%vreg290<def> = MOV32rm %vreg293, 1, %noreg, 12, %noreg; mem:LD4[%total_in_lo32] GR32:%vreg290 GR64:%vreg293
2352B		%vreg290<def,tied1> = ADD32ri8 %vreg290<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg290
2368B		MOV32mr %vreg293, 1, %noreg, 12, %noreg, %vreg290; mem:ST4[%total_in_lo32] GR64:%vreg293 GR32:%vreg290
2384B		%vreg286<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg286
2400B		%vreg285<def> = MOV64rm %vreg286, 1, %noreg, 0, %noreg; mem:LD8[%strm51] GR64:%vreg285,%vreg286
2416B		CMP32mi8 %vreg285, 1, %noreg, 12, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%total_in_lo3252] GR64:%vreg285
2432B		JNE_1 <BB#18>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#18 BB#17

2448B	BB#17: derived from LLVM BB %if.then.55
	    Predecessors according to CFG: BB#16
2464B		%vreg318<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg318
2480B		%vreg317<def> = MOV64rm %vreg318, 1, %noreg, 0, %noreg; mem:LD8[%strm56] GR64:%vreg317,%vreg318
2496B		%vreg314<def> = MOV32rm %vreg317, 1, %noreg, 16, %noreg; mem:LD4[%total_in_hi32] GR32:%vreg314 GR64:%vreg317
2528B		%vreg314<def,tied1> = ADD32ri8 %vreg314<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg314
2544B		MOV32mr %vreg317, 1, %noreg, 16, %noreg, %vreg314; mem:ST4[%total_in_hi32] GR64:%vreg317 GR32:%vreg314
	    Successors according to CFG: BB#18

2560B	BB#18: derived from LLVM BB %if.end.58
	    Predecessors according to CFG: BB#16 BB#17
2576B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2

2592B	BB#19: derived from LLVM BB %while.end
	    Predecessors according to CFG: BB#5 BB#3
2608B		JMP_1 <BB#41>
	    Successors according to CFG: BB#41

2624B	BB#20: derived from LLVM BB %if.else.59
	    Predecessors according to CFG: BB#0
2640B		JMP_1 <BB#21>
	    Successors according to CFG: BB#21

2656B	BB#21: derived from LLVM BB %while.body.60
	    Predecessors according to CFG: BB#20 BB#39
2672B		%vreg14<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg14
2688B		%vreg13<def> = MOV32rm %vreg14, 1, %noreg, 108, %noreg; mem:LD4[%nblock61] GR32:%vreg13 GR64:%vreg14
2704B		%vreg11<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg11
2720B		CMP32rm %vreg13, %vreg11, 1, %noreg, 112, %noreg, %EFLAGS<imp-def>; mem:LD4[%nblockMAX62] GR32:%vreg13 GR64:%vreg11
2736B		JL_1 <BB#23>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#23 BB#22

2752B	BB#22: derived from LLVM BB %if.then.65
	    Predecessors according to CFG: BB#21
2768B		JMP_1 <BB#40>
	    Successors according to CFG: BB#40

2784B	BB#23: derived from LLVM BB %if.end.66
	    Predecessors according to CFG: BB#21
2800B		%vreg19<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg19
2816B		%vreg18<def> = MOV64rm %vreg19, 1, %noreg, 0, %noreg; mem:LD8[%strm67] GR64:%vreg18,%vreg19
2832B		CMP32mi8 %vreg18, 1, %noreg, 8, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_in68] GR64:%vreg18
2848B		JNE_1 <BB#25>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#25 BB#24

2864B	BB#24: derived from LLVM BB %if.then.71
	    Predecessors according to CFG: BB#23
2880B		JMP_1 <BB#40>
	    Successors according to CFG: BB#40

2896B	BB#25: derived from LLVM BB %if.end.72
	    Predecessors according to CFG: BB#23
2912B		%vreg22<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg22
2928B		CMP32mi8 %vreg22, 1, %noreg, 16, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_in_expect] GR64:%vreg22
2944B		JNE_1 <BB#27>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#27 BB#26

2960B	BB#26: derived from LLVM BB %if.then.75
	    Predecessors according to CFG: BB#25
2976B		JMP_1 <BB#40>
	    Successors according to CFG: BB#40

2992B	BB#27: derived from LLVM BB %if.end.76
	    Predecessors according to CFG: BB#25
3008B		MOV8mi <fi#1>, 1, %noreg, 0, %noreg, 1; mem:ST1[%progress_in]
3024B		%vreg36<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg36
3040B		%vreg35<def> = MOV64rm %vreg36, 1, %noreg, 0, %noreg; mem:LD8[%strm78] GR64:%vreg35,%vreg36
3056B		%vreg33<def> = MOV64rm %vreg35, 1, %noreg, 0, %noreg; mem:LD8[%next_in79] GR64:%vreg33,%vreg35
3072B		%vreg30<def> = MOVZX32rm8 %vreg33, 1, %noreg, 0, %noreg; mem:LD1[%78] GR32:%vreg30 GR64:%vreg33
3088B		MOV32mr <fi#4>, 1, %noreg, 0, %noreg, %vreg30; mem:ST4[%zchh77] GR32:%vreg30
3104B		%vreg27<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%zchh77] GR32:%vreg27
3120B		%vreg26<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg26
3136B		CMP32rm %vreg27, %vreg26, 1, %noreg, 92, %noreg, %EFLAGS<imp-def>; mem:LD4[%state_in_ch81] GR32:%vreg27 GR64:%vreg26
3152B		JE_1 <BB#30>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#30 BB#28

3168B	BB#28: derived from LLVM BB %land.lhs.true.84
	    Predecessors according to CFG: BB#27
3184B		%vreg39<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg39
3200B		CMP32mi8 %vreg39, 1, %noreg, 96, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%state_in_len85] GR64:%vreg39
3216B		JNE_1 <BB#30>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#30 BB#29

3232B	BB#29: derived from LLVM BB %if.then.88
	    Predecessors according to CFG: BB#28
3248B		%vreg124<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg124
3264B		%vreg123<def> = MOV32rm %vreg124, 1, %noreg, 92, %noreg; mem:LD4[%state_in_ch90] GR32:%vreg123 GR64:%vreg124
3296B		MOV8mr <fi#5>, 1, %noreg, 0, %noreg, %vreg123:sub_8bit; mem:ST1[%ch89] GR32:%vreg123
3312B		%vreg118<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg118
3328B		%vreg99<def> = MOV32rm %vreg118, 1, %noreg, 648, %noreg; mem:LD4[%blockCRC92] GR32:%vreg99 GR64:%vreg118
3360B		%vreg99<def,tied1> = SHL32ri %vreg99<tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg99
3376B		%vreg113<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg113
3392B		%vreg106<def> = MOV32rm %vreg113, 1, %noreg, 648, %noreg; mem:LD4[%blockCRC94] GR32:%vreg106 GR64:%vreg113
3424B		%vreg106<def,tied1> = SHR32ri %vreg106<tied0>, 24, %EFLAGS<imp-def,dead>; GR32:%vreg106
3440B		%vreg108<def> = MOVZX32rm8 <fi#5>, 1, %noreg, 0, %noreg; mem:LD1[%ch89] GR32:%vreg108
3472B		%vreg106<def,tied1> = XOR32rr %vreg106<tied0>, %vreg108, %EFLAGS<imp-def,dead>; GR32:%vreg106,%vreg108
3488B		%vreg103:sub_32bit<def,read-undef> = MOV32rr %vreg106; GR64_NOSP:%vreg103 GR32:%vreg106
3536B		%vreg99<def,tied1> = XOR32rm %vreg99<tied0>, %noreg, 4, %vreg103, <ga:@BZ2_crc32Table>, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%arrayidx99] GR32:%vreg99 GR64_NOSP:%vreg103
3552B		%vreg96<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg96
3568B		MOV32mr %vreg96, 1, %noreg, 648, %noreg, %vreg99; mem:ST4[%blockCRC101] GR64:%vreg96 GR32:%vreg99
3584B		%vreg93<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg93
3600B		%vreg91:sub_32bit<def,read-undef> = MOV32rm %vreg93, 1, %noreg, 92, %noreg; mem:LD4[%state_in_ch102] GR64_NOSP:%vreg91 GR64:%vreg93
3632B		%vreg88<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg88
3648B		MOV8mi %vreg88, 1, %vreg91, 128, %noreg, 1; mem:ST1[%arrayidx105] GR64:%vreg88 GR64_NOSP:%vreg91
3664B		%vreg85<def> = MOV8rm <fi#5>, 1, %noreg, 0, %noreg; mem:LD1[%ch89] GR8:%vreg85
3680B		%vreg84<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg84
3696B		%vreg82<def> = MOVSX64rm32 %vreg84, 1, %noreg, 108, %noreg; mem:LD4[%nblock106] GR64_NOSP:%vreg82 GR64:%vreg84
3712B		%vreg80<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg80
3728B		%vreg79<def> = MOV64rm %vreg80, 1, %noreg, 64, %noreg; mem:LD8[%block108] GR64:%vreg79,%vreg80
3744B		MOV8mr %vreg79, 1, %vreg82, 0, %noreg, %vreg85; mem:ST1[%arrayidx109] GR64:%vreg79 GR64_NOSP:%vreg82 GR8:%vreg85
3760B		%vreg74<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg74
3776B		%vreg72<def> = MOV32rm %vreg74, 1, %noreg, 108, %noreg; mem:LD4[%nblock110] GR32:%vreg72 GR64:%vreg74
3808B		%vreg72<def,tied1> = ADD32ri8 %vreg72<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg72
3824B		MOV32mr %vreg74, 1, %noreg, 108, %noreg, %vreg72; mem:ST4[%nblock110] GR64:%vreg74 GR32:%vreg72
3840B		%vreg68<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%zchh77] GR32:%vreg68
3856B		%vreg67<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg67
3872B		MOV32mr %vreg67, 1, %noreg, 92, %noreg, %vreg68; mem:ST4[%state_in_ch112] GR64:%vreg67 GR32:%vreg68
3888B		JMP_1 <BB#37>
	    Successors according to CFG: BB#37

3904B	BB#30: derived from LLVM BB %if.else.113
	    Predecessors according to CFG: BB#27 BB#28
3920B		%vreg44<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%zchh77] GR32:%vreg44
3936B		%vreg43<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg43
3952B		CMP32rm %vreg44, %vreg43, 1, %noreg, 92, %noreg, %EFLAGS<imp-def>; mem:LD4[%state_in_ch114] GR32:%vreg44 GR64:%vreg43
3968B		JNE_1 <BB#32>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#32 BB#31

3984B	BB#31: derived from LLVM BB %lor.lhs.false.117
	    Predecessors according to CFG: BB#30
4000B		%vreg47<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg47
4016B		CMP32mi %vreg47, 1, %noreg, 96, %noreg, 255, %EFLAGS<imp-def>; mem:LD4[%state_in_len118] GR64:%vreg47
4032B		JNE_1 <BB#35>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#35 BB#32

4048B	BB#32: derived from LLVM BB %if.then.121
	    Predecessors according to CFG: BB#30 BB#31
4064B		%vreg56<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg56
4080B		CMP32mi %vreg56, 1, %noreg, 92, %noreg, 256, %EFLAGS<imp-def>; mem:LD4[%state_in_ch122] GR64:%vreg56
4096B		JAE_1 <BB#34>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#34 BB#33

4112B	BB#33: derived from LLVM BB %if.then.125
	    Predecessors according to CFG: BB#32
4128B		%vreg58<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg58
4144B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4160B		%RDI<def> = COPY %vreg58; GR64:%vreg58
4176B		CALL64pcrel32 <ga:@add_pair_to_block>, <regmask>, %RSP<imp-use>, %RDI<imp-use>
4192B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4208B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4224B		STACKMAP 2, 0, 0, <fi#5>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack5](align=1) LD8[FixedStack1](align=1) LD8[FixedStack0] LD8[FixedStack4](align=4)
4240B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#34

4256B	BB#34: derived from LLVM BB %if.end.126
	    Predecessors according to CFG: BB#32 BB#33
4272B		%vreg64<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%zchh77] GR32:%vreg64
4288B		%vreg63<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg63
4304B		MOV32mr %vreg63, 1, %noreg, 92, %noreg, %vreg64; mem:ST4[%state_in_ch127] GR64:%vreg63 GR32:%vreg64
4320B		%vreg60<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg60
4336B		MOV32mi %vreg60, 1, %noreg, 96, %noreg, 1; mem:ST4[%state_in_len128] GR64:%vreg60
4352B		JMP_1 <BB#36>
	    Successors according to CFG: BB#36

4368B	BB#35: derived from LLVM BB %if.else.129
	    Predecessors according to CFG: BB#31
4384B		%vreg53<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg53
4400B		%vreg51<def> = MOV32rm %vreg53, 1, %noreg, 96, %noreg; mem:LD4[%state_in_len130] GR32:%vreg51 GR64:%vreg53
4432B		%vreg51<def,tied1> = ADD32ri8 %vreg51<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg51
4448B		MOV32mr %vreg53, 1, %noreg, 96, %noreg, %vreg51; mem:ST4[%state_in_len130] GR64:%vreg53 GR32:%vreg51
	    Successors according to CFG: BB#36

4464B	BB#36: derived from LLVM BB %if.end.132
	    Predecessors according to CFG: BB#35 BB#34
4480B		JMP_1 <BB#37>
	    Successors according to CFG: BB#37

4496B	BB#37: derived from LLVM BB %if.end.133
	    Predecessors according to CFG: BB#36 BB#29
4512B		%vreg153<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg153
4528B		%vreg152<def> = MOV64rm %vreg153, 1, %noreg, 0, %noreg; mem:LD8[%strm134] GR64:%vreg152,%vreg153
4544B		%vreg149<def> = MOV64rm %vreg152, 1, %noreg, 0, %noreg; mem:LD8[%next_in135] GR64:%vreg149,%vreg152
4576B		%vreg149<def,tied1> = ADD64ri8 %vreg149<tied0>, 1, %EFLAGS<imp-def,dead>; GR64:%vreg149
4592B		MOV64mr %vreg152, 1, %noreg, 0, %noreg, %vreg149; mem:ST8[%next_in135] GR64:%vreg152,%vreg149
4608B		%vreg145<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg145
4624B		%vreg144<def> = MOV64rm %vreg145, 1, %noreg, 0, %noreg; mem:LD8[%strm137] GR64:%vreg144,%vreg145
4640B		%vreg141<def> = MOV32rm %vreg144, 1, %noreg, 8, %noreg; mem:LD4[%avail_in138] GR32:%vreg141 GR64:%vreg144
4672B		%vreg141<def,tied1> = ADD32ri8 %vreg141<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg141
4688B		MOV32mr %vreg144, 1, %noreg, 8, %noreg, %vreg141; mem:ST4[%avail_in138] GR64:%vreg144 GR32:%vreg141
4704B		%vreg137<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg137
4720B		%vreg136<def> = MOV64rm %vreg137, 1, %noreg, 0, %noreg; mem:LD8[%strm140] GR64:%vreg136,%vreg137
4736B		%vreg133<def> = MOV32rm %vreg136, 1, %noreg, 12, %noreg; mem:LD4[%total_in_lo32141] GR32:%vreg133 GR64:%vreg136
4768B		%vreg133<def,tied1> = ADD32ri8 %vreg133<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg133
4784B		MOV32mr %vreg136, 1, %noreg, 12, %noreg, %vreg133; mem:ST4[%total_in_lo32141] GR64:%vreg136 GR32:%vreg133
4800B		%vreg129<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg129
4816B		%vreg128<def> = MOV64rm %vreg129, 1, %noreg, 0, %noreg; mem:LD8[%strm143] GR64:%vreg128,%vreg129
4832B		CMP32mi8 %vreg128, 1, %noreg, 12, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%total_in_lo32144] GR64:%vreg128
4848B		JNE_1 <BB#39>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#39 BB#38

4864B	BB#38: derived from LLVM BB %if.then.147
	    Predecessors according to CFG: BB#37
4880B		%vreg161<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg161
4896B		%vreg160<def> = MOV64rm %vreg161, 1, %noreg, 0, %noreg; mem:LD8[%strm148] GR64:%vreg160,%vreg161
4912B		%vreg157<def> = MOV32rm %vreg160, 1, %noreg, 16, %noreg; mem:LD4[%total_in_hi32149] GR32:%vreg157 GR64:%vreg160
4944B		%vreg157<def,tied1> = ADD32ri8 %vreg157<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg157
4960B		MOV32mr %vreg160, 1, %noreg, 16, %noreg, %vreg157; mem:ST4[%total_in_hi32149] GR64:%vreg160 GR32:%vreg157
	    Successors according to CFG: BB#39

4976B	BB#39: derived from LLVM BB %if.end.151
	    Predecessors according to CFG: BB#37 BB#38
4992B		%vreg167<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg167
5008B		%vreg165<def> = MOV32rm %vreg167, 1, %noreg, 16, %noreg; mem:LD4[%avail_in_expect152] GR32:%vreg165 GR64:%vreg167
5040B		%vreg165<def,tied1> = ADD32ri8 %vreg165<tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg165
5056B		MOV32mr %vreg167, 1, %noreg, 16, %noreg, %vreg165; mem:ST4[%avail_in_expect152] GR64:%vreg167 GR32:%vreg165
5072B		JMP_1 <BB#21>
	    Successors according to CFG: BB#21

5088B	BB#40: derived from LLVM BB %while.end.154
	    Predecessors according to CFG: BB#26 BB#24 BB#22
5104B		JMP_1 <BB#41>
	    Successors according to CFG: BB#41

5120B	BB#41: derived from LLVM BB %if.end.155
	    Predecessors according to CFG: BB#40 BB#19
5136B		%vreg321<def> = MOV64ri <ga:@copy_input_until_stop>; GR64:%vreg321
5168B		%vreg323<def> = MOV8rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD1[%progress_in] GR8:%vreg323
5184B		%vreg322<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg322
5200B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5216B		%RDI<def> = COPY %vreg321; GR64:%vreg321
5232B		%RSI<def> = COPY %vreg322; GR64:%vreg322
5248B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
5264B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5280B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5296B		STACKMAP 3, 0, %vreg323, ...; GR8:%vreg323
5312B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5328B		%AL<def> = COPY %vreg323; GR8:%vreg323
5344B		RETQ %AL<imp-use,kill>

# End machine code for function copy_input_until_stop.


selectOrSplit GR64:%vreg1 [16r,224r:0)  0@16r w=4.983553e-03
hints: %RDI
missed hint %RDI
assigning %vreg1 to %RBX: BH [16r,224r:0)  0@16r BL [16r,224r:0)  0@16r

selectOrSplit GR64:%vreg6 [48r,112r:0)  0@48r w=2.176724e-03
hints: %RDI
assigning %vreg6 to %RDI: DIL [48r,112r:0)  0@48r

selectOrSplit GR64:%vreg7 [80r,128r:0)  0@80r w=4.508928e-03
hints: %RSI
assigning %vreg7 to %RSI: SIL [80r,128r:0)  0@80r

selectOrSplit GR64:%vreg215 [1712r,1744r:0)  0@1712r w=2.114740e-04
hints: %RDI
assigning %vreg215 to %RDI: DIL [1712r,1744r:0)  0@1712r

selectOrSplit GR64:%vreg58 [4128r,4160r:0)  0@4128r w=8.615609e-05
hints: %RDI
assigning %vreg58 to %RDI: DIL [4128r,4160r:0)  0@4128r

selectOrSplit GR64:%vreg321 [5136r,5216r:0)  0@5136r w=2.104167e-03
hints: %RDI
assigning %vreg321 to %RDI: DIL [5136r,5216r:0)  0@5136r

selectOrSplit GR8:%vreg323 [5168r,5328r:0)  0@5168r w=5.410714e-03
hints: %AL
missed hint %AL
assigning %vreg323 to %BL: BL [5168r,5328r:0)  0@5168r

selectOrSplit GR64:%vreg322 [5184r,5232r:0)  0@5184r w=4.508928e-03
hints: %RSI
assigning %vreg322 to %RSI: SIL [5184r,5232r:0)  0@5184r

selectOrSplit GR64:%vreg4 [256r,272r:0)  0@256r w=inf
assigning %vreg4 to %RAX: AH [256r,272r:0)  0@256r AL [256r,272r:0)  0@256r

selectOrSplit GR64:%vreg174 [352r,368r:0)  0@352r w=inf
assigning %vreg174 to %RAX: AH [352r,368r:0)  0@352r AL [352r,368r:0)  0@352r

selectOrSplit GR32:%vreg173 [368r,400r:0)  0@368r w=3.086420e-03
assigning %vreg173 to %EAX: AH [368r,400r:0)  0@368r AL [368r,400r:0)  0@368r

selectOrSplit GR64:%vreg171 [384r,400r:0)  0@384r w=inf
assigning %vreg171 to %RCX: CH [384r,400r:0)  0@384r CL [384r,400r:0)  0@384r

selectOrSplit GR64:%vreg179 [480r,496r:0)  0@480r w=inf
assigning %vreg179 to %RAX: AH [480r,496r:0)  0@480r AL [480r,496r:0)  0@480r

selectOrSplit GR64:%vreg178 [496r,512r:0)  0@496r w=inf
assigning %vreg178 to %RAX: AH [496r,512r:0)  0@496r AL [496r,512r:0)  0@496r

selectOrSplit GR64:%vreg193 [608r,624r:0)  0@608r w=inf
assigning %vreg193 to %RAX: AH [608r,624r:0)  0@608r AL [608r,624r:0)  0@608r

selectOrSplit GR64:%vreg192 [624r,640r:0)  0@624r w=inf
assigning %vreg192 to %RAX: AH [624r,640r:0)  0@624r AL [624r,640r:0)  0@624r

selectOrSplit GR64:%vreg190 [640r,656r:0)  0@640r w=inf
assigning %vreg190 to %RAX: AH [640r,656r:0)  0@640r AL [640r,656r:0)  0@640r

selectOrSplit GR32:%vreg187 [656r,672r:0)  0@656r w=inf
assigning %vreg187 to %EAX: AH [656r,672r:0)  0@656r AL [656r,672r:0)  0@656r

selectOrSplit GR32:%vreg184 [688r,720r:0)  0@688r w=7.677275e-04
assigning %vreg184 to %EAX: AH [688r,720r:0)  0@688r AL [688r,720r:0)  0@688r

selectOrSplit GR64:%vreg183 [704r,720r:0)  0@704r w=inf
assigning %vreg183 to %RCX: CH [704r,720r:0)  0@704r CL [704r,720r:0)  0@704r

selectOrSplit GR64:%vreg196 [768r,784r:0)  0@768r w=inf
assigning %vreg196 to %RAX: AH [768r,784r:0)  0@768r AL [768r,784r:0)  0@768r

selectOrSplit GR64:%vreg281 [832r,848r:0)  0@832r w=inf
assigning %vreg281 to %RAX: AH [832r,848r:0)  0@832r AL [832r,848r:0)  0@832r

selectOrSplit GR32:%vreg280 [848r,880r:0)  0@848r w=inf
assigning %vreg280 to %EAX: AH [848r,880r:0)  0@848r AL [848r,880r:0)  0@848r

selectOrSplit GR64:%vreg275 [896r,912r:0)  0@896r w=inf
assigning %vreg275 to %RAX: AH [896r,912r:0)  0@896r AL [896r,912r:0)  0@896r

selectOrSplit GR32:%vreg256 [912r,944r:2)[944r,1120r:0)[1120r,1152r:1)  0@944r 1@1120r 2@912r w=3.768844e-04
assigning %vreg256 to %EAX: AH [912r,944r:2)[944r,1120r:0)[1120r,1152r:1)  0@944r 1@1120r 2@912r AL [912r,944r:2)[944r,1120r:0)[1120r,1152r:1)  0@944r 1@1120r 2@912r

selectOrSplit GR64:%vreg270 [960r,976r:0)  0@960r w=inf
assigning %vreg270 to %RCX: CH [960r,976r:0)  0@960r CL [960r,976r:0)  0@960r

selectOrSplit GR32:%vreg263 [976r,1008r:2)[1008r,1056r:0)[1056r,1072r:1)  0@1008r 1@1056r 2@976r w=4.863025e-04
assigning %vreg263 to %ECX: CH [976r,1008r:2)[1008r,1056r:0)[1056r,1072r:1)  0@1008r 1@1056r 2@976r CL [976r,1008r:2)[1008r,1056r:0)[1056r,1072r:1)  0@1008r 1@1056r 2@976r

selectOrSplit GR32:%vreg265 [1024r,1056r:0)  0@1024r w=inf
assigning %vreg265 to %EDX: DH [1024r,1056r:0)  0@1024r DL [1024r,1056r:0)  0@1024r

selectOrSplit GR64_NOSP:%vreg260 [1072r,1120r:0)  0@1072r w=inf
assigning %vreg260 to %RCX: CH [1072r,1120r:0)  0@1072r CL [1072r,1120r:0)  0@1072r

selectOrSplit GR64:%vreg253 [1136r,1152r:0)  0@1136r w=inf
assigning %vreg253 to %RCX: CH [1136r,1152r:0)  0@1136r CL [1136r,1152r:0)  0@1136r

selectOrSplit GR64:%vreg250 [1168r,1184r:0)  0@1168r w=inf
assigning %vreg250 to %RAX: AH [1168r,1184r:0)  0@1168r AL [1168r,1184r:0)  0@1168r

selectOrSplit GR64_NOSP:%vreg248 [1184r,1232r:0)  0@1184r w=1.794688e-04
assigning %vreg248 to %RAX: AH [1184r,1232r:0)  0@1184r AL [1184r,1232r:0)  0@1184r

selectOrSplit GR64:%vreg245 [1216r,1232r:0)  0@1216r w=inf
assigning %vreg245 to %RCX: CH [1216r,1232r:0)  0@1216r CL [1216r,1232r:0)  0@1216r

selectOrSplit GR8:%vreg242 [1248r,1328r:0)  0@1248r w=1.675042e-04
assigning %vreg242 to %AL: AL [1248r,1328r:0)  0@1248r

selectOrSplit GR64:%vreg241 [1264r,1280r:0)  0@1264r w=inf
assigning %vreg241 to %RCX: CH [1264r,1280r:0)  0@1264r CL [1264r,1280r:0)  0@1264r

selectOrSplit GR64_NOSP:%vreg239 [1280r,1328r:0)  0@1280r w=1.794688e-04
assigning %vreg239 to %RCX: CH [1280r,1328r:0)  0@1280r CL [1280r,1328r:0)  0@1280r

selectOrSplit GR64:%vreg237 [1296r,1312r:0)  0@1296r w=inf
assigning %vreg237 to %RDX: DH [1296r,1312r:0)  0@1296r DL [1296r,1312r:0)  0@1296r

selectOrSplit GR64:%vreg236 [1312r,1328r:0)  0@1312r w=inf
assigning %vreg236 to %RDX: DH [1312r,1328r:0)  0@1312r DL [1312r,1328r:0)  0@1312r

selectOrSplit GR64:%vreg231 [1344r,1408r:0)  0@1344r w=2.599203e-04
assigning %vreg231 to %RAX: AH [1344r,1408r:0)  0@1344r AL [1344r,1408r:0)  0@1344r

selectOrSplit GR32:%vreg229 [1360r,1392r:0)[1392r,1408r:1)  0@1360r 1@1392r w=inf
assigning %vreg229 to %ECX: CH [1360r,1392r:0)[1392r,1408r:1)  0@1360r 1@1392r CL [1360r,1392r:0)[1392r,1408r:1)  0@1360r 1@1392r

selectOrSplit GR32:%vreg225 [1424r,1456r:0)  0@1424r w=1.861158e-04
assigning %vreg225 to %EAX: AH [1424r,1456r:0)  0@1424r AL [1424r,1456r:0)  0@1424r

selectOrSplit GR64:%vreg224 [1440r,1456r:0)  0@1440r w=inf
assigning %vreg224 to %RCX: CH [1440r,1456r:0)  0@1440r CL [1440r,1456r:0)  0@1440r

selectOrSplit GR32:%vreg201 [1504r,1536r:0)  0@1504r w=5.738569e-04
assigning %vreg201 to %EAX: AH [1504r,1536r:0)  0@1504r AL [1504r,1536r:0)  0@1504r

selectOrSplit GR64:%vreg200 [1520r,1536r:0)  0@1520r w=inf
assigning %vreg200 to %RCX: CH [1520r,1536r:0)  0@1520r CL [1520r,1536r:0)  0@1520r

selectOrSplit GR64:%vreg204 [1584r,1600r:0)  0@1584r w=inf
assigning %vreg204 to %RAX: AH [1584r,1600r:0)  0@1584r AL [1584r,1600r:0)  0@1584r

selectOrSplit GR64:%vreg213 [1648r,1664r:0)  0@1648r w=inf
assigning %vreg213 to %RAX: AH [1648r,1664r:0)  0@1648r AL [1648r,1664r:0)  0@1648r

selectOrSplit GR32:%vreg221 [1856r,1888r:0)  0@1856r w=4.265153e-04
assigning %vreg221 to %EAX: AH [1856r,1888r:0)  0@1856r AL [1856r,1888r:0)  0@1856r

selectOrSplit GR64:%vreg220 [1872r,1888r:0)  0@1872r w=inf
assigning %vreg220 to %RCX: CH [1872r,1888r:0)  0@1872r CL [1872r,1888r:0)  0@1872r

selectOrSplit GR64:%vreg217 [1904r,1920r:0)  0@1904r w=inf
assigning %vreg217 to %RAX: AH [1904r,1920r:0)  0@1904r AL [1904r,1920r:0)  0@1904r

selectOrSplit GR64:%vreg210 [1968r,2032r:0)  0@1968r w=1.949402e-04
assigning %vreg210 to %RAX: AH [1968r,2032r:0)  0@1968r AL [1968r,2032r:0)  0@1968r

selectOrSplit GR32:%vreg208 [1984r,2016r:0)[2016r,2032r:1)  0@1984r 1@2016r w=inf
assigning %vreg208 to %ECX: CH [1984r,2016r:0)[2016r,2032r:1)  0@1984r 1@2016r CL [1984r,2016r:0)[2016r,2032r:1)  0@1984r 1@2016r

selectOrSplit GR64:%vreg310 [2096r,2112r:0)  0@2096r w=inf
assigning %vreg310 to %RAX: AH [2096r,2112r:0)  0@2096r AL [2096r,2112r:0)  0@2096r

selectOrSplit GR64:%vreg309 [2112r,2176r:0)  0@2112r w=1.072171e-03
assigning %vreg309 to %RAX: AH [2112r,2176r:0)  0@2112r AL [2112r,2176r:0)  0@2112r

selectOrSplit GR64:%vreg306 [2128r,2160r:0)[2160r,2176r:1)  0@2128r 1@2160r w=inf
assigning %vreg306 to %RCX: CH [2128r,2160r:0)[2160r,2176r:1)  0@2128r 1@2160r CL [2128r,2160r:0)[2160r,2176r:1)  0@2128r 1@2160r

selectOrSplit GR64:%vreg302 [2192r,2208r:0)  0@2192r w=inf
assigning %vreg302 to %RAX: AH [2192r,2208r:0)  0@2192r AL [2192r,2208r:0)  0@2192r

selectOrSplit GR64:%vreg301 [2208r,2272r:0)  0@2208r w=1.072171e-03
assigning %vreg301 to %RAX: AH [2208r,2272r:0)  0@2208r AL [2208r,2272r:0)  0@2208r

selectOrSplit GR32:%vreg298 [2224r,2256r:0)[2256r,2272r:1)  0@2224r 1@2256r w=inf
assigning %vreg298 to %ECX: CH [2224r,2256r:0)[2256r,2272r:1)  0@2224r 1@2256r CL [2224r,2256r:0)[2256r,2272r:1)  0@2224r 1@2256r

selectOrSplit GR64:%vreg294 [2288r,2304r:0)  0@2288r w=inf
assigning %vreg294 to %RAX: AH [2288r,2304r:0)  0@2288r AL [2288r,2304r:0)  0@2288r

selectOrSplit GR64:%vreg293 [2304r,2368r:0)  0@2304r w=1.072171e-03
assigning %vreg293 to %RAX: AH [2304r,2368r:0)  0@2304r AL [2304r,2368r:0)  0@2304r

selectOrSplit GR32:%vreg290 [2320r,2352r:0)[2352r,2368r:1)  0@2320r 1@2352r w=inf
assigning %vreg290 to %ECX: CH [2320r,2352r:0)[2352r,2368r:1)  0@2320r 1@2352r CL [2320r,2352r:0)[2352r,2368r:1)  0@2320r 1@2352r

selectOrSplit GR64:%vreg286 [2384r,2400r:0)  0@2384r w=inf
assigning %vreg286 to %RAX: AH [2384r,2400r:0)  0@2384r AL [2384r,2400r:0)  0@2384r

selectOrSplit GR64:%vreg285 [2400r,2416r:0)  0@2400r w=inf
assigning %vreg285 to %RAX: AH [2400r,2416r:0)  0@2400r AL [2400r,2416r:0)  0@2400r

selectOrSplit GR64:%vreg318 [2464r,2480r:0)  0@2464r w=inf
assigning %vreg318 to %RAX: AH [2464r,2480r:0)  0@2464r AL [2464r,2480r:0)  0@2464r

selectOrSplit GR64:%vreg317 [2480r,2544r:0)  0@2480r w=5.306706e-04
assigning %vreg317 to %RAX: AH [2480r,2544r:0)  0@2480r AL [2480r,2544r:0)  0@2480r

selectOrSplit GR32:%vreg314 [2496r,2528r:0)[2528r,2544r:1)  0@2496r 1@2528r w=inf
assigning %vreg314 to %ECX: CH [2496r,2528r:0)[2528r,2544r:1)  0@2496r 1@2528r CL [2496r,2528r:0)[2528r,2544r:1)  0@2496r 1@2528r

selectOrSplit GR64:%vreg14 [2672r,2688r:0)  0@2672r w=inf
assigning %vreg14 to %RAX: AH [2672r,2688r:0)  0@2672r AL [2672r,2688r:0)  0@2672r

selectOrSplit GR32:%vreg13 [2688r,2720r:0)  0@2688r w=2.644395e-03
assigning %vreg13 to %EAX: AH [2688r,2720r:0)  0@2688r AL [2688r,2720r:0)  0@2688r

selectOrSplit GR64:%vreg11 [2704r,2720r:0)  0@2704r w=inf
assigning %vreg11 to %RCX: CH [2704r,2720r:0)  0@2704r CL [2704r,2720r:0)  0@2704r

selectOrSplit GR64:%vreg19 [2800r,2816r:0)  0@2800r w=inf
assigning %vreg19 to %RAX: AH [2800r,2816r:0)  0@2800r AL [2800r,2816r:0)  0@2800r

selectOrSplit GR64:%vreg18 [2816r,2832r:0)  0@2816r w=inf
assigning %vreg18 to %RAX: AH [2816r,2832r:0)  0@2816r AL [2816r,2832r:0)  0@2816r

selectOrSplit GR64:%vreg22 [2912r,2928r:0)  0@2912r w=inf
assigning %vreg22 to %RAX: AH [2912r,2928r:0)  0@2912r AL [2912r,2928r:0)  0@2912r

selectOrSplit GR64:%vreg36 [3024r,3040r:0)  0@3024r w=inf
assigning %vreg36 to %RAX: AH [3024r,3040r:0)  0@3024r AL [3024r,3040r:0)  0@3024r

selectOrSplit GR64:%vreg35 [3040r,3056r:0)  0@3040r w=inf
assigning %vreg35 to %RAX: AH [3040r,3056r:0)  0@3040r AL [3040r,3056r:0)  0@3040r

selectOrSplit GR64:%vreg33 [3056r,3072r:0)  0@3056r w=inf
assigning %vreg33 to %RAX: AH [3056r,3072r:0)  0@3056r AL [3056r,3072r:0)  0@3056r

selectOrSplit GR32:%vreg30 [3072r,3088r:0)  0@3072r w=inf
assigning %vreg30 to %EAX: AH [3072r,3088r:0)  0@3072r AL [3072r,3088r:0)  0@3072r

selectOrSplit GR32:%vreg27 [3104r,3136r:0)  0@3104r w=3.257026e-04
assigning %vreg27 to %EAX: AH [3104r,3136r:0)  0@3104r AL [3104r,3136r:0)  0@3104r

selectOrSplit GR64:%vreg26 [3120r,3136r:0)  0@3120r w=inf
assigning %vreg26 to %RCX: CH [3120r,3136r:0)  0@3120r CL [3120r,3136r:0)  0@3120r

selectOrSplit GR64:%vreg39 [3184r,3200r:0)  0@3184r w=inf
assigning %vreg39 to %RAX: AH [3184r,3200r:0)  0@3184r AL [3184r,3200r:0)  0@3184r

selectOrSplit GR64:%vreg124 [3248r,3264r:0)  0@3248r w=inf
assigning %vreg124 to %RAX: AH [3248r,3264r:0)  0@3248r AL [3248r,3264r:0)  0@3248r

selectOrSplit GR32:%vreg123 [3264r,3296r:0)  0@3264r w=inf
assigning %vreg123 to %EAX: AH [3264r,3296r:0)  0@3264r AL [3264r,3296r:0)  0@3264r

selectOrSplit GR64:%vreg118 [3312r,3328r:0)  0@3312r w=inf
assigning %vreg118 to %RAX: AH [3312r,3328r:0)  0@3312r AL [3312r,3328r:0)  0@3312r

selectOrSplit GR32:%vreg99 [3328r,3360r:2)[3360r,3536r:0)[3536r,3568r:1)  0@3360r 1@3536r 2@3328r w=1.570352e-04
assigning %vreg99 to %EAX: AH [3328r,3360r:2)[3360r,3536r:0)[3536r,3568r:1)  0@3360r 1@3536r 2@3328r AL [3328r,3360r:2)[3360r,3536r:0)[3536r,3568r:1)  0@3360r 1@3536r 2@3328r

selectOrSplit GR64:%vreg113 [3376r,3392r:0)  0@3376r w=inf
assigning %vreg113 to %RCX: CH [3376r,3392r:0)  0@3376r CL [3376r,3392r:0)  0@3376r

selectOrSplit GR32:%vreg106 [3392r,3424r:2)[3424r,3472r:0)[3472r,3488r:1)  0@3424r 1@3472r 2@3392r w=2.026260e-04
assigning %vreg106 to %ECX: CH [3392r,3424r:2)[3424r,3472r:0)[3472r,3488r:1)  0@3424r 1@3472r 2@3392r CL [3392r,3424r:2)[3424r,3472r:0)[3472r,3488r:1)  0@3424r 1@3472r 2@3392r

selectOrSplit GR32:%vreg108 [3440r,3472r:0)  0@3440r w=inf
assigning %vreg108 to %EDX: DH [3440r,3472r:0)  0@3440r DL [3440r,3472r:0)  0@3440r

selectOrSplit GR64_NOSP:%vreg103 [3488r,3536r:0)  0@3488r w=inf
assigning %vreg103 to %RCX: CH [3488r,3536r:0)  0@3488r CL [3488r,3536r:0)  0@3488r

selectOrSplit GR64:%vreg96 [3552r,3568r:0)  0@3552r w=inf
assigning %vreg96 to %RCX: CH [3552r,3568r:0)  0@3552r CL [3552r,3568r:0)  0@3552r

selectOrSplit GR64:%vreg93 [3584r,3600r:0)  0@3584r w=inf
assigning %vreg93 to %RAX: AH [3584r,3600r:0)  0@3584r AL [3584r,3600r:0)  0@3584r

selectOrSplit GR64_NOSP:%vreg91 [3600r,3648r:0)  0@3600r w=7.477865e-05
assigning %vreg91 to %RAX: AH [3600r,3648r:0)  0@3600r AL [3600r,3648r:0)  0@3600r

selectOrSplit GR64:%vreg88 [3632r,3648r:0)  0@3632r w=inf
assigning %vreg88 to %RCX: CH [3632r,3648r:0)  0@3632r CL [3632r,3648r:0)  0@3632r

selectOrSplit GR8:%vreg85 [3664r,3744r:0)  0@3664r w=6.979341e-05
assigning %vreg85 to %AL: AL [3664r,3744r:0)  0@3664r

selectOrSplit GR64:%vreg84 [3680r,3696r:0)  0@3680r w=inf
assigning %vreg84 to %RCX: CH [3680r,3696r:0)  0@3680r CL [3680r,3696r:0)  0@3680r

selectOrSplit GR64_NOSP:%vreg82 [3696r,3744r:0)  0@3696r w=7.477865e-05
assigning %vreg82 to %RCX: CH [3696r,3744r:0)  0@3696r CL [3696r,3744r:0)  0@3696r

selectOrSplit GR64:%vreg80 [3712r,3728r:0)  0@3712r w=inf
assigning %vreg80 to %RDX: DH [3712r,3728r:0)  0@3712r DL [3712r,3728r:0)  0@3712r

selectOrSplit GR64:%vreg79 [3728r,3744r:0)  0@3728r w=inf
assigning %vreg79 to %RDX: DH [3728r,3744r:0)  0@3728r DL [3728r,3744r:0)  0@3728r

selectOrSplit GR64:%vreg74 [3760r,3824r:0)  0@3760r w=1.083001e-04
assigning %vreg74 to %RAX: AH [3760r,3824r:0)  0@3760r AL [3760r,3824r:0)  0@3760r

selectOrSplit GR32:%vreg72 [3776r,3808r:0)[3808r,3824r:1)  0@3776r 1@3808r w=inf
assigning %vreg72 to %ECX: CH [3776r,3808r:0)[3808r,3824r:1)  0@3776r 1@3808r CL [3776r,3808r:0)[3808r,3824r:1)  0@3776r 1@3808r

selectOrSplit GR32:%vreg68 [3840r,3872r:0)  0@3840r w=7.754823e-05
assigning %vreg68 to %EAX: AH [3840r,3872r:0)  0@3840r AL [3840r,3872r:0)  0@3840r

selectOrSplit GR64:%vreg67 [3856r,3872r:0)  0@3856r w=inf
assigning %vreg67 to %RCX: CH [3856r,3872r:0)  0@3856r CL [3856r,3872r:0)  0@3856r

selectOrSplit GR32:%vreg44 [3920r,3952r:0)  0@3920r w=2.403995e-04
assigning %vreg44 to %EAX: AH [3920r,3952r:0)  0@3920r AL [3920r,3952r:0)  0@3920r

selectOrSplit GR64:%vreg43 [3936r,3952r:0)  0@3936r w=inf
assigning %vreg43 to %RCX: CH [3936r,3952r:0)  0@3936r CL [3936r,3952r:0)  0@3936r

selectOrSplit GR64:%vreg47 [4000r,4016r:0)  0@4000r w=inf
assigning %vreg47 to %RAX: AH [4000r,4016r:0)  0@4000r AL [4000r,4016r:0)  0@4000r

selectOrSplit GR64:%vreg56 [4064r,4080r:0)  0@4064r w=inf
assigning %vreg56 to %RAX: AH [4064r,4080r:0)  0@4064r AL [4064r,4080r:0)  0@4064r

selectOrSplit GR32:%vreg64 [4272r,4304r:0)  0@4272r w=1.783609e-04
assigning %vreg64 to %EAX: AH [4272r,4304r:0)  0@4272r AL [4272r,4304r:0)  0@4272r

selectOrSplit GR64:%vreg63 [4288r,4304r:0)  0@4288r w=inf
assigning %vreg63 to %RCX: CH [4288r,4304r:0)  0@4288r CL [4288r,4304r:0)  0@4288r

selectOrSplit GR64:%vreg60 [4320r,4336r:0)  0@4320r w=inf
assigning %vreg60 to %RAX: AH [4320r,4336r:0)  0@4320r AL [4320r,4336r:0)  0@4320r

selectOrSplit GR64:%vreg53 [4384r,4448r:0)  0@4384r w=8.664010e-05
assigning %vreg53 to %RAX: AH [4384r,4448r:0)  0@4384r AL [4384r,4448r:0)  0@4384r

selectOrSplit GR32:%vreg51 [4400r,4432r:0)[4432r,4448r:1)  0@4400r 1@4432r w=inf
assigning %vreg51 to %ECX: CH [4400r,4432r:0)[4432r,4448r:1)  0@4400r 1@4432r CL [4400r,4432r:0)[4432r,4448r:1)  0@4400r 1@4432r

selectOrSplit GR64:%vreg153 [4512r,4528r:0)  0@4512r w=inf
assigning %vreg153 to %RAX: AH [4512r,4528r:0)  0@4512r AL [4512r,4528r:0)  0@4512r

selectOrSplit GR64:%vreg152 [4528r,4592r:0)  0@4528r w=4.548605e-04
assigning %vreg152 to %RAX: AH [4528r,4592r:0)  0@4528r AL [4528r,4592r:0)  0@4528r

selectOrSplit GR64:%vreg149 [4544r,4576r:0)[4576r,4592r:1)  0@4544r 1@4576r w=inf
assigning %vreg149 to %RCX: CH [4544r,4576r:0)[4576r,4592r:1)  0@4544r 1@4576r CL [4544r,4576r:0)[4576r,4592r:1)  0@4544r 1@4576r

selectOrSplit GR64:%vreg145 [4608r,4624r:0)  0@4608r w=inf
assigning %vreg145 to %RAX: AH [4608r,4624r:0)  0@4608r AL [4608r,4624r:0)  0@4608r

selectOrSplit GR64:%vreg144 [4624r,4688r:0)  0@4624r w=4.548605e-04
assigning %vreg144 to %RAX: AH [4624r,4688r:0)  0@4624r AL [4624r,4688r:0)  0@4624r

selectOrSplit GR32:%vreg141 [4640r,4672r:0)[4672r,4688r:1)  0@4640r 1@4672r w=inf
assigning %vreg141 to %ECX: CH [4640r,4672r:0)[4672r,4688r:1)  0@4640r 1@4672r CL [4640r,4672r:0)[4672r,4688r:1)  0@4640r 1@4672r

selectOrSplit GR64:%vreg137 [4704r,4720r:0)  0@4704r w=inf
assigning %vreg137 to %RAX: AH [4704r,4720r:0)  0@4704r AL [4704r,4720r:0)  0@4704r

selectOrSplit GR64:%vreg136 [4720r,4784r:0)  0@4720r w=4.548605e-04
assigning %vreg136 to %RAX: AH [4720r,4784r:0)  0@4720r AL [4720r,4784r:0)  0@4720r

selectOrSplit GR32:%vreg133 [4736r,4768r:0)[4768r,4784r:1)  0@4736r 1@4768r w=inf
assigning %vreg133 to %ECX: CH [4736r,4768r:0)[4768r,4784r:1)  0@4736r 1@4768r CL [4736r,4768r:0)[4768r,4784r:1)  0@4736r 1@4768r

selectOrSplit GR64:%vreg129 [4800r,4816r:0)  0@4800r w=inf
assigning %vreg129 to %RAX: AH [4800r,4816r:0)  0@4800r AL [4800r,4816r:0)  0@4800r

selectOrSplit GR64:%vreg128 [4816r,4832r:0)  0@4816r w=inf
assigning %vreg128 to %RAX: AH [4816r,4832r:0)  0@4816r AL [4816r,4832r:0)  0@4816r

selectOrSplit GR64:%vreg161 [4880r,4896r:0)  0@4880r w=inf
assigning %vreg161 to %RAX: AH [4880r,4896r:0)  0@4880r AL [4880r,4896r:0)  0@4880r

selectOrSplit GR64:%vreg160 [4896r,4960r:0)  0@4896r w=2.274303e-04
assigning %vreg160 to %RAX: AH [4896r,4960r:0)  0@4896r AL [4896r,4960r:0)  0@4896r

selectOrSplit GR32:%vreg157 [4912r,4944r:0)[4944r,4960r:1)  0@4912r 1@4944r w=inf
assigning %vreg157 to %ECX: CH [4912r,4944r:0)[4944r,4960r:1)  0@4912r 1@4944r CL [4912r,4944r:0)[4944r,4960r:1)  0@4912r 1@4944r

selectOrSplit GR64:%vreg167 [4992r,5056r:0)  0@4992r w=4.548605e-04
assigning %vreg167 to %RAX: AH [4992r,5056r:0)  0@4992r AL [4992r,5056r:0)  0@4992r

selectOrSplit GR32:%vreg165 [5008r,5040r:0)[5040r,5056r:1)  0@5008r 1@5040r w=inf
assigning %vreg165 to %ECX: CH [5008r,5040r:0)[5040r,5056r:1)  0@5008r 1@5040r CL [5008r,5040r:0)[5040r,5056r:1)  0@5008r 1@5040r

********** STACK TRANSFORMATION METADATA **********
********** Function: copy_input_until_stop
********** REGISTER MAP **********
[%vreg1 -> %RBX] GR64
[%vreg4 -> %RAX] GR64
[%vreg6 -> %RDI] GR64
[%vreg7 -> %RSI] GR64
[%vreg11 -> %RCX] GR64
[%vreg13 -> %EAX] GR32
[%vreg14 -> %RAX] GR64
[%vreg18 -> %RAX] GR64
[%vreg19 -> %RAX] GR64
[%vreg22 -> %RAX] GR64
[%vreg26 -> %RCX] GR64
[%vreg27 -> %EAX] GR32
[%vreg30 -> %EAX] GR32
[%vreg33 -> %RAX] GR64
[%vreg35 -> %RAX] GR64
[%vreg36 -> %RAX] GR64
[%vreg39 -> %RAX] GR64
[%vreg43 -> %RCX] GR64
[%vreg44 -> %EAX] GR32
[%vreg47 -> %RAX] GR64
[%vreg51 -> %ECX] GR32
[%vreg53 -> %RAX] GR64
[%vreg56 -> %RAX] GR64
[%vreg58 -> %RDI] GR64
[%vreg60 -> %RAX] GR64
[%vreg63 -> %RCX] GR64
[%vreg64 -> %EAX] GR32
[%vreg67 -> %RCX] GR64
[%vreg68 -> %EAX] GR32
[%vreg72 -> %ECX] GR32
[%vreg74 -> %RAX] GR64
[%vreg79 -> %RDX] GR64
[%vreg80 -> %RDX] GR64
[%vreg82 -> %RCX] GR64_NOSP
[%vreg84 -> %RCX] GR64
[%vreg85 -> %AL] GR8
[%vreg88 -> %RCX] GR64
[%vreg91 -> %RAX] GR64_NOSP
[%vreg93 -> %RAX] GR64
[%vreg96 -> %RCX] GR64
[%vreg99 -> %EAX] GR32
[%vreg103 -> %RCX] GR64_NOSP
[%vreg106 -> %ECX] GR32
[%vreg108 -> %EDX] GR32
[%vreg113 -> %RCX] GR64
[%vreg118 -> %RAX] GR64
[%vreg123 -> %EAX] GR32
[%vreg124 -> %RAX] GR64
[%vreg128 -> %RAX] GR64
[%vreg129 -> %RAX] GR64
[%vreg133 -> %ECX] GR32
[%vreg136 -> %RAX] GR64
[%vreg137 -> %RAX] GR64
[%vreg141 -> %ECX] GR32
[%vreg144 -> %RAX] GR64
[%vreg145 -> %RAX] GR64
[%vreg149 -> %RCX] GR64
[%vreg152 -> %RAX] GR64
[%vreg153 -> %RAX] GR64
[%vreg157 -> %ECX] GR32
[%vreg160 -> %RAX] GR64
[%vreg161 -> %RAX] GR64
[%vreg165 -> %ECX] GR32
[%vreg167 -> %RAX] GR64
[%vreg171 -> %RCX] GR64
[%vreg173 -> %EAX] GR32
[%vreg174 -> %RAX] GR64
[%vreg178 -> %RAX] GR64
[%vreg179 -> %RAX] GR64
[%vreg183 -> %RCX] GR64
[%vreg184 -> %EAX] GR32
[%vreg187 -> %EAX] GR32
[%vreg190 -> %RAX] GR64
[%vreg192 -> %RAX] GR64
[%vreg193 -> %RAX] GR64
[%vreg196 -> %RAX] GR64
[%vreg200 -> %RCX] GR64
[%vreg201 -> %EAX] GR32
[%vreg204 -> %RAX] GR64
[%vreg208 -> %ECX] GR32
[%vreg210 -> %RAX] GR64
[%vreg213 -> %RAX] GR64
[%vreg215 -> %RDI] GR64
[%vreg217 -> %RAX] GR64
[%vreg220 -> %RCX] GR64
[%vreg221 -> %EAX] GR32
[%vreg224 -> %RCX] GR64
[%vreg225 -> %EAX] GR32
[%vreg229 -> %ECX] GR32
[%vreg231 -> %RAX] GR64
[%vreg236 -> %RDX] GR64
[%vreg237 -> %RDX] GR64
[%vreg239 -> %RCX] GR64_NOSP
[%vreg241 -> %RCX] GR64
[%vreg242 -> %AL] GR8
[%vreg245 -> %RCX] GR64
[%vreg248 -> %RAX] GR64_NOSP
[%vreg250 -> %RAX] GR64
[%vreg253 -> %RCX] GR64
[%vreg256 -> %EAX] GR32
[%vreg260 -> %RCX] GR64_NOSP
[%vreg263 -> %ECX] GR32
[%vreg265 -> %EDX] GR32
[%vreg270 -> %RCX] GR64
[%vreg275 -> %RAX] GR64
[%vreg280 -> %EAX] GR32
[%vreg281 -> %RAX] GR64
[%vreg285 -> %RAX] GR64
[%vreg286 -> %RAX] GR64
[%vreg290 -> %ECX] GR32
[%vreg293 -> %RAX] GR64
[%vreg294 -> %RAX] GR64
[%vreg298 -> %ECX] GR32
[%vreg301 -> %RAX] GR64
[%vreg302 -> %RAX] GR64
[%vreg306 -> %RCX] GR64
[%vreg309 -> %RAX] GR64
[%vreg310 -> %RAX] GR64
[%vreg314 -> %ECX] GR32
[%vreg317 -> %RAX] GR64
[%vreg318 -> %RAX] GR64
[%vreg321 -> %RDI] GR64
[%vreg322 -> %RSI] GR64
[%vreg323 -> %BL] GR8


Stackmap 0:
  STACKMAP 0, 0, 0, <fi#3>, 0, 0, <fi#5>, 0, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack3](align=1) LD8[FixedStack5](align=1) LD8[FixedStack1](align=1) LD8[FixedStack0] LD8[FixedStack2](align=4) LD8[FixedStack4](align=4) GR64:%vreg1

i8* %ch: in stack slot 3 (size: 1)
i8* %ch89: in stack slot 5 (size: 1)
i8* %progress_in: in stack slot 1 (size: 1)
%struct.EState* %s: in register %RBX (vreg 1)
%struct.EState** %s.addr: in stack slot 0 (size: 8)
i32* %zchh: in stack slot 2 (size: 4)
i32* %zchh77: in stack slot 4 (size: 4)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, 0, <fi#3>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, ...; mem:LD8[FixedStack3](align=1) LD8[FixedStack1](align=1) LD8[FixedStack0] LD8[FixedStack2](align=4)

i8* %ch: in stack slot 3 (size: 1)
i8* %progress_in: in stack slot 1 (size: 1)
%struct.EState** %s.addr: in stack slot 0 (size: 8)
i32* %zchh: in stack slot 2 (size: 4)

Duplicate operand locations:


Stackmap 2:
  STACKMAP 2, 0, 0, <fi#5>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack5](align=1) LD8[FixedStack1](align=1) LD8[FixedStack0] LD8[FixedStack4](align=4)

i8* %ch89: in stack slot 5 (size: 1)
i8* %progress_in: in stack slot 1 (size: 1)
%struct.EState** %s.addr: in stack slot 0 (size: 8)
i32* %zchh77: in stack slot 4 (size: 4)

Duplicate operand locations:


Stackmap 3:
  STACKMAP 3, 0, %vreg323, ...; GR8:%vreg323

i8 %136: in register %BL (vreg 323)

Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, 0, <fi#3>, 0, 0, <fi#5>, 0, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack3](align=1) LD8[FixedStack5](align=1) LD8[FixedStack1](align=1) LD8[FixedStack0] LD8[FixedStack2](align=4) LD8[FixedStack4](align=4) GR64:%vreg1
  -> Call instruction SlotIndex 144B, searching vregs 0 -> 324 and stack slots -1 -> 6

  STACKMAP 1, 0, 0, <fi#3>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, ...; mem:LD8[FixedStack3](align=1) LD8[FixedStack1](align=1) LD8[FixedStack0] LD8[FixedStack2](align=4)
  -> Call instruction SlotIndex 1760B, searching vregs 0 -> 324 and stack slots -1 -> 6

  STACKMAP 2, 0, 0, <fi#5>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack5](align=1) LD8[FixedStack1](align=1) LD8[FixedStack0] LD8[FixedStack4](align=4)
  -> Call instruction SlotIndex 4176B, searching vregs 0 -> 324 and stack slots -1 -> 6

  STACKMAP 3, 0, %vreg323, ...; GR8:%vreg323
  -> Call instruction SlotIndex 5248B, searching vregs 0 -> 324 and stack slots -1 -> 6

********** REWRITE VIRTUAL REGISTERS **********
********** Function: copy_input_until_stop
********** REGISTER MAP **********
[%vreg1 -> %RBX] GR64
[%vreg4 -> %RAX] GR64
[%vreg6 -> %RDI] GR64
[%vreg7 -> %RSI] GR64
[%vreg11 -> %RCX] GR64
[%vreg13 -> %EAX] GR32
[%vreg14 -> %RAX] GR64
[%vreg18 -> %RAX] GR64
[%vreg19 -> %RAX] GR64
[%vreg22 -> %RAX] GR64
[%vreg26 -> %RCX] GR64
[%vreg27 -> %EAX] GR32
[%vreg30 -> %EAX] GR32
[%vreg33 -> %RAX] GR64
[%vreg35 -> %RAX] GR64
[%vreg36 -> %RAX] GR64
[%vreg39 -> %RAX] GR64
[%vreg43 -> %RCX] GR64
[%vreg44 -> %EAX] GR32
[%vreg47 -> %RAX] GR64
[%vreg51 -> %ECX] GR32
[%vreg53 -> %RAX] GR64
[%vreg56 -> %RAX] GR64
[%vreg58 -> %RDI] GR64
[%vreg60 -> %RAX] GR64
[%vreg63 -> %RCX] GR64
[%vreg64 -> %EAX] GR32
[%vreg67 -> %RCX] GR64
[%vreg68 -> %EAX] GR32
[%vreg72 -> %ECX] GR32
[%vreg74 -> %RAX] GR64
[%vreg79 -> %RDX] GR64
[%vreg80 -> %RDX] GR64
[%vreg82 -> %RCX] GR64_NOSP
[%vreg84 -> %RCX] GR64
[%vreg85 -> %AL] GR8
[%vreg88 -> %RCX] GR64
[%vreg91 -> %RAX] GR64_NOSP
[%vreg93 -> %RAX] GR64
[%vreg96 -> %RCX] GR64
[%vreg99 -> %EAX] GR32
[%vreg103 -> %RCX] GR64_NOSP
[%vreg106 -> %ECX] GR32
[%vreg108 -> %EDX] GR32
[%vreg113 -> %RCX] GR64
[%vreg118 -> %RAX] GR64
[%vreg123 -> %EAX] GR32
[%vreg124 -> %RAX] GR64
[%vreg128 -> %RAX] GR64
[%vreg129 -> %RAX] GR64
[%vreg133 -> %ECX] GR32
[%vreg136 -> %RAX] GR64
[%vreg137 -> %RAX] GR64
[%vreg141 -> %ECX] GR32
[%vreg144 -> %RAX] GR64
[%vreg145 -> %RAX] GR64
[%vreg149 -> %RCX] GR64
[%vreg152 -> %RAX] GR64
[%vreg153 -> %RAX] GR64
[%vreg157 -> %ECX] GR32
[%vreg160 -> %RAX] GR64
[%vreg161 -> %RAX] GR64
[%vreg165 -> %ECX] GR32
[%vreg167 -> %RAX] GR64
[%vreg171 -> %RCX] GR64
[%vreg173 -> %EAX] GR32
[%vreg174 -> %RAX] GR64
[%vreg178 -> %RAX] GR64
[%vreg179 -> %RAX] GR64
[%vreg183 -> %RCX] GR64
[%vreg184 -> %EAX] GR32
[%vreg187 -> %EAX] GR32
[%vreg190 -> %RAX] GR64
[%vreg192 -> %RAX] GR64
[%vreg193 -> %RAX] GR64
[%vreg196 -> %RAX] GR64
[%vreg200 -> %RCX] GR64
[%vreg201 -> %EAX] GR32
[%vreg204 -> %RAX] GR64
[%vreg208 -> %ECX] GR32
[%vreg210 -> %RAX] GR64
[%vreg213 -> %RAX] GR64
[%vreg215 -> %RDI] GR64
[%vreg217 -> %RAX] GR64
[%vreg220 -> %RCX] GR64
[%vreg221 -> %EAX] GR32
[%vreg224 -> %RCX] GR64
[%vreg225 -> %EAX] GR32
[%vreg229 -> %ECX] GR32
[%vreg231 -> %RAX] GR64
[%vreg236 -> %RDX] GR64
[%vreg237 -> %RDX] GR64
[%vreg239 -> %RCX] GR64_NOSP
[%vreg241 -> %RCX] GR64
[%vreg242 -> %AL] GR8
[%vreg245 -> %RCX] GR64
[%vreg248 -> %RAX] GR64_NOSP
[%vreg250 -> %RAX] GR64
[%vreg253 -> %RCX] GR64
[%vreg256 -> %EAX] GR32
[%vreg260 -> %RCX] GR64_NOSP
[%vreg263 -> %ECX] GR32
[%vreg265 -> %EDX] GR32
[%vreg270 -> %RCX] GR64
[%vreg275 -> %RAX] GR64
[%vreg280 -> %EAX] GR32
[%vreg281 -> %RAX] GR64
[%vreg285 -> %RAX] GR64
[%vreg286 -> %RAX] GR64
[%vreg290 -> %ECX] GR32
[%vreg293 -> %RAX] GR64
[%vreg294 -> %RAX] GR64
[%vreg298 -> %ECX] GR32
[%vreg301 -> %RAX] GR64
[%vreg302 -> %RAX] GR64
[%vreg306 -> %RCX] GR64
[%vreg309 -> %RAX] GR64
[%vreg310 -> %RAX] GR64
[%vreg314 -> %ECX] GR32
[%vreg317 -> %RAX] GR64
[%vreg318 -> %RAX] GR64
[%vreg321 -> %RDI] GR64
[%vreg322 -> %RSI] GR64
[%vreg323 -> %BL] GR8

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI
16B		%vreg1<def> = COPY %RDI; GR64:%vreg1
48B		%vreg6<def> = MOV64ri <ga:@copy_input_until_stop>; GR64:%vreg6
80B		%vreg7<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg7
96B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
112B		%RDI<def> = COPY %vreg6<kill>; GR64:%vreg6
128B		%RSI<def> = COPY %vreg7<kill>; GR64:%vreg7
144B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
160B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
192B		STACKMAP 0, 0, 0, <fi#3>, 0, 0, <fi#5>, 0, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack3](align=1) LD8[FixedStack5](align=1) LD8[FixedStack1](align=1) LD8[FixedStack0] LD8[FixedStack2](align=4) LD8[FixedStack4](align=4) GR64:%vreg1
208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1<kill>; mem:ST8[%s.addr] GR64:%vreg1
240B		MOV8mi <fi#1>, 1, %noreg, 0, %noreg, 0; mem:ST1[%progress_in]
256B		%vreg4<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg4
272B		CMP32mi8 %vreg4<kill>, 1, %noreg, 8, %noreg, 2, %EFLAGS<imp-def>; mem:LD4[%mode] GR64:%vreg4
288B		JNE_1 <BB#20>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#20 BB#1
> %RBX<def> = COPY %RDI
> %RDI<def> = MOV64ri <ga:@copy_input_until_stop>
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 0, 0, 0, <fi#3>, 0, 0, <fi#5>, 0, 0, <fi#1>, 0, %RBX, 0, <fi#0>, 0, 0, <fi#2>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack3](align=1) LD8[FixedStack5](align=1) LD8[FixedStack1](align=1) LD8[FixedStack0] LD8[FixedStack2](align=4) LD8[FixedStack4](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %RBX<kill>; mem:ST8[%s.addr]
> MOV8mi <fi#1>, 1, %noreg, 0, %noreg, 0; mem:ST1[%progress_in]
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> CMP32mi8 %RAX<kill>, 1, %noreg, 8, %noreg, 2, %EFLAGS<imp-def>; mem:LD4[%mode]
> JNE_1 <BB#20>, %EFLAGS<imp-use,kill>
304B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
320B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2
> JMP_1 <BB#2>
336B	BB#2: derived from LLVM BB %while.body
	    Predecessors according to CFG: BB#1 BB#18
352B		%vreg174<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg174
368B		%vreg173<def> = MOV32rm %vreg174<kill>, 1, %noreg, 108, %noreg; mem:LD4[%nblock] GR32:%vreg173 GR64:%vreg174
384B		%vreg171<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg171
400B		CMP32rm %vreg173<kill>, %vreg171<kill>, 1, %noreg, 112, %noreg, %EFLAGS<imp-def>; mem:LD4[%nblockMAX] GR32:%vreg173 GR64:%vreg171
416B		JL_1 <BB#4>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#4 BB#3
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 108, %noreg; mem:LD4[%nblock]
> %RCX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> CMP32rm %EAX<kill>, %RCX<kill>, 1, %noreg, 112, %noreg, %EFLAGS<imp-def>; mem:LD4[%nblockMAX]
> JL_1 <BB#4>, %EFLAGS<imp-use,kill>
432B	BB#3: derived from LLVM BB %if.then.2
	    Predecessors according to CFG: BB#2
448B		JMP_1 <BB#19>
	    Successors according to CFG: BB#19
> JMP_1 <BB#19>
464B	BB#4: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#2
480B		%vreg179<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg179
496B		%vreg178<def> = MOV64rm %vreg179<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm] GR64:%vreg178,%vreg179
512B		CMP32mi8 %vreg178<kill>, 1, %noreg, 8, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_in] GR64:%vreg178
528B		JNE_1 <BB#6>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#6 BB#5
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm]
> CMP32mi8 %RAX<kill>, 1, %noreg, 8, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_in]
> JNE_1 <BB#6>, %EFLAGS<imp-use,kill>
544B	BB#5: derived from LLVM BB %if.then.4
	    Predecessors according to CFG: BB#4
560B		JMP_1 <BB#19>
	    Successors according to CFG: BB#19
> JMP_1 <BB#19>
576B	BB#6: derived from LLVM BB %if.end.5
	    Predecessors according to CFG: BB#4
592B		MOV8mi <fi#1>, 1, %noreg, 0, %noreg, 1; mem:ST1[%progress_in]
608B		%vreg193<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg193
624B		%vreg192<def> = MOV64rm %vreg193<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm6] GR64:%vreg192,%vreg193
640B		%vreg190<def> = MOV64rm %vreg192<kill>, 1, %noreg, 0, %noreg; mem:LD8[%next_in] GR64:%vreg190,%vreg192
656B		%vreg187<def> = MOVZX32rm8 %vreg190<kill>, 1, %noreg, 0, %noreg; mem:LD1[%11] GR32:%vreg187 GR64:%vreg190
672B		MOV32mr <fi#2>, 1, %noreg, 0, %noreg, %vreg187<kill>; mem:ST4[%zchh] GR32:%vreg187
688B		%vreg184<def> = MOV32rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD4[%zchh] GR32:%vreg184
704B		%vreg183<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg183
720B		CMP32rm %vreg184<kill>, %vreg183<kill>, 1, %noreg, 92, %noreg, %EFLAGS<imp-def>; mem:LD4[%state_in_ch] GR32:%vreg184 GR64:%vreg183
736B		JE_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#7
> MOV8mi <fi#1>, 1, %noreg, 0, %noreg, 1; mem:ST1[%progress_in]
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm6]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%next_in]
> %EAX<def> = MOVZX32rm8 %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD1[%11]
> MOV32mr <fi#2>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%zchh]
> %EAX<def> = MOV32rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD4[%zchh]
> %RCX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> CMP32rm %EAX<kill>, %RCX<kill>, 1, %noreg, 92, %noreg, %EFLAGS<imp-def>; mem:LD4[%state_in_ch]
> JE_1 <BB#9>, %EFLAGS<imp-use,kill>
752B	BB#7: derived from LLVM BB %land.lhs.true
	    Predecessors according to CFG: BB#6
768B		%vreg196<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg196
784B		CMP32mi8 %vreg196<kill>, 1, %noreg, 96, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%state_in_len] GR64:%vreg196
800B		JNE_1 <BB#9>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#9 BB#8
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> CMP32mi8 %RAX<kill>, 1, %noreg, 96, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%state_in_len]
> JNE_1 <BB#9>, %EFLAGS<imp-use,kill>
816B	BB#8: derived from LLVM BB %if.then.11
	    Predecessors according to CFG: BB#7
832B		%vreg281<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg281
848B		%vreg280<def> = MOV32rm %vreg281<kill>, 1, %noreg, 92, %noreg; mem:LD4[%state_in_ch12] GR32:%vreg280 GR64:%vreg281
880B		MOV8mr <fi#3>, 1, %noreg, 0, %noreg, %vreg280:sub_8bit<kill>; mem:ST1[%ch] GR32:%vreg280
896B		%vreg275<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg275
912B		%vreg256<def> = MOV32rm %vreg275<kill>, 1, %noreg, 648, %noreg; mem:LD4[%blockCRC] GR32:%vreg256 GR64:%vreg275
944B		%vreg256<def,tied1> = SHL32ri %vreg256<kill,tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg256
960B		%vreg270<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg270
976B		%vreg263<def> = MOV32rm %vreg270<kill>, 1, %noreg, 648, %noreg; mem:LD4[%blockCRC14] GR32:%vreg263 GR64:%vreg270
1008B		%vreg263<def,tied1> = SHR32ri %vreg263<kill,tied0>, 24, %EFLAGS<imp-def,dead>; GR32:%vreg263
1024B		%vreg265<def> = MOVZX32rm8 <fi#3>, 1, %noreg, 0, %noreg; mem:LD1[%ch] GR32:%vreg265
1056B		%vreg263<def,tied1> = XOR32rr %vreg263<kill,tied0>, %vreg265<kill>, %EFLAGS<imp-def,dead>; GR32:%vreg263,%vreg265
1072B		%vreg260:sub_32bit<def,read-undef> = MOV32rr %vreg263<kill>; GR64_NOSP:%vreg260 GR32:%vreg263
1120B		%vreg256<def,tied1> = XOR32rm %vreg256<kill,tied0>, %noreg, 4, %vreg260<kill>, <ga:@BZ2_crc32Table>, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%arrayidx] GR32:%vreg256 GR64_NOSP:%vreg260
1136B		%vreg253<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg253
1152B		MOV32mr %vreg253<kill>, 1, %noreg, 648, %noreg, %vreg256<kill>; mem:ST4[%blockCRC17] GR64:%vreg253 GR32:%vreg256
1168B		%vreg250<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg250
1184B		%vreg248:sub_32bit<def,read-undef> = MOV32rm %vreg250<kill>, 1, %noreg, 92, %noreg; mem:LD4[%state_in_ch18] GR64_NOSP:%vreg248 GR64:%vreg250
1216B		%vreg245<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg245
1232B		MOV8mi %vreg245<kill>, 1, %vreg248<kill>, 128, %noreg, 1; mem:ST1[%arrayidx20] GR64:%vreg245 GR64_NOSP:%vreg248
1248B		%vreg242<def> = MOV8rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD1[%ch] GR8:%vreg242
1264B		%vreg241<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg241
1280B		%vreg239<def> = MOVSX64rm32 %vreg241<kill>, 1, %noreg, 108, %noreg; mem:LD4[%nblock21] GR64_NOSP:%vreg239 GR64:%vreg241
1296B		%vreg237<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg237
1312B		%vreg236<def> = MOV64rm %vreg237<kill>, 1, %noreg, 64, %noreg; mem:LD8[%block] GR64:%vreg236,%vreg237
1328B		MOV8mr %vreg236<kill>, 1, %vreg239<kill>, 0, %noreg, %vreg242<kill>; mem:ST1[%arrayidx23] GR64:%vreg236 GR64_NOSP:%vreg239 GR8:%vreg242
1344B		%vreg231<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg231
1360B		%vreg229<def> = MOV32rm %vreg231, 1, %noreg, 108, %noreg; mem:LD4[%nblock24] GR32:%vreg229 GR64:%vreg231
1392B		%vreg229<def,tied1> = ADD32ri8 %vreg229<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg229
1408B		MOV32mr %vreg231<kill>, 1, %noreg, 108, %noreg, %vreg229<kill>; mem:ST4[%nblock24] GR64:%vreg231 GR32:%vreg229
1424B		%vreg225<def> = MOV32rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD4[%zchh] GR32:%vreg225
1440B		%vreg224<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg224
1456B		MOV32mr %vreg224<kill>, 1, %noreg, 92, %noreg, %vreg225<kill>; mem:ST4[%state_in_ch25] GR64:%vreg224 GR32:%vreg225
1472B		JMP_1 <BB#16>
	    Successors according to CFG: BB#16
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 92, %noreg; mem:LD4[%state_in_ch12]
> MOV8mr <fi#3>, 1, %noreg, 0, %noreg, %AL, %EAX<imp-use,kill>; mem:ST1[%ch]
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 648, %noreg; mem:LD4[%blockCRC]
> %EAX<def,tied1> = SHL32ri %EAX<kill,tied0>, 8, %EFLAGS<imp-def,dead>
> %RCX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RCX<kill>, 1, %noreg, 648, %noreg; mem:LD4[%blockCRC14]
> %ECX<def,tied1> = SHR32ri %ECX<kill,tied0>, 24, %EFLAGS<imp-def,dead>
> %EDX<def> = MOVZX32rm8 <fi#3>, 1, %noreg, 0, %noreg; mem:LD1[%ch]
> %ECX<def,tied1> = XOR32rr %ECX<kill,tied0>, %EDX<kill>, %EFLAGS<imp-def,dead>
> %ECX<def> = MOV32rr %ECX<kill>, %RCX<imp-def>
> %EAX<def,tied1> = XOR32rm %EAX<kill,tied0>, %noreg, 4, %RCX<kill>, <ga:@BZ2_crc32Table>, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%arrayidx]
> %RCX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mr %RCX<kill>, 1, %noreg, 648, %noreg, %EAX<kill>; mem:ST4[%blockCRC17]
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 92, %noreg, %RAX<imp-def>; mem:LD4[%state_in_ch18]
> %RCX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV8mi %RCX<kill>, 1, %RAX<kill>, 128, %noreg, 1; mem:ST1[%arrayidx20]
> %AL<def> = MOV8rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD1[%ch]
> %RCX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RCX<def> = MOVSX64rm32 %RCX<kill>, 1, %noreg, 108, %noreg; mem:LD4[%nblock21]
> %RDX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RDX<def> = MOV64rm %RDX<kill>, 1, %noreg, 64, %noreg; mem:LD8[%block]
> MOV8mr %RDX<kill>, 1, %RCX<kill>, 0, %noreg, %AL<kill>; mem:ST1[%arrayidx23]
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 108, %noreg; mem:LD4[%nblock24]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 108, %noreg, %ECX<kill>; mem:ST4[%nblock24]
> %EAX<def> = MOV32rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD4[%zchh]
> %RCX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mr %RCX<kill>, 1, %noreg, 92, %noreg, %EAX<kill>; mem:ST4[%state_in_ch25]
> JMP_1 <BB#16>
1488B	BB#9: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#6 BB#7
1504B		%vreg201<def> = MOV32rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD4[%zchh] GR32:%vreg201
1520B		%vreg200<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg200
1536B		CMP32rm %vreg201<kill>, %vreg200<kill>, 1, %noreg, 92, %noreg, %EFLAGS<imp-def>; mem:LD4[%state_in_ch26] GR32:%vreg201 GR64:%vreg200
1552B		JNE_1 <BB#11>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#11 BB#10
> %EAX<def> = MOV32rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD4[%zchh]
> %RCX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> CMP32rm %EAX<kill>, %RCX<kill>, 1, %noreg, 92, %noreg, %EFLAGS<imp-def>; mem:LD4[%state_in_ch26]
> JNE_1 <BB#11>, %EFLAGS<imp-use,kill>
1568B	BB#10: derived from LLVM BB %lor.lhs.false
	    Predecessors according to CFG: BB#9
1584B		%vreg204<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg204
1600B		CMP32mi %vreg204<kill>, 1, %noreg, 96, %noreg, 255, %EFLAGS<imp-def>; mem:LD4[%state_in_len29] GR64:%vreg204
1616B		JNE_1 <BB#14>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#14 BB#11
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> CMP32mi %RAX<kill>, 1, %noreg, 96, %noreg, 255, %EFLAGS<imp-def>; mem:LD4[%state_in_len29]
> JNE_1 <BB#14>, %EFLAGS<imp-use,kill>
1632B	BB#11: derived from LLVM BB %if.then.32
	    Predecessors according to CFG: BB#9 BB#10
1648B		%vreg213<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg213
1664B		CMP32mi %vreg213<kill>, 1, %noreg, 92, %noreg, 256, %EFLAGS<imp-def>; mem:LD4[%state_in_ch33] GR64:%vreg213
1680B		JAE_1 <BB#13>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#13 BB#12
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> CMP32mi %RAX<kill>, 1, %noreg, 92, %noreg, 256, %EFLAGS<imp-def>; mem:LD4[%state_in_ch33]
> JAE_1 <BB#13>, %EFLAGS<imp-use,kill>
1696B	BB#12: derived from LLVM BB %if.then.36
	    Predecessors according to CFG: BB#11
1712B		%vreg215<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg215
1728B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1744B		%RDI<def> = COPY %vreg215<kill>; GR64:%vreg215
1760B		CALL64pcrel32 <ga:@add_pair_to_block>, <regmask>, %RSP<imp-use>, %RDI<imp-use>
1776B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1792B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1808B		STACKMAP 1, 0, 0, <fi#3>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, ...; mem:LD8[FixedStack3](align=1) LD8[FixedStack1](align=1) LD8[FixedStack0] LD8[FixedStack2](align=4)
1824B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#13
> %RDI<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@add_pair_to_block>, <regmask>, %RSP<imp-use>, %RDI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 1, 0, 0, <fi#3>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#2>, 0, ...; mem:LD8[FixedStack3](align=1) LD8[FixedStack1](align=1) LD8[FixedStack0] LD8[FixedStack2](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
1840B	BB#13: derived from LLVM BB %if.end.37
	    Predecessors according to CFG: BB#11 BB#12
1856B		%vreg221<def> = MOV32rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD4[%zchh] GR32:%vreg221
1872B		%vreg220<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg220
1888B		MOV32mr %vreg220<kill>, 1, %noreg, 92, %noreg, %vreg221<kill>; mem:ST4[%state_in_ch38] GR64:%vreg220 GR32:%vreg221
1904B		%vreg217<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg217
1920B		MOV32mi %vreg217<kill>, 1, %noreg, 96, %noreg, 1; mem:ST4[%state_in_len39] GR64:%vreg217
1936B		JMP_1 <BB#15>
	    Successors according to CFG: BB#15
> %EAX<def> = MOV32rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD4[%zchh]
> %RCX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mr %RCX<kill>, 1, %noreg, 92, %noreg, %EAX<kill>; mem:ST4[%state_in_ch38]
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 96, %noreg, 1; mem:ST4[%state_in_len39]
> JMP_1 <BB#15>
1952B	BB#14: derived from LLVM BB %if.else.40
	    Predecessors according to CFG: BB#10
1968B		%vreg210<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg210
1984B		%vreg208<def> = MOV32rm %vreg210, 1, %noreg, 96, %noreg; mem:LD4[%state_in_len41] GR32:%vreg208 GR64:%vreg210
2016B		%vreg208<def,tied1> = ADD32ri8 %vreg208<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg208
2032B		MOV32mr %vreg210<kill>, 1, %noreg, 96, %noreg, %vreg208<kill>; mem:ST4[%state_in_len41] GR64:%vreg210 GR32:%vreg208
	    Successors according to CFG: BB#15
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 96, %noreg; mem:LD4[%state_in_len41]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 96, %noreg, %ECX<kill>; mem:ST4[%state_in_len41]
2048B	BB#15: derived from LLVM BB %if.end.43
	    Predecessors according to CFG: BB#14 BB#13
2064B		JMP_1 <BB#16>
	    Successors according to CFG: BB#16
> JMP_1 <BB#16>
2080B	BB#16: derived from LLVM BB %if.end.44
	    Predecessors according to CFG: BB#15 BB#8
2096B		%vreg310<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg310
2112B		%vreg309<def> = MOV64rm %vreg310<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm45] GR64:%vreg309,%vreg310
2128B		%vreg306<def> = MOV64rm %vreg309, 1, %noreg, 0, %noreg; mem:LD8[%next_in46] GR64:%vreg306,%vreg309
2160B		%vreg306<def,tied1> = ADD64ri8 %vreg306<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR64:%vreg306
2176B		MOV64mr %vreg309<kill>, 1, %noreg, 0, %noreg, %vreg306<kill>; mem:ST8[%next_in46] GR64:%vreg309,%vreg306
2192B		%vreg302<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg302
2208B		%vreg301<def> = MOV64rm %vreg302<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm47] GR64:%vreg301,%vreg302
2224B		%vreg298<def> = MOV32rm %vreg301, 1, %noreg, 8, %noreg; mem:LD4[%avail_in48] GR32:%vreg298 GR64:%vreg301
2256B		%vreg298<def,tied1> = ADD32ri8 %vreg298<kill,tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg298
2272B		MOV32mr %vreg301<kill>, 1, %noreg, 8, %noreg, %vreg298<kill>; mem:ST4[%avail_in48] GR64:%vreg301 GR32:%vreg298
2288B		%vreg294<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg294
2304B		%vreg293<def> = MOV64rm %vreg294<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm49] GR64:%vreg293,%vreg294
2320B		%vreg290<def> = MOV32rm %vreg293, 1, %noreg, 12, %noreg; mem:LD4[%total_in_lo32] GR32:%vreg290 GR64:%vreg293
2352B		%vreg290<def,tied1> = ADD32ri8 %vreg290<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg290
2368B		MOV32mr %vreg293<kill>, 1, %noreg, 12, %noreg, %vreg290<kill>; mem:ST4[%total_in_lo32] GR64:%vreg293 GR32:%vreg290
2384B		%vreg286<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg286
2400B		%vreg285<def> = MOV64rm %vreg286<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm51] GR64:%vreg285,%vreg286
2416B		CMP32mi8 %vreg285<kill>, 1, %noreg, 12, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%total_in_lo3252] GR64:%vreg285
2432B		JNE_1 <BB#18>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#18 BB#17
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm45]
> %RCX<def> = MOV64rm %RAX, 1, %noreg, 0, %noreg; mem:LD8[%next_in46]
> %RCX<def,tied1> = ADD64ri8 %RCX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV64mr %RAX<kill>, 1, %noreg, 0, %noreg, %RCX<kill>; mem:ST8[%next_in46]
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm47]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 8, %noreg; mem:LD4[%avail_in48]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, -1, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 8, %noreg, %ECX<kill>; mem:ST4[%avail_in48]
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm49]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 12, %noreg; mem:LD4[%total_in_lo32]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 12, %noreg, %ECX<kill>; mem:ST4[%total_in_lo32]
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm51]
> CMP32mi8 %RAX<kill>, 1, %noreg, 12, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%total_in_lo3252]
> JNE_1 <BB#18>, %EFLAGS<imp-use,kill>
2448B	BB#17: derived from LLVM BB %if.then.55
	    Predecessors according to CFG: BB#16
2464B		%vreg318<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg318
2480B		%vreg317<def> = MOV64rm %vreg318<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm56] GR64:%vreg317,%vreg318
2496B		%vreg314<def> = MOV32rm %vreg317, 1, %noreg, 16, %noreg; mem:LD4[%total_in_hi32] GR32:%vreg314 GR64:%vreg317
2528B		%vreg314<def,tied1> = ADD32ri8 %vreg314<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg314
2544B		MOV32mr %vreg317<kill>, 1, %noreg, 16, %noreg, %vreg314<kill>; mem:ST4[%total_in_hi32] GR64:%vreg317 GR32:%vreg314
	    Successors according to CFG: BB#18
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm56]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 16, %noreg; mem:LD4[%total_in_hi32]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 16, %noreg, %ECX<kill>; mem:ST4[%total_in_hi32]
2560B	BB#18: derived from LLVM BB %if.end.58
	    Predecessors according to CFG: BB#16 BB#17
2576B		JMP_1 <BB#2>
	    Successors according to CFG: BB#2
> JMP_1 <BB#2>
2592B	BB#19: derived from LLVM BB %while.end
	    Predecessors according to CFG: BB#5 BB#3
2608B		JMP_1 <BB#41>
	    Successors according to CFG: BB#41
> JMP_1 <BB#41>
2624B	BB#20: derived from LLVM BB %if.else.59
	    Predecessors according to CFG: BB#0
2640B		JMP_1 <BB#21>
	    Successors according to CFG: BB#21
> JMP_1 <BB#21>
2656B	BB#21: derived from LLVM BB %while.body.60
	    Predecessors according to CFG: BB#20 BB#39
2672B		%vreg14<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg14
2688B		%vreg13<def> = MOV32rm %vreg14<kill>, 1, %noreg, 108, %noreg; mem:LD4[%nblock61] GR32:%vreg13 GR64:%vreg14
2704B		%vreg11<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg11
2720B		CMP32rm %vreg13<kill>, %vreg11<kill>, 1, %noreg, 112, %noreg, %EFLAGS<imp-def>; mem:LD4[%nblockMAX62] GR32:%vreg13 GR64:%vreg11
2736B		JL_1 <BB#23>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#23 BB#22
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 108, %noreg; mem:LD4[%nblock61]
> %RCX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> CMP32rm %EAX<kill>, %RCX<kill>, 1, %noreg, 112, %noreg, %EFLAGS<imp-def>; mem:LD4[%nblockMAX62]
> JL_1 <BB#23>, %EFLAGS<imp-use,kill>
2752B	BB#22: derived from LLVM BB %if.then.65
	    Predecessors according to CFG: BB#21
2768B		JMP_1 <BB#40>
	    Successors according to CFG: BB#40
> JMP_1 <BB#40>
2784B	BB#23: derived from LLVM BB %if.end.66
	    Predecessors according to CFG: BB#21
2800B		%vreg19<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg19
2816B		%vreg18<def> = MOV64rm %vreg19<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm67] GR64:%vreg18,%vreg19
2832B		CMP32mi8 %vreg18<kill>, 1, %noreg, 8, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_in68] GR64:%vreg18
2848B		JNE_1 <BB#25>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#25 BB#24
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm67]
> CMP32mi8 %RAX<kill>, 1, %noreg, 8, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_in68]
> JNE_1 <BB#25>, %EFLAGS<imp-use,kill>
2864B	BB#24: derived from LLVM BB %if.then.71
	    Predecessors according to CFG: BB#23
2880B		JMP_1 <BB#40>
	    Successors according to CFG: BB#40
> JMP_1 <BB#40>
2896B	BB#25: derived from LLVM BB %if.end.72
	    Predecessors according to CFG: BB#23
2912B		%vreg22<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg22
2928B		CMP32mi8 %vreg22<kill>, 1, %noreg, 16, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_in_expect] GR64:%vreg22
2944B		JNE_1 <BB#27>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#27 BB#26
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> CMP32mi8 %RAX<kill>, 1, %noreg, 16, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%avail_in_expect]
> JNE_1 <BB#27>, %EFLAGS<imp-use,kill>
2960B	BB#26: derived from LLVM BB %if.then.75
	    Predecessors according to CFG: BB#25
2976B		JMP_1 <BB#40>
	    Successors according to CFG: BB#40
> JMP_1 <BB#40>
2992B	BB#27: derived from LLVM BB %if.end.76
	    Predecessors according to CFG: BB#25
3008B		MOV8mi <fi#1>, 1, %noreg, 0, %noreg, 1; mem:ST1[%progress_in]
3024B		%vreg36<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg36
3040B		%vreg35<def> = MOV64rm %vreg36<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm78] GR64:%vreg35,%vreg36
3056B		%vreg33<def> = MOV64rm %vreg35<kill>, 1, %noreg, 0, %noreg; mem:LD8[%next_in79] GR64:%vreg33,%vreg35
3072B		%vreg30<def> = MOVZX32rm8 %vreg33<kill>, 1, %noreg, 0, %noreg; mem:LD1[%78] GR32:%vreg30 GR64:%vreg33
3088B		MOV32mr <fi#4>, 1, %noreg, 0, %noreg, %vreg30<kill>; mem:ST4[%zchh77] GR32:%vreg30
3104B		%vreg27<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%zchh77] GR32:%vreg27
3120B		%vreg26<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg26
3136B		CMP32rm %vreg27<kill>, %vreg26<kill>, 1, %noreg, 92, %noreg, %EFLAGS<imp-def>; mem:LD4[%state_in_ch81] GR32:%vreg27 GR64:%vreg26
3152B		JE_1 <BB#30>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#30 BB#28
> MOV8mi <fi#1>, 1, %noreg, 0, %noreg, 1; mem:ST1[%progress_in]
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm78]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%next_in79]
> %EAX<def> = MOVZX32rm8 %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD1[%78]
> MOV32mr <fi#4>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%zchh77]
> %EAX<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%zchh77]
> %RCX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> CMP32rm %EAX<kill>, %RCX<kill>, 1, %noreg, 92, %noreg, %EFLAGS<imp-def>; mem:LD4[%state_in_ch81]
> JE_1 <BB#30>, %EFLAGS<imp-use,kill>
3168B	BB#28: derived from LLVM BB %land.lhs.true.84
	    Predecessors according to CFG: BB#27
3184B		%vreg39<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg39
3200B		CMP32mi8 %vreg39<kill>, 1, %noreg, 96, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%state_in_len85] GR64:%vreg39
3216B		JNE_1 <BB#30>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#30 BB#29
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> CMP32mi8 %RAX<kill>, 1, %noreg, 96, %noreg, 1, %EFLAGS<imp-def>; mem:LD4[%state_in_len85]
> JNE_1 <BB#30>, %EFLAGS<imp-use,kill>
3232B	BB#29: derived from LLVM BB %if.then.88
	    Predecessors according to CFG: BB#28
3248B		%vreg124<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg124
3264B		%vreg123<def> = MOV32rm %vreg124<kill>, 1, %noreg, 92, %noreg; mem:LD4[%state_in_ch90] GR32:%vreg123 GR64:%vreg124
3296B		MOV8mr <fi#5>, 1, %noreg, 0, %noreg, %vreg123:sub_8bit<kill>; mem:ST1[%ch89] GR32:%vreg123
3312B		%vreg118<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg118
3328B		%vreg99<def> = MOV32rm %vreg118<kill>, 1, %noreg, 648, %noreg; mem:LD4[%blockCRC92] GR32:%vreg99 GR64:%vreg118
3360B		%vreg99<def,tied1> = SHL32ri %vreg99<kill,tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg99
3376B		%vreg113<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg113
3392B		%vreg106<def> = MOV32rm %vreg113<kill>, 1, %noreg, 648, %noreg; mem:LD4[%blockCRC94] GR32:%vreg106 GR64:%vreg113
3424B		%vreg106<def,tied1> = SHR32ri %vreg106<kill,tied0>, 24, %EFLAGS<imp-def,dead>; GR32:%vreg106
3440B		%vreg108<def> = MOVZX32rm8 <fi#5>, 1, %noreg, 0, %noreg; mem:LD1[%ch89] GR32:%vreg108
3472B		%vreg106<def,tied1> = XOR32rr %vreg106<kill,tied0>, %vreg108<kill>, %EFLAGS<imp-def,dead>; GR32:%vreg106,%vreg108
3488B		%vreg103:sub_32bit<def,read-undef> = MOV32rr %vreg106<kill>; GR64_NOSP:%vreg103 GR32:%vreg106
3536B		%vreg99<def,tied1> = XOR32rm %vreg99<kill,tied0>, %noreg, 4, %vreg103<kill>, <ga:@BZ2_crc32Table>, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%arrayidx99] GR32:%vreg99 GR64_NOSP:%vreg103
3552B		%vreg96<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg96
3568B		MOV32mr %vreg96<kill>, 1, %noreg, 648, %noreg, %vreg99<kill>; mem:ST4[%blockCRC101] GR64:%vreg96 GR32:%vreg99
3584B		%vreg93<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg93
3600B		%vreg91:sub_32bit<def,read-undef> = MOV32rm %vreg93<kill>, 1, %noreg, 92, %noreg; mem:LD4[%state_in_ch102] GR64_NOSP:%vreg91 GR64:%vreg93
3632B		%vreg88<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg88
3648B		MOV8mi %vreg88<kill>, 1, %vreg91<kill>, 128, %noreg, 1; mem:ST1[%arrayidx105] GR64:%vreg88 GR64_NOSP:%vreg91
3664B		%vreg85<def> = MOV8rm <fi#5>, 1, %noreg, 0, %noreg; mem:LD1[%ch89] GR8:%vreg85
3680B		%vreg84<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg84
3696B		%vreg82<def> = MOVSX64rm32 %vreg84<kill>, 1, %noreg, 108, %noreg; mem:LD4[%nblock106] GR64_NOSP:%vreg82 GR64:%vreg84
3712B		%vreg80<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg80
3728B		%vreg79<def> = MOV64rm %vreg80<kill>, 1, %noreg, 64, %noreg; mem:LD8[%block108] GR64:%vreg79,%vreg80
3744B		MOV8mr %vreg79<kill>, 1, %vreg82<kill>, 0, %noreg, %vreg85<kill>; mem:ST1[%arrayidx109] GR64:%vreg79 GR64_NOSP:%vreg82 GR8:%vreg85
3760B		%vreg74<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg74
3776B		%vreg72<def> = MOV32rm %vreg74, 1, %noreg, 108, %noreg; mem:LD4[%nblock110] GR32:%vreg72 GR64:%vreg74
3808B		%vreg72<def,tied1> = ADD32ri8 %vreg72<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg72
3824B		MOV32mr %vreg74<kill>, 1, %noreg, 108, %noreg, %vreg72<kill>; mem:ST4[%nblock110] GR64:%vreg74 GR32:%vreg72
3840B		%vreg68<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%zchh77] GR32:%vreg68
3856B		%vreg67<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg67
3872B		MOV32mr %vreg67<kill>, 1, %noreg, 92, %noreg, %vreg68<kill>; mem:ST4[%state_in_ch112] GR64:%vreg67 GR32:%vreg68
3888B		JMP_1 <BB#37>
	    Successors according to CFG: BB#37
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 92, %noreg; mem:LD4[%state_in_ch90]
> MOV8mr <fi#5>, 1, %noreg, 0, %noreg, %AL, %EAX<imp-use,kill>; mem:ST1[%ch89]
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 648, %noreg; mem:LD4[%blockCRC92]
> %EAX<def,tied1> = SHL32ri %EAX<kill,tied0>, 8, %EFLAGS<imp-def,dead>
> %RCX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RCX<kill>, 1, %noreg, 648, %noreg; mem:LD4[%blockCRC94]
> %ECX<def,tied1> = SHR32ri %ECX<kill,tied0>, 24, %EFLAGS<imp-def,dead>
> %EDX<def> = MOVZX32rm8 <fi#5>, 1, %noreg, 0, %noreg; mem:LD1[%ch89]
> %ECX<def,tied1> = XOR32rr %ECX<kill,tied0>, %EDX<kill>, %EFLAGS<imp-def,dead>
> %ECX<def> = MOV32rr %ECX<kill>, %RCX<imp-def>
> %EAX<def,tied1> = XOR32rm %EAX<kill,tied0>, %noreg, 4, %RCX<kill>, <ga:@BZ2_crc32Table>, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%arrayidx99]
> %RCX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mr %RCX<kill>, 1, %noreg, 648, %noreg, %EAX<kill>; mem:ST4[%blockCRC101]
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 92, %noreg, %RAX<imp-def>; mem:LD4[%state_in_ch102]
> %RCX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV8mi %RCX<kill>, 1, %RAX<kill>, 128, %noreg, 1; mem:ST1[%arrayidx105]
> %AL<def> = MOV8rm <fi#5>, 1, %noreg, 0, %noreg; mem:LD1[%ch89]
> %RCX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RCX<def> = MOVSX64rm32 %RCX<kill>, 1, %noreg, 108, %noreg; mem:LD4[%nblock106]
> %RDX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RDX<def> = MOV64rm %RDX<kill>, 1, %noreg, 64, %noreg; mem:LD8[%block108]
> MOV8mr %RDX<kill>, 1, %RCX<kill>, 0, %noreg, %AL<kill>; mem:ST1[%arrayidx109]
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 108, %noreg; mem:LD4[%nblock110]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 108, %noreg, %ECX<kill>; mem:ST4[%nblock110]
> %EAX<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%zchh77]
> %RCX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mr %RCX<kill>, 1, %noreg, 92, %noreg, %EAX<kill>; mem:ST4[%state_in_ch112]
> JMP_1 <BB#37>
3904B	BB#30: derived from LLVM BB %if.else.113
	    Predecessors according to CFG: BB#27 BB#28
3920B		%vreg44<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%zchh77] GR32:%vreg44
3936B		%vreg43<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg43
3952B		CMP32rm %vreg44<kill>, %vreg43<kill>, 1, %noreg, 92, %noreg, %EFLAGS<imp-def>; mem:LD4[%state_in_ch114] GR32:%vreg44 GR64:%vreg43
3968B		JNE_1 <BB#32>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#32 BB#31
> %EAX<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%zchh77]
> %RCX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> CMP32rm %EAX<kill>, %RCX<kill>, 1, %noreg, 92, %noreg, %EFLAGS<imp-def>; mem:LD4[%state_in_ch114]
> JNE_1 <BB#32>, %EFLAGS<imp-use,kill>
3984B	BB#31: derived from LLVM BB %lor.lhs.false.117
	    Predecessors according to CFG: BB#30
4000B		%vreg47<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg47
4016B		CMP32mi %vreg47<kill>, 1, %noreg, 96, %noreg, 255, %EFLAGS<imp-def>; mem:LD4[%state_in_len118] GR64:%vreg47
4032B		JNE_1 <BB#35>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#35 BB#32
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> CMP32mi %RAX<kill>, 1, %noreg, 96, %noreg, 255, %EFLAGS<imp-def>; mem:LD4[%state_in_len118]
> JNE_1 <BB#35>, %EFLAGS<imp-use,kill>
4048B	BB#32: derived from LLVM BB %if.then.121
	    Predecessors according to CFG: BB#30 BB#31
4064B		%vreg56<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg56
4080B		CMP32mi %vreg56<kill>, 1, %noreg, 92, %noreg, 256, %EFLAGS<imp-def>; mem:LD4[%state_in_ch122] GR64:%vreg56
4096B		JAE_1 <BB#34>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#34 BB#33
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> CMP32mi %RAX<kill>, 1, %noreg, 92, %noreg, 256, %EFLAGS<imp-def>; mem:LD4[%state_in_ch122]
> JAE_1 <BB#34>, %EFLAGS<imp-use,kill>
4112B	BB#33: derived from LLVM BB %if.then.125
	    Predecessors according to CFG: BB#32
4128B		%vreg58<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg58
4144B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4160B		%RDI<def> = COPY %vreg58<kill>; GR64:%vreg58
4176B		CALL64pcrel32 <ga:@add_pair_to_block>, <regmask>, %RSP<imp-use>, %RDI<imp-use>
4192B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4208B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4224B		STACKMAP 2, 0, 0, <fi#5>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack5](align=1) LD8[FixedStack1](align=1) LD8[FixedStack0] LD8[FixedStack4](align=4)
4240B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#34
> %RDI<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@add_pair_to_block>, <regmask>, %RSP<imp-use>, %RDI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 2, 0, 0, <fi#5>, 0, 0, <fi#1>, 0, 0, <fi#0>, 0, 0, <fi#4>, 0, ...; mem:LD8[FixedStack5](align=1) LD8[FixedStack1](align=1) LD8[FixedStack0] LD8[FixedStack4](align=4)
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
4256B	BB#34: derived from LLVM BB %if.end.126
	    Predecessors according to CFG: BB#32 BB#33
4272B		%vreg64<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%zchh77] GR32:%vreg64
4288B		%vreg63<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg63
4304B		MOV32mr %vreg63<kill>, 1, %noreg, 92, %noreg, %vreg64<kill>; mem:ST4[%state_in_ch127] GR64:%vreg63 GR32:%vreg64
4320B		%vreg60<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg60
4336B		MOV32mi %vreg60<kill>, 1, %noreg, 96, %noreg, 1; mem:ST4[%state_in_len128] GR64:%vreg60
4352B		JMP_1 <BB#36>
	    Successors according to CFG: BB#36
> %EAX<def> = MOV32rm <fi#4>, 1, %noreg, 0, %noreg; mem:LD4[%zchh77]
> %RCX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mr %RCX<kill>, 1, %noreg, 92, %noreg, %EAX<kill>; mem:ST4[%state_in_ch127]
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mi %RAX<kill>, 1, %noreg, 96, %noreg, 1; mem:ST4[%state_in_len128]
> JMP_1 <BB#36>
4368B	BB#35: derived from LLVM BB %if.else.129
	    Predecessors according to CFG: BB#31
4384B		%vreg53<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg53
4400B		%vreg51<def> = MOV32rm %vreg53, 1, %noreg, 96, %noreg; mem:LD4[%state_in_len130] GR32:%vreg51 GR64:%vreg53
4432B		%vreg51<def,tied1> = ADD32ri8 %vreg51<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg51
4448B		MOV32mr %vreg53<kill>, 1, %noreg, 96, %noreg, %vreg51<kill>; mem:ST4[%state_in_len130] GR64:%vreg53 GR32:%vreg51
	    Successors according to CFG: BB#36
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 96, %noreg; mem:LD4[%state_in_len130]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 96, %noreg, %ECX<kill>; mem:ST4[%state_in_len130]
4464B	BB#36: derived from LLVM BB %if.end.132
	    Predecessors according to CFG: BB#35 BB#34
4480B		JMP_1 <BB#37>
	    Successors according to CFG: BB#37
> JMP_1 <BB#37>
4496B	BB#37: derived from LLVM BB %if.end.133
	    Predecessors according to CFG: BB#36 BB#29
4512B		%vreg153<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg153
4528B		%vreg152<def> = MOV64rm %vreg153<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm134] GR64:%vreg152,%vreg153
4544B		%vreg149<def> = MOV64rm %vreg152, 1, %noreg, 0, %noreg; mem:LD8[%next_in135] GR64:%vreg149,%vreg152
4576B		%vreg149<def,tied1> = ADD64ri8 %vreg149<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR64:%vreg149
4592B		MOV64mr %vreg152<kill>, 1, %noreg, 0, %noreg, %vreg149<kill>; mem:ST8[%next_in135] GR64:%vreg152,%vreg149
4608B		%vreg145<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg145
4624B		%vreg144<def> = MOV64rm %vreg145<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm137] GR64:%vreg144,%vreg145
4640B		%vreg141<def> = MOV32rm %vreg144, 1, %noreg, 8, %noreg; mem:LD4[%avail_in138] GR32:%vreg141 GR64:%vreg144
4672B		%vreg141<def,tied1> = ADD32ri8 %vreg141<kill,tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg141
4688B		MOV32mr %vreg144<kill>, 1, %noreg, 8, %noreg, %vreg141<kill>; mem:ST4[%avail_in138] GR64:%vreg144 GR32:%vreg141
4704B		%vreg137<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg137
4720B		%vreg136<def> = MOV64rm %vreg137<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm140] GR64:%vreg136,%vreg137
4736B		%vreg133<def> = MOV32rm %vreg136, 1, %noreg, 12, %noreg; mem:LD4[%total_in_lo32141] GR32:%vreg133 GR64:%vreg136
4768B		%vreg133<def,tied1> = ADD32ri8 %vreg133<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg133
4784B		MOV32mr %vreg136<kill>, 1, %noreg, 12, %noreg, %vreg133<kill>; mem:ST4[%total_in_lo32141] GR64:%vreg136 GR32:%vreg133
4800B		%vreg129<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg129
4816B		%vreg128<def> = MOV64rm %vreg129<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm143] GR64:%vreg128,%vreg129
4832B		CMP32mi8 %vreg128<kill>, 1, %noreg, 12, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%total_in_lo32144] GR64:%vreg128
4848B		JNE_1 <BB#39>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#39 BB#38
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm134]
> %RCX<def> = MOV64rm %RAX, 1, %noreg, 0, %noreg; mem:LD8[%next_in135]
> %RCX<def,tied1> = ADD64ri8 %RCX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV64mr %RAX<kill>, 1, %noreg, 0, %noreg, %RCX<kill>; mem:ST8[%next_in135]
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm137]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 8, %noreg; mem:LD4[%avail_in138]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, -1, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 8, %noreg, %ECX<kill>; mem:ST4[%avail_in138]
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm140]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 12, %noreg; mem:LD4[%total_in_lo32141]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 12, %noreg, %ECX<kill>; mem:ST4[%total_in_lo32141]
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm143]
> CMP32mi8 %RAX<kill>, 1, %noreg, 12, %noreg, 0, %EFLAGS<imp-def>; mem:LD4[%total_in_lo32144]
> JNE_1 <BB#39>, %EFLAGS<imp-use,kill>
4864B	BB#38: derived from LLVM BB %if.then.147
	    Predecessors according to CFG: BB#37
4880B		%vreg161<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg161
4896B		%vreg160<def> = MOV64rm %vreg161<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm148] GR64:%vreg160,%vreg161
4912B		%vreg157<def> = MOV32rm %vreg160, 1, %noreg, 16, %noreg; mem:LD4[%total_in_hi32149] GR32:%vreg157 GR64:%vreg160
4944B		%vreg157<def,tied1> = ADD32ri8 %vreg157<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg157
4960B		MOV32mr %vreg160<kill>, 1, %noreg, 16, %noreg, %vreg157<kill>; mem:ST4[%total_in_hi32149] GR64:%vreg160 GR32:%vreg157
	    Successors according to CFG: BB#39
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RAX<def> = MOV64rm %RAX<kill>, 1, %noreg, 0, %noreg; mem:LD8[%strm148]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 16, %noreg; mem:LD4[%total_in_hi32149]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 16, %noreg, %ECX<kill>; mem:ST4[%total_in_hi32149]
4976B	BB#39: derived from LLVM BB %if.end.151
	    Predecessors according to CFG: BB#37 BB#38
4992B		%vreg167<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg167
5008B		%vreg165<def> = MOV32rm %vreg167, 1, %noreg, 16, %noreg; mem:LD4[%avail_in_expect152] GR32:%vreg165 GR64:%vreg167
5040B		%vreg165<def,tied1> = ADD32ri8 %vreg165<kill,tied0>, -1, %EFLAGS<imp-def,dead>; GR32:%vreg165
5056B		MOV32mr %vreg167<kill>, 1, %noreg, 16, %noreg, %vreg165<kill>; mem:ST4[%avail_in_expect152] GR64:%vreg167 GR32:%vreg165
5072B		JMP_1 <BB#21>
	    Successors according to CFG: BB#21
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 16, %noreg; mem:LD4[%avail_in_expect152]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, -1, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 16, %noreg, %ECX<kill>; mem:ST4[%avail_in_expect152]
> JMP_1 <BB#21>
5088B	BB#40: derived from LLVM BB %while.end.154
	    Predecessors according to CFG: BB#26 BB#24 BB#22
5104B		JMP_1 <BB#41>
	    Successors according to CFG: BB#41
> JMP_1 <BB#41>
5120B	BB#41: derived from LLVM BB %if.end.155
	    Predecessors according to CFG: BB#40 BB#19
5136B		%vreg321<def> = MOV64ri <ga:@copy_input_until_stop>; GR64:%vreg321
5168B		%vreg323<def> = MOV8rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD1[%progress_in] GR8:%vreg323
5184B		%vreg322<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg322
5200B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5216B		%RDI<def> = COPY %vreg321<kill>; GR64:%vreg321
5232B		%RSI<def> = COPY %vreg322<kill>; GR64:%vreg322
5248B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
5264B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5280B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5296B		STACKMAP 3, 0, %vreg323, ...; GR8:%vreg323
5312B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
5328B		%AL<def> = COPY %vreg323<kill>; GR8:%vreg323
5344B		RETQ %AL<imp-use>
> %RDI<def> = MOV64ri <ga:@copy_input_until_stop>
> %BL<def> = MOV8rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD1[%progress_in]
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 3, 0, %BL, ...
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %AL<def> = COPY %BL<kill>
> RETQ %AL<imp-use>
Computing live-in reg-units in ABI blocks.
0B	BB#0 DIL#0
Created 1 new intervals.
********** INTERVALS **********
DIL [0B,16r:0)[112r,144r:4)[336r,352r:3)[480r,496r:1)[640r,672r:2)  0@0B-phi 1@480r 2@640r 3@336r 4@112r
%vreg0 [16r,32r:0)  0@16r
%vreg1 [32r,224r:0)  0@32r
%vreg4 [240r,256r:0)  0@240r
%vreg5 [48r,64r:0)  0@48r
%vreg6 [64r,112r:0)  0@64r
%vreg7 [80r,128r:0)  0@80r
%vreg9 [304r,336r:0)  0@304r
%vreg10 [528r,544r:0)  0@528r
%vreg11 [544r,640r:0)  0@544r
%vreg12 [608r,656r:0)  0@608r
%vreg14 [448r,480r:0)  0@448r
RegMasks: 144r 352r 496r 672r
********** MACHINEINSTRS **********
# Machine code for function flush_RL: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=8, align=8, at location [SP+8]
Function Live Ins: %RDI in %vreg0

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI
16B		%vreg0<def> = COPY %RDI; GR64:%vreg0
32B		%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
48B		%vreg5<def> = MOV64ri <ga:@flush_RL>; GR64:%vreg5
64B		%vreg6<def> = COPY %vreg5; GR64:%vreg6,%vreg5
80B		%vreg7<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg7
96B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
112B		%RDI<def> = COPY %vreg6; GR64:%vreg6
128B		%RSI<def> = COPY %vreg7; GR64:%vreg7
144B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
160B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
192B		STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0] GR64:%vreg1
208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%s.addr] GR64:%vreg1
240B		%vreg4<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg4
256B		CMP32mi %vreg4, 1, %noreg, 92, %noreg, 256, %EFLAGS<imp-def>; mem:LD4[%state_in_ch] GR64:%vreg4
272B		JAE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

288B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
304B		%vreg9<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg9
320B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
336B		%RDI<def> = COPY %vreg9; GR64:%vreg9
352B		CALL64pcrel32 <ga:@add_pair_to_block>, <regmask>, %RSP<imp-use>, %RDI<imp-use>
368B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
384B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
400B		STACKMAP 1, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0]
416B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#2

432B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#1
448B		%vreg14<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg14
464B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
480B		%RDI<def> = COPY %vreg14; GR64:%vreg14
496B		CALL64pcrel32 <ga:@init_RL>, <regmask>, %RSP<imp-use>, %RDI<imp-use>
512B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
528B		%vreg10<def> = MOV64ri <ga:@flush_RL>; GR64:%vreg10
544B		%vreg11<def> = COPY %vreg10; GR64:%vreg11,%vreg10
560B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
576B		STACKMAP 2, 0, ...
592B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
608B		%vreg12<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg12
624B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
640B		%RDI<def> = COPY %vreg11; GR64:%vreg11
656B		%RSI<def> = COPY %vreg12; GR64:%vreg12
672B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
688B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
704B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
720B		STACKMAP 3, 0, ...
736B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
752B		RETQ

# End machine code for function flush_RL.

********** SIMPLE REGISTER COALESCING **********
********** Function: flush_RL
********** JOINING INTERVALS ***********
entry:
16B	%vreg0<def> = COPY %RDI; GR64:%vreg0
	Considering merging %vreg0 with %RDI
	Can only merge into reserved registers.
112B	%RDI<def> = COPY %vreg6; GR64:%vreg6
	Considering merging %vreg6 with %RDI
	Can only merge into reserved registers.
128B	%RSI<def> = COPY %vreg7; GR64:%vreg7
	Considering merging %vreg7 with %RSI
	Can only merge into reserved registers.
if.then:
336B	%RDI<def> = COPY %vreg9; GR64:%vreg9
	Considering merging %vreg9 with %RDI
	Can only merge into reserved registers.
if.end:
480B	%RDI<def> = COPY %vreg14; GR64:%vreg14
	Considering merging %vreg14 with %RDI
	Can only merge into reserved registers.
640B	%RDI<def> = COPY %vreg11; GR64:%vreg11
	Considering merging %vreg11 with %RDI
	Can only merge into reserved registers.
656B	%RSI<def> = COPY %vreg12; GR64:%vreg12
	Considering merging %vreg12 with %RSI
	Can only merge into reserved registers.
32B	%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
	Considering merging to GR64 with %vreg0 in %vreg1
		RHS = %vreg0 [16r,32r:0)  0@16r
		LHS = %vreg1 [32r,224r:0)  0@32r
		merge %vreg1:0@32r into %vreg0:0@16r --> @16r
		erased:	32r	%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
		updated: 16B	%vreg1<def> = COPY %RDI; GR64:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [16r,224r:0)  0@16r
64B	%vreg6<def> = COPY %vreg5; GR64:%vreg6,%vreg5
	Considering merging to GR64 with %vreg5 in %vreg6
		RHS = %vreg5 [48r,64r:0)  0@48r
		LHS = %vreg6 [64r,112r:0)  0@64r
		merge %vreg6:0@64r into %vreg5:0@48r --> @48r
		erased:	64r	%vreg6<def> = COPY %vreg5; GR64:%vreg6,%vreg5
		updated: 48B	%vreg6<def> = MOV64ri <ga:@flush_RL>; GR64:%vreg6
	Success: %vreg5 -> %vreg6
	Result = %vreg6 [48r,112r:0)  0@48r
544B	%vreg11<def> = COPY %vreg10; GR64:%vreg11,%vreg10
	Considering merging to GR64 with %vreg10 in %vreg11
		RHS = %vreg10 [528r,544r:0)  0@528r
		LHS = %vreg11 [544r,640r:0)  0@544r
		merge %vreg11:0@544r into %vreg10:0@528r --> @528r
		erased:	544r	%vreg11<def> = COPY %vreg10; GR64:%vreg11,%vreg10
		updated: 528B	%vreg11<def> = MOV64ri <ga:@flush_RL>; GR64:%vreg11
	Success: %vreg10 -> %vreg11
	Result = %vreg11 [528r,640r:0)  0@528r
112B	%RDI<def> = COPY %vreg6; GR64:%vreg6
	Considering merging %vreg6 with %RDI
	Can only merge into reserved registers.
640B	%RDI<def> = COPY %vreg11; GR64:%vreg11
	Considering merging %vreg11 with %RDI
	Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
DIL [0B,16r:0)[112r,144r:4)[336r,352r:3)[480r,496r:1)[640r,672r:2)  0@0B-phi 1@480r 2@640r 3@336r 4@112r
%vreg1 [16r,224r:0)  0@16r
%vreg4 [240r,256r:0)  0@240r
%vreg6 [48r,112r:0)  0@48r
%vreg7 [80r,128r:0)  0@80r
%vreg9 [304r,336r:0)  0@304r
%vreg11 [528r,640r:0)  0@528r
%vreg12 [608r,656r:0)  0@608r
%vreg14 [448r,480r:0)  0@448r
RegMasks: 144r 352r 496r 672r
********** MACHINEINSTRS **********
# Machine code for function flush_RL: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=8, align=8, at location [SP+8]
Function Live Ins: %RDI in %vreg0

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI
16B		%vreg1<def> = COPY %RDI; GR64:%vreg1
48B		%vreg6<def> = MOV64ri <ga:@flush_RL>; GR64:%vreg6
80B		%vreg7<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg7
96B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
112B		%RDI<def> = COPY %vreg6; GR64:%vreg6
128B		%RSI<def> = COPY %vreg7; GR64:%vreg7
144B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
160B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
192B		STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0] GR64:%vreg1
208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%s.addr] GR64:%vreg1
240B		%vreg4<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg4
256B		CMP32mi %vreg4, 1, %noreg, 92, %noreg, 256, %EFLAGS<imp-def>; mem:LD4[%state_in_ch] GR64:%vreg4
272B		JAE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

288B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
304B		%vreg9<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg9
320B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
336B		%RDI<def> = COPY %vreg9; GR64:%vreg9
352B		CALL64pcrel32 <ga:@add_pair_to_block>, <regmask>, %RSP<imp-use>, %RDI<imp-use>
368B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
384B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
400B		STACKMAP 1, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0]
416B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#2

432B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#1
448B		%vreg14<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg14
464B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
480B		%RDI<def> = COPY %vreg14; GR64:%vreg14
496B		CALL64pcrel32 <ga:@init_RL>, <regmask>, %RSP<imp-use>, %RDI<imp-use>
512B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
528B		%vreg11<def> = MOV64ri <ga:@flush_RL>; GR64:%vreg11
560B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
576B		STACKMAP 2, 0, ...
592B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
608B		%vreg12<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg12
624B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
640B		%RDI<def> = COPY %vreg11; GR64:%vreg11
656B		%RSI<def> = COPY %vreg12; GR64:%vreg12
672B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
688B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
704B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
720B		STACKMAP 3, 0, ...
736B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
752B		RETQ

# End machine code for function flush_RL.

********** GREEDY REGISTER ALLOCATION **********
********** Function: flush_RL
********** INTERVALS **********
DIL [0B,16r:0)[112r,144r:4)[336r,352r:3)[480r,496r:1)[640r,672r:2)  0@0B-phi 1@480r 2@640r 3@336r 4@112r
%vreg1 [16r,224r:0)  0@16r
%vreg4 [240r,256r:0)  0@240r
%vreg6 [48r,112r:0)  0@48r
%vreg7 [80r,128r:0)  0@80r
%vreg9 [304r,336r:0)  0@304r
%vreg11 [528r,640r:0)  0@528r
%vreg12 [608r,656r:0)  0@608r
%vreg14 [448r,480r:0)  0@448r
RegMasks: 144r 352r 496r 672r
********** MACHINEINSTRS **********
# Machine code for function flush_RL: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=8, align=8, at location [SP+8]
Function Live Ins: %RDI in %vreg0

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI
16B		%vreg1<def> = COPY %RDI; GR64:%vreg1
48B		%vreg6<def> = MOV64ri <ga:@flush_RL>; GR64:%vreg6
80B		%vreg7<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg7
96B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
112B		%RDI<def> = COPY %vreg6; GR64:%vreg6
128B		%RSI<def> = COPY %vreg7; GR64:%vreg7
144B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
160B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
192B		STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0] GR64:%vreg1
208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%s.addr] GR64:%vreg1
240B		%vreg4<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg4
256B		CMP32mi %vreg4, 1, %noreg, 92, %noreg, 256, %EFLAGS<imp-def>; mem:LD4[%state_in_ch] GR64:%vreg4
272B		JAE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1

288B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
304B		%vreg9<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg9
320B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
336B		%RDI<def> = COPY %vreg9; GR64:%vreg9
352B		CALL64pcrel32 <ga:@add_pair_to_block>, <regmask>, %RSP<imp-use>, %RDI<imp-use>
368B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
384B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
400B		STACKMAP 1, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0]
416B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#2

432B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#1
448B		%vreg14<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg14
464B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
480B		%RDI<def> = COPY %vreg14; GR64:%vreg14
496B		CALL64pcrel32 <ga:@init_RL>, <regmask>, %RSP<imp-use>, %RDI<imp-use>
512B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
528B		%vreg11<def> = MOV64ri <ga:@flush_RL>; GR64:%vreg11
560B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
576B		STACKMAP 2, 0, ...
592B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
608B		%vreg12<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg12
624B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
640B		%RDI<def> = COPY %vreg11; GR64:%vreg11
656B		%RSI<def> = COPY %vreg12; GR64:%vreg12
672B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
688B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
704B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
720B		STACKMAP 3, 0, ...
736B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
752B		RETQ

# End machine code for function flush_RL.


selectOrSplit GR64:%vreg1 [16r,224r:0)  0@16r w=4.983553e-03
hints: %RDI
missed hint %RDI
assigning %vreg1 to %RBX: BH [16r,224r:0)  0@16r BL [16r,224r:0)  0@16r

selectOrSplit GR64:%vreg6 [48r,112r:0)  0@48r w=2.176724e-03
hints: %RDI
assigning %vreg6 to %RDI: DIL [48r,112r:0)  0@48r

selectOrSplit GR64:%vreg7 [80r,128r:0)  0@80r w=4.508928e-03
hints: %RSI
assigning %vreg7 to %RSI: SIL [80r,128r:0)  0@80r

selectOrSplit GR64:%vreg9 [304r,336r:0)  0@304r w=2.337963e-03
hints: %RDI
assigning %vreg9 to %RDI: DIL [304r,336r:0)  0@304r

selectOrSplit GR64:%vreg14 [448r,480r:0)  0@448r w=4.675926e-03
hints: %RDI
assigning %vreg14 to %RDI: DIL [448r,480r:0)  0@448r

selectOrSplit GR64:%vreg11 [528r,640r:0)  0@528r w=1.972656e-03
hints: %RDI
assigning %vreg11 to %RDI: DIL [528r,640r:0)  0@528r

selectOrSplit GR64:%vreg12 [608r,656r:0)  0@608r w=4.508928e-03
hints: %RSI
assigning %vreg12 to %RSI: SIL [608r,656r:0)  0@608r

selectOrSplit GR64:%vreg4 [240r,256r:0)  0@240r w=inf
assigning %vreg4 to %RAX: AH [240r,256r:0)  0@240r AL [240r,256r:0)  0@240r

********** STACK TRANSFORMATION METADATA **********
********** Function: flush_RL
********** REGISTER MAP **********
[%vreg1 -> %RBX] GR64
[%vreg4 -> %RAX] GR64
[%vreg6 -> %RDI] GR64
[%vreg7 -> %RSI] GR64
[%vreg9 -> %RDI] GR64
[%vreg11 -> %RDI] GR64
[%vreg12 -> %RSI] GR64
[%vreg14 -> %RDI] GR64


Stackmap 0:
  STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0] GR64:%vreg1

%struct.EState* %s: in register %RBX (vreg 1)
%struct.EState** %s.addr: in stack slot 0 (size: 8)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0]

%struct.EState** %s.addr: in stack slot 0 (size: 8)

Duplicate operand locations:


Stackmap 2:
  STACKMAP 2, 0, ...


Duplicate operand locations:


Stackmap 3:
  STACKMAP 3, 0, ...


Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0] GR64:%vreg1
  -> Call instruction SlotIndex 144B, searching vregs 0 -> 15 and stack slots -1 -> 1

  STACKMAP 1, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0]
  -> Call instruction SlotIndex 352B, searching vregs 0 -> 15 and stack slots -1 -> 1

  STACKMAP 2, 0, ...
  -> Call instruction SlotIndex 496B, searching vregs 0 -> 15 and stack slots -1 -> 1

  STACKMAP 3, 0, ...
  -> Call instruction SlotIndex 672B, searching vregs 0 -> 15 and stack slots -1 -> 1

********** REWRITE VIRTUAL REGISTERS **********
********** Function: flush_RL
********** REGISTER MAP **********
[%vreg1 -> %RBX] GR64
[%vreg4 -> %RAX] GR64
[%vreg6 -> %RDI] GR64
[%vreg7 -> %RSI] GR64
[%vreg9 -> %RDI] GR64
[%vreg11 -> %RDI] GR64
[%vreg12 -> %RSI] GR64
[%vreg14 -> %RDI] GR64

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI
16B		%vreg1<def> = COPY %RDI; GR64:%vreg1
48B		%vreg6<def> = MOV64ri <ga:@flush_RL>; GR64:%vreg6
80B		%vreg7<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg7
96B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
112B		%RDI<def> = COPY %vreg6<kill>; GR64:%vreg6
128B		%RSI<def> = COPY %vreg7<kill>; GR64:%vreg7
144B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
160B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
192B		STACKMAP 0, 0, %vreg1, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0] GR64:%vreg1
208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1<kill>; mem:ST8[%s.addr] GR64:%vreg1
240B		%vreg4<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg4
256B		CMP32mi %vreg4<kill>, 1, %noreg, 92, %noreg, 256, %EFLAGS<imp-def>; mem:LD4[%state_in_ch] GR64:%vreg4
272B		JAE_1 <BB#2>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#2 BB#1
> %RBX<def> = COPY %RDI
> %RDI<def> = MOV64ri <ga:@flush_RL>
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 0, 0, %RBX, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %RBX<kill>; mem:ST8[%s.addr]
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> CMP32mi %RAX<kill>, 1, %noreg, 92, %noreg, 256, %EFLAGS<imp-def>; mem:LD4[%state_in_ch]
> JAE_1 <BB#2>, %EFLAGS<imp-use,kill>
288B	BB#1: derived from LLVM BB %if.then
	    Predecessors according to CFG: BB#0
304B		%vreg9<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg9
320B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
336B		%RDI<def> = COPY %vreg9<kill>; GR64:%vreg9
352B		CALL64pcrel32 <ga:@add_pair_to_block>, <regmask>, %RSP<imp-use>, %RDI<imp-use>
368B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
384B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
400B		STACKMAP 1, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0]
416B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	    Successors according to CFG: BB#2
> %RDI<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@add_pair_to_block>, <regmask>, %RSP<imp-use>, %RDI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 1, 0, 0, <fi#0>, 0, ...; mem:LD8[FixedStack0]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
432B	BB#2: derived from LLVM BB %if.end
	    Predecessors according to CFG: BB#0 BB#1
448B		%vreg14<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg14
464B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
480B		%RDI<def> = COPY %vreg14<kill>; GR64:%vreg14
496B		CALL64pcrel32 <ga:@init_RL>, <regmask>, %RSP<imp-use>, %RDI<imp-use>
512B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
528B		%vreg11<def> = MOV64ri <ga:@flush_RL>; GR64:%vreg11
560B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
576B		STACKMAP 2, 0, ...
592B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
608B		%vreg12<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg12
624B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
640B		%RDI<def> = COPY %vreg11<kill>; GR64:%vreg11
656B		%RSI<def> = COPY %vreg12<kill>; GR64:%vreg12
672B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
688B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
704B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
720B		STACKMAP 3, 0, ...
736B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
752B		RETQ
> %RDI<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@init_RL>, <regmask>, %RSP<imp-use>, %RDI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = MOV64ri <ga:@flush_RL>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 2, 0, ...
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 3, 0, ...
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> RETQ
Computing live-in reg-units in ABI blocks.
0B	BB#0 DIL#0
Created 1 new intervals.
********** INTERVALS **********
DIL [0B,16r:0)[112r,144r:2)[3424r,3456r:1)  0@0B-phi 1@3424r 2@112r
%vreg0 [16r,32r:0)  0@16r
%vreg1 [32r,224r:0)  0@32r
%vreg4 [272r,288r:0)  0@272r
%vreg6 [256r,272r:0)  0@256r
%vreg7 [240r,256r:0)  0@240r
%vreg8 [48r,64r:0)  0@48r
%vreg9 [64r,112r:0)  0@64r
%vreg10 [80r,128r:0)  0@80r
%vreg14 [352r,368r:0)  0@352r
%vreg15 [336r,368r:0)  0@336r
%vreg16 [880r,1056r:0)  0@880r
%vreg17 [800r,848r:0)  0@800r
%vreg18 [816r,832r:0)  0@816r
%vreg19 [832r,848r:0)  0@832r
%vreg20 [864r,880r:0)  0@864r
%vreg21 [896r,912r:0)[912r,912d:1)  0@896r 1@912r
%vreg22 [976r,992r:0)[992r,992d:1)  0@976r 1@992r
%vreg23 [1056r,1072r:0)[1072r,1072d:1)  0@1056r 1@1072r
%vreg27 [2208r,2224r:0)[2224r,2240r:1)  0@2208r 1@2224r
%vreg28 [2192r,2208r:0)  0@2192r
%vreg29 [2176r,2240r:0)  0@2176r
%vreg34 [2144r,2160r:0)  0@2144r
%vreg35 [2128r,2144r:0)  0@2128r
%vreg37 [2112r,2160r:0)  0@2112r
%vreg39 [2096r,2112r:0)  0@2096r
%vreg40 [2080r,2160r:0)  0@2080r
%vreg44 [2032r,2048r:0)[2048r,2064r:1)  0@2032r 1@2048r
%vreg45 [2016r,2032r:0)  0@2016r
%vreg46 [2000r,2064r:0)  0@2000r
%vreg51 [1968r,1984r:0)  0@1968r
%vreg52 [1952r,1968r:0)  0@1952r
%vreg54 [1936r,1984r:0)  0@1936r
%vreg56 [1920r,1936r:0)  0@1920r
%vreg57 [1904r,1984r:0)  0@1904r
%vreg61 [1856r,1872r:0)[1872r,1888r:1)  0@1856r 1@1872r
%vreg62 [1840r,1856r:0)  0@1840r
%vreg63 [1824r,1888r:0)  0@1824r
%vreg68 [1792r,1808r:0)  0@1792r
%vreg69 [1776r,1792r:0)  0@1776r
%vreg71 [1760r,1808r:0)  0@1760r
%vreg73 [1744r,1760r:0)  0@1744r
%vreg74 [1728r,1808r:0)  0@1728r
%vreg78 [1648r,1664r:0)[1664r,1680r:1)  0@1648r 1@1664r
%vreg79 [1632r,1648r:0)  0@1632r
%vreg80 [1616r,1680r:0)  0@1616r
%vreg85 [1584r,1600r:0)  0@1584r
%vreg86 [1568r,1584r:0)  0@1568r
%vreg88 [1552r,1600r:0)  0@1552r
%vreg90 [1536r,1552r:0)  0@1536r
%vreg91 [1520r,1600r:0)  0@1520r
%vreg95 [1472r,1488r:0)[1488r,1504r:1)  0@1472r 1@1488r
%vreg96 [1456r,1472r:0)  0@1456r
%vreg97 [1440r,1504r:0)  0@1440r
%vreg102 [1408r,1424r:0)  0@1408r
%vreg103 [1392r,1408r:0)  0@1392r
%vreg105 [1376r,1424r:0)  0@1376r
%vreg107 [1360r,1376r:0)  0@1360r
%vreg108 [1344r,1424r:0)  0@1344r
%vreg112 [1264r,1280r:0)[1280r,1296r:1)  0@1264r 1@1280r
%vreg113 [1248r,1264r:0)  0@1248r
%vreg114 [1232r,1296r:0)  0@1232r
%vreg119 [1200r,1216r:0)  0@1200r
%vreg120 [1184r,1200r:0)  0@1184r
%vreg122 [1168r,1216r:0)  0@1168r
%vreg124 [1152r,1168r:0)  0@1152r
%vreg125 [1136r,1216r:0)  0@1136r
%vreg129 [3296r,3312r:0)[3312r,3328r:1)  0@3296r 1@3312r
%vreg130 [3280r,3296r:0)  0@3280r
%vreg131 [3264r,3328r:0)  0@3264r
%vreg136 [3232r,3248r:0)  0@3232r
%vreg137 [3216r,3232r:0)  0@3216r
%vreg139 [3200r,3248r:0)  0@3200r
%vreg141 [3184r,3200r:0)  0@3184r
%vreg143 [3168r,3248r:0)  0@3168r
%vreg145 [3136r,3152r:0)[3152r,3168r:1)  0@3136r 1@3152r
%vreg147 [3120r,3136r:0)  0@3120r
%vreg148 [3104r,3120r:0)  0@3104r
%vreg152 [3056r,3072r:0)[3072r,3088r:1)  0@3056r 1@3072r
%vreg153 [3040r,3056r:0)  0@3040r
%vreg154 [3024r,3088r:0)  0@3024r
%vreg159 [2992r,3008r:0)  0@2992r
%vreg160 [2976r,2992r:0)  0@2976r
%vreg162 [2960r,3008r:0)  0@2960r
%vreg164 [2944r,2960r:0)  0@2944r
%vreg165 [2928r,3008r:0)  0@2928r
%vreg169 [2880r,2896r:0)[2896r,2912r:1)  0@2880r 1@2896r
%vreg170 [2864r,2880r:0)  0@2864r
%vreg171 [2848r,2912r:0)  0@2848r
%vreg176 [2816r,2832r:0)  0@2816r
%vreg177 [2800r,2816r:0)  0@2800r
%vreg179 [2784r,2832r:0)  0@2784r
%vreg181 [2768r,2784r:0)  0@2768r
%vreg182 [2752r,2832r:0)  0@2752r
%vreg186 [2704r,2720r:0)[2720r,2736r:1)  0@2704r 1@2720r
%vreg187 [2688r,2704r:0)  0@2688r
%vreg188 [2672r,2736r:0)  0@2672r
%vreg193 [2640r,2656r:0)  0@2640r
%vreg194 [2624r,2640r:0)  0@2624r
%vreg196 [2608r,2656r:0)  0@2608r
%vreg198 [2592r,2608r:0)  0@2592r
%vreg199 [2576r,2656r:0)  0@2576r
%vreg203 [2528r,2544r:0)[2544r,2560r:1)  0@2528r 1@2544r
%vreg204 [2512r,2528r:0)  0@2512r
%vreg205 [2496r,2560r:0)  0@2496r
%vreg210 [2464r,2480r:0)  0@2464r
%vreg211 [2448r,2464r:0)  0@2448r
%vreg213 [2432r,2480r:0)  0@2432r
%vreg215 [2416r,2432r:0)  0@2416r
%vreg216 [2400r,2480r:0)  0@2400r
%vreg219 [2368r,2384r:0)  0@2368r
%vreg221 [2352r,2384r:0)  0@2352r
%vreg223 [2320r,2336r:0)[2336r,2352r:1)  0@2320r 1@2336r
%vreg225 [2304r,2320r:0)  0@2304r
%vreg226 [2288r,2304r:0)  0@2288r
%vreg227 [3360r,3376r:0)  0@3360r
%vreg228 [3376r,3424r:0)  0@3376r
%vreg229 [3392r,3440r:0)  0@3392r
%vreg232 [656r,672r:0)  0@656r
%vreg235 [624r,640r:0)[640r,672r:1)  0@624r 1@640r
%vreg238 [592r,608r:0)  0@592r
%vreg239 [608r,640r:0)  0@608r
%vreg242 [560r,576r:0)[576r,592r:1)  0@560r 1@576r
%vreg244 [544r,576r:0)  0@544r
%vreg246 [512r,528r:0)[528r,560r:1)  0@512r 1@528r
%vreg248 [496r,512r:0)  0@496r
%vreg249 [480r,496r:0)  0@480r
%vreg251 [448r,464r:0)[464r,624r:1)  0@448r 1@464r
%vreg253 [432r,448r:0)  0@432r
%vreg254 [416r,432r:0)  0@416r
%vreg257 [720r,736r:0)[736r,752r:1)  0@720r 1@736r
%vreg258 [704r,720r:0)  0@704r
RegMasks: 144r 3456r
********** MACHINEINSTRS **********
# Machine code for function add_pair_to_block: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=8, align=8, at location [SP+8]
  fi#1: size=4, align=4, at location [SP+8]
  fi#2: size=1, align=1, at location [SP+8]
Function Live Ins: %RDI in %vreg0

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI
16B		%vreg0<def> = COPY %RDI; GR64:%vreg0
32B		%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
48B		%vreg8<def> = MOV64ri <ga:@add_pair_to_block>; GR64:%vreg8
64B		%vreg9<def> = COPY %vreg8; GR64:%vreg9,%vreg8
80B		%vreg10<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg10
96B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
112B		%RDI<def> = COPY %vreg9; GR64:%vreg9
128B		%RSI<def> = COPY %vreg10; GR64:%vreg10
144B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
160B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
192B		STACKMAP 0, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack1](align=4) LD8[FixedStack0] GR64:%vreg1
208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%s.addr] GR64:%vreg1
240B		%vreg7<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg7
256B		%vreg6<def> = MOV32rm %vreg7, 1, %noreg, 92, %noreg; mem:LD4[%state_in_ch] GR32:%vreg6 GR64:%vreg7
272B		%vreg4<def> = COPY %vreg6:sub_8bit; GR8:%vreg4 GR32:%vreg6
288B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg4; mem:ST1[%ch] GR8:%vreg4
304B		MOV32mi <fi#1>, 1, %noreg, 0, %noreg, 0; mem:ST4[%i]
	    Successors according to CFG: BB#1

320B	BB#1: derived from LLVM BB %for.cond
	    Predecessors according to CFG: BB#0 BB#3
336B		%vreg15<def> = MOV32rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD4[%i] GR32:%vreg15
352B		%vreg14<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg14
368B		CMP32rm %vreg15, %vreg14, 1, %noreg, 96, %noreg, %EFLAGS<imp-def>; mem:LD4[%state_in_len] GR32:%vreg15 GR64:%vreg14
384B		JGE_1 <BB#4>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#4 BB#2

400B	BB#2: derived from LLVM BB %for.body
	    Predecessors according to CFG: BB#1
416B		%vreg254<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg254
432B		%vreg253<def> = MOV32rm %vreg254, 1, %noreg, 648, %noreg; mem:LD4[%blockCRC] GR32:%vreg253 GR64:%vreg254
448B		%vreg251<def> = COPY %vreg253; GR32:%vreg251,%vreg253
464B		%vreg251<def,tied1> = SHL32ri %vreg251<tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg251
480B		%vreg249<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg249
496B		%vreg248<def> = MOV32rm %vreg249, 1, %noreg, 648, %noreg; mem:LD4[%blockCRC2] GR32:%vreg248 GR64:%vreg249
512B		%vreg246<def> = COPY %vreg248; GR32:%vreg246,%vreg248
528B		%vreg246<def,tied1> = SHR32ri %vreg246<tied0>, 24, %EFLAGS<imp-def,dead>; GR32:%vreg246
544B		%vreg244<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%ch] GR32:%vreg244
560B		%vreg242<def> = COPY %vreg246; GR32:%vreg242,%vreg246
576B		%vreg242<def,tied1> = XOR32rr %vreg242<tied0>, %vreg244, %EFLAGS<imp-def,dead>; GR32:%vreg242,%vreg244
592B		%vreg238<def> = MOV32rr %vreg242; GR32:%vreg238,%vreg242
608B		%vreg239<def> = SUBREG_TO_REG 0, %vreg238, 4; GR64_NOSP:%vreg239 GR32:%vreg238
624B		%vreg235<def> = COPY %vreg251; GR32:%vreg235,%vreg251
640B		%vreg235<def,tied1> = XOR32rm %vreg235<tied0>, %noreg, 4, %vreg239, <ga:@BZ2_crc32Table>, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%arrayidx] GR32:%vreg235 GR64_NOSP:%vreg239
656B		%vreg232<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg232
672B		MOV32mr %vreg232, 1, %noreg, 648, %noreg, %vreg235; mem:ST4[%blockCRC5] GR64:%vreg232 GR32:%vreg235
	    Successors according to CFG: BB#3

688B	BB#3: derived from LLVM BB %for.inc
	    Predecessors according to CFG: BB#2
704B		%vreg258<def> = MOV32rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD4[%i] GR32:%vreg258
720B		%vreg257<def> = COPY %vreg258; GR32:%vreg257,%vreg258
736B		%vreg257<def,tied1> = ADD32ri8 %vreg257<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg257
752B		MOV32mr <fi#1>, 1, %noreg, 0, %noreg, %vreg257; mem:ST4[%i] GR32:%vreg257
768B		JMP_1 <BB#1>
	    Successors according to CFG: BB#1

784B	BB#4: derived from LLVM BB %for.end
	    Predecessors according to CFG: BB#1
800B		%vreg17<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg17
816B		%vreg18<def> = MOV32rm %vreg17, 1, %noreg, 92, %noreg; mem:LD4[%state_in_ch6] GR32:%vreg18 GR64:%vreg17
832B		%vreg19<def> = SUBREG_TO_REG 0, %vreg18, 4; GR64_NOSP:%vreg19 GR32:%vreg18
848B		MOV8mi %vreg17, 1, %vreg19, 128, %noreg, 1; mem:ST1[%arrayidx8] GR64:%vreg17 GR64_NOSP:%vreg19
864B		%vreg20<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg20
880B		%vreg16<def> = MOV32rm %vreg20, 1, %noreg, 96, %noreg; mem:LD4[%state_in_len9] GR32:%vreg16 GR64:%vreg20
896B		%vreg21<def> = COPY %vreg16; GR32:%vreg21,%vreg16
912B		%vreg21<def,dead,tied1> = SUB32ri8 %vreg21<tied0>, 1, %EFLAGS<imp-def>; GR32:%vreg21
928B		JE_1 <BB#7>, %EFLAGS<imp-use,kill>
944B		JMP_1 <BB#5>
	    Successors according to CFG: BB#7 BB#5

960B	BB#5: derived from LLVM BB %for.end
	    Predecessors according to CFG: BB#4
976B		%vreg22<def> = COPY %vreg16; GR32:%vreg22,%vreg16
992B		%vreg22<def,dead,tied1> = SUB32ri8 %vreg22<tied0>, 2, %EFLAGS<imp-def>; GR32:%vreg22
1008B		JE_1 <BB#8>, %EFLAGS<imp-use,kill>
1024B		JMP_1 <BB#6>
	    Successors according to CFG: BB#8 BB#6

1040B	BB#6: derived from LLVM BB %for.end
	    Predecessors according to CFG: BB#5
1056B		%vreg23<def> = COPY %vreg16; GR32:%vreg23,%vreg16
1072B		%vreg23<def,dead,tied1> = SUB32ri8 %vreg23<tied0>, 3, %EFLAGS<imp-def>; GR32:%vreg23
1088B		JE_1 <BB#9>, %EFLAGS<imp-use,kill>
1104B		JMP_1 <BB#10>
	    Successors according to CFG: BB#9 BB#10

1120B	BB#7: derived from LLVM BB %sw.bb
	    Predecessors according to CFG: BB#4
1136B		%vreg125<def> = MOV8rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%ch] GR8:%vreg125
1152B		%vreg124<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg124
1168B		%vreg122<def> = MOVSX64rm32 %vreg124, 1, %noreg, 108, %noreg; mem:LD4[%nblock] GR64_NOSP:%vreg122 GR64:%vreg124
1184B		%vreg120<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg120
1200B		%vreg119<def> = MOV64rm %vreg120, 1, %noreg, 64, %noreg; mem:LD8[%block] GR64:%vreg119,%vreg120
1216B		MOV8mr %vreg119, 1, %vreg122, 0, %noreg, %vreg125; mem:ST1[%arrayidx11] GR64:%vreg119 GR64_NOSP:%vreg122 GR8:%vreg125
1232B		%vreg114<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg114
1248B		%vreg113<def> = MOV32rm %vreg114, 1, %noreg, 108, %noreg; mem:LD4[%nblock12] GR32:%vreg113 GR64:%vreg114
1264B		%vreg112<def> = COPY %vreg113; GR32:%vreg112,%vreg113
1280B		%vreg112<def,tied1> = ADD32ri8 %vreg112<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg112
1296B		MOV32mr %vreg114, 1, %noreg, 108, %noreg, %vreg112; mem:ST4[%nblock12] GR64:%vreg114 GR32:%vreg112
1312B		JMP_1 <BB#11>
	    Successors according to CFG: BB#11

1328B	BB#8: derived from LLVM BB %sw.bb.14
	    Predecessors according to CFG: BB#5
1344B		%vreg108<def> = MOV8rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%ch] GR8:%vreg108
1360B		%vreg107<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg107
1376B		%vreg105<def> = MOVSX64rm32 %vreg107, 1, %noreg, 108, %noreg; mem:LD4[%nblock15] GR64_NOSP:%vreg105 GR64:%vreg107
1392B		%vreg103<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg103
1408B		%vreg102<def> = MOV64rm %vreg103, 1, %noreg, 64, %noreg; mem:LD8[%block17] GR64:%vreg102,%vreg103
1424B		MOV8mr %vreg102, 1, %vreg105, 0, %noreg, %vreg108; mem:ST1[%arrayidx18] GR64:%vreg102 GR64_NOSP:%vreg105 GR8:%vreg108
1440B		%vreg97<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg97
1456B		%vreg96<def> = MOV32rm %vreg97, 1, %noreg, 108, %noreg; mem:LD4[%nblock19] GR32:%vreg96 GR64:%vreg97
1472B		%vreg95<def> = COPY %vreg96; GR32:%vreg95,%vreg96
1488B		%vreg95<def,tied1> = ADD32ri8 %vreg95<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg95
1504B		MOV32mr %vreg97, 1, %noreg, 108, %noreg, %vreg95; mem:ST4[%nblock19] GR64:%vreg97 GR32:%vreg95
1520B		%vreg91<def> = MOV8rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%ch] GR8:%vreg91
1536B		%vreg90<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg90
1552B		%vreg88<def> = MOVSX64rm32 %vreg90, 1, %noreg, 108, %noreg; mem:LD4[%nblock21] GR64_NOSP:%vreg88 GR64:%vreg90
1568B		%vreg86<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg86
1584B		%vreg85<def> = MOV64rm %vreg86, 1, %noreg, 64, %noreg; mem:LD8[%block23] GR64:%vreg85,%vreg86
1600B		MOV8mr %vreg85, 1, %vreg88, 0, %noreg, %vreg91; mem:ST1[%arrayidx24] GR64:%vreg85 GR64_NOSP:%vreg88 GR8:%vreg91
1616B		%vreg80<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg80
1632B		%vreg79<def> = MOV32rm %vreg80, 1, %noreg, 108, %noreg; mem:LD4[%nblock25] GR32:%vreg79 GR64:%vreg80
1648B		%vreg78<def> = COPY %vreg79; GR32:%vreg78,%vreg79
1664B		%vreg78<def,tied1> = ADD32ri8 %vreg78<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg78
1680B		MOV32mr %vreg80, 1, %noreg, 108, %noreg, %vreg78; mem:ST4[%nblock25] GR64:%vreg80 GR32:%vreg78
1696B		JMP_1 <BB#11>
	    Successors according to CFG: BB#11

1712B	BB#9: derived from LLVM BB %sw.bb.27
	    Predecessors according to CFG: BB#6
1728B		%vreg74<def> = MOV8rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%ch] GR8:%vreg74
1744B		%vreg73<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg73
1760B		%vreg71<def> = MOVSX64rm32 %vreg73, 1, %noreg, 108, %noreg; mem:LD4[%nblock28] GR64_NOSP:%vreg71 GR64:%vreg73
1776B		%vreg69<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg69
1792B		%vreg68<def> = MOV64rm %vreg69, 1, %noreg, 64, %noreg; mem:LD8[%block30] GR64:%vreg68,%vreg69
1808B		MOV8mr %vreg68, 1, %vreg71, 0, %noreg, %vreg74; mem:ST1[%arrayidx31] GR64:%vreg68 GR64_NOSP:%vreg71 GR8:%vreg74
1824B		%vreg63<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg63
1840B		%vreg62<def> = MOV32rm %vreg63, 1, %noreg, 108, %noreg; mem:LD4[%nblock32] GR32:%vreg62 GR64:%vreg63
1856B		%vreg61<def> = COPY %vreg62; GR32:%vreg61,%vreg62
1872B		%vreg61<def,tied1> = ADD32ri8 %vreg61<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg61
1888B		MOV32mr %vreg63, 1, %noreg, 108, %noreg, %vreg61; mem:ST4[%nblock32] GR64:%vreg63 GR32:%vreg61
1904B		%vreg57<def> = MOV8rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%ch] GR8:%vreg57
1920B		%vreg56<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg56
1936B		%vreg54<def> = MOVSX64rm32 %vreg56, 1, %noreg, 108, %noreg; mem:LD4[%nblock34] GR64_NOSP:%vreg54 GR64:%vreg56
1952B		%vreg52<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg52
1968B		%vreg51<def> = MOV64rm %vreg52, 1, %noreg, 64, %noreg; mem:LD8[%block36] GR64:%vreg51,%vreg52
1984B		MOV8mr %vreg51, 1, %vreg54, 0, %noreg, %vreg57; mem:ST1[%arrayidx37] GR64:%vreg51 GR64_NOSP:%vreg54 GR8:%vreg57
2000B		%vreg46<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg46
2016B		%vreg45<def> = MOV32rm %vreg46, 1, %noreg, 108, %noreg; mem:LD4[%nblock38] GR32:%vreg45 GR64:%vreg46
2032B		%vreg44<def> = COPY %vreg45; GR32:%vreg44,%vreg45
2048B		%vreg44<def,tied1> = ADD32ri8 %vreg44<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg44
2064B		MOV32mr %vreg46, 1, %noreg, 108, %noreg, %vreg44; mem:ST4[%nblock38] GR64:%vreg46 GR32:%vreg44
2080B		%vreg40<def> = MOV8rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%ch] GR8:%vreg40
2096B		%vreg39<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg39
2112B		%vreg37<def> = MOVSX64rm32 %vreg39, 1, %noreg, 108, %noreg; mem:LD4[%nblock40] GR64_NOSP:%vreg37 GR64:%vreg39
2128B		%vreg35<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg35
2144B		%vreg34<def> = MOV64rm %vreg35, 1, %noreg, 64, %noreg; mem:LD8[%block42] GR64:%vreg34,%vreg35
2160B		MOV8mr %vreg34, 1, %vreg37, 0, %noreg, %vreg40; mem:ST1[%arrayidx43] GR64:%vreg34 GR64_NOSP:%vreg37 GR8:%vreg40
2176B		%vreg29<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg29
2192B		%vreg28<def> = MOV32rm %vreg29, 1, %noreg, 108, %noreg; mem:LD4[%nblock44] GR32:%vreg28 GR64:%vreg29
2208B		%vreg27<def> = COPY %vreg28; GR32:%vreg27,%vreg28
2224B		%vreg27<def,tied1> = ADD32ri8 %vreg27<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg27
2240B		MOV32mr %vreg29, 1, %noreg, 108, %noreg, %vreg27; mem:ST4[%nblock44] GR64:%vreg29 GR32:%vreg27
2256B		JMP_1 <BB#11>
	    Successors according to CFG: BB#11

2272B	BB#10: derived from LLVM BB %sw.default
	    Predecessors according to CFG: BB#6
2288B		%vreg226<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg226
2304B		%vreg225<def> = MOV32rm %vreg226, 1, %noreg, 96, %noreg; mem:LD4[%state_in_len46] GR32:%vreg225 GR64:%vreg226
2320B		%vreg223<def> = COPY %vreg225; GR32:%vreg223,%vreg225
2336B		%vreg223<def,tied1> = SUB32ri8 %vreg223<tied0>, 4, %EFLAGS<imp-def,dead>; GR32:%vreg223
2352B		%vreg221<def> = MOVSX64rr32 %vreg223; GR64_NOSP:%vreg221 GR32:%vreg223
2368B		%vreg219<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg219
2384B		MOV8mi %vreg219, 1, %vreg221, 128, %noreg, 1; mem:ST1[%arrayidx49] GR64:%vreg219 GR64_NOSP:%vreg221
2400B		%vreg216<def> = MOV8rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%ch] GR8:%vreg216
2416B		%vreg215<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg215
2432B		%vreg213<def> = MOVSX64rm32 %vreg215, 1, %noreg, 108, %noreg; mem:LD4[%nblock50] GR64_NOSP:%vreg213 GR64:%vreg215
2448B		%vreg211<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg211
2464B		%vreg210<def> = MOV64rm %vreg211, 1, %noreg, 64, %noreg; mem:LD8[%block52] GR64:%vreg210,%vreg211
2480B		MOV8mr %vreg210, 1, %vreg213, 0, %noreg, %vreg216; mem:ST1[%arrayidx53] GR64:%vreg210 GR64_NOSP:%vreg213 GR8:%vreg216
2496B		%vreg205<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg205
2512B		%vreg204<def> = MOV32rm %vreg205, 1, %noreg, 108, %noreg; mem:LD4[%nblock54] GR32:%vreg204 GR64:%vreg205
2528B		%vreg203<def> = COPY %vreg204; GR32:%vreg203,%vreg204
2544B		%vreg203<def,tied1> = ADD32ri8 %vreg203<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg203
2560B		MOV32mr %vreg205, 1, %noreg, 108, %noreg, %vreg203; mem:ST4[%nblock54] GR64:%vreg205 GR32:%vreg203
2576B		%vreg199<def> = MOV8rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%ch] GR8:%vreg199
2592B		%vreg198<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg198
2608B		%vreg196<def> = MOVSX64rm32 %vreg198, 1, %noreg, 108, %noreg; mem:LD4[%nblock56] GR64_NOSP:%vreg196 GR64:%vreg198
2624B		%vreg194<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg194
2640B		%vreg193<def> = MOV64rm %vreg194, 1, %noreg, 64, %noreg; mem:LD8[%block58] GR64:%vreg193,%vreg194
2656B		MOV8mr %vreg193, 1, %vreg196, 0, %noreg, %vreg199; mem:ST1[%arrayidx59] GR64:%vreg193 GR64_NOSP:%vreg196 GR8:%vreg199
2672B		%vreg188<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg188
2688B		%vreg187<def> = MOV32rm %vreg188, 1, %noreg, 108, %noreg; mem:LD4[%nblock60] GR32:%vreg187 GR64:%vreg188
2704B		%vreg186<def> = COPY %vreg187; GR32:%vreg186,%vreg187
2720B		%vreg186<def,tied1> = ADD32ri8 %vreg186<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg186
2736B		MOV32mr %vreg188, 1, %noreg, 108, %noreg, %vreg186; mem:ST4[%nblock60] GR64:%vreg188 GR32:%vreg186
2752B		%vreg182<def> = MOV8rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%ch] GR8:%vreg182
2768B		%vreg181<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg181
2784B		%vreg179<def> = MOVSX64rm32 %vreg181, 1, %noreg, 108, %noreg; mem:LD4[%nblock62] GR64_NOSP:%vreg179 GR64:%vreg181
2800B		%vreg177<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg177
2816B		%vreg176<def> = MOV64rm %vreg177, 1, %noreg, 64, %noreg; mem:LD8[%block64] GR64:%vreg176,%vreg177
2832B		MOV8mr %vreg176, 1, %vreg179, 0, %noreg, %vreg182; mem:ST1[%arrayidx65] GR64:%vreg176 GR64_NOSP:%vreg179 GR8:%vreg182
2848B		%vreg171<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg171
2864B		%vreg170<def> = MOV32rm %vreg171, 1, %noreg, 108, %noreg; mem:LD4[%nblock66] GR32:%vreg170 GR64:%vreg171
2880B		%vreg169<def> = COPY %vreg170; GR32:%vreg169,%vreg170
2896B		%vreg169<def,tied1> = ADD32ri8 %vreg169<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg169
2912B		MOV32mr %vreg171, 1, %noreg, 108, %noreg, %vreg169; mem:ST4[%nblock66] GR64:%vreg171 GR32:%vreg169
2928B		%vreg165<def> = MOV8rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%ch] GR8:%vreg165
2944B		%vreg164<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg164
2960B		%vreg162<def> = MOVSX64rm32 %vreg164, 1, %noreg, 108, %noreg; mem:LD4[%nblock68] GR64_NOSP:%vreg162 GR64:%vreg164
2976B		%vreg160<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg160
2992B		%vreg159<def> = MOV64rm %vreg160, 1, %noreg, 64, %noreg; mem:LD8[%block70] GR64:%vreg159,%vreg160
3008B		MOV8mr %vreg159, 1, %vreg162, 0, %noreg, %vreg165; mem:ST1[%arrayidx71] GR64:%vreg159 GR64_NOSP:%vreg162 GR8:%vreg165
3024B		%vreg154<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg154
3040B		%vreg153<def> = MOV32rm %vreg154, 1, %noreg, 108, %noreg; mem:LD4[%nblock72] GR32:%vreg153 GR64:%vreg154
3056B		%vreg152<def> = COPY %vreg153; GR32:%vreg152,%vreg153
3072B		%vreg152<def,tied1> = ADD32ri8 %vreg152<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg152
3088B		MOV32mr %vreg154, 1, %noreg, 108, %noreg, %vreg152; mem:ST4[%nblock72] GR64:%vreg154 GR32:%vreg152
3104B		%vreg148<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg148
3120B		%vreg147<def> = MOV32rm %vreg148, 1, %noreg, 96, %noreg; mem:LD4[%state_in_len74] GR32:%vreg147 GR64:%vreg148
3136B		%vreg145<def> = COPY %vreg147; GR32:%vreg145,%vreg147
3152B		%vreg145<def,tied1> = SUB32ri8 %vreg145<tied0>, 4, %EFLAGS<imp-def,dead>; GR32:%vreg145
3168B		%vreg143<def> = COPY %vreg145:sub_8bit; GR8:%vreg143 GR32:%vreg145
3184B		%vreg141<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg141
3200B		%vreg139<def> = MOVSX64rm32 %vreg141, 1, %noreg, 108, %noreg; mem:LD4[%nblock77] GR64_NOSP:%vreg139 GR64:%vreg141
3216B		%vreg137<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg137
3232B		%vreg136<def> = MOV64rm %vreg137, 1, %noreg, 64, %noreg; mem:LD8[%block79] GR64:%vreg136,%vreg137
3248B		MOV8mr %vreg136, 1, %vreg139, 0, %noreg, %vreg143; mem:ST1[%arrayidx80] GR64:%vreg136 GR64_NOSP:%vreg139 GR8:%vreg143
3264B		%vreg131<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg131
3280B		%vreg130<def> = MOV32rm %vreg131, 1, %noreg, 108, %noreg; mem:LD4[%nblock81] GR32:%vreg130 GR64:%vreg131
3296B		%vreg129<def> = COPY %vreg130; GR32:%vreg129,%vreg130
3312B		%vreg129<def,tied1> = ADD32ri8 %vreg129<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg129
3328B		MOV32mr %vreg131, 1, %noreg, 108, %noreg, %vreg129; mem:ST4[%nblock81] GR64:%vreg131 GR32:%vreg129
	    Successors according to CFG: BB#11

3344B	BB#11: derived from LLVM BB %sw.epilog
	    Predecessors according to CFG: BB#9 BB#8 BB#7 BB#10
3360B		%vreg227<def> = MOV64ri <ga:@add_pair_to_block>; GR64:%vreg227
3376B		%vreg228<def> = COPY %vreg227; GR64:%vreg228,%vreg227
3392B		%vreg229<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg229
3408B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3424B		%RDI<def> = COPY %vreg228; GR64:%vreg228
3440B		%RSI<def> = COPY %vreg229; GR64:%vreg229
3456B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
3472B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3488B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3504B		STACKMAP 1, 0, ...
3520B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3536B		RETQ

# End machine code for function add_pair_to_block.

********** SIMPLE REGISTER COALESCING **********
********** Function: add_pair_to_block
********** JOINING INTERVALS ***********
for.cond:
for.body:
608B	%vreg239<def> = SUBREG_TO_REG 0, %vreg238, 4; GR64_NOSP:%vreg239 GR32:%vreg238
	Considering merging to GR64_NOSP with %vreg238 in %vreg239:sub_32bit
		RHS = %vreg238 [592r,608r:0)  0@592r
		LHS = %vreg239 [608r,640r:0)  0@608r
		merge %vreg239:0@608r into %vreg238:0@592r --> @592r
		erased:	608r	%vreg239<def> = SUBREG_TO_REG 0, %vreg238, 4; GR64_NOSP:%vreg239 GR32:%vreg238
		updated: 592B	%vreg239:sub_32bit<def,read-undef> = MOV32rr %vreg242; GR64_NOSP:%vreg239 GR32:%vreg242
	Success: %vreg238:sub_32bit -> %vreg239
	Result = %vreg239 [592r,640r:0)  0@592r
for.inc:
448B	%vreg251<def> = COPY %vreg253; GR32:%vreg251,%vreg253
	Considering merging to GR32 with %vreg253 in %vreg251
		RHS = %vreg253 [432r,448r:0)  0@432r
		LHS = %vreg251 [448r,464r:0)[464r,624r:1)  0@448r 1@464r
		merge %vreg251:0@448r into %vreg253:0@432r --> @432r
		erased:	448r	%vreg251<def> = COPY %vreg253; GR32:%vreg251,%vreg253
		updated: 432B	%vreg251<def> = MOV32rm %vreg254, 1, %noreg, 648, %noreg; mem:LD4[%blockCRC] GR32:%vreg251 GR64:%vreg254
	Success: %vreg253 -> %vreg251
	Result = %vreg251 [432r,464r:0)[464r,624r:1)  0@432r 1@464r
512B	%vreg246<def> = COPY %vreg248; GR32:%vreg246,%vreg248
	Considering merging to GR32 with %vreg248 in %vreg246
		RHS = %vreg248 [496r,512r:0)  0@496r
		LHS = %vreg246 [512r,528r:0)[528r,560r:1)  0@512r 1@528r
		merge %vreg246:0@512r into %vreg248:0@496r --> @496r
		erased:	512r	%vreg246<def> = COPY %vreg248; GR32:%vreg246,%vreg248
		updated: 496B	%vreg246<def> = MOV32rm %vreg249, 1, %noreg, 648, %noreg; mem:LD4[%blockCRC2] GR32:%vreg246 GR64:%vreg249
	Success: %vreg248 -> %vreg246
	Result = %vreg246 [496r,528r:0)[528r,560r:1)  0@496r 1@528r
560B	%vreg242<def> = COPY %vreg246; GR32:%vreg242,%vreg246
	Considering merging to GR32 with %vreg246 in %vreg242
		RHS = %vreg246 [496r,528r:0)[528r,560r:1)  0@496r 1@528r
		LHS = %vreg242 [560r,576r:0)[576r,592r:1)  0@560r 1@576r
		merge %vreg242:0@560r into %vreg246:1@528r --> @528r
		erased:	560r	%vreg242<def> = COPY %vreg246; GR32:%vreg242,%vreg246
		updated: 496B	%vreg242<def> = MOV32rm %vreg249, 1, %noreg, 648, %noreg; mem:LD4[%blockCRC2] GR32:%vreg242 GR64:%vreg249
		updated: 528B	%vreg242<def,tied1> = SHR32ri %vreg242<tied0>, 24, %EFLAGS<imp-def,dead>; GR32:%vreg242
	Success: %vreg246 -> %vreg242
	Result = %vreg242 [496r,528r:2)[528r,576r:0)[576r,592r:1)  0@528r 1@576r 2@496r
624B	%vreg235<def> = COPY %vreg251; GR32:%vreg235,%vreg251
	Considering merging to GR32 with %vreg251 in %vreg235
		RHS = %vreg251 [432r,464r:0)[464r,624r:1)  0@432r 1@464r
		LHS = %vreg235 [624r,640r:0)[640r,672r:1)  0@624r 1@640r
		merge %vreg235:0@624r into %vreg251:1@464r --> @464r
		erased:	624r	%vreg235<def> = COPY %vreg251; GR32:%vreg235,%vreg251
		updated: 432B	%vreg235<def> = MOV32rm %vreg254, 1, %noreg, 648, %noreg; mem:LD4[%blockCRC] GR32:%vreg235 GR64:%vreg254
		updated: 464B	%vreg235<def,tied1> = SHL32ri %vreg235<tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg235
	Success: %vreg251 -> %vreg235
	Result = %vreg235 [432r,464r:2)[464r,640r:0)[640r,672r:1)  0@464r 1@640r 2@432r
720B	%vreg257<def> = COPY %vreg258; GR32:%vreg257,%vreg258
	Considering merging to GR32 with %vreg258 in %vreg257
		RHS = %vreg258 [704r,720r:0)  0@704r
		LHS = %vreg257 [720r,736r:0)[736r,752r:1)  0@720r 1@736r
		merge %vreg257:0@720r into %vreg258:0@704r --> @704r
		erased:	720r	%vreg257<def> = COPY %vreg258; GR32:%vreg257,%vreg258
		updated: 704B	%vreg257<def> = MOV32rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD4[%i] GR32:%vreg257
	Success: %vreg258 -> %vreg257
	Result = %vreg257 [704r,736r:0)[736r,752r:1)  0@704r 1@736r
sw.epilog:
3424B	%RDI<def> = COPY %vreg228; GR64:%vreg228
	Considering merging %vreg228 with %RDI
	Can only merge into reserved registers.
3440B	%RSI<def> = COPY %vreg229; GR64:%vreg229
	Considering merging %vreg229 with %RSI
	Can only merge into reserved registers.
for.end:
832B	%vreg19<def> = SUBREG_TO_REG 0, %vreg18, 4; GR64_NOSP:%vreg19 GR32:%vreg18
	Considering merging to GR64_NOSP with %vreg18 in %vreg19:sub_32bit
		RHS = %vreg18 [816r,832r:0)  0@816r
		LHS = %vreg19 [832r,848r:0)  0@832r
		merge %vreg19:0@832r into %vreg18:0@816r --> @816r
		erased:	832r	%vreg19<def> = SUBREG_TO_REG 0, %vreg18, 4; GR64_NOSP:%vreg19 GR32:%vreg18
		updated: 816B	%vreg19:sub_32bit<def,read-undef> = MOV32rm %vreg17, 1, %noreg, 92, %noreg; mem:LD4[%state_in_ch6] GR64_NOSP:%vreg19 GR64:%vreg17
	Success: %vreg18:sub_32bit -> %vreg19
	Result = %vreg19 [816r,848r:0)  0@816r
for.end:
for.end:
sw.bb:
sw.bb.14:
sw.bb.27:
sw.default:
entry:
16B	%vreg0<def> = COPY %RDI; GR64:%vreg0
	Considering merging %vreg0 with %RDI
	Can only merge into reserved registers.
112B	%RDI<def> = COPY %vreg9; GR64:%vreg9
	Considering merging %vreg9 with %RDI
	Can only merge into reserved registers.
128B	%RSI<def> = COPY %vreg10; GR64:%vreg10
	Considering merging %vreg10 with %RSI
	Can only merge into reserved registers.
3376B	%vreg228<def> = COPY %vreg227; GR64:%vreg228,%vreg227
	Considering merging to GR64 with %vreg227 in %vreg228
		RHS = %vreg227 [3360r,3376r:0)  0@3360r
		LHS = %vreg228 [3376r,3424r:0)  0@3376r
		merge %vreg228:0@3376r into %vreg227:0@3360r --> @3360r
		erased:	3376r	%vreg228<def> = COPY %vreg227; GR64:%vreg228,%vreg227
		updated: 3360B	%vreg228<def> = MOV64ri <ga:@add_pair_to_block>; GR64:%vreg228
	Success: %vreg227 -> %vreg228
	Result = %vreg228 [3360r,3424r:0)  0@3360r
896B	%vreg21<def> = COPY %vreg16; GR32:%vreg21,%vreg16
	Considering merging to GR32 with %vreg16 in %vreg21
		RHS = %vreg16 [880r,1056r:0)  0@880r
		LHS = %vreg21 [896r,912r:0)[912r,912d:1)  0@896r 1@912r
		merge %vreg21:0@896r into %vreg16:0@880r --> @880r
		interference at %vreg21:1@912r
	Interference!
976B	%vreg22<def> = COPY %vreg16; GR32:%vreg22,%vreg16
	Considering merging to GR32 with %vreg16 in %vreg22
		RHS = %vreg16 [880r,1056r:0)  0@880r
		LHS = %vreg22 [976r,992r:0)[992r,992d:1)  0@976r 1@992r
		merge %vreg22:0@976r into %vreg16:0@880r --> @880r
		interference at %vreg22:1@992r
	Interference!
1056B	%vreg23<def> = COPY %vreg16; GR32:%vreg23,%vreg16
	Considering merging to GR32 with %vreg16 in %vreg23
		RHS = %vreg16 [880r,1056r:0)  0@880r
		LHS = %vreg23 [1056r,1072r:0)[1072r,1072d:1)  0@1056r 1@1072r
		merge %vreg23:0@1056r into %vreg16:0@880r --> @880r
		erased:	1056r	%vreg23<def> = COPY %vreg16; GR32:%vreg23,%vreg16
		updated: 880B	%vreg23<def> = MOV32rm %vreg20, 1, %noreg, 96, %noreg; mem:LD4[%state_in_len9] GR32:%vreg23 GR64:%vreg20
		updated: 896B	%vreg21<def> = COPY %vreg23; GR32:%vreg21,%vreg23
		updated: 976B	%vreg22<def> = COPY %vreg23; GR32:%vreg22,%vreg23
	Success: %vreg16 -> %vreg23
	Result = %vreg23 [880r,1072r:0)[1072r,1072d:1)  0@880r 1@1072r
1264B	%vreg112<def> = COPY %vreg113; GR32:%vreg112,%vreg113
	Considering merging to GR32 with %vreg113 in %vreg112
		RHS = %vreg113 [1248r,1264r:0)  0@1248r
		LHS = %vreg112 [1264r,1280r:0)[1280r,1296r:1)  0@1264r 1@1280r
		merge %vreg112:0@1264r into %vreg113:0@1248r --> @1248r
		erased:	1264r	%vreg112<def> = COPY %vreg113; GR32:%vreg112,%vreg113
		updated: 1248B	%vreg112<def> = MOV32rm %vreg114, 1, %noreg, 108, %noreg; mem:LD4[%nblock12] GR32:%vreg112 GR64:%vreg114
	Success: %vreg113 -> %vreg112
	Result = %vreg112 [1248r,1280r:0)[1280r,1296r:1)  0@1248r 1@1280r
1472B	%vreg95<def> = COPY %vreg96; GR32:%vreg95,%vreg96
	Considering merging to GR32 with %vreg96 in %vreg95
		RHS = %vreg96 [1456r,1472r:0)  0@1456r
		LHS = %vreg95 [1472r,1488r:0)[1488r,1504r:1)  0@1472r 1@1488r
		merge %vreg95:0@1472r into %vreg96:0@1456r --> @1456r
		erased:	1472r	%vreg95<def> = COPY %vreg96; GR32:%vreg95,%vreg96
		updated: 1456B	%vreg95<def> = MOV32rm %vreg97, 1, %noreg, 108, %noreg; mem:LD4[%nblock19] GR32:%vreg95 GR64:%vreg97
	Success: %vreg96 -> %vreg95
	Result = %vreg95 [1456r,1488r:0)[1488r,1504r:1)  0@1456r 1@1488r
1648B	%vreg78<def> = COPY %vreg79; GR32:%vreg78,%vreg79
	Considering merging to GR32 with %vreg79 in %vreg78
		RHS = %vreg79 [1632r,1648r:0)  0@1632r
		LHS = %vreg78 [1648r,1664r:0)[1664r,1680r:1)  0@1648r 1@1664r
		merge %vreg78:0@1648r into %vreg79:0@1632r --> @1632r
		erased:	1648r	%vreg78<def> = COPY %vreg79; GR32:%vreg78,%vreg79
		updated: 1632B	%vreg78<def> = MOV32rm %vreg80, 1, %noreg, 108, %noreg; mem:LD4[%nblock25] GR32:%vreg78 GR64:%vreg80
	Success: %vreg79 -> %vreg78
	Result = %vreg78 [1632r,1664r:0)[1664r,1680r:1)  0@1632r 1@1664r
1856B	%vreg61<def> = COPY %vreg62; GR32:%vreg61,%vreg62
	Considering merging to GR32 with %vreg62 in %vreg61
		RHS = %vreg62 [1840r,1856r:0)  0@1840r
		LHS = %vreg61 [1856r,1872r:0)[1872r,1888r:1)  0@1856r 1@1872r
		merge %vreg61:0@1856r into %vreg62:0@1840r --> @1840r
		erased:	1856r	%vreg61<def> = COPY %vreg62; GR32:%vreg61,%vreg62
		updated: 1840B	%vreg61<def> = MOV32rm %vreg63, 1, %noreg, 108, %noreg; mem:LD4[%nblock32] GR32:%vreg61 GR64:%vreg63
	Success: %vreg62 -> %vreg61
	Result = %vreg61 [1840r,1872r:0)[1872r,1888r:1)  0@1840r 1@1872r
2032B	%vreg44<def> = COPY %vreg45; GR32:%vreg44,%vreg45
	Considering merging to GR32 with %vreg45 in %vreg44
		RHS = %vreg45 [2016r,2032r:0)  0@2016r
		LHS = %vreg44 [2032r,2048r:0)[2048r,2064r:1)  0@2032r 1@2048r
		merge %vreg44:0@2032r into %vreg45:0@2016r --> @2016r
		erased:	2032r	%vreg44<def> = COPY %vreg45; GR32:%vreg44,%vreg45
		updated: 2016B	%vreg44<def> = MOV32rm %vreg46, 1, %noreg, 108, %noreg; mem:LD4[%nblock38] GR32:%vreg44 GR64:%vreg46
	Success: %vreg45 -> %vreg44
	Result = %vreg44 [2016r,2048r:0)[2048r,2064r:1)  0@2016r 1@2048r
2208B	%vreg27<def> = COPY %vreg28; GR32:%vreg27,%vreg28
	Considering merging to GR32 with %vreg28 in %vreg27
		RHS = %vreg28 [2192r,2208r:0)  0@2192r
		LHS = %vreg27 [2208r,2224r:0)[2224r,2240r:1)  0@2208r 1@2224r
		merge %vreg27:0@2208r into %vreg28:0@2192r --> @2192r
		erased:	2208r	%vreg27<def> = COPY %vreg28; GR32:%vreg27,%vreg28
		updated: 2192B	%vreg27<def> = MOV32rm %vreg29, 1, %noreg, 108, %noreg; mem:LD4[%nblock44] GR32:%vreg27 GR64:%vreg29
	Success: %vreg28 -> %vreg27
	Result = %vreg27 [2192r,2224r:0)[2224r,2240r:1)  0@2192r 1@2224r
2320B	%vreg223<def> = COPY %vreg225; GR32:%vreg223,%vreg225
	Considering merging to GR32 with %vreg225 in %vreg223
		RHS = %vreg225 [2304r,2320r:0)  0@2304r
		LHS = %vreg223 [2320r,2336r:0)[2336r,2352r:1)  0@2320r 1@2336r
		merge %vreg223:0@2320r into %vreg225:0@2304r --> @2304r
		erased:	2320r	%vreg223<def> = COPY %vreg225; GR32:%vreg223,%vreg225
		updated: 2304B	%vreg223<def> = MOV32rm %vreg226, 1, %noreg, 96, %noreg; mem:LD4[%state_in_len46] GR32:%vreg223 GR64:%vreg226
	Success: %vreg225 -> %vreg223
	Result = %vreg223 [2304r,2336r:0)[2336r,2352r:1)  0@2304r 1@2336r
2528B	%vreg203<def> = COPY %vreg204; GR32:%vreg203,%vreg204
	Considering merging to GR32 with %vreg204 in %vreg203
		RHS = %vreg204 [2512r,2528r:0)  0@2512r
		LHS = %vreg203 [2528r,2544r:0)[2544r,2560r:1)  0@2528r 1@2544r
		merge %vreg203:0@2528r into %vreg204:0@2512r --> @2512r
		erased:	2528r	%vreg203<def> = COPY %vreg204; GR32:%vreg203,%vreg204
		updated: 2512B	%vreg203<def> = MOV32rm %vreg205, 1, %noreg, 108, %noreg; mem:LD4[%nblock54] GR32:%vreg203 GR64:%vreg205
	Success: %vreg204 -> %vreg203
	Result = %vreg203 [2512r,2544r:0)[2544r,2560r:1)  0@2512r 1@2544r
2704B	%vreg186<def> = COPY %vreg187; GR32:%vreg186,%vreg187
	Considering merging to GR32 with %vreg187 in %vreg186
		RHS = %vreg187 [2688r,2704r:0)  0@2688r
		LHS = %vreg186 [2704r,2720r:0)[2720r,2736r:1)  0@2704r 1@2720r
		merge %vreg186:0@2704r into %vreg187:0@2688r --> @2688r
		erased:	2704r	%vreg186<def> = COPY %vreg187; GR32:%vreg186,%vreg187
		updated: 2688B	%vreg186<def> = MOV32rm %vreg188, 1, %noreg, 108, %noreg; mem:LD4[%nblock60] GR32:%vreg186 GR64:%vreg188
	Success: %vreg187 -> %vreg186
	Result = %vreg186 [2688r,2720r:0)[2720r,2736r:1)  0@2688r 1@2720r
2880B	%vreg169<def> = COPY %vreg170; GR32:%vreg169,%vreg170
	Considering merging to GR32 with %vreg170 in %vreg169
		RHS = %vreg170 [2864r,2880r:0)  0@2864r
		LHS = %vreg169 [2880r,2896r:0)[2896r,2912r:1)  0@2880r 1@2896r
		merge %vreg169:0@2880r into %vreg170:0@2864r --> @2864r
		erased:	2880r	%vreg169<def> = COPY %vreg170; GR32:%vreg169,%vreg170
		updated: 2864B	%vreg169<def> = MOV32rm %vreg171, 1, %noreg, 108, %noreg; mem:LD4[%nblock66] GR32:%vreg169 GR64:%vreg171
	Success: %vreg170 -> %vreg169
	Result = %vreg169 [2864r,2896r:0)[2896r,2912r:1)  0@2864r 1@2896r
3056B	%vreg152<def> = COPY %vreg153; GR32:%vreg152,%vreg153
	Considering merging to GR32 with %vreg153 in %vreg152
		RHS = %vreg153 [3040r,3056r:0)  0@3040r
		LHS = %vreg152 [3056r,3072r:0)[3072r,3088r:1)  0@3056r 1@3072r
		merge %vreg152:0@3056r into %vreg153:0@3040r --> @3040r
		erased:	3056r	%vreg152<def> = COPY %vreg153; GR32:%vreg152,%vreg153
		updated: 3040B	%vreg152<def> = MOV32rm %vreg154, 1, %noreg, 108, %noreg; mem:LD4[%nblock72] GR32:%vreg152 GR64:%vreg154
	Success: %vreg153 -> %vreg152
	Result = %vreg152 [3040r,3072r:0)[3072r,3088r:1)  0@3040r 1@3072r
3136B	%vreg145<def> = COPY %vreg147; GR32:%vreg145,%vreg147
	Considering merging to GR32 with %vreg147 in %vreg145
		RHS = %vreg147 [3120r,3136r:0)  0@3120r
		LHS = %vreg145 [3136r,3152r:0)[3152r,3168r:1)  0@3136r 1@3152r
		merge %vreg145:0@3136r into %vreg147:0@3120r --> @3120r
		erased:	3136r	%vreg145<def> = COPY %vreg147; GR32:%vreg145,%vreg147
		updated: 3120B	%vreg145<def> = MOV32rm %vreg148, 1, %noreg, 96, %noreg; mem:LD4[%state_in_len74] GR32:%vreg145 GR64:%vreg148
	Success: %vreg147 -> %vreg145
	Result = %vreg145 [3120r,3152r:0)[3152r,3168r:1)  0@3120r 1@3152r
3168B	%vreg143<def> = COPY %vreg145:sub_8bit; GR8:%vreg143 GR32:%vreg145
	Considering merging to GR32 with %vreg143 in %vreg145:sub_8bit
		RHS = %vreg143 [3168r,3248r:0)  0@3168r
		LHS = %vreg145 [3120r,3152r:0)[3152r,3168r:1)  0@3120r 1@3152r
		merge %vreg143:0@3168r into %vreg145:1@3152r --> @3152r
		erased:	3168r	%vreg143<def> = COPY %vreg145:sub_8bit; GR8:%vreg143 GR32:%vreg145
		updated: 3248B	MOV8mr %vreg136, 1, %vreg139, 0, %noreg, %vreg145:sub_8bit; mem:ST1[%arrayidx80] GR64:%vreg136 GR64_NOSP:%vreg139 GR32:%vreg145
	Success: %vreg143:sub_8bit -> %vreg145
	Result = %vreg145 [3120r,3152r:0)[3152r,3248r:1)  0@3120r 1@3152r
3296B	%vreg129<def> = COPY %vreg130; GR32:%vreg129,%vreg130
	Considering merging to GR32 with %vreg130 in %vreg129
		RHS = %vreg130 [3280r,3296r:0)  0@3280r
		LHS = %vreg129 [3296r,3312r:0)[3312r,3328r:1)  0@3296r 1@3312r
		merge %vreg129:0@3296r into %vreg130:0@3280r --> @3280r
		erased:	3296r	%vreg129<def> = COPY %vreg130; GR32:%vreg129,%vreg130
		updated: 3280B	%vreg129<def> = MOV32rm %vreg131, 1, %noreg, 108, %noreg; mem:LD4[%nblock81] GR32:%vreg129 GR64:%vreg131
	Success: %vreg130 -> %vreg129
	Result = %vreg129 [3280r,3312r:0)[3312r,3328r:1)  0@3280r 1@3312r
32B	%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
	Considering merging to GR64 with %vreg0 in %vreg1
		RHS = %vreg0 [16r,32r:0)  0@16r
		LHS = %vreg1 [32r,224r:0)  0@32r
		merge %vreg1:0@32r into %vreg0:0@16r --> @16r
		erased:	32r	%vreg1<def> = COPY %vreg0; GR64:%vreg1,%vreg0
		updated: 16B	%vreg1<def> = COPY %RDI; GR64:%vreg1
	Success: %vreg0 -> %vreg1
	Result = %vreg1 [16r,224r:0)  0@16r
64B	%vreg9<def> = COPY %vreg8; GR64:%vreg9,%vreg8
	Considering merging to GR64 with %vreg8 in %vreg9
		RHS = %vreg8 [48r,64r:0)  0@48r
		LHS = %vreg9 [64r,112r:0)  0@64r
		merge %vreg9:0@64r into %vreg8:0@48r --> @48r
		erased:	64r	%vreg9<def> = COPY %vreg8; GR64:%vreg9,%vreg8
		updated: 48B	%vreg9<def> = MOV64ri <ga:@add_pair_to_block>; GR64:%vreg9
	Success: %vreg8 -> %vreg9
	Result = %vreg9 [48r,112r:0)  0@48r
272B	%vreg4<def> = COPY %vreg6:sub_8bit; GR8:%vreg4 GR32:%vreg6
	Considering merging to GR32 with %vreg4 in %vreg6:sub_8bit
		RHS = %vreg4 [272r,288r:0)  0@272r
		LHS = %vreg6 [256r,272r:0)  0@256r
		merge %vreg4:0@272r into %vreg6:0@256r --> @256r
		erased:	272r	%vreg4<def> = COPY %vreg6:sub_8bit; GR8:%vreg4 GR32:%vreg6
		updated: 288B	MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg6:sub_8bit; mem:ST1[%ch] GR32:%vreg6
	Success: %vreg4:sub_8bit -> %vreg6
	Result = %vreg6 [256r,288r:0)  0@256r
3424B	%RDI<def> = COPY %vreg228; GR64:%vreg228
	Considering merging %vreg228 with %RDI
	Can only merge into reserved registers.
112B	%RDI<def> = COPY %vreg9; GR64:%vreg9
	Considering merging %vreg9 with %RDI
	Can only merge into reserved registers.
896B	%vreg21<def> = COPY %vreg23; GR32:%vreg21,%vreg23
	Considering merging to GR32 with %vreg23 in %vreg21
		RHS = %vreg23 [880r,1072r:0)[1072r,1072d:1)  0@880r 1@1072r
		LHS = %vreg21 [896r,912r:0)[912r,912d:1)  0@896r 1@912r
		merge %vreg21:0@896r into %vreg23:0@880r --> @880r
		interference at %vreg21:1@912r
	Interference!
976B	%vreg22<def> = COPY %vreg23; GR32:%vreg22,%vreg23
	Considering merging to GR32 with %vreg23 in %vreg22
		RHS = %vreg23 [880r,1072r:0)[1072r,1072d:1)  0@880r 1@1072r
		LHS = %vreg22 [976r,992r:0)[992r,992d:1)  0@976r 1@992r
		merge %vreg22:0@976r into %vreg23:0@880r --> @880r
		interference at %vreg22:1@992r
	Interference!
Trying to inflate 0 regs.
********** INTERVALS **********
DIL [0B,16r:0)[112r,144r:2)[3424r,3456r:1)  0@0B-phi 1@3424r 2@112r
%vreg1 [16r,224r:0)  0@16r
%vreg6 [256r,288r:0)  0@256r
%vreg7 [240r,256r:0)  0@240r
%vreg9 [48r,112r:0)  0@48r
%vreg10 [80r,128r:0)  0@80r
%vreg14 [352r,368r:0)  0@352r
%vreg15 [336r,368r:0)  0@336r
%vreg17 [800r,848r:0)  0@800r
%vreg19 [816r,848r:0)  0@816r
%vreg20 [864r,880r:0)  0@864r
%vreg21 [896r,912r:0)[912r,912d:1)  0@896r 1@912r
%vreg22 [976r,992r:0)[992r,992d:1)  0@976r 1@992r
%vreg23 [880r,1072r:0)[1072r,1072d:1)  0@880r 1@1072r
%vreg27 [2192r,2224r:0)[2224r,2240r:1)  0@2192r 1@2224r
%vreg29 [2176r,2240r:0)  0@2176r
%vreg34 [2144r,2160r:0)  0@2144r
%vreg35 [2128r,2144r:0)  0@2128r
%vreg37 [2112r,2160r:0)  0@2112r
%vreg39 [2096r,2112r:0)  0@2096r
%vreg40 [2080r,2160r:0)  0@2080r
%vreg44 [2016r,2048r:0)[2048r,2064r:1)  0@2016r 1@2048r
%vreg46 [2000r,2064r:0)  0@2000r
%vreg51 [1968r,1984r:0)  0@1968r
%vreg52 [1952r,1968r:0)  0@1952r
%vreg54 [1936r,1984r:0)  0@1936r
%vreg56 [1920r,1936r:0)  0@1920r
%vreg57 [1904r,1984r:0)  0@1904r
%vreg61 [1840r,1872r:0)[1872r,1888r:1)  0@1840r 1@1872r
%vreg63 [1824r,1888r:0)  0@1824r
%vreg68 [1792r,1808r:0)  0@1792r
%vreg69 [1776r,1792r:0)  0@1776r
%vreg71 [1760r,1808r:0)  0@1760r
%vreg73 [1744r,1760r:0)  0@1744r
%vreg74 [1728r,1808r:0)  0@1728r
%vreg78 [1632r,1664r:0)[1664r,1680r:1)  0@1632r 1@1664r
%vreg80 [1616r,1680r:0)  0@1616r
%vreg85 [1584r,1600r:0)  0@1584r
%vreg86 [1568r,1584r:0)  0@1568r
%vreg88 [1552r,1600r:0)  0@1552r
%vreg90 [1536r,1552r:0)  0@1536r
%vreg91 [1520r,1600r:0)  0@1520r
%vreg95 [1456r,1488r:0)[1488r,1504r:1)  0@1456r 1@1488r
%vreg97 [1440r,1504r:0)  0@1440r
%vreg102 [1408r,1424r:0)  0@1408r
%vreg103 [1392r,1408r:0)  0@1392r
%vreg105 [1376r,1424r:0)  0@1376r
%vreg107 [1360r,1376r:0)  0@1360r
%vreg108 [1344r,1424r:0)  0@1344r
%vreg112 [1248r,1280r:0)[1280r,1296r:1)  0@1248r 1@1280r
%vreg114 [1232r,1296r:0)  0@1232r
%vreg119 [1200r,1216r:0)  0@1200r
%vreg120 [1184r,1200r:0)  0@1184r
%vreg122 [1168r,1216r:0)  0@1168r
%vreg124 [1152r,1168r:0)  0@1152r
%vreg125 [1136r,1216r:0)  0@1136r
%vreg129 [3280r,3312r:0)[3312r,3328r:1)  0@3280r 1@3312r
%vreg131 [3264r,3328r:0)  0@3264r
%vreg136 [3232r,3248r:0)  0@3232r
%vreg137 [3216r,3232r:0)  0@3216r
%vreg139 [3200r,3248r:0)  0@3200r
%vreg141 [3184r,3200r:0)  0@3184r
%vreg145 [3120r,3152r:0)[3152r,3248r:1)  0@3120r 1@3152r
%vreg148 [3104r,3120r:0)  0@3104r
%vreg152 [3040r,3072r:0)[3072r,3088r:1)  0@3040r 1@3072r
%vreg154 [3024r,3088r:0)  0@3024r
%vreg159 [2992r,3008r:0)  0@2992r
%vreg160 [2976r,2992r:0)  0@2976r
%vreg162 [2960r,3008r:0)  0@2960r
%vreg164 [2944r,2960r:0)  0@2944r
%vreg165 [2928r,3008r:0)  0@2928r
%vreg169 [2864r,2896r:0)[2896r,2912r:1)  0@2864r 1@2896r
%vreg171 [2848r,2912r:0)  0@2848r
%vreg176 [2816r,2832r:0)  0@2816r
%vreg177 [2800r,2816r:0)  0@2800r
%vreg179 [2784r,2832r:0)  0@2784r
%vreg181 [2768r,2784r:0)  0@2768r
%vreg182 [2752r,2832r:0)  0@2752r
%vreg186 [2688r,2720r:0)[2720r,2736r:1)  0@2688r 1@2720r
%vreg188 [2672r,2736r:0)  0@2672r
%vreg193 [2640r,2656r:0)  0@2640r
%vreg194 [2624r,2640r:0)  0@2624r
%vreg196 [2608r,2656r:0)  0@2608r
%vreg198 [2592r,2608r:0)  0@2592r
%vreg199 [2576r,2656r:0)  0@2576r
%vreg203 [2512r,2544r:0)[2544r,2560r:1)  0@2512r 1@2544r
%vreg205 [2496r,2560r:0)  0@2496r
%vreg210 [2464r,2480r:0)  0@2464r
%vreg211 [2448r,2464r:0)  0@2448r
%vreg213 [2432r,2480r:0)  0@2432r
%vreg215 [2416r,2432r:0)  0@2416r
%vreg216 [2400r,2480r:0)  0@2400r
%vreg219 [2368r,2384r:0)  0@2368r
%vreg221 [2352r,2384r:0)  0@2352r
%vreg223 [2304r,2336r:0)[2336r,2352r:1)  0@2304r 1@2336r
%vreg226 [2288r,2304r:0)  0@2288r
%vreg228 [3360r,3424r:0)  0@3360r
%vreg229 [3392r,3440r:0)  0@3392r
%vreg232 [656r,672r:0)  0@656r
%vreg235 [432r,464r:2)[464r,640r:0)[640r,672r:1)  0@464r 1@640r 2@432r
%vreg239 [592r,640r:0)  0@592r
%vreg242 [496r,528r:2)[528r,576r:0)[576r,592r:1)  0@528r 1@576r 2@496r
%vreg244 [544r,576r:0)  0@544r
%vreg249 [480r,496r:0)  0@480r
%vreg254 [416r,432r:0)  0@416r
%vreg257 [704r,736r:0)[736r,752r:1)  0@704r 1@736r
RegMasks: 144r 3456r
********** MACHINEINSTRS **********
# Machine code for function add_pair_to_block: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=8, align=8, at location [SP+8]
  fi#1: size=4, align=4, at location [SP+8]
  fi#2: size=1, align=1, at location [SP+8]
Function Live Ins: %RDI in %vreg0

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI
16B		%vreg1<def> = COPY %RDI; GR64:%vreg1
48B		%vreg9<def> = MOV64ri <ga:@add_pair_to_block>; GR64:%vreg9
80B		%vreg10<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg10
96B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
112B		%RDI<def> = COPY %vreg9; GR64:%vreg9
128B		%RSI<def> = COPY %vreg10; GR64:%vreg10
144B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
160B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
192B		STACKMAP 0, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack1](align=4) LD8[FixedStack0] GR64:%vreg1
208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%s.addr] GR64:%vreg1
240B		%vreg7<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg7
256B		%vreg6<def> = MOV32rm %vreg7, 1, %noreg, 92, %noreg; mem:LD4[%state_in_ch] GR32:%vreg6 GR64:%vreg7
288B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg6:sub_8bit; mem:ST1[%ch] GR32:%vreg6
304B		MOV32mi <fi#1>, 1, %noreg, 0, %noreg, 0; mem:ST4[%i]
	    Successors according to CFG: BB#1

320B	BB#1: derived from LLVM BB %for.cond
	    Predecessors according to CFG: BB#0 BB#3
336B		%vreg15<def> = MOV32rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD4[%i] GR32:%vreg15
352B		%vreg14<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg14
368B		CMP32rm %vreg15, %vreg14, 1, %noreg, 96, %noreg, %EFLAGS<imp-def>; mem:LD4[%state_in_len] GR32:%vreg15 GR64:%vreg14
384B		JGE_1 <BB#4>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#4 BB#2

400B	BB#2: derived from LLVM BB %for.body
	    Predecessors according to CFG: BB#1
416B		%vreg254<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg254
432B		%vreg235<def> = MOV32rm %vreg254, 1, %noreg, 648, %noreg; mem:LD4[%blockCRC] GR32:%vreg235 GR64:%vreg254
464B		%vreg235<def,tied1> = SHL32ri %vreg235<tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg235
480B		%vreg249<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg249
496B		%vreg242<def> = MOV32rm %vreg249, 1, %noreg, 648, %noreg; mem:LD4[%blockCRC2] GR32:%vreg242 GR64:%vreg249
528B		%vreg242<def,tied1> = SHR32ri %vreg242<tied0>, 24, %EFLAGS<imp-def,dead>; GR32:%vreg242
544B		%vreg244<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%ch] GR32:%vreg244
576B		%vreg242<def,tied1> = XOR32rr %vreg242<tied0>, %vreg244, %EFLAGS<imp-def,dead>; GR32:%vreg242,%vreg244
592B		%vreg239:sub_32bit<def,read-undef> = MOV32rr %vreg242; GR64_NOSP:%vreg239 GR32:%vreg242
640B		%vreg235<def,tied1> = XOR32rm %vreg235<tied0>, %noreg, 4, %vreg239, <ga:@BZ2_crc32Table>, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%arrayidx] GR32:%vreg235 GR64_NOSP:%vreg239
656B		%vreg232<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg232
672B		MOV32mr %vreg232, 1, %noreg, 648, %noreg, %vreg235; mem:ST4[%blockCRC5] GR64:%vreg232 GR32:%vreg235
	    Successors according to CFG: BB#3

688B	BB#3: derived from LLVM BB %for.inc
	    Predecessors according to CFG: BB#2
704B		%vreg257<def> = MOV32rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD4[%i] GR32:%vreg257
736B		%vreg257<def,tied1> = ADD32ri8 %vreg257<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg257
752B		MOV32mr <fi#1>, 1, %noreg, 0, %noreg, %vreg257; mem:ST4[%i] GR32:%vreg257
768B		JMP_1 <BB#1>
	    Successors according to CFG: BB#1

784B	BB#4: derived from LLVM BB %for.end
	    Predecessors according to CFG: BB#1
800B		%vreg17<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg17
816B		%vreg19:sub_32bit<def,read-undef> = MOV32rm %vreg17, 1, %noreg, 92, %noreg; mem:LD4[%state_in_ch6] GR64_NOSP:%vreg19 GR64:%vreg17
848B		MOV8mi %vreg17, 1, %vreg19, 128, %noreg, 1; mem:ST1[%arrayidx8] GR64:%vreg17 GR64_NOSP:%vreg19
864B		%vreg20<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg20
880B		%vreg23<def> = MOV32rm %vreg20, 1, %noreg, 96, %noreg; mem:LD4[%state_in_len9] GR32:%vreg23 GR64:%vreg20
896B		%vreg21<def> = COPY %vreg23; GR32:%vreg21,%vreg23
912B		%vreg21<def,dead,tied1> = SUB32ri8 %vreg21<tied0>, 1, %EFLAGS<imp-def>; GR32:%vreg21
928B		JE_1 <BB#7>, %EFLAGS<imp-use,kill>
944B		JMP_1 <BB#5>
	    Successors according to CFG: BB#7 BB#5

960B	BB#5: derived from LLVM BB %for.end
	    Predecessors according to CFG: BB#4
976B		%vreg22<def> = COPY %vreg23; GR32:%vreg22,%vreg23
992B		%vreg22<def,dead,tied1> = SUB32ri8 %vreg22<tied0>, 2, %EFLAGS<imp-def>; GR32:%vreg22
1008B		JE_1 <BB#8>, %EFLAGS<imp-use,kill>
1024B		JMP_1 <BB#6>
	    Successors according to CFG: BB#8 BB#6

1040B	BB#6: derived from LLVM BB %for.end
	    Predecessors according to CFG: BB#5
1072B		%vreg23<def,dead,tied1> = SUB32ri8 %vreg23<tied0>, 3, %EFLAGS<imp-def>; GR32:%vreg23
1088B		JE_1 <BB#9>, %EFLAGS<imp-use,kill>
1104B		JMP_1 <BB#10>
	    Successors according to CFG: BB#9 BB#10

1120B	BB#7: derived from LLVM BB %sw.bb
	    Predecessors according to CFG: BB#4
1136B		%vreg125<def> = MOV8rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%ch] GR8:%vreg125
1152B		%vreg124<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg124
1168B		%vreg122<def> = MOVSX64rm32 %vreg124, 1, %noreg, 108, %noreg; mem:LD4[%nblock] GR64_NOSP:%vreg122 GR64:%vreg124
1184B		%vreg120<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg120
1200B		%vreg119<def> = MOV64rm %vreg120, 1, %noreg, 64, %noreg; mem:LD8[%block] GR64:%vreg119,%vreg120
1216B		MOV8mr %vreg119, 1, %vreg122, 0, %noreg, %vreg125; mem:ST1[%arrayidx11] GR64:%vreg119 GR64_NOSP:%vreg122 GR8:%vreg125
1232B		%vreg114<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg114
1248B		%vreg112<def> = MOV32rm %vreg114, 1, %noreg, 108, %noreg; mem:LD4[%nblock12] GR32:%vreg112 GR64:%vreg114
1280B		%vreg112<def,tied1> = ADD32ri8 %vreg112<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg112
1296B		MOV32mr %vreg114, 1, %noreg, 108, %noreg, %vreg112; mem:ST4[%nblock12] GR64:%vreg114 GR32:%vreg112
1312B		JMP_1 <BB#11>
	    Successors according to CFG: BB#11

1328B	BB#8: derived from LLVM BB %sw.bb.14
	    Predecessors according to CFG: BB#5
1344B		%vreg108<def> = MOV8rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%ch] GR8:%vreg108
1360B		%vreg107<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg107
1376B		%vreg105<def> = MOVSX64rm32 %vreg107, 1, %noreg, 108, %noreg; mem:LD4[%nblock15] GR64_NOSP:%vreg105 GR64:%vreg107
1392B		%vreg103<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg103
1408B		%vreg102<def> = MOV64rm %vreg103, 1, %noreg, 64, %noreg; mem:LD8[%block17] GR64:%vreg102,%vreg103
1424B		MOV8mr %vreg102, 1, %vreg105, 0, %noreg, %vreg108; mem:ST1[%arrayidx18] GR64:%vreg102 GR64_NOSP:%vreg105 GR8:%vreg108
1440B		%vreg97<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg97
1456B		%vreg95<def> = MOV32rm %vreg97, 1, %noreg, 108, %noreg; mem:LD4[%nblock19] GR32:%vreg95 GR64:%vreg97
1488B		%vreg95<def,tied1> = ADD32ri8 %vreg95<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg95
1504B		MOV32mr %vreg97, 1, %noreg, 108, %noreg, %vreg95; mem:ST4[%nblock19] GR64:%vreg97 GR32:%vreg95
1520B		%vreg91<def> = MOV8rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%ch] GR8:%vreg91
1536B		%vreg90<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg90
1552B		%vreg88<def> = MOVSX64rm32 %vreg90, 1, %noreg, 108, %noreg; mem:LD4[%nblock21] GR64_NOSP:%vreg88 GR64:%vreg90
1568B		%vreg86<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg86
1584B		%vreg85<def> = MOV64rm %vreg86, 1, %noreg, 64, %noreg; mem:LD8[%block23] GR64:%vreg85,%vreg86
1600B		MOV8mr %vreg85, 1, %vreg88, 0, %noreg, %vreg91; mem:ST1[%arrayidx24] GR64:%vreg85 GR64_NOSP:%vreg88 GR8:%vreg91
1616B		%vreg80<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg80
1632B		%vreg78<def> = MOV32rm %vreg80, 1, %noreg, 108, %noreg; mem:LD4[%nblock25] GR32:%vreg78 GR64:%vreg80
1664B		%vreg78<def,tied1> = ADD32ri8 %vreg78<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg78
1680B		MOV32mr %vreg80, 1, %noreg, 108, %noreg, %vreg78; mem:ST4[%nblock25] GR64:%vreg80 GR32:%vreg78
1696B		JMP_1 <BB#11>
	    Successors according to CFG: BB#11

1712B	BB#9: derived from LLVM BB %sw.bb.27
	    Predecessors according to CFG: BB#6
1728B		%vreg74<def> = MOV8rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%ch] GR8:%vreg74
1744B		%vreg73<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg73
1760B		%vreg71<def> = MOVSX64rm32 %vreg73, 1, %noreg, 108, %noreg; mem:LD4[%nblock28] GR64_NOSP:%vreg71 GR64:%vreg73
1776B		%vreg69<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg69
1792B		%vreg68<def> = MOV64rm %vreg69, 1, %noreg, 64, %noreg; mem:LD8[%block30] GR64:%vreg68,%vreg69
1808B		MOV8mr %vreg68, 1, %vreg71, 0, %noreg, %vreg74; mem:ST1[%arrayidx31] GR64:%vreg68 GR64_NOSP:%vreg71 GR8:%vreg74
1824B		%vreg63<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg63
1840B		%vreg61<def> = MOV32rm %vreg63, 1, %noreg, 108, %noreg; mem:LD4[%nblock32] GR32:%vreg61 GR64:%vreg63
1872B		%vreg61<def,tied1> = ADD32ri8 %vreg61<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg61
1888B		MOV32mr %vreg63, 1, %noreg, 108, %noreg, %vreg61; mem:ST4[%nblock32] GR64:%vreg63 GR32:%vreg61
1904B		%vreg57<def> = MOV8rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%ch] GR8:%vreg57
1920B		%vreg56<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg56
1936B		%vreg54<def> = MOVSX64rm32 %vreg56, 1, %noreg, 108, %noreg; mem:LD4[%nblock34] GR64_NOSP:%vreg54 GR64:%vreg56
1952B		%vreg52<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg52
1968B		%vreg51<def> = MOV64rm %vreg52, 1, %noreg, 64, %noreg; mem:LD8[%block36] GR64:%vreg51,%vreg52
1984B		MOV8mr %vreg51, 1, %vreg54, 0, %noreg, %vreg57; mem:ST1[%arrayidx37] GR64:%vreg51 GR64_NOSP:%vreg54 GR8:%vreg57
2000B		%vreg46<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg46
2016B		%vreg44<def> = MOV32rm %vreg46, 1, %noreg, 108, %noreg; mem:LD4[%nblock38] GR32:%vreg44 GR64:%vreg46
2048B		%vreg44<def,tied1> = ADD32ri8 %vreg44<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg44
2064B		MOV32mr %vreg46, 1, %noreg, 108, %noreg, %vreg44; mem:ST4[%nblock38] GR64:%vreg46 GR32:%vreg44
2080B		%vreg40<def> = MOV8rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%ch] GR8:%vreg40
2096B		%vreg39<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg39
2112B		%vreg37<def> = MOVSX64rm32 %vreg39, 1, %noreg, 108, %noreg; mem:LD4[%nblock40] GR64_NOSP:%vreg37 GR64:%vreg39
2128B		%vreg35<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg35
2144B		%vreg34<def> = MOV64rm %vreg35, 1, %noreg, 64, %noreg; mem:LD8[%block42] GR64:%vreg34,%vreg35
2160B		MOV8mr %vreg34, 1, %vreg37, 0, %noreg, %vreg40; mem:ST1[%arrayidx43] GR64:%vreg34 GR64_NOSP:%vreg37 GR8:%vreg40
2176B		%vreg29<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg29
2192B		%vreg27<def> = MOV32rm %vreg29, 1, %noreg, 108, %noreg; mem:LD4[%nblock44] GR32:%vreg27 GR64:%vreg29
2224B		%vreg27<def,tied1> = ADD32ri8 %vreg27<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg27
2240B		MOV32mr %vreg29, 1, %noreg, 108, %noreg, %vreg27; mem:ST4[%nblock44] GR64:%vreg29 GR32:%vreg27
2256B		JMP_1 <BB#11>
	    Successors according to CFG: BB#11

2272B	BB#10: derived from LLVM BB %sw.default
	    Predecessors according to CFG: BB#6
2288B		%vreg226<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg226
2304B		%vreg223<def> = MOV32rm %vreg226, 1, %noreg, 96, %noreg; mem:LD4[%state_in_len46] GR32:%vreg223 GR64:%vreg226
2336B		%vreg223<def,tied1> = SUB32ri8 %vreg223<tied0>, 4, %EFLAGS<imp-def,dead>; GR32:%vreg223
2352B		%vreg221<def> = MOVSX64rr32 %vreg223; GR64_NOSP:%vreg221 GR32:%vreg223
2368B		%vreg219<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg219
2384B		MOV8mi %vreg219, 1, %vreg221, 128, %noreg, 1; mem:ST1[%arrayidx49] GR64:%vreg219 GR64_NOSP:%vreg221
2400B		%vreg216<def> = MOV8rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%ch] GR8:%vreg216
2416B		%vreg215<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg215
2432B		%vreg213<def> = MOVSX64rm32 %vreg215, 1, %noreg, 108, %noreg; mem:LD4[%nblock50] GR64_NOSP:%vreg213 GR64:%vreg215
2448B		%vreg211<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg211
2464B		%vreg210<def> = MOV64rm %vreg211, 1, %noreg, 64, %noreg; mem:LD8[%block52] GR64:%vreg210,%vreg211
2480B		MOV8mr %vreg210, 1, %vreg213, 0, %noreg, %vreg216; mem:ST1[%arrayidx53] GR64:%vreg210 GR64_NOSP:%vreg213 GR8:%vreg216
2496B		%vreg205<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg205
2512B		%vreg203<def> = MOV32rm %vreg205, 1, %noreg, 108, %noreg; mem:LD4[%nblock54] GR32:%vreg203 GR64:%vreg205
2544B		%vreg203<def,tied1> = ADD32ri8 %vreg203<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg203
2560B		MOV32mr %vreg205, 1, %noreg, 108, %noreg, %vreg203; mem:ST4[%nblock54] GR64:%vreg205 GR32:%vreg203
2576B		%vreg199<def> = MOV8rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%ch] GR8:%vreg199
2592B		%vreg198<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg198
2608B		%vreg196<def> = MOVSX64rm32 %vreg198, 1, %noreg, 108, %noreg; mem:LD4[%nblock56] GR64_NOSP:%vreg196 GR64:%vreg198
2624B		%vreg194<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg194
2640B		%vreg193<def> = MOV64rm %vreg194, 1, %noreg, 64, %noreg; mem:LD8[%block58] GR64:%vreg193,%vreg194
2656B		MOV8mr %vreg193, 1, %vreg196, 0, %noreg, %vreg199; mem:ST1[%arrayidx59] GR64:%vreg193 GR64_NOSP:%vreg196 GR8:%vreg199
2672B		%vreg188<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg188
2688B		%vreg186<def> = MOV32rm %vreg188, 1, %noreg, 108, %noreg; mem:LD4[%nblock60] GR32:%vreg186 GR64:%vreg188
2720B		%vreg186<def,tied1> = ADD32ri8 %vreg186<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg186
2736B		MOV32mr %vreg188, 1, %noreg, 108, %noreg, %vreg186; mem:ST4[%nblock60] GR64:%vreg188 GR32:%vreg186
2752B		%vreg182<def> = MOV8rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%ch] GR8:%vreg182
2768B		%vreg181<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg181
2784B		%vreg179<def> = MOVSX64rm32 %vreg181, 1, %noreg, 108, %noreg; mem:LD4[%nblock62] GR64_NOSP:%vreg179 GR64:%vreg181
2800B		%vreg177<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg177
2816B		%vreg176<def> = MOV64rm %vreg177, 1, %noreg, 64, %noreg; mem:LD8[%block64] GR64:%vreg176,%vreg177
2832B		MOV8mr %vreg176, 1, %vreg179, 0, %noreg, %vreg182; mem:ST1[%arrayidx65] GR64:%vreg176 GR64_NOSP:%vreg179 GR8:%vreg182
2848B		%vreg171<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg171
2864B		%vreg169<def> = MOV32rm %vreg171, 1, %noreg, 108, %noreg; mem:LD4[%nblock66] GR32:%vreg169 GR64:%vreg171
2896B		%vreg169<def,tied1> = ADD32ri8 %vreg169<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg169
2912B		MOV32mr %vreg171, 1, %noreg, 108, %noreg, %vreg169; mem:ST4[%nblock66] GR64:%vreg171 GR32:%vreg169
2928B		%vreg165<def> = MOV8rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%ch] GR8:%vreg165
2944B		%vreg164<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg164
2960B		%vreg162<def> = MOVSX64rm32 %vreg164, 1, %noreg, 108, %noreg; mem:LD4[%nblock68] GR64_NOSP:%vreg162 GR64:%vreg164
2976B		%vreg160<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg160
2992B		%vreg159<def> = MOV64rm %vreg160, 1, %noreg, 64, %noreg; mem:LD8[%block70] GR64:%vreg159,%vreg160
3008B		MOV8mr %vreg159, 1, %vreg162, 0, %noreg, %vreg165; mem:ST1[%arrayidx71] GR64:%vreg159 GR64_NOSP:%vreg162 GR8:%vreg165
3024B		%vreg154<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg154
3040B		%vreg152<def> = MOV32rm %vreg154, 1, %noreg, 108, %noreg; mem:LD4[%nblock72] GR32:%vreg152 GR64:%vreg154
3072B		%vreg152<def,tied1> = ADD32ri8 %vreg152<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg152
3088B		MOV32mr %vreg154, 1, %noreg, 108, %noreg, %vreg152; mem:ST4[%nblock72] GR64:%vreg154 GR32:%vreg152
3104B		%vreg148<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg148
3120B		%vreg145<def> = MOV32rm %vreg148, 1, %noreg, 96, %noreg; mem:LD4[%state_in_len74] GR32:%vreg145 GR64:%vreg148
3152B		%vreg145<def,tied1> = SUB32ri8 %vreg145<tied0>, 4, %EFLAGS<imp-def,dead>; GR32:%vreg145
3184B		%vreg141<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg141
3200B		%vreg139<def> = MOVSX64rm32 %vreg141, 1, %noreg, 108, %noreg; mem:LD4[%nblock77] GR64_NOSP:%vreg139 GR64:%vreg141
3216B		%vreg137<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg137
3232B		%vreg136<def> = MOV64rm %vreg137, 1, %noreg, 64, %noreg; mem:LD8[%block79] GR64:%vreg136,%vreg137
3248B		MOV8mr %vreg136, 1, %vreg139, 0, %noreg, %vreg145:sub_8bit; mem:ST1[%arrayidx80] GR64:%vreg136 GR64_NOSP:%vreg139 GR32:%vreg145
3264B		%vreg131<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg131
3280B		%vreg129<def> = MOV32rm %vreg131, 1, %noreg, 108, %noreg; mem:LD4[%nblock81] GR32:%vreg129 GR64:%vreg131
3312B		%vreg129<def,tied1> = ADD32ri8 %vreg129<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg129
3328B		MOV32mr %vreg131, 1, %noreg, 108, %noreg, %vreg129; mem:ST4[%nblock81] GR64:%vreg131 GR32:%vreg129
	    Successors according to CFG: BB#11

3344B	BB#11: derived from LLVM BB %sw.epilog
	    Predecessors according to CFG: BB#9 BB#8 BB#7 BB#10
3360B		%vreg228<def> = MOV64ri <ga:@add_pair_to_block>; GR64:%vreg228
3392B		%vreg229<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg229
3408B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3424B		%RDI<def> = COPY %vreg228; GR64:%vreg228
3440B		%RSI<def> = COPY %vreg229; GR64:%vreg229
3456B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
3472B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3488B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3504B		STACKMAP 1, 0, ...
3520B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3536B		RETQ

# End machine code for function add_pair_to_block.

AllocationOrder(SEGMENT_REG) = [ ]
AllocationOrder(SEGMENT_REG) = [ ]
AllocationOrder(SEGMENT_REG) = [ ]
AllocationOrder(SEGMENT_REG) = [ ]
AllocationOrder(SEGMENT_REG) = [ ]
********** GREEDY REGISTER ALLOCATION **********
********** Function: add_pair_to_block
********** INTERVALS **********
DIL [0B,16r:0)[112r,144r:2)[3424r,3456r:1)  0@0B-phi 1@3424r 2@112r
%vreg1 [16r,224r:0)  0@16r
%vreg6 [256r,288r:0)  0@256r
%vreg7 [240r,256r:0)  0@240r
%vreg9 [48r,112r:0)  0@48r
%vreg10 [80r,128r:0)  0@80r
%vreg14 [352r,368r:0)  0@352r
%vreg15 [336r,368r:0)  0@336r
%vreg17 [800r,848r:0)  0@800r
%vreg19 [816r,848r:0)  0@816r
%vreg20 [864r,880r:0)  0@864r
%vreg21 [896r,912r:0)[912r,912d:1)  0@896r 1@912r
%vreg22 [976r,992r:0)[992r,992d:1)  0@976r 1@992r
%vreg23 [880r,1072r:0)[1072r,1072d:1)  0@880r 1@1072r
%vreg27 [2192r,2224r:0)[2224r,2240r:1)  0@2192r 1@2224r
%vreg29 [2176r,2240r:0)  0@2176r
%vreg34 [2144r,2160r:0)  0@2144r
%vreg35 [2128r,2144r:0)  0@2128r
%vreg37 [2112r,2160r:0)  0@2112r
%vreg39 [2096r,2112r:0)  0@2096r
%vreg40 [2080r,2160r:0)  0@2080r
%vreg44 [2016r,2048r:0)[2048r,2064r:1)  0@2016r 1@2048r
%vreg46 [2000r,2064r:0)  0@2000r
%vreg51 [1968r,1984r:0)  0@1968r
%vreg52 [1952r,1968r:0)  0@1952r
%vreg54 [1936r,1984r:0)  0@1936r
%vreg56 [1920r,1936r:0)  0@1920r
%vreg57 [1904r,1984r:0)  0@1904r
%vreg61 [1840r,1872r:0)[1872r,1888r:1)  0@1840r 1@1872r
%vreg63 [1824r,1888r:0)  0@1824r
%vreg68 [1792r,1808r:0)  0@1792r
%vreg69 [1776r,1792r:0)  0@1776r
%vreg71 [1760r,1808r:0)  0@1760r
%vreg73 [1744r,1760r:0)  0@1744r
%vreg74 [1728r,1808r:0)  0@1728r
%vreg78 [1632r,1664r:0)[1664r,1680r:1)  0@1632r 1@1664r
%vreg80 [1616r,1680r:0)  0@1616r
%vreg85 [1584r,1600r:0)  0@1584r
%vreg86 [1568r,1584r:0)  0@1568r
%vreg88 [1552r,1600r:0)  0@1552r
%vreg90 [1536r,1552r:0)  0@1536r
%vreg91 [1520r,1600r:0)  0@1520r
%vreg95 [1456r,1488r:0)[1488r,1504r:1)  0@1456r 1@1488r
%vreg97 [1440r,1504r:0)  0@1440r
%vreg102 [1408r,1424r:0)  0@1408r
%vreg103 [1392r,1408r:0)  0@1392r
%vreg105 [1376r,1424r:0)  0@1376r
%vreg107 [1360r,1376r:0)  0@1360r
%vreg108 [1344r,1424r:0)  0@1344r
%vreg112 [1248r,1280r:0)[1280r,1296r:1)  0@1248r 1@1280r
%vreg114 [1232r,1296r:0)  0@1232r
%vreg119 [1200r,1216r:0)  0@1200r
%vreg120 [1184r,1200r:0)  0@1184r
%vreg122 [1168r,1216r:0)  0@1168r
%vreg124 [1152r,1168r:0)  0@1152r
%vreg125 [1136r,1216r:0)  0@1136r
%vreg129 [3280r,3312r:0)[3312r,3328r:1)  0@3280r 1@3312r
%vreg131 [3264r,3328r:0)  0@3264r
%vreg136 [3232r,3248r:0)  0@3232r
%vreg137 [3216r,3232r:0)  0@3216r
%vreg139 [3200r,3248r:0)  0@3200r
%vreg141 [3184r,3200r:0)  0@3184r
%vreg145 [3120r,3152r:0)[3152r,3248r:1)  0@3120r 1@3152r
%vreg148 [3104r,3120r:0)  0@3104r
%vreg152 [3040r,3072r:0)[3072r,3088r:1)  0@3040r 1@3072r
%vreg154 [3024r,3088r:0)  0@3024r
%vreg159 [2992r,3008r:0)  0@2992r
%vreg160 [2976r,2992r:0)  0@2976r
%vreg162 [2960r,3008r:0)  0@2960r
%vreg164 [2944r,2960r:0)  0@2944r
%vreg165 [2928r,3008r:0)  0@2928r
%vreg169 [2864r,2896r:0)[2896r,2912r:1)  0@2864r 1@2896r
%vreg171 [2848r,2912r:0)  0@2848r
%vreg176 [2816r,2832r:0)  0@2816r
%vreg177 [2800r,2816r:0)  0@2800r
%vreg179 [2784r,2832r:0)  0@2784r
%vreg181 [2768r,2784r:0)  0@2768r
%vreg182 [2752r,2832r:0)  0@2752r
%vreg186 [2688r,2720r:0)[2720r,2736r:1)  0@2688r 1@2720r
%vreg188 [2672r,2736r:0)  0@2672r
%vreg193 [2640r,2656r:0)  0@2640r
%vreg194 [2624r,2640r:0)  0@2624r
%vreg196 [2608r,2656r:0)  0@2608r
%vreg198 [2592r,2608r:0)  0@2592r
%vreg199 [2576r,2656r:0)  0@2576r
%vreg203 [2512r,2544r:0)[2544r,2560r:1)  0@2512r 1@2544r
%vreg205 [2496r,2560r:0)  0@2496r
%vreg210 [2464r,2480r:0)  0@2464r
%vreg211 [2448r,2464r:0)  0@2448r
%vreg213 [2432r,2480r:0)  0@2432r
%vreg215 [2416r,2432r:0)  0@2416r
%vreg216 [2400r,2480r:0)  0@2400r
%vreg219 [2368r,2384r:0)  0@2368r
%vreg221 [2352r,2384r:0)  0@2352r
%vreg223 [2304r,2336r:0)[2336r,2352r:1)  0@2304r 1@2336r
%vreg226 [2288r,2304r:0)  0@2288r
%vreg228 [3360r,3424r:0)  0@3360r
%vreg229 [3392r,3440r:0)  0@3392r
%vreg232 [656r,672r:0)  0@656r
%vreg235 [432r,464r:2)[464r,640r:0)[640r,672r:1)  0@464r 1@640r 2@432r
%vreg239 [592r,640r:0)  0@592r
%vreg242 [496r,528r:2)[528r,576r:0)[576r,592r:1)  0@528r 1@576r 2@496r
%vreg244 [544r,576r:0)  0@544r
%vreg249 [480r,496r:0)  0@480r
%vreg254 [416r,432r:0)  0@416r
%vreg257 [704r,736r:0)[736r,752r:1)  0@704r 1@736r
RegMasks: 144r 3456r
********** MACHINEINSTRS **********
# Machine code for function add_pair_to_block: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP]
  fi#0: size=8, align=8, at location [SP+8]
  fi#1: size=4, align=4, at location [SP+8]
  fi#2: size=1, align=1, at location [SP+8]
Function Live Ins: %RDI in %vreg0

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI
16B		%vreg1<def> = COPY %RDI; GR64:%vreg1
48B		%vreg9<def> = MOV64ri <ga:@add_pair_to_block>; GR64:%vreg9
80B		%vreg10<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg10
96B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
112B		%RDI<def> = COPY %vreg9; GR64:%vreg9
128B		%RSI<def> = COPY %vreg10; GR64:%vreg10
144B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
160B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
192B		STACKMAP 0, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack1](align=4) LD8[FixedStack0] GR64:%vreg1
208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1; mem:ST8[%s.addr] GR64:%vreg1
240B		%vreg7<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg7
256B		%vreg6<def> = MOV32rm %vreg7, 1, %noreg, 92, %noreg; mem:LD4[%state_in_ch] GR32:%vreg6 GR64:%vreg7
288B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg6:sub_8bit; mem:ST1[%ch] GR32:%vreg6
304B		MOV32mi <fi#1>, 1, %noreg, 0, %noreg, 0; mem:ST4[%i]
	    Successors according to CFG: BB#1

320B	BB#1: derived from LLVM BB %for.cond
	    Predecessors according to CFG: BB#0 BB#3
336B		%vreg15<def> = MOV32rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD4[%i] GR32:%vreg15
352B		%vreg14<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg14
368B		CMP32rm %vreg15, %vreg14, 1, %noreg, 96, %noreg, %EFLAGS<imp-def>; mem:LD4[%state_in_len] GR32:%vreg15 GR64:%vreg14
384B		JGE_1 <BB#4>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#4 BB#2

400B	BB#2: derived from LLVM BB %for.body
	    Predecessors according to CFG: BB#1
416B		%vreg254<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg254
432B		%vreg235<def> = MOV32rm %vreg254, 1, %noreg, 648, %noreg; mem:LD4[%blockCRC] GR32:%vreg235 GR64:%vreg254
464B		%vreg235<def,tied1> = SHL32ri %vreg235<tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg235
480B		%vreg249<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg249
496B		%vreg242<def> = MOV32rm %vreg249, 1, %noreg, 648, %noreg; mem:LD4[%blockCRC2] GR32:%vreg242 GR64:%vreg249
528B		%vreg242<def,tied1> = SHR32ri %vreg242<tied0>, 24, %EFLAGS<imp-def,dead>; GR32:%vreg242
544B		%vreg244<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%ch] GR32:%vreg244
576B		%vreg242<def,tied1> = XOR32rr %vreg242<tied0>, %vreg244, %EFLAGS<imp-def,dead>; GR32:%vreg242,%vreg244
592B		%vreg239:sub_32bit<def,read-undef> = MOV32rr %vreg242; GR64_NOSP:%vreg239 GR32:%vreg242
640B		%vreg235<def,tied1> = XOR32rm %vreg235<tied0>, %noreg, 4, %vreg239, <ga:@BZ2_crc32Table>, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%arrayidx] GR32:%vreg235 GR64_NOSP:%vreg239
656B		%vreg232<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg232
672B		MOV32mr %vreg232, 1, %noreg, 648, %noreg, %vreg235; mem:ST4[%blockCRC5] GR64:%vreg232 GR32:%vreg235
	    Successors according to CFG: BB#3

688B	BB#3: derived from LLVM BB %for.inc
	    Predecessors according to CFG: BB#2
704B		%vreg257<def> = MOV32rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD4[%i] GR32:%vreg257
736B		%vreg257<def,tied1> = ADD32ri8 %vreg257<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg257
752B		MOV32mr <fi#1>, 1, %noreg, 0, %noreg, %vreg257; mem:ST4[%i] GR32:%vreg257
768B		JMP_1 <BB#1>
	    Successors according to CFG: BB#1

784B	BB#4: derived from LLVM BB %for.end
	    Predecessors according to CFG: BB#1
800B		%vreg17<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg17
816B		%vreg19:sub_32bit<def,read-undef> = MOV32rm %vreg17, 1, %noreg, 92, %noreg; mem:LD4[%state_in_ch6] GR64_NOSP:%vreg19 GR64:%vreg17
848B		MOV8mi %vreg17, 1, %vreg19, 128, %noreg, 1; mem:ST1[%arrayidx8] GR64:%vreg17 GR64_NOSP:%vreg19
864B		%vreg20<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg20
880B		%vreg23<def> = MOV32rm %vreg20, 1, %noreg, 96, %noreg; mem:LD4[%state_in_len9] GR32:%vreg23 GR64:%vreg20
896B		%vreg21<def> = COPY %vreg23; GR32:%vreg21,%vreg23
912B		%vreg21<def,dead,tied1> = SUB32ri8 %vreg21<tied0>, 1, %EFLAGS<imp-def>; GR32:%vreg21
928B		JE_1 <BB#7>, %EFLAGS<imp-use,kill>
944B		JMP_1 <BB#5>
	    Successors according to CFG: BB#7 BB#5

960B	BB#5: derived from LLVM BB %for.end
	    Predecessors according to CFG: BB#4
976B		%vreg22<def> = COPY %vreg23; GR32:%vreg22,%vreg23
992B		%vreg22<def,dead,tied1> = SUB32ri8 %vreg22<tied0>, 2, %EFLAGS<imp-def>; GR32:%vreg22
1008B		JE_1 <BB#8>, %EFLAGS<imp-use,kill>
1024B		JMP_1 <BB#6>
	    Successors according to CFG: BB#8 BB#6

1040B	BB#6: derived from LLVM BB %for.end
	    Predecessors according to CFG: BB#5
1072B		%vreg23<def,dead,tied1> = SUB32ri8 %vreg23<tied0>, 3, %EFLAGS<imp-def>; GR32:%vreg23
1088B		JE_1 <BB#9>, %EFLAGS<imp-use,kill>
1104B		JMP_1 <BB#10>
	    Successors according to CFG: BB#9 BB#10

1120B	BB#7: derived from LLVM BB %sw.bb
	    Predecessors according to CFG: BB#4
1136B		%vreg125<def> = MOV8rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%ch] GR8:%vreg125
1152B		%vreg124<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg124
1168B		%vreg122<def> = MOVSX64rm32 %vreg124, 1, %noreg, 108, %noreg; mem:LD4[%nblock] GR64_NOSP:%vreg122 GR64:%vreg124
1184B		%vreg120<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg120
1200B		%vreg119<def> = MOV64rm %vreg120, 1, %noreg, 64, %noreg; mem:LD8[%block] GR64:%vreg119,%vreg120
1216B		MOV8mr %vreg119, 1, %vreg122, 0, %noreg, %vreg125; mem:ST1[%arrayidx11] GR64:%vreg119 GR64_NOSP:%vreg122 GR8:%vreg125
1232B		%vreg114<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg114
1248B		%vreg112<def> = MOV32rm %vreg114, 1, %noreg, 108, %noreg; mem:LD4[%nblock12] GR32:%vreg112 GR64:%vreg114
1280B		%vreg112<def,tied1> = ADD32ri8 %vreg112<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg112
1296B		MOV32mr %vreg114, 1, %noreg, 108, %noreg, %vreg112; mem:ST4[%nblock12] GR64:%vreg114 GR32:%vreg112
1312B		JMP_1 <BB#11>
	    Successors according to CFG: BB#11

1328B	BB#8: derived from LLVM BB %sw.bb.14
	    Predecessors according to CFG: BB#5
1344B		%vreg108<def> = MOV8rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%ch] GR8:%vreg108
1360B		%vreg107<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg107
1376B		%vreg105<def> = MOVSX64rm32 %vreg107, 1, %noreg, 108, %noreg; mem:LD4[%nblock15] GR64_NOSP:%vreg105 GR64:%vreg107
1392B		%vreg103<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg103
1408B		%vreg102<def> = MOV64rm %vreg103, 1, %noreg, 64, %noreg; mem:LD8[%block17] GR64:%vreg102,%vreg103
1424B		MOV8mr %vreg102, 1, %vreg105, 0, %noreg, %vreg108; mem:ST1[%arrayidx18] GR64:%vreg102 GR64_NOSP:%vreg105 GR8:%vreg108
1440B		%vreg97<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg97
1456B		%vreg95<def> = MOV32rm %vreg97, 1, %noreg, 108, %noreg; mem:LD4[%nblock19] GR32:%vreg95 GR64:%vreg97
1488B		%vreg95<def,tied1> = ADD32ri8 %vreg95<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg95
1504B		MOV32mr %vreg97, 1, %noreg, 108, %noreg, %vreg95; mem:ST4[%nblock19] GR64:%vreg97 GR32:%vreg95
1520B		%vreg91<def> = MOV8rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%ch] GR8:%vreg91
1536B		%vreg90<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg90
1552B		%vreg88<def> = MOVSX64rm32 %vreg90, 1, %noreg, 108, %noreg; mem:LD4[%nblock21] GR64_NOSP:%vreg88 GR64:%vreg90
1568B		%vreg86<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg86
1584B		%vreg85<def> = MOV64rm %vreg86, 1, %noreg, 64, %noreg; mem:LD8[%block23] GR64:%vreg85,%vreg86
1600B		MOV8mr %vreg85, 1, %vreg88, 0, %noreg, %vreg91; mem:ST1[%arrayidx24] GR64:%vreg85 GR64_NOSP:%vreg88 GR8:%vreg91
1616B		%vreg80<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg80
1632B		%vreg78<def> = MOV32rm %vreg80, 1, %noreg, 108, %noreg; mem:LD4[%nblock25] GR32:%vreg78 GR64:%vreg80
1664B		%vreg78<def,tied1> = ADD32ri8 %vreg78<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg78
1680B		MOV32mr %vreg80, 1, %noreg, 108, %noreg, %vreg78; mem:ST4[%nblock25] GR64:%vreg80 GR32:%vreg78
1696B		JMP_1 <BB#11>
	    Successors according to CFG: BB#11

1712B	BB#9: derived from LLVM BB %sw.bb.27
	    Predecessors according to CFG: BB#6
1728B		%vreg74<def> = MOV8rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%ch] GR8:%vreg74
1744B		%vreg73<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg73
1760B		%vreg71<def> = MOVSX64rm32 %vreg73, 1, %noreg, 108, %noreg; mem:LD4[%nblock28] GR64_NOSP:%vreg71 GR64:%vreg73
1776B		%vreg69<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg69
1792B		%vreg68<def> = MOV64rm %vreg69, 1, %noreg, 64, %noreg; mem:LD8[%block30] GR64:%vreg68,%vreg69
1808B		MOV8mr %vreg68, 1, %vreg71, 0, %noreg, %vreg74; mem:ST1[%arrayidx31] GR64:%vreg68 GR64_NOSP:%vreg71 GR8:%vreg74
1824B		%vreg63<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg63
1840B		%vreg61<def> = MOV32rm %vreg63, 1, %noreg, 108, %noreg; mem:LD4[%nblock32] GR32:%vreg61 GR64:%vreg63
1872B		%vreg61<def,tied1> = ADD32ri8 %vreg61<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg61
1888B		MOV32mr %vreg63, 1, %noreg, 108, %noreg, %vreg61; mem:ST4[%nblock32] GR64:%vreg63 GR32:%vreg61
1904B		%vreg57<def> = MOV8rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%ch] GR8:%vreg57
1920B		%vreg56<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg56
1936B		%vreg54<def> = MOVSX64rm32 %vreg56, 1, %noreg, 108, %noreg; mem:LD4[%nblock34] GR64_NOSP:%vreg54 GR64:%vreg56
1952B		%vreg52<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg52
1968B		%vreg51<def> = MOV64rm %vreg52, 1, %noreg, 64, %noreg; mem:LD8[%block36] GR64:%vreg51,%vreg52
1984B		MOV8mr %vreg51, 1, %vreg54, 0, %noreg, %vreg57; mem:ST1[%arrayidx37] GR64:%vreg51 GR64_NOSP:%vreg54 GR8:%vreg57
2000B		%vreg46<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg46
2016B		%vreg44<def> = MOV32rm %vreg46, 1, %noreg, 108, %noreg; mem:LD4[%nblock38] GR32:%vreg44 GR64:%vreg46
2048B		%vreg44<def,tied1> = ADD32ri8 %vreg44<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg44
2064B		MOV32mr %vreg46, 1, %noreg, 108, %noreg, %vreg44; mem:ST4[%nblock38] GR64:%vreg46 GR32:%vreg44
2080B		%vreg40<def> = MOV8rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%ch] GR8:%vreg40
2096B		%vreg39<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg39
2112B		%vreg37<def> = MOVSX64rm32 %vreg39, 1, %noreg, 108, %noreg; mem:LD4[%nblock40] GR64_NOSP:%vreg37 GR64:%vreg39
2128B		%vreg35<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg35
2144B		%vreg34<def> = MOV64rm %vreg35, 1, %noreg, 64, %noreg; mem:LD8[%block42] GR64:%vreg34,%vreg35
2160B		MOV8mr %vreg34, 1, %vreg37, 0, %noreg, %vreg40; mem:ST1[%arrayidx43] GR64:%vreg34 GR64_NOSP:%vreg37 GR8:%vreg40
2176B		%vreg29<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg29
2192B		%vreg27<def> = MOV32rm %vreg29, 1, %noreg, 108, %noreg; mem:LD4[%nblock44] GR32:%vreg27 GR64:%vreg29
2224B		%vreg27<def,tied1> = ADD32ri8 %vreg27<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg27
2240B		MOV32mr %vreg29, 1, %noreg, 108, %noreg, %vreg27; mem:ST4[%nblock44] GR64:%vreg29 GR32:%vreg27
2256B		JMP_1 <BB#11>
	    Successors according to CFG: BB#11

2272B	BB#10: derived from LLVM BB %sw.default
	    Predecessors according to CFG: BB#6
2288B		%vreg226<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg226
2304B		%vreg223<def> = MOV32rm %vreg226, 1, %noreg, 96, %noreg; mem:LD4[%state_in_len46] GR32:%vreg223 GR64:%vreg226
2336B		%vreg223<def,tied1> = SUB32ri8 %vreg223<tied0>, 4, %EFLAGS<imp-def,dead>; GR32:%vreg223
2352B		%vreg221<def> = MOVSX64rr32 %vreg223; GR64_NOSP:%vreg221 GR32:%vreg223
2368B		%vreg219<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg219
2384B		MOV8mi %vreg219, 1, %vreg221, 128, %noreg, 1; mem:ST1[%arrayidx49] GR64:%vreg219 GR64_NOSP:%vreg221
2400B		%vreg216<def> = MOV8rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%ch] GR8:%vreg216
2416B		%vreg215<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg215
2432B		%vreg213<def> = MOVSX64rm32 %vreg215, 1, %noreg, 108, %noreg; mem:LD4[%nblock50] GR64_NOSP:%vreg213 GR64:%vreg215
2448B		%vreg211<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg211
2464B		%vreg210<def> = MOV64rm %vreg211, 1, %noreg, 64, %noreg; mem:LD8[%block52] GR64:%vreg210,%vreg211
2480B		MOV8mr %vreg210, 1, %vreg213, 0, %noreg, %vreg216; mem:ST1[%arrayidx53] GR64:%vreg210 GR64_NOSP:%vreg213 GR8:%vreg216
2496B		%vreg205<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg205
2512B		%vreg203<def> = MOV32rm %vreg205, 1, %noreg, 108, %noreg; mem:LD4[%nblock54] GR32:%vreg203 GR64:%vreg205
2544B		%vreg203<def,tied1> = ADD32ri8 %vreg203<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg203
2560B		MOV32mr %vreg205, 1, %noreg, 108, %noreg, %vreg203; mem:ST4[%nblock54] GR64:%vreg205 GR32:%vreg203
2576B		%vreg199<def> = MOV8rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%ch] GR8:%vreg199
2592B		%vreg198<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg198
2608B		%vreg196<def> = MOVSX64rm32 %vreg198, 1, %noreg, 108, %noreg; mem:LD4[%nblock56] GR64_NOSP:%vreg196 GR64:%vreg198
2624B		%vreg194<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg194
2640B		%vreg193<def> = MOV64rm %vreg194, 1, %noreg, 64, %noreg; mem:LD8[%block58] GR64:%vreg193,%vreg194
2656B		MOV8mr %vreg193, 1, %vreg196, 0, %noreg, %vreg199; mem:ST1[%arrayidx59] GR64:%vreg193 GR64_NOSP:%vreg196 GR8:%vreg199
2672B		%vreg188<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg188
2688B		%vreg186<def> = MOV32rm %vreg188, 1, %noreg, 108, %noreg; mem:LD4[%nblock60] GR32:%vreg186 GR64:%vreg188
2720B		%vreg186<def,tied1> = ADD32ri8 %vreg186<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg186
2736B		MOV32mr %vreg188, 1, %noreg, 108, %noreg, %vreg186; mem:ST4[%nblock60] GR64:%vreg188 GR32:%vreg186
2752B		%vreg182<def> = MOV8rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%ch] GR8:%vreg182
2768B		%vreg181<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg181
2784B		%vreg179<def> = MOVSX64rm32 %vreg181, 1, %noreg, 108, %noreg; mem:LD4[%nblock62] GR64_NOSP:%vreg179 GR64:%vreg181
2800B		%vreg177<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg177
2816B		%vreg176<def> = MOV64rm %vreg177, 1, %noreg, 64, %noreg; mem:LD8[%block64] GR64:%vreg176,%vreg177
2832B		MOV8mr %vreg176, 1, %vreg179, 0, %noreg, %vreg182; mem:ST1[%arrayidx65] GR64:%vreg176 GR64_NOSP:%vreg179 GR8:%vreg182
2848B		%vreg171<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg171
2864B		%vreg169<def> = MOV32rm %vreg171, 1, %noreg, 108, %noreg; mem:LD4[%nblock66] GR32:%vreg169 GR64:%vreg171
2896B		%vreg169<def,tied1> = ADD32ri8 %vreg169<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg169
2912B		MOV32mr %vreg171, 1, %noreg, 108, %noreg, %vreg169; mem:ST4[%nblock66] GR64:%vreg171 GR32:%vreg169
2928B		%vreg165<def> = MOV8rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%ch] GR8:%vreg165
2944B		%vreg164<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg164
2960B		%vreg162<def> = MOVSX64rm32 %vreg164, 1, %noreg, 108, %noreg; mem:LD4[%nblock68] GR64_NOSP:%vreg162 GR64:%vreg164
2976B		%vreg160<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg160
2992B		%vreg159<def> = MOV64rm %vreg160, 1, %noreg, 64, %noreg; mem:LD8[%block70] GR64:%vreg159,%vreg160
3008B		MOV8mr %vreg159, 1, %vreg162, 0, %noreg, %vreg165; mem:ST1[%arrayidx71] GR64:%vreg159 GR64_NOSP:%vreg162 GR8:%vreg165
3024B		%vreg154<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg154
3040B		%vreg152<def> = MOV32rm %vreg154, 1, %noreg, 108, %noreg; mem:LD4[%nblock72] GR32:%vreg152 GR64:%vreg154
3072B		%vreg152<def,tied1> = ADD32ri8 %vreg152<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg152
3088B		MOV32mr %vreg154, 1, %noreg, 108, %noreg, %vreg152; mem:ST4[%nblock72] GR64:%vreg154 GR32:%vreg152
3104B		%vreg148<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg148
3120B		%vreg145<def> = MOV32rm %vreg148, 1, %noreg, 96, %noreg; mem:LD4[%state_in_len74] GR32:%vreg145 GR64:%vreg148
3152B		%vreg145<def,tied1> = SUB32ri8 %vreg145<tied0>, 4, %EFLAGS<imp-def,dead>; GR32:%vreg145
3184B		%vreg141<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg141
3200B		%vreg139<def> = MOVSX64rm32 %vreg141, 1, %noreg, 108, %noreg; mem:LD4[%nblock77] GR64_NOSP:%vreg139 GR64:%vreg141
3216B		%vreg137<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg137
3232B		%vreg136<def> = MOV64rm %vreg137, 1, %noreg, 64, %noreg; mem:LD8[%block79] GR64:%vreg136,%vreg137
3248B		MOV8mr %vreg136, 1, %vreg139, 0, %noreg, %vreg145:sub_8bit; mem:ST1[%arrayidx80] GR64:%vreg136 GR64_NOSP:%vreg139 GR32:%vreg145
3264B		%vreg131<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg131
3280B		%vreg129<def> = MOV32rm %vreg131, 1, %noreg, 108, %noreg; mem:LD4[%nblock81] GR32:%vreg129 GR64:%vreg131
3312B		%vreg129<def,tied1> = ADD32ri8 %vreg129<tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg129
3328B		MOV32mr %vreg131, 1, %noreg, 108, %noreg, %vreg129; mem:ST4[%nblock81] GR64:%vreg131 GR32:%vreg129
	    Successors according to CFG: BB#11

3344B	BB#11: derived from LLVM BB %sw.epilog
	    Predecessors according to CFG: BB#9 BB#8 BB#7 BB#10
3360B		%vreg228<def> = MOV64ri <ga:@add_pair_to_block>; GR64:%vreg228
3392B		%vreg229<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg229
3408B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3424B		%RDI<def> = COPY %vreg228; GR64:%vreg228
3440B		%RSI<def> = COPY %vreg229; GR64:%vreg229
3456B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use,kill>
3472B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3488B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3504B		STACKMAP 1, 0, ...
3520B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3536B		RETQ

# End machine code for function add_pair_to_block.


selectOrSplit GR64:%vreg1 [16r,224r:0)  0@16r w=4.983553e-03
hints: %RDI
missed hint %RDI
assigning %vreg1 to %RBX: BH [16r,224r:0)  0@16r BL [16r,224r:0)  0@16r

selectOrSplit GR64:%vreg9 [48r,112r:0)  0@48r w=2.176724e-03
hints: %RDI
assigning %vreg9 to %RDI: DIL [48r,112r:0)  0@48r

selectOrSplit GR64:%vreg10 [80r,128r:0)  0@80r w=4.508928e-03
hints: %RSI
assigning %vreg10 to %RSI: SIL [80r,128r:0)  0@80r

selectOrSplit GR64:%vreg228 [3360r,3424r:0)  0@3360r w=2.176724e-03
hints: %RDI
assigning %vreg228 to %RDI: DIL [3360r,3424r:0)  0@3360r

selectOrSplit GR64:%vreg229 [3392r,3440r:0)  0@3392r w=4.508928e-03
hints: %RSI
assigning %vreg229 to %RSI: SIL [3392r,3440r:0)  0@3392r

selectOrSplit GR32:%vreg23 [880r,1072r:0)[1072r,1072d:1)  0@880r 1@1072r w=5.109612e-03
assigning %vreg23 to %EAX: AH [880r,1072r:0)[1072r,1072d:1)  0@880r 1@1072r AL [880r,1072r:0)[1072r,1072d:1)  0@880r 1@1072r

selectOrSplit GR64:%vreg7 [240r,256r:0)  0@240r w=inf
assigning %vreg7 to %RAX: AH [240r,256r:0)  0@240r AL [240r,256r:0)  0@240r

selectOrSplit GR32:%vreg6 [256r,288r:0)  0@256r w=inf
assigning %vreg6 to %EAX: AH [256r,288r:0)  0@256r AL [256r,288r:0)  0@256r

selectOrSplit GR32:%vreg15 [336r,368r:0)  0@336r w=9.186922e-03
assigning %vreg15 to %EAX: AH [336r,368r:0)  0@336r AL [336r,368r:0)  0@336r

selectOrSplit GR64:%vreg14 [352r,368r:0)  0@352r w=inf
assigning %vreg14 to %RCX: CH [352r,368r:0)  0@352r CL [352r,368r:0)  0@352r

selectOrSplit GR64:%vreg254 [416r,432r:0)  0@416r w=inf
assigning %vreg254 to %RAX: AH [416r,432r:0)  0@416r AL [416r,432r:0)  0@416r

selectOrSplit GR32:%vreg235 [432r,464r:2)[464r,640r:0)[640r,672r:1)  0@464r 1@640r 2@432r w=9.228515e-03
assigning %vreg235 to %EAX: AH [432r,464r:2)[464r,640r:0)[640r,672r:1)  0@464r 1@640r 2@432r AL [432r,464r:2)[464r,640r:0)[640r,672r:1)  0@464r 1@640r 2@432r

selectOrSplit GR64:%vreg249 [480r,496r:0)  0@480r w=inf
assigning %vreg249 to %RCX: CH [480r,496r:0)  0@480r CL [480r,496r:0)  0@480r

selectOrSplit GR32:%vreg242 [496r,528r:2)[528r,576r:0)[576r,592r:1)  0@528r 1@576r 2@496r w=1.190776e-02
assigning %vreg242 to %ECX: CH [496r,528r:2)[528r,576r:0)[576r,592r:1)  0@528r 1@576r 2@496r CL [496r,528r:2)[528r,576r:0)[576r,592r:1)  0@528r 1@576r 2@496r

selectOrSplit GR32:%vreg244 [544r,576r:0)  0@544r w=inf
assigning %vreg244 to %EDX: DH [544r,576r:0)  0@544r DL [544r,576r:0)  0@544r

selectOrSplit GR64_NOSP:%vreg239 [592r,640r:0)  0@592r w=inf
assigning %vreg239 to %RCX: CH [592r,640r:0)  0@592r CL [592r,640r:0)  0@592r

selectOrSplit GR64:%vreg232 [656r,672r:0)  0@656r w=inf
assigning %vreg232 to %RCX: CH [656r,672r:0)  0@656r CL [656r,672r:0)  0@656r

selectOrSplit GR32:%vreg257 [704r,736r:0)[736r,752r:1)  0@704r 1@736r w=inf
assigning %vreg257 to %EAX: AH [704r,736r:0)[736r,752r:1)  0@704r 1@736r AL [704r,736r:0)[736r,752r:1)  0@704r 1@736r

selectOrSplit GR64:%vreg17 [800r,848r:0)  0@800r w=6.696429e-03
assigning %vreg17 to %RAX: AH [800r,848r:0)  0@800r AL [800r,848r:0)  0@800r

selectOrSplit GR64_NOSP:%vreg19 [816r,848r:0)  0@816r w=inf
assigning %vreg19 to %RCX: CH [816r,848r:0)  0@816r CL [816r,848r:0)  0@816r

selectOrSplit GR64:%vreg20 [864r,880r:0)  0@864r w=inf
assigning %vreg20 to %RAX: AH [864r,880r:0)  0@864r AL [864r,880r:0)  0@864r

selectOrSplit GR32:%vreg21 [896r,912r:0)[912r,912d:1)  0@896r 1@912r w=inf
hints: %EAX
assigning %vreg21 to %ECX: CH [896r,912r:0)[912r,912d:1)  0@896r 1@912r CL [896r,912r:0)[912r,912d:1)  0@896r 1@912r

selectOrSplit GR32:%vreg22 [976r,992r:0)[992r,992d:1)  0@976r 1@992r w=inf
hints: %EAX
assigning %vreg22 to %ECX: CH [976r,992r:0)[992r,992d:1)  0@976r 1@992r CL [976r,992r:0)[992r,992d:1)  0@976r 1@992r

selectOrSplit GR8:%vreg125 [1136r,1216r:0)  0@1136r w=2.083333e-03
assigning %vreg125 to %AL: AL [1136r,1216r:0)  0@1136r

selectOrSplit GR64:%vreg124 [1152r,1168r:0)  0@1152r w=inf
assigning %vreg124 to %RCX: CH [1152r,1168r:0)  0@1152r CL [1152r,1168r:0)  0@1152r

selectOrSplit GR64_NOSP:%vreg122 [1168r,1216r:0)  0@1168r w=2.232143e-03
assigning %vreg122 to %RCX: CH [1168r,1216r:0)  0@1168r CL [1168r,1216r:0)  0@1168r

selectOrSplit GR64:%vreg120 [1184r,1200r:0)  0@1184r w=inf
assigning %vreg120 to %RDX: DH [1184r,1200r:0)  0@1184r DL [1184r,1200r:0)  0@1184r

selectOrSplit GR64:%vreg119 [1200r,1216r:0)  0@1200r w=inf
assigning %vreg119 to %RDX: DH [1200r,1216r:0)  0@1200r DL [1200r,1216r:0)  0@1200r

selectOrSplit GR64:%vreg114 [1232r,1296r:0)  0@1232r w=3.232759e-03
assigning %vreg114 to %RAX: AH [1232r,1296r:0)  0@1232r AL [1232r,1296r:0)  0@1232r

selectOrSplit GR32:%vreg112 [1248r,1280r:0)[1280r,1296r:1)  0@1248r 1@1280r w=inf
assigning %vreg112 to %ECX: CH [1248r,1280r:0)[1280r,1296r:1)  0@1248r 1@1280r CL [1248r,1280r:0)[1280r,1296r:1)  0@1248r 1@1280r

selectOrSplit GR8:%vreg108 [1344r,1424r:0)  0@1344r w=1.041667e-03
assigning %vreg108 to %AL: AL [1344r,1424r:0)  0@1344r

selectOrSplit GR64:%vreg107 [1360r,1376r:0)  0@1360r w=inf
assigning %vreg107 to %RCX: CH [1360r,1376r:0)  0@1360r CL [1360r,1376r:0)  0@1360r

selectOrSplit GR64_NOSP:%vreg105 [1376r,1424r:0)  0@1376r w=1.116071e-03
assigning %vreg105 to %RCX: CH [1376r,1424r:0)  0@1376r CL [1376r,1424r:0)  0@1376r

selectOrSplit GR64:%vreg103 [1392r,1408r:0)  0@1392r w=inf
assigning %vreg103 to %RDX: DH [1392r,1408r:0)  0@1392r DL [1392r,1408r:0)  0@1392r

selectOrSplit GR64:%vreg102 [1408r,1424r:0)  0@1408r w=inf
assigning %vreg102 to %RDX: DH [1408r,1424r:0)  0@1408r DL [1408r,1424r:0)  0@1408r

selectOrSplit GR64:%vreg97 [1440r,1504r:0)  0@1440r w=1.616379e-03
assigning %vreg97 to %RAX: AH [1440r,1504r:0)  0@1440r AL [1440r,1504r:0)  0@1440r

selectOrSplit GR32:%vreg95 [1456r,1488r:0)[1488r,1504r:1)  0@1456r 1@1488r w=inf
assigning %vreg95 to %ECX: CH [1456r,1488r:0)[1488r,1504r:1)  0@1456r 1@1488r CL [1456r,1488r:0)[1488r,1504r:1)  0@1456r 1@1488r

selectOrSplit GR8:%vreg91 [1520r,1600r:0)  0@1520r w=1.041667e-03
assigning %vreg91 to %AL: AL [1520r,1600r:0)  0@1520r

selectOrSplit GR64:%vreg90 [1536r,1552r:0)  0@1536r w=inf
assigning %vreg90 to %RCX: CH [1536r,1552r:0)  0@1536r CL [1536r,1552r:0)  0@1536r

selectOrSplit GR64_NOSP:%vreg88 [1552r,1600r:0)  0@1552r w=1.116071e-03
assigning %vreg88 to %RCX: CH [1552r,1600r:0)  0@1552r CL [1552r,1600r:0)  0@1552r

selectOrSplit GR64:%vreg86 [1568r,1584r:0)  0@1568r w=inf
assigning %vreg86 to %RDX: DH [1568r,1584r:0)  0@1568r DL [1568r,1584r:0)  0@1568r

selectOrSplit GR64:%vreg85 [1584r,1600r:0)  0@1584r w=inf
assigning %vreg85 to %RDX: DH [1584r,1600r:0)  0@1584r DL [1584r,1600r:0)  0@1584r

selectOrSplit GR64:%vreg80 [1616r,1680r:0)  0@1616r w=1.616379e-03
assigning %vreg80 to %RAX: AH [1616r,1680r:0)  0@1616r AL [1616r,1680r:0)  0@1616r

selectOrSplit GR32:%vreg78 [1632r,1664r:0)[1664r,1680r:1)  0@1632r 1@1664r w=inf
assigning %vreg78 to %ECX: CH [1632r,1664r:0)[1664r,1680r:1)  0@1632r 1@1664r CL [1632r,1664r:0)[1664r,1680r:1)  0@1632r 1@1664r

selectOrSplit GR8:%vreg74 [1728r,1808r:0)  0@1728r w=5.208334e-04
assigning %vreg74 to %AL: AL [1728r,1808r:0)  0@1728r

selectOrSplit GR64:%vreg73 [1744r,1760r:0)  0@1744r w=inf
assigning %vreg73 to %RCX: CH [1744r,1760r:0)  0@1744r CL [1744r,1760r:0)  0@1744r

selectOrSplit GR64_NOSP:%vreg71 [1760r,1808r:0)  0@1760r w=5.580357e-04
assigning %vreg71 to %RCX: CH [1760r,1808r:0)  0@1760r CL [1760r,1808r:0)  0@1760r

selectOrSplit GR64:%vreg69 [1776r,1792r:0)  0@1776r w=inf
assigning %vreg69 to %RDX: DH [1776r,1792r:0)  0@1776r DL [1776r,1792r:0)  0@1776r

selectOrSplit GR64:%vreg68 [1792r,1808r:0)  0@1792r w=inf
assigning %vreg68 to %RDX: DH [1792r,1808r:0)  0@1792r DL [1792r,1808r:0)  0@1792r

selectOrSplit GR64:%vreg63 [1824r,1888r:0)  0@1824r w=8.081897e-04
assigning %vreg63 to %RAX: AH [1824r,1888r:0)  0@1824r AL [1824r,1888r:0)  0@1824r

selectOrSplit GR32:%vreg61 [1840r,1872r:0)[1872r,1888r:1)  0@1840r 1@1872r w=inf
assigning %vreg61 to %ECX: CH [1840r,1872r:0)[1872r,1888r:1)  0@1840r 1@1872r CL [1840r,1872r:0)[1872r,1888r:1)  0@1840r 1@1872r

selectOrSplit GR8:%vreg57 [1904r,1984r:0)  0@1904r w=5.208334e-04
assigning %vreg57 to %AL: AL [1904r,1984r:0)  0@1904r

selectOrSplit GR64:%vreg56 [1920r,1936r:0)  0@1920r w=inf
assigning %vreg56 to %RCX: CH [1920r,1936r:0)  0@1920r CL [1920r,1936r:0)  0@1920r

selectOrSplit GR64_NOSP:%vreg54 [1936r,1984r:0)  0@1936r w=5.580357e-04
assigning %vreg54 to %RCX: CH [1936r,1984r:0)  0@1936r CL [1936r,1984r:0)  0@1936r

selectOrSplit GR64:%vreg52 [1952r,1968r:0)  0@1952r w=inf
assigning %vreg52 to %RDX: DH [1952r,1968r:0)  0@1952r DL [1952r,1968r:0)  0@1952r

selectOrSplit GR64:%vreg51 [1968r,1984r:0)  0@1968r w=inf
assigning %vreg51 to %RDX: DH [1968r,1984r:0)  0@1968r DL [1968r,1984r:0)  0@1968r

selectOrSplit GR64:%vreg46 [2000r,2064r:0)  0@2000r w=8.081897e-04
assigning %vreg46 to %RAX: AH [2000r,2064r:0)  0@2000r AL [2000r,2064r:0)  0@2000r

selectOrSplit GR32:%vreg44 [2016r,2048r:0)[2048r,2064r:1)  0@2016r 1@2048r w=inf
assigning %vreg44 to %ECX: CH [2016r,2048r:0)[2048r,2064r:1)  0@2016r 1@2048r CL [2016r,2048r:0)[2048r,2064r:1)  0@2016r 1@2048r

selectOrSplit GR8:%vreg40 [2080r,2160r:0)  0@2080r w=5.208334e-04
assigning %vreg40 to %AL: AL [2080r,2160r:0)  0@2080r

selectOrSplit GR64:%vreg39 [2096r,2112r:0)  0@2096r w=inf
assigning %vreg39 to %RCX: CH [2096r,2112r:0)  0@2096r CL [2096r,2112r:0)  0@2096r

selectOrSplit GR64_NOSP:%vreg37 [2112r,2160r:0)  0@2112r w=5.580357e-04
assigning %vreg37 to %RCX: CH [2112r,2160r:0)  0@2112r CL [2112r,2160r:0)  0@2112r

selectOrSplit GR64:%vreg35 [2128r,2144r:0)  0@2128r w=inf
assigning %vreg35 to %RDX: DH [2128r,2144r:0)  0@2128r DL [2128r,2144r:0)  0@2128r

selectOrSplit GR64:%vreg34 [2144r,2160r:0)  0@2144r w=inf
assigning %vreg34 to %RDX: DH [2144r,2160r:0)  0@2144r DL [2144r,2160r:0)  0@2144r

selectOrSplit GR64:%vreg29 [2176r,2240r:0)  0@2176r w=8.081897e-04
assigning %vreg29 to %RAX: AH [2176r,2240r:0)  0@2176r AL [2176r,2240r:0)  0@2176r

selectOrSplit GR32:%vreg27 [2192r,2224r:0)[2224r,2240r:1)  0@2192r 1@2224r w=inf
assigning %vreg27 to %ECX: CH [2192r,2224r:0)[2224r,2240r:1)  0@2192r 1@2224r CL [2192r,2224r:0)[2224r,2240r:1)  0@2192r 1@2224r

selectOrSplit GR64:%vreg226 [2288r,2304r:0)  0@2288r w=inf
assigning %vreg226 to %RAX: AH [2288r,2304r:0)  0@2288r AL [2288r,2304r:0)  0@2288r

selectOrSplit GR32:%vreg223 [2304r,2336r:0)[2336r,2352r:1)  0@2304r 1@2336r w=inf
assigning %vreg223 to %EAX: AH [2304r,2336r:0)[2336r,2352r:1)  0@2304r 1@2336r AL [2304r,2336r:0)[2336r,2352r:1)  0@2304r 1@2336r

selectOrSplit GR64_NOSP:%vreg221 [2352r,2384r:0)  0@2352r w=5.787037e-04
assigning %vreg221 to %RAX: AH [2352r,2384r:0)  0@2352r AL [2352r,2384r:0)  0@2352r

selectOrSplit GR64:%vreg219 [2368r,2384r:0)  0@2368r w=inf
assigning %vreg219 to %RCX: CH [2368r,2384r:0)  0@2368r CL [2368r,2384r:0)  0@2368r

selectOrSplit GR8:%vreg216 [2400r,2480r:0)  0@2400r w=5.208334e-04
assigning %vreg216 to %AL: AL [2400r,2480r:0)  0@2400r

selectOrSplit GR64:%vreg215 [2416r,2432r:0)  0@2416r w=inf
assigning %vreg215 to %RCX: CH [2416r,2432r:0)  0@2416r CL [2416r,2432r:0)  0@2416r

selectOrSplit GR64_NOSP:%vreg213 [2432r,2480r:0)  0@2432r w=5.580357e-04
assigning %vreg213 to %RCX: CH [2432r,2480r:0)  0@2432r CL [2432r,2480r:0)  0@2432r

selectOrSplit GR64:%vreg211 [2448r,2464r:0)  0@2448r w=inf
assigning %vreg211 to %RDX: DH [2448r,2464r:0)  0@2448r DL [2448r,2464r:0)  0@2448r

selectOrSplit GR64:%vreg210 [2464r,2480r:0)  0@2464r w=inf
assigning %vreg210 to %RDX: DH [2464r,2480r:0)  0@2464r DL [2464r,2480r:0)  0@2464r

selectOrSplit GR64:%vreg205 [2496r,2560r:0)  0@2496r w=8.081897e-04
assigning %vreg205 to %RAX: AH [2496r,2560r:0)  0@2496r AL [2496r,2560r:0)  0@2496r

selectOrSplit GR32:%vreg203 [2512r,2544r:0)[2544r,2560r:1)  0@2512r 1@2544r w=inf
assigning %vreg203 to %ECX: CH [2512r,2544r:0)[2544r,2560r:1)  0@2512r 1@2544r CL [2512r,2544r:0)[2544r,2560r:1)  0@2512r 1@2544r

selectOrSplit GR8:%vreg199 [2576r,2656r:0)  0@2576r w=5.208334e-04
assigning %vreg199 to %AL: AL [2576r,2656r:0)  0@2576r

selectOrSplit GR64:%vreg198 [2592r,2608r:0)  0@2592r w=inf
assigning %vreg198 to %RCX: CH [2592r,2608r:0)  0@2592r CL [2592r,2608r:0)  0@2592r

selectOrSplit GR64_NOSP:%vreg196 [2608r,2656r:0)  0@2608r w=5.580357e-04
assigning %vreg196 to %RCX: CH [2608r,2656r:0)  0@2608r CL [2608r,2656r:0)  0@2608r

selectOrSplit GR64:%vreg194 [2624r,2640r:0)  0@2624r w=inf
assigning %vreg194 to %RDX: DH [2624r,2640r:0)  0@2624r DL [2624r,2640r:0)  0@2624r

selectOrSplit GR64:%vreg193 [2640r,2656r:0)  0@2640r w=inf
assigning %vreg193 to %RDX: DH [2640r,2656r:0)  0@2640r DL [2640r,2656r:0)  0@2640r

selectOrSplit GR64:%vreg188 [2672r,2736r:0)  0@2672r w=8.081897e-04
assigning %vreg188 to %RAX: AH [2672r,2736r:0)  0@2672r AL [2672r,2736r:0)  0@2672r

selectOrSplit GR32:%vreg186 [2688r,2720r:0)[2720r,2736r:1)  0@2688r 1@2720r w=inf
assigning %vreg186 to %ECX: CH [2688r,2720r:0)[2720r,2736r:1)  0@2688r 1@2720r CL [2688r,2720r:0)[2720r,2736r:1)  0@2688r 1@2720r

selectOrSplit GR8:%vreg182 [2752r,2832r:0)  0@2752r w=5.208334e-04
assigning %vreg182 to %AL: AL [2752r,2832r:0)  0@2752r

selectOrSplit GR64:%vreg181 [2768r,2784r:0)  0@2768r w=inf
assigning %vreg181 to %RCX: CH [2768r,2784r:0)  0@2768r CL [2768r,2784r:0)  0@2768r

selectOrSplit GR64_NOSP:%vreg179 [2784r,2832r:0)  0@2784r w=5.580357e-04
assigning %vreg179 to %RCX: CH [2784r,2832r:0)  0@2784r CL [2784r,2832r:0)  0@2784r

selectOrSplit GR64:%vreg177 [2800r,2816r:0)  0@2800r w=inf
assigning %vreg177 to %RDX: DH [2800r,2816r:0)  0@2800r DL [2800r,2816r:0)  0@2800r

selectOrSplit GR64:%vreg176 [2816r,2832r:0)  0@2816r w=inf
assigning %vreg176 to %RDX: DH [2816r,2832r:0)  0@2816r DL [2816r,2832r:0)  0@2816r

selectOrSplit GR64:%vreg171 [2848r,2912r:0)  0@2848r w=8.081897e-04
assigning %vreg171 to %RAX: AH [2848r,2912r:0)  0@2848r AL [2848r,2912r:0)  0@2848r

selectOrSplit GR32:%vreg169 [2864r,2896r:0)[2896r,2912r:1)  0@2864r 1@2896r w=inf
assigning %vreg169 to %ECX: CH [2864r,2896r:0)[2896r,2912r:1)  0@2864r 1@2896r CL [2864r,2896r:0)[2896r,2912r:1)  0@2864r 1@2896r

selectOrSplit GR8:%vreg165 [2928r,3008r:0)  0@2928r w=5.208334e-04
assigning %vreg165 to %AL: AL [2928r,3008r:0)  0@2928r

selectOrSplit GR64:%vreg164 [2944r,2960r:0)  0@2944r w=inf
assigning %vreg164 to %RCX: CH [2944r,2960r:0)  0@2944r CL [2944r,2960r:0)  0@2944r

selectOrSplit GR64_NOSP:%vreg162 [2960r,3008r:0)  0@2960r w=5.580357e-04
assigning %vreg162 to %RCX: CH [2960r,3008r:0)  0@2960r CL [2960r,3008r:0)  0@2960r

selectOrSplit GR64:%vreg160 [2976r,2992r:0)  0@2976r w=inf
assigning %vreg160 to %RDX: DH [2976r,2992r:0)  0@2976r DL [2976r,2992r:0)  0@2976r

selectOrSplit GR64:%vreg159 [2992r,3008r:0)  0@2992r w=inf
assigning %vreg159 to %RDX: DH [2992r,3008r:0)  0@2992r DL [2992r,3008r:0)  0@2992r

selectOrSplit GR64:%vreg154 [3024r,3088r:0)  0@3024r w=8.081897e-04
assigning %vreg154 to %RAX: AH [3024r,3088r:0)  0@3024r AL [3024r,3088r:0)  0@3024r

selectOrSplit GR32:%vreg152 [3040r,3072r:0)[3072r,3088r:1)  0@3040r 1@3072r w=inf
assigning %vreg152 to %ECX: CH [3040r,3072r:0)[3072r,3088r:1)  0@3040r 1@3072r CL [3040r,3072r:0)[3072r,3088r:1)  0@3040r 1@3072r

selectOrSplit GR64:%vreg148 [3104r,3120r:0)  0@3104r w=inf
assigning %vreg148 to %RAX: AH [3104r,3120r:0)  0@3104r AL [3104r,3120r:0)  0@3104r

selectOrSplit GR32:%vreg145 [3120r,3152r:0)[3152r,3248r:1)  0@3120r 1@3152r w=9.469697e-04
assigning %vreg145 to %EAX: AH [3120r,3152r:0)[3152r,3248r:1)  0@3120r 1@3152r AL [3120r,3152r:0)[3152r,3248r:1)  0@3120r 1@3152r

selectOrSplit GR64:%vreg141 [3184r,3200r:0)  0@3184r w=inf
assigning %vreg141 to %RCX: CH [3184r,3200r:0)  0@3184r CL [3184r,3200r:0)  0@3184r

selectOrSplit GR64_NOSP:%vreg139 [3200r,3248r:0)  0@3200r w=5.580357e-04
assigning %vreg139 to %RCX: CH [3200r,3248r:0)  0@3200r CL [3200r,3248r:0)  0@3200r

selectOrSplit GR64:%vreg137 [3216r,3232r:0)  0@3216r w=inf
assigning %vreg137 to %RDX: DH [3216r,3232r:0)  0@3216r DL [3216r,3232r:0)  0@3216r

selectOrSplit GR64:%vreg136 [3232r,3248r:0)  0@3232r w=inf
assigning %vreg136 to %RDX: DH [3232r,3248r:0)  0@3232r DL [3232r,3248r:0)  0@3232r

selectOrSplit GR64:%vreg131 [3264r,3328r:0)  0@3264r w=8.081897e-04
assigning %vreg131 to %RAX: AH [3264r,3328r:0)  0@3264r AL [3264r,3328r:0)  0@3264r

selectOrSplit GR32:%vreg129 [3280r,3312r:0)[3312r,3328r:1)  0@3280r 1@3312r w=inf
assigning %vreg129 to %ECX: CH [3280r,3312r:0)[3312r,3328r:1)  0@3280r 1@3312r CL [3280r,3312r:0)[3312r,3328r:1)  0@3280r 1@3312r

********** STACK TRANSFORMATION METADATA **********
********** Function: add_pair_to_block
********** REGISTER MAP **********
[%vreg1 -> %RBX] GR64
[%vreg6 -> %EAX] GR32
[%vreg7 -> %RAX] GR64
[%vreg9 -> %RDI] GR64
[%vreg10 -> %RSI] GR64
[%vreg14 -> %RCX] GR64
[%vreg15 -> %EAX] GR32
[%vreg17 -> %RAX] GR64
[%vreg19 -> %RCX] GR64_NOSP
[%vreg20 -> %RAX] GR64
[%vreg21 -> %ECX] GR32
[%vreg22 -> %ECX] GR32
[%vreg23 -> %EAX] GR32
[%vreg27 -> %ECX] GR32
[%vreg29 -> %RAX] GR64
[%vreg34 -> %RDX] GR64
[%vreg35 -> %RDX] GR64
[%vreg37 -> %RCX] GR64_NOSP
[%vreg39 -> %RCX] GR64
[%vreg40 -> %AL] GR8
[%vreg44 -> %ECX] GR32
[%vreg46 -> %RAX] GR64
[%vreg51 -> %RDX] GR64
[%vreg52 -> %RDX] GR64
[%vreg54 -> %RCX] GR64_NOSP
[%vreg56 -> %RCX] GR64
[%vreg57 -> %AL] GR8
[%vreg61 -> %ECX] GR32
[%vreg63 -> %RAX] GR64
[%vreg68 -> %RDX] GR64
[%vreg69 -> %RDX] GR64
[%vreg71 -> %RCX] GR64_NOSP
[%vreg73 -> %RCX] GR64
[%vreg74 -> %AL] GR8
[%vreg78 -> %ECX] GR32
[%vreg80 -> %RAX] GR64
[%vreg85 -> %RDX] GR64
[%vreg86 -> %RDX] GR64
[%vreg88 -> %RCX] GR64_NOSP
[%vreg90 -> %RCX] GR64
[%vreg91 -> %AL] GR8
[%vreg95 -> %ECX] GR32
[%vreg97 -> %RAX] GR64
[%vreg102 -> %RDX] GR64
[%vreg103 -> %RDX] GR64
[%vreg105 -> %RCX] GR64_NOSP
[%vreg107 -> %RCX] GR64
[%vreg108 -> %AL] GR8
[%vreg112 -> %ECX] GR32
[%vreg114 -> %RAX] GR64
[%vreg119 -> %RDX] GR64
[%vreg120 -> %RDX] GR64
[%vreg122 -> %RCX] GR64_NOSP
[%vreg124 -> %RCX] GR64
[%vreg125 -> %AL] GR8
[%vreg129 -> %ECX] GR32
[%vreg131 -> %RAX] GR64
[%vreg136 -> %RDX] GR64
[%vreg137 -> %RDX] GR64
[%vreg139 -> %RCX] GR64_NOSP
[%vreg141 -> %RCX] GR64
[%vreg145 -> %EAX] GR32
[%vreg148 -> %RAX] GR64
[%vreg152 -> %ECX] GR32
[%vreg154 -> %RAX] GR64
[%vreg159 -> %RDX] GR64
[%vreg160 -> %RDX] GR64
[%vreg162 -> %RCX] GR64_NOSP
[%vreg164 -> %RCX] GR64
[%vreg165 -> %AL] GR8
[%vreg169 -> %ECX] GR32
[%vreg171 -> %RAX] GR64
[%vreg176 -> %RDX] GR64
[%vreg177 -> %RDX] GR64
[%vreg179 -> %RCX] GR64_NOSP
[%vreg181 -> %RCX] GR64
[%vreg182 -> %AL] GR8
[%vreg186 -> %ECX] GR32
[%vreg188 -> %RAX] GR64
[%vreg193 -> %RDX] GR64
[%vreg194 -> %RDX] GR64
[%vreg196 -> %RCX] GR64_NOSP
[%vreg198 -> %RCX] GR64
[%vreg199 -> %AL] GR8
[%vreg203 -> %ECX] GR32
[%vreg205 -> %RAX] GR64
[%vreg210 -> %RDX] GR64
[%vreg211 -> %RDX] GR64
[%vreg213 -> %RCX] GR64_NOSP
[%vreg215 -> %RCX] GR64
[%vreg216 -> %AL] GR8
[%vreg219 -> %RCX] GR64
[%vreg221 -> %RAX] GR64_NOSP
[%vreg223 -> %EAX] GR32
[%vreg226 -> %RAX] GR64
[%vreg228 -> %RDI] GR64
[%vreg229 -> %RSI] GR64
[%vreg232 -> %RCX] GR64
[%vreg235 -> %EAX] GR32
[%vreg239 -> %RCX] GR64_NOSP
[%vreg242 -> %ECX] GR32
[%vreg244 -> %EDX] GR32
[%vreg249 -> %RCX] GR64
[%vreg254 -> %RAX] GR64
[%vreg257 -> %EAX] GR32


Stackmap 0:
  STACKMAP 0, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack1](align=4) LD8[FixedStack0] GR64:%vreg1

i8* %ch: in stack slot 2 (size: 1)
i32* %i: in stack slot 1 (size: 4)
%struct.EState* %s: in register %RBX (vreg 1)
%struct.EState** %s.addr: in stack slot 0 (size: 8)

Duplicate operand locations:


Stackmap 1:
  STACKMAP 1, 0, ...


Duplicate operand locations:


*** Finding architecture-specific live values ***

  STACKMAP 0, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack1](align=4) LD8[FixedStack0] GR64:%vreg1
  -> Call instruction SlotIndex 144B, searching vregs 0 -> 259 and stack slots -1 -> 3

  STACKMAP 1, 0, ...
  -> Call instruction SlotIndex 3456B, searching vregs 0 -> 259 and stack slots -1 -> 3

********** REWRITE VIRTUAL REGISTERS **********
********** Function: add_pair_to_block
********** REGISTER MAP **********
[%vreg1 -> %RBX] GR64
[%vreg6 -> %EAX] GR32
[%vreg7 -> %RAX] GR64
[%vreg9 -> %RDI] GR64
[%vreg10 -> %RSI] GR64
[%vreg14 -> %RCX] GR64
[%vreg15 -> %EAX] GR32
[%vreg17 -> %RAX] GR64
[%vreg19 -> %RCX] GR64_NOSP
[%vreg20 -> %RAX] GR64
[%vreg21 -> %ECX] GR32
[%vreg22 -> %ECX] GR32
[%vreg23 -> %EAX] GR32
[%vreg27 -> %ECX] GR32
[%vreg29 -> %RAX] GR64
[%vreg34 -> %RDX] GR64
[%vreg35 -> %RDX] GR64
[%vreg37 -> %RCX] GR64_NOSP
[%vreg39 -> %RCX] GR64
[%vreg40 -> %AL] GR8
[%vreg44 -> %ECX] GR32
[%vreg46 -> %RAX] GR64
[%vreg51 -> %RDX] GR64
[%vreg52 -> %RDX] GR64
[%vreg54 -> %RCX] GR64_NOSP
[%vreg56 -> %RCX] GR64
[%vreg57 -> %AL] GR8
[%vreg61 -> %ECX] GR32
[%vreg63 -> %RAX] GR64
[%vreg68 -> %RDX] GR64
[%vreg69 -> %RDX] GR64
[%vreg71 -> %RCX] GR64_NOSP
[%vreg73 -> %RCX] GR64
[%vreg74 -> %AL] GR8
[%vreg78 -> %ECX] GR32
[%vreg80 -> %RAX] GR64
[%vreg85 -> %RDX] GR64
[%vreg86 -> %RDX] GR64
[%vreg88 -> %RCX] GR64_NOSP
[%vreg90 -> %RCX] GR64
[%vreg91 -> %AL] GR8
[%vreg95 -> %ECX] GR32
[%vreg97 -> %RAX] GR64
[%vreg102 -> %RDX] GR64
[%vreg103 -> %RDX] GR64
[%vreg105 -> %RCX] GR64_NOSP
[%vreg107 -> %RCX] GR64
[%vreg108 -> %AL] GR8
[%vreg112 -> %ECX] GR32
[%vreg114 -> %RAX] GR64
[%vreg119 -> %RDX] GR64
[%vreg120 -> %RDX] GR64
[%vreg122 -> %RCX] GR64_NOSP
[%vreg124 -> %RCX] GR64
[%vreg125 -> %AL] GR8
[%vreg129 -> %ECX] GR32
[%vreg131 -> %RAX] GR64
[%vreg136 -> %RDX] GR64
[%vreg137 -> %RDX] GR64
[%vreg139 -> %RCX] GR64_NOSP
[%vreg141 -> %RCX] GR64
[%vreg145 -> %EAX] GR32
[%vreg148 -> %RAX] GR64
[%vreg152 -> %ECX] GR32
[%vreg154 -> %RAX] GR64
[%vreg159 -> %RDX] GR64
[%vreg160 -> %RDX] GR64
[%vreg162 -> %RCX] GR64_NOSP
[%vreg164 -> %RCX] GR64
[%vreg165 -> %AL] GR8
[%vreg169 -> %ECX] GR32
[%vreg171 -> %RAX] GR64
[%vreg176 -> %RDX] GR64
[%vreg177 -> %RDX] GR64
[%vreg179 -> %RCX] GR64_NOSP
[%vreg181 -> %RCX] GR64
[%vreg182 -> %AL] GR8
[%vreg186 -> %ECX] GR32
[%vreg188 -> %RAX] GR64
[%vreg193 -> %RDX] GR64
[%vreg194 -> %RDX] GR64
[%vreg196 -> %RCX] GR64_NOSP
[%vreg198 -> %RCX] GR64
[%vreg199 -> %AL] GR8
[%vreg203 -> %ECX] GR32
[%vreg205 -> %RAX] GR64
[%vreg210 -> %RDX] GR64
[%vreg211 -> %RDX] GR64
[%vreg213 -> %RCX] GR64_NOSP
[%vreg215 -> %RCX] GR64
[%vreg216 -> %AL] GR8
[%vreg219 -> %RCX] GR64
[%vreg221 -> %RAX] GR64_NOSP
[%vreg223 -> %EAX] GR32
[%vreg226 -> %RAX] GR64
[%vreg228 -> %RDI] GR64
[%vreg229 -> %RSI] GR64
[%vreg232 -> %RCX] GR64
[%vreg235 -> %EAX] GR32
[%vreg239 -> %RCX] GR64_NOSP
[%vreg242 -> %ECX] GR32
[%vreg244 -> %EDX] GR32
[%vreg249 -> %RCX] GR64
[%vreg254 -> %RAX] GR64
[%vreg257 -> %EAX] GR32

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %RDI
16B		%vreg1<def> = COPY %RDI; GR64:%vreg1
48B		%vreg9<def> = MOV64ri <ga:@add_pair_to_block>; GR64:%vreg9
80B		%vreg10<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg10
96B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
112B		%RDI<def> = COPY %vreg9<kill>; GR64:%vreg9
128B		%RSI<def> = COPY %vreg10<kill>; GR64:%vreg10
144B		CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
160B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
176B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
192B		STACKMAP 0, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, %vreg1, 0, <fi#0>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack1](align=4) LD8[FixedStack0] GR64:%vreg1
208B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
224B		MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1<kill>; mem:ST8[%s.addr] GR64:%vreg1
240B		%vreg7<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg7
256B		%vreg6<def> = MOV32rm %vreg7<kill>, 1, %noreg, 92, %noreg; mem:LD4[%state_in_ch] GR32:%vreg6 GR64:%vreg7
288B		MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %vreg6:sub_8bit<kill>; mem:ST1[%ch] GR32:%vreg6
304B		MOV32mi <fi#1>, 1, %noreg, 0, %noreg, 0; mem:ST4[%i]
	    Successors according to CFG: BB#1
> %RBX<def> = COPY %RDI
> %RDI<def> = MOV64ri <ga:@add_pair_to_block>
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_enter>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 0, 0, 0, <fi#2>, 0, 0, <fi#1>, 0, %RBX, 0, <fi#0>, 0, ...; mem:LD8[FixedStack2](align=1) LD8[FixedStack1](align=4) LD8[FixedStack0]
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> MOV64mr <fi#0>, 1, %noreg, 0, %noreg, %RBX<kill>; mem:ST8[%s.addr]
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 92, %noreg; mem:LD4[%state_in_ch]
> MOV8mr <fi#2>, 1, %noreg, 0, %noreg, %AL, %EAX<imp-use,kill>; mem:ST1[%ch]
> MOV32mi <fi#1>, 1, %noreg, 0, %noreg, 0; mem:ST4[%i]
320B	BB#1: derived from LLVM BB %for.cond
	    Predecessors according to CFG: BB#0 BB#3
336B		%vreg15<def> = MOV32rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD4[%i] GR32:%vreg15
352B		%vreg14<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg14
368B		CMP32rm %vreg15<kill>, %vreg14<kill>, 1, %noreg, 96, %noreg, %EFLAGS<imp-def>; mem:LD4[%state_in_len] GR32:%vreg15 GR64:%vreg14
384B		JGE_1 <BB#4>, %EFLAGS<imp-use,kill>
	    Successors according to CFG: BB#4 BB#2
> %EAX<def> = MOV32rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD4[%i]
> %RCX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> CMP32rm %EAX<kill>, %RCX<kill>, 1, %noreg, 96, %noreg, %EFLAGS<imp-def>; mem:LD4[%state_in_len]
> JGE_1 <BB#4>, %EFLAGS<imp-use,kill>
400B	BB#2: derived from LLVM BB %for.body
	    Predecessors according to CFG: BB#1
416B		%vreg254<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg254
432B		%vreg235<def> = MOV32rm %vreg254<kill>, 1, %noreg, 648, %noreg; mem:LD4[%blockCRC] GR32:%vreg235 GR64:%vreg254
464B		%vreg235<def,tied1> = SHL32ri %vreg235<kill,tied0>, 8, %EFLAGS<imp-def,dead>; GR32:%vreg235
480B		%vreg249<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg249
496B		%vreg242<def> = MOV32rm %vreg249<kill>, 1, %noreg, 648, %noreg; mem:LD4[%blockCRC2] GR32:%vreg242 GR64:%vreg249
528B		%vreg242<def,tied1> = SHR32ri %vreg242<kill,tied0>, 24, %EFLAGS<imp-def,dead>; GR32:%vreg242
544B		%vreg244<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%ch] GR32:%vreg244
576B		%vreg242<def,tied1> = XOR32rr %vreg242<kill,tied0>, %vreg244<kill>, %EFLAGS<imp-def,dead>; GR32:%vreg242,%vreg244
592B		%vreg239:sub_32bit<def,read-undef> = MOV32rr %vreg242<kill>; GR64_NOSP:%vreg239 GR32:%vreg242
640B		%vreg235<def,tied1> = XOR32rm %vreg235<kill,tied0>, %noreg, 4, %vreg239<kill>, <ga:@BZ2_crc32Table>, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%arrayidx] GR32:%vreg235 GR64_NOSP:%vreg239
656B		%vreg232<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg232
672B		MOV32mr %vreg232<kill>, 1, %noreg, 648, %noreg, %vreg235<kill>; mem:ST4[%blockCRC5] GR64:%vreg232 GR32:%vreg235
	    Successors according to CFG: BB#3
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 648, %noreg; mem:LD4[%blockCRC]
> %EAX<def,tied1> = SHL32ri %EAX<kill,tied0>, 8, %EFLAGS<imp-def,dead>
> %RCX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RCX<kill>, 1, %noreg, 648, %noreg; mem:LD4[%blockCRC2]
> %ECX<def,tied1> = SHR32ri %ECX<kill,tied0>, 24, %EFLAGS<imp-def,dead>
> %EDX<def> = MOVZX32rm8 <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%ch]
> %ECX<def,tied1> = XOR32rr %ECX<kill,tied0>, %EDX<kill>, %EFLAGS<imp-def,dead>
> %ECX<def> = MOV32rr %ECX<kill>, %RCX<imp-def>
> %EAX<def,tied1> = XOR32rm %EAX<kill,tied0>, %noreg, 4, %RCX<kill>, <ga:@BZ2_crc32Table>, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%arrayidx]
> %RCX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV32mr %RCX<kill>, 1, %noreg, 648, %noreg, %EAX<kill>; mem:ST4[%blockCRC5]
688B	BB#3: derived from LLVM BB %for.inc
	    Predecessors according to CFG: BB#2
704B		%vreg257<def> = MOV32rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD4[%i] GR32:%vreg257
736B		%vreg257<def,tied1> = ADD32ri8 %vreg257<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg257
752B		MOV32mr <fi#1>, 1, %noreg, 0, %noreg, %vreg257<kill>; mem:ST4[%i] GR32:%vreg257
768B		JMP_1 <BB#1>
	    Successors according to CFG: BB#1
> %EAX<def> = MOV32rm <fi#1>, 1, %noreg, 0, %noreg; mem:LD4[%i]
> %EAX<def,tied1> = ADD32ri8 %EAX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV32mr <fi#1>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[%i]
> JMP_1 <BB#1>
784B	BB#4: derived from LLVM BB %for.end
	    Predecessors according to CFG: BB#1
800B		%vreg17<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg17
816B		%vreg19:sub_32bit<def,read-undef> = MOV32rm %vreg17, 1, %noreg, 92, %noreg; mem:LD4[%state_in_ch6] GR64_NOSP:%vreg19 GR64:%vreg17
848B		MOV8mi %vreg17<kill>, 1, %vreg19<kill>, 128, %noreg, 1; mem:ST1[%arrayidx8] GR64:%vreg17 GR64_NOSP:%vreg19
864B		%vreg20<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg20
880B		%vreg23<def> = MOV32rm %vreg20<kill>, 1, %noreg, 96, %noreg; mem:LD4[%state_in_len9] GR32:%vreg23 GR64:%vreg20
896B		%vreg21<def> = COPY %vreg23; GR32:%vreg21,%vreg23
912B		%vreg21<def,dead,tied1> = SUB32ri8 %vreg21<kill,tied0>, 1, %EFLAGS<imp-def>; GR32:%vreg21
928B		JE_1 <BB#7>, %EFLAGS<imp-use,kill>
944B		JMP_1 <BB#5>
	    Successors according to CFG: BB#7 BB#5
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 92, %noreg, %RCX<imp-def>; mem:LD4[%state_in_ch6]
> MOV8mi %RAX<kill>, 1, %RCX<kill>, 128, %noreg, 1; mem:ST1[%arrayidx8]
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 96, %noreg; mem:LD4[%state_in_len9]
> %ECX<def> = COPY %EAX
> %ECX<def,dead,tied1> = SUB32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def>
> JE_1 <BB#7>, %EFLAGS<imp-use,kill>
> JMP_1 <BB#5>
960B	BB#5: derived from LLVM BB %for.end
	    Live Ins: %EAX
	    Predecessors according to CFG: BB#4
976B		%vreg22<def> = COPY %vreg23; GR32:%vreg22,%vreg23
992B		%vreg22<def,dead,tied1> = SUB32ri8 %vreg22<kill,tied0>, 2, %EFLAGS<imp-def>; GR32:%vreg22
1008B		JE_1 <BB#8>, %EFLAGS<imp-use,kill>
1024B		JMP_1 <BB#6>
	    Successors according to CFG: BB#8 BB#6
> %ECX<def> = COPY %EAX
> %ECX<def,dead,tied1> = SUB32ri8 %ECX<kill,tied0>, 2, %EFLAGS<imp-def>
> JE_1 <BB#8>, %EFLAGS<imp-use,kill>
> JMP_1 <BB#6>
1040B	BB#6: derived from LLVM BB %for.end
	    Live Ins: %EAX
	    Predecessors according to CFG: BB#5
1072B		%vreg23<def,dead,tied1> = SUB32ri8 %vreg23<kill,tied0>, 3, %EFLAGS<imp-def>; GR32:%vreg23
1088B		JE_1 <BB#9>, %EFLAGS<imp-use,kill>
1104B		JMP_1 <BB#10>
	    Successors according to CFG: BB#9 BB#10
> %EAX<def,dead,tied1> = SUB32ri8 %EAX<kill,tied0>, 3, %EFLAGS<imp-def>
> JE_1 <BB#9>, %EFLAGS<imp-use,kill>
> JMP_1 <BB#10>
1120B	BB#7: derived from LLVM BB %sw.bb
	    Predecessors according to CFG: BB#4
1136B		%vreg125<def> = MOV8rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%ch] GR8:%vreg125
1152B		%vreg124<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg124
1168B		%vreg122<def> = MOVSX64rm32 %vreg124<kill>, 1, %noreg, 108, %noreg; mem:LD4[%nblock] GR64_NOSP:%vreg122 GR64:%vreg124
1184B		%vreg120<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg120
1200B		%vreg119<def> = MOV64rm %vreg120<kill>, 1, %noreg, 64, %noreg; mem:LD8[%block] GR64:%vreg119,%vreg120
1216B		MOV8mr %vreg119<kill>, 1, %vreg122<kill>, 0, %noreg, %vreg125<kill>; mem:ST1[%arrayidx11] GR64:%vreg119 GR64_NOSP:%vreg122 GR8:%vreg125
1232B		%vreg114<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg114
1248B		%vreg112<def> = MOV32rm %vreg114, 1, %noreg, 108, %noreg; mem:LD4[%nblock12] GR32:%vreg112 GR64:%vreg114
1280B		%vreg112<def,tied1> = ADD32ri8 %vreg112<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg112
1296B		MOV32mr %vreg114<kill>, 1, %noreg, 108, %noreg, %vreg112<kill>; mem:ST4[%nblock12] GR64:%vreg114 GR32:%vreg112
1312B		JMP_1 <BB#11>
	    Successors according to CFG: BB#11
> %AL<def> = MOV8rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%ch]
> %RCX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RCX<def> = MOVSX64rm32 %RCX<kill>, 1, %noreg, 108, %noreg; mem:LD4[%nblock]
> %RDX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RDX<def> = MOV64rm %RDX<kill>, 1, %noreg, 64, %noreg; mem:LD8[%block]
> MOV8mr %RDX<kill>, 1, %RCX<kill>, 0, %noreg, %AL<kill>; mem:ST1[%arrayidx11]
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 108, %noreg; mem:LD4[%nblock12]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 108, %noreg, %ECX<kill>; mem:ST4[%nblock12]
> JMP_1 <BB#11>
1328B	BB#8: derived from LLVM BB %sw.bb.14
	    Predecessors according to CFG: BB#5
1344B		%vreg108<def> = MOV8rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%ch] GR8:%vreg108
1360B		%vreg107<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg107
1376B		%vreg105<def> = MOVSX64rm32 %vreg107<kill>, 1, %noreg, 108, %noreg; mem:LD4[%nblock15] GR64_NOSP:%vreg105 GR64:%vreg107
1392B		%vreg103<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg103
1408B		%vreg102<def> = MOV64rm %vreg103<kill>, 1, %noreg, 64, %noreg; mem:LD8[%block17] GR64:%vreg102,%vreg103
1424B		MOV8mr %vreg102<kill>, 1, %vreg105<kill>, 0, %noreg, %vreg108<kill>; mem:ST1[%arrayidx18] GR64:%vreg102 GR64_NOSP:%vreg105 GR8:%vreg108
1440B		%vreg97<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg97
1456B		%vreg95<def> = MOV32rm %vreg97, 1, %noreg, 108, %noreg; mem:LD4[%nblock19] GR32:%vreg95 GR64:%vreg97
1488B		%vreg95<def,tied1> = ADD32ri8 %vreg95<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg95
1504B		MOV32mr %vreg97<kill>, 1, %noreg, 108, %noreg, %vreg95<kill>; mem:ST4[%nblock19] GR64:%vreg97 GR32:%vreg95
1520B		%vreg91<def> = MOV8rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%ch] GR8:%vreg91
1536B		%vreg90<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg90
1552B		%vreg88<def> = MOVSX64rm32 %vreg90<kill>, 1, %noreg, 108, %noreg; mem:LD4[%nblock21] GR64_NOSP:%vreg88 GR64:%vreg90
1568B		%vreg86<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg86
1584B		%vreg85<def> = MOV64rm %vreg86<kill>, 1, %noreg, 64, %noreg; mem:LD8[%block23] GR64:%vreg85,%vreg86
1600B		MOV8mr %vreg85<kill>, 1, %vreg88<kill>, 0, %noreg, %vreg91<kill>; mem:ST1[%arrayidx24] GR64:%vreg85 GR64_NOSP:%vreg88 GR8:%vreg91
1616B		%vreg80<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg80
1632B		%vreg78<def> = MOV32rm %vreg80, 1, %noreg, 108, %noreg; mem:LD4[%nblock25] GR32:%vreg78 GR64:%vreg80
1664B		%vreg78<def,tied1> = ADD32ri8 %vreg78<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg78
1680B		MOV32mr %vreg80<kill>, 1, %noreg, 108, %noreg, %vreg78<kill>; mem:ST4[%nblock25] GR64:%vreg80 GR32:%vreg78
1696B		JMP_1 <BB#11>
	    Successors according to CFG: BB#11
> %AL<def> = MOV8rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%ch]
> %RCX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RCX<def> = MOVSX64rm32 %RCX<kill>, 1, %noreg, 108, %noreg; mem:LD4[%nblock15]
> %RDX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RDX<def> = MOV64rm %RDX<kill>, 1, %noreg, 64, %noreg; mem:LD8[%block17]
> MOV8mr %RDX<kill>, 1, %RCX<kill>, 0, %noreg, %AL<kill>; mem:ST1[%arrayidx18]
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 108, %noreg; mem:LD4[%nblock19]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 108, %noreg, %ECX<kill>; mem:ST4[%nblock19]
> %AL<def> = MOV8rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%ch]
> %RCX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RCX<def> = MOVSX64rm32 %RCX<kill>, 1, %noreg, 108, %noreg; mem:LD4[%nblock21]
> %RDX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RDX<def> = MOV64rm %RDX<kill>, 1, %noreg, 64, %noreg; mem:LD8[%block23]
> MOV8mr %RDX<kill>, 1, %RCX<kill>, 0, %noreg, %AL<kill>; mem:ST1[%arrayidx24]
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 108, %noreg; mem:LD4[%nblock25]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 108, %noreg, %ECX<kill>; mem:ST4[%nblock25]
> JMP_1 <BB#11>
1712B	BB#9: derived from LLVM BB %sw.bb.27
	    Predecessors according to CFG: BB#6
1728B		%vreg74<def> = MOV8rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%ch] GR8:%vreg74
1744B		%vreg73<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg73
1760B		%vreg71<def> = MOVSX64rm32 %vreg73<kill>, 1, %noreg, 108, %noreg; mem:LD4[%nblock28] GR64_NOSP:%vreg71 GR64:%vreg73
1776B		%vreg69<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg69
1792B		%vreg68<def> = MOV64rm %vreg69<kill>, 1, %noreg, 64, %noreg; mem:LD8[%block30] GR64:%vreg68,%vreg69
1808B		MOV8mr %vreg68<kill>, 1, %vreg71<kill>, 0, %noreg, %vreg74<kill>; mem:ST1[%arrayidx31] GR64:%vreg68 GR64_NOSP:%vreg71 GR8:%vreg74
1824B		%vreg63<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg63
1840B		%vreg61<def> = MOV32rm %vreg63, 1, %noreg, 108, %noreg; mem:LD4[%nblock32] GR32:%vreg61 GR64:%vreg63
1872B		%vreg61<def,tied1> = ADD32ri8 %vreg61<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg61
1888B		MOV32mr %vreg63<kill>, 1, %noreg, 108, %noreg, %vreg61<kill>; mem:ST4[%nblock32] GR64:%vreg63 GR32:%vreg61
1904B		%vreg57<def> = MOV8rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%ch] GR8:%vreg57
1920B		%vreg56<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg56
1936B		%vreg54<def> = MOVSX64rm32 %vreg56<kill>, 1, %noreg, 108, %noreg; mem:LD4[%nblock34] GR64_NOSP:%vreg54 GR64:%vreg56
1952B		%vreg52<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg52
1968B		%vreg51<def> = MOV64rm %vreg52<kill>, 1, %noreg, 64, %noreg; mem:LD8[%block36] GR64:%vreg51,%vreg52
1984B		MOV8mr %vreg51<kill>, 1, %vreg54<kill>, 0, %noreg, %vreg57<kill>; mem:ST1[%arrayidx37] GR64:%vreg51 GR64_NOSP:%vreg54 GR8:%vreg57
2000B		%vreg46<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg46
2016B		%vreg44<def> = MOV32rm %vreg46, 1, %noreg, 108, %noreg; mem:LD4[%nblock38] GR32:%vreg44 GR64:%vreg46
2048B		%vreg44<def,tied1> = ADD32ri8 %vreg44<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg44
2064B		MOV32mr %vreg46<kill>, 1, %noreg, 108, %noreg, %vreg44<kill>; mem:ST4[%nblock38] GR64:%vreg46 GR32:%vreg44
2080B		%vreg40<def> = MOV8rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%ch] GR8:%vreg40
2096B		%vreg39<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg39
2112B		%vreg37<def> = MOVSX64rm32 %vreg39<kill>, 1, %noreg, 108, %noreg; mem:LD4[%nblock40] GR64_NOSP:%vreg37 GR64:%vreg39
2128B		%vreg35<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg35
2144B		%vreg34<def> = MOV64rm %vreg35<kill>, 1, %noreg, 64, %noreg; mem:LD8[%block42] GR64:%vreg34,%vreg35
2160B		MOV8mr %vreg34<kill>, 1, %vreg37<kill>, 0, %noreg, %vreg40<kill>; mem:ST1[%arrayidx43] GR64:%vreg34 GR64_NOSP:%vreg37 GR8:%vreg40
2176B		%vreg29<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg29
2192B		%vreg27<def> = MOV32rm %vreg29, 1, %noreg, 108, %noreg; mem:LD4[%nblock44] GR32:%vreg27 GR64:%vreg29
2224B		%vreg27<def,tied1> = ADD32ri8 %vreg27<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg27
2240B		MOV32mr %vreg29<kill>, 1, %noreg, 108, %noreg, %vreg27<kill>; mem:ST4[%nblock44] GR64:%vreg29 GR32:%vreg27
2256B		JMP_1 <BB#11>
	    Successors according to CFG: BB#11
> %AL<def> = MOV8rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%ch]
> %RCX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RCX<def> = MOVSX64rm32 %RCX<kill>, 1, %noreg, 108, %noreg; mem:LD4[%nblock28]
> %RDX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RDX<def> = MOV64rm %RDX<kill>, 1, %noreg, 64, %noreg; mem:LD8[%block30]
> MOV8mr %RDX<kill>, 1, %RCX<kill>, 0, %noreg, %AL<kill>; mem:ST1[%arrayidx31]
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 108, %noreg; mem:LD4[%nblock32]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 108, %noreg, %ECX<kill>; mem:ST4[%nblock32]
> %AL<def> = MOV8rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%ch]
> %RCX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RCX<def> = MOVSX64rm32 %RCX<kill>, 1, %noreg, 108, %noreg; mem:LD4[%nblock34]
> %RDX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RDX<def> = MOV64rm %RDX<kill>, 1, %noreg, 64, %noreg; mem:LD8[%block36]
> MOV8mr %RDX<kill>, 1, %RCX<kill>, 0, %noreg, %AL<kill>; mem:ST1[%arrayidx37]
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 108, %noreg; mem:LD4[%nblock38]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 108, %noreg, %ECX<kill>; mem:ST4[%nblock38]
> %AL<def> = MOV8rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%ch]
> %RCX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RCX<def> = MOVSX64rm32 %RCX<kill>, 1, %noreg, 108, %noreg; mem:LD4[%nblock40]
> %RDX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RDX<def> = MOV64rm %RDX<kill>, 1, %noreg, 64, %noreg; mem:LD8[%block42]
> MOV8mr %RDX<kill>, 1, %RCX<kill>, 0, %noreg, %AL<kill>; mem:ST1[%arrayidx43]
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 108, %noreg; mem:LD4[%nblock44]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 108, %noreg, %ECX<kill>; mem:ST4[%nblock44]
> JMP_1 <BB#11>
2272B	BB#10: derived from LLVM BB %sw.default
	    Predecessors according to CFG: BB#6
2288B		%vreg226<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg226
2304B		%vreg223<def> = MOV32rm %vreg226<kill>, 1, %noreg, 96, %noreg; mem:LD4[%state_in_len46] GR32:%vreg223 GR64:%vreg226
2336B		%vreg223<def,tied1> = SUB32ri8 %vreg223<kill,tied0>, 4, %EFLAGS<imp-def,dead>; GR32:%vreg223
2352B		%vreg221<def> = MOVSX64rr32 %vreg223<kill>; GR64_NOSP:%vreg221 GR32:%vreg223
2368B		%vreg219<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg219
2384B		MOV8mi %vreg219<kill>, 1, %vreg221<kill>, 128, %noreg, 1; mem:ST1[%arrayidx49] GR64:%vreg219 GR64_NOSP:%vreg221
2400B		%vreg216<def> = MOV8rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%ch] GR8:%vreg216
2416B		%vreg215<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg215
2432B		%vreg213<def> = MOVSX64rm32 %vreg215<kill>, 1, %noreg, 108, %noreg; mem:LD4[%nblock50] GR64_NOSP:%vreg213 GR64:%vreg215
2448B		%vreg211<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg211
2464B		%vreg210<def> = MOV64rm %vreg211<kill>, 1, %noreg, 64, %noreg; mem:LD8[%block52] GR64:%vreg210,%vreg211
2480B		MOV8mr %vreg210<kill>, 1, %vreg213<kill>, 0, %noreg, %vreg216<kill>; mem:ST1[%arrayidx53] GR64:%vreg210 GR64_NOSP:%vreg213 GR8:%vreg216
2496B		%vreg205<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg205
2512B		%vreg203<def> = MOV32rm %vreg205, 1, %noreg, 108, %noreg; mem:LD4[%nblock54] GR32:%vreg203 GR64:%vreg205
2544B		%vreg203<def,tied1> = ADD32ri8 %vreg203<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg203
2560B		MOV32mr %vreg205<kill>, 1, %noreg, 108, %noreg, %vreg203<kill>; mem:ST4[%nblock54] GR64:%vreg205 GR32:%vreg203
2576B		%vreg199<def> = MOV8rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%ch] GR8:%vreg199
2592B		%vreg198<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg198
2608B		%vreg196<def> = MOVSX64rm32 %vreg198<kill>, 1, %noreg, 108, %noreg; mem:LD4[%nblock56] GR64_NOSP:%vreg196 GR64:%vreg198
2624B		%vreg194<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg194
2640B		%vreg193<def> = MOV64rm %vreg194<kill>, 1, %noreg, 64, %noreg; mem:LD8[%block58] GR64:%vreg193,%vreg194
2656B		MOV8mr %vreg193<kill>, 1, %vreg196<kill>, 0, %noreg, %vreg199<kill>; mem:ST1[%arrayidx59] GR64:%vreg193 GR64_NOSP:%vreg196 GR8:%vreg199
2672B		%vreg188<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg188
2688B		%vreg186<def> = MOV32rm %vreg188, 1, %noreg, 108, %noreg; mem:LD4[%nblock60] GR32:%vreg186 GR64:%vreg188
2720B		%vreg186<def,tied1> = ADD32ri8 %vreg186<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg186
2736B		MOV32mr %vreg188<kill>, 1, %noreg, 108, %noreg, %vreg186<kill>; mem:ST4[%nblock60] GR64:%vreg188 GR32:%vreg186
2752B		%vreg182<def> = MOV8rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%ch] GR8:%vreg182
2768B		%vreg181<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg181
2784B		%vreg179<def> = MOVSX64rm32 %vreg181<kill>, 1, %noreg, 108, %noreg; mem:LD4[%nblock62] GR64_NOSP:%vreg179 GR64:%vreg181
2800B		%vreg177<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg177
2816B		%vreg176<def> = MOV64rm %vreg177<kill>, 1, %noreg, 64, %noreg; mem:LD8[%block64] GR64:%vreg176,%vreg177
2832B		MOV8mr %vreg176<kill>, 1, %vreg179<kill>, 0, %noreg, %vreg182<kill>; mem:ST1[%arrayidx65] GR64:%vreg176 GR64_NOSP:%vreg179 GR8:%vreg182
2848B		%vreg171<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg171
2864B		%vreg169<def> = MOV32rm %vreg171, 1, %noreg, 108, %noreg; mem:LD4[%nblock66] GR32:%vreg169 GR64:%vreg171
2896B		%vreg169<def,tied1> = ADD32ri8 %vreg169<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg169
2912B		MOV32mr %vreg171<kill>, 1, %noreg, 108, %noreg, %vreg169<kill>; mem:ST4[%nblock66] GR64:%vreg171 GR32:%vreg169
2928B		%vreg165<def> = MOV8rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%ch] GR8:%vreg165
2944B		%vreg164<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg164
2960B		%vreg162<def> = MOVSX64rm32 %vreg164<kill>, 1, %noreg, 108, %noreg; mem:LD4[%nblock68] GR64_NOSP:%vreg162 GR64:%vreg164
2976B		%vreg160<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg160
2992B		%vreg159<def> = MOV64rm %vreg160<kill>, 1, %noreg, 64, %noreg; mem:LD8[%block70] GR64:%vreg159,%vreg160
3008B		MOV8mr %vreg159<kill>, 1, %vreg162<kill>, 0, %noreg, %vreg165<kill>; mem:ST1[%arrayidx71] GR64:%vreg159 GR64_NOSP:%vreg162 GR8:%vreg165
3024B		%vreg154<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg154
3040B		%vreg152<def> = MOV32rm %vreg154, 1, %noreg, 108, %noreg; mem:LD4[%nblock72] GR32:%vreg152 GR64:%vreg154
3072B		%vreg152<def,tied1> = ADD32ri8 %vreg152<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg152
3088B		MOV32mr %vreg154<kill>, 1, %noreg, 108, %noreg, %vreg152<kill>; mem:ST4[%nblock72] GR64:%vreg154 GR32:%vreg152
3104B		%vreg148<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg148
3120B		%vreg145<def> = MOV32rm %vreg148<kill>, 1, %noreg, 96, %noreg; mem:LD4[%state_in_len74] GR32:%vreg145 GR64:%vreg148
3152B		%vreg145<def,tied1> = SUB32ri8 %vreg145<kill,tied0>, 4, %EFLAGS<imp-def,dead>; GR32:%vreg145
3184B		%vreg141<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg141
3200B		%vreg139<def> = MOVSX64rm32 %vreg141<kill>, 1, %noreg, 108, %noreg; mem:LD4[%nblock77] GR64_NOSP:%vreg139 GR64:%vreg141
3216B		%vreg137<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg137
3232B		%vreg136<def> = MOV64rm %vreg137<kill>, 1, %noreg, 64, %noreg; mem:LD8[%block79] GR64:%vreg136,%vreg137
3248B		MOV8mr %vreg136<kill>, 1, %vreg139<kill>, 0, %noreg, %vreg145:sub_8bit<kill>; mem:ST1[%arrayidx80] GR64:%vreg136 GR64_NOSP:%vreg139 GR32:%vreg145
3264B		%vreg131<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr] GR64:%vreg131
3280B		%vreg129<def> = MOV32rm %vreg131, 1, %noreg, 108, %noreg; mem:LD4[%nblock81] GR32:%vreg129 GR64:%vreg131
3312B		%vreg129<def,tied1> = ADD32ri8 %vreg129<kill,tied0>, 1, %EFLAGS<imp-def,dead>; GR32:%vreg129
3328B		MOV32mr %vreg131<kill>, 1, %noreg, 108, %noreg, %vreg129<kill>; mem:ST4[%nblock81] GR64:%vreg131 GR32:%vreg129
	    Successors according to CFG: BB#11
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 96, %noreg; mem:LD4[%state_in_len46]
> %EAX<def,tied1> = SUB32ri8 %EAX<kill,tied0>, 4, %EFLAGS<imp-def,dead>
> %RAX<def> = MOVSX64rr32 %EAX<kill>
> %RCX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> MOV8mi %RCX<kill>, 1, %RAX<kill>, 128, %noreg, 1; mem:ST1[%arrayidx49]
> %AL<def> = MOV8rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%ch]
> %RCX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RCX<def> = MOVSX64rm32 %RCX<kill>, 1, %noreg, 108, %noreg; mem:LD4[%nblock50]
> %RDX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RDX<def> = MOV64rm %RDX<kill>, 1, %noreg, 64, %noreg; mem:LD8[%block52]
> MOV8mr %RDX<kill>, 1, %RCX<kill>, 0, %noreg, %AL<kill>; mem:ST1[%arrayidx53]
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 108, %noreg; mem:LD4[%nblock54]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 108, %noreg, %ECX<kill>; mem:ST4[%nblock54]
> %AL<def> = MOV8rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%ch]
> %RCX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RCX<def> = MOVSX64rm32 %RCX<kill>, 1, %noreg, 108, %noreg; mem:LD4[%nblock56]
> %RDX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RDX<def> = MOV64rm %RDX<kill>, 1, %noreg, 64, %noreg; mem:LD8[%block58]
> MOV8mr %RDX<kill>, 1, %RCX<kill>, 0, %noreg, %AL<kill>; mem:ST1[%arrayidx59]
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 108, %noreg; mem:LD4[%nblock60]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 108, %noreg, %ECX<kill>; mem:ST4[%nblock60]
> %AL<def> = MOV8rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%ch]
> %RCX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RCX<def> = MOVSX64rm32 %RCX<kill>, 1, %noreg, 108, %noreg; mem:LD4[%nblock62]
> %RDX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RDX<def> = MOV64rm %RDX<kill>, 1, %noreg, 64, %noreg; mem:LD8[%block64]
> MOV8mr %RDX<kill>, 1, %RCX<kill>, 0, %noreg, %AL<kill>; mem:ST1[%arrayidx65]
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 108, %noreg; mem:LD4[%nblock66]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 108, %noreg, %ECX<kill>; mem:ST4[%nblock66]
> %AL<def> = MOV8rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD1[%ch]
> %RCX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RCX<def> = MOVSX64rm32 %RCX<kill>, 1, %noreg, 108, %noreg; mem:LD4[%nblock68]
> %RDX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RDX<def> = MOV64rm %RDX<kill>, 1, %noreg, 64, %noreg; mem:LD8[%block70]
> MOV8mr %RDX<kill>, 1, %RCX<kill>, 0, %noreg, %AL<kill>; mem:ST1[%arrayidx71]
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 108, %noreg; mem:LD4[%nblock72]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 108, %noreg, %ECX<kill>; mem:ST4[%nblock72]
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %EAX<def> = MOV32rm %RAX<kill>, 1, %noreg, 96, %noreg; mem:LD4[%state_in_len74]
> %EAX<def,tied1> = SUB32ri8 %EAX<kill,tied0>, 4, %EFLAGS<imp-def,dead>
> %RCX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RCX<def> = MOVSX64rm32 %RCX<kill>, 1, %noreg, 108, %noreg; mem:LD4[%nblock77]
> %RDX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %RDX<def> = MOV64rm %RDX<kill>, 1, %noreg, 64, %noreg; mem:LD8[%block79]
> MOV8mr %RDX<kill>, 1, %RCX<kill>, 0, %noreg, %AL, %EAX<imp-use,kill>; mem:ST1[%arrayidx80]
> %RAX<def> = MOV64rm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%s.addr]
> %ECX<def> = MOV32rm %RAX, 1, %noreg, 108, %noreg; mem:LD4[%nblock81]
> %ECX<def,tied1> = ADD32ri8 %ECX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
> MOV32mr %RAX<kill>, 1, %noreg, 108, %noreg, %ECX<kill>; mem:ST4[%nblock81]
3344B	BB#11: derived from LLVM BB %sw.epilog
	    Predecessors according to CFG: BB#9 BB#8 BB#7 BB#10
3360B		%vreg228<def> = MOV64ri <ga:@add_pair_to_block>; GR64:%vreg228
3392B		%vreg229<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1] GR64:%vreg229
3408B		ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3424B		%RDI<def> = COPY %vreg228<kill>; GR64:%vreg228
3440B		%RSI<def> = COPY %vreg229<kill>; GR64:%vreg229
3456B		CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
3472B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3488B		ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3504B		STACKMAP 1, 0, ...
3520B		ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
3536B		RETQ
> %RDI<def> = MOV64ri <ga:@add_pair_to_block>
> %RSI<def> = MOV64rm <fi#-1>, 1, %noreg, 0, %noreg; mem:LD8[FixedStack-1]
> ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> %RDI<def> = COPY %RDI<kill>
Deleting identity copy.
> %RSI<def> = COPY %RSI<kill>
Deleting identity copy.
> CALL64pcrel32 <ga:@__cyg_profile_func_exit>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSI<imp-use>
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> STACKMAP 1, 0, ...
> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
> RETQ