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7416245 and 7486

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commit ed45d5edc1bd4996008c6c5a9515fbf656caf362 1 parent 4e9f55a
stefan_tauner authored
View
154 symbols/logic/7416245-pwr-1.sym
@@ -0,0 +1,154 @@
+v 20060113 1
+P 0 2300 300 2300 1 0 0
+{
+T 200 2350 5 8 1 1 0 6 1
+pinnumber=4
+T 200 2250 5 8 0 1 0 8 1
+pinseq=1
+T 350 2300 9 8 1 1 0 0 1
+pinlabel=GND
+T 350 2300 5 8 0 1 0 2 1
+pintype=pwr
+}
+P 0 2000 300 2000 1 0 0
+{
+T 200 2050 5 8 1 1 0 6 1
+pinnumber=45
+T 200 1950 5 8 0 1 0 8 1
+pinseq=2
+T 350 2000 9 8 1 1 0 0 1
+pinlabel=GND
+T 350 2000 5 8 0 1 0 2 1
+pintype=pwr
+}
+P 0 1700 300 1700 1 0 0
+{
+T 200 1750 5 8 1 1 0 6 1
+pinnumber=10
+T 200 1650 5 8 0 1 0 8 1
+pinseq=3
+T 350 1700 9 8 1 1 0 0 1
+pinlabel=GND
+T 350 1700 5 8 0 1 0 2 1
+pintype=pwr
+}
+P 0 1400 300 1400 1 0 0
+{
+T 200 1450 5 8 1 1 0 6 1
+pinnumber=39
+T 200 1350 5 8 0 1 0 8 1
+pinseq=4
+T 350 1400 9 8 1 1 0 0 1
+pinlabel=GND
+T 350 1400 5 8 0 1 0 2 1
+pintype=pwr
+}
+P 0 1100 300 1100 1 0 0
+{
+T 200 1150 5 8 1 1 0 6 1
+pinnumber=15
+T 200 1050 5 8 0 1 0 8 1
+pinseq=5
+T 350 1100 9 8 1 1 0 0 1
+pinlabel=GND
+T 350 1100 5 8 0 1 0 2 1
+pintype=pwr
+}
+P 0 800 300 800 1 0 0
+{
+T 200 850 5 8 1 1 0 6 1
+pinnumber=34
+T 200 750 5 8 0 1 0 8 1
+pinseq=6
+T 350 800 9 8 1 1 0 0 1
+pinlabel=GND
+T 350 800 5 8 0 1 0 2 1
+pintype=pwr
+}
+P 0 500 300 500 1 0 0
+{
+T 200 550 5 8 1 1 0 6 1
+pinnumber=21
+T 200 450 5 8 0 1 0 8 1
+pinseq=7
+T 350 500 9 8 1 1 0 0 1
+pinlabel=GND
+T 350 500 5 8 0 1 0 2 1
+pintype=pwr
+}
+P 0 200 300 200 1 0 0
+{
+T 200 250 5 8 1 1 0 6 1
+pinnumber=28
+T 200 150 5 8 0 1 0 8 1
+pinseq=8
+T 350 200 9 8 1 1 0 0 1
+pinlabel=GND
+T 350 200 5 8 0 1 0 2 1
+pintype=pwr
+}
+P 3000 2300 2700 2300 1 0 0
+{
+T 2800 2350 5 8 1 1 0 0 1
+pinnumber=7
+T 2800 2250 5 8 0 1 0 2 1
+pinseq=9
+T 2650 2300 9 8 1 1 0 6 1
+pinlabel=VCC
+T 2650 2300 5 8 0 1 0 8 1
+pintype=pwr
+}
+P 3000 2000 2700 2000 1 0 0
+{
+T 2800 2050 5 8 1 1 0 0 1
+pinnumber=42
+T 2800 1950 5 8 0 1 0 2 1
+pinseq=10
+T 2650 2000 9 8 1 1 0 6 1
+pinlabel=VCC
+T 2650 2000 5 8 0 1 0 8 1
+pintype=pwr
+}
+P 3000 1700 2700 1700 1 0 0
+{
+T 2800 1750 5 8 1 1 0 0 1
+pinnumber=18
+T 2800 1650 5 8 0 1 0 2 1
+pinseq=11
+T 2650 1700 9 8 1 1 0 6 1
+pinlabel=VCC
+T 2650 1700 5 8 0 1 0 8 1
+pintype=pwr
+}
+P 3000 1400 2700 1400 1 0 0
+{
+T 2800 1450 5 8 1 1 0 0 1
+pinnumber=31
+T 2800 1350 5 8 0 1 0 2 1
+pinseq=12
+T 2650 1400 9 8 1 1 0 6 1
+pinlabel=VCC
+T 2650 1400 5 8 0 1 0 8 1
+pintype=pwr
+}
+B 300 0 2400 2600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
+T 2700 2700 8 10 1 1 0 6 1
+refdes=U?
+T 300 2700 9 10 1 0 0 0 1
+7416245
+T 300 2900 5 10 0 0 0 0 1
+device=MC74LCX16245,74LCX16245MTD,SN74LVCH16245A
+T 300 3100 5 10 0 0 0 0 1
+footprint=TSSOP48
+T 300 3300 5 10 0 0 0 0 1
+author=Stefan Tauner
+T 300 3500 5 10 0 0 0 0 1
+documentation=http://www.onsemi.com/pub/Collateral/MC74LCX16245-D.PDF
+T 300 3700 5 10 0 0 0 0 1
+description=16-Bit Transceiver
+T 300 3900 5 10 0 0 0 0 1
+numslots=0
+T 300 4100 5 10 0 0 0 0 1
+dist-license=GPLv3, see http://www.gnu.org/licenses/gpl-3.0.txt
+T 300 4300 5 10 0 0 0 0 1
+use-license=unlimited
View
72 symbols/logic/7416245-pwr-1.sym.tragesym
@@ -0,0 +1,72 @@
+# This is the template file for creating symbols with tragesym
+# every line starting with '#' is a comment line.
+
+[options]
+# wordswap swaps labels if the pin is on the right side an looks like this:
+# "PB1 (CLK)". That's useful for micro controller port labels
+# rotate_labels rotates the pintext of top and bottom pins
+# this is useful for large symbols like FPGAs with more than 100 pins
+# sort_labels will sort the pins by it's labels
+# useful for address ports, busses, ...
+wordswap=yes
+rotate_labels=yes
+sort_labels=no
+generate_pinseq=yes
+sym_width=2400
+pinwidthvertical=300
+pinwidthhorizontal=300
+
+[geda_attr]
+# name will be printed in the top of the symbol
+# name is only some graphical text, not an attribute
+# version specifies a gschem version.
+# if you have a device with slots, you'll have to use slot= and slotdef=
+# use comment= if there are special information you want to add
+version=20060113 1
+name=7416245
+device=MC74LCX16245,74LCX16245MTD,SN74LVCH16245A
+refdes=U?
+footprint=TSSOP48
+description=16-Bit Transceiver
+documentation=http://www.onsemi.com/pub/Collateral/MC74LCX16245-D.PDF
+author=Stefan Tauner
+dist-license=GPLv3, see http://www.gnu.org/licenses/gpl-3.0.txt
+use-license=unlimited
+numslots=0
+#slot=1
+#slotdef=1:
+#slotdef=2:
+#slotdef=3:
+#slotdef=4:
+#comment=
+#comment=
+#comment=
+
+[pins]
+# tabseparated list of pin descriptions
+# ----------------------------------------
+# pinnr is the physical number of the pin
+# seq is the pinseq= attribute, leave it blank if it doesn't matter
+# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr)
+# style can be (line,dot,clk,dotclk,none). none if only want to add a net
+# posit. can be (l,r,t,b) or empty for nets
+# net specifies the name of the net. Vcc or GND for example.
+# label represents the pinlabel.
+# negation lines can be added with "\_" example: \_enable\_
+# if you want to write a "\" use "\\" as escape sequence
+#-----------------------------------------------------
+#pinseq type style posit. net label
+#-----------------------------------------------------
+4 pwr line l GND GND
+45 pwr line l GND GND
+10 pwr line l GND GND
+39 pwr line l GND GND
+15 pwr line l GND GND
+34 pwr line l GND GND
+21 pwr line l GND GND
+28 pwr line l GND GND
+
+7 pwr line r Vcc VCC
+42 pwr line r Vcc VCC
+18 pwr line r Vcc VCC
+31 pwr line r Vcc VCC
View
420 symbols/logic/7416245.sym
@@ -0,0 +1,420 @@
+v 20100214 2
+P 900 5600 900 5400 1 0 0
+{
+T 850 5400 5 8 1 1 90 0 1
+pinnumber=48
+T 950 5400 5 8 0 1 90 2 1
+pinseq=2
+T 900 5250 9 8 1 1 90 6 1
+pinlabel=\_OE1\_
+T 900 5250 5 8 0 1 90 8 1
+pintype=in
+}
+V 900 5350 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
+P 1200 5600 1200 5300 1 0 0
+{
+T 1150 5400 5 8 1 1 90 0 1
+pinnumber=1
+T 1250 5400 5 8 0 1 90 2 1
+pinseq=1
+T 1200 5250 9 8 1 1 90 6 1
+pinlabel=T/\_R1\_
+T 1200 5250 5 8 0 1 90 8 1
+pintype=in
+}
+P 1900 5000 1600 5000 1 0 0
+{
+T 1700 5050 5 8 1 1 0 0 1
+pinnumber=2
+T 1700 4950 5 8 0 1 0 2 1
+pinseq=4
+T 1550 5000 9 8 1 1 0 6 1
+pinlabel=B0
+T 1550 5000 5 8 0 1 0 8 1
+pintype=io
+}
+P 1900 4700 1600 4700 1 0 0
+{
+T 1700 4750 5 8 1 1 0 0 1
+pinnumber=3
+T 1700 4650 5 8 0 1 0 2 1
+pinseq=6
+T 1550 4700 9 8 1 1 0 6 1
+pinlabel=B1
+T 1550 4700 5 8 0 1 0 8 1
+pintype=io
+}
+P 1900 4400 1600 4400 1 0 0
+{
+T 1700 4450 5 8 1 1 0 0 1
+pinnumber=5
+T 1700 4350 5 8 0 1 0 2 1
+pinseq=8
+T 1550 4400 9 8 1 1 0 6 1
+pinlabel=B2
+T 1550 4400 5 8 0 1 0 8 1
+pintype=io
+}
+P 1900 4100 1600 4100 1 0 0
+{
+T 1700 4150 5 8 1 1 0 0 1
+pinnumber=6
+T 1700 4050 5 8 0 1 0 2 1
+pinseq=10
+T 1550 4100 9 8 1 1 0 6 1
+pinlabel=B3
+T 1550 4100 5 8 0 1 0 8 1
+pintype=io
+}
+P 1900 3800 1600 3800 1 0 0
+{
+T 1700 3850 5 8 1 1 0 0 1
+pinnumber=8
+T 1700 3750 5 8 0 1 0 2 1
+pinseq=12
+T 1550 3800 9 8 1 1 0 6 1
+pinlabel=B4
+T 1550 3800 5 8 0 1 0 8 1
+pintype=io
+}
+P 1900 3500 1600 3500 1 0 0
+{
+T 1700 3550 5 8 1 1 0 0 1
+pinnumber=9
+T 1700 3450 5 8 0 1 0 2 1
+pinseq=14
+T 1550 3500 9 8 1 1 0 6 1
+pinlabel=B5
+T 1550 3500 5 8 0 1 0 8 1
+pintype=io
+}
+P 1900 3200 1600 3200 1 0 0
+{
+T 1700 3250 5 8 1 1 0 0 1
+pinnumber=11
+T 1700 3150 5 8 0 1 0 2 1
+pinseq=16
+T 1550 3200 9 8 1 1 0 6 1
+pinlabel=B6
+T 1550 3200 5 8 0 1 0 8 1
+pintype=io
+}
+P 1900 2900 1600 2900 1 0 0
+{
+T 1700 2950 5 8 1 1 0 0 1
+pinnumber=12
+T 1700 2850 5 8 0 1 0 2 1
+pinseq=18
+T 1550 2900 9 8 1 1 0 6 1
+pinlabel=B7
+T 1550 2900 5 8 0 1 0 8 1
+pintype=io
+}
+P 1900 2600 1600 2600 1 0 0
+{
+T 1700 2650 5 8 1 1 0 0 1
+pinnumber=13
+T 1700 2550 5 8 0 1 0 2 1
+pinseq=22
+T 1550 2600 9 8 1 1 0 6 1
+pinlabel=B8
+T 1550 2600 5 8 0 1 0 8 1
+pintype=io
+}
+P 1900 2300 1600 2300 1 0 0
+{
+T 1700 2350 5 8 1 1 0 0 1
+pinnumber=14
+T 1700 2250 5 8 0 1 0 2 1
+pinseq=24
+T 1550 2300 9 8 1 1 0 6 1
+pinlabel=B9
+T 1550 2300 5 8 0 1 0 8 1
+pintype=io
+}
+P 1900 2000 1600 2000 1 0 0
+{
+T 1700 2050 5 8 1 1 0 0 1
+pinnumber=16
+T 1700 1950 5 8 0 1 0 2 1
+pinseq=26
+T 1550 2000 9 8 1 1 0 6 1
+pinlabel=B10
+T 1550 2000 5 8 0 1 0 8 1
+pintype=io
+}
+P 1900 1700 1600 1700 1 0 0
+{
+T 1700 1750 5 8 1 1 0 0 1
+pinnumber=17
+T 1700 1650 5 8 0 1 0 2 1
+pinseq=28
+T 1550 1700 9 8 1 1 0 6 1
+pinlabel=B11
+T 1550 1700 5 8 0 1 0 8 1
+pintype=io
+}
+P 1900 1400 1600 1400 1 0 0
+{
+T 1700 1450 5 8 1 1 0 0 1
+pinnumber=19
+T 1700 1350 5 8 0 1 0 2 1
+pinseq=30
+T 1550 1400 9 8 1 1 0 6 1
+pinlabel=B12
+T 1550 1400 5 8 0 1 0 8 1
+pintype=io
+}
+P 1900 1100 1600 1100 1 0 0
+{
+T 1700 1150 5 8 1 1 0 0 1
+pinnumber=20
+T 1700 1050 5 8 0 1 0 2 1
+pinseq=32
+T 1550 1100 9 8 1 1 0 6 1
+pinlabel=B13
+T 1550 1100 5 8 0 1 0 8 1
+pintype=io
+}
+P 1900 800 1600 800 1 0 0
+{
+T 1700 850 5 8 1 1 0 0 1
+pinnumber=22
+T 1700 750 5 8 0 1 0 2 1
+pinseq=34
+T 1550 800 9 8 1 1 0 6 1
+pinlabel=B14
+T 1550 800 5 8 0 1 0 8 1
+pintype=io
+}
+P 1900 500 1600 500 1 0 0
+{
+T 1700 550 5 8 1 1 0 0 1
+pinnumber=23
+T 1700 450 5 8 0 1 0 2 1
+pinseq=36
+T 1550 500 9 8 1 1 0 6 1
+pinlabel=B15
+T 1550 500 5 8 0 1 0 8 1
+pintype=io
+}
+P 100 5000 400 5000 1 0 0
+{
+T 300 5050 5 8 1 1 0 6 1
+pinnumber=47
+T 300 4950 5 8 0 1 0 8 1
+pinseq=3
+T 450 5000 9 8 1 1 0 0 1
+pinlabel=A0
+T 450 5000 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 4700 400 4700 1 0 0
+{
+T 300 4750 5 8 1 1 0 6 1
+pinnumber=46
+T 300 4650 5 8 0 1 0 8 1
+pinseq=5
+T 450 4700 9 8 1 1 0 0 1
+pinlabel=A1
+T 450 4700 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 4400 400 4400 1 0 0
+{
+T 300 4450 5 8 1 1 0 6 1
+pinnumber=44
+T 300 4350 5 8 0 1 0 8 1
+pinseq=7
+T 450 4400 9 8 1 1 0 0 1
+pinlabel=A2
+T 450 4400 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 4100 400 4100 1 0 0
+{
+T 300 4150 5 8 1 1 0 6 1
+pinnumber=43
+T 300 4050 5 8 0 1 0 8 1
+pinseq=9
+T 450 4100 9 8 1 1 0 0 1
+pinlabel=A3
+T 450 4100 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 3800 400 3800 1 0 0
+{
+T 300 3850 5 8 1 1 0 6 1
+pinnumber=41
+T 300 3750 5 8 0 1 0 8 1
+pinseq=11
+T 450 3800 9 8 1 1 0 0 1
+pinlabel=A4
+T 450 3800 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 3500 400 3500 1 0 0
+{
+T 300 3550 5 8 1 1 0 6 1
+pinnumber=40
+T 300 3450 5 8 0 1 0 8 1
+pinseq=13
+T 450 3500 9 8 1 1 0 0 1
+pinlabel=A5
+T 450 3500 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 3200 400 3200 1 0 0
+{
+T 300 3250 5 8 1 1 0 6 1
+pinnumber=38
+T 300 3150 5 8 0 1 0 8 1
+pinseq=15
+T 450 3200 9 8 1 1 0 0 1
+pinlabel=A6
+T 450 3200 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 2900 400 2900 1 0 0
+{
+T 300 2950 5 8 1 1 0 6 1
+pinnumber=37
+T 300 2850 5 8 0 1 0 8 1
+pinseq=17
+T 450 2900 9 8 1 1 0 0 1
+pinlabel=A7
+T 450 2900 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 2600 400 2600 1 0 0
+{
+T 300 2650 5 8 1 1 0 6 1
+pinnumber=36
+T 300 2550 5 8 0 1 0 8 1
+pinseq=21
+T 450 2600 9 8 1 1 0 0 1
+pinlabel=A8
+T 450 2600 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 2300 400 2300 1 0 0
+{
+T 300 2350 5 8 1 1 0 6 1
+pinnumber=35
+T 300 2250 5 8 0 1 0 8 1
+pinseq=23
+T 450 2300 9 8 1 1 0 0 1
+pinlabel=A9
+T 450 2300 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 2000 400 2000 1 0 0
+{
+T 300 2050 5 8 1 1 0 6 1
+pinnumber=33
+T 300 1950 5 8 0 1 0 8 1
+pinseq=25
+T 450 2000 9 8 1 1 0 0 1
+pinlabel=A10
+T 450 2000 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 1700 400 1700 1 0 0
+{
+T 300 1750 5 8 1 1 0 6 1
+pinnumber=32
+T 300 1650 5 8 0 1 0 8 1
+pinseq=27
+T 450 1700 9 8 1 1 0 0 1
+pinlabel=A11
+T 450 1700 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 1400 400 1400 1 0 0
+{
+T 300 1450 5 8 1 1 0 6 1
+pinnumber=30
+T 300 1350 5 8 0 1 0 8 1
+pinseq=29
+T 450 1400 9 8 1 1 0 0 1
+pinlabel=A12
+T 450 1400 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 1100 400 1100 1 0 0
+{
+T 300 1150 5 8 1 1 0 6 1
+pinnumber=29
+T 300 1050 5 8 0 1 0 8 1
+pinseq=31
+T 450 1100 9 8 1 1 0 0 1
+pinlabel=A13
+T 450 1100 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 800 400 800 1 0 0
+{
+T 300 850 5 8 1 1 0 6 1
+pinnumber=27
+T 300 750 5 8 0 1 0 8 1
+pinseq=33
+T 450 800 9 8 1 1 0 0 1
+pinlabel=A14
+T 450 800 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 500 400 500 1 0 0
+{
+T 300 550 5 8 1 1 0 6 1
+pinnumber=26
+T 300 450 5 8 0 1 0 8 1
+pinseq=35
+T 450 500 9 8 1 1 0 0 1
+pinlabel=A15
+T 450 500 5 8 0 1 0 2 1
+pintype=io
+}
+P 900 0 900 200 1 0 0
+{
+T 850 200 5 8 1 1 90 6 1
+pinnumber=25
+T 950 200 5 8 0 1 90 8 1
+pinseq=20
+T 900 350 9 8 1 1 90 0 1
+pinlabel=\_OE2\_
+T 900 350 5 8 0 1 90 2 1
+pintype=in
+}
+V 900 250 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
+P 1200 0 1200 300 1 0 0
+{
+T 1150 200 5 8 1 1 90 6 1
+pinnumber=24
+T 1250 200 5 8 0 1 90 8 1
+pinseq=19
+T 1200 350 9 8 1 1 90 0 1
+pinlabel=T/\_R2\_
+T 1200 350 5 8 0 1 90 2 1
+pintype=in
+}
+B 400 300 1200 5000 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
+T 1600 5400 8 10 1 1 0 6 1
+refdes=U?
+T 1000 2800 9 10 1 0 90 4 1
+7416245
+T 850 3050 5 10 0 0 0 0 1
+device=MC74LCX16245,74LCX16245MTD,SN74LVCH16245A
+T 850 3250 5 10 0 0 0 0 1
+footprint=TSSOP48
+T 850 3450 5 10 0 0 0 0 1
+author=Stefan Tauner
+T 850 3650 5 10 0 0 0 0 1
+documentation=http://www.onsemi.com/pub/Collateral/MC74LCX16245-D.PDF
+T 850 3850 5 10 0 0 0 0 1
+description=16-Bit Transceiver
+T 850 4050 5 10 0 0 0 0 1
+numslots=0
+T 850 4250 5 10 0 0 0 0 1
+dist-license=GPLv3, see http://www.gnu.org/licenses/gpl-3.0.txt
+T 850 4450 5 10 0 0 0 0 1
+use-license=unlimited
View
96 symbols/logic/7416245.sym.tragesym
@@ -0,0 +1,96 @@
+# This is the template file for creating symbols with tragesym
+# every line starting with '#' is a comment line.
+
+[options]
+# wordswap swaps labels if the pin is on the right side an looks like this:
+# "PB1 (CLK)". That's useful for micro controller port labels
+# rotate_labels rotates the pintext of top and bottom pins
+# this is useful for large symbols like FPGAs with more than 100 pins
+# sort_labels will sort the pins by it's labels
+# useful for address ports, busses, ...
+wordswap=yes
+rotate_labels=yes
+sort_labels=yes
+generate_pinseq=yes
+sym_width=1200
+pinwidthvertical=300
+pinwidthhorizontal=300
+
+[geda_attr]
+# name will be printed in the top of the symbol
+# name is only some graphical text, not an attribute
+# version specifies a gschem version.
+# if you have a device with slots, you'll have to use slot= and slotdef=
+# use comment= if there are special information you want to add
+version=20060113 1
+name=7416245
+device=MC74LCX16245,74LCX16245MTD,SN74LVCH16245A
+refdes=U?
+footprint=TSSOP48
+description=16-Bit Transceiver
+documentation=http://www.onsemi.com/pub/Collateral/MC74LCX16245-D.PDF
+author=Stefan Tauner
+dist-license=GPLv3, see http://www.gnu.org/licenses/gpl-3.0.txt
+use-license=unlimited
+numslots=0
+#numslots=2
+#slot=1
+#slotdef=1:1,48,
+#slotdef=2:24,25,
+#slotdef=3:
+#slotdef=4:
+#comment=
+#comment=
+#comment=
+
+[pins]
+# tabseparated list of pin descriptions
+# ----------------------------------------
+# pinnr is the physical number of the pin
+# seq is the pinseq= attribute, leave it blank if it doesn't matter
+# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr)
+# style can be (line,dot,clk,dotclk,none). none if only want to add a net
+# posit. can be (l,r,t,b) or empty for nets
+# net specifies the name of the net. Vcc or GND for example.
+# label represents the pinlabel.
+# negation lines can be added with "\_" example: \_enable\_
+# if you want to write a "\" use "\\" as escape sequence
+#-----------------------------------------------------
+#pinnr seq type style posit. net label
+#-----------------------------------------------------
+1 in line t T/\_R1\_
+48 in dot t \_OE1\_
+47 io line l A0
+2 io line r B0
+46 io line l A1
+3 io line r B1
+44 io line l A2
+5 io line r B2
+43 io line l A3
+6 io line r B3
+41 io line l A4
+8 io line r B4
+40 io line l A5
+9 io line r B5
+38 io line l A6
+11 io line r B6
+37 io line l A7
+12 io line r B7
+24 in line b T/\_R2\_
+25 in dot b \_OE2\_
+36 io line l A8
+13 io line r B8
+35 io line l A9
+14 io line r B9
+33 io line l A10
+16 io line r B10
+32 io line l A11
+17 io line r B11
+30 io line l A12
+19 io line r B12
+29 io line l A13
+20 io line r B13
+27 io line l A14
+22 io line r B14
+26 io line l A15
+23 io line r B15
View
176 symbols/logic/7486.sym
@@ -0,0 +1,176 @@
+v 20060113 1
+P 0 2000 300 2000 1 0 0
+{
+T 200 2050 5 8 1 1 0 6 1
+pinnumber=1
+T 200 1950 5 8 0 1 0 8 1
+pinseq=1
+T 350 2000 9 8 1 1 0 0 1
+pinlabel=1A
+T 350 2000 5 8 0 1 0 2 1
+pintype=in
+}
+P 0 1700 300 1700 1 0 0
+{
+T 200 1750 5 8 1 1 0 6 1
+pinnumber=2
+T 200 1650 5 8 0 1 0 8 1
+pinseq=2
+T 350 1700 9 8 1 1 0 0 1
+pinlabel=1B
+T 350 1700 5 8 0 1 0 2 1
+pintype=in
+}
+P 0 1400 300 1400 1 0 0
+{
+T 200 1450 5 8 1 1 0 6 1
+pinnumber=3
+T 200 1350 5 8 0 1 0 8 1
+pinseq=3
+T 350 1400 9 8 1 1 0 0 1
+pinlabel=1Y
+T 350 1400 5 8 0 1 0 2 1
+pintype=out
+}
+P 0 1100 300 1100 1 0 0
+{
+T 200 1150 5 8 1 1 0 6 1
+pinnumber=4
+T 200 1050 5 8 0 1 0 8 1
+pinseq=4
+T 350 1100 9 8 1 1 0 0 1
+pinlabel=2A
+T 350 1100 5 8 0 1 0 2 1
+pintype=in
+}
+P 0 800 300 800 1 0 0
+{
+T 200 850 5 8 1 1 0 6 1
+pinnumber=5
+T 200 750 5 8 0 1 0 8 1
+pinseq=5
+T 350 800 9 8 1 1 0 0 1
+pinlabel=2B
+T 350 800 5 8 0 1 0 2 1
+pintype=in
+}
+P 0 500 300 500 1 0 0
+{
+T 200 550 5 8 1 1 0 6 1
+pinnumber=6
+T 200 450 5 8 0 1 0 8 1
+pinseq=6
+T 350 500 9 8 1 1 0 0 1
+pinlabel=2Y
+T 350 500 5 8 0 1 0 2 1
+pintype=out
+}
+P 0 200 300 200 1 0 0
+{
+T 200 250 5 8 1 1 0 6 1
+pinnumber=7
+T 200 150 5 8 0 1 0 8 1
+pinseq=7
+T 350 200 9 8 1 1 0 0 1
+pinlabel=GND
+T 350 200 5 8 0 1 0 2 1
+pintype=pwr
+}
+P 1500 2000 1200 2000 1 0 0
+{
+T 1300 2050 5 8 1 1 0 0 1
+pinnumber=14
+T 1300 1950 5 8 0 1 0 2 1
+pinseq=8
+T 1150 2000 9 8 1 1 0 6 1
+pinlabel=Vcc
+T 1150 2000 5 8 0 1 0 8 1
+pintype=pwr
+}
+P 1500 1700 1200 1700 1 0 0
+{
+T 1300 1750 5 8 1 1 0 0 1
+pinnumber=13
+T 1300 1650 5 8 0 1 0 2 1
+pinseq=9
+T 1150 1700 9 8 1 1 0 6 1
+pinlabel=4B
+T 1150 1700 5 8 0 1 0 8 1
+pintype=in
+}
+P 1500 1400 1200 1400 1 0 0
+{
+T 1300 1450 5 8 1 1 0 0 1
+pinnumber=12
+T 1300 1350 5 8 0 1 0 2 1
+pinseq=10
+T 1150 1400 9 8 1 1 0 6 1
+pinlabel=4A
+T 1150 1400 5 8 0 1 0 8 1
+pintype=in
+}
+P 1500 1100 1200 1100 1 0 0
+{
+T 1300 1150 5 8 1 1 0 0 1
+pinnumber=11
+T 1300 1050 5 8 0 1 0 2 1
+pinseq=11
+T 1150 1100 9 8 1 1 0 6 1
+pinlabel=4Y
+T 1150 1100 5 8 0 1 0 8 1
+pintype=out
+}
+P 1500 800 1200 800 1 0 0
+{
+T 1300 850 5 8 1 1 0 0 1
+pinnumber=10
+T 1300 750 5 8 0 1 0 2 1
+pinseq=12
+T 1150 800 9 8 1 1 0 6 1
+pinlabel=3B
+T 1150 800 5 8 0 1 0 8 1
+pintype=in
+}
+P 1500 500 1200 500 1 0 0
+{
+T 1300 550 5 8 1 1 0 0 1
+pinnumber=9
+T 1300 450 5 8 0 1 0 2 1
+pinseq=13
+T 1150 500 9 8 1 1 0 6 1
+pinlabel=3A
+T 1150 500 5 8 0 1 0 8 1
+pintype=in
+}
+P 1500 200 1200 200 1 0 0
+{
+T 1300 250 5 8 1 1 0 0 1
+pinnumber=8
+T 1300 150 5 8 0 1 0 2 1
+pinseq=14
+T 1150 200 9 8 1 1 0 6 1
+pinlabel=3Y
+T 1150 200 5 8 0 1 0 8 1
+pintype=out
+}
+B 300 0 900 2300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
+T 1200 2400 8 10 1 1 0 6 1
+refdes=U?
+T 300 2400 9 10 1 0 0 0 1
+7486
+T 300 2600 5 10 0 0 0 0 1
+device=74HCT86
+T 300 2800 5 10 0 0 0 0 1
+footprint=SO14
+T 300 3000 5 10 0 0 0 0 1
+author=Stefan Tauner
+T 300 3200 5 10 0 0 0 0 1
+documentation=http://www.ti.com/lit/gpn/cd74hct86
+T 300 3400 5 10 0 0 0 0 1
+description=Quad 2-Input EXCLUSIVE-OR Gate (4x2XOR)
+T 300 3600 5 10 0 0 0 0 1
+numslots=0
+T 300 3800 5 10 0 0 0 0 1
+dist-license=GPLv3, see http://www.gnu.org/licenses/gpl-3.0.txt
+T 300 4000 5 10 0 0 0 0 1
+use-license=unlimited
View
74 symbols/logic/7486.sym.tragesym
@@ -0,0 +1,74 @@
+# This is the template file for creating symbols with tragesym
+# every line starting with '#' is a comment line.
+
+[options]
+# wordswap swaps labels if the pin is on the right side an looks like this:
+# "PB1 (CLK)". That's useful for micro controller port labels
+# rotate_labels rotates the pintext of top and bottom pins
+# this is useful for large symbols like FPGAs with more than 100 pins
+# sort_labels will sort the pins by it's labels
+# useful for address ports, busses, ...
+wordswap=yes
+rotate_labels=no
+sort_labels=no
+generate_pinseq=yes
+sym_width=900
+pinwidthvertical=300
+pinwidthhorizontal=300
+
+[geda_attr]
+# name will be printed in the top of the symbol
+# name is only some graphical text, not an attribute
+# version specifies a gschem version.
+# if you have a device with slots, you'll have to use slot= and slotdef=
+# use comment= if there are special information you want to add
+version=20060113 1
+name=7486
+device=74HCT86
+refdes=U?
+footprint=SO14
+description=Quad 2-Input EXCLUSIVE-OR Gate (4x2XOR)
+documentation=http://www.ti.com/lit/gpn/cd74hct86
+author=Stefan Tauner
+dist-license=GPLv3, see http://www.gnu.org/licenses/gpl-3.0.txt
+use-license=unlimited
+numslots=0
+#slot=1
+#slotdef=1:
+#slotdef=2:
+#slotdef=3:
+#slotdef=4:
+#comment=
+#comment=
+#comment=
+
+[pins]
+# tabseparated list of pin descriptions
+# ----------------------------------------
+# pinnr is the physical number of the pin
+# seq is the pinseq= attribute, leave it blank if it doesn't matter
+# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr)
+# style can be (line,dot,clk,dotclk,none). none if only want to add a net
+# posit. can be (l,r,t,b) or empty for nets
+# net specifies the name of the net. Vcc or GND for example.
+# label represents the pinlabel.
+# negation lines can be added with "\_" example: \_enable\_
+# if you want to write a "\" use "\\" as escape sequence
+#-----------------------------------------------------
+#pinnr seq type style posit. net label
+#-----------------------------------------------------
+1 in line l 1A
+2 in line l 1B
+3 out line l 1Y
+4 in line l 2A
+5 in line l 2B
+6 out line l 2Y
+7 pwr line l GND
+
+14 pwr line r Vcc
+13 in line r 4B
+12 in line r 4A
+11 out line r 4Y
+10 in line r 3B
+9 in line r 3A
+8 out line r 3Y
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