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Stores tag instead of whole address instead directory.

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commit cd62ac6dad8867c575225d67898eb8c98e49d8b8 1 parent 6a998fd
ResumeNothing ResumeNothing authored

Showing 1 changed file with 12 additions and 10 deletions. Show diff stats Hide diff stats

  1. +12 10 cache.cc
22 cache.cc
@@ -53,6 +53,8 @@ Cache::Cache(int s, int a, int b) {
53 53 since this function is an entry point
54 54 to the memory hierarchy (i.e. caches)**/
55 55 void Cache::Access(ulong addr, uchar op, vector<Cache*> &cachesArray, directory &dir, int proc_num) {
  56 + ulong tag;
  57 +
56 58 currentCycle++; /*per cache global counter to maintain LRU order
57 59 among cache ways, updated on every cache access*/
58 60
@@ -60,14 +62,15 @@ void Cache::Access(ulong addr, uchar op, vector<Cache*> &cachesArray, directory
60 62 else { reads++; }
61 63
62 64 cacheLine *line = findLine(addr);
63   -
  65 + tag = calcTag(addr);
  66 +
64 67 if (line == NULL || line->getFlags() == INVALID) { // --=== THESE ARE CACHE MISSES ===--
65   - int index = dir.findTagPos(addr); // search directory for index of tag (-1 denotes not found)
  68 + int index = dir.findTagPos(tag); // search directory for index of tag (-1 denotes not found)
66 69 if (op == 'r') { // READ request
67 70 ++readMisses; // STATS: record read miss
68 71 if (index < 0) { // Case: cache miss, directory miss (read)
69 72 int insert_pos = dir.findUnownedPos(); // find first open directory position
70   - dir.position[insert_pos].setTag(addr); // set directory tag
  73 + dir.position[insert_pos].setTag(tag); // set directory tag
71 74 dir.position[insert_pos].processorOn(proc_num); // turn this processor bit on
72 75 dir.position[insert_pos].setStateEM(); // set directory to EXCLUSIVE_MODIFIED state
73 76 cacheLine *newline = fillLine(addr, dir, proc_num); // put line in cache
@@ -94,7 +97,7 @@ void Cache::Access(ulong addr, uchar op, vector<Cache*> &cachesArray, directory
94 97 ++writeMisses; // STATS: record write miss
95 98 if (index < 0) { // Case: cache miss, directory miss (write)
96 99 int insert_pos = dir.findUnownedPos(); // find first open directory position
97   - dir.position[insert_pos].setTag(addr); // set directory tag
  100 + dir.position[insert_pos].setTag(tag); // set directory tag
98 101 dir.position[insert_pos].processorOn(proc_num); // turn on this processor bit
99 102 dir.position[insert_pos].setStateEM(); // set directory state to EXCLUSIVE_MODIFIED
100 103 dir.position[insert_pos].setDirty(); // set dirty bit on
@@ -114,7 +117,7 @@ void Cache::Access(ulong addr, uchar op, vector<Cache*> &cachesArray, directory
114 117 dir.position[index].processorOff(i); // turn off invalid pocessor bits
115 118 }
116 119 }
117   - dir.position[index].setTag(addr); // set directory tag
  120 + dir.position[index].setTag(tag); // set directory tag
118 121 dir.position[index].processorOn(proc_num); // turn on this processor bit
119 122 dir.position[index].setStateEM(); // set directory state to EXCLUSIVE_MODIFIED
120 123 dir.position[index].setDirty(); // set dirty bit on
@@ -125,7 +128,7 @@ void Cache::Access(ulong addr, uchar op, vector<Cache*> &cachesArray, directory
125 128 }
126 129 }
127 130 else { // --=== THESE ARE CACHE HITS ===--
128   - int index = dir.findTagPos(addr);
  131 + int index = dir.findTagPos(tag);
129 132 if (op == 'r') { // READ request
130 133 // Reading from your own cache on a hit won't do anything (line already tested as valid)
131 134 // Case: cache hit (will never check directory)
@@ -133,7 +136,7 @@ void Cache::Access(ulong addr, uchar op, vector<Cache*> &cachesArray, directory
133 136 else { // WRITE request
134 137 if (index < 0) { // Case: cache hit, directory miss (write)
135 138 //cout << "THIS SHOULD PROBABLY NEVER HAPPEN\n\n";
136   - //dir.position[index].setTag(addr); // set directory tag
  139 + //dir.position[index].setTag(tag); // set directory tag
137 140 //dir.position[index].processorOn(proc_num); // turn on this processor bit
138 141 //dir.position[index].setStateEM(); // set directory state to EXCLUSIVE_MODIFIED
139 142 //dir.position[index].setDirty(); // set dirty bit on
@@ -228,11 +231,11 @@ cacheLine *Cache::findLineToReplace(ulong addr) {
228 231
229 232 /*allocate a new line*/
230 233 cacheLine *Cache::fillLine(ulong addr, directory &dir, int pnum) {
231   - ulong tag;
  234 + ulong tag = calcTag(addr);
232 235
233 236 cacheLine *victim = findLineToReplace(addr);
234 237 if (victim->getFlags() != INVALID) { // on cache eviction
235   - int index = dir.findTagPos(addr); // find position in directory
  238 + int index = dir.findTagPos(tag); // find position in directory
236 239 if (index >= 0) { // if it is in directory
237 240 dir.position[index].processorOff(pnum); // turn off this processor bit
238 241 }
@@ -243,7 +246,6 @@ cacheLine *Cache::fillLine(ulong addr, directory &dir, int pnum) {
243 246 writeBack(addr);
244 247 }
245 248
246   - tag = calcTag(addr);
247 249 victim->setTag(tag);
248 250 victim->setFlags(INVALID);
249 251 /**note that this cache line has been already

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