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base fork: sterlingalexander/CacheSim-2
base: fed06c5bb0
...
head fork: sterlingalexander/CacheSim-2
compare: de43a444a6
  • 2 commits
  • 8 files changed
  • 0 commit comments
  • 1 contributor
9 cache.cc
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@@ -68,18 +68,17 @@ void Cache::Access(ulong addr, uchar op, vector<Cache*> &cachesArray, directory
tag = calcTag(addr);
if (line == NULL || line->getFlags() == INVALID) { // --=== THESE ARE CACHE MISSES ===--
- int index = dir.findTagPos(tag); // search directory for index of tag (-1 denotes not found)
+ cacheLine *newline = fillLine(addr, dir, proc_num); // put line in cache
+ int index = dir.findTagPos(tag); // search directory for index of tag (-1 denotes not found)
if (op == 'r') { // READ request
readMisses++; // STATS: record read miss
if (index < 0) { // Case: cache miss, directory miss (read)
- cacheLine *newline = fillLine(addr, dir, proc_num); // put line in cache
int insert_pos = dir.findUnownedPos(); // find first open directory position
dir.position[insert_pos].setTag(tag); // set directory tag
dir.position[insert_pos].processorOn(proc_num); // turn this processor bit on
dir.position[insert_pos].setStateEM(); // set directory to EXCLUSIVE_MODIFIED state
newline->setFlags(EXCLUSIVE); // set cache state to EXCLUSIVE
} else { // Case: cache miss, directory hit (read)
- cacheLine *newline = fillLine(addr, dir, proc_num); // put line in cache
if (dir.position[index].isEM()) {
cacheToCacheTransfers++;
}
@@ -101,14 +100,12 @@ void Cache::Access(ulong addr, uchar op, vector<Cache*> &cachesArray, directory
} else { // WRITE request
writeMisses++; // STATS: record write miss
if (index < 0) { // Case: cache miss, directory miss (write)
- cacheLine *newline = fillLine(addr, dir, proc_num); // put line in cache
int insert_pos = dir.findUnownedPos(); // find first open directory position
dir.position[insert_pos].setTag(tag); // set directory tag
dir.position[insert_pos].processorOn(proc_num); // turn on this processor bit
dir.position[insert_pos].setStateEM(); // set directory state to EXCLUSIVE_MODIFIED
newline->setFlags(MODIFIED); // set cache state to modified
} else { // Case: cache miss, directory hit (write)
- cacheLine *newline = fillLine(addr, dir, proc_num); // fill cache line
if (dir.position[index].isEM()) {
cacheToCacheTransfers++;
}
@@ -131,6 +128,8 @@ void Cache::Access(ulong addr, uchar op, vector<Cache*> &cachesArray, directory
}
}
} else { // --=== THESE ARE CACHE HITS ===--
+ /**since it's a hit, update LRU**/
+ updateLRU(line);
int index = dir.findTagPos(tag);
if (op == 'r') { // READ request
// Reading from your own cache on a hit won't do anything (line already tested as valid)
0  p3_outputs/debug_32768_32.out 100644 → 100755
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File mode changed
0  p3_outputs/debug_8192_64.out 100644 → 100755
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22 p3_outputs/readme.txt 100644 → 100755
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@@ -1,11 +1,11 @@
-debug runs
-./smp_cache 8192 8 64 canneal.04t.debug > debug_8192_64.out
-./smp_cache 32768 8 32 canneal.04t.debug > debug_32768_32.out
-
-validation runs
-./smp_cache 8192 8 64 canneal.04t.longTrace > val_8192_64.out
-./smp_cache 32768 8 32 canneal.04t.longTrace > val_32768_32.out
-
-Extra runs with longTrace
-./smp_cache 524288 8 64 canneal.04t.longTrace > val_524288_64.out
-./smp_cache 1048576 8 128 canneal.04t.longTrace > val_1048576_128.out
+debug runs
+./smp_cache 8192 8 64 canneal.04t.debug > debug_8192_64.out
+./smp_cache 32768 8 32 canneal.04t.debug > debug_32768_32.out
+
+validation runs
+./smp_cache 8192 8 64 canneal.04t.longTrace > val_8192_64.out
+./smp_cache 32768 8 32 canneal.04t.longTrace > val_32768_32.out
+
+Extra runs with longTrace
+./smp_cache 524288 8 64 canneal.04t.longTrace > val_524288_64.out
+./smp_cache 1048576 8 128 canneal.04t.longTrace > val_1048576_128.out
0  p3_outputs/val_1048576_128.out 100644 → 100755
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File mode changed
0  p3_outputs/val_32768_32.out 100644 → 100755
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File mode changed
0  p3_outputs/val_524288_64.out 100644 → 100755
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File mode changed
0  p3_outputs/val_8192_64.out 100644 → 100755
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File mode changed

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