steveWang/Notes

Fetching contributors…
Cannot retrieve contributors at this time
1824 lines (1818 sloc) 112 KB


EE 105: Devices & Circuits

Wednesday, January 18, 2012.

semiconductor physics. 3-terminal devices.

Office hours: * 512 Cory. * W 2-3, F 10:30-11:30, by appointment. Labs: * 353 Cory. * Partner. * No food. Grading: * Homework 20 * Midterm 20 * Final 30 * Lab 20 * Project 10 Extra credit. Cheating: strongly discouraged.

bspace, Piazza, web page.

Overview

Device Physics * bandgap, dopants, PN, etc. Linearization * operating point * local derivatives time/frequency domain analysis * Heaviside: ODE -> algebra * Bode * Feedback <-> stability I/O impedances

Device Physics

Bohr

Hydrogen spectrum. (plots of intensity vs. frequency. Spectral lines)

Quantized energy levels of electrons orbiting atoms. Bohr model, so to speak: difference of energies would result in the emission of a photon at a specific frequency, which generates a specific wavelength/color.

Si: 1s2 2s2 2p6 3s2 3p2

Pauli Exclusion Principle

twinning

crystal * N atoms. silicon: 5 \cdot 10^{22} per cubic centimeter. * N splits per level. Turn effectively into bands.

valence band, conduction band. zero-energy is somewhere, 8 eV away.

At absolute zero, in semiconductors (and insulators), the valence band is full, and the conduction band is empty.

Conductivity of this material @ T=0 is basically 0. Resistivity is essentially infinite, i.e. electrons can't move.

Slight chance electrons can jump to a different energy level. In their place, they leave "holes". now we have non-zero conductivity and finite resistivity.

The behavior of this follows Fermi-Dirac statistics. i.e. The probability of one of these energy levels being full depends on the energy and the temperature.

(you have your standard Fermi distribution)

k_B T = 26 meV @ room temperature. n_i = 10^{10} electron/hole pairs per cubic centimeter.

Bandgaps:

Si: 1.1 eV, 1.1 um Ge: 0.67 GaAs: 1.4, 0.8 um C (diamond): 5.5 GaN: 3.4, 0.35 um

E = hc/λ λ = hc/E = 1.2 um-eV/E

EE 105: Devices & Circuits

Friday, January 20, 2012.

Lab 1 * Dangerous! * Diodes + $I_D = I_S e^{V_D/V_{DD}}$

EE 105: Devices & Circuits

Monday, January 23, 2012.

Lab 1 * Dangerous! * Diodes + $I_D = I_S e^{V_D/V_{DD}}$

EE 105: Devices & Circuits

Wednesday, January 25, 2012.

Oscilloscope: * Frequency * Amplitude / scale * DC offset * Trigger

DO NOT PRESS [ autoscale ]. Nobody who knows how to use an oscilloscope uses autoscale.

Built-in potential V₀

High-level: why are we studying PN-junction? It's central to every semiconductor device we have. NPN-junction, MOSFET. Basically same thing, but one new thing. Field-effect.

Everything you need to know about these devices aside from field-effect is in the PN-junction.

From last time, if we have a junction, there are more N-type carriers on the N side, and vice versa. Concentration profiles look like Nd ≈ 10¹⁷, peak concentration of other carriers is much less. Reversed on the P side.

Huge gradient from N-type carriers, so they want to flow. However, they leave behind a difference in electric charge – electric potential generated, so we have a resulting electric field (E = -∇V).

In order to have charge neutrality, we have to have that drift and diffusion current cancel each other out perfectly. True for both carrier types and on both sides. True everywhere. Can't be net charge flow in equilibrium.

In terms of concentration, we have gradients. Something happens; we don't know the actual shape.

So... If we assume that this is an abrupt junction (so, as fabricated, there is a uniform concentration of N on one side, uniform concentration of P on the other side – NOT the way real world is; doping is graded), J{drift} = -J{diffusion} for hole currents, qpμ{p}E = qD{p}∇p. Now talking about number of carriers vs. number of coulombs. E = -∇V, so we can make this substitution to eliminate E. Using the Einstein relation, we get that V(x₂) - V(x₁) = (D{p}/μ{p})ln(p(x₂)/p(x₁). Therefore: V{D} = (k{B}T/q) ln(N{A}N{D}/n{i}²). This is the built-in potential.

If a photon comes in with a λ < λ{crit}, i.e. hc/λ ≥ E{g}, it'll create an electron-hole pair. Contributions to n{p} and p{p}.

Characteristic lifetime measured in ns → ms, depending on parameters such as doping: heavier doping ⇒ shorter lifetime. Defects, surfaces. If an electron wanders over and sees the edge of the depletion region, it gets shot back by the electric field.

Thermocouple, similar sort of thing. Vaguely similar. Probably similar.

So what about minority carriers? Right at the edge of the depletion region, it's going to be essentially 0.

lifetime ⇒ diffusion length L{n}, L{p}. Minority carrier diffusion current across edge of depletion region.

qD{n}∇n + qD{p}∇p. Approximate ∇n as n{p}/L{n}, ∇p as p{n}/L{p}.

So the actual current I{diff.min.carriers at edge of dep. reg} = Aq(D{n}n{p}/L{n} + D{p}p{n}/L{p})

[ n{p} = n{i}²/N{A}, p{n} = n{i}²/N{D} ]

= Aqn{i}²(D{n}/(N{A}L{n}) + D{p}/(N{D}L{p})) = I{drift}. Eq 2.99.

Reverse bias Is

At zero bias (V{D}=0), I{drif} + I{diff} = 0 = I{D} (current on diode). In reverse bias, V{D} < 0. We're increasing the electric field, so I{diff} → 0. I{diode} = I{drift} = I{s} (saturation current)

For V{D} < 3k{B}T/q, this might happen.

One last thing to point out: saturation current depends on n{i}². Diode leakage current is a huge function of temperature, as a result.

Linear increase in charge ⇒ quadratic increase in voltage.

Going through and deriving equations is tedious. Not terribly educational. Results: with a voltage V{D} applied, width of the depletion region W = X{n} + X{p} = [2ε(V₀-VD)/q (1/NA + 1/ND)]^{1/2}.

x{n} = W/(1+N{D}/N{A}). x{p} = W/(1+N{A}/N{D}).

Forward bias

exponential current-stuffs.

EE 105: Devices & Circuits

Friday, January 27, 2012.

Everywhere inside there you've got fixed trapped charges. Some number of P or As charges per cc. We only draw them in the depletion region because this is the region where they're actually exposed. (balanced with free electron for charge neutrality outside of the depletion region -- inside depletion region, no charge neutrality, which generates a very nice electric field.)

Integration allows us to figure out what the built-in voltage is.

peak electric field as function of size of depletion region. Do a numeric integral! E{max} is a function of x{n} and dopant and so on. We're not going to do this; you can find it in your 130 textbook if you want. W, the total width of the depletion region, x{n} + x{p}, is equal to √(2εV₀/q (1/N{A} + 1/N{D})⁻¹).

Once you've got that W, you know that capacitance is equal to εA/d. C = εA/W = ε/√(εV₀/q (1/N{A} + 1/N{D})⁻¹) = √(εq/(2V₀) N{A}N{D}/(N{A} + N{D})). Freshman physics.

All of this stays the same, except we replace V₀ with V₀ - V{D}.

AC{j0}/√(1 - stuff)reverse bias:

V{D} < 0, increasing E field, increasing W, decreasing C,
decreasing diffusion, increasing barrier height.

forward bias:

V{D} > 0, decreasing E field, decreasing W, increasing C,
increasing diffusion, decreasing barrier height.

The model breaks down at some point. C{j0}[F/m²].

Varactor: variable capacitor.

electric breakdown: avalanche. lightning.

zener breakdown:

Electrons are somewhat like ball bearings, and holes are somewhat like bubbles. Initially, when you put these things together, the electrons float across. This barrier appears because of electric field and stuff and grows until it's big enough to keep electrons and holes from diffusing across. Less and less energy as you go up. Probability of having energy is exponential. It's less, but it's not zero. Every 26 meV I go up, I decrease by a factor of e. Every 60, I decrease by a factor of 10.

The drift current is, these guys are wandering around. There's not many of them on the p-side, etc. One of them wanders to the edge and gets shot to the other side. Minority carriers that get too close to the edge.

all these things bend. conduction band on either side, distance between fermi levels is, again, qv{r}. larger energy barrier.

thermal excitation. barrier even higher. probability gone down even further. shut off diffusion of majority carriers. nothing done to change diffusion of minority carriers.

zener: electrons actually want to move this way. all drawn in this region. if i dope junctions heavily enough, i shrink depletion region sufficiently and make the potential bigger. it's more stretched, and they physically get closer. if this is narrow enough, i'll get an electron that'll actually tunnel across this barrier. quantum tunneling, wave function having some probability. black magics.

equations 2.91 — 2.99. " provable. "

Forward bias ⇒ reduced barrier height. That's the big handwave.

Last time, we talked about the diffusion we get or the drift current due to minority carriers near the edge. We said that at equilibrium, I{drift} = -I{S}; I{S} = qAn²{i} and more stuff

So we derived this, we also know that I{drift} + I{diff} = 0, since we're at equilibrium. Therefore I{diff} (V{D} = 0) = I{S}, and we know that diffusion current is exponential in this barrier energy thingy. So you've got to get I{diff} = I{s} e^{V{D}/V{th}}. So now I{d} = I{drift} + I{diff} = I{S}(e^{stuff} - 1).

Turn-on voltage. If I've got a diode with I{S} = 10⁻¹⁵ (an ideal diode) at room temperature, what's the current going to be? 0 at no applied voltage; at +26mV, I{D} = 10⁻¹⁵(e-1); et cetera sequantur.

EE 105: Devices & Circuits

Monday, January 30, 2012.

graphing iv curve. turn-on voltage. exponentials look the same. Curve just shifts to right. No such thing as a turn-on voltage for a diode without context.

SPICE

All right. So. Now, let me say a little bit about SPICE. Every company has their own flavor of spice. All of those trees trace their origin back to Cory Hall. Don Peterson and his group. Simulation program, integrated circuit emphasis. Used all over: electromechanical systems, mems, thermal systems, biological systems, etc. Anyway, SPICE is so widely used because it was built by people who needed to use it. Also, it was put in public domain. Good things come out of putting things in public domain.

SPICE. What is it? The idea is that you've got a core program that implements models of device physics (and these evolve over time) that different companies (and there's a framework where you can build your own understanding of device physics)

level 1 through 200 or something like that for MOSFETs. Extensible device physics modeling here for these things.

There's a net list or schematic that says how are these hooked up, the concept of having nodes with node voltages (natural for circuits people to think about) – you get to do it graphically in LTSpice.

It does generate inside of there and spit out a net list.

And then there's device model statements in there, like 2M3904. That's a particular BJT that you've got that you're using in the lab. It has particular parameters that then go in and get used by the device physics inside of this thing.

When you create the model for the 3904, you're using the parameters, e.g. doping levels and more.

And then there's a whole bunch of simulation engines that live inside of this that take all this stuff and spit out a bunch of results.

Since you've got LTSpice, there's a graphical interface. There's also text-based stuff, esp. the .op files.

So. .op, probably the most important one, this one is a nonlinear coupled equation solver. The idea is you wire it with some circuit, and you run .op on that, and it tells you what the voltage is going to be on that thing. Bottom line is, you've got a nonlinear equation here. Fundamentally, you're stuck with this transcendental equation. Pretty much have to use numerical methods for that.

This gives you a "DC" (static) operating point. Most important because it's often the one people ignore, and they don't understand why fancier simulations aren't giving them the results they expect.

Single most important thing to do is check what the DC voltages are at each node (starts with the power supply), and see if they match up with your internal model.

Then, .fran does nonlinear time-varying ordinary differential equation solution. Very broad class, but with nodal analysis, you've got these nonlinear equations, and you throw a capacitor in there, and all of a sudden you've got dynamics.

.ac is the linearized transfer function you get from a defined input to a defined output. How much is the output going to wiggle, and how much does it depend on frequency? This is where we're going to spend most of the semester.

So that's what SPICE does. The linearization, by the way, if I plot I-V on a particular scale, you know that you're operating within an approximate range. One way to solve circuits like this is to use first-order Taylor approximation.

[ talk about what we'll have to do for our homework ]

What you find is as long as your signals are small, you don't have too much error.

On the homework, this is your first introduction to the idea.

Zeners

Most zeners that you buy are actually avalanche diodes that don't actually use the zener effect. What if you had a diode that had a region of very low doping in between the P and N regions (PIN ⇒ P-Insulator-N)? Holds up very well against reverse bias. Could be used in power supplies. Not too useful any more, since power is actually precious. Also works with AC voltage. Step one, put it through a diode to rectify it, then put it through a resistor, then through a zener, a cap to flatten things out. Very useful power supply.

[ talk about solar cells. Optimum value, talks about quadrants in which devices operate. Most in Q1/3. Solar cells in Q4. ]

Schottky discovered this effect that when you have a metal-silicon junction, you get a similar effect to what we see with N+-P+. It's slightly different. You have the conduction band for the metal, and you actually get the band bending, and your N-type semiconductor ends up with its electrons right there.

It turns out when you do this, this barrier is lower. The result is you don't need to put very much forward bias on these things for the electrons to overcome the barrier. High current at low forward bias. Also fast. One thing we haven't discussed is speed. Turns out, it takes a while for most diodes to recombine. And while they're recombining, you've still got current flowing through these things.

So instead of dropping 500mV with a silicon diode, you could drop 50mV with a Schottky. And of course if you want this thing to be a regulated voltage, you throw on yet another diode.

Any questions on diodes? All right. Now I'm going to draw some more diodes. But that's because we're going to start talking about bipolar junction transistors. So. Recall: if I have an N+-P device with 10¹⁷ and 10¹⁵. When I put it in forward bias, I get a big flood of electrons flowing one way and holes flowing the other way, and it's driven by diffusion as per Fick's Law.

So forward bias, I've got I{n} is roughly 100x I{p}. That's basically all we need to recall.

So let's say we make two of these junctions in the same substrate. So I have a p-type substrate, and I'm going to connect a voltage of that of say .5V. I'm going to diffuse in an N+ region at much higher carrier concentration, and I'm going to put another one right next to it. Also, take potential up to 10V reverse bias on the left side. What does this look like? We've got a depletion region, mostly in the P-side, since that's more lightly doped. Very small in the N-side.

So which way does the electron go? Electric field from depletion region is set up such that it's trying to shove all these electrons back. Reverse bias. Turns out very few holes are going to show up. There are some. Now, I'm going to take the right side, and we're going to ground it. Forward bias.

Now I've got this massive current of electrons pouring out of this thing. What's going to happen when they hit this barrier? They get shot right across the depletion region. Huge concentration of electrons here.

It turns out the current from the P-side is much much smaller. Tiny trickle of p-type going back in. Huge gradient going down toward it. Diffusion toward it, and once they hit it, there's drift.

AT&T labs were the first to do this. Germanium substrate with insulating structure. emitter + collector on base. Figures we use today use same labeling.

EE 105: Devices & Circuits

Wednesday, February 1, 2012

Diodes * Small signal model

The idea is that nonlinearities are a pain, and you can basically use
a first-order Taylor approximation -- locally, everything is flat.

You may recall from basic physics, if you're trying to find some f(x),
find some f₀ that you know, then write f(x) as f₀ + Δx. Technically,
you'd use Newton linearization. Works great very close to the point,
i.e in the case of small-signal.

In particular, for a diode, ID = IsV^{VDD/Vth} (ideal diode). If I can
find a bias point, operating point, or whatever, and I've found some
point on this curve, then I can say for small variations around VD*,
we can use a small-signal variation about the operating point. It's
going to technically cause nonlinear variation, but with a small
enough signal, we can ignore the effects of higher-order
terms. Convention says that lower-case means small signal. Presumably
upper-case means large-signal, then.

total distortion you get from nonlinear terms that we threw out tends
to be listed as a spec. Human ears like some forms of distortion more
than other, so some people prefer tube amps over transistor amps.

Local coordinate system: good approximation close to the
center. Probably a good idea to check higher-order terms start
becoming non-negligible.
• PTAT

Proportional to absolute temperature. Very useful circuit to build. The central idea is this: if I have a diode, and I shove some current I₀ through it, that's going to give me some voltage VD₁. If I have some other diode, and I shove nI₀ through that diode, if these two diodes are identical, I'll get some other voltage VD₂. If I consider the difference between these voltages as Vx, Vx = VD₂ - VD₁ = VT(ln n). The difference between these two voltages, then, is proportional to temperature in Kelvin.

• Voltage doubler

Charge pump: charge in parallel, discharge in series. Cap to smooth things out, zener to limit.

BJT physics

Recall: PN-junction. Next to no minority carriers in reverse
bias. Base-emitter junction, base-collector junction.

EE 105: Devices & Circuits

Friday, February 3, 2012

So, in talking to some of you about hte homework, I realized there's at least one thing on there. When I say ideal diode, I mean exponential response of current to voltage. Thinking about region of operation, small signal model for 3-terminal devices.

Simple model for BJTs

If we consider a diode, and it looks like something, there's a bunch of regions of operation of this diode. Power supplies: operating in vastly different regions of said diode. If we're sitting in some zone and increase bias voltage, what do we expect current change to be?

dI{D}/dV{T} = I{D}/V{T}.

rare that we care about something past second decimal point.

Small signal model in a particular region of operation. In region, I look at conductance of diode (reciprocal of small signal resistance V{T}/I{D}).

So let's get back to the bipolar transistor, and, as we said, last time, if I've got an N-type junction and a P-type junction, some depletion region in there, some point called x₁, the concentration of carriers depends on bias. Forward bias: magnitude of currents roughly proportional to magnitude of doping.

Reverse bias, if P has a lower voltage than N, we've got a huge field, shut down diffusion current, and any minority carrier can't diffuse across. Increased energy barrier, made a cliff there, so when an electron hits the cliff, it gets shot across. Minority concentration effectively 0: any thermal noise causes them to get shot to the other side.

Let's say we've got two of these regions put back to back. NPN transistor. Let's say we put this through a 1k resistor. Forward bias on one PN junction. At that voltage, that causes 1 mA of current to flow through this device. [ roughly where we were last time ]

n(x₁) = n{p₁}exp[V{BE}/V{T}] { n{p₁} = n²{i}/N{A} } n(x₂) = 0

Formula for diffusion current is J = D{n}(-q∇n)

transistor is magical: not very much base current: there's some holes flowing across this junction, but orders of magnitude less than electrons flowing. Also electron-hole recombination going on, so those need to be replenished.

Essentially, you've got a small current controlling a much larger current. Magical.

We've got a system. In particular operating conditions, this is 0.6V, and the output is equal to 9V. This current I{C} in here depends exponentially on my bias voltage. What happens if I increase this bias voltage by 26 mV? Factor of e.

EE 105: Devices & Circuits

Monday, February 6, 2012

Few words about lab 2. Talk about BJTs, region of operation, \alpha, \beta, small signal model, early effects. Monday's section, not everyone was able to finish. You can go in to the lab any time during the day or night; encouraged to do that. Seem to not like to leave cabinet unlocked, will try to change that. Shouldn't take too long to finish. Report this time, will give powerpoint template, circuits schematic.

Dopant diffusion (implant 8) 8-in or 12-in. 200mm or 300mm in diameter; thickness is around 650 to 800 microns.

For bipolar, they start with a p-type wafer. Grow an n-type region on top of that. And then use ion implantation and diffusion to make this p-type. So now you've got a p-type wafer, lightly-doped n-type (heavily underneath), and they're all surrounded by p-type material. Most negative voltage, so we're never getting forward bias.

Forward active region of operation.

BE In
+---+-------+----------+
|   |Rev    |   Fwd    |
+---+-------+----------+

BC In |Rev|Cutoff |Forward | | | |active | +---+-------+----------+ |Fwd|Reverse|Saturation| | |active | | +---+-------+----------+

N^+PN^+, wouldn't care which way you ran. Work just the same. Curves would be the same. Called reverse active.We talked about this last time: let's say I increase V{be} by \delta V{be}by 26mV. The 26mV here means that I increase I{c} by some \delta I{c}. That will cause a decrease in voltage. \partial V{ce}/\partialV{bd}.

Operating point: where you first bias a device All of the extra \delta s represent your small signal.

EE 105: Devices & Circuits

Wednesday, February 8, 2012

Talk about RC, LC circuits. If I have a step function that goes from 0 to some current I, I know the differential equation that governs the current on this thing is I/C = dV/dt. Pretty straightforward.

Recall RC = τ. There's some voltage that I'm heading to. The thing I want you to internalize and regurgitate is that the initial slope is where I want to get in τ seconds.

Small-signal model (SSM)

Fleming diode: hot filament + plate (1904). Forest diode: hot filament + grid + plate (1906): three terminal device. Section where he talks about the physics of the device. Hilarious.

1948: point-contact transistor. BJT. Three-terminal device. Pretty quickly after that, people figured out the JFET. Consider N-type material with good N+ connections to it. Now a resistor. Can calculate resistance based on geometry + doping.

Now, put in a P+ material here and make this your gate electrode. By playing with the voltage, we can manipulate the width of the depletion region. Pinch-off: maximum current you effectively can get. All four of these devices have the same picture: three-terminal devices, you've got some control voltage, some output voltage, and there's some output current. And in every case, I can make a device with some V{supply}, a resistor, and increasing V{in} causes an increase in I{out}, which causes a decrease in V{out}. So if I plot V{out} vs. V{in}, I get some kind of a curve that looks vaguely like logistic decay (?). So that's why we care so much about the two control parameters.

I(V{in}, V{out}) = string(V{in})weak(V{out}).

∂I/∂V{in} = g{m}: transconductance, ∂I/∂V{out} = g{o}: output conductance; therefore resistance r{o} = 1/g{o}

We want g{m} to be large and g{o} to be small. Gain is ∂V{out}/∂V{in}.

g{m} = ∂I{c}/∂V{BE} = I{C}/V{T}

EE 105: Devices & Circuits

Friday, February 10, 2012

I{c} = I{s} e^{V{be}/V{T}}(1 + V{out}/V{A}) V{out} = V{cc} - RI{s}e^{V{be}/V{T}}(1 + V{out}/V{A})

Don't try to take V{in} up to V{cc}. Explosions bad.

Nice and analytic. This is a transcendental expression. Have to solve iteratively (e.g. via linearization). Voltage gain = dV{out}/dV{in}, which is roughly V{out}/V{in}. I{c}(V{be},V{ce}) = I{c} + i{c} =I{c}(V{be},V{ce}*)+g{m}v{be}+v{ce}/r{p} Asterisk refers at operating point (small signal model).

g{m} = ΔI/ΔV. g{o} = ΔI/ΔV{ce} ⇒r{o} = ΔV/Δ{I}.

equation of tangent plane at that point.

This is my new circuit now. That looks like voltage controlled current source (g{m}v{be}) with a collector node, an emitter node, base node, etc. So the real device is linearization + operating point + higher order terms we ignore.

So what does that mean when we look at that thing? There's other things in there. There's a voltage source. What does that voltage source look like that's supplying V{cc}? A real voltage source has some source resistance on it, and so if I want to look at my output voltage here, then I get that the current I = (V{out}-V{cc})/R{s} for this device. Actual IV relationship of this non-ideal voltage source. The linear version of this is dI/dV{out}, which is 1/R{s} = g{out}. r{out} = 1/g{out} = R{s}. Any voltage source gets replaced in the small signal model by an R{s}. R{s} = 0 ⇒ ground ("small-signal ground").

Similarly, by the same argument, a current source also turns, at small signals, into an R{s}. An ideal current source has a parallel resistance of ∞. If R{s} is infinite, this turns into the empty set: an open circuit. No current flows into it no matter what voltage change you make.

Steps: Replace voltage source with a ground, replace transistor with linearized version current source and resistor in parallel, emitter grounded. Large signal turns into a short. Voltage source called little v{be}. Both of these go to ground. If we have some source resistance, that would be R{c}. We ignore because it's usually many orders of magnitude larger than source resistance.

Kirchoff's current laws. g{m}v{be} + v{o}/R{out} = 0. We'll do this a lot of times.

So we have v{o}/v{be} = -g{m}R{out} ≡ A. G{M} =∂I{o}/∂V{I} G{out} = ∂I{o}/∂V{out} = 1/R{out}.

g{o} ≠ I{c}/V{ce}. Definitely not. It's the derivative of the curve. Don't make that mistake.

Metal-oxide semiconductors. Used to have metal gates, but now have silicon gates. Not really metal, but they're heavily doped, so it looks like it.

BJT: I{c} = I{s}e^{V{be}/V{T}}(1 + V{ce}/V{A}).

MOS: I{D} = C{1}(V{gs}-V{th})²(1 + v{ds}/v{a}). Exact analogues. Another three-terminal device, weak function of input, strong function of output.

BJTs are much better, but MOS you can fit many more on a chip.

So same weak function part (early effect and all) and strong function part (but now it's a quadratic, not an exponential). Normally,v{gs}-v{th} is about a couple hundred millivolts (whereas V{T} is 26mV @ room temp).

g{o} = ∂I{o}/∂V{DS} = 1/V{A}I{D}, r{o} = V{A}/I{D}. Instead of talking about V{A} in the MOS world, we talk about λ ≡ 1/V{A}. Consider λ as percent change per volt. So if it's .1, it's changing 10% per volt. etc.

changes from n-type to p-type locally. you put a field across there, and you have a mobility as they move. the oxide capacitance here is critical in determining how that happens. smaller gap => larger capacitance.

I{D} = μ{n}C{ox}/2 (V{gs}-V{th})²(1 + λV{DS})

EE 105: Devices & Circuits

Monday, February 13, 2012

Physics of MOSFETs

Discovered and patented in 1927. Going to be black magic for just a minute. For now: recall, in a reverse-biased diode,when we have a voltage source that makes the N-side more positive than the P-side, it takes the existing depletion region and pushes the carriers away and expands the depletion region. Capacitance as a function of V₀ = C{j₀}/√(1 + V{A}/V{D}). C vs. V{r}looks vaguely concave down.

What happens now if we make the same structure but put an insulator between them? I've still got an N-region and a P-region, but now I'm going to put a nearly perfect insulator in the middle (typically SiO₂ in the old days). The fact that silicon dioxide forms a tight, stable oxide with silicon (high temps) is the main reason why silicon took off.Germanium, not so much.

Putting a voltage across, you largely get the same things happening. Still have depletion region expanding. We can call this something oxide silicon. If you dope it sufficiently, it looks like a metal. Fermi level goes up, electrons go into the conduction band.

Polycrystal silicon: "metal". We still experience the same sort of curve. If I go positive enough on the voltage, we'll see a very abrupt shift to a higher capacitance level. Turns out this happens in both the forward as well as reverse direction. Capacitance is just oxide capacitance. What happens is that I end up bending the bands and make the insulator locally n-type. Discovered + patented by Lillian Field in 1927.

The result of this is that I can make a device where I've got a p-type substrate, infuse in two places an n+ region, and I put this gate (typically n+ silicon) on top of a layer of SiO₂. You generally take teh substrate and put it at the lowest level.

If we put a positive voltage, we get a resistance between the two sides. Since this is a capacitor, I don't have to put any current directly into the gate to make it work.

Right now, if you look at the charge density σ[C/cm²] = #cbe/cm²

Separation between the source and drain is length of the transistor. The width into the board is called W, the width of the transistor. This is telling me that I've got a sheet of charge. If I put a potential across, charge moves. σ = C{ox}(V{GS}-V{thresh}). V{gs}>V{th}.

V{G} on gate, V{D} on drain. Assume for now that V{D} ≪ V{GS}-V{th} (overdrive voltage). We can say, then, that our charge density under the gate is as stated above, our electric field is just potential V{DS}/L, and we get a velocity out of this v=μ{n}E. So now we can just puzzle out what the current has to be. The current I{D} = σ[C/cm²]W[cm] ⇒ [C/cm] v[cm/s] ⇒ [C/s] = [A]

I = C{ox)(V{gs} - V{th})Wμ{n}V{DS}/L = μ{n}C{ox}W/L(V{GS}-V{th})V{DS}

μ{n}C{ox}: Fabrication process & materials dependent. W/L : geometry. V{GS}-V{th}: also fab process?

So now we've made ourselves a resistor. Sometimes people draw this as a resistor with a gate (when it's used as a resistor).

R{on} = V{DS}/I{D}. calculations result in 5Ω.

V{G} - V{chann} - V{th} ⇒ V{cc} - V{th}. 〈σ〉 = average charge density in channel. 〈σ〉 =C{ox}(V{gs} - ½V{DS} - V{th}).

So now, if I plug that in, do the same calculation, then I get I{D} = μ{N}C{ox}(V{GS} - ½V{DS} - V{th})V{ds}

r{on} = 1/g{on}. Slope in there is g{on}. As we increase V{gs}, we increase charge density and max allowed electric field.

V{ds,max} = V{gs} - V{th}. I{d,max} = μ{n}C{ox}/2 W/L (V{gs} - V{th})². So now we're getting close. We've got this quadratic behavior of V{gs}.

Where does this come from? As I increase V{gs}, charge density increases linearly. Also increasing linearly is the amount I can put on the drain.

As you're increasing V{gs}, you're increasing energy density.

EE 105: Devices & Circuits

Monday, February 27, 2012

Body effect, Current mirrorers, Voltage followers

We know that MOSFETs actually have 4 terminals: gate, source, drain, and body (biasing the P-). By now, in the MOS, if I'm looking at voltage, $\Phi$ as a function of x going straight down the gate, in the p-type substrate, I've got some $\Phi_p$, short the gate with the substrate, get some potential across the oxide. Finally, bring gate voltage up enough that I bring the surface potential $\Phi_s$ to the point that it's equal in magnitude but opposite in sign so we go from having n-type to having p-type in the channel.

In particular, let's keep the source grounded, but let's assume that we're going to put a different voltage on the bulk, and that's $V_{SB}$. So first off, if I make the source lower than the bulk ($V_{BS} > 0$; source lower potential than body). You generally do NOT forward bias source/body diode. In general, you reverse-bias the source/body diode.

What's going on? You're making your transistors in a p-type substrate. You make a bunch of different transistors. Somewhere on there you've got your p-type contact. If you do anything with that NMOS transistor (aside from set source to ground), you are going to have a bias on this junction.

In particular, when you make your source follower, if you make it with a single transistor and a resistor, you get to hook the bulk and the source together in your ALD1106. Current source: MOSFET (ground substrate). Positive $V_{SB}$ bias for upper device, and for other device, $V_{BS} = 0$. The whole point of MOS electrostatics was so that we could write down what $V_{th}$ was.

$V_{SB} > 0$: What was the effect on $V_{th}$?

assume grounded source, putting $V_{SB}$ bias.

I know what I need to get inversion, I've got $\Phi_p$. Turns out the formula we had before (what the charge is and what we're going to include in there).

What you get is that $V_{th,0} = V_{FB} - 2\Phi_p + \frac{1}{C_ox} \sqrt{ 2q \epsilon_s N_A (-2\Phi_p)}$.

(we now call $\sqrt{ 2q \epsilon_s N_A (-2\Phi_p)}$ $Q_{dep,0}$)

So now we get that $V_{th} = V_{th,0} + \frac{1}{C_ox}\sqrt{2q \epsilon_s N_A (-2\Phi_p + V_SB)} - \frac{1}{C_ox}Q_{dep,0}$.

And so what I get is that $V_{th} = V_{th,0} + \gamma(\sqrt{-2\Phi_p + V_{SB}} - \sqrt{-2\Phi_p})$, $\gamma \equiv \frac{1}{C_ox}\sqrt{2q \epsilon_s N_A}$. $\gamma \approx 0.5 [\sqrt{V}]$.

In particular, you've got a figure on your datasheet that shows (with the gate-drain hooked together and source grounded and applying a potential difference $V_{SB}$ between the source and body) a plot of $V_{GS}$ vs. $I_D$ at various values of $V_{SB}$.

Remember $I_D = \frac{\mu_n C_{ox}}{2}\frac{W}{L}\left(V_{GS} - V_{th} \right)^2(1 + \lambda V_{DS})$ (where $V_{GS} > V_{th}$, $V_{DS} > V_{GS} - V{th} = V_{DSAT}$).

Not quite quadratic -- superquadratic, rather. So. This is $V_{th,0}$, and you did this measurement in lab 4. If you put 12V here, then you know that you're going to end up with a larger threshold voltage, and it takes off.

This is called the body effect.

If I start with an n-type in separate wells, they can have separate body substrates. Normally, I can have the p-well down to ground, but if I'm doing something where I'm stacking these devices (i.e. in a chain; cascaded), your source follower with a current follower node, $V_{in}$ is tied to the drain of this transistor down there.

Triple-well process, where you can make PMOS transistors in my n-type substrate. Put p+ on either side. Both of these two transistors in the same bulk. Various dopings for isolation of wells, so we can make separate body contacts for each of them. These days, you throw a lot of different dopants to make all sorts of things. Not the luxury you have in older / cheaper processes. You'll have to deal with the fact that one of your transistors likely won't be made in a well.

Mirrors

Diode connected. You do the same thing with a MOSFET, I still have a two-terminal device. With a BJT, I had an exponential relationship with current; with a MOSFET, current goes quadratically. When you make a current mirror, it's very common to use a resistor. Stuff about current vs. bias voltage. If you want a mA of current, you just have to set your resistor to go through a specific point (linearization with transcendental equations).

$V = IR$, or equivalently, $\vec{J} = \sigma \vec{E}$.

A resistor is a pretty lousy current source.

EE 105: Devices & Circuits

Wednesday, February 29, 2012

Lab 5 Lab 5 reports body offset impedance of passives amplifier types in/out resistance

Lab 5 parts 1-4: do the experiment during week 7, turn in report during week 8. Parts 5-6: folded into week 8.

Handout: rubric regarding specifications of lab report.

Body offset?

Recall stuff.

Passives

$I = C\deriv{V}{t}$, $V = L\deriv{I}{t}$. $V = V_0\sin(\omega t) \implies \deriv{V}{t} = \omega V_0\cos(\omega t) \implies I = C\omega V_0\cos(\omega t)$. $"R" \equiv Z = \frac{V}{I} = \frac{V_0\sin\omega t}{C\omega V_0\cos(\omega t)}$. $\abs{Z} = \frac{1}{\omega C}$.

We can do a similar thing and get $\abs{Z_L} = \omega L$. On the homework, we're supposed to plot magnitude of impedance vs frequency on a log-log plot.

Amplifier types

Voltage amplifier

You'd like input resistance to be very large (ideally infinite), and output resistance to be very small (ideally zero). $A_v = \frac{v_o}{v_{in}}$

Current amplifier

$A_i = \frac{i_o}{i_{in}}$. Here, we want our output impedance to be infinite and our input impedance to be infinite. $A_i = \frac{i_o}{i_{in}}$

Transconductance amplifier

Mixed. Voltage in, current out. Ideally input and output impedances infinite. $G = \frac{i_o}{v_{in}}$

Finally, transresistance amplifier.

Output resistance 0, input resistance 0 (ideally). $R = \frac{v_o}{i_{in}}$

+-----+-------+-------+ |O / I| V | I | +-----+-------+-------+ | V |0$A_v$ | 0 R 0 | +-----+-------+-------+ | I | $G$ | $A_i$0| +-----+-------+-------+

Input/output resistance.

On the input, you'll have some $R_s$. You'll have some $R_{out}$. You'll have some output load actuator, and it'll have some load resistance $R_L$. Both input and load resistances reduce our gain, which is unfortunate.

Microphone and speaker.

Microphone impedance: electrets that have $R_s > 1M$ (JFET typically has on the order of $1k$). Could have voice coil that has an $R_s$ on the order of $1\Omega$. So that can vary.

On the speaker side.

Voice coils. Anywhere from 4, 8, 16 $\Omega$ for common speakers. Or you can be fancy and use electrostatics (rub graphite on mylar film, put between two fine sheets of metal, put voltage between the sheets, move mylar back and forth. Really hurts when you touch both sides.)

Depends what combination of speaker/microphone you've got in order to decide what values you want.

So let's say we've purchased a bare electret microphone (no integrated JFET that you'd normally find with these things). So let's say $R_s \equiv 1M\Omega$, $V_o = 20mV$ @ desired input volume. You've found a speaker, it's a standard 8 $\Omega$ voice coil speaker, and you've decided that you want 1W of power from this speaker (dissipated). So $P = \frac{V^2} {2R} \implies V = 4V$ (sinusoidal input). Suppose you take some bias voltage, and you stick it into a common emitter amplifier.

Take $\beta \equiv 200$, $V_A \equiv 50V$, $I_s \equiv 1 pA$.

Two issues: huge output resistance relative to load resistance, voltage division, so output voltage isn't really 5V.

Voltage follower would work just fine. But here's the problem: I have this thing biased @ 5V, voltage drop maybe 0.8V, so we've got half an amp flowing through a resistor.

Any reason why we need that speaker directly coupled to the output? Nope. (buffer?!) decoupling, DC-blocking, big, infinite <- all describing some capacitor that we use to block out the DC signal. We want its impedance to be small relative to 8$\Omega$. So we'd like $\frac{1}{\omega C} \ll 8\Omega \implies C \gg \frac{1}{\omega 8\Omega}$. Frequency of interest of a good system is 20 Hz to 20 kHz, or 120-120k rad/sec. high frequencies aren't worrisome. So we want C $\gg \frac{1}{120 rad/sec \cdot 8 \Omega} \implies C \gg 1 mF$.

I still have this problem that I've got my amplifier, and I've got an 8 $\Omega$ load here, so I'd still like to stick something in there such that our output resistance is much less than 8 $\Omega$, and $R_in \gg 1k$ (for "much greater than", factor of 10 is roughly sufficient).

So we have yet another with $r_\pi$, so we need to put in yet another unity-gain buffer (totally different specs regarding impedance, though).

EE 105: Devices & Circuits

Friday, March 2, 2012

Standard diode bridge, allows you to efficiently convert AC to DC. Full-wave rectifier. So now you've got your diode bridge going, typically, to some bypass capacitor, and then back those into a regulator, and you've already seen the very simplest regulator is just a reverse-biased zener diode. And then you've got your regulated supply out.

You can imagine with your regulator, you can actually set the voltage this thing regulates. One common regulator, actually, is a comparator driving a MOSFET. Feedback-controlled regulator. So now, the amount of current I pull out of the transformer depends on what load I hang off of it.

There's no direct relationship between symbols for ground.

LAST TIME:

If I have a voltage amplifier, I know that this thing has some input impedance $R_{in}$, some voltage source that has some output impedance $R_{out}$, and we have some gain. And then I have a voltage source. It has some intrinsic source resistance $R_s$.

For a voltage amplifier, to make it ideal, our input impedance should be infinite. Real systems, 10 $M\Omega$ is pretty common. For very fancy systems, 1 $G\Omega$. Beyond that, you get very weird effects.

Basically, you get that $V_{in} = \frac{R_{in}}{R_{in} + R_s}}V_s$; $V_{out} = AV_s\frac{R_{in}}{R_{in} + R_s}\frac{R_L}{R_L + R_{out}}$. This is assuming that $R_s \ll R_{in}$, $R_{out} \ll R_L$.

We can do the exact same thing for current. We start out with our source, and we'd like to build an amplifier such that we see all of that current. The only way to guarantee that is by having $R_{in}$ just be a short.

Intrinsic Gain

We looked at common-emitter amplifiers, and we know that the gain is $g_m$ multiplied by the resistance. So what if instead of putting a resistance there, I put a perfect current source? What's the gain now? The way to do this is draw the small-signal model, and normally, if we have a resistor up there, we draw that resistance up to an AC ground. If I put a current source there, I still draw that resistance. But if this is an ideal current source (i.e. infinite output impedance), then this goes away.

So if I use conservation of current, $g_m v_i + \frac{1}{R_o} v_o = 0 \implies \frac{v_o}{v_i} = -g_m r_o$.

So both the MOSFET and the BJT, this is the gain for an ideal current source (intrinsic gain). You can make a current source that has a much much bigger input impedance than $r_o$, and then this becomes a pretty good approximation.

For BJT, we have that $g_m = \frac{I_C}{V_T}$, $v_o = \frac{V_A}{I_c}$; $g_m r_o = \frac{v_A}{V_t} > 1000$.

We will see things like $\frac{1}{g_m}$ in parallel with $r_o$. So just for completeness with the MOSFET, there are many ways to write $g_m$. $g_m = \frac{2I_D}{V_{D,SAT}}$; $r_o = \frac{1}{\lambda I_D}$. So $g_m r_o = \frac{2}{\lambda V_{D,SAT}}$. $\lambda$, for your transistors is like 0.02, 0.01. For this class, whenever you see $g_m r_o$, you may assume that $g_m r_o \gg 10$.

So $r_o$ is a device parameter, and when you put the device in a circuit, you start talking about the input and output resistance of that circuit. In particular, if you think of two different examples, might be using in common-emitter with emitter grounded.

Find operating point, draw small signal model, find $\frac{v_i}{i_i}$. That gives you your $r_o, g_m, r_\pi$. So now we draw our small-signal model, and clearly $v_i = i_i r_\pi$ in this simple circuit.

[ insert derivation here. ]

$$v_i - v_o = i_i r_\pi = v_{in} \\ v_o = v_i - i_i r\pi, v_{be} = v_i - v_o \\ \frac{1}{R_x} v_o - g_m v_{be - \frac{1}{r\pi}v_{be} = 0 \\ \frac{1}{R_x}v_o = \left(g_m + \frac{1}{r_\pi}\right)i_i r_\pi \\ r_{in} = r_\pi + (\beta + 1)R_x$$

EE 105: Devices & Circuits

Monday, March 5, 2012

Last time: real amplifiers; idealized model.

Result is you get two voltage dividers.

Similarly, you'll get a voltage divider on the output.

On the lab, in addition to doing parts 5 and 6 from last time's, you'll be designing an amplifier.

Output buffer, etc. The idea is to give you some additional sense as to why you care.

$V_i = V_{BE} + V_{out}$. $V_{BE} = I_i r_\pi$. $V_{out} = I_x R_x$. So we get that $V_i = i_i r_\pi + i_x R_x$. $i_x = i_i + g_m V_{BE} = i_i + g_m i_i r_\pi = i_i(1 + g_m r_\pi) = i_i(1 + \beta)$. This matches what we know.

Plugging this back in, we have $v_i = i_i r_pi + i_i(1 + \beta)R_x$, and $R_{in} = \frac{v_i}{i_i} = r_\pi + (1 + \beta)R_x$. $R_{in} = \frac{\beta V_T}{I_C} + (1 + \beta)(r_o \parallel R_E) = \frac{\beta V_T}{I_C^*} + (1 + \beta)(\frac{V_A}{I_C^*} \parallel \frac{V_E^*}{I_C^*})$

($r_o = \frac{V_A}{I_C^*}$, $R_E = \frac{V_E^*}{I_C^*}$)

So this is equivalent to $\frac{\beta V_T}{I_C^*}(1 + \beta)\frac{V_C^*}{I_C}$.

When looking for output impedance, input is not moving. $R_{out} = r_\pi \parallel r_o \parallel R_E \parallel \frac{1}{g_m} \approx \frac{1}{g_m}$. So why do we care about input and output impedance? From a high level point of view, affects gain of amplifier.

Amplifier Gain

Taylor + IFT. $I_o(V_I, V_o)$. Nonlinear. Find operating point: $(V_I^*, V_o^*)$. And current at that point is 0. You can generalize this, but let's ignore that for now.

We also know that from Taylor, if we know an operating point, we can approximate this with linearization (valid close to operating point).

$I_o(V_I, V_i) = I_o(V_I^*, V_o^*) + \pderiv{I_o}{V_I}V_I + \pderiv{I_o}{V_o}V_o$. x$G_m v_i + G_o v_o = 0$.

$$A_v = -G_m R_o$$ This is still true of many systems outside of circuits.

Specific operating point will lead to no current flow -- no imbalance to correct.

Apply $v_o$, calculate $i_o$, $v_i$ shorted. $G_m = \frac{g_m}{V_i}\bigg| _{V_o=0}$

Do the same later: apply $v_i$, calculate $i_o$ with $v_o$ shorted.

So... let's do a simple example that we already know the answer to.

We are going to wiggle around the operating point that we found.

In this simple case, our transconductance is 0, so we just have $R_o = \frac{V_o}{I_o}\bigg|_{V_i=0} = r_o \parallel R_D$. So now let's make it a little harder. Bipolar emitter source degeneration: bunch of reasons to do it. One is that it stabilizes the gain.

On the homework this week, you'll see that the same circuit for bipolar, if the source degeneration is 0, if you vary process ($I_s$, $V_A$, $\beta$, $\mu_n$, $C_{ox}$, $V_{th}$, $\lambda$), voltage ($V_{CC}$, $V_{DD}$), temperature (also, heating) -- "PVT".

EE 105: Devices & Circuits

Wednesday, March 7, 2012

potatoes

$G_m$, $G_o$, $R_o$, $A_v$.

Graph of $I_C$ vs $V_{CE}$.

Process variation: $I_s$ and other values varying by some amount. Process: $I_s$ varies $2^{\pm 1}$; Voltage: $V_{DD}$ varies $\pm 10\%$; Temperature: $T$ varies $\pm 10$ (this affects values most -- $I_s$ depends heavily on $n_i$ which is a strong function of temperature)

One solution for discrete amplifiers: emitter degeneration (source). You put a resistor at your emitter. You know that if $R_E$ is very small, it'll look as if it isn't there, and if it's very large, you get a follower (of sorts). A change in the emitter current goes directly to the collector currrent.

$G_m \sim \frac{1}{R_E}$ as $R_E$ large, and as $R_E$ small, $G_m \sim g_m$. So what do I do? I draw the small signal model. I'm going to do it for the MOS case so we can ignore $r_\pi$ (which doesn't actually change anything).

more potatoes -- no current flowing, because they have no potential.

some textbooks are between the math and the potato.

derivations, more derivations.

Remember $A_v = -G_m R_o$ whether it's bipolar or MOS, which is equal to $-\frac{g_m}{1 + g_M R_s}\parens{R_o\parallel r_o(1 + g_m R_s)}$. So if $R_s \gg \frac{1}{g_m}$, we get $A_v \approx -\frac{R_D}{R_S} = -\frac{R_C} {R_E}$. So you'll often make five resistors next to each other, and that

EE 105: Devices & Circuits

Friday, March 9, 2012

• lab hints
• LTSpice
• BJT tester
• in digital voltmeter.
• MOS test?
• simplest thing to do, connect gate and drain to 100k resistor to Vdd, make sure that's 0.7 V.

Frequency response

First thing: make sure we agree what the equivalent resistance is of two resistors in parallel and in series. Equivalent resistance of the two is the maximum of the two. Maximum error is 50%. In parallel, we use minimum of the two. Also max error of 50%.

Worst-case error happens when your impedances are equal in magnitude.

So right now, that's what you do.

In particular, if you have an R and a C in parallel, and you want to know what impedance I see, what the magnitude of that impedance is, I'm just going to take the minimium of the magnitude of the impedances, which is simply $\min(R, \frac{1}{\omega C}$. On a log-log plot, we draw R = 1k, $\frac{1}{\omega C}$ -- on a log-log plot, that's a straight line with slope -1. SO that's $\frac{1}{\omega C}$. Since we're considering these in parallel, always take the lower line. There's some error (off by $\sqrt{2}$), but that doesn't really matter.

Tempted to draw capacitive load to $V_{dd}$, but it doesn't really matter. All it means is that it's shorting out a resistor at high frequencies.

One more review thing from last time: potatoes?

Comparing amplifiers. $A_v = -g_m(R_c\parallel r_o)$. In general, this is $-g_mR_c$. Once we add in a resistance, we have $R_o = R_c \parallel r_o(1 + g_mR_E)$; $G_m = \frac{g_m}{1+g_mR_E}$; $A_v = -G_mR_o = -\frac{R_c} {R_E}$.

Gain from base to collector is going to be -10.

EE 105: Devices & Circuits

Wednesday, March 14, 2012

PNP, PMOS

For the PNP, we have

E P+ (highest doping)
B N
C P

(depletion region between B and C; E at higher potential $V_{cc}$; EB forward-biased, BC reverse-biased. Large hole current now going straight across, small number of holes that recombine; small electron current.

Still current multiplication. The arrow is drawn from positive to negative.

$\abs{I_c} = \abs{I_s} e^{\abs{V_{BE}}/V_T}\parens{1 + \frac{\abs{V_{CE}}} {V_A}}$

We need that $V_{BE} < 0$. Similarly, $V_{CE} < 0$. Finally, $I_c < 0$, so $I_s$ must also be negative. Reasoning: to get forward active, we have holes flooding in; we want the junction to be reverse-biased so there's a field that naturally pushes holes and electrons back. But then, with this upper forward-biased diode, we have electrons flooding across.

So what's the result of this? If we plot, we're going to find that you actually need $V_{CE} < V_{CE,sat}$

Region before you hit forward-active. Looks like with NPN, except our axes are both negative, now.

Now, if you're in your local coordinate system (sitting at your bias point), now the question is if I make a small change in $V_{CE}$, I am going to have a positive $I_C$. Purpose: small-signal model will look exactly the same as in the NPN.

VDD
___|___
[       ]
__________=========_____________
\_P+_/           \_P+|N+_/

Pretty close to flat-band, but not quite. As I make this more negative, surface is going to start getting depleted of electrons, and I am going to expose the positive carriers. Eventually, it's going to bend down far enough that the surface potential crosses zero, so right at the surface, I'll start seeing mobile holes.

And when it bends down even further (i.e. $-\Phi_n$). As long as this drain is a little more negative than the source, all of the holes are going to want to flow that way. I need that $V_{DS} < V_{GS} - V_{th}$. etc. With our graph, again, we have negative axes. In this case, $V_{GS} < V_{th} < 0$ -- consider that $\abs{V_{GS}} > \abs{V_{th}}$. Pulldown.

Again, in our local coordinate system, this looks identical to what we saw before (with NMOS).

The thing I want you to remember is that all four of these devices, and in fact JFETs, and in fact vacuum tubes, and everything else, all of them looks like this: control (pops between curves), output (looks more or less linear), in all of them, positive change in voltage means positive differential change in current (whether positive current getting bigger or negative change becoming less negative).

Result: if I draw a PNP common-emitter, the small-signal model is just a mirror image of what we're used to. Positive input means output goes down. Small positive change on input voltage: less current flowing in resistor, so output goes down. So in both cases: small positive change in input means output goes down.

CMOS inverter: NMOS tied to a PMOS. (gates connected, drains connected)

Similarly, if I've got a $V_{BN}$ and a $V_i$, then what do I get? $R_{out} = R \parallel R_{DN}$; $R_{DN} = g_{m2}r_{o2}r_{o1}$. The last one before we move on is two PMOS on top of two NMOS. You can make very high gains doing this.

Let's talk a little bit about Oliver Heaviside. Difficult person to get along with, but amazing guy.

Suppose we've got a serise RC circuit. $i_c = C\pderiv{V_o}{t}$; $i_R = \frac {V_i - V_o}{R}$. So $RC\pderiv{V_o}{t} = \Delta V_i - V_o$. If we assume $V_i = V_x\sin(\omega t)$, we know that $V_o = V_A\sin(\omega t) + V_B\cos(\omega t)$; $\pderiv{V_o}{t} = \omega V_A\cos\omega t - \omega V_B\sin\omega t$. The only way there can be a solution of the equation means that the sum and cosine coefficients have to balanced (method of undetermined coefficients).

cosine and sine axes: real and imaginary. Math works out beautifully.

EE 105: Devices & Circuits

Friday, March 16, 2012

MT2 - Friday in class. OBONNS. Right before spring break.

Heaviside, $H(j\omega)$, Spice, emitter/source impedance, single-pole systems.

Heaviside

Energy-storing elements correspond to poles. Derivatives of output.

$x + jy \equiv Re^{j\theta}$. That angle $\theta$ just corresponds directly to the phase of the sine wave.

So when you go through and replace all these derivatives by a $j\omega$ term to rotate you 90 degrees and scale you appropriately according to the frequency, and you transform this whole thing, the next short-hand is when people get tired of writing $j\omega$, they start calling it $s$. This then starts looking like a polynomial in $s$.

At the end of the day, when we solve for gain ($V_o/V_i$, it then becomes a ratio of two polynomials in $s$. This is our transfer function. At the end of the day, we have $R(s)e^{i\theta(s)}$. If I've got a linear system that's defined by a differential equation relating derivatives of the inputs to derivatives of the outputs, the magnitude of the vector corresponds to the magnitude amplification of a sine, and the phase corresponds to the phase shift of the same sine.

There are some beautiful things people have done.

Clearly, from this, $R = \abs{H(j\omega)}$, $\theta = \angle H(j\omega)$. This is pretty powerful. It means that as long as I've got a linear system, I can get this transfer function. From that one function, I can tell you what the corresponding output is for any input.

So that's the magic that Oliver Heaviside gave to us. Heaviside was the guy who used this to solve differential equations for circuits. Laplace didn't know that his integral could be used to solve differential equations.

SPICE

Spice does all these different analyses. It does a DC or operating point analysis. Operating point says we'll solve nonlinear algebraic equations (i.e. no time-variance). Capacitors are open, and inductors are shorted (i.e. $\omega = 0$. You've seen that, and it takes your nonlinear circuit and figures out that when you put in a particular set of DC biases, it'll go through and tell you the whole system is operating here.

That's .op.

DC is just a sweep of those, It's just a sequence of .op samples.

If you pick a particular operating point, at that operating point, we have a linearized model of the transistor. Once we pick the bias point, we can take derivatives, and make this nonlinear device into circuits made of linear components.

Once we've taken the linearization, now we have an (linear!) ordinary time-invariant differential equation. You can either solve this yourself or have SPICE do it. For simple circuits, you'll get the same answer as SPICE. For complex circuits, you'd get the same answer if you had the time.

AC analysis: Bode plot of linearized system -- linearized around a particular operating point. In particular, different operating points correspond to completely different Bode plots.

Most SPICEs allow you to vary multiple voltage sources simultaneously.

You tell AC what amplitude you want. In AC, you use a start and end frequency, step size (how many per decade), linear / logarithmic; somewhere, there's a source. And all this does is scale the output. That's something to keep in mind: just because .ac tells you something is going to work, that doesn't mean it will.

TO capture this, that's transient analysis. Transient is the full nonlinear time-varying differential equation. There's still ordinary differential equations (they're not partial differential equations), but they're no longer linear.

Transient actually is your best guess as to what's going to show up on the oscilloscope.

.ac gives you an idea of what a sinusoid will look like.

It turns out, by the way, that this concept works for way more than integrated circuits. You can use the same tools to compose mechanical elements in MEMS devices. Came up with SUGAR (doesn't stand for anything). Worked fine.

Back to looking at impedance. So we saw that when you look down into the drain of a transistor at some $R_s$ or into the collector of a BJT at some $R_E$, $R_o = r_o(1 + g_mR_s) \approx g_mr_mR_s$. So what if I'm looking up at a drain resistance? How do we do this? Find an operating point, draw small signal model, apply small signal test voltage, calculate values.

The key thing to note here is that you don't know how the current splits between devices, but all of it goes through $R_D$. So the voltage at the drain is equal to $i_xR_D$. We also know that $V_{GS} = 0 - V_x$, and $V_{DS} = i_xR_D - V_x$. So if we do KCL at $V_x$, the sum of all currents entering that node has to be zero, so $i_x + g_m v_{gs} + \frac{1}{ro} v_{ds} = 0$. We want to find $R_{out} = \frac{V_{out}}{i_x} = \frac{1}{g_m} \parens{1 + \frac{R_D}{r_o}}\parens{\frac{1}{1 + \frac{1}{g_m r_o}}}$. Roughly $1/g_m (R_D \ll r_o)$; $R_D/g_mr_o (R_D \gg r_o)$

Good idea on your exams is to check your formulas and make sure everything you're adding together has the same unit.

SO: what we see is that if you put something on the source, it looks bigger when seen from the drain, and when you put something on the drain, it looks smaller when seen from the source.

Good midterm question is "looking into each of these nodes, what impedance do I see?"

Discussion

Discussion: Monday, March 19, 2012

Discussion today!

Techniques in finding impedance, then homework.

Probably will be okay, but if not, stop me, and I'll explain.

So let's start with a cascode. What is the output resistance looking down into the drain of the top MOSFET? $r_{o2} + (1 + g_{m2}v_{o2})r_{o1}$.

So now we want to find the impedance looking up into the source.

Impedance transformation. Explanation upcoming.

Here, impedance is the ratio between voltage and current. You need two things to explain electrical conductivity. You need both voltage and current. The relationship is called impedance.

EE 105: Devices & Circuits

Monday, March 19, 2012

Single-pole systems, Bode plots. Homework, just posted solutions. Would encourage to treat homework as midterm. Sit down and see what you get.

Midterm covers everything. Stuff on homework, stuff on the labs. MOS physics. A little about potential in the cross-section of a MOS device.

That midterm is not a perfect reflection of what you're going to see.

If we just look at our amplifier with some output resistance driving some load (perhaps resistive), then it's certainly in parallel. Whether you make this a MOS or bipolar amplifier with capacitances to ground or some fixed voltage, there's always going to be some intrinsic capacitance.

You know your gain is the $g_m$ times the output impedance. We know impedance of capacitors goes down with frequency, etc. So what you end up with is a very common thing: current source of $G_mv_i$ in parallel with $R_{out}$ and $C_{load}$. If we do KCL in this circuit, the sum of current in the three branches is equal to zero. We know $i = C\pderiv{V}{t}$, and as Master Heaviside teaches us, derivatives are just rotations by ninety degrees. Thus our current is $C\pderiv{V}{t} \equiv j\omega CV$; since we get tired of writing $j\omega$ all the time, we call this $sCV$.

So we have $R_{cc}$ @ $V_0$. Our transfer function, remember, is $H(\omega) = \frac{V_o}{V_i} = \frac{-G_m}{\frac{1}{R_{out} + sC_{load}}} = \frac{-G_m R_{out}}{1 + sR_{out}C_{load}}$.

So we've got several cases for $\abs{H(j\omega)} = \abs{\frac{-G_m R_{out}} {1 + j\omega R_{out} C_{load}}}$: either $\omega \ll \frac{1}{R_{out} C_{load}}$, in which case it's just $G_m R_{out}$; or $\omega = \frac{1} {R_{out}C_{load}}$, in which case it's roughly divided by $\sqrt{2}$; or $\omega \gg \frac{1} {R_{out}C_{load}}$, in which case it's just $\frac{ G_m}{\omega C_{load}}$.

Unity gain frequency (i.e. $\abs{H(j\omega_u)} = 1$)? $\omega_u = \frac{G_m }{C_{load}}$. This bottom one, this is basically just $G_m Z_{cap}$, which happens to also be the unity-gain frequency. So the gain above that point just happens to be $\frac{\omega_u}{\omega}$

The fun thing about EE is that you get to work with systems that span many many decades of frequencies.

Four simple formulas for single-pole systems:

$$A_{v,0} = A_v = \abs{H(j\omega)} = G_m R_{out} \\ \omega_p = \frac{1}{R_{out} C_{load}} \\ \omega_u = \frac{G_m}{C_{load}} \\ \omega_u = A_{v,0}\omega_p$$

So once we've got $\omega_u$ and $A_{v,0}$, we can get $\omega_p$. If we know the pole frequency and the load, we know that $G_m = \omega_u C_{load}$. We can find everything given just a handful of values.

$G_m = \frac{I_c}{V_T} = \frac{1 \mu A}{26 mV}$. Now if I said 1 nA, no way.

Plots of magnitude for single-pole systems. Got to be able to draw this in sleep by the time you take midterm (roughly constant at $A_{v,0}$ until $\omega_p$; drops off linearly and hits 1 at $\omega_u$.

Trading off DC gain for low-frequency gain accuracy.

So what happens if we increase $R_o$? DC gain goes up, poles frequency goes down, and nothing happens at unity gain frequency.

And if we increase $C_{load}$? We shift the graph to the left. Generally bad -- all things being equal, you'd like to have as much bandwidth as possible. Also, increasing $R_o$ is good.

The last parameter we get to control is $G_m$. Note that there's no effect on $\omega_p$. It just lifts the curve up directly. This is a great thing. However, the problem is that it costs you power.

All right. All right. So that's single-pole systems. Very simple, but very important.

So let's go back to the transient response. We haven't talked about phase yet. So how do we calculate the angle of $H(j\omega)$? When $\omega \ll \omega_p$, then our phase is effectively $\pi$ (assume that sign of $G_m$ is positive).

When $\omega \gg \omega_p$, what happens? We get a $\frac{\pi}{2}$: in the denominator, the second term dominates, so this is roughly $\frac{-1}{j} = j$.

How do we get there? When $\omega = \omega_p$, we get roughly $\frac{3\pi} {4}$.

Consider: all we're doing is increasing the imaginary component relative to the real component (which is negative!), so this certainly goes through the motions and hits $\infty$ when we reach $\theta \equiv \frac{\pi}{2}$.

Problem: radians vs degrees; wraparound; modulo 360 or $2\pi$. If you're caring about phase, you're probably talking about stability.

You all know how to draw the phase; the interval spanning from one decade before to one decade after $\omega_p$ defines our linear region.

For Bode plot, straight line approximation; fine. However, accuracy demands that we consider the actual numerical values (not going to be drawn): just examine the unit circle and reference triangles, and use small signal approximation.

EE 105: Devices & Circuits

Wednesday, March 21, 2012

Midterm Friday; OBONNS.

Today: Graphing and calculating $G_m$, $R_o$, $A_v$, keep talking about frequency response.

Graphings

So, the thing to do: you know you're going to have (if I've got some $A_0\sin(\omega t) \mapsto \abs{H(j\omega)}A_0\sin(\omega t + \angle H(\omega))$. If I give you a plot of angle or frequency, one way or another, you've got to find the angle of $H(j\omega)$. Also, find max/min voltages (determined by gain at various stages). Should make sure that those points are marked (circled, even) so Pister can see that we know what's up.

If it's greater than 0, it's called "phase lead". You want to find and label and mark zero-crossings and min/max in time (which is really in phase). Points move left.

If it's less than 0, it's called "phase lag", and points move right.

Calculating $G_m$, $R_o$

There have been some questions about this on Piazza. There's the basics, like when you're looking into a collector or a drain, you're going to see $r_o$; when you're looking into an emitter or a source, and the collector/drain are at some AC ground, you're going to see $\frac{1}{g_m}$, and then there's the blocks that you know and ought to recognize/use in circuits, which are: what happens if I have some emitter degeneration or some source degeneration ($G_m \equiv \frac{g_m}{1 + g_m R_s}$ for MOS, $R_s \equiv R_E \parallel r_\pi$); if I'm looking into the source/emitter, then this looks like $\frac{1}{g_m}\parens{1 + \frac{R_D}{r_o}}$. Note that for a BJT, you have $r_\pi$ in parallel with this whole thing.

For example: steps for finding gain: $A_v = -G_m R_o$. In general, this is how you'll find gain. $G_m = \frac{I_o}{V_i}\bigg|_{v_i=0}$. Straight taylor approximation: this is why we set $V_o = 0$ when calculating $G_m$ and $V_i = 0$ when calculating $R_o$.

When doing $G_m$ calculation, we just don't care about anything above the junction.

Mentally, what people like Razavi do is say "aha! I've got a bias voltage on that gate; this thing now is one of my basic elements! Aha! I've got a $\frac{1}{g_m}$ to ground, and now I can draw my small signal model." And so the current coming out is roughly $g_m v_i$. The only time you look up is if there's a current source up there that depends on one of the lower node voltages.

The reason why we call it $g_m$ is because it's mutual transconductance.

So now we're not so sure. What I see is $\frac{1}{g_m}\parens{1 + \frac{1 / g_m}{r_o}}$ when looking into source.

So now we've figured out what our $g_m v_i$ is. Current dividers.

So I wanted to do a couple more examples. For example, source follower (recall, measure output at source). We know $A_v = -G_m R_o$. So what is $R_o$? It's $\frac{1}{g_m} \parallel R_s$. $G_m$ is a little tricky. Draw the small signal model, then do KCL at the output node. Note that since we're grounding $v_s$, $v_{gs} = v_i$, and no current is flowing through the source resistance (or the output resistance, even!). Thus $G_m \equiv -g_m$. What does this mean? We're shoving current out, instead of shoving current in.

So finally $A_v = -G_m R_o = \frac{g_m R_s}{1 + g_m R_s}$. And in particular, in a MOS, it's very common that you'd see the output between two MOSFETs, so you'd get something like $\frac{g_m r_o}{1 + g_m r_o}$. If you're lucky, this looks something like $0.9 - 0.999$.

All right. So here's a couple of good ones to think about. (various practice circuits)

EE 105: Devices & Circuits

Monday, April 2, 2012

Spice files for the lab, etc.

The lab is a high-gain bipolar amplifier with a PMOS load on it. Two ways to do this. When we learn about intrinsic impedances, we see why we put the cascode in the common gate thingy.

$A_v = -G_m R_o$. $G_m = g_{m4}$, and $R_o = r_{o1a} \parallel r_{o3}\parens{1 + g_m(r_{o4} \parallel r_{\pi 3})}$. $r_{o4} \gg r_\pi \implies r_{o4} \parallel r_\pi \approx r_\pi$.

Our output is just $r_{o1a}$. So now we know that our gain is $-g_{m4} r_{o1a}$, or roughly $-\frac{V_A}{V_T} \sim -1000$.

Comments on how low frequencies might be more difficult to measure -- gain too great.

Result on frequency response? I've got $g_m$, $R_o$, and $C_L$. Now I'm taking that from $20k \to 2M$. Other than that, my single-pole system is the same.

How to bias? The answer is almost feedback. In general, when you have an amplifier like this, you have some big high-gain region. If you can figure out a way to put a resistor around this thing and set the input equal to the input at $V_c$, then it self-biases and the thing operates around that point. For MOS, that works great. For bipolar, we've got this huge output impedance, so we need to make our feedback resistor large.

Gain is now $-\frac{R_f}{R_{in}}$, which is made of ratio of passive components, which means you can make a very accurate gain. Very insensitive to PVT variation. Unity-gain frequency stays the same, and it keeps a nice constant gain over a very large bandwidth. Turns out, also causes problems with stability. There might actually be a little bump, and that could turn your amplifier into an oscillator.

Why is the second transistor in there? Not for the 2x gain. Rather, it's to reduce the base-collector voltage. You get something called Miller multiplication.

Intrinsic capacitance. Intrinsic to the thing that makes BJTs work is the PN-junction. Fundamentally, these things have two capacitors that you cannot get away from. For historical reasons, the base-collector junction capacitance is $C_\mu$, and the base-emitter junction capacitance is $C_\pi$. For the MOSFET, intrinsic to the operation of this device is having a gate that induces a charge in a channel. Cannot make a MOSFET without making this capacitor. We've got $C_{ox}$, which is in terms of $F/m^2$. We have charge $Q = WLC_{ox}(V_{GS} - V_{th})$. We don't need any charge in there until we cross this threshold, and above that, it looks linear (ramp).

So in the linear region, you've got that the source and drain are roughly the same voltage. So you end up with $C_{gs} \approx C_{gd} \approx \frac{1}{2} WL C_{ox}$. Intrinsically, changing the gate has negligible effect. $C_{gs} = \frac{2}{3} WL C_{ox}$ and $C_{gd} = 0$ intrinsically: no matter what you do, you cannot get away from this. The $2/3$ is because this is not uniform: it has some shape.

There are also extrinsic capacitances which are overlap. Looking at the field lines, there's an overlap capacitance. Overlap multiplied by width. $C^\prime_{gd} = WC^\prime_{ox}$

EE 105: Devices & Circuits

Wednesday, April 4, 2012

Why we like to use active loads: give us nice flat voltage regions, as opposed to passive loads.

So now we have two currents for two devices. If I tie them together, then the magnitudes have to equal each other. The only place this happens is where the two curves cross.

What else: biasing, gain figure. Miller. Feedback.

Miller capacitance

Suppose I have an amplifier with gain A from $v_i to v_o$. Small signal, so $v_o = Av_i$. If I measure a current across some impedance, we know $v = iZ$. What's going to happen if I plug that same impedance Z between the input and output of the amplifier?

We'll have some $i_i$, and across this Z, I have $v_i$ on one side, and $Av_i$ on the other side. So I get $v_i - Av_i = i_i Z$, so $Z_{in} = \frac{v_i}{i_i} = \frac{Z}{1 - A}$. So that means in particular that if you do something like this (where the magnitude of the gain is approximately a million), what's the input impedance I see? Roughly a millionth of what it would be. A $M\Omega$ resistor therefore starts looking like a single ohm. The idea is that if I raise this up a little bit, a ton more scurrent is flowing through it than it looks.

Also see gains close to 1: impedance gets very large. So what happens if I've got a capacitor across an amplifier? $Z_{in} = \frac{\frac{1}{sC}}{1-A} = \frac{1}{sC(1-A)} = \frac{1}{sC_{miller}}$. Therefore $C_{miller} = (1-A)C$. This is known as Miller multiplication.

So let's look at a bipolar transistor and think about what the input capacitance looks like if I've got an ideal current source load on it. Recall this has two junctions in it ($C_{je,0}, C_{jc,0}$, which you know how to calculate from area and doping like you did on midterm 1), which are very dependent on bias. For the 2N3904, the zero-bias values look like $4\text{pF}, 8\text{pF}$. In the model, under bias, these get called $C_\mu, C_\pi$. $C_\mu = \frac{C_{jc,0}}{\sqrt{1 - \frac{V_{BE}} {V_{0, CE}}}}$, $C_\pi = \frac{C_{j,e,0}}{\sqrt{1 - \frac{V_{BE}}{V_{D, BE}}}}$.

$A_v = -G_m R_o = -\frac{V_A}{V_T} \sim -1000$. So $C_{jn} = C_\pi + (1-A) C_\mu \approx 25 pF + (1 + 1000) 2pF \approx 2 nF$.

Similarly, for the MOS, $C_{gs} \approx 300 fF, C_{gd} \approx 100 fF$. Taking $\lambda = 0.1, V_{D,SAT} = 0.4V$, what do we get? $C_{in} = C_{gs} + (1 - A) C_{gd}$; $A = -g_m r_o = -\frac{2}{\lambda V_{DSAT}} = -50$. So my input capacitance is $300 fF + 5100 fF = 5400 fF$. These capacitances start adding more poles.

(possibility of negative capacitance?)

EE 105: Devices & Circuits

Friday, April 6, 2012

CMOS inverter (how to make inverter versus how to make oscillator), frequency response, feedback, oscillation

Miller gain, with an effective input impedance. In general, some $Z_{eff} = \frac{Z}{1-A}$. Turns voltage amplifier into a transconductance amplifier. The gain of this amplifier is just this $R_F$.

Last time. Talked about $C_{gd}, C_{\mu}$, if you've got an amplifier where you've got high gain, you end up with a lot of input capacitance. Even though this may be much smaller than parasitic capacitor to ground, may still dominate. Often, Miller effect is bad. Some cases where you do like it.

For example, suppose you've got a source follower. As long as it's a good source follower, we can make the effective capacitance much smaller. Also lowers output impedance.

Let's do an example with bipolar (as was the case in the lab). There's a basic amplifier, and let's say we're trying to design something where we've got some kind of a sensor as our source. Has a very high source impedance. Stick into amplifier, shoot for gain on the order of 1000. Must drive 10 pF on the other side.

WIth inverting amplifier, at low frequency, we have a phase shift of 180, pick up phase of 90 from one decade before to one decade after. When measuring, you find a much smaller value. Why? (Miller multiplication of $C_\mu$)

For a gain of 400, $C_{in} = 25p + 800p = 825p$. So $\omega_{p,in} = \frac{1}{R_s C_{in}} \approx 10^3 rad/sec$. Instead of getting this nice Bode plot I thought I was going to get, it dies off much earlier.

Once again, inserting components for reduction of input capacitance by an order of magnitude. Doubled gain is just an added bonus.

What would we have done to deal with this problem before midterm 2? We would have bolted on another stage: follower (buffer). Gain is basically 1, so Miller multiplication makes $C_\mu$ of the follower go away.

CMOS

Suppose I tie the gates of an NMOS and a PMOS together. Consider small signal model. Completely symmetric: once you draw the same small signal model, you can't tell which was which. $G_m = g_{m1} + g_{m2}$. $A_v = -(g_{m1} + g_{m2})(r_{o1} \parallel r_{o2})$. And if I just have some capacitive loading on the output ($C_L$), and I get my classic single-pole picture. This is an inverter. If I put in a low voltage, PMOS pulls voltage high; if I put in a high voltage, NMOS pulls voltage low.

You'll build one of these and measure the Bode plot, and then we'll put three of them in series (with explicit 100pF capacitance on output of each one). We'll find that we've got a gain of something like -1000. Very difficult to bias, so we'll try the same trick that we did in the last lab: we put a feedback resistor on there and put an input and voltage source, and you'll find that you get a nice, easy-to-bias, reliable-gain amplifier. And gain is $-\frac{R_F}{R_i}$. Amplifier. It works nicely.

And then you'll show this to one of your friends in EE141 or CS150, and in those classes, they'll note that you're working on ring oscillators in EE105. it's well-known that if you daisy-chain three of them, you get a 3-stage ring oscillator. So how can this be an oscillator and an amplifier? Very subtle.

The challenge is to make sure that you understand the math that governs which way this goes.

So: what's going on there? If we look at the Bode plot for the 3-stage amplifier, assuming they all have the same load, three of them in series, gain of something like $A_0^3 = 10^4$, right at that frequency, my gain drops off very quickly: $\frac{1}{\omega^3}$, gain of -3 on a log-log plot. It's a third-degree pole. Phase-wise, what happens? Tripled slope in the region, so goes from 0 to 270 in that time.

At 10x the pole frequency, we still have a magnitude of gain of $10$. Important: we also know that at some frequency less than that, our phase crosses 360. Think of this as a black box: if I put in a sine wave on one side, I'll get a sine wave on the other side. We know that at that frequency, we get exactly zero phase shift, and it comes out with some amplitude more than 10x what we input.

If ever $\abs{H(j\omega_{360})} > 1$ (for any value of $\omega_{360}$), then it will oscillate. Otherwise, it will be an amplifier. How to fix? I have resistors, capacitors; if I can push one of these poles further left so that I can get a gain less than 1, then the sine wave goes in and gets a little smaller, so the system is stable. And then you can use this as an amplifier.

EE 105: Devices & Circuits

Monday, April 9, 2012

CMOS amps. Ways to draw PMOS, NMOS. (analog way: PMOS on top, NMOS on bottom (source = bulk); LTSpice puts the two together. Way to remember: always PN-junction). Always looks like a diode. If you're a digital person, you draw transistors with a NOT (bubble) on the gate of the PMOS. LTSpice's way is the most faithful: analog way could be wrong, since it really depends on which way the current's flowing.

So given those devices, on your homework I ask you to draw explicitly (using the bubbles). You get an I/O relationship that has two flat regions on it. When within threshold region, it's just plain off; in between, I get two quadratics, and in between, I get a high-gain region. If we draw five different regions of operation of this thing, if we look at the P and the N current in each one:

When $0 < V_{in} < V_{th,N}$, the PMOS device has almost all the $V_{DD}$ across it. It's going to go into saturation pretty close to the top rail. Very little saturation there; almost all triode region. N current is just identically zero.

In the next region, $V_{th,N} < V_{in} < ?$, N is in saturation now, and P is still in triode.

Then, at some point, both devices are in saturation, intersection point in there, and that is our high gain region. Not perfectly straight, but pretty darn straight. Both curves moving as $g_m v_{in}$.

Next, the NMOS device goes up to even higher current, PMOS goes to lower current, NMOS in triode, PMOS saturated.

Finally, PMOS is just off, NMOS is in triode.

For homework, must calculate what these transition points are. Pretty straightforward to calculate: for ALD1106 and ALD1107, $\mu_n C_{ox} \approx 40 \mu A/V^2, \mu_p C_{ox} \approx 16 \mu A/V^2$. So if you want to find $V_{in}$ s.t. $V_{out} = V_{DD}/2 = 2.5V$, the two currents have to be equal to each other, so $I_{DN} = I_{DP}$, so $\mu_n C_{ox}(V_{in} - V_{th})^2 = \mu_p C_{ox}(V_{DD} - V_{in} - \abs{V_{th,p}})$. You can solve, and you get something around $2V$. That's going to tell you how to get to that point.

So how do you figure out what the input and output swing is where both devices stay in saturation? Pretty straightforward with the picture: you know it goes into saturation at $V_{in} - V_{th}$ for the NMOS, and similarly, for the PMOS device, this is going to be $V_{DD} - \abs{V_{th}}$. These tell you exactly what your output swing is, so once you know this, you can calculate how high/low it can go until a transistor drops out of saturation; divide by gain, and you have your input.

Managed to get Excel to plot these things.

A, H: open loop gain (once through main amp). Then, feedback factor K: will often see as F. If you're a control theorist, you'll draw some sort of summing junction. If you go around this loop once (break or open loop) and look at the gain once through the amplifier and feedback, then that (AK) is called the loop gain.

So what is the overall gain of a system with feedback? For the gain (closed-loop gain) we get $y = Ae$, $e = x - Ky$. When we combine these, we get $y = Ax - AKy$, or $\frac{y}{x} = \frac{A}{1 + AK} = \frac{A}{AK \parens{1 + \frac{1}{AK}}} = \frac{1}{K}\frac{1}{1 + \frac{1}{AK}} \approx \frac{1}{K}\parens{1 - \frac{1}{AK}}$. So that's good news. We get to take our amplifier, which we're building out of transistors.

Closest thing that you can make (that control theorists like to see) is an opamp -- darn good approximation. If you take 140, you take what you've learned in 105 and learn to design opamps. But you already know some circuits that look pretty opamp-like.

In datasheets: $A_v(V_+ - V_- + V_{offset})$. Important thing that'll show up early.

So: in your lab, you built a bunch of CMOS inverters; calculate input capacitance. Couple of polarized capacitors. Pretty subtle. Explicitly place 100pF so we don't have to worry about the subtleties. So let's say the gain of each stage is 10, that'll make a nice ring oscillator. So what is the open-loop gain, feedback factor, loop gain of this? Feedback gain is 1, open-loop gain is -1000. So loop gain is -1000. People tend to drop minus signs.

Proper place to break feedback loop: right in front of each amplifier (since we explicitly drew load capacitors).

Response of closed-loop gain to frequency.

Very quickly: single-pole system. $A = \frac{A_0}{1 + \frac{s}{\omega_p}}$, so $\frac{V}{X} = \frac{A}{1 + AK} = \frac{A_0}{1 + \frac{s}{\omega_p} + A_0K}$. Put this back into original form, etc. Pole moves. With feedback, pole moved to higher frequency.

EE 105: Devices & Circuits

Wednesday, April 11, 2012

Feedback:

• Math
• circuits poles move
• stability and amplitudes

Nice mathematical abstraction of feedback with an amplifier with open-loop gain given by A, and a feedback factor K, and loop gain AK. If we close the loop, then we know that we get a closed-loop gain of $\frac{A}{1+AK}$. For $\abs{AK} \gg 1$, this is approximately $\frac{1}{K}\parens{1 - \frac{1}{AK}}$.

Turns out same analysis we do for amplifiers is the same we need to do for oscillators. Circuits don't quite match this.

So let's do a little math, and example where I mess up and am too busy thinking about the beautiful math. Single-pole amplifier with $A(s) = \frac{A_o}{1 + s/\omega_{p0}}$. CLG is $\frac{A}{1 + AK} = \frac{A_0}{1 + A_0 K + s/\omega_{p0}} = \frac{A_0}{1 + A_0 K} \frac{1}{1 + s / \omega_{p,cl}}$. DC gain is the same, and then we've got some frequency-dependent component. So we have $\omega_{p,cl} = (1 + A_0 K)\omega_{p0}$. Pole has moved: depends on how much feedback we provide. In particular, if the amount of feedback I put into this thing is 0, then I get the right answer.

So if we look at (the magnitude of) the open-loop transfer function, we have this $\omega_{u0} = A_0 \omega_{p0}$. And now, as I add feedback, this should not move.

Mathematically, as we change the loop, unity gain does not change.

We know from Miller that we can write the equivalent linear circuit with input and output loads.

Calculate $G_m, R_o$ the usual way (small signal model). Math ran into real world: taking last lab into account, unity gain frequency moved. Mistaken assumption was that the resistor impedance stays small at all frequencies. Impedance goes up with frequency, and all of a sudden, $r_\pi$ is not negligible any more. Initially 7k, and I'm driving a 7k with a 100k resistor. cut effective $G_m$.

Now let's look at your next lab, where we'll build a ring oscillator. Feeding back to the input and trying to turn this thing into an amplifier. Put a 100k resistor in the loop, each stage has an explicit 100pF capacitance on the input. Start with $R_{fb} = 0$, put load on this capacitance. Then we can figure stuff out from $V_{in}$ to $V_{fb}$.

We're going to get three frequencies out of these. Initially they're identical, and we're going to get an open-loop gain $A = \parens{\frac{G_m R_o}{1 + s/\omega_{p1}}}^3$. All the poles line up at the same place.

Gets bigger each loop until saturation. Mathematical criteria for stability: $\abs{H(j\omega)} < 1, \angle H(j\omega) = 0$. Phase margin: $\angle H(j\omega)$. If that's 360, we're doomed. $360 - \angle H(j\omega)$ tells you how close to instability you are. Then there's gain margin, which is $H(j\omega_{360})/1$. People get very nervous when your phase margin is less than $45^\circ$. So this thing is going to oscillate, and that's what you found. (when phase margin dips below 0, you oscillate)

So how to keep this an oscillator? (generally used for clocks; stick through handful of inverters afterward and measure that final output) Current source: have some reference current with resistor up to rail (setting ref. voltage), and now you have some transistors whose drains are all tied together and have particular values of $W/L$. We control the bias voltage with more MOSFETs or whatever. Lots of advice to take 142 and stuff.

system absolutely unstable, etc. How do we guarantee small gain? Get rid of poles or stuff. Single inverter will not oscillate. Not enough poles to get you to 360.

EE 105: Devices & Circuits

Monday, April 16, 2012

Lab,

slew rate: trying to drive an $8\Omega$ speaker. Probably want to drive this with a DC-block capacitor. In systems like this, you generally want AC-coupling so you don't have to worry how things are inserted. You also want this to work for audio. C should be blocking. 20Hz. For lab, only have to go down to 1kHz. May use 10 or 100 $\mu F$. Why is this bad? Output stage is a cascode (sort of) with capacitive load.

If you've got a sine wave on this thing at some DC offset of 1-5V, you know that what you'd like to see is the output tracking the input with a diode drop. In fact, that works fine for low amplitudes at low frequencies.

But at high amplitudes / frequency, what you see is this thing called the slew rate (looks like capacitor action). What's happening? Current flowing across this capacitor is equal to $C\omega V_0 \cos(\omega t)$. The magnitude of the current is simply $\omega C V_0$. If f is 160 Hz and C is 1 $\mu F$, then $\omega = 10^3$, $\omega C = 10^{-3}$, so you're going to get 1 mA of current that you need at the peaks of these sine waves. But if you take this up to $f = 1 kHz, C = 10 \mu F$, you'll need $60 mA$. etc.

What you see on the scope is that output tracks just fine on the way up. No problems with emitter follower transistor. On its way up, if this voltage is lagging, it only takes 60 mV to give 10x the current. More than happy to source extra current. But once you hit the peak, current coming down, and you need to discharge capacitor with that current. And that's why with this setup you end up with a slew rate $\deriv{V}{t}\Big|_{max} = \frac{I_{bias}}{C}$.

Bunch of tricks people have come up with over the years. Problem here is that we have a hard time pulling down. So what if we make a CE or CC with a PNP transistor? On the negative-going transitions, this thing will happily pull much more current. But it'll have problems with the positive-going.

So combine the two, make an NPN follower to bring this voltage up and a PNP follower to bring this voltage down. Tie these together, and this is our $V_{in}$. Challenge: if you look at $I_{out}$ vs. $V_{in} - V_{out}$, you know that we have a dead zone of two diode drops, i.e. when these things turn on/off. SO what do we want to do to fix this?

Ideally you put a battery in there that biases these two bases far enough apart that they're always on. How do you do that? Turns out, lots of other ways to do a voltage source.

Simplest: just put two diodes in there. Trying to compensate for the diode drops. Want some current flowing through, so just put a resistor before the diodes. Conceptually, this will do. Could put input anywhere, really, and the output really would track the input.

This is one of the problems with the lab: driving low impedance with output. Driving high-impedance source. If this were actual electret, this would have huge impedance. But inside this can, there's already a JFET to lower the impedance.

Two issues: slew rate; impedance is basically 8$\Omega$. Somehow you've got to get from k$\Omega$s to $\Omega$s. Put in a follower. Key: understand what you're adding and why. Perfectly fine as well as you get reasonable performance. Hand calculations match spice calculations match measurements.

One thing you might put in there is another CC, which magnifies impedance by that $1+\beta$ factor. Darlington pair.

As always, at the input to the amplifier, we have a magical subtracter box for now. We'll eventually show how to make this with transistors (differential pairs).

Unity-gain feedback can be used to manipulate what an output impedance looks like. Should not be a surprise: we already knew this because we knew that with that same configuration where we had some load capacitance, we got a system with an open-loop gain at 0 and a pole at $\frac{1}{R_o C_L}$. When we wrap feedback around it, this moves to $\omega_{p,cl} = (1 + A_0 K)\omega_{p,ol}$.

So that's a very good thing: for a voltage amplifier, feedback lowers your output impedance, potentially dramatically.

So how about the input impedance? This is a little trickier in that it's doing some handwaving regarding how the feedback actually happens.

Want to get high gain because you can always trade it for good things in circuits: low stable gain, etc. The only caveat is that this is a real amplifier, so there's only so much swing you can get.

Magical subtracter box! We'd like $V_D = V_+ - V_-$. If they're both going up and down together, we'd like nothing to happen.

Works because of linearization around our operating point.

Take current and turn into voltage by putting in resistors. And now you've got a differential voltage across here.

Similar to common emitter: how is this different? the change on either side will set the other rail. Another way to look at this: we're rejecting the average.

EE 105: Devices & Circuits

Wednesday, April 18, 2012

Output impedance, slew rate. Feedbacks, op amps, digital.

From lab: trying to derive load with resistive component, passive component. Bunch of issues here: R is small (8 ohm), output resistance much smaller than load resistance means burn current.

Current limits: $I = \omega C V_{swing}$. Pick C such that impedance small compared to R.

cleverness. Cleverness in short supply. Nice to have ability to just throw op amps at problems instead of cleverness.

What if we had some way to measure output voltage and compare to input voltage and use to affect bias voltage on transistor? Would be nice if we could somehow measure output voltage relative to input, gain it up (positive) and apply to $V_{BE1}$.

Turns out: negative feedback. Doesn't fit nicely into picture we like of summing junction, etc, but it turns out most circuit feedback doesn't (at transistor level). If you take 140, you learn what true pain is. Until you start using op amps. Which is an abstraction.

Something that lets me drive with small current in small-signal model.

Still have problem slewing north, but slewing south is fine. Before we had the opposite problem.

Turns out when you're slewing, linearity of drive not good; going to sound distorted.

Op amps!

Last time we learned about differential amplifiers. Now we'll put that to use. There's no precise definition of what an op amp is. But roughly, there are three parts: differential amplifier (where the goal is to separate the common mode from the difference of the signal), gain stage, and maybe an output stage. Sometimes you see amplfiiers drawn as trapezoids, which just means that it's missing the output stage: could be very large output impedance.

EE 105: Devices & Circuits

Monday, April 23, 2012

Operational amps; oscillated at 800Hz in speaker-to-microphone feedback. Ideal op amp: is differential amplifier with gain. Infinite input impedance, no output impedance, etc. Doesn't care where output goes; no current limits. All things that real op amps don't share with ideal op amps. We're not going to get into the details of designing op amps, but it's a nice circuit: uses things you've learned all semester long. Relatively easy to make and buy.

If we look at the simplest op amp, you have to have a differential pair, and you have to have some sort of current flowing through that differential pair. We know from last lecture if the common mode voltage is the same, as they move up and down, the emitter moves up and down. Depending on the resistor, your current stays relatively constant. So this gives us some common-mode rejection. Slight changes of this (if you draw the SSM) -- virtual ground. You get a differential current (one side is +, other is -). Keeping current constant. Simplest way to turn this into a voltage is to make it single-sided, and that is an op amp.

So how do we find the gain? We have to find the operating point. For this particular circuit, we need to know what the inputs are at. Our operating point, therefore, is one $V_{BE}$ drop below the DC bias at 0. Tail resistance. Named by people doing tubes. Tail current: $\frac{V_{EE} - V_{BE} - V_{cm}}{R_{tail}}$. So $g_{m1}$ is $\frac{I_c}{V_T}$. $R_{out} \approx R_c$, and $G_m$ ends up being $\frac{g_{m1}}{2}$.

Gain ends up being around 50.

So this thing actually does work as an op amp. If I wanted to make a follower or unity-gain buffer out of it,

Stability? Depends on gain at $\omega_{360}$. If there is no $\omega_{360}$, then we don't have to worry about this. This particular case is a single-pole system (to a good approximation).

Traditional thing to do in tube amplifiers: -500V (really big volts).

This ends up getting an output impedance of about 200 ohms, which is not ideal, but still better than 10k.

So let's add a second stage.

Reduces gain, but eh. Usually see follower.

Small signal does poor job approximating: well out of region of approximation.

Let's suppose we have an amplifier, and we put it in feedback. Assume gain is 1000, output resistance is just $R_c = 1k$. This stuff here is all about creating K, the feedback factor. So open-loop, this is $K=0$. AK is about 10, so closed-loop gain is about 90, output resistance is about 100. If K is 0.1, closed-loop gain is about 10, output resistance is about 1.

Unity-gain frequency, closed-loop gain is about 1, output resistance is about 1.

$A_{CL} \approx \frac{1}{K}$, $R_o \approx \frac{R_{out}{1 + A_0 K}$.

So this can drive a speaker pretty well. So what does it look like when it's driving it? Fine for small signals. If you think about that output stage, drawing just part of this, with no bias on the input, and I've got my feedback, then it turns out the way this thing is set up is such that I get an output bias of a couple of volts. Pretty close to zero. With no input, I'm going to have something like 6 mA flowing.

Talk about slew. Can slew fast in positive direction, but in negative direction, stuck with bias current through $R_C$.

That's why the next step is to take that amplifier that we have and have it drive two emitter followers.

EE 105: Devices & Circuits

Wednesday, April 25, 2012

Next week: lecture is just going to be review, examples, Q&A. If we run out of Q's or A's, we'll quit. Comprehensive final. Stuff certainly on capacitance versus applied voltage.

Will be a homework next week to throw in all the things we haven't had homework on.

Not an op amp class, so all we need to know is that they're made of common emitters and common collectors and things like that. Might do some good to see that people design real products using these tools that we now know.

Some stuff quite subtle and not covered at all.

3T, 5T op-amp. On some problems, we lost half of our transconductance. Lose gain $R_1 \parallel r_{\pi3}$ (not a big deal yet, but will be an issue when we add a current source) -- costs us a factor of 2 for now. Bias currents depend on common mode (CM) input and output voltage and supply.

On the output stage, there's a very nasty deadband on the output, and there's no over current protection on the output. On the LM324, they made the output stage even worse: got current source -- NPN common emitter stuck into PNP and also an NPN with a Darlington on the NPN. The problem over here is that if the output is at 0, we've got a range of three diode drops that does nothing. Quad op amp. Power, ground, plus, minus for 4 op amps. Nine cents in volume.

One interesting thing on this guy: they've got a current source feeding the gate of the Darlington pair (100 uA), so they've got $\beta^2$. If my input goes low, then all the current is going to flow through the Darlington pair and get multiplied by $\beta^2$. Huge amount of current dropping across big voltage. (potentially at 30V). Literally can destroy transistors.

So what do you do to stop that? Very common they'll put in a sense resistor, so now you have a voltage proportional to the current flowing through the output, and so if the current gets too high, I steal some of the output current.

Thermal runaway: $I_c \propto I_s(\tau)$, more or less.

$\beta$-helper: try to minimize current being stolen from $I_{ref}$. Going to have to have $I_B$ flowing into the node. Therefore current flowing that way is $\frac{NI_B}{\beta}$, which is basically nothing.

Can turn any one of these and turn into a source by just mirroring it: diode connect a transistor on the other end so it has a current of $I_{ref}$, and I just do the same thing.

MOS case. Now we don't need a $\beta$-helper because we don't have a current. Multiple copies, mostly same thing. Except now you change the $\frac{W}{L}$ (as opposed to area). Don't want to change $L$, since that's coupled to nonlinear device behavior.

We normally lose half of our $g_m$

What I really want is a current mirror. If I put in a PNP current mirror and mirror one side's current over to the other side, now I recover my original current, and this thing self-biases. Standard 2-stage op amp.

Got a differential pair that gives you a current proportional to difference between two signals, stick that into an active load current mirror, and now this thing has very high gain (as long as the next stage has high gain). Stick that into a common-emitter amplifier to get another gain stage, and maybe you put some gain after it. These are driven by current sources (which we know how to make -- diode-connected transistor and a resistor), and that is your classic two-stage op amp.

Works with MOS as well: differential input stage, current mirror as a load, and common source gain stage. Both of these want current sources as loads.

The nice thing about both of these is that you just wire them up and they work. Might not work well (point of 140).

Miller effect helps. Pole-splitting, beautiful thing. Outside of the scope of this class. So that's it for op amps.

Something went wrong with that request. Please try again.