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+CS 150 - Digital Design
+=======================
+August 23, 2012
+-----------------
+
+30 lab stations. Initially, individual, but later will partner up. Can
+admit up to 60 people -- limit. Waitlist + enrolled is a little over
+that. Lab lecture that many people miss: Friday 2-3. Specific lab sections
+(that you're in). Go to the assigned section at least for the first several
+weeks.
+
+This is a lab-intensive course. You will get to know 125 Cory very
+well. Food and drink on round tables only. Very reasonable policy.
+
+As mentioned: first few are individual labs, after that you'll pair up for
+the projects. The right strategy is to work really hard on the first few
+labs so you look good and get a good partner.
+
+The book is Harris & Harris, Computer Design & Architecture.
+
+Reading: (skim chapter 1, read section 5.6.2 on FPGAs) -- H&H, start to
+look at Ch. 5 of the Virtex User's Guide.
+
+H&H Ch. 2 is on combinational circuits. Assuming you took 61C, not doing
+proofs of equivalence, etc.
+
+Ch. 3 is sequential logic. Combinational is history-agnostic; sequential
+allows us to store state (dynamical time-variant system).
+
+With memory and a NAND gate, you can make everything.
+
+Chapter 4 is HDLs. Probably good to flip through for now. We're going to
+use Verilog this semester. Book gives comparisons between Verilog and VHDL.
+
+First lab next week, you will be writing simple Verilog code to implement
+simple boolean functions. 5 is building blocks like ALUs. 6 is
+architecture. 7, microarchitecture: why does it work, and how do you make
+pipelined processors. May find there's actually code useful to final
+project. Chapter 8 is on memory.
+
+Would suggest that you read the book sooner rather than later. Can sit down
+in first couple of weeks and read entire thing through.
+
+Lecture notes: will be using the whiteboard. If you want lecture notes, go
+to the web. Tons of resources out there. If there's something particular
+about the thing Kris says, use *Piazza*. Probably used several times by
+now, so not an issue.
+
+Cheating vs. collaboration: link on website that points to Kris's version
+of a cheating policy.
+
+Grading! There will be homeworks, and there will probably be homework
+quizzes (a handful, so probably 10 + 5%). There will be a midterm at least
+(possibly two), so that's like 15%. Labs and project are like 10 and 30%,
+and the final is 30%.
+
+Couple things to note: lab is very important, because this is a lab
+course. If you take the final and the midterm and the quizzes into account,
+that's 50% of your grade.
+
+Lab lecture in this room (306 Soda, F 2-3p). Will probably have five weeks
+of lab lecture. Section's 3-4. Starting tomorrow.
+
+Office hours to be posted -- as soon as website is up. Hopefully by
+tomorrow morning.
+
+King Silicon
+------------
+
+FINFETs (from Berkeley, in use by Intel). Waht can you do with 22nm tech?
+Logic? You get something more than $10^6$ digital gates per $mm^2$. SRAM,
+you get something like $10 Mb/mm^2$, Flash and DRAM, you get something like
+$10 MB/mm^2$. You want to put your MIPS processor on there, or a 32-bit ARM
+Cortex? A small but efficient machine? On the order of $10^5$ gates, so
+about $0.1 mm^2$. Don't need a whole lot of RAM and flash for your
+program. Maybe a megabit of RAM, a megabyte of flash, and that adds up to
+$0.3 mm^2$. Even taking into account cost of packaging and testing, you're
+making a chip for a few pennies.
+
+Think of the cell phone: processor surrounded by a whole bunch of
+peripherals. I/O devices (speakers, screens, LEDs, buzzer; microphone,
+keypad, buttons, N-megapixel camera, 3-axis accelerometer, 3-axis
+gyroscope, 3-axis magnetometer, touchscreen, etc), networking devices
+(cell, Wifi, bluetooth, etc), Cool thing here is that it means that you can
+get all of these sensors in a little chip package. Something:
+microprocessor in general will not want direct interface. A whole cloud of
+"glue logic" that frees the processor from having to deal with
+idiosyncrasies of these things. Lots of different interfaces that you have
+to deal with. Another way of looking at this: microprocessor at the core,
+glue logic around the outside of that, that is talking to the analog
+circuitry, which talks to the actual transducers (something has to do
+conversions between different energy domains).
+
+another way of looking at this is that you have this narrow waist of
+microprocessors, which connects all of this stuff. the real reason we do
+this is to get up to software. one goal of this class is to make you
+understand the tradeoffs between hw and sw. hw is faster, lower power,
+cheaper, more accurate (several axes: timing, sw is more flexible. if we
+knew everything people wanted to do, we'd put it in hw. everything is
+better in hw, except when you put it in hw, it's fixed. in general, you've
+got a bunch more people working in sw than in hw. this class is nice in
+that it connects these two worlds.
+
+if you can cross that bridge and understand how to understand a software
+problem in hardware design stages, or solve a hw bug through software, you
+can be the magician.
+
+what we're going to do this semester in the project is similar to previous
+projects in that we'll have a mips processor. looks like a 3-stage pipeline
+design, and we'll have you do a bunch of hardware interfaces (going across
+the hw/sw boundary, not into analog obviously). we have, for example,
+video: we might do audio out. we'll do a keyboard for sure and a
+timer. there's some things in here; all of this will end up being
+memory-mapped io so that software on the processor can get to it, and it'll
+also have interrupts (exceptions). not that many people who understand
+interrupts and can design that interface well so that sw people are happy
+with it.
+
+You will *not* be wiring up chips on breadboards (or protoboards), the way
+we used to in this class. You'll be writing in Verilog. You'll basically be
+using a text editor to write Verilog, which is a HDL. There's a couple of
+forms: one is a structural one, where you actually specify the nodes. First
+lab you'll do that, but afterwards, you'll be working at a behavioral
+level. You'll let the synthesis engine figure out how to take that
+high-level description and turn it into the right stuff in the target
+technology. Has to do a mapping function, and eventually a place & route.
+
+Lot of logic. Whole bunch of underlying techs you might map to, and in the
+end, you might go to an IC where there's some cell library that the
+particular foundry gives you. Very different than if you're mapping to a
+FPGA, which is what you'll be doing this semester. Job of the synthesis
+tool to turn text into right set of circuits, and that goes into simulation
+engine(s), and it lets you go around one of these loops in minutes for
+small designs, hours for larger designs, and iterate on your design and
+make sure it's right.
+
+Some of you have used LTSpice and are used to using drawing to get a
+schematic, and that's another way to get into this kind of system as well,
+but that's structural. A big part of this course, unfortunately, is
+learning and understanding how these tools work: how I go through the
+simulation and synthesis process.
+
+The better you get at navigating the software, the better a digital
+designer you'll be. Painful truth of it all. Reality is that this is
+exactly the way it works in industry. Nature of the IC CAD world. Something
+like a $10B/yr industry. Whole lot better than plugging into a board.
+
+FPGA board: fast and cheap upfront, but expensive per part. Other part of
+spectrum is to go with an IC or application-specific integrated circuit
+(ASIC), which is slow and costly upfront, but cheap per unit. Something in
+between: use an FPGA + commercial off-the-shelf chips, and a custom
+PCB. Still expensive per part (less so), but it's pretty fast.
+
+FPGA? Field-programmable gate array. The core of an FPGA is the
+configurable logic block. The whole idea behind a CLB is that you have the
+dataplane, where you have a bunch of digital inputs to the box, and some
+number of outputs in the data plane, and there's a separate control plane
+(configuration) that's often loaded from a ROM or flash chip externally
+when the chip boots up. Depending on what you put in, it can look
+different. Fast, since it's implemented at the HW level.
+
+If you take a bunch of CLBs and put them in an array, and you put a bunch
+of wiring through that array, that is configurable wiring.
+
+If we made this chip and went through the process, when we turned it into a
+single chip, we'd take everything we put into this, it'd be less than a
+square millimeter of 22nm silicon.
+
+Talk about how FPGAs make it easy to connect external devices to a
+microprocessor.
+
+Course material: we can start from systems perspective: systems are
+composed of datapath and control (FSM), or we can start from the very
+bottom: transistors compose gates, which get turned into registers and
+combinational logic, which gets turned into state and next state logic,
+which make up the control. Also, storage and math/ALU (from registers and
+combinational logic) makes up the datapath.
+
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+CS 150 Lab Lecture 0
+====================
+August 24, 2012
+---------------
+
+Note: please make sure to finish labs 2 and 4, since those will be going
+into your final project. Labs will run first 6 weeks, after which we will
+be starting the final project.
+
+Large design checkpoint, group sizes < 3.
+
+stuff.
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+CS 150: Digital Design & Computer Architecture
+===============================================
+August 28, 2012
+---------------
+
+Admin
+-----
+
+Lab: cardkey, working on that. Not a problem yet. Labs: T 5:30-8:30, W 5-8,
+θ 5-8. Discussion section: looking for a room. Office hours online. &theta;
+11-12, F 10:30-11:30. In 512 Cory.
+
+Reading: Ch. 4 (HDL). This week: through 4.3 (section that talks about
+structural Verilog). For next week: the rest. It is Verilog only; we're not
+going to need VHDL. If you get an interview question in VHDL, answer it in
+Verilog.
+
+Taxonomy
+--------
+you've got HDLs, and there are really two flavors: VHDL and
+Verilog. Inside of Verilog you've got structural (from gates) and
+behavioral (say output is equal to a & b).
+
+Abstraction
+-----------
+Real signals are continuous in time and magnitude. Before you do anything
+with signals, these days, you'll discretize in time and magnitude --
+generally close enough to continuous for practical purposes. If it's a
+serial line, there's some dividing line in the middle, and the HW has to
+make a decision. Regular time interval called CLK; two values of
+magnitude is called binary.
+
+Hierarchy
+---------
+Compose bigger blocks from smaller blocks. Principle of reuse -- modularity
+based on abstraction is how we get things done (Liskov). Reuse tested
+modules. Very important design habit to get into. Both partners work on and
+define interface specification. Layering. Expose inputs and outputs and
+behavior. Define spec, then divide labor.
+
+One partner implements module, one partner implements test harness.
+
+Regularity: because transistors are cheap, and design time is expensive,
+sometimes you build smaller (simpler) blocks out of tested bigger
+blocks. Key pieces of what we want to do with our digital abstraction.
+
+Abstraction is not reality. Simulation: Intel FDIV bug in the original
+Pentium. Voltage sag because of relatively high wire resistance.
+
+Lab 0: our abstraction is structural Verilog. There are tons of online
+tutorials on Verilog; Ch 4.3 in H\&H is a good reference on that; your TAs
+are a good reference. Pister's not a good reference on the syntax. You're
+allowed to drop a small number of different components on your circuit
+board and wire them up. If you want to make some circuit, you can.
+
+Powers of two!
+
+FDIV bug: from EE dept at UCLA: outraged that they had not done exhaustive
+testing.
+
+note: $1 yr \approx \pi \cdot 10^7 s$. With this approximation, $\pi$ and
+$2$ are about the same. Combinatorial problem.
+
+Combinational logic vs. sequential logic. Combinational logic: outputs are
+a function of current inputs, potentially after some delay (memoryless),
+versus sequential, where output can be a function of previous inputs.
+
+Combinational circuits have no loops (no feedback), whereas circuits with
+memory have feedback. Classic: SR latch (2 xor gates hooked to each other).
+
+So let's look at the high-level top-down big picture that we drew before:
+system design comes from a combination of datapath and control (FSM). On
+the midterm (or every midterm Pister's given for this course), there's
+going to be a problem about SRAM, and you're going to have to design a
+simple system with that SRAM.
+
+e.g. Given 64k x 16 SRAM design, design a HW solution to find the min and
+max two's complement numbers in that SRAM.
+
+Things you need to know about transistors for this class: you already know
+them.
+
+Wired OR (could be a wired AND, depending on how you look at it). Open
+drain or open collector: this sort of thing.
+
+Zero static power: CMOS inverter. Not longer true; power going down, but
+number goes up. Leakage current ends up being on the order of an amp. Also,
+increasingly, gates leak.
+
+switching current: charging and discharging capacitors. $\alpha C V%2 f$
+
+crowbar current: $I_{CC}$, While voltage is swinging from min to max or
+vice versa, this current exists. All of these things come together to limit
+performance of microprocessor.
+
+a minterm is a product containing every input variable or its complement,
+and a maxterm is a sum containing every input variable or its complement.
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+CS 150: Digital Design & Computer Architecture
+===============================================
+August 30, 2012
+---------------
+
+Introduction
+------------
+Finite state machines, namely in Verilog. If we have time, canonical forms
+and more going from transistor to inverter to flip-flop.
+
+So. The idea with lab1 is that you're going to be making a digital
+lock. The real idea is that you're going to be learning behavioral Verilog.
+
+Finite State Machines
+---------------------
+
+Finite state machines are sequential circuits (as opposed to combinational
+circuits), so they may depend on previous inputs. What we're interested in
+are synchronous (clocked) sequential circuits. In a synchronous circuit,
+the additional restriction is that you only care about in/out values on the
+(almost always) positive-going edge of the clock.
+
+Drawing with a caret on it refers to a circuit sensitive on a positive
+clock edge. A bubble corresponds to the negative edge.
+
+If we have a clock, some input D, and output Q, we have our standard
+positive edge-triggered D flip-flop. The way we draw an unknown value, we
+draw both values.
+
+A register is one or more D flip-flops with a shared clock.
+
+Blocking vs. unblocking assignments.
+
+So. We have three parts to a Moore machine. State, Output logic, and next
+state. Mealy machine is not very different.
+
+Canonical forms
+---------------
+
+Minterms and maxterms. Truth table is the most obvious way of writing down
+a canonical form. And then there's minterm expansion and maxterm
+expansion. Both are popular and useful for different reasons. A minterm is
+a product term containing every input variable, while a maxterm is a sum
+term containing every input variable. Consider min term as a way of
+specifying the ones in the truth table. Construction looks like disjunctive
+normal form.
+
+Maxterms are just the opposite: you're trying to knock out rows of the
+truth table. If you've got some function that's mostly ones, you have to
+write a bunch of minterms to get it, as opposed to a handful of
+maxterms. Construction looks like conjunctive normal form.
+
+Both maxterm and minterm are unique.
+
+de Morgan's law: "bubble-pushing".
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