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#ifndef __pform_H
#define __pform_H
* Copyright (c) 1998-1999 Stephen Williams (
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
#if !defined(WINNT)
#ident "$Id: pform.h,v 1.9 1999/04/19 01:59:37 steve Exp $"
# include "netlist.h"
# include "Module.h"
# include "Statement.h"
# include "PGate.h"
# include "PExpr.h"
# include "PUdp.h"
# include "PWire.h"
# include "verinum.h"
# include <iostream.h>
# include <string>
# include <list>
# include <vector>
# include <stdio.h>
* These classes implement the parsed form (P-form for short) of the
* original verilog source. the parser generates the pform for the
* convenience of later processing steps.
* Wire objects represent the named wires (of various flavor) declared
* in the source.
* Gate objects are the functional modules that are connected together
* by wires.
* Wires and gates, connected by joints, represent a netlist. The
* netlist is therefore a representation of the desired circuit.
class PGate;
class PExpr;
* These type are lexical types -- that is, types that are used as
* lexical values to decorate the parse tree during parsing. They are
* not in any way preserved once parsing is done.
struct lgate {
: parms(0), lineno(0)
{ range[0] = 0;
range[1] = 0;
string name;
string file;
unsigned lineno;
* The parser uses startmodule and endmodule together to build up a
* module as it parses it. The startmodule tells the pform code that a
* module has been noticed in the source file and the following events
* are to apply to the scope of that module. The endmodule causes the
* pform to close up and finish the named module.
extern void pform_startmodule(const string&, list<PWire*>*ports);
extern void pform_endmodule(const string&);
extern void pform_make_udp(string*name, list<string>*parms,
list<PWire*>*decl, list<string>*table,
* The makewire functions announce to the pform code new wires. These
* go into a module that is currently opened.
extern void pform_makewire(const string&name, NetNet::Type type = NetNet::IMPLICIT);
extern void pform_makewire(const list<string>*names, NetNet::Type type);
extern void pform_set_port_type(list<string>*names, NetNet::PortType);
extern void pform_set_net_range(list<string>*names, list<PExpr*>*);
extern void pform_set_reg_idx(const string&name, PExpr*l, PExpr*r);
extern void pform_set_attrib(const string&name, const string&key,
const string&value);
extern void pform_set_type_attrib(const string&name, const string&key,
const string&value);
extern void pform_set_parameter(const string&name, PExpr*expr);
extern PProcess* pform_make_behavior(PProcess::Type, Statement*);
extern Statement* pform_make_block(PBlock::BL_TYPE, list<Statement*>*);
extern Statement* pform_make_assignment(string*t, PExpr*e);
extern Statement* pform_make_calltask(string*t, list<PExpr*>* =0);
extern list<PWire*>* pform_make_udp_input_ports(list<string>*);
* The makegate function creates a new gate (which need not have a
* name) and connects it to the specified wires.
extern void pform_makegates(PGBuiltin::Type type,
extern void pform_make_modgates(const string&type, list<lgate>*gates);
/* Make a continuous assignment node, with optional bit- or part- select. */
extern void pform_make_pgassign(const string&lval, PExpr*rval);
extern void pform_make_pgassign(const string&lval, PExpr*sel, PExpr*rval);
* These are functions that the outside-the-parser code uses the do
* interesting things to the verilog. The parse function reads and
* parses the source file and places all the modules it finds into the
* mod list. The dump function dumps a module to the output stream.
extern int pform_parse(const char*path, map<string,Module*>&mod,
extern void pform_dump(ostream&out, Module*mod);
* $Log: pform.h,v $
* Revision 1.9 1999/04/19 01:59:37 steve
* Add memories to the parse and elaboration phases.
* Revision 1.8 1999/02/21 17:01:57 steve
* Add support for module parameters.
* Revision 1.7 1999/02/15 02:06:15 steve
* Elaborate gate ranges.
* Revision 1.6 1999/01/25 05:45:56 steve
* Add the LineInfo class to carry the source file
* location of things. PGate, Statement and PProcess.
* elaborate handles module parameter mismatches,
* missing or incorrect lvalues for procedural
* assignment, and errors are propogated to the
* top of the elaboration call tree.
* Attach line numbers to processes, gates and
* assignment statements.
* Revision 1.5 1998/12/09 04:02:47 steve
* Support the include directive.
* Revision 1.4 1998/12/01 00:42:14 steve
* Elaborate UDP devices,
* Support UDP type attributes, and
* pass those attributes to nodes that
* are instantiated by elaboration,
* Put modules into a map instead of
* a simple list.
* Revision 1.3 1998/11/25 02:35:53 steve
* Parse UDP primitives all the way to pform.
* Revision 1.2 1998/11/23 00:20:23 steve
* NetAssign handles lvalues as pin links
* instead of a signal pointer,
* Wire attributes added,
* Ability to parse UDP descriptions added,
* XNF generates EXT records for signals with
* the PAD attribute.
* Revision 1.1 1998/11/03 23:29:04 steve
* Introduce verilog to CVS.
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