Skip to content
This repository
tag: v0_9_5
Fetching contributors…

Cannot retrieve contributors at this time

file 72 lines (61 sloc) 1.125 kb
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

// Standard definitions for Verilog-AMS
`ifdef DISCIPLINES_VAMS
`else
`define DISCIPLINES_VAMS 1

discipline \logic ;
  domain discrete;
enddiscipline

discipline ddiscrete;
  domain discrete;
enddiscipline

nature Current;
  units = "A";
  access = I;
  idt_nature = Charge;
`ifdef CURRENT_ABSTOL
  abstol = `CURRENT_ABSTOL
`else
  abstol = 1e-12;
`endif
endnature

nature Charge;
  units = "coul";
  access = Q;
  ddt_nature = Current;
`ifdef CHARGE_ABSTOL
  abstol = `CHARGE_ABSTOL;
`else
  abstol = 1e-14;
`endif
endnature

nature Voltage;
  units = "V";
  access = V;
  idt_nature = Flux;
`ifdef VOLTAGE_ABSTOL
  abstol = `VOLTAGE_ABSTOL;
`else
  abstol = 1e-6;
`endif
endnature

nature Flux;
  units = "Wb";
  access = Phi;
  ddt_nature = Voltage;
`ifdef FLUX_ABSTOL
  abstol = `flux_ABSTOL;
`else
  abstol = 1e-9;
`endif
endnature

discipline electrical;
  potential Voltage;
  flow Current;
enddiscipline

discipline voltage;
  potential Voltage;
enddiscipline

discipline current;
  flow Current;
enddiscipline

`endif // !`ifdef DISCIPLINES_VAMS
Something went wrong with that request. Please try again.