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Introduce verilog to CVS.

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0 parents commit 3fb7a053bef0b62ca4b47ad629fca3e789cd2a19 steve committed Nov 3, 1998
Showing with 6,268 additions and 0 deletions.
  1. +5 −0 .cvsignore
  2. +30 −0 Makefile
  3. +61 −0 Module.cc
  4. +81 −0 Module.h
  5. +35 −0 PExpr.cc
  6. +144 −0 PExpr.h
  7. +136 −0 PGate.h
  8. +65 −0 PWire.h
  9. +67 −0 Statement.cc
  10. +193 −0 Statement.h
  11. +323 −0 design_dump.cc
  12. +605 −0 elaborate.cc
  13. +183 −0 emit.cc
  14. +41 −0 eval.cc
  15. +426 −0 lexor.lex
  16. +152 −0 main.cc
  17. +57 −0 mangle.cc
  18. +242 −0 netlist.cc
  19. +594 −0 netlist.h
  20. +548 −0 parse.y
  21. +60 −0 parse_misc.cc
  22. +60 −0 parse_misc.h
  23. +288 −0 pform.cc
  24. +127 −0 pform.h
  25. +294 −0 pform_dump.cc
  26. +81 −0 stupid.cc
  27. +298 −0 t-verilog.cc
  28. +493 −0 t-vvm.cc
  29. +122 −0 target.cc
  30. +115 −0 target.h
  31. +39 −0 targets.cc
  32. +219 −0 verinum.cc
  33. +84 −0 verinum.h
@@ -0,0 +1,5 @@
+parse.h
+parse.cc
+parse.cc.output
+lexor.cc
+vl
@@ -0,0 +1,30 @@
+
+CXXFLAGS = -O -g -Wall -Wno-uninitialized
+
+%.o dep/%.d: %.cc
+ $(CXX) $(CXXFLAGS) -MD -c $< -o $*.o
+ mv $*.d dep
+
+#TT = t-debug.o t-vvm.o
+TT = t-verilog.o t-vvm.o
+
+O = main.o design_dump.o elaborate.o emit.o eval.o lexor.o mangle.o \
+netlist.o parse.o parse_misc.o pform.o pform_dump.o stupid.o verinum.o \
+target.o targets.o Module.o PExpr.o Statement.o $(TT)
+
+vl: $O
+ $(CXX) $(CXXFLAGS) -o vl $O
+
+clean:
+ rm *.o parse.cc parse.cc.output parse.h dep/*.d lexor.cc
+
+lexor.o dep/lexor.d: lexor.cc parse.h
+
+parse.h parse.cc: parse.y
+ bison --verbose -t -p VL -d parse.y -o parse.cc
+ mv parse.cc.h parse.h
+
+lexor.cc: lexor.lex
+ flex -PVL -s -olexor.cc lexor.lex
+
+-include $(patsubst %.o, dep/%.d, $O)
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 1998 Stephen Williams (steve@icarus.com)
+ *
+ * This source code is free software; you can redistribute it
+ * and/or modify it in source code form under the terms of the GNU
+ * General Public License as published by the Free Software
+ * Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+#if !defined(WINNT)
+#ident "$Id: Module.cc,v 1.1 1998/11/03 23:28:51 steve Exp $"
+#endif
+
+# include "Module.h"
+# include "PWire.h"
+
+void Module::add_gate(PGate*gate)
+{
+ gates_.push_back(gate);
+}
+
+void Module::add_wire(PWire*wire)
+{
+ wires_.push_back(wire);
+}
+
+void Module::add_behavior(PProcess*b)
+{
+ behaviors_.push_back(b);
+}
+
+PWire* Module::get_wire(const string&name)
+{
+ for (list<PWire*>::iterator cur = wires_.begin()
+ ; cur != wires_.end()
+ ; cur ++ ) {
+
+ if ((*cur)->name == name)
+ return *cur;
+ }
+
+ return 0;
+}
+
+
+/*
+ * $Log: Module.cc,v $
+ * Revision 1.1 1998/11/03 23:28:51 steve
+ * Introduce verilog to CVS.
+ *
+ */
+
@@ -0,0 +1,81 @@
+#ifndef __Module_H
+#define __Module_H
+/*
+ * Copyright (c) 1998 Stephen Williams (steve@icarus.com)
+ *
+ * This source code is free software; you can redistribute it
+ * and/or modify it in source code form under the terms of the GNU
+ * General Public License as published by the Free Software
+ * Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+#if !defined(WINNT)
+#ident "$Id: Module.h,v 1.1 1998/11/03 23:28:52 steve Exp $"
+#endif
+
+# include <list>
+# include <vector>
+# include <string>
+class PGate;
+class PWire;
+class PProcess;
+class Design;
+
+/*
+ * A module is a named container and scope. A module holds a bunch of
+ * semantic quantities such as wires and gates. The module is
+ * therefore the handle for grasping the described circuit.
+ */
+
+class Module {
+ public:
+ explicit Module(const string&name, unsigned nports)
+ : ports(nports), name_(name) { }
+
+ vector<PWire*> ports;
+
+ const string&get_name() const { return name_; }
+
+ void add_gate(PGate*gate);
+ void add_wire(PWire*wire);
+ void add_behavior(PProcess*behave);
+
+ // Find a wire by name. This is used for connecting gates to
+ // existing wires, etc.
+ PWire* get_wire(const string&name);
+
+ const list<PWire*>& get_wires() const { return wires_; }
+ const list<PGate*>& get_gates() const { return gates_; }
+ const list<PProcess*>& get_behaviors() const { return behaviors_; }
+
+ void elaborate(Design*, const string&path) const;
+
+ private:
+ const string name_;
+
+ list<PWire*> wires_;
+ list<PGate*> gates_;
+ list<PProcess*> behaviors_;
+
+ private: // Not implemented
+ Module(const Module&);
+ Module& operator= (const Module&);
+};
+
+
+/*
+ * $Log: Module.h,v $
+ * Revision 1.1 1998/11/03 23:28:52 steve
+ * Introduce verilog to CVS.
+ *
+ */
+#endif
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 1998 Stephen Williams <steve@icarus.com>
+ *
+ * This source code is free software; you can redistribute it
+ * and/or modify it in source code form under the terms of the GNU
+ * General Public License as published by the Free Software
+ * Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+#if !defined(WINNT)
+#ident "$Id: PExpr.cc,v 1.1 1998/11/03 23:28:53 steve Exp $"
+#endif
+
+# include "PExpr.h"
+
+PExpr::~PExpr()
+{
+}
+
+/*
+ * $Log: PExpr.cc,v $
+ * Revision 1.1 1998/11/03 23:28:53 steve
+ * Introduce verilog to CVS.
+ *
+ */
+
144 PExpr.h
@@ -0,0 +1,144 @@
+#ifndef __PExpr_H
+#define __PExpr_H
+/*
+ * Copyright (c) 1998 Stephen Williams <steve@icarus.com>
+ *
+ * This source code is free software; you can redistribute it
+ * and/or modify it in source code form under the terms of the GNU
+ * General Public License as published by the Free Software
+ * Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+#if !defined(WINNT)
+#ident "$Id: PExpr.h,v 1.1 1998/11/03 23:28:54 steve Exp $"
+#endif
+
+# include <string>
+# include "verinum.h"
+
+class Design;
+class NetNet;
+class NetExpr;
+
+/*
+ * The PExpr class hierarchy supports the description of
+ * expressions. The parser can generate expression objects from the
+ * source, possibly reducing things that it knows how to reduce.
+ *
+ * The elaborate_net method is used by structural elaboration to build
+ * up a netlist interpretation of the expression.
+ */
+
+class PExpr {
+ public:
+ virtual ~PExpr();
+
+ virtual void dump(ostream&) const;
+ virtual NetNet* elaborate_net(Design*des, const string&path) const;
+ virtual NetExpr*elaborate_expr(Design*des, const string&path) const;
+
+ // This attempts to evaluate a constant expression, and return
+ // a verinum as a result. If the expression cannot be
+ // evaluated, return 0.
+ virtual verinum* eval_const() const;
+};
+
+ostream& operator << (ostream&, const PExpr&);
+
+class PEIdent : public PExpr {
+
+ public:
+ explicit PEIdent(const string&s)
+ : text_(s), msb_(0), lsb_(0) { }
+
+ virtual void dump(ostream&) const;
+ virtual NetNet* elaborate_net(Design*des, const string&path) const;
+ virtual NetExpr*elaborate_expr(Design*des, const string&path) const;
+
+
+ private:
+ string text_;
+
+ public:
+ // Use these to support bit- and part-select operators.
+ PExpr*msb_;
+ PExpr*lsb_;
+};
+
+class PENumber : public PExpr {
+
+ public:
+ explicit PENumber(verinum*vp)
+ : value_(vp) { assert(vp); }
+ ~PENumber() { delete value_; }
+
+ const verinum& value() const { return *value_; }
+
+ virtual void dump(ostream&) const;
+ virtual NetExpr*elaborate_expr(Design*des, const string&path) const;
+ virtual verinum* eval_const() const;
+
+ private:
+ verinum*const value_;
+};
+
+class PEString : public PExpr {
+
+ public:
+ explicit PEString(const string&s)
+ : text_(s) { }
+
+ string value() const { return text_; }
+ virtual void dump(ostream&) const;
+ virtual NetExpr*elaborate_expr(Design*des, const string&path) const;
+
+ private:
+ const string text_;
+};
+
+class PEUnary : public PExpr {
+
+ public:
+ explicit PEUnary(char op, PExpr*ex)
+ : op_(op), expr_(ex) { }
+
+ virtual void dump(ostream&out) const;
+ virtual NetNet* elaborate_net(Design*des, const string&path) const;
+ virtual NetExpr*elaborate_expr(Design*des, const string&path) const;
+
+ private:
+ char op_;
+ PExpr*expr_;
+};
+
+class PEBinary : public PExpr {
+
+ public:
+ explicit PEBinary(char op, PExpr*l, PExpr*r)
+ : op_(op), left_(l), right_(r) { }
+
+ virtual void dump(ostream&out) const;
+ virtual NetNet* elaborate_net(Design*des, const string&path) const;
+
+ private:
+ char op_;
+ PExpr*left_;
+ PExpr*right_;
+};
+
+/*
+ * $Log: PExpr.h,v $
+ * Revision 1.1 1998/11/03 23:28:54 steve
+ * Introduce verilog to CVS.
+ *
+ */
+#endif
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