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Add power operator (**) for real values in a continuous assignment.

This patch adds the power operator for real values in a continuous
assignment.
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commit 5e8a1bd8cc0fd45cafe1b9e24036ac2be4a6bda3 1 parent fa759c1
@caryr caryr authored committed
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7 PExpr.h
@@ -1,7 +1,7 @@
#ifndef __PExpr_H
#define __PExpr_H
/*
- * Copyright (c) 1998-2000 Stephen Williams <steve@icarus.com>
+ * Copyright (c) 1998-2008 Stephen Williams <steve@icarus.com>
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -589,6 +589,11 @@ class PEBinary : public PExpr {
const NetExpr* rise,
const NetExpr* fall,
const NetExpr* decay) const;
+ NetNet* elaborate_net_pow_(Design*des, NetScope*scope,
+ unsigned lwidth,
+ const NetExpr* rise,
+ const NetExpr* fall,
+ const NetExpr* decay) const;
NetNet* elaborate_net_shift_(Design*des, NetScope*scope,
unsigned lwidth,
const NetExpr* rise,
View
13 design_dump.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 1998-2000 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 1998-2008 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -16,9 +16,6 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
-#ifdef HAVE_CVS_IDENT
-#ident "$Id: design_dump.cc,v 1.176 2007/06/02 03:42:12 steve Exp $"
-#endif
# include "config.h"
@@ -303,6 +300,13 @@ void NetMult::dump_node(ostream&o, unsigned ind) const
dump_obj_attr(o, ind+4);
}
+void NetPow::dump_node(ostream&o, unsigned ind) const
+{
+ o << setw(ind) << "" << "LPM_POW (NetPow): " << name() << endl;
+ dump_node_pins(o, ind+4);
+ dump_obj_attr(o, ind+4);
+}
+
void NetMux::dump_node(ostream&o, unsigned ind) const
{
o << setw(ind) << "" << "Multiplexer (NetMux): " << name()
@@ -1232,4 +1236,3 @@ void Design::dump(ostream&o) const
idx->dump(o, 0);
}
-
View
104 elab_net.cc
@@ -70,6 +70,8 @@ NetNet* PEBinary::elaborate_net(Design*des, NetScope*scope,
return elaborate_net_mod_(des, scope, width, rise, fall, decay);
case '/':
return elaborate_net_div_(des, scope, width, rise, fall, decay);
+ case 'p': // **
+ return elaborate_net_pow_(des, scope, width, rise, fall, decay);
case '+':
case '-':
return elaborate_net_add_(des, scope, width, rise, fall, decay);
@@ -96,10 +98,6 @@ NetNet* PEBinary::elaborate_net(Design*des, NetScope*scope,
case 'r': // >>
case 'R': // >>>
return elaborate_net_shift_(des, scope, width, rise, fall, decay);
- case 'p': // **
- cerr << get_fileline() << ": sorry: ** is currently unsupported"
- " in continuous assignments." << endl;
- des->errors += 1;
return 0;
}
@@ -769,8 +767,6 @@ NetNet* PEBinary::elaborate_net_div_(Design*des, NetScope*scope,
des->errors += 1;
}
- ivl_variable_type_t data_type = lsig->data_type();
-
// Create a device with the calculated dimensions.
NetDivide*div = new NetDivide(scope, scope->local_symbol(), rwidth,
lsig->vector_width(),
@@ -799,7 +795,7 @@ NetNet* PEBinary::elaborate_net_div_(Design*des, NetScope*scope,
NetNet::IMPLICIT, lwidth);
osig->local_flag(true);
osig->set_line(*this);
- osig->data_type(data_type);
+ osig->data_type( lsig->data_type() );
osig->set_signed(div->get_signed());
connect(div->pin_Result(), osig->pin(0));
@@ -838,8 +834,6 @@ NetNet* PEBinary::elaborate_net_mod_(Design*des, NetScope*scope,
des->errors += 1;
}
- ivl_variable_type_t data_type = lsig->data_type();
-
/* rwidth is result width. */
unsigned rwidth = lwidth;
if (rwidth == 0) {
@@ -865,7 +859,7 @@ NetNet* PEBinary::elaborate_net_mod_(Design*des, NetScope*scope,
NetNet*osig = new NetNet(scope, scope->local_symbol(),
NetNet::IMPLICIT, rwidth);
osig->set_line(*this);
- osig->data_type(data_type);
+ osig->data_type( lsig->data_type() );
osig->local_flag(true);
connect(mod->pin_Result(), osig->pin(0));
@@ -1030,9 +1024,6 @@ NetNet* PEBinary::elaborate_net_mul_(Design*des, NetScope*scope,
NetNet*rsig = right_->elaborate_net(des, scope, lwidth, 0, 0, 0);
if (rsig == 0) return 0;
- // The mult is signed if both its operands are signed.
- bool arith_is_signed = lsig->get_signed() && rsig->get_signed();
-
/* The arguments of a multiply must have the same type. */
if (lsig->data_type() != rsig->data_type()) {
cerr << get_fileline() << ": error: Arguments of multiply "
@@ -1043,7 +1034,8 @@ NetNet* PEBinary::elaborate_net_mul_(Design*des, NetScope*scope,
des->errors += 1;
}
- ivl_variable_type_t data_type = lsig->data_type();
+ // The mult is signed if both its operands are signed.
+ bool arith_is_signed = lsig->get_signed() && rsig->get_signed();
unsigned rwidth = lwidth;
if (rwidth == 0) {
@@ -1079,13 +1071,84 @@ NetNet* PEBinary::elaborate_net_mul_(Design*des, NetScope*scope,
// Make a signal to carry the output from the multiply.
NetNet*osig = new NetNet(scope, scope->local_symbol(),
NetNet::IMPLICIT, rwidth);
- osig->data_type(data_type);
+ osig->data_type( lsig->data_type() );
osig->local_flag(true);
connect(mult->pin_Result(), osig->pin(0));
return osig;
}
+NetNet* PEBinary::elaborate_net_pow_(Design*des, NetScope*scope,
+ unsigned lwidth,
+ const NetExpr* rise,
+ const NetExpr* fall,
+ const NetExpr* decay) const
+{
+ NetNet*lsig = left_->elaborate_net(des, scope, lwidth, 0, 0, 0);
+ if (lsig == 0) return 0;
+ NetNet*rsig = right_->elaborate_net(des, scope, lwidth, 0, 0, 0);
+ if (rsig == 0) return 0;
+
+ /* The arguments of a power must have the same type. */
+ if (lsig->data_type() != rsig->data_type()) {
+ cerr << get_fileline() << ": error: Arguments of power "
+ << "have different data types." << endl;
+ cerr << get_fileline() << ": : Left argument is "
+ << lsig->data_type() << ", right argument is "
+ << rsig->data_type() << "." << endl;
+ des->errors += 1;
+ }
+
+ /* For now we only support real values. */
+ if (lsig->data_type() != IVL_VT_REAL) {
+ cerr << get_fileline() << ": sorry: Bit based power (**) is "
+ << "currently unsupported in continuous assignments." << endl;
+ return 0;
+ }
+
+ // The power is signed if both its operands are signed.
+ bool arith_is_signed = lsig->get_signed() && rsig->get_signed();
+
+ unsigned rwidth = lwidth;
+ if (rwidth == 0) {
+ /* Reals are always 1 wide and lsig/rsig types match here. */
+ if (lsig->data_type() == IVL_VT_REAL) {
+ rwidth = 1;
+ lwidth = 1;
+ } else {
+ /* Nothing for now. Need integer value.*/
+ }
+ }
+
+ if (arith_is_signed) {
+ lsig = pad_to_width_signed(des, lsig, rwidth);
+ rsig = pad_to_width_signed(des, rsig, rwidth);
+ }
+
+ NetPow*powr = new NetPow(scope, scope->local_symbol(), rwidth,
+ lsig->vector_width(),
+ rsig->vector_width());
+ powr->set_line(*this);
+ powr->rise_time(rise);
+ powr->fall_time(fall);
+ powr->decay_time(decay);
+ des->add_node(powr);
+
+ powr->set_signed( arith_is_signed );
+
+ connect(powr->pin_DataA(), lsig->pin(0));
+ connect(powr->pin_DataB(), rsig->pin(0));
+
+ // Make a signal to carry the output from the power.
+ NetNet*osig = new NetNet(scope, scope->local_symbol(),
+ NetNet::IMPLICIT, rwidth);
+ osig->data_type( lsig->data_type() );
+ osig->local_flag(true);
+ connect(powr->pin_Result(), osig->pin(0));
+
+ return osig;
+}
+
NetNet* PEBinary::elaborate_net_shift_(Design*des, NetScope*scope,
unsigned lwidth,
const NetExpr* rise,
@@ -1100,7 +1163,6 @@ NetNet* PEBinary::elaborate_net_shift_(Design*des, NetScope*scope,
bool right_flag = op_ == 'r' || op_ == 'R';
bool signed_flag = op_ == 'R';
- ivl_variable_type_t data_type = lsig->data_type();
/* Handle the special case of a constant shift amount. There
is no reason in this case to create a gate at all, just
@@ -1121,7 +1183,7 @@ NetNet* PEBinary::elaborate_net_shift_(Design*des, NetScope*scope,
result that I return from this function. */
NetNet*osig = new NetNet(scope, scope->local_symbol(),
NetNet::WIRE, lwidth);
- osig->data_type( data_type );
+ osig->data_type( lsig->data_type() );
osig->local_flag(true);
@@ -1150,7 +1212,7 @@ NetNet* PEBinary::elaborate_net_shift_(Design*des, NetScope*scope,
NetNet*zero = new NetNet(scope, scope->local_symbol(),
NetNet::WIRE, pad_width);
- zero->data_type( data_type );
+ zero->data_type( lsig->data_type() );
zero->local_flag(true);
zero->set_line(*this);
@@ -1167,7 +1229,7 @@ NetNet* PEBinary::elaborate_net_shift_(Design*des, NetScope*scope,
des->add_node(sign_pad);
NetNet*tmp = new NetNet(scope, scope->local_symbol(),
NetNet::WIRE, 1);
- tmp->data_type( data_type );
+ tmp->data_type( lsig->data_type() );
tmp->local_flag(true);
tmp->set_line(*this);
connect(sign_bit->pin(0), tmp->pin(0));
@@ -1238,7 +1300,7 @@ NetNet* PEBinary::elaborate_net_shift_(Design*des, NetScope*scope,
input) */
NetNet*tmp = new NetNet(scope, scope->local_symbol(),
NetNet::WIRE, part_width);
- tmp->data_type( data_type );
+ tmp->data_type( lsig->data_type() );
tmp->local_flag(true);
tmp->set_line(*this);
connect(part->pin(0), tmp->pin(0));
@@ -1268,7 +1330,7 @@ NetNet* PEBinary::elaborate_net_shift_(Design*des, NetScope*scope,
NetNet*osig = new NetNet(scope, scope->local_symbol(),
NetNet::WIRE, lwidth);
- osig->data_type( data_type );
+ osig->data_type( lsig->data_type() );
osig->local_flag(true);
osig->set_signed(signed_flag);
View
8 emit.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 1998-2005 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 1998-2008 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -128,6 +128,12 @@ bool NetPartSelect::emit_node(struct target_t*tgt) const
return tgt->part_select(this);
}
+bool NetPow::emit_node(struct target_t*tgt) const
+{
+ tgt->lpm_pow(this);
+ return true;
+}
+
bool NetReplicate::emit_node(struct target_t*tgt) const
{
return tgt->replicate(this);
View
68 functor.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 1999-2005 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 1999-2008 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -16,9 +16,6 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
-#ifdef HAVE_CVS_IDENT
-#ident "$Id: functor.cc,v 1.35 2005/07/07 16:22:49 steve Exp $"
-#endif
# include "config.h"
@@ -83,6 +80,10 @@ void functor_t::lpm_mux(class Design*, class NetMux*)
{
}
+void functor_t::lpm_pow(class Design*, class NetPow*)
+{
+}
+
void functor_t::sign_extend(class Design*, class NetSignExtend*)
{
}
@@ -223,6 +224,11 @@ void NetMux::functor_node(Design*des, functor_t*fun)
fun->lpm_mux(des, this);
}
+void NetPow::functor_node(Design*des, functor_t*fun)
+{
+ fun->lpm_pow(des, this);
+}
+
void NetSignExtend::functor_node(Design*des, functor_t*fun)
{
fun->sign_extend(des, this);
@@ -291,57 +297,3 @@ int proc_match_t::event_wait(NetEvWait*)
{
return 0;
}
-
-/*
- * $Log: functor.cc,v $
- * Revision 1.35 2005/07/07 16:22:49 steve
- * Generalize signals to carry types.
- *
- * Revision 1.34 2005/05/24 01:44:27 steve
- * Do sign extension of structuran nets.
- *
- * Revision 1.33 2005/02/03 04:56:20 steve
- * laborate reduction gates into LPM_RED_ nodes.
- *
- * Revision 1.32 2004/10/04 01:10:53 steve
- * Clean up spurious trailing white space.
- *
- * Revision 1.31 2002/08/16 05:18:27 steve
- * Fix intermix of node functors and node delete.
- *
- * Revision 1.30 2002/08/12 01:34:59 steve
- * conditional ident string using autoconfig.
- *
- * Revision 1.29 2002/08/10 22:07:38 steve
- * Remove useless error messages.
- *
- * Revision 1.28 2002/06/05 03:44:25 steve
- * Add support for memory words in l-value of
- * non-blocking assignments, and remove the special
- * NetAssignMem_ and NetAssignMemNB classes.
- *
- * Revision 1.27 2002/06/04 05:38:44 steve
- * Add support for memory words in l-value of
- * blocking assignments, and remove the special
- * NetAssignMem class.
- *
- * Revision 1.26 2001/10/19 21:53:24 steve
- * Support multiple root modules (Philip Blundell)
- *
- * Revision 1.25 2001/07/25 03:10:49 steve
- * Create a config.h.in file to hold all the config
- * junk, and support gcc 3.0. (Stephan Boettcher)
- *
- * Revision 1.24 2000/11/19 20:48:30 steve
- * Fix cases where signal iteration might die early.
- *
- * Revision 1.23 2000/11/18 04:53:04 steve
- * Watch out in functor, it may delete the last signal.
- *
- * Revision 1.22 2000/09/17 21:26:15 steve
- * Add support for modulus (Eric Aardoom)
- *
- * Revision 1.21 2000/08/01 02:48:41 steve
- * Support <= in synthesis of DFF and ram devices.
- */
-
View
48 functor.h
@@ -1,7 +1,7 @@
#ifndef __functor_H
#define __functor_H
/*
- * Copyright (c) 1999-2005 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 1999-2008 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -18,9 +18,6 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
-#ifdef HAVE_CVS_IDENT
-#ident "$Id: functor.h,v 1.23 2005/07/07 16:22:49 steve Exp $"
-#endif
/*
* The functor is an object that can be applied to a design to
@@ -81,6 +78,9 @@ struct functor_t {
/* This method is called for each MUX. */
virtual void lpm_mux(class Design*des, class NetMux*);
+ /* This method is called for each power. */
+ virtual void lpm_pow(class Design*des, class NetPow*);
+
/* This method is called for each unary reduction gate. */
virtual void lpm_ureduce(class Design*des, class NetUReduce*);
@@ -97,44 +97,4 @@ struct proc_match_t {
virtual int block(class NetBlock*);
};
-
-/*
- * $Log: functor.h,v $
- * Revision 1.23 2005/07/07 16:22:49 steve
- * Generalize signals to carry types.
- *
- * Revision 1.22 2005/05/24 01:44:27 steve
- * Do sign extension of structuran nets.
- *
- * Revision 1.21 2005/02/03 04:56:20 steve
- * laborate reduction gates into LPM_RED_ nodes.
- *
- * Revision 1.20 2002/08/12 01:34:59 steve
- * conditional ident string using autoconfig.
- *
- * Revision 1.19 2002/06/05 03:44:25 steve
- * Add support for memory words in l-value of
- * non-blocking assignments, and remove the special
- * NetAssignMem_ and NetAssignMemNB classes.
- *
- * Revision 1.18 2002/06/04 05:38:44 steve
- * Add support for memory words in l-value of
- * blocking assignments, and remove the special
- * NetAssignMem class.
- *
- * Revision 1.17 2000/09/17 21:26:15 steve
- * Add support for modulus (Eric Aardoom)
- *
- * Revision 1.16 2000/08/01 02:48:42 steve
- * Support <= in synthesis of DFF and ram devices.
- *
- * Revision 1.15 2000/07/16 04:56:07 steve
- * Handle some edge cases during node scans.
- *
- * Revision 1.14 2000/07/15 05:13:44 steve
- * Detect muxing Vz as a bufufN.
- *
- * Revision 1.13 2000/04/20 00:28:03 steve
- * Catch some simple identity compareoptimizations.
- */
#endif
View
17 ivl_target.h
@@ -245,6 +245,7 @@ typedef enum ivl_lpm_type_e {
IVL_LPM_PART_BI= 28, /* part select: bi-directional (part on 0) */
IVL_LPM_PART_VP= 15, /* part select: vector to part */
IVL_LPM_PART_PV= 17, /* part select: part written to vector */
+ IVL_LPM_POW = 31,
IVL_LPM_RE_AND = 20,
IVL_LPM_RE_NAND= 21,
IVL_LPM_RE_NOR = 22,
@@ -947,6 +948,16 @@ extern unsigned ivl_lpm_lineno(ivl_lpm_t net);
* Multiply may be signed. If so, the output should be sign extended
* to fill in its result.
*
+ * - Power (IVL_LPM_POWR)
+ * The power takes two inputs and generates an output. Unlike other
+ * arithmetic nodes, the width only refers to the output. The inputs
+ * have independent widths, to reflect the arithmetic truth that the
+ * width of a general power is the XXXX of the widths of the
+ * inputs.
+ *
+ * Power may be signed. If so, the output should be sign extended
+ * to fill in its result.
+ *
* - Part Select (IVL_LPM_PART_VP and IVL_LPM_PART_PV)
* There are two part select devices, one that extracts a part from a
* vector, and another that writes a part of a vector. The _VP is
@@ -1113,12 +1124,12 @@ extern ivl_scope_t ivl_lpm_define(ivl_lpm_t net);
/* IVL_LPM_FF */
extern ivl_nexus_t ivl_lpm_enable(ivl_lpm_t net);
/* IVL_LPM_ADD IVL_LPM_CONCAT IVL_LPM_FF IVL_LPM_PART IVL_LPM_MULT
- IVL_LPM_MUX IVL_LPM_SHIFTL IVL_LPM_SHIFTR IVL_LPM_SUB
+ IVL_LPM_MUX IVL_LPM_POWR IVL_LPM_SHIFTL IVL_LPM_SHIFTR IVL_LPM_SUB
IVL_LPM_UFUNC */
extern ivl_nexus_t ivl_lpm_data(ivl_lpm_t net, unsigned idx);
- /* IVL_LPM_ADD IVL_LPM_MULT IVL_LPM_SUB */
+ /* IVL_LPM_ADD IVL_LPM_MULT IVL_LPM_POWR IVL_LPM_SUB */
extern ivl_nexus_t ivl_lpm_datab(ivl_lpm_t net, unsigned idx);
- /* IVL_LPM_ADD IVL_LPM_FF IVL_LPM_MULT IVL_LPM_PART
+ /* IVL_LPM_ADD IVL_LPM_FF IVL_LPM_MULT IVL_LPM_PART IVL_LPM_POWR
IVL_LPM_SUB IVL_LPM_UFUNC */
extern ivl_nexus_t ivl_lpm_q(ivl_lpm_t net, unsigned idx);
/* IVL_LPM_MUX */
View
228 netlist.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 1998-2004 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 1998-2008 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -1557,6 +1557,78 @@ const Link& NetMult::pin_DataB() const
return pin(2);
}
+NetPow::NetPow(NetScope*sc, perm_string n, unsigned wr,
+ unsigned wa, unsigned wb)
+: NetNode(sc, n, 3),
+ signed_(false), width_r_(wr), width_a_(wa), width_b_(wb)
+{
+ pin(0).set_dir(Link::OUTPUT);
+ pin(0).set_name(perm_string::literal("Result"), 0);
+ pin(1).set_dir(Link::INPUT);
+ pin(1).set_name(perm_string::literal("DataA"), 0);
+ pin(2).set_dir(Link::INPUT);
+ pin(2).set_name(perm_string::literal("DataB"), 0);
+}
+
+NetPow::~NetPow()
+{
+}
+
+void NetPow::set_signed(bool flag)
+{
+ signed_ = flag;
+}
+
+bool NetPow::get_signed() const
+{
+ return signed_;
+}
+
+unsigned NetPow::width_r() const
+{
+ return width_r_;
+}
+
+unsigned NetPow::width_a() const
+{
+ return width_a_;
+}
+
+unsigned NetPow::width_b() const
+{
+ return width_b_;
+}
+
+Link& NetPow::pin_Result()
+{
+ return pin(0);
+}
+
+const Link& NetPow::pin_Result() const
+{
+ return pin(0);
+}
+
+Link& NetPow::pin_DataA()
+{
+ return pin(1);
+}
+
+const Link& NetPow::pin_DataA() const
+{
+ return pin(1);
+}
+
+Link& NetPow::pin_DataB()
+{
+ return pin(2);
+}
+
+const Link& NetPow::pin_DataB() const
+{
+ return pin(2);
+}
+
/*
* The NetMux class represents an LPM_MUX device. The pinout is assigned
* like so:
@@ -2339,157 +2411,3 @@ const NetProc*NetTaskDef::proc() const
{
return proc_;
}
-
-/*
- * $Log: netlist.cc,v $
- * Revision 1.258 2007/06/02 03:42:13 steve
- * Properly evaluate scope path expressions.
- *
- * Revision 1.257 2007/04/02 01:12:34 steve
- * Seperate arrayness from word count
- *
- * Revision 1.256 2007/03/02 06:13:22 steve
- * Add support for edge sensitive spec paths.
- *
- * Revision 1.255 2007/03/01 06:19:38 steve
- * Add support for conditional specify delay paths.
- *
- * Revision 1.254 2007/02/20 05:58:36 steve
- * Handle unary minus of real valued expressions.
- *
- * Revision 1.253 2007/02/14 05:59:46 steve
- * Handle type of ternary expressions properly.
- *
- * Revision 1.252 2007/01/19 04:25:37 steve
- * Fix missing passive setting for array word pins.
- *
- * Revision 1.251 2007/01/16 05:44:15 steve
- * Major rework of array handling. Memories are replaced with the
- * more general concept of arrays. The NetMemory and NetEMemory
- * classes are removed from the ivl core program, and the IVL_LPM_RAM
- * lpm type is removed from the ivl_target API.
- *
- * Revision 1.250 2006/11/10 04:54:26 steve
- * Add test_width methods for PETernary and PEString.
- *
- * Revision 1.249 2006/09/23 04:57:19 steve
- * Basic support for specify timing.
- *
- * Revision 1.248 2005/09/14 02:53:14 steve
- * Support bool expressions and compares handle them optimally.
- *
- * Revision 1.247 2005/08/06 17:58:16 steve
- * Implement bi-directional part selects.
- *
- * Revision 1.246 2005/07/11 16:56:50 steve
- * Remove NetVariable and ivl_variable_t structures.
- *
- * Revision 1.245 2005/07/07 16:22:49 steve
- * Generalize signals to carry types.
- *
- * Revision 1.244 2005/05/24 01:44:28 steve
- * Do sign extension of structuran nets.
- *
- * Revision 1.243 2005/05/08 23:44:08 steve
- * Add support for variable part select.
- *
- * Revision 1.242 2005/04/24 23:44:02 steve
- * Update DFF support to new data flow.
- *
- * Revision 1.241 2005/04/08 04:51:16 steve
- * All memory addresses are signed.
- *
- * Revision 1.240 2005/04/06 05:29:08 steve
- * Rework NetRamDq and IVL_LPM_RAM nodes.
- *
- * Revision 1.239 2005/03/09 05:52:04 steve
- * Handle case inequality in netlists.
- *
- * Revision 1.238 2005/02/19 02:43:38 steve
- * Support shifts and divide.
- *
- * Revision 1.237 2005/02/12 06:25:40 steve
- * Restructure NetMux devices to pass vectors.
- * Generate NetMux devices from ternary expressions,
- * Reduce NetMux devices to bufif when appropriate.
- *
- * Revision 1.236 2005/02/08 00:12:36 steve
- * Add the NetRepeat node, and code generator support.
- *
- * Revision 1.235 2005/02/03 04:56:20 steve
- * laborate reduction gates into LPM_RED_ nodes.
- *
- * Revision 1.234 2005/01/28 05:39:33 steve
- * Simplified NetMult and IVL_LPM_MULT.
- *
- * Revision 1.233 2005/01/24 05:28:30 steve
- * Remove the NetEBitSel and combine all bit/part select
- * behavior into the NetESelect node and IVL_EX_SELECT
- * ivl_target expression type.
- *
- * Revision 1.232 2005/01/22 18:16:01 steve
- * Remove obsolete NetSubnet class.
- *
- * Revision 1.231 2005/01/22 01:06:55 steve
- * Change case compare from logic to an LPM node.
- *
- * Revision 1.230 2005/01/16 04:20:32 steve
- * Implement LPM_COMPARE nodes as two-input vector functors.
- *
- * Revision 1.229 2005/01/09 20:16:01 steve
- * Use PartSelect/PV and VP to handle part selects through ports.
- *
- * Revision 1.228 2004/12/29 23:55:43 steve
- * Unify elaboration of l-values for all proceedural assignments,
- * including assing, cassign and force.
- *
- * Generate NetConcat devices for gate outputs that feed into a
- * vector results. Use this to hande gate arrays. Also let gate
- * arrays handle vectors of gates when the outputs allow for it.
- *
- * Revision 1.227 2004/12/11 02:31:26 steve
- * Rework of internals to carry vectors through nexus instead
- * of single bits. Make the ivl, tgt-vvp and vvp initial changes
- * down this path.
- *
- * Revision 1.226 2004/10/04 01:10:54 steve
- * Clean up spurious trailing white space.
- *
- * Revision 1.225 2004/06/30 02:16:26 steve
- * Implement signed divide and signed right shift in nets.
- *
- * Revision 1.224 2004/06/13 04:56:54 steve
- * Add support for the default_nettype directive.
- *
- * Revision 1.223 2004/05/31 23:34:37 steve
- * Rewire/generalize parsing an elaboration of
- * function return values to allow for better
- * speed and more type support.
- *
- * Revision 1.222 2004/02/20 06:22:56 steve
- * parameter keys are per_strings.
- *
- * Revision 1.221 2004/02/18 17:11:56 steve
- * Use perm_strings for named langiage items.
- *
- * Revision 1.220 2003/11/10 19:44:30 steve
- * Fix return value warnings.
- *
- * Revision 1.219 2003/09/03 23:32:10 steve
- * Oops, missing pin_Sset implementation.
- *
- * Revision 1.218 2003/08/15 02:23:52 steve
- * Add synthesis support for synchronous reset.
- *
- * Revision 1.217 2003/07/05 20:42:08 steve
- * Fix some enumeration warnings.
- *
- * Revision 1.216 2003/06/18 03:55:18 steve
- * Add arithmetic shift operators.
- *
- * Revision 1.215 2003/05/01 01:13:57 steve
- * More complete bit range internal error message,
- * Better test of part select ranges on non-zero
- * signal ranges.
- */
-
View
50 netlist.h
@@ -1,7 +1,7 @@
#ifndef __netlist_H
#define __netlist_H
/*
- * Copyright (c) 1998-2006 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 1998-2008 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -18,9 +18,6 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
-#ifdef HAVE_CVS_IDENT
-#ident "$Id: netlist.h,v 1.380 2007/06/02 03:42:13 steve Exp $"
-#endif
/*
* The netlist types, as described in this header file, are intended
@@ -984,6 +981,51 @@ class NetMux : public NetNode {
/*
+ * This class implements a basic LPM_POW combinational power. It
+ * is used as a structural representation of the ** operator. The
+ * device has inputs A and B and output Result all with independent
+ * widths.
+ *
+ * NOTE: Check this width thing. I think that the independence of the
+ * widths is not necessary or even useful.
+ */
+class NetPow : public NetNode {
+
+ public:
+ NetPow(NetScope*sc, perm_string n, unsigned width,
+ unsigned wa, unsigned wb);
+ ~NetPow();
+
+ bool get_signed() const;
+ void set_signed(bool);
+
+ // Get the width of the device bussed inputs. There are these
+ // parameterized widths:
+ unsigned width_r() const; // Result
+ unsigned width_a() const; // DataA
+ unsigned width_b() const; // DataB
+
+ Link& pin_DataA();
+ Link& pin_DataB();
+ Link& pin_Result();
+
+ const Link& pin_DataA() const;
+ const Link& pin_DataB() const;
+ const Link& pin_Result() const;
+
+ virtual void dump_node(ostream&, unsigned ind) const;
+ virtual bool emit_node(struct target_t*) const;
+ virtual void functor_node(Design*des, functor_t*fun);
+
+ private:
+ bool signed_;
+ unsigned width_r_;
+ unsigned width_a_;
+ unsigned width_b_;
+};
+
+
+/*
* The NetReplicate node takes a vector input and makes it into a larger
* vector by repeating the input vector some number of times. The
* repeat count is a fixed value. This is just like the repeat
View
5 t-dll-api.cc
@@ -868,6 +868,7 @@ extern "C" ivl_nexus_t ivl_lpm_data(ivl_lpm_t net, unsigned idx)
case IVL_LPM_DIVIDE:
case IVL_LPM_MOD:
case IVL_LPM_MULT:
+ case IVL_LPM_POW:
case IVL_LPM_SUB:
assert(idx <= 1);
if (idx == 0)
@@ -948,6 +949,7 @@ extern "C" ivl_nexus_t ivl_lpm_datab(ivl_lpm_t net, unsigned idx)
case IVL_LPM_DIVIDE:
case IVL_LPM_MOD:
case IVL_LPM_MULT:
+ case IVL_LPM_POW:
case IVL_LPM_SUB:
assert(idx == 0);
return net->u_.arith.b;
@@ -998,6 +1000,7 @@ extern "C" ivl_nexus_t ivl_lpm_q(ivl_lpm_t net, unsigned idx)
case IVL_LPM_DIVIDE:
case IVL_LPM_MOD:
case IVL_LPM_MULT:
+ case IVL_LPM_POW:
case IVL_LPM_SUB:
assert(idx == 0);
return net->u_.arith.q;
@@ -1119,6 +1122,7 @@ extern "C" int ivl_lpm_signed(ivl_lpm_t net)
case IVL_LPM_DIVIDE:
case IVL_LPM_MOD:
case IVL_LPM_MULT:
+ case IVL_LPM_POW:
case IVL_LPM_SUB:
return net->u_.arith.signed_flag;
case IVL_LPM_RE_AND:
@@ -2073,4 +2077,3 @@ extern "C" ivl_statement_t ivl_stmt_sub_stmt(ivl_statement_t net)
return 0;
}
-
View
42 t-dll.cc
@@ -1770,6 +1770,47 @@ void dll_target::lpm_mux(const NetMux*net)
}
+/*
+ * Make the NetPow object into an IVL_LPM_POW node.
+ */
+void dll_target::lpm_pow(const NetPow*net)
+{
+ ivl_lpm_t obj = new struct ivl_lpm_s;
+ obj->type = IVL_LPM_POW;
+ obj->name = net->name();
+ assert(net->scope());
+ obj->scope = find_scope(des_, net->scope());
+ assert(obj->scope);
+
+ unsigned wid = net->width_r();
+
+ obj->width = wid;
+
+ const Nexus*nex;
+
+ nex = net->pin_Result().nexus();
+ assert(nex->t_cookie());
+
+ obj->u_.arith.q = nex->t_cookie();
+ nexus_lpm_add(obj->u_.arith.q, obj, 0, IVL_DR_STRONG, IVL_DR_STRONG);
+
+ nex = net->pin_DataA().nexus();
+ assert(nex->t_cookie());
+
+ obj->u_.arith.a = nex->t_cookie();
+ nexus_lpm_add(obj->u_.arith.a, obj, 0, IVL_DR_HiZ, IVL_DR_HiZ);
+
+ nex = net->pin_DataB().nexus();
+ assert(nex->t_cookie());
+
+ obj->u_.arith.b = nex->t_cookie();
+ nexus_lpm_add(obj->u_.arith.b, obj, 0, IVL_DR_HiZ, IVL_DR_HiZ);
+
+ make_lpm_delays_(obj, net);
+
+ scope_add_lpm(obj->scope, obj);
+}
+
bool dll_target::concat(const NetConcat*net)
{
ivl_lpm_t obj = new struct ivl_lpm_s;
@@ -2327,4 +2368,3 @@ bool dll_target::signal_paths(const NetNet*net)
}
extern const struct target tgt_dll = { "dll", &dll_target_obj };
-
View
1  t-dll.h
@@ -79,6 +79,7 @@ struct dll_target : public target_t, public expr_scan_t {
void lpm_modulo(const NetModulo*);
void lpm_mult(const NetMult*);
void lpm_mux(const NetMux*);
+ void lpm_pow(const NetPow*);
bool concat(const NetConcat*);
bool part_select(const NetPartSelect*);
bool replicate(const NetReplicate*);
View
209 target.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 1998-2007 Stephen Williams <steve@icarus.com>
+ * Copyright (c) 1998-2008 Stephen Williams <steve@icarus.com>
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -135,6 +135,13 @@ void target_t::lpm_mux(const NetMux*)
cerr << "target (" << typeid(*this).name() << "): "
"Unhandled NetMux." << endl;
}
+
+void target_t::lpm_pow(const NetPow*)
+{
+ cerr << "target (" << typeid(*this).name() << "): "
+ "Unhandled NetPow." << endl;
+}
+
bool target_t::concat(const NetConcat*)
{
cerr << "target (" << typeid(*this).name() << "): "
@@ -423,203 +430,3 @@ void expr_scan_t::expr_binary(const NetEBinary*ex)
cerr << "expr_scan_t (" << typeid(*this).name() << "): "
"unhandled expr_binary: " <<*ex << endl;
}
-
-/*
- * $Log: target.cc,v $
- * Revision 1.81 2007/06/02 03:42:13 steve
- * Properly evaluate scope path expressions.
- *
- * Revision 1.80 2007/01/16 05:44:16 steve
- * Major rework of array handling. Memories are replaced with the
- * more general concept of arrays. The NetMemory and NetEMemory
- * classes are removed from the ivl core program, and the IVL_LPM_RAM
- * lpm type is removed from the ivl_target API.
- *
- * Revision 1.79 2006/11/10 05:44:45 steve
- * Process delay paths in second path over signals.
- *
- * Revision 1.78 2006/06/18 04:15:50 steve
- * Add support for system functions in continuous assignments.
- *
- * Revision 1.77 2005/07/11 16:56:51 steve
- * Remove NetVariable and ivl_variable_t structures.
- *
- * Revision 1.76 2005/07/07 16:22:49 steve
- * Generalize signals to carry types.
- *
- * Revision 1.75 2005/05/24 01:44:28 steve
- * Do sign extension of structuran nets.
- *
- * Revision 1.74 2005/02/08 00:12:36 steve
- * Add the NetRepeat node, and code generator support.
- *
- * Revision 1.73 2005/02/03 04:56:21 steve
- * laborate reduction gates into LPM_RED_ nodes.
- *
- * Revision 1.72 2005/01/24 05:28:31 steve
- * Remove the NetEBitSel and combine all bit/part select
- * behavior into the NetESelect node and IVL_EX_SELECT
- * ivl_target expression type.
- *
- * Revision 1.71 2004/12/29 23:55:43 steve
- * Unify elaboration of l-values for all proceedural assignments,
- * including assing, cassign and force.
- *
- * Generate NetConcat devices for gate outputs that feed into a
- * vector results. Use this to hande gate arrays. Also let gate
- * arrays handle vectors of gates when the outputs allow for it.
- *
- * Revision 1.70 2004/12/11 02:31:28 steve
- * Rework of internals to carry vectors through nexus instead
- * of single bits. Make the ivl, tgt-vvp and vvp initial changes
- * down this path.
- *
- * Revision 1.69 2004/05/31 23:34:39 steve
- * Rewire/generalize parsing an elaboration of
- * function return values to allow for better
- * speed and more type support.
- *
- * Revision 1.68 2003/05/30 02:55:32 steve
- * Support parameters in real expressions and
- * as real expressions, and fix multiply and
- * divide with real results.
- *
- * Revision 1.67 2003/04/22 04:48:30 steve
- * Support event names as expressions elements.
- *
- * Revision 1.66 2003/03/10 23:40:54 steve
- * Keep parameter constants for the ivl_target API.
- *
- * Revision 1.65 2003/01/30 16:23:08 steve
- * Spelling fixes.
- *
- * Revision 1.64 2003/01/26 21:15:59 steve
- * Rework expression parsing and elaboration to
- * accommodate real/realtime values and expressions.
- *
- * Revision 1.63 2002/08/12 01:35:01 steve
- * conditional ident string using autoconfig.
- *
- * Revision 1.62 2002/06/05 03:44:25 steve
- * Add support for memory words in l-value of
- * non-blocking assignments, and remove the special
- * NetAssignMem_ and NetAssignMemNB classes.
- *
- * Revision 1.61 2002/06/04 05:38:44 steve
- * Add support for memory words in l-value of
- * blocking assignments, and remove the special
- * NetAssignMem class.
- *
- * Revision 1.60 2002/03/09 02:10:22 steve
- * Add the NetUserFunc netlist node.
- *
- * Revision 1.59 2002/01/28 00:52:41 steve
- * Add support for bit select of parameters.
- * This leads to a NetESelect node and the
- * vvp code generator to support that.
- *
- * Revision 1.58 2002/01/19 19:02:08 steve
- * Pass back target errors processing conditionals.
- *
- * Revision 1.57 2001/08/25 23:50:03 steve
- * Change the NetAssign_ class to refer to the signal
- * instead of link into the netlist. This is faster
- * and uses less space. Make the NetAssignNB carry
- * the delays instead of the NetAssign_ lval objects.
- *
- * Change the vvp code generator to support multiple
- * l-values, i.e. concatenations of part selects.
- *
- * Revision 1.56 2001/07/27 04:51:44 steve
- * Handle part select expressions as variants of
- * NetESignal/IVL_EX_SIGNAL objects, instead of
- * creating new and useless temporary signals.
- *
- * Revision 1.55 2001/07/25 03:10:50 steve
- * Create a config.h.in file to hold all the config
- * junk, and support gcc 3.0. (Stephan Boettcher)
- *
- * Revision 1.54 2001/06/27 18:34:43 steve
- * Report line of unsupported cassign.
- *
- * Revision 1.53 2001/04/22 23:09:46 steve
- * More UDP consolidation from Stephan Boettcher.
- *
- * Revision 1.52 2001/04/06 02:28:02 steve
- * Generate vvp code for functions with ports.
- *
- * Revision 1.51 2001/04/02 02:28:13 steve
- * Generate code for task calls.
- *
- * Revision 1.50 2001/03/27 03:31:06 steve
- * Support error code from target_t::end_design method.
- *
- * Revision 1.49 2000/09/26 01:35:42 steve
- * Remove the obsolete NetEIdent class.
- *
- * Revision 1.48 2000/09/17 21:26:16 steve
- * Add support for modulus (Eric Aardoom)
- *
- * Revision 1.47 2000/09/03 17:57:53 steve
- * Slightly more helpful warning.
- *
- * Revision 1.46 2000/09/02 20:54:21 steve
- * Rearrange NetAssign to make NetAssign_ separate.
- *
- * Revision 1.45 2000/08/27 15:51:51 steve
- * t-dll iterates signals, and passes them to the
- * target module.
- *
- * Some of NetObj should return char*, not string.
- *
- * Revision 1.44 2000/08/14 04:39:57 steve
- * add th t-dll functions for net_const, net_bufz and processes.
- *
- * Revision 1.43 2000/08/09 03:43:45 steve
- * Move all file manipulation out of target class.
- *
- * Revision 1.42 2000/08/08 01:50:42 steve
- * target methods need not take a file stream.
- *
- * Revision 1.41 2000/07/29 16:21:08 steve
- * Report code generation errors through proc_delay.
- *
- * Revision 1.40 2000/07/27 05:13:44 steve
- * Support elaboration of disable statements.
- *
- * Revision 1.39 2000/05/11 23:37:27 steve
- * Add support for procedural continuous assignment.
- *
- * Revision 1.38 2000/05/04 03:37:59 steve
- * Add infrastructure for system functions, move
- * $time to that structure and add $random.
- *
- * Revision 1.37 2000/04/23 03:45:24 steve
- * Add support for the procedural release statement.
- *
- * Revision 1.36 2000/04/22 04:20:19 steve
- * Add support for force assignment.
- *
- * Revision 1.35 2000/04/12 04:23:58 steve
- * Named events really should be expressed with PEIdent
- * objects in the pform,
- *
- * Handle named events within the mix of net events
- * and edges. As a unified lot they get caught together.
- * wait statements are broken into more complex statements
- * that include a conditional.
- *
- * Do not generate NetPEvent or NetNEvent objects in
- * elaboration. NetEvent, NetEvWait and NetEvProbe
- * take over those functions in the netlist.
- *
- * Revision 1.34 2000/04/10 05:26:06 steve
- * All events now use the NetEvent class.
- *
- * Revision 1.33 2000/04/04 03:20:15 steve
- * Simulate named event trigger and waits.
- *
- * Revision 1.32 2000/04/01 21:40:23 steve
- * Add support for integer division.
- */
-
View
117 target.h
@@ -1,7 +1,7 @@
#ifndef __target_H
#define __target_H
/*
- * Copyright (c) 1998-2003 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 1998-2008 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -18,9 +18,6 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
-#ifdef HAVE_CVS_IDENT
-#ident "$Id: target.h,v 1.77 2007/01/16 05:44:16 steve Exp $"
-#endif
# include "netlist.h"
@@ -80,6 +77,7 @@ struct target_t {
virtual void lpm_ff(const NetFF*);
virtual void lpm_mult(const NetMult*);
virtual void lpm_mux(const NetMux*);
+ virtual void lpm_pow(const NetPow*);
virtual bool concat(const NetConcat*);
virtual bool part_select(const NetPartSelect*);
@@ -166,115 +164,4 @@ extern string stresc(const string&str);
terminated array of pointers to targets. */
extern const struct target *target_table[];
-/*
- * $Log: target.h,v $
- * Revision 1.77 2007/01/16 05:44:16 steve
- * Major rework of array handling. Memories are replaced with the
- * more general concept of arrays. The NetMemory and NetEMemory
- * classes are removed from the ivl core program, and the IVL_LPM_RAM
- * lpm type is removed from the ivl_target API.
- *
- * Revision 1.76 2006/11/10 05:44:45 steve
- * Process delay paths in second path over signals.
- *
- * Revision 1.75 2006/06/18 04:15:50 steve
- * Add support for system functions in continuous assignments.
- *
- * Revision 1.74 2005/07/11 16:56:51 steve
- * Remove NetVariable and ivl_variable_t structures.
- *
- * Revision 1.73 2005/07/07 16:22:49 steve
- * Generalize signals to carry types.
- *
- * Revision 1.72 2005/05/24 01:44:28 steve
- * Do sign extension of structuran nets.
- *
- * Revision 1.71 2005/02/08 00:12:36 steve
- * Add the NetRepeat node, and code generator support.
- *
- * Revision 1.70 2005/02/03 04:56:21 steve
- * laborate reduction gates into LPM_RED_ nodes.
- *
- * Revision 1.69 2005/01/24 05:28:31 steve
- * Remove the NetEBitSel and combine all bit/part select
- * behavior into the NetESelect node and IVL_EX_SELECT
- * ivl_target expression type.
- *
- * Revision 1.68 2005/01/22 01:06:55 steve
- * Change case compare from logic to an LPM node.
- *
- * Revision 1.67 2004/12/29 23:55:43 steve
- * Unify elaboration of l-values for all proceedural assignments,
- * including assing, cassign and force.
- *
- * Generate NetConcat devices for gate outputs that feed into a
- * vector results. Use this to hande gate arrays. Also let gate
- * arrays handle vectors of gates when the outputs allow for it.
- *
- * Revision 1.66 2004/12/11 02:31:28 steve
- * Rework of internals to carry vectors through nexus instead
- * of single bits. Make the ivl, tgt-vvp and vvp initial changes
- * down this path.
- *
- * Revision 1.65 2004/05/31 23:34:39 steve
- * Rewire/generalize parsing an elaboration of
- * function return values to allow for better
- * speed and more type support.
- *
- * Revision 1.64 2003/05/30 02:55:32 steve
- * Support parameters in real expressions and
- * as real expressions, and fix multiply and
- * divide with real results.
- *
- * Revision 1.63 2003/04/22 04:48:30 steve
- * Support event names as expressions elements.
- *
- * Revision 1.62 2003/03/10 23:40:54 steve
- * Keep parameter constants for the ivl_target API.
- *
- * Revision 1.61 2003/01/26 21:15:59 steve
- * Rework expression parsing and elaboration to
- * accommodate real/realtime values and expressions.
- *
- * Revision 1.60 2002/08/12 01:35:01 steve
- * conditional ident string using autoconfig.
- *
- * Revision 1.59 2002/06/05 03:44:25 steve
- * Add support for memory words in l-value of
- * non-blocking assignments, and remove the special
- * NetAssignMem_ and NetAssignMemNB classes.
- *
- * Revision 1.58 2002/06/04 05:38:44 steve
- * Add support for memory words in l-value of
- * blocking assignments, and remove the special
- * NetAssignMem class.
- *
- * Revision 1.57 2002/03/09 02:10:22 steve
- * Add the NetUserFunc netlist node.
- *
- * Revision 1.56 2002/01/28 00:52:41 steve
- * Add support for bit select of parameters.
- * This leads to a NetESelect node and the
- * vvp code generator to support that.
- *
- * Revision 1.55 2002/01/19 19:02:08 steve
- * Pass back target errors processing conditionals.
- *
- * Revision 1.54 2001/08/25 23:50:03 steve
- * Change the NetAssign_ class to refer to the signal
- * instead of link into the netlist. This is faster
- * and uses less space. Make the NetAssignNB carry
- * the delays instead of the NetAssign_ lval objects.
- *
- * Change the vvp code generator to support multiple
- * l-values, i.e. concatenations of part selects.
- *
- * Revision 1.53 2001/07/27 04:51:44 steve
- * Handle part select expressions as variants of
- * NetESignal/IVL_EX_SIGNAL objects, instead of
- * creating new and useless temporary signals.
- *
- * Revision 1.52 2001/04/22 23:09:46 steve
- * More UDP consolidation from Stephan Boettcher.
- */
#endif
View
9 tgt-vvp/vvp_scope.c
@@ -678,6 +678,7 @@ static char* draw_net_input_drive(ivl_nexus_t nex, ivl_nexus_ptr_t nptr)
case IVL_LPM_SUB:
case IVL_LPM_MULT:
case IVL_LPM_MUX:
+ case IVL_LPM_POW:
case IVL_LPM_DIVIDE:
case IVL_LPM_MOD:
case IVL_LPM_UFUNC:
@@ -1704,6 +1705,12 @@ static void draw_lpm_add(ivl_lpm_t net)
else
type = "mod";
break;
+ case IVL_LPM_POW:
+ if (dto == IVL_VT_REAL)
+ type = "pow.r";
+ else
+ assert(0); /* Not supported for bit based signals, */
+ break;
default:
assert(0);
}
@@ -2290,6 +2297,7 @@ static void draw_lpm_in_scope(ivl_lpm_t net)
case IVL_LPM_MULT:
case IVL_LPM_DIVIDE:
case IVL_LPM_MOD:
+ case IVL_LPM_POW:
draw_lpm_add(net);
return;
@@ -2477,4 +2485,3 @@ int draw_scope(ivl_scope_t net, ivl_scope_t parent)
ivl_scope_children(net, (ivl_scope_f*) draw_scope, net);
return 0;
}
-
View
19 vvp/arith.cc
@@ -26,6 +26,7 @@
#ifdef HAVE_MALLOC_H
# include <malloc.h>
#endif
+# include <math.h>
vvp_arith_::vvp_arith_(unsigned wid)
: wid_(wid), x_val_(wid)
@@ -770,6 +771,23 @@ void vvp_arith_mult_real::recv_real(vvp_net_ptr_t ptr, double bit)
vvp_send_real(ptr.ptr()->out, val);
}
+/* Real power. */
+vvp_arith_pow_real::vvp_arith_pow_real()
+{
+}
+
+vvp_arith_pow_real::~vvp_arith_pow_real()
+{
+}
+
+void vvp_arith_pow_real::recv_real(vvp_net_ptr_t ptr, double bit)
+{
+ dispatch_operand_(ptr, bit);
+
+ double val = pow(op_a_, op_b_);
+ vvp_send_real(ptr.ptr()->out, val);
+}
+
/* Real division. */
vvp_arith_div_real::vvp_arith_div_real()
{
@@ -884,4 +902,3 @@ void vvp_cmp_gt_real::recv_real(vvp_net_ptr_t ptr, const double bit)
vvp_send_vec4(ptr.ptr()->out, res);
}
-
View
8 vvp/arith.h
@@ -239,6 +239,14 @@ class vvp_arith_mult_real : public vvp_arith_real_ {
void recv_real(vvp_net_ptr_t ptr, double bit);
};
+class vvp_arith_pow_real : public vvp_arith_real_ {
+
+ public:
+ explicit vvp_arith_pow_real();
+ ~vvp_arith_pow_real();
+ void recv_real(vvp_net_ptr_t ptr, double bit);
+};
+
class vvp_arith_sub_real : public vvp_arith_real_ {
public:
View
13 vvp/compile.cc
@@ -983,6 +983,18 @@ void compile_arith_mult_r(char*label, unsigned argc, struct symb_s*argv)
make_arith(arith, label, argc, argv);
}
+void compile_arith_pow_r(char*label, unsigned argc, struct symb_s*argv)
+{
+ if (argc != 2) {
+ fprintf(stderr, "%s .arith/pow.r has wrong number of symbols\n", label);
+ compile_errors += 1;
+ return;
+ }
+
+ vvp_arith_real_ *arith = new vvp_arith_pow_real;
+ make_arith(arith, label, argc, argv);
+}
+
void compile_arith_sub(char*label, long wid, unsigned argc, struct symb_s*argv)
{
assert( wid > 0 );
@@ -1788,4 +1800,3 @@ void compile_param_string(char*label, char*name, char*value)
free(label);
}
-
View
1  vvp/compile.h
@@ -171,6 +171,7 @@ extern void compile_cmp_gt(char*label, long width, bool signed_flag,
extern void compile_arith_mult_r(char*label, unsigned argc,
struct symb_s*argv);
+extern void compile_arith_pow_r(char*label, unsigned argc, struct symb_s*argv);
extern void compile_arith_div_r(char*label, unsigned argc, struct symb_s*argv);
extern void compile_arith_sum_r(char*label, unsigned argc, struct symb_s*argv);
extern void compile_arith_sub_r(char*label, unsigned argc, struct symb_s*argv);
View
2  vvp/lexor.lex
@@ -93,6 +93,7 @@
".arith/mod" { return K_ARITH_MOD; }
".arith/mult" { return K_ARITH_MULT; }
".arith/mult.r" { return K_ARITH_MULT_R; }
+".arith/pow.r" { return K_ARITH_POW_R; }
".arith/sub" { return K_ARITH_SUB; }
".arith/sub.r" { return K_ARITH_SUB_R; }
".arith/sum" { return K_ARITH_SUM; }
@@ -237,4 +238,3 @@ int yywrap()
{
return -1;
}
-
View
8 vvp/parse.y
@@ -68,7 +68,7 @@ static struct __vpiModPath*modpath_dst = 0;
%token K_ALIAS K_ALIAS_S K_ALIAS_R
%token K_ARITH_DIV K_ARITH_DIV_R K_ARITH_DIV_S K_ARITH_MOD K_ARITH_MULT
%token K_ARITH_MULT_R K_ARITH_SUB K_ARITH_SUB_R K_ARITH_SUM K_ARITH_SUM_R
-%token K_ARRAY K_ARRAY_I K_ARRAY_R K_ARRAY_S K_ARRAY_PORT
+%token K_ARITH_POW_R K_ARRAY K_ARRAY_I K_ARRAY_R K_ARRAY_S K_ARRAY_PORT
%token K_CMP_EEQ K_CMP_EQ K_CMP_EQ_R K_CMP_NEE K_CMP_NE K_CMP_NE_R
%token K_CMP_GE K_CMP_GE_R K_CMP_GE_S K_CMP_GT K_CMP_GT_R K_CMP_GT_S
%token K_CONCAT K_DEBUG K_DELAY K_DFF
@@ -280,6 +280,11 @@ statement
compile_arith_mult_r($1, obj.cnt, obj.vect);
}
+ | T_LABEL K_ARITH_POW_R T_NUMBER ',' symbols ';'
+ { struct symbv_s obj = $5;
+ compile_arith_pow_r($1, obj.cnt, obj.vect);
+ }
+
| T_LABEL K_ARITH_SUB T_NUMBER ',' symbols ';'
{ struct symbv_s obj = $5;
compile_arith_sub($1, $3, obj.cnt, obj.vect);
@@ -891,4 +896,3 @@ int compile_design(const char*path)
int rc = yyparse();
return rc;
}
-
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