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Rework of internals to carry vectors through nexus instead

 of single bits. Make the ivl, tgt-vvp and vvp initial changes
 down this path.
  • Loading branch information...
commit 65e9b6be12840d1089d0ee069c2b76b575a7b59e 1 parent 6854660
steve authored
Showing with 3,400 additions and 3,120 deletions.
  1. +3 −3 Makefile.in
  2. +8 −2 Statement.h
  3. +20 −95 cprop.cc
  4. +36 −33 design_dump.cc
  5. +7 −2 dup_expr.cc
  6. +18 −2 elab_expr.cc
  7. +7 −4 elab_lval.cc
  8. +126 −74 elab_net.cc
  9. +12 −1 elab_sig.cc
  10. +98 −196 elaborate.cc
  11. +11 −139 emit.cc
  12. +32 −45 expr_synth.cc
  13. +1 −0  ivl.def
  14. +98 −14 ivl_target.h
  15. +10 −1 main.cc
  16. +44 −35 net_assign.cc
  17. +6 −102 net_force.cc
  18. +125 −95 netlist.cc
  19. +70 −73 netlist.h
  20. +11 −2 netmisc.cc
  21. +7 −2 pform.cc
  22. +6 −4 pform.h
  23. +7 −2 synth2.cc
  24. +81 −72 t-dll-api.cc
  25. +57 −181 t-dll-proc.cc
  26. +99 −95 t-dll.cc
  27. +21 −20 t-dll.h
  28. +13 −16 target.cc
  29. +8 −3 target.h
  30. +10 −2 targets.cc
  31. +86 −62 tgt-stub/stub.c
  32. +16 −2 tgt-vvp/draw_vpi.c
  33. +11 −16 tgt-vvp/eval_expr.c
  34. +7 −2 tgt-vvp/vvp_priv.h
  35. +78 −181 tgt-vvp/vvp_process.c
  36. +107 −61 tgt-vvp/vvp_scope.c
  37. +5 −4 vvp/Makefile.in
  38. +86 −51 vvp/README.txt
  39. +110 −220 vvp/arith.cc
  40. +24 −86 vvp/arith.h
  41. +10 −7 vvp/codes.h
  42. +154 −215 vvp/compile.cc
  43. +13 −4 vvp/compile.h
  44. +50 −147 vvp/event.cc
  45. +37 −25 vvp/event.h
  46. +41 −0 vvp/examples/assign_reg.vvp
  47. +35 −0 vvp/examples/set_reg.vvp
  48. +14 −78 vvp/force.cc
  49. +6 −10 vvp/functor.h
  50. +7 −1 vvp/lexor.lex
  51. +27 −88 vvp/logic.cc
  52. +12 −28 vvp/logic.h
  53. +30 −32 vvp/opcodes.txt
  54. +13 −6 vvp/parse.y
  55. +75 −0 vvp/part.cc
  56. +23 −23 vvp/resolv.cc
  57. +17 −35 vvp/resolv.h
  58. +73 −65 vvp/schedule.cc
  59. +10 −21 vvp/schedule.h
  60. +9 −2 vvp/symbols.h
  61. +10 −2 vvp/ufunc.cc
  62. +23 −173 vvp/vpi_callback.cc
  63. +7 −2 vvp/vpi_event.cc
  64. +13 −9 vvp/vpi_priv.h
  65. +40 −89 vvp/vpi_signal.cc
  66. +168 −58 vvp/vthread.cc
  67. +494 −0 vvp/vvp_net.cc
  68. +407 −0 vvp/vvp_net.h
View
6 Makefile.in
@@ -16,7 +16,7 @@
# 59 Temple Place - Suite 330
# Boston, MA 02111-1307, USA
#
-#ident "$Id: Makefile.in,v 1.169 2004/10/13 22:01:34 steve Exp $"
+#ident "$Id: Makefile.in,v 1.170 2004/12/11 02:31:25 steve Exp $"
#
#
SHELL = /bin/sh
@@ -104,8 +104,8 @@ distclean: clean
do (cd $$dir ; $(MAKE) $@); done
rm -f Makefile config.status config.log config.cache config.h
-TT = t-dll.o t-dll-api.o t-dll-expr.o t-dll-proc.o t-xnf.o
-FF = cprop.o nodangle.o synth.o synth2.o syn-rules.o xnfio.o
+TT = t-dll.o t-dll-api.o t-dll-expr.o t-dll-proc.o
+FF = cprop.o nodangle.o synth.o synth2.o syn-rules.o
O = main.o async.o design_dump.o dup_expr.o elaborate.o elab_expr.o \
elab_lval.o elab_net.o elab_anet.o elab_pexpr.o elab_scope.o \
View
10 Statement.h
@@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
-#ident "$Id: Statement.h,v 1.40 2004/02/20 18:53:33 steve Exp $"
+#ident "$Id: Statement.h,v 1.41 2004/12/11 02:31:25 steve Exp $"
#endif
# include <string>
@@ -36,6 +36,7 @@ class Design;
class NetAssign_;
class NetCAssign;
class NetDeassign;
+class NetForce;
class NetScope;
/*
@@ -345,7 +346,7 @@ class PForce : public Statement {
explicit PForce(PExpr*l, PExpr*r);
~PForce();
- virtual NetProc* elaborate(Design*des, NetScope*scope) const;
+ virtual NetForce* elaborate(Design*des, NetScope*scope) const;
virtual void dump(ostream&out, unsigned ind) const;
private:
@@ -456,6 +457,11 @@ class PWhile : public Statement {
/*
* $Log: Statement.h,v $
+ * Revision 1.41 2004/12/11 02:31:25 steve
+ * Rework of internals to carry vectors through nexus instead
+ * of single bits. Make the ivl, tgt-vvp and vvp initial changes
+ * down this path.
+ *
* Revision 1.40 2004/02/20 18:53:33 steve
* Addtrbute keys are perm_strings.
*
View
115 cprop.cc
@@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
-#ident "$Id: cprop.cc,v 1.47 2004/02/20 18:53:34 steve Exp $"
+#ident "$Id: cprop.cc,v 1.48 2004/12/11 02:31:25 steve Exp $"
#endif
# include "config.h"
@@ -55,86 +55,6 @@ void cprop_functor::signal(Design*des, NetNet*obj)
void cprop_functor::lpm_add_sub(Design*des, NetAddSub*obj)
{
- // For now, only additions are handled.
- if (obj->attribute(perm_string::literal("LPM_Direction")) != verinum("ADD"))
- return;
-
- // If the low bit on the A side is 0, then eliminate it from
- // the adder, and pass the B side directly to the
- // result. Don't reduce the adder smaller then a 1-bit
- // adder. These will be eliminated later.
- while ((obj->width() > 1)
- && obj->pin_DataA(0).nexus()->drivers_constant()
- && (obj->pin_DataA(0).nexus()->driven_value() == verinum::V0)) {
-
- NetAddSub*tmp = 0;
- tmp = new NetAddSub(obj->scope(), obj->name(), obj->width()-1);
- //connect(tmp->pin_Aclr(), obj->pin_Aclr());
- //connect(tmp->pin_Add_Sub(), obj->pin_Add_Sub());
- //connect(tmp->pin_Clock(), obj->pin_Clock());
- //connect(tmp->pin_Cin(), obj->pin_Cin());
- connect(tmp->pin_Cout(), obj->pin_Cout());
- //connect(tmp->pin_Overflow(), obj->pin_Overflow());
- for (unsigned idx = 0 ; idx < tmp->width() ; idx += 1) {
- connect(tmp->pin_DataA(idx), obj->pin_DataA(idx+1));
- connect(tmp->pin_DataB(idx), obj->pin_DataB(idx+1));
- connect(tmp->pin_Result(idx), obj->pin_Result(idx+1));
- }
- connect(obj->pin_Result(0), obj->pin_DataB(0));
- delete obj;
- des->add_node(tmp);
- obj = tmp;
- count += 1;
- }
-
- // Now do the same thing on the B side.
- while ((obj->width() > 1)
- && obj->pin_DataB(0).nexus()->drivers_constant()
- && (obj->pin_DataB(0).nexus()->driven_value() == verinum::V0)) {
-
- NetAddSub*tmp = 0;
- tmp = new NetAddSub(obj->scope(), obj->name(), obj->width()-1);
- //connect(tmp->pin_Aclr(), obj->pin_Aclr());
- //connect(tmp->pin_Add_Sub(), obj->pin_Add_Sub());
- //connect(tmp->pin_Clock(), obj->pin_Clock());
- //connect(tmp->pin_Cin(), obj->pin_Cin());
- connect(tmp->pin_Cout(), obj->pin_Cout());
- //connect(tmp->pin_Overflow(), obj->pin_Overflow());
- for (unsigned idx = 0 ; idx < tmp->width() ; idx += 1) {
- connect(tmp->pin_DataA(idx), obj->pin_DataA(idx+1));
- connect(tmp->pin_DataB(idx), obj->pin_DataB(idx+1));
- connect(tmp->pin_Result(idx), obj->pin_Result(idx+1));
- }
- connect(obj->pin_Result(0), obj->pin_DataA(0));
- delete obj;
- des->add_node(tmp);
- obj = tmp;
- count += 1;
- }
-
- // If the adder is only 1 bit wide, then replace it with the
- // simple logic gate.
- if (obj->width() == 1) {
- NetLogic*tmp;
- if (obj->pin_Cout().is_linked()) {
- tmp = new NetLogic(obj->scope(),
- obj->scope()->local_symbol(),
- 3, NetLogic::AND);
- connect(tmp->pin(0), obj->pin_Cout());
- connect(tmp->pin(1), obj->pin_DataA(0));
- connect(tmp->pin(2), obj->pin_DataB(0));
- des->add_node(tmp);
- }
- tmp = new NetLogic(obj->scope(), obj->name(), 3, NetLogic::XOR);
- connect(tmp->pin(0), obj->pin_Result(0));
- connect(tmp->pin(1), obj->pin_DataA(0));
- connect(tmp->pin(2), obj->pin_DataB(0));
- delete obj;
- des->add_node(tmp);
- count += 1;
- return;
- }
-
}
void cprop_functor::lpm_compare(Design*des, NetCompare*obj)
@@ -248,7 +168,7 @@ void cprop_functor::lpm_compare_eq_(Design*des, NetCompare*obj)
with a simple XOR gate. */
if (top == 1) {
NetLogic*tmp = new NetLogic(scope, obj->name(), 3,
- NetLogic::XNOR);
+ NetLogic::XNOR, 1);
connect(tmp->pin(0), obj->pin_AEB());
connect(tmp->pin(1), obj->pin_DataA(0));
connect(tmp->pin(2), obj->pin_DataB(0));
@@ -449,12 +369,12 @@ void cprop_functor::lpm_logic(Design*des, NetLogic*obj)
case NetLogic::AND:
tmp = new NetLogic(scope,
obj->name(), 2,
- NetLogic::BUF);
+ NetLogic::BUF, 1);
break;
case NetLogic::NAND:
tmp = new NetLogic(scope,
obj->name(), 2,
- NetLogic::NOT);
+ NetLogic::NOT, 1);
break;
default:
assert(0);
@@ -480,7 +400,7 @@ void cprop_functor::lpm_logic(Design*des, NetLogic*obj)
if (top < obj->pin_count()) {
NetLogic*tmp = new NetLogic(scope,
obj->name(), top,
- obj->type());
+ obj->type(), 1);
tmp->rise_time(obj->rise_time());
tmp->fall_time(obj->fall_time());
tmp->decay_time(obj->decay_time());
@@ -597,12 +517,12 @@ void cprop_functor::lpm_logic(Design*des, NetLogic*obj)
case NetLogic::OR:
tmp = new NetLogic(scope,
obj->name(), 2,
- NetLogic::BUF);
+ NetLogic::BUF, 1);
break;
case NetLogic::NOR:
tmp = new NetLogic(scope,
obj->name(), 2,
- NetLogic::NOT);
+ NetLogic::NOT, 1);
break;
default:
assert(0);
@@ -627,7 +547,7 @@ void cprop_functor::lpm_logic(Design*des, NetLogic*obj)
if (top < obj->pin_count()) {
NetLogic*tmp = new NetLogic(scope,
obj->name(), top,
- obj->type());
+ obj->type(), 1);
tmp->rise_time(obj->rise_time());
tmp->fall_time(obj->fall_time());
tmp->decay_time(obj->decay_time());
@@ -766,11 +686,11 @@ void cprop_functor::lpm_logic(Design*des, NetLogic*obj)
if (obj->type() == NetLogic::XOR)
tmp = new NetLogic(scope,
obj->name(), 2,
- NetLogic::NOT);
+ NetLogic::NOT, 1);
else
tmp = new NetLogic(scope,
obj->name(), 2,
- NetLogic::BUF);
+ NetLogic::BUF, 1);
tmp->rise_time(obj->rise_time());
tmp->fall_time(obj->fall_time());
@@ -795,11 +715,11 @@ void cprop_functor::lpm_logic(Design*des, NetLogic*obj)
if (obj->type() == NetLogic::XOR)
tmp = new NetLogic(scope,
obj->name(), 2,
- NetLogic::BUF);
+ NetLogic::BUF, 1);
else
tmp = new NetLogic(scope,
obj->name(), 2,
- NetLogic::NOT);
+ NetLogic::NOT, 1);
tmp->rise_time(obj->rise_time());
tmp->fall_time(obj->fall_time());
@@ -821,7 +741,7 @@ void cprop_functor::lpm_logic(Design*des, NetLogic*obj)
if (top < obj->pin_count()) {
NetLogic*tmp = new NetLogic(scope,
obj->name(), top,
- obj->type());
+ obj->type(), 1);
des->add_node(tmp);
tmp->pin(0).drive0(obj->pin(0).drive0());
tmp->pin(0).drive1(obj->pin(0).drive1());
@@ -873,7 +793,7 @@ void cprop_functor::lpm_mux(Design*des, NetMux*obj)
for (unsigned idx = 0 ; idx < obj->width() ; idx += 1) {
NetLogic*tmp = new NetLogic(obj->scope(),
scope->local_symbol(),
- 3, NetLogic::BUFIF1);
+ 3, NetLogic::BUFIF1, 1);
connect(obj->pin_Result(idx), tmp->pin(0));
connect(obj->pin_Data(idx,1), tmp->pin(1));
@@ -906,7 +826,7 @@ void cprop_functor::lpm_mux(Design*des, NetMux*obj)
for (unsigned idx = 0 ; idx < obj->width() ; idx += 1) {
NetLogic*tmp = new NetLogic(obj->scope(),
scope->local_symbol(),
- 3, NetLogic::BUFIF0);
+ 3, NetLogic::BUFIF0, 1);
connect(obj->pin_Result(idx), tmp->pin(0));
connect(obj->pin_Data(idx,0), tmp->pin(1));
@@ -1038,6 +958,11 @@ void cprop(Design*des)
/*
* $Log: cprop.cc,v $
+ * Revision 1.48 2004/12/11 02:31:25 steve
+ * Rework of internals to carry vectors through nexus instead
+ * of single bits. Make the ivl, tgt-vvp and vvp initial changes
+ * down this path.
+ *
* Revision 1.47 2004/02/20 18:53:34 steve
* Addtrbute keys are perm_strings.
*
View
69 design_dump.cc
@@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
-#ident "$Id: design_dump.cc,v 1.149 2004/10/04 01:10:52 steve Exp $"
+#ident "$Id: design_dump.cc,v 1.150 2004/12/11 02:31:25 steve Exp $"
#endif
# include "config.h"
@@ -96,8 +96,10 @@ void NetNet::dump_net(ostream&o, unsigned ind) const
o << " (eref=" << peek_eref() << ", lref=" << peek_lref() << ")";
if (scope())
o << " scope=" << scope()->name();
- o << " #(" << rise_time() << "," << fall_time() << "," <<
- decay_time() << ") init=";
+ o << " #(" << rise_time() << "," << fall_time() << ","
+ << decay_time() << ") vector_width=" << vector_width()
+ << " pin_count=" << pin_count()
+ << " init=";
for (unsigned idx = pin_count() ; idx > 0 ; idx -= 1)
o << pin(idx-1).get_init();
@@ -189,18 +191,13 @@ void NetObj::dump_obj_attr(ostream&o, unsigned ind) const
void NetAddSub::dump_node(ostream&o, unsigned ind) const
{
- o << setw(ind) << "" << "Adder (NetAddSub): " << name() << endl;
+ o << setw(ind) << "" << "Adder (NetAddSub): " << name()
+ << " width=" << width() << " pin_count=" << pin_count()
+ << endl;
dump_node_pins(o, ind+4);
dump_obj_attr(o, ind+4);
}
-void NetCAssign::dump_node(ostream&o, unsigned ind) const
-{
- o << setw(ind) << "" << "Procedural continuous assign (NetCAssign): "
- << name() << endl;
- dump_node_pins(o, ind+4);
-}
-
void NetCLShift::dump_node(ostream&o, unsigned ind) const
{
o << setw(ind) << "" << "Combinatorial shift (NetCLShift): " <<
@@ -223,12 +220,6 @@ void NetDivide::dump_node(ostream&o, unsigned ind) const
dump_obj_attr(o, ind+4);
}
-void NetForce::dump_node(ostream&o, unsigned ind) const
-{
- o << setw(ind) << "" << "force " << lval_->name() << endl;
- dump_node_pins(o, ind+4);
-}
-
void NetMult::dump_node(ostream&o, unsigned ind) const
{
o << setw(ind) << "" << "LPM_MULT (NetMult): " << name() << endl;
@@ -249,7 +240,7 @@ void NetBUFZ::dump_node(ostream&o, unsigned ind) const
o << setw(ind) << "" << "NetBUFZ: " << name()
<< " scope=" << (scope()? scope()->name() : "")
<< " delay=(" << rise_time() << "," << fall_time() << "," <<
- decay_time() << ")" << endl;
+ decay_time() << ") width=" << width() << endl;
dump_node_pins(o, ind+4);
}
@@ -261,8 +252,8 @@ void NetCaseCmp::dump_node(ostream&o, unsigned ind) const
void NetConst::dump_node(ostream&o, unsigned ind) const
{
- o << setw(ind) << "" << "constant ";
- for (unsigned idx = pin_count() ; idx > 0 ; idx -= 1)
+ o << setw(ind) << "" << "constant " << width_ << "'b";
+ for (unsigned idx = width_ ; idx > 0 ; idx -= 1)
o << value_[idx-1];
o << ": " << name() << endl;
dump_node_pins(o, ind+4);
@@ -353,6 +344,13 @@ void NetModulo::dump_node(ostream&o, unsigned ind) const
dump_obj_attr(o, ind+4);
}
+void NetPartSelect::dump_node(ostream&o, unsigned ind) const
+{
+ o << setw(ind) << "" << "NetPartSelect: "
+ << name() << " off=" << off_ << " wid=" << wid_ <<endl;
+ dump_node_pins(o, ind+4);
+ dump_obj_attr(o, ind+4);
+}
void NetRamDq::dump_node(ostream&o, unsigned ind) const
{
o << setw(ind) << "" << "LPM_RAM_DQ (" << mem_->name() << "): "
@@ -557,8 +555,9 @@ void NetCase::dump(ostream&o, unsigned ind) const
void NetCAssign::dump(ostream&o, unsigned ind) const
{
- o << setw(ind) << "" << "cassign " << lval_->name() << " = "
- << name() << ";" << endl;
+ o << setw(ind) << "" << "cassign ";
+ dump_lval(o);
+ o << " = " << *rval() << "; /* " << get_line() << " */" << endl;
}
void NetCondit::dump(ostream&o, unsigned ind) const
@@ -578,8 +577,9 @@ void NetCondit::dump(ostream&o, unsigned ind) const
void NetDeassign::dump(ostream&o, unsigned ind) const
{
- o << setw(ind) << "" << "deassign " << lval_->name() << "; "
- << "/* " << get_line() << " */" << endl;
+ o << setw(ind) << "" << "deassign ";
+ dump_lval(o);
+ o << "; /* " << get_line() << " */" << endl;
}
void NetDisable::dump(ostream&o, unsigned ind) const
@@ -632,8 +632,9 @@ void NetEvWait::dump(ostream&o, unsigned ind) const
void NetForce::dump(ostream&o, unsigned ind) const
{
- o << setw(ind) << "" << "force " << lval_->name() << " = "
- << name() << ";" << endl;
+ o << setw(ind) << "" << "force ";
+ dump_lval(o);
+ o << " = " << *rval() << "; /* " << get_line() << " */" << endl;
}
void NetForever::dump(ostream&o, unsigned ind) const
@@ -677,12 +678,9 @@ void NetPDelay::dump(ostream&o, unsigned ind) const
void NetRelease::dump(ostream&o, unsigned ind) const
{
- if (lval_)
- o << setw(ind) << "" << "release " << lval_->name() << "; "
- << "/* " << get_line() << " */" << endl;
- else
- o << setw(ind) << "" << "release (null); "
- << "/* " << get_line() << " */" << endl;
+ o << setw(ind) << "" << "release ";
+ dump_lval(o);
+ o << "; /* " << get_line() << " */" << endl;
}
void NetRepeat::dump(ostream&o, unsigned ind) const
@@ -995,7 +993,7 @@ void NetESignal::dump(ostream&o) const
{
if (has_sign())
o << "+";
- o << name() << "[" << msi_<<":"<<lsi_ << "]";
+ o << name() << "[" << msi()<<":"<<lsi() << "]";
}
void NetEBitSel::dump(ostream&o) const
@@ -1089,6 +1087,11 @@ void Design::dump(ostream&o) const
/*
* $Log: design_dump.cc,v $
+ * Revision 1.150 2004/12/11 02:31:25 steve
+ * Rework of internals to carry vectors through nexus instead
+ * of single bits. Make the ivl, tgt-vvp and vvp initial changes
+ * down this path.
+ *
* Revision 1.149 2004/10/04 01:10:52 steve
* Clean up spurious trailing white space.
*
View
9 dup_expr.cc
@@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
-#ident "$Id: dup_expr.cc,v 1.18 2004/06/17 16:06:18 steve Exp $"
+#ident "$Id: dup_expr.cc,v 1.19 2004/12/11 02:31:25 steve Exp $"
#endif
# include "config.h"
@@ -87,7 +87,7 @@ NetESFunc* NetESFunc::dup_expr() const
NetESignal* NetESignal::dup_expr() const
{
- NetESignal*tmp = new NetESignal(net_, msi_, lsi_);
+ NetESignal*tmp = new NetESignal(net_);
assert(tmp);
tmp->expr_width(expr_width());
return tmp;
@@ -143,6 +143,11 @@ NetEVariable* NetEVariable::dup_expr() const
/*
* $Log: dup_expr.cc,v $
+ * Revision 1.19 2004/12/11 02:31:25 steve
+ * Rework of internals to carry vectors through nexus instead
+ * of single bits. Make the ivl, tgt-vvp and vvp initial changes
+ * down this path.
+ *
* Revision 1.18 2004/06/17 16:06:18 steve
* Help system function signedness survive elaboration.
*
View
20 elab_expr.cc
@@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
-#ident "$Id: elab_expr.cc,v 1.91 2004/10/04 01:10:52 steve Exp $"
+#ident "$Id: elab_expr.cc,v 1.92 2004/12/11 02:31:25 steve Exp $"
#endif
# include "config.h"
@@ -699,10 +699,15 @@ NetExpr* PEIdent::elaborate_expr(Design*des, NetScope*scope,
delete msn;
return 0;
}
-
+#if 0
NetESignal*tmp = new NetESignal(net,
net->sb_to_idx(msv),
net->sb_to_idx(lsv));
+#else
+ NetESignal*tmp = new NetESignal(net);
+ cerr << get_line() << ": internal error: I forgot "
+ "how to elaborate part selects." << endl;
+#endif
tmp->set_line(*this);
return tmp;
@@ -735,7 +740,13 @@ NetExpr* PEIdent::elaborate_expr(Design*des, NetScope*scope,
return tmp;
}
+#if 0
NetESignal*tmp = new NetESignal(net, idx, idx);
+#else
+ NetESignal*tmp = new NetESignal(net);
+ cerr << get_line() << ": internal error: I forgot "
+ "how to elaborate constant bit selects." << endl;
+#endif
tmp->set_line(*this);
return tmp;
@@ -1005,6 +1016,11 @@ NetExpr* PEUnary::elaborate_expr(Design*des, NetScope*scope, bool) const
/*
* $Log: elab_expr.cc,v $
+ * Revision 1.92 2004/12/11 02:31:25 steve
+ * Rework of internals to carry vectors through nexus instead
+ * of single bits. Make the ivl, tgt-vvp and vvp initial changes
+ * down this path.
+ *
* Revision 1.91 2004/10/04 01:10:52 steve
* Clean up spurious trailing white space.
*
View
11 elab_lval.cc
@@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
-#ident "$Id: elab_lval.cc,v 1.29 2004/10/04 01:10:52 steve Exp $"
+#ident "$Id: elab_lval.cc,v 1.30 2004/12/11 02:31:25 steve Exp $"
#endif
# include "config.h"
@@ -283,7 +283,7 @@ NetAssign_* PEIdent::elaborate_lval(Design*des, NetScope*scope) const
converted to normalized form so is relative the
variable pins. */
- if ((wid + loff) > reg->pin_count()) {
+ if ((wid + loff) > reg->vector_width()) {
cerr << get_line() << ": error: bit/part select "
<< reg->name() << "[" << msb<<":"<<lsb<<"]"
<< " is out of range." << endl;
@@ -293,8 +293,6 @@ NetAssign_* PEIdent::elaborate_lval(Design*des, NetScope*scope) const
lv = new NetAssign_(reg);
lv->set_part(loff, wid);
-
- assert(moff < reg->pin_count());
}
@@ -352,6 +350,11 @@ NetAssign_* PENumber::elaborate_lval(Design*des, NetScope*) const
/*
* $Log: elab_lval.cc,v $
+ * Revision 1.30 2004/12/11 02:31:25 steve
+ * Rework of internals to carry vectors through nexus instead
+ * of single bits. Make the ivl, tgt-vvp and vvp initial changes
+ * down this path.
+ *
* Revision 1.29 2004/10/04 01:10:52 steve
* Clean up spurious trailing white space.
*
View
200 elab_net.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 1999-2003 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 1999-2004 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
-#ident "$Id: elab_net.cc,v 1.138 2004/10/04 03:09:38 steve Exp $"
+#ident "$Id: elab_net.cc,v 1.139 2004/12/11 02:31:25 steve Exp $"
#endif
# include "config.h"
@@ -195,14 +195,13 @@ NetNet* PEBinary::elaborate_net_add_(Design*des, NetScope*scope,
/* The owidth is the output width of the lpm_add_sub
device. If the desired width is greater then the width of
the operands, then widen the adder and let code below pad
- the operands. If this is an adder, we can take advantage of
- the carry bit. */
+ the operands. */
unsigned owidth = width;
switch (op_) {
case '+':
if (lwidth > owidth) {
owidth = lwidth;
- width = lwidth-1;
+ width = lwidth;
}
break;
case '-':
@@ -228,18 +227,21 @@ NetNet* PEBinary::elaborate_net_add_(Design*des, NetScope*scope,
osig = new NetNet(scope, scope->local_symbol(),
NetNet::WIRE, owidth);
osig->local_flag(true);
+ if (debug_elaborate) {
+ cerr << get_line() << ": debug: Elaborate NetAddSub "
+ << "width=" << width << " lwidth=" << lwidth
+ << endl;
+ }
NetAddSub*adder = new NetAddSub(scope, scope->local_symbol(), width);
// Connect the adder to the various parts.
- for (unsigned idx = 0 ; idx < lsig->pin_count() ; idx += 1)
- connect(lsig->pin(idx), adder->pin_DataA(idx));
- for (unsigned idx = 0 ; idx < rsig->pin_count() ; idx += 1)
- connect(rsig->pin(idx), adder->pin_DataB(idx));
- for (unsigned idx = 0 ; idx < width ; idx += 1)
- connect(osig->pin(idx), adder->pin_Result(idx));
+ connect(lsig->pin(0), adder->pin_DataA());
+ connect(rsig->pin(0), adder->pin_DataB());
+ connect(osig->pin(0), adder->pin_Result());
+#ifdef XXXX
if (owidth > width)
connect(osig->pin(width), adder->pin_Cout());
-
+#endif
NetNode*gate = adder;
gate->rise_time(rise);
gate->fall_time(fall);
@@ -311,7 +313,7 @@ NetNet* PEBinary::elaborate_net_bit_(Design*des, NetScope*scope,
for (unsigned idx = 0 ; idx < lsig->pin_count() ; idx += 1) {
NetLogic*gate = new NetLogic(scope, scope->local_symbol(),
- 3, gtype);
+ 3, gtype, 1);
connect(gate->pin(1), lsig->pin(idx));
connect(gate->pin(2), rsig->pin(idx));
connect(gate->pin(0), osig->pin(idx));
@@ -394,12 +396,12 @@ static NetNet* compare_eq_constant(Design*des, NetScope*scope,
NetLogic*ones_gate = 0;
if (zeros > 0)
zero_gate = new NetLogic(scope,
- scope->local_symbol(), zeros + 1,
- (op_code == 'n') ? NetLogic::OR : NetLogic::NOR);
+ scope->local_symbol(), zeros + 1,
+ (op_code == 'n') ? NetLogic::OR : NetLogic::NOR, 1);
if (ones > 0)
ones_gate = new NetLogic(scope,
- scope->local_symbol(), ones + 1,
- (op_code == 'n') ? NetLogic::NAND : NetLogic::AND);
+ scope->local_symbol(), ones + 1,
+ (op_code == 'n') ? NetLogic::NAND : NetLogic::AND, 1);
unsigned zidx = 0;
unsigned oidx = 0;
@@ -426,7 +428,7 @@ static NetNet* compare_eq_constant(Design*des, NetScope*scope,
connect(and_sig->pin(1), ones_gate->pin(0));
NetLogic*and_gate = new NetLogic(scope,
scope->local_symbol(), 3,
- (op_code == 'n') ? NetLogic::OR : NetLogic::AND);
+ (op_code == 'n') ? NetLogic::OR : NetLogic::AND, 1);
connect(and_gate->pin(0), osig->pin(0));
connect(and_gate->pin(1), and_sig->pin(0));
connect(and_gate->pin(2), and_sig->pin(1));
@@ -625,7 +627,7 @@ NetNet* PEBinary::elaborate_net_cmp_(Design*des, NetScope*scope,
gate = new NetLogic(scope, scope->local_symbol(),
1+dwidth,
- (op_ == 'E')? NetLogic::AND : NetLogic::NAND);
+ (op_ == 'E')? NetLogic::AND : NetLogic::NAND, 1);
connect(gate->pin(0), osig->pin(0));
for (unsigned idx = 0 ; idx < dwidth ; idx += 1) {
NetCaseCmp*cmp = new NetCaseCmp(scope,
@@ -659,7 +661,7 @@ NetNet* PEBinary::elaborate_net_cmp_(Design*des, NetScope*scope,
single XNOR gate. This is easy and direct. */
if (dwidth == 1) {
gate = new NetLogic(scope, scope->local_symbol(),
- 3, NetLogic::XNOR);
+ 3, NetLogic::XNOR, 1);
connect(gate->pin(0), osig->pin(0));
connect(gate->pin(1), lsig->pin(0));
connect(gate->pin(2), rsig->pin(0));
@@ -693,7 +695,7 @@ NetNet* PEBinary::elaborate_net_cmp_(Design*des, NetScope*scope,
single XOR gate. This is easy and direct. */
if (dwidth == 1) {
gate = new NetLogic(scope, scope->local_symbol(),
- 3, NetLogic::XOR);
+ 3, NetLogic::XOR, 1);
connect(gate->pin(0), osig->pin(0));
connect(gate->pin(1), lsig->pin(0));
connect(gate->pin(2), rsig->pin(0));
@@ -899,11 +901,11 @@ NetNet* PEBinary::elaborate_net_log_(Design*des, NetScope*scope,
switch (op_) {
case 'a':
gate = new NetLogic(scope, scope->local_symbol(),
- 3, NetLogic::AND);
+ 3, NetLogic::AND, 1);
break;
case 'o':
gate = new NetLogic(scope, scope->local_symbol(),
- 3, NetLogic::OR);
+ 3, NetLogic::OR, 1);
break;
default:
assert(0);
@@ -915,7 +917,7 @@ NetNet* PEBinary::elaborate_net_log_(Design*des, NetScope*scope,
// The first OR gate returns 1 if the left value is true...
if (lsig->pin_count() > 1) {
gate_t = new NetLogic(scope, scope->local_symbol(),
- 1+lsig->pin_count(), NetLogic::OR);
+ 1+lsig->pin_count(), NetLogic::OR, 1);
for (unsigned idx = 0 ; idx < lsig->pin_count() ; idx += 1)
connect(gate_t->pin(idx+1), lsig->pin(idx));
@@ -937,7 +939,7 @@ NetNet* PEBinary::elaborate_net_log_(Design*des, NetScope*scope,
// The second OR gate returns 1 if the right value is true...
if (rsig->pin_count() > 1) {
gate_t = new NetLogic(scope, scope->local_symbol(),
- 1+rsig->pin_count(), NetLogic::OR);
+ 1+rsig->pin_count(), NetLogic::OR, 1);
for (unsigned idx = 0 ; idx < rsig->pin_count() ; idx += 1)
connect(gate_t->pin(idx+1), rsig->pin(idx));
connect(gate->pin(2), gate_t->pin(0));
@@ -1586,7 +1588,7 @@ NetNet* PEIdent::elaborate_net(Design*des, NetScope*scope,
signal for the part select to be correct. */
if (! (sig->sb_is_valid(mbit) && sig->sb_is_valid(lbit))) {
cerr << get_line() << ": error: bit/part select ["
- << mval->as_long() << ":" << lval->as_long()
+ << mbit << ":" << lbit
<< "] out of range for " << sig->name() << endl;
des->errors += 1;
return sig;
@@ -1619,7 +1621,19 @@ NetNet* PEIdent::elaborate_net(Design*des, NetScope*scope,
unsigned part_count = midx-lidx+1;
- NetSubnet*tmp = new NetSubnet(sig, lidx, part_count);
+ if (debug_elaborate) {
+ cerr << get_line() << ": debug: Elaborate part select "
+ << sig->name() << "["<<mbit<<":"<<lbit<<"]" << endl;
+ }
+
+ NetPartSelect*ps = new NetPartSelect(sig, lidx, part_count);
+ ps->set_line(*sig);
+ des->add_node(ps);
+
+ NetNet*tmp = new NetNet(scope, scope->local_symbol(),
+ NetNet::WIRE, part_count-1, 0);
+ tmp->local_flag(true);
+ connect(tmp->pin(0), ps->pin(0));
sig = tmp;
@@ -1632,15 +1646,35 @@ NetNet* PEIdent::elaborate_net(Design*des, NetScope*scope,
}
assert(mval);
- unsigned idx = sig->sb_to_idx(mval->as_long());
- if (idx >= sig->pin_count()) {
- cerr << get_line() << ": error: index " << sig->name() <<
- "[" << mval->as_long() << "] out of range." << endl;
+ long mbit = mval->as_long();
+
+ /* Check that the part select is valid. Both ends of the
+ constant part select must be within the range of the
+ signal for the part select to be correct. */
+ if (! sig->sb_is_valid(mbit)) {
+ cerr << get_line() << ": error: bit/part select ["
+ << mbit
+ << "] out of range for " << sig->name() << endl;
des->errors += 1;
- idx = 0;
+ return sig;
}
- NetSubnet*tmp = new NetSubnet(sig, idx, 1);
+ unsigned midx = sig->sb_to_idx(mbit);
+
+ if (debug_elaborate) {
+ cerr << get_line() << ": debug: Elaborate part select "
+ << sig->name() << "["<<mval->as_long()<<"]" << endl;
+ }
+
+ NetPartSelect*ps = new NetPartSelect(sig, midx, 1);
+ ps->set_line(*sig);
+ des->add_node(ps);
+
+ NetNet*tmp = new NetNet(scope, scope->local_symbol(),
+ NetNet::WIRE, 1, 0);
+ tmp->local_flag(true);
+ connect(tmp->pin(0), ps->pin(0));
+
sig = tmp;
}
@@ -1698,7 +1732,10 @@ NetNet* PEIdent::elaborate_net_ram_(Design*des, NetScope*scope,
/*
* The concatenation is also OK an an l-value. This method elaborates
- * it as a structural l-value.
+ * it as a structural l-value. The return values is the *input* net of
+ * the l-value, which may feed via part selects to the final
+ * destination. The caller can connect gate outputs to this signal to
+ * make the l-value connections.
*/
NetNet* PEConcat::elaborate_lnet(Design*des, NetScope*scope,
bool implicit_net_ok) const
@@ -1706,7 +1743,7 @@ NetNet* PEConcat::elaborate_lnet(Design*des, NetScope*scope,
assert(scope);
svector<NetNet*>nets (parms_.count());
- unsigned pins = 0;
+ unsigned width = 0;
unsigned errors = 0;
if (repeat_) {
@@ -1718,6 +1755,12 @@ NetNet* PEConcat::elaborate_lnet(Design*des, NetScope*scope,
/* Elaborate the operands of the concatenation. */
for (unsigned idx = 0 ; idx < nets.count() ; idx += 1) {
+ if (debug_elaborate) {
+ cerr << get_line() << ": debug: Elaborate subexpression "
+ << idx << " of " << nets.count() << " l-values: "
+ << *parms_[idx] << endl;
+ }
+
if (parms_[idx] == 0) {
cerr << get_line() << ": error: Empty expressions "
<< "not allowed in concatenations." << endl;
@@ -1730,7 +1773,7 @@ NetNet* PEConcat::elaborate_lnet(Design*des, NetScope*scope,
if (nets[idx] == 0)
errors += 1;
else
- pins += nets[idx]->pin_count();
+ width += nets[idx]->vector_width();
}
/* If any of the sub expressions failed to elaborate, then
@@ -1745,19 +1788,33 @@ NetNet* PEConcat::elaborate_lnet(Design*des, NetScope*scope,
/* Make the temporary signal that connects to all the
operands, and connect it up. Scan the operands of the
- concat operator from least significant to most significant,
- which is opposite from how they are given in the list. */
+ concat operator from most significant to least significant,
+ which is the order they are given in the concat list. */
+
NetNet*osig = new NetNet(scope, scope->local_symbol(),
- NetNet::IMPLICIT, pins);
- pins = 0;
- for (unsigned idx = nets.count() ; idx > 0 ; idx -= 1) {
- NetNet*cur = nets[idx-1];
- for (unsigned pin = 0 ; pin < cur->pin_count() ; pin += 1) {
- connect(osig->pin(pins), cur->pin(pin));
- pins += 1;
- }
+ NetNet::IMPLICIT, width);
+
+
+ if (debug_elaborate) {
+ cerr << get_line() << ": debug: Generating part selects "
+ << "to connect input l-value to subexpressions."
+ << endl;
}
+ for (unsigned idx = 0 ; idx < nets.count() ; idx += 1) {
+ unsigned wid = nets[idx]->vector_width();
+ unsigned off = width - wid;
+ NetPartSelect*ps = new NetPartSelect(osig, off, wid);
+ des->add_node(ps);
+
+ connect(ps->pin(1), osig->pin(0));
+ connect(ps->pin(0), nets[idx]->pin(0));
+
+ assert(wid <= width);
+ width -= wid;
+ }
+ assert(width == 0);
+
osig->local_flag(true);
return osig;
}
@@ -2046,18 +2103,15 @@ NetNet* PENumber::elaborate_net(Design*des, NetScope*scope,
break;
}
- verinum num(top_v, net->pin_count());
+ verinum num(top_v, net->vector_width());
unsigned idx;
for (idx = 0 ; idx < num.len() && idx < value_->len(); idx += 1)
num.set(idx, value_->get(idx));
- NetConst*tmp = new NetConst(scope, scope->local_symbol(),
- num);
- for (idx = 0 ; idx < net->pin_count() ; idx += 1) {
- tmp->pin(idx).drive0(drive0);
- tmp->pin(idx).drive1(drive1);
- connect(net->pin(idx), tmp->pin(idx));
- }
+ NetConst*tmp = new NetConst(scope, scope->local_symbol(), num);
+ tmp->pin(0).drive0(drive0);
+ tmp->pin(0).drive1(drive1);
+ connect(net->pin(0), tmp->pin(0));
des->add_node(tmp);
return net;
@@ -2073,8 +2127,7 @@ NetNet* PENumber::elaborate_net(Design*des, NetScope*scope,
net->set_signed(value_->has_sign());
NetConst*tmp = new NetConst(scope, scope->local_symbol(),
*value_);
- for (unsigned idx = 0 ; idx < value_->len() ; idx += 1)
- connect(net->pin(idx), tmp->pin(idx));
+ connect(net->pin(0), tmp->pin(0));
des->add_node(tmp);
return net;
@@ -2116,8 +2169,7 @@ NetNet* PENumber::elaborate_net(Design*des, NetScope*scope,
NetNet::IMPLICIT, width);
net->local_flag(true);
NetConst*tmp = new NetConst(scope, scope->local_symbol(), num);
- for (unsigned idx = 0 ; idx < width ; idx += 1)
- connect(net->pin(idx), tmp->pin(idx));
+ connect(net->pin(0), tmp->pin(0));
des->add_node(tmp);
return net;
@@ -2224,7 +2276,7 @@ NetNet* PETernary::elaborate_net(Design*des, NetScope*scope,
if (expr_sig->pin_count() > 1) {
NetLogic*log = new NetLogic(scope, scope->local_symbol(),
expr_sig->pin_count()+1,
- NetLogic::OR);
+ NetLogic::OR, 1);
for (unsigned idx = 0; idx < expr_sig->pin_count(); idx += 1)
connect(log->pin(idx+1), expr_sig->pin(idx));
@@ -2284,7 +2336,7 @@ NetNet* PETernary::elaborate_net(Design*des, NetScope*scope,
NetNet::WIRE, dwidth);
for (unsigned idx = 0 ; idx < dwidth ; idx += 1) {
- NetBUFZ*tmpz = new NetBUFZ(scope, scope->local_symbol());
+ NetBUFZ*tmpz = new NetBUFZ(scope, scope->local_symbol(), 1);
tmpz->rise_time(rise);
tmpz->fall_time(fall);
tmpz->decay_time(decay);
@@ -2388,7 +2440,7 @@ NetNet* PEUnary::elaborate_net(Design*des, NetScope*scope,
sig->local_flag(true);
for (unsigned idx = 0 ; idx < sub_sig->pin_count() ; idx += 1) {
gate = new NetLogic(scope, scope->local_symbol(),
- 2, NetLogic::NOT);
+ 2, NetLogic::NOT, 1);
connect(gate->pin(1), sub_sig->pin(idx));
connect(gate->pin(0), sig->pin(idx));
des->add_node(gate);
@@ -2427,7 +2479,7 @@ NetNet* PEUnary::elaborate_net(Design*des, NetScope*scope,
case 1:
gate = new NetLogic(scope, scope->local_symbol(),
- 2, NetLogic::BUF);
+ 2, NetLogic::BUF, 1);
connect(gate->pin(0), sig->pin(0));
connect(gate->pin(1), sub_sig->pin(0));
des->add_node(gate);
@@ -2438,7 +2490,7 @@ NetNet* PEUnary::elaborate_net(Design*des, NetScope*scope,
case 2:
gate = new NetLogic(scope, scope->local_symbol(),
- 2, NetLogic::BUF);
+ 2, NetLogic::BUF, 1);
connect(gate->pin(0), sig->pin(0));
connect(gate->pin(1), sub_sig->pin(0));
des->add_node(gate);
@@ -2447,7 +2499,7 @@ NetNet* PEUnary::elaborate_net(Design*des, NetScope*scope,
gate->decay_time(decay);
gate = new NetLogic(scope, scope->local_symbol(),
- 3, NetLogic::XOR);
+ 3, NetLogic::XOR, 1);
connect(gate->pin(0), sig->pin(1));
connect(gate->pin(1), sub_sig->pin(0));
connect(gate->pin(2), sub_sig->pin(1));
@@ -2464,11 +2516,8 @@ NetNet* PEUnary::elaborate_net(Design*des, NetScope*scope,
des->add_node(sub);
- for (unsigned idx = 0 ; idx < sig->pin_count(); idx += 1)
- connect(sig->pin(idx), sub->pin_Result(idx));
-
- for (unsigned idx = 0; idx < sub_sig->pin_count(); idx += 1)
- connect(sub_sig->pin(idx), sub->pin_DataB(idx));
+ connect(sig->pin(0), sub->pin_Result());
+ connect(sub_sig->pin(0), sub->pin_DataB());
verinum tmp_num (verinum::V0, sub->width(), true);
NetConst*tmp_con = new NetConst(scope,
@@ -2481,10 +2530,8 @@ NetNet* PEUnary::elaborate_net(Design*des, NetScope*scope,
sub_sig->pin_count());
tmp_sig->local_flag(true);
- for (unsigned idx = 0; idx < sig->pin_count(); idx += 1) {
- connect(tmp_sig->pin(idx), sub->pin_DataA(idx));
- connect(tmp_sig->pin(idx), tmp_con->pin(idx));
- }
+ connect(tmp_sig->pin(0), sub->pin_DataA());
+ connect(tmp_sig->pin(0), tmp_con->pin(0));
break;
}
break;
@@ -2497,7 +2544,7 @@ NetNet* PEUnary::elaborate_net(Design*des, NetScope*scope,
sig = new NetNet(scope, scope->local_symbol(), NetNet::WIRE);
sig->local_flag(true);
gate = new NetLogic(scope, scope->local_symbol(),
- 1+sub_sig->pin_count(), gtype);
+ 1+sub_sig->pin_count(), gtype, 1);
connect(gate->pin(0), sig->pin(0));
for (unsigned idx = 0 ; idx < sub_sig->pin_count() ; idx += 1)
connect(gate->pin(idx+1), sub_sig->pin(idx));
@@ -2513,6 +2560,11 @@ NetNet* PEUnary::elaborate_net(Design*des, NetScope*scope,
/*
* $Log: elab_net.cc,v $
+ * Revision 1.139 2004/12/11 02:31:25 steve
+ * Rework of internals to carry vectors through nexus instead
+ * of single bits. Make the ivl, tgt-vvp and vvp initial changes
+ * down this path.
+ *
* Revision 1.138 2004/10/04 03:09:38 steve
* Fix excessive error message.
*
View
13 elab_sig.cc
@@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
-#ident "$Id: elab_sig.cc,v 1.36 2004/09/27 22:34:10 steve Exp $"
+#ident "$Id: elab_sig.cc,v 1.37 2004/12/11 02:31:25 steve Exp $"
#endif
# include "config.h"
@@ -610,6 +610,12 @@ void PWire::elaborate_sig(Design*des, NetScope*scope) const
} else {
perm_string name = lex_strings.make(hname_.peek_tail_name());
+ if (debug_elaborate) {
+ cerr << get_line() << ": debug: Create signal "
+ << name << "["<<msb<<":"<<lsb<<"]"
+ << " in scope " << scope->name() << endl;
+ }
+
NetNet*sig = new NetNet(scope, name, wtype, msb, lsb);
sig->set_line(*this);
sig->port_type(port_type_);
@@ -623,6 +629,11 @@ void PWire::elaborate_sig(Design*des, NetScope*scope) const
/*
* $Log: elab_sig.cc,v $
+ * Revision 1.37 2004/12/11 02:31:25 steve
+ * Rework of internals to carry vectors through nexus instead
+ * of single bits. Make the ivl, tgt-vvp and vvp initial changes
+ * down this path.
+ *
* Revision 1.36 2004/09/27 22:34:10 steve
* Cleanup and factoring of autoconf.
*
View
294 elaborate.cc
@@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
-#ident "$Id: elaborate.cc,v 1.308 2004/10/04 01:10:52 steve Exp $"
+#ident "$Id: elaborate.cc,v 1.309 2004/12/11 02:31:25 steve Exp $"
#endif
# include "config.h"
@@ -91,6 +91,12 @@ void PGAssign::elaborate(Design*des, NetScope*scope) const
return;
}
+ assert(lval->pin_count() == 1);
+
+ if (debug_elaborate) {
+ cerr << lval->get_line() << ": debug: Elaborated l-value "
+ << "width=" << lval->vector_width() << endl;
+ }
/* Handle the special case that the rval is simply an
identifier. Get the rval as a NetNet, then use NetBUFZ
@@ -98,7 +104,7 @@ void PGAssign::elaborate(Design*des, NetScope*scope) const
direct drivers. This is how I attach strengths to the
assignment operation. */
if (const PEIdent*id = dynamic_cast<const PEIdent*>(pin(1))) {
- NetNet*rid = id->elaborate_net(des, scope, lval->pin_count(),
+ NetNet*rid = id->elaborate_net(des, scope, lval->vector_width(),
0, 0, 0, Link::STRONG,
Link::STRONG);
if (rid == 0) {
@@ -107,7 +113,7 @@ void PGAssign::elaborate(Design*des, NetScope*scope) const
}
assert(rid);
-
+ assert(rid->pin_count() == 1);
/* If the right hand net is the same type as the left
side net (i.e., WIRE/WIRE) then it is enough to just
@@ -118,20 +124,16 @@ void PGAssign::elaborate(Design*des, NetScope*scope) const
is not as wide as the l-value by padding with a
constant-0. */
- unsigned cnt = lval->pin_count();
- if (rid->pin_count() < cnt)
+ unsigned cnt = lval->vector_width();
+ if (rid->vector_width() < cnt)
cnt = rid->pin_count();
bool need_driver_flag = false;
/* If the device is linked to itself, a driver is
needed. Should I print a warning here? */
- for (unsigned idx = 0 ; idx < cnt ; idx += 1) {
- if (lval->pin(idx) .is_linked (rid->pin(idx))) {
- need_driver_flag = true;
- break;
- }
- }
+ if (lval->pin(0) .is_linked (rid->pin(0)))
+ need_driver_flag = true;
/* If the nets are different type (i.e., reg vs. tri) then
a driver is needed. */
@@ -145,16 +147,12 @@ void PGAssign::elaborate(Design*des, NetScope*scope) const
/* If there is a strength to be carried, then I need a
driver to carry that strength. */
- for (unsigned idx = 0 ; idx < cnt ; idx += 1) {
- if (rid->pin(idx).drive0() != drive0) {
- need_driver_flag = true;
- break;
- }
- if (rid->pin(idx).drive1() != drive1) {
- need_driver_flag = true;
- break;
- }
- }
+ if (rid->pin(0).drive0() != drive0)
+ need_driver_flag = true;
+
+ if (rid->pin(0).drive1() != drive1)
+ need_driver_flag = true;
+
if (! need_driver_flag) {
/* Don't need a driver, presumably because the
@@ -162,11 +160,10 @@ void PGAssign::elaborate(Design*des, NetScope*scope) const
hook things up. If the r-value is too narrow
for the l-value, then sign extend it or zero
extend it, whichever makes sense. */
- unsigned idx;
- for (idx = 0 ; idx < cnt; idx += 1)
- connect(lval->pin(idx), rid->pin(idx));
+ connect(lval->pin(0), rid->pin(0));
if (cnt < lval->pin_count()) {
+#if 0
if (lval->get_signed() && rid->get_signed()) {
for (idx = cnt
; idx < lval->pin_count()
@@ -184,45 +181,28 @@ void PGAssign::elaborate(Design*des, NetScope*scope) const
; idx += 1)
connect(lval->pin(idx), tmp->pin(idx-cnt));
}
+#else
+ cerr << get_line() << ": internal error: "
+ << "Forgot how to handle mismatched widths."
+ << endl;
+#endif
}
} else {
/* Do need a driver. Use BUFZ objects to carry the
strength and delays. */
- unsigned idx;
- for (idx = 0 ; idx < cnt ; idx += 1) {
- NetBUFZ*dev = new NetBUFZ(scope,scope->local_symbol());
- connect(lval->pin(idx), dev->pin(0));
- connect(rid->pin(idx), dev->pin(1));
- dev->rise_time(rise_time);
- dev->fall_time(fall_time);
- dev->decay_time(decay_time);
- dev->pin(0).drive0(drive0);
- dev->pin(0).drive1(drive1);
- des->add_node(dev);
- }
- if (cnt < lval->pin_count()) {
- if (lval->get_signed() && rid->get_signed()) {
- for (idx = cnt
- ; idx < lval->pin_count()
- ; idx += 1)
- connect(lval->pin(idx), lval->pin(cnt-1));
-
- } else {
- NetConst*dev = new NetConst(scope,
- scope->local_symbol(),
- verinum::V0);
+ NetBUFZ*dev = new NetBUFZ(scope, scope->local_symbol(),
+ rid->vector_width());
+ connect(lval->pin(0), dev->pin(0));
+ connect(rid->pin(0), dev->pin(1));
+ dev->rise_time(rise_time);
+ dev->fall_time(fall_time);
+ dev->decay_time(decay_time);
+ dev->pin(0).drive0(drive0);
+ dev->pin(0).drive1(drive1);
+ des->add_node(dev);
- des->add_node(dev);
- dev->pin(0).drive0(drive0);
- dev->pin(0).drive1(drive1);
- for (idx = cnt
- ; idx < lval->pin_count()
- ; idx += 1)
- connect(lval->pin(idx), dev->pin(0));
- }
- }
}
return;
@@ -232,7 +212,7 @@ void PGAssign::elaborate(Design*des, NetScope*scope) const
which are going to be attached to the last gate before the
generated NetNet. */
NetNet*rval = pin(1)->elaborate_net(des, scope,
- lval->pin_count(),
+ lval->vector_width(),
rise_time, fall_time, decay_time,
drive0, drive1);
if (rval == 0) {
@@ -243,17 +223,16 @@ void PGAssign::elaborate(Design*des, NetScope*scope) const
}
assert(lval && rval);
-
+ assert(rval->pin_count() == 1);
/* If the r-value insists on being smaller then the l-value
(perhaps it is explicitly sized) the pad it out to be the
right width so that something is connected to all the bits
of the l-value. */
- if (lval->pin_count() > rval->pin_count())
- rval = pad_to_width(des, rval, lval->pin_count());
+ if (lval->vector_width() > rval->vector_width())
+ rval = pad_to_width(des, rval, lval->vector_width());
- for (unsigned idx = 0 ; idx < lval->pin_count() ; idx += 1)
- connect(lval->pin(idx), rval->pin(idx));
+ connect(lval->pin(0), rval->pin(0));
if (lval->local_flag())
delete lval;
@@ -355,75 +334,75 @@ void PGBuiltin::elaborate(Design*des, NetScope*scope) const
switch (type()) {
case AND:
cur[idx] = new NetLogic(scope, inm, pin_count(),
- NetLogic::AND);
+ NetLogic::AND, 1);
break;
case BUF:
cur[idx] = new NetLogic(scope, inm, pin_count(),
- NetLogic::BUF);
+ NetLogic::BUF, 1);
break;
case BUFIF0:
cur[idx] = new NetLogic(scope, inm, pin_count(),
- NetLogic::BUFIF0);
+ NetLogic::BUFIF0, 1);
break;
case BUFIF1:
cur[idx] = new NetLogic(scope, inm, pin_count(),
- NetLogic::BUFIF1);
+ NetLogic::BUFIF1, 1);
break;
case NAND:
cur[idx] = new NetLogic(scope, inm, pin_count(),
- NetLogic::NAND);
+ NetLogic::NAND, 1);
break;
case NMOS:
cur[idx] = new NetLogic(scope, inm, pin_count(),
- NetLogic::NMOS);
+ NetLogic::NMOS, 1);
break;
case NOR:
cur[idx] = new NetLogic(scope, inm, pin_count(),
- NetLogic::NOR);
+ NetLogic::NOR, 1);
break;
case NOT:
cur[idx] = new NetLogic(scope, inm, pin_count(),
- NetLogic::NOT);
+ NetLogic::NOT, 1);
break;
case NOTIF0:
cur[idx] = new NetLogic(scope, inm, pin_count(),
- NetLogic::NOTIF0);
+ NetLogic::NOTIF0, 1);
break;
case NOTIF1:
cur[idx] = new NetLogic(scope, inm, pin_count(),
- NetLogic::NOTIF1);
+ NetLogic::NOTIF1, 1);
break;
case OR:
cur[idx] = new NetLogic(scope, inm, pin_count(),
- NetLogic::OR);
+ NetLogic::OR, 1);
break;
case RNMOS:
cur[idx] = new NetLogic(scope, inm, pin_count(),
- NetLogic::RNMOS);
+ NetLogic::RNMOS, 1);
break;
case RPMOS:
cur[idx] = new NetLogic(scope, inm, pin_count(),
- NetLogic::RPMOS);
+ NetLogic::RPMOS, 1);
break;
case PMOS:
cur[idx] = new NetLogic(scope, inm, pin_count(),
- NetLogic::PMOS);
+ NetLogic::PMOS, 1);
break;
case PULLDOWN:
cur[idx] = new NetLogic(scope, inm, pin_count(),
- NetLogic::PULLDOWN);
+ NetLogic::PULLDOWN, 1);
break;
case PULLUP:
cur[idx] = new NetLogic(scope, inm, pin_count(),
- NetLogic::PULLUP);
+ NetLogic::PULLUP, 1);
break;
case XNOR:
cur[idx] = new NetLogic(scope, inm, pin_count(),
- NetLogic::XNOR);
+ NetLogic::XNOR, 1);
break;
case XOR:
cur[idx] = new NetLogic(scope, inm, pin_count(),
- NetLogic::XOR);
+ NetLogic::XOR, 1);
break;
default:
cerr << get_line() << ": internal error: unhandled "
@@ -1712,29 +1691,36 @@ NetProc* PCallTask::elaborate_usr(Design*des, NetScope*scope) const
return block;
}
+/*
+ * Elaborate a proceedural continuous assign. This really looks very
+ * much like other prodeedural assignments, at this point, but there
+ * is no delay to worry about. The code generator will take care of
+ * the differences between continuous assign and normal assignments.
+ */
NetCAssign* PCAssign::elaborate(Design*des, NetScope*scope) const
{
+ NetCAssign*dev = 0;
assert(scope);
- NetNet*lval = lval_->elaborate_anet(des, scope);
+ NetAssign_*lval = lval_->elaborate_lval(des, scope);
if (lval == 0)
return 0;
- NetNet*rval = expr_->elaborate_net(des, scope, lval->pin_count(),
- 0, 0, 0);
- if (rval == 0)
+ NetExpr*rexp = elab_and_eval(des, scope, expr_);
+ if (rexp == 0)
return 0;
- if (rval->pin_count() < lval->pin_count())
- rval = pad_to_width(des, rval, lval->pin_count());
-
- NetCAssign* dev = new NetCAssign(scope, scope->local_symbol(), lval);
- dev->set_line(*this);
- des->add_node(dev);
+ dev = new NetCAssign(lval, rexp);
- for (unsigned idx = 0 ; idx < dev->pin_count() ; idx += 1)
- connect(dev->pin(idx), rval->pin(idx));
+ if (debug_elaborate) {
+ cerr << get_line() << ": debug: ELaborate cassign,"
+ << " lval width=" << lval->lwidth()
+ << " rval width=" << rexp->expr_width()
+ << " rval=" << *rexp
+ << endl;
+ }
+ dev->set_line(*this);
return dev;
}
@@ -1742,7 +1728,7 @@ NetDeassign* PDeassign::elaborate(Design*des, NetScope*scope) const
{
assert(scope);
- NetNet*lval = lval_->elaborate_anet(des, scope);
+ NetAssign_*lval = lval_->elaborate_lval(des, scope);
if (lval == 0)
return 0;
@@ -2225,28 +2211,30 @@ NetProc* PForever::elaborate(Design*des, NetScope*scope) const
return proc;
}
-NetProc* PForce::elaborate(Design*des, NetScope*scope) const
+NetForce* PForce::elaborate(Design*des, NetScope*scope) const
{
+ NetForce*dev = 0;
assert(scope);
- NetNet*lval = lval_->elaborate_net(des, scope, 0, 0, 0, 0);
+ NetAssign_*lval = lval_->elaborate_lval(des, scope);
if (lval == 0)
return 0;
- NetNet*rval = expr_->elaborate_net(des, scope, lval->pin_count(),
- 0, 0, 0);
- if (rval == 0)
+ NetExpr*rexp = elab_and_eval(des, scope, expr_);
+ if (rexp == 0)
return 0;
- if (rval->pin_count() < lval->pin_count())
- rval = pad_to_width(des, rval, lval->pin_count());
+ dev = new NetForce(lval, rexp);
- NetForce* dev = new NetForce(scope, scope->local_symbol(), lval);
- des->add_node(dev);
-
- for (unsigned idx = 0 ; idx < dev->pin_count() ; idx += 1)
- connect(dev->pin(idx), rval->pin(idx));
+ if (debug_elaborate) {
+ cerr << get_line() << ": debug: ELaborate force,"
+ << " lval width=" << lval->lwidth()
+ << " rval width=" << rexp->expr_width()
+ << " rval=" << *rexp
+ << endl;
+ }
+ dev->set_line(*this);
return dev;
}
@@ -2398,7 +2386,7 @@ NetProc* PRelease::elaborate(Design*des, NetScope*scope) const
{
assert(scope);
- NetNet*lval = lval_->elaborate_net(des, scope, 0, 0, 0, 0);
+ NetAssign_*lval = lval_->elaborate_lval(des, scope);
if (lval == 0)
return 0;
@@ -2769,96 +2757,10 @@ Design* elaborate(list<perm_string>roots)
/*
* $Log: elaborate.cc,v $
- * Revision 1.308 2004/10/04 01:10:52 steve
- * Clean up spurious trailing white space.
- *
- * Revision 1.307 2004/09/05 21:07:26 steve
- * Support degenerat wait statements.
- *
- * Revision 1.306 2004/09/05 17:44:41 steve
- * Add support for module instance arrays.
- *
- * Revision 1.305 2004/06/30 15:32:02 steve
- * Propagate source line number in synthetic delay statements.
- *
- * Revision 1.304 2004/06/20 15:59:06 steve
- * Only pad the width of vector r-values.
- *
- * Revision 1.303 2004/06/13 04:56:54 steve
- * Add support for the default_nettype directive.
- *
- * Revision 1.302 2004/05/31 23:34:37 steve
- * Rewire/generalize parsing an elaboration of
- * function return values to allow for better
- * speed and more type support.
- *
- * Revision 1.301 2004/05/25 03:42:58 steve
- * Handle wait with constant-false expression.
- *
- * Revision 1.300 2004/03/08 00:47:44 steve
- * primitive ports can bind bi name.
- *
- * Revision 1.299 2004/03/08 00:10:29 steve
- * Verilog2001 new style port declartions for primitives.
- *
- * Revision 1.298 2004/03/07 20:04:10 steve
- * MOre thorough use of elab_and_eval function.
- *
- * Revision 1.297 2004/02/20 18:53:34 steve
- * Addtrbute keys are perm_strings.
- *
- * Revision 1.296 2004/02/18 17:11:55 steve
- * Use perm_strings for named langiage items.
- *
- * Revision 1.295 2004/01/21 04:35:03 steve
- * Get rid of useless warning.
- *
- * Revision 1.294 2004/01/13 03:42:49 steve
- * Handle wide expressions in wait condition.
- *
- * Revision 1.293 2003/10/26 04:49:51 steve
- * Attach line number information to for loop parts.
- *
- * Revision 1.292 2003/09/25 00:25:14 steve
- * Summary list of missing modules.
- *
- * Revision 1.291 2003/09/20 06:08:53 steve
- * Evaluate nb-assign r-values using elab_and_eval.
- *
- * Revision 1.290 2003/09/20 06:00:37 steve
- * Evaluate gate array index constants using elab_and_eval.
- *
- * Revision 1.289 2003/09/20 01:05:35 steve
- * Obsolete find_symbol and find_event from the Design class.
- *
- * Revision 1.288 2003/09/13 01:01:51 steve
- * Spelling fixes.
- *
- * Revision 1.287 2003/09/04 20:28:05 steve
- * Support time0 resolution of combinational threads.
- *
- * Revision 1.286 2003/08/28 04:11:17 steve
- * Spelling patch.
- *
- * Revision 1.285 2003/08/05 03:01:58 steve
- * Primitive outputs have same limitations as continuous assignment.
- *
- * Revision 1.284 2003/07/02 04:19:16 steve
- * Elide empty begin-end in conditionals.
- *
- * Revision 1.283 2003/06/21 01:21:43 steve
- * Harmless fixup of warnings.
- *
- * Revision 1.282 2003/06/13 19:10:20 steve
- * Handle assign of real to vector.
- *
- * Revision 1.281 2003/05/19 02:50:58 steve
- * Implement the wait statement behaviorally instead of as nets.
- *
- * Revision 1.280 2003/05/04 20:04:08 steve
- * Fix truncation of signed constant in constant addition.
+ * Revision 1.309 2004/12/11 02:31:25 steve
+ * Rework of internals to carry vectors through nexus instead
+ * of single bits. Make the ivl, tgt-vvp and vvp initial changes
+ * down this path.
*
- * Revision 1.279 2003/04/24 05:25:55 steve
- * Include port name in port assignment error message.
*/
View
150 emit.cc
@@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
-#ident "$Id: emit.cc,v 1.77 2004/10/04 01:10:53 steve Exp $"
+#ident "$Id: emit.cc,v 1.78 2004/12/11 02:31:26 steve Exp $"
#endif
# include "config.h"
@@ -63,12 +63,6 @@ bool NetCaseCmp::emit_node(struct target_t*tgt) const
return true;
}
-bool NetCAssign::emit_node(struct target_t*tgt) const
-{
- tgt->net_cassign(this);
- return true;
-}
-
bool NetCLShift::emit_node(struct target_t*tgt) const
{
tgt->lpm_clshift(this);
@@ -98,12 +92,6 @@ bool NetFF::emit_node(struct target_t*tgt) const
return true;
}
-bool NetForce::emit_node(struct target_t*tgt) const
-{
- tgt->net_force(this);
- return true;
-}
-
bool NetModulo::emit_node(struct target_t*tgt) const
{
tgt->lpm_modulo(this);
@@ -122,6 +110,11 @@ bool NetMux::emit_node(struct target_t*tgt) const
return true;
}
+bool NetPartSelect::emit_node(struct target_t*tgt) const
+{
+ return tgt->part_select(this);
+}
+
bool NetRamDq::emit_node(struct target_t*tgt) const
{
tgt->lpm_ram_dq(this);
@@ -511,6 +504,11 @@ bool emit(const Design*des, const char*type)
/*
* $Log: emit.cc,v $
+ * Revision 1.78 2004/12/11 02:31:26 steve
+ * Rework of internals to carry vectors through nexus instead
+ * of single bits. Make the ivl, tgt-vvp and vvp initial changes
+ * down this path.
+ *
* Revision 1.77 2004/10/04 01:10:53 steve
* Clean up spurious trailing white space.
*
@@ -536,131 +534,5 @@ bool emit(const Design*des, const char*type)
* Revision 1.71 2003/01/26 21:15:58 steve
* Rework expression parsing and elaboration to
* accommodate real/realtime values and expressions.
- *
- * Revision 1.70 2002/11/03 20:36:10 steve
- * Error message for mising code generator type.
- *
- * Revision 1.69 2002/08/12 01:34:59 steve
- * conditional ident string using autoconfig.
- *
- * Revision 1.68 2002/06/05 03:44:25 steve
- * Add support for memory words in l-value of
- * non-blocking assignments, and remove the special
- * NetAssignMem_ and NetAssignMemNB classes.
- *
- * Revision 1.67 2002/06/04 05:38:44 steve
- * Add support for memory words in l-value of
- * blocking assignments, and remove the special
- * NetAssignMem class.
- *
- * Revision 1.66 2002/03/09 02:10:22 steve
- * Add the NetUserFunc netlist node.
- *
- * Revision 1.65 2002/01/28 00:52:41 steve
- * Add support for bit select of parameters.
- * This leads to a NetESelect node and the
- * vvp code generator to support that.
- *
- * Revision 1.64 2002/01/19 19:02:08 steve
- * Pass back target errors processing conditionals.
- *
- * Revision 1.63 2001/10/19 21:53:24 steve
- * Support multiple root modules (Philip Blundell)
- *
- * Revision 1.62 2001/08/25 23:50:02 steve
- * Change the NetAssign_ class to refer to the signal
- * instead of link into the netlist. This is faster
- * and uses less space. Make the NetAssignNB carry
- * the delays instead of the NetAssign_ lval objects.
- *
- * Change the vvp code generator to support multiple
- * l-values, i.e. concatenations of part selects.
- *
- * Revision 1.61 2001/07/27 04:51:44 steve
- * Handle part select expressions as variants of
- * NetESignal/IVL_EX_SIGNAL objects, instead of
- * creating new and useless temporary signals.
- *
- * Revision 1.60 2001/07/25 03:10:49 steve
- * Create a config.h.in file to hold all the config
- * junk, and support gcc 3.0. (Stephan Boettcher)
- *
- * Revision 1.59 2001/04/22 23:09:46 steve
- * More UDP consolidation from Stephan Boettcher.
- *
- * Revision 1.58 2001/04/06 02:28:02 steve
- * Generate vvp code for functions with ports.
- *
- * Revision 1.57 2001/04/02 02:28:12 steve
- * Generate code for task calls.
- *
- * Revision 1.56 2001/03/27 03:31:06 steve
- * Support error code from target_t::end_design method.
- *
- * Revision 1.55 2000/11/04 01:54:01 steve
- * Modifications in support of gcc 2.96
- *
- * Revision 1.54 2000/09/26 01:35:42 steve
- * Remove the obsolete NetEIdent class.
- *
- * Revision 1.53 2000/09/17 21:26:15 steve
- * Add support for modulus (Eric Aardoom)
- *
- * Revision 1.52 2000/09/02 20:54:20 steve
- * Rearrange NetAssign to make NetAssign_ separate.
- *
- * Revision 1.51 2000/08/14 04:39:56 steve
- * add th t-dll functions for net_const, net_bufz and processes.
- *
- * Revision 1.50 2000/08/09 03:43:45 steve
- * Move all file manipulation out of target class.
- *
- * Revision 1.49 2000/08/08 01:50:42 steve
- * target methods need not take a file stream.
- *
- * Revision 1.48 2000/07/30 18:25:43 steve
- * Rearrange task and function elaboration so that the
- * NetTaskDef and NetFuncDef functions are created during
- * signal enaboration, and carry these objects in the
- * NetScope class instead of the extra, useless map in
- * the Design class.
- *
- * Revision 1.47 2000/07/29 16:21:08 steve
- * Report code generation errors through proc_delay.
- *
- * Revision 1.46 2000/07/27 05:13:44 steve
- * Support elaboration of disable statements.
- *
- * Revision 1.45 2000/05/11 23:37:27 steve
- * Add support for procedural continuous assignment.
- *
- * Revision 1.44 2000/05/04 03:37:58 steve
- * Add infrastructure for system functions, move
- * $time to that structure and add $random.
- *
- * Revision 1.43 2000/05/02 03:13:31 steve
- * Move memories to the NetScope object.
- *
- * Revision 1.42 2000/05/02 00:58:12 steve
- * Move signal tables to the NetScope class.
- *
- * Revision 1.41 2000/04/23 03:45:24 steve
- * Add support for the procedural release statement.
- *
- * Revision 1.40 2000/04/22 04:20:19 steve
- * Add support for force assignment.
- *
- * Revision 1.39 2000/04/12 04:23:58 steve
- * Named events really should be expressed with PEIdent
- * objects in the pform,
- *
- * Handle named events within the mix of net events
- * and edges. As a unified lot they get caught together.
- * wait statements are broken into more complex statements
- * that include a conditional.
- *
- * Do not generate NetPEvent or NetNEvent objects in
- * elaboration. NetEvent, NetEvWait and NetEvProbe
- * take over those functions in the netlist.
*/
View
77 expr_synth.cc
@@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
-#ident "$Id: expr_synth.cc,v 1.59 2004/06/30 02:16:26 steve Exp $"
+#ident "$Id: expr_synth.cc,v 1.60 2004/12/11 02:31:26 steve Exp $"
#endif
# include "config.h"
@@ -60,11 +60,9 @@ NetNet* NetEBAdd::synthesize(Design*des)
perm_string oname = osig->scope()->local_symbol();
NetAddSub *adder = new NetAddSub(lsig->scope(), oname, width);
- for (unsigned idx = 0 ; idx < width; idx += 1) {
- connect(lsig->pin(idx), adder->pin_DataA(idx));
- connect(rsig->pin(idx), adder->pin_DataB(idx));
- connect(osig->pin(idx), adder->pin_Result(idx));
- }
+ connect(lsig->pin(0), adder->pin_DataA());
+ connect(rsig->pin(0), adder->pin_DataB());
+ connect(osig->pin(0), adder->pin_Result());
des->add_node(adder);
switch (op()) {
@@ -136,19 +134,19 @@ NetNet* NetEBBits::synthesize(Design*des)
switch (op()) {
case '&':
- gate = new NetLogic(scope, oname, 3, NetLogic::AND);
+ gate = new NetLogic(scope, oname, 3, NetLogic::AND, 1);
break;
case '|':
- gate = new NetLogic(scope, oname, 3, NetLogic::OR);
+ gate = new NetLogic(scope, oname, 3, NetLogic::OR, 1);
break;
case '^':
- gate = new NetLogic(scope, oname, 3, NetLogic::XOR);
+ gate = new NetLogic(scope, oname, 3, NetLogic::XOR, 1);
break;
case 'O':
- gate = new NetLogic(scope, oname, 3, NetLogic::NOR);
+ gate = new NetLogic(scope, oname, 3, NetLogic::NOR, 1);
break;
case 'X':
- gate = new NetLogic(scope, oname, 3, NetLogic::XNOR);
+ gate = new NetLogic(scope, oname, 3, NetLogic::XNOR, 1);
break;
default:
assert(0);
@@ -191,12 +189,12 @@ NetNet* NetEBComp::synthesize(Design*des)
case 'e':
case 'E':
gate = new NetLogic(scope, scope->local_symbol(),
- lsig->pin_count()+1, NetLogic::NOR);
+ lsig->pin_count()+1, NetLogic::NOR, 1);
break;
case 'n':
case 'N':
gate = new NetLogic(scope, scope->local_symbol(),
- lsig->pin_count()+1, NetLogic::OR);
+ lsig->pin_count()+1, NetLogic::OR, 1);
break;
case '>':
@@ -205,11 +203,11 @@ NetNet* NetEBComp::synthesize(Design*des)
happen. */
if (rcon) {
gate = new NetLogic(scope, scope->local_symbol(),
- lsig->pin_count()+1, NetLogic::OR);
+ lsig->pin_count()+1, NetLogic::OR, 1);
} else {
assert(0);
gate = new NetLogic(scope, scope->local_symbol(),
- lsig->pin_count()+1, NetLogic::NOR);
+ lsig->pin_count()+1, NetLogic::NOR, 1);
}
break;
@@ -217,11 +215,11 @@ NetNet* NetEBComp::synthesize(Design*des)
/* 0 < sig is handled like sig > 0. */
if (! rcon) {
gate = new NetLogic(scope, scope->local_symbol(),
- lsig->pin_count()+1, NetLogic::OR);
+ lsig->pin_count()+1, NetLogic::OR, 1);
} else {
assert(0);
gate = new NetLogic(scope, scope->local_symbol(),
- lsig->pin_count()+1, NetLogic::NOR);
+ lsig->pin_count()+1, NetLogic::NOR, 1);
}
break;
@@ -258,7 +256,7 @@ NetNet* NetEBComp::synthesize(Design*des)
operation. Make an XNOR gate instead of a comparator. */
if ((width == 1) && ((op_ == 'e') || (op_ == 'E'))) {
NetLogic*gate = new NetLogic(scope, scope->local_symbol(),
- 3, NetLogic::XNOR);
+ 3, NetLogic::XNOR, 1);
connect(gate->pin(0), osig->pin(0));
connect(gate->pin(1), lsig->pin(0));
connect(gate->pin(2), rsig->pin(0));
@@ -271,7 +269,7 @@ NetNet* NetEBComp::synthesize(Design*des)
an XOR instead of an XNOR gate. */
if ((width == 1) && ((op_ == 'n') || (op_ == 'N'))) {
NetLogic*gate = new NetLogic(scope, scope->local_symbol(),
- 3, NetLogic::XOR);
+ 3, NetLogic::XOR, 1);
connect(gate->pin(0), osig->pin(0));
connect(gate->pin(1), lsig->pin(0));
connect(gate->pin(2), rsig->pin(0));
@@ -449,7 +447,7 @@ NetNet* NetEBLogic::synthesize(Design*des)
NetLogic*olog = new NetLogic(scope, oname,
lsig->pin_count()+rsig->pin_count()+1,
- NetLogic::OR);
+ NetLogic::OR, 1);
connect(osig->pin(0), olog->pin(0));
@@ -471,7 +469,7 @@ NetNet* NetEBLogic::synthesize(Design*des)
NetLogic*olog;
perm_string oname = scope->local_symbol();
- olog = new NetLogic(scope, oname, 3, NetLogic::AND);
+ olog = new NetLogic(scope, oname, 3, NetLogic::AND, 1);
connect(osig->pin(0), olog->pin(0));
des->add_node(olog);
@@ -669,7 +667,7 @@ NetNet* NetEUBits::synthesize(Design*des)
switch (op()) {
case '~':
- gate = new NetLogic(scope, oname, 2, NetLogic::NOT);
+ gate = new NetLogic(scope, oname, 2, NetLogic::NOT, 1);
break;
default:
assert(0);
@@ -702,32 +700,32 @@ NetNet* NetEUReduce::synthesize(Design*des)
case 'N':
case '!':
gate = new NetLogic(scope, oname, isig->pin_count()+1,
- NetLogic::NOR);
+ NetLogic::NOR, 1);
break;
case '&':
gate = new NetLogic(scope, oname, isig->pin_count()+1,
- NetLogic::AND);
+ NetLogic::AND, 1);
break;
case '|':
gate = new NetLogic(scope, oname, isig->pin_count()+1,
- NetLogic::OR);
+ NetLogic::OR, 1);
break;
case '^':
gate = new NetLogic(scope, oname, isig->pin_count()+1,
- NetLogic::XOR);
+ NetLogic::XOR, 1);
break;
case 'A':
gate = new NetLogic(scope, oname, isig->pin_count()+1,
- NetLogic::NAND);
+ NetLogic::NAND, 1);
break;
case 'X':
gate = new NetLogic(scope, oname, isig->pin_count()+1,
- NetLogic::XNOR);
+ NetLogic::XNOR, 1);
break;
default:
@@ -854,27 +852,16 @@ NetNet* NetETernary::synthesize(Design *des)
*/
NetNet* NetESignal::synthesize(Design*des)
{
- if ((lsi_ == 0) && (msi_ == (net_->pin_count() - 1)))
- return net_;
-
- assert(msi_ >= lsi_);
- unsigned wid = msi_ - lsi_ + 1;
-
- NetScope*scope = net_->scope();
- assert(scope);
-
- perm_string name = scope->local_symbol();
- NetNet*tmp = new NetNet(scope, name, NetNet::WIRE, wid);
- tmp->local_flag(true);
-
- for (unsigned idx = 0 ; idx < wid ; idx += 1)
- connect(tmp->pin(idx), net_->pin(idx+lsi_));
-
- return tmp;
+ return net_;
}
/*
* $Log: expr_synth.cc,v $
+ * Revision 1.60 2004/12/11 02:31:26 steve
+ * Rework of internals to carry vectors through nexus instead
+ * of single bits. Make the ivl, tgt-vvp and vvp initial changes
+ * down this path.
+ *
* Revision 1.59 2004/06/30 02:16:26 steve
* Implement signed divide and signed right shift in nets.
*
View
1  ivl.def
@@ -62,6 +62,7 @@ ivl_logic_udp
ivl_lpm_aset_value
ivl_lpm_async_clr
ivl_lpm_async_set
+ivl_lpm_base
ivl_lpm_basename
ivl_lpm_clk
ivl_lpm_data
View
112 ivl_target.h
@@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
-#ident "$Id: ivl_target.h,v 1.126 2004/10/04 01:10:53 steve Exp $"
+#ident "$Id: ivl_target.h,v 1.127 2004/12/11 02:31:26 steve Exp $"
#endif
#ifdef __cplusplus
@@ -231,6 +231,7 @@ typedef enum ivl_lpm_type_e {
IVL_LPM_MOD = 13,
IVL_LPM_MULT = 4,
IVL_LPM_MUX = 5,
+ IVL_LPM_PART = 15, /* part select */
IVL_LPM_SHIFTL = 6,