diff --git a/verilog.spec b/verilog.spec
index 2846b419ee..afcf32737c 100644
--- a/verilog.spec
+++ b/verilog.spec
@@ -32,7 +32,7 @@ engineering formats, including simulation. It strives to be true
 to the IEEE-1364 standard.
 
 %prep
-%setup -n verilog%{suff}-%{rev_date}
+%setup -n verilog-%{version}
 
 %build
 if test X%{suff} != X