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Do sign extension of structuran nets.

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steve
steve committed May 24, 2005
1 parent b6fd4f6 commit 739a1839ed354dce699a6942c31896f61084b231
Showing with 267 additions and 25 deletions.
  1. +12 −1 design_dump.cc
  2. +14 −4 elab_net.cc
  3. +13 −4 elaborate.cc
  4. +9 −1 emit.cc
  5. +13 −1 functor.cc
  6. +6 −1 functor.h
  7. +10 −1 ivl_target.h
  8. +22 −1 netlist.cc
  9. +27 −1 netlist.h
  10. +6 −1 netmisc.h
  11. +27 −1 pad_to_width.cc
  12. +9 −1 t-dll-api.cc
  13. +32 −1 t-dll.cc
  14. +6 −2 t-dll.h
  15. +11 −1 target.cc
  16. +5 −1 target.h
  17. +28 −1 tgt-stub/stub.c
  18. +17 −1 tgt-vvp/vvp_scope.c
View
@@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
-#ident "$Id: design_dump.cc,v 1.159 2005/05/17 20:56:55 steve Exp $"
+#ident "$Id: design_dump.cc,v 1.160 2005/05/24 01:44:27 steve Exp $"
#endif
# include "config.h"
@@ -388,6 +388,14 @@ void NetReplicate::dump_node(ostream&o, unsigned ind) const
dump_obj_attr(o, ind+4);
}
+void NetSignExtend::dump_node(ostream&o, unsigned ind) const
+{
+ o << setw(ind) << "" << "NetSignExtend: "
+ << name() << " output width=" << width_ << endl;
+ dump_node_pins(o, ind+4);
+ dump_obj_attr(o, ind+4);
+}
+
void NetUReduce::dump_node(ostream&o, unsigned ind) const
{
o << setw(ind) << "" << "reduction logic: ";
@@ -1143,6 +1151,9 @@ void Design::dump(ostream&o) const
/*
* $Log: design_dump.cc,v $
+ * Revision 1.160 2005/05/24 01:44:27 steve
+ * Do sign extension of structuran nets.
+ *
* Revision 1.159 2005/05/17 20:56:55 steve
* Parameters cannot have their width changed.
*
View
@@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
-#ident "$Id: elab_net.cc,v 1.164 2005/05/19 03:51:38 steve Exp $"
+#ident "$Id: elab_net.cc,v 1.165 2005/05/24 01:44:27 steve Exp $"
#endif
# include "config.h"
@@ -901,20 +901,27 @@ NetNet* PEBinary::elaborate_net_mul_(Design*des, NetScope*scope,
NetNet*rsig = right_->elaborate_net(des, scope, lwidth, 0, 0, 0);
if (rsig == 0) return 0;
+ // The mult is signed if both its operands are signed.
+ bool arith_is_signed = lsig->get_signed() && rsig->get_signed();
+
unsigned rwidth = lwidth;
if (rwidth == 0) {
- rwidth = lsig->pin_count() + rsig->pin_count();
+ rwidth = lsig->vector_width() + rsig->vector_width();
lwidth = rwidth;
}
+ if (arith_is_signed) {
+ lsig = pad_to_width_signed(des, lsig, rwidth);
+ rsig = pad_to_width_signed(des, rsig, rwidth);
+ }
+
NetMult*mult = new NetMult(scope, scope->local_symbol(), rwidth,
lsig->vector_width(),
rsig->vector_width());
mult->set_line(*this);
des->add_node(mult);
- // The mult is signed if both its operands are signed.
- mult->set_signed( lsig->get_signed() && rsig->get_signed() );
+ mult->set_signed( arith_is_signed );
connect(mult->pin_DataA(), lsig->pin(0));
connect(mult->pin_DataB(), rsig->pin(0));
@@ -2461,6 +2468,9 @@ NetNet* PEUnary::elaborate_net(Design*des, NetScope*scope,
/*
* $Log: elab_net.cc,v $
+ * Revision 1.165 2005/05/24 01:44:27 steve
+ * Do sign extension of structuran nets.
+ *
* Revision 1.164 2005/05/19 03:51:38 steve
* Make sure comparison widths match.
*
View
@@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
-#ident "$Id: elaborate.cc,v 1.323 2005/05/17 20:56:55 steve Exp $"
+#ident "$Id: elaborate.cc,v 1.324 2005/05/24 01:44:27 steve Exp $"
#endif
# include "config.h"
@@ -157,9 +157,15 @@ void PGAssign::elaborate(Design*des, NetScope*scope) const
it to the desired width. */
if (cnt < lval->vector_width()) {
if (lval->get_signed() && rid->get_signed()) {
- cerr << get_line() << ": internal error: "
- << "Forgot how to sign-extend r-value "
- << "to l-value." << endl;
+
+ unsigned use_width = lval->vector_width();
+
+ if (debug_elaborate)
+ cerr << get_line() << ": debug: PGassign "
+ << "Generate sign-extend node." << endl;
+
+ rid = pad_to_width_signed(des, rid, use_width);
+
} else {
if (debug_elaborate)
@@ -2965,6 +2971,9 @@ Design* elaborate(list<perm_string>roots)
/*
* $Log: elaborate.cc,v $
+ * Revision 1.324 2005/05/24 01:44:27 steve
+ * Do sign extension of structuran nets.
+ *
* Revision 1.323 2005/05/17 20:56:55 steve
* Parameters cannot have their width changed.
*
View
10 emit.cc
@@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
-#ident "$Id: emit.cc,v 1.83 2005/02/08 00:12:36 steve Exp $"
+#ident "$Id: emit.cc,v 1.84 2005/05/24 01:44:27 steve Exp $"
#endif
# include "config.h"
@@ -131,6 +131,11 @@ bool NetReplicate::emit_node(struct target_t*tgt) const
return tgt->replicate(this);
}
+bool NetSignExtend::emit_node(struct target_t*tgt) const
+{
+ return tgt->sign_extend(this);
+}
+
bool NetUReduce::emit_node(struct target_t*tgt) const
{
return tgt->ureduce(this);
@@ -523,6 +528,9 @@ int emit(const Design*des, const char*type)
/*
* $Log: emit.cc,v $
+ * Revision 1.84 2005/05/24 01:44:27 steve
+ * Do sign extension of structuran nets.
+ *
* Revision 1.83 2005/02/08 00:12:36 steve
* Add the NetRepeat node, and code generator support.
*
View
@@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
-#ident "$Id: functor.cc,v 1.33 2005/02/03 04:56:20 steve Exp $"
+#ident "$Id: functor.cc,v 1.34 2005/05/24 01:44:27 steve Exp $"
#endif
# include "config.h"
@@ -79,6 +79,10 @@ void functor_t::lpm_mux(class Design*, class NetMux*)
{
}
+void functor_t::sign_extend(class Design*, class NetSignExtend*)
+{
+}
+
void functor_t::lpm_ureduce(class Design*, class NetUReduce*)
{
}
@@ -210,6 +214,11 @@ void NetMux::functor_node(Design*des, functor_t*fun)
fun->lpm_mux(des, this);
}
+void NetSignExtend::functor_node(Design*des, functor_t*fun)
+{
+ fun->sign_extend(des, this);
+}
+
void NetUReduce::functor_node(Design*des, functor_t*fun)
{
fun->lpm_ureduce(des, this);
@@ -276,6 +285,9 @@ int proc_match_t::event_wait(NetEvWait*)
/*
* $Log: functor.cc,v $
+ * Revision 1.34 2005/05/24 01:44:27 steve
+ * Do sign extension of structuran nets.
+ *
* Revision 1.33 2005/02/03 04:56:20 steve
* laborate reduction gates into LPM_RED_ nodes.
*
View
@@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
-#ident "$Id: functor.h,v 1.21 2005/02/03 04:56:20 steve Exp $"
+#ident "$Id: functor.h,v 1.22 2005/05/24 01:44:27 steve Exp $"
#endif
/*
@@ -80,6 +80,8 @@ struct functor_t {
/* This method is called for each unary reduction gate. */
virtual void lpm_ureduce(class Design*des, class NetUReduce*);
+
+ virtual void sign_extend(class Design*des, class NetSignExtend*);
};
struct proc_match_t {
@@ -95,6 +97,9 @@ struct proc_match_t {
/*
* $Log: functor.h,v $
+ * Revision 1.22 2005/05/24 01:44:27 steve
+ * Do sign extension of structuran nets.
+ *
* Revision 1.21 2005/02/03 04:56:20 steve
* laborate reduction gates into LPM_RED_ nodes.
*
View
@@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
-#ident "$Id: ivl_target.h,v 1.154 2005/05/08 23:44:08 steve Exp $"
+#ident "$Id: ivl_target.h,v 1.155 2005/05/24 01:44:28 steve Exp $"
#endif
#ifdef __cplusplus
@@ -247,6 +247,7 @@ typedef enum ivl_lpm_type_e {
IVL_LPM_REPEAT = 26,
IVL_LPM_SHIFTL = 6,
IVL_LPM_SHIFTR = 7,
+ IVL_LPM_SIGN_EXT=27,
IVL_LPM_SUB = 8,
IVL_LPM_RAM = 9,
IVL_LPM_UFUNC = 14
@@ -933,6 +934,11 @@ extern const char* ivl_udp_name(ivl_udp_t net);
* repeated to get the desired width. The ivl core assures that the
* input vector is exactly ivl_lpm_width() / ivl_lpm_size() bits.
*
+ * - Sign Exend (IVL_LPM_SIGN_EXT)
+ * This node takes a single input and generates a single output. The
+ * input must be signed, and the output will be a vector sign extended
+ * to the desired width. The ivl_lpm_width() value is the output
+ * width, the input will be whatever it wants to be.
* - Shifts (IVL_LPM_SHIFTL/SHIFTR)
* This node takes two inputs, a vector and a shift distance. The
* ivl_lpm_data(0) nexus is the vector input, and the ivl_lpm_data(1)
@@ -1658,6 +1664,9 @@ _END_DECL
/*
* $Log: ivl_target.h,v $
+ * Revision 1.155 2005/05/24 01:44:28 steve
+ * Do sign extension of structuran nets.
+ *
* Revision 1.154 2005/05/08 23:44:08 steve
* Add support for variable part select.
*
View
@@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
-#ident "$Id: netlist.cc,v 1.243 2005/05/08 23:44:08 steve Exp $"
+#ident "$Id: netlist.cc,v 1.244 2005/05/24 01:44:28 steve Exp $"
#endif
# include "config.h"
@@ -1474,6 +1474,24 @@ const Link& NetRamDq::pin_Q() const
return pin(5);
}
+NetSignExtend::NetSignExtend(NetScope*s, perm_string n, unsigned w)
+: NetNode(s, n, 2), width_(w)
+{
+ pin(0).set_dir(Link::OUTPUT);
+ pin(1).set_dir(Link::INPUT);
+ pin(0).set_name(perm_string::literal("O"), 0);
+ pin(1).set_name(perm_string::literal("I"), 0);
+}
+
+NetSignExtend::~NetSignExtend()
+{
+}
+
+unsigned NetSignExtend::width() const
+{
+ return width_;
+}
+
NetBUFZ::NetBUFZ(NetScope*s, perm_string n, unsigned w)
: NetNode(s, n, 2), width_(w)
{
@@ -2185,6 +2203,9 @@ const NetProc*NetTaskDef::proc() const
/*
* $Log: netlist.cc,v $
+ * Revision 1.244 2005/05/24 01:44:28 steve
+ * Do sign extension of structuran nets.
+ *
* Revision 1.243 2005/05/08 23:44:08 steve
* Add support for variable part select.
*
View
@@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
-#ident "$Id: netlist.h,v 1.343 2005/05/17 20:56:55 steve Exp $"
+#ident "$Id: netlist.h,v 1.344 2005/05/24 01:44:28 steve Exp $"
#endif
/*
@@ -1364,6 +1364,29 @@ class NetLogic : public NetNode {
unsigned width_;
};
+/*
+ * This class represents a structural sign extension. The pin-0 is a
+ * vector of the input pin-1 sign-extended. The input is taken to be
+ * signed. This generally matches a hardware implementation of
+ * replicating the top bit enough times to create the desired output
+ * width.
+ */
+class NetSignExtend : public NetNode {
+
+ public:
+ explicit NetSignExtend(NetScope*s, perm_string n, unsigned wid);
+ ~NetSignExtend();
+
+ unsigned width() const;
+
+ virtual void dump_node(ostream&, unsigned ind) const;
+ virtual bool emit_node(struct target_t*) const;
+ virtual void functor_node(Design*, functor_t*);
+
+ private:
+ unsigned width_;
+};
+
/*
* This class represents *reduction* logic operators. Certain boolean
* logic operators have reduction forms which take in a vector and
@@ -3444,6 +3467,9 @@ extern ostream& operator << (ostream&, NetNet::Type);
/*
* $Log: netlist.h,v $
+ * Revision 1.344 2005/05/24 01:44:28 steve
+ * Do sign extension of structuran nets.
+ *
* Revision 1.343 2005/05/17 20:56:55 steve
* Parameters cannot have their width changed.
*
View
@@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
-#ident "$Id: netmisc.h,v 1.21 2005/04/24 23:44:02 steve Exp $"
+#ident "$Id: netmisc.h,v 1.22 2005/05/24 01:44:28 steve Exp $"
#endif
# include "netlist.h"
@@ -50,6 +50,8 @@ extern NetScope* symbol_search(Design*des, NetScope*start, hname_t path,
extern NetExpr*pad_to_width(NetExpr*expr, unsigned wid);
extern NetNet*pad_to_width(Design*des, NetNet*n, unsigned w);
+extern NetNet*pad_to_width_signed(Design*des, NetNet*n, unsigned w);
+
/*
* This function transforms an expression by cropping the high bits
* off with a part select. The result has the width w passed in. This
@@ -99,6 +101,9 @@ extern NetExpr* elab_and_eval(Design*des, NetScope*scope, const PExpr*pe);
/*
* $Log: netmisc.h,v $
+ * Revision 1.22 2005/05/24 01:44:28 steve
+ * Do sign extension of structuran nets.
+ *
* Revision 1.21 2005/04/24 23:44:02 steve
* Update DFF support to new data flow.
*
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