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Generalize signals to carry types.

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1 parent 3ac79c2 commit 75ad90534bcc2c3b30b2e25ce242d5ba1dc9e4e6 steve committed Jul 7, 2005
Showing with 915 additions and 164 deletions.
  1. +12 −1 PExpr.h
  2. +30 −6 PWire.cc
  3. +16 −3 PWire.h
  4. +14 −0 README.txt
  5. +11 −2 compiler.h
  6. +34 −1 design_dump.cc
  7. +111 −12 elab_net.cc
  8. +5 −1 elab_sig.cc
  9. +9 −1 emit.cc
  10. +13 −1 functor.cc
  11. +7 −1 functor.h
  12. +35 −8 ivl_target.h
  13. +18 −3 lexor.lex
  14. +3 −0 lexor_keyword.gperf
  15. +10 −1 main.cc
  16. +36 −3 netlist.cc
  17. +44 −3 netlist.h
  18. +8 −1 pad_to_width.cc
  19. +127 −48 parse.y
  20. +39 −19 pform.cc
  21. +17 −4 pform.h
  22. +10 −5 pform_dump.cc
  23. +41 −6 t-dll-api.cc
  24. +37 −2 t-dll.cc
  25. +9 −2 t-dll.h
  26. +11 −1 target.cc
  27. +5 −1 target.h
  28. +54 −6 tgt-stub/stub.c
  29. +32 −2 tgt-vvp/eval_real.c
  30. +41 −2 tgt-vvp/vvp_process.c
  31. +76 −18 tgt-vvp/vvp_scope.c
View
@@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
-#ident "$Id: PExpr.h,v 1.68 2005/01/09 20:16:00 steve Exp $"
+#ident "$Id: PExpr.h,v 1.69 2005/07/07 16:22:49 steve Exp $"
#endif
# include <string>
@@ -198,6 +198,14 @@ class PEFNumber : public PExpr {
bool sys_task_arg =false) const;
virtual NetExpr*elaborate_pexpr(Design*des, NetScope*sc) const;
+ virtual NetNet* elaborate_net(Design*des, NetScope*scope,
+ unsigned lwidth,
+ unsigned long rise,
+ unsigned long fall,
+ unsigned long decay,
+ Link::strength_t drive0,
+ Link::strength_t drive1) const;
+
virtual void dump(ostream&) const;
private:
@@ -506,6 +514,9 @@ class PECallFunction : public PExpr {
/*
* $Log: PExpr.h,v $
+ * Revision 1.69 2005/07/07 16:22:49 steve
+ * Generalize signals to carry types.
+ *
* Revision 1.68 2005/01/09 20:16:00 steve
* Use PartSelect/PV and VP to handle part selects through ports.
*
View
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 1999 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 1999-2005 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -17,15 +17,19 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
-#ident "$Id: PWire.cc,v 1.10 2002/08/12 01:34:58 steve Exp $"
+#ident "$Id: PWire.cc,v 1.11 2005/07/07 16:22:49 steve Exp $"
#endif
# include "config.h"
# include "PWire.h"
# include <assert.h>
-PWire::PWire(const hname_t&n, NetNet::Type t, NetNet::PortType pt)
-: hname_(n), type_(t), port_type_(pt), signed_(false), isint_(false),
+PWire::PWire(const hname_t&n,
+ NetNet::Type t,
+ NetNet::PortType pt,
+ ivl_variable_type_t dt)
+: hname_(n), type_(t), port_type_(pt), data_type_(dt),
+ signed_(false), isint_(false),
lidx_(0), ridx_(0)
{
if (t == NetNet::INTEGER) {
@@ -35,8 +39,12 @@ lidx_(0), ridx_(0)
}
}
-PWire::PWire(char*n, NetNet::Type t, NetNet::PortType pt)
-: hname_(n), type_(t), port_type_(pt), signed_(false), isint_(false),
+PWire::PWire(char*n,
+ NetNet::Type t,
+ NetNet::PortType pt,
+ ivl_variable_type_t dt)
+: hname_(n), type_(t), port_type_(pt), data_type_(dt),
+ signed_(false), isint_(false),
lidx_(0), ridx_(0)
{
if (t == NetNet::INTEGER) {
@@ -108,6 +116,19 @@ bool PWire::set_port_type(NetNet::PortType pt)
}
}
+bool PWire::set_data_type(ivl_variable_type_t dt)
+{
+ if (data_type_ != IVL_VT_NO_TYPE)
+ if (data_type_ != dt)
+ return false;
+ else
+ return true;
+
+ assert(data_type_ == IVL_VT_NO_TYPE);
+ data_type_ = dt;
+ return true;
+}
+
void PWire::set_signed(bool flag)
{
signed_ = flag;
@@ -140,6 +161,9 @@ void PWire::set_memory_idx(PExpr*ldx, PExpr*rdx)
/*
* $Log: PWire.cc,v $
+ * Revision 1.11 2005/07/07 16:22:49 steve
+ * Generalize signals to carry types.
+ *
* Revision 1.10 2002/08/12 01:34:58 steve
* conditional ident string using autoconfig.
*
View
@@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
-#ident "$Id: PWire.h,v 1.17 2004/02/20 18:53:33 steve Exp $"
+#ident "$Id: PWire.h,v 1.18 2005/07/07 16:22:49 steve Exp $"
#endif
# include "netlist.h"
@@ -49,8 +49,14 @@ class Design;
class PWire : public LineInfo {
public:
- PWire(const hname_t&hname, NetNet::Type t, NetNet::PortType pt);
- PWire(char*name, NetNet::Type t, NetNet::PortType pt);
+ PWire(const hname_t&hname,
+ NetNet::Type t,
+ NetNet::PortType pt,
+ ivl_variable_type_t dt);
+ PWire(char*name,
+ NetNet::Type t,
+ NetNet::PortType pt,
+ ivl_variable_type_t dt);
// Return a hierarchical name.
const hname_t&path() const;
@@ -65,6 +71,9 @@ class PWire : public LineInfo {
bool get_signed() const;
bool get_isint() const;
+ bool set_data_type(ivl_variable_type_t dt);
+ ivl_variable_type_t get_data_type() const;
+
void set_range(PExpr*msb, PExpr*lsb);
void set_memory_idx(PExpr*ldx, PExpr*rdx);
@@ -80,6 +89,7 @@ class PWire : public LineInfo {
hname_t hname_;
NetNet::Type type_;
NetNet::PortType port_type_;
+ ivl_variable_type_t data_type_;
bool signed_;
bool isint_; // original type of integer
@@ -100,6 +110,9 @@ class PWire : public LineInfo {
/*
* $Log: PWire.h,v $
+ * Revision 1.18 2005/07/07 16:22:49 steve
+ * Generalize signals to carry types.
+ *
* Revision 1.17 2004/02/20 18:53:33 steve
* Addtrbute keys are perm_strings.
*
View
@@ -470,6 +470,20 @@ language that are defined.
combinational always blocks to be triggered when the values in
the sensitivity list are initialized by initial threads.
+ Nets with Types
+
+ Icarus Verilog support an extension syntax that allows nets
+ and regs to be explicitly typed. The currently supported types
+ are logic, bool and real. This implies that "logic" and "bool"
+ are new keywords. Typical syntax is:
+
+ wire real foo = 1.0;
+ reg logic bar, bat;
+
+ ... and so forth. The syntax can be turned off by using the
+ -g2 flag to iverilog, and turned on explicitly with the -g2x
+ flag to iverilog.
+
6.0 CREDITS
Except where otherwise noted, Icarus Verilog, ivl and ivlpp are
View
@@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
-#ident "$Id: compiler.h,v 1.28 2005/06/28 04:25:55 steve Exp $"
+#ident "$Id: compiler.h,v 1.29 2005/07/07 16:22:49 steve Exp $"
#endif
# include <list>
@@ -94,7 +94,8 @@ extern list<const char*>library_suff;
extern int build_library_index(const char*path, bool key_case_sensitive);
/* This is the generation of Verilog that the compiler is asked to
- support. */
+ support. Then there are also more detailed controls for more
+ specific language features. */
enum generation_t {
GN_VER1995 = 1,
GN_VER2001 = 2,
@@ -103,6 +104,11 @@ enum generation_t {
};
extern generation_t generation_flag;
+extern bool gn_cadence_types_flag;
+
+/* These functions test that specific features are enabled. */
+inline bool gn_cadence_types_enabled()
+{ return gn_cadence_types_flag && generation_flag==GN_VER2001X; }
/* This is the string to use to invoke the preprocessor. */
extern char*ivlpp_string;
@@ -137,6 +143,9 @@ extern int load_sys_func_table(const char*path);
/*
* $Log: compiler.h,v $
+ * Revision 1.29 2005/07/07 16:22:49 steve
+ * Generalize signals to carry types.
+ *
* Revision 1.28 2005/06/28 04:25:55 steve
* Remove reference to SystemVerilog.
*
View
@@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
-#ident "$Id: design_dump.cc,v 1.160 2005/05/24 01:44:27 steve Exp $"
+#ident "$Id: design_dump.cc,v 1.161 2005/07/07 16:22:49 steve Exp $"
#endif
# include "config.h"
@@ -68,13 +68,36 @@ ostream& operator << (ostream&o, Link::strength_t str)
return o;
}
+ostream& operator << (ostream&o, ivl_variable_type_t val)
+{
+ switch (val) {
+ case IVL_VT_VOID:
+ o << "void";
+ break;
+ case IVL_VT_NO_TYPE:
+ o << "<no_type>";
+ break;
+ case IVL_VT_REAL:
+ o << "real";
+ break;
+ case IVL_VT_BOOL:
+ o << "bool";
+ break;
+ case IVL_VT_LOGIC:
+ o << "logic";
+ break;
+ }
+ return o;
+}
+
/* Dump a net. This can be a wire or register. */
void NetNet::dump_net(ostream&o, unsigned ind) const
{
o << setw(ind) << "" << type() << ": " << name() << "[" <<
pin_count() << "]";
if (local_flag_)
o << " (local)";
+ o << " " << data_type_;
if (signed_)
o << " signed";
switch (port_type_) {
@@ -276,6 +299,13 @@ void NetFF::dump_node(ostream&o, unsigned ind) const
dump_obj_attr(o, ind+4);
}
+void NetLiteral::dump_node(ostream&o, unsigned ind) const
+{
+ o << setw(ind) << "" << "constant real " << real_
+ << ": " << name() << endl;
+ dump_node_pins(o, ind+4);
+}
+
void NetLogic::dump_node(ostream&o, unsigned ind) const
{
o << setw(ind) << "" << "logic: ";
@@ -1151,6 +1181,9 @@ void Design::dump(ostream&o) const
/*
* $Log: design_dump.cc,v $
+ * Revision 1.161 2005/07/07 16:22:49 steve
+ * Generalize signals to carry types.
+ *
* Revision 1.160 2005/05/24 01:44:27 steve
* Do sign extension of structuran nets.
*
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