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Extend VPI and build to for SIMetrix cosimulation

Added: basic vpiPort VPI Objects for vpiModulkes
    vpiDirection, vpiPortIndex,   vpiName, vpiSize attributes

   Since ports do not exist as net-like entities (nets either side
   module instance boundaries are in effect connect directly in
   the language front-ends internal representation) the port information
   is effectively just meta-data passed through t-dll  interface and
   output as a additional annotation of module scopes in vvp.

Added: vpiLocalParam attribute for vpiParameter VPI objects

Added: support build for 32-bit target on 64-bit host (--with-m32
   option to configure.in and minor tweaks to Makefiles and systemc-vpi).
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1 parent 3354d83 commit 9b3d20239a6688de9127a1d8593d4c83c1c25fce @wackston wackston committed with Jun 4, 2012
Showing with 622 additions and 92 deletions.
  1. +3 −1 Makefile.in
  2. +16 −0 Module.cc
  3. +3 −0 Module.h
  4. +1 −1 PExpr.h
  5. +28 −0 configure.in
  6. +3 −3 elab_net.cc
  7. +7 −5 elab_scope.cc
  8. +47 −7 elaborate.cc
  9. +1 −1 iverilog-vpi.sh
  10. +14 −2 ivl_target.h
  11. +5 −1 libveriuser/Makefile.in
  12. +9 −1 main.cc
  13. +37 −12 net_scope.cc
  14. +27 −1 netlist.cc
  15. +55 −6 netlist.h
  16. +46 −0 t-dll-api.cc
  17. +10 −4 t-dll.cc
  18. +7 −0 t-dll.h
  19. +76 −14 tgt-vvp/vvp_scope.c
  20. +12 −0 vpi_user.h
  21. +12 −5 vvp/compile.cc
  22. +14 −1 vvp/compile.h
  23. +1 −0 vvp/delay.h
  24. +7 −0 vvp/lexor.lex
  25. +10 −0 vvp/main.cc
  26. +26 −9 vvp/parse.y
  27. +1 −0 vvp/parse_misc.h
  28. +1 −1 vvp/schedule.cc
  29. +36 −12 vvp/vpi_const.cc
  30. +5 −2 vvp/vpi_priv.cc
  31. +7 −3 vvp/vpi_priv.h
  32. +94 −0 vvp/vpi_scope.cc
  33. +1 −0 vvp/words.cc
View
@@ -95,6 +95,7 @@ CFLAGS = @WARNING_FLAGS@ @CFLAGS@
CXXFLAGS = @WARNING_FLAGS@ @WARNING_FLAGS_CXX@ @CXXFLAGS@
PICFLAGS = @PICFLAG@
LDFLAGS = @rdynamic@ @LDFLAGS@
+CTARGETFLAGS = @CTARGETFLAGS@
# Source files in the libmisc directory
M = LineInfo.o StringHeap.o
@@ -228,6 +229,7 @@ iverilog-vpi: $(srcdir)/iverilog-vpi.sh Makefile
-e 's;@IVCXX@;$(CXX);' \
-e 's;@IVCFLAGS@;$(CFLAGS);' \
-e 's;@IVCXXFLAGS@;$(CXXFLAGS);' \
+ -e 's;@IVCTARGETFLAGS@;$(CTARGETFLAGS);' \
-e 's;@INCLUDEDIR@;$(includedir);' \
-e 's;@LIBDIR@;@libdir@;' $< > $@
chmod +x $@
@@ -239,7 +241,7 @@ version.exe: $(srcdir)/version.c $(srcdir)/version_base.h version_tag.h
%.o: %.cc config.h
$(CXX) $(CPPFLAGS) $(CXXFLAGS) @DEPENDENCY_FLAG@ -c $< -o $*.o
mv $*.d dep/$*.d
-
+
# Here are some explicit dependencies needed to get things going.
main.o: main.cc version_tag.h
View
@@ -90,6 +90,22 @@ unsigned Module::find_port(const char*name) const
return ports.size();
}
+perm_string Module::get_port_name(unsigned idx) const
+{
+
+ assert(idx < ports.size());
+ if (ports[idx] == 0) {
+ /* It is possible to have undeclared ports. These
+ are ports that are skipped in the declaration,
+ for example like so: module foo(x ,, y); The
+ port between x and y is unnamed and thus
+ inaccessible to binding by name. */
+ return perm_string::literal("");
+ }
+ return ports[idx]->name;
+}
+
+
PGate* Module::get_gate(perm_string name)
{
View
@@ -136,6 +136,9 @@ class Module : public PScopeExtra, public LineInfo {
const vector<PEIdent*>& get_port(unsigned idx) const;
unsigned find_port(const char*name) const;
+ // Return port name ("" for undeclared port)
+ perm_string get_port_name(unsigned idx) const;
+
PGate* get_gate(perm_string name);
const list<PGate*>& get_gates() const;
View
@@ -311,7 +311,7 @@ class PEIdent : public PExpr {
// Elaborate the PEIdent as a port to a module. This method
// only applies to Ident expressions.
- NetNet* elaborate_port(Design*des, NetScope*sc) const;
+ NetNet* elaborate_subport(Design*des, NetScope*sc) const;
verinum* eval_const(Design*des, NetScope*sc) const;
View
@@ -91,6 +91,20 @@ fi
AC_LANG(C++)
+AC_ARG_WITH([m32], [AC_HELP_STRING([--with-m32], [Compile 32-bit on x86_64])],
+ [ with_m32=yes ],[ with_m32=no ])
+
+AS_IF( [test "x$with_m32" = xyes],
+ [ AC_MSG_NOTICE([Compiling for 32-bit environment - needs gcc on x86_64])
+ LDTARGETFLAGS="-m elf_i386"
+ CTARGETFLAGS="-m32"
+ ],
+ [])
+
+CFLAGS="$CTARGETFLAGS $CFLAGS"
+CXXFLAGS="$CTARGETFLAGS $CXXFLAGS"
+LDFLAGS="$CTARGETFLAGS $LDFLAGS"
+
# Check that we are using either the GNU compilers or the Sun compilers
# but not a mixture of the two (not currently supported).
AC_CHECK_DECL(__SUNPRO_CC, using_sunpro_cc=1, using_sunpro_cc=0)
@@ -111,7 +125,11 @@ else
fi
fi
+iverilog_temp_cxxflags="$CXXFLAGS"
+CXXFLAGS="-DHAVE_DECL_BASENAME $CXXFLAGS"
+
AC_CHECK_HEADERS(getopt.h inttypes.h libiberty.h iosfwd sys/wait.h)
+CXXFLAGS="$iverilog_temp_cxxflags"
AC_CHECK_SIZEOF(unsigned long long)
AC_CHECK_SIZEOF(unsigned long)
@@ -178,6 +196,11 @@ if test -z "$DLLIB" ; then
AC_CHECK_LIB(dld,shl_load,[DLLIB=-ldld])
fi
AC_SUBST(DLLIB)
+AC_SUBST(LDRELOCFLAGS)
+
+AC_SUBST(CTARGETFLAGS)
+AC_SUBST(LDTARGETFLAGS)
+
AC_PROG_INSTALL
@@ -304,4 +327,9 @@ AC_MSG_RESULT(ok)
# XXX disable tgt-fpga for the moment
+#
+# Ensure compiler target options go in...
+
+
+
AC_OUTPUT(Makefile ivlpp/Makefile vhdlpp/Makefile vvp/Makefile vpi/Makefile driver/Makefile driver-vpi/Makefile cadpli/Makefile libveriuser/Makefile tgt-null/Makefile tgt-stub/Makefile tgt-vvp/Makefile tgt-vhdl/Makefile tgt-fpga/Makefile tgt-verilog/Makefile tgt-pal/Makefile tgt-vlog95/Makefile tgt-pcb/Makefile)
View
@@ -691,7 +691,7 @@ NetNet* PEIdent::elaborate_bi_net(Design*des, NetScope*scope) const
* instantiation (PGModule::elaborate_mod_) to get NetNet objects for
* the port.
*/
-NetNet* PEIdent::elaborate_port(Design*des, NetScope*scope) const
+NetNet* PEIdent::elaborate_subport(Design*des, NetScope*scope) const
{
ivl_assert(*this, scope->type() == NetScope::MODULE);
NetNet*sig = des->find_signal(scope, path_);
@@ -748,7 +748,7 @@ NetNet* PEIdent::elaborate_port(Design*des, NetScope*scope) const
/* If this is a part select of the entire signal (or no part
select at all) then we're done. */
if ((lidx == 0) && (midx == (long)sig->vector_width()-1)) {
- scope->add_module_port(sig);
+ scope->add_module_port_net(sig);
return sig;
}
@@ -795,7 +795,7 @@ NetNet* PEIdent::elaborate_port(Design*des, NetScope*scope) const
ps->set_line(*this);
des->add_node(ps);
- scope->add_module_port(sig);
+ scope->add_module_port_net(sig);
return sig;
}
View
@@ -52,7 +52,8 @@ typedef map<perm_string,LexicalScope::param_expr_t>::const_iterator mparm_it_t;
static void collect_parm_item_(Design*des, NetScope*scope, perm_string name,
const LexicalScope::param_expr_t&cur,
- bool is_annotatable)
+ bool is_annotatable,
+ bool local_flag)
{
NetScope::range_t*range_list = 0;
for (LexicalScope::range_t*range = cur.range ; range ; range = range->next) {
@@ -88,8 +89,9 @@ static void collect_parm_item_(Design*des, NetScope*scope, perm_string name,
range_list = tmp;
}
+
scope->set_parameter(name, is_annotatable, cur.expr, cur.type, cur.msb,
- cur.lsb, cur.signed_flag, range_list, cur);
+ cur.lsb, cur.signed_flag, local_flag, range_list, cur);
}
static void collect_scope_parameters_(Design*des, NetScope*scope,
@@ -107,7 +109,7 @@ static void collect_scope_parameters_(Design*des, NetScope*scope,
des->errors += 1;
}
- collect_parm_item_(des, scope, (*cur).first, (*cur).second, false);
+ collect_parm_item_(des, scope, (*cur).first, (*cur).second, false, false);
}
}
@@ -126,7 +128,7 @@ static void collect_scope_localparams_(Design*des, NetScope*scope,
des->errors += 1;
}
- collect_parm_item_(des, scope, (*cur).first, (*cur).second, false);
+ collect_parm_item_(des, scope, (*cur).first, (*cur).second, false, true);
}
}
@@ -145,7 +147,7 @@ static void collect_scope_specparams_(Design*des, NetScope*scope,
des->errors += 1;
}
- collect_parm_item_(des, scope, (*cur).first, (*cur).second, true);
+ collect_parm_item_(des, scope, (*cur).first, (*cur).second, true, false);
}
}
View
@@ -1250,6 +1250,7 @@ void PGModule::elaborate_mod_(Design*des, Module*rmod, NetScope*scope) const
get_name() << "..." << endl;
for (unsigned inst = 0 ; inst < instance.size() ; inst += 1) {
rmod->elaborate(des, instance[inst]);
+ instance[inst]->set_num_ports( rmod->port_count() );
}
if (debug_elaborate) cerr << get_fileline() << ": debug: ...done." << endl;
@@ -1329,7 +1330,7 @@ void PGModule::elaborate_mod_(Design*des, Module*rmod, NetScope*scope) const
unconnected_port = true;
}
- // Inside the module, the port is zero or more signals
+ // Inside the module, the port connects zero or more signals
// that were already elaborated. List all those signals
// and the NetNet equivalents, for all the instances.
vector<PEIdent*> mport = rmod->get_port(idx);
@@ -1349,19 +1350,24 @@ void PGModule::elaborate_mod_(Design*des, Module*rmod, NetScope*scope) const
// will be assembled in that order as well.
NetScope*inst_scope = instance[instance.size()-inst-1];
+ unsigned int prt_vector_width = 0;
+ PortType::Enum ptype = PortType::PIMPLICIT;
// Scan the module sub-ports for this instance...
for (unsigned ldx = 0 ; ldx < mport.size() ; ldx += 1) {
unsigned lbase = inst * mport.size();
PEIdent*pport = mport[ldx];
assert(pport);
- prts[lbase + ldx]
- = pport->elaborate_port(des, inst_scope);
- if (prts[lbase + ldx] == 0)
+ NetNet *netnet = pport->elaborate_subport(des, inst_scope);
+ prts[lbase + ldx] = netnet;
+ if (netnet == 0)
continue;
- assert(prts[lbase + ldx]);
- prts_vector_width += prts[lbase + ldx]->vector_width();
+ assert(netnet);
+ prts_vector_width += netnet->vector_width();
+ prt_vector_width += netnet->vector_width();
+ ptype = PortType::merged(netnet->port_type(), ptype);
}
+ inst_scope->add_module_port_info(idx, rmod->get_port_name(idx), ptype, prt_vector_width );
}
// If I find that the port is unconnected inside the
@@ -4512,6 +4518,7 @@ static void elaborate_tasks(Design*des, NetScope*scope,
* When a module is instantiated, it creates the scope then uses this
* method to elaborate the contents of the module.
*/
+
bool Module::elaborate(Design*des, NetScope*scope) const
{
bool result_flag = true;
@@ -4976,10 +4983,22 @@ Design* elaborate(list<perm_string>roots)
// creates all the NetNet and NetMemory objects for declared
// objects.
for (i = 0; i < root_elems.count(); i++) {
+
Module *rmod = root_elems[i]->mod;
NetScope *scope = root_elems[i]->scope;
+ scope->set_num_ports( rmod->port_count() );
+
+ if (debug_elaborate) {
+ cerr << "<toplevel>" << ": debug: " << rmod->mod_name()
+ << ": port elaboration root "
+ << rmod->port_count() << " ports" << endl;
+ }
if (! rmod->elaborate_sig(des, scope)) {
+ if (debug_elaborate) {
+ cerr << "<toplevel>" << ": debug: " << rmod->mod_name()
+ << ": elaborate_sig failed!!!" << endl;
+ }
delete des;
return 0;
}
@@ -4988,11 +5007,26 @@ Design* elaborate(list<perm_string>roots)
// defined for the root modules. This code does that.
for (unsigned idx = 0; idx < rmod->port_count(); idx += 1) {
vector<PEIdent*> mport = rmod->get_port(idx);
+ unsigned int prt_vector_width = 0;
+ PortType::Enum ptype = PortType::PIMPLICIT;
for (unsigned pin = 0; pin < mport.size(); pin += 1) {
// This really does more than we need and adds extra
// stuff to the design that should be cleaned later.
- (void) mport[pin]->elaborate_port(des, scope);
+ (void) mport[pin]->elaborate_subport(des, scope);
+ NetNet *netnet = mport[pin]->elaborate_subport(des, scope);
+ if( netnet != 0 )
+ {
+ // Elaboration may actually fail with erroneous input source
+ prt_vector_width += netnet->vector_width();
+ ptype = PortType::merged(netnet->port_type(), ptype);
+ }
}
+ if (debug_elaborate) {
+ cerr << "<toplevel>" << ": debug: " << rmod->mod_name()
+ << ": adding module port "
+ << rmod->get_port_name(idx) << endl;
+ }
+ scope->add_module_port_info(idx, rmod->get_port_name(idx), ptype, prt_vector_width );
}
}
@@ -5019,5 +5053,11 @@ Design* elaborate(list<perm_string>roots)
des = 0;
}
+ if (debug_elaborate) {
+ cerr << "<toplevel>" << ": debug: "
+ << " finishing with "
+ << des->find_root_scopes().size() << " root scopes " << endl;
+ }
+
return des;
}
View
@@ -28,7 +28,7 @@ SUFFIX=@SUFFIX@
# These are used for linking...
LD=$CC
-LDFLAGS="@SHARED@ -L@LIBDIR@"
+LDFLAGS="@IVCTARGETFLAGS@ @SHARED@ -L@LIBDIR@"
LDLIBS="-lveriuser$SUFFIX -lvpi$SUFFIX"
CCSRC=
View
@@ -193,6 +193,7 @@ typedef struct ivl_parameter_s*ivl_parameter_t;
typedef struct ivl_process_s *ivl_process_t;
typedef struct ivl_scope_s *ivl_scope_t;
typedef struct ivl_signal_s *ivl_signal_t;
+typedef struct ivl_port_info_s *ivl_port_info_t;
typedef struct ivl_switch_s *ivl_switch_t;
typedef struct ivl_memory_s *ivl_memory_t; //XXXX __attribute__((deprecated));
typedef struct ivl_statement_s*ivl_statement_t;
@@ -363,7 +364,7 @@ typedef enum ivl_scope_type_e {
/* Signals (ivl_signal_t) that are ports into the scope that contains
them have a port type. Otherwise, they are port IVL_SIP_NONE. */
-typedef enum ivl_signal_port_e {
+typedef enum OUT {
IVL_SIP_NONE = 0,
IVL_SIP_INPUT = 1,
IVL_SIP_OUTPUT= 2,
@@ -1568,14 +1569,18 @@ extern ivl_signal_t ivl_nexus_ptr_sig(ivl_nexus_ptr_t net);
* Return the value of the parameter. This should be a simple
* constant expression, an IVL_EX_STRING or IVL_EX_NUMBER.
*
+ * ivl_parameter_local
+ * Return whether parameter was local (localparam, implicit genvar etc)
+ * or not.
+ *
* ivl_parameter_file
* ivl_parameter_lineno
* Returns the file and line where this parameter is defined
*/
extern const char* ivl_parameter_basename(ivl_parameter_t net);
extern ivl_scope_t ivl_parameter_scope(ivl_parameter_t net);
extern ivl_expr_t ivl_parameter_expr(ivl_parameter_t net);
-
+extern int ivl_parameter_local(ivl_parameter_t net);
extern const char* ivl_parameter_file(ivl_parameter_t net);
extern unsigned ivl_parameter_lineno(ivl_parameter_t net);
@@ -1738,6 +1743,12 @@ extern const char* ivl_scope_basename(ivl_scope_t net);
extern unsigned ivl_scope_params(ivl_scope_t net);
extern ivl_parameter_t ivl_scope_param(ivl_scope_t net, unsigned idx);
extern ivl_scope_t ivl_scope_parent(ivl_scope_t net);
+
+extern unsigned ivl_scope_mod_module_ports(ivl_scope_t net);
+extern const char *ivl_scope_mod_module_port_name(ivl_scope_t net, unsigned idx );
+extern ivl_signal_port_t ivl_scope_mod_module_port_type(ivl_scope_t net, unsigned idx );
+extern unsigned ivl_scope_mod_module_port_width(ivl_scope_t net, unsigned idx );
+
extern unsigned ivl_scope_ports(ivl_scope_t net);
extern ivl_signal_t ivl_scope_port(ivl_scope_t net, unsigned idx);
extern ivl_nexus_t ivl_scope_mod_port(ivl_scope_t net, unsigned idx);
@@ -1878,6 +1889,7 @@ extern int ivl_signal_msb(ivl_signal_t net) __attribute__((deprecated));
extern int ivl_signal_lsb(ivl_signal_t net) __attribute__((deprecated));
extern unsigned ivl_signal_width(ivl_signal_t net);
extern ivl_signal_port_t ivl_signal_port(ivl_signal_t net);
+extern int ivl_signal_module_port_index(ivl_signal_t net);
extern int ivl_signal_signed(ivl_signal_t net);
extern int ivl_signal_integer(ivl_signal_t net);
extern int ivl_signal_local(ivl_signal_t net);
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