diff --git a/Attrib.cc b/Attrib.cc
index f82b4293d9..aa01d05568 100644
--- a/Attrib.cc
+++ b/Attrib.cc
@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT)
-#ident "$Id: Attrib.cc,v 1.3 2002/05/23 03:08:50 steve Exp $"
+#ident "$Id: Attrib.cc,v 1.4 2002/05/26 01:39:02 steve Exp $"
 #endif
 
 # include "config.h"
@@ -103,18 +103,18 @@ bool Attrib::has_compat_attributes(const Attrib&that) const
       return true;
 }
 
-unsigned Attrib::size() const
+unsigned Attrib::attr_cnt() const
 {
       return nlist_;
 }
 
-string Attrib::key(unsigned idx) const
+const char* Attrib::attr_key(unsigned idx) const
 {
       assert(idx < nlist_);
-      return list_[idx].key;
+      return list_[idx].key.c_str();
 }
 
-const verinum& Attrib::value(unsigned idx) const
+const verinum& Attrib::attr_value(unsigned idx) const
 {
       assert(idx < nlist_);
       return list_[idx].val;
@@ -123,6 +123,13 @@ const verinum& Attrib::value(unsigned idx) const
 
 /*
  * $Log: Attrib.cc,v $
+ * Revision 1.4  2002/05/26 01:39:02  steve
+ *  Carry Verilog 2001 attributes with processes,
+ *  all the way through to the ivl_target API.
+ *
+ *  Divide signal reference counts between rval
+ *  and lval references.
+ *
  * Revision 1.3  2002/05/23 03:08:50  steve
  *  Add language support for Verilog-2001 attribute
  *  syntax. Hook this support into existing $attribute
diff --git a/Attrib.h b/Attrib.h
index dd77cbf173..58e5f52437 100644
--- a/Attrib.h
+++ b/Attrib.h
@@ -19,11 +19,10 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT)
-#ident "$Id: Attrib.h,v 1.2 2002/05/23 03:08:50 steve Exp $"
+#ident "$Id: Attrib.h,v 1.3 2002/05/26 01:39:02 steve Exp $"
 #endif
 
 # include  <string>
-# include  <map>
 # include  "verinum.h"
 
 /*
@@ -42,9 +41,9 @@ class Attrib {
 
 
 	/* Provide a means of iterating over the entries in the map. */
-      unsigned size() const;
-      string key(unsigned idx) const;
-      const verinum& value(unsigned idx) const;
+      unsigned       attr_cnt() const;
+      const char*    attr_key(unsigned idx) const;
+      const verinum& attr_value(unsigned idx) const;
 
 
     private:
@@ -63,6 +62,13 @@ class Attrib {
 
 /*
  * $Log: Attrib.h,v $
+ * Revision 1.3  2002/05/26 01:39:02  steve
+ *  Carry Verilog 2001 attributes with processes,
+ *  all the way through to the ivl_target API.
+ *
+ *  Divide signal reference counts between rval
+ *  and lval references.
+ *
  * Revision 1.2  2002/05/23 03:08:50  steve
  *  Add language support for Verilog-2001 attribute
  *  syntax. Hook this support into existing $attribute
diff --git a/Statement.h b/Statement.h
index a6cc65de48..b5456aa2ef 100644
--- a/Statement.h
+++ b/Statement.h
@@ -19,7 +19,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: Statement.h,v 1.33 2002/04/21 22:31:02 steve Exp $"
+#ident "$Id: Statement.h,v 1.34 2002/05/26 01:39:02 steve Exp $"
 #endif
 
 # include  <string>
@@ -56,6 +56,8 @@ class PProcess : public LineInfo {
       Type type() const { return type_; }
       Statement*statement() { return statement_; }
 
+      map<string,PExpr*> attributes;
+
       virtual void dump(ostream&out, unsigned ind) const;
 
     private:
@@ -453,6 +455,13 @@ class PWhile  : public Statement {
 
 /*
  * $Log: Statement.h,v $
+ * Revision 1.34  2002/05/26 01:39:02  steve
+ *  Carry Verilog 2001 attributes with processes,
+ *  all the way through to the ivl_target API.
+ *
+ *  Divide signal reference counts between rval
+ *  and lval references.
+ *
  * Revision 1.33  2002/04/21 22:31:02  steve
  *  Redo handling of assignment internal delays.
  *  Leave it possible for them to be calculated
diff --git a/cprop.cc b/cprop.cc
index 064bc8488d..c85e377d38 100644
--- a/cprop.cc
+++ b/cprop.cc
@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: cprop.cc,v 1.34 2002/05/23 03:08:51 steve Exp $"
+#ident "$Id: cprop.cc,v 1.35 2002/05/26 01:39:02 steve Exp $"
 #endif
 
 # include "config.h"
@@ -915,7 +915,7 @@ void cprop_dc_functor::lpm_const(Design*des, NetConst*obj)
 		    // If the net has an eref, then there is an
 		    // expression somewhere that reads this signal. So
 		    // the constant does get read.
-		  if (tmp->get_eref() > 0)
+		  if (tmp->peek_eref() > 0)
 			return;
 
 		    // If the net is a port of the root module, then
@@ -949,6 +949,13 @@ void cprop(Design*des)
 
 /*
  * $Log: cprop.cc,v $
+ * Revision 1.35  2002/05/26 01:39:02  steve
+ *  Carry Verilog 2001 attributes with processes,
+ *  all the way through to the ivl_target API.
+ *
+ *  Divide signal reference counts between rval
+ *  and lval references.
+ *
  * Revision 1.34  2002/05/23 03:08:51  steve
  *  Add language support for Verilog-2001 attribute
  *  syntax. Hook this support into existing $attribute
diff --git a/design_dump.cc b/design_dump.cc
index 56f75d4f0e..487f085f89 100644
--- a/design_dump.cc
+++ b/design_dump.cc
@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: design_dump.cc,v 1.123 2002/05/05 21:11:49 steve Exp $"
+#ident "$Id: design_dump.cc,v 1.124 2002/05/26 01:39:02 steve Exp $"
 #endif
 
 # include "config.h"
@@ -93,7 +93,7 @@ void NetNet::dump_net(ostream&o, unsigned ind) const
 	    o << " inout";
 	    break;
       }
-      o << " (eref=" << get_eref() << ")";
+      o << " (eref=" << peek_eref() << ", lref=" << peek_lref() << ")";
       if (scope())
 	    o << " scope=" << scope()->name();
       o << " #(" << rise_time() << "," << fall_time() << "," <<
@@ -174,9 +174,9 @@ void NetObj::dump_node_pins(ostream&o, unsigned ind) const
 void NetObj::dump_obj_attr(ostream&o, unsigned ind) const
 {
       unsigned idx;
-      for (idx = 0 ;  idx < attributes_.size() ;  idx += 1) {
-	    o << setw(ind) << "" << attributes_.key(idx) << " = \"" <<
-		  attributes_.value(idx) << "\"" << endl;
+      for (idx = 0 ;  idx < attr_cnt() ;  idx += 1) {
+	    o << setw(ind) << "" << attr_key(idx) << " = \"" <<
+		  attr_value(idx) << "\"" << endl;
       }
 }
 
@@ -413,6 +413,11 @@ void NetProcTop::dump(ostream&o, unsigned ind) const
 	    break;
       }
 
+      for (unsigned idx = 0 ;  idx < attr_cnt() ;  idx += 1) {
+	    o << setw(ind+2) << "" << "(* " << attr_key(idx) << " = "
+	      << attr_value(idx) << " *)" << endl;
+      }
+
       statement_->dump(o, ind+2);
 }
 
@@ -980,6 +985,13 @@ void Design::dump(ostream&o) const
 
 /*
  * $Log: design_dump.cc,v $
+ * Revision 1.124  2002/05/26 01:39:02  steve
+ *  Carry Verilog 2001 attributes with processes,
+ *  all the way through to the ivl_target API.
+ *
+ *  Divide signal reference counts between rval
+ *  and lval references.
+ *
  * Revision 1.123  2002/05/05 21:11:49  steve
  *  Put off evaluation of concatenation repeat expresions
  *  until after parameters are defined. This allows parms
diff --git a/elaborate.cc b/elaborate.cc
index 06e211e4c0..f81559722c 100644
--- a/elaborate.cc
+++ b/elaborate.cc
@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: elaborate.cc,v 1.249 2002/05/23 03:08:51 steve Exp $"
+#ident "$Id: elaborate.cc,v 1.250 2002/05/26 01:39:02 steve Exp $"
 #endif
 
 # include "config.h"
@@ -2417,7 +2417,9 @@ bool Module::elaborate(Design*des, NetScope*scope) const
 	    (*gt)->elaborate(des, scope);
       }
 
-	// Elaborate the behaviors, making processes out of them.
+	// Elaborate the behaviors, making processes out of them. This
+	// involves scanning the PProcess* list, creating a NetProcTop
+	// for each process.
       const list<PProcess*>&sl = get_behaviors();
 
       for (list<PProcess*>::const_iterator st = sl.begin()
@@ -2440,6 +2442,21 @@ bool Module::elaborate(Design*des, NetScope*scope) const
 		  break;
 	    }
 
+	      // Evaluate the attributes for this process, if there
+	      // are any. These attributes are to be attached to the
+	      // NetProcTop object.
+	    struct attrib_list_t*attrib_list = 0;
+	    unsigned attrib_list_n = 0;
+	    attrib_list = evaluate_attributes((*st)->attributes,
+					      attrib_list_n,
+					      des, scope);
+
+	    for (unsigned adx = 0 ;  adx < attrib_list_n ;  adx += 1)
+		  top->attribute(attrib_list[adx].key,
+				 attrib_list[adx].val);
+
+	    delete[]attrib_list;
+
 	    top->set_line(*(*st));
 	    des->add_process(top);
       }
@@ -2551,6 +2568,13 @@ Design* elaborate(list<const char*>roots)
 
 /*
  * $Log: elaborate.cc,v $
+ * Revision 1.250  2002/05/26 01:39:02  steve
+ *  Carry Verilog 2001 attributes with processes,
+ *  all the way through to the ivl_target API.
+ *
+ *  Divide signal reference counts between rval
+ *  and lval references.
+ *
  * Revision 1.249  2002/05/23 03:08:51  steve
  *  Add language support for Verilog-2001 attribute
  *  syntax. Hook this support into existing $attribute
diff --git a/expr_synth.cc b/expr_synth.cc
index 28c1ceeb18..274fc8b13a 100644
--- a/expr_synth.cc
+++ b/expr_synth.cc
@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: expr_synth.cc,v 1.32 2002/05/23 03:08:51 steve Exp $"
+#ident "$Id: expr_synth.cc,v 1.33 2002/05/26 01:39:02 steve Exp $"
 #endif
 
 # include "config.h"
@@ -378,7 +378,7 @@ NetNet* NetEConcat::synthesize(Design*des)
 		  obit += 1;
 	    }
 
-	    if (tmp[idx-1]->local_flag() && tmp[idx-1]->get_eref() == 0)
+	    if (tmp[idx-1]->local_flag() && tmp[idx-1]->get_refs() == 0)
 		  delete tmp[idx-1];
       }
 
@@ -587,6 +587,13 @@ NetNet* NetESignal::synthesize(Design*des)
 
 /*
  * $Log: expr_synth.cc,v $
+ * Revision 1.33  2002/05/26 01:39:02  steve
+ *  Carry Verilog 2001 attributes with processes,
+ *  all the way through to the ivl_target API.
+ *
+ *  Divide signal reference counts between rval
+ *  and lval references.
+ *
  * Revision 1.32  2002/05/23 03:08:51  steve
  *  Add language support for Verilog-2001 attribute
  *  syntax. Hook this support into existing $attribute
diff --git a/ivl.def b/ivl.def
index 138ee8b075..0f916481da 100644
--- a/ivl.def
+++ b/ivl.def
@@ -131,6 +131,8 @@ ivl_signal_type
 ivl_signal_name
 ivl_signal_basename
 
+ivl_process_attr_cnt
+ivl_process_attr_val
 ivl_process_scope
 ivl_process_stmt
 ivl_process_type
diff --git a/ivl_target.h b/ivl_target.h
index b4546d4fe8..c0c812c98e 100644
--- a/ivl_target.h
+++ b/ivl_target.h
@@ -19,7 +19,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: ivl_target.h,v 1.96 2002/05/24 04:36:23 steve Exp $"
+#ident "$Id: ivl_target.h,v 1.97 2002/05/26 01:39:02 steve Exp $"
 #endif
 
 #ifdef __cplusplus
@@ -938,6 +938,9 @@ extern ivl_attribute_t ivl_signal_attr_val(ivl_signal_t net, unsigned idx);
  * The ivl_process_stmt function gets the statement that forms the
  * process. See the statement related functions for how to manipulate
  * statements.
+ *
+ * Processes can have attributes attached to them. the attr_cnt and
+ * attr_val methods return those attributes.
  */
 extern ivl_process_type_t ivl_process_type(ivl_process_t net);
 
@@ -945,6 +948,9 @@ extern ivl_scope_t ivl_process_scope(ivl_process_t net);
 
 extern ivl_statement_t ivl_process_stmt(ivl_process_t net);
 
+extern unsigned        ivl_process_attr_cnt(ivl_process_t net);
+extern ivl_attribute_t ivl_process_attr_val(ivl_process_t net, unsigned idx);
+
 /*
  * These functions manage statements of various type. This includes
  * all the different kinds of statements (as enumerated in
@@ -1037,6 +1043,13 @@ _END_DECL
 
 /*
  * $Log: ivl_target.h,v $
+ * Revision 1.97  2002/05/26 01:39:02  steve
+ *  Carry Verilog 2001 attributes with processes,
+ *  all the way through to the ivl_target API.
+ *
+ *  Divide signal reference counts between rval
+ *  and lval references.
+ *
  * Revision 1.96  2002/05/24 04:36:23  steve
  *  Verilog 2001 attriubtes on nets/wires.
  *
diff --git a/net_assign.cc b/net_assign.cc
index cd3f32de3d..ef418219fc 100644
--- a/net_assign.cc
+++ b/net_assign.cc
@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: net_assign.cc,v 1.9 2002/04/21 22:31:02 steve Exp $"
+#ident "$Id: net_assign.cc,v 1.10 2002/05/26 01:39:02 steve Exp $"
 #endif
 
 # include "config.h"
@@ -43,13 +43,13 @@ NetAssign_::NetAssign_(NetNet*s)
 {
       loff_ = 0;
       lwid_ = sig_->pin_count();
-      sig_->incr_eref();
+      sig_->incr_lref();
       more = 0;
 }
 
 NetAssign_::~NetAssign_()
 {
-      if (sig_) sig_->decr_eref();
+      if (sig_) sig_->decr_lref();
       assert( more == 0 );
       if (bmux_) delete bmux_;
 }
@@ -210,6 +210,13 @@ NetAssignNB::~NetAssignNB()
 
 /*
  * $Log: net_assign.cc,v $
+ * Revision 1.10  2002/05/26 01:39:02  steve
+ *  Carry Verilog 2001 attributes with processes,
+ *  all the way through to the ivl_target API.
+ *
+ *  Divide signal reference counts between rval
+ *  and lval references.
+ *
  * Revision 1.9  2002/04/21 22:31:02  steve
  *  Redo handling of assignment internal delays.
  *  Leave it possible for them to be calculated
diff --git a/netlist.cc b/netlist.cc
index e45daa957c..ba1a8b3e58 100644
--- a/netlist.cc
+++ b/netlist.cc
@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: netlist.cc,v 1.186 2002/05/23 03:08:51 steve Exp $"
+#ident "$Id: netlist.cc,v 1.187 2002/05/26 01:39:02 steve Exp $"
 #endif
 
 # include "config.h"
@@ -205,37 +205,6 @@ const NetScope* NetObj::scope() const
       return scope_;
 }
 
-const verinum& NetObj::attribute(const string&key) const
-{
-      return attributes_.attribute(key);
-}
-
-void NetObj::attribute(const string&key, const verinum&value)
-{
-      attributes_.attribute(key, value);
-}
-
-bool NetObj::has_compat_attributes(const NetObj&that) const
-{
-      return attributes_.has_compat_attributes(that.attributes_);
-}
-
-unsigned NetObj::nattr() const
-{
-      return attributes_.size();
-}
-
-const char* NetObj::attr_key(unsigned idx) const
-{
-      return attributes_.key(idx).c_str();
-}
-
-const verinum& NetObj::attr_value(unsigned idx) const
-{
-      return attributes_.value(idx);
-}
-
-
 Link& NetObj::pin(unsigned idx)
 {
       assert(idx < npins_);
@@ -297,7 +266,7 @@ NetNode* NetNode::next_node()
 NetNet::NetNet(NetScope*s, const string&n, Type t, unsigned npins)
 : NetObj(s, n, npins), sig_next_(0), sig_prev_(0),
     type_(t), port_type_(NOT_A_PORT), signed_(false), msb_(npins-1), lsb_(0),
-    local_flag_(false), eref_count_(0)
+    local_flag_(false), eref_count_(0), lref_count_(0)
 {
       assert(s);
 
@@ -335,7 +304,7 @@ NetNet::NetNet(NetScope*s, const string&n, Type t, long ms, long ls)
 : NetObj(s, n, ((ms>ls)?ms-ls:ls-ms) + 1), sig_next_(0),
     sig_prev_(0), type_(t),
     port_type_(NOT_A_PORT), signed_(false), msb_(ms), lsb_(ls),
-    local_flag_(false), eref_count_(0)
+    local_flag_(false), eref_count_(0), lref_count_(0)
 {
       assert(s);
 
@@ -378,6 +347,13 @@ NetNet::~NetNet()
 	    dump_net(cerr, 4);
       }
       assert(eref_count_ == 0);
+      if (lref_count_ > 0) {
+	    cerr << get_line() << ": internal error: attempt to delete "
+		 << "signal ``" << name() << "'' which has "
+		 << "assign references." << endl;
+	    dump_net(cerr, 4);
+      }
+      assert(lref_count_ == 0);
       if (scope())
 	    scope()->rem_signal(this);
 }
@@ -436,11 +412,33 @@ void NetNet::decr_eref()
       eref_count_ -= 1;
 }
 
-unsigned NetNet::get_eref() const
+unsigned NetNet::peek_eref() const
 {
       return eref_count_;
 }
 
+void NetNet::incr_lref()
+{
+      lref_count_ += 1;
+}
+
+void NetNet::decr_lref()
+{
+      assert(lref_count_ > 0);
+      lref_count_ -= 1;
+}
+
+unsigned NetNet::peek_lref() const
+{
+      return lref_count_;
+}
+
+unsigned NetNet::get_refs() const
+{
+      return lref_count_ + eref_count_;
+}
+
+
 NetTmp::NetTmp(NetScope*s, const string&name, unsigned npins)
 : NetNet(s, name, IMPLICIT, npins)
 {
@@ -2354,6 +2352,13 @@ const NetProc*NetTaskDef::proc() const
 
 /*
  * $Log: netlist.cc,v $
+ * Revision 1.187  2002/05/26 01:39:02  steve
+ *  Carry Verilog 2001 attributes with processes,
+ *  all the way through to the ivl_target API.
+ *
+ *  Divide signal reference counts between rval
+ *  and lval references.
+ *
  * Revision 1.186  2002/05/23 03:08:51  steve
  *  Add language support for Verilog-2001 attribute
  *  syntax. Hook this support into existing $attribute
diff --git a/netlist.h b/netlist.h
index 13ef7080db..7cb55b727d 100644
--- a/netlist.h
+++ b/netlist.h
@@ -19,7 +19,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: netlist.h,v 1.237 2002/05/23 03:08:51 steve Exp $"
+#ident "$Id: netlist.h,v 1.238 2002/05/26 01:39:02 steve Exp $"
 #endif
 
 /*
@@ -78,7 +78,7 @@ struct functor_t;
  * interpretation of the rise/fall/decay times is typically left to
  * the target to properly interpret.
  */
-class NetObj {
+class NetObj  : public Attrib {
 
     public:
     public:
@@ -101,17 +101,6 @@ class NetObj {
       void fall_time(unsigned d) { delay2_ = d; }
       void decay_time(unsigned d) { delay3_ = d; }
 
-      const verinum& attribute(const string&key) const;
-      void attribute(const string&key, const verinum&value);
-
-	// Return true if this has all the attributes in that and they
-	// all have the same values.
-      bool has_compat_attributes(const NetObj&that) const;
-
-      unsigned nattr() const;
-      const char* attr_key(unsigned) const;
-      const verinum& attr_value(unsigned) const;
-
       Link&pin(unsigned idx);
       const Link&pin(unsigned idx) const;
 
@@ -126,8 +115,6 @@ class NetObj {
       unsigned delay1_;
       unsigned delay2_;
       unsigned delay3_;
-
-      Attrib attributes_;
 };
 
 class Link {
@@ -392,8 +379,14 @@ class NetNet  : public NetObj, public LineInfo {
 	   reference count so that I keep track of them. */
       void incr_eref();
       void decr_eref();
-      unsigned get_eref() const;
+      unsigned peek_eref() const;
 
+	/* Assignment statements count their lrefs here. */
+      void incr_lref();
+      void decr_lref();
+      unsigned peek_lref() const;
+
+      unsigned get_refs() const;
 
       virtual void dump_net(ostream&, unsigned) const;
 
@@ -411,6 +404,7 @@ class NetNet  : public NetObj, public LineInfo {
 
       bool local_flag_;
       unsigned eref_count_;
+      unsigned lref_count_;
 };
 
 /*
@@ -2067,7 +2061,7 @@ class NetWhile  : public NetProc {
  * always) and a pointer to the statement, probably a block, that
  * makes up the process.
  */
-class NetProcTop  : public LineInfo {
+class NetProcTop  : public LineInfo, public Attrib {
 
     public:
       enum Type { KINITIAL, KALWAYS };
@@ -2979,6 +2973,13 @@ extern ostream& operator << (ostream&, NetNet::Type);
 
 /*
  * $Log: netlist.h,v $
+ * Revision 1.238  2002/05/26 01:39:02  steve
+ *  Carry Verilog 2001 attributes with processes,
+ *  all the way through to the ivl_target API.
+ *
+ *  Divide signal reference counts between rval
+ *  and lval references.
+ *
  * Revision 1.237  2002/05/23 03:08:51  steve
  *  Add language support for Verilog-2001 attribute
  *  syntax. Hook this support into existing $attribute
diff --git a/nodangle.cc b/nodangle.cc
index 01ef9f1c9d..d162233f02 100644
--- a/nodangle.cc
+++ b/nodangle.cc
@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: nodangle.cc,v 1.14 2002/02/02 06:13:38 steve Exp $"
+#ident "$Id: nodangle.cc,v 1.15 2002/05/26 01:39:02 steve Exp $"
 #endif
 
 # include "config.h"
@@ -57,8 +57,9 @@ void nodangle_f::event(Design*des, NetEvent*ev)
 
 void nodangle_f::signal(Design*des, NetNet*sig)
 {
-	/* Cannot delete signals referenced in an expression. */
-      if (sig->get_eref() > 0)
+	/* Cannot delete signals referenced in an expression
+	   or an l-value. */
+      if (sig->get_refs() > 0)
 	    return;
 
 	/* Cannot delete the ports of tasks or functions. There are
@@ -131,6 +132,13 @@ void nodangle(Design*des)
 
 /*
  * $Log: nodangle.cc,v $
+ * Revision 1.15  2002/05/26 01:39:02  steve
+ *  Carry Verilog 2001 attributes with processes,
+ *  all the way through to the ivl_target API.
+ *
+ *  Divide signal reference counts between rval
+ *  and lval references.
+ *
  * Revision 1.14  2002/02/02 06:13:38  steve
  *  event find_similar should not find self.
  *
diff --git a/parse.y b/parse.y
index 0addd8d6de..1d0d737f8b 100644
--- a/parse.y
+++ b/parse.y
@@ -19,7 +19,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: parse.y,v 1.153 2002/05/24 04:36:23 steve Exp $"
+#ident "$Id: parse.y,v 1.154 2002/05/26 01:39:02 steve Exp $"
 #endif
 
 # include "config.h"
@@ -1443,15 +1443,20 @@ module_item
 
 	| K_assign drive_strength_opt delay3_opt assign_list ';'
 		{ pform_make_pgassign_list($4, $3, $2, @1.text, @1.first_line); }
-	| K_always statement
-		{ PProcess*tmp = pform_make_behavior(PProcess::PR_ALWAYS, $2);
-		  tmp->set_file(@1.text);
-		  tmp->set_lineno(@1.first_line);
+
+  /* Always and initial items are behavioral processes. */
+
+	| attribute_list_opt K_always statement
+		{ PProcess*tmp = pform_make_behavior(PProcess::PR_ALWAYS,
+						     $3, $1);
+		  tmp->set_file(@2.text);
+		  tmp->set_lineno(@2.first_line);
 		}
-	| K_initial statement
-		{ PProcess*tmp = pform_make_behavior(PProcess::PR_INITIAL, $2);
-		  tmp->set_file(@1.text);
-		  tmp->set_lineno(@1.first_line);
+	| attribute_list_opt K_initial statement
+		{ PProcess*tmp = pform_make_behavior(PProcess::PR_INITIAL,
+						     $3, $1);
+		  tmp->set_file(@2.text);
+		  tmp->set_lineno(@2.first_line);
 		}
 
   /* The task declaration rule matches the task declaration
diff --git a/pform.cc b/pform.cc
index f95756542c..6ee85c26d8 100644
--- a/pform.cc
+++ b/pform.cc
@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: pform.cc,v 1.97 2002/05/24 04:36:23 steve Exp $"
+#ident "$Id: pform.cc,v 1.98 2002/05/26 01:39:02 steve Exp $"
 #endif
 
 # include "config.h"
@@ -1289,9 +1289,19 @@ svector<PWire*>* pform_make_udp_input_ports(list<char*>*names)
       return out;
 }
 
-PProcess* pform_make_behavior(PProcess::Type type, Statement*st)
+PProcess* pform_make_behavior(PProcess::Type type, Statement*st,
+			      svector<named_pexpr_t*>*attr)
 {
       PProcess*pp = new PProcess(type, st);
+
+      if (attr) {
+	    for (unsigned idx = 0 ;  idx < attr->count() ;  idx += 1) {
+		  named_pexpr_t*tmp = (*attr)[idx];
+		  pp->attributes[tmp->name] = tmp->parm;
+	    }
+	    delete attr;
+      }
+
       pform_cur_module->add_behavior(pp);
       return pp;
 }
@@ -1337,6 +1347,13 @@ int pform_parse(const char*path, FILE*file)
 
 /*
  * $Log: pform.cc,v $
+ * Revision 1.98  2002/05/26 01:39:02  steve
+ *  Carry Verilog 2001 attributes with processes,
+ *  all the way through to the ivl_target API.
+ *
+ *  Divide signal reference counts between rval
+ *  and lval references.
+ *
  * Revision 1.97  2002/05/24 04:36:23  steve
  *  Verilog 2001 attriubtes on nets/wires.
  *
diff --git a/pform.h b/pform.h
index 410dead719..44addec6db 100644
--- a/pform.h
+++ b/pform.h
@@ -19,7 +19,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: pform.h,v 1.59 2002/05/24 04:36:23 steve Exp $"
+#ident "$Id: pform.h,v 1.60 2002/05/26 01:39:02 steve Exp $"
 #endif
 
 # include  "netlist.h"
@@ -199,7 +199,13 @@ extern void pform_set_type_attrib(const string&name, const string&key,
 extern void pform_set_parameter(const string&name, PExpr*expr);
 extern void pform_set_localparam(const string&name, PExpr*expr);
 extern void pform_set_defparam(const hname_t&name, PExpr*expr);
-extern PProcess*  pform_make_behavior(PProcess::Type, Statement*);
+
+/*
+ * pform_make_behavior creates processes that are declared with always
+ * or initial items.
+ */
+extern PProcess*  pform_make_behavior(PProcess::Type, Statement*,
+				      svector<named_pexpr_t*>*attr);
 
 extern svector<PWire*>* pform_make_udp_input_ports(list<char*>*);
 
@@ -250,6 +256,13 @@ extern void pform_dump(ostream&out, Module*mod);
 
 /*
  * $Log: pform.h,v $
+ * Revision 1.60  2002/05/26 01:39:02  steve
+ *  Carry Verilog 2001 attributes with processes,
+ *  all the way through to the ivl_target API.
+ *
+ *  Divide signal reference counts between rval
+ *  and lval references.
+ *
  * Revision 1.59  2002/05/24 04:36:23  steve
  *  Verilog 2001 attriubtes on nets/wires.
  *
diff --git a/pform_dump.cc b/pform_dump.cc
index ef6efe92cd..0a6cb2ab72 100644
--- a/pform_dump.cc
+++ b/pform_dump.cc
@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: pform_dump.cc,v 1.73 2002/05/24 04:36:23 steve Exp $"
+#ident "$Id: pform_dump.cc,v 1.74 2002/05/26 01:39:02 steve Exp $"
 #endif
 
 # include "config.h"
@@ -674,6 +674,16 @@ void PProcess::dump(ostream&out, unsigned ind) const
 
       out << " /* " << get_line() << " */" << endl;
 
+      for (map<string,PExpr*>::const_iterator idx = attributes.begin()
+		 ; idx != attributes.end() ; idx++ ) {
+
+	    out << setw(ind+2) << "" << "(* " << (*idx).first;
+	    if ((*idx).second) {
+		  out << " = " << *(*idx).second;
+	    }
+	    out << " *)" << endl;
+      }
+
       statement_->dump(out, ind+2);
 }
 
@@ -828,6 +838,13 @@ void PUdp::dump(ostream&out) const
 
 /*
  * $Log: pform_dump.cc,v $
+ * Revision 1.74  2002/05/26 01:39:02  steve
+ *  Carry Verilog 2001 attributes with processes,
+ *  all the way through to the ivl_target API.
+ *
+ *  Divide signal reference counts between rval
+ *  and lval references.
+ *
  * Revision 1.73  2002/05/24 04:36:23  steve
  *  Verilog 2001 attriubtes on nets/wires.
  *
diff --git a/t-dll-api.cc b/t-dll-api.cc
index 7eaca3f411..1a06ebafef 100644
--- a/t-dll-api.cc
+++ b/t-dll-api.cc
@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: t-dll-api.cc,v 1.79 2002/05/24 04:36:23 steve Exp $"
+#ident "$Id: t-dll-api.cc,v 1.80 2002/05/26 01:39:03 steve Exp $"
 #endif
 
 # include "config.h"
@@ -993,6 +993,18 @@ extern "C" ivl_statement_t ivl_process_stmt(ivl_process_t net)
       return net->stmt_;
 }
 
+extern "C" unsigned ivl_process_attr_cnt(ivl_process_t net)
+{
+      return net->nattr;
+}
+
+extern "C" ivl_attribute_t ivl_process_attr_val(ivl_process_t net,
+						unsigned idx)
+{
+      assert(idx < net->nattr);
+      return net->attr + idx;
+}
+
 extern "C" const char* ivl_scope_basename(ivl_scope_t net)
 {
       assert(net);
@@ -1519,6 +1531,13 @@ extern "C" ivl_statement_t ivl_stmt_sub_stmt(ivl_statement_t net)
 
 /*
  * $Log: t-dll-api.cc,v $
+ * Revision 1.80  2002/05/26 01:39:03  steve
+ *  Carry Verilog 2001 attributes with processes,
+ *  all the way through to the ivl_target API.
+ *
+ *  Divide signal reference counts between rval
+ *  and lval references.
+ *
  * Revision 1.79  2002/05/24 04:36:23  steve
  *  Verilog 2001 attriubtes on nets/wires.
  *
diff --git a/t-dll-proc.cc b/t-dll-proc.cc
index 84f9552a43..e2b0c32365 100644
--- a/t-dll-proc.cc
+++ b/t-dll-proc.cc
@@ -18,7 +18,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: t-dll-proc.cc,v 1.42 2002/04/21 22:31:02 steve Exp $"
+#ident "$Id: t-dll-proc.cc,v 1.43 2002/05/26 01:39:03 steve Exp $"
 #endif
 
 # include "config.h"
@@ -54,6 +54,8 @@ bool dll_target::process(const NetProcTop*net)
 	/* Save the scope of the process. */
       obj->scope_ = lookup_scope_(net->scope());
 
+      obj->nattr = net->attr_cnt();
+      obj->attr = fill_in_attributes(net);
 
 	/* This little bit causes the process to be completely
 	   generated so that it can be passed to the DLL. The
@@ -806,6 +808,13 @@ void dll_target::proc_while(const NetWhile*net)
 
 /*
  * $Log: t-dll-proc.cc,v $
+ * Revision 1.43  2002/05/26 01:39:03  steve
+ *  Carry Verilog 2001 attributes with processes,
+ *  all the way through to the ivl_target API.
+ *
+ *  Divide signal reference counts between rval
+ *  and lval references.
+ *
  * Revision 1.42  2002/04/21 22:31:02  steve
  *  Redo handling of assignment internal delays.
  *  Leave it possible for them to be calculated
diff --git a/t-dll.cc b/t-dll.cc
index 7f4e5bdfc4..a12d13b580 100644
--- a/t-dll.cc
+++ b/t-dll.cc
@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: t-dll.cc,v 1.83 2002/05/24 04:36:23 steve Exp $"
+#ident "$Id: t-dll.cc,v 1.84 2002/05/26 01:39:03 steve Exp $"
 #endif
 
 # include "config.h"
@@ -135,10 +135,10 @@ static void drive_from_link(const Link&lnk, ivl_drive_t&drv0, ivl_drive_t&drv1)
       }
 }
 
-static ivl_attribute_s* fill_in_attributes(const NetObj*net)
+ivl_attribute_s* dll_target::fill_in_attributes(const Attrib*net)
 {
       ivl_attribute_s*attr;
-      unsigned nattr = net->nattr();
+      unsigned nattr = net->attr_cnt();
 
       if (nattr == 0)
 	    return 0;
@@ -504,8 +504,8 @@ int dll_target::end_design(const Design*)
 static void logic_attributes(struct ivl_net_logic_s *obj,
 			     const NetNode*net)
 {
-      obj->nattr = net->nattr();
-      obj->attr = fill_in_attributes(net);
+      obj->nattr = net->attr_cnt();
+      obj->attr = dll_target::fill_in_attributes(net);
 }
 
 /*
@@ -1893,7 +1893,7 @@ void dll_target::signal(const NetNet*net)
 	    break;
       }
 
-      obj->nattr = net->nattr();
+      obj->nattr = net->attr_cnt();
       obj->attr = fill_in_attributes(net);
 
 
@@ -1946,6 +1946,13 @@ extern const struct target tgt_dll = { "dll", &dll_target_obj };
 
 /*
  * $Log: t-dll.cc,v $
+ * Revision 1.84  2002/05/26 01:39:03  steve
+ *  Carry Verilog 2001 attributes with processes,
+ *  all the way through to the ivl_target API.
+ *
+ *  Divide signal reference counts between rval
+ *  and lval references.
+ *
  * Revision 1.83  2002/05/24 04:36:23  steve
  *  Verilog 2001 attriubtes on nets/wires.
  *
diff --git a/t-dll.h b/t-dll.h
index 25f6ad85a8..b2c84ea80f 100644
--- a/t-dll.h
+++ b/t-dll.h
@@ -19,7 +19,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: t-dll.h,v 1.78 2002/05/24 04:36:23 steve Exp $"
+#ident "$Id: t-dll.h,v 1.79 2002/05/26 01:39:03 steve Exp $"
 #endif
 
 # include  "target.h"
@@ -143,10 +143,13 @@ struct dll_target  : public target_t, public expr_scan_t {
       ivl_scope_t lookup_scope_(const NetScope*scope);
       ivl_memory_t lookup_memory_(const NetMemory*mem);
 
+      static ivl_attribute_s* fill_in_attributes(const Attrib*net);
+
     private:
       static ivl_scope_t find_scope(ivl_design_s &des, const NetScope*cur);
       static ivl_signal_t find_signal(ivl_design_s &des, const NetNet*net);
       void add_root(ivl_design_s &des_, const NetScope *s);
+
 };
 
 /*
@@ -447,6 +450,9 @@ struct ivl_process_s {
       ivl_scope_t scope_;
       ivl_statement_t stmt_;
 
+      struct ivl_attribute_s*attr;
+      unsigned nattr;
+
       ivl_process_t next_;
 };
 
@@ -597,6 +603,13 @@ struct ivl_statement_s {
 
 /*
  * $Log: t-dll.h,v $
+ * Revision 1.79  2002/05/26 01:39:03  steve
+ *  Carry Verilog 2001 attributes with processes,
+ *  all the way through to the ivl_target API.
+ *
+ *  Divide signal reference counts between rval
+ *  and lval references.
+ *
  * Revision 1.78  2002/05/24 04:36:23  steve
  *  Verilog 2001 attriubtes on nets/wires.
  *
diff --git a/tgt-stub/stub.c b/tgt-stub/stub.c
index 6ebe23d479..489553a999 100644
--- a/tgt-stub/stub.c
+++ b/tgt-stub/stub.c
@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: stub.c,v 1.59 2002/05/24 04:36:23 steve Exp $"
+#ident "$Id: stub.c,v 1.60 2002/05/26 01:39:03 steve Exp $"
 #endif
 
 # include "config.h"
@@ -382,6 +382,8 @@ static void show_statement(ivl_statement_t net, unsigned ind)
 
 static int show_process(ivl_process_t net, void*x)
 {
+      unsigned idx;
+
       switch (ivl_process_type(net)) {
 	  case IVL_PR_INITIAL:
 	    fprintf(out, "initial\n");
@@ -391,6 +393,23 @@ static int show_process(ivl_process_t net, void*x)
 	    break;
       }
 
+      for (idx = 0 ;  idx < ivl_process_attr_cnt(net) ;  idx += 1) {
+	    ivl_attribute_t attr = ivl_process_attr_val(net, idx);
+	    switch (attr->type) {
+		case IVL_ATT_VOID:
+		  fprintf(out, "    (* %s *)\n", attr->key);
+		  break;
+		case IVL_ATT_STR:
+		  fprintf(out, "    (* %s = \"%s\" *)\n", attr->key,
+			  attr->val.str);
+		  break;
+		case IVL_ATT_NUM:
+		  fprintf(out, "    (* %s = %ld *)\n", attr->key,
+			  attr->val.num);
+		  break;
+	    }
+      }
+
       show_statement(ivl_process_stmt(net), 4);
 
       return 0;
@@ -663,6 +682,13 @@ int target_design(ivl_design_t des)
 
 /*
  * $Log: stub.c,v $
+ * Revision 1.60  2002/05/26 01:39:03  steve
+ *  Carry Verilog 2001 attributes with processes,
+ *  all the way through to the ivl_target API.
+ *
+ *  Divide signal reference counts between rval
+ *  and lval references.
+ *
  * Revision 1.59  2002/05/24 04:36:23  steve
  *  Verilog 2001 attriubtes on nets/wires.
  *