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Spelling fixes.

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1 parent 4641966 commit cadf4cfdef5a8eae07f2ebd9831f6412d8c52c4e steve committed Jul 15, 2003
Showing with 49 additions and 28 deletions.
  1. +5 −2 PUdp.h
  2. +5 −5 README.txt
  3. +5 −2 dosify.c
  4. +1 −1 driver-vpi/res.rc
  5. +5 −2 elab_sig.cc
  6. +1 −1 examples/xnf_add.vl
  7. +5 −2 ieee1364-notes.txt
  8. +2 −2 iverilog-vpi.man
  9. +2 −2 iverilog.conf
  10. +3 −3 mingw.txt
  11. +5 −2 netlist.h
  12. +1 −1 swift.txt
  13. +5 −2 vpi_user.h
  14. +4 −1 xnf.txt
View
7 PUdp.h
@@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
-#ident "$Id: PUdp.h,v 1.8 2003/01/30 16:23:07 steve Exp $"
+#ident "$Id: PUdp.h,v 1.9 2003/07/15 03:49:22 steve Exp $"
#endif
# include <map>
@@ -38,7 +38,7 @@ svector<string>::svector<string>(unsigned size)
* This class represents a parsed UDP. This is a much simpler object
* then a module or macromodule.
*
- * - all ports are scaler,
+ * - all ports are scalar,
* - pin 0 (the first port) is always output,
* and the remaining pins are input.
*
@@ -84,6 +84,9 @@ class PUdp {
/*
* $Log: PUdp.h,v $
+ * Revision 1.9 2003/07/15 03:49:22 steve
+ * Spelling fixes.
+ *
* Revision 1.8 2003/01/30 16:23:07 steve
* Spelling fixes.
*
View
@@ -76,7 +76,7 @@ with the commands:
./configure
make
-Normally, this command automatically figures out every thing it needs
+Normally, this command automatically figures out everything it needs
to know. It generally works pretty well. There are a few flags to the
configure script that modify its behavior:
@@ -138,14 +138,14 @@ only sees a single input file. See ivlpp/ivlpp.txt for details.
3.2 Parse
The Verilog compiler starts by parsing the Verilog source file. The
-output of the parse in a list of Module objects in PFORM. The pform
+output of the parse is a list of Module objects in "pform". The pform
(see pform.h) is mostly a direct reflection of the compilation
step. There may be dangling references, and it is not yet clear which
module is the root.
-One can see a human readable version of the final PFORM by using the
+One can see a human readable version of the final pform by using the
``-P <path>'' flag to the compiler. This will cause iverilog to dump
-the PFORM into the file named <path>.
+the pform into the file named <path>.
3.3 Elaboration
@@ -407,7 +407,7 @@ language that are defined.
completely specify the format.
Icarus Verilog allows the programmer to specify the field
- with. The "%t" format in Icarus Verilog works exactly as it
+ width. The "%t" format in Icarus Verilog works exactly as it
does in standard Verilog. However, if the programmer chooses
to specify a minimum width (i.e., "%5t"), then for that display
Icarus Verilog will override the $timeformat minimum width and
View
@@ -16,8 +16,8 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
-#ifdef HAVE_CVS_IDENT
-#ident "$Id: dosify.c,v 1.3 2002/08/12 01:34:58 steve Exp $"
+#ivied HAVE_CVS_IDENT
+#ident "$Id: dosify.c,v 1.4 2003/07/15 03:49:22 steve Exp $"
#endif
/*
@@ -69,6 +69,9 @@ int main(int argc, char*argv[])
/*
* $Log: dosify.c,v $
+ * Revision 1.4 2003/07/15 03:49:22 steve
+ * Spelling fixes.
+ *
* Revision 1.3 2002/08/12 01:34:58 steve
* conditional ident string using autoconfig.
*
View
@@ -22,7 +22,7 @@ BEGIN
BLOCK "040904b0"
BEGIN
VALUE "CompanyName", "Icarus Verilog\0"
- VALUE "FileDescription", "Icarus Veriog VPI Tool\0"
+ VALUE "FileDescription", "Icarus Verilog VPI Tool\0"
VALUE "FileVersion", "2002, 11, 13, 0\0"
VALUE "InternalName", "iverilog-vpi\0"
VALUE "LegalCopyright", "Copyright 2002 Gus Baldauf\0"
View
@@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
-#ident "$Id: elab_sig.cc,v 1.30 2003/06/24 01:38:02 steve Exp $"
+#ident "$Id: elab_sig.cc,v 1.31 2003/07/15 03:49:22 steve Exp $"
#endif
# include "config.h"
@@ -391,7 +391,7 @@ void PWire::elaborate_sig(Design*des, NetScope*scope) const
svector<long>mnum (msb_.count());
svector<long>lnum (msb_.count());
/* There may be places where the signal is declared as a
- scaler. Count those here, for consistency check
+ scalar. Count those here, for consistency check
later. */
unsigned count_scalars = 0;
@@ -524,6 +524,9 @@ void PWire::elaborate_sig(Design*des, NetScope*scope) const
/*
* $Log: elab_sig.cc,v $
+ * Revision 1.31 2003/07/15 03:49:22 steve
+ * Spelling fixes.
+ *
* Revision 1.30 2003/06/24 01:38:02 steve
* Various warnings fixed.
*
View
@@ -72,7 +72,7 @@ module main;
// These attribute commands assign pins to the listed wires.
// This can be done to wires and registers, as internally both
// are treated as named signals. It doesn't work (yet) on vectors,
- // though, so break out the vectors with scaler assignments.
+ // though, so break out the vectors with scalar assignments.
assign a[0] = a0;
assign a[1] = a1;
View
@@ -435,7 +435,7 @@ bit and part selects.
* EDGES OF VECTORS
-Consider this exapmle:
+Consider this example:
reg [ 5:0] clock;
always @(posedge clock) [do stuff]
@@ -498,8 +498,11 @@ of 4-value behavior in the dead zone, and appears more user friendly
when viewed by reasonable viewers.
-$Id: ieee1364-notes.txt,v 1.16 2003/04/14 03:40:21 steve Exp $
+$Id: ieee1364-notes.txt,v 1.17 2003/07/15 03:49:22 steve Exp $
$Log: ieee1364-notes.txt,v $
+Revision 1.17 2003/07/15 03:49:22 steve
+ Spelling fixes.
+
Revision 1.16 2003/04/14 03:40:21 steve
Make some effort to preserve bits while
operating on constant values.
View
@@ -1,4 +1,4 @@
-.TH iverilog-vpi 1 "$Date: 2002/11/23 00:51:53 $" Version "$Date: 2002/11/23 00:51:53 $"
+.TH iverilog-vpi 1 "$Date: 2003/07/15 03:49:22 $" Version "$Date: 2003/07/15 03:49:22 $"
.SH NAME
iverilog-vpi - Compile front end for VPI modules
@@ -44,7 +44,7 @@ the program locate parts that it needs.
Tell the program the root of the Mingw compiler tool suite. The
\fBvvp\fP runtime is compiled with this compiler, and this is the
compiler that \fIiverilog-vpi\fP expects to use to compile your source
-code. This is notmally not needed, and if you do use it, it is only
+code. This is normally not needed, and if you do use it, it is only
needed once. The compiler will save the \fIpath\fP in the registry for
use later.
View
@@ -32,7 +32,7 @@
#
# %f Substitute the -f flags from the command line.
#
-# %g Substitule the -g flag
+# %g Substitute the -g flag
#
# %s Substitute the start module (-s flag) from the user.
#
@@ -57,7 +57,7 @@
# terminated by a ``]'' character.
-# This is the null (no op) target. Thre is a synthesis version and a
+# This is the null (no op) target. There is a synthesis version and a
# non-synthesis version. Normally, this does not matter, but this can
# be useful and interesting if the -N flag is included.
View
@@ -26,7 +26,7 @@ of any support for software development. Everything needed to compile
Icarus Verilog must be collected from various sources and stitched
together by hand. Normal human beings with a basic understanding of
software development can do this, but some patience (and access to the
-internet) is required. You may choose to print these instructions.
+Internet) is required. You may choose to print these instructions.
I have no plans to intentionally support MSVC++ compilation. Don't ask.
@@ -229,7 +229,7 @@ details. Run these commands:
Your PATH variable was set in the previous step.
- Use forward slashes as directory charactors. All the various
+ Use forward slashes as directory characters. All the various
tools prefer the forward slash.
Substitute your chosen directory for the prefix. This will cause the
@@ -264,7 +264,7 @@ This is part of what the configure program did for you. The Makefiles
now know to put the files under the D:\iverilog directory (or whatever
directory you chose) and away you go.
-You may find that you need to put some of the prerequisite DLLS into
+You may find that you need to put some of the prerequisite DLLs into
the d:\iverilog\bin directory. These include:
d:\mingw-2.0.0\bin\mingw10.dll
View
@@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
-#ident "$Id: netlist.h,v 1.293 2003/07/02 04:19:16 steve Exp $"
+#ident "$Id: netlist.h,v 1.294 2003/07/15 03:49:22 steve Exp $"
#endif
/*
@@ -343,7 +343,7 @@ class NetNode : public NetObj {
/*
* NetNet is a special kind of NetObj that doesn't really do anything,
* but carries the properties of the wire/reg/trireg, including its
- * name. A scaler wire is a NetNet with one pin, a vector a wider
+ * name. A scalar wire is a NetNet with one pin, a vector a wider
* NetNet. NetNet objects also appear as side effects of synthesis or
* other abstractions.
*
@@ -3309,6 +3309,9 @@ extern ostream& operator << (ostream&, NetNet::Type);
/*
* $Log: netlist.h,v $
+ * Revision 1.294 2003/07/15 03:49:22 steve
+ * Spelling fixes.
+ *
* Revision 1.293 2003/07/02 04:19:16 steve
* Elide empty begin-end in conditionals.
*
View
@@ -20,7 +20,7 @@ in your SWIFT model documentation.
* Compilation
-When compiling your Veriog design to include a SWIFT model, you need
+When compiling your Verilog design to include a SWIFT model, you need
to include wrappers for the model you intend to use. You may choose to
use ncverilog or verilogxl compatible wrappers, they work the
same. Locate your smartmodel directory, and include it in your command
View
@@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
-#ident "$Id: vpi_user.h,v 1.28 2003/06/04 01:56:20 steve Exp $"
+#ident "$Id: vpi_user.h,v 1.29 2003/07/15 03:49:22 steve Exp $"
#endif
@@ -391,14 +391,17 @@ extern DLLEXPORT void (*vlog_startup_routines[])();
* manner of the $display system task.
*/
- /* Format a scaler a la %v. The str points to a 4byte character
+ /* Format a scalar a la %v. The str points to a 4byte character
buffer. The value must be a vpiStrengthVal. */
extern void vpip_format_strength(char*str, s_vpi_value*value);
EXTERN_C_END
/*
* $Log: vpi_user.h,v $
+ * Revision 1.29 2003/07/15 03:49:22 steve
+ * Spelling fixes.
+ *
* Revision 1.28 2003/06/04 01:56:20 steve
* 1) Adds configure logic to clean up compiler warnings
* 2) adds acc_compare_handle, acc_fetch_range, acc_next_scope and
View
@@ -51,7 +51,7 @@ be accounted for as well.
XNF PADS IN VERILOG SOURCE
You can assign wires to pads using the Icarus Verilog $attribute
-extension. Attach to a scaler signal (wire or register) the PAD
+extension. Attach to a scalar signal (wire or register) the PAD
attribute with the value that specifies the direction and pin
number. For example:
@@ -245,6 +245,9 @@ IBUF, NOT gates cannot be absorbed as in the OPAD case.
$Log: xnf.txt,v $
+ Revision 1.16 2003/07/15 03:49:22 steve
+ Spelling fixes.
+
Revision 1.15 2003/01/30 16:23:08 steve
Spelling fixes.

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