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Spelling fixes

Mostly then/than confusion.  All comments or README files,
except for one user-visible change in a tgt-vlog95 error message.
  • Loading branch information...
commit e9fda22ad955bbd103d4b5726441f6f9c85fd50d 1 parent 98f5ed2
Larry Doolittle ldoolitt authored committed
6 BUGS.txt
View
@@ -54,7 +54,7 @@ So, if your program doesn't compile, tell me so, tell me where the
error occurs, and include a complete Perfectly Valid Test Program(tm).
You tell me that it fails to compile for you, and I find that it
compiles for me, then hooray I fixed it. It can happen, you
-know. What's on my disk is more recent then the latest snapshot.
+know. What's on my disk is more recent than the latest snapshot.
If your program does compile, but generates incorrect output, I need
to know what it says and what you think it should say. From this I can
@@ -82,9 +82,9 @@ clarification.
If the output is strictly correct, but just not good enough for
practical use, I would like to know. These sorts of problems are
-likely to be more subjective then a core dump, but are worthy of
+likely to be more subjective than a core dump, but are worthy of
consideration. However, realize that outright errors will get more
-attention then missed optimizations.
+attention than missed optimizations.
THE MAKING OF A GOOD TEST PROGRAM
2  Module.h
View
@@ -79,7 +79,7 @@ class Module : public PScope, public LineInfo {
enum UCDriveType { UCD_NONE, UCD_PULL0, UCD_PULL1 };
UCDriveType uc_drive;
- /* specparams are simpler then other params, in that they have
+ /* specparams are simpler than other params, in that they have
no type information. They are merely constant
expressions. */
map<perm_string,PExpr*>specparams;
2  PUdp.h
View
@@ -29,7 +29,7 @@ class PExpr;
/*
* This class represents a parsed UDP. This is a much simpler object
- * then a module or macromodule.
+ * than a module or macromodule.
*
* - all ports are scalar,
* - pin 0 (the first port) is always output,
2  README.txt
View
@@ -237,7 +237,7 @@ item. The syntax of the $attribute item is:
$attribute (<identifier>, <key>, <value>);
The $attribute keyword looks like a system task invocation. The
-difference here is that the parameters are more restricted then those
+difference here is that the parameters are more restricted than those
of a system task. The <identifier> must be an identifier. This will be
the item to get an attribute. The <key> and <value> are strings, not
expressions, that give the key and the value of the attribute to be
2  elab_expr.cc
View
@@ -664,7 +664,7 @@ unsigned PEBComp::test_width(Design*des, NetScope*scope, width_mode_t&)
if (type_is_vectorable(r_type) && (l_width > r_width))
r_width_ = l_width;
- // If the expression is unsized and smaller then the integer
+ // If the expression is unsized and smaller than the integer
// minimum, then tweak the size up.
// NOTE: I really would rather try to figure out what it would
// take to get expand the sub-expressions so that they are
2  elab_lval.cc
View
@@ -56,7 +56,7 @@
* l-value.
*
* This last case can turn up in statements like: {a, b[1]} = c;
- * rather then create a NetAssign_ for each item in the concatenation,
+ * rather than create a NetAssign_ for each item in the concatenation,
* elaboration makes a single NetAssign_ and connects it up properly.
*/
4 elab_net.cc
View
@@ -565,10 +565,10 @@ NetNet* PEIdent::elaborate_lnet_common_(Design*des, NetScope*scope,
sig = tmp;
}
- /* If the desired l-value vector is narrower then the
+ /* If the desired l-value vector is narrower than the
signal itself, then use a NetPartSelect node to
arrange for connection to the desired bits. All this
- can be skipped if the desired with matches the
+ can be skipped if the desired width matches the
original vector. */
if (subnet_wid != sig->vector_width()) {
6 elaborate.cc
View
@@ -144,7 +144,7 @@ void PGAssign::elaborate(Design*des, NetScope*scope) const
need_driver_flag = false;
}
- /* If the r-value insists on being smaller then the l-value
+ /* If the r-value insists on being smaller than the l-value
(perhaps it is explicitly sized) the pad it out to be the
right width so that something is connected to all the bits
of the l-value. */
@@ -157,7 +157,7 @@ void PGAssign::elaborate(Design*des, NetScope*scope) const
}
/* If, on the other hand, the r-value insists on being
- LARGER then the l-value, use a part select to chop it down
+ LARGER than the l-value, use a part select to chop it down
down to size. */
if (lval->vector_width() < rval->vector_width()) {
NetPartSelect*tmp = new NetPartSelect(rval, 0,lval->vector_width(),
@@ -3487,7 +3487,7 @@ NetProc* PForever::elaborate(Design*des, NetScope*scope) const
* force <lval> = <rval>
*
* The <lval> can be anything that a normal behavioral assignment can
- * take, plus net signals. This is a little bit more lax then the
+ * take, plus net signals. This is a little bit more lax than the
* other procedural assignments.
*/
NetForce* PForce::elaborate(Design*des, NetScope*scope) const
2  eval_tree.cc
View
@@ -1434,7 +1434,7 @@ NetExpr* NetEUnary::eval_tree()
break;
case '~':
- /* Bitwise not is even simpler then logical
+ /* Bitwise not is even simpler than logical
not. Just invert all the bits of the operand and
make the new value with the same dimensions. */
for (unsigned idx = 0 ; idx < val.len() ; idx += 1)
4 ieee1364-notes.txt
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@@ -285,12 +285,12 @@ One might note that the quote from section 4.1.14 says "Unsized
expressions...", so arguably accepting (15+1) or even (16+0) as an
operand to a concatenation is not a violation of the letter of the
law. However, the very next sentence of the quote expresses the
-intent, and accepting (15+1) as having a more defined size then (16)
+intent, and accepting (15+1) as having a more defined size taen (16)
seems to be a violation of that intent.
Whatever a compiler decides the size is, the user has no way to
predict it, and the compiler should not have the right to treat (15+1)
-any differently then (16). Therefore, Icarus Verilog takes the
+any differently than (16). Therefore, Icarus Verilog takes the
position that such expressions are *unsized* and are not allowed as
operands to concatenations. Icarus Verilog will in general assume that
operations on unsized numbers produce unsized results. There are
4 lexor.lex
View
@@ -979,9 +979,9 @@ verinum* make_undef_highz_dec(const char* ptr)
}
/*
- * Making a decimal number is much easier then the other base numbers
+ * Making a decimal number is much easier than the other base numbers
* because there are no z or x values to worry about. It is much
- * harder then other base numbers because the width needed in bits is
+ * harder than other base numbers because the width needed in bits is
* hard to calculate.
*/
2  macosx.txt
View
@@ -34,7 +34,7 @@ quite similar.
Snapshots of Icarus Verilog source now come with the
lexor_keyword.cc file pre-made, so if you have trouble with gperf,
- then just make sure the distributed lexor_keyword.cc is newer then
+ then just make sure the distributed lexor_keyword.cc is newer than
lexor_keyword.gperf, and use that.
3) If working with a CVS snapshot, you must run autoconf in several
2  net_design.cc
View
@@ -309,7 +309,7 @@ void NetScope::run_defparams_later(Design*des)
(*cur)->evaluate_parameters(des);
// If there are some scopes that still have missing scopes,
- // then sav them back into the defparams_later list for a
+ // then save them back into the defparams_later list for a
// later pass.
defparams_later = defparams_even_later;
if (! defparams_later.empty())
2  netlist.h
View
@@ -1144,7 +1144,7 @@ class NetCLShift : public NetNode {
* This class supports the LPM_COMPARE device.
*
* The width of the device is the width of the inputs. If one of the
- * inputs is narrower then the other, it is up to the generator to
+ * inputs is narrower than the other, it is up to the generator to
* make sure all the data pins are properly driven.
*
* The signed() property is true if the comparison is to be done to
6 parse.y
View
@@ -2267,7 +2267,7 @@ atom2_type
/* An lpvalue is the expression that can go on the left side of a
procedural assignment. This rule handles only procedural
- assignments. It is more limited then the general expr_primary
+ assignments. It is more limited than the general expr_primary
rule to reflect the rules for assignment l-values. */
lpvalue
: hierarchy_identifier
@@ -3937,7 +3937,7 @@ statement
/* assign and deassign statements are procedural code to do
structural assignments, and to turn that structural assignment
- off. This stronger then any other assign, but weaker then the
+ off. This is stronger than any other assign, but weaker than the
force assignments. */
: K_assign lpvalue '=' expression ';'
@@ -3970,7 +3970,7 @@ statement
/* begin-end blocks come in a variety of forms, including named and
anonymous. The named blocks can also carry their own reg
variables, which are placed in the scope created by the block
- name. These are handled by pushing the scope name then matching
+ name. These are handled by pushing the scope name, then matching
the declarations. The scope is popped at the end of the block. */
| K_begin statement_list K_end
2  synth2.cc
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@@ -483,7 +483,7 @@ bool NetBlock::synth_sync(Design*des, NetScope* /*scope*/, NetFF* /*ff*/,
substatement to the output of the block as a
whole. It is occasionally possible to have outputs
beyond the input set, for example when the l-value of
- an assignment is smaller then the r-value. */
+ an assignment is smaller than the r-value. */
for (unsigned idx = 0 ; idx < tmp_out->pin_count() ; idx += 1) {
unsigned ptr = find_nexus_in_set(nex_map,
tmp_map->pin(idx).nexus());
2  sys_funcs.cc
View
@@ -58,7 +58,7 @@ void cleanup_sys_func_table()
const struct sfunc_return_type* lookup_sys_func(const char*name)
{
- /* First, try to find then name in the function stack. */
+ /* First, try to find the name in the function stack. */
struct sfunc_return_type_cell*cur = sfunc_stack;
while (cur) {
if (strcmp(cur->name, name) == 0)
2  t-dll.h
View
@@ -608,7 +608,7 @@ struct ivl_process_s {
/*
* Scopes are kept in a tree. Each scope points to its first child,
* and also to any siblings. Thus a parent can scan all its children
- * by following its child pointer then following sibling pointers from
+ * by following its child pointer, then following sibling pointers from
* there.
*/
struct ivl_scope_s {
2  tgt-fpga/d-virtex.c
View
@@ -206,7 +206,7 @@ static void virtex_or_wide(ivl_net_logic_t net)
/*
* Pick off the cases where there is a Virtex specific implementation
- * that is better then the generic Xilinx implementation. Route the
+ * that is better than the generic Xilinx implementation. Route the
* remaining to the base xilinx_logic implementation.
*/
void virtex_logic(ivl_net_logic_t net)
2  tgt-vhdl/stmt.cc
View
@@ -939,7 +939,7 @@ static int draw_wait(vhdl_procedural *_proc, stmt_container *container,
else {
// Build a test expression to represent the edge event
// If this process contains no `wait' statements and this
- // is the top-level container then we
+ // is the top-level container, then we
// wrap it in an `if' statement with this test and add the
// edge triggered signals to the sensitivity, otherwise
// build a `wait until' statement at the top of the process
2  tgt-vlog95/misc.c
View
@@ -96,7 +96,7 @@ static unsigned check_scaled_expr(ivl_expr_t expr, uint64_t scale,
scale_val = get_uint64_from_number(ivl_expr_oper2(expr), &rtype);
if (rtype > 0) {
fprintf(stderr, "%s:%u: vlog95 error: %s expression/value "
- "scale coefficient was greater then 64 bits "
+ "scale coefficient was greater than 64 bits "
"(%d).\n", ivl_expr_file(expr),
ivl_expr_lineno(expr), msg, rtype);
vlog_errors += 1;
4 tgt-vlog95/scope.c
View
@@ -240,7 +240,7 @@ void emit_net_def(ivl_scope_t scope, ivl_signal_t sig)
static char *get_mangled_name(ivl_scope_t scope, unsigned root)
{
char *name;
- /* If the module has parameters and it's not a root module than it
+ /* If the module has parameters and it's not a root module then it
* may not be unique so we create a mangled name version instead. */
if (ivl_scope_params(scope) && ! root) {
unsigned idx;
@@ -464,7 +464,7 @@ int emit_scope(ivl_scope_t scope, ivl_scope_t parent)
/* This is an instantiation. */
if (parent) {
assert(indent != 0);
- /* If the module has parameters than it may not be unique
+ /* If the module has parameters then it may not be unique
* so we create a mangled name version instead. */
fprintf(vlog_out, "\n%*c%s %s(", indent, ' ', name,
ivl_scope_basename(scope));
2  tgt-vvp/draw_vpi.c
View
@@ -80,7 +80,7 @@ static int get_vpi_taskfunc_signal_arg(struct args_info *result,
switch (ivl_expr_type(expr)) {
case IVL_EX_SIGNAL:
- /* If the signal node is narrower then the signal itself,
+ /* If the signal node is narrower than the signal itself,
then this is a part select so I'm going to need to
evaluate the expression.
10 tgt-vvp/eval_expr.c
View
@@ -1984,7 +1984,7 @@ static struct vector_info draw_pad_expr(ivl_expr_t expr, unsigned wid)
return res;
}
- /* So now we know that the subexpression is smaller then the
+ /* So now we know that the subexpression is smaller than the
desired result (the usual case) so we build the
result. Evaluate the subexpression into the target buffer,
then pad it as appropriate. */
@@ -2441,7 +2441,7 @@ static void draw_select_signal_dest(ivl_expr_t expr,
/* Special case: If the operand is a signal (not an array) and
the part select is coming from the LSB, and the part select
- is no larger then the signal itself, then we can load the
+ is no larger than the signal itself, then we can load the
value in place, directly. */
if ((ivl_signal_dimensions(sig) == 0)
&& (ivl_expr_width(sube) >= dest.wid)
@@ -2597,7 +2597,7 @@ static struct vector_info draw_select_unsized_literal(ivl_expr_t expr,
subv = res;
}
- /* If the subv result is narrower then the select width, then
+ /* If the subv result is narrower than the select width, then
copy it into a wider vector. */
if (subv.wid < wid && ivl_expr_signed(sube)) {
res.base = allocate_vector(wid);
@@ -3008,7 +3008,7 @@ static struct vector_info draw_unary_expr(ivl_expr_t expr, unsigned wid)
break;
}
- /* If the result needs to be bigger then the calculated
+ /* If the result needs to be bigger than the calculated
value, then write it into a padded vector. */
if (res.wid < wid) {
struct vector_info tmp;
@@ -3071,7 +3071,7 @@ static struct vector_info draw_unary_expr(ivl_expr_t expr, unsigned wid)
fprintf(vvp_out, " %%inv %u, 1;\n", res.base);
}
- /* If the result needs to be bigger then the calculated
+ /* If the result needs to be bigger than the calculated
value, then write it into a passed vector. */
if (res.wid < wid) {
struct vector_info tmp;
2  vhdlpp/lexor.lex
View
@@ -178,7 +178,7 @@ based_integer [0-9a-fA-F](_?[0-9a-fA-F])*
"<<" { return DLT; }
">>" { return DGT; }
/*
- Here comes a list of symbols that are more then strange,
+ Here comes a list of symbols that are more than strange,
at least for the time being.
"??" { return K_CC; }
4 vvp/README.txt
View
@@ -874,7 +874,7 @@ of four possible values (0, 1, x and z) so two bits are needed to
represent them. So the input of the functor is 8 bits, and the output
2 bits. A complete lookup table for generating the 2-bit output from
an 8-bit input is 512 bits. That can be packed into 64 bytes. This is
-small enough that the table should take less space then the code to
+small enough that the table should take less space than the code to
implement the logic.
To implement the truth table, we need to assign 2-bit encodings for
@@ -1034,7 +1034,7 @@ becomes:
Notice the first parameter of the .functor is the type. The type
includes a truth table that describes the output with a given
-input. If the gate is wider then four inputs, then cascade
+input. If the gate is wider than four inputs, then cascade
functors. For example:
and gate (out, i1, i2, i3, i4, i5, i6, i7, i8);
2  vvp/compile.h
View
@@ -457,7 +457,7 @@ extern void compile_var_real(char*label, char*name,
int msb, int lsb);
/*
- * The compile_net functio is called to create a .net vector with a
+ * The compile_net function is called to create a .net vector with a
* given name.
*
* The vpi_type_code argument of compile_net() is one of the vpi
2  vvp/event.h
View
@@ -350,7 +350,7 @@ class vvp_fun_event_or_aa : public vvp_fun_event_or, public automatic_hooks_s {
};
/*
- * A named event is simpler then a vvp_fun_edge in that it triggers on
+ * A named event is simpler than a vvp_fun_edge in that it triggers on
* any input at all to port-0. The idea here is that behavioral code
* can use a %set/v instruction to trigger the event.
*/
2  vvp/vpi_priv.cc
View
@@ -928,7 +928,7 @@ void vpip_put_value_event::run_run()
case vpiStringVal:
free(value.value.str);
break;
- /* If these are every copied then free them too. */
+ /* If these are ever copied then free them too. */
case vpiTimeVal:
case vpiVectorVal:
case vpiStrengthVal:
6 vvp/vthread.cc
View
@@ -2945,7 +2945,7 @@ bool of_LOAD_AV(vthread_t thr, vvp_code_t cp)
directly to skip the excess calls to thr_check_addr. */
thr->bits4.set_vec(bit, word);
- /* If the source is shorter then the desired width, then pad
+ /* If the source is shorter than the desired width, then pad
with BIT4_X values. */
for (unsigned idx = word.size() ; idx < wid ; idx += 1)
thr->bits4.set_bit(bit+idx, BIT4_X);
@@ -3135,7 +3135,7 @@ bool of_LOAD_VEC(vthread_t thr, vvp_code_t cp)
directly to skip the excess calls to thr_check_addr. */
thr->bits4.set_vec(bit, sig_value);
- /* If the source is shorter then the desired width, then pad
+ /* If the source is shorter than the desired width, then pad
with BIT4_X values. */
for (unsigned idx = sig_value.size() ; idx < wid ; idx += 1)
thr->bits4.set_bit(bit+idx, BIT4_X);
@@ -4236,7 +4236,7 @@ bool of_SET_X0(vthread_t thr, vvp_code_t cp)
if (index < 0 && (wid <= (unsigned)-index))
return true;
- // If the entire part is above then end of the vector, then we
+ // If the entire part is above the end of the vector, then we
// are done.
if (index >= (long)sig->value_size())
return true;
2  vvp/vvp.man.in
View
@@ -101,7 +101,7 @@ the expense of some file size.
.ns
.TP
.B -lx2\fR|\fP-lx2-speed\fR|\fP-lx2-space
-The LXT2 format is slower then LXT but usually takes less space, and
+The LXT2 format is slower than LXT but usually takes less space, and
is written out incrementally. Thus, you can view lxt2 files while a
simulation is still running (or paused) or if your simulation crashes
or is killed, you still have a useful dump. The \fB\-lxt2\-speed\fP
6 vvp/vvp_net.h
View
@@ -723,7 +723,7 @@ inline vvp_vector2_t vvp_vector2_t::subvalue(unsigned base, unsigned wid) const
/*
* This class represents a scalar value with strength. These are
- * heavier then the simple vvp_bit4_t, but more information is
+ * heavier than the simple vvp_bit4_t, but more information is
* carried by that weight.
*
* The strength values are as defined here:
@@ -882,7 +882,7 @@ class vvp_vector8_t {
private:
// This is the number of vvp_scalar_t objects we can keep in
- // the val_ buffer. If the vector8 is bigger then this, then
+ // the val_ buffer. If the vector8 is bigger than this, then
// resort to allocations to get a larger buffer.
unsigned size_;
union {
@@ -1396,7 +1396,7 @@ class vvp_fun_drive : public vvp_net_fun_t {
/*
* EXTEND functors expand an input vector to the desired output
* width. The extend_signed functor sign extends the input. If the
- * input is already wider then the desired output, then it is passed
+ * input is already wider than the desired output, then it is passed
* unmodified.
*/
class vvp_fun_extend_signed : public vvp_net_fun_t {
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