Permalink
Browse files

New things are supported.

  • Loading branch information...
1 parent 66ac537 commit f039b472d4bb2ee7d68d00bc6a4b3b5381745f3e steve committed Jun 7, 1999
Showing with 5 additions and 7 deletions.
  1. +5 −7 README.txt
View
@@ -219,16 +219,14 @@ To run the program
5.0 Unsupported Constructs
-IVL is in development - as such it still only supports a subset
+IVL is in development - as such it still only supports a (growing) subset
of verilog. Below is a description of some of the currently unsupported
verilog features.
-Event Control - ??
+ - Lvalue bit ranges - Example: regvalue [7:3] = 5'b0;
-Lvalue bit ranges - Example: regvalue [7:3] = 5'b0;
+ - Complex delay expressions, specifically min,typ,max expressions.
-Non-blocking Assignment - Example: regvalue <= 5'b0;
+ - Tasks/functions
-Complex delay expressions - ??
-
-Tasks/functions
+ - Other things I forgot to mention.

0 comments on commit f039b47

Please sign in to comment.