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parse more verilog.

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1 parent 63627de commit 29da349106636e52a7d6cf20c27b9c114577d425 steve committed Jun 12, 1999
Showing with 81 additions and 47 deletions.
  1. +10 −1 lexor.lex
  2. +32 −14 parse.y
  3. +32 −28 pform.cc
  4. +7 −4 pform.h
View
11 lexor.lex
@@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#if !defined(WINNT)
-#ident "$Id: lexor.lex,v 1.18 1999/06/12 03:41:30 steve Exp $"
+#ident "$Id: lexor.lex,v 1.19 1999/06/12 20:35:27 steve Exp $"
#endif
//# define YYSTYPE lexval
@@ -57,6 +57,7 @@ static verinum*make_unsized_hex(const char*txt);
%x CSTRING
%s UDPTABLE
%x PPINCLUDE
+%x PPTIMESCALE
%%
@@ -168,6 +169,14 @@ static verinum*make_unsized_hex(const char*txt);
delete[]bits;
return NUMBER; }
+`timescale { BEGIN(PPTIMESCALE); }
+<PPTIMESCALE>. { ; }
+<PPTIMESCALE>\n {
+ cerr << yylloc.text << ":" << yylloc.first_line
+ << ": Sorry, `timescale not supported." << endl;
+ yylloc.first_line += 1;
+ BEGIN(0); }
+
`include {
BEGIN(PPINCLUDE); }
View
46 parse.y
@@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#if !defined(WINNT)
-#ident "$Id: parse.y,v 1.37 1999/06/12 03:42:57 steve Exp $"
+#ident "$Id: parse.y,v 1.38 1999/06/12 20:35:27 steve Exp $"
#endif
# include "parse_misc.h"
@@ -53,7 +53,7 @@ extern void lex_end_table();
NetNet::PortType porttype;
PWire*wire;
- list<PWire*>*wires;
+ svector<PWire*>*wires;
PEventStatement*event_statement;
Statement*statement;
@@ -222,9 +222,9 @@ delay_value
;
delay_value_list
- : delay_value
+ : expression
{ $$ = $1; }
- | delay_value_list ',' delay_value
+ | delay_value_list ',' expression
{ yyerror(@1, "Sorry, delay value lists not supported.");
$$ = $1;
delete $3;
@@ -698,13 +698,13 @@ identifier
list_of_ports
: port
- { list<PWire*>*tmp = new list<PWire*>;
- tmp->push_back($1);
+ { svector<PWire*>*tmp = new svector<PWire*>(1);
+ (*tmp)[0] = $1;
$$ = tmp;
}
| list_of_ports ',' port
- { list<PWire*>*tmp = $1;
- tmp->push_back($3);
+ { svector<PWire*>*tmp = new svector<PWire*>(*$1, $3);
+ delete $1;
$$ = tmp;
}
;
@@ -1111,6 +1111,12 @@ register_variable
{ pform_makewire(@1, *$1, NetNet::REG);
$$ = $1;
}
+ | IDENTIFIER '=' expression
+ { pform_makewire(@1, *$1, NetNet::REG);
+ yyerror(@2, "net declaration assignment to reg/integer not allowed.");
+ delete $3;
+ $$ = $1;
+ }
| IDENTIFIER '[' expression ':' expression ']'
{ pform_makewire(@1, *$1, NetNet::REG);
if (! pform_expression_is_constant($3))
@@ -1175,9 +1181,21 @@ statement
| K_disable IDENTIFIER ';'
{ yyerror(@1, "Sorry, disable statements not supported.");
delete $2;
+ $$ = 0;
+ }
+ | K_forever statement
+ { yyerror(@1, "Sorry, forever statements not supported.");
+ delete $2;
+ $$ = 0;
}
| K_fork statement_list K_join
{ $$ = pform_make_block(PBlock::BL_PAR, $2); }
+ | K_repeat '(' expression ')' statement
+ { yyerror(@1, "Sorry, repeat statements not supported.");
+ delete $3;
+ delete $5;
+ $$ = 0;
+ }
| K_begin K_end
{ $$ = pform_make_block(PBlock::BL_SEQ, 0); }
| K_begin ':' IDENTIFIER K_end
@@ -1479,16 +1497,16 @@ udp_port_decl
| K_output IDENTIFIER ';'
{ PWire*pp = new PWire(*$2);
pp->port_type = NetNet::POUTPUT;
- list<PWire*>*tmp = new list<PWire*>;
- tmp->push_back(pp);
+ svector<PWire*>*tmp = new svector<PWire*>(1);
+ (*tmp)[0] = pp;
delete $2;
$$ = tmp;
}
| K_reg IDENTIFIER ';'
{ PWire*pp = new PWire(*$2, NetNet::REG);
pp->port_type = NetNet::PIMPLICIT;
- list<PWire*>*tmp = new list<PWire*>;
- tmp->push_back(pp);
+ svector<PWire*>*tmp = new svector<PWire*>(1);
+ (*tmp)[0] = pp;
delete $2;
$$ = tmp;
}
@@ -1498,8 +1516,8 @@ udp_port_decls
: udp_port_decl
{ $$ = $1; }
| udp_port_decls udp_port_decl
- { list<PWire*>*tmp = $1;
- tmp->merge(*$2);
+ { svector<PWire*>*tmp = new svector<PWire*>(*$1, *$2);
+ delete $1;
delete $2;
$$ = tmp;
}
View
60 pform.cc
@@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#if !defined(WINNT)
-#ident "$Id: pform.cc,v 1.24 1999/06/12 03:42:17 steve Exp $"
+#ident "$Id: pform.cc,v 1.25 1999/06/12 20:35:27 steve Exp $"
#endif
# include "compiler.h"
@@ -57,20 +57,16 @@ static unsigned long evaluate_delay(PExpr*delay)
return pp->value().as_ulong();
}
-void pform_startmodule(const string&name, list<PWire*>*ports)
+void pform_startmodule(const string&name, svector<PWire*>*ports)
{
assert( cur_module == 0 );
- cur_module = new Module(name, ports? ports->size() : 0);
+ cur_module = new Module(name, ports? ports->count() : 0);
if (ports) {
- unsigned idx = 0;
- for (list<PWire*>::iterator cur = ports->begin()
- ; cur != ports->end()
- ; cur ++ ) {
- cur_module->add_wire(*cur);
- cur_module->ports[idx++] = *cur;
+ for (unsigned idx = 0 ; idx < ports->count() ; idx += 1) {
+ cur_module->add_wire((*ports)[idx]);
+ cur_module->ports[idx] = (*ports)[idx];
}
-
delete ports;
}
}
@@ -89,7 +85,7 @@ bool pform_expression_is_constant(const PExpr*ex)
}
void pform_make_udp(string*name, list<string>*parms,
- list<PWire*>*decl, list<string>*table,
+ svector<PWire*>*decl, list<string>*table,
Statement*init_expr)
{
assert(parms->size() > 0);
@@ -98,28 +94,26 @@ void pform_make_udp(string*name, list<string>*parms,
off with the parameters in the list. I will rebuild a list
of parameters for the PUdp object. */
map<string,PWire*> defs;
- for (list<PWire*>::iterator cur = decl->begin()
- ; cur != decl->end()
- ; cur ++ )
+ for (unsigned idx = 0 ; idx < decl->count() ; idx += 1)
- if (defs[(*cur)->name] == 0) {
- defs[(*cur)->name] = *cur;
+ if (defs[(*decl)[idx]->name] == 0) {
+ defs[(*decl)[idx]->name] = (*decl)[idx];
- } else switch ((*cur)->port_type) {
+ } else switch ((*decl)[idx]->port_type) {
case NetNet::PIMPLICIT:
case NetNet::POUTPUT:
- assert(defs[(*cur)->name]->port_type != NetNet::PINPUT);
+ assert(defs[(*decl)[idx]->name]->port_type != NetNet::PINPUT);
// OK, merge the output definitions.
- defs[(*cur)->name]->port_type = NetNet::POUTPUT;
- if ((*cur)->type == NetNet::REG)
- defs[(*cur)->name]->type = NetNet::REG;
+ defs[(*decl)[idx]->name]->port_type = NetNet::POUTPUT;
+ if ((*decl)[idx]->type == NetNet::REG)
+ defs[(*decl)[idx]->name]->type = NetNet::REG;
break;
case NetNet::PINPUT:
// Allow duplicate input declarations.
- assert(defs[(*cur)->name]->port_type == NetNet::PINPUT);
- delete *cur;
+ assert(defs[(*decl)[idx]->name]->port_type == NetNet::PINPUT);
+ delete (*decl)[idx];
break;
default:
@@ -453,8 +447,14 @@ static void pform_set_net_range(const string&name, const svector<PExpr*>*range)
cur->msb = (*range)[0];
cur->lsb = (*range)[1];
} else {
- assert(cur->msb);
- assert(cur->lsb);
+ if (cur->msb == 0) {
+ VLerror(yylloc, "missing msb of range.");
+ return;
+ }
+ if (cur->lsb == 0) {
+ VLerror(yylloc, "missing lsb of range.");
+ return;
+ }
PExpr*msb = (*range)[0];
PExpr*lsb = (*range)[1];
assert(msb);
@@ -519,16 +519,17 @@ void pform_set_reg_integer(list<string>*names)
}
}
-list<PWire*>* pform_make_udp_input_ports(list<string>*names)
+svector<PWire*>* pform_make_udp_input_ports(list<string>*names)
{
- list<PWire*>*out = new list<PWire*>;
+ svector<PWire*>*out = new svector<PWire*>(names->size());
+ unsigned idx = 0;
for (list<string>::const_iterator cur = names->begin()
; cur != names->end()
; cur ++ ) {
PWire*pp = new PWire(*cur);
pp->port_type = NetNet::PINPUT;
- out->push_back(pp);
+ (*out)[idx] = pp;
}
delete names;
@@ -589,6 +590,9 @@ int pform_parse(const char*path, map<string,Module*>&modules,
/*
* $Log: pform.cc,v $
+ * Revision 1.25 1999/06/12 20:35:27 steve
+ * parse more verilog.
+ *
* Revision 1.24 1999/06/12 03:42:17 steve
* Assert state of bit range expressions.
*
View
11 pform.h
@@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#if !defined(WINNT)
-#ident "$Id: pform.h,v 1.18 1999/06/06 20:45:39 steve Exp $"
+#ident "$Id: pform.h,v 1.19 1999/06/12 20:35:27 steve Exp $"
#endif
# include "netlist.h"
@@ -95,11 +95,11 @@ struct lgate {
* are to apply to the scope of that module. The endmodule causes the
* pform to close up and finish the named module.
*/
-extern void pform_startmodule(const string&, list<PWire*>*ports);
+extern void pform_startmodule(const string&, svector<PWire*>*ports);
extern void pform_endmodule(const string&);
extern void pform_make_udp(string*name, list<string>*parms,
- list<PWire*>*decl, list<string>*table,
+ svector<PWire*>*decl, list<string>*table,
Statement*init);
/*
@@ -123,7 +123,7 @@ extern PProcess* pform_make_behavior(PProcess::Type, Statement*);
extern Statement* pform_make_block(PBlock::BL_TYPE, list<Statement*>*);
extern Statement* pform_make_calltask(string*t, svector<PExpr*>* =0);
-extern list<PWire*>* pform_make_udp_input_ports(list<string>*);
+extern svector<PWire*>* pform_make_udp_input_ports(list<string>*);
extern bool pform_expression_is_constant(const PExpr*);
@@ -152,6 +152,9 @@ extern void pform_dump(ostream&out, Module*mod);
/*
* $Log: pform.h,v $
+ * Revision 1.19 1999/06/12 20:35:27 steve
+ * parse more verilog.
+ *
* Revision 1.18 1999/06/06 20:45:39 steve
* Add parse and elaboration of non-blocking assignments,
* Replace list<PCase::Item*> with an svector version,

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