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Parse and elaborate rise/fall/decay times

 for gates, and handle the rules for partial
 lists of times.
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1 parent dae5916 commit 71d35f32b2190936c3d964eadcda51cf5fc33f02 steve committed
Showing with 327 additions and 197 deletions.
  1. +88 −1 PGate.cc
  2. +28 −13 PGate.h
  3. +15 −10 design_dump.cc
  4. +70 −113 elaborate.cc
  5. +19 −7 netlist.h
  6. +24 −17 parse.y
  7. +20 −10 pform.cc
  8. +9 −3 pform.h
  9. +30 −9 pform_dump.cc
  10. +9 −4 t-verilog.cc
  11. +15 −10 t-vvm.cc
View
89 PGate.cc
@@ -17,10 +17,92 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#if !defined(WINNT)
-#ident "$Id: PGate.cc,v 1.1 1999/02/15 02:06:15 steve Exp $"
+#ident "$Id: PGate.cc,v 1.2 1999/08/01 16:34:50 steve Exp $"
#endif
# include "PGate.h"
+# include "PExpr.h"
+# include <assert.h>
+
+PGate::PGate(const string&name,
+ svector<PExpr*>*pins,
+ const svector<PExpr*>*del)
+: name_(name), pins_(pins)
+{
+ for (unsigned idx = 0 ; idx < 3 ; idx += 1)
+ delay_[idx] = 0;
+
+ if (del) {
+ assert(del->count() <= 3);
+ for (unsigned idx = 0 ; idx < del->count() ; idx += 1)
+ delay_[idx] = (*del)[idx];
+ }
+}
+
+PGate::PGate(const string&name,
+ svector<PExpr*>*pins,
+ PExpr*del)
+: name_(name), pins_(pins)
+{
+ delay_[0] = del;
+ delay_[1] = 0;
+ delay_[2] = 0;
+}
+
+PGate::PGate(const string&name, svector<PExpr*>*pins)
+: name_(name), pins_(pins)
+{
+ delay_[0] = 0;
+ delay_[1] = 0;
+ delay_[2] = 0;
+}
+
+PGate::~PGate()
+{
+ for (unsigned idx = 0 ; idx < 3 ; idx += 1)
+ delete delay_[idx];
+}
+
+const PExpr* PGate::get_delay(unsigned idx) const
+{
+ assert(idx < 3);
+ return delay_[idx];
+}
+
+PGAssign::PGAssign(svector<PExpr*>*pins)
+: PGate("", pins)
+{
+ assert(pins->count() == 2);
+}
+
+PGAssign::PGAssign(svector<PExpr*>*pins, svector<PExpr*>*dels)
+: PGate("", pins, dels)
+{
+ assert(pins->count() == 2);
+}
+
+PGAssign::~PGAssign()
+{
+}
+
+PGBuiltin::PGBuiltin(Type t, const string&name,
+ svector<PExpr*>*pins,
+ svector<PExpr*>*del)
+: PGate(name, pins, del), type_(t), msb_(0), lsb_(0)
+{
+}
+
+PGBuiltin::PGBuiltin(Type t, const string&name,
+ svector<PExpr*>*pins,
+ PExpr*del)
+: PGate(name, pins, del), type_(t), msb_(0), lsb_(0)
+{
+}
+
+
+PGBuiltin::~PGBuiltin()
+{
+}
void PGBuiltin::set_range(PExpr*msb, PExpr*lsb)
{
@@ -33,6 +115,11 @@ void PGBuiltin::set_range(PExpr*msb, PExpr*lsb)
/*
* $Log: PGate.cc,v $
+ * Revision 1.2 1999/08/01 16:34:50 steve
+ * Parse and elaborate rise/fall/decay times
+ * for gates, and handle the rules for partial
+ * lists of times.
+ *
* Revision 1.1 1999/02/15 02:06:15 steve
* Elaborate gate ranges.
*
View
41 PGate.h
@@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#if !defined(WINNT)
-#ident "$Id: PGate.h,v 1.6 1999/05/29 02:36:17 steve Exp $"
+#ident "$Id: PGate.h,v 1.7 1999/08/01 16:34:50 steve Exp $"
#endif
# include "svector.h"
@@ -41,14 +41,19 @@ class Module;
class PGate : public LineInfo {
public:
- explicit PGate(const string&name, svector<PExpr*>*pins, long del)
- : name_(name), delay_(del), pins_(pins) { }
+ explicit PGate(const string&name, svector<PExpr*>*pins,
+ const svector<PExpr*>*del);
- virtual ~PGate() { }
+ explicit PGate(const string&name, svector<PExpr*>*pins,
+ PExpr*del);
+
+ explicit PGate(const string&name, svector<PExpr*>*pins);
+
+ virtual ~PGate();
const string& get_name() const { return name_; }
- long get_delay() const { return delay_; }
+ const PExpr* get_delay(unsigned idx) const;
unsigned pin_count() const { return pins_? pins_->count() : 0; }
const PExpr*pin(unsigned idx) const { return (*pins_)[idx]; }
@@ -60,10 +65,11 @@ class PGate : public LineInfo {
const svector<PExpr*>* get_pins() const { return pins_; }
void dump_pins(ostream&out) const;
+ void dump_delays(ostream&out) const;
private:
const string name_;
- const unsigned long delay_;
+ PExpr* delay_[3];
svector<PExpr*>*pins_;
private: // not implemented
@@ -78,8 +84,9 @@ class PGate : public LineInfo {
class PGAssign : public PGate {
public:
- explicit PGAssign(svector<PExpr*>*pins)
- : PGate("", pins, 0) { assert(pins->count() == 2); }
+ explicit PGAssign(svector<PExpr*>*pins);
+ explicit PGAssign(svector<PExpr*>*pins, svector<PExpr*>*dels);
+ ~PGAssign();
void dump(ostream&out) const;
virtual void elaborate(Design*des, const string&path) const;
@@ -108,9 +115,12 @@ class PGBuiltin : public PGate {
public:
explicit PGBuiltin(Type t, const string&name,
- svector<PExpr*>*pins, long del = 0)
- : PGate(name, pins, del), type_(t), msb_(0), lsb_(0)
- { }
+ svector<PExpr*>*pins,
+ svector<PExpr*>*del);
+ explicit PGBuiltin(Type t, const string&name,
+ svector<PExpr*>*pins,
+ PExpr*del);
+ ~PGBuiltin();
Type type() const { return type_; }
void set_range(PExpr*msb, PExpr*lsb);
@@ -138,7 +148,7 @@ class PGModule : public PGate {
// builds everything all at once.
explicit PGModule(const string&type, const string&name,
svector<PExpr*>*pins)
- : PGate(name, pins, 0), type_(type), pins_(0), npins_(0) { }
+ : PGate(name, pins), type_(type), pins_(0), npins_(0) { }
// If the binding of ports is by name, this constructor takes
// the bindings and stores them for later elaboration.
@@ -148,7 +158,7 @@ class PGModule : public PGate {
};
explicit PGModule(const string&type, const string&name,
bind_t*pins, unsigned npins)
- : PGate(name, 0, 0), type_(type), pins_(pins), npins_(npins) { }
+ : PGate(name, 0), type_(type), pins_(pins), npins_(npins) { }
virtual void dump(ostream&out) const;
@@ -165,6 +175,11 @@ class PGModule : public PGate {
/*
* $Log: PGate.h,v $
+ * Revision 1.7 1999/08/01 16:34:50 steve
+ * Parse and elaborate rise/fall/decay times
+ * for gates, and handle the rules for partial
+ * lists of times.
+ *
* Revision 1.6 1999/05/29 02:36:17 steve
* module parameter bind by name.
*
View
25 design_dump.cc
@@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#if !defined(WINNT)
-#ident "$Id: design_dump.cc,v 1.33 1999/07/24 02:11:20 steve Exp $"
+#ident "$Id: design_dump.cc,v 1.34 1999/08/01 16:34:50 steve Exp $"
#endif
/*
@@ -49,8 +49,8 @@ void NetNet::dump_net(ostream&o, unsigned ind) const
pin_count() << "]";
if (local_flag_)
o << " (local)";
- o << " #(" << delay1() << "," << delay2() << "," << delay3() <<
- ") init=";
+ o << " #(" << rise_time() << "," << fall_time() << "," <<
+ decay_time() << ") init=";
for (unsigned idx = pin_count() ; idx > 0 ; idx -= 1)
o << ivalue_[idx-1];
o << endl;
@@ -70,8 +70,8 @@ void NetMemory::dump(ostream&o, unsigned ind) const
void NetNode::dump_node(ostream&o, unsigned ind) const
{
o << setw(ind) << "" << "node: ";
- o << typeid(*this).name() << " #(" << delay1()
- << "," << delay2() << "," << delay3() << ") " << name()
+ o << typeid(*this).name() << " #(" << rise_time()
+ << "," << fall_time() << "," << decay_time() << ") " << name()
<< endl;
dump_node_pins(o, ind+4);
@@ -185,8 +185,8 @@ void NetLogic::dump_node(ostream&o, unsigned ind) const
o << "xor";
break;
}
- o << " #(" << delay1()
- << "," << delay2() << "," << delay3() << ") " << name()
+ o << " #(" << rise_time()
+ << "," << fall_time() << "," << decay_time() << ") " << name()
<< endl;
dump_node_pins(o, ind+4);
@@ -227,8 +227,8 @@ void NetUDP::dump_sequ_(ostream&o, unsigned ind) const
for (unsigned idx = 0 ; idx < ind ; idx += 1)
tmp += " ";
- o << tmp << "Sequential UDP" << " #(" << delay1() <<
- "," << delay2() << "," << delay3() << ") " << name() <<
+ o << tmp << "Sequential UDP" << " #(" << rise_time() <<
+ "," << fall_time() << "," << decay_time() << ") " << name() <<
endl;
for (FSM_::const_iterator ent = fsm_.begin()
@@ -270,7 +270,7 @@ void NetUDP::dump_sequ_(ostream&o, unsigned ind) const
void NetUDP::dump_comb_(ostream&o, unsigned ind) const
{
o << setw(ind) << "" << "Combinational UDP: ";
- o << " #(" << delay1() << "," << delay2() << "," << delay3() <<
+ o << " #(" << rise_time() << "," << fall_time() << "," << decay_time() <<
") " << name() << endl;
dump_node_pins(o, ind+4);
@@ -690,6 +690,11 @@ void Design::dump(ostream&o) const
/*
* $Log: design_dump.cc,v $
+ * Revision 1.34 1999/08/01 16:34:50 steve
+ * Parse and elaborate rise/fall/decay times
+ * for gates, and handle the rules for partial
+ * lists of times.
+ *
* Revision 1.33 1999/07/24 02:11:20 steve
* Elaborate task input ports.
*
View
183 elaborate.cc
@@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#if !defined(WINNT)
-#ident "$Id: elaborate.cc,v 1.62 1999/07/31 03:16:54 steve Exp $"
+#ident "$Id: elaborate.cc,v 1.63 1999/08/01 16:34:50 steve Exp $"
#endif
/*
@@ -232,6 +232,12 @@ void PGAssign::elaborate(Design*des, const string&path) const
}
do_assign(des, path, lval, rval);
+
+ if (get_delay(0)) {
+ cerr << get_line() << ": Sorry, elaboration does not support"
+ " delayed continuous assignments." << endl;
+ des->errors += 1;
+ }
}
/*
@@ -281,6 +287,59 @@ void PGBuiltin::elaborate(Design*des, const string&path) const
NetLogic**cur = new NetLogic*[count];
assert(cur);
+ /* Calculate the gate delays from the delay expressions
+ given in the source. For logic gates, the decay time
+ is meaningless because it can never go to high
+ impedence. However, the bufif devices can generate
+ 'bz output, so we will pretend that anything can.
+
+ If only one delay value expression is given (i.e. #5
+ nand(foo,...)) then rise, fall and decay times are
+ all the same value. If two values are given, rise and
+ fall times are use, and the decay time is the minimum
+ of the rise and fall times. Finally, if all three
+ values are given, they are taken as specified. */
+
+ verinum*dv;
+ unsigned long rise_time, fall_time, decay_time;
+
+ if (get_delay(0)) {
+ dv = get_delay(0)->eval_const(des, path);
+ assert(dv);
+ rise_time = dv->as_ulong();
+ delete dv;
+
+ if (get_delay(1)) {
+ dv = get_delay(1)->eval_const(des, path);
+ assert(dv);
+ fall_time = dv->as_ulong();
+ delete dv;
+
+ if (get_delay(2)) {
+ dv = get_delay(2)->eval_const(des, path);
+ assert(dv);
+ decay_time = dv->as_ulong();
+ delete dv;
+ } else {
+ if (rise_time < fall_time)
+ decay_time = rise_time;
+ else
+ decay_time = fall_time;
+ }
+ } else {
+ assert(get_delay(2) == 0);
+ fall_time = rise_time;
+ decay_time = rise_time;
+ }
+ } else {
+ rise_time = 0;
+ fall_time = 0;
+ decay_time = 0;
+ }
+
+ /* Now make as many gates as the bit count dictates. Give each
+ a unique name, and set the delay times. */
+
for (unsigned idx = 0 ; idx < count ; idx += 1) {
strstream tmp;
unsigned index;
@@ -325,9 +384,11 @@ void PGBuiltin::elaborate(Design*des, const string&path) const
break;
}
- cur[idx]->delay1(get_delay());
- cur[idx]->delay2(get_delay());
- cur[idx]->delay3(get_delay());
+
+ cur[idx]->rise_time(rise_time);
+ cur[idx]->fall_time(fall_time);
+ cur[idx]->decay_time(decay_time);
+
des->add_node(cur[idx]);
}
@@ -1991,6 +2052,11 @@ Design* elaborate(const map<string,Module*>&modules,
/*
* $Log: elaborate.cc,v $
+ * Revision 1.63 1999/08/01 16:34:50 steve
+ * Parse and elaborate rise/fall/decay times
+ * for gates, and handle the rules for partial
+ * lists of times.
+ *
* Revision 1.62 1999/07/31 03:16:54 steve
* move binary operators to derived classes.
*
@@ -2140,114 +2206,5 @@ Design* elaborate(const map<string,Module*>&modules,
*
* Revision 1.22 1999/05/01 02:57:53 steve
* Handle much more complex event expressions.
- *
- * Revision 1.21 1999/04/29 02:16:26 steve
- * Parse OR of event expressions.
- *
- * Revision 1.20 1999/04/25 00:44:10 steve
- * Core handles subsignal expressions.
- *
- * Revision 1.19 1999/04/19 01:59:36 steve
- * Add memories to the parse and elaboration phases.
- *
- * Revision 1.18 1999/03/15 02:43:32 steve
- * Support more operators, especially logical.
- *
- * Revision 1.17 1999/03/01 03:27:53 steve
- * Prevent the duplicate allocation of ESignal objects.
- *
- * Revision 1.16 1999/02/21 17:01:57 steve
- * Add support for module parameters.
- *
- * Revision 1.15 1999/02/15 02:06:15 steve
- * Elaborate gate ranges.
- *
- * Revision 1.14 1999/02/08 02:49:56 steve
- * Turn the NetESignal into a NetNode so
- * that it can connect to the netlist.
- * Implement the case statement.
- * Convince t-vvm to output code for
- * the case statement.
- *
- * Revision 1.13 1999/02/03 04:20:11 steve
- * Parse and elaborate the Verilog CASE statement.
- *
- * Revision 1.12 1999/02/01 00:26:49 steve
- * Carry some line info to the netlist,
- * Dump line numbers for processes.
- * Elaborate prints errors about port vector
- * width mismatch
- * Emit better handles null statements.
- *
- * Revision 1.11 1999/01/25 05:45:56 steve
- * Add the LineInfo class to carry the source file
- * location of things. PGate, Statement and PProcess.
- *
- * elaborate handles module parameter mismatches,
- * missing or incorrect lvalues for procedural
- * assignment, and errors are propogated to the
- * top of the elaboration call tree.
- *
- * Attach line numbers to processes, gates and
- * assignment statements.
- *
- * Revision 1.10 1998/12/14 02:01:34 steve
- * Fully elaborate Sequential UDP behavior.
- *
- * Revision 1.9 1998/12/07 04:53:17 steve
- * Generate OBUF or IBUF attributes (and the gates
- * to garry them) where a wire is a pad. This involved
- * figuring out enough of the netlist to know when such
- * was needed, and to generate new gates and signales
- * to handle what's missing.
- *
- * Revision 1.8 1998/12/02 04:37:13 steve
- * Add the nobufz function to eliminate bufz objects,
- * Object links are marked with direction,
- * constant propagation is more careful will wide links,
- * Signal folding is aware of attributes, and
- * the XNF target can dump UDP objects based on LCA
- * attributes.
- *
- * Revision 1.7 1998/12/01 00:42:14 steve
- * Elaborate UDP devices,
- * Support UDP type attributes, and
- * pass those attributes to nodes that
- * are instantiated by elaboration,
- * Put modules into a map instead of
- * a simple list.
- *
- * Revision 1.6 1998/11/23 00:20:22 steve
- * NetAssign handles lvalues as pin links
- * instead of a signal pointer,
- * Wire attributes added,
- * Ability to parse UDP descriptions added,
- * XNF generates EXT records for signals with
- * the PAD attribute.
- *
- * Revision 1.5 1998/11/21 19:19:44 steve
- * Give anonymous modules a name when elaborated.
- *
- * Revision 1.4 1998/11/11 03:13:04 steve
- * Handle while loops.
- *
- * Revision 1.3 1998/11/09 18:55:34 steve
- * Add procedural while loops,
- * Parse procedural for loops,
- * Add procedural wait statements,
- * Add constant nodes,
- * Add XNOR logic gate,
- * Make vvm output look a bit prettier.
- *
- * Revision 1.2 1998/11/07 17:05:05 steve
- * Handle procedural conditional, and some
- * of the conditional expressions.
- *
- * Elaborate signals and identifiers differently,
- * allowing the netlist to hold signal information.
- *
- * Revision 1.1 1998/11/03 23:28:56 steve
- * Introduce verilog to CVS.
- *
*/
View
26 netlist.h
@@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#if !defined(WINNT)
-#ident "$Id: netlist.h,v 1.52 1999/07/31 03:16:54 steve Exp $"
+#ident "$Id: netlist.h,v 1.53 1999/08/01 16:34:50 steve Exp $"
#endif
/*
@@ -58,6 +58,13 @@ struct functor_t;
* A link can be INPUT, OUTPUT or PASSIVE. An input never drives the
* signal, and PASSIVE never receives the value of the signal. Wires
* are PASSIVE, for example.
+ *
+ * A NetObj also has delays specified as rise_time, fall_time and
+ * decay_time. The rise and fall time are the times to transition to 1
+ * or 0 values. The decay_time is the time needed to decay to a 'bz
+ * value, or to decay of the net is a trireg. The exact and precise
+ * interpretation of the rise/fall/decay times is typically left to
+ * the target to properly interpret.
*/
class NetObj {
@@ -143,13 +150,13 @@ class NetObj {
unsigned pin_count() const { return npins_; }
- unsigned delay1() const { return delay1_; }
- unsigned delay2() const { return delay2_; }
- unsigned delay3() const { return delay3_; }
+ unsigned rise_time() const { return delay1_; }
+ unsigned fall_time() const { return delay2_; }
+ unsigned decay_time() const { return delay3_; }
- void delay1(unsigned d) { delay1_ = d; }
- void delay2(unsigned d) { delay2_ = d; }
- void delay3(unsigned d) { delay3_ = d; }
+ void rise_time(unsigned d) { delay1_ = d; }
+ void fall_time(unsigned d) { delay2_ = d; }
+ void decay_time(unsigned d) { delay3_ = d; }
void set_attributes(const map<string,string>&);
string attribute(const string&key) const;
@@ -1437,6 +1444,11 @@ extern ostream& operator << (ostream&, NetNet::Type);
/*
* $Log: netlist.h,v $
+ * Revision 1.53 1999/08/01 16:34:50 steve
+ * Parse and elaborate rise/fall/decay times
+ * for gates, and handle the rules for partial
+ * lists of times.
+ *
* Revision 1.52 1999/07/31 03:16:54 steve
* move binary operators to derived classes.
*
View
41 parse.y
@@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#if !defined(WINNT)
-#ident "$Id: parse.y,v 1.54 1999/07/31 19:14:47 steve Exp $"
+#ident "$Id: parse.y,v 1.55 1999/08/01 16:34:50 steve Exp $"
#endif
# include "parse_misc.h"
@@ -120,9 +120,10 @@ extern void lex_end_table();
%type <gate> gate_instance
%type <gates> gate_instance_list
-%type <expr> delay delay_opt delay_value delay_value_list
%type <expr> expression expr_primary
%type <expr> lavalue lpvalue
+%type <expr> delay_value
+%type <exprs> delay delay_opt delay_value_list
%type <exprs> expression_list
%type <exprs> range range_opt
@@ -247,7 +248,9 @@ defparam_assign_list
delay
: '#' delay_value
- { $$ = $2;
+ { svector<PExpr*>*tmp = new svector<PExpr*>(1);
+ (*tmp)[0] = $2;
+ $$ = tmp;
}
| '#' '(' delay_value_list ')'
{ $$ = $3;
@@ -282,11 +285,14 @@ delay_value
delay_value_list
: expression
- { $$ = $1; }
+ { svector<PExpr*>*tmp = new svector<PExpr*>(1);
+ (*tmp)[0] = $1;
+ $$ = tmp;
+ }
| delay_value_list ',' expression
- { yyerror(@1, "Sorry, delay value lists not supported.");
- $$ = $1;
- delete $3;
+ { svector<PExpr*>*tmp = new svector<PExpr*>(*$1, $3);
+ delete $1;
+ $$ = tmp;
}
;
@@ -986,13 +992,9 @@ module_item
}
}
| K_assign delay_opt lavalue '=' expression ';'
- { PGAssign*tmp = pform_make_pgassign($3, $5);
+ { PGAssign*tmp = pform_make_pgassign($3, $5, $2);
tmp->set_file(@1.text);
tmp->set_lineno(@1.first_line);
- if ($2) {
- yyerror(@2, "Sorry, assign delays not supported.");
- delete $2;
- }
}
| K_assign error '=' expression ';'
| K_always statement
@@ -1051,18 +1053,17 @@ module_item_list
net_decl_assign
: IDENTIFIER '=' expression
{ PEIdent*id = new PEIdent($1);
- PGAssign*tmp = pform_make_pgassign(id, $3);
+ PGAssign*tmp = pform_make_pgassign(id, $3, 0);
tmp->set_file(@1.text);
tmp->set_lineno(@1.first_line);
$$ = $1;
}
| delay IDENTIFIER '=' expression
{ PEIdent*id = new PEIdent($2);
- PGAssign*tmp = pform_make_pgassign(id, $4);
+ PGAssign*tmp = pform_make_pgassign(id, $4, $1);
tmp->set_file(@2.text);
tmp->set_lineno(@2.first_line);
$$ = $2;
- yyerror(@1, "Sorry, net assign delay not supported.");
}
;
@@ -1456,7 +1457,10 @@ statement
yyerror(@3, "Error in while loop condition.");
}
| delay statement_opt
- { PDelayStatement*tmp = new PDelayStatement($1, $2);
+ { PExpr*del = (*$1)[0];
+ if ($1->count() != 1)
+ yyerror(@1, "Sorry, delay lists not supported here.");
+ PDelayStatement*tmp = new PDelayStatement(del, $2);
tmp->set_file(@1.text);
tmp->set_lineno(@1.first_line);
$$ = tmp;
@@ -1484,7 +1488,10 @@ statement
$$ = tmp;
}
| lpvalue '=' delay expression ';'
- { PAssign*tmp = new PAssign($1,$3,$4);
+ { PExpr*del = (*$3)[0];
+ if ($3->count() != 1)
+ yyerror(@1, "Sorry, delay lists not supported here.");
+ PAssign*tmp = new PAssign($1,del,$4);
tmp->set_file(@1.text);
tmp->set_lineno(@1.first_line);
$$ = tmp;
View
30 pform.cc
@@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#if !defined(WINNT)
-#ident "$Id: pform.cc,v 1.35 1999/07/31 19:15:21 steve Exp $"
+#ident "$Id: pform.cc,v 1.36 1999/08/01 16:34:50 steve Exp $"
#endif
# include "compiler.h"
@@ -267,7 +267,7 @@ void pform_make_udp(const char*name, list<string>*parms,
* gates and calls the pform_makegate function to make the individual gate.
*/
void pform_makegate(PGBuiltin::Type type,
- unsigned long delay_val,
+ svector<PExpr*>* delay,
const lgate&info)
{
if (info.parms_by_name) {
@@ -277,7 +277,7 @@ void pform_makegate(PGBuiltin::Type type,
return;
}
- PGBuiltin*cur = new PGBuiltin(type, info.name, info.parms, delay_val);
+ PGBuiltin*cur = new PGBuiltin(type, info.name, info.parms, delay);
if (info.range[0])
cur->set_range(info.range[0], info.range[1]);
@@ -288,13 +288,10 @@ void pform_makegate(PGBuiltin::Type type,
}
void pform_makegates(PGBuiltin::Type type,
- PExpr*delay, svector<lgate>*gates)
+ svector<PExpr*>*delay, svector<lgate>*gates)
{
- unsigned long delay_val = delay? evaluate_delay(delay) : 0;
- delete delay;
-
for (unsigned idx = 0 ; idx < gates->count() ; idx += 1) {
- pform_makegate(type, delay_val, (*gates)[idx]);
+ pform_makegate(type, delay, (*gates)[idx]);
}
delete gates;
@@ -370,12 +367,20 @@ void pform_make_modgates(const string&type, svector<lgate>*gates)
delete gates;
}
-PGAssign* pform_make_pgassign(PExpr*lval, PExpr*rval)
+PGAssign* pform_make_pgassign(PExpr*lval, PExpr*rval,
+ svector<PExpr*>*del)
{
svector<PExpr*>*wires = new svector<PExpr*>(2);
(*wires)[0] = lval;
(*wires)[1] = rval;
- PGAssign*cur = new PGAssign(wires);
+
+ PGAssign*cur;
+
+ if (del == 0)
+ cur = new PGAssign(wires);
+ else
+ cur = new PGAssign(wires, del);
+
pform_cur_module->add_gate(cur);
return cur;
}
@@ -657,6 +662,11 @@ int pform_parse(const char*path, map<string,Module*>&modules,
/*
* $Log: pform.cc,v $
+ * Revision 1.36 1999/08/01 16:34:50 steve
+ * Parse and elaborate rise/fall/decay times
+ * for gates, and handle the rules for partial
+ * lists of times.
+ *
* Revision 1.35 1999/07/31 19:15:21 steve
* misspelled comment.
*
View
12 pform.h
@@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#if !defined(WINNT)
-#ident "$Id: pform.h,v 1.25 1999/07/31 19:14:47 steve Exp $"
+#ident "$Id: pform.h,v 1.26 1999/08/01 16:34:50 steve Exp $"
#endif
# include "netlist.h"
@@ -138,13 +138,14 @@ extern bool pform_expression_is_constant(const PExpr*);
* name) and connects it to the specified wires.
*/
extern void pform_makegates(PGBuiltin::Type type,
- PExpr*delay,
+ svector<PExpr*>*delay,
svector<lgate>*gates);
extern void pform_make_modgates(const string&type, svector<lgate>*gates);
/* Make a continuous assignment node, with optional bit- or part- select. */
-extern PGAssign* pform_make_pgassign(PExpr*lval, PExpr*rval);
+extern PGAssign* pform_make_pgassign(PExpr*lval, PExpr*rval,
+ svector<PExpr*>*delays);
/* Given a port type and a list of names, make a list of wires that
@@ -166,6 +167,11 @@ extern void pform_dump(ostream&out, Module*mod);
/*
* $Log: pform.h,v $
+ * Revision 1.26 1999/08/01 16:34:50 steve
+ * Parse and elaborate rise/fall/decay times
+ * for gates, and handle the rules for partial
+ * lists of times.
+ *
* Revision 1.25 1999/07/31 19:14:47 steve
* Add functions up to elaboration (Ed Carter)
*
View
39 pform_dump.cc
@@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#if !defined(WINNT)
-#ident "$Id: pform_dump.cc,v 1.31 1999/07/31 19:14:47 steve Exp $"
+#ident "$Id: pform_dump.cc,v 1.32 1999/08/01 16:34:50 steve Exp $"
#endif
/*
@@ -209,10 +209,23 @@ void PGate::dump_pins(ostream&out) const
}
}
+void PGate::dump_delays(ostream&out) const
+{
+ if (delay_[0] && delay_[1] && delay_[2])
+ out << "#(" << *delay_[0] << "," << *delay_[1] << "," <<
+ *delay_[2] << ")";
+ else if (delay_[0])
+ out << "#" << *delay_[0];
+ else
+ out << "#0";
+
+}
+
void PGate::dump(ostream&out) const
{
- out << " " << typeid(*this).name() << " #"
- << get_delay() << " " << get_name() << "(";
+ out << " " << typeid(*this).name() << " ";
+ dump_delays(out);
+ out << " " << get_name() << "(";
dump_pins(out);
out << ");" << endl;
@@ -220,26 +233,29 @@ void PGate::dump(ostream&out) const
void PGAssign::dump(ostream&out) const
{
- out << " assign " << *pin(0) << " = " << *pin(1) << ";" << endl;
+ out << " assign ";
+ dump_delays(out);
+ out << " " << *pin(0) << " = " << *pin(1) << ";" << endl;
}
void PGBuiltin::dump(ostream&out) const
{
switch (type()) {
case PGBuiltin::BUFIF0:
- out << " bufif0 #";
+ out << " bufif0 ";
break;
case PGBuiltin::BUFIF1:
- out << " bufif1 #";
+ out << " bufif1 ";
break;
case PGBuiltin::NAND:
- out << " nand #";
+ out << " nand ";
break;
default:
- out << " builtin gate #";
+ out << " builtin gate ";
}
- out << get_delay() << " " << get_name();
+ dump_delays(out);
+ out << " " << get_name();
if (msb_) {
out << " [" << *msb_ << ":" << *lsb_ << "]";
@@ -578,6 +594,11 @@ void PUdp::dump(ostream&out) const
/*
* $Log: pform_dump.cc,v $
+ * Revision 1.32 1999/08/01 16:34:50 steve
+ * Parse and elaborate rise/fall/decay times
+ * for gates, and handle the rules for partial
+ * lists of times.
+ *
* Revision 1.31 1999/07/31 19:14:47 steve
* Add functions up to elaboration (Ed Carter)
*
View
13 t-verilog.cc
@@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#if !defined(WINNT)
-#ident "$Id: t-verilog.cc,v 1.6 1999/07/03 02:12:52 steve Exp $"
+#ident "$Id: t-verilog.cc,v 1.7 1999/08/01 16:34:50 steve Exp $"
#endif
/*
@@ -78,8 +78,8 @@ void target_verilog::signal(ostream&os, const NetNet*net)
if (net->pin_count() > 1)
os << " [" << net->msb() << ":" << net->lsb() << "]";
- if (net->delay1())
- os << " #" << net->delay1();
+ if (net->rise_time())
+ os << " #" << net->rise_time();
os << " " << mangle(net->name()) << ";" << endl;
}
@@ -111,7 +111,7 @@ void target_verilog::logic(ostream&os, const NetLogic*net)
break;
}
- os << " #" << net->delay1() << " " << mangle(net->name()) << "(";
+ os << " #" << net->rise_time() << " " << mangle(net->name()) << "(";
unsigned sidx;
const NetNet*sig = find_link_signal(net, 0, sidx);
@@ -271,6 +271,11 @@ const struct target tgt_verilog = {
/*
* $Log: t-verilog.cc,v $
+ * Revision 1.7 1999/08/01 16:34:50 steve
+ * Parse and elaborate rise/fall/decay times
+ * for gates, and handle the rules for partial
+ * lists of times.
+ *
* Revision 1.6 1999/07/03 02:12:52 steve
* Elaborate user defined tasks.
*
View
25 t-vvm.cc
@@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#if !defined(WINNT)
-#ident "$Id: t-vvm.cc,v 1.32 1999/07/18 21:17:51 steve Exp $"
+#ident "$Id: t-vvm.cc,v 1.33 1999/08/01 16:34:50 steve Exp $"
#endif
# include <iostream>
@@ -530,36 +530,36 @@ void target_vvm::logic(ostream&os, const NetLogic*gate)
switch (gate->type()) {
case NetLogic::AND:
os << "static vvm_and" << "<" << gate->pin_count()-1 <<
- "," << gate->delay1() << "> ";
+ "," << gate->rise_time() << "> ";
break;
case NetLogic::BUFIF0:
- os << "static vvm_bufif0<" << gate->delay1() << "> ";
+ os << "static vvm_bufif0<" << gate->rise_time() << "> ";
break;
case NetLogic::BUFIF1:
- os << "static vvm_bufif1<" << gate->delay1() << "> ";
+ os << "static vvm_bufif1<" << gate->rise_time() << "> ";
break;
case NetLogic::NAND:
os << "static vvm_nand" << "<" << gate->pin_count()-1 <<
- "," << gate->delay1() << "> ";
+ "," << gate->rise_time() << "> ";
break;
case NetLogic::NOR:
os << "static vvm_nor" << "<" << gate->pin_count()-1 <<
- "," << gate->delay1() << "> ";
+ "," << gate->rise_time() << "> ";
break;
case NetLogic::NOT:
- os << "static vvm_not" << "<" << gate->delay1() << "> ";
+ os << "static vvm_not" << "<" << gate->rise_time() << "> ";
break;
case NetLogic::OR:
os << "static vvm_or" << "<" << gate->pin_count()-1 <<
- "," << gate->delay1() << "> ";
+ "," << gate->rise_time() << "> ";
break;
case NetLogic::XNOR:
os << "static vvm_xnor" << "<" << gate->pin_count()-1 <<
- "," << gate->delay1() << "> ";
+ "," << gate->rise_time() << "> ";
break;
case NetLogic::XOR:
os << "static vvm_xor" << "<" << gate->pin_count()-1 <<
- "," << gate->delay1() << "> ";
+ "," << gate->rise_time() << "> ";
break;
}
@@ -1287,6 +1287,11 @@ extern const struct target tgt_vvm = {
};
/*
* $Log: t-vvm.cc,v $
+ * Revision 1.33 1999/08/01 16:34:50 steve
+ * Parse and elaborate rise/fall/decay times
+ * for gates, and handle the rules for partial
+ * lists of times.
+ *
* Revision 1.32 1999/07/18 21:17:51 steve
* Add support for CE input to XNF DFF, and do
* complete cleanup of replaced design nodes.

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