This patch modifies the compiler and the ivl interface to pass the type of indexed part select that is being represented (up/down) in a procedural L-value or R-value. This is needed by any back end that wants to correctly denormalize the (zero based) base expression.
In a self determined context the width of the power operator is defined to be the left argument width.
This fixes up the elaboration of binary expressions found in parameter expressions. Parameter expressions are special because they elaborate early, before all the other parameters are necessarily completed.
In some cases, it was possible for the NetEConcat expression to lose track of the repeat expression, causing the output result to have a broken concatenation expression. This also adds some internal checks that the concatenation widths add up properly.
The natures of disciplines were already available, this just brings the information forward to the ivl_target.h API and exposes them via access functions.
When doing lossless addition to an unsized constant, we make the size be width of an integer, only to be consistent with other tools. In fact, don't go overboard if we don't have to.
The arguments to bitwise operators are padded if *either* of the operands is unsigned. This is according to the sign/unsigned expression rules of Verilog, and also matches the behavior of the "Big-3."
When a multiply expression is IVL_VT_REAL, then the default width is the width of the operands, and not the sum of the operands. In fact, it should turn out to be 1. Also, the width of the multiply expression when we get to the ivl_target API, need not be the sum of the widths of its arguments. In fact, if the arguments are signed, that would be completely wrong. So adjust the stub target to properly test this constraint.
The NetBranch object is connected, but not like an object, so the NetPins object base class is factored out from NetObj to handle the connectivity, and the NetBranch class uses the NetPins to connect a branch. Also, account for the fact that nets with a discipline are by default real-valued.
Before this, the types of parameters were always logic, only the width and signed-ness could be controlled. A parameter may take on implicit real values if the expression were real. With this patch, the type for the parameter can be explicitly set to logic or real. This also means that the parameter real valued expressions need to be more crefully treated, possibly with casting integral expressions to real values, or real expressions to integral values.
If there is an x or z bin in the sign position of a logic number to be padded, pad with the x or z, not zero.
Implement in behavioral the abs/min/max operators for real values. The parser treats these builtin functions as operators, unary or binary, and elaborates them appropriately. Also add enough code generator support to handle real valued expressions in thread context.
This patch reworks much of the ternary code to short circuit when possible and supports real values better. It adds a blend operator for real values that returns 0.0 when the values differ and the value when they match. This deviates slightly from the standard which specifies that the value for reals is always 0.0 when the conditional is 'bx. There are also a couple bug fixes. These fixes have not been ported to continuous assignments yet. Ternary operators used at compile time and in procedural assignments should be complete (short circuit and support real values).
This patch adds the power operator for signed bit based values in a continuous assignment. It also fixes a few other power expression width problems. The expression width is still not calculated correctly, since the correct method can produce huge possible bit widths. The result is currently limited to the width of the native long. This is because lround() is used to convert from a double to an integer. A check in the code generator protects the runtime from this limitation.