In vvp, create the .var/str variable for representing strings, and handle strings in the $display system task. Add to vvp threads the concept of a stack of strings. This is going to be how complex objects are to me handled in the future: forth-like operation stacks. Also add the first two instructions to minimally get strings to work. In the parser, handle the variable declaration and make it available to the ivl_target.h code generator. The vvp code generator can use this information to generate the code for new vvp support.
An important advantage of program blocks is its ability to nest within a module. This winds up also allowing modules to nest, which is legal but presumably less used feature.
This patch extends the compiler to support all specparam declarations allowed by the 1364-2005 standard. For compatibility with other simulators, it allows specparam values to be used in any constant expression, but outputs a warning message and disables run-time annotation of a specparam if it is used in an expression that must be evaluated at compile time.
This is a cleanup in preparation for better support of range lists. (cherry picked from commit 8f7cf32) Conflicts: PTask.h elab_scope.cc elab_sig.cc parse.y pform.cc pform.h pform_types.h Signed-off-by: Stephen Williams <firstname.lastname@example.org>
Class methods belong in a class scope, not the containing module. So create a lexical scope that carries tasks and functions and create a PClass to represent classes.
…thod. This adds the vector_type_t and real_type_t types to handle vector and real types in tf_port items. This cleans up a lot of the parsing for these items.
During parse/pform processing, convert increment statements to the equivalent compressed assignment statement. This is less weird for elaboration processing and better expresses what is going on.
This gets me to the point where the parser stashes a defined type, and the lexical analyzer uses the type names to differentiate IDENTIFIER and TYPE_IDENTIFIER.
Parse typedefs with structs and enums, but give a sorry message, because they are not yet supported. Rearrange some of the parse rules for variables in order to increase comonality with the typedef rules.
SystemVerilog has support for time literals. The time literal for example #10ns, adds a delay of 10ns no matter the time unit currently in effect. For more details please refer to http://iverilog.wikia.com/wiki/Projects#SystemVerilog_Style_Time_Literals Tested-by: Oswaldo Cadenas <email@example.com> Signed-off-by: Prasad Joshi <firstname.lastname@example.org>
This patch fixes the following problem in the compiler: An integer task argument should be marked as an integer port. An implicit register can be converted to either a reg or an integer. An old style task port should default to <no type> unless reg or some other type is provided. ANSI style is always defined. For example: input ri; output ro; inout rio; real ri, ro, rio; should define all three task ports to be of type real.
Allow more complex enumeration expressions, which means putting off the evaluation of the expression values until elaboration.
The pform propagates the parsed enum base type information to the elaborator so that the base type can be fully elaborated. This is necessary to get the types of the enumeration literals correct.
I'm adding more uses of the make_range_from_width function, so it seems like time to get rid of its use of the svector template. This thread led to a lot of other uses of svector that had to also be removed.