We really want lazy processing of concatenation because it has multiple inputs and lazy processing should (in theory) prevent redundant and useless propagations through the net. But enabling it seems to cause many tests in the regression test suite to fail to compare their results. There are races in many tests that are interacting badly with this feature. So for now, ifdef it out.
It doesn't really make any sense to do lazy processing of part selects, but it is possible to use the part select position to more toroughly check for changes in output and suppress non-changes. In particular, we only need to check that the output part actually changes, and by the way we only need to save those bits for the next go-round. We do want to make sure that the very first input causes an output, though, so that time-0 values get propagated.
This is not a solution to all the problems, but is a better catch-all then what is currently there. Allow the index field to be a T<> that accesses the thread to get the address index. Note that the lexor.lex currently returns the T<> as a T_SYMBOL, and the users of T_SYMBOL objects need to interpret the meaning. This is probably not the best idea, in light of all the other *<> formats that now exist.
Part selects to signals are allowed to be off the ends of the signal itself. The bits that are beyond the vector return X. This may mean creating constant X bits on one or both ends of the result.
…ects. The vvp_net_t objects are never deleted, so overload the new operator to do a more space efficient permanent allocation. The %assign/v instruction copied the vvp_vector4_t object needlessly on its way to the scheduler. Eliminate that duplication.
The concat and resolv functors are best evaluated lazily, because each evaluation is costly and there is a high probability that an evaluation will be invalidated when new input comes in. Also optimization the recv_vec4_pv method of the resolver, which is commonly used, and adjust the order of handling of vvp_fun_part to work more efficiently.
The vvp_vector8_t constructor and destructor involve memory allocation so it is best to pass these objects by reference as much as possible. Also rework the resolver functor to only perform resolution after inputs are in so that it doesn't get needlessly repeated. This eliminates many resolve function calls, as well as activations throughout the net. Also have the islands take more care not to perform resolution if the inputs aren't really different.
localparam declarations were messing up the state of parser variables so that the default types of following parameters got messed up.
If a memory word was accessed before it was defined the code was returning a zero width vector result. Now it returns an appropriately sized vector of 'x'.
Tran devices linked in series were not getting properly joined up due to a problem with the add_branch method.
This patch cleans up the dump routines and adds file and line number information for errors. It also adds some of the missing MemoryWord properties so they can now be dumped and monitored correctly.
This patch adds $simparam and $simparam$str from Verilog-A. The analog simulator parameters return 0.0 or N/A. The vvp_cpu_wordsize system function has been moved into the $simparam call and is now named CPUWordSize. This patch also starts the factoring of common code in the vpi directory. Some routines were renamed. The priv.c file was renamed to sys_priv.c to match the include file. System functions can now have strings put to their output.
Rather then join islands while branches are initially created, save the island creating for the end. This way, the process is actually recursive and greedy, reliably collecting branches into islands without conflict.