You can clone with
HTTPS or Subversion.
use bufif0 if z is in true case of mux.
tri01 support in vvm.
Extend x or z that is top bit of a constant.
Use the iverilog command in documentation.
Support <= in synthesis of DFF and ram devices.
Treat CR as white space in timespec lines.
Handle different forms of line end.
Report error when dumpfile is missing.
timescale and min:typ:max expressions *do* work onw.
Rearrange task and function elaboration so that the
NetTaskDef and NetFuncDef functions are created during
signal enaboration, and carry these objects in the
NetScope class instead of the extra, useless map in
the Design class.
Introduce min:typ:max support.
Report code generation errors through proc_delay.
fix problem coalescing events w/ probes.
Support elaboration of disable statements.
Parse disable statements to pform.
Get VCD timescale from design precision.
Make simulation precision available to VPI.
Fix RAM matching.
memory is not a data type in verilog.
Unlink z constants from nets.
Document ieee1364 issues.
Document time scale in netlists.
Parse and elaborate timescale to scopes.
Handle some edge cases during node scans.
Detect muxing Vz as a bufufN.
Move inital value handling from NetNet to Nexus
objects. This allows better propogation of inital
Clean up constant propagation a bit to account
for regs that are not really values.
More detailed handling of exit status from commands.
proper init method for bufz devices.
Better handle failures to build lexor_keyword.cc
Add the dist_uniform function.
Allow set vpiIntVal on bitset type objects.
pass zero-delay values immediately.
Eleminate reduction gate for 1-bit compares.