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Handle out of range part select expressions.
Get at gate information for ivl_target interface.
Clean up warnings and portability issues.
Add ivl_target support for logic gates, and
make the interface more accessible.
Add target calls for scope, events and logic.
Proper error messages when port direction is missing.
add th t-dll functions for net_const, net_bufz and processes.
use -fPIC for sparc.
Limit signal scope search at module boundaries.
Start stub for loadable targets.
Move all file manipulation out of target class.
Add the -N switch to the iverilog command.
target methods need not take a file stream.
Add vpi_vlog_info support from Adrian
use bufif0 if z is in true case of mux.
tri01 support in vvm.
Extend x or z that is top bit of a constant.
Use the iverilog command in documentation.
Support <= in synthesis of DFF and ram devices.
Treat CR as white space in timespec lines.
Handle different forms of line end.
Report error when dumpfile is missing.
timescale and min:typ:max expressions *do* work onw.
Rearrange task and function elaboration so that the
NetTaskDef and NetFuncDef functions are created during
signal enaboration, and carry these objects in the
NetScope class instead of the extra, useless map in
the Design class.
Introduce min:typ:max support.
Report code generation errors through proc_delay.
fix problem coalescing events w/ probes.
Support elaboration of disable statements.
Parse disable statements to pform.
Get VCD timescale from design precision.
Make simulation precision available to VPI.
Fix RAM matching.
memory is not a data type in verilog.
Unlink z constants from nets.