Make configure detect malloc.h
Support != in virtex code generator.
Add XOR and XNOR gates.
Elaborate == to NetCompare instead of XNOR and AND
gates. This allows code generators to generate
better code in certain cases.
Generate code for identity comparators.
Xilinx uses GROUND and VCC as pin names for the
GND and VCC devices.
Connect the top end of the EQ chain to the MUXCY
instead of to the LUT. The MUXCY has the real output.
Use carry mux to implement wide identity compare,
Place property item in correct place in LUT cell list.
initial structural memory propagation (Stephan Boettcher)
Add 4 wide identity compare.
Virtex support for mux devices and adders
with carry chains. Also, make Virtex specific
implementations of primitive logic.
pin down some enumerated constants.
Connect right ANEB pin when doing NE comparator.
No code for unlinked constants.
extend xz from the top character, not the second-from-top.
Redo of_SUBU in a more obvious algorithm, that
is not significantly slower. Also, clean up the
implementation of %mov from a constant.
Fix initial clearing of vector by vector_to_array
Separate the virtex and generic-edif code generators.
Add documentation for the code generator.
Add virtex support for some basic logic, the DFF
and constant signals.
Rearrange the XNF code generator to be generic-xnf
so that non-XNF code generation is also possible.
Start into the virtex EDIF output driver.
Generic ADD code.
Generate code for MUX devices.
identity compare, and PWR records for constants.
Make constants available through the design root
Relax pin count restriction on logic gates.
synthesize the special case of compare with 0.
Support DFF CE inputs.
Handle more path polarity cases.
Parse $setuphold statements.
Add the fpga target.
Many more logic gate types.
Add root port SIG records.
Handle update in place of repeat constants.
Bind escaped names with non-escaped equivilents. (PR#256)