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Commits on Aug 31, 2008
  1. Fix a bug in vector evaluation of abs().

    steveicarus committed Aug 31, 2008
    The calculation of the abs of a signed value
    was inverting the value if it was signed,
    and not if it was negative.
Commits on Aug 30, 2008
  1. Fix right shift of vvp_vector2_t.

    steveicarus committed Aug 30, 2008
    The right shift of vvp_vector2_t needs to
    account for and mask off shifted bits. Otherwise
    there will be unexpected results after
    a vvp_vector2_t::trim method.
  2. Remove unneeded real compare code.

    caryr committed with steveicarus Aug 30, 2008
    The code removed is unneeded since real values are already
    handled by the real specific comparison that is called at
    the beginning of each function.
  3. Add the Verilog-2005 and Verilog-AMS constant system functions.

    steveicarus committed Aug 30, 2008
    This patch adds the constant system functions for Verilog-2005
    and Verilog-AMS. These are evaluated at compile time. $abs(),
    $min() and $max() support their polymorphic behavior in the
    compiler where it really matters. They are always evaluated
    as reals in the run time and the result/argument(s) will be
    converted as needed.
    
    The Verilog-2005 functions are available if using the 2005
    generation (default) and if either the icarus-misc (also on
    by default) or verilog-ams flags are set.
    
    The Verilog-AMS functions are available if either the
    icarus-misc or verilog-ams flags are set.
  4. Evaluate constant real EQ and NE constructs.

    caryr committed with steveicarus Aug 29, 2008
    This patch adds code to evaluate constant == and != with real values.
  5. More NaN constant fixes.

    caryr committed with steveicarus Aug 29, 2008
    This patch cleans up %loadi/wr regarding NaN values. It also
    fixes the code generator to correctly output a NaN value as
    a Cr<> constant.
  6. Handle NaN constant in the code generator and fix loadi/wr NaN bug.

    caryr committed with steveicarus Aug 29, 2008
    This patch fixes a bug in %loadi/wr regarding NaN values. It also
    fixes the code generator to correctly output a NaN value.
  7. Remove dead EEQ code.

    steveicarus committed Aug 29, 2008
    The EEQ function is handled by vvp_cmp_eeq, an arithmetic expression
    processor and the logic version of EEQ is never used.
  8. Clean up $clog2() measurement of unsized numbers.

    steveicarus committed Aug 29, 2008
    If the argument to $clog2() is unsized constant, then trim it to the
    smallest representation that doesn't lose the sign, then do the $clog2
    on that.
    
    Also, use integer_width instead of 32 for the minimum $clog2() result
    for a negative value.
Commits on Aug 29, 2008
  1. Fix the always zero delay check to happen after elaboration.

    caryr committed with steveicarus Aug 28, 2008
    This patch moves the always zero or possibly zero delay checks
    to a point after the circuit is full elaborated. Before it
    could try to check tasks that had not already been evaluated
    resulting in a crash.
  2. Work around a flex limitation with yyrestart()

    caryr committed with steveicarus Aug 28, 2008
    See the comments added with this patch for more information.
  3. Optimize block delay type check

    caryr committed with steveicarus Aug 28, 2008
    When looking for a delay_type() in a block stop when we have a
    DEFINITE_DELAY. Doing this could reduce the number of statements
    that need to be checked.
  4. Spelling fixes

    ldoolitt committed with steveicarus Aug 28, 2008
    Comments only, no code changes
Commits on Aug 28, 2008
  1. Ensure binary operands have correct signedness

    nickg committed Aug 28, 2008
    Previously only signedness was only corrected for the
    result. This patch ensures the VHDL operands have the
    same signedness as their Verilog counterparts.
    
    This fixes a few of the signedX tests.
  2. By default convert a recv_vec8_pv to a recv_vec4_pv

    caryr committed with steveicarus Aug 28, 2008
    Assume that anything that is strength aware already handles a
    recv_vec8_pv and make the default function convert the bits
    to a vec4 and then call recv_vec4_pv with this new value.
  3. Variable arrays need to keep their signedness.

    caryr committed with steveicarus Aug 28, 2008
    Since variable arrays create their elements dynamically the base array
    structure for them needs to keep the signedness information.
  4. Make &A and &PV nestable.

    caryr committed with steveicarus Aug 27, 2008
    This patch makes it so that &A and &PV can nest for the symbol
    argument. This allows nested array selects, etc.
  5. Don't crash looking for delay_type of empty task.

    steveicarus committed Aug 28, 2008
    It is legal for a task to have no definition. In that case, the
    delay_type calculations (used to detect infinite loops) can assume
    that an empty definition is a no-op and return NO_DELAY.
  6. Better optimization of constants in expressions

    steveicarus committed Aug 28, 2008
    Be more sophisticated with the code generated for constant values.
    When values are large, use an optimal mix of %movi and %mov
    instructions to get the desired value, no matter what the content.
  7. Broken run-time wide divide.

    steveicarus committed Aug 28, 2008
    The wide-divide function was broke. It generated bad results.
Commits on Aug 27, 2008
  1. Finish cast.cc cleanup

    nickg committed Aug 27, 2008
    Replace big if statement with switch statemetn
  2. Refactor and clean up cast.cc

    nickg committed Aug 27, 2008
    This splits up the monolithic and confusing vhdl_expr::cast function into
    several smaller to_XXX functions which each generate code to cast an 
    expression to type XXX. This makes it much easier to understand and maintain.
Commits on Aug 26, 2008
  1. Correctly cast strlen() for %*s width argument.

    caryr committed with steveicarus Aug 26, 2008
    We had fixed many of these warning before, but I missed this
    one since this file was not part of the distribution when we
    fixed the other cases.
Commits on Aug 25, 2008
Commits on Aug 23, 2008
  1. Print a better message for instance port expression errors.

    caryr committed with steveicarus Aug 23, 2008
    This patch adds code to print an error message when there is
    a syntax error in the port expression list.
  2. Error message for missing system tasks/functions.

    caryr committed with steveicarus Aug 21, 2008
    This patch adds an error message for the standard system
    tasks and functions that are not currently implemented.
    These are currently $fmonitor*, $ferror, $fread, the
    queue and PLA tasks.
Commits on Aug 22, 2008
  1. Remove redundant function

    nickg committed Aug 22, 2008
  2. Support conversion of (un)signed to std_logic

    nickg committed Aug 22, 2008
    Take the least-significant bit. This fixes a couple of broken
    test cases.
  3. Catch case where component name and instance differ only in case

    nickg committed Aug 22, 2008
    This causes an error in VHDL (which is case-insensitive). This 
    patch simply appends _Inst to the instance name if it detects this.