Commits on May 9, 2012
  1. Repair handling of attributes attached to variables.

    (cherry picked from commit 5d05d97)
    committed May 9, 2012
Commits on May 1, 2012
  1. Fix check for SV continuous assign to variable.

    SystemVerilog allows a variable to be used as a variable OR
    as an unresolved wire. The detection of this case was checking
    the references to the affected value, instead of the l-value
    (cherry picked from commit cceeaa30f27260cd444015cb39b04353cb858768)
    committed Apr 16, 2012
Commits on Apr 30, 2012
  1. Disable width minimisation of literal numbers passed to system tasks.

    The final step of expression elaboration is to reduce the width of
    lossless/unsized constant expressions to the minimum needed to hold
    the resulting constant value. This leads to unexpected results if
    the user supplies a literal number with redundant digits that gets
    passed to a system task that is sensitive to the width (e.g. $display).
    This patch prevents width reduction occurring in this case.
    Martin Whitaker committed with Apr 30, 2012
  2. Handle case generate under a conditional generate that is unnamed.

    When a conditional statement is unnamed, it doesn't create a scope
    and we get into "direct" generate scheme elaboration. This direct
    elaboration needs to handle case generate schemes.
    committed Apr 30, 2012
Commits on Apr 28, 2012
  1. @GordonMcGregor
  2. Improved behaviour of tranif when control is 'x' or 'z'.

    The IEEE standard does not specify the behaviour of a tranif primitive
    when its control input is an 'x' or 'z'. vvp currently treats these as
    if the tran was turned off, but it would be better to propagate the
    uncertainty to the tran bi-directional ports. For compatibility with
    other simulators, we adopt the behaviour specified for MOS primitives.
    Martin Whitaker committed with Mar 14, 2012
Commits on Apr 11, 2012
  1. @caryr
  2. @caryr

    Spelling fix

    caryr committed Apr 11, 2012
Commits on Apr 10, 2012
  1. Ranges are ranges, not expression lists.

    This is a cleanup in preparation for better support of range lists.
    (cherry picked from commit 8f7cf3255acad55841f8b3725e3786ef49daad68)
    Signed-off-by: Stephen Williams <>
    committed Apr 10, 2012
Commits on Apr 9, 2012
  1. @ldoolitt @caryr

    Spelling refresh

    ldoolitt committed with caryr Apr 6, 2012
  2. @caryr

    SystemVerilog unbased literals cannot take a size.

    The SystemVerilog unbased literals (e.g. '0, '1, etc.) are expected to be
    used standalone and cannot take a size. This patch modifies the parsing
    code to give a good error message when this is done.
    caryr committed Apr 9, 2012
Commits on Apr 3, 2012
  1. @caryr

    Add code to test the width of individual structure elements.

    This patch adds code to correctly set the type and width of individual
    structure elements. Note the sign information is not currently available.
    caryr committed Apr 3, 2012
  2. Merge branch 'x-ms1'

    committed Apr 3, 2012
Commits on Apr 2, 2012
  1. @caryr

    Update vecval size calculation in vvp and vpi code.

    The standard specifies that the size of a vecval should be calculated as
    (size - 1)/32 + 1. When size is a PLI_INT32 this is needed to prevent an
    overflow, but when the size is unsigned this can be simplified to
    (size + 31)/32 since the size must fit into an integer, but we have an
    extra significant bit in an unsigned so no overflow can happen.
    This patch changes the code to use the correct version of the equation
    depending on the context.
    The previous patch does this in vvp/
    caryr committed Apr 1, 2012
  2. @caryr

    For a delayed vpi_put_value() copy any pointer data members.

    When vpi_put_value() is asked to delay the assignment any pointer data
    needs to be duplicated so that the caller can clean up the locally
    allocated memory without causing memory access problems.
    Also update word calculation to match the next patch.
    caryr committed Apr 1, 2012
Commits on Mar 12, 2012
  1. @caryr

    Fix for pr3499807.

    If a tranif gate has a delay, the vvp code generator needs to generate
    a unique label for the island port used for the tranif enable, to
    prevent a name collision if the undelayed signal is also connected
    to the island.
    Also add an assertion in vvp to catch bugs like this.
    Martin Whitaker committed with caryr Mar 9, 2012
Commits on Mar 11, 2012
  1. Allow variable initialization in any scope.

    This is a SystemVerilog feature, so only allow it when
    compiling SystemVerilog files.
    committed Mar 11, 2012
  2. Get the scope of class methods right

    Class methods belong in a class scope, not the containing module.
    So create a lexical scope that carries tasks and functions and
    create a PClass to represent classes.
    committed Mar 11, 2012
Commits on Mar 10, 2012
  1. Parse SystemVerilog syntax for task calls.

    Tasks call arguments may be dropped in favor of default values.
    Allow for that in the syntax. This requires a little handling
    of the non-SystemVerilog case during elaboration.
    committed Mar 10, 2012
Commits on Mar 5, 2012
  1. Miscellaneous SystemVerilog syntax.

    ... and sorry messages.
    committed Mar 5, 2012
Commits on Mar 3, 2012
  1. Handle complexities of class name pre-declarations

    Class names can be declared early, before definitions, so that the
    name can be used as a type name. This thus allows class definitions
    to be separate from the declaration. This creates some complexity in
    the parser, since the lexor knows about the class names.
    committed Mar 3, 2012
Commits on Mar 2, 2012
Commits on Feb 27, 2012
  1. Parse function declarations in classes.

    Also add support for function end names when parsing SystemVerilog.
    committed Feb 27, 2012