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Dec 11, 2008

  1. Stephen Williams

    Merge branch 'master' into verilog-ams

    authored December 10, 2008
  2. Cary R.

    Make a copy of the local include directory so that it doesn't get lost.

    Some compilers when optimizing can overwrite the path before it is
    read so make a copy of the local include directory and free it when
    we are done.
    authored December 10, 2008 steveicarus committed December 10, 2008
  3. Cary R.

    Check system() return when getting version information.

    We were not checking the return of the two system calls used
    to get the version information from ivlpp and ivl. This patch
    adds checks and prints an appropriate message if they fail.
    authored December 10, 2008 steveicarus committed December 10, 2008

Dec 10, 2008

  1. Stephen Williams

    Treat assignment into a task port exactly like blocking assignment.

    Reuse the code that the blocking assignment uses. This fixes makes
    the task port input assignment work better.
    authored December 09, 2008

Dec 09, 2008

  1. Cary R.

    Check for too few buf/not port expressions.

    This patch adds code to check that buf and not primitives have
    at least two port expressions. An error message is printed for
    this case.
    authored December 08, 2008 steveicarus committed December 08, 2008

Dec 08, 2008

  1. Nick Gasson

    Remove some uneccessary zero-time waits from VHDL outputs

    This patch optimises away straight line sequences like:
    wait for 0 ns;
    wait for X ns;
    wait for X ns;
    This tidies up the output a bit.
    It also has the effect of removing all code from initial
    processes where the assignments have been extracted as
    VHDL signal intialisers. (c.f. pr2391337)
    authored December 07, 2008 steveicarus committed December 07, 2008
  2. Nick Gasson

    Emit useful error message for pr2362211

    This prints out an error message rather than crashing out with
    an assertion failure when a function assigns to a non-local
    variable, which cannot be done in VHDL.
    authored December 07, 2008 steveicarus committed December 07, 2008
  3. Nick Gasson

    Rework VHDL assignment statement generation

    This changes the assignment statement generator so that
    each VHDL declaration "knows" which type of assignment
    statement can/should be used on (i.e. signals must be
    assigned with <=). This will help us catch cases when
    we try to use, for example, := with signals. This occurs
    in pr2362211 where we try to assign to a signal within
    a function (where only := can be used).
    authored December 07, 2008 steveicarus committed December 07, 2008
  4. Nick Gasson

    Fix assignment of constant to input

    If a module's input was connected to a nexus that contained
    a constant driver. That constant would be incorrectly generated
    as an assignment to the input *inside* the child module (instead
    of an assignment inside the instantiating module).
    authored December 06, 2008 steveicarus committed December 07, 2008

Dec 06, 2008

  1. Stephen Williams

    Remove most of the lingering CVS droppings.

    Remove the #ident and $Log$ strings from all the header files and
    almost all of the C/C++ source files. I think it is better to get
    this done all at once, then to wait for each of the files to be
    touched and edited in unrelated patches.
    authored December 05, 2008
  2. Larry Doolittle

    Allow building with gcc-4.4

    With this small patch, building succeeds with Debian's current gcc-snapshot,
    gcc (Debian 20081130-1) 4.4.0 20081130 (experimental) [trunk revision 142292]
    That gcc also warns about the remaining #idents in
    The resulting build shows some regressions in the test suite, that
    I am still investigating.  The patch does not break building, or show
    test suite regressions, with gcc-4.3.
    authored December 03, 2008 steveicarus committed December 05, 2008

Dec 02, 2008

  1. Cary R.

    Fix out of range indexed part selects and negative verinum width calc.

    This patch fixes fully out of range constant indexed part selects
    to just return 'bx. It also adds support for constant undefined
    base values which also just return 'bx.
    A bug in the bit width calculation when building an unsized, signed
    negative integer value was also fixed (-3 needs 3 bits not 2, etc.)
    authored December 01, 2008 steveicarus committed December 01, 2008
  2. Cary R.

    Add two missing function definitions.

    This patch adds the function definitions for ivl_expr_branch and
    ivl_expr_nature to the ivl.def file. This is needed to get Cygwin
    and MinGW to compile correctly.
    authored December 01, 2008 steveicarus committed December 01, 2008

Nov 30, 2008

  1. Stephen Williams

    Case statements need their expresions probed.

    Probe the widths of the case statement expressions. The expressions
    are self-determined in that context, but the probe is needed to
    setup the expression types.
    authored November 29, 2008
  2. Nick Gasson

    Add debugging output to VHDL target

    Prints progress when -pdebug=1 specified.
    Adds a new debug_msg function to print progress messages.
    authored November 29, 2008 steveicarus committed November 29, 2008

Nov 29, 2008

  1. Stephen Williams

    Seperate islands from tran/switch islands

    Tran islands are a kinds of island, so seperate the tran handling
    from the core island concept. This will allow for creating new
    kinds of islands. (Think analog.)
    authored November 29, 2008
  2. Stephen Williams

    probe expression widths of analog contribution expressions.

    The expressions of a contribution statement are real valued by
    definition, but we need to do the width probing anyhow in order
    to resolve types and the widths of subexpressions.
    authored November 28, 2008
  3. Stephen Williams

    Merge branch 'master' into verilog-ams

    authored November 28, 2008

Nov 28, 2008

  1. Stephen Williams

    Rework shift and power PExpr nodes for their special needs.

    The power (**) and shift operators are different from other binary
    operators because their expression width calculations rely only on
    their left operand, with their right operand self-determined. Get
    the handling of these operators out of the PEBinary base class to
    prevent confusion.
    authored November 28, 2008
  2. Stephen Williams

    More self-determined expressions need width probed.

    Find and fix some more expressions that are self-determined, that
    nevertheless need their widths probled.
    authored November 28, 2008
  3. Cary R.

    A power needs to use the signed (real pow) if either argument is signed.

    The power operator is different in that it uses the signed version
    if either of it's arguments are signed. This patch fixes the code
    generator to do this correctly.
    authored November 26, 2008 steveicarus committed November 28, 2008
  4. Cary R.

    Add the procedural signed power function.

    This patch adds the procedural power function %pow/s for signed
    values. This has bit based inputs and outputs, but uses the double
    pow() function to calculate the value.
    authored November 26, 2008 steveicarus committed November 28, 2008
  5. Stephen Williams

    Fix calculation of verinum==verinum

    This test was way to picky about the widths of the arguments. In real
    tests, the arguments may have different widths. This especially matter
    when comparing unsized values.
    authored November 27, 2008
  6. Stephen Williams

    Support direct nesting of conditional generate schemes.

    Verilog generate schemes support a special case where conditional
    generate schemes that contain only a nested conditional generate
    scheme do not create a new scope. Instead, it relies on the nested
    generate scheme to generate the scope.
    authored November 27, 2008

Nov 26, 2008

  1. Stephen Williams

    During test_width is not the time to assert on no_type

    unary expressions that have problems should not assert in the
    test_width method. Instead, let the error propagate back and be
    handled during expression elaboration. This found a few places
    where expression widths/types weren't probed before elaboration.
    authored November 26, 2008
  2. Nick Gasson

    Fix part select of width-1 vector

    Signals of width 1 are declared in VHDL as std_logic, as this
    is the usual way to represent them. Unfortunately, we cannot
    distinguish between
    reg [0:0] a;
    reg a;
    This patch avoids trying to slice a std_logic so a[0] is equivalent to a.
    authored November 26, 2008 steveicarus committed November 26, 2008
  3. Stephen Williams

    The iverilog-vpi script depends on the Makefile

    Building the iverilog-vpi script involves editing commands in the
    Makefile, so it makes sense for iverilog-vpi to depend on it.
    authored November 25, 2008
  4. Cary R.

    Update to have current version by default.

    This patch removes the CVS ident information from the
    files it also puts in the current version 0.9.devel for the default
    VERSION definition. This is normally passed down, but a local make
    will use the value from the local Makefile. This will eventually be
    replaced with a file based version to give us just one place to
    reliably modify the version.
    authored November 25, 2008 steveicarus committed November 25, 2008
  5. Stephen Williams

    Merge branch 'master' of ssh://…

    authored November 25, 2008
  6. Stephen Williams

    Install header files in includedir/iverilog

    Move the header files from includedir/verilog to .../iverilog
    because the verilog name is a little too generic. The iverilog-vpi
    command should handle the changes.
    authored November 25, 2008

Nov 25, 2008

  1. Cary R.

    Put a version in the vvp file and have vvp verify compatibility.

    This patch makes the code generator put the compiler version
    information in the vvp output file. It also adds checks in vvp
    to verify that this version is compatible with the run time.
    I am assuming that a base release 0.9.0, etc. will have a
    blank VERSION_TAG. Any change relative to the release will have
    authored November 24, 2008 steveicarus committed November 25, 2008
  2. Larry Doolittle

    Restore pristine builds

    Commit 24827c4 broke
    pristine builds.  Touch up CPPFLAGS so tgt-vvp/vvp.c
    and tgt-vhdl/vhdl.c can find version.h when building
    authored November 24, 2008 steveicarus committed November 24, 2008
  3. Stephen Williams

    Branches are parts of islands.

    Expose the island information for branches to the ivl_target API.
    authored November 24, 2008

Nov 24, 2008

  1. Stephen Williams

    ivl_target.h access branch terminals

    Fill in the functions to add branch terminals, and add code in the
    stub to check that the terminals are present and reasonable.
    authored November 23, 2008
  2. Stephen Williams

    Add functions for targets to scan disciplines.

    The disciplines are, from the perspective of the ivl target, collected
    into the design. Add functions for the target to scan the disciplines
    in the design.
    In the process, also clean up the handlng of design constants.
    authored November 23, 2008
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