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Commits on Dec 11, 2008
  1. Make a copy of the local include directory so that it doesn't get lost.

    caryr authored and steveicarus committed Dec 11, 2008
    Some compilers when optimizing can overwrite the path before it is
    read so make a copy of the local include directory and free it when
    we are done.
  2. Check system() return when getting version information.

    caryr authored and steveicarus committed Dec 11, 2008
    We were not checking the return of the two system calls used
    to get the version information from ivlpp and ivl. This patch
    adds checks and prints an appropriate message if they fail.
Commits on Dec 10, 2008
  1. Treat assignment into a task port exactly like blocking assignment.

    steveicarus committed Dec 10, 2008
    Reuse the code that the blocking assignment uses. This fixes makes
    the task port input assignment work better.
Commits on Dec 9, 2008
  1. Check for too few buf/not port expressions.

    caryr authored and steveicarus committed Dec 8, 2008
    This patch adds code to check that buf and not primitives have
    at least two port expressions. An error message is printed for
    this case.
Commits on Dec 8, 2008
  1. Remove some uneccessary zero-time waits from VHDL outputs

    nickg authored and steveicarus committed Dec 7, 2008
    This patch optimises away straight line sequences like:
    
    wait for 0 ns;
    wait for X ns;
    
    to:
    
    wait for X ns;
    
    This tidies up the output a bit.
    
    It also has the effect of removing all code from initial
    processes where the assignments have been extracted as
    VHDL signal intialisers. (c.f. pr2391337)
  2. Emit useful error message for pr2362211

    nickg authored and steveicarus committed Dec 7, 2008
    This prints out an error message rather than crashing out with
    an assertion failure when a function assigns to a non-local
    variable, which cannot be done in VHDL.
  3. Rework VHDL assignment statement generation

    nickg authored and steveicarus committed Dec 7, 2008
    This changes the assignment statement generator so that
    each VHDL declaration "knows" which type of assignment
    statement can/should be used on (i.e. signals must be
    assigned with <=). This will help us catch cases when
    we try to use, for example, := with signals. This occurs
    in pr2362211 where we try to assign to a signal within
    a function (where only := can be used).
  4. Fix assignment of constant to input

    nickg authored and steveicarus committed Dec 6, 2008
    If a module's input was connected to a nexus that contained
    a constant driver. That constant would be incorrectly generated
    as an assignment to the input *inside* the child module (instead
    of an assignment inside the instantiating module).
Commits on Dec 6, 2008
  1. Remove most of the lingering CVS droppings.

    steveicarus committed Dec 6, 2008
    Remove the #ident and $Log$ strings from all the header files and
    almost all of the C/C++ source files. I think it is better to get
    this done all at once, then to wait for each of the files to be
    touched and edited in unrelated patches.
  2. Allow building with gcc-4.4

    ldoolitt authored and steveicarus committed Dec 3, 2008
    With this small patch, building succeeds with Debian's current gcc-snapshot,
    gcc (Debian 20081130-1) 4.4.0 20081130 (experimental) [trunk revision 142292]
    
    That gcc also warns about the remaining #idents in
      vvp/concat.cc
      vvp/dff.h
    
    The resulting build shows some regressions in the test suite, that
    I am still investigating.  The patch does not break building, or show
    test suite regressions, with gcc-4.3.
Commits on Dec 2, 2008
  1. Fix out of range indexed part selects and negative verinum width calc.

    caryr authored and steveicarus committed Dec 2, 2008
    This patch fixes fully out of range constant indexed part selects
    to just return 'bx. It also adds support for constant undefined
    base values which also just return 'bx.
    
    A bug in the bit width calculation when building an unsized, signed
    negative integer value was also fixed (-3 needs 3 bits not 2, etc.)
  2. Add two missing function definitions.

    caryr authored and steveicarus committed Dec 1, 2008
    This patch adds the function definitions for ivl_expr_branch and
    ivl_expr_nature to the ivl.def file. This is needed to get Cygwin
    and MinGW to compile correctly.
Commits on Nov 30, 2008
  1. Case statements need their expresions probed.

    steveicarus committed Nov 30, 2008
    Probe the widths of the case statement expressions. The expressions
    are self-determined in that context, but the probe is needed to
    setup the expression types.
  2. Add debugging output to VHDL target

    nickg authored and steveicarus committed Nov 29, 2008
    Prints progress when -pdebug=1 specified.
    
    Adds a new debug_msg function to print progress messages.
Commits on Nov 29, 2008
  1. Seperate islands from tran/switch islands

    steveicarus committed Nov 29, 2008
    Tran islands are a kinds of island, so seperate the tran handling
    from the core island concept. This will allow for creating new
    kinds of islands. (Think analog.)
  2. probe expression widths of analog contribution expressions.

    steveicarus committed Nov 29, 2008
    The expressions of a contribution statement are real valued by
    definition, but we need to do the width probing anyhow in order
    to resolve types and the widths of subexpressions.
Commits on Nov 28, 2008
  1. Rework shift and power PExpr nodes for their special needs.

    steveicarus committed Nov 28, 2008
    The power (**) and shift operators are different from other binary
    operators because their expression width calculations rely only on
    their left operand, with their right operand self-determined. Get
    the handling of these operators out of the PEBinary base class to
    prevent confusion.
  2. More self-determined expressions need width probed.

    steveicarus committed Nov 28, 2008
    Find and fix some more expressions that are self-determined, that
    nevertheless need their widths probled.
  3. A power needs to use the signed (real pow) if either argument is signed.

    caryr authored and steveicarus committed Nov 27, 2008
    The power operator is different in that it uses the signed version
    if either of it's arguments are signed. This patch fixes the code
    generator to do this correctly.
  4. Add the procedural signed power function.

    caryr authored and steveicarus committed Nov 27, 2008
    This patch adds the procedural power function %pow/s for signed
    values. This has bit based inputs and outputs, but uses the double
    pow() function to calculate the value.
  5. Fix calculation of verinum==verinum

    steveicarus committed Nov 28, 2008
    This test was way to picky about the widths of the arguments. In real
    tests, the arguments may have different widths. This especially matter
    when comparing unsized values.
  6. Support direct nesting of conditional generate schemes.

    steveicarus committed Nov 28, 2008
    Verilog generate schemes support a special case where conditional
    generate schemes that contain only a nested conditional generate
    scheme do not create a new scope. Instead, it relies on the nested
    generate scheme to generate the scope.
Commits on Nov 26, 2008
  1. During test_width is not the time to assert on no_type

    steveicarus committed Nov 26, 2008
    unary expressions that have problems should not assert in the
    test_width method. Instead, let the error propagate back and be
    handled during expression elaboration. This found a few places
    where expression widths/types weren't probed before elaboration.
  2. Fix part select of width-1 vector

    nickg authored and steveicarus committed Nov 26, 2008
    Signals of width 1 are declared in VHDL as std_logic, as this
    is the usual way to represent them. Unfortunately, we cannot
    distinguish between
    
    reg [0:0] a;
    
    and
    
    reg a;
    
    This patch avoids trying to slice a std_logic so a[0] is equivalent to a.
  3. The iverilog-vpi script depends on the Makefile

    steveicarus committed Nov 26, 2008
    Building the iverilog-vpi script involves editing commands in the
    Makefile, so it makes sense for iverilog-vpi to depend on it.
  4. Update Makefile.in to have current version by default.

    caryr authored and steveicarus committed Nov 25, 2008
    This patch removes the CVS ident information from the Makefile.in
    files it also puts in the current version 0.9.devel for the default
    VERSION definition. This is normally passed down, but a local make
    will use the value from the local Makefile. This will eventually be
    replaced with a file based version to give us just one place to
    reliably modify the version.
  5. Install header files in includedir/iverilog

    steveicarus committed Nov 26, 2008
    Move the header files from includedir/verilog to .../iverilog
    because the verilog name is a little too generic. The iverilog-vpi
    command should handle the changes.
Commits on Nov 25, 2008
  1. Put a version in the vvp file and have vvp verify compatibility.

    caryr authored and steveicarus committed Nov 24, 2008
    This patch makes the code generator put the compiler version
    information in the vvp output file. It also adds checks in vvp
    to verify that this version is compatible with the run time.
    I am assuming that a base release 0.9.0, etc. will have a
    blank VERSION_TAG. Any change relative to the release will have
    a VERSION_TAG.
  2. Restore pristine builds

    ldoolitt authored and steveicarus committed Nov 24, 2008
    Commit 24827c4 broke
    pristine builds.  Touch up CPPFLAGS so tgt-vvp/vvp.c
    and tgt-vhdl/vhdl.c can find version.h when building
    out-of-tree.
  3. Branches are parts of islands.

    steveicarus committed Nov 25, 2008
    Expose the island information for branches to the ivl_target API.
Commits on Nov 24, 2008
  1. ivl_target.h access branch terminals

    steveicarus committed Nov 24, 2008
    Fill in the functions to add branch terminals, and add code in the
    stub to check that the terminals are present and reasonable.
  2. Add functions for targets to scan disciplines.

    steveicarus committed Nov 24, 2008
    The disciplines are, from the perspective of the ivl target, collected
    into the design. Add functions for the target to scan the disciplines
    in the design.
    
    In the process, also clean up the handlng of design constants.