Icarus Verilog bug in processing "1'b1 >= |1'bx"

[cliffordwolf]

The following module should set y to 1'bx. But Icarus Verilog (git b1ef099) sets the output to 1'b1.

module issue_024(y);
  output y;
  assign y = 1'b1 >= |1'bx;
endmodule

[martinwhitaker]

I've pushed a fix for this to the git master branch.