Icarus does undef propagation of const adds incorrectly

[cliffordwolf]

The following module should set both outputs to constant 4'bxxx:

module test(a, y1, y2);
  input [1:0] a;
  output [3:0] y1, y2;
  assign y1 = 4'bxx00 + 2'b00;
  assign y2 = 4'bxx00 + a;
endmodule

But Icarus Verilog (git 5a06602) does only the case involving a variable
correctly. In the constant case it is too smart and outputs 4'bxx00 instead.

[martinwhitaker]

Yes, what the verinum class add/subtract operators do is entirely sensible, but is not what the Verilog LRM specifies. I'm currently working on the verinum arithmetic operators to fix the result width issue, so will fix this issue as well.

[martinwhitaker]

I've pushed a fix for this to the git master branch.