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synthesis translate_{off,on} inside behavioral code #36
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-----BEGIN PGP SIGNED MESSAGE----- The "syntax" is a horrible hack that was superceded by the It looks like what you are doing should work, though, so I'll On 08/08/2014 06:23 AM, Clifford Wolf wrote:
Steve Williams "The woods are lovely, dark and deep. iEYEARECAAYFAlPk3lcACgkQrPt1Sc2b3ik2OgCeJTp0NEwJOOyM1zfobHUMw1vY |
In Yosys they are handled in the lexer as a special form of comment block. Recently I found this in some user code:
Because in yosys the `include is interpreted by the pre processor (which is run before the lexer of course), it is executed in yosys. I'm not sure what "the right thing to do" is in this cases like this (and many others that I could come up with, but this one I actually found). Any suggestions? Funny detail: There is no "timescale_x.v". So the yosys pre-processor created an `error for that. But this was ignored because the lexer was skipping the "translate_off" block. I only noticed this piece of code because a bug in the pre-processor caused an off-by-one error in a line number for an error later in that file. |
-----BEGIN PGP SIGNED MESSAGE----- In Icarus Verilog they are handled in the lexor, but they mark On 08/08/2014 06:22 PM, Clifford Wolf wrote:
iEYEARECAAYFAlPmMTYACgkQrPt1Sc2b3ikAegCfTh9Tr2pvRsmYP5UM5gj9D1eE |
Should be fixed in git master, now. I've fixed it to be handled in the lexor, instead of in the parser, which in retrospect was a bad idea. |
The following module
results in the following syntax error (iverilog git 0f294cb):
I'm not sure if there is any kind of formal definition for the
synthesis translate_off
/synthesis translate_on
comments, but the lattice lm32 CPU is using them inside behavioral code like in my example.The text was updated successfully, but these errors were encountered: