vvp asserts on reduce of one-bit .arith/sub

[cliffordwolf]

The following module builds fine with iverilog (ivl) but triggers an assert in vvp:

module issue_011(a, y);
  input [0:0] a;
  output [0:0] y;
  assign y  = |(-a);
endmodule

The error I get is:

Internal error: Input vector expected width=1, got bit=2'b00, base=0, vwid=2
vvp: vvp_net_sig.cc:896: virtual vvp_net_fil_t::prop_t vvp_wire_vec4::filter_vec4(const vvp_vector4_t&, vvp_vector4_t&, unsigned int, unsigned int): Assertion `bits4_.size() == vwid' failed.

[caryr]

I only looked at this briefly. This looks to be a problem in the vvp code generator. Icarus converts the unary -a to the binary 0-a expression. The problem is in the constant zero code. The compiler is creating a net that represents the 0 to feed to the subtraction function, but this single bit net is being driven by a two bit constant (C4<00>).

[martinwhitaker]

I've pushed a fix for this bug and added a regression test to the test suite. I've named the test br_gh6 to distinguish it from bugs reported via the main bug tracker on SourceForge.