Undef propagation in power operator

[cliffordwolf]

icarus verilog (git d1c9dd5) does not correctly propagate undef thru power operator. For example, y should be 4'bx when a is zero in the following test case, but iverilog returns 4'd1:

module issue_012(a, y);
  input [3:0] a;
  output [3:0] y;
  assign y = 4'd2 ** (4'd1/a);
endmodule

PS: In case anyone is wondering: I find this bugs using VlogHammer (http://www.clifford.at/yosys/vloghammer.html).

[caryr]

There are a couple things here. At the moment the vec2 constructor that takes a vec4 is documented to return is_NaN when given a vector with undefined values. The issue is that the routine that copies the bits does not actually do this. This may be what we want and the constructor documentation needs to be changed and then in the vvp_arith_pow::recv_vec4() code the checks for undefined bits can use common code like what is done for a signed power (e.g. move the signed undefined check code outside of the if statement). Someone needs to spend some time checking which is the correct fix (change the constructor or change the power routine).

[martinwhitaker]

I've just pushed a fix for this bug to the git master branch.

Note to the Icarus developers: I've changed the vvp_vector2_t constructor that takes a vvp_vector4_t value to take an optional second parameter that selects whether NaN or standard Verilog (XZ -> 0) semantics are used, as both behaviours are needed. I've made the default be standard Verilog semantics, otherwise there is a nasty gotcha where

vvp_vector2_t bit2 = bit4;

and

vvp_vector2_t bit2;
bit2 = bit4;

give different behaviour.