Add SV string plusargs test code and update results

ivltests/plus_arg_string.v

@@ -0,0 +1,14 @@
+module main;
+  string img;
+
+  initial begin
+    if (!$value$plusargs("img=%s", img)) begin
+      $display("Specify image file with +img=<image>.");
+      $finish_and_return(1);
+    end
+    $display("Using image: %s", img);
+// HERE: this fails with !==
+    if (img != "test_image.file") $display("FAILED");
+    else $display("PASSED");
+  end
+endmodule // main

regress-sv.list

@@ -154,6 +154,7 @@ parpkg_test		normal,-g2009		ivltests
 parpkg_test2		normal,-g2009		ivltests
 parpkg_test3		normal,-g2009		ivltests
 plus_5			normal,-g2009		ivltests
+plus_arg_string		normal,-g2009,+img=test_image.file	ivltests
 pr3366114		normal,-g2009		ivltests
 pr3366217a		CE,-g2005-sv		ivltests gold=pr3366217a.gold
 pr3366217b		CE,-g2005-sv		ivltests gold=pr3366217b.gold

regress-vlog95.list

@@ -216,6 +216,7 @@ array_string		CE,-g2009,-pallowsigned=1	ivltests
 br932a			CE,-g2009		ivltests
 br932b			CE,-g2009		ivltests
 br_gh4			CE,-g2009		ivltests
+plus_arg_string		CE,-g2009		ivltests
 string_index		CE,-g2005-sv		ivltests
 sv_string1		CE,-g2009		ivltests
 sv_string2		CE,-g2009		ivltests

regression_report-devel.txt

@@ -1805,6 +1805,7 @@ test_mos_strength_reduction: Passed.
                parpkg_test2: Passed.
                parpkg_test3: Passed.
                      plus_5: Passed.
+            plus_arg_string: Passed.
                   pr3366114: Passed.
                  pr3366217a: Passed - CE.
                  pr3366217b: Passed - CE.
@@ -2105,4 +2106,4 @@ test_mos_strength_reduction: Passed.
                 ufuncsynth1: Passed.
 ============================================================================
 Test results:
-  Total=2103, Passed=2098, Failed=5, Not Implemented=0, Expected Fail=0
+  Total=2104, Passed=2099, Failed=5, Not Implemented=0, Expected Fail=0

regression_report-strict.txt

@@ -1743,6 +1743,7 @@ test_mos_strength_reduction: Passed.
             enum_base_range: Passed.
            enum_elem_ranges: Passed.
                   enum_next: Passed.
+                 enum_ports: Passed.
                  enum_test1: Passed.
                  enum_test2: Passed.
                  enum_test3: Passed - CE.
@@ -1801,6 +1802,7 @@ test_mos_strength_reduction: Passed.
                parpkg_test2: Passed.
                parpkg_test3: Passed.
                      plus_5: Passed.
+            plus_arg_string: Passed.
                   pr3366114: Passed.
                  pr3366217a: Passed - CE.
                  pr3366217b: Passed - CE.
@@ -1894,7 +1896,6 @@ test_mos_strength_reduction: Passed.
            sv_darray_args2b: Passed.
             sv_darray_args3: Passed.
             sv_darray_args4: Passed.
-           sv_darray_return: Passed.
                sv_end_label: Passed.
           sv_end_label_fail: Passed - CE.
               sv_end_labels: Passed.
@@ -1966,7 +1967,6 @@ test_mos_strength_reduction: Passed.
                   uint_test: Passed.
               ulongint_test: Passed.
        undef_lval_select_SV: Passed.
-          unp_array_typedef: Passed.
              ushortint_test: Passed.
                   wait_fork: Passed.
                       work7: Passed.
@@ -1988,14 +1988,17 @@ test_mos_strength_reduction: Passed.
               vhdl_and_gate: Passed.
               vhdl_andg_bit: Passed.
          vhdl_andg_stdlogic: Passed.
+            vhdl_case_multi: Passed.
                 vhdl_concat: Passed.
          vhdl_const_package: Passed.
+           vhdl_const_array: Passed.
                  vhdl_expr1: Passed.
              vhdl_fa4_test1: Passed.
              vhdl_fa4_test2: Passed.
              vhdl_fa4_test3: Passed.
              vhdl_fa4_test4: Passed.
                   vhdl_init: Passed.
+        vhdl_labeled_assign: Passed.
       vhdl_nand104_stdlogic: Passed.
             vhdl_nand23_bit: Passed.
              vhdl_nandg_bit: Passed.
@@ -2015,6 +2018,7 @@ test_mos_strength_reduction: Passed.
           vhdl_org_stdlogic: Passed.
             vhdl_rand23_bit: Passed.
                  vhdl_range: Passed.
+            vhdl_range_func: Passed.
                   vhdl_real: Passed.
            vhdl_record_elab: Passed.
                   vhdl_rtoi: Passed.
@@ -2025,6 +2029,7 @@ test_mos_strength_reduction: Passed.
        vhdl_sadd23_stdlogic: Passed.
             vhdl_sdiv23_bit: Passed.
        vhdl_sdiv23_stdlogic: Passed.
+                 vhdl_shift: Passed.
                vhdl_signals: Passed.
             vhdl_smul23_bit: Passed.
        vhdl_smul23_stdlogic: Passed.
@@ -2041,13 +2046,15 @@ test_mos_strength_reduction: Passed.
                  vhdl_test7: Passed.
                  vhdl_test8: Passed.
                  vhdl_test9: Passed.
+            vhdl_to_integer: Passed.
             vhdl_uadd23_bit: Passed.
        vhdl_uadd23_stdlogic: Passed.
             vhdl_udiv23_bit: Passed.
        vhdl_udiv23_stdlogic: Passed.
             vhdl_umul23_bit: Passed.
        vhdl_umul23_stdlogic: Passed.
              vhdl_unbounded: Passed.
+        vhdl_unbounded_func: Passed.
             vhdl_usub23_bit: Passed.
        vhdl_usub23_stdlogic: Passed.
       vhdl_xnor104_stdlogic: Passed.
@@ -2096,4 +2103,4 @@ test_mos_strength_reduction: Passed.
                 ufuncsynth1: Passed.
 ============================================================================
 Test results:
-  Total=2094, Passed=2089, Failed=5, Not Implemented=0, Expected Fail=0
+  Total=2101, Passed=2096, Failed=5, Not Implemented=0, Expected Fail=0

regression_report-vlog95.txt

@@ -137,6 +137,7 @@ Running vlog95 compiler/VVP tests for Icarus Verilog version: 0.10.
                      br932a: Passed - CE.
                      br932b: Passed - CE.
                      br_gh4: Passed - CE.
+            plus_arg_string: Passed - CE.
                string_index: Passed - CE.
                  sv_string1: Passed - CE.
                  sv_string2: Passed - CE.
@@ -2105,4 +2106,4 @@ test_mos_strength_reduction: Passed.
            synth_if_no_else: Passed.
 ============================================================================
 Test results:
-  Total=2103, Passed=2073, Failed=3, Not Implemented=3, Expected Fail=24
+  Total=2104, Passed=2074, Failed=3, Not Implemented=3, Expected Fail=24