Browse files

Cleanup CVS junk, reorganize and add a new README

Remove the .cvsignore files.
Move a number of files into obsolete.
Add a new README.
Fix pr723 for V0.8.
Remove the vcddiff executable for the archive.
Change some files permissions to 0644.
Create the log/, work/ or vpi_log/ directories when needed.
Ignore the appropriate files/directories
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1 parent de496dc commit 3f1fa3df9248e9b493a43e0d8f085d13f9313fd1 @caryr caryr committed with Mar 9, 2009
View
10 .cvsignore
@@ -1,10 +0,0 @@
-simv
-vsim
-dfile
-*.vcd
-*.dump
-*.o
-*.vpi
-regression_report.txt
-vhdl_regression_report.txt
-vhdl
View
26 .gitignore
@@ -0,0 +1,26 @@
+# Lines that start with '#' are comments.
+#
+# This file is for the development branch of Icarus Verilog.
+#
+# The following files will be ignored by git.
+
+# The log and work directories
+log/
+work/
+vpi_log/
+vhdl/
+
+# The normal regression output files.
+
+regression_report.txt
+vhdl_regression_report.txt
+
+# These should be cleaned up, but ignore them as well.
+*.o
+*.vpi
+src/vcddiff
+vsim
+
+# Some tests do not work out of the work directory, so
+# ignore these files that they leave in the home directory.
+dump.vcd
View
333 README
@@ -1,290 +1,101 @@
-Important Notice - this is not the sign-off regression
-list for IVL - that is a separate list that Steve Williams
-currently has. It is a subset of these tests.
+####################
+#
+# Main test script
+#
+####################
-21 April 2007
+There are a group of tests that are meant to exercise the compiler
+and the run time. To run them just type:
-I've added to CVS regression_report-devel.txt that is the
-expected regression test results for the snapshot at the
-time of the checkin. I expect to tag this file with the
-makes of snapshots that are made, so that the expected
-result for a given snapshot can be found.
+./regress
-11/3/2000
+or
-Added format.v, and gold/format.gold and test4.v
+perl vvp_reg.pl
+or if perl is located in /usr/bin
-10/6/2000
+./vvp_reg.pl
-Fixed bug in function3.11D.v - now runs on verilog XL okay.
-Added #1 before big if clause in drive_strength.v
+The output from these tests are displayed on the screen
+and are also placed in the regression_report.txt file.
+The expected output for V0.9.devel is located in the
+regression_report-devel.txt file. The expected output
+for V0.8.? is located in regression_report-v0.8.txt.
-8/13/2000
+The results from individual tests can be found in the
+log directory and gold files, when needed, are in the
+gold directory. The source files can be found in the
+ivltests and contrib directories. The list of tests
+and how they are run is in the regress.list file.
-Went thru older test submissions and found some missing. Added
-stask_parm1.v, assign_mem1, task_inpad, task_omemw2
-6/12/2000
+####################
+#
+# VPI test script
+#
+####################
-Re-release with defparam race condition fixed and mail
-headers removed on param_string.
+To test the VPI interface type:
-6/11/2000
+perl vpi_reg.pl
-Added several tests (most sent from Steve Williams as bug
-reports.) Added CRASH detection for CE class tests.
-Also added Tom Coonan's pic processor to the suite.
-Reworked the sregress.pl script to allow addition of
-diff/gold AND module choices.
+or if perl is located in /usr/bin
-5/08/2000
+./vpi_reg.pl
-Modified the script to support log file comparison against gold files and
-against created files against gold files. Added Steven Tell's new
-fdisplay, and fopen tests. Added div16.v to the contrib list now that
-we can handle $random (this from Tom Coonan)
+All these tests should pass for V0.9.devel. V0.8.? is
+expected to fail for realtime (64 bit time issue) and
+memmon (no full array call backs).
-5/04/2000
+The individual test results are found in the vpi_log
+directory and the gold files are in the vpi_gold
+directory. The source files are in the vpi directory.
+The vpi_regress.list file has the tests to perform.
-Wrote some simple preprocessor tests - didn't find anything -didn't
-think I would.. ;-) ifdef1-ifdef4, else1-else3, include1-include3, and
-define1. Also now using iverilog.
+####################
+#
+# VHDL test script
+#
+####################
-4/30/2000
+This test script require that ghdl be installed in your
+path and is used to test the Verilog to VHDL translation.
-Received 4 tests from Peter Monta via Steve Williams. I'm including
-three of them (reworked two to be self-checking..) The new tests are
-assign_nb1, wireland, and param_concat and function_exp.
+perl vhdl_reg.pl
-Also added an aliasing mechanism so that we can recover with tests
-that barf. Now you simply type ./regress and it'll run ./sregress.pl.
-The difference is that this script sets the coredumpsize to zero via
-csh. This seems to help ALOT. No arguments are passed - if you want
-to use sregress.pl directly - run it under csh with this set!!
+or if perl is located in /usr/bin
-4/29/2000
+./vhdl_reg.pl
-Received scope1 from Steve Williams.
+The expected output for V0.9.devel is located in the
+vhdl_regression_report-devel.txt file. V0.8 does not
+support converting Verilog to VHDL.
-4/28/2000
-Added three tests from Steve Williams and commented out wiresr/wiresl
-since they're crashing the test bench right now at run time.
-Note - We've got some contributed code to compare .vcd results. The
-problem is it's in C and everything in this suite todate has been
-source files or a perl program -still cogitating how to handle it.
+####################
+#
+# MinGW test issues
+#
+####################
-4/27/2000
+Running under MinGW (3.14+ runtime) the following tests are
+expected to fail:
-Several new tests - a couple by myself and a bunch by Steve Williams.
-I added a test for Procedural continuous assignment (pca1) and used
-this to create another test for Wildcard sensitivity ( always @ *)
-from the verilog 2000 spec.
-
-4/16/2000
-
-Added nblkorder to validate case where same variable is assigned
-sequentially in a non-blocking always block. This was suggested from
-a question on a the comp.lang.verilog usenet group. IVL does the
-right thing according to IEEE1364-Draft, page 5-3, section 5.4.1.
-
-This test still needs to be refereed by JML though.
-
-4/10/2000
-
-Added posedge.v and event_list.v sent by S Williams.
-
-4/5/2000
-
-Incorporated 3 tests sent by Steve Williams (dff1, idiv, con_tri) and
-wrote fork3.19A, and fork3.19B.
-
-3/13/2000
-
-Well - been a month - geewhiz. defparam needs main added in
-regress.list and had to change the summary error print message
-to REPORT file in sregress.pl
-
-2/13/2000
-
-Added readmemb and readmemh tests.
-
-2/11/20000
-
-Been awhile! Anyway, got a bug report from George Gallant concerning
-functions with either case or if statements. Thus sdw_function4 and
-sdw_function5 both which fail. Also need to add readmemh and readmemb!
-
-1/23/2000
-
-Added drive_strength.v and pullupdown.v to test suite. Contributed!
-
-01/13/2000
-
-Wrote mult1.v to test reg and wire multiply case, and modulus.v
-to test % operator. Fixed the race in them. Fixed contrib8.5
-in regress.list - it needed to NOT call the top level mod.
-Added xnor_test.v sent to me from Steve Williams(via Guy
-Hutchinson)
-
-01/10/2000
-
-Added inout.v and modparam.v tests. inout does some sneaky
-stuff with modname(a,a); inout a; This is legal to short
-two signals together. modparam passes paramters down from
-a top level module and overides the loever level. Added udp_bufg
-back to list. It doesn't work, but doesn't core dump or hang
-anymore.
-
-01/02/2000
-
-Fixed the error message from fifo.v to get correctly detected.
-(It should say "Failed.") Added gencrc and onehot to the regress.list.
-
-01/01/2000
-
-Added a set of unary operator tests. unary_and, unary_nand,
-unary_or,unary_nor, unary_xor, unary_xnor1, and unary_xnor2.
-There are three elaboration problems in this last bunch. Added
-a scan for "Unable" which seems to qualify elaboration
-errors to the sregress.pl script.
-
-12/27/99
-
-This is a BIG release for one simple fact. The entire suite has
-been tested against Cadence Verilog XL....and we found a bug in
-XL! See time2.v for the failing testcase.
-
-Did some basic maintenance/QA on test suite. Changed sregress.pl
-to use the -l option for XL, as oppossed to redirection. Works
-more reliably on Sun(well - this FIXED a problem with all the
-verilog runs going into backround with the >& syntax?)
-
-Fixed always3.1.9A.v, Fixed always3.1.9B.v. Added tests always3.1.9C,D.v
-Fixed wiremod1.v, syntax error in ptest006-008 in $display. Howcome
-IVL likes these? Removed sdw_template.v. Added "PASSED" printout
-to z1,z2. This should make them compatible with XL.
-Fixed assign3.2D.v syntax error, moved syntax error into assign3.2E.v
-to test for it!
-Fixed contrib8.4.v so that it prints PASSED.
-
-12/11/99
-
-Added contrib directory and fifo.v in same donated by Tom Coonan.
-He's GPL this and other work for inclusion within the test suite!
-THANKS TOM!!!!!
-
-Note that two tests always3.1.11B and udp_bufg are commented
-out because they hang the testsuite currently.
-
-12/1/99
-
-Added qmark6.v contributed by Dan Nelsen. Muxtest.v validates
-X on sel, when inputs are both 1 or 0.
-
-11/12/99
-
-Added several ga_* tests that use a primitive gate vector. The ga_nand.v test
-of this sequence fails. Went thru the ptestxxx.v series and replaced all
-!= or == constructs with !==/===.
-
-11/8/99
-
-Fixed stuff added on 11/6 - it now says PASSED!
-Added wirele.v, wirege.v, wireeq.v tests. These with the
-CVS 11/7/99 cut that I used to test.
-
-11/6/99
-
-Added tests wireadd1.v wiremod1.v wiresl.v wiresr.v wiresub1.v wirexor1.v
-Several of the tests in regress.list had the .v extension so they
-weren't running correctly. That's fixed.
-
-10/14/99
-
-This is mainly a debug release. See below.
-
-lh_varindx added (tests left hand variable index of a vector.)
-Rewrote always3.1.6A-C COMPLETELY. Changed time1.v to use
-always block and #5 d = a; Added time3.v that looks at same
-structure for non-blocking (#5 d <= a).
-
-Added an always3.1.6D.v ( a case test from Steve Williams.)
-
-There was a race condition in the always3.1.6A-C that was
-due in part to the nature of always case (x) ...default #1; whoops!
-
-Removed qmark2.v - it became redundant(besides it was broken sematically)
-
-10/5/99
-
-Changed location of #0 to first item in the initial
-block for always3.1.6A-C.v This also counts as a
-test for proper operation of the semantics for #0
-which is used to defeat what would otherwise be
-a race condition. Researched the operation of #0 in
-Moorby 4th edition. This seems to be kosher (though
-not GOOD programming practice.)
-
-Added several contributed tests by many folks.
-
-Note that the regression_report.txt is the results of
-running with the 9/28 IVL release.
-
-9/27/99
-
-Added a #0 to take care of a race in always3.1.6A-C.
-Added the ability to put an optional main module name as
-a 4th arguement within the regress.list line.
-
-9/20/99
-
-This release collects the tests together along with a
-regression script(sregress.pl) which is a modified
-version of a script contributed by Guy Hutchison.
-(Thanks Guy!!!)
-
-To run the testsuite - ensure that you have the
-appropriate IVL environment variables set - the
-script doesn't check for THAT yet - maybe next
-time;-) You need the appropriate stuff in your
-search path for IVL and set VPI_MODULE_PATH and
-LD_LIBRARY_PATH as necessary. See the IVL docs
-for info.
-
-Now - simply move into the testsuite directory
-and type: ./sregress.pl <cr>
-
-This will run the regression script, and create a
-series of log files in the log directory. The test
-runs are summarized in regression_report.txt. The
-tests run are obtained from regress.list.
-
-9/9/99
-
-Completed thru 3.14F(tasks). So Added from Section
-3.11-3.14. Updated ivl_test.html file. Also have included
-some of the "contributed" tests. Haven't worked them all
-into the test document yet.
-
-9/6/99
-
-Completed all of the always block tests. Added tests
-for sections 3.2-3.10. Reworked the 3.1.5 tests that
-had bugs. Updated the ivl_tests.html file to
-reflect work to date.
-
-Note that runsh doesn't use the "verilog" script yet.
-
-
-8/18/99
-
-New tests added 3.1.5C - 3.1.7B
-
-8/12/99
-
-Initial release to Steve Williams.
+pr1699519 - MinGW has three digit exponents.
+pr1703120 - integer infinity and infinity display
+pr1752823a - missing -0
+pr1752823b - infinity display and missing -0
+swrite - MinGW has three digit exponents
+pr1864115 - %#g of 0.0 gives six decimal digits
+ca_mult - %#g of 0.0 gives six decimal digits
+pr1873372 - MinGW has three digit exponents
+test_va_math - infinity and NaN display, missing -0
+test_vams_math - infinity and NaN display, missing -0
+ca_time - %#g of 0.0 gives six decimal digits
+pr723 - MinGW has some fd problems that need to be investigated.
+All of these issues produce something that humans should recognize
+as correct results (-0 == 0, extra digits, out of order text, etc.).
View
1 errlog/.cvsignore
@@ -1 +0,0 @@
-*.log
View
1 log/.cvsignore
@@ -1 +0,0 @@
-*.log
View
4 log/.log
@@ -1,4 +0,0 @@
-./ivltests/.v: No such file or directory
-No top level modules, and no -s option.
-errors translating Verilog program.
-COMPERR
View
290 obsolete/README
@@ -0,0 +1,290 @@
+Important Notice - this is not the sign-off regression
+list for IVL - that is a separate list that Steve Williams
+currently has. It is a subset of these tests.
+
+21 April 2007
+
+I've added to CVS regression_report-devel.txt that is the
+expected regression test results for the snapshot at the
+time of the checkin. I expect to tag this file with the
+makes of snapshots that are made, so that the expected
+result for a given snapshot can be found.
+
+11/3/2000
+
+Added format.v, and gold/format.gold and test4.v
+
+
+10/6/2000
+
+Fixed bug in function3.11D.v - now runs on verilog XL okay.
+Added #1 before big if clause in drive_strength.v
+
+8/13/2000
+
+Went thru older test submissions and found some missing. Added
+stask_parm1.v, assign_mem1, task_inpad, task_omemw2
+
+6/12/2000
+
+Re-release with defparam race condition fixed and mail
+headers removed on param_string.
+
+6/11/2000
+
+Added several tests (most sent from Steve Williams as bug
+reports.) Added CRASH detection for CE class tests.
+Also added Tom Coonan's pic processor to the suite.
+Reworked the sregress.pl script to allow addition of
+diff/gold AND module choices.
+
+5/08/2000
+
+Modified the script to support log file comparison against gold files and
+against created files against gold files. Added Steven Tell's new
+fdisplay, and fopen tests. Added div16.v to the contrib list now that
+we can handle $random (this from Tom Coonan)
+
+5/04/2000
+
+Wrote some simple preprocessor tests - didn't find anything -didn't
+think I would.. ;-) ifdef1-ifdef4, else1-else3, include1-include3, and
+define1. Also now using iverilog.
+
+
+4/30/2000
+
+Received 4 tests from Peter Monta via Steve Williams. I'm including
+three of them (reworked two to be self-checking..) The new tests are
+assign_nb1, wireland, and param_concat and function_exp.
+
+Also added an aliasing mechanism so that we can recover with tests
+that barf. Now you simply type ./regress and it'll run ./sregress.pl.
+The difference is that this script sets the coredumpsize to zero via
+csh. This seems to help ALOT. No arguments are passed - if you want
+to use sregress.pl directly - run it under csh with this set!!
+
+4/29/2000
+
+Received scope1 from Steve Williams.
+
+4/28/2000
+
+Added three tests from Steve Williams and commented out wiresr/wiresl
+since they're crashing the test bench right now at run time.
+Note - We've got some contributed code to compare .vcd results. The
+problem is it's in C and everything in this suite todate has been
+source files or a perl program -still cogitating how to handle it.
+
+4/27/2000
+
+Several new tests - a couple by myself and a bunch by Steve Williams.
+I added a test for Procedural continuous assignment (pca1) and used
+this to create another test for Wildcard sensitivity ( always @ *)
+from the verilog 2000 spec.
+
+4/16/2000
+
+Added nblkorder to validate case where same variable is assigned
+sequentially in a non-blocking always block. This was suggested from
+a question on a the comp.lang.verilog usenet group. IVL does the
+right thing according to IEEE1364-Draft, page 5-3, section 5.4.1.
+
+This test still needs to be refereed by JML though.
+
+4/10/2000
+
+Added posedge.v and event_list.v sent by S Williams.
+
+4/5/2000
+
+Incorporated 3 tests sent by Steve Williams (dff1, idiv, con_tri) and
+wrote fork3.19A, and fork3.19B.
+
+3/13/2000
+
+Well - been a month - geewhiz. defparam needs main added in
+regress.list and had to change the summary error print message
+to REPORT file in sregress.pl
+
+2/13/2000
+
+Added readmemb and readmemh tests.
+
+2/11/20000
+
+Been awhile! Anyway, got a bug report from George Gallant concerning
+functions with either case or if statements. Thus sdw_function4 and
+sdw_function5 both which fail. Also need to add readmemh and readmemb!
+
+1/23/2000
+
+Added drive_strength.v and pullupdown.v to test suite. Contributed!
+
+01/13/2000
+
+Wrote mult1.v to test reg and wire multiply case, and modulus.v
+to test % operator. Fixed the race in them. Fixed contrib8.5
+in regress.list - it needed to NOT call the top level mod.
+Added xnor_test.v sent to me from Steve Williams(via Guy
+Hutchinson)
+
+01/10/2000
+
+Added inout.v and modparam.v tests. inout does some sneaky
+stuff with modname(a,a); inout a; This is legal to short
+two signals together. modparam passes paramters down from
+a top level module and overides the loever level. Added udp_bufg
+back to list. It doesn't work, but doesn't core dump or hang
+anymore.
+
+01/02/2000
+
+Fixed the error message from fifo.v to get correctly detected.
+(It should say "Failed.") Added gencrc and onehot to the regress.list.
+
+01/01/2000
+
+Added a set of unary operator tests. unary_and, unary_nand,
+unary_or,unary_nor, unary_xor, unary_xnor1, and unary_xnor2.
+There are three elaboration problems in this last bunch. Added
+a scan for "Unable" which seems to qualify elaboration
+errors to the sregress.pl script.
+
+12/27/99
+
+This is a BIG release for one simple fact. The entire suite has
+been tested against Cadence Verilog XL....and we found a bug in
+XL! See time2.v for the failing testcase.
+
+Did some basic maintenance/QA on test suite. Changed sregress.pl
+to use the -l option for XL, as oppossed to redirection. Works
+more reliably on Sun(well - this FIXED a problem with all the
+verilog runs going into backround with the >& syntax?)
+
+Fixed always3.1.9A.v, Fixed always3.1.9B.v. Added tests always3.1.9C,D.v
+Fixed wiremod1.v, syntax error in ptest006-008 in $display. Howcome
+IVL likes these? Removed sdw_template.v. Added "PASSED" printout
+to z1,z2. This should make them compatible with XL.
+Fixed assign3.2D.v syntax error, moved syntax error into assign3.2E.v
+to test for it!
+Fixed contrib8.4.v so that it prints PASSED.
+
+12/11/99
+
+Added contrib directory and fifo.v in same donated by Tom Coonan.
+He's GPL this and other work for inclusion within the test suite!
+THANKS TOM!!!!!
+
+Note that two tests always3.1.11B and udp_bufg are commented
+out because they hang the testsuite currently.
+
+12/1/99
+
+Added qmark6.v contributed by Dan Nelsen. Muxtest.v validates
+X on sel, when inputs are both 1 or 0.
+
+11/12/99
+
+Added several ga_* tests that use a primitive gate vector. The ga_nand.v test
+of this sequence fails. Went thru the ptestxxx.v series and replaced all
+!= or == constructs with !==/===.
+
+11/8/99
+
+Fixed stuff added on 11/6 - it now says PASSED!
+Added wirele.v, wirege.v, wireeq.v tests. These with the
+CVS 11/7/99 cut that I used to test.
+
+11/6/99
+
+Added tests wireadd1.v wiremod1.v wiresl.v wiresr.v wiresub1.v wirexor1.v
+Several of the tests in regress.list had the .v extension so they
+weren't running correctly. That's fixed.
+
+10/14/99
+
+This is mainly a debug release. See below.
+
+lh_varindx added (tests left hand variable index of a vector.)
+Rewrote always3.1.6A-C COMPLETELY. Changed time1.v to use
+always block and #5 d = a; Added time3.v that looks at same
+structure for non-blocking (#5 d <= a).
+
+Added an always3.1.6D.v ( a case test from Steve Williams.)
+
+There was a race condition in the always3.1.6A-C that was
+due in part to the nature of always case (x) ...default #1; whoops!
+
+Removed qmark2.v - it became redundant(besides it was broken sematically)
+
+10/5/99
+
+Changed location of #0 to first item in the initial
+block for always3.1.6A-C.v This also counts as a
+test for proper operation of the semantics for #0
+which is used to defeat what would otherwise be
+a race condition. Researched the operation of #0 in
+Moorby 4th edition. This seems to be kosher (though
+not GOOD programming practice.)
+
+Added several contributed tests by many folks.
+
+Note that the regression_report.txt is the results of
+running with the 9/28 IVL release.
+
+9/27/99
+
+Added a #0 to take care of a race in always3.1.6A-C.
+Added the ability to put an optional main module name as
+a 4th arguement within the regress.list line.
+
+9/20/99
+
+This release collects the tests together along with a
+regression script(sregress.pl) which is a modified
+version of a script contributed by Guy Hutchison.
+(Thanks Guy!!!)
+
+To run the testsuite - ensure that you have the
+appropriate IVL environment variables set - the
+script doesn't check for THAT yet - maybe next
+time;-) You need the appropriate stuff in your
+search path for IVL and set VPI_MODULE_PATH and
+LD_LIBRARY_PATH as necessary. See the IVL docs
+for info.
+
+Now - simply move into the testsuite directory
+and type: ./sregress.pl <cr>
+
+This will run the regression script, and create a
+series of log files in the log directory. The test
+runs are summarized in regression_report.txt. The
+tests run are obtained from regress.list.
+
+9/9/99
+
+Completed thru 3.14F(tasks). So Added from Section
+3.11-3.14. Updated ivl_test.html file. Also have included
+some of the "contributed" tests. Haven't worked them all
+into the test document yet.
+
+9/6/99
+
+Completed all of the always block tests. Added tests
+for sections 3.2-3.10. Reworked the 3.1.5 tests that
+had bugs. Updated the ivl_tests.html file to
+reflect work to date.
+
+Note that runsh doesn't use the "verilog" script yet.
+
+
+8/18/99
+
+New tests added 3.1.5C - 3.1.7B
+
+8/12/99
+
+Initial release to Steve Williams.
+
+
View
0 elist → obsolete/elist
File renamed without changes.
View
0 eregress.pl → obsolete/eregress.pl 100755 → 100644
File renamed without changes.
View
0 sregress.pl → obsolete/sregress.pl 100755 → 100644
File renamed without changes.
View
0 vvptests/COPYING → obsolete/vvptests/COPYING
File renamed without changes.
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0 vvptests/README → obsolete/vvptests/README
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0 vvptests/regress.list → obsolete/vvptests/regress.list
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0 vvptests/vvp.pl → obsolete/vvptests/vvp.pl 100755 → 100644
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0 vvptests/vvpsources/assignx0.vp → obsolete/vvptests/vvpsources/assignx0.vp 100755 → 100644
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0 vvptests/vvpsources/force.vp → obsolete/vvptests/vvpsources/force.vp 100755 → 100644
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0 vvptests/vvpsources/force0.vp → obsolete/vvptests/vvpsources/force0.vp 100755 → 100644
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0 vvptests/vvpsources/force_pca.vp → obsolete/vvptests/vvpsources/force_pca.vp 100755 → 100644
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0 vvptests/vvpsources/hello.vp → obsolete/vvptests/vvpsources/hello.vp 100755 → 100644
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0 vvptests/vvpsources/resolvz.vp → obsolete/vvptests/vvpsources/resolvz.vp
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35 vpi_gold/pr723-v0.8.log
@@ -0,0 +1,35 @@
+Compiling vpi/pr723.c...
+Making pr723.vpi from pr723.o...
+write to FD 2
+Open some files
+open MCD returned 00000002
+open MCD returned 00000004
+open MCD returned 00000008
+open MCD returned 00000010
+open FD ('r') returned 80000003
+open FD ('r') returned 80000004
+open FD ('w') returned 80000005
+open FD ('w') returned 80000006
+open FD ('a') returned 80000007
+open FD ('a') returned 80000008
+MCD 01: stdout
+MCD 02: /dev/null
+MCD 03: /dev/null
+MCD 04: /dev/null
+MCD 05: /dev/null
+FP 00: stdin
+FP 01: stdout
+FP 02: stderr
+FP 03: /dev/null
+FP 04: /dev/null
+FP 05: /dev/null
+FP 06: /dev/null
+FP 07: /dev/null
+FP 08: /dev/null
+write to MCD 1
+write to FD 1
+Close some files
+MCD 01: stdout
+FP 00: stdin
+FP 01: stdout
+FP 02: stderr
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1 vpi_log/.cvsignore
@@ -1 +0,0 @@
-*.log
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5 vpi_reg.pl
@@ -152,6 +152,11 @@ sub execute_regression {
$len = length($tname) if (length($tname) > $len);
}
+ # Make sure we have a log directory.
+ if (! -d 'vpi_log') {
+ mkdir 'vpi_log' or die "Error: unable to create vpi_log directory.\n";
+ }
+
foreach $tname (@testlist) {
next if ($tname eq ""); # Skip test that have been replaced.
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2 vpi_regress.list
@@ -50,7 +50,7 @@ v0.8:scopes normal scopes.c scopes.log -DIVERILOG_V0_8
v0.8:by_name normal by_name.c by_name.log -DIVERILOG_V0_8
v0.8:realcb normal realcb.c realcb.log -DIVERILOG_V0_8
v0.8:pr686 normal pr686.c pr686.log -DIVERILOG_V0_8
-v0.8:pr723 normal pr723.c pr723.log -DIVERILOG_V0_8
+v0.8:pr723 normal pr723.c pr723-v0.8.log -DIVERILOG_V0_8
# V0.8 has some 32 bit time problems so this test fails.
v0.8:realtime normal realtime.c realtime.log -DIVERILOG_V0_8
v0.8:realtime2 normal realtime2.c realtime2.log -DIVERILOG_V0_8
View
8 vvp_reg.pl
@@ -63,6 +63,14 @@ sub execute_regression {
$len = length($tname) if (length($tname) > $len);
}
+ # Make sure we have a log and work directory.
+ if (! -d 'log') {
+ mkdir 'log' or die "Error: unable to create log directory.\n";
+ }
+ if (! -d 'work') {
+ mkdir 'work' or die "Error: unable to create work directory.\n";
+ }
+
foreach $tname (@testlist) {
next if ($tname eq ""); # Skip test that have been replaced.
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1 vvptests/log/.cvsignore
@@ -1 +0,0 @@
-*.log
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11 work/.cvsignore
@@ -1,11 +0,0 @@
-fopen2.out*
-fdisplay2.out
-pr2029336.out
-*.vcd
-*.dump
-temp.txt
-test.txt
-writemem*.dat
-writemem*.txt
-sp2.inv
-BBCDBBCD

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