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Add specify block test for inertial delays.

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commit 4ccd2166792fad20d5f9b3ba82f4aac1350de138 1 parent 56b873a
@caryr caryr authored
Showing with 63 additions and 0 deletions.
  1. +62 −0 ivltests/pr2829776b.v
  2. +1 −0  regress.list
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62 ivltests/pr2829776b.v
@@ -0,0 +1,62 @@
+`timescale 1ns/1ps
+
+module top;
+ reg pass;
+ reg ina, inb;
+ wire out;
+
+ my_or dut(out, ina, inb);
+
+ initial begin
+ pass = 1'b1;
+ ina = 1'b0;
+ inb = 1'b0;
+ #0.399
+ if (out !== 1'bx && out !== 1'bz) begin
+ $display("FAILED: gate had incorrect delay, expected x/z, got %b.", out);
+ pass = 1'b0;
+ end
+ #0.002
+ if (out !== 1'b0) begin
+ $display("FAILED: gate had incorrect delay, expected 0, got %b.", out);
+ pass = 1'b0;
+ end
+
+ // Check inertial delays.
+ ina = 1'b1;
+ #0.399
+ ina = 1'b0;
+ #0.002
+ if (out !== 1'b0) begin
+ $display("FAILED: inertial delay, expected 0, got %b.", out);
+ pass = 1'b0;
+ end
+
+ // Check that this change is relative to the first edge.
+ ina = 1'b1;
+ #0.200;
+ inb = 1'b1;
+ #0.201;
+ if (out !== 1'b1) begin
+ $display("FAILED: double edge delay, expected 1, got %b.", out);
+ pass = 1'b0;
+ #0.200;
+ if (out === 1'b1) begin
+ $display("FAILED: double edge delay was off second edge.");
+ end
+ end
+
+ if (pass) $display("PASSED");
+ end
+endmodule
+
+module my_or(out, ina, inb);
+ output out;
+ input ina, inb;
+
+ or(out, ina, inb);
+
+ specify
+ (ina, inb *> out) = 0.4;
+ endspecify
+endmodule
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1  regress.list
@@ -2194,3 +2194,4 @@ udp_delay_fail CE ivltests
udp_eval_arg normal ivltests
cmdline_parm1 normal,-Pmain.foo=2 ivltests
pr2829776 normal ivltests
+pr2829776b normal,-gspecify ivltests
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